code
stringlengths 1
1.05M
| repo_name
stringlengths 6
83
| path
stringlengths 3
242
| language
stringclasses 222
values | license
stringclasses 20
values | size
int64 1
1.05M
|
|---|---|---|---|---|---|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "pwr_seq_func.h"
#define MAC_AX_PWR_POLL_CNT 20
#define MAC_AX_PWR_POLL_MS 1
u32 pwr_poll_u32(struct mac_ax_adapter *adapter, u32 offset,
u32 mask, u32 pwr_val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt = MAC_AX_PWR_POLL_CNT, val;
while (--cnt) {
val = MAC_REG_R32(offset);
if ((val & mask) == pwr_val)
return MACSUCCESS;
PLTFM_DELAY_MS(MAC_AX_PWR_POLL_MS);
}
PLTFM_MSG_ERR("[ERR] Power sequence polling timeout\n");
PLTFM_MSG_ERR("[ERR] offset: %08X\n", offset);
PLTFM_MSG_ERR("[ERR] read val: %08X, targe val: %08X\n", (val & mask), pwr_val);
return MACPOLLTO;
}
u32 pwr_poll_u16(struct mac_ax_adapter *adapter, u32 offset,
u16 mask, u16 pwr_val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt = MAC_AX_PWR_POLL_CNT;
u16 val;
while (--cnt) {
val = MAC_REG_R16(offset);
if ((val & mask) == pwr_val)
return MACSUCCESS;
PLTFM_DELAY_MS(MAC_AX_PWR_POLL_MS);
}
PLTFM_MSG_ERR("[ERR] Power sequence polling timeout\n");
PLTFM_MSG_ERR("[ERR] offset: %08X\n", offset);
PLTFM_MSG_ERR("[ERR] read val: %04X, targe val: %04X\n", (val & mask), pwr_val);
return MACPOLLTO;
}
u32 pwr_poll_u8(struct mac_ax_adapter *adapter, u32 offset,
u8 mask, u8 pwr_val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt = MAC_AX_PWR_POLL_CNT;
u8 val;
while (--cnt) {
val = MAC_REG_R8(offset);
if ((val & mask) == pwr_val)
return MACSUCCESS;
PLTFM_DELAY_MS(MAC_AX_PWR_POLL_MS);
}
PLTFM_MSG_ERR("[ERR] Power sequence polling timeout\n");
PLTFM_MSG_ERR("[ERR] offset: %08X\n", offset);
PLTFM_MSG_ERR("[ERR] read val: %02X, targe val: %02X\n", (val & mask), pwr_val);
return MACPOLLTO;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/pwr_seq_func.c
|
C
|
agpl-3.0
| 2,382
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PWR_SEQ_FUNC_H_
#define _MAC_AX_PWR_SEQ_FUNC_H_
#include "../mac_def.h"
u32 pwr_poll_u32(struct mac_ax_adapter *adapter, u32 offset,
u32 mask, u32 pwr_val);
u32 pwr_poll_u16(struct mac_ax_adapter *adapter, u32 offset,
u16 mask, u16 pwr_val);
u32 pwr_poll_u8(struct mac_ax_adapter *adapter, u32 offset,
u8 mask, u8 pwr_val);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/pwr_seq_func.h
|
C
|
agpl-3.0
| 1,042
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "role.h"
#define MAC_AX_ACTUAL_WMM_BAND BIT(1)
#define MAC_AX_ACTUAL_WMM_DRV_WMM BIT(0)
static inline void __role_queue_head_init(struct mac_ax_adapter *adapter,
struct mac_role_tbl_head *list)
{
PLTFM_MUTEX_LOCK(&list->lock);
list->prev = (struct mac_role_tbl *)list;
list->next = (struct mac_role_tbl *)list;
list->qlen = 0;
PLTFM_MUTEX_UNLOCK(&list->lock);
}
static inline void __role_insert(struct mac_ax_adapter *adapter,
struct mac_role_tbl *new_role,
struct mac_role_tbl *prev,
struct mac_role_tbl *next,
struct mac_role_tbl_head *list)
{
PLTFM_MUTEX_LOCK(&list->lock);
new_role->next = next;
new_role->prev = prev;
next->prev = new_role;
prev->next = new_role;
list->qlen++;
PLTFM_MUTEX_UNLOCK(&list->lock);
}
static inline void __role_queue_before(struct mac_ax_adapter *adapter,
struct mac_role_tbl_head *list,
struct mac_role_tbl *next,
struct mac_role_tbl *new_role)
{
__role_insert(adapter, new_role, next->prev, next, list);
}
static inline void __role_unlink(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role,
struct mac_role_tbl_head *list)
{
struct mac_role_tbl *next, *prev;
PLTFM_MUTEX_LOCK(&list->lock);
list->qlen--;
next = role->next;
prev = role->prev;
role->prev = NULL;
role->next = NULL;
next->prev = prev;
prev->next = next;
PLTFM_MUTEX_UNLOCK(&list->lock);
}
static inline struct mac_role_tbl *__role_peek(struct mac_role_tbl_head *list)
{
struct mac_role_tbl *role = list->next;
if (role == (struct mac_role_tbl *)list)
role = NULL;
return role;
}
static struct mac_role_tbl *role_alloc(struct mac_ax_adapter *adapter)
{
struct mac_role_tbl *role;
role = (struct mac_role_tbl *)PLTFM_MALLOC(sizeof(struct mac_role_tbl));
if (!role)
return NULL;
role->macid = 0;
role->wmm = 0;
return role;
}
static inline u32 role_queue_len(struct mac_role_tbl_head *list)
{
return list->qlen;
}
static inline void role_queue_head_init(struct mac_ax_adapter *adapter,
struct mac_role_tbl_head *list)
{
PLTFM_MUTEX_INIT(&list->lock);
__role_queue_head_init(adapter, list);
}
static inline void role_enqueue(struct mac_ax_adapter *adapter,
struct mac_role_tbl_head *list,
struct mac_role_tbl *new_role)
{
__role_queue_before(adapter,
list, (struct mac_role_tbl *)list, new_role);
}
static inline struct mac_role_tbl *role_dequeue(struct mac_ax_adapter *adapter,
struct mac_role_tbl_head *list)
{
struct mac_role_tbl *role = __role_peek(list);
if (role)
__role_unlink(adapter, role, list);
return role;
}
static struct mac_role_tbl *role_get(struct mac_ax_adapter *adapter)
{
struct mac_role_tbl *role;
struct mac_role_tbl_head *role_pool;
if (adapter->role_tbl)
role_pool = adapter->role_tbl->role_tbl_pool;
else
return NULL;
if (!role_pool->qlen)
role = NULL;
else
role = role_dequeue(adapter, role_pool);
return role;
}
static void role_return(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role)
{
struct mac_role_tbl_head *role_head = adapter->role_tbl;
struct mac_role_tbl_head *role_pool = NULL;
if (role_head)
role_pool = adapter->role_tbl->role_tbl_pool;
else
return;
__role_unlink(adapter, role, role_head);
role_enqueue(adapter, role_pool, role);
}
static u32 role_free(struct mac_ax_adapter *adapter)
{
struct mac_role_tbl *role;
struct mac_role_tbl_head *role_head;
struct mac_role_tbl_head *role_pool = NULL;
u32 ret = MACSUCCESS;
role_head = adapter->role_tbl;
if (role_head) {
role_pool = role_head->role_tbl_pool;
while (role_queue_len(role_head) > 0) {
role = role_dequeue(adapter, role_head);
if (role) {
PLTFM_FREE(role, sizeof(struct mac_role_tbl));
} else {
ret = MACMEMRO;
break;
}
}
PLTFM_MUTEX_DEINIT(&role_head->lock);
}
if (role_pool) {
while (role_queue_len(role_pool) > 0) {
role = role_dequeue(adapter, role_pool);
if (role) {
PLTFM_FREE(role, sizeof(struct mac_role_tbl));
} else {
ret = MACMEMRO;
break;
}
}
PLTFM_MUTEX_DEINIT(&role_pool->lock);
}
return ret;
}
u32 role_info_valid(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
enum mac_ax_role_opmode op)
{
// Check info is NULL or not
if (!info) {
PLTFM_MSG_ERR("role info is null\n");
return MACNPTR;
}
if (op == ADD) {
// check add role opmode
if (info->opmode != MAC_AX_ROLE_DISCONN) {
PLTFM_MSG_ERR("add_role, opmode should equals to:\n");
PLTFM_MSG_ERR("MAC_AX_ROLE_DISCONN\n");
return MACFUNCINPUT;
}
// check add role updmode
if (info->upd_mode != MAC_AX_ROLE_CREATE) {
PLTFM_MSG_ERR("add_role, updmode should equals to:\n");
PLTFM_MSG_ERR("MAC_AX_ROLE_CREATE\n");
return MACFUNCINPUT;
}
// Check macid exist or not
if (mac_role_srch(adapter, info->macid)) {
PLTFM_MSG_ERR("existing macid: %d\n", info->macid);
return MACSAMACID;
}
} else if (op == CHG) {
if (info->upd_mode == MAC_AX_ROLE_CREATE) {
PLTFM_MSG_ERR("change_role, updmode should not:\n");
PLTFM_MSG_ERR("equals to MAC_AX_ROLE_CREATE\n");
return MACFUNCINPUT;
}
if (!mac_role_srch(adapter, info->macid)) {
PLTFM_MSG_ERR("macid not exist: %d\n", info->macid);
return MACNOITEM;
}
}
// If net_type is IFRA, self_role should only be CLIENT
if (info->net_type == MAC_AX_NET_TYPE_INFRA &&
(info->self_role == MAC_AX_SELF_ROLE_AP ||
info->self_role == MAC_AX_SELF_ROLE_AP_CLIENT)) {
PLTFM_MSG_ERR("net_type is INFRA, self_role can only be:\n");
PLTFM_MSG_ERR("CLIENT\n");
return MACFUNCINPUT;
}
// If net_type is AP, self_role should be AP or AP_CLIENT
if (info->net_type == MAC_AX_NET_TYPE_AP &&
info->self_role == MAC_AX_SELF_ROLE_CLIENT) {
PLTFM_MSG_ERR("net_type is AP, self_role should be AP:\n");
PLTFM_MSG_ERR("or AP_CLIENT\n");
return MACFUNCINPUT;
}
// If self_role is AP, the SMA and TMA should equals to BSSID
if (info->self_role == MAC_AX_SELF_ROLE_AP &&
info->net_type == MAC_AX_NET_TYPE_AP) {
if (PLTFM_MEMCMP(info->self_mac, info->bssid, 6) ||
PLTFM_MEMCMP(info->target_mac, info->bssid, 6)) {
PLTFM_MSG_ERR("self_role is AP, the SMA and TMA:\n");
PLTFM_MSG_ERR("should equal to BSSID\n");
return MACFUNCINPUT;
}
}
// If is_mulitcast_entry = 1, group bit should equals to 1
if (!(info->is_mul_ent ^
((info->net_type != MAC_AX_NET_TYPE_AP &&
((info->self_mac[0] & BIT0) == 0)) ||
(info->net_type == MAC_AX_NET_TYPE_AP &&
((info->bssid[0] & BIT0) == 0))))) {
PLTFM_MSG_ERR("is_mul_ent = 1, group bit should = 1\n");
return MACFUNCINPUT;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (info->wmm >= 2) {
PLTFM_MSG_ERR("invalid wmm %d\n", info->wmm);
return MACFUNCINPUT;
}
if (info->band == MAC_AX_BAND_1) {
PLTFM_MSG_ERR("invalid band %d\n", info->band);
return MACFUNCINPUT;
}
}
if (info->band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("invalid band %d\n", info->band);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
u32 role_tbl_init(struct mac_ax_adapter *adapter)
{
struct mac_role_tbl *role = NULL;
struct mac_role_tbl_head *role_head;
struct mac_role_tbl_head *role_pool;
u16 a_idx;
u32 ret = 0;
adapter->role_tbl = NULL;
adapter->role_tbl = (struct mac_role_tbl_head *)
PLTFM_MALLOC(sizeof(struct mac_role_tbl_head));
if (!adapter->role_tbl) {
PLTFM_MSG_ERR("%s memory alloc failed\n", __func__);
return MACBUFALLOC;
}
adapter->role_tbl->role_tbl_pool = NULL;
adapter->role_tbl->role_tbl_pool = (struct mac_role_tbl_head *)
PLTFM_MALLOC(sizeof(struct mac_role_tbl_head));
if (!adapter->role_tbl->role_tbl_pool) {
PLTFM_MSG_ERR("%s memory alloc failed\n", __func__);
return MACBUFALLOC;
}
role_head = adapter->role_tbl;
role_pool = adapter->role_tbl->role_tbl_pool;
role_queue_head_init(adapter, role_head);
role_queue_head_init(adapter, role_pool);
for (a_idx = 0; a_idx < adapter->hw_info->macid_num; a_idx++) {
role = role_alloc(adapter);
if (role) {
role_enqueue(adapter, role_pool, role);
} else {
PLTFM_MSG_ERR("%s memory alloc failed\n", __func__);
ret = MACBUFALLOC;
break;
}
}
if (a_idx < adapter->hw_info->macid_num)
role_tbl_exit(adapter);
else
ret = MACSUCCESS;
return ret;
}
u32 role_tbl_exit(struct mac_ax_adapter *adapter)
{
u32 ret = MACSUCCESS;
ret = role_free(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s memory free failed\n", __func__);
if (adapter->role_tbl) {
if (adapter->role_tbl->role_tbl_pool) {
PLTFM_FREE(adapter->role_tbl->role_tbl_pool,
sizeof(struct mac_role_tbl_head));
adapter->role_tbl->role_tbl_pool = NULL;
}
PLTFM_FREE(adapter->role_tbl,
sizeof(struct mac_role_tbl_head));
adapter->role_tbl = NULL;
}
return ret;
}
u32 role_info_init(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
u8 i;
// address cam info
info->a_info.len = get_addr_cam_size(adapter);
info->a_info.offset = 0;
info->a_info.mask_sel = info->mask_sel;
info->a_info.addr_mask = info->addr_mask;
info->a_info.hit_rule = info->hit_rule;
info->a_info.bcn_hit_cond = info->bcn_hit_cond;
info->a_info.is_mul_ent = info->is_mul_ent;
info->a_info.port_int = info->port;
info->a_info.tsf_sync = info->tsf_sync;
info->a_info.lsig_txop = info->lsig_txop;
info->a_info.tgt_ind = info->tgt_ind;
info->a_info.frm_tgt_ind = info->frm_tgt_ind;
info->a_info.wol_pattern = info->wol_pattern;
info->a_info.wol_uc = info->wol_uc;
info->a_info.wol_magic = info->wol_magic;
info->a_info.bb_sel = info->band;
info->a_info.tf_trs = info->trigger;
info->a_info.aid12 = info->aid & 0xfff;
info->a_info.macid = info->macid;
info->a_info.wapi = info->wapi;
info->a_info.sec_ent_mode = info->sec_ent_mode;
info->a_info.net_type = info->net_type;
// bssid cam info
info->b_info.len = BSSID_CAM_ENT_SIZE;
info->b_info.offset = 0;
info->b_info.valid = 1;
info->b_info.bss_color = info->bss_color;
info->b_info.bb_sel = info->band;
for (i = 0; i < 6; i++) {
info->a_info.sma[i] = info->self_mac[i];
info->a_info.tma[i] = info->target_mac[i];
info->b_info.bssid[i] = info->bssid[i];
}
return MACSUCCESS;
}
u32 sec_info_init(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
u8 i;
info->a_info.sec_ent_valid = 0;
for (i = 0; i < 7; i++) {
info->a_info.sec_ent_keyid[i] = 0;
info->a_info.sec_ent[i] = 0;
}
return MACSUCCESS;
}
u32 sec_info_deinit(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct mac_role_tbl *role)
{
u32 i, ret;
struct sec_cam_table_t *sec_cam_table = adapter->hw_info->sec_cam_table;
if (!sec_cam_table)
return MACSUCCESS;
ret = disconnect_flush_key(adapter, role);
if (ret != MACSUCCESS)
return ret;
/* deinit info */
info->a_info.sec_ent_mode = 0;
info->a_info.sec_ent_valid = 0;
for (i = 0; i < 7; i++) {
info->a_info.sec_ent_keyid[i] = 0;
info->a_info.sec_ent[i] = 0;
}
/* deinit role */
role->info.a_info.sec_ent_mode = 0;
role->info.a_info.sec_ent_valid = 0;
for (i = 0; i < 7; i++) {
role->info.a_info.sec_ent_keyid[i] = 0;
role->info.a_info.sec_ent[i] = 0;
}
return MACSUCCESS;
}
u32 role_init(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role,
struct mac_ax_role_info *info)
{
struct mac_ax_macid_pause_cfg pause;
u32 ret;
role_info_init(adapter, info);
pause.macid = info->macid;
pause.pause = 0;
ret = set_macid_pause(adapter, &pause);
if (ret != MACSUCCESS)
return ret;
/* The definition of wmm is different between MAC & drivers
* MAC HW use wmm 0~3 to indicate
* phy0-wmm0, phy0-wmm1, phy1-wmm0, phy1-wmm1 correspondingly.
* Drivers use wmm 0/1 & band 0/1
*/
role->macid = info->macid;
role->wmm = (info->band ? MAC_AX_ACTUAL_WMM_BAND : 0) |
(info->wmm ? MAC_AX_ACTUAL_WMM_DRV_WMM : 0);
role->info = *info;
return MACSUCCESS;
}
u32 set_role_bss_clr(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 bss_clr = 0;
switch (info->port) {
case MAC_AX_PORT_0:
bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1);
bss_clr = SET_CLR_WORD(bss_clr, info->bss_color,
B_AX_BSS_COLOB_AX_PORT_0);
MAC_REG_W32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1, bss_clr);
break;
case MAC_AX_PORT_1:
bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1);
bss_clr = SET_CLR_WORD(bss_clr, info->bss_color,
B_AX_BSS_COLOB_AX_PORT_1);
MAC_REG_W32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1, bss_clr);
break;
case MAC_AX_PORT_2:
bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1);
bss_clr = SET_CLR_WORD(bss_clr, info->bss_color,
B_AX_BSS_COLOB_AX_PORT_2);
MAC_REG_W32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1, bss_clr);
break;
case MAC_AX_PORT_3:
bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1);
bss_clr = SET_CLR_WORD(bss_clr, info->bss_color,
B_AX_BSS_COLOB_AX_PORT_3);
MAC_REG_W32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_0 :
R_AX_PTCL_BSS_COLOR_0_C1, bss_clr);
break;
case MAC_AX_PORT_4:
bss_clr = MAC_REG_R32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_1 :
R_AX_PTCL_BSS_COLOR_1_C1);
bss_clr = SET_CLR_WORD(bss_clr, info->bss_color,
B_AX_BSS_COLOB_AX_PORT_4);
MAC_REG_W32((info->band == MAC_AX_BAND_0) ?
R_AX_PTCL_BSS_COLOR_1 :
R_AX_PTCL_BSS_COLOR_1_C1, bss_clr);
break;
default:
break;
}
return 0;
}
u32 mac_add_role(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info)
{
struct mac_role_tbl *role = NULL;
struct mac_role_tbl_head *list_head = adapter->role_tbl;
u32 ret = MACSUCCESS;
u32 cmac_en;
cmac_en = check_mac_en(adapter, info->band, MAC_AX_CMAC_SEL);
if (cmac_en != MACSUCCESS)
PLTFM_MSG_WARN("%s CMAC%d not enable\n", __func__, info->band);
role = role_get(adapter);
if (!role) {
PLTFM_MSG_ERR("role get failed\n");
return MACBUFALLOC;
}
ret = role_info_valid(adapter, info, ADD);
if (ret != MACSUCCESS)
goto role_add_fail;
info->a_info.valid = 1;
if (role_queue_len(list_head) > adapter->hw_info->macid_num) {
PLTFM_MSG_ERR("role list full\n");
ret = MACMACIDFL;
goto role_add_fail;
}
if (sec_info_init(adapter, info)) {
PLTFM_MSG_ERR("sec info change failed\n");
return MACROLEINITFL;
}
if (role_init(adapter, role, info)) {
PLTFM_MSG_ERR("role init failed\n");
ret = MACROLEINITFL;
goto role_add_fail;
}
ret = mac_fw_role_maintain(adapter, info);
if (ret != MACSUCCESS) {
if (ret == MACFWNONRDY) {
PLTFM_MSG_WARN("skip fw role maintain\n");
} else {
PLTFM_MSG_ERR("mac_fw_role_maintain failed:%d\n", ret);
goto role_add_fail;
}
}
if (info->self_role == MAC_AX_SELF_ROLE_AP) {
ret = mac_h2c_join_info(adapter, info);
if (ret != MACSUCCESS) {
if (ret == MACFWNONRDY) {
PLTFM_MSG_WARN("skip join info\n");
} else {
PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret);
return ret;
}
}
}
ret = mac_upd_addr_cam(adapter, &role->info, ADD);
if (ret == MACADDRCAMFL) {
PLTFM_MSG_ERR("ADDRESS CAM full\n");
ret = MACADDRCAMFL;
goto role_add_fail;
} else if (ret == MACBSSIDCAMFL) {
PLTFM_MSG_ERR("BSSID CAM full\n");
ret = MACBSSIDCAMFL;
goto role_add_fail;
}
role_enqueue(adapter, list_head, role);
if (cmac_en)
set_role_bss_clr(adapter, info);
return MACSUCCESS;
role_add_fail:
role_enqueue(adapter, list_head->role_tbl_pool, role);
return ret;
}
u32 mac_change_role(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
struct mac_role_tbl *role;
u32 ret;
u32 cmac_en;
cmac_en = check_mac_en(adapter, info->band, MAC_AX_CMAC_SEL);
if (cmac_en != MACSUCCESS)
PLTFM_MSG_WARN("%s CMAC%d not enable\n", __func__, info->band);
ret = role_info_valid(adapter, info, CHG);
if (ret != MACSUCCESS)
return ret;
role = mac_role_srch(adapter, info->macid);
if (!role) {
PLTFM_MSG_ERR("role search failed\n");
return MACNOITEM;
}
info->a_info = role->info.a_info;
if (role_info_init(adapter, info)) {
PLTFM_MSG_ERR("role change failed\n");
return MACROLEINITFL;
}
role->macid = info->macid;
role->wmm = (info->band ? MAC_AX_ACTUAL_WMM_BAND : 0) |
(info->wmm ? MAC_AX_ACTUAL_WMM_DRV_WMM : 0);
role->info = *info;
if (info->upd_mode == MAC_AX_ROLE_TYPE_CHANGE ||
info->upd_mode == MAC_AX_ROLE_REMOVE) {
ret = mac_fw_role_maintain(adapter, info);
if (ret != MACSUCCESS) {
if (ret == MACFWNONRDY) {
PLTFM_MSG_WARN("skip fw role maintain\n");
} else {
PLTFM_MSG_ERR("mac_fw_role_maintain :%d\n",
ret);
return ret;
}
}
if (info->upd_mode == MAC_AX_ROLE_TYPE_CHANGE &&
info->self_role == MAC_AX_SELF_ROLE_AP) {
ret = mac_h2c_join_info(adapter, info);
if (ret != MACSUCCESS) {
if (ret == MACFWNONRDY) {
PLTFM_MSG_WARN("skip join info\n");
} else {
PLTFM_MSG_ERR("mac_h2c_join_info: %d\n",
ret);
return ret;
}
}
}
} else if (info->upd_mode == MAC_AX_ROLE_CON_DISCONN) {
if (info->opmode == MAC_AX_ROLE_DISCONN) {
ret = sec_info_deinit(adapter, info, role);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("sec info change failed\n");
return ret;
}
}
ret = mac_h2c_join_info(adapter, info);
if (ret != MACSUCCESS) {
if (ret == MACFWNONRDY) {
PLTFM_MSG_WARN("skip join info\n");
} else {
PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret);
return ret;
}
}
} else if (info->upd_mode == MAC_AX_ROLE_INFO_CHANGE) {
ret = mac_h2c_join_info(adapter, info);
if (ret != MACSUCCESS) {
if (ret == MACFWNONRDY) {
PLTFM_MSG_WARN("skip join info\n");
} else {
PLTFM_MSG_ERR("mac_h2c_join_info: %d\n", ret);
return ret;
}
}
} else {
PLTFM_MSG_ERR("role info upd_mode invalid\n");
return ret;
}
ret = mac_upd_addr_cam(adapter, &role->info, CHG);
if (ret == MACBSSIDCAMFL) {
PLTFM_MSG_ERR("BSSID CAM full\n");
return MACBSSIDCAMFL;
}
if (cmac_en)
set_role_bss_clr(adapter, info);
return ret;
}
u32 mac_remove_role(struct mac_ax_adapter *adapter, u8 macid)
{
struct mac_role_tbl *role;
u32 ret;
role = mac_role_srch(adapter, macid);
if (!role) {
PLTFM_MSG_ERR("no role for macid %d\n", macid);
return MACNOROLE;
}
role->info.a_info.valid = 0;
role->info.upd_mode = MAC_AX_ROLE_REMOVE;
role->info.opmode = MAC_AX_ROLE_DISCONN;
if (!mac_role_srch_by_bssid(adapter, role->info.a_info.bssid_cam_idx))
role->info.b_info.valid = 0;
ret = mac_change_role(adapter, &role->info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: %d\n", __func__, ret);
return ret;
}
role_return(adapter, role);
return MACSUCCESS;
}
static u32 mac_remove_role_soft(struct mac_ax_adapter *adapter, u8 macid)
{
/* This function should be called only before poweroff,
* because it will unlink the role without update any info to FW
*/
struct mac_role_tbl *role;
role = mac_role_srch(adapter, macid);
if (!role) {
PLTFM_MSG_ERR("no role for macid %d\n", macid);
return MACNOROLE;
}
role_return(adapter, role);
return MACSUCCESS;
}
u32 mac_remove_role_by_band(struct mac_ax_adapter *adapter, u8 band, u8 sw)
{
struct mac_role_tbl *role, *curr_role;
struct mac_role_tbl_head *list_head = adapter->role_tbl;
u32 ret = MACSUCCESS;
u32 (*_rm_role)(struct mac_ax_adapter *adapter, u8 macid);
if (sw)
_rm_role = mac_remove_role_soft;
else
_rm_role = mac_remove_role;
role = list_head->next;
while (role->next != list_head->next) {
curr_role = role;
role = role->next;
if (band == curr_role->info.band) {
ret = _rm_role(adapter, curr_role->macid);
if (ret && ret != MACNOROLE)
return ret;
}
}
return MACSUCCESS;
}
struct mac_role_tbl *mac_role_srch(struct mac_ax_adapter *adapter, u8 macid)
{
struct mac_role_tbl *role;
struct mac_role_tbl_head *list_head = adapter->role_tbl;
if (!list_head)
return NULL;
role = list_head->next;
for (; role->next != list_head->next; role = role->next) {
if (macid == role->macid)
return role;
}
return NULL;
}
struct mac_role_tbl *mac_role_srch_by_addr_cam(struct mac_ax_adapter *adapter,
u16 addr_cam_idx)
{
struct mac_role_tbl *role;
struct mac_role_tbl_head *list_head = adapter->role_tbl;
if (!list_head)
return NULL;
role = list_head->next;
for (; role->next != list_head->next; role = role->next) {
if (addr_cam_idx == role->info.a_info.addr_cam_idx &&
role->info.a_info.valid)
return role;
}
return NULL;
}
struct mac_role_tbl *mac_role_srch_by_bssid(struct mac_ax_adapter *adapter,
u8 bssid_cam_idx)
{
struct mac_role_tbl *role;
struct mac_role_tbl_head *list_head = adapter->role_tbl;
if (!list_head)
return NULL;
role = list_head->next;
for (; role->next != list_head->next; role = role->next) {
if (bssid_cam_idx == role->info.b_info.bssid_cam_idx &&
role->info.a_info.valid)
return role;
}
return NULL;
}
u32 mac_get_macaddr(struct mac_ax_adapter *adapter,
struct mac_ax_macaddr *macaddr,
u8 role_idx)
{
struct mac_role_tbl *role;
struct mac_role_tbl_head *list_head = adapter->role_tbl;
struct mac_ax_macaddr *macaddr_list;
u8 i;
u8 m_list_idx;
u32 ret;
if (role_idx >= adapter->hw_info->macid_num) {
PLTFM_MSG_ERR("role_idx: %d\n", role_idx);
return MACFUNCINPUT;
}
if (!macaddr) {
PLTFM_MSG_ERR("mac_ax_macaddr is NULL\n");
return MACFUNCINPUT;
}
macaddr_list = (struct mac_ax_macaddr *)
PLTFM_MALLOC(sizeof(struct mac_ax_macaddr) *
adapter->hw_info->macid_num);
role = list_head->next;
for (m_list_idx = 0; role->next != list_head->next; role = role->next) {
if (!role->info.a_info.valid)
continue;
for (i = 0; i < m_list_idx; i++) {
if (!PLTFM_MEMCMP(macaddr_list + i,
role->info.a_info.sma,
sizeof(struct mac_ax_macaddr))) {
break;
}
}
if (i < m_list_idx)
continue;
PLTFM_MEMCPY(macaddr_list + m_list_idx,
role->info.a_info.sma,
sizeof(struct mac_ax_macaddr));
if (m_list_idx == role_idx) {
PLTFM_MEMCPY(macaddr,
role->info.a_info.sma,
sizeof(struct mac_ax_macaddr));
ret = MACSUCCESS;
goto fin;
}
m_list_idx++;
}
ret = MACNOITEM;
fin:
PLTFM_FREE(macaddr_list, sizeof(struct mac_ax_macaddr) *
adapter->hw_info->macid_num);
return ret;
}
u32 mac_set_slot_time(struct mac_ax_adapter *adapter, enum mac_ax_slot_time st)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
switch (st) {
case MAC_AX_SLOT_TIME_BAND0_9US:
ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG,
B_AX_SLOT_TIME_MSK <<
B_AX_SLOT_TIME_SH, 9, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, R_AX_SLOTTIME_CFG, ret);
return ret;
}
break;
case MAC_AX_SLOT_TIME_BAND0_20US:
ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG,
B_AX_SLOT_TIME_MSK <<
B_AX_SLOT_TIME_SH, 20, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, R_AX_SLOTTIME_CFG, ret);
return ret;
}
break;
case MAC_AX_SLOT_TIME_BAND1_9US:
ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG_C1,
B_AX_SLOT_TIME_MSK <<
B_AX_SLOT_TIME_SH, 9, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n", __func__,
R_AX_SLOTTIME_CFG_C1, ret);
return ret;
}
break;
case MAC_AX_SLOT_TIME_BAND1_20US:
ret = MAC_REG_W_OFLD(R_AX_SLOTTIME_CFG_C1,
B_AX_SLOT_TIME_MSK <<
B_AX_SLOT_TIME_SH, 20, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n", __func__,
R_AX_SLOTTIME_CFG_C1, ret);
return ret;
}
break;
}
return ret;
}
#endif
switch (st) {
case MAC_AX_SLOT_TIME_BAND0_9US:
MAC_REG_W8(R_AX_SLOTTIME_CFG, 9);
break;
case MAC_AX_SLOT_TIME_BAND0_20US:
MAC_REG_W8(R_AX_SLOTTIME_CFG, 20);
break;
case MAC_AX_SLOT_TIME_BAND1_9US:
MAC_REG_W8(R_AX_SLOTTIME_CFG_C1, 9);
break;
case MAC_AX_SLOT_TIME_BAND1_20US:
MAC_REG_W8(R_AX_SLOTTIME_CFG_C1, 20);
break;
default:
ret = MACFUNCINPUT;
break;
}
return ret;
}
static u32 mac_h2c_join_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_joininfo *fwcmd_tbl;
struct mac_ax_sta_init_info sta;
u32 ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_WARN("%s fw not ready\n", __func__);
return MACFWNONRDY;
}
// sta info
sta.macid = info->macid;
sta.opmode = info->opmode;
sta.band = info->band;
sta.wmm = (info->band ? MAC_AX_ACTUAL_WMM_BAND : 0) |
(info->wmm ? MAC_AX_ACTUAL_WMM_DRV_WMM : 0);
sta.trigger = info->trigger;
sta.is_hesta = info->is_hesta;
sta.dl_bw = info->dl_bw;
sta.tf_mac_padding = info->tf_mac_padding;
sta.dl_t_pe = info->dl_t_pe;
sta.port_id = info->port;
sta.net_type = info->net_type;
sta.wifi_role = info->wifi_role;
sta.self_role = info->self_role;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_joininfo));
if (!buf) {
ret = MACNOBUF;
goto join_info_fail;
}
fwcmd_tbl = (struct fwcmd_joininfo *)buf;
fwcmd_tbl->dword0 =
cpu_to_le32(SET_WORD(sta.macid, FWCMD_H2C_JOININFO_MACID) |
(sta.opmode ? FWCMD_H2C_JOININFO_OPMODE : 0) |
(sta.band ? FWCMD_H2C_JOININFO_BAND : 0) |
SET_WORD(sta.wmm, FWCMD_H2C_JOININFO_WMM) |
(sta.trigger ? FWCMD_H2C_JOININFO_TRIGGER : 0) |
(sta.is_hesta ? FWCMD_H2C_JOININFO_ISHESTA : 0) |
SET_WORD(sta.dl_bw, FWCMD_H2C_JOININFO_DL_BW) |
SET_WORD(sta.tf_mac_padding,
FWCMD_H2C_JOININFO_TF_MAC_PADDING) |
SET_WORD(sta.dl_t_pe, FWCMD_H2C_JOININFO_DL_T_PE) |
SET_WORD(sta.port_id, FWCMD_H2C_JOININFO_PORT_ID) |
SET_WORD(sta.net_type, FWCMD_H2C_JOININFO_NET_TYPE) |
SET_WORD(sta.wifi_role, FWCMD_H2C_JOININFO_WIFI_ROLE) |
SET_WORD(sta.self_role, FWCMD_H2C_JOININFO_SELF_ROLE));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MEDIA_RPT,
FWCMD_H2C_FUNC_JOININFO,
0,
1);
if (ret != MACSUCCESS)
goto join_info_fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto join_info_fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret != MACSUCCESS)
goto join_info_fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
join_info_fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 mac_fw_role_maintain(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_fwrole_maintain *fwcmd_tbl;
struct mac_ax_fwrole_maintain fwrole_main;
u32 ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_WARN("%s fw not ready\n", __func__);
return MACFWNONRDY;
}
fwrole_main.macid = info->macid;
fwrole_main.self_role = info->self_role;
fwrole_main.upd_mode = info->upd_mode;
fwrole_main.wifi_role = info->wifi_role;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_fwrole_maintain));
if (!buf) {
ret = MACNOBUF;
goto role_maintain_fail;
}
fwcmd_tbl = (struct fwcmd_fwrole_maintain *)buf;
fwcmd_tbl->dword0 =
cpu_to_le32(SET_WORD(fwrole_main.macid,
FWCMD_H2C_FWROLE_MAINTAIN_MACID) |
SET_WORD(fwrole_main.self_role,
FWCMD_H2C_FWROLE_MAINTAIN_SELF_ROLE) |
SET_WORD(fwrole_main.upd_mode,
FWCMD_H2C_FWROLE_MAINTAIN_UPD_MODE) |
SET_WORD(fwrole_main.wifi_role,
FWCMD_H2C_FWROLE_MAINTAIN_WIFI_ROLE));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MEDIA_RPT,
FWCMD_H2C_FUNC_FWROLE_MAINTAIN,
0,
1);
if (ret != MACSUCCESS)
goto role_maintain_fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto role_maintain_fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret != MACSUCCESS)
goto role_maintain_fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
role_maintain_fail:
h2cb_free(adapter, h2cb);
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/role.c
|
C
|
agpl-3.0
| 30,086
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_ROLE_H_
#define _MAC_AX_ROLE_H_
#include "../type.h"
#include "fwcmd.h"
#include "addr_cam.h"
#include "security_cam.h"
#include "hw.h"
#include "trxcfg.h"
#define CCTL_NTX_PATH_EN 3
#define CCTL_PATH_MAP_B 1
#define CCTL_PATH_MAP_C 2
#define CCTL_PATH_MAP_D 3
#define CCTRL_NC 1
#define CCTRL_NR 1
#define CCTRL_CB 1
#define CCTRL_CSI_PARA_EN 1
#define CCTRL_CSI_PARA_EN_MSK 1
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief role_tbl_init
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 role_tbl_init(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief role_tbl_exit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 role_tbl_exit(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief role_info_valid
*
* @param *adapter
* @param *info
* @param change_role
* @return Please Place Description here.
* @retval u32
*/
u32 role_info_valid(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
enum mac_ax_role_opmode op);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_add_role
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_add_role(struct mac_ax_adapter *adapter, struct mac_ax_role_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_remove_role
*
* @param *adapter
* @param macid
* @return Please Place Description here.
* @retval u32
*/
u32 mac_remove_role(struct mac_ax_adapter *adapter, u8 macid);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_remove_role_by_band
*
* @param *adapter
* @param band
* @param sw
* @return Please Place Description here.
* @retval u32
*/
u32 mac_remove_role_by_band(struct mac_ax_adapter *adapter, u8 band, u8 sw);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_change_role
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_change_role(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_role_srch
*
* @param *adapter
* @param macid
* @return Please Place Description here.
* @retval mac_role_tbl
*/
struct mac_role_tbl *mac_role_srch(struct mac_ax_adapter *adapter,
u8 macid);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_role_srch_by_addr_cam
*
* @param *adapter
* @param addr_cam_idx
* @return Please Place Description here.
* @retval mac_role_tbl
*/
struct mac_role_tbl *mac_role_srch_by_addr_cam(struct mac_ax_adapter *adapter,
u16 addr_cam_idx);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_role_srch_by_bssid
*
* @param *adapter
* @param bssid_cam_idx
* @return Please Place Description here.
* @retval mac_role_tbl
*/
struct mac_role_tbl *mac_role_srch_by_bssid(struct mac_ax_adapter *adapter,
u8 bssid_cam_idx);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_get_macaddr
*
* @param *adapter
* @param *macaddr
* @param role_idx
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_macaddr(struct mac_ax_adapter *adapter,
struct mac_ax_macaddr *macaddr,
u8 role_idx);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_set_slot_time
*
* @param *adapter
* @param mac_ax_slot_time
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_slot_time(struct mac_ax_adapter *adapter, enum mac_ax_slot_time);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_h2c_join_info
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
static u32 mac_h2c_join_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup Role_Related
* @{
*/
/**
* @brief mac_fw_role_maintain
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
static u32 mac_fw_role_maintain(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/role.h
|
C
|
agpl-3.0
| 5,581
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "rrsr.h"
u32 mac_get_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_rrsr_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, rrsr_ctl_0, rrsr_ctl_1;
val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
return val32;
}
rrsr_ctl_0 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ?
R_AX_TRXPTCL_RRSR_CTL_0_C1 : R_AX_TRXPTCL_RRSR_CTL_0);
cfg->rrsr_rate_en = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_RATE_EN);
cfg->doppler_en = ((rrsr_ctl_0 & B_AX_WMAC_RESP_DOPPLEB_AX_EN) != 0);
cfg->dcm_en = ((rrsr_ctl_0 & B_AX_WMAC_RESP_DCM_EN) != 0);
cfg->cck_cfg = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RRSB_AX_CCK);
cfg->rsc = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_RSC);
cfg->ref_rate_sel = ((rrsr_ctl_0 & B_AX_WMAC_RESP_REF_RATE_SEL) != 0);
cfg->ref_rate = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_REF_RATE);
rrsr_ctl_1 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ?
R_AX_TRXPTCL_RRSR_CTL_1_C1 : R_AX_TRXPTCL_RRSR_CTL_1_C1);
cfg->ofdm_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_OFDM);
cfg->ht_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_HT);
cfg->vht_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_VHT);
cfg->he_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_HE);
return MACSUCCESS;
}
u32 mac_set_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_rrsr_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, rrsr_ctl_0, rrsr_ctl_1;
val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
return val32;
}
rrsr_ctl_0 = SET_WORD(cfg->rrsr_rate_en, B_AX_WMAC_RESP_RATE_EN) |
(cfg->doppler_en ? B_AX_WMAC_RESP_DOPPLEB_AX_EN : 0) |
(cfg->dcm_en ? B_AX_WMAC_RESP_DCM_EN : 0) |
SET_WORD(cfg->cck_cfg, B_AX_WMAC_RRSB_AX_CCK) |
SET_WORD(cfg->rsc, B_AX_WMAC_RESP_RSC) |
(cfg->ref_rate_sel ? B_AX_WMAC_RESP_REF_RATE_SEL : 0) |
SET_WORD(cfg->ref_rate, B_AX_WMAC_RESP_REF_RATE);
rrsr_ctl_1 = SET_WORD(cfg->ofdm_cfg, B_AX_WMAC_RRSR_OFDM) |
SET_WORD(cfg->ht_cfg, B_AX_WMAC_RRSR_HT) |
SET_WORD(cfg->vht_cfg, B_AX_WMAC_RRSR_VHT) |
SET_WORD(cfg->he_cfg, B_AX_WMAC_RRSR_HE);
// add fw offload later
if (cfg->band == MAC_AX_BAND_0) {
MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_0, rrsr_ctl_0);
MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_1, rrsr_ctl_1);
} else {
MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_0_C1, rrsr_ctl_0);
MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_1_C1, rrsr_ctl_1);
}
return MACSUCCESS;
}
u32 mac_get_cts_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_cts_rrsr_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
return val32;
}
val32 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ?
R_AX_TRXPTCL_CTS_RRSR_C1 : R_AX_TRXPTCL_CTS_RRSR);
cfg->cts_rrsr_rsc = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_RSC);
cfg->cts_rrsr_opt = ((val32 & B_AX_WMAC_CTS_RESP_OPT) != 0);
cfg->cts_rrsr_cck_cfg = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_CCK);
cfg->cts_rrsr_ofdm_cfg = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_OFDM);
return MACSUCCESS;
}
u32 mac_set_cts_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_cts_rrsr_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
return val32;
}
val32 = SET_WORD(cfg->cts_rrsr_rsc, B_AX_WMAC_CTS_RRSR_RSC) |
(cfg->cts_rrsr_opt ? B_AX_WMAC_CTS_RESP_OPT : 0) |
SET_WORD(cfg->cts_rrsr_cck_cfg, B_AX_WMAC_CTS_RRSR_CCK) |
SET_WORD(cfg->cts_rrsr_ofdm_cfg, B_AX_WMAC_CTS_RRSR_OFDM);
// add fw offload later
if (cfg->band == MAC_AX_BAND_0)
MAC_REG_W32(R_AX_TRXPTCL_CTS_RRSR, val32);
else
MAC_REG_W32(R_AX_TRXPTCL_CTS_RRSR_C1, val32);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/rrsr.c
|
C
|
agpl-3.0
| 4,813
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_RRSR_H_
#define _MAC_AX_RRSR_H_
#include "../type.h"
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RRSR
* @{
*/
/**
* @brief mac_get_rrsr_cfg
*
* @param *adapter
* @param *mac_ax_rrsr_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_rrsr_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RRSR
* @{
*/
/**
* @brief mac_set_rrsr_cfg
*
* @param *adapter
* @param *mac_ax_rrsr_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_rrsr_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RRSR
* @{
*/
/**
* @brief mac_get_rrsr_cfg
*
* @param *adapter
* @param mac_ax_cts_rrsr_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_cts_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_cts_rrsr_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RRSR
* @{
*/
/**
* @brief mac_set_rrsr_cfg
*
* @param *adapter
* @param mac_ax_cts_rrsr_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_cts_rrsr_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_cts_rrsr_cfg *cfg);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/rrsr.h
|
C
|
agpl-3.0
| 2,048
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "rx_filter.h"
/* control frames: drop, mgnt frames: to host, data frame: to host */
static enum mac_ax_fwd_target trxcfg_rx_fltr_mgnt_frame = MAC_AX_FWD_TO_HOST;
static enum mac_ax_fwd_target trxcfg_rx_fltr_ctrl_frame = MAC_AX_FWD_TO_HOST;
static enum mac_ax_fwd_target trxcfg_rx_fltr_data_frame = MAC_AX_FWD_TO_HOST;
static struct mac_ax_rx_fltr_ctrl_t rx_fltr_init_opt = {
1, /* sniffer_mode */
1, /* acpt_a1_match_pkt */
1, /* acpt_bc_pkt */
1, /* acpt_mc_pkt */
1, /* uc_pkt_chk_cam_match */
1, /* bc_pkt_chk_cam_match */
0, /* mc_pkt_white_lst_mode */
0, /* bcn_chk_en */
0, /* bcn_chk_rule */
0, /* acpt_pwr_mngt_pkt */
0, /* acpt_crc32_err_pkt */
0, /* acpt_unsupport_pkt */
0, /* acpt_mac_hdr_content_err_pkt */
0, /* acpt_ftm_req_pkt */
0, /* pkt_len_fltr */
0, /* unsp_pkt_target */
3, /* uid_fltr */
1, /* cck_crc_chk_enable */
1, /* cck_sig_chk_enable */
1, /* lsig_parity_chk_enable */
1, /* siga_crc_chk_enable */
1, /* vht_su_sigb_crc_chk_enable */
1, /* vht_mu_sigb_crc_chk_enable */
1, /* he_sigb_crc_chk_enable */
0, /* min_len_chk_disable */
};
u32 rx_fltr_init(struct mac_ax_adapter *adapter, enum mac_ax_band band)
{
u32 ret;
struct mac_ax_ops *mac_ax_ops = adapter_to_mac_ops(adapter);
struct mac_ax_rx_fltr_ctrl_t opt_msk = {
0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x1, 0x1, 0x1,
0x1, 0x1, 0x3F, 0x3, 0x3, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1
};
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
ret = mac_ax_ops->set_rx_fltr_typ_opt(adapter,
MAC_AX_PKT_MGNT,
trxcfg_rx_fltr_mgnt_frame,
band);
if (ret != MACSUCCESS)
return ret;
ret = mac_ax_ops->set_rx_fltr_typ_opt(adapter,
MAC_AX_PKT_CTRL,
trxcfg_rx_fltr_ctrl_frame,
band);
if (ret != MACSUCCESS)
return ret;
ret = mac_ax_ops->set_rx_fltr_typ_opt(adapter,
MAC_AX_PKT_DATA,
trxcfg_rx_fltr_data_frame,
band);
if (ret != MACSUCCESS)
return ret;
ret = mac_ax_ops->set_rx_fltr_opt(adapter,
&rx_fltr_init_opt,
&opt_msk,
band);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
static void rx_fltr_opt_2_uint(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt,
u32 *mac_fltr_value,
u16 *plcp_fltr_value)
{
u32 val32 = 0x0;
u8 val16 = 0x0;
val32 =
((fltr_opt->sniffer_mode) ?
B_AX_SNIFFER_MODE : 0) |
((fltr_opt->acpt_a1_match_pkt) ?
B_AX_A_A1_MATCH : 0) |
((fltr_opt->acpt_bc_pkt) ?
B_AX_A_BC : 0) |
((fltr_opt->acpt_mc_pkt) ?
B_AX_A_MC : 0) |
((fltr_opt->uc_pkt_chk_cam_match) ?
B_AX_A_UC_CAM_MATCH : 0) |
((fltr_opt->bc_pkt_chk_cam_match) ?
B_AX_A_BC_CAM_MATCH : 0) |
((fltr_opt->mc_pkt_white_lst_mode) ?
B_AX_A_MC_LIST_CAM_MATCH : 0) |
((fltr_opt->bcn_chk_en) ?
B_AX_A_BCN_CHK_EN : 0) |
((fltr_opt->acpt_pwr_mngt_pkt) ?
B_AX_A_PWR_MGNT : 0) |
((fltr_opt->acpt_crc32_err_pkt) ?
B_AX_A_CRC32_ERR : 0) |
((fltr_opt->acpt_mac_hdr_content_err_pkt) ?
B_AX_A_ERR_PKT : 0) |
((fltr_opt->acpt_unsupport_pkt) ?
B_AX_A_UNSUP_PKT : 0) |
((fltr_opt->acpt_ftm_req_pkt) ?
B_AX_A_FTM_REQ : 0) |
SET_WORD(fltr_opt->bcn_chk_rule,
RX_FLTR_BCN_CHK_RULE) |
SET_WORD(fltr_opt->pkt_len_fltr,
RX_FLTR_PKT_LEN_FLTR) |
SET_WORD(fltr_opt->unsp_pkt_target,
RX_FLTR_UNSUPPORT_PKT_FLTR) |
SET_WORD(fltr_opt->uid_fltr,
RX_FLTR_UID_FLTR);
*mac_fltr_value = val32;
val16 =
((fltr_opt->cck_crc_chk_enable) ?
B_AX_CCK_CRC_CHK : 0) |
((fltr_opt->cck_sig_chk_enable) ?
B_AX_CCK_SIG_CHK : 0) |
((fltr_opt->lsig_parity_chk_enable) ?
B_AX_LSIG_PARITY_CHK : 0) |
((fltr_opt->siga_crc_chk_enable) ?
B_AX_SIGA_CRC_CHK : 0) |
((fltr_opt->vht_su_sigb_crc_chk_enable) ?
B_AX_VHT_SU_SIGB_CRC_CHK : 0) |
((fltr_opt->vht_mu_sigb_crc_chk_enable) ?
B_AX_VHT_MU_SIGB_CRC_CHK : 0) |
((fltr_opt->he_sigb_crc_chk_enable) ?
B_AX_HE_SIGB_CRC_CHK : 0) |
((fltr_opt->min_len_chk_disable) ?
B_AX_DIS_CHK_MIN_LEN : 0);
*plcp_fltr_value = val16;
}
u32 mac_get_rx_fltr_opt(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return val32;
}
if (!fltr_opt) {
PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__);
return MACNPTR;
}
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_RX_FLTR_OPT_C1 : R_AX_RX_FLTR_OPT);
fltr_opt->sniffer_mode = ((val32 & B_AX_SNIFFER_MODE) != 0);
fltr_opt->acpt_a1_match_pkt = ((val32 & B_AX_A_A1_MATCH) != 0);
fltr_opt->acpt_bc_pkt = ((val32 & B_AX_A_BC) != 0);
fltr_opt->acpt_mc_pkt = ((val32 & B_AX_A_MC) != 0);
fltr_opt->uc_pkt_chk_cam_match = ((val32 & B_AX_A_UC_CAM_MATCH) != 0);
fltr_opt->bc_pkt_chk_cam_match = ((val32 & B_AX_A_BC_CAM_MATCH) != 0);
fltr_opt->mc_pkt_white_lst_mode = ((val32 &
B_AX_A_MC_LIST_CAM_MATCH) != 0);
fltr_opt->bcn_chk_en = ((val32 & B_AX_A_BCN_CHK_EN) != 0);
fltr_opt->acpt_pwr_mngt_pkt = ((val32 & B_AX_A_PWR_MGNT) != 0);
fltr_opt->acpt_crc32_err_pkt = ((val32 & B_AX_A_CRC32_ERR) != 0);
fltr_opt->acpt_mac_hdr_content_err_pkt = ((val32 &
B_AX_A_ERR_PKT) != 0);
fltr_opt->acpt_unsupport_pkt = ((val32 & B_AX_A_UNSUP_PKT) != 0);
fltr_opt->acpt_ftm_req_pkt = ((val32 & B_AX_A_FTM_REQ) != 0);
fltr_opt->bcn_chk_rule = GET_FIELD(val32, RX_FLTR_BCN_CHK_RULE);
fltr_opt->pkt_len_fltr = GET_FIELD(val32, RX_FLTR_PKT_LEN_FLTR);
fltr_opt->unsp_pkt_target = GET_FIELD(val32,
RX_FLTR_UNSUPPORT_PKT_FLTR);
fltr_opt->uid_fltr = GET_FIELD(val32, RX_FLTR_UID_FLTR);
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_PLCP_HDR_FLTR_C1 : R_AX_PLCP_HDR_FLTR);
fltr_opt->cck_crc_chk_enable = ((val32 & B_AX_CCK_CRC_CHK) != 0);
fltr_opt->cck_sig_chk_enable = ((val32 & B_AX_CCK_SIG_CHK) != 0);
fltr_opt->lsig_parity_chk_enable = ((val32 &
B_AX_LSIG_PARITY_CHK) != 0);
fltr_opt->siga_crc_chk_enable = ((val32 & B_AX_SIGA_CRC_CHK) != 0);
fltr_opt->vht_su_sigb_crc_chk_enable = ((val32 &
B_AX_VHT_SU_SIGB_CRC_CHK)
!= 0);
fltr_opt->vht_mu_sigb_crc_chk_enable = ((val32 &
B_AX_VHT_MU_SIGB_CRC_CHK)
!= 0);
fltr_opt->he_sigb_crc_chk_enable = ((val32 & B_AX_HE_SIGB_CRC_CHK)
!= 0);
fltr_opt->min_len_chk_disable = ((val32 & B_AX_DIS_CHK_MIN_LEN)
!= 0);
return MACSUCCESS;
}
u32 mac_set_rx_fltr_opt(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt_msk,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_rx_fltr_ctrl_t opt = {0};
u32 mac_opt;
u16 plcp_opt;
u32 mac_opt_msk;
u16 plcp_opt_msk;
u32 mac_opt_value;
u16 plcp_opt_value;
u32 ret = MACSUCCESS;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return ret;
}
if (!fltr_opt || !fltr_opt_msk) {
PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__);
return MACNPTR;
}
mac_get_rx_fltr_opt(adapter, &opt, band);
rx_fltr_opt_2_uint(adapter,
fltr_opt,
&mac_opt,
&plcp_opt);
rx_fltr_opt_2_uint(adapter,
fltr_opt_msk,
&mac_opt_msk,
&plcp_opt_msk);
rx_fltr_opt_2_uint(adapter,
&opt,
&mac_opt_value,
&plcp_opt_value);
mac_opt_value = (mac_opt & mac_opt_msk) |
(~(~mac_opt & mac_opt_msk) & mac_opt_value);
plcp_opt_value = (plcp_opt & plcp_opt_msk) |
(~(~plcp_opt & plcp_opt_msk) & plcp_opt_value);
// add fw offload later
if (band == MAC_AX_BAND_0) {
MAC_REG_W32(R_AX_RX_FLTR_OPT, mac_opt_value);
MAC_REG_W16(R_AX_PLCP_HDR_FLTR, plcp_opt_value);
} else {
MAC_REG_W32(R_AX_RX_FLTR_OPT_C1, mac_opt_value);
MAC_REG_W16(R_AX_PLCP_HDR_FLTR_C1, plcp_opt_value);
}
return ret;
}
u32 mac_set_typ_fltr_opt(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
enum mac_ax_fwd_target fwd_target,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return val32;
}
switch (fwd_target) {
case MAC_AX_FWD_DONT_CARE:
val32 = RX_FLTR_FRAME_DROP;
break;
case MAC_AX_FWD_TO_HOST:
val32 = RX_FLTR_FRAME_TO_HOST;
break;
case MAC_AX_FWD_TO_WLAN_CPU:
val32 = RX_FLTR_FRAME_TO_WLCPU;
break;
default:
PLTFM_MSG_ERR("[ERR]%s fwd target err\n", __func__);
return MACNOITEM;
}
switch (type) {
case MAC_AX_PKT_MGNT:
MAC_REG_W32((band == MAC_AX_BAND_1) ?
R_AX_MGNT_FLTR_C1 : R_AX_MGNT_FLTR, val32);
break;
case MAC_AX_PKT_CTRL:
MAC_REG_W32((band == MAC_AX_BAND_1) ?
R_AX_CTRL_FLTR_C1 : R_AX_CTRL_FLTR, val32);
break;
case MAC_AX_PKT_DATA:
MAC_REG_W32((band == MAC_AX_BAND_1) ?
R_AX_DATA_FLTR_C1 : R_AX_DATA_FLTR, val32);
break;
default:
PLTFM_MSG_ERR("[ERR]%s type err\n", __func__);
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_set_typsbtyp_fltr_opt(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
u8 subtype,
enum mac_ax_fwd_target fwd_target,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return val32;
}
if (fwd_target != MAC_AX_FWD_DONT_CARE &&
fwd_target != MAC_AX_FWD_TO_HOST &&
fwd_target != MAC_AX_FWD_TO_WLAN_CPU) {
PLTFM_MSG_ERR("[ERR]%s fwd target err\n", __func__);
return MACNOITEM;
}
switch (type) {
case MAC_AX_PKT_MGNT:
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_MGNT_FLTR_C1 : R_AX_MGNT_FLTR);
val32 = SET_CLR_WOR2(val32, fwd_target,
((subtype & 0xf) * 2), 0x3);
MAC_REG_W32((band == MAC_AX_BAND_1) ?
R_AX_MGNT_FLTR_C1 : R_AX_MGNT_FLTR, val32);
break;
case MAC_AX_PKT_CTRL:
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_CTRL_FLTR_C1 : R_AX_CTRL_FLTR);
val32 = SET_CLR_WOR2(val32, fwd_target,
((subtype & 0xf) * 2), 0x3);
MAC_REG_W32((band == MAC_AX_BAND_1) ?
R_AX_CTRL_FLTR_C1 : R_AX_CTRL_FLTR, val32);
break;
case MAC_AX_PKT_DATA:
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_DATA_FLTR_C1 : R_AX_DATA_FLTR);
val32 = SET_CLR_WOR2(val32, fwd_target,
((subtype & 0xf) * 2), 0x3);
MAC_REG_W32((band == MAC_AX_BAND_1) ?
R_AX_DATA_FLTR_C1 : R_AX_DATA_FLTR, val32);
break;
default:
PLTFM_MSG_ERR("[ERR]%s type err\n", __func__);
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_set_typsbtyp_fltr_detail(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
struct mac_ax_rx_fltr_elem *elem,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 cmp_bit = 1;
u16 reg;
u8 idx;
val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return val32;
}
switch (type) {
case MAC_AX_PKT_CTRL:
reg = (band == MAC_AX_BAND_0) ? R_AX_CTRL_FLTR : R_AX_CTRL_FLTR_C1;
break;
case MAC_AX_PKT_MGNT:
reg = (band == MAC_AX_BAND_0) ? R_AX_MGNT_FLTR : R_AX_MGNT_FLTR_C1;
break;
case MAC_AX_PKT_DATA:
reg = (band == MAC_AX_BAND_0) ? R_AX_DATA_FLTR : R_AX_DATA_FLTR_C1;
break;
default:
PLTFM_MSG_ERR("[ERR]%s type err\n", __func__);
return MACNOITEM;
}
val32 = MAC_REG_R32(reg);
for (idx = 0; idx < RX_FLTR_SUBTYPE_NUM; idx++) {
if ((elem->subtype_mask & cmp_bit) != 0)
val32 = SET_CLR_WOR2(val32, elem->target_arr[idx],
ENTRY_SH(idx), ENTRY_MSK);
cmp_bit = cmp_bit << ENTRY_IDX;
}
MAC_REG_W32(reg, val32);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/rx_filter.c
|
C
|
agpl-3.0
| 12,710
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_RX_FILTER_H_
#define _MAC_AX_RX_FILTER_H_
#include "trxcfg.h"
#include "../type.h"
#define RX_FLTR_BCN_CHK_RULE_SH 8
#define RX_FLTR_BCN_CHK_RULE_MSK 0x3
#define RX_FLTR_PKT_LEN_FLTR_SH 16
#define RX_FLTR_PKT_LEN_FLTR_MSK 0x7F
#define RX_FLTR_UNSUPPORT_PKT_FLTR_SH 22
#define RX_FLTR_UNSUPPORT_PKT_FLTR_MSK 0x3
#define RX_FLTR_UID_FLTR_SH 24
#define RX_FLTR_UID_FLTR_MSK 0xFF
#define RX_FLTR_FRAME_DROP 0x00000000
#define RX_FLTR_FRAME_TO_HOST 0x55555555
#define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA
#define RX_FLTR_SUBTYPE_NUM 16
#define ENTRY_MSK 0x3
#define ENTRY_SH(_idx) (_idx * 2)
#define ENTRY_IDX 1
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RX_Filter
* @{
*/
/**
* @brief mac_get_rx_fltr_opt
*
* @param *adapter
* @param *fltr_opt
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_rx_fltr_opt(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt,
enum mac_ax_band band);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RX_Filter
* @{
*/
/**
* @brief mac_set_rx_fltr_opt
*
* @param *adapter
* @param *fltr_opt
* @param *fltr_opt_msk
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_rx_fltr_opt(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt,
struct mac_ax_rx_fltr_ctrl_t *fltr_opt_msk,
enum mac_ax_band band);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RX_Filter
* @{
*/
/**
* @brief mac_set_typ_fltr_opt
*
* @param *adapter
* @param type
* @param fwd_target
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_typ_fltr_opt(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
enum mac_ax_fwd_target fwd_target,
enum mac_ax_band band);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RX_Filter
* @{
*/
/**
* @brief mac_set_typsbtyp_fltr_opt
*
* @param *adapter
* @param type
* @param subtype
* @param fwd_target
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_typsbtyp_fltr_opt(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
u8 subtype,
enum mac_ax_fwd_target fwd_target,
enum mac_ax_band band);
/**
* @}
* @}
*/
u32 rx_fltr_init(struct mac_ax_adapter *adapter,
enum mac_ax_band band);
/**
* @brief mac_set_typ_fltr_opt
*
* @param *adapter
* @param type
* @param fwd_target
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_typsbtyp_fltr_detail(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
struct mac_ax_rx_fltr_elem *elem,
enum mac_ax_band band);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/rx_filter.h
|
C
|
agpl-3.0
| 3,453
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "rx_forwarding.h"
#if MAC_AX_FW_REG_OFLD
u32 mac_set_rx_forwarding(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_rx_fwd *rx_fwd;
struct mac_ax_af_ud_ctrl_t *af_ud;
struct mac_ax_pm_cam_ctrl_t *pm_cam;
if (!rf_ctrl_p)
return MACNPTR;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_rx_fwd));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
rx_fwd = (struct fwcmd_rx_fwd *)buf;
rx_fwd->dword0 =
cpu_to_le32(SET_WORD(rf_ctrl_p->type, FWCMD_H2C_RX_FWD_TYPE) |
SET_WORD(rf_ctrl_p->frame, FWCMD_H2C_RX_FWD_FRAME) |
SET_WORD(rf_ctrl_p->fwd_tg, FWCMD_H2C_RX_FWD_FWD_TG));
af_ud = &rf_ctrl_p->af_ud_ctrl;
rx_fwd->dword1 =
cpu_to_le32(SET_WORD(af_ud->index, FWCMD_H2C_RX_FWD_AF_UD_INDEX) |
SET_WORD(af_ud->fwd_tg, FWCMD_H2C_RX_FWD_AF_UD_FWD_TG) |
SET_WORD(af_ud->category, FWCMD_H2C_RX_FWD_AF_UD_CATEGORY) |
SET_WORD(af_ud->action_field,
FWCMD_H2C_RX_FWD_AF_UD_ACTION_FIELD));
pm_cam = &rf_ctrl_p->pm_cam_ctrl;
rx_fwd->dword2 =
cpu_to_le32((pm_cam->valid ? FWCMD_H2C_RX_FWD_PM_CAM_VALID : 0) |
SET_WORD(pm_cam->type, FWCMD_H2C_RX_FWD_PM_CAM_TYPE) |
SET_WORD(pm_cam->subtype, FWCMD_H2C_RX_FWD_PM_CAM_SUBTYPE) |
(pm_cam->skip_mac_iv_hdr ?
FWCMD_H2C_RX_FWD_PM_CAM_SKIP_MAC_IV_HDR : 0) |
SET_WORD(pm_cam->target_ind,
FWCMD_H2C_RX_FWD_PM_CAM_TARGET_IND) |
SET_WORD(pm_cam->entry_index,
FWCMD_H2C_RX_FWD_PM_CAM_INDEX) |
SET_WORD(pm_cam->crc16, FWCMD_H2C_RX_FWD_PM_CAM_CRC16));
rx_fwd->dword3 =
cpu_to_le32(SET_WORD(pm_cam->pld_mask0,
FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK0));
rx_fwd->dword4 =
cpu_to_le32(SET_WORD(pm_cam->pld_mask1,
FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK1));
rx_fwd->dword5 =
cpu_to_le32(SET_WORD(pm_cam->pld_mask2,
FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK2));
rx_fwd->dword6 =
cpu_to_le32(SET_WORD(pm_cam->pld_mask3,
FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK3));
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_RX_FWD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
} else {
ret = MACFWNONRDY;
goto fail;
}
ret = MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#else
static inline u32 af_fwd_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_action_frame frame,
enum mac_ax_fwd_target fwd_tg)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_ACTION_FWD0);
switch (frame) {
case MAC_AX_AF_CSA:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSA);
break;
case MAC_AX_AF_ADDTS_REQ:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_REQ);
break;
case MAC_AX_AF_ADDTS_RES:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_RES);
break;
case MAC_AX_AF_DELTS:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELTS);
break;
case MAC_AX_AF_ADDBA_REQ:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_REQ);
break;
case MAC_AX_AF_ADDBA_RES:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_RES);
break;
case MAC_AX_AF_DELBA:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELBA);
break;
case MAC_AX_AF_NCW:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_NCW);
break;
case MAC_AX_AF_GID_MGNT:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_GID_MGNT);
break;
case MAC_AX_AF_OP_MODE:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_OP_MODE);
break;
case MAC_AX_AF_CSI:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSI);
break;
case MAC_AX_AF_HT_CBFM:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_HT_CBFM);
break;
case MAC_AX_AF_VHT_CBFM:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_VHT_CBFM);
break;
default:
return MACNOITEM;
}
MAC_REG_W32(R_AX_ACTION_FWD0, val32);
return MACSUCCESS;
}
static inline u32 af_ud_fwd_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_af_ud_ctrl_t *af_ud_ctrl_p)
{
u32 val32;
u16 val16;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_ACTION_FWD1);
switch (af_ud_ctrl_p->index) {
case MAC_AX_AF_UD_0:
val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL0);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category,
B_AX_FWD_ACTN_CAT0);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field,
B_AX_FWD_ACTN_ACTN0);
MAC_REG_W16(R_AX_ACTION_FWD_CTRL0, val16);
val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg,
B_AX_FWD_ACTN_CTRL0);
break;
case MAC_AX_AF_UD_1:
val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL1);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category,
B_AX_FWD_ACTN_CAT1);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field,
B_AX_FWD_ACTN_ACTN1);
MAC_REG_W16(R_AX_ACTION_FWD_CTRL1, val16);
val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg,
B_AX_FWD_ACTN_CTRL1);
break;
case MAC_AX_AF_UD_2:
val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL2);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category,
B_AX_FWD_ACTN_CAT2);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field,
B_AX_FWD_ACTN_ACTN2);
MAC_REG_W16(R_AX_ACTION_FWD_CTRL2, val16);
val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg,
B_AX_FWD_ACTN_CTRL2);
break;
case MAC_AX_AF_UD_3:
val16 = MAC_REG_R16(R_AX_ACTION_FWD_CTRL3);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->category,
B_AX_FWD_ACTN_CAT3);
val16 = SET_CLR_WORD(val16, af_ud_ctrl_p->action_field,
B_AX_FWD_ACTN_ACTN3);
MAC_REG_W16(R_AX_ACTION_FWD_CTRL3, val16);
val32 = SET_CLR_WORD(val32, af_ud_ctrl_p->fwd_tg,
B_AX_FWD_ACTN_CTRL3);
break;
default:
return MACNOITEM;
}
MAC_REG_W32(R_AX_ACTION_FWD1, val32);
return MACSUCCESS;
}
static inline u32 tf_fwd_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_trigger_frame frame,
enum mac_ax_fwd_target fwd_tg)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_TF_FWD);
switch (frame) {
case MAC_AX_TF_BT:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF0);
break;
case MAC_AX_TF_BFRP:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF1);
break;
case MAC_AX_TF_MU_BAR:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF2);
break;
case MAC_AX_TF_MU_RTS:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF3);
break;
case MAC_AX_TF_BSRP:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF4);
break;
case MAC_AX_TF_GCR_MU_BAR:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF5);
break;
case MAC_AX_TF_BQRP:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF6);
break;
case MAC_AX_TF_NFRP:
val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_TF7);
break;
default:
return MACNOITEM;
}
MAC_REG_W32(R_AX_TF_FWD, val32);
return MACSUCCESS;
}
static inline u32 pm_cam_access_polling(struct mac_ax_adapter *adapter)
{
u32 cnt = PM_CAM_WAIT_CNT;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
while (cnt--) {
if (!(MAC_REG_R32(R_AX_PLD_CAM_ACCESS) & B_AX_PLD_CAM_POLL))
break;
PLTFM_DELAY_US(PM_CAM_WAIT_US);
}
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]PM CAM access timeout\n");
return MACPOLLTO;
}
return MACSUCCESS;
}
static inline u32 pm_cam_indirect_r(struct mac_ax_adapter *adapter,
u32 offset)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = 0;
val32 = SET_CLR_WORD(val32, offset, B_AX_PLD_CAM_OFFSET);
val32 &= ~B_AX_PLD_CAM_CLR;
val32 &= ~B_AX_PLD_CAM_RW;
val32 |= B_AX_PLD_CAM_POLL;
MAC_REG_W32(R_AX_PLD_CAM_ACCESS, val32);
if (pm_cam_access_polling(adapter)) {
PLTFM_MSG_ERR("[ERR]PM CAM read timeout\n");
return MACSUCCESS;
}
return MAC_REG_R32(R_AX_PLD_CAM_RDATA);
}
static inline void pm_cam_indirect_w(struct mac_ax_adapter *adapter,
u32 offset, u32 data)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
MAC_REG_W32(R_AX_PLD_CAM_WDATA, data);
val32 = 0;
val32 = SET_CLR_WORD(val32, offset, B_AX_PLD_CAM_OFFSET);
val32 &= ~B_AX_PLD_CAM_CLR;
val32 |= B_AX_PLD_CAM_RW;
val32 |= B_AX_PLD_CAM_POLL;
MAC_REG_W32(R_AX_PLD_CAM_ACCESS, val32);
if (pm_cam_access_polling(adapter))
PLTFM_MSG_ERR("[ERR]PM CAM write timeout\n");
}
static inline u32 pm_cam_fwd_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_pm_cam_ctrl_t *pm_cam_ctrl_p)
{
u32 val32, offset;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
PLTFM_MSG_ERR("[ERR]%s PM_CAM API is removed in 52C & 92XB.\n"
, __func__);
return MACSUCCESS;
}
if (!pm_cam_ctrl_p)
return MACNPTR;
if (pm_cam_ctrl_p->entry_index >= MAC_AX_PM_CAM_ENTRY_NUM_MAX)
return MACNOITEM;
// Set as indirect access and enable PM CAM
val32 = MAC_REG_R32(R_AX_PLD_CAM_CTRL);
val32 = SET_CLR_WORD(val32, 0xf, B_AX_PLD_CAM_RANGE);
val32 |= B_AX_PLD_CAM_ACC;
val32 |= B_AX_PLD_CAM_EN;
MAC_REG_W32(R_AX_PLD_CAM_CTRL, val32);
// offset unit: 4 bytes
offset = (pm_cam_ctrl_p->entry_index *
MAC_AX_PM_CAM_ENTRY_CONTENT_SIZE) / 4;
val32 = 0;
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask0, PM_CAM_PLD_MASK0);
pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW1, val32);
if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW1)) {
PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 1\n");
return MACRFPMCAM;
}
val32 = 0;
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask1, PM_CAM_PLD_MASK1);
pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW2, val32);
if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW2)) {
PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 2\n");
return MACRFPMCAM;
}
val32 = 0;
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask2, PM_CAM_PLD_MASK2);
pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW3, val32);
if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW3)) {
PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 3\n");
return MACRFPMCAM;
}
val32 = 0;
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->pld_mask3, PM_CAM_PLD_MASK3);
pm_cam_indirect_w(adapter, offset + PM_CAM_OFFSET_DW4, val32);
if (val32 != pm_cam_indirect_r(adapter, offset + PM_CAM_OFFSET_DW4)) {
PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 4\n");
return MACRFPMCAM;
}
// PMCAM is not trigger-type reg!
val32 = 0;
val32 |= (pm_cam_ctrl_p->valid ? PM_CAM_VALID : 0);
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->type, PM_CAM_TYPE);
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->subtype, PM_CAM_SUBTYPE);
val32 |= (pm_cam_ctrl_p->skip_mac_iv_hdr ? PM_CAM_SKIP_MAC_IV_HDR : 0);
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->target_ind,
PM_CAM_TARGET_IND);
val32 = SET_CLR_WORD(val32, pm_cam_ctrl_p->crc16, PM_CAM_CRC16);
pm_cam_indirect_w(adapter, offset, val32);
if (val32 != pm_cam_indirect_r(adapter, offset)) {
PLTFM_MSG_ERR("[ERR]PM CAM cfg fail 5, %x, %x\n",
val32, pm_cam_indirect_r(adapter, offset));
return MACRFPMCAM;
}
return MACSUCCESS;
}
u32 mac_set_rx_forwarding(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p)
{
u32 ret = 0;
if (!rf_ctrl_p) {
PLTFM_MSG_ERR("[ERR]%s NULL pointer!\n", __func__);
return MACNPTR;
}
switch (rf_ctrl_p->type) {
case MAC_AX_FT_ACTION:
ret = af_fwd_cfg(adapter,
(enum mac_ax_action_frame)rf_ctrl_p->frame,
(enum mac_ax_fwd_target)rf_ctrl_p->fwd_tg);
break;
case MAC_AX_FT_ACTION_UD:
ret = af_ud_fwd_cfg(adapter, &rf_ctrl_p->af_ud_ctrl);
break;
case MAC_AX_FT_TRIGGER:
ret = tf_fwd_cfg(adapter,
(enum mac_ax_trigger_frame)rf_ctrl_p->frame,
(enum mac_ax_fwd_target)rf_ctrl_p->fwd_tg);
break;
case MAC_AX_FT_PM_CAM:
// Don't suggest using indirect access.
ret = pm_cam_fwd_cfg(adapter, &rf_ctrl_p->pm_cam_ctrl);
break;
}
return ret;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/rx_forwarding.c
|
C
|
agpl-3.0
| 12,828
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_RX_FORWARDING_H_
#define _MAC_AX_RX_FORWARDING_H_
#include "../type.h"
/*--------------------Define ----------------------------------------*/
// Payload Match CAM
#define PM_CAM_OFFSET_DW0 0
#define PM_CAM_OFFSET_DW1 1
#define PM_CAM_OFFSET_DW2 2
#define PM_CAM_OFFSET_DW3 3
#define PM_CAM_OFFSET_DW4 4
/* dword0 */
#define PM_CAM_VALID BIT(0)
#define PM_CAM_TYPE_SH 1
#define PM_CAM_TYPE_MSK 0x3
#define PM_CAM_SUBTYPE_SH 3
#define PM_CAM_SUBTYPE_MSK 0xf
#define PM_CAM_SKIP_MAC_IV_HDR BIT(7)
#define PM_CAM_TARGET_IND_SH 8
#define PM_CAM_TARGET_IND_MSK 0x7
#define PM_CAM_CRC16_SH 16
#define PM_CAM_CRC16_MSK 0xffff
/* dword1 */
#define PM_CAM_PLD_MASK0_SH 0
#define PM_CAM_PLD_MASK0_MSK 0xffffffff
/* dword2 */
#define PM_CAM_PLD_MASK1_SH 0
#define PM_CAM_PLD_MASK1_MSK 0xffffffff
/* dword3 */
#define PM_CAM_PLD_MASK2_SH 0
#define PM_CAM_PLD_MASK2_MSK 0xffffffff
/* dword4 */
#define PM_CAM_PLD_MASK3_SH 0
#define PM_CAM_PLD_MASK3_MSK 0xffffffff
#define MAC_AX_PM_CAM_ENTRY_CONTENT_SIZE 20
#define MAC_AX_PM_CAM_ENTRY_NUM_MAX 16
#define PM_CAM_WAIT_CNT 2000
#define PM_CAM_WAIT_US 1
/*--------------------Define Enum------------------------------------*/
/*--------------------Define MACRO----------------------------------*/
/*--------------------Define Struct-----------------------------------*/
/*--------------------Export global variable----------------------------*/
/*--------------------Function declaration-----------------------------*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup RX_Forwarding
* @{
*/
/**
* @brief mac_set_rx_forwarding:
* Set rx forwarding feature:
* 1. MAC_AX_FT_ACTION: for action frame
* 2. MAC_AX_FT_ACTION_UD: for action frame with user define
* 3. MAC_AX_FT_TRIGGER: for trigger frame
* 4. MAC_AX_FT_PM_CAM: for Payload match CAM
*
* @param *adapter
* @param *rf_ctrl_p
* @return Please Place Description here.
* @retval u32
* #if MAC_AX_FW_REG_OFLD
* 1. MACSUCCESS 0
* 2. MACNPTR 5
* 3. MACNOBUF 9
* 4. MACFWNONRDY 80
* #else
* 1. MACSUCCESS 0
* 2. MACNPTR 5
* 3. MACNOITEM 11
* 4. MACPOLLTO 12
* 5. MACRFPMCAM 42
* #endif
*/
u32 mac_set_rx_forwarding(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/rx_forwarding.h
|
C
|
agpl-3.0
| 2,986
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "security_cam.h"
#define ADDR_CAM_SECINFO_OFFSET 0x1C
#define HW_SUPPORT_ENC_TYPE_NUM 0x0A
#define OUTRANGE_KEY_INDEX 0xFF
#define NO_MACID_ROLE 0xFF
#define VALID 0x01
#define INVALID 0x00
#define FORCE_KEYCAM_INDEX_TYPE 0xF0
struct addr_sec_only_info {
u32 dword0;
u32 dword1;
u32 dword2;
};
enum SEC_CAM_KEY_TYPE {
SEC_CAM_KEY_TYPE_UNI = 0,
SEC_CAM_KEY_TYPE_GROUP = 1,
SEC_CAM_KEY_TYPE_BIP = 2,
SEC_CAM_KEY_TYPE_DEFAULT = 3
};
enum ADDR_CAM_SEC_MODE {
ADDR_CAM_SEC_MODE_ZERO = 0,
ADDR_CAM_SEC_MODE_ONE = 1,
ADDR_CAM_SEC_MODE_TWO = 2,
ADDR_CAM_SEC_MODE_THREE = 3,
};
enum HW_SUPPORT_ENC_TYPE {
HW_SUPPORT_ENC_TYPE_NONE = 0x0,
HW_SUPPORT_ENC_TYPE_WEP40 = 0x1,
HW_SUPPORT_ENC_TYPE_WEP104 = 0x2,
HW_SUPPORT_ENC_TYPE_TKIP = 0x3,
HW_SUPPORT_ENC_TYPE_WAPI = 0x4,
HW_SUPPORT_ENC_TYPE_GCMSMS4 = 0x5,
HW_SUPPORT_ENC_TYPE_CCMP128 = 0x6,
HW_SUPPORT_ENC_TYPE_CCMP256 = 0x7,
HW_SUPPORT_ENC_TYPE_GCMP128 = 0x8,
HW_SUPPORT_ENC_TYPE_GCMP256 = 0x9,
HW_SUPPORT_ENC_TYPE_BIP128 = 0xA,
};
u32 sec_info_tbl_init(struct mac_ax_adapter *adapter, u8 op_mode)
{
u8 i = 0;
struct sec_cam_table_t **sec_cam_table;
if (op_mode == SEC_CAM_BACKUP)
sec_cam_table = &adapter->hw_info->sec_cam_table_bk;
else
sec_cam_table = &adapter->hw_info->sec_cam_table;
/*First time access sec cam , initial sec cam table INVALID */
if ((*sec_cam_table) == NULL) {
(*sec_cam_table) = (struct sec_cam_table_t *)PLTFM_MALLOC
(sizeof(struct sec_cam_table_t));
if (!(*sec_cam_table))
return MACNOBUF;
for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) {
(*sec_cam_table)->sec_cam_entry[i] =
(struct sec_cam_entry_t *)PLTFM_MALLOC
(sizeof(struct sec_cam_entry_t));
if (!(*sec_cam_table)->sec_cam_entry[i])
return MACNOBUF;
(*sec_cam_table)->sec_cam_entry[i]->sec_cam_info =
(struct mac_ax_sec_cam_info *)PLTFM_MALLOC
(sizeof(struct mac_ax_sec_cam_info));
if (!(*sec_cam_table)->sec_cam_entry[i]->sec_cam_info)
return MACNOBUF;
/* initial value*/
(*sec_cam_table)->sec_cam_entry[i]->valid = INVALID;
(*sec_cam_table)->sec_cam_entry[i]->mac_id = 0;
(*sec_cam_table)->sec_cam_entry[i]->key_id = 0;
(*sec_cam_table)->sec_cam_entry[i]->key_type = 0;
}
(*sec_cam_table)->next_cam_storage_idx = 0;
}
return MACSUCCESS;
}
u32 free_sec_info_tbl(struct mac_ax_adapter *adapter, u8 op_mode)
{
u8 i;
struct sec_cam_table_t *sec_cam_table;
if (op_mode == SEC_CAM_RESTORE)
sec_cam_table = adapter->hw_info->sec_cam_table_bk;
else
sec_cam_table = adapter->hw_info->sec_cam_table;
if (!sec_cam_table)
return MACSUCCESS;
for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) {
PLTFM_FREE(sec_cam_table->sec_cam_entry[i]->sec_cam_info,
sizeof(struct mac_ax_sec_cam_info));
}
for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) {
PLTFM_FREE(sec_cam_table->sec_cam_entry[i],
sizeof(struct sec_cam_entry_t));
}
PLTFM_FREE(sec_cam_table, sizeof(struct sec_cam_table_t));
if (op_mode == SEC_CAM_RESTORE)
adapter->hw_info->sec_cam_table_bk = NULL;
else
adapter->hw_info->sec_cam_table = NULL;
return MACSUCCESS;
}
u32 fill_sec_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_sec_cam_info *s_info,
struct fwcmd_seccam_info *sec_info,
u8 clear)
{
if (clear == INVALID) {
sec_info->dword0 =
cpu_to_le32(SET_WORD(s_info->sec_cam_idx, FWCMD_H2C_SECCAM_INFO_IDX) |
SET_WORD(s_info->offset, FWCMD_H2C_SECCAM_INFO_OFFSET) |
SET_WORD(s_info->len, FWCMD_H2C_SECCAM_INFO_LEN));
sec_info->dword1 =
cpu_to_le32(SET_WORD(s_info->type, FWCMD_H2C_SECCAM_INFO_TYPE) |
((s_info->ext_key) ? FWCMD_H2C_SECCAM_INFO_EXT_KEY : 0) |
((s_info->spp_mode) ? FWCMD_H2C_SECCAM_INFO_SPP_MODE : 0));
sec_info->dword2 = s_info->key[0];
sec_info->dword3 = s_info->key[1];
sec_info->dword4 = s_info->key[2];
sec_info->dword5 = s_info->key[3];
} else {
sec_info->dword0 =
cpu_to_le32(SET_WORD(s_info->sec_cam_idx, FWCMD_H2C_SECCAM_INFO_IDX) |
SET_WORD(s_info->offset, FWCMD_H2C_SECCAM_INFO_OFFSET) |
SET_WORD(s_info->len, FWCMD_H2C_SECCAM_INFO_LEN));
sec_info->dword1 = 0x0;
sec_info->dword2 = 0x0;
sec_info->dword3 = 0x0;
sec_info->dword4 = 0x0;
sec_info->dword5 = 0x0;
}
return MACSUCCESS;
}
u32 fill_addr_cam_sec_only(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct addr_sec_only_info *addr_sec_info)
{
struct mac_ax_addr_cam_info a_info;
a_info = info->a_info;
addr_sec_info->dword0 =
cpu_to_le32((a_info.aid12 & 0xfff) |
((a_info.wol_pattern) ? FWCMD_H2C_ADDRCAM_INFO_WOL_PATTERN
: 0) |
((a_info.wol_uc) ? FWCMD_H2C_ADDRCAM_INFO_WOL_UC : 0) |
((a_info.wol_magic) ?
FWCMD_H2C_ADDRCAM_INFO_WOL_MAGIC : 0) |
((a_info.wapi) ? FWCMD_H2C_ADDRCAM_INFO_WAPI : 0) |
SET_WORD(a_info.sec_ent_mode,
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE) |
SET_WORD(a_info.sec_ent_keyid[0],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID) |
SET_WORD(a_info.sec_ent_keyid[1],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID) |
SET_WORD(a_info.sec_ent_keyid[2],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID) |
SET_WORD(a_info.sec_ent_keyid[3],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID) |
SET_WORD(a_info.sec_ent_keyid[4],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID) |
SET_WORD(a_info.sec_ent_keyid[5],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID) |
SET_WORD(a_info.sec_ent_keyid[6],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID));
addr_sec_info->dword1 =
cpu_to_le32(SET_WORD(a_info.sec_ent_valid,
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID) |
SET_WORD(a_info.sec_ent[0],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0) |
SET_WORD(a_info.sec_ent[1],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1) |
SET_WORD(a_info.sec_ent[2],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2));
addr_sec_info->dword2 =
cpu_to_le32(SET_WORD(a_info.sec_ent[3],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3) |
SET_WORD(a_info.sec_ent[4],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4) |
SET_WORD(a_info.sec_ent[5],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5) |
SET_WORD(a_info.sec_ent[6],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6));
return MACSUCCESS;
}
u32 mac_upd_sec_infotbl(struct mac_ax_adapter *adapter,
struct fwcmd_seccam_info *info)
{
u32 ret = 0, s_info_tbl[6], cam_address = 0;
u8 *buf, i;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_seccam_info *tbl;
struct mac_ax_sec_cam_info *s_info;
/*h2c access*/
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_seccam_info));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_seccam_info *)buf;
tbl->dword0 = info->dword0;
tbl->dword1 = info->dword1;
tbl->dword2 = info->dword2;
tbl->dword3 = info->dword3;
tbl->dword4 = info->dword4;
tbl->dword5 = info->dword5;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_SEC_CAM,
FWCMD_H2C_FUNC_SECCAM_INFO,
0,
1);
if (ret != MACSUCCESS)
goto fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret != MACSUCCESS)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
} else {
/* Indirect Access */
s_info = (struct mac_ax_sec_cam_info *)info;
s_info_tbl[0] = info->dword0;
s_info_tbl[1] = info->dword1;
s_info_tbl[2] = info->dword2;
s_info_tbl[3] = info->dword3;
s_info_tbl[4] = info->dword4;
s_info_tbl[5] = info->dword5;
/* Indirect write security cam */
PLTFM_MSG_WARN("%s ind access start\n", __func__);
cam_address = s_info->sec_cam_idx * SEC_CAM_ENTRY_SIZE;
for (i = 0; i < 5; i++)
mac_sram_dbg_write(adapter, cam_address + (i * 4),
cpu_to_le32(s_info_tbl[i + 1]),
SEC_CAM_SEL);
PLTFM_MSG_WARN("%s ind access end\n", __func__);
return MACSUCCESS;
}
return ret;
}
u8 check_key_index(u8 addr_cam_sec_mode, u8 key_type, u8 key_index)
{
switch (addr_cam_sec_mode) {
case ADDR_CAM_SEC_MODE_ZERO:
switch (key_type) {
case SEC_CAM_KEY_TYPE_UNI:
if (key_index <= 6)
return MACSUCCESS;
default:
break;
}
break;
case ADDR_CAM_SEC_MODE_ONE:
switch (key_type) {
case SEC_CAM_KEY_TYPE_UNI:
if (key_index <= 6)
return MACSUCCESS;
default:
break;
}
break;
case ADDR_CAM_SEC_MODE_TWO:
switch (key_type) {
case SEC_CAM_KEY_TYPE_UNI:
if (key_index <= 1)
return MACSUCCESS;
break;
case SEC_CAM_KEY_TYPE_GROUP:
if (key_index >= 2 && key_index <= 4)
return MACSUCCESS;
break;
case SEC_CAM_KEY_TYPE_BIP:
if (key_index >= 5 && key_index <= 6)
return MACSUCCESS;
break;
default:
break;
}
break;
case ADDR_CAM_SEC_MODE_THREE:
switch (key_type) {
case SEC_CAM_KEY_TYPE_UNI:
if (key_index <= 1)
return MACSUCCESS;
break;
case SEC_CAM_KEY_TYPE_GROUP:
if (key_index >= 2 && key_index <= 5)
return MACSUCCESS;
break;
case SEC_CAM_KEY_TYPE_BIP:
if (key_index == 6)
return MACSUCCESS;
break;
default:
break;
}
break;
}
return 1;
}
u8 decide_key_index(u8 addr_cam_sec_mode, u8 key_type)
{
u8 key_index = 0;
switch (addr_cam_sec_mode) {
case ADDR_CAM_SEC_MODE_ZERO:
if (key_type == SEC_CAM_KEY_TYPE_UNI)
key_index = 0;
else if (key_type == SEC_CAM_KEY_TYPE_GROUP)
return MACWNGKEYTYPE;
else if (key_type == SEC_CAM_KEY_TYPE_BIP)
return MACWNGKEYTYPE;
break;
case ADDR_CAM_SEC_MODE_ONE:
if (key_type == SEC_CAM_KEY_TYPE_UNI)
key_index = 0;
else if (key_type == SEC_CAM_KEY_TYPE_GROUP)
return MACWNGKEYTYPE;
else if (key_type == SEC_CAM_KEY_TYPE_BIP)
return MACWNGKEYTYPE;
break;
case ADDR_CAM_SEC_MODE_TWO:
if (key_type == SEC_CAM_KEY_TYPE_UNI)
key_index = 0;
else if (key_type == SEC_CAM_KEY_TYPE_GROUP)
key_index = 2;
else if (key_type == SEC_CAM_KEY_TYPE_BIP)
key_index = 5;
break;
case ADDR_CAM_SEC_MODE_THREE:
if (key_type == SEC_CAM_KEY_TYPE_UNI)
key_index = 0;
else if (key_type == SEC_CAM_KEY_TYPE_GROUP)
key_index = 2;
else if (key_type == SEC_CAM_KEY_TYPE_BIP)
key_index = 6;
break;
default:
break;
}
return key_index;
}
u8 decide_sec_cam_index(struct mac_ax_adapter *adapter, u8 *sec_cam_idx)
{
u8 sec_idx = 0, i = 0;
/* call by pointer */
struct sec_cam_table_t **sec_cam_table =
&adapter->hw_info->sec_cam_table;
/*First time access sec cam , initial sec cam table INVALID */
if ((*sec_cam_table) == NULL) {
(*sec_cam_table) = (struct sec_cam_table_t *)PLTFM_MALLOC
(sizeof(struct sec_cam_table_t));
if (!(*sec_cam_table))
return MACNOBUF;
for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) {
(*sec_cam_table)->sec_cam_entry[i] =
(struct sec_cam_entry_t *)PLTFM_MALLOC
(sizeof(struct sec_cam_entry_t));
if (!(*sec_cam_table)->sec_cam_entry[i])
return MACNOBUF;
(*sec_cam_table)->sec_cam_entry[i]->sec_cam_info =
(struct mac_ax_sec_cam_info *)PLTFM_MALLOC
(sizeof(struct mac_ax_sec_cam_info));
if (!(*sec_cam_table)->sec_cam_entry[i]->sec_cam_info)
return MACNOBUF;
/* initial value*/
(*sec_cam_table)->sec_cam_entry[i]->valid = INVALID;
(*sec_cam_table)->sec_cam_entry[i]->mac_id = 0;
(*sec_cam_table)->sec_cam_entry[i]->key_id = 0;
(*sec_cam_table)->sec_cam_entry[i]->key_type = 0;
}
(*sec_cam_table)->next_cam_storage_idx = 0;
}
/*If table has been initialize, assgin the sec cam storge idx */
sec_idx = (*sec_cam_table)->next_cam_storage_idx;
for (i = 0; i < SEC_CAM_ENTRY_NUM; i++) {
if ((*sec_cam_table)->sec_cam_entry[sec_idx]->valid ==
INVALID) {
(*sec_cam_table)->next_cam_storage_idx =
(sec_idx + 1) % SEC_CAM_ENTRY_NUM;
*sec_cam_idx = sec_idx;
return MACSUCCESS;
}
sec_idx++;
sec_idx %= SEC_CAM_ENTRY_NUM;
}
return MACSECCAMFL;
}
u8 delete_key_from_addr_cam(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role, u8 key_type,
u8 key_id, u8 *sec_cam_idx)
{
u32 ret = 0;
u8 key_index = 0, key_valid_byte = 0, i = 0;
u8 key_valid[7] = {0}, hit_flag = 0;
key_valid_byte = role->info.a_info.sec_ent_valid;
key_index = decide_key_index(role->info.a_info.sec_ent_mode, key_type);
if (key_index == MACWNGKEYTYPE)
return MACWNGKEYTYPE;
for (i = 0; i < 7; i++) {
key_valid[i] = key_valid_byte % 2;
key_valid_byte = key_valid_byte >> 1;
}
/* find the key real storage idx */
for (i = key_index; i < 7; i++) {
if (role->info.a_info.sec_ent_keyid[i] == key_id &&
key_valid[i] == VALID) {
key_index = i;
hit_flag = 1;
break;
}
}
if (hit_flag == 0)
return MACKEYNOTEXT;
if (check_key_index(role->info.a_info.sec_ent_mode,
key_type, key_index)) {
PLTFM_MSG_TRACE("check addr key index full\n");
return MACADDRCAMKEYFL;
}
/*get the key cam index*/
*sec_cam_idx = role->info.a_info.sec_ent[key_index];
role->info.a_info.sec_ent_keyid[key_index] = 0;
role->info.a_info.sec_ent_valid &= ~(BIT(key_index));
role->info.a_info.sec_ent[key_index] = 0;
/* update addr cam */
ret = mac_upd_addr_cam(adapter, &role->info, CHG);
if (ret == MACBSSIDCAMFL) {
PLTFM_MSG_ERR("[ERR]: BSSID CAM full\n");
return MACBSSIDCAMFL;
}
return MACSUCCESS;
}
u8 insert_key_to_addr_cam(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role, u8 key_type,
u8 key_id, u8 sec_cam_idx)
{
u32 ret = 0;
u8 key_index = 0, key_valid_byte = 0, i = 0;
u8 key_valid[7] = {0}, hit_flag = 0;
key_valid_byte = role->info.a_info.sec_ent_valid;
key_index = decide_key_index(role->info.a_info.sec_ent_mode, key_type);
if (key_index == MACWNGKEYTYPE)
return MACWNGKEYTYPE;
for (i = 0; i < 7; i++) {
key_valid[i] = key_valid_byte % 2;
key_valid_byte = key_valid_byte >> 1;
}
/* find the key real storage idx */
for (i = key_index; i < 7; i++) {
if (key_valid[i] != VALID) {
key_index = i;
hit_flag = 1;
break;
}
}
if (hit_flag == 0)
return MACADDRCAMKEYFL;
if (check_key_index(role->info.a_info.sec_ent_mode,
key_type, key_index)) {
PLTFM_MSG_TRACE("check addr key index full\n");
return MACADDRCAMKEYFL;
}
role->info.a_info.sec_ent_keyid[key_index] = key_id;
role->info.a_info.sec_ent_valid |= BIT(key_index);
role->info.a_info.sec_ent[key_index] = sec_cam_idx;
ret = mac_upd_addr_cam(adapter, &role->info, CHG);
if (ret == MACBSSIDCAMFL) {
PLTFM_MSG_ERR("[ERR]: BSSID CAM full\n");
return MACBSSIDCAMFL;
}
return MACSUCCESS;
}
u32 m_security_cam_hal(struct mac_ax_adapter *adapter,
struct mac_ax_sec_cam_info *sec_cam_info,
u8 mac_id, u8 key_id, u8 key_type,
u8 sec_cam_idx, u8 opmode)
{
u8 i = 0;
struct sec_cam_entry_t *sec_cam_entry = NULL;
struct sec_cam_entry_t *sec_cam_bk_entry = NULL;
struct sec_cam_table_t *sec_cam_table = adapter->hw_info->sec_cam_table;
struct sec_cam_table_t *sec_cam_table_bk =
adapter->hw_info->sec_cam_table_bk;
if (!sec_cam_table)
return MACSUCCESS;
sec_cam_entry =
adapter->hw_info->sec_cam_table->sec_cam_entry[sec_cam_idx];
if (opmode == SEC_CAM_CLEAR) {
sec_cam_entry->valid = INVALID;
sec_cam_entry->mac_id = 0;
sec_cam_entry->key_id = 0;
sec_cam_entry->key_type = 0;
sec_cam_entry->sec_cam_info->type = 0;
sec_cam_entry->sec_cam_info->ext_key = 0;
sec_cam_entry->sec_cam_info->spp_mode = 0;
for (i = 0; i < 3; i++)
sec_cam_entry->sec_cam_info->key[i] = 0;
} else if (opmode == SEC_CAM_BACKUP) {
if (!sec_cam_table_bk)
return MACSUCCESS;
sec_cam_bk_entry = adapter->hw_info->sec_cam_table_bk
->sec_cam_entry[sec_cam_idx];
// backup security entry in halmac
sec_cam_bk_entry->valid = sec_cam_entry->valid;
sec_cam_bk_entry->mac_id = sec_cam_entry->mac_id;
sec_cam_bk_entry->key_id = sec_cam_entry->key_id;
sec_cam_bk_entry->key_type = sec_cam_entry->key_type;
sec_cam_bk_entry->sec_cam_info->type =
sec_cam_entry->sec_cam_info->type;
sec_cam_bk_entry->sec_cam_info->ext_key =
sec_cam_entry->sec_cam_info->ext_key;
sec_cam_bk_entry->sec_cam_info->spp_mode =
sec_cam_entry->sec_cam_info->spp_mode;
for (i = 0; i < 4; i++)
sec_cam_bk_entry->sec_cam_info->key[i] =
sec_cam_entry->sec_cam_info->key[i];
} else {
if (!sec_cam_info) {
sec_cam_entry->valid = VALID;
sec_cam_entry->mac_id = mac_id;
sec_cam_entry->key_id = key_id;
sec_cam_entry->key_type = key_type;
sec_cam_entry->sec_cam_info->type = 0x0;
sec_cam_entry->sec_cam_info->ext_key = 0x0;
sec_cam_entry->sec_cam_info->spp_mode = 0x0;
for (i = 0; i < 4; i++)
sec_cam_entry->sec_cam_info->key[i] = 0x0;
} else {
sec_cam_entry->valid = VALID;
sec_cam_entry->mac_id = mac_id;
sec_cam_entry->key_id = key_id;
sec_cam_entry->key_type = key_type;
sec_cam_entry->sec_cam_info->type = sec_cam_info->type;
sec_cam_entry->sec_cam_info->ext_key =
sec_cam_info->ext_key;
sec_cam_entry->sec_cam_info->spp_mode =
sec_cam_info->spp_mode;
for (i = 0; i < 4; i++)
sec_cam_entry->sec_cam_info->key[i] =
sec_cam_info->key[i];
}
}
return MACSUCCESS;
}
u32 disconnect_flush_key(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role)
{
struct mac_ax_sec_cam_info *sec_cam_info = NULL;
u8 i, sec_ent_valid, mac_id, key_type, key_index;
u8 key_valid[7] = {0}, sec_cam_index[7] = {0}, sec_ent_keyid[7] = {0};
sec_ent_valid = role->info.a_info.sec_ent_valid;
mac_id = role->info.a_info.sec_ent_valid;
for (i = 0; i < 7; i++) {
key_valid[i] = sec_ent_valid % 2;
sec_ent_valid = sec_ent_valid >> 1;
sec_cam_index[i] = role->info.a_info.sec_ent[i];
sec_ent_keyid[i] = role->info.a_info.sec_ent_keyid[i];
}
key_type = SEC_CAM_KEY_TYPE_DEFAULT;
for (key_index = 0; key_index < 7; key_index++) {
if (key_valid[key_index] == VALID) {
m_security_cam_hal(adapter, sec_cam_info,
mac_id, sec_ent_keyid[key_index],
key_type, sec_cam_index[key_index],
SEC_CAM_CLEAR);
}
}
return MACSUCCESS;
}
u32 mac_sta_del_key(struct mac_ax_adapter *adapter,
u8 mac_id,
u8 key_id,
u8 key_type)
{
struct mac_ax_sec_cam_info sec_cam_info;
struct mac_role_tbl *role = NULL;
u8 sec_cam_idx = 0;
u32 sec_table[6] = {0}, ret = 0;
role = mac_role_srch(adapter, mac_id);
if (!role)
return MACNOROLE;
ret = delete_key_from_addr_cam(adapter, role, key_type,
key_id, &sec_cam_idx);
if (ret != MACSUCCESS)
return ret;
sec_cam_info.sec_cam_idx = sec_cam_idx;
sec_cam_info.offset = 0x00;
sec_cam_info.len = SEC_CAM_ENTRY_SIZE;
fill_sec_cam_info(adapter, &sec_cam_info,
(struct fwcmd_seccam_info *)sec_table, 1);
ret = (u8)mac_upd_sec_infotbl(adapter,
(struct fwcmd_seccam_info *)sec_table);
if (ret != MACSUCCESS)
return ret;
m_security_cam_hal(adapter, NULL,
mac_id, key_id, key_type,
sec_cam_idx, SEC_CAM_CLEAR);
return MACSUCCESS;
}
u32 mac_sta_add_key(struct mac_ax_adapter *adapter,
struct mac_ax_sec_cam_info *sec_cam_info,
u8 mac_id,
u8 key_id,
u8 key_type)
{
u8 sec_cam_idx = 0;
u32 sec_table[6] = {0}, ret = 0;
struct mac_role_tbl *role = NULL;
if (sec_cam_info->type > HW_SUPPORT_ENC_TYPE_NUM)
return MACWNGKEYTYPE;
role = mac_role_srch(adapter, mac_id);
if (!role)
return MACNOROLE;
if (sec_cam_info->offset != FORCE_KEYCAM_INDEX_TYPE) {
ret = decide_sec_cam_index(adapter, &sec_cam_idx);
if (ret != MACSUCCESS)
return ret;
} else {
sec_cam_idx = sec_cam_info->sec_cam_idx;
}
sec_cam_info->sec_cam_idx = sec_cam_idx;
sec_cam_info->offset = 0x00;
sec_cam_info->len = SEC_CAM_ENTRY_SIZE;
ret = insert_key_to_addr_cam(adapter, role, key_type, key_id,
sec_cam_info->sec_cam_idx);
if (ret != MACSUCCESS)
return ret;
fill_sec_cam_info(adapter, sec_cam_info,
(struct fwcmd_seccam_info *)sec_table, 0);
ret = (u8)mac_upd_sec_infotbl(adapter,
(struct fwcmd_seccam_info *)sec_table);
if (ret != MACSUCCESS)
return ret;
m_security_cam_hal(adapter, sec_cam_info,
mac_id, key_id, key_type,
sec_cam_idx, SEC_CAM_NORMAL);
return MACSUCCESS;
}
u32 mac_sta_keycam_backup(struct mac_ax_adapter *adapter, u8 op_mode)
{
u8 sec_cam_idx = 0, i = 0;
u32 ret = 0;
struct sec_cam_entry_t *s_entry = NULL;
struct mac_ax_sec_cam_info sec_cam_info;
struct sec_cam_table_t *sec_cam_table =
adapter->hw_info->sec_cam_table;
struct sec_cam_table_t *sec_cam_table_bk =
adapter->hw_info->sec_cam_table_bk;
if (op_mode > SEC_CAM_RESTORE)
return MACNOITEM;
if (op_mode == SEC_CAM_BACKUP) {
/*Initial backup sec cam table */
ret = sec_info_tbl_init(adapter, SEC_CAM_BACKUP);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret);
return ret;
}
/*Backup sec cam table valid entry*/
for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM;
sec_cam_idx++) {
/* Only search valid entry */
if (sec_cam_table->sec_cam_entry[sec_cam_idx]->valid ==
VALID) {
m_security_cam_hal(adapter, NULL, 0, 0, 0,
sec_cam_idx, SEC_CAM_BACKUP);
}
}
ret = free_sec_info_tbl(adapter, SEC_CAM_NORMAL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret);
return ret;
}
} else if (op_mode == SEC_CAM_RESTORE) {
ret = sec_info_tbl_init(adapter, SEC_CAM_NORMAL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret);
return ret;
}
/*Force sec cam table */
for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM;
sec_cam_idx++) {
s_entry = sec_cam_table_bk->sec_cam_entry[sec_cam_idx];
PLTFM_MSG_ERR("sec_cam_idx %d\n", sec_cam_idx);
/* Only search valid entry */
if (s_entry->valid == VALID) {
sec_cam_info.offset = FORCE_KEYCAM_INDEX_TYPE;
sec_cam_info.sec_cam_idx = sec_cam_idx;
sec_cam_info.type =
s_entry->sec_cam_info->type;
sec_cam_info.ext_key =
s_entry->sec_cam_info->ext_key;
sec_cam_info.spp_mode =
s_entry->sec_cam_info->spp_mode;
for (i = 0; i < 4; i++) {
sec_cam_info.key[i] =
s_entry->sec_cam_info->key[i];
}
mac_sta_add_key(adapter, &sec_cam_info,
s_entry->mac_id, s_entry->key_id,
s_entry->key_type);
}
}
/*Free backup sec cam table */
ret = free_sec_info_tbl(adapter, SEC_CAM_RESTORE);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sec info tbl backup %d\n", ret);
return ret;
}
} else {
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_sta_search_key_idx(struct mac_ax_adapter *adapter,
u8 mac_id, u8 key_id, u8 key_type)
{
u32 sec_cam_idx = 0;
struct sec_cam_entry_t *s_entry = NULL;
struct sec_cam_table_t *sec_cam_table =
adapter->hw_info->sec_cam_table;
if (!sec_cam_table)
return MACNOKEYINDEX;
/*Search SEC CAM Table */
for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM; sec_cam_idx++) {
/* Only search valid entry */
if (sec_cam_table->sec_cam_entry[sec_cam_idx]->valid == VALID) {
s_entry = sec_cam_table->sec_cam_entry[sec_cam_idx];
if (s_entry->mac_id != mac_id)
continue;
if (s_entry->key_id != key_id)
continue;
if (s_entry->key_type != key_type)
continue;
return sec_cam_idx;
}
}
return MACNOKEYINDEX;
}
u32 mac_sta_hw_security_support(struct mac_ax_adapter *adapter,
u8 hw_security_support_type, u8 enable)
{
u32 val32 = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (enable) {
case 1:
val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL);
switch (hw_security_support_type) {
case SEC_TX_ENC:
val32 |= B_AX_SEC_TX_ENC;
break;
case SEC_RX_ENC:
val32 |= B_AX_SEC_RX_DEC;
break;
case SEC_BC_ENC:
val32 |= B_AX_BC_DEC;
break;
case SEC_MC_ENC:
val32 |= B_AX_MC_DEC;
break;
case SEC_UC_MGNT_ENC:
val32 |= B_AX_UC_MGNT_DEC;
break;
case SEC_BMC_MGNT_ENC:
val32 |= B_AX_BMC_MGNT_DEC;
break;
default:
break;
}
MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32);
break;
case 0:
val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL);
switch (hw_security_support_type) {
case SEC_TX_ENC:
val32 &= ~B_AX_SEC_TX_ENC;
break;
case SEC_RX_ENC:
val32 &= ~B_AX_SEC_RX_DEC;
break;
case SEC_BC_ENC:
val32 &= ~B_AX_BC_DEC;
break;
case SEC_MC_ENC:
val32 &= ~B_AX_MC_DEC;
break;
case SEC_UC_MGNT_ENC:
val32 &= ~B_AX_UC_MGNT_DEC;
break;
case SEC_BMC_MGNT_ENC:
val32 &= ~B_AX_BMC_MGNT_DEC;
break;
default:
break;
}
MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32);
break;
default:
break;
}
return MACSUCCESS;
}
u8 check_key_type(u8 addr_cam_sec_mode, u8 key_index)
{
switch (addr_cam_sec_mode) {
case ADDR_CAM_SEC_MODE_ZERO:
if (key_index <= 6)
return SEC_CAM_KEY_TYPE_UNI;
break;
case ADDR_CAM_SEC_MODE_ONE:
if (key_index <= 6)
return SEC_CAM_KEY_TYPE_UNI;
break;
case ADDR_CAM_SEC_MODE_TWO:
if (key_index <= 1)
return SEC_CAM_KEY_TYPE_UNI;
else if (key_index >= 2 && key_index <= 4)
return SEC_CAM_KEY_TYPE_GROUP;
else if (key_index >= 5 && key_index <= 6)
return SEC_CAM_KEY_TYPE_BIP;
else
break;
break;
case ADDR_CAM_SEC_MODE_THREE:
if (key_index <= 1)
return SEC_CAM_KEY_TYPE_UNI;
else if (key_index >= 2 && key_index <= 5)
return SEC_CAM_KEY_TYPE_GROUP;
else if (key_index == 6)
return SEC_CAM_KEY_TYPE_BIP;
else
break;
break;
}
return MACKEYNOTEXT;
}
u32 refresh_security_cam_info(struct mac_ax_adapter *adapter,
u8 mac_id)
{
u32 addr_idx = 0, cam_address = 0;
u32 i = 0;
u8 key_valid[7] = {0}, key_cam_index[7] = {0}, sec_ent_keyid[7] = {0};
u8 macid = 0, hit_flag = VALID, key_id_sh = 0, key_cam_idx_sh = 0;
u8 key_valid_byte = 0, key_valid_byte_ori = 0, key_type = 0;
u8 key_index = 0, sec_ent_mode = 0, sec_cam_idx = 0;
u32 dword[10] = {0};
u8 addr_cam_size = get_addr_cam_size(adapter);
struct sec_cam_entry_t *s_entry = NULL;
struct sec_cam_table_t *sec_cam_table = adapter->hw_info->sec_cam_table;
struct mac_role_tbl *role = NULL;
/*read HW key in address cam */
for (addr_idx = 0; addr_idx < 0x80; addr_idx++) {
hit_flag = INVALID;
PLTFM_MSG_WARN("%s ind access macid %d start\n", __func__, mac_id);
cam_address = addr_idx * addr_cam_size;
for (i = 0; i < 10; i++)
dword[i] = mac_sram_dbg_read(adapter, cam_address,
ADDR_CAM_SEL);
PLTFM_MSG_WARN("%s ind access macid %d end\n", __func__, mac_id);
if ((dword[0] & ADDRCAM_VALID) == VALID) {
macid = (dword[6] & ADDRCAM_MACID_MSK);
if (macid == mac_id) {
sec_ent_mode = (dword[7] >> ADDRCAM_SEC_MODE_SH)
& ADDRCAM_SECMODE_MSK;
key_id_sh = ADDRCAM_SEC_ENT0_KEYID_SH;
for (i = 0; i < 7; i++) {
sec_ent_keyid[i] =
(dword[7] >> key_id_sh) &
ADDRCAM_KEYID_MSK;
key_id_sh += 2;
}
key_valid_byte =
dword[8] & ADDRCAM_KEY_VALID_MSK;
key_valid_byte_ori = key_valid_byte;
for (i = 0; i < 7; i++) {
key_valid[i] = key_valid_byte % 2;
key_valid_byte = key_valid_byte >> 1;
}
key_cam_idx_sh = 0;
for (i = 0; i < 3; i++) {
key_cam_idx_sh = (i + 1) * 8;
key_cam_index[i] =
(dword[8] >> key_cam_idx_sh) &
ADDRCAM_KEY_CAM_IDX_MSK;
}
key_cam_idx_sh = 0;
for (i = 3; i < 7; i++) {
key_cam_idx_sh = (i - 3) * 8;
key_cam_index[i] =
(dword[9] >> key_cam_idx_sh) &
ADDRCAM_KEY_CAM_IDX_MSK;
}
hit_flag = VALID;
break;
}
}
}
if (hit_flag == INVALID) {
PLTFM_MSG_TRACE("MACID : %d not exist\n", mac_id);
return MACNOROLE;
}
// clear halmac table
for (sec_cam_idx = 0; sec_cam_idx < SEC_CAM_ENTRY_NUM; sec_cam_idx++) {
// Only search valid entry
if (sec_cam_table->sec_cam_entry[sec_cam_idx]->valid == VALID) {
s_entry = sec_cam_table->sec_cam_entry[sec_cam_idx];
if (s_entry->mac_id == mac_id) {
m_security_cam_hal(adapter, NULL,
mac_id, DEFAULT_KEYID,
DEFAULT_KEYTYPE,
sec_cam_idx, SEC_CAM_CLEAR);
}
}
}
// insert halmac table
for (key_index = 0; key_index < 7; key_index++) {
if (key_valid[key_index] == VALID) {
key_type = check_key_type(sec_ent_mode, key_index);
m_security_cam_hal(adapter, NULL,
mac_id, sec_ent_keyid[key_index],
key_type, key_cam_index[key_index],
SEC_CAM_NORMAL);
}
}
// write back to address cam sec part
role = mac_role_srch(adapter, mac_id);
if (!role)
return MACNOROLE;
role->info.a_info.sec_ent_valid = key_valid_byte_ori;
for (i = 0; i < 7; i++) {
role->info.a_info.sec_ent_keyid[i] = sec_ent_keyid[i];
role->info.a_info.sec_ent[i] = key_cam_index[i];
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/security_cam.c
|
C
|
agpl-3.0
| 29,567
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_SEC_CAM_H_
#define _MAC_AX_SEC_CAM_H_
#include "../mac_def.h"
#include "role.h"
#include "fwcmd.h"
#include "addr_cam.h"
/*--------------------Define ----------------------------------------*/
#ifdef PHL_FEATURE_AP
#define SEC_CAM_ENTRY_NUM 0x80
#else
#define SEC_CAM_ENTRY_NUM 0x10
#endif
#define ADDRCAM_VALID BIT0
#define ADDRCAM_SEC_MODE_SH 16
#define ADDRCAM_SEC_ENT0_KEYID_SH 18
#define ADDRCAM_SEC_ENT0_KEYID_SH 18
#define ADDRCAM_KEYID_MSK 0x3
#define ADDRCAM_SECMODE_MSK 0x3
#define ADDRCAM_MACID_MSK 0xFF
#define ADDRCAM_KEY_VALID_MSK 0xFF
#define ADDRCAM_KEY_CAM_IDX_MSK 0xFF
#define ADDRCAM_VALID_BIT_OFFSET 0x00
#define ADDRCAM_MACID_OFFSET 0x18
#define ADDRCAM_SECMODE_OFFSET 0x1C
#define ADDRCAM_KEY_VALID_OFFSET 0x20
#define ADDRCAM_KEY_IDX_OFFSET 0x21
#define SEC_CAM_ENTRY_SIZE 0x20
#define ADDR_CAM_ENTRY_SIZE 0x40
#define MACNOKEYINDEX 0xFF
#define DEFAULT_KEYID 0x0
#define DEFAULT_KEYTYPE 0x0
/*--------------------DSecurity cam type declaration-----------------*/
/**
* @struct sec_cam_entry_t
* @brief sec_cam_entry_t
*
* @var sec_cam_entry_t::valid
* Please Place Description here.
* @var sec_cam_entry_t::mac_id
* Please Place Description here.
* @var sec_cam_entry_t::key_id
* Please Place Description here.
* @var sec_cam_entry_t::key_type
* Please Place Description here.
* @var sec_cam_entry_t::sec_cam_info
* Please Place Description here.
*/
struct sec_cam_entry_t {
u8 valid;
u8 mac_id;
u8 key_id;
u8 key_type;
struct mac_ax_sec_cam_info *sec_cam_info;
};
/**
* @struct sec_cam_table_t
* @brief sec_cam_table_t
*
* @var sec_cam_table_t::sec_cam_entry
* Please Place Description here.
* @var sec_cam_table_t::next_cam_storage_idx
* Please Place Description here.
*/
struct sec_cam_table_t {
struct sec_cam_entry_t *sec_cam_entry[128];
u8 next_cam_storage_idx;
};
/**
* @enum SEC_FUNCTION_TYPE
*
* @brief SEC_FUNCTION_TYPE
*
* @var SEC_FUNCTION_TYPE::SEC_TX_ENC
* Please Place Description here.
* @var SEC_FUNCTION_TYPE::SEC_RX_ENC
* Please Place Description here.
* @var SEC_FUNCTION_TYPE::SEC_BC_ENC
* Please Place Description here.
* @var SEC_FUNCTION_TYPE::SEC_MC_ENC
* Please Place Description here.
* @var SEC_FUNCTION_TYPE::SEC_UC_MGNT_ENC
* Please Place Description here.
* @var SEC_FUNCTION_TYPE::SEC_BMC_MGNT_ENC
* Please Place Description here.
*/
enum SEC_FUNCTION_TYPE {
SEC_TX_ENC = 0,
SEC_RX_ENC = 1,
SEC_BC_ENC = 2,
SEC_MC_ENC = 3,
SEC_UC_MGNT_ENC = 4,
SEC_BMC_MGNT_ENC = 5,
};
enum SEC_CAM_OP_MODE {
SEC_CAM_NORMAL = 0,
SEC_CAM_CLEAR = 1,
SEC_CAM_BACKUP = 2,
SEC_CAM_RESTORE = 3,
};
/*--------------------Funciton declaration----------------------------*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief disconnect_flush_key
*
* @param *adapter
* @param *role
* @return Please Place Description here.
* @retval u32
*/
u32 disconnect_flush_key(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief sec_info_tbl_init
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 sec_info_tbl_init(struct mac_ax_adapter *adapter, u8 op_mode);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief free_sec_info_tbl
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 free_sec_info_tbl(struct mac_ax_adapter *adapter, u8 op_mode);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief fill_sec_cam_info
*
* @param *adapter
* @param *s_info
* @param *sec_info
* @return Please Place Description here.
* @retval u32
*/
u32 fill_sec_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_sec_cam_info *s_info,
struct fwcmd_seccam_info *sec_info,
u8 op_mode);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief mac_sta_add_key
*
* @param *adapter
* @param *sec_cam_content
* @param mac_id
* @param key_id
* @param key_type
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sta_add_key(struct mac_ax_adapter *adapter,
struct mac_ax_sec_cam_info *sec_cam_content,
u8 mac_id,
u8 key_id,
u8 key_type);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief mac_sta_del_key
*
* @param *adapter
* @param mac_id
* @param key_id
* @param key_type
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sta_del_key(struct mac_ax_adapter *adapter,
u8 mac_id,
u8 key_id,
u8 key_type);
/**
* @}
* @}
*/
u32 mac_sta_keycam_backup(struct mac_ax_adapter *adapter, u8 op_mode);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief mac_sta_search_key_idx
*
* @param *adapter
* @param mac_id
* @param key_id
* @param key_type
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sta_search_key_idx(struct mac_ax_adapter *adapter,
u8 mac_id, u8 key_id, u8 key_type);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup Security
* @{
*/
/**
* @brief mac_sta_hw_security_support
*
* @param *adapter
* @param hw_security_support_type
* @param enable
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sta_hw_security_support(struct mac_ax_adapter *adapter,
u8 hw_security_support_type, u8 enable);
/**
* @}
* @}
*/
u32 refresh_security_cam_info(struct mac_ax_adapter *adapter,
u8 mac_id);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/security_cam.h
|
C
|
agpl-3.0
| 6,384
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "ser.h"
static void dump_err_status_dispatcher(struct mac_ax_adapter *adapter);
static void dump_err_status_dmac(struct mac_ax_adapter *adapter);
static void dump_err_status_cmac(struct mac_ax_adapter *adapter, u8 band);
u32 mac_trigger_cmac_err(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
u16 val16;
u32 ret;
ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val8 = MAC_REG_R8(R_AX_CMAC_FUNC_EN);
MAC_REG_W8(R_AX_CMAC_FUNC_EN, val8 & (~B_AX_TMAC_EN));
PLTFM_DELAY_MS(1);
MAC_REG_W8(R_AX_CMAC_FUNC_EN, val8);
val16 = MAC_REG_R16(R_AX_PTCL_IMR0) | B_AX_F2PCMD_EMPTY_ERR_INT_EN;
MAC_REG_W16(R_AX_PTCL_IMR0, val16);
MAC_REG_W16(R_AX_PTCL_IMR0, val16 & ~B_AX_F2PCMD_EMPTY_ERR_INT_EN);
return MACSUCCESS;
}
u32 mac_trigger_cmac1_err(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
u16 val16;
u32 ret;
ret = check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val8 = MAC_REG_R8(R_AX_CMAC_FUNC_EN_C1);
MAC_REG_W8(R_AX_CMAC_FUNC_EN_C1, val8 & (~B_AX_TMAC_EN));
PLTFM_DELAY_MS(1);
MAC_REG_W8(R_AX_CMAC_FUNC_EN_C1, val8);
val16 = MAC_REG_R16(R_AX_PTCL_IMR0_C1) | B_AX_F2PCMD_EMPTY_ERR_INT_EN;
MAC_REG_W16(R_AX_PTCL_IMR0_C1, val16);
MAC_REG_W16(R_AX_PTCL_IMR0_C1, val16 & ~B_AX_F2PCMD_EMPTY_ERR_INT_EN);
return MACSUCCESS;
}
u32 mac_trigger_dmac_err(struct mac_ax_adapter *adapter)
{
struct cpuio_buf_req_t buf_req;
struct cpuio_ctrl_t ctrl_para;
u32 ret;
// Use CPUIO to enqueue packet.
//WD
buf_req.len = 0x20;
ret = mac_dle_buf_req_wd(adapter, &buf_req);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]WDE DLE buf req\n");
return ret;
}
// Enqueue two pkt_id, but only has one pkt_id.
PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para));
ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
ctrl_para.start_pktid = buf_req.pktid;
ctrl_para.end_pktid = buf_req.pktid;
ctrl_para.pkt_num = 1;
ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
ctrl_para.dst_qid = 4;
ret = mac_set_cpuio_wd(adapter, &ctrl_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]WDE DLE enqueue to head\n");
return ret;
}
return MACSUCCESS;
}
u32 mac_dump_err_status(struct mac_ax_adapter *adapter,
enum mac_ax_err_info err)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
PLTFM_MSG_ERR("--->\n err=0x%x\n", err);
if (err == MAC_AX_ERR_L1_ERR_DMAC ||
err == MAC_AX_ERR_L0_PROMOTE_TO_L1 ||
err == MAC_AX_ERR_L0_ERR_CMAC0 ||
err == MAC_AX_ERR_L0_ERR_CMAC1) {
PLTFM_MSG_ERR("R_AX_SER_DBG_INFO =0x%08x\n",
MAC_REG_R32(R_AX_SER_DBG_INFO));
dump_err_status_dmac(adapter);
dump_err_status_cmac(adapter, MAC_AX_BAND_0);
dump_err_status_cmac(adapter, MAC_AX_BAND_1);
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
PLTFM_MSG_ERR("R_AX_DBG_ERR_FLAG=0x%08x\n",
MAC_REG_R32(R_AX_DBG_ERR_FLAG));
PLTFM_MSG_ERR("R_AX_LBC_WATCHDOG=0x%08x\n",
MAC_REG_R32(R_AX_LBC_WATCHDOG));
}
}
PLTFM_MSG_ERR("<---\n");
return MACSUCCESS;
}
u32 mac_set_err_status(struct mac_ax_adapter *adapter,
enum mac_ax_err_info err)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt = MAC_SET_ERR_DLY_CNT;
u32 ret = MACSUCCESS;
if (err > MAC_AX_SET_ERR_MAX) {
PLTFM_MSG_ERR("Bad set-err-status value\n");
return MACFUNCINPUT;
}
PLTFM_MUTEX_LOCK(&adapter->hw_info->err_set_lock);
while (--cnt) {
if (!MAC_REG_R32(R_AX_HALT_H2C_CTRL))
break;
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("FW does not receive previous msg\n");
ret = MACPOLLTO;
goto end;
}
if (err == MAC_AX_ERR_L1_DISABLE_EN)
adapter->sm.fw_rst = MAC_AX_FW_RESET_RECV_DONE;
MAC_REG_W32(R_AX_HALT_H2C, err);
MAC_REG_W32(R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_set_lock);
return ret;
}
u32 mac_get_err_status(struct mac_ax_adapter *adapter,
enum mac_ax_err_info *err)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt = MAC_SET_ERR_DLY_CNT;
u32 ret = MACSUCCESS;
u32 error_senario = 0;
PLTFM_MUTEX_LOCK(&adapter->hw_info->err_get_lock);
adapter->sm.l2_st = MAC_AX_L2_DIS;
while (--cnt) {
if (MAC_REG_R32(R_AX_HALT_C2H_CTRL))
break;
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("Polling FW err status fail\n");
ret = MACPOLLTO;
goto end;
}
*err = (enum mac_ax_err_info)MAC_REG_R32(R_AX_HALT_C2H);
MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0);
switch (*err) {
case MAC_AX_ERR_L1_ERR_DMAC:
case MAC_AX_ERR_L0_PROMOTE_TO_L1:
adapter->sm.fw_rst = MAC_AX_FW_RESET_RECV;
break;
case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE:
adapter->sm.fw_rst = MAC_AX_FW_RESET_PROCESS;
break;
case MAC_AX_ERR_L1_RESET_RECOVERY_DONE:
adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE;
break;
default:
break;
}
/* Decode the error status from halc2h */
error_senario = (*err) >> DBG_SENARIO_SH;
if (!(MAC_REG_R32(R_AX_UDM0) & (1 << B_AX_UDM0_DBG_MODE_SH))) {
if (error_senario == CPU_EXCEPTION)
*err = MAC_AX_ERR_CPU_EXCEPTION;
else if (error_senario == ASSERTION)
*err = MAC_AX_ERR_ASSERTION;
}
//3 3. Execute Recode Normal Debug Register
if (*err == MAC_AX_ERR_L0_ERR_CMAC0 ||
*err == MAC_AX_ERR_L0_ERR_CMAC1) {
pltfm_dbg_dump(adapter);
}
fw_st_dbg_dump(adapter);
mac_dump_err_status(adapter, *err);
if (*err == MAC_AX_ERR_L0_ERR_CMAC0 ||
*err == MAC_AX_ERR_L0_ERR_CMAC1) {
pltfm_dbg_dump(adapter);
}
//3 4. Execute Recode Share memory debug information
if (MAC_REG_R32(R_AX_UDM0) & (1 << B_AX_UDM0_DBG_MODE_SH)) {
/* if debug mode =1 , dump share buffer */
if (error_senario) {
*err = (enum mac_ax_err_info)MAC_AX_DUMP_SHAREBUFF_INDICATOR;
//notify phl to print share buffer
}
}
end:
adapter->sm.l2_st = MAC_AX_L2_EN;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_get_lock);
return ret;
}
u32 mac_lv1_rcvy(struct mac_ax_adapter *adapter, enum mac_ax_lv1_rcvy_step step)
{
u32 ret = MACSUCCESS;
#if MAC_AX_PCIE_SUPPORT
u8 val8;
#endif
switch (step) {
case MAC_AX_LV1_RCVY_STEP_1:
if (adapter->sm.fw_rst != MAC_AX_FW_RESET_RECV) {
PLTFM_MSG_ERR("The rst-flow state is wrong\n");
return MACPROCERR;
}
#if MAC_AX_PCIE_SUPPORT
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
val8 = 0;
ret = lv1rst_stop_dma_pcie(adapter, val8);
if (ret) {
PLTFM_MSG_ERR("lv1 rcvy pcie stop dma fail\n");
return ret;
}
}
#endif
#if MAC_AX_USB_SUPPORT
if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
ret = usb_flush_mode(adapter, MAC_AX_FUNC_EN);
if (ret) {
PLTFM_MSG_ERR("lv1 rcvy USB flush mode fail\n");
return ret;
}
PLTFM_DELAY_MS(30);
}
#endif
break;
case MAC_AX_LV1_RCVY_STEP_2:
if (adapter->sm.fw_rst != MAC_AX_FW_RESET_PROCESS) {
PLTFM_MSG_ERR("The rst-flow state is wrong\n");
return MACPROCERR;
}
#if MAC_AX_PCIE_SUPPORT
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
val8 = 0;
ret = lv1rst_start_dma_pcie(adapter, val8);
if (ret) {
PLTFM_MSG_ERR("lv1 rcvy pcie start dma fail\n");
return ret;
}
}
#endif
#if MAC_AX_USB_SUPPORT
if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
ret = 0;
ret = usb_flush_mode(adapter, MAC_AX_FUNC_DIS);
if (ret) {
PLTFM_MSG_ERR("lv1 rcvy USB norm mode fail\n");
return ret;
}
}
#endif
break;
default:
return MACLV1STEPERR;
}
return ret;
}
u32 mac_err_imr_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 v32_dmac, v32_cmac0, v32_cmac1;
u32 ret = MACSUCCESS;
u8 is_dbcc;
v32_dmac = sw != MAC_AX_FUNC_DIS ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS;
v32_cmac0 = sw != MAC_AX_FUNC_DIS ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS;
v32_cmac1 = sw != MAC_AX_FUNC_DIS ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS;
is_dbcc = is_curr_dbcc(adapter);
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)R_AX_DMAC_ERR_IMR, DMAC_ERR_IMR_MASK,
v32_dmac, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("dmac err imr w ofld fail\n");
return ret;
}
ret = MAC_REG_W_OFLD((u16)R_AX_CMAC_ERR_IMR, CMAC0_ERR_IMR_MASK,
v32_cmac0, (is_dbcc ? 0 : 1));
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("cmac0 err imr w ofld fail\n");
return ret;
}
if (is_dbcc) {
ret = MAC_REG_W_OFLD((u16)R_AX_CMAC_ERR_IMR_C1,
CMAC1_ERR_IMR_MASK,
v32_cmac1, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("cmac1 err imr w ofld fail\n");
return ret;
}
}
return ret;
}
#endif
MAC_REG_W32(R_AX_DMAC_ERR_IMR, v32_dmac);
MAC_REG_W32(R_AX_CMAC_ERR_IMR, v32_cmac0);
if (is_dbcc)
MAC_REG_W32(R_AX_CMAC_ERR_IMR_C1, v32_cmac1);
return ret;
}
static void dump_err_status_dispatcher(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
PLTFM_MSG_ERR("R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR));
PLTFM_MSG_ERR("R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_ISR));
PLTFM_MSG_ERR("R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR));
PLTFM_MSG_ERR("R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_ISR));
PLTFM_MSG_ERR("R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x ",
MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR));
PLTFM_MSG_ERR("R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_ISR));
}
static void dump_err_status_dmac(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 dmac_err;
dmac_err = MAC_REG_R32(R_AX_DMAC_ERR_ISR);
PLTFM_MSG_ERR("R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
PLTFM_MSG_ERR("R_AX_DMAC_FUNC_EN =0x%08x\n",
MAC_REG_R32(R_AX_DMAC_FUNC_EN));
PLTFM_MSG_ERR("R_AX_DMAC_CLK_EN =0x%08x\n",
MAC_REG_R32(R_AX_DMAC_CLK_EN));
if (dmac_err) {
PLTFM_MSG_ERR("R_AX_WDE_ERR_FLAG_CFG =0x%08x\n",
MAC_REG_R32(R_AX_WDE_ERR_FLAG_CFG));
PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
MAC_REG_R32(R_AX_PLE_ERR_FLAG_CFG));
}
if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_WDRLS_ERR_IMR =0x%08x\n",
MAC_REG_R32(R_AX_WDRLS_ERR_IMR));
PLTFM_MSG_ERR("R_AX_WDRLS_ERR_ISR =0x%08x\n",
MAC_REG_R32(R_AX_WDRLS_ERR_ISR));
PLTFM_MSG_ERR("R_AX_RPQ_RXBD_IDX =0x%08x\n",
MAC_REG_R32(R_AX_RPQ_RXBD_IDX));
}
if (dmac_err & B_AX_WSEC_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
MAC_REG_R32(R_AX_SEC_DEBUG));
PLTFM_MSG_ERR("SEC_local_Register 0x9D00 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_ENG_CTRL));
PLTFM_MSG_ERR("SEC_local_Register 0x9D04 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_MPDU_PROC));
PLTFM_MSG_ERR("SEC_local_Register 0x9D10 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_CAM_ACCESS));
PLTFM_MSG_ERR("SEC_local_Register 0x9D14 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_CAM_RDATA));
PLTFM_MSG_ERR("SEC_local_Register 0x9D18 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_CAM_WDATA));
PLTFM_MSG_ERR("SEC_local_Register 0x9D20 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_TX_DEBUG));
PLTFM_MSG_ERR("SEC_local_Register 0x9D24 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_RX_DEBUG));
PLTFM_MSG_ERR("SEC_local_Register 0x9D28 =0x%08x\n",
MAC_REG_R32(R_AX_SEC_TRX_PKT_CNT));
PLTFM_MSG_ERR("SEC_local_Register 0x9D2C =0x%08x\n",
MAC_REG_R32(R_AX_SEC_TRX_BLK_CNT));
}
if (dmac_err & B_AX_MPDU_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_MPDU_TX_ERR_IMR =0x%08x\n",
MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR));
PLTFM_MSG_ERR("R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR));
PLTFM_MSG_ERR("R_AX_MPDU_RX_ERR_IMR =0x%08x\n",
MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR));
PLTFM_MSG_ERR("R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
MAC_REG_R32(R_AX_MPDU_RX_ERR_ISR));
}
if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_STA_SCHEDULER_ERR_IMR =0x%08x\n",
MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR));
PLTFM_MSG_ERR("R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_ISR));
}
if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_WDE_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_WDE_ERR_IMR));
PLTFM_MSG_ERR("R_AX_WDE_ERR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_WDE_ERR_ISR));
PLTFM_MSG_ERR("R_AX_PLE_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_PLE_ERR_IMR));
PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR));
}
if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR));
PLTFM_MSG_ERR("R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
}
if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_WDE_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_WDE_ERR_IMR));
PLTFM_MSG_ERR("R_AX_WDE_ERR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_WDE_ERR_ISR));
PLTFM_MSG_ERR("R_AX_PLE_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_PLE_ERR_IMR));
PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR));
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_0=0x%08x\n",
MAC_REG_R32(R_AX_WD_CPUQ_OP_0));
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_1=0x%08x\n",
MAC_REG_R32(R_AX_WD_CPUQ_OP_1));
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_2=0x%08x\n",
MAC_REG_R32(R_AX_WD_CPUQ_OP_2));
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
MAC_REG_R32(R_AX_WD_CPUQ_OP_STATUS));
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_0=0x%08x\n",
MAC_REG_R32(R_AX_PL_CPUQ_OP_0));
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_1=0x%08x\n",
MAC_REG_R32(R_AX_PL_CPUQ_OP_1));
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_2=0x%08x\n",
MAC_REG_R32(R_AX_PL_CPUQ_OP_2));
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
MAC_REG_R32(R_AX_PL_CPUQ_OP_STATUS));
PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
MAC_REG_R32(R_AX_RXDMA_PKT_INFO_0));
PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
MAC_REG_R32(R_AX_RXDMA_PKT_INFO_1));
PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
MAC_REG_R32(R_AX_RXDMA_PKT_INFO_2));
dump_err_status_dispatcher(adapter);
}
if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_IMR =0x%08x\n",
MAC_REG_R32(R_AX_PKTIN_ERR_IMR));
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_ISR =0x%08x\n",
MAC_REG_R32(R_AX_PKTIN_ERR_ISR));
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_IMR =0x%08x ",
MAC_REG_R32(R_AX_PKTIN_ERR_IMR));
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_ISR =0x%08x\n",
MAC_REG_R32(R_AX_PKTIN_ERR_ISR));
}
if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
dump_err_status_dispatcher(adapter);
if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
PLTFM_MSG_ERR("R_AX_CPUIO_ERR_IMR=0x%08x\n",
MAC_REG_R32(R_AX_CPUIO_ERR_IMR));
PLTFM_MSG_ERR("R_AX_CPUIO_ERR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_CPUIO_ERR_ISR));
}
if (dmac_err & BIT(11)) {
PLTFM_MSG_ERR("R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR));
}
}
static void dump_err_status_cmac(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cmac_err;
u32 ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return;
PLTFM_MSG_ERR("CMAC Band =0x%02x\n", band);
cmac_err = MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CMAC_ERR_ISR :
R_AX_CMAC_ERR_ISR_C1);
PLTFM_MSG_ERR("R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
PLTFM_MSG_ERR("R_AX_CMAC_FUNC_EN =0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CMAC_FUNC_EN :
R_AX_CMAC_FUNC_EN_C1));
PLTFM_MSG_ERR("R_AX_CK_EN =0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CK_EN :
R_AX_CK_EN_C1));
if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
PLTFM_MSG_ERR("R_AX_SCHEDULE_ERR_IMR=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_SCHEDULE_ERR_IMR : R_AX_SCHEDULE_ERR_IMR_C1));
PLTFM_MSG_ERR("R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
MAC_REG_R16(band == MAC_AX_BAND_0 ?
R_AX_SCHEDULE_ERR_ISR : R_AX_SCHEDULE_ERR_ISR_C1));
}
if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
PLTFM_MSG_ERR("R_AX_PTCL_IMR0=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_PTCL_IMR0 : R_AX_PTCL_IMR0_C1));
PLTFM_MSG_ERR("R_AX_PTCL_ISR0=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_PTCL_ISR0 : R_AX_PTCL_ISR0_C1));
}
if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
PLTFM_MSG_ERR("R_AX_DLE_CTRL=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_DLE_CTRL : R_AX_DLE_CTRL_C1));
}
if (cmac_err & B_AX_PHYINTF_ERR_IND) {
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_IMR=0x%04x\n",
MAC_REG_R16(band == MAC_AX_BAND_0 ?
R_AX_PHYINFO_ERR_IMR : R_AX_PHYINFO_ERR_IMR_C1));
}
if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
PLTFM_MSG_ERR("R_AX_TXPWR_IMR=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_TXPWR_IMR : R_AX_TXPWR_IMR_C1));
PLTFM_MSG_ERR("R_AX_TXPWR_ISR=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_TXPWR_ISR : R_AX_TXPWR_ISR_C1));
}
if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
PLTFM_MSG_ERR("R_AX_DBGSEL_TRXPTCL=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_DBGSEL_TRXPTCL : R_AX_DBGSEL_TRXPTCL_C1));
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_ISR=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_PHYINFO_ERR_ISR : R_AX_PHYINFO_ERR_ISR_C1));
}
if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
PLTFM_MSG_ERR("R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_TMAC_ERR_IMR_ISR : R_AX_TMAC_ERR_IMR_ISR_C1));
PLTFM_MSG_ERR("R_AX_DBGSEL_TRXPTCL=0x%08x\n",
MAC_REG_R32(band == MAC_AX_BAND_0 ?
R_AX_DBGSEL_TRXPTCL : R_AX_DBGSEL_TRXPTCL_C1));
}
}
u32 mac_ser_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
enum mac_ax_err_info err_info;
u32 val32, ret, cnt;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) && is_cv(adapter, CAV)) {
PLTFM_MSG_WARN("[WARN]SER ctrl not support\n");
return MACSUCCESS;
}
if (sw == MAC_AX_FUNC_EN) {
err_info = MAC_AX_ERR_L1_RCVY_START_REQ;
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_SRT;
} else if (sw == MAC_AX_FUNC_DIS) {
err_info = MAC_AX_ERR_L1_RCVY_STOP_REQ;
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_STOP;
} else {
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
PLTFM_MSG_ERR("[ERR]SER ctrl input err %d\n", sw);
return MACFUNCINPUT;
}
ret = mac_set_err_status(adapter, err_info);
if (ret != MACSUCCESS) {
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
PLTFM_MSG_ERR("[ERR]set err for stop ser %d\n", ret);
return ret;
}
cnt = MAC_SET_ERR_DLY_CNT;
while (cnt) {
val32 = MAC_REG_R32(R_AX_HALT_H2C_CTRL);
if (!(val32 & B_AX_HALT_H2C_TRIGGER))
break;
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
cnt--;
}
if (!cnt) {
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
PLTFM_MSG_ERR("[ERR]FW not handle haltH2C req\n");
ret = MACPOLLTO;
return ret;
}
if (sw == MAC_AX_FUNC_EN)
return MACSUCCESS;
cnt = MAC_SER_STOP_DLY_CNT;
while (cnt) {
PLTFM_DELAY_US(MAC_SER_STOP_DLY_US);
val32 = MAC_REG_R32(R_AX_UDM0);
val32 = GET_FIELD(val32, FW_ST);
if (val32 != FW_ST_ERR_IN)
break;
cnt--;
}
if (!cnt) {
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
PLTFM_MSG_ERR("[ERR]stop ser polling FW ST timeout\n");
return MACPOLLTO;
}
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/ser.c
|
C
|
agpl-3.0
| 20,376
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_SER_H_
#define _MAC_AX_SER_H_
#include "../type.h"
#if MAC_AX_SDIO_SUPPORT
#include "_sdio.h"
#endif
#if MAC_AX_PCIE_SUPPORT
#include "_pcie.h"
#endif
#if MAC_AX_USB_SUPPORT
#include "_usb.h"
#endif
#define SER_ENABLE 0XFFFFFFFF
#define SER_DISABLE 0X00000000
#if defined(PHL_FEATURE_AP)
/*--------------------CMAC ERROR ----------------------------------------*/
/*--------------------CMAC DMA IMR --------------------------------------*/
// 0xC800
// bit[14]
#define CMAC_DMA_RXSTS_FSM_HANG_SER_EN SER_ENABLE
// bit[15]
#define CMAC_DMA_RXDATA_FSM_HANG_SER_EN SER_DISABLE
// bit[23]
#define CMAC_DMA_NO_RSVD_PAGE_SER_EN SER_DISABLE
// 0xC828
// bit[31]
#define CMAC_DMA_RXDATA_SUBFSM_HANG_SER_EN SER_ENABLE
/*-------------------- PTCL IMR -----------------------------------------*/
// 0xC6C0
// bit[0]
#define PTCL_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[8]
#define PTCL_F2PCMDRPT_FULL_DROP_SER_EN SER_DISABLE
// bit[9]
#define PTCL_TXRPT_FULL_DROP_SER_EN SER_DISABLE
// bit[10]
#define PTCL_D_PKTID_ERR_SER_EN SER_DISABLE
// bit[11]
#define PTCL_Q_PKTID_ERR_SER_EN SER_DISABLE
// bit[12]
#define PTCL_BCNQ_ORDER_ERR_SER_EN SER_DISABLE
// bit[14]
#define PTCL_TWTSP_QSEL_ERR_SER_EN SER_DISABLE
// bit[15]
#define PTCL_F2PCMD_EMPTY_ERR_SER_EN SER_DISABLE
// bit[23]
#define PTCL_TX_RECORD_PKTID_ERR_SER_EN SER_ENABLE
// bit[24]
#define PTCL_TX_SPF_U3_PKTID_ERR_SER_EN SER_DISABLE
// bit[25]
#define PTCL_TX_SPF_U2_PKTID_ERR_SER_EN SER_DISABLE
// bit[26]
#define PTCL_TX_SPF_U1_PKTID_ERR_SER_EN SER_DISABLE
// bit[27]
#define PTCL_TX_SPF_U0_PKTID_ERR_SER_EN SER_DISABLE
// bit[28]
#define PTCL_F2PCMD_USER_ALLC_ERR_SER_EN SER_ENABLE
// bit[29]
#define PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN SER_DISABLE
// bit[30]
#define PTCL_F2PCMD_RD_PKTID_ERR_SER_EN SER_DISABLE
// bit[31]
#define PTCL_F2PCMD_PKTID_ERR_SER_EN SER_DISABLE
/*-------------------- Scheduler IMR ------------------------------------*/
// 0xC3E8 : 0x00000000
// bit[0]
#define SCHEDULER_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[1]
#define SCHEDULER_SORT_NON_IDLE_ERR_SER_EN SER_DISABLE
/*-------------------- PHY INTF IMR --------------------------------------*/
// 0xCCFE : 0x0000
// bit[0]
#define PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[1]
#define PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[2]
#define PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[3]
#define PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[4]
#define PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[5]
#define PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
/*-------------------- RMAC IMR -----------------------------------------*/
// 0xCEF6
// bit[4]
#define RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[5]
#define RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[6]
#define RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[7]
#define RMAC_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[8]
#define RMAC_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[9]
#define RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[10]
#define RMAC_RX_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[11]
#define RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN SER_ENABLE
/*-------------------- TMAC IMR -----------------------------------------*/
// 0xCCEC
// bit[7]
#define TMAC_MACTX_TIME_ERR_SER_EN SER_ENABLE
// bit[8]
#define TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[9]
#define TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[10]
#define TMAC_TX_PLCP_INFO_ERR_SER_EN SER_ENABLE
#elif defined(PHL_FEATURE_STA)
/*--------------------CMAC ERROR ----------------------------------------*/
/*--------------------CMAC DMA IMR --------------------------------------*/
// 0xC800
// bit[14]
#define CMAC_DMA_RXSTS_FSM_HANG_SER_EN SER_ENABLE
// bit[15]
#define CMAC_DMA_RXDATA_FSM_HANG_SER_EN SER_DISABLE
// bit[23]
#define CMAC_DMA_NO_RSVD_PAGE_SER_EN SER_DISABLE
// 0xC828
// bit[31]
#define CMAC_DMA_RXDATA_SUBFSM_HANG_SER_EN SER_ENABLE
/*-------------------- PTCL IMR -----------------------------------------*/
// 0xC6C0
// bit[0]
#define PTCL_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[8]
#define PTCL_F2PCMDRPT_FULL_DROP_SER_EN SER_DISABLE
// bit[9]
#define PTCL_TXRPT_FULL_DROP_SER_EN SER_DISABLE
// bit[10]
#define PTCL_D_PKTID_ERR_SER_EN SER_DISABLE
// bit[11]
#define PTCL_Q_PKTID_ERR_SER_EN SER_DISABLE
// bit[12]
#define PTCL_BCNQ_ORDER_ERR_SER_EN SER_DISABLE
// bit[14]
#define PTCL_TWTSP_QSEL_ERR_SER_EN SER_DISABLE
// bit[15]
#define PTCL_F2PCMD_EMPTY_ERR_SER_EN SER_DISABLE
// bit[23]
#define PTCL_TX_RECORD_PKTID_ERR_SER_EN SER_ENABLE
// bit[24]
#define PTCL_TX_SPF_U3_PKTID_ERR_SER_EN SER_DISABLE
// bit[25]
#define PTCL_TX_SPF_U2_PKTID_ERR_SER_EN SER_DISABLE
// bit[26]
#define PTCL_TX_SPF_U1_PKTID_ERR_SER_EN SER_DISABLE
// bit[27]
#define PTCL_TX_SPF_U0_PKTID_ERR_SER_EN SER_DISABLE
// bit[28]
#define PTCL_F2PCMD_USER_ALLC_ERR_SER_EN SER_ENABLE
// bit[29]
#define PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN SER_DISABLE
// bit[30]
#define PTCL_F2PCMD_RD_PKTID_ERR_SER_EN SER_DISABLE
// bit[31]
#define PTCL_F2PCMD_PKTID_ERR_SER_EN SER_DISABLE
/*-------------------- Scheduler IMR ------------------------------------*/
// 0xC3E8 : 0x00000000
// bit[0]
#define SCHEDULER_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[1]
#define SCHEDULER_SORT_NON_IDLE_ERR_SER_EN SER_DISABLE
/*-------------------- PHY INTF IMR --------------------------------------*/
// 0xCCFE : 0x0000
// bit[0]
#define PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[1]
#define PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[2]
#define PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[3]
#define PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[4]
#define PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[5]
#define PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
/*-------------------- RMAC IMR -----------------------------------------*/
// 0xCEF6
// bit[4]
#define RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[5]
#define RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[6]
#define RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[7]
#define RMAC_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[8]
#define RMAC_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[9]
#define RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[10]
#define RMAC_RX_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[11]
#define RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN SER_ENABLE
/*-------------------- TMAC IMR -----------------------------------------*/
// 0xCCEC
// bit[7]
#define TMAC_MACTX_TIME_ERR_SER_EN SER_ENABLE
// bit[8]
#define TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[9]
#define TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[10]
#define TMAC_TX_PLCP_INFO_ERR_SER_EN SER_ENABLE
#else
/*--------------------CMAC ERROR ----------------------------------------*/
/*--------------------CMAC DMA IMR --------------------------------------*/
// 0xC800
// bit[14]
#define CMAC_DMA_RXSTS_FSM_HANG_SER_EN SER_ENABLE
// bit[15]
#define CMAC_DMA_RXDATA_FSM_HANG_SER_EN SER_DISABLE
// bit[23]
#define CMAC_DMA_NO_RSVD_PAGE_SER_EN SER_DISABLE
// 0xC828
// bit[31]
#define CMAC_DMA_RXDATA_SUBFSM_HANG_SER_EN SER_ENABLE
/*-------------------- PTCL IMR -----------------------------------------*/
// 0xC6C0
// bit[0]
#define PTCL_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[8]
#define PTCL_F2PCMDRPT_FULL_DROP_SER_EN SER_DISABLE
// bit[9]
#define PTCL_TXRPT_FULL_DROP_SER_EN SER_DISABLE
// bit[10]
#define PTCL_D_PKTID_ERR_SER_EN SER_DISABLE
// bit[11]
#define PTCL_Q_PKTID_ERR_SER_EN SER_DISABLE
// bit[12]
#define PTCL_BCNQ_ORDER_ERR_SER_EN SER_DISABLE
// bit[14]
#define PTCL_TWTSP_QSEL_ERR_SER_EN SER_DISABLE
// bit[15]
#define PTCL_F2PCMD_EMPTY_ERR_SER_EN SER_DISABLE
// bit[23]
#define PTCL_TX_RECORD_PKTID_ERR_SER_EN SER_ENABLE
// bit[24]
#define PTCL_TX_SPF_U3_PKTID_ERR_SER_EN SER_DISABLE
// bit[25]
#define PTCL_TX_SPF_U2_PKTID_ERR_SER_EN SER_DISABLE
// bit[26]
#define PTCL_TX_SPF_U1_PKTID_ERR_SER_EN SER_DISABLE
// bit[27]
#define PTCL_TX_SPF_U0_PKTID_ERR_SER_EN SER_DISABLE
// bit[28]
#define PTCL_F2PCMD_USER_ALLC_ERR_SER_EN SER_ENABLE
// bit[29]
#define PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN SER_DISABLE
// bit[30]
#define PTCL_F2PCMD_RD_PKTID_ERR_SER_EN SER_DISABLE
// bit[31]
#define PTCL_F2PCMD_PKTID_ERR_SER_EN SER_DISABLE
/*-------------------- Scheduler IMR ------------------------------------*/
// 0xC3E8 : 0x00000000
// bit[0]
#define SCHEDULER_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[1]
#define SCHEDULER_SORT_NON_IDLE_ERR_SER_EN SER_DISABLE
/*-------------------- PHY INTF IMR --------------------------------------*/
// 0xCCFE : 0x0000
// bit[0]
#define PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[1]
#define PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[2]
#define PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[3]
#define PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[4]
#define PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[5]
#define PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
/*-------------------- RMAC IMR -----------------------------------------*/
// 0xCEF6
// bit[4]
#define RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[5]
#define RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[6]
#define RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[7]
#define RMAC_CCA_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[8]
#define RMAC_DATA_ON_TIMEOUT_ERR_SER_EN SER_DISABLE
// bit[9]
#define RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[10]
#define RMAC_RX_FSM_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[11]
#define RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN SER_ENABLE
/*-------------------- TMAC IMR -----------------------------------------*/
// 0xCCEC
// bit[7]
#define TMAC_MACTX_TIME_ERR_SER_EN SER_ENABLE
// bit[8]
#define TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[9]
#define TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN SER_ENABLE
// bit[10]
#define TMAC_TX_PLCP_INFO_ERR_SER_EN SER_ENABLE
#endif
//WDRLS 0x9430
//bit[0]
#define DMAC_WDRLS_CTL_WDPKTID_ISNULL_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_WDRLS_CTL_PLPKTID_ISNULL_ERR_SER_EN SER_ENABLE
//bit[2]
#define DMAC_WDRLS_CTL_FRZTO_ERR_SER_EN SER_ENABLE
//bit[4]
#define DMAC_WDRLS_PLEBREQ_TO_ERR_SER_EN SER_DISABLE
//bit[5]
#define DMAC_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_SER_EN SER_ENABLE
//bit[8]
#define DMAC_WDRLS_RPT0_AGGNUM0_ERR_SER_EN SER_ENABLE
//bit[9]
#define DMAC_WDRLS_RPT0_FRZTO_ERR_SER_EN SER_ENABLE
//bit[12]
#define DMAC_WDRLS_RPT1_AGGNUM0_ERR_SER_EN SER_ENABLE
//bit[13]
#define DMAC_WDRLS_RPT1_FRZTO_ERR_SER_EN SER_ENABLE
//SEC_DEBUG 0x9D1C
//bit[3]
#define DMAC_IMR_ERROR SER_ENABLE
//MPDU_TX_ERR_IMR 0x9BF4
//bit[1]
#define DMAC_TX_GET_ERRPKTID_SER_EN SER_DISABLE
//bit[2]
#define DMAC_TX_NXT_ERRPKTID_SER_EN SER_DISABLE
//bit[3]
#define DMAC_TX_MPDU_SIZE_ZERO_SER_EN SER_DISABLE
//bit[4]
#define DMAC_TX_OFFSET_ERR_SER_EN SER_DISABLE
//bit[5]
#define DMAC_TX_HDR3_SIZE_ERR_SER_EN SER_DISABLE
//MPDU_RX_ERR_IMR 0x9CF4
//bit[0]
#define DMAC_GETPKTID_ERR_SER_EN SER_DISABLE
//bit[1]
#define DMAC_MHDRLEN_ERR_SER_EN SER_DISABLE
//bit[3]
#define DMAC_RPT_ERR_SER_EN SER_DISABLE
//STA_SCHEDULER_ERR_IMR 0x9EF0
//bit[0]
#define DMAC_SEARCH_HANG_TIMEOUT_SER_EN SER_ENABLE
//bit[1]
#define DMAC_RPT_HANG_TIMEOUT_SER_EN SER_ENABLE
//bit[2]
#define DMAC_PLE_B_PKTID_ERR_SER_EN SER_ENABLE
//TXPKTCTL_ERR_IMR_ISR 0x9F1C
//bit[0]
#define DMAC_TXPKTCTL_USRCTL_REINIT_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_TXPKTCTL_USRCTL_NOINIT_ERR_SER_EN SER_DISABLE
//bit[2]
#define DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_SER_EN SER_DISABLE
//bit[3]
#define DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_SER_EN SER_DISABLE
//bit[8]
#define DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_SER_EN SER_ENABLE
//bit[9]
#define DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_SER_EN SER_DISABLE
//TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
//bit[0]
#define DMAC_TXPKTCTL_USRCTL_REINIT_B1_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_TXPKTCTL_USRCTL_NOINIT_B1_ERR_SER_EN SER_ENABLE
//bit[2]
#define DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_B1_ERR_SER_EN SER_DISABLE
//bit[3]
#define DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_B1_ERR_SER_EN SER_DISABLE
//bit[8]
#define DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_B1_SER_EN SER_ENABLE
//bit[9]
#define DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_B1_SER_EN SER_ENABLE
//WDE_ERR_IMR 0x8C38
//bit[0]
#define DMAC_WDE_BUFREQ_QTAID_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_WDE_BUFREQ_UNAVAL_ERR_SER_EN SER_ENABLE
//bit[2]
#define DMAC_WDE_BUFRTN_INVLD_PKTID_ERR_SER_EN SER_ENABLE
//bit[3]
#define DMAC_WDE_BUFRTN_SIZE_ERR_SER_EN SER_ENABLE
//bit[4]
#define DMAC_WDE_BUFREQ_SRCHTAILPG_ERR_SER_EN SER_ENABLE
//bit[5]
#define DMAC_WDE_GETNPG_STRPG_ERR_SER_EN SER_ENABLE
//bit[6]
#define DMAC_WDE_GETNPG_PGOFST_ERR_SER_EN SER_ENABLE
//bit[7]
#define DMAC_WDE_BUFMGN_FRZTO_ERR_SER_EN SER_ENABLE
//bit[12]
#define DMAC_WDE_QUE_CMDTYPE_ERR_SER_EN SER_ENABLE
//bit[13]
#define DMAC_WDE_QUE_DSTQUEID_ERR_SER_EN SER_ENABLE
//bit[14]
#define DMAC_WDE_QUE_SRCQUEID_ERR_SER_EN SER_ENABLE
//bit[15]
#define DMAC_WDE_ENQ_PKTCNT_OVRF_ERR_SER_EN SER_ENABLE
//bit[16]
#define DMAC_WDE_ENQ_PKTCNT_NVAL_ERR_SER_EN SER_ENABLE
//bit[17]
#define DMAC_WDE_PREPKTLLT_AD_ERR_SER_EN SER_ENABLE
//bit[18]
#define DMAC_WDE_NXTPKTLL_AD_ERR_SER_EN SER_ENABLE
//bit[19]
#define DMAC_WDE_QUEMGN_FRZTO_ERR_SER_EN SER_ENABLE
//bit[24]
#define DMAC_WDE_DATCHN_ARBT_ERR_SER_EN SER_ENABLE
//bit[25]
#define DMAC_WDE_DATCHN_NULLPG_ERR_SER_EN SER_ENABLE
//bit[26]
#define DMAC_WDE_DATCHN_FRZTO_ERR_SER_EN SER_ENABLE
//PLE_ERR_IMR 0x9038
//bit[0]
#define DMAC_PLE_BUFREQ_QTAID_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_PLE_BUFREQ_UNAVAL_ERR_SER_EN SER_ENABLE
//bit[2]
#define DMAC_PLE_BUFRTN_INVLD_PKTID_ERR_SER_EN SER_ENABLE
//bit[3]
#define DMAC_PLE_BUFRTN_SIZE_ERR_SER_EN SER_ENABLE
//bit[4]
#define DMAC_PLE_BUFREQ_SRCHTAILPG_ERR_SER_EN SER_ENABLE
//bit[5]
#define DMAC_PLE_GETNPG_STRPG_ERR_SER_EN SER_DISABLE
//bit[6]
#define DMAC_PLE_GETNPG_PGOFST_ERR_SER_EN SER_ENABLE
//bit[7]
#define DMAC_PLE_BUFMGN_FRZTO_ERR_SER_EN SER_ENABLE
//bit[12]
#define DMAC_PLE_QUE_CMDTYPE_ERR_SER_EN SER_ENABLE
//bit[13]
#define DMAC_PLE_QUE_DSTQUEID_ERR_SER_EN SER_ENABLE
//bit[14]
#define DMAC_PLE_QUE_SRCQUEID_ERR_SER_EN SER_ENABLE
//bit[15]
#define DMAC_PLE_ENQ_PKTCNT_OVRF_ERR_SER_EN SER_ENABLE
//bit[16]
#define DMAC_PLE_ENQ_PKTCNT_NVAL_ERR_SER_EN SER_ENABLE
//bit[17]
#define DMAC_PLE_PREPKTLLT_AD_ERR_SER_EN SER_ENABLE
//bit[18]
#define DMAC_PLE_NXTPKTLL_AD_ERR_SER_EN SER_ENABLE
//bit[19]
#define DMAC_PLE_QUEMGN_FRZTO_ERR_SER_EN SER_ENABLE
//bit[24]
#define DMAC_PLE_DATCHN_ARBT_ERR_SER_EN SER_ENABLE
//bit[25]
#define DMAC_PLE_DATCHN_NULLPG_ERR_SER_EN SER_ENABLE
//bit[26]
#define DMAC_PLE_DATCHN_FRZTO_ERR_SER_EN SER_ENABLE
//PKTIN_ERR_IMR 0x9A20
//bit[0]
#define DMAC_PKTIN_GETPKTID_ERR_SER_EN SER_ENABLE
//HOST_DISPATCHER_ERR_IMR 0x8850
//bit[0]
#define DMAC_HDT_CHANNEL_DIFF_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_HDT_CHANNEL_ID_ERR_SER_EN SER_DISABLE
//bit[2]
#define DMAC_HDT_PKT_FAIL_DBG_SER_EN SER_DISABLE
//bit[3]
#define DMAC_HDT_PERMU_OVERFLOW_SER_EN SER_DISABLE
//bit[4]
#define DMAC_HDT_PERMU_UNDERFLOW_SER_EN SER_DISABLE
//bit[5]
#define DMAC_HDT_PAYLOAD_OVERFLOW_SER_EN SER_ENABLE
//bit[6]
#define DMAC_HDT_PAYLOAD_UNDERFLOW_SER_EN SER_ENABLE
//bit[7]
#define DMAC_HDT_OFFSET_UNMATCH_SER_EN SER_DISABLE
//bit[8]
#define DMAC_HDT_CHANNEL_DMA_ERR_SER_EN SER_ENABLE
//bit[9]
#define DMAC_HDT_WD_CHK_ERR_SER_EN SER_DISABLE
//bit[10]
#define DMAC_HDT_PRE_COST_ERR_SER_EN SER_DISABLE
//bit[11]
#define DMAC_HDT_TXPKTSIZE_ERR_SER_EN SER_DISABLE
//bit[12]
#define DMAC_HDT_TCP_CHK_ERR_SER_EN SER_DISABLE
//bit[13]
#define DMAC_HDT_TX_WRITE_OVERFLOW_SER_EN SER_DISABLE
//bit[14]
#define DMAC_HDT_TX_WRITE_UNDERFLOW_SER_EN SER_DISABLE
//bit[15]
#define DMAC_HDT_PLD_CMD_OVERLOW_SER_EN SER_DISABLE
//bit[16]
#define DMAC_HDT_PLD_CMD_UNDERFLOW_SER_EN SER_DISABLE
//bit[17]
#define DMAC_HDT_FLOW_CTRL_ERR_SER_EN SER_DISABLE
//bit[18]
#define DMAC_HDT_NULLPKT_ERR_SER_EN SER_DISABLE
//bit[19]
#define DMAC_HDT_BURST_NUM_ERR_SER_EN SER_DISABLE
//bit[24]
#define DMAC_HDT_RXAGG_CFG_ERR_SER_EN SER_DISABLE
//bit[25]
#define DMAC_HDT_SHIFT_EN_ERR_SER_EN SER_DISABLE
//bit[26]
#define DMAC_HDT_TOTAL_LEN_ERR_SER_EN SER_ENABLE
//bit[27]
#define DMAC_HDT_DMA_PROCESS_ERR_SER_EN SER_ENABLE
//bit[28]
#define DMAC_HDT_SHIFT_DMA_CFG_ERR_SER_EN SER_DISABLE
//bit[29]
#define DMAC_HDT_CHKSUM_FSM_ERR_SER_EN SER_DISABLE
//bit[30]
#define DMAC_HDT_RX_WRITE_OVERFLOW_SER_EN SER_DISABLE
//bit[31]
#define DMAC_HDT_RX_WRITE_UNDERFLOW_SER_EN SER_DISABLE
//CPU_DISPATCHER_ERR_IMR 0x8854
//bit[0]
#define DMAC_CPU_CHANNEL_DIFF_ERR_SER_EN SER_DISABLE
//bit[1]
#define DMAC_CPU_PKT_FAIL_DBG_SER_EN SER_ENABLE
//bit[2]
#define DMAC_CPU_CHANNEL_ID_ERR_SER_EN SER_DISABLE
//bit[3]
#define DMAC_CPU_PERMU_OVERFLOW_SER_EN SER_DISABLE
//bit[4]
#define DMAC_CPU_PERMU_UNDERFLOW_SER_EN SER_DISABLE
//bit[5]
#define DMAC_CPU_PAYLOAD_OVERFLOW_SER_EN SER_ENABLE
//bit[6]
#define DMAC_CPU_PAYLOAD_UNDERFLOW_SER_EN SER_ENABLE
//bit[7]
#define DMAC_CPU_PAYLOAD_CHKSUM_ERR_SER_EN SER_DISABLE
//bit[8]
#define DMAC_CPU_OFFSET_UNMATCH_SER_EN SER_DISABLE
//bit[9]
#define DMAC_CPU_CHANNEL_DMA_ERR_SER_EN SER_DISABLE
//bit[10]
#define DMAC_CPU_WD_CHK_ERR_SER_EN SER_DISABLE
//bit[11]
#define DMAC_CPU_PRE_COST_ERR_SER_EN SER_DISABLE
//bit[12]
#define DMAC_CPU_PLD_CMD_OVERLOW_SER_EN SER_DISABLE
//bit[13]
#define DMAC_CPU_PLD_CMD_UNDERFLOW_SER_EN SER_DISABLE
//bit[14]
#define DMAC_CPU_F2P_QSEL_ERR_SER_EN SER_DISABLE
//bit[15]
#define DMAC_CPU_F2P_SEQ_ERR_SER_EN SER_DISABLE
//bit[16]
#define DMAC_CPU_FLOW_CTRL_ERR_SER_EN SER_DISABLE
//bit[17]
#define DMAC_CPU_NULLPKT_ERR_SER_EN SER_DISABLE
//bit[18]
#define DMAC_CPU_BURST_NUM_ERR_SER_EN SER_DISABLE
//bit[24]
#define DMAC_CPU_RXAGG_CFG_ERR_SER_EN SER_DISABLE
//bit[25]
#define DMAC_CPU_SHIFT_EN_ERR_SER_EN SER_DISABLE
//bit[26]
#define DMAC_CPU_TOTAL_LEN_ERR_SER_EN SER_ENABLE
//bit[27]
#define DMAC_CPU_DMA_PROCESS_ERR_SER_EN SER_DISABLE
//bit[28]
#define DMAC_CPU_SHIFT_DMA_CFG_ERR_SER_EN SER_DISABLE
//bit[29]
#define DMAC_CPU_CHKSUM_FSM_ERR_SER_EN SER_DISABLE
//OTHER_DISPATCHER_ERR_IMR 0x8858
//bit[0]
#define DMAC_WDE_FLOW_CTRL_ERR_SER_EN SER_DISABLE
//bit[1]
#define DMAC_WDE_NULL_PKT_ERR_SER_EN SER_DISABLE
//bit[2]
#define DMAC_WDE_BURST_NUM_ERR_SER_EN SER_DISABLE
//bit[3]
#define DMAC_WDE_RESP_ERR_SER_EN SER_DISABLE
//bit[4]
#define DMAC_WDE_OUTPUT_ERR_SER_EN SER_DISABLE
//bit[8]
#define DMAC_PLE_FLOW_CTRL_ERR_SER_EN SER_DISABLE
//bit[9]
#define DMAC_PLE_NULL_PKT_ERR_SER_EN SER_DISABLE
//bit[10]
#define DMAC_PLE_BURST_NUM_ERR_SER_EN SER_DISABLE
//bit[11]
#define DMAC_PLE_RESP_ERR_SER_EN SER_DISABLE
//bit[12]
#define DMAC_PLE_OUTPUT_ERR_SER_EN SER_DISABLE
//bit[16]
#define DMAC_CPU_ADDR_INFO_LEN_ZERO_ERR_SER_EN SER_DISABLE
//bit[17]
#define DMAC_HOST_ADDR_INFO_LEN_ZERO_ERR_SER_EN SER_DISABLE
//bit[24]
#define DMAC_OTHER_STF_CMD_OVERFLOW_SER_EN SER_DISABLE
//bit[25]
#define DMAC_OTHER_STF_CMD_UNDERFLOW_SER_EN SER_DISABLE
//bit[26]
#define DMAC_OTHER_STF_WRFF_OVERFLOW_SER_EN SER_DISABLE
//bit[27]
#define DMAC_OTHER_STF_WRFF_UNDERFLOW_SER_EN SER_DISABLE
//bit[28]
#define DMAC_OTHER_STF_WROQT_OVERFLOW_SER_EN SER_DISABLE
//bit[29]
#define DMAC_OTHER_STF_WROQT_UNDERFLOW_SER_EN SER_DISABLE
//CPUIO_ERR_IMR 0x9840
//bit[0]
#define DMAC_WDEBUF_OP_ERR_SER_EN SER_ENABLE
//bit[4]
#define DMAC_WDEQUE_OP_ERR_SER_EN SER_ENABLE
//bit[8]
#define DMAC_PLEBUF_OP_ERR_SER_EN SER_ENABLE
//bit[12]
#define DMAC_PLEQUE_OP_ERR_SER_EN SER_ENABLE
//BBRPT_COM_ERR_IMR_ISR 0x960C
//bit[0]
#define DMAC_BBRPT_COM_NULL_PLPKTID_ERR_SER_EN SER_ENABLE
//BBRPT_CHINFO_ERR_IMR_ISR 0x962C
//bit[0]
#define DMAC_BBPRT_CHIF_BB_TO_ERR_SER_EN SER_ENABLE
//bit[1]
#define DMAC_BBPRT_CHIF_OVF_ERR_SER_EN SER_ENABLE
//bit[2]
#define DMAC_BBPRT_CHIF_BOVF_ERR_SER_EN SER_ENABLE
//bit[3]
#define DMAC_BBPRT_CHIF_HDRL_ERR_SER_EN SER_ENABLE
//bit[4]
#define DMAC_BBPRT_CHIF_LEFT1_ERR_SER_EN SER_ENABLE
//bit[5]
#define DMAC_BBPRT_CHIF_LEFT2_ERR_SER_EN SER_ENABLE
//bit[6]
#define DMAC_BBPRT_CHIF_NULL_ERR_SER_EN SER_ENABLE
//bit[7]
#define DMAC_BBPRT_CHIF_TO_ERR_SER_EN SER_ENABLE
//BBRPT_DFS_ERR_IMR_ISR 0x963C
//bit[0]
#define DMAC_BBRPT_DFS_TO_ERR_SER_EN SER_ENABLE
//LA_ERRFLAG 0x966C
//bit[0]
#define DMAC_LA_IMR_DATA_LOSS_ERR SER_ENABLE
/*--------------------Define -------------------------------------------*/
#define MAC_SET_ERR_DLY_CNT 200
#define MAC_SET_ERR_DLY_US 50
#define DMAC_ERR_IMR_MASK 0xFFFFFFFF
#define DMAC_ERR_IMR_EN 0xFFFFFFFF
#define CMAC0_ERR_IMR_MASK 0xFFFFFFFF
#define CMAC0_ERR_IMR_EN 0xFFFFFFFF
#define CMAC1_ERR_IMR_MASK 0xFFFFFFFF
#define CMAC1_ERR_IMR_EN 0xFFFFFFFF
#define DMAC_ERR_IMR_DIS 0
#define CMAC0_ERR_IMR_DIS 0
#define CMAC1_ERR_IMR_DIS 0
#define FW_ST_MSK 0xFFFF
#define FW_ST_SH 8
#define FW_ST_ERR_IN 0x11
#define MAC_SER_STOP_DLY_CNT 200
#define MAC_SER_STOP_DLY_US 50
/*--------------------Define Enum---------------------------------------*/
enum WCPU_ERR_SCENARIO {
RXI300_ERROR = 1,
CPU_EXCEPTION = 2,
ASSERTION = 3,
WDT_ALARM = 4,
};
/*--------------------Define MACRO--------------------------------------*/
/*--------------------Define Struct-------------------------------------*/
/*--------------------Function declaration------------------------------*/
u32 mac_trigger_cmac_err(struct mac_ax_adapter *adapter);
u32 mac_trigger_cmac1_err(struct mac_ax_adapter *adapter);
u32 mac_trigger_dmac_err(struct mac_ax_adapter *adapter);
u32 mac_dump_err_status(struct mac_ax_adapter *adapter,
enum mac_ax_err_info err);
u32 mac_set_err_status(struct mac_ax_adapter *adapter,
enum mac_ax_err_info err);
u32 mac_get_err_status(struct mac_ax_adapter *adapter,
enum mac_ax_err_info *err);
u32 mac_lv1_rcvy(struct mac_ax_adapter *adapter,
enum mac_ax_lv1_rcvy_step step);
u32 mac_err_imr_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw);
u32 mac_ser_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/ser.h
|
C
|
agpl-3.0
| 22,481
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "sounding.h"
u32 mac_get_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band,
u8 csi_buffer_id)
{
u32 val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (csi_buffer_id > CSI_MAX_BUFFER_IDX)
return MACCSIBUFIDERR;
val32 = MAC_REG_R32((band ? R_AX_BFMER_CSI_BUFF_IDX0_C1 :
R_AX_BFMER_CSI_BUFF_IDX0) + CSI_SH * csi_buffer_id);
return val32;
}
u32 mac_set_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band,
u8 macid, u16 csi_buffer_id, u16 buffer_idx)
{
u32 val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FW_REG_OFLD
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (csi_buffer_id > CSI_MAX_BUFFER_IDX)
return MACCSIBUFIDERR;
cr = (band ? R_AX_BFMER_CSI_BUFF_IDX0_C1 :
R_AX_BFMER_CSI_BUFF_IDX0) + (CSI_SH * csi_buffer_id);
val32 = (buffer_idx & B_AX_MER_TXBF_CSI_BUFF_IDX0_MSK)
<< B_AX_MER_SND_CSI_BUFF_IDX0_SH |
(macid & B_AX_MER_CSI_BUFF_MACID_IDX0_MSK);
ret = MAC_REG_W32_OFLD(cr, val32, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (csi_buffer_id > CSI_MAX_BUFFER_IDX)
return MACCSIBUFIDERR;
val32 = (buffer_idx & B_AX_MER_TXBF_CSI_BUFF_IDX0_MSK)
<< B_AX_MER_SND_CSI_BUFF_IDX0_SH |
(macid & B_AX_MER_CSI_BUFF_MACID_IDX0_MSK);
MAC_REG_W32((band ? R_AX_BFMER_CSI_BUFF_IDX0_C1 :
R_AX_BFMER_CSI_BUFF_IDX0) + CSI_SH * csi_buffer_id, val32);
return MACSUCCESS;
}
u32 mac_get_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 index)
{
u32 va32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (index > SOUNDING_STS_MAX_IDX)
return MACSNDSTSIDERR;
va32 = MAC_REG_R16((band ? R_AX_BFMER_ASSOCIATED_SU0_C1 :
R_AX_BFMER_ASSOCIATED_SU0) + SND_SH * index);
return va32;
}
u32 mac_set_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 macid,
u8 index)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
#if MAC_AX_FW_REG_OFLD
u16 cr, val16;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (index > SOUNDING_STS_MAX_IDX)
return MACSNDSTSIDERR;
cr = (band ? R_AX_BFMER_ASSOCIATED_SU0_C1 :
R_AX_BFMER_ASSOCIATED_SU0) + (SND_SH * index);
val16 = B_AX_MER_SU_BFMEE0_EN | macid;
ret = MAC_REG_W16_OFLD(cr, val16, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (index > SOUNDING_STS_MAX_IDX)
return MACSNDSTSIDERR;
MAC_REG_W16((band ? R_AX_BFMER_ASSOCIATED_SU0_C1 :
R_AX_BFMER_ASSOCIATED_SU0) + SND_SH * index,
B_AX_MER_SU_BFMEE0_EN | macid);
return MACSUCCESS;
}
u32 mac_init_snd_mer(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
#if MAC_AX_FW_REG_OFLD
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cr = band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0;
val32 = B_AX_BFMER_NDP_BFEN;
val32 |= HT_PAYLOAD_OFFSET << B_AX_BFMER_HT_CSI_OFFSET_SH;
val32 |= VHT_PAYLOAD_OFFSET << B_AX_BFMER_VHT_CSI_OFFSET_SH;
val32 |= HE_PAYLOAD_OFFSET << B_AX_BFMER_HE_CSI_OFFSET_SH;
ret = MAC_REG_W32_OFLD(cr, val32, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32 = B_AX_BFMER_NDP_BFEN;
val32 |= HT_PAYLOAD_OFFSET << B_AX_BFMER_HT_CSI_OFFSET_SH;
val32 |= VHT_PAYLOAD_OFFSET << B_AX_BFMER_VHT_CSI_OFFSET_SH;
val32 |= HE_PAYLOAD_OFFSET << B_AX_BFMER_HE_CSI_OFFSET_SH;
MAC_REG_W32(band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0, val32);
return MACSUCCESS;
}
u32 mac_init_snd_mee(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
#if MAC_AX_FW_REG_OFLD
u32 mask;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cr = band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 : R_AX_TRXPTCL_RESP_CSI_RRSC;
val32 = CSI_RRSC_BMAP;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = band ? R_AX_BFMEE_RESP_OPTION_C1 : R_AX_BFMEE_RESP_OPTION;
val32 = (BFRP_RX_STANDBY_TIMER << B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_SH);
val32 |= (NDP_RX_STANDBY_TIMER << B_AX_BFMEE_NDP_RX_STANDBY_TIMER_SH);
val32 |= (B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
B_AX_BFMEE_HE_NDPA_EN);
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
cr = band ? R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 :
R_AX_TRXPTCL_ERROR_INDICA_MASK;
mask = B_AX_RMAC_CSI;
ret = write_mac_reg_ofld(adapter, cr, mask, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
}
cr = band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0;
val32 = (B_AX_BFMEE_BFPARAM_SEL | B_AX_BFMEE_USE_NSTS |
B_AX_BFMEE_CSI_GID_SEL | B_AX_BFMEE_CSI_FORCE_RETE_EN);
ret = MAC_REG_W32_OFLD(cr, val32, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
/*AP mode set tx gid to 63*/
/*STA mode set tx gid to 0(default)*/
val32 = MAC_REG_R32(band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0);
val32 |= B_AX_BFMER_NDP_BFEN;
MAC_REG_W32(band ? R_AX_BFMER_CTRL_0_C1 : R_AX_BFMER_CTRL_0, val32);
MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 :
R_AX_TRXPTCL_RESP_CSI_RRSC, CSI_RRSC_BMAP);
val32 = (BFRP_RX_STANDBY_TIMER << B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_SH);
val32 |= (NDP_RX_STANDBY_TIMER << B_AX_BFMEE_NDP_RX_STANDBY_TIMER_SH);
val32 |= (B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
B_AX_BFMEE_HE_NDPA_EN);
MAC_REG_W32(band ? R_AX_BFMEE_RESP_OPTION_C1 :
R_AX_BFMEE_RESP_OPTION, val32);
val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0);
val32 |= (B_AX_BFMEE_BFPARAM_SEL | B_AX_BFMEE_USE_NSTS |
B_AX_BFMEE_CSI_GID_SEL | B_AX_BFMEE_CSI_FORCE_RETE_EN);
MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 :
R_AX_TRXPTCL_ERROR_INDICA_MASK);
val32 &= (~B_AX_RMAC_CSI);
MAC_REG_W32(band ? R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 :
R_AX_TRXPTCL_ERROR_INDICA_MASK, val32);
}
return MACSUCCESS;
}
u32 mac_csi_force_rate(struct mac_ax_adapter *adapter, u8 band, u8 ht_rate,
u8 vht_rate, u8 he_rate)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
#if MAC_AX_FW_REG_OFLD
u32 mask;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cr = band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : R_AX_TRXPTCL_RESP_CSI_CTRL_0;
mask = B_AX_BFMEE_CSI_FORCE_RETE_EN;
ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
mask = B_AX_BFMEE_BFPARAM_SEL;
ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = band ? R_AX_TRXPTCL_RESP_CSI_RATE_C1 : R_AX_TRXPTCL_RESP_CSI_RATE;
mask |= B_AX_BFMEE_HT_CSI_RATE_MSK;
mask |= B_AX_BFMEE_VHT_CSI_RATE_MSK << B_AX_BFMEE_VHT_CSI_RATE_SH;
mask |= B_AX_BFMEE_HE_CSI_RATE_MSK << B_AX_BFMEE_HE_CSI_RATE_SH;
val32 = ((u32)ht_rate | ((u32)vht_rate << B_AX_BFMEE_VHT_CSI_RATE_SH) |
((u32)he_rate << B_AX_BFMEE_HE_CSI_RATE_SH));
ret = write_mac_reg_ofld(adapter, cr, mask, val32, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0);
val32 |= B_AX_BFMEE_CSI_FORCE_RETE_EN | B_AX_BFMEE_BFPARAM_SEL;
MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32);
val32 = ((u32)ht_rate | ((u32)vht_rate << B_AX_BFMEE_VHT_CSI_RATE_SH) |
((u32)he_rate << B_AX_BFMEE_HE_CSI_RATE_SH));
MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_RATE_C1 :
R_AX_TRXPTCL_RESP_CSI_RATE, val32);
return MACSUCCESS;
}
u32 mac_csi_rrsc(struct mac_ax_adapter *adapter, u8 band, u32 rrsc)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
#if MAC_AX_FW_REG_OFLD
u32 mask;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cr = band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 : R_AX_TRXPTCL_RESP_CSI_CTRL_0;
mask = B_AX_BFMEE_CSI_FORCE_RETE_EN;
ret = write_mac_reg_ofld(adapter, cr, mask, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
mask = B_AX_BFMEE_BFPARAM_SEL;
ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 : R_AX_TRXPTCL_RESP_CSI_RRSC;
val32 = rrsc;
ret = MAC_REG_W32_OFLD(cr, val32, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32 = MAC_REG_R32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0);
val32 |= B_AX_BFMEE_BFPARAM_SEL;
val32 &= (~B_AX_BFMEE_CSI_FORCE_RETE_EN);
MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32);
MAC_REG_W32(band ? R_AX_TRXPTCL_RESP_CSI_RRSC_C1 :
R_AX_TRXPTCL_RESP_CSI_RRSC, rrsc);
return MACSUCCESS;
}
u32 mac_set_mu_table(struct mac_ax_adapter *adapter,
struct mac_mu_table *mu_table)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FW_REG_OFLD
u32 val32, ret;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
cr = R_AX_SS_MU_CTRL;
val32 = mu_table->mu_score_tbl_ctrl;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = R_AX_SS_MU_TBL_0;
val32 = mu_table->mu_score_tbl_0;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = R_AX_SS_MU_TBL_1;
val32 = mu_table->mu_score_tbl_1;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = R_AX_SS_MU_TBL_2;
val32 = mu_table->mu_score_tbl_2;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = R_AX_SS_MU_TBL_3;
val32 = mu_table->mu_score_tbl_3;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = R_AX_SS_MU_TBL_4;
val32 = mu_table->mu_score_tbl_4;
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = R_AX_SS_MU_TBL_5;
val32 = mu_table->mu_score_tbl_5;
ret = MAC_REG_W32_OFLD(cr, val32, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
MAC_REG_W32(R_AX_SS_MU_CTRL, mu_table->mu_score_tbl_ctrl);
MAC_REG_W32(R_AX_SS_MU_TBL_0, mu_table->mu_score_tbl_0);
MAC_REG_W32(R_AX_SS_MU_TBL_1, mu_table->mu_score_tbl_1);
MAC_REG_W32(R_AX_SS_MU_TBL_2, mu_table->mu_score_tbl_2);
MAC_REG_W32(R_AX_SS_MU_TBL_3, mu_table->mu_score_tbl_3);
MAC_REG_W32(R_AX_SS_MU_TBL_4, mu_table->mu_score_tbl_4);
MAC_REG_W32(R_AX_SS_MU_TBL_5, mu_table->mu_score_tbl_5);
return MACSUCCESS;
}
u32 mac_set_snd_para(struct mac_ax_adapter *adapter,
struct mac_ax_fwcmd_snd *snd_info)
{
#define MAX_FWCMD_SND_LEN 600
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_set_snd_para *h2c;
switch (snd_info->frexgtype) {
case FRAME_EXCHANGE_SND_N_SU:
snd_info->wd[0].txpktsize = 31;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].ndpa = 1;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].snd_pkt_sel = 2;
snd_info->wd[1].ndpa = 1;
break;
case FRAME_EXCHANGE_SND_AC_SU:
snd_info->wd[0].txpktsize = 19;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].ndpa = 2;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].snd_pkt_sel = 2;
snd_info->wd[1].ndpa = 2;
break;
case FRAME_EXCHANGE_SND_AC_MU_BFRP1:
snd_info->wd[0].txpktsize = 21;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].snd_pkt_sel = 1;
snd_info->wd[0].ndpa = 2;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].sifs_tx = 1;
snd_info->wd[1].snd_pkt_sel = 3;
snd_info->wd[1].ndpa = 2;
snd_info->wd[2].txpktsize = 17;
snd_info->wd[2].stf_mode = 1;
snd_info->wd[2].disdatafb = 1;
snd_info->wd[2].data_txcnt_lmt_sel = 1;
snd_info->wd[2].data_txcnt_lmt = 1;
snd_info->wd[2].snd_pkt_sel = 5;
snd_info->wd[2].ndpa = 2;
break;
case FRAME_EXCHANGE_SND_AC_MU_BFRP2:
snd_info->wd[0].txpktsize = 23;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].snd_pkt_sel = 1;
snd_info->wd[0].ndpa = 2;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].sifs_tx = 1;
snd_info->wd[1].snd_pkt_sel = 3;
snd_info->wd[1].ndpa = 2;
snd_info->wd[2].txpktsize = 17;
snd_info->wd[2].stf_mode = 1;
snd_info->wd[2].disdatafb = 1;
snd_info->wd[2].data_txcnt_lmt_sel = 1;
snd_info->wd[2].data_txcnt_lmt = 1;
snd_info->wd[2].sifs_tx = 1;
snd_info->wd[2].snd_pkt_sel = 4;
snd_info->wd[2].ndpa = 2;
snd_info->wd[3].txpktsize = 17;
snd_info->wd[3].stf_mode = 1;
snd_info->wd[3].disdatafb = 1;
snd_info->wd[3].data_txcnt_lmt_sel = 1;
snd_info->wd[3].data_txcnt_lmt = 1;
snd_info->wd[3].snd_pkt_sel = 5;
snd_info->wd[3].ndpa = 2;
break;
case FRAME_EXCHANGE_SND_AC_MU_BFRP3:
snd_info->wd[0].txpktsize = 25;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].snd_pkt_sel = 1;
snd_info->wd[0].ndpa = 2;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].sifs_tx = 1;
snd_info->wd[1].snd_pkt_sel = 3;
snd_info->wd[1].ndpa = 2;
snd_info->wd[2].txpktsize = 17;
snd_info->wd[2].stf_mode = 1;
snd_info->wd[2].disdatafb = 1;
snd_info->wd[2].data_txcnt_lmt_sel = 1;
snd_info->wd[2].data_txcnt_lmt = 1;
snd_info->wd[2].sifs_tx = 1;
snd_info->wd[2].snd_pkt_sel = 4;
snd_info->wd[2].ndpa = 2;
snd_info->wd[3].txpktsize = 17;
snd_info->wd[3].stf_mode = 1;
snd_info->wd[3].disdatafb = 1;
snd_info->wd[3].data_txcnt_lmt_sel = 1;
snd_info->wd[3].data_txcnt_lmt = 1;
snd_info->wd[3].sifs_tx = 1;
snd_info->wd[3].snd_pkt_sel = 4;
snd_info->wd[3].ndpa = 2;
snd_info->wd[4].txpktsize = 17;
snd_info->wd[4].stf_mode = 1;
snd_info->wd[4].disdatafb = 1;
snd_info->wd[4].data_txcnt_lmt_sel = 1;
snd_info->wd[4].data_txcnt_lmt = 1;
snd_info->wd[4].snd_pkt_sel = 5;
snd_info->wd[4].ndpa = 2;
break;
case FRAME_EXCHANGE_SND_AX_SU:
snd_info->wd[0].txpktsize = 21;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].ndpa = 3;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].sifs_tx = 1;
snd_info->wd[1].snd_pkt_sel = 2;
snd_info->wd[1].ndpa = 3;
break;
case FRAME_EXCHANGE_SND_AX_MU_BFRP1:
snd_info->wd[0].txpktsize = 17 + 4 * snd_info->bfrp0_user_num;
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].snd_pkt_sel = 1;
snd_info->wd[0].ndpa = 3;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].sifs_tx = 1;
snd_info->wd[1].snd_pkt_sel = 3;
snd_info->wd[1].ndpa = 3;
snd_info->wd[2].txpktsize = 24 + 6 * snd_info->bfrp0_user_num;
snd_info->wd[2].stf_mode = 1;
snd_info->wd[2].disdatafb = 1;
snd_info->wd[2].data_txcnt_lmt_sel = 1;
snd_info->wd[2].data_txcnt_lmt = 1;
snd_info->wd[2].snd_pkt_sel = 5;
snd_info->wd[2].ndpa = 3;
break;
case FRAME_EXCHANGE_SND_AX_MU_BFRP2:
snd_info->wd[0].txpktsize = 17 + 4 * (snd_info->bfrp0_user_num +
snd_info->bfrp1_user_num);
snd_info->wd[0].stf_mode = 1;
snd_info->wd[0].disdatafb = 1;
snd_info->wd[0].data_txcnt_lmt_sel = 1;
snd_info->wd[0].data_txcnt_lmt = 1;
snd_info->wd[0].sifs_tx = 1;
snd_info->wd[0].snd_pkt_sel = 1;
snd_info->wd[0].ndpa = 3;
snd_info->wd[1].stf_mode = 1;
snd_info->wd[1].disdatafb = 1;
snd_info->wd[1].data_txcnt_lmt_sel = 1;
snd_info->wd[1].data_txcnt_lmt = 1;
snd_info->wd[1].sifs_tx = 1;
snd_info->wd[1].snd_pkt_sel = 3;
snd_info->wd[1].ndpa = 3;
snd_info->wd[2].txpktsize = 24 + 6 * snd_info->bfrp0_user_num;
snd_info->wd[2].stf_mode = 1;
snd_info->wd[2].disdatafb = 1;
snd_info->wd[2].data_txcnt_lmt_sel = 1;
snd_info->wd[2].data_txcnt_lmt = 1;
snd_info->wd[2].sifs_tx = 1;
snd_info->wd[2].snd_pkt_sel = 4;
snd_info->wd[2].ndpa = 3;
snd_info->wd[3].txpktsize = 24 + 6 * snd_info->bfrp1_user_num;
snd_info->wd[3].stf_mode = 1;
snd_info->wd[3].disdatafb = 1;
snd_info->wd[3].data_txcnt_lmt_sel = 1;
snd_info->wd[3].data_txcnt_lmt = 1;
snd_info->wd[3].snd_pkt_sel = 5;
snd_info->wd[3].ndpa = 3;
break;
default:
return MACNOTSUP;
}
// check input valid
if (snd_info->sfp.f2p_type > SNDF2P_DEL) {
PLTFM_MSG_ERR("Unrecognized SND F2P type: %d\n", snd_info->sfp.f2p_type);
return MACFUNCINPUT;
}
if (snd_info->sfp.f2p_index >= MAX_SNDTXCMDINFO_NUM) {
PLTFM_MSG_ERR("Unrecognized SND F2P index: %d\n", snd_info->sfp.f2p_index);
return MACFUNCINPUT;
}
if (snd_info->sfp.f2p_type == SNDF2P_ADD && snd_info->sfp.f2p_period == 0) {
PLTFM_MSG_ERR("Unrecognized SND F2P period: %d\n", snd_info->sfp.f2p_period);
return MACFUNCINPUT;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, MAX_FWCMD_SND_LEN);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMSET(buf, 0, MAX_FWCMD_SND_LEN);
h2c = (struct fwcmd_set_snd_para *)buf;
h2c->dword0 =
cpu_to_le32(SET_WORD(snd_info->frexgtype,
FWCMD_H2C_SET_SND_PARA_FREXCH_TYPE) |
SET_WORD(snd_info->mode, FWCMD_H2C_SET_SND_PARA_MODE) |
SET_WORD(snd_info->bfrp0_user_num,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_USER_NUM) |
SET_WORD(snd_info->bfrp1_user_num,
FWCMD_H2C_SET_SND_PARA_HE_BFRP1_USER_NUM));
h2c->dword1 =
cpu_to_le32(SET_WORD(snd_info->macid[0], FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->macid[1], FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->macid[2], FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->macid[3], FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword2 =
cpu_to_le32(SET_WORD(snd_info->macid[4], FWCMD_H2C_SET_SND_PARA_MACID4) |
SET_WORD(snd_info->macid[5], FWCMD_H2C_SET_SND_PARA_MACID5) |
SET_WORD(snd_info->macid[6], FWCMD_H2C_SET_SND_PARA_MACID6) |
SET_WORD(snd_info->macid[7], FWCMD_H2C_SET_SND_PARA_MACID7));
h2c->dword3 =
cpu_to_le32(SET_WORD(snd_info->pndpa.common.frame_ctl,
FWCMD_H2C_SET_SND_PARA_NDPA_FRAME_CTRL) |
SET_WORD(snd_info->pndpa.common.duration,
FWCMD_H2C_SET_SND_PARA_NDPA_DURATION));
h2c->dword4 =
cpu_to_le32(SET_WORD(snd_info->pndpa.common.addr1[0],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pndpa.common.addr1[1],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pndpa.common.addr1[2],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pndpa.common.addr1[3],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword5 =
cpu_to_le32(SET_WORD(snd_info->pndpa.common.addr1[4],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pndpa.common.addr1[5],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pndpa.common.addr2[0],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pndpa.common.addr2[1],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword6 =
cpu_to_le32(SET_WORD(snd_info->pndpa.common.addr2[2],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pndpa.common.addr2[3],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pndpa.common.addr2[4],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pndpa.common.addr2[5],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword7 =
cpu_to_le32((snd_info->pndpa.snd_dialog.he ?
FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_HE : 0) |
SET_WORD(snd_info->pndpa.snd_dialog.dialog,
FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_DIALOG));
h2c->dword8 =
cpu_to_le32(SET_WORD(snd_info->pndpa.ht_para.addr3[0],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pndpa.ht_para.addr3[1],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pndpa.ht_para.addr3[2],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pndpa.ht_para.addr3[3],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword9 =
cpu_to_le32(SET_WORD(snd_info->pndpa.ht_para.addr3[4],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pndpa.ht_para.addr3[5],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pndpa.ht_para.seq_control,
FWCMD_H2C_SET_SND_PARA_HT_SEQ_CONTROL));
h2c->dword10 =
cpu_to_le32(SET_WORD(snd_info->pndpa.vht_para.sta_info[0].aid,
FWCMD_H2C_SET_SND_PARA_VHT_STA0_AID12) |
(snd_info->pndpa.vht_para.sta_info[0].fb_type ?
FWCMD_H2C_SET_SND_PARA_VHT_STA0_FEEDBACK_TYPE : 0) |
SET_WORD(snd_info->pndpa.vht_para.sta_info[0].nc,
FWCMD_H2C_SET_SND_PARA_VHT_STA0_NC) |
SET_WORD(snd_info->pndpa.vht_para.sta_info[1].aid,
FWCMD_H2C_SET_SND_PARA_VHT_STA1_AID12) |
(snd_info->pndpa.vht_para.sta_info[1].fb_type ?
FWCMD_H2C_SET_SND_PARA_VHT_STA1_FEEDBACK_TYPE : 0) |
SET_WORD(snd_info->pndpa.vht_para.sta_info[1].nc,
FWCMD_H2C_SET_SND_PARA_VHT_STA1_NC));
h2c->dword11 =
cpu_to_le32(SET_WORD(snd_info->pndpa.vht_para.sta_info[2].aid,
FWCMD_H2C_SET_SND_PARA_VHT_STA2_AID12) |
(snd_info->pndpa.vht_para.sta_info[2].fb_type ?
FWCMD_H2C_SET_SND_PARA_VHT_STA2_FEEDBACK_TYPE : 0) |
SET_WORD(snd_info->pndpa.vht_para.sta_info[2].nc,
FWCMD_H2C_SET_SND_PARA_VHT_STA2_NC) |
SET_WORD(snd_info->pndpa.vht_para.sta_info[3].aid,
FWCMD_H2C_SET_SND_PARA_VHT_STA3_AID12) |
(snd_info->pndpa.vht_para.sta_info[3].fb_type ?
FWCMD_H2C_SET_SND_PARA_VHT_STA3_FEEDBACK_TYPE : 0) |
SET_WORD(snd_info->pndpa.vht_para.sta_info[3].nc,
FWCMD_H2C_SET_SND_PARA_VHT_STA3_NC));
h2c->dword12 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[0].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA0_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[0].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA0_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[0].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA0_FB_NG) |
(snd_info->pndpa.he_para.sta_info[0].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA0_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[0].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA0_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[0].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA0_NC));
h2c->dword13 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[1].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA1_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[1].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA1_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[1].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA1_FB_NG) |
(snd_info->pndpa.he_para.sta_info[1].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA1_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[1].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA1_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[1].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA1_NC));
h2c->dword14 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[2].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA2_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[2].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA2_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[2].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA2_FB_NG) |
(snd_info->pndpa.he_para.sta_info[2].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA2_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[2].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA2_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[2].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA2_NC));
h2c->dword15 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[3].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA3_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[3].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA3_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[3].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA3_FB_NG) |
(snd_info->pndpa.he_para.sta_info[3].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA3_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[3].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA3_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[3].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA3_NC));
h2c->dword16 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[4].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA4_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[4].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA4_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[4].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA4_FB_NG) |
(snd_info->pndpa.he_para.sta_info[4].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA4_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[4].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA4_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[4].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA4_NC));
h2c->dword17 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[5].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA5_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[5].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA5_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[5].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA5_FB_NG) |
(snd_info->pndpa.he_para.sta_info[5].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA5_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[5].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA5_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[5].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA5_NC));
h2c->dword18 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[6].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA6_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[6].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA6_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[6].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA6_FB_NG) |
(snd_info->pndpa.he_para.sta_info[6].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA6_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[6].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA6_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[6].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA6_NC));
h2c->dword19 =
cpu_to_le32(SET_WORD(snd_info->pndpa.he_para.sta_info[7].aid,
FWCMD_H2C_SET_SND_PARA_HE_STA7_AID11) |
SET_WORD(snd_info->pndpa.he_para.sta_info[7].bw,
FWCMD_H2C_SET_SND_PARA_HE_STA7_BW) |
SET_WORD(snd_info->pndpa.he_para.sta_info[7].fb_ng,
FWCMD_H2C_SET_SND_PARA_HE_STA7_FB_NG) |
(snd_info->pndpa.he_para.sta_info[7].disambiguation ?
FWCMD_H2C_SET_SND_PARA_HE_STA7_DISAMBIGUATION : 0) |
(snd_info->pndpa.he_para.sta_info[7].cb ?
FWCMD_H2C_SET_SND_PARA_HE_STA7_CB : 0) |
SET_WORD(snd_info->pndpa.he_para.sta_info[7].nc,
FWCMD_H2C_SET_SND_PARA_HE_STA7_NC));
h2c->dword20 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].frame_ctl,
FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL) |
SET_WORD(snd_info->pbfrp.hdr[0].duration,
FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION));
h2c->dword21 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].addr1[0],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[0].addr1[1],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[0].addr1[2],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[0].addr1[3],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword22 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].addr1[4],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[0].addr1[5],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[0].addr2[0],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[0].addr2[1],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword23 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[0].addr2[2],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[0].addr2[3],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[0].addr2[4],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[0].addr2[5],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword24 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].frame_ctl,
FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL) |
SET_WORD(snd_info->pbfrp.hdr[1].duration,
FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION));
h2c->dword25 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].addr1[0],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[1].addr1[1],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[1].addr1[2],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[1].addr1[3],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword26 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].addr1[4],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[1].addr1[5],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[1].addr2[0],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[1].addr2[1],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword27 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[1].addr2[2],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[1].addr2[3],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[1].addr2[4],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[1].addr2[5],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword28 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].frame_ctl,
FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL) |
SET_WORD(snd_info->pbfrp.hdr[2].duration,
FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION));
h2c->dword29 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].addr1[0],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[2].addr1[1],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[2].addr1[2],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[2].addr1[3],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword30 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].addr1[4],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[2].addr1[5],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[2].addr2[0],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[2].addr2[1],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword31 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.hdr[2].addr2[2],
FWCMD_H2C_SET_SND_PARA_MACID0) |
SET_WORD(snd_info->pbfrp.hdr[2].addr2[3],
FWCMD_H2C_SET_SND_PARA_MACID1) |
SET_WORD(snd_info->pbfrp.hdr[2].addr2[4],
FWCMD_H2C_SET_SND_PARA_MACID2) |
SET_WORD(snd_info->pbfrp.hdr[2].addr2[5],
FWCMD_H2C_SET_SND_PARA_MACID3));
h2c->dword32 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].common.tgr_info,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO) |
SET_WORD(snd_info->pbfrp.he_para[0].common.ul_len,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH) |
(snd_info->pbfrp.he_para[0].common.more_tf ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MORE_TF : 0) |
(snd_info->pbfrp.he_para[0].common.cs_rqd ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_CS_REQUIRED : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].common.ul_bw,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW) |
SET_WORD(snd_info->pbfrp.he_para[0].common.gi_ltf,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF) |
(snd_info->pbfrp.he_para[0].common.mimo_ltfmode ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MU_MIMO_LTF_MODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].common.num_heltf,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF) |
SET_WORD(snd_info->pbfrp.he_para[0].common.ul_pktext,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT) |
(snd_info->pbfrp.he_para[0].common.ul_stbc ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_STBC : 0) |
(snd_info->pbfrp.he_para[0].common.ldpc_extra_sym ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_LDPC_EXTRA_SYMBOL : 0) |
(snd_info->pbfrp.he_para[0].common.dplr ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_DOPPLER : 0));
h2c->dword33 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].common.ap_tx_pwr,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER) |
SET_WORD(snd_info->pbfrp.he_para[0].common.ul_sr,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE));
h2c->dword34 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[0].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[0].user[0].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[0].user[0].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[0].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[0].user[0].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[0].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword35 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[0].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[0].user[0].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword36 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[1].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[0].user[1].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[0].user[1].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[1].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[0].user[1].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[1].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword37 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[1].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[0].user[1].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword38 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[2].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[0].user[2].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[0].user[2].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[2].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[0].user[2].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[2].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword39 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[2].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[0].user[2].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword40 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[3].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[0].user[3].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[0].user[3].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[3].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[0].user[3].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[0].user[3].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword41 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[0].user[3].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[0].user[3].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword42 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].common.tgr_info,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO) |
SET_WORD(snd_info->pbfrp.he_para[1].common.ul_len,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH) |
(snd_info->pbfrp.he_para[1].common.more_tf ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MORE_TF : 0) |
(snd_info->pbfrp.he_para[1].common.cs_rqd ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_CS_REQUIRED : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].common.ul_bw,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW) |
SET_WORD(snd_info->pbfrp.he_para[1].common.gi_ltf,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF) |
(snd_info->pbfrp.he_para[1].common.mimo_ltfmode ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MU_MIMO_LTF_MODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].common.num_heltf,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF) |
SET_WORD(snd_info->pbfrp.he_para[1].common.ul_pktext,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT) |
(snd_info->pbfrp.he_para[1].common.ul_stbc ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_STBC : 0) |
(snd_info->pbfrp.he_para[1].common.ldpc_extra_sym ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_LDPC_EXTRA_SYMBOL : 0) |
(snd_info->pbfrp.he_para[1].common.dplr ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_DOPPLER : 0));
h2c->dword43 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].common.ap_tx_pwr,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER) |
SET_WORD(snd_info->pbfrp.he_para[1].common.ul_sr,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE));
h2c->dword44 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[0].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[1].user[0].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[1].user[0].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[0].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[1].user[0].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[0].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword45 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[0].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[1].user[0].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword46 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[1].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[1].user[1].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[1].user[1].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[1].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[1].user[1].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[1].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword47 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[1].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[1].user[1].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword48 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[2].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[1].user[2].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[1].user[2].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[2].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[1].user[2].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[2].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword49 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[2].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[1].user[2].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword50 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[3].aid12,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12) |
SET_WORD(snd_info->pbfrp.he_para[1].user[3].ru_pos,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS) |
(snd_info->pbfrp.he_para[1].user[3].ul_fec_code ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[3].ul_mcs,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS) |
(snd_info->pbfrp.he_para[1].user[3].ul_dcm ?
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM : 0) |
SET_WORD(snd_info->pbfrp.he_para[1].user[3].ss_alloc,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC));
h2c->dword51 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.he_para[1].user[3].fbseg_rexmit_bmp,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.he_para[1].user[3].ul_tgt_rssi,
FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI));
h2c->dword52 =
cpu_to_le32(SET_WORD(snd_info->pbfrp.vht_para[0].retransmission_bitmap,
FWCMD_H2C_SET_SND_PARA_VHT_BFRP0_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.vht_para[1].retransmission_bitmap,
FWCMD_H2C_SET_SND_PARA_VHT_BFRP1_FB_REXMIT) |
SET_WORD(snd_info->pbfrp.vht_para[2].retransmission_bitmap,
FWCMD_H2C_SET_SND_PARA_VHT_BFRP2_FB_REXMIT));
h2c->dword53 =
cpu_to_le32(SET_WORD(snd_info->wd[0].txpktsize,
FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) |
SET_WORD(snd_info->wd[0].ndpa_duration,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0));
h2c->dword54 =
cpu_to_le32(SET_WORD(snd_info->wd[0].datarate,
FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) |
SET_WORD(snd_info->wd[0].macid,
FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) |
(snd_info->wd[0].force_txop ?
FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) |
SET_WORD(snd_info->wd[0].data_bw,
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) |
SET_WORD(snd_info->wd[0].gi_ltf,
FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) |
(snd_info->wd[0].data_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) |
(snd_info->wd[0].data_dcm ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) |
(snd_info->wd[0].data_stbc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) |
(snd_info->wd[0].data_ldpc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) |
(snd_info->wd[0].data_bw_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) |
(snd_info->wd[0].multiport_id ?
FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) |
SET_WORD(snd_info->wd[0].mbssid,
FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0));
h2c->dword55 =
cpu_to_le32(SET_WORD(snd_info->wd[0].signaling_ta_pkt_sc,
FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) |
SET_WORD(snd_info->wd[0].sw_define,
FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) |
SET_WORD(snd_info->wd[0].txpwr_ofset_type,
FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) |
SET_WORD(snd_info->wd[0].lifetime_sel,
FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) |
(snd_info->wd[0].stf_mode ?
FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) |
(snd_info->wd[0].disdatafb ?
FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) |
(snd_info->wd[0].data_txcnt_lmt_sel ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) |
SET_WORD(snd_info->wd[0].data_txcnt_lmt,
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) |
(snd_info->wd[0].sifs_tx ?
FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) |
SET_WORD(snd_info->wd[0].snd_pkt_sel,
FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) |
SET_WORD(snd_info->wd[0].ndpa,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0));
h2c->dword56 =
cpu_to_le32(SET_WORD(snd_info->wd[1].txpktsize,
FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) |
SET_WORD(snd_info->wd[1].ndpa_duration,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0));
h2c->dword57 =
cpu_to_le32(SET_WORD(snd_info->wd[1].datarate,
FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) |
SET_WORD(snd_info->wd[1].macid,
FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) |
(snd_info->wd[1].force_txop ?
FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) |
SET_WORD(snd_info->wd[1].data_bw,
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) |
SET_WORD(snd_info->wd[1].gi_ltf,
FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) |
(snd_info->wd[1].data_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) |
(snd_info->wd[1].data_dcm ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) |
(snd_info->wd[1].data_stbc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) |
(snd_info->wd[1].data_ldpc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) |
(snd_info->wd[1].data_bw_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) |
(snd_info->wd[1].multiport_id ?
FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) |
SET_WORD(snd_info->wd[1].mbssid,
FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0));
h2c->dword58 =
cpu_to_le32(SET_WORD(snd_info->wd[1].signaling_ta_pkt_sc,
FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) |
SET_WORD(snd_info->wd[1].sw_define,
FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) |
SET_WORD(snd_info->wd[1].txpwr_ofset_type,
FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) |
SET_WORD(snd_info->wd[1].lifetime_sel,
FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) |
(snd_info->wd[1].stf_mode ?
FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) |
(snd_info->wd[1].disdatafb ?
FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) |
(snd_info->wd[1].data_txcnt_lmt_sel ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) |
SET_WORD(snd_info->wd[1].data_txcnt_lmt,
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) |
(snd_info->wd[1].sifs_tx ?
FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) |
SET_WORD(snd_info->wd[1].snd_pkt_sel,
FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) |
SET_WORD(snd_info->wd[1].ndpa,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0));
h2c->dword59 =
cpu_to_le32(SET_WORD(snd_info->wd[2].txpktsize,
FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) |
SET_WORD(snd_info->wd[2].ndpa_duration,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0));
h2c->dword60 =
cpu_to_le32(SET_WORD(snd_info->wd[2].datarate,
FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) |
SET_WORD(snd_info->wd[2].macid,
FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) |
(snd_info->wd[2].force_txop ?
FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) |
SET_WORD(snd_info->wd[2].data_bw,
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) |
SET_WORD(snd_info->wd[2].gi_ltf,
FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) |
(snd_info->wd[2].data_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) |
(snd_info->wd[2].data_dcm ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) |
(snd_info->wd[2].data_stbc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) |
(snd_info->wd[2].data_ldpc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) |
(snd_info->wd[2].data_bw_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) |
(snd_info->wd[2].multiport_id ?
FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) |
SET_WORD(snd_info->wd[2].mbssid,
FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0));
h2c->dword61 =
cpu_to_le32(SET_WORD(snd_info->wd[2].signaling_ta_pkt_sc,
FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) |
SET_WORD(snd_info->wd[2].sw_define,
FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) |
SET_WORD(snd_info->wd[2].txpwr_ofset_type,
FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) |
SET_WORD(snd_info->wd[2].lifetime_sel,
FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) |
(snd_info->wd[2].stf_mode ?
FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) |
(snd_info->wd[2].disdatafb ?
FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) |
(snd_info->wd[2].data_txcnt_lmt_sel ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) |
SET_WORD(snd_info->wd[2].data_txcnt_lmt,
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) |
(snd_info->wd[2].sifs_tx ?
FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) |
SET_WORD(snd_info->wd[2].snd_pkt_sel,
FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) |
SET_WORD(snd_info->wd[2].ndpa,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0));
h2c->dword62 =
cpu_to_le32(SET_WORD(snd_info->wd[3].txpktsize,
FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) |
SET_WORD(snd_info->wd[3].ndpa_duration,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0));
h2c->dword63 =
cpu_to_le32(SET_WORD(snd_info->wd[3].datarate,
FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) |
SET_WORD(snd_info->wd[3].macid,
FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) |
(snd_info->wd[3].force_txop ?
FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) |
SET_WORD(snd_info->wd[3].data_bw,
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) |
SET_WORD(snd_info->wd[3].gi_ltf,
FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) |
(snd_info->wd[3].data_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) |
(snd_info->wd[3].data_dcm ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) |
(snd_info->wd[3].data_stbc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) |
(snd_info->wd[3].data_ldpc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) |
(snd_info->wd[3].data_bw_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) |
(snd_info->wd[3].multiport_id ?
FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) |
SET_WORD(snd_info->wd[3].mbssid,
FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0));
h2c->dword64 =
cpu_to_le32(SET_WORD(snd_info->wd[3].signaling_ta_pkt_sc,
FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) |
SET_WORD(snd_info->wd[3].sw_define,
FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) |
SET_WORD(snd_info->wd[3].txpwr_ofset_type,
FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) |
SET_WORD(snd_info->wd[3].lifetime_sel,
FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) |
(snd_info->wd[3].stf_mode ?
FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) |
(snd_info->wd[3].disdatafb ?
FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) |
(snd_info->wd[3].data_txcnt_lmt_sel ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) |
SET_WORD(snd_info->wd[3].data_txcnt_lmt,
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) |
(snd_info->wd[3].sifs_tx ?
FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) |
SET_WORD(snd_info->wd[3].snd_pkt_sel,
FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) |
SET_WORD(snd_info->wd[3].ndpa,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0));
h2c->dword65 =
cpu_to_le32(SET_WORD(snd_info->wd[4].txpktsize,
FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0) |
SET_WORD(snd_info->wd[4].ndpa_duration,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0));
h2c->dword66 =
cpu_to_le32(SET_WORD(snd_info->wd[4].datarate,
FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0) |
SET_WORD(snd_info->wd[4].macid,
FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0) |
(snd_info->wd[4].force_txop ?
FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 : 0) |
SET_WORD(snd_info->wd[4].data_bw,
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0) |
SET_WORD(snd_info->wd[4].gi_ltf,
FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0) |
(snd_info->wd[4].data_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 : 0) |
(snd_info->wd[4].data_dcm ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 : 0) |
(snd_info->wd[4].data_stbc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 : 0) |
(snd_info->wd[4].data_ldpc ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 : 0) |
(snd_info->wd[4].data_bw_er ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 : 0) |
(snd_info->wd[4].multiport_id ?
FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 : 0) |
SET_WORD(snd_info->wd[4].mbssid,
FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0));
h2c->dword67 =
cpu_to_le32(SET_WORD(snd_info->wd[4].signaling_ta_pkt_sc,
FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0) |
SET_WORD(snd_info->wd[4].sw_define,
FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0) |
SET_WORD(snd_info->wd[4].txpwr_ofset_type,
FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0) |
SET_WORD(snd_info->wd[4].lifetime_sel,
FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0) |
(snd_info->wd[4].stf_mode ?
FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 : 0) |
(snd_info->wd[4].disdatafb ?
FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 : 0) |
(snd_info->wd[4].data_txcnt_lmt_sel ?
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 : 0) |
SET_WORD(snd_info->wd[4].data_txcnt_lmt,
FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0) |
(snd_info->wd[4].sifs_tx ?
FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 : 0) |
SET_WORD(snd_info->wd[4].snd_pkt_sel,
FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0) |
SET_WORD(snd_info->wd[4].ndpa,
FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0));
h2c->dword68 =
cpu_to_le32(SET_WORD(snd_info->f2p[0].csi_len_bfrp,
FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0) |
SET_WORD(snd_info->f2p[0].tb_t_pe_bfrp,
FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0) |
SET_WORD(snd_info->f2p[0].tri_pad_bfrp,
FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0) |
(snd_info->f2p[0].ul_cqi_rpt_tri_bfrp ?
FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP0 : 0) |
SET_WORD(snd_info->f2p[0].rf_gain_idx_bfrp,
FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0) |
(snd_info->f2p[0].fix_gain_en_bfrp ?
FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP0 : 0));
h2c->dword69 =
cpu_to_le32(SET_WORD(snd_info->f2p[1].csi_len_bfrp,
FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0) |
SET_WORD(snd_info->f2p[1].tb_t_pe_bfrp,
FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0) |
SET_WORD(snd_info->f2p[1].tri_pad_bfrp,
FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0) |
(snd_info->f2p[1].ul_cqi_rpt_tri_bfrp ?
FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP0 : 0) |
SET_WORD(snd_info->f2p[1].rf_gain_idx_bfrp,
FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0) |
(snd_info->f2p[1].fix_gain_en_bfrp ?
FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP0 : 0));
h2c->dword70 =
cpu_to_le32(SET_WORD(snd_info->sfp.f2p_type,
FWCMD_H2C_SET_SND_PARA_F2P_TYPE) |
SET_WORD(snd_info->sfp.f2p_index,
FWCMD_H2C_SET_SND_PARA_F2P_INDEX) |
SET_WORD(snd_info->sfp.f2p_period,
FWCMD_H2C_SET_SND_PARA_F2P_PERIOD));
h2c->dword71 =
cpu_to_le32(SET_WORD(snd_info->sfp.f2p_updcnt,
FWCMD_H2C_SET_SND_PARA_F2P_UPDCNT) |
SET_WORD(snd_info->sfp.cr_idx,
FWCMD_H2C_SET_SND_PARA_CR_IDX));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_SOUND,
FWCMD_H2C_FUNC_SET_SND_PARA,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_set_csi_para_reg(struct mac_ax_adapter *adapter,
struct mac_reg_csi_para *csi_para)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
u16 val16;
#if MAC_AX_FW_REG_OFLD
u32 mask;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
}
cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0;
mask = B_AX_BFMEE_BFPARAM_SEL;
ret = write_mac_reg_ofld(adapter, cr, mask, 1, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
if (csi_para->portsel == 0)
cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0;
else
cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_1;
val16 = SET_WORD(csi_para->nc, B_AX_BFMEE_CSIINFO0_NC) |
SET_WORD(csi_para->nr, B_AX_BFMEE_CSIINFO0_NR) |
SET_WORD(csi_para->ng, B_AX_BFMEE_CSIINFO0_NG) |
SET_WORD(csi_para->cb, B_AX_BFMEE_CSIINFO0_CB) |
SET_WORD(csi_para->cs, B_AX_BFMEE_CSIINFO0_CS) |
(csi_para->ldpc_en ? B_AX_BFMEE_CSIINFO0_LDPC_EN : 0) |
(csi_para->stbc_en ? B_AX_BFMEE_CSIINFO0_STBC_EN : 0);
ret = MAC_REG_W16_OFLD(cr, val16, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, (u8)csi_para->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
}
val32 = MAC_REG_R32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0);
val32 |= B_AX_BFMEE_BFPARAM_SEL;
MAC_REG_W32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32);
val16 = SET_WORD(csi_para->nc, B_AX_BFMEE_CSIINFO0_NC) |
SET_WORD(csi_para->nr, B_AX_BFMEE_CSIINFO0_NR) |
SET_WORD(csi_para->ng, B_AX_BFMEE_CSIINFO0_NG) |
SET_WORD(csi_para->cb, B_AX_BFMEE_CSIINFO0_CB) |
SET_WORD(csi_para->cs, B_AX_BFMEE_CSIINFO0_CS) |
(csi_para->ldpc_en ? B_AX_BFMEE_CSIINFO0_LDPC_EN : 0) |
(csi_para->stbc_en ? B_AX_BFMEE_CSIINFO0_STBC_EN : 0);
if (csi_para->portsel == 0)
MAC_REG_W16(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0, val16);
else
MAC_REG_W16(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_1, val16);
return MACSUCCESS;
}
u32 mac_set_csi_para_cctl(struct mac_ax_adapter *adapter,
struct mac_cctl_csi_para *csi_para)
{
struct mac_ax_cctl_info info;
struct mac_ax_cctl_info mask;
struct mac_ax_ops *ax_ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret, val32;
#if MAC_AX_FW_REG_OFLD
u32 msk;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, (u8)csi_para->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
}
cr = csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0;
msk = B_AX_BFMEE_BFPARAM_SEL;
ret = write_mac_reg_ofld(adapter, cr, msk, 0, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
info.nc = csi_para->nc;
info.nr = csi_para->nr;
info.ng = csi_para->ng;
info.cb = csi_para->cb;
info.cs = csi_para->cs;
//info.csi_txbf_en = csi_para->bf_en; BB HW BUG not support
info.csi_txbf_en = 0x0;
info.csi_stbc_en = csi_para->stbc_en;
info.csi_ldpc_en = csi_para->ldpc_en;
info.csi_para_en = 1;
info.csi_fix_rate = csi_para->rate;
info.csi_gi_ltf = csi_para->gi_ltf;
info.uldl = csi_para->gid_sel;
info.csi_bw = csi_para->bw;
PLTFM_MEMSET(&mask, 0, sizeof(mask));
mask.nc = 0x7;
mask.nr = 0x7;
mask.ng = 0x3;
mask.cb = 0x3;
mask.cs = 0x3;
mask.csi_txbf_en = 0x1;
mask.csi_stbc_en = 0x1;
mask.csi_ldpc_en = 0x1;
mask.csi_para_en = 0x1;
mask.csi_fix_rate = 0x1FF;
mask.csi_gi_ltf = 0x7;
mask.uldl = 0x1;
mask.csi_bw = 0x3;
ret = ax_ops->upd_cctl_info(adapter, &info, &mask, csi_para->macid, 1);
if (ret)
return MACCCTLWRFAIL;
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, (u8)csi_para->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV)) {
if (csi_para->ng == 3)
return MACHWNOSUP;
}
}
val32 = MAC_REG_R32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0);
val32 &= (~B_AX_BFMEE_BFPARAM_SEL);
MAC_REG_W32(csi_para->band ? R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 :
R_AX_TRXPTCL_RESP_CSI_CTRL_0, val32);
info.nc = csi_para->nc;
info.nr = csi_para->nr;
info.ng = csi_para->ng;
info.cb = csi_para->cb;
info.cs = csi_para->cs;
//info.csi_txbf_en = csi_para->bf_en; BB HW BUG not support
info.csi_txbf_en = 0x0;
info.csi_stbc_en = csi_para->stbc_en;
info.csi_ldpc_en = csi_para->ldpc_en;
info.csi_para_en = 1;
info.csi_fix_rate = csi_para->rate;
info.csi_gi_ltf = csi_para->gi_ltf;
info.uldl = csi_para->gid_sel;
info.csi_bw = csi_para->bw;
PLTFM_MEMSET(&mask, 0, sizeof(mask));
mask.nc = 0x7;
mask.nr = 0x7;
mask.ng = 0x3;
mask.cb = 0x3;
mask.cs = 0x3;
mask.csi_txbf_en = 0x1;
mask.csi_stbc_en = 0x1;
mask.csi_ldpc_en = 0x1;
mask.csi_para_en = 0x1;
mask.csi_fix_rate = 0x1FF;
mask.csi_gi_ltf = 0x7;
mask.uldl = 0x1;
mask.csi_bw = 0x3;
ret = ax_ops->upd_cctl_info(adapter, &info, &mask, csi_para->macid, 1);
if (ret)
return MACCCTLWRFAIL;
return MACSUCCESS;
}
u32 mac_hw_snd_pause_release(struct mac_ax_adapter *adapter, u8 band,
u8 pr)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
#if MAC_AX_FW_REG_OFLD
u16 cr, val16;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cr = band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN;
val16 = pr ? HW_SND_RELEASE : HW_SND_PAUSE;
ret = MAC_REG_W16_OFLD(cr, val16, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
MAC_REG_W16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN,
pr ? HW_SND_RELEASE : HW_SND_PAUSE);
return MACSUCCESS;
}
u32 mac_bypass_snd_sts(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
#if MAC_AX_FW_REG_OFLD
u32 mask, ret;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
cr = R_AX_AGG_BK_0;
mask = B_AX_DIS_SND_STS_CHECK;
ret = write_mac_reg_ofld(adapter, cr, mask, 1, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
val8 = MAC_REG_R8(R_AX_AGG_BK_0);
MAC_REG_W8(R_AX_AGG_BK_0, val8 | B_AX_DIS_SND_STS_CHECK);
return MACSUCCESS;
}
u32 mac_deinit_mee(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
#if MAC_AX_FW_REG_OFLD
u32 mask;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cr = band ? R_AX_BFMEE_RESP_OPTION_C1 : R_AX_BFMEE_RESP_OPTION;
mask = (B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
B_AX_BFMEE_HE_NDPA_EN);
ret = write_mac_reg_ofld(adapter, cr, mask, 0, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32 = MAC_REG_R32(band ? R_AX_BFMEE_RESP_OPTION_C1 :
R_AX_BFMEE_RESP_OPTION);
val32 &= ~(B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
B_AX_BFMEE_HE_NDPA_EN);
MAC_REG_W32(band ? R_AX_BFMEE_RESP_OPTION_C1 :
R_AX_BFMEE_RESP_OPTION, val32);
return MACSUCCESS;
}
u32 mac_snd_sup(struct mac_ax_adapter *adapter, struct mac_bf_sup *bf_sup)
{
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
bf_sup->bf_entry_num = 16;
bf_sup->su_buffer_num = 16;
bf_sup->mu_buffer_num = 6;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
bf_sup->bf_entry_num = 16;
bf_sup->su_buffer_num = 16;
bf_sup->mu_buffer_num = 6;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
bf_sup->bf_entry_num = 16;
bf_sup->su_buffer_num = 16;
bf_sup->mu_buffer_num = 6;
} else {
return MACNOTSUP;
}
return MACSUCCESS;
}
u32 mac_gidpos(struct mac_ax_adapter *adapter, struct mac_gid_pos *mu_gid)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FW_REG_OFLD
u32 ret, val32;
u16 cr;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
cr = mu_gid->band ? R_AX_GID_POSITION_EN0_C1 : R_AX_GID_POSITION_EN0;
val32 = mu_gid->gid_tab[0];
ret = MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = mu_gid->band ? R_AX_GID_POSITION_EN1_C1 : R_AX_GID_POSITION_EN1;
val32 = mu_gid->gid_tab[1];
MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = mu_gid->band ? R_AX_GID_POSITION0_C1 : R_AX_GID_POSITION0;
val32 = mu_gid->user_pos[0];
MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = mu_gid->band ? R_AX_GID_POSITION1_C1 : R_AX_GID_POSITION1;
val32 = mu_gid->user_pos[1];
MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = mu_gid->band ? R_AX_GID_POSITION2_C1 : R_AX_GID_POSITION2;
val32 = mu_gid->user_pos[2];
MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
cr = mu_gid->band ? R_AX_GID_POSITION3_C1 : R_AX_GID_POSITION3;
val32 = mu_gid->user_pos[3];
MAC_REG_W32_OFLD(cr, val32, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, cr);
return ret;
}
return MACSUCCESS;
}
#endif
MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION_EN0_C1 :
R_AX_GID_POSITION_EN0, mu_gid->gid_tab[0]);
MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION_EN1_C1 :
R_AX_GID_POSITION_EN1, mu_gid->gid_tab[1]);
MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION0_C1 : R_AX_GID_POSITION0,
mu_gid->user_pos[0]);
MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION1_C1 : R_AX_GID_POSITION1,
mu_gid->user_pos[1]);
MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION2_C1 : R_AX_GID_POSITION2,
mu_gid->user_pos[2]);
MAC_REG_W32(mu_gid->band ? R_AX_GID_POSITION3_C1 : R_AX_GID_POSITION3,
mu_gid->user_pos[3]);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/sounding.c
|
C
|
agpl-3.0
| 72,493
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_SOUNDING_H_
#define _MAC_AX_SOUNDING_H_
#include "../type.h"
#include "fwcmd.h"
#include "trxcfg.h"
#define CSI_MAX_BUFFER_IDX 0xF
#define SOUNDING_STS_MAX_IDX 0x15
#define CSI_RRSC_BMAP 0x29292911
#define BFRP_RX_STANDBY_TIMER 0x0
#define NDP_RX_STANDBY_TIMER 0xFF
#define CSI_INIT_RATE_HE 0x0
#define CSI_INIT_RATE_VHT 0x0
#define CSI_INIT_RATE_HT 0x0
#define HW_SND_RELEASE 0xFFFF
#define HW_SND_PAUSE 0x0
#define HT_PAYLOAD_OFFSET 0x10
#define VHT_PAYLOAD_OFFSET 0x11
#define HE_PAYLOAD_OFFSET 0x13
#define CSI_SH 0x4
#define SND_SH 0x2
#define SND_MEE_CFG (B_AX_BFMEE_BFPARAM_SEL | B_AX_BFMEE_USE_NSTS | \
B_AX_BFMEE_CSI_FORCE_RETE_EN | B_AX_BFMEE_BFINF0_NR | \
B_AX_BFMEE_BFINFO0_NC)
#define MAX_SNDTXCMDINFO_NUM 0x4
enum FrameExchangeType {
FRAME_EXCHANGE_SND_AC_SU = 31,
FRAME_EXCHANGE_SND_AC_MU_BFRP1 = 32,
FRAME_EXCHANGE_SND_AC_MU_BFRP2 = 33,
FRAME_EXCHANGE_SND_AC_MU_BFRP3 = 34,
FRAME_EXCHANGE_SND_AX_SU = 35,
FRAME_EXCHANGE_SND_AX_MU_BFRP1 = 36,
FRAME_EXCHANGE_SND_AX_MU_BFRP2 = 37,
FRAME_EXCHANGE_SND_N_SU = 38
};
enum SND_F2P_TYPE {
SNDF2P_ONCE = 0,
SNDF2P_ADD = 1,
SNDF2P_DEL = 2
};
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_get_csi_buffer_index
*
* @param *adapter
* @param band
* @param csi_buffer_id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band,
u8 csi_buffer_id);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_set_csi_buffer_index
*
* @param *adapter
* @param band
* @param macid
* @param csi_buffer_id
* @param buffer_idx
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_csi_buffer_index(struct mac_ax_adapter *adapter, u8 band,
u8 macid, u16 csi_buffer_id, u16 buffer_idx);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_get_snd_sts_index
*
* @param *adapter
* @param band
* @param index
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 index);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_set_snd_sts_index
*
* @param *adapter
* @param band
* @param macid
* @param index
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_snd_sts_index(struct mac_ax_adapter *adapter, u8 band, u8 macid,
u8 index);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_init_snd_mer
*
* @param *adapter
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_init_snd_mer(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_init_snd_mee
*
* @param *adapter
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_init_snd_mee(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_csi_force_rate
*
* @param *adapter
* @param band
* @param ht_rate
* @param vht_rate
* @param he_rate
* @return Please Place Description here.
* @retval u32
*/
u32 mac_csi_force_rate(struct mac_ax_adapter *adapter, u8 band, u8 ht_rate,
u8 vht_rate, u8 he_rate);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_csi_rrsc
*
* @param *adapter
* @param band
* @param rrsc
* @return Please Place Description here.
* @retval u32
*/
u32 mac_csi_rrsc(struct mac_ax_adapter *adapter, u8 band, u32 rrsc);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_set_mu_table
*
* @param *adapter
* @param *mu_table
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_mu_table(struct mac_ax_adapter *adapter,
struct mac_mu_table *mu_table);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_set_snd_para
*
* @param *adapter
* @param *snd_info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_snd_para(struct mac_ax_adapter *adapter,
struct mac_ax_fwcmd_snd *snd_info);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_set_csi_para_reg
*
* @param *adapter
* @param *csi_para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_csi_para_reg(struct mac_ax_adapter *adapter,
struct mac_reg_csi_para *csi_para);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_set_csi_para_cctl
*
* @param *adapter
* @param *csi_para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_csi_para_cctl(struct mac_ax_adapter *adapter,
struct mac_cctl_csi_para *csi_para);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_hw_snd_pause_release
*
* @param *adapter
* @param band
* @param pr
* @return Please Place Description here.
* @retval u32
*/
u32 mac_hw_snd_pause_release(struct mac_ax_adapter *adapter, u8 band, u8 pr);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_bypass_snd_sts
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_bypass_snd_sts(struct mac_ax_adapter *adapter);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_deinit_mee
*
* @param *adapter
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_deinit_mee(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_snd_sup
*
* @param *adapter
* @param *bf_sup
* @return Please Place Description here.
* @retval u32
*/
u32 mac_snd_sup(struct mac_ax_adapter *adapter, struct mac_bf_sup *bf_sup);
/**
* @}
*/
/**
* @addtogroup Sounding
* @{
*/
/**
* @brief mac_gid_pos
*
* @param *adapter
* @param *mac_gid_pos
* @return Please Place Description here.
* @retval u32
*/
u32 mac_gidpos(struct mac_ax_adapter *adapter, struct mac_gid_pos *mu_gid);
/**
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/sounding.h
|
C
|
agpl-3.0
| 6,671
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "spatial_reuse.h"
u32 mac_sr_update(struct mac_ax_adapter *adapter,
struct mac_ax_sr_info *sr_info,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
u32 val32, ret, reg;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ? R_AX_RX_SR_CTRL_C1 : R_AX_RX_SR_CTRL;
val8 = MAC_REG_R8(reg);
val8 = (sr_info->sr_en) ? (val8 | B_AX_SR_EN) : (val8 & ~B_AX_SR_EN);
MAC_REG_W8(reg, val8);
reg = band == MAC_AX_BAND_1 ? R_AX_TCR0_C1 : R_AX_TCR0;
val8 = MAC_REG_R8(reg);
val8 = (sr_info->sr_field_v15_allowed) ?
(val8 | B_AX_TCR_SR_VAL15_ALLOW) :
(val8 & ~B_AX_TCR_SR_VAL15_ALLOW);
MAC_REG_W8(reg, val8);
reg = band == MAC_AX_BAND_1 ? R_AX_SR_OBSS_PD_C1 : R_AX_SR_OBSS_PD;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_min,
B_AX_NONSRG_OBSS_PD_MIN);
val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_max,
B_AX_NONSRG_OBSS_PD_MAX);
val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_min,
B_AX_SRG_OBSS_PD_MIN);
val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_max,
B_AX_SRG_OBSS_PD_MAX);
MAC_REG_W32(reg, val32);
reg = band == MAC_AX_BAND_1 ?
R_AX_SR_BSSCOLOR_BITMAP_C1 : R_AX_SR_BSSCOLOR_BITMAP;
MAC_REG_W32(reg, sr_info->srg_bsscolor_bitmap_0);
MAC_REG_W32(reg + 4, sr_info->srg_bsscolor_bitmap_1);
reg = band == MAC_AX_BAND_1 ?
R_AX_SR_PARTIAL_BSSCOLOR_BITMAP_C1 :
R_AX_SR_PARTIAL_BSSCOLOR_BITMAP;
MAC_REG_W32(reg, sr_info->srg_partbsid_bitmap_0);
MAC_REG_W32(reg + 4, sr_info->srg_partbsid_bitmap_1);
return MACSUCCESS;
}
u32 spatial_reuse_init(struct mac_ax_adapter *adapter,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
u32 ret, reg;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ? R_AX_RX_SR_CTRL_C1 : R_AX_RX_SR_CTRL;
val8 = MAC_REG_R8(reg) & ~B_AX_SR_EN;
MAC_REG_W8(reg, val8);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/spatial_reuse.c
|
C
|
agpl-3.0
| 2,762
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_SPATIAL_REUSE_H_
#define _MAC_AX_SPATIAL_REUSE_H_
#include "../type.h"
u32 mac_sr_update(struct mac_ax_adapter *adapter,
struct mac_ax_sr_info *sr_info,
enum mac_ax_band band);
u32 spatial_reuse_init(struct mac_ax_adapter *adapter,
enum mac_ax_band band);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/spatial_reuse.h
|
C
|
agpl-3.0
| 985
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_STATE_MACH_H_
#define _MAC_AX_STATE_MACH_H_
/**
* @struct mac_ax_state_mach
* @brief mac_ax_state_mach
*
* @var mac_ax_state_mach::pwr
* Please Place Description here.
* @var mac_ax_state_mach::fwdl
* Please Place Description here.
* @var mac_ax_state_mach::efuse
* Please Place Description here.
* @var mac_ax_state_mach::read_request
* Please Place Description here.
* @var mac_ax_state_mach::write_request
* Please Place Description here.
* @var mac_ax_state_mach::conf_request
* Please Place Description here.
* @var mac_ax_state_mach::write_h2c
* Please Place Description here.
* @var mac_ax_state_mach::conf_h2c
* Please Place Description here.
* @var mac_ax_state_mach::read_h2c
* Please Place Description here.
* @var mac_ax_state_mach::pkt_ofld
* Please Place Description here.
* @var mac_ax_state_mach::efuse_ofld
* Please Place Description here.
* @var mac_ax_state_mach::macid_pause
* Please Place Description here.
* @var mac_ax_state_mach::mcc_group
* Please Place Description here.
* @var mac_ax_state_mach::mcc_request
* Please Place Description here.
* @var mac_ax_state_mach::fw_rst
* Please Place Description here.
* @var mac_ax_state_mach::aoac_rpt
* Please Place Description here.
*/
/**
* @struct mac_ax_state_mach
* @brief mac_ax_state_mach
*
* @var mac_ax_state_mach::pwr
* Please Place Description here.
* @var mac_ax_state_mach::fwdl
* Please Place Description here.
* @var mac_ax_state_mach::efuse
* Please Place Description here.
* @var mac_ax_state_mach::read_request
* Please Place Description here.
* @var mac_ax_state_mach::write_request
* Please Place Description here.
* @var mac_ax_state_mach::conf_request
* Please Place Description here.
* @var mac_ax_state_mach::write_h2c
* Please Place Description here.
* @var mac_ax_state_mach::conf_h2c
* Please Place Description here.
* @var mac_ax_state_mach::read_h2c
* Please Place Description here.
* @var mac_ax_state_mach::pkt_ofld
* Please Place Description here.
* @var mac_ax_state_mach::efuse_ofld
* Please Place Description here.
* @var mac_ax_state_mach::macid_pause
* Please Place Description here.
* @var mac_ax_state_mach::mcc_group
* Please Place Description here.
* @var mac_ax_state_mach::mcc_request
* Please Place Description here.
* @var mac_ax_state_mach::fw_rst
* Please Place Description here.
* @var mac_ax_state_mach::aoac_rpt
* Please Place Description here.
* @var mac_ax_state_mach::p2p_stat
* Please Place Description here.
*/
struct mac_ax_state_mach {
#define MAC_AX_PWR_OFF 0
#define MAC_AX_PWR_ON 1
#define MAC_AX_PWR_PRE_OFF 2
#define MAC_AX_PWR_ERR 3
u8 pwr;
#define MAC_AX_FWDL_IDLE 0
#define MAC_AX_FWDL_CPU_ON 1
#define MAC_AX_FWDL_H2C_PATH_RDY 2
#define MAC_AX_FWDL_PATH_RDY 3
#define MAC_AX_FWDL_INIT_RDY 4
u8 fwdl;
#define MAC_AX_EFUSE_IDLE 0
#define MAC_AX_EFUSE_PHY 1
#define MAC_AX_EFUSE_LOG_MAP 2
#define MAC_AX_EFUSE_LOG_MASK 3
#define MAC_AX_EFUSE_MAX 4
u8 efuse;
#define MAC_AX_OFLD_REQ_IDLE 0
#define MAC_AX_OFLD_REQ_H2C_SENT 1
#define MAC_AX_OFLD_REQ_CREATED 2
#define MAC_AX_OFLD_REQ_CLEANED 3
u8 read_request;
u8 write_request;
u8 conf_request;
#define MAC_AX_CMD_OFLD_IDLE 0
#define MAC_AX_CMD_OFLD_PROC 1
#define MAC_AX_CMD_OFLD_SENDING 2
#define MAC_AX_CMD_OFLD_RCVD 3
u8 cmd_state;
#define MAC_AX_OFLD_H2C_IDLE 0
#define MAC_AX_OFLD_H2C_SENDING 1
#define MAC_AX_OFLD_H2C_RCVD 2
#define MAC_AX_OFLD_H2C_ERROR 4
u8 write_h2c;
u8 conf_h2c;
#define MAC_AX_OFLD_H2C_DONE 3
u8 read_h2c;
u8 pkt_ofld;
u8 efuse_ofld;
u8 macid_pause;
#define MAC_AX_MCC_EMPTY 0
#define MAC_AX_MCC_STATE_H2C_SENT 1
#define MAC_AX_MCC_STATE_H2C_RCVD 2
#define MAC_AX_MCC_ADD_DONE 3
#define MAC_AX_MCC_START_DONE 4
#define MAC_AX_MCC_STOP_DONE 5
#define MAC_AX_MCC_STATE_ERROR 6
u8 mcc_group[4];
#define MAC_AX_MCC_REQ_IDLE 0
#define MAC_AX_MCC_REQ_H2C_SENT 1
#define MAC_AX_MCC_REQ_H2C_RCVD 2
#define MAC_AX_MCC_REQ_DONE 3
#define MAC_AX_MCC_REQ_FAIL 4
u8 mcc_request[4];
#define MAC_AX_FW_RESET_IDLE 0
#define MAC_AX_FW_RESET_RECV 1
#define MAC_AX_FW_RESET_RECV_DONE 2
#define MAC_AX_FW_RESET_PROCESS 3
u8 fw_rst;
#define MAC_AX_AOAC_RPT_IDLE 0
#define MAC_AX_AOAC_RPT_H2C_SENDING 1
#define MAC_AX_AOAC_RPT_H2C_RCVD 2
#define MAC_AX_AOAC_RPT_H2C_DONE 3
#define MAC_AX_AOAC_RPT_ERROR 4
u8 aoac_rpt;
#define MAC_AX_P2P_ACT_IDLE 0
#define MAC_AX_P2P_ACT_BUSY 1
#define MAC_AX_P2P_ACT_FAIL 2
u8 p2p_stat;
#define MAC_AX_FUNC_OFF 0
#define MAC_AX_FUNC_ON 1
u8 dmac_func;
u8 cmac0_func;
u8 cmac1_func;
u8 bb0_func;
u8 bb1_func;
#define MAC_AX_WOW_STOPTRX_IDLE 0
#define MAC_AX_WOW_STOPTRX_BUSY 1
#define MAC_AX_WOW_STOPTRX_FAIL 2
u8 wow_stoptrx_stat;
#define MAC_AX_MAC_NOT_RDY 0
#define MAC_AX_MAC_RDY 1
#define MAC_AX_MAC_INIT_ERR 2
#define MAC_AX_MAC_DEINIT_ERR 3
#define MAC_AX_MAC_FINIT_ERR 4
#define MAC_AX_MAC_FDEINIT_ERR 5
u8 mac_rdy;
#define MAC_AX_ROLE_ALOC_SUCC 0
#define MAC_AX_ROLE_INIT_SUCC 1
#define MAC_AX_ROLE_HW_UPD_SUCC 2
#define MAC_AX_ROLE_ALOC_FAIL 3
#define MAC_AX_ROLE_INIT_FAIL 4
#define MAC_AX_ROLE_HW_UPD_FAIL 5
u8 role_stat;
#define MAC_AX_PLAT_OFF 0
#define MAC_AX_PLAT_ON 1
u8 plat;
#define MAC_AX_IO_ST_NORM 0
#define MAC_AX_IO_ST_HANG 1
u8 io_st;
#define MAC_AX_L2_DIS 0
#define MAC_AX_L2_EN 1
#define MAC_AX_L2_TRIG 2
u8 l2_st;
#define MAC_AX_SER_CTRL_SRT 0
#define MAC_AX_SER_CTRL_STOP 1
#define MAC_AX_SER_CTRL_ERR 2
u8 ser_ctrl_st;
};
#define MAC_AX_DFLT_SM \
{MAC_AX_PWR_OFF, MAC_AX_FWDL_IDLE, MAC_AX_EFUSE_IDLE, \
MAC_AX_OFLD_REQ_IDLE, MAC_AX_OFLD_REQ_IDLE, MAC_AX_OFLD_REQ_IDLE, \
MAC_AX_CMD_OFLD_IDLE, MAC_AX_OFLD_H2C_IDLE, MAC_AX_OFLD_H2C_IDLE, \
MAC_AX_OFLD_H2C_IDLE, MAC_AX_OFLD_H2C_IDLE, MAC_AX_OFLD_H2C_IDLE, \
MAC_AX_OFLD_H2C_IDLE, {MAC_AX_MCC_EMPTY}, {MAC_AX_MCC_REQ_IDLE}, \
MAC_AX_FW_RESET_IDLE, MAC_AX_AOAC_RPT_IDLE, MAC_AX_P2P_ACT_IDLE, \
MAC_AX_FUNC_OFF, MAC_AX_FUNC_OFF, MAC_AX_FUNC_OFF, MAC_AX_FUNC_OFF, \
MAC_AX_FUNC_OFF, MAC_AX_WOW_STOPTRX_IDLE, MAC_AX_MAC_NOT_RDY, \
MAC_AX_ROLE_ALOC_SUCC, MAC_AX_PLAT_OFF, MAC_AX_IO_ST_NORM, \
MAC_AX_L2_EN, MAC_AX_SER_CTRL_SRT}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/state_mach.h
|
C
|
agpl-3.0
| 6,746
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "status.h"
u32 mac_get_ft_status(struct mac_ax_adapter *adapter,
enum mac_ax_feature mac_ft, enum mac_ax_status *stat,
u8 *buf, const u32 size, u32 *ret_size)
{
struct mac_ax_ft_status *ft_stat;
ft_stat = mac_get_ft(adapter, mac_ft);
if (!ft_stat)
return MACNOITEM;
if (!buf)
return MACNPTR;
*stat = ft_stat->status;
if (ft_stat->size) {
if (size < ft_stat->size)
return MACNOBUF;
PLTFM_MEMCMP(buf, ft_stat->buf, ft_stat->size);
*ret_size = ft_stat->size;
}
return MACSUCCESS;
}
struct mac_ax_ft_status *mac_get_ft(struct mac_ax_adapter *adapter,
enum mac_ax_feature mac_ft)
{
struct mac_ax_ft_status *ft_stat = adapter->ft_stat;
for (; ft_stat->mac_ft != MAC_AX_FT_MAX; ft_stat++) {
if (ft_stat->mac_ft == mac_ft)
return ft_stat;
}
PLTFM_MSG_ERR("The mac feature is not supported\n");
return NULL;
}
u32 set_hw_ch_busy_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_ch_busy_cnt_cfg *cfg)
{
u8 band;
u32 ret;
u32 reg_addr;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
band = cfg->band;
reg_addr = (band ? R_AX_PTCL_ATM_C1 : R_AX_PTCL_ATM);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
switch (cfg->cnt_ctrl) {
case MAC_AX_CH_BUSY_CNT_CTRL_CNT_EN:
MAC_REG_W32(reg_addr,
MAC_REG_R32(reg_addr) | B_AX_CHNL_INFO_EN);
break;
case MAC_AX_CH_BUSY_CNT_CTRL_CNT_DIS:
MAC_REG_W32(reg_addr,
MAC_REG_R32(reg_addr) & ~B_AX_CHNL_INFO_EN);
break;
case MAC_AX_CH_BUSY_CNT_CTRL_CNT_BUSY_RST:
val32 = MAC_REG_R32(reg_addr);
MAC_REG_W32(reg_addr, val32 | B_AX_RST_CHNL_BUSY);
MAC_REG_W32(reg_addr, val32 & ~B_AX_RST_CHNL_BUSY);
break;
case MAC_AX_CH_BUSY_CNT_CTRL_CNT_IDLE_RST:
val32 = MAC_REG_R32(reg_addr);
MAC_REG_W32(reg_addr, val32 | B_AX_RST_CHNL_IDLE);
MAC_REG_W32(reg_addr, val32 & ~B_AX_RST_CHNL_IDLE);
break;
case MAC_AX_CH_BUSY_CNT_CTRL_CNT_RST:
val32 = MAC_REG_R32(reg_addr);
MAC_REG_W32(reg_addr, val32 |
(B_AX_RST_CHNL_IDLE | B_AX_RST_CHNL_BUSY));
MAC_REG_W32(reg_addr, val32 &
~(B_AX_RST_CHNL_IDLE | B_AX_RST_CHNL_BUSY));
break;
case MAC_AX_CH_BUSY_CNT_CTRL_CNT_REF:
val32 = MAC_REG_R32(reg_addr) &
~(B_AX_CHNL_REF_RX_BASIC_NAV |
B_AX_CHNL_REF_RX_INTRA_NAV |
B_AX_CHNL_REF_DATA_ON |
B_AX_CHNL_REF_EDCCA_P20 |
B_AX_CHNL_REF_CCA_P20 |
B_AX_CHNL_REF_CCA_S20 |
B_AX_CHNL_REF_CCA_S40 |
B_AX_CHNL_REF_CCA_S80 |
B_AX_CHNL_REF_PHY_TXON);
val32 |= (cfg->ref.basic_nav ? B_AX_CHNL_REF_RX_BASIC_NAV : 0) |
(cfg->ref.intra_nav ? B_AX_CHNL_REF_RX_INTRA_NAV : 0) |
(cfg->ref.data_on ? B_AX_CHNL_REF_DATA_ON : 0) |
(cfg->ref.edcca_p20 ? B_AX_CHNL_REF_EDCCA_P20 : 0) |
(cfg->ref.cca_p20 ? B_AX_CHNL_REF_CCA_P20 : 0) |
(cfg->ref.cca_s20 ? B_AX_CHNL_REF_CCA_S20 : 0) |
(cfg->ref.cca_s40 ? B_AX_CHNL_REF_CCA_S40 : 0) |
(cfg->ref.cca_s80 ? B_AX_CHNL_REF_CCA_S80 : 0) |
(cfg->ref.phy_txon ? B_AX_CHNL_REF_PHY_TXON : 0);
MAC_REG_W32(reg_addr, val32);
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 get_hw_ch_stat_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_ch_stat_cnt *cnt)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 band;
u32 ret;
band = cnt->band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
cnt->busy_cnt = MAC_REG_R32(band ? R_AX_CHNL_BUSY_TIME_0_C1 :
R_AX_CHNL_BUSY_TIME_0);
cnt->idle_cnt = MAC_REG_R32(band ? R_AX_CHNL_IDLE_TIME_0_C1 :
R_AX_CHNL_IDLE_TIME_0);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/status.c
|
C
|
agpl-3.0
| 4,278
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_STATUS_H_
#define _MAC_AX_STATUS_H_
#include "../type.h"
#include "trxcfg.h"
/**
* @brief mac_get_ft_status
*
* @param *adapter
* @param mac_ft
* @param *stat
* @param *buf
* @param size
* @param *ret_size
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_ft_status(struct mac_ax_adapter *adapter,
enum mac_ax_feature mac_ft, enum mac_ax_status *stat,
u8 *buf, const u32 size, u32 *ret_size);
/**
* @brief mac_get_ft
*
* @param *adapter
* @param mac_ft
* @return Please Place Description here.
* @retval mac_ax_ft_status
*/
struct mac_ax_ft_status *mac_get_ft(struct mac_ax_adapter *adapter,
enum mac_ax_feature mac_ft);
/**
* @brief set_hw_ch_busy_cnt
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_ch_busy_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_ch_busy_cnt_cfg *cfg);
/**
* @brief get_hw_ch_stat_cnt
*
* @param *adapter
* @param *cnt
* @return Please Place Description here.
* @retval u32
*/
u32 get_hw_ch_stat_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_ch_stat_cnt *cnt);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/status.h
|
C
|
agpl-3.0
| 1,859
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "tblupd.h"
u32 mac_upd_mudecision_para(struct mac_ax_adapter *adapter,
struct mac_ax_mudecision_para *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_mude_para_tblud *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_mude_para_tblud));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_mude_para_tblud *)buf;
tbl->dword0 =
cpu_to_le32((info->tbl_hdr.rw ? FWCMD_H2C_TBLUD_R_W : 0) |
SET_WORD(info->tbl_hdr.idx, FWCMD_H2C_TBLUD_MACID_GROUP) |
SET_WORD(info->tbl_hdr.offset, FWCMD_H2C_TBLUD_OFFSET) |
SET_WORD(info->tbl_hdr.len, FWCMD_H2C_TBLUD_LENGTH) |
(info->tbl_hdr.type ? FWCMD_H2C_TBLUD_TYPE : 0) |
SET_WORD(CLASS_MUDECISION_PARA,
FWCMD_H2C_TBLUD_TABLE_CLASS));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->mu_thold,
FWCMD_H2C_MUDECISION_PARA_MUINFO_THOLD) |
(info->bypass_thold ?
FWCMD_H2C_MUDECISION_PARA_BYPASS_THOLD : 0) |
(info->bypass_tp ?
FWCMD_H2C_MUDECISION_PARA_BYPASS_TP : 0));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->init_rate,
FWCMD_H2C_MUDECISION_PARA_INIT_RATE) |
SET_WORD(info->retry_th,
FWCMD_H2C_MUDECISION_PARA_RETRY_TH));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_TBLUD,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_upd_ul_fixinfo(struct mac_ax_adapter *adapter,
struct mac_ax_ul_fixinfo *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_ul_fixinfo_tblud *tbl;
struct mac_ul_macid_info *sta_info;
struct mac_ul_macid_info *sta_info_2;
struct mac_ax_ulru_out_sta_ent *sta_ent;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ul_fixinfo_tblud));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_ul_fixinfo_tblud *)buf;
tbl->dword0 =
cpu_to_le32((info->tbl_hdr.rw ? FWCMD_H2C_TBLUD_R_W : 0) |
SET_WORD(info->tbl_hdr.idx, FWCMD_H2C_TBLUD_MACID_GROUP) |
SET_WORD(info->tbl_hdr.offset, FWCMD_H2C_TBLUD_OFFSET) |
SET_WORD(info->tbl_hdr.len, FWCMD_H2C_TBLUD_LENGTH) |
(info->tbl_hdr.type ? FWCMD_H2C_TBLUD_TYPE : 0) |
SET_WORD(CLASS_UL_FIXINFO,
FWCMD_H2C_TBLUD_TABLE_CLASS));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->cfg.mode, FWCMD_H2C_UL_FIXINFO_CFG_MODE) |
SET_WORD(info->cfg.interval,
FWCMD_H2C_UL_FIXINFO_CFG_INTERVAL) |
SET_WORD(info->cfg.bsr_thold,
FWCMD_H2C_UL_FIXINFO_CFG_BSR_THOLD) |
SET_WORD(info->cfg.storemode,
FWCMD_H2C_UL_FIXINFO_CFG_STOREMODE));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->ndpa_dur,
FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_DUR) |
SET_WORD(info->tf_type,
FWCMD_H2C_UL_FIXINFO_ULINFO_TF_TYPE) |
(info->sig_ta_pkten ?
FWCMD_H2C_UL_FIXINFO_ULINFO_SIGEN : 0) |
SET_WORD(info->sig_ta_pktsc,
FWCMD_H2C_UL_FIXINFO_ULINFO_SIGSC) |
(info->murts_flag ?
FWCMD_H2C_UL_FIXINFO_ULINFO_MURTS : 0) |
SET_WORD(info->ndpa,
FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA) |
SET_WORD(info->snd_pkt_sel,
FWCMD_H2C_UL_FIXINFO_ULINFO_SNDPKT) |
SET_WORD(info->gi_ltf,
FWCMD_H2C_UL_FIXINFO_ULINFO_GI_LTF));
tbl->dword3 =
cpu_to_le32(SET_WORD(info->data_rate,
FWCMD_H2C_UL_FIXINFO_ULINFO_DATART) |
(info->data_er ?
FWCMD_H2C_UL_FIXINFO_ULINFO_DATAER : 0) |
SET_WORD(info->data_bw,
FWCMD_H2C_UL_FIXINFO_ULINFO_DATABW) |
SET_WORD(info->data_stbc,
FWCMD_H2C_UL_FIXINFO_ULINFO_STBC) |
(info->data_ldpc ?
FWCMD_H2C_UL_FIXINFO_ULINFO_LDPC : 0) |
(info->data_dcm ?
FWCMD_H2C_UL_FIXINFO_ULINFO_DATADCM : 0) |
SET_WORD(info->apep_len,
FWCMD_H2C_UL_FIXINFO_ULINFO_APEPLEN) |
(info->more_tf ?
FWCMD_H2C_UL_FIXINFO_ULINFO_MORETF : 0) |
(info->data_bw_er ?
FWCMD_H2C_UL_FIXINFO_ULINFO_DATA_VWER : 0) |
(info->istwt ?
FWCMD_H2C_UL_FIXINFO_ULINFO_ISTWT : 0));
tbl->dword4 =
cpu_to_le32(SET_WORD(info->multiport_id,
FWCMD_H2C_UL_FIXINFO_ULINFO_MULTIPORT) |
SET_WORD(info->mbssid,
FWCMD_H2C_UL_FIXINFO_ULINFO_MBSSID) |
SET_WORD(info->txpwr_mode,
FWCMD_H2C_UL_FIXINFO_ULINFO_TXPWR_MODE) |
SET_WORD(info->ulfix_usage,
FWCMD_H2C_UL_FIXINFO_ULINFO_ULFIX_USAGE) |
SET_WORD(info->twtgrp_stanum_sel,
FWCMD_H2C_UL_FIXINFO_ULINFO_TWTGRP_STANUM_SEL) |
SET_WORD(info->store_idx,
FWCMD_H2C_UL_FIXINFO_ULINFO_STORE_IDX));
sta_info = &info->sta[0];
sta_info_2 = &info->sta[1];
tbl->dword5 =
cpu_to_le32(SET_WORD(sta_info->macid,
FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0) |
SET_WORD(sta_info->pref_AC,
FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0) |
SET_WORD(sta_info_2->macid,
FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1) |
SET_WORD(sta_info_2->pref_AC,
FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1));
sta_info = &info->sta[2];
sta_info_2 = &info->sta[3];
tbl->dword6 =
cpu_to_le32(SET_WORD(sta_info->macid,
FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0) |
SET_WORD(sta_info->pref_AC,
FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0) |
SET_WORD(sta_info_2->macid,
FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1) |
SET_WORD(sta_info_2->pref_AC,
FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1));
tbl->dword7 =
cpu_to_le32((info->ulrua.ru2su ?
FWCMD_H2C_UL_FIXINFO_ULRUA_RU2SU : 0) |
SET_WORD(info->ulrua.ppdu_bw,
FWCMD_H2C_UL_FIXINFO_ULRUA_PPDU_BW) |
SET_WORD(info->ulrua.gi_ltf,
FWCMD_H2C_UL_FIXINFO_ULRUA_GI_LTF) |
(info->ulrua.stbc ?
FWCMD_H2C_UL_FIXINFO_ULRUA_STBC : 0) |
(info->ulrua.doppler ?
FWCMD_H2C_UL_FIXINFO_ULRUA_DOPPLER : 0) |
SET_WORD(info->ulrua.n_ltf_and_ma,
FWCMD_H2C_UL_FIXINFO_ULRUA_LTF_MA) |
SET_WORD(info->ulrua.sta_num,
FWCMD_H2C_UL_FIXINFO_ULRUA_STANUM) |
(info->ulrua.rf_gain_fix ?
FWCMD_H2C_UL_FIXINFO_ULRUA_RFGFIX : 0) |
SET_WORD(info->ulrua.rf_gain_idx,
FWCMD_H2C_UL_FIXINFO_ULRUA_RFGIDX) |
SET_WORD(info->ulrua.tb_t_pe_nom,
FWCMD_H2C_UL_FIXINFO_ULRUA_TB_NOM));
tbl->dword8 =
cpu_to_le32((info->ulrua.grp_mode ?
FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_MODE : 0) |
SET_WORD(info->ulrua.grp_id,
FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_ID) |
(info->ulrua.fix_mode ?
FWCMD_H2C_UL_FIXINFO_ULRUA_FIX_MODE : 0));
sta_ent = &info->ulrua.sta[0];
tbl->dword9 =
cpu_to_le32((sta_ent->dropping ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) |
SET_WORD(sta_ent->tgt_rssi,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) |
SET_WORD(sta_ent->mac_id,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) |
SET_WORD(sta_ent->ru_pos,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) |
(sta_ent->coding ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) |
(sta_ent->vip_flag ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0));
tbl->dword10 =
cpu_to_le32(SET_WORD(sta_ent->bsr_length,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) |
(sta_ent->rate.dcm ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) |
SET_WORD(sta_ent->rate.ss,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) |
SET_WORD(sta_ent->rate.mcs,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) |
SET_WORD(sta_ent->rpt.rt_tblcol,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) |
(sta_ent->rpt.prtl_alloc ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) |
(sta_ent->rpt.rate_chg ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0));
sta_ent = &info->ulrua.sta[1];
tbl->dword11 =
cpu_to_le32((sta_ent->dropping ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) |
SET_WORD(sta_ent->tgt_rssi,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) |
SET_WORD(sta_ent->mac_id,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) |
SET_WORD(sta_ent->ru_pos,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) |
(sta_ent->coding ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) |
(sta_ent->vip_flag ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0));
tbl->dword12 =
cpu_to_le32(SET_WORD(sta_ent->bsr_length,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) |
(sta_ent->rate.dcm ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) |
SET_WORD(sta_ent->rate.ss,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) |
SET_WORD(sta_ent->rate.mcs,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) |
SET_WORD(sta_ent->rpt.rt_tblcol,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) |
(sta_ent->rpt.prtl_alloc ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) |
(sta_ent->rpt.rate_chg ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0));
sta_ent = &info->ulrua.sta[2];
tbl->dword13 =
cpu_to_le32((sta_ent->dropping ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) |
SET_WORD(sta_ent->tgt_rssi,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) |
SET_WORD(sta_ent->mac_id,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) |
SET_WORD(sta_ent->ru_pos,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) |
(sta_ent->coding ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) |
(sta_ent->vip_flag ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0));
tbl->dword14 =
cpu_to_le32(SET_WORD(sta_ent->bsr_length,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) |
(sta_ent->rate.dcm ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) |
SET_WORD(sta_ent->rate.ss,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) |
SET_WORD(sta_ent->rate.mcs,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) |
SET_WORD(sta_ent->rpt.rt_tblcol,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) |
(sta_ent->rpt.prtl_alloc ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) |
(sta_ent->rpt.rate_chg ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0));
sta_ent = &info->ulrua.sta[3];
tbl->dword15 =
cpu_to_le32((sta_ent->dropping ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP : 0) |
SET_WORD(sta_ent->tgt_rssi,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI) |
SET_WORD(sta_ent->mac_id,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID) |
SET_WORD(sta_ent->ru_pos,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS) |
(sta_ent->coding ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE : 0) |
(sta_ent->vip_flag ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP : 0));
tbl->dword16 =
cpu_to_le32(SET_WORD(sta_ent->bsr_length,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN) |
(sta_ent->rate.dcm ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM : 0) |
SET_WORD(sta_ent->rate.ss,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS) |
SET_WORD(sta_ent->rate.mcs,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS) |
SET_WORD(sta_ent->rpt.rt_tblcol,
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL) |
(sta_ent->rpt.prtl_alloc ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC : 0) |
(sta_ent->rpt.rate_chg ?
FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_TBLUD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_f2p_test_cmd(struct mac_ax_adapter *adapter,
struct mac_ax_f2p_test_para *info,
struct mac_ax_f2p_wd *f2pwd,
struct mac_ax_f2p_tx_cmd *ptxcmd,
u8 *psigb_addr)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_test_para *tbl;
struct mac_ax_tf_user_para *user;
struct mac_ax_tf_depend_user_para *dep_user;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_test_para));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMSET(buf, 0, sizeof(struct fwcmd_test_para));
tbl = (struct fwcmd_test_para *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(info->tf_pkt.ul_bw, FWCMD_F2PTEST_ULBW) |
SET_WORD(info->tf_pkt.gi_ltf, FWCMD_F2PTEST_GILTF) |
SET_WORD(info->tf_pkt.num_he_ltf, FWCMD_F2PTEST_NUMLTF) |
SET_WORD(info->tf_pkt.ul_stbc, FWCMD_F2PTEST_ULSTBC) |
SET_WORD(info->tf_pkt.doppler, FWCMD_F2PTEST_DPLR) |
SET_WORD(info->tf_pkt.ap_tx_power, FWCMD_F2PTEST_TXPWR) |
SET_WORD(info->tf_pkt.user_num, FWCMD_F2PTEST_USERNUM) |
SET_WORD(info->tf_pkt.pktnum, FWCMD_F2PTEST_PKTNUM) |
SET_WORD(info->tf_pkt.pri20_bitmap, FWCMD_F2PTEST_BITMAP));
user = &info->tf_pkt.user[0];
tbl->dword1 =
cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) |
SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) |
SET_WORD(user->macid, FWCMD_F2PTEST_MACID) |
SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS));
tbl->dword2 =
cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) |
SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) |
SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) |
SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI));
user = &info->tf_pkt.user[1];
tbl->dword3 =
cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) |
SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) |
SET_WORD(user->macid, FWCMD_F2PTEST_MACID) |
SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS));
tbl->dword4 =
cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) |
SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) |
SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) |
SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI));
user = &info->tf_pkt.user[2];
tbl->dword5 =
cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) |
SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) |
SET_WORD(user->macid, FWCMD_F2PTEST_MACID) |
SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS));
tbl->dword6 =
cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) |
SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) |
SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) |
SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI));
user = &info->tf_pkt.user[3];
tbl->dword7 =
cpu_to_le32(SET_WORD(user->aid12, FWCMD_F2PTEST_AID12) |
SET_WORD(user->ul_mcs, FWCMD_F2PTEST_ULMCS) |
SET_WORD(user->macid, FWCMD_F2PTEST_MACID) |
SET_WORD(user->ru_pos, FWCMD_F2PTEST_RUPOS));
tbl->dword8 =
cpu_to_le32(SET_WORD(user->ul_fec_code, FWCMD_F2PTEST_ULFEC) |
SET_WORD(user->ul_dcm, FWCMD_F2PTEST_ULDCM) |
SET_WORD(user->ss_alloc, FWCMD_F2PTEST_SS_ALLOC) |
SET_WORD(user->ul_tgt_rssi, FWCMD_F2PTEST_UL_TGTRSSI));
dep_user = &info->tf_pkt.dep_user[0];
tbl->byte9 =
cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC));
dep_user = &info->tf_pkt.dep_user[1];
tbl->byte10 =
cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC));
dep_user = &info->tf_pkt.dep_user[2];
tbl->byte11 =
cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC));
dep_user = &info->tf_pkt.dep_user[3];
tbl->byte12 =
cpu_to_le32(SET_WORD(dep_user->pref_AC, FWCMD_F2PTEST_PREF_AC));
tbl->dword13 =
cpu_to_le32(SET_WORD(info->tf_wd.datarate, FWCMD_F2PTEST_DATARATE) |
SET_WORD(info->tf_wd.mulport_id, FWCMD_F2PTEST_MULPORT) |
SET_WORD(info->tf_wd.pwr_ofset, FWCMD_F2PTEST_PWR_OFSET) |
SET_WORD(info->mode, FWCMD_F2PTEST_MODE) |
SET_WORD(info->frexch_type, FWCMD_F2PTEST_TYPE) |
SET_WORD(info->sigb_len, FWCMD_F2PTEST_SIGB_LEN));
tbl->dword14 =
cpu_to_le32(SET_WORD(f2pwd->cmd_qsel, F2P_WD_CMD_QSEL) |
(f2pwd->ls ? F2P_WD_LS : 0) |
(f2pwd->fs ? F2P_WD_FS : 0) |
SET_WORD(f2pwd->total_number, F2P_WD_TOTAL_NUMBER) |
SET_WORD(f2pwd->seq, F2P_WD_SEQ) |
SET_WORD(f2pwd->length, F2P_WD_LENGTH));
tbl->dword16 =
cpu_to_le32(SET_WORD(ptxcmd->cmd_type, F2P_CMD_TYPE) |
SET_WORD(ptxcmd->cmd_sub_type, F2P_CMD_SUB_TYPE) |
SET_WORD(ptxcmd->dl_user_num, F2P_DL_USER_NUM) |
SET_WORD(ptxcmd->bw, F2P_BW) |
SET_WORD(ptxcmd->tx_power, F2P_TX_POWER));
tbl->dword17 =
cpu_to_le32(SET_WORD(ptxcmd->fw_define, F2P_FW_DEFINE) |
SET_WORD(ptxcmd->ss_sel_mode, F2P_SS_SEL_MODE) |
SET_WORD(ptxcmd->next_qsel, F2P_NEXT_QSEL) |
SET_WORD(ptxcmd->twt_group, F2P_TWT_GROUP) |
(ptxcmd->dis_chk_slp ? F2P_DIS_CHK_SLP : 0) |
(ptxcmd->ru_mu_2_su ? F2P_RU_MU_2_SU : 0) |
SET_WORD(ptxcmd->dl_t_pe, F2P_DL_T_PE));
tbl->dword18 =
cpu_to_le32(SET_WORD(ptxcmd->sigb_ch1_len, F2P_SIGB_CH1_LEN) |
SET_WORD(ptxcmd->sigb_ch2_len, F2P_SIGB_CH2_LEN) |
SET_WORD(ptxcmd->sigb_sym_num, F2P_SIGB_SYM_NUM) |
SET_WORD(ptxcmd->sigb_ch2_ofs, F2P_SIGB_CH2_OFS) |
(ptxcmd->dis_htp_ack ? F2P_DIS_HTP_ACK : 0) |
SET_WORD(ptxcmd->tx_time_ref, F2P_TX_TIME_REF) |
SET_WORD(ptxcmd->pri_user_idx, F2P_PRI_USER_IDX));
tbl->dword19 =
cpu_to_le32(SET_WORD(ptxcmd->ampdu_max_txtime, F2P_AMPDU_MAX_TXTIME) |
SET_WORD(ptxcmd->group_id, F2P_GROUP_ID) |
(ptxcmd->twt_chk_en ? F2P_TWT_CHK_EN : 0) |
SET_WORD(ptxcmd->twt_port_id, F2P_TWT_PORT_ID));
tbl->dword20 =
cpu_to_le32(SET_WORD(ptxcmd->twt_start_time, F2P_TWT_START_TIME));
tbl->dword21 =
cpu_to_le32(SET_WORD(ptxcmd->twt_end_time, F2P_TWT_END_TIME));
tbl->dword22 =
cpu_to_le32(SET_WORD(ptxcmd->apep_len, F2P_APEP_LEN) |
SET_WORD(ptxcmd->tri_pad, F2P_TRI_PAD) |
SET_WORD(ptxcmd->ul_t_pe, F2P_UL_T_PE) |
SET_WORD(ptxcmd->rf_gain_idx, F2P_RF_GAIN_IDX) |
(ptxcmd->fixed_gain_en ? F2P_FIXED_GAIN_EN : 0) |
SET_WORD(ptxcmd->ul_gi_ltf, F2P_UL_GI_LTF) |
(ptxcmd->ul_doppler ? F2P_UL_DOPPLER : 0) |
(ptxcmd->ul_stbc ? F2P_UL_STBC : 0));
tbl->dword23 =
cpu_to_le32((ptxcmd->ul_mid_per ? F2P_UL_MID_PER : 0) |
(ptxcmd->ul_cqi_rrp_tri ? F2P_UL_CQI_RRP_TRI : 0) |
(ptxcmd->sigb_dcm ? F2P_SIGB_DCM : 0) |
(ptxcmd->sigb_comp ? F2P_SIGB_COMP : 0) |
(ptxcmd->doppler ? F2P_DOPPLER : 0) |
(ptxcmd->stbc ? F2P_STBC : 0) |
(ptxcmd->mid_per ? F2P_MID_PER : 0) |
SET_WORD(ptxcmd->gi_ltf_size, F2P_GI_LTF_SIZE) |
SET_WORD(ptxcmd->sigb_mcs, F2P_SIGB_MCS));
tbl->dword24 =
cpu_to_le32(SET_WORD(ptxcmd->macid_u0, F2P_MACID_U0) |
SET_WORD(ptxcmd->ac_type_u0, F2P_AC_TYPE_U0) |
SET_WORD(ptxcmd->mu_sta_pos_u0, F2P_MU_STA_POS_U0) |
SET_WORD(ptxcmd->dl_rate_idx_u0, F2P_DL_RATE_IDX_U0) |
(ptxcmd->dl_dcm_en_u0 ? F2P_TX_CMD_DL_DCM_EN_U0 : 0) |
SET_WORD(ptxcmd->ru_alo_idx_u0, F2P_RU_ALO_IDX_U0) |
(ptxcmd->rsvd6 ? BIT(22) : 0));
tbl->dword25 =
cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u0, F2P_PWR_BOOST_U0) |
SET_WORD(ptxcmd->agg_bmp_alo_u0, F2P_AGG_BMP_ALO_U0) |
SET_WORD(ptxcmd->ampdu_max_txnum_u0, F2P_AMPDU_MAX_NUM_U0) |
SET_WORD(ptxcmd->user_define_u0, F2P_USER_DEFINE_U0) |
SET_WORD(ptxcmd->user_define_ext_u0, F2P_USER_DEFINE_EXT_U0)
);
tbl->dword26 =
cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u0, F2P_UL_ADDR_IDX_U0) |
(ptxcmd->ul_dcm_u0 ? F2P_UL_DCM_U0 : 0) |
(ptxcmd->ul_fec_cod_u0 ? F2P_UL_FEC_COD_U0 : 0) |
SET_WORD(ptxcmd->ul_ru_rate_u0, F2P_UL_RU_RATE_U0) |
SET_WORD(ptxcmd->ul_ru_alo_idx_u0, F2P_UL_RU_ALO_IDX_U0));
tbl->dword28 =
cpu_to_le32(SET_WORD(ptxcmd->macid_u1, F2P_MACID_U1) |
SET_WORD(ptxcmd->ac_type_u1, F2P_AC_TYPE_U1) |
SET_WORD(ptxcmd->mu_sta_pos_u1, F2P_MU_STA_POS_U1) |
SET_WORD(ptxcmd->dl_rate_idx_u1, F2P_DL_RATE_IDX_U1) |
(ptxcmd->dl_dcm_en_u1 ? F2P_TX_CMD_DL_DCM_EN_U1 : 0) |
SET_WORD(ptxcmd->ru_alo_idx_u1, F2P_RU_ALO_IDX_U1) |
(ptxcmd->rsvd10 ? BIT(22) : 0));
tbl->dword29 =
cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u1, F2P_PWR_BOOST_U1) |
SET_WORD(ptxcmd->agg_bmp_alo_u1, F2P_AGG_BMP_ALO_U1) |
SET_WORD(ptxcmd->ampdu_max_txnum_u1, F2P_AMPDU_MAX_NUM_U1) |
SET_WORD(ptxcmd->user_define_u1, F2P_USER_DEFINE_U1) |
SET_WORD(ptxcmd->user_define_ext_u1, F2P_USER_DEFINE_EXT_U1)
);
tbl->dword30 =
cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u1, F2P_UL_ADDR_IDX_U1) |
(ptxcmd->ul_dcm_u1 ? F2P_UL_DCM_U1 : 0) |
(ptxcmd->ul_fec_cod_u1 ? F2P_UL_FEC_COD_U1 : 0) |
SET_WORD(ptxcmd->ul_ru_rate_u1, F2P_UL_RU_RATE_U1) |
SET_WORD(ptxcmd->ul_ru_alo_idx_u1, F2P_UL_RU_ALO_IDX_U1));
tbl->dword32 =
cpu_to_le32(SET_WORD(ptxcmd->macid_u2, F2P_MACID_U2) |
SET_WORD(ptxcmd->ac_type_u2, F2P_AC_TYPE_U2) |
SET_WORD(ptxcmd->mu_sta_pos_u2, F2P_MU_STA_POS_U2) |
SET_WORD(ptxcmd->dl_rate_idx_u2, F2P_DL_RATE_IDX_U2) |
(ptxcmd->dl_dcm_en_u2 ? F2P_TX_CMD_DL_DCM_EN_U2 : 0) |
SET_WORD(ptxcmd->ru_alo_idx_u2, F2P_RU_ALO_IDX_U2) |
(ptxcmd->rsvd14 ? BIT(22) : 0));
tbl->dword33 =
cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u2, F2P_PWR_BOOST_U2) |
SET_WORD(ptxcmd->agg_bmp_alo_u2, F2P_AGG_BMP_ALO_U2) |
SET_WORD(ptxcmd->ampdu_max_txnum_u2, F2P_AMPDU_MAX_NUM_U2) |
SET_WORD(ptxcmd->user_define_u2, F2P_USER_DEFINE_U2) |
SET_WORD(ptxcmd->user_define_ext_u2, F2P_USER_DEFINE_EXT_U2)
);
tbl->dword34 =
cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u2, F2P_UL_ADDR_IDX_U2) |
(ptxcmd->ul_dcm_u2 ? F2P_UL_DCM_U2 : 0) |
(ptxcmd->ul_fec_cod_u2 ? F2P_UL_FEC_COD_U2 : 0) |
SET_WORD(ptxcmd->ul_ru_rate_u2, F2P_UL_RU_RATE_U2) |
SET_WORD(ptxcmd->ul_ru_alo_idx_u2, F2P_UL_RU_ALO_IDX_U2));
tbl->dword36 =
cpu_to_le32(SET_WORD(ptxcmd->macid_u3, F2P_MACID_U3) |
SET_WORD(ptxcmd->ac_type_u3, F2P_AC_TYPE_U3) |
SET_WORD(ptxcmd->mu_sta_pos_u3, F2P_MU_STA_POS_U3) |
SET_WORD(ptxcmd->dl_rate_idx_u3, F2P_DL_RATE_IDX_U3) |
(ptxcmd->dl_dcm_en_u3 ? F2P_TX_CMD_DL_DCM_EN_U3 : 0) |
SET_WORD(ptxcmd->ru_alo_idx_u3, F2P_RU_ALO_IDX_U3) |
(ptxcmd->rsvd18 ? BIT(22) : 0));
tbl->dword37 =
cpu_to_le32(SET_WORD(ptxcmd->pwr_boost_u3, F2P_PWR_BOOST_U3) |
SET_WORD(ptxcmd->agg_bmp_alo_u3, F2P_AGG_BMP_ALO_U3) |
SET_WORD(ptxcmd->ampdu_max_txnum_u3, F2P_AMPDU_MAX_NUM_U3) |
SET_WORD(ptxcmd->user_define_u3, F2P_USER_DEFINE_U3) |
SET_WORD(ptxcmd->user_define_ext_u3, F2P_USER_DEFINE_EXT_U3)
);
tbl->dword38 =
cpu_to_le32(SET_WORD(ptxcmd->ul_addr_idx_u3, F2P_UL_ADDR_IDX_U3) |
(ptxcmd->ul_dcm_u3 ? F2P_UL_DCM_U3 : 0) |
(ptxcmd->ul_fec_cod_u3 ? F2P_UL_FEC_COD_U3 : 0) |
SET_WORD(ptxcmd->ul_ru_rate_u3, F2P_UL_RU_RATE_U3) |
SET_WORD(ptxcmd->ul_ru_alo_idx_u3, F2P_UL_RU_ALO_IDX_U3));
tbl->dword40 =
cpu_to_le32(SET_WORD(ptxcmd->pkt_id_0, F2P_PKT_ID_0) |
(ptxcmd->valid_0 ? F2P_VALID_0 : 0) |
SET_WORD(ptxcmd->ul_user_num_0, F2P_UL_USER_NUM_0));
tbl->dword41 =
cpu_to_le32(SET_WORD(ptxcmd->pkt_id_1, F2P_PKT_ID_1) |
(ptxcmd->valid_1 ? F2P_VALID_1 : 0) |
SET_WORD(ptxcmd->ul_user_num_1, F2P_UL_USER_NUM_1));
tbl->dword42 =
cpu_to_le32(SET_WORD(ptxcmd->pkt_id_2, F2P_PKT_ID_2) |
(ptxcmd->valid_2 ? F2P_VALID_2 : 0) |
SET_WORD(ptxcmd->ul_user_num_2, F2P_UL_USER_NUM_2));
tbl->dword43 =
cpu_to_le32(SET_WORD(ptxcmd->pkt_id_3, F2P_PKT_ID_3) |
(ptxcmd->valid_3 ? F2P_VALID_3 : 0) |
SET_WORD(ptxcmd->ul_user_num_3, F2P_UL_USER_NUM_3));
tbl->dword44 =
cpu_to_le32(SET_WORD(ptxcmd->pkt_id_4, F2P_PKT_ID_4) |
(ptxcmd->valid_4 ? F2P_VALID_4 : 0) |
SET_WORD(ptxcmd->ul_user_num_4, F2P_UL_USER_NUM_4));
tbl->dword45 =
cpu_to_le32(SET_WORD(ptxcmd->pkt_id_5, F2P_PKT_ID_5) |
(ptxcmd->valid_5 ? F2P_VALID_5 : 0) |
SET_WORD(ptxcmd->ul_user_num_5, F2P_UL_USER_NUM_5));
PLTFM_MEMCPY(tbl->byte46, psigb_addr, info->sigb_len);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_F2P_TEST,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_snd_test_cmd(struct mac_ax_adapter *adapter,
u8 *cmd_buf)
{
return MACSUCCESS;
}
u32 mac_upd_dctl_info(struct mac_ax_adapter *adapter,
struct mac_ax_dctl_info *info,
struct mac_ax_dctl_info *mask, u8 macid, u8 operation)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_dctlinfo_ud *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_dctlinfo_ud));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_dctlinfo_ud *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(macid, FWCMD_H2C_DCTLINFO_UD_MACID) |
(operation ? FWCMD_H2C_DCTLINFO_UD_OP : 0));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->qos_field_h, FWCMD_H2C_DCTRL_QOS_FIELD_H) |
SET_WORD(info->hw_exseq_macid, FWCMD_H2C_DCTRL_HW_EXSEQ_MACID) |
(info->qos_field_h_en ? FWCMD_H2C_DCTRL_QOS_FIELD_H_EN : 0) |
SET_WORD(info->aes_iv_l, FWCMD_H2C_DCTRL_AES_IV_L));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->aes_iv_h, FWCMD_H2C_DCTRL_AES_IV_H));
tbl->dword3 =
cpu_to_le32(SET_WORD(info->seq0, FWCMD_H2C_DCTRL_SEQ0) |
SET_WORD(info->seq1, FWCMD_H2C_DCTRL_SEQ1) |
SET_WORD(info->amsdu_max_length, FWCMD_H2C_DCTRL_AMSDU_MAX_LEN) |
(info->sta_amsdu_en ? FWCMD_H2C_DCTRL_STA_AMSDU_EN : 0) |
(info->chksum_offload_en ? FWCMD_H2C_DCTRL_CHKSUM_OFLD_EN : 0) |
(info->with_llc ? FWCMD_H2C_DCTRL_WITH_LLC : 0) |
(info->sec_hw_enc ? FWCMD_H2C_DCTRL_SEC_HW_ENC : 0));
tbl->dword4 =
cpu_to_le32(SET_WORD(info->seq2, FWCMD_H2C_DCTRL_SEQ2) |
SET_WORD(info->seq3, FWCMD_H2C_DCTRL_SEQ3) |
SET_WORD(info->sec_cam_idx, FWCMD_H2C_DCTRL_SEC_CAM_IDX));
tbl->dword5 =
cpu_to_le32(SET_WORD(mask->qos_field_h, FWCMD_H2C_DCTRL_QOS_FIELD_H) |
SET_WORD(mask->hw_exseq_macid, FWCMD_H2C_DCTRL_HW_EXSEQ_MACID) |
(mask->qos_field_h_en ? FWCMD_H2C_DCTRL_QOS_FIELD_H_EN : 0) |
SET_WORD(mask->aes_iv_l, FWCMD_H2C_DCTRL_AES_IV_L));
tbl->dword6 =
cpu_to_le32(SET_WORD(mask->aes_iv_h, FWCMD_H2C_DCTRL_AES_IV_H));
tbl->dword7 =
cpu_to_le32(SET_WORD(mask->seq0, FWCMD_H2C_DCTRL_SEQ0) |
SET_WORD(mask->seq1, FWCMD_H2C_DCTRL_SEQ1) |
SET_WORD(mask->amsdu_max_length, FWCMD_H2C_DCTRL_AMSDU_MAX_LEN) |
(mask->sta_amsdu_en ? FWCMD_H2C_DCTRL_STA_AMSDU_EN : 0) |
(mask->chksum_offload_en ? FWCMD_H2C_DCTRL_CHKSUM_OFLD_EN : 0) |
(mask->with_llc ? FWCMD_H2C_DCTRL_WITH_LLC : 0) |
(mask->sec_hw_enc ? FWCMD_H2C_DCTRL_SEC_HW_ENC : 0));
tbl->dword8 =
cpu_to_le32(SET_WORD(mask->seq2, FWCMD_H2C_DCTRL_SEQ2) |
SET_WORD(mask->seq3, FWCMD_H2C_DCTRL_SEQ3) |
SET_WORD(mask->sec_cam_idx, FWCMD_H2C_DCTRL_SEC_CAM_IDX));
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_DCTLINFO_UD,
0,
1);
if (ret)
goto fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
} else {
#if MAC_AX_FEATURE_DBGPKG
if (operation)
dctl_info_debug_write(adapter, macid,
(struct fwcmd_dctlinfo_ud *)buf);
#else
return MACFWNONRDY;
#endif
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_upd_shcut_mhdr(struct mac_ax_adapter *adapter,
struct mac_ax_shcut_mhdr *info, u8 shcut_camid)
{
u32 ret = 0;
u32 i;
u8 *buf;
u32 *src, *dest;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_shcut_update *tbl;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACNOTSUP;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_shcut_update));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_shcut_update *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(shcut_camid, FWCMD_H2C_DCTLINFO_UD_MACID));
src = (u32 *)info;
dest = (u32 *)(&tbl->dword1);
for (i = 0; i < (sizeof(struct mac_ax_shcut_mhdr) / 4); i++)
*(dest++) = *(src++);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_SHCUT_UPDATE,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
void _set_role_cctrl(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_info *info,
struct mac_ax_cctl_info *mask,
struct mac_ax_cctl_info *cctrl)
{
cctrl->datarate = (cctrl->datarate & ~mask->datarate) |
(mask->datarate & info->datarate);
cctrl->force_txop = (cctrl->force_txop & ~mask->force_txop) |
(mask->force_txop & info->force_txop);
cctrl->data_bw = (cctrl->data_bw & ~mask->data_bw) |
(mask->data_bw & info->data_bw);
cctrl->data_gi_ltf = (cctrl->data_gi_ltf & ~mask->data_gi_ltf) |
(mask->data_gi_ltf & info->data_gi_ltf);
cctrl->darf_tc_index = (cctrl->darf_tc_index & ~mask->darf_tc_index) |
(mask->darf_tc_index & info->darf_tc_index);
cctrl->arfr_ctrl = (cctrl->arfr_ctrl & ~mask->arfr_ctrl) |
(mask->arfr_ctrl & info->arfr_ctrl);
cctrl->acq_rpt_en = (cctrl->acq_rpt_en & ~mask->acq_rpt_en) |
(mask->acq_rpt_en & info->acq_rpt_en);
cctrl->mgq_rpt_en = (cctrl->mgq_rpt_en & ~mask->mgq_rpt_en) |
(mask->mgq_rpt_en & info->mgq_rpt_en);
cctrl->ulq_rpt_en = (cctrl->ulq_rpt_en & ~mask->ulq_rpt_en) |
(mask->ulq_rpt_en & info->ulq_rpt_en);
cctrl->twtq_rpt_en = (cctrl->twtq_rpt_en & ~mask->twtq_rpt_en) |
(mask->twtq_rpt_en & info->twtq_rpt_en);
cctrl->disrtsfb = (cctrl->disrtsfb & ~mask->disrtsfb) |
(mask->disrtsfb & info->disrtsfb);
cctrl->disdatafb = (cctrl->disdatafb & ~mask->disdatafb) |
(mask->disdatafb & info->disdatafb);
cctrl->tryrate = (cctrl->tryrate & ~mask->tryrate) |
(mask->tryrate & info->tryrate);
cctrl->ampdu_density = (cctrl->ampdu_density & ~mask->ampdu_density) |
(mask->ampdu_density & info->ampdu_density);
cctrl->data_rty_lowest_rate =
(cctrl->data_rty_lowest_rate &
~mask->data_rty_lowest_rate) |
(mask->data_rty_lowest_rate &
info->data_rty_lowest_rate);
cctrl->ampdu_time_sel = (cctrl->ampdu_time_sel &
~mask->ampdu_time_sel) |
(mask->ampdu_time_sel & info->ampdu_time_sel);
cctrl->ampdu_len_sel = (cctrl->ampdu_len_sel & ~mask->ampdu_len_sel) |
(mask->ampdu_len_sel & info->ampdu_len_sel);
cctrl->rts_txcnt_lmt_sel =
(cctrl->rts_txcnt_lmt_sel & ~mask->rts_txcnt_lmt_sel) |
(mask->rts_txcnt_lmt_sel & info->rts_txcnt_lmt_sel);
cctrl->rts_txcnt_lmt = (cctrl->rts_txcnt_lmt & ~mask->rts_txcnt_lmt) |
(mask->rts_txcnt_lmt & info->rts_txcnt_lmt);
cctrl->rtsrate = (cctrl->rtsrate & ~mask->rtsrate) |
(mask->rtsrate & info->rtsrate);
cctrl->vcs_stbc = (cctrl->vcs_stbc & ~mask->vcs_stbc) |
(mask->vcs_stbc & info->vcs_stbc);
cctrl->rts_rty_lowest_rate =
(cctrl->rts_rty_lowest_rate &
~mask->rts_rty_lowest_rate) |
(mask->rts_rty_lowest_rate & info->rts_rty_lowest_rate);
cctrl->data_tx_cnt_lmt =
(cctrl->data_tx_cnt_lmt & ~mask->data_tx_cnt_lmt) |
(mask->data_tx_cnt_lmt & info->data_tx_cnt_lmt);
cctrl->data_txcnt_lmt_sel =
(cctrl->data_txcnt_lmt_sel &
~mask->data_txcnt_lmt_sel) |
(mask->data_txcnt_lmt_sel & info->data_txcnt_lmt_sel);
cctrl->max_agg_num_sel = (cctrl->max_agg_num_sel &
~mask->max_agg_num_sel) |
(mask->max_agg_num_sel & info->max_agg_num_sel);
cctrl->rts_en = (cctrl->rts_en & ~mask->rts_en) |
(mask->rts_en & info->rts_en);
cctrl->cts2self_en = (cctrl->cts2self_en & ~mask->cts2self_en) |
(mask->cts2self_en & info->cts2self_en);
cctrl->cca_rts = (cctrl->cca_rts & ~mask->cca_rts) |
(mask->cca_rts & info->cca_rts);
cctrl->hw_rts_en = (cctrl->hw_rts_en & ~mask->hw_rts_en) |
(mask->hw_rts_en & info->hw_rts_en);
cctrl->rts_drop_data_mode =
(cctrl->rts_drop_data_mode &
~mask->rts_drop_data_mode) |
(mask->rts_drop_data_mode & info->rts_drop_data_mode);
cctrl->ampdu_max_len = (cctrl->ampdu_max_len & ~mask->ampdu_max_len) |
(mask->ampdu_max_len & info->ampdu_max_len);
cctrl->ul_mu_dis = (cctrl->ul_mu_dis & ~mask->ul_mu_dis) |
(mask->ul_mu_dis & info->ul_mu_dis);
cctrl->ampdu_max_time = (cctrl->ampdu_max_time &
~mask->ampdu_max_time) |
(mask->ampdu_max_time & info->ampdu_max_time);
cctrl->max_agg_num = (cctrl->ampdu_max_time & ~mask->max_agg_num) |
(mask->ampdu_max_time & info->max_agg_num);
cctrl->ba_bmap = (cctrl->ba_bmap & ~mask->ba_bmap) |
(mask->ba_bmap & info->ba_bmap);
cctrl->vo_lftime_sel = (cctrl->vo_lftime_sel & ~mask->vo_lftime_sel) |
(mask->vo_lftime_sel & info->vo_lftime_sel);
cctrl->vi_lftime_sel = (cctrl->vi_lftime_sel & ~mask->vi_lftime_sel) |
(mask->vi_lftime_sel & info->vi_lftime_sel);
cctrl->be_lftime_sel = (cctrl->be_lftime_sel & ~mask->be_lftime_sel) |
(mask->be_lftime_sel & info->be_lftime_sel);
cctrl->bk_lftime_sel = (cctrl->bk_lftime_sel & ~mask->bk_lftime_sel) |
(mask->bk_lftime_sel & info->bk_lftime_sel);
cctrl->sectype = (cctrl->bk_lftime_sel & ~mask->sectype) |
(mask->bk_lftime_sel & info->sectype);
cctrl->multi_port_id = (cctrl->multi_port_id & ~mask->multi_port_id) |
(mask->multi_port_id & info->multi_port_id);
cctrl->bmc = (cctrl->multi_port_id & ~mask->bmc) |
(mask->multi_port_id & info->bmc);
cctrl->mbssid = (cctrl->mbssid & ~mask->mbssid) |
(mask->mbssid & info->mbssid);
cctrl->navusehdr = (cctrl->navusehdr & ~mask->navusehdr) |
(mask->navusehdr & info->navusehdr);
cctrl->txpwr_mode = (cctrl->txpwr_mode & ~mask->txpwr_mode) |
(mask->txpwr_mode & info->txpwr_mode);
cctrl->data_dcm = (cctrl->data_dcm & ~mask->data_dcm) |
(mask->data_dcm & info->data_dcm);
cctrl->data_er = (cctrl->data_er & ~mask->data_er) |
(mask->data_er & info->data_er);
cctrl->data_ldpc = (cctrl->data_ldpc & ~mask->data_ldpc) |
(mask->data_ldpc & info->data_ldpc);
cctrl->data_stbc = (cctrl->data_stbc & ~mask->data_stbc) |
(mask->data_stbc & info->data_stbc);
cctrl->a_ctrl_bqr = (cctrl->a_ctrl_bqr & ~mask->a_ctrl_bqr) |
(mask->a_ctrl_bqr & info->a_ctrl_bqr);
cctrl->a_ctrl_uph = (cctrl->a_ctrl_uph & ~mask->a_ctrl_uph) |
(mask->a_ctrl_uph & info->a_ctrl_uph);
cctrl->a_ctrl_bsr = (cctrl->a_ctrl_bsr & ~mask->a_ctrl_bsr) |
(mask->a_ctrl_bsr & info->a_ctrl_bsr);
cctrl->a_ctrl_cas = (cctrl->a_ctrl_cas & ~mask->a_ctrl_cas) |
(mask->a_ctrl_cas & info->a_ctrl_cas);
cctrl->data_bw_er = (cctrl->data_bw_er & ~mask->data_bw_er) |
(mask->data_bw_er & info->data_bw_er);
cctrl->lsig_txop_en = (cctrl->lsig_txop_en & ~mask->lsig_txop_en) |
(mask->lsig_txop_en & info->lsig_txop_en);
cctrl->ctrl_cnt_vld = (cctrl->ctrl_cnt_vld & ~mask->ctrl_cnt_vld) |
(mask->ctrl_cnt_vld & info->ctrl_cnt_vld);
cctrl->ctrl_cnt = (cctrl->ctrl_cnt & ~mask->ctrl_cnt) |
(mask->ctrl_cnt & info->ctrl_cnt);
cctrl->resp_ref_rate = (cctrl->resp_ref_rate & ~mask->resp_ref_rate) |
(mask->resp_ref_rate & info->resp_ref_rate);
cctrl->all_ack_support =
(cctrl->all_ack_support & ~mask->all_ack_support) |
(mask->all_ack_support & info->all_ack_support);
cctrl->bsr_queue_size_format =
(cctrl->bsr_queue_size_format &
~mask->bsr_queue_size_format) |
(mask->bsr_queue_size_format &
info->bsr_queue_size_format);
cctrl->ntx_path_en = (cctrl->ntx_path_en & ~mask->ntx_path_en) |
(mask->ntx_path_en & info->ntx_path_en);
cctrl->path_map_a = (cctrl->ntx_path_en & ~mask->path_map_a) |
(mask->ntx_path_en & info->path_map_a);
cctrl->path_map_b = (cctrl->path_map_b & ~mask->path_map_b) |
(mask->path_map_b & info->path_map_b);
cctrl->path_map_c = (cctrl->path_map_c & ~mask->path_map_c) |
(mask->path_map_c & info->path_map_c);
cctrl->path_map_d = (cctrl->path_map_d & ~mask->path_map_d) |
(mask->path_map_d & info->path_map_d);
cctrl->antsel_a = (cctrl->antsel_a & ~mask->antsel_a) |
(mask->antsel_a & info->antsel_a);
cctrl->antsel_b = (cctrl->antsel_b & ~mask->antsel_b) |
(mask->antsel_b & info->antsel_b);
cctrl->antsel_c = (cctrl->antsel_c & ~mask->antsel_c) |
(mask->antsel_c & info->antsel_c);
cctrl->antsel_d = (cctrl->antsel_d & ~mask->antsel_d) |
(mask->antsel_d & info->antsel_d);
cctrl->addr_cam_index = (cctrl->addr_cam_index &
~mask->addr_cam_index) |
(mask->addr_cam_index & info->addr_cam_index);
cctrl->paid = (cctrl->paid & ~mask->paid) |
(mask->paid & info->paid);
cctrl->uldl = (cctrl->uldl & ~mask->uldl) |
(mask->uldl & info->uldl);
cctrl->doppler_ctrl = (cctrl->doppler_ctrl & ~mask->doppler_ctrl) |
(mask->doppler_ctrl & info->doppler_ctrl);
cctrl->nominal_pkt_padding =
(cctrl->nominal_pkt_padding &
~mask->nominal_pkt_padding) |
(mask->nominal_pkt_padding & info->nominal_pkt_padding);
cctrl->nominal_pkt_padding40 =
(cctrl->nominal_pkt_padding40 &
~mask->nominal_pkt_padding40) |
(mask->nominal_pkt_padding40 &
info->nominal_pkt_padding40);
cctrl->nominal_pkt_padding80 =
(cctrl->nominal_pkt_padding80 &
~mask->nominal_pkt_padding80) |
(mask->nominal_pkt_padding80 &
info->nominal_pkt_padding80);
cctrl->txpwr_tolerence =
(cctrl->txpwr_tolerence & ~mask->txpwr_tolerence) |
(mask->txpwr_tolerence & info->txpwr_tolerence);
cctrl->nc = (cctrl->nc & ~mask->nc) |
(mask->nc & info->nc);
cctrl->nr = (cctrl->nr & ~mask->nr) |
(mask->nr & info->nr);
cctrl->ng = (cctrl->ng & ~mask->ng) |
(mask->ng & info->ng);
cctrl->cb = (cctrl->cb & ~mask->cb) |
(mask->cb & info->cb);
cctrl->cs = (cctrl->cs & ~mask->cs) |
(mask->cs & info->cs);
cctrl->csi_txbf_en = (cctrl->csi_txbf_en & ~mask->csi_txbf_en) |
(mask->csi_txbf_en & info->csi_txbf_en);
cctrl->csi_stbc_en = (cctrl->csi_stbc_en & ~mask->csi_stbc_en) |
(mask->csi_stbc_en & info->csi_stbc_en);
cctrl->csi_ldpc_en = (cctrl->csi_ldpc_en & ~mask->csi_ldpc_en) |
(mask->csi_ldpc_en & info->csi_ldpc_en);
cctrl->csi_para_en = (cctrl->csi_para_en & ~mask->csi_para_en) |
(mask->csi_para_en & info->csi_para_en);
cctrl->csi_fix_rate = (cctrl->csi_fix_rate & ~mask->csi_fix_rate) |
(mask->csi_fix_rate & info->csi_fix_rate);
cctrl->csi_gi_ltf = (cctrl->csi_gi_ltf & ~mask->csi_gi_ltf) |
(mask->csi_gi_ltf & info->csi_gi_ltf);
cctrl->nominal_pkt_padding160 =
(cctrl->nominal_pkt_padding160 &
~mask->nominal_pkt_padding160) |
(mask->nominal_pkt_padding160 &
info->nominal_pkt_padding160);
cctrl->csi_bw = (cctrl->csi_bw & ~mask->csi_bw) |
(mask->csi_bw & info->csi_bw);
}
void mac_upd_role_cctrl(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_info *info,
struct mac_ax_cctl_info *mask, u8 macid)
{
struct mac_role_tbl *role;
role = mac_role_srch(adapter, macid);
if (!role) {
PLTFM_MSG_ERR("role search failed\n");
return;
}
_set_role_cctrl(adapter, info, mask, &role->info.c_info);
}
u32 mac_upd_cctl_info(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_info *info,
struct mac_ax_cctl_info *mask, u8 macid, u8 operation)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_cctlinfo_ud *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_cctlinfo_ud));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_cctlinfo_ud *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(macid, FWCMD_H2C_CCTLINFO_UD_MACID) |
(operation ? FWCMD_H2C_CCTLINFO_UD_OP : 0));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->datarate, FWCMD_H2C_CCTRL_DATARATE) |
(info->force_txop ? FWCMD_H2C_CCTRL_FORCE_TXOP : 0) |
SET_WORD(info->data_bw, FWCMD_H2C_CCTRL_DATA_BW) |
SET_WORD(info->data_gi_ltf, FWCMD_H2C_CCTRL_DATA_GI_LTF) |
(info->darf_tc_index ? FWCMD_H2C_CCTRL_DARF_TC_INDEX : 0) |
SET_WORD(info->arfr_ctrl, FWCMD_H2C_CCTRL_ARFR_CTRL) |
(info->acq_rpt_en ? FWCMD_H2C_CCTRL_ACQ_RPT_EN : 0) |
(info->mgq_rpt_en ? FWCMD_H2C_CCTRL_MGQ_RPT_EN : 0) |
(info->ulq_rpt_en ? FWCMD_H2C_CCTRL_ULQ_RPT_EN : 0) |
(info->twtq_rpt_en ? FWCMD_H2C_CCTRL_TWTQ_RPT_EN : 0) |
(info->disrtsfb ? FWCMD_H2C_CCTRL_DISRTSFB : 0) |
(info->disdatafb ? FWCMD_H2C_CCTRL_DISDATAFB : 0) |
(info->tryrate ? FWCMD_H2C_CCTRL_TRYRATE : 0) |
SET_WORD(info->ampdu_density, FWCMD_H2C_CCTRL_AMPDU_DENSITY));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->data_rty_lowest_rate,
FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE) |
(info->ampdu_time_sel ? FWCMD_H2C_CCTRL_AMPDU_TIME_SEL : 0) |
(info->ampdu_len_sel ? FWCMD_H2C_CCTRL_AMPDU_LEN_SEL : 0) |
(info->rts_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SEL :
0) |
SET_WORD(info->rts_txcnt_lmt, FWCMD_H2C_CCTRL_RTS_TXCNT_LMT) |
SET_WORD(info->rtsrate, FWCMD_H2C_CCTRL_RTSRATE) |
(info->vcs_stbc ? FWCMD_H2C_CCTRL_VCS_STBC : 0) |
SET_WORD(info->rts_rty_lowest_rate,
FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE));
tbl->dword3 =
cpu_to_le32(SET_WORD(info->data_tx_cnt_lmt, FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT) |
(info->data_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_DATA_TXCNT_LMT_SEL :
0) |
(info->max_agg_num_sel ? FWCMD_H2C_CCTRL_MAX_AGG_NUM_SEL : 0) |
(info->rts_en ? FWCMD_H2C_CCTRL_RTS_EN : 0) |
(info->cts2self_en ? FWCMD_H2C_CCTRL_CTS2SELF_EN : 0) |
SET_WORD(info->cca_rts, FWCMD_H2C_CCTRL_CCA_RTS) |
(info->hw_rts_en ? FWCMD_H2C_CCTRL_HW_RTS_EN : 0) |
SET_WORD(info->rts_drop_data_mode,
FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE) |
SET_WORD(info->ampdu_max_len, FWCMD_H2C_CCTRL_AMPDU_MAX_LEN) |
(info->ul_mu_dis ? FWCMD_H2C_CCTRL_UL_MU_DIS : 0) |
SET_WORD(info->ampdu_max_time, FWCMD_H2C_CCTRL_AMPDU_MAX_TIME));
tbl->dword4 =
cpu_to_le32(SET_WORD(info->max_agg_num, FWCMD_H2C_CCTRL_MAX_AGG_NUM) |
SET_WORD(info->ba_bmap, FWCMD_H2C_CCTRL_BA_BMAP) |
SET_WORD(info->vo_lftime_sel, FWCMD_H2C_CCTRL_VO_LFTIME_SEL) |
SET_WORD(info->vi_lftime_sel, FWCMD_H2C_CCTRL_VI_LFTIME_SEL) |
SET_WORD(info->be_lftime_sel, FWCMD_H2C_CCTRL_BE_LFTIME_SEL) |
SET_WORD(info->bk_lftime_sel, FWCMD_H2C_CCTRL_BK_LFTIME_SEL) |
SET_WORD(info->sectype, FWCMD_H2C_CCTRL_SECTYPE));
tbl->dword5 =
cpu_to_le32(SET_WORD(info->multi_port_id, FWCMD_H2C_CCTRL_MULTI_PORT_ID) |
(info->bmc ? FWCMD_H2C_CCTRL_BMC : 0) |
SET_WORD(info->mbssid, FWCMD_H2C_CCTRL_MBSSID) |
(info->navusehdr ? FWCMD_H2C_CCTRL_NAVUSEHDR : 0) |
SET_WORD(info->txpwr_mode, FWCMD_H2C_CCTRL_TXPWR_MODE) |
(info->data_dcm ? FWCMD_H2C_CCTRL_DATA_DCM : 0) |
(info->data_er ? FWCMD_H2C_CCTRL_DATA_ER : 0) |
(info->data_ldpc ? FWCMD_H2C_CCTRL_DATA_LDPC : 0) |
(info->data_stbc ? FWCMD_H2C_CCTRL_DATA_STBC : 0) |
(info->a_ctrl_bqr ? FWCMD_H2C_CCTRL_A_CTRL_BQR : 0) |
(info->a_ctrl_uph ? FWCMD_H2C_CCTRL_A_CTRL_UPH : 0) |
(info->a_ctrl_bsr ? FWCMD_H2C_CCTRL_A_CTRL_BSR : 0) |
(info->a_ctrl_cas ? FWCMD_H2C_CCTRL_A_CTRL_CAS : 0) |
(info->data_bw_er ? FWCMD_H2C_CCTRL_DATA_BW_ER : 0) |
(info->lsig_txop_en ? FWCMD_H2C_CCTRL_LSIG_TXOP_EN : 0) |
(info->ctrl_cnt_vld ? FWCMD_H2C_CCTRL_CTRL_CNT_VLD : 0) |
SET_WORD(info->ctrl_cnt, FWCMD_H2C_CCTRL_CTRL_CNT));
tbl->dword6 =
cpu_to_le32(SET_WORD(info->resp_ref_rate, FWCMD_H2C_CCTRL_RESP_REF_RATE) |
(info->all_ack_support ? FWCMD_H2C_CCTRL_ALL_ACK_SUPPORT : 0) |
(info->bsr_queue_size_format ?
FWCMD_H2C_CCTRL_BSR_QUEUE_SIZE_FORMAT : 0) |
SET_WORD(info->ntx_path_en, FWCMD_H2C_CCTRL_NTX_PATH_EN) |
SET_WORD(info->path_map_a, FWCMD_H2C_CCTRL_PATH_MAP_A) |
SET_WORD(info->path_map_b, FWCMD_H2C_CCTRL_PATH_MAP_B) |
SET_WORD(info->path_map_c, FWCMD_H2C_CCTRL_PATH_MAP_C) |
SET_WORD(info->path_map_d, FWCMD_H2C_CCTRL_PATH_MAP_D) |
(info->antsel_a ? FWCMD_H2C_CCTRL_ANTSEL_A : 0) |
(info->antsel_b ? FWCMD_H2C_CCTRL_ANTSEL_B : 0) |
(info->antsel_c ? FWCMD_H2C_CCTRL_ANTSEL_C : 0) |
(info->antsel_d ? FWCMD_H2C_CCTRL_ANTSEL_D : 0));
tbl->dword7 =
cpu_to_le32(SET_WORD(info->addr_cam_index, FWCMD_H2C_CCTRL_ADDR_CAM_INDEX) |
SET_WORD(info->paid, FWCMD_H2C_CCTRL_PAID) |
(info->uldl ? FWCMD_H2C_CCTRL_ULDL : 0) |
SET_WORD(info->doppler_ctrl, FWCMD_H2C_CCTRL_DOPPLER_CTRL) |
SET_WORD(info->nominal_pkt_padding,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING) |
SET_WORD(info->nominal_pkt_padding40,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40) |
SET_WORD(info->nominal_pkt_padding80,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80) |
SET_WORD(info->txpwr_tolerence, FWCMD_H2C_CCTRL_TXPWR_TOLERENCE));
tbl->dword8 =
cpu_to_le32(SET_WORD(info->nc, FWCMD_H2C_CCTRL_NC) |
SET_WORD(info->nr, FWCMD_H2C_CCTRL_NR) |
SET_WORD(info->ng, FWCMD_H2C_CCTRL_NG) |
SET_WORD(info->cb, FWCMD_H2C_CCTRL_CB) |
SET_WORD(info->cs, FWCMD_H2C_CCTRL_CS) |
(info->csi_txbf_en ? FWCMD_H2C_CCTRL_CSI_TXBF_EN : 0) |
(info->csi_stbc_en ? FWCMD_H2C_CCTRL_CSI_STBC_EN : 0) |
(info->csi_ldpc_en ? FWCMD_H2C_CCTRL_CSI_LDPC_EN : 0) |
(info->csi_para_en ? FWCMD_H2C_CCTRL_CSI_PARA_EN : 0) |
SET_WORD(info->csi_fix_rate, FWCMD_H2C_CCTRL_CSI_FIX_RATE) |
SET_WORD(info->csi_gi_ltf, FWCMD_H2C_CCTRL_CSI_GI_LTF) |
SET_WORD(info->nominal_pkt_padding160,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160) |
SET_WORD(info->csi_bw, FWCMD_H2C_CCTRL_CSI_BW));
tbl->dword9 =
cpu_to_le32(SET_WORD(mask->datarate, FWCMD_H2C_CCTRL_DATARATE) |
(mask->force_txop ? FWCMD_H2C_CCTRL_FORCE_TXOP : 0) |
SET_WORD(mask->data_bw, FWCMD_H2C_CCTRL_DATA_BW) |
SET_WORD(mask->data_gi_ltf, FWCMD_H2C_CCTRL_DATA_GI_LTF) |
(mask->darf_tc_index ? FWCMD_H2C_CCTRL_DARF_TC_INDEX : 0) |
SET_WORD(mask->arfr_ctrl, FWCMD_H2C_CCTRL_ARFR_CTRL) |
(mask->acq_rpt_en ? FWCMD_H2C_CCTRL_ACQ_RPT_EN : 0) |
(mask->mgq_rpt_en ? FWCMD_H2C_CCTRL_MGQ_RPT_EN : 0) |
(mask->ulq_rpt_en ? FWCMD_H2C_CCTRL_ULQ_RPT_EN : 0) |
(mask->twtq_rpt_en ? FWCMD_H2C_CCTRL_TWTQ_RPT_EN : 0) |
(mask->disrtsfb ? FWCMD_H2C_CCTRL_DISRTSFB : 0) |
(mask->disdatafb ? FWCMD_H2C_CCTRL_DISDATAFB : 0) |
(mask->tryrate ? FWCMD_H2C_CCTRL_TRYRATE : 0) |
SET_WORD(mask->ampdu_density, FWCMD_H2C_CCTRL_AMPDU_DENSITY));
tbl->dword10 =
cpu_to_le32(SET_WORD(mask->data_rty_lowest_rate,
FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE) |
(mask->ampdu_time_sel ? FWCMD_H2C_CCTRL_AMPDU_TIME_SEL : 0) |
(mask->ampdu_len_sel ? FWCMD_H2C_CCTRL_AMPDU_LEN_SEL : 0) |
(mask->rts_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SEL :
0) |
SET_WORD(mask->rts_txcnt_lmt, FWCMD_H2C_CCTRL_RTS_TXCNT_LMT) |
SET_WORD(mask->rtsrate, FWCMD_H2C_CCTRL_RTSRATE) |
(mask->vcs_stbc ? FWCMD_H2C_CCTRL_VCS_STBC : 0) |
SET_WORD(mask->rts_rty_lowest_rate,
FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE));
tbl->dword11 =
cpu_to_le32(SET_WORD(mask->data_tx_cnt_lmt, FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT) |
(mask->data_txcnt_lmt_sel ? FWCMD_H2C_CCTRL_DATA_TXCNT_LMT_SEL :
0) |
(mask->max_agg_num_sel ? FWCMD_H2C_CCTRL_MAX_AGG_NUM_SEL : 0) |
(mask->rts_en ? FWCMD_H2C_CCTRL_RTS_EN : 0) |
(mask->cts2self_en ? FWCMD_H2C_CCTRL_CTS2SELF_EN : 0) |
SET_WORD(mask->cca_rts, FWCMD_H2C_CCTRL_CCA_RTS) |
(mask->hw_rts_en ? FWCMD_H2C_CCTRL_HW_RTS_EN : 0) |
SET_WORD(mask->rts_drop_data_mode,
FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE) |
SET_WORD(mask->ampdu_max_len, FWCMD_H2C_CCTRL_AMPDU_MAX_LEN) |
(mask->ul_mu_dis ? FWCMD_H2C_CCTRL_UL_MU_DIS : 0) |
SET_WORD(mask->ampdu_max_time, FWCMD_H2C_CCTRL_AMPDU_MAX_TIME));
tbl->dword12 =
cpu_to_le32(SET_WORD(mask->max_agg_num, FWCMD_H2C_CCTRL_MAX_AGG_NUM) |
SET_WORD(mask->ba_bmap, FWCMD_H2C_CCTRL_BA_BMAP) |
SET_WORD(mask->vo_lftime_sel, FWCMD_H2C_CCTRL_VO_LFTIME_SEL) |
SET_WORD(mask->vi_lftime_sel, FWCMD_H2C_CCTRL_VI_LFTIME_SEL) |
SET_WORD(mask->be_lftime_sel, FWCMD_H2C_CCTRL_BE_LFTIME_SEL) |
SET_WORD(mask->bk_lftime_sel, FWCMD_H2C_CCTRL_BK_LFTIME_SEL) |
SET_WORD(mask->sectype, FWCMD_H2C_CCTRL_SECTYPE));
tbl->dword13 =
cpu_to_le32(SET_WORD(mask->multi_port_id, FWCMD_H2C_CCTRL_MULTI_PORT_ID) |
(mask->bmc ? FWCMD_H2C_CCTRL_BMC : 0) |
SET_WORD(mask->mbssid, FWCMD_H2C_CCTRL_MBSSID) |
(mask->navusehdr ? FWCMD_H2C_CCTRL_NAVUSEHDR : 0) |
SET_WORD(mask->txpwr_mode, FWCMD_H2C_CCTRL_TXPWR_MODE) |
(mask->data_dcm ? FWCMD_H2C_CCTRL_DATA_DCM : 0) |
(mask->data_er ? FWCMD_H2C_CCTRL_DATA_ER : 0) |
(mask->data_ldpc ? FWCMD_H2C_CCTRL_DATA_LDPC : 0) |
(mask->data_stbc ? FWCMD_H2C_CCTRL_DATA_STBC : 0) |
(mask->a_ctrl_bqr ? FWCMD_H2C_CCTRL_A_CTRL_BQR : 0) |
(mask->a_ctrl_uph ? FWCMD_H2C_CCTRL_A_CTRL_UPH : 0) |
(mask->a_ctrl_bsr ? FWCMD_H2C_CCTRL_A_CTRL_BSR : 0) |
(mask->a_ctrl_cas ? FWCMD_H2C_CCTRL_A_CTRL_CAS : 0) |
(mask->data_bw_er ? FWCMD_H2C_CCTRL_DATA_BW_ER : 0) |
(mask->lsig_txop_en ? FWCMD_H2C_CCTRL_LSIG_TXOP_EN : 0) |
(mask->ctrl_cnt_vld ? FWCMD_H2C_CCTRL_CTRL_CNT_VLD : 0) |
SET_WORD(mask->ctrl_cnt, FWCMD_H2C_CCTRL_CTRL_CNT));
tbl->dword14 =
cpu_to_le32(SET_WORD(mask->resp_ref_rate, FWCMD_H2C_CCTRL_RESP_REF_RATE) |
(mask->all_ack_support ? FWCMD_H2C_CCTRL_ALL_ACK_SUPPORT : 0) |
(mask->bsr_queue_size_format ?
FWCMD_H2C_CCTRL_BSR_QUEUE_SIZE_FORMAT : 0) |
SET_WORD(mask->ntx_path_en, FWCMD_H2C_CCTRL_NTX_PATH_EN) |
SET_WORD(mask->path_map_a, FWCMD_H2C_CCTRL_PATH_MAP_A) |
SET_WORD(mask->path_map_b, FWCMD_H2C_CCTRL_PATH_MAP_B) |
SET_WORD(mask->path_map_c, FWCMD_H2C_CCTRL_PATH_MAP_C) |
SET_WORD(mask->path_map_d, FWCMD_H2C_CCTRL_PATH_MAP_D) |
(mask->antsel_a ? FWCMD_H2C_CCTRL_ANTSEL_A : 0) |
(mask->antsel_b ? FWCMD_H2C_CCTRL_ANTSEL_B : 0) |
(mask->antsel_c ? FWCMD_H2C_CCTRL_ANTSEL_C : 0) |
(mask->antsel_d ? FWCMD_H2C_CCTRL_ANTSEL_D : 0));
tbl->dword15 =
cpu_to_le32(SET_WORD(mask->addr_cam_index, FWCMD_H2C_CCTRL_ADDR_CAM_INDEX) |
SET_WORD(mask->paid, FWCMD_H2C_CCTRL_PAID) |
(mask->uldl ? FWCMD_H2C_CCTRL_ULDL : 0) |
SET_WORD(mask->doppler_ctrl, FWCMD_H2C_CCTRL_DOPPLER_CTRL) |
SET_WORD(mask->nominal_pkt_padding,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING) |
SET_WORD(mask->nominal_pkt_padding40,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40) |
SET_WORD(mask->nominal_pkt_padding80,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80) |
SET_WORD(mask->txpwr_tolerence,
FWCMD_H2C_CCTRL_TXPWR_TOLERENCE));
tbl->dword16 =
cpu_to_le32(SET_WORD(mask->nc, FWCMD_H2C_CCTRL_NC) |
SET_WORD(mask->nr, FWCMD_H2C_CCTRL_NR) |
SET_WORD(mask->ng, FWCMD_H2C_CCTRL_NG) |
SET_WORD(mask->cb, FWCMD_H2C_CCTRL_CB) |
SET_WORD(mask->cs, FWCMD_H2C_CCTRL_CS) |
(mask->csi_txbf_en ? FWCMD_H2C_CCTRL_CSI_TXBF_EN : 0) |
(mask->csi_stbc_en ? FWCMD_H2C_CCTRL_CSI_STBC_EN : 0) |
(mask->csi_ldpc_en ? FWCMD_H2C_CCTRL_CSI_LDPC_EN : 0) |
(mask->csi_para_en ? FWCMD_H2C_CCTRL_CSI_PARA_EN : 0) |
SET_WORD(mask->csi_fix_rate, FWCMD_H2C_CCTRL_CSI_FIX_RATE) |
SET_WORD(mask->csi_gi_ltf, FWCMD_H2C_CCTRL_CSI_GI_LTF) |
SET_WORD(mask->nominal_pkt_padding160,
FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160) |
SET_WORD(mask->csi_bw, FWCMD_H2C_CCTRL_CSI_BW));
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_CCTLINFO_UD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
} else {
#if MAC_AX_FEATURE_DBGPKG
if (operation)
cctl_info_debug_write(adapter, macid,
(struct fwcmd_cctlinfo_ud *)buf);
#else
return MACFWNONRDY;
#endif
}
h2cb_free(adapter, h2cb);
mac_upd_role_cctrl(adapter, info, mask, macid);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_set_fixmode_mib(struct mac_ax_adapter *adapter,
struct mac_ax_fixmode_para *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_fixmode_para_tblud *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_fixmode_para_tblud));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMSET(buf, 0, sizeof(struct fwcmd_fixmode_para_tblud));
tbl = (struct fwcmd_fixmode_para_tblud *)buf;
tbl->dword0 =
cpu_to_le32((info->tbl_hdr.rw ? FWCMD_H2C_TBLUD_R_W : 0) |
SET_WORD(info->tbl_hdr.idx, FWCMD_H2C_TBLUD_MACID_GROUP) |
SET_WORD(info->tbl_hdr.offset, FWCMD_H2C_TBLUD_OFFSET) |
SET_WORD(info->tbl_hdr.len, FWCMD_H2C_TBLUD_LENGTH) |
(info->tbl_hdr.type ? FWCMD_H2C_TBLUD_TYPE : 0) |
SET_WORD(CLASS_F2P_FIXMODE_PARA,
FWCMD_H2C_TBLUD_TABLE_CLASS));
tbl->dword1 =
cpu_to_le32((info->force_sumuru_en ?
FWCMD_H2C_FIXMODE_PARA_FORCE_SUMURU_EN : 0) |
(info->forcesu ?
FWCMD_H2C_FIXMODE_PARA_FORCESU : 0) |
(info->forcemu ?
FWCMD_H2C_FIXMODE_PARA_FORCEMU : 0) |
(info->forceru ?
FWCMD_H2C_FIXMODE_PARA_FORCERU : 0) |
(info->fix_fe_su_en ?
FWCMD_H2C_FIXMODE_PARA_FIX_FE_SU_EN : 0) |
(info->fix_fe_vhtmu_en ?
FWCMD_H2C_FIXMODE_PARA_FIX_FE_VHTMU_EN : 0) |
(info->fix_fe_hemu_en ?
FWCMD_H2C_FIXMODE_PARA_FIX_FE_HEMU_EN : 0) |
(info->fix_fe_heru_en ?
FWCMD_H2C_FIXMODE_PARA_FIX_FE_HERU_EN : 0) |
(info->fix_fe_ul_en ?
FWCMD_H2C_FIXMODE_PARA_FIX_FE_UL_EN : 0) |
(info->fix_frame_seq_su ?
FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_SU : 0) |
(info->fix_frame_seq_vhtmu ?
FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_VHTMU : 0) |
(info->fix_frame_seq_hemu ?
FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HEMU : 0) |
(info->fix_frame_seq_heru ?
FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HERU : 0) |
(info->fix_frame_seq_ul ?
FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_UL : 0) |
(info->is_dlruhwgrp ?
FWCMD_H2C_FIXMODE_PARA_IS_DLRUHWGRP : 0) |
(info->is_ulruhwgrp ?
FWCMD_H2C_FIXMODE_PARA_IS_ULRUHWGRP : 0) |
SET_WORD(info->prot_type_su,
FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_SU) |
SET_WORD(info->prot_type_vhtmu,
FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_VHTMU) |
SET_WORD(info->resp_type_vhtmu,
FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_VHTMU) |
SET_WORD(info->prot_type_hemu,
FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HEMU));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->resp_type_hemu,
FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HEMU) |
SET_WORD(info->prot_type_heru,
FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HERU) |
SET_WORD(info->resp_type_heru,
FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HERU) |
SET_WORD(info->ul_prot_type,
FWCMD_H2C_FIXMODE_PARA_UL_PROT_TYPE) |
SET_WORD(info->rugrpid,
FWCMD_H2C_FIXMODE_PARA_RUGRPID) |
SET_WORD(info->mugrpid,
FWCMD_H2C_FIXMODE_PARA_MUGRPID) |
SET_WORD(info->ulgrpid,
FWCMD_H2C_FIXMODE_PARA_ULGRPID));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_TBLUD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 rst_bacam(struct mac_ax_adapter *adapter, struct rst_bacam_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, cnt;
val32 = MAC_REG_R32(R_AX_RESPBA_CAM_CTRL);
switch (info->type) {
case BACAM_RST_ALL:
val32 = SET_CLR_WORD(val32, S_AX_BACAM_RST_ALL, B_AX_BACAM_RST);
break;
case BACAM_RST_ENT:
val32 = SET_CLR_WORD(val32, info->ent, B_AX_SRC_ENTRY_IDX);
MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32);
val32 = SET_CLR_WORD(val32, S_AX_BACAM_RST_ENT, B_AX_BACAM_RST);
break;
}
MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32);
cnt = BACAM_RST_DLY_CNT;
while (cnt) {
val32 = MAC_REG_R32(R_AX_RESPBA_CAM_CTRL);
if (GET_FIELD(val32, B_AX_BACAM_RST) == S_AX_BACAM_RST_DONE)
break;
PLTFM_DELAY_US(BACAM_RST_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]bacam rst timeout %X\n", val32);
return MACPOLLTO;
}
return MACSUCCESS;
}
u32 mac_bacam_info(struct mac_ax_adapter *adapter,
struct mac_ax_bacam_info *info)
{
u32 ret = MACSUCCESS;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_ba_cam *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]h2cb_alloc\n");
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ba_cam));
if (!buf) {
ret = MACNOBUF;
PLTFM_MSG_ERR("[ERR]h2cb_put %d\n", ret);
goto fail;
}
tbl = (struct fwcmd_ba_cam *)buf;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
tbl->dword0 =
cpu_to_le32((info->valid ? FWCMD_H2C_BA_CAM_VALID : 0) |
(info->init_req ? FWCMD_H2C_BA_CAM_INIT_REQ : 0) |
SET_WORD(info->entry_idx, FWCMD_H2C_BA_CAM_ENTRY_IDX) |
SET_WORD(info->tid, FWCMD_H2C_BA_CAM_TID) |
SET_WORD(info->macid, FWCMD_H2C_BA_CAM_MACID) |
SET_WORD(info->bmap_size, FWCMD_H2C_BA_CAM_BMAP_SIZE) |
SET_WORD(info->ssn, FWCMD_H2C_BA_CAM_SSN)
);
} else {
//8852C
if (info->entry_idx) {
PLTFM_MSG_ERR("[ERR]entry_idx is replaced by entry_idx_v1 in 52C\n");
return MACNOITEM;
}
tbl->dword0 =
cpu_to_le32((info->valid ? FWCMD_H2C_BA_CAM_VALID : 0) |
(info->init_req ? FWCMD_H2C_BA_CAM_INIT_REQ : 0) |
SET_WORD(info->tid, FWCMD_H2C_BA_CAM_TID) |
SET_WORD(info->macid, FWCMD_H2C_BA_CAM_MACID) |
SET_WORD(info->bmap_size, FWCMD_H2C_BA_CAM_BMAP_SIZE) |
SET_WORD(info->ssn, FWCMD_H2C_BA_CAM_SSN)
);
tbl->dword1 =
cpu_to_le32(SET_WORD(info->uid_value, FWCMD_H2C_BA_CAM_UID_VALUE) |
(info->std_entry_en ? FWCMD_H2C_BA_CAM_STD_ENTRY_EN : 0) |
(info->band_sel ? FWCMD_H2C_BA_CAM_BAND_SEL : 0) |
SET_WORD(info->entry_idx_v1, FWCMD_H2C_BA_CAM_ENTRY_IDX_V1)
);
}
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_BA_CAM,
FWCMD_H2C_FUNC_BA_CAM,
0,
1);
if (ret) {
PLTFM_MSG_ERR("[ERR]h2c_pkt_set_hdr %d\n", ret);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]h2c_pkt_build_txd %d\n", ret);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]PLTFM_TX %d\n", ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_ss_dl_grp_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ss_dl_grp_upd *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_dl_grp_upd *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_dl_grp_upd));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_dl_grp_upd *)buf;
tbl->dword0 =
cpu_to_le32((info->grp_valid ? FWCMD_H2C_DL_GRP_UPD_GRP_VALID : 0) |
SET_WORD(info->grp_id, FWCMD_H2C_DL_GRP_UPD_GRP_ID) |
(info->is_hwgrp ? FWCMD_H2C_DL_GRP_UPD_IS_HWGRP : 0) |
SET_WORD(info->macid_u0, FWCMD_H2C_DL_GRP_UPD_MACID_U0) |
SET_WORD(info->macid_u1, FWCMD_H2C_DL_GRP_UPD_MACID_U1) |
SET_WORD(info->macid_u2, FWCMD_H2C_DL_GRP_UPD_MACID_U2));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->macid_u3, FWCMD_H2C_DL_GRP_UPD_MACID_U3) |
SET_WORD(info->macid_u4, FWCMD_H2C_DL_GRP_UPD_MACID_U4) |
SET_WORD(info->macid_u5, FWCMD_H2C_DL_GRP_UPD_MACID_U5) |
SET_WORD(info->macid_u6, FWCMD_H2C_DL_GRP_UPD_MACID_U6));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->macid_u7, FWCMD_H2C_DL_GRP_UPD_MACID_U7) |
SET_WORD(info->ac_bitmap_u0,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U0) |
SET_WORD(info->ac_bitmap_u1,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U1) |
SET_WORD(info->ac_bitmap_u2,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U2) |
SET_WORD(info->ac_bitmap_u3,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U3) |
SET_WORD(info->ac_bitmap_u4,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U4) |
SET_WORD(info->ac_bitmap_u5,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U5));
tbl->dword3 =
cpu_to_le32(SET_WORD(info->ac_bitmap_u6,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U6) |
SET_WORD(info->ac_bitmap_u7,
FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U7) |
SET_WORD(info->next_protecttype,
FWCMD_H2C_DL_GRP_UPD_NEXT_PROTECTTYPE) |
SET_WORD(info->next_rsptype,
FWCMD_H2C_DL_GRP_UPD_NEXT_RSPTYPE));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MEDIA_RPT,
FWCMD_H2C_FUNC_DL_GRP_UPD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_ss_ul_grp_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ss_ul_grp_upd *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_ul_grp_upd *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ul_grp_upd));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_ul_grp_upd *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(info->macid_u0, FWCMD_H2C_UL_GRP_UPD_MACID_U0) |
SET_WORD(info->macid_u1, FWCMD_H2C_UL_GRP_UPD_MACID_U1) |
SET_WORD(info->grp_bitmap,
FWCMD_H2C_UL_GRP_UPD_GRP_BITMAP));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MEDIA_RPT,
FWCMD_H2C_FUNC_UL_GRP_UPD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_ss_ul_sta_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ss_ul_sta_upd *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_ss_ulsta_upd *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ss_ulsta_upd));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_ss_ulsta_upd *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(info->mode, FWCMD_H2C_SS_ULSTA_UPD_MODE));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->macid[0], FWCMD_H2C_SS_ULSTA_UPD_MACID_U0) |
SET_WORD(info->macid[1], FWCMD_H2C_SS_ULSTA_UPD_MACID_U1) |
SET_WORD(info->macid[2], FWCMD_H2C_SS_ULSTA_UPD_MACID_U2) |
SET_WORD(info->macid[3], FWCMD_H2C_SS_ULSTA_UPD_MACID_U3));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->bsr_len[0],
FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U0) |
SET_WORD(info->bsr_len[1],
FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U1));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_SS_ULSTA_UPD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_mu_sta_upd(struct mac_ax_adapter *adapter,
struct mac_ax_mu_sta_upd *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_mu_sta_upd *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_mu_sta_upd));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_mu_sta_upd *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_MU_STA_UPD_MACID) |
SET_WORD(info->mu_idx, FWCMD_H2C_MU_STA_UPD_MU_IDX) |
SET_WORD(info->prot_rsp_type[0].u.byte_type,
FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_0) |
SET_WORD(info->prot_rsp_type[1].u.byte_type,
FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_1));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->prot_rsp_type[2].u.byte_type,
FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_2) |
SET_WORD(info->prot_rsp_type[3].u.byte_type,
FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_3) |
SET_WORD(info->prot_rsp_type[4].u.byte_type,
FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_4) |
SET_WORD(info->mugrp_bitmap,
FWCMD_H2C_MU_STA_UPD_MUGRP_BITMAP) |
(info->dis_256q ?
FWCMD_H2C_MU_STA_UPD_DIS_256Q : 0) |
(info->dis_1024q ?
FWCMD_H2C_MU_STA_UPD_DIS_1024Q : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MEDIA_RPT,
FWCMD_H2C_FUNC_MU_STA_UPD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_wlaninfo_get(struct mac_ax_adapter *adapter,
struct mac_ax_wlaninfo_get *info)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_wlaninfo_get *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_wlaninfo_get));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct fwcmd_wlaninfo_get *)buf;
tbl->dword0 =
cpu_to_le32(SET_WORD(info->info_sel, FWCMD_H2C_WLANINFO_GET_INFO_SEL) |
SET_WORD(info->argv0, FWCMD_H2C_WLANINFO_GET_ARGV0) |
SET_WORD(info->argv1,
FWCMD_H2C_WLANINFO_GET_ARGV1) |
SET_WORD(info->argv2,
FWCMD_H2C_WLANINFO_GET_ARGV2));
tbl->dword1 =
cpu_to_le32(SET_WORD(info->argv3,
FWCMD_H2C_WLANINFO_GET_ARGV3) |
SET_WORD(info->argv4,
FWCMD_H2C_WLANINFO_GET_ARGV4) |
SET_WORD(info->argv5,
FWCMD_H2C_WLANINFO_GET_ARGV5) |
SET_WORD(info->argv6,
FWCMD_H2C_WLANINFO_GET_ARGV6));
tbl->dword2 =
cpu_to_le32(SET_WORD(info->argv7,
FWCMD_H2C_WLANINFO_GET_ARGV7));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_WLANINFO_GET,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_dumpwlanc(struct mac_ax_adapter *adapter, struct mac_ax_dumpwlanc *para)
{
struct mac_ax_wlaninfo_get info;
u32 ret = 0;
info.info_sel = DUMPWLANC;
info.argv0 = para->cmdid;
info.argv1 = 0;
info.argv2 = 0;
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
ret = mac_wlaninfo_get(adapter, &info);
return ret;
}
u32 mac_dumpwlans(struct mac_ax_adapter *adapter, struct mac_ax_dumpwlans *para)
{
struct mac_ax_wlaninfo_get info;
u32 ret = 0;
info.info_sel = DUMPWLANS;
info.argv0 = para->cmdid;
info.argv1 = para->macid_grp;
info.argv2 = 0;
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
ret = mac_wlaninfo_get(adapter, &info);
return ret;
}
u32 mac_dumpwland(struct mac_ax_adapter *adapter, struct mac_ax_dumpwland *para)
{
u32 ret = 0;
struct mac_ax_wlaninfo_get info;
info.argv0 = 0;
info.argv1 = 0;
info.argv2 = 0;
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
info.info_sel = DUMPWLAND;
info.argv0 = para->cmdid;
if (para->cmdid == DLDECISION_SU_FORCEMU_FAIL) {
info.argv1 = para->macid[0];
info.argv2 = para->macid[1];
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
} else if (para->cmdid == DLDECISION_SU_FORCERU_FAIL) {
info.argv1 = para->grp_type;
info.argv2 = para->grp_id;
info.argv3 = para->macid[0];
info.argv4 = para->macid[1];
info.argv5 = para->macid[2];
info.argv6 = para->macid[3];
info.argv7 = 0;
} else if (para->cmdid == DLDECISION_SU_MUTXTIME_PASS_MU_NOTSUPPORT) {
info.argv1 = para->macid[0];
info.argv2 = para->macid[1];
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
} else if (para->cmdid == DLDECISION_SU_MUTXTIME_FAIL_RU_NOTSUPPORT) {
info.argv1 = para->grp_type;
info.argv2 = para->grp_id;
info.argv3 = para->macid[0];
info.argv4 = para->macid[1];
info.argv5 = para->macid[2];
info.argv6 = para->macid[3];
info.argv7 = 0;
} else if (para->cmdid == DLDECISION_MU_TPCOMPARE_RST) {
info.argv1 = para->macid[0];
info.argv2 = para->macid[1];
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
} else if (para->cmdid == DLDECISION_RU_TPCOMPARE_RST) {
info.argv1 = para->grp_type;
info.argv2 = para->grp_id;
info.argv3 = para->macid[0];
info.argv4 = para->macid[1];
info.argv5 = para->macid[2];
info.argv6 = para->macid[3];
info.argv7 = 0;
} else if (para->cmdid == DLDECISION_SU_TPCOMPARE_RST) {
if (para->muru == 0) {
info.argv1 = para->macid[0];
info.argv2 = para->macid[1];
info.argv3 = 0;
info.argv4 = 0;
info.argv5 = 0;
info.argv6 = 0;
info.argv7 = 0;
} else {
info.argv1 = para->grp_type;
info.argv2 = para->grp_id;
info.argv3 = para->macid[0];
info.argv4 = para->macid[1];
info.argv5 = para->macid[2];
info.argv6 = para->macid[3];
info.argv7 = 0;
}
}
ret = mac_wlaninfo_get(adapter, &info);
return ret;
}
#if MAC_AX_FEATURE_DBGPKG
u32 cctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid,
struct fwcmd_cctlinfo_ud *tbl)
{
u32 val;
u32 *data = &tbl->dword1, *msk = &tbl->dword9;
u8 i;
for (i = 0; i < (CCTL_INFO_SIZE >> 2); i++) {
val = mac_sram_dbg_read(adapter, macid * CCTL_INFO_SIZE + i * 4,
CMAC_TBL_SEL);
val = (val & ~(*(msk + i))) | ((*(data + i)) & (*(msk + i)));
mac_sram_dbg_write(adapter, macid * CCTL_INFO_SIZE + i * 4, val,
CMAC_TBL_SEL);
}
return MACSUCCESS;
}
u32 dctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid,
struct fwcmd_dctlinfo_ud *tbl)
{
mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE, tbl->dword1,
DMAC_TBL_SEL);
mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE + 4, tbl->dword2,
DMAC_TBL_SEL);
mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE + 8, tbl->dword3,
DMAC_TBL_SEL);
mac_sram_dbg_write(adapter, macid * DCTL_INFO_SIZE + 12, tbl->dword4,
DMAC_TBL_SEL);
return MACSUCCESS;
}
#endif
u32 mac_fw_status_cmd(struct mac_ax_adapter *adapter,
struct mac_ax_fwstatus_payload *info)
{
u32 ret = 0;
u32 i;
u8 *buf;
u32 *src, *dest;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_fwstatus_payload *tbl;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_fwstatus_payload));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
tbl = (struct mac_ax_fwstatus_payload *)buf;
src = (u32 *)info;
dest = (u32 *)tbl;
for (i = 0; i < (sizeof(struct mac_ax_fwstatus_payload) / 4); i++)
*(dest++) = cpu_to_le32(*(src++));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_TEST,
FWCMD_H2C_CL_FW_STATUS_TEST,
0,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_fwc2h_ofdma_sts_parse(struct mac_ax_adapter *adapter,
struct mac_ax_fwc2h_sts *fw_c2h_sts,
u32 *content)
{
u32 val;
u8 i;
if (!fw_c2h_sts || !content) {
PLTFM_MSG_ERR("[ERR]fwc2h_sts is null\n");
return MACNPTR;
}
val = le32_to_cpu(*(content++));
fw_c2h_sts->tfsts.user_num =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_USER_NUM);
fw_c2h_sts->tfsts.ru_su_per =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_RU_SU_PER);
for (i = 0; i < fw_c2h_sts->tfsts.user_num; i++) {
val = le32_to_cpu(*(content++));
fw_c2h_sts->tfsts.tf_user_sts[i].macid =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_MACID);
fw_c2h_sts->tfsts.tf_user_sts[i].tb_rate =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_TB_RATE);
fw_c2h_sts->tfsts.tf_user_sts[i].tb_fail_per =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_TB_FAIL_PER);
fw_c2h_sts->tfsts.tf_user_sts[i].avg_tb_rssi =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_RSSI);
val = le32_to_cpu(*(content++));
fw_c2h_sts->tfsts.tf_user_sts[i].cca_miss_per =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_CCA_MISS_PER);
fw_c2h_sts->tfsts.tf_user_sts[i].avg_uph =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_AVG_UPH);
fw_c2h_sts->tfsts.tf_user_sts[i].minflag_per =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_MINFLAG_PER);
fw_c2h_sts->tfsts.tf_user_sts[i].avg_tb_evm =
GET_FIELD(val, FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_EVM);
}
return MACSUCCESS;
}
u32 mac_fw_ofdma_sts_en(struct mac_ax_adapter *adapter,
struct mac_ax_fwsts_para *fwsts_para)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u32 *para;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(u32));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
para = (u32 *)buf;
(*para) = cpu_to_le32((fwsts_para->en ? FWCMD_H2C_FW_STS_PARA_EN : 0) |
SET_WORD(fwsts_para->intvl_ms,
FWCMD_H2C_FW_STS_PARA_INTVL_MS));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_FW_STS_PARA,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/tblupd.c
|
C
|
agpl-3.0
| 77,811
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _TABLEUPD_H2C_H_
#define _TABLEUPD_H2C_H_
#include "../type.h"
#include "fwcmd.h"
#include "trx_desc.h"
#include "addr_cam.h"
/*--------------------Define MACRO--------------------------------------*/
#define DLRU_CLASS_GRP_TBL 0
#define ULRU_CLASS_GRP_TBL 1
#define CLASS_RUSTA_INFO 2
#define DLRU_CLASS_FIXED_TBL 3
#define ULRU_CLASS_FIXED_TBL 4
#define CLASS_BA_INFOTBL 5
#define CLASS_MUDECISION_PARA 6
#define CLASS_UL_FIXINFO 7
#define CLASS_F2P_FIXMODE_PARA 8
#define BACAM_RST_DLY_CNT 1000
#define BACAM_RST_DLY_US 1
/*--------------------Define Enum---------------------------------------*/
/**
* @enum H2C_WLANINFO_SEL
*
* @brief H2C_WLANINFO_SEL
*
* @var H2C_WLANINFO_SEL::DUMPWLANC
* Please Place Description here.
* @var H2C_WLANINFO_SEL::DUMPWLANS
* Please Place Description here.
* @var H2C_WLANINFO_SEL::DUMPWLAND
* Please Place Description here.
*/
enum H2C_WLANINFO_SEL {
DUMPWLANC = BIT0,
DUMPWLANS = BIT1,
DUMPWLAND = BIT2
};
/**
* @enum DLDECISION_RESULT_TYPE
*
* @brief DLDECISION_RESULT_TYPE
*
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCESU
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_MU_FORCEMU
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCEMU_FAIL
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCERU_FAIL
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_FORCERU_RUARST_RU2SU
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_RU_FORCERU_RUSRST_FIXTBL
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_RU_FORCERU
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_WDINFO_USERATE
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_PRINULLWD
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_MU_BYPASS_MUTPCOMPARE
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_MUTXTIME_PASS_MU_NOTSUPPORT
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_MUTXTIME_FAIL_RU_NOTSUPPORT
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_RUARST_RU2SU
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_RU_RUARST_FIXTBL
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_MU_TPCOMPARE_RST
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_RU_TPCOMPARE_RST
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_SU_TPCOMPARE_RST
* Please Place Description here.
* @var DLDECISION_RESULT_TYPE::DLDECISION_MAX
* Please Place Description here.
*/
enum DLDECISION_RESULT_TYPE {
DLDECISION_SU_FORCESU = 0,
DLDECISION_MU_FORCEMU = 1,
DLDECISION_SU_FORCEMU_FAIL = 2,
DLDECISION_SU_FORCERU_FAIL = 3,
DLDECISION_SU_FORCERU_RUARST_RU2SU = 4,
DLDECISION_RU_FORCERU_RUSRST_FIXTBL = 5,
DLDECISION_RU_FORCERU = 6,
DLDECISION_SU_WDINFO_USERATE = 7,
DLDECISION_SU_PRINULLWD = 8,
DLDECISION_MU_BYPASS_MUTPCOMPARE = 9,
DLDECISION_SU_MUTXTIME_PASS_MU_NOTSUPPORT = 10,
DLDECISION_SU_MUTXTIME_FAIL_RU_NOTSUPPORT = 11,
DLDECISION_SU_RUARST_RU2SU = 12,
DLDECISION_RU_RUARST_FIXTBL = 13,
DLDECISION_MU_TPCOMPARE_RST = 14,
DLDECISION_RU_TPCOMPARE_RST = 15,
DLDECISION_SU_TPCOMPARE_RST = 16,
DLDECISION_MAX = 17
};
enum S_AX_BACAM_RST {
S_AX_BACAM_RST_DONE = 0,
S_AX_BACAM_RST_ENT,
S_AX_BACAM_RST_ALL,
S_AX_BACAM_RST_RSVD
};
enum BACAM_RST_TYPE {
BACAM_RST_ALL = 0,
BACAM_RST_ENT,
};
/*--------------------Define Struct-------------------------------------*/
struct rst_bacam_info {
enum BACAM_RST_TYPE type;
u8 ent;
};
/**
* @addtogroup Association
* @{
* @addtogroup BA_Info
* @{
*/
/**
* @brief mac_upd_ba_infotbl
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_ba_infotbl(struct mac_ax_adapter *adapter,
struct mac_ax_ba_infotbl *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup MU
* @{
*/
/**
* @brief mac_upd_mudecision_para
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_mudecision_para(struct mac_ax_adapter *adapter,
struct mac_ax_mudecision_para *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup UL
* @{
*/
/**
* @brief mac_upd_ul_fixinfo
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_ul_fixinfo(struct mac_ax_adapter *adapter,
struct mac_ax_ul_fixinfo *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup F2P_TestCmd
* @{
*/
/**
* @brief mac_f2p_test_cmd
*
* @param *adapter
* @param *info
* @param *f2pwd
* @param *ptxcmd
* @param *psigb_addr
* @return Please Place Description here.
* @retval u32
*/
u32 mac_f2p_test_cmd(struct mac_ax_adapter *adapter,
struct mac_ax_f2p_test_para *info,
struct mac_ax_f2p_wd *f2pwd,
struct mac_ax_f2p_tx_cmd *ptxcmd,
u8 *psigb_addr);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup DMAC_Table
* @{
*/
/**
* @brief mac_upd_dctl_info
*
* @param *adapter
* @param *info
* @param *mask
* @param macid
* @param operation
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_dctl_info(struct mac_ax_adapter *adapter,
struct mac_ax_dctl_info *info,
struct mac_ax_dctl_info *mask, u8 macid, u8 operation);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_upd_shcut_mhdr
*
* @param *adapter
* @param *info
* @param macid
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_shcut_mhdr(struct mac_ax_adapter *adapter,
struct mac_ax_shcut_mhdr *info, u8 macid);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup CMAC_Table
* @{
*/
/**
* @brief mac_upd_cctl_info
*
* @param *adapter
* @param *info
* @param *mask
* @param macid
* @param operation
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_cctl_info(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_info *info,
struct mac_ax_cctl_info *mask, u8 macid, u8 operation);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup FW_CommonInfo
* @{
*/
/**
* @brief mac_set_fixmode_mib
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_fixmode_mib(struct mac_ax_adapter *adapter,
struct mac_ax_fixmode_para *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup F2P_TestCmd
* @{
*/
/**
* @brief mac_snd_test_cmd
*
* @param *adapter
* @param *cmd_buf
* @return Please Place Description here.
* @retval u32
*/
u32 mac_snd_test_cmd(struct mac_ax_adapter *adapter,
u8 *cmd_buf);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup BA_Info
* @{
*/
/**
* @brief rst_bacam
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 rst_bacam(struct mac_ax_adapter *adapter, struct rst_bacam_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Association
* @{
* @addtogroup BA_Info
* @{
*/
/**
* @brief mac_bacam_info
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_bacam_info(struct mac_ax_adapter *adapter,
struct mac_ax_bacam_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup SU
* @{
*/
/**
* @brief mac_ss_dl_grp_upd
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ss_dl_grp_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ss_dl_grp_upd *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup UL
* @{
*/
/**
* @brief mac_ss_ul_grp_upd
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ss_ul_grp_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ss_ul_grp_upd *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup UL
* @{
*/
/**
* @brief mac_ss_ul_sta_upd
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ss_ul_sta_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ss_ul_sta_upd *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup MU
* @{
*/
/**
* @brief mac_mu_sta_upd
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mu_sta_upd(struct mac_ax_adapter *adapter,
struct mac_ax_mu_sta_upd *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup FW_CommonInfo
* @{
*/
/**
* @brief mac_wlaninfo_get
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_wlaninfo_get(struct mac_ax_adapter *adapter,
struct mac_ax_wlaninfo_get *info);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup FW_CommonInfo
* @{
*/
/**
* @brief mac_dumpwlanc
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dumpwlanc(struct mac_ax_adapter *adapter,
struct mac_ax_dumpwlanc *para);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup FW_CommonInfo
* @{
*/
/**
* @brief mac_dumpwlans
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dumpwlans(struct mac_ax_adapter *adapter,
struct mac_ax_dumpwlans *para);
/**
* @}
* @}
*/
/**
* @addtogroup FrameExchange
* @{
* @addtogroup FW_CommonInfo
* @{
*/
/**
* @brief mac_dumpwland
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dumpwland(struct mac_ax_adapter *adapter,
struct mac_ax_dumpwland *para);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup CMAC_Table
* @{
*/
/**
* @brief cctl_info_debug_write
*
* @param *adapter
* @param macid
* @param *tbl
* @return Please Place Description here.
* @retval u32
*/
#if MAC_AX_FEATURE_DBGPKG
u32 cctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid,
struct fwcmd_cctlinfo_ud *tbl);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup DMAC_Table
* @{
*/
/**
* @brief dctl_info_debug_write
*
* @param *adapter
* @param macid
* @param *tbl
* @return Please Place Description here.
* @retval u32
*/
u32 dctl_info_debug_write(struct mac_ax_adapter *adapter, u8 macid,
struct fwcmd_dctlinfo_ud *tbl);
/**
* @}
* @}
*/
#endif
u32 mac_fw_status_cmd(struct mac_ax_adapter *adapter,
struct mac_ax_fwstatus_payload *info);
u32 mac_fwc2h_ofdma_sts_parse(struct mac_ax_adapter *adapter,
struct mac_ax_fwc2h_sts *fw_c2h_sts,
u32 *content);
u32 mac_fw_ofdma_sts_en(struct mac_ax_adapter *adapter,
struct mac_ax_fwsts_para *fwsts_para);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/tblupd.h
|
C
|
agpl-3.0
| 11,912
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "tcpip_checksum_offload.h"
#if MAC_AX_FW_REG_OFLD
u32 mac_tcpip_chksum_ofd(struct mac_ax_adapter *adapter,
u8 en_tx_chksum_ofd, u8 en_rx_chksum_ofd)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_en_tcpipchksum *content;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_tcpipchksum));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
content = (struct mac_ax_en_tcpipchksum *)buf;
content->en_tx_chksum_ofd = en_tx_chksum_ofd;
content->en_rx_chksum_ofd = en_rx_chksum_ofd;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_TCPIP_CHKSUM_OFFLOAD_REG,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#else
u32 mac_tcpip_chksum_ofd(struct mac_ax_adapter *adapter,
u8 en_tx_chksum_ofd, u8 en_rx_chksum_ofd)
{
u32 val;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (en_tx_chksum_ofd) {
val = MAC_REG_R32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION);
val |= B_AX_HDT_TCPIP_CHKSUM_EN;
MAC_REG_W32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION, val);
} else {
val = MAC_REG_R32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION);
val &= (~B_AX_HDT_TCPIP_CHKSUM_EN);
MAC_REG_W32(R_AX_TX_TCPIP_CHECKSUM_FUNCTION, val);
}
if (en_rx_chksum_ofd) {
val = MAC_REG_R32(R_AX_RX_TCPIP_CHECKSUM_FUNCTION);
val |= B_AX_HDR_TCPIP_CHKSUM_EN;
MAC_REG_W32((R_AX_RX_TCPIP_CHECKSUM_FUNCTION), val);
} else {
val = MAC_REG_R32((R_AX_RX_TCPIP_CHECKSUM_FUNCTION));
val &= (~B_AX_HDR_TCPIP_CHKSUM_EN);
MAC_REG_W32((R_AX_RX_TCPIP_CHECKSUM_FUNCTION), val);
}
return MACSUCCESS;
}
#endif
u32 mac_chk_rx_tcpip_chksum_ofd(struct mac_ax_adapter *adapter,
u8 chksum_status)
{
u8 chk_val = (chksum_status & 0xF0);
if (!(chk_val & MAC_AX_CHKOFD_TCP_CHKSUM_VLD))
return MAC_AX_CHKSUM_OFD_HW_NO_SUPPORT;
if (chk_val & MAC_AX_CHKOFD_TCP_CHKSUM_ERR)
return MAC_AX_CHKSUM_OFD_CHKSUM_ERR;
if (!(chk_val & MAC_AX_CHKOFD_RX_IS_TCP_UDP) &&
!(chk_val & MAC_AX_CHKOFD_RX_IPV))
return MAC_AX_CHKSUM_OFD_IPV4_TCP_OK;
if (!(chk_val & MAC_AX_CHKOFD_RX_IS_TCP_UDP) &&
(chk_val & MAC_AX_CHKOFD_RX_IPV))
return MAC_AX_CHKSUM_OFD_IPV6_TCP_OK;
if ((chk_val & MAC_AX_CHKOFD_RX_IS_TCP_UDP) &&
!(chk_val & MAC_AX_CHKOFD_RX_IPV))
return MAC_AX_CHKSUM_OFD_IPV4_UDP_OK;
return MAC_AX_CHKSUM_OFD_IPV6_UDP_OK;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.c
|
C
|
agpl-3.0
| 3,345
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_TCPIP_CHECKSUM_OFFLOAD_H_
#define _MAC_AX_TCPIP_CHECKSUM_OFFLOAD_H_
#include "../type.h"
#include "../mac_ax.h"
/**
* @struct mac_ax_en_tcpipchksum
* @brief mac_ax_en_tcpipchksum
*
* @var mac_ax_en_tcpipchksum::en_tx_chksum_ofd
* Please Place Description here.
* @var mac_ax_en_tcpipchksum::en_rx_chksum_ofd
* Please Place Description here.
* @var mac_ax_en_tcpipchksum::rsvd0
* Please Place Description here.
*/
struct mac_ax_en_tcpipchksum {
/* dword0 */
u32 en_tx_chksum_ofd: 1;
u32 en_rx_chksum_ofd: 1;
u32 rsvd0: 30;
};
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_tcpip_chksum_ofd
*
* @param *adapter
* @param en_tx_chksum_ofd
* @param en_rx_chksum_ofd
* @return Please Place Description here.
* @retval u32
*/
u32 mac_tcpip_chksum_ofd(struct mac_ax_adapter *adapter,
u8 en_tx_chksum_ofd,
u8 en_rx_chksum_ofd);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_chk_rx_tcpip_chksum_ofd
*
* @param *adapter
* @param chksum_status
* @return Please Place Description here.
* @retval u32
*/
u32 mac_chk_rx_tcpip_chksum_ofd(struct mac_ax_adapter *adapter,
u8 chksum_status);
/**
* @}
* @}
*/
#define MAC_AX_CHKSUM_OFD_TX 0x1
#define MAC_AX_CHKSUM_OFD_RX 0x2
#define MAC_AX_CHKOFD_TCP_CHKSUM_ERR BIT(4)
#define MAC_AX_CHKOFD_RX_IS_TCP_UDP BIT(6)
#define MAC_AX_CHKOFD_RX_IPV BIT(5)
#define MAC_AX_CHKOFD_TCP_CHKSUM_VLD BIT(7)
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/tcpip_checksum_offload.h
|
C
|
agpl-3.0
| 2,191
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "trx_desc.h"
#define RXD_RPKT_TYPE_INVALID 0xFF
#define TXD_AC_TYPE_MSK 0x3
#define TXD_TID_IND_SH 2
#define TID_MAX_NUM 8
#define TID_0_QSEL 0
#define TID_1_QSEL 1
#define TID_2_QSEL 1
#define TID_3_QSEL 0
#define TID_4_QSEL 2
#define TID_5_QSEL 2
#define TID_6_QSEL 3
#define TID_7_QSEL 3
#define TID_0_IND 0
#define TID_1_IND 0
#define TID_2_IND 1
#define TID_3_IND 1
#define TID_4_IND 0
#define TID_5_IND 1
#define TID_6_IND 0
#define TID_7_IND 1
enum wd_info_pkt_type {
WD_INFO_PKT_NORMAL,
/* keep last */
WD_INFO_PKT_LAST,
WD_INFO_PKT_MAX = WD_INFO_PKT_LAST,
};
static u8 qsel_l[TID_MAX_NUM] = {
TID_0_QSEL, TID_1_QSEL, TID_2_QSEL, TID_3_QSEL,
TID_4_QSEL, TID_5_QSEL, TID_6_QSEL, TID_7_QSEL
};
static u8 tid_ind[TID_MAX_NUM] = {
TID_0_IND, TID_1_IND, TID_2_IND, TID_3_IND,
TID_4_IND, TID_5_IND, TID_6_IND, TID_7_IND
};
u32 mac_txdesc_len(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info)
{
u32 len;
enum rtw_packet_type pkt_type = info->type;
len = WD_BODY_LEN;
if (pkt_type != RTW_PHL_PKT_TYPE_H2C &&
pkt_type != RTW_PHL_PKT_TYPE_FWDL &&
info->wdinfo_en != 0)
len += WD_INFO_LEN;
return len;
}
static u32 txdes_proc_h2c_fwdl(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len)
{
struct wd_body_t *wdb;
if (len != mac_txdesc_len(adapter, info)) {
PLTFM_MSG_ERR("[ERR] illegal len %d\n", len);
return MACBUFSZ;
}
if (info->pktlen > AX_TXD_TXPKTSIZE_MSK || !info->pktlen) {
PLTFM_MSG_ERR("[ERR] illegal txpktsize %d\n", info->pktlen);
return MACFUNCINPUT;
}
wdb = (struct wd_body_t *)buf;
wdb->dword0 = cpu_to_le32(SET_WORD(MAC_AX_DMA_H2C, AX_TXD_CH_DMA) |
(info->type == RTW_PHL_PKT_TYPE_FWDL ? AX_TXD_FWDL_EN : 0));
wdb->dword1 = 0;
wdb->dword2 = cpu_to_le32(SET_WORD(info->pktlen, AX_TXD_TXPKTSIZE));
wdb->dword3 = 0;
wdb->dword4 = 0;
wdb->dword5 = 0;
return MACSUCCESS;
}
#if MAC_AX_FEATURE_HV
static u32 txdes_proc_hv(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info,
struct wd_body_t *wdb,
struct wd_info_t *wdi)
{
struct hv_txpkt_info *hv_info = (struct hv_txpkt_info *)info->mac_priv;
wdb->dword0 |= cpu_to_le32((hv_info->chk_en ? AX_TXD_CHK_EN : 0));
wdi->dword3 |= cpu_to_le32((hv_info->null_1 ? AX_TXD_NULL_1 : 0) |
(hv_info->null_0 ? AX_TXD_NULL_0 : 0) |
(hv_info->tri_frame ? AX_TXD_TRI_FRAME : 0) |
(hv_info->ht_data_snd ? AX_TXD_HT_DATA_SND : 0));
wdi->dword5 |= cpu_to_le32(SET_WORD(hv_info->ndpa_dur, AX_TXD_NDPA_DURATION));
return MACSUCCESS;
}
#endif
static u32 txdes_proc_data(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len)
{
struct wd_body_t *wdb;
struct wd_info_t *wdi;
u8 wd_info_tmpl[WD_INFO_PKT_MAX][24] = {{0}};
u32 ret;
u8 ch, qsel;
if (len != mac_txdesc_len(adapter, info)) {
PLTFM_MSG_ERR("[ERR] illegal len %d\n", len);
return MACBUFSZ;
}
if (info->dma_ch > MAC_AX_DATA_HIQ) {
PLTFM_MSG_ERR("[ERR] txd ch %d illegal\n", info->dma_ch);
return MACTXCHDMA;
}
if (info->pktlen > AX_TXD_TXPKTSIZE_MSK || !info->pktlen) {
PLTFM_MSG_ERR("[ERR] illegal txpktsize %d\n", info->pktlen);
return MACFUNCINPUT;
}
wdb = (struct wd_body_t *)buf;
if (adapter->hw_info->intf == MAC_AX_INTF_SDIO) {
wdb->dword0 =
cpu_to_le32(AX_TXD_STF_MODE);
} else if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
wdb->dword0 =
cpu_to_le32(AX_TXD_STF_MODE |
(info->usb_pkt_ofst ?
AX_TXD_PKT_OFFSET : 0));
} else if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
wdb->dword0 =
cpu_to_le32((info->wd_page_size ? AX_TXD_WD_PAGE : 0) |
(adapter->dle_info.qta_mode ==
MAC_AX_QTA_SCC_STF ||
adapter->dle_info.qta_mode ==
MAC_AX_QTA_DBCC_STF ?
AX_TXD_STF_MODE : 0));
} else {
PLTFM_MSG_ERR("[ERR] unknown intf %d\n",
adapter->hw_info->intf);
return MACINTF;
}
if (info->dma_ch == MAC_AX_DATA_HIQ &&
adapter->hw_info->intf == MAC_AX_INTF_USB)
ch = info->band ? MAC_AX_DMA_B1MG : MAC_AX_DMA_B0MG;
else if (info->dma_ch == MAC_AX_DATA_HIQ)
ch = info->band ? MAC_AX_DMA_B1HI : MAC_AX_DMA_B0HI;
else
ch = info->dma_ch;
wdb->dword0 |=
cpu_to_le32(SET_WORD(info->hw_seq_mode,
AX_TXD_EN_HWSEQ_MODE) |
SET_WORD(info->hw_ssn_sel,
AX_TXD_HW_SSN_SEL) |
SET_WORD(info->hdr_len,
AX_TXD_HDR_LLC_LEN) |
SET_WORD(ch, AX_TXD_CH_DMA) |
(info->hw_amsdu ? AX_TXD_HWAMSDU : 0) |
(info->smh_en ? AX_TXD_SMH_EN : 0) |
(info->hw_sec_iv ? AX_TXD_HW_AES_IV : 0) |
(info->wdinfo_en ? AX_TXD_WDINFO_EN : 0) |
SET_WORD(info->wp_offset,
AX_TXD_WP_OFFSET));
wdb->dword1 =
cpu_to_le32(SET_WORD(info->shcut_camid, AX_TXD_SHCUT_CAMID));
/* Get bb and qsel from qsel by according MAC ID */
if (info->dma_ch == MAC_AX_DATA_HIQ)
qsel = info->band ? MAC_AX_HI1_SEL : MAC_AX_HI0_SEL;
else
qsel = (info->band << 3) | (info->wmm << 2) | qsel_l[info->tid];
wdb->dword2 =
cpu_to_le32(SET_WORD(info->pktlen, AX_TXD_TXPKTSIZE) |
SET_WORD(qsel, AX_TXD_QSEL) |
(tid_ind[info->tid] ? AX_TXD_TID_IND : 0) |
SET_WORD(info->macid, AX_TXD_MACID));
wdb->dword3 = cpu_to_le32(SET_WORD(info->sw_seq,
AX_TXD_WIFI_SEQ) |
(info->ampdu_en ? AX_TXD_AGG_EN : 0) |
((info->bk || info->ack_ch_info) ?
AX_TXD_BK : 0));
wdb->dword4 = 0;
wdb->dword5 = 0;
wdi = (struct wd_info_t *)wd_info_tmpl[WD_INFO_PKT_NORMAL];
wdi->dword0 =
cpu_to_le32((info->userate_sel ? AX_TXD_USERATE_SEL : 0) |
SET_WORD(info->f_rate, AX_TXD_DATARATE) |
SET_WORD(info->f_bw, AX_TXD_DATA_BW) |
(info->data_bw_er ? AX_TXD_DATA_BW_ER : 0) |
SET_WORD(info->f_gi_ltf, AX_TXD_GI_LTF) |
(info->f_er ? AX_TXD_DATA_ER : 0) |
(info->f_dcm ? AX_TXD_DATA_DCM : 0) |
(info->f_stbc ? AX_TXD_DATA_STBC : 0) |
(info->f_ldpc ? AX_TXD_DATA_LDPC : 0) |
(info->dis_data_rate_fb ? AX_TXD_DISDATAFB : 0) |
(info->dis_rts_rate_fb ? AX_TXD_DISRTSFB : 0) |
SET_WORD(info->hal_port,
AX_TXD_MULTIPORT_ID) |
SET_WORD(info->mbssid, AX_TXD_MBSSID) |
(info->ack_ch_info ? AX_TXD_ACK_CH_INFO : 0));
wdi->dword1 =
cpu_to_le32(SET_WORD(info->max_agg_num, AX_TXD_MAX_AGG_NUM) |
SET_WORD(info->data_tx_cnt_lmt, AX_TXD_DATA_TXCNT_LMT) |
(info->data_tx_cnt_lmt_en ?
AX_TXD_DATA_TXCNT_LMT_SEL : 0) |
(info->bc || info->mc ? AX_TXD_BMC : 0) |
(info->nav_use_hdr ? AX_TXD_NAVUSEHDR : 0) |
(info->bc || info->mc ? AX_TXD_BMC : 0) |
(info->a_ctrl_uph ? AX_TXD_A_CTRL_UPH : 0) |
(info->a_ctrl_bsr ? AX_TXD_A_CTRL_BSR : 0) |
(info->a_ctrl_cas ? AX_TXD_A_CTRL_CAS : 0) |
SET_WORD(info->data_rty_lowest_rate,
AX_TXD_DATA_RTY_LOWEST_RATE));
wdi->dword2 =
cpu_to_le32(SET_WORD(info->life_time_sel, AX_TXD_LIFETIME_SEL) |
SET_WORD(info->sec_type, AX_TXD_SECTYPE) |
(info->sec_hw_enc ? AX_TXD_SEC_HW_ENC : 0) |
SET_WORD(info->sec_cam_idx, AX_TXD_SEC_CAM_IDX) |
SET_WORD(info->ampdu_density,
AX_TXD_AMPDU_DENSITY));
wdi->dword3 =
cpu_to_le32((info->sifs_tx ? AX_TXD_SIFS_TX : 0) |
SET_WORD(info->ndpa, AX_TXD_NDPA) |
SET_WORD(info->snd_pkt_sel, AX_TXD_SND_PKT_SEL) |
(info->rtt_en ? AX_TXD_RTT_EN : 0) |
(info->spe_rpt ? AX_TXD_SPE_RPT : 0));
wdi->dword4 =
cpu_to_le32((info->rts_en ? AX_TXD_RTS_EN : 0) |
(info->cts2self ? AX_TXD_CTS2SELF : 0) |
SET_WORD(info->rts_cca_mode, AX_TXD_CCA_RTS) |
(info->hw_rts_en ? AX_TXD_HW_RTS_EN : 0) |
SET_WORD(info->sw_define, AX_TXD_SW_DEFINE));
wdi->dword5 = 0;
#if MAC_AX_FEATURE_HV
txdes_proc_hv(adapter, info, wdb, wdi);
#endif
if (info->wdinfo_en)
PLTFM_MEMCPY(buf + WD_BODY_LEN, (u8 *)wdi, WD_INFO_LEN);
if (adapter->hw_info->wd_checksum_en) {
ret = mac_wd_checksum(adapter, info, buf);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] mac_wd_checksum %d\n", ret);
return ret;
}
}
return MACSUCCESS;
}
static u32 txdes_proc_mgnt(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len)
{
struct wd_body_t *wdb;
struct wd_info_t *wdi;
u8 wd_info_tmpl[WD_INFO_PKT_MAX][24] = {{0}};
u32 ret;
if (len != mac_txdesc_len(adapter, info)) {
PLTFM_MSG_ERR("[ERR] illegal len %d\n", len);
return MACBUFSZ;
}
if (info->pktlen > AX_TXD_TXPKTSIZE_MSK || !info->pktlen) {
PLTFM_MSG_ERR("[ERR] illegal txpktsize %d\n", info->pktlen);
return MACFUNCINPUT;
}
wdb = (struct wd_body_t *)buf;
if (adapter->hw_info->intf == MAC_AX_INTF_SDIO) {
wdb->dword0 =
cpu_to_le32(AX_TXD_STF_MODE);
} else if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
wdb->dword0 =
cpu_to_le32(AX_TXD_STF_MODE |
(info->usb_pkt_ofst ?
AX_TXD_PKT_OFFSET : 0));
} else if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
wdb->dword0 =
cpu_to_le32((info->wd_page_size ? AX_TXD_WD_PAGE : 0) |
(adapter->dle_info.qta_mode ==
MAC_AX_QTA_SCC_STF ||
adapter->dle_info.qta_mode ==
MAC_AX_QTA_DBCC_STF ?
AX_TXD_STF_MODE : 0));
} else {
PLTFM_MSG_ERR("[ERR] unknown intf %d\n",
adapter->hw_info->intf);
return MACINTF;
}
wdb->dword0 |=
cpu_to_le32(SET_WORD(info->hw_seq_mode,
AX_TXD_EN_HWSEQ_MODE) |
SET_WORD(info->hw_ssn_sel,
AX_TXD_HW_SSN_SEL) |
SET_WORD(info->hdr_len,
AX_TXD_HDR_LLC_LEN) |
(info->wdinfo_en ? AX_TXD_WDINFO_EN : 0));
wdb->dword0 |=
cpu_to_le32(SET_WORD((info->band ?
MAC_AX_DMA_B1MG :
MAC_AX_DMA_B0MG),
AX_TXD_CH_DMA));
wdb->dword1 = 0;
/* Get bb and qsel from qsel by according MAC ID */
wdb->dword2 =
cpu_to_le32(SET_WORD(info->pktlen, AX_TXD_TXPKTSIZE) |
SET_WORD((info->band ?
MAC_AX_MG1_SEL : MAC_AX_MG0_SEL),
AX_TXD_QSEL) |
SET_WORD(info->macid, AX_TXD_MACID));
wdb->dword3 = cpu_to_le32(SET_WORD(info->sw_seq,
AX_TXD_WIFI_SEQ) |
(info->bk ? AX_TXD_BK : 0));
wdb->dword4 = 0;
wdb->dword5 = 0;
wdi = (struct wd_info_t *)wd_info_tmpl[WD_INFO_PKT_NORMAL];
wdi->dword0 =
cpu_to_le32((info->userate_sel ? AX_TXD_USERATE_SEL : 0) |
SET_WORD(info->f_rate, AX_TXD_DATARATE) |
SET_WORD(info->f_bw, AX_TXD_DATA_BW) |
(info->data_bw_er ? AX_TXD_DATA_BW_ER : 0) |
SET_WORD(info->f_gi_ltf, AX_TXD_GI_LTF) |
(info->f_er ? AX_TXD_DATA_ER : 0) |
(info->f_dcm ? AX_TXD_DATA_DCM : 0) |
(info->f_stbc ? AX_TXD_DATA_STBC : 0) |
(info->f_ldpc ? AX_TXD_DATA_LDPC : 0) |
(info->dis_data_rate_fb ? AX_TXD_DISDATAFB : 0) |
(info->dis_rts_rate_fb ? AX_TXD_DISRTSFB : 0) |
SET_WORD(info->hal_port, AX_TXD_MULTIPORT_ID) |
SET_WORD(info->mbssid, AX_TXD_MBSSID));
wdi->dword1 =
cpu_to_le32(SET_WORD(info->max_agg_num, AX_TXD_MAX_AGG_NUM) |
SET_WORD(info->data_tx_cnt_lmt, AX_TXD_DATA_TXCNT_LMT) |
(info->data_tx_cnt_lmt_en ?
AX_TXD_DATA_TXCNT_LMT_SEL : 0) |
(info->bc || info->mc ? AX_TXD_BMC : 0) |
(info->nav_use_hdr ? AX_TXD_NAVUSEHDR : 0));
wdi->dword2 =
cpu_to_le32(SET_WORD(info->life_time_sel, AX_TXD_LIFETIME_SEL) |
SET_WORD(info->sec_type, AX_TXD_SECTYPE) |
(info->sec_hw_enc ? AX_TXD_SEC_HW_ENC : 0) |
SET_WORD(info->sec_cam_idx, AX_TXD_SEC_CAM_IDX) |
SET_WORD(info->ampdu_density,
AX_TXD_AMPDU_DENSITY));
wdi->dword3 =
cpu_to_le32((info->sifs_tx ? AX_TXD_SIFS_TX : 0) |
SET_WORD(info->ndpa, AX_TXD_NDPA) |
SET_WORD(info->snd_pkt_sel, AX_TXD_SND_PKT_SEL) |
(info->rtt_en ? AX_TXD_RTT_EN : 0) |
(info->spe_rpt ? AX_TXD_SPE_RPT : 0));
wdi->dword4 =
cpu_to_le32((info->rts_en ? AX_TXD_RTS_EN : 0) |
(info->cts2self ? AX_TXD_CTS2SELF : 0) |
SET_WORD(info->rts_cca_mode, AX_TXD_CCA_RTS) |
(info->hw_rts_en ? AX_TXD_HW_RTS_EN : 0) |
SET_WORD(info->sw_define, AX_TXD_SW_DEFINE));
wdi->dword5 = 0;
#if MAC_AX_FEATURE_HV
txdes_proc_hv(adapter, info, wdb, wdi);
#endif
if (info->wdinfo_en)
PLTFM_MEMCPY(buf + WD_BODY_LEN, (u8 *)wdi, WD_INFO_LEN);
if (adapter->hw_info->wd_checksum_en) {
ret = mac_wd_checksum(adapter, info, buf);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] mac_wd_checksum %d\n", ret);
return ret;
}
}
return MACSUCCESS;
}
static struct txd_proc_type txdes_proc_mac[] = {
{RTW_PHL_PKT_TYPE_H2C, txdes_proc_h2c_fwdl},
{RTW_PHL_PKT_TYPE_FWDL, txdes_proc_h2c_fwdl},
{RTW_PHL_PKT_TYPE_DATA, txdes_proc_data},
{RTW_PHL_PKT_TYPE_MGNT, txdes_proc_mgnt},
{RTW_PHL_PKT_TYPE_MAX, NULL},
};
u32 mac_build_txdesc(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len)
{
struct txd_proc_type *proc = txdes_proc_mac;
enum rtw_packet_type pkt_type = info->type;
u32 (*handler)(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len) = NULL;
for (; proc->type != RTW_PHL_PKT_TYPE_MAX; proc++) {
if (pkt_type == proc->type) {
handler = proc->handler;
break;
}
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null type handler type: %X\n", proc->type);
return MACNOITEM;
}
return handler(adapter, info, buf, len);
}
u32 mac_refill_txdesc(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *txpkt_info,
struct mac_ax_refill_info *mask,
struct mac_ax_refill_info *info)
{
u32 dw0 = ((struct wd_body_t *)info->pkt)->dword0;
u32 dw1 = ((struct wd_body_t *)info->pkt)->dword1;
u32 ret;
if (mask->packet_offset)
((struct wd_body_t *)info->pkt)->dword0 =
dw0 | (info->packet_offset ? AX_TXD_PKT_OFFSET : 0);
if (mask->agg_num == AX_TXD_DMA_TXAGG_NUM_MSK)
((struct wd_body_t *)info->pkt)->dword1 =
SET_CLR_WORD(dw1, info->agg_num, AX_TXD_DMA_TXAGG_NUM);
if (adapter->hw_info->wd_checksum_en) {
ret = mac_wd_checksum(adapter, txpkt_info, info->pkt);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] mac_wd_checksum %d\n", ret);
return ret;
}
}
return MACSUCCESS;
}
static u32 rxdes_parse_comm(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf)
{
u32 hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword0);
info->rxdlen = hdr_val & AX_RXD_LONG_RXD ? RXD_LONG_LEN : RXD_SHORT_LEN;
info->pktsize = GET_FIELD(hdr_val, AX_RXD_RPKT_LEN);
info->shift = (u8)GET_FIELD(hdr_val, AX_RXD_SHIFT);
info->drvsize = (u8)GET_FIELD(hdr_val, AX_RXD_DRV_INFO_SIZE);
return MACSUCCESS;
}
static u32 rxdes_parse_wifi(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len)
{
u32 hdr_val;
info->type = MAC_AX_PKT_DATA;
hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword3);
info->u.data.crc_err = !!(hdr_val & AX_RXD_CRC32_ERR);
info->u.data.icv_err = !!(hdr_val & AX_RXD_ICV_ERR);
return MACSUCCESS;
}
static u32 rxdes_parse_c2h(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len)
{
info->type = MAC_AX_PKT_C2H;
return MACSUCCESS;
}
static u32 rxdes_parse_ch_info(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len)
{
info->type = MAC_AX_PKT_CH_INFO;
return MACSUCCESS;
}
static u32 rxdes_parse_dfs(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len)
{
info->type = MAC_AX_PKT_DFS;
return MACSUCCESS;
}
static u32 rxdes_parse_ppdu(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len)
{
u32 hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword0);
info->type = MAC_AX_PKT_PPDU;
info->u.ppdu.mac_info = !!(hdr_val & AX_RXD_MAC_INFO_VLD);
return MACSUCCESS;
}
static struct rxd_parse_type rxdes_parse_mac[] = {
{RXD_S_RPKT_TYPE_WIFI, rxdes_parse_wifi},
{RXD_S_RPKT_TYPE_C2H, rxdes_parse_c2h},
{RXD_S_RPKT_TYPE_PPDU, rxdes_parse_ppdu},
{RXD_S_RPKT_TYPE_CH_INFO, rxdes_parse_ch_info},
{RXD_S_RPKT_TYPE_DFS_RPT, rxdes_parse_dfs},
{RXD_RPKT_TYPE_INVALID, NULL},
};
u32 mac_parse_rxdesc(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len)
{
struct rxd_parse_type *parse = rxdes_parse_mac;
u8 rpkt_type;
u32 hdr_val;
u32 (*handler)(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len) = NULL;
hdr_val = le32_to_cpu(((struct rxd_short_t *)buf)->dword0);
rpkt_type = (u8)GET_FIELD(hdr_val, AX_RXD_RPKT_TYPE);
rxdes_parse_comm(adapter, info, buf);
for (; parse->type != RXD_RPKT_TYPE_INVALID; parse++) {
if (rpkt_type == parse->type) {
handler = parse->handler;
break;
}
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null type handler type: %X\n", parse->type);
return MACNOITEM;
}
return handler(adapter, info, buf, len);
}
u32 mac_wd_checksum(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *wddesc)
{
u16 chksum = 0;
u32 wddesc_size;
u16 *data;
u32 i, dw4;
if (!wddesc) {
PLTFM_MSG_ERR("[ERR]null pointer\n");
return MACNPTR;
}
if (adapter->hw_info->wd_checksum_en != 1)
PLTFM_MSG_TRACE("[TRACE]chksum disable\n");
dw4 = ((struct wd_body_t *)wddesc)->dword4;
((struct wd_body_t *)wddesc)->dword4 =
SET_CLR_WORD(dw4, 0x0, AX_TXD_TXDESC_CHECKSUM);
data = (u16 *)(wddesc);
/*unit : 4 bytes*/
wddesc_size = mac_txdesc_len(adapter, info) >> 2;
for (i = 0; i < wddesc_size; i++)
chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1)));
/* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/
/* Process eniadn issue after checksum calculation */
((struct wd_body_t *)wddesc)->dword4 =
SET_CLR_WORD(dw4, (u16)(chksum), AX_TXD_TXDESC_CHECKSUM);
return MACSUCCESS;
}
u32 mac_patch_rx_rate(struct mac_ax_adapter *adapter,
struct rtw_r_meta_data *info)
{
u32 nss;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
return MACSUCCESS;
if (is_cv(adapter, CBV)) {
if (info->rpkt_type != RX_8852A_DESC_PKT_T_WIFI ||
info->ppdu_type != RX_8852A_DESC_PPDU_T_HE_SU ||
info->rx_gi_ltf != RX_8852A_DESC_RX_GI_LTF_4X_0_8)
return MACSUCCESS;
nss = GET_NSS_FROM_RX_RATE(info->rx_rate);
if (nss == NSS_1) /* real nss = 2 */
info->rx_rate = SET_NSS_TO_RX_RATE(info->rx_rate, NSS_2);
else if (nss == NSS_8) /* real nss = 1 */
info->rx_rate = SET_NSS_TO_RX_RATE(info->rx_rate, NSS_1);
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/trx_desc.c
|
C
|
agpl-3.0
| 18,967
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_TRX_DESC_H_
#define _MAC_AX_TRX_DESC_H_
#include "../type.h"
#include "role.h"
#if MAC_AX_8852C_SUPPORT
#include "mac_8852c/trx_desc_8852c.h"
#endif
#if MAC_AX_8192XB_SUPPORT
#include "mac_8192xb/trx_desc_8192xb.h"
#endif
/* VHT/HE nss = rx_rate[6:4] */
#define GET_NSS_FROM_RX_RATE(rate) (((rate) & 0x70) >> 4)
#define SET_NSS_TO_RX_RATE(rate, nss) (((rate) & 0xFF8F) | (((nss) & 0x7) << 4))
/**
* 0000: WIFI packet
* 0001: PPDU status
* 0010: channel info
* 0011: BB scope mode
* 0100: F2P TX CMD report
* 0101: SS2FW report
* 0110: TX report
* 0111: TX payload release to host
* 1000: DFS report
* 1001: TX payload release to WLCPU
* 1010: C2H packet
*/
#define RX_8852A_DESC_PKT_T_WIFI 0
#define RX_8852A_DESC_PKT_T_PPDU_STATUS 1
#define RX_8852A_DESC_PKT_T_CHANNEL_INFO 2
#define RX_8852A_DESC_PKT_T_BB_SCOPE 3
#define RX_8852A_DESC_PKT_T_F2P_TX_CMD_RPT 4
#define RX_8852A_DESC_PKT_T_SS2FW_RPT 5
#define RX_8852A_DESC_PKT_T_TX_RPT 6
#define RX_8852A_DESC_PKT_T_TX_PD_RELEASE_HOST 7
#define RX_8852A_DESC_PKT_T_DFS_RPT 8
#define RX_8852A_DESC_PKT_T_TX_PD_RELEASE_WLCPU 9
#define RX_8852A_DESC_PKT_T_C2H 10
#define RX_8852A_DESC_PPDU_T_LCCK 0
#define RX_8852A_DESC_PPDU_T_SCCK 1
#define RX_8852A_DESC_PPDU_T_OFDM 2
#define RX_8852A_DESC_PPDU_T_HT 3
#define RX_8852A_DESC_PPDU_T_HTGF 4
#define RX_8852A_DESC_PPDU_T_VHT_SU 5
#define RX_8852A_DESC_PPDU_T_VHT_MU 6
#define RX_8852A_DESC_PPDU_T_HE_SU 7
#define RX_8852A_DESC_PPDU_T_HE_ERSU 8
#define RX_8852A_DESC_PPDU_T_HE_MU 9
#define RX_8852A_DESC_PPDU_T_HE_TB 10
#define RX_8852A_DESC_PPDU_T_UNKNOWN 15
#define RX_8852A_DESC_RX_GI_LTF_4X_3_2 0
#define RX_8852A_DESC_RX_GI_LTF_4X_0_8 1
#define RX_8852A_DESC_RX_GI_LTF_2X_1_6 2
#define RX_8852A_DESC_RX_GI_LTF_2X_0_8 3
#define RX_8852A_DESC_RX_GI_LTF_1X_1_6 4
#define RX_8852A_DESC_RX_GI_LTF_1X_0_8 5
#define NSS_8 7
#define NSS_7 6
#define NSS_6 5
#define NSS_5 4
#define NSS_4 3
#define NSS_3 2
#define NSS_2 1
#define NSS_1 0
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_txdesc_len
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_txdesc_len(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_build_txdesc
*
* @param *adapter
* @param *info
* @param *buf
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_build_txdesc(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_refill_txdesc
*
* @param *adapter
* @param *txpkt_info
* @param *mask
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_refill_txdesc(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *txpkt_info,
struct mac_ax_refill_info *mask,
struct mac_ax_refill_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_parse_rxdesc
*
* @param *adapter
* @param *info
* @param *buf
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_parse_rxdesc(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_wd_checksum
*
* @param *adapter
* @param *info
* @param *wddesc
* @return Please Place Description here.
* @retval u32
*/
u32 mac_wd_checksum(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *wddesc);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_patch_rx_rate
*
* @param *adapter
* @param *rtw_r_meta_data
* @return For RMAC rate patch func
* @retval u32
*/
u32 mac_patch_rx_rate(struct mac_ax_adapter *adapter,
struct rtw_r_meta_data *info);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/trx_desc.h
|
C
|
agpl-3.0
| 4,786
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "trxcfg.h"
inline u32 check_mac_en(struct mac_ax_adapter *adapter, u8 band,
enum mac_ax_hwmod_sel sel)
{
if (adapter->sm.pwr != MAC_AX_PWR_ON)
return MACPROCERR;
if (sel == MAC_AX_DMAC_SEL) {
if (adapter->sm.dmac_func != MAC_AX_FUNC_ON)
return MACIOERRDMAC;
} else if (sel == MAC_AX_CMAC_SEL && band == MAC_AX_BAND_0) {
if (adapter->sm.cmac0_func != MAC_AX_FUNC_ON)
return MACIOERRCMAC0;
} else if (sel == MAC_AX_CMAC_SEL && band == MAC_AX_BAND_1) {
if (adapter->sm.cmac1_func != MAC_AX_FUNC_ON)
return MACIOERRCMAC1;
} else {
PLTFM_MSG_ERR("[ERR] mac sel: %d\n", sel);
return MACNOITEM;
}
return MACSUCCESS;
}
static u32 scheduler_imr_enable(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
reg = band == MAC_AX_BAND_0 ?
R_AX_SCHEDULE_ERR_IMR : R_AX_SCHEDULE_ERR_IMR_C1;
val32 = MAC_REG_R32(reg);
val32 &= ~(B_AX_SORT_NON_IDLE_ERR_INT_EN |
B_AX_FSM_TIMEOUT_ERR_INT_EN);
val32 |= ((B_AX_SORT_NON_IDLE_ERR_INT_EN &
SCHEDULER_SORT_NON_IDLE_ERR_SER_EN) |
(B_AX_FSM_TIMEOUT_ERR_INT_EN &
SCHEDULER_FSM_TIMEOUT_ERR_SER_EN));
MAC_REG_W32(reg, val32);
return 0;
}
static u32 ptcl_imr_enable(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
reg = band == MAC_AX_BAND_0 ?
R_AX_PTCL_IMR0 : R_AX_PTCL_IMR0_C1;
val32 = 0;
val32 &= ~(B_AX_FSM_TIMEOUT_ERR_INT_EN |
B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN |
B_AX_TXPRT_FULL_DROP_ERR_INT_EN |
B_AX_D_PKTID_ERR_INT_EN |
B_AX_Q_PKTID_ERR_INT_EN |
B_AX_BCNQ_ORDER_ERR_INT_EN |
B_AX_TWTSP_QSEL_ERR_INT_EN |
B_AX_F2PCMD_EMPTY_ERR_INT_EN |
B_AX_TX_RECORD_PKTID_ERR_INT_EN |
B_AX_TX_SPF_U3_PKTID_ERR_INT_EN |
B_AX_TX_SPF_U2_PKTID_ERR_INT_EN |
B_AX_TX_SPF_U1_PKTID_ERR_INT_EN |
B_AX_RX_SPF_U0_PKTID_ERR_INT_EN |
B_AX_F2PCMD_USER_ALLC_ERR_INT_EN |
B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN |
B_AX_F2PCMD_RD_PKTID_ERR_INT_EN |
B_AX_F2PCMD_PKTID_ERR_INT_EN);
val32 |= ((B_AX_FSM_TIMEOUT_ERR_INT_EN &
PTCL_FSM_TIMEOUT_ERR_SER_EN) |
(B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN &
PTCL_F2PCMDRPT_FULL_DROP_SER_EN) |
(B_AX_TXPRT_FULL_DROP_ERR_INT_EN &
PTCL_TXRPT_FULL_DROP_SER_EN) |
(B_AX_D_PKTID_ERR_INT_EN &
PTCL_D_PKTID_ERR_SER_EN) |
(B_AX_Q_PKTID_ERR_INT_EN &
PTCL_Q_PKTID_ERR_SER_EN) |
(B_AX_BCNQ_ORDER_ERR_INT_EN &
PTCL_BCNQ_ORDER_ERR_SER_EN) |
(B_AX_TWTSP_QSEL_ERR_INT_EN &
PTCL_TWTSP_QSEL_ERR_SER_EN) |
(B_AX_F2PCMD_EMPTY_ERR_INT_EN &
PTCL_F2PCMD_EMPTY_ERR_SER_EN) |
(B_AX_TX_RECORD_PKTID_ERR_INT_EN &
PTCL_TX_RECORD_PKTID_ERR_SER_EN) |
(B_AX_TX_SPF_U3_PKTID_ERR_INT_EN &
PTCL_TX_SPF_U3_PKTID_ERR_SER_EN) |
(B_AX_TX_SPF_U2_PKTID_ERR_INT_EN &
PTCL_TX_SPF_U2_PKTID_ERR_SER_EN) |
(B_AX_TX_SPF_U1_PKTID_ERR_INT_EN &
PTCL_TX_SPF_U1_PKTID_ERR_SER_EN) |
(B_AX_RX_SPF_U0_PKTID_ERR_INT_EN &
PTCL_TX_SPF_U0_PKTID_ERR_SER_EN) |
(B_AX_F2PCMD_USER_ALLC_ERR_INT_EN &
PTCL_F2PCMD_USER_ALLC_ERR_SER_EN) |
(B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN &
PTCL_F2PCMD_ASSIGN_PKTID_ERR_SER_EN) |
(B_AX_F2PCMD_RD_PKTID_ERR_INT_EN &
PTCL_F2PCMD_RD_PKTID_ERR_SER_EN) |
(B_AX_F2PCMD_PKTID_ERR_INT_EN &
PTCL_F2PCMD_PKTID_ERR_SER_EN));
MAC_REG_W32(reg, val32);
return 0;
}
static u32 _patch_cdma_fa(struct mac_ax_adapter *adapter)
{
if (adapter->hw_info->chip_id == MAC_AX_CHIP_ID_8852A &&
adapter->hw_info->cv <= CBV)
/*
* AP Disable B_AX_STS_FSM_HANG_ERROR_IMR
* STA Enable B_AX_STS_FSM_HANG_ERROR_IMR (Wait for "Scan+SER L0")
*/
return 0;
else if (adapter->hw_info->chip_id == MAC_AX_CHIP_ID_8852B &&
adapter->hw_info->cv == CAV)
return B_AX_RXSTS_FSM_HANG_ERROR_IMR |
B_AX_RXDATA_FSM_HANG_ERROR_IMR;
return B_AX_RXSTS_FSM_HANG_ERROR_IMR | B_AX_RXDATA_FSM_HANG_ERROR_IMR;
}
static u32 cdma_imr_enable(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
reg = band == MAC_AX_BAND_0 ? R_AX_DLE_CTRL : R_AX_DLE_CTRL_C1;
val32 = MAC_REG_R32(reg);
val32 &= ~(B_AX_RXSTS_FSM_HANG_ERROR_IMR |
B_AX_RXDATA_FSM_HANG_ERROR_IMR |
B_AX_NO_RESERVE_PAGE_ERR_IMR);
val32 |= ((B_AX_RXSTS_FSM_HANG_ERROR_IMR &
CMAC_DMA_RXSTS_FSM_HANG_SER_EN) |
(B_AX_RXDATA_FSM_HANG_ERROR_IMR &
CMAC_DMA_RXDATA_FSM_HANG_SER_EN) |
(B_AX_NO_RESERVE_PAGE_ERR_IMR &
CMAC_DMA_NO_RSVD_PAGE_SER_EN));
val32 |= _patch_cdma_fa(adapter);
MAC_REG_W32(reg, val32);
return 0;
}
static u32 phy_intf_imr_enable(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u16 val16;
u32 reg;
reg = band == MAC_AX_BAND_0 ?
R_AX_PHYINFO_ERR_IMR : R_AX_PHYINFO_ERR_IMR_C1;
val16 = MAC_REG_R16(reg);
val16 &= ~(B_AXC_PHY_TXON_TIMEOUT_INT_EN |
B_AX_CCK_CCA_TIMEOUT_INT_EN |
B_AX_OFDM_CCA_TIMEOUT_INT_EN |
B_AX_DATA_ON_TIMEOUT_INT_EN |
B_AX_STS_ON_TIMEOUT_INT_EN |
B_AX_CSI_ON_TIMEOUT_INT_EN);
val16 |= ((B_AXC_PHY_TXON_TIMEOUT_INT_EN &
PHYINTF_PHY_TXON_TIMEOUT_ERR_SER_EN) |
(B_AX_CCK_CCA_TIMEOUT_INT_EN &
PHYINTF_CCK_CCA_TIMEOUT_ERR_SER_EN) |
(B_AX_OFDM_CCA_TIMEOUT_INT_EN &
PHYINTF_OFDM_CCA_TIMEOUT_ERR_SER_EN) |
(B_AX_DATA_ON_TIMEOUT_INT_EN &
PHYINTF_DATA_ON_TIMEOUT_ERR_SER_EN) |
(B_AX_STS_ON_TIMEOUT_INT_EN &
PHYINTF_STS_ON_TIMEOUT_ERR_SER_EN) |
(B_AX_CSI_ON_TIMEOUT_INT_EN &
PHYINTF_CSI_ON_TIMEOUT_ERR_SER_EN));
MAC_REG_W16(reg, val16);
return 0;
}
static u32 rmac_imr_enable(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
reg = band == MAC_AX_BAND_0 ?
R_AX_RMAC_ERR_ISR : R_AX_RMAC_ERR_ISR_C1;
val32 = MAC_REG_R32(reg);
val32 &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN |
B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN |
B_AX_RMAC_DMA_TIMEOUT_INT_EN |
B_AX_RMAC_CCA_TIMEOUT_INT_EN |
B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN |
B_AX_RMAC_CSI_TIMEOUT_INT_EN |
B_AX_RMAC_RX_TIMEOUT_INT_EN |
B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN);
val32 |= ((B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN &
RMAC_CCA_TO_RX_IDLE_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN &
RMAC_DATA_ON_TO_RX_IDLE_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_DMA_TIMEOUT_INT_EN &
RMAC_DMA_WRITE_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_CCA_TIMEOUT_INT_EN &
RMAC_CCA_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN &
RMAC_DATA_ON_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_CSI_TIMEOUT_INT_EN &
RMAC_CSI_DATA_ON_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_RX_TIMEOUT_INT_EN &
RMAC_RX_FSM_TIMEOUT_ERR_SER_EN) |
(B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN &
RMAC_CSI_MODE_TIMEOUT_ERR_SER_EN));
MAC_REG_W32(reg, val32);
return 0;
}
static u32 tmac_imr_enable(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
reg = band == MAC_AX_BAND_0 ?
R_AX_TMAC_ERR_IMR_ISR : R_AX_TMAC_ERR_IMR_ISR_C1;
val32 = MAC_REG_R32(reg);
val32 &= ~(B_AX_TMAC_MACTX_INT_EN |
B_AX_TMAC_TXCTL_INT_EN |
B_AX_TMAC_RESP_INT_EN |
B_AX_TMAC_TXPLCP_INT_EN);
val32 |= ((B_AX_TMAC_MACTX_INT_EN &
TMAC_MACTX_TIME_ERR_SER_EN) |
(B_AX_TMAC_TXCTL_INT_EN &
TMAC_TRXPTCL_TXCTL_TIMEOUT_ERR_SER_EN) |
(B_AX_TMAC_RESP_INT_EN &
TMAC_RESPONSE_TXCTL_TIMEOUT_ERR_SER_EN) |
(B_AX_TMAC_TXPLCP_INT_EN &
TMAC_TX_PLCP_INFO_ERR_SER_EN));
MAC_REG_W32(reg, val32);
return 0;
}
static u32 wdrls_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_WDRLS_ERR_IMR);
val32 &= ~(B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN |
B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN |
B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN |
B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN |
B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN |
B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN |
B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN |
B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN |
B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN);
val32 |= ((B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN &
DMAC_WDRLS_CTL_WDPKTID_ISNULL_ERR_SER_EN) |
(B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN &
DMAC_WDRLS_CTL_PLPKTID_ISNULL_ERR_SER_EN) |
(B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN &
DMAC_WDRLS_CTL_FRZTO_ERR_SER_EN) |
(B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN &
DMAC_WDRLS_PLEBREQ_TO_ERR_SER_EN) |
(B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN &
DMAC_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_SER_EN) |
(B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN &
DMAC_WDRLS_RPT0_AGGNUM0_ERR_SER_EN) |
(B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN &
DMAC_WDRLS_RPT0_FRZTO_ERR_SER_EN) |
(B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN &
DMAC_WDRLS_RPT1_AGGNUM0_ERR_SER_EN) |
(B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN &
DMAC_WDRLS_RPT1_FRZTO_ERR_SER_EN));
MAC_REG_W32(R_AX_WDRLS_ERR_IMR, val32);
return 0;
}
static u32 wsec_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_SEC_DEBUG);
val32 &= ~(B_AX_IMR_ERROR);
val32 |= ((B_AX_IMR_ERROR &
DMAC_IMR_ERROR));
MAC_REG_W32(R_AX_SEC_DEBUG, val32);
return 0;
}
static u32 mpdu_trx_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
/* MDPU Processor TX */
val32 = MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR);
val32 &= ~(B_AX_TX_GET_ERRPKTID_INT_EN |
B_AX_TX_NXT_ERRPKTID_INT_EN |
B_AX_TX_MPDU_SIZE_ZERO_INT_EN |
B_AX_TX_OFFSET_ERR_INT_EN |
B_AX_TX_HDR3_SIZE_ERR_INT_EN);
val32 |= ((B_AX_TX_GET_ERRPKTID_INT_EN &
DMAC_TX_GET_ERRPKTID_SER_EN) |
(B_AX_TX_NXT_ERRPKTID_INT_EN &
DMAC_TX_NXT_ERRPKTID_SER_EN) |
(B_AX_TX_MPDU_SIZE_ZERO_INT_EN &
DMAC_TX_MPDU_SIZE_ZERO_SER_EN) |
(B_AX_TX_OFFSET_ERR_INT_EN &
DMAC_TX_OFFSET_ERR_SER_EN) |
(B_AX_TX_HDR3_SIZE_ERR_INT_EN &
DMAC_TX_HDR3_SIZE_ERR_SER_EN));
MAC_REG_W32(R_AX_MPDU_TX_ERR_IMR, val32);
/* MDPU Processor RX */
val32 = MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR);
val32 &= ~(B_AX_GETPKTID_ERR_INT_EN |
B_AX_MHDRLEN_ERR_INT_EN |
B_AX_RPT_ERR_INT_EN);
val32 |= ((B_AX_GETPKTID_ERR_INT_EN &
DMAC_GETPKTID_ERR_SER_EN) |
(B_AX_MHDRLEN_ERR_INT_EN &
DMAC_MHDRLEN_ERR_SER_EN) |
(B_AX_RPT_ERR_INT_EN &
DMAC_RPT_ERR_SER_EN));
MAC_REG_W32(R_AX_MPDU_RX_ERR_IMR, val32);
return 0;
}
static u32 sta_sch_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
/* MDPU Processor TX */
val32 = MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR);
val32 &= ~(B_AX_SEARCH_HANG_TIMEOUT_INT_EN |
B_AX_RPT_HANG_TIMEOUT_INT_EN |
B_AX_PLE_B_PKTID_ERR_INT_EN);
val32 |= ((B_AX_SEARCH_HANG_TIMEOUT_INT_EN &
DMAC_SEARCH_HANG_TIMEOUT_SER_EN) |
(B_AX_RPT_HANG_TIMEOUT_INT_EN &
DMAC_RPT_HANG_TIMEOUT_SER_EN) |
(B_AX_PLE_B_PKTID_ERR_INT_EN &
DMAC_PLE_B_PKTID_ERR_SER_EN));
MAC_REG_W32(R_AX_STA_SCHEDULER_ERR_IMR, val32);
return 0;
}
static u32 txpktctl_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR);
val32 &= ~(B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN |
B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN |
B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN |
B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN |
B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN |
B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN);
val32 |= ((B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_REINIT_ERR_SER_EN) |
(B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_NOINIT_ERR_SER_EN) |
(B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_SER_EN) |
(B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_SER_EN) |
(B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN &
DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_SER_EN) |
(B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN &
DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_SER_EN));
MAC_REG_W32(R_AX_TXPKTCTL_ERR_IMR_ISR, val32);
val32 = MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1);
val32 &= ~(B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN |
B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN |
B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN |
B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN |
B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN |
B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN);
val32 |= ((B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_REINIT_B1_ERR_SER_EN) |
(B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_NOINIT_B1_ERR_SER_EN) |
(B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_RDNRLSCMD_B1_ERR_SER_EN) |
(B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN &
DMAC_TXPKTCTL_USRCTL_RLSBMPLEN_B1_ERR_SER_EN) |
(B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN &
DMAC_TXPKTCTL_CMDPSR_CMDTYPE_ERR_B1_SER_EN) |
(B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN &
DMAC_TXPKTCTL_CMDPSR_FRZTO_ERR_B1_SER_EN));
MAC_REG_W32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1, val32);
return 0;
}
static u32 wde_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_WDE_ERR_IMR);
val32 &= ~(B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN |
B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN |
B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN |
B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN |
B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN |
B_AX_WDE_GETNPG_STRPG_ERR_INT_EN |
B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN |
B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN |
B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN |
B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN |
B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN |
B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN |
B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN |
B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN |
B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN |
B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN |
B_AX_WDE_DATCHN_ARBT_ERR_INT_EN |
B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN |
B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN);
val32 |= ((B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN &
DMAC_WDE_BUFREQ_QTAID_ERR_SER_EN) |
(B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN &
DMAC_WDE_BUFREQ_UNAVAL_ERR_SER_EN) |
(B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN &
DMAC_WDE_BUFRTN_INVLD_PKTID_ERR_SER_EN) |
(B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN &
DMAC_WDE_BUFRTN_SIZE_ERR_SER_EN) |
(B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN &
DMAC_WDE_BUFREQ_SRCHTAILPG_ERR_SER_EN) |
(B_AX_WDE_GETNPG_STRPG_ERR_INT_EN &
DMAC_WDE_GETNPG_STRPG_ERR_SER_EN) |
(B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN &
DMAC_WDE_GETNPG_PGOFST_ERR_SER_EN) |
(B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN &
DMAC_WDE_BUFMGN_FRZTO_ERR_SER_EN) |
(B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN &
DMAC_WDE_QUE_CMDTYPE_ERR_SER_EN) |
(B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN &
DMAC_WDE_QUE_DSTQUEID_ERR_SER_EN) |
(B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN &
DMAC_WDE_QUE_SRCQUEID_ERR_SER_EN) |
(B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN &
DMAC_WDE_ENQ_PKTCNT_OVRF_ERR_SER_EN) |
(B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN &
DMAC_WDE_ENQ_PKTCNT_NVAL_ERR_SER_EN) |
(B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN &
DMAC_WDE_PREPKTLLT_AD_ERR_SER_EN) |
(B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN &
DMAC_WDE_NXTPKTLL_AD_ERR_SER_EN) |
(B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN &
DMAC_WDE_QUEMGN_FRZTO_ERR_SER_EN) |
(B_AX_WDE_DATCHN_ARBT_ERR_INT_EN &
DMAC_WDE_DATCHN_ARBT_ERR_SER_EN) |
(B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN &
DMAC_WDE_DATCHN_NULLPG_ERR_SER_EN) |
(B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN &
DMAC_WDE_DATCHN_FRZTO_ERR_SER_EN));
MAC_REG_W32(R_AX_WDE_ERR_IMR, val32);
return 0;
}
static u32 ple_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_PLE_ERR_IMR);
val32 &= ~(B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN |
B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN |
B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN |
B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN |
B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN |
B_AX_PLE_GETNPG_STRPG_ERR_INT_EN |
B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN |
B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN |
B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN |
B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN |
B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN |
B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN |
B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN |
B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN |
B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN |
B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN |
B_AX_PLE_DATCHN_ARBT_ERR_INT_EN |
B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN |
B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN);
val32 |= ((B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN &
DMAC_PLE_BUFREQ_QTAID_ERR_SER_EN) |
(B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN &
DMAC_PLE_BUFREQ_UNAVAL_ERR_SER_EN) |
(B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN &
DMAC_PLE_BUFRTN_INVLD_PKTID_ERR_SER_EN) |
(B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN &
DMAC_PLE_BUFRTN_SIZE_ERR_SER_EN) |
(B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN &
DMAC_PLE_BUFREQ_SRCHTAILPG_ERR_SER_EN) |
(B_AX_PLE_GETNPG_STRPG_ERR_INT_EN &
DMAC_PLE_GETNPG_STRPG_ERR_SER_EN) |
(B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN &
DMAC_PLE_GETNPG_PGOFST_ERR_SER_EN) |
(B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN &
DMAC_PLE_BUFMGN_FRZTO_ERR_SER_EN) |
(B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN &
DMAC_PLE_QUE_CMDTYPE_ERR_SER_EN) |
(B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN &
DMAC_PLE_QUE_DSTQUEID_ERR_SER_EN) |
(B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN &
DMAC_PLE_QUE_SRCQUEID_ERR_SER_EN) |
(B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN &
DMAC_PLE_ENQ_PKTCNT_OVRF_ERR_SER_EN) |
(B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN &
DMAC_PLE_ENQ_PKTCNT_NVAL_ERR_SER_EN) |
(B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN &
DMAC_PLE_PREPKTLLT_AD_ERR_SER_EN) |
(B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN &
DMAC_PLE_NXTPKTLL_AD_ERR_SER_EN) |
(B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN &
DMAC_PLE_QUEMGN_FRZTO_ERR_SER_EN) |
(B_AX_PLE_DATCHN_ARBT_ERR_INT_EN &
DMAC_PLE_DATCHN_ARBT_ERR_SER_EN) |
(B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN &
DMAC_PLE_DATCHN_NULLPG_ERR_SER_EN) |
(B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN &
DMAC_PLE_DATCHN_FRZTO_ERR_SER_EN));
MAC_REG_W32(R_AX_PLE_ERR_IMR, val32);
return 0;
}
static u32 pktin_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_PKTIN_ERR_IMR);
val32 &= ~(B_AX_PKTIN_GETPKTID_ERR_INT_EN);
val32 |= ((B_AX_PKTIN_GETPKTID_ERR_INT_EN &
DMAC_PKTIN_GETPKTID_ERR_SER_EN));
MAC_REG_W32(R_AX_PKTIN_ERR_IMR, val32);
return 0;
}
static u32 dispatcher_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR);
val32 &= ~(B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN |
B_AX_HDT_CHANNEL_ID_ERR_INT_EN |
B_AX_HDT_PKT_FAIL_DBG_INT_EN |
B_AX_HDT_PERMU_OVERFLOW_INT_EN |
B_AX_HDT_PERMU_UNDERFLOW_INT_EN |
B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN |
B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN |
B_AX_HDT_OFFSET_UNMATCH_INT_EN |
B_AX_HDT_CHANNEL_DMA_ERR_INT_EN |
B_AX_HDT_WD_CHK_ERR_INT_EN |
B_AX_HDT_PRE_COST_ERR_INT_EN |
B_AX_HDT_TXPKTSIZE_ERR_INT_EN |
B_AX_HDT_TCP_CHK_ERR_INT_EN |
B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN |
B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN |
B_AX_HDT_PLD_CMD_OVERLOW_INT_EN |
B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN |
B_AX_HDT_FLOW_CTRL_ERR_INT_EN |
B_AX_HDT_NULLPKT_ERR_INT_EN |
B_AX_HDT_BURST_NUM_ERR_INT_EN |
B_AX_HDT_RXAGG_CFG_ERR_INT_EN |
B_AX_HDT_SHIFT_EN_ERR_INT_EN |
B_AX_HDT_TOTAL_LEN_ERR_INT_EN |
B_AX_HDT_DMA_PROCESS_ERR_INT_EN |
B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN |
B_AX_HDT_CHKSUM_FSM_ERR_INT_EN |
B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN |
B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN);
val32 |= ((B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN &
DMAC_HDT_CHANNEL_DIFF_ERR_SER_EN) |
(B_AX_HDT_CHANNEL_ID_ERR_INT_EN &
DMAC_HDT_CHANNEL_ID_ERR_SER_EN) |
(B_AX_HDT_PKT_FAIL_DBG_INT_EN &
DMAC_HDT_PKT_FAIL_DBG_SER_EN) |
(B_AX_HDT_PERMU_OVERFLOW_INT_EN &
DMAC_HDT_PERMU_OVERFLOW_SER_EN) |
(B_AX_HDT_PERMU_UNDERFLOW_INT_EN &
DMAC_HDT_PERMU_UNDERFLOW_SER_EN) |
(B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN &
DMAC_HDT_PAYLOAD_OVERFLOW_SER_EN) |
(B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN &
DMAC_HDT_PAYLOAD_UNDERFLOW_SER_EN) |
(B_AX_HDT_OFFSET_UNMATCH_INT_EN &
DMAC_HDT_OFFSET_UNMATCH_SER_EN) |
(B_AX_HDT_CHANNEL_DMA_ERR_INT_EN &
DMAC_HDT_CHANNEL_DMA_ERR_SER_EN) |
(B_AX_HDT_WD_CHK_ERR_INT_EN &
DMAC_HDT_WD_CHK_ERR_SER_EN) |
(B_AX_HDT_PRE_COST_ERR_INT_EN &
DMAC_HDT_PRE_COST_ERR_SER_EN) |
(B_AX_HDT_TXPKTSIZE_ERR_INT_EN &
DMAC_HDT_TXPKTSIZE_ERR_SER_EN) |
(B_AX_HDT_TCP_CHK_ERR_INT_EN &
DMAC_HDT_TCP_CHK_ERR_SER_EN) |
(B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN &
DMAC_HDT_TX_WRITE_OVERFLOW_SER_EN) |
(B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN &
DMAC_HDT_TX_WRITE_UNDERFLOW_SER_EN) |
(B_AX_HDT_PLD_CMD_OVERLOW_INT_EN &
DMAC_HDT_PLD_CMD_OVERLOW_SER_EN) |
(B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN &
DMAC_HDT_PLD_CMD_UNDERFLOW_SER_EN) |
(B_AX_HDT_FLOW_CTRL_ERR_INT_EN &
DMAC_HDT_FLOW_CTRL_ERR_SER_EN) |
(B_AX_HDT_NULLPKT_ERR_INT_EN &
DMAC_HDT_NULLPKT_ERR_SER_EN) |
(B_AX_HDT_BURST_NUM_ERR_INT_EN &
DMAC_HDT_BURST_NUM_ERR_SER_EN) |
(B_AX_HDT_RXAGG_CFG_ERR_INT_EN &
DMAC_HDT_RXAGG_CFG_ERR_SER_EN) |
(B_AX_HDT_SHIFT_EN_ERR_INT_EN &
DMAC_HDT_SHIFT_EN_ERR_SER_EN) |
(B_AX_HDT_TOTAL_LEN_ERR_INT_EN &
DMAC_HDT_TOTAL_LEN_ERR_SER_EN) |
(B_AX_HDT_DMA_PROCESS_ERR_INT_EN &
DMAC_HDT_DMA_PROCESS_ERR_SER_EN) |
(B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN &
DMAC_HDT_SHIFT_DMA_CFG_ERR_SER_EN) |
(B_AX_HDT_CHKSUM_FSM_ERR_INT_EN &
DMAC_HDT_CHKSUM_FSM_ERR_SER_EN) |
(B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN &
DMAC_HDT_RX_WRITE_OVERFLOW_SER_EN) |
(B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN &
DMAC_HDT_RX_WRITE_UNDERFLOW_SER_EN));
MAC_REG_W32(R_AX_HOST_DISPATCHER_ERR_IMR, val32);
val32 = MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR);
val32 &= ~(B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN |
B_AX_CPU_PKT_FAIL_DBG_INT_EN |
B_AX_CPU_CHANNEL_ID_ERR_INT_EN |
B_AX_CPU_PERMU_OVERFLOW_INT_EN |
B_AX_CPU_PERMU_UNDERFLOW_INT_EN |
B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN |
B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN |
B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN |
B_AX_CPU_OFFSET_UNMATCH_INT_EN |
B_AX_CPU_CHANNEL_DMA_ERR_INT_EN |
B_AX_CPU_WD_CHK_ERR_INT_EN |
B_AX_CPU_PRE_COST_ERR_INT_EN |
B_AX_CPU_PLD_CMD_OVERLOW_INT_EN |
B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN |
B_AX_CPU_F2P_QSEL_ERR_INT_EN |
B_AX_CPU_F2P_SEQ_ERR_INT_EN |
B_AX_CPU_FLOW_CTRL_ERR_INT_EN |
B_AX_CPU_NULLPKT_ERR_INT_EN |
B_AX_CPU_BURST_NUM_ERR_INT_EN |
B_AX_CPU_RXAGG_CFG_ERR_INT_EN |
B_AX_CPU_SHIFT_EN_ERR_INT_EN |
B_AX_CPU_TOTAL_LEN_ERR_INT_EN |
B_AX_CPU_DMA_PROCESS_ERR_INT_EN |
B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN |
B_AX_CPU_CHKSUM_FSM_ERR_INT_EN |
B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN |
B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN);
val32 |= ((B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN &
DMAC_CPU_CHANNEL_DIFF_ERR_SER_EN) |
(B_AX_CPU_PKT_FAIL_DBG_INT_EN &
DMAC_CPU_PKT_FAIL_DBG_SER_EN) |
(B_AX_CPU_CHANNEL_ID_ERR_INT_EN &
DMAC_CPU_CHANNEL_ID_ERR_SER_EN) |
(B_AX_CPU_PERMU_OVERFLOW_INT_EN &
DMAC_CPU_PERMU_OVERFLOW_SER_EN) |
(B_AX_CPU_PERMU_UNDERFLOW_INT_EN &
DMAC_CPU_PERMU_UNDERFLOW_SER_EN) |
(B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN &
DMAC_CPU_PAYLOAD_OVERFLOW_SER_EN) |
(B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN &
DMAC_CPU_PAYLOAD_UNDERFLOW_SER_EN) |
(B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN &
DMAC_CPU_PAYLOAD_CHKSUM_ERR_SER_EN) |
(B_AX_CPU_OFFSET_UNMATCH_INT_EN &
DMAC_CPU_OFFSET_UNMATCH_SER_EN) |
(B_AX_CPU_CHANNEL_DMA_ERR_INT_EN &
DMAC_CPU_CHANNEL_DMA_ERR_SER_EN) |
(B_AX_CPU_WD_CHK_ERR_INT_EN &
DMAC_CPU_WD_CHK_ERR_SER_EN) |
(B_AX_CPU_PRE_COST_ERR_INT_EN &
DMAC_CPU_PRE_COST_ERR_SER_EN) |
(B_AX_CPU_PLD_CMD_OVERLOW_INT_EN &
DMAC_CPU_PLD_CMD_OVERLOW_SER_EN) |
(B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN &
DMAC_CPU_PLD_CMD_UNDERFLOW_SER_EN) |
(B_AX_CPU_F2P_QSEL_ERR_INT_EN &
DMAC_CPU_F2P_QSEL_ERR_SER_EN) |
(B_AX_CPU_F2P_SEQ_ERR_INT_EN &
DMAC_CPU_F2P_SEQ_ERR_SER_EN) |
(B_AX_CPU_FLOW_CTRL_ERR_INT_EN &
DMAC_CPU_FLOW_CTRL_ERR_SER_EN) |
(B_AX_CPU_NULLPKT_ERR_INT_EN &
DMAC_CPU_NULLPKT_ERR_SER_EN) |
(B_AX_CPU_BURST_NUM_ERR_INT_EN &
DMAC_CPU_BURST_NUM_ERR_SER_EN) |
(B_AX_CPU_RXAGG_CFG_ERR_INT_EN &
DMAC_CPU_RXAGG_CFG_ERR_SER_EN) |
(B_AX_CPU_SHIFT_EN_ERR_INT_EN &
DMAC_CPU_SHIFT_EN_ERR_SER_EN) |
(B_AX_CPU_TOTAL_LEN_ERR_INT_EN &
DMAC_CPU_TOTAL_LEN_ERR_SER_EN) |
(B_AX_CPU_DMA_PROCESS_ERR_INT_EN &
DMAC_CPU_DMA_PROCESS_ERR_SER_EN) |
(B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN &
DMAC_CPU_SHIFT_DMA_CFG_ERR_SER_EN) |
(B_AX_CPU_CHKSUM_FSM_ERR_INT_EN &
DMAC_CPU_CHKSUM_FSM_ERR_SER_EN));
MAC_REG_W32(R_AX_CPU_DISPATCHER_ERR_IMR, val32);
val32 = MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR);
val32 &= ~(B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN |
B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN |
B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN |
B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN |
B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN |
B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN |
B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN |
B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN |
B_AX_PLE_OUTPUT_ERR_INT_EN |
B_AX_PLE_RESP_ERR_INT_EN |
B_AX_PLE_BURST_NUM_ERR_INT_EN |
B_AX_PLE_NULL_PKT_ERR_INT_EN |
B_AX_PLE_FLOW_CTRL_ERR_INT_EN |
B_AX_WDE_OUTPUT_ERR_INT_EN |
B_AX_WDE_RESP_ERR_INT_EN |
B_AX_WDE_BURST_NUM_ERR_INT_EN |
B_AX_WDE_NULL_PKT_ERR_INT_EN |
B_AX_WDE_FLOW_CTRL_ERR_INT_EN);
val32 |= ((B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN &
DMAC_OTHER_STF_WROQT_UNDERFLOW_SER_EN) |
(B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN &
DMAC_OTHER_STF_WROQT_OVERFLOW_SER_EN) |
(B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN &
DMAC_OTHER_STF_WRFF_UNDERFLOW_SER_EN) |
(B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN &
DMAC_OTHER_STF_WRFF_OVERFLOW_SER_EN) |
(B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN &
DMAC_OTHER_STF_CMD_UNDERFLOW_SER_EN) |
(B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN &
DMAC_OTHER_STF_CMD_OVERFLOW_SER_EN) |
(B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN &
DMAC_HOST_ADDR_INFO_LEN_ZERO_ERR_SER_EN) |
(B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN &
DMAC_CPU_ADDR_INFO_LEN_ZERO_ERR_SER_EN) |
(B_AX_PLE_OUTPUT_ERR_INT_EN &
DMAC_PLE_OUTPUT_ERR_SER_EN) |
(B_AX_PLE_RESP_ERR_INT_EN &
DMAC_PLE_RESP_ERR_SER_EN) |
(B_AX_PLE_BURST_NUM_ERR_INT_EN &
DMAC_PLE_BURST_NUM_ERR_SER_EN) |
(B_AX_PLE_NULL_PKT_ERR_INT_EN &
DMAC_PLE_NULL_PKT_ERR_SER_EN) |
(B_AX_PLE_FLOW_CTRL_ERR_INT_EN &
DMAC_PLE_FLOW_CTRL_ERR_SER_EN) |
(B_AX_WDE_OUTPUT_ERR_INT_EN &
DMAC_WDE_OUTPUT_ERR_SER_EN) |
(B_AX_WDE_RESP_ERR_INT_EN &
DMAC_WDE_RESP_ERR_SER_EN) |
(B_AX_WDE_BURST_NUM_ERR_INT_EN &
DMAC_WDE_BURST_NUM_ERR_SER_EN) |
(B_AX_WDE_NULL_PKT_ERR_INT_EN &
DMAC_WDE_NULL_PKT_ERR_SER_EN) |
(B_AX_WDE_FLOW_CTRL_ERR_INT_EN &
DMAC_WDE_FLOW_CTRL_ERR_SER_EN));
MAC_REG_W32(R_AX_OTHER_DISPATCHER_ERR_IMR, val32);
return 0;
}
static u32 cpuio_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_CPUIO_ERR_IMR);
val32 &= ~(B_AX_WDEBUF_OP_ERR_INT_EN |
B_AX_WDEQUE_OP_ERR_INT_EN |
B_AX_PLEBUF_OP_ERR_INT_EN |
B_AX_PLEQUE_OP_ERR_INT_EN);
val32 |= ((B_AX_WDEBUF_OP_ERR_INT_EN &
DMAC_WDEBUF_OP_ERR_SER_EN) |
(B_AX_WDEQUE_OP_ERR_INT_EN &
DMAC_WDEQUE_OP_ERR_SER_EN) |
(B_AX_PLEBUF_OP_ERR_INT_EN &
DMAC_PLEBUF_OP_ERR_SER_EN) |
(B_AX_PLEQUE_OP_ERR_INT_EN &
DMAC_PLEQUE_OP_ERR_SER_EN));
MAC_REG_W32(R_AX_CPUIO_ERR_IMR, val32);
return 0;
}
static u32 bbrpt_imr_enable(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR);
val32 &= ~(B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN);
val32 |= ((B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN &
DMAC_BBRPT_COM_NULL_PLPKTID_ERR_SER_EN));
MAC_REG_W32(R_AX_BBRPT_COM_ERR_IMR_ISR, val32);
val32 = MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_IMR_ISR);
val32 &= ~(B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN |
B_AX_BBPRT_CHIF_OVF_ERR_INT_EN |
B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN |
B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN |
B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN |
B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN |
B_AX_BBPRT_CHIF_NULL_ERR_INT_EN |
B_AX_BBPRT_CHIF_TO_ERR_INT_EN);
val32 |= ((B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN &
DMAC_BBPRT_CHIF_BB_TO_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_OVF_ERR_INT_EN &
DMAC_BBPRT_CHIF_OVF_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN &
DMAC_BBPRT_CHIF_BOVF_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN &
DMAC_BBPRT_CHIF_HDRL_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN &
DMAC_BBPRT_CHIF_LEFT1_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN &
DMAC_BBPRT_CHIF_LEFT2_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_NULL_ERR_INT_EN &
DMAC_BBPRT_CHIF_NULL_ERR_SER_EN) |
(B_AX_BBPRT_CHIF_TO_ERR_INT_EN &
DMAC_BBPRT_CHIF_TO_ERR_SER_EN));
MAC_REG_W32(R_AX_BBRPT_CHINFO_ERR_IMR_ISR, val32);
val32 = MAC_REG_R32(R_AX_BBRPT_DFS_ERR_IMR_ISR);
val32 &= ~(B_AX_BBRPT_DFS_TO_ERR_INT_EN);
val32 |= ((B_AX_BBRPT_DFS_TO_ERR_INT_EN &
DMAC_BBRPT_DFS_TO_ERR_SER_EN));
MAC_REG_W32(R_AX_BBRPT_DFS_ERR_IMR_ISR, val32);
val32 = MAC_REG_R32(R_AX_LA_ERRFLAG);
val32 &= ~(B_AX_LA_IMR_DATA_LOSS_ERR);
val32 |= ((B_AX_LA_IMR_DATA_LOSS_ERR &
DMAC_LA_IMR_DATA_LOSS_ERR));
MAC_REG_W32(R_AX_LA_ERRFLAG, val32);
return 0;
}
static u32 sta_sch_init(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
u32 cnt, ret, val32;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val8 = MAC_REG_R8(R_AX_SS_CTRL);
val8 |= B_AX_SS_EN;
MAC_REG_W8(R_AX_SS_CTRL, val8);
cnt = TRXCFG_WAIT_CNT;
while (cnt--) {
if (MAC_REG_R32(R_AX_SS_CTRL) & B_AX_SS_INIT_DONE_1)
break;
PLTFM_DELAY_US(TRXCFG_WAIT_US);
}
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]STA scheduler init\n");
return MACPOLLTO;
}
MAC_REG_W32(R_AX_SS_CTRL,
MAC_REG_R32(R_AX_SS_CTRL) | B_AX_SS_WARM_INIT_FLG);
val32 = MAC_REG_R32(R_AX_SS_CTRL);
if (info->trx_mode == MAC_AX_TRX_SW_MODE)
val32 |= B_AX_SS_NONEMPTY_SS2FINFO_EN;
else
val32 &= ~B_AX_SS_NONEMPTY_SS2FINFO_EN;
MAC_REG_W32(R_AX_SS_CTRL, val32);
return MACSUCCESS;
}
static u32 scheduler_init(struct mac_ax_adapter *adapter, u8 band)
{
u32 reg, val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_edca_param edca_para;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_1_C1 : R_AX_PREBKF_CFG_1;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, SIFS_MACTXEN_T1, B_AX_SIFS_MACTXEN_T1);
MAC_REG_W32(reg, val32);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
reg = band == MAC_AX_BAND_1 ?
R_AX_SCH_EXT_CTRL_C1 : R_AX_SCH_EXT_CTRL;
val32 = MAC_REG_R32(reg) | B_AX_PORT_RST_TSF_ADV;
MAC_REG_W32(reg, val32);
}
#if MAC_AX_ASIC_TEMP
reg = band == MAC_AX_BAND_1 ? R_AX_CCA_CFG_0_C1 : R_AX_CCA_CFG_0;
val32 = MAC_REG_R32(reg) & ~(B_AX_BTCCA_EN);
MAC_REG_W32(reg, val32);
#endif
#ifdef PHL_FEATURE_AP
reg = band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_0_C1 : R_AX_PREBKF_CFG_0;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, SCH_PREBKF_16US, B_AX_PREBKF_TIME);
MAC_REG_W32(reg, val32);
reg = band == MAC_AX_BAND_1 ?
R_AX_CCA_CFG_0_C1 : R_AX_CCA_CFG_0;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, 0x6a, B_AX_R_SIFS_AGGR_TIME);
MAC_REG_W32(reg, val32);
#else /*for NIC mode setting*/
reg = band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_0_C1 : R_AX_PREBKF_CFG_0;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, SCH_PREBKF_24US, B_AX_PREBKF_TIME);
MAC_REG_W32(reg, val32);
#endif
edca_para.band = band;
edca_para.path = MAC_AX_CMAC_PATH_SEL_BCN;
edca_para.ecw_min = 0;
edca_para.ecw_max = 1;
edca_para.aifs_us = BCN_IFS_25US;
ret = set_hw_edca_param(adapter, &edca_para);
return ret;
}
static u32 mpdu_proc_init(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS)
return ret;
MAC_REG_W32(R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
MAC_REG_W32(R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
val32 = MAC_REG_R32(R_AX_MPDU_PROC);
val32 |= (B_AX_APPEND_FCS | B_AX_A_ICV_ERR);
MAC_REG_W32(R_AX_MPDU_PROC, val32);
MAC_REG_W32(R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
return MACSUCCESS;
}
static u32 sec_eng_init(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32 = 0;
u32 ret;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL);
// init clock
val32 |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
// init TX encryption
val32 |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
val32 |= (B_AX_MC_DEC | B_AX_BC_DEC);
val32 |= (B_AX_BMC_MGNT_DEC | B_AX_UC_MGNT_DEC);
val32 &= ~B_AX_TX_PARTIAL_MODE;
MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32);
//init MIC ICV append
val32 = MAC_REG_R32(R_AX_SEC_MPDU_PROC);
val32 |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC);
// option init
MAC_REG_W32(R_AX_SEC_MPDU_PROC, val32);
return MACSUCCESS;
}
static u32 tmac_init(struct mac_ax_adapter *adapter, u8 band,
struct mac_ax_trx_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg, val32, ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ? R_AX_MAC_LOOPBACK_C1 : R_AX_MAC_LOOPBACK;
val32 = MAC_REG_R32(reg);
if (info->trx_mode == MAC_AX_TRX_LOOPBACK)
val32 |= B_AX_MACLBK_EN;
else
val32 &= ~B_AX_MACLBK_EN;
MAC_REG_W32(reg, val32);
#if MAC_AX_FPGA_TEST
reg = band == MAC_AX_BAND_1 ? R_AX_MAC_LOOPBACK_C1 : R_AX_MAC_LOOPBACK;
val32 = MAC_REG_R32(reg);
if (info->trx_mode == MAC_AX_TRX_LOOPBACK)
val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_FPGA,
B_AX_MACLBK_PLCP_DLY);
else
val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_DEF,
B_AX_MACLBK_PLCP_DLY);
MAC_REG_W32(reg, val32);
#endif
return MACSUCCESS;
}
static u32 trxptcl_init(struct mac_ax_adapter *adapter, u8 band,
struct mac_ax_trx_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg, val32, ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ?
R_AX_TRXPTCL_RESP_0_C1 : R_AX_TRXPTCL_RESP_0;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_CCK,
B_AX_WMAC_SPEC_SIFS_CCK);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52A,
B_AX_WMAC_SPEC_SIFS_OFDM);
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52B,
B_AX_WMAC_SPEC_SIFS_OFDM);
else
val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52C,
B_AX_WMAC_SPEC_SIFS_OFDM);
MAC_REG_W32(reg, val32);
reg = band == MAC_AX_BAND_1 ?
R_AX_RXTRIG_TEST_USER_2_C1 : R_AX_RXTRIG_TEST_USER_2;
val32 = MAC_REG_R32(reg);
val32 |= B_AX_RXTRIG_FCSCHK_EN;
MAC_REG_W32(reg, val32);
return MACSUCCESS;
}
static u32 rmac_init(struct mac_ax_adapter *adapter, u8 band,
struct mac_ax_trx_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct rst_bacam_info rst_info;
u32 ret;
u8 val8;
u16 val16;
u32 val32, rx_max_len, rx_max_pg, reg;
u32 rx_min_qta, rx_max_lenb;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (band == MAC_AX_BAND_0) {
rst_info.type = BACAM_RST_ALL;
rst_info.ent = 0;
ret = rst_bacam(adapter, &rst_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]bacam rst %d\n", ret);
return ret;
}
}
reg = band == MAC_AX_BAND_1 ?
R_AX_RESPBA_CAM_CTRL_C1 : R_AX_RESPBA_CAM_CTRL;
val8 = MAC_REG_R8(reg) | B_AX_SSN_SEL;
MAC_REG_W8(reg, val8);
reg = band == MAC_AX_BAND_1 ?
R_AX_DLK_PROTECT_CTL_C1 : R_AX_DLK_PROTECT_CTL;
val16 = MAC_REG_R16(reg);
val16 = SET_CLR_WORD(val16, TRXCFG_RMAC_DATA_TO,
B_AX_RX_DLK_DATA_TIME);
val16 = SET_CLR_WORD(val16, TRXCFG_RMAC_CCA_TO,
B_AX_RX_DLK_CCA_TIME);
val16 |= B_AX_RX_DLK_RST_EN;
MAC_REG_W16(reg, val16);
reg = band == MAC_AX_BAND_1 ? R_AX_RCR_C1 : R_AX_RCR;
val8 = MAC_REG_R8(reg);
if (band == MAC_AX_BAND_0 && info->trx_mode == MAC_AX_TRX_SW_MODE)
val8 = SET_CLR_WORD(val8, 0xF, B_AX_CH_EN);
else
val8 = SET_CLR_WORD(val8, 0x1, B_AX_CH_EN);
MAC_REG_W8(reg, val8);
rx_min_qta = band == MAC_AX_BAND_1 ?
adapter->dle_info.c1_rx_qta : adapter->dle_info.c0_rx_qta;
rx_max_pg = rx_min_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_min_qta;
rx_max_lenb = rx_max_pg * adapter->dle_info.ple_pg_size;
if (rx_max_lenb < RX_SPEC_MAX_LEN)
PLTFM_MSG_ERR("[ERR]B%dRX max len %d illegal\n",
band, rx_max_lenb);
else
rx_max_lenb = RX_SPEC_MAX_LEN;
/* rx_max_len shall not be larger than B_AX_RX_MPDU_MAX_LEN_MSK */
rx_max_len = rx_max_lenb / RX_MAX_LEN_UNIT;
reg = band == MAC_AX_BAND_1 ? R_AX_RX_FLTR_OPT_C1 : R_AX_RX_FLTR_OPT;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, rx_max_len, B_AX_RX_MPDU_MAX_LEN);
MAC_REG_W32(reg, val32);
if (is_cv(adapter, CBV) &&
is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
reg = band == MAC_AX_BAND_1 ?
R_AX_DLK_PROTECT_CTL_C1 : R_AX_DLK_PROTECT_CTL;
val16 = MAC_REG_R16(reg);
val16 = SET_CLR_WORD(val16, 0x0, B_AX_RX_DLK_CCA_TIME);
MAC_REG_W16(reg, val16);
reg = band == MAC_AX_BAND_1 ? R_AX_RCR_C1 : R_AX_RCR;
val16 = MAC_REG_R16(reg);
MAC_REG_W16(reg, val16 | BIT12);
} else {
//cut_ver_checker
}
/* Add drv_info dbg size as dummy (SDIO) */
if (adapter->hw_info->intf == MAC_AX_INTF_SDIO &&
adapter->hw_info->chip_id == MAC_AX_CHIP_ID_8852A) {
val16 = MAC_REG_R16(R_AX_RCR);
MAC_REG_W16(R_AX_RCR, val16 |
SET_WORD(SDIO_DRV_INFO_SIZE, B_AX_DRV_INFO_SIZE));
}
/* NOT ALL vendors calculate VHT SIG-B's CRC */
reg = band == MAC_AX_BAND_1 ?
R_AX_PLCP_HDR_FLTR_C1 : R_AX_PLCP_HDR_FLTR;
val8 = MAC_REG_R8(reg) & ~B_AX_VHT_SU_SIGB_CRC_CHK;
MAC_REG_W8(reg, val8);
return MACSUCCESS;
}
static u32 cmac_com_init(struct mac_ax_adapter *adapter, u8 band,
struct mac_ax_trx_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
u32 ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ?
R_AX_TX_SUB_CARRIER_VALUE_C1 : R_AX_TX_SUB_CARRIER_VALUE;
val32 = MAC_REG_R32(reg);
if (info->trx_mode == MAC_AX_TRX_LOOPBACK) {
val32 = SET_CLR_WORD(val32, S_AX_TXSC_20M_4, B_AX_TXSC_20M);
val32 = SET_CLR_WORD(val32, S_AX_TXSC_40M_4, B_AX_TXSC_40M);
val32 = SET_CLR_WORD(val32, S_AX_TXSC_80M_4, B_AX_TXSC_80M);
} else {
val32 = SET_CLR_WORD(val32, S_AX_TXSC_20M_0, B_AX_TXSC_20M);
val32 = SET_CLR_WORD(val32, S_AX_TXSC_40M_0, B_AX_TXSC_40M);
val32 = SET_CLR_WORD(val32, S_AX_TXSC_80M_0, B_AX_TXSC_80M);
}
MAC_REG_W32(reg, val32);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
reg = band == MAC_AX_BAND_1 ?
R_AX_PTCL_RRSR1_C1 : R_AX_PTCL_RRSR1;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, RRSR_OFDM_CCK_EN,
B_AX_RRSR_RATE_EN);
MAC_REG_W32(reg, val32);
}
return MACSUCCESS;
}
static void _patch_vht_ampdu_max_len(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 reg;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
return;
reg = band == MAC_AX_BAND_1 ?
R_AX_AGG_LEN_VHT_0_C1 : R_AX_AGG_LEN_VHT_0;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, AMPDU_MAX_LEN_VHT_262K,
B_AX_AMPDU_MAX_LEN_VHT);
MAC_REG_W32(reg, val32);
}
static u32 ptcl_init(struct mac_ax_adapter *adapter, u8 band,
struct mac_ax_trx_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 val8;
u32 reg;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
ret = is_qta_poh(adapter, info->qta_mode, &val8);
if (ret)
return ret;
if (val8) {
reg = band == MAC_AX_BAND_1 ?
R_AX_SIFS_SETTING_C1 : R_AX_SIFS_SETTING;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, S_AX_CTS2S_TH_1K,
B_AX_HW_CTS2SELF_PKT_LEN_TH);
val32 = SET_CLR_WORD(val32, S_AX_CTS2S_TH_SEC_256B,
B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW);
val32 |= B_AX_HW_CTS2SELF_EN;
MAC_REG_W32(reg, val32);
reg = band == MAC_AX_BAND_1 ?
R_AX_PTCL_FSM_MON_C1 : R_AX_PTCL_FSM_MON;
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, S_AX_PTCL_TO_2MS,
B_AX_PTCL_TX_ARB_TO_THR);
val32 &= ~B_AX_PTCL_TX_ARB_TO_MODE;
MAC_REG_W32(reg, val32);
}
}
if (band == MAC_AX_BAND_0) {
val8 = MAC_REG_R8(R_AX_PTCL_COMMON_SETTING_0);
if (info->trx_mode == MAC_AX_TRX_SW_MODE) {
val8 &= ~(B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1);
val8 |= B_AX_PTCL_TRIGGER_SS_EN_0 |
B_AX_PTCL_TRIGGER_SS_EN_1 |
B_AX_PTCL_TRIGGER_SS_EN_UL;
} else {
val8 |= B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1;
val8 &= ~(B_AX_PTCL_TRIGGER_SS_EN_0 |
B_AX_PTCL_TRIGGER_SS_EN_1 |
B_AX_PTCL_TRIGGER_SS_EN_UL);
}
MAC_REG_W8(R_AX_PTCL_COMMON_SETTING_0, val8);
val8 = MAC_REG_R8(R_AX_PTCLRPT_FULL_HDL);
val8 = SET_CLR_WORD(val8, FWD_TO_WLCPU, B_AX_SPE_RPT_PATH);
MAC_REG_W8(R_AX_PTCLRPT_FULL_HDL, val8);
} else if (band == MAC_AX_BAND_1) {
val8 = MAC_REG_R8(R_AX_PTCLRPT_FULL_HDL_C1);
val8 = SET_CLR_WORD(val8, FWD_TO_WLCPU, B_AX_SPE_RPT_PATH);
MAC_REG_W8(R_AX_PTCLRPT_FULL_HDL_C1, val8);
}
_patch_vht_ampdu_max_len(adapter, band);
return MACSUCCESS;
}
static u32 cmac_dma_init(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg_rx_ctrl;
u32 ret;
u8 val8, rx_full_mode;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
rx_full_mode = B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE |
B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE |
B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE;
reg_rx_ctrl = (band == MAC_AX_BAND_1) ?
R_AX_RXDMA_CTRL_0_C1 : R_AX_RXDMA_CTRL_0;
val8 = MAC_REG_R8(reg_rx_ctrl) & ~rx_full_mode;
MAC_REG_W8(reg_rx_ctrl, val8);
} else {
return MACSUCCESS;
}
return MACSUCCESS;
}
static void _patch_dis_resp_chk(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg, val32;
u32 b_rsp_chk_nav, b_rsp_chk_cca;
b_rsp_chk_nav = B_AX_RSP_CHK_TX_NAV | B_AX_RSP_CHK_INTRA_NAV |
B_AX_RSP_CHK_BASIC_NAV;
b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 |
B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA |
B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
reg = band == MAC_AX_BAND_1 ?
R_AX_RSP_CHK_SIG_C1 : R_AX_RSP_CHK_SIG;
val32 = MAC_REG_R32(reg) & ~b_rsp_chk_nav;
MAC_REG_W32(reg, val32);
reg = band == MAC_AX_BAND_1 ?
R_AX_TRXPTCL_RESP_0_C1 : R_AX_TRXPTCL_RESP_0;
val32 = MAC_REG_R32(reg) & ~b_rsp_chk_cca;
MAC_REG_W32(reg, val32);
} else {
reg = band == MAC_AX_BAND_1 ?
R_AX_RSP_CHK_SIG_C1 : R_AX_RSP_CHK_SIG;
val32 = MAC_REG_R32(reg) | b_rsp_chk_nav;
MAC_REG_W32(reg, val32);
reg = band == MAC_AX_BAND_1 ?
R_AX_TRXPTCL_RESP_0_C1 : R_AX_TRXPTCL_RESP_0;
val32 = MAC_REG_R32(reg) | b_rsp_chk_cca;
MAC_REG_W32(reg, val32);
}
}
static u32 cca_ctrl_init(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
u32 ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ? R_AX_CCA_CONTROL_C1 : R_AX_CCA_CONTROL;
val32 = MAC_REG_R32(reg);
val32 |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 |
B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 |
B_AX_CTN_CHK_INTRA_NAV |
B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
B_AX_CTN_CHK_CCA_P20);
val32 &= (~B_AX_TB_CHK_TX_NAV & ~B_AX_TB_CHK_CCA_S80 &
~B_AX_TB_CHK_CCA_S40 & ~B_AX_TB_CHK_CCA_S20 &
~B_AX_SIFS_CHK_CCA_S80 & ~B_AX_SIFS_CHK_CCA_S40 &
~B_AX_SIFS_CHK_CCA_S20 & ~B_AX_SIFS_CHK_EDCCA &
~B_AX_CTN_CHK_TXNAV);
MAC_REG_W32(reg, val32);
_patch_dis_resp_chk(adapter, band);
return MACSUCCESS;
}
u32 mac_sifs_chk_cca_en(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
u32 ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ? R_AX_CCA_CONTROL_C1 : R_AX_CCA_CONTROL;
val32 = MAC_REG_R32(reg);
val32 |= (B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
B_AX_SIFS_CHK_CCA_S20 | B_AX_SIFS_CHK_EDCCA);
MAC_REG_W32(reg, val32);
return MACSUCCESS;
}
static u32 nav_ctrl_init(struct mac_ax_adapter *adapter, u8 band)
{
struct mac_ax_2nav_info info;
u32 ret;
info.plcp_upd_nav_en = 1;
info.tgr_fram_upd_nav_en = 1;
info.nav_up = NAV_12MS;
ret = mac_two_nav_cfg(adapter, &info);
return MACSUCCESS;
}
u32 dmac_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info,
enum mac_ax_band band)
{
u32 ret = 0;
ret = dle_init(adapter, info->qta_mode, MAC_AX_QTA_INVALID);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]DLE init %d\n", ret);
return ret;
}
ret = hfc_init(adapter, 1, 1, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]HCI FC init %d\n", ret);
return ret;
}
ret = sta_sch_init(adapter, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]STA SCH init %d\n", ret);
return ret;
}
ret = mpdu_proc_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]MPDU Proc init %d\n", ret);
return ret;
}
ret = sec_eng_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]Security Engine init %d\n", ret);
return ret;
}
return ret;
}
u32 cmac_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info,
enum mac_ax_band band)
{
u32 ret;
ret = scheduler_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d SCH init %d\n", band, ret);
return ret;
}
ret = rst_port_info(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d rst port info %d\n", band, ret);
return ret;
}
ret = addr_cam_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d ADDR_CAM reset %d\n", band, ret);
return ret;
}
ret = rx_fltr_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d RX filter init %d\n", band, ret);
return ret;
}
ret = cca_ctrl_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d CCA CTRL init %d\n", band, ret);
return ret;
}
ret = nav_ctrl_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d NAV CTRL init %d\n", band, ret);
return ret;
}
ret = spatial_reuse_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d Spatial Reuse init %d\n", band, ret);
return ret;
}
ret = tmac_init(adapter, band, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d TMAC init %d\n", band, ret);
return ret;
}
ret = trxptcl_init(adapter, band, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d TRXPTCL init %d\n", band, ret);
return ret;
}
ret = rmac_init(adapter, band, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d RMAC init %d\n", band, ret);
return ret;
}
ret = cmac_com_init(adapter, band, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d Com init %d\n", band, ret);
return ret;
}
ret = ptcl_init(adapter, band, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d PTCL init %d\n", band, ret);
return ret;
}
ret = cmac_dma_init(adapter, band);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d DMA init %d\n", band, ret);
return ret;
}
return ret;
}
static u32 band1_enable(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info)
{
u32 ret;
u32 sleep_bak[4] = {0};
u32 pause_bak[4] = {0};
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_sch_tx_en_cfg txen_bak;
txen_bak.band = 0;
ret = stop_sch_tx(adapter, SCH_TX_SEL_ALL, &txen_bak);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]stop sch tx %d\n", ret);
return ret;
}
sleep_bak[0] = MAC_REG_R32(R_AX_MACID_SLEEP_0);
sleep_bak[1] = MAC_REG_R32(R_AX_MACID_SLEEP_1);
sleep_bak[2] = MAC_REG_R32(R_AX_MACID_SLEEP_2);
sleep_bak[3] = MAC_REG_R32(R_AX_MACID_SLEEP_3);
pause_bak[0] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0);
pause_bak[1] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1);
pause_bak[2] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2);
pause_bak[3] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3);
MAC_REG_W32(R_AX_MACID_SLEEP_0, 0xFFFFFFFF);
MAC_REG_W32(R_AX_MACID_SLEEP_1, 0xFFFFFFFF);
MAC_REG_W32(R_AX_MACID_SLEEP_2, 0xFFFFFFFF);
MAC_REG_W32(R_AX_MACID_SLEEP_3, 0xFFFFFFFF);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, 0xFFFFFFFF);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, 0xFFFFFFFF);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, 0xFFFFFFFF);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, 0xFFFFFFFF);
ret = tx_idle_poll_band(adapter, 0, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]tx idle poll %d\n", ret);
return ret;
}
ret = dle_quota_change(adapter, info->qta_mode);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]DLE quota change %d\n", ret);
return ret;
}
MAC_REG_W32(R_AX_MACID_SLEEP_0, sleep_bak[0]);
MAC_REG_W32(R_AX_MACID_SLEEP_1, sleep_bak[1]);
MAC_REG_W32(R_AX_MACID_SLEEP_2, sleep_bak[2]);
MAC_REG_W32(R_AX_MACID_SLEEP_3, sleep_bak[3]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, pause_bak[0]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, pause_bak[1]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, pause_bak[2]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, pause_bak[3]);
ret = resume_sch_tx(adapter, &txen_bak);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d resume sch tx %d\n",
txen_bak.band, ret);
return ret;
}
ret = cmac_func_en(adapter, MAC_AX_BAND_1, MAC_AX_FUNC_EN);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d func en %d\n", MAC_AX_BAND_1, ret);
return ret;
}
ret = cmac_init(adapter, info, MAC_AX_BAND_1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d init %d\n", MAC_AX_BAND_1, ret);
return ret;
}
MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND,
MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) |
(B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1));
adapter->sm.bb1_func = MAC_AX_FUNC_ON;
ret = mac_enable_imr(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] enable CMAC1 IMR %d\n", ret);
return ret;
}
return MACSUCCESS;
}
static u32 band1_disable(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info)
{
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_pkt_drop_info drop_info;
MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND,
MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) &
~B_AX_R_SYM_FEN_WLBBFUN_1);
drop_info.band = MAC_AX_BAND_1;
drop_info.sel = MAC_AX_PKT_DROP_SEL_BAND;
ret = adapter->ops->pkt_drop(adapter, &drop_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d pkt drop %d\n", drop_info.band, ret);
return ret;
}
ret = mac_remove_role_by_band(adapter, MAC_AX_BAND_1, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]Remove Address CAM %d\n", ret);
return ret;
}
ret = cmac_func_en(adapter, MAC_AX_BAND_1, MAC_AX_FUNC_DIS);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d func dis %d\n", MAC_AX_BAND_1, ret);
return ret;
}
ret = dle_quota_change(adapter, info->qta_mode);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]DLE quota change %d\n", ret);
return ret;
}
return 0;
}
u32 mac_check_access(struct mac_ax_adapter *adapter, u32 offset)
{
if (offset >= CMAC1_START_ADDR && offset <= CMAC1_END_ADDR) {
if (adapter->dle_info.qta_mode == MAC_AX_QTA_SCC)
return MACHWNOTEN;
else if (adapter->dle_info.qta_mode == MAC_AX_QTA_SCC_STF)
return MACHWNOTEN;
else
return MACSUCCESS;
} else {
return MACSUCCESS;
}
}
u32 mac_enable_imr(struct mac_ax_adapter *adapter, u8 band,
enum mac_ax_hwmod_sel sel)
{
u32 ret;
ret = check_mac_en(adapter, band, sel);
if (ret) {
PLTFM_MSG_ERR("MAC%d band%d is not ready\n", sel, band);
return ret;
}
if (sel == MAC_AX_DMAC_SEL) {
ret = wdrls_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]wdrls_imr_enable %d\n", ret);
return ret;
}
ret = wsec_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]wsec_imr_enable %d\n", ret);
return ret;
}
ret = mpdu_trx_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]mpdu_trx_imr_enable %d\n", ret);
return ret;
}
ret = sta_sch_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]sta_sch_imr_enable %d\n", ret);
return ret;
}
ret = txpktctl_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]txpktctl_imr_enable %d\n", ret);
return ret;
}
ret = wde_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]wde_imr_enable %d\n", ret);
return ret;
}
ret = ple_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]ple_imr_enable %d\n", ret);
return ret;
}
ret = pktin_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]pktin_imr_enable %d\n", ret);
return ret;
}
ret = dispatcher_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]dispatcher_imr_enable %d\n", ret);
return ret;
}
ret = cpuio_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]cpuio_imr_enable %d\n", ret);
return ret;
}
ret = bbrpt_imr_enable(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]bbrpt_imr_enable %d\n", ret);
return ret;
}
} else if (sel == MAC_AX_CMAC_SEL) {
ret = scheduler_imr_enable(adapter, band);
if (ret) {
PLTFM_MSG_ERR("[ERR]scheduler_imr_enable %d\n", ret);
return ret;
}
ret = ptcl_imr_enable(adapter, band);
if (ret) {
PLTFM_MSG_ERR("[ERR]ptcl_imr_enable %d\n", ret);
return ret;
}
ret = cdma_imr_enable(adapter, band);
if (ret) {
PLTFM_MSG_ERR("[ERR]cdma_imr_enable %d\n", ret);
return ret;
}
ret = phy_intf_imr_enable(adapter, band);
if (ret) {
PLTFM_MSG_ERR("[ERR]phy_intf_imr_enable %d\n", ret);
return ret;
}
ret = rmac_imr_enable(adapter, band);
if (ret) {
PLTFM_MSG_ERR("[ERR]rmac_imr_enable %d\n", ret);
return ret;
}
ret = tmac_imr_enable(adapter, band);
if (ret) {
PLTFM_MSG_ERR("[ERR]tmac_imr_enable %d\n", ret);
return ret;
}
} else {
PLTFM_MSG_ERR("illegal sel %d\n", sel);
return MACNOITEM;
}
return MACSUCCESS;
}
#if MAC_AX_COEX_INIT_EN
static u32 coex_mac_init(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val;
u32 ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
ret = mac_write_lte(adapter, R_AX_LTECOEX_CTRL, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("Write LTE REG fail\n");
return ret;
}
ret = mac_write_lte(adapter, R_AX_LTECOEX_CTRL_2, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("Write LTE REG fail\n");
return ret;
}
val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3);
MAC_REG_W8(R_AX_SYS_SDIO_CTRL + 3, val | BIT(2));
} else {
MAC_REG_W32(R_AX_GNT_SW_CTRL, 0);
}
return MACSUCCESS;
}
#endif
u32 mac_trx_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info)
{
u32 ret = 0;
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
u8 val8;
/* Check TRX status is idle later. */
ret = dmac_init(adapter, info, MAC_AX_BAND_0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]DMAC init %d\n", ret);
return ret;
}
ret = cmac_init(adapter, info, MAC_AX_BAND_0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC%d init %d\n", MAC_AX_BAND_0, ret);
return ret;
}
#if MAC_AX_COEX_INIT_EN
ret = coex_mac_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] update coex setting %d\n", ret);
return ret;
}
#endif
ret = is_qta_dbcc(adapter, info->qta_mode, &val8);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] is_qta_dbcc %d\n", ret);
return ret;
}
if (val8) {
ret = mac_ops->dbcc_enable(adapter, info, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dbcc_enable init %d\n", ret);
return ret;
}
}
ret = mac_enable_imr(adapter, MAC_AX_BAND_0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] enable DMAC IMR %d\n", ret);
return ret;
}
ret = mac_enable_imr(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] enable CMAC0 IMR %d\n", ret);
return ret;
}
ret = mac_err_imr_ctrl(adapter, MAC_AX_FUNC_EN);
if (ret) {
PLTFM_MSG_ERR("[ERR] enable err IMR %d\n", ret);
return ret;
}
ret = set_host_rpr(adapter, info->rpr_cfg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]set host rpr %d\n", ret);
return ret;
}
ret = set_l2_status(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s %d\n", __func__, ret);
return ret;
}
return MACSUCCESS;
}
u32 mac_dbcc_enable(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info, u8 dbcc_en)
{
u32 ret;
if (dbcc_en) {
ret = band1_enable(adapter, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] band1_enable %d\n", ret);
return ret;
}
ret = mac_notify_fw_dbcc(adapter, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: [ERR] notfify dbcc fail %d\n",
__func__, ret);
return ret;
}
} else {
ret = mac_notify_fw_dbcc(adapter, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: [ERR] notfify dbcc fail %d\n",
__func__, ret);
return ret;
}
ret = band1_disable(adapter, info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] band1_disable %d\n", ret);
return ret;
}
}
return MACSUCCESS;
}
u32 mac_tx_mode_sel(struct mac_ax_adapter *adapter,
struct mac_ax_mac_tx_mode_sel *mode_sel)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret;
ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32 = MAC_REG_R32(R_AX_SS_DL_RPT_CRTL);
val32 &= ~(B_AX_SS_TXOP_MODE_0 | B_AX_SS_TXOP_MODE_1 |
B_AX_SS_TXOP_MODE_2 | B_AX_SS_TXOP_MODE_3);
val32 |= (mode_sel->txop_rot_wmm0_en ? B_AX_SS_TXOP_MODE_0 : 0) |
(mode_sel->txop_rot_wmm1_en ? B_AX_SS_TXOP_MODE_1 : 0) |
(mode_sel->txop_rot_wmm2_en ? B_AX_SS_TXOP_MODE_2 : 0) |
(mode_sel->txop_rot_wmm3_en ? B_AX_SS_TXOP_MODE_3 : 0);
MAC_REG_W32(R_AX_SS_DL_RPT_CRTL, val32);
return MACSUCCESS;
}
u32 mac_two_nav_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_2nav_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32 = 0;
val32 = MAC_REG_R32(R_AX_WMAC_NAV_CTL);
val32 |= ((info->plcp_upd_nav_en == 1 ? 1 : 0) << 17) |
((info->tgr_fram_upd_nav_en == 1 ? 1 : 0) << 16) |
(info->nav_up << 8);
MAC_REG_W32(R_AX_WMAC_NAV_CTL, val32);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/trxcfg.c
|
C
|
agpl-3.0
| 61,087
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_TRXCFG_H_
#define _MAC_AX_TRXCFG_H_
#include "../type.h"
#include "hw.h"
#include "init.h"
#include "role.h"
#include "cmac_tx.h"
#include "rx_filter.h"
#include "dle.h"
#include "hci_fc.h"
#include "mport.h"
#include "spatial_reuse.h"
/*--------------------Define -------------------------------------------*/
#define TRXCFG_WAIT_CNT 2000
#define TRXCFG_WAIT_US 1
/* MPDU Processor Control */
#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
#define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0
/* RMAC timeout control */
#define TRXCFG_RMAC_CCA_TO 32
#define TRXCFG_RMAC_DATA_TO 15
#define S_AX_TXSC_20M_0 0
#define S_AX_TXSC_20M_4 4
#define S_AX_TXSC_40M_0 0
#define S_AX_TXSC_40M_4 4
#define S_AX_TXSC_80M_0 0
#define S_AX_TXSC_80M_4 4
#define RRSR_OFDM_CCK_EN 3
/* TRXPTCL SIFS TIME*/
#define WMAC_SPEC_SIFS_OFDM_52A 0x15
#define WMAC_SPEC_SIFS_OFDM_52B 0x11
#define WMAC_SPEC_SIFS_OFDM_52C 0x11
#define WMAC_SPEC_SIFS_CCK 0xA
/* SRAM fifo address */
#define CMAC_TBL_BASE_ADDR 0x18840000
#define CMAC1_START_ADDR 0xE000
#define CMAC1_END_ADDR 0xFFFF
#if MAC_AX_ASIC_TEMP
#define R_AX_LTECOEX_CTRL 0x38
#define R_AX_LTECOEX_CTRL_2 0x3C
#endif
#define S_AX_CTS2S_TH_1K 4
#define S_AX_CTS2S_TH_SEC_256B 1
#define S_AX_PTCL_TO_2MS 0x3F
#define LBK_PLCP_DLY_DEF 0x28
#define LBK_PLCP_DLY_FPGA 0x46
#define PLD_RLS_MAX_PG 127
#define RX_MAX_LEN_UNIT 512
/* if spec max len is not align to rx max len unit, add 1 unit */
#define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
#define SCH_PREBKF_24US 0x18
#define SCH_PREBKF_16US 0x10
#define BCN_IFS_25US 0x19
#define SIFS_MACTXEN_T1 0x47
#define SDIO_DRV_INFO_SIZE 2
#define DMA_MOD_PCIE_1B 0x0
#define DMA_MOD_PCIE_4B 0x1
#define DMA_MOD_USB 0x2
#define DMA_MOD_SDIO 0x3
#define NAV_12MS 0xBC // (12ms, unit: 64us)
#define FWD_TO_HOST 0
#define FWD_TO_WLCPU 1
#define FWD_TO_DATACPU 2
#define AMPDU_MAX_LEN_VHT_262K 0x3FF80
/*--------------------Define MACRO--------------------------------------*/
/*--------------------Define Enum---------------------------------------*/
/*--------------------Define Struct-------------------------------------*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_enable_imr
*
* @param *adapter
* @param band
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 mac_enable_imr(struct mac_ax_adapter *adapter, u8 band,
enum mac_ax_hwmod_sel sel);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief check_mac_en
*
* @param *adapter
* @param band
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 check_mac_en(struct mac_ax_adapter *adapter, u8 band,
enum mac_ax_hwmod_sel sel);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_check_access
*
* @param *adapter
* @param offset
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_access(struct mac_ax_adapter *adapter, u32 offset);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_trx_init
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_trx_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_dbcc_enable
*
* @param *adapter
* @param *info
* @param dbcc_en
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dbcc_enable(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info, u8 dbcc_en);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_tx_mode_sel
*
* @param *adapter
* @param *mode_sel
* @return Please Place Description here.
* @retval u32
*/
u32 mac_tx_mode_sel(struct mac_ax_adapter *adapter,
struct mac_ax_mac_tx_mode_sel *mode_sel);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_two_nav_cfg
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_two_nav_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_2nav_info *info);
/**
* @}
* @}
*//**
* @brief mac_sifs_chk_edcca_en
*
* @param *adapter
* @param *band
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sifs_chk_cca_en(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/trxcfg.h
|
C
|
agpl-3.0
| 5,299
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "twt.h"
u32 mac_twt_info_upd_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_twt_para *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_twtinfo_upd *hdr;
u32 ret = MACSUCCESS;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_twtinfo_upd *)
h2cb_put(h2cb, sizeof(struct fwcmd_twtinfo_upd));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
/* port 4 not support */
if (info->port >= MAC_AX_PORT_4) {
PLTFM_MSG_ERR("[ERR] twt info upd h2c port %d\n", info->port);
return MACFUNCINPUT;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(info->nego_tp,
FWCMD_H2C_TWTINFO_UPD_NEGOTYPE) |
SET_WORD(info->act, FWCMD_H2C_TWTINFO_UPD_ACT) |
(info->trig ? FWCMD_H2C_TWTINFO_UPD_TRIGGER : 0) |
(info->flow_tp ?
FWCMD_H2C_TWTINFO_UPD_FLOWTYPE : 0) |
(info->impt ? FWCMD_H2C_TWTINFO_UPD_IMPT : 0) |
(info->wake_unit ?
FWCMD_H2C_TWTINFO_UPD_WAKEDURUNIT : 0) |
(info->rsp_pm ? FWCMD_H2C_TWTINFO_UPD_RSPPM : 0) |
(info->proct ? FWCMD_H2C_TWTINFO_UPD_PROT : 0) |
SET_WORD(info->flow_id,
FWCMD_H2C_TWTINFO_UPD_FLOWID) |
SET_WORD(info->id, FWCMD_H2C_TWTINFO_UPD_ID) |
(info->band ? FWCMD_H2C_TWTINFO_UPD_BAND : 0) |
SET_WORD(info->port, FWCMD_H2C_TWTINFO_UPD_PORT));
hdr->dword1 =
cpu_to_le32(SET_WORD(info->wake_exp,
FWCMD_H2C_TWTINFO_UPD_WAKE_EXP) |
SET_WORD(info->wake_man,
FWCMD_H2C_TWTINFO_UPD_WAKE_MAN) |
SET_WORD(info->twtulfixmode,
FWCMD_H2C_TWTINFO_UPD_ULFIXMODE) |
SET_WORD(info->dur,
FWCMD_H2C_TWTINFO_UPD_DUR));
hdr->dword2 =
cpu_to_le32(SET_WORD(info->trgt_l,
FWCMD_H2C_TWTINFO_UPD_TGT_L));
hdr->dword3 =
cpu_to_le32(SET_WORD(info->trgt_h,
FWCMD_H2C_TWTINFO_UPD_TGT_H));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_TWT,
FWCMD_H2C_FUNC_TWTINFO_UPD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_twt_act_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_twtact_para *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_twt_stansp_upd *hdr;
u32 ret = MACSUCCESS;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_twt_stansp_upd *)
h2cb_put(h2cb, sizeof(struct fwcmd_twt_stansp_upd));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(info->macid,
FWCMD_H2C_TWT_STANSP_UPD_MACID) |
SET_WORD(info->id,
FWCMD_H2C_TWT_STANSP_UPD_ID) |
SET_WORD(info->act,
FWCMD_H2C_TWT_STANSP_UPD_ACT));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_TWT,
FWCMD_H2C_FUNC_TWT_STANSP_UPD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_twt_staanno_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_twtanno_para *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_twt_announce_upd *hdr;
u32 ret = MACSUCCESS;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_twt_announce_upd *)h2cb_put(h2cb,
sizeof(struct fwcmd_twt_announce_upd));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_TWT_ANNOUNCE_UPD_MACID));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_TWT,
FWCMD_H2C_FUNC_TWT_ANNOUNCE_UPD,
1,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
void mac_twt_wait_anno(struct mac_ax_adapter *adapter,
u8 *c2h_content, u8 *upd_addr)
{
u32 plat_c2h_content = *(u32 *)(c2h_content);
struct mac_ax_twtanno_c2hpara *para =
(struct mac_ax_twtanno_c2hpara *)upd_addr;
para->wait_case = GET_FIELD(plat_c2h_content,
FWCMD_C2H_WAIT_ANNOUNCE_WAIT_CASE);
para->macid0 = GET_FIELD(plat_c2h_content,
FWCMD_C2H_WAIT_ANNOUNCE_MACID0);
para->macid1 = GET_FIELD(plat_c2h_content,
FWCMD_C2H_WAIT_ANNOUNCE_MACID1);
para->macid2 = GET_FIELD(plat_c2h_content,
FWCMD_C2H_WAIT_ANNOUNCE_MACID2);
}
void mac_get_tsf(struct mac_ax_adapter *adapter,
struct mac_ax_port_tsf *tsf)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg_l = 0;
u32 reg_h = 0;
switch (tsf->port) {
case 0:
reg_h = R_AX_TSFTR_HIGH_P0;
reg_l = R_AX_TSFTR_LOW_P0;
break;
case 1:
reg_h = R_AX_TSFTR_HIGH_P1;
reg_l = R_AX_TSFTR_LOW_P1;
break;
case 2:
reg_h = R_AX_TSFTR_HIGH_P2;
reg_l = R_AX_TSFTR_LOW_P2;
break;
case 3:
reg_h = R_AX_TSFTR_HIGH_P3;
reg_l = R_AX_TSFTR_LOW_P3;
break;
default:
reg_h = R_AX_TSFTR_HIGH_P0;
reg_l = R_AX_TSFTR_LOW_P0;
break;
}
tsf->tsf_h = MAC_REG_R32(reg_h);
tsf->tsf_l = MAC_REG_R32(reg_l);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/twt.c
|
C
|
agpl-3.0
| 6,602
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_TWT_H_
#define _MAC_AX_TWT_H_
#include "../type.h"
#include "fwcmd.h"
/**
* @addtogroup PowerSaving
* @{
* @addtogroup TWT
* @{
*/
/**
* @brief mac_twt_info_upd_h2c
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_twt_info_upd_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_twt_para *info);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup TWT
* @{
*/
/**
* @brief mac_twt_act_h2c
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_twt_act_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_twtact_para *info);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup TWT
* @{
*/
/**
* @brief mac_twt_staanno_h2c
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_twt_staanno_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_twtanno_para *info);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup TWT
* @{
*/
/**
* @brief mac_twt_wait_anno
*
* @param *adapter
* @param *c2h_content
* @param *upd_addr
* @return Please Place Description here.
* @retval void
*/
void mac_twt_wait_anno(struct mac_ax_adapter *adapter,
u8 *c2h_content, u8 *upd_addr);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup TWT
* @{
*/
/**
* @brief mac_get_tsf
*
* @param *adapter
* @param *tsf
* @return Please Place Description here.
* @retval void
*/
void mac_get_tsf(struct mac_ax_adapter *adapter,
struct mac_ax_port_tsf *tsf);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/twt.h
|
C
|
agpl-3.0
| 2,356
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "wowlan.h"
static u32 wow_bk_status[4] = {0};
static u32 tgt_ind_orig;
static u32 frm_tgt_ind_orig;
static u32 wol_pattern_orig;
static u32 wol_uc_orig;
static u32 wol_magic_orig;
static u32 send_h2c_keep_alive(struct mac_ax_adapter *adapter,
struct keep_alive *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_keep_alive *fwcmd_kalive;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_keep_alive));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_kalive = (struct fwcmd_keep_alive *)buf;
fwcmd_kalive->dword0 =
cpu_to_le32((parm->keepalive_en ?
FWCMD_H2C_KEEP_ALIVE_KEEPALIVE_EN : 0) |
SET_WORD(parm->packet_id, FWCMD_H2C_KEEP_ALIVE_PACKET_ID) |
SET_WORD(parm->period, FWCMD_H2C_KEEP_ALIVE_PERIOD) |
SET_WORD(parm->mac_id, FWCMD_H2C_KEEP_ALIVE_MAC_ID));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_KEEP_ALIVE,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_disconnect_detect(struct mac_ax_adapter *adapter,
struct disconnect_detect *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_disconnect_detect *fwcmd_disconnect_det;
u32 ret = 0;
u32 tmp;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_disconnect_detect));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_disconnect_det = (struct fwcmd_disconnect_detect *)buf;
fwcmd_disconnect_det->dword0 =
cpu_to_le32((parm->disconnect_detect_en ?
FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_DETECT_EN : 0) |
(parm->tryok_bcnfail_count_en ?
FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN : 0) |
(parm->disconnect_en ? FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_EN : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_DISCONNECT_DETECT_MAC_ID) |
SET_WORD(parm->check_period, FWCMD_H2C_DISCONNECT_DETECT_CHECK_PERIOD) |
SET_WORD(parm->try_pkt_count,
FWCMD_H2C_DISCONNECT_DETECT_TRY_PKT_COUNT));
tmp = SET_WORD(parm->tryok_bcnfail_count_limit,
FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT);
fwcmd_disconnect_det->dword1 = cpu_to_le32(tmp);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_DISCONNECT_DETECT,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_wow_global(struct mac_ax_adapter *adapter,
struct wow_global *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_wow_global *fwcmd_wow_glo;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_wow_global)
+ sizeof(struct mac_ax_remotectrl_info_parm_) - 4);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_wow_glo = (struct fwcmd_wow_global *)buf;
fwcmd_wow_glo->dword0 =
cpu_to_le32((parm->wow_en ? FWCMD_H2C_WOW_GLOBAL_WOW_EN : 0) |
(parm->drop_all_pkt ? FWCMD_H2C_WOW_GLOBAL_DROP_ALL_PKT : 0) |
(parm->rx_parse_after_wake ?
FWCMD_H2C_WOW_GLOBAL_RX_PARSE_AFTER_WAKE : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_WOW_GLOBAL_MAC_ID) |
SET_WORD(parm->pairwise_sec_algo,
FWCMD_H2C_WOW_GLOBAL_PAIRWISE_SEC_ALGO) |
SET_WORD(parm->group_sec_algo,
FWCMD_H2C_WOW_GLOBAL_GROUP_SEC_ALGO));
//fwcmd_wow_glo->dword1 =
// cpu_to_le32(parm->remotectrl_info_content);
PLTFM_MEMCPY(&fwcmd_wow_glo->dword1, &parm->remotectrl_info_content,
sizeof(struct mac_ax_remotectrl_info_parm_));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_WOW_GLOBAL,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_gtk_ofld(struct mac_ax_adapter *adapter,
struct gtk_ofld *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_gtk_ofld *fwcmd_gtk_ofl;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_gtk_ofld)
+ sizeof(struct mac_ax_gtk_info_parm_) - 4);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_gtk_ofl = (struct fwcmd_gtk_ofld *)buf;
fwcmd_gtk_ofl->dword0 =
cpu_to_le32((parm->gtk_en ? FWCMD_H2C_GTK_OFLD_GTK_EN : 0) |
(parm->tkip_en ? FWCMD_H2C_GTK_OFLD_TKIP_EN : 0) |
(parm->ieee80211w_en ? FWCMD_H2C_GTK_OFLD_IEEE80211W_EN : 0) |
(parm->pairwise_wakeup ?
FWCMD_H2C_GTK_OFLD_PAIRWISE_WAKEUP : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_GTK_OFLD_MAC_ID) |
SET_WORD(parm->gtk_rsp_id, FWCMD_H2C_GTK_OFLD_GTK_RSP_ID));
fwcmd_gtk_ofl->dword1 =
cpu_to_le32(SET_WORD(parm->pmf_sa_query_id, FWCMD_H2C_GTK_OFLD_PMF_SA_QUERY_ID) |
SET_WORD(parm->bip_sec_algo, FWCMD_H2C_GTK_OFLD_PMF_BIP_SEC_ALGO) |
SET_WORD(parm->algo_akm_suit, FWCMD_H2C_GTK_OFLD_ALGO_AKM_SUIT));
PLTFM_MEMCPY(&fwcmd_gtk_ofl->dword2, &parm->gtk_info_content,
sizeof(struct mac_ax_gtk_info_parm_));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_GTK_OFLD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_arp_ofld(struct mac_ax_adapter *adapter,
struct arp_ofld *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_arp_ofld *fwcmd_arp_ofl;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_arp_ofld));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_arp_ofl = (struct fwcmd_arp_ofld *)buf;
fwcmd_arp_ofl->dword0 =
cpu_to_le32((parm->arp_en ? FWCMD_H2C_ARP_OFLD_ARP_EN : 0) |
(parm->arp_action ? FWCMD_H2C_ARP_OFLD_ARP_ACTION : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_ARP_OFLD_MAC_ID) |
SET_WORD(parm->arp_rsp_id, FWCMD_H2C_ARP_OFLD_ARP_RSP_ID));
fwcmd_arp_ofl->dword1 =
cpu_to_le32(parm->arp_info_content);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_ARP_OFLD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_ndp_ofld(struct mac_ax_adapter *adapter,
struct ndp_ofld *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_ndp_ofld *fwcmd_ndp_ofl;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ndp_ofld) + 2 *
sizeof(struct mac_ax_ndp_info_parm_) - 4);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_ndp_ofl = (struct fwcmd_ndp_ofld *)buf;
fwcmd_ndp_ofl->dword0 =
cpu_to_le32((parm->ndp_en ? FWCMD_H2C_NDP_OFLD_NDP_EN : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_NDP_OFLD_MAC_ID) |
SET_WORD(parm->na_id, FWCMD_H2C_NDP_OFLD_NA_ID));
PLTFM_MEMCPY(&fwcmd_ndp_ofl->dword1, &parm->ndp_info_content, 2 *
sizeof(struct mac_ax_ndp_info_parm_));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_NDP_OFLD,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_realwow(struct mac_ax_adapter *adapter,
struct realwow *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_realwow *fwcmd_realw;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_realwow) +
sizeof(struct mac_ax_realwowv2_info_parm_) - 4);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_realw = (struct fwcmd_realwow *)buf;
fwcmd_realw->dword0 =
cpu_to_le32((parm->realwow_en ? FWCMD_H2C_REALWOW_REALWOW_EN : 0) |
(parm->auto_wakeup ? FWCMD_H2C_REALWOW_AUTO_WAKEUP : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_REALWOW_MAC_ID));
fwcmd_realw->dword1 =
cpu_to_le32(SET_WORD(parm->keepalive_id,
FWCMD_H2C_REALWOW_KEEPALIVE_ID) |
SET_WORD(parm->wakeup_pattern_id, FWCMD_H2C_REALWOW_WAKEUP_PATTERN_ID) |
SET_WORD(parm->ack_pattern_id, FWCMD_H2C_REALWOW_ACK_PATTERN_ID));
fwcmd_realw->dword2 =
cpu_to_le32(parm->realwow_info_content);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_REALWOW,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_nlo(struct mac_ax_adapter *adapter,
struct nlo *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_nlo *fwcmd_nl;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_nlo) +
sizeof(struct mac_ax_nlo_networklist_parm_) - 4);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_nl = (struct fwcmd_nlo *)buf;
fwcmd_nl->dword0 =
cpu_to_le32((parm->nlo_en ? FWCMD_H2C_NLO_NLO_EN : 0) |
(parm->nlo_32k_en ? FWCMD_H2C_NLO_NLO_32K_EN : 0) |
(parm->ignore_cipher_type ? FWCMD_H2C_NLO_IGNORE_CIPHER_TYPE : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_NLO_MAC_ID));
fwcmd_nl->dword1 =
cpu_to_le32(parm->nlo_networklistinfo_content);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_NLO,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_wakeup_ctrl(struct mac_ax_adapter *adapter,
struct wakeup_ctrl *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_wakeup_ctrl *fwcmd_wakeup_ctr;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_wakeup_ctrl));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_wakeup_ctr = (struct fwcmd_wakeup_ctrl *)buf;
fwcmd_wakeup_ctr->dword0 =
cpu_to_le32((parm->pattern_match_en ?
FWCMD_H2C_WAKEUP_CTRL_PATTERN_MATCH_EN : 0) |
(parm->magic_en ? FWCMD_H2C_WAKEUP_CTRL_MAGIC_EN : 0) |
(parm->hw_unicast_en ? FWCMD_H2C_WAKEUP_CTRL_HW_UNICAST_EN : 0) |
(parm->fw_unicast_en ? FWCMD_H2C_WAKEUP_CTRL_FW_UNICAST_EN : 0) |
(parm->deauth_wakeup ? FWCMD_H2C_WAKEUP_CTRL_DEAUTH_WAKEUP : 0) |
(parm->rekey_wakeup ? FWCMD_H2C_WAKEUP_CTRL_REKEY_WAKEUP : 0) |
(parm->eap_wakeup ? FWCMD_H2C_WAKEUP_CTRL_EAP_WAKEUP : 0) |
(parm->all_data_wakeup ? FWCMD_H2C_WAKEUP_CTRL_ALL_DATA_WAKEUP : 0) |
SET_WORD(parm->mac_id, FWCMD_H2C_WAKEUP_CTRL_MAC_ID));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_WAKEUP_CTRL,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_negative_pattern(struct mac_ax_adapter *adapter,
struct negative_pattern *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_negative_pattern *fwcmd_negative_patter;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_negative_pattern));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_negative_patter = (struct fwcmd_negative_pattern *)buf;
fwcmd_negative_patter->dword0 =
cpu_to_le32((parm->negative_pattern_en ?
FWCMD_H2C_NEGATIVE_PATTERN_NEGATIVE_PATTERN_EN : 0) |
SET_WORD(parm->pattern_count,
FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_COUNT) |
SET_WORD(parm->mac_id, FWCMD_H2C_NEGATIVE_PATTERN_MAC_ID));
fwcmd_negative_patter->dword1 =
cpu_to_le32(parm->pattern_content);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_NEGATIVE_PATTERN,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_cfg_dev2hst_gpio(struct mac_ax_adapter *adapter,
struct mac_ax_dev2hst_gpio_info *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_dev2hst_gpio *fwcmd_dev2hst_gpi;
u32 ret = 0;
if (parm->gpio_output_input == MAC_AX_DEV2HST_GPIO_INPUT &&
parm->toggle_pulse == MAC_AX_DEV2HST_PULSE) {
PLTFM_MSG_ERR("pulse mode not supported under input mode");
return MACNOITEM;
}
if (parm->gpio_num > MAC_AX_GPIO15) {
PLTFM_MSG_ERR("gpio num > 15");
return MACNOITEM;
}
if (parm->toggle_pulse == MAC_AX_DEV2HST_PULSE) {
if (parm->gpio_pulse_dura == 0) {
PLTFM_MSG_ERR("gpio pulse duration cant be 0");
return MACNOITEM;
}
if (parm->gpio_pulse_period <= parm->gpio_pulse_dura) {
PLTFM_MSG_ERR("gpio pulse period can less than duration");
return MACNOITEM;
}
if (!parm->gpio_pulse_nonstop && parm->gpio_pulse_count == 0) {
PLTFM_MSG_ERR("gpio pulse count cant be 0");
return MACNOITEM;
}
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_dev2hst_gpio));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_dev2hst_gpi = (struct fwcmd_dev2hst_gpio *)buf;
fwcmd_dev2hst_gpi->dword0 =
cpu_to_le32((parm->dev2hst_gpio_en ? FWCMD_H2C_DEV2HST_GPIO_DEV2HST_GPIO_EN : 0) |
(parm->disable_inband ? FWCMD_H2C_DEV2HST_GPIO_DISABLE_INBAND : 0) |
(parm->gpio_output_input ? FWCMD_H2C_DEV2HST_GPIO_GPIO_OUTPUT_INPUT : 0) |
(parm->gpio_active ? FWCMD_H2C_DEV2HST_GPIO_GPIO_ACTIVE : 0) |
(parm->toggle_pulse ? FWCMD_H2C_DEV2HST_GPIO_TOGGLE_PULSE : 0) |
(parm->data_pin_wakeup ? FWCMD_H2C_DEV2HST_GPIO_DATA_PIN_WAKEUP : 0) |
(parm->data_pin_wakeup ? FWCMD_H2C_DEV2HST_GPIO_DATA_PIN_WAKEUP : 0) |
(parm->gpio_pulse_nonstop ? FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_NONSTOP : 0) |
(parm->gpio_time_unit ? FWCMD_H2C_DEV2HST_GPIO_GPIO_TIME_UNIT : 0) |
SET_WORD(parm->gpio_num, FWCMD_H2C_DEV2HST_GPIO_GPIO_NUM) |
SET_WORD(parm->gpio_pulse_dura, FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_DURATION) |
SET_WORD(parm->gpio_pulse_period, FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_PERIOD));
fwcmd_dev2hst_gpi->dword1 =
cpu_to_le32(SET_WORD(parm->gpio_pulse_count,
FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_COUNT));
fwcmd_dev2hst_gpi->dword2 =
cpu_to_le32(SET_WORD(parm->customer_id,
FWCMD_H2C_DEV2HST_GPIO_CUSTOMER_ID));
fwcmd_dev2hst_gpi->dword3 =
cpu_to_le32((parm->rsn_a_en ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_EN : 0) |
(parm->rsn_a_toggle_pulse ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_TOGGLE_PULSE : 0) |
(parm->rsn_a_pulse_nonstop ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_NONSTOP : 0) |
(parm->rsn_a_time_unit ? FWCMD_H2C_DEV2HST_GPIO_RSN_A_TIME_UNIT : 0));
fwcmd_dev2hst_gpi->dword4 =
cpu_to_le32(SET_WORD(parm->rsn_a, FWCMD_H2C_DEV2HST_GPIO_RSN_A) |
SET_WORD(parm->rsn_a_pulse_duration,
FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_DURATION) |
SET_WORD(parm->rsn_a_pulse_period, FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_PERIOD) |
SET_WORD(parm->rsn_a_pulse_count, FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_COUNT));
fwcmd_dev2hst_gpi->dword5 =
cpu_to_le32((parm->rsn_b_en ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_EN : 0) |
(parm->rsn_b_toggle_pulse ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_TOGGLE_PULSE : 0) |
(parm->rsn_b_pulse_nonstop ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_NONSTOP : 0) |
(parm->rsn_b_time_unit ? FWCMD_H2C_DEV2HST_GPIO_RSN_B_TIME_UNIT : 0));
fwcmd_dev2hst_gpi->dword6 =
cpu_to_le32(SET_WORD(parm->rsn_b, FWCMD_H2C_DEV2HST_GPIO_RSN_B) |
SET_WORD(parm->rsn_b_pulse_duration,
FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_DURATION) |
SET_WORD(parm->rsn_b_pulse_period, FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_PERIOD) |
SET_WORD(parm->rsn_b_pulse_count, FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_COUNT));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_DEV2HST_GPIO,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
PLTFM_MSG_TRACE("ok");
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_uphy_ctrl(struct mac_ax_adapter *adapter,
struct uphy_ctrl *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_uphy_ctrl *fwcmd_uphy_ctr;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_uphy_ctrl));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_uphy_ctr = (struct fwcmd_uphy_ctrl *)buf;
fwcmd_uphy_ctr->dword0 =
cpu_to_le32((parm->disable_uphy ?
FWCMD_H2C_UPHY_CTRL_DISABLE_UPHY : 0) |
SET_WORD(parm->handshake_mode, FWCMD_H2C_UPHY_CTRL_HANDSHAKE_MODE) |
(parm->rise_hst2dev_dis_uphy ? FWCMD_H2C_UPHY_CTRL_RISE_HST2DEV_DIS_UPHY
: 0) |
(parm->uphy_dis_delay_unit ? FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_UNIT
: 0) |
(parm->pdn_as_uphy_dis ? FWCMD_H2C_UPHY_CTRL_PDN_AS_UPHY_DIS : 0) |
(parm->pdn_to_enable_uphy ? FWCMD_H2C_UPHY_CTRL_PDN_TO_ENABLE_UPHY
: 0) |
SET_WORD(parm->hst2dev_gpio_num, FWCMD_H2C_UPHY_CTRL_HST2DEV_GPIO_NUM) |
SET_WORD(parm->uphy_dis_delay_count,
FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_COUNT));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_UPHY_CTRL,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 send_h2c_wowcam_upd(struct mac_ax_adapter *adapter,
struct wowcam_upd *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_wow_cam_upd *fwcmd_wowcam_upd;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_wow_cam_upd));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_wowcam_upd = (struct fwcmd_wow_cam_upd *)buf;
fwcmd_wowcam_upd->dword0 =
cpu_to_le32((parm->r_w ? FWCMD_H2C_WOW_CAM_UPD_R_W : 0) |
SET_WORD(parm->idx, FWCMD_H2C_WOW_CAM_UPD_IDX));
fwcmd_wowcam_upd->dword1 =
cpu_to_le32(parm->wkfm1);
fwcmd_wowcam_upd->dword2 =
cpu_to_le32(parm->wkfm2);
fwcmd_wowcam_upd->dword3 =
cpu_to_le32(parm->wkfm3);
fwcmd_wowcam_upd->dword4 =
cpu_to_le32(parm->wkfm4);
fwcmd_wowcam_upd->dword5 =
cpu_to_le32(SET_WORD(parm->crc, FWCMD_H2C_WOW_CAM_UPD_CRC) |
(parm->negative_pattern_match ? FWCMD_H2C_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH : 0) |
(parm->skip_mac_hdr ? FWCMD_H2C_WOW_CAM_UPD_SKIP_MAC_HDR : 0) |
(parm->uc ? FWCMD_H2C_WOW_CAM_UPD_UC : 0) |
(parm->mc ? FWCMD_H2C_WOW_CAM_UPD_MC : 0) |
(parm->bc ? FWCMD_H2C_WOW_CAM_UPD_BC : 0) |
(parm->valid ? FWCMD_H2C_WOW_CAM_UPD_VALID : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW,
FWCMD_H2C_FUNC_WOW_CAM_UPD,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_cfg_wow_wake(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_wow_wake_info *info,
struct mac_ax_remotectrl_info_parm_ *content)
{
u32 ret = 0;
struct wow_global parm1;
struct wakeup_ctrl parm2;
struct mac_role_tbl *role;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
parm2.pattern_match_en = info->pattern_match_en;
parm2.magic_en = info->magic_en;
parm2.hw_unicast_en = info->hw_unicast_en;
parm2.fw_unicast_en = info->fw_unicast_en;
parm2.deauth_wakeup = info->deauth_wakeup;
parm2.rekey_wakeup = info->rekey_wakeup;
parm2.eap_wakeup = info->eap_wakeup;
parm2.all_data_wakeup = info->all_data_wakeup;
parm2.mac_id = macid;
ret = send_h2c_wakeup_ctrl(adapter, &parm2);
if (ret) {
PLTFM_MSG_ERR("send h2c wakeup ctrl failed\n");
return ret;
}
parm1.wow_en = info->wow_en;
parm1.drop_all_pkt = info->drop_all_pkt;
parm1.rx_parse_after_wake = info->rx_parse_after_wake;
parm1.mac_id = macid;
parm1.pairwise_sec_algo = info->pairwise_sec_algo;
parm1.group_sec_algo = info->group_sec_algo;
//parm1.remotectrl_info_content =
//info->remotectrl_info_content;
if (content)
PLTFM_MEMCPY(&parm1.remotectrl_info_content,
content,
sizeof(struct mac_ax_remotectrl_info_parm_));
if (info->wow_en) {
role = mac_role_srch(adapter, macid);
if (role) {
tgt_ind_orig = role->info.tgt_ind;
frm_tgt_ind_orig = role->info.frm_tgt_ind;
wol_pattern_orig = role->info.wol_pattern;
wol_uc_orig = role->info.wol_uc;
wol_magic_orig = role->info.wol_magic;
wow_bk_status[(macid >> 5)] |= BIT(macid & 0x1F);
role->info.wol_pattern = (u8)parm2.pattern_match_en;
role->info.wol_uc = info->hw_unicast_en;
role->info.wol_magic = info->magic_en;
ret = mac_change_role(adapter, &role->info);
if (ret) {
PLTFM_MSG_ERR("role change failed\n");
return ret;
}
} else {
PLTFM_MSG_ERR("role search failed\n");
return MACNOITEM;
}
} else {
if (wow_bk_status[(macid >> 5)] & BIT(macid & 0x1F)) {
//restore address cam
role = mac_role_srch(adapter, macid);
if (role) {
role->info.tgt_ind = (u8)tgt_ind_orig;
role->info.frm_tgt_ind = (u8)frm_tgt_ind_orig;
role->info.wol_pattern = (u8)wol_pattern_orig;
role->info.wol_uc = (u8)wol_uc_orig;
role->info.wol_magic = (u8)wol_magic_orig;
ret = mac_change_role(adapter, &role->info);
if (ret) {
PLTFM_MSG_ERR("role change failed\n");
return ret;
}
}
wow_bk_status[(macid >> 5)] &= ~BIT(macid & 0x1F);
} else {
PLTFM_MSG_ERR("role search failed\n");
return MACNOITEM;
}
}
ret = send_h2c_wow_global(adapter, &parm1);
if (ret)
PLTFM_MSG_ERR("set wow global failed\n");
return ret;
}
u32 mac_cfg_disconnect_det(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_disconnect_det_info *info)
{
u32 ret = 0;
struct disconnect_detect parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
parm.disconnect_detect_en = info->disconnect_detect_en;
parm.tryok_bcnfail_count_en =
info->tryok_bcnfail_count_en;
parm.disconnect_en = info->disconnect_en;
parm.mac_id = macid;
parm.check_period = info->check_period;
parm.try_pkt_count = info->try_pkt_count;
parm.tryok_bcnfail_count_limit =
info->tryok_bcnfail_count_limit;
ret = send_h2c_disconnect_detect(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_keep_alive(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_keep_alive_info *info)
{
u32 ret = 0;
struct keep_alive parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
parm.keepalive_en = info->keepalive_en;
parm.packet_id = info->packet_id;
parm.period = info->period;
parm.mac_id = macid;
ret = send_h2c_keep_alive(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_gtk_ofld(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_gtk_ofld_info *info,
struct mac_ax_gtk_info_parm_ *content)
{
u32 ret = 0;
struct gtk_ofld parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
parm.gtk_en = info->gtk_en;
parm.tkip_en = info->tkip_en;
parm.ieee80211w_en = info->ieee80211w_en;
parm.pairwise_wakeup = info->pairwise_wakeup;
parm.mac_id = macid;
parm.gtk_rsp_id = info->gtk_rsp_id;
parm.pmf_sa_query_id = info->pmf_sa_query_id;
parm.bip_sec_algo = info->bip_sec_algo;
parm.algo_akm_suit = info->algo_akm_suit;
if (content)
PLTFM_MEMCPY(&parm.gtk_info_content, content,
sizeof(struct mac_ax_gtk_info_parm_));
ret = send_h2c_gtk_ofld(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_arp_ofld(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_arp_ofld_info *info,
void *parp_info_content)
{
u32 ret = 0;
struct arp_ofld parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
PLTFM_MEMSET(&parm, 0, sizeof(struct arp_ofld));
parm.arp_en = info->arp_en;
parm.arp_action = info->arp_action;
parm.mac_id = macid;
parm.arp_rsp_id = info->arp_rsp_id;
//if (parp_info_content)
// PLTFM_MEMCPY(&parm.ndp_info_content, parp_info_content,
// sizeof(struct _arp_info_parm_) * 2);
ret = send_h2c_arp_ofld(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_ndp_ofld(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_ndp_ofld_info *info,
struct mac_ax_ndp_info_parm_ *content)
{
u32 ret = 0;
struct ndp_ofld parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
PLTFM_MEMSET(&parm, 0, sizeof(struct ndp_ofld));
parm.ndp_en = info->ndp_en;
parm.na_id = info->na_id;
parm.mac_id = macid;
if (content)
PLTFM_MEMCPY(&parm.ndp_info_content, content,
sizeof(struct mac_ax_ndp_info_parm_) * 2);
ret = send_h2c_ndp_ofld(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_realwow(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_realwow_info *info,
struct mac_ax_realwowv2_info_parm_ *content)
{
u32 ret = 0;
struct realwow parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
PLTFM_MEMSET(&parm, 0, sizeof(struct realwow));
parm.realwow_en = info->realwow_en;
parm.auto_wakeup = info->auto_wakeup;
parm.mac_id = macid;
parm.keepalive_id = info->keepalive_id;
parm.wakeup_pattern_id = info->wakeup_pattern_id;
parm.ack_pattern_id = info->ack_pattern_id;
if (content)
PLTFM_MEMCPY(&parm.realwow_info_content, content,
sizeof(struct mac_ax_realwowv2_info_parm_));
ret = send_h2c_realwow(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_nlo(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_nlo_info *info,
struct mac_ax_nlo_networklist_parm_ *content)
{
u32 ret = 0;
struct nlo parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
PLTFM_MEMSET(&parm, 0, sizeof(struct nlo));
parm.nlo_en = info->nlo_en;
parm.nlo_32k_en = info->nlo_32k_en;
parm.ignore_cipher_type = info->ignore_cipher_type;
parm.mac_id = macid;
if (content)
PLTFM_MEMCPY(&parm.nlo_networklistinfo_content,
content,
sizeof(struct mac_ax_nlo_networklist_parm_));
ret = send_h2c_nlo(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_cfg_uphy_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_uphy_ctrl_info *info)
{
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
return MACSUCCESS;
}
u32 mac_cfg_wowcam_upd(struct mac_ax_adapter *adapter,
struct mac_ax_wowcam_upd_info *info)
{
u32 ret = 0;
struct wowcam_upd parm;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
PLTFM_MEMSET(&parm, 0, sizeof(struct wowcam_upd));
parm.r_w = info->r_w;
parm.idx = info->idx;
parm.wkfm1 = info->wkfm1;
parm.wkfm2 = info->wkfm2;
parm.wkfm3 = info->wkfm3;
parm.wkfm4 = info->wkfm4;
parm.crc = info->crc;
parm.negative_pattern_match = info->negative_pattern_match;
parm.skip_mac_hdr = info->skip_mac_hdr;
parm.uc = info->uc;
parm.mc = info->mc;
parm.bc = info->bc;
parm.valid = info->valid;
ret = send_h2c_wowcam_upd(adapter, &parm);
if (ret)
return ret;
return MACSUCCESS;
}
u32 get_wake_reason(struct mac_ax_adapter *adapter, u8 *wowlan_wake_reason)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
*wowlan_wake_reason = MAC_REG_R8(R_AX_C2HREG_DATA3_V1 + 3);
else
*wowlan_wake_reason = MAC_REG_R8(R_AX_C2HREG_DATA3 + 3);
return MACSUCCESS;
}
u32 mac_get_wow_wake_rsn(struct mac_ax_adapter *adapter, u8 *wake_rsn,
u8 *reset)
{
u32 ret = MACSUCCESS;
ret = get_wake_reason(adapter, wake_rsn);
if (ret != MACSUCCESS)
return ret;
switch (*wake_rsn) {
case MAC_AX_WOW_DMAC_ERROR_OCCURRED:
case MAC_AX_WOW_EXCEPTION_OCCURRED:
case MAC_AX_WOW_L0_TO_L1_ERROR_OCCURRED:
case MAC_AX_WOW_ASSERT_OCCURRED:
case MAC_AX_WOW_L2_ERROR_OCCURRED:
case MAC_AX_WOW_WDT_TIMEOUT_WAKE:
*reset = 1;
break;
default:
*reset = 0;
break;
}
return MACSUCCESS;
}
u32 mac_cfg_wow_sleep(struct mac_ax_adapter *adapter,
u8 sleep)
{
u32 ret;
u32 val32;
u8 dbg_page;
struct mac_ax_phy_rpt_cfg cfg;
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
PLTFM_MEMSET(&cfg, 0, sizeof(struct mac_ax_phy_rpt_cfg));
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
if (sleep) {
ret = _patch_redu_rx_qta(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch reduce rx qta %d\n", ret);
return ret;
}
cfg.type = MAC_AX_PPDU_STATUS;
cfg.en = 0;
ret = mac_ops->cfg_phy_rpt(adapter, &cfg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP, 1, 0);
if (ret)
return ret;
ret = MAC_REG_W_OFLD(R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE, 0, 0);
if (ret)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_ACTION_FWD0, 0x00000000, 0);
if (ret)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_ACTION_FWD1, 0x00000000, 0);
if (ret)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_TF_FWD, 0x00000000, 0);
if (ret)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_HW_RPT_FWD, 0x00000000, 1);
if (ret)
return ret;
} else {
ret = _patch_restr_rx_qta(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch resume rx qta %d\n", ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP, 0, 0);
if (ret)
return ret;
ret = MAC_REG_W_OFLD(R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE, 1, 0);
if (ret)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD, 0);
if (ret)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD, 1);
if (ret)
return ret;
cfg.type = MAC_AX_PPDU_STATUS;
cfg.en = 1;
ret = mac_ops->cfg_phy_rpt(adapter, &cfg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret);
return ret;
}
}
return MACSUCCESS;
}
#endif
if (sleep) {
ret = _patch_redu_rx_qta(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch reduce rx qta %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(R_AX_RX_FUNCTION_STOP);
val32 |= B_AX_HDR_RX_STOP;
MAC_REG_W32(R_AX_RX_FUNCTION_STOP, val32);
val32 = MAC_REG_R32(R_AX_RX_FLTR_OPT);
val32 &= ~B_AX_SNIFFER_MODE;
MAC_REG_W32(R_AX_RX_FLTR_OPT, val32);
cfg.type = MAC_AX_PPDU_STATUS;
cfg.en = 0;
ret = mac_ops->cfg_phy_rpt(adapter, &cfg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret);
return ret;
}
MAC_REG_W32(R_AX_ACTION_FWD0, 0x00000000);
MAC_REG_W32(R_AX_ACTION_FWD1, 0x00000000);
MAC_REG_W32(R_AX_TF_FWD, 0x00000000);
MAC_REG_W32(R_AX_HW_RPT_FWD, 0x00000000);
} else {
ret = _patch_restr_rx_qta(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch resume rx qta %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(R_AX_RX_FUNCTION_STOP);
val32 &= ~B_AX_HDR_RX_STOP;
MAC_REG_W32(R_AX_RX_FUNCTION_STOP, val32);
val32 = MAC_REG_R32(R_AX_RX_FLTR_OPT);
MAC_REG_W32(R_AX_RX_FLTR_OPT, val32);
cfg.type = MAC_AX_PPDU_STATUS;
cfg.en = 1;
ret = mac_ops->cfg_phy_rpt(adapter, &cfg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]cfg_phy_rpt failed %d\n", ret);
return ret;
}
MAC_REG_W32(R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
MAC_REG_W32(R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
PLTFM_MSG_ERR("[wow] Start to dump PLE debug pages\n");
for (dbg_page = 0; dbg_page < 4; dbg_page++)
mac_ops->dump_ple_dbg_page(adapter, dbg_page);
}
return MACSUCCESS;
}
u32 mac_get_wow_fw_status(struct mac_ax_adapter *adapter, u8 *status,
u8 func_en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (func_en)
func_en = 1;
*status = !!((MAC_REG_R8(R_AX_WOW_CTRL) & B_AX_WOW_WOWEN));
if (func_en == *status)
*status = 1;
else
*status = 0;
return MACSUCCESS;
}
u32 _mac_request_aoac_report_rx_rdy(struct mac_ax_adapter *adapter)
{
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
struct fwcmd_aoac_report_req *fwcmd_aoac_rpt_req;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_aoac_report_req));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_aoac_rpt_req = (struct fwcmd_aoac_report_req *)buf;
fwcmd_aoac_rpt_req->dword0 =
cpu_to_le32(FWCMD_H2C_AOAC_REPORT_REQ_RX_READY);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_WOW, FWCMD_H2C_FUNC_AOAC_REPORT_REQ,
1, 0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_ERROR;
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 _mac_request_aoac_report_rx_not_rdy(struct mac_ax_adapter *adapter)
{
struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info;
struct mac_ax_aoac_report *aoac_rpt = (struct mac_ax_aoac_report *)wow_info->aoac_report;
struct mac_ax_h2creg_info h2c_info = {0};
struct mac_ax_c2hreg_poll c2h_poll = {0};
struct fwcmd_c2hreg *c2h_content = &c2h_poll.c2hreg_cont.c2h_content;
u32 ret;
u8 *p_iv;
h2c_info.id = FWCMD_H2CREG_FUNC_AOAC_RPT_1;
h2c_info.content_len = sizeof(struct fwcmd_aoac_rpt_1);
c2h_poll.polling_id = FWCMD_C2HREG_FUNC_AOAC_RPT_1;
c2h_poll.retry_cnt = WOW_GET_AOAC_RPT_C2H_CNT;
c2h_poll.retry_wait_us = WOW_GET_AOAC_RPT_C2H_DLY;
ret = proc_msg_reg(adapter, &h2c_info, &c2h_poll);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: get aoac rpt(%d) fail: %d\n",
__func__, FWCMD_C2HREG_FUNC_AOAC_RPT_1, ret);
return ret;
}
aoac_rpt->key_idx = GET_FIELD(c2h_content->dword0,
FWCMD_C2HREG_AOAC_RPT_1_KEY_IDX);
aoac_rpt->rekey_ok = GET_FIELD(c2h_content->dword0,
FWCMD_C2HREG_AOAC_RPT_1_REKEY_OK);
p_iv = (&aoac_rpt->gtk_rx_iv_0[0] + (aoac_rpt->key_idx * IV_LENGTH));
p_iv[0] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_1_IV_0);
p_iv[1] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_1_IV_1);
p_iv[2] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_1_IV_2);
p_iv[3] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_1_IV_3);
p_iv[4] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_1_IV_4);
p_iv[5] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_1_IV_5);
p_iv[6] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_1_IV_6);
p_iv[7] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_1_IV_7);
aoac_rpt->ptk_rx_iv[0] = GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_0);
aoac_rpt->ptk_rx_iv[1] = GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_1);
aoac_rpt->ptk_rx_iv[2] = GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_2);
aoac_rpt->ptk_rx_iv[3] = GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_3);
h2c_info.id = FWCMD_H2CREG_FUNC_AOAC_RPT_2;
h2c_info.content_len = sizeof(struct fwcmd_aoac_rpt_2);
c2h_poll.polling_id = FWCMD_C2HREG_FUNC_AOAC_RPT_2;
c2h_poll.retry_cnt = WOW_GET_AOAC_RPT_C2H_CNT;
c2h_poll.retry_wait_us = WOW_GET_AOAC_RPT_C2H_DLY;
ret = proc_msg_reg(adapter, &h2c_info, &c2h_poll);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: get aoac rpt(%d) fail: %d\n",
__func__, FWCMD_C2HREG_FUNC_AOAC_RPT_2, ret);
return ret;
}
aoac_rpt->ptk_rx_iv[4] = GET_FIELD(c2h_content->dword0,
FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_4);
aoac_rpt->ptk_rx_iv[5] = GET_FIELD(c2h_content->dword0,
FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_5);
aoac_rpt->ptk_rx_iv[6] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_6);
aoac_rpt->ptk_rx_iv[7] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_7);
aoac_rpt->igtk_ipn[0] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_0);
aoac_rpt->igtk_ipn[1] = GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_1);
aoac_rpt->igtk_ipn[2] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_2);
aoac_rpt->igtk_ipn[3] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_3);
aoac_rpt->igtk_ipn[4] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_4);
aoac_rpt->igtk_ipn[5] = GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_5);
aoac_rpt->igtk_ipn[6] = GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_6);
aoac_rpt->igtk_ipn[7] = GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_7);
return MACSUCCESS;
}
u32 mac_request_aoac_report(struct mac_ax_adapter *adapter,
u8 rx_ready)
{
u32 ret;
struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info;
if (adapter->sm.aoac_rpt != MAC_AX_AOAC_RPT_IDLE)
return MACPROCERR;
if (wow_info->aoac_report) {
PLTFM_FREE(wow_info->aoac_report,
sizeof(struct mac_ax_aoac_report));
}
wow_info->aoac_report = (u8 *)PLTFM_MALLOC(sizeof(struct mac_ax_aoac_report));
if (!wow_info->aoac_report) {
PLTFM_MSG_ERR("%s: malloc fail\n", __func__);
return MACBUFALLOC;
}
adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_H2C_SENDING;
if (rx_ready)
ret = _mac_request_aoac_report_rx_rdy(adapter);
else
ret = _mac_request_aoac_report_rx_not_rdy(adapter);
return ret;
}
u32 mac_read_aoac_report(struct mac_ax_adapter *adapter,
struct mac_ax_aoac_report *rpt_buf, u8 rx_ready)
{
struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info;
u32 ret = MACSUCCESS;
u8 cnt = 100;
while ((rx_ready) && (adapter->sm.aoac_rpt != MAC_AX_AOAC_RPT_H2C_DONE)) {
PLTFM_DELAY_MS(1);
if (--cnt == 0) {
PLTFM_MSG_ERR("[ERR] read aoac report(%d) fail\n",
adapter->sm.aoac_rpt);
adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_IDLE;
return MACPOLLTO;
}
}
if (wow_info->aoac_report) {
PLTFM_MEMCPY(rpt_buf, wow_info->aoac_report,
sizeof(struct mac_ax_aoac_report));
PLTFM_FREE(wow_info->aoac_report,
sizeof(struct mac_ax_aoac_report));
wow_info->aoac_report = NULL;
} else {
PLTFM_MSG_ERR("[ERR] aoac report memory allocate fail\n");
ret = MACBUFALLOC;
}
adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_IDLE;
return ret;
}
u32 mac_check_aoac_report_done(struct mac_ax_adapter *adapter)
{
PLTFM_MSG_TRACE("[TRACE]%s: curr state: %d\n", __func__,
adapter->sm.aoac_rpt);
if (adapter->sm.aoac_rpt == MAC_AX_AOAC_RPT_H2C_DONE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_wow_stop_trx(struct mac_ax_adapter *adapter)
{
struct mac_ax_h2creg_info h2c_info;
struct mac_ax_c2hreg_poll c2h_poll;
u32 ret;
if (adapter->sm.wow_stoptrx_stat == MAC_AX_WOW_STOPTRX_BUSY) {
PLTFM_MSG_ERR("[ERR]wow stop trx busy\n");
return MACPROCERR;
} else if (adapter->sm.wow_stoptrx_stat == MAC_AX_WOW_STOPTRX_FAIL) {
PLTFM_MSG_WARN("[WARN]prev wow stop trx fail\n");
}
adapter->sm.wow_stoptrx_stat = MAC_AX_WOW_STOPTRX_BUSY;
h2c_info.id = FWCMD_H2CREG_FUNC_WOW_TRX_STOP;
h2c_info.content_len = 0;
h2c_info.h2c_content.dword0 = 0;
h2c_info.h2c_content.dword1 = 0;
h2c_info.h2c_content.dword2 = 0;
h2c_info.h2c_content.dword3 = 0;
c2h_poll.polling_id = FWCMD_C2HREG_FUNC_WOW_TRX_STOP;
c2h_poll.retry_cnt = WOW_GET_STOP_TRX_C2H_CNT;
c2h_poll.retry_wait_us = WOW_GET_STOP_TRX_C2H_DLY;
ret = proc_msg_reg(adapter, &h2c_info, &c2h_poll);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]wow stoptrx proc msg reg %d\n", ret);
adapter->sm.wow_stoptrx_stat = MAC_AX_WOW_STOPTRX_FAIL;
return ret;
}
adapter->sm.wow_stoptrx_stat = MAC_AX_WOW_STOPTRX_IDLE;
return MACSUCCESS;
}
u32 free_aoac_report(struct mac_ax_adapter *adapter)
{
struct mac_ax_wowlan_info *wow_info = &adapter->wowlan_info;
if (wow_info->aoac_report) {
PLTFM_FREE(wow_info->aoac_report,
sizeof(struct mac_ax_aoac_report));
wow_info->aoac_report = NULL;
} else {
PLTFM_MSG_ERR("[ERR] aoac report pointer null\n");
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/wowlan.c
|
C
|
agpl-3.0
| 44,883
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_WOWLAN_H_
#define _MAC_AX_WOWLAN_H_
#include "../type.h"
#include "fwcmd.h"
#include "role.h"
#include "gpio_cmd.h"
#define WOW_GET_STOP_TRX_C2H_CNT 10000
#define WOW_GET_STOP_TRX_C2H_DLY 10
#define WOW_GET_AOAC_RPT_C2H_CNT 1000
#define WOW_GET_AOAC_RPT_C2H_DLY 100
#define WOW_STOPTRX_H2CREG_DW_SIZE 1 /* mapping to struct wow_stoptrx_h2creg */
/**
* @struct keep_alive
* @brief keep_alive
*
* @var keep_alive::keepalive_en
* Please Place Description here.
* @var keep_alive::rsvd0
* Please Place Description here.
* @var keep_alive::packet_id
* Please Place Description here.
* @var keep_alive::period
* Please Place Description here.
* @var keep_alive::mac_id
* Please Place Description here.
*/
struct keep_alive {
u32 keepalive_en:1;
u32 rsvd0:7;
u32 packet_id:8;
u32 period:8;
u32 mac_id:8;
};
/**
* @struct disconnect_detect
* @brief disconnect_detect
*
* @var disconnect_detect::disconnect_detect_en
* Please Place Description here.
* @var disconnect_detect::tryok_bcnfail_count_en
* Please Place Description here.
* @var disconnect_detect::disconnect_en
* Please Place Description here.
* @var disconnect_detect::rsvd0
* Please Place Description here.
* @var disconnect_detect::mac_id
* Please Place Description here.
* @var disconnect_detect::check_period
* Please Place Description here.
* @var disconnect_detect::try_pkt_count
* Please Place Description here.
* @var disconnect_detect::tryok_bcnfail_count_limit
* Please Place Description here.
* @var disconnect_detect::rsvd1
* Please Place Description here.
*/
struct disconnect_detect {
u32 disconnect_detect_en:1;
u32 tryok_bcnfail_count_en:1;
u32 disconnect_en:1;
u32 rsvd0:5;
u32 mac_id:8;
u32 check_period:8;
u32 try_pkt_count:8;
u32 tryok_bcnfail_count_limit:8;
u32 rsvd1:24;
};
/**
* @struct wow_global
* @brief wow_global
*
* @var wow_global::wow_en
* Please Place Description here.
* @var wow_global::drop_all_pkt
* Please Place Description here.
* @var wow_global::rx_parse_after_wake
* Please Place Description here.
* @var wow_global::rsvd0
* Please Place Description here.
* @var wow_global::mac_id
* Please Place Description here.
* @var wow_global::pairwise_sec_algo
* Please Place Description here.
* @var wow_global::group_sec_algo
* Please Place Description here.
* @var wow_global::remotectrl_info_content
* Please Place Description here.
* @var wow_global::remotectrl_info_more
* Please Place Description here.
*/
struct wow_global {
u32 wow_en:1;
u32 drop_all_pkt:1;
u32 rx_parse_after_wake:1;
u32 rsvd0:5;
u32 mac_id:8;
u32 pairwise_sec_algo:8;
u32 group_sec_algo:8;
u32 remotectrl_info_content;
u32 remotectrl_info_more[sizeof(struct
mac_ax_remotectrl_info_parm_) / 4 - 1];
};
/**
* @struct gtk_ofld
* @brief gtk_ofld
*
* @var gtk_ofld::gtk_en
* Please Place Description here.
* @var gtk_ofld::tkip_en
* Please Place Description here.
* @var gtk_ofld::ieee80211w_en
* Please Place Description here.
* @var gtk_ofld::pairwise_wakeup
* Please Place Description here.
* @var gtk_ofld::rsvd0
* Please Place Description here.
* @var gtk_ofld::aoac_rep_id
* Please Place Description here.
* @var gtk_ofld::mac_id
* Please Place Description here.
* @var gtk_ofld::gtk_rsp_id
* Please Place Description here.
* @var gtk_ofld::pmf_sa_query_id
* Please Place Description here.
* @var gtk_ofld::bip_sec_algo
* Please Place Description here.
* @var gtk_ofld::rsvd1
* Please Place Description here.
* @var gtk_ofld::gtk_info_content
* Please Place Description here.
* @var gtk_ofld::gtk_info_more
* Please Place Description here.
*/
struct gtk_ofld {
u32 gtk_en:1;
u32 tkip_en:1;
u32 ieee80211w_en:1;
u32 pairwise_wakeup:1;
u32 rsvd0:4;
u32 aoac_rep_id:8;
u32 mac_id:8;
u32 gtk_rsp_id:8;
u32 pmf_sa_query_id:8;
u32 bip_sec_algo:2;
u32 algo_akm_suit: 8;
u32 rsvd1: 14;
u32 gtk_info_content;
//u32 gtk_info_more[30];
u32 gtk_info_more[sizeof(struct mac_ax_gtk_info_parm_) / 4 - 1];
};
/**
* @struct arp_ofld
* @brief arp_ofld
*
* @var arp_ofld::arp_en
* Please Place Description here.
* @var arp_ofld::arp_action
* Please Place Description here.
* @var arp_ofld::rsvd0
* Please Place Description here.
* @var arp_ofld::mac_id
* Please Place Description here.
* @var arp_ofld::arp_rsp_id
* Please Place Description here.
* @var arp_ofld::arp_info_content
* Please Place Description here.
*/
struct arp_ofld {
u32 arp_en:1;
u32 arp_action:1;
u32 rsvd0:14;
u32 mac_id:8;
u32 arp_rsp_id:8;
u32 arp_info_content:32;
};
/**
* @struct ndp_ofld
* @brief ndp_ofld
*
* @var ndp_ofld::ndp_en
* Please Place Description here.
* @var ndp_ofld::rsvd0
* Please Place Description here.
* @var ndp_ofld::mac_id
* Please Place Description here.
* @var ndp_ofld::na_id
* Please Place Description here.
* @var ndp_ofld::ndp_info_content
* Please Place Description here.
* @var ndp_ofld::ndp_info_more
* Please Place Description here.
*/
struct ndp_ofld {
u32 ndp_en:1;
u32 rsvd0:15;
u32 mac_id:8;
u32 na_id:8;
u32 ndp_info_content;
//u32 ndp_info_more[27];
u32 ndp_info_more[2 * sizeof(struct mac_ax_ndp_info_parm_) / 4 - 1];
};
/**
* @struct realwow
* @brief realwow
*
* @var realwow::realwow_en
* Please Place Description here.
* @var realwow::auto_wakeup
* Please Place Description here.
* @var realwow::rsvd0
* Please Place Description here.
* @var realwow::mac_id
* Please Place Description here.
* @var realwow::keepalive_id
* Please Place Description here.
* @var realwow::wakeup_pattern_id
* Please Place Description here.
* @var realwow::ack_pattern_id
* Please Place Description here.
* @var realwow::rsvd1
* Please Place Description here.
* @var realwow::realwow_info_content
* Please Place Description here.
* @var realwow::realwow_info_more
* Please Place Description here.
*/
struct realwow {
u32 realwow_en:1;
u32 auto_wakeup:1;
u32 rsvd0:22;
u32 mac_id:8;
u32 keepalive_id:8;
u32 wakeup_pattern_id:8;
u32 ack_pattern_id:8;
u32 rsvd1:8;
u32 realwow_info_content;
u32 realwow_info_more[sizeof(struct mac_ax_realwowv2_info_parm_)
/ 4 - 1];
};
/**
* @struct nlo
* @brief nlo
*
* @var nlo::nlo_en
* Please Place Description here.
* @var nlo::nlo_32k_en
* Please Place Description here.
* @var nlo::ignore_cipher_type
* Please Place Description here.
* @var nlo::rsvd0
* Please Place Description here.
* @var nlo::mac_id
* Please Place Description here.
* @var nlo::nlo_networklistinfo_content
* Please Place Description here.
* @var nlo::nlo_networklistinfo_more
* Please Place Description here.
*/
struct nlo {
u32 nlo_en:1;
u32 nlo_32k_en:1;
u32 ignore_cipher_type:1;
u32 rsvd0:21;
u32 mac_id:8;
u32 nlo_networklistinfo_content;
u32 nlo_networklistinfo_more[sizeof(struct mac_ax_nlo_networklist_parm_)
/ 4 - 1];
};
/**
* @struct wakeup_ctrl
* @brief wakeup_ctrl
*
* @var wakeup_ctrl::pattern_match_en
* Please Place Description here.
* @var wakeup_ctrl::magic_en
* Please Place Description here.
* @var wakeup_ctrl::hw_unicast_en
* Please Place Description here.
* @var wakeup_ctrl::fw_unicast_en
* Please Place Description here.
* @var wakeup_ctrl::deauth_wakeup
* Please Place Description here.
* @var wakeup_ctrl::rekey_wakeup
* Please Place Description here.
* @var wakeup_ctrl::eap_wakeup
* Please Place Description here.
* @var wakeup_ctrl::all_data_wakeup
* Please Place Description here.
* @var wakeup_ctrl::rsvd0
* Please Place Description here.
* @var wakeup_ctrl::rsvd1
* Please Place Description here.
* @var wakeup_ctrl::mac_id
* Please Place Description here.
*/
struct wakeup_ctrl {
u32 pattern_match_en:1;
u32 magic_en:1;
u32 hw_unicast_en:1;
u32 fw_unicast_en:1;
u32 deauth_wakeup:1;
u32 rekey_wakeup:1;
u32 eap_wakeup:1;
u32 all_data_wakeup:1;
u32 rsvd0:1;
u32 rsvd1:15;
u32 mac_id:8;
};
/**
* @struct negative_pattern
* @brief negative_pattern
*
* @var negative_pattern::negative_pattern_en
* Please Place Description here.
* @var negative_pattern::rsvd0
* Please Place Description here.
* @var negative_pattern::pattern_count
* Please Place Description here.
* @var negative_pattern::mac_id
* Please Place Description here.
* @var negative_pattern::pattern_content
* Please Place Description here.
*/
struct negative_pattern {
u32 negative_pattern_en:1;
u32 rsvd0:19;
u32 pattern_count:4;
u32 mac_id:8;
u32 pattern_content:32;
};
/**
* @struct uphy_ctrl
* @brief uphy_ctrl
*
* @var uphy_ctrl::disable_uphy
* Please Place Description here.
* @var uphy_ctrl::handshake_mode
* Please Place Description here.
* @var uphy_ctrl::rsvd0
* Please Place Description here.
* @var uphy_ctrl::rise_hst2dev_dis_uphy
* Please Place Description here.
* @var uphy_ctrl::uphy_dis_delay_unit
* Please Place Description here.
* @var uphy_ctrl::pdn_as_uphy_dis
* Please Place Description here.
* @var uphy_ctrl::pdn_to_enable_uphy
* Please Place Description here.
* @var uphy_ctrl::rsvd1
* Please Place Description here.
* @var uphy_ctrl::hst2dev_gpio_num
* Please Place Description here.
* @var uphy_ctrl::uphy_dis_delay_count
* Please Place Description here.
*/
struct uphy_ctrl {
u32 disable_uphy:1;
u32 handshake_mode:3;
u32 rsvd0:4;
u32 rise_hst2dev_dis_uphy:1;
u32 uphy_dis_delay_unit:1;
u32 pdn_as_uphy_dis:1;
u32 pdn_to_enable_uphy:1;
u32 rsvd1:4;
u32 hst2dev_gpio_num:8;
u32 uphy_dis_delay_count:8;
};
/**
* @struct wowcam_upd
* @brief wowcam_upd
*
* @var wowcam_upd::r_w
* Please Place Description here.
* @var wowcam_upd::idx
* Please Place Description here.
* @var wowcam_upd::rsvd0
* Please Place Description here.
* @var wowcam_upd::wkfm1
* Please Place Description here.
* @var wowcam_upd::wkfm2
* Please Place Description here.
* @var wowcam_upd::wkfm3
* Please Place Description here.
* @var wowcam_upd::wkfm4
* Please Place Description here.
* @var wowcam_upd::crc
* Please Place Description here.
* @var wowcam_upd::rsvd1
* Please Place Description here.
* @var wowcam_upd::negative_pattern_match
* Please Place Description here.
* @var wowcam_upd::skip_mac_hdr
* Please Place Description here.
* @var wowcam_upd::uc
* Please Place Description here.
* @var wowcam_upd::mc
* Please Place Description here.
* @var wowcam_upd::bc
* Please Place Description here.
* @var wowcam_upd::rsvd2
* Please Place Description here.
* @var wowcam_upd::valid
* Please Place Description here.
*/
struct wowcam_upd {
u32 r_w: 1;
u32 idx: 7;
u32 rsvd0: 24;
u32 wkfm1: 32;
u32 wkfm2: 32;
u32 wkfm3: 32;
u32 wkfm4: 32;
u32 crc: 16;
u32 rsvd1: 6;
u32 negative_pattern_match: 1;
u32 skip_mac_hdr: 1;
u32 uc: 1;
u32 mc: 1;
u32 bc: 1;
u32 rsvd2: 4;
u32 valid: 1;
};
struct wow_stoptrx_h2creg {
u32 func:7;
u32 ack:1;
u32 total_len:4;
u32 seq_num:4;
u32 rsvd:16;
};
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_wow_wake
*
* @param *adapter
* @param macid
* @param *info
* @param *content
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_wow_wake(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_wow_wake_info *info,
struct mac_ax_remotectrl_info_parm_ *content);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_disconnect_det
*
* @param *adapter
* @param macid
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_disconnect_det(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_disconnect_det_info *info);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_keep_alive
*
* @param *adapter
* @param macid
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_keep_alive(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_keep_alive_info *info);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief get_wake_reason
*
* @param *adapter
* @param *wowlan_wake_reason
* @return Please Place Description here.
* @retval u32
*/
u32 get_wake_reason(struct mac_ax_adapter *adapter,
u8 *wowlan_wake_reason);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_gtk_ofld
*
* @param *adapter
* @param macid
* @param *info
* @param *content
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_gtk_ofld(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_gtk_ofld_info *info,
struct mac_ax_gtk_info_parm_ *content);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_arp_ofld
*
* @param *adapter
* @param macid
* @param *info
* @param *parp_info_content
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_arp_ofld(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_arp_ofld_info *info,
void *parp_info_content);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_ndp_ofld
*
* @param *adapter
* @param macid
* @param *info
* @param *content
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_ndp_ofld(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_ndp_ofld_info *info,
struct mac_ax_ndp_info_parm_ *content);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_realwow
*
* @param *adapter
* @param macid
* @param *info
* @param *content
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_realwow(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_realwow_info *info,
struct mac_ax_realwowv2_info_parm_ *content);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_nlo
*
* @param *adapter
* @param macid
* @param *info
* @param *content
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_nlo(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_nlo_info *info,
struct mac_ax_nlo_networklist_parm_ *content);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_dev2hst_gpio
*
* @param *adapter
* @param *parm
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_dev2hst_gpio(struct mac_ax_adapter *adapter,
struct mac_ax_dev2hst_gpio_info *parm);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_uphy_ctrl
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_uphy_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_uphy_ctrl_info *info);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_wowcam_upd
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_wowcam_upd(struct mac_ax_adapter *adapter,
struct mac_ax_wowcam_upd_info *info);
/**
* @}
*/
u32 mac_get_wow_wake_rsn(struct mac_ax_adapter *adapter, u8 *wake_rsn,
u8 *reset);
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_cfg_wow_sleep
*
* @param *adapter
* @param sleep
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_wow_sleep(struct mac_ax_adapter *adapter,
u8 sleep);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_get_wow_fw_status
*
* @param *adapter
* @param *status
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_wow_fw_status(struct mac_ax_adapter *adapter,
u8 *status, u8 func_en);
/**
* @}
*/
static u32 read_aoac_c2hreg(struct mac_ax_adapter *adapter,
struct mac_ax_aoac_report *aoac_rpt);
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_request_aoac_report
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_request_aoac_report(struct mac_ax_adapter *adapter,
u8 rx_ready);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_read_aoac_report
*
* @param *adapter
* @param **rpt_buf
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_aoac_report(struct mac_ax_adapter *adapter,
struct mac_ax_aoac_report *rpt_buf, u8 rx_ready);
/**
* @}
*/
/**
* @addtogroup WakeOnWlan
* @{
*/
/**
* @brief mac_check_aoac_report_done
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_aoac_report_done(struct mac_ax_adapter *adapter);
/**
* @}
*/
u32 mac_wow_stop_trx(struct mac_ax_adapter *adapter);
u32 mac_wow_get_stoptrx_st(struct mac_ax_adapter *adapter);
/**
* @brief free_aoac_report
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 free_aoac_report(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
#endif // #define _MAC_AX_WOWLAN_H_
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/wowlan.h
|
C
|
agpl-3.0
| 17,492
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "mac_ax.h"
#define CHIP_ID_HW_DEF_8852A 0x50
#define CHIP_ID_HW_DEF_8852B 0x51
#define CHIP_ID_HW_DEF_8852C 0x52
#define CHIP_ID_HW_DEF_8192XB 0x53
#define SDIO_WAIT_CNT 50
#if MAC_AX_SDIO_SUPPORT
static u8 r8_indir_cmd52_sdio(void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb, u32 adr);
#endif
#ifndef CONFIG_NEW_HALMAC_INTERFACE
static u8 chk_pltfm_cb(void *drv_adapter, enum mac_ax_intf intf,
struct mac_ax_pltfm_cb *pltfm_cb)
{
if (!pltfm_cb)
return MACSUCCESS;
if (!pltfm_cb->msg_print)
return MACSUCCESS;
#if MAC_AX_SDIO_SUPPORT
if (!pltfm_cb->sdio_cmd52_r8 || !pltfm_cb->sdio_cmd53_r8 ||
!pltfm_cb->sdio_cmd53_r16 || !pltfm_cb->sdio_cmd53_r32 ||
!pltfm_cb->sdio_cmd53_rn || !pltfm_cb->sdio_cmd52_w8 ||
!pltfm_cb->sdio_cmd53_w8 || !pltfm_cb->sdio_cmd53_w16 ||
!pltfm_cb->sdio_cmd53_w32 || !pltfm_cb->sdio_cmd53_wn ||
!pltfm_cb->sdio_cmd52_cia_r8) {
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]CB-SDIO\n");
return MACSUCCESS;
}
#endif
#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT)
if (!pltfm_cb->reg_r8 || !pltfm_cb->reg_r16 ||
!pltfm_cb->reg_r32 || !pltfm_cb->reg_w8 ||
!pltfm_cb->reg_w16 || !pltfm_cb->reg_w32) {
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]CB-USB or PCIE\n");
return MACSUCCESS;
}
#endif
if (!pltfm_cb->rtl_free || !pltfm_cb->rtl_malloc ||
!pltfm_cb->rtl_memcpy || !pltfm_cb->rtl_memset ||
!pltfm_cb->rtl_delay_us || !pltfm_cb->rtl_delay_ms ||
!pltfm_cb->rtl_mutex_init || !pltfm_cb->rtl_mutex_deinit ||
!pltfm_cb->rtl_mutex_lock || !pltfm_cb->rtl_mutex_unlock ||
!pltfm_cb->event_notify) {
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]CB-OS\n");
return MACSUCCESS;
}
return MACPFCB;
}
#endif /*CONFIG_NEW_HALMAC_INTERFACE*/
static u8 chk_pltfm_endian(void)
{
u32 num = 1;
u8 *num_ptr = (u8 *)#
if (*num_ptr != PLATFOM_IS_LITTLE_ENDIAN)
return MACSUCCESS;
return MACPFCB;
}
#ifdef CONFIG_NEW_HALMAC_INTERFACE
#if MAC_AX_SDIO_SUPPORT
static u8 r8_indir_cmd52_sdio(void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb, u32 adr)
{
u8 tmp;
u32 cnt;
PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR, (u8)adr);
PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR + 1, (u8)(adr >> 8));
PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR + 2, (u8)(adr >> 16));
PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_ADDR + 3,
(u8)((adr | B_AX_INDIRECT_RDY) >> 24));
PLTFM_SDIO_CMD52_W8(R_AX_SDIO_INDIRECT_CTRL, (u8)B_AX_INDIRECT_REG_R);
cnt = SDIO_WAIT_CNT;
do {
tmp = PLTFM_SDIO_CMD52_R8(R_AX_SDIO_INDIRECT_ADDR + 3);
cnt--;
} while (((tmp & BIT(7)) == 0) && (cnt > 0));
if (((tmp & BIT(7)) == 0) && cnt == 0)
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n");
return PLTFM_SDIO_CMD52_R8(R_AX_SDIO_INDIRECT_DATA);
}
#endif
static u32 get_chip_info(struct mac_ax_adapter *adapter,
struct mac_ax_pltfm_cb *pltfm_cb,
enum mac_ax_intf intf, u8 *id, u8 *cv)
{
u32 cv_temp;
u8 cur_id;
if (!cv || !id)
return MACNPTR;
switch (intf) {
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_INTF_SDIO:
cur_id = r8_indir_cmd52_sdio(adapter, R_AX_SYS_CHIPINFO);
*cv = r8_indir_cmd52_sdio(adapter, R_AX_SYS_CFG1 + 1) >> 4;
break;
#endif
#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT)
case MAC_AX_INTF_USB:
case MAC_AX_INTF_PCIE:
cur_id = PLTFM_REG_R8(R_AX_SYS_CHIPINFO);
*cv = PLTFM_REG_R8(R_AX_SYS_CFG1 + 1) >> 4;
if (cur_id == CHIP_ID_HW_DEF_8852A) {
if (*cv <= CBV) {
cv_temp = PLTFM_REG_R32(R_AX_GPIO0_7_FUNC_SEL);
if (cv_temp == 0xdeadbeef)
*cv = CAV;
else
*cv = CBV;
}
}
break;
#endif
default:
return MACINTF;
}
switch (cur_id) {
case CHIP_ID_HW_DEF_8852A:
*id = MAC_AX_CHIP_ID_8852A;
break;
case CHIP_ID_HW_DEF_8852B:
*id = MAC_AX_CHIP_ID_8852B;
break;
case CHIP_ID_HW_DEF_8852C:
*id = MAC_AX_CHIP_ID_8852C;
break;
default:
return MACCHIPID;
}
return MACSUCCESS;
}
u32 mac_ax_ops_init_v1(void *phl_adapter, void *drv_adapter,
enum rtw_chip_id chip_id,
enum rtw_hci_type hci,
struct mac_ax_adapter **mac_adapter,
struct mac_ax_ops **mac_ops)
{
u32 ret;
u8 cv;
struct mac_ax_adapter *adapter;
enum mac_ax_intf intf = MAC_AX_INTF_INVALID;
if (!chk_pltfm_endian())
return MACPFED;
ret = 0;
if (hci == RTW_HCI_PCIE)
intf = MAC_AX_INTF_PCIE;
else if (hci == RTW_HCI_USB)
intf = MAC_AX_INTF_USB;
else if (hci == RTW_HCI_SDIO)
intf = MAC_AX_INTF_SDIO;
ret = get_chip_info(drv_adapter, NULL, intf, &chip_id, &cv);
if (ret)
return ret;
adapter = get_mac_ax_adapter(intf, chip_id, cv, phl_adapter,
drv_adapter, NULL);
if (!adapter) {
PLTFM_MSG_PRINT("[ERR]Get MAC adapter\n");
return MACADAPTER;
}
PLTFM_MSG_ALWAYS("MAC_AX_MAJOR_VER = %d\n"
"MAC_AX_PROTOTYPE_VER = %d\n"
"MAC_AX_SUB_VER = %d\n"
"MAC_AX_SUB_INDEX = %d\n",
MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER,
MAC_AX_SUB_VER, MAC_AX_SUB_INDEX);
*mac_adapter = adapter;
*mac_ops = adapter->ops;
return MACSUCCESS;
}
#else
#if MAC_AX_SDIO_SUPPORT
static u8 r8_indir_cmd52_sdio(void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb, u32 adr)
{
u8 tmp;
u32 cnt;
pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR,
(u8)adr);
pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR + 1,
(u8)(adr >> 8));
pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR + 2,
(u8)(adr >> 16));
pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_ADDR + 3,
(u8)((adr | B_AX_INDIRECT_RDY) >> 24));
pltfm_cb->sdio_cmd52_w8(drv_adapter, R_AX_SDIO_INDIRECT_CTRL,
(u8)B_AX_INDIRECT_REG_R);
cnt = SDIO_WAIT_CNT;
do {
tmp = pltfm_cb->sdio_cmd52_r8(drv_adapter,
R_AX_SDIO_INDIRECT_ADDR + 3);
cnt--;
} while (((tmp & BIT(7)) == 0) && (cnt > 0));
if (((tmp & BIT(7)) == 0) && cnt == 0)
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_,
"[ERR]sdio indirect CMD52 read\n");
return pltfm_cb->sdio_cmd52_r8(drv_adapter, R_AX_SDIO_INDIRECT_DATA);
}
#endif
static u32 get_chip_info(void *drv_adapter, struct mac_ax_pltfm_cb *pltfm_cb,
enum mac_ax_intf intf, u8 *id, u8 *cv)
{
u8 cur_id;
if (!cv || !id)
return MACNPTR;
switch (intf) {
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_INTF_SDIO:
cur_id = r8_indir_cmd52_sdio(drv_adapter, pltfm_cb,
R_AX_SYS_CHIPINFO);
*cv = r8_indir_cmd52_sdio(drv_adapter, pltfm_cb,
R_AX_SYS_CFG1 + 1) >> 4;
if (cur_id == CHIP_ID_HW_DEF_8852A)
if (*cv <= CBV)
*cv = CBV;
break;
#endif
#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT)
case MAC_AX_INTF_USB:
case MAC_AX_INTF_PCIE:
cur_id = pltfm_cb->reg_r8(drv_adapter, R_AX_SYS_CHIPINFO);
*cv = pltfm_cb->reg_r8(drv_adapter, R_AX_SYS_CFG1 + 1) >> 4;
if (cur_id == CHIP_ID_HW_DEF_8852A)
if (*cv <= CBV)
*cv = CBV;
break;
#endif
default:
return MACINTF;
}
switch (cur_id) {
case CHIP_ID_HW_DEF_8852A:
*id = MAC_AX_CHIP_ID_8852A;
break;
case CHIP_ID_HW_DEF_8852B:
*id = MAC_AX_CHIP_ID_8852B;
break;
case CHIP_ID_HW_DEF_8852C:
*id = MAC_AX_CHIP_ID_8852C;
break;
case CHIP_ID_HW_DEF_8192XB:
*id = MAC_AX_CHIP_ID_8192XB;
break;
default:
return MACCHIPID;
}
return MACSUCCESS;
}
u32 mac_ax_ops_init(void *drv_adapter, struct mac_ax_pltfm_cb *pltfm_cb,
enum mac_ax_intf intf,
struct mac_ax_adapter **mac_adapter,
struct mac_ax_ops **mac_ops)
{
u32 ret;
u8 chip_id = 0;
u8 cv = 0;
struct mac_ax_adapter *adapter;
if (!chk_pltfm_cb(drv_adapter, intf, pltfm_cb))
return MACPFCB;
if (!chk_pltfm_endian())
return MACPFED;
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_,
"MAC_AX_MAJOR_VER = %d\n"
"MAC_AX_PROTOTYPE_VER = %d\n"
"MAC_AX_SUB_VER = %d\n"
"MAC_AX_SUB_INDEX = %d\n",
MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER,
MAC_AX_SUB_VER, MAC_AX_SUB_INDEX);
ret = get_chip_info(drv_adapter, pltfm_cb, intf, &chip_id, &cv);
if (ret)
return ret;
adapter = get_mac_ax_adapter(intf, chip_id, cv, drv_adapter,
pltfm_cb);
if (!adapter) {
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "[ERR]Get MAC adapter\n");
return MACADAPTER;
}
*mac_adapter = adapter;
*mac_ops = adapter->ops;
#if MAC_AX_FEATURE_HV
adapter->hv_ops = get_hv_ax_ops(adapter);
#endif
#if MAC_AX_PHL_H2C
#else
ret = h2cb_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]h2cb init %d\n", ret);
return ret;
}
#endif
ret = role_tbl_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]role tbl init %d\n", ret);
return ret;
}
ret = sec_info_tbl_init(adapter, SEC_CAM_NORMAL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sec info tbl init %d\n", ret);
return ret;
}
ret = efuse_tbl_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]efuse tbl init %d\n", ret);
return ret;
}
ret = p2p_info_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]p2p info init %d\n", ret);
return ret;
}
ret = mport_info_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mpinfo info init %d\n", ret);
return ret;
}
ret = mix_info_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mix info init %d\n", ret);
return ret;
}
#if MAC_AX_SDIO_SUPPORT
ret = sdio_tbl_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sdio tbl init %d\n", ret);
return ret;
}
#endif
ret = hfc_info_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]hfc info init %d\n", ret);
return ret;
}
return MACSUCCESS;
}
#endif /*CONFIG_NEW_HALMAC_INTERFACE*/
#if MAC_AX_PHL_H2C
u32 mac_ax_phl_init(void *phl_adapter, struct mac_ax_adapter *mac_adapter)
{
struct mac_ax_adapter *adapter = mac_adapter;
adapter->phl_adapter = phl_adapter;
return MACSUCCESS;
}
#endif
u32 mac_ax_ops_exit(struct mac_ax_adapter *adapter)
{
u32 ret;
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
ret = h2cb_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]h2c buffer exit %d\n", ret);
return ret;
}
ret = free_sec_info_tbl(adapter, SEC_CAM_NORMAL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sec table exit %d\n", ret);
return ret;
}
ret = role_tbl_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]role table exit %d\n", ret);
return ret;
}
ret = efuse_tbl_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]efuse table exit %d\n", ret);
return ret;
}
ret = p2p_info_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]p2p info exit %d\n", ret);
return ret;
}
ret = mport_info_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mpinfo info exit %d\n", ret);
return ret;
}
ret = mix_info_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mix info exit %d\n", ret);
return ret;
}
#if MAC_AX_SDIO_SUPPORT
ret = sdio_tbl_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]efuse table exit %d\n", ret);
return ret;
}
#endif
ret = hfc_info_exit(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]hfc info exit %d\n", ret);
return ret;
}
ret = free_aoac_report(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]free aoac report %d\n", ret);
return ret;
}
if (efuse_param->efuse_map) {
PLTFM_FREE(efuse_param->efuse_map,
adapter->hw_info->efuse_size);
efuse_param->efuse_map = (u8 *)NULL;
}
if (efuse_param->bt_efuse_map) {
PLTFM_FREE(efuse_param->bt_efuse_map,
adapter->hw_info->bt_efuse_size);
efuse_param->bt_efuse_map = (u8 *)NULL;
}
if (efuse_param->log_efuse_map) {
PLTFM_FREE(efuse_param->log_efuse_map,
adapter->hw_info->log_efuse_size);
efuse_param->log_efuse_map = (u8 *)NULL;
}
if (efuse_param->bt_log_efuse_map) {
PLTFM_FREE(efuse_param->bt_log_efuse_map,
adapter->hw_info->bt_log_efuse_size);
efuse_param->bt_log_efuse_map = (u8 *)NULL;
}
if (efuse_param->dav_efuse_map) {
PLTFM_FREE(efuse_param->dav_efuse_map,
adapter->hw_info->dav_efuse_size);
efuse_param->dav_efuse_map = (u8 *)NULL;
}
if (efuse_param->dav_log_efuse_map) {
PLTFM_FREE(efuse_param->dav_log_efuse_map,
adapter->hw_info->dav_log_efuse_size);
efuse_param->dav_log_efuse_map = (u8 *)NULL;
}
PLTFM_FREE(adapter->hw_info, sizeof(struct mac_ax_hw_info));
PLTFM_FREE(adapter, sizeof(struct mac_ax_adapter));
return MACSUCCESS;
}
u32 is_chip_id(struct mac_ax_adapter *adapter, enum mac_ax_chip_id id)
{
return (id == adapter->hw_info->chip_id ? 1 : 0);
}
u32 is_cv(struct mac_ax_adapter *adapter, enum rtw_cv cv)
{
return (cv == adapter->hw_info->cv ? 1 : 0);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax.c
|
C
|
agpl-3.0
| 13,197
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_H_
#define _MAC_AX_H_
#include "mac_def.h"
#include "mac_ax/fwcmd.h"
#include "mac_ax/security_cam.h"
#include "mac_ax/efuse.h"
#include "mac_ax/p2p.h"
#if MAC_AX_SDIO_SUPPORT
#include "mac_ax/_sdio.h"
#endif
#if MAC_AX_FEATURE_HV
#include "hv_ax/init_hv.h"
#include "hv_ax/fwcmd_hv.h"
#endif
#if MAC_AX_FEATURE_HV
#include "hv_type.h"
#endif
#define MAC_AX_MAJOR_VER 0 /*Software Architcture Modify*/
#define MAC_AX_PROTOTYPE_VER 25 /*New Feature;Regular Release*/
#define MAC_AX_SUB_VER 34 /*for bug fix*/
#define MAC_AX_SUB_INDEX 0 /*for special used*/
#define MAC_AX_SRC_VER(a, b, c, d) \
(((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
#ifdef CONFIG_NEW_HALMAC_INTERFACE
/**
* @brief mac_ax_ops_init_v1
*
* @param *phl_adapter
* @param *drv_adapter
* @param chip_id
* @param hci
* @param **mac_adapter
* @param **mac_ops
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ax_ops_init_v1(void *phl_adapter, void *drv_adapter,
enum rtw_chip_id chip_id,
enum rtw_hci_type hci,
struct mac_ax_adapter **mac_adapter,
struct mac_ax_ops **mac_ops);
/**
* @brief mac_ax_ops_init
*
* @param *drv_adapter
* @param *pltfm_cb
* @param intf
* @param **mac_adapter
* @param **mac_ops
* @return Please Place Description here.
* @retval u32
*/
#else
u32 mac_ax_ops_init(void *drv_adapter, struct mac_ax_pltfm_cb *pltfm_cb,
enum mac_ax_intf intf,
struct mac_ax_adapter **mac_adapter,
struct mac_ax_ops **mac_ops);
/**
* @brief mac_ax_phl_init
*
* @param *phl_adapter
* @param *mac_adapter
* @return Please Place Description here.
* @retval u32
*/
#endif
#if MAC_AX_PHL_H2C
u32 mac_ax_phl_init(void *phl_adapter, struct mac_ax_adapter *mac_adapter);
/**
* @brief mac_ax_ops_exit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
#endif
u32 mac_ax_ops_exit(struct mac_ax_adapter *adapter);
/**
* @brief is_chip_id
*
* @param *adapter
* @param id
* @return Please Place Description here.
* @retval u32
*/
u32 is_chip_id(struct mac_ax_adapter *adapter, enum mac_ax_chip_id id);
/**
* @brief is_cv
*
* @param *adapter
* @param rtw_cv cv
* @return Please Place Description here.
* @retval u32
*/
u32 is_cv(struct mac_ax_adapter *adapter, enum rtw_cv cv);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax.h
|
C
|
agpl-3.0
| 3,053
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_MAC_DEF_H_
#define _MAC_AX_MAC_DEF_H_
#include "pltfm_cfg.h"
#include "feature_cfg.h"
#include "chip_cfg.h"
#include "mac_ax/state_mach.h"
#include "errors.h"
#if MAC_AX_FEATURE_HV
#include "hv_type.h"
#endif
/*--------------------Define -------------------------------------------*/
#ifdef CONFIG_NEW_HALMAC_INTERFACE
#define PLTFM_SDIO_CMD52_R8(addr) \
hal_sdio_cmd52_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R8(addr) \
hal_sdio_cmd53_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R16(addr) \
hal_sdio_cmd53_r16(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R32(addr) \
hal_sdio_cmd53_r32(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_RN(addr, size, val) \
hal_sdio_cmd53_rn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD52_W8(addr, val) \
hal_sdio_cmd52_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W8(addr, val) \
hal_sdio_cmd53_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_WN(addr, size, val) \
hal_sdio_cmd53_wn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD53_W16(addr, val) \
hal_sdio_cmd53_w16(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W32(addr, val) \
hal_sdio_cmd53_w32(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD52_CIA_R8(addr) \
hal_sdio_read_cia_r8(adapter->drv_adapter, addr)
#define PLTFM_TX(buf, len) \
hal_tx(adapter->drv_adapter, buf, len)
#define PLTFM_FREE(buf, size) \
hal_mem_free(adapter->drv_adapter, buf, size)
#define PLTFM_MALLOC(size) \
hal_mem_alloc(adapter->drv_adapter, size)
#define PLTFM_MEMCPY(dest, src, size) \
hal_mem_cpy(adapter->drv_adapter, dest, src, size)
#define PLTFM_MEMSET(addr, value, size) \
hal_mem_set(adapter->drv_adapter, addr, value, size)
#define PLTFM_MEMCMP(ptr1, ptr2, num) \
hal_mem_cmp(adapter->drv_adapter, ptr1, ptr2, num)
#define PLTFM_DELAY_US(us) \
hal_udelay(adapter->drv_adapter, us)
#define PLTFM_DELAY_MS(ms) \
hal_mdelay(adapter->drv_adapter, ms)
#define PLTFM_MUTEX_INIT(mutex) \
hal_mutex_init(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_DEINIT(mutex) \
hal_mutex_deinit(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_LOCK(mutex) \
hal_mutex_lock(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_UNLOCK(mutex) \
hal_mutex_unlock(adapter->drv_adapter, mutex)
#define PLTFM_MSG_PRINT(...) \
hal_mac_msg_print(drv_adapter, __VA_ARGS__)
#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops))
#define adapter_to_intf_ops(adapter) \
((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops))
#define PLTFM_REG_R8(addr) \
hal_read8(adapter->drv_adapter, addr)
#define PLTFM_REG_R16(addr) \
hal_read16(adapter->drv_adapter, addr)
#define PLTFM_REG_R32(addr) \
hal_read32(adapter->drv_adapter, addr)
#define PLTFM_REG_W8(addr, val) \
hal_write8(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W16(addr, val) \
hal_write16(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W32(addr, val) \
hal_write32(adapter->drv_adapter, addr, val)
#define MAC_REG_R8(addr) hal_read8(adapter->drv_adapter, addr)
#define MAC_REG_R16(addr) hal_read16(adapter->drv_adapter, addr)
#define MAC_REG_R32(addr) hal_read32(adapter->drv_adapter, addr)
#define MAC_REG_W8(addr, val) hal_write8(adapter->drv_adapter, addr, val)
#define MAC_REG_W16(addr, val) hal_write16(adapter->drv_adapter, addr, val)
#define MAC_REG_W32(addr, val) hal_write32(adapter->drv_adapter, addr, val)
#if MAC_AX_FEATURE_DBGCMD
#define PLTFM_SNPRINTF(s, sz, fmt, ...) \
hal_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__)
#define PLTFM_STRCMP(s1, s2) \
hal_strcmp(adapter->drv_adapter, s1, s2)
#define PLTFM_STRSEP(s, ct) \
hal_strsep(adapter->drv_adapter, s, ct)
#define PLTFM_STRLEN(s) \
hal_strlen(adapter->drv_adapter, s)
#define PLTFM_STRCPY(dest, src) \
hal_strcpy(adapter->drv_adapter, dest, src)
#define PLTFM_STRPBRK(cs, ct) \
hal_strpbrk(adapter->drv_adapter, cs, ct)
#define PLTFM_STRTOUL(buf, base) \
hal_strtoul(adapter->drv_adapter, buf, base)
#endif
#else
/* platform callback */
#define PLTFM_SDIO_CMD52_R8(addr) \
adapter->pltfm_cb->sdio_cmd52_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R8(addr) \
adapter->pltfm_cb->sdio_cmd53_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R16(addr) \
adapter->pltfm_cb->sdio_cmd53_r16(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R32(addr) \
adapter->pltfm_cb->sdio_cmd53_r32(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_RN(addr, size, val) \
adapter->pltfm_cb->sdio_cmd53_rn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD52_W8(addr, val) \
adapter->pltfm_cb->sdio_cmd52_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W8(addr, val) \
adapter->pltfm_cb->sdio_cmd53_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W16(addr, val) \
adapter->pltfm_cb->sdio_cmd53_w16(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W32(addr, val) \
adapter->pltfm_cb->sdio_cmd53_w32(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_WN(addr, size, val) \
adapter->pltfm_cb->sdio_cmd53_wn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD52_CIA_R8(addr) \
adapter->pltfm_cb->sdio_cmd52_cia_r8(adapter->drv_adapter, addr)
#define PLTFM_REG_R8(addr) \
adapter->pltfm_cb->reg_r8(adapter->drv_adapter, addr)
#define PLTFM_REG_R16(addr) \
adapter->pltfm_cb->reg_r16(adapter->drv_adapter, addr)
#define PLTFM_REG_R32(addr) \
adapter->pltfm_cb->reg_r32(adapter->drv_adapter, addr)
#define PLTFM_REG_W8(addr, val) \
adapter->pltfm_cb->reg_w8(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W16(addr, val) \
adapter->pltfm_cb->reg_w16(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W32(addr, val) \
adapter->pltfm_cb->reg_w32(adapter->drv_adapter, addr, val)
#if MAC_AX_PHL_H2C
#define PLTFM_TX(buf) \
adapter->pltfm_cb->tx(adapter->phl_adapter, adapter->drv_adapter, buf)
#define PLTFM_QUERY_H2C(type) \
adapter->pltfm_cb->rtl_query_h2c(adapter->phl_adapter, \
adapter->drv_adapter, type)
#define PLTFM_RECYCLE_H2C(buf) \
adapter->pltfm_cb->rtl_recycle_h2c(adapter->phl_adapter, buf)
#else
#define PLTFM_TX(buf, len) \
adapter->pltfm_cb->tx(adapter->drv_adapter, buf, len)
#endif
#define PLTFM_FREE(buf, size) \
adapter->pltfm_cb->rtl_free(adapter->drv_adapter, buf, size)
#define PLTFM_MALLOC(size) \
adapter->pltfm_cb->rtl_malloc(adapter->drv_adapter, size)
#define PLTFM_MEMCPY(dest, src, size) \
adapter->pltfm_cb->rtl_memcpy(adapter->drv_adapter, dest, src, size)
#define PLTFM_MEMSET(addr, value, size) \
adapter->pltfm_cb->rtl_memset(adapter->drv_adapter, addr, value, size)
#define PLTFM_MEMCMP(ptr1, ptr2, num) \
adapter->pltfm_cb->rtl_memcmp(adapter->drv_adapter, ptr1, ptr2, num)
#define PLTFM_DELAY_US(us) \
adapter->pltfm_cb->rtl_delay_us(adapter->drv_adapter, us)
#define PLTFM_DELAY_MS(ms) \
adapter->pltfm_cb->rtl_delay_ms(adapter->drv_adapter, ms)
#define PLTFM_MUTEX_INIT(mutex) \
adapter->pltfm_cb->rtl_mutex_init(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_DEINIT(mutex) \
adapter->pltfm_cb->rtl_mutex_deinit(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_LOCK(mutex) \
adapter->pltfm_cb->rtl_mutex_lock(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_UNLOCK(mutex) \
adapter->pltfm_cb->rtl_mutex_unlock(adapter->drv_adapter, mutex)
#define PLTFM_EVENT_NOTIFY(mac_ft, stat, buf, size) \
adapter->pltfm_cb->event_notify(adapter->drv_adapter, mac_ft, stat, \
buf, size)
#define PLTFM_L2_NOTIFY(void) \
adapter->pltfm_cb->ser_l2_notify(adapter->phl_adapter, adapter->drv_adapter)
#define PLTFM_LD_FW_SYMBOL(name, buf, buf_size) \
adapter->pltfm_cb->ld_fw_symbol(adapter->phl_adapter, adapter->drv_adapter,\
name, buf, buf_size)
#define PLTFM_MSG_PRINT(...) \
adapter->pltfm_cb->msg_print(drv_adapter, u8 dbg_level, __VA_ARGS__)
#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops))
#define adapter_to_intf_ops(adapter) \
((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops))
#define MAC_REG_R8(addr) ops->reg_read8(adapter, addr)
#define MAC_REG_R16(addr) ops->reg_read16(adapter, addr)
#define MAC_REG_R32(addr) ops->reg_read32(adapter, addr)
#define MAC_REG_W8(addr, val) ops->reg_write8(adapter, addr, val)
#define MAC_REG_W16(addr, val) ops->reg_write16(adapter, addr, val)
#define MAC_REG_W32(addr, val) ops->reg_write32(adapter, addr, val)
#if MAC_AX_FEATURE_DBGCMD
#define PLTFM_SNPRINTF(s, sz, fmt, ...) \
adapter->pltfm_cb->rtl_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__)
#define PLTFM_STRCMP(s1, s2) \
adapter->pltfm_cb->rtl_strcmp(adapter->drv_adapter, s1, s2)
#define PLTFM_STRSEP(s, ct) \
adapter->pltfm_cb->rtl_strsep(adapter->drv_adapter, s, ct)
#define PLTFM_STRLEN(s) \
adapter->pltfm_cb->rtl_strlen(adapter->drv_adapter, s)
#define PLTFM_STRCPY(dest, src) \
adapter->pltfm_cb->rtl_strcpy(adapter->drv_adapter, dest, src)
#define PLTFM_STRPBRK(cs, ct) \
adapter->pltfm_cb->rtl_strpbrk(adapter->drv_adapter, cs, ct)
#define PLTFM_STRTOUL(buf, base) \
adapter->pltfm_cb->rtl_strtoul(adapter->drv_adapter, buf, base)
#endif
#endif /*CONFIG_NEW_HALMAC_INTERFACE*/
/*--------------------Define MACRO--------------------------------------*/
#define MAC_AX_MAX_RU_NUM 4
#define WLAN_ADDR_LEN 6
#define MAX_VHT_SUPPORT_SOUND_STA 4
#define MAX_HE_SUPPORT_SOUND_STA 8
#define MAC_AX_BCN_INTERVAL_DEFAULT 100
#define MAC_RX_USB_AGG_MODE_UNIT 4096
#define MAC_RX_DMA_AGG_MODE_UNIT 1024
#define MAC_MAX_ARGC 20
#define MAC_MAX_ARGV 16
#define MAC_AX_DP_SEL_NUM 2
#ifdef PHL_FEATURE_AP
#define MAC_STA_NUM 128
#else /*for NIC mode setting*/
#define MAC_STA_NUM 32
#endif
#define MAC_AX_FAST_CH_SW_MAX_STA_NUM 4
#define UL_PER_STA_DBGINFO_NUM 0x10
/*--------------------Define Enum---------------------------------------*/
/**
* @enum mac_ax_intf
*
* @brief mac_ax_intf
*
* @var mac_ax_intf::MAC_AX_INTF_USB
* Please Place Description here.
* @var mac_ax_intf::MAC_AX_INTF_SDIO
* Please Place Description here.
* @var mac_ax_intf::MAC_AX_INTF_PCIE
* Please Place Description here.
* @var mac_ax_intf::MAC_AX_INTF_LAST
* Please Place Description here.
* @var mac_ax_intf::MAC_AX_INTF_MAX
* Please Place Description here.
* @var mac_ax_intf::MAC_AX_INTF_INVALID
* Please Place Description here.
*/
enum mac_ax_intf {
MAC_AX_INTF_USB,
MAC_AX_INTF_SDIO,
MAC_AX_INTF_PCIE,
/* keep last */
MAC_AX_INTF_LAST,
MAC_AX_INTF_MAX = MAC_AX_INTF_LAST,
MAC_AX_INTF_INVALID = MAC_AX_INTF_LAST,
};
/**
* @enum mac_ax_feature
*
* @brief mac_ax_feature
*
* @var mac_ax_feature::MAC_AX_FT_DUMP_EFUSE
* Please Place Description here.
* @var mac_ax_feature::MAC_AX_FT_LAST
* Please Place Description here.
* @var mac_ax_feature::MAC_AX_FT_MAX
* Please Place Description here.
* @var mac_ax_feature::MAC_AX_FT_INVALID
* Please Place Description here.
*/
enum mac_ax_feature {
MAC_AX_FT_DUMP_EFUSE,
/* keep last */
MAC_AX_FT_LAST,
MAC_AX_FT_MAX = MAC_AX_FT_LAST,
MAC_AX_FT_INVALID = MAC_AX_FT_LAST,
};
/**
* @enum mac_ax_status
*
* @brief mac_ax_status
*
* @var mac_ax_status::MAC_AX_STATUS_IDLE
* Please Place Description here.
* @var mac_ax_status::MAC_AX_STATUS_PROC
* Please Place Description here.
* @var mac_ax_status::MAC_AX_STATUS_DONE
* Please Place Description here.
* @var mac_ax_status::MAC_AX_STATUS_ERR
* Please Place Description here.
*/
enum mac_ax_status {
MAC_AX_STATUS_IDLE,
MAC_AX_STATUS_PROC,
MAC_AX_STATUS_DONE,
MAC_AX_STATUS_ERR,
};
/**
* @enum mac_ax_sdio_4byte_mode
*
* @brief mac_ax_sdio_4byte_mode
*
* @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_DISABLE
* Please Place Description here.
* @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_RW
* Please Place Description here.
* @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_LAST
* Please Place Description here.
* @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_MAX
* Please Place Description here.
* @var mac_ax_sdio_4byte_mode::MAC_AX_SDIO_4BYTE_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_sdio_4byte_mode {
MAC_AX_SDIO_4BYTE_MODE_DISABLE,
MAC_AX_SDIO_4BYTE_MODE_RW,
/* keep last */
MAC_AX_SDIO_4BYTE_MODE_LAST,
MAC_AX_SDIO_4BYTE_MODE_MAX = MAC_AX_SDIO_4BYTE_MODE_LAST,
MAC_AX_SDIO_4BYTE_MODE_INVALID = MAC_AX_SDIO_4BYTE_MODE_LAST,
};
/**
* @enum mac_ax_sdio_tx_mode
*
* @brief mac_ax_sdio_tx_mode
*
* @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_AGG
* Please Place Description here.
* @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_DUMMY_BLOCK
* Please Place Description here.
* @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_DUMMY_AUTO
* Please Place Description here.
* @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_LAST
* Please Place Description here.
* @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_MAX
* Please Place Description here.
* @var mac_ax_sdio_tx_mode::MAC_AX_SDIO_TX_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_sdio_tx_mode {
MAC_AX_SDIO_TX_MODE_AGG,
MAC_AX_SDIO_TX_MODE_DUMMY_BLOCK,
MAC_AX_SDIO_TX_MODE_DUMMY_AUTO,
/* keep last */
MAC_AX_SDIO_TX_MODE_LAST,
MAC_AX_SDIO_TX_MODE_MAX = MAC_AX_SDIO_TX_MODE_LAST,
MAC_AX_SDIO_TX_MODE_INVALID = MAC_AX_SDIO_TX_MODE_LAST,
};
/**
* @enum mac_ax_sdio_opn_mode
*
* @brief mac_ax_sdio_opn_mode
*
* @var mac_ax_sdio_opn_mode::MAC_AX_SDIO_OPN_MODE_BYTE
* Please Place Description here.
* @var mac_ax_sdio_opn_mode::MAC_AX_SDIO_OPN_MODE_BLOCK
* Please Place Description here.
* @var mac_ax_sdio_opn_mode::MAC_AX_SDIO_OPN_MODE_UNKNOWN
* Please Place Description here.
*/
enum mac_ax_sdio_opn_mode {
MAC_AX_SDIO_OPN_MODE_BYTE = 0,
MAC_AX_SDIO_OPN_MODE_BLOCK,
MAC_AX_SDIO_OPN_MODE_UNKNOWN,
};
/**
* @enum mac_ax_sdio_spec_ver
*
* @brief mac_ax_sdio_spec_ver
*
* @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_2_00
* Please Place Description here.
* @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_3_00
* Please Place Description here.
* @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_LAST
* Please Place Description here.
* @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_MAX
* Please Place Description here.
* @var mac_ax_sdio_spec_ver::MAC_AX_SDIO_SPEC_VER_INVALID
* Please Place Description here.
*/
enum mac_ax_sdio_spec_ver {
MAC_AX_SDIO_SPEC_VER_2_00,
MAC_AX_SDIO_SPEC_VER_3_00,
/* keep last */
MAC_AX_SDIO_SPEC_VER_LAST,
MAC_AX_SDIO_SPEC_VER_MAX = MAC_AX_SDIO_SPEC_VER_LAST,
MAC_AX_SDIO_SPEC_VER_INVALID = MAC_AX_SDIO_SPEC_VER_LAST,
};
/**
* @enum mac_ax_use_ver
*
* @brief mac_ax_use_ver
*
* @var mac_ax_use_ver::MAC_AX_USB11
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB2
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB3
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_LAST
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_MAX
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_INVALID
* Please Place Description here.
*/
enum mac_ax_use_ver {
MAC_AX_USB10,
MAC_AX_USB11,
MAC_AX_USB2,
MAC_AX_USB3,
MAC_AX_USB_LAST,
MAC_AX_USB_MAX = MAC_AX_USB_LAST,
MAC_AX_USB_INVALID = MAC_AX_USB_LAST,
};
/**
* @enum mac_ax_use_mode
*
* @brief mac_ax_use_mode
*
* @var mac_ax_use_ver::MAC_AX_USB_NORM
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_AUTOINSTALL
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_LAST
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_MAX
* Please Place Description here.
* @var mac_ax_use_ver::MAC_AX_USB_INVALID
* Please Place Description here.
*/
enum mac_ax_use_mode {
MAC_AX_USB_NORM,
MAC_AX_USB_AUTOINSTALL,
MAC_AX_USB_MODE_LAST,
MAC_AX_USB_MODE_MAX = MAC_AX_USB_LAST,
MAC_AX_USB_MODE_INVALID = MAC_AX_USB_LAST,
};
/**
* @enum mac_ax_lv1_rcvy_step
*
* @brief mac_ax_lv1_rcvy_step
*
* @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_1
* Please Place Description here.
* @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_2
* Please Place Description here.
* @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_LAST
* Please Place Description here.
* @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_MAX
* Please Place Description here.
* @var mac_ax_lv1_rcvy_step::MAC_AX_LV1_RCVY_STEP_INVALID
* Please Place Description here.
*/
enum mac_ax_lv1_rcvy_step {
MAC_AX_LV1_RCVY_STEP_1 = 0,
MAC_AX_LV1_RCVY_STEP_2,
/* keep last */
MAC_AX_LV1_RCVY_STEP_LAST,
MAC_AX_LV1_RCVY_STEP_MAX = MAC_AX_LV1_RCVY_STEP_LAST,
MAC_AX_LV1_RCVY_STEP_INVALID = MAC_AX_LV1_RCVY_STEP_LAST,
};
/**
* @enum mac_ax_ex_shift
*
* @brief mac_ax_ex_shift
*
* @var mac_ax_ex_shift::MAC_AX_NO_SHIFT
* Please Place Description here.
* @var mac_ax_ex_shift::MAC_AX_BYTE_ALIGNED_4
* Please Place Description here.
* @var mac_ax_ex_shift::MAC_AX_BYTE_ALIGNED_8
* Please Place Description here.
*/
enum mac_ax_ex_shift {
MAC_AX_NO_SHIFT = 0,
MAC_AX_BYTE_ALIGNED_4 = 1,
MAC_AX_BYTE_ALIGNED_8 = 2
};
/**
* @enum mac_ax_ps_mode
*
* @brief mac_ax_ps_mode
*
* @var mac_ax_ps_mode::MAC_AX_PS_MODE_ACTIVE
* Please Place Description here.
* @var mac_ax_ps_mode::MAC_AX_PS_MODE_LEGACY
* Please Place Description here.
* @var mac_ax_ps_mode::MAC_AX_PS_MODE_WMMPS
* Please Place Description here.
* @var mac_ax_ps_mode::MAC_AX_PS_MODE_MAX
* Please Place Description here.
*/
enum mac_ax_ps_mode {
MAC_AX_PS_MODE_ACTIVE = 0,
MAC_AX_PS_MODE_LEGACY = 1,
MAC_AX_PS_MODE_WMMPS = 2,
MAC_AX_PS_MODE_MAX = 3,
};
/**
* @enum mac_ax_pwr_state_action
*
* @brief mac_ax_pwr_state_action
*
* @var mac_ax_pwr_state_action::MAC_AX_PWR_STATE_ACT_REQ
* Please Place Description here.
* @var mac_ax_pwr_state_action::MAC_AX_PWR_STATE_ACT_CHK
* Please Place Description here.
* @var mac_ax_pwr_state_action::MAC_AX_PWR_STATE_ACT_MAX
* Please Place Description here.
*/
enum mac_ax_pwr_state_action {
MAC_AX_PWR_STATE_ACT_REQ = 0,
MAC_AX_PWR_STATE_ACT_CHK = 1,
MAC_AX_PWR_STATE_ACT_MAX,
};
/**
* @enum mac_ax_rpwm_req_pwr_state
*
* @brief mac_ax_rpwm_req_pwr_state
*
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFON
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFON
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFOFF
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFOFF
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED
* Please Place Description here.
* @var mac_ax_rpwm_req_pwr_state::MAC_AX_RPWM_REQ_PWR_STATE_MAX
* Please Place Description here.
*/
enum mac_ax_rpwm_req_pwr_state {
MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE = 0,
MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
MAC_AX_RPWM_REQ_PWR_STATE_MAX,
};
/**
* @enum mac_ax_port_cfg_type
*
* @brief mac_ax_port_cfg_type
*
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_FUNC_SW
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_TX_SW
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_TX_RPT
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_RX_SW
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_RX_RPT
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_RX_SYNC
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_PRCT
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_TBTT_AGG
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_TBTT_SHIFT
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_RST_TSF
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_RST_TPR
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCAID
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_HIQ_WIN
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_HIQ_DTIM
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_HIQ_NOLIMIT
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_NET_TYPE
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_INTV
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_SETUP_TIME
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_HOLD_TIME
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_MBSSID_EN
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_ERLY
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_MASK_AREA
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_TBTT_ERLY
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BSS_CLR
* Please Place Description here.
* @var mac_ax_port_cfg_type::MAC_AX_PCFG_BCN_DRP_ALL
* Please Place Description here.
*/
enum mac_ax_port_cfg_type {
MAC_AX_PCFG_FUNC_SW = 0,
MAC_AX_PCFG_TX_SW,
MAC_AX_PCFG_TX_RPT,
MAC_AX_PCFG_RX_SW,
MAC_AX_PCFG_RX_RPT,
MAC_AX_PCFG_RX_SYNC,
MAC_AX_PCFG_BCN_PRCT,
MAC_AX_PCFG_TBTT_AGG,
MAC_AX_PCFG_TBTT_SHIFT,
MAC_AX_PCFG_RST_TSF,
MAC_AX_PCFG_RST_TPR,
MAC_AX_PCFG_BCAID,
MAC_AX_PCFG_HIQ_WIN,
MAC_AX_PCFG_HIQ_DTIM,
MAC_AX_PCFG_HIQ_NOLIMIT,
MAC_AX_PCFG_NET_TYPE,
MAC_AX_PCFG_BCN_INTV,
MAC_AX_PCFG_BCN_SETUP_TIME,
MAC_AX_PCFG_BCN_HOLD_TIME,
MAC_AX_PCFG_MBSSID_EN,
MAC_AX_PCFG_BCN_ERLY,
MAC_AX_PCFG_BCN_MASK_AREA,
MAC_AX_PCFG_TBTT_ERLY,
MAC_AX_PCFG_BSS_CLR,
MAC_AX_PCFG_MBSSID_NUM,
MAC_AX_PCFG_BCN_DRP_ALL,
};
/**
* @enum mac_ax_band
*
* @brief mac_ax_band
*
* @var mac_ax_band::MAC_AX_BAND_0
* Please Place Description here.
* @var mac_ax_band::MAC_AX_BAND_1
* Please Place Description here.
* @var mac_ax_band::MAC_AX_BAND_NUM
* Please Place Description here.
*/
enum mac_ax_band {
MAC_AX_BAND_0 = 0,
MAC_AX_BAND_1 = 1,
MAC_AX_BAND_NUM = 2
};
/**
* @enum mac_ax_port
*
* @brief mac_ax_port
*
* @var mac_ax_port::MAC_AX_PORT_0
* Please Place Description here.
* @var mac_ax_port::MAC_AX_PORT_1
* Please Place Description here.
* @var mac_ax_port::MAC_AX_PORT_2
* Please Place Description here.
* @var mac_ax_port::MAC_AX_PORT_3
* Please Place Description here.
* @var mac_ax_port::MAC_AX_PORT_4
* Please Place Description here.
* @var mac_ax_port::MAC_AX_PORT_NUM
* Please Place Description here.
*/
enum mac_ax_port {
MAC_AX_PORT_0 = 0,
MAC_AX_PORT_1 = 1,
MAC_AX_PORT_2 = 2,
MAC_AX_PORT_3 = 3,
MAC_AX_PORT_4 = 4,
MAC_AX_PORT_NUM
};
/**
* @enum mac_ax_addr_msk_sel
*
* @brief mac_ax_addr_msk_sel
*
* @var mac_ax_addr_msk_sel::MAC_AX_NO_MSK
* Please Place Description here.
* @var mac_ax_addr_msk_sel::MAC_AX_SMA_MSK
* Please Place Description here.
* @var mac_ax_addr_msk_sel::MAC_AX_TMA_MSK
* Please Place Description here.
* @var mac_ax_addr_msk_sel::MAC_AX_BSSID_MSK
* Please Place Description here.
*/
enum mac_ax_addr_msk_sel {
MAC_AX_NO_MSK,
MAC_AX_SMA_MSK,
MAC_AX_TMA_MSK,
MAC_AX_BSSID_MSK
};
/**
* @enum mac_ax_addr_msk
*
* @brief mac_ax_addr_msk
*
* @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE5
* Please Place Description here.
* @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE4
* Please Place Description here.
* @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE3
* Please Place Description here.
* @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE2
* Please Place Description here.
* @var mac_ax_addr_msk::MAC_AX_MASK_BYTE5_TO_BYTE1
* Please Place Description here.
*/
enum mac_ax_addr_msk {
MAC_AX_MSK_NONE = 0x3f,
MAC_AX_BYTE5 = 0x1f,
MAC_AX_BYTE5_TO_BYTE4 = 0xf,
MAC_AX_BYTE5_TO_BYTE3 = 0x7,
MAC_AX_BYTE5_TO_BYTE2 = 0x3,
MAC_AX_BYTE5_TO_BYTE1 = 0x1,
MAC_AX_MSK_ALL = 0x0
};
/**
* @enum mac_ax_mbssid_idx
*
* @brief mac_ax_mbssid_idx
*
* @var mac_ax_mbssid_idx::MAC_AX_P0_ROOT
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID1
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID2
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID3
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID4
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID5
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID6
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID7
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID8
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID9
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID10
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID11
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID12
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID13
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID14
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID15
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID_LAST
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID_MAX
* Please Place Description here.
* @var mac_ax_mbssid_idx::MAC_AX_P0_MBID_INVALID
* Please Place Description here.
*/
enum mac_ax_mbssid_idx {
MAC_AX_P0_ROOT = 0,
MAC_AX_P0_MBID1,
MAC_AX_P0_MBID2,
MAC_AX_P0_MBID3,
MAC_AX_P0_MBID4,
MAC_AX_P0_MBID5,
MAC_AX_P0_MBID6,
MAC_AX_P0_MBID7,
MAC_AX_P0_MBID8,
MAC_AX_P0_MBID9,
MAC_AX_P0_MBID10,
MAC_AX_P0_MBID11,
MAC_AX_P0_MBID12,
MAC_AX_P0_MBID13,
MAC_AX_P0_MBID14,
MAC_AX_P0_MBID15,
/* keep last */
MAC_AX_P0_MBID_LAST,
MAC_AX_P0_MBID_MAX = MAC_AX_P0_MBID_LAST,
MAC_AX_P0_MBID_INVALID = MAC_AX_P0_MBID_LAST,
};
/**
* @enum mac_ax_hwmod_sel
*
* @brief mac_ax_hwmod_sel
*
* @var mac_ax_hwmod_sel::MAC_AX_DMAC_SEL
* Please Place Description here.
* @var mac_ax_hwmod_sel::MAC_AX_CMAC_SEL
* Please Place Description here.
* @var mac_ax_hwmod_sel::MAC_AX_MAC_LAST
* Please Place Description here.
* @var mac_ax_hwmod_sel::MAC_AX_MAC_MAX
* Please Place Description here.
* @var mac_ax_hwmod_sel::MAC_AX_MAC_INVALID
* Please Place Description here.
*/
enum mac_ax_hwmod_sel {
MAC_AX_DMAC_SEL = 0,
MAC_AX_CMAC_SEL = 1,
/* keep last */
MAC_AX_MAC_LAST,
MAC_AX_MAC_MAX = MAC_AX_MAC_LAST,
MAC_AX_MAC_INVALID = MAC_AX_MAC_LAST,
};
/**
* @enum mac_ax_ss_wmm
*
* @brief mac_ax_ss_wmm
*
* @var mac_ax_ss_wmm::MAC_AX_SS_WMM0
* Please Place Description here.
* @var mac_ax_ss_wmm::MAC_AX_SS_WMM1
* Please Place Description here.
* @var mac_ax_ss_wmm::MAC_AX_SS_WMM2
* Please Place Description here.
* @var mac_ax_ss_wmm::MAC_AX_SS_WMM3
* Please Place Description here.
* @var mac_ax_ss_wmm::MAC_AX_SS_UL
* Please Place Description here.
*/
enum mac_ax_ss_wmm {
MAC_AX_SS_WMM0,
MAC_AX_SS_WMM1,
MAC_AX_SS_WMM2,
MAC_AX_SS_WMM3,
MAC_AX_SS_UL,
};
/**
* @enum mac_ax_ss_quota_mode
*
* @brief mac_ax_ss_quota_mode
*
* @var mac_ax_ss_quota_mode::MAC_AX_SS_QUOTA_MODE_TIME
* Please Place Description here.
* @var mac_ax_ss_quota_mode::MAC_AX_SS_QUOTA_MODE_CNT
* Please Place Description here.
*/
enum mac_ax_ss_quota_mode {
MAC_AX_SS_QUOTA_MODE_TIME = 0,
MAC_AX_SS_QUOTA_MODE_CNT = 1,
};
/**
* @enum mac_ax_issue_uldl_type
*
* @brief mac_ax_issue_uldl_type
*
* @var mac_ax_issue_uldl_type::mac_ax_issue_dl
* Please Place Description here.
* @var mac_ax_issue_uldl_type::mac_ax_issue_ul
* Please Place Description here.
*/
enum mac_ax_issue_uldl_type {
mac_ax_issue_dl = 0,
mac_ax_issue_ul = 1,
};
/**
* @enum mac_ax_hw_id
*
* @brief mac_ax_hw_id
*
* @var mac_ax_hw_id::MAC_AX_HW_MAPPING
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_INT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_CNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_TX_AGG_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_AMPDU_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_EDCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_EDCCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_MUEDCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_MUEDCA_TIMER
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_TBPPDU_CTRL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_MUEDCA_CTRL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_DELAYTX_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_SS_WMM_TBL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_EFUSE_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_BT_EFUSE_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_EFUSE_MASK_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_CH_STAT_CNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_LIFETIME_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_APP_FCS
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_RX_ICVERR
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_PWR_STATE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_WAKE_REASON
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_SCOREBOARD
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_COEX_GNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_RRSR
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_COEX_CTRL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_TX_CNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_TX_TF_INFO
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_TSF
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_MAX_TX_TIME
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_SS_QUOTA_MODE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_SS_QUOTA_SETTING
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_POLLUTED_CNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_DATA_RTY_LMT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_DFLT_NAV
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_GET_BACAM_MODE_SEL
* To get the BACAM option mode.
* @var mac_ax_hw_id::MAC_AX_HW_GET_RRSR_CFG
* for Get Response rate cfg
* @var mac_ax_hw_id::MAC_AX_HW_GET_CTS_RRSR_CFG
* for Get CTS Response rate cfg
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_INFO
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_TX_MODE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_RX_AGG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_TX_AGG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_AVAL_PAGE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_WT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SDIO_MON_CLK
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_PCIE_CFGSPC_SET
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_PCIE_RST_BDRAM
* Please Place Description here.
* @var mac_ax_hw_id::MAX_AX_HW_PCIE_LTR_SW_TRIGGER
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_ID_PAUSE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_AMPDU_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_USR_EDCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_EDCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_EDCCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_MUEDCA_PARAM
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_TBPPDU_CTRL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_SCH_TXEN_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_HOST_RPR
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_MUEDCA_CTRL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_DELAYTX_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_BW_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_BT_BLOCK_TX
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_LIFETIME_CFG
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_EN_BB_RF
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_APP_FCS
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_RX_ICVERR
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_CCTL_RTY_LMT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_COEX_GNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_SCOREBOARD
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_POLLUTED
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_COEX_CTRL
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_CLR_TX_CNT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_SLOT_TIME
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_XTAL_AAC_MODE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_NAV_PADDING
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_MAX_TX_TIME
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_SS_QUOTA_MODE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_SS_QUOTA_SETTING
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_TX_RU26_TB
* To enable or disable responding TB in RU26
* @var mac_ax_hw_id::MAC_AX_HW_SET_BACAM_MODE_SEL
* To change the BACAM option mode
* @var mac_ax_hw_id::MAC_AX_HW_SET_CORE_SWR_VOLT
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_PARTIAL_PLD_MODE
* Please Place Description here.
* @var mac_ax_hw_id::MAC_AX_HW_SET_RRSR_CFG
* for Response rate cfg
* @var mac_ax_hw_id::MAC_AX_HW_SET_CTS_RRSR_CFG
* for CTS Response rate cfg
*/
enum mac_ax_hw_id {
/* Get HW value */
MAC_AX_HW_MAPPING = 0x00,
MAC_AX_HW_SDIO_MON_INT,
MAC_AX_HW_SDIO_MON_CNT,
MAC_AX_HW_GET_ID_PAUSE,
MAC_AX_HW_SDIO_TX_AGG_SIZE,
MAC_AX_HW_GET_EDCA_PARAM,
MAC_AX_HW_GET_TBPPDU_CTRL,
MAC_AX_HW_GET_SCH_TXEN_STATUS,
MAC_AX_HW_GET_DELAYTX_CFG,
MAC_AX_HW_GET_SS_WMM_TBL,
MAC_AX_HW_GET_EFUSE_SIZE,
MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE,
MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE,
MAC_AX_HW_GET_BT_EFUSE_SIZE,
MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE,
MAC_AX_HW_GET_EFUSE_MASK_SIZE,
MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE,
MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE,
MAC_AX_HW_GET_EFUSE_VERSION_SIZE,
MAC_AX_HW_GET_CH_STAT_CNT,
MAC_AX_HW_GET_LIFETIME_CFG,
MAC_AX_HW_GET_APP_FCS,
MAC_AX_HW_GET_RX_ICVERR,
MAC_AX_HW_GET_PWR_STATE,
MAC_AX_HW_GET_WAKE_REASON,
MAC_AX_HW_GET_SCOREBOARD,
MAC_AX_HW_GET_COEX_GNT,
MAC_AX_HW_GET_COEX_CTRL,
MAC_AX_HW_GET_TX_CNT,
MAC_AX_HW_GET_TSF,
MAC_AX_HW_GET_MAX_TX_TIME,
MAC_AX_HW_GET_POLLUTED_CNT,
MAC_AX_HW_GET_DATA_RTY_LMT,
MAC_AX_HW_GET_DFLT_NAV,
MAC_AX_HW_GET_SCHE_PREBKF,
MAC_AX_HW_GET_FW_CAP,
MAC_AX_HW_GET_BACAM_MODE_SEL,
MAC_AX_HW_GET_RRSR_CFG,
MAC_AX_HW_GET_CTS_RRSR_CFG,
MAC_AX_HW_GET_USB_STS,
/* Set HW value */
MAC_AX_HW_SETTING = 0x60,
MAC_AX_HW_SDIO_INFO,
MAC_AX_HW_SDIO_TX_MODE,
MAC_AX_HW_SDIO_RX_AGG,
MAC_AX_HW_SDIO_TX_AGG,
MAC_AX_HW_SDIO_AVAL_PAGE,
MAC_AX_HW_SDIO_MON_WT,
MAC_AX_HW_SDIO_MON_CLK,
MAC_AX_HW_PCIE_CFGSPC_SET,
MAC_AX_HW_PCIE_RST_BDRAM,
MAX_AX_HW_PCIE_LTR_SW_TRIGGER,
MAX_AX_HW_PCIE_MIT,
MAX_AX_HW_PCIE_L2_LEAVE,
MAC_AX_HW_SET_ID_PAUSE,
MAC_AX_HW_SET_MULTI_ID_PAUSE,
MAC_AX_HW_SET_AMPDU_CFG,
MAC_AX_HW_SET_USR_EDCA_PARAM,
MAC_AX_HW_SET_USR_TX_RPT_CFG,
MAC_AX_HW_SET_EDCA_PARAM,
MAC_AX_HW_SET_EDCCA_PARAM,
MAC_AX_HW_SET_MUEDCA_PARAM,
MAC_AX_HW_SET_TBPPDU_CTRL,
MAC_AX_HW_SET_SCH_TXEN_CFG,
MAC_AX_HW_SET_HOST_RPR,
MAC_AX_HW_SET_MUEDCA_CTRL,
MAC_AX_HW_SET_DELAYTX_CFG,
MAC_AX_HW_SET_BW_CFG,
MAC_AX_HW_SET_CH_BUSY_STAT_CFG,
MAC_AX_HW_SET_LIFETIME_CFG,
MAC_AX_HW_EN_BB_RF,
MAC_AX_HW_SET_APP_FCS,
MAC_AX_HW_SET_RX_ICVERR,
MAC_AX_HW_SET_CCTL_RTY_LMT,
MAC_AX_HW_SET_COEX_GNT,
MAC_AX_HW_SET_SCOREBOARD,
MAC_AX_HW_SET_POLLUTED,
MAC_AX_HW_SET_COEX_CTRL,
MAC_AX_HW_SET_CLR_TX_CNT,
MAC_AX_HW_SET_SLOT_TIME,
MAC_AX_HW_SET_XTAL_AAC_MODE,
MAC_AX_HW_SET_NAV_PADDING,
MAC_AX_HW_SET_MAX_TX_TIME,
MAC_AX_HW_SET_SS_QUOTA_MODE,
MAC_AX_HW_SET_SS_QUOTA_SETTING,
MAC_AX_HW_SET_SCHE_PREBKF,
MAC_AX_HW_SET_WDT_ISR_RST,
MAC_AX_HW_SET_RESP_ACK,
MAC_AX_HW_SET_HW_RTS_TH,
MAC_AX_HW_SET_TX_RU26_TB,
MAC_AX_HW_SET_BACAM_MODE_SEL,
MAC_AX_HW_SET_CORE_SWR_VOLT,
MAC_AX_HW_SET_PARTIAL_PLD_MODE,
MAC_AX_HW_SET_RRSR_CFG,
MAC_AX_HW_SET_CTS_RRSR_CFG,
MAC_AX_HW_SET_GT3_TIMER,
};
/**
* @enum mac_ax_rx_agg_mode
*
* @brief mac_ax_rx_agg_mode
*
* @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_NONE
* Please Place Description here.
* @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_DMA
* Please Place Description here.
* @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_USB
* Please Place Description here.
* @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_LAST
* Please Place Description here.
* @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_MAX
* Please Place Description here.
* @var mac_ax_rx_agg_mode::MAC_AX_RX_AGG_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_rx_agg_mode {
MAC_AX_RX_AGG_MODE_NONE,
MAC_AX_RX_AGG_MODE_DMA,
MAC_AX_RX_AGG_MODE_USB,
/* keep last */
MAC_AX_RX_AGG_MODE_LAST,
MAC_AX_RX_AGG_MODE_MAX = MAC_AX_RX_AGG_MODE_LAST,
MAC_AX_RX_AGG_MODE_INVALID = MAC_AX_RX_AGG_MODE_LAST,
};
/**
* @enum mac_ax_usr_tx_rpt_mode
*
* @brief mac_ax_usr_tx_rpt_mode
*
* @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_DIS
* disable report
* @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_PERIOD
* period mode
* @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_LAST_PKT
* report after last packet Tx
*/
enum mac_ax_usr_tx_rpt_mode {
MAC_AX_USR_TX_RPT_DIS = 0,
MAC_AX_USR_TX_RPT_PERIOD = 1,
MAC_AX_USR_TX_RPT_LAST_PKT = 2,
};
/**
* @enum mac_ax_usr_tx_rpt_mode
*
* @brief mac_ax_usr_tx_rpt_mode
*
* @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_DIS
* disable report
* @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_PERIOD
* period mode
* @var mac_ax_usr_tx_rpt_mode::MAC_AX_USR_TX_RPT_LAST_PKT
* report after last packet Tx
*/
enum mac_ax_ofld_mode {
MAC_AX_OFLD_MODE_DU_DIS = 0,
MAC_AX_OFLD_MODE_DU_VAL = 1,
};
/**
* @enum mac_ax_cmac_ac_sel
*
* @brief mac_ax_cmac_ac_sel
*
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_BE
* Please Place Description here.
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_BK
* Please Place Description here.
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_VI
* Please Place Description here.
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_VO
* Please Place Description here.
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_LAST
* Please Place Description here.
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_MAX
* Please Place Description here.
* @var mac_ax_cmac_ac_sel::MAC_AX_CMAC_AC_SEL_INVALID
* Please Place Description here.
*/
enum mac_ax_cmac_ac_sel {
MAC_AX_CMAC_AC_SEL_BE = 0,
MAC_AX_CMAC_AC_SEL_BK = 1,
MAC_AX_CMAC_AC_SEL_VI = 2,
MAC_AX_CMAC_AC_SEL_VO = 3,
/* keep last */
MAC_AX_CMAC_AC_SEL_LAST,
MAC_AX_CMAC_AC_SEL_MAX = MAC_AX_CMAC_AC_SEL_LAST,
MAC_AX_CMAC_AC_SEL_INVALID = MAC_AX_CMAC_AC_SEL_LAST,
};
/**
* @enum mac_ax_cmac_path_sel
*
* @brief mac_ax_cmac_path_sel
*
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BE0
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BK0
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VI0
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VO0
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BE1
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BK1
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VI1
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_VO1
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_MG0_1
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_MG2
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_BCN
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_TF
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_TWT0
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_TWT1
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_LAST
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_MAX
* Please Place Description here.
* @var mac_ax_cmac_path_sel::MAC_AX_CMAC_PATH_SEL_INVALID
* Please Place Description here.
*/
enum mac_ax_cmac_path_sel {
MAC_AX_CMAC_PATH_SEL_BE0,
MAC_AX_CMAC_PATH_SEL_BK0,
MAC_AX_CMAC_PATH_SEL_VI0,
MAC_AX_CMAC_PATH_SEL_VO0,
MAC_AX_CMAC_PATH_SEL_BE1,
MAC_AX_CMAC_PATH_SEL_BK1,
MAC_AX_CMAC_PATH_SEL_VI1,
MAC_AX_CMAC_PATH_SEL_VO1,
MAC_AX_CMAC_PATH_SEL_MG0_1,
MAC_AX_CMAC_PATH_SEL_MG2,
MAC_AX_CMAC_PATH_SEL_BCN,
MAC_AX_CMAC_PATH_SEL_TF,
MAC_AX_CMAC_PATH_SEL_TWT0,
MAC_AX_CMAC_PATH_SEL_TWT1,
/* keep last */
MAC_AX_CMAC_PATH_SEL_LAST,
MAC_AX_CMAC_PATH_SEL_MAX = MAC_AX_CMAC_PATH_SEL_LAST,
MAC_AX_CMAC_PATH_SEL_INVALID = MAC_AX_CMAC_PATH_SEL_LAST,
};
/**
* @enum mac_ax_cmac_usr_edca_idx
*
* @brief mac_ax_cmac_usr_edca_idx
*
* @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_0
* Please Place Description here.
* @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_1
* Please Place Description here.
* @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_2
* Please Place Description here.
* @var mac_ax_cmac_usr_edca_idx::MAC_AX_CMAC_USR_EDCA_IDX_3
* Please Place Description here.
*/
enum mac_ax_cmac_usr_edca_idx {
MAC_AX_CMAC_USR_EDCA_IDX_0 = 0,
MAC_AX_CMAC_USR_EDCA_IDX_1 = 1,
MAC_AX_CMAC_USR_EDCA_IDX_2 = 2,
MAC_AX_CMAC_USR_EDCA_IDX_3 = 3,
};
/**
* @enum mac_ax_cmac_wmm_sel
*
* @brief mac_ax_cmac_wmm_sel
*
* @var mac_ax_cmac_wmm_sel::MAC_AX_CMAC_WMM0_SEL
* Please Place Description here.
* @var mac_ax_cmac_wmm_sel::MAC_AX_CMAC_WMM1_SEL
* Please Place Description here.
*/
enum mac_ax_cmac_wmm_sel {
MAC_AX_CMAC_WMM0_SEL = 0,
MAC_AX_CMAC_WMM1_SEL = 1,
};
/**
* @enum mac_ax_ss_wmm_tbl
*
* @brief mac_ax_ss_wmm_tbl
*
* @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C0_WMM0
* Please Place Description here.
* @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C0_WMM1
* Please Place Description here.
* @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C1_WMM0
* Please Place Description here.
* @var mac_ax_ss_wmm_tbl::MAC_AX_SS_WMM_TBL_C1_WMM1
* Please Place Description here.
*/
enum mac_ax_ss_wmm_tbl {
MAC_AX_SS_WMM_TBL_C0_WMM0 = 0,
MAC_AX_SS_WMM_TBL_C0_WMM1 = 1,
MAC_AX_SS_WMM_TBL_C1_WMM0 = 2,
MAC_AX_SS_WMM_TBL_C1_WMM1 = 3,
};
enum mac_ax_tx_idle_poll_sel {
MAC_AX_TX_IDLE_POLL_SEL_BAND,
};
/**
* @enum mac_ax_mcc_status
*
* @brief mac_ax_mcc_status
*
* @var mac_ax_mcc_status::MAC_AX_MCC_ADD_ROLE_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_START_GROUP_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_STOP_GROUP_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_DEL_GROUP_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_RESET_GROUP_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_SWITCH_CH_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL0_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL1_OK
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_SWITCH_EARLY
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_TBTT
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_DURATION_START
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_DURATION_END
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_ADD_ROLE_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_START_GROUP_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_STOP_GROUP_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_DEL_GROUP_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_RESET_GROUP_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_SWITCH_CH_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL0_FAIL
* Please Place Description here.
* @var mac_ax_mcc_status::MAC_AX_MCC_TXNULL1_FAIL
* Please Place Description here.
*/
enum mac_ax_mcc_status {
MAC_AX_MCC_ADD_ROLE_OK = 0,
MAC_AX_MCC_START_GROUP_OK = 1,
MAC_AX_MCC_STOP_GROUP_OK = 2,
MAC_AX_MCC_DEL_GROUP_OK = 3,
MAC_AX_MCC_RESET_GROUP_OK = 4,
MAC_AX_MCC_SWITCH_CH_OK = 5,
MAC_AX_MCC_TXNULL0_OK = 6,
MAC_AX_MCC_TXNULL1_OK = 7,
MAC_AX_MCC_SWITCH_EARLY = 10,
MAC_AX_MCC_TBTT = 11,
MAC_AX_MCC_DURATION_START = 12,
MAC_AX_MCC_DURATION_END = 13,
MAC_AX_MCC_ADD_ROLE_FAIL = 20,
MAC_AX_MCC_START_GROUP_FAIL = 21,
MAC_AX_MCC_STOP_GROUP_FAIL = 22,
MAC_AX_MCC_DEL_GROUP_FAIL = 23,
MAC_AX_MCC_RESET_GROUP_FAIL = 24,
MAC_AX_MCC_SWITCH_CH_FAIL = 25,
MAC_AX_MCC_TXNULL0_FAIL = 26,
MAC_AX_MCC_TXNULL1_FAIL = 27,
};
/**
* @enum mac_ax_trx_mitigation_timer_unit
*
* @brief mac_ax_trx_mitigation_timer_unit
*
* @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_64US
* Please Place Description here.
* @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_128US
* Please Place Description here.
* @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_256US
* Please Place Description here.
* @var mac_ax_trx_mitigation_timer_unit::MAC_AX_MIT_512US
* Please Place Description here.
*/
enum mac_ax_trx_mitigation_timer_unit {
MAC_AX_MIT_64US,
MAC_AX_MIT_128US,
MAC_AX_MIT_256US,
MAC_AX_MIT_512US
};
/**
* @enum mac_ax_wow_wake_reason
*
* @brief mac_ax_wow_wake_reason
*
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_PAIRWISEKEY
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_GTK
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_FOURWAY_HANDSHAKE
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DISASSOC
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DEAUTH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_ARP_REQUEST
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_NS
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_EAPREQ_IDENTIFY
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_FW_DECISION_DISCONNECT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_MAGIC_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_UNICAST_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_PATTERN_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RTD3_SSID_MATCH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DATA_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_SSDP_MATCH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_WSD_MATCH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_SLP_MATCH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_LLTD_MATCH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_MDNS_MATCH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_REALWOW_V2_WAKEUP_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_REALWOW_V2_ACK_LOST
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_REALWOW_V2_TX_KAPKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_ENABLE_FAIL_DMA_IDLE
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_ENABLE_FAIL_DMA_PAUSE
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RTIME_FAIL_DMA_IDLE
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RTIME_FAIL_DMA_PAUSE
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_SNMP_MISMATCHED_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_RX_DESIGNATED_MAC_PKT
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_NLO_SSID_MACH
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_AP_OFFLOAD_WAKEUP
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_DMAC_ERROR_OCCURRED
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_EXCEPTION_OCCURRED
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_CLK_32K_UNLOCK
* Please Place Description here.
* @var mac_ax_wow_wake_reason::MAC_AX_WOW_CLK_32K_LOCK
* Please Place Description here.
*/
enum mac_ax_wow_wake_reason {
MAC_AX_WOW_RX_PAIRWISEKEY = 0x01,
MAC_AX_WOW_RX_GTK = 0x02,
MAC_AX_WOW_RX_FOURWAY_HANDSHAKE = 0x03,
MAC_AX_WOW_RX_DISASSOC = 0x04,
MAC_AX_WOW_RX_DEAUTH = 0x08,
MAC_AX_WOW_RX_ARP_REQUEST = 0x09,
MAC_AX_WOW_RX_NS = 0x0A,
MAC_AX_WOW_RX_EAPREQ_IDENTIFY = 0x0B,
MAC_AX_WOW_FW_DECISION_DISCONNECT = 0x10,
MAC_AX_WOW_RX_MAGIC_PKT = 0x21,
MAC_AX_WOW_RX_UNICAST_PKT = 0x22,
MAC_AX_WOW_RX_PATTERN_PKT = 0x23,
MAC_AX_WOW_RTD3_SSID_MATCH = 0x24,
MAC_AX_WOW_RX_DATA_PKT = 0x25,
MAC_AX_WOW_RX_SSDP_MATCH = 0x26,
MAC_AX_WOW_RX_WSD_MATCH = 0x27,
MAC_AX_WOW_RX_SLP_MATCH = 0x28,
MAC_AX_WOW_RX_LLTD_MATCH = 0x29,
MAC_AX_WOW_RX_MDNS_MATCH = 0x2A,
MAC_AX_WOW_RX_REALWOW_V2_WAKEUP_PKT = 0x30,
MAC_AX_WOW_RX_REALWOW_V2_ACK_LOST = 0x31,
MAC_AX_WOW_RX_REALWOW_V2_TX_KAPKT = 0x32,
MAC_AX_WOW_ENABLE_FAIL_DMA_IDLE = 0x40,
MAC_AX_WOW_ENABLE_FAIL_DMA_PAUSE = 0x41,
MAC_AX_WOW_RTIME_FAIL_DMA_IDLE = 0x42,
MAC_AX_WOW_RTIME_FAIL_DMA_PAUSE = 0x43,
MAC_AX_WOW_RX_SNMP_MISMATCHED_PKT = 0x50,
MAC_AX_WOW_RX_DESIGNATED_MAC_PKT = 0x51,
MAC_AX_WOW_NLO_SSID_MACH = 0x55,
MAC_AX_WOW_AP_OFFLOAD_WAKEUP = 0x66,
MAC_AX_WOW_DMAC_ERROR_OCCURRED = 0x70,
MAC_AX_WOW_EXCEPTION_OCCURRED = 0x71,
MAC_AX_WOW_L0_TO_L1_ERROR_OCCURRED = 0x72,
MAC_AX_WOW_ASSERT_OCCURRED = 0x73,
MAC_AX_WOW_L2_ERROR_OCCURRED = 0x74,
MAC_AX_WOW_WDT_TIMEOUT_WAKE = 0x75,
MAC_AX_WOW_RX_ACTION = 0xD0,
MAC_AX_WOW_CLK_32K_UNLOCK = 0xFD,
MAC_AX_WOW_CLK_32K_LOCK = 0xFE
};
/**
* @enum mac_ax_wow_fw_status
*
* @brief mac_ax_wow_fw_status
*
* @var mac_ax_wow_fw_status::MAC_AX_WOW_NOT_READY
* Please Place Description here.
* @var mac_ax_wow_fw_status::MAC_AX_WOW_SLEEP
* Please Place Description here.
* @var mac_ax_wow_fw_status::MAC_AX_WOW_RESUME
* Please Place Description here.
*/
enum mac_ax_wow_fw_status {
MAC_AX_WOW_NOT_READY,
MAC_AX_WOW_SLEEP,
MAC_AX_WOW_RESUME
};
/**
* @enum mac_ax_wow_ctrl
*
* @brief mac_ax_wow_ctrl
*
* @var mac_ax_wow_ctrl::MAC_AX_WOW_ENTER
* Please Place Description here.
* @var mac_ax_wow_ctrl::MAC_AX_WOW_LEAVE
* Please Place Description here.
*/
enum mac_ax_wow_ctrl {
MAC_AX_WOW_ENTER,
MAC_AX_WOW_LEAVE
};
/**
* @enum mac_ax_mac_pwr_st
*
* @brief mac_ax_mac_pwr_st
*
* @var mac_ax_mac_pwr_st::MAC_AX_MAC_OFF
* Please Place Description here.
* @var mac_ax_mac_pwr_st::MAC_AX_MAC_ON
* Please Place Description here.
* @var mac_ax_mac_pwr_st::MAC_AX_MAC_LPS
* Please Place Description here.
*/
enum mac_ax_mac_pwr_st {
MAC_AX_MAC_OFF = 0,
MAC_AX_MAC_ON = 1,
MAC_AX_MAC_LPS = 2
};
/**
* @enum mac_ax_core_swr_volt
*
* @brief mac_ax_core_swr_volt
*
* @var mac_ax_core_swr_volt::MAC_AX_SWR_LOW
* Please Place Description here.
* @var mac_ax_core_swr_volt::MAC_AX_SWR_NORM
* Please Place Description here.
* @var mac_ax_core_swr_volt::MAC_AX_SWR_HIGH
* Please Place Description here.
*/
enum mac_ax_core_swr_volt {
MAC_AX_SWR_LOW = 0,
MAC_AX_SWR_NORM = 3,
MAC_AX_SWR_HIGH = 6
};
/*--------------------Define DBG and recovery related enum--------------------*/
/**
* @enum mac_ax_err_info
*
* @brief mac_ax_err_info
*
* @var mac_ax_err_info::MAC_AX_ERR_L0_ERR_CMAC0
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_ERR_CMAC1
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_RESET_DONE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_PROMOTE_TO_L1
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L1_ERR_DMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L1_RESET_RECOVERY_DONE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L1_PROMOTE_TO_L2
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_DMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_HCI
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_RLX4081
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_RX4281
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AH_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_DMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_HCI
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_RX4281
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L2_RESET_DONE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_GET_ERR_MAX
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L1_DISABLE_EN
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L1_RCVY_EN
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_CFG_NOTIFY
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_CFG_DIS_NOTIFY
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_CFG_HANDSHAKE
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_ERR_L0_RCVY_EN
* Please Place Description here.
* @var mac_ax_err_info::MAC_AX_SET_ERR_MAX
* Please Place Description here.
*/
enum mac_ax_err_info {
// Get error info
// L0
MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
MAC_AX_ERR_L0_RESET_DONE = 0x0003,
MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
// L1
MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
// L2
// address hole (master)
MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
// AHB bridge timeout (master)
MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
// APB_SA bridge timeout (master + slave)
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
// APB_BBRF bridge timeout (master)
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
MAC_AX_ERR_L2_RESET_DONE = 0x2400,
MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
MAC_AX_ERR_ASSERTION = 0x4000,
MAC_AX_GET_ERR_MAX,
//Use the special code to indicate phl should dump share buffer
MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
// set error info
MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
MAC_AX_ERR_L1_RCVY_EN = 0x0002,
MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
MAC_AX_ERR_L0_RCVY_EN = 0x0013,
MAC_AX_SET_ERR_MAX,
};
/**
* @enum mac_ax_mem_sel
*
* @brief mac_ax_mem_sel
*
* @var mac_ax_mem_sel::MAC_AX_MEM_AXIDMA
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_SHARED_BUF
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_DMAC_TBL
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_SHCUT_MACHDR
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_STA_SCHED
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_RXPLD_FLTR_CAM
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_SECURITY_CAM
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_WOW_CAM
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_CMAC_TBL
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_ADDR_CAM
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_BA_CAM
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_BCN_IE_CAM0
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_BCN_IE_CAM1
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_TXD_FIFO_0
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_TXD_FIFO_1
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_LAST
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_MAX
* Please Place Description here.
* @var mac_ax_mem_sel::MAC_AX_MEM_INVALID
* Please Place Description here.
*/
enum mac_ax_mem_sel {
MAC_AX_MEM_CPU_LOCAL,
MAC_AX_MEM_AXIDMA,
MAC_AX_MEM_SHARED_BUF,
MAC_AX_MEM_DMAC_TBL,
MAC_AX_MEM_SHCUT_MACHDR,
MAC_AX_MEM_STA_SCHED,
MAC_AX_MEM_RXPLD_FLTR_CAM,
MAC_AX_MEM_SECURITY_CAM,
MAC_AX_MEM_WOW_CAM,
MAC_AX_MEM_CMAC_TBL,
MAC_AX_MEM_ADDR_CAM,
MAC_AX_MEM_BA_CAM,
MAC_AX_MEM_BCN_IE_CAM0,
MAC_AX_MEM_BCN_IE_CAM1,
MAC_AX_MEM_TXD_FIFO_0,
MAC_AX_MEM_TXD_FIFO_1,
/* keep last */
MAC_AX_MEM_LAST,
MAC_AX_MEM_MAX = MAC_AX_MEM_LAST,
MAC_AX_MEM_INVALID = MAC_AX_MEM_LAST,
};
/**
* @enum mac_ax_reg_sel
*
* @brief mac_ax_reg_sel
*
* @var mac_ax_reg_sel::MAC_AX_REG_MAC
* Please Place Description here.
* @var mac_ax_reg_sel::MAC_AX_REG_BB
* Please Place Description here.
* @var mac_ax_reg_sel::MAC_AX_REG_IQK
* Please Place Description here.
* @var mac_ax_reg_sel::MAC_AX_REG_RFC
* Please Place Description here.
* @var mac_ax_reg_sel::MAC_AX_REG_LAST
* Please Place Description here.
* @var mac_ax_reg_sel::MAC_AX_REG_MAX
* Please Place Description here.
* @var mac_ax_reg_sel::MAC_AX_REG_INVALID
* Please Place Description here.
*/
enum mac_ax_reg_sel {
MAC_AX_REG_MAC,
MAC_AX_REG_BB,
MAC_AX_REG_IQK,
MAC_AX_REG_RFC,
/* keep last */
MAC_AX_REG_LAST,
MAC_AX_REG_MAX = MAC_AX_REG_LAST,
MAC_AX_REG_INVALID = MAC_AX_REG_LAST,
};
/*--------------------Define GPIO related enum-------------------------------*/
/**
* @enum mac_ax_gpio_func
*
* @brief mac_ax_gpio_func
*
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_0
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_1
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_2
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_3
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_4
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_5
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_6
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_7
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_8
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_9
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_10
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_11
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_12
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_13
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_14
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_SW_IO_15
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_UART_TX_GPIO5
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_UART_TX_GPIO7
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_UART_TX_GPIO8
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_UART_RX_GPIO6
* Please Place Description here.
* @var mac_ax_gpio_func::MAC_AX_GPIO_UART_RX_GPIO14
* Please Place Description here.
*/
enum mac_ax_gpio_func {
MAC_AX_GPIO_SW_IO_0,
MAC_AX_GPIO_SW_IO_1,
MAC_AX_GPIO_SW_IO_2,
MAC_AX_GPIO_SW_IO_3,
MAC_AX_GPIO_SW_IO_4,
MAC_AX_GPIO_SW_IO_5,
MAC_AX_GPIO_SW_IO_6,
MAC_AX_GPIO_SW_IO_7,
MAC_AX_GPIO_SW_IO_8,
MAC_AX_GPIO_SW_IO_9,
MAC_AX_GPIO_SW_IO_10,
MAC_AX_GPIO_SW_IO_11,
MAC_AX_GPIO_SW_IO_12,
MAC_AX_GPIO_SW_IO_13,
MAC_AX_GPIO_SW_IO_14,
MAC_AX_GPIO_SW_IO_15,
MAC_AX_GPIO_UART_TX_GPIO5,
MAC_AX_GPIO_UART_TX_GPIO7,
MAC_AX_GPIO_UART_TX_GPIO8,
MAC_AX_GPIO_UART_RX_GPIO6,
MAC_AX_GPIO_UART_RX_GPIO14,
};
/**
* @enum mac_ax_uart_tx_pin
*
* @brief mac_ax_uart_tx_pin
*
* @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO5
* Please Place Description here.
* @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO7
* Please Place Description here.
* @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO8
* Please Place Description here.
* @var mac_ax_uart_tx_pin::MAC_AX_UART_TX_GPIO5_GPIO8
* Please Place Description here.
*/
enum mac_ax_uart_tx_pin {
MAC_AX_UART_TX_GPIO5,
MAC_AX_UART_TX_GPIO7,
MAC_AX_UART_TX_GPIO8,
MAC_AX_UART_TX_GPIO5_GPIO8,
};
/**
* @enum mac_ax_uart_rx_pin
*
* @brief mac_ax_uart_rx_pin
*
* @var mac_ax_uart_rx_pin::MAC_AX_UART_RX_GPIO6
* Please Place Description here.
* @var mac_ax_uart_rx_pin::MAC_AX_UART_RX_GPIO14
* Please Place Description here.
*/
enum mac_ax_uart_rx_pin {
MAC_AX_UART_RX_GPIO6,
MAC_AX_UART_RX_GPIO14,
};
/**
* @enum mac_ax_led_mode
*
* @brief mac_ax_led_mode
*
* @var mac_ax_led_mode::MAC_AX_LED_MODE_TRX_ON
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_TX_ON
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_RX_ON
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_SW_CTRL_OD
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_SW_CTRL_PP
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_LAST
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_MAX
* Please Place Description here.
* @var mac_ax_led_mode::MAC_AX_LED_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_led_mode {
MAC_AX_LED_MODE_TRX_ON,
MAC_AX_LED_MODE_TX_ON,
MAC_AX_LED_MODE_RX_ON,
MAC_AX_LED_MODE_SW_CTRL_OD,
MAC_AX_LED_MODE_SW_CTRL_PP,
/* keep last */
MAC_AX_LED_MODE_LAST,
MAC_AX_LED_MODE_MAX = MAC_AX_LED_MODE_LAST,
MAC_AX_LED_MODE_INVALID = MAC_AX_LED_MODE_LAST,
};
/**
* @enum mac_ax_sw_io_mode
*
* @brief mac_ax_sw_io_mode
*
* @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_INPUT
* Please Place Description here.
* @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_OUTPUT_OD
* Please Place Description here.
* @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_OUTPUT_PP
* Please Place Description here.
* @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_LAST
* Please Place Description here.
* @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_MAX
* Please Place Description here.
* @var mac_ax_sw_io_mode::MAC_AX_SW_IO_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_sw_io_mode {
MAC_AX_SW_IO_MODE_INPUT,
MAC_AX_SW_IO_MODE_OUTPUT_OD,
MAC_AX_SW_IO_MODE_OUTPUT_PP,
/* keep last */
MAC_AX_SW_IO_MODE_LAST,
MAC_AX_SW_IO_MODE_MAX = MAC_AX_SW_IO_MODE_LAST,
MAC_AX_SW_IO_MODE_INVALID = MAC_AX_SW_IO_MODE_LAST,
};
/*--------------------Define Efuse related enum-------------------------------*/
/**
* @enum mac_ax_efuse_read_cfg
*
* @brief mac_ax_efuse_read_cfg
*
* @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_AUTO
* Please Place Description here.
* @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_DRV
* Please Place Description here.
* @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_FW
* Please Place Description here.
* @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_LAST
* Please Place Description here.
* @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_MAX
* Please Place Description here.
* @var mac_ax_efuse_read_cfg::MAC_AX_EFUSE_R_INVALID
* Please Place Description here.
*/
enum mac_ax_efuse_read_cfg {
MAC_AX_EFUSE_R_AUTO,
MAC_AX_EFUSE_R_DRV,
MAC_AX_EFUSE_R_FW,
/* keep last */
MAC_AX_EFUSE_R_LAST,
MAC_AX_EFUSE_R_MAX = MAC_AX_EFUSE_R_LAST,
MAC_AX_EFUSE_R_INVALID = MAC_AX_EFUSE_R_LAST,
};
/**
* @enum mac_ax_efuse_bank
*
* @brief mac_ax_efuse_bank
*
* @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_WIFI
* Please Place Description here.
* @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_BT
* Please Place Description here.
* @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_LAST
* Please Place Description here.
* @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_MAX
* Please Place Description here.
* @var mac_ax_efuse_bank::MAC_AX_EFUSE_BANK_INVALID
* Please Place Description here.
*/
enum mac_ax_efuse_bank {
MAC_AX_EFUSE_BANK_WIFI,
MAC_AX_EFUSE_BANK_BT,
/* keep last */
MAC_AX_EFUSE_BANK_LAST,
MAC_AX_EFUSE_BANK_MAX = MAC_AX_EFUSE_BANK_LAST,
MAC_AX_EFUSE_BANK_INVALID = MAC_AX_EFUSE_BANK_LAST,
};
/**
* @enum mac_ax_efuse_parser_cfg
*
* @brief mac_ax_efuse_parser_cfg
*
* @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_MAP
* Please Place Description here.
* @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_MASK
* Please Place Description here.
* @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_LAST
* Please Place Description here.
* @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_MAX
* Please Place Description here.
* @var mac_ax_efuse_parser_cfg::MAC_AX_EFUSE_PARSER_INVALID
* Please Place Description here.
*/
enum mac_ax_efuse_parser_cfg {
MAC_AX_EFUSE_PARSER_MAP,
MAC_AX_EFUSE_PARSER_MASK,
/* keep last */
MAC_AX_EFUSE_PARSER_LAST,
MAC_AX_EFUSE_PARSER_MAX = MAC_AX_EFUSE_PARSER_LAST,
MAC_AX_EFUSE_PARSER_INVALID = MAC_AX_EFUSE_PARSER_LAST,
};
/**
* @enum mac_ax_efuse_feature_id
*
* @brief mac_ax_efuse_feature_id
*
* @var mac_ax_efuse_feature_id::MAC_AX_DUMP_PHYSICAL_EFUSE
* Please Place Description here.
* @var mac_ax_efuse_feature_id::MAC_AX_DUMP_LOGICAL_EFUSE
* Please Place Description here.
* @var mac_ax_efuse_feature_id::MAC_AX_DUMP_LOGICAL_EFUSE_MASK
* Please Place Description here.
*/
enum mac_ax_efuse_feature_id {
MAC_AX_DUMP_PHYSICAL_EFUSE, /* Support */
MAC_AX_DUMP_LOGICAL_EFUSE, /* Support */
MAC_AX_DUMP_LOGICAL_EFUSE_MASK, /* Support */
};
/*--------------------Define TRX PKT INFO/RPT related enum--------------------*/
/**
* @enum mac_ax_trx_mode
*
* @brief mac_ax_trx_mode
*
* @var mac_ax_trx_mode::MAC_AX_TRX_SW_MODE
* Please Place Description here.
* @var mac_ax_trx_mode::MAC_AX_TRX_HW_MODE
* Please Place Description here.
* @var mac_ax_trx_mode::MAC_AX_TRX_LOOPBACK
* Please Place Description here.
* @var mac_ax_trx_mode::MAC_AX_TRX_LAST
* Please Place Description here.
* @var mac_ax_trx_mode::MAC_AX_TRX_MAX
* Please Place Description here.
* @var mac_ax_trx_mode::MAC_AX_TRX_INVALID
* Please Place Description here.
*/
enum mac_ax_trx_mode {
MAC_AX_TRX_SW_MODE,
MAC_AX_TRX_HW_MODE,
MAC_AX_TRX_LOOPBACK,
MAC_AX_TRX_NORMAL, /* shall remove when v0_22 release, Rick */
/* keep last */
MAC_AX_TRX_LAST,
MAC_AX_TRX_MAX = MAC_AX_TRX_LAST,
MAC_AX_TRX_INVALID = MAC_AX_TRX_LAST,
};
/**
* @enum mac_ax_qta_mode
*
* @brief mac_ax_qta_mode
*
* @var mac_ax_qta_mode::MAC_AX_QTA_SCC
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_DBCC
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_SCC_STF
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_DBCC_STF
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_SU_TP
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_DLFW
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_BCN_TEST
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_LAMODE
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_LAST
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_MAX
* Please Place Description here.
* @var mac_ax_qta_mode::MAC_AX_QTA_INVALID
* Please Place Description here.
*/
enum mac_ax_qta_mode {
MAC_AX_QTA_SCC,
MAC_AX_QTA_DBCC,
MAC_AX_QTA_SCC_STF,
MAC_AX_QTA_DBCC_STF,
MAC_AX_QTA_SU_TP,
MAC_AX_QTA_DLFW,
MAC_AX_QTA_BCN_TEST,
MAC_AX_QTA_LAMODE,
/* keep last */
MAC_AX_QTA_LAST,
MAC_AX_QTA_MAX = MAC_AX_QTA_LAST,
MAC_AX_QTA_INVALID = MAC_AX_QTA_LAST,
};
/**
* @enum mac_ax_pkt_t
*
* @brief mac_ax_pkt_t
*
* @var mac_ax_pkt_t::MAC_AX_PKT_DATA
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_MGNT
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_CTRL
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_8023
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_H2C
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_FWDL
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_C2H
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_PPDU
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_CH_INFO
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_DFS
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_LAST
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_MAX
* Please Place Description here.
* @var mac_ax_pkt_t::MAC_AX_PKT_INVALID
* Please Place Description here.
*/
enum mac_ax_pkt_t {
MAC_AX_PKT_DATA,
MAC_AX_PKT_MGNT,
MAC_AX_PKT_CTRL,
MAC_AX_PKT_8023,
MAC_AX_PKT_H2C,
MAC_AX_PKT_FWDL,
MAC_AX_PKT_C2H,
MAC_AX_PKT_PPDU,
MAC_AX_PKT_CH_INFO,
MAC_AX_PKT_DFS,
/* keep last */
MAC_AX_PKT_LAST,
MAC_AX_PKT_MAX = MAC_AX_PKT_LAST,
MAC_AX_PKT_INVALID = MAC_AX_PKT_LAST,
};
/**
* @enum mac_ax_amsdu_pkt_num
*
* @brief mac_ax_amsdu_pkt_num
*
* @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_1
* Please Place Description here.
* @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_2
* Please Place Description here.
* @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_3
* Please Place Description here.
* @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_4
* Please Place Description here.
* @var mac_ax_amsdu_pkt_num::MAC_AX_AMSDU_AGG_NUM_MAX
* Please Place Description here.
*/
enum mac_ax_amsdu_pkt_num {
MAC_AX_AMSDU_AGG_NUM_1 = 0,
MAC_AX_AMSDU_AGG_NUM_2 = 1,
MAC_AX_AMSDU_AGG_NUM_3 = 2,
MAC_AX_AMSDU_AGG_NUM_4 = 3,
MAC_AX_AMSDU_AGG_NUM_MAX
};
/**
* @enum mac_ax_phy_rpt
*
* @brief mac_ax_phy_rpt
*
* @var mac_ax_phy_rpt::MAC_AX_PPDU_STATUS
* Please Place Description here.
* @var mac_ax_phy_rpt::MAC_AX_CH_INFO
* Please Place Description here.
* @var mac_ax_phy_rpt::MAC_AX_DFS
* Please Place Description here.
*/
enum mac_ax_phy_rpt {
MAC_AX_PPDU_STATUS,
MAC_AX_CH_INFO,
MAC_AX_DFS,
};
/**
* @enum mac_ax_pkt_drop_sel
*
* @brief mac_ax_pkt_drop_sel
*
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_BE_ONCE
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_BK_ONCE
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_VI_ONCE
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_VO_ONCE
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MACID_ALL
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MG0_ONCE
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_HIQ_ONCE
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_HIQ_PORT
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_HIQ_MBSSID
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_BAND
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_REL_MACID
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_LAST
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_MAX
* Please Place Description here.
* @var mac_ax_pkt_drop_sel::MAC_AX_PKT_DROP_SEL_INVALID
* Please Place Description here.
*/
enum mac_ax_pkt_drop_sel {
MAC_AX_PKT_DROP_SEL_MACID_BE_ONCE,
MAC_AX_PKT_DROP_SEL_MACID_BK_ONCE,
MAC_AX_PKT_DROP_SEL_MACID_VI_ONCE,
MAC_AX_PKT_DROP_SEL_MACID_VO_ONCE,
MAC_AX_PKT_DROP_SEL_MACID_ALL,
MAC_AX_PKT_DROP_SEL_MG0_ONCE,
MAC_AX_PKT_DROP_SEL_HIQ_ONCE,
MAC_AX_PKT_DROP_SEL_HIQ_PORT,
MAC_AX_PKT_DROP_SEL_HIQ_MBSSID,
MAC_AX_PKT_DROP_SEL_BAND,
MAC_AX_PKT_DROP_SEL_BAND_ONCE,
MAC_AX_PKT_DROP_SEL_REL_MACID,
MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT,
MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID,
/* keep last */
MAC_AX_PKT_DROP_SEL_LAST,
MAC_AX_PKT_DROP_SEL_MAX = MAC_AX_PKT_DROP_SEL_LAST,
MAC_AX_PKT_DROP_SEL_INVALID = MAC_AX_PKT_DROP_SEL_LAST,
};
/*need to check and move to other */
/**
* @enum mac_ax_fwd_target
*
* @brief mac_ax_fwd_target
*
* @var mac_ax_fwd_target::MAC_AX_FWD_DONT_CARE
* Please Place Description here.
* @var mac_ax_fwd_target::MAC_AX_FWD_TO_HOST
* Please Place Description here.
* @var mac_ax_fwd_target::MAC_AX_FWD_TO_WLAN_CPU
* Please Place Description here.
*/
enum mac_ax_fwd_target {
MAC_AX_FWD_DONT_CARE = 0,
MAC_AX_FWD_TO_HOST = 1,
MAC_AX_FWD_TO_WLAN_CPU = 2
};
/**
* @enum mac_ax_action_frame
*
* @brief mac_ax_action_frame
*
* @var mac_ax_action_frame::MAC_AX_AF_CSA
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_ADDTS_REQ
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_ADDTS_RES
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_DELTS
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_ADDBA_REQ
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_ADDBA_RES
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_DELBA
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_NCW
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_GID_MGNT
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_OP_MODE
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_CSI
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_HT_CBFM
* Please Place Description here.
* @var mac_ax_action_frame::MAC_AX_AF_VHT_CBFM
* Please Place Description here.
*/
enum mac_ax_action_frame {
MAC_AX_AF_CSA = 0,
MAC_AX_AF_ADDTS_REQ = 1,
MAC_AX_AF_ADDTS_RES = 2,
MAC_AX_AF_DELTS = 3,
MAC_AX_AF_ADDBA_REQ = 4,
MAC_AX_AF_ADDBA_RES = 5,
MAC_AX_AF_DELBA = 6,
MAC_AX_AF_NCW = 7,
MAC_AX_AF_GID_MGNT = 8,
MAC_AX_AF_OP_MODE = 9,
MAC_AX_AF_CSI = 10,
MAC_AX_AF_HT_CBFM = 11,
MAC_AX_AF_VHT_CBFM = 12
};
/**
* @enum mac_ax_af_user_define_index
*
* @brief mac_ax_af_user_define_index
*
* @var mac_ax_af_user_define_index::MAC_AX_AF_UD_0
* Please Place Description here.
* @var mac_ax_af_user_define_index::MAC_AX_AF_UD_1
* Please Place Description here.
* @var mac_ax_af_user_define_index::MAC_AX_AF_UD_2
* Please Place Description here.
* @var mac_ax_af_user_define_index::MAC_AX_AF_UD_3
* Please Place Description here.
*/
enum mac_ax_af_user_define_index {
MAC_AX_AF_UD_0 = 0,
MAC_AX_AF_UD_1 = 1,
MAC_AX_AF_UD_2 = 2,
MAC_AX_AF_UD_3 = 3
};
/**
* @enum mac_ax_trigger_frame
*
* @brief mac_ax_trigger_frame
*
* @var mac_ax_trigger_frame::MAC_AX_TF_BT
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_BFRP
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_MU_BAR
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_MU_RTS
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_BSRP
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_GCR_MU_BAR
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_BQRP
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_NFRP
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF8
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF9
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF10
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF11
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF12
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF13
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF14
* Please Place Description here.
* @var mac_ax_trigger_frame::MAC_AX_TF_TF15
* Please Place Description here.
*/
enum mac_ax_trigger_frame {
MAC_AX_TF_BT = 0,
MAC_AX_TF_BFRP = 1,
MAC_AX_TF_MU_BAR = 2,
MAC_AX_TF_MU_RTS = 3,
MAC_AX_TF_BSRP = 4,
MAC_AX_TF_GCR_MU_BAR = 5,
MAC_AX_TF_BQRP = 6,
MAC_AX_TF_NFRP = 7,
MAC_AX_TF_TF8 = 8,
MAC_AX_TF_TF9 = 9,
MAC_AX_TF_TF10 = 10,
MAC_AX_TF_TF11 = 11,
MAC_AX_TF_TF12 = 12,
MAC_AX_TF_TF13 = 13,
MAC_AX_TF_TF14 = 14,
MAC_AX_TF_TF15 = 15
};
/**
* @enum mac_ax_frame_type
*
* @brief mac_ax_frame_type
*
* @var mac_ax_frame_type::MAC_AX_FT_ACTION
* Please Place Description here.
* @var mac_ax_frame_type::MAC_AX_FT_ACTION_UD
* Please Place Description here.
* @var mac_ax_frame_type::MAC_AX_FT_TRIGGER
* Please Place Description here.
* @var mac_ax_frame_type::MAC_AX_FT_PM_CAM
* Please Place Description here.
*/
enum mac_ax_frame_type {
MAC_AX_FT_ACTION = 0,
MAC_AX_FT_ACTION_UD = 1,
MAC_AX_FT_TRIGGER = 2,
MAC_AX_FT_PM_CAM = 3
};
/**
* @enum mac_ax_bd_trunc_mode
*
* @brief mac_ax_bd_trunc_mode
*
* @var mac_ax_bd_trunc_mode::MAC_AX_BD_NORM
* Please Place Description here.
* @var mac_ax_bd_trunc_mode::MAC_AX_BD_TRUNC
* Please Place Description here.
* @var mac_ax_bd_trunc_mode::MAC_AX_BD_DEF
* Please Place Description here.
*/
enum mac_ax_bd_trunc_mode {
MAC_AX_BD_NORM,
MAC_AX_BD_TRUNC,
MAC_AX_BD_DEF = 0xFE
};
/**
* @enum mac_ax_rxbd_mode
*
* @brief mac_ax_rxbd_mode
*
* @var mac_ax_rxbd_mode::MAC_AX_RXBD_PKT
* Please Place Description here.
* @var mac_ax_rxbd_mode::MAC_AX_RXBD_SEP
* Please Place Description here.
* @var mac_ax_rxbd_mode::MAC_AX_RXBD_DEF
* Please Place Description here.
*/
enum mac_ax_rxbd_mode {
MAC_AX_RXBD_PKT,
MAC_AX_RXBD_SEP,
MAC_AX_RXBD_DEF = 0xFE
};
/**
* @enum mac_ax_tag_mode
*
* @brief mac_ax_tag_mode
*
* @var mac_ax_tag_mode::MAC_AX_TAG_SGL
* Please Place Description here.
* @var mac_ax_tag_mode::MAC_AX_TAG_MULTI
* Please Place Description here.
* @var mac_ax_tag_mode::MAC_AX_TAG_DEF
* Please Place Description here.
*/
enum mac_ax_tag_mode {
MAC_AX_TAG_SGL,
MAC_AX_TAG_MULTI,
MAC_AX_TAG_DEF = 0xFE
};
/**
* @enum mac_ax_rx_fecth
*
* @brief mac_ax_rx_fecth
*
* @var mac_ax_rx_fecth::MAC_AX_RX_NORM_FETCH
* Please Place Description here.
* @var mac_ax_rx_fecth::MAC_AX_RX_PRE_FETCH
* Please Place Description here.
* @var mac_ax_rx_fecth::MAC_AX_RX_FETCH_DEF
* Please Place Description here.
*/
enum mac_ax_rx_fecth {
MAC_AX_RX_NORM_FETCH,
MAC_AX_RX_PRE_FETCH,
MAC_AX_RX_FETCH_DEF = 0xFE
};
/**
* @enum mac_ax_tx_burst
*
* @brief mac_ax_tx_burst
*
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_16B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_32B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_64B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_128B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_256B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_512B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_1024B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_2048B
* Please Place Description here.
* @var mac_ax_tx_burst::MAC_AX_TX_BURST_DEF
* Please Place Description here.
*/
enum mac_ax_tx_burst {
MAC_AX_TX_BURST_16B = 0,
MAC_AX_TX_BURST_32B = 1,
MAC_AX_TX_BURST_64B = 2,
MAC_AX_TX_BURST_V1_64B = 0,
MAC_AX_TX_BURST_128B = 3,
MAC_AX_TX_BURST_V1_128B = 1,
MAC_AX_TX_BURST_256B = 4,
MAC_AX_TX_BURST_V1_256B = 2,
MAC_AX_TX_BURST_512B = 5,
MAC_AX_TX_BURST_1024B = 6,
MAC_AX_TX_BURST_2048B = 7,
MAC_AX_TX_BURST_DEF = 0xFE
};
/**
* @enum mac_ax_rx_burst
*
* @brief mac_ax_rx_burst
*
* @var mac_ax_rx_burst::MAC_AX_RX_BURST_16B
* Please Place Description here.
* @var mac_ax_rx_burst::MAC_AX_RX_BURST_32B
* Please Place Description here.
* @var mac_ax_rx_burst::MAC_AX_RX_BURST_64B
* Please Place Description here.
* @var mac_ax_rx_burst::MAC_AX_RX_BURST_128B
* Please Place Description here.
* @var mac_ax_rx_burst::MAC_AX_RX_BURST_DEF
* Please Place Description here.
*/
enum mac_ax_rx_burst {
MAC_AX_RX_BURST_16B = 0,
MAC_AX_RX_BURST_32B = 1,
MAC_AX_RX_BURST_64B = 2,
MAC_AX_RX_BURST_V1_64B = 0,
MAC_AX_RX_BURST_128B = 3,
MAC_AX_RX_BURST_V1_128B = 1,
MAC_AX_RX_BURST_V1_256B = 0,
MAC_AX_RX_BURST_DEF = 0xFE
};
/**
* @enum mac_ax_wd_dma_intvl
*
* @brief mac_ax_wd_dma_intvl
*
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_0S
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_256NS
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_512NS
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_768NS
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_1US
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_1_5US
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_2US
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_4US
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_8US
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_16US
* Please Place Description here.
* @var mac_ax_wd_dma_intvl::MAC_AX_WD_DMA_INTVL_DEF
* Please Place Description here.
*/
enum mac_ax_wd_dma_intvl {
MAC_AX_WD_DMA_INTVL_0S,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_WD_DMA_INTVL_512NS,
MAC_AX_WD_DMA_INTVL_768NS,
MAC_AX_WD_DMA_INTVL_1US,
MAC_AX_WD_DMA_INTVL_1_5US,
MAC_AX_WD_DMA_INTVL_2US,
MAC_AX_WD_DMA_INTVL_4US,
MAC_AX_WD_DMA_INTVL_8US,
MAC_AX_WD_DMA_INTVL_16US,
MAC_AX_WD_DMA_INTVL_DEF = 0xFE
};
/**
* @enum mac_ax_multi_tag_num
*
* @brief mac_ax_multi_tag_num
*
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_1
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_2
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_3
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_4
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_5
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_6
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_7
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_8
* Please Place Description here.
* @var mac_ax_multi_tag_num::MAC_AX_TAG_NUM_DEF
* Please Place Description here.
*/
enum mac_ax_multi_tag_num {
MAC_AX_TAG_NUM_1,
MAC_AX_TAG_NUM_2,
MAC_AX_TAG_NUM_3,
MAC_AX_TAG_NUM_4,
MAC_AX_TAG_NUM_5,
MAC_AX_TAG_NUM_6,
MAC_AX_TAG_NUM_7,
MAC_AX_TAG_NUM_8,
MAC_AX_TAG_NUM_DEF = 0xFE
};
/**
* @enum mac_ax_rx_adv_pref
*
* @brief mac_ax_rx_adv_pref
*
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_1BD
* Please Place Description here.
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_2BD
* Please Place Description here.
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_4BD
* Please Place Description here.
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_8BD
* Please Place Description here.
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_LAST
* Please Place Description here.
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_MAX
* Please Place Description here.
* @var mac_ax_rx_adv_pref::MAC_AX_RX_APREF_INVALID
* Please Place Description here.
*/
enum mac_ax_rx_adv_pref {
MAC_AX_RX_APREF_1BD = 0,
MAC_AX_RX_APREF_2BD,
MAC_AX_RX_APREF_4BD,
MAC_AX_RX_APREF_8BD,
/* keep last */
MAC_AX_RX_APREF_LAST,
MAC_AX_RX_APREF_MAX = MAC_AX_RX_APREF_LAST,
MAC_AX_RX_APREF_INVALID = MAC_AX_RX_APREF_LAST,
};
/**
* @enum mac_ax_lbc_tmr
*
* @brief mac_ax_lbc_tmr
*
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_8US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_16US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_32US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_64US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_128US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_256US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_512US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_1MS
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_2MS
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_4MS
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_8MS
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_LBC_TMR_DEF
* Please Place Description here.
*/
enum mac_ax_lbc_tmr {
MAC_AX_LBC_TMR_8US = 0,
MAC_AX_LBC_TMR_16US,
MAC_AX_LBC_TMR_32US,
MAC_AX_LBC_TMR_64US,
MAC_AX_LBC_TMR_128US,
MAC_AX_LBC_TMR_256US,
MAC_AX_LBC_TMR_512US,
MAC_AX_LBC_TMR_1MS,
MAC_AX_LBC_TMR_2MS,
MAC_AX_LBC_TMR_4MS,
MAC_AX_LBC_TMR_8MS,
MAC_AX_LBC_TMR_DEF = 0xFE
};
/**
* @enum mac_ax_io_rcv_tmr
*
* @brief mac_ax_io_rcv_tmr
*
* @var mac_ax_lbc_tmr::MAC_AX_IO_RCV_ANA_TMR_200US
* Please Place Description here.
* @var mac_ax_lbc_tmr::MAC_AX_IO_RCV_ANA_TMR_300US
* Please Place Description here.
*/
enum mac_ax_io_rcy_tmr {
MAC_AX_IO_RCY_ANA_TMR_20US = 240,
MAC_AX_IO_RCY_ANA_TMR_40US = 480,
MAC_AX_IO_RCY_ANA_TMR_60US = 720,
MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
};
/*END need to check and move to other */
/**
* @enum mac_ax_edcca_sel
*
* @brief mac_ax_edcca_sel
*
* @var mac_ax_edcca_sel::MAC_AX_EDCCA_IN_TB_CHK
* Please Place Description here.
* @var mac_ax_edcca_sel::MAC_AX_EDCCA_IN_SIFS_CHK
* Please Place Description here.
* @var mac_ax_edcca_sel::MAC_AX_EDCCA_IN_CTN_CHK
* Please Place Description here.
* @var mac_ax_edcca_sel::MAC_AX_EDCCA_SEL_LAST
* Please Place Description here.
* @var mac_ax_edcca_sel::MAC_AX_EDCCA_SEL_MAX
* Please Place Description here.
* @var mac_ax_edcca_sel::MAC_AX_EDCCA_SEL_INVALID
* Please Place Description here.
*/
enum mac_ax_edcca_sel {
MAC_AX_EDCCA_IN_TB_CHK,
MAC_AX_EDCCA_IN_SIFS_CHK,
MAC_AX_EDCCA_IN_CTN_CHK,
/* keep last */
MAC_AX_EDCCA_SEL_LAST,
MAC_AX_EDCCA_SEL_MAX = MAC_AX_EDCCA_SEL_LAST,
MAC_AX_EDCCA_SEL_INVALID = MAC_AX_EDCCA_SEL_LAST,
};
/**
* @enum mac_ax_chip_id
*
* @brief mac_ax_chip_id
*
* @var mac_ax_chip_id::MAC_AX_CHIP_ID_8852A
* Please Place Description here.
* @var mac_ax_chip_id::MAC_AX_CHIP_ID_8852B
* Please Place Description here.
* @var mac_ax_chip_id::MAC_AX_CHIP_ID_8852C
* Please Place Description here.
* @var mac_ax_chip_id::MAC_AX_CHIP_ID_LAST
* Please Place Description here.
* @var mac_ax_chip_id::MAC_AX_CHIP_ID_MAX
* Please Place Description here.
* @var mac_ax_chip_id::MAC_AX_CHIP_ID_INVALID
* Please Place Description here.
*/
enum mac_ax_chip_id {
MAC_AX_CHIP_ID_8852A = 0,
MAC_AX_CHIP_ID_8852B,
MAC_AX_CHIP_ID_8852C,
MAC_AX_CHIP_ID_8192XB,
/* keep last */
MAC_AX_CHIP_ID_LAST,
MAC_AX_CHIP_ID_MAX = MAC_AX_CHIP_ID_LAST,
MAC_AX_CHIP_ID_INVALID = MAC_AX_CHIP_ID_LAST,
};
/**
* @enum mac_ax_wdbk_mode
*
* @brief mac_ax_wdbk_mode
*
* @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_SINGLE_BK
* Please Place Description here.
* @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_GRP_BK
* Please Place Description here.
* @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_LAST
* Please Place Description here.
* @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_MAX
* Please Place Description here.
* @var mac_ax_wdbk_mode::MAC_AX_WDBK_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_wdbk_mode {
MAC_AX_WDBK_MODE_SINGLE_BK = 0,
MAC_AX_WDBK_MODE_GRP_BK = 1,
/* keep last */
MAC_AX_WDBK_MODE_LAST,
MAC_AX_WDBK_MODE_MAX = MAC_AX_WDBK_MODE_LAST,
MAC_AX_WDBK_MODE_INVALID = MAC_AX_WDBK_MODE_LAST,
};
/**
* @enum mac_ax_rty_bk_mode
*
* @brief mac_ax_rty_bk_mode
*
* @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_AGG
* Please Place Description here.
* @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_RATE_FB
* Please Place Description here.
* @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_BK
* Please Place Description here.
* @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_LAST
* Please Place Description here.
* @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_MAX
* Please Place Description here.
* @var mac_ax_rty_bk_mode::MAC_AX_RTY_BK_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_rty_bk_mode {
MAC_AX_RTY_BK_MODE_AGG = 0x0,
MAC_AX_RTY_BK_MODE_RATE_FB = 0x1,
MAC_AX_RTY_BK_MODE_BK = 0x2,
/* keep last */
MAC_AX_RTY_BK_MODE_LAST,
MAC_AX_RTY_BK_MODE_MAX = MAC_AX_RTY_BK_MODE_LAST,
MAC_AX_RTY_BK_MODE_INVALID = MAC_AX_RTY_BK_MODE_LAST,
};
/**
* @enum mac_ax_ch_busy_cnt_ctrl
*
* @brief mac_ax_ch_busy_cnt_ctrl
*
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_REF
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_BUSY_RST
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_IDLE_RST
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_EN
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_CNT_DIS
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_LAST
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_MAX
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ctrl::MAC_AX_CH_BUSY_CNT_CTRL_INVALID
* Please Place Description here.
*/
enum mac_ax_ch_busy_cnt_ctrl {
MAC_AX_CH_BUSY_CNT_CTRL_CNT_REF,
MAC_AX_CH_BUSY_CNT_CTRL_CNT_BUSY_RST,
MAC_AX_CH_BUSY_CNT_CTRL_CNT_IDLE_RST,
MAC_AX_CH_BUSY_CNT_CTRL_CNT_RST,
MAC_AX_CH_BUSY_CNT_CTRL_CNT_EN,
MAC_AX_CH_BUSY_CNT_CTRL_CNT_DIS,
/* keep last */
MAC_AX_CH_BUSY_CNT_CTRL_LAST,
MAC_AX_CH_BUSY_CNT_CTRL_MAX = MAC_AX_CH_BUSY_CNT_CTRL_LAST,
MAC_AX_CH_BUSY_CNT_CTRL_INVALID = MAC_AX_CH_BUSY_CNT_CTRL_LAST,
};
/**
* @enum mac_ax_func_sw
*
* @brief mac_ax_func_sw
*
* @var mac_ax_func_sw::MAC_AX_FUNC_DIS
* Please Place Description here.
* @var mac_ax_func_sw::MAC_AX_FUNC_EN
* Please Place Description here.
* @var mac_ax_func_sw::MAC_AX_FUNC_DEF
* Please Place Description here.
*/
enum mac_ax_func_sw {
MAC_AX_FUNC_DIS = 0,
MAC_AX_FUNC_EN,
MAC_AX_FUNC_DEF
};
/**
* @enum mac_ax_twt_nego_tp
*
* @brief mac_ax_twt_nego_tp
*
* @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_IND
* Please Place Description here.
* @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_WAKE
* Please Place Description here.
* @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_BRC
* Please Place Description here.
* @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_LAST
* Please Place Description here.
* @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_MAX
* Please Place Description here.
* @var mac_ax_twt_nego_tp::MAC_AX_TWT_NEGO_TP_INVALID
* Please Place Description here.
*/
enum mac_ax_twt_nego_tp {
MAC_AX_TWT_NEGO_TP_IND,
MAC_AX_TWT_NEGO_TP_WAKE,
MAC_AX_TWT_NEGO_TP_BRC,
/* keep last */
MAC_AX_TWT_NEGO_TP_LAST,
MAC_AX_TWT_NEGO_TP_MAX = MAC_AX_TWT_NEGO_TP_LAST,
MAC_AX_TWT_NEGO_TP_INVALID = MAC_AX_TWT_NEGO_TP_LAST,
};
/**
* @enum mac_ax_twt_act_tp
*
* @brief mac_ax_twt_act_tp
*
* @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_ADD
* Please Place Description here.
* @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_DEL
* Please Place Description here.
* @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_MOD
* Please Place Description here.
* @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_LAST
* Please Place Description here.
* @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_MAX
* Please Place Description here.
* @var mac_ax_twt_act_tp::MAC_AX_TWT_ACT_TP_INVALID
* Please Place Description here.
*/
enum mac_ax_twt_act_tp {
MAC_AX_TWT_ACT_TP_ADD,
MAC_AX_TWT_ACT_TP_DEL,
MAC_AX_TWT_ACT_TP_MOD,
/* keep last */
MAC_AX_TWT_ACT_TP_LAST,
MAC_AX_TWT_ACT_TP_MAX = MAC_AX_TWT_ACT_TP_LAST,
MAC_AX_TWT_ACT_TP_INVALID = MAC_AX_TWT_ACT_TP_LAST,
};
/**
* @enum mac_ax_twtact_act_tp
*
* @brief mac_ax_twtact_act_tp
*
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_ADD
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_DEL
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_TRMNT
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_SUS
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_RSUM
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_LAST
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_MAX
* Please Place Description here.
* @var mac_ax_twtact_act_tp::MAC_AX_TWTACT_ACT_TP_INVALID
* Please Place Description here.
*/
enum mac_ax_twtact_act_tp {
MAC_AX_TWTACT_ACT_TP_ADD,
MAC_AX_TWTACT_ACT_TP_DEL,
MAC_AX_TWTACT_ACT_TP_TRMNT,
MAC_AX_TWTACT_ACT_TP_SUS,
MAC_AX_TWTACT_ACT_TP_RSUM,
/* keep last */
MAC_AX_TWTACT_ACT_TP_LAST,
MAC_AX_TWTACT_ACT_TP_MAX = MAC_AX_TWTACT_ACT_TP_LAST,
MAC_AX_TWTACT_ACT_TP_INVALID = MAC_AX_TWTACT_ACT_TP_LAST,
};
/**
* @enum mac_ax_twt_waitanno_tp
*
* @brief mac_ax_twt_waitanno_tp
*
* @var mac_ax_twt_waitanno_tp::MAC_AX_TWT_ANNOWAIT_DIS_MACID
* Please Place Description here.
* @var mac_ax_twt_waitanno_tp::MAC_AX_TWT_ANNOWAIT_EN_MACID
* Please Place Description here.
*/
enum mac_ax_twt_waitanno_tp {
MAC_AX_TWT_ANNOWAIT_DIS_MACID,
MAC_AX_TWT_ANNOWAIT_EN_MACID,
};
/**
* @enum mac_ax_tsf_sync_act
*
* @brief mac_ax_tsf_sync_act
*
* @var mac_ax_tsf_sync_act::MAC_AX_TSF_SYNC_NOW_ONCE
* Please Place Description here.
* @var mac_ax_tsf_sync_act::MAC_AX_TSF_EN_SYNC_AUTO
* Please Place Description here.
* @var mac_ax_tsf_sync_act::MAC_AX_TSF_DIS_SYNC_AUTO
* Please Place Description here.
*/
enum mac_ax_tsf_sync_act {
MAC_AX_TSF_SYNC_NOW_ONCE,
MAC_AX_TSF_EN_SYNC_AUTO,
MAC_AX_TSF_DIS_SYNC_AUTO
};
/**
* @enum mac_ax_slot_time
*
* @brief mac_ax_slot_time
*
* @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND0_9US
* Please Place Description here.
* @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND0_20US
* Please Place Description here.
* @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND1_9US
* Please Place Description here.
* @var mac_ax_slot_time::MAC_AX_SLOT_TIME_BAND1_20US
* Please Place Description here.
*/
enum mac_ax_slot_time {
MAC_AX_SLOT_TIME_BAND0_9US,
MAC_AX_SLOT_TIME_BAND0_20US,
MAC_AX_SLOT_TIME_BAND1_9US,
MAC_AX_SLOT_TIME_BAND1_20US,
};
/*------------------------Define HCI related enum ----------------------------*/
/**
* @enum mac_ax_pcie_func_ctrl
*
* @brief mac_ax_pcie_func_ctrl
*
* @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_DISABLE
* Please Place Description here.
* @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_ENABLE
* Please Place Description here.
* @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_DEFAULT
* Please Place Description here.
* @var mac_ax_pcie_func_ctrl::MAC_AX_PCIE_IGNORE
* Please Place Description here.
*/
enum mac_ax_pcie_func_ctrl {
MAC_AX_PCIE_DISABLE = 0,
MAC_AX_PCIE_ENABLE = 1,
MAC_AX_PCIE_DEFAULT = 0xFE,
MAC_AX_PCIE_IGNORE = 0xFF
};
/**
* @enum mac_ax_pcie_clkdly
*
* @brief mac_ax_pcie_clkdly
*
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_0
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_5US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_6US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_11US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_15US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_19US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_25US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_30US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_38US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_50US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_64US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_100US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_128US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_150US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_192US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_200US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_300US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_400US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_500US
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_1MS
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_3MS
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_5MS
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_10MS
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_R_ERR
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_DEF
* Please Place Description here.
* @var mac_ax_pcie_clkdly::MAC_AX_PCIE_CLKDLY_IGNORE
* Please Place Description here.
*/
enum mac_ax_pcie_clkdly {
MAC_AX_PCIE_CLKDLY_0 = 0,
MAC_AX_PCIE_CLKDLY_5US = 1,
MAC_AX_PCIE_CLKDLY_6US = 2,
MAC_AX_PCIE_CLKDLY_11US = 3,
MAC_AX_PCIE_CLKDLY_15US = 4,
MAC_AX_PCIE_CLKDLY_19US = 5,
MAC_AX_PCIE_CLKDLY_25US = 6,
MAC_AX_PCIE_CLKDLY_30US = 7,
MAC_AX_PCIE_CLKDLY_38US = 8,
MAC_AX_PCIE_CLKDLY_50US = 9,
MAC_AX_PCIE_CLKDLY_64US = 10,
MAC_AX_PCIE_CLKDLY_100US = 11,
MAC_AX_PCIE_CLKDLY_128US = 12,
MAC_AX_PCIE_CLKDLY_150US = 13,
MAC_AX_PCIE_CLKDLY_192US = 14,
MAC_AX_PCIE_CLKDLY_200US = 15,
MAC_AX_PCIE_CLKDLY_300US = 16,
MAC_AX_PCIE_CLKDLY_400US = 17,
MAC_AX_PCIE_CLKDLY_500US = 18,
MAC_AX_PCIE_CLKDLY_1MS = 19,
MAC_AX_PCIE_CLKDLY_3MS = 20,
MAC_AX_PCIE_CLKDLY_5MS = 21,
MAC_AX_PCIE_CLKDLY_10MS = 22,
MAC_AX_PCIE_CLKDLY_R_ERR = 0xFD,
MAC_AX_PCIE_CLKDLY_DEF = 0xFE,
MAC_AX_PCIE_CLKDLY_IGNORE = 0xFF
};
/**
* @enum mac_ax_rx_ch
*
* @brief mac_ax_rx_ch
*
* @var mac_ax_rx_ch::MAC_AX_RX_CH_RXQ
* Please Place Description here.
* @var mac_ax_rx_ch::MAC_AX_RX_CH_RPQ
* Please Place Description here.
* @var mac_ax_rx_ch::MAC_AX_RX_CH_NUM
* Please Place Description here.
*/
enum mac_ax_rx_ch {
MAC_AX_RX_CH_RXQ = 0,
MAC_AX_RX_CH_RPQ,
MAC_AX_RX_CH_NUM
};
/**
* @enum mac_ax_pcie_l1dly
*
* @brief mac_ax_pcie_l1dly
*
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_16US
* Please Place Description here.
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_32US
* Please Place Description here.
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_64US
* Please Place Description here.
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_INFI
* Please Place Description here.
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_R_ERR
* Please Place Description here.
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_DEF
* Please Place Description here.
* @var mac_ax_pcie_l1dly::MAC_AX_PCIE_L1DLY_IGNORE
* Please Place Description here.
*/
enum mac_ax_pcie_l1dly {
MAC_AX_PCIE_L1DLY_16US = 0,
MAC_AX_PCIE_L1DLY_32US = 1,
MAC_AX_PCIE_L1DLY_64US = 2,
MAC_AX_PCIE_L1DLY_INFI = 3,
MAC_AX_PCIE_L1DLY_R_ERR = 0xFD,
MAC_AX_PCIE_L1DLY_DEF = 0xFE,
MAC_AX_PCIE_L1DLY_IGNORE = 0xFF
};
/**
* @enum mac_ax_pcie_l0sdly
*
* @brief mac_ax_pcie_l0sdly
*
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_1US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_2US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_3US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_4US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_5US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_6US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_7US
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_R_ERR
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_DEF
* Please Place Description here.
* @var mac_ax_pcie_l0sdly::MAC_AX_PCIE_L0SDLY_IGNORE
* Please Place Description here.
*/
enum mac_ax_pcie_l0sdly {
MAC_AX_PCIE_L0SDLY_1US = 0,
MAC_AX_PCIE_L0SDLY_2US = 1,
MAC_AX_PCIE_L0SDLY_3US = 2,
MAC_AX_PCIE_L0SDLY_4US = 3,
MAC_AX_PCIE_L0SDLY_5US = 4,
MAC_AX_PCIE_L0SDLY_6US = 5,
MAC_AX_PCIE_L0SDLY_7US = 6,
MAC_AX_PCIE_L0SDLY_R_ERR = 0xFD,
MAC_AX_PCIE_L0SDLY_DEF = 0xFE,
MAC_AX_PCIE_L0SDLY_IGNORE = 0xFF
};
/**
* @enum mac_ax_pcie_ltr_spc
*
* @brief mac_ax_pcie_ltr_spc
*
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_10US
* Please Place Description here.
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_100US
* Please Place Description here.
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_500US
* Please Place Description here.
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_1MS
* Please Place Description here.
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_R_ERR
* Please Place Description here.
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_DEF
* Please Place Description here.
* @var mac_ax_pcie_ltr_spc::MAC_AX_PCIE_LTR_SPC_IGNORE
* Please Place Description here.
*/
enum mac_ax_pcie_ltr_spc {
MAC_AX_PCIE_LTR_SPC_10US = 0,
MAC_AX_PCIE_LTR_SPC_100US = 1,
MAC_AX_PCIE_LTR_SPC_500US = 2,
MAC_AX_PCIE_LTR_SPC_1MS = 3,
MAC_AX_PCIE_LTR_SPC_R_ERR = 0xFD,
MAC_AX_PCIE_LTR_SPC_DEF = 0xFE,
MAC_AX_PCIE_LTR_SPC_IGNORE = 0xFF
};
/**
* @enum mac_ax_pcie_ltr_idle_timer
*
* @brief mac_ax_pcie_ltr_idle_timer
*
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_1US
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_10US
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_100US
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_200US
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_400US
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_800US
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_1_6MS
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_3_2MS
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_R_ERR
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_DEF
* Please Place Description here.
* @var mac_ax_pcie_ltr_idle_timer::MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE
* Please Place Description here.
*/
enum mac_ax_pcie_ltr_idle_timer {
MAC_AX_PCIE_LTR_IDLE_TIMER_1US = 0,
MAC_AX_PCIE_LTR_IDLE_TIMER_10US = 1,
MAC_AX_PCIE_LTR_IDLE_TIMER_100US = 2,
MAC_AX_PCIE_LTR_IDLE_TIMER_200US = 3,
MAC_AX_PCIE_LTR_IDLE_TIMER_400US = 4,
MAC_AX_PCIE_LTR_IDLE_TIMER_800US = 5,
MAC_AX_PCIE_LTR_IDLE_TIMER_1_6MS = 6,
MAC_AX_PCIE_LTR_IDLE_TIMER_3_2MS = 7,
MAC_AX_PCIE_LTR_IDLE_TIMER_R_ERR = 0xFD,
MAC_AX_PCIE_LTR_IDLE_TIMER_DEF = 0xFE,
MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE = 0xFF
};
/**
* @enum mac_ax_pcie_ltr_sw_ctrl
*
* @brief mac_ax_pcie_ltr_sw_ctrl
*
* @var mac_ax_pcie_ltr_sw_ctrl::MAC_AX_PCIE_LTR_SW_ACT
* Please Place Description here.
* @var mac_ax_pcie_ltr_sw_ctrl::MAC_AX_PCIE_LTR_SW_IDLE
* Please Place Description here.
*/
enum mac_ax_pcie_ltr_sw_ctrl {
MAC_AX_PCIE_LTR_SW_ACT,
MAC_AX_PCIE_LTR_SW_IDLE
};
/**
* @enum mac_ax_sdio_clk_mon
*
* @brief mac_ax_sdio_clk_mon
*
* @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_SHORT
* Please Place Description here.
* @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_LONG
* Please Place Description here.
* @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_USER_DEFINE
* Please Place Description here.
* @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_LAST
* Please Place Description here.
* @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_MAX
* Please Place Description here.
* @var mac_ax_sdio_clk_mon::MAC_AX_SDIO_CLK_MON_INVALID
* Please Place Description here.
*/
enum mac_ax_sdio_clk_mon {
MAC_AX_SDIO_CLK_MON_SHORT,
MAC_AX_SDIO_CLK_MON_LONG,
MAC_AX_SDIO_CLK_MON_USER_DEFINE,
/* keep last */
MAC_AX_SDIO_CLK_MON_LAST,
MAC_AX_SDIO_CLK_MON_MAX = MAC_AX_SDIO_CLK_MON_LAST,
MAC_AX_SDIO_CLK_MON_INVALID = MAC_AX_SDIO_CLK_MON_LAST,
};
/**
* @enum mac_ax_rx_ppdu_type
*
* @brief mac_ax_rx_ppdu_type
*
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_CCK
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_OFDM
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_HT
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_VHT_SU
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_VHT_MU
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_HE_SU
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_HE_MU
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_HE_TB
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_PPDU_LAST
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_PPDU_MAX
* Please Place Description here.
* @var mac_ax_rx_ppdu_type::MAC_AX_RX_PPDU_INVLAID
* Please Place Description here.
*/
enum mac_ax_rx_ppdu_type {
MAC_AX_RX_CCK,
MAC_AX_RX_OFDM,
MAC_AX_RX_HT,
MAC_AX_RX_VHT_SU,
MAC_AX_RX_VHT_MU,
MAC_AX_RX_HE_SU,
MAC_AX_RX_HE_MU,
MAC_AX_RX_HE_TB,
MAC_AX_RX_PPDU_LAST,
MAC_AX_RX_PPDU_MAX = MAC_AX_RX_PPDU_LAST,
MAC_AX_RX_PPDU_INVLAID = MAC_AX_RX_PPDU_LAST,
};
/**
* @enum mac_ax_net_type
*
* @brief mac_ax_net_type
*
* @var mac_ax_net_type::MAC_AX_NET_TYPE_NO_LINK
* Please Place Description here.
* @var mac_ax_net_type::MAC_AX_NET_TYPE_ADHOC
* Please Place Description here.
* @var mac_ax_net_type::MAC_AX_NET_TYPE_INFRA
* Please Place Description here.
* @var mac_ax_net_type::MAC_AX_NET_TYPE_AP
* Please Place Description here.
*/
enum mac_ax_net_type {
MAC_AX_NET_TYPE_NO_LINK,
MAC_AX_NET_TYPE_ADHOC,
MAC_AX_NET_TYPE_INFRA,
MAC_AX_NET_TYPE_AP
};
/**
* @enum mac_ax_disable_rf_func
*
* @brief mac_ax_disable_rf_func
*
* @var mac_ax_disable_rf_func::MAC_AX_DISABLE_RF_FUNC_FBVR
* Please Place Description here.
* @var mac_ax_disable_rf_func::MAC_AX_DISABLE_RF_FUNC_MAX
* Please Place Description here.
*/
enum mac_ax_disable_rf_func {
MAC_AX_DISABLE_RF_FUNC_FBVR,
MAC_AX_DISABLE_RF_FUNC_MAX
};
/**
* @enum mac_ax_self_role
*
* @brief mac_ax_self_role
*
* @var mac_ax_self_role::MAC_AX_SELF_ROLE_CLIENT
* Please Place Description here.
* @var mac_ax_self_role::MAC_AX_SELF_ROLE_AP
* Please Place Description here.
* @var mac_ax_self_role::MAC_AX_SELF_ROLE_AP_CLIENT
* Please Place Description here.
*/
enum mac_ax_self_role {
MAC_AX_SELF_ROLE_CLIENT,
MAC_AX_SELF_ROLE_AP,
MAC_AX_SELF_ROLE_AP_CLIENT
};
/**
* @enum mac_ax_wifi_role
*
* @brief mac_ax_wifi_role
*
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_NONE
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_STATION
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_AP
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_VAP
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_ADHOC
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_ADHOC_MASTER
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_MESH
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_MONITOR
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_P2P_DEVICE
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_P2P_GC
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_P2P_GO
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_NAN
* Please Place Description here.
* @var mac_ax_wifi_role::MAC_AX_WIFI_ROLE_MLME_MAX
* Please Place Description here.
*/
enum mac_ax_wifi_role {
MAC_AX_WIFI_ROLE_NONE,
MAC_AX_WIFI_ROLE_STATION,
MAC_AX_WIFI_ROLE_AP,
MAC_AX_WIFI_ROLE_VAP,
MAC_AX_WIFI_ROLE_ADHOC,
MAC_AX_WIFI_ROLE_ADHOC_MASTER,
MAC_AX_WIFI_ROLE_MESH,
MAC_AX_WIFI_ROLE_MONITOR,
MAC_AX_WIFI_ROLE_P2P_DEVICE,
MAC_AX_WIFI_ROLE_P2P_GC,
MAC_AX_WIFI_ROLE_P2P_GO,
MAC_AX_WIFI_ROLE_NAN,
MAC_AX_WIFI_ROLE_MLME_MAX
};
/**
* @enum mac_ax_opmode
*
* @brief mac_ax_opmode
*
* @var mac_ax_opmode::MAC_AX_ROLE_CONNECT
* Please Place Description here.
* @var mac_ax_opmode::MAC_AX_ROLE_DISCONN
* Please Place Description here.
*/
enum mac_ax_opmode {
MAC_AX_ROLE_CONNECT,
MAC_AX_ROLE_DISCONN
};
/**
* @enum mac_ax_upd_mode
*
* @brief mac_ax_upd_mode
*
* @var mac_ax_upd_mode::MAC_AX_ROLE_CREATE
* Please Place Description here.
* @var mac_ax_upd_mode::MAC_AX_ROLE_REMOVE
* Please Place Description here.
* @var mac_ax_upd_mode::MAC_AX_ROLE_TYPE_CHANGE
* Please Place Description here.
* @var mac_ax_upd_mode::MAC_AX_ROLE_INFO_CHANGE
* Please Place Description here.
* @var mac_ax_upd_mode::MAC_AX_ROLE_CON_DISCONN
* Please Place Description here.
*/
enum mac_ax_upd_mode {
MAC_AX_ROLE_CREATE,
MAC_AX_ROLE_REMOVE,
MAC_AX_ROLE_TYPE_CHANGE,
MAC_AX_ROLE_INFO_CHANGE,
MAC_AX_ROLE_CON_DISCONN
};
/**
* @enum mac_ax_host_rpr_mode
*
* @brief mac_ax_host_rpr_mode
*
* @var mac_ax_host_rpr_mode::MAC_AX_RPR_MODE_POH
* Please Place Description here.
* @var mac_ax_host_rpr_mode::MAC_AX_RPR_MODE_STF
* Please Place Description here.
*/
enum mac_ax_host_rpr_mode {
MAC_AX_RPR_MODE_POH = 0,
MAC_AX_RPR_MODE_STF
};
#ifndef CONFIG_FW_IO_OFLD_SUPPORT
/**
* @enum rtw_mac_src_cmd_ofld
*
* @brief rtw_mac_src_cmd_ofld
*
* @var rtw_mac_src_cmd_ofld::MAC_AX_BB_CMD_OFLD
* Please Place Description here.
* @var rtw_mac_src_cmd_ofld::MAC_AX_RF_CMD_OFLD
* Please Place Description here.
* @var rtw_mac_src_cmd_ofld::MAC_AX_MAC_CMD_OFLD
* Please Place Description here.
* @var rtw_mac_src_cmd_ofld::MAC_AX_OTHER_CMD_OFLD
* Please Place Description here.
*/
enum rtw_mac_src_cmd_ofld {
RTW_MAC_BB_CMD_OFLD = 0,
RTW_MAC_RF_CMD_OFLD,
RTW_MAC_MAC_CMD_OFLD,
RTW_MAC_OTHER_CMD_OFLD
};
/**
* @enum rtw_mac_cmd_type_ofld
*
* @brief rtw_mac_cmd_type_ofld
*
* @var rtw_mac_cmd_type_ofld::MAC_AX_WRITE_OFLD
* Please Place Description here.
* @var rtw_mac_cmd_type_ofld::MAC_AX_POLLING_OFLD
* Please Place Description here.
* @var rtw_mac_cmd_type_ofld::MAC_AX_DELAY_OFLD
* Please Place Description here.
*/
enum rtw_mac_cmd_type_ofld {
RTW_MAC_WRITE_OFLD = 0,
RTW_MAC_COMPARE_OFLD,
RTW_MAC_DELAY_OFLD
};
/**
* @enum mac_ax_cmd_id
*
* @brief mac_ax_cmd_id
*
* @var mac_ax_host_rpr_mode::MAC_AX_ID_0
* Please Place Description here.
* @var mac_ax_host_rpr_mode::MAC_AX_ID_1
* Please Place Description here.
*/
enum mac_ax_cmd_id {
MAC_AX_ID_0 = 0,
MAC_AX_ID_1
};
/**
* @enum rtw_mac_rf_path
*
* @brief rtw_mac_rf_path
*
* @var rtw_mac_rf_path::RF_PATH_A
* Please Place Description here.
* @var rtw_mac_rf_path::RF_PATH_B
* Please Place Description here.
* @var rtw_mac_rf_path::RF_PATH_C
* Please Place Description here.
* @var rtw_mac_rf_path::RF_PATH_D
* Please Place Description here.
*/
enum rtw_mac_rf_path {
RTW_MAC_RF_PATH_A = 0, //Radio Path A
RTW_MAC_RF_PATH_B, //Radio Path B
RTW_MAC_RF_PATH_C, //Radio Path C
RTW_MAC_RF_PATH_D, //Radio Path D
};
enum rtw_fw_cap {
FW_CAP_IO_OFLD = BIT(0),
};
#endif
/**
* @struct mac_ax_role_opmode
* @brief mac_ax_role_opmode
*
* @var mac_ax_role_opmode::ADD
* Please Place Description here.
* @var mac_ax_role_opmode::CHG
* Please Place Description here.
* @var mac_ax_role_opmode::RMV
* Please Place Description here.
*/
enum mac_ax_role_opmode {
ADD = 0,
CHG,
RMV
};
/*--------------------Define FAST_CH_SW related enum-------------------------------------*/
/**
* @struct mac_ax_fast_ch_sw_status_code
* @brief mac_ax_fast_ch_sw_status_code
*
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_OK
* FAST_CH_SW done without error
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_MALLOC_FAIL
* fail when malloc pkt for part of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_MALLOC_FAIL
* fail when malloc pkt for all of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_READOFLD_FAIL
* fail when reading offloaded pkt for part of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_READOFLD_FAIL
* fail when reading offloaded pkt for all of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_SENDPKT_FAIL
* fail when sending pkt to part of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_SENDPKT_FAIL
* fail when sending pkt to all of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_PART_NO_ACK
* not receiving ack from part of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_ALL_NO_ACK
* not receiving ack from all of stas
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_SWITCH_CH_FAIL
* AP fail to switch channel
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_RF_PARAM_ERR
* AP fail to restore RF params
* @var mac_ax_fast_ch_sw_status_code::MAC_AX_FAST_CH_SW_STATUS_MAX
* Please Place Description here.
*/
enum mac_ax_fast_ch_sw_status_code {
MAC_AX_FAST_CH_SW_STATUS_OK = 0,
MAC_AX_FAST_CH_SW_STATUS_PART_MALLOC_FAIL = 1,
MAC_AX_FAST_CH_SW_STATUS_ALL_MALLOC_FAIL = 2,
MAC_AX_FAST_CH_SW_STATUS_PART_READOFLD_FAIL = 3,
MAC_AX_FAST_CH_SW_STATUS_ALL_READOFLD_FAIL = 4,
MAC_AX_FAST_CH_SW_STATUS_PART_SENDPKT_FAIL = 5,
MAC_AX_FAST_CH_SW_STATUS_ALL_SENDPKT_FAIL = 6,
MAC_AX_FAST_CH_SW_STATUS_PART_NO_ACK = 7,
MAC_AX_FAST_CH_SW_STATUS_ALL_NO_ACK = 8,
MAC_AX_FAST_CH_SW_STATUS_SWITCH_CH_FAIL = 9,
MAC_AX_FAST_CH_SW_STATUS_RF_PARAM_ERR = 10,
MAC_AX_FAST_CH_SW_STATUS_MAX
};
enum mac_ax_fw_state {
FS_SLEEP_IN = 0x10,
FS_ERRHDL_IN = 0x11,
FS_ASSERT_IN = 0x12,
FS_EXCEP_IN = 0x13,
FS_L2ERR_IN = 0x14,
FS_L2ERR_CPU_IN = 0x15,//CPU address hole
FS_L2ERR_HCI_IN = 0x16,//HCI timeout
FS_L2ERR_ELSE_IN = 0x17,
FS_WOW_FWDL_IN = 0x18,
FS_SLEEP_OUT = 0x80,
FS_ERRHDL_OUT = 0x81,
FS_ASSERT_OUT = 0x82,
//rsvd: 0xFFFFFF83
FS_L2ERR_OUT = 0x84,
// Defeature
FS_DEFEA_RXNSS = 0xEA01,
FS_DEFEA_BW5 = 0xEA02,
FS_DEFEA_BW10 = 0xEA03,
FS_DEFEA_BW20 = 0xEA04,
FS_DEFEA_BW40 = 0xEA05,
FS_DEFEA_BW80 = 0xEA06,
FS_DEFEA_BW160 = 0xEA07,
FS_DEFEA_TXNSS = 0xEA08,
FS_DEFEA_PTCL = 0xEA09,
FS_DEFEA_DBLABORT = 0xEA0A,
};
enum mac_ax_dev2hst_gpio {
MAC_AX_DEV2HST_GPIO_OUTPUT = 0,
MAC_AX_DEV2HST_GPIO_INPUT = 1,
MAC_AX_DEV2HST_GPIO_MAX
};
enum mac_ax_dev2hst_active {
MAC_AX_DEV2HST_LOW_ACTIVE = 0,
MAC_AX_DEV2HST_HIGH_ACTIVE = 1,
MAC_AX_DEV2HST_ACTIVE_MAX
};
enum mac_ax_dev2hst_toggle_pulse {
MAC_AX_DEV2HST_TOGGLE = 0,
MAC_AX_DEV2HST_PULSE = 1,
MAC_AX_DEV2HST_TOGGLE_PULSE_MAX
};
enum mac_ax_dev2hst_time_unit {
MAC_AX_DEV2HST_US = 0,
MAC_AX_DEV2HST_MS = 1,
MAC_AX_DEV2HST_TIME_UNIT_MAX
};
/**
* @enum h2c_buf_class
*
* @brief h2c_buf_class
*
* @var h2c_buf_class::H2CB_CLASS_CMD
* Please Place Description here.
* @var h2c_buf_class::H2CB_CLASS_DATA
* Please Place Description here.
* @var h2c_buf_class::H2CB_CLASS_LONG_DATA
* Please Place Description here.
* @var h2c_buf_class::H2CB_CLASS_LAST
* Please Place Description here.
* @var h2c_buf_class::H2CB_CLASS_MAX
* Please Place Description here.
* @var h2c_buf_class::H2CB_CLASS_INVALID
* Please Place Description here.
*/
enum h2c_buf_class {
H2CB_CLASS_CMD, /* FW command */
H2CB_CLASS_DATA, /* FW command + data */
H2CB_CLASS_LONG_DATA, /* FW command + long data */
/* keep last */
H2CB_CLASS_LAST,
H2CB_CLASS_MAX = H2CB_CLASS_LAST,
H2CB_CLASS_INVALID = H2CB_CLASS_LAST,
};
/*--------------------Define Power Saving related enum-------------------------------------*/
/**
* @enum mac_ax_listern_bcn_mode
*
* @brief mac_ax_listern_bcn_mode
*
* @var mac_ax_listern_bcn_mode::MAC_AX_RLBM_MIN
* Please Place Description here.
* @var mac_ax_listern_bcn_mode::MAC_AX_RLBM_MAX
* Please Place Description here.
* @var mac_ax_listern_bcn_mode::MAC_AX_RLBM_USERDEFINE
* Please Place Description here.
*/
enum mac_ax_listern_bcn_mode {
MAC_AX_RLBM_MIN = 0,
MAC_AX_RLBM_MAX = 1,
MAC_AX_RLBM_USERDEFINE = 2,
};
/**
* @enum mac_ax_smart_ps_mode
*
* @brief mac_ax_smart_ps_mode
*
* @var mac_ax_smart_ps_mode::MAC_AX_SMART_PS_MODE_LEGACY_PWR1
* Please Place Description here.
* @var mac_ax_smart_ps_mode::MAC_AX_SMART_PS_MODE_TRX_PWR0
* Please Place Description here.
*/
enum mac_ax_smart_ps_mode {
MAC_AX_SMART_PS_MODE_LEGACY_PWR1 = 0,
MAC_AX_SMART_PS_MODE_TRX_PWR0 = 1,
};
/*--------------------Define Struct-------------------------------------*/
/**
* @struct mac_ax_sch_tx_en
* @brief mac_ax_sch_tx_en
*
* @var mac_ax_sch_tx_en::be0
* Please Place Description here.
* @var mac_ax_sch_tx_en::bk0
* Please Place Description here.
* @var mac_ax_sch_tx_en::vi0
* Please Place Description here.
* @var mac_ax_sch_tx_en::vo0
* Please Place Description here.
* @var mac_ax_sch_tx_en::be1
* Please Place Description here.
* @var mac_ax_sch_tx_en::bk1
* Please Place Description here.
* @var mac_ax_sch_tx_en::vi1
* Please Place Description here.
* @var mac_ax_sch_tx_en::vo1
* Please Place Description here.
* @var mac_ax_sch_tx_en::mg0
* Please Place Description here.
* @var mac_ax_sch_tx_en::mg1
* Please Place Description here.
* @var mac_ax_sch_tx_en::mg2
* Please Place Description here.
* @var mac_ax_sch_tx_en::hi
* Please Place Description here.
* @var mac_ax_sch_tx_en::bcn
* Please Place Description here.
* @var mac_ax_sch_tx_en::ul
* Please Place Description here.
* @var mac_ax_sch_tx_en::twt0
* Please Place Description here.
* @var mac_ax_sch_tx_en::twt1
* Please Place Description here.
*/
struct mac_ax_sch_tx_en {
u8 be0:1;
u8 bk0:1;
u8 vi0:1;
u8 vo0:1;
u8 be1:1;
u8 bk1:1;
u8 vi1:1;
u8 vo1:1;
u8 mg0:1;
u8 mg1:1;
u8 mg2:1;
u8 hi:1;
u8 bcn:1;
u8 ul:1;
u8 twt0:1;
u8 twt1:1;
};
/**
* @struct mac_ax_hw_info
* @brief mac_ax_hw_info
*
* @var mac_ax_hw_info::done
* Please Place Description here.
* @var mac_ax_hw_info::chip_id
* Please Place Description here.
* @var mac_ax_hw_info::cv
* Please Place Description here.
* @var mac_ax_hw_info::intf
* Please Place Description here.
* @var mac_ax_hw_info::tx_ch_num
* Please Place Description here.
* @var mac_ax_hw_info::tx_data_ch_num
* Please Place Description here.
* @var mac_ax_hw_info::wd_body_len
* Please Place Description here.
* @var mac_ax_hw_info::wd_info_len
* Please Place Description here.
* @var mac_ax_hw_info::pwr_on_seq
* Please Place Description here.
* @var mac_ax_hw_info::pwr_off_seq
* Please Place Description here.
* @var mac_ax_hw_info::pwr_seq_ver
* Please Place Description here.
* @var mac_ax_hw_info::fifo_size
* Please Place Description here.
* @var mac_ax_hw_info::macid_num
* Please Place Description here.
* @var mac_ax_hw_info::bssid_num
* Please Place Description here.
* @var mac_ax_hw_info::wl_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::log_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::limit_efuse_size_pcie
* Please Place Description here.
* @var mac_ax_hw_info::limit_efuse_size_usb
* Please Place Description here.
* @var mac_ax_hw_info::limit_efuse_size_sdio
* Please Place Description here.
* @var mac_ax_hw_info::bt_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::bt_log_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::hidden_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::sec_ctrl_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::sec_data_efuse_size
* Please Place Description here.
* @var mac_ax_hw_info::sec_cam_table
* Please Place Description here.
* @var mac_ax_hw_info::ple_rsvd_space
* Please Place Description here.
* @var mac_ax_hw_info::payload_desc_size
* Please Place Description here.
* @var mac_ax_hw_info::wd_checksum_en
* Please Place Description here.
* @var mac_ax_hw_info::sw_amsdu_max_size
* Please Place Description here.
* @var mac_ax_hw_info::core_swr_volt
* Please Place Description here.
* @var mac_ax_hw_info::core_swr_volt_sel
* Please Place Description here.
*/
struct mac_ax_hw_info {
u8 done;
u8 chip_id;
u8 cv;
enum mac_ax_intf intf;
u8 tx_ch_num;
u8 tx_data_ch_num;
u8 wd_body_len;
u8 wd_info_len;
struct mac_pwr_cfg **pwr_on_seq;
struct mac_pwr_cfg **pwr_off_seq;
u8 pwr_seq_ver;
u32 fifo_size;
u16 macid_num;
u8 port_num;
u8 mbssid_num;
u8 bssid_num;
u32 wl_efuse_size;
u32 efuse_size;
u32 log_efuse_size;
u32 limit_efuse_size_pcie;
u32 limit_efuse_size_usb;
u32 limit_efuse_size_sdio;
u32 bt_efuse_size;
u32 bt_log_efuse_size;
u8 hidden_efuse_size;
u32 sec_ctrl_efuse_size;
u32 sec_data_efuse_size;
struct sec_cam_table_t *sec_cam_table;
struct sec_cam_table_t *sec_cam_table_bk;
u8 ple_rsvd_space;
u8 payload_desc_size;
u8 efuse_version_size;
u32 dav_full_efuse_size;
u32 dav_efuse_size;
u32 dav_hidden_efuse_size;
u32 dav_log_efuse_size;
u32 wl_efuse_start_addr;
u32 dav_efuse_start_addr;
u32 bt_efuse_start_addr;
u8 wd_checksum_en;
u32 sw_amsdu_max_size;
u32 (*pwr_on)(void *vadapter);
u32 (*pwr_off)(void *vadapter);
u32 ind_aces_cnt;
u32 dbg_port_cnt;
u8 core_swr_volt;
enum mac_ax_core_swr_volt core_swr_volt_sel;
mac_ax_mutex ind_access_lock;
mac_ax_mutex lte_rlock;
mac_ax_mutex lte_wlock;
mac_ax_mutex dbg_port_lock;
mac_ax_mutex err_set_lock;
mac_ax_mutex err_get_lock;
mac_ax_mutex dbi_lock;
mac_ax_mutex mdio_lock;
};
/**
* @struct mac_ax_fw_info
* @brief mac_ax_fw_info
*
* @var mac_ax_fw_info::major_ver
* Please Place Description here.
* @var mac_ax_fw_info::minor_ver
* Please Place Description here.
* @var mac_ax_fw_info::sub_ver
* Please Place Description here.
* @var mac_ax_fw_info::sub_idx
* Please Place Description here.
* @var mac_ax_fw_info::build_year
* Please Place Description here.
* @var mac_ax_fw_info::build_mon
* Please Place Description here.
* @var mac_ax_fw_info::build_date
* Please Place Description here.
* @var mac_ax_fw_info::build_hour
* Please Place Description here.
* @var mac_ax_fw_info::build_min
* Please Place Description here.
* @var mac_ax_fw_info::h2c_seq
* Please Place Description here.
* @var mac_ax_fw_info::rec_seq
* Please Place Description here.
* @var mac_ax_fw_info::seq_lock
* Please Place Description here.
*/
struct mac_ax_fw_info {
u8 major_ver;
u8 minor_ver;
u8 sub_ver;
u8 sub_idx;
u16 build_year;
u16 build_mon;
u16 build_date;
u16 build_hour;
u16 build_min;
u8 h2c_seq;
u8 rec_seq;
mac_ax_mutex seq_lock;
mac_ax_mutex msg_reg;
};
/**
* @struct mac_ax_h2c_agg_node
* @brief mac_ax_h2c_agg_node
*
* @var mac_ax_h2c_agg_node::next
* Please Place Description here.
* @var mac_ax_h2c_agg_node::h2c_pkt
* Please Place Description here.
*/
struct mac_ax_h2c_agg_node {
struct mac_ax_h2c_agg_node *next;
u8 *h2c_pkt;
};
/**
* @struct mac_ax_h2c_agg_info
* @brief mac_ax_h2c_agg_info
*
* @var mac_ax_h2c_agg_info::h2c_agg_en
* Please Place Description here.
* @var mac_ax_h2c_agg_info::h2c_agg_pkt_num
* Please Place Description here.
* @var mac_ax_h2c_agg_info::h2c_agg_queue_head
* Please Place Description here.
* @var mac_ax_h2c_agg_info::h2c_agg_queue_last
* Please Place Description here.
* @var mac_ax_h2c_agg_info::h2c_agg_lock
* Please Place Description here.
*/
struct mac_ax_h2c_agg_info {
u8 h2c_agg_en;
u32 h2c_agg_pkt_num;
struct mac_ax_h2c_agg_node *h2c_agg_queue_head;
struct mac_ax_h2c_agg_node *h2c_agg_queue_last;
mac_ax_mutex h2c_agg_lock;
};
/**
* @struct mac_ax_mac_pwr_info
* @brief mac_ax_mac_pwr_info
*
* @var mac_ax_mac_pwr_info::pwr_seq_proc
* Please Place Description here.
* @var mac_ax_mac_pwr_info::pwr_in_lps
* Please Place Description here.
* @var mac_ax_mac_pwr_info::intf_pwr_switch
* Please Place Description here.
*/
struct mac_ax_mac_pwr_info {
u8 pwr_seq_proc;
u8 pwr_in_lps;
u32 (*intf_pwr_switch)(void *vadapter,
u8 pre_switch, u8 on);
};
/**
* @struct mac_ax_ft_status
* @brief mac_ax_ft_status
*
* @var mac_ax_ft_status::mac_ft
* Please Place Description here.
* @var mac_ax_ft_status::status
* Please Place Description here.
* @var mac_ax_ft_status::buf
* Please Place Description here.
* @var mac_ax_ft_status::size
* Please Place Description here.
*/
struct mac_ax_ft_status {
enum mac_ax_feature mac_ft;
enum mac_ax_status status;
u8 *buf;
u32 size;
};
/**
* @struct mac_ax_dle_info
* @brief mac_ax_dle_info
*
* @var mac_ax_dle_info::qta_mode
* Please Place Description here.
* @var mac_ax_dle_info::wde_pg_size
* Please Place Description here.
* @var mac_ax_dle_info::ple_pg_size
* Please Place Description here.
* @var mac_ax_dle_info::c0_rx_qta
* Please Place Description here.
* @var mac_ax_dle_info::c1_rx_qta
* Please Place Description here.
*/
struct mac_ax_dle_info {
enum mac_ax_qta_mode qta_mode;
u16 wde_pg_size;
u16 ple_pg_size;
u16 c0_rx_qta;
u16 c1_rx_qta;
u16 c0_ori_max;
u16 c1_ori_max;
u16 c0_tx_min;
u16 c1_tx_min;
};
/**
* @struct mac_ax_gpio_info
* @brief mac_ax_gpio_info
*
* @var mac_ax_gpio_info::sw_io_0
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_1
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_2
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_3
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_4
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_5
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_6
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_7
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_8
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_9
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_10
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_11
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_12
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_13
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_14
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_15
* Please Place Description here.
* @var mac_ax_gpio_info::uart_tx_gpio5
* Please Place Description here.
* @var mac_ax_gpio_info::uart_tx_gpio7
* Please Place Description here.
* @var mac_ax_gpio_info::uart_tx_gpio8
* Please Place Description here.
* @var mac_ax_gpio_info::uart_rx_gpio6
* Please Place Description here.
* @var mac_ax_gpio_info::uart_rx_gpio14
* Please Place Description here.
* @var mac_ax_gpio_info::status
* Please Place Description here.
* @var mac_ax_gpio_info::sw_io_output
* Please Place Description here.
*/
struct mac_ax_gpio_info {
#define MAC_AX_GPIO_NUM 19
/* byte0 */
u8 sw_io_0:1;
u8 sw_io_1:1;
u8 sw_io_2:1;
u8 sw_io_3:1;
u8 sw_io_4:1;
u8 sw_io_5:1;
u8 sw_io_6:1;
u8 sw_io_7:1;
/* byte1 */
u8 sw_io_8:1;
u8 sw_io_9:1;
u8 sw_io_10:1;
u8 sw_io_11:1;
u8 sw_io_12:1;
u8 sw_io_13:1;
u8 sw_io_14:1;
u8 sw_io_15:1;
/* byte2 */
u8 uart_tx_gpio5:1;
u8 uart_tx_gpio7:1;
u8 uart_tx_gpio8:1;
u8 uart_rx_gpio6:1;
u8 uart_rx_gpio14:1;
enum rtw_mac_gfunc status[MAC_AX_GPIO_NUM];
#define MAC_AX_SW_IO_OUT_PP 0
#define MAC_AX_SW_IO_OUT_OD 1
u8 sw_io_output[MAC_AX_GPIO_NUM];
};
/**
* @struct mac_ax_trx_info
* @brief mac_ax_trx_info
*
* @var mac_ax_trx_info::trx_mode
* Please Place Description here.
* @var mac_ax_trx_info::qta_mode
* Please Place Description here.
* @var mac_ax_trx_info::rpr_cfg
* Please Place Description here.
*/
struct mac_ax_trx_info {
enum mac_ax_trx_mode trx_mode;
enum mac_ax_qta_mode qta_mode;
struct mac_ax_host_rpr_cfg *rpr_cfg;
};
/**
* @struct mac_ax_fwdl_info
* @brief mac_ax_fwdl_info
*
* @var mac_ax_fwdl_info::fw_en
* Please Place Description here.
* @var mac_ax_fwdl_info::dlrom_en
* Please Place Description here.
* @var mac_ax_fwdl_info::dlram_en
* Please Place Description here.
* @var mac_ax_fwdl_info::fw_from_hdr
* Please Place Description here.
* @var mac_ax_fwdl_info::fw_cat
* Please Place Description here.
* @var mac_ax_fwdl_info::rom_buff
* Please Place Description here.
* @var mac_ax_fwdl_info::rom_size
* Please Place Description here.
* @var mac_ax_fwdl_info::ram_buff
* Please Place Description here.
* @var mac_ax_fwdl_info::ram_size
* Please Place Description here.
*/
struct mac_ax_fwdl_info {
u8 fw_en;
u8 dlrom_en;
u8 dlram_en;
u8 fw_from_hdr;
enum rtw_fw_type fw_cat;
u8 *rom_buff;
u32 rom_size;
u8 *ram_buff;
u32 ram_size;
};
/**
* @struct mac_ax_txdma_ch_map
* @brief mac_ax_txdma_ch_map
*
* @var mac_ax_txdma_ch_map::ch0
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch1
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch2
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch3
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch4
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch5
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch6
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch7
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch8
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch9
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch10
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch11
* Please Place Description here.
* @var mac_ax_txdma_ch_map::ch12
* Please Place Description here.
*/
struct mac_ax_txdma_ch_map {
enum mac_ax_pcie_func_ctrl ch0;
enum mac_ax_pcie_func_ctrl ch1;
enum mac_ax_pcie_func_ctrl ch2;
enum mac_ax_pcie_func_ctrl ch3;
enum mac_ax_pcie_func_ctrl ch4;
enum mac_ax_pcie_func_ctrl ch5;
enum mac_ax_pcie_func_ctrl ch6;
enum mac_ax_pcie_func_ctrl ch7;
enum mac_ax_pcie_func_ctrl ch8;
enum mac_ax_pcie_func_ctrl ch9;
enum mac_ax_pcie_func_ctrl ch10;
enum mac_ax_pcie_func_ctrl ch11;
enum mac_ax_pcie_func_ctrl ch12;
};
/**
* @struct mac_ax_rxdma_ch_map
* @brief mac_ax_rxdma_ch_map
*
* @var mac_ax_rxdma_ch_map::rxq
* Please Place Description here.
* @var mac_ax_rxdma_ch_map::rpq
* Please Place Description here.
*/
struct mac_ax_rxdma_ch_map {
enum mac_ax_pcie_func_ctrl rxq;
enum mac_ax_pcie_func_ctrl rpq;
};
/**
* @struct mac_ax_intf_info
* @brief mac_ax_intf_info
*
* @var mac_ax_intf_info::txbd_trunc_mode
* Please Place Description here.
* @var mac_ax_intf_info::rxbd_trunc_mode
* Please Place Description here.
* @var mac_ax_intf_info::rxbd_mode
* Please Place Description here.
* @var mac_ax_intf_info::tag_mode
* Please Place Description here.
* @var mac_ax_intf_info::tx_burst
* Please Place Description here.
* @var mac_ax_intf_info::rx_burst
* Please Place Description here.
* @var mac_ax_intf_info::wd_dma_idle_intvl
* Please Place Description here.
* @var mac_ax_intf_info::wd_dma_act_intvl
* Please Place Description here.
* @var mac_ax_intf_info::multi_tag_num
* Please Place Description here.
* @var mac_ax_intf_info::rx_sep_append_len
* Please Place Description here.
* @var mac_ax_intf_info::txbd_buf
* Please Place Description here.
* @var mac_ax_intf_info::rxbd_buf
* Please Place Description here.
* @var mac_ax_intf_info::skip_all
* Please Place Description here.
* @var mac_ax_intf_info::txch_map
* Please Place Description here.
* @var mac_ax_intf_info::lbc_en
* Please Place Description here.
* @var mac_ax_intf_info::lbc_tmr
* Please Place Description here.
* @var mac_ax_intf_info::autok_en
* Please Place Description here.
*/
struct mac_ax_intf_info {
enum mac_ax_bd_trunc_mode txbd_trunc_mode;
enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
enum mac_ax_rxbd_mode rxbd_mode;
enum mac_ax_tag_mode tag_mode;
enum mac_ax_tx_burst tx_burst;
enum mac_ax_rx_burst rx_burst;
enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
enum mac_ax_multi_tag_num multi_tag_num;
u16 rx_sep_append_len;
u8 *txbd_buf;
u8 *rxbd_buf;
u8 skip_all;
struct mac_ax_txdma_ch_map *txch_map;
enum mac_ax_pcie_func_ctrl lbc_en;
enum mac_ax_lbc_tmr lbc_tmr;
enum mac_ax_pcie_func_ctrl autok_en;
enum mac_ax_pcie_func_ctrl io_rcy_en;
enum mac_ax_io_rcy_tmr io_rcy_tmr;
};
/**
* @struct mac_ax_pcie_trx_mitigation
* @brief mac_ax_pcie_trx_mitigation
*
* @var mac_ax_pcie_trx_mitigation::txch_map
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::tx_timer_unit
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::tx_timer
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::tx_counter
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::rxch_map
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::rx_timer_unit
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::rx_timer
* Please Place Description here.
* @var mac_ax_pcie_trx_mitigation::rx_counter
* Please Place Description here.
*/
struct mac_ax_pcie_trx_mitigation {
struct mac_ax_txdma_ch_map *txch_map;
enum mac_ax_trx_mitigation_timer_unit tx_timer_unit;
u8 tx_timer;
u8 tx_counter;
struct mac_ax_rxdma_ch_map *rxch_map;
enum mac_ax_trx_mitigation_timer_unit rx_timer_unit;
u8 rx_timer;
u8 rx_counter;
};
/**
* @struct mac_mu_table
* @brief mac_mu_table
*
* @var mac_mu_table::mu_score_tbl_ctrl
* Please Place Description here.
* @var mac_mu_table::mu_score_tbl_0
* Please Place Description here.
* @var mac_mu_table::mu_score_tbl_1
* Please Place Description here.
* @var mac_mu_table::mu_score_tbl_2
* Please Place Description here.
* @var mac_mu_table::mu_score_tbl_3
* Please Place Description here.
* @var mac_mu_table::mu_score_tbl_4
* Please Place Description here.
* @var mac_mu_table::mu_score_tbl_5
* Please Place Description here.
*/
struct mac_mu_table {
u32 mu_score_tbl_ctrl;
u32 mu_score_tbl_0;
u32 mu_score_tbl_1;
u32 mu_score_tbl_2;
u32 mu_score_tbl_3;
u32 mu_score_tbl_4;
u32 mu_score_tbl_5;
};
/**
* @struct mac_ax_ss_dl_grp_upd
* @brief mac_ax_ss_dl_grp_upd
*
* @var mac_ax_ss_dl_grp_upd::grp_valid
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::grp_id
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::is_hwgrp
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::rsvd
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u0
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u1
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u2
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u3
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u4
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u5
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u6
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::macid_u7
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u0
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u1
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u2
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u3
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u4
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u5
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u6
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::ac_bitmap_u7
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::next_protecttype
* Please Place Description here.
* @var mac_ax_ss_dl_grp_upd::next_rsptype
* Please Place Description here.
*/
struct mac_ax_ss_dl_grp_upd {
u8 grp_valid:1; //0: non valid 1: valid
u8 grp_id:5; //grp 0~16
u8 is_hwgrp:1;
u8 rsvd:1;
u8 macid_u0;
u8 macid_u1;
u8 macid_u2;
u8 macid_u3;
u8 macid_u4;
u8 macid_u5;
u8 macid_u6;
u8 macid_u7;
u8 ac_bitmap_u0:4;
u8 ac_bitmap_u1:4;
u8 ac_bitmap_u2:4;
u8 ac_bitmap_u3:4;
u8 ac_bitmap_u4:4;
u8 ac_bitmap_u5:4;
u8 ac_bitmap_u6:4;
u8 ac_bitmap_u7:4;
u8 next_protecttype:4;
u8 next_rsptype:4;
};
/**
* @struct mac_ax_ss_ul_grp_upd
* @brief mac_ax_ss_ul_grp_upd
*
* @var mac_ax_ss_ul_grp_upd::macid_u0
* Please Place Description here.
* @var mac_ax_ss_ul_grp_upd::macid_u1
* Please Place Description here.
* @var mac_ax_ss_ul_grp_upd::grp_bitmap
* Please Place Description here.
*/
struct mac_ax_ss_ul_grp_upd {
u8 macid_u0;
u8 macid_u1;
u16 grp_bitmap;
};
/**
* @struct mac_ax_ss_ul_sta_upd
* @brief mac_ax_ss_ul_sta_upd
*
* @var mac_ax_ss_ul_sta_upd::mode
* Please Place Description here.
* @var mac_ax_ss_ul_sta_upd::rsvd
* Please Place Description here.
* @var mac_ax_ss_ul_sta_upd::macid
* Please Place Description here.
* @var mac_ax_ss_ul_sta_upd::bsr_len
* Please Place Description here.
*/
struct mac_ax_ss_ul_sta_upd {
u32 mode:8; //0:del; 1: add
u32 rsvd:24;
u8 macid[4];
u16 bsr_len[2];
};
/**
* @struct mac_ax_2nav_info
* @brief mac_ax_2nav_info
*
* @var mac_ax_2nav_info::plcp_upd_nav_en
* Please Place Description here.
* @var mac_ax_2nav_info::tgr_fram_upd_nav_en
* Please Place Description here.
* @var mac_ax_2nav_info::nav_up
* Please Place Description here.
*/
struct mac_ax_2nav_info {
u8 plcp_upd_nav_en;
u8 tgr_fram_upd_nav_en;
u8 nav_up;
};
/**
* @struct mac_ax_bcn_info
* @brief mac_ax_bcn_info
*
* @var mac_ax_bcn_info::port
* Please Place Description here.
* @var mac_ax_bcn_info::mbssid
* Please Place Description here.
* @var mac_ax_bcn_info::band
* Please Place Description here.
* @var mac_ax_bcn_info::grp_ie_ofst
* Please Place Description here.
* @var mac_ax_bcn_info::macid
* Please Place Description here.
* @var mac_ax_bcn_info::ssn_sel
* Please Place Description here.
* @var mac_ax_bcn_info::ssn_mode
* Please Place Description here.
* @var mac_ax_bcn_info::rate_sel
* Please Place Description here.
* @var mac_ax_bcn_info::txpwr
* Please Place Description here.
* @var mac_ax_bcn_info::txinfo_ctrl_en
* Please Place Description here.
* @var mac_ax_bcn_info::ntx_path_en
* Please Place Description here.
* @var mac_ax_bcn_info::path_map_a
* Please Place Description here.
* @var mac_ax_bcn_info::path_map_b
* Please Place Description here.
* @var mac_ax_bcn_info::path_map_c
* Please Place Description here.
* @var mac_ax_bcn_info::path_map_d
* Please Place Description here.
* @var mac_ax_bcn_info::antsel_a
* Please Place Description here.
* @var mac_ax_bcn_info::antsel_b
* Please Place Description here.
* @var mac_ax_bcn_info::antsel_c
* Please Place Description here.
* @var mac_ax_bcn_info::antsel_d
* Please Place Description here.
* @var mac_ax_bcn_info::sw_tsf
* Please Place Description here.
* @var mac_ax_bcn_info::pld_buf
* Please Place Description here.
* @var mac_ax_bcn_info::pld_len
* Please Place Description here.
* @var mac_ax_bcn_info::csa_ofst
* Please Place Description here.
*/
struct mac_ax_bcn_info {
u8 port;
u8 mbssid;
u8 band;
u8 grp_ie_ofst;
u8 macid;
u8 ssn_sel;
u8 ssn_mode;
u16 rate_sel;
u8 txpwr;
u8 txinfo_ctrl_en;
u8 ntx_path_en;
u8 path_map_a;
u8 path_map_b;
u8 path_map_c;
u8 path_map_d;
u8 antsel_a;
u8 antsel_b;
u8 antsel_c;
u8 antsel_d;
u8 sw_tsf;
u8 *pld_buf;
u16 pld_len;
u16 csa_ofst;
};
/**
* @struct mac_ax_twt_para
* @brief mac_ax_twt_para
*
* @var mac_ax_twt_para::nego_tp
* Please Place Description here.
* @var mac_ax_twt_para::act
* Please Place Description here.
* @var mac_ax_twt_para::trig
* Please Place Description here.
* @var mac_ax_twt_para::flow_tp
* Please Place Description here.
* @var mac_ax_twt_para::proct
* Please Place Description here.
* @var mac_ax_twt_para::flow_id
* Please Place Description here.
* @var mac_ax_twt_para::id
* Please Place Description here.
* @var mac_ax_twt_para::wake_exp
* Please Place Description here.
* @var mac_ax_twt_para::band
* Please Place Description here.
* @var mac_ax_twt_para::port
* Please Place Description here.
* @var mac_ax_twt_para::rsp_pm
* Please Place Description here.
* @var mac_ax_twt_para::wake_unit
* Please Place Description here.
* @var mac_ax_twt_para::impt
* Please Place Description here.
* @var mac_ax_twt_para::twtulfixmode
* Please Place Description here.
* @var mac_ax_twt_para::rsvd
* Please Place Description here.
* @var mac_ax_twt_para::wake_man
* Please Place Description here.
* @var mac_ax_twt_para::dur
* Please Place Description here.
* @var mac_ax_twt_para::trgt_l
* Please Place Description here.
* @var mac_ax_twt_para::trgt_h
* Please Place Description here.
*/
struct mac_ax_twt_para {
enum mac_ax_twt_nego_tp nego_tp;
enum mac_ax_twt_act_tp act;
u32 trig:1;
u32 flow_tp:1;
u32 proct:1;
u32 flow_id:3;
u32 id:3;
u32 wake_exp:5;
u32 band:1;
u32 port:3;
u32 rsp_pm:1;
u32 wake_unit:1;
u32 impt:1;
u32 twtulfixmode:3;
u32 rsvd:8;
u16 wake_man;
u8 dur;
u32 trgt_l;
u32 trgt_h;
};
/**
* @struct mac_ax_twtact_para
* @brief mac_ax_twtact_para
*
* @var mac_ax_twtact_para::act
* Please Place Description here.
* @var mac_ax_twtact_para::macid
* Please Place Description here.
* @var mac_ax_twtact_para::id
* Please Place Description here.
* @var mac_ax_twtact_para::rsvd
* Please Place Description here.
*/
struct mac_ax_twtact_para {
enum mac_ax_twtact_act_tp act;
u16 macid;
u8 id:3;
u8 rsvd:5;
};
/**
* @struct mac_ax_twtanno_para
* @brief mac_ax_twtanno_para
*
* @var mac_ax_twtanno_para::macid
* Please Place Description here.
*/
struct mac_ax_twtanno_para {
u8 macid;
};
/**
* @struct mac_ax_twtanno_c2hpara
* @brief mac_ax_twtanno_c2hpara
*
* @var mac_ax_twtanno_c2hpara::wait_case
* Please Place Description here.
* @var mac_ax_twtanno_c2hpara::rsvd
* Please Place Description here.
* @var mac_ax_twtanno_c2hpara::macid0
* Please Place Description here.
* @var mac_ax_twtanno_c2hpara::macid1
* Please Place Description here.
* @var mac_ax_twtanno_c2hpara::macid2
* Please Place Description here.
*/
struct mac_ax_twtanno_c2hpara {
u32 wait_case:4;
u32 rsvd:4;
u32 macid0:8;
u32 macid1:8;
u32 macid2:8;
};
/**
* @struct mac_ax_port_cfg_para
* @brief mac_ax_port_cfg_para
*
* @var mac_ax_port_cfg_para::mbssid_idx
* Please Place Description here.
* @var mac_ax_port_cfg_para::val
* Please Place Description here.
* @var mac_ax_port_cfg_para::port
* Please Place Description here.
* @var mac_ax_port_cfg_para::band
* Please Place Description here.
*/
struct mac_ax_port_cfg_para {
u32 mbssid_idx;
u32 val;
u8 port;
u8 band;
};
/**
* @struct mac_ax_port_init_para
* @brief mac_ax_port_init_para
*
* @var mac_ax_port_init_para::port_idx
* Please Place Description here.
* @var mac_ax_port_init_para::band_idx
* Please Place Description here.
* @var mac_ax_port_init_para::net_type
* Please Place Description here.
* @var mac_ax_port_init_para::dtim_period
* Please Place Description here.
* @var mac_ax_port_init_para::mbid_num
* Please Place Description here.
* @var mac_ax_port_init_para::bss_color
* Please Place Description here.
* @var mac_ax_port_init_para::bcn_interval
* Please Place Description here.
* @var mac_ax_port_init_para::hiq_win
* Please Place Description here.
*/
struct mac_ax_port_init_para {
enum mac_ax_port port_idx;
enum mac_ax_band band_idx;
enum mac_ax_net_type net_type;
u8 dtim_period;
u8 mbid_num;
u8 bss_color;
u16 bcn_interval;
u32 hiq_win;
};
/**
* @struct mac_ax_fw_log
* @brief mac_ax_fw_log
*
* @var mac_ax_fw_log::level
* Please Place Description here.
* @var mac_ax_fw_log::output
* Please Place Description here.
* @var mac_ax_fw_log::comp
* Please Place Description here.
* @var mac_ax_fw_log::comp_ext
* Please Place Description here.
*/
struct mac_ax_fw_log {
#define MAC_AX_FL_LV_OFF 0
#define MAC_AX_FL_LV_CRT 1
#define MAC_AX_FL_LV_SER 2
#define MAC_AX_FL_LV_WARN 3
#define MAC_AX_FL_LV_LOUD 4
#define MAC_AX_FL_LV_TR 5
u32 level;
#define MAC_AX_FL_LV_UART BIT(0)
#define MAC_AX_FL_LV_C2H BIT(1)
#define MAC_AX_FL_LV_SNI BIT(2)
u32 output;
#define MAC_AX_FL_COMP_VER BIT(0)
#define MAC_AX_FL_COMP_INIT BIT(1)
#define MAC_AX_FL_COMP_TASK BIT(2)
#define MAC_AX_FL_COMP_CNS BIT(3)
#define MAC_AX_FL_COMP_H2C BIT(4)
#define MAC_AX_FL_COMP_C2H BIT(5)
#define MAC_AX_FL_COMP_TX BIT(6)
#define MAC_AX_FL_COMP_RX BIT(7)
#define MAC_AX_FL_COMP_IPSEC BIT(8)
#define MAC_AX_FL_COMP_TIMER BIT(9)
#define MAC_AX_FL_COMP_DBGPKT BIT(10)
#define MAC_AX_FL_COMP_PS BIT(11)
#define MAC_AX_FL_COMP_ERROR BIT(12)
#define MAC_AX_FL_COMP_WOWLAN BIT(13)
#define MAC_AX_FL_COMP_SECURE_BOOT BIT(14)
#define MAC_AX_FL_COMP_BTC BIT(15)
#define MAC_AX_FL_COMP_BB BIT(16)
#define MAC_AX_FL_COMP_TWT BIT(17)
#define MAC_AX_FL_COMP_RF BIT(18)
#define MAC_AX_FL_COMP_MCC BIT(20)
u32 comp;
u32 comp_ext;
};
/**
* @struct mac_ax_dbgpkg
* @brief mac_ax_dbgpkg
*
* @var mac_ax_dbgpkg::ss_dbg_0
* Please Place Description here.
* @var mac_ax_dbgpkg::ss_dbg_1
* Please Place Description here.
*/
struct mac_ax_dbgpkg {
u32 ss_dbg_0;
u32 ss_dbg_1;
};
/**
* @struct mac_ax_dbgport_hw_en
* @brief mac_ax_dbgport_hw_en
*
* @var mac_ax_dbgport_hw_en::system
* Please Place Description here.
* @var mac_ax_dbgport_hw_en::wl_cpu
* Please Place Description here.
*/
struct mac_ax_dbgport_hw_en {
u8 system:1;
u8 pinmux:1;
u8 loader:1;
u8 hmux:1;
u8 pcie:1;
u8 usb:1;
u8 sdio:1;
u8 bt:1;
// WLAN_MAC
u8 axidma:1;
u8 wlphydbg_gpio:1;
u8 btcoexist:1;
u8 ltecoex:1;
u8 wlphydbg:1;
u8 wlan_mac_reg:1;
u8 wlan_mac_pmc:1;
u8 calib_top:1;
//DMAC
u16 dispatcher_top:1;
u16 wde_dle:1;
u16 ple_dle:1;
u16 wdrls:1;
u16 dle_cpuio:1;
u16 bbrpt:1;
u16 txpktctl:1;
u16 pktbuffer:1;
u16 dmac_table:1;
u16 sta_scheduler:1;
u16 dmac_pktin:1;
u16 wsec_top:1;
u16 mpdu_processor:1;
u16 dmac_apb_bridge:1;
u16 ltr_ctrl:1;
u16 rsvd0:1;
//CMAC 0
u8 cmac0_cmac_dma_top:1;
u8 cmac0_ptcltop:1;
u8 cmac0_schedulertop:1;
u8 cmac0_txpwr_ctrl:1;
u8 cmac0_cmac_apb_bridge:1;
u8 cmac0_mactx:1;
u8 cmac0_macrx:1;
u8 cmac0_wmac_trxptcl:1;
//CMAC 1
u8 cmac1_cmac_dma_top:1;
u8 cmac1_ptcltop:1;
u8 cmac1_schedulertop:1;
u8 cmac1_txpwr_ctrl:1;
u8 cmac1_cmac_apb_bridge:1;
u8 cmac1_mactx:1;
u8 cmac1_macrx:1;
u8 cmac1_wmac_trxptcl:1;
//others
u8 cmac_share:1;
u8 wl_cpu:1;
u8 rsvd1:6;
};
/**
* @struct mac_ax_dbgpkg_en
* @brief mac_ax_dbgpkg_en
*
* @var mac_ax_dbgpkg_en::ss_dbg
* Please Place Description here.
* @var mac_ax_dbgpkg_en::dle_dbg
* Please Place Description here.
* @var mac_ax_dbgpkg_en::dmac_dbg
* Please Place Description here.
* @var mac_ax_dbgpkg_en::cmac_dbg
* Please Place Description here.
* @var mac_ax_dbgpkg_en::mac_dbg_port
* Please Place Description here.
* @var mac_ax_dbgpkg_en::plersvd_dbg
* Please Place Description here.
* @var mac_ax_dbgpkg_en::dp_hw_en
* Please Place Description here.
*/
struct mac_ax_dbgpkg_en {
u8 ss_dbg:1;
u8 dle_dbg:1;
u8 dmac_dbg:1;
u8 cmac_dbg:1;
u8 mac_dbg_port:1;
u8 plersvd_dbg:1;
u8 tx_flow_dbg:1;
u8 rsvd:1;
struct mac_ax_dbgport_hw_en dp_hw_en;
};
/**
* @struct mac_ax_dbgport_hw
* @brief mac_ax_dbgport_hw
*
* @var mac_ax_dbgport_hw::dbg_sel
* valid value: enum mac_ax_dbgport_sel
* @var mac_ax_dbgport_hw::dbg_sel_16b
* valid value: enum mac_ax_dbgport_sel0_16b
* enum mac_ax_dbgport_sel1_16b
* @var mac_ax_dbgport_hw::dbg_sel_4b
* valid value: enum mac_ax_dbgport_sel_4b
* @var mac_ax_dbgport_hw::intn_idx
* valid value: #define MAC_AX_DP_INTN_IDX_XXX_XXX
* @var mac_ax_dbgport_hw::mode
* 0x0: for dump mode
* 0x1: for LA mode
* @var mac_ax_dbgport_hw::rsp_val
* return value: debug port info
*/
struct mac_ax_dbgport_hw {
// input
u8 dbg_sel[MAC_AX_DP_SEL_NUM];
u8 dbg_sel_16b[MAC_AX_DP_SEL_NUM];
u8 dbg_sel_4b[MAC_AX_DP_SEL_NUM];
u8 intn_idx[MAC_AX_DP_SEL_NUM];
u8 mode;
// output
u32 rsp_val;
};
/**
* @struct mac_ax_fwdbg_en
* @brief mac_ax_fwdbg_en
*
* @var mac_ax_fwdbg_en::status_dbg
* Please Place Description here.
* @var mac_ax_fwdbg_en::rsv_ple_dbg
* Please Place Description here.
* @var mac_ax_fwdbg_en::ps_dbg
* Please Place Description here.
*/
struct mac_ax_fwdbg_en {
u8 status_dbg:1;
u8 rsv_ple_dbg:1;
u8 ps_dbg:1;
};
union mac_conf_ofld_hioe_param0 {
u32 register_addr;
u32 delay_value;
};
union mac_conf_ofld_hioe_param1 {
u16 byte_data_h;
u16 bit_mask;
};
union mac_conf_ofld_hioe_param2 {
u16 byte_data_l;
u16 bit_data;
};
/**
* @struct mac_conf_ofld_hioe
* @brief mac_conf_ofld_hioe
*
* @var mac_conf_ofld_hioe::hioe_op
* Please Place Description here.
* @var mac_conf_ofld_hioe::inst_type
* Please Place Description here.
* @var mac_conf_ofld_hioe::rsvd
* Please Place Description here.
* @var mac_conf_ofld_hioe::data_mode
* Please Place Description here.
* @var mac_conf_ofld_hioe::param0
* Please Place Description here.
* @var mac_conf_ofld_hioe::param1
* Please Place Description here.
* @var mac_conf_ofld_hioe::param2
* Please Place Description here.
*/
struct mac_conf_ofld_hioe {
#define CONF_OFLD_HIOE_OP_RESTORE 0
#define CONF_OFLD_HIOE_OP_BACKUP 1
#define CONF_OFLD_HIOE_OP_BOTH 2
u8 hioe_op;
#define CONF_OFLD_HIOE_INST_IO 0
#define CONF_OFLD_HIOE_INST_POLLING 1
#define CONF_OFLD_HIOE_INST_DELAY 2
u8 inst_type;
u8 rsvd;
#define CONF_OFLD_HIOE_INST_DATA_BYTE 0
#define CONF_OFLD_HIOE_INST_DATA_BIT 3
u8 data_mode;
union mac_conf_ofld_hioe_param0 param0;
union mac_conf_ofld_hioe_param1 param1;
union mac_conf_ofld_hioe_param2 param2;
};
/**
* @struct mac_conf_ofld_ddma
* @brief mac_conf_ofld_ddma
*
* @var mac_conf_ofld_ddma::ddma_mode
* Please Place Description here.
* @var mac_conf_ofld_ddma::finish
* Please Place Description here.
* @var mac_conf_ofld_ddma::dma_len
* Please Place Description here.
* @var mac_conf_ofld_ddma::dma_src_addr
* Please Place Description here.
* @var mac_conf_ofld_ddma::dma_dst_addr
* Please Place Description here.
*/
struct mac_conf_ofld_ddma {
#define CONF_OFLD_DDMA_OP_RESTORE 0
#define CONF_OFLD_DDMA_OP_BACKUP 1
#define CONF_OFLD_DDMA_OP_BOTH 2
u8 ddma_mode;
u8 finish;
u16 dma_len;
u32 dma_src_addr;
u32 dma_dst_addr;
};
union mac_conf_ofld_req_bd {
struct mac_conf_ofld_hioe hioe;
struct mac_conf_ofld_ddma ddma;
};
/**
* @struct mac_ax_conf_ofld_req
* @brief mac_ax_conf_ofld_req
*
* @var mac_ax_conf_ofld_req::device
* Please Place Description here.
* @var mac_ax_conf_ofld_req::rsvd
* Please Place Description here.
* @var mac_ax_conf_ofld_req::req
* Please Place Description here.
*/
struct mac_ax_conf_ofld_req {
#define CONF_OFLD_DEVICE_HIOE 0
#define CONF_OFLD_DEVICE_DDMA 1
u32 device:8;
u32 rsvd:24;
union mac_conf_ofld_req_bd req;
};
/**
* @struct mac_defeature_value
* @brief mac_defeature_value
*
* @var mac_defeature_value::rx_spatial_stream
* Please Place Description here.
* @var mac_defeature_value::bandwidth
* Please Place Description here.
* @var mac_defeature_value::tx_spatial_stream
* Please Place Description here.
* @var mac_defeature_value::protocol_80211
* Please Place Description here.
* @var mac_defeature_value::NIC_router
* Please Place Description here.
* @var mac_defeature_value::wl_func_support
* Please Place Description here.
* @var mac_defeature_value::hw_special_type
* Please Place Description here.
* @var mac_defeature_value::uuid
* Please Place Description here.
*/
struct mac_defeature_value {
u8 rx_spatial_stream;
u8 bandwidth;
u8 tx_spatial_stream;
u8 protocol_80211;
u8 NIC_router;
u8 wl_func_support;
u8 hw_special_type;
u32 uuid;
};
/**
* @struct mac_ax_wowlan_info
* @brief mac_ax_wowlan_info
*
* @var mac_ax_wowlan_info::aoac_report
* Please Place Description here.
*/
struct mac_ax_wowlan_info {
u8 *aoac_report;
};
/**
* @struct mac_ax_p2p_info
* @brief mac_ax_p2p_info
*
* @var mac_ax_p2p_info::macid
* Please Place Description here.
* @var mac_ax_p2p_info::p2pid
* Please Place Description here.
*/
struct mac_ax_p2p_info {
u8 macid;
u8 run:1;
u8 wait_dack:1;
u8 rsvd:6;
};
/**
* @struct mac_ax_p2p_act_info
* @brief mac_ax_p2p_act_info
*
* @var mac_ax_p2p_act_info::macid
* Please Place Description here.
* @var mac_ax_p2p_act_info::noaid
* Please Place Description here.
* @var mac_ax_p2p_act_info::act
* Please Place Description here.
* @var mac_ax_p2p_act_info::type
* Please Place Description here.
* @var mac_ax_p2p_act_info::all_slep
* Please Place Description here.
* @var mac_ax_p2p_act_info::srt
* Please Place Description here.
* @var mac_ax_p2p_act_info::itvl
* Please Place Description here.
* @var mac_ax_p2p_act_info::dur
* Please Place Description here.
* @var mac_ax_p2p_act_info::cnt
* Please Place Description here.
* @var mac_ax_p2p_act_info::ctw
* Please Place Description here.
*/
struct mac_ax_p2p_act_info {
u8 macid;
u8 noaid;
u8 act;
u8 type;
u8 all_slep;
u32 srt;
u32 itvl;
u32 dur;
u8 cnt;
u16 ctw;
};
struct mac_ax_p2p_macid_info {
u8 main_macid;
u8 ctrl_type;
u8 *bitmap;
u32 bmap_len;
};
struct mac_ax_t32_togl_info {
u8 band;
u8 port;
u8 en;
u16 early;
};
struct mac_ax_t32_togl_rpt {
u8 band;
u8 port;
u8 valid;
u16 early;
u16 status;
u32 tsf_l;
u32 tsf_h;
};
struct mac_ax_port_info {
u8 stat;
#define MAC_AX_PORT_H2C_IDLE 0
#define MAC_AX_PORT_H2C_BUSY 1
#define MAC_AX_PORT_H2C_FAIL 2
u8 h2c_sm;
};
struct mac_ax_int_stats {
u32 h2c_reg_uninit;
u32 h2c_pkt_uninit;
u32 c2h_reg_uninit;
};
/*-------------------- Define Struct needed to be moved-----------------------*/
/**
* @struct mac_ax_tbl_hdr
* @brief mac_ax_tbl_hdr
*
* @var mac_ax_tbl_hdr::rw
* Please Place Description here.
* @var mac_ax_tbl_hdr::idx
* Please Place Description here.
* @var mac_ax_tbl_hdr::offset
* Please Place Description here.
* @var mac_ax_tbl_hdr::len
* Please Place Description here.
* @var mac_ax_tbl_hdr::type
* Please Place Description here.
*/
struct mac_ax_tbl_hdr {
u8 rw:1;
u8 idx:7;
u16 offset:5;
u16 len:10;
u16 type:1;
};
/**
* @struct mac_ax_ru_rate_ent
* @brief mac_ax_ru_rate_ent
*
* @var mac_ax_ru_rate_ent::dcm
* Please Place Description here.
* @var mac_ax_ru_rate_ent::ss
* Please Place Description here.
* @var mac_ax_ru_rate_ent::mcs
* Please Place Description here.
*/
struct mac_ax_ru_rate_ent {
u8 dcm:1;
u8 ss:3;
u8 mcs:4;
};
/**
* @struct mac_ax_dl_fix_sta_ent
* @brief mac_ax_dl_fix_sta_ent
*
* @var mac_ax_dl_fix_sta_ent::mac_id
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::ru_pos
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::fix_rate
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::fix_coding
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::fix_txbf
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::fix_pwr_fac
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::rsvd0
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::rate
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::txbf
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::coding
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::pwr_boost_fac
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::rsvd1
* Please Place Description here.
* @var mac_ax_dl_fix_sta_ent::rsvd2
* Please Place Description here.
*/
struct mac_ax_dl_fix_sta_ent {
u8 mac_id;
u8 ru_pos[3];
u8 fix_rate:1;
u8 fix_coding:1;
u8 fix_txbf:1;
u8 fix_pwr_fac:1;
u8 rsvd0: 4;
struct mac_ax_ru_rate_ent rate;
u8 txbf:1;
u8 coding:1;
u8 pwr_boost_fac:5;
u8 rsvd1: 1;
u8 rsvd2;
};
/**
* @struct mac_ax_dlru_fixtbl
* @brief mac_ax_dlru_fixtbl
*
* @var mac_ax_dlru_fixtbl::tbl_hdr
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::max_sta_num
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::min_sta_num
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::doppler
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::stbc
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::gi_ltf
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::ma_type
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::fixru_flag
* Please Place Description here.
* @var mac_ax_dlru_fixtbl::sta
* Please Place Description here.
*/
struct mac_ax_dlru_fixtbl {
struct mac_ax_tbl_hdr tbl_hdr;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 doppler:1;
u8 stbc:1;
u8 gi_ltf:3;
u8 ma_type:1;
u8 fixru_flag:1;
struct mac_ax_dl_fix_sta_ent sta[MAC_AX_MAX_RU_NUM];
};
/**
* @struct mac_ax_ul_fix_sta_ent
* @brief mac_ax_ul_fix_sta_ent
*
* @var mac_ax_ul_fix_sta_ent::mac_id
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::ru_pos
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::tgt_rssi
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::fix_tgt_rssi
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::fix_rate
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::fix_coding
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::coding
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::rsvd1
* Please Place Description here.
* @var mac_ax_ul_fix_sta_ent::rate
* Please Place Description here.
*/
struct mac_ax_ul_fix_sta_ent {
u8 mac_id;
u8 ru_pos[3];
u8 tgt_rssi[3];
u8 fix_tgt_rssi: 1;
u8 fix_rate: 1;
u8 fix_coding: 1;
u8 coding: 1;
u8 rsvd1: 4;
struct mac_ax_ru_rate_ent rate;
};
/**
* @struct mac_ax_ulru_fixtbl
* @brief mac_ax_ulru_fixtbl
*
* @var mac_ax_ulru_fixtbl::tbl_hdr
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::max_sta_num
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::min_sta_num
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::doppler
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::ma_type
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::gi_ltf
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::stbc
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::fix_tb_t_pe_nom
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::tb_t_pe_nom
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::fixru_flag
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::rsvd
* Please Place Description here.
* @var mac_ax_ulru_fixtbl::sta
* Please Place Description here.
*/
struct mac_ax_ulru_fixtbl {
struct mac_ax_tbl_hdr tbl_hdr;
u8 max_sta_num: 3;
u8 min_sta_num: 3;
u8 doppler: 1;
u8 ma_type: 1;
u8 gi_ltf: 3;
u8 stbc: 1;
u8 fix_tb_t_pe_nom: 1;
u8 tb_t_pe_nom: 2;
u8 fixru_flag: 1;
u16 rsvd;
struct mac_ax_ul_fix_sta_ent sta[MAC_AX_MAX_RU_NUM];
};
/*--------------------END Define Struct needed to be moved--------------------*/
/*--------------------Define HCI related structure----------------------------*/
/**
* @struct mac_ax_hfc_ch_cfg
* @brief mac_ax_hfc_ch_cfg
*
* @var mac_ax_hfc_ch_cfg::min
* Please Place Description here.
* @var mac_ax_hfc_ch_cfg::max
* Please Place Description here.
* @var mac_ax_hfc_ch_cfg::grp
* Please Place Description here.
*/
struct mac_ax_hfc_ch_cfg {
u16 min;
u16 max;
#define grp_0 0
#define grp_1 1
#define grp_num 2
u8 grp;
};
/**
* @struct mac_ax_hfc_ch_info
* @brief mac_ax_hfc_ch_info
*
* @var mac_ax_hfc_ch_info::aval
* Please Place Description here.
* @var mac_ax_hfc_ch_info::used
* Please Place Description here.
*/
struct mac_ax_hfc_ch_info {
u16 aval;
u16 used;
};
/**
* @struct mac_ax_hfc_pub_cfg
* @brief mac_ax_hfc_pub_cfg
*
* @var mac_ax_hfc_pub_cfg::group0
* Please Place Description here.
* @var mac_ax_hfc_pub_cfg::group1
* Please Place Description here.
* @var mac_ax_hfc_pub_cfg::pub_max
* Please Place Description here.
* @var mac_ax_hfc_pub_cfg::wp_thrd
* Please Place Description here.
*/
struct mac_ax_hfc_pub_cfg {
u16 group0;
u16 group1;
u16 pub_max;
u16 wp_thrd;
};
/**
* @struct mac_ax_hfc_pub_info
* @brief mac_ax_hfc_pub_info
*
* @var mac_ax_hfc_pub_info::g0_used
* Please Place Description here.
* @var mac_ax_hfc_pub_info::g1_used
* Please Place Description here.
* @var mac_ax_hfc_pub_info::g0_aval
* Please Place Description here.
* @var mac_ax_hfc_pub_info::g1_aval
* Please Place Description here.
* @var mac_ax_hfc_pub_info::pub_aval
* Please Place Description here.
* @var mac_ax_hfc_pub_info::wp_aval
* Please Place Description here.
*/
struct mac_ax_hfc_pub_info {
u16 g0_used;
u16 g1_used;
u16 g0_aval;
u16 g1_aval;
u16 pub_aval;
u16 wp_aval;
};
/**
* @struct mac_ax_hfc_prec_cfg
* @brief mac_ax_hfc_prec_cfg
*
* @var mac_ax_hfc_prec_cfg::ch011_prec
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::h2c_prec
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::wp_ch07_prec
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::wp_ch811_prec
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::ch011_full_cond
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::h2c_full_cond
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::wp_ch07_full_cond
* Please Place Description here.
* @var mac_ax_hfc_prec_cfg::wp_ch811_full_cond
* Please Place Description here.
*/
struct mac_ax_hfc_prec_cfg {
u16 ch011_prec;
u16 h2c_prec;
u16 wp_ch07_prec;
u16 wp_ch811_prec;
u8 ch011_full_cond;
u8 h2c_full_cond;
u8 wp_ch07_full_cond;
u8 wp_ch811_full_cond;
};
/**
* @struct mac_ax_hfc_param
* @brief mac_ax_hfc_param
*
* @var mac_ax_hfc_param::en
* Please Place Description here.
* @var mac_ax_hfc_param::h2c_en
* Please Place Description here.
* @var mac_ax_hfc_param::mode
* Please Place Description here.
* @var mac_ax_hfc_param::ch_cfg
* Please Place Description here.
* @var mac_ax_hfc_param::ch_info
* Please Place Description here.
* @var mac_ax_hfc_param::pub_cfg
* Please Place Description here.
* @var mac_ax_hfc_param::pub_info
* Please Place Description here.
* @var mac_ax_hfc_param::prec_cfg
* Please Place Description here.
*/
struct mac_ax_hfc_param {
u8 en;
u8 h2c_en;
u8 mode;
struct mac_ax_hfc_ch_cfg *ch_cfg;
struct mac_ax_hfc_ch_info *ch_info;
struct mac_ax_hfc_pub_cfg *pub_cfg;
struct mac_ax_hfc_pub_info *pub_info;
struct mac_ax_hfc_prec_cfg *prec_cfg;
};
/**
* @struct mac_ax_sdio_tx_info
* @brief mac_ax_sdio_tx_info
*
* @var mac_ax_sdio_tx_info::total_size
* Please Place Description here.
* @var mac_ax_sdio_tx_info::dma_txagg_num
* Please Place Description here.
* @var mac_ax_sdio_tx_info::ch_dma
* Please Place Description here.
* @var mac_ax_sdio_tx_info::pkt_size
* Please Place Description here.
* @var mac_ax_sdio_tx_info::wp_offset
* Please Place Description here.
* @var mac_ax_sdio_tx_info::chk_cnt
* Please Place Description here.
* @var mac_ax_sdio_tx_info::wde_rqd_num
* Please Place Description here.
* @var mac_ax_sdio_tx_info::ple_rqd_num
* Please Place Description here.
*/
struct mac_ax_sdio_tx_info {
u32 total_size;
u8 dma_txagg_num;
u8 ch_dma;
u8 *pkt_size;
u8 *wp_offset;
u8 chk_cnt;
u16 wde_rqd_num;
u16 ple_rqd_num;
};
/**
* @struct mac_ax_sdio_clk_mon_cfg
* @brief mac_ax_sdio_clk_mon_cfg
*
* @var mac_ax_sdio_clk_mon_cfg::mon
* Please Place Description here.
* @var mac_ax_sdio_clk_mon_cfg::cycle
* Please Place Description here.
*/
struct mac_ax_sdio_clk_mon_cfg {
enum mac_ax_sdio_clk_mon mon;
u32 cycle;
};
/**
* @struct mac_ax_pcie_ltr_rx_th_ctrl
* @brief mac_ax_pcie_ltr_rx_th_ctrl
*
* @var mac_ax_pcie_ltr_rx_th_ctrl::ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_rx_th_ctrl::val
* Please Place Description here.
*/
struct mac_ax_pcie_ltr_rx_th_ctrl {
enum mac_ax_pcie_func_ctrl ctrl;
u16 val;
};
/**
* @struct mac_ax_pcie_ltr_lat_ctrl
* @brief mac_ax_pcie_ltr_lat_ctrl
*
* @var mac_ax_pcie_ltr_lat_ctrl::ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_lat_ctrl::val
* Please Place Description here.
*/
struct mac_ax_pcie_ltr_lat_ctrl {
enum mac_ax_pcie_func_ctrl ctrl;
u32 val;
};
/**
* @struct mac_ax_pcie_ltr_param
* @brief mac_ax_pcie_ltr_param
*
* @var mac_ax_pcie_ltr_param::write
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::read
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_hw_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_spc_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_idle_timer_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_rx0_th_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_rx1_th_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_idle_lat_ctrl
* Please Place Description here.
* @var mac_ax_pcie_ltr_param::ltr_act_lat_ctrl
* Please Place Description here.
*/
struct mac_ax_pcie_ltr_param {
u8 write;
u8 read;
enum mac_ax_pcie_func_ctrl ltr_ctrl;
enum mac_ax_pcie_func_ctrl ltr_hw_ctrl;
enum mac_ax_pcie_ltr_spc ltr_spc_ctrl;
enum mac_ax_pcie_ltr_idle_timer ltr_idle_timer_ctrl;
struct mac_ax_pcie_ltr_rx_th_ctrl ltr_rx0_th_ctrl;
struct mac_ax_pcie_ltr_rx_th_ctrl ltr_rx1_th_ctrl;
struct mac_ax_pcie_ltr_lat_ctrl ltr_idle_lat_ctrl;
struct mac_ax_pcie_ltr_lat_ctrl ltr_act_lat_ctrl;
};
/**
* @struct mac_ax_usb_tx_agg_cfg
* @brief mac_ax_usb_tx_agg_cfg
*
* @var mac_ax_usb_tx_agg_cfg::pkt
* Please Place Description here.
* @var mac_ax_usb_tx_agg_cfg::agg_num
* Please Place Description here.
*/
struct mac_ax_usb_tx_agg_cfg {
u8 *pkt;
u32 agg_num;
};
/**
* @struct mac_ax_pcie_cfgspc_param
* @brief mac_ax_pcie_cfgspc_param
*
* @var mac_ax_pcie_cfgspc_param::write
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::read
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::l0s_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::l1_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::l1ss_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::wake_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::crq_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::clkdly_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::l0sdly_ctrl
* Please Place Description here.
* @var mac_ax_pcie_cfgspc_param::l1dly_ctrl
* Please Place Description here.
*/
struct mac_ax_pcie_cfgspc_param {
u8 write;
u8 read;
enum mac_ax_pcie_func_ctrl l0s_ctrl;
enum mac_ax_pcie_func_ctrl l1_ctrl;
enum mac_ax_pcie_func_ctrl l1ss_ctrl;
enum mac_ax_pcie_func_ctrl wake_ctrl;
enum mac_ax_pcie_func_ctrl crq_ctrl;
enum mac_ax_pcie_clkdly clkdly_ctrl;
enum mac_ax_pcie_l0sdly l0sdly_ctrl;
enum mac_ax_pcie_l1dly l1dly_ctrl;
};
/**
* @struct mac_ax_rx_agg_thold
* @brief mac_ax_rx_agg_thold
*
* @var mac_ax_rx_agg_thold::drv_define
* Please Place Description here.
* @var mac_ax_rx_agg_thold::timeout
* Please Place Description here.
* @var mac_ax_rx_agg_thold::size
* Please Place Description here.
* @var mac_ax_rx_agg_thold::pkt_num
* Please Place Description here.
*/
struct mac_ax_rx_agg_thold {
u8 drv_define;
u8 timeout;
u8 size;
u8 pkt_num;
};
/**
* @struct mac_ax_lifetime_en
* @brief mac_ax_lifetime_en
*
* @var mac_ax_lifetime_en::acq_en
* Please Place Description here.
* @var mac_ax_lifetime_en::mgq_en
* Please Place Description here.
*/
struct mac_ax_lifetime_en {
u8 acq_en;
u8 mgq_en;
};
/**
* @struct mac_ax_lifetime_val
* @brief mac_ax_lifetime_val
*
* @var mac_ax_lifetime_val::acq_val_1
* Please Place Description here.
* @var mac_ax_lifetime_val::acq_val_2
* Please Place Description here.
* @var mac_ax_lifetime_val::acq_val_3
* Please Place Description here.
* @var mac_ax_lifetime_val::acq_val_4
* Please Place Description here.
* @var mac_ax_lifetime_val::mgq_val
* Please Place Description here.
*/
struct mac_ax_lifetime_val {
u16 acq_val_1;
u16 acq_val_2;
u16 acq_val_3;
u16 acq_val_4;
u16 mgq_val;
};
/**
* @struct mac_ax_cfg_bw
* @brief mac_ax_cfg_bw
*
* @var mac_ax_cfg_bw::pri_ch
* Please Place Description here.
* @var mac_ax_cfg_bw::central_ch
* Please Place Description here.
* @var mac_ax_cfg_bw::band
* Please Place Description here.
* @var mac_ax_cfg_bw::rsvd
* Please Place Description here.
* @var mac_ax_cfg_bw::cbw
* Please Place Description here.
*/
struct mac_ax_cfg_bw {
u8 pri_ch;
u8 central_ch;
u16 band: 1;
u16 rsvd: 15;
enum channel_width cbw;
};
/*-------------------- Define Efuse related structure ------------------------*/
/**
* @struct mac_ax_pg_efuse_info
* @brief mac_ax_pg_efuse_info
*
* @var mac_ax_pg_efuse_info::efuse_map
* Please Place Description here.
* @var mac_ax_pg_efuse_info::efuse_map_size
* Please Place Description here.
* @var mac_ax_pg_efuse_info::efuse_mask
* Please Place Description here.
* @var mac_ax_pg_efuse_info::efuse_mask_size
* Please Place Description here.
*/
struct mac_ax_pg_efuse_info {
u8 *efuse_map;
u32 efuse_map_size;
u8 *efuse_mask;
u32 efuse_mask_size;
};
/**
* @struct mac_ax_efuse_param
* @brief mac_ax_efuse_param
*
* @var mac_ax_efuse_param::efuse_map
* Please Place Description here.
* @var mac_ax_efuse_param::bt_efuse_map
* Please Place Description here.
* @var mac_ax_efuse_param::log_efuse_map
* Please Place Description here.
* @var mac_ax_efuse_param::bt_log_efuse_map
* Please Place Description here.
* @var mac_ax_efuse_param::efuse_end
* Please Place Description here.
* @var mac_ax_efuse_param::bt_efuse_end
* Please Place Description here.
* @var mac_ax_efuse_param::efuse_map_valid
* Please Place Description here.
* @var mac_ax_efuse_param::bt_efuse_map_valid
* Please Place Description here.
* @var mac_ax_efuse_param::log_efuse_map_valid
* Please Place Description here.
* @var mac_ax_efuse_param::bt_log_efuse_map_valid
* Please Place Description here.
* @var mac_ax_efuse_param::auto_ck_en
* Please Place Description here.
* @var mac_ax_efuse_param::dav_efuse_map
* Please Place Description here.
* @var mac_ax_efuse_param::dav_log_efuse_map
* Please Place Description here.
* @var mac_ax_efuse_param::dav_efuse_end
* Please Place Description here.
* @var mac_ax_efuse_param::dav_efuse_map_valid
* Please Place Description here.
* @var mac_ax_efuse_param::dav_log_efuse_map_valid
* Please Place Description here.
*/
struct mac_ax_efuse_param {
u8 *efuse_map;
u8 *bt_efuse_map;
u8 *log_efuse_map;
u8 *bt_log_efuse_map;
u32 efuse_end;
u32 bt_efuse_end;
u8 efuse_map_valid;
u8 bt_efuse_map_valid;
u8 log_efuse_map_valid;
u8 bt_log_efuse_map_valid;
u8 auto_ck_en;
u8 *dav_efuse_map;
u8 *dav_log_efuse_map;
u32 dav_efuse_end;
u8 dav_efuse_map_valid;
u8 dav_log_efuse_map_valid;
};
/*-------------------- Define offload related Struct -------------------------*/
/**
* @struct mac_ax_read_req
* @brief mac_ax_read_req
*
* @var mac_ax_read_req::value_len
* Please Place Description here.
* @var mac_ax_read_req::rsvd0
* Please Place Description here.
* @var mac_ax_read_req::ls
* Please Place Description here.
* @var mac_ax_read_req::ofld_id
* Please Place Description here.
* @var mac_ax_read_req::entry_num
* Please Place Description here.
* @var mac_ax_read_req::offset
* Please Place Description here.
* @var mac_ax_read_req::rsvd1
* Please Place Description here.
*/
struct mac_ax_read_req {
u16 value_len:11;
u16 rsvd0: 4;
u16 ls: 1;
u8 ofld_id;
u8 entry_num;
u16 offset;
u16 rsvd1;
};
/**
* @struct mac_ax_read_ofld_info
* @brief mac_ax_read_ofld_info
*
* @var mac_ax_read_ofld_info::buf
* Please Place Description here.
* @var mac_ax_read_ofld_info::buf_wptr
* Please Place Description here.
* @var mac_ax_read_ofld_info::last_req
* Please Place Description here.
* @var mac_ax_read_ofld_info::buf_size
* Please Place Description here.
* @var mac_ax_read_ofld_info::avl_buf_size
* Please Place Description here.
* @var mac_ax_read_ofld_info::used_size
* Please Place Description here.
* @var mac_ax_read_ofld_info::req_num
* Please Place Description here.
*/
struct mac_ax_read_ofld_info {
u8 *buf;
u8 *buf_wptr;
struct mac_ax_read_req *last_req;
u32 buf_size;
u32 avl_buf_size;
u32 used_size;
u32 req_num;
};
/**
* @struct mac_ax_read_ofld_value
* @brief mac_ax_read_ofld_value
*
* @var mac_ax_read_ofld_value::len
* Please Place Description here.
* @var mac_ax_read_ofld_value::rsvd
* Please Place Description here.
* @var mac_ax_read_ofld_value::buf
* Please Place Description here.
*/
struct mac_ax_read_ofld_value {
u16 len;
u16 rsvd;
u8 *buf;
};
/**
* @struct mac_ax_efuse_ofld_info
* @brief mac_ax_efuse_ofld_info
*
* @var mac_ax_efuse_ofld_info::buf
* Please Place Description here.
*/
struct mac_ax_efuse_ofld_info {
u8 *buf;
};
/**
* @struct mac_ax_write_req
* @brief mac_ax_write_req
*
* @var mac_ax_write_req::value_len
* Please Place Description here.
* @var mac_ax_write_req::rsvd0
* Please Place Description here.
* @var mac_ax_write_req::polling
* Please Place Description here.
* @var mac_ax_write_req::mask_en
* Please Place Description here.
* @var mac_ax_write_req::ls
* Please Place Description here.
* @var mac_ax_write_req::ofld_id
* Please Place Description here.
* @var mac_ax_write_req::entry_num
* Please Place Description here.
* @var mac_ax_write_req::offset
* Please Place Description here.
* @var mac_ax_write_req::rsvd1
* Please Place Description here.
*/
struct mac_ax_write_req {
u16 value_len:11;
u16 rsvd0: 2;
u16 polling: 1;
u16 mask_en: 1;
u16 ls: 1;
u8 ofld_id;
u8 entry_num;
u16 offset;
u16 rsvd1;
};
/**
* @struct mac_ax_write_ofld_info
* @brief mac_ax_write_ofld_info
*
* @var mac_ax_write_ofld_info::buf
* Please Place Description here.
* @var mac_ax_write_ofld_info::buf_wptr
* Please Place Description here.
* @var mac_ax_write_ofld_info::last_req
* Please Place Description here.
* @var mac_ax_write_ofld_info::buf_size
* Please Place Description here.
* @var mac_ax_write_ofld_info::avl_buf_size
* Please Place Description here.
* @var mac_ax_write_ofld_info::used_size
* Please Place Description here.
* @var mac_ax_write_ofld_info::req_num
* Please Place Description here.
*/
struct mac_ax_write_ofld_info {
u8 *buf;
u8 *buf_wptr;
struct mac_ax_write_req *last_req;
u32 buf_size;
u32 avl_buf_size;
u32 used_size;
u32 req_num;
};
/**
* @struct mac_ax_conf_ofld_info
* @brief mac_ax_conf_ofld_info
*
* @var mac_ax_conf_ofld_info::buf
* Please Place Description here.
* @var mac_ax_conf_ofld_info::buf_wptr
* Please Place Description here.
* @var mac_ax_conf_ofld_info::buf_size
* Please Place Description here.
* @var mac_ax_conf_ofld_info::avl_buf_size
* Please Place Description here.
* @var mac_ax_conf_ofld_info::used_size
* Please Place Description here.
* @var mac_ax_conf_ofld_info::req_num
* Please Place Description here.
*/
struct mac_ax_conf_ofld_info {
u8 *buf;
u8 *buf_wptr;
u32 buf_size;
u32 avl_buf_size;
u32 used_size;
u16 req_num;
};
/**
* @struct mac_ax_pkt_ofld_info
* @brief mac_ax_pkt_ofld_info
*
* @var mac_ax_pkt_ofld_info::last_op
* Please Place Description here.
* @var mac_ax_pkt_ofld_info::free_id_count
* Please Place Description here.
* @var mac_ax_pkt_ofld_info::used_id_count
* Please Place Description here.
* @var mac_ax_pkt_ofld_info::id_bitmap
* Please Place Description here.
*/
struct mac_ax_pkt_ofld_info {
#define PKT_OFLD_MAX_COUNT 256
u8 last_op;
u16 free_id_count;
u16 used_id_count;
u8 id_bitmap[PKT_OFLD_MAX_COUNT >> 3];
};
/**
* @struct mac_ax_pkt_ofld_pkt
* @brief mac_ax_pkt_ofld_pkt
*
* @var mac_ax_pkt_ofld_pkt::pkt_id
* Please Place Description here.
* @var mac_ax_pkt_ofld_pkt::rsvd
* Please Place Description here.
* @var mac_ax_pkt_ofld_pkt::pkt_len
* Please Place Description here.
* @var mac_ax_pkt_ofld_pkt::pkt
* Please Place Description here.
*/
struct mac_ax_pkt_ofld_pkt {
u8 pkt_id;
u8 rsvd;
u16 pkt_len;
u8 *pkt;
};
/**
* @struct mac_ax_general_pkt_ids
* @brief mac_ax_general_pkt_ids
*
* @var mac_ax_general_pkt_ids::macid
* Please Place Description here.
* @var mac_ax_general_pkt_ids::probersp
* Please Place Description here.
* @var mac_ax_general_pkt_ids::pspoll
* Please Place Description here.
* @var mac_ax_general_pkt_ids::nulldata
* Please Place Description here.
* @var mac_ax_general_pkt_ids::qosnull
* Please Place Description here.
* @var mac_ax_general_pkt_ids::cts2self
* Please Place Description here.
* @var mac_ax_general_pkt_ids::probereq
* offloaded probe request pkt id
* @var mac_ax_general_pkt_ids::apcsa
* offloaded CSA frame id
*/
struct mac_ax_general_pkt_ids {
u8 macid;
u8 probersp;
u8 pspoll;
u8 nulldata;
u8 qosnull;
u8 cts2self;
u8 probereq;
u8 apcsa;
};
#ifndef CONFIG_FW_IO_OFLD_SUPPORT
/**
* @struct rtw_mac_cmd
* @brief rtw_mac_cmd
*
* @var rtw_mac_cmd::src
* Please Place Description here.
* @var rtw_mac_cmd::type
* Please Place Description here.
* @var rtw_mac_cmd::lc
* Please Place Description here.
* @var rtw_mac_cmd::rf_path
* Please Place Description here.
* @var rtw_mac_cmd::offset
* Please Place Description here.
* @var rtw_mac_cmd::id
* Please Place Description here.
* @var rtw_mac_cmd::value
* Please Place Description here.
* @var rtw_mac_cmd::mask
* Please Place Description here.
*/
struct rtw_mac_cmd {
enum rtw_mac_src_cmd_ofld src;
enum rtw_mac_cmd_type_ofld type;
u8 lc;
enum rtw_mac_rf_path rf_path;
u16 offset;
u16 id;
u32 value;
u32 mask;
};
#endif
/**
* @struct mac_ax_cmd_ofld_info
* @brief mac_ax_cmd_ofld_info
*
* @var mac_ax_cmd_ofld_info::buf
* Please Place Description here.
* @var mac_ax_cmd_ofld_info::end_ptr
* Please Place Description here.
* @var mac_ax_cmd_ofld_info::buf_size
* Please Place Description here.
* @var mac_ax_cmd_ofld_info::avl_buf_size
* Please Place Description here.
* @var mac_ax_cmd_ofld_info::used_size
* Please Place Description here.
* @var mac_ax_cmd_ofld_info::cmd_num
* Please Place Description here.
*/
struct mac_ax_cmd_ofld_info {
u8 *buf;
u8 *buf_wptr;
u8 *last_wptr;
u16 buf_size;
u16 avl_buf_size;
u16 used_size;
u8 cmd_num;
u8 result;
u32 accu_delay;
mac_ax_mutex cmd_ofld_lock;
};
/**
* @struct mac_ax_tx_duty_ofld_info
* @brief mac_ax_tx_duty_ofld_info
*
* @var mac_ax_tx_duty_ofld_info::timer_err
* Please Place Description here.
*/
struct mac_ax_tx_duty_ofld_info {
u8 timer_err;
};
/*--------------------Define OutSrc related ----------------------------------*/
/**
* @struct mac_ax_la_cfg
* @brief mac_ax_la_cfg
*
* @var mac_ax_la_cfg::la_func_en
* Please Place Description here.
* @var mac_ax_la_cfg::la_restart_en
* Please Place Description here.
* @var mac_ax_la_cfg::la_timeout_en
* Please Place Description here.
* @var mac_ax_la_cfg::la_timeout_val
* Please Place Description here.
* @var mac_ax_la_cfg::la_data_loss_imr
* Please Place Description here.
* @var mac_ax_la_cfg::la_tgr_tu_sel
* Please Place Description here.
* @var mac_ax_la_cfg::la_tgr_time_val
* Please Place Description here.
* @var mac_ax_la_cfg::rsvd
* Please Place Description here.
*/
struct mac_ax_la_cfg {
u32 la_func_en:1;
u32 la_restart_en:1;
u32 la_timeout_en:1;
/* 2'h0: 1s, 2'h1: 2s, 2'h2: 4s, 2'h3: 8s */
u32 la_timeout_val:2;
/*Error flag mask bit for LA data loss due to pktbuffer busy */
u32 la_data_loss_imr:1;
/* TU (time unit) = 2^ B_AX_LA_TRIG_TU_SEL */
u32 la_tgr_tu_sel:4;
/* 6'h0: No delay, 6'h1: 1 TU, 6'h2: 2TU, ??*/
u32 la_tgr_time_val:7;
u32 rsvd:15;
};
/**
* @struct mac_ax_la_status
* @brief mac_ax_la_status
*
* @var mac_ax_la_status::la_buf_wptr
* Please Place Description here.
* @var mac_ax_la_status::la_buf_rndup_ind
* Please Place Description here.
* @var mac_ax_la_status::la_sw_fsmst
* Please Place Description here.
* @var mac_ax_la_status::la_data_loss
* Please Place Description here.
*/
struct mac_ax_la_status {
/* LA data dump finish address = (la_buf_wptr -1) */
u16 la_buf_wptr;
/*1: round up, 0: No round up */
u8 la_buf_rndup_ind:1;
/*3'h0: LA idle ; 3'h1: LA start; 3'h2: LA finish stop;*/
/*3'h3:LA finish timeout; 3'h4: LA re-start*/
u8 la_sw_fsmst:3;
/* LA data loss due to pktbuffer busy */
u8 la_data_loss:1;
};
/**
* @struct mac_ax_la_buf_param
* @brief mac_ax_la_buf_param
*
* @var mac_ax_la_buf_param::start_addr
* Please Place Description here.
* @var mac_ax_la_buf_param::end_addr
* Please Place Description here.
* @var mac_ax_la_buf_param::la_buf_sel
* Please Place Description here.
*/
struct mac_ax_la_buf_param {
u32 start_addr;
u32 end_addr;
u8 la_buf_sel; /*0: 64KB; 1: 128KB; 2: 192KB; 3: 256KB; 4: 320KB*/
};
/*--------------------Define TRX PKT INFO/RPT---------------------------------*/
/**
* @struct mac_ax_pkt_data
* @brief mac_ax_pkt_data
*
* @var mac_ax_pkt_data::wifi_seq
* Please Place Description here.
* @var mac_ax_pkt_data::hw_ssn_sel
* Please Place Description here.
* @var mac_ax_pkt_data::hw_seq_mode
* Please Place Description here.
* @var mac_ax_pkt_data::chk_en
* Please Place Description here.
* @var mac_ax_pkt_data::hw_amsdu
* Please Place Description here.
* @var mac_ax_pkt_data::shcut_camid
* Please Place Description here.
* @var mac_ax_pkt_data::headerwllc_len
* Please Place Description here.
* @var mac_ax_pkt_data::smh_en
* Please Place Description here.
* @var mac_ax_pkt_data::wd_page
* Please Place Description here.
* @var mac_ax_pkt_data::wp_offset
* Please Place Description here.
* @var mac_ax_pkt_data::wdinfo_en
* Please Place Description here.
* @var mac_ax_pkt_data::hw_aes_iv
* Please Place Description here.
* @var mac_ax_pkt_data::hdr_len
* Please Place Description here.
* @var mac_ax_pkt_data::ch
* Please Place Description here.
* @var mac_ax_pkt_data::macid
* Please Place Description here.
* @var mac_ax_pkt_data::agg_en
* Please Place Description here.
* @var mac_ax_pkt_data::bk
* Please Place Description here.
* @var mac_ax_pkt_data::max_agg_num
* Please Place Description here.
* @var mac_ax_pkt_data::bmc
* Please Place Description here.
* @var mac_ax_pkt_data::lifetime_sel
* Please Place Description here.
* @var mac_ax_pkt_data::ampdu_density
* Please Place Description here.
* @var mac_ax_pkt_data::userate
* Please Place Description here.
* @var mac_ax_pkt_data::data_rate
* Please Place Description here.
* @var mac_ax_pkt_data::data_bw
* Please Place Description here.
* @var mac_ax_pkt_data::er_bw
* Please Place Description here.
* @var mac_ax_pkt_data::data_gi_ltf
* Please Place Description here.
* @var mac_ax_pkt_data::data_er
* Please Place Description here.
* @var mac_ax_pkt_data::data_dcm
* Please Place Description here.
* @var mac_ax_pkt_data::data_stbc
* Please Place Description here.
* @var mac_ax_pkt_data::data_ldpc
* Please Place Description here.
* @var mac_ax_pkt_data::hw_sec_en
* Please Place Description here.
* @var mac_ax_pkt_data::sec_cam_idx
* Please Place Description here.
* @var mac_ax_pkt_data::sec_type
* Please Place Description here.
* @var mac_ax_pkt_data::dis_data_fb
* Please Place Description here.
* @var mac_ax_pkt_data::dis_rts_fb
* Please Place Description here.
* @var mac_ax_pkt_data::tid
* Please Place Description here.
* @var mac_ax_pkt_data::rts_en
* Please Place Description here.
* @var mac_ax_pkt_data::cts2self
* Please Place Description here.
* @var mac_ax_pkt_data::cca_rts
* Please Place Description here.
* @var mac_ax_pkt_data::hw_rts_en
* Please Place Description here.
* @var mac_ax_pkt_data::ndpa
* Please Place Description here.
* @var mac_ax_pkt_data::snd_pkt_sel
* Please Place Description here.
* @var mac_ax_pkt_data::sifs_tx
* Please Place Description here.
* @var mac_ax_pkt_data::tx_cnt_lmt_sel
* Please Place Description here.
* @var mac_ax_pkt_data::tx_cnt_lmt
* Please Place Description here.
* @var mac_ax_pkt_data::ndpa_dur
* Please Place Description here.
* @var mac_ax_pkt_data::nav_use_hdr
* Please Place Description here.
* @var mac_ax_pkt_data::multiport_id
* Please Place Description here.
* @var mac_ax_pkt_data::mbssid
* Please Place Description here.
* @var mac_ax_pkt_data::null_0
* Please Place Description here.
* @var mac_ax_pkt_data::null_1
* Please Place Description here.
* @var mac_ax_pkt_data::tri_frame
* Please Place Description here.
* @var mac_ax_pkt_data::ack_ch_info
* Please Place Description here.
* @var mac_ax_pkt_data::pkt_offset
* Please Place Description here.
* @var mac_ax_pkt_data::a_ctrl_uph
* Please Place Description here.
* @var mac_ax_pkt_data::a_ctrl_bsr
* Please Place Description here.
* @var mac_ax_pkt_data::a_ctrl_cas
* Please Place Description here.
* @var mac_ax_pkt_data::rtt
* Please Place Description here.
* @var mac_ax_pkt_data::ht_data_snd
* Please Place Description here.
* @var mac_ax_pkt_data::no_ack
* Please Place Description here.
* @var mac_ax_pkt_data::sw_define
* Please Place Description here.
*/
struct mac_ax_pkt_data {
u16 wifi_seq;
u8 hw_ssn_sel;
u8 hw_seq_mode;
u8 chk_en;
u8 hw_amsdu;
u8 shcut_camid;
u8 headerwllc_len;
u8 smh_en;
u8 wd_page;
u8 wp_offset;
u8 wdinfo_en;
u8 hw_aes_iv;
u8 hdr_len;
u8 ch;
u8 macid;
u8 wmm;
u8 band;
u8 agg_en;
u8 bk;
u8 max_agg_num;
u8 bmc;
u8 lifetime_sel;
u8 ampdu_density;
u8 userate;
u16 data_rate;
u8 data_bw;
u8 er_bw;
u8 data_gi_ltf;
u8 data_er;
u8 data_dcm;
u8 data_stbc;
u8 data_ldpc;
u8 hw_sec_en;
u8 sec_cam_idx;
u8 sec_type;
u8 dis_data_fb;
u8 dis_rts_fb;
u8 tid;
u8 rts_en;
u8 cts2self;
u8 cca_rts;
u8 hw_rts_en;
u8 ndpa;
u8 snd_pkt_sel;
u8 sifs_tx;
u8 tx_cnt_lmt_sel;
u8 tx_cnt_lmt;
u16 ndpa_dur;
u8 nav_use_hdr;
u8 multiport_id;
u8 mbssid;
u8 null_0;
u8 null_1;
u8 tri_frame;
u8 ack_ch_info;
u8 pkt_offset;
u8 a_ctrl_uph;
u8 a_ctrl_bsr;
u8 a_ctrl_cas;
u8 rtt;
u8 ht_data_snd;
u8 no_ack;
u8 sw_define;
u8 addr_info_num;
u8 reuse_start_num;
u8 reuse_size;
u8 reuse_num;
u8 hw_sec_iv;
u8 sw_sec_iv;
u8 sec_keyid;
u8 rls_to_cpuio;
u8 force_key_en;
u8 upd_wlan_hdr;
u16 data_rty_lowest_rate;
u8 spe_rpt;
};
/**
* @struct mac_ax_pkt_mgnt
* @brief mac_ax_pkt_mgnt
*
* @var mac_ax_pkt_mgnt::wifi_seq
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hw_ssn_sel
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hw_seq_mode
* Please Place Description here.
* @var mac_ax_pkt_mgnt::chk_en
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hw_amsdu
* Please Place Description here.
* @var mac_ax_pkt_mgnt::shcut_camid
* Please Place Description here.
* @var mac_ax_pkt_mgnt::headerwllc_len
* Please Place Description here.
* @var mac_ax_pkt_mgnt::smh_en
* Please Place Description here.
* @var mac_ax_pkt_mgnt::wd_page
* Please Place Description here.
* @var mac_ax_pkt_mgnt::wp_offset
* Please Place Description here.
* @var mac_ax_pkt_mgnt::wdinfo_en
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hw_aes_iv
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hdr_len
* Please Place Description here.
* @var mac_ax_pkt_mgnt::rsvd0
* Please Place Description here.
* @var mac_ax_pkt_mgnt::macid
* Please Place Description here.
* @var mac_ax_pkt_mgnt::rsvd1
* Please Place Description here.
* @var mac_ax_pkt_mgnt::bk
* Please Place Description here.
* @var mac_ax_pkt_mgnt::max_agg_num
* Please Place Description here.
* @var mac_ax_pkt_mgnt::bmc
* Please Place Description here.
* @var mac_ax_pkt_mgnt::lifetime_sel
* Please Place Description here.
* @var mac_ax_pkt_mgnt::ampdu_density
* Please Place Description here.
* @var mac_ax_pkt_mgnt::userate
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_rate
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_bw
* Please Place Description here.
* @var mac_ax_pkt_mgnt::er_bw
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_gi_ltf
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_er
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_dcm
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_stbc
* Please Place Description here.
* @var mac_ax_pkt_mgnt::data_ldpc
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hw_sec_en
* Please Place Description here.
* @var mac_ax_pkt_mgnt::sec_cam_idx
* Please Place Description here.
* @var mac_ax_pkt_mgnt::sec_type
* Please Place Description here.
* @var mac_ax_pkt_mgnt::dis_data_fb
* Please Place Description here.
* @var mac_ax_pkt_mgnt::dis_rts_fb
* Please Place Description here.
* @var mac_ax_pkt_mgnt::tid
* Please Place Description here.
* @var mac_ax_pkt_mgnt::rts_en
* Please Place Description here.
* @var mac_ax_pkt_mgnt::cts2self
* Please Place Description here.
* @var mac_ax_pkt_mgnt::cca_rts
* Please Place Description here.
* @var mac_ax_pkt_mgnt::hw_rts_en
* Please Place Description here.
* @var mac_ax_pkt_mgnt::ndpa
* Please Place Description here.
* @var mac_ax_pkt_mgnt::snd_pkt_sel
* Please Place Description here.
* @var mac_ax_pkt_mgnt::sifs_tx
* Please Place Description here.
* @var mac_ax_pkt_mgnt::tx_cnt_lmt_sel
* Please Place Description here.
* @var mac_ax_pkt_mgnt::tx_cnt_lmt
* Please Place Description here.
* @var mac_ax_pkt_mgnt::ndpa_dur
* Please Place Description here.
* @var mac_ax_pkt_mgnt::nav_use_hdr
* Please Place Description here.
* @var mac_ax_pkt_mgnt::multiport_id
* Please Place Description here.
* @var mac_ax_pkt_mgnt::mbssid
* Please Place Description here.
* @var mac_ax_pkt_mgnt::null_0
* Please Place Description here.
* @var mac_ax_pkt_mgnt::null_1
* Please Place Description here.
* @var mac_ax_pkt_mgnt::tri_frame
* Please Place Description here.
* @var mac_ax_pkt_mgnt::ack_ch_info
* Please Place Description here.
* @var mac_ax_pkt_mgnt::pkt_offset
* Please Place Description here.
* @var mac_ax_pkt_mgnt::a_ctrl_bsr
* Please Place Description here.
* @var mac_ax_pkt_mgnt::rtt
* Please Place Description here.
* @var mac_ax_pkt_mgnt::ht_data_snd
* Please Place Description here.
* @var mac_ax_pkt_mgnt::no_ack
* Please Place Description here.
*/
struct mac_ax_pkt_mgnt {
u16 wifi_seq;
u8 hw_ssn_sel;
u8 hw_seq_mode;
u8 chk_en;
u8 hw_amsdu;
u8 shcut_camid;
u8 headerwllc_len;
u8 smh_en;
u8 wd_page;
u8 wp_offset;
u8 wdinfo_en;
u8 hw_aes_iv;
u8 hdr_len;
u8 ch;
u8 macid;
u8 wmm;
u8 band;
u8 agg_en;
u8 bk;
u8 max_agg_num;
u8 bmc;
u8 lifetime_sel;
u8 ampdu_density;
u8 userate;
u16 data_rate;
u8 data_bw;
u8 er_bw;
u8 data_gi_ltf;
u8 data_er;
u8 data_dcm;
u8 data_stbc;
u8 data_ldpc;
u8 hw_sec_en;
u8 sec_cam_idx;
u8 sec_type;
u8 dis_data_fb;
u8 dis_rts_fb;
u8 tid;
u8 rts_en;
u8 cts2self;
u8 cca_rts;
u8 hw_rts_en;
u8 ndpa;
u8 snd_pkt_sel;
u8 sifs_tx;
u8 tx_cnt_lmt_sel;
u8 tx_cnt_lmt;
u16 ndpa_dur;
u8 nav_use_hdr;
u8 multiport_id;
u8 mbssid;
u8 null_0;
u8 null_1;
u8 tri_frame;
u8 ack_ch_info;
u8 pkt_offset;
u8 a_ctrl_uph;
u8 a_ctrl_bsr;
u8 a_ctrl_cas;
u8 rtt;
u8 ht_data_snd;
u8 no_ack;
u8 sw_define;
u8 addr_info_num;
u8 reuse_start_num;
u8 reuse_size;
u8 reuse_num;
u8 hw_sec_iv;
u8 sw_sec_iv;
u8 sec_keyid;
u8 rls_to_cpuio;
u8 force_key_en;
u8 upd_wlan_hdr;
u16 data_rty_lowest_rate;
u8 spe_rpt;
};
/**
* @struct mac_ax_rpkt_data
* @brief mac_ax_rpkt_data
*
* @var mac_ax_rpkt_data::crc_err
* Please Place Description here.
* @var mac_ax_rpkt_data::icv_err
* Please Place Description here.
*/
struct mac_ax_rpkt_data {
u8 crc_err;
u8 icv_err;
};
/**
* @struct mac_ax_txpkt_info
* @brief mac_ax_txpkt_info
*
* @var mac_ax_txpkt_info::type
* Please Place Description here.
* @var mac_ax_txpkt_info::pktsize
* Please Place Description here.
* @var mac_ax_txpkt_info::data
* Please Place Description here.
* @var mac_ax_txpkt_info::mgnt
* Please Place Description here.
* @var mac_ax_txpkt_info::u
* Please Place Description here.
*/
struct mac_ax_txpkt_info {
enum mac_ax_pkt_t type;
u32 pktsize;
union {
struct mac_ax_pkt_data data;
struct mac_ax_pkt_mgnt mgnt;
} u;
};
/**
* @struct mac_ax_bcn_cnt
* @brief mac_ax_bcn_cnt
*
* @var mac_ax_bcn_cnt::port
* Please Place Description here.
* @var mac_ax_bcn_cnt::mbssid
* Please Place Description here.
* @var mac_ax_bcn_cnt::ok_cnt
* Please Place Description here.
* @var mac_ax_bcn_cnt::fail_cnt
* Please Place Description here.
*/
struct mac_ax_bcn_cnt {
u8 port;
u8 mbssid;
u8 band;
u8 ok_cnt;
u8 cca_cnt;
u8 edcca_cnt;
u8 nav_cnt;
u8 txon_cnt;
u8 mac_cnt;
u8 others_cnt;
u8 lock_cnt;
u8 cmp_cnt;
u8 invalid_cnt;
u8 srchend_cnt;
};
/**
* @struct mac_ax_refill_info
* @brief mac_ax_refill_info
*
* @var mac_ax_refill_info::pkt
* Please Place Description here.
* @var mac_ax_refill_info::agg_num
* Please Place Description here.
* @var mac_ax_refill_info::packet_offset
* Please Place Description here.
*/
struct mac_ax_refill_info {
u8 *pkt;
u32 agg_num;
u8 packet_offset;
};
/**
* @struct mac_ax_rpkt_ppdu
* @brief mac_ax_rpkt_ppdu
*
* @var mac_ax_rpkt_ppdu::mac_info
* Please Place Description here.
*/
struct mac_ax_rpkt_ppdu {
u8 mac_info;
};
/**
* @struct mac_ax_mac_tx_mode_sel
* @brief mac_ax_mac_tx_mode_sel
*
* @var mac_ax_mac_tx_mode_sel::txop_rot_wmm0_en
* Please Place Description here.
* @var mac_ax_mac_tx_mode_sel::txop_rot_wmm1_en
* Please Place Description here.
* @var mac_ax_mac_tx_mode_sel::txop_rot_wmm2_en
* Please Place Description here.
* @var mac_ax_mac_tx_mode_sel::txop_rot_wmm3_en
* Please Place Description here.
*/
struct mac_ax_mac_tx_mode_sel {
u8 txop_rot_wmm0_en;
u8 txop_rot_wmm1_en;
u8 txop_rot_wmm2_en;
u8 txop_rot_wmm3_en;
u8 sw_mode_band0_en; /* shall remove when v0_22 release, Rick */
};
/**
* @struct mac_ax_rxpkt_info
* @brief mac_ax_rxpkt_info
*
* @var mac_ax_rxpkt_info::type
* Please Place Description here.
* @var mac_ax_rxpkt_info::rxdlen
* Please Place Description here.
* @var mac_ax_rxpkt_info::drvsize
* Please Place Description here.
* @var mac_ax_rxpkt_info::shift
* Please Place Description here.
* @var mac_ax_rxpkt_info::pktsize
* Please Place Description here.
* @var mac_ax_rxpkt_info::data
* Please Place Description here.
* @var mac_ax_rxpkt_info::ppdu
* Please Place Description here.
* @var mac_ax_rxpkt_info::u
* Please Place Description here.
*/
struct mac_ax_rxpkt_info {
enum mac_ax_pkt_t type;
u16 rxdlen;
u8 drvsize;
u8 shift;
u32 pktsize;
union {
struct mac_ax_rpkt_data data;
struct mac_ax_rpkt_ppdu ppdu;
} u;
};
/**
* @struct mac_ax_pm_cam_ctrl_t
* @brief mac_ax_pm_cam_ctrl_t
*
* @var mac_ax_pm_cam_ctrl_t::pld_mask0
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::pld_mask1
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::pld_mask2
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::pld_mask3
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::entry_index
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::valid
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::type
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::subtype
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::skip_mac_iv_hdr
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::target_ind
* Please Place Description here.
* @var mac_ax_pm_cam_ctrl_t::crc16
* Please Place Description here.
*/
struct mac_ax_pm_cam_ctrl_t {
u32 pld_mask0;
u32 pld_mask1;
u32 pld_mask2;
u32 pld_mask3;
u8 entry_index;
u8 valid;
u8 type;
u8 subtype;
u8 skip_mac_iv_hdr;
u8 target_ind;
u16 crc16;
};
/**
* @struct mac_ax_af_ud_ctrl_t
* @brief mac_ax_af_ud_ctrl_t
*
* @var mac_ax_af_ud_ctrl_t::index
* Please Place Description here.
* @var mac_ax_af_ud_ctrl_t::fwd_tg
* Please Place Description here.
* @var mac_ax_af_ud_ctrl_t::category
* Please Place Description here.
* @var mac_ax_af_ud_ctrl_t::action_field
* Please Place Description here.
*/
struct mac_ax_af_ud_ctrl_t {
u8 index;
u8 fwd_tg;
u8 category;
u8 action_field;
};
/**
* @struct mac_ax_rx_fwd_ctrl_t
* @brief mac_ax_rx_fwd_ctrl_t
*
* @var mac_ax_rx_fwd_ctrl_t::pm_cam_ctrl
* Please Place Description here.
* @var mac_ax_rx_fwd_ctrl_t::af_ud_ctrl
* Please Place Description here.
* @var mac_ax_rx_fwd_ctrl_t::type
* Please Place Description here.
* @var mac_ax_rx_fwd_ctrl_t::frame
* Please Place Description here.
* @var mac_ax_rx_fwd_ctrl_t::fwd_tg
* Please Place Description here.
*/
struct mac_ax_rx_fwd_ctrl_t {
struct mac_ax_pm_cam_ctrl_t pm_cam_ctrl;
struct mac_ax_af_ud_ctrl_t af_ud_ctrl;
u8 type;
u8 frame;
u8 fwd_tg;
};
/**
* @struct mac_ax_rx_fltr_ctrl_t
* @brief mac_ax_rx_fltr_ctrl_t
*
* @var mac_ax_rx_fltr_ctrl_t::sniffer_mode
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_a1_match_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_bc_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_mc_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::uc_pkt_chk_cam_match
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::bc_pkt_chk_cam_match
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::mc_pkt_white_lst_mode
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::bcn_chk_en
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::bcn_chk_rule
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_pwr_mngt_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_crc32_err_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_unsupport_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_mac_hdr_content_err_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::acpt_ftm_req_pkt
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::pkt_len_fltr
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::unsp_pkt_target
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::uid_fltr
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::cck_crc_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::cck_sig_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::lsig_parity_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::siga_crc_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::vht_su_sigb_crc_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::vht_mu_sigb_crc_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::he_sigb_crc_chk_enable
* Please Place Description here.
* @var mac_ax_rx_fltr_ctrl_t::min_len_chk_disable
* Please Place Description here.
*/
struct mac_ax_rx_fltr_ctrl_t {
// mac fltr
u8 sniffer_mode:1;
u8 acpt_a1_match_pkt:1;
u8 acpt_bc_pkt:1;
u8 acpt_mc_pkt:1;
u8 uc_pkt_chk_cam_match:1;
u8 bc_pkt_chk_cam_match:1;
u8 mc_pkt_white_lst_mode:1;
u8 bcn_chk_en:1;
u8 bcn_chk_rule:2;
u8 acpt_pwr_mngt_pkt:1;
u8 acpt_crc32_err_pkt:1;
u8 acpt_unsupport_pkt:1;
u8 acpt_mac_hdr_content_err_pkt:1;
u8 acpt_ftm_req_pkt:1;
u8 pkt_len_fltr:6;
u8 unsp_pkt_target:2;
u8 uid_fltr:2;
// plcp fltr
u8 cck_crc_chk_enable:1;
u8 cck_sig_chk_enable:1;
u8 lsig_parity_chk_enable:1;
u8 siga_crc_chk_enable:1;
u8 vht_su_sigb_crc_chk_enable:1;
u8 vht_mu_sigb_crc_chk_enable:1;
u8 he_sigb_crc_chk_enable:1;
u8 min_len_chk_disable:1;
};
struct mac_ax_rx_fltr_elem {
u16 subtype_mask;
enum mac_ax_fwd_target target_arr[16];
};
/**
* @struct mac_ax_addrcam_ctrl_t
* @brief mac_ax_addrcam_ctrl_t
*/
struct mac_ax_addrcam_ctrl_t {
u8 addrcam_en:1;
u8 srch_per_mpdu:1;
u8 a2_bit0_cmp_en:1;
u8 rsvd1:5;
u8 clr_all_content:1;
u8 rsvd2:3;
u8 srch_time_lmt:4;
u8 srch_range_lmt;
u8 rsvd3;
};
/**
* @struct mac_ax_addrcam_dis_ctrl_t
* @brief mac_ax_addrcam_dis_ctrl_t
*
*/
struct mac_ax_addrcam_dis_ctrl_t {
u8 def_hit_idx;
u8 def_hit_result : 1;
u8 def_a1_hit_result : 1;
u8 def_a2_hit_result : 1;
u8 def_a3_hit_result : 1;
u8 def_port : 3;
u8 rsvd : 1;
u8 def_sec_idx;
u8 def_macid;
};
/**
* @struct mac_ax_dfs_rpt
* @brief mac_ax_dfs_rpt
*
* @var mac_ax_dfs_rpt::dfs_ptr
* Please Place Description here.
* @var mac_ax_dfs_rpt::drop_num
* Please Place Description here.
* @var mac_ax_dfs_rpt::max_cont_drop
* Please Place Description here.
* @var mac_ax_dfs_rpt::total_drop
* Please Place Description here.
* @var mac_ax_dfs_rpt::dfs_num
* Please Place Description here.
*/
struct mac_ax_dfs_rpt {
u8 *dfs_ptr;
u16 drop_num;
u16 max_cont_drop;
u16 total_drop;
u16 dfs_num;
};
/**
* @struct mac_ax_ppdu_usr
* @brief mac_ax_ppdu_usr
*
* @var mac_ax_ppdu_usr::vld
* Please Place Description here.
* @var mac_ax_ppdu_usr::has_data
* Please Place Description here.
* @var mac_ax_ppdu_usr::has_ctrl
* Please Place Description here.
* @var mac_ax_ppdu_usr::has_mgnt
* Please Place Description here.
* @var mac_ax_ppdu_usr::has_bcn
* Please Place Description here.
* @var mac_ax_ppdu_usr::macid
* Please Place Description here.
*/
struct mac_ax_ppdu_usr {
u8 vld:1;
u8 has_data:1;
u8 has_ctrl:1;
u8 has_mgnt:1;
u8 has_bcn:1;
u8 macid;
};
/**
* @struct mac_ax_ppdu_stat
* @brief mac_ax_ppdu_stat
*
* @var mac_ax_ppdu_stat::band
* Please Place Description here.
* @var mac_ax_ppdu_stat::bmp_append_info
* Please Place Description here.
* @var mac_ax_ppdu_stat::bmp_filter
* Please Place Description here.
* @var mac_ax_ppdu_stat::dup2fw_en
* Please Place Description here.
* @var mac_ax_ppdu_stat::dup2fw_len
* Please Place Description here.
*/
struct mac_ax_ppdu_stat {
u8 band;
#define MAC_AX_PPDU_MAC_INFO BIT(1)
#define MAC_AX_PPDU_PLCP BIT(3)
#define MAC_AX_PPDU_RX_CNT BIT(2)
u8 bmp_append_info;
#define MAC_AX_PPDU_HAS_A1M BIT(4)
#define MAC_AX_PPDU_HAS_CRC_OK BIT(5)
u8 bmp_filter;
u8 dup2fw_en;
u8 dup2fw_len;
};
/**
* @struct mac_ax_ch_info
* @brief mac_ax_ch_info
*
* @var mac_ax_ch_info::trigger
* Please Place Description here.
* @var mac_ax_ch_info::macid
* Please Place Description here.
* @var mac_ax_ch_info::bmp_filter
* Please Place Description here.
* @var mac_ax_ch_info::dis_to
* Please Place Description here.
* @var mac_ax_ch_info::seg_size
* Please Place Description here.
*/
struct mac_ax_ch_info {
#define MAC_AX_CH_INFO_MACID 0
#define MAC_AX_CH_INFO_NDP 1
#define MAC_AX_CH_INFO_SND 2
#define MAC_AX_CH_INFO_ACK 3
u8 trigger;
u8 macid;
#define MAC_AX_CH_INFO_CRC_FAIL BIT(0)
#define MAC_AX_CH_INFO_DATA_FRM BIT(1)
#define MAC_AX_CH_INFO_CTRL_FRM BIT(2)
#define MAC_AX_CH_INFO_MGNT_FRM BIT(3)
u8 bmp_filter;
u8 dis_to;
#define MAC_AX_CH_IFNO_SEG_128 0
#define MAC_AX_CH_IFNO_SEG_256 1
#define MAC_AX_CH_IFNO_SEG_512 2
#define MAC_AX_CH_IFNO_SEG_1024 3
u8 seg_size;
};
/**
* @struct mac_ax_dfs
* @brief mac_ax_dfs
*
* @var mac_ax_dfs::num_th
* Please Place Description here.
* @var mac_ax_dfs::en_timeout
* Please Place Description here.
*/
struct mac_ax_dfs {
#define MAC_AX_DFS_TH_29 0
#define MAC_AX_DFS_TH_61 1
#define MAC_AX_DFS_TH_93 2
#define MAC_AX_DFS_TH_125 3
u8 num_th;
u8 en_timeout;
};
/**
* @struct mac_ax_ppdu_rpt
* @brief mac_ax_ppdu_rpt
*
* @var mac_ax_ppdu_rpt::rx_cnt_ptr
* Please Place Description here.
* @var mac_ax_ppdu_rpt::plcp_ptr
* Please Place Description here.
* @var mac_ax_ppdu_rpt::phy_st_ptr
* Please Place Description here.
* @var mac_ax_ppdu_rpt::phy_st_size
* Please Place Description here.
* @var mac_ax_ppdu_rpt::rx_cnt_size
* Please Place Description here.
* @var mac_ax_ppdu_rpt::lsig_len
* Please Place Description here.
* @var mac_ax_ppdu_rpt::service
* Please Place Description here.
* @var mac_ax_ppdu_rpt::usr_num
* Please Place Description here.
* @var mac_ax_ppdu_rpt::fw_def
* Please Place Description here.
* @var mac_ax_ppdu_rpt::is_to_self
* Please Place Description here.
* @var mac_ax_ppdu_rpt::plcp_size
* Please Place Description here.
* @var mac_ax_ppdu_rpt::usr
* Please Place Description here.
*/
struct mac_ax_ppdu_rpt {
#define MAC_AX_PPDU_MAX_USR 4
u8 *rx_cnt_ptr;
u8 *plcp_ptr;
u8 *phy_st_ptr;
u32 phy_st_size;
u32 rx_cnt_size;
u16 lsig_len;
u16 service;
u8 usr_num;
u8 fw_def;
u8 is_to_self;
u8 plcp_size;
struct mac_ax_ppdu_usr usr[MAC_AX_PPDU_MAX_USR];
};
/**
* @struct mac_ax_phy_rpt_cfg
* @brief mac_ax_phy_rpt_cfg
*
* @var mac_ax_phy_rpt_cfg::type
* Please Place Description here.
* @var mac_ax_phy_rpt_cfg::en
* Please Place Description here.
* @var mac_ax_phy_rpt_cfg::dest
* Please Place Description here.
* @var mac_ax_phy_rpt_cfg::ppdu
* Please Place Description here.
* @var mac_ax_phy_rpt_cfg::chif
* Please Place Description here.
* @var mac_ax_phy_rpt_cfg::dfs
* Please Place Description here.
* @var mac_ax_phy_rpt_cfg::u
* Please Place Description here.
*/
struct mac_ax_phy_rpt_cfg {
enum mac_ax_phy_rpt type;
u8 en;
#define MAC_AX_PRPT_DEST_HOST 0
#define MAC_AX_PRPT_DEST_WLCPU 1
u8 dest;
union {
struct mac_ax_ppdu_stat ppdu;
struct mac_ax_ch_info chif;
struct mac_ax_dfs dfs;
} u;
};
/**
* @struct mac_ax_pkt_drop_info
* @brief mac_ax_pkt_drop_info
*
* @var mac_ax_pkt_drop_info::sel
* Please Place Description here.
* @var mac_ax_pkt_drop_info::macid
* Please Place Description here.
* @var mac_ax_pkt_drop_info::band
* Please Place Description here.
* @var mac_ax_pkt_drop_info::port
* Please Place Description here.
* @var mac_ax_pkt_drop_info::mbssid
* Please Place Description here.
*/
struct mac_ax_pkt_drop_info {
enum mac_ax_pkt_drop_sel sel;
u8 macid;
u8 band;
u8 port;
u8 mbssid;
};
/**
* @struct mac_ax_ch_busy_cnt_ref
* @brief mac_ax_ch_busy_cnt_ref
*
* @var mac_ax_ch_busy_cnt_ref::basic_nav
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::intra_nav
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::data_on
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::edcca_p20
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::cca_p20
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::cca_s20
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::cca_s40
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_ref::cca_s80
* Please Place Description here.
*/
struct mac_ax_ch_busy_cnt_ref {
u16 basic_nav:1;
u16 intra_nav:1;
u16 data_on:1;
u16 edcca_p20:1;
u16 cca_p20:1;
u16 cca_s20:1;
u16 cca_s40:1;
u16 cca_s80:1;
u16 phy_txon:1;
u16 rsvd:7;
};
/**
* @struct mac_ax_tx_queue_empty
* @brief mac_ax_tx_queue_empty
*
* @var mac_ax_tx_queue_empty::macid_txq_empty
* Please Place Description here.
* @var mac_ax_tx_queue_empty::band0_mgnt_empty
* Please Place Description here.
* @var mac_ax_tx_queue_empty::band1_mgnt_empty
* Please Place Description here.
* @var mac_ax_tx_queue_empty::fw_txq_empty
* Please Place Description here.
* @var mac_ax_tx_queue_empty::h2c_empty
* Please Place Description here.
* @var mac_ax_tx_queue_empty::others_empty
* Please Place Description here.
* @var mac_ax_tx_queue_empty::rsvd
* Please Place Description here.
*/
struct mac_ax_tx_queue_empty {
#define WDE_QEMPTY_ACQ_NUM_MAX 16 /* shall be the max num of all chip */
u8 macid_txq_empty[WDE_QEMPTY_ACQ_NUM_MAX];
u8 band0_mgnt_empty:1;
u8 band1_mgnt_empty:1;
u8 fw_txq_empty:1;
u8 h2c_empty:1;
u8 others_empty:1;
u8 rsvd:3;
};
/**
* @struct mac_ax_rx_queue_empty
* @brief mac_ax_rx_queue_empty
*
* @var mac_ax_rx_queue_empty::band0_rxq_empty
* Please Place Description here.
* @var mac_ax_rx_queue_empty::band1_rxq_empty
* Please Place Description here.
* @var mac_ax_rx_queue_empty::c2h_empty
* Please Place Description here.
* @var mac_ax_rx_queue_empty::others_empty
* Please Place Description here.
* @var mac_ax_rx_queue_empty::rsvd
* Please Place Description here.
*/
struct mac_ax_rx_queue_empty {
u8 band0_rxq_empty:1;
u8 band1_rxq_empty:1;
u8 c2h_empty:1;
u8 others_empty:1;
u8 rsvd:4;
};
/*--------------------Define TF2PCMD related struct --------------------------*/
/**
* @struct mac_ax_rura_report
* @brief mac_ax_rura_report
*
* @var mac_ax_rura_report::rt_tblcol
* Please Place Description here.
* @var mac_ax_rura_report::prtl_alloc
* Please Place Description here.
* @var mac_ax_rura_report::rate_chg
* Please Place Description here.
*/
struct mac_ax_rura_report {
u8 rt_tblcol: 6;
u8 prtl_alloc: 1;
u8 rate_chg: 1;
};
//for ul rua output
/**
* @struct mac_ax_ulru_out_sta_ent
* @brief mac_ax_ulru_out_sta_ent
*
* @var mac_ax_ulru_out_sta_ent::dropping
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::tgt_rssi
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::mac_id
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::ru_pos
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::coding
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::vip_flag
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::rsvd1
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::bsr_length
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::rsvd2
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::rate
* Please Place Description here.
* @var mac_ax_ulru_out_sta_ent::rpt
* Please Place Description here.
*/
struct mac_ax_ulru_out_sta_ent {
u8 dropping: 1;
u8 tgt_rssi: 7;
u8 mac_id;
u8 ru_pos;
u8 coding: 1;
u8 vip_flag: 1;
u8 rsvd1: 6;
u16 bsr_length: 15;
u16 rsvd2: 1;
struct mac_ax_ru_rate_ent rate;
struct mac_ax_rura_report rpt;
};
/**
* @struct mac_ax_ulrua_output
* @brief mac_ax_ulrua_output
*
* @var mac_ax_ulrua_output::ru2su
* Please Place Description here.
* @var mac_ax_ulrua_output::ppdu_bw
* Please Place Description here.
* @var mac_ax_ulrua_output::gi_ltf
* Please Place Description here.
* @var mac_ax_ulrua_output::stbc
* Please Place Description here.
* @var mac_ax_ulrua_output::doppler
* Please Place Description here.
* @var mac_ax_ulrua_output::n_ltf_and_ma
* Please Place Description here.
* @var mac_ax_ulrua_output::sta_num
* Please Place Description here.
* @var mac_ax_ulrua_output::rsvd1
* Please Place Description here.
* @var mac_ax_ulrua_output::rf_gain_fix
* Please Place Description here.
* @var mac_ax_ulrua_output::rf_gain_idx
* Please Place Description here.
* @var mac_ax_ulrua_output::tb_t_pe_nom
* Please Place Description here.
* @var mac_ax_ulrua_output::rsvd2
* Please Place Description here.
* @var mac_ax_ulrua_output::grp_mode
* Please Place Description here.
* @var mac_ax_ulrua_output::grp_id
* Please Place Description here.
* @var mac_ax_ulrua_output::fix_mode
* Please Place Description here.
* @var mac_ax_ulrua_output::rsvd3
* Please Place Description here.
* @var mac_ax_ulrua_output::sta
* Please Place Description here.
*/
struct mac_ax_ulrua_output {
u8 ru2su: 1;
u8 ppdu_bw: 2;
u8 gi_ltf: 3;
u8 stbc: 1;
u8 doppler: 1;
u8 n_ltf_and_ma: 3;
u8 sta_num: 4;
u8 rsvd1: 1;
u16 rf_gain_fix: 1;
u16 rf_gain_idx: 10;
u16 tb_t_pe_nom: 2;
u16 rsvd2: 3;
u32 grp_mode: 1;
u32 grp_id: 6;
u32 fix_mode: 1;
u32 rsvd3: 24;
struct mac_ax_ulru_out_sta_ent sta[MAC_AX_MAX_RU_NUM];
};
/**
* @struct mac_ul_macid_info
* @brief mac_ul_macid_info
*
* @var mac_ul_macid_info::macid
* Please Place Description here.
* @var mac_ul_macid_info::pref_AC
* Please Place Description here.
* @var mac_ul_macid_info::rsvd
* Please Place Description here.
*/
struct mac_ul_macid_info {
u8 macid;
u8 pref_AC:2;
u8 rsvd:6;
};
/**
* @struct mac_ul_mode_cfg
* @brief mac_ul_mode_cfg
*
* @var mac_ul_mode_cfg::mode
* Please Place Description here.
* @var mac_ul_mode_cfg::interval
* Please Place Description here.
* @var mac_ul_mode_cfg::bsr_thold
* Please Place Description here.
* @var mac_ul_mode_cfg::storemode
* Please Place Description here.
* @var mac_ul_mode_cfg::rsvd
* Please Place Description here.
*/
struct mac_ul_mode_cfg {
u32 mode:2; /* 0: peoridic ; 1: normal ; 2: non_tgr */
u32 interval:6; /* unit: sec */
u32 bsr_thold:8;
u32 storemode:2;
u32 rsvd:14;
};
/**
* @struct mac_ax_ul_fixinfo
* @brief mac_ax_ul_fixinfo
*
* @var mac_ax_ul_fixinfo::tbl_hdr
* Please Place Description here.
* @var mac_ax_ul_fixinfo::cfg
* Please Place Description here.
* @var mac_ax_ul_fixinfo::ndpa_dur
* Please Place Description here.
* @var mac_ax_ul_fixinfo::tf_type
* Please Place Description here.
* @var mac_ax_ul_fixinfo::sig_ta_pkten
* Please Place Description here.
* @var mac_ax_ul_fixinfo::sig_ta_pktsc
* Please Place Description here.
* @var mac_ax_ul_fixinfo::murts_flag
* Please Place Description here.
* @var mac_ax_ul_fixinfo::ndpa
* Please Place Description here.
* @var mac_ax_ul_fixinfo::snd_pkt_sel
* Please Place Description here.
* @var mac_ax_ul_fixinfo::gi_ltf
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_rate
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_er
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_bw
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_stbc
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_ldpc
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_dcm
* Please Place Description here.
* @var mac_ax_ul_fixinfo::apep_len
* Please Place Description here.
* @var mac_ax_ul_fixinfo::more_tf
* Please Place Description here.
* @var mac_ax_ul_fixinfo::data_bw_er
* Please Place Description here.
* @var mac_ax_ul_fixinfo::istwt
* Please Place Description here.
* @var mac_ax_ul_fixinfo::rsvd0
* Please Place Description here.
* @var mac_ax_ul_fixinfo::multiport_id
* Please Place Description here.
* @var mac_ax_ul_fixinfo::mbssid
* Please Place Description here.
* @var mac_ax_ul_fixinfo::txpwr_mode
* Please Place Description here.
* @var mac_ax_ul_fixinfo::ulfix_usage
* Please Place Description here.
* @var mac_ax_ul_fixinfo::twtgrp_stanum_sel
* Please Place Description here.
* @var mac_ax_ul_fixinfo::store_idx
* Please Place Description here.
* @var mac_ax_ul_fixinfo::rsvd1
* Please Place Description here.
* @var mac_ax_ul_fixinfo::sta
* Please Place Description here.
* @var mac_ax_ul_fixinfo::ulrua
* Please Place Description here.
*/
struct mac_ax_ul_fixinfo {
struct mac_ax_tbl_hdr tbl_hdr;
struct mac_ul_mode_cfg cfg;
u32 ndpa_dur:16;
u32 tf_type:3;
u32 sig_ta_pkten:1;
u32 sig_ta_pktsc:4;
u32 murts_flag:1;
u32 ndpa:2;
u32 snd_pkt_sel:2;
u32 gi_ltf:3;
u32 data_rate:9;
u32 data_er:1;
u32 data_bw:2;
u32 data_stbc:2;
u32 data_ldpc:1;
u32 data_dcm:1;
u32 apep_len:12;
u32 more_tf:1;
u32 data_bw_er:1;
u32 istwt:1;
u32 rsvd0:1;
u32 multiport_id:3;
u32 mbssid:4;
u32 txpwr_mode:3;
u32 ulfix_usage:3;
u32 twtgrp_stanum_sel:2;
u32 store_idx:4;
u32 rsvd1:13;
struct mac_ul_macid_info sta[4];
struct mac_ax_ulrua_output ulrua;
};
/**
* @struct mac_ax_mudecision_para
* @brief mac_ax_mudecision_para
*
* @var mac_ax_mudecision_para::tbl_hdr
* Please Place Description here.
* @var mac_ax_mudecision_para::mu_thold
* Please Place Description here.
* @var mac_ax_mudecision_para::bypass_thold
* Please Place Description here.
* @var mac_ax_mudecision_para::bypass_tp
* Please Place Description here.
*/
struct mac_ax_mudecision_para {
struct mac_ax_tbl_hdr tbl_hdr;
u32 mu_thold:30;
u32 bypass_thold:1; //macid bypass tx time thold check
u32 bypass_tp:1; //T1 unit:us
u32 init_rate: 4;
u32 retry_th: 3;
u32 rsvd: 25;
};
/**
* @struct mac_ax_protect_rsp_field
* @brief mac_ax_protect_rsp_field
*
* @var mac_ax_protect_rsp_field::protect
* Please Place Description here.
* @var mac_ax_protect_rsp_field::rsp
* Please Place Description here.
*/
struct mac_ax_protect_rsp_field {
u8 protect: 4;
u8 rsp: 4;
};
/**
* @struct mac_ax_mu_protect_rsp_type
* @brief mac_ax_mu_protect_rsp_type
*
* @var mac_ax_mu_protect_rsp_type::byte_type
* Please Place Description here.
* @var mac_ax_mu_protect_rsp_type::feld_type
* Please Place Description here.
* @var mac_ax_mu_protect_rsp_type::u
* Please Place Description here.
*/
struct mac_ax_mu_protect_rsp_type {
union {
u8 byte_type;
struct mac_ax_protect_rsp_field feld_type;
} u;
};
/**
* @struct mac_ax_mu_sta_upd
* @brief mac_ax_mu_sta_upd
*
* @var mac_ax_mu_sta_upd::macid
* Please Place Description here.
* @var mac_ax_mu_sta_upd::mu_idx
* Please Place Description here.
* @var mac_ax_mu_sta_upd::prot_rsp_type
* Please Place Description here.
* @var mac_ax_mu_sta_upd::mugrp_bitmap
* Please Place Description here.
* @var mac_ax_mu_sta_upd::dis_256q
* Please Place Description here.
* @var mac_ax_mu_sta_upd::dis_1024q
* Please Place Description here.
* @var mac_ax_mu_sta_upd::rsvd
* Please Place Description here.
*/
struct mac_ax_mu_sta_upd {
u8 macid;
u8 mu_idx;
struct mac_ax_mu_protect_rsp_type prot_rsp_type[5];
u8 mugrp_bitmap: 5;
u8 dis_256q: 1;
u8 dis_1024q: 1;
u8 rsvd: 1;
};
/**
* @struct mac_ax_wlaninfo_get
* @brief mac_ax_wlaninfo_get
*
* @var mac_ax_wlaninfo_get::info_sel
* Please Place Description here.
* @var mac_ax_wlaninfo_get::rsvd0
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv0
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv1
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv2
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv3
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv4
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv5
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv6
* Please Place Description here.
* @var mac_ax_wlaninfo_get::argv7
* Please Place Description here.
* @var mac_ax_wlaninfo_get::rsvd1
* Please Place Description here.
*/
struct mac_ax_wlaninfo_get {
u32 info_sel:4;
u32 rsvd0:4;
u32 argv0:8;
u32 argv1:8;
u32 argv2:8;
u32 argv3:8;
u32 argv4:8;
u32 argv5:8;
u32 argv6:8;
u32 argv7:8;
u32 rsvd1:24;
};
/**
* @struct mac_ax_ccxrpt
* @brief mac_ax_ccxrpt
*
* @var mac_ax_ccxrpt::macid
* Please Place Description here.
* @var mac_ax_ccxrpt::tx_state
* Please Place Description here.
* @var mac_ax_ccxrpt::sw_define
* Please Place Description here.
* @var mac_ax_ccxrpt::pkt_ok_num
* Please Place Description here.
* @var mac_ax_ccxrpt::rsvd0
* Please Place Description here.
*/
struct mac_ax_ccxrpt {
u32 macid:7;
u32 tx_state:2;
u32 sw_define:4;
u32 pkt_ok_num:8;
u32 data_txcnt:6;
u32 rsvd0:5;
};
/**
* @struct mac_ax_dumpwlanc
* @brief mac_ax_dumpwlanc
*
* @var mac_ax_dumpwlanc::cmdid
* Please Place Description here.
* @var mac_ax_dumpwlanc::rsvd0
* Please Place Description here.
*/
struct mac_ax_dumpwlanc {
u32 cmdid:8;
u32 rsvd0:24;
};
/**
* @struct mac_ax_dumpwlans
* @brief mac_ax_dumpwlans
*
* @var mac_ax_dumpwlans::cmdid
* Please Place Description here.
* @var mac_ax_dumpwlans::macid_grp
* Please Place Description here.
* @var mac_ax_dumpwlans::rsvd0
* Please Place Description here.
*/
struct mac_ax_dumpwlans {
u32 cmdid:8;
u32 macid_grp:8;
u32 rsvd0:16;
};
/**
* @struct mac_ax_dumpwland
* @brief mac_ax_dumpwland
*
* @var mac_ax_dumpwland::cmdid
* Please Place Description here.
* @var mac_ax_dumpwland::grp_type
* Please Place Description here.
* @var mac_ax_dumpwland::grp_id
* Please Place Description here.
* @var mac_ax_dumpwland::muru
* Please Place Description here.
* @var mac_ax_dumpwland::macid
* Please Place Description here.
*/
struct mac_ax_dumpwland {
u32 cmdid:8;
u32 grp_type:8;
u32 grp_id:8;
u32 muru:8;
u8 macid[4];
};
/**
* @struct mac_ax_fixmode_para
* @brief mac_ax_fixmode_para
*
* @var mac_ax_fixmode_para::tbl_hdr
* Please Place Description here.
* @var mac_ax_fixmode_para::force_sumuru_en
* Please Place Description here.
* @var mac_ax_fixmode_para::forcesu
* Please Place Description here.
* @var mac_ax_fixmode_para::forcemu
* Please Place Description here.
* @var mac_ax_fixmode_para::forceru
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_fe_su_en
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_fe_vhtmu_en
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_fe_hemu_en
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_fe_heru_en
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_fe_ul_en
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_frame_seq_su
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_frame_seq_vhtmu
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_frame_seq_hemu
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_frame_seq_heru
* Please Place Description here.
* @var mac_ax_fixmode_para::fix_frame_seq_ul
* Please Place Description here.
* @var mac_ax_fixmode_para::is_dlruhwgrp
* Please Place Description here.
* @var mac_ax_fixmode_para::is_ulruhwgrp
* Please Place Description here.
* @var mac_ax_fixmode_para::prot_type_su
* Please Place Description here.
* @var mac_ax_fixmode_para::prot_type_vhtmu
* Please Place Description here.
* @var mac_ax_fixmode_para::resp_type_vhtmu
* Please Place Description here.
* @var mac_ax_fixmode_para::prot_type_hemu
* Please Place Description here.
* @var mac_ax_fixmode_para::resp_type_hemu
* Please Place Description here.
* @var mac_ax_fixmode_para::prot_type_heru
* Please Place Description here.
* @var mac_ax_fixmode_para::resp_type_heru
* Please Place Description here.
* @var mac_ax_fixmode_para::ul_prot_type
* Please Place Description here.
* @var mac_ax_fixmode_para::rugrpid
* Please Place Description here.
* @var mac_ax_fixmode_para::mugrpid
* Please Place Description here.
* @var mac_ax_fixmode_para::ulgrpid
* Please Place Description here.
* @var mac_ax_fixmode_para::rsvd1
* Please Place Description here.
*/
struct mac_ax_fixmode_para {
struct mac_ax_tbl_hdr tbl_hdr;
u32 force_sumuru_en: 1;
u32 forcesu: 1;
u32 forcemu: 1;
u32 forceru: 1;
u32 fix_fe_su_en:1;
u32 fix_fe_vhtmu_en:1;
u32 fix_fe_hemu_en:1;
u32 fix_fe_heru_en:1;
u32 fix_fe_ul_en:1;
u32 fix_frame_seq_su: 1;
u32 fix_frame_seq_vhtmu: 1;
u32 fix_frame_seq_hemu: 1;
u32 fix_frame_seq_heru: 1;
u32 fix_frame_seq_ul: 1;
u32 is_dlruhwgrp: 1;
u32 is_ulruhwgrp:1;
u32 prot_type_su: 4;
u32 prot_type_vhtmu: 4;
u32 resp_type_vhtmu: 4;
u32 prot_type_hemu: 4;
u32 resp_type_hemu: 4;
u32 prot_type_heru: 4;
u32 resp_type_heru: 4;
u32 ul_prot_type: 4;
u32 rugrpid: 5;
u32 mugrpid:5;
u32 ulgrpid:5;
u32 rsvd1:1;
};
/**
* @struct mac_ax_tf_ba
* @brief mac_ax_tf_ba
*
* @var mac_ax_tf_ba::fix_ba
* Please Place Description here.
* @var mac_ax_tf_ba::ru_psd
* Please Place Description here.
* @var mac_ax_tf_ba::tf_rate
* Please Place Description here.
* @var mac_ax_tf_ba::rf_gain_fix
* Please Place Description here.
* @var mac_ax_tf_ba::rf_gain_idx
* Please Place Description here.
* @var mac_ax_tf_ba::tb_ppdu_bw
* Please Place Description here.
* @var mac_ax_tf_ba::rate
* Please Place Description here.
* @var mac_ax_tf_ba::gi_ltf
* Please Place Description here.
* @var mac_ax_tf_ba::doppler
* Please Place Description here.
* @var mac_ax_tf_ba::stbc
* Please Place Description here.
* @var mac_ax_tf_ba::sta_coding
* Please Place Description here.
* @var mac_ax_tf_ba::tb_t_pe_nom
* Please Place Description here.
* @var mac_ax_tf_ba::pr20_bw_en
* Please Place Description here.
* @var mac_ax_tf_ba::ma_type
* Please Place Description here.
* @var mac_ax_tf_ba::rsvd1
* Please Place Description here.
*/
struct mac_ax_tf_ba {
u32 fix_ba:1;
u32 ru_psd:9;
u32 tf_rate:9;
u32 rf_gain_fix:1;
u32 rf_gain_idx:10;
u32 tb_ppdu_bw:2;
struct mac_ax_ru_rate_ent rate;
u8 gi_ltf:3;
u8 doppler:1;
u8 stbc:1;
u8 sta_coding:1;
u8 tb_t_pe_nom:2;
u8 pr20_bw_en:1;
u8 ma_type: 1;
u8 rsvd1: 6;
};
/**
* @struct mac_ax_ba_infotbl
* @brief mac_ax_ba_infotbl
*
* @var mac_ax_ba_infotbl::tbl_hdr
* Please Place Description here.
* @var mac_ax_ba_infotbl::tfba
* Please Place Description here.
*/
struct mac_ax_ba_infotbl {
struct mac_ax_tbl_hdr tbl_hdr;
struct mac_ax_tf_ba tfba;
};
/**
* @struct mac_ax_dl_ru_grptbl
* @brief mac_ax_dl_ru_grptbl
*
* @var mac_ax_dl_ru_grptbl::tbl_hdr
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::ppdu_bw
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::tx_pwr
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::pwr_boost_fac
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::fix_mode_flag
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::rsvd1
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::rsvd
* Please Place Description here.
* @var mac_ax_dl_ru_grptbl::tf
* Please Place Description here.
*/
struct mac_ax_dl_ru_grptbl {
struct mac_ax_tbl_hdr tbl_hdr;
u16 ppdu_bw:2;
u16 tx_pwr:9;
u16 pwr_boost_fac:5;
u8 fix_mode_flag:1;
u8 rsvd1:7;
u8 rsvd;
struct mac_ax_tf_ba tf;
};
/**
* @struct mac_ax_ul_ru_grptbl
* @brief mac_ax_ul_ru_grptbl
*
* @var mac_ax_ul_ru_grptbl::tbl_hdr
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::grp_psd_max
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::grp_psd_min
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::tf_rate
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::fix_tf_rate
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::rsvd2
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::ppdu_bw
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::rf_gain_fix
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::rf_gain_idx
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::fix_mode_flag
* Please Place Description here.
* @var mac_ax_ul_ru_grptbl::rsvd1
* Please Place Description here.
*/
struct mac_ax_ul_ru_grptbl {
struct mac_ax_tbl_hdr tbl_hdr;
u32 grp_psd_max: 9;
u32 grp_psd_min: 9;
u32 tf_rate: 9;
u32 fix_tf_rate: 1;
u32 rsvd2: 4;
u16 ppdu_bw: 2;
u16 rf_gain_fix: 1;
u16 rf_gain_idx: 10;
u16 fix_mode_flag: 1;
u16 rsvd1: 2;
};
/**
* @struct mac_ax_bb_stainfo
* @brief mac_ax_bb_stainfo
*
* @var mac_ax_bb_stainfo::tbl_hdr
* Please Place Description here.
* @var mac_ax_bb_stainfo::gi_ltf_48spt
* Please Place Description here.
* @var mac_ax_bb_stainfo::gi_ltf_18spt
* Please Place Description here.
* @var mac_ax_bb_stainfo::rsvd3
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_info_en
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_bw
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_gi_ltf
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_doppler_ctrl
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_coding
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_txbf
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_stbc
* Please Place Description here.
* @var mac_ax_bb_stainfo::dl_fwcqi_flag
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlru_ratetbl_ridx
* Please Place Description here.
* @var mac_ax_bb_stainfo::csi_info_bitmap
* Please Place Description here.
* @var mac_ax_bb_stainfo::dl_swgrp_bitmap
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_dcm
* Please Place Description here.
* @var mac_ax_bb_stainfo::rsvd1
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_rate
* Please Place Description here.
* @var mac_ax_bb_stainfo::dlsu_pwr
* Please Place Description here.
* @var mac_ax_bb_stainfo::rsvd2
* Please Place Description here.
* @var mac_ax_bb_stainfo::rsvd4
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_info_en
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_bw
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_gi_ltf
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_doppler_ctrl
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_dcm
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_ss
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_mcs
* Please Place Description here.
* @var mac_ax_bb_stainfo::ul_fwcqi_flag
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulru_ratetbl_ridx
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_stbc
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_coding
* Please Place Description here.
* @var mac_ax_bb_stainfo::ulsu_rssi_m
* Please Place Description here.
* @var mac_ax_bb_stainfo::ul_swgrp_bitmap
* Please Place Description here.
*/
struct mac_ax_bb_stainfo {
struct mac_ax_tbl_hdr tbl_hdr;
//sta capability
u8 gi_ltf_48spt:1;
u8 gi_ltf_18spt:1;
u8 rsvd3:6;
//downlink su
u8 dlsu_info_en:1;
u8 dlsu_bw:2;
u8 dlsu_gi_ltf:3;
u8 dlsu_doppler_ctrl:2;
u8 dlsu_coding:1;
u8 dlsu_txbf:1;
u8 dlsu_stbc:1;
u8 dl_fwcqi_flag:1;
u8 dlru_ratetbl_ridx:4;
u8 csi_info_bitmap;
u32 dl_swgrp_bitmap;
u16 dlsu_dcm:1;
u16 rsvd1:6;
u16 dlsu_rate:9;
u8 dlsu_pwr:6;
u8 rsvd2:2;
u8 rsvd4;
//uplink su
u8 ulsu_info_en:1;
u8 ulsu_bw:2;
u8 ulsu_gi_ltf:3;
u8 ulsu_doppler_ctrl:2;
u8 ulsu_dcm:1;
u8 ulsu_ss:3;
u8 ulsu_mcs:4;
u16 ul_fwcqi_flag:1;
u16 ulru_ratetbl_ridx:4;
u16 ulsu_stbc:1;
u16 ulsu_coding:1;
u16 ulsu_rssi_m:9;
u32 ul_swgrp_bitmap;
//tb info
};
/**
* @struct mac_ax_tf_depend_user_para
* @brief mac_ax_tf_depend_user_para
*
* @var mac_ax_tf_depend_user_para::pref_AC
* Please Place Description here.
* @var mac_ax_tf_depend_user_para::rsvd
* Please Place Description here.
*/
struct mac_ax_tf_depend_user_para {
u8 pref_AC: 2;
u8 rsvd: 6;
};
/**
* @struct mac_ax_tf_user_para
* @brief mac_ax_tf_user_para
*
* @var mac_ax_tf_user_para::aid12
* Please Place Description here.
* @var mac_ax_tf_user_para::ul_mcs
* Please Place Description here.
* @var mac_ax_tf_user_para::macid
* Please Place Description here.
* @var mac_ax_tf_user_para::ru_pos
* Please Place Description here.
* @var mac_ax_tf_user_para::ul_fec_code
* Please Place Description here.
* @var mac_ax_tf_user_para::ul_dcm
* Please Place Description here.
* @var mac_ax_tf_user_para::ss_alloc
* Please Place Description here.
* @var mac_ax_tf_user_para::ul_tgt_rssi
* Please Place Description here.
* @var mac_ax_tf_user_para::rsvd
* Please Place Description here.
* @var mac_ax_tf_user_para::rsvd2
* Please Place Description here.
*/
struct mac_ax_tf_user_para {
u16 aid12: 12;
u16 ul_mcs: 4;
u8 macid;
u8 ru_pos;
u8 ul_fec_code: 1;
u8 ul_dcm: 1;
u8 ss_alloc: 6;
u8 ul_tgt_rssi: 7;
u8 rsvd: 1;
u16 rsvd2;
};
/**
* @struct mac_ax_tf_pkt_para
* @brief mac_ax_tf_pkt_para
*
* @var mac_ax_tf_pkt_para::ul_bw
* Please Place Description here.
* @var mac_ax_tf_pkt_para::gi_ltf
* Please Place Description here.
* @var mac_ax_tf_pkt_para::num_he_ltf
* Please Place Description here.
* @var mac_ax_tf_pkt_para::ul_stbc
* Please Place Description here.
* @var mac_ax_tf_pkt_para::doppler
* Please Place Description here.
* @var mac_ax_tf_pkt_para::ap_tx_power
* Please Place Description here.
* @var mac_ax_tf_pkt_para::rsvd0
* Please Place Description here.
* @var mac_ax_tf_pkt_para::user_num
* Please Place Description here.
* @var mac_ax_tf_pkt_para::pktnum
* Please Place Description here.
* @var mac_ax_tf_pkt_para::rsvd1
* Please Place Description here.
* @var mac_ax_tf_pkt_para::pri20_bitmap
* Please Place Description here.
* @var mac_ax_tf_pkt_para::user
* Please Place Description here.
* @var mac_ax_tf_pkt_para::dep_user
* Please Place Description here.
*/
struct mac_ax_tf_pkt_para {
u8 ul_bw: 2;
u8 gi_ltf: 2;
u8 num_he_ltf: 3;
u8 ul_stbc: 1;
u8 doppler: 1;
u8 ap_tx_power: 6;
u8 rsvd0: 1;
u8 user_num: 3;
u8 pktnum: 3;
u8 rsvd1: 2;
u8 pri20_bitmap;
struct mac_ax_tf_user_para user[MAC_AX_MAX_RU_NUM];
struct mac_ax_tf_depend_user_para dep_user[MAC_AX_MAX_RU_NUM];
};
/**
* @struct mac_ax_tf_wd_para
* @brief mac_ax_tf_wd_para
*
* @var mac_ax_tf_wd_para::datarate
* Please Place Description here.
* @var mac_ax_tf_wd_para::mulport_id
* Please Place Description here.
* @var mac_ax_tf_wd_para::pwr_ofset
* Please Place Description here.
* @var mac_ax_tf_wd_para::rsvd
* Please Place Description here.
*/
struct mac_ax_tf_wd_para {
u16 datarate: 9;
u16 mulport_id: 3;
u16 pwr_ofset: 3;
u16 rsvd: 1;
};
/**
* @struct mac_ax_f2p_test_para
* @brief mac_ax_f2p_test_para
*
* @var mac_ax_f2p_test_para::tf_pkt
* Please Place Description here.
* @var mac_ax_f2p_test_para::tf_wd
* Please Place Description here.
* @var mac_ax_f2p_test_para::mode
* Please Place Description here.
* @var mac_ax_f2p_test_para::frexch_type
* Please Place Description here.
* @var mac_ax_f2p_test_para::sigb_len
* Please Place Description here.
*/
struct mac_ax_f2p_test_para {
struct mac_ax_tf_pkt_para tf_pkt;
struct mac_ax_tf_wd_para tf_wd;
u8 mode: 2;
u8 frexch_type: 6;
u8 sigb_len;
};
/**
* @struct mac_ax_f2p_wd
* @brief mac_ax_f2p_wd
*
* @var mac_ax_f2p_wd::cmd_qsel
* Please Place Description here.
* @var mac_ax_f2p_wd::rsvd0
* Please Place Description here.
* @var mac_ax_f2p_wd::rsvd1
* Please Place Description here.
* @var mac_ax_f2p_wd::ls
* Please Place Description here.
* @var mac_ax_f2p_wd::fs
* Please Place Description here.
* @var mac_ax_f2p_wd::total_number
* Please Place Description here.
* @var mac_ax_f2p_wd::seq
* Please Place Description here.
* @var mac_ax_f2p_wd::length
* Please Place Description here.
* @var mac_ax_f2p_wd::rsvd2
* Please Place Description here.
*/
struct mac_ax_f2p_wd {
/* dword 0 */
u32 cmd_qsel:6;
u32 rsvd0:2;
u32 rsvd1:2;
u32 ls:1;
u32 fs:1;
u32 total_number:4;
u32 seq:8;
u32 length:8;
/* dword 1 */
u32 rsvd2;
};
/**
* @struct mac_ax_f2p_tx_cmd
* @brief mac_ax_f2p_tx_cmd
*
* @var mac_ax_f2p_tx_cmd::cmd_type
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::cmd_sub_type
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_user_num
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::bw
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::tx_power
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::fw_define
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ss_sel_mode
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::next_qsel
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::twt_group
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dis_chk_slp
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ru_mu_2_su
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_t_pe
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_ch1_len
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_ch2_len
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_sym_num
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_ch2_ofs
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dis_htp_ack
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::tx_time_ref
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pri_user_idx
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ampdu_max_txtime
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::group_id
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::twt_chk_en
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::twt_port_id
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::twt_start_time
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::twt_end_time
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::apep_len
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::tri_pad
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_t_pe
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rf_gain_idx
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::fixed_gain_en
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_gi_ltf
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_doppler
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_stbc
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_mid_per
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_cqi_rrp_tri
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd4
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_dcm
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_comp
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::doppler
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::stbc
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::mid_per
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::gi_ltf_size
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::sigb_mcs
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd5
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::macid_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ac_type_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::mu_sta_pos_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_rate_idx_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_dcm_en_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd6
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ru_alo_idx_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pwr_boost_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_ext_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_addr_idx_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_dcm_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_fec_cod_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_rate_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd8
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd9
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::macid_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ac_type_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::mu_sta_pos_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_rate_idx_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_dcm_en_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd10
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ru_alo_idx_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pwr_boost_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_ext_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_addr_idx_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_dcm_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_fec_cod_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_rate_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd12
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd13
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::macid_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ac_type_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::mu_sta_pos_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_rate_idx_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_dcm_en_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd14
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ru_alo_idx_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pwr_boost_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_ext_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_addr_idx_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_dcm_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_fec_cod_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_rate_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd16
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd17
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::macid_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ac_type_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::mu_sta_pos_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_rate_idx_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::dl_dcm_en_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd18
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ru_alo_idx_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pwr_boost_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::agg_bmp_alo_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ampdu_max_txnum_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::user_define_ext_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_addr_idx_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_dcm_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_fec_cod_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_rate_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd20
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_ru_alo_idx_u3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd21
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pkt_id_0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd22
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::valid_0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_user_num_0
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd23
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pkt_id_1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd24
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::valid_1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_user_num_1
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd25
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pkt_id_2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd26
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::valid_2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_user_num_2
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd27
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pkt_id_3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd28
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::valid_3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_user_num_3
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd29
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pkt_id_4
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd30
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::valid_4
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_user_num_4
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd31
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::pkt_id_5
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd32
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::valid_5
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::ul_user_num_5
* Please Place Description here.
* @var mac_ax_f2p_tx_cmd::rsvd33
* Please Place Description here.
*/
struct mac_ax_f2p_tx_cmd {
/* dword 0 */
u32 cmd_type:8;
u32 cmd_sub_type:8;
u32 dl_user_num:5;
u32 bw:2;
u32 tx_power:9;
/* dword 1 */
u32 fw_define:16;
u32 ss_sel_mode:2;
u32 next_qsel:6;
u32 twt_group:4;
u32 dis_chk_slp:1;
u32 ru_mu_2_su:1;
u32 dl_t_pe:2;
/* dword 2 */
u32 sigb_ch1_len:8;
u32 sigb_ch2_len:8;
u32 sigb_sym_num:6;
u32 sigb_ch2_ofs:5;
u32 dis_htp_ack:1;
u32 tx_time_ref:2;
u32 pri_user_idx:2;
/* dword 3 */
u32 ampdu_max_txtime:14;
u32 rsvd0:2;
u32 group_id:6;
u32 rsvd1:2;
u32 rsvd2:4;
u32 twt_chk_en:1;
u32 twt_port_id:3;
/* dword 4 */
u32 twt_start_time:32;
/* dword 5 */
u32 twt_end_time:32;
/* dword 6 */
u32 apep_len:12;
u32 tri_pad:2;
u32 ul_t_pe:2;
u32 rf_gain_idx:10;
u32 fixed_gain_en:1;
u32 ul_gi_ltf:3;
u32 ul_doppler:1;
u32 ul_stbc:1;
/* dword 7 */
u32 ul_mid_per:1;
u32 ul_cqi_rrp_tri:1;
u32 rsvd3:6;
u32 rsvd4:8;
u32 sigb_dcm:1;
u32 sigb_comp:1;
u32 doppler:1;
u32 stbc:1;
u32 mid_per:1;
u32 gi_ltf_size:3;
u32 sigb_mcs:3;
u32 rsvd5:5;
/* dword 8 */
u32 macid_u0:8;
u32 ac_type_u0:2;
u32 mu_sta_pos_u0:2;
u32 dl_rate_idx_u0:9;
u32 dl_dcm_en_u0:1;
u32 rsvd6:2;
u32 ru_alo_idx_u0:8;
/* dword 9 */
u32 pwr_boost_u0:5;
u32 agg_bmp_alo_u0:3;
u32 ampdu_max_txnum_u0:8;
u32 user_define_u0:8;
u32 user_define_ext_u0:8;
/* dword 10 */
u32 ul_addr_idx_u0:8;
u32 ul_dcm_u0:1;
u32 ul_fec_cod_u0:1;
u32 ul_ru_rate_u0:7;
u32 rsvd8:7;
u32 ul_ru_alo_idx_u0:8;
/* dword 11 */
u32 rsvd9:32;
/* dword 12 */
u32 macid_u1:8;
u32 ac_type_u1:2;
u32 mu_sta_pos_u1:2;
u32 dl_rate_idx_u1:9;
u32 dl_dcm_en_u1:1;
u32 rsvd10:2;
u32 ru_alo_idx_u1:8;
/* dword 13 */
u32 pwr_boost_u1:5;
u32 agg_bmp_alo_u1:3;
u32 ampdu_max_txnum_u1:8;
u32 user_define_u1:8;
u32 user_define_ext_u1:8;
/* dword 14 */
u32 ul_addr_idx_u1:8;
u32 ul_dcm_u1:1;
u32 ul_fec_cod_u1:1;
u32 ul_ru_rate_u1:7;
u32 rsvd12:7;
u32 ul_ru_alo_idx_u1:8;
/* dword 15 */
u32 rsvd13:32;
/* dword 16 */
u32 macid_u2:8;
u32 ac_type_u2:2;
u32 mu_sta_pos_u2:2;
u32 dl_rate_idx_u2:9;
u32 dl_dcm_en_u2:1;
u32 rsvd14:2;
u32 ru_alo_idx_u2:8;
/* dword 17 */
u32 pwr_boost_u2:5;
u32 agg_bmp_alo_u2:3;
u32 ampdu_max_txnum_u2:8;
u32 user_define_u2:8;
u32 user_define_ext_u2:8;
/* dword 18 */
u32 ul_addr_idx_u2:8;
u32 ul_dcm_u2:1;
u32 ul_fec_cod_u2:1;
u32 ul_ru_rate_u2:7;
u32 rsvd16:7;
u32 ul_ru_alo_idx_u2:8;
/* dword 19 */
u32 rsvd17:32;
/* dword 20 */
u32 macid_u3:8;
u32 ac_type_u3:2;
u32 mu_sta_pos_u3:2;
u32 dl_rate_idx_u3:9;
u32 dl_dcm_en_u3:1;
u32 rsvd18:2;
u32 ru_alo_idx_u3:8;
/* dword 21 */
u32 pwr_boost_u3:5;
u32 agg_bmp_alo_u3:3;
u32 ampdu_max_txnum_u3:8;
u32 user_define_u3:8;
u32 user_define_ext_u3:8;
/* dword 22 */
u32 ul_addr_idx_u3:8;
u32 ul_dcm_u3:1;
u32 ul_fec_cod_u3:1;
u32 ul_ru_rate_u3:7;
u32 rsvd20:7;
u32 ul_ru_alo_idx_u3:8;
/* dword 23 */
u32 rsvd21:32;
/* dword 24 */
u32 pkt_id_0:12;
u32 rsvd22:3;
u32 valid_0:1;
u32 ul_user_num_0:4;
u32 rsvd23:12;
/* dword 25 */
u32 pkt_id_1:12;
u32 rsvd24:3;
u32 valid_1:1;
u32 ul_user_num_1:4;
u32 rsvd25:12;
/* dword 26 */
u32 pkt_id_2:12;
u32 rsvd26:3;
u32 valid_2:1;
u32 ul_user_num_2:4;
u32 rsvd27:12;
/* dword 27 */
u32 pkt_id_3:12;
u32 rsvd28:3;
u32 valid_3:1;
u32 ul_user_num_3:4;
u32 rsvd29:12;
/* dword 28 */
u32 pkt_id_4:12;
u32 rsvd30:3;
u32 valid_4:1;
u32 ul_user_num_4:4;
u32 rsvd31:12;
/* dword 29 */
u32 pkt_id_5:12;
u32 rsvd32:3;
u32 valid_5:1;
u32 ul_user_num_5:4;
u32 rsvd33:12;
};
/*--------------------Define Sounding related struct -------------------------*/
/**
* @struct mac_reg_csi_para
* @brief mac_reg_csi_para
*
* @var mac_reg_csi_para::band
* Please Place Description here.
* @var mac_reg_csi_para::portsel
* Please Place Description here.
* @var mac_reg_csi_para::nc
* Please Place Description here.
* @var mac_reg_csi_para::nr
* Please Place Description here.
* @var mac_reg_csi_para::ng
* Please Place Description here.
* @var mac_reg_csi_para::cb
* Please Place Description here.
* @var mac_reg_csi_para::cs
* Please Place Description here.
* @var mac_reg_csi_para::ldpc_en
* Please Place Description here.
* @var mac_reg_csi_para::stbc_en
* Please Place Description here.
* @var mac_reg_csi_para::bf_en
* Please Place Description here.
*/
struct mac_reg_csi_para {
u32 band: 1;
u32 portsel: 1;
u32 nc: 3;
u32 nr: 3;
u32 ng: 2;
u32 cb: 2;
u32 cs: 2;
u32 ldpc_en: 1;
u32 stbc_en: 1;
u32 bf_en: 1;
};
/**
* @struct mac_cctl_csi_para
* @brief mac_cctl_csi_para
*
* @var mac_cctl_csi_para::macid
* Please Place Description here.
* @var mac_cctl_csi_para::band
* Please Place Description here.
* @var mac_cctl_csi_para::nc
* Please Place Description here.
* @var mac_cctl_csi_para::nr
* Please Place Description here.
* @var mac_cctl_csi_para::ng
* Please Place Description here.
* @var mac_cctl_csi_para::cb
* Please Place Description here.
* @var mac_cctl_csi_para::cs
* Please Place Description here.
* @var mac_cctl_csi_para::bf_en
* Please Place Description here.
* @var mac_cctl_csi_para::stbc_en
* Please Place Description here.
* @var mac_cctl_csi_para::ldpc_en
* Please Place Description here.
* @var mac_cctl_csi_para::rate
* Please Place Description here.
* @var mac_cctl_csi_para::gi_ltf
* Please Place Description here.
* @var mac_cctl_csi_para::gid_sel
* Please Place Description here.
* @var mac_cctl_csi_para::bw
* Please Place Description here.
*/
struct mac_cctl_csi_para {
u8 macid;
u32 band: 1;
u32 nc: 3;
u32 nr: 3;
u32 ng: 2;
u32 cb: 2;
u32 cs: 2;
u32 bf_en: 1;
u32 stbc_en: 1;
u32 ldpc_en: 1;
u32 rate: 9;
u32 gi_ltf: 3;
u32 gid_sel: 1;
u32 bw: 2;
};
/**
* @struct mac_bf_sup
* @brief mac_bf_sup
*
* @var mac_bf_sup::bf_entry_num
* Please Place Description here.
* @var mac_bf_sup::su_buffer_num
* Please Place Description here.
* @var mac_bf_sup::mu_buffer_num
* Please Place Description here.
*/
struct mac_bf_sup {
u32 bf_entry_num;
u32 su_buffer_num;
u32 mu_buffer_num;
};
/**
* @struct mac_gid_pos
* @brief mac_gid_pos
*
* @var mac_gid_pos::gid_en
* Please Place Description here.
* @var mac_gid_pos::gid_pos
* Please Place Description here.
*/
struct mac_gid_pos {
u32 band;
u32 gid_tab[2];
u32 user_pos[4];
};
/**
* @struct mac_ax_ndpa_hdr
* @brief mac_ax_ndpa_hdr
*
* @var mac_ax_ndpa_hdr::frame_ctl
* Please Place Description here.
* @var mac_ax_ndpa_hdr::duration
* Please Place Description here.
* @var mac_ax_ndpa_hdr::addr1
* Please Place Description here.
* @var mac_ax_ndpa_hdr::addr2
* Please Place Description here.
*/
struct mac_ax_ndpa_hdr {
u16 frame_ctl;
u16 duration;
u8 addr1[6];
u8 addr2[6];
};
/**
* @struct mac_ax_snd_dialog
* @brief mac_ax_snd_dialog
*
* @var mac_ax_snd_dialog::he
* Please Place Description here.
* @var mac_ax_snd_dialog::dialog
* Please Place Description here.
* @var mac_ax_snd_dialog::rsvd
* Please Place Description here.
*/
struct mac_ax_snd_dialog {
u32 he: 1;
u32 dialog: 6;
u32 rsvd: 25;
};
/**
* @struct mac_ax_ht_ndpa_para
* @brief mac_ax_ht_ndpa_para
*
* @var mac_ax_ht_ndpa_para::addr3
* Please Place Description here.
* @var mac_ax_ht_ndpa_para::seq_control
* Please Place Description here.
*/
struct mac_ax_ht_ndpa_para {
u8 addr3[WLAN_ADDR_LEN];
u16 seq_control;
};
/**
* @struct mac_ax_vht_ndpa_sta_info
* @brief mac_ax_vht_ndpa_sta_info
*
* @var mac_ax_vht_ndpa_sta_info::aid
* Please Place Description here.
* @var mac_ax_vht_ndpa_sta_info::fb_type
* Please Place Description here.
* @var mac_ax_vht_ndpa_sta_info::nc
* Please Place Description here.
*/
struct mac_ax_vht_ndpa_sta_info {
u16 aid: 12;
u16 fb_type: 1;
u16 nc: 3;
};
/**
* @struct mac_ax_vht_ndpa_para
* @brief mac_ax_vht_ndpa_para
*
* @var mac_ax_vht_ndpa_para::sta_info
* Please Place Description here.
*/
struct mac_ax_vht_ndpa_para {
struct mac_ax_vht_ndpa_sta_info sta_info[MAX_VHT_SUPPORT_SOUND_STA];
};
/**
* @struct mac_ax_he_ndpa_sta_info
* @brief mac_ax_he_ndpa_sta_info
*
* @var mac_ax_he_ndpa_sta_info::aid
* Please Place Description here.
* @var mac_ax_he_ndpa_sta_info::bw
* Please Place Description here.
* @var mac_ax_he_ndpa_sta_info::fb_ng
* Please Place Description here.
* @var mac_ax_he_ndpa_sta_info::disambiguation
* Please Place Description here.
* @var mac_ax_he_ndpa_sta_info::cb
* Please Place Description here.
* @var mac_ax_he_ndpa_sta_info::nc
* Please Place Description here.
*/
struct mac_ax_he_ndpa_sta_info {
u32 aid: 11;
u32 bw: 14;
u32 fb_ng: 2;
u32 disambiguation: 1;
u32 cb: 1;
u32 nc: 3;
};
/**
* @struct mac_ax_he_ndpa_para
* @brief mac_ax_he_ndpa_para
*
* @var mac_ax_he_ndpa_para::sta_info
* Please Place Description here.
*/
struct mac_ax_he_ndpa_para {
struct mac_ax_he_ndpa_sta_info sta_info[MAX_HE_SUPPORT_SOUND_STA];
};
/**
* @struct mac_ax_ndpa_para
* @brief mac_ax_ndpa_para
*
* @var mac_ax_ndpa_para::common
* Please Place Description here.
* @var mac_ax_ndpa_para::snd_dialog
* Please Place Description here.
* @var mac_ax_ndpa_para::ht_para
* Please Place Description here.
* @var mac_ax_ndpa_para::vht_para
* Please Place Description here.
* @var mac_ax_ndpa_para::he_para
* Please Place Description here.
*/
struct mac_ax_ndpa_para {
struct mac_ax_ndpa_hdr common;
struct mac_ax_snd_dialog snd_dialog;
struct mac_ax_ht_ndpa_para ht_para;
struct mac_ax_vht_ndpa_para vht_para;
struct mac_ax_he_ndpa_para he_para;
};
/**
* @struct mac_ax_bfrp_hdr
* @brief mac_ax_bfrp_hdr
*
* @var mac_ax_bfrp_hdr::frame_ctl
* Please Place Description here.
* @var mac_ax_bfrp_hdr::duration
* Please Place Description here.
* @var mac_ax_bfrp_hdr::addr1
* Please Place Description here.
* @var mac_ax_bfrp_hdr::addr2
* Please Place Description here.
*/
struct mac_ax_bfrp_hdr {
u16 frame_ctl;
u16 duration;
u8 addr1[WLAN_ADDR_LEN];
u8 addr2[WLAN_ADDR_LEN];
};
/**
* @struct mac_ax_vht_bfrp_para
* @brief mac_ax_vht_bfrp_para
*
* @var mac_ax_vht_bfrp_para::retransmission_bitmap
* Please Place Description here.
*/
struct mac_ax_vht_bfrp_para {
u8 retransmission_bitmap;
};
/**
* @struct mac_ax_he_bfrp_common
* @brief mac_ax_he_bfrp_common
*
* @var mac_ax_he_bfrp_common::tgr_info
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ul_len
* Please Place Description here.
* @var mac_ax_he_bfrp_common::more_tf
* Please Place Description here.
* @var mac_ax_he_bfrp_common::cs_rqd
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ul_bw
* Please Place Description here.
* @var mac_ax_he_bfrp_common::gi_ltf
* Please Place Description here.
* @var mac_ax_he_bfrp_common::mimo_ltfmode
* Please Place Description here.
* @var mac_ax_he_bfrp_common::num_heltf
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ul_pktext
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ul_stbc
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ldpc_extra_sym
* Please Place Description here.
* @var mac_ax_he_bfrp_common::dplr
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ap_tx_pwr
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ul_sr
* Please Place Description here.
* @var mac_ax_he_bfrp_common::ul_siga2_rsvd
* Please Place Description here.
* @var mac_ax_he_bfrp_common::rsvd
* Please Place Description here.
*/
struct mac_ax_he_bfrp_common {
u32 tgr_info: 4;
u32 ul_len: 12;
u32 more_tf: 1;
u32 cs_rqd: 1;
u32 ul_bw: 2;
u32 gi_ltf: 2;
u32 mimo_ltfmode: 1;
u32 num_heltf: 3;
u32 ul_pktext: 3;
u32 ul_stbc: 1;
u32 ldpc_extra_sym: 1;
u32 dplr: 1;
u32 ap_tx_pwr: 6;
u32 ul_sr: 16;
u32 ul_siga2_rsvd: 9;
u32 rsvd: 1;
};
/**
* @struct mac_ax_he_bfrp_user
* @brief mac_ax_he_bfrp_user
*
* @var mac_ax_he_bfrp_user::aid12
* Please Place Description here.
* @var mac_ax_he_bfrp_user::ru_pos
* Please Place Description here.
* @var mac_ax_he_bfrp_user::ul_fec_code
* Please Place Description here.
* @var mac_ax_he_bfrp_user::ul_mcs
* Please Place Description here.
* @var mac_ax_he_bfrp_user::ul_dcm
* Please Place Description here.
* @var mac_ax_he_bfrp_user::ss_alloc
* Please Place Description here.
* @var mac_ax_he_bfrp_user::fbseg_rexmit_bmp
* Please Place Description here.
* @var mac_ax_he_bfrp_user::ul_tgt_rssi
* Please Place Description here.
* @var mac_ax_he_bfrp_user::rsvd
* Please Place Description here.
*/
struct mac_ax_he_bfrp_user {
u32 aid12: 12;
u32 ru_pos: 8;
u32 ul_fec_code: 1;
u32 ul_mcs: 4;
u32 ul_dcm: 1;
u32 ss_alloc: 6;
u32 fbseg_rexmit_bmp: 8;
u32 ul_tgt_rssi: 7;
u32 rsvd: 17;
};
/**
* @struct mac_ax_he_bfrp_para
* @brief mac_ax_he_bfrp_para
*
* @var mac_ax_he_bfrp_para::common
* Please Place Description here.
* @var mac_ax_he_bfrp_para::user
* Please Place Description here.
*/
struct mac_ax_he_bfrp_para {
struct mac_ax_he_bfrp_common common;
struct mac_ax_he_bfrp_user user[4];
};
/**
* @struct mac_ax_bfrp_para
* @brief mac_ax_bfrp_para
*
* @var mac_ax_bfrp_para::hdr
* Please Place Description here.
* @var mac_ax_bfrp_para::he_para
* Please Place Description here.
* @var mac_ax_bfrp_para::vht_para
* Please Place Description here.
* @var mac_ax_bfrp_para::rsvd
* Please Place Description here.
*/
struct mac_ax_bfrp_para {
struct mac_ax_bfrp_hdr hdr[3];
struct mac_ax_he_bfrp_para he_para[2];
struct mac_ax_vht_bfrp_para vht_para[3];
u8 rsvd;
};
/**
* @struct mac_ax_snd_wd_para
* @brief mac_ax_snd_wd_para
*
* @var mac_ax_snd_wd_para::txpktsize
* Please Place Description here.
* @var mac_ax_snd_wd_para::ndpa_duration
* Please Place Description here.
* @var mac_ax_snd_wd_para::datarate
* Please Place Description here.
* @var mac_ax_snd_wd_para::macid
* Please Place Description here.
* @var mac_ax_snd_wd_para::force_txop
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_bw
* Please Place Description here.
* @var mac_ax_snd_wd_para::gi_ltf
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_er
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_dcm
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_stbc
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_ldpc
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_bw_er
* Please Place Description here.
* @var mac_ax_snd_wd_para::multiport_id
* Please Place Description here.
* @var mac_ax_snd_wd_para::mbssid
* Please Place Description here.
* @var mac_ax_snd_wd_para::signaling_ta_pkt_sc
* Please Place Description here.
* @var mac_ax_snd_wd_para::sw_define
* Please Place Description here.
* @var mac_ax_snd_wd_para::txpwr_ofset_type
* Please Place Description here.
* @var mac_ax_snd_wd_para::lifetime_sel
* Please Place Description here.
* @var mac_ax_snd_wd_para::stf_mode
* Please Place Description here.
* @var mac_ax_snd_wd_para::disdatafb
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_txcnt_lmt_sel
* Please Place Description here.
* @var mac_ax_snd_wd_para::data_txcnt_lmt
* Please Place Description here.
* @var mac_ax_snd_wd_para::sifs_tx
* Please Place Description here.
* @var mac_ax_snd_wd_para::snd_pkt_sel
* Please Place Description here.
* @var mac_ax_snd_wd_para::ndpa
* Please Place Description here.
* @var mac_ax_snd_wd_para::rsvd
* Please Place Description here.
*/
struct mac_ax_snd_wd_para {
u16 txpktsize;
u16 ndpa_duration;
u16 datarate: 9;
u16 macid: 7;//wd
u8 force_txop: 1;
u8 data_bw: 2;
u8 gi_ltf: 3;
u8 data_er: 1;
u8 data_dcm: 1;
u8 data_stbc: 1;
u8 data_ldpc: 1;
u8 data_bw_er : 1;
u8 multiport_id: 1;
u8 mbssid: 4;
u8 signaling_ta_pkt_sc: 4;
u8 sw_define: 4;
u8 txpwr_ofset_type: 3;
u8 lifetime_sel: 3;
u8 stf_mode: 1;
u8 disdatafb: 1;
u8 data_txcnt_lmt_sel: 1;
u8 data_txcnt_lmt: 6;
u8 sifs_tx: 1;
u8 snd_pkt_sel: 3;
u8 ndpa: 2;
u8 rsvd: 3;
};
/**
* @struct mac_ax_snd_f2P
* @brief mac_ax_snd_f2P
*
* @var mac_ax_snd_f2P::csi_len_bfrp
* Please Place Description here.
* @var mac_ax_snd_f2P::tb_t_pe_bfrp
* Please Place Description here.
* @var mac_ax_snd_f2P::tri_pad_bfrp
* Please Place Description here.
* @var mac_ax_snd_f2P::ul_cqi_rpt_tri_bfrp
* Please Place Description here.
* @var mac_ax_snd_f2P::rf_gain_idx_bfrp
* Please Place Description here.
* @var mac_ax_snd_f2P::fix_gain_en_bfrp
* Please Place Description here.
* @var mac_ax_snd_f2P::rsvd
* Please Place Description here.
*/
struct mac_ax_snd_f2P {
u16 csi_len_bfrp: 12;
u16 tb_t_pe_bfrp: 2;
u16 tri_pad_bfrp: 2;
u16 ul_cqi_rpt_tri_bfrp: 1;
u16 rf_gain_idx_bfrp: 10;
u16 fix_gain_en_bfrp: 1;
u16 rsvd: 4;
};
/**
* @struct mac_ax_snd_f2P_info
* @brief mac_ax_snd_f2P_info
*
* @var mac_ax_snd_f2p_info::f2p_type
* Please Place Description here.
* @var mac_ax_snd_f2p_info::f2p_index
* Please Place Description here.
* @var mac_ax_snd_f2p_info::f2p_period
* Please Place Description here.
* @var mac_ax_snd_f2p_info::f2p_updcnt
* Please Place Description here.
* @var mac_ax_snd_f2p_info:cr_idx
* Please Place Description here.
* @var mac_ax_snd_f2p_info::rsvd
* Please Place Description here..
*/
struct mac_ax_snd_f2p_info {
u16 f2p_type: 8;
u16 f2p_index: 8;
u16 f2p_period;
u32 f2p_updcnt: 8;
u32 cr_idx: 22;
u32 rsvd: 2;
};
/**
* @struct mac_ax_fwcmd_snd
* @brief mac_ax_fwcmd_snd
*
* @var mac_ax_fwcmd_snd::frexgtype
* Please Place Description here.
* @var mac_ax_fwcmd_snd::mode
* Please Place Description here.
* @var mac_ax_fwcmd_snd::bfrp0_user_num
* Please Place Description here.
* @var mac_ax_fwcmd_snd::bfrp1_user_num
* Please Place Description here.
* @var mac_ax_fwcmd_snd::rsvd
* Please Place Description here.
* @var mac_ax_fwcmd_snd::macid
* Please Place Description here.
* @var mac_ax_fwcmd_snd::pndpa
* Please Place Description here.
* @var mac_ax_fwcmd_snd::pbfrp
* Please Place Description here.
* @var mac_ax_fwcmd_snd::wd
* Please Place Description here.
* @var mac_ax_fwcmd_snd::f2p
* Please Place Description here.
*/
struct mac_ax_fwcmd_snd {
u32 frexgtype: 6;
u32 mode: 2;
u32 bfrp0_user_num: 3;
u32 bfrp1_user_num: 3;
u32 rsvd: 18;
u8 macid[8];
struct mac_ax_ndpa_para pndpa;
struct mac_ax_bfrp_para pbfrp;
struct mac_ax_snd_wd_para wd[5];
struct mac_ax_snd_f2P f2p[2];
struct mac_ax_snd_f2p_info sfp;
};
/**
* @struct mac_ax_ie_cam_info
* @brief mac_ax_ie_cam_info
*
* @var mac_ax_ie_cam_info::type
* Please Place Description here.
* @var mac_ax_ie_cam_info::ienum_ie
* Please Place Description here.
* @var mac_ax_ie_cam_info::ie_ofst_len
* Please Place Description here.
* @var mac_ax_ie_cam_info::ie_msk_crc
* Please Place Description here.
* @var mac_ax_ie_cam_info::ie_val
* Please Place Description here.
* @var mac_ax_ie_cam_info::rsvd0
* Please Place Description here.
* @var mac_ax_ie_cam_info::rsvd1
* Please Place Description here.
* @var mac_ax_ie_cam_info::rsvd2
* Please Place Description here.
*/
struct mac_ax_ie_cam_info {
u8 type;
u8 ienum_ie;
u8 ie_ofst_len;
u8 ie_msk_crc;
u8 ie_val;
u8 rsvd0;
u8 rsvd1;
u8 rsvd2;
};
/*--------------------Define wowlan related struct ---------------------------*/
/**
* @struct mac_ax_keep_alive_info
* @brief mac_ax_keep_alive_info
*
* @var mac_ax_keep_alive_info::keepalive_en
* Please Place Description here.
* @var mac_ax_keep_alive_info::rsvd
* Please Place Description here.
* @var mac_ax_keep_alive_info::packet_id
* Please Place Description here.
* @var mac_ax_keep_alive_info::period
* Please Place Description here.
*/
struct mac_ax_keep_alive_info {
u8 keepalive_en: 1;
u8 rsvd: 7;
u8 packet_id;
u8 period;
};
/**
* @struct mac_ax_disconnect_det_info
* @brief mac_ax_disconnect_det_info
*
* @var mac_ax_disconnect_det_info::disconnect_detect_en
* Please Place Description here.
* @var mac_ax_disconnect_det_info::tryok_bcnfail_count_en
* Please Place Description here.
* @var mac_ax_disconnect_det_info::disconnect_en
* Please Place Description here.
* @var mac_ax_disconnect_det_info::rsvd
* Please Place Description here.
* @var mac_ax_disconnect_det_info::check_period
* Please Place Description here.
* @var mac_ax_disconnect_det_info::try_pkt_count
* Please Place Description here.
* @var mac_ax_disconnect_det_info::tryok_bcnfail_count_limit
* Please Place Description here.
*/
struct mac_ax_disconnect_det_info {
u8 disconnect_detect_en: 1;
u8 tryok_bcnfail_count_en: 1;
u8 disconnect_en: 1;
u8 rsvd: 5;
u8 check_period;
u8 try_pkt_count;
u8 tryok_bcnfail_count_limit;
};
/**
* @enum mac_ax_enc_alg
*
* @brief mac_ax_enc_alg
*
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_NONE
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_WEP40
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_WEP104
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_TKIP
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_WAPI
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_GCMSMS4
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_CCMP
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_CCMP256
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_GCMP
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_GCMP256
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_BIP_CCMP128
* Please Place Description here.
* @var mac_ax_enc_alg::MAC_AX_RTW_ENC_MAX
* Please Place Description here.
*/
enum mac_ax_enc_alg {
MAC_AX_RTW_ENC_NONE = 0,
MAC_AX_RTW_ENC_WEP40 = 1,
MAC_AX_RTW_ENC_WEP104,
MAC_AX_RTW_ENC_TKIP,
MAC_AX_RTW_ENC_WAPI,
MAC_AX_RTW_ENC_GCMSMS4,
MAC_AX_RTW_ENC_CCMP,
MAC_AX_RTW_ENC_CCMP256,
MAC_AX_RTW_ENC_GCMP,
MAC_AX_RTW_ENC_GCMP256,
MAC_AX_RTW_ENC_BIP_CCMP128,
MAC_AX_RTW_ENC_MAX
};
/**
* @enum bip_sec_algo_type
*
* @brief bip_sec_algo_type
*
* @var bip_sec_algo_type::BIP_CMAC_128
* Please Place Description here.
* @var bip_sec_algo_type::BIP_CMAC_256
* Please Place Description here.
* @var bip_sec_algo_type::BIP_GMAC_128
* Please Place Description here.
* @var bip_sec_algo_type::BIP_GMAC_256
* Please Place Description here.
*/
enum bip_sec_algo_type {
BIP_CMAC_128 = 0,
BIP_CMAC_256 = 1,
BIP_GMAC_128 = 2,
BIP_GMAC_256 = 3
};
/**
* @struct mac_ax_wow_wake_info
* @brief mac_ax_wow_wake_info
*
* @var mac_ax_wow_wake_info::wow_en
* Please Place Description here.
* @var mac_ax_wow_wake_info::drop_all_pkt
* Please Place Description here.
* @var mac_ax_wow_wake_info::rx_parse_after_wake
* Please Place Description here.
* @var mac_ax_wow_wake_info::rsvd
* Please Place Description here.
* @var mac_ax_wow_wake_info::pairwise_sec_algo
* Please Place Description here.
* @var mac_ax_wow_wake_info::group_sec_algo
* Please Place Description here.
* @var mac_ax_wow_wake_info::remotectrl_info_content
* Please Place Description here.
* @var mac_ax_wow_wake_info::pattern_match_en
* Please Place Description here.
* @var mac_ax_wow_wake_info::magic_en
* Please Place Description here.
* @var mac_ax_wow_wake_info::hw_unicast_en
* Please Place Description here.
* @var mac_ax_wow_wake_info::fw_unicast_en
* Please Place Description here.
* @var mac_ax_wow_wake_info::deauth_wakeup
* Please Place Description here.
* @var mac_ax_wow_wake_info::rekey_wakeup
* Please Place Description here.
* @var mac_ax_wow_wake_info::eap_wakeup
* Please Place Description here.
* @var mac_ax_wow_wake_info::all_data_wakeup
* Please Place Description here.
*/
struct mac_ax_wow_wake_info {
u8 wow_en: 1;
u8 drop_all_pkt: 1;
u8 rx_parse_after_wake: 1;
u8 rsvd: 5;
enum mac_ax_enc_alg pairwise_sec_algo;
enum mac_ax_enc_alg group_sec_algo;
u32 remotectrl_info_content;
u8 pattern_match_en: 1;
u8 magic_en: 1;
u8 hw_unicast_en: 1;
u8 fw_unicast_en: 1;
u8 deauth_wakeup: 1;
u8 rekey_wakeup: 1;
u8 eap_wakeup: 1;
u8 all_data_wakeup: 1;
};
#define IV_LENGTH 8
/**
* @struct mac_ax_remotectrl_info_parm_
* @brief mac_ax_remotectrl_info_parm_
*
* @var mac_ax_remotectrl_info_parm_::ptktxiv
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::validcheck
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::symbolchecken
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::lastkeyid
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::rsvd
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::rxptkiv
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::rxgtkiv_0
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::rxgtkiv_1
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::rxgtkiv_2
* Please Place Description here.
* @var mac_ax_remotectrl_info_parm_::rxgtkiv_3
* Please Place Description here.
*/
struct mac_ax_remotectrl_info_parm_ {
u8 ptktxiv[IV_LENGTH];
/* value = 0xdd */
u8 validcheck;
/* bit0 : check ptk, bit1 : check gtk */
u8 symbolchecken;
/* the last gtk index used by driver */
u8 lastkeyid;
u8 rsvd[5];
/* unicast iv */
u8 rxptkiv[IV_LENGTH];
/* broadcast/mulicast iv, 4 gtk index */
u8 rxgtkiv_0[IV_LENGTH];
u8 rxgtkiv_1[IV_LENGTH];
u8 rxgtkiv_2[IV_LENGTH];
u8 rxgtkiv_3[IV_LENGTH];
};
/**
* @struct mac_ax_wake_ctrl_info
* @brief mac_ax_wake_ctrl_info
*
* @var mac_ax_wake_ctrl_info::pattern_match_en
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::magic_en
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::hw_unicast_en
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::fw_unicast_en
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::deauth_wakeup
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::rekey_wakeup
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::eap_wakeup
* Please Place Description here.
* @var mac_ax_wake_ctrl_info::all_data_wakeup
* Please Place Description here.
*/
struct mac_ax_wake_ctrl_info {
u8 pattern_match_en: 1;
u8 magic_en: 1;
u8 hw_unicast_en: 1;
u8 fw_unicast_en: 1;
u8 deauth_wakeup: 1;
u8 rekey_wakeup: 1;
u8 eap_wakeup: 1;
u8 all_data_wakeup: 1;
};
/**
* @struct mac_ax_gtk_ofld_info
* @brief mac_ax_gtk_ofld_info
*
* @var mac_ax_gtk_ofld_info::gtk_en
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::tkip_en
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::ieee80211w_en
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::pairwise_wakeup
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::bip_sec_algo
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::rsvd
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::gtk_rsp_id
* Please Place Description here.
* @var mac_ax_gtk_ofld_info::pmf_sa_query_id
* Please Place Description here.
*/
struct mac_ax_gtk_ofld_info {
u8 gtk_en: 1;
u8 tkip_en: 1;
u8 ieee80211w_en: 1;
u8 pairwise_wakeup: 1;
u8 bip_sec_algo: 2;
u8 rsvd: 2;
u8 gtk_rsp_id: 8;
u8 pmf_sa_query_id: 8;
u8 algo_akm_suit: 8;
};
#define AOAC_REPORT_VERSION 1
/**
* @struct mac_ax_aoac_report
* @brief mac_ax_aoac_report
*
* @var mac_ax_aoac_report::rpt_ver
* Please Place Description here.
* @var mac_ax_aoac_report::sec_type
* Please Place Description here.
* @var mac_ax_aoac_report::key_idx
* Please Place Description here.
* @var mac_ax_aoac_report::pattern_idx
* Please Place Description here.
* @var mac_ax_aoac_report::rekey_ok
* Please Place Description here.
* @var mac_ax_aoac_report::rsvd0
* Please Place Description here.
* @var mac_ax_aoac_report::rsvd1
* Please Place Description here.
* @var mac_ax_aoac_report::ptk_tx_iv
* Please Place Description here.
* @var mac_ax_aoac_report::eapol_key_replay_count
* Please Place Description here.
* @var mac_ax_aoac_report::gtk
* Please Place Description here.
* @var mac_ax_aoac_report::ptk_rx_iv
* Please Place Description here.
* @var mac_ax_aoac_report::gtk_rx_iv_0
* Please Place Description here.
* @var mac_ax_aoac_report::gtk_rx_iv_1
* Please Place Description here.
* @var mac_ax_aoac_report::gtk_rx_iv_2
* Please Place Description here.
* @var mac_ax_aoac_report::gtk_rx_iv_3
* Please Place Description here.
* @var mac_ax_aoac_report::igtk_key_id
* Please Place Description here.
* @var mac_ax_aoac_report::igtk_ipn
* Please Place Description here.
* @var mac_ax_aoac_report::igtk
* Please Place Description here.
*/
struct mac_ax_aoac_report {
u8 rpt_ver;
u8 sec_type;
u8 key_idx;
u8 pattern_idx;
u8 rekey_ok: 1;
u8 rsvd0: 7;
u8 rsvd1[3];
u8 ptk_tx_iv[IV_LENGTH];
u8 eapol_key_replay_count[8];
u8 gtk[32];
u8 ptk_rx_iv[IV_LENGTH];
u8 gtk_rx_iv_0[IV_LENGTH];
u8 gtk_rx_iv_1[IV_LENGTH];
u8 gtk_rx_iv_2[IV_LENGTH];
u8 gtk_rx_iv_3[IV_LENGTH];
u8 igtk_key_id[8];
u8 igtk_ipn[8];
u8 igtk[32];
};
#define EAPOL_KCK_LENGTH 32
#define EAPOL_KEK_LENGTH 32
#define TKIP_TK_LENGTH 16
#define TKIP_MIC_KEY_LENGTH 8
#define IGTK_KEY_ID_LENGTH 4
#define IGTK_PKT_NUM_LENGTH 8
#define IGTK_LENGTH 16
#define IGTK_OFFSET 4
union keytype {
u8 SKEY[32];
u32 LKEY[4];
};
/**
* @struct mac_ax_gtk_info_parm_
* @brief mac_ax_gtk_info_parm_
*
* @var mac_ax_gtk_info_parm_::kck
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::kek
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::tk1
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::txmickey
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::rxmickey
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::igtk_keyid
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::ipn
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::igtk
* Please Place Description here.
* @var mac_ax_gtk_info_parm_::sk
* Please Place Description here.
*/
struct mac_ax_gtk_info_parm_ {
/* eapol - key confirmation key (kck) */
u8 kck[EAPOL_KCK_LENGTH];
/* eapol - key encryption key (kek) */
u8 kek[EAPOL_KEK_LENGTH];
/* temporal key 1 (tk1) */
u8 tk1[TKIP_TK_LENGTH];
u8 txmickey[TKIP_MIC_KEY_LENGTH];
u8 rxmickey[TKIP_MIC_KEY_LENGTH];
u8 igtk_keyid[IGTK_KEY_ID_LENGTH];
u8 ipn[IGTK_PKT_NUM_LENGTH];
union keytype igtk[2];
union keytype sk[1];
};
/**
* @struct mac_ax_arp_ofld_info
* @brief mac_ax_arp_ofld_info
*
* @var mac_ax_arp_ofld_info::arp_en
* Please Place Description here.
* @var mac_ax_arp_ofld_info::arp_action
* Please Place Description here.
* @var mac_ax_arp_ofld_info::rsvd
* Please Place Description here.
* @var mac_ax_arp_ofld_info::arp_rsp_id
* Please Place Description here.
*/
struct mac_ax_arp_ofld_info {
u8 arp_en: 1;
u8 arp_action: 1;
u8 rsvd: 6;
u8 arp_rsp_id: 8;
};
/**
* @struct mac_ax_ndp_ofld_info
* @brief mac_ax_ndp_ofld_info
*
* @var mac_ax_ndp_ofld_info::ndp_en
* Please Place Description here.
* @var mac_ax_ndp_ofld_info::rsvd
* Please Place Description here.
* @var mac_ax_ndp_ofld_info::na_id
* Please Place Description here.
*/
struct mac_ax_ndp_ofld_info {
u8 ndp_en: 1;
u8 rsvd: 7;
u8 na_id: 8;
};
#define MAC_ADDRESS_LENGTH 6
#define IPV6_ADDRESS_LENGTH 16
/**
* @struct mac_ax_ndp_info_parm_
* @brief mac_ax_ndp_info_parm_
*
* @var mac_ax_ndp_info_parm_::enable
* Please Place Description here.
* @var mac_ax_ndp_info_parm_::checkremoveip
* Please Place Description here.
* @var mac_ax_ndp_info_parm_::rsvd
* Please Place Description here.
* @var mac_ax_ndp_info_parm_::numberoftargetip
* Please Place Description here.
* @var mac_ax_ndp_info_parm_::targetlinkaddress
* Please Place Description here.
* @var mac_ax_ndp_info_parm_::remoteipv6address
* Please Place Description here.
* @var mac_ax_ndp_info_parm_::targetip
* Please Place Description here.
*/
struct mac_ax_ndp_info_parm_ {
u8 enable: 1;
/* need to check sender ip or not */
u8 checkremoveip: 1;
/* need to check sender ip or not */
u8 rsvd: 6;
/* number of check ip which na query ip */
u8 numberoftargetip;
/* maybe support change mac address !! */
u8 targetlinkaddress[MAC_ADDRESS_LENGTH];
/* just respond ip */
u8 remoteipv6address[IPV6_ADDRESS_LENGTH];
/* target ip */
u8 targetip[2][IPV6_ADDRESS_LENGTH];
};
/**
* @struct mac_ax_realwow_info
* @brief mac_ax_realwow_info
*
* @var mac_ax_realwow_info::realwow_en
* Please Place Description here.
* @var mac_ax_realwow_info::auto_wakeup
* Please Place Description here.
* @var mac_ax_realwow_info::rsvd0
* Please Place Description here.
* @var mac_ax_realwow_info::keepalive_id
* Please Place Description here.
* @var mac_ax_realwow_info::wakeup_pattern_id
* Please Place Description here.
* @var mac_ax_realwow_info::ack_pattern_id
* Please Place Description here.
*/
struct mac_ax_realwow_info {
u8 realwow_en: 1;
u8 auto_wakeup: 1;
u8 rsvd0: 6;
u8 keepalive_id: 8;
u8 wakeup_pattern_id: 8;
u8 ack_pattern_id: 8;
};
/**
* @struct mac_ax_realwowv2_info_parm_
* @brief mac_ax_realwowv2_info_parm_
*
* @var mac_ax_realwowv2_info_parm_::interval
* Please Place Description here.
* @var mac_ax_realwowv2_info_parm_::kapktsize
* Please Place Description here.
* @var mac_ax_realwowv2_info_parm_::acklostlimit
* Please Place Description here.
* @var mac_ax_realwowv2_info_parm_::ackpatternsize
* Please Place Description here.
* @var mac_ax_realwowv2_info_parm_::wakeuppatternsize
* Please Place Description here.
* @var mac_ax_realwowv2_info_parm_::rsvd
* Please Place Description here.
* @var mac_ax_realwowv2_info_parm_::wakeupsecnum
* Please Place Description here.
*/
struct mac_ax_realwowv2_info_parm_ {
u16 interval; /*unit : 1 ms */
u16 kapktsize;
u16 acklostlimit;
u16 ackpatternsize;
u16 wakeuppatternsize;
u16 rsvd;
u32 wakeupsecnum;
};
/**
* @struct mac_ax_nlo_info
* @brief mac_ax_nlo_info
*
* @var mac_ax_nlo_info::nlo_en
* Please Place Description here.
* @var mac_ax_nlo_info::nlo_32k_en
* Please Place Description here.
* @var mac_ax_nlo_info::ignore_cipher_type
* Please Place Description here.
* @var mac_ax_nlo_info::rsvd
* Please Place Description here.
*/
struct mac_ax_nlo_info {
u8 nlo_en: 1;
u8 nlo_32k_en: 1;
u8 ignore_cipher_type: 1;
u8 rsvd: 5;
};
#define MAX_SUPPORT_NL_NUM 16
#define MAX_PROBE_REQ_NUM 8
#define SSID_MAX_LEN 32
/**
* @struct mac_ax_nlo_networklist_parm_
* @brief mac_ax_nlo_networklist_parm_
*
* @var mac_ax_nlo_networklist_parm_::numofentries
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::numofhiddenap
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::rsvd
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::patterncheck
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::rsvd1
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::rsvd2
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::ssidlen
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::chipertype
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::rsvd3
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::locprobereq
* Please Place Description here.
* @var mac_ax_nlo_networklist_parm_::ssid
* Please Place Description here.
*/
struct mac_ax_nlo_networklist_parm_ {
u8 numofentries;
u8 numofhiddenap;
u8 rsvd[2];
u32 patterncheck;
u32 rsvd1;
u32 rsvd2;
u8 ssidlen[MAX_SUPPORT_NL_NUM];
u8 chipertype[MAX_SUPPORT_NL_NUM];
u8 rsvd3[MAX_SUPPORT_NL_NUM];
u8 locprobereq[MAX_PROBE_REQ_NUM];
u8 ssid[MAX_SUPPORT_NL_NUM][SSID_MAX_LEN];
};
/**
* @struct mac_ax_negative_pattern_info
* @brief mac_ax_negative_pattern_info
*
* @var mac_ax_negative_pattern_info::negative_pattern_en
* Please Place Description here.
* @var mac_ax_negative_pattern_info::rsvd
* Please Place Description here.
* @var mac_ax_negative_pattern_info::pattern_count
* Please Place Description here.
*/
struct mac_ax_negative_pattern_info {
u8 negative_pattern_en: 1;
u8 rsvd: 3;
u8 pattern_count: 4;
};
/**
* @struct mac_ax_dev2hst_gpio_info
* @brief mac_ax_dev2hst_gpio_info
*
* @var mac_ax_dev2hst_gpio_info::dev2hst_gpio_en
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::disable_inband
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_output_input
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_active
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::toggle_pulse
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::data_pin_wakeup
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_nonstop
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_time_unit
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_num
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_dura
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_period
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_count
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::rsvd0
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::customer_id
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::rsvd1
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_en_a
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_duration_unit_a
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_nonstop_a
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::rsvd2
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::special_reason_a
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_duration_a
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_count_a
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_en_b
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_duration_unit_b
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_nonstop_b
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::rsvd3
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::special_reason_b
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_duration_b
* Please Place Description here.
* @var mac_ax_dev2hst_gpio_info::gpio_pulse_count_b
* Please Place Description here.
*/
struct mac_ax_dev2hst_gpio_info {
/* dword0 */
u32 dev2hst_gpio_en:1;
u32 disable_inband:1;
u32 gpio_output_input:1;
u32 gpio_active:1;
u32 toggle_pulse:1;
u32 data_pin_wakeup:1;
u32 gpio_pulse_nonstop:1;
u32 gpio_time_unit:1;
u32 gpio_num:8;
u32 gpio_pulse_dura:8;
u32 gpio_pulse_period:8;
/* dword1 */
u32 gpio_pulse_count:8;
u32 rsvd0:24;
/* dword2 */
u32 customer_id:8;
u32 rsvd1:24;
/* dword3 */
u32 rsn_a_en:1;
u32 rsn_a_toggle_pulse:1;
u32 rsn_a_pulse_nonstop:1;
u32 rsn_a_time_unit:1;
u32 rsvd2:28;
/* dword4 */
u32 rsn_a:8;
u32 rsn_a_pulse_duration:8;
u32 rsn_a_pulse_period:8;
u32 rsn_a_pulse_count:8;
/* dword5 */
u32 rsn_b_en:1;
u32 rsn_b_toggle_pulse:1;
u32 rsn_b_pulse_nonstop:1;
u32 rsn_b_time_unit:1;
u32 rsvd3:28;
/* dword6 */
u32 rsn_b:8;
u32 rsn_b_pulse_duration:8;
u32 rsn_b_pulse_period:8;
u32 rsn_b_pulse_count:8;
/* dword7 */
u32 gpio_pulse_en_a:8; /*deprecated*/
u32 gpio_duration_unit_a:8; /*deprecated*/
u32 gpio_pulse_nonstop_a:8; /*deprecated*/
u32 special_reason_a:8; /*deprecated*/
u32 gpio_duration_a:8; /*deprecated*/
u32 gpio_pulse_count_a:8; /*deprecated*/
};
/**
* @struct mac_ax_uphy_ctrl_info
* @brief mac_ax_uphy_ctrl_info
*
* @var mac_ax_uphy_ctrl_info::disable_uphy
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::handshake_mode
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::rsvd0
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::rise_hst2dev_dis_uphy
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::uphy_dis_delay_unit
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::pdn_as_uphy_dis
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::pdn_to_enable_uphy
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::rsvd1
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::hst2dev_gpio_num
* Please Place Description here.
* @var mac_ax_uphy_ctrl_info::uphy_dis_delay_count
* Please Place Description here.
*/
struct mac_ax_uphy_ctrl_info {
u8 disable_uphy: 1;
u8 handshake_mode: 3;
u8 rsvd0: 4;
u8 rise_hst2dev_dis_uphy: 1;
u8 uphy_dis_delay_unit: 1;
u8 pdn_as_uphy_dis: 1;
u8 pdn_to_enable_uphy: 1;
u8 rsvd1: 4;
u8 hst2dev_gpio_num: 8;
u8 uphy_dis_delay_count: 8;
};
/**
* @struct mac_ax_wowcam_upd_info
* @brief mac_ax_wowcam_upd_info
*
* @var mac_ax_wowcam_upd_info::r_w
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::idx
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::rsvd0
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::wkfm1
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::wkfm2
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::wkfm3
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::wkfm4
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::crc
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::rsvd1
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::negative_pattern_match
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::skip_mac_hdr
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::uc
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::mc
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::bc
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::rsvd2
* Please Place Description here.
* @var mac_ax_wowcam_upd_info::valid
* Please Place Description here.
*/
struct mac_ax_wowcam_upd_info {
u8 r_w: 1;
u8 idx: 7;
u8 rsvd0[3];
u32 wkfm1: 32;
u32 wkfm2: 32;
u32 wkfm3: 32;
u32 wkfm4: 32;
u16 crc: 16;
u8 rsvd1: 6;
u8 negative_pattern_match: 1;
u8 skip_mac_hdr: 1;
u8 uc: 1;
u8 mc: 1;
u8 bc: 1;
u8 rsvd2: 4;
u8 valid: 1;
};
/*--------------------Define SET/GET HW VALUE struct -------------------------*/
/**
* @struct mac_ax_sdio_info
* @brief mac_ax_sdio_info
*
* @var mac_ax_sdio_info::sdio_4byte
* Please Place Description here.
* @var mac_ax_sdio_info::tx_mode
* Please Place Description here.
* @var mac_ax_sdio_info::spec_ver
* Please Place Description here.
* @var mac_ax_sdio_info::block_size
* Please Place Description here.
* @var mac_ax_sdio_info::tx_seq
* Please Place Description here.
* @var mac_ax_sdio_info::tx_align_size
* Please Place Description here.
* @var mac_ax_sdio_info::rpwm_bak
* Please Place Description here.
*/
struct mac_ax_sdio_info {
enum mac_ax_sdio_4byte_mode sdio_4byte;
enum mac_ax_sdio_tx_mode tx_mode;
enum mac_ax_sdio_spec_ver spec_ver;
enum mac_ax_sdio_opn_mode opn_mode;
u16 block_size;
u8 tx_seq;
u16 tx_align_size;
u32 rpwm_bak;
};
/**
* @struct mac_ax_sdio_txagg_cfg
* @brief mac_ax_sdio_txagg_cfg
*
* @var mac_ax_sdio_txagg_cfg::en
* Please Place Description here.
* @var mac_ax_sdio_txagg_cfg::align_size
* Please Place Description here.
*/
struct mac_ax_sdio_txagg_cfg {
u8 en;
u16 align_size;
};
/**
* @struct mac_ax_usb_info
* @brief mac_ax_usb_info
*
* @var mac_ax_usb_info::ep5
* Please Place Description here.
* @var mac_ax_usb_info::ep6
* Please Place Description here.
* @var mac_ax_usb_info::ep10
* Please Place Description here.
* @var mac_ax_usb_info::ep11
* Please Place Description here.
* @var mac_ax_usb_info::ep12
* Please Place Description here.
* @var mac_ax_usb_info::max_bulkout_wd_num
* Please Place Description here.
* @var mac_ax_usb_info::usb_mode
* Please Place Description here.
*/
struct mac_ax_usb_info {
u8 ep5;
u8 ep6;
u8 ep10;
u8 ep11;
u8 ep12;
u8 max_bulkout_wd_num;
enum mac_ax_use_mode usb_mode;
};
struct mac_ax_flash_info {
u8 read_done;
u8 reading;
u32 read_addr;
u8 write_done;
u8 writing;
u32 write_addr;
u8 erasing;
u8 erase_done;
u32 erase_addr;
u8 *buf_addr;
mac_ax_mutex lock;
};
/**
* @struct mac_ax_fw_dbgcmd
* @brief mac_ax_fw_dbgcmd
*
* @var mac_ax_fw_dbgcmd::buf
* Please Place Description here.
* @var mac_ax_fw_dbgcmd::out_len
* Please Place Description here.
* @var mac_ax_fw_dbgcmd::used
* Please Place Description here.
* @var mac_ax_fw_dbgcmd::cmd_idle
* Please Place Description here.
* @var mac_ax_fw_dbgcmd::lock
* Please Place Description here.
*/
struct mac_ax_fw_dbgcmd {
char *buf;
u32 out_len;
u32 used;
u32 cmd_idle;
mac_ax_mutex lock;
};
/**
* @struct mac_ax_aval_page_cfg
* @brief mac_ax_aval_page_cfg
*
* @var mac_ax_aval_page_cfg::thold_wd
* Please Place Description here.
* @var mac_ax_aval_page_cfg::thold_wp
* Please Place Description here.
* @var mac_ax_aval_page_cfg::ch_dma
* Please Place Description here.
* @var mac_ax_aval_page_cfg::en
* Please Place Description here.
*/
struct mac_ax_aval_page_cfg {
u32 thold_wd;
u32 thold_wp;
u8 ch_dma;
u8 en;
};
/**
* @struct mac_ax_rx_agg_cfg
* @brief mac_ax_rx_agg_cfg
*
* @var mac_ax_rx_agg_cfg::mode
* Please Place Description here.
* @var mac_ax_rx_agg_cfg::thold
* Please Place Description here.
*/
struct mac_ax_rx_agg_cfg {
enum mac_ax_rx_agg_mode mode;
struct mac_ax_rx_agg_thold thold;
};
/**
* @struct mac_ax_usr_tx_rpt_cfg
* @brief mac_ax_usr_tx_rpt_cfg
*
* @var mac_ax_usr_tx_rpt_cfg::mode
* sel report mode
* @var mac_ax_usr_tx_rpt_cfg::rpt_start
* flag of first packet
* @var mac_ax_usr_tx_rpt_cfg::macid
* target macid
* @var mac_ax_usr_tx_rpt_cfg::rpt_period_us
* period of report, unit:us
*/
struct mac_ax_usr_tx_rpt_cfg {
enum mac_ax_usr_tx_rpt_mode mode;
u8 rpt_start;
u8 macid;
u8 band;
u8 port;
u32 rpt_period_us;
};
/**
* @struct mac_ax_ofld_cfg
* @brief disable ofld feature
*
* @var mac_ax_ofld_cfg::usr_edca_dis
* 1: disable; 0:enable
*/
struct mac_ax_ofld_cfg {
enum mac_ax_ofld_mode mode;
u8 usr_txop_be;
u16 usr_txop_be_val;
};
/**
* @struct mac_ax_ac_edca_param
* @brief mac_ax_ac_edca_param
*
* @var mac_ax_ac_edca_param::txop_32us
* Please Place Description here.
* @var mac_ax_ac_edca_param::ecw_max
* Please Place Description here.
* @var mac_ax_ac_edca_param::ecw_min
* Please Place Description here.
* @var mac_ax_ac_edca_param::aifs_us
* Please Place Description here.
*/
struct mac_ax_ac_edca_param {
u16 txop_32us;
u8 ecw_max;
u8 ecw_min;
u8 aifs_us;
};
/**
* @struct mac_ax_usr_edca_param
* @brief mac_ax_usr_edca_param
*
* @var mac_ax_usr_edca_param::idx
* Please Place Description here.
* @var mac_ax_usr_edca_param::enable
* Please Place Description here.
* @var mac_ax_usr_edca_param::band
* Please Place Description here.
* @var mac_ax_usr_edca_param::wmm
* Please Place Description here.
* @var mac_ax_usr_edca_param::ac
* Please Place Description here.
* @var mac_ax_usr_edca_param::aggressive
* Please Place Description here.
* @var mac_ax_usr_edca_param::moderate
* Please Place Description here.
*/
struct mac_ax_usr_edca_param {
enum mac_ax_cmac_usr_edca_idx idx;
u8 enable;
u8 band;
enum mac_ax_cmac_wmm_sel wmm;
enum mac_ax_cmac_ac_sel ac;
struct mac_ax_ac_edca_param aggressive;
struct mac_ax_ac_edca_param moderate;
};
/**
* @struct mac_ax_edca_param
* @brief mac_ax_edca_param
*
* @var mac_ax_edca_param::band
* Please Place Description here.
* @var mac_ax_edca_param::path
* Please Place Description here.
* @var mac_ax_edca_param::txop_32us
* Please Place Description here.
* @var mac_ax_edca_param::ecw_max
* Please Place Description here.
* @var mac_ax_edca_param::ecw_min
* Please Place Description here.
* @var mac_ax_edca_param::aifs_us
* Please Place Description here.
*/
struct mac_ax_edca_param {
u8 band;
enum mac_ax_cmac_path_sel path;
u16 txop_32us;
u8 ecw_max;
u8 ecw_min;
u8 aifs_us;
};
/**
* @struct mac_ax_muedca_param
* @brief mac_ax_muedca_param
*
* @var mac_ax_muedca_param::band
* Please Place Description here.
* @var mac_ax_muedca_param::ac
* Please Place Description here.
* @var mac_ax_muedca_param::muedca_timer_32us
* Please Place Description here.
* @var mac_ax_muedca_param::ecw_max
* Please Place Description here.
* @var mac_ax_muedca_param::ecw_min
* Please Place Description here.
* @var mac_ax_muedca_param::aifs_us
* Please Place Description here.
*/
struct mac_ax_muedca_param {
u8 band;
enum mac_ax_cmac_ac_sel ac;
u16 muedca_timer_32us;
u8 ecw_max;
u8 ecw_min;
u8 aifs_us;
};
/**
* @struct mac_ax_muedca_timer
* @brief mac_ax_muedca_timer
*
* @var mac_ax_muedca_timer::band
* Please Place Description here.
* @var mac_ax_muedca_timer::ac
* Please Place Description here.
* @var mac_ax_muedca_timer::muedca_timer_32us
* Please Place Description here.
*/
struct mac_ax_muedca_timer {
u8 band;
enum mac_ax_cmac_ac_sel ac;
u16 muedca_timer_32us;
};
/**
* @struct mac_ax_muedca_cfg
* @brief mac_ax_muedca_cfg
*
* @var mac_ax_muedca_cfg::band
* Please Place Description here.
* @var mac_ax_muedca_cfg::wmm_sel
* Please Place Description here.
* @var mac_ax_muedca_cfg::countdown_en
* Please Place Description here.
* @var mac_ax_muedca_cfg::tb_update_en
* Please Place Description here.
*/
struct mac_ax_muedca_cfg {
u8 band;
enum mac_ax_cmac_wmm_sel wmm_sel;
u8 countdown_en;
u8 tb_update_en;
};
/**
* @struct mac_ax_sch_tx_en_cfg
* @brief mac_ax_sch_tx_en_cfg
*
* @var mac_ax_sch_tx_en_cfg::band
* Please Place Description here.
* @var mac_ax_sch_tx_en_cfg::tx_en
* Please Place Description here.
* @var mac_ax_sch_tx_en_cfg::tx_en_mask
* Please Place Description here.
*/
struct mac_ax_sch_tx_en_cfg {
u8 band;
struct mac_ax_sch_tx_en tx_en;
struct mac_ax_sch_tx_en tx_en_mask;
};
struct mac_ax_tx_idle_poll_cfg {
u8 band;
enum mac_ax_tx_idle_poll_sel sel;
};
/**
* @struct mac_ax_lifetime_cfg
* @brief mac_ax_lifetime_cfg
*
* @var mac_ax_lifetime_cfg::band
* Please Place Description here.
* @var mac_ax_lifetime_cfg::en
* Please Place Description here.
* @var mac_ax_lifetime_cfg::val
* Please Place Description here.
*/
struct mac_ax_lifetime_cfg {
u8 band;
struct mac_ax_lifetime_en en;
struct mac_ax_lifetime_val val;
};
/**
* @struct mac_ax_tb_ppdu_ctrl
* @brief mac_ax_tb_ppdu_ctrl
*
* @var mac_ax_tb_ppdu_ctrl::band
* Please Place Description here.
* @var mac_ax_tb_ppdu_ctrl::pri_ac
* Please Place Description here.
* @var mac_ax_tb_ppdu_ctrl::be_dis
* Please Place Description here.
* @var mac_ax_tb_ppdu_ctrl::bk_dis
* Please Place Description here.
* @var mac_ax_tb_ppdu_ctrl::vi_dis
* Please Place Description here.
* @var mac_ax_tb_ppdu_ctrl::vo_dis
* Please Place Description here.
*/
struct mac_ax_tb_ppdu_ctrl {
u8 band;
enum mac_ax_cmac_ac_sel pri_ac;
u8 be_dis;
u8 bk_dis;
u8 vi_dis;
u8 vo_dis;
};
/**
* @struct macid_tx_bak
* @brief macid_tx_bak
*
* @var macid_tx_bak::sch_bak
* Please Place Description here.
* @var macid_tx_bak::ac_dis_bak
* Please Place Description here.
*/
struct macid_tx_bak {
struct mac_ax_sch_tx_en_cfg sch_bak;
struct mac_ax_tb_ppdu_ctrl ac_dis_bak;
};
/**
* @struct mac_ax_edcca_param
* @brief mac_ax_edcca_param
*
* @var mac_ax_edcca_param::band
* Please Place Description here.
* @var mac_ax_edcca_param::tb_check_en
* Please Place Description here.
* @var mac_ax_edcca_param::sifs_check_en
* Please Place Description here.
* @var mac_ax_edcca_param::ctn_check_en
* Please Place Description here.
* @var mac_ax_edcca_param::rsvd
* Please Place Description here.
* @var mac_ax_edcca_param::sel
* Please Place Description here.
*/
struct mac_ax_edcca_param {
u8 band:1;
u8 tb_check_en:1;
u8 sifs_check_en:1;
u8 ctn_check_en:1;
u8 rsvd:4;
enum mac_ax_edcca_sel sel;
};
/**
* @struct mac_ax_host_rpr_cfg
* @brief mac_ax_host_rpr_cfg
*
* @var mac_ax_host_rpr_cfg::agg
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::tmr
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::agg_def
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::tmr_def
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::rsvd
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::txok_en
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::rty_lmt_en
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::lft_drop_en
* Please Place Description here.
* @var mac_ax_host_rpr_cfg::macid_drop_en
* Please Place Description here.
*/
struct mac_ax_host_rpr_cfg {
u8 agg;
u8 tmr;
u8 agg_def:1;
u8 tmr_def:1;
u8 rsvd:5;
enum mac_ax_func_sw txok_en;
enum mac_ax_func_sw rty_lmt_en;
enum mac_ax_func_sw lft_drop_en;
enum mac_ax_func_sw macid_drop_en;
};
/**
* @struct mac_ax_macid_pause_cfg
* @brief mac_ax_macid_pause_cfg
*
* @var mac_ax_macid_pause_cfg::macid
* Please Place Description here.
* @var mac_ax_macid_pause_cfg::pause
* Please Place Description here.
*/
struct mac_ax_macid_pause_cfg {
u8 macid;
u8 pause;
};
/**
* @struct mac_ax_macid_pause_grp
* @brief mac_ax_macid_pause_grp
*
* @var mac_ax_macid_pause_grp::pause_grp
* Please Place Description here.
* @var mac_ax_macid_pause_grp::mask_grp
* Please Place Description here.
*/
struct mac_ax_macid_pause_grp {
u32 pause_grp[4];
u32 mask_grp[4];
};
/**
* @struct mac_ax_ampdu_cfg
* @brief mac_ax_ampdu_cfg
*
* @var mac_ax_ampdu_cfg::band
* Please Place Description here.
* @var mac_ax_ampdu_cfg::wdbk_mode
* Please Place Description here.
* @var mac_ax_ampdu_cfg::rty_bk_mode
* Please Place Description here.
* @var mac_ax_ampdu_cfg::max_agg_num
* Please Place Description here.
* @var mac_ax_ampdu_cfg::max_agg_time_32us
* Please Place Description here.
*/
struct mac_ax_ampdu_cfg {
u8 band;
enum mac_ax_wdbk_mode wdbk_mode;
enum mac_ax_rty_bk_mode rty_bk_mode;
u16 max_agg_num;
u8 max_agg_time_32us;
};
/**
* @struct mac_ax_ch_stat_cnt
* @brief mac_ax_ch_stat_cnt
*
* @var mac_ax_ch_stat_cnt::band
* Please Place Description here.
* @var mac_ax_ch_stat_cnt::busy_cnt
* Please Place Description here.
* @var mac_ax_ch_stat_cnt::idle_cnt
* Please Place Description here.
*/
struct mac_ax_ch_stat_cnt {
u8 band;
u32 busy_cnt;
u32 idle_cnt;
};
/**
* @struct mac_ax_ch_busy_cnt_cfg
* @brief mac_ax_ch_busy_cnt_cfg
*
* @var mac_ax_ch_busy_cnt_cfg::band
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_cfg::cnt_ctrl
* Please Place Description here.
* @var mac_ax_ch_busy_cnt_cfg::ref
* Please Place Description here.
*/
struct mac_ax_ch_busy_cnt_cfg {
u8 band;
enum mac_ax_ch_busy_cnt_ctrl cnt_ctrl;
struct mac_ax_ch_busy_cnt_ref ref;
};
/**
* @struct mac_ax_ss_wmm_tbl_ctrl
* @brief mac_ax_ss_wmm_tbl_ctrl
*
* @var mac_ax_ss_wmm_tbl_ctrl::wmm
* Please Place Description here.
* @var mac_ax_ss_wmm_tbl_ctrl::wmm_mapping
* Please Place Description here.
*/
struct mac_ax_ss_wmm_tbl_ctrl {
u8 wmm;
enum mac_ax_ss_wmm_tbl wmm_mapping;
};
/**
* @struct mac_ax_bt_block_tx
* @brief mac_ax_bt_block_tx
*
* @var mac_ax_bt_block_tx::band
* Please Place Description here.
* @var mac_ax_bt_block_tx::en
* Please Place Description here.
*/
struct mac_ax_block_tx {
u8 band;
u8 en;
};
/**
* @struct mac_ax_gt3_cfg
* @brief mac_ax_gt3_cfg
*
* @var mac_ax_gt3_cfg::count_en
* Please Place Description here.
* @var mac_ax_gt3_cfg::mode
* Please Place Description here.
* @var mac_ax_gt3_cfg::gt3_en
* Please Place Description here.
* @var mac_ax_gt3_cfg::sort_en
* Please Place Description here.
* @var mac_ax_gt3_cfg::timeout
* Please Place Description here.
*/
struct mac_ax_gt3_cfg {
u32 count_en:1;
u32 mode:1; /*0 = counter mode; 1 = timer mode"*/
u32 gt3_en:1; /*HW clear when count down to zero in counter mode."*/
u32 sort_en:1;
u32 timeout:28;
};
/**
* @struct mac_ax_rty_lmt
* @brief mac_ax_rty_lmt
*
* @var mac_ax_rty_lmt::tx_cnt
* Please Place Description here.
* @var mac_ax_rty_lmt::macid
* Please Place Description here.
*/
struct mac_ax_rty_lmt {
u32 tx_cnt;
u8 macid;
};
/**
* @struct mac_ax_cctl_rty_lmt_cfg
* @brief mac_ax_cctl_rty_lmt_cfg
*
* @var mac_ax_cctl_rty_lmt_cfg::macid
* Please Place Description here.
* @var mac_ax_cctl_rty_lmt_cfg::data_lmt_sel
* Please Place Description here.
* @var mac_ax_cctl_rty_lmt_cfg::data_lmt_val
* Please Place Description here.
* @var mac_ax_cctl_rty_lmt_cfg::rsvd0
* Please Place Description here.
* @var mac_ax_cctl_rty_lmt_cfg::rts_lmt_sel
* Please Place Description here.
* @var mac_ax_cctl_rty_lmt_cfg::rts_lmt_val
* Please Place Description here.
* @var mac_ax_cctl_rty_lmt_cfg::rsvd1
* Please Place Description here.
*/
struct mac_ax_cctl_rty_lmt_cfg {
u8 macid;
u8 data_lmt_sel:1;
u8 data_lmt_val:6;
u8 rsvd0:1;
u8 rts_lmt_sel:1;
u8 rts_lmt_val:4;
u8 rsvd1:3;
};
/**
* @struct mac_ax_cr_rty_lmt_cfg
* @brief mac_ax_cr_rty_lmt_cfg
*
* @var mac_ax_cr_rty_lmt_cfg::long_tx_cnt_lmt
* Please Place Description here.
* @var mac_ax_cr_rty_lmt_cfg::short_tx_cnt_lmt
* Please Place Description here.
* @var mac_ax_cr_rty_lmt_cfg::band
* Please Place Description here.
*/
struct mac_ax_cr_rty_lmt_cfg {
u16 long_tx_cnt_lmt:6; /*CR: long rty*/
u16 short_tx_cnt_lmt:6; /*CR: short rty*/
enum mac_ax_band band;
};
/**
* @struct mac_ax_rrsr_cfg
* @brief mac_ax_rrsr_cfg
*
* @var mac_ax_rrsr_cfg::rrsr_rate_en
* Please Place Description here.
* @var mac_ax_rrsr_cfg::rsc
* Please Place Description here.
* @var mac_ax_rrsr_cfg::doppler_en
* Please Place Description here.
* @var mac_ax_rrsr_cfg::dcm_en
* Please Place Description here.
* @var mac_ax_rrsr_cfg::ref_rate_sel
* Please Place Description here.
* @var mac_ax_rrsr_cfg::ref_rate
* Please Place Description here.
* @var mac_ax_rrsr_cfg::cck_cfg
* Please Place Description here.
* @var mac_ax_rrsr_cfg::rsvd
* Please Place Description here.
* @var mac_ax_rrsr_cfg::ofdm_cfg
* Please Place Description here.
* @var mac_ax_rrsr_cfg::ht_cfg
* Please Place Description here.
* @var mac_ax_rrsr_cfg::vht_cfg
* Please Place Description here.
* @var mac_ax_rrsr_cfg::he_cfg
* Please Place Description here.
*/
struct mac_ax_rrsr_cfg {
u32 rrsr_rate_en:4;
u32 rsc:2;
u32 doppler_en:1;
u32 dcm_en:1;
u32 ref_rate_sel:1;
u32 ref_rate:9;
u32 cck_cfg:4;
u32 rsvd:10;
u32 ofdm_cfg:8;
u32 ht_cfg:8;
u32 vht_cfg:8;
u32 he_cfg:8;
u8 band;
};
/**
* @struct mac_ax_cts_rrsr_cfg
* @brief mac_ax_cts_rrsr_cfg
*
* @var mac_ax_rrsr_cfg::cts_rrsr_rsc
* Please Place Description here.
* @var mac_ax_rrsr_cfg::cts_rrsr_opt
* Please Place Description here.
* @var mac_ax_rrsr_cfg::cts_rrsr_cck_cfg
* Please Place Description here.
* @var mac_ax_rrsr_cfg::cts_rrsr_ofdm_cfg
* Please Place Description here.
* @var mac_ax_rrsr_cfg::rsvd
* Please Place Description here.
*/
struct mac_ax_cts_rrsr_cfg {
u32 cts_rrsr_rsc:2;
u32 cts_rrsr_opt:1;
u32 cts_rrsr_cck_cfg:4;
u32 cts_rrsr_ofdm_cfg:8;
u32 rsvd:17;
u8 band;
};
/**
* @struct mac_ax_ss_quota_mode_ctrl
* @brief mac_ax_ss_quota_mode_ctrl
*
* @var mac_ax_ss_quota_mode_ctrl::wmm
* Please Place Description here.
* @var mac_ax_ss_quota_mode_ctrl::mode
* Please Place Description here.
*/
struct mac_ax_ss_quota_mode_ctrl {
enum mac_ax_ss_wmm wmm;
enum mac_ax_ss_quota_mode mode;
};
/**
* @struct mac_ax_ss_quota_setting
* @brief mac_ax_ss_quota_setting
*
* @var mac_ax_ss_quota_setting::macid
* Please Place Description here.
* @var mac_ax_ss_quota_setting::ac_type
* Please Place Description here.
* @var mac_ax_ss_quota_setting::val
* Please Place Description here.
* @var mac_ax_ss_quota_setting::ul_dl
* Please Place Description here.
*/
struct mac_ax_ss_quota_setting {
u8 macid;
u8 ac_type;
u8 val;
enum mac_ax_issue_uldl_type ul_dl;
};
/**
* @struct mac_ax_bt_polt_cnt
* @brief mac_ax_bt_polt_cnt
*
* @var mac_ax_bt_polt_cnt::band
* Please Place Description here.
* @var mac_ax_bt_polt_cnt::cnt
* Please Place Description here.
*/
struct mac_ax_bt_polt_cnt {
u8 band;
u16 cnt;
};
/**
* @struct mac_ax_prebkf_setting
* @brief mac_ax_prebkf_setting
*
* @var mac_ax_prebkf_setting::band
* Please Place Description here.
* @var mac_ax_prebkf_setting::val
* Please Place Description here.
*/
struct mac_ax_prebkf_setting {
u8 band;
u8 val;
};
/*--------------------Define SRAM FIFO ---------------------------------------*/
/**
* @struct mac_ax_bacam_info
* @brief mac_ax_bacam_info
*
* @var mac_ax_bacam_info::valid
* Please Place Description here.
* @var mac_ax_bacam_info::init_req
* Please Place Description here.
* @var mac_ax_bacam_info::entry_idx
* Tha var is only for 8852A.
* @var mac_ax_bacam_info::tid
* Please Place Description here.
* @var mac_ax_bacam_info::macid
* Please Place Description here.
* @var mac_ax_bacam_info::bmap_size
* Please Place Description here.
* @var mac_ax_bacam_info::ssn
* Please Place Description here.
* @var mac_ax_bacam_info::uid_value
* The var is for 8852C.
* @var mac_ax_bacam_info::std_entry_en
* The var is for 8852C.
* @var mac_ax_bacam_info::band_sel
* The var is for 8852C.
* @var mac_ax_bacam_info::entry_idx_v1
* The var is for 8852C.
*/
struct mac_ax_bacam_info {
u32 valid: 1;
u32 init_req: 1;
u32 entry_idx: 2;
u32 tid: 4;
u32 macid: 8;
u32 bmap_size: 4;
u32 ssn: 12;
u32 uid_value: 8;
u32 std_entry_en: 1;
u32 band_sel: 1;
u32 rsvd: 18;
u32 entry_idx_v1: 4;
};
/**
* @struct mac_ax_shcut_mhdr
* @brief mac_ax_shcut_mhdr
*
* @var mac_ax_shcut_mhdr::mac_header_length
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword0
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword1
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword2
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword3
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword4
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword5
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword6
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword7
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword8
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword9
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword10
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword11
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword12
* Please Place Description here.
* @var mac_ax_shcut_mhdr::dword13
* Please Place Description here.
*/
struct mac_ax_shcut_mhdr {/*need to revise note by kkbomb 0204*/
// dword 0
u32 mac_header_length:8;
u32 dword0:24;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
};
/**
* @struct mac_ax_fwstatus_payload
* @brief mac_ax_fwstatus_payload
*
* @var mac_ax_fwstatus_payload::dword0
* Please Place Description here.
* @var mac_ax_fwstatus_payload::dword1
* Please Place Description here.
*/
struct mac_ax_fwstatus_payload {
u32 dword0;
u32 dword1;
};
/**
* @struct mac_ax_ie_cam_cmd_info
* @brief mac_ax_ie_cam_cmd_info
*
* @var mac_ax_ie_cam_cmd_info::en
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::band
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::port
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::hit_en
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::miss_en
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::rst
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::hit_sel
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::miss_sel
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::rsvd0
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::num
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::rsvd1
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::buf
* Please Place Description here.
* @var mac_ax_ie_cam_cmd_info::buf_len
* Please Place Description here.
*/
struct mac_ax_ie_cam_cmd_info {
u8 en:1;
u8 band:1;
u8 port:3;
u8 hit_en:1;
u8 miss_en:1;
u8 rst:1;
u8 hit_sel:2;
u8 miss_sel:2;
u8 rsvd0:4;
u8 num:5;
u8 rsvd1:3;
u8 *buf;
u32 buf_len;
};
/**
* @struct mac_ax_addr_cam_info
* @brief mac_ax_addr_cam_info
*
* @var mac_ax_addr_cam_info::addr_cam_idx
* Please Place Description here.
* @var mac_ax_addr_cam_info::offset
* Please Place Description here.
* @var mac_ax_addr_cam_info::len
* Please Place Description here.
* @var mac_ax_addr_cam_info::valid
* Please Place Description here.
* @var mac_ax_addr_cam_info::net_type
* Please Place Description here.
* @var mac_ax_addr_cam_info::bcn_hit_cond
* Please Place Description here.
* @var mac_ax_addr_cam_info::hit_rule
* Please Place Description here.
* @var mac_ax_addr_cam_info::bb_sel
* Please Place Description here.
* @var mac_ax_addr_cam_info::addr_mask
* Please Place Description here.
* @var mac_ax_addr_cam_info::mask_sel
* Please Place Description here.
* @var mac_ax_addr_cam_info::bssid_cam_idx
* Please Place Description here.
* @var mac_ax_addr_cam_info::is_mul_ent
* Please Place Description here.
* @var mac_ax_addr_cam_info::sma
* Please Place Description here.
* @var mac_ax_addr_cam_info::tma
* Please Place Description here.
* @var mac_ax_addr_cam_info::macid
* Please Place Description here.
* @var mac_ax_addr_cam_info::port_int
* Please Place Description here.
* @var mac_ax_addr_cam_info::tsf_sync
* Please Place Description here.
* @var mac_ax_addr_cam_info::tf_trs
* Please Place Description here.
* @var mac_ax_addr_cam_info::lsig_txop
* Please Place Description here.
* @var mac_ax_addr_cam_info::tgt_ind
* Please Place Description here.
* @var mac_ax_addr_cam_info::frm_tgt_ind
* Please Place Description here.
* @var mac_ax_addr_cam_info::aid12
* Please Place Description here.
* @var mac_ax_addr_cam_info::wol_pattern
* Please Place Description here.
* @var mac_ax_addr_cam_info::wol_uc
* Please Place Description here.
* @var mac_ax_addr_cam_info::wol_magic
* Please Place Description here.
* @var mac_ax_addr_cam_info::wapi
* Please Place Description here.
* @var mac_ax_addr_cam_info::sec_ent_mode
* Please Place Description here.
* @var mac_ax_addr_cam_info::sec_ent_keyid
* Please Place Description here.
* @var mac_ax_addr_cam_info::sec_ent_valid
* Please Place Description here.
* @var mac_ax_addr_cam_info::sec_ent
* Please Place Description here.
*/
struct mac_ax_addr_cam_info {
u8 addr_cam_idx; /* Addr cam entry index */
u8 offset; /* Offset */
u8 len; /* Length */
u8 valid : 1;
u8 net_type : 2;
u8 bcn_hit_cond : 2;
u8 hit_rule : 2;
u8 bb_sel : 1;
u8 addr_mask : 6;
u8 mask_sel : 2;
u8 bssid_cam_idx : 6;
u8 is_mul_ent : 1;
u8 sma[6];
u8 tma[6];
u8 macid;
u8 port_int: 3;
u8 tsf_sync: 3;
u8 tf_trs: 1;
u8 lsig_txop: 1;
u8 tgt_ind: 3;
u8 frm_tgt_ind: 3;
u16 aid12: 12;
u8 wol_pattern: 1;
u8 wol_uc: 1;
u8 wol_magic: 1;
u8 wapi: 1;
u8 sec_ent_mode: 2;
u8 sec_ent_keyid[7];
u8 sec_ent_valid;
u8 sec_ent[7];
};
/**
* @struct mac_ax_bssid_cam_info
* @brief mac_ax_bssid_cam_info
*
* @var mac_ax_bssid_cam_info::bssid_cam_idx
* Please Place Description here.
* @var mac_ax_bssid_cam_info::offset
* Please Place Description here.
* @var mac_ax_bssid_cam_info::len
* Please Place Description here.
* @var mac_ax_bssid_cam_info::valid
* Please Place Description here.
* @var mac_ax_bssid_cam_info::bb_sel
* Please Place Description here.
* @var mac_ax_bssid_cam_info::bss_color
* Please Place Description here.
* @var mac_ax_bssid_cam_info::bssid
* Please Place Description here.
*/
struct mac_ax_bssid_cam_info {
u8 bssid_cam_idx; /* BSSID cam entry index */
u8 offset; /* Offset */
u8 len; /* Length */
u8 valid : 1;
u8 bb_sel : 1;
u8 addr_mask : 6;
u8 bss_color : 7;
u8 bssid[6];
};
/**
* @struct mac_ax_sec_cam_info
* @brief mac_ax_sec_cam_info
*
* @var mac_ax_sec_cam_info::sec_cam_idx
* Please Place Description here.
* @var mac_ax_sec_cam_info::offset
* Please Place Description here.
* @var mac_ax_sec_cam_info::len
* Please Place Description here.
* @var mac_ax_sec_cam_info::type
* Please Place Description here.
* @var mac_ax_sec_cam_info::ext_key
* Please Place Description here.
* @var mac_ax_sec_cam_info::spp_mode
* Please Place Description here.
* @var mac_ax_sec_cam_info::key
* Please Place Description here.
*/
struct mac_ax_sec_cam_info {
u8 sec_cam_idx; /* Security cam entry index */
u8 offset; /* Offset */
u8 len; /* Length */
u8 type : 4;
u8 ext_key : 1;
u8 spp_mode : 1;
u32 key[4];
};
/**
* @struct mac_ax_macaddr
* @brief mac_ax_macaddr
*
* @var mac_ax_macaddr::macaddr
* Please Place Description here.
*/
struct mac_ax_macaddr {
u8 macaddr[6];
};
/**
* @struct mac_ax_sta_init_info
* @brief mac_ax_sta_init_info
*
* @var mac_ax_sta_init_info::macid
* Please Place Description here.
* @var mac_ax_sta_init_info::opmode
* Please Place Description here.
* @var mac_ax_sta_init_info::band
* Please Place Description here.
* @var mac_ax_sta_init_info::wmm
* Please Place Description here.
* @var mac_ax_sta_init_info::trigger
* Please Place Description here.
* @var mac_ax_sta_init_info::is_hesta
* Please Place Description here.
* @var mac_ax_sta_init_info::dl_bw
* Please Place Description here.
* @var mac_ax_sta_init_info::tf_mac_padding
* Please Place Description here.
* @var mac_ax_sta_init_info::dl_t_pe
* Please Place Description here.
* @var mac_ax_sta_init_info::port_id
* Please Place Description here.
* @var mac_ax_sta_init_info::net_type
* Please Place Description here.
* @var mac_ax_sta_init_info::wifi_role
* Please Place Description here.
* @var mac_ax_sta_init_info::self_role
* Please Place Description here.
*/
struct mac_ax_sta_init_info {
u8 macid;
u8 opmode:1;
u8 band:1;
u8 wmm:2;
u8 trigger:1;
u8 is_hesta: 1;
u8 dl_bw: 2;
u8 tf_mac_padding:2;
u8 dl_t_pe:3;
u8 port_id:3;
u8 net_type:2;
u8 wifi_role:4;
u8 self_role:2;
};
/**
* @struct mac_ax_fwrole_maintain
* @brief mac_ax_fwrole_maintain
*
* @var mac_ax_fwrole_maintain::macid
* Please Place Description here.
* @var mac_ax_fwrole_maintain::self_role
* Please Place Description here.
* @var mac_ax_fwrole_maintain::upd_mode
* Please Place Description here.
* @var mac_ax_fwrole_maintain::wifi_role
* Please Place Description here.
*/
struct mac_ax_fwrole_maintain {
u8 macid;
u8 self_role : 2;
u8 upd_mode : 3;
u8 wifi_role : 4;
};
/**
* @struct mac_ax_cctl_info
* @brief mac_ax_cctl_info
*
* @var mac_ax_cctl_info::datarate
* Please Place Description here.
* @var mac_ax_cctl_info::force_txop
* Please Place Description here.
* @var mac_ax_cctl_info::data_bw
* Please Place Description here.
* @var mac_ax_cctl_info::data_gi_ltf
* Please Place Description here.
* @var mac_ax_cctl_info::darf_tc_index
* Please Place Description here.
* @var mac_ax_cctl_info::arfr_ctrl
* Please Place Description here.
* @var mac_ax_cctl_info::acq_rpt_en
* Please Place Description here.
* @var mac_ax_cctl_info::mgq_rpt_en
* Please Place Description here.
* @var mac_ax_cctl_info::ulq_rpt_en
* Please Place Description here.
* @var mac_ax_cctl_info::twtq_rpt_en
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd0
* Please Place Description here.
* @var mac_ax_cctl_info::disrtsfb
* Please Place Description here.
* @var mac_ax_cctl_info::disdatafb
* Please Place Description here.
* @var mac_ax_cctl_info::tryrate
* Please Place Description here.
* @var mac_ax_cctl_info::ampdu_density
* Please Place Description here.
* @var mac_ax_cctl_info::data_rty_lowest_rate
* Please Place Description here.
* @var mac_ax_cctl_info::ampdu_time_sel
* Please Place Description here.
* @var mac_ax_cctl_info::ampdu_len_sel
* Please Place Description here.
* @var mac_ax_cctl_info::rts_txcnt_lmt_sel
* Please Place Description here.
* @var mac_ax_cctl_info::rts_txcnt_lmt
* Please Place Description here.
* @var mac_ax_cctl_info::rtsrate
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd1
* Please Place Description here.
* @var mac_ax_cctl_info::vcs_stbc
* Please Place Description here.
* @var mac_ax_cctl_info::rts_rty_lowest_rate
* Please Place Description here.
* @var mac_ax_cctl_info::data_tx_cnt_lmt
* Please Place Description here.
* @var mac_ax_cctl_info::data_txcnt_lmt_sel
* Please Place Description here.
* @var mac_ax_cctl_info::max_agg_num_sel
* Please Place Description here.
* @var mac_ax_cctl_info::rts_en
* Please Place Description here.
* @var mac_ax_cctl_info::cts2self_en
* Please Place Description here.
* @var mac_ax_cctl_info::cca_rts
* Please Place Description here.
* @var mac_ax_cctl_info::hw_rts_en
* Please Place Description here.
* @var mac_ax_cctl_info::rts_drop_data_mode
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd2
* Please Place Description here.
* @var mac_ax_cctl_info::ampdu_max_len
* Please Place Description here.
* @var mac_ax_cctl_info::ul_mu_dis
* Please Place Description here.
* @var mac_ax_cctl_info::ampdu_max_time
* Please Place Description here.
* @var mac_ax_cctl_info::max_agg_num
* Please Place Description here.
* @var mac_ax_cctl_info::ba_bmap
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd3
* Please Place Description here.
* @var mac_ax_cctl_info::vo_lftime_sel
* Please Place Description here.
* @var mac_ax_cctl_info::vi_lftime_sel
* Please Place Description here.
* @var mac_ax_cctl_info::be_lftime_sel
* Please Place Description here.
* @var mac_ax_cctl_info::bk_lftime_sel
* Please Place Description here.
* @var mac_ax_cctl_info::sectype
* Please Place Description here.
* @var mac_ax_cctl_info::multi_port_id
* Please Place Description here.
* @var mac_ax_cctl_info::bmc
* Please Place Description here.
* @var mac_ax_cctl_info::mbssid
* Please Place Description here.
* @var mac_ax_cctl_info::navusehdr
* Please Place Description here.
* @var mac_ax_cctl_info::txpwr_mode
* Please Place Description here.
* @var mac_ax_cctl_info::data_dcm
* Please Place Description here.
* @var mac_ax_cctl_info::data_er
* Please Place Description here.
* @var mac_ax_cctl_info::data_ldpc
* Please Place Description here.
* @var mac_ax_cctl_info::data_stbc
* Please Place Description here.
* @var mac_ax_cctl_info::a_ctrl_bqr
* Please Place Description here.
* @var mac_ax_cctl_info::a_ctrl_uph
* Please Place Description here.
* @var mac_ax_cctl_info::a_ctrl_bsr
* Please Place Description here.
* @var mac_ax_cctl_info::a_ctrl_cas
* Please Place Description here.
* @var mac_ax_cctl_info::data_bw_er
* Please Place Description here.
* @var mac_ax_cctl_info::lsig_txop_en
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd4
* Please Place Description here.
* @var mac_ax_cctl_info::ctrl_cnt_vld
* Please Place Description here.
* @var mac_ax_cctl_info::ctrl_cnt
* Please Place Description here.
* @var mac_ax_cctl_info::resp_ref_rate
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd5
* Please Place Description here.
* @var mac_ax_cctl_info::all_ack_support
* Please Place Description here.
* @var mac_ax_cctl_info::bsr_queue_size_format
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd6
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd7
* Please Place Description here.
* @var mac_ax_cctl_info::ntx_path_en
* Please Place Description here.
* @var mac_ax_cctl_info::path_map_a
* Please Place Description here.
* @var mac_ax_cctl_info::path_map_b
* Please Place Description here.
* @var mac_ax_cctl_info::path_map_c
* Please Place Description here.
* @var mac_ax_cctl_info::path_map_d
* Please Place Description here.
* @var mac_ax_cctl_info::antsel_a
* Please Place Description here.
* @var mac_ax_cctl_info::antsel_b
* Please Place Description here.
* @var mac_ax_cctl_info::antsel_c
* Please Place Description here.
* @var mac_ax_cctl_info::antsel_d
* Please Place Description here.
* @var mac_ax_cctl_info::addr_cam_index
* Please Place Description here.
* @var mac_ax_cctl_info::paid
* Please Place Description here.
* @var mac_ax_cctl_info::uldl
* Please Place Description here.
* @var mac_ax_cctl_info::doppler_ctrl
* Please Place Description here.
* @var mac_ax_cctl_info::nominal_pkt_padding
* Please Place Description here.
* @var mac_ax_cctl_info::nominal_pkt_padding40
* Please Place Description here.
* @var mac_ax_cctl_info::txpwr_tolerence
* Please Place Description here.
* @var mac_ax_cctl_info::rsvd9
* Please Place Description here.
* @var mac_ax_cctl_info::nominal_pkt_padding80
* Please Place Description here.
* @var mac_ax_cctl_info::nc
* Please Place Description here.
* @var mac_ax_cctl_info::nr
* Please Place Description here.
* @var mac_ax_cctl_info::ng
* Please Place Description here.
* @var mac_ax_cctl_info::cb
* Please Place Description here.
* @var mac_ax_cctl_info::cs
* Please Place Description here.
* @var mac_ax_cctl_info::csi_txbf_en
* Please Place Description here.
* @var mac_ax_cctl_info::csi_stbc_en
* Please Place Description here.
* @var mac_ax_cctl_info::csi_ldpc_en
* Please Place Description here.
* @var mac_ax_cctl_info::csi_para_en
* Please Place Description here.
* @var mac_ax_cctl_info::csi_fix_rate
* Please Place Description here.
* @var mac_ax_cctl_info::csi_gi_ltf
* Please Place Description here.
* @var mac_ax_cctl_info::nominal_pkt_padding160
* Please Place Description here.
* @var mac_ax_cctl_info::csi_bw
* Please Place Description here.
*/
struct mac_ax_cctl_info {
/* dword 0 */
u32 datarate:9;
u32 force_txop:1;
u32 data_bw:2;
u32 data_gi_ltf:3;
u32 darf_tc_index:1;
u32 arfr_ctrl:4;
u32 acq_rpt_en:1;
u32 mgq_rpt_en:1;
u32 ulq_rpt_en:1;
u32 twtq_rpt_en:1;
u32 rsvd0:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 tryrate:1;
u32 ampdu_density:4;
/* dword 1 */
u32 data_rty_lowest_rate:9;
u32 ampdu_time_sel:1;
u32 ampdu_len_sel:1;
u32 rts_txcnt_lmt_sel:1;
u32 rts_txcnt_lmt:4;
u32 rtsrate:9;
u32 rsvd1:2;
u32 vcs_stbc:1;
u32 rts_rty_lowest_rate:4;
/* dword 2 */
u32 data_tx_cnt_lmt:6;
u32 data_txcnt_lmt_sel:1;
u32 max_agg_num_sel:1;
u32 rts_en:1;
u32 cts2self_en:1;
u32 cca_rts:2;
u32 hw_rts_en:1;
u32 rts_drop_data_mode:2;
u32 rsvd2:1;
u32 ampdu_max_len:11;
u32 ul_mu_dis:1;
u32 ampdu_max_time:4;
/* dword 3 */
u32 max_agg_num:8;
u32 ba_bmap:2;
u32 rsvd3:6;
u32 vo_lftime_sel:3;
u32 vi_lftime_sel:3;
u32 be_lftime_sel:3;
u32 bk_lftime_sel:3;
u32 sectype:4;
/* dword 4 */
u32 multi_port_id:3;
u32 bmc:1;
u32 mbssid:4;
u32 navusehdr:1;
u32 txpwr_mode:3;
u32 data_dcm:1;
u32 data_er:1;
u32 data_ldpc:1;
u32 data_stbc:1;
u32 a_ctrl_bqr:1;
u32 a_ctrl_uph:1;
u32 a_ctrl_bsr:1;
u32 a_ctrl_cas:1;
u32 data_bw_er:1;
u32 lsig_txop_en:1;
u32 rsvd4:5;
u32 ctrl_cnt_vld:1;
u32 ctrl_cnt:4;
/* dword 5 */
u32 resp_ref_rate:9;
u32 rsvd5:3;
u32 all_ack_support:1;
u32 bsr_queue_size_format:1;
u32 rsvd6:1;
u32 rsvd7:1;
u32 ntx_path_en:4;
u32 path_map_a:2;
u32 path_map_b:2;
u32 path_map_c:2;
u32 path_map_d:2;
u32 antsel_a:1;
u32 antsel_b:1;
u32 antsel_c:1;
u32 antsel_d:1;
/* dword 6 */
u32 addr_cam_index:8;
u32 paid:9;
u32 uldl:1;
u32 doppler_ctrl:2;
u32 nominal_pkt_padding:2;
u32 nominal_pkt_padding40:2;
u32 txpwr_tolerence:4;
u32 rsvd9:2;
u32 nominal_pkt_padding80:2;
/* dword 7 */
u32 nc:3;
u32 nr:3;
u32 ng:2;
u32 cb:2;
u32 cs:2;
u32 csi_txbf_en:1;
u32 csi_stbc_en:1;
u32 csi_ldpc_en:1;
u32 csi_para_en:1;
u32 csi_fix_rate:9;
u32 csi_gi_ltf:3;
u32 nominal_pkt_padding160:2;
u32 csi_bw:2;
};
/**
* @struct mac_ax_dctl_info
* @brief mac_ax_dctl_info
*
* @var mac_ax_dctl_info::qos_field_h
* Please Place Description here.
* @var mac_ax_dctl_info::hw_exseq_macid
* Please Place Description here.
* @var mac_ax_dctl_info::qos_field_h_en
* Please Place Description here.
* @var mac_ax_dctl_info::aes_iv_l
* Please Place Description here.
* @var mac_ax_dctl_info::aes_iv_h
* Please Place Description here.
* @var mac_ax_dctl_info::seq0
* Please Place Description here.
* @var mac_ax_dctl_info::seq1
* Please Place Description here.
* @var mac_ax_dctl_info::amsdu_max_length
* Please Place Description here.
* @var mac_ax_dctl_info::sta_amsdu_en
* Please Place Description here.
* @var mac_ax_dctl_info::chksum_offload_en
* Please Place Description here.
* @var mac_ax_dctl_info::with_llc
* Please Place Description here.
* @var mac_ax_dctl_info::rsvd0
* Please Place Description here.
* @var mac_ax_dctl_info::sec_hw_enc
* Please Place Description here.
* @var mac_ax_dctl_info::seq2
* Please Place Description here.
* @var mac_ax_dctl_info::seq3
* Please Place Description here.
* @var mac_ax_dctl_info::sec_cam_idx
* Please Place Description here.
*/
struct mac_ax_dctl_info {
/* dword 0 */
u32 qos_field_h:8;
u32 hw_exseq_macid:7;
u32 qos_field_h_en:1;
u32 aes_iv_l:16;
/* dword 1 */
u32 aes_iv_h:32;
/* dword 2 */
u32 seq0:12;
u32 seq1:12;
u32 amsdu_max_length:3;
u32 sta_amsdu_en:1;
u32 chksum_offload_en:1;
u32 with_llc:1;
u32 rsvd0:1;
u32 sec_hw_enc:1;
/* dword 3 */
u32 seq2:12;
u32 seq3:12;
u32 sec_cam_idx:8;
};
/**
* struct mac_ax_role_info - role information
* @macid: MAC ID.
* @band: Band selection, band0 or band1.
* @wmm: WMM selection, wmm0 ow wmm1.
* There are four sets about band and wmm,
* band0+wmm0, band0+wmm1, band1+wmm0,band1+wmm1.
*/
/**
* @struct mac_ax_role_info
* @brief mac_ax_role_info
*
* @var mac_ax_role_info::self_role
* Please Place Description here.
* @var mac_ax_role_info::wifi_role
* Please Place Description here.
* @var mac_ax_role_info::net_type
* Please Place Description here.
* @var mac_ax_role_info::upd_mode
* Please Place Description here.
* @var mac_ax_role_info::opmode
* Please Place Description here.
* @var mac_ax_role_info::band
* Please Place Description here.
* @var mac_ax_role_info::port
* Please Place Description here.
* @var mac_ax_role_info::macid
* Please Place Description here.
* @var mac_ax_role_info::wmm
* Please Place Description here.
* @var mac_ax_role_info::self_mac
* Please Place Description here.
* @var mac_ax_role_info::target_mac
* Please Place Description here.
* @var mac_ax_role_info::bssid
* Please Place Description here.
* @var mac_ax_role_info::bss_color
* Please Place Description here.
* @var mac_ax_role_info::bcn_hit_cond
* Please Place Description here.
* @var mac_ax_role_info::hit_rule
* Please Place Description here.
* @var mac_ax_role_info::is_mul_ent
* Please Place Description here.
* @var mac_ax_role_info::tsf_sync
* Please Place Description here.
* @var mac_ax_role_info::trigger
* Please Place Description here.
* @var mac_ax_role_info::lsig_txop
* Please Place Description here.
* @var mac_ax_role_info::tgt_ind
* Please Place Description here.
* @var mac_ax_role_info::frm_tgt_ind
* Please Place Description here.
* @var mac_ax_role_info::wol_pattern
* Please Place Description here.
* @var mac_ax_role_info::wol_uc
* Please Place Description here.
* @var mac_ax_role_info::wol_magic
* Please Place Description here.
* @var mac_ax_role_info::wapi
* Please Place Description here.
* @var mac_ax_role_info::sec_ent_mode
* Please Place Description here.
* @var mac_ax_role_info::is_hesta
* Please Place Description here.
* @var mac_ax_role_info::dl_bw
* Please Place Description here.
* @var mac_ax_role_info::tf_mac_padding
* Please Place Description here.
* @var mac_ax_role_info::dl_t_pe
* Please Place Description here.
* @var mac_ax_role_info::aid
* Please Place Description here.
* @var mac_ax_role_info::a_info
* Please Place Description here.
* @var mac_ax_role_info::b_info
* Please Place Description here.
* @var mac_ax_role_info::s_info
* Please Place Description here.
* @var mac_ax_role_info::c_info
* Please Place Description here.
*/
struct mac_ax_role_info {
enum mac_ax_self_role self_role;
enum mac_ax_wifi_role wifi_role;
enum mac_ax_net_type net_type;
enum mac_ax_upd_mode upd_mode;
enum mac_ax_opmode opmode;
enum mac_ax_band band;
enum mac_ax_port port;
enum mac_ax_addr_msk_sel mask_sel;
enum mac_ax_addr_msk addr_mask;
u8 macid;
u8 wmm:2;
u8 self_mac[6];
u8 target_mac[6];
u8 bssid[6];
u8 bss_color:6;
u8 bcn_hit_cond:2;
u8 hit_rule:2;
u8 is_mul_ent:1;
u8 tsf_sync:3;
u8 trigger:1;
u8 lsig_txop:1;
u8 tgt_ind:3;
u8 frm_tgt_ind:3;
u8 wol_pattern:1;
u8 wol_uc:1;
u8 wol_magic:1;
u8 wapi:1;
u8 sec_ent_mode:2;
u8 is_hesta:1;
u8 dl_bw:2;
u8 tf_mac_padding:2;
u8 dl_t_pe: 3;
u16 aid;
struct mac_ax_addr_cam_info a_info;
struct mac_ax_bssid_cam_info b_info;
struct mac_ax_sec_cam_info s_info;
struct mac_ax_cctl_info c_info;
};
/**
* @struct mac_role_tbl
* @brief mac_role_tbl
*
* @var mac_role_tbl::next
* Please Place Description here.
* @var mac_role_tbl::prev
* Please Place Description here.
* @var mac_role_tbl::info
* Please Place Description here.
* @var mac_role_tbl::macid
* Please Place Description here.
* @var mac_role_tbl::wmm
* Please Place Description here.
*/
struct mac_role_tbl {
/* keep first */
struct mac_role_tbl *next;
struct mac_role_tbl *prev;
struct mac_ax_role_info info;
u8 macid;
u8 wmm;
};
/**
* @struct mac_role_tbl_head
* @brief mac_role_tbl_head
*
* @var mac_role_tbl_head::next
* Please Place Description here.
* @var mac_role_tbl_head::prev
* Please Place Description here.
* @var mac_role_tbl_head::role_tbl_pool
* Please Place Description here.
* @var mac_role_tbl_head::qlen
* Please Place Description here.
* @var mac_role_tbl_head::lock
* Please Place Description here.
*/
struct mac_role_tbl_head {
/* keep first */
struct mac_role_tbl *next;
struct mac_role_tbl *prev;
struct mac_role_tbl_head *role_tbl_pool;
u32 qlen;
mac_ax_mutex lock;
};
/**
* @struct mac_ax_coex
* @brief mac_ax_coex
*
* @var mac_ax_coex::pta_mode
* Please Place Description here.
* @var mac_ax_coex::direction
* Please Place Description here.
*/
struct mac_ax_coex {
#define MAC_AX_COEX_RTK_MODE 0
#define MAC_AX_COEX_CSR_MODE 1
u8 pta_mode;
#define MAC_AX_COEX_INNER 0
#define MAC_AX_COEX_OUTPUT 1
#define MAC_AX_COEX_INPUT 2
u8 direction;
};
/**
* @struct mac_ax_port_tsf
* @brief mac_ax_port_tsf
*
* @var mac_ax_port_tsf::tsf_l
* Please Place Description here.
* @var mac_ax_port_tsf::tsf_h
* Please Place Description here.
* @var mac_ax_port_tsf::port
* Please Place Description here.
*/
struct mac_ax_port_tsf {
u32 tsf_l;
u32 tsf_h;
u8 port;
};
/**
* @struct mac_ax_gnt
* @brief mac_ax_gnt
*
* @var mac_ax_gnt::gnt_bt_sw_en
* Please Place Description here.
* @var mac_ax_gnt::gnt_bt
* Please Place Description here.
* @var mac_ax_gnt::gnt_wl_sw_en
* Please Place Description here.
* @var mac_ax_gnt::gnt_wl
* Please Place Description here.
*/
struct mac_ax_gnt {
u8 gnt_bt_sw_en;
u8 gnt_bt;
u8 gnt_wl_sw_en;
u8 gnt_wl;
};
/**
* @struct mac_ax_coex_gnt
* @brief mac_ax_coex_gnt
*
* @var mac_ax_coex_gnt::band0
* Please Place Description here.
* @var mac_ax_coex_gnt::band1
* Please Place Description here.
*/
struct mac_ax_coex_gnt {
struct mac_ax_gnt band0;
struct mac_ax_gnt band1;
};
/**
* @struct mac_ax_plt
* @brief mac_ax_plt
*
* @var mac_ax_plt::band
* Please Place Description here.
* @var mac_ax_plt::tx
* Please Place Description here.
* @var mac_ax_plt::rx
* Please Place Description here.
*/
struct mac_ax_plt {
#define MAC_AX_PLT_LTE_RX BIT(0)
#define MAC_AX_PLT_GNT_BT_TX BIT(1)
#define MAC_AX_PLT_GNT_BT_RX BIT(2)
#define MAC_AX_PLT_GNT_WL BIT(3)
u8 band;
u8 tx;
u8 rx;
};
/**
* @struct mac_ax_rx_cnt
* @brief mac_ax_rx_cnt
*
* @var mac_ax_rx_cnt::type
* Please Place Description here.
* @var mac_ax_rx_cnt::op
* Please Place Description here.
* @var mac_ax_rx_cnt::idx
* Please Place Description here.
* @var mac_ax_rx_cnt::band
* Please Place Description here.
* @var mac_ax_rx_cnt::buf
* Please Place Description here.
*/
struct mac_ax_rx_cnt {
#define MAC_AX_RX_CRC_OK 0
#define MAC_AX_RX_CRC_FAIL 1
#define MAC_AX_RX_FA 2
#define MAC_AX_RX_PPDU 3
#define MAC_AX_RX_IDX 4
u8 type;
#define MAC_AX_RXCNT_R 0
#define MAC_AX_RXCNT_RST_ALL 1
u8 op;
u8 idx;
u8 band;
u16 *buf;
};
/**
* @struct mac_ax_tx_cnt
* @brief mac_ax_tx_cnt
*
* @var mac_ax_tx_cnt::band
* Please Place Description here.
* @var mac_ax_tx_cnt::sel
* Please Place Description here.
* @var mac_ax_tx_cnt::txcnt
* Please Place Description here.
*/
struct mac_ax_tx_cnt {
#define MAC_AX_TX_LCCK 0
#define MAC_AX_TX_SCCK 1
#define MAC_AX_TX_OFDM 2
#define MAC_AX_TX_HT 3
#define MAC_AX_TX_HTGF 4
#define MAC_AX_TX_VHTSU 5
#define MAC_AX_TX_VHTMU 6
#define MAC_AX_TX_HESU 7
#define MAC_AX_TX_HEERSU 8
#define MAC_AX_TX_HEMU 9
#define MAC_AX_TX_HETB 10
#define MAC_AX_TX_ALLTYPE 11
u8 band;
u8 sel;
u16 txcnt[MAC_AX_TX_ALLTYPE];
};
/**
* @struct mac_ax_mcc_role
* @brief mac_ax_mcc_role
*
* @var mac_ax_mcc_role::macid
* Please Place Description here.
* @var mac_ax_mcc_role::central_ch_seg0
* Please Place Description here.
* @var mac_ax_mcc_role::central_ch_seg1
* Please Place Description here.
* @var mac_ax_mcc_role::primary_ch
* Please Place Description here.
* @var mac_ax_mcc_role::bandwidth
* Please Place Description here.
* @var mac_ax_mcc_role::group
* Please Place Description here.
* @var mac_ax_mcc_role::c2h_rpt
* Please Place Description here.
* @var mac_ax_mcc_role::dis_tx_null
* Please Place Description here.
* @var mac_ax_mcc_role::dis_sw_retry
* Please Place Description here.
* @var mac_ax_mcc_role::in_curr_ch
* Please Place Description here.
* @var mac_ax_mcc_role::sw_retry_count
* Please Place Description here.
* @var mac_ax_mcc_role::tx_null_early
* Please Place Description here.
* @var mac_ax_mcc_role::rsvd0
* Please Place Description here.
* @var mac_ax_mcc_role::duration
* Please Place Description here.
*/
struct mac_ax_mcc_role {
/* dword0 */
u32 macid: 8;
u32 central_ch_seg0: 8;
u32 central_ch_seg1: 8;
u32 primary_ch: 8;
/* dword1 */
enum channel_width bandwidth: 4;
u32 group: 2;
#define MCC_C2H_RPT_OFF 0
#define MCC_C2H_RPT_FAIL_ONLY 1
#define MCC_C2H_RPT_ALL 2
u32 c2h_rpt: 2;
u32 dis_tx_null: 1;
u32 dis_sw_retry: 1;
u32 in_curr_ch: 1;
u32 sw_retry_count: 3;
u32 tx_null_early: 4;
u32 btc_in_2g: 1;
u32 pta_en: 1;
u32 rfk_by_pass: 1;
u32 rsvd0: 11;
/* dword2 */
u32 duration: 32;
/* dword3 */
u8 courtesy_en;
u8 courtesy_num;
u8 courtesy_target;
u8 rsvd1;
};
struct mac_ax_mcc_start {
/* dword0 */
u32 group: 2;
u32 btc_in_group: 1;
u32 old_group_action: 2;
u32 old_group:2;
u32 rsvd0: 17;
u32 macid: 8;
/* dword1 */
u32 tsf_low;
/* dword2 */
u32 tsf_high;
};
/**
* @struct mac_ax_mcc_duration_info
* @brief mac_ax_mcc_duration_info
*
* @var mac_ax_mcc_duration_info::group
* Please Place Description here.
* @var mac_ax_mcc_duration_info::rsvd0
* Please Place Description here.
* @var mac_ax_mcc_duration_info::start_macid
* Please Place Description here.
* @var mac_ax_mcc_duration_info::macid_x
* Please Place Description here.
* @var mac_ax_mcc_duration_info::macid_y
* Please Place Description here.
* @var mac_ax_mcc_duration_info::start_tsf_low
* Please Place Description here.
* @var mac_ax_mcc_duration_info::start_tsf_high
* Please Place Description here.
* @var mac_ax_mcc_duration_info::duration_x
* Please Place Description here.
* @var mac_ax_mcc_duration_info::duration_y
* Please Place Description here.
*/
struct mac_ax_mcc_duration_info {
/* dword0 */
u32 group: 2;
u32 btc_in_group:1;
u32 rsvd0: 5;
u32 start_macid: 8;
u32 macid_x: 8;
u32 macid_y: 8;
/* dword1 */
u32 start_tsf_low;
/* dword2 */
u32 start_tsf_high;
/* dword3 */
u32 duration_x;
/* dword4 */
u32 duration_y;
};
/**
* @struct mac_ax_mcc_group
* @brief mac_ax_mcc_group
*
* @var mac_ax_mcc_group::rpt_status
* Please Place Description here.
* @var mac_ax_mcc_group::rpt_macid
* Please Place Description here.
* @var mac_ax_mcc_group::macid_x
* Please Place Description here.
* @var mac_ax_mcc_group::macid_y
* Please Place Description here.
* @var mac_ax_mcc_group::rpt_tsf_high
* Please Place Description here.
* @var mac_ax_mcc_group::rpt_tsf_low
* Please Place Description here.
* @var mac_ax_mcc_group::tsf_x_high
* Please Place Description here.
* @var mac_ax_mcc_group::tsf_x_low
* Please Place Description here.
* @var mac_ax_mcc_group::tsf_y_high
* Please Place Description here.
* @var mac_ax_mcc_group::tsf_y_low
* Please Place Description here.
*/
struct mac_ax_mcc_group {
u8 rpt_status;
u8 rpt_macid;
u8 macid_x;
u8 macid_y;
u32 rpt_tsf_high;
u32 rpt_tsf_low;
u32 tsf_x_high;
u32 tsf_x_low;
u32 tsf_y_high;
u32 tsf_y_low;
};
/**
* @struct mac_ax_mcc_group_info
* @brief mac_ax_mcc_group_info
*
* @var mac_ax_mcc_group_info::groups
* Please Place Description here.
*/
struct mac_ax_mcc_group_info {
struct mac_ax_mcc_group groups[4];
};
/**
* @struct mac_ax_tx_tf_info
* @brief mac_ax_tx_tf_info
*
* @var mac_ax_tx_tf_info::tx_tf_infol
* Please Place Description here.
* @var mac_ax_tx_tf_info::tx_tf_infoh
* Please Place Description here.
* @var mac_ax_tx_tf_info::tx_tf_infosel
* Please Place Description here.
*/
struct mac_ax_tx_tf_info {
u32 tx_tf_infol;
u32 tx_tf_infoh;
u8 tx_tf_infosel;//4:common info; 0~3: user0 ~ user3 info
};
/**
* @struct mac_ax_sr_info
* @brief mac_ax_sr_info
*
* @var mac_ax_sr_info::sr_en
* Please Place Description here.
* @var mac_ax_sr_info::sr_field_v15_allowed
* Please Place Description here.
* @var mac_ax_sr_info::srg_obss_pd_min
* Please Place Description here.
* @var mac_ax_sr_info::srg_obss_pd_max
* Please Place Description here.
* @var mac_ax_sr_info::non_srg_obss_pd_min
* Please Place Description here.
* @var mac_ax_sr_info::non_srg_obss_pd_max
* Please Place Description here.
* @var mac_ax_sr_info::srg_bsscolor_bitmap_0
* Please Place Description here.
* @var mac_ax_sr_info::srg_bsscolor_bitmap_1
* Please Place Description here.
* @var mac_ax_sr_info::srg_partbsid_bitmap_0
* Please Place Description here.
* @var mac_ax_sr_info::srg_partbsid_bitmap_1
* Please Place Description here.
*/
struct mac_ax_sr_info {
u8 sr_en: 1;
u8 sr_field_v15_allowed: 1;
u8 srg_obss_pd_min;
u8 srg_obss_pd_max;
u8 non_srg_obss_pd_min;
u8 non_srg_obss_pd_max;
u32 srg_bsscolor_bitmap_0;
u32 srg_bsscolor_bitmap_1;
u32 srg_partbsid_bitmap_0;
u32 srg_partbsid_bitmap_1;
};
/**
* @struct mac_ax_nav_padding
* @brief mac_ax_nav_padding
*
* @var mac_ax_nav_padding::band
* Please Place Description here.
* @var mac_ax_nav_padding::nav_pad_en
* Please Place Description here.
* @var mac_ax_nav_padding::over_txop_en
* Please Place Description here.
* @var mac_ax_nav_padding::nav_padding
* Please Place Description here.
*/
struct mac_ax_nav_padding {
u8 band;
u8 nav_pad_en;
u8 over_txop_en;
u16 nav_padding;
};
/**
* @struct mac_ax_max_tx_time
* @brief mac_ax_max_tx_time
*
* @var mac_ax_max_tx_time::macid
* Please Place Description here.
* @var mac_ax_max_tx_time::is_cctrl
* Please Place Description here.
* @var mac_ax_max_tx_time::max_tx_time
* Please Place Description here.
*/
struct mac_ax_max_tx_time {
u8 macid;
u8 is_cctrl;
u32 max_tx_time; /* us */
};
/**
* @struct mac_ax_hw_rts_th
* @brief Config HW RTS time/len threshold
*
* @var mac_ax_hw_rts_th::band
* the mac_band to setup/query
* @var mac_ax_hw_rts_th::time_th
* HW RTS time threshold
* @var mac_ax_hw_rts_th::time_th
* HW RTS length threshold
*/
struct mac_ax_hw_rts_th {
u8 band;
u16 time_th; /* us */
u16 len_th; /* byte */
};
/**
* @struct mac_ax_io_stat
* @brief Get IO state from HCI (PCIE: LBC)
*
* @var mac_ax_io_stat::to_flag
* timeout flag is set
* @var mac_ax_io_stat::io_st
* IO state from sm.io_st
* @var mac_ax_io_stat::rsvd
* reserved
* @var mac_ax_io_stat::addr
* the last timeout addr when timeout flag is set
*/
struct mac_ax_io_stat {
u8 to_flag:1;
u8 io_st:1;
u8 rsvd:6;
u32 addr;
};
/**
* @struct mac_ax_drv_stats
* @brief
*
* The driver status in halmac
*
* @var mac_ax_drv_stats::rx_ok
* RX status
* @var mac_ax_drv_stats::drv_rm
* Driver is removed
*/
struct mac_ax_drv_stats {
u8 rx_ok;
u8 drv_rm;
};
/**
* @struct mac_ax_wps_cfg
* @brief
*
* WPS is a driver feature to detect button pressed or released.
* In HW view, the feature is to check the GPIO input value is 0->1 or 1->0
* We use FW to detect GPIO val.
* In a specified interval, if FW detects value changed, it will send a C2H
*
* @var mac_ax_wps_cfg::en
* Enable WPS function i.e, Enable FW reports C2H
* @var mac_ax_wps_cfg::gpio
* The GPIO to be detected
* @var mac_ax_wps_cfg::interval
* The detecting interval in ms
*/
struct mac_ax_cfg_wps {
u8 en;
u8 gpio;
u8 interval; /* ms */
};
/**
* @struct mac_fw_msg
* @brief
*
* fw message encode/decode table
*
* @var mac_fw_msg::msgno
* @var mac_fw_msg::msg
*/
struct mac_fw_msg {
u32 msgno;
char *msg;
};
/*------------------- Define FAST_CH_SW related structure ---------------------------*/
/**
* @struct mac_ax_fast_ch_sw_param
* @brief
*
* FAST_CH_SW H2C params in driver
*
* @var mac_ax_fast_ch_sw_param::ap_port_id
* ap port id
* @var mac_ax_fast_ch_sw_param::ch_idx
* mapped channel idx for restoring rf param
* @var mac_ax_fast_ch_sw_param::thermal_idx
* thermal idx for restoring rf param
* @var mac_ax_fast_ch_sw_param::pause_rel_mode
* pause and release mode
* @var mac_ax_fast_ch_sw_param::con_sta_num
* num of connected sta currently
* @var mac_ax_fast_ch_sw_param::band
* PHY band
* @var mac_ax_fast_ch_sw_param::bandwidth
* bw of 20/40/80
* @var mac_ax_fast_ch_sw_param::pri_ch
* pri channel of target channel
* @var mac_ax_fast_ch_sw_param::central_ch
* central channel of target channel
* @var mac_ax_fast_ch_sw_param::rel_pause_tsfl
* release pause tsfl
* @var mac_ax_fast_ch_sw_param::rel_pause_tsfh
* release pause tsfh
* @var mac_ax_fast_ch_sw_param::rel_pause_delay_time
* release pause delay time
* @var mac_ax_fast_ch_sw_param::csa_pkt_id[MAC_AX_FAST_CH_SW_MAX_STA_NUM]
* offloaded CSA packet id for at most 4 stas
*/
struct mac_ax_fast_ch_sw_param {
/* dword0 */
u8 ap_port_id:4;
u8 ch_idx:4;
u8 thermal_idx:4;
u8 pause_rel_mode:4;
u8 con_sta_num;
u8 band:1;
u8 bandwidth:2;
u8 rsvd0:5;
/* dword1 */
u8 pri_ch;
u8 central_ch;
u16 rsvd1;
/* dword2 */
u32 rel_pause_tsfl;
/* dword3 */
u32 rel_pause_tsfh;
/* dword4 */
u32 rel_pause_delay_time;
/* dword5 */
u8 csa_pkt_id[MAC_AX_FAST_CH_SW_MAX_STA_NUM];
};
/**
* @struct mac_ax_fast_ch_sw_info
* @brief
*
* FAST_CH_SW status in driver
*
* @var mac_ax_fast_ch_sw_info::busy
* FW handling or not
* @var mac_ax_fast_ch_sw_info::status
* Last status of FCS
*/
struct mac_ax_fast_ch_sw_info{
bool busy;
u32 status;
};
/*------------------- END Define FAST_CH_SW related structure ---------------------------*/
struct mac_ax_tf_user_sts {
u8 macid;
u8 tb_rate;
u8 tb_fail_per;
u8 avg_tb_rssi;
u8 cca_miss_per;
u8 avg_uph;
u8 minflag_per;
u8 avg_tb_evm;
};
struct mac_ax_tf_sts {
u8 user_num;
u8 ru_su_per;
u16 rsvd;
struct mac_ax_tf_user_sts tf_user_sts[UL_PER_STA_DBGINFO_NUM];
};
struct mac_ax_fwc2h_sts {
struct mac_ax_tf_sts tfsts;
};
struct mac_ax_fwsts_para {
u16 en:1;
u16 rsvd:15;
u16 intvl_ms;
};
/*--------------------Define Adapter & OPs------------------------------------*/
#ifndef CONFIG_NEW_HALMAC_INTERFACE
/**
* @struct mac_ax_pltfm_cb
* @brief mac_ax_pltfm_cb
*
* @var mac_ax_pltfm_cb::sdio_cmd52_r8
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_r8
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_r16
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_r32
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_rn
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd52_w8
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_w8
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_w16
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_w32
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd53_wn
* Please Place Description here.
* @var mac_ax_pltfm_cb::sdio_cmd52_cia_r8
* Please Place Description here.
* @var mac_ax_pltfm_cb::reg_r8
* Please Place Description here.
* @var mac_ax_pltfm_cb::reg_r16
* Please Place Description here.
* @var mac_ax_pltfm_cb::reg_r32
* Please Place Description here.
* @var mac_ax_pltfm_cb::reg_w8
* Please Place Description here.
* @var mac_ax_pltfm_cb::reg_w16
* Please Place Description here.
* @var mac_ax_pltfm_cb::reg_w32
* Please Place Description here.
* @var mac_ax_pltfm_cb::tx
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_query_h2c
* Please Place Description here.
* @var mac_ax_pltfm_cb::tx
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_free
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_malloc
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_memcpy
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_memset
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_memcmp
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_delay_us
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_delay_ms
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_mutex_init
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_mutex_deinit
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_mutex_lock
* Please Place Description here.
* @var mac_ax_pltfm_cb::rtl_mutex_unlock
* Please Place Description here.
* @var mac_ax_pltfm_cb::msg_print
* Please Place Description here.
* @var mac_ax_pltfm_cb::event_notify
* Please Place Description here.
*/
struct mac_ax_pltfm_cb {
#if MAC_AX_SDIO_SUPPORT
u8 (*sdio_cmd52_r8)(void *drv_adapter, u32 addr);
u8 (*sdio_cmd53_r8)(void *drv_adapter, u32 addr);
u16 (*sdio_cmd53_r16)(void *drv_adapter, u32 addr);
u32 (*sdio_cmd53_r32)(void *drv_adapter, u32 addr);
u8 (*sdio_cmd53_rn)(void *drv_adapter, u32 addr, u32 size, u8 *val);
void (*sdio_cmd52_w8)(void *drv_adapter, u32 addr, u8 val);
void (*sdio_cmd53_w8)(void *drv_adapter, u32 addr, u8 val);
void (*sdio_cmd53_w16)(void *drv_adapter, u32 addr, u16 val);
void (*sdio_cmd53_w32)(void *drv_adapter, u32 addr, u32 val);
u8 (*sdio_cmd53_wn)(void *drv_adapter, u32 addr, u32 size, u8 *val);
u8 (*sdio_cmd52_cia_r8)(void *drv_adapter, u32 addr);
#endif
#if (MAC_AX_USB_SUPPORT || MAC_AX_PCIE_SUPPORT)
u8 (*reg_r8)(void *drv_adapter, u32 addr);
u16 (*reg_r16)(void *drv_adapter, u32 addr);
u32 (*reg_r32)(void *drv_adapter, u32 addr);
void (*reg_w8)(void *drv_adapter, u32 addr, u8 val);
void (*reg_w16)(void *drv_adapter, u32 addr, u16 val);
void (*reg_w32)(void *drv_adapter, u32 addr, u32 val);
#endif
#if MAC_AX_PHL_H2C
enum rtw_hal_status (*tx)(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com,
struct rtw_h2c_pkt *pkt);
struct rtw_h2c_pkt *(*rtl_query_h2c)(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com,
enum h2c_buf_class type);
enum rtw_hal_status (*rtl_recycle_h2c)(struct rtw_phl_com_t *phl_com,
struct rtw_h2c_pkt *h2c_pkt);
#else
u32 (*tx)(void *drv_adapter, u8 *buf, u32 len);
#endif
void (*rtl_free)(void *drv_adapter, void *buf, u32 size);
void* (*rtl_malloc)(void *drv_adapter, u32 size);
void (*rtl_memcpy)(void *drv_adapter, void *dest, void *src, u32 size);
void (*rtl_memset)(void *drv_adapter, void *addr, u8 val, u32 size);
s32 (*rtl_memcmp)(void *drv_adapter, void *ptr1, void *ptr2, u32 num);
void (*rtl_delay_us)(void *drv_adapter, u32 us);
void (*rtl_delay_ms)(void *drv_adapter, u32 ms);
void (*rtl_mutex_init)(void *drv_adapter, mac_ax_mutex *mutex);
void (*rtl_mutex_deinit)(void *drv_adapter, mac_ax_mutex *mutex);
void (*rtl_mutex_lock)(void *drv_adapter, mac_ax_mutex *mutex);
void (*rtl_mutex_unlock)(void *drv_adapter, mac_ax_mutex *mutex);
void (*msg_print)(void *drv_adapter, u8 dbg_level, s8 *fmt, ...);
void (*event_notify)(void *drv_adapter,
enum mac_ax_feature mac_ft,
enum mac_ax_status stat, u8 *buf, u32 size);
#if MAC_AX_FEATURE_DBGCMD
s32 (*rtl_sprintf)(void *drv_adapter, char *buf, size_t size, const char *fmt, ...);
s32 (*rtl_strcmp)(void *drv_adapter, const char *s1, const char *s2);
char* (*rtl_strsep)(void *drv_adapter, char **s, const char *ct);
u32 (*rtl_strlen)(void *drv_adapter, char *buf);
char* (*rtl_strcpy)(void *drv_adapter, char *dest, const char *src);
char* (*rtl_strpbrk)(void *drv_adapter, const char *cs, const char *ct);
u32 (*rtl_strtoul)(void *drv_adapter, const char *buf, u32 base);
#endif
void (*ser_l2_notify)(void *phl_com,
void *hal_com);
u8 (*ld_fw_symbol)(void *phl_adapter, void *drv_adapter,
const char *name, u8 **buf, u32 *buf_size);
};
#endif/*CONFIG_NEW_HALMAC_INTERFACE*/
/**
* @struct mac_ax_adapter
* @brief mac_ax_adapter
*
* @var mac_ax_adapter::ops
* Please Place Description here.
* @var mac_ax_adapter::drv_adapter
* Please Place Description here.
* @var mac_ax_adapter::phl_adapter
* Please Place Description here.
* @var mac_ax_adapter::pltfm_cb
* Please Place Description here.
* @var mac_ax_adapter::sm
* Please Place Description here.
* @var mac_ax_adapter::hw_info
* Please Place Description here.
* @var mac_ax_adapter::fw_info
* Please Place Description here.
* @var mac_ax_adapter::efuse_param
* Please Place Description here.
* @var mac_ax_adapter::mac_pwr_info
* Please Place Description here.
* @var mac_ax_adapter::ft_stat
* Please Place Description here.
* @var mac_ax_adapter::hfc_param
* Please Place Description here.
* @var mac_ax_adapter::dle_info
* Please Place Description here.
* @var mac_ax_adapter::gpio_info
* Please Place Description here.
* @var mac_ax_adapter::role_tbl
* Please Place Description here.
* @var mac_ax_adapter::read_ofld_info
* Please Place Description here.
* @var mac_ax_adapter::read_ofld_value
* Please Place Description here.
* @var mac_ax_adapter::write_ofld_info
* Please Place Description here.
* @var mac_ax_adapter::efuse_ofld_info
* Please Place Description here.
* @var mac_ax_adapter::conf_ofld_info
* Please Place Description here.
* @var mac_ax_adapter::pkt_ofld_info
* Please Place Description here.
* @var mac_ax_adapter::pkt_ofld_pkt
* Please Place Description here.
* @var mac_ax_adapter::mcc_group_info
* Please Place Description here.
* @var mac_ax_adapter::wowlan_info
* Please Place Description here.
* @var mac_ax_adapter::sdio_info
* Please Place Description here.
* @var mac_ax_adapter::usb_info
* Please Place Description here.
* @var mac_ax_adapter::hv_ops
* Please Place Description here.
*/
struct mac_ax_adapter {
struct mac_ax_ops *ops;
void *drv_adapter; //hal_com adapter
void *phl_adapter; //phl_com adapter
struct mac_ax_pltfm_cb *pltfm_cb;
struct mac_ax_state_mach sm;
struct mac_ax_hw_info *hw_info;
struct mac_ax_fw_info fw_info;
struct mac_ax_efuse_param efuse_param;
struct mac_ax_mac_pwr_info mac_pwr_info;
struct mac_ax_ft_status *ft_stat;
struct mac_ax_hfc_param *hfc_param;
struct mac_ax_dle_info dle_info;
struct mac_ax_gpio_info gpio_info;
struct mac_role_tbl_head *role_tbl;
struct mac_ax_read_ofld_info read_ofld_info;
struct mac_ax_read_ofld_value read_ofld_value;
struct mac_ax_write_ofld_info write_ofld_info;
struct mac_ax_efuse_ofld_info efuse_ofld_info;
struct mac_ax_conf_ofld_info conf_ofld_info;
struct mac_ax_pkt_ofld_info pkt_ofld_info;
struct mac_ax_pkt_ofld_pkt pkt_ofld_pkt;
struct mac_ax_cmd_ofld_info cmd_ofld_info;
struct mac_ax_mcc_group_info mcc_group_info;
struct mac_ax_wowlan_info wowlan_info;
struct mac_ax_p2p_info *p2p_info;
struct mac_ax_t32_togl_rpt *t32_togl_rpt;
struct mac_ax_port_info *port_info;
struct mac_ax_int_stats stats;
struct mac_ax_drv_stats drv_stats;
struct mac_ax_h2c_agg_info h2c_agg_info;
#if MAC_AX_SDIO_SUPPORT
struct mac_ax_sdio_info sdio_info;
#endif
#if MAC_AX_USB_SUPPORT
struct mac_ax_usb_info usb_info;
#endif
struct mac_ax_flash_info flash_info;
struct mac_ax_fast_ch_sw_info fast_ch_sw_info;
#if MAC_AX_FEATURE_HV
struct hv_ax_ops *hv_ops;
u8 env;
#endif
#if MAC_AX_FEATURE_DBGCMD
struct mac_ax_fw_dbgcmd fw_dbgcmd;
#endif
#if MAC_AX_FEATURE_DBGDEC
struct mac_fw_msg *fw_log_array;
struct mac_fw_msg *fw_log_array_dl;
u32 fw_log_array_dl_size;
#endif
struct mac_ax_fw_log log_cfg;
};
/**
* mac_ax_intf_ops - interface related callbacks
* @reg_read8:
* @reg_write8:
* @reg_read16:
* @reg_write16:
* @reg_read32:
* @reg_write32:
* @tx_allow_sdio:
* @tx_cmd_addr_sdio:
* @init_intf:
* @reg_read_n_sdio:
* @get_bulkout_id:
*/
/**
* @struct mac_ax_intf_ops
* @brief mac_ax_intf_ops
*
* @var mac_ax_intf_ops::reg_read8
* Please Place Description here.
* @var mac_ax_intf_ops::reg_write8
* Please Place Description here.
* @var mac_ax_intf_ops::reg_read16
* Please Place Description here.
* @var mac_ax_intf_ops::reg_write16
* Please Place Description here.
* @var mac_ax_intf_ops::reg_read32
* Please Place Description here.
* @var mac_ax_intf_ops::reg_write32
* Please Place Description here.
* @var mac_ax_intf_ops::tx_allow_sdio
* Please Place Description here.
* @var mac_ax_intf_ops::tx_cmd_addr_sdio
* Please Place Description here.
* @var mac_ax_intf_ops::intf_pre_init
* Please Place Description here.
* @var mac_ax_intf_ops::intf_init
* Please Place Description here.
* @var mac_ax_intf_ops::intf_deinit
* Please Place Description here.
* @var mac_ax_intf_ops::reg_read_n_sdio
* Please Place Description here.
* @var mac_ax_intf_ops::get_bulkout_id
* Please Place Description here.
* @var mac_ax_intf_ops::ltr_set_pcie
* Please Place Description here.
* @var mac_ax_intf_ops::u2u3_switch
* Please Place Description here.
* @var mac_ax_intf_ops::get_usb_mode
* Please Place Description here.
* @var mac_ax_intf_ops::get_usb_support_ability
* Please Place Description here.
* @var mac_ax_intf_ops::usb_tx_agg_cfg
* Please Place Description here.
* @var mac_ax_intf_ops::usb_rx_agg_cfg
* Please Place Description here.
* @var mac_ax_intf_ops::set_wowlan
* Please Place Description here.
*/
struct mac_ax_intf_ops {
u8 (*reg_read8)(struct mac_ax_adapter *adapter, u32 addr);
void (*reg_write8)(struct mac_ax_adapter *adapter, u32 addr, u8 val);
u16 (*reg_read16)(struct mac_ax_adapter *adapter, u32 addr);
void (*reg_write16)(struct mac_ax_adapter *adapter, u32 addr, u16 val);
u32 (*reg_read32)(struct mac_ax_adapter *adapter, u32 addr);
void (*reg_write32)(struct mac_ax_adapter *adapter, u32 addr, u32 val);
/**
* @tx_allow_sdio
* Only support SDIO interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*tx_allow_sdio)(struct mac_ax_adapter *adapter,
struct mac_ax_sdio_tx_info *info);
/**
* @tx_cmd_addr_sdio
* Only support SDIO interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*tx_cmd_addr_sdio)(struct mac_ax_adapter *adapter,
struct mac_ax_sdio_tx_info *info,
u32 *cmd_addr);
u32 (*intf_pre_init)(struct mac_ax_adapter *adapter, void *param);
u32 (*intf_init)(struct mac_ax_adapter *adapter, void *param);
u32 (*intf_deinit)(struct mac_ax_adapter *adapter, void *param);
/**
* @reg_read_n_sdio
* Only support SDIO interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*reg_read_n_sdio)(struct mac_ax_adapter *adapter, u32 addr,
u32 size, u8 *val);
/**
* @get_bulkout_id
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u8 (*get_bulkout_id)(struct mac_ax_adapter *adapter, u8 ch_dma,
u8 mode);
/**
* @ltr_set_pcie
* Only support PCIe interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*ltr_set_pcie)(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_ltr_param *param);
/**
* @u2u3_switch
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*u2u3_switch)(struct mac_ax_adapter *adapter);
/**
* @get_usb_mode
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*get_usb_mode)(struct mac_ax_adapter *adapter);
/**
* @get_usb_support_ability
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*get_usb_support_ability)(struct mac_ax_adapter *adapter);
/**
* @usb_tx_agg_cfg
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*usb_tx_agg_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_usb_tx_agg_cfg *agg);
/**
* @usb_rx_agg_cfg
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*usb_rx_agg_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_rx_agg_cfg *cfg);
u32 (*set_wowlan)(struct mac_ax_adapter *adapter,
enum mac_ax_wow_ctrl w_c);
/**
* @ctrl_txdma_ch
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*ctrl_txdma_ch)(struct mac_ax_adapter *adapter,
struct mac_ax_txdma_ch_map *ch_map);
/**
* @clr_idx_all
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*clr_idx_all)(struct mac_ax_adapter *adapter);
/**
* @poll_txdma_ch_idle
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*poll_txdma_ch_idle)(struct mac_ax_adapter *adapter,
struct mac_ax_txdma_ch_map *ch_map);
/**
* @poll_rxdma_ch_idle
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*poll_rxdma_ch_idle)(struct mac_ax_adapter *adapter,
struct mac_ax_rxdma_ch_map *ch_map);
/**
* @ctrl_txhci
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*ctrl_txhci)(struct mac_ax_adapter *adapter,
enum mac_ax_func_sw en);
/**
* @ctrl_rxhci
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*ctrl_rxhci)(struct mac_ax_adapter *adapter,
enum mac_ax_func_sw en);
/**
* @ctrl_dma_io
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*ctrl_dma_io)(struct mac_ax_adapter *adapter,
enum mac_ax_func_sw en);
/**
* @get_io_stat
* Only support PCIE interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*get_io_stat)(struct mac_ax_adapter *adapter,
struct mac_ax_io_stat *out_st);
/**
* @get_txagg_num
*/
u32 (*get_txagg_num)(struct mac_ax_adapter *adapter,
u8 band);
/**
* @get_rx_state
* Only support USB interface. Using this API in other interface
* may cause system crash or segmentation fault.
*/
u32 (*get_rx_state)(struct mac_ax_adapter *adapter, u32 *val);
};
/**
* struct mac_ax_ops - callbacks for mac control
* All callbacks can be used after initializing mac_ax_ops by mac_ax_ops_init.
* @intf_ops: interface related callbacks, refer struct mac_ax_intf_ops to get
* more deatails.
* @get_hw_info: get mac hardware information
* @mac_txdesc_len:
* @build_mac_txdesc:
*/
/**
* @struct mac_ax_ops
* @brief mac_ax_ops
*
* @var mac_ax_ops::intf_ops
* Please Place Description here.
* @var mac_ax_ops::hal_init
* Please Place Description here.
* @var mac_ax_ops::hal_fast_init
* Please Place Description here.
* @var mac_ax_ops::hal_deinit
* Please Place Description here.
* @var mac_ax_ops::hal_fast_deinit
* Please Place Description here.
* @var mac_ax_ops::add_role
* Please Place Description here.
* @var mac_ax_ops::remove_role
* Please Place Description here.
* @var mac_ax_ops::change_role
* Please Place Description here.
* @var mac_ax_ops::pwr_switch
* Please Place Description here.
* @var mac_ax_ops::sys_init
* Please Place Description here.
* @var mac_ax_ops::trx_init
* Please Place Description here.
* @var mac_ax_ops::romdl
* Please Place Description here.
* @var mac_ax_ops::enable_cpu
* Please Place Description here.
* @var mac_ax_ops::disable_cpu
* Please Place Description here.
* @var mac_ax_ops::fwredl
* Please Place Description here.
* @var mac_ax_ops::fwdl
* Please Place Description here.
* @var mac_ax_ops::enable_fw
* Please Place Description here.
* @var mac_ax_ops::lv1_rcvy
* Please Place Description here.
* @var mac_ax_ops::get_macaddr
* Please Place Description here.
* @var mac_ax_ops::build_txdesc
* Please Place Description here.
* @var mac_ax_ops::refill_txdesc
* Please Place Description here.
* @var mac_ax_ops::parse_rxdesc
* Please Place Description here.
* @var mac_ax_ops::reset_fwofld_state
* Please Place Description here.
* @var mac_ax_ops::check_fwofld_done
* Please Place Description here.
* @var mac_ax_ops::read_pkt_ofld
* Please Place Description here.
* @var mac_ax_ops::del_pkt_ofld
* Please Place Description here.
* @var mac_ax_ops::add_pkt_ofld
* Please Place Description here.
* @var mac_ax_ops::pkt_ofld_packet
* Please Place Description here.
* @var mac_ax_ops::dump_efuse_ofld
* Please Place Description here.
* @var mac_ax_ops::efuse_ofld_map
* Please Place Description here.
* @var mac_ax_ops::upd_dctl_info
* Please Place Description here.
* @var mac_ax_ops::upd_cctl_info
* Please Place Description here.
* @var mac_ax_ops::ie_cam_upd
* Please Place Description here.
* @var mac_ax_ops::twt_info_upd_h2c
* Please Place Description here.
* @var mac_ax_ops::twt_act_h2c
* Please Place Description here.
* @var mac_ax_ops::twt_anno_h2c
* Please Place Description here.
* @var mac_ax_ops::twt_wait_anno
* Please Place Description here.
* @var mac_ax_ops::mac_host_getpkt_h2c
* Please Place Description here.
* @var mac_ax_ops::p2p_act_h2c
* Please Place Description here.
* @var mac_ax_ops::sta_add_key
* Please Place Description here.
* @var mac_ax_ops::sta_del_key
* Please Place Description here.
* @var mac_ax_ops::sta_search_key_idx
* Please Place Description here.
* @var mac_ax_ops::sta_hw_security_support
* Please Place Description here.
* @var mac_ax_ops::set_mu_table
* Please Place Description here.
* @var mac_ax_ops::ss_dl_grp_upd
* Please Place Description here.
* @var mac_ax_ops::ss_ul_grp_upd
* Please Place Description here.
* @var mac_ax_ops::ss_ul_sta_upd
* Please Place Description here.
* @var mac_ax_ops::bacam_info
* Please Place Description here.
* @var mac_ax_ops::txdesc_len
* Please Place Description here.
* @var mac_ax_ops::upd_shcut_mhdr
* Please Place Description here.
* @var mac_ax_ops::enable_hwmasdu
* Please Place Description here.
* @var mac_ax_ops::enable_cut_hwamsdu
* Please Place Description here.
* @var mac_ax_ops::hdr_conv
* Please Place Description here.
* @var mac_ax_ops::set_hwseq_reg
* Please Place Description here.
* @var mac_ax_ops::process_c2h
* Please Place Description here.
* @var mac_ax_ops::parse_dfs
* Please Place Description here.
* @var mac_ax_ops::parse_ppdu
* Please Place Description here.
* @var mac_ax_ops::cfg_phy_rpt
* Please Place Description here.
* @var mac_ax_ops::set_rx_forwarding
* Please Place Description here.
* @var mac_ax_ops::get_rx_fltr_opt
* Please Place Description here.
* @var mac_ax_ops::set_rx_fltr_opt
* Please Place Description here.
* @var mac_ax_ops::set_rx_fltr_typ_opt
* Please Place Description here.
* @var mac_ax_ops::set_rx_fltr_typstyp_opt
* Please Place Description here.
* @var mac_ax_ops::sr_update
* Please Place Description here.
* @var mac_ax_ops::two_nav_cfg
* Please Place Description here.
* @var mac_ax_ops::pkt_drop
* Please Place Description here.
* @var mac_ax_ops::send_bcn_h2c
* Please Place Description here.
* @var mac_ax_ops::tx_mode_sel
* Please Place Description here.
* @var mac_ax_ops::tcpip_chksum_ofd
* Please Place Description here.
* @var mac_ax_ops::chk_rx_tcpip_chksum_ofd
* Please Place Description here.
* @var mac_ax_ops::chk_allq_empty
* Please Place Description here.
* @var mac_ax_ops::is_txq_empty
* Please Place Description here.
* @var mac_ax_ops::is_rxq_empty
* Please Place Description here.
* @var mac_ax_ops::parse_bcn_stats_c2h
* Please Place Description here.
* @var mac_ax_ops::upd_mudecision_para
* Please Place Description here.
* @var mac_ax_ops::mu_sta_upd
* Please Place Description here.
* @var mac_ax_ops::upd_ul_fixinfo
* Please Place Description here.
* @var mac_ax_ops::f2p_test_cmd
* Please Place Description here.
* @var mac_ax_ops::snd_test_cmd
* Please Place Description here.
* @var mac_ax_ops::set_fw_fixmode
* Please Place Description here.
* @var mac_ax_ops::mac_dumpwlanc
* Please Place Description here.
* @var mac_ax_ops::mac_dumpwlans
* Please Place Description here.
* @var mac_ax_ops::mac_dumpwland
* Please Place Description here.
* @var mac_ax_ops::outsrc_h2c_common
* Please Place Description here.
* @var mac_ax_ops::read_pwr_reg
* Please Place Description here.
* @var mac_ax_ops::write_pwr_reg
* Please Place Description here.
* @var mac_ax_ops::write_msk_pwr_reg
* Please Place Description here.
* @var mac_ax_ops::write_pwr_ofst_mode
* Please Place Description here.
* @var mac_ax_ops::write_pwr_ofst_bw
* Please Place Description here.
* @var mac_ax_ops::write_pwr_ref_reg
* Please Place Description here.
* @var mac_ax_ops::write_pwr_limit_en
* Please Place Description here.
* @var mac_ax_ops::write_pwr_limit_rua_reg
* Please Place Description here.
* @var mac_ax_ops::write_pwr_limit_reg
* Please Place Description here.
* @var mac_ax_ops::write_pwr_by_rate_reg
* Please Place Description here.
* @var mac_ax_ops::lamode_cfg
* Please Place Description here.
* @var mac_ax_ops::lamode_trigger
* Please Place Description here.
* @var mac_ax_ops::lamode_buf_cfg
* Please Place Description here.
* @var mac_ax_ops::get_lamode_st
* Please Place Description here.
* @var mac_ax_ops::read_xcap_reg
* Please Place Description here.
* @var mac_ax_ops::write_xcap_reg
* Please Place Description here.
* @var mac_ax_ops::write_bbrst_reg
* Please Place Description here.
* @var mac_ax_ops::get_csi_buffer_index
* Please Place Description here.
* @var mac_ax_ops::set_csi_buffer_index
* Please Place Description here.
* @var mac_ax_ops::get_snd_sts_index
* Please Place Description here.
* @var mac_ax_ops::set_snd_sts_index
* Please Place Description here.
* @var mac_ax_ops::init_snd_mer
* Please Place Description here.
* @var mac_ax_ops::init_snd_mee
* Please Place Description here.
* @var mac_ax_ops::csi_force_rate
* Please Place Description here.
* @var mac_ax_ops::csi_rrsc
* Please Place Description here.
* @var mac_ax_ops::set_snd_para
* Please Place Description here.
* @var mac_ax_ops::set_csi_para_reg
* Please Place Description here.
* @var mac_ax_ops::set_csi_para_cctl
* Please Place Description here.
* @var mac_ax_ops::hw_snd_pause_release
* Please Place Description here.
* @var mac_ax_ops::bypass_snd_sts
* Please Place Description here.
* @var mac_ax_ops::deinit_mee
* Please Place Description here.
* @var mac_ax_ops::cfg_lps
* Please Place Description here.
* @var mac_ax_ops::lps_pwr_state
* Please Place Description here.
* @var mac_ax_ops::chk_leave_lps
* Please Place Description here.
* @var mac_ax_ops::lps_chk_access
* Please Place Description here.
* @var mac_ax_ops::cfg_wow_wake
* Please Place Description here.
* @var mac_ax_ops::cfg_disconnect_det
* Please Place Description here.
* @var mac_ax_ops::cfg_keepalive
* Please Place Description here.
* @var mac_ax_ops::cfg_gtk_ofld
* Please Place Description here.
* @var mac_ax_ops::cfg_arp_ofld
* Please Place Description here.
* @var mac_ax_ops::cfg_ndp_ofld
* Please Place Description here.
* @var mac_ax_ops::cfg_realwow
* Please Place Description here.
* @var mac_ax_ops::cfg_nlo
* Please Place Description here.
* @var mac_ax_ops::cfg_dev2hst_gpio
* Please Place Description here.
* @var mac_ax_ops::cfg_uphy_ctrl
* Please Place Description here.
* @var mac_ax_ops::cfg_wowcam_upd
* Please Place Description here.
* @var mac_ax_ops::cfg_wow_sleep
* Please Place Description here.
* @var mac_ax_ops::get_wow_fw_status
* Please Place Description here.
* @var mac_ax_ops::request_aoac_report
* Please Place Description here.
* @var mac_ax_ops::read_aoac_report
* Please Place Description here.
* @var mac_ax_ops::check_aoac_report_done
* Please Place Description here.
* @var mac_ax_ops::dbcc_enable
* Please Place Description here.
* @var mac_ax_ops::port_cfg
* Please Place Description here.
* @var mac_ax_ops::port_init
* Please Place Description here.
* @var mac_ax_ops::enable_imr
* Please Place Description here.
* @var mac_ax_ops::dump_efuse_map_wl
* Please Place Description here.
* @var mac_ax_ops::dump_efuse_map_bt
* Please Place Description here.
* @var mac_ax_ops::write_efuse
* Please Place Description here.
* @var mac_ax_ops::read_efuse
* Please Place Description here.
* @var mac_ax_ops::get_efuse_avl_size
* Please Place Description here.
* @var mac_ax_ops::get_efuse_avl_size_bt
* Please Place Description here.
* @var mac_ax_ops::dump_log_efuse
* Please Place Description here.
* @var mac_ax_ops::read_log_efuse
* Please Place Description here.
* @var mac_ax_ops::write_log_efuse
* Please Place Description here.
* @var mac_ax_ops::dump_log_efuse_bt
* Please Place Description here.
* @var mac_ax_ops::read_log_efuse_bt
* Please Place Description here.
* @var mac_ax_ops::write_log_efuse_bt
* Please Place Description here.
* @var mac_ax_ops::pg_efuse_by_map
* Please Place Description here.
* @var mac_ax_ops::pg_efuse_by_map_bt
* Please Place Description here.
* @var mac_ax_ops::mask_log_efuse
* Please Place Description here.
* @var mac_ax_ops::pg_sec_data_by_map
* Please Place Description here.
* @var mac_ax_ops::cmp_sec_data_by_map
* Please Place Description here.
* @var mac_ax_ops::get_efuse_info
* Please Place Description here.
* @var mac_ax_ops::set_efuse_info
* Please Place Description here.
* @var mac_ax_ops::read_hidden_rpt
* Please Place Description here.
* @var mac_ax_ops::check_efuse_autoload
* Please Place Description here.
* @var mac_ax_ops::pg_simulator
* Please Place Description here.
* @var mac_ax_ops::checksum_update
* Please Place Description here.
* @var mac_ax_ops::checksum_rpt
* Please Place Description here.
* @var mac_ax_ops::set_efuse_ctrl
* Please Place Description here.
* @var mac_ax_ops::otp_test
* Please Place Description here.
* @var mac_ax_ops::get_mac_ft_status
* Please Place Description here.
* @var mac_ax_ops::fw_log_cfg
* Please Place Description here.
* @var mac_ax_ops::pinmux_set_func
* Please Place Description here.
* @var mac_ax_ops::pinmux_free_func
* Please Place Description here.
* @var mac_ax_ops::sel_uart_tx_pin
* Please Place Description here.
* @var mac_ax_ops::sel_uart_rx_pin
* Please Place Description here.
* @var mac_ax_ops::set_gpio_func
* Please Place Description here.
* @var mac_ax_ops::get_hw_info
* Please Place Description here.
* @var mac_ax_ops::set_hw_value
* Please Place Description here.
* @var mac_ax_ops::get_hw_value
* Please Place Description here.
* @var mac_ax_ops::get_err_status
* Please Place Description here.
* @var mac_ax_ops::set_err_status
* Please Place Description here.
* @var mac_ax_ops::general_pkt_ids
* Please Place Description here.
* @var mac_ax_ops::coex_init
* Please Place Description here.
* @var mac_ax_ops::coex_read
* Please Place Description here.
* @var mac_ax_ops::coex_write
* Please Place Description here.
* @var mac_ax_ops::trigger_cmac_err
* Please Place Description here.
* @var mac_ax_ops::trigger_cmac1_err
* Please Place Description here.
* @var mac_ax_ops::trigger_dmac_err
* Please Place Description here.
* @var mac_ax_ops::tsf_sync
* Please Place Description here.
* @var mac_ax_ops::reset_mcc_group
* Please Place Description here.
* @var mac_ax_ops::reset_mcc_request
* Please Place Description here.
* @var mac_ax_ops::add_mcc
* Please Place Description here.
* @var mac_ax_ops::start_mcc
* Please Place Description here.
* @var mac_ax_ops::stop_mcc
* Please Place Description here.
* @var mac_ax_ops::del_mcc_group
* Please Place Description here.
* @var mac_ax_ops::mcc_request_tsf
* Please Place Description here.
* @var mac_ax_ops::mcc_macid_bitmap
* Please Place Description here.
* @var mac_ax_ops::mcc_sync_enable
* Please Place Description here.
* @var mac_ax_ops::mcc_set_duration
* Please Place Description here.
* @var mac_ax_ops::get_mcc_tsf_rpt
* Please Place Description here.
* @var mac_ax_ops::get_mcc_status_rpt
* Please Place Description here.
* @var mac_ax_ops::check_add_mcc_done
* Please Place Description here.
* @var mac_ax_ops::check_start_mcc_done
* Please Place Description here.
* @var mac_ax_ops::check_stop_mcc_done
* Please Place Description here.
* @var mac_ax_ops::check_del_mcc_group_done
* Please Place Description here.
* @var mac_ax_ops::check_mcc_request_tsf_done
* Please Place Description here.
* @var mac_ax_ops::check_mcc_macid_bitmap_done
* Please Place Description here.
* @var mac_ax_ops::check_mcc_sync_enable_done
* Please Place Description here.
* @var mac_ax_ops::check_mcc_set_duration_done
* Please Place Description here.
* @var mac_ax_ops::check_access
* Please Place Description here.
* @var mac_ax_ops::set_led_mode
* Please Place Description here.
* @var mac_ax_ops::led_ctrl
* Please Place Description here.
* @var mac_ax_ops::set_sw_gpio_mode
* Please Place Description here.
* @var mac_ax_ops::sw_gpio_ctrl
* Please Place Description here.
* @var mac_ax_ops::fwcmd_lb
* Please Place Description here.
* @var mac_ax_ops::mem_dump
* Please Place Description here.
* @var mac_ax_ops::get_mem_size
* Please Place Description here.
* @var mac_ax_ops::dbg_status_dump
* Please Place Description here.
* @var mac_ax_ops::reg_dump
* Please Place Description here.
* @var mac_ax_ops::rx_cnt
* Please Place Description here.
* @var mac_ax_ops::dump_fw_rsvd_ple
* Please Place Description here.
* @var mac_ax_ops::fw_dbg_dump
* Please Place Description here.
* @var mac_ax_ops::event_notify
* Please Place Description here.
* @var mac_ax_ops::ram_boot
* Please Place Description here.
* @var mac_ax_ops::clear_write_request
* Please Place Description here.
* @var mac_ax_ops::add_write_request
* Please Place Description here.
* @var mac_ax_ops::write_ofld
* Please Place Description here.
* @var mac_ax_ops::clear_conf_request
* Please Place Description here.
* @var mac_ax_ops::add_conf_request
* Please Place Description here.
* @var mac_ax_ops::conf_ofld
* Please Place Description here.
* @var mac_ax_ops::clear_read_request
* Please Place Description here.
* @var mac_ax_ops::add_read_request
* Please Place Description here.
* @var mac_ax_ops::read_ofld
* Please Place Description here.
* @var mac_ax_ops::read_ofld_value
* Please Place Description here.
* @var mac_ax_ops::get_fw_status
* Please Place Description here.
*/
struct mac_ax_ops {
struct mac_ax_intf_ops *intf_ops;
/*System level*/
u32 (*hal_init)(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *trx_info,
struct mac_ax_fwdl_info *fwdl_info,
struct mac_ax_intf_info *intf_info);
u32 (*hal_fast_init)(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *trx_info,
struct mac_ax_fwdl_info *fwdl_info,
struct mac_ax_intf_info *intf_info);
u32 (*hal_deinit)(struct mac_ax_adapter *adapter);
u32 (*hal_fast_deinit)(struct mac_ax_adapter *adapter);
u32 (*add_role)(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info);
u32 (*remove_role)(struct mac_ax_adapter *adapter, u8 macid);
u32 (*change_role)(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info);
u32 (*pwr_switch)(struct mac_ax_adapter *adapter, u8 on);
u32 (*sys_init)(struct mac_ax_adapter *adapter);
u32 (*trx_init)(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info);
u32 (*romdl)(struct mac_ax_adapter *adapter, u8 *rom, u32 romaddr,
u32 len);
u32 (*enable_cpu)(struct mac_ax_adapter *adapter,
u8 boot_reason, u8 dlfw);
u32 (*disable_cpu)(struct mac_ax_adapter *adapter);
u32 (*fwredl)(struct mac_ax_adapter *adapter, u8 *fw, u32 len);
u32 (*fwdl)(struct mac_ax_adapter *adapter, u8 *fw, u32 len);
u32 (*enable_fw)(struct mac_ax_adapter *adapter,
enum rtw_fw_type cat);
u32 (*lv1_rcvy)(struct mac_ax_adapter *adapter,
enum mac_ax_lv1_rcvy_step step);
u32 (*get_macaddr)(struct mac_ax_adapter *adapter,
struct mac_ax_macaddr *macaddr,
u8 role_idx);
u32 (*build_txdesc)(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len);
u32 (*refill_txdesc)(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *txpkt_info,
struct mac_ax_refill_info *mask,
struct mac_ax_refill_info *info);
u32 (*parse_rxdesc)(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len);
/*FW offload related*/
u32 (*reset_fwofld_state)(struct mac_ax_adapter *adapter, u8 op);
u32 (*check_fwofld_done)(struct mac_ax_adapter *adapter, u8 op);
u32 (*read_pkt_ofld)(struct mac_ax_adapter *adapter, u8 id);
u32 (*del_pkt_ofld)(struct mac_ax_adapter *adapter, u8 id);
u32 (*add_pkt_ofld)(struct mac_ax_adapter *adapter, u8 *pkt,
u16 len, u8 *id);
u32 (*pkt_ofld_packet)(struct mac_ax_adapter *adapter,
u8 **pkt_buf, u16 *pkt_len, u8 *pkt_id);
u32 (*dump_efuse_ofld)(struct mac_ax_adapter *adapter, u32 efuse_size,
bool is_hidden);
u32 (*efuse_ofld_map)(struct mac_ax_adapter *adapter, u8 *efuse_map,
u32 efuse_size);
u32 (*upd_dctl_info)(struct mac_ax_adapter *adapter,
struct mac_ax_dctl_info *info,
struct mac_ax_dctl_info *mask, u8 macid,
u8 operation);
u32 (*upd_cctl_info)(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_info *info,
struct mac_ax_cctl_info *mask, u8 macid,
u8 operation);
u32 (*ie_cam_upd)(struct mac_ax_adapter *adapter,
struct mac_ax_ie_cam_cmd_info *info);
u32 (*twt_info_upd_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_twt_para *info);
u32 (*twt_act_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_twtact_para *info);
u32 (*twt_anno_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_twtanno_para *info);
void (*twt_wait_anno)(struct mac_ax_adapter *adapter,
u8 *c2h_content, u8 *upd_addr);
u32 (*mac_host_getpkt_h2c)(struct mac_ax_adapter *adapter,
u8 macid, u8 pkttype);
u32 (*p2p_act_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_p2p_act_info *info);
u32 (*p2p_macid_ctrl_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_p2p_macid_info *info);
u32 (*get_p2p_stat)(struct mac_ax_adapter *adapter);
u32 (*tsf32_togl_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_t32_togl_info *info);
u32 (*get_t32_togl_rpt)(struct mac_ax_adapter *adapter,
struct mac_ax_t32_togl_rpt *ret_rpt);
u32 (*ccxrpt_parsing)(struct mac_ax_adapter *adapter,
u8 *buf, struct mac_ax_ccxrpt *info);
/*Association, de-association related*/
u32 (*sta_add_key)(struct mac_ax_adapter *adapter,
struct mac_ax_sec_cam_info *sec_cam_content,
u8 mac_id, u8 key_id, u8 key_type);
u32 (*sta_del_key)(struct mac_ax_adapter *adapter,
u8 mac_id, u8 key_id, u8 key_type);
u32 (*sta_search_key_idx)(struct mac_ax_adapter *adapter,
u8 mac_id, u8 key_id, u8 key_type);
u32 (*sta_hw_security_support)(struct mac_ax_adapter *adapter,
u8 hw_security_support_type, u8 enable);
u32 (*sta_keycam_backup)(struct mac_ax_adapter *adapter,
u8 op_mode);
u32 (*set_mu_table)(struct mac_ax_adapter *adapter,
struct mac_mu_table *mu_table);
u32 (*ss_dl_grp_upd)(struct mac_ax_adapter *adapter,
struct mac_ax_ss_dl_grp_upd *info);
u32 (*ss_ul_grp_upd)(struct mac_ax_adapter *adapter,
struct mac_ax_ss_ul_grp_upd *info);
u32 (*ss_ul_sta_upd)(struct mac_ax_adapter *adapter,
struct mac_ax_ss_ul_sta_upd *info);
u32 (*bacam_info)(struct mac_ax_adapter *adapter,
struct mac_ax_bacam_info *info);
/*TRX related*/
u32 (*txdesc_len)(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info);
u32 (*upd_shcut_mhdr)(struct mac_ax_adapter *adapter,
struct mac_ax_shcut_mhdr *info, u8 macid);
u32 (*enable_hwmasdu)(struct mac_ax_adapter *adapter,
u8 enable,
enum mac_ax_amsdu_pkt_num max_num,
u8 en_single_amsdu,
u8 en_last_amsdu_padding);
u32 (*enable_cut_hwamsdu)(struct mac_ax_adapter *adapter,
u8 enable,
u8 low_th,
u16 high_th,
enum mac_ax_ex_shift aligned);
u32 (*hdr_conv)(struct mac_ax_adapter *adapter,
u8 en_hdr_conv);
u32 (*set_hwseq_reg)(struct mac_ax_adapter *adapter,
u8 reg_seq_idx,
u16 reg_seq_val);
u32 (*process_c2h)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
u8 *ret);
u32 (*parse_dfs)(struct mac_ax_adapter *adapter,
u8 *buf, u32 dfs_len, struct mac_ax_dfs_rpt *rpt);
u32 (*parse_ppdu)(struct mac_ax_adapter *adapter,
u8 *buf, u32 ppdu_len, u8 mac_info,
struct mac_ax_ppdu_rpt *rpt);
u32 (*cfg_phy_rpt)(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *cfg);
u32 (*set_rx_forwarding)(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fwd_ctrl_t *rf_ctrl_p);
u32 (*get_rx_fltr_opt)(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *opt,
enum mac_ax_band band);
u32 (*set_rx_fltr_opt)(struct mac_ax_adapter *adapter,
struct mac_ax_rx_fltr_ctrl_t *opt,
struct mac_ax_rx_fltr_ctrl_t *opt_msk,
enum mac_ax_band band);
u32 (*set_rx_fltr_typ_opt)(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
enum mac_ax_fwd_target fwd_target,
enum mac_ax_band band);
u32 (*set_rx_fltr_typstyp_opt)(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
u8 subtype,
enum mac_ax_fwd_target fwd_target,
enum mac_ax_band band);
u32 (*set_typsbtyp_fltr_detail)(struct mac_ax_adapter *adapter,
enum mac_ax_pkt_t type,
struct mac_ax_rx_fltr_elem *elem,
enum mac_ax_band band);
u32 (*get_cfg_addr_cam)(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *opt,
enum mac_ax_band band);
u32 (*get_cfg_addr_cam_dis)(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *opt,
enum mac_ax_band band);
u32 (*cfg_addr_cam)(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *ctl_opt,
struct mac_ax_addrcam_ctrl_t *ctl_msk,
enum mac_ax_band band);
u32 (*cfg_addr_cam_dis)(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *ctl_opt,
struct mac_ax_addrcam_dis_ctrl_t *ctl_msk,
enum mac_ax_band band);
u32 (*sr_update)(struct mac_ax_adapter *adapter,
struct mac_ax_sr_info *sr_info,
enum mac_ax_band band);
u32 (*two_nav_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_2nav_info *info);
u32 (*pkt_drop)(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info);
u32 (*send_bcn_h2c)(struct mac_ax_adapter *adapter,
struct mac_ax_bcn_info *info);
u32 (*tx_mode_sel)(struct mac_ax_adapter *adapter,
struct mac_ax_mac_tx_mode_sel *mode_sel);
u32 (*tcpip_chksum_ofd)(struct mac_ax_adapter *adapter,
u8 en_tx_chksum_ofd,
u8 en_rx_chksum_ofd);
u32 (*chk_rx_tcpip_chksum_ofd)(struct mac_ax_adapter *adapter,
u8 chksum_status);
u32 (*chk_allq_empty)(struct mac_ax_adapter *adapter, u8 *empty);
u32 (*is_txq_empty)(struct mac_ax_adapter *adapter,
struct mac_ax_tx_queue_empty *val);
u32 (*is_rxq_empty)(struct mac_ax_adapter *adapter,
struct mac_ax_rx_queue_empty *val);
u32 (*parse_bcn_stats_c2h)(struct mac_ax_adapter *adapter,
u8 *content,
struct mac_ax_bcn_cnt *val);
u32 (*tx_idle_poll)(struct mac_ax_adapter *adapter,
struct mac_ax_tx_idle_poll_cfg *poll_cfg);
u32 (*sifs_chk_cca_en)(struct mac_ax_adapter *adapter,
u8 band);
u32 (*patch_rx_rate)(struct mac_ax_adapter *adapter,
struct rtw_r_meta_data *info);
/*frame exchange related*/
u32 (*upd_mudecision_para)(struct mac_ax_adapter *adapter,
struct mac_ax_mudecision_para *info);
u32 (*mu_sta_upd)(struct mac_ax_adapter *adapter,
struct mac_ax_mu_sta_upd *info);
u32 (*upd_ul_fixinfo)(struct mac_ax_adapter *adapter,
struct mac_ax_ul_fixinfo *info);
u32 (*f2p_test_cmd)(struct mac_ax_adapter *adapter,
struct mac_ax_f2p_test_para *info,
struct mac_ax_f2p_wd *f2pwd,
struct mac_ax_f2p_tx_cmd *ptxcmd,
u8 *psigb_addr);
u32 (*snd_test_cmd)(struct mac_ax_adapter *adapter,
u8 *cmd_buf);
u32 (*set_fw_fixmode)(struct mac_ax_adapter *adapter,
struct mac_ax_fixmode_para *info);
u32 (*mac_dumpwlanc)(struct mac_ax_adapter *adapter,
struct mac_ax_dumpwlanc *para);
u32 (*mac_dumpwlans)(struct mac_ax_adapter *adapter,
struct mac_ax_dumpwlans *para);
u32 (*mac_dumpwland)(struct mac_ax_adapter *adapter,
struct mac_ax_dumpwland *para);
/*outsrcing related */
u32 (*outsrc_h2c_common)(struct mac_ax_adapter *adapter,
struct rtw_g6_h2c_hdr *hdr,
u32 *pvalue);
u32 (*read_pwr_reg)(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 *val);
u32 (*write_pwr_reg)(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 val);
u32 (*write_msk_pwr_reg)(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 mask, u32 val);
u32 (*write_pwr_ofst_mode)(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
u32 (*write_pwr_ofst_bw)(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
u32 (*write_pwr_ref_reg)(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
u32 (*write_pwr_limit_en)(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
u32 (*write_pwr_limit_rua_reg)(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
u32 (*write_pwr_limit_reg)(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_pwr_imt_info *tpu);
u32 (*write_pwr_by_rate_reg)(struct mac_ax_adapter *adapter,
u8 band,
struct rtw_tpu_pwr_by_rate_info *tpu);
u32 (*lamode_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_la_cfg *cfg);
u32 (*lamode_trigger)(struct mac_ax_adapter *adapter, u8 tgr);
u32 (*lamode_buf_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_la_buf_param *param);
struct mac_ax_la_status (*get_lamode_st)
(struct mac_ax_adapter *adapter);
u32 (*read_xcap_reg)(struct mac_ax_adapter *adapter, u8 sc_xo,
u32 *val);
u32 (*write_xcap_reg)(struct mac_ax_adapter *adapter, u8 sc_xo,
u32 val);
u32 (*write_bbrst_reg)(struct mac_ax_adapter *adapter, u8 val);
/*sounding related*/
u32 (*get_csi_buffer_index)(struct mac_ax_adapter *adapter, u8 band,
u8 csi_buffer_id);
u32 (*set_csi_buffer_index)(struct mac_ax_adapter *adapter, u8 band,
u8 macid, u16 csi_buffer_id,
u16 buffer_idx);
u32 (*get_snd_sts_index)(struct mac_ax_adapter *adapter, u8 band,
u8 index);
u32 (*set_snd_sts_index)(struct mac_ax_adapter *adapter, u8 band,
u8 macid, u8 index);
u32 (*init_snd_mer)(struct mac_ax_adapter *adapter, u8 band);
u32 (*init_snd_mee)(struct mac_ax_adapter *adapter, u8 band);
u32 (*csi_force_rate)(struct mac_ax_adapter *adapter, u8 band,
u8 ht_rate, u8 vht_rate, u8 he_rate);
u32 (*csi_rrsc)(struct mac_ax_adapter *adapter, u8 band, u32 rrsc);
u32 (*set_snd_para)(struct mac_ax_adapter *adapter,
struct mac_ax_fwcmd_snd *snd_info);
u32 (*set_csi_para_reg)(struct mac_ax_adapter *adapter,
struct mac_reg_csi_para *csi_para);
u32 (*set_csi_para_cctl)(struct mac_ax_adapter *adapter,
struct mac_cctl_csi_para *csi_para);
u32 (*hw_snd_pause_release)(struct mac_ax_adapter *adapter,
u8 band, u8 pr);
u32 (*bypass_snd_sts)(struct mac_ax_adapter *adapter);
u32 (*deinit_mee)(struct mac_ax_adapter *adapter, u8 band);
u32 (*snd_sup)(struct mac_ax_adapter *adapter,
struct mac_bf_sup *bf_sup);
u32 (*gidpos)(struct mac_ax_adapter *adapter,
struct mac_gid_pos *mu_gid);
/*lps related*/
u32 (*cfg_lps)(struct mac_ax_adapter *adapter,
u8 macid,
enum mac_ax_ps_mode ps_mode,
void *lps_info);
u32 (*lps_pwr_state)(struct mac_ax_adapter *adapter,
enum mac_ax_pwr_state_action action,
enum mac_ax_rpwm_req_pwr_state req_pwr_state);
u32 (*chk_leave_lps)(struct mac_ax_adapter *adapter, u8 macid);
/*Wowlan related*/
u32 (*cfg_wow_wake)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_wow_wake_info *info,
struct mac_ax_remotectrl_info_parm_ *content);
u32 (*cfg_disconnect_det)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_disconnect_det_info *info);
u32 (*cfg_keepalive)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_keep_alive_info *info);
u32 (*cfg_gtk_ofld)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_gtk_ofld_info *info,
struct mac_ax_gtk_info_parm_ *content);
u32 (*cfg_arp_ofld)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_arp_ofld_info *info,
void *parp_info_content);
u32 (*cfg_ndp_ofld)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_ndp_ofld_info *info,
struct mac_ax_ndp_info_parm_ *content);
u32 (*cfg_realwow)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_realwow_info *info,
struct mac_ax_realwowv2_info_parm_ *content);
u32 (*cfg_nlo)(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_nlo_info *info,
struct mac_ax_nlo_networklist_parm_ *content);
u32 (*cfg_dev2hst_gpio)(struct mac_ax_adapter *adapter,
struct mac_ax_dev2hst_gpio_info *parm);
u32 (*cfg_uphy_ctrl)(struct mac_ax_adapter *adapter,
struct mac_ax_uphy_ctrl_info *info);
u32 (*cfg_wowcam_upd)(struct mac_ax_adapter *adapter,
struct mac_ax_wowcam_upd_info *info);
u32 (*get_wow_wake_rsn)(struct mac_ax_adapter *adapter, u8 *wake_rsn,
u8 *reset);
u32 (*cfg_wow_sleep)(struct mac_ax_adapter *adapter,
u8 sleep);
u32 (*get_wow_fw_status)(struct mac_ax_adapter *adapter,
u8 *status, u8 func_en);
u32 (*request_aoac_report)(struct mac_ax_adapter *adapter,
u8 rx_ready);
u32 (*read_aoac_report)(struct mac_ax_adapter *adapter,
struct mac_ax_aoac_report *rpt_buf, u8 rx_ready);
u32 (*check_aoac_report_done)(struct mac_ax_adapter *adapter);
u32 (*wow_stop_trx)(struct mac_ax_adapter *adapter);
/*system related*/
u32 (*dbcc_enable)(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *info, u8 dbcc_en);
u32 (*port_cfg)(struct mac_ax_adapter *adapter,
enum mac_ax_port_cfg_type type,
struct mac_ax_port_cfg_para *para);
u32 (*port_init)(struct mac_ax_adapter *adapter,
struct mac_ax_port_init_para *para);
u32 (*enable_imr)(struct mac_ax_adapter *adapter, u8 band,
enum mac_ax_hwmod_sel sel);
u32 (*dump_efuse_map_wl)(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map);
u32 (*dump_efuse_map_bt)(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map);
u32 (*write_efuse)(struct mac_ax_adapter *adapter, u32 addr, u8 val,
enum mac_ax_efuse_bank bank);
u32 (*read_efuse)(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val, enum mac_ax_efuse_bank bank);
u32 (*get_efuse_avl_size)(struct mac_ax_adapter *adapter, u32 *size);
u32 (*get_efuse_avl_size_bt)(struct mac_ax_adapter *adapter, u32 *size);
u32 (*dump_log_efuse)(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map, bool is_limit);
u32 (*read_log_efuse)(struct mac_ax_adapter *adapter, u32 addr,
u32 size, u8 *val);
u32 (*write_log_efuse)(struct mac_ax_adapter *adapter, u32 addr,
u8 val);
u32 (*dump_log_efuse_bt)(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map);
u32 (*read_log_efuse_bt)(struct mac_ax_adapter *adapter, u32 addr,
u32 size, u8 *val);
u32 (*write_log_efuse_bt)(struct mac_ax_adapter *adapter, u32 addr,
u8 val);
u32 (*pg_efuse_by_map)(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg,
bool part, bool is_limit);
u32 (*pg_efuse_by_map_bt)(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg);
u32 (*mask_log_efuse)(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
u32 (*pg_sec_data_by_map)(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
u32 (*cmp_sec_data_by_map)(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
u32 (*get_efuse_info)(struct mac_ax_adapter *adapter, u8 *efuse_map,
enum rtw_efuse_info id, void *value,
u32 length, u8 *autoload_status);
u32 (*set_efuse_info)(struct mac_ax_adapter *adapter, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length);
u32 (*read_hidden_rpt)(struct mac_ax_adapter *adapter,
struct mac_defeature_value *rpt);
u32 (*check_efuse_autoload)(struct mac_ax_adapter *adapter,
u8 *autoload_status);
u32 (*pg_simulator)(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *phy_map);
u32 (*checksum_update)(struct mac_ax_adapter *adapter);
u32 (*checksum_rpt)(struct mac_ax_adapter *adapter, u16 *chksum);
u32 (*disable_rf)(struct mac_ax_adapter *adapter,
enum mac_ax_disable_rf_func func,
enum mac_ax_net_type type);
void (*set_efuse_ctrl)(struct mac_ax_adapter *adapter, u8 is_secure);
u32 (*otp_test)(struct mac_ax_adapter *adapter, bool is_OTP_test);
u32 (*get_mac_ft_status)(struct mac_ax_adapter *adapter,
enum mac_ax_feature mac_ft,
enum mac_ax_status *stat, u8 *buf,
const u32 size, u32 *ret_size);
u32 (*fw_log_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_fw_log *log_cfg);
u32 (*pinmux_set_func)(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func);
u32 (*pinmux_free_func)(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func);
u32 (*sel_uart_tx_pin)(struct mac_ax_adapter *adapter,
enum mac_ax_uart_tx_pin uart_pin);
u32 (*sel_uart_rx_pin)(struct mac_ax_adapter *adapter,
enum mac_ax_uart_rx_pin uart_pin);
u32 (*set_gpio_func)(struct mac_ax_adapter *adapter,
enum rtw_mac_gfunc func, s8 gpio);
struct mac_ax_hw_info* (*get_hw_info)(struct mac_ax_adapter *adapter);
u32 (*set_hw_value)(struct mac_ax_adapter *adapter,
enum mac_ax_hw_id hw_id, void *value);
u32 (*get_hw_value)(struct mac_ax_adapter *adapter,
enum mac_ax_hw_id hw_id, void *value);
u32 (*get_err_status)(struct mac_ax_adapter *adapter,
enum mac_ax_err_info *err);
u32 (*set_err_status)(struct mac_ax_adapter *adapter,
enum mac_ax_err_info err);
u32 (*general_pkt_ids)(struct mac_ax_adapter *adapter,
struct mac_ax_general_pkt_ids *ids);
u32 (*coex_init)(struct mac_ax_adapter *adapter,
struct mac_ax_coex *coex);
u32 (*coex_read)(struct mac_ax_adapter *adapter,
const u32 offset, u32 *val);
u32 (*coex_write)(struct mac_ax_adapter *adapter,
const u32 offset, const u32 val);
u32 (*trigger_cmac_err)(struct mac_ax_adapter *adapter);
u32 (*trigger_cmac1_err)(struct mac_ax_adapter *adapter);
u32 (*trigger_dmac_err)(struct mac_ax_adapter *adapter);
u32 (*tsf_sync)(struct mac_ax_adapter *adapter, u8 from_port,
u8 to_port, s32 sync_offset,
enum mac_ax_tsf_sync_act action);
u32 (*read_xtal_si)(struct mac_ax_adapter *adapter, u8 offset, u8 *val);
u32 (*write_xtal_si)(struct mac_ax_adapter *adapter, u8 offset, u8 val,
u8 bitmask);
u32 (*io_chk_access)(struct mac_ax_adapter *adapter, u32 offset);
u32 (*ser_ctrl)(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw);
/* mcc */
u32 (*reset_mcc_group)(struct mac_ax_adapter *adapter, u8 group);
u32 (*reset_mcc_request)(struct mac_ax_adapter *adapter, u8 group);
u32 (*add_mcc)(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_role *info);
u32 (*start_mcc)(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_start *info);
u32 (*stop_mcc)(struct mac_ax_adapter *adapter, u8 group, u8 macid,
u8 prev_groups);
u32 (*del_mcc_group)(struct mac_ax_adapter *adapter, u8 group,
u8 prev_groups);
u32 (*mcc_request_tsf)(struct mac_ax_adapter *adapter, u8 group,
u8 macid_x, u8 macid_y);
u32 (*mcc_macid_bitmap)(struct mac_ax_adapter *adapter, u8 group,
u8 macid, u8 *bitmap, u8 len);
u32 (*mcc_sync_enable)(struct mac_ax_adapter *adapter, u8 group,
u8 source, u8 target, u8 offset);
u32 (*mcc_set_duration)(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_duration_info *info);
u32 (*get_mcc_tsf_rpt)(struct mac_ax_adapter *adapter, u8 group,
u32 *tsf_x_high, u32 *tsf_x_low,
u32 *tsf_y_high, u32 *tsf_y_low);
u32 (*get_mcc_status_rpt)(struct mac_ax_adapter *adapter, u8 group,
u8 *status, u32 *tsf_high, u32 *tsf_low);
u32 (*get_mcc_group)(struct mac_ax_adapter *adapter, u8 *pget_group);
u32 (*check_add_mcc_done)(struct mac_ax_adapter *adapter, u8 group);
u32 (*check_start_mcc_done)(struct mac_ax_adapter *adapter, u8 group);
u32 (*check_stop_mcc_done)(struct mac_ax_adapter *adapter, u8 group);
u32 (*check_del_mcc_group_done)(struct mac_ax_adapter *adapter,
u8 group);
u32 (*check_mcc_request_tsf_done)(struct mac_ax_adapter *adapter,
u8 group);
u32 (*check_mcc_macid_bitmap_done)(struct mac_ax_adapter *adapter,
u8 group);
u32 (*check_mcc_sync_enable_done)(struct mac_ax_adapter *adapter,
u8 group);
u32 (*check_mcc_set_duration_done)(struct mac_ax_adapter *adapter,
u8 group);
/* not mcc */
u32 (*check_access)(struct mac_ax_adapter *adapter, u32 offset);
u32 (*set_led_mode)(struct mac_ax_adapter *adapter,
enum mac_ax_led_mode mode, u8 led_id);
u32 (*led_ctrl)(struct mac_ax_adapter *adapter, u8 high, u8 led_id);
u32 (*set_sw_gpio_mode)(struct mac_ax_adapter *adapter,
enum mac_ax_sw_io_mode mode, u8 gpio);
u32 (*sw_gpio_ctrl)(struct mac_ax_adapter *adapter, u8 high, u8 gpio);
u32 (*get_c2h_event)(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info);
u32 (*cfg_wps)(struct mac_ax_adapter *adapter,
struct mac_ax_cfg_wps *wps);
u32 (*get_wl_dis_val)(struct mac_ax_adapter *adapter, u8 *val);
#if MAC_AX_FEATURE_DBGPKG
u32 (*fwcmd_lb)(struct mac_ax_adapter *adapter, u32 len, u8 burst);
u32 (*mem_dump)(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel,
u32 strt_addr, u8 *data, u32 size, u32 dbg_path);
u32 (*get_mem_size)(struct mac_ax_adapter *adapter,
enum mac_ax_mem_sel sel);
void (*dbg_status_dump)(struct mac_ax_adapter *adapter,
struct mac_ax_dbgpkg *val,
struct mac_ax_dbgpkg_en *en);
u32 (*reg_dump)(struct mac_ax_adapter *adapter,
enum mac_ax_reg_sel sel);
u32 (*rx_cnt)(struct mac_ax_adapter *adapter,
struct mac_ax_rx_cnt *rxcnt);
u32 (*dump_fw_rsvd_ple)(struct mac_ax_adapter *adapter, u8 **buf);
void (*dump_ple_dbg_page)(struct mac_ax_adapter *adapter, u8 page_num);
u32 (*fw_dbg_dump)(struct mac_ax_adapter *adapter,
u8 **buf,
struct mac_ax_fwdbg_en *en);
u32 (*event_notify)(struct mac_ax_adapter *adapter,
enum phl_msg_evt_id id, u8 band);
u32 (*dbgport_hw_set)(struct mac_ax_adapter *adapter,
struct mac_ax_dbgport_hw *dp_hw);
#endif
#if MAC_AX_FEATURE_HV
u32 (*ram_boot)(struct mac_ax_adapter *adapter, u8 *fw, u32 len);
/*fw offload related*/
u32 (*clear_write_request)(struct mac_ax_adapter *adapter);
u32 (*add_write_request)(struct mac_ax_adapter *adapter,
struct mac_ax_write_req *req,
u8 *value, u8 *mask);
u32 (*write_ofld)(struct mac_ax_adapter *adapter);
u32 (*clear_conf_request)(struct mac_ax_adapter *adapter);
u32 (*add_conf_request)(struct mac_ax_adapter *adapter,
struct mac_ax_conf_ofld_req *req);
u32 (*conf_ofld)(struct mac_ax_adapter *adapter);
u32 (*clear_read_request)(struct mac_ax_adapter *adapter);
u32 (*add_read_request)(struct mac_ax_adapter *adapter,
struct mac_ax_read_req *req);
u32 (*read_ofld)(struct mac_ax_adapter *adapter);
u32 (*read_ofld_value)(struct mac_ax_adapter *adapter,
u8 **val_buf, u16 *val_len);
#endif
u32 (*add_cmd_ofld)(struct mac_ax_adapter *adapter,
struct rtw_mac_cmd *cmd);
/* flash related*/
u32 (*flash_erase)(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u32 timeout);
u32 (*flash_read)(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout);
u32 (*flash_write)(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout);
u32 (*fw_status_cmd)(struct mac_ax_adapter *adapter,
struct mac_ax_fwstatus_payload *info);
u32 (*fwc2h_ofdma_sts_parse)(struct mac_ax_adapter *adapter,
struct mac_ax_fwc2h_sts *fw_c2h_sts,
u32 *content);
u32 (*fw_ofdma_sts_en)(struct mac_ax_adapter *adapter,
struct mac_ax_fwsts_para *fwsts_para);
u32 (*tx_duty)(struct mac_ax_adapter *adapter,
u16 pause_intvl, u16 tx_intvl);
u32 (*tx_duty_stop)(struct mac_ax_adapter *adapter);
#if MAC_AX_FEATURE_DBGCMD
s32 (*halmac_cmd)(struct mac_ax_adapter *adapter, char *input, char *output, u32 out_len);
void (*halmac_cmd_parser)(struct mac_ax_adapter *adapter,
char input[][MAC_MAX_ARGV], u32 input_num, char *output,
u32 out_len);
#endif
/* FAST_CH_SW */
u32 (*fast_ch_sw)(struct mac_ax_adapter *adapter,
struct mac_ax_fast_ch_sw_param *fast_ch_sw_param);
u32 (*fast_ch_sw_done)(struct mac_ax_adapter *adapter);
u32 (*get_fast_ch_sw_rpt)(struct mac_ax_adapter *adapter, u32 *fast_ch_sw_status_code);
u32 (*write_coex_mask)(struct mac_ax_adapter *adapter,
u32 offset, u32 mask, u32 val);
u32 (*fw_dbg_dle_cfg)(struct mac_ax_adapter *adapter, bool lock);
void (*h2c_agg_en)(struct mac_ax_adapter *adapter, u8 enable);
void (*h2c_agg_flush)(struct mac_ax_adapter *adapter);
u32 (*h2c_agg_tx)(struct mac_ax_adapter *adapter);
#if MAC_AX_FEATURE_DBGDEC
u32 (*fw_log_set_array)(struct mac_ax_adapter *adapter, void *symbol_ptr, u32 file_size);
u32 (*fw_log_unset_array)(struct mac_ax_adapter *adapter);
#endif
u32 (*get_fw_status)(struct mac_ax_adapter *adapter);
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_def.h
|
C
|
agpl-3.0
| 428,365
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __MAC_HW_INFO_H
#define __MAC_HW_INFO_H
/*--------------------Define -------------------------------------------*/
/*--------------------Define MACRO--------------------------------------*/
/*--------------------Define Enum---------------------------------------*/
// TRX Desc related
// MAC_REG related
// F2P CMD related
/**
* @enum mac_ax_snd_pkt_sel
*
* @brief mac_ax_snd_pkt_sel
*
* @var mac_ax_snd_pkt_sel::MAC_AX_UNICAST_NDPA
* Please Place Description here.
* @var mac_ax_snd_pkt_sel::MAC_AX_BROADCAST_NDPA
* Please Place Description here.
* @var mac_ax_snd_pkt_sel::MAC_AX_LAST_NDPA
* Please Place Description here.
* @var mac_ax_snd_pkt_sel::MAC_AX_MIDDLE_NDPA
* Please Place Description here.
* @var mac_ax_snd_pkt_sel::MAC_AX_BF_REPORT_POLL
* Please Place Description here.
* @var mac_ax_snd_pkt_sel::MAC_AX_FINAL_BFRP
* Please Place Description here.
*/
enum mac_ax_snd_pkt_sel {
MAC_AX_UNICAST_NDPA = 0,
MAC_AX_BROADCAST_NDPA = 1,
MAC_AX_LAST_NDPA = 2,
MAC_AX_MIDDLE_NDPA = 3,
MAC_AX_BF_REPORT_POLL = 4,
MAC_AX_FINAL_BFRP = 5,
};
/**
* @enum mac_ax_ndpa_pkt
*
* @brief mac_ax_ndpa_pkt
*
* @var mac_ax_ndpa_pkt::MAC_AX_NORMAL_PKT
* Please Place Description here.
* @var mac_ax_ndpa_pkt::MAC_AX_HT_PKT
* Please Place Description here.
* @var mac_ax_ndpa_pkt::MAC_AX_VHT_PKT
* Please Place Description here.
* @var mac_ax_ndpa_pkt::MAC_AX_HE_PKT
* Please Place Description here.
*/
enum mac_ax_ndpa_pkt {
MAC_AX_NORMAL_PKT = 0,
MAC_AX_HT_PKT = 1,
MAC_AX_VHT_PKT = 2,
MAC_AX_HE_PKT = 2,
};
/*--------------------Define Struct-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_hw_info.h
|
C
|
agpl-3.0
| 2,318
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __INC_MAC_REG_H
#define __INC_MAC_REG_H
//
// WL_AX_REG_DMAC.xls
//
//
// TOP_OFF
//
#define R_AX_GT0_CTRL 0x8000
#define B_AX_GT0_COUNT_EN BIT(31)
#define B_AX_GT0_MODE BIT(30)
#define B_AX_GT0_EN BIT(29)
#define B_AX_GT0_SORT_EN BIT(28)
#define B_AX_GT0_DATA_SH 0
#define B_AX_GT0_DATA_MSK 0xfffffff
#define R_AX_GT0_CNT 0x8004
#define B_AX_GT0_CNT_SH 0
#define B_AX_GT0_CNT_MSK 0x1fffffff
#define R_AX_GT1_CTRL 0x8008
#define B_AX_GT1_COUNT_EN BIT(31)
#define B_AX_GT1_MODE BIT(30)
#define B_AX_GT1_EN BIT(29)
#define B_AX_GT1_SORT_EN BIT(28)
#define B_AX_GT1_DATA_SH 0
#define B_AX_GT1_DATA_MSK 0xfffffff
#define R_AX_GT1_CNT 0x800C
#define B_AX_GT1_CNT_SH 0
#define B_AX_GT1_CNT_MSK 0x1fffffff
#define R_AX_GT2_CTRL 0x8010
#define B_AX_GT2_COUNT_EN BIT(31)
#define B_AX_GT2_MODE BIT(30)
#define B_AX_GT2_EN BIT(29)
#define B_AX_GT2_SORT_EN BIT(28)
#define B_AX_GT2_DATA_SH 0
#define B_AX_GT2_DATA_MSK 0xfffffff
#define R_AX_GT2_CNT 0x8014
#define B_AX_GT2_CNT_SH 0
#define B_AX_GT2_CNT_MSK 0x1fffffff
#define R_AX_GT3_CTRL 0x8018
#define B_AX_GT3_COUNT_EN BIT(31)
#define B_AX_GT3_MODE BIT(30)
#define B_AX_GT3_EN BIT(29)
#define B_AX_GT3_SORT_EN BIT(28)
#define B_AX_GT3_DATA_SH 0
#define B_AX_GT3_DATA_MSK 0xfffffff
#define R_AX_GT3_CNT 0x801C
#define B_AX_GT3_CNT_SH 0
#define B_AX_GT3_CNT_MSK 0x1fffffff
#define R_AX_SORT_CTRL 0x8024
#define B_AX_CMAC1_SORT_EN BIT(1)
#define B_AX_CMAC0_SORT_EN BIT(0)
#define R_AX_PHYREG_SET 0x8040
#define B_AX_PHYREG_SET_SH 0
#define B_AX_PHYREG_SET_MSK 0xf
#define R_AX_FWD0IMR 0x8100
#define B_AX_FS_H2C_INT_EN BIT(8)
#define B_AX_FS_HIOE_ERR_INT_EN BIT(7)
#define B_AX_FS_SW_PLL_LEAVE_32K_INT_EN BIT(6)
#define B_AX_FS_MAILBOX_OUT_EMPTY_INT_EN BIT(5)
#define B_AX_FS_LTE_COEX_INT_EN BIT(4)
#define B_AX_FS_GT3_INT_EN BIT(3)
#define B_AX_FS_GT2_INT_EN BIT(2)
#define B_AX_FS_GT1_INT_EN BIT(1)
#define B_AX_FS_GT0_INT_EN BIT(0)
#define R_AX_FWD0ISR 0x8104
#define B_AX_FS_H2C_INT BIT(8)
#define B_AX_FS_HIOE_ERR_INT BIT(7)
#define B_AX_FS_SW_PLL_LEAVE_32K_INT BIT(6)
#define B_AX_FS_MAILBOX_OUT_EMPTY_INT BIT(5)
#define B_AX_FS_LTE_COEX_INT BIT(4)
#define B_AX_FS_GT3_INT BIT(3)
#define B_AX_FS_GT2_INT BIT(2)
#define B_AX_FS_GT1_INT BIT(1)
#define B_AX_FS_GT0_INT BIT(0)
#define R_AX_HD0IMR 0x8110
#define B_AX_WDT_PTFM_INT_EN BIT(5)
#define B_AX_CPWM_INT_EN BIT(2)
#define B_AX_GT3_INT_EN BIT(1)
#define B_AX_C2H_INT_EN BIT(0)
#define R_AX_HD0ISR 0x8114
#define B_AX_WDT_PTFM_INT BIT(5)
#define B_AX_CPWM_INT BIT(2)
#define B_AX_GT3_INT BIT(1)
#define B_AX_C2H_INT BIT(0)
#define R_AX_H2CREG_DATA0 0x8140
#define B_AX_H2CREG_D0_SH 0
#define B_AX_H2CREG_D0_MSK 0xffffffffL
#define R_AX_H2CREG_DATA1 0x8144
#define B_AX_H2CREG_D1_SH 0
#define B_AX_H2CREG_D1_MSK 0xffffffffL
#define R_AX_H2CREG_DATA2 0x8148
#define B_AX_H2CREG_D2_SH 0
#define B_AX_H2CREG_D2_MSK 0xffffffffL
#define R_AX_H2CREG_DATA3 0x814C
#define B_AX_H2CREG_D3_SH 0
#define B_AX_H2CREG_D3_MSK 0xffffffffL
#define R_AX_C2HREG_DATA0 0x8150
#define B_AX_C2HREG_D0_SH 0
#define B_AX_C2HREG_D0_MSK 0xffffffffL
#define R_AX_C2HREG_DATA1 0x8154
#define B_AX_C2HREG_D1_SH 0
#define B_AX_C2HREG_D1_MSK 0xffffffffL
#define R_AX_C2HREG_DATA2 0x8158
#define B_AX_C2HREG_D2_SH 0
#define B_AX_C2HREG_D2_MSK 0xffffffffL
#define R_AX_C2HREG_DATA3 0x815C
#define B_AX_C2HREG_D3_SH 0
#define B_AX_C2HREG_D3_MSK 0xffffffffL
#define R_AX_H2CREG_CTRL 0x8160
#define B_AX_H2CREG_TRIGGER BIT(0)
#define R_AX_C2HREG_CTRL 0x8164
#define B_AX_C2HREG_TRIGGER BIT(0)
#define R_AX_CPWM 0x8170
#define B_AX_CPWM_TOGGLE BIT(15)
#define B_AX_CPWM_VAL_SH 0
#define B_AX_CPWM_VAL_MSK 0x7fff
//
// 8852C TOP_OFF
//
#define R_AX_GT0_CTRL_V1 0x7000
#define R_AX_GT0_CNT_V1 0x7004
#define R_AX_GT1_CTRL_V1 0x7008
#define R_AX_GT1_CNT_V1 0x700C
#define R_AX_GT2_CTRL_V1 0x7010
#define R_AX_GT2_CNT_V1 0x7014
#define R_AX_GT3_CTRL_V1 0x7018
#define R_AX_GT3_CNT_V1 0x701C
#define R_AX_SORT_CTRL_V1 0x7024
#define R_AX_PHYREG_SET_V1 0x7040
#define R_AX_FWD0IMR_V1 0x7100
#define R_AX_FWD0ISR_V1 0x7104
#define R_AX_HD0IMR_V1 0x7110
#define R_AX_HD0ISR_V1 0x7114
#define R_AX_H2CREG_DATA0_V1 0x7140
#define R_AX_H2CREG_DATA1_V1 0x7144
#define R_AX_H2CREG_DATA2_V1 0x7148
#define R_AX_H2CREG_DATA3_V1 0x714C
#define R_AX_C2HREG_DATA0_V1 0x7150
#define R_AX_C2HREG_DATA1_V1 0x7154
#define R_AX_C2HREG_DATA2_V1 0x7158
#define R_AX_C2HREG_DATA3_V1 0x715C
#define R_AX_H2CREG_CTRL_V1 0x7160
#define R_AX_C2HREG_CTRL_V1 0x7164
#define R_AX_CPWM_V1 0x7170
//
// WL_PON
//
#define R_AX_FWD1IMR 0x8300
#define B_AX_FS_TM_WAKE_INT_EN BIT(16)
#define B_AX_FS_BT_MAILBOX_INT_EN BIT(1)
#define B_AX_FS_RPWM_INT_EN BIT(0)
#define R_AX_FWD1ISR 0x8304
#define B_AX_FS_TM_WAKE_INT BIT(16)
#define B_AX_FS_BT_MAILBOX_INT BIT(1)
#define B_AX_FS_RPWM_INT BIT(0)
#define R_AX_FSMIMR 0x8308
#define B_AX_FSM_RP_END_EVENT_IMR BIT(6)
#define B_AX_FSM_RX_BCN_TO_CNT_EVENT_IMR BIT(5)
#define B_AX_FSM_RX_MATCH_EVENT_IMR BIT(4)
#define B_AX_FSM_HIOE_ERR_EVENT_IMR BIT(3)
#define B_AX_FSM_OTHERS_WAKE_EVENT_IMR BIT(2)
#define B_AX_FSM_TIMER_TO_EVENT_IMR BIT(1)
#define R_AX_FSMISR 0x830C
#define B_AX_FSM_RP_END_EVENT_ISR BIT(6)
#define B_AX_FSM_RX_BCN_TO_CNT_EVENT_ISR BIT(5)
#define B_AX_FSM_RX_MATCH_EVENT_ISR BIT(4)
#define B_AX_FSM_HIOE_ERR_EVENT_ISR BIT(3)
#define B_AX_FSM_OTHERS_WAKE_EVENT_ISR BIT(2)
#define B_AX_FSM_TIMER_TO_EVENT_ISR BIT(1)
#define R_AX_TM_BKP_RES_CTRL 0x8310
#define B_AX_TM_WAKE_IND BIT(7)
#define B_AX_TM_BKP_EN_STS BIT(6)
#define B_AX_PRE_CHK_DONE BIT(3)
#define B_AX_PRE_CHK_VALID BIT(2)
#define B_AX_TM_RES_EN BIT(1)
#define B_AX_TM_BKP_EN_TRIGGER BIT(0)
#define R_AX_PRE_CHK_CTRL 0x8314
#define B_AX_PRE_CHK_THD_SH 16
#define B_AX_PRE_CHK_THD_MSK 0xffff
#define B_AX_PRE_WAKE_TIME_SH 0
#define B_AX_PRE_WAKE_TIME_MSK 0xffff
#define R_AX_LPS_WTM_SC 0x8318
#define B_AX_LPS_WTM_SC_SH 0
#define B_AX_LPS_WTM_SC_MSK 0xffffffffL
#define R_AX_LPS_WTM_CNT 0x831C
#define R_AX_TSF_32K_SEL 0x8320
#define B_AX_TSF_CLK_STABLE BIT(17)
#define B_AX_CKSL_WLTSF BIT(16)
#define B_AX_32K_SRC_SEL BIT(8)
#define B_AX_US_TIME_VALUE_SH 0
#define B_AX_US_TIME_VALUE_MSK 0xff
#define R_AX_HIOE_END_ADDR 0x8340
#define B_AX_HIOE_END_ADDR_SH 0
#define B_AX_HIOE_END_ADDR_MSK 0xffffffffL
#define R_AX_HIOE_STR_ADDR 0x8344
#define B_AX_HIOE_STR_ADDR_SH 0
#define B_AX_HIOE_STR_ADDR_MSK 0xffffffffL
#define R_AX_BKP_HIOE_CTRL 0x8348
#define B_AX_BKP_HIOE_CTRL_SH 0
#define B_AX_BKP_HIOE_CTRL_MSK 0xffffffffL
#define R_AX_RES_HIOE_CTRL 0x834C
#define B_AX_RES_HIOE_CTRL_SH 0
#define B_AX_RES_HIOE_CTRL_MSK 0xffffffffL
#define R_AX_HCI_FUNC_EN 0x8380
#define B_AX_HCI_RXDMA_EN BIT(1)
#define B_AX_HCI_TXDMA_EN BIT(0)
#define R_AX_OSC_32K_CTRL 0x8394
#define B_AX_LPOSC32K_OK BIT(31)
#define B_AX_CAL_32K_DBG_SEL BIT(3)
#define B_AX_CAL32K_XTAL_EN BIT(2)
#define B_AX_CAL32K_OSC_EN BIT(1)
#define B_AX_WL_POW_32KOSC BIT(0)
#define R_AX_32K_CAL_REG0 0x8398
#define B_AX_CAL_32K_REG_WR BIT(31)
#define B_AX_CAL_OSC_XTAL_SEL BIT(22)
#define B_AX_CAL_32K_REG_ADDR_SH 16
#define B_AX_CAL_32K_REG_ADDR_MSK 0x3f
#define B_AX_CAL_32K_REG_DATA_SH 0
#define B_AX_CAL_32K_REG_DATA_MSK 0xffff
#define R_AX_BOOT_DBG 0x83F0
#define B_AX_BOOT_STATUS_SH 16
#define B_AX_BOOT_STATUS_MSK 0xffff
#define B_AX_SECUREBOOT_STATUS_SH 0
#define B_AX_SECUREBOOT_STATUS_MSK 0xffff
//
// 8852C WL_PON
//
#define R_AX_FWD1IMR_V1 0x7800
#define R_AX_FWD1ISR_V1 0x7804
#define R_AX_FSMIMR_V1 0x7808
#define R_AX_FSMISR_V1 0x780C
#define R_AX_TM_BKP_RES_CTRL_V1 0x7810
#define R_AX_PRE_CHK_CTRL_V1 0x7814
#define R_AX_LPS_WTM_SC_V1 0x7818
#define R_AX_LPS_WTM_CNT_V1 0x781C
#define R_AX_TSF_32K_SEL_V1 0x7820
#define R_AX_HIOE_END_ADDR_V1 0x7840
#define R_AX_HIOE_STR_ADDR_V1 0x7844
#define R_AX_BKP_HIOE_CTRL_V1 0x7848
#define R_AX_RES_HIOE_CTRL_V1 0x784C
#define R_AX_HCI_FUNC_EN_V1 0x7880
#define R_AX_OSC_32K_CTRL_V1 0x7894
#define R_AX_32K_CAL_REG0_V1 0x7898
#define R_AX_BOOT_DBG_V1 0x78F0
//
// COMMON
//
#define R_AX_DMAC_FUNC_EN 0x8400
#define B_AX_DMAC_CRPRT BIT(31)
#define B_AX_MAC_FUNC_EN BIT(30)
#define B_AX_DMAC_FUNC_EN BIT(29)
#define B_AX_MPDU_PROC_EN BIT(28)
#define B_AX_WD_RLS_EN BIT(27)
#define B_AX_DLE_WDE_EN BIT(26)
#define B_AX_TXPKT_CTRL_EN BIT(25)
#define B_AX_STA_SCH_EN BIT(24)
#define B_AX_DLE_PLE_EN BIT(23)
#define B_AX_PKT_BUF_EN BIT(22)
#define B_AX_DMAC_TBL_EN BIT(21)
#define B_AX_PKT_IN_EN BIT(20)
#define B_AX_DLE_CPUIO_EN BIT(19)
#define B_AX_DISPATCHER_EN BIT(18)
#define B_AX_BBRPT_EN BIT(17)
#define B_AX_MAC_SEC_EN BIT(16)
#define B_AX_H_AXIDMA_EN BIT(14)
#define B_AX_DMAC_SER_PS BIT(13)
#define B_AX_CMAC_SER_PS BIT(12)
#define R_AX_DMAC_CLK_EN 0x8404
#define B_AX_MAC_CKEN BIT(30)
#define B_AX_DMAC_CKEN BIT(29)
#define B_AX_MPDU_CKEN BIT(28)
#define B_AX_WD_RLS_CLK_EN BIT(27)
#define B_AX_DLE_WDE_CLK_EN BIT(26)
#define B_AX_TXPKT_CTRL_CLK_EN BIT(25)
#define B_AX_STA_SCH_CLK_EN BIT(24)
#define B_AX_DLE_PLE_CLK_EN BIT(23)
#define B_AX_PKT_IN_CLK_EN BIT(20)
#define B_AX_DLE_CPUIO_CLK_EN BIT(19)
#define B_AX_DISPATCHER_CLK_EN BIT(18)
#define B_AX_BBRPT_CLK_EN BIT(17)
#define B_AX_MAC_SEC_CLK_EN BIT(16)
#define R_AX_LTR_CTRL_0 0x8410
#define B_AX_LTR_SPACE_IDX_SH 12
#define B_AX_LTR_SPACE_IDX_MSK 0x3
#define B_AX_LTR_IDLE_TIMER_IDX_SH 8
#define B_AX_LTR_IDLE_TIMER_IDX_MSK 0x7
#define B_AX_LTR_WD_NOEMP_CHK BIT(6)
#define B_AX_APP_LTR_ACT BIT(5)
#define B_AX_APP_LTR_IDLE BIT(4)
#define B_AX_LTR_EN BIT(1)
#define B_AX_LTR_HW_EN BIT(0)
#define R_AX_LTR_CTRL_1 0x8414
#define B_AX_LTR_RX0_TH_SH 16
#define B_AX_LTR_RX0_TH_MSK 0xfff
#define B_AX_LTR_RX1_TH_SH 0
#define B_AX_LTR_RX1_TH_MSK 0xfff
#define R_AX_LTR_IDLE_LATENCY 0x8418
#define B_AX_LTR_IDLE_LTCY_SH 0
#define B_AX_LTR_IDLE_LTCY_MSK 0xffffffffL
#define R_AX_LTR_ACTIVE_LATENCY 0x841C
#define B_AX_LTR_ACT_LTCY_SH 0
#define B_AX_LTR_ACT_LTCY_MSK 0xffffffffL
#define R_AX_DMAC_TABLE_CTRL 0x8420
#define B_AX_HWAMSDU_PADDING_MODE BIT(31)
#define B_AX_MACID_MPDU_PROCESSOR_OFFSET_SH 16
#define B_AX_MACID_MPDU_PROCESSOR_OFFSET_MSK 0x7ff
#define B_AX_DMAC_CTRL_INFO_OFFSET_SH 0
#define B_AX_DMAC_CTRL_INFO_OFFSET_MSK 0x7ff
#define R_AX_SER_DBG_INFO 0x8424
#define R_AX_DLE_EMPTY0 0x8430
#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25)
#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23)
#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22)
#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21)
#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20)
#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19)
#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18)
#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17)
#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16)
#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10)
#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8)
#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7)
#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2)
#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
#define R_AX_DLE_EMPTY1 0x8434
#define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
#define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
#define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
#define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
#define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
#define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
#define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
#define R_AX_FWD2IMR 0x8500
#define B_AX_FS_TXPKTIN_INT_EN BIT(5)
#define B_AX_FS_WWLAN_INT_EN BIT(4)
#define B_AX_FS_PLD_CPU_IO_PORT_Q1_INT_EN BIT(3)
#define B_AX_FS_PLD_CPU_IO_PORT_Q0_INT_EN BIT(2)
#define B_AX_FS_WD_CPU_IO_PORT_Q1_INT_EN BIT(1)
#define B_AX_FS_WD_CPU_IO_PORT_Q0_INT_EN BIT(0)
#define R_AX_FWD2ISR 0x8504
#define B_AX_FS_TXPKTIN_INT BIT(5)
#define B_AX_FS_WWLAN_INT BIT(4)
#define B_AX_FS_PLD_CPU_IO_PORT_Q1_INT BIT(3)
#define B_AX_FS_PLD_CPU_IO_PORT_Q0_INT BIT(2)
#define B_AX_FS_WD_CPU_IO_PORT_Q1_INT BIT(1)
#define B_AX_FS_WD_CPU_IO_PORT_Q0_INT BIT(0)
#define R_AX_DMAC_ERR_IMR 0x8520
#define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10)
#define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
#define B_AX_DISPATCH_ERR_INT_EN BIT(8)
#define B_AX_PKTIN_ERR_INT_EN BIT(7)
#define B_AX_PLE_DLE_ERR_INT_EN BIT(6)
#define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5)
#define B_AX_WDE_DLE_ERR_INT_EN BIT(4)
#define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3)
#define B_AX_MPDU_ERR_INT_EN BIT(2)
#define B_AX_WSEC_ERR_INT_EN BIT(1)
#define B_AX_WDRLS_ERR_INT_EN BIT(0)
#define R_AX_DMAC_ERR_ISR 0x8524
#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10)
#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
#define B_AX_DISPATCH_ERR_FLAG BIT(8)
#define B_AX_PKTIN_ERR_FLAG BIT(7)
#define B_AX_PLE_DLE_ERR_FLAG BIT(6)
#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5)
#define B_AX_WDE_DLE_ERR_FLAG BIT(4)
#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3)
#define B_AX_MPDU_ERR_FLAG BIT(2)
#define B_AX_WSEC_ERR_FLAG BIT(1)
#define B_AX_WDRLS_ERR_FLAG BIT(0)
#define R_AX_BIST_CTRL 0x8600
#define B_AX_BIST_DYN_READ_EN BIT(14)
#define B_AX_BIST_LOOP_MODE BIT(13)
#define B_AX_BIST_LVDRF_CLKDIS BIT(12)
#define B_AX_BIST_DRF_RESUME BIT(3)
#define B_AX_BIST_DRF_MODE BIT(2)
#define B_AX_BIST_MODE BIT(1)
#define B_AX_BIST_RSTN_ALL BIT(0)
#define R_AX_SYS_CTRL 0x8604
#define B_AX_SYM_MEM_RMV_FABDBG_SH 30
#define B_AX_SYM_MEM_RMV_FABDBG_MSK 0x3
#define B_AX_SYM_MEM_RMV_SIGN BIT(29)
#define B_AX_SYM_MEM_RMV_2PRF BIT(27)
#define B_AX_SYM_MEM_RMV_1PRF BIT(26)
#define B_AX_SYM_MEM_RMV_1PSR BIT(25)
#define B_AX_SYM_MEM_RMV_ROM BIT(24)
#define B_AX_SYM_MEM_RMV_WL_SH 4
#define B_AX_SYM_MEM_RMV_WL_MSK 0xf
#define R_AX_BIST_CTRL_1 0x8610
#define B_AX_BIST_RSTN_N_DMAC_SH 0
#define B_AX_BIST_RSTN_N_DMAC_MSK 0xfffffff
#define R_AX_BIST_CTRL_2 0x8614
#define B_AX_BIST_DONE_DMAC_SH 0
#define B_AX_BIST_DONE_DMAC_MSK 0xfffffff
#define R_AX_BIST_CTRL_3 0x8618
#define B_AX_BIST_FAIL_DMAC_SH 0
#define B_AX_BIST_FAIL_DMAC_MSK 0xfffffff
#define R_AX_BIST_CTRL_4 0x861C
#define B_AX_BIST_DRF_PAUSE_DMAC_SH 0
#define B_AX_BIST_DRF_PAUSE_DMAC_MSK 0xfffffff
//
// Dispatcher
//
#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800
#define B_AX_PL_PAGE_128B_SEL BIT(9)
#define B_AX_WD_PAGE_64B_SEL BIT(8)
#define B_AX_CDR_GATTING_DISABLE BIT(3)
#define B_AX_CDT_GATTING_DISABLE BIT(2)
#define B_AX_HDR_GATTING_DISABLE BIT(1)
#define B_AX_HDT_GATTING_DISABLE BIT(0)
#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804
#define B_AX_OTHER_STF_WROQT_UNDERFLOW BIT(29)
#define B_AX_OTHER_STF_WROQT_OVERFLOW BIT(28)
#define B_AX_OTHER_STF_WRFF_UNDERFLOW BIT(27)
#define B_AX_OTHER_STF_WRFF_OVERFLOW BIT(26)
#define B_AX_OTHER_STF_CMD_UNDERFLOW BIT(25)
#define B_AX_OTHER_STF_CMD_OVERFLOW BIT(24)
#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR BIT(17)
#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR BIT(16)
#define B_AX_PLE_OUTPUT_ERR BIT(12)
#define B_AX_PLE_RESP_ERR BIT(11)
#define B_AX_PLE_BURST_NUM_ERR BIT(10)
#define B_AX_PLE_NULL_PKT_ERR BIT(9)
#define B_AX_PLE_FLOW_CTRL_ERR BIT(8)
#define B_AX_WDE_OUTPUT_ERR BIT(4)
#define B_AX_WDE_RESP_ERR BIT(3)
#define B_AX_WDE_BURST_NUM_ERR BIT(2)
#define B_AX_WDE_NULL_PKT_ERR BIT(1)
#define B_AX_WDE_FLOW_CTRL_ERR BIT(0)
#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808
#define B_AX_HDT_RX_WRITE_UNDERFLOW BIT(31)
#define B_AX_HDT_RX_WRITE_OVERFLOW BIT(30)
#define B_AX_HDT_CHKSUM_FSM_ERR BIT(29)
#define B_AX_HDT_SHIFT_DMA_CFG_ERR BIT(28)
#define B_AX_HDT_DMA_PROCESS_ERR BIT(27)
#define B_AX_HDT_TOTAL_LEN_ERR BIT(26)
#define B_AX_HDT_SHIFT_EN_ERR BIT(25)
#define B_AX_HDT_RXAGG_CFG_ERR BIT(24)
#define B_AX_HDT_OUTPUT_ERR BIT(21)
#define B_AX_HDT_RESP_ERR BIT(20)
#define B_AX_HDT_BURST_NUM_ERR BIT(19)
#define B_AX_HDT_NULLPKT_ERR BIT(18)
#define B_AX_HDT_FLOW_CTRL_ERR BIT(17)
#define B_AX_HDT_PLD_CMD_UNDERFLOW BIT(16)
#define B_AX_HDT_PLD_CMD_OVERLOW BIT(15)
#define B_AX_HDT_TX_WRITE_UNDERFLOW BIT(14)
#define B_AX_HDT_TX_WRITE_OVERFLOW BIT(13)
#define B_AX_HDT_TCP_CHK_ERR BIT(12)
#define B_AX_HDT_TXPKTSIZE_ERR BIT(11)
#define B_AX_HDT_PRE_COST_ERR BIT(10)
#define B_AX_HDT_WD_CHK_ERR BIT(9)
#define B_AX_HDT_CHANNEL_DMA_ERR BIT(8)
#define B_AX_HDT_OFFSET_UNMATCH BIT(7)
#define B_AX_HDT_PAYLOAD_UNDERFLOW BIT(6)
#define B_AX_HDT_PAYLOAD_OVERFLOW BIT(5)
#define B_AX_HDT_PERMU_UNDERFLOW BIT(4)
#define B_AX_HDT_PERMU_OVERFLOW BIT(3)
#define B_AX_HDT_PKT_FAIL_DBG BIT(2)
#define B_AX_HDT_CHANNEL_ID_ERR BIT(1)
#define B_AX_HDT_CHANNEL_DIFF_ERR BIT(0)
#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C
#define B_AX_CPU_RX_WRITE_UNDERFLOW BIT(31)
#define B_AX_CPU_RX_WRITE_OVERFLOW BIT(30)
#define B_AX_CPU_CHKSUM_FSM_ERR BIT(29)
#define B_AX_CPU_SHIFT_DMA_CFG_ERR BIT(28)
#define B_AX_CPU_DMA_PROCESS_ERR BIT(27)
#define B_AX_CPU_TOTAL_LEN_ERR BIT(26)
#define B_AX_CPU_SHIFT_EN_ERR BIT(25)
#define B_AX_CPU_RXAGG_CFG_ERR BIT(24)
#define B_AX_CPU_OUTPUT_ERR BIT(20)
#define B_AX_CPU_RESP_ERR BIT(19)
#define B_AX_CPU_BURST_NUM_ERR BIT(18)
#define B_AX_CPU_NULLPKT_ERR BIT(17)
#define B_AX_CPU_FLOW_CTRL_ERR BIT(16)
#define B_AX_CPU_F2P_SEQ_ERR BIT(15)
#define B_AX_CPU_F2P_QSEL_ERR BIT(14)
#define B_AX_CPU_PLD_CMD_UNDERFLOW BIT(13)
#define B_AX_CPU_PLD_CMD_OVERLOW BIT(12)
#define B_AX_CPU_PRE_COST_ERR BIT(11)
#define B_AX_CPU_WD_CHK_ERR BIT(10)
#define B_AX_CPU_CHANNEL_DMA_ERR BIT(9)
#define B_AX_CPU_OFFSET_UNMATCH BIT(8)
#define B_AX_CPU_PAYLOAD_CHKSUM_ERR BIT(7)
#define B_AX_CPU_PAYLOAD_UNDERFLOW BIT(6)
#define B_AX_CPU_PAYLOAD_OVERFLOW BIT(5)
#define B_AX_CPU_PERMU_UNDERFLOW BIT(4)
#define B_AX_CPU_PERMU_OVERFLOW BIT(3)
#define B_AX_CPU_CHANNEL_ID_ERR BIT(2)
#define B_AX_CPU_PKT_FAIL_DBG BIT(1)
#define B_AX_CPU_CHANNEL_DIFF_ERR BIT(0)
#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810
#define B_AX_CPU_ADDR_INFO_8B_SEL BIT(8)
#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0)
#define R_AX_TX_TCPIP_CHECKSUM_FUNCTION 0x8814
#define B_AX_HDT_TCPIP_CHKSUM_EN BIT(0)
#define R_AX_TXAGG_ALIGN_CFG 0x8818
#define B_AX_TXAGG_ALIGN_SIZE_EN BIT(31)
#define B_AX_TXAGG_ALIGN_SIZE_SH 0
#define B_AX_TXAGG_ALIGN_SIZE_MSK 0xfff
#define R_AX_TX_PASTE_TIMESTAMP_SETTING 0x881C
#define B_AX_HDT_TIMESTAMP_EN BIT(0)
#define R_AX_CPU_PORT_DEBUG_SETTING 0x8820
#define B_AX_CDT_F2P_CPU_PORT_EN BIT(9)
#define B_AX_CDT_AC_CPU_PORT_EN BIT(8)
#define B_AX_HDT_AC_CPU_PORT_EN BIT(0)
#define R_AX_TX_CHECK_OFFSET_SETTING 0x8824
#define B_AX_CDT_CHK_OFFSET_EN BIT(24)
#define B_AX_CDT_CHK_OFFSET_SH 16
#define B_AX_CDT_CHK_OFFSET_MSK 0xff
#define B_AX_HDT_CHK_OFFSET_EN BIT(8)
#define B_AX_HDT_CHK_OFFSET_SH 0
#define B_AX_HDT_CHK_OFFSET_MSK 0xff
#define R_AX_TX_QUEUE_CLEAR_SETTING 0x8828
#define B_AX_HDT_TXQUE_CLR_EN BIT(0)
#define R_AX_TX_ERROR_STOP_DEBUG_SETTING 0x882C
#define B_AX_CDT_ERROR_STOP BIT(8)
#define B_AX_HDT_ERROR_STOP BIT(0)
#define R_AX_WD_CHECKSUM_FUNCTION_ENABLE 0x8830
#define B_AX_CDT_WD_CHKSUM_EN BIT(8)
#define B_AX_HDT_WD_CHKSUM_EN BIT(0)
#define R_AX_TX_DTAT_DROP_DEBUG_SETTING 0x8834
#define B_AX_CDT_DATA_DROP_EN BIT(8)
#define B_AX_HDT_DATA_DROP_EN BIT(0)
#define R_AX_REQUEST_PLE_BUFFER_SETTING 0x8838
#define B_AX_AMSDU_PADDING_SPACE_SH 8
#define B_AX_AMSDU_PADDING_SPACE_MSK 0xff
#define B_AX_RSV_PLD_SPACE_SH 0
#define B_AX_RSV_PLD_SPACE_MSK 0xff
#define R_AX_DMAC_MACID_DROP_0 0x8840
#define B_AX_DMAC_MACID31_0_DROP_SH 0
#define B_AX_DMAC_MACID31_0_DROP_MSK 0xffffffffL
#define R_AX_DMAC_MACID_DROP_1 0x8844
#define B_AX_DMAC_MACID63_32_DROP_SH 0
#define B_AX_DMAC_MACID63_32_DROP_MSK 0xffffffffL
#define R_AX_DMAC_MACID_DROP_2 0x8848
#define B_AX_DMAC_MACID95_64_DROP_SH 0
#define B_AX_DMAC_MACID95_64_DROP_MSK 0xffffffffL
#define R_AX_DMAC_MACID_DROP_3 0x884C
#define B_AX_DMAC_MACID127_96_DROP_SH 0
#define B_AX_DMAC_MACID127_96_DROP_MSK 0xffffffffL
#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850
#define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
#define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30)
#define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29)
#define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
#define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27)
#define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26)
#define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25)
#define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24)
#define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21)
#define B_AX_HDT_RES_ERR_INT_EN BIT(20)
#define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19)
#define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18)
#define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17)
#define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16)
#define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15)
#define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14)
#define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13)
#define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12)
#define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11)
#define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10)
#define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9)
#define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8)
#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7)
#define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
#define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5)
#define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4)
#define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3)
#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2)
#define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1)
#define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0)
#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854
#define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
#define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30)
#define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29)
#define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
#define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27)
#define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26)
#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25)
#define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24)
#define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20)
#define B_AX_CPU_RESP_ERR_INT_EN BIT(19)
#define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18)
#define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17)
#define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16)
#define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15)
#define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14)
#define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13)
#define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12)
#define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11)
#define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10)
#define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9)
#define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8)
#define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
#define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
#define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5)
#define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4)
#define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3)
#define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2)
#define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1)
#define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0)
#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858
#define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29)
#define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28)
#define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27)
#define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26)
#define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25)
#define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24)
#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17)
#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16)
#define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12)
#define B_AX_PLE_RESP_ERR_INT_EN BIT(11)
#define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10)
#define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9)
#define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
#define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4)
#define B_AX_WDE_RESP_ERR_INT_EN BIT(3)
#define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2)
#define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1)
#define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
#define R_AX_DISPATCHER_DBG_PORT 0x8860
#define B_AX_DISPATCHER_DBG_SEL_SH 8
#define B_AX_DISPATCHER_DBG_SEL_MSK 0xf
#define B_AX_DISPATCHER_INTN_SEL_SH 4
#define B_AX_DISPATCHER_INTN_SEL_MSK 0xf
#define B_AX_DISPATCHER_CH_SEL_SH 0
#define B_AX_DISPATCHER_CH_SEL_MSK 0xf
#define R_AX_HDP_DBG_INFO_4 0x8890
#define B_AX_ADDR_INFO_CS_SH 28
#define B_AX_ADDR_INFO_CS_MSK 0xf
#define B_AX_HCI_WP_FF_FULL BIT(27)
#define B_AX_AXI_WP_FF_FULL BIT(26)
#define B_AX_HFC_CH_FULL_SH 13
#define B_AX_HFC_CH_FULL_MSK 0x1fff
#define B_AX_HFC_CH_REQ_SH 0
#define B_AX_HFC_CH_REQ_MSK 0x1fff
#define R_AX_HDP_DBG_INFO_10 0x88A8
#define B_AX_DMA_ST_HDR_HDP_SH 20
#define B_AX_DMA_ST_HDR_HDP_MSK 0x7
#define B_AX_RX_ST_HDR_HDP_SH 16
#define B_AX_RX_ST_HDR_HDP_MSK 0x7
#define R_AX_RXAGG_0 0x8900
#define B_AX_RXAGG_EN BIT(31)
#define B_AX_RXAGG_DMA_STORE BIT(30)
#define B_AX_RXAGG_SW_EN BIT(29)
#define B_AX_RXAGG_SW_TRIG BIT(28)
#define B_AX_RXAGG_PKTNUM_TH_SH 16
#define B_AX_RXAGG_PKTNUM_TH_MSK 0xff
#define B_AX_RXAGG_TIMEOUT_TH_SH 8
#define B_AX_RXAGG_TIMEOUT_TH_MSK 0xff
#define B_AX_RXAGG_LEN_TH_SH 0
#define B_AX_RXAGG_LEN_TH_MSK 0xff
#define R_AX_RXAGG_1 0x8904
#define B_AX_RXAGG_SML_PKT_SIZE_SH 8
#define B_AX_RXAGG_SML_PKT_SIZE_MSK 0x7
#define B_AX_RXAGG_SML_PKTNUM_TH_SH 0
#define B_AX_RXAGG_SML_PKTNUM_TH_MSK 0x1f
#define R_AX_RXDMA_SETTING 0x8908
#define B_AX_PLE_BURST_READ BIT(24)
#define B_AX_REQ_DEPTH_SH 16
#define B_AX_REQ_DEPTH_MSK 0x3
#define B_AX_BULK_TH_OPT BIT(10)
#define B_AX_BURST_CNT_SH 8
#define B_AX_BURST_CNT_MSK 0x3
#define B_AX_BULK_SIZE_SH 0
#define B_AX_BULK_SIZE_MSK 0x3
#define R_AX_FWDL_CHECKSUM 0x890C
#define B_AX_FWDL_CHKSUM_SH 16
#define B_AX_FWDL_CHKSUM_MSK 0xffff
#define B_AX_FWDL_CHKSUM_VALID BIT(2)
#define B_AX_FWDL_CHKSUM_RESULT BIT(1)
#define B_AX_FWDL_CHKSUM_EN BIT(0)
#define R_AX_H2C_SETTING 0x8910
#define B_AX_CDR_REMOVE_H2C_WD BIT(0)
#define R_AX_RX_PPDU_STATUS_FW_MODE 0x8914
#define B_AX_HDR_PPDU_ENQ_WLCPU_EN BIT(31)
#define B_AX_CDR_PPDU_2_WLCPU_LEN_SH 0
#define B_AX_CDR_PPDU_2_WLCPU_LEN_MSK 0x3fff
#define R_AX_RX_TCPIP_CHECKSUM_FUNCTION 0x8918
#define B_AX_HDR_TCPIP_CHKSUM_EN BIT(0)
#define R_AX_RX_FC_BD_VALID_MASK 0x891C
#define B_AX_CDR_BD_MASK_SH 8
#define B_AX_CDR_BD_MASK_MSK 0x1f
#define B_AX_HDR_BD_MASK_SH 0
#define B_AX_HDR_BD_MASK_MSK 0x3
#define R_AX_RX_FUNCTION_STOP 0x8920
#define B_AX_HDR_RX_STOP BIT(0)
#define R_AX_HCI_FC_CTRL 0x8A00
#define B_AX_HCI_FC_CH12_FULL_COND_SH 10
#define B_AX_HCI_FC_CH12_FULL_COND_MSK 0x3
#define B_AX_HCI_FC_WP_CH811_FULL_COND_SH 8
#define B_AX_HCI_FC_WP_CH811_FULL_COND_MSK 0x3
#define B_AX_HCI_FC_WP_CH07_FULL_COND_SH 6
#define B_AX_HCI_FC_WP_CH07_FULL_COND_MSK 0x3
#define B_AX_HCI_FC_WD_FULL_COND_SH 4
#define B_AX_HCI_FC_WD_FULL_COND_MSK 0x3
#define B_AX_HCI_FC_CH12_EN BIT(3)
#define B_AX_HCI_FC_MODE_SH 1
#define B_AX_HCI_FC_MODE_MSK 0x3
#define B_AX_HCI_FC_EN BIT(0)
#define R_AX_CH_PAGE_CTRL 0x8A04
#define B_AX_PREC_PAGE_CH12_SH 16
#define B_AX_PREC_PAGE_CH12_MSK 0xff
#define B_AX_PREC_PAGE_CH011_SH 0
#define B_AX_PREC_PAGE_CH011_MSK 0xff
#define R_AX_ACH011_INTRPT_STAT 0x8A08
#define B_AX_ACH11_INTRPT_STAT BIT(11)
#define B_AX_ACH10_INTRPT_STAT BIT(10)
#define B_AX_ACH9_INTRPT_STAT BIT(9)
#define B_AX_ACH8_INTRPT_STAT BIT(8)
#define B_AX_ACH7_INTRPT_STAT BIT(7)
#define B_AX_ACH6_INTRPT_STAT BIT(6)
#define B_AX_ACH5_INTRPT_STAT BIT(5)
#define B_AX_ACH4_INTRPT_STAT BIT(4)
#define B_AX_ACH3_INTRPT_STAT BIT(3)
#define B_AX_ACH2_INTRPT_STAT BIT(2)
#define B_AX_ACH1_INTRPT_STAT BIT(1)
#define B_AX_ACH0_INTRPT_STAT BIT(0)
#define R_AX_HCI_FC_ERR_FLAG 0x8A0C
#define B_AX_PUB_AVAL_PG_OFW BIT(10)
#define B_AX_PUB_AVAL_PG_UFW BIT(9)
#define B_AX_PUB_USE_PG_OFW BIT(8)
#define B_AX_PUB_USE_PG_UFW BIT(7)
#define B_AX_CH011_USE_PG_OFW BIT(6)
#define B_AX_CH011_USE_PG_UFW BIT(5)
#define B_AX_CH011_AVAL_PG_OFW BIT(4)
#define B_AX_CH011_AVAL_PG_UFW BIT(3)
#define B_AX_WP_REQ_PG_ERR BIT(2)
#define B_AX_CH12_REQ_PG_ERR BIT(1)
#define B_AX_CH011_REQ_PG_ERR BIT(0)
#define R_AX_ACH0_PAGE_CTRL 0x8A10
#define B_AX_ACH0_GRP BIT(31)
#define B_AX_ACH0_MAX_PG_SH 16
#define B_AX_ACH0_MAX_PG_MSK 0xfff
#define B_AX_ACH0_MIN_PG_SH 0
#define B_AX_ACH0_MIN_PG_MSK 0xfff
#define R_AX_ACH1_PAGE_CTRL 0x8A14
#define B_AX_ACH1_GRP BIT(31)
#define B_AX_ACH1_MAX_PG_SH 16
#define B_AX_ACH1_MAX_PG_MSK 0xfff
#define B_AX_ACH1_MIN_PG_SH 0
#define B_AX_ACH1_MIN_PG_MSK 0xfff
#define R_AX_ACH2_PAGE_CTRL 0x8A18
#define B_AX_ACH2_GRP BIT(31)
#define B_AX_ACH2_MAX_PG_SH 16
#define B_AX_ACH2_MAX_PG_MSK 0xfff
#define B_AX_ACH2_MIN_PG_SH 0
#define B_AX_ACH2_MIN_PG_MSK 0xfff
#define R_AX_ACH3_PAGE_CTRL 0x8A1C
#define B_AX_ACH3_GRP BIT(31)
#define B_AX_ACH3_MAX_PG_SH 16
#define B_AX_ACH3_MAX_PG_MSK 0xfff
#define B_AX_ACH3_MIN_PG_SH 0
#define B_AX_ACH3_MIN_PG_MSK 0xfff
#define R_AX_ACH4_PAGE_CTRL 0x8A20
#define B_AX_ACH4_GRP BIT(31)
#define B_AX_ACH4_MAX_PG_SH 16
#define B_AX_ACH4_MAX_PG_MSK 0xfff
#define B_AX_ACH4_MIN_PG_SH 0
#define B_AX_ACH4_MIN_PG_MSK 0xfff
#define R_AX_ACH5_PAGE_CTRL 0x8A24
#define B_AX_ACH5_GRP BIT(31)
#define B_AX_ACH5_MAX_PG_SH 16
#define B_AX_ACH5_MAX_PG_MSK 0xfff
#define B_AX_ACH5_MIN_PG_SH 0
#define B_AX_ACH5_MIN_PG_MSK 0xfff
#define R_AX_ACH6_PAGE_CTRL 0x8A28
#define B_AX_ACH6_GRP BIT(31)
#define B_AX_ACH6_MAX_PG_SH 16
#define B_AX_ACH6_MAX_PG_MSK 0xfff
#define B_AX_ACH6_MIN_PG_SH 0
#define B_AX_ACH6_MIN_PG_MSK 0xfff
#define R_AX_ACH7_PAGE_CTRL 0x8A2C
#define B_AX_ACH7_GRP BIT(31)
#define B_AX_ACH7_MAX_PG_SH 16
#define B_AX_ACH7_MAX_PG_MSK 0xfff
#define B_AX_ACH7_MIN_PG_SH 0
#define B_AX_ACH7_MIN_PG_MSK 0xfff
#define R_AX_CH8_PAGE_CTRL 0x8A30
#define B_AX_CH8_GRP BIT(31)
#define B_AX_CH8_MAX_PG_SH 16
#define B_AX_CH8_MAX_PG_MSK 0xfff
#define B_AX_CH8_MIN_PG_SH 0
#define B_AX_CH8_MIN_PG_MSK 0xfff
#define R_AX_CH9_PAGE_CTRL 0x8A34
#define B_AX_CH9_GRP BIT(31)
#define B_AX_CH9_MAX_PG_SH 16
#define B_AX_CH9_MAX_PG_MSK 0xfff
#define B_AX_CH9_MIN_PG_SH 0
#define B_AX_CH9_MIN_PG_MSK 0xfff
#define R_AX_CH10_PAGE_CTRL 0x8A38
#define B_AX_CH10_GRP BIT(31)
#define B_AX_CH10_MAX_PG_SH 16
#define B_AX_CH10_MAX_PG_MSK 0xfff
#define B_AX_CH10_MIN_PG_SH 0
#define B_AX_CH10_MIN_PG_MSK 0xfff
#define R_AX_CH11_PAGE_CTRL 0x8A3C
#define B_AX_CH11_GRP BIT(31)
#define B_AX_CH11_MAX_PG_SH 16
#define B_AX_CH11_MAX_PG_MSK 0xfff
#define B_AX_CH11_MIN_PG_SH 0
#define B_AX_CH11_MIN_PG_MSK 0xfff
#define R_AX_ACH0_PAGE_INFO 0x8A50
#define B_AX_ACH0_AVAL_PG_SH 16
#define B_AX_ACH0_AVAL_PG_MSK 0xfff
#define B_AX_ACH0_USE_PG_SH 0
#define B_AX_ACH0_USE_PG_MSK 0xfff
#define R_AX_ACH1_PAGE_INFO 0x8A54
#define B_AX_ACH1_AVAL_PG_SH 16
#define B_AX_ACH1_AVAL_PG_MSK 0xfff
#define B_AX_ACH1_USE_PG_SH 0
#define B_AX_ACH1_USE_PG_MSK 0xfff
#define R_AX_ACH2_PAGE_INFO 0x8A58
#define B_AX_ACH2_AVAL_PG_SH 16
#define B_AX_ACH2_AVAL_PG_MSK 0xfff
#define B_AX_ACH2_USE_PG_SH 0
#define B_AX_ACH2_USE_PG_MSK 0xfff
#define R_AX_ACH3_PAGE_INFO 0x8A5C
#define B_AX_ACH3_AVAL_PG_SH 16
#define B_AX_ACH3_AVAL_PG_MSK 0xfff
#define B_AX_ACH3_USE_PG_SH 0
#define B_AX_ACH3_USE_PG_MSK 0xfff
#define R_AX_ACH4_PAGE_INFO 0x8A60
#define B_AX_ACH4_AVAL_PG_SH 16
#define B_AX_ACH4_AVAL_PG_MSK 0xfff
#define B_AX_ACH4_USE_PG_SH 0
#define B_AX_ACH4_USE_PG_MSK 0xfff
#define R_AX_ACH5_PAGE_INFO 0x8A64
#define B_AX_ACH5_AVAL_PG_SH 16
#define B_AX_ACH5_AVAL_PG_MSK 0xfff
#define B_AX_ACH5_USE_PG_SH 0
#define B_AX_ACH5_USE_PG_MSK 0xfff
#define R_AX_ACH6_PAGE_INFO 0x8A68
#define B_AX_ACH6_AVAL_PG_SH 16
#define B_AX_ACH6_AVAL_PG_MSK 0xfff
#define B_AX_ACH6_USE_PG_SH 0
#define B_AX_ACH6_USE_PG_MSK 0xfff
#define R_AX_ACH7_PAGE_INFO 0x8A6C
#define B_AX_ACH7_AVAL_PG_SH 16
#define B_AX_ACH7_AVAL_PG_MSK 0xfff
#define B_AX_ACH7_USE_PG_SH 0
#define B_AX_ACH7_USE_PG_MSK 0xfff
#define R_AX_CH8_PAGE_INFO 0x8A70
#define B_AX_CH8_AVAL_PG_SH 16
#define B_AX_CH8_AVAL_PG_MSK 0xfff
#define B_AX_CH8_USE_PG_SH 0
#define B_AX_CH8_USE_PG_MSK 0xfff
#define R_AX_CH9_PAGE_INFO 0x8A74
#define B_AX_CH9_AVAL_PG_SH 16
#define B_AX_CH9_AVAL_PG_MSK 0xfff
#define B_AX_CH9_USE_PG_SH 0
#define B_AX_CH9_USE_PG_MSK 0xfff
#define R_AX_CH10_PAGE_INFO 0x8A78
#define B_AX_CH10_AVAL_PG_SH 16
#define B_AX_CH10_AVAL_PG_MSK 0xfff
#define B_AX_CH10_USE_PG_SH 0
#define B_AX_CH10_USE_PG_MSK 0xfff
#define R_AX_CH11_PAGE_INFO 0x8A7C
#define B_AX_CH11_AVAL_PG_SH 16
#define B_AX_CH11_AVAL_PG_MSK 0xfff
#define B_AX_CH11_USE_PG_SH 0
#define B_AX_CH11_USE_PG_MSK 0xfff
#define R_AX_CH12_PAGE_INFO 0x8A80
#define B_AX_CH12_AVAL_PG_SH 16
#define B_AX_CH12_AVAL_PG_MSK 0xfff
#define R_AX_PUB_PAGE_INFO3 0x8A8C
#define B_AX_G1_AVAL_PG_SH 16
#define B_AX_G1_AVAL_PG_MSK 0x1fff
#define B_AX_G0_AVAL_PG_SH 0
#define B_AX_G0_AVAL_PG_MSK 0x1fff
#define R_AX_PUB_PAGE_CTRL1 0x8A90
#define B_AX_PUBPG_G1_SH 16
#define B_AX_PUBPG_G1_MSK 0x1fff
#define B_AX_PUBPG_G0_SH 0
#define B_AX_PUBPG_G0_MSK 0x1fff
#define R_AX_PUB_PAGE_CTRL2 0x8A94
#define B_AX_PUBPG_ALL_SH 0
#define B_AX_PUBPG_ALL_MSK 0x1fff
#define R_AX_PUB_PAGE_INFO1 0x8A98
#define B_AX_G1_USE_PG_SH 16
#define B_AX_G1_USE_PG_MSK 0x1fff
#define B_AX_G0_USE_PG_SH 0
#define B_AX_G0_USE_PG_MSK 0x1fff
#define R_AX_PUB_PAGE_INFO2 0x8A9C
#define B_AX_PUB_AVAL_PG_SH 0
#define B_AX_PUB_AVAL_PG_MSK 0x1fff
#define R_AX_WP_PAGE_CTRL1 0x8AA0
#define B_AX_PREC_PAGE_WP_CH811_SH 16
#define B_AX_PREC_PAGE_WP_CH811_MSK 0x1ff
#define B_AX_PREC_PAGE_WP_CH07_SH 0
#define B_AX_PREC_PAGE_WP_CH07_MSK 0x1ff
#define R_AX_WP_PAGE_CTRL2 0x8AA4
#define B_AX_WP_THRD_SH 0
#define B_AX_WP_THRD_MSK 0x1fff
#define R_AX_WP_PAGE_INFO1 0x8AA8
#define B_AX_WP_AVAL_PG_SH 16
#define B_AX_WP_AVAL_PG_MSK 0x1fff
#define R_AX_ACH0_THR 0x8AB0
#define B_AX_ACH0_INTRPT_EN BIT(31)
#define B_AX_ACH0_THR_WP_SH 16
#define B_AX_ACH0_THR_WP_MSK 0xfff
#define B_AX_ACH0_THR_WD_SH 0
#define B_AX_ACH0_THR_WD_MSK 0xfff
#define R_AX_ACH1_THR 0x8AB4
#define B_AX_ACH1_INTRPT_EN BIT(31)
#define B_AX_ACH1_THR_WP_SH 16
#define B_AX_ACH1_THR_WP_MSK 0xfff
#define B_AX_ACH1_THR_WD_SH 0
#define B_AX_ACH1_THR_WD_MSK 0xfff
#define R_AX_ACH2_THR 0x8AB8
#define B_AX_ACH2_INTRPT_EN BIT(31)
#define B_AX_ACH2_THR_WP_SH 16
#define B_AX_ACH2_THR_WP_MSK 0xfff
#define B_AX_ACH2_THR_WD_SH 0
#define B_AX_ACH2_THR_WD_MSK 0xfff
#define R_AX_ACH3_THR 0x8ABC
#define B_AX_ACH3_INTRPT_EN BIT(31)
#define B_AX_ACH3_THR_WP_SH 16
#define B_AX_ACH3_THR_WP_MSK 0xfff
#define B_AX_ACH3_THR_WD_SH 0
#define B_AX_ACH3_THR_WD_MSK 0xfff
#define R_AX_ACH4_THR 0x8AC0
#define B_AX_ACH4_INTRPT_EN BIT(31)
#define B_AX_ACH4_THR_WP_SH 16
#define B_AX_ACH4_THR_WP_MSK 0xfff
#define B_AX_ACH4_THR_WD_SH 0
#define B_AX_ACH4_THR_WD_MSK 0xfff
#define R_AX_ACH5_THR 0x8AC4
#define B_AX_ACH5_INTRPT_EN BIT(31)
#define B_AX_ACH5_THR_WP_SH 16
#define B_AX_ACH5_THR_WP_MSK 0xfff
#define B_AX_ACH5_THR_WD_SH 0
#define B_AX_ACH5_THR_WD_MSK 0xfff
#define R_AX_ACH6_THR 0x8AC8
#define B_AX_ACH6_INTRPT_EN BIT(31)
#define B_AX_ACH6_THR_WP_SH 16
#define B_AX_ACH6_THR_WP_MSK 0xfff
#define B_AX_ACH6_THR_WD_SH 0
#define B_AX_ACH6_THR_WD_MSK 0xfff
#define R_AX_ACH7_THR 0x8ACC
#define B_AX_ACH7_INTRPT_EN BIT(31)
#define B_AX_ACH7_THR_WP_SH 16
#define B_AX_ACH7_THR_WP_MSK 0xfff
#define B_AX_ACH7_THR_WD_SH 0
#define B_AX_ACH7_THR_WD_MSK 0xfff
#define R_AX_CH8_THR 0x8AD0
#define B_AX_CH8_INTRPT_EN BIT(31)
#define B_AX_CH8_THR_WP_SH 16
#define B_AX_CH8_THR_WP_MSK 0xfff
#define B_AX_CH8_THR_WD_SH 0
#define B_AX_CH8_THR_WD_MSK 0xfff
#define R_AX_CH9_THR 0x8AD4
#define B_AX_CH9_INTRPT_EN BIT(31)
#define B_AX_CH9_THR_WP_SH 16
#define B_AX_CH9_THR_WP_MSK 0xfff
#define B_AX_CH9_THR_WD_SH 0
#define B_AX_CH9_THR_WD_MSK 0xfff
#define R_AX_CH10_THR 0x8AD8
#define B_AX_CH10_INTRPT_EN BIT(31)
#define B_AX_CH10_THR_WP_SH 16
#define B_AX_CH10_THR_WP_MSK 0xfff
#define B_AX_CH10_THR_WD_SH 0
#define B_AX_CH10_THR_WD_MSK 0xfff
#define R_AX_CH11_THR 0x8ADC
#define B_AX_CH11_INTRPT_EN BIT(31)
#define B_AX_CH11_THR_WP_SH 16
#define B_AX_CH11_THR_WP_MSK 0xfff
#define B_AX_CH11_THR_WD_SH 0
#define B_AX_CH11_THR_WD_MSK 0xfff
//
// HCI FC 8852C
//
#define R_AX_HCI_FC_CTRL_V1 0x1700
#define R_AX_CH_PAGE_CTRL_V1 0x1704
#define R_AX_ACH011_INTRPT_STAT_V1 0x1708
#define R_AX_HCI_FC_ERR_FLAG_V1 0x170C
#define R_AX_ACH0_PAGE_CTRL_V1 0x1710
#define R_AX_ACH1_PAGE_CTRL_V1 0x1714
#define R_AX_ACH2_PAGE_CTRL_V1 0x1718
#define R_AX_ACH3_PAGE_CTRL_V1 0x171C
#define R_AX_ACH4_PAGE_CTRL_V1 0x1720
#define R_AX_ACH5_PAGE_CTRL_V1 0x1724
#define R_AX_ACH6_PAGE_CTRL_V1 0x1728
#define R_AX_ACH7_PAGE_CTRL_V1 0x172C
#define R_AX_CH8_PAGE_CTRL_V1 0x1730
#define R_AX_CH9_PAGE_CTRL_V1 0x1734
#define R_AX_CH10_PAGE_CTRL_V1 0x1738
#define R_AX_CH11_PAGE_CTRL_V1 0x173C
#define R_AX_ACH0_PAGE_INFO_V1 0x1750
#define R_AX_ACH1_PAGE_INFO_V1 0x1754
#define R_AX_ACH2_PAGE_INFO_V1 0x1758
#define R_AX_ACH3_PAGE_INFO_V1 0x175C
#define R_AX_ACH4_PAGE_INFO_V1 0x1760
#define R_AX_ACH5_PAGE_INFO_V1 0x1764
#define R_AX_ACH6_PAGE_INFO_V1 0x1768
#define R_AX_ACH7_PAGE_INFO_V1 0x176C
#define R_AX_CH8_PAGE_INFO_V1 0x1770
#define R_AX_CH9_PAGE_INFO_V1 0x1774
#define R_AX_CH10_PAGE_INFO_V1 0x1778
#define R_AX_CH11_PAGE_INFO_V1 0x177C
#define R_AX_CH12_PAGE_INFO_V1 0x1780
#define R_AX_PUB_PAGE_INFO3_V1 0x178C
#define R_AX_PUB_PAGE_CTRL1_V1 0x1790
#define R_AX_PUB_PAGE_CTRL2_V1 0x1794
#define R_AX_PUB_PAGE_INFO1_V1 0x1798
#define R_AX_PUB_PAGE_INFO2_V1 0x179C
#define R_AX_WP_PAGE_CTRL1_V1 0x17A0
#define R_AX_WP_PAGE_CTRL2_V1 0x17A4
#define R_AX_WP_PAGE_INFO1_V1 0x17A8
#define R_AX_ACH0_THR_V1 0x17B0
#define R_AX_ACH1_THR_V1 0x17B4
#define R_AX_ACH2_THR_V1 0x17B8
#define R_AX_ACH3_THR_V1 0x17BC
#define R_AX_ACH4_THR_V1 0x17C0
#define R_AX_ACH5_THR_V1 0x17C4
#define R_AX_ACH6_THR_V1 0x17C8
#define R_AX_ACH7_THR_V1 0x17CC
#define R_AX_CH8_THR_V1 0x17D0
#define R_AX_CH9_THR_V1 0x17D4
#define R_AX_CH10_THR_V1 0x17D8
#define R_AX_CH11_THR_V1 0x17DC
//
// WDE_DLE
//
#define R_AX_WDE_PKTBUF_CFG 0x8C08
#define B_AX_WDE_FREE_PAGE_NUM_SH 16
#define B_AX_WDE_FREE_PAGE_NUM_MSK 0x1fff
#define B_AX_WDE_START_BOUND_SH 8
#define B_AX_WDE_START_BOUND_MSK 0x3f
#define B_AX_WDE_PAGE_SEL_SH 0
#define B_AX_WDE_PAGE_SEL_MSK 0x3
#define R_AX_WDE_ERR_FLAG_CFG 0x8C34
#define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2)
#define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1)
#define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
#define R_AX_WDE_ERR_IMR 0x8C38
#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
#define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
#define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5)
#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
#define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
#define R_AX_WDE_ERR_ISR 0x8C3C
#define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26)
#define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25)
#define B_AX_WDE_DATCHN_ARBT_ERR BIT(24)
#define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19)
#define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18)
#define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17)
#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16)
#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15)
#define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14)
#define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13)
#define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12)
#define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7)
#define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6)
#define B_AX_WDE_GETNPG_STRPG_ERR BIT(5)
#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4)
#define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3)
#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2)
#define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1)
#define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0)
#define R_AX_WDE_QTA0_CFG 0x8C40
#define B_AX_WDE_Q0_MAX_SIZE_SH 16
#define B_AX_WDE_Q0_MAX_SIZE_MSK 0xfff
#define B_AX_WDE_Q0_MIN_SIZE_SH 0
#define B_AX_WDE_Q0_MIN_SIZE_MSK 0xfff
#define R_AX_WDE_QTA1_CFG 0x8C44
#define B_AX_WDE_Q1_MAX_SIZE_SH 16
#define B_AX_WDE_Q1_MAX_SIZE_MSK 0xfff
#define B_AX_WDE_Q1_MIN_SIZE_SH 0
#define B_AX_WDE_Q1_MIN_SIZE_MSK 0xfff
#define R_AX_WDE_QTA2_CFG 0x8C48
#define B_AX_WDE_Q2_MAX_SIZE_SH 16
#define B_AX_WDE_Q2_MAX_SIZE_MSK 0xfff
#define B_AX_WDE_Q2_MIN_SIZE_SH 0
#define B_AX_WDE_Q2_MIN_SIZE_MSK 0xfff
#define R_AX_WDE_QTA3_CFG 0x8C4C
#define B_AX_WDE_Q3_MAX_SIZE_SH 16
#define B_AX_WDE_Q3_MAX_SIZE_MSK 0xfff
#define B_AX_WDE_Q3_MIN_SIZE_SH 0
#define B_AX_WDE_Q3_MIN_SIZE_MSK 0xfff
#define R_AX_WDE_QTA4_CFG 0x8C50
#define B_AX_WDE_Q4_MAX_SIZE_SH 16
#define B_AX_WDE_Q4_MAX_SIZE_MSK 0xfff
#define B_AX_WDE_Q4_MIN_SIZE_SH 0
#define B_AX_WDE_Q4_MIN_SIZE_MSK 0xfff
#define R_AX_WDE_QTA5_CFG 0x8C54
#define R_AX_WDE_QTA6_CFG 0x8C58
#define R_AX_WDE_QTA7_CFG 0x8C5C
#define R_AX_WDE_QTA8_CFG 0x8C60
#define R_AX_WDE_QTA9_CFG 0x8C64
#define R_AX_WDE_QTA10_CFG 0x8C68
#define R_AX_WDE_QTA11_CFG 0x8C6C
#define R_AX_WDE_QTA12_CFG 0x8C70
#define R_AX_WDE_QTA13_CFG 0x8C74
#define R_AX_WDE_QTA14_CFG 0x8C78
#define R_AX_WDE_QTA15_CFG 0x8C7C
#define R_AX_WDE_INI_STATUS 0x8D00
#define B_AX_WDE_Q_MGN_INI_RDY BIT(1)
#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0)
#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10
#define B_AX_WDE_DFI_ACTIVE BIT(31)
#define B_AX_WDE_DFI_TRGSEL_SH 16
#define B_AX_WDE_DFI_TRGSEL_MSK 0xf
#define B_AX_WDE_DFI_ADDR_SH 0
#define B_AX_WDE_DFI_ADDR_MSK 0xffff
#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14
#define B_AX_WDE_DFI_DATA_SH 0
#define B_AX_WDE_DFI_DATA_MSK 0xffffffffL
#define R_AX_WDE_DBG_CTL 0x8D18
#define B_AX_WDE_DBG1_SEL_SH 8
#define B_AX_WDE_DBG1_SEL_MSK 0xff
#define B_AX_WDE_DBG0_SEL_SH 0
#define B_AX_WDE_DBG0_SEL_MSK 0xff
#define R_AX_DBG_OUT 0x8D1C
#define B_AX_WDE_DBG1_OUT_SH 16
#define B_AX_WDE_DBG1_OUT_MSK 0xffff
#define B_AX_WDE_DBG0_OUT_SH 0
#define B_AX_WDE_DBG0_OUT_MSK 0xffff
#define R_AX_WDE_Q_STATUS_CFG 0x8D80
#define B_AX_WDE_Q_STATUS_SEL_SH 0
#define B_AX_WDE_Q_STATUS_SEL_MSK 0x7
#define R_AX_WDE_Q_STATUS_VAL 0x8D84
#define B_AX_WDE_Q_STATUS_VAL_SH 0
#define B_AX_WDE_Q_STATUS_VAL_MSK 0xffffffffL
//
// PLE_DLE
//
#define R_AX_PLE_PKTBUF_CFG 0x9008
#define B_AX_PLE_FREE_PAGE_NUM_SH 16
#define B_AX_PLE_FREE_PAGE_NUM_MSK 0x1fff
#define B_AX_PLE_START_BOUND_SH 8
#define B_AX_PLE_START_BOUND_MSK 0x3f
#define B_AX_PLE_PAGE_SEL_SH 0
#define B_AX_PLE_PAGE_SEL_MSK 0x3
#define R_AX_PLE_ERR_FLAG_CFG 0x9034
#define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2)
#define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1)
#define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
#define R_AX_PLE_ERR_IMR 0x9038
#define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
#define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
#define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
#define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
#define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
#define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
#define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
#define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
#define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5)
#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
#define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
#define R_AX_PLE_ERR_FLAG_ISR 0x903C
#define B_AX_PLE_DATCHN_FRZTO_ERR BIT(26)
#define B_AX_PLE_DATCHN_NULLPG_ERR BIT(25)
#define B_AX_PLE_DATCHN_ARBT_ERR BIT(24)
#define B_AX_PLE_QUEMGN_FRZTO_ERR BIT(19)
#define B_AX_PLE_NXTPKTLL_AD_ERR BIT(18)
#define B_AX_PLE_PREPKTLLT_AD_ERR BIT(17)
#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR BIT(16)
#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR BIT(15)
#define B_AX_PLE_QUE_SRCQUEID_ERR BIT(14)
#define B_AX_PLE_QUE_DSTQUEID_ERR BIT(13)
#define B_AX_PLE_QUE_CMDTYPE_ERR BIT(12)
#define B_AX_PLE_BUFMGN_FRZTO_ERR BIT(7)
#define B_AX_PLE_GETNPG_PGOFST_ERR BIT(6)
#define B_AX_PLE_GETNPG_STRPG_ERR BIT(5)
#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR BIT(4)
#define B_AX_PLE_BUFRTN_SIZE_ERR BIT(3)
#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR BIT(2)
#define B_AX_PLE_BUFREQ_UNAVAL_ERR BIT(1)
#define B_AX_PLE_BUFREQ_QTAID_ERR BIT(0)
#define R_AX_PLE_QTA0_CFG 0x9040
#define B_AX_PLE_Q0_MAX_SIZE_SH 16
#define B_AX_PLE_Q0_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q0_MIN_SIZE_SH 0
#define B_AX_PLE_Q0_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA1_CFG 0x9044
#define B_AX_PLE_Q1_MAX_SIZE_SH 16
#define B_AX_PLE_Q1_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q1_MIN_SIZE_SH 0
#define B_AX_PLE_Q1_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA2_CFG 0x9048
#define B_AX_PLE_Q2_MAX_SIZE_SH 16
#define B_AX_PLE_Q2_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q2_MIN_SIZE_SH 0
#define B_AX_PLE_Q2_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA3_CFG 0x904C
#define B_AX_PLE_Q3_MAX_SIZE_SH 16
#define B_AX_PLE_Q3_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q3_MIN_SIZE_SH 0
#define B_AX_PLE_Q3_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA4_CFG 0x9050
#define B_AX_PLE_Q4_MAX_SIZE_SH 16
#define B_AX_PLE_Q4_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q4_MIN_SIZE_SH 0
#define B_AX_PLE_Q4_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA5_CFG 0x9054
#define B_AX_PLE_Q5_MAX_SIZE_SH 16
#define B_AX_PLE_Q5_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q5_MIN_SIZE_SH 0
#define B_AX_PLE_Q5_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA6_CFG 0x9058
#define B_AX_PLE_Q6_MAX_SIZE_SH 16
#define B_AX_PLE_Q6_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q6_MIN_SIZE_SH 0
#define B_AX_PLE_Q6_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA7_CFG 0x905C
#define B_AX_PLE_Q7_MAX_SIZE_SH 16
#define B_AX_PLE_Q7_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q7_MIN_SIZE_SH 0
#define B_AX_PLE_Q7_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA8_CFG 0x9060
#define B_AX_PLE_Q8_MAX_SIZE_SH 16
#define B_AX_PLE_Q8_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q8_MIN_SIZE_SH 0
#define B_AX_PLE_Q8_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA9_CFG 0x9064
#define B_AX_PLE_Q9_MAX_SIZE_SH 16
#define B_AX_PLE_Q9_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q9_MIN_SIZE_SH 0
#define B_AX_PLE_Q9_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA10_CFG 0x9068
#define B_AX_PLE_Q10_MAX_SIZE_SH 16
#define B_AX_PLE_Q10_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q10_MIN_SIZE_SH 0
#define B_AX_PLE_Q10_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA11_CFG 0x906C
#define B_AX_PLE_Q11_MAX_SIZE_SH 16
#define B_AX_PLE_Q11_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q11_MIN_SIZE_SH 0
#define B_AX_PLE_Q11_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA12_CFG 0x9070
#define B_AX_PLE_Q12_MAX_SIZE_SH 16
#define B_AX_PLE_Q12_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q12_MIN_SIZE_SH 0
#define B_AX_PLE_Q12_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA13_CFG 0x9074
#define B_AX_PLE_Q13_MAX_SIZE_SH 16
#define B_AX_PLE_Q13_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q13_MIN_SIZE_SH 0
#define B_AX_PLE_Q13_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA14_CFG 0x9078
#define B_AX_PLE_Q14_MAX_SIZE_SH 16
#define B_AX_PLE_Q14_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q14_MIN_SIZE_SH 0
#define B_AX_PLE_Q14_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_QTA15_CFG 0x907C
#define B_AX_PLE_Q15_MAX_SIZE_SH 16
#define B_AX_PLE_Q15_MAX_SIZE_MSK 0xfff
#define B_AX_PLE_Q15_MIN_SIZE_SH 0
#define B_AX_PLE_Q15_MIN_SIZE_MSK 0xfff
#define R_AX_PLE_INI_STATUS 0x9100
#define B_AX_PLE_Q_MGN_INI_RDY BIT(1)
#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0)
#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110
#define B_AX_PLE_DFI_ACTIVE BIT(31)
#define B_AX_PLE_DFI_TRGSEL_SH 16
#define B_AX_PLE_DFI_TRGSEL_MSK 0xf
#define B_AX_PLE_DFI_ADDR_SH 0
#define B_AX_PLE_DFI_ADDR_MSK 0xffff
#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114
#define B_AX_PLE_DFI_DATA_SH 0
#define B_AX_PLE_DFI_DATA_MSK 0xffffffffL
#define R_AX_PLE_DBG_CTL 0x9118
#define B_AX_PLE_DBG1_SEL_SH 8
#define B_AX_PLE_DBG1_SEL_MSK 0xff
#define B_AX_PLE_DBG0_SEL_SH 0
#define B_AX_PLE_DBG0_SEL_MSK 0xff
#define R_AX_PLE_DBG_OUT 0x911C
#define B_AX_PLE_DBG1_OUT_SH 16
#define B_AX_PLE_DBG1_OUT_MSK 0xffff
#define B_AX_PLE_DBG0_OUT_SH 0
#define B_AX_PLE_DBG0_OUT_MSK 0xffff
//
// WDRLS
//
#define R_AX_WDRLS_CFG 0x9408
#define B_AX_RLSRPT_BUFREQ_TO_SH 8
#define B_AX_RLSRPT_BUFREQ_TO_MSK 0xff
#define B_AX_WDRLS_MODE_SH 0
#define B_AX_WDRLS_MODE_MSK 0x3
#define R_AX_RLSRPT0_CFG0 0x9410
#define B_AX_RLSRPT0_FLTR_MAP_SH 24
#define B_AX_RLSRPT0_FLTR_MAP_MSK 0xf
#define B_AX_RLSRPT0_PKTTYPE_SH 16
#define B_AX_RLSRPT0_PKTTYPE_MSK 0xf
#define B_AX_RLSRPT0_PID_SH 8
#define B_AX_RLSRPT0_PID_MSK 0x7
#define B_AX_RLSRPT0_QID_SH 0
#define B_AX_RLSRPT0_QID_MSK 0x3f
#define R_AX_RLSRPT0_CFG1 0x9414
#define B_AX_RLSRPT0_TO_SH 16
#define B_AX_RLSRPT0_TO_MSK 0xff
#define B_AX_RLSRPT0_AGGNUM_SH 0
#define B_AX_RLSRPT0_AGGNUM_MSK 0xff
#define R_AX_RLSRPT1_CFG0 0x9420
#define B_AX_RLSRPT1_FLTR_MAP_SH 24
#define B_AX_RLSRPT1_FLTR_MAP_MSK 0xf
#define B_AX_RLSRPT1_PKTTYPE_SH 16
#define B_AX_RLSRPT1_PKTTYPE_MSK 0xf
#define B_AX_RLSRPT1_PID_SH 8
#define B_AX_RLSRPT1_PID_MSK 0x7
#define B_AX_RLSRPT1_QID_SH 0
#define B_AX_RLSRPT1_QID_MSK 0x3f
#define R_AX_RLSRPT1_CFG1 0x9424
#define B_AX_RLSRPT1_TO_SH 16
#define B_AX_RLSRPT1_TO_MSK 0xff
#define B_AX_RLSRPT1_AGGNUM_SH 0
#define B_AX_RLSRPT1_AGGNUM_MSK 0xff
#define R_AX_WDRLS_ERR_IMR 0x9430
#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
#define R_AX_WDRLS_ERR_ISR 0x9434
#define B_AX_WDRLS_RPT1_FRZTO_ERR BIT(13)
#define B_AX_WDRLS_RPT1_AGGNUM_ERR BIT(12)
#define B_AX_WDRLS_RPT0_FRZTO_ERR BIT(9)
#define B_AX_WDRLS_RPT0_AGGNUM0_ERR BIT(8)
#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR BIT(5)
#define B_AX_WDRLS_PLEBREQ_TO_ERR BIT(4)
#define B_AX_WDRLS_CTL_FRZTO_ERR BIT(2)
#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR BIT(1)
#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR BIT(0)
#define R_AX_DBG_CTL_WDRLS 0x9438
#define B_AX_DBG1_SEL_SH 8
#define B_AX_DBG1_SEL_MSK 0xff
#define B_AX_DBG0_SEL_SH 0
#define B_AX_DBG0_SEL_MSK 0xff
#define R_AX_DBG_OUT_WDRLS 0x943C
#define B_AX_DBG1_OUT_SH 16
#define B_AX_DBG1_OUT_MSK 0xffff
#define B_AX_DBG0_OUT_SH 0
#define B_AX_DBG0_OUT_MSK 0xffff
//
// BBRPT
//
#define R_AX_COM_CFG 0x9600
#define R_AX_BB_COEX_CFG 0x9604
#define B_AX_DFS_THR_SH 8
#define B_AX_DFS_THR_MSK 0xf
#define B_AX_BBRPT_COEX_EN BIT(0)
#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C
#define B_AX_BBRPT_COM__NULL_PLPKTID_ERR BIT(16)
#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
#define R_AX_CH_INFO 0x9620
#define B_AX_CH_INFO_QID_SH 24
#define B_AX_CH_INFO_QID_MSK 0x3f
#define B_AX_CH_INFO_PRTID_SH 20
#define B_AX_CH_INFO_PRTID_MSK 0x7
#define B_AX_CH_INFO_REQ_SH 18
#define B_AX_CH_INFO_REQ_MSK 0x3
#define B_AX_CH_INFO_SEG_SH 16
#define B_AX_CH_INFO_SEG_MSK 0x3
#define B_AX_CH_INFO_INTVL_SH 12
#define B_AX_CH_INFO_INTVL_MSK 0xf
#define B_AX_GET_CH_INFO_TO_SH 9
#define B_AX_GET_CH_INFO_TO_MSK 0x7
#define B_AX_CH_INFO_PHY BIT(8)
#define B_AX_CH_INFO_BUF_SH 6
#define B_AX_CH_INFO_BUF_MSK 0x3
#define B_AX_CH_INFO_STOP BIT(5)
#define B_AX_CH_INFO_STOP_REQ BIT(4)
#define B_AX_CH_INFO_ON BIT(3)
#define B_AX_CH_INFO_EN BIT(0)
#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C
#define B_AX_BBPRT_CHIF_TO_ERR BIT(23)
#define B_AX_BBPRT_CHIF_NULL_ERR BIT(22)
#define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21)
#define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20)
#define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19)
#define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18)
#define B_AX_BBPRT_CHIF_OVF_ERR BIT(17)
#define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16)
#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
#define R_AX_DFS_CFG0 0x9630
#define B_AX_DFS_QID_SH 24
#define B_AX_DFS_QID_MSK 0x3f
#define B_AX_DFS_PRTID_SH 20
#define B_AX_DFS_PRTID_MSK 0x7
#define B_AX_DFS_TIME_TH_SH 10
#define B_AX_DFS_TIME_TH_MSK 0x3
#define B_AX_DFS_NUM_TH_SH 8
#define B_AX_DFS_NUM_TH_MSK 0x3
#define B_AX_DFS_BUF_SH 6
#define B_AX_DFS_BUF_MSK 0x3
#define B_AX_DFS_IN_STOP BIT(5)
#define B_AX_STOP_DFS BIT(4)
#define B_AX_DFS_RPT_EN BIT(0)
#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C
#define B_AX_BBRPT_DFS_TO_ERR BIT(16)
#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
#define R_AX_LA_CFG 0x9660
#define B_AX_LA_TRIG_TIME_VAL_SH 24
#define B_AX_LA_TRIG_TIME_VAL_MSK 0x7f
#define B_AX_LA_TRIG_TU_SEL_SH 20
#define B_AX_LA_TRIG_TU_SEL_MSK 0xf
#define B_AX_LA_BUF_SEL_SH 16
#define B_AX_LA_BUF_SEL_MSK 0xf
#define B_AX_LA_BUF_BNDY_SH 8
#define B_AX_LA_BUF_BNDY_MSK 0x3f
#define B_AX_LA_TO_VAL_SH 6
#define B_AX_LA_TO_VAL_MSK 0x3
#define B_AX_LA_TO_EN BIT(5)
#define B_AX_LA_RESTART_EN BIT(4)
#define B_AX_LA_TRIG_START BIT(3)
#define B_AX_LA_FEN BIT(0)
#define R_AX_LA_STATUS 0x9664
#define B_AX_LA_SW_FSMST_SH 17
#define B_AX_LA_SW_FSMST_MSK 0x7
#define B_AX_LA_BUF_RNDUP BIT(16)
#define B_AX_LA_BUF_WPTR_SH 0
#define B_AX_LA_BUF_WPTR_MSK 0xFFFF
#define R_AX_LA_ERRFLAG 0x966C
#define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16)
#define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
//
// CPUIO
//
#define R_AX_WD_BUF_REQ 0x9800
#define B_AX_WD_BUF_REQ_EXEC BIT(31)
#define B_AX_WD_BUF_REQ_QUOTA_ID_SH 16
#define B_AX_WD_BUF_REQ_QUOTA_ID_MSK 0xff
#define B_AX_WD_BUF_REQ_LEN_SH 0
#define B_AX_WD_BUF_REQ_LEN_MSK 0xffff
#define R_AX_WD_BUF_STATUS 0x9804
#define B_AX_WD_BUF_STAT_DONE BIT(31)
#define B_AX_WD_BUF_STAT_PKTID_SH 0
#define B_AX_WD_BUF_STAT_PKTID_MSK 0xfff
#define R_AX_WD_QUOTA_STATUS 0x9808
#define R_AX_WD_CPUQ_OP_0 0x9810
#define B_AX_WD_CPUQ_OP_EXEC BIT(31)
#define B_AX_WD_CPUQ_OP_CMD_TYPE_SH 24
#define B_AX_WD_CPUQ_OP_CMD_TYPE_MSK 0xf
#define B_AX_WD_CPUQ_OP_MACID_SH 16
#define B_AX_WD_CPUQ_OP_MACID_MSK 0xff
#define B_AX_WD_CPUQ_OP_PKTNUM_SH 0
#define B_AX_WD_CPUQ_OP_PKTNUM_MSK 0xff
#define R_AX_WD_CPUQ_OP_1 0x9814
#define B_AX_WD_CPUQ_OP_SRC_PID_SH 22
#define B_AX_WD_CPUQ_OP_SRC_PID_MSK 0x7
#define B_AX_WD_CPUQ_OP_SRC_QID_SH 16
#define B_AX_WD_CPUQ_OP_SRC_QID_MSK 0x3f
#define B_AX_WD_CPUQ_OP_DST_PID_SH 6
#define B_AX_WD_CPUQ_OP_DST_PID_MSK 0x7
#define B_AX_WD_CPUQ_OP_DST_QID_SH 0
#define B_AX_WD_CPUQ_OP_DST_QID_MSK 0x3f
#define R_AX_WD_CPUQ_OP_2 0x9818
#define B_AX_WD_CPUQ_OP_STRT_PKTID_SH 16
#define B_AX_WD_CPUQ_OP_STRT_PKTID_MSK 0xfff
#define B_AX_WD_CPUQ_OP_END_PKTID_SH 0
#define B_AX_WD_CPUQ_OP_END_PKTID_MSK 0xfff
#define R_AX_WD_CPUQ_OP_STATUS 0x981C
#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
#define B_AX_WD_CPUQ_OP_PKTID_SH 0
#define B_AX_WD_CPUQ_OP_PKTID_MSK 0xfff
#define R_AX_PL_BUF_REQ 0x9820
#define B_AX_PL_BUF_REQ_EXEC BIT(31)
#define B_AX_PL_BUF_REQ_QUOTA_ID_SH 16
#define B_AX_PL_BUF_REQ_QUOTA_ID_MSK 0xf
#define B_AX_PL_BUF_REQ_LEN_SH 0
#define B_AX_PL_BUF_REQ_LEN_MSK 0xffff
#define R_AX_PL_BUF_STATUS 0x9824
#define B_AX_PL_BUF_STAT_DONE BIT(31)
#define B_AX_PL_BUF_STAT_PKTID_SH 0
#define B_AX_PL_BUF_STAT_PKTID_MSK 0xfff
#define R_AX_PL_QUOTA_STATUS 0x9828
#define R_AX_PL_CPUQ_OP_0 0x9830
#define B_AX_PL_CPUQ_OP_EXEC BIT(31)
#define B_AX_PL_CPUQ_OP_CMD_TYPE_SH 24
#define B_AX_PL_CPUQ_OP_CMD_TYPE_MSK 0xf
#define B_AX_PL_CPUQ_OP_MACID_SH 16
#define B_AX_PL_CPUQ_OP_MACID_MSK 0xff
#define B_AX_PL_CPUQ_OP_PKTNUM_SH 0
#define B_AX_PL_CPUQ_OP_PKTNUM_MSK 0xff
#define R_AX_PL_CPUQ_OP_1 0x9834
#define B_AX_PL_CPUQ_OP_SRC_PID_SH 22
#define B_AX_PL_CPUQ_OP_SRC_PID_MSK 0x7
#define B_AX_PL_CPUQ_OP_SRC_QID_SH 16
#define B_AX_PL_CPUQ_OP_SRC_QID_MSK 0x3f
#define B_AX_PL_CPUQ_OP_DST_PID_SH 6
#define B_AX_PL_CPUQ_OP_DST_PID_MSK 0x7
#define B_AX_PL_CPUQ_OP_DST_QID_SH 0
#define B_AX_PL_CPUQ_OP_DST_QID_MSK 0x3f
#define R_AX_PL_CPUQ_OP_2 0x9838
#define B_AX_PL_CPUQ_OP_STRT_PKTID_SH 16
#define B_AX_PL_CPUQ_OP_STRT_PKTID_MSK 0xfff
#define B_AX_PL_CPUQ_OP_END_PKTID_SH 0
#define B_AX_PL_CPUQ_OP_END_PKTID_MSK 0xfff
#define R_AX_PL_CPUQ_OP_STATUS 0x983C
#define B_AX_PL_CPUQ_OP_STAT_DONE BIT(31)
#define B_AX_PL_CPUQ_OP_PKTID_SH 0
#define B_AX_PL_CPUQ_OP_PKTID_MSK 0xfff
#define R_AX_CPUIO_ERR_IMR 0x9840
#define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12)
#define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8)
#define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4)
#define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0)
#define R_AX_CPUIO_ERR_ISR 0x9844
#define B_AX_PLEQUE_OP_ERR BIT(12)
#define B_AX_PLEBUF_OP_ERR BIT(8)
#define B_AX_ERR_WDEQUE_OP_ERR BIT(4)
#define B_AX_ERR_WDEBUF_OP_ERR BIT(0)
#define R_AX_SEC_ERR_IMR_ISR 0x991C
#define B_AX_SEC_TRX_TIMEOUT_INT_EN BIT(3)
#define B_AX_SEC_RX_TIMEOUT_ISR BIT(2)
#define B_AX_SEC_TX_TIMEOUT_ISR BIT(1)
//
// PKTIN
//
#define R_AX_PKTIN_SETTING 0x9A00
#define B_AX_WD_ADDR_INFO_LENGTH BIT(1)
#define B_AX_PKTIN_CLK_GATING_DIS BIT(0)
#define R_AX_HWAMSDU_CTRL 0x9A04
#define B_AX_MAX_AMSDU_NUM_SH 3
#define B_AX_MAX_AMSDU_NUM_MSK 0x3
#define B_AX_SINGLE_AMSDU BIT(2)
#define B_AX_HWAMSDU_EN BIT(0)
#define R_AX_HWAMSDU_STATUS 0x9A08
#define B_AX_AMSDU_PKT_SIZE_ERR BIT(31)
#define B_AX_AMSDU_EN_ERR BIT(30)
#define B_AX_AMSDU_ADDR_INFO_ERR BIT(29)
#define R_AX_HW_SEQ_0_1 0x9A0C
#define B_AX_HW_SEQ1_SH 16
#define B_AX_HW_SEQ1_MSK 0xfff
#define B_AX_HW_SEQ0_SH 0
#define B_AX_HW_SEQ0_MSK 0xfff
#define R_AX_HW_SEQ_2_3 0x9A10
#define B_AX_HW_SEQ3_SH 16
#define B_AX_HW_SEQ3_MSK 0xfff
#define B_AX_HW_SEQ2_SH 0
#define B_AX_HW_SEQ2_MSK 0xfff
#define R_AX_TXPKTIN_CTRL 0x9A14
#define B_AX_C1P4_TXPKTIN_STS BIT(25)
#define B_AX_C1P3_TXPKTIN_STS BIT(24)
#define B_AX_C1P2_TXPKTIN_STS BIT(23)
#define B_AX_C1P1_TXPKTIN_STS BIT(22)
#define B_AX_C1P0_TXPKTIN_STS BIT(21)
#define B_AX_C0P4_TXPKTIN_STS BIT(20)
#define B_AX_C0P3_TXPKTIN_STS BIT(19)
#define B_AX_C0P2_TXPKTIN_STS BIT(18)
#define B_AX_C0P1_TXPKTIN_STS BIT(17)
#define B_AX_C0P0_TXPKTIN_STS BIT(16)
#define B_AX_TXPKTIN_CTRL_EN BIT(15)
#define B_AX_C1P4_TXPKTIN_EN BIT(9)
#define B_AX_C1P3_TXPKTIN_EN BIT(8)
#define B_AX_C1P2_TXPKTIN_EN BIT(7)
#define B_AX_C1P1_TXPKTIN_EN BIT(6)
#define B_AX_C1P0_TXPKTIN_EN BIT(5)
#define B_AX_C0P4_TXPKTIN_EN BIT(4)
#define B_AX_C0P3_TXPKTIN_EN BIT(3)
#define B_AX_C0P2_TXPKTIN_EN BIT(2)
#define B_AX_C0P1_TXPKTIN_EN BIT(1)
#define B_AX_C0P0_TXPKTIN_EN BIT(0)
#define R_AX_TXPKTIN_DBG_SEL 0x9A18
#define B_AX_TXPKTIN_DBG_SEL_SH 0
#define B_AX_TXPKTIN_DBG_SEL_MSK 0xf
#define R_AX_PKTIN_ERR_IMR 0x9A20
#define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0)
#define R_AX_PKTIN_ERR_ISR 0x9A24
#define B_AX_PKTIN_GETPKTID_ERR_ISR BIT(0)
//
// MPDU_Processor_1
//
#define R_AX_HDR_SHCUT_SETTING 0x9B00
#define B_AX_MAC_MPDU_PROC_EN BIT(2)
#define B_AX_SHCUT_LLC_WR_LOCK BIT(1)
#define B_AX_SHCUT_PARSE_DASA BIT(0)
#define R_AX_SHCUT_LLC_ETH_TYPE0 0x9B04
#define B_AX_SHUT_ETH_TYPE1_SH 16
#define B_AX_SHUT_ETH_TYPE1_MSK 0xffff
#define B_AX_SHUT_ETH_TYPE0_SH 0
#define B_AX_SHUT_ETH_TYPE0_MSK 0xffff
#define R_AX_SHCUT_LLC_ETH_TYPE1 0x9B08
#define B_AX_SHUT_ETH_TYPE2_SH 0
#define B_AX_SHUT_ETH_TYPE2_MSK 0xffff
#define R_AX_SHCUT_LLC_OUI0 0x9B0C
#define B_AX_SHUT_ENABLE_OUI0 BIT(24)
#define B_AX_SHUT_ETH_OUI0_SH 0
#define B_AX_SHUT_ETH_OUI0_MSK 0xffffff
#define R_AX_SHCUT_LLC_OUI1 0x9B10
#define B_AX_SHUT_ENABLE_OUI1 BIT(24)
#define B_AX_SHUT_ETH_OUI1_SH 0
#define B_AX_SHUT_ETH_OUI1_MSK 0xffffff
#define R_AX_SHCUT_LLC_OUI2 0x9B14
#define B_AX_SHUT_ENABLE_OUI2 BIT(24)
#define B_AX_SHUT_ETH_OUI2_SH 0
#define B_AX_SHUT_ETH_OUI2_MSK 0xffffff
#define R_AX_SHCUT_LLC_OUI3 0x9B18
#define B_AX_SHUT_ENABLE_OUI3 BIT(24)
#define B_AX_SHUT_ETH_OUI3_SH 0
#define B_AX_SHUT_ETH_OUI3_MSK 0xffffff
#define R_AX_TX_PTK_CNT 0x9BEC
#define B_AX_TX_PTKOUT_CNT_SH 16
#define B_AX_TX_PTKOUT_CNT_MSK 0xffff
#define B_AX_TX_PKTIN_CNT_SH 0
#define B_AX_TX_PKTIN_CNT_MSK 0xffff
#define R_AX_MPDU_TX_ERR_ISR 0x9BF0
#define B_AX_TX_HDR3_SIZE_ERR BIT(5)
#define B_AX_TX_OFFSET_ERR BIT(4)
#define B_AX_TX_MPDU_SIZE_ZERO_ERR BIT(3)
#define B_AX_TX_NXT_ERRPKTID_ERR BIT(2)
#define B_AX_TX_GET_ERRPKTID_ERR BIT(1)
#define R_AX_MPDU_TX_ERR_IMR 0x9BF4
#define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5)
#define B_AX_TX_OFFSET_ERR_INT_EN BIT(4)
#define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3)
#define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2)
#define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1)
#define R_AX_MPDU_TX_DBG 0x9BFC
#define B_AX_MPDU_TX_DBGEN BIT(8)
#define B_AX_MPDU_TX_DLAST BIT(0)
//
// MPDU_Processor_2
//
#define R_AX_MPDU_PROC 0x9C00
#define B_AX_A_ICV_ERR BIT(1)
#define B_AX_APPEND_FCS BIT(0)
#define R_AX_ACTION_FWD0 0x9C04
#define B_AX_FWD_VHT_CBFM_SH 24
#define B_AX_FWD_VHT_CBFM_MSK 0x3
#define B_AX_FWD_HT_CBFM_SH 22
#define B_AX_FWD_HT_CBFM_MSK 0x3
#define B_AX_FWD_CSI_SH 20
#define B_AX_FWD_CSI_MSK 0x3
#define B_AX_FWD_OP_MODE_SH 18
#define B_AX_FWD_OP_MODE_MSK 0x3
#define B_AX_FWD_GID_MGNT_SH 16
#define B_AX_FWD_GID_MGNT_MSK 0x3
#define B_AX_FWD_NCW_SH 14
#define B_AX_FWD_NCW_MSK 0x3
#define B_AX_FWD_DELBA_SH 12
#define B_AX_FWD_DELBA_MSK 0x3
#define B_AX_FWD_ADDBA_RES_SH 10
#define B_AX_FWD_ADDBA_RES_MSK 0x3
#define B_AX_FWD_ADDBA_REQ_SH 8
#define B_AX_FWD_ADDBA_REQ_MSK 0x3
#define B_AX_FWD_DELTS_SH 6
#define B_AX_FWD_DELTS_MSK 0x3
#define B_AX_FWD_ADDTS_RES_SH 4
#define B_AX_FWD_ADDTS_RES_MSK 0x3
#define B_AX_FWD_ADDTS_REQ_SH 2
#define B_AX_FWD_ADDTS_REQ_MSK 0x3
#define B_AX_FWD_CSA_SH 0
#define B_AX_FWD_CSA_MSK 0x3
#define R_AX_ACTION_FWD1 0x9C08
#define B_AX_FWD_ACTN_CTRL3_SH 6
#define B_AX_FWD_ACTN_CTRL3_MSK 0x3
#define B_AX_FWD_ACTN_CTRL2_SH 4
#define B_AX_FWD_ACTN_CTRL2_MSK 0x3
#define B_AX_FWD_ACTN_CTRL1_SH 2
#define B_AX_FWD_ACTN_CTRL1_MSK 0x3
#define B_AX_FWD_ACTN_CTRL0_SH 0
#define B_AX_FWD_ACTN_CTRL0_MSK 0x3
#define R_AX_ACTION_FWD_CTRL0 0x9C0C
#define B_AX_FWD_ACTN_ACTN0_SH 8
#define B_AX_FWD_ACTN_ACTN0_MSK 0xff
#define B_AX_FWD_ACTN_CAT0_SH 0
#define B_AX_FWD_ACTN_CAT0_MSK 0xff
#define R_AX_ACTION_FWD_CTRL1 0x9C0E
#define B_AX_FWD_ACTN_ACTN1_SH 8
#define B_AX_FWD_ACTN_ACTN1_MSK 0xff
#define B_AX_FWD_ACTN_CAT1_SH 0
#define B_AX_FWD_ACTN_CAT1_MSK 0xff
#define R_AX_ACTION_FWD_CTRL2 0x9C10
#define B_AX_FWD_ACTN_ACTN2_SH 8
#define B_AX_FWD_ACTN_ACTN2_MSK 0xff
#define B_AX_FWD_ACTN_CAT2_SH 0
#define B_AX_FWD_ACTN_CAT2_MSK 0xff
#define R_AX_ACTION_FWD_CTRL3 0x9C12
#define B_AX_FWD_ACTN_ACTN3_SH 8
#define B_AX_FWD_ACTN_ACTN3_MSK 0xff
#define B_AX_FWD_ACTN_CAT3_SH 0
#define B_AX_FWD_ACTN_CAT3_MSK 0xff
#define R_AX_TF_FWD 0x9C14
#define B_AX_FWD_TF15_SH 30
#define B_AX_FWD_TF15_MSK 0x3
#define B_AX_FWD_TF14_SH 28
#define B_AX_FWD_TF14_MSK 0x3
#define B_AX_FWD_TF13_SH 26
#define B_AX_FWD_TF13_MSK 0x3
#define B_AX_FWD_TF12_SH 24
#define B_AX_FWD_TF12_MSK 0x3
#define B_AX_FWD_TF11_SH 22
#define B_AX_FWD_TF11_MSK 0x3
#define B_AX_FWD_TF10_SH 20
#define B_AX_FWD_TF10_MSK 0x3
#define B_AX_FWD_TF9_SH 18
#define B_AX_FWD_TF9_MSK 0x3
#define B_AX_FWD_TF8_SH 16
#define B_AX_FWD_TF8_MSK 0x3
#define B_AX_FWD_TF7_SH 14
#define B_AX_FWD_TF7_MSK 0x3
#define B_AX_FWD_TF6_SH 12
#define B_AX_FWD_TF6_MSK 0x3
#define B_AX_FWD_TF5_SH 10
#define B_AX_FWD_TF5_MSK 0x3
#define B_AX_FWD_TF4_SH 8
#define B_AX_FWD_TF4_MSK 0x3
#define B_AX_FWD_TF3_SH 6
#define B_AX_FWD_TF3_MSK 0x3
#define B_AX_FWD_TF2_SH 4
#define B_AX_FWD_TF2_MSK 0x3
#define B_AX_FWD_TF1_SH 2
#define B_AX_FWD_TF1_MSK 0x3
#define B_AX_FWD_TF0_SH 0
#define B_AX_FWD_TF0_MSK 0x3
#define R_AX_HW_RPT_FWD 0x9C18
#define B_AX_FWD_TX_PLD_REL_WCPU_SH 16
#define B_AX_FWD_TX_PLD_REL_WCPU_MSK 0x3
#define B_AX_FWD_DFS_RPT_SH 14
#define B_AX_FWD_DFS_RPT_MSK 0x3
#define B_AX_FWD_TX_PLD_REL_HOST_SH 12
#define B_AX_FWD_TX_PLD_REL_HOST_MSK 0x3
#define B_AX_FWD_TX_RPT_SH 10
#define B_AX_FWD_TX_RPT_MSK 0x3
#define B_AX_FWD_SS2FW_RPT_SH 8
#define B_AX_FWD_SS2FW_RPT_MSK 0x3
#define B_AX_FWD_F2P_TX_CMD_RPT_SH 6
#define B_AX_FWD_F2P_TX_CMD_RPT_MSK 0x3
#define B_AX_FWD_BB_SCOPE_MODE_SH 4
#define B_AX_FWD_BB_SCOPE_MODE_MSK 0x3
#define B_AX_FWD_CH_INFO_SH 2
#define B_AX_FWD_CH_INFO_MSK 0x3
#define B_AX_FWD_PPDU_STAT_SH 0
#define B_AX_FWD_PPDU_STAT_MSK 0x3
#define R_AX_PLD_CAM_CTRL 0x9C1C
#define B_AX_PLD_CAM_EN BIT(7)
#define B_AX_PLD_CAM_ACC BIT(4)
#define B_AX_PLD_CAM_RANGE_SH 0
#define B_AX_PLD_CAM_RANGE_MSK 0xf
#define R_AX_PLD_CAM_ACCESS 0x9C20
#define B_AX_PLD_CAM_POLL BIT(31)
#define B_AX_PLD_CAM_RW BIT(30)
#define B_AX_PLD_CAM_CLR BIT(29)
#define B_AX_PLD_CAM_OFFSET_SH 0
#define B_AX_PLD_CAM_OFFSET_MSK 0xffff
#define R_AX_PLD_CAM_RDATA 0x9C24
#define B_AX_PLD_CAM_RDATA_SH 0
#define B_AX_PLD_CAM_RDATA_MSK 0xffffffffL
#define R_AX_PLD_CAM_WDATA 0x9C28
#define B_PLD_CAM_WDATA_SH 0
#define B_PLD_CAM_WDATA_MSK 0xffffffffL
#define R_AX_CUT_AMSDU_CTRL 0x9C40
#define B_AX_BIT_EN_CUT_AMSDU BIT(30)
#define B_AX_BIT_CUT_AMSDU_CHKLEN_EN BIT(24)
#define B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH_SH 16
#define B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH_MSK 0xff
#define B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH_SH 0
#define B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH_MSK 0xffff
#define R_AX_CUT_AMSDU_CTRL_2 0x9C44
#define B_AX_MSDU_DROP_SEQUENCE_NUMBER_SH 20
#define B_AX_MSDU_DROP_SEQUENCE_NUMBER_MSK 0xfff
#define B_AX_MSDU_DROP BIT(19)
#define B_AX_EXTRA_SHIFT_SH 17
#define B_AX_EXTRA_SHIFT_MSK 0x3
#define R_AX_REG_ERROR_MON 0x9C48
#define B_AX_BIT_MACRX_ERR_5 BIT(21)
#define R_AX_WOW_CTRL 0x9C50
#define B_AX_WOW_HCI BIT(5)
#define B_AX_WOW_DROP BIT(2)
#define B_AX_WOW_WOWEN BIT(1)
#define B_AX_WOW_WOWEN_SH 1
#define B_AX_WOW_FORCE_WAKEUP BIT(0)
#define R_AX_MPDU_RX_PKTCNT 0x9CE8
#define B_AX_RX_PKTOUT_CNT_SH 16
#define B_AX_RX_PKTOUT_CNT_MSK 0xffff
#define B_AX_RX_PKTIN_CNT_SH 0
#define B_AX_RX_PKTIN_CNT_MSK 0xffff
#define R_AX_MPDU_DROP_PKTCNT 0x9CEC
#define B_AX_DROP_PKTCNT_SH 0
#define B_AX_DROP_PKTCNT_MSK 0xffff
#define R_AX_MPDU_RX_ERR_ISR 0x9CF0
#define B_AX_RPT_ERR_ISR BIT(3)
#define B_AX_MHDRLEN_ERR_ISR BIT(1)
#define B_AX_GETPKTID_ERR_ISR BIT(0)
#define R_AX_MPDU_RX_ERR_IMR 0x9CF4
#define B_AX_RPT_ERR_INT_EN BIT(3)
#define B_AX_MHDRLEN_ERR_INT_EN BIT(1)
#define B_AX_GETPKTID_ERR_INT_EN BIT(0)
#define R_AX_MPDU_RX_DBG 0x9CF8
#define B_AX_MPDU_RX_CKEN_DIS BIT(15)
#define B_AX_MPDU_RX_DBG_EN BIT(8)
#define B_AX_MPDU_RX_D_LAST_EN BIT(0)
//
// SEC_ENG
//
#define R_AX_SEC_ENG_CTRL 0x9D00
#define B_AX_SEC_ENG_EN BIT(31)
#define B_AX_CCMP_SPP_MIC BIT(30)
#define B_AX_CCMP_SPP_CTR BIT(29)
#define B_AX_SEC_CAM_ACC BIT(28)
#define B_AX_SEC_CAM_CLK BIT(15)
#define B_AX_SEC_ENG_CLK BIT(14)
#define B_AX_RX_ICV_ERR BIT(13)
#define B_AX_TX_PARTIAL_MODE BIT(11)
#define B_AX_CLK_EN_CGCMP BIT(10)
#define B_AX_CLK_EN_WAPI BIT(9)
#define B_AX_CLK_EN_WEP_TKIP BIT(8)
#define B_AX_BMC_MGNT_DEC BIT(5)
#define B_AX_UC_MGNT_DEC BIT(4)
#define B_AX_MC_DEC BIT(3)
#define B_AX_BC_DEC BIT(2)
#define B_AX_SEC_RX_DEC BIT(1)
#define B_AX_SEC_TX_ENC BIT(0)
#define R_AX_SEC_MPDU_PROC 0x9D04
#define B_AX_APPEND_ICV BIT(1)
#define B_AX_APPEND_MIC BIT(0)
#define R_AX_SEC_CAM_ACCESS 0x9D10
#define B_AX_SEC_CAM_POLL BIT(15)
#define B_AX_SEC_CAM_RW BIT(14)
#define B_AX_SEC_CAM_ACC_FAIL BIT(13)
#define B_AX_SEC_CAM_OFFSET_SH 0
#define B_AX_SEC_CAM_OFFSET_MSK 0x3ff
#define R_AX_SEC_CAM_RDATA 0x9D14
#define B_AX_SEC_CAM_RDATA_SH 0
#define B_AX_SEC_CAM_RDATA_MSK 0xffffffffL
#define R_AX_SEC_CAM_WDATA 0x9D18
#define B_AX_SEC_CAM_WDATA_SH 0
#define B_AX_SEC_CAM_WDATA_MSK 0xffffffffL
#define R_AX_SEC_DEBUG 0x9D1C
#define B_AX_NON_SEC_SH 30
#define B_AX_NON_SEC_MSK 0x3
#define B_AX_TX_AMSDU_WAPI_SH 28
#define B_AX_TX_AMSDU_WAPI_MSK 0x3
#define B_AX__TX_AMSDU_RC4_SH 26
#define B_AX__TX_AMSDU_RC4_MSK 0x3
#define B_AX__TX_AMSDU__CCMP_GCMP_SH 24
#define B_AX__TX_AMSDU__CCMP_GCMP_MSK 0x3
#define B_AX_TX_WAPI_SH 22
#define B_AX_TX_WAPI_MSK 0x3
#define B_AX_TX_RC4_SH 20
#define B_AX_TX_RC4_MSK 0x3
#define B_AX_TX_CCMP_GCMP_SH 18
#define B_AX_TX_CCMP_GCMP_MSK 0x3
#define B_AX_RX_WAPI_SH 16
#define B_AX_RX_WAPI_MSK 0x3
#define B_AX_RX_RC4_SH 14
#define B_AX_RX_RC4_MSK 0x3
#define B_AX_RX_CCMP_GCMP_SH 12
#define B_AX_RX_CCMP_GCMP_MSK 0x3
#define B_AX_RX_PARSER_FSM_SH 8
#define B_AX_RX_PARSER_FSM_MSK 0xf
#define B_AX_TX_PARSER_FSM_SH 4
#define B_AX_TX_PARSER_FSM_MSK 0xf
#define B_AX_IMR_ERROR BIT(3)
#define B_AX_RX_HANG_ERROR BIT(2)
#define B_AX_TX_HANG_ERROR BIT(1)
#define B_AX_BYPASS_PKT BIT(0)
#define R_AX_SEC_TX_DEBUG 0x9D20
#define B_AX_TX_HANG BIT(22)
#define B_AX_TX_ENC_CLOCK_SH 6
#define B_AX_TX_ENC_CLOCK_MSK 0xffff
#define B_AX_TX_SEC_TYPE_SH 2
#define B_AX_TX_SEC_TYPE_MSK 0xf
#define B_AX_TX_EXKEY_ERROR BIT(1)
#define B_AX_TX_ENCRYPT BIT(0)
#define R_AX_SEC_RX_DEBUG 0x9D24
#define B_AX_RX_HANG BIT(31)
#define B_AX_RX_ENC_CLOCK_SH 15
#define B_AX_RX_ENC_CLOCK_MSK 0xffff
#define B_AX_RX_SEC_TYPE_SH 11
#define B_AX_RX_SEC_TYPE_MSK 0xf
#define B_AX_RX_MIC_ERROR BIT(10)
#define B_AX_RX_ICV_ERROR BIT(9)
#define B_AX_RX_EXKEY_INDEX_SH 1
#define B_AX_RX_EXKEY_INDEX_MSK 0x7f
#define B_AX_RX_ENCRYPT BIT(0)
#define R_AX_SEC_TRX_PKT_CNT 0x9D28
#define B_AX_TX_PKT_CLR BIT(31)
#define B_AX_TX_PKT_CNT_SH 16
#define B_AX_TX_PKT_CNT_MSK 0x7fff
#define B_AX_RX_PKT_CLR BIT(15)
#define B_AX_RX_PKT_CNT_SH 0
#define B_AX_RX_PKT_CNT_MSK 0x7fff
#define R_AX_SEC_TRX_BLK_CNT 0x9D2C
#define B_AX_TX_BLK_CNT_SH 16
#define B_AX_TX_BLK_CNT_MSK 0xffff
#define B_AX_RX_BLK_CNT_SH 0
#define B_AX_RX_BLK_CNT_MSK 0xffff
//
// STA scheduler
//
#define R_AX_SS_DBG_0 0x9E00
#define B_AX_SS_PARAM_STAT_SH 24
#define B_AX_SS_PARAM_STAT_MSK 0x7f
#define B_AX_SS_PC_STAT_SH 16
#define B_AX_SS_PC_STAT_MSK 0x3f
#define B_AX_SS_SA_STAT_SH 8
#define B_AX_SS_SA_STAT_MSK 0x3f
#define B_AX_SS_SS_INIT_DONE_0 BIT(7)
#define B_AX_SS_LM_STAT_SH 0
#define B_AX_SS_LM_STAT_MSK 0x7f
#define R_AX_SS_DBG_1 0x9E04
#define B_AX_SS_DEL_STAT_SH 28
#define B_AX_SS_DEL_STAT_MSK 0x3
#define B_AX_SS_ADD_STAT_SH 24
#define B_AX_SS_ADD_STAT_MSK 0x3
#define B_AX_SS_ULRU_STAT_SH 16
#define B_AX_SS_ULRU_STAT_MSK 0xf
#define B_AX_SS_DLTX_STAT_SH 8
#define B_AX_SS_DLTX_STAT_MSK 0x1f
#define B_AX_SS_LEN_STAT_SH 0
#define B_AX_SS_LEN_STAT_MSK 0x7f
#define R_AX_SS_DBG_2 0x9E08
#define B_AX_SS_PLEA_STAT_SH 24
#define B_AX_SS_PLEA_STAT_MSK 0xf
#define B_AX_SS_WDEA_STAT_SH 16
#define B_AX_SS_WDEA_STAT_MSK 0xf
#define B_AX_SS_RPTA_STAT_SH 8
#define B_AX_SS_RPTA_STAT_MSK 0x3f
#define B_AX_SS_FWTX_STAT_SH 0
#define B_AX_SS_FWTX_STAT_MSK 0x1f
#define R_AX_SS_DBG_3 0x9E0C
#define B_AX_SS_CLK_GATE_DIS_SH 30
#define B_AX_SS_CLK_GATE_DIS_MSK 0x3
#define B_AX_SS_HW_ADD_LEN_OVF BIT(26)
#define B_AX_SS_SW_DECR_LEN_UDN BIT(25)
#define B_AX_SS_HW_DECR_LEN_UDN BIT(24)
#define B_AX_SS_ATM_ERR BIT(18)
#define B_AX_SS_DEL_STA_ERR BIT(17)
#define B_AX_SS_ADD_STA_ERR BIT(16)
#define B_AX_SS_LEN_INIT_DONE BIT(10)
#define B_AX_SS_PARAM_INIT_DONE BIT(9)
#define B_AX_SS_LINK_INIT_DONE BIT(8)
#define B_AX_SS_MOD_DBG_SEL_SH 4
#define B_AX_SS_MOD_DBG_SEL_MSK 0x3
#define B_AX_SS_TOP_DBG_SEL_SH 0
#define B_AX_SS_TOP_DBG_SEL_MSK 0xf
#define R_AX_SS_CTRL 0x9E10
#define B_AX_SS_INIT_DONE_1 BIT(31)
#define B_AX_SS_HW_STA_DIS BIT(30)
#define B_AX_SS_WARM_INIT_FLG BIT(29)
#define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28)
#define B_AX_SS_DELAY_TX_BAND_SEL_SH 24
#define B_AX_SS_DELAY_TX_BAND_SEL_MSK 0x3
#define B_AX_SS_WMM_SEL_3_SH 22
#define B_AX_SS_WMM_SEL_3_MSK 0x3
#define B_AX_SS_WMM_SEL_2_SH 20
#define B_AX_SS_WMM_SEL_2_MSK 0x3
#define B_AX_SS_WMM_SEL_1_SH 18
#define B_AX_SS_WMM_SEL_1_MSK 0x3
#define B_AX_SS_WMM_SEL_0_SH 16
#define B_AX_SS_WMM_SEL_0_MSK 0x3
#define B_AX_SS_HW_LEN_EN BIT(2)
#define B_AX_SS_HW_PARAM_EN BIT(1)
#define B_AX_SS_EN BIT(0)
#define R_AX_SS_DL_QUOTA_CTRL 0x9E14
#define B_AX_SS_QUOTA_MODE_3 BIT(31)
#define B_AX_SS_QUOTA_MODE_2 BIT(30)
#define B_AX_SS_QUOTA_MODE_1 BIT(29)
#define B_AX_SS_QUOTA_MODE_0 BIT(28)
#define B_AX_SS_DL_QUOTA_LOWER_LIMIT_SH 8
#define B_AX_SS_DL_QUOTA_LOWER_LIMIT_MSK 0xff
#define B_AX_SS_DL_QUOTA_INIT_SH 0
#define B_AX_SS_DL_QUOTA_INIT_MSK 0xf
#define R_AX_SS_UL_QUOTA_CTRL 0x9E18
#define B_AX_SS_QUOTA_MODE_UL BIT(31)
#define B_AX_SS_UL_QUOTA_LOWER_LIMIT_SH 8
#define B_AX_SS_UL_QUOTA_LOWER_LIMIT_MSK 0xff
#define B_AX_SS_UL_QUOTA_INIT_SH 0
#define B_AX_SS_UL_QUOTA_INIT_MSK 0xf
#define R_AX_SS_BSR_CTRL 0x9E1C
#define B_AX_SS_BSR_THR_1_SH 16
#define B_AX_SS_BSR_THR_1_MSK 0x3fff
#define B_AX_SS_BSR_THR_0_SH 0
#define B_AX_SS_BSR_THR_0_MSK 0x3fff
#define R_AX_SS_DL_RPT_CRTL 0x9E20
#define B_AX_SS_TXOP_MODE_3 BIT(30)
#define B_AX_SS_TXOP_MODE_2 BIT(22)
#define B_AX_SS_TXOP_MODE_1 BIT(14)
#define B_AX_SS_TWT_MAX_SU_NUM_1_SH 11
#define B_AX_SS_TWT_MAX_SU_NUM_1_MSK 0x7
#define B_AX_SS_MAX_SU_NUM_1_SH 8
#define B_AX_SS_MAX_SU_NUM_1_MSK 0x7
#define B_AX_SS_TXOP_MODE_0 BIT(6)
#define B_AX_SS_TWT_MAX_SU_NUM_0_SH 3
#define B_AX_SS_TWT_MAX_SU_NUM_0_MSK 0x7
#define B_AX_SS_MAX_SU_NUM_0_SH 0
#define B_AX_SS_MAX_SU_NUM_0_MSK 0x7
#define R_AX_SS_UL_RPT_CRTL 0x9E24
#define B_AX_SS_MAX_RU_NUM_UL_SH 16
#define B_AX_SS_MAX_RU_NUM_UL_MSK 0x3
#define B_AX_SS_UL_WMM_SH 8
#define B_AX_SS_UL_WMM_MSK 0x3
#define B_AX_SS_TWT_MAX_SU_NUM_UL_SH 3
#define B_AX_SS_TWT_MAX_SU_NUM_UL_MSK 0x7
#define B_AX_SS_MAX_SU_NUM_UL_SH 0
#define B_AX_SS_MAX_SU_NUM_UL_MSK 0x7
#define R_AX_SS_SEARCH_TO 0x9E28
#define B_AX_SS_SEARCH_TO_SH 0
#define B_AX_SS_SEARCH_TO_MSK 0xff
#define R_AX_SS_SEARCH_LVL 0x9E2C
#define B_AX_SS_NEG_CNT_SH 16
#define B_AX_SS_NEG_CNT_MSK 0xff
#define B_AX_SS_NEG_LVL_SH 0
#define B_AX_SS_NEG_LVL_MSK 0xff
#define R_AX_SS_SRAM_DATA 0x9E30
#define B_AX_SS_SRAM_DATA_SH 0
#define B_AX_SS_SRAM_DATA_MSK 0xffffffffL
#define R_AX_SS_SRAM_W_EN 0x9E34
#define B_AX_SS_SRAM_W_EN_SH 0
#define B_AX_SS_SRAM_W_EN_MSK 0xffffffffL
#define R_AX_SS_SRAM_CTRL_0 0x9E38
#define B_AX_SS_OWN BIT(31)
#define B_AX_SS_RW BIT(23)
#define B_AX_SS_CMD_SH 20
#define B_AX_SS_CMD_MSK 0x7
#define B_AX_SS_OFFSET_SH 8
#define B_AX_SS_OFFSET_MSK 0x3
#define B_AX_SS_PARAM_SEL_SH 0
#define B_AX_SS_PARAM_SEL_MSK 0xff
#define R_AX_SS_LINK_INFO 0x9E3C
#define B_AX_SS_OWN BIT(31)
#define B_AX_SS_STATUS_SH 29
#define B_AX_SS_STATUS_MSK 0x3
#define B_AX_SS_UL BIT(28)
#define B_AX_SS_WMM_SH 26
#define B_AX_SS_WMM_MSK 0x3
#define B_AX_SS_AC_SH 24
#define B_AX_SS_AC_MSK 0x3
#define B_AX_SS_LINK_LEN_SH 16
#define B_AX_SS_LINK_LEN_MSK 0xff
#define B_AX_SS_LINK_TAIL_SH 8
#define B_AX_SS_LINK_TAIL_MSK 0xff
#define B_AX_SS_LINK_HEAD_SH 0
#define B_AX_SS_LINK_HEAD_MSK 0xff
#define R_AX_SS_LINK_ADD 0x9E40
#define B_AX_SS_OWN BIT(31)
#define B_AX_SS_UL BIT(28)
#define B_AX_SS_MACID_2_SH 16
#define B_AX_SS_MACID_2_MSK 0xff
#define B_AX_SS_MACID_1_SH 8
#define B_AX_SS_MACID_1_MSK 0xff
#define B_AX_SS_MACID_0_SH 0
#define B_AX_SS_MACID_0_MSK 0xff
#define R_AX_SS_LINK_DEL 0x9E44
#define B_AX_SS_OWN BIT(31)
#define B_AX_SS_UL BIT(28)
#define R_AX_SS_LINK_SEARCH 0x9E48
#define B_AX_SS_OWN BIT(31)
#define B_AX_SS_UL BIT(28)
#define B_AX_SS_TWT_GROUP_SH 20
#define B_AX_SS_TWT_GROUP_MSK 0xf
#define B_AX_SS_MODE_SEL_SH 16
#define B_AX_SS_MODE_SEL_MSK 0x3
#define R_AX_SS_SRAM_CTRL_1 0x9E4C
#define B_AX_SS_OWN BIT(31)
#define B_AX_SS_CMD_SEL_SH 26
#define B_AX_SS_CMD_SEL_MSK 0x1f
#define B_AX_SS_VALUE_SH 8
#define B_AX_SS_VALUE_MSK 0xffff
#define R_AX_SS2FINFO_PATH 0x9E50
#define B_AX_SS_UL_REL BIT(31)
#define B_AX_SS_REL_QUEUE_SH 24
#define B_AX_SS_REL_QUEUE_MSK 0x3f
#define B_AX_SS_REL_PORT_SH 16
#define B_AX_SS_REL_PORT_MSK 0x7
#define B_AX_SS_DEST_QUEUE_SH 8
#define B_AX_SS_DEST_QUEUE_MSK 0x3f
#define B_AX_SS_DEST_PORT_SH 0
#define B_AX_SS_DEST_PORT_MSK 0x7
#define R_AX_WMM_LINK_EMPTY 0x9E54
#define B_AX_WMM3_VO_LINK_EMPTY BIT(15)
#define B_AX_WMM3_VI_LINK_EMPTY BIT(14)
#define B_AX_WMM3_BK_LINK_EMPTY BIT(13)
#define B_AX_WMM3_BE_LINK_EMPTY BIT(12)
#define B_AX_WMM2_VO_LINK_EMPTY BIT(11)
#define B_AX_WMM2_VI_LINK_EMPTY BIT(10)
#define B_AX_WMM2_BK_LINK_EMPTY BIT(9)
#define B_AX_WMM2_BE_LINK_EMPTY BIT(8)
#define B_AX_WMM1_VO_LINK_EMPTY BIT(7)
#define B_AX_WMM1_VI_LINK_EMPTY BIT(6)
#define B_AX_WMM1_BK_LINK_EMPTY BIT(5)
#define B_AX_WMM1_BE_LINK_EMPTY BIT(4)
#define B_AX_WMM0_VO_LINK_EMPTY BIT(3)
#define B_AX_WMM0_VI_LINK_EMPTY BIT(2)
#define B_AX_WMM0_BK_LINK_EMPTY BIT(1)
#define B_AX_WMM0_BE_LINK_EMPTY BIT(0)
#define R_AX_SS_DELAYTX_TO 0x9E60
#define B_AX_SS_BEBK_TO_1_SH 24
#define B_AX_SS_BEBK_TO_1_MSK 0xff
#define B_AX_SS_VOVI_TO_1_SH 16
#define B_AX_SS_VOVI_TO_1_MSK 0xff
#define B_AX_SS_BEBK_TO_0_SH 8
#define B_AX_SS_BEBK_TO_0_MSK 0xff
#define B_AX_SS_VOVI_TO_0_SH 0
#define B_AX_SS_VOVI_TO_0_MSK 0xff
#define R_AX_SS_DELAYTX_LEN_THR 0x9E70
#define B_AX_SS_BEBK_LEN_THR_1_SH 24
#define B_AX_SS_BEBK_LEN_THR_1_MSK 0xff
#define B_AX_SS_VOVI_LEN_THR_1_SH 16
#define B_AX_SS_VOVI_LEN_THR_1_MSK 0xff
#define B_AX_SS_BEBK_LEN_THR_0_SH 8
#define B_AX_SS_BEBK_LEN_THR_0_MSK 0xff
#define B_AX_SS_VOVI_LEN_THR_0_SH 0
#define B_AX_SS_VOVI_LEN_THR_0_MSK 0xff
#define R_AX_SS_MU_CTRL 0x9E80
#define B_AX_SS_DLRU_STATE_SH 28
#define B_AX_SS_DLRU_STATE_MSK 0xf
#define B_AX_SS_DLMU_STATE_SH 24
#define B_AX_SS_DLMU_STATE_MSK 0xf
#define B_AX_SS_MU_OPT BIT(2)
#define B_AX_SS_SCORE_THR_SH 0
#define B_AX_SS_SCORE_THR_MSK 0x3
#define R_AX_SS_MU_TBL_0 0x9E84
#define B_AX_SS_MU_MACID_SH 11
#define B_AX_SS_MU_MACID_MSK 0x7f
#define B_AX_SS_TBL_VLD BIT(10)
#define B_AX_SS_SCORE_0_SH 8
#define B_AX_SS_SCORE_0_MSK 0x3
#define B_AX_SS_SCORE_1_SH 6
#define B_AX_SS_SCORE_1_MSK 0x3
#define B_AX_SS_SCORE_2_SH 4
#define B_AX_SS_SCORE_2_MSK 0x3
#define B_AX_SS_SCORE_3_SH 2
#define B_AX_SS_SCORE_3_MSK 0x3
#define B_AX_SS_SCORE_4_SH 0
#define B_AX_SS_SCORE_4_MSK 0x3
#define R_AX_SS_MU_TBL_1 0x9E88
#define B_AX_SS_TBL_VLD BIT(10)
#define R_AX_SS_MU_TBL_2 0x9E8C
#define B_AX_SS_TBL_VLD BIT(10)
#define R_AX_SS_MU_TBL_3 0x9E90
#define B_AX_SS_TBL_VLD BIT(10)
#define R_AX_SS_MU_TBL_4 0x9E94
#define B_AX_SS_TBL_VLD BIT(10)
#define R_AX_SS_MU_TBL_5 0x9E98
#define B_AX_SS_TBL_VLD BIT(10)
#define R_AX_SS_DL_MU_RPT_CRTL 0x9E9C
#define B_AX_SS_TWT_MAX_MU_NUM_1_SH 12
#define B_AX_SS_TWT_MAX_MU_NUM_1_MSK 0xf
#define B_AX_SS_MAX_MU_NUM_1_SH 8
#define B_AX_SS_MAX_MU_NUM_1_MSK 0xf
#define B_AX_SS_TWT_MAX_MU_NUM_0_SH 4
#define B_AX_SS_TWT_MAX_MU_NUM_0_MSK 0xf
#define B_AX_SS_MAX_MU_NUM_0_SH 0
#define B_AX_SS_MAX_MU_NUM_0_MSK 0xf
#define R_AX_SS_RU_CTRL 0x9EA0
#define B_AX_SS_GROUP_VLD_SH 16
#define B_AX_SS_GROUP_VLD_MSK 0xffff
#define B_AX_SS_RU_SEARCH_MODE_SH 0
#define B_AX_SS_RU_SEARCH_MODE_MSK 0xf
#define R_AX_SS_DL_RU_RPT_CRTL 0x9EA4
#define B_AX_SS_TWT_MAX_RU_NUM_1_SH 12
#define B_AX_SS_TWT_MAX_RU_NUM_1_MSK 0xf
#define B_AX_SS_MAX_RU_NUM_1_SH 8
#define B_AX_SS_MAX_RU_NUM_1_MSK 0xf
#define B_AX_SS_TWT_MAX_RU_NUM_0_SH 4
#define B_AX_SS_TWT_MAX_RU_NUM_0_MSK 0xf
#define B_AX_SS_MAX_RU_NUM_0_SH 0
#define B_AX_SS_MAX_RU_NUM_0_MSK 0xf
#define R_AX_SS_MACID_PAUSE_0 0x9EB0
#define B_AX_SS_MACID31_0_PAUSE_SH 0
#define B_AX_SS_MACID31_0_PAUSE_MSK 0xffffffffL
#define R_AX_SS_MACID_PAUSE_1 0x9EB4
#define B_AX_SS_MACID63_32_PAUSE_SH 0
#define B_AX_SS_MACID63_32_PAUSE_MSK 0xffffffffL
#define R_AX_SS_MACID_PAUSE_2 0x9EB8
#define B_AX_SS_MACID95_64_PAUSE_SH 0
#define B_AX_SS_MACID95_64_PAUSE_MSK 0xffffffffL
#define R_AX_SS_MACID_PAUSE_3 0x9EBC
#define B_AX_SS_MACID127_96_PAUSE_SH 0
#define B_AX_SS_MACID127_96_PAUSE_MSK 0xffffffffL
#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0
#define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2)
#define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1)
#define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0)
#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4
#define B_AX_PLE_B_PKTID_ERR_ISR BIT(2)
#define B_AX_RPT_HANG_TIMEOUT_ISR BIT(1)
#define B_AX_SEARCH_HANG_TIMEOUT_ISR BIT(0)
//
// Tx Packet Controller
//
#define R_AX_B0_CFG 0x9F10
#define B_AX_B0_ATCPAR_REFTU_VAL_SH 8
#define B_AX_B0_ATCPAR_REFTU_VAL_MSK 0xff
#define B_AX_B0_ATCTMR_REFTU_CYC_SH 4
#define B_AX_B0_ATCTMR_REFTU_CYC_MSK 0x7
#define B_AX_B0_DIS_ACGC BIT(0)
#define R_AX_B0_CTL 0x9F14
#define B_AX_B0_CMDPSR_CTLST_REQPS BIT(7)
#define B_AX_CMDPSR_CTLST_NXTST_SH 0
#define B_AX_CMDPSR_CTLST_NXTST_MSK 0x1f
#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C
#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25)
#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19)
#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18)
#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17)
#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16)
#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8)
#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
#define B_AX_B1_ATCPAR_REFTU_VAL_SH 8
#define B_AX_B1_ATCPAR_REFTU_VAL_MSK 0xff
#define B_AX_B1_ATCTMR_REFTU_CYC_SH 4
#define B_AX_B1_ATCTMR_REFTU_CYC_MSK 0x7
#define B_AX_B1_DIS_ACGC BIT(0)
#define B_AX_B1_CMDPSR_CTLST_REQPS BIT(7)
#define B_AX_B1_CMDPSR_CTLST_NXTST_SH 0
#define B_AX_B1_CMDPSR_CTLST_NXTST_MSK 0x1f
#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25)
#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19)
#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18)
#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17)
#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16)
#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8)
#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
#define R_AX_DBG_FUN_INTF_CTL 0x9F30
#define B_AX_DFI_ACTIVE BIT(31)
#define B_AX_DFI_TRGSEL_SH 16
#define B_AX_DFI_TRGSEL_MSK 0xf
#define B_AX_DFI_ADDR_SH 0
#define B_AX_DFI_ADDR_MSK 0xffff
#define R_AX_DBG_FUN_INTF_DATA 0x9F34
#define B_AX_DFI_DATA_SH 0
#define B_AX_DFI_DATA_MSK 0xffffffffL
#define R_AX_DBG_CTL_TXPKT 0x9F38
#define B_AX_TPC_DBG1_SEL_SH 16
#define B_AX_TPC_DBG1_SEL_MSK 0xffff
#define B_AX_TPC_DBG0_SEL_SH 0
#define B_AX_TPC_DBG0_SEL_MSK 0xffff
#define R_AX_TPC_DBG_OUT 0x9F3C
#define B_AX_DBG1_OUT_SH 16
#define B_AX_DBG1_OUT_MSK 0xffff
#define B_AX_DBG0_OUT_SH 0
#define B_AX_DBG0_OUT_MSK 0xffff
#define R_AX_TXPKTCTL_B0_CTL 0x9F44
#define B_AX_B0_CTLST_IDLE BIT(1)
#define B_AX_B0_STOP_REQ BIT(0)
#define R_AX_TXPKTCTL_B1_CTL 0x9F84
#define B_AX_B1_CTLST_IDLE BIT(1)
#define B_AX_B1_STOP_REQ BIT(0)
//
// WL_AX_Reg_AON.xls
//
//
// AON
//
#define R_AX_SYS_ISO_CTRL 0x0000
#define B_AX_PWC_EV2EF_SH 14
#define B_AX_PWC_EV2EF_MSK 0x3
#define B_AX_PA33V_EN BIT(13)
#define B_AX_PA12V_EN BIT(12)
#define B_AX_UA33V_EN BIT(11)
#define B_AX_UA12V_EN BIT(10)
#define B_AX_ISO_RFDIO BIT(9)
#define B_AX_ISO_EB2CORE BIT(8)
#define B_AX_ISO_DIOE BIT(7)
#define B_AX_ISO_WLPON2PP BIT(6)
#define B_AX_ISO_IP2MAC_WA2PP BIT(5)
#define B_AX_ISO_PD2CORE BIT(4)
#define B_AX_ISO_PA2PCIE BIT(3)
#define B_AX_ISO_UD2CORE BIT(2)
#define B_AX_ISO_UA2USB BIT(1)
#define B_AX_ISO_WD2PP BIT(0)
#define R_AX_SYS_FUNC_EN 0x0002
#define B_AX_FEN_MREGEN BIT(15)
#define B_AX_FEN_HWPDN BIT(14)
#define B_AX_FEN_ELDR BIT(12)
#define B_AX_FEN_DCORE BIT(11)
#define B_AX_FEN_CPUEN BIT(10)
#define B_AX_FEN_DIOE BIT(9)
#define B_AX_FEN_PCIED BIT(8)
#define B_AX_FEN_PPLL BIT(7)
#define B_AX_FEN_PCIEA BIT(6)
#define B_AX_FEN_USBD BIT(4)
#define B_AX_FEN_UPLL BIT(3)
#define B_AX_FEN_USBA BIT(2)
#define B_AX_FEN_BB_GLB_RSTN BIT(1)
#define B_AX_FEN_BBRSTB BIT(0)
#define R_AX_SYS_PW_CTRL 0x0004
#define B_AX_SOP_ASWRM BIT(31)
#define B_AX_SOP_EASWR BIT(30)
#define B_AX_SOP_PWMM_DSWR BIT(29)
#define B_AX_SOP_EDSWR BIT(28)
#define B_AX_SOP_ACKF BIT(27)
#define B_AX_SOP_ERCK BIT(26)
#define B_AX_SOP_ANA_CLK_DIVISION_2 BIT(25)
#define B_AX_SOP_EXTL BIT(24)
#define B_AX_ROP_SWPR BIT(21)
#define B_AX_DIS_HW_LPLDM BIT(20)
#define B_AX_RDY_SYSPWR BIT(17)
#define B_AX_EN_WLON BIT(16)
#define B_AX_APDM_HPDN BIT(15)
#define B_AX_PSUS_OFF_CAPC_EN BIT(14)
#define B_AX_AFSM_PCIE_SUS_EN BIT(12)
#define B_AX_AFSM_WLSUS_EN BIT(11)
#define B_AX_APFM_SWLPS BIT(10)
#define B_AX_APFM_OFFMAC BIT(9)
#define B_AX_APFN_ONMAC BIT(8)
#define B_AX_CHIP_PDN_EN BIT(7)
#define B_AX_RDY_MACDIS BIT(6)
#define B_AX_SW_AFE_MODE BIT(4)
#define B_AX_PFM_WOWL BIT(3)
#define B_AX_WL_HCI_ALD BIT(1)
#define B_AX_EFUSE_LDALL BIT(0)
#define R_AX_SYS_CLK_CTRL 0x0008
#define B_AX_CPU_IDMEM_CLK_EN BIT(15)
#define B_AX_CPU_CLK_EN BIT(14)
#define B_AX_SYMR_AX_CLK_EN BIT(13)
#define B_AX_MAC_CLK_EN BIT(11)
#define B_AX_EXT_32K_EN BIT(8)
#define B_AX_WL_CLK_TEST BIT(7)
#define B_AX_LOADER_CLK_EN BIT(5)
#define B_AX_ANA_CLK_DIVISION_2 BIT(1)
#define B_AX_CNTD16V_EN BIT(0)
#define R_AX_SYS_EEPROM_CTRL 0x000A
#define B_AX_AUTOLOAD_SUS BIT(5)
#define R_AX_SYS_SWR_CTRL1 0x0010
#define B_AX_SYM_CTRL_SPSANA_PWMFREQ BIT(11)
#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
#define B_AX_HW_AUTO_CTRL_EXT_SWR BIT(9)
#define B_AX_USE_INTERNAL_SWR_AND_LDO BIT(8)
#define B_AX_MAC_ID_EN BIT(7)
#define B_AX_OPTION_DIS_XTAL_BG BIT(2)
#define R_AX_ANAPARSW_POW_MAC 0x0014
#define B_AX_POW_LDO15 BIT(2)
#define B_AX_POW_SW_SPSANA BIT(1)
#define B_AX_POW_LDO14_SPSANA BIT(0)
#define R_AX_ANAPARLDO_POW_MAC 0x0015
#define B_AX_R_PD12_N_LDO BIT(5)
#define B_AX_POW_SW_SPSDIG BIT(1)
#define B_AX_POW_LDO14_SPSDIG BIT(0)
#define R_AX_ANAPAR_POW_MAC 0x0016
#define B_AX_POW_PC_LDO_PORT1 BIT(3)
#define B_AX_POW_PC_LDO_PORT0 BIT(2)
#define B_AX_POW_PLL_V1 BIT(1)
#define B_AX_POW_POWER_CUT_POW_LDO BIT(0)
#define R_AX_ANAPAR_POW_XTAL 0x0017
#define B_AX_POW_XTAL BIT(1)
#define B_AX_POW_BG BIT(0)
#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
#define R_AX_RSV_CTRL 0x001C
#define B_AX_HR_AX_DBG BIT(23)
#define B_AX_R_EN_HRST_PWRON BIT(8)
#define B_AX_LOCK_ALL_EN BIT(7)
#define B_AX_R_DIS_PRST BIT(6)
#define B_AX_WLOCK_1C_B6 BIT(5)
#define B_AX_WLOCK_40 BIT(4)
#define B_AX_WLOCK_08 BIT(3)
#define B_AX_WLOCK_04 BIT(2)
#define B_AX_WLOCK_00 BIT(1)
#define B_AX_WLOCK_ALL BIT(0)
#define R_AX_RF_CTRL 0x001F
#define B_AX_S0_RFC_WO_0 BIT(7)
#define B_AX_S0_RFC_WT_0 BIT(6)
#define B_AX_S0_RFC_RSTB BIT(1)
#define R_AX_AFE_LDO_CTRL 0x0020
#define B_AX_R_SYM_WLPOFF_P4_PC_EN BIT(28)
#define B_AX_R_SYM_WLPOFF_P3_PC_EN BIT(27)
#define B_AX_R_SYM_WLPOFF_P2_PC_EN BIT(26)
#define B_AX_R_SYM_WLPOFF_P1_PC_EN BIT(25)
#define B_AX_R_SYM_WLPOFF_PC_EN BIT(24)
#define B_AX_AON_OFF_PC_EN BIT(23)
#define B_AX_R_SYM_WLPON_P3_PC_EN BIT(21)
#define B_AX_R_SYM_WLPON_P2_PC_EN BIT(20)
#define B_AX_R_SYM_WLPON_P1_PC_EN BIT(19)
#define B_AX_R_SYM_WLPON_PC_EN BIT(18)
#define B_AX_R_SYM_DIS_WPHYBBOFF_PC BIT(10)
#define B_AX_R_SYM_WLBBOFF1_P4_PC_EN BIT(9)
#define B_AX_R_SYM_WLBBOFF1_P3_PC_EN BIT(8)
#define B_AX_R_SYM_WLBBOFF1_P2_PC_EN BIT(7)
#define B_AX_R_SYM_WLBBOFF1_P1_PC_EN BIT(6)
#define B_AX_R_SYM_WLBBOFF_P4_PC_EN BIT(4)
#define B_AX_R_SYM_WLBBOFF_P3_PC_EN BIT(3)
#define B_AX_R_SYM_WLBBOFF_P2_PC_EN BIT(2)
#define B_AX_R_SYM_WLBBOFF_P1_PC_EN BIT(1)
#define B_AX_R_SYM_WLBBOFF_PC_EN BIT(0)
#define R_AX_AFE_CTRL1 0x0024
#define B_AX_WLCPU_CLK_SEL_SH 22
#define B_AX_WLCPU_CLK_SEL_MSK 0x3
#define B_AX_CMAC_CLK_SEL BIT(21)
#define B_AX_PLL_DIV_SEL BIT(20)
#define B_AX_DMEM3_PC_EN BIT(15)
#define B_AX_DMEM2_PC_EN BIT(14)
#define B_AX_DMEM1_PC_EN BIT(13)
#define B_AX_IMEM4_PC_EN BIT(12)
#define B_AX_IMEM3_PC_EN BIT(11)
#define B_AX_IMEM2_PC_EN BIT(10)
#define B_AX_IMEM1_PC_EN BIT(9)
#define B_AX_IMEM0_PC_EN BIT(8)
#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0)
#define R_AX_SYS_OCP_CTRL 0x0028
#define B_AX_SPS_OCP_DIS BIT(31)
#define B_AX_SPS_OCP_TH_SH 16
#define B_AX_SPS_OCP_TH_MSK 0x7fff
#define B_AX_OCP_WINDOW_SH 0
#define B_AX_OCP_WINDOW_MSK 0xffff
#define R_AX_SYSANA_OCP_CTRL 0x002C
#define B_AX_SPSANA_OCP_DIS BIT(31)
#define B_AX_SPSANA_OCP_TH_SH 16
#define B_AX_SPSANA_OCP_TH_MSK 0x7fff
#define B_AX_OCPANA_WINDOW_SH 0
#define B_AX_OCPANA_WINDOW_MSK 0xffff
#define R_AX_EFUSE_CTRL 0x0030
#define B_AX_EF_MODE_SEL_SH 30
#define B_AX_EF_MODE_SEL_MSK 0x3
#define B_AX_EF_RDY BIT(29)
#define B_AX_EF_COMP_RESULT BIT(28)
#define B_AX_EF_ADDR_SH 16
#define B_AX_EF_ADDR_MSK 0x7ff
#define B_AX_EF_DATA_SH 0
#define B_AX_EF_DATA_MSK 0xffff
#define R_AX_EFUSE_TEST 0x0034
#define B_AX_EF_CRES_SEL BIT(31)
#define B_AX_EF_SCAN_SADR_SH 19
#define B_AX_EF_SCAN_SADR_MSK 0x7ff
#define B_AX_EF_SCAN_EADR_SH 8
#define B_AX_EF_SCAN_EADR_MSK 0x7ff
#define B_AX_EF_SCAN_TRPT BIT(7)
#define B_AX_EF_SCAN_FTHR_SH 0
#define B_AX_EF_SCAN_FTHR_MSK 0x7f
#define R_AX_EFUSE_CTRL_1 0x0038
#define B_AX_EF_PGPD_SH 28
#define B_AX_EF_PGPD_MSK 0x7
#define B_AX_EF_RDT BIT(27)
#define B_AX_EF_VDDQST_SH 24
#define B_AX_EF_VDDQST_MSK 0x7
#define B_AX_EF_PGTS_SH 20
#define B_AX_EF_PGTS_MSK 0xf
#define B_AX_EF_PD_DIS BIT(11)
#define B_AX_EF_POR BIT(10)
#define B_AX_EF_CELL_SEL_SH 8
#define B_AX_EF_CELL_SEL_MSK 0x3
#define R_AX_EFUSE_CTRL_1_V1 0x0038
#define B_AX_EF_ENT BIT(31)
#define B_AX_EF_BURST BIT(19)
#define B_AX_EF_TEST_SEL_SH 16
#define B_AX_EF_TEST_SEL_MSK 0x7
#define B_AX_EF_TROW_EN BIT(15)
#define B_AX_EF_ERR_FLAG BIT(14)
#define B_AX_EF_DSB_EN BIT(11)
#define B_AX_PCIE_CALIB_EN_V1 BIT(12)
#define B_AX_WDT_WAKE_PCIE_EN BIT(10)
#define B_AX_WDT_WAKE_USB_EN BIT(9)
#define R_AX_GPIO_MUXCFG 0x0040
#define B_AX_BOOT_MODE BIT(19)
#define B_AX_WL_EECS_EXT_32K_SEL BIT(18)
#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17)
#define B_AX_SECSIC_SEL BIT(16)
#define B_AX_ENHTP BIT(14)
#define B_AX_BT_AOD_GPIO3 BIT(13)
#define B_AX_ENSIC BIT(12)
#define B_AX_SIC_SWRST BIT(11)
#define B_AX_PO_WIFI_PTA_PINS BIT(10)
#define B_AX_PO_BT_PTA_PINS BIT(9)
#define B_AX_ENUARTTX BIT(8)
#define B_AX_BTMODE_SH 6
#define B_AX_BTMODE_MSK 0x3
#define B_AX_ENBT BIT(5)
#define B_AX_EROM_EN BIT(4)
#define B_AX_ENUARTRX BIT(2)
#define B_AX_GPIOSEL_SH 0
#define B_AX_GPIOSEL_MSK 0x3
#define R_AX_GPIO_PIN_CTRL 0x0044
#define B_AX_GPIO_MOD_7_TO_0_SH 24
#define B_AX_GPIO_MOD_7_TO_0_MSK 0xff
#define B_AX_GPIO_IO_SEL_7_TO_0_SH 16
#define B_AX_GPIO_IO_SEL_7_TO_0_MSK 0xff
#define B_AX_GPIO_OUT_7_TO_0_SH 8
#define B_AX_GPIO_OUT_7_TO_0_MSK 0xff
#define B_AX_GPIO_IN_7_TO_0_SH 0
#define B_AX_GPIO_IN_7_TO_0_MSK 0xff
#define R_AX_GPIO_INTM 0x0048
#define B_AX_EXTWOL_SEL BIT(17)
#define B_AX_EXTWOL_EN BIT(16)
#define B_AX_GPIOF_INT_MD BIT(15)
#define B_AX_GPIOE_INT_MD BIT(14)
#define B_AX_GPIOD_INT_MD BIT(13)
#define B_AX_GPIOC_INT_MD BIT(12)
#define B_AX_GPIOB_INT_MD BIT(11)
#define B_AX_GPIOA_INT_MD BIT(10)
#define B_AX_GPIO9_INT_MD BIT(9)
#define B_AX_GPIO8_INT_MD BIT(8)
#define B_AX_GPIO7_INT_MD BIT(7)
#define B_AX_GPIO6_INT_MD BIT(6)
#define B_AX_GPIO5_INT_MD BIT(5)
#define B_AX_GPIO4_INT_MD BIT(4)
#define B_AX_GPIO3_INT_MD BIT(3)
#define B_AX_GPIO2_INT_MD BIT(2)
#define B_AX_GPIO1_INT_MD BIT(1)
#define B_AX_GPIO0_INT_MD BIT(0)
#define R_AX_LED_CFG 0x004C
#define B_AX_MAILBOX_1WIRE_GPIO_CFG BIT(31)
#define B_AX_BT_RF_GPIO_CFG BIT(30)
#define B_AX_BT_SDIO_INT_GPIO_CFG BIT(29)
#define B_AX_MAILBOX_3WIRE_GPIO_CFG BIT(28)
#define B_AX_GPIO13_14_WL_CTRL_EN BIT(22)
#define B_AX_LED2DIS BIT(21)
#define B_AX_LED2PL BIT(20)
#define B_AX_LED2SV BIT(19)
#define B_AX_LED2CM_SH 16
#define B_AX_LED2CM_MSK 0x7
#define B_AX_LED0LED1_RD_ONLY_SH 13
#define B_AX_LED0LED1_RD_ONLY_MSK 0x3
#define R_AX_PWR_OPTION_CTRL 0x0050
#define B_AX_DIS_LPS_WT_PDNSUS BIT(24)
#define B_AX_SYSON_DBG_PAD_E2 BIT(11)
#define B_AX_SYSON_LED_PAD_E2 BIT(10)
#define B_AX_SYSON_GPEE_PAD_E2 BIT(9)
#define B_AX_SYSON_PCI_PAD_E2 BIT(8)
#define B_AX_SYSON_WLPC_IDX_SH 6
#define B_AX_SYSON_WLPC_IDX_MSK 0x3
#define B_AX_SYSON_SPS0WWV_WT_SH 4
#define B_AX_SYSON_SPS0WWV_WT_MSK 0x3
#define B_AX_SYSON_SPS0LDO_WT_SH 2
#define B_AX_SYSON_SPS0LDO_WT_MSK 0x3
#define B_AX_SYSON_RCLK_SCALE_SH 0
#define B_AX_SYSON_RCLK_SCALE_MSK 0x3
#define R_AX_CAL_TIMER 0x0054
#define B_AX_UART_TX_SEL_SH 30
#define B_AX_UART_TX_SEL_MSK 0x3
#define B_AX_UART_RX_SEL BIT(29)
#define B_AX_CAL_SCAL_SH 0
#define B_AX_CAL_SCAL_MSK 0xffff
#define R_AX_DBG_CTRL 0x0058
#define B_AX_DBG_SEL1_4BIT_SH 30
#define B_AX_DBG_SEL1_4BIT_MSK 0x3
#define B_AX_DBG_SEL1_16BIT BIT(27)
#define B_AX_DBG_SEL1_SH 16
#define B_AX_DBG_SEL1_MSK 0xff
#define B_AX_DBG_SEL0_4BIT_SH 14
#define B_AX_DBG_SEL0_4BIT_MSK 0x3
#define B_AX_DBG_SEL0_16BIT BIT(11)
#define B_AX_DBG_SEL0_SH 0
#define B_AX_DBG_SEL0_MSK 0xff
#define R_AX_PWR_CUT_CTRL 0x005C
#define B_AX_WLBBPC1_WT_SH 24
#define B_AX_WLBBPC1_WT_MSK 0xff
#define B_AX_WLBBPC0_WT_SH 16
#define B_AX_WLBBPC0_WT_MSK 0xff
#define B_AX_WLMACPC1_WT_SH 12
#define B_AX_WLMACPC1_WT_MSK 0xf
#define B_AX_WLMACPC0_WT_SH 8
#define B_AX_WLMACPC0_WT_MSK 0xf
#define B_AX_WLPONPC1_WT_SH 4
#define B_AX_WLPONPC1_WT_MSK 0xf
#define B_AX_WLPONPC0_WT_SH 0
#define B_AX_WLPONPC0_WT_MSK 0xf
#define R_AX_GPIO_EXT_CTRL 0x0060
#define B_AX_GPIO_MOD_15_TO_8_SH 24
#define B_AX_GPIO_MOD_15_TO_8_MSK 0xff
#define B_AX_GPIO_IO_SEL_15_TO_8_SH 16
#define B_AX_GPIO_IO_SEL_15_TO_8_MSK 0xff
#define B_AX_GPIO_OUT_15_TO_8_SH 8
#define B_AX_GPIO_OUT_15_TO_8_MSK 0xff
#define B_AX_GPIO_IN_15_TO_8_SH 0
#define B_AX_GPIO_IN_15_TO_8_MSK 0xff
#define R_AX_PAD_CTRL1 0x0064
#define B_AX_BT_BQB_GPIO_SEL BIT(27)
#define B_AX_BTGP_GPG3_FEN BIT(26)
#define B_AX_BTGP_GPG2_FEN BIT(25)
#define B_AX_BTGP_JTAG_EN BIT(24)
#define B_AX_XTAL_CLK_EXTARNAL_EN BIT(23)
#define B_AX_BTGP_UART0_EN BIT(22)
#define B_AX_BTGP_UART1_EN BIT(21)
#define B_AX_BTGP_SPI_EN BIT(20)
#define B_AX_BTGP_GPIO_E2 BIT(19)
#define B_AX_BTGP_GPIO_EN BIT(18)
#define B_AX_BTGP_GPIO_SL_SH 16
#define B_AX_BTGP_GPIO_SL_MSK 0x3
#define B_AX_WL_JTAG_EN BIT(15)
#define B_AX_PAD_SDIO_SR BIT(14)
#define B_AX_GPIO14_OUTPUT_PL BIT(13)
#define B_AX_HOST_WAKE_PAD_PULL_EN BIT(12)
#define B_AX_HOST_WAKE_PAD_SL BIT(11)
#define R_AX_WL_BT_PWR_CTRL 0x0068
#define B_AX_ISO_BD2PP BIT(31)
#define B_AX_LDOV12B_EN BIT(30)
#define B_AX_CKEN_BT BIT(29)
#define B_AX_FEN_BT BIT(28)
#define B_AX_BTCPU_BOOTSEL BIT(27)
#define B_AX_SPI_SPEEDUP BIT(26)
#define B_AX_BT_LDO_MODE BIT(25)
#define B_AX_DEVWAKE_PAD_TYPE_SEL BIT(24)
#define B_AX_CLKREQ_PAD_TYPE_SEL BIT(23)
#define B_AX_ISO_BTPON2PP BIT(22)
#define B_AX_BT_HWROF_EN BIT(19)
#define B_AX_BT_FUNC_EN BIT(18)
#define B_AX_BT_HWPDN_SL BIT(17)
#define B_AX_BT_DISN_EN BIT(16)
#define B_AX_BT_PDN_PULL_EN BIT(15)
#define B_AX_WL_PDN_PULL_EN BIT(14)
#define B_AX_EXTERNAL_REQUEST_PL BIT(13)
#define B_AX_GPIO0_2_3_PULL_LOW_EN BIT(12)
#define B_AX_ISO_BA2PP BIT(11)
#define B_AX_BT_AFE_LDO_EN BIT(10)
#define B_AX_BT_AFE_PLL_EN BIT(9)
#define B_AX_BT_DIG_CLK_EN BIT(8)
#define B_AX_WLAN_32K_SEL BIT(6)
#define B_AX_WL_DRV_EXIST_IDX BIT(5)
#define B_AX_DOP_EHPAD BIT(4)
#define B_AX_WL_HWROF_EN BIT(3)
#define B_AX_WL_FUNC_EN BIT(2)
#define B_AX_WL_HWPDN_SL BIT(1)
#define B_AX_WL_HWPDN_EN BIT(0)
#define R_AX_SDM_DEBUG 0x006C
#define B_AX_GPIO_IE_V18 BIT(10)
#define B_AX_PCIE_IE_V18 BIT(9)
#define B_AX_UART_IE_V18 BIT(8)
#define R_AX_SYS_SDIO_CTRL 0x0070
#define B_AX_DBG_GNT_WL_BT BIT(27)
#define B_AX_LTE_MUX_CTRL_PATH BIT(26)
#define B_AX_LTE_COEX_UART BIT(25)
#define B_AX_3W_LTE_WL_GPIO BIT(24)
#define B_AX_SDIO_INT_POLARITY BIT(19)
#define B_AX_SDIO_INT BIT(18)
#define B_AX_SDIO_OFF_EN BIT(17)
#define B_AX_SDIO_ON_EN BIT(16)
#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15)
#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14)
#define B_AX_PCIE_FORCE_PWR_NGAT BIT(13)
#define B_AX_PCIE_CALIB_EN_V1 BIT(12)
#define B_AX_PCIE_AUXCLK_GATE BIT(11)
#define B_AX_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
#define B_AX_PCIE_WAIT_TIME BIT(9)
#define B_AX_USBA_FORCE_PWR_NGAT BIT(7)
#define B_AX_USBD_FORCE_PWR_NGAT BIT(6)
#define B_AX_BT_CTRL_USB_PWR BIT(5)
#define B_AX_USB_D_STATE_HOLD BIT(4)
#define B_AX_R_AX_FORCE_DP BIT(3)
#define B_AX_R_AX_DP_MODE BIT(2)
#define B_AX_RES_USB_MASS_STORAGE_DESC BIT(1)
#define B_AX_USB_WAIT_TIME BIT(0)
#define R_AX_HCI_OPT_CTRL 0x0074
#define B_AX_PCIE_CPHY_CCK_XTAL_SEL BIT(20)
#define B_AX_SDIO_DATA_PAD_SMT BIT(19)
#define B_AX_SDIO_PAD_E5 BIT(18)
#define B_AX_NOPWR_CTRL_SEL BIT(13)
#define B_AX_USB_HOST_PWR_OFF_EN BIT(12)
#define B_AX_SYM_LPS_BLOCK_EN BIT(11)
#define B_AX_USB_LPM_ACT_EN BIT(10)
#define B_AX_USB_LPM_NY BIT(9)
#define B_AX_USB_SUS_DIS BIT(8)
#define B_AX_SDIO_PAD_E_SH 5
#define B_AX_SDIO_PAD_E_MSK 0x7
#define B_AX_USB_LPPLL_EN BIT(4)
#define B_AX_USB1_1_USB2_0_DECISION BIT(3)
#define B_AX_ROP_SW15 BIT(2)
#define B_AX_PCI_CKRDY_OPT BIT(1)
#define B_AX_PCI_VAUX_EN BIT(0)
#define R_AX_HCI_BG_CTRL 0x0078
#define B_AX_IBX_EN_VALUE BIT(15)
#define B_AX_IB_EN_VALUE BIT(14)
#define B_AX_FORCED_IB_EN BIT(4)
#define B_AX_EN_REGBG BIT(3)
#define B_AX_R_AX_BG_LPF BIT(2)
#define B_AX_R_AX_BG_SH 0
#define B_AX_R_AX_BG_MSK 0x3
#define R_AX_HCI_LDO_CTRL 0x007A
#define B_AX_EN_LW_PWR BIT(6)
#define B_AX_EN_REGU BIT(5)
#define B_AX_EN_PC BIT(4)
#define B_AX_R_AX_VADJ_SH 0
#define B_AX_R_AX_VADJ_MSK 0xf
#define R_AX_LDO_SWR_CTRL 0x007C
#define B_AX_DIG_ZCD_HW_AUTO_EN BIT(27)
#define B_AX_DIG_ZCD_REGSEL BIT(26)
#define B_AX_DIG_AUTO_ZCD_IN_CODE_SH 21
#define B_AX_DIG_AUTO_ZCD_IN_CODE_MSK 0x1f
#define B_AX_DIG_ZCD_CODE_IN_L_SH 16
#define B_AX_DIG_ZCD_CODE_IN_L_MSK 0x1f
#define B_AX_ANA_ZCD_HW_AUTO_EN BIT(11)
#define B_AX_ANA_ZCD_REGSEL BIT(10)
#define B_AX_ANA_AUTO_ZCD_IN_CODE_SH 5
#define B_AX_ANA_AUTO_ZCD_IN_CODE_MSK 0x1f
#define B_AX_ANA_ZCD_CODE_IN_L_SH 0
#define B_AX_ANA_ZCD_CODE_IN_L_MSK 0x1f
#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080
#define B_AX_R_SYM_FEN_WLMACOFF BIT(31)
#define B_AX_CMAC1_FEN BIT(30)
#define B_AX_R_SYM_ISO_DMEM32PP BIT(28)
#define B_AX_R_SYM_ISO_DMEM22PP BIT(27)
#define B_AX_R_SYM_ISO_DMEM12PP BIT(26)
#define B_AX_R_SYM_ISO_IMEM42PP BIT(22)
#define B_AX_R_SYM_ISO_IMEM32PP BIT(21)
#define B_AX_R_SYM_ISO_IMEM22PP BIT(20)
#define B_AX_R_SYM_ISO_IMEM12PP BIT(19)
#define B_AX_R_SYM_ISO_IMEM02PP BIT(18)
#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17)
#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16)
#define B_AX_R_SYM_ISO_AON_OFF2PP BIT(15)
#define B_AX_R_SYM_PWC_PD12V BIT(12)
#define B_AX_R_SYM_PWC_UD12V BIT(11)
#define B_AX_R_SYM_LDOBTSDIO_EN BIT(9)
#define B_AX_R_SYM_LDOSPDIO_EN BIT(8)
#define B_AX_R_SYM_ISO_BB2PP BIT(7)
#define B_AX_R_SYM_ISO_DENG2PP BIT(6)
#define B_AX_R_SYM_ISO_CMAC12PP BIT(5)
#define B_AX_R_SYM_ISO_BTSDIO2PP BIT(1)
#define B_AX_R_SYM_ISO_SPDIO2PP BIT(0)
#define R_AX_PLATFORM_ENABLE 0x0088
#define B_AX_SYM_WLPLT_MEM_MUX_EN BIT(10)
#define B_AX_WCPU_WARM_EN BIT(9)
#define B_AX_SPIC_EN BIT(8)
#define B_AX_UART_EN BIT(7)
#define B_AX_IDDMA_EN BIT(6)
#define B_AX_IPSEC_EN BIT(5)
#define B_AX_HIOE_EN BIT(4)
#define B_AX_AXIDMA_EN BIT(3)
#define B_AX_APB_WRAP_EN BIT(2)
#define B_AX_WCPU_EN BIT(1)
#define B_AX_PLATFORM_EN BIT(0)
#define R_AX_WLLPS_CTRL 0x0090
#define B_AX_LPSOP_BBOFF BIT(29)
#define B_AX_LPSOP_MACOFF BIT(28)
#define B_AX_LPSOP_MEM_DS BIT(26)
#define B_AX_LPSOP_XTALM_LPS BIT(23)
#define B_AX_LPSOP_XTAL BIT(22)
#define B_AX_LPSOP_ACLK_DIV_2 BIT(21)
#define B_AX_LPSOP_ACLK_SEL BIT(20)
#define B_AX_LPSOP_ASWRM BIT(17)
#define B_AX_LPSOP_ASWR BIT(16)
#define B_AX_LPSOP_DSWR_ADJ_SH 12
#define B_AX_LPSOP_DSWR_ADJ_MSK 0xf
#define B_AX_LPSOP_DSWRSD BIT(10)
#define B_AX_LPSOP_DSWRM BIT(9)
#define B_AX_LPSOP_DSWR BIT(8)
#define B_AX_LPSOP_OLD_ADJ_SH 4
#define B_AX_LPSOP_OLD_ADJ_MSK 0xf
#define B_AX_FORCE_LEAVE_LPS BIT(3)
#define B_AX_LPSOP_OLDSD BIT(2)
#define B_AX_LPSOP_OLDM BIT(1)
#define B_AX_WL_LPS_EN BIT(0)
#define R_AX_WLRESUME_CTRL 0x0094
#define B_AX_LPSROP_CMAC1 BIT(20)
#define B_AX_LPSROP_XTALM BIT(19)
#define B_AX_LPSROP_AFEM BIT(18)
#define B_AX_LPSROP_HIOE BIT(17)
#define B_AX_LPSROP_CPU BIT(16)
#define B_AX_LPSROP_DSWRSD_SEL_SH 4
#define B_AX_LPSROP_DSWRSD_SEL_MSK 0x3
#define R_AX_GPIO_DEBOUNCE_CTRL 0x0098
#define B_AX_WLGP_DBC1EN BIT(15)
#define B_AX_WLGP_DBC1_SH 8
#define B_AX_WLGP_DBC1_MSK 0xf
#define B_AX_WLGP_DBC0EN BIT(7)
#define B_AX_WLGP_DBC0_SH 0
#define B_AX_WLGP_DBC0_MSK 0xf
#define R_AX_SYSON_FSM_MON 0x00A0
#define B_AX_FSM_MON_SEL_SH 24
#define B_AX_FSM_MON_SEL_MSK 0x7
#define B_AX_DOP_ELDO BIT(23)
#define B_AX_FSM_MON_UPD BIT(15)
#define B_AX_FSM_PAR_SH 0
#define B_AX_FSM_PAR_MSK 0x7fff
#define R_AX_PMC_DBG_CTRL1 0x00A8
#define B_AX_PMC_WR_OVF BIT(8)
#define B_AX_WLPMC_ERRINT_SH 0
#define B_AX_WLPMC_ERRINT_MSK 0xff
#define R_AX_SCOREBOARD 0x00AC
#define B_AX_TOGGLE BIT(31)
#define B_AX_DATA_LINE_SH 0
#define B_AX_DATA_LINE_MSK 0x7fffffffL
#define R_AX_DBG_PORT_SEL 0x00C0
#define B_AX_DEBUG_ST_SH 0
#define B_AX_DEBUG_ST_MSK 0xffffffffL
#define R_AX_PAD_CTRL2 0x00C4
#define B_AX_FORCE_CLK_U2 BIT(25)
#define B_AX_FORCE_U2_CK BIT(24)
#define B_AX_FORCE_U3_CK BIT(23)
#define B_AX_USB2_FORCE BIT(22)
#define B_AX_USB3_FORCE BIT(21)
#define B_AX_USB3_USB2_TRANSITION BIT(20)
#define B_AX_USB23_SW_MODE_V1_SH 18
#define B_AX_USB23_SW_MODE_V1_MSK 0x3
#define B_AX_NO_PDN_CHIPOFF_V1 BIT(17)
#define B_AX_RSM_EN_V1 BIT(16)
#define B_AX_MATCH_CNT_SH 8
#define B_AX_MATCH_CNT_MSK 0xff
#define B_AX_LD_B12V_EN BIT(7)
#define B_AX_EECS_IOSEL_V1 BIT(6)
#define B_AX_EECS_DATA_O_V1 BIT(5)
#define B_AX_EECS_DATA_I_V1 BIT(4)
#define B_AX_EESK_IOSEL_V1 BIT(2)
#define B_AX_EESK_DATA_O_V1 BIT(1)
#define B_AX_EESK_DATA_I_V1 BIT(0)
#define R_AX_PMC_DBG_CTRL2 0x00CC
#define B_AX_EFUSE_BURN_GNT_SH 24
#define B_AX_EFUSE_BURN_GNT_MSK 0xff
#define B_AX_DIS_IOWRAP_TIMEOUT BIT(16)
#define B_AX_STOP_WL_PMC BIT(9)
#define B_AX_STOP_SYM_PMC BIT(8)
#define B_AX_BT_ACCESS_WL_PAGE0 BIT(6)
#define B_AX_R_AX_RST_WLPMC BIT(5)
#define B_AX_R_AX_RST_PD12N BIT(4)
#define B_AX_SYSON_DIS_WLR_AX_WRMSK BIT(3)
#define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2)
#define B_AX_SYSON_R_AX_ARB_SH 0
#define B_AX_SYSON_R_AX_ARB_MSK 0x3
#define R_AX_MEM_PWR_CTRL 0x00D0
#define B_AX_MEM_BB_SD BIT(17)
#define B_AX_MEM_BB_DS BIT(16)
#define B_AX_MEM_BT_DS BIT(10)
#define B_AX_MEM_SDIO_LS BIT(9)
#define B_AX_MEM_SDIO_DS BIT(8)
#define B_AX_MEM_USB_LS BIT(7)
#define B_AX_MEM_USB_DS BIT(6)
#define B_AX_MEM_PCI_LS BIT(5)
#define B_AX_MEM_PCI_DS BIT(4)
#define B_AX_MEM_WLMAC_LS BIT(3)
#define B_AX_MEM_WLMAC_DS BIT(2)
#define B_AX_MEM_WLMCU_LS BIT(1)
#define B_AX_MEM_WLMCU_DS BIT(0)
#define R_AX_INDIR_ADR_SDIO 0x00D4
#define B_AX_INDIR_READY_SDIO BIT(17)
#define B_AX_INDIR_R_SDIO BIT(16)
#define B_AX_INDIR_ADR_SDIO_SH 0
#define B_AX_INDIR_ADR_SDIO_MSK 0xffff
#define R_AX_INDIR_DATA_SDIO 0x00D8
#define B_AX_INDIR_DATA_SDIO_SH 0
#define B_AX_INDIR_DATA_SDIO_MSK 0xffffffffL
#define R_AX_USB_SIE_INTF 0x00E0
#define B_AX_USB_REG_SEL BIT(31)
#define B_AX_USB_WRITE_EN BIT(30)
#define B_AX_USB_REG_EN BIT(29)
#define B_AX_USB_SIE_SEL BIT(28)
#define B_AX_USB_REG_STATUS BIT(27)
#define B_AX_USB_PHY_BYTE_SEL BIT(26)
#define B_AX_USB_SIE_INTF_ADDR_SH 16
#define B_AX_USB_SIE_INTF_ADDR_MSK 0x3ff
#define B_AX_USB_SIE_INTF_RD_SH 8
#define B_AX_USB_SIE_INTF_RD_MSK 0xff
#define B_AX_USB_SIE_INTF_WD_SH 0
#define B_AX_USB_SIE_INTF_WD_MSK 0xff
#define R_AX_PCIE_MIO_INTF 0x00E4
#define B_AX_PCIE_MIO_ADDR_PAGE_SH 16
#define B_AX_PCIE_MIO_ADDR_PAGE_MSK 0x3
#define B_AX_PCIE_MIO_BYIOREG BIT(13)
#define B_AX_PCIE_MIO_RE BIT(12)
#define B_AX_PCIE_MIO_WE_SH 8
#define B_AX_PCIE_MIO_WE_MSK 0xf
#define B_AX_PCIE_MIO_ADDR_SH 0
#define B_AX_PCIE_MIO_ADDR_MSK 0xff
#define R_AX_PCIE_MIO_INTD 0x00E8
#define B_AX_PCIE_MIO_DATA_SH 0
#define B_AX_PCIE_MIO_DATA_MSK 0xffffffffL
#define R_AX_WLRF1 0x00EC
#define B_AX_S1_RFC_WO_0 BIT(31)
#define B_AX_S1_RFC_WT_0 BIT(30)
#define B_AX_S1_RFC_RSTB BIT(25)
#define R_AX_SYS_CFG1 0x00F0
#define B_AX_TRP_ICFG_SH 28
#define B_AX_TRP_ICFG_MSK 0xf
#define B_AX_RF_TYPE_ID BIT(27)
#define B_AX_BD_HCI_SEL BIT(26)
#define B_AX_BD_PKG_SEL BIT(25)
#define B_AX_RTL_ID BIT(23)
#define B_AX_PAD_HWPD_IDN BIT(22)
#define B_AX_TESTMODE BIT(20)
#define B_AX_VENDOR_ID_SH 16
#define B_AX_VENDOR_ID_MSK 0xf
#define B_AX_CHIP_VER_SH 12
#define B_AX_CHIP_VER_MSK 0xf
#define B_AX_BD_MAC3 BIT(11)
#define B_AX_BD_MAC1 BIT(10)
#define B_AX_BD_MAC2 BIT(9)
#define B_AX_SIC_IDLE BIT(8)
#define B_AX_ANA_SPS_OCP_SHUTDN BIT(7)
#define B_AX_DIG_SPS_OCP_SHUTDN BIT(6)
#define B_AX_V15_VLD BIT(5)
#define B_AX_PCIRSTB BIT(4)
#define B_AX_PCLK_VLD BIT(3)
#define B_AX_UCLK_VLD BIT(2)
#define B_AX_ACLK_VLD BIT(1)
#define B_AX_XCLK_VLD BIT(0)
#define R_AX_SYS_STATUS1 0x00F4
#define B_AX_RF_RL_ID_SH 28
#define B_AX_RF_RL_ID_MSK 0xf
#define B_AX_BT_LPS_EN BIT(27)
#define B_AX_WLAN_LPS_EN BIT(26)
#define B_AX_HPHY_ICFG BIT(19)
#define B_AX_SEL_0XC0_SH 16
#define B_AX_SEL_0XC0_MSK 0x3
#define B_AX_HCI_SEL_V4_SH 13
#define B_AX_HCI_SEL_V4_MSK 0x7
#define B_AX_USB_OPERATION_MODE BIT(12)
#define B_AX_BT_PDN BIT(11)
#define B_AX_AUTO_WLPON BIT(10)
#define B_AX_WL_MODE_SH 8
#define B_AX_WL_MODE_MSK 0x3
#define B_AX_PKG_SEL_HCI BIT(6)
#define B_AX_PAD_HCI_SEL_V2_SH 3
#define B_AX_PAD_HCI_SEL_V2_MSK 0x7
#define B_AX_EFS_HCI_SEL_V1_SH 0
#define B_AX_EFS_HCI_SEL_V1_MSK 0x7
#define R_AX_SYS_STATUS2 0x00F8
#define B_AX_SIC_ON_TIMEOUT BIT(22)
#define B_AX_CPU_ON_TIMEOUT BIT(21)
#define B_AX_HCI_ON_TIMEOUT BIT(20)
#define B_AX_SIO_ALDN BIT(19)
#define B_AX_USB_ALDN BIT(18)
#define B_AX_PCI_ALDN BIT(17)
#define B_AX_SYS_ALDN BIT(16)
#define B_AX_EPVID1_SH 8
#define B_AX_EPVID1_MSK 0xff
#define B_AX_EPVID0_SH 0
#define B_AX_EPVID0_MSK 0xff
#define R_AX_SYS_CHIPINFO 0x00FC
#define B_AX_USB2_SEL BIT(31)
#define B_AX_U3PHY_RST_V1 BIT(30)
#define B_AX_U3_TERM_DETECT BIT(29)
#define B_AX_HW_ID_SH 0
#define B_AX_HW_ID_MSK 0xff
#define R_AX_SYS_CFG3 0x0100
#define R_AX_ANAPARSW_MAC_0 0x0110
#define B_AX_OCP_L BIT(31)
#define B_AX_POWOCP_L BIT(30)
#define B_AX_CF_L_V2_SH 28
#define B_AX_CF_L_V2_MSK 0x3
#define B_AX_CFC_L_V2_SH 26
#define B_AX_CFC_L_V2_MSK 0x3
#define B_AX_R3_L_V2_SH 24
#define B_AX_R3_L_V2_MSK 0x3
#define B_AX_R2_L_SH 22
#define B_AX_R2_L_MSK 0x3
#define B_AX_R1_L_SH 20
#define B_AX_R1_L_MSK 0x3
#define B_AX_C3_L_SH 18
#define B_AX_C3_L_MSK 0x3
#define B_AX_C2_L_SH 16
#define B_AX_C2_L_MSK 0x3
#define B_AX_C1_L_V2_SH 14
#define B_AX_C1_L_V2_MSK 0x3
#define B_AX_R_AX_OCPS_L_V2 BIT(13)
#define B_AX_R_AX_PWM_L BIT(12)
#define B_AX_V15ADJ_L_SH 9
#define B_AX_V15ADJ_L_MSK 0x7
#define B_AX_IN_L_SH 6
#define B_AX_IN_L_MSK 0x7
#define B_AX_STD_L_SH 4
#define B_AX_STD_L_MSK 0x3
#define B_AX_VOL_L_SH 0
#define B_AX_VOL_L_MSK 0xf
#define R_AX_ANAPARSW_MAC_1 0x0114
#define B_AX_OCP_L_PFM_SH 29
#define B_AX_OCP_L_PFM_MSK 0x7
#define B_AX_CFC_L_PFM_SH 27
#define B_AX_CFC_L_PFM_MSK 0x3
#define B_AX_R_AX_FREQ_L_V1_SH 20
#define B_AX_R_AX_FREQ_L_V1_MSK 0x7
#define B_AX_EN_DUTY BIT(19)
#define B_AX_R_AX_MODE_V2_SH 17
#define B_AX_R_AX_MODE_V2_MSK 0x3
#define B_AX_EN_SP BIT(16)
#define B_AX_R_AX_AUTO_L_V2 BIT(15)
#define B_AX_R_AX_LDOF_L_V2 BIT(14)
#define B_AX_R_AX_TYPE_L_V2 BIT(13)
#define B_AX_VO15_V1P05_H BIT(12)
#define B_AX_ARENB_L_V2 BIT(11)
#define B_AX_TBOX_L1_V2_SH 9
#define B_AX_TBOX_L1_V2_MSK 0x3
#define B_AX_R_AX_DELAY_L_SH 7
#define B_AX_R_AX_DELAY_L_MSK 0x3
#define B_AX_R_AX_CLAMP_D_L BIT(6)
#define B_AX_R_AX_BYPASS_L_V2 BIT(5)
#define B_AX_R_AX_AUTOZCD_L BIT(4)
#define B_AX_POW_ZCD_L_V2 BIT(3)
#define B_AX_R_AX_HALF_L BIT(2)
#define B_AX_OCP_L_V2_SH 0
#define B_AX_OCP_L_V2_MSK 0x3
#define R_AX_ANAPAR_MAC_0 0x0118
#define B_AX_R_AX_LPF_R3_SH 29
#define B_AX_R_AX_LPF_R3_MSK 0x7
#define B_AX_R_AX_LPF_R2_SH 24
#define B_AX_R_AX_LPF_R2_MSK 0x1f
#define B_AX_R_AX_LPF_C3_SH 21
#define B_AX_R_AX_LPF_C3_MSK 0x7
#define B_AX_R_AX_LPF_C2_SH 18
#define B_AX_R_AX_LPF_C2_MSK 0x7
#define B_AX_R_AX_LPF_C1_SH 15
#define B_AX_R_AX_LPF_C1_MSK 0x7
#define B_AX_R_AX_LDO_SEL_V1_SH 13
#define B_AX_R_AX_LDO_SEL_V1_MSK 0x3
#define B_AX_R_AX_CP_ICPX2 BIT(12)
#define B_AX_R_AX_CP_ICP_SEL_FAST_SH 9
#define B_AX_R_AX_CP_ICP_SEL_FAST_MSK 0x7
#define B_AX_R_AX_CP_ICP_SEL_SH 6
#define B_AX_R_AX_CP_ICP_SEL_MSK 0x7
#define B_AX_R_AX_IB_PI_SH 4
#define B_AX_R_AX_IB_PI_MSK 0x3
#define B_AX_LDO2PWRCUT BIT(3)
#define B_AX_VPULSE_LDO BIT(2)
#define B_AX_LDO_VSEL_SH 0
#define B_AX_LDO_VSEL_MSK 0x3
#define R_AX_ANAPAR_MAC_1 0x011C
#define B_AX_R_AX_CK_MON_SEL_SH 29
#define B_AX_R_AX_CK_MON_SEL_MSK 0x7
#define B_AX_R_AX_CK_MON_EN BIT(28)
#define B_AX_R_AX_XTAL_FREQ_SEL BIT(27)
#define B_AX_R_AX_XTAL_EDGE_SEL BIT(26)
#define B_AX_R_AX_VCO_KVCO BIT(25)
#define B_AX_R_AX_SDM_EDGE_SEL BIT(24)
#define B_AX_R_AX_SDM_CK_SEL BIT(23)
#define B_AX_R_AX_SDM_CK_GATED BIT(22)
#define B_AX_R_AX_PFD_RESET_GATED BIT(21)
#define B_AX_R_AX_LPF_R3_FAST_SH 16
#define B_AX_R_AX_LPF_R3_FAST_MSK 0x1f
#define B_AX_R_AX_LPF_R2_FAST_SH 11
#define B_AX_R_AX_LPF_R2_FAST_MSK 0x1f
#define B_AX_R_AX_LPF_C3_FAST_SH 8
#define B_AX_R_AX_LPF_C3_FAST_MSK 0x7
#define B_AX_R_AX_LPF_C2_FAST_SH 5
#define B_AX_R_AX_LPF_C2_FAST_MSK 0x7
#define B_AX_R_AX_LPF_C1_FAST_SH 2
#define B_AX_R_AX_LPF_C1_FAST_MSK 0x7
#define B_AX_R_AX_LPF_R3_V1_SH 0
#define B_AX_R_AX_LPF_R3_V1_MSK 0x3
#define R_AX_ANAPAR_MAC_2 0x0120
#define B_AX_AGPIO_DRV_V1_SH 30
#define B_AX_AGPIO_DRV_V1_MSK 0x3
#define B_AX_AGPIO_GPO_V1 BIT(29)
#define B_AX_AGPIO_GPE_V1 BIT(28)
#define B_AX_SEL_CLK BIT(27)
#define B_AX_LS_XTAL_SEL_SH 23
#define B_AX_LS_XTAL_SEL_MSK 0xf
#define B_AX_LS_SDM_ORDER_V1 BIT(22)
#define B_AX_LS_DELAY_PH BIT(21)
#define B_AX_DIVIDER_SEL BIT(20)
#define B_AX_PCODE_SH 15
#define B_AX_PCODE_MSK 0x1f
#define B_AX_NCODE_SH 7
#define B_AX_NCODE_MSK 0xff
#define B_AX_R_AX_BEACON BIT(6)
#define B_AX_R_AX_MBIASE BIT(5)
#define B_AX_R_AX_FAST_SEL_SH 3
#define B_AX_R_AX_FAST_SEL_MSK 0x3
#define B_AX_R_AX_CK960M_EN BIT(2)
#define B_AX_R_AX_CK320M_EN BIT(1)
#define B_AX_R_AX_CK_5M_EN BIT(0)
#define R_AX_RFE_PINMUX_CTRL 0x0140
#define B_AX__BANDSELN_5G_SEL BIT(31)
#define B_AX__BANDSELN_5G_EN BIT(30)
#define B_AX_BANDSELN_5_6G_SEL BIT(29)
#define B_AX_BANDSELN_5_6G_EN BIT(28)
#define B_AX_PAON_LNAON_6G_S1_SEL BIT(27)
#define B_AX_PAON_LNAON_6G_S1_EN BIT(26)
#define B_AX_PAON_LNAON_6G_S0_SEL BIT(25)
#define B_AX_PAON_LNAON_6G_S0_EN BIT(24)
#define B_AX_PAON_LNAON_5G_S1_SEL BIT(23)
#define B_AX_PAON_LNAON_5G_S1_EN BIT(22)
#define B_AX_PAON_LNAON_5G_S0_SEL BIT(21)
#define B_AX_PAON_LNAON_5G_S0_EN BIT(20)
#define B_AX_PAON_LNAON_2G_S1_SEL BIT(19)
#define B_AX_PAON_LNAON_2G_S1_EN BIT(18)
#define B_AX_PAON_LNAON_2G_S0_SEL BIT(17)
#define B_AX_PAON_LNAON_2G_S0_EN BIT(16)
#define B_AX__BANDSELN_5G_G7G6_SEL BIT(15)
#define B_AX__BANDSELN_5G_G7G6_EN BIT(14)
#define R_AX_RFE_PINMUX_SEL_FUNC 0x0144
#define B_AX_RFE_WLBT_FUNC_8_SEL_EN BIT(8)
#define B_AX_RFE_WLBT_FUNC_7_SEL_EN BIT(7)
#define B_AX_RFE_WLBT_FUNC_6_SEL_EN BIT(6)
#define B_AX_RFE_WLBT_FUNC_5_SEL_EN BIT(5)
#define B_AX_RFE_WLBT_FUNC_4_SEL_EN BIT(4)
#define B_AX_RFE_WLBT_FUNC_3_SEL_EN BIT(3)
#define B_AX_RFE_WLBT_FUNC_2_SEL_EN BIT(2)
#define B_AX_RFE_WLBT_FUNC_1_SEL_EN BIT(1)
#define B_AX_RFE_WLBT_FUNC_0_SEL_EN BIT(0)
#define R_AX_GPIO_EESK_EECS_HIGH_PRI_PINMUX 0x0148
#define B_AX_STD_EECS_PINMUX_HIGH_PRI_EN BIT(17)
#define B_AX_STD_EESK_PINMUX_HIGH_PRI_EN BIT(16)
#define B_AX_STD_GPIO15_PINMUX_HIGH_PRI_EN BIT(15)
#define B_AX_STD_GPIO14_PINMUX_HIGH_PRI_EN BIT(14)
#define B_AX_STD_GPIO13_PINMUX_HIGH_PRI_EN BIT(13)
#define B_AX_STD_GPIO12_PINMUX_HIGH_PRI_EN BIT(12)
#define B_AX_STD_GPIO11_PINMUX_HIGH_PRI_EN BIT(11)
#define B_AX_STD_GPIO10_PINMUX_HIGH_PRI_EN BIT(10)
#define B_AX_STD_GPIO9_PINMUX_HIGH_PRI_EN BIT(9)
#define B_AX_STD_GPIO8_PINMUX_HIGH_PRI_EN BIT(8)
#define B_AX_STD_GPIO7_PINMUX_HIGH_PRI_EN BIT(7)
#define B_AX_STD_GPIO6_PINMUX_HIGH_PRI_EN BIT(6)
#define B_AX_STD_GPIO5_PINMUX_HIGH_PRI_EN BIT(5)
#define B_AX_STD_GPIO4_PINMUX_HIGH_PRI_EN BIT(4)
#define B_AX_STD_GPIO3_PINMUX_HIGH_PRI_EN BIT(3)
#define B_AX_STD_GPIO2_PINMUX_HIGH_PRI_EN BIT(2)
#define B_AX_STD_GPIO1_PINMUX_HIGH_PRI_EN BIT(1)
#define B_AX_STD_GPIO0_PINMUX_HIGH_PRI_EN BIT(0)
#define R_AX_RFE_CTRL 0x014C
#define B_AX_SW_LNAON_6G_S1_SEL_DATA BIT(13)
#define B_AX_SW_PAON_6G_S1_SEL_DATA BIT(12)
#define B_AX_BANDSELP_5G_SEL_DATA BIT(11)
#define B_AX_BANDSELP_5 BIT(10)
#define B_AX_SW_LNAON_6G_S0_SEL_DATA BIT(9)
#define B_AX_SW_PAON_6G_S0_SEL_DATA BIT(8)
#define B_AX_SW_LNAON_5G_S1_SEL_DATA BIT(7)
#define B_AX_SW_PAON_5G_S1_SEL_DATA BIT(6)
#define B_AX_SW_LNAON_5G_S0_SEL_DATA BIT(5)
#define B_AX_SW_PAON_5G_S0_SEL_DATA BIT(4)
#define B_AX_SW_LNAON_2G_S1_SEL_DATA BIT(3)
#define B_AX_SW_PAON_2G_S1_SEL_DATA BIT(2)
#define B_AX_SW_LNAON_2G_S0_SEL_DATA BIT(1)
#define B_AX_SW_PAON_2G_S0_SEL_DATA BIT(0)
#define R_AX_ANAPAR_XTAL_AACK_0 0x0154
#define R_AX_ANAPAR_XTAL_AACK_1 0x0158
#define R_AX_HALT_H2C_CTRL 0x0160
#define B_AX_HALT_H2C_TRIGGER BIT(0)
#define R_AX_HALT_C2H_CTRL 0x0164
#define B_AX_HALT_C2H_TRIGGER BIT(0)
#define R_AX_HALT_H2C 0x0168
#define B_AX_HALT_H2C_SH 0
#define B_AX_HALT_H2C_MSK 0xffffffffL
#define R_AX_HALT_C2H 0x016C
#define DBG_SENARIO_SH 28
#define B_AX_HALT_C2H_SH 0
#define B_AX_HALT_C2H_MSK 0xffffffffL
#define R_AX_SYS_CFG5 0x0170
#define B_AX_LPS_STATUS BIT(3)
#define B_AX_HCI_TXDMA_BUSY BIT(2)
#define B_AX_HCI_TXDMA_ALLOW BIT(1)
#define B_AX_FW_CTRL_HCI_TXDMA_EN BIT(0)
#define R_AX_ANACK_CAL_CTRL 0x0180
#define B_AX_CLK_CAL_EN BIT(31)
#define B_AX_CLK_SEL_SH 24
#define B_AX_CLK_SEL_MSK 0x3
#define B_AX_CLK_CAL_RPT_SH 0
#define B_AX_CLK_CAL_RPT_MSK 0xffff
#define R_AX_FWS0IMR 0x0190
#define B_AX_FS_HALT_H2C_INT_EN BIT(31)
#define B_AX_FS_FSM_HIOE_TO_EVENT_INT_EN BIT(30)
#define B_AX_FS_HCI_SUS_INT_EN BIT(29)
#define B_AX_FS_HCI_RES_INT_EN BIT(28)
#define B_AX_FS_HCI_RESET_INT_EN BIT(27)
#define B_AX_FS_USB_SCSI_CMD_INT_EN BIT(26)
#define B_AX_FS_ACT2RECOVERY_INT_EN BIT(25)
#define B_AX_FS_GEN1GEN2_SWITCH_INT_EN BIT(24)
#define B_AX_FS_HCI_TXDMA_REQ_INT_EN BIT(23)
#define B_AX_FS_USB_LPMRSM_INT_EN BIT(22)
#define B_AX_FS_USB_LPMINT_INT_EN BIT(21)
#define B_AX_FS_PWMERR_INT_EN BIT(20)
#define B_AX_FS_PDNINT_EN BIT(19)
#define B_AX_FS_SPSA_OCP_INT_EN BIT(18)
#define B_AX_FS_SPSD_OCP_INT_EN BIT(17)
#define B_AX_FS_BT_SB_INT_EN BIT(16)
#define B_AX_FS_GPIOF_INT_EN BIT(15)
#define B_AX_FS_GPIOE_INT_EN BIT(14)
#define B_AX_FS_GPIOD_INT_EN BIT(13)
#define B_AX_FS_GPIOC_INT_EN BIT(12)
#define B_AX_FS_GPIOB_INT_EN BIT(11)
#define B_AX_FS_GPIOA_INT_EN BIT(10)
#define B_AX_FS_GPIO9_INT_EN BIT(9)
#define B_AX_FS_GPIO8_INT_EN BIT(8)
#define B_AX_FS_GPIO7_INT_EN BIT(7)
#define B_AX_FS_GPIO6_INT_EN BIT(6)
#define B_AX_FS_GPIO5_INT_EN BIT(5)
#define B_AX_FS_GPIO4_INT_EN BIT(4)
#define B_AX_FS_GPIO3_INT_EN BIT(3)
#define B_AX_FS_GPIO2_INT_EN BIT(2)
#define B_AX_FS_GPIO1_INT_EN BIT(1)
#define B_AX_FS_GPIO0_INT_EN BIT(0)
#define R_AX_FWS0ISR 0x0194
#define B_AX_FS_HALT_H2C_INT BIT(31)
#define B_AX_FS_FSM_HIOE_TO_EVENT_INT BIT(30)
#define B_AX_FS_HCI_SUS_INT BIT(29)
#define B_AX_FS_HCI_RES_INT BIT(28)
#define B_AX_FS_HCI_RESET_INT BIT(27)
#define B_AX_FS_USB_SCSI_CMD_INT BIT(26)
#define B_AX_FS_ACT2RECOVERY_INT BIT(25)
#define B_AX_FS_GEN1GEN2_SWITCH_INT BIT(24)
#define B_AX_FS_HCI_TXDMA_REQ_INT BIT(23)
#define B_AX_FS_USB_LPMRSM_INT BIT(22)
#define B_AX_FS_USB_LPMINT_INT BIT(21)
#define B_AX_FS_PWMERR_INT BIT(20)
#define B_AX_FS_PDNINT BIT(19)
#define B_AX_FS_SPSA_OCP_INT BIT(18)
#define B_AX_FS_SPSD_OCP_INT BIT(17)
#define B_AX_FS_BT_SB_INT BIT(16)
#define B_AX_FS_GPIOF_INT BIT(15)
#define B_AX_FS_GPIOE_INT BIT(14)
#define B_AX_FS_GPIOD_INT BIT(13)
#define B_AX_FS_GPIOC_INT BIT(12)
#define B_AX_FS_GPIOB_INT BIT(11)
#define B_AX_FS_GPIOA_INT BIT(10)
#define B_AX_FS_GPIO9_INT BIT(9)
#define B_AX_FS_GPIO8_INT BIT(8)
#define B_AX_FS_GPIO7_INT BIT(7)
#define B_AX_FS_GPIO6_INT BIT(6)
#define B_AX_FS_GPIO5_INT BIT(5)
#define B_AX_FS_GPIO4_INT BIT(4)
#define B_AX_FS_GPIO3_INT BIT(3)
#define B_AX_FS_GPIO2_INT BIT(2)
#define B_AX_FS_GPIO1_INT BIT(1)
#define B_AX_FS_GPIO0_INT BIT(0)
#define R_AX_HSIMR 0x0198
#define R_AX_HSISR 0x019C
#define R_AX_HIMR0 0x01A0
#define B_AX_HALT_C2H_INT_EN BIT(21)
#define B_AX_RON_INT_EN BIT(20)
#define B_AX_PDNINT_EN BIT(19)
#define B_AX_SPSANA_OCP_INT_EN BIT(18)
#define B_AX_SPS_OCP_INT_EN BIT(17)
#define B_AX_BTON_STS_UPDATE_INT_EN BIT(16)
#define B_AX_GPIOF_INT_EN BIT(15)
#define B_AX_GPIOE_INT_EN BIT(14)
#define B_AX_GPIOD_INT_EN BIT(13)
#define B_AX_GPIOC_INT_EN BIT(12)
#define B_AX_GPIOB_INT_EN BIT(11)
#define B_AX_GPIOA_INT_EN BIT(10)
#define B_AX_GPIO9_INT_EN BIT(9)
#define B_AX_GPIO8_INT_EN BIT(8)
#define B_AX_GPIO7_INT_EN BIT(7)
#define B_AX_GPIO6_INT_EN BIT(6)
#define B_AX_GPIO5_INT_EN BIT(5)
#define B_AX_GPIO4_INT_EN BIT(4)
#define B_AX_GPIO3_INT_EN BIT(3)
#define B_AX_GPIO2_INT_EN BIT(2)
#define B_AX_GPIO1_INT_EN BIT(1)
#define B_AX_GPIO0_INT_EN BIT(0)
#define R_AX_HISR0 0x01A4
#define B_AX_HALT_C2H_INT BIT(21)
#define B_AX_RON_INT BIT(20)
#define B_AX_PDNINT BIT(19)
#define B_AX_SPSANA_OCP_INT BIT(18)
#define B_AX_SPS_OCP_INT BIT(17)
#define B_AX_BTON_STS_UPDATE_INT BIT(16)
#define B_AX_GPIOF_INT BIT(15)
#define B_AX_GPIOE_INT BIT(14)
#define B_AX_GPIOD_INT BIT(13)
#define B_AX_GPIOC_INT BIT(12)
#define B_AX_GPIOB_INT BIT(11)
#define B_AX_GPIOA_INT BIT(10)
#define B_AX_GPIO9_INT BIT(9)
#define B_AX_GPIO8_INT BIT(8)
#define B_AX_GPIO7_INT BIT(7)
#define B_AX_GPIO6_INT BIT(6)
#define B_AX_GPIO5_INT BIT(5)
#define B_AX_GPIO4_INT BIT(4)
#define B_AX_GPIO3_INT BIT(3)
#define B_AX_GPIO2_INT BIT(2)
#define B_AX_GPIO1_INT BIT(1)
#define B_AX_GPIO0_INT BIT(0)
#define R_AX_HIMR1 0x01A8
#define R_AX_HISR1 0x01AC
#define R_AX_HIMR2 0x01B0
#define R_AX_HISR2 0x01B4
#define R_AX_HIMR3 0x01B8
#define R_AX_HISR3 0x01BC
#define R_AX_SW_MDIO 0x01C0
#define B_AX_DIS_TIMEOUT_IO BIT(24)
#define R_AX_H2C_PKT_READADDR 0x01D0
#define B_AX_H2C_PKT_READADDR_SH 0
#define B_AX_H2C_PKT_READADDR_MSK 0x3ffff
#define R_AX_H2C_PKT_WRITEADDR 0x01D4
#define B_AX_H2C_PKT_WRITEADDR_SH 0
#define B_AX_H2C_PKT_WRITEADDR_MSK 0x3ffff
#define R_AX_MEM_PWR_CRTL 0x01D8
#define B_AX_MEM_BB_SD BIT(17)
#define B_AX_MEM_BB_DS BIT(16)
#define B_AX_MEM_BT_DS BIT(10)
#define B_AX_MEM_SDIO_LS BIT(9)
#define B_AX_MEM_SDIO_DS BIT(8)
#define B_AX_MEM_USB_LS BIT(7)
#define B_AX_MEM_USB_DS BIT(6)
#define B_AX_MEM_PCI_LS BIT(5)
#define B_AX_MEM_PCI_DS BIT(4)
#define B_AX_MEM_WLMAC_LS BIT(3)
#define B_AX_MEM_WLMAC_DS BIT(2)
#define B_AX_MEM_WLMCU_LS BIT(1)
#define B_AX_MEM_WLMCU_DS BIT(0)
#define R_AX_WCPU_FW_CTRL 0x01E0
#define B_AX_WCPU_ROM_ENUART BIT(31)
#define B_AX_WCPU_ROM_CUT_REQ BIT(30)
#define B_AX_WCPU_ROM_CUT_SH 8
#define B_AX_WCPU_ROM_CUT_MSK 0xff
#define B_AX_WCPU_FWDL_STS_SH 5
#define B_AX_WCPU_FWDL_STS_MSK 0x7
#define B_AX_FWDL_PATH_RDY BIT(2)
#define B_AX_H2C_PATH_RDY BIT(1)
#define B_AX_WCPU_FWDL_EN BIT(0)
#define R_AX_BOOT_REASON 0x01E6
#define B_AX_BOOT_REASON_SH 0
#define B_AX_BOOT_REASON_MSK 0x7
#define R_AX_RPWM 0x01E4
#define B_AX_RPWM_TOGGLE BIT(15)
#define B_AX_RPWM_VAL_SH 0
#define B_AX_RPWM_VAL_MSK 0x7fff
#define R_AX_LDM 0x01E8
#define B_AX_LDM_SH 0
#define B_AX_LDM_MSK 0xffffffffL
#define R_AX_UDM0 0x01F0
#define B_AX_UDM0_SH 0
#define B_AX_UDM0_MSK 0xffffffffL
#define B_AX_UDM0_DBG_MODE_SH 0
#define B_AX_UDM0_FS_CODE_SH 8
#define B_AX_UDM0_FS_CODE_MSK 0xffff
#define B_AX_UDM0_TRAP_LOOP_CTRL BIT(2)
#define B_AX_UDM0_DBG_MODE_CTRL BIT(0)
#define R_AX_UDM1 0x01F4
#define B_AX_UDM1_SH 0
#define B_AX_UDM1_MSK 0xffffffffL
#define R_AX_UDM2 0x01F8
#define B_AX_UDM2_SH 0
#define B_AX_UDM2_MSK 0xffffffffL
#define R_AX_UDM3 0x01FC
#define B_AX_UDM3_SH 0
#define B_AX_UDM3_MSK 0xffffffffL
#define R_AX_SPSLDO_ON_CTRL0 0x0200
#define B_AX_PFMCMP_IQ BIT(31)
#define B_AX_OFF_END_SEL BIT(29)
#define B_AX_POW_MINOFF_L BIT(28)
#define B_AX_COT_I_L_SH 26
#define B_AX_COT_I_L_MSK 0x3
#define B_AX_VREFPFM_L_SH 22
#define B_AX_VREFPFM_L_MSK 0xf
#define B_AX_FORCE_ZCD_BIAS BIT(21)
#define B_AX_ZCD_SDZ_L_SH 19
#define B_AX_ZCD_SDZ_L_MSK 0x3
#define B_AX_REG_ZCDC_H_SH 17
#define B_AX_REG_ZCDC_H_MSK 0x3
#define B_AX_POW_ZCD_L BIT(16)
#define B_AX_OCP_L1_SH 13
#define B_AX_OCP_L1_MSK 0x7
#define B_AX_POWOCP_L1 BIT(12)
#define B_AX_SAW_FREQ_L_SH 8
#define B_AX_SAW_FREQ_L_MSK 0xf
#define B_AX_REG_BYPASS_L BIT(7)
#define B_AX_FPWM_L1 BIT(6)
#define B_AX_STD_L1_SH 4
#define B_AX_STD_L1_MSK 0x3
#define B_AX_VOL_L1_SH 0
#define B_AX_VOL_L1_MSK 0xf
#define R_AX_SPSLDO_ON_CTRL1 0x0204
#define B_AX_SN_N_L_SH 28
#define B_AX_SN_N_L_MSK 0xf
#define B_AX_SP_N_L_SH 24
#define B_AX_SP_N_L_MSK 0xf
#define B_AX_SN_P_L_SH 20
#define B_AX_SN_P_L_MSK 0xf
#define B_AX_SP_P_L_SH 16
#define B_AX_SP_P_L_MSK 0xf
#define B_AX_VO_DISCHG_PWM_H BIT(15)
#define B_AX_REG_MODE_PREDRIVER BIT(14)
#define B_AX_REG_ADJSLDO_L_SH 10
#define B_AX_REG_ADJSLDO_L_MSK 0xf
#define B_AX_REG_LDOR_L BIT(9)
#define B_AX_PWM_FORCE BIT(8)
#define B_AX_PFM_PD_RST BIT(7)
#define B_AX_VC_PFM_RSTB BIT(6)
#define B_AX_PFM_IN_SEL BIT(5)
#define B_AX_VC_RSTB BIT(4)
#define B_AX_FPWMDELAY BIT(3)
#define B_AX_ENFPWMDELAY_H BIT(2)
#define B_AX_REG_MOS_HALF_L BIT(1)
#define B_AX_CURRENT_SENSE_MOS BIT(0)
#define B_AX_SPS_PFM_ZCDC_H_PFM_SH 4
#define B_AX_SPS_PFM_ZCDC_H_PFM_MSK 0x3
#define B_AX_SPS_PFM_OCP_L_PFM_SH 0
#define B_AX_SPS_PFM_OCP_L_PFM_MSK 0x7
#define R_AX_LDO_AON_CTRL0 0x0218
#define B_AX_CK12M_EN BIT(11)
#define B_AX_CK12M_SEL BIT(10)
#define B_AX_EN_SLEEP BIT(8)
#define B_AX_LDOH12_V12ADJ_L_SH 4
#define B_AX_LDOH12_V12ADJ_L_MSK 0xf
#define B_AX_LDOE25_V12ADJ_L_SH 0
#define B_AX_LDOE25_V12ADJ_L_MSK 0xf
#define R_AX_SPSANA_ON_CTRL0 0x0220
#define B_AX_PFMCMP_IQ BIT(31)
#define B_AX_REG_EXTERNAL_CLK_SEL_L BIT(30)
#define B_AX_OFF_END_SEL BIT(29)
#define B_AX_POW_MINOFF_L BIT(28)
#define B_AX_FORCE_ZCD_BIAS BIT(21)
#define B_AX_POW_ZCD_L BIT(16)
#define B_AX_POWOCP_L1 BIT(12)
#define B_AX_REG_BYPASS_L BIT(7)
#define B_AX_FPWM_L1 BIT(6)
#define R_AX_SPSANA_ON_CTRL1 0x0224
#define B_AX_VO_DISCHG_PWM_H BIT(15)
#define B_AX_REG_MODE_PREDRIVER BIT(14)
#define B_AX_REG_LDOR_L BIT(9)
#define B_AX_PWM_FORCE BIT(8)
#define B_AX_PFM_PD_RST BIT(7)
#define B_AX_VC_PFM_RSTB BIT(6)
#define B_AX_PFM_IN_SEL BIT(5)
#define B_AX_VC_RSTB BIT(4)
#define B_AX_FPWMDELAY BIT(3)
#define B_AX_ENFPWMDELAY_H BIT(2)
#define B_AX_REG_MOS_HALF_L BIT(1)
#define B_AX_CURRENT_SENSE_MOS BIT(0)
#define B_AX_SPS_ANA_PFM_ZCDC_H_SH 4
#define B_AX_SPS_ANA_PFM_ZCDC_H_MSK 0x3
#define B_AX_SPS_ANA_PFM_OCP_L_SH 0
#define B_AX_SPS_ANA_PFM_OCP_L_MSK 0x7
#define R_AX_AFE_ON_CTRL0 0x0240
#define B_AX_REG_LPF_R3_SH 29
#define B_AX_REG_LPF_R3_MSK 0x7
#define B_AX_REG_LPF_R2_SH 24
#define B_AX_REG_LPF_R2_MSK 0x1f
#define B_AX_REG_LPF_C3_SH 21
#define B_AX_REG_LPF_C3_MSK 0x7
#define B_AX_REG_LPF_C2_SH 18
#define B_AX_REG_LPF_C2_MSK 0x7
#define B_AX_REG_LPF_C1_SH 15
#define B_AX_REG_LPF_C1_MSK 0x7
#define B_AX_REG_LDO_SEL_SH 13
#define B_AX_REG_LDO_SEL_MSK 0x3
#define B_AX_REG_CP_ICPX2 BIT(12)
#define B_AX_REG_CP_ICP_SEL_FAST_SH 9
#define B_AX_REG_CP_ICP_SEL_FAST_MSK 0x7
#define B_AX_REG_CP_ICP_SEL_SH 6
#define B_AX_REG_CP_ICP_SEL_MSK 0x7
#define B_AX_REG_IB_PI_SH 4
#define B_AX_REG_IB_PI_MSK 0x3
#define B_AX_LDO2PWRCUT BIT(3)
#define B_AX_VPULSE_LDO BIT(2)
#define R_AX_AFE_ON_CTRL1 0x0244
#define B_AX_REG_CK_MON_SEL_SH 29
#define B_AX_REG_CK_MON_SEL_MSK 0x7
#define B_AX_REG_CK_MON_EN BIT(28)
#define B_AX_REG_XTAL_FREQ_SEL BIT(27)
#define B_AX_REG_XTAL_EDGE_SEL BIT(26)
#define B_AX_REG_VCO_KVCO BIT(25)
#define B_AX_REG_SDM_EDGE_SEL BIT(24)
#define B_AX_REG_SDM_CK_SEL BIT(23)
#define B_AX_REG_SDM_CK_GATED BIT(22)
#define B_AX_REG_PFD_RESET_GATED BIT(21)
#define B_AX_REG_LPF_R3_FAST_SH 16
#define B_AX_REG_LPF_R3_FAST_MSK 0x1f
#define B_AX_REG_LPF_R2_FAST_SH 11
#define B_AX_REG_LPF_R2_FAST_MSK 0x1f
#define B_AX_REG_LPF_C3_FAST_SH 8
#define B_AX_REG_LPF_C3_FAST_MSK 0x7
#define B_AX_REG_LPF_C2_FAST_SH 5
#define B_AX_REG_LPF_C2_FAST_MSK 0x7
#define B_AX_REG_LPF_C1_FAST_SH 2
#define B_AX_REG_LPF_C1_FAST_MSK 0x7
#define B_AX_REG_LPF_R3__SH 0
#define B_AX_REG_LPF_R3__MSK 0x3
#define R_AX_AFE_ON_CTRL2 0x0248
#define B_AX_AGPIO_DRV_SH 30
#define B_AX_AGPIO_DRV_MSK 0x3
#define B_AX_AGPIO_GPO BIT(29)
#define B_AX_AGPIO_GPE BIT(28)
#define B_AX_SEL_CLK BIT(27)
#define B_AX_LS_SDM_ORDER BIT(22)
#define B_AX_LS_DELAY_PH BIT(21)
#define B_AX_DIVIDER_SEL BIT(20)
#define B_AX_REG_BEACON BIT(6)
#define B_AX_REG_MBIASE BIT(5)
#define B_AX_REG_FAST_SEL_SH 3
#define B_AX_REG_FAST_SEL_MSK 0x3
#define B_AX_REG_CK480M_EN BIT(2)
#define B_AX_REG_CK320M_EN BIT(1)
#define B_AX_REG_CK_5M_EN BIT(0)
#define R_AX_AFE_ON_CTRL3 0x024C
#define B_AX_REG_CK640M_EN BIT(0)
#define R_AX_WLAN_XTAL_SI_CTRL 0x0270
#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30)
#define B_AX_WL_XTAL_GNT BIT(29)
#define B_AX_BT_XTAL_GNT BIT(28)
#define B_AX_WL_XTAL_SI_MODE_SH 24
#define B_AX_WL_XTAL_SI_MODE_MSK 0x3
#define B_AX_WL_XTAL_SI_BITMASK_SH 16
#define B_AX_WL_XTAL_SI_BITMASK_MSK 0xff
#define B_AX_WL_XTAL_SI_DATA_SH 8
#define B_AX_WL_XTAL_SI_DATA_MSK 0xff
#define B_AX_WL_XTAL_SI_ADDR_SH 0
#define B_AX_WL_XTAL_SI_ADDR_MSK 0xff
#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274
#define B_AX_XTAL_SI_CLK_DIV2 BIT(1)
#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)
#define R_AX_XTAL_ON_CTRL0 0x0280
#define B_AX_XTAL_SC_LPS BIT(31)
#define B_AX_XTAL_SC_INIT_SH 24
#define B_AX_XTAL_SC_INIT_MSK 0x7f
#define B_AX_XTAL_SC_XO_SH 17
#define B_AX_XTAL_SC_XO_MSK 0x7f
#define B_AX_XTAL_SC_XI_SH 10
#define B_AX_XTAL_SC_XI_MSK 0x7f
#define B_AX_XTAL_GMN_SH 5
#define B_AX_XTAL_GMN_MSK 0x1f
#define B_AX_XTAL_GMP_SH 0
#define B_AX_XTAL_GMP_MSK 0x1f
#define B_AX_EN_XBUF_DRV_LPS BIT(6)
#define R_AX_XTAL_ON_CTRL1 0x0284
#define B_AX_XTAL_VREF_SEL_SH 29
#define B_AX_XTAL_VREF_SEL_MSK 0x7
#define B_AX_XTAL_LPS_DIVISOR BIT(28)
#define B_AX_XTAL_CKDIGI_SEL BIT(27)
#define B_AX_EN_XTAL_SCHMITT BIT(26)
#define B_AX_XTAL_SEL_TOK_SH 23
#define B_AX_XTAL_SEL_TOK_MSK 0x7
#define B_AX_EN_XTAL_LPS_CLK BIT(22)
#define B_AX_XTAL_AAC_OPCUR_SH 20
#define B_AX_XTAL_AAC_OPCUR_MSK 0x3
#define B_AX_XTAL_LDO_VREF_SH 17
#define B_AX_XTAL_LDO_VREF_MSK 0x7
#define B_AX_EN_XTAL_DRV_BT BIT(16)
#define B_AX_EN_XTAL_DRV_BCN BIT(15)
#define B_AX_EN_XTAL_DRV_IQK BIT(14)
#define B_AX_EN_XTAL_DRV_LPS BIT(13)
#define B_AX_EN_XTAL_DRV_DIGI BIT(12)
#define B_AX_EN_XTAL_DRV_USB BIT(11)
#define B_AX_EN_XTAL_DRV_AFE BIT(10)
#define B_AX_XTAL_DRV_RF2N_RELAY BIT(9)
#define B_AX_XTAL_DRV_RF2P_RELAY BIT(8)
#define B_AX_EN_XTAL_DRV_RF2 BIT(7)
#define B_AX_EN_XTAL_DRV_RF1 BIT(6)
#define B_AX_XTAL_SC_LPS_SH 0
#define B_AX_XTAL_SC_LPS_MSK 0x3f
#define R_AX_XTAL_ON_CTRL2 0x0288
#define B_AX_XTAL_VREF_SEL__SH 6
#define B_AX_XTAL_VREF_SEL__MSK 0x3
#define B_AX_AAC_MODE_SH 4
#define B_AX_AAC_MODE_MSK 0x3
#define B_AX_XTAL_CFIX_SH 0
#define B_AX_XTAL_CFIX_MSK 0xf
#define R_AX_SYM_ANAPAR_XTAL_MODE_DECODER 0x02A0
#define B_AX_WIFI_FORCE_XTAL_HPMODE BIT(31)
#define B_AX_XTAL_LDO_LPS_SH 21
#define B_AX_XTAL_LDO_LPS_MSK 0x7
#define B_AX_XTAL_WAIT_CYC_SH 15
#define B_AX_XTAL_WAIT_CYC_MSK 0x3f
#define B_AX_XTAL_LDO_OK_SH 12
#define B_AX_XTAL_LDO_OK_MSK 0x7
#define B_AX_XTAL_MD_LPOW BIT(11)
#define B_AX_XTAL_OV_RATIO_SH 9
#define B_AX_XTAL_OV_RATIO_MSK 0x3
#define B_AX_XTAL_OV_UNIT_SH 6
#define B_AX_XTAL_OV_UNIT_MSK 0x7
#define B_AX_XTAL_MODE_MANUAL_SH 4
#define B_AX_XTAL_MODE_MANUAL_MSK 0x3
#define B_AX_XTAL_MANU_SEL BIT(3)
#define B_AX_XTAL_MODE BIT(1)
#define B_AX_RESET_N_ BIT(0)
#define R_AX_GPIO0_7_FUNC_SEL 0x02D0
#define B_AX_PINMUX_GPIO7_FUNC_SEL_SH 28
#define B_AX_PINMUX_GPIO7_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO6_FUNC_SEL_SH 24
#define B_AX_PINMUX_GPIO6_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO5_FUNC_SEL_SH 20
#define B_AX_PINMUX_GPIO5_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO4_FUNC_SEL_SH 16
#define B_AX_PINMUX_GPIO4_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO3_FUNC_SEL_SH 12
#define B_AX_PINMUX_GPIO3_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO2_FUNC_SEL_SH 8
#define B_AX_PINMUX_GPIO2_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO1_FUNC_SEL_SH 4
#define B_AX_PINMUX_GPIO1_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO0_FUNC_SEL_SH 0
#define B_AX_PINMUX_GPIO0_FUNC_SEL_MSK 0xf
#define R_AX_GPIO8_15_FUNC_SEL 0x02D4
#define B_AX_PINMUX_GPIO15_FUNC_SEL_SH 28
#define B_AX_PINMUX_GPIO15_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO14_FUNC_SEL_SH 24
#define B_AX_PINMUX_GPIO14_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO13_FUNC_SEL_SH 20
#define B_AX_PINMUX_GPIO13_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO12_FUNC_SEL_SH 16
#define B_AX_PINMUX_GPIO12_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO11_FUNC_SEL_SH 12
#define B_AX_PINMUX_GPIO11_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO10_FUNC_SEL_SH 8
#define B_AX_PINMUX_GPIO10_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO9_FUNC_SEL_SH 4
#define B_AX_PINMUX_GPIO9_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_GPIO8_FUNC_SEL_SH 0
#define B_AX_PINMUX_GPIO8_FUNC_SEL_MSK 0xf
#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
#define B_AX_PINMUX_LED1_FUNC_SEL_SH 8
#define B_AX_PINMUX_LED1_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_EESK_FUNC_SEL_SH 4
#define B_AX_PINMUX_EESK_FUNC_SEL_MSK 0xf
#define B_AX_PINMUX_EECS_FUNC_SEL_SH 0
#define B_AX_PINMUX_EECS_FUNC_SEL_MSK 0xf
#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_HIGH_EN 0x02E0
#define B_AX_LED1_PULL_HIGH_EN BIT(18)
#define B_AX_EESK_PULL_HIGH_EN BIT(17)
#define B_AX_EECS_PULL_HIGH_EN BIT(16)
#define B_AX_GPIO15_PULL_HIGH_EN BIT(15)
#define B_AX_GPIO14_PULL_HIGH_EN BIT(14)
#define B_AX_GPIO13_PULL_HIGH_EN BIT(13)
#define B_AX_GPIO12_PULL_HIGH_EN BIT(12)
#define B_AX_GPIO11_PULL_HIGH_EN BIT(11)
#define B_AX_GPIO10_PULL_HIGH_EN BIT(10)
#define B_AX_GPIO9_PULL_HIGH_EN BIT(9)
#define B_AX_GPIO8_PULL_HIGH_EN BIT(8)
#define B_AX_GPIO7_PULL_HIGH_EN BIT(7)
#define B_AX_GPIO6_PULL_HIGH_EN BIT(6)
#define B_AX_GPIO5_PULL_HIGH_EN BIT(5)
#define B_AX_GPIO4_PULL_HIGH_EN BIT(4)
#define B_AX_GPIO3_PULL_HIGH_EN BIT(3)
#define B_AX_GPIO2_PULL_HIGH_EN BIT(2)
#define B_AX_GPIO1_PULL_HIGH_EN BIT(1)
#define B_AX_GPIO0_PULL_HIGH_EN BIT(0)
#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
#define B_AX_LED1_PULL_LOW_EN BIT(18)
#define B_AX_EESK_PULL_LOW_EN BIT(17)
#define B_AX_EECS_PULL_LOW_EN BIT(16)
#define B_AX_GPIO15_PULL_LOW_EN BIT(15)
#define B_AX_GPIO14_PULL_LOW_EN BIT(14)
#define B_AX_GPIO13_PULL_LOW_EN BIT(13)
#define B_AX_GPIO12_PULL_LOW_EN BIT(12)
#define B_AX_GPIO11_PULL_LOW_EN BIT(11)
#define B_AX_GPIO10_PULL_LOW_EN BIT(10)
#define B_AX_GPIO9_PULL_LOW_EN BIT(9)
#define B_AX_GPIO8_PULL_LOW_EN BIT(8)
#define B_AX_GPIO7_PULL_LOW_EN BIT(7)
#define B_AX_GPIO6_PULL_LOW_EN BIT(6)
#define B_AX_GPIO5_PULL_LOW_EN BIT(5)
#define B_AX_GPIO4_PULL_LOW_EN BIT(4)
#define B_AX_GPIO3_PULL_LOW_EN BIT(3)
#define B_AX_GPIO2_PULL_LOW_EN BIT(2)
#define B_AX_GPIO1_PULL_LOW_EN BIT(1)
#define B_AX_GPIO0_PULL_LOW_EN BIT(0)
#define R_AX_WLRF_CTRL 0x02F0
#define B_AX_AFC_AFEDIG BIT(17)
#define B_AX_WLRF1_CTRL_7 BIT(15)
#define B_AX_WLRF1_CTRL_6 BIT(14)
#define B_AX_WLRF1_CTRL_5 BIT(13)
#define B_AX_WLRF1_CTRL_4 BIT(12)
#define B_AX_WLRF1_CTRL_3 BIT(11)
#define B_AX_WLRF1_CTRL_2 BIT(10)
#define B_AX_WLRF1_CTRL_1 BIT(9)
#define B_AX_WLRF1_CTRL_0 BIT(8)
#define B_AX_WLRF_CTRL_7 BIT(7)
#define B_AX_WLRF_CTRL_6 BIT(6)
#define B_AX_WLRF_CTRL_5 BIT(5)
#define B_AX_WLRF_CTRL_4 BIT(4)
#define B_AX_WLRF_CTRL_3 BIT(3)
#define B_AX_WLRF_CTRL_2 BIT(2)
#define B_AX_WLRF_CTRL_1 BIT(1)
#define B_AX_WLRF_CTRL_0 BIT(0)
#define R_AX_TMETER 0x0390
#define B_AX_TEMP_VALID BIT(31)
#define B_AX_TEMP_VALUE_SH 24
#define B_AX_TEMP_VALUE_MSK 0x3f
#define B_AX_REG_TMETER_TIMER_SH 8
#define B_AX_REG_TMETER_TIMER_MSK 0xfff
#define B_AX_REG_TEMP_DELTA_SH 2
#define B_AX_REG_TEMP_DELTA_MSK 0x3f
#define B_AX_REG_TMETER_EN BIT(0)
#define B_AX_OSC_32K_CLKGEN_0_SH 16
#define B_AX_OSC_32K_CLKGEN_0_MSK 0xffff
#define B_AX_OSC_32K_RES_COMP_SH 4
#define B_AX_OSC_32K_RES_COMP_MSK 0x3
#define B_AX_OSC_32K_OUT_SEL BIT(3)
#define B_AX_ISO_WL_2_OSC_32K BIT(1)
#define B_AX_POW_CKGEN BIT(0)
#define B_AX_CAL_32K_DBGMOD BIT(28)
#define B_AX_CAL32K_WR BIT(23)
#define B_AX_CAL_OSC_XTAL_SEL BIT(22)
#define R_AX_32K_CAL_REG1 0x039C
#define B_AX_OSC32K_RCAL_SEL BIT(31)
#define B_AX_OSC32K_RCAL_RPT_SH 16
#define B_AX_OSC32K_RCAL_RPT_MSK 0x7fff
#define B_AX_OSC32K_RCAL_SH 0
#define B_AX_OSC32K_RCAL_MSK 0x7fff
#define R_AX_IC_PWR_STATE 0x03F0
#define B_AX_WHOLE_SYS_PWR_STE_SH 16
#define B_AX_WHOLE_SYS_PWR_STE_MSK 0x3ff
#define B_AX_WLMAC_PWR_STE_SH 8
#define B_AX_WLMAC_PWR_STE_MSK 0x3
#define B_AX_UART_HCISYS_PWR_STE_SH 6
#define B_AX_UART_HCISYS_PWR_STE_MSK 0x3
#define B_AX_SDIO_HCISYS_PWR_STE_SH 4
#define B_AX_SDIO_HCISYS_PWR_STE_MSK 0x3
#define B_AX_USB_HCISYS_PWR_STE_SH 2
#define B_AX_USB_HCISYS_PWR_STE_MSK 0x3
#define B_AX_PCIE_HCISYS_PWR_STE_SH 0
#define B_AX_PCIE_HCISYS_PWR_STE_MSK 0x3
#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
#define B_AX_SDZN_L_SH 30
#define B_AX_SDZN_L_MSK 0x3
#define B_AX_REG_AUTOZCD_L BIT(29)
#define B_AX_REG_VOFB_SEL BIT(28)
#define B_AX_TBOX_L1_SH 26
#define B_AX_TBOX_L1_MSK 0x3
#define B_AX_ENOCPMUX_L BIT(25)
#define B_AX_FORCE_LDOS BIT(24)
#define B_AX_VO_DISCHG BIT(23)
#define B_AX_LDO_OC_CLAMP BIT(22)
#define B_AX_MINOFF_LIQ BIT(21)
#define B_AX_MINON_LIQ BIT(20)
#define B_AX_POW_AUTO_L BIT(19)
#define B_AX_ARENB_H BIT(18)
#define B_AX_NO_OFFTIME_L BIT(17)
#define B_AX_EN_ON_END_L BIT(16)
#define B_AX_ENCOT_L BIT(15)
#define B_AX_REG_CLK_SEL_SH 13
#define B_AX_REG_CLK_SEL_MSK 0x3
#define B_AX_REG_TYPE_L BIT(12)
#define B_AX_R3_L1_SH 10
#define B_AX_R3_L1_MSK 0x3
#define B_AX_R2_L1_SH 8
#define B_AX_R2_L1_MSK 0x3
#define B_AX_R1_L1_SH 6
#define B_AX_R1_L1_MSK 0x3
#define B_AX_C3_L1_SH 4
#define B_AX_C3_L1_MSK 0x3
#define B_AX_C2_L1_SH 2
#define B_AX_C2_L1_MSK 0x3
#define B_AX_C1_L1_SH 0
#define B_AX_C1_L1_MSK 0x3
#define R_AX_SPS_DIG_OFF_CTRL1 0x0404
#define B_AX_REG_NMOS_OFF_L BIT(5)
#define B_AX_REG_MUX_PI_L BIT(4)
#define B_AX_REG_PWM_CTRL_L BIT(3)
#define B_AX_ENSR_L BIT(2)
#define B_AX_SDZP_L_SH 0
#define B_AX_SDZP_L_MSK 0x3
#define R_AX_SPSLDO_OFF_CTRL0 0x0400
#define B_AX_SDZN_L_SH 30
#define B_AX_SDZN_L_MSK 0x3
#define B_AX_REG_AUTOZCD_L BIT(29)
#define B_AX_REG_VOFB_SEL BIT(28)
#define B_AX_TBOX_L1_SH 26
#define B_AX_TBOX_L1_MSK 0x3
#define B_AX_ENOCPMUX_L BIT(25)
#define B_AX_FORCE_LDOS BIT(24)
#define B_AX_VO_DISCHG BIT(23)
#define B_AX_LDO_OC_CLAMP BIT(22)
#define B_AX_MINOFF_LIQ BIT(21)
#define B_AX_MINON_LIQ BIT(20)
#define B_AX_POW_AUTO_L BIT(19)
#define B_AX_ARENB_H BIT(18)
#define B_AX_NO_OFFTIME_L BIT(17)
#define B_AX_EN_ON_END_L BIT(16)
#define B_AX_ENCOT_L BIT(15)
#define B_AX_REG_CLK_SEL_SH 13
#define B_AX_REG_CLK_SEL_MSK 0x3
#define B_AX_REG_TYPE_L BIT(12)
#define B_AX_R3_L1_SH 10
#define B_AX_R3_L1_MSK 0x3
#define B_AX_R2_L1_SH 8
#define B_AX_R2_L1_MSK 0x3
#define B_AX_R1_L1_SH 6
#define B_AX_R1_L1_MSK 0x3
#define B_AX_C3_L1_SH 4
#define B_AX_C3_L1_MSK 0x3
#define B_AX_C2_L1_SH 2
#define B_AX_C2_L1_MSK 0x3
#define B_AX_C1_L1_SH 0
#define B_AX_C1_L1_MSK 0x3
#define R_AX_SPSLDO_OFF_CTRL1 0x0404
#define B_AX_REG_NMOS_OFF_L BIT(5)
#define B_AX_REG_MUX_PI_L BIT(4)
#define B_AX_REG_PWM_CTRL_L BIT(3)
#define B_AX_ENSR_L BIT(2)
#define B_AX_SDZP_L_SH 0
#define B_AX_SDZP_L_MSK 0x3
#define R_AX_SPSANA_OFF_CTRL0 0x0420
#define B_AX_REG_AUTOZCD_L BIT(29)
#define B_AX_REG_VOFB_SEL BIT(28)
#define B_AX_ENOCPMUX_L BIT(25)
#define B_AX_FORCE_LDOS BIT(24)
#define B_AX_VO_DISCHG BIT(23)
#define B_AX_LDO_OC_CLAMP BIT(22)
#define B_AX_MINOFF_LIQ BIT(21)
#define B_AX_MINON_LIQ BIT(20)
#define B_AX_POW_AUTO_L BIT(19)
#define B_AX_ARENB_H BIT(18)
#define B_AX_NO_OFFTIME_L BIT(17)
#define B_AX_EN_ON_END_L BIT(16)
#define B_AX_ENCOT_L BIT(15)
#define B_AX_REG_TYPE_L BIT(12)
#define R_AX_SPSANA_OFF_CTRL1 0x0424
#define B_AX_REG_NMOS_OFF_L BIT(5)
#define B_AX_REG_MUX_PI_L BIT(4)
#define B_AX_REG_PWM_CTRL_L BIT(3)
#define B_AX_ENSR_L BIT(2)
#define R_AX_AFE_OFF_CTRL0 0x0440
#define B_AX_S1_AD0_LDO2PWRCUT BIT(31)
#define B_AX_S1_AD_SEL_Q_SH 27
#define B_AX_S1_AD_SEL_Q_MSK 0xf
#define B_AX_S1_AD_SEL_I_SH 23
#define B_AX_S1_AD_SEL_I_MSK 0xf
#define B_AX_S0_DA1_LDO_VSEL_SH 21
#define B_AX_S0_DA1_LDO_VSEL_MSK 0x3
#define B_AX_S0_DA1_LDO2PWRCUT BIT(20)
#define B_AX_S0_DA0_LDO_VSEL_SH 18
#define B_AX_S0_DA0_LDO_VSEL_MSK 0x3
#define B_AX_S0_DA0_LDO2PWRCUT BIT(17)
#define B_AX_S0_AD2_LDO_VSEL_SH 15
#define B_AX_S0_AD2_LDO_VSEL_MSK 0x3
#define B_AX_S0_AD2_LDO2PWRCUT BIT(14)
#define B_AX_S0_AD1_LDO_VSEL_SH 12
#define B_AX_S0_AD1_LDO_VSEL_MSK 0x3
#define B_AX_S0_AD1_LDO2PWRCUT BIT(11)
#define B_AX_S0_AD0_LDO_VSEL_SH 9
#define B_AX_S0_AD0_LDO_VSEL_MSK 0x3
#define B_AX_S0_AD0_LDO2PWRCUT BIT(8)
#define B_AX_S0_AD_SEL_Q_SH 4
#define B_AX_S0_AD_SEL_Q_MSK 0xf
#define B_AX_S0_AD_SEL_I_SH 0
#define B_AX_S0_AD_SEL_I_MSK 0xf
#define R_AX_AFE_OFF_CTRL1 0x0444
#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL_SH 24
#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL_MSK 0x3
#define B_AX_S1_DAI2V_LDO2PWRCUT BIT(23)
#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL__SH 21
#define B_AX_S0_DAI2V_LDO2PW__LDO_VSEL__MSK 0x3
#define B_AX_S0_DAI2V_LDO2PWRCUT BIT(20)
#define B_AX_S0_RXBB__LDO_VSEL_SH 18
#define B_AX_S0_RXBB__LDO_VSEL_MSK 0x3
#define B_AX_S0_RXBB__LDO2PWRCUT BIT(17)
#define B_AX_S0_RXBB__LDO_VSEL__SH 15
#define B_AX_S0_RXBB__LDO_VSEL__MSK 0x3
#define B_AX_S0_RXBB_LDO2PWRCUT BIT(14)
#define B_AX_S1_DA1_LDO_VSEL_SH 12
#define B_AX_S1_DA1_LDO_VSEL_MSK 0x3
#define B_AX_S1_DA1_LDO2PWRCUT BIT(11)
#define B_AX_S1_DA0_LDO_VSEL_SH 9
#define B_AX_S1_DA0_LDO_VSEL_MSK 0x3
#define B_AX_S1_DA0_LDO2PWRCUT BIT(8)
#define B_AX_S1_AD2_LDO_VSEL_SH 6
#define B_AX_S1_AD2_LDO_VSEL_MSK 0x3
#define B_AX_S1_AD2_LDO2PWRCUT BIT(5)
#define B_AX_S1_AD1_LDO_VSEL_SH 3
#define B_AX_S1_AD1_LDO_VSEL_MSK 0x3
#define B_AX_S1_AD1_LDO2PWRCUT BIT(2)
#define B_AX_S1_AD0_LDO_VSEL_SH 0
#define B_AX_S1_AD0_LDO_VSEL_MSK 0x3
#define R_AX_XTAL_OFF_CTRL0 0x0480
#define B_AX_XTAL_PK_SEL_OFFSET BIT(31)
#define B_AX_XTAL_MANU_PK_SEL_SH 29
#define B_AX_XTAL_MANU_PK_SEL_MSK 0x3
#define B_AX_XTAL_AACK_PK_MANU BIT(28)
#define B_AX_EN_XTAL_AAC_PKDET BIT(27)
#define B_AX_EN_XTAL_AAC_GM BIT(26)
#define B_AX_XTAL_LDO_OPVB_SEL BIT(25)
#define B_AX_XTAL_LDO_NC BIT(24)
#define B_AX_XTAL_LPMODE BIT(23)
#define B_AX_XTAL_DELAY_DIGI BIT(22)
#define B_AX_XTAL_DELAY_USB BIT(21)
#define B_AX_XTAL_DELAY_AFE BIT(20)
#define B_AX_XTAL_DRV_BT_SH 18
#define B_AX_XTAL_DRV_BT_MSK 0x3
#define B_AX_XTAL_DRV_DIGI_SH 16
#define B_AX_XTAL_DRV_DIGI_MSK 0x3
#define B_AX_XTAL_DRV_USB_SH 14
#define B_AX_XTAL_DRV_USB_MSK 0x3
#define B_AX_XTAL_DRV_AFE_SH 12
#define B_AX_XTAL_DRV_AFE_MSK 0x3
#define B_AX_XTAL_DRV_RF2_RELAY_SH 10
#define B_AX_XTAL_DRV_RF2_RELAY_MSK 0x3
#define B_AX_XTAL_DRV_RF2_SH 8
#define B_AX_XTAL_DRV_RF2_MSK 0x3
#define B_AX_XTAL_DRV_RF1_SH 6
#define B_AX_XTAL_DRV_RF1_MSK 0x3
#define B_AX_XTAL_DRV_RF_LATCH BIT(5)
#define B_AX_XTAL_GM_SEP BIT(4)
#define B_AX_XQSEL_RF_AWAKE BIT(3)
#define B_AX_XQSEL_RF_INITIAL BIT(2)
#define B_AX_XQSEL BIT(1)
#define B_AX_GATED_XTAL_OK0 BIT(0)
#define R_AX_XTAL_OFF_CTRL1 0x0484
#define B_AX_XTAL_LDO_VREF_UP_SH 14
#define B_AX_XTAL_LDO_VREF_UP_MSK 0x7
#define B_AX_XTAL_EN_LNBUF BIT(13)
#define B_AX_XTAL__AAC_TIE_MID BIT(12)
#define B_AX_XTAL_AAC_IOFFSET_SH 10
#define B_AX_XTAL_AAC_IOFFSET_MSK 0x3
#define B_AX_XTAL_AAC_CAP_SH 8
#define B_AX_XTAL_AAC_CAP_MSK 0x3
#define B_AX_XTAL_PDSW_SH 6
#define B_AX_XTAL_PDSW_MSK 0x3
#define B_AX_XTAL_LPS_BUF_VB_SH 4
#define B_AX_XTAL_LPS_BUF_VB_MSK 0x3
#define B_AX_XTAL_PDCK_MANU BIT(3)
#define B_AX_XTAL_PDCK_OK_MANU BIT(2)
#define B_AX_EN_XTAL_PDCK_VREF BIT(1)
#define B_AX_XTAL_SEL_PWR BIT(0)
#define R_AX_SYM_ANAPAR_XTAL_AAC_0 0x04A0
#define B_AX_XAAC_LPOW BIT(31)
#define B_AX_AAC_MODE__SH 29
#define B_AX_AAC_MODE__MSK 0x3
#define B_AX_EN_XTAL_AAC_TRIG BIT(28)
#define B_AX_EN_XTAL_AAC BIT(27)
#define B_AX_EN_XTAL_AAC_DIGI BIT(26)
#define B_AX_GM_MANUAL_SH 21
#define B_AX_GM_MANUAL_MSK 0x1f
#define B_AX_GM_STUP_SH 16
#define B_AX_GM_STUP_MSK 0x1f
#define B_AX_XTAL_CK_SET_SH 13
#define B_AX_XTAL_CK_SET_MSK 0x7
#define B_AX_GM_INIT_SH 8
#define B_AX_GM_INIT_MSK 0x1f
#define B_AX_GM_STEP BIT(7)
#define B_AX_XAAC_GM_OFFSET_SH 2
#define B_AX_XAAC_GM_OFFSET_MSK 0x1f
#define B_AX_OFFSET_PLUS BIT(1)
#define B_AX_RESET_N BIT(0)
#define R_AX_SYM_ANAPAR_XTAL_AAC_1 0x04A4
#define B_AX_PK_END_AR_SH 2
#define B_AX_PK_END_AR_MSK 0x3
#define B_AX_PK_START_AR_SH 0
#define B_AX_PK_START_AR_MSK 0x3
#define R_AX_SYM_ANAPAR_XTAL_PDCK 0x04C0
#define B_AX_EN_XTAL_PDCK_DIGI_SH 17
#define B_AX_EN_XTAL_PDCK_DIGI_MSK 0x1f
#define B_AX_PDCK_SEARCH_MODE_SH 15
#define B_AX_PDCK_SEARCH_MODE_MSK 0x3
#define B_AX_PDCK_WAIT_CYC_SH 10
#define B_AX_PDCK_WAIT_CYC_MSK 0x1f
#define B_AX_VREF_MANUAL_SH 5
#define B_AX_VREF_MANUAL_MSK 0x1f
#define B_AX_VREF_INIT_SH 3
#define B_AX_VREF_INIT_MSK 0x3
#define B_AX_XTAL_PDCK_UNIT BIT(2)
#define B_AX_XPDCK_VREF_SEL BIT(1)
#define B_AX_PDCK_LPOW BIT(0)
//
// AON_C
//
#define R_AX_SEC_CTRL 0x0C00
#define B_AX_SEC_IDMEM_SIZE_CONFIG_SH 16
#define B_AX_SEC_IDMEM_SIZE_CONFIG_MSK 0x3
#define B_AX_SEC_BT_SEC1_DIS BIT(15)
#define B_AX_SEC_BT_SEC0_DIS BIT(14)
#define B_AX_SEC_UART_RX_EN BIT(4)
#define B_AX_SEC_UART_TX_EN BIT(3)
#define B_AX_SEC_JTAG_EN BIT(2)
#define B_AX_SEC_SIC_EN BIT(1)
#define B_AX_SEC_SEC_DIS BIT(0)
#define R_AX_FILTER_MODEL_ADDR 0x0C04
#define B_AX_SEC_FILTER_MODEL_ADDR_SH 0
#define B_AX_SEC_FILTER_MODEL_ADDR_MSK 0xffffffffL
#define R_AX_EFUSE_CTRL_S 0x0C30
#define B_AX_EF_MODE_SEL_S_SH 30
#define B_AX_EF_MODE_SEL_S_MSK 0x3
#define B_AX_EF_RDY_S BIT(29)
#define B_AX_EF_ADDR_S_SH 16
#define B_AX_EF_ADDR_S_MSK 0x7ff
#define B_AX_EF_DATA_S_SH 0
#define B_AX_EF_DATA_S_MSK 0xffff
#define R_AX_EFUSE_TEST_S 0x0C34
#define B_AX_EF_CRES_SEL_S BIT(31)
#define B_AX_EF_SCAN_SADR_S_SH 19
#define B_AX_EF_SCAN_SADR_S_MSK 0x7ff
#define B_AX_EF_SCAN_EADR_S_SH 8
#define B_AX_EF_SCAN_EADR_S_MSK 0x7ff
#define B_AX_EF_SCAN_TRPT_S BIT(7)
#define B_AX_EF_SCAN_FTHR_S_SH 0
#define B_AX_EF_SCAN_FTHR_S_MSK 0x7f
//
// WL_AX_Reg_AXIDMA.xls
//
//
// AXIDMA_Reg_Spec
//
#define R_PL_AXIDMA_INIT_CFG1 0x0000
#define B_PL_AXIDMA__MASTER_STOP BIT(20)
#define B_PL_AXIDMA_RESET_KEEP_REG BIT(19)
#define B_PL_AXIDMA_RX_EN BIT(13)
#define B_PL_AXIDMA_TX_EN BIT(11)
#define R_PL_AXIDMA_DMA_STOP 0x0004
#define B_PL_AXIDMA_WPDMA_STOP BIT(12)
#define B_PL_AXIDMA_CH3_TX_STOP BIT(11)
#define B_PL_AXIDMA_CH2_TX_STOP BIT(10)
#define B_PL_AXIDMA_CH1_TX_STOP BIT(9)
#define B_PL_AXIDMA_CH0_TX_STOP BIT(8)
#define R_PL_AXIDMA_INIT_CFG2 0x0008
#define B_PL_AXIDMA_WD_ITVL_ACT_SH 24
#define B_PL_AXIDMA_WD_ITVL_ACT_MSK 0xff
#define B_PL_AXIDMA_WD_ITVL_IDLE_SH 16
#define B_PL_AXIDMA_WD_ITVL_IDLE_MSK 0xff
#define R_PL_AXIDMA_INFO 0x0100
#define B_PL_AXIDMA_MASTER_IDLE BIT(16)
#define B_PL_AXIDMA_RX_IDLE BIT(1)
#define B_PL_AXIDMA_TX_IDLE BIT(0)
#define R_PL_AXIDMA_BUSY 0x0104
#define B_PL_AXIDMA_WPDMA_BUSY BIT(12)
#define B_PL_AXIDMA_CH3_TX_BUSY BIT(11)
#define B_PL_AXIDMA_CH2_TX_BUSY BIT(10)
#define B_PL_AXIDMA_CH1_TX_BUSY BIT(9)
#define B_PL_AXIDMA_CH0_TX_BUSY BIT(8)
#define B_PL_AXIDMA_CH5_RX_BUSY BIT(5)
#define B_PL_AXIDMA_CH4_RX_BUSY BIT(4)
#define B_PL_AXIDMA_CH3_RX_BUSY BIT(3)
#define B_PL_AXIDMA_CH2_RX_BUSY BIT(2)
#define B_PL_AXIDMA_CH1_RX_BUSY BIT(1)
#define B_PL_AXIDMA_CH0_RX_BUSY BIT(0)
#define R_PL_AXIDMA_INT_MIT_TX 0x0200
#define B_PL_AXIDMA_TXMIT_CH3_SEL BIT(22)
#define B_PL_AXIDMA_TXMIT_CH2_SEL BIT(21)
#define B_PL_AXIDMA_TXMIT_CH1_SEL BIT(20)
#define B_PL_AXIDMA_TXMIT_CH0_SEL BIT(19)
#define B_PL_AXIDMA_TXTIMER_UNIT_SH 16
#define B_PL_AXIDMA_TXTIMER_UNIT_MSK 0x3
#define B_PL_AXIDMA_TXCOUNTER_MATCH_SH 8
#define B_PL_AXIDMA_TXCOUNTER_MATCH_MSK 0xff
#define B_PL_AXIDMA_TXTIMER_MATCH_SH 0
#define B_PL_AXIDMA_TXTIMER_MATCH_MSK 0xff
#define R_PL_AXIDMA_INT_MIT_RX 0x0204
#define B_PL_AXIDMA_RXMIT_CH5_SEL BIT(24)
#define B_PL_AXIDMA_RXMIT_CH4_SEL BIT(23)
#define B_PL_AXIDMA_RXMIT_CH3_SEL BIT(22)
#define B_PL_AXIDMA_RXMIT_CH2_SEL BIT(21)
#define B_PL_AXIDMA_RXMIT_CH1_SEL BIT(20)
#define B_PL_AXIDMA_RXMIT_CH0_SEL BIT(19)
#define B_PL_AXIDMA_RXTIMER_UNIT_SH 16
#define B_PL_AXIDMA_RXTIMER_UNIT_MSK 0x3
#define B_PL_AXIDMA_RXCOUNTER_MATCH_SH 8
#define B_PL_AXIDMA_RXCOUNTER_MATCH_MSK 0xff
#define B_PL_AXIDMA_RXTIMER_MATCH_SH 0
#define B_PL_AXIDMA_RXTIMER_MATCH_MSK 0xff
#define R_PL_AXIDMA_CH0_RXBD_NUM 0x0300
#define B_PL_AXIDMA_CH0_RXBD_NUM_SH 0
#define B_PL_AXIDMA_CH0_RXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH1_RXBD_NUM 0x0302
#define B_PL_AXIDMA_CH1_RXBD_NUM_SH 0
#define B_PL_AXIDMA_CH1_RXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH2_RXBD_NUM 0x0304
#define B_PL_AXIDMA_CH2_RXBD_NUM_SH 0
#define B_PL_AXIDMA_CH2_RXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH3_RXBD_NUM 0x0306
#define B_PL_AXIDMA_CH3_RXBD_NUM_SH 0
#define B_PL_AXIDMA_CH3_RXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH4_RXBD_NUM 0x0308
#define B_PL_AXIDMA_CH4_RXBD_NUM_SH 0
#define B_PL_AXIDMA_CH4_RXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH5_RXBD_NUM 0x030A
#define B_PL_AXIDMA_CH5_RXBD_NUM_SH 0
#define B_PL_AXIDMA_CH5_RXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH0_TXBD_NUM 0x0320
#define B_PL_AXIDMA_CH0_TXBD_FLAG BIT(14)
#define B_PL_AXIDMA_CH0_TXBD_NUM_SH 0
#define B_PL_AXIDMA_CH0_TXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH1_TXBD_NUM 0x0322
#define B_PL_AXIDMA_CH1_TXBD_FLAG BIT(14)
#define B_PL_AXIDMA_CH1_TXBD_NUM_SH 0
#define B_PL_AXIDMA_CH1_TXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH2_TXBD_NUM 0x0324
#define B_PL_AXIDMA_CH2_TXBD_FLAG BIT(14)
#define B_PL_AXIDMA_CH2_TXBD_NUM_SH 0
#define B_PL_AXIDMA_CH2_TXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH3_TXBD_NUM 0x0326
#define B_PL_AXIDMA_CH3_TXBD_FLAG BIT(14)
#define B_PL_AXIDMA_CH3_TXBD_NUM_SH 0
#define B_PL_AXIDMA_CH3_TXBD_NUM_MSK 0xfff
#define R_PL_AXIDMA_CH0_RXBD_IDX 0x0400
#define B_PL_AXIDMA_CH0_RX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH0_RX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH0_RX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH0_RX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH1_RXBD_IDX 0x0404
#define B_PL_AXIDMA_CH1_RX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH1_RX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH1_RX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH1_RX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH2_RXBD_IDX 0x0408
#define B_PL_AXIDMA_CH2_RX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH2_RX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH2_RX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH2_RX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH3_RXBD_IDX 0x040C
#define B_PL_AXIDMA_CH3_RX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH3_RX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH3_RX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH3_RX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH4_RXBD_IDX 0x0410
#define B_PL_AXIDMA_CH4_RX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH4_RX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH4_RX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH4_RX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH5_RXBD_IDX 0x0414
#define B_PL_AXIDMA_CH5_RX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH5_RX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH5_RX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH5_RX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH0_TXBD_IDX 0x0420
#define B_PL_AXIDMA_CH0_TX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH0_TX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH0_TX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH0_TX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH1_TXBD_IDX 0x0424
#define B_PL_AXIDMA_CH1_TX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH1_TX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH1_TX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH1_TX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH2_TXBD_IDX 0x0428
#define B_PL_AXIDMA_CH2_TX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH2_TX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH2_TX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH2_TX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_CH3_TXBD_IDX 0x042C
#define B_PL_AXIDMA_CH3_TX_HW_IDX_SH 16
#define B_PL_AXIDMA_CH3_TX_HW_IDX_MSK 0xfff
#define B_PL_AXIDMA_CH3_TX_HOST_IDX_SH 0
#define B_PL_AXIDMA_CH3_TX_HOST_IDX_MSK 0xfff
#define R_PL_AXIDMA_TXBD_RWPTR_CLR 0x0430
#define B_PL_AXIDMA_CLR_CH3_TX_IDX BIT(3)
#define B_PL_AXIDMA_CLR_CH2_TX_IDX BIT(2)
#define B_PL_AXIDMA_CLR_CH1_TX_IDX BIT(1)
#define B_PL_AXIDMA_CLR_CH0_TX_IDX BIT(0)
#define R_PL_AXIDMA_RXBD_RWPTR_CLR 0x0434
#define B_PL_AXIDMA_CLR_CH5_RX_IDX BIT(5)
#define B_PL_AXIDMA_CLR_CH4_RX_IDX BIT(4)
#define B_PL_AXIDMA_CLR_CH3_RX_IDX BIT(3)
#define B_PL_AXIDMA_CLR_CH2_RX_IDX BIT(2)
#define B_PL_AXIDMA_CLR_CH1_RX_IDX BIT(1)
#define B_PL_AXIDMA_CLR_CH0_RX_IDX BIT(0)
#define R_PL_AXIDMA_DBG_CTRL 0x0500
#define B_PL_AXIDMA_DBG_SEL_SH 16
#define B_PL_AXIDMA_DBG_SEL_MSK 0x1ff
#define B_PL_AXIDMA_SEC_ACCESS BIT(2)
#define B_PL_AXIDMA_EN_STUCK_DBG BIT(0)
#define R_PL_AXIDMA_DBG_ERR_FLAG 0x0504
#define B_PL_AXIDMA_CH1_RX_FULL BIT(29)
#define B_PL_AXIDMA_CH0_RX_FULL BIT(28)
#define B_PL_AXIDMA_RX_STUCK BIT(22)
#define B_PL_AXIDMA_TX_STUCK BIT(21)
#define B_PL_AXIDMA_DBG_TXERR BIT(16)
#define B_PL_AXIDMA_CH5_RX_FULL BIT(5)
#define B_PL_AXIDMA_CH4_RX_FULL BIT(4)
#define B_PL_AXIDMA_CH3_RX_FULL BIT(3)
#define B_PL_AXIDMA_CH2_RX_FULL BIT(2)
#define B_PL_AXIDMA_TXBD_LEN0 BIT(1)
#define B_PL_AXIDMA_TXBD_4KBOUD_LENERR BIT(0)
#define R_PL_AXIDMA_CH0_RXBD_DESA_L 0x0600
#define B_PL_AXIDMA_CH0_RXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH0_RXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH1_RXBD_DESA_L 0x0608
#define B_PL_AXIDMA_CH1_RXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH1_RXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH2_RXBD_DESA_L 0x0610
#define B_PL_AXIDMA_CH2_RXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH2_RXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH3_RXBD_DESA_L 0x0618
#define B_PL_AXIDMA_CH3_RXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH3_RXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH4_RXBD_DESA_L 0x0620
#define B_PL_AXIDMA_CH4_RXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH4_RXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH5_RXBD_DESA_L 0x0628
#define B_PL_AXIDMA_CH5_RXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH5_RXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH0_TXBD_DESA_L 0x0640
#define B_PL_AXIDMA_CH0_TXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH0_TXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH1_TXBD_DESA_L 0x0648
#define B_PL_AXIDMA_CH1_TXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH1_TXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH2_TXBD_DESA_L 0x0650
#define B_PL_AXIDMA_CH2_TXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH2_TXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_CH3_TXBD_DESA_L 0x0658
#define B_PL_AXIDMA_CH3_TXBD_DESA_L_SH 0
#define B_PL_AXIDMA_CH3_TXBD_DESA_L_MSK 0xffffffffL
#define R_PL_AXIDMA_FC_CTRL1 0x0700
#define B_PL_AXIDMA_FC_MODE BIT(2)
#define B_PL_AXIDMA_SET1_FC_EN BIT(1)
#define B_PL_AXIDMA_SET0_FC_EN BIT(0)
#define R_PL_AXIDMA_FC_CTRL2 0x0704
#define B_PL_AXIDMA_SET1_PREC_PAGE_SH 16
#define B_PL_AXIDMA_SET1_PREC_PAGE_MSK 0x1ff
#define B_PL_AXIDMA_SET0_PREC_PAGE_SH 0
#define B_PL_AXIDMA_SET0_PREC_PAGE_MSK 0x1ff
#define R_PL_AXIDMA_CH1_PAGE_CTRL 0x0710
#define B_PL_AXIDMA_CH1_GRP BIT(31)
#define B_PL_AXIDMA_CH1_MAX_PG_SH 16
#define B_PL_AXIDMA_CH1_MAX_PG_MSK 0x1fff
#define B_PL_AXIDMA_CH1_MIN_PG_SH 0
#define B_PL_AXIDMA_CH1_MIN_PG_MSK 0x1fff
#define R_PL_AXIDMA_CH3_PAGE_CTRL 0x0714
#define B_PL_AXIDMA_CH3_GRP BIT(31)
#define B_PL_AXIDMA_CH3_MAX_PG_SH 16
#define B_PL_AXIDMA_CH3_MAX_PG_MSK 0x1fff
#define B_PL_AXIDMA_CH3_MIN_PG_SH 0
#define B_PL_AXIDMA_CH3_MIN_PG_MSK 0x1fff
#define R_PL_AXIDMA_CH1_PAGE_INFO 0x0720
#define B_PL_AXIDMA_CH1_AVAIL_PG_SH 16
#define B_PL_AXIDMA_CH1_AVAIL_PG_MSK 0x1fff
#define B_PL_AXIDMA_CH1_USE_PG_SH 0
#define B_PL_AXIDMA_CH1_USE_PG_MSK 0x1fff
#define R_PL_AXIDMA_CH3_PAGE_INFO 0x0724
#define B_PL_AXIDMA_CH3_AVAIL_PG_SH 16
#define B_PL_AXIDMA_CH3_AVAIL_PG_MSK 0x1fff
#define B_PL_AXIDMA_CH3_USE_PG_SH 0
#define B_PL_AXIDMA_CH3_USE_PG_MSK 0x1fff
#define R_PL_AXIDMA_SET0_PUB_PAGE_INFO 0x0730
#define B_PL_AXIDMA_SET0_AVAL_PUBPG_SH 0
#define B_PL_AXIDMA_SET0_AVAL_PUBPG_MSK 0x1fff
#define R_PL_AXIDMA_SET1_PUB_PAGE_CTRL1 0x0740
#define B_PL_AXIDMA_SET1_G1_MAX_PUBPG_SH 16
#define B_PL_AXIDMA_SET1_G1_MAX_PUBPG_MSK 0x1fff
#define B_PL_AXIDMA_SET1_G0_MAX_PUBPG_SH 0
#define B_PL_AXIDMA_SET1_G0_MAX_PUBPG_MSK 0x1fff
#define R_PL_AXIDMA_SET1_PUB_PAGE_CTRL2 0x0744
#define B_PL_AXIDMA_SET1_ALL_MAX_PUBPG_SH 0
#define B_PL_AXIDMA_SET1_ALL_MAX_PUBPG_MSK 0x1fff
#define R_PL_AXIDMA_SET1_PUB_PAGE_INFO1 0x0748
#define B_PL_AXIDMA_SET1_G1_USE_PUBPG_SH 16
#define B_PL_AXIDMA_SET1_G1_USE_PUBPG_MSK 0x1fff
#define B_PL_AXIDMA_SET1_G0_USE_PUBPG_SH 0
#define B_PL_AXIDMA_SET1_G0_USE_PUBPG_MSK 0x1fff
#define R_PL_AXIDMA_SET1_PUB_PAGE_INFO2 0x074C
#define B_PL_AXIDMA_SET1_AVAL_PUBPG_SH 0
#define B_PL_AXIDMA_SET1_AVAL_PUBPG_MSK 0x1fff
#define R_PL_AXIDMA_SET1_PUB_PAGE_INFO3 0x0750
#define B_PL_AXIDMA_SET1_G1_AVAL_PUBPG_SH 16
#define B_PL_AXIDMA_SET1_G1_AVAL_PUBPG_MSK 0x1fff
#define B_PL_AXIDMA_SET1_G0_AVAL_PUBPG_SH 0
#define B_PL_AXIDMA_SET1_G0_AVAL_PUBPG_MSK 0x1fff
#define R_PL_AXIDMA_WP_PAGE_CTRL1 0x0760
#define B_PL_AXIDMA_PREC_PAGE_WP_SH 16
#define B_PL_AXIDMA_PREC_PAGE_WP_MSK 0x1ff
#define R_PL_AXIDMA_WP_PAGE_CTRL2 0x0764
#define B_PL_AXIDMA_WP_THRD_SH 0
#define B_PL_AXIDMA_WP_THRD_MSK 0x1fff
#define R_PL_AXIDMA_WP_PAGE_INFO 0x0768
#define B_PL_AXIDMA_WP_AVAL_PG_SH 16
#define B_PL_AXIDMA_WP_AVAL_PG_MSK 0x1fff
#define R_PL_AXIDMA_FC_ERR_FLAG 0x0770
#define B_PL_AXIDMA_SET1_PUB_USE_PG_OFW BIT(24)
#define B_PL_AXIDMA_SET1_PUB_USE_PG_UFW BIT(23)
#define B_PL_AXIDMA_SET1_USE_PG_OFW BIT(22)
#define B_PL_AXIDMA_SET1_USE_PG_UFW BIT(21)
#define B_PL_AXIDMA_SET1_AVAL_PG_OFW BIT(20)
#define B_PL_AXIDMA_SET1_AVAL_PG_UFW BIT(19)
#define B_PL_AXIDMA_SET1_WP_REQ_PG_ERR BIT(18)
#define B_PL_AXIDMA_SET1_REQ_PG_ERR BIT(16)
#define B_PL_AXIDMA_SET0_REQ_PG_ERR BIT(0)
#define R_PL_AXIDMA_FWIMR0 0x0900
#define B_PL_AXIDMA_CH5_RX_RDU_MSK BIT(21)
#define B_PL_AXIDMA_CH4_RX_RDU_MSK BIT(20)
#define B_PL_AXIDMA_CH3_RX_RDU_MSK BIT(19)
#define B_PL_AXIDMA_CH2_RX_RDU_MSK BIT(18)
#define B_PL_AXIDMA_CH1_RX_RDU_MSK BIT(17)
#define B_PL_AXIDMA_CH0_RX_RDU_MSK BIT(16)
#define B_PL_AXIDMA_CH5_RX_DERR_MSK BIT(13)
#define B_PL_AXIDMA_CH4_RX_DERR_MSK BIT(12)
#define B_PL_AXIDMA_CH3_RX_DERR_MSK BIT(11)
#define B_PL_AXIDMA_CH2_RX_DERR_MSK BIT(10)
#define B_PL_AXIDMA_CH1_RX_DERR_MSK BIT(9)
#define B_PL_AXIDMA_CH0_RX_DERR_MSK BIT(8)
#define B_PL_AXIDMA_CH5_RX_DOK_MSK BIT(5)
#define B_PL_AXIDMA_CH4_RX_DOK_MSK BIT(4)
#define B_PL_AXIDMA_CH3_RX_DOK_MSK BIT(3)
#define B_PL_AXIDMA_CH2_RX_DOK_MSK BIT(2)
#define B_PL_AXIDMA_CH1_RX_DOK_MSK BIT(1)
#define B_PL_AXIDMA_CH0_RX_DOK_MSK BIT(0)
#define R_PL_AXIDMA_FWIMR1 0x0904
#define B_PL_AXIDMA_CH3_TX_DERR_MSK BIT(11)
#define B_PL_AXIDMA_CH2_TX_DERR_MSK BIT(10)
#define B_PL_AXIDMA_CH1_TX_DERR_MSK BIT(9)
#define B_PL_AXIDMA_CH0_TX_DERR_MSK BIT(8)
#define B_PL_AXIDMA_CH3_TX_DOK_MSK BIT(3)
#define B_PL_AXIDMA_CH2_TX_DOK_MSK BIT(2)
#define B_PL_AXIDMA_CH1_TX_DOK_MSK BIT(1)
#define B_PL_AXIDMA_CH0_TX_DOK_MSK BIT(0)
#define R_PL_AXIDMA_FWISR0 0x0908
#define B_PL_AXIDMA_CH5_RX_RDU BIT(21)
#define B_PL_AXIDMA_CH4_RX_RDU BIT(20)
#define B_PL_AXIDMA_CH3_RX_RDU BIT(19)
#define B_PL_AXIDMA_CH2_RX_RDU BIT(18)
#define B_PL_AXIDMA_CH1_RX_RDU BIT(17)
#define B_PL_AXIDMA_CH0_RX_RDU BIT(16)
#define B_PL_AXIDMA_CH5_RX_DERR BIT(13)
#define B_PL_AXIDMA_CH4_RX_DERR BIT(12)
#define B_PL_AXIDMA_CH3_RX_DERR BIT(11)
#define B_PL_AXIDMA_CH2_RX_DERR BIT(10)
#define B_PL_AXIDMA_CH1_RX_DERR BIT(9)
#define B_PL_AXIDMA_CH0_RX_DERR BIT(8)
#define B_PL_AXIDMA_CH5_RX_DOK BIT(5)
#define B_PL_AXIDMA_CH4_RX_DOK BIT(4)
#define B_PL_AXIDMA_CH3_RX_DOK BIT(3)
#define B_PL_AXIDMA_CH2_RX_DOK BIT(2)
#define B_PL_AXIDMA_CH1_RX_DOK BIT(1)
#define B_PL_AXIDMA_CH0_RX_DOK BIT(0)
#define R_PL_AXIDMA_FWISR1 0x090C
#define B_PL_AXIDMA_CH3_TX_DOK BIT(3)
#define B_PL_AXIDMA_CH2_TX_DOK BIT(2)
#define B_PL_AXIDMA_CH1_TX_DOK BIT(1)
#define B_PL_AXIDMA_CH0_TX_DOK BIT(0)
//
// WL_AX_Reg_CMAC_0.xls
//
//
// COMMON
//
#define R_AX_CMAC_FUNC_EN 0xC000
#define R_AX_CMAC_FUNC_EN_C1 0xE000
#define B_AX_CMAC_CRPRT BIT(31)
#define B_AX_CMAC_EN BIT(30)
#define B_AX_CMAC_TXEN BIT(29)
#define B_AX_CMAC_RXEN BIT(28)
#define B_AX_FORCE_CMACREG_GCKEN BIT(15)
#define B_AX_PHYINTF_EN BIT(5)
#define B_AX_CMAC_DMA_EN BIT(4)
#define B_AX_PTCLTOP_EN BIT(3)
#define B_AX_SCHEDULER_EN BIT(2)
#define B_AX_TMAC_EN BIT(1)
#define B_AX_RMAC_EN BIT(0)
#define R_AX_CK_EN 0xC004
#define R_AX_CK_EN_C1 0xE004
#define B_AX_CMAC_CKEN BIT(30)
#define B_AX_PHYINTF_CKEN BIT(5)
#define B_AX_CMAC_DMA_CKEN BIT(4)
#define B_AX_PTCLTOP_CKEN BIT(3)
#define B_AX_SCHEDULER_CKEN BIT(2)
#define B_AX_TMAC_CKEN BIT(1)
#define B_AX_RMAC_CKEN BIT(0)
#define R_AX_WMAC_RFMOD 0xC010
#define R_AX_WMAC_RFMOD_C1 0xE010
#define B_AX_WMAC_RFMOD_SH 0
#define B_AX_WMAC_RFMOD_MSK 0x3
#define R_AX_R_BIST_CTRL 0xC040
#define R_AX_R_BIST_CTRL_C1 0xE040
#define B_AX_R_BIST_DYN_READ_EN BIT(14)
#define B_AX_R_BIST_LOOP_MODE BIT(13)
#define B_AX_R_BIST_LVDRF_CLKDIS BIT(12)
#define B_AX_R_BIST_DRF_RESUME BIT(3)
#define B_AX_R_BIST_DRF_MODE BIT(2)
#define B_AX_R_BIST_MODE BIT(1)
#define B_AX_R_BIST_RSTN_ALL BIT(0)
#define R_AX_SYM_MEM_RM_CTRL 0xC044
#define R_AX_SYM_MEM_RM_CTRL_C1 0xE044
#define B_AX_R_SYM_MEM_RMV_FABDBG_SH 30
#define B_AX_R_SYM_MEM_RMV_FABDBG_MSK 0x3
#define B_AX_R_SYM_MEM_RMV_SIGN BIT(29)
#define B_AX_R_SYM_MEM_RMV_2PRF BIT(27)
#define B_AX_R_SYM_MEM_RMV_1PRF BIT(26)
#define B_AX_R_SYM_MEM_RMV_1PSR BIT(25)
#define B_AX_R_SYM_MEM_RMV_ROM BIT(24)
#define B_AX_R_SYM_MEM_RME_WL_SH 4
#define B_AX_R_SYM_MEM_RME_WL_MSK 0xf
#define R_AX_PARAM_CMAC_BIST_RSTN 0xC050
#define R_AX_PARAM_CMAC_BIST_RSTN_C1 0xE050
#define B_AX_R_BIST_RST_N_CMAC_SH 0
#define B_AX_R_BIST_RST_N_CMAC_MSK 0x1ff
#define R_AX_PARAM_CMAC_BIST_DONE 0xC054
#define R_AX_PARAM_CMAC_BIST_DONE_C1 0xE054
#define B_AX_BIST_DONE_CMAC_SH 0
#define B_AX_BIST_DONE_CMAC_MSK 0x1ff
#define R_AX_PARAM_CMAC_BIST_FAIL 0xC058
#define R_AX_PARAM_CMAC_BIST_FAIL_C1 0xE058
#define B_AX_BIST_FAIL_CMAC_SH 0
#define B_AX_BIST_FAIL_CMAC_MSK 0x1ff
#define R_AX_PARAM_CMAC_DRF_PAUSE 0xC05C
#define R_AX_PARAM_CMAC_DRF_PAUSE_C1 0xE05C
#define B_AX_BIST_DRF_PAUSE_CMAC_SH 0
#define B_AX_BIST_DRF_PAUSE_CMAC_MSK 0x1ff
#define R_AX_PARAM_CMAC_BIST_RSTN_SHARE 0xC060
#define R_AX_PARAM_CMAC_BIST_RSTN_SHARE_C1 0xE060
#define B_AX_R_BIST_RST_N_CMAC_SHARE_SH 0
#define B_AX_R_BIST_RST_N_CMAC_SHARE_MSK 0x7
#define R_AX_PARAM_CMAC_BIST_DONE_SHARE 0xC064
#define R_AX_PARAM_CMAC_BIST_DONE_SHARE_C1 0xE064
#define B_AX_BIST_DONE_CMAC_SHARE_SH 0
#define B_AX_BIST_DONE_CMAC_SHARE_MSK 0x7
#define R_AX_PARAM_CMAC_BIST_FAIL_SHARE 0xC068
#define R_AX_PARAM_CMAC_BIST_FAIL_SHARE_C1 0xE068
#define B_AX_BIST_FAIL_CMAC_SHARE_SH 0
#define B_AX_BIST_FAIL_CMAC_SHARE_MSK 0x7
#define R_AX_PARAM_CMAC_DRF_PAUSE_SHARE 0xC06C
#define R_AX_PARAM_CMAC_DRF_PAUSE_SHARE_C1 0xE06C
#define B_AX_BIST_DRF_PAUSE_CMAC_SHARE_SH 0
#define B_AX_BIST_DRF_PAUSE_CMAC_SHARE_MSK 0x7
#define R_AX_GID_POSITION0 0xC070
#define R_AX_GID_POSITION0_C1 0xE070
#define B_AX_GID_15_POSITION_SH 30
#define B_AX_GID_15_POSITION_MSK 0x3
#define B_AX_GID_14_POSITION_SH 28
#define B_AX_GID_14_POSITION_MSK 0x3
#define B_AX_GID_13_POSITION_SH 26
#define B_AX_GID_13_POSITION_MSK 0x3
#define B_AX_GID_12_POSITION_SH 24
#define B_AX_GID_12_POSITION_MSK 0x3
#define B_AX_GID_11_POSITION_SH 22
#define B_AX_GID_11_POSITION_MSK 0x3
#define B_AX_GID_10_POSITION_SH 20
#define B_AX_GID_10_POSITION_MSK 0x3
#define B_AX_GID_9_POSITION_SH 18
#define B_AX_GID_9_POSITION_MSK 0x3
#define B_AX_GID_8_POSITION_SH 16
#define B_AX_GID_8_POSITION_MSK 0x3
#define B_AX_GID_7_POSITION_SH 14
#define B_AX_GID_7_POSITION_MSK 0x3
#define B_AX_GID_6_POSITION_SH 12
#define B_AX_GID_6_POSITION_MSK 0x3
#define B_AX_GID_5_POSITION_SH 10
#define B_AX_GID_5_POSITION_MSK 0x3
#define B_AX_GID_4_POSITION_SH 8
#define B_AX_GID_4_POSITION_MSK 0x3
#define B_AX_GID_3_POSITION_SH 6
#define B_AX_GID_3_POSITION_MSK 0x3
#define B_AX_GID_2_POSITION_SH 4
#define B_AX_GID_2_POSITION_MSK 0x3
#define B_AX_GID_1_POSITION_SH 2
#define B_AX_GID_1_POSITION_MSK 0x3
#define B_AX_GID_0_POSITION_SH 0
#define B_AX_GID_0_POSITION_MSK 0x3
#define R_AX_GID_POSITION1 0xC074
#define R_AX_GID_POSITION1_C1 0xE074
#define B_AX_GID_31_POSITION_SH 30
#define B_AX_GID_31_POSITION_MSK 0x3
#define B_AX_GID_30_POSITION_SH 28
#define B_AX_GID_30_POSITION_MSK 0x3
#define B_AX_GID_29_POSITION_SH 26
#define B_AX_GID_29_POSITION_MSK 0x3
#define B_AX_GID_28_POSITION_SH 24
#define B_AX_GID_28_POSITION_MSK 0x3
#define B_AX_GID_27_POSITION_SH 22
#define B_AX_GID_27_POSITION_MSK 0x3
#define B_AX_GID_26_POSITION_SH 20
#define B_AX_GID_26_POSITION_MSK 0x3
#define B_AX_GID_25_POSITION_SH 18
#define B_AX_GID_25_POSITION_MSK 0x3
#define B_AX_GID_24_POSITION_SH 16
#define B_AX_GID_24_POSITION_MSK 0x3
#define B_AX_GID_23_POSITION_SH 14
#define B_AX_GID_23_POSITION_MSK 0x3
#define B_AX_GID_22_POSITION_SH 12
#define B_AX_GID_22_POSITION_MSK 0x3
#define B_AX_GID_21_POSITION_SH 10
#define B_AX_GID_21_POSITION_MSK 0x3
#define B_AX_GID_20_POSITION_SH 8
#define B_AX_GID_20_POSITION_MSK 0x3
#define B_AX_GID_19_POSITION_SH 6
#define B_AX_GID_19_POSITION_MSK 0x3
#define B_AX_GID_18_POSITION_SH 4
#define B_AX_GID_18_POSITION_MSK 0x3
#define B_AX_GID_17_POSITION_SH 2
#define B_AX_GID_17_POSITION_MSK 0x3
#define B_AX_GID_16_POSITION_SH 0
#define B_AX_GID_16_POSITION_MSK 0x3
#define R_AX_GID_POSITION2 0xC078
#define R_AX_GID_POSITION2_C1 0xE078
#define B_AX_GID_47_POSITION_SH 30
#define B_AX_GID_47_POSITION_MSK 0x3
#define B_AX_GID_46_POSITION_SH 28
#define B_AX_GID_46_POSITION_MSK 0x3
#define B_AX_GID_45_POSITION_SH 26
#define B_AX_GID_45_POSITION_MSK 0x3
#define B_AX_GID_44_POSITION_SH 24
#define B_AX_GID_44_POSITION_MSK 0x3
#define B_AX_GID_43_POSITION_SH 22
#define B_AX_GID_43_POSITION_MSK 0x3
#define B_AX_GID_42_POSITION_SH 20
#define B_AX_GID_42_POSITION_MSK 0x3
#define B_AX_GID_41_POSITION_SH 18
#define B_AX_GID_41_POSITION_MSK 0x3
#define B_AX_GID_40_POSITION_SH 16
#define B_AX_GID_40_POSITION_MSK 0x3
#define B_AX_GID_39_POSITION_SH 14
#define B_AX_GID_39_POSITION_MSK 0x3
#define B_AX_GID_38_POSITION_SH 12
#define B_AX_GID_38_POSITION_MSK 0x3
#define B_AX_GID_37_POSITION_SH 10
#define B_AX_GID_37_POSITION_MSK 0x3
#define B_AX_GID_36_POSITION_SH 8
#define B_AX_GID_36_POSITION_MSK 0x3
#define B_AX_GID_35_POSITION_SH 6
#define B_AX_GID_35_POSITION_MSK 0x3
#define B_AX_GID_34_POSITION_SH 4
#define B_AX_GID_34_POSITION_MSK 0x3
#define B_AX_GID_33_POSITION_SH 2
#define B_AX_GID_33_POSITION_MSK 0x3
#define B_AX_GID_32_POSITION_SH 0
#define B_AX_GID_32_POSITION_MSK 0x3
#define R_AX_GID_POSITION3 0xC07C
#define R_AX_GID_POSITION3_C1 0xE07C
#define B_AX_GID_63_POSITION_SH 30
#define B_AX_GID_63_POSITION_MSK 0x3
#define B_AX_GID_62_POSITION_SH 28
#define B_AX_GID_62_POSITION_MSK 0x3
#define B_AX_GID_61_POSITION_SH 26
#define B_AX_GID_61_POSITION_MSK 0x3
#define B_AX_GID_60_POSITION_SH 24
#define B_AX_GID_60_POSITION_MSK 0x3
#define B_AX_GID_59_POSITION_SH 22
#define B_AX_GID_59_POSITION_MSK 0x3
#define B_AX_GID_58_POSITION_SH 20
#define B_AX_GID_58_POSITION_MSK 0x3
#define B_AX_GID_57_POSITION_SH 18
#define B_AX_GID_57_POSITION_MSK 0x3
#define B_AX_GID_56_POSITION_SH 16
#define B_AX_GID_56_POSITION_MSK 0x3
#define B_AX_GID_55_POSITION_SH 14
#define B_AX_GID_55_POSITION_MSK 0x3
#define B_AX_GID_54_POSITION_SH 12
#define B_AX_GID_54_POSITION_MSK 0x3
#define B_AX_GID_53_POSITION_SH 10
#define B_AX_GID_53_POSITION_MSK 0x3
#define B_AX_GID_52_POSITION_SH 8
#define B_AX_GID_52_POSITION_MSK 0x3
#define B_AX_GID_51_POSITION_SH 6
#define B_AX_GID_51_POSITION_MSK 0x3
#define B_AX_GID_50_POSITION_SH 4
#define B_AX_GID_50_POSITION_MSK 0x3
#define B_AX_GID_49_POSITION_SH 2
#define B_AX_GID_49_POSITION_MSK 0x3
#define B_AX_GID_48_POSITION_SH 0
#define B_AX_GID_48_POSITION_MSK 0x3
#define R_AX_GID_POSITION_EN0 0xC080
#define R_AX_GID_POSITION_EN0_C1 0xE080
#define B_AX_GID_31_POSITION_EN BIT(31)
#define B_AX_GID_30_POSITION_EN BIT(30)
#define B_AX_GID_29_POSITION_EN BIT(29)
#define B_AX_GID_28_POSITION_EN BIT(28)
#define B_AX_GID_27_POSITION_EN BIT(27)
#define B_AX_GID_26_POSITION_EN BIT(26)
#define B_AX_GID_25_POSITION_EN BIT(25)
#define B_AX_GID_24_POSITION_EN BIT(24)
#define B_AX_GID_23_POSITION_EN BIT(23)
#define B_AX_GID_22_POSITION_EN BIT(22)
#define B_AX_GID_21_POSITION_EN BIT(21)
#define B_AX_GID_20_POSITION_EN BIT(20)
#define B_AX_GID_19_POSITION_EN BIT(19)
#define B_AX_GID_18_POSITION_EN BIT(18)
#define B_AX_GID_17_POSITION_EN BIT(17)
#define B_AX_GID_16_POSITION_EN BIT(16)
#define B_AX_GID_15_POSITION_EN BIT(15)
#define B_AX_GID_14_POSITION_EN BIT(14)
#define B_AX_GID_13_POSITION_EN BIT(13)
#define B_AX_GID_12_POSITION_EN BIT(12)
#define B_AX_GID_11_POSITION_EN BIT(11)
#define B_AX_GID_10_POSITION_EN BIT(10)
#define B_AX_GID_9_POSITION_EN BIT(9)
#define B_AX_GID_8_POSITION_EN BIT(8)
#define B_AX_GID_7_POSITION_EN BIT(7)
#define B_AX_GID_6_POSITION_EN BIT(6)
#define B_AX_GID_5_POSITION_EN BIT(5)
#define B_AX_GID_4_POSITION_EN BIT(4)
#define B_AX_GID_3_POSITION_EN BIT(3)
#define B_AX_GID_2_POSITION_EN BIT(2)
#define B_AX_GID_1_POSITION_EN BIT(1)
#define B_AX_GID_0_POSITION_EN BIT(0)
#define R_AX_GID_POSITION_EN1 0xC084
#define R_AX_GID_POSITION_EN1_C1 0xE084
#define B_AX_GID_63_POSITION_EN BIT(31)
#define B_AX_GID_62_POSITION_EN BIT(30)
#define B_AX_GID_61_POSITION_EN BIT(29)
#define B_AX_GID_60_POSITION_EN BIT(28)
#define B_AX_GID_59_POSITION_EN BIT(27)
#define B_AX_GID_58_POSITION_EN BIT(26)
#define B_AX_GID_57_POSITION_EN BIT(25)
#define B_AX_GID_56_POSITION_EN BIT(24)
#define B_AX_GID_55_POSITION_EN BIT(23)
#define B_AX_GID_54_POSITION_EN BIT(22)
#define B_AX_GID_53_POSITION_EN BIT(21)
#define B_AX_GID_52_POSITION_EN BIT(20)
#define B_AX_GID_51_POSITION_EN BIT(19)
#define B_AX_GID_50_POSITION_EN BIT(18)
#define B_AX_GID_49_POSITION_EN BIT(17)
#define B_AX_GID_48_POSITION_EN BIT(16)
#define B_AX_GID_47_POSITION_EN BIT(15)
#define B_AX_GID_46_POSITION_EN BIT(14)
#define B_AX_GID_45_POSITION_EN BIT(13)
#define B_AX_GID_44_POSITION_EN BIT(12)
#define B_AX_GID_43_POSITION_EN BIT(11)
#define B_AX_GID_42_POSITION_EN BIT(10)
#define B_AX_GID_41_POSITION_EN BIT(9)
#define B_AX_GID_40_POSITION_EN BIT(8)
#define B_AX_GID_39_POSITION_EN BIT(7)
#define B_AX_GID_38_POSITION_EN BIT(6)
#define B_AX_GID_37_POSITION_EN BIT(5)
#define B_AX_GID_36_POSITION_EN BIT(4)
#define B_AX_GID_35_POSITION_EN BIT(3)
#define B_AX_GID_34_POSITION_EN BIT(2)
#define B_AX_GID_33_POSITION_EN BIT(1)
#define B_AX_GID_32_POSITION_EN BIT(0)
#define R_AX_TX_SUB_CARRIER_VALUE 0xC088
#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088
#define B_AX_TXSC_80M_SH 8
#define B_AX_TXSC_80M_MSK 0xf
#define B_AX_TXSC_40M_SH 4
#define B_AX_TXSC_40M_MSK 0xf
#define B_AX_TXSC_20M_SH 0
#define B_AX_TXSC_20M_MSK 0xf
#define R_AX_RRSR0 0xC08C
#define R_AX_RRSR0_C1 0xE08C
#define B_AX_RRSR_HE_SH 24
#define B_AX_RRSR_HE_MSK 0xff
#define B_AX_RRSR_VHT_SH 16
#define B_AX_RRSR_VHT_MSK 0xff
#define B_AX_RRSR_HT_SH 8
#define B_AX_RRSR_HT_MSK 0xff
#define B_AX_RRSR_OFDM_SH 0
#define B_AX_RRSR_OFDM_MSK 0xff
#define R_AX_PTCL_RRSR1 0xC090
#define R_AX_PTCL_RRSR1_C1 0xE090
#define B_AX_RRSR_RATE_EN_SH 8
#define B_AX_RRSR_RATE_EN_MSK 0xf
#define B_AX_RSC_SH 6
#define B_AX_RSC_MSK 0x3
#define B_AX_RRSR_CCK_SH 0
#define B_AX_RRSR_CCK_MSK 0xf
#define R_AX_FWC00IMR 0xC100
#define R_AX_FWC00IMR_C1 0xE100
#define B_AX_FS_SND_RDY_INT_EN BIT(29)
#define B_AX_FS_RP_END_INT_EN BIT(28)
#define B_AX_FS_RXBCN_TO_CNT_INT_EN BIT(27)
#define B_AX_FS_RXBCN_HIT_INT_EN BIT(26)
#define B_AX_FS_RX_MATCH_RTT_INT_EN BIT(25)
#define B_AX_FS_BCNQ_LOCK_INT_EN BIT(24)
#define B_AX_FS_P2P1_CTWEND_INT_EN BIT(23)
#define B_AX_FS_P2P1_TSF32_TOGGLE_INT_EN BIT(22)
#define B_AX_FS_P2P1_RFON_INT_EN BIT(21)
#define B_AX_FS_P2P1_RFOFF_INT_EN BIT(20)
#define B_AX_FS_P2P0_CTWEND_INT_EN BIT(19)
#define B_AX_FS_P2P0_TSF32_TOGGLE_INT_EN BIT(18)
#define B_AX_FS_P2P0_RFON_INT_EN BIT(17)
#define B_AX_FS_P2P0_RFOFF_INT_EN BIT(16)
#define B_AX_FS_MACID_PWRCHANGE3_INT_EN BIT(15)
#define B_AX_FS_MACID_PWRCHANGE2_INT_EN BIT(14)
#define B_AX_FS_MACID_PWRCHANGE1_INT_EN BIT(13)
#define B_AX_FS_MACID_PWRCHANGE0_INT_EN BIT(12)
#define B_AX_FS_RXFTMREQ_INT_EN BIT(11)
#define B_AX_FS_RXFTM_INT_EN BIT(10)
#define B_AX_FS_FTM_PTT_EN BIT(9)
#define B_AX_FS_TXFTM_INT_EN BIT(8)
#define B_AX_FS_SOUND_DONE_INT_EN BIT(7)
#define B_AX_FS_RXDONE_INT_EN BIT(6)
#define B_AX_FS_PSTIMER_5_INT_EN BIT(5)
#define B_AX_FS_PSTIMER_4_INT_EN BIT(4)
#define B_AX_FS_PSTIMER_3_INT_EN BIT(3)
#define B_AX_FS_PSTIMER_2_INT_EN BIT(2)
#define B_AX_FS_PSTIMER_1_INT_EN BIT(1)
#define B_AX_FS_PSTIMER_0_INT_EN BIT(0)
#define R_AX_FWC00ISR 0xC104
#define R_AX_FWC00ISR_C1 0xE104
#define B_AX_FS_SND_RDY_INT BIT(29)
#define B_AX_FS_RP_END_INT BIT(28)
#define B_AX_FS_RXBCN_TO_CNT_INT BIT(27)
#define B_AX_FS_RXBCN_HIT_INT BIT(26)
#define B_AX_FS_RX_MATCH_RTT_INT BIT(25)
#define B_AX_FS_BCNQ_LOCK_INT BIT(24)
#define B_AX_FS_P2P1_CTWEND_INT BIT(23)
#define B_AX_FS_P2P1_TSF32_TOGGLE_INT BIT(22)
#define B_AX_FS_P2P1_RFON_INT BIT(21)
#define B_AX_FS_P2P1_RFOFF_INT BIT(20)
#define B_AX_FS_P2P0_CTWEND_INT BIT(19)
#define B_AX_FS_P2P0_TSF32_TOGGLE_INT BIT(18)
#define B_AX_FS_P2P0_RFON_INT BIT(17)
#define B_AX_FS_P2P0_RFOFF_INT BIT(16)
#define B_AX_FS_MACID_PWRCHANGE3_INT BIT(15)
#define B_AX_FS_MACID_PWRCHANGE2_INT BIT(14)
#define B_AX_FS_MACID_PWRCHANGE1_INT BIT(13)
#define B_AX_FS_MACID_PWRCHANGE0_INT BIT(12)
#define B_AX_FS_RXFTMREQ_INT BIT(11)
#define B_AX_FS_RXFTM_INT BIT(10)
#define B_AX_FS_FTM_PTT_INT BIT(9)
#define B_AX_FS_TXFTM_INT BIT(8)
#define B_AX_FS_SOUND_DONE_INT BIT(7)
#define B_AX_FS_RXDONE_INT BIT(6)
#define B_AX_FS_PSTIMER_5_INT BIT(5)
#define B_AX_FS_PSTIMER_4_INT BIT(4)
#define B_AX_FS_PSTIMER_3_INT BIT(3)
#define B_AX_FS_PSTIMER_2_INT BIT(2)
#define B_AX_FS_PSTIMER_1_INT BIT(1)
#define B_AX_FS_PSTIMER_0_INT BIT(0)
#define R_AX_FWC01IMR 0xC108
#define R_AX_FWC01IMR_C1 0xE108
#define B_AX_FS_P0_RXBCN_NOHIT_INT_EN BIT(22)
#define B_AX_FS_P0_RXMTF1MRR0_INT_EN BIT(21)
#define B_AX_FS_P0_RXMTF0_INT_EN BIT(20)
#define B_AX_FS_P0_RX_UAPSDMD1_INT_EN BIT(19)
#define B_AX_FS_P0_RX_UAPSDMD0_INT_EN BIT(18)
#define B_AX_FS_P0_TRIGGER_PKT_INT_EN BIT(17)
#define B_AX_FS_P0_EOSP_INT_EN BIT(16)
#define B_AX_FS_P0_TXPKTIN_EN BIT(15)
#define B_AX_FS_P0_TX_NULL1_INT_EN BIT(14)
#define B_AX_FS_P0_TX_NULL0_INT_EN BIT(13)
#define B_AX_FS_P0_RX_UMD0_INT_EN BIT(12)
#define B_AX_FS_P0_RX_UMD1_INT_EN BIT(11)
#define B_AX_FS_P0_RX_BMD0_INT_EN BIT(10)
#define B_AX_FS_P0_RX_BMD1_INT_EN BIT(9)
#define B_AX_FS_P0_RXBCNOK_INT_EN BIT(8)
#define B_AX_FS_P0MB0_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P0MB0_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P0MB0_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P0MB0_TBTT_INT_EN BIT(2)
#define B_AX_FS_P0MB0_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P0MB0_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC01ISR 0xC10C
#define R_AX_FWC01ISR_C1 0xE10C
#define B_AX_FS_P0_RXBCN_NOHIT_INT BIT(22)
#define B_AX_FS_P0_RXMTF1MRR0_INT BIT(21)
#define B_AX_FS_P0_RXMTF0_INT BIT(20)
#define B_AX_FS_P0_RX_UAPSDMD1_INT BIT(19)
#define B_AX_FS_P0_RX_UAPSDMD0_INT BIT(18)
#define B_AX_FS_P0_TRIGGER_PKT_INT BIT(17)
#define B_AX_FS_P0_EOSP_INT BIT(16)
#define B_AX_FS_P0_TXPKTIN_INT BIT(15)
#define B_AX_FS_P0_TX_NULL1_INT BIT(14)
#define B_AX_FS_P0_TX_NULL0_INT BIT(13)
#define B_AX_FS_P0_RX_UMD0_INT BIT(12)
#define B_AX_FS_P0_RX_UMD1_INT BIT(11)
#define B_AX_FS_P0_RX_BMD0_INT BIT(10)
#define B_AX_FS_P0_RX_BMD1_INT BIT(9)
#define B_AX_FS_P0_RXBCNOK_INT BIT(8)
#define B_AX_FS_P0MB0_TXBCNERR_INT BIT(5)
#define B_AX_FS_P0MB0_TXBCNOK_INT BIT(4)
#define B_AX_FS_P0MB0_HIQWND_INT BIT(3)
#define B_AX_FS_P0MB0_TBTT_INT BIT(2)
#define B_AX_FS_P0MB0_TBTTERLY_INT BIT(1)
#define B_AX_FS_P0MB0_BCNERLY_INT BIT(0)
#define R_AX_FWC02IMR 0xC110
#define R_AX_FWC02IMR_C1 0xE110
#define B_AX_FS_P1_RXBCN_NOHIT_INT_EN BIT(22)
#define B_AX_FS_P1_RXMTF1MRR0_INT_EN BIT(21)
#define B_AX_FS_P1_RXMTF0_INT_EN BIT(20)
#define B_AX_FS_P1_RX_UAPSDMD1_INT_EN BIT(19)
#define B_AX_FS_P1_RX_UAPSDMD0_INT_EN BIT(18)
#define B_AX_FS_P1_TRIGGER_PKT_INT_EN BIT(17)
#define B_AX_FS_P1_EOSP_INT_EN BIT(16)
#define B_AX_FS_P1_TXPKTIN_INT_EN BIT(15)
#define B_AX_FS_P1_TX_NULL1_INT_EN BIT(14)
#define B_AX_FS_P1_TX_NULL0_INT_EN BIT(13)
#define B_AX_FS_P1_RX_UMD0_INT_EN BIT(12)
#define B_AX_FS_P1_RX_UMD1_INT_EN BIT(11)
#define B_AX_FS_P1_RX_BMD0_INT_EN BIT(10)
#define B_AX_FS_P1_RX_BMD1_INT_EN BIT(9)
#define B_AX_FS_P1_RXBCNOK_INT_EN BIT(8)
#define B_AX_FS_P1_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P1_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P1_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P1_TBTT_INT_EN BIT(2)
#define B_AX_FS_P1_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P1_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC02ISR 0xC114
#define R_AX_FWC02ISR_C1 0xE114
#define B_AX_FS_P1_RXBCN_NOHIT_INT BIT(22)
#define B_AX_FS_P1_RXMTF1MRR0_INT BIT(21)
#define B_AX_FS_P1_RXMTF0_INT BIT(20)
#define B_AX_FS_P1_RX_UAPSDMD1_INT BIT(19)
#define B_AX_FS_P1_RX_UAPSDMD0_INT BIT(18)
#define B_AX_FS_P1_TRIGGER_PKT_INT BIT(17)
#define B_AX_FS_P1_EOSP_INT BIT(16)
#define B_AX_FS_P1_TXPKTIN_INT BIT(15)
#define B_AX_FS_P1_TX_NULL1_INT BIT(14)
#define B_AX_FS_P1_TX_NULL0_INT BIT(13)
#define B_AX_FS_P1_RX_UMD0_INT BIT(12)
#define B_AX_FS_P1_RX_UMD1_INT BIT(11)
#define B_AX_FS_P1_RX_BMD0_INT BIT(10)
#define B_AX_FS_P1_RX_BMD1_INT BIT(9)
#define B_AX_FS_P1_RXBCNOK_INT BIT(8)
#define B_AX_FS_P1_TXBCNERR_INT BIT(5)
#define B_AX_FS_P1_TXBCNOK_INT BIT(4)
#define B_AX_FS_P1_HIQWND_INT BIT(3)
#define B_AX_FS_P1_TBTT_INT BIT(2)
#define B_AX_FS_P1_TBTTERLY_INT BIT(1)
#define B_AX_FS_P1_BCNERLY_INT BIT(0)
#define R_AX_FWC03IMR 0xC118
#define R_AX_FWC03IMR_C1 0xE118
#define B_AX_FS_P2_RXBCN_NOHIT_INT_EN BIT(22)
#define B_AX_FS_P2_RXMTF1MRR0_INT_EN BIT(21)
#define B_AX_FS_P2_RXMTF0_INT_EN BIT(20)
#define B_AX_FS_P2_RX_UAPSDMD1_INT_EN BIT(19)
#define B_AX_FS_P2_RX_UAPSDMD0_INT_EN BIT(18)
#define B_AX_FS_P2_TRIGGER_PKT_INT_EN BIT(17)
#define B_AX_FS_P2_EOSP_INT_EN BIT(16)
#define B_AX_FS_P2_TXPKTIN_INT_EN BIT(15)
#define B_AX_FS_P2_TX_NULL1_INT_EN BIT(14)
#define B_AX_FS_P2_TX_NULL0_INT_EN BIT(13)
#define B_AX_FS_P2_RX_UMD0_INT_EN BIT(12)
#define B_AX_FS_P2_RX_UMD1_INT_EN BIT(11)
#define B_AX_FS_P2_RX_BMD0_INT_EN BIT(10)
#define B_AX_FS_P2_RX_BMD1_INT_EN BIT(9)
#define B_AX_FS_P2_RXBCNOK_INT_EN BIT(8)
#define B_AX_FS_P2_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P2_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P2_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P2_TBTT_INT_EN BIT(2)
#define B_AX_FS_P2_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P2_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC03ISR 0xC11C
#define R_AX_FWC03ISR_C1 0xE11C
#define B_AX_FS_P2_RXBCN_NOHIT_INT BIT(22)
#define B_AX_FS_P2_RXMTF1MRR0_INT BIT(21)
#define B_AX_FS_P2_RXMTF0_INT BIT(20)
#define B_AX_FS_P2_RX_UAPSDMD1_INT BIT(19)
#define B_AX_FS_P2_RX_UAPSDMD0_INT BIT(18)
#define B_AX_FS_P2_TRIGGER_PKT_INT BIT(17)
#define B_AX_FS_P2_EOSP_INT BIT(16)
#define B_AX_FS_P2_TXPKTIN_INT BIT(15)
#define B_AX_FS_P2_TX_NULL1_INT BIT(14)
#define B_AX_FS_P2_TX_NULL0_INT BIT(13)
#define B_AX_FS_P2_RX_UMD0_INT BIT(12)
#define B_AX_FS_P2_RX_UMD1_INT BIT(11)
#define B_AX_FS_P2_RX_BMD0_INT BIT(10)
#define B_AX_FS_P2_RX_BMD1_INT BIT(9)
#define B_AX_FS_P2_RXBCNOK_INT BIT(8)
#define B_AX_FS_P2_TXBCNERR_INT BIT(5)
#define B_AX_FS_P2_TXBCNOK_INT BIT(4)
#define B_AX_FS_P2_HIQWND_INT BIT(3)
#define B_AX_FS_P2_TBTT_INT BIT(2)
#define B_AX_FS_P2_TBTTERLY_INT BIT(1)
#define B_AX_FS_P2_BCNERLY_INT BIT(0)
#define R_AX_FWC04IMR 0xC120
#define R_AX_FWC04IMR_C1 0xE120
#define B_AX_FS_P3_RXBCN_NOHIT_INT_EN BIT(22)
#define B_AX_FS_P3_RXMTF1MRR0_INT_EN BIT(21)
#define B_AX_FS_P3_RXMTF0_INT_EN BIT(20)
#define B_AX_FS_P3_RX_UAPSDMD1_INT_EN BIT(19)
#define B_AX_FS_P3_RX_UAPSDMD0_INT_EN BIT(18)
#define B_AX_FS_P3_TRIGGER_PKT_INT_EN BIT(17)
#define B_AX_FS_P3_EOSP_INT_EN BIT(16)
#define B_AX_FS_P3_TXPKTIN_INT_EN BIT(15)
#define B_AX_FS_P3_TX_NULL1_INT_EN BIT(14)
#define B_AX_FS_P3_TX_NULL0_INT_EN BIT(13)
#define B_AX_FS_P3_RX_UMD0_INT_EN BIT(12)
#define B_AX_FS_P3_RX_UMD1_INT_EN BIT(11)
#define B_AX_FS_P3_RX_BMD0_INT_EN BIT(10)
#define B_AX_FS_P3_RX_BMD1_INT_EN BIT(9)
#define B_AX_FS_P3_RXBCNOK_INT_EN BIT(8)
#define B_AX_FS_P3_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P3_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P3_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P3_TBTT_INT_EN BIT(2)
#define B_AX_FS_P3_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P3_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC04ISR 0xC124
#define R_AX_FWC04ISR_C1 0xE124
#define B_AX_FS_P3_RXBCN_NOHIT_INT BIT(22)
#define B_AX_FS_P3_RXMTF1MRR0_INT BIT(21)
#define B_AX_FS_P3_RXMTF0_INT BIT(20)
#define B_AX_FS_P3_RX_UAPSDMD1_INT BIT(19)
#define B_AX_FS_P3_RX_UAPSDMD0_INT BIT(18)
#define B_AX_FS_P3_TRIGGER_PKT_INT BIT(17)
#define B_AX_FS_P3_EOSP_INT BIT(16)
#define B_AX_FS_P3_TXPKTIN_INT BIT(15)
#define B_AX_FS_P3_TX_NULL1_INT BIT(14)
#define B_AX_FS_P3_TX_NULL0_INT BIT(13)
#define B_AX_FS_P3_RX_UMD0_INT BIT(12)
#define B_AX_FS_P3_RX_UMD1_INT BIT(11)
#define B_AX_FS_P3_RX_BMD0_INT BIT(10)
#define B_AX_FS_P3_RX_BMD1_INT BIT(9)
#define B_AX_FS_P3_RXBCNOK_INT BIT(8)
#define B_AX_FS_P3_TXBCNERR_INT BIT(5)
#define B_AX_FS_P3_TXBCNOK_INT BIT(4)
#define B_AX_FS_P3_HIQWND_INT BIT(3)
#define B_AX_FS_P3_TBTT_INT BIT(2)
#define B_AX_FS_P3_TBTTERLY_INT BIT(1)
#define B_AX_FS_P3_BCNERLY_INT BIT(0)
#define R_AX_FWC05IMR 0xC128
#define R_AX_FWC05IMR_C1 0xE128
#define B_AX_FS_P4_RXBCN_NOHIT_INT_EN BIT(22)
#define B_AX_FS_P4_RXMTF1MRR0_INT_EN BIT(21)
#define B_AX_FS_P4_RXMTF0_INT_EN BIT(20)
#define B_AX_FS_P4_RX_UAPSDMD1_INT_EN BIT(19)
#define B_AX_FS_P4_RX_UAPSDMD0_INT_EN BIT(18)
#define B_AX_FS_P4_TRIGGER_PKT_INT_EN BIT(17)
#define B_AX_FS_P4_EOSP_INT_EN BIT(16)
#define B_AX_FS_P4_TXPKTIN_INT_EN BIT(15)
#define B_AX_FS_P4_TX_NULL1_INT_EN BIT(14)
#define B_AX_FS_P4_TX_NULL0_INT_EN BIT(13)
#define B_AX_FS_P4_RX_UMD0_INT_EN BIT(12)
#define B_AX_FS_P4_RX_UMD1_INT_EN BIT(11)
#define B_AX_FS_P4_RX_BMD0_INT_EN BIT(10)
#define B_AX_FS_P4_RX_BMD1_INT_EN BIT(9)
#define B_AX_FS_P4_RXBCNOK_INT_EN BIT(8)
#define B_AX_FS_P4_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P4_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P4_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P4_TBTT_INT_EN BIT(2)
#define B_AX_FS_P4_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P4_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC05ISR 0xC12C
#define R_AX_FWC05ISR_C1 0xE12C
#define B_AX_FS_P4_RXBCN_NOHIT_INT BIT(22)
#define B_AX_FS_P4_RXMTF1MRR0_INT BIT(21)
#define B_AX_FS_P4_RXMTF0_INT BIT(20)
#define B_AX_FS_P4_RX_UAPSDMD1_INT BIT(19)
#define B_AX_FS_P4_RX_UAPSDMD0_INT BIT(18)
#define B_AX_FS_P4_TRIGGER_PKT_INT BIT(17)
#define B_AX_FS_P4_EOSP_INT BIT(16)
#define B_AX_FS_P4_TXPKTIN_INT BIT(15)
#define B_AX_FS_P4_TX_NULL1_INT BIT(14)
#define B_AX_FS_P4_TX_NULL0_INT BIT(13)
#define B_AX_FS_P4_RX_UMD0_INT BIT(12)
#define B_AX_FS_P4_RX_UMD1_INT BIT(11)
#define B_AX_FS_P4_RX_BMD0_INT BIT(10)
#define B_AX_FS_P4_RX_BMD1_INT BIT(9)
#define B_AX_FS_P4_RXBCNOK_INT BIT(8)
#define B_AX_FS_P4_TXBCNERR_INT BIT(5)
#define B_AX_FS_P4_TXBCNOK_INT BIT(4)
#define B_AX_FS_P4_HIQWND_INT BIT(3)
#define B_AX_FS_P4_TBTT_INT BIT(2)
#define B_AX_FS_P4_TBTTERLY_INT BIT(1)
#define B_AX_FS_P4_BCNERLY_INT BIT(0)
#define R_AX_FWC06IMR 0xC130
#define R_AX_FWC06IMR_C1 0xE130
#define B_AX_FS_P0MB4_TXBCNERR_INT_EN BIT(29)
#define B_AX_FS_P0MB4_TXBCNOK_INT_EN BIT(28)
#define B_AX_FS_P0MB4_HIQWND_INT_EN BIT(27)
#define B_AX_FS_P0MB4_TBTT_INT_EN BIT(26)
#define B_AX_FS_P0MB4_TBTTERLY_INT_EN BIT(25)
#define B_AX_FS_P0MB4_BCNERLY_INT_EN BIT(24)
#define B_AX_FS_P0MB3_TXBCNERR_INT_EN BIT(21)
#define B_AX_FS_P0MB3_TXBCNOK_INT_EN BIT(20)
#define B_AX_FS_P0MB3_HIQWND_INT_EN BIT(19)
#define B_AX_FS_P0MB3_TBTT_INT_EN BIT(18)
#define B_AX_FS_P0MB3_TBTTERLY_INT_EN BIT(17)
#define B_AX_FS_P0MB3_BCNERLY_INT_EN BIT(16)
#define B_AX_FS_P0MB2_TXBCNERR_INT_EN BIT(13)
#define B_AX_FS_P0MB2_TXBCNOK_INT_EN BIT(12)
#define B_AX_FS_P0MB2_HIQWND_INT_EN BIT(11)
#define B_AX_FS_P0MB2_TBTT_INT_EN BIT(10)
#define B_AX_FS_P0MB2_TBTTERLY_INT_EN BIT(9)
#define B_AX_FS_P0MB2_BCNERLY_INT_EN BIT(8)
#define B_AX_FS_P0MB1_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P0MB1_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P0MB1_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P0MB1_TBTT_INT_EN BIT(2)
#define B_AX_FS_P0MB1_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P0MB1_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC06ISR 0xC134
#define R_AX_FWC06ISR_C1 0xE134
#define B_AX_FS_P0MB4_TXBCNERR_INT BIT(29)
#define B_AX_FS_P0MB4_TXBCNOK_INT BIT(28)
#define B_AX_FS_P0MB4_HIQWND_INT BIT(27)
#define B_AX_FS_P0MB4_TBTT_INT BIT(26)
#define B_AX_FS_P0MB4_TBTTERLY_INT BIT(25)
#define B_AX_FS_P0MB4_BCNERLY_INT BIT(24)
#define B_AX_FS_P0MB3_TXBCNERR_INT BIT(21)
#define B_AX_FS_P0MB3_TXBCNOK_INT BIT(20)
#define B_AX_FS_P0MB3_HIQWND_INT BIT(19)
#define B_AX_FS_P0MB3_TBTT_INT BIT(18)
#define B_AX_FS_P0MB3_TBTTERLY_INT BIT(17)
#define B_AX_FS_P0MB3_BCNERLY_INT BIT(16)
#define B_AX_FS_P0MB2_TXBCNERR_INT BIT(13)
#define B_AX_FS_P0MB2_TXBCNOK_INT BIT(12)
#define B_AX_FS_P0MB2_HIQWND_INT BIT(11)
#define B_AX_FS_P0MB2_TBTT_INT BIT(10)
#define B_AX_FS_P0MB2_TBTTERLY_INT BIT(9)
#define B_AX_FS_P0MB2_BCNERLY_INT BIT(8)
#define B_AX_FS_P0MB1_TXBCNERR_INT BIT(5)
#define B_AX_FS_P0MB1_TXBCNOK_INT BIT(4)
#define B_AX_FS_P0MB1_HIQWND_INT BIT(3)
#define B_AX_FS_P0MB1_TBTT_INT BIT(2)
#define B_AX_FS_P0MB1_TBTTERLY_INT BIT(1)
#define B_AX_FS_P0MB1_BCNERLY_INT BIT(0)
#define R_AX_FWC07IMR 0xC138
#define R_AX_FWC07IMR_C1 0xE138
#define B_AX_FS_P0MB8_TXBCNERR_INT_EN BIT(29)
#define B_AX_FS_P0MB8_TXBCNOK_INT_EN BIT(28)
#define B_AX_FS_P0MB8_HIQWND_INT_EN BIT(27)
#define B_AX_FS_P0MB8_TBTT_INT_EN BIT(26)
#define B_AX_FS_P0MB8_TBTTERLY_INT_EN BIT(25)
#define B_AX_FS_P0MB8_BCNERLY_INT_EN BIT(24)
#define B_AX_FS_P0MB7_TXBCNERR_INT_EN BIT(21)
#define B_AX_FS_P0MB7_TXBCNOK_INT_EN BIT(20)
#define B_AX_FS_P0MB7_HIQWND_INT_EN BIT(19)
#define B_AX_FS_P0MB7_TBTT_INT_EN BIT(18)
#define B_AX_FS_P0MB7_TBTTERLY_INT_EN BIT(17)
#define B_AX_FS_P0MB7_BCNERLY_INT_EN BIT(16)
#define B_AX_FS_P0MB6_TXBCNERR_INT_EN BIT(13)
#define B_AX_FS_P0MB6_TXBCNOK_INT_EN BIT(12)
#define B_AX_FS_P0MB6_HIQWND_INT_EN BIT(11)
#define B_AX_FS_P0MB6_TBTT_INT_EN BIT(10)
#define B_AX_FS_P0MB6_TBTTERLY_INT_EN BIT(9)
#define B_AX_FS_P0MB6_BCNERLY_INT_EN BIT(8)
#define B_AX_FS_P0MB5_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P0MB5_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P0MB5_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P0MB5_TBTT_INT_EN BIT(2)
#define B_AX_FS_P0MB5_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P0MB5_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC07ISR 0xC13C
#define R_AX_FWC07ISR_C1 0xE13C
#define B_AX_FS_P0MB8_TXBCNERR_INT BIT(29)
#define B_AX_FS_P0MB8_TXBCNOK_INT BIT(28)
#define B_AX_FS_P0MB8_HIQWND_INT BIT(27)
#define B_AX_FS_P0MB8_TBTT_INT BIT(26)
#define B_AX_FS_P0MB8_TBTTERLY_INT BIT(25)
#define B_AX_FS_P0MB8_BCNERLY_INT BIT(24)
#define B_AX_FS_P0MB7_TXBCNERR_INT BIT(21)
#define B_AX_FS_P0MB7_TXBCNOK_INT BIT(20)
#define B_AX_FS_P0MB7_HIQWND_INT BIT(19)
#define B_AX_FS_P0MB7_TBTT_INT BIT(18)
#define B_AX_FS_P0MB7_TBTTERLY_INT BIT(17)
#define B_AX_FS_P0MB7_BCNERLY_INT BIT(16)
#define B_AX_FS_P0MB6_TXBCNERR_INT BIT(13)
#define B_AX_FS_P0MB6_TXBCNOK_INT BIT(12)
#define B_AX_FS_P0MB6_HIQWND_INT BIT(11)
#define B_AX_FS_P0MB6_TBTT_INT BIT(10)
#define B_AX_FS_P0MB6_TBTTERLY_INT BIT(9)
#define B_AX_FS_P0MB6_BCNERLY_INT BIT(8)
#define B_AX_FS_P0MB5_TXBCNERR_INT BIT(5)
#define B_AX_FS_P0MB5_TXBCNOK_INT BIT(4)
#define B_AX_FS_P0MB5_HIQWND_INT BIT(3)
#define B_AX_FS_P0MB5_TBTT_INT BIT(2)
#define B_AX_FS_P0MB5_TBTTERLY_INT BIT(1)
#define B_AX_FS_P0MB5_BCNERLY_INT BIT(0)
#define R_AX_FWC08IMR 0xC140
#define R_AX_FWC08IMR_C1 0xE140
#define B_AX_FS_P0MB12_TXBCNERR_INT_EN BIT(29)
#define B_AX_FS_P0MB12_TXBCNOK_INT_EN BIT(28)
#define B_AX_FS_P0MB12_HIQWND_INT_EN BIT(27)
#define B_AX_FS_P0MB12_TBTT_INT_EN BIT(26)
#define B_AX_FS_P0MB12_TBTTERLY_INT_EN BIT(25)
#define B_AX_FS_P0MB12_BCNERLY_INT_EN BIT(24)
#define B_AX_FS_P0MB11_TXBCNERR_INT_EN BIT(21)
#define B_AX_FS_P0MB11_TXBCNOK_INT_EN BIT(20)
#define B_AX_FS_P0MB11_HIQWND_INT_EN BIT(19)
#define B_AX_FS_P0MB11_TBTT_INT_EN BIT(18)
#define B_AX_FS_P0MB11_TBTTERLY_INT_EN BIT(17)
#define B_AX_FS_P0MB11_BCNERLY_INT_EN BIT(16)
#define B_AX_FS_P0MB10_TXBCNERR_INT_EN BIT(13)
#define B_AX_FS_P0MB10_TXBCNOK_INT_EN BIT(12)
#define B_AX_FS_P0MB10_HIQWND_INT_EN BIT(11)
#define B_AX_FS_P0MB10_TBTT_INT_EN BIT(10)
#define B_AX_FS_P0MB10_TBTTERLY_INT_EN BIT(9)
#define B_AX_FS_P0MB10_BCNERLY_INT_EN BIT(8)
#define B_AX_FS_P0MB9_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P0MB9_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P0MB9_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P0MB9_TBTT_INT_EN BIT(2)
#define B_AX_FS_P0MB9_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P0MB9_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC08ISR 0xC144
#define R_AX_FWC08ISR_C1 0xE144
#define B_AX_FS_P0MB12_TXBCNERR_INT BIT(29)
#define B_AX_FS_P0MB12_TXBCNOK_INT BIT(28)
#define B_AX_FS_P0MB12_HIQWND_INT BIT(27)
#define B_AX_FS_P0MB12_TBTT_INT BIT(26)
#define B_AX_FS_P0MB12_TBTTERLY_INT BIT(25)
#define B_AX_FS_P0MB12_BCNERLY_INT BIT(24)
#define B_AX_FS_P0MB11_TXBCNERR_INT BIT(21)
#define B_AX_FS_P0MB11_TXBCNOK_INT BIT(20)
#define B_AX_FS_P0MB11_HIQWND_INT BIT(19)
#define B_AX_FS_P0MB11_TBTT_INT BIT(18)
#define B_AX_FS_P0MB11_TBTTERLY_INT BIT(17)
#define B_AX_FS_P0MB11_BCNERLY_INT BIT(16)
#define B_AX_FS_P0MB10_TXBCNERR_INT BIT(13)
#define B_AX_FS_P0MB10_TXBCNOK_INT BIT(12)
#define B_AX_FS_P0MB10_HIQWND_INT BIT(11)
#define B_AX_FS_P0MB10_TBTT_INT BIT(10)
#define B_AX_FS_P0MB10_TBTTERLY_INT BIT(9)
#define B_AX_FS_P0MB10_BCNERLY_INT BIT(8)
#define B_AX_FS_P0MB9_TXBCNERR_INT BIT(5)
#define B_AX_FS_P0MB9_TXBCNOK_INT BIT(4)
#define B_AX_FS_P0MB9_HIQWND_INT BIT(3)
#define B_AX_FS_P0MB9_TBTT_INT BIT(2)
#define B_AX_FS_P0MB9_TBTTERLY_INT BIT(1)
#define B_AX_FS_P0MB9_BCNERLY_INT BIT(0)
#define R_AX_FWC09IMR 0xC148
#define R_AX_FWC09IMR_C1 0xE148
#define B_AX_FS_P0MB15_TXBCNERR_INT_EN BIT(21)
#define B_AX_FS_P0MB15_TXBCNOK_INT_EN BIT(20)
#define B_AX_FS_P0MB15_HIQWND_INT_EN BIT(19)
#define B_AX_FS_P0MB15_TBTT_INT_EN BIT(18)
#define B_AX_FS_P0MB15_TBTTERLY_INT_EN BIT(17)
#define B_AX_FS_P0MB15_BCNERLY_INT_EN BIT(16)
#define B_AX_FS_P0MB14_TXBCNERR_INT_EN BIT(13)
#define B_AX_FS_P0MB14_TXBCNOK_INT_EN BIT(12)
#define B_AX_FS_P0MB14_HIQWND_INT_EN BIT(11)
#define B_AX_FS_P0MB14_TBTT_INT_EN BIT(10)
#define B_AX_FS_P0MB14_TBTTERLY_INT_EN BIT(9)
#define B_AX_FS_P0MB14_BCNERLY_INT_EN BIT(8)
#define B_AX_FS_P0MB13_TXBCNERR_INT_EN BIT(5)
#define B_AX_FS_P0MB13_TXBCNOK_INT_EN BIT(4)
#define B_AX_FS_P0MB13_HIQWND_INT_EN BIT(3)
#define B_AX_FS_P0MB13_TBTT_INT_EN BIT(2)
#define B_AX_FS_P0MB13_TBTTERLY_INT_EN BIT(1)
#define B_AX_FS_P0MB13_BCNERLY_INT_EN BIT(0)
#define R_AX_FWC09ISR 0xC14C
#define R_AX_FWC09ISR_C1 0xE14C
#define B_AX_FS_P0MB15_TXBCNERR_INT BIT(21)
#define B_AX_FS_P0MB15_TXBCNOK_INT BIT(20)
#define B_AX_FS_P0MB15_HIQWND_INT BIT(19)
#define B_AX_FS_P0MB15_TBTT_INT BIT(18)
#define B_AX_FS_P0MB15_TBTTERLY_INT BIT(17)
#define B_AX_FS_P0MB15_BCNERLY_INT BIT(16)
#define B_AX_FS_P0MB14_TXBCNERR_INT BIT(13)
#define B_AX_FS_P0MB14_TXBCNOK_INT BIT(12)
#define B_AX_FS_P0MB14_HIQWND_INT BIT(11)
#define B_AX_FS_P0MB14_TBTT_INT BIT(10)
#define B_AX_FS_P0MB14_TBTTERLY_INT BIT(9)
#define B_AX_FS_P0MB14_BCNERLY_INT BIT(8)
#define B_AX_FS_P0MB13_TXBCNERR_INT BIT(5)
#define B_AX_FS_P0MB13_TXBCNOK_INT BIT(4)
#define B_AX_FS_P0MB13_HIQWND_INT BIT(3)
#define B_AX_FS_P0MB13_TBTT_INT BIT(2)
#define B_AX_FS_P0MB13_TBTTERLY_INT BIT(1)
#define B_AX_FS_P0MB13_BCNERLY_INT BIT(0)
#define R_AX_CMAC_ERR_IMR 0xC160
#define R_AX_CMAC_ERR_IMR_C1 0xE160
#define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
#define B_AX_WMAC_RX_ERR_IND_EN BIT(6)
#define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5)
#define B_AX_PHYINTF_ERR_IND_EN BIT(4)
#define B_AX_DMA_TOP_ERR_IND_EN BIT(3)
#define B_AX_PTCL_TOP_ERR_IND_EN BIT(1)
#define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0)
#define R_AX_CMAC_ERR_ISR 0xC164
#define R_AX_CMAC_ERR_ISR_C1 0xE164
#define B_AX_WMAC_TX_ERR_IND BIT(7)
#define B_AX_WMAC_RX_ERR_IND BIT(6)
#define B_AX_TXPWR_CTRL_ERR_IND BIT(5)
#define B_AX_PHYINTF_ERR_IND BIT(4)
#define B_AX_DMA_TOP_ERR_IND BIT(3)
#define B_AX_PTCL_TOP_ERR_IND BIT(1)
#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
#define R_AX_HC00IMR 0xC180
#define R_AX_HC00IMR_C1 0xE180
#define B_AX_TBTT_B0P4_INT_EN BIT(16)
#define B_AX_TBTT_B0P3_INT_EN BIT(15)
#define B_AX_TBTT_B0P2_INT_EN BIT(14)
#define B_AX_TBTT_B0P1_INT_EN BIT(13)
#define B_AX_TBTT_B0P0_INT_EN BIT(12)
#define B_AX_PKT_INFO_ERR_INT_EN BIT(11)
#define B_AX_BB_STOPRX_INT_EN BIT(10)
#define B_AX_TXERR_INT_EN BIT(9)
#define B_AX_RXERR_INT_EN BIT(8)
#define B_AX_P2P1_TSF32_TOGG_INT_EN BIT(7)
#define B_AX_P2P0_TSF32_TOGG_INT_EN BIT(6)
#define B_AX_PWR_127TO96_INT_EN BIT(5)
#define B_AX_PWR_95TO64_INT_EN BIT(4)
#define B_AX_PWR_63TO32_INT_EN BIT(3)
#define B_AX_PWR_31TO0_INT_EN BIT(2)
#define B_AX_PSTIMER_5_INT_EN BIT(1)
#define B_AX_PSTIMER_4_INT_EN BIT(0)
#define R_AX_HC00ISR 0xC184
#define R_AX_HC00ISR_C1 0xE184
#define B_AX_TBTT_B0P4_INT BIT(16)
#define B_AX_TBTT_B0P3_INT BIT(15)
#define B_AX_TBTT_B0P2_INT BIT(14)
#define B_AX_TBTT_B0P1_INT BIT(13)
#define B_AX_TBTT_B0P0_INT BIT(12)
#define B_AX_PKT_INFO_ERR_INT BIT(11)
#define B_AX_BB_STOPRX_INT BIT(10)
#define B_AX_TXERR_INT BIT(9)
#define B_AX_RXERR_INT BIT(8)
#define B_AX_P2P1_TSF32_TOGG_INT BIT(7)
#define B_AX_P2P0_TSF32_TOGG_INT BIT(6)
#define B_AX_PWR_127TO96_INT BIT(5)
#define B_AX_PWR_95TO64_INT BIT(4)
#define B_AX_PWR_63TO32_INT BIT(3)
#define B_AX_PWR_31TO0_INT BIT(2)
#define B_AX_PSTIMER_5_INT BIT(1)
#define B_AX_PSTIMER_4_INT BIT(0)
//
// SCH
//
#define R_AX_PPS0_CTRL 0xC200
#define R_AX_PPS0_CTRL_C1 0xE200
#define B_AX_PPS0_PWR_RST1 BIT(31)
#define B_AX_PPS0_PWR_RST0 BIT(30)
#define B_AX_PPS0_CTWIN_SH 16
#define B_AX_PPS0_CTWIN_MSK 0xfff
#define B_AX_PPS0_TXOP_BRK_EN BIT(15)
#define B_AX_PPS0_AGG_BRK_EN BIT(14)
#define B_AX_PPS0_POF_AND_EN BIT(13)
#define B_AX_PPS0_PSWIND_EN BIT(12)
#define B_AX_PPS0_TSFB32_RST_EN BIT(11)
#define B_AX_PPS0_PORT_SEL_SH 8
#define B_AX_PPS0_PORT_SEL_MSK 0x7
#define B_AX_PPS0_ALLSLEEP_EN BIT(7)
#define B_AX_PPS0_OFF_DISTX_EN BIT(6)
#define B_AX_PPS0_CTWIN_EN BIT(5)
#define B_AX_PPS0_BCNAREA_EN BIT(4)
#define B_AX_PPS0_WITHBCNERY BIT(3)
#define B_AX_PPS0_POF1_EN BIT(2)
#define B_AX_PPS0_POF0_EN BIT(1)
#define B_AX_PPS0_PWR_MGT_EN BIT(0)
#define R_AX_PPS0_SPEC_STATE 0xC204
#define R_AX_PPS0_SPEC_STATE_C1 0xE204
#define B_AX_PPS0_SPEC_POW_STATE BIT(7)
#define B_AX_PPS0_SPEC_CTWIN_ON BIT(6)
#define B_AX_PPS0_SPEC_BCNAREA_ON BIT(5)
#define B_AX_PPS0_SPEC_BCNERLY BIT(4)
#define B_AX_PPS0_SPEC_POF1_OFF_PERD BIT(3)
#define B_AX_PPS0_SPEC_FORCE_DOZE1 BIT(2)
#define B_AX_PPS0_SPEC_POF0_OFF_PERD BIT(1)
#define B_AX_PPS0_SPEC_FORCE_DOZE0 BIT(0)
#define R_AX_PPS0_STATE 0xC205
#define R_AX_PPS0_STATE_C1 0xE205
#define B_AX_PPS0_POW_STATE BIT(7)
#define B_AX_PPS0_CTWIN_ON BIT(6)
#define B_AX_PPS0_BCNAREA_ON BIT(5)
#define B_AX_PPS0_BCNERLY BIT(4)
#define B_AX_PPS0_POF1_OFF_PERD BIT(3)
#define B_AX_PPS0_FORCE_DOZE1 BIT(2)
#define B_AX_PPS0_POF0_OFF_PERD BIT(1)
#define B_AX_PPS0_FORCE_DOZE0 BIT(0)
#define R_AX_PPS0_PAUSE_CTRL0 0xC206
#define R_AX_PPS0_PAUSE_CTRL0_C1 0xE206
#define B_AX_PPS0_POF_STOP_TX_HANG BIT(15)
#define B_AX_PPS0_MGQ_PAUSE_EN BIT(11)
#define B_AX_PPS0_HIQ_PAUSE_EN BIT(10)
#define B_AX_PPS0_BCNQ_PAUSE_EN BIT(9)
#define B_AX_PPS0_MACID_PAUSE_EN BIT(8)
#define B_AX_PPS0_PAUSE_MACID_SH 0
#define B_AX_PPS0_PAUSE_MACID_MSK 0xff
#define R_AX_PPS0_PAUSE_CTRL1 0xC208
#define R_AX_PPS0_PAUSE_CTRL1_C1 0xE208
#define B_AX_PPS0_POWON_DISTX_SH 16
#define B_AX_PPS0_POWON_DISTX_MSK 0xffff
#define B_AX_PPS0_POWOFF_DISTX_SH 0
#define B_AX_PPS0_POWOFF_DISTX_MSK 0xffff
#define R_AX_PPS0_PAUSE_CTRL2 0xC20C
#define R_AX_PPS0_PAUSE_CTRL2_C1 0xE20C
#define B_AX_PPS0_POWOFF_ERLY_SH 16
#define B_AX_PPS0_POWOFF_ERLY_MSK 0xffff
#define B_AX_PPS0_POWON_ERLY_SH 0
#define B_AX_PPS0_POWON_ERLY_MSK 0xffff
#define R_AX_PPS0_POF0_PARAM0 0xC210
#define R_AX_PPS0_POF0_PARAM0_C1 0xE210
#define B_AX_PPS0_POF0_DUR_SH 0
#define B_AX_PPS0_POF0_DUR_MSK 0xffffffffL
#define R_AX_PPS0_POF0_PARAM1 0xC214
#define R_AX_PPS0_POF0_PARAM1_C1 0xE214
#define B_AX_PPS0_POF0_ITVL_SH 0
#define B_AX_PPS0_POF0_ITVL_MSK 0xffffffffL
#define R_AX_PPS0_POF0_PARAM2 0xC218
#define R_AX_PPS0_POF0_PARAM2_C1 0xE218
#define B_AX_PPS0_POF0_START_SH 0
#define B_AX_PPS0_POF0_START_MSK 0xffffffffL
#define R_AX_PPS0_POF0_PARAM3 0xC21C
#define R_AX_PPS0_POF0_PARAM3_C1 0xE21C
#define B_AX_PPS0_POF0_CUR_CNT_SH 8
#define B_AX_PPS0_POF0_CUR_CNT_MSK 0xff
#define B_AX_PPS0_POF0_CNT_SH 0
#define B_AX_PPS0_POF0_CNT_MSK 0xff
#define R_AX_PPS0_POF1_PARAM0 0xC220
#define R_AX_PPS0_POF1_PARAM0_C1 0xE220
#define B_AX_PPS0_POF1_DUR_SH 0
#define B_AX_PPS0_POF1_DUR_MSK 0xffffffffL
#define R_AX_PPS0_POF1_PARAM1 0xC224
#define R_AX_PPS0_POF1_PARAM1_C1 0xE224
#define B_AX_PPS0_POF1_ITVL_SH 0
#define B_AX_PPS0_POF1_ITVL_MSK 0xffffffffL
#define R_AX_PPS0_POF1_PARAM2 0xC228
#define R_AX_PPS0_POF1_PARAM2_C1 0xE228
#define B_AX_PPS0_POF1_START_SH 0
#define B_AX_PPS0_POF1_START_MSK 0xffffffffL
#define R_AX_PPS0_POF1_PARAM3 0xC22C
#define R_AX_PPS0_POF1_PARAM3_C1 0xE22C
#define B_AX_PPS0_POF1_CUR_CNT_SH 8
#define B_AX_PPS0_POF1_CUR_CNT_MSK 0xff
#define B_AX_PPS0_POF1_CNT_SH 0
#define B_AX_PPS0_POF1_CNT_MSK 0xff
#define R_AX_PPS0_CURR_DOZE0 0xC230
#define R_AX_PPS0_CURR_DOZE0_C1 0xE230
#define B_AX_PPS0_POF0_CURR_DOZE_SH 0
#define B_AX_PPS0_POF0_CURR_DOZE_MSK 0xffffffffL
#define R_AX_PPS0_CURR_DOZE1 0xC234
#define R_AX_PPS0_CURR_DOZE1_C1 0xE234
#define B_AX_PPS0_POF1_CURR_DOZE_SH 0
#define B_AX_PPS0_POF1_CURR_DOZE_MSK 0xffffffffL
#define R_AX_PPS1_CTRL 0xC240
#define R_AX_PPS1_CTRL_C1 0xE240
#define B_AX_PPS1_PWR_RST1 BIT(31)
#define B_AX_PPS1_PWR_RST0 BIT(30)
#define B_AX_PPS1_CTWIN_SH 16
#define B_AX_PPS1_CTWIN_MSK 0xfff
#define B_AX_PPS1_TXOP_BRK_EN BIT(15)
#define B_AX_PPS1_AGG_BRK_EN BIT(14)
#define B_AX_PPS1_POF_AND_EN BIT(13)
#define B_AX_PPS1_PSWIND_EN BIT(12)
#define B_AX_PPS1_TSFB32_RST_EN BIT(11)
#define B_AX_PPS1_PORT_SEL_SH 8
#define B_AX_PPS1_PORT_SEL_MSK 0x7
#define B_AX_PPS1_ALLSLEEP_EN BIT(7)
#define B_AX_PPS1_OFF_DISTX_EN BIT(6)
#define B_AX_PPS1_CTWIN_EN BIT(5)
#define B_AX_PPS1_BCNAREA_EN BIT(4)
#define B_AX_PPS1_WITHBCNERY BIT(3)
#define B_AX_PPS1_POF1_EN BIT(2)
#define B_AX_PPS1_POF0_EN BIT(1)
#define B_AX_PPS1_PWR_MGT_EN BIT(0)
#define R_AX_PPS1_SPEC_STATE 0xC244
#define R_AX_PPS1_SPEC_STATE_C1 0xE244
#define B_AX_PPS1_SPEC_POW_STATE BIT(7)
#define B_AX_PPS1_SPEC_CTWIN_ON BIT(6)
#define B_AX_PPS1_SPEC_BCNAREA_ON BIT(5)
#define B_AX_PPS1_SPEC_BCNERLY BIT(4)
#define B_AX_PPS1_SPEC_POF1_OFF_PERD BIT(3)
#define B_AX_PPS1_SPEC_FORCE_DOZE1 BIT(2)
#define B_AX_PPS1_SPEC_POF0_OFF_PERD BIT(1)
#define B_AX_PPS1_SPEC_FORCE_DOZE0 BIT(0)
#define R_AX_PPS1_STATE 0xC245
#define R_AX_PPS1_STATE_C1 0xE245
#define B_AX_PPS1_POW_STATE BIT(7)
#define B_AX_PPS1_CTWIN_ON BIT(6)
#define B_AX_PPS1_BCNAREA_ON BIT(5)
#define B_AX_PPS1_BCNERLY BIT(4)
#define B_AX_PPS1_POF1_OFF_PERD BIT(3)
#define B_AX_PPS1_FORCE_DOZE1 BIT(2)
#define B_AX_PPS1_POF0_OFF_PERD BIT(1)
#define B_AX_PPS1_FORCE_DOZE0 BIT(0)
#define R_AX_PPS1_PAUSE_CTRL0 0xC246
#define R_AX_PPS1_PAUSE_CTRL0_C1 0xE246
#define B_AX_PPS1_POF_STOP_TX_HANG BIT(15)
#define B_AX_PPS1_POF1_MGQ_PAUSE_EN BIT(14)
#define B_AX_PPS1_POF1_HIQ_PAUSE_EN BIT(13)
#define B_AX_PPS1_POF1_BCNQ_PAUSE_EN BIT(12)
#define B_AX_PPS1_POF0_MGQ_PAUSE_EN BIT(11)
#define B_AX_PPS1_POF0_HIQ_PAUSE_EN BIT(10)
#define B_AX_PPS1_POF0_BCNQ_PAUSE_EN BIT(9)
#define B_AX_PPS1_MACID_PAUSE_EN BIT(8)
#define B_AX_PPS1_PAUSE_MACID_SH 0
#define B_AX_PPS1_PAUSE_MACID_MSK 0xff
#define R_AX_PPS1_PAUSE_CTRL1 0xC248
#define R_AX_PPS1_PAUSE_CTRL1_C1 0xE248
#define B_AX_PPS1_POWON_DISTX_SH 16
#define B_AX_PPS1_POWON_DISTX_MSK 0xffff
#define B_AX_PPS1_POWOFF_DISTX_SH 0
#define B_AX_PPS1_POWOFF_DISTX_MSK 0xffff
#define R_AX_PPS1_PAUSE_CTRL2 0xC24C
#define R_AX_PPS1_PAUSE_CTRL2_C1 0xE24C
#define B_AX_PPS1_POWOFF_ERLY_SH 16
#define B_AX_PPS1_POWOFF_ERLY_MSK 0xffff
#define B_AX_PPS1_POWON_ERLY_SH 0
#define B_AX_PPS1_POWON_ERLY_MSK 0xffff
#define R_AX_PPS1_POF0_PARAM0 0xC250
#define R_AX_PPS1_POF0_PARAM0_C1 0xE250
#define B_AX_PPS1_POF0_DUR_SH 0
#define B_AX_PPS1_POF0_DUR_MSK 0xffffffffL
#define R_AX_PPS1_POF0_PARAM1 0xC254
#define R_AX_PPS1_POF0_PARAM1_C1 0xE254
#define B_AX_PPS1_POF0_ITVL_SH 0
#define B_AX_PPS1_POF0_ITVL_MSK 0xffffffffL
#define R_AX_PPS1_POF0_PARAM2 0xC258
#define R_AX_PPS1_POF0_PARAM2_C1 0xE258
#define B_AX_PPS1_POF0_START_SH 0
#define B_AX_PPS1_POF0_START_MSK 0xffffffffL
#define R_AX_PPS1_POF0_PARAM3 0xC25C
#define R_AX_PPS1_POF0_PARAM3_C1 0xE25C
#define B_AX_PPS1_POF0_CUR_CNT_SH 8
#define B_AX_PPS1_POF0_CUR_CNT_MSK 0xff
#define B_AX_PPS1_POF0_CNT_SH 0
#define B_AX_PPS1_POF0_CNT_MSK 0xff
#define R_AX_PPS1_POF1_PARAM0 0xC260
#define R_AX_PPS1_POF1_PARAM0_C1 0xE260
#define B_AX_PPS1_POF1_DUR_SH 0
#define B_AX_PPS1_POF1_DUR_MSK 0xffffffffL
#define R_AX_PPS1_POF1_PARAM1 0xC264
#define R_AX_PPS1_POF1_PARAM1_C1 0xE264
#define B_AX_PPS1_POF1_ITVL_SH 0
#define B_AX_PPS1_POF1_ITVL_MSK 0xffffffffL
#define R_AX_PPS1_POF1_PARAM2 0xC268
#define R_AX_PPS1_POF1_PARAM2_C1 0xE268
#define B_AX_PPS1_POF1_START_SH 0
#define B_AX_PPS1_POF1_START_MSK 0xffffffffL
#define R_AX_PPS1_POF1_PARAM3 0xC26C
#define R_AX_PPS1_POF1_PARAM3_C1 0xE26C
#define B_AX_PPS1_POF1_CUR_CNT_SH 8
#define B_AX_PPS1_POF1_CUR_CNT_MSK 0xff
#define B_AX_PPS1_POF1_CNT_SH 0
#define B_AX_PPS1_POF1_CNT_MSK 0xffffffffL
#define R_AX_PPS1_CURR_DOZE0 0xC270
#define R_AX_PPS1_CURR_DOZE0_C1 0xE270
#define B_AX_PPS1_POF0_CURR_DOZE_SH 0
#define B_AX_PPS1_POF0_CURR_DOZE_MSK 0xffffffffL
#define R_AX_PPS1_CURR_DOZE1 0xC274
#define R_AX_PPS1_CURR_DOZE1_C1 0xE274
#define B_AX_PPS1_POF1_CURR_DOZE_SH 0
#define B_AX_PPS1_POF1_CURR_DOZE_MSK 0xffffffffL
#define R_AX_PORT_0_TSF_SYNC 0xC2A0
#define R_AX_PORT_0_TSF_SYNC_C1 0xE2A0
#define B_AX_P0_SYNC_NOW_P BIT(30)
#define B_AX_P0_SYNC_ONCE_P BIT(29)
#define B_AX_P0_AUTO_SYNC BIT(28)
#define B_AX_P0_SYNC_PORT_SRC_SEL_SH 24
#define B_AX_P0_SYNC_PORT_SRC_SEL_MSK 0x7
#define B_AX_P0_TSFTR_SYNC_OFFSET_SH 0
#define B_AX_P0_TSFTR_SYNC_OFFSET_MSK 0x7ffff
#define R_AX_PORT_1_TSF_SYNC 0xC2A4
#define R_AX_PORT_1_TSF_SYNC_C1 0xE2A4
#define B_AX_P1_SYNC_NOW_P BIT(30)
#define B_AX_P1_SYNC_ONCE_P BIT(29)
#define B_AX_P1_AUTO_SYNC BIT(28)
#define B_AX_P1_SYNC_PORT_SRC_SEL_SH 24
#define B_AX_P1_SYNC_PORT_SRC_SEL_MSK 0x7
#define B_AX_P1_TSFTR_SYNC_OFFSET_SH 0
#define B_AX_P1_TSFTR_SYNC_OFFSET_MSK 0x7ffff
#define R_AX_PORT_2_TSF_SYNC 0xC2A8
#define R_AX_PORT_2_TSF_SYNC_C1 0xE2A8
#define B_AX_P2_SYNC_NOW_P BIT(30)
#define B_AX_P2_SYNC_ONCE_P BIT(29)
#define B_AX_P2_AUTO_SYNC BIT(28)
#define B_AX_P2_SYNC_PORT_SRC_SEL_SH 24
#define B_AX_P2_SYNC_PORT_SRC_SEL_MSK 0x7
#define B_AX_P2_TSFTR_SYNC_OFFSET_SH 0
#define B_AX_P2_TSFTR_SYNC_OFFSET_MSK 0x7ffff
#define R_AX_PORT_3_TSF_SYNC 0xC2AC
#define R_AX_PORT_3_TSF_SYNC_C1 0xE2AC
#define B_AX_P3_SYNC_NOW_P BIT(30)
#define B_AX_P3_SYNC_ONCE_P BIT(29)
#define B_AX_P3_AUTO_SYNC BIT(28)
#define B_AX_P3_SYNC_PORT_SRC_SEL_SH 24
#define B_AX_P3_SYNC_PORT_SRC_SEL_MSK 0x7
#define B_AX_P3_TSFTR_SYNC_OFFSET_SH 0
#define B_AX_P3_TSFTR_SYNC_OFFSET_MSK 0x7ffff
#define R_AX_PORT_4_TSF_SYNC 0xC2B0
#define R_AX_PORT_4_TSF_SYNC_C1 0xE2B0
#define B_AX_P4_SYNC_NOW_P BIT(30)
#define B_AX_P4_SYNC_ONCE_P BIT(29)
#define B_AX_P4_AUTO_SYNC BIT(28)
#define B_AX_P4_SYNC_PORT_SRC_SEL_SH 24
#define B_AX_P4_SYNC_PORT_SRC_SEL_MSK 0x7
#define B_AX_P4_TSFTR_SYNC_OFFSET_SH 0
#define B_AX_P4_TSFTR_SYNC_OFFSET_MSK 0x7ffff
#define R_AX_MACID_SLEEP_0 0xC2C0
#define R_AX_MACID_SLEEP_0_C1 0xE2C0
#define B_AX_MACID31_0_SLEEP_SH 0
#define B_AX_MACID31_0_SLEEP_MSK 0xffffffffL
#define R_AX_MACID_SLEEP_1 0xC2C4
#define R_AX_MACID_SLEEP_1_C1 0xE2C4
#define B_AX_MACID63_32_SLEEP_SH 0
#define B_AX_MACID63_32_SLEEP_MSK 0xffffffffL
#define R_AX_MACID_SLEEP_2 0xC2C8
#define R_AX_MACID_SLEEP_2_C1 0xE2C8
#define B_AX_MACID95_64_SLEEP_SH 0
#define B_AX_MACID95_64_SLEEP_MSK 0xffffffffL
#define R_AX_MACID_SLEEP_3 0xC2CC
#define R_AX_MACID_SLEEP_3_C1 0xE2CC
#define B_AX_MACID127_96_SLEEP_SH 0
#define B_AX_MACID127_96_SLEEP_MSK 0xffffffffL
#define R_AX_CMAC_MACID_DROP_0 0xC2E0
#define R_AX_CMAC_MACID_DROP_0_C1 0xE2E0
#define B_AX_CMAC_MACID31_0_DROP_SH 0
#define B_AX_CMAC_MACID31_0_DROP_MSK 0xffffffffL
#define R_AX_CMAC_MACID_DROP_1 0xC2E4
#define R_AX_CMAC_MACID_DROP_1_C1 0xE2E4
#define B_AX_CMAC_MACID63_32_DROP_SH 0
#define B_AX_CMAC_MACID63_32_DROP_MSK 0xffffffffL
#define R_AX_CMAC_MACID_DROP_2 0xC2E8
#define R_AX_CMAC_MACID_DROP_2_C1 0xE2E8
#define B_AX_CMAC_MACID95_64_DROP_SH 0
#define B_AX_CMAC_MACID95_64_DROP_MSK 0xffffffffL
#define R_AX_CMAC_MACID_DROP_3 0xC2EC
#define R_AX_CMAC_MACID_DROP_3_C1 0xE2EC
#define B_AX_CMAC_MACID127_96_DROP_SH 0
#define B_AX_CMAC_MACID127_96_DROP_MSK 0xffffffffL
#define R_AX_EDCA_BE_PARAM_0 0xC300
#define R_AX_EDCA_BE_PARAM_0_C1 0xE300
#define B_AX_BE_0_TXOPLMT_SH 16
#define B_AX_BE_0_TXOPLMT_MSK 0x7ff
#define B_AX_BE_0_CW_SH 8
#define B_AX_BE_0_CW_MSK 0xff
#define B_AX_BE_0_AIFS_SH 0
#define B_AX_BE_0_AIFS_MSK 0xff
#define R_AX_EDCA_BK_PARAM_0 0xC304
#define R_AX_EDCA_BK_PARAM_0_C1 0xE304
#define B_AX_BK_0_TXOPLMT_SH 16
#define B_AX_BK_0_TXOPLMT_MSK 0x7ff
#define B_AX_BK_0_CW_SH 8
#define B_AX_BK_0_CW_MSK 0xff
#define B_AX_BK_0_AIFS_SH 0
#define B_AX_BK_0_AIFS_MSK 0xff
#define R_AX_EDCA_VI_PARAM_0 0xC308
#define R_AX_EDCA_VI_PARAM_0_C1 0xE308
#define B_AX_VI_0_TXOPLMT_SH 16
#define B_AX_VI_0_TXOPLMT_MSK 0x7ff
#define B_AX_VI_0_CW_SH 8
#define B_AX_VI_0_CW_MSK 0xff
#define B_AX_VI_0_AIFS_SH 0
#define B_AX_VI_0_AIFS_MSK 0xff
#define R_AX_EDCA_VO_PARAM_0 0xC30C
#define R_AX_EDCA_VO_PARAM_0_C1 0xE30C
#define B_AX_VO_0_TXOPLMT_SH 16
#define B_AX_VO_0_TXOPLMT_MSK 0x7ff
#define B_AX_VO_0_CW_SH 8
#define B_AX_VO_0_CW_MSK 0xff
#define B_AX_VO_0_AIFS_SH 0
#define B_AX_VO_0_AIFS_MSK 0xff
#define R_AX_EDCA_BE_PARAM_1 0xC310
#define R_AX_EDCA_BE_PARAM_1_C1 0xE310
#define B_AX_BE_1_TXOPLMT_SH 16
#define B_AX_BE_1_TXOPLMT_MSK 0x7ff
#define B_AX_BE_1_CW_SH 8
#define B_AX_BE_1_CW_MSK 0xff
#define B_AX_BE_1_AIFS_SH 0
#define B_AX_BE_1_AIFS_MSK 0xff
#define R_AX_EDCA_BK_PARAM_1 0xC314
#define R_AX_EDCA_BK_PARAM_1_C1 0xE314
#define B_AX_BK_1_TXOPLMT_SH 16
#define B_AX_BK_1_TXOPLMT_MSK 0x7ff
#define B_AX_BK_1_CW_SH 8
#define B_AX_BK_1_CW_MSK 0xff
#define B_AX_BK_1_AIFS_SH 0
#define B_AX_BK_1_AIFS_MSK 0xff
#define R_AX_EDCA_VI_PARAM_1 0xC318
#define R_AX_EDCA_VI_PARAM_1_C1 0xE318
#define B_AX_VI_1_TXOPLMT_SH 16
#define B_AX_VI_1_TXOPLMT_MSK 0x7ff
#define B_AX_VI_1_CW_SH 8
#define B_AX_VI_1_CW_MSK 0xff
#define B_AX_VI_1_AIFS_SH 0
#define B_AX_VI_1_AIFS_MSK 0xff
#define R_AX_EDCA_VO_PARAM_1 0xC31C
#define R_AX_EDCA_VO_PARAM_1_C1 0xE31C
#define B_AX_VO_1_TXOPLMT_SH 16
#define B_AX_VO_1_TXOPLMT_MSK 0x7ff
#define B_AX_VO_1_CW_SH 8
#define B_AX_VO_1_CW_MSK 0xff
#define B_AX_VO_1_AIFS_SH 0
#define B_AX_VO_1_AIFS_MSK 0xff
#define R_AX_EDCA_MGQ_PARAM 0xC320
#define R_AX_EDCA_MGQ_PARAM_C1 0xE320
#define B_AX_CPUMGQ_CW_SH 24
#define B_AX_CPUMGQ_CW_MSK 0xff
#define B_AX_CPUMGQ_AIFS_SH 16
#define B_AX_CPUMGQ_AIFS_MSK 0xff
#define B_AX_MGQ_CW_SH 8
#define B_AX_MGQ_CW_MSK 0xff
#define B_AX_MGQ_AIFS_SH 0
#define B_AX_MGQ_AIFS_MSK 0xff
#define R_AX_EDCA_BCNQ_PARAM 0xC324
#define R_AX_EDCA_BCNQ_PARAM_C1 0xE324
#define B_AX_BCNQ_CW_SH 24
#define B_AX_BCNQ_CW_MSK 0xff
#define B_AX_BCNQ_AIFS_SH 16
#define B_AX_BCNQ_AIFS_MSK 0xff
#define B_AX_FORCE_BCN_IFS_SH 8
#define B_AX_FORCE_BCN_IFS_MSK 0xff
#define B_AX_PIFS_SH 0
#define B_AX_PIFS_MSK 0xff
#define R_AX_EDCA_ULQ_PARAM 0xC328
#define R_AX_EDCA_ULQ_PARAM_C1 0xE328
#define B_AX_ULQ_TXOPLMT_SH 16
#define B_AX_ULQ_TXOPLMT_MSK 0x7ff
#define B_AX_ULQ_CW_SH 8
#define B_AX_ULQ_CW_MSK 0xff
#define B_AX_ULQ_AIFS_SH 0
#define B_AX_ULQ_AIFS_MSK 0xff
#define R_AX_EDCA_TWT_PARAM_0 0xC32C
#define R_AX_EDCA_TWT_PARAM_0_C1 0xE32C
#define B_AX_TWT_0_TXOPLMT_SH 16
#define B_AX_TWT_0_TXOPLMT_MSK 0x7ff
#define B_AX_TWT_0_CW_SH 8
#define B_AX_TWT_0_CW_MSK 0xff
#define B_AX_TWT_0_AIFS_SH 0
#define B_AX_TWT_0_AIFS_MSK 0xff
#define R_AX_EDCA_TWT_PARAM_1 0xC330
#define R_AX_EDCA_TWT_PARAM_1_C1 0xE330
#define B_AX_TWT_1_TXOPLMT_SH 16
#define B_AX_TWT_1_TXOPLMT_MSK 0x7ff
#define B_AX_TWT_1_CW_SH 8
#define B_AX_TWT_1_CW_MSK 0xff
#define B_AX_TWT_1_AIFS_SH 0
#define B_AX_TWT_1_AIFS_MSK 0xff
#define R_AX_SLOTTIME_CFG 0xC334
#define R_AX_SLOTTIME_CFG_C1 0xE334
#define B_AX_SLOT_TIME_SH 0
#define B_AX_SLOT_TIME_MSK 0xff
#define R_AX_PREBKF_CFG_0 0xC338
#define R_AX_PREBKF_CFG_0_C1 0xE338
#define B_AX_100NS_TIME_SH 24
#define B_AX_100NS_TIME_MSK 0x1f
#define B_AX_RX_AIR_END_TIME_SH 16
#define B_AX_RX_AIR_END_TIME_MSK 0x7f
#define B_AX_MACTX_LATENCY_SH 8
#define B_AX_MACTX_LATENCY_MSK 0x3f
#define B_AX_PREBKF_TIME_SH 0
#define B_AX_PREBKF_TIME_MSK 0xff
#define R_AX_PREBKF_CFG_1 0xC33C
#define R_AX_PREBKF_CFG_1_C1 0xE33C
#define B_AX_SIFS_PREBKF_SH 16
#define B_AX_SIFS_PREBKF_MSK 0xff
#define B_AX_SIFS_TIMEOUT_T2_SH 8
#define B_AX_SIFS_TIMEOUT_T2_MSK 0x7f
#define B_AX_SIFS_MACTXEN_T1_SH 0
#define B_AX_SIFS_MACTXEN_T1_MSK 0x7f
#define R_AX_CCA_CFG_0 0xC340
#define R_AX_CCA_CFG_0_C1 0xE340
#define B_AX_R_SIFS_AGGR_TIME_SH 24
#define B_AX_R_SIFS_AGGR_TIME_MSK 0x7f
#define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
#define B_AX_NAV_BRK_TXOP_EN BIT(8)
#define B_AX_TX_NAV_EN BIT(7)
#define B_AX_BCN_IGNORE_EDCCA BIT(6)
#define B_AX_BTCCA_EN BIT(5)
#define B_AX_EDCCA_EN BIT(4)
#define B_AX_SEC80_EN BIT(3)
#define B_AX_SEC40_EN BIT(2)
#define B_AX_SEC20_EN BIT(1)
#define B_AX_CCA_EN BIT(0)
#define R_AX_MISC_0 0xC344
#define R_AX_MISC_0_C1 0xE344
#define B_AX_RST_FREERUN_P BIT(15)
#define B_AX_EN_FREERUN BIT(8)
#define B_AX_EN_TBTT_AREA_FOR_AX_BB BIT(0)
#define R_AX_CTN_TXEN 0xC348
#define R_AX_CTN_TXEN_C1 0xE348
#define B_AX_CTN_TXEN_TWT_1 BIT(15)
#define B_AX_CTN_TXEN_TWT_0 BIT(14)
#define B_AX_CTN_TXEN_ULQ BIT(13)
#define B_AX_CTN_TXEN_BCNQ BIT(12)
#define B_AX_CTN_TXEN_HGQ BIT(11)
#define B_AX_CTN_TXEN_CPUMGQ BIT(10)
#define B_AX_CTN_TXEN_MGQ1 BIT(9)
#define B_AX_CTN_TXEN_MGQ BIT(8)
#define B_AX_CTN_TXEN_VO_1 BIT(7)
#define B_AX_CTN_TXEN_VI_1 BIT(6)
#define B_AX_CTN_TXEN_BK_1 BIT(5)
#define B_AX_CTN_TXEN_BE_1 BIT(4)
#define B_AX_CTN_TXEN_VO_0 BIT(3)
#define B_AX_CTN_TXEN_VI_0 BIT(2)
#define B_AX_CTN_TXEN_BK_0 BIT(1)
#define B_AX_CTN_TXEN_BE_0 BIT(0)
#define R_AX_CTN_CFG_0 0xC34C
#define R_AX_CTN_CFG_0_C1 0xE34C
#define B_AX_NAV_BLK_HGQ BIT(1)
#define B_AX_NAV_BLK_MGQ BIT(0)
#define R_AX_MUEDCA_BE_PARAM_0 0xC350
#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350
#define B_AX_MUEDCA_BE_PARAM_0_TIMER_SH 16
#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MSK 0xffff
#define B_AX_MUEDCA_BE_PARAM_0_CW_SH 8
#define B_AX_MUEDCA_BE_PARAM_0_CW_MSK 0xff
#define B_AX_MUEDCA_BE_PARAM_0_AIFS_SH 0
#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MSK 0xff
#define R_AX_MUEDCA_BK_PARAM_0 0xC354
#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354
#define B_AX_MUEDCA_BK_PARAM_0_TIMER_SH 16
#define B_AX_MUEDCA_BK_PARAM_0_TIMER_MSK 0xffff
#define B_AX_MUEDCA_BK_PARAM_0_CW_SH 8
#define B_AX_MUEDCA_BK_PARAM_0_CW_MSK 0xff
#define B_AX_MUEDCA_BK_PARAM_0_AIFS_SH 0
#define B_AX_MUEDCA_BK_PARAM_0_AIFS_MSK 0xff
#define R_AX_MUEDCA_VI_PARAM_0 0xC358
#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358
#define B_AX_MUEDCA_VI_PARAM_0_TIMER_SH 16
#define B_AX_MUEDCA_VI_PARAM_0_TIMER_MSK 0xffff
#define B_AX_MUEDCA_VI_PARAM_0_CW_SH 8
#define B_AX_MUEDCA_VI_PARAM_0_CW_MSK 0xff
#define B_AX_MUEDCA_VI_PARAM_0_AIFS_SH 0
#define B_AX_MUEDCA_VI_PARAM_0_AIFS_MSK 0xff
#define R_AX_MUEDCA_VO_PARAM_0 0xC35C
#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C
#define B_AX_MUEDCA_VO_PARAM_0_TIMER_SH 16
#define B_AX_MUEDCA_VO_PARAM_0_TIMER_MSK 0xffff
#define B_AX_MUEDCA_VO_PARAM_0_CW_SH 8
#define B_AX_MUEDCA_VO_PARAM_0_CW_MSK 0xff
#define B_AX_MUEDCA_VO_PARAM_0_AIFS_SH 0
#define B_AX_MUEDCA_VO_PARAM_0_AIFS_MSK 0xff
#define R_AX_MUEDCA_EN 0xC370
#define R_AX_MUEDCA_EN_C1 0xE370
#define B_AX_MUEDCA_WMM_SEL BIT(8)
#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4)
#define B_AX_MUEDCA_EN_0 BIT(0)
#define R_AX_RAND_SCR_BIT 0xC374
#define R_AX_RAND_SCR_BIT_C1 0xE374
#define B_AX_RAND_SCBITS_SH 0
#define B_AX_RAND_SCBITS_MSK 0x7fffff
#define R_AX_RANDOM_CFG 0xC378
#define R_AX_RANDOM_CFG_C1 0xE378
#define B_AX_RAND_SET_SH 0
#define B_AX_RAND_SET_MSK 0xffffff
#define R_AX_MUEDCATIMER_0 0xC380
#define R_AX_MUEDCATIMER_0_C1 0xE380
#define B_AX_MUEDCATIMER_BK_0_SH 16
#define B_AX_MUEDCATIMER_BK_0_MSK 0xffff
#define B_AX_MUEDCATIMER_BE_0_SH 0
#define B_AX_MUEDCATIMER_BE_0_MSK 0xffff
#define R_AX_MUEDCATIMER_1 0xC384
#define R_AX_MUEDCATIMER_1_C1 0xE384
#define B_AX_MUEDCATIMER_VO_0_SH 16
#define B_AX_MUEDCATIMER_VO_0_MSK 0xffff
#define B_AX_MUEDCATIMER_VI_0_SH 0
#define B_AX_MUEDCATIMER_VI_0_MSK 0xffff
#define R_AX_CCA_CONTROL 0xC390
#define R_AX_CCA_CONTROL_C1 0xE390
#define B_AX_TB_CHK_TX_NAV BIT(31)
#define B_AX_TB_CHK_BASIC_NAV BIT(30)
#define B_AX_TB_CHK_BTCCA BIT(29)
#define B_AX_TB_CHK_EDCCA BIT(28)
#define B_AX_TB_CHK_CCA_S80 BIT(27)
#define B_AX_TB_CHK_CCA_S40 BIT(26)
#define B_AX_TB_CHK_CCA_S20 BIT(25)
#define B_AX_TB_CHK_CCA_P20 BIT(24)
#define B_AX_SIFS_CHK_BTCCA BIT(21)
#define B_AX_SIFS_CHK_EDCCA BIT(20)
#define B_AX_SIFS_CHK_CCA_S80 BIT(19)
#define B_AX_SIFS_CHK_CCA_S40 BIT(18)
#define B_AX_SIFS_CHK_CCA_S20 BIT(17)
#define B_AX_SIFS_CHK_CCA_P20 BIT(16)
#define B_AX_CTN_CHK_TXNAV BIT(8)
#define B_AX_CTN_CHK_INTRA_NAV BIT(7)
#define B_AX_CTN_CHK_BASIC_NAV BIT(6)
#define B_AX_CTN_CHK_BTCCA BIT(5)
#define B_AX_CTN_CHK_EDCCA BIT(4)
#define B_AX_CTN_CHK_CCA_S80 BIT(3)
#define B_AX_CTN_CHK_CCA_S40 BIT(2)
#define B_AX_CTN_CHK_CCA_S20 BIT(1)
#define B_AX_CTN_CHK_CCA_P20 BIT(0)
#define R_AX_SCHEDULE_ERR_IMR 0xC3E8
#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8
#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1)
#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
#define R_AX_SCHEDULE_ERR_ISR 0xC3EC
#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC
#define B_AX_SORT_NON_IDLE_ERR_INT BIT(1)
#define B_AX_FSM_TIMEOUT_ERR_INT BIT(0)
#define R_AX_SCH_DBG_SEL 0xC3F4
#define R_AX_SCH_DBG_SEL_C1 0xE3F4
#define B_AX_SCH_DBG_EN BIT(16)
#define B_AX_SCH_CFG_CMD_SEL_SH 8
#define B_AX_SCH_CFG_CMD_SEL_MSK 0xff
#define B_AX_SCH_DBG_SEL_SH 0
#define B_AX_SCH_DBG_SEL_MSK 0xff
#define R_AX_SCH_DBG 0xC3F8
#define R_AX_SCH_DBG_C1 0xE3F8
#define B_AX_SCHEDULER_DBG_SH 0
#define B_AX_SCHEDULER_DBG_MSK 0xffffffffL
#define R_AX_SCH_EXT_CTRL 0xC3FC
#define R_AX_SCH_EXT_CTRL_C1 0xE3FC
#define B_AX_PORT_RST_TSF_ADV BIT(1)
#define B_AX_SCH_RESP_CTRL BIT(0)
#define R_AX_PORT_CFG_P0 0xC400
#define R_AX_PORT_CFG_P0_C1 0xE400
#define B_AX_BRK_SETUP_P0 BIT(16)
#define B_AX_TBTT_UPD_SHIFT_SEL_P0 BIT(15)
#define B_AX_BCN_DROP_ALLOW_P0 BIT(14)
#define B_AX_TBTT_PROHIB_EN_P0 BIT(13)
#define B_AX_BCNTX_EN_P0 BIT(12)
#define B_AX_NET_TYPE_P0_SH 10
#define B_AX_NET_TYPE_P0_MSK 0x3
#define B_AX_BCN_FORCETX_EN_P0 BIT(9)
#define B_AX_TXBCN_BTCCA_EN_P0 BIT(8)
#define B_AX_BCNERR_CNT_EN_P0 BIT(7)
#define B_AX_BCN_AGRES_P0 BIT(6)
#define B_AX_TSFTR_RST_P0 BIT(5)
#define B_AX_RX_BSSID_FIT_EN_P0 BIT(4)
#define B_AX_TSF_UDT_EN_P0 BIT(3)
#define B_AX_PORT_FUNC_EN_P0 BIT(2)
#define B_AX_TXBCN_RPT_EN_P0 BIT(1)
#define B_AX_RXBCN_RPT_EN_P0 BIT(0)
#define R_AX_TBTT_PROHIB_P0 0xC404
#define R_AX_TBTT_PROHIB_P0_C1 0xE404
#define B_AX_TBTT_HOLD_P0_SH 16
#define B_AX_TBTT_HOLD_P0_MSK 0xfff
#define B_AX_TBTT_SETUP_P0_SH 0
#define B_AX_TBTT_SETUP_P0_MSK 0xff
#define R_AX_BCN_AREA_P0 0xC408
#define R_AX_BCN_AREA_P0_C1 0xE408
#define B_AX_BCN_MSK_AREA_P0_SH 16
#define B_AX_BCN_MSK_AREA_P0_MSK 0xfff
#define B_AX_BCN_CTN_AREA_P0_SH 0
#define B_AX_BCN_CTN_AREA_P0_MSK 0xfff
#define R_AX_BCNERLYINT_CFG_P0 0xC40C
#define R_AX_BCNERLYINT_CFG_P0_C1 0xE40C
#define B_AX_BCNERLY_P0_SH 0
#define B_AX_BCNERLY_P0_MSK 0xfff
#define R_AX_TBTTERLYINT_CFG_P0 0xC40E
#define R_AX_TBTTERLYINT_CFG_P0_C1 0xE40E
#define B_AX_TBTTERLY_P0_SH 0
#define B_AX_TBTTERLY_P0_MSK 0xfff
#define R_AX_TBTT_AGG_P0 0xC412
#define R_AX_TBTT_AGG_P0_C1 0xE412
#define B_AX_TBTT_AGG_NUM_P0_SH 8
#define B_AX_TBTT_AGG_NUM_P0_MSK 0xff
#define R_AX_BCN_SPACE_CFG_P0 0xC414
#define R_AX_BCN_SPACE_CFG_P0_C1 0xE414
#define B_AX_SUB_BCN_SPACE_P0_SH 16
#define B_AX_SUB_BCN_SPACE_P0_MSK 0xff
#define B_AX_BCN_SPACE_P0_SH 0
#define B_AX_BCN_SPACE_P0_MSK 0xffff
#define R_AX_BCN_FORCETX_P0 0xC418
#define R_AX_BCN_FORCETX_P0_C1 0xE418
#define B_AX_FORCE_BCN_CURRCNT_P0_SH 16
#define B_AX_FORCE_BCN_CURRCNT_P0_MSK 0xff
#define B_AX_FORCE_BCN_NUM_P0_SH 8
#define B_AX_FORCE_BCN_NUM_P0_MSK 0xff
#define B_AX_BCN_MAX_ERR_P0_SH 0
#define B_AX_BCN_MAX_ERR_P0_MSK 0xff
#define R_AX_BCN_ERR_CNT_P0 0xC420
#define R_AX_BCN_ERR_CNT_P0_C1 0xE420
#define B_AX_BCN_ERR_CNT_SUM_P0_SH 24
#define B_AX_BCN_ERR_CNT_SUM_P0_MSK 0xff
#define B_AX_BCN_ERR_CNT_NAV_P0_SH 16
#define B_AX_BCN_ERR_CNT_NAV_P0_MSK 0xff
#define B_AX_BCN_ERR_CNT_EDCCA_P0_SH 8
#define B_AX_BCN_ERR_CNT_EDCCA_P0_MSK 0xff
#define B_AX_BCN_ERR_CNT_CCA_P0_SH 0
#define B_AX_BCN_ERR_CNT_CCA_P0_MSK 0xff
#define R_AX_BCN_ERR_FLAG_P0 0xC424
#define R_AX_BCN_ERR_FLAG_P0_C1 0xE424
#define B_AX_BCN_ERR_FLAG_OTHERS_P0 BIT(6)
#define B_AX_BCN_ERR_FLAG_MAC_P0 BIT(5)
#define B_AX_BCN_ERR_FLAG_TXON_P0 BIT(4)
#define B_AX_BCN_ERR_FLAG_SRCHEND_P0 BIT(3)
#define B_AX_BCN_ERR_FLAG_INVALID_P0 BIT(2)
#define B_AX_BCN_ERR_FLAG_CMP_P0 BIT(1)
#define B_AX_BCN_ERR_FLAG_LOCK_P0 BIT(0)
#define R_AX_DTIM_CTRL_P0 0xC426
#define R_AX_DTIM_CTRL_P0_C1 0xE426
#define B_AX_DTIM_NUM_P0_SH 8
#define B_AX_DTIM_NUM_P0_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0_SH 0
#define B_AX_DTIM_CURRCNT_P0_MSK 0xff
#define R_AX_TBTT_SHIFT_P0 0xC428
#define R_AX_TBTT_SHIFT_P0_C1 0xE428
#define B_AX_TBTT_SHIFT_OFST_P0_SH 0
#define B_AX_TBTT_SHIFT_OFST_P0_MSK 0xfff
#define R_AX_BCN_CNT_TMR_P0 0xC434
#define R_AX_BCN_CNT_TMR_P0_C1 0xE434
#define B_AX_BCN_CNT_TMR_P0_SH 0
#define B_AX_BCN_CNT_TMR_P0_MSK 0xffffffffL
#define R_AX_TSFTR_LOW_P0 0xC438
#define R_AX_TSFTR_LOW_P0_C1 0xE438
#define B_AX_TSFTR_LOW_P0_SH 0
#define B_AX_TSFTR_LOW_P0_MSK 0xffffffffL
#define R_AX_TSFTR_HIGH_P0 0xC43C
#define R_AX_TSFTR_HIGH_P0_C1 0xE43C
#define B_AX_TSFTR_HIGH_P0_SH 0
#define B_AX_TSFTR_HIGH_P0_MSK 0xffffffffL
#define R_AX_PORT_CFG_P1 0xC440
#define R_AX_PORT_CFG_P1_C1 0xE440
#define B_AX_BRK_SETUP_P1 BIT(16)
#define B_AX_TBTT_UPD_SHIFT_SEL_P1 BIT(15)
#define B_AX_BCN_DROP_ALLOW_P1 BIT(14)
#define B_AX_TBTT_PROHIB_EN_P1 BIT(13)
#define B_AX_BCNTX_EN_P1 BIT(12)
#define B_AX_NET_TYPE_P1_SH 10
#define B_AX_NET_TYPE_P1_MSK 0x3
#define B_AX_BCN_FORCETX_EN_P1 BIT(9)
#define B_AX_TXBCN_BTCCA_EN_P1 BIT(8)
#define B_AX_BCNERR_CNT_EN_P1 BIT(7)
#define B_AX_BCN_AGRES_P1 BIT(6)
#define B_AX_TSFTR_RST_P1 BIT(5)
#define B_AX_RX_BSSID_FIT_EN_P1 BIT(4)
#define B_AX_TSF_UDT_EN_P1 BIT(3)
#define B_AX_PORT_FUNC_EN_P1 BIT(2)
#define B_AX_TXBCN_RPT_EN_P1 BIT(1)
#define B_AX_RXBCN_RPT_EN_P1 BIT(0)
#define R_AX_TBTT_PROHIB_P1 0xC444
#define R_AX_TBTT_PROHIB_P1_C1 0xE444
#define B_AX_TBTT_HOLD_P1_SH 16
#define B_AX_TBTT_HOLD_P1_MSK 0xfff
#define B_AX_TBTT_SETUP_P1_SH 0
#define B_AX_TBTT_SETUP_P1_MSK 0xff
#define R_AX_BCN_AREA_P1 0xC448
#define R_AX_BCN_AREA_P1_C1 0xE448
#define B_AX_BCN_MSK_AREA_P1_SH 16
#define B_AX_BCN_MSK_AREA_P1_MSK 0xfff
#define B_AX_BCN_CTN_AREA_P1_SH 0
#define B_AX_BCN_CTN_AREA_P1_MSK 0xfff
#define R_AX_BCNERLYINT_CFG_P1 0xC44C
#define R_AX_BCNERLYINT_CFG_P1_C1 0xE44C
#define B_AX_BCNERLY_P1_SH 0
#define B_AX_BCNERLY_P1_MSK 0xfff
#define R_AX_TBTTERLYINT_CFG_P1 0xC44E
#define R_AX_TBTTERLYINT_CFG_P1_C1 0xE44E
#define B_AX_TBTTERLY_P1_SH 0
#define B_AX_TBTTERLY_P1_MSK 0xfff
#define R_AX_TBTT_AGG_P1 0xC452
#define R_AX_TBTT_AGG_P1_C1 0xE452
#define B_AX_TBTT_AGG_NUM_P1_SH 8
#define B_AX_TBTT_AGG_NUM_P1_MSK 0xff
#define R_AX_BCN_SPACE_CFG_P1 0xC454
#define R_AX_BCN_SPACE_CFG_P1_C1 0xE454
#define B_AX_BCN_SPACE_P1_SH 0
#define B_AX_BCN_SPACE_P1_MSK 0xffff
#define R_AX_BCN_FORCETX_P1 0xC458
#define R_AX_BCN_FORCETX_P1_C1 0xE458
#define B_AX_FORCE_BCN_CURRCNT_P1_SH 16
#define B_AX_FORCE_BCN_CURRCNT_P1_MSK 0xff
#define B_AX_FORCE_BCN_NUM_P1_SH 8
#define B_AX_FORCE_BCN_NUM_P1_MSK 0xff
#define B_AX_BCN_MAX_ERR_P1_SH 0
#define B_AX_BCN_MAX_ERR_P1_MSK 0xff
#define R_AX_BCN_ERR_CNT_P1 0xC460
#define R_AX_BCN_ERR_CNT_P1_C1 0xE460
#define B_AX_BCN_ERR_CNT_SUM_P1_SH 24
#define B_AX_BCN_ERR_CNT_SUM_P1_MSK 0xff
#define B_AX_BCN_ERR_CNT_NAV_P1_SH 16
#define B_AX_BCN_ERR_CNT_NAV_P1_MSK 0xff
#define B_AX_BCN_ERR_CNT_EDCCA_P1_SH 8
#define B_AX_BCN_ERR_CNT_EDCCA_P1_MSK 0xff
#define B_AX_BCN_ERR_CNT_CCA_P1_SH 0
#define B_AX_BCN_ERR_CNT_CCA_P1_MSK 0xff
#define R_AX_BCN_ERR_FLAG_P1 0xC464
#define R_AX_BCN_ERR_FLAG_P1_C1 0xE464
#define B_AX_BCN_ERR_FLAG_OTHERS_P1 BIT(6)
#define B_AX_BCN_ERR_FLAG_MAC_P1 BIT(5)
#define B_AX_BCN_ERR_FLAG_TXON_P1 BIT(4)
#define B_AX_BCN_ERR_FLAG_SRCHEND_P1 BIT(3)
#define B_AX_BCN_ERR_FLAG_INVALID_P1 BIT(2)
#define B_AX_BCN_ERR_FLAG_CMP_P1 BIT(1)
#define B_AX_BCN_ERR_FLAG_LOCK_P1 BIT(0)
#define R_AX_DTIM_CTRL_P1 0xC466
#define R_AX_DTIM_CTRL_P1_C1 0xE466
#define B_AX_DTIM_NUM_P1_SH 8
#define B_AX_DTIM_NUM_P1_MSK 0xff
#define B_AX_DTIM_CURRCNT_P1_SH 0
#define B_AX_DTIM_CURRCNT_P1_MSK 0xff
#define R_AX_TBTT_SHIFT_P1 0xC468
#define R_AX_TBTT_SHIFT_P1_C1 0xE468
#define B_AX_TBTT_SHIFT_OFST_P1_SH 0
#define B_AX_TBTT_SHIFT_OFST_P1_MSK 0xfff
#define R_AX_BCN_CNT_TMR_P1 0xC474
#define R_AX_BCN_CNT_TMR_P1_C1 0xE474
#define B_AX_BCN_CNT_TMR_P1_SH 0
#define B_AX_BCN_CNT_TMR_P1_MSK 0xffffffffL
#define R_AX_TSFTR_LOW_P1 0xC478
#define R_AX_TSFTR_LOW_P1_C1 0xE478
#define B_AX_TSFTR_LOW_P1_SH 0
#define B_AX_TSFTR_LOW_P1_MSK 0xffffffffL
#define R_AX_TSFTR_HIGH_P1 0xC47C
#define R_AX_TSFTR_HIGH_P1_C1 0xE47C
#define B_AX_TSFTR_HIGH_P1_SH 0
#define B_AX_TSFTR_HIGH_P1_MSK 0xffffffffL
#define R_AX_PORT_CFG_P2 0xC480
#define R_AX_PORT_CFG_P2_C1 0xE480
#define B_AX_BRK_SETUP_P2 BIT(16)
#define B_AX_TBTT_UPD_SHIFT_SEL_P2 BIT(15)
#define B_AX_BCN_DROP_ALLOW_P2 BIT(14)
#define B_AX_TBTT_PROHIB_EN_P2 BIT(13)
#define B_AX_BCNTX_EN_P2 BIT(12)
#define B_AX_NET_TYPE_P2_SH 10
#define B_AX_NET_TYPE_P2_MSK 0x3
#define B_AX_BCN_FORCETX_EN_P2 BIT(9)
#define B_AX_TXBCN_BTCCA_EN_P2 BIT(8)
#define B_AX_BCNERR_CNT_EN_P2 BIT(7)
#define B_AX_BCN_AGRES_P2 BIT(6)
#define B_AX_TSFTR_RST_P2 BIT(5)
#define B_AX_RX_BSSID_FIT_EN_P2 BIT(4)
#define B_AX_TSF_UDT_EN_P2 BIT(3)
#define B_AX_PORT_FUNC_EN_P2 BIT(2)
#define B_AX_TXBCN_RPT_EN_P2 BIT(1)
#define B_AX_RXBCN_RPT_EN_P2 BIT(0)
#define R_AX_BCN_AREA_P2 0xC488
#define R_AX_BCN_AREA_P2_C1 0xE488
#define B_AX_BCN_MSK_AREA_P2_SH 16
#define B_AX_BCN_MSK_AREA_P2_MSK 0xfff
#define R_AX_BCNERLYINT_CFG_P2 0xC48C
#define R_AX_BCNERLYINT_CFG_P2_C1 0xE48C
#define B_AX_BCNERLY_P2_SH 0
#define B_AX_BCNERLY_P2_MSK 0xfff
#define R_AX_TBTTERLYINT_CFG_P2 0xC48E
#define R_AX_TBTTERLYINT_CFG_P2_C1 0xE48E
#define B_AX_TBTTERLY_P2_SH 0
#define B_AX_TBTTERLY_P2_MSK 0xfff
#define R_AX_TBTT_AGG_P2 0xC492
#define R_AX_TBTT_AGG_P2_C1 0xE492
#define B_AX_TBTT_AGG_NUM_P2_SH 8
#define B_AX_TBTT_AGG_NUM_P2_MSK 0xff
#define R_AX_BCN_SPACE_CFG_P2 0xC494
#define R_AX_BCN_SPACE_CFG_P2_C1 0xE494
#define B_AX_BCN_SPACE_P2_SH 0
#define B_AX_BCN_SPACE_P2_MSK 0xffff
#define R_AX_BCN_FORCETX_P2 0xC498
#define R_AX_BCN_FORCETX_P2_C1 0xE498
#define B_AX_FORCE_BCN_CURRCNT_P2_SH 16
#define B_AX_FORCE_BCN_CURRCNT_P2_MSK 0xff
#define B_AX_FORCE_BCN_NUM_P2_SH 8
#define B_AX_FORCE_BCN_NUM_P2_MSK 0xff
#define B_AX_BCN_MAX_ERR_P2_SH 0
#define B_AX_BCN_MAX_ERR_P2_MSK 0xff
#define R_AX_BCN_ERR_CNT_P2 0xC4A0
#define R_AX_BCN_ERR_CNT_P2_C1 0xE4A0
#define B_AX_BCN_ERR_CNT_SUM_P2_SH 24
#define B_AX_BCN_ERR_CNT_SUM_P2_MSK 0xff
#define B_AX_BCN_ERR_CNT_NAV_P2_SH 16
#define B_AX_BCN_ERR_CNT_NAV_P2_MSK 0xff
#define B_AX_BCN_ERR_CNT_EDCCA_P2_SH 8
#define B_AX_BCN_ERR_CNT_EDCCA_P2_MSK 0xff
#define B_AX_BCN_ERR_CNT_CCA_P2_SH 0
#define B_AX_BCN_ERR_CNT_CCA_P2_MSK 0xff
#define R_AX_BCN_ERR_FLAG_P2 0xC4A4
#define R_AX_BCN_ERR_FLAG_P2_C1 0xE4A4
#define B_AX_BCN_ERR_FLAG_OTHERS_P2 BIT(6)
#define B_AX_BCN_ERR_FLAG_MAC_P2 BIT(5)
#define B_AX_BCN_ERR_FLAG_TXON_P2 BIT(4)
#define B_AX_BCN_ERR_FLAG_SRCHEND_P2 BIT(3)
#define B_AX_BCN_ERR_FLAG_INVALID_P2 BIT(2)
#define B_AX_BCN_ERR_FLAG_CMP_P2 BIT(1)
#define B_AX_BCN_ERR_FLAG_LOCK_P2 BIT(0)
#define R_AX_DTIM_CTRL_P2 0xC4A6
#define R_AX_DTIM_CTRL_P2_C1 0xE4A6
#define B_AX_DTIM_NUM_P2_SH 8
#define B_AX_DTIM_NUM_P2_MSK 0xff
#define B_AX_DTIM_CURRCNT_P2_SH 0
#define B_AX_DTIM_CURRCNT_P2_MSK 0xff
#define R_AX_TBTT_SHIFT_P2 0xC4A8
#define R_AX_TBTT_SHIFT_P2_C1 0xE4A8
#define B_AX_TBTT_SHIFT_OFST_P2_SH 0
#define B_AX_TBTT_SHIFT_OFST_P2_MSK 0xfff
#define R_AX_BCN_CNT_TMR_P2 0xC4B4
#define R_AX_BCN_CNT_TMR_P2_C1 0xE4B4
#define B_AX_BCN_CNT_TMR_P2_SH 0
#define B_AX_BCN_CNT_TMR_P2_MSK 0xffffffffL
#define R_AX_TSFTR_LOW_P2 0xC4B8
#define R_AX_TSFTR_LOW_P2_C1 0xE4B8
#define B_AX_TSFTR_LOW_P2_SH 0
#define B_AX_TSFTR_LOW_P2_MSK 0xffffffffL
#define R_AX_TSFTR_HIGH_P2 0xC4BC
#define R_AX_TSFTR_HIGH_P2_C1 0xE4BC
#define B_AX_TSFTR_HIGH_P2_SH 0
#define B_AX_TSFTR_HIGH_P2_MSK 0xffffffffL
#define R_AX_PORT_CFG_P3 0xC4C0
#define R_AX_PORT_CFG_P3_C1 0xE4C0
#define B_AX_BRK_SETUP_P3 BIT(16)
#define B_AX_TBTT_UPD_SHIFT_SEL_P3 BIT(15)
#define B_AX_BCN_DROP_ALLOW_P3 BIT(14)
#define B_AX_TBTT_PROHIB_EN_P3 BIT(13)
#define B_AX_BCNTX_EN_P3 BIT(12)
#define B_AX_NET_TYPE_P3_SH 10
#define B_AX_NET_TYPE_P3_MSK 0x3
#define B_AX_BCN_FORCETX_EN_P3 BIT(9)
#define B_AX_TXBCN_BTCCA_EN_P3 BIT(8)
#define B_AX_BCNERR_CNT_EN_P3 BIT(7)
#define B_AX_BCN_AGRES_P3 BIT(6)
#define B_AX_TSFTR_RST_P3 BIT(5)
#define B_AX_RX_BSSID_FIT_EN_P3 BIT(4)
#define B_AX_TSF_UDT_EN_P3 BIT(3)
#define B_AX_PORT_FUNC_EN_P3 BIT(2)
#define B_AX_TXBCN_RPT_EN_P3 BIT(1)
#define B_AX_RXBCN_RPT_EN_P3 BIT(0)
#define R_AX_BCN_AREA_P3 0xC4C8
#define R_AX_BCN_AREA_P3_C1 0xE4C8
#define B_AX_BCN_MSK_AREA_P3_SH 16
#define B_AX_BCN_MSK_AREA_P3_MSK 0xfff
#define R_AX_BCNERLYINT_CFG_P3 0xC4CC
#define R_AX_BCNERLYINT_CFG_P3_C1 0xE4CC
#define B_AX_BCNERLY_P3_SH 0
#define B_AX_BCNERLY_P3_MSK 0xfff
#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE
#define R_AX_TBTTERLYINT_CFG_P3_C1 0xE4CE
#define B_AX_TBTTERLY_P3_SH 0
#define B_AX_TBTTERLY_P3_MSK 0xfff
#define R_AX_TBTT_AGG_P3 0xC4D2
#define R_AX_TBTT_AGG_P3_C1 0xE4D2
#define B_AX_TBTT_AGG_NUM_P3_SH 8
#define B_AX_TBTT_AGG_NUM_P3_MSK 0xff
#define R_AX_BCN_SPACE_CFG_P3 0xC4D4
#define R_AX_BCN_SPACE_CFG_P3_C1 0xE4D4
#define B_AX_BCN_SPACE_P3_SH 0
#define B_AX_BCN_SPACE_P3_MSK 0xffff
#define R_AX_BCN_FORCETX_P3 0xC4D8
#define R_AX_BCN_FORCETX_P3_C1 0xE4D8
#define B_AX_FORCE_BCN_CURRCNT_P3_SH 16
#define B_AX_FORCE_BCN_CURRCNT_P3_MSK 0xff
#define B_AX_FORCE_BCN_NUM_P3_SH 8
#define B_AX_FORCE_BCN_NUM_P3_MSK 0xff
#define B_AX_BCN_MAX_ERR_P3_SH 0
#define B_AX_BCN_MAX_ERR_P3_MSK 0xff
#define R_AX_BCN_ERR_CNT_P3 0xC4E0
#define R_AX_BCN_ERR_CNT_P3_C1 0xE4E0
#define B_AX_BCN_ERR_CNT_SUM_P3_SH 24
#define B_AX_BCN_ERR_CNT_SUM_P3_MSK 0xff
#define B_AX_BCN_ERR_CNT_NAV_P3_SH 16
#define B_AX_BCN_ERR_CNT_NAV_P3_MSK 0xff
#define B_AX_BCN_ERR_CNT_EDCCA_P3_SH 8
#define B_AX_BCN_ERR_CNT_EDCCA_P3_MSK 0xff
#define B_AX_BCN_ERR_CNT_CCA_P3_SH 0
#define B_AX_BCN_ERR_CNT_CCA_P3_MSK 0xff
#define R_AX_BCN_ERR_FLAG_P3 0xC4E4
#define R_AX_BCN_ERR_FLAG_P3_C1 0xE4E4
#define B_AX_BCN_ERR_FLAG_OTHERS_P3 BIT(6)
#define B_AX_BCN_ERR_FLAG_MAC_P3 BIT(5)
#define B_AX_BCN_ERR_FLAG_TXON_P3 BIT(4)
#define B_AX_BCN_ERR_FLAG_SRCHEND_P3 BIT(3)
#define B_AX_BCN_ERR_FLAG_INVALID_P3 BIT(2)
#define B_AX_BCN_ERR_FLAG_CMP_P3 BIT(1)
#define B_AX_BCN_ERR_FLAG_LOCK_P3 BIT(0)
#define R_AX_DTIM_CTRL_P3 0xC4E6
#define R_AX_DTIM_CTRL_P3_C1 0xE4E6
#define B_AX_DTIM_NUM_P3_SH 8
#define B_AX_DTIM_NUM_P3_MSK 0xff
#define B_AX_DTIM_CURRCNT_P3_SH 0
#define B_AX_DTIM_CURRCNT_P3_MSK 0xff
#define R_AX_TBTT_SHIFT_P3 0xC4E8
#define R_AX_TBTT_SHIFT_P3_C1 0xE4E8
#define B_AX_TBTT_SHIFT_OFST_P3_SH 0
#define B_AX_TBTT_SHIFT_OFST_P3_MSK 0xfff
#define R_AX_BCN_CNT_TMR_P3 0xC4F4
#define R_AX_BCN_CNT_TMR_P3_C1 0xE4F4
#define B_AX_BCN_CNT_TMR_P3_SH 0
#define B_AX_BCN_CNT_TMR_P3_MSK 0xffffffffL
#define R_AX_TSFTR_LOW_P3 0xC4F8
#define R_AX_TSFTR_LOW_P3_C1 0xE4F8
#define B_AX_TSFTR_LOW_P3_SH 0
#define B_AX_TSFTR_LOW_P3_MSK 0xffffffffL
#define R_AX_TSFTR_HIGH_P3 0xC4FC
#define R_AX_TSFTR_HIGH_P3_C1 0xE4FC
#define B_AX_TSFTR_HIGH_P3_SH 0
#define B_AX_TSFTR_HIGH_P3_MSK 0xffffffffL
#define R_AX_PORT_CFG_P4 0xC500
#define R_AX_PORT_CFG_P4_C1 0xE500
#define B_AX_BRK_SETUP_P4 BIT(16)
#define B_AX_TBTT_UPD_SHIFT_SEL_P4 BIT(15)
#define B_AX_BCN_DROP_ALLOW_P4 BIT(14)
#define B_AX_TBTT_PROHIB_EN_P4 BIT(13)
#define B_AX_BCNTX_EN_P4 BIT(12)
#define B_AX_NET_TYPE_P4_SH 10
#define B_AX_NET_TYPE_P4_MSK 0x3
#define B_AX_BCN_FORCETX_EN_P4 BIT(9)
#define B_AX_TXBCN_BTCCA_EN_P4 BIT(8)
#define B_AX_BCNERR_CNT_EN_P4 BIT(7)
#define B_AX_BCN_AGRES_P4 BIT(6)
#define B_AX_TSFTR_RST_P4 BIT(5)
#define B_AX_RX_BSSID_FIT_EN_P4 BIT(4)
#define B_AX_TSF_UDT_EN_P4 BIT(3)
#define B_AX_PORT_FUNC_EN_P4 BIT(2)
#define B_AX_TXBCN_RPT_EN_P4 BIT(1)
#define B_AX_RXBCN_RPT_EN_P4 BIT(0)
#define R_AX_BCN_AREA_P4 0xC508
#define R_AX_BCN_AREA_P4_C1 0xE508
#define B_AX_BCN_MSK_AREA_P4_SH 16
#define B_AX_BCN_MSK_AREA_P4_MSK 0xfff
#define R_AX_BCNERLYINT_CFG_P4 0xC50C
#define R_AX_BCNERLYINT_CFG_P4_C1 0xE50C
#define B_AX_BCNERLY_P4_SH 0
#define B_AX_BCNERLY_P4_MSK 0xfff
#define R_AX_TBTTERLYINT_CFG_P4 0xC50E
#define R_AX_TBTTERLYINT_CFG_P4_C1 0xE50E
#define B_AX_TBTTERLY_P4_SH 0
#define B_AX_TBTTERLY_P4_MSK 0xfff
#define R_AX_TBTT_AGG_P4 0xC512
#define R_AX_TBTT_AGG_P4_C1 0xE512
#define B_AX_TBTT_AGG_NUM_P4_SH 8
#define B_AX_TBTT_AGG_NUM_P4_MSK 0xff
#define R_AX_BCN_SPACE_CFG_P4 0xC514
#define R_AX_BCN_SPACE_CFG_P4_C1 0xE514
#define B_AX_BCN_SPACE_P4_SH 0
#define B_AX_BCN_SPACE_P4_MSK 0xffff
#define R_AX_BCN_FORCETX_P4 0xC518
#define R_AX_BCN_FORCETX_P4_C1 0xE518
#define B_AX_FORCE_BCN_CURRCNT_P4_SH 16
#define B_AX_FORCE_BCN_CURRCNT_P4_MSK 0xff
#define B_AX_FORCE_BCN_NUM_P4_SH 8
#define B_AX_FORCE_BCN_NUM_P4_MSK 0xff
#define B_AX_BCN_MAX_ERR_P4_SH 0
#define B_AX_BCN_MAX_ERR_P4_MSK 0xff
#define R_AX_BCN_ERR_CNT_P4 0xC520
#define R_AX_BCN_ERR_CNT_P4_C1 0xE520
#define B_AX_BCN_ERR_CNT_SUM_P4_SH 24
#define B_AX_BCN_ERR_CNT_SUM_P4_MSK 0xff
#define B_AX_BCN_ERR_CNT_NAV_P4_SH 16
#define B_AX_BCN_ERR_CNT_NAV_P4_MSK 0xff
#define B_AX_BCN_ERR_CNT_EDCCA_P4_SH 8
#define B_AX_BCN_ERR_CNT_EDCCA_P4_MSK 0xff
#define B_AX_BCN_ERR_CNT_CCA_P4_SH 0
#define B_AX_BCN_ERR_CNT_CCA_P4_MSK 0xff
#define R_AX_BCN_ERR_FLAG_P4 0xC524
#define R_AX_BCN_ERR_FLAG_P4_C1 0xE524
#define B_AX_BCN_ERR_FLAG_OTHERS_P4 BIT(6)
#define B_AX_BCN_ERR_FLAG_MAC_P4 BIT(5)
#define B_AX_BCN_ERR_FLAG_TXON_P4 BIT(4)
#define B_AX_BCN_ERR_FLAG_SRCHEND_P4 BIT(3)
#define B_AX_BCN_ERR_FLAG_INVALID_P4 BIT(2)
#define B_AX_BCN_ERR_FLAG_CMP_P4 BIT(1)
#define B_AX_BCN_ERR_FLAG_LOCK_P4 BIT(0)
#define R_AX_DTIM_CTRL_P4 0xC526
#define R_AX_DTIM_CTRL_P4_C1 0xE526
#define B_AX_DTIM_NUM_P4_SH 8
#define B_AX_DTIM_NUM_P4_MSK 0xff
#define B_AX_DTIM_CURRCNT_P4_SH 0
#define B_AX_DTIM_CURRCNT_P4_MSK 0xff
#define R_AX_TBTT_SHIFT_P4 0xC528
#define R_AX_TBTT_SHIFT_P4_C1 0xE528
#define B_AX_TBTT_SHIFT_OFST_P4_SH 0
#define B_AX_TBTT_SHIFT_OFST_P4_MSK 0xfff
#define R_AX_BCN_CNT_TMR_P4 0xC534
#define R_AX_BCN_CNT_TMR_P4_C1 0xE534
#define B_AX_BCN_CNT_TMR_P4_SH 0
#define B_AX_BCN_CNT_TMR_P4_MSK 0xffffffffL
#define R_AX_TSFTR_LOW_P4 0xC538
#define R_AX_TSFTR_LOW_P4_C1 0xE538
#define B_AX_TSFTR_LOW_P4_SH 0
#define B_AX_TSFTR_LOW_P4_MSK 0xffffffffL
#define R_AX_TSFTR_HIGH_P4 0xC53C
#define R_AX_TSFTR_HIGH_P4_C1 0xE53C
#define B_AX_TSFTR_HIGH_P4_SH 0
#define B_AX_TSFTR_HIGH_P4_MSK 0xffffffffL
#define R_AX_DTIM_NUM0 0xC540
#define R_AX_DTIM_NUM0_C1 0xE540
#define B_AX_DTIM_NUM_P0MB3_SH 24
#define B_AX_DTIM_NUM_P0MB3_MSK 0xff
#define B_AX_DTIM_NUM_P0MB2_SH 16
#define B_AX_DTIM_NUM_P0MB2_MSK 0xff
#define B_AX_DTIM_NUM_P0MB1_SH 8
#define B_AX_DTIM_NUM_P0MB1_MSK 0xff
#define R_AX_DTIM_NUM1 0xC544
#define R_AX_DTIM_NUM1_C1 0xE544
#define B_AX_DTIM_NUM_P0MB7_SH 24
#define B_AX_DTIM_NUM_P0MB7_MSK 0xff
#define B_AX_DTIM_NUM_P0MB6_SH 16
#define B_AX_DTIM_NUM_P0MB6_MSK 0xff
#define B_AX_DTIM_NUM_P0MB5_SH 8
#define B_AX_DTIM_NUM_P0MB5_MSK 0xff
#define B_AX_DTIM_NUM_P0MB4_SH 0
#define B_AX_DTIM_NUM_P0MB4_MSK 0xff
#define R_AX_DTIM_NUM2 0xC548
#define R_AX_DTIM_NUM2_C1 0xE548
#define B_AX_DTIM_NUM_P0MB11_SH 24
#define B_AX_DTIM_NUM_P0MB11_MSK 0xff
#define B_AX_DTIM_NUM_P0MB10_SH 16
#define B_AX_DTIM_NUM_P0MB10_MSK 0xff
#define B_AX_DTIM_NUM_P0MB9_SH 8
#define B_AX_DTIM_NUM_P0MB9_MSK 0xff
#define B_AX_DTIM_NUM_P0MB8_SH 0
#define B_AX_DTIM_NUM_P0MB8_MSK 0xff
#define R_AX_DTIM_NUM3 0xC54C
#define R_AX_DTIM_NUM3_C1 0xE54C
#define B_AX_DTIM_NUM_P0MB15_SH 24
#define B_AX_DTIM_NUM_P0MB15_MSK 0xff
#define B_AX_DTIM_NUM_P0MB14_SH 16
#define B_AX_DTIM_NUM_P0MB14_MSK 0xff
#define B_AX_DTIM_NUM_P0MB13_SH 8
#define B_AX_DTIM_NUM_P0MB13_MSK 0xff
#define B_AX_DTIM_NUM_P0MB12_SH 0
#define B_AX_DTIM_NUM_P0MB12_MSK 0xff
#define R_AX_DTIM_CURRCNT0 0xC550
#define R_AX_DTIM_CURRCNT0_C1 0xE550
#define B_AX_DTIM_CURRCNT_P0MB3_SH 24
#define B_AX_DTIM_CURRCNT_P0MB3_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB2_SH 16
#define B_AX_DTIM_CURRCNT_P0MB2_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB1_SH 8
#define B_AX_DTIM_CURRCNT_P0MB1_MSK 0xff
#define R_AX_DTIM_CURRCNT1 0xC554
#define R_AX_DTIM_CURRCNT1_C1 0xE554
#define B_AX_DTIM_CURRCNT_P0MB7_SH 24
#define B_AX_DTIM_CURRCNT_P0MB7_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB6_SH 16
#define B_AX_DTIM_CURRCNT_P0MB6_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB5_SH 8
#define B_AX_DTIM_CURRCNT_P0MB5_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB4_SH 0
#define B_AX_DTIM_CURRCNT_P0MB4_MSK 0xff
#define R_AX_DTIM_CURRCNT2 0xC558
#define R_AX_DTIM_CURRCNT2_C1 0xE558
#define B_AX_DTIM_CURRCNT_P0MB11_SH 24
#define B_AX_DTIM_CURRCNT_P0MB11_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB10_SH 16
#define B_AX_DTIM_CURRCNT_P0MB10_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB9_SH 8
#define B_AX_DTIM_CURRCNT_P0MB9_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB8_SH 0
#define B_AX_DTIM_CURRCNT_P0MB8_MSK 0xff
#define R_AX_DTIM_CURRCNT3 0xC55C
#define R_AX_DTIM_CURRCNT3_C1 0xE55C
#define B_AX_DTIM_CURRCNT_P0MB15_SH 24
#define B_AX_DTIM_CURRCNT_P0MB15_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB14_SH 16
#define B_AX_DTIM_CURRCNT_P0MB14_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB13_SH 8
#define B_AX_DTIM_CURRCNT_P0MB13_MSK 0xff
#define B_AX_DTIM_CURRCNT_P0MB12_SH 0
#define B_AX_DTIM_CURRCNT_P0MB12_MSK 0xff
#define R_AX_BCN_DROP_ALL0 0xC560
#define R_AX_BCN_DROP_ALL0_C1 0xE560
#define B_AX_BCN_DROP_ALL_P4 BIT(4)
#define B_AX_BCN_DROP_ALL_P3 BIT(3)
#define B_AX_BCN_DROP_ALL_P2 BIT(2)
#define B_AX_BCN_DROP_ALL_P1 BIT(1)
#define B_AX_BCN_DROP_ALL_P0 BIT(0)
#define R_AX_BCN_DROP_ALL0_P0MB 0xC564
#define R_AX_BCN_DROP_ALL0_P0MB_C1 0xE564
#define B_AX_BCN_DROP_ALL_P0MB15 BIT(15)
#define B_AX_BCN_DROP_ALL_P0MB14 BIT(14)
#define B_AX_BCN_DROP_ALL_P0MB13 BIT(13)
#define B_AX_BCN_DROP_ALL_P0MB12 BIT(12)
#define B_AX_BCN_DROP_ALL_P0MB11 BIT(11)
#define B_AX_BCN_DROP_ALL_P0MB10 BIT(10)
#define B_AX_BCN_DROP_ALL_P0MB9 BIT(9)
#define B_AX_BCN_DROP_ALL_P0MB8 BIT(8)
#define B_AX_BCN_DROP_ALL_P0MB7 BIT(7)
#define B_AX_BCN_DROP_ALL_P0MB6 BIT(6)
#define B_AX_BCN_DROP_ALL_P0MB5 BIT(5)
#define B_AX_BCN_DROP_ALL_P0MB4 BIT(4)
#define B_AX_BCN_DROP_ALL_P0MB3 BIT(3)
#define B_AX_BCN_DROP_ALL_P0MB2 BIT(2)
#define B_AX_BCN_DROP_ALL_P0MB1 BIT(1)
#define R_AX_MBSSID_CTRL 0xC568
#define R_AX_MBSSID_CTRL_C1 0xE568
#define B_AX_P0MB_NUM_SH 16
#define B_AX_P0MB_NUM_MSK 0xff
#define B_AX_P0MB15_EN BIT(15)
#define B_AX_P0MB14_EN BIT(14)
#define B_AX_P0MB13_EN BIT(13)
#define B_AX_P0MB12_EN BIT(12)
#define B_AX_P0MB11_EN BIT(11)
#define B_AX_P0MB10_EN BIT(10)
#define B_AX_P0MB9_EN BIT(9)
#define B_AX_P0MB8_EN BIT(8)
#define B_AX_P0MB7_EN BIT(7)
#define B_AX_P0MB6_EN BIT(6)
#define B_AX_P0MB5_EN BIT(5)
#define B_AX_P0MB4_EN BIT(4)
#define B_AX_P0MB3_EN BIT(3)
#define B_AX_P0MB2_EN BIT(2)
#define B_AX_P0MB1_EN BIT(1)
#define R_AX_RXTSF_OFST 0xC570
#define R_AX_RXTSF_OFST_C1 0xE570
#define B_AX_RXTSF_OFST_OFDM_SH 8
#define B_AX_RXTSF_OFST_OFDM_MSK 0xff
#define B_AX_RXTSF_OFST_CCK_SH 0
#define B_AX_RXTSF_OFST_CCK_MSK 0xff
#define R_AX_RXBCN_TIME_CTRL 0xC574
#define R_AX_RXBCN_TIME_CTRL_C1 0xE574
#define B_AX_RXBCN_TIME_PORT_SH 28
#define B_AX_RXBCN_TIME_PORT_MSK 0x7
#define B_AX_RXBCN_TIME_VLD BIT(17)
#define B_AX_RXBCN_TIME_UDFW BIT(16)
#define B_AX_RXBCN_TIME_DIFF_SH 0
#define B_AX_RXBCN_TIME_DIFF_MSK 0xffff
#define R_AX_RXBCN_TIME_SYNC 0xC578
#define R_AX_RXBCN_TIME_SYNC_C1 0xE578
#define B_AX_RXBCN_TIME_SYNC_SH 0
#define B_AX_RXBCN_TIME_SYNC_MSK 0xffffffffL
#define R_AX_TBTT_TSF_INFO 0xC57C
#define R_AX_TBTT_TSF_INFO_C1 0xE57C
#define B_AX_TBTT_TSF_INFO_SH 0
#define B_AX_TBTT_TSF_INFO_MSK 0xffffffffL
#define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
#define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
#define B_AX_HGQWND_3_SH 24
#define B_AX_HGQWND_3_MSK 0xff
#define B_AX_HGQWND_2_SH 16
#define B_AX_HGQWND_2_MSK 0xff
#define B_AX_HGQWND_1_SH 8
#define B_AX_HGQWND_1_MSK 0xff
#define B_AX_HGQWND_0_SH 0
#define B_AX_HGQWND_0_MSK 0xff
#define R_AX_P0MB_HGQ_WINDOW_CFG_1 0xC594
#define R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 0xE594
#define B_AX_HGQWND_7_SH 24
#define B_AX_HGQWND_7_MSK 0xff
#define B_AX_HGQWND_6_SH 16
#define B_AX_HGQWND_6_MSK 0xff
#define B_AX_HGQWND_5_SH 8
#define B_AX_HGQWND_5_MSK 0xff
#define B_AX_HGQWND_4_SH 0
#define B_AX_HGQWND_4_MSK 0xff
#define R_AX_P0MB_HGQ_WINDOW_CFG_2 0xC598
#define R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 0xE598
#define B_AX_HGQWND_11_SH 24
#define B_AX_HGQWND_11_MSK 0xff
#define B_AX_HGQWND_10_SH 16
#define B_AX_HGQWND_10_MSK 0xff
#define B_AX_HGQWND_9_SH 8
#define B_AX_HGQWND_9_MSK 0xff
#define B_AX_HGQWND_8_SH 0
#define B_AX_HGQWND_8_MSK 0xff
#define R_AX_P0MB_HGQ_WINDOW_CFG_3 0xC59C
#define R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 0xE59C
#define B_AX_HGQWND_15_SH 24
#define B_AX_HGQWND_15_MSK 0xff
#define B_AX_HGQWND_14_SH 16
#define B_AX_HGQWND_14_MSK 0xff
#define B_AX_HGQWND_13_SH 8
#define B_AX_HGQWND_13_MSK 0xff
#define B_AX_HGQWND_12_SH 0
#define B_AX_HGQWND_12_MSK 0xff
#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
#define B_AX_HGQWND_19_SH 24
#define B_AX_HGQWND_19_MSK 0xff
#define B_AX_HGQWND_18_SH 16
#define B_AX_HGQWND_18_MSK 0xff
#define B_AX_HGQWND_17_SH 8
#define B_AX_HGQWND_17_MSK 0xff
#define B_AX_HGQWND_16_SH 0
#define B_AX_HGQWND_16_MSK 0xff
#define R_AX_EN_HGQ_NOLIMIT 0xC5A4
#define R_AX_EN_HGQ_NOLIMIT_C1 0xE5A4
#define B_AX_HIQ_NO_LMT_EN_P4 BIT(19)
#define B_AX_HIQ_NO_LMT_EN_P3 BIT(18)
#define B_AX_HIQ_NO_LMT_EN_P2 BIT(17)
#define B_AX_HIQ_NO_LMT_EN_P1 BIT(16)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP15 BIT(15)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP14 BIT(14)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP13 BIT(13)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP12 BIT(12)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP11 BIT(11)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP10 BIT(10)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP9 BIT(9)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP8 BIT(8)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP7 BIT(7)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP6 BIT(6)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP5 BIT(5)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP4 BIT(4)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP3 BIT(3)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP2 BIT(2)
#define B_AX_HIQ_NO_LMT_EN_P0_VAP1 BIT(1)
#define B_AX_HIQ_NO_LMT_EN_P0_ROOT BIT(0)
#define R_AX_LPS_RX_PERIOD_CTRL 0xC5B8
#define R_AX_LPS_RX_PERIOD_CTRL_C1 0xE5B8
#define B_AX_RXBCN_PERIOD_SH 16
#define B_AX_RXBCN_PERIOD_MSK 0xff
#define B_AX_CAT_PERIOD_SH 8
#define B_AX_CAT_PERIOD_MSK 0xff
#define B_AX_LPS_RX_CTRL_EN BIT(3)
#define B_AX_LPS_PORT_SEL_SH 0
#define B_AX_LPS_PORT_SEL_MSK 0x7
#define R_AX_LPS_BCN_CNT 0xC5BC
#define R_AX_LPS_BCN_CNT_C1 0xE5BC
#define B_AX_BCN_TO_ACC_CNT_SH 24
#define B_AX_BCN_TO_ACC_CNT_MSK 0xff
#define B_AX_BCN_OK_ACC_CNT_SH 16
#define B_AX_BCN_OK_ACC_CNT_MSK 0xff
#define B_AX_BCN_TO_CNT_THD_SH 8
#define B_AX_BCN_TO_CNT_THD_MSK 0xff
#define B_AX_BCN_TO_CNT_SH 0
#define B_AX_BCN_TO_CNT_MSK 0xff
#define R_AX_FREERUN_CNT_LOW 0xC5C0
#define R_AX_FREERUN_CNT_LOW_C1 0xE5C0
#define B_AX_FREERUN_CNT_LOW_SH 0
#define B_AX_FREERUN_CNT_LOW_MSK 0xffffffffL
#define R_AX_FREERUN_CNT_HIGH 0xC5C4
#define R_AX_FREERUN_CNT_HIGH_C1 0xE5C4
#define B_AX_FREERUN_CNT_HIGH_SH 0
#define B_AX_FREERUN_CNT_HIGH_MSK 0xffffffffL
#define R_AX_PSTIMER0 0xC5CC
#define R_AX_PSTIMER0_C1 0xE5CC
#define B_AX_PSTIMER0_VAL_SH 0
#define B_AX_PSTIMER0_VAL_MSK 0xffffffffL
#define R_AX_PSTIMER1 0xC23D
#define R_AX_PSTIMER1_C1 0xE23D
#define B_AX_PSTIMER1_VAL_SH 0
#define B_AX_PSTIMER1_VAL_MSK 0xffffffffL
#define R_AX_PSTIMER2 0xC5D4
#define R_AX_PSTIMER2_C1 0xE5D4
#define B_AX_PSTIMER2_VAL_SH 0
#define B_AX_PSTIMER2_VAL_MSK 0xffffffffL
#define R_AX_PSTIMER3 0xC5D8
#define R_AX_PSTIMER3_C1 0xE5D8
#define B_AX_PSTIMER3_VAL_SH 0
#define B_AX_PSTIMER3_VAL_MSK 0xffffffffL
#define R_AX_PSTIMER4 0xC5DC
#define R_AX_PSTIMER4_C1 0xE5DC
#define B_AX_PSTIMER4_VAL_SH 0
#define B_AX_PSTIMER4_VAL_MSK 0xffffffffL
#define R_AX_PSTIMER5 0xC5E0
#define R_AX_PSTIMER5_C1 0xE5E0
#define B_AX_PSTIMER5_VAL_SH 0
#define B_AX_PSTIMER5_VAL_MSK 0xffffffffL
#define R_AX_PSTIMER_CTRL 0xC5E4
#define R_AX_PSTIMER_CTRL_C1 0xE5E4
#define B_AX_PSTIMER5_EN BIT(23)
#define B_AX_PSTIMER5_SEL_SH 20
#define B_AX_PSTIMER5_SEL_MSK 0x7
#define B_AX_PSTIMER4_EN BIT(19)
#define B_AX_PSTIMER4_SEL_SH 16
#define B_AX_PSTIMER4_SEL_MSK 0x7
#define B_AX_PSTIMER3_EN BIT(15)
#define B_AX_PSTIMER3_SEL_SH 12
#define B_AX_PSTIMER3_SEL_MSK 0x7
#define B_AX_PSTIMER2_EN BIT(11)
#define B_AX_PSTIMER2_SEL_SH 8
#define B_AX_PSTIMER2_SEL_MSK 0x7
#define B_AX_PSTIMER1_EN BIT(7)
#define B_AX_PSTIMER1_SEL_SH 4
#define B_AX_PSTIMER1_SEL_MSK 0x7
#define B_AX_PSTIMER0_EN BIT(3)
#define B_AX_PSTIMER0_SEL_SH 0
#define B_AX_PSTIMER0_SEL_MSK 0x7
#define R_AX_TIMER_COMPARE 0xC5E8
#define R_AX_TIMER_COMPARE_C1 0xE5E8
#define B_AX_X_COMP_Y_TSFT_P BIT(7)
#define B_AX_Y_COMP_SEL_SH 4
#define B_AX_Y_COMP_SEL_MSK 0x7
#define B_AX_X_COMP_Y_OVER BIT(3)
#define B_AX_X_COMP_SEL_SH 0
#define B_AX_X_COMP_SEL_MSK 0x7
#define R_AX_TIMER_COMPARE_VALUE_LOW 0xC5EC
#define R_AX_TIMER_COMPARE_VALUE_LOW_C1 0xE5EC
#define B_AX_X_COMP_Y_VAL_LOW_SH 0
#define B_AX_X_COMP_Y_VAL_LOW_MSK 0xffffffffL
#define R_AX_TIMER_COMPARE_VALUE_HIGH 0xC5F0
#define R_AX_TIMER_COMPARE_VALUE_HIGH_C1 0xE5F0
#define B_AX_X_COMP_Y_VAL_HIGH_SH 0
#define B_AX_X_COMP_Y_VAL_HIGH_MSK 0xffffffffL
//
// PTCL
//
#define R_AX_PTCL_COMMON_SETTING_0 0xC600
#define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
#define B_AX_CPUMGQ_LIFETIME_EN BIT(8)
#define B_AX_MGQ_LIFETIME_EN BIT(7)
#define B_AX_LIFETIME_EN BIT(6)
#define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
#define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3)
#define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2)
#define B_AX_CMAC_TX_MODE_1 BIT(1)
#define B_AX_CMAC_TX_MODE_0 BIT(0)
#define R_AX_AGG_BK_0 0xC604
#define R_AX_AGG_BK_0_C1 0xE604
#define B_AX_DIS_SND_STS_CHECK BIT(7)
#define B_AX_NAV_PAUS_PHB_EN BIT(6)
#define B_AX_TXOP_SHT_PHB_EN BIT(5)
#define B_AX_AGG_BRK_PHB_EN BIT(4)
#define B_AX_DIS_SSN_CHK BIT(3)
#define B_AX_WDBK_CFG BIT(2)
#define B_AX_EN_RTY_BK BIT(1)
#define B_AX_EN_RTY_BK_COD BIT(0)
#define R_AX_TX_CTRL 0xC608
#define R_AX_TX_CTRL_C1 0xE608
#define B_AX_DROP_CHK_MAX_NUM_SH 24
#define B_AX_DROP_CHK_MAX_NUM_MSK 0xff
#define B_AX_DROP_CHK_TIMEOUT_SH 20
#define B_AX_DROP_CHK_TIMEOUT_MSK 0xf
#define B_AX_FWD_SRCH_TIMEOUT_SH 16
#define B_AX_FWD_SRCH_TIMEOUT_MSK 0xf
#define B_AX_PTCL_STOP_WMM BIT(7)
#define B_AX_TXOP_DELAY_TX_SH 0
#define B_AX_TXOP_DELAY_TX_MSK 0x1f
#define R_AX_TB_PPDU_CTRL 0xC60C
#define R_AX_TB_PPDU_CTRL_C1 0xE60C
#define B_AX_TB_PPDU_BK_DIS BIT(15)
#define B_AX_TB_PPDU_BE_DIS BIT(14)
#define B_AX_TB_PPDU_VI_DIS BIT(13)
#define B_AX_TB_PPDU_VO_DIS BIT(12)
#define B_AX_TB_BYPASS_TXPWR BIT(2)
#define B_AX_SW_PREFER_AC_SH 0
#define B_AX_SW_PREFER_AC_MSK 0x3
#define R_AX_AMPDU_AGG_LIMIT 0xC610
#define R_AX_AMPDU_AGG_LIMIT_C1 0xE610
#define B_AX_AMPDU_MAX_TIME_SH 24
#define B_AX_AMPDU_MAX_TIME_MSK 0xff
#define B_AX_RA_TRY_RATE_AGG_LMT_SH 16
#define B_AX_RA_TRY_RATE_AGG_LMT_MSK 0xff
#define B_AX_RTS_MAX_AGG_NUM_SH 8
#define B_AX_RTS_MAX_AGG_NUM_MSK 0xff
#define B_AX_MAX_AGG_NUM_SH 0
#define B_AX_MAX_AGG_NUM_MSK 0xff
#define R_AX_AGG_LEN_HT_0 0xC614
#define R_AX_AGG_LEN_HT_0_C1 0xE614
#define B_AX_AMPDU_MAX_LEN_HT_SH 16
#define B_AX_AMPDU_MAX_LEN_HT_MSK 0xffff
#define B_AX_RTS_TXTIME_TH_SH 8
#define B_AX_RTS_TXTIME_TH_MSK 0xff
#define B_AX_RTS_LEN_TH_SH 0
#define B_AX_RTS_LEN_TH_MSK 0xff
#define R_AX_AGG_LEN_VHT_0 0xC618
#define R_AX_AGG_LEN_VHT_0_C1 0xE618
#define B_AX_AMPDU_MAX_LEN_VHT_SH 0
#define B_AX_AMPDU_MAX_LEN_VHT_MSK 0xfffff
#define R_AX_AGG_LEN_HE_0 0xC61C
#define R_AX_AGG_LEN_HE_0_C1 0xE61C
#define B_AX_AMPDU_MAX_LEN_HE_SH 0
#define B_AX_AMPDU_MAX_LEN_HE_MSK 0x7fffff
#define R_AX_SPECIAL_TX_SETTING 0xC620
#define R_AX_SPECIAL_TX_SETTING_C1 0xE620
#define B_AX_USE_DATA_BW BIT(29)
#define B_AX_BW_SIGTA_SH 27
#define B_AX_BW_SIGTA_MSK 0x3
#define B_AX_BMC_NAV_PROTECT BIT(26)
#define B_AX_STBC_CFEND_SH 18
#define B_AX_STBC_CFEND_MSK 0x3
#define B_AX_STBC_CFEND_RATE_SH 9
#define B_AX_STBC_CFEND_RATE_MSK 0x1ff
#define B_AX_BASIC_CFEND_RATE_SH 0
#define B_AX_BASIC_CFEND_RATE_MSK 0x1ff
#define R_AX_SIFS_SETTING 0xC624
#define R_AX_SIFS_SETTING_C1 0xE624
#define B_AX_HW_CTS2SELF_PKT_LEN_TH_SH 24
#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MSK 0xff
#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_SH 18
#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MSK 0x3f
#define B_AX_HW_CTS2SELF_EN BIT(16)
#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8
#define B_AX_SPEC_SIFS_OFDM_PTCL_MSK 0xff
#define B_AX_SPEC_SIFS_CCK_PTCL_SH 0
#define B_AX_SPEC_SIFS_CCK_PTCL_MSK 0xff
#define R_AX_TXRATE_CHK 0xC628
#define R_AX_TXRATE_CHK_C1 0xE628
#define B_AX_DEFT_RATE_SH 7
#define B_AX_DEFT_RATE_MSK 0x1ff
#define B_AX_BAND_MODE BIT(4)
#define B_AX_MAX_TXNSS_SH 2
#define B_AX_MAX_TXNSS_MSK 0x3
#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1)
#define B_AX_CHECK_CCK_EN BIT(0)
#define R_AX_TXCNT 0xC62C
#define R_AX_TXCNT_C1 0xE62C
#define B_AX_ADD_TXCNT_BY BIT(31)
#define B_AX_S_TXCNT_LMT_SH 24
#define B_AX_S_TXCNT_LMT_MSK 0x3f
#define B_AX_L_TXCNT_LMT_SH 16
#define B_AX_L_TXCNT_LMT_MSK 0x3f
#define R_AX_LIFETIME_0 0xC630
#define R_AX_LIFETIME_0_C1 0xE630
#define B_AX_PKT_LIFETIME_2_SH 16
#define B_AX_PKT_LIFETIME_2_MSK 0xffff
#define B_AX_PKT_LIFETIME_1_SH 0
#define B_AX_PKT_LIFETIME_1_MSK 0xffff
#define R_AX_LIFETIME_1 0xC634
#define R_AX_LIFETIME_1_C1 0xE634
#define B_AX_PKT_LIFETIME_4_SH 16
#define B_AX_PKT_LIFETIME_4_MSK 0xffff
#define B_AX_PKT_LIFETIME_3_SH 0
#define B_AX_PKT_LIFETIME_3_MSK 0xffff
#define R_AX_LIFETIME_2 0xC638
#define R_AX_LIFETIME_2_C1 0xE638
#define B_AX_CPUMGQ_LIFETIME_SH 16
#define B_AX_CPUMGQ_LIFETIME_MSK 0xffff
#define B_AX_MGQ_LIFETIME_SH 0
#define B_AX_MGQ_LIFETIME_MSK 0xffff
#define R_AX_MBSSID_DROP_0 0xC63C
#define R_AX_MBSSID_DROP_0_C1 0xE63C
#define B_AX_GI_LTF_FB_SEL BIT(30)
#define B_AX_RATE_SEL_SH 24
#define B_AX_RATE_SEL_MSK 0x3f
#define B_AX_PORT_DROP_4_0_SH 16
#define B_AX_PORT_DROP_4_0_MSK 0x1f
#define B_AX_MBSSID_DROP_15_0_SH 0
#define B_AX_MBSSID_DROP_15_0_MSK 0xffff
#define R_AX_ARFR_WT_0 0xC640
#define R_AX_ARFR_WT_0_C1 0xE640
#define B_AX_RATE7_WEIGHTING_SH 28
#define B_AX_RATE7_WEIGHTING_MSK 0xf
#define B_AX_RATE6_WEIGHTING_SH 24
#define B_AX_RATE6_WEIGHTING_MSK 0xf
#define B_AX_RATE5_WEIGHTING_SH 20
#define B_AX_RATE5_WEIGHTING_MSK 0xf
#define B_AX_RATE4_WEIGHTING_SH 16
#define B_AX_RATE4_WEIGHTING_MSK 0xf
#define B_AX_RATE3_WEIGHTING_SH 12
#define B_AX_RATE3_WEIGHTING_MSK 0xf
#define B_AX_RATE2_WEIGHTING_SH 8
#define B_AX_RATE2_WEIGHTING_MSK 0xf
#define B_AX_RATE1_WEIGHTING_SH 4
#define B_AX_RATE1_WEIGHTING_MSK 0xf
#define B_AX_RATE0_WEIGHTING_SH 0
#define B_AX_RATE0_WEIGHTING_MSK 0xf
#define R_AX_DARF_TC 0xC648
#define R_AX_DARF_TC_C1 0xE648
#define B_AX_DARF_TC9_SH 28
#define B_AX_DARF_TC9_MSK 0xf
#define B_AX_DARF_TC8_SH 24
#define B_AX_DARF_TC8_MSK 0xf
#define B_AX_DARF_TC7_SH 20
#define B_AX_DARF_TC7_MSK 0xf
#define B_AX_DARF_TC6_SH 16
#define B_AX_DARF_TC6_MSK 0xf
#define B_AX_DARF_TC5_SH 12
#define B_AX_DARF_TC5_MSK 0xf
#define B_AX_DARF_TC4_SH 8
#define B_AX_DARF_TC4_MSK 0xf
#define B_AX_DARF_TC3_SH 4
#define B_AX_DARF_TC3_MSK 0xf
#define B_AX_DARF_TC2_SH 0
#define B_AX_DARF_TC2_MSK 0xf
#define R_AX_DARF1_TC 0xC64C
#define R_AX_DARF1_TC_C1 0xE64C
#define B_AX_DARF1_TC9_SH 28
#define B_AX_DARF1_TC9_MSK 0xf
#define B_AX_DARF1_TC8_SH 24
#define B_AX_DARF1_TC8_MSK 0xf
#define B_AX_DARF1_TC7_SH 20
#define B_AX_DARF1_TC7_MSK 0xf
#define B_AX_DARF1_TC6_SH 16
#define B_AX_DARF1_TC6_MSK 0xf
#define B_AX_DARF1_TC5_SH 12
#define B_AX_DARF1_TC5_MSK 0xf
#define B_AX_DARF1_TC4_SH 8
#define B_AX_DARF1_TC4_MSK 0xf
#define B_AX_DARF1_TC3_SH 4
#define B_AX_DARF1_TC3_MSK 0xf
#define B_AX_DARF1_TC2_SH 0
#define B_AX_DARF1_TC2_MSK 0xf
#define R_AX_RARF_TC 0xC650
#define R_AX_RARF_TC_C1 0xE650
#define B_AX_RARF_TC9_SH 28
#define B_AX_RARF_TC9_MSK 0xf
#define B_AX_RARF_TC8_SH 24
#define B_AX_RARF_TC8_MSK 0xf
#define B_AX_RARF_TC7_SH 20
#define B_AX_RARF_TC7_MSK 0xf
#define B_AX_RARF_TC6_SH 16
#define B_AX_RARF_TC6_MSK 0xf
#define B_AX_RARF_TC5_SH 12
#define B_AX_RARF_TC5_MSK 0xf
#define B_AX_RARF_TC4_SH 8
#define B_AX_RARF_TC4_MSK 0xf
#define B_AX_RARF_TC3_SH 4
#define B_AX_RARF_TC3_MSK 0xf
#define B_AX_RARF_TC2_SH 0
#define B_AX_RARF_TC2_MSK 0xf
#define R_AX_PTCL_ATM 0xC654
#define R_AX_PTCL_ATM_C1 0xE654
#define B_AX_CHNL_REF_RX_BASIC_NAV BIT(31)
#define B_AX_CHNL_REF_RX_INTRA_NAV BIT(30)
#define B_AX_CHNL_REF_DATA_ON BIT(29)
#define B_AX_CHNL_REF_EDCCA_P20 BIT(28)
#define B_AX_CHNL_REF_CCA_P20 BIT(27)
#define B_AX_CHNL_REF_CCA_S20 BIT(26)
#define B_AX_CHNL_REF_CCA_S40 BIT(25)
#define B_AX_CHNL_REF_CCA_S80 BIT(24)
#define B_AX_CHNL_REF_PHY_TXON BIT(23)
#define B_AX_RST_CHNL_BUSY BIT(19)
#define B_AX_RST_CHNL_IDLE BIT(18)
#define B_AX_CHNL_INFO_EN BIT(17)
#define B_AX_ATM_AIRTIME_EN BIT(16)
#define B_AX_ATM_TF_UD BIT(12)
#define B_AX_ATM_SR_UD_1_SH 10
#define B_AX_ATM_SR_UD_1_MSK 0x3
#define B_AX_ATM_SR_UD_0_SH 8
#define B_AX_ATM_SR_UD_0_MSK 0x3
#define B_AX_ATM_TB_UD_1_SH 6
#define B_AX_ATM_TB_UD_1_MSK 0x3
#define B_AX_ATM_TB_UD_0_SH 4
#define B_AX_ATM_TB_UD_0_MSK 0x3
#define B_AX_ATM_TX_UD_1_SH 2
#define B_AX_ATM_TX_UD_1_MSK 0x3
#define B_AX_ATM_TX_UD_0_SH 0
#define B_AX_ATM_TX_UD_0_MSK 0x3
#define R_AX_CHNL_IDLE_TIME_0 0xC658
#define R_AX_CHNL_IDLE_TIME_0_C1 0xE658
#define B_AX_CHNL_IDLE_TIME_SH 0
#define B_AX_CHNL_IDLE_TIME_MSK 0xffffffffL
#define R_AX_CHNL_BUSY_TIME_0 0xC65C
#define R_AX_CHNL_BUSY_TIME_0_C1 0xE65C
#define B_AX_CHNL_BUSY_TIME_SH 0
#define B_AX_CHNL_BUSY_TIME_MSK 0xffffffffL
#define R_AX_PTCLRPT_FULL_HDL 0xC660
#define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
#define B_AX_F2PCMD_RPT_EN BIT(8)
#define B_AX_BCN_RPT_PATH_SH 6
#define B_AX_BCN_RPT_PATH_MSK 0x3
#define B_AX_SPE_RPT_PATH_SH 4
#define B_AX_SPE_RPT_PATH_MSK 0x3
#define B_AX_TX_RPT_PATH_SH 2
#define B_AX_TX_RPT_PATH_MSK 0x3
#define B_AX_F2PCMDRPT_FULL_DROP BIT(1)
#define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
#define R_AX_PTCL_TXOP_BK 0xC670
#define R_AX_PTCL_TXOP_BK_C1 0xE670
#define B_AX_DIS_TXOP_CFE BIT(31)
#define B_AX_DIS_LSIG_CFE BIT(30)
#define B_AX_TXOP_BK_PKT_NUM_SH 12
#define B_AX_TXOP_BK_PKT_NUM_MSK 0x3f
#define B_AX_TXOP_BK_TX_TIME_SH 4
#define B_AX_TXOP_BK_TX_TIME_MSK 0xff
#define B_AX_TXOP_BK_EN_SH 0
#define B_AX_TXOP_BK_EN_MSK 0xf
#define B_AX_SPEC_MBA_HE_PTCL_SH 16
#define B_AX_SPEC_MBA_HE_PTCL_MSK 0xffff
#define B_AX_NAV_PROT_LEN_SH 0
#define B_AX_NAV_PROT_LEN_MSK 0xffff
#define R_AX_PROT_0 0xC674
#define R_AX_PROT_0_C1 0xE674
#define B_AX_SPEC_MBA_HE_PTCL_SH 16
#define B_AX_SPEC_MBA_HE_PTCL_MSK 0xffff
#define B_AX_NAV_PROT_LEN_SH 0
#define B_AX_NAV_PROT_LEN_MSK 0xffff
#define R_AX_PROT 0xC678
#define R_AX_PROT_C1 0xE678
#define B_AX_NAV_OVER_TXOP_EN BIT(16)
#define B_AX_NAV_PROT_LEN_CTN_MODE_SH 0
#define B_AX_NAV_PROT_LEN_CTN_MODE_MSK 0xffff
#define R_AX_BT_PLT 0xC67C
#define R_AX_BT_PLT_C1 0xE67C
#define B_AX_BT_PLT_PKT_CNT_SH 16
#define B_AX_BT_PLT_PKT_CNT_MSK 0xffff
#define B_AX_BT_PLT_RST BIT(9)
#define B_AX_PLT_EN BIT(8)
#define B_AX_RX_PLT_GNT_LTE_RX BIT(7)
#define B_AX_RX_PLT_GNT_BT_RX BIT(6)
#define B_AX_RX_PLT_GNT_BT_TX BIT(5)
#define B_AX_RX_PLT_GNT_WL BIT(4)
#define B_AX_TX_PLT_GNT_LTE_RX BIT(3)
#define B_AX_TX_PLT_GNT_BT_RX BIT(2)
#define B_AX_TX_PLT_GNT_BT_TX BIT(1)
#define B_AX_TX_PLT_GNT_WL BIT(0)
#define R_AX_TWTQ_CTRL1 0xC680
#define R_AX_TWTQ_CTRL1_C1 0xE680
#define B_AX_TWTQ_ULTRHD_SH 16
#define B_AX_TWTQ_ULTRHD_MSK 0xffff
#define B_AX_TWTQ_TXOPTRHD_SH 0
#define B_AX_TWTQ_TXOPTRHD_MSK 0xffff
#define R_AX_TWTQ_CTRL2 0xC684
#define R_AX_TWTQ_CTRL2_C1 0xE684
#define B_AX_TWTQ_AGGTRHD_SH 0
#define B_AX_TWTQ_AGGTRHD_MSK 0xffff
#define R_AX_BCNQ_CTRL 0xC690
#define R_AX_BCNQ_CTRL_C1 0xE690
#define B_AX_BCNQ_LOCK_STUS BIT(31)
#define B_AX_BCNQ_LOCK BIT(0)
#define R_AX_PTCL_BSS_COLOR_0 0xC6A0
#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0
#define B_AX_BSS_COLOB_AX_PORT_3_SH 24
#define B_AX_BSS_COLOB_AX_PORT_3_MSK 0x3f
#define B_AX_BSS_COLOB_AX_PORT_2_SH 16
#define B_AX_BSS_COLOB_AX_PORT_2_MSK 0x3f
#define B_AX_BSS_COLOB_AX_PORT_1_SH 8
#define B_AX_BSS_COLOB_AX_PORT_1_MSK 0x3f
#define B_AX_BSS_COLOB_AX_PORT_0_SH 0
#define B_AX_BSS_COLOB_AX_PORT_0_MSK 0x3f
#define R_AX_PTCL_BSS_COLOR_1 0xC6A4
#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4
#define B_AX_BSS_COLOB_AX_PORT_4_SH 0
#define B_AX_BSS_COLOB_AX_PORT_4_MSK 0x3f
#define R_AX_PTCL_F2P_TX_SETTING 0xC6B0
#define R_AX_PTCL_F2P_TX_SETTING_C1 0xE6B0
#define B_AX_TF_DATA_TF_LENGTH_SH 0
#define B_AX_TF_DATA_TF_LENGTH_MSK 0xff
#define R_AX_PTCL_IMR0 0xC6C0
#define R_AX_PTCL_IMR0_C1 0xE6C0
#define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
#define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30)
#define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29)
#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28)
#define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27)
#define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26)
#define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25)
#define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24)
#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23)
#define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15)
#define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14)
#define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12)
#define B_AX_Q_PKTID_ERR_INT_EN BIT(11)
#define B_AX_D_PKTID_ERR_INT_EN BIT(10)
#define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9)
#define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8)
#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
#define R_AX_PTCL_ISR0 0xC6C4
#define R_AX_PTCL_ISR0_C1 0xE6C4
#define B_AX_F2PCMD_PKTID_ERR BIT(31)
#define B_AX_F2PCMD_RD_PKTID_ERR BIT(30)
#define B_AX_F2PCMD_ASSIGN_PKTID_ERR BIT(29)
#define B_AX_F2PCMD_USER_ALLC_ERR BIT(28)
#define B_AX_RX_SPF_U0_PKTID_ERR BIT(27)
#define B_AX_TX_SPF_U1_PKTID_ERR BIT(26)
#define B_AX_TX_SPF_U2_PKTID_ERR BIT(25)
#define B_AX_TX_SPF_U3_PKTID_ERR BIT(24)
#define B_AX_TX_RECORD_PKTID_ERR BIT(23)
#define B_AX_F2PCMD_EMPTY_ERR BIT(15)
#define B_AX_TWTSP_QSEL_ERR BIT(14)
#define B_AX_BCNQ_ORDER_ERR BIT(12)
#define B_AX_Q_PKTID_ERR BIT(11)
#define B_AX_D_PKTID_ERR BIT(10)
#define B_AX_TXPRT_FULL_DROP_ERR BIT(9)
#define B_AX_F2PCMDRPT_FULL_DROP_ERR BIT(8)
#define B_AX_FSM_TIMEOUT_ERR BIT(0)
#define R_AX_PTCL_RST_CTRL 0xC6E0
#define R_AX_PTCL_RST_CTRL_C1 0xE6E0
#define B_AX_PTCL_TX_FINISH_REQ_STATUS BIT(24)
#define B_AX_PTCL_WDE_EN BIT(1)
#define B_AX_PTCL_TX_FINISH_REQ BIT(0)
#define R_AX_PTCL_FSM_MON 0xC6E8
#define R_AX_PTCL_FSM_MON_C1 0xE6E8
#define B_AX_PTCL_FSM2_TO_MODE BIT(30)
#define B_AX_PTCL_FSM2_TO_THR_SH 24
#define B_AX_PTCL_FSM2_TO_THR_MSK 0x3f
#define B_AX_PTCL_FSM1_TO_MODE BIT(22)
#define B_AX_PTCL_FSM1_TO_THR_SH 16
#define B_AX_PTCL_FSM1_TO_THR_MSK 0x3f
#define B_AX_PTCL_FSM0_TO_MODE BIT(14)
#define B_AX_PTCL_FSM0_TO_THR_SH 8
#define B_AX_PTCL_FSM0_TO_THR_MSK 0x3f
#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6)
#define B_AX_PTCL_TX_ARB_TO_THR_SH 0
#define B_AX_PTCL_TX_ARB_TO_THR_MSK 0x3f
#define R_AX_PTCL_TX_CTN_SEL 0xC6EC
#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC
#define B_AX_PTCL_TX_ON_STAT BIT(7)
#define B_AX_PTCL_DROP BIT(5)
#define B_AX_PTCL_TX_QUEUE_IDX_SH 0
#define B_AX_PTCL_TX_QUEUE_IDX_MSK 0x1f
#define R_AX_PTCL_DBG_INFO 0xC6F0
#define R_AX_PTCL_DBG_INFO_C1 0xE6F0
#define B_AX_PTCL_DBG_INFO_SH 0
#define B_AX_PTCL_DBG_INFO_MSK 0xffffffffL
#define R_AX_NULL_PKT_STATUS 0xC6F6
#define R_AX_NULL_PKT_STATUS_C1 0xE6F6
#define B_AX_P4_NULL_1_STATUS BIT(9)
#define B_AX_P4_NULL_0_STATUS BIT(8)
#define B_AX_P3_NULL_1_STATUS BIT(7)
#define B_AX_P3_NULL_0_STATUS BIT(6)
#define B_AX_P2_NULL_1_STATUS BIT(5)
#define B_AX_P2_NULL_0_STATUS BIT(4)
#define B_AX_P1_NULL_1_STATUS BIT(3)
#define B_AX_P1_NULL_0_STATUS BIT(2)
#define B_AX_P0_NULL_1_STATUS BIT(1)
#define B_AX_P0_NULL_0_STATUS BIT(0)
#define R_AX_PTCL_DBG 0xC6F4
#define R_AX_PTCL_DBG_C1 0xE6F4
#define B_AX_PTCL_DBG_EN BIT(8)
#define B_AX_PTCL_DBG_SEL_SH 0
#define B_AX_PTCL_DBG_SEL_MSK 0xff
#define R_AX_PTCL_TX_MACID_0 0xC6FC
#define R_AX_PTCL_TX_MACID_0_C1 0xE6FC
#define B_AX_TX_MACID_3_SH 24
#define B_AX_TX_MACID_3_MSK 0xff
#define B_AX_TX_MACID_2_SH 16
#define B_AX_TX_MACID_2_MSK 0xff
#define B_AX_TX_MACID_1_SH 8
#define B_AX_TX_MACID_1_MSK 0xff
#define B_AX_TX_MACID_0_SH 0
#define B_AX_TX_MACID_0_MSK 0xff
//
// CMAC_DMA 8852C
//
#define R_AX_RX_CTRL2 0xC810
#define R_AX_RX_CTRL2_C1 0xE810
#define B_AX_DLE_WDE_STATE_V1_SH 30
#define B_AX_DLE_WDE_STATE_V1_MSK 0x3
#define B_AX_DLE_PLE_STATE_V1_SH 28
#define B_AX_DLE_PLE_STATE_V1_MSK 0x3
#define B_AX_DLE_REQ_BUF_STATE_SH 26
#define B_AX_DLE_REQ_BUF_STATE_MSK 0x3
#define B_AX_DLE_ENQ_STATE_V1 BIT(25)
#define B_AX_RX_DBG_SEL_SH 19
#define B_AX_RX_DBG_SEL_MSK 0x3f
#define B_AX_MACRX_CS_SH 14
#define B_AX_MACRX_CS_MSK 0x1f
#define B_AX_RXSTS_CS_SH 9
#define B_AX_RXSTS_CS_MSK 0x1f
#define B_AX_ERR_INDICATOR BIT(5)
#define B_AX_TXRPT_CS_SH 0
#define B_AX_TXRPT_CS_MSK 0x1f
#define R_AX_RX_INFO_RU0RU1 0xC814
#define R_AX_RX_INFO_RU0RU1_C1 0xE814
#define B_AX_RU1_IS_IDLE BIT(31)
#define B_AX_RU1_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RU1_IS_REQ_BUF BIT(29)
#define B_AX_RU1_IS_ENQ BIT(28)
#define B_AX_RU1_WR_PKT_ID_SH 16
#define B_AX_RU1_WR_PKT_ID_MSK 0xfff
#define B_AX_RU0_IS_IDLE BIT(15)
#define B_AX_RU0_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RU0_IS_REQ_BUF BIT(13)
#define B_AX_RU0_IS_ENQ BIT(12)
#define B_AX_RU0_WR_PKT_ID_SH 0
#define B_AX_RU0_WR_PKT_ID_MSK 0xfff
#define R_AX_RX_INFO_RU2RU3 0xC818
#define R_AX_RX_INFO_RU2RU3_C1 0xE818
#define B_AX_RU3_IS_IDLE BIT(31)
#define B_AX_RU3_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RU3_IS_REQ_BUF BIT(29)
#define B_AX_RU3_IS_ENQ BIT(28)
#define B_AX_RU3_WR_PKT_ID_SH 16
#define B_AX_RU3_WR_PKT_ID_MSK 0xfff
#define B_AX_RU2_IS_IDLE BIT(15)
#define B_AX_RU2_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RU2_IS_REQ_BUF BIT(13)
#define B_AX_RU2_IS_ENQ BIT(12)
#define B_AX_RU2_WR_PKT_ID_SH 0
#define B_AX_RU2_WR_PKT_ID_MSK 0xfff
#define R_AX_RX_INFO_RU4RU5 0xC81C
#define R_AX_RX_INFO_RU4RU5_C1 0xE81C
#define B_AX_RU5_IS_IDLE BIT(31)
#define B_AX_RU5_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RU5_IS_REQ_BUF BIT(29)
#define B_AX_RU5_IS_ENQ BIT(28)
#define B_AX_RU5_WR_PKT_ID_SH 16
#define B_AX_RU5_WR_PKT_ID_MSK 0xfff
#define B_AX_RU4_IS_IDLE BIT(15)
#define B_AX_RU4_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RU4_IS_REQ_BUF BIT(13)
#define B_AX_RU4_IS_ENQ BIT(12)
#define B_AX_RU4_WR_PKT_ID_SH 0
#define B_AX_RU4_WR_PKT_ID_MSK 0xfff
#define R_AX_RX_INFO_RU6RU7 0xC820
#define R_AX_RX_INFO_RU6RU7_C1 0xE820
#define B_AX_RU7_IS_IDLE BIT(31)
#define B_AX_RU7_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RU7_IS_REQ_BUF BIT(29)
#define B_AX_RU7_IS_ENQ BIT(28)
#define B_AX_RU7_WR_PKT_ID_SH 16
#define B_AX_RU7_WR_PKT_ID_MSK 0xfff
#define B_AX_RU6_IS_IDLE BIT(15)
#define B_AX_RU6_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RU6_IS_REQ_BUF BIT(13)
#define B_AX_RU6_IS_ENQ BIT(12)
#define B_AX_RU6_WR_PKT_ID_SH 0
#define B_AX_RU6_WR_PKT_ID_MSK 0xfff
#define R_AX_RX_INFO_F2P_TXRPT 0xC824
#define R_AX_RX_INFO_F2P_TXRPT_C1 0xE824
#define B_AX_F2PCMD_IS_IDLE_V1 BIT(31)
#define B_AX_F2PCMD_RXDATA_RECOVER_MANNUL_V1 BIT(30)
#define B_AX_F2PCMD_IS_REQ_BUF BIT(29)
#define B_AX_F2PCMD_IS_ENQ BIT(28)
#define B_AX_F2PCMD_WR_PKT_ID_V1_SH 16
#define B_AX_F2PCMD_WR_PKT_ID_V1_MSK 0xfff
#define B_AX_TXRPT_IS_IDLE_V1 BIT(15)
#define B_AX_TXRPT_RXDATA_RECOVER_MANNUL_V1 BIT(14)
#define B_AX_TXRPT_IS_REQ_BUF BIT(13)
#define B_AX_TXRPT_IS_ENQ BIT(12)
#define B_AX_TXRPT_WR_PKT_ID_V1_SH 0
#define B_AX_TXRPT_WR_PKT_ID_V1_MSK 0xfff
#define R_AX_RX_INFO_RXSTS 0xC828
#define R_AX_RX_INFO_RXSTS_C1 0xE828
#define B_AX_ENQ_FIFO_EMPTY BIT(31)
#define B_AX_CSI_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RXSTS_IS_IDLE BIT(15)
#define B_AX_RXSTS_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RXSTS_IS_REQ_BUF BIT(13)
#define B_AX_RXSTS_IS_ENQ BIT(12)
#define B_AX_RXSTS_WR_PKT_ID_SH 0
#define B_AX_RXSTS_WR_PKT_ID_MSK 0xfff
#define R_AX_RX_INFO_CSI 0xC82C
#define R_AX_RX_INFO_CSI_C1 0xE82C
#define B_AX_CSI_PKTID_1_VALID_V1 BIT(31)
#define B_AX_CSI_PKTID_1_V1_SH 16
#define B_AX_CSI_PKTID_1_V1_MSK 0xfff
#define B_AX_CSI_PKTID_0_VALID_V1 BIT(15)
#define B_AX_CSI_PKTID_0_V1_SH 0
#define B_AX_CSI_PKTID_0_V1_MSK 0xfff
//
// CMAC_DMA
//
#define R_AX_DLE_CTRL 0xC800
#define R_AX_DLE_CTRL_C1 0xE800
#define B_AX_NO_RESERVE_PAGE_ERR BIT(31)
#define B_AX_SET_NULL_PKT_ERROR BIT(30)
#define B_AX_PLE_SET_BURST_NUM_ERROR BIT(29)
#define B_AX_PLE_RESPONSE_ERROR BIT(28)
#define B_AX_PLE_OUTPUT_ERROR BIT(27)
#define B_AX_WDE_SET_BURST_NUM_ERROR BIT(26)
#define B_AX_WDE_RESPONSE_ERROR BIT(25)
#define B_AX_WDE_OUTPUT_ERROR BIT(24)
#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23)
#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15)
#define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14)
#define B_AX_DLE_WDE_STATE_SH 11
#define B_AX_DLE_WDE_STATE_MSK 0x3
#define B_AX_DLE_PLE_STATE_SH 9
#define B_AX_DLE_PLE_STATE_MSK 0x3
#define B_AX_DLE_REQUEST_BUFF_STATE_SH 7
#define B_AX_DLE_REQUEST_BUFF_STATE_MSK 0x3
#define B_AX_DLE_ENQ_STATE BIT(6)
#define B_AX_RECOVERY_INDICATOR BIT(5)
#define B_AX_DLE_CLOCK_FORCE BIT(4)
#define B_AX_TXDMA_CLOCK_FORCE BIT(3)
#define B_AX_RXDMA_CLOCK_FORCE BIT(2)
#define B_AX_DMA_DBG_SEL BIT(1)
#define B_AX_PL_PAGE_128B BIT(0)
#define R_AX_RXDMA_CTRL_0 0xC804
#define R_AX_RXDMA_CTRL_0_C1 0xE804
#define B_AX_RXDMA_DBGOUT_EN BIT(31)
#define B_AX_RXDMA_DBG_SEL_SH 29
#define B_AX_RXDMA_DBG_SEL_MSK 0x3
#define B_AX_RXDMA_FIFO_DBG_SEL_SH 25
#define B_AX_RXDMA_FIFO_DBG_SEL_MSK 0xf
#define B_AX_RXDMA_BUFF_REQ_PRI_SH 19
#define B_AX_RXDMA_BUFF_REQ_PRI_MSK 0x3
#define B_AX_RXDMA_TGT_QUEID_SH 13
#define B_AX_RXDMA_TGT_QUEID_MSK 0x3f
#define B_AX_RXDMA_TGT_PRID_SH 10
#define B_AX_RXDMA_TGT_PRID_MSK 0x7
#define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9)
#define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7)
#define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6)
#define B_AX_RXSTS_PTR_FULL_MODE BIT(5)
#define B_AX_CSI_PTR_FULL_MODE BIT(4)
#define B_AX_RU3_PTR_FULL_MODE BIT(3)
#define B_AX_RU2_PTR_FULL_MODE BIT(2)
#define B_AX_RU1_PTR_FULL_MODE BIT(1)
#define B_AX_RU0_PTR_FULL_MODE BIT(0)
#define R_AX_RXDMA_CTRL_1 0xC808
#define R_AX_RXDMA_CTRL_1_C1 0xE808
#define B_AX_F2PCMD_FULL_RSV_DEPTH_SH 28
#define B_AX_F2PCMD_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_TXRPT_FULL_RSV_DEPTH_SH 24
#define B_AX_TXRPT_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_RXSTS_FULL_RSV_DEPTH_SH 20
#define B_AX_RXSTS_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_CSI_FULL_RSV_DEPTH_SH 16
#define B_AX_CSI_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_RU3_FULL_RSV_DEPTH_SH 12
#define B_AX_RU3_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_RU2_FULL_RSV_DEPTH_SH 8
#define B_AX_RU2_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_RU1_FULL_RSV_DEPTH_SH 4
#define B_AX_RU1_FULL_RSV_DEPTH_MSK 0xf
#define B_AX_RU0_FULL_RSV_DEPTH_SH 0
#define B_AX_RU0_FULL_RSV_DEPTH_MSK 0xf
#define R_AX_RXDMA_ERR_FLG_0 0xC80C
#define R_AX_RXDMA_ERR_FLG_0_C1 0xE80C
#define B_AX_RXDMA_ORDER_FIFO_FULL BIT(14)
#define B_AX_RXDMA_F2PCMD_PTR_OVERFLOW BIT(12)
#define B_AX_RXDMA_TXRPT_PTR_OVERFLOW BIT(11)
#define B_AX_RXDMA_RXSTS_PTR_OVERFLOW BIT(10)
#define B_AX_RXDMA_RU3_PTR_OVERFLOW BIT(9)
#define B_AX_RXDMA_RU2_PTR_OVERFLOW BIT(8)
#define B_AX_RXDMA_RU1_PTR_OVERFLOW BIT(7)
#define B_AX_RXDMA_RU0_PTR_OVERFLOW BIT(6)
#define B_AX_RXDMA_RXSTS_PTR_ERROR BIT(5)
#define B_AX_RXDMA_CSI_PTR_ERROR BIT(4)
#define B_AX_RXDMA_RU3_PTR_ERROR BIT(3)
#define B_AX_RXDMA_RU2_PTR_ERROR BIT(2)
#define B_AX_RXDMA_RU1_PTR_ERROR BIT(1)
#define B_AX_RXDMA_RU0_PTR_ERROR BIT(0)
#define R_AX_RXDMA_ERR_FLG_1 0xC810
#define R_AX_RXDMA_ERR_FLG_1_C1 0xE810
#define B_AX_F2PCMD_PKT_ERR_TYPE2 BIT(27)
#define B_AX_F2PCMD_PKT_ERR_TYPE1 BIT(26)
#define B_AX_F2PCMD_DMA_ERR_TYPE2 BIT(25)
#define B_AX_F2PCMD_DMA_ERR_TYPE1 BIT(24)
#define B_AX_TXRPT_PKT_ERR_TYPE2 BIT(23)
#define B_AX_TXRPT_PKT_ERR_TYPE1 BIT(22)
#define B_AX_TXRPT_DMA_ERR_TYPE2 BIT(21)
#define B_AX_TXRPT_DMA_ERR_TYPE1 BIT(20)
#define B_AX_RXSTS_PKT_ERR_TYPE2 BIT(19)
#define B_AX_RXSTS_PKT_ERR_TYPE1 BIT(18)
#define B_AX_RXSTS_DMA_ERR_TYPE2 BIT(17)
#define B_AX_RXSTS_DMA_ERR_TYPE1 BIT(16)
#define B_AX_RU3_PKT_ERR_TYPE2 BIT(15)
#define B_AX_RU3_PKT_ERR_TYPE1 BIT(14)
#define B_AX_RU3_DMA_ERR_TYPE2 BIT(13)
#define B_AX_RU3_DMA_ERR_TYPE1 BIT(12)
#define B_AX_RU2_PKT_ERR_TYPE2 BIT(11)
#define B_AX_RU2_PKT_ERR_TYPE1 BIT(10)
#define B_AX_RU2_DMA_ERR_TYPE2 BIT(9)
#define B_AX_RU2_DMA_ERR_TYPE1 BIT(8)
#define B_AX_RU1_PKT_ERR_TYPE2 BIT(7)
#define B_AX_RU1_PKT_ERR_TYPE1 BIT(6)
#define B_AX_RU1_DMA_ERR_TYPE2 BIT(5)
#define B_AX_RU1_DMA_ERR_TYPE1 BIT(4)
#define B_AX_RU0_PKT_ERR_TYPE2 BIT(3)
#define B_AX_RU0_PKT_ERR_TYPE1 BIT(2)
#define B_AX_RU0_DMA_ERR_TYPE2 BIT(1)
#define B_AX_RU0_DMA_ERR_TYPE1 BIT(0)
#define R_AX_RXDMA_PKT_INFO_0 0xC814
#define R_AX_RXDMA_PKT_INFO_0_C1 0xE814
#define B_AX_RU1_IS_IDLE BIT(31)
#define B_AX_RU1_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RU1_WR_PKT_ID_SH 16
#define B_AX_RU1_WR_PKT_ID_MSK 0xfff
#define B_AX_RU0_IS_IDLE BIT(15)
#define B_AX_RU0_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RU0_WR_PKT_ID_SH 0
#define B_AX_RU0_WR_PKT_ID_MSK 0xfff
#define R_AX_RXDMA_PKT_INFO_1 0xC818
#define R_AX_RXDMA_PKT_INFO_1_C1 0xE818
#define B_AX_RU3_IS_IDLE BIT(31)
#define B_AX_RU3_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_RU3_WR_PKT_ID_SH 16
#define B_AX_RU3_WR_PKT_ID_MSK 0xfff
#define B_AX_RU2_IS_IDLE BIT(15)
#define B_AX_RU2_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RU2_WR_PKT_ID_SH 0
#define B_AX_RU2_WR_PKT_ID_MSK 0xfff
#define R_AX_RXDMA_PKT_INFO_2 0xC81C
#define R_AX_RXDMA_PKT_INFO_2_C1 0xE81C
#define B_AX_TXRPT_IS_IDLE BIT(31)
#define B_AX_TXRPT_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_TXRPT_WR_PKT_ID_SH 16
#define B_AX_TXRPT_WR_PKT_ID_MSK 0xfff
#define B_AX_RXSTS_IS_IDLE BIT(15)
#define B_AX_RXSTS_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_RXSTS_WR_PKT_ID_SH 0
#define B_AX_RXSTS_WR_PKT_ID_MSK 0xfff
#define R_AX_RXDMA_PKT_INFO_3 0xC820
#define R_AX_RXDMA_PKT_INFO_3_C1 0xE820
#define B_AX_CSI_ENQ_FIFO_EMPTY BIT(31)
#define B_AX_CSI_RXDATA_RECOVER_MANNUL BIT(30)
#define B_AX_F2PCMD_IS_IDLE BIT(15)
#define B_AX_F2PCMD_RXDATA_RECOVER_MANNUL BIT(14)
#define B_AX_F2PCMD_WR_PKT_ID_SH 0
#define B_AX_F2PCMD_WR_PKT_ID_MSK 0xfff
#define R_AX_RXDMA_PKT_INFO_4 0xC824
#define R_AX_RXDMA_PKT_INFO_4_C1 0xE824
#define B_AX_CSI_PKTID_1_VALID BIT(31)
#define B_AX_CSI_PKTID_1_SH 16
#define B_AX_CSI_PKTID_1_MSK 0xfff
#define B_AX_CSI_PKTID_0_VALID BIT(15)
#define B_AX_CSI_PKTID_0_SH 0
#define B_AX_CSI_PKTID_0_MSK 0xfff
#define R_AX_TXDMA_FIFO_INFO_0 0xC834
#define R_AX_TXDMA_FIFO_INFO_0_C1 0xE834
#define B_AX_MACTX_ALLOT_DEPTH_1_SH 0
#define B_AX_MACTX_ALLOT_DEPTH_1_MSK 0x3fffffff
#define R_AX_TXDMA_FIFO_INFO_1 0xC838
#define R_AX_TXDMA_FIFO_INFO_1_C1 0xE838
#define B_AX_RU1_TXFIFO_COUNT_SH 20
#define B_AX_RU1_TXFIFO_COUNT_MSK 0x3ff
#define B_AX_RU0_TXFIFO_COUNT_SH 10
#define B_AX_RU0_TXFIFO_COUNT_MSK 0x3ff
#define B_AX_MACTX_ALLOT_DEPTH_2_SH 0
#define B_AX_MACTX_ALLOT_DEPTH_2_MSK 0x3ff
#define R_AX_TXDMA_FIFO_INFO_2 0xC83C
#define R_AX_TXDMA_FIFO_INFO_2_C1 0xE83C
#define B_AX_RU3_TXFIFO_COUNT_SH 10
#define B_AX_RU3_TXFIFO_COUNT_MSK 0x3ff
#define B_AX_RU2_TXFIFO_COUNT_SH 0
#define B_AX_RU2_TXFIFO_COUNT_MSK 0x3ff
#define R_AX_TXDMA_DBG 0xC840
#define R_AX_TXDMA_DBG_C1 0xE840
#define B_AX_TXDMA_DBG_SEL_SH 27
#define B_AX_TXDMA_DBG_SEL_MSK 0x1f
#define B_AX_TXDMA_DBG_EN BIT(26)
#define B_AX_TX_FINISH_REQ BIT(6)
#define B_AX_PL_ARB_RU_SH 4
#define B_AX_PL_ARB_RU_MSK 0x3
#define B_AX_WD_ARB_RU_SH 2
#define B_AX_WD_ARB_RU_MSK 0x3
#define B_AX_REQ_WD_PLD_ID_CS_SH 0
#define B_AX_REQ_WD_PLD_ID_CS_MSK 0x3
#define R_AX_TXDMA_RU_INFO_0 0xC844
#define R_AX_TXDMA_RU_INFO_0_C1 0xE844
#define B_AX_RU0_CUR_WD_ID_SH 18
#define B_AX_RU0_CUR_WD_ID_MSK 0xfff
#define B_AX_RU0_CUR_PL_ID_SH 6
#define B_AX_RU0_CUR_PL_ID_MSK 0xfff
#define B_AX_RU0_READ_CS_SH 3
#define B_AX_RU0_READ_CS_MSK 0x7
#define B_AX_RU0_WRITE_CS_SH 0
#define B_AX_RU0_WRITE_CS_MSK 0x7
#define R_AX_TXDMA_RU_INFO_1 0xC848
#define R_AX_TXDMA_RU_INFO_1_C1 0xE848
#define B_AX_RU1_CUR_WD_ID_SH 18
#define B_AX_RU1_CUR_WD_ID_MSK 0xfff
#define B_AX_RU1_CUR_PL_ID_SH 6
#define B_AX_RU1_CUR_PL_ID_MSK 0xfff
#define B_AX_RU1_READ_CS_SH 3
#define B_AX_RU1_READ_CS_MSK 0x7
#define B_AX_RU1_WRITE_CS_SH 0
#define B_AX_RU1_WRITE_CS_MSK 0x7
#define R_AX_TXDMA_RU_INFO_2 0xC84C
#define R_AX_TXDMA_RU_INFO_2_C1 0xE84C
#define B_AX_RU2_CUR_WD_ID_SH 18
#define B_AX_RU2_CUR_WD_ID_MSK 0xfff
#define B_AX_RU2_CUR_PL_ID_SH 6
#define B_AX_RU2_CUR_PL_ID_MSK 0xfff
#define B_AX_RU2_READ_CS_SH 3
#define B_AX_RU2_READ_CS_MSK 0x7
#define B_AX_RU2_WRITE_CS_SH 0
#define B_AX_RU2_WRITE_CS_MSK 0x7
#define R_AX_TXDMA_RU_INFO_3 0xC850
#define R_AX_TXDMA_RU_INFO_3_C1 0xE850
#define B_AX_RU3_CUR_WD_ID_SH 18
#define B_AX_RU3_CUR_WD_ID_MSK 0xfff
#define B_AX_RU3_CUR_PL_ID_SH 6
#define B_AX_RU3_CUR_PL_ID_MSK 0xfff
#define B_AX_RU3_READ_CS_SH 3
#define B_AX_RU3_READ_CS_MSK 0x7
#define B_AX_RU3_WRITE_CS_SH 0
#define B_AX_RU3_WRITE_CS_MSK 0x7
//
// TMAC
//
#define R_AX_TCR0 0xCA00
#define R_AX_TCR0_C1 0xEA00
#define B_AX_TCR_ZLD_NUM_SH 24
#define B_AX_TCR_ZLD_NUM_MSK 0xff
#define B_AX_TCR_UDF_EN BIT(23)
#define B_AX_TCR_UDF_THSD_SH 16
#define B_AX_TCR_UDF_THSD_MSK 0x7f
#define B_AX_TCR_ERRSTEN_SH 10
#define B_AX_TCR_ERRSTEN_MSK 0x3f
#define B_AX_TCR_VHTSIGA1_TXPS BIT(9)
#define B_AX_TCR_PLCP_ERRHDL_EN BIT(8)
#define B_AX_TCR_PADSEL BIT(7)
#define B_AX_TCR_MASK_SIGBCRC BIT(6)
#define B_AX_TCR_SR_VAL15_ALLOW BIT(5)
#define B_AX_TCR_EN_EOF BIT(4)
#define B_AX_TCR_EN_SCRAM_INC BIT(3)
#define B_AX_TCR_EN_20MST BIT(2)
#define B_AX_TCR_CRC BIT(1)
#define B_AX_TCR_DISGCLK BIT(0)
#define R_AX_TCR1 0xCA04
#define R_AX_TCR1_C1 0xEA04
#define B_AX_TXDFIFO_THRESHOLD_SH 28
#define B_AX_TXDFIFO_THRESHOLD_MSK 0xf
#define B_AX_TCR_CCK_LOCK_CLK BIT(27)
#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26)
#define B_AX_TCR_USTIME_SH 16
#define B_AX_TCR_USTIME_MSK 0xff
#define B_AX_TCR_SMOOTH_VAL BIT(15)
#define B_AX_TCR_SMOOTH_CTRL BIT(14)
#define B_AX_CS_REQ_VAL BIT(13)
#define B_AX_CS_REQ_SEL BIT(12)
#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON_SH 8
#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON_MSK 0xf
#define B_AX_TCR_TXTIMEOUT_SH 0
#define B_AX_TCR_TXTIMEOUT_MSK 0xff
#define R_AX_MD_TSFT_STMP_CTL 0xCA08
#define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
#define B_AX_TSFT_OFS_SH 16
#define B_AX_TSFT_OFS_MSK 0xffff
#define B_AX_STMP_THSD_SH 8
#define B_AX_STMP_THSD_MSK 0xff
#define B_AX_UPD_HGQMD BIT(1)
#define B_AX_UPD_TIMIE BIT(0)
#define R_AX_PPWRBIT_SETTING 0xCA0C
#define R_AX_PPWRBIT_SETTING_C1 0xEA0C
#define B_AX_P4_PWRMGT_CTRL_EN BIT(19)
#define B_AX_P4_PWRMGT_DATA_EN BIT(18)
#define B_AX_P4_PWRMGT_ACT_EN BIT(17)
#define B_AX_P4_PWR_ST BIT(16)
#define B_AX_P3_PWRMGT_CTRL_EN BIT(15)
#define B_AX_P3_PWRMGT_DATA_EN BIT(14)
#define B_AX_P3_PWRMGT_ACT_EN BIT(13)
#define B_AX_P3_PWR_ST BIT(12)
#define B_AX_P2_PWRMGT_CTRL_EN BIT(11)
#define B_AX_P2_PWRMGT_DATA_EN BIT(10)
#define B_AX_P2_PWRMGT_ACT_EN BIT(9)
#define B_AX_P2_PWR_ST BIT(8)
#define B_AX_P1_PWRMGT_CTRL_EN BIT(7)
#define B_AX_P1_PWRMGT_DATA_EN BIT(6)
#define B_AX_P1_PWRMGT_ACT_EN BIT(5)
#define B_AX_P1_PWR_ST BIT(4)
#define B_AX_P0_PWRMGT_CTRL_EN BIT(3)
#define B_AX_P0_PWRMGT_DATA_EN BIT(2)
#define B_AX_P0_PWRMGT_ACT_EN BIT(1)
#define B_AX_P0_PWR_ST BIT(0)
#define R_AX_HTC 0xCA10
#define R_AX_HTC_C1 0xEA10
#define B_AX_MHDR_HTC_SH 0
#define B_AX_MHDR_HTC_MSK 0xffffffffL
#define R_AX_SOUNDING 0xCA14
#define R_AX_SOUNDING_C1 0xEA14
#define B_AX_USE_NSTS BIT(22)
#define B_AX_RETRY_BFRPT_SEQ_UPD BIT(21)
#define B_AX_TXNDP_SIGB_SH 0
#define B_AX_TXNDP_SIGB_MSK 0x1fffff
#define R_AX_BSR_CTRL 0xCA18
#define R_AX_BSR_CTRL_C1 0xEA18
#define B_AX_RO_MIN_TX_PWR_FLAG BIT(21)
#define B_AX_RO_UPH_SH 16
#define B_AX_RO_UPH_MSK 0x1f
#define B_AX_BSR_BK_TID_SEL BIT(4)
#define B_AX_BSR_BE_TID_SEL BIT(3)
#define B_AX_BSR_VI_TID_SEL BIT(2)
#define B_AX_BSR_VO_TID_SEL BIT(1)
#define B_AX_BSR_QOS_SEL BIT(0)
#define R_AX_TXD_FIFO_CTRL 0xCA1C
#define R_AX_TXD_FIFO_CTRL_C1 0xEA1C
#define B_AX_TXDFIFO_HIGH_MCS_THRE_SH 12
#define B_AX_TXDFIFO_HIGH_MCS_THRE_MSK 0xf
#define B_AX_TXDFIFO_LOW_MCS_THRE_SH 8
#define B_AX_TXDFIFO_LOW_MCS_THRE_MSK 0xf
#define B_AX_HIGH_MCS_PHY_RATE_SH 4
#define B_AX_HIGH_MCS_PHY_RATE_MSK 0xf
#define B_AX_BW_PHY_RATE_SH 0
#define B_AX_BW_PHY_RATE_MSK 0x3
#define R_AX_MACTX_DBG_SEL_CNT 0xCA20
#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20
#define B_AX_MACTX_MPDU_CNT_SH 24
#define B_AX_MACTX_MPDU_CNT_MSK 0xff
#define B_AX_MACTX_DMA_CNT_SH 16
#define B_AX_MACTX_DMA_CNT_MSK 0xff
#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11)
#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10)
#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9)
#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8)
#define B_AX_DBGSEL_MACTX_SH 0
#define B_AX_DBGSEL_MACTX_MSK 0x3f
#define R_AX_TX_PPDU_CNT 0xCAE0
#define R_AX_TX_PPDU_CNT_C1 0xEAE0
#define B_AX_TX_PPDU_CNT_SH 16
#define B_AX_TX_PPDU_CNT_MSK 0xffff
#define B_AX_RST_PPDU_CNT BIT(12)
#define B_AX_PPDU_CNT_RIDX_SH 8
#define B_AX_PPDU_CNT_RIDX_MSK 0xf
#define B_AX_PPDU_CNT_IDX_SH 0
#define B_AX_PPDU_CNT_IDX_MSK 0xf
#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4
#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4
#define B_AX_TX_CTRL_DEBUG_SEL_SH 0
#define B_AX_TX_CTRL_DEBUG_SEL_MSK 0xf
#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8
#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8
#define B_AX_TX_CTRL_INFO_P0_SH 0
#define B_AX_TX_CTRL_INFO_P0_MSK 0xffffffffL
#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC
#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC
#define B_AX_TX_CTRL_INFO_P1_SH 0
#define B_AX_TX_CTRL_INFO_P1_MSK 0xffffffffL
//
// TRXPTCL
//
#define R_AX_RSP_CHK_SIG 0xCC00
#define R_AX_RSP_CHK_SIG_C1 0xEC00
#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29)
#define B_AX_RSP_CHK_BASIC_NAV BIT(21)
#define B_AX_RSP_CHK_INTRA_NAV BIT(20)
#define B_AX_RSP_CHK_TX_NAV BIT(19)
#define B_AX_TXDATA_END_PS_OPT BIT(18)
#define B_AX_CHECK_SOUNDING_SEQ BIT(17)
#define B_AX_RXBA_IGNOREA2 BIT(16)
#define B_AX_ACKTO_CCK_SH 8
#define B_AX_ACKTO_CCK_MSK 0xff
#define B_AX_ACKTO_SH 0
#define B_AX_ACKTO_MSK 0xff
#define R_AX_TRXPTCL_RESP_0 0xCC04
#define R_AX_TRXPTCL_RESP_0_C1 0xEC04
#define B_AX_WMAC_RESP_STBC_EN BIT(31)
#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30)
#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29)
#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28)
#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27)
#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26)
#define B_AX_RSP_CHK_BTCCA BIT(25)
#define B_AX_RSP_CHK_EDCCA BIT(24)
#define B_AX_RSP_CHK_CCA BIT(23)
#define B_AX_WMAC_LDPC_EN BIT(22)
#define B_AX_WMAC_SGIEN BIT(21)
#define B_AX_WMAC_SPLCPEN BIT(20)
#define B_AX_WMAC_BESP_CHNBUSY_SH 18
#define B_AX_WMAC_BESP_CHNBUSY_MSK 0x3
#define B_AX_WMAC_BESP_EABLY_TXBA BIT(17)
#define B_AX_WMAC_EN_TXACKBA_INTXOP BIT(16)
#define B_AX_WMAC_SPEC_SIFS_OFDM_SH 8
#define B_AX_WMAC_SPEC_SIFS_OFDM_MSK 0xff
#define B_AX_WMAC_SPEC_SIFS_CCK_SH 0
#define B_AX_WMAC_SPEC_SIFS_CCK_MSK 0xff
#define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
#define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
#define B_AX_FTM_RRSR_RATE_EN_SH 24
#define B_AX_FTM_RRSR_RATE_EN_MSK 0xf
#define B_AX_NESS_SH 22
#define B_AX_NESS_MSK 0x3
#define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21)
#define B_AX_WMAC_RESP_DCM_EN BIT(20)
#define B_AX_WMAC_RRSB_AX_CCK_SH 16
#define B_AX_WMAC_RRSB_AX_CCK_MSK 0xf
#define B_AX_WMAC_RESP_RATE_EN_SH 12
#define B_AX_WMAC_RESP_RATE_EN_MSK 0xf
#define B_AX_WMAC_RESP_RSC_SH 10
#define B_AX_WMAC_RESP_RSC_MSK 0x3
#define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
#define B_AX_WMAC_RESP_REF_RATE_SH 0
#define B_AX_WMAC_RESP_REF_RATE_MSK 0x1ff
#define R_AX_TRXPTCL_RRSR_CTL_1 0xCC0C
#define R_AX_TRXPTCL_RRSR_CTL_1_C1 0xEC0C
#define B_AX_WMAC_RRSR_HE_SH 24
#define B_AX_WMAC_RRSR_HE_MSK 0xff
#define B_AX_WMAC_RRSR_VHT_SH 16
#define B_AX_WMAC_RRSR_VHT_MSK 0xff
#define B_AX_WMAC_RRSR_HT_SH 8
#define B_AX_WMAC_RRSR_HT_MSK 0xff
#define B_AX_WMAC_RRSR_OFDM_SH 0
#define B_AX_WMAC_RRSR_OFDM_MSK 0xff
#define R_AX_TRXPTCL_RESP_TX_ABORT_COUNTER 0xCC1C
#define R_AX_TRXPTCL_RESP_TX_ABORT_COUNTER_C1 0xEC1C
#define B_AX_WMAC_RMAC_BUSY_ABORT_RESP_TX_SH 24
#define B_AX_WMAC_RMAC_BUSY_ABORT_RESP_TX_MSK 0xff
#define B_AX_WMAC_NAV_ABORT_RESP_TX_SH 16
#define B_AX_WMAC_NAV_ABORT_RESP_TX_MSK 0xff
#define B_AX_WMAC_SEC_CCA_ABORT_RESP_TX_SH 8
#define B_AX_WMAC_SEC_CCA_ABORT_RESP_TX_MSK 0xff
#define B_AX_WMAC_CCA_ABORT_RESP_TX_SH 0
#define B_AX_WMAC_CCA_ABORT_RESP_TX_MSK 0xff
#define R_AX_MAC_LOOPBACK 0xCC20
#define R_AX_MAC_LOOPBACK_C1 0xEC20
#define B_AX_MACLBK_RDY_PERIOD_SH 17
#define B_AX_MACLBK_RDY_PERIOD_MSK 0xfff
#define B_AX_MACLBK_PLCP_DLY_SH 8
#define B_AX_MACLBK_PLCP_DLY_MSK 0x1ff
#define B_AX_MACLBK_RDY_NUM_SH 3
#define B_AX_MACLBK_RDY_NUM_MSK 0x1f
#define B_AX_MACLBK_EN BIT(0)
#define R_AX_TRXPTCL_CTS_RRSR 0xCC24
#define R_AX_TRXPTCL_CTS_RRSR_C1 0xEC24
#define B_AX_WMAC_CTS_RRSR_RSC_SH 14
#define B_AX_WMAC_CTS_RRSR_RSC_MSK 0x3
#define B_AX_WMAC_CTS_RESP_OPT BIT(12)
#define B_AX_WMAC_CTS_RRSR_CCK_SH 8
#define B_AX_WMAC_CTS_RRSR_CCK_MSK 0xf
#define B_AX_WMAC_CTS_RRSR_OFDM_SH 0
#define B_AX_WMAC_CTS_RRSR_OFDM_MSK 0xff
#define R_AX_MAC_LOOPBACK_COUNT 0xCC28
#define R_AX_MAC_LOOPBACK_COUNT_C1 0xEC28
#define B_AX_MACLBK_COUNT_CLR BIT(0)
#define R_AX_CLIENT_OM_CTRL 0xCC40
#define R_AX_CLIENT_OM_CTRL_C1 0xEC40
#define B_AX_WMAC_DIS_SIGTA BIT(16)
#define B_AX_UL_DATA_DIS_SH 0
#define B_AX_UL_DATA_DIS_MSK 0x1f
#define R_AX_WMAC_FTM_CTL 0xCC50
#define R_AX_WMAC_FTM_CTL_C1 0xEC50
#define B_AX_FTM_RPT_ERROR BIT(15)
#define B_AX_FTM_TIMEOUT_BYPASS BIT(14)
#define B_AX_RXFTM_EN BIT(2)
#define B_AX_RXFTMREQ_EN BIT(1)
#define B_AX_FTM_EN BIT(0)
#define R_AX_GET_RTT 0xCC54
#define R_AX_GET_RTT_C1 0xEC54
#define B_AX_ACTION_FIELD_SH 16
#define B_AX_ACTION_FIELD_MSK 0xff
#define B_AX_CATEGORY_FIELD_SH 8
#define B_AX_CATEGORY_FIELD_MSK 0xff
#define B_AX_RTT_TYPE_SUBTYPE_SH 1
#define B_AX_RTT_TYPE_SUBTYPE_MSK 0x3f
#define B_AX_RTT_FILTER_EN BIT(0)
#define R_AX_FTM_PTT 0xCC58
#define R_AX_FTM_PTT_C1 0xEC58
#define B_AX_FTM_PTT_TSF_R2T_SEL_SH 3
#define B_AX_FTM_PTT_TSF_R2T_SEL_MSK 0x7
#define B_AX_FTM_PTT_TSF_T2R_SEL_SH 0
#define B_AX_FTM_PTT_TSF_T2R_SEL_MSK 0x7
#define R_AX_FTM_TSF 0xCC5C
#define R_AX_FTM_TSF_C1 0xEC5C
#define B_AX_FTM_T2_TSF_SH 16
#define B_AX_FTM_T2_TSF_MSK 0xffff
#define B_AX_FTM_T1_TSF_SH 0
#define B_AX_FTM_T1_TSF_MSK 0xffff
#define R_AX_MD_CTRL 0xCC72
#define R_AX_MD_CTRL_C1 0xEC72
#define B_AX_BC_MD_EN BIT(1)
#define B_AX_UC_MD_EN BIT(0)
#define R_AX_WMMPS_UAPSD_TID 0xCC70
#define R_AX_WMMPS_UAPSD_TID_C1 0xEC70
#define B_AX_WMMPS_UAPSD_TID7 BIT(7)
#define B_AX_WMMPS_UAPSD_TID6 BIT(6)
#define B_AX_WMMPS_UAPSD_TID5 BIT(5)
#define B_AX_WMMPS_UAPSD_TID4 BIT(4)
#define B_AX_WMMPS_UAPSD_TID3 BIT(3)
#define B_AX_WMMPS_UAPSD_TID2 BIT(2)
#define B_AX_WMMPS_UAPSD_TID1 BIT(1)
#define B_AX_WMMPS_UAPSD_TID0 BIT(0)
#define R_AX_WMAC_NAV_CTL 0xCC80
#define R_AX_WMAC_NAV_CTL_C1 0xEC80
#define R_AX_WMAC_NAV_UP_INFO 0xCC84
#define R_AX_WMAC_NAV_UP_INFO_C1 0xEC84
#define R_AX_RXTRIG_TEST_COMM_0 0xCCA0
#define R_AX_RXTRIG_TEST_COMM_0_C1 0xECA0
#define R_AX_RXTRIG_TEST_COMM_1 0xCCA4
#define R_AX_RXTRIG_TEST_COMM_1_C1 0xECA4
#define R_AX_RXTRIG_TEST_USER_0 0xCCA8
#define R_AX_RXTRIG_TEST_USER_0_C1 0xECA8
#define R_AX_RXTRIG_TEST_USER_1 0xCCAC
#define R_AX_RXTRIG_TEST_USER_1_C1 0xECAC
#define R_AX_RXTRIG_TEST_USER_2 0xCCB0
#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0
#define B_AX_RXTRIG_MACID_SH 24
#define B_AX_RXTRIG_MACID_MSK 0xff
#define B_AX_RXTRIG_RU26_DIS BIT(21)
#define B_AX_RXTRIG_FCSCHK_EN BIT(20)
#define B_AX_RXTRIG_PORT_SEL_SH 17
#define B_AX_RXTRIG_PORT_SEL_MSK 0x7
#define B_AX_RXTRIG_EN BIT(16)
#define B_AX_RXTRIG_USERINFO_2_SH 0
#define B_AX_RXTRIG_USERINFO_2_MSK 0xffff
#define R_AX_RXTRIG_TEST_CTRL1 0xCCB4
#define R_AX_RXTRIG_TEST_CTRL1_C1 0xECB4
#define R_AX_SR_CONTROL_DBG 0xCCB8
#define R_AX_SR_CONTROL_DBG_C1 0xECB8
#define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC
#define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC
#define B_AX_WMAC_MODE BIT(22)
#define B_AX_WMAC_TIMETOUT_THR_SH 16
#define B_AX_WMAC_TIMETOUT_THR_MSK 0x3f
#define B_AX_RMAC_FTM BIT(8)
#define B_AX_RMAC_CSI BIT(7)
#define B_AX_TMAC_MIMO_CTRL BIT(6)
#define B_AX_TMAC_RXTB BIT(5)
#define B_AX_TMAC_HWSIGB_GEN BIT(4)
#define B_AX_TMAC_TXPLCP BIT(3)
#define B_AX_TMAC_RESP BIT(2)
#define B_AX_TMAC_TXCTL BIT(1)
#define B_AX_TMAC_MACTX BIT(0)
#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
#define B_AX_WMAC_TX_TF_INFO_SEL_SH 0
#define B_AX_WMAC_TX_TF_INFO_SEL_MSK 0x7
#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4
#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4
#define B_AX_WMAC_TX_TF_INFO_P0_SH 0
#define B_AX_WMAC_TX_TF_INFO_P0_MSK 0xffffffffL
#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8
#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8
#define B_AX_WMAC_TX_TF_INFO_P1_SH 0
#define B_AX_WMAC_TX_TF_INFO_P1_MSK 0xffffffffL
#define R_AX_CTRL_FRAME_CNT_CTRL 0xCCE0
#define R_AX_CTRL_FRAME_CNT_CTRL_C1 0xECE0
#define B_AX_WMAC_ALLCNT_RST BIT(16)
#define B_AX_CTRL_SUBTYPE_SH 12
#define B_AX_CTRL_SUBTYPE_MSK 0xf
#define B_AX_WMAC_WDATA_EN BIT(9)
#define B_AX_WMAC_ALLCNT_EN BIT(8)
#define B_AX_WMAC_CTRL_CNT_IDX_SH 0
#define B_AX_WMAC_CTRL_CNT_IDX_MSK 0xf
#define R_AX_CTRL_FRAME_CNT_SUBCTRL 0xCCE4
#define R_AX_CTRL_FRAME_CNT_SUBCTRL_C1 0xECE4
#define B_AX_CNT_INDEX_SH 8
#define B_AX_CNT_INDEX_MSK 0xf
#define B_AX_CNTRST BIT(1)
#define B_AX_CNTEN BIT(0)
#define R_AX_CTRL_FRAME_CNT_RPT 0xCCE8
#define R_AX_CTRL_FRAME_CNT_RPT_C1 0xECE8
#define B_AX_RX_CTRL_FRAME_CNT_SH 16
#define B_AX_RX_CTRL_FRAME_CNT_MSK 0xffff
#define B_AX_TX_CTRL_FRAME_CNT_SH 0
#define B_AX_TX_CTRL_FRAME_CNT_MSK 0xffff
#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC
#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC
#define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19)
#define B_AX_TMAC_RESP_ERR_CLR BIT(18)
#define B_AX_TMAC_TXCTL_ERR_CLR BIT(17)
#define B_AX_TMAC_MACTX_ERR_CLR BIT(16)
#define B_AX_TMAC_TXPLCP_ERR BIT(14)
#define B_AX_TMAC_RESP_ERR BIT(13)
#define B_AX_TMAC_TXCTL_ERR BIT(12)
#define B_AX_TMAC_MACTX_ERR BIT(11)
#define B_AX_TMAC_TXPLCP_INT_EN BIT(10)
#define B_AX_TMAC_RESP_INT_EN BIT(9)
#define B_AX_TMAC_TXCTL_INT_EN BIT(8)
#define B_AX_TMAC_MACTX_INT_EN BIT(7)
#define B_AX_TMAC_MODE_INT_EN BIT(6)
#define B_AX_TMAC_TIMETOUT_THR_SH 0
#define B_AX_TMAC_TIMETOUT_THR_MSK 0x3f
#define R_AX_WMAC_DEBUG_PORT 0xCCF0
#define R_AX_WMAC_DEBUG_PORT_C1 0xECF0
#define B_AX_WMAC_DEBUG_SH 0
#define B_AX_WMAC_DEBUG_MSK 0xffffffffL
#define R_AX_DBGSEL_TRXPTCL 0xCCF4
#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4
#define B_AX_DBGSEL_TRXPTCL_SH 0
#define B_AX_DBGSEL_TRXPTCL_MSK 0x3f
#define R_AX_PHYINFO_ERR_IMR 0xCCFE
#define R_AX_PHYINFO_ERR_IMR_C1 0xECFE
#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(5)
#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(4)
#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(3)
#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(2)
#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(1)
#define B_AXC_PHY_TXON_TIMEOUT_INT_EN BIT(0)
#define R_AX_PHYINFO_ERR_ISR 0xCCFF
#define R_AX_PHYINFO_ERR_ISR_C1 0xECFF
#define B_AX_CSI_ON_TIMEOUT BIT(5)
#define B_AX_STS_ON_TIMEOUT BIT(4)
#define B_AX_DATA_ON_TIMEOUT BIT(3)
#define B_AX_OFDM_CCA_TIMEOUT BIT(2)
#define B_AX_CCK_CCA_TIMEOUT BIT(1)
#define B_AXC_PHY_TXON_TIMEOUT BIT(0)
#define R_AX_BFMER_ASSOCIATED_SU0 0xCD00
#define R_AX_BFMER_ASSOCIATED_SU0_C1 0xED00
#define B_AX_MER_IGNORE_SU_BFMEE1_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE1_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE1_EN BIT(24)
#define B_AX_MER_SU_BFMEE1_MACID_SH 16
#define B_AX_MER_SU_BFMEE1_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE0_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE0_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE0_EN BIT(8)
#define B_AX_MER_SU_BFMEE0_MACID_SH 0
#define B_AX_MER_SU_BFMEE0_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU2 0xCD04
#define R_AX_BFMER_ASSOCIATED_SU2_C1 0xED04
#define B_AX_MER_IGNORE_SU_BFMEE3_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE3_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE3_EN BIT(24)
#define B_AX_MER_SU_BFMEE3_MACID_SH 16
#define B_AX_MER_SU_BFMEE3_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE2_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE2_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE2_EN BIT(8)
#define B_AX_MER_SU_BFMEE2_MACID_SH 0
#define B_AX_MER_SU_BFMEE2_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU4 0xCD08
#define R_AX_BFMER_ASSOCIATED_SU4_C1 0xED08
#define B_AX_MER_IGNORE_SU_BFMEE5_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE5_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE5_EN BIT(24)
#define B_AX_MER_SU_BFMEE5_MACID_SH 16
#define B_AX_MER_SU_BFMEE5_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE4_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE4_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE4_EN BIT(8)
#define B_AX_MER_SU_BFMEE4_MACID_SH 0
#define B_AX_MER_SU_BFMEE4_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU6 0xCD0C
#define R_AX_BFMER_ASSOCIATED_SU6_C1 0xED0C
#define B_AX_MER_IGNORE_SU_BFMEE7_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE7_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE7_EN BIT(24)
#define B_AX_MER_SU_BFMEE7_MACID_SH 16
#define B_AX_MER_SU_BFMEE7_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE6_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE6_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE6_EN BIT(8)
#define B_AX_MER_SU_BFMEE6_MACID_SH 0
#define B_AX_MER_SU_BFMEE6_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU8 0xCD10
#define R_AX_BFMER_ASSOCIATED_SU8_C1 0xED10
#define B_AX_MER_IGNORE_SU_BFMEE9_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE9_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE9_EN BIT(24)
#define B_AX_MER_SU_BFMEE9_MACID_SH 16
#define B_AX_MER_SU_BFMEE9_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE8_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE8_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE8_EN BIT(8)
#define B_AX_MER_SU_BFMEE8_MACID_SH 0
#define B_AX_MER_SU_BFMEE8_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU10 0xCD14
#define R_AX_BFMER_ASSOCIATED_SU10_C1 0xED14
#define B_AX_MER_IGNORE_SU_BFMEE11_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE11_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE11_EN BIT(24)
#define B_AX_MER_SU_BFMEE11_MACID_SH 16
#define B_AX_MER_SU_BFMEE11_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE10_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE10_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE10_EN BIT(8)
#define B_AX_MER_SU_BFMEE10_MACID_SH 0
#define B_AX_MER_SU_BFMEE10_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU12 0xCD18
#define R_AX_BFMER_ASSOCIATED_SU12_C1 0xED18
#define B_AX_MER_IGNORE_SU_BFMEE13_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE13_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE13_EN BIT(24)
#define B_AX_MER_SU_BFMEE13_MACID_SH 16
#define B_AX_MER_SU_BFMEE13_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE12_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE12_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE12_EN BIT(8)
#define B_AX_MER_SU_BFMEE12_MACID_SH 0
#define B_AX_MER_SU_BFMEE12_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_SU14 0xCD1C
#define R_AX_BFMER_ASSOCIATED_SU14_C1 0xED1C
#define B_AX_MER_IGNORE_SU_BFMEE15_SND_STS BIT(26)
#define B_AX_MER_SU_BFMEE15_SND_STS BIT(25)
#define B_AX_MER_SU_BFMEE15_EN BIT(24)
#define B_AX_MER_SU_BFMEE15_MACID_SH 16
#define B_AX_MER_SU_BFMEE15_MACID_MSK 0xff
#define B_AX_MER_IGNORE_SU_BFMEE14_SND_STS BIT(10)
#define B_AX_MER_SU_BFMEE14_SND_STS BIT(9)
#define B_AX_MER_SU_BFMEE14_EN BIT(8)
#define B_AX_MER_SU_BFMEE14_MACID_SH 0
#define B_AX_MER_SU_BFMEE14_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_MU0 0xCD20
#define R_AX_BFMER_ASSOCIATED_MU0_C1 0xED20
#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE1 BIT(27)
#define B_AX_MER_IGNORE_MU_BFMEE1_SND_STS BIT(26)
#define B_AX_MER_MU_BFMEE1_SND_STS BIT(25)
#define B_AX_MER_MU_BFMEE1_EN BIT(24)
#define B_AX_MER_MU_BFMEE1_MACID_SH 16
#define B_AX_MER_MU_BFMEE1_MACID_MSK 0xff
#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE0 BIT(11)
#define B_AX_MER_IGNORE_MU_BFMEE0_SND_STS BIT(10)
#define B_AX_MER_MU_BFMEE0_SND_STS BIT(9)
#define B_AX_MER_MU_BFMEE0_EN BIT(8)
#define B_AX_MER_MU_BFMEE0_MACID_SH 0
#define B_AX_MER_MU_BFMEE0_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_MU2 0xCD24
#define R_AX_BFMER_ASSOCIATED_MU2_C1 0xED24
#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE3 BIT(27)
#define B_AX_MER_IGNORE_MU_BFMEE3_SND_STS BIT(26)
#define B_AX_MER_MU_BFMEE3_SND_STS BIT(25)
#define B_AX_MER_MU_BFMEE3_EN BIT(24)
#define B_AX_MER_MU_BFMEE3_MACID_SH 16
#define B_AX_MER_MU_BFMEE3_MACID_MSK 0xff
#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE2 BIT(11)
#define B_AX_MER_IGNORE_MU_BFMEE2_SND_STS BIT(10)
#define B_AX_MER_MU_BFMEE2_SND_STS BIT(9)
#define B_AX_MER_MU_BFMEE2_EN BIT(8)
#define B_AX_MER_MU_BFMEE2_MACID_SH 0
#define B_AX_MER_MU_BFMEE2_MACID_MSK 0xff
#define R_AX_BFMER_ASSOCIATED_MU4 0xCD28
#define R_AX_BFMER_ASSOCIATED_MU4_C1 0xED28
#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE5 BIT(27)
#define B_AX_MER_IGNORE_MU_BFMEE5_SND_STS BIT(26)
#define B_AX_MER_MU_BFMEE5_SND_STS BIT(25)
#define B_AX_MER_MU_BFMEE5_EN BIT(24)
#define B_AX_MER_MU_BFMEE5_MACID_SH 16
#define B_AX_MER_MU_BFMEE5_MACID_MSK 0xff
#define B_AX_MER_DIS_SU_TXBF_MU_BFMEE4 BIT(11)
#define B_AX_MER_IGNORE_MU_BFMEE4_SND_STS BIT(10)
#define B_AX_MER_MU_BFMEE4_SND_STS BIT(9)
#define B_AX_MER_MU_BFMEE4_EN BIT(8)
#define B_AX_MER_MU_BFMEE4_MACID_SH 0
#define B_AX_MER_MU_BFMEE4_MACID_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX0 0xCD2C
#define R_AX_BFMER_CSI_BUFF_IDX0_C1 0xED2C
#define B_AX_MER_TXBF_CSI_BUFF_IDX0_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX0_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX0_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX0_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX0_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX0_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX1 0xCD30
#define R_AX_BFMER_CSI_BUFF_IDX1_C1 0xED30
#define B_AX_MER_TXBF_CSI_BUFF_IDX1_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX1_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX1_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX1_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX1_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX1_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX2 0xCD34
#define R_AX_BFMER_CSI_BUFF_IDX2_C1 0xED34
#define B_AX_MER_TXBF_CSI_BUFF_IDX2_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX2_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX2_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX2_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX2_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX2_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX3 0xCD38
#define R_AX_BFMER_CSI_BUFF_IDX3_C1 0xED38
#define B_AX_MER_TXBF_CSI_BUFF_IDX3_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX3_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX3_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX3_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX3_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX3_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX4 0xCD3C
#define R_AX_BFMER_CSI_BUFF_IDX4_C1 0xED3C
#define B_AX_MER_TXBF_CSI_BUFF_IDX4_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX4_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX4_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX4_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX4_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX4_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX5 0xCD40
#define R_AX_BFMER_CSI_BUFF_IDX5_C1 0xED40
#define B_AX_MER_TXBF_CSI_BUFF_IDX5_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX5_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX5_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX5_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX5_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX5_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX6 0xCD44
#define R_AX_BFMER_CSI_BUFF_IDX6_C1 0xED44
#define B_AX_MER_TXBF_CSI_BUFF_IDX6_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX6_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX6_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX6_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX6_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX6_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX7 0xCD48
#define R_AX_BFMER_CSI_BUFF_IDX7_C1 0xED48
#define B_AX_MER_TXBF_CSI_BUFF_IDX7_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX7_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX7_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX7_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX7_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX7_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX8 0xCD4C
#define R_AX_BFMER_CSI_BUFF_IDX8_C1 0xED4C
#define B_AX_MER_TXBF_CSI_BUFF_IDX8_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX8_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX8_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX8_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX8_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX8_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX9 0xCD50
#define R_AX_BFMER_CSI_BUFF_IDX9_C1 0xED50
#define B_AX_MER_TXBF_CSI_BUFF_IDX9_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX9_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX9_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX9_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX9_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX9_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX10 0xCD54
#define R_AX_BFMER_CSI_BUFF_IDX10_C1 0xED54
#define B_AX_MER_TXBF_CSI_BUFF_IDX10_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX10_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX10_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX10_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX10_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX10_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX11 0xCD58
#define R_AX_BFMER_CSI_BUFF_IDX11_C1 0xED58
#define B_AX_MER_TXBF_CSI_BUFF_IDX11_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX11_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX11_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX11_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX11_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX11_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX12 0xCD5C
#define R_AX_BFMER_CSI_BUFF_IDX12_C1 0xED5C
#define B_AX_MER_TXBF_CSI_BUFF_IDX12_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX12_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX12_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX12_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX12_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX12_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX13 0xCD60
#define R_AX_BFMER_CSI_BUFF_IDX13_C1 0xED60
#define B_AX_MER_TXBF_CSI_BUFF_IDX13_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX13_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX13_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX13_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX13_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX13_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX14 0xCD64
#define R_AX_BFMER_CSI_BUFF_IDX14_C1 0xED64
#define B_AX_MER_TXBF_CSI_BUFF_IDX14_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX14_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX14_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX14_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX14_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX14_MSK 0xff
#define R_AX_BFMER_CSI_BUFF_IDX15 0xCD68
#define R_AX_BFMER_CSI_BUFF_IDX15_C1 0xED68
#define B_AX_MER_TXBF_CSI_BUFF_IDX15_SH 20
#define B_AX_MER_TXBF_CSI_BUFF_IDX15_MSK 0xfff
#define B_AX_MER_SND_CSI_BUFF_IDX15_SH 8
#define B_AX_MER_SND_CSI_BUFF_IDX15_MSK 0xfff
#define B_AX_MER_CSI_BUFF_MACID_IDX15_SH 0
#define B_AX_MER_CSI_BUFF_MACID_IDX15_MSK 0xff
#define R_AX_BFMER_SND_DEBUG_CNT 0xCD6C
#define R_AX_BFMER_SND_DEBUG_CNT_C1 0xED6C
#define B_AX_SND_DNGCNT_RST BIT(20)
#define B_AX_MER_SND_DNGCNT_SH 0
#define B_AX_MER_SND_DNGCNT_MSK 0xffff
#define R_AX_BFMER_UPD_MEE_PARA 0xCD70
#define R_AX_BFMER_UPD_MEE_PARA_C1 0xED70
#define B_AX_MER_UPDMEE_OPTION BIT(31)
#define B_AX_MER_UPDMEE_USERID_SH 16
#define B_AX_MER_UPDMEE_USERID_MSK 0xf
#define B_AX_MER_UPDMEE_FT_SH 12
#define B_AX_MER_UPDMEE_FT_MSK 0x3
#define B_AX_MER_UPDMEE_BW_SH 10
#define B_AX_MER_UPDMEE_BW_MSK 0x3
#define B_AX_MER_UPDMEE_CB_SH 8
#define B_AX_MER_UPDMEE_CB_MSK 0x3
#define B_AX_MER_UPDMEE_NG_SH 6
#define B_AX_MER_UPDMEE_NG_MSK 0x3
#define B_AX_MER_UPDMEE_NR_SH 3
#define B_AX_MER_UPDMEE_NR_MSK 0x7
#define B_AX_MER_UPDMEE_NC_SH 0
#define B_AX_MER_UPDMEE_NC_MSK 0x7
#define R_AX_BFMER_RO_MEE_PARA 0xCD74
#define R_AX_BFMER_RO_MEE_PARA_C1 0xED74
#define B_AX_BFMER_RO_MEE_PARA_FT_SH 12
#define B_AX_BFMER_RO_MEE_PARA_FT_MSK 0x3
#define B_AX_BFMER_RO_MEE_PARA_BW_SH 10
#define B_AX_BFMER_RO_MEE_PARA_BW_MSK 0x3
#define B_AX_BFMER_RO_MEE_PARA_CB_SH 8
#define B_AX_BFMER_RO_MEE_PARA_CB_MSK 0x3
#define B_AX_BFMER_RO_MEE_PARA_NG_SH 6
#define B_AX_BFMER_RO_MEE_PARA_NG_MSK 0x3
#define B_AX_BFMER_RO_MEE_PARA_NR_SH 3
#define B_AX_BFMER_RO_MEE_PARA_NR_MSK 0x7
#define B_AX_BFMER_RO_MEE_PARA_NC_SH 0
#define B_AX_BFMER_RO_MEE_PARA_NC_MSK 0x7
#define R_AX_BFMER_CTRL_0 0xCD78
#define R_AX_BFMER_CTRL_0_C1 0xED78
#define B_AX_BFMER_HE_CSI_OFFSET_SH 24
#define B_AX_BFMER_HE_CSI_OFFSET_MSK 0xff
#define B_AX_BFMER_VHT_CSI_OFFSET_SH 16
#define B_AX_BFMER_VHT_CSI_OFFSET_MSK 0xff
#define B_AX_BFMER_HT_CSI_OFFSET_SH 8
#define B_AX_BFMER_HT_CSI_OFFSET_MSK 0xff
#define B_AX_BFMER_NDP_BFEN BIT(2)
#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0)
#define R_AX_BFMER_CTRL_1 0xCD7C
#define R_AX_BFMER_CTRL_1_C1 0xED7C
#define B_AX_BFMER_CTRLINFO_MACID_SH 0
#define B_AX_BFMER_CTRLINFO_MACID_MSK 0xff
#define R_AX_BFMEE_RESP_OPTION 0xCD80
#define R_AX_BFMEE_RESP_OPTION_C1 0xED80
#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_SH 24
#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MSK 0xff
#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_SH 20
#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MSK 0xf
#define B_AX_MU_BFRPTSEG_SEL_SH 17
#define B_AX_MU_BFRPTSEG_SEL_MSK 0x3
#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16)
#define R_AX_BFMEE_OPTION 0xCD84
#define R_AX_BFMEE_OPTION_C1 0xED84
#define B_AX_BFMEE_MU_BFEE_DIS BIT(7)
#define B_AX_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6)
#define B_AX_BFMEE_NOCHK_BFPOLL_BMP BIT(5)
#define B_AX_BFMEE_HE_NDPA_EN BIT(2)
#define B_AX_BFMEE_VHT_NDPA_EN BIT(1)
#define B_AX_BFMEE_HT_NDPA_EN BIT(0)
#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88
#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88
#define B_AX_BFMEE_CSISEQ_SEL BIT(29)
#define B_AX_BFMEE_BFPARAM_SEL BIT(28)
#define B_AX_BFMEE_OFDM_LEN_TH_SH 24
#define B_AX_BFMEE_OFDM_LEN_TH_MSK 0xf
#define B_AX_BFMEE_BF_PORT_SEL BIT(23)
#define B_AX_BFMEE_USE_NSTS BIT(22)
#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21)
#define B_AX_BFMEE_CSI_GID_SEL BIT(20)
#define B_AX_BFMEE_CSI_RSC_SH 18
#define B_AX_BFMEE_CSI_RSC_MSK 0x3
#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17)
#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16)
#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15)
#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14)
#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13)
#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12)
#define B_AX_BFMEE_CSIINFO0_CS_SH 10
#define B_AX_BFMEE_CSIINFO0_CS_MSK 0x3
#define B_AX_BFMEE_CSIINFO0_CB_SH 8
#define B_AX_BFMEE_CSIINFO0_CB_MSK 0x3
#define B_AX_BFMEE_CSIINFO0_NG_SH 6
#define B_AX_BFMEE_CSIINFO0_NG_MSK 0x3
#define B_AX_BFMEE_CSIINFO0_NR_SH 3
#define B_AX_BFMEE_CSIINFO0_NR_MSK 0x7
#define B_AX_BFMEE_CSIINFO0_NC_SH 0
#define B_AX_BFMEE_CSIINFO0_NC_MSK 0x7
#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C
#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C
#define B_AX_BFMEE_CSI_RRSC_BMAP_SH 0
#define B_AX_BFMEE_CSI_RRSC_BMAP_MSK 0xffffffffL
#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90
#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90
#define B_AX_BFMEE_HE_CSI_RATE_SH 16
#define B_AX_BFMEE_HE_CSI_RATE_MSK 0x7f
#define B_AX_BFMEE_VHT_CSI_RATE_SH 8
#define B_AX_BFMEE_VHT_CSI_RATE_MSK 0x7f
#define B_AX_BFMEE_HT_CSI_RATE_SH 0
#define B_AX_BFMEE_HT_CSI_RATE_MSK 0x7f
#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94
#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94
#define B_AX_BFMEE_CSIINFO1_BF_EN BIT(14)
#define B_AX_BFMEE_CSIINFO1_STBC_EN BIT(13)
#define B_AX_BFMEE_CSIINFO1_LDPC_EN BIT(12)
#define B_AX_BFMEE_CSIINFO1_CS_SH 10
#define B_AX_BFMEE_CSIINFO1_CS_MSK 0x3
#define B_AX_BFMEE_CSIINFO1_CB_SH 8
#define B_AX_BFMEE_CSIINFO1_CB_MSK 0x3
#define B_AX_BFMEE_CSIINFO1_NG_SH 6
#define B_AX_BFMEE_CSIINFO1_NG_MSK 0x3
#define B_AX_BFMEE_CSIINFO1_NR_SH 3
#define B_AX_BFMEE_CSIINFO1_NR_MSK 0x7
#define B_AX_BFMEE_CSIINFO1_NC_SH 0
#define B_AX_BFMEE_CSIINFO1_NC_MSK 0x7
//
// RMAC
//
#define R_AX_RCR 0xCE00
#define R_AX_RCR_C1 0xEE00
#define B_AX_STOP_RX_IN BIT(11)
#define B_AX_DRV_INFO_SIZE_SH 8
#define B_AX_DRV_INFO_SIZE_MSK 0x7
#define B_AX_CH_EN_SH 0
#define B_AX_CH_EN_MSK 0xf
#define R_AX_DLK_PROTECT_CTL 0xCE02
#define R_AX_DLK_PROTECT_CTL_C1 0xEE02
#define B_AX_RX_DLK_CCA_TIME_SH 8
#define B_AX_RX_DLK_CCA_TIME_MSK 0xff
#define B_AX_RX_DLK_DATA_TIME_SH 4
#define B_AX_RX_DLK_DATA_TIME_MSK 0xf
#define B_AX_RX_DLK_RST_EN BIT(1)
#define B_AX_RX_DLK_INT_EN BIT(0)
#define R_AX_PLCP_HDR_FLTR 0xCE04
#define R_AX_PLCP_HDR_FLTR_C1 0xEE04
#define B_AX_DIS_CHK_MIN_LEN BIT(8)
#define B_AX_HE_SIGB_CRC_CHK BIT(6)
#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5)
#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4)
#define B_AX_SIGA_CRC_CHK BIT(3)
#define B_AX_LSIG_PARITY_CHK BIT(2)
#define B_AX_CCK_SIG_CHK BIT(1)
#define B_AX_CCK_CRC_CHK BIT(0)
#define R_AX_RXGCK_CTRL 0xCE06
#define R_AX_RXGCK_CTRL_C1 0xEE06
#define B_AX_RXGCK_GCK_RATE_LIMIT_SH 8
#define B_AX_RXGCK_GCK_RATE_LIMIT_MSK 0x3
#define B_AX_RXGCK_ENTRY_DELAY_SH 4
#define B_AX_RXGCK_ENTRY_DELAY_MSK 0x7
#define B_AX_RXGCK_GCK_CYCLE_SH 2
#define B_AX_RXGCK_GCK_CYCLE_MSK 0x3
#define B_AX_RXGCK_CCA_EN BIT(1)
#define B_AX_DISGCLK BIT(0)
#define R_AX_RXPSF_CTRL 0xCE08
#define R_AX_RXPSF_CTRL_C1 0xEE08
#define B_AX_RXPSF_PKTLENTHR_SH 16
#define B_AX_RXPSF_PKTLENTHR_MSK 0x7
#define B_AX_RXPSF_ERRTHR_SH 12
#define B_AX_RXPSF_ERRTHR_MSK 0x7
#define B_AX_INVALID_WIDTH_SH 8
#define B_AX_INVALID_WIDTH_MSK 0x3
#define B_AX_RXPSF_PLCP_CHKEN BIT(4)
#define B_AX_RXPSF_BSS_CHKEN BIT(3)
#define B_AX_RXPSF_MHCHKEN BIT(2)
#define B_AX_RXPSF_CONT_ERRCHKEN BIT(1)
#define R_AX_RXPSF_MGT_TYPE 0xCE0E
#define R_AX_RXPSF_MGT_TYPE_C1 0xEE0E
#define B_AX_RXPSF_MGT15_PRSV BIT(15)
#define B_AX_RXPSF_MGT14_PRSV BIT(14)
#define B_AX_RXPSF_MGT13_PRSV BIT(13)
#define B_AX_RXPSF_MGT12_PRSV BIT(12)
#define B_AX_RXPSF_MGT11_PRSV BIT(11)
#define B_AX_RXPSF_MGT10_PRSV BIT(10)
#define B_AX_RXPSF_MGT9_PRSV BIT(9)
#define B_AX_RXPSF_MGT8_PRSV BIT(8)
#define B_AX_RXPSF_MGT7_PRSV BIT(7)
#define B_AX_RXPSF_MGT6_PRSV BIT(6)
#define B_AX_RXPSF_MGT5_PRSV BIT(5)
#define B_AX_RXPSF_MGT4_PRSV BIT(4)
#define B_AX_RXPSF_MGT3_PRSV BIT(3)
#define B_AX_RXPSF_MGT2_PRSV BIT(2)
#define B_AX_RXPSF_MGT1_PRSV BIT(1)
#define B_AX_RXPSF_MGT0_PRSV BIT(0)
#define R_AX_RXPSF_DATA_TYPE 0xCE0C
#define R_AX_RXPSF_DATA_TYPE_C1 0xEE0C
#define B_AX_RXPSF_DATA15_PRSV BIT(15)
#define B_AX_RXPSF_DATA14_PRSV BIT(14)
#define B_AX_RXPSF_DATA13_PRSV BIT(13)
#define B_AX_RXPSF_DATA12_PRSV BIT(12)
#define B_AX_RXPSF_DATA11_PRSV BIT(11)
#define B_AX_RXPSF_DATA10_PRSV BIT(10)
#define B_AX_RXPSF_DATA9_PRSV BIT(9)
#define B_AX_RXPSF_DATA8_PRSV BIT(8)
#define B_AX_RXPSF_DATA7_PRSV BIT(7)
#define B_AX_RXPSF_DATA6_PRSV BIT(6)
#define B_AX_RXPSF_DATA5_PRSV BIT(5)
#define B_AX_RXPSF_DATA4_PRSV BIT(4)
#define B_AX_RXPSF_DATA3_PRSV BIT(3)
#define B_AX_RXPSF_DATA2_PRSV BIT(2)
#define B_AX_RXPSF_DATA1_PRSV BIT(1)
#define B_AX_RXPSF_DATA_PRSV BIT(0)
#define R_AX_RXPSF_CTRL_TYPE 0xCE10
#define R_AX_RXPSF_CTRL_TYPE_C1 0xEE10
#define B_AX_RXPSF_CTRL_PRSV BIT(0)
#define R_AX_RXPSF_RATE 0xCE12
#define R_AX_RXPSF_RATE_C1 0xEE12
#define B_AX_RXPSF_HETB_PRSV BIT(8)
#define B_AX_RXPSF_HEMU_PRSV BIT(7)
#define B_AX_RXPSF_HEERSU_PRSV BIT(6)
#define B_AX_RXPSF_HESU_PRSV BIT(5)
#define B_AX_RXPSF_VHTMU_PRSV BIT(4)
#define B_AX_RXPSF_VHTSU_PRSV BIT(3)
#define B_AX_RXPSF_HT_PRSV BIT(2)
#define B_AX_RXPSF_OFDM_PRSV BIT(1)
#define B_AX_RXPSF_CCK_PRSV BIT(0)
#define R_AX_RXAI_CTRL 0xCE14
#define R_AX_RXAI_CTRL_C1 0xEE14
#define B_AX_RXAI_INFO_RST BIT(7)
#define B_AX_RXAI_PRTCT_REL BIT(6)
#define B_AX_RXAI_PRTCT_VIO BIT(5)
#define B_AX_RXAI_PRTCT_SEL BIT(1)
#define B_AX_RXAI_PRTCT_EN BIT(0)
#define R_AX_RX_FIFO_CTRL 0xCE1C
#define R_AX_RX_FIFO_CTRL_C1 0xEE1C
#define B_AX_RXD_FIFO_MAX_LEV_CLR BIT(23)
#define B_AX_RXD_FIFO_MAX_LEV_SH 8
#define B_AX_RXD_FIFO_MAX_LEV_MSK 0xff
#define B_AX_RXD_FIFO_FULL_TH_SH 0
#define B_AX_RXD_FIFO_FULL_TH_MSK 0xff
#define R_AX_RX_FLTR_OPT 0xCE20
#define R_AX_RX_FLTR_OPT_C1 0xEE20
#define B_AX_UID_FILTER_SH 24
#define B_AX_UID_FILTER_MSK 0xff
#define B_AX_UNSPT_FILTER_SH 22
#define B_AX_UNSPT_FILTER_MSK 0x3
#define B_AX_RX_MPDU_MAX_LEN_SH 16
#define B_AX_RX_MPDU_MAX_LEN_MSK 0x3f
#define B_AX_A_FTM_REQ BIT(14)
#define B_AX_A_ERR_PKT BIT(13)
#define B_AX_A_UNSUP_PKT BIT(12)
#define B_AX_A_CRC32_ERR BIT(11)
#define B_AX_A_PWR_MGNT BIT(10)
#define B_AX_A_BCN_CHK_RULE_SH 8
#define B_AX_A_BCN_CHK_RULE_MSK 0x3
#define B_AX_A_BCN_CHK_EN BIT(7)
#define B_AX_A_MC_LIST_CAM_MATCH BIT(6)
#define B_AX_A_BC_CAM_MATCH BIT(5)
#define B_AX_A_UC_CAM_MATCH BIT(4)
#define B_AX_A_MC BIT(3)
#define B_AX_A_BC BIT(2)
#define B_AX_A_A1_MATCH BIT(1)
#define B_AX_SNIFFER_MODE BIT(0)
#define R_AX_CTRL_FLTR 0xCE24
#define R_AX_CTRL_FLTR_C1 0xEE24
#define B_AX_A_CTRL15_SH 30
#define B_AX_A_CTRL15_MSK 0x3
#define B_AX_A_CTRL14_SH 28
#define B_AX_A_CTRL14_MSK 0x3
#define B_AX_A_CTRL13_SH 26
#define B_AX_A_CTRL13_MSK 0x3
#define B_AX_A_CTRL12_SH 24
#define B_AX_A_CTRL12_MSK 0x3
#define B_AX_A_CTRL11_SH 22
#define B_AX_A_CTRL11_MSK 0x3
#define B_AX_A_CTRL10_SH 20
#define B_AX_A_CTRL10_MSK 0x3
#define B_AX_A_CTRL9_SH 18
#define B_AX_A_CTRL9_MSK 0x3
#define B_AX_A_CTRL8_SH 16
#define B_AX_A_CTRL8_MSK 0x3
#define B_AX_A_CTRL7_SH 14
#define B_AX_A_CTRL7_MSK 0x3
#define B_AX_A_CTRL6_SH 12
#define B_AX_A_CTRL6_MSK 0x3
#define B_AX_A_CTRL5_SH 10
#define B_AX_A_CTRL5_MSK 0x3
#define B_AX_A_CTRL4_SH 8
#define B_AX_A_CTRL4_MSK 0x3
#define B_AX_A_CTRL3_SH 6
#define B_AX_A_CTRL3_MSK 0x3
#define B_AX_A_CTRL2_SH 4
#define B_AX_A_CTRL2_MSK 0x3
#define B_AX_A_CTRL1_SH 2
#define B_AX_A_CTRL1_MSK 0x3
#define B_AX_A_CTRL0_SH 0
#define B_AX_A_CTRL0_MSK 0x3
#define R_AX_MGNT_FLTR 0xCE28
#define R_AX_MGNT_FLTR_C1 0xEE28
#define B_AX_A_MGNT15_SH 30
#define B_AX_A_MGNT15_MSK 0x3
#define B_AX_A_MGNT14_SH 28
#define B_AX_A_MGNT14_MSK 0x3
#define B_AX_A_MGNT13_SH 26
#define B_AX_A_MGNT13_MSK 0x3
#define B_AX_A_MGNT12_SH 24
#define B_AX_A_MGNT12_MSK 0x3
#define B_AX_A_MGNT11_SH 22
#define B_AX_A_MGNT11_MSK 0x3
#define B_AX_A_MGNT10_SH 20
#define B_AX_A_MGNT10_MSK 0x3
#define B_AX_A_MGNT9_SH 18
#define B_AX_A_MGNT9_MSK 0x3
#define B_AX_A_MGNT8_SH 16
#define B_AX_A_MGNT8_MSK 0x3
#define B_AX_A_MGNT7_SH 14
#define B_AX_A_MGNT7_MSK 0x3
#define B_AX_A_MGNT6_SH 12
#define B_AX_A_MGNT6_MSK 0x3
#define B_AX_A_MGNT5_SH 10
#define B_AX_A_MGNT5_MSK 0x3
#define B_AX_A_MGNT4_SH 8
#define B_AX_A_MGNT4_MSK 0x3
#define B_AX_A_MGNT3_SH 6
#define B_AX_A_MGNT3_MSK 0x3
#define B_AX_A_MGNT2_SH 4
#define B_AX_A_MGNT2_MSK 0x3
#define B_AX_A_MGNT1_SH 2
#define B_AX_A_MGNT1_MSK 0x3
#define B_AX_A_MGNT0_SH 0
#define B_AX_A_MGNT0_MSK 0x3
#define R_AX_DATA_FLTR 0xCE2C
#define R_AX_DATA_FLTR_C1 0xEE2C
#define B_AX_A_DATA15_SH 30
#define B_AX_A_DATA15_MSK 0x3
#define B_AX_A_DATA14_SH 28
#define B_AX_A_DATA14_MSK 0x3
#define B_AX_A_DATA13_SH 26
#define B_AX_A_DATA13_MSK 0x3
#define B_AX_A_DATA12_SH 24
#define B_AX_A_DATA12_MSK 0x3
#define B_AX_A_DATA11_SH 22
#define B_AX_A_DATA11_MSK 0x3
#define B_AX_A_DATA10_SH 20
#define B_AX_A_DATA10_MSK 0x3
#define B_AX_A_DATA9_SH 18
#define B_AX_A_DATA9_MSK 0x3
#define B_AX_A_DATA8_SH 16
#define B_AX_A_DATA8_MSK 0x3
#define B_AX_A_DATA7_SH 14
#define B_AX_A_DATA7_MSK 0x3
#define B_AX_A_DATA6_SH 12
#define B_AX_A_DATA6_MSK 0x3
#define B_AX_A_DATA5_SH 10
#define B_AX_A_DATA5_MSK 0x3
#define B_AX_A_DATA4_SH 8
#define B_AX_A_DATA4_MSK 0x3
#define B_AX_A_DATA3_SH 6
#define B_AX_A_DATA3_MSK 0x3
#define B_AX_A_DATA2_SH 4
#define B_AX_A_DATA2_MSK 0x3
#define B_AX_A_DATA1_SH 2
#define B_AX_A_DATA1_MSK 0x3
#define B_AX_A_DATA0_SH 0
#define B_AX_A_DATA0_MSK 0x3
#define R_AX_ZLENDEL_COUNT 0xCE30
#define R_AX_ZLENDEL_COUNT_C1 0xEE30
#define B_AX_RXD_DELI_NUM_SH 8
#define B_AX_RXD_DELI_NUM_MSK 0xff
#define B_AX_RXD_DELI_NUM_SEL_SH 4
#define B_AX_RXD_DELI_NUM_SEL_MSK 0xf
#define B_AX_RXD_DELI_UNIT_SH 1
#define B_AX_RXD_DELI_UNIT_MSK 0x3
#define B_AX_RXD_DELI_EN BIT(0)
#define R_AX_ADDR_CAM_CTRL 0xCE34
#define R_AX_ADDR_CAM_CTRL_C1 0xEE34
#define B_AX_ADDR_CAM_RANGE_SH 16
#define B_AX_ADDR_CAM_RANGE_MSK 0xff
#define B_AX_ADDR_CAM_CMPLIMT_SH 12
#define B_AX_ADDR_CAM_CMPLIMT_MSK 0xf
#define B_AX_ADDR_CAM_CLR BIT(8)
#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2)
#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1)
#define B_AX_ADDR_CAM_EN BIT(0)
#define R_AX_ADDR_CAM_DIS_INFO 0xCE38
#define R_AX_ADDR_CAM_DIS_INFO_C1 0xEE38
#define B_AX_ADDR_CAM_DIS_MACID_SH 24
#define B_AX_ADDR_CAM_DIS_MACID_MSK 0xff
#define B_AX_ADDR_CAM_DIS_SEC_IDX_SH 16
#define B_AX_ADDR_CAM_DIS_SEC_IDX_MSK 0xff
#define B_AX_ADDR_CAM_DIS_PORT_SH 12
#define B_AX_ADDR_CAM_DIS_PORT_MSK 0x7
#define B_AX_ADDR_CAM_DIS_A3_HIT BIT(11)
#define B_AX_ADDR_CAM_DIS_A2_HIT BIT(10)
#define B_AX_ADDR_CAM_DIS_A1_HIT BIT(9)
#define B_AX_ADDR_CAM_DIS_CAM_HIT BIT(8)
#define B_AX_ADDR_CAM_DIS_IDX_SH 0
#define B_AX_ADDR_CAM_DIS_IDX_MSK 0xff
#define R_AX_RESPBA_CAM_CTRL 0xCE3C
#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
#define B_AX_DEST_ENTRY_IDX_SH 12
#define B_AX_DEST_ENTRY_IDX_MSK 0xf
#define B_AX_SRC_ENTRY_IDX_SH 8
#define B_AX_SRC_ENTRY_IDX_MSK 0xf
#define B_AX_BACAM_SHIFT_POLL BIT(7)
#define B_AX_BACAM_ENT_CFG BIT(4)
#define B_AX_COMPL_VAL BIT(3)
#define B_AX_SSN_SEL BIT(2)
#define B_AX_BACAM_RST_SH 0
#define B_AX_BACAM_RST_MSK 0x3
#define R_AX_PPDU_STAT 0xCE40
#define R_AX_PPDU_STAT_C1 0xEE40
#define B_AX_PPDU_STAT_RPT_TRIG BIT(8)
#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5)
#define B_AX_PPDU_STAT_RPT_A1M BIT(4)
#define B_AX_APP_PLCP_HDR_RPT BIT(3)
#define B_AX_APP_RX_CNT_RPT BIT(2)
#define B_AX_APP_MAC_INFO_RPT BIT(1)
#define B_AX_PPDU_STAT_RPT_EN BIT(0)
#define R_AX_PPDU_STAT_ERR 0xCE42
#define R_AX_PPDU_STAT_ERR_C1 0xEE42
#define B_AX_PPDU_STAT_ERR_3_CLR BIT(6)
#define B_AX_PPDU_STAT_ERR_2_CLR BIT(5)
#define B_AX_PPDU_STAT_ERR_1_CLR BIT(4)
#define B_AX_PPDU_STAT_ERR_3 BIT(2)
#define B_AX_PPDU_STAT_ERR_2 BIT(1)
#define B_AX_PPDU_STAT_ERR_1 BIT(0)
#define R_AX_CH_INFO_QRY 0xCE44
#define R_AX_CH_INFO_QRY_C1 0xEE44
#define B_AX_CH_INFO_TIME_SH 24
#define B_AX_CH_INFO_TIME_MSK 0xff
#define B_AX_CH_INFO_CNT_SH 21
#define B_AX_CH_INFO_CNT_MSK 0x7
#define B_AX_CH_INFO_REQUSTING BIT(20)
#define B_AX_CH_INFO_MGNT_FRM BIT(19)
#define B_AX_CH_INFO_CTRL_FRM BIT(18)
#define B_AX_CH_INFO_DATA_FRM BIT(17)
#define B_AX_CH_INFO_CRC_FAIL BIT(16)
#define B_AX_CH_INFO_MACID_SH 8
#define B_AX_CH_INFO_MACID_MSK 0xff
#define B_AX_CH_INFO_MODE_SH 1
#define B_AX_CH_INFO_MODE_MSK 0x7
#define B_AX_GET_CH_INFO_EN BIT(0)
#define R_AX_MACID_MATCH 0xCE48
#define R_AX_MACID_MATCH_C1 0xEE48
#define B_AX_MACID_MATCH_SH 8
#define B_AX_MACID_MATCH_MSK 0xff
#define B_AX_MACID_MATCH_MODE BIT(1)
#define B_AX_MACID_MATCH_EN BIT(0)
#define R_AX_RX_SR_CTRL 0xCE4A
#define R_AX_RX_SR_CTRL_C1 0xEE4A
#define B_AX_SR_OP_MODE_SH 4
#define B_AX_SR_OP_MODE_MSK 0x3
#define B_AX_SRG_CHK_EN BIT(2)
#define B_AX_SR_CTRL_PLCP_EN BIT(1)
#define B_AX_SR_EN BIT(0)
#define R_AX_BSSID_SRC_CTRL 0xCE4B
#define R_AX_BSSID_SRC_CTRL_C1 0xEE4B
#define B_AX_BSSID_MATCH BIT(3)
#define B_AX_PARTIAL_AID_MATCH BIT(2)
#define B_AX_BSSCOLOR_MATCH BIT(1)
#define B_AX_PLCP_SRC_EN BIT(0)
#define R_AX_SR_OBSS_PD 0xCE4C
#define R_AX_SR_OBSS_PD_C1 0xEE4C
#define B_AX_SRG_OBSS_PD_MAX_SH 24
#define B_AX_SRG_OBSS_PD_MAX_MSK 0xff
#define B_AX_SRG_OBSS_PD_MIN_SH 16
#define B_AX_SRG_OBSS_PD_MIN_MSK 0xff
#define B_AX_NONSRG_OBSS_PD_MAX_SH 8
#define B_AX_NONSRG_OBSS_PD_MAX_MSK 0xff
#define B_AX_NONSRG_OBSS_PD_MIN_SH 0
#define B_AX_NONSRG_OBSS_PD_MIN_MSK 0xff
#define R_AX_SR_BSSCOLOR_BITMAP 0xCE50
#define R_AX_SR_BSSCOLOR_BITMAP_C1 0xEE50
#define B_AX_BSSCOLOR_BITMAP_SH 0
#define B_AX_BSSCOLOR_BITMAP_MSK 0xffffffffffffffffL
#define R_AX_SR_PARTIAL_BSSCOLOR_BITMAP 0xCE58
#define R_AX_SR_PARTIAL_BSSCOLOR_BITMAP_C1 0xEE58
#define B_AX_PARTIAL_BSSID_BITMAP_SH 0
#define B_AX_PARTIAL_BSSID_BITMAP_MSK 0xffffffffffffffffL
#define R_AX_SEGMENT_CTRL 0xCE60
#define R_AX_SEGMENT_CTRL_C1 0xEE60
#define B_AX_SEG_LENGTH_SH 4
#define B_AX_SEG_LENGTH_MSK 0xf
#define B_AX_SEG_APP_ZERO BIT(1)
#define B_AX_SEG_EN BIT(0)
#define B_AX_CSIRPT_CHKSUM_ERROR BIT(31)
#define B_AX_CSIRPT_BBLEN_LT_MAC BIT(30)
#define B_AX_CSIRPT_BBLEN_GT_MAC BIT(29)
#define B_AX_CSIRPT_FIFO_RESUME_THR_SH 16
#define B_AX_CSIRPT_FIFO_RESUME_THR_MSK 0xff
#define B_AX_CSIRPT_FIFO_PAUSE_THR_SH 8
#define B_AX_CSIRPT_FIFO_PAUSE_THR_MSK 0xff
#define B_AX_CSIRPT_CHECKSUM_DIS BIT(2)
#define B_AX_CSIRPT_EMPTY_APPZERO BIT(1)
#define B_AX_CSIRPT_NDPPLCP_CHK_EN BIT(0)
#define B_AX_QSIZE_UPD BIT(0)
#define R_AX_BCN_PSR_CTRL 0xCE80
#define R_AX_BCN_PSR_CTRL_C1 0xEE80
#define B_AX_BCN_HIT_INT_PORT_SH 4
#define B_AX_BCN_HIT_INT_PORT_MSK 0xf
#define B_AX_BCAID_HIT_INT_EN BIT(3)
#define B_AX_UNIAID_HIT_INT_EN BIT(2)
#define B_AX_IE_HIT_INT_EN BIT(1)
#define B_AX_TIM_PARSER_EN BIT(0)
#define R_AX_BCN_IECAM_CTRL 0xCE82
#define R_AX_BCN_IECAM_CTRL_C1 0xEE82
#define B_AX_BCN_PSR_BUSY BIT(15)
#define B_AX_BCN_IECAM_IORST BIT(14)
#define B_AX_BCN_IE_NOHIT_FRWD_SH 10
#define B_AX_BCN_IE_NOHIT_FRWD_MSK 0x3
#define B_AX_BCN_IE_HIT_FRWD_SH 8
#define B_AX_BCN_IE_HIT_FRWD_MSK 0x3
#define B_AX_BCN_IECAM_PORT_SH 4
#define B_AX_BCN_IECAM_PORT_MSK 0xf
#define B_AX_BCN_IECAM_CLR BIT(3)
#define B_AX_BCN_IE_NOHIT_FRWD_EN BIT(2)
#define B_AX_BCN_IE_HIT_FRWD_EN BIT(1)
#define B_AX_BCN_IECAM_EN BIT(0)
#define R_AX_BCN_PSR_RPT_P0 0xCE84
#define R_AX_BCN_PSR_RPT_P0_C1 0xEE84
#define B_AX_DTIM_CNT_P0_SH 24
#define B_AX_DTIM_CNT_P0_MSK 0xff
#define B_AX_DTIM_PERIOD_P0_SH 16
#define B_AX_DTIM_PERIOD_P0_MSK 0xff
#define B_AX_BCAID_HIT_P0 BIT(15)
#define B_AX_UNIAID_HIT_P0 BIT(14)
#define B_AX_IE_HIT_P0 BIT(13)
#define B_AX_TIM_ILEGAL_P0 BIT(12)
#define B_AX_RPT_VALID_P0 BIT(11)
#define B_AX_BCAID_P0_SH 0
#define B_AX_BCAID_P0_MSK 0x7ff
#define R_AX_BCN_PSR_RPT_P1 0xCE88
#define R_AX_BCN_PSR_RPT_P1_C1 0xEE88
#define B_AX_DTIM_CNT_P1_SH 24
#define B_AX_DTIM_CNT_P1_MSK 0xff
#define B_AX_DTIM_PERIOD_P1_SH 16
#define B_AX_DTIM_PERIOD_P1_MSK 0xff
#define B_AX_BCAID_HIT_P1 BIT(15)
#define B_AX_UNIAID_HIT_P1 BIT(14)
#define B_AX_IE_HIT_P1 BIT(13)
#define B_AX_TIM_ILEGAL_P1 BIT(12)
#define B_AX_RPT_VALID_P1 BIT(11)
#define B_AX_BCAID_P1_SH 0
#define B_AX_BCAID_P1_MSK 0x7ff
#define R_AX_BCN_PSR_RPT_P2 0xCE8C
#define R_AX_BCN_PSR_RPT_P2_C1 0xEE8C
#define B_AX_DTIM_CNT_P2_SH 24
#define B_AX_DTIM_CNT_P2_MSK 0xff
#define B_AX_DTIM_PERIOD_P2_SH 16
#define B_AX_DTIM_PERIOD_P2_MSK 0xff
#define B_AX_BCAID_HIT_P2 BIT(15)
#define B_AX_UNIAID_HIT_P2 BIT(14)
#define B_AX_IE_HIT_P2 BIT(13)
#define B_AX_TIM_ILEGAL_P2 BIT(12)
#define B_AX_RPT_VALID_P2 BIT(11)
#define B_AX_BCAID_P2_SH 0
#define B_AX_BCAID_P2_MSK 0x7ff
#define R_AX_BCN_PSR_RPT_P3 0xCE90
#define R_AX_BCN_PSR_RPT_P3_C1 0xEE90
#define B_AX_DTIM_CNT_P3_SH 24
#define B_AX_DTIM_CNT_P3_MSK 0xff
#define B_AX_DTIM_PERIOD_P3_SH 16
#define B_AX_DTIM_PERIOD_P3_MSK 0xff
#define B_AX_BCAID_HIT_P3 BIT(15)
#define B_AX_UNIAID_HIT_P3 BIT(14)
#define B_AX_IE_HIT_P3 BIT(13)
#define B_AX_TIM_ILEGAL_P3 BIT(12)
#define B_AX_RPT_VALID_P3 BIT(11)
#define B_AX_BCAID_P3_SH 0
#define B_AX_BCAID_P3_MSK 0x7ff
#define R_AX_BCN_PSR_RPT_P4 0xCE94
#define R_AX_BCN_PSR_RPT_P4_C1 0xEE94
#define B_AX_DTIM_CNT_P4_SH 24
#define B_AX_DTIM_CNT_P4_MSK 0xff
#define B_AX_DTIM_PERIOD_P4_SH 16
#define B_AX_DTIM_PERIOD_P4_MSK 0xff
#define B_AX_BCAID_HIT_P4 BIT(15)
#define B_AX_UNIAID_HIT_P4 BIT(14)
#define B_AX_IE_HIT_P4 BIT(13)
#define B_AX_TIM_ILEGAL_P4 BIT(12)
#define B_AX_RPT_VALID_P4 BIT(11)
#define B_AX_BCAID_P4_SH 0
#define B_AX_BCAID_P4_MSK 0x7ff
#define R_AX_PS_RXINFO 0xCEA0
#define R_AX_PS_RXINFO_C1 0xEEA0
#define B_AX_P4_RXCTRL BIT(14)
#define B_AX_P4_RXMGT BIT(13)
#define B_AX_P4_RXDATA BIT(12)
#define B_AX_P3_RXCTRL BIT(11)
#define B_AX_P3_RXMGT BIT(10)
#define B_AX_P3_RXDATA BIT(9)
#define B_AX_P2_RXCTRL BIT(8)
#define B_AX_P2_RXMGT BIT(7)
#define B_AX_P2_RXDATA BIT(6)
#define B_AX_P1_RXCTRL BIT(5)
#define B_AX_P1_RXMGT BIT(4)
#define B_AX_P1_RXDATA BIT(3)
#define B_AX_P0_RXCTRL BIT(2)
#define B_AX_P0_RXMGT BIT(1)
#define B_AX_P0_RXDATA BIT(0)
#define R_AX_PWRINT_CTRL 0xCEAC
#define R_AX_PWRINT_CTRL_C1 0xEEAC
#define B_AX_SEQNUM_MACID_SH 16
#define B_AX_SEQNUM_MACID_MSK 0xffff
#define B_AX_REF_MACID_SH 8
#define B_AX_REF_MACID_MSK 0x7f
#define B_AX_PWRINT_EN BIT(0)
#define R_AX_SPWR0 0xCEB0
#define R_AX_SPWR0_C1 0xEEB0
#define B_AX_MID_31TO0_SH 0
#define B_AX_MID_31TO0_MSK 0xffffffffL
#define R_AX_SPWR1 0xCEB4
#define R_AX_SPWR1_C1 0xEEB4
#define B_AX_MID_63TO32_SH 0
#define B_AX_MID_63TO32_MSK 0xffffffffL
#define R_AX_SPWR2 0xCEB8
#define R_AX_SPWR2_C1 0xEEB8
#define B_AX_MID_95O64_SH 0
#define B_AX_MID_95O64_MSK 0xffffffffL
#define R_AX_SPWR3 0xCEBC
#define R_AX_SPWR3_C1 0xEEBC
#define B_AX_MID_127TO96_SH 0
#define B_AX_MID_127TO96_MSK 0xffffffffL
#define R_AX_SNIFFER_MODE_CTRL 0xCEC0
#define R_AX_SNIFFER_MODE_CTRL_C1 0xEEC0
#define B_AX_AID3_ENABLE BIT(3)
#define B_AX_AID2_ENABLE BIT(2)
#define B_AX_AID1_ENABLE BIT(1)
#define B_AX_AID0_ENABLE BIT(0)
#define R_AX_SNIFFER_MODE_AID0 0xCEC4
#define R_AX_SNIFFER_MODE_AID0_C1 0xEEC4
#define B_AX_SNIFFER_MODE_AID1_SH 16
#define B_AX_SNIFFER_MODE_AID1_MSK 0xfff
#define B_AX_SNIFFER_MODE_AID0_SH 0
#define B_AX_SNIFFER_MODE_AID0_MSK 0xfff
#define R_AX_SNIFFER_MODE_AID1 0xCEC8
#define R_AX_SNIFFER_MODE_AID1_C1 0xEEC8
#define B_AX_SNIFFER_MODE_AID3_SH 16
#define B_AX_SNIFFER_MODE_AID3_MSK 0xfff
#define B_AX_SNIFFER_MODE_AID2_SH 0
#define B_AX_SNIFFER_MODE_AID2_MSK 0xfff
#define R_AX_RX_DBG_CNT_SEL 0xCEE0
#define R_AX_RX_DBG_CNT_SEL_C1 0xEEE0
#define B_AX_RX_DBG_CNT_SH 16
#define B_AX_RX_DBG_CNT_MSK 0xffff
#define B_AX_RXERR_RPT_RST BIT(8)
#define B_AX_RX_CNT_IDX_SH 0
#define B_AX_RX_CNT_IDX_MSK 0x3f
#define R_AX_RX_DBG_CNT_UD 0xCEE4
#define R_AX_RX_DBG_CNT_UD_C1 0xEEE4
#define B_AX_UD_W1S BIT(31)
#define B_AX_UD_MSK_RUTONE BIT(30)
#define B_AX_UD_MSK_RATE BIT(29)
#define B_AX_UD_MSK_BSSID BIT(28)
#define B_AX_UD_MSK_FC BIT(27)
#define B_AX_UD_RUTONE_SH 24
#define B_AX_UD_RUTONE_MSK 0x7
#define B_AX_UD_GI_TYPE_SH 20
#define B_AX_UD_GI_TYPE_MSK 0x7
#define B_AX_UD_RATE_SH 11
#define B_AX_UD_RATE_MSK 0x1ff
#define B_AX_UD_SELECT_BSSID_SH 8
#define B_AX_UD_SELECT_BSSID_MSK 0x7
#define B_AX_UD_SUB_TYPE_SH 2
#define B_AX_UD_SUB_TYPE_MSK 0xf
#define B_AX_UD_TYPE_SH 0
#define B_AX_UD_TYPE_MSK 0x3
#define R_AX_RX_TIME_MON 0xCEEC
#define R_AX_RX_TIME_MON_C1 0xEEEC
#define B_AX_DMA_WR_TIME_SH 20
#define B_AX_DMA_WR_TIME_MSK 0xf
#define B_AX_DMA_WR_TIMEOUT_SH 16
#define B_AX_DMA_WR_TIMEOUT_MSK 0xf
#define B_AX_LATENCY_TIME_SH 8
#define B_AX_LATENCY_TIME_MSK 0xf
#define B_AX_CCA2DAT_TIME_SH 0
#define B_AX_CCA2DAT_TIME_MSK 0xff
#define R_AX_RX_STATE_MONITOR 0xCEF0
#define R_AX_RX_STATE_MONITOR_C1 0xEEF0
#define B_AX_STATE_CUR_SH 16
#define B_AX_STATE_CUR_MSK 0xffff
#define B_AX_STATE_NXT_SH 8
#define B_AX_STATE_NXT_MSK 0x3f
#define B_AX_STATE_UPD BIT(7)
#define B_AX_STATE_SEL_SH 0
#define B_AX_STATE_SEL_MSK 0x1f
#define R_AX_RMAC_ERR_ISR 0xCEF4
#define R_AX_RMAC_ERR_ISR_C1 0xEEF4
#define B_AX_RXERR_INTPS_EN BIT(31)
#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19)
#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18)
#define B_AX_RMAC_CSI_TIMEOUT_INT_EN (17)
#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16)
#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15)
#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14)
#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13)
#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12)
#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7)
#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6)
#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5)
#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4)
#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3)
#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2)
#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1)
#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0)
#define R_AX_RMAC_PLCP_MON 0xCEF8
#define R_AX_RMAC_PLCP_MON_C1 0xEEF8
#define B_AX_PCLP_MON_SEL_SH 28
#define B_AX_PCLP_MON_SEL_MSK 0xf
#define B_AX_PCLP_MON_CONT_SH 0
#define B_AX_PCLP_MON_CONT_MSK 0xfffffff
#define R_AX_RX_DEBUG_SELECT 0xCEFC
#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC
#define B_AX_DEBUG_SEL_SH 0
#define B_AX_DEBUG_SEL_MSK 0xff
//
// PWR
//
#define R_AX_PWR_RATE_CTRL 0xD200
#define R_AX_PWR_RATE_CTRL_C1 0xF200
#define B_AX_TXPWR_CTRL_CLR BIT(31)
#define B_AX_FORCE_MODE_IDX_SH 28
#define B_AX_FORCE_MODE_IDX_MSK 0x7
#define B_AX_TXAGC_OFDM_REF_SH 19
#define B_AX_TXAGC_OFDM_REF_MSK 0x1ff
#define B_AX_TXAGC_CCK_REF_SH 10
#define B_AX_TXAGC_CCK_REF_MSK 0x1ff
#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
#define B_AX_FORCE_PWR_BY_RATE_VALUE_SH 0
#define B_AX_FORCE_PWR_BY_RATE_VALUE_MSK 0x1ff
#define R_AX_PWR_RATE_OFST_CTRL 0xD204
#define R_AX_PWR_RATE_OFST_CTRL_C1 0xF204
#define B_AX_TXAGC_TBL_RD BIT(26)
#define B_AX_TXAGC_TBL_RA_SH 20
#define B_AX_TXAGC_TBL_RA_MSK 0x3f
#define B_AX_TXAGC_CCK_HT_OFFSET_SH 16
#define B_AX_TXAGC_CCK_HT_OFFSET_MSK 0xf
#define B_AX_TXAGC_LEGACY_HT_OFFSET_SH 12
#define B_AX_TXAGC_LEGACY_HT_OFFSET_MSK 0xf
#define B_AX_TXAGC_HT_OFFSET_SH 8
#define B_AX_TXAGC_HT_OFFSET_MSK 0xf
#define B_AX_TXAGC_VHT_HT_OFFSET_SH 4
#define B_AX_TXAGC_VHT_HT_OFFSET_MSK 0xf
#define B_AX_TXAGC_HE_HT_OFFSET_SH 0
#define B_AX_TXAGC_HE_HT_OFFSET_MSK 0xf
#define R_AX_PWR_LMT_CTRL 0xD208
#define R_AX_PWR_LMT_CTRL_C1 0xF208
#define B_AX_FORCE_NORM_RSP_HE_TB_EN_ON BIT(24)
#define B_AX_FORCE_PWR_BY_LIMIT_BF0_EN BIT(23)
#define B_AX_FORCE_PWR_BY_LIMIT_BF1_EN BIT(22)
#define B_AX_TXAGC_PWR_LIM_BF0_EN BIT(21)
#define B_AX_TXAGC_PWR_LIM_BF1_EN BIT(20)
#define B_AX_TXAGC_BW20_BW40_OFFSET_SH 16
#define B_AX_TXAGC_BW20_BW40_OFFSET_MSK 0xf
#define B_AX_TXAGC_RFBW_40M_OFFSET_SH 12
#define B_AX_TXAGC_RFBW_40M_OFFSET_MSK 0xf
#define B_AX_TXAGC_BW80_BW40_OFFSET_SH 8
#define B_AX_TXAGC_BW80_BW40_OFFSET_MSK 0xf
#define B_AX_TXAGC_BW160_BW40_OFFSET_SH 4
#define B_AX_TXAGC_BW160_BW40_OFFSET_MSK 0xf
#define B_AX_TXAGC_BW80_80_BW40_OFFSET_SH 0
#define B_AX_TXAGC_BW80_80_BW40_OFFSET_MSK 0xf
#define R_AX_PWR_MACID_CTRL 0xD20C
#define R_AX_PWR_MACID_CTRL_C1 0xF20C
#define B_AX_TXAGC_PWR_BY_MACID_EN BIT(29)
#define B_AX_FORCE_CCA_PWR_TH_VALUE_EN BIT(28)
#define B_AX_FORCE_CCA_PWR_TH_VALUE_SH 20
#define B_AX_FORCE_CCA_PWR_TH_VALUE_MSK 0xff
#define B_AX_FORCE_CCA_PWR_TH_EN BIT(17)
#define B_AX_FORCE_PWR_BY_MACID_EN BIT(16)
#define B_AX_FORCE_PWR_BY_MACID_VALUE_SH 8
#define B_AX_FORCE_PWR_BY_MACID_VALUE_MSK 0xff
#define B_AX_FORCE_PWR_BY_MACID_VALUE_EN BIT(7)
#define B_AX_TXPWR_LIM_TBL_RD BIT(6)
#define B_AX_TXPWR_LIM_TBL_RA_SH 0
#define B_AX_TXPWR_LIM_TBL_RA_MSK 0x3f
#define R_AX_PWR_BF_CTRL 0xD210
#define R_AX_PWR_BF_CTRL_C1 0xF210
#define B_AX_TXAGC_BF_PWR_BOOST_EN BIT(31)
#define B_AX_HE_ER_SU_PWR_REDUCE_VAL_SH 19
#define B_AX_HE_ER_SU_PWR_REDUCE_VAL_MSK 0x1f
#define B_AX_HE_ER_SU_PWR_REDUCE_EN BIT(18)
#define B_AX_FORCE_PWR_BY_LIMIT_BFOFF_VALUE_SH 9
#define B_AX_FORCE_PWR_BY_LIMIT_BFOFF_VALUE_MSK 0x1ff
#define B_AX_FORCE_PWR_BY_LIMIT_BFON_VALUE_SH 0
#define B_AX_FORCE_PWR_BY_LIMIT_BFON_VALUE_MSK 0x1ff
#define R_AX_PWR_MACID_REG 0xD214
#define R_AX_PWR_MACID_REG_C1 0xF214
#define B_AX_TXPWR_REG3_SH 24
#define B_AX_TXPWR_REG3_MSK 0xff
#define B_AX_TXPWR_REG2_SH 16
#define B_AX_TXPWR_REG2_MSK 0xff
#define B_AX_TXPWR_REG1_SH 8
#define B_AX_TXPWR_REG1_MSK 0xff
#define B_AX_TXPWR_REG0_SH 0
#define B_AX_TXPWR_REG0_MSK 0xff
#define R_AX_PWR_MACID_REG2 0xD218
#define R_AX_PWR_MACID_REG2_C1 0xF218
#define B_AX_TXPWR_BY_MACID_TBL_RD BIT(31)
#define B_AX_TXPWR_BY_MACID_TBL_RA_SH 24
#define B_AX_TXPWR_BY_MACID_TBL_RA_MSK 0x7f
#define B_AX_TXPWR_REG5_EN BIT(21)
#define B_AX_TXPWR_REG4_EN BIT(20)
#define B_AX_TXPWR_REG3_EN BIT(19)
#define B_AX_TXPWR_REG2_EN BIT(18)
#define B_AX_TXPWR_REG1_EN BIT(17)
#define B_AX_TXPWR_REG0_EN BIT(16)
#define B_AX_TXPWR_REG5_SH 8
#define B_AX_TXPWR_REG5_MSK 0xff
#define B_AX_TXPWR_REG4_SH 0
#define B_AX_TXPWR_REG4_MSK 0xff
#define R_AX_PWR_RU_LMT_CTRL 0xD21C
#define R_AX_PWR_RU_LMT_CTRL_C1 0xF21C
#define B_AX_TXAGC_LTE_SH 18
#define B_AX_TXAGC_LTE_MSK 0x1ff
#define B_AX_TXPWR_RU_LIM_EN BIT(17)
#define B_AX_TXPWR_RU_LIM_TBL_RD BIT(16)
#define B_AX_TXPWR_RU_LIM_TBL_RA_SH 11
#define B_AX_TXPWR_RU_LIM_TBL_RA_MSK 0x1f
#define B_AX_FORCE_PWR_BY_RU_LIMIT_EN BIT(10)
#define B_AX_FORCE_PWR_BY_RU_LIMIT_EN_VALUE BIT(9)
#define B_AX_FORCE_PWR_BY_RU_LIMIT_VALUE_SH 0
#define B_AX_FORCE_PWR_BY_RU_LIMIT_VALUE_MSK 0x1ff
#define R_AX_PWR_COEXT_CTRL 0xD220
#define R_AX_PWR_COEXT_CTRL_C1 0xF220
#define B_AX_CCK_NORM_TERM_SH 18
#define B_AX_CCK_NORM_TERM_MSK 0x7f
#define B_AX_TXPWR_MAC_MAX_BND_SH 12
#define B_AX_TXPWR_MAC_MAX_BND_MSK 0x3f
#define B_AX_TXAGC_BT_SH 3
#define B_AX_TXAGC_BT_MSK 0x1ff
#define B_AX_TXAGC_LTE_EN BIT(2)
#define B_AX_TXAGC_BT_EN BIT(1)
#define R_AX_PWR_SWING_LEG_CTRL 0xD224
#define R_AX_PWR_SWING_LEG_CTRL_C1 0xF224
#define B_AX_TXBIAS_LEGACY_BELOW_TH_VAL_SH 29
#define B_AX_TXBIAS_LEGACY_BELOW_TH_VAL_MSK 0x3
#define B_AX_TXBIAS_LEGACY_OV_TH_VAL_SH 27
#define B_AX_TXBIAS_LEGACY_OV_TH_VAL_MSK 0x3
#define B_AX_TXBBSWING_LEGACY_BELOW_TH_VAL_SH 23
#define B_AX_TXBBSWING_LEGACY_BELOW_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_LEGACY_OV_TH_VAL_SH 19
#define B_AX_TXBBSWING_LEGACY_OV_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_TXBIAS_LEGACY_TH_SH 15
#define B_AX_TXBBSWING_TXBIAS_LEGACY_TH_MSK 0xf
#define B_AX_TXBIAS_CCK_BELOW_TH_VAL_SH 13
#define B_AX_TXBIAS_CCK_BELOW_TH_VAL_MSK 0x3
#define B_AX_TXBIAS_CCK_OV_TH_VAL_SH 11
#define B_AX_TXBIAS_CCK_OV_TH_VAL_MSK 0x3
#define B_AX_TXBBSWING_CCK_BELOW_TH_VAL_SH 7
#define B_AX_TXBBSWING_CCK_BELOW_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_CCK_OV_TH_VAL_SH 3
#define B_AX_TXBBSWING_CCK_OV_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_TXBIAS_CCK_TH_SH 0
#define B_AX_TXBBSWING_TXBIAS_CCK_TH_MSK 0x7
#define R_AX_PWR_SWING_VHT_CTRL 0xD228
#define R_AX_PWR_SWING_VHT_CTRL_C1 0xF228
#define B_AX_TXBIAS_VHT_OV_TH_VAL_SH 30
#define B_AX_TXBIAS_VHT_OV_TH_VAL_MSK 0x3
#define B_AX_TXBBSWING_VHT_BELOW_TH_VAL_SH 26
#define B_AX_TXBBSWING_VHT_BELOW_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_VHT_OV_TH_VAL_SH 22
#define B_AX_TXBBSWING_VHT_OV_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_TXBIAS_VHT_TH_SH 18
#define B_AX_TXBBSWING_TXBIAS_VHT_TH_MSK 0xf
#define B_AX_TXBIAS_HT_BELOW_TH_VAL_SH 16
#define B_AX_TXBIAS_HT_BELOW_TH_VAL_MSK 0x3
#define B_AX_TXBIAS_HT_OV_TH_VAL_SH 14
#define B_AX_TXBIAS_HT_OV_TH_VAL_MSK 0x3
#define B_AX_TXBBSWING_HT_BELOW_TH_VAL_SH 10
#define B_AX_TXBBSWING_HT_BELOW_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_HT_OV_TH_VAL_SH 6
#define B_AX_TXBBSWING_HT_OV_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_TXBIAS_HT_TH_SH 2
#define B_AX_TXBBSWING_TXBIAS_HT_TH_MSK 0xf
#define R_AX_PWR_SWING_HE_CTRL 0xD22C
#define R_AX_PWR_SWING_HE_CTRL_C1 0xF22C
#define B_AX_CFIR_BY_RATE_OFF_LEGACY_BELOW_TH_VAL BIT(28)
#define B_AX_CFIR_BY_RATE_OFF_LEGACY_OV_TH_VAL BIT(27)
#define B_AX_CFIR_BY_RATE_OFF_LEGACY_TH_SH 23
#define B_AX_CFIR_BY_RATE_OFF_LEGACY_TH_MSK 0xf
#define B_AX_CFIR_BY_RATE_OFF_CCK_BELOW_TH_VAL BIT(22)
#define B_AX_CFIR_BY_RATE_OFF_CCK_OV_TH_VAL BIT(21)
#define B_AX_CFIR_BY_RATE_OFF_CCK_TH_SH 18
#define B_AX_CFIR_BY_RATE_OFF_CCK_TH_MSK 0x7
#define B_AX_TXBIAS_HE_BELOW_TH_VAL_SH 16
#define B_AX_TXBIAS_HE_BELOW_TH_VAL_MSK 0x3
#define B_AX_TXBIAS_HE_OV_TH_VAL_SH 14
#define B_AX_TXBIAS_HE_OV_TH_VAL_MSK 0x3
#define B_AX_TXBBSWING_HE_BELOW_TH_VAL_SH 10
#define B_AX_TXBBSWING_HE_BELOW_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_HE_OV_TH_VAL_SH 6
#define B_AX_TXBBSWING_HE_OV_TH_VAL_MSK 0xf
#define B_AX_TXBBSWING_TXBIAS_HE_TH_SH 2
#define B_AX_TXBBSWING_TXBIAS_HE_TH_MSK 0xf
#define B_AX_TXBIAS_VHT_BELOW_TH_VAL_SH 0
#define B_AX_TXBIAS_VHT_BELOW_TH_VAL_MSK 0x3
#define R_AX_PWR_SWING_OTHER_CTRL0 0xD230
#define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230
#define B_AX_DPD_BY_RATE_OFF_LEGACY_BELOW_TH_VAL BIT(28)
#define B_AX_DPD_BY_RATE_OFF_LEGACY_OV_TH_VAL BIT(27)
#define B_AX_DPD_BY_RATE_OFF_LEGACY_TH_SH 23
#define B_AX_DPD_BY_RATE_OFF_LEGACY_TH_MSK 0xf
#define B_AX_DPD_BY_RATE_OFF_CCK_BELOW_TH_VAL BIT(22)
#define B_AX_DPD_BY_RATE_OFF_CCK_OV_TH_VAL BIT(21)
#define B_AX_DPD_BY_RATE_OFF_CCK_TH_SH 18
#define B_AX_DPD_BY_RATE_OFF_CCK_TH_MSK 0x7
#define B_AX_CFIR_BY_RATE_OFF_HE_BELOW_TH_VAL BIT(17)
#define B_AX_CFIR_BY_RATE_OFF_HE_OV_TH_VAL BIT(16)
#define B_AX_CFIR_BY_RATE_OFF_HE_TH_SH 12
#define B_AX_CFIR_BY_RATE_OFF_HE_TH_MSK 0xf
#define B_AX_CFIR_BY_RATE_OFF_VHT_BELOW_TH_VAL BIT(11)
#define B_AX_CFIR_BY_RATE_OFF_VHT_OV_TH_VAL BIT(10)
#define B_AX_CFIR_BY_RATE_OFF_VHT_TH_SH 6
#define B_AX_CFIR_BY_RATE_OFF_VHT_TH_MSK 0xf
#define B_AX_CFIR_BY_RATE_OFF_HT_BELOW_TH_VAL BIT(5)
#define B_AX_CFIR_BY_RATE_OFF_HT_OV_TH_VAL BIT(4)
#define B_AX_CFIR_BY_RATE_OFF_HT_TH_SH 0
#define B_AX_CFIR_BY_RATE_OFF_HT_TH_MSK 0xf
#define R_AX_PWR_SWING_OTHER_CTRL1 0xD234
#define R_AX_PWR_SWING_OTHER_CTRL1_C1 0xF234
#define B_AX_DPD_BY_RATE_OFF_SR_DONT_APPLY BIT(30)
#define B_AX_CFIR_BY_RATE_OFF_SR_DONT_APPLY BIT(29)
#define B_AX_TXBBSWING_TXBIAS_SR_DONT_APPLY BIT(28)
#define B_AX_DPD_BY_RATE_OFF_HE_BELOW_TH_VAL BIT(17)
#define B_AX_DPD_BY_RATE_OFF_HE_OV_TH_VAL BIT(16)
#define B_AX_DPD_BY_RATE_OFF_HE_TH_SH 12
#define B_AX_DPD_BY_RATE_OFF_HE_TH_MSK 0xf
#define B_AX_DPD_BY_RATE_OFF_VHT_BELOW_TH_VAL BIT(11)
#define B_AX_DPD_BY_RATE_OFF_VHT_OV_TH_VAL BIT(10)
#define B_AX_DPD_BY_RATE_OFF_VHT_TH_SH 6
#define B_AX_DPD_BY_RATE_OFF_VHT_TH_MSK 0xf
#define B_AX_DPD_BY_RATE_OFF_HT_BELOW_TH_VAL BIT(5)
#define B_AX_DPD_BY_RATE_OFF_HT_OV_TH_VAL BIT(4)
#define B_AX_DPD_BY_RATE_OFF_HT_TH_SH 0
#define B_AX_DPD_BY_RATE_OFF_HT_TH_MSK 0xf
#define R_AX_PWR_SR_CTRL0 0xD238
#define R_AX_PWR_SR_CTRL0_C1 0xF238
#define B_AX_SR_PWR_CTRL_DBG_EN BIT(31)
#define B_AX_SR_RATE_TBL_RD_MCS_TXDIFF_SH 20
#define B_AX_SR_RATE_TBL_RD_MCS_TXDIFF_MSK 0x1f
#define B_AX_SR_RATE_MAP_TBL_RD_MCS_SEL BIT(19)
#define B_AX_TXPWR_SR_FORCE_OFF BIT(18)
#define B_AX_TXPWR_STA_UL_FORCE_OFF BIT(17)
#define B_AX_SR_TXPWR_PD_WITH_PD_MACID BIT(16)
#define B_AX_SR_RATE_MAP_TBL_RD BIT(15)
#define B_AX_SR_RATE_MAP_TBL_RD_MCS_SH 11
#define B_AX_SR_RATE_MAP_TBL_RD_MCS_MSK 0xf
#define B_AX_TXPWR_CTRL_NORM_RESP_DBG_EN BIT(10)
#define B_AX_TXAGC_PSEUDO_PWR_EN BIT(9)
#define B_AX_TXAGC_PSEUDO_PWR_SH 0
#define B_AX_TXAGC_PSEUDO_PWR_MSK 0x1ff
#define R_AX_PWR_SR_CTRL1 0xD23C
#define R_AX_PWR_SR_CTRL1_C1 0xF23C
#define B_AX_MCS_TH_HE_SH 24
#define B_AX_MCS_TH_HE_MSK 0xf
#define B_AX_MCS_TH_VHT_SH 20
#define B_AX_MCS_TH_VHT_MSK 0xf
#define B_AX_MCS_TH_HT_MOD8_SH 16
#define B_AX_MCS_TH_HT_MOD8_MSK 0xf
#define B_AX_MCS_TH_LEGACY_SH 12
#define B_AX_MCS_TH_LEGACY_MSK 0xf
#define B_AX_MCS_TH_CCK_SH 8
#define B_AX_MCS_TH_CCK_MSK 0xf
#define B_AX_TXPWR_REF_SH 0
#define B_AX_TXPWR_REF_MSK 0x7f
#define R_AX_PWR_UL_CTRL0 0xD240
#define R_AX_PWR_UL_CTRL0_C1 0xF240
#define B_AX_PL_TOLER_RANGE_SH 20
#define B_AX_PL_TOLER_RANGE_MSK 0x1ff
#define B_AX_PWR_BB_MIN_DBM_SH 9
#define B_AX_PWR_BB_MIN_DBM_MSK 0x1ff
#define B_AX_PWR_ERROR_TOLER_SH 0
#define B_AX_PWR_ERROR_TOLER_MSK 0xff
#define R_AX_PWR_UL_CTRL1 0xD244
#define R_AX_PWR_UL_CTRL1_C1 0xF244
#define B_AX_MACID3_SH 24
#define B_AX_MACID3_MSK 0x7f
#define B_AX_MACID2_SH 16
#define B_AX_MACID2_MSK 0x7f
#define B_AX_MACID1_SH 8
#define B_AX_MACID1_MSK 0x7f
#define B_AX_MACID0_SH 0
#define B_AX_MACID0_MSK 0x7f
#define R_AX_PWR_UL_CTRL2 0xD248
#define R_AX_PWR_UL_CTRL2_C1 0xF248
#define B_AX_CFO_COMP_SR_SH 24
#define B_AX_CFO_COMP_SR_MSK 0x7
#define B_AX_CFO_COMP_NORM_RESP_SH 20
#define B_AX_CFO_COMP_NORM_RESP_MSK 0x7
#define B_AX_CFO_COMP4_SH 16
#define B_AX_CFO_COMP4_MSK 0x7
#define B_AX_CFO_COMP3_SH 12
#define B_AX_CFO_COMP3_MSK 0x7
#define B_AX_CFO_COMP2_SH 8
#define B_AX_CFO_COMP2_MSK 0x7
#define B_AX_CFO_COMP1_SH 4
#define B_AX_CFO_COMP1_MSK 0x7
#define B_AX_CFO_COMP0_SH 0
#define B_AX_CFO_COMP0_MSK 0x7
#define R_AX_PWR_UL_CTRL3 0xD24C
#define R_AX_PWR_UL_CTRL3_C1 0xF24C
#define B_AX_TF_RDY_TXBF_FORCE_OFF BIT(22)
#define B_AX_FORCE_PL_UPPER_EN_EQUL_N_TX_DIVIDE2 BIT(21)
#define B_AX_FORCE_N_TX_DIVIDE2_OFF BIT(20)
#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MAX_SH 11
#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MAX_MSK 0x1ff
#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MIN_SH 0
#define B_AX_STA_PWR_CTRL_PWRMAX_LIM_MIN_MSK 0x1ff
#define R_AX_PWR_UL_CTRL4 0xD250
#define R_AX_PWR_UL_CTRL4_C1 0xF250
#define B_AX_STA_PWR_CTRL_RPL_LIM_MIN_SH 16
#define B_AX_STA_PWR_CTRL_RPL_LIM_MIN_MSK 0x3ff
#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MAX_SH 8
#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MAX_MSK 0xff
#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MIN_SH 0
#define B_AX_STA_PWR_CTRL_RSSI_TARGET_LIM_MIN_MSK 0xff
#define R_AX_PWR_UL_CTRL5 0xD254
#define R_AX_PWR_UL_CTRL5_C1 0xF254
#define B_AX_FORCE_PL_UPPER_EN_VAL BIT(23)
#define B_AX_FORCE_PL_UPPER_EN_ON BIT(22)
#define B_AX_SR_TXPWR_RESP_RDY_FORCE_OFF BIT(15)
#define B_AX_SR_TXPWR_PD_RDY_FORCE_OFF BIT(14)
#define B_AX_SR_TXPWR_RATE_RDY_FORCE_OFF BIT(13)
#define B_AX_TF_RDY_FORCE_OFF BIT(12)
#define B_AX_TXCTRL_INFO_RDY_FORCE_OFF BIT(11)
#define B_AX_STA_PWR_CTRL_DBG_EN BIT(10)
#define B_AX_STA_PWR_CTRL_RPL_LIM_MAX_SH 0
#define B_AX_STA_PWR_CTRL_RPL_LIM_MAX_MSK 0x3ff
#define R_AX_PWR_UL_CTRL6 0xD258
#define R_AX_PWR_UL_CTRL6_C1 0xF258
#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MIN_SH 24
#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MIN_MSK 0x7f
#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MAX_SH 16
#define B_AX_STA_PWR_CTRL_AP_TXPWR_LIM_MAX_MSK 0x7f
#define B_AX_TXPWR_FORCE_RATE_EN BIT(12)
#define B_AX_TXPWR_FORCE_RATE_SH 0
#define B_AX_TXPWR_FORCE_RATE_MSK 0xfff
#define R_AX_PWR_NORM_FORCE0 0xD25C
#define R_AX_PWR_NORM_FORCE0_C1 0xF25C
#define B_AX_FORCE_MACID_EN BIT(30)
#define B_AX_FORCE_MACID_VALUE_SH 23
#define B_AX_FORCE_MACID_VALUE_MSK 0x7f
#define B_AX_FORCE_BW80P80_EN_EN BIT(22)
#define B_AX_FORCE_BW80P80_EN_VALUE BIT(21)
#define B_AX_FORCE_RF_BW_IDX_EN BIT(20)
#define B_AX_FORCE_RF_BW_IDX_VALUE_SH 18
#define B_AX_FORCE_RF_BW_IDX_VALUE_MSK 0x3
#define B_AX_FORCE_DCM_EN BIT(17)
#define B_AX_FORCE_DCM_VALUE BIT(16)
#define B_AX_FORCE_DBW_IDX_EN BIT(15)
#define B_AX_FORCE_DBW_IDX_VALUE_SH 13
#define B_AX_FORCE_DBW_IDX_VALUE_MSK 0x3
#define B_AX_FORCE_MAX_RATE_EN BIT(12)
#define B_AX_FORCE_MAX_RATE_VALUE_SH 0
#define B_AX_FORCE_MAX_RATE_VALUE_MSK 0xfff
#define R_AX_PWR_NORM_FORCE1 0xD260
#define R_AX_PWR_NORM_FORCE1_C1 0xF260
#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29)
#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_SH 24
#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MSK 0x1f
#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23)
#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22)
#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21)
#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20)
#define B_AX_FORCE_BT_GRANT_EN BIT(19)
#define B_AX_FORCE_BT_GRANT_VALUE BIT(18)
#define B_AX_FORCE_RX_LTE_EN BIT(17)
#define B_AX_FORCE_RX_LTE_VALUE BIT(16)
#define B_AX_FORCE_TXBF_EN_EN BIT(15)
#define B_AX_FORCE_TXBF_EN_VALUE BIT(14)
#define B_AX_FORCE_TXSC_EN BIT(13)
#define B_AX_FORCE_TXSC_VALUE_SH 9
#define B_AX_FORCE_TXSC_VALUE_MSK 0xf
#define B_AX_FORCE_NTX_EN BIT(6)
#define B_AX_FORCE_NTX_VALUE BIT(5)
#define B_AX_FORCE_PWR_MODE_EN BIT(3)
#define B_AX_FORCE_PWR_MODE_VALUE_SH 0
#define B_AX_FORCE_PWR_MODE_VALUE_MSK 0x7
#define R_AX_PWR_SR_FORCE0 0xD264
#define R_AX_PWR_SR_FORCE0_C1 0xF264
#define B_AX_FORCE_SR_RESP_DCM_EN BIT(30)
#define B_AX_FORCE_SR_RESP_DCM_VALUE BIT(29)
#define B_AX_FORCE_SR_RATE_DCM_EN BIT(28)
#define B_AX_FORCE_SR_RATE_DCM_VALUE BIT(27)
#define B_AX_FORCE_SR_TXPWR_PD_EN BIT(26)
#define B_AX_FORCE_SR_TXPWR_PD_VALUE_SH 20
#define B_AX_FORCE_SR_TXPWR_PD_VALUE_MSK 0x3f
#define B_AX_FORCE_SR_RATE_IDX_EN BIT(19)
#define B_AX_FORCE_SR_RATE_IDX_VALUE_SH 7
#define B_AX_FORCE_SR_RATE_IDX_VALUE_MSK 0xfff
#define B_AX_FORCE_SR_TXPWR_TOLERANCE_EN BIT(6)
#define B_AX_FORCE_SR_TXPWR_TOLERANCE_VALUE_SH 0
#define B_AX_FORCE_SR_TXPWR_TOLERANCE_VALUE_MSK 0x3f
#define R_AX_PWR_SR_FORCE1 0xD268
#define R_AX_PWR_SR_FORCE1_C1 0xF268
#define B_AX_FORCE_RPL_EN BIT(29)
#define B_AX_FORCE_RPL_VALUE_SH 20
#define B_AX_FORCE_RPL_VALUE_MSK 0x1ff
#define B_AX_FORCE_SR_RESP_RATE_IDX_EN BIT(19)
#define B_AX_FORCE_SR_RESP_RATE_IDX_VALUE_SH 7
#define B_AX_FORCE_SR_RESP_RATE_IDX_VALUE_MSK 0xfff
#define B_AX_FORCE_SR_RESP_TXPWR_PD_EN BIT(6)
#define B_AX_FORCE_SR_RESP_TXPWR_PD_VALUE_SH 0
#define B_AX_FORCE_SR_RESP_TXPWR_PD_VALUE_MSK 0x3f
#define R_AX_PWR_SR_FORCE2 0xD26C
#define R_AX_PWR_SR_FORCE2_C1 0xF26C
#define B_AX_FORCE_TF_AP_TX_PWR_EN BIT(31)
#define B_AX_FORCE_TF_AP_TX_PWR_VALUE_SH 25
#define B_AX_FORCE_TF_AP_TX_PWR_VALUE_MSK 0x3f
#define B_AX_FORCE_TF_RATE_IDX_EN BIT(24)
#define B_AX_FORCE_TF_RATE_IDX_VALUE_SH 12
#define B_AX_FORCE_TF_RATE_IDX_VALUE_MSK 0xfff
#define B_AX_FORCE_RPL_UPPER_EN_EN BIT(11)
#define B_AX_FORCE_RPL_UPPER_EN_VALUE BIT(10)
#define B_AX_FORCE_RPL_UPPER_EN BIT(9)
#define B_AX_FORCE_RPL_UPPER_VALUE_SH 0
#define B_AX_FORCE_RPL_UPPER_VALUE_MSK 0x1ff
#define R_AX_PWR_UL_FORCE0 0xD270
#define R_AX_PWR_UL_FORCE0_C1 0xF270
#define B_AX_FORCE_RU_ALLOC_EN BIT(24)
#define B_AX_FORCE_RU_ALLOC_VALUE_SH 16
#define B_AX_FORCE_RU_ALLOC_VALUE_MSK 0xff
#define B_AX_FORCE_TF_MACID_EN BIT(15)
#define B_AX_FORCE_TF_MACID_VALUE_SH 8
#define B_AX_FORCE_TF_MACID_VALUE_MSK 0x7f
#define B_AX_FORCE_TF_RSSI_TARGET_EN BIT(7)
#define B_AX_FORCE_TF_RSSI_TARGET_VALUE_SH 0
#define B_AX_FORCE_TF_RSSI_TARGET_VALUE_MSK 0x7f
#define R_AX_PWR_NORM_FORCE2 0xD274
#define R_AX_PWR_NORM_FORCE2_C1 0xF274
#define B_AX_FORCE_OUT_CCA_PWR_TH_EN_ON BIT(18)
#define B_AX_FORCE_OUT_CCA_PWR_TH_EN BIT(17)
#define B_AX_FORCE_OUT_CCA_PWR_TH_ON BIT(16)
#define B_AX_FORCE_OUT_CCA_PWR_TH_SH 8
#define B_AX_FORCE_OUT_CCA_PWR_TH_MSK 0xff
#define B_AX_TXPWR_CTRL_DBG_SEL_SH 0
#define B_AX_TXPWR_CTRL_DBG_SEL_MSK 0x3f
#define R_AX_PWR_UL_FORCE1 0xD278
#define R_AX_PWR_UL_FORCE1_C1 0xF278
#define B_AX_FORCE_OUT_CFO_COMP_ON BIT(31)
#define B_AX_FORCE_OUT_CFO_COMP_SH 28
#define B_AX_FORCE_OUT_CFO_COMP_MSK 0x7
#define B_AX_FORCE_OUT_ABORT_TX_IDX_ON BIT(27)
#define B_AX_FORCE_OUT_ABORT_TX_IDX_SH 25
#define B_AX_FORCE_OUT_ABORT_TX_IDX_MSK 0x3
#define B_AX_FORCE_OUT_MIN_TX_PWR_FLAG_ON BIT(24)
#define B_AX_FORCE_OUT_MIN_TX_PWR_FLAG BIT(23)
#define B_AX_FORCE_OUT_UPH_ON BIT(22)
#define B_AX_FORCE_OUT_UPH_SH 17
#define B_AX_FORCE_OUT_UPH_MSK 0x1f
#define B_AX_FORCE_OUT_STA_TXPWR_MAC_ON BIT(16)
#define B_AX_FORCE_OUT_STA_TXPWR_MAC_SH 10
#define B_AX_FORCE_OUT_STA_TXPWR_MAC_MSK 0x3f
#define B_AX_FORCE_OUT_STA_TXPWR_BB_ON BIT(9)
#define B_AX_FORCE_OUT_STA_TXPWR_BB_SH 0
#define B_AX_FORCE_OUT_STA_TXPWR_BB_MSK 0x1ff
#define R_AX_PWR_NORM_FORCE3 0xD27C
#define R_AX_PWR_NORM_FORCE3_C1 0xF27C
#define B_AX_FORCE_OUT_TXAGC_BBSWING_ON BIT(31)
#define B_AX_FORCE_OUT_TXAGC_BBSWING_SH 27
#define B_AX_FORCE_OUT_TXAGC_BBSWING_MSK 0xf
#define B_AX_FORCE_OUT_TXBIAS_ON BIT(26)
#define B_AX_FORCE_OUT_TXBIAS_SH 24
#define B_AX_FORCE_OUT_TXBIAS_MSK 0x3
#define B_AX_FORCE_OUT_TXPWR_BFON_BOOST_DB_SEG0_ON BIT(23)
#define B_AX_FORCE_OUT_TXPWR_BFON_BOOST_DB_SEG0_SH 18
#define B_AX_FORCE_OUT_TXPWR_BFON_BOOST_DB_SEG0_MSK 0x1f
#define B_AX_FORCE_OUT_TXPWR_BB_ON BIT(17)
#define B_AX_FORCE_OUT_TXPWR_BB_SH 8
#define B_AX_FORCE_OUT_TXPWR_BB_MSK 0x1ff
#define B_AX_FORCE_OUT_TXPWR_MAC_ON BIT(6)
#define B_AX_FORCE_OUT_TXPWR_MAC_SH 0
#define B_AX_FORCE_OUT_TXPWR_MAC_MSK 0x3f
#define R_AX_PWR_NORM_FORCE4 0xD280
#define R_AX_PWR_NORM_FORCE4_C1 0xF280
#define B_AX_FORCE_OUT_SR_DCM_ON BIT(25)
#define B_AX_FORCE_OUT_SR_DCM BIT(24)
#define B_AX_FORCE_OUT_SR_MCS_ON BIT(23)
#define B_AX_FORCE_OUT_SR_MCS_SH 11
#define B_AX_FORCE_OUT_SR_MCS_MSK 0xfff
#define B_AX_FORCE_OUT_SR_PD_THREHOLD_ON BIT(10)
#define B_AX_FORCE_OUT_SR_PD_THREHOLD_SH 4
#define B_AX_FORCE_OUT_SR_PD_THREHOLD_MSK 0x3f
#define B_AX_FORCE_OUT_CFIR_BY_RATE_OFF_ON BIT(3)
#define B_AX_FORCE_OUT_CFIR_BY_RATE_OFF BIT(2)
#define B_AX_FORCE_OUT_DPD_BY_RATE_OFF_ON BIT(1)
#define B_AX_FORCE_OUT_DPD_BY_RATE_OFF BIT(0)
#define R_AX_PWR_RATE_TABLE0 0xD2C0
#define R_AX_PWR_RATE_TABLE0_C1 0xF2C0
#define B_AX_TXAGC_CCK11M_SH 24
#define B_AX_TXAGC_CCK11M_MSK 0x1f
#define B_AX_TXAGC_CCK5P5M_SH 16
#define B_AX_TXAGC_CCK5P5M_MSK 0x1f
#define B_AX_TXAGC_CCK2M_SH 8
#define B_AX_TXAGC_CCK2M_MSK 0xf
#define B_AX_TXAGC_CCK1M_SH 0
#define B_AX_TXAGC_CCK1M_MSK 0x1f
#define R_AX_PWR_RATE_TABLE1 0xD2C4
#define R_AX_PWR_RATE_TABLE1_C1 0xF2C4
#define B_AX_TXAGC_LEGACY18M_SH 24
#define B_AX_TXAGC_LEGACY18M_MSK 0x1f
#define B_AX_TXAGC_LEGACY12M_SH 16
#define B_AX_TXAGC_LEGACY12M_MSK 0x1f
#define B_AX_TXAGC_LEGACY9M_SH 8
#define B_AX_TXAGC_LEGACY9M_MSK 0xf
#define B_AX_TXAGC_LEGACY6M_SH 0
#define B_AX_TXAGC_LEGACY6M_MSK 0x1f
#define R_AX_PWR_RATE_TABLE2 0xD2C8
#define R_AX_PWR_RATE_TABLE2_C1 0xF2C8
#define B_AX_TXAGC_LEGACY54M_SH 24
#define B_AX_TXAGC_LEGACY54M_MSK 0x1f
#define B_AX_TXAGC_LEGACY48M_SH 16
#define B_AX_TXAGC_LEGACY48M_MSK 0x1f
#define B_AX_TXAGC_LEGACY36M_SH 8
#define B_AX_TXAGC_LEGACY36M_MSK 0xf
#define B_AX_TXAGC_LEGACY24M_SH 0
#define B_AX_TXAGC_LEGACY24M_MSK 0x1f
#define R_AX_PWR_RATE_TABLE3 0xD2CC
#define R_AX_PWR_RATE_TABLE3_C1 0xF2CC
#define B_AX_TXAGC_NONLEGACY_MCS3_NSS1_SH 24
#define B_AX_TXAGC_NONLEGACY_MCS3_NSS1_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS2_NSS1_SH 16
#define B_AX_TXAGC_NONLEGACY_MCS2_NSS1_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS1_NSS1_SH 8
#define B_AX_TXAGC_NONLEGACY_MCS1_NSS1_MSK 0xf
#define B_AX_TXAGC_NONLEGACY_MCS0_NSS1_SH 0
#define B_AX_TXAGC_NONLEGACY_MCS0_NSS1_MSK 0x1f
#define R_AX_PWR_RATE_TABLE4 0xD2D0
#define R_AX_PWR_RATE_TABLE4_C1 0xF2D0
#define B_AX_TXAGC_NONLEGACY_MCS7_NSS1_SH 24
#define B_AX_TXAGC_NONLEGACY_MCS7_NSS1_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS6_NSS1_SH 16
#define B_AX_TXAGC_NONLEGACY_MCS6_NSS1_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS5_NSS1_SH 8
#define B_AX_TXAGC_NONLEGACY_MCS5_NSS1_MSK 0xf
#define B_AX_TXAGC_NONLEGACY_MCS4_NSS1_SH 0
#define B_AX_TXAGC_NONLEGACY_MCS4_NSS1_MSK 0x1f
#define R_AX_PWR_RATE_TABLE5 0xD2D4
#define R_AX_PWR_RATE_TABLE5_C1 0xF2D4
#define B_AX_TXAGC_NONLEGACY_MCS11_NSS1_SH 24
#define B_AX_TXAGC_NONLEGACY_MCS11_NSS1_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS10_NSS1_SH 16
#define B_AX_TXAGC_NONLEGACY_MCS10_NSS1_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS9_NSS1_SH 8
#define B_AX_TXAGC_NONLEGACY_MCS9_NSS1_MSK 0xf
#define B_AX_TXAGC_NONLEGACY_MCS8_NSS1_SH 0
#define B_AX_TXAGC_NONLEGACY_MCS8_NSS1_MSK 0x1f
#define R_AX_PWR_RATE_TABLE6 0xD2D8
#define R_AX_PWR_RATE_TABLE6_C1 0xF2D8
#define B_AX_TXAGC_DCM_MCS4_NSS1_SH 24
#define B_AX_TXAGC_DCM_MCS4_NSS1_MSK 0x1f
#define B_AX_TXAGC_DCM_MCS3_NSS1_SH 16
#define B_AX_TXAGC_DCM_MCS3_NSS1_MSK 0x1f
#define B_AX_TXAGC_DCM_MCS1_NSS1_SH 8
#define B_AX_TXAGC_DCM_MCS1_NSS1_MSK 0xf
#define B_AX_TXAGC_DCM_MCS0_NSS1_SH 0
#define B_AX_TXAGC_DCM_MCS0_NSS1_MSK 0x1f
#define R_AX_PWR_RATE_TABLE7 0xD2DC
#define R_AX_PWR_RATE_TABLE7_C1 0xF2DC
#define B_AX_TXAGC_NONLEGACY_MCS3_NSS2_SH 24
#define B_AX_TXAGC_NONLEGACY_MCS3_NSS2_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS2_NSS2_SH 16
#define B_AX_TXAGC_NONLEGACY_MCS2_NSS2_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS1_NSS2_SH 8
#define B_AX_TXAGC_NONLEGACY_MCS1_NSS2_MSK 0xf
#define B_AX_TXAGC_NONLEGACY_MCS0_NSS2_SH 0
#define B_AX_TXAGC_NONLEGACY_MCS0_NSS2_MSK 0x1f
#define R_AX_PWR_RATE_TABLE8 0xD2E0
#define R_AX_PWR_RATE_TABLE8_C1 0xF2E0
#define B_AX_TXAGC_NONLEGACY_MCS7_NSS2_SH 24
#define B_AX_TXAGC_NONLEGACY_MCS7_NSS2_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS6_NSS2_SH 16
#define B_AX_TXAGC_NONLEGACY_MCS6_NSS2_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS5_NSS2_SH 8
#define B_AX_TXAGC_NONLEGACY_MCS5_NSS2_MSK 0xf
#define B_AX_TXAGC_NONLEGACY_MCS4_NSS2_SH 0
#define B_AX_TXAGC_NONLEGACY_MCS4_NSS2_MSK 0x1f
#define R_AX_PWR_RATE_TABLE9 0xD2E4
#define R_AX_PWR_RATE_TABLE9_C1 0xF2E4
#define B_AX_TXAGC_NONLEGACY_MCS11_NSS2_SH 24
#define B_AX_TXAGC_NONLEGACY_MCS11_NSS2_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS10_NSS2_SH 16
#define B_AX_TXAGC_NONLEGACY_MCS10_NSS2_MSK 0x1f
#define B_AX_TXAGC_NONLEGACY_MCS9_NSS2_SH 8
#define B_AX_TXAGC_NONLEGACY_MCS9_NSS2_MSK 0xf
#define B_AX_TXAGC_NONLEGACY_MCS8_NSS2_SH 0
#define B_AX_TXAGC_NONLEGACY_MCS8_NSS2_MSK 0x1f
#define R_AX_PWR_RATE_TABLE10 0xD2E8
#define R_AX_PWR_RATE_TABLE10_C1 0xF2E8
#define B_AX_TXAGC_DCM_MCS4_NSS2_SH 24
#define B_AX_TXAGC_DCM_MCS4_NSS2_MSK 0x1f
#define B_AX_TXAGC_DCM_MCS3_NSS2_SH 16
#define B_AX_TXAGC_DCM_MCS3_NSS2_MSK 0x1f
#define B_AX_TXAGC_DCM_MCS1_NSS2_SH 8
#define B_AX_TXAGC_DCM_MCS1_NSS2_MSK 0xf
#define B_AX_TXAGC_DCM_MCS0_NSS2_SH 0
#define B_AX_TXAGC_DCM_MCS0_NSS2_MSK 0x1f
#define R_AX_PWR_LMT_TABLE0 0xD2EC
#define R_AX_PWR_LMT_TABLE0_C1 0xF2EC
#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW40M_SH 24
#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW40M_MSK 0x7f
#define B_AX_TXAGC_MAX_CCK_1TX_BW40M_SH 15
#define B_AX_TXAGC_MAX_CCK_1TX_BW40M_MSK 0x7f
#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW20M_SH 8
#define B_AX_TXAGC_MAX_CCK_BF_1TX_BW20M_MSK 0x3f
#define B_AX_TXAGC_MAX_CCK_1TX_BW20M_SH 0
#define B_AX_TXAGC_MAX_CCK_1TX_BW20M_MSK 0x7f
#define R_AX_PWR_LMT_TABLE1 0xD2F0
#define R_AX_PWR_LMT_TABLE1_C1 0xF2F0
#define B_AX_TXAGC_MAX_1TX_BF_BW20_0_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW20_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW20_0_SH 15
#define B_AX_TXAGC_MAX_1TX_BW20_0_MSK 0x7f
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_1TX_SH 8
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_1TX_MSK 0x3f
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_1TX_SH 0
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_1TX_MSK 0x7f
#define R_AX_PWR_LMT_TABLE2 0xD2F4
#define R_AX_PWR_LMT_TABLE2_C1 0xF2F4
#define B_AX_TXAGC_MAX_1TX_BF_BW20_2_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW20_2_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW20_2_SH 15
#define B_AX_TXAGC_MAX_1TX_BW20_2_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW20_1_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW20_1_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW20_1_SH 0
#define B_AX_TXAGC_MAX_1TX_BW20_1_MSK 0x7f
#define R_AX_PWR_LMT_TABLE3 0xD2F8
#define R_AX_PWR_LMT_TABLE3_C1 0xF2F8
#define B_AX_TXAGC_MAX_1TX_BF_BW20_4_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW20_4_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW20_4_SH 15
#define B_AX_TXAGC_MAX_1TX_BW20_4_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW20_3_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW20_3_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW20_3_SH 0
#define B_AX_TXAGC_MAX_1TX_BW20_3_MSK 0x7f
#define R_AX_PWR_LMT_TABLE4 0xD2FC
#define R_AX_PWR_LMT_TABLE4_C1 0xF2FC
#define B_AX_TXAGC_MAX_1TX_BF_BW20_6_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW20_6_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW20_6_SH 15
#define B_AX_TXAGC_MAX_1TX_BW20_6_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW20_5_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW20_5_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW20_5_SH 0
#define B_AX_TXAGC_MAX_1TX_BW20_5_MSK 0x7f
#define R_AX_PWR_LMT_TABLE5 0xD300
#define R_AX_PWR_LMT_TABLE5_C1 0xF300
#define B_AX_TXAGC_MAX_1TX_BF_BW40_0_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW40_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW40_0_SH 15
#define B_AX_TXAGC_MAX_1TX_BW40_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW20_7_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW20_7_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW20_7_SH 0
#define B_AX_TXAGC_MAX_1TX_BW20_7_MSK 0x7f
#define R_AX_PWR_LMT_TABLE6 0xD304
#define R_AX_PWR_LMT_TABLE6_C1 0xF304
#define B_AX_TXAGC_MAX_1TX_BF_BW40_2_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW40_2_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW40_2_SH 15
#define B_AX_TXAGC_MAX_1TX_BW40_2_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW40_1_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW40_1_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW40_1_SH 0
#define B_AX_TXAGC_MAX_1TX_BW40_1_MSK 0x7f
#define R_AX_PWR_LMT_TABLE7 0xD308
#define R_AX_PWR_LMT_TABLE7_C1 0xF308
#define B_AX_TXAGC_MAX_1TX_BF_BW80_0_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW80_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW80_0_SH 15
#define B_AX_TXAGC_MAX_1TX_BW80_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW40_3_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW40_3_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW40_3_SH 0
#define B_AX_TXAGC_MAX_1TX_BW40_3_MSK 0x7f
#define R_AX_PWR_LMT_TABLE8 0xD30C
#define R_AX_PWR_LMT_TABLE8_C1 0xF30C
#define B_AX_TXAGC_MAX_1TX_BF_BW160_0_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW160_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW160_0_SH 15
#define B_AX_TXAGC_MAX_1TX_BW160_0_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW80_1_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW80_1_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW80_1_SH 0
#define B_AX_TXAGC_MAX_1TX_BW80_1_MSK 0x7f
#define R_AX_PWR_LMT_TABLE9 0xD310
#define R_AX_PWR_LMT_TABLE9_C1 0xF310
#define B_AX_TXAGC_MAX_1TX_BF_BW40_2P5_SH 24
#define B_AX_TXAGC_MAX_1TX_BF_BW40_2P5_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BW40_2P5_SH 15
#define B_AX_TXAGC_MAX_1TX_BW40_2P5_MSK 0x7f
#define B_AX_TXAGC_MAX_1TX_BF_BW40_0P5_SH 8
#define B_AX_TXAGC_MAX_1TX_BF_BW40_0P5_MSK 0x3f
#define B_AX_TXAGC_MAX_1TX_BW40_0P5_SH 0
#define B_AX_TXAGC_MAX_1TX_BW40_0P5_MSK 0x7f
#define R_AX_PWR_LMT_TABLE10 0xD314
#define R_AX_PWR_LMT_TABLE10_C1 0xF314
#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW40M_SH 24
#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW40M_MSK 0x7f
#define B_AX_TXAGC_MAX_CCK_2TX_BW40M_SH 15
#define B_AX_TXAGC_MAX_CCK_2TX_BW40M_MSK 0x7f
#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW20M_SH 8
#define B_AX_TXAGC_MAX_CCK_BF_2TX_BW20M_MSK 0x3f
#define B_AX_TXAGC_MAX_CCK_2TX_BW20M_SH 0
#define B_AX_TXAGC_MAX_CCK_2TX_BW20M_MSK 0x7f
#define R_AX_PWR_LMT_TABLE11 0xD318
#define R_AX_PWR_LMT_TABLE11_C1 0xF318
#define B_AX_TXAGC_MAX_2TX_BF_BW20_0_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW20_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW20_0_SH 15
#define B_AX_TXAGC_MAX_2TX_BW20_0_MSK 0x7f
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_2TX_SH 8
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_BF_2TX_MSK 0x3f
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_2TX_SH 0
#define B_AX_TXAGC_MAX_LEGACY_NON_DUP_2TX_MSK 0x7f
#define R_AX_PWR_LMT_TABLE12 0xD31C
#define R_AX_PWR_LMT_TABLE12_C1 0xF31C
#define B_AX_TXAGC_MAX_2TX_BF_BW20_2_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW20_2_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW20_2_SH 15
#define B_AX_TXAGC_MAX_2TX_BW20_2_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW20_1_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW20_1_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW20_1_SH 0
#define B_AX_TXAGC_MAX_2TX_BW20_1_MSK 0x7f
#define R_AX_PWR_LMT_TABLE13 0xD320
#define R_AX_PWR_LMT_TABLE13_C1 0xF320
#define B_AX_TXAGC_MAX_2TX_BF_BW20_4_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW20_4_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW20_4_SH 15
#define B_AX_TXAGC_MAX_2TX_BW20_4_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW20_3_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW20_3_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW20_3_SH 0
#define B_AX_TXAGC_MAX_2TX_BW20_3_MSK 0x7f
#define R_AX_PWR_LMT_TABLE14 0xD324
#define R_AX_PWR_LMT_TABLE14_C1 0xF324
#define B_AX_TXAGC_MAX_2TX_BF_BW20_6_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW20_6_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW20_6_SH 15
#define B_AX_TXAGC_MAX_2TX_BW20_6_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW20_5_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW20_5_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW20_5_SH 0
#define B_AX_TXAGC_MAX_2TX_BW20_5_MSK 0x7f
#define R_AX_PWR_LMT_TABLE15 0xD328
#define R_AX_PWR_LMT_TABLE15_C1 0xF328
#define B_AX_TXAGC_MAX_2TX_BF_BW40_0_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW40_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW40_0_SH 15
#define B_AX_TXAGC_MAX_2TX_BW40_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW20_7_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW20_7_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW20_7_SH 0
#define B_AX_TXAGC_MAX_2TX_BW20_7_MSK 0x7f
#define R_AX_PWR_LMT_TABLE16 0xD32C
#define R_AX_PWR_LMT_TABLE16_C1 0xF32C
#define B_AX_TXAGC_MAX_2TX_BF_BW40_2_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW40_2_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW40_2_SH 15
#define B_AX_TXAGC_MAX_2TX_BW40_2_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW40_1_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW40_1_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW40_1_SH 0
#define B_AX_TXAGC_MAX_2TX_BW40_1_MSK 0x7f
#define R_AX_PWR_LMT_TABLE17 0xD330
#define R_AX_PWR_LMT_TABLE17_C1 0xF330
#define B_AX_TXAGC_MAX_2TX_BF_BW80_0_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW80_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW80_0_SH 15
#define B_AX_TXAGC_MAX_2TX_BW80_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW40_3_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW40_3_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW40_3_SH 0
#define B_AX_TXAGC_MAX_2TX_BW40_3_MSK 0x7f
#define R_AX_PWR_LMT_TABLE18 0xD334
#define R_AX_PWR_LMT_TABLE18_C1 0xF334
#define B_AX_TXAGC_MAX_2TX_BF_BW160_0_SH 24
#define B_AX_TXAGC_MAX_2TX_BF_BW160_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BW160_0_SH 15
#define B_AX_TXAGC_MAX_2TX_BW160_0_MSK 0x7f
#define B_AX_TXAGC_MAX_2TX_BF_BW80_1_SH 8
#define B_AX_TXAGC_MAX_2TX_BF_BW80_1_MSK 0x3f
#define B_AX_TXAGC_MAX_2TX_BW80_1_SH 0
#define B_AX_TXAGC_MAX_2TX_BW80_1_MSK 0x7f
#define R_AX_PWR_LMT_TABLE19 0xD338
#define R_AX_PWR_LMT_TABLE19_C1 0xF338
#define R_AX_PWR_RU_LMT_TABLE0 0xD33C
#define R_AX_PWR_RU_LMT_TABLE0_C1 0xF33C
#define B_AX_TXAGC_RU_1TX_RFBW80_0_SH 24
#define B_AX_TXAGC_RU_1TX_RFBW80_0_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW40_1_SH 15
#define B_AX_TXAGC_RU_1TX_RFBW40_1_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW40_0_SH 8
#define B_AX_TXAGC_RU_1TX_RFBW40_0_MSK 0x3f
#define B_AX_TXAGC_RU_1TX_RFBW20_0_SH 0
#define B_AX_TXAGC_RU_1TX_RFBW20_0_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE1 0xD340
#define R_AX_PWR_RU_LMT_TABLE1_C1 0xF340
#define B_AX_TXAGC_RU_1TX_RFBW160_0_SH 24
#define B_AX_TXAGC_RU_1TX_RFBW160_0_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW80_3_SH 15
#define B_AX_TXAGC_RU_1TX_RFBW80_3_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW80_2_SH 8
#define B_AX_TXAGC_RU_1TX_RFBW80_2_MSK 0x3f
#define B_AX_TXAGC_RU_1TX_RFBW80_1_SH 0
#define B_AX_TXAGC_RU_1TX_RFBW80_1_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE2 0xD344
#define R_AX_PWR_RU_LMT_TABLE2_C1 0xF344
#define B_AX_TXAGC_RU_1TX_RFBW160_4_SH 24
#define B_AX_TXAGC_RU_1TX_RFBW160_4_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW160_3_SH 15
#define B_AX_TXAGC_RU_1TX_RFBW160_3_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW160_2_SH 8
#define B_AX_TXAGC_RU_1TX_RFBW160_2_MSK 0x3f
#define B_AX_TXAGC_RU_1TX_RFBW160_1_SH 0
#define B_AX_TXAGC_RU_1TX_RFBW160_1_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE3 0xD348
#define R_AX_PWR_RU_LMT_TABLE3_C1 0xF348
#define B_AX_TXAGC_RU_2TX_RFBW20_0_SH 24
#define B_AX_TXAGC_RU_2TX_RFBW20_0_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW160_7_SH 15
#define B_AX_TXAGC_RU_1TX_RFBW160_7_MSK 0x7f
#define B_AX_TXAGC_RU_1TX_RFBW160_6_SH 8
#define B_AX_TXAGC_RU_1TX_RFBW160_6_MSK 0x3f
#define B_AX_TXAGC_RU_1TX_RFBW160_5_SH 0
#define B_AX_TXAGC_RU_1TX_RFBW160_5_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE4 0xD34C
#define R_AX_PWR_RU_LMT_TABLE4_C1 0xF34C
#define B_AX_TXAGC_RU_2TX_RFBW80_2_SH 24
#define B_AX_TXAGC_RU_2TX_RFBW80_2_MSK 0x7f
#define B_AX_TXAGC_RU_2TX_RFBW80_1_SH 15
#define B_AX_TXAGC_RU_2TX_RFBW80_1_MSK 0x7f
#define B_AX_TXAGC_RU_2TX_RFBW80_0_SH 8
#define B_AX_TXAGC_RU_2TX_RFBW80_0_MSK 0x3f
#define B_AX_TXAGC_RU_2TX_RFBW40_1_SH 0
#define B_AX_TXAGC_RU_2TX_RFBW40_1_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE5 0xD350
#define R_AX_PWR_RU_LMT_TABLE5_C1 0xF350
#define B_AX_TXAGC_RU_2TX_RFBW160_2_SH 24
#define B_AX_TXAGC_RU_2TX_RFBW160_2_MSK 0x7f
#define B_AX_TXAGC_RU_2TX_RFBW160_1_SH 15
#define B_AX_TXAGC_RU_2TX_RFBW160_1_MSK 0x7f
#define B_AX_TXAGC_RU_2TX_RFBW160_0_SH 8
#define B_AX_TXAGC_RU_2TX_RFBW160_0_MSK 0x3f
#define B_AX_TXAGC_RU_2TX_RFBW80_3_SH 0
#define B_AX_TXAGC_RU_2TX_RFBW80_3_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE6 0xD354
#define R_AX_PWR_RU_LMT_TABLE6_C1 0xF354
#define B_AX_TXAGC_RU_2TX_RFBW160_6_SH 24
#define B_AX_TXAGC_RU_2TX_RFBW160_6_MSK 0x7f
#define B_AX_TXAGC_RU_2TX_RFBW160_5_SH 15
#define B_AX_TXAGC_RU_2TX_RFBW160_5_MSK 0x7f
#define B_AX_TXAGC_RU_2TX_RFBW160_4_SH 8
#define B_AX_TXAGC_RU_2TX_RFBW160_4_MSK 0x3f
#define B_AX_TXAGC_RU_2TX_RFBW160_3_SH 0
#define B_AX_TXAGC_RU_2TX_RFBW160_3_MSK 0x7f
#define R_AX_PWR_RU_LMT_TABLE7 0xD358
#define R_AX_PWR_RU_LMT_TABLE7_C1 0xF358
#define B_AX_TXAGC_RU_2TX_RFBW160_7_SH 0
#define B_AX_TXAGC_RU_2TX_RFBW160_7_MSK 0x7f
#define R_AX_PWR_MACID_TABLE0 0xD35C
#define R_AX_PWR_MACID_TABLE0_C1 0xF35C
#define B_AX_MACID_0_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_0_TXPWR1_EN BIT(25)
#define B_AX_MACID_0_TXPWR0_EN BIT(24)
#define B_AX_MACID_0_CCA_PWR_TH_SH 16
#define B_AX_MACID_0_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_0_TXPWR1_SH 8
#define B_AX_MACID_0_TXPWR1_MSK 0xff
#define B_AX_MACID_0_TXPWR0_SH 0
#define B_AX_MACID_0_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE1 0xD360
#define R_AX_PWR_MACID_TABLE1_C1 0xF360
#define B_AX_MACID_1_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_1_TXPWR1_EN BIT(25)
#define B_AX_MACID_1_TXPWR0_EN BIT(24)
#define B_AX_MACID_1_CCA_PWR_TH_SH 16
#define B_AX_MACID_1_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_1_TXPWR1_SH 8
#define B_AX_MACID_1_TXPWR1_MSK 0xff
#define B_AX_MACID_1_TXPWR0_SH 0
#define B_AX_MACID_1_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE2 0xD364
#define R_AX_PWR_MACID_TABLE2_C1 0xF364
#define B_AX_MACID_2_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_2_TXPWR1_EN BIT(25)
#define B_AX_MACID_2_TXPWR0_EN BIT(24)
#define B_AX_MACID_2_CCA_PWR_TH_SH 16
#define B_AX_MACID_2_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_2_TXPWR1_SH 8
#define B_AX_MACID_2_TXPWR1_MSK 0xff
#define B_AX_MACID_2_TXPWR0_SH 0
#define B_AX_MACID_2_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE3 0xD368
#define R_AX_PWR_MACID_TABLE3_C1 0xF368
#define B_AX_MACID_3_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_3_TXPWR1_EN BIT(25)
#define B_AX_MACID_3_TXPWR0_EN BIT(24)
#define B_AX_MACID_3_CCA_PWR_TH_SH 16
#define B_AX_MACID_3_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_3_TXPWR1_SH 8
#define B_AX_MACID_3_TXPWR1_MSK 0xff
#define B_AX_MACID_3_TXPWR0_SH 0
#define B_AX_MACID_3_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE4 0xD36C
#define R_AX_PWR_MACID_TABLE4_C1 0xF36C
#define B_AX_MACID_4_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_4_TXPWR1_EN BIT(25)
#define B_AX_MACID_4_TXPWR0_EN BIT(24)
#define B_AX_MACID_4_CCA_PWR_TH_SH 16
#define B_AX_MACID_4_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_4_TXPWR1_SH 8
#define B_AX_MACID_4_TXPWR1_MSK 0xff
#define B_AX_MACID_4_TXPWR0_SH 0
#define B_AX_MACID_4_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE5 0xD370
#define R_AX_PWR_MACID_TABLE5_C1 0xF370
#define B_AX_MACID_5_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_5_TXPWR1_EN BIT(25)
#define B_AX_MACID_5_TXPWR0_EN BIT(24)
#define B_AX_MACID_5_CCA_PWR_TH_SH 16
#define B_AX_MACID_5_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_5_TXPWR1_SH 8
#define B_AX_MACID_5_TXPWR1_MSK 0xff
#define B_AX_MACID_5_TXPWR0_SH 0
#define B_AX_MACID_5_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE6 0xD374
#define R_AX_PWR_MACID_TABLE6_C1 0xF374
#define B_AX_MACID_6_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_6_TXPWR1_EN BIT(25)
#define B_AX_MACID_6_TXPWR0_EN BIT(24)
#define B_AX_MACID_6_CCA_PWR_TH_SH 16
#define B_AX_MACID_6_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_6_TXPWR1_SH 8
#define B_AX_MACID_6_TXPWR1_MSK 0xff
#define B_AX_MACID_6_TXPWR0_SH 0
#define B_AX_MACID_6_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE7 0xD378
#define R_AX_PWR_MACID_TABLE7_C1 0xF378
#define B_AX_MACID_7_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_7_TXPWR1_EN BIT(25)
#define B_AX_MACID_7_TXPWR0_EN BIT(24)
#define B_AX_MACID_7_CCA_PWR_TH_SH 16
#define B_AX_MACID_7_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_7_TXPWR1_SH 8
#define B_AX_MACID_7_TXPWR1_MSK 0xff
#define B_AX_MACID_7_TXPWR0_SH 0
#define B_AX_MACID_7_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE8 0xD37C
#define R_AX_PWR_MACID_TABLE8_C1 0xF37C
#define B_AX_MACID_8_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_8_TXPWR1_EN BIT(25)
#define B_AX_MACID_8_TXPWR0_EN BIT(24)
#define B_AX_MACID_8_CCA_PWR_TH_SH 16
#define B_AX_MACID_8_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_8_TXPWR1_SH 8
#define B_AX_MACID_8_TXPWR1_MSK 0xff
#define B_AX_MACID_8_TXPWR0_SH 0
#define B_AX_MACID_8_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE9 0xD380
#define R_AX_PWR_MACID_TABLE9_C1 0xF380
#define B_AX_MACID_9_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_9_TXPWR1_EN BIT(25)
#define B_AX_MACID_9_TXPWR0_EN BIT(24)
#define B_AX_MACID_9_CCA_PWR_TH_SH 16
#define B_AX_MACID_9_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_9_TXPWR1_SH 8
#define B_AX_MACID_9_TXPWR1_MSK 0xff
#define B_AX_MACID_9_TXPWR0_SH 0
#define B_AX_MACID_9_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE10 0xD384
#define R_AX_PWR_MACID_TABLE10_C1 0xF384
#define B_AX_MACID_10_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_10_TXPWR1_EN BIT(25)
#define B_AX_MACID_10_TXPWR0_EN BIT(24)
#define B_AX_MACID_10_CCA_PWR_TH_SH 16
#define B_AX_MACID_10_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_10_TXPWR1_SH 8
#define B_AX_MACID_10_TXPWR1_MSK 0xff
#define B_AX_MACID_10_TXPWR0_SH 0
#define B_AX_MACID_10_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE11 0xD388
#define R_AX_PWR_MACID_TABLE11_C1 0xF388
#define B_AX_MACID_11_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_11_TXPWR1_EN BIT(25)
#define B_AX_MACID_11_TXPWR0_EN BIT(24)
#define B_AX_MACID_11_CCA_PWR_TH_SH 16
#define B_AX_MACID_11_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_11_TXPWR1_SH 8
#define B_AX_MACID_11_TXPWR1_MSK 0xff
#define B_AX_MACID_11_TXPWR0_SH 0
#define B_AX_MACID_11_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE12 0xD38C
#define R_AX_PWR_MACID_TABLE12_C1 0xF38C
#define B_AX_MACID_12_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_12_TXPWR1_EN BIT(25)
#define B_AX_MACID_12_TXPWR0_EN BIT(24)
#define B_AX_MACID_12_CCA_PWR_TH_SH 16
#define B_AX_MACID_12_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_12_TXPWR1_SH 8
#define B_AX_MACID_12_TXPWR1_MSK 0xff
#define B_AX_MACID_12_TXPWR0_SH 0
#define B_AX_MACID_12_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE13 0xD390
#define R_AX_PWR_MACID_TABLE13_C1 0xF390
#define B_AX_MACID_13_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_13_TXPWR1_EN BIT(25)
#define B_AX_MACID_13_TXPWR0_EN BIT(24)
#define B_AX_MACID_13_CCA_PWR_TH_SH 16
#define B_AX_MACID_13_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_13_TXPWR1_SH 8
#define B_AX_MACID_13_TXPWR1_MSK 0xff
#define B_AX_MACID_13_TXPWR0_SH 0
#define B_AX_MACID_13_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE14 0xD394
#define R_AX_PWR_MACID_TABLE14_C1 0xF394
#define B_AX_MACID_14_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_14_TXPWR1_EN BIT(25)
#define B_AX_MACID_14_TXPWR0_EN BIT(24)
#define B_AX_MACID_14_CCA_PWR_TH_SH 16
#define B_AX_MACID_14_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_14_TXPWR1_SH 8
#define B_AX_MACID_14_TXPWR1_MSK 0xff
#define B_AX_MACID_14_TXPWR0_SH 0
#define B_AX_MACID_14_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE15 0xD398
#define R_AX_PWR_MACID_TABLE15_C1 0xF398
#define B_AX_MACID_15_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_15_TXPWR1_EN BIT(25)
#define B_AX_MACID_15_TXPWR0_EN BIT(24)
#define B_AX_MACID_15_CCA_PWR_TH_SH 16
#define B_AX_MACID_15_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_15_TXPWR1_SH 8
#define B_AX_MACID_15_TXPWR1_MSK 0xff
#define B_AX_MACID_15_TXPWR0_SH 0
#define B_AX_MACID_15_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE16 0xD39C
#define R_AX_PWR_MACID_TABLE16_C1 0xF39C
#define B_AX_MACID_16_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_16_TXPWR1_EN BIT(25)
#define B_AX_MACID_16_TXPWR0_EN BIT(24)
#define B_AX_MACID_16_CCA_PWR_TH_SH 16
#define B_AX_MACID_16_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_16_TXPWR1_SH 8
#define B_AX_MACID_16_TXPWR1_MSK 0xff
#define B_AX_MACID_16_TXPWR0_SH 0
#define B_AX_MACID_16_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE17 0xD3A0
#define R_AX_PWR_MACID_TABLE17_C1 0xF3A0
#define B_AX_MACID_17_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_17_TXPWR1_EN BIT(25)
#define B_AX_MACID_17_TXPWR0_EN BIT(24)
#define B_AX_MACID_17_CCA_PWR_TH_SH 16
#define B_AX_MACID_17_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_17_TXPWR1_SH 8
#define B_AX_MACID_17_TXPWR1_MSK 0xff
#define B_AX_MACID_17_TXPWR0_SH 0
#define B_AX_MACID_17_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE18 0xD3A4
#define R_AX_PWR_MACID_TABLE18_C1 0xF3A4
#define B_AX_MACID_18_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_18_TXPWR1_EN BIT(25)
#define B_AX_MACID_18_TXPWR0_EN BIT(24)
#define B_AX_MACID_18_CCA_PWR_TH_SH 16
#define B_AX_MACID_18_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_18_TXPWR1_SH 8
#define B_AX_MACID_18_TXPWR1_MSK 0xff
#define B_AX_MACID_18_TXPWR0_SH 0
#define B_AX_MACID_18_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE19 0xD3A8
#define R_AX_PWR_MACID_TABLE19_C1 0xF3A8
#define B_AX_MACID_19_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_19_TXPWR1_EN BIT(25)
#define B_AX_MACID_19_TXPWR0_EN BIT(24)
#define B_AX_MACID_19_CCA_PWR_TH_SH 16
#define B_AX_MACID_19_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_19_TXPWR1_SH 8
#define B_AX_MACID_19_TXPWR1_MSK 0xff
#define B_AX_MACID_19_TXPWR0_SH 0
#define B_AX_MACID_19_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE20 0xD3AC
#define R_AX_PWR_MACID_TABLE20_C1 0xF3AC
#define B_AX_MACID_20_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_20_TXPWR1_EN BIT(25)
#define B_AX_MACID_20_TXPWR0_EN BIT(24)
#define B_AX_MACID_20_CCA_PWR_TH_SH 16
#define B_AX_MACID_20_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_20_TXPWR1_SH 8
#define B_AX_MACID_20_TXPWR1_MSK 0xff
#define B_AX_MACID_20_TXPWR0_SH 0
#define B_AX_MACID_20_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE21 0xD3B0
#define R_AX_PWR_MACID_TABLE21_C1 0xF3B0
#define B_AX_MACID_21_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_21_TXPWR1_EN BIT(25)
#define B_AX_MACID_21_TXPWR0_EN BIT(24)
#define B_AX_MACID_21_CCA_PWR_TH_SH 16
#define B_AX_MACID_21_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_21_TXPWR1_SH 8
#define B_AX_MACID_21_TXPWR1_MSK 0xff
#define B_AX_MACID_21_TXPWR0_SH 0
#define B_AX_MACID_21_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE22 0xD3B4
#define R_AX_PWR_MACID_TABLE22_C1 0xF3B4
#define B_AX_MACID_22_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_22_TXPWR1_EN BIT(25)
#define B_AX_MACID_22_TXPWR0_EN BIT(24)
#define B_AX_MACID_22_CCA_PWR_TH_SH 16
#define B_AX_MACID_22_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_22_TXPWR1_SH 8
#define B_AX_MACID_22_TXPWR1_MSK 0xff
#define B_AX_MACID_22_TXPWR0_SH 0
#define B_AX_MACID_22_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE23 0xD3B8
#define R_AX_PWR_MACID_TABLE23_C1 0xF3B8
#define B_AX_MACID_23_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_23_TXPWR1_EN BIT(25)
#define B_AX_MACID_23_TXPWR0_EN BIT(24)
#define B_AX_MACID_23_CCA_PWR_TH_SH 16
#define B_AX_MACID_23_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_23_TXPWR1_SH 8
#define B_AX_MACID_23_TXPWR1_MSK 0xff
#define B_AX_MACID_23_TXPWR0_SH 0
#define B_AX_MACID_23_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE24 0xD3BC
#define R_AX_PWR_MACID_TABLE24_C1 0xF3BC
#define B_AX_MACID_24_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_24_TXPWR1_EN BIT(25)
#define B_AX_MACID_24_TXPWR0_EN BIT(24)
#define B_AX_MACID_24_CCA_PWR_TH_SH 16
#define B_AX_MACID_24_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_24_TXPWR1_SH 8
#define B_AX_MACID_24_TXPWR1_MSK 0xff
#define B_AX_MACID_24_TXPWR0_SH 0
#define B_AX_MACID_24_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE25 0xD3C0
#define R_AX_PWR_MACID_TABLE25_C1 0xF3C0
#define B_AX_MACID_25_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_25_TXPWR1_EN BIT(25)
#define B_AX_MACID_25_TXPWR0_EN BIT(24)
#define B_AX_MACID_25_CCA_PWR_TH_SH 16
#define B_AX_MACID_25_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_25_TXPWR1_SH 8
#define B_AX_MACID_25_TXPWR1_MSK 0xff
#define B_AX_MACID_25_TXPWR0_SH 0
#define B_AX_MACID_25_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE26 0xD3C4
#define R_AX_PWR_MACID_TABLE26_C1 0xF3C4
#define B_AX_MACID_26_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_26_TXPWR1_EN BIT(25)
#define B_AX_MACID_26_TXPWR0_EN BIT(24)
#define B_AX_MACID_26_CCA_PWR_TH_SH 16
#define B_AX_MACID_26_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_26_TXPWR1_SH 8
#define B_AX_MACID_26_TXPWR1_MSK 0xff
#define B_AX_MACID_26_TXPWR0_SH 0
#define B_AX_MACID_26_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE27 0xD3C8
#define R_AX_PWR_MACID_TABLE27_C1 0xF3C8
#define B_AX_MACID_27_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_27_TXPWR1_EN BIT(25)
#define B_AX_MACID_27_TXPWR0_EN BIT(24)
#define B_AX_MACID_27_CCA_PWR_TH_SH 16
#define B_AX_MACID_27_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_27_TXPWR1_SH 8
#define B_AX_MACID_27_TXPWR1_MSK 0xff
#define B_AX_MACID_27_TXPWR0_SH 0
#define B_AX_MACID_27_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE28 0xD3CC
#define R_AX_PWR_MACID_TABLE28_C1 0xF3CC
#define B_AX_MACID_28_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_28_TXPWR1_EN BIT(25)
#define B_AX_MACID_28_TXPWR0_EN BIT(24)
#define B_AX_MACID_28_CCA_PWR_TH_SH 16
#define B_AX_MACID_28_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_28_TXPWR1_SH 8
#define B_AX_MACID_28_TXPWR1_MSK 0xff
#define B_AX_MACID_28_TXPWR0_SH 0
#define B_AX_MACID_28_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE29 0xD3D0
#define R_AX_PWR_MACID_TABLE29_C1 0xF3D0
#define B_AX_MACID_29_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_29_TXPWR1_EN BIT(25)
#define B_AX_MACID_29_TXPWR0_EN BIT(24)
#define B_AX_MACID_29_CCA_PWR_TH_SH 16
#define B_AX_MACID_29_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_29_TXPWR1_SH 8
#define B_AX_MACID_29_TXPWR1_MSK 0xff
#define B_AX_MACID_29_TXPWR0_SH 0
#define B_AX_MACID_29_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE30 0xD3D4
#define R_AX_PWR_MACID_TABLE30_C1 0xF3D4
#define B_AX_MACID_30_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_30_TXPWR1_EN BIT(25)
#define B_AX_MACID_30_TXPWR0_EN BIT(24)
#define B_AX_MACID_30_CCA_PWR_TH_SH 16
#define B_AX_MACID_30_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_30_TXPWR1_SH 8
#define B_AX_MACID_30_TXPWR1_MSK 0xff
#define B_AX_MACID_30_TXPWR0_SH 0
#define B_AX_MACID_30_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE31 0xD3D8
#define R_AX_PWR_MACID_TABLE31_C1 0xF3D8
#define B_AX_MACID_31_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_31_TXPWR1_EN BIT(25)
#define B_AX_MACID_31_TXPWR0_EN BIT(24)
#define B_AX_MACID_31_CCA_PWR_TH_SH 16
#define B_AX_MACID_31_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_31_TXPWR1_SH 8
#define B_AX_MACID_31_TXPWR1_MSK 0xff
#define B_AX_MACID_31_TXPWR0_SH 0
#define B_AX_MACID_31_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE32 0xD3DC
#define R_AX_PWR_MACID_TABLE32_C1 0xF3DC
#define B_AX_MACID_32_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_32_TXPWR1_EN BIT(25)
#define B_AX_MACID_32_TXPWR0_EN BIT(24)
#define B_AX_MACID_32_CCA_PWR_TH_SH 16
#define B_AX_MACID_32_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_32_TXPWR1_SH 8
#define B_AX_MACID_32_TXPWR1_MSK 0xff
#define B_AX_MACID_32_TXPWR0_SH 0
#define B_AX_MACID_32_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE33 0xD3E0
#define R_AX_PWR_MACID_TABLE33_C1 0xF3E0
#define B_AX_MACID_33_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_33_TXPWR1_EN BIT(25)
#define B_AX_MACID_33_TXPWR0_EN BIT(24)
#define B_AX_MACID_33_CCA_PWR_TH_SH 16
#define B_AX_MACID_33_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_33_TXPWR1_SH 8
#define B_AX_MACID_33_TXPWR1_MSK 0xff
#define B_AX_MACID_33_TXPWR0_SH 0
#define B_AX_MACID_33_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE34 0xD3E4
#define R_AX_PWR_MACID_TABLE34_C1 0xF3E4
#define B_AX_MACID_34_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_34_TXPWR1_EN BIT(25)
#define B_AX_MACID_34_TXPWR0_EN BIT(24)
#define B_AX_MACID_34_CCA_PWR_TH_SH 16
#define B_AX_MACID_34_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_34_TXPWR1_SH 8
#define B_AX_MACID_34_TXPWR1_MSK 0xff
#define B_AX_MACID_34_TXPWR0_SH 0
#define B_AX_MACID_34_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE35 0xD3E8
#define R_AX_PWR_MACID_TABLE35_C1 0xF3E8
#define B_AX_MACID_35_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_35_TXPWR1_EN BIT(25)
#define B_AX_MACID_35_TXPWR0_EN BIT(24)
#define B_AX_MACID_35_CCA_PWR_TH_SH 16
#define B_AX_MACID_35_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_35_TXPWR1_SH 8
#define B_AX_MACID_35_TXPWR1_MSK 0xff
#define B_AX_MACID_35_TXPWR0_SH 0
#define B_AX_MACID_35_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE36 0xD3EC
#define R_AX_PWR_MACID_TABLE36_C1 0xF3EC
#define B_AX_MACID_36_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_36_TXPWR1_EN BIT(25)
#define B_AX_MACID_36_TXPWR0_EN BIT(24)
#define B_AX_MACID_36_CCA_PWR_TH_SH 16
#define B_AX_MACID_36_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_36_TXPWR1_SH 8
#define B_AX_MACID_36_TXPWR1_MSK 0xff
#define B_AX_MACID_36_TXPWR0_SH 0
#define B_AX_MACID_36_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE37 0xD3F0
#define R_AX_PWR_MACID_TABLE37_C1 0xF3F0
#define B_AX_MACID_37_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_37_TXPWR1_EN BIT(25)
#define B_AX_MACID_37_TXPWR0_EN BIT(24)
#define B_AX_MACID_37_CCA_PWR_TH_SH 16
#define B_AX_MACID_37_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_37_TXPWR1_SH 8
#define B_AX_MACID_37_TXPWR1_MSK 0xff
#define B_AX_MACID_37_TXPWR0_SH 0
#define B_AX_MACID_37_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE38 0xD3F4
#define R_AX_PWR_MACID_TABLE38_C1 0xF3F4
#define B_AX_MACID_38_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_38_TXPWR1_EN BIT(25)
#define B_AX_MACID_38_TXPWR0_EN BIT(24)
#define B_AX_MACID_38_CCA_PWR_TH_SH 16
#define B_AX_MACID_38_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_38_TXPWR1_SH 8
#define B_AX_MACID_38_TXPWR1_MSK 0xff
#define B_AX_MACID_38_TXPWR0_SH 0
#define B_AX_MACID_38_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE39 0xD3F8
#define R_AX_PWR_MACID_TABLE39_C1 0xF3F8
#define B_AX_MACID_39_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_39_TXPWR1_EN BIT(25)
#define B_AX_MACID_39_TXPWR0_EN BIT(24)
#define B_AX_MACID_39_CCA_PWR_TH_SH 16
#define B_AX_MACID_39_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_39_TXPWR1_SH 8
#define B_AX_MACID_39_TXPWR1_MSK 0xff
#define B_AX_MACID_39_TXPWR0_SH 0
#define B_AX_MACID_39_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE40 0xD3FC
#define R_AX_PWR_MACID_TABLE40_C1 0xF3FC
#define B_AX_MACID_40_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_40_TXPWR1_EN BIT(25)
#define B_AX_MACID_40_TXPWR0_EN BIT(24)
#define B_AX_MACID_40_CCA_PWR_TH_SH 16
#define B_AX_MACID_40_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_40_TXPWR1_SH 8
#define B_AX_MACID_40_TXPWR1_MSK 0xff
#define B_AX_MACID_40_TXPWR0_SH 0
#define B_AX_MACID_40_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE41 0xD400
#define R_AX_PWR_MACID_TABLE41_C1 0xF400
#define B_AX_MACID_41_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_41_TXPWR1_EN BIT(25)
#define B_AX_MACID_41_TXPWR0_EN BIT(24)
#define B_AX_MACID_41_CCA_PWR_TH_SH 16
#define B_AX_MACID_41_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_41_TXPWR1_SH 8
#define B_AX_MACID_41_TXPWR1_MSK 0xff
#define B_AX_MACID_41_TXPWR0_SH 0
#define B_AX_MACID_41_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE42 0xD404
#define R_AX_PWR_MACID_TABLE42_C1 0xF404
#define B_AX_MACID_42_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_42_TXPWR1_EN BIT(25)
#define B_AX_MACID_42_TXPWR0_EN BIT(24)
#define B_AX_MACID_42_CCA_PWR_TH_SH 16
#define B_AX_MACID_42_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_42_TXPWR1_SH 8
#define B_AX_MACID_42_TXPWR1_MSK 0xff
#define B_AX_MACID_42_TXPWR0_SH 0
#define B_AX_MACID_42_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE43 0xD408
#define R_AX_PWR_MACID_TABLE43_C1 0xF408
#define B_AX_MACID_43_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_43_TXPWR1_EN BIT(25)
#define B_AX_MACID_43_TXPWR0_EN BIT(24)
#define B_AX_MACID_43_CCA_PWR_TH_SH 16
#define B_AX_MACID_43_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_43_TXPWR1_SH 8
#define B_AX_MACID_43_TXPWR1_MSK 0xff
#define B_AX_MACID_43_TXPWR0_SH 0
#define B_AX_MACID_43_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE44 0xD40C
#define R_AX_PWR_MACID_TABLE44_C1 0xF40C
#define B_AX_MACID_44_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_44_TXPWR1_EN BIT(25)
#define B_AX_MACID_44_TXPWR0_EN BIT(24)
#define B_AX_MACID_44_CCA_PWR_TH_SH 16
#define B_AX_MACID_44_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_44_TXPWR1_SH 8
#define B_AX_MACID_44_TXPWR1_MSK 0xff
#define B_AX_MACID_44_TXPWR0_SH 0
#define B_AX_MACID_44_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE45 0xD410
#define R_AX_PWR_MACID_TABLE45_C1 0xF410
#define B_AX_MACID_45_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_45_TXPWR1_EN BIT(25)
#define B_AX_MACID_45_TXPWR0_EN BIT(24)
#define B_AX_MACID_45_CCA_PWR_TH_SH 16
#define B_AX_MACID_45_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_45_TXPWR1_SH 8
#define B_AX_MACID_45_TXPWR1_MSK 0xff
#define B_AX_MACID_45_TXPWR0_SH 0
#define B_AX_MACID_45_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE46 0xD414
#define R_AX_PWR_MACID_TABLE46_C1 0xF414
#define B_AX_MACID_46_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_46_TXPWR1_EN BIT(25)
#define B_AX_MACID_46_TXPWR0_EN BIT(24)
#define B_AX_MACID_46_CCA_PWR_TH_SH 16
#define B_AX_MACID_46_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_46_TXPWR1_SH 8
#define B_AX_MACID_46_TXPWR1_MSK 0xff
#define B_AX_MACID_46_TXPWR0_SH 0
#define B_AX_MACID_46_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE47 0xD418
#define R_AX_PWR_MACID_TABLE47_C1 0xF418
#define B_AX_MACID_47_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_47_TXPWR1_EN BIT(25)
#define B_AX_MACID_47_TXPWR0_EN BIT(24)
#define B_AX_MACID_47_CCA_PWR_TH_SH 16
#define B_AX_MACID_47_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_47_TXPWR1_SH 8
#define B_AX_MACID_47_TXPWR1_MSK 0xff
#define B_AX_MACID_47_TXPWR0_SH 0
#define B_AX_MACID_47_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE48 0xD41C
#define R_AX_PWR_MACID_TABLE48_C1 0xF41C
#define B_AX_MACID_48_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_48_TXPWR1_EN BIT(25)
#define B_AX_MACID_48_TXPWR0_EN BIT(24)
#define B_AX_MACID_48_CCA_PWR_TH_SH 16
#define B_AX_MACID_48_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_48_TXPWR1_SH 8
#define B_AX_MACID_48_TXPWR1_MSK 0xff
#define B_AX_MACID_48_TXPWR0_SH 0
#define B_AX_MACID_48_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE49 0xD420
#define R_AX_PWR_MACID_TABLE49_C1 0xF420
#define B_AX_MACID_49_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_49_TXPWR1_EN BIT(25)
#define B_AX_MACID_49_TXPWR0_EN BIT(24)
#define B_AX_MACID_49_CCA_PWR_TH_SH 16
#define B_AX_MACID_49_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_49_TXPWR1_SH 8
#define B_AX_MACID_49_TXPWR1_MSK 0xff
#define B_AX_MACID_49_TXPWR0_SH 0
#define B_AX_MACID_49_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE50 0xD424
#define R_AX_PWR_MACID_TABLE50_C1 0xF424
#define B_AX_MACID_50_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_50_TXPWR1_EN BIT(25)
#define B_AX_MACID_50_TXPWR0_EN BIT(24)
#define B_AX_MACID_50_CCA_PWR_TH_SH 16
#define B_AX_MACID_50_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_50_TXPWR1_SH 8
#define B_AX_MACID_50_TXPWR1_MSK 0xff
#define B_AX_MACID_50_TXPWR0_SH 0
#define B_AX_MACID_50_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE51 0xD428
#define R_AX_PWR_MACID_TABLE51_C1 0xF428
#define B_AX_MACID_51_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_51_TXPWR1_EN BIT(25)
#define B_AX_MACID_51_TXPWR0_EN BIT(24)
#define B_AX_MACID_51_CCA_PWR_TH_SH 16
#define B_AX_MACID_51_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_51_TXPWR1_SH 8
#define B_AX_MACID_51_TXPWR1_MSK 0xff
#define B_AX_MACID_51_TXPWR0_SH 0
#define B_AX_MACID_51_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE52 0xD42C
#define R_AX_PWR_MACID_TABLE52_C1 0xF42C
#define B_AX_MACID_52_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_52_TXPWR1_EN BIT(25)
#define B_AX_MACID_52_TXPWR0_EN BIT(24)
#define B_AX_MACID_52_CCA_PWR_TH_SH 16
#define B_AX_MACID_52_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_52_TXPWR1_SH 8
#define B_AX_MACID_52_TXPWR1_MSK 0xff
#define B_AX_MACID_52_TXPWR0_SH 0
#define B_AX_MACID_52_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE53 0xD430
#define R_AX_PWR_MACID_TABLE53_C1 0xF430
#define B_AX_MACID_53_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_53_TXPWR1_EN BIT(25)
#define B_AX_MACID_53_TXPWR0_EN BIT(24)
#define B_AX_MACID_53_CCA_PWR_TH_SH 16
#define B_AX_MACID_53_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_53_TXPWR1_SH 8
#define B_AX_MACID_53_TXPWR1_MSK 0xff
#define B_AX_MACID_53_TXPWR0_SH 0
#define B_AX_MACID_53_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE54 0xD434
#define R_AX_PWR_MACID_TABLE54_C1 0xF434
#define B_AX_MACID_54_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_54_TXPWR1_EN BIT(25)
#define B_AX_MACID_54_TXPWR0_EN BIT(24)
#define B_AX_MACID_54_CCA_PWR_TH_SH 16
#define B_AX_MACID_54_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_54_TXPWR1_SH 8
#define B_AX_MACID_54_TXPWR1_MSK 0xff
#define B_AX_MACID_54_TXPWR0_SH 0
#define B_AX_MACID_54_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE55 0xD438
#define R_AX_PWR_MACID_TABLE55_C1 0xF438
#define B_AX_MACID_55_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_55_TXPWR1_EN BIT(25)
#define B_AX_MACID_55_TXPWR0_EN BIT(24)
#define B_AX_MACID_55_CCA_PWR_TH_SH 16
#define B_AX_MACID_55_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_55_TXPWR1_SH 8
#define B_AX_MACID_55_TXPWR1_MSK 0xff
#define B_AX_MACID_55_TXPWR0_SH 0
#define B_AX_MACID_55_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE56 0xD43C
#define R_AX_PWR_MACID_TABLE56_C1 0xF43C
#define B_AX_MACID_56_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_56_TXPWR1_EN BIT(25)
#define B_AX_MACID_56_TXPWR0_EN BIT(24)
#define B_AX_MACID_56_CCA_PWR_TH_SH 16
#define B_AX_MACID_56_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_56_TXPWR1_SH 8
#define B_AX_MACID_56_TXPWR1_MSK 0xff
#define B_AX_MACID_56_TXPWR0_SH 0
#define B_AX_MACID_56_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE57 0xD440
#define R_AX_PWR_MACID_TABLE57_C1 0xF440
#define B_AX_MACID_57_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_57_TXPWR1_EN BIT(25)
#define B_AX_MACID_57_TXPWR0_EN BIT(24)
#define B_AX_MACID_57_CCA_PWR_TH_SH 16
#define B_AX_MACID_57_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_57_TXPWR1_SH 8
#define B_AX_MACID_57_TXPWR1_MSK 0xff
#define B_AX_MACID_57_TXPWR0_SH 0
#define B_AX_MACID_57_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE58 0xD444
#define R_AX_PWR_MACID_TABLE58_C1 0xF444
#define B_AX_MACID_58_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_58_TXPWR1_EN BIT(25)
#define B_AX_MACID_58_TXPWR0_EN BIT(24)
#define B_AX_MACID_58_CCA_PWR_TH_SH 16
#define B_AX_MACID_58_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_58_TXPWR1_SH 8
#define B_AX_MACID_58_TXPWR1_MSK 0xff
#define B_AX_MACID_58_TXPWR0_SH 0
#define B_AX_MACID_58_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE59 0xD448
#define R_AX_PWR_MACID_TABLE59_C1 0xF448
#define B_AX_MACID_59_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_59_TXPWR1_EN BIT(25)
#define B_AX_MACID_59_TXPWR0_EN BIT(24)
#define B_AX_MACID_59_CCA_PWR_TH_SH 16
#define B_AX_MACID_59_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_59_TXPWR1_SH 8
#define B_AX_MACID_59_TXPWR1_MSK 0xff
#define B_AX_MACID_59_TXPWR0_SH 0
#define B_AX_MACID_59_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE60 0xD44C
#define R_AX_PWR_MACID_TABLE60_C1 0xF44C
#define B_AX_MACID_60_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_60_TXPWR1_EN BIT(25)
#define B_AX_MACID_60_TXPWR0_EN BIT(24)
#define B_AX_MACID_60_CCA_PWR_TH_SH 16
#define B_AX_MACID_60_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_60_TXPWR1_SH 8
#define B_AX_MACID_60_TXPWR1_MSK 0xff
#define B_AX_MACID_60_TXPWR0_SH 0
#define B_AX_MACID_60_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE61 0xD450
#define R_AX_PWR_MACID_TABLE61_C1 0xF450
#define B_AX_MACID_61_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_61_TXPWR1_EN BIT(25)
#define B_AX_MACID_61_TXPWR0_EN BIT(24)
#define B_AX_MACID_61_CCA_PWR_TH_SH 16
#define B_AX_MACID_61_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_61_TXPWR1_SH 8
#define B_AX_MACID_61_TXPWR1_MSK 0xff
#define B_AX_MACID_61_TXPWR0_SH 0
#define B_AX_MACID_61_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE62 0xD454
#define R_AX_PWR_MACID_TABLE62_C1 0xF454
#define B_AX_MACID_62_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_62_TXPWR1_EN BIT(25)
#define B_AX_MACID_62_TXPWR0_EN BIT(24)
#define B_AX_MACID_62_CCA_PWR_TH_SH 16
#define B_AX_MACID_62_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_62_TXPWR1_SH 8
#define B_AX_MACID_62_TXPWR1_MSK 0xff
#define B_AX_MACID_62_TXPWR0_SH 0
#define B_AX_MACID_62_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE63 0xD458
#define R_AX_PWR_MACID_TABLE63_C1 0xF458
#define B_AX_MACID_63_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_63_TXPWR1_EN BIT(25)
#define B_AX_MACID_63_TXPWR0_EN BIT(24)
#define B_AX_MACID_63_CCA_PWR_TH_SH 16
#define B_AX_MACID_63_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_63_TXPWR1_SH 8
#define B_AX_MACID_63_TXPWR1_MSK 0xff
#define B_AX_MACID_63_TXPWR0_SH 0
#define B_AX_MACID_63_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE64 0xD45C
#define R_AX_PWR_MACID_TABLE64_C1 0xF45C
#define B_AX_MACID_64_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_64_TXPWR1_EN BIT(25)
#define B_AX_MACID_64_TXPWR0_EN BIT(24)
#define B_AX_MACID_64_CCA_PWR_TH_SH 16
#define B_AX_MACID_64_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_64_TXPWR1_SH 8
#define B_AX_MACID_64_TXPWR1_MSK 0xff
#define B_AX_MACID_64_TXPWR0_SH 0
#define B_AX_MACID_64_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE65 0xD460
#define R_AX_PWR_MACID_TABLE65_C1 0xF460
#define B_AX_MACID_65_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_65_TXPWR1_EN BIT(25)
#define B_AX_MACID_65_TXPWR0_EN BIT(24)
#define B_AX_MACID_65_CCA_PWR_TH_SH 16
#define B_AX_MACID_65_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_65_TXPWR1_SH 8
#define B_AX_MACID_65_TXPWR1_MSK 0xff
#define B_AX_MACID_65_TXPWR0_SH 0
#define B_AX_MACID_65_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE66 0xD464
#define R_AX_PWR_MACID_TABLE66_C1 0xF464
#define B_AX_MACID_66_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_66_TXPWR1_EN BIT(25)
#define B_AX_MACID_66_TXPWR0_EN BIT(24)
#define B_AX_MACID_66_CCA_PWR_TH_SH 16
#define B_AX_MACID_66_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_66_TXPWR1_SH 8
#define B_AX_MACID_66_TXPWR1_MSK 0xff
#define B_AX_MACID_66_TXPWR0_SH 0
#define B_AX_MACID_66_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE67 0xD468
#define R_AX_PWR_MACID_TABLE67_C1 0xF468
#define B_AX_MACID_67_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_67_TXPWR1_EN BIT(25)
#define B_AX_MACID_67_TXPWR0_EN BIT(24)
#define B_AX_MACID_67_CCA_PWR_TH_SH 16
#define B_AX_MACID_67_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_67_TXPWR1_SH 8
#define B_AX_MACID_67_TXPWR1_MSK 0xff
#define B_AX_MACID_67_TXPWR0_SH 0
#define B_AX_MACID_67_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE68 0xD46C
#define R_AX_PWR_MACID_TABLE68_C1 0xF46C
#define B_AX_MACID_68_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_68_TXPWR1_EN BIT(25)
#define B_AX_MACID_68_TXPWR0_EN BIT(24)
#define B_AX_MACID_68_CCA_PWR_TH_SH 16
#define B_AX_MACID_68_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_68_TXPWR1_SH 8
#define B_AX_MACID_68_TXPWR1_MSK 0xff
#define B_AX_MACID_68_TXPWR0_SH 0
#define B_AX_MACID_68_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE69 0xD470
#define R_AX_PWR_MACID_TABLE69_C1 0xF470
#define B_AX_MACID_69_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_69_TXPWR1_EN BIT(25)
#define B_AX_MACID_69_TXPWR0_EN BIT(24)
#define B_AX_MACID_69_CCA_PWR_TH_SH 16
#define B_AX_MACID_69_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_69_TXPWR1_SH 8
#define B_AX_MACID_69_TXPWR1_MSK 0xff
#define B_AX_MACID_69_TXPWR0_SH 0
#define B_AX_MACID_69_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE70 0xD474
#define R_AX_PWR_MACID_TABLE70_C1 0xF474
#define B_AX_MACID_70_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_70_TXPWR1_EN BIT(25)
#define B_AX_MACID_70_TXPWR0_EN BIT(24)
#define B_AX_MACID_70_CCA_PWR_TH_SH 16
#define B_AX_MACID_70_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_70_TXPWR1_SH 8
#define B_AX_MACID_70_TXPWR1_MSK 0xff
#define B_AX_MACID_70_TXPWR0_SH 0
#define B_AX_MACID_70_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE71 0xD478
#define R_AX_PWR_MACID_TABLE71_C1 0xF478
#define B_AX_MACID_71_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_71_TXPWR1_EN BIT(25)
#define B_AX_MACID_71_TXPWR0_EN BIT(24)
#define B_AX_MACID_71_CCA_PWR_TH_SH 16
#define B_AX_MACID_71_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_71_TXPWR1_SH 8
#define B_AX_MACID_71_TXPWR1_MSK 0xff
#define B_AX_MACID_71_TXPWR0_SH 0
#define B_AX_MACID_71_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE72 0xD47C
#define R_AX_PWR_MACID_TABLE72_C1 0xF47C
#define B_AX_MACID_72_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_72_TXPWR1_EN BIT(25)
#define B_AX_MACID_72_TXPWR0_EN BIT(24)
#define B_AX_MACID_72_CCA_PWR_TH_SH 16
#define B_AX_MACID_72_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_72_TXPWR1_SH 8
#define B_AX_MACID_72_TXPWR1_MSK 0xff
#define B_AX_MACID_72_TXPWR0_SH 0
#define B_AX_MACID_72_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE73 0xD480
#define R_AX_PWR_MACID_TABLE73_C1 0xF480
#define B_AX_MACID_73_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_73_TXPWR1_EN BIT(25)
#define B_AX_MACID_73_TXPWR0_EN BIT(24)
#define B_AX_MACID_73_CCA_PWR_TH_SH 16
#define B_AX_MACID_73_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_73_TXPWR1_SH 8
#define B_AX_MACID_73_TXPWR1_MSK 0xff
#define B_AX_MACID_73_TXPWR0_SH 0
#define B_AX_MACID_73_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE74 0xD484
#define R_AX_PWR_MACID_TABLE74_C1 0xF484
#define B_AX_MACID_74_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_74_TXPWR1_EN BIT(25)
#define B_AX_MACID_74_TXPWR0_EN BIT(24)
#define B_AX_MACID_74_CCA_PWR_TH_SH 16
#define B_AX_MACID_74_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_74_TXPWR1_SH 8
#define B_AX_MACID_74_TXPWR1_MSK 0xff
#define B_AX_MACID_74_TXPWR0_SH 0
#define B_AX_MACID_74_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE75 0xD488
#define R_AX_PWR_MACID_TABLE75_C1 0xF488
#define B_AX_MACID_75_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_75_TXPWR1_EN BIT(25)
#define B_AX_MACID_75_TXPWR0_EN BIT(24)
#define B_AX_MACID_75_CCA_PWR_TH_SH 16
#define B_AX_MACID_75_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_75_TXPWR1_SH 8
#define B_AX_MACID_75_TXPWR1_MSK 0xff
#define B_AX_MACID_75_TXPWR0_SH 0
#define B_AX_MACID_75_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE76 0xD48C
#define R_AX_PWR_MACID_TABLE76_C1 0xF48C
#define B_AX_MACID_76_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_76_TXPWR1_EN BIT(25)
#define B_AX_MACID_76_TXPWR0_EN BIT(24)
#define B_AX_MACID_76_CCA_PWR_TH_SH 16
#define B_AX_MACID_76_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_76_TXPWR1_SH 8
#define B_AX_MACID_76_TXPWR1_MSK 0xff
#define B_AX_MACID_76_TXPWR0_SH 0
#define B_AX_MACID_76_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE77 0xD490
#define R_AX_PWR_MACID_TABLE77_C1 0xF490
#define B_AX_MACID_77_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_77_TXPWR1_EN BIT(25)
#define B_AX_MACID_77_TXPWR0_EN BIT(24)
#define B_AX_MACID_77_CCA_PWR_TH_SH 16
#define B_AX_MACID_77_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_77_TXPWR1_SH 8
#define B_AX_MACID_77_TXPWR1_MSK 0xff
#define B_AX_MACID_77_TXPWR0_SH 0
#define B_AX_MACID_77_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE78 0xD494
#define R_AX_PWR_MACID_TABLE78_C1 0xF494
#define B_AX_MACID_78_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_78_TXPWR1_EN BIT(25)
#define B_AX_MACID_78_TXPWR0_EN BIT(24)
#define B_AX_MACID_78_CCA_PWR_TH_SH 16
#define B_AX_MACID_78_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_78_TXPWR1_SH 8
#define B_AX_MACID_78_TXPWR1_MSK 0xff
#define B_AX_MACID_78_TXPWR0_SH 0
#define B_AX_MACID_78_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE79 0xD498
#define R_AX_PWR_MACID_TABLE79_C1 0xF498
#define B_AX_MACID_79_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_79_TXPWR1_EN BIT(25)
#define B_AX_MACID_79_TXPWR0_EN BIT(24)
#define B_AX_MACID_79_CCA_PWR_TH_SH 16
#define B_AX_MACID_79_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_79_TXPWR1_SH 8
#define B_AX_MACID_79_TXPWR1_MSK 0xff
#define B_AX_MACID_79_TXPWR0_SH 0
#define B_AX_MACID_79_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE80 0xD49C
#define R_AX_PWR_MACID_TABLE80_C1 0xF49C
#define B_AX_MACID_80_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_80_TXPWR1_EN BIT(25)
#define B_AX_MACID_80_TXPWR0_EN BIT(24)
#define B_AX_MACID_80_CCA_PWR_TH_SH 16
#define B_AX_MACID_80_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_80_TXPWR1_SH 8
#define B_AX_MACID_80_TXPWR1_MSK 0xff
#define B_AX_MACID_80_TXPWR0_SH 0
#define B_AX_MACID_80_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE81 0xD4A0
#define R_AX_PWR_MACID_TABLE81_C1 0xF4A0
#define B_AX_MACID_81_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_81_TXPWR1_EN BIT(25)
#define B_AX_MACID_81_TXPWR0_EN BIT(24)
#define B_AX_MACID_81_CCA_PWR_TH_SH 16
#define B_AX_MACID_81_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_81_TXPWR1_SH 8
#define B_AX_MACID_81_TXPWR1_MSK 0xff
#define B_AX_MACID_81_TXPWR0_SH 0
#define B_AX_MACID_81_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE82 0xD4A4
#define R_AX_PWR_MACID_TABLE82_C1 0xF4A4
#define B_AX_MACID_82_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_82_TXPWR1_EN BIT(25)
#define B_AX_MACID_82_TXPWR0_EN BIT(24)
#define B_AX_MACID_82_CCA_PWR_TH_SH 16
#define B_AX_MACID_82_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_82_TXPWR1_SH 8
#define B_AX_MACID_82_TXPWR1_MSK 0xff
#define B_AX_MACID_82_TXPWR0_SH 0
#define B_AX_MACID_82_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE83 0xD4A8
#define R_AX_PWR_MACID_TABLE83_C1 0xF4A8
#define B_AX_MACID_83_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_83_TXPWR1_EN BIT(25)
#define B_AX_MACID_83_TXPWR0_EN BIT(24)
#define B_AX_MACID_83_CCA_PWR_TH_SH 16
#define B_AX_MACID_83_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_83_TXPWR1_SH 8
#define B_AX_MACID_83_TXPWR1_MSK 0xff
#define B_AX_MACID_83_TXPWR0_SH 0
#define B_AX_MACID_83_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE84 0xD4AC
#define R_AX_PWR_MACID_TABLE84_C1 0xF4AC
#define B_AX_MACID_84_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_84_TXPWR1_EN BIT(25)
#define B_AX_MACID_84_TXPWR0_EN BIT(24)
#define B_AX_MACID_84_CCA_PWR_TH_SH 16
#define B_AX_MACID_84_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_84_TXPWR1_SH 8
#define B_AX_MACID_84_TXPWR1_MSK 0xff
#define B_AX_MACID_84_TXPWR0_SH 0
#define B_AX_MACID_84_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE85 0xD4B0
#define R_AX_PWR_MACID_TABLE85_C1 0xF4B0
#define B_AX_MACID_85_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_85_TXPWR1_EN BIT(25)
#define B_AX_MACID_85_TXPWR0_EN BIT(24)
#define B_AX_MACID_85_CCA_PWR_TH_SH 16
#define B_AX_MACID_85_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_85_TXPWR1_SH 8
#define B_AX_MACID_85_TXPWR1_MSK 0xff
#define B_AX_MACID_85_TXPWR0_SH 0
#define B_AX_MACID_85_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE86 0xD4B4
#define R_AX_PWR_MACID_TABLE86_C1 0xF4B4
#define B_AX_MACID_86_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_86_TXPWR1_EN BIT(25)
#define B_AX_MACID_86_TXPWR0_EN BIT(24)
#define B_AX_MACID_86_CCA_PWR_TH_SH 16
#define B_AX_MACID_86_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_86_TXPWR1_SH 8
#define B_AX_MACID_86_TXPWR1_MSK 0xff
#define B_AX_MACID_86_TXPWR0_SH 0
#define B_AX_MACID_86_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE87 0xD4B8
#define R_AX_PWR_MACID_TABLE87_C1 0xF4B8
#define B_AX_MACID_87_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_87_TXPWR1_EN BIT(25)
#define B_AX_MACID_87_TXPWR0_EN BIT(24)
#define B_AX_MACID_87_CCA_PWR_TH_SH 16
#define B_AX_MACID_87_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_87_TXPWR1_SH 8
#define B_AX_MACID_87_TXPWR1_MSK 0xff
#define B_AX_MACID_87_TXPWR0_SH 0
#define B_AX_MACID_87_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE88 0xD4BC
#define R_AX_PWR_MACID_TABLE88_C1 0xF4BC
#define B_AX_MACID_88_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_88_TXPWR1_EN BIT(25)
#define B_AX_MACID_88_TXPWR0_EN BIT(24)
#define B_AX_MACID_88_CCA_PWR_TH_SH 16
#define B_AX_MACID_88_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_88_TXPWR1_SH 8
#define B_AX_MACID_88_TXPWR1_MSK 0xff
#define B_AX_MACID_88_TXPWR0_SH 0
#define B_AX_MACID_88_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE89 0xD4C0
#define R_AX_PWR_MACID_TABLE89_C1 0xF4C0
#define B_AX_MACID_89_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_89_TXPWR1_EN BIT(25)
#define B_AX_MACID_89_TXPWR0_EN BIT(24)
#define B_AX_MACID_89_CCA_PWR_TH_SH 16
#define B_AX_MACID_89_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_89_TXPWR1_SH 8
#define B_AX_MACID_89_TXPWR1_MSK 0xff
#define B_AX_MACID_89_TXPWR0_SH 0
#define B_AX_MACID_89_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE90 0xD4C4
#define R_AX_PWR_MACID_TABLE90_C1 0xF4C4
#define B_AX_MACID_90_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_90_TXPWR1_EN BIT(25)
#define B_AX_MACID_90_TXPWR0_EN BIT(24)
#define B_AX_MACID_90_CCA_PWR_TH_SH 16
#define B_AX_MACID_90_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_90_TXPWR1_SH 8
#define B_AX_MACID_90_TXPWR1_MSK 0xff
#define B_AX_MACID_90_TXPWR0_SH 0
#define B_AX_MACID_90_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE91 0xD4C8
#define R_AX_PWR_MACID_TABLE91_C1 0xF4C8
#define B_AX_MACID_91_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_91_TXPWR1_EN BIT(25)
#define B_AX_MACID_91_TXPWR0_EN BIT(24)
#define B_AX_MACID_91_CCA_PWR_TH_SH 16
#define B_AX_MACID_91_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_91_TXPWR1_SH 8
#define B_AX_MACID_91_TXPWR1_MSK 0xff
#define B_AX_MACID_91_TXPWR0_SH 0
#define B_AX_MACID_91_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE92 0xD4CC
#define R_AX_PWR_MACID_TABLE92_C1 0xF4CC
#define B_AX_MACID_92_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_92_TXPWR1_EN BIT(25)
#define B_AX_MACID_92_TXPWR0_EN BIT(24)
#define B_AX_MACID_92_CCA_PWR_TH_SH 16
#define B_AX_MACID_92_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_92_TXPWR1_SH 8
#define B_AX_MACID_92_TXPWR1_MSK 0xff
#define B_AX_MACID_92_TXPWR0_SH 0
#define B_AX_MACID_92_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE93 0xD4D0
#define R_AX_PWR_MACID_TABLE93_C1 0xF4D0
#define B_AX_MACID_93_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_93_TXPWR1_EN BIT(25)
#define B_AX_MACID_93_TXPWR0_EN BIT(24)
#define B_AX_MACID_93_CCA_PWR_TH_SH 16
#define B_AX_MACID_93_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_93_TXPWR1_SH 8
#define B_AX_MACID_93_TXPWR1_MSK 0xff
#define B_AX_MACID_93_TXPWR0_SH 0
#define B_AX_MACID_93_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE94 0xD4D4
#define R_AX_PWR_MACID_TABLE94_C1 0xF4D4
#define B_AX_MACID_94_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_94_TXPWR1_EN BIT(25)
#define B_AX_MACID_94_TXPWR0_EN BIT(24)
#define B_AX_MACID_94_CCA_PWR_TH_SH 16
#define B_AX_MACID_94_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_94_TXPWR1_SH 8
#define B_AX_MACID_94_TXPWR1_MSK 0xff
#define B_AX_MACID_94_TXPWR0_SH 0
#define B_AX_MACID_94_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE95 0xD4D8
#define R_AX_PWR_MACID_TABLE95_C1 0xF4D8
#define B_AX_MACID_95_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_95_TXPWR1_EN BIT(25)
#define B_AX_MACID_95_TXPWR0_EN BIT(24)
#define B_AX_MACID_95_CCA_PWR_TH_SH 16
#define B_AX_MACID_95_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_95_TXPWR1_SH 8
#define B_AX_MACID_95_TXPWR1_MSK 0xff
#define B_AX_MACID_95_TXPWR0_SH 0
#define B_AX_MACID_95_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE96 0xD4DC
#define R_AX_PWR_MACID_TABLE96_C1 0xF4DC
#define B_AX_MACID_96_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_96_TXPWR1_EN BIT(25)
#define B_AX_MACID_96_TXPWR0_EN BIT(24)
#define B_AX_MACID_96_CCA_PWR_TH_SH 16
#define B_AX_MACID_96_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_96_TXPWR1_SH 8
#define B_AX_MACID_96_TXPWR1_MSK 0xff
#define B_AX_MACID_96_TXPWR0_SH 0
#define B_AX_MACID_96_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE97 0xD4E0
#define R_AX_PWR_MACID_TABLE97_C1 0xF4E0
#define B_AX_MACID_97_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_97_TXPWR1_EN BIT(25)
#define B_AX_MACID_97_TXPWR0_EN BIT(24)
#define B_AX_MACID_97_CCA_PWR_TH_SH 16
#define B_AX_MACID_97_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_97_TXPWR1_SH 8
#define B_AX_MACID_97_TXPWR1_MSK 0xff
#define B_AX_MACID_97_TXPWR0_SH 0
#define B_AX_MACID_97_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE98 0xD4E4
#define R_AX_PWR_MACID_TABLE98_C1 0xF4E4
#define B_AX_MACID_98_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_98_TXPWR1_EN BIT(25)
#define B_AX_MACID_98_TXPWR0_EN BIT(24)
#define B_AX_MACID_98_CCA_PWR_TH_SH 16
#define B_AX_MACID_98_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_98_TXPWR1_SH 8
#define B_AX_MACID_98_TXPWR1_MSK 0xff
#define B_AX_MACID_98_TXPWR0_SH 0
#define B_AX_MACID_98_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE99 0xD4E8
#define R_AX_PWR_MACID_TABLE99_C1 0xF4E8
#define B_AX_MACID_99_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_99_TXPWR1_EN BIT(25)
#define B_AX_MACID_99_TXPWR0_EN BIT(24)
#define B_AX_MACID_99_CCA_PWR_TH_SH 16
#define B_AX_MACID_99_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_99_TXPWR1_SH 8
#define B_AX_MACID_99_TXPWR1_MSK 0xff
#define B_AX_MACID_99_TXPWR0_SH 0
#define B_AX_MACID_99_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE100 0xD4EC
#define R_AX_PWR_MACID_TABLE100_C1 0xF4EC
#define B_AX_MACID_100_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_100_TXPWR1_EN BIT(25)
#define B_AX_MACID_100_TXPWR0_EN BIT(24)
#define B_AX_MACID_100_CCA_PWR_TH_SH 16
#define B_AX_MACID_100_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_100_TXPWR1_SH 8
#define B_AX_MACID_100_TXPWR1_MSK 0xff
#define B_AX_MACID_100_TXPWR0_SH 0
#define B_AX_MACID_100_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE101 0xD4F0
#define R_AX_PWR_MACID_TABLE101_C1 0xF4F0
#define B_AX_MACID_101_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_101_TXPWR1_EN BIT(25)
#define B_AX_MACID_101_TXPWR0_EN BIT(24)
#define B_AX_MACID_101_CCA_PWR_TH_SH 16
#define B_AX_MACID_101_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_101_TXPWR1_SH 8
#define B_AX_MACID_101_TXPWR1_MSK 0xff
#define B_AX_MACID_101_TXPWR0_SH 0
#define B_AX_MACID_101_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE102 0xD4F4
#define R_AX_PWR_MACID_TABLE102_C1 0xF4F4
#define B_AX_MACID_102_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_102_TXPWR1_EN BIT(25)
#define B_AX_MACID_102_TXPWR0_EN BIT(24)
#define B_AX_MACID_102_CCA_PWR_TH_SH 16
#define B_AX_MACID_102_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_102_TXPWR1_SH 8
#define B_AX_MACID_102_TXPWR1_MSK 0xff
#define B_AX_MACID_102_TXPWR0_SH 0
#define B_AX_MACID_102_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE103 0xD4F8
#define R_AX_PWR_MACID_TABLE103_C1 0xF4F8
#define B_AX_MACID_103_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_103_TXPWR1_EN BIT(25)
#define B_AX_MACID_103_TXPWR0_EN BIT(24)
#define B_AX_MACID_103_CCA_PWR_TH_SH 16
#define B_AX_MACID_103_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_103_TXPWR1_SH 8
#define B_AX_MACID_103_TXPWR1_MSK 0xff
#define B_AX_MACID_103_TXPWR0_SH 0
#define B_AX_MACID_103_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE104 0xD4FC
#define R_AX_PWR_MACID_TABLE104_C1 0xF4FC
#define B_AX_MACID_104_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_104_TXPWR1_EN BIT(25)
#define B_AX_MACID_104_TXPWR0_EN BIT(24)
#define B_AX_MACID_104_CCA_PWR_TH_SH 16
#define B_AX_MACID_104_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_104_TXPWR1_SH 8
#define B_AX_MACID_104_TXPWR1_MSK 0xff
#define B_AX_MACID_104_TXPWR0_SH 0
#define B_AX_MACID_104_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE105 0xD500
#define R_AX_PWR_MACID_TABLE105_C1 0xF500
#define B_AX_MACID_105_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_105_TXPWR1_EN BIT(25)
#define B_AX_MACID_105_TXPWR0_EN BIT(24)
#define B_AX_MACID_105_CCA_PWR_TH_SH 16
#define B_AX_MACID_105_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_105_TXPWR1_SH 8
#define B_AX_MACID_105_TXPWR1_MSK 0xff
#define B_AX_MACID_105_TXPWR0_SH 0
#define B_AX_MACID_105_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE106 0xD504
#define R_AX_PWR_MACID_TABLE106_C1 0xF504
#define B_AX_MACID_106_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_106_TXPWR1_EN BIT(25)
#define B_AX_MACID_106_TXPWR0_EN BIT(24)
#define B_AX_MACID_106_CCA_PWR_TH_SH 16
#define B_AX_MACID_106_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_106_TXPWR1_SH 8
#define B_AX_MACID_106_TXPWR1_MSK 0xff
#define B_AX_MACID_106_TXPWR0_SH 0
#define B_AX_MACID_106_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE107 0xD508
#define R_AX_PWR_MACID_TABLE107_C1 0xF508
#define B_AX_MACID_107_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_107_TXPWR1_EN BIT(25)
#define B_AX_MACID_107_TXPWR0_EN BIT(24)
#define B_AX_MACID_107_CCA_PWR_TH_SH 16
#define B_AX_MACID_107_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_107_TXPWR1_SH 8
#define B_AX_MACID_107_TXPWR1_MSK 0xff
#define B_AX_MACID_107_TXPWR0_SH 0
#define B_AX_MACID_107_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE108 0xD50C
#define R_AX_PWR_MACID_TABLE108_C1 0xF50C
#define B_AX_MACID_108_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_108_TXPWR1_EN BIT(25)
#define B_AX_MACID_108_TXPWR0_EN BIT(24)
#define B_AX_MACID_108_CCA_PWR_TH_SH 16
#define B_AX_MACID_108_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_108_TXPWR1_SH 8
#define B_AX_MACID_108_TXPWR1_MSK 0xff
#define B_AX_MACID_108_TXPWR0_SH 0
#define B_AX_MACID_108_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE109 0xD510
#define R_AX_PWR_MACID_TABLE109_C1 0xF510
#define B_AX_MACID_109_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_109_TXPWR1_EN BIT(25)
#define B_AX_MACID_109_TXPWR0_EN BIT(24)
#define B_AX_MACID_109_CCA_PWR_TH_SH 16
#define B_AX_MACID_109_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_109_TXPWR1_SH 8
#define B_AX_MACID_109_TXPWR1_MSK 0xff
#define B_AX_MACID_109_TXPWR0_SH 0
#define B_AX_MACID_109_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE110 0xD514
#define R_AX_PWR_MACID_TABLE110_C1 0xF514
#define B_AX_MACID_110_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_110_TXPWR1_EN BIT(25)
#define B_AX_MACID_110_TXPWR0_EN BIT(24)
#define B_AX_MACID_110_CCA_PWR_TH_SH 16
#define B_AX_MACID_110_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_110_TXPWR1_SH 8
#define B_AX_MACID_110_TXPWR1_MSK 0xff
#define B_AX_MACID_110_TXPWR0_SH 0
#define B_AX_MACID_110_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE111 0xD518
#define R_AX_PWR_MACID_TABLE111_C1 0xF518
#define B_AX_MACID_111_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_111_TXPWR1_EN BIT(25)
#define B_AX_MACID_111_TXPWR0_EN BIT(24)
#define B_AX_MACID_111_CCA_PWR_TH_SH 16
#define B_AX_MACID_111_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_111_TXPWR1_SH 8
#define B_AX_MACID_111_TXPWR1_MSK 0xff
#define B_AX_MACID_111_TXPWR0_SH 0
#define B_AX_MACID_111_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE112 0xD51C
#define R_AX_PWR_MACID_TABLE112_C1 0xF51C
#define B_AX_MACID_112_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_112_TXPWR1_EN BIT(25)
#define B_AX_MACID_112_TXPWR0_EN BIT(24)
#define B_AX_MACID_112_CCA_PWR_TH_SH 16
#define B_AX_MACID_112_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_112_TXPWR1_SH 8
#define B_AX_MACID_112_TXPWR1_MSK 0xff
#define B_AX_MACID_112_TXPWR0_SH 0
#define B_AX_MACID_112_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE113 0xD520
#define R_AX_PWR_MACID_TABLE113_C1 0xF520
#define B_AX_MACID_113_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_113_TXPWR1_EN BIT(25)
#define B_AX_MACID_113_TXPWR0_EN BIT(24)
#define B_AX_MACID_113_CCA_PWR_TH_SH 16
#define B_AX_MACID_113_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_113_TXPWR1_SH 8
#define B_AX_MACID_113_TXPWR1_MSK 0xff
#define B_AX_MACID_113_TXPWR0_SH 0
#define B_AX_MACID_113_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE114 0xD524
#define R_AX_PWR_MACID_TABLE114_C1 0xF524
#define B_AX_MACID_114_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_114_TXPWR1_EN BIT(25)
#define B_AX_MACID_114_TXPWR0_EN BIT(24)
#define B_AX_MACID_114_CCA_PWR_TH_SH 16
#define B_AX_MACID_114_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_114_TXPWR1_SH 8
#define B_AX_MACID_114_TXPWR1_MSK 0xff
#define B_AX_MACID_114_TXPWR0_SH 0
#define B_AX_MACID_114_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE115 0xD528
#define R_AX_PWR_MACID_TABLE115_C1 0xF528
#define B_AX_MACID_115_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_115_TXPWR1_EN BIT(25)
#define B_AX_MACID_115_TXPWR0_EN BIT(24)
#define B_AX_MACID_115_CCA_PWR_TH_SH 16
#define B_AX_MACID_115_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_115_TXPWR1_SH 8
#define B_AX_MACID_115_TXPWR1_MSK 0xff
#define B_AX_MACID_115_TXPWR0_SH 0
#define B_AX_MACID_115_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE116 0xD52C
#define R_AX_PWR_MACID_TABLE116_C1 0xF52C
#define B_AX_MACID_116_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_116_TXPWR1_EN BIT(25)
#define B_AX_MACID_116_TXPWR0_EN BIT(24)
#define B_AX_MACID_116_CCA_PWR_TH_SH 16
#define B_AX_MACID_116_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_116_TXPWR1_SH 8
#define B_AX_MACID_116_TXPWR1_MSK 0xff
#define B_AX_MACID_116_TXPWR0_SH 0
#define B_AX_MACID_116_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE117 0xD530
#define R_AX_PWR_MACID_TABLE117_C1 0xF530
#define B_AX_MACID_117_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_117_TXPWR1_EN BIT(25)
#define B_AX_MACID_117_TXPWR0_EN BIT(24)
#define B_AX_MACID_117_CCA_PWR_TH_SH 16
#define B_AX_MACID_117_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_117_TXPWR1_SH 8
#define B_AX_MACID_117_TXPWR1_MSK 0xff
#define B_AX_MACID_117_TXPWR0_SH 0
#define B_AX_MACID_117_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE118 0xD534
#define R_AX_PWR_MACID_TABLE118_C1 0xF534
#define B_AX_MACID_118_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_118_TXPWR1_EN BIT(25)
#define B_AX_MACID_118_TXPWR0_EN BIT(24)
#define B_AX_MACID_118_CCA_PWR_TH_SH 16
#define B_AX_MACID_118_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_118_TXPWR1_SH 8
#define B_AX_MACID_118_TXPWR1_MSK 0xff
#define B_AX_MACID_118_TXPWR0_SH 0
#define B_AX_MACID_118_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE119 0xD538
#define R_AX_PWR_MACID_TABLE119_C1 0xF538
#define B_AX_MACID_119_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_119_TXPWR1_EN BIT(25)
#define B_AX_MACID_119_TXPWR0_EN BIT(24)
#define B_AX_MACID_119_CCA_PWR_TH_SH 16
#define B_AX_MACID_119_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_119_TXPWR1_SH 8
#define B_AX_MACID_119_TXPWR1_MSK 0xff
#define B_AX_MACID_119_TXPWR0_SH 0
#define B_AX_MACID_119_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE120 0xD53C
#define R_AX_PWR_MACID_TABLE120_C1 0xF53C
#define B_AX_MACID_120_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_120_TXPWR1_EN BIT(25)
#define B_AX_MACID_120_TXPWR0_EN BIT(24)
#define B_AX_MACID_120_CCA_PWR_TH_SH 16
#define B_AX_MACID_120_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_120_TXPWR1_SH 8
#define B_AX_MACID_120_TXPWR1_MSK 0xff
#define B_AX_MACID_120_TXPWR0_SH 0
#define B_AX_MACID_120_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE121 0xD540
#define R_AX_PWR_MACID_TABLE121_C1 0xF540
#define B_AX_MACID_121_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_121_TXPWR1_EN BIT(25)
#define B_AX_MACID_121_TXPWR0_EN BIT(24)
#define B_AX_MACID_121_CCA_PWR_TH_SH 16
#define B_AX_MACID_121_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_121_TXPWR1_SH 8
#define B_AX_MACID_121_TXPWR1_MSK 0xff
#define B_AX_MACID_121_TXPWR0_SH 0
#define B_AX_MACID_121_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE122 0xD544
#define R_AX_PWR_MACID_TABLE122_C1 0xF544
#define B_AX_MACID_122_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_122_TXPWR1_EN BIT(25)
#define B_AX_MACID_122_TXPWR0_EN BIT(24)
#define B_AX_MACID_122_CCA_PWR_TH_SH 16
#define B_AX_MACID_122_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_122_TXPWR1_SH 8
#define B_AX_MACID_122_TXPWR1_MSK 0xff
#define B_AX_MACID_122_TXPWR0_SH 0
#define B_AX_MACID_122_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE123 0xD548
#define R_AX_PWR_MACID_TABLE123_C1 0xF548
#define B_AX_MACID_123_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_123_TXPWR1_EN BIT(25)
#define B_AX_MACID_123_TXPWR0_EN BIT(24)
#define B_AX_MACID_123_CCA_PWR_TH_SH 16
#define B_AX_MACID_123_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_123_TXPWR1_SH 8
#define B_AX_MACID_123_TXPWR1_MSK 0xff
#define B_AX_MACID_123_TXPWR0_SH 0
#define B_AX_MACID_123_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE124 0xD54C
#define R_AX_PWR_MACID_TABLE124_C1 0xF54C
#define B_AX_MACID_124_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_124_TXPWR1_EN BIT(25)
#define B_AX_MACID_124_TXPWR0_EN BIT(24)
#define B_AX_MACID_124_CCA_PWR_TH_SH 16
#define B_AX_MACID_124_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_124_TXPWR1_SH 8
#define B_AX_MACID_124_TXPWR1_MSK 0xff
#define B_AX_MACID_124_TXPWR0_SH 0
#define B_AX_MACID_124_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE125 0xD550
#define R_AX_PWR_MACID_TABLE125_C1 0xF550
#define B_AX_MACID_125_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_125_TXPWR1_EN BIT(25)
#define B_AX_MACID_125_TXPWR0_EN BIT(24)
#define B_AX_MACID_125_CCA_PWR_TH_SH 16
#define B_AX_MACID_125_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_125_TXPWR1_SH 8
#define B_AX_MACID_125_TXPWR1_MSK 0xff
#define B_AX_MACID_125_TXPWR0_SH 0
#define B_AX_MACID_125_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE126 0xD554
#define R_AX_PWR_MACID_TABLE126_C1 0xF554
#define B_AX_MACID_126_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_126_TXPWR1_EN BIT(25)
#define B_AX_MACID_126_TXPWR0_EN BIT(24)
#define B_AX_MACID_126_CCA_PWR_TH_SH 16
#define B_AX_MACID_126_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_126_TXPWR1_SH 8
#define B_AX_MACID_126_TXPWR1_MSK 0xff
#define B_AX_MACID_126_TXPWR0_SH 0
#define B_AX_MACID_126_TXPWR0_MSK 0xff
#define R_AX_PWR_MACID_TABLE127 0xD558
#define R_AX_PWR_MACID_TABLE127_C1 0xF558
#define B_AX_MACID_127_CCA_PWR_TH_EN BIT(26)
#define B_AX_MACID_127_TXPWR1_EN BIT(25)
#define B_AX_MACID_127_TXPWR0_EN BIT(24)
#define B_AX_MACID_127_CCA_PWR_TH_SH 16
#define B_AX_MACID_127_CCA_PWR_TH_MSK 0xff
#define B_AX_MACID_127_TXPWR1_SH 8
#define B_AX_MACID_127_TXPWR1_MSK 0xff
#define B_AX_MACID_127_TXPWR0_SH 0
#define B_AX_MACID_127_TXPWR0_MSK 0xff
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE0 0xD55C
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE0_C1 0xF55C
#define B_AX_MCS0_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS0_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS0_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS0_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS0_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS0_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE1 0xD560
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE1_C1 0xF560
#define B_AX_MCS0_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS0_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS0_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS0_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS0_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS0_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE2 0xD564
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE2_C1 0xF564
#define B_AX_MCS0_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS0_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS0_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS0_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS0_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS0_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE3 0xD568
#define R_AX_PWR_SR_MCS0_TXDIFF_TABLE3_C1 0xF568
#define B_AX_MCS0_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS0_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS0_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS0_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS0_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS0_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS0_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE0 0xD56C
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE0_C1 0xF56C
#define B_AX_MCS1_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS1_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS1_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS1_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS1_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS1_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE1 0xD570
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE1_C1 0xF570
#define B_AX_MCS1_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS1_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS1_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS1_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS1_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS1_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE2 0xD574
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE2_C1 0xF574
#define B_AX_MCS1_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS1_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS1_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS1_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS1_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS1_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE3 0xD578
#define R_AX_PWR_SR_MCS1_TXDIFF_TABLE3_C1 0xF578
#define B_AX_MCS1_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS1_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS1_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS1_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS1_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS1_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS1_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE0 0xD57C
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE0_C1 0xF57C
#define B_AX_MCS2_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS2_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS2_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS2_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS2_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS2_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE1 0xD580
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE1_C1 0xF580
#define B_AX_MCS2_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS2_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS2_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS2_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS2_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS2_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE2 0xD584
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE2_C1 0xF584
#define B_AX_MCS2_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS2_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS2_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS2_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS2_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS2_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE3 0xD588
#define R_AX_PWR_SR_MCS2_TXDIFF_TABLE3_C1 0xF588
#define B_AX_MCS2_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS2_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS2_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS2_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS2_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS2_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS2_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE0 0xD58C
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE0_C1 0xF58C
#define B_AX_MCS3_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS3_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS3_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS3_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS3_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS3_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE1 0xD590
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE1_C1 0xF590
#define B_AX_MCS3_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS3_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS3_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS3_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS3_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS3_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE2 0xD594
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE2_C1 0xF594
#define B_AX_MCS3_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS3_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS3_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS3_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS3_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS3_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE3 0xD598
#define R_AX_PWR_SR_MCS3_TXDIFF_TABLE3_C1 0xF598
#define B_AX_MCS3_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS3_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS3_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS3_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS3_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS3_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS3_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE0 0xD59C
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE0_C1 0xF59C
#define B_AX_MCS4_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS4_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS4_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS4_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS4_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS4_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE1 0xD5A0
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE1_C1 0xF5A0
#define B_AX_MCS4_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS4_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS4_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS4_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS4_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS4_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE2 0xD5A4
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE2_C1 0xF5A4
#define B_AX_MCS4_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS4_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS4_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS4_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS4_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS4_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE3 0xD5A8
#define R_AX_PWR_SR_MCS4_TXDIFF_TABLE3_C1 0xF5A8
#define B_AX_MCS4_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS4_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS4_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS4_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS4_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS4_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS4_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE0 0xD5AC
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE0_C1 0xF5AC
#define B_AX_MCS5_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS5_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS5_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS5_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS5_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS5_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE1 0xD5B0
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE1_C1 0xF5B0
#define B_AX_MCS5_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS5_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS5_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS5_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS5_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS5_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE2 0xD5B4
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE2_C1 0xF5B4
#define B_AX_MCS5_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS5_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS5_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS5_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS5_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS5_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE3 0xD5B8
#define R_AX_PWR_SR_MCS5_TXDIFF_TABLE3_C1 0xF5B8
#define B_AX_MCS5_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS5_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS5_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS5_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS5_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS5_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS5_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE0 0xD5BC
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE0_C1 0xF5BC
#define B_AX_MCS6_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS6_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS6_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS6_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS6_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS6_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE1 0xD5C0
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE1_C1 0xF5C0
#define B_AX_MCS6_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS6_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS6_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS6_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS6_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS6_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE2 0xD5C4
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE2_C1 0xF5C4
#define B_AX_MCS6_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS6_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS6_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS6_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS6_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS6_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE3 0xD5C8
#define R_AX_PWR_SR_MCS6_TXDIFF_TABLE3_C1 0xF5C8
#define B_AX_MCS6_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS6_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS6_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS6_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS6_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS6_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS6_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE0 0xD5CC
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE0_C1 0xF5CC
#define B_AX_MCS7_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS7_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS7_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS7_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS7_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS7_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE1 0xD5D0
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE1_C1 0xF5D0
#define B_AX_MCS7_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS7_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS7_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS7_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS7_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS7_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE2 0xD5D4
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE2_C1 0xF5D4
#define B_AX_MCS7_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS7_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS7_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS7_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS7_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS7_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE3 0xD5D8
#define R_AX_PWR_SR_MCS7_TXDIFF_TABLE3_C1 0xF5D8
#define B_AX_MCS7_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS7_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS7_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS7_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS7_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS7_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS7_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE0 0xD5DC
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE0_C1 0xF5DC
#define B_AX_MCS8_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS8_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS8_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS8_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS8_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS8_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE1 0xD5E0
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE1_C1 0xF5E0
#define B_AX_MCS8_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS8_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS8_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS8_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS8_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS8_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE2 0xD5E4
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE2_C1 0xF5E4
#define B_AX_MCS8_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS8_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS8_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS8_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS8_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS8_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE3 0xD5E8
#define R_AX_PWR_SR_MCS8_TXDIFF_TABLE3_C1 0xF5E8
#define B_AX_MCS8_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS8_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS8_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS8_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS8_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS8_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS8_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE0 0xD5EC
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE0_C1 0xF5EC
#define B_AX_MCS9_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS9_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS9_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS9_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS9_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS9_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE1 0xD5F0
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE1_C1 0xF5F0
#define B_AX_MCS9_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS9_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS9_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS9_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS9_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS9_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE2 0xD5F4
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE2_C1 0xF5F4
#define B_AX_MCS9_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS9_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS9_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS9_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS9_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS9_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE3 0xD5F8
#define R_AX_PWR_SR_MCS9_TXDIFF_TABLE3_C1 0xF5F8
#define B_AX_MCS9_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS9_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS9_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS9_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS9_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS9_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS9_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE0 0xD5FC
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE0_C1 0xF5FC
#define B_AX_MCS10_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS10_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS10_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS10_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS10_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS10_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE1 0xD600
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE1_C1 0xF600
#define B_AX_MCS10_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS10_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS10_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS10_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS10_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS10_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE2 0xD604
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE2_C1 0xF604
#define B_AX_MCS10_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS10_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS10_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS10_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS10_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS10_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE3 0xD608
#define R_AX_PWR_SR_MCS10_TXDIFF_TABLE3_C1 0xF608
#define B_AX_MCS10_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS10_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS10_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS10_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS10_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS10_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS10_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE0 0xD60C
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE0_C1 0xF60C
#define B_AX_MCS11_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_MCS11_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_MCS11_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_MCS11_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_MCS11_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_MCS11_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE1 0xD610
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE1_C1 0xF610
#define B_AX_MCS11_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_MCS11_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_MCS11_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_MCS11_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_MCS11_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_MCS11_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE2 0xD614
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE2_C1 0xF614
#define B_AX_MCS11_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_MCS11_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_MCS11_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_MCS11_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_MCS11_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_MCS11_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE3 0xD618
#define R_AX_PWR_SR_MCS11_TXDIFF_TABLE3_C1 0xF618
#define B_AX_MCS11_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_MCS11_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_MCS11_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_MCS11_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_MCS11_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_MCS11_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_MCS11_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE0 0xD61C
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE0_C1 0xF61C
#define B_AX_CCK1M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_CCK1M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_CCK1M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_CCK1M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_CCK1M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_CCK1M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE1 0xD620
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE1_C1 0xF620
#define B_AX_CCK1M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_CCK1M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_CCK1M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_CCK1M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_CCK1M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_CCK1M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE2 0xD624
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE2_C1 0xF624
#define B_AX_CCK1M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_CCK1M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_CCK1M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_CCK1M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_CCK1M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_CCK1M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE3 0xD628
#define R_AX_PWR_SR_CCK1M_TXDIFF_TABLE3_C1 0xF628
#define B_AX_CCK1M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_CCK1M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_CCK1M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_CCK1M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_CCK1M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK1M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_CCK1M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE0 0xD62C
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE0_C1 0xF62C
#define B_AX_CCK2M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_CCK2M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_CCK2M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_CCK2M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_CCK2M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_CCK2M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE1 0xD630
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE1_C1 0xF630
#define B_AX_CCK2M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_CCK2M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_CCK2M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_CCK2M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_CCK2M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_CCK2M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE2 0xD634
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE2_C1 0xF634
#define B_AX_CCK2M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_CCK2M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_CCK2M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_CCK2M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_CCK2M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_CCK2M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE3 0xD638
#define R_AX_PWR_SR_CCK2M_TXDIFF_TABLE3_C1 0xF638
#define B_AX_CCK2M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_CCK2M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_CCK2M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_CCK2M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_CCK2M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK2M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_CCK2M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE0 0xD63C
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE0_C1 0xF63C
#define B_AX_CCK5P5M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_CCK5P5M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_CCK5P5M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_CCK5P5M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_CCK5P5M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_CCK5P5M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE1 0xD640
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE1_C1 0xF640
#define B_AX_CCK5P5M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_CCK5P5M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_CCK5P5M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_CCK5P5M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_CCK5P5M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_CCK5P5M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE2 0xD644
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE2_C1 0xF644
#define B_AX_CCK5P5M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_CCK5P5M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_CCK5P5M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_CCK5P5M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_CCK5P5M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_CCK5P5M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE3 0xD648
#define R_AX_PWR_SR_CCK5P5M_TXDIFF_TABLE3_C1 0xF648
#define B_AX_CCK5P5M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_CCK5P5M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_CCK5P5M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_CCK5P5M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_CCK5P5M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK5P5M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_CCK5P5M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE0 0xD64C
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE0_C1 0xF64C
#define B_AX_CCK11M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_CCK11M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_CCK11M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_CCK11M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_CCK11M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_CCK11M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE1 0xD650
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE1_C1 0xF650
#define B_AX_CCK11M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_CCK11M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_CCK11M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_CCK11M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_CCK11M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_CCK11M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE2 0xD654
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE2_C1 0xF654
#define B_AX_CCK11M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_CCK11M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_CCK11M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_CCK11M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_CCK11M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_CCK11M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE3 0xD658
#define R_AX_PWR_SR_CCK11M_TXDIFF_TABLE3_C1 0xF658
#define B_AX_CCK11M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_CCK11M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_CCK11M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_CCK11M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_CCK11M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_CCK11M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_CCK11M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE0 0xD65C
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE0_C1 0xF65C
#define B_AX_LEGACY6M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY6M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY6M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY6M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY6M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY6M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE1 0xD660
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE1_C1 0xF660
#define B_AX_LEGACY6M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY6M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY6M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY6M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY6M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY6M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE2 0xD664
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE2_C1 0xF664
#define B_AX_LEGACY6M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY6M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY6M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY6M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY6M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY6M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE3 0xD668
#define R_AX_PWR_SR_LEGACY6M_TXDIFF_TABLE3_C1 0xF668
#define B_AX_LEGACY6M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY6M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY6M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY6M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY6M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY6M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY6M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE0 0xD66C
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE0_C1 0xF66C
#define B_AX_LEGACY9M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY9M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY9M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY9M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY9M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY9M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE1 0xD670
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE1_C1 0xF670
#define B_AX_LEGACY9M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY9M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY9M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY9M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY9M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY9M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE2 0xD674
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE2_C1 0xF674
#define B_AX_LEGACY9M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY9M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY9M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY9M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY9M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY9M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE3 0xD678
#define R_AX_PWR_SR_LEGACY9M_TXDIFF_TABLE3_C1 0xF678
#define B_AX_LEGACY9M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY9M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY9M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY9M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY9M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY9M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY9M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE0 0xD67C
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE0_C1 0xF67C
#define B_AX_LEGACY12M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY12M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY12M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY12M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY12M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY12M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE1 0xD680
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE1_C1 0xF680
#define B_AX_LEGACY12M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY12M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY12M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY12M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY12M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY12M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE2 0xD684
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE2_C1 0xF684
#define B_AX_LEGACY12M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY12M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY12M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY12M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY12M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY12M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE3 0xD688
#define R_AX_PWR_SR_LEGACY12M_TXDIFF_TABLE3_C1 0xF688
#define B_AX_LEGACY12M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY12M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY12M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY12M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY12M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY12M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY12M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE0 0xD68C
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE0_C1 0xF68C
#define B_AX_LEGACY18M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY18M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY18M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY18M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY18M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY18M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE1 0xD690
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE1_C1 0xF690
#define B_AX_LEGACY18M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY18M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY18M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY18M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY18M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY18M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE2 0xD694
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE2_C1 0xF694
#define B_AX_LEGACY18M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY18M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY18M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY18M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY18M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY18M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE3 0xD698
#define R_AX_PWR_SR_LEGACY18M_TXDIFF_TABLE3_C1 0xF698
#define B_AX_LEGACY18M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY18M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY18M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY18M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY18M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY18M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY18M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE0 0xD69C
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE0_C1 0xF69C
#define B_AX_LEGACY24M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY24M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY24M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY24M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY24M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY24M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE1 0xD6A0
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE1_C1 0xF6A0
#define B_AX_LEGACY24M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY24M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY24M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY24M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY24M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY24M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE2 0xD6A4
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE2_C1 0xF6A4
#define B_AX_LEGACY24M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY24M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY24M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY24M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY24M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY24M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE3 0xD6A8
#define R_AX_PWR_SR_LEGACY24M_TXDIFF_TABLE3_C1 0xF6A8
#define B_AX_LEGACY24M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY24M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY24M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY24M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY24M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY24M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY24M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE0 0xD6AC
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE0_C1 0xF6AC
#define B_AX_LEGACY36M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY36M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY36M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY36M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY36M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY36M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE1 0xD6B0
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE1_C1 0xF6B0
#define B_AX_LEGACY36M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY36M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY36M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY36M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY36M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY36M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE2 0xD6B4
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE2_C1 0xF6B4
#define B_AX_LEGACY36M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY36M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY36M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY36M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY36M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY36M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE3 0xD6B8
#define R_AX_PWR_SR_LEGACY36M_TXDIFF_TABLE3_C1 0xF6B8
#define B_AX_LEGACY36M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY36M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY36M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY36M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY36M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY36M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY36M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE0 0xD6BC
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE0_C1 0xF6BC
#define B_AX_LEGACY48M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY48M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY48M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY48M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY48M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY48M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE1 0xD6C0
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE1_C1 0xF6C0
#define B_AX_LEGACY48M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY48M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY48M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY48M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY48M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY48M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE2 0xD6C4
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE2_C1 0xF6C4
#define B_AX_LEGACY48M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY48M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY48M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY48M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY48M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY48M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE3 0xD6C8
#define R_AX_PWR_SR_LEGACY48M_TXDIFF_TABLE3_C1 0xF6C8
#define B_AX_LEGACY48M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY48M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY48M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY48M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY48M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY48M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY48M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE0 0xD6CC
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE0_C1 0xF6CC
#define B_AX_LEGACY54M_TXDIFF_5DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY54M_TXDIFF_5DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_4DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY54M_TXDIFF_4DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_3DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY54M_TXDIFF_3DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_2DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY54M_TXDIFF_2DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_1DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY54M_TXDIFF_1DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE1 0xD6D0
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE1_C1 0xF6D0
#define B_AX_LEGACY54M_TXDIFF_10DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY54M_TXDIFF_10DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_9DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY54M_TXDIFF_9DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_8DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY54M_TXDIFF_8DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_7DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY54M_TXDIFF_7DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_6DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY54M_TXDIFF_6DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE2 0xD6D4
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE2_C1 0xF6D4
#define B_AX_LEGACY54M_TXDIFF_15DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY54M_TXDIFF_15DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_14DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY54M_TXDIFF_14DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_13DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY54M_TXDIFF_13DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_12DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY54M_TXDIFF_12DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_11DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY54M_TXDIFF_11DB_MCS_OFFSET_MSK 0xf
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE3 0xD6D8
#define R_AX_PWR_SR_LEGACY54M_TXDIFF_TABLE3_C1 0xF6D8
#define B_AX_LEGACY54M_TXDIFF_20DB_MCS_OFFSET_SH 16
#define B_AX_LEGACY54M_TXDIFF_20DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_19DB_MCS_OFFSET_SH 12
#define B_AX_LEGACY54M_TXDIFF_19DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_18DB_MCS_OFFSET_SH 8
#define B_AX_LEGACY54M_TXDIFF_18DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_17DB_MCS_OFFSET_SH 4
#define B_AX_LEGACY54M_TXDIFF_17DB_MCS_OFFSET_MSK 0xf
#define B_AX_LEGACY54M_TXDIFF_16DB_MCS_OFFSET_SH 0
#define B_AX_LEGACY54M_TXDIFF_16DB_MCS_OFFSET_MSK 0xf
#define R_AX_TXPWR_IMR 0xD9E0
#define R_AX_TXPWR_IMR_C1 0xF9E0
#define B_AX_TXPWR_FSM_TIMEOUT_INT_EN BIT(0)
#define R_AX_TXPWR_ISR 0xD9E4
#define R_AX_TXPWR_ISR_C1 0xF9E4
#define B_AX_TXPWR_FSM_TIMEOUT_ISR BIT(0)
#define R_AX_TXPWR_DBG_CFG 0xD9F8
#define R_AX_TXPWR_DBG_CFG_C1 0xF9F8
#define B_AX_TXPWR_DBG_SEL_SH 24
#define B_AX_TXPWR_DBG_SEL_MSK 0xff
#define B_AX_TXPWR_DBG_EN BIT(17)
#define B_AX_TXPWR_CLK_GATING_DIS BIT(16)
#define B_AX_TXPWR_TB_NTX BIT(8)
#define R_AX_TXPWR_DBG 0xD9FC
#define R_AX_TXPWR_DBG_C1 0xF9FC
#define B_AX_TXPWR_CTRL_DBG_SH 0
#define B_AX_TXPWR_CTRL_DBG_MSK 0xffffffffL
//
// BTCOEX
//
#define R_AX_BTC_CFG 0xDA00
#define R_AX_BTC_CFG_C1 0xFA00
#define B_AX_DIS_BTC_CLK_G BIT(2)
#define B_AX_GNT_WL_RX_CTRL BIT(1)
#define B_AX_WL_SRC BIT(0)
#define R_AX_WL_PRI_MSK 0xDA10
#define R_AX_WL_PRI_MSK_C1 0xFA10
#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8)
#define B_AX_PTA_WL_PRI_MASK_HIQ BIT(7)
#define B_AX_PTA_WL_PRI_MASK_CPUMGQ BIT(6)
#define B_AX_PTA_WL_PRI_MASK_PSMGQ BIT(5)
#define B_AX_PTA_WL_PRI_MASK_MGQ BIT(4)
#define B_AX_PTA_WL_PRI_MASK_BK BIT(3)
#define B_AX_PTA_WL_PRI_MASK_BE BIT(2)
#define B_AX_PTA_WL_PRI_MASK_VI BIT(1)
#define B_AX_PTA_WL_PRI_MASK_VO BIT(0)
#define R_AX_BTC_FUNC_EN 0xDA20
#define R_AX_BTC_FUNC_EN_C1 0xFA20
#define B_AX_PTA_EDCCA_EN BIT(1)
#define B_AX_PTA_WL_TX_EN BIT(0)
#define R_AX_COEX_TABLE_1 0xDA24
#define R_AX_COEX_TABLE_1_C1 0xFA24
#define B_AX_COEX_TABLE_1_SH 0
#define B_AX_COEX_TABLE_1_MSK 0xffffffffL
#define R_AX_COEX_TABLE_2 0xDA28
#define R_AX_COEX_TABLE_2_C1 0xFA28
#define B_AX_COEX_TABLE_2_SH 0
#define B_AX_COEX_TABLE_2_MSK 0xffffffffL
#define R_AX_BREAK_TABLE 0xDA2C
#define R_AX_BREAK_TABLE_C1 0xFA2C
#define B_AX_COEX_BREAK_TABLE_2_SH 16
#define B_AX_COEX_BREAK_TABLE_2_MSK 0xffff
#define B_AX_COEX_BREAK_TABLE_1_SH 0
#define B_AX_COEX_BREAK_TABLE_1_MSK 0xffff
#define R_AX_BT_COEX_MSK_TABLE 0xDA30
#define R_AX_BT_COEX_MSK_TABLE_C1 0xFA30
#define B_AX_PRI_MASK_RX_RESP_V1 BIT(30)
#define B_AX_PRI_MASK_RXOFDM_V1 BIT(29)
#define B_AX_PRI_MASK_RXCCK_V1 BIT(28)
#define B_AX_PRI_MASK_TXAC_SH 21
#define B_AX_PRI_MASK_TXAC_MSK 0x7f
#define B_AX_PRI_MASK_NAV_SH 13
#define B_AX_PRI_MASK_NAV_MSK 0xff
#define B_AX_PRI_MASK_CCK_V1 BIT(12)
#define B_AX_PRI_MASK_OFDM_V1 BIT(11)
#define B_AX_PRI_MASK_RTY_V1 BIT(10)
#define B_AX_PRI_MASK_NUM_SH 6
#define B_AX_PRI_MASK_NUM_MSK 0xf
#define B_AX_PRI_MASK_TYPE_SH 2
#define B_AX_PRI_MASK_TYPE_MSK 0xf
#define B_AX_OOB_V1 BIT(1)
#define B_AX_ANT_SEL_V1 BIT(0)
#define R_AX_BT_COEX_CFG_2 0xDA34
#define R_AX_BT_COEX_CFG_2_C1 0xFA34
#define B_AX_GNT_BT_POLARITY BIT(12)
#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(8)
#define B_AX_TIMER_SH 0
#define B_AX_TIMER_MSK 0xff
#define R_AX_BT_COEX_CFG_3 0xDA38
#define R_AX_BT_COEX_CFG_3_C1 0xFA38
#define B_AX_R_BT_CNT_THREN BIT(8)
#define B_AX_R_BT_CNT_THR_SH 0
#define B_AX_R_BT_CNT_THR_MSK 0xff
#define R_AX_BT_COEX_CFG_4 0xDA3C
#define R_AX_BT_COEX_CFG_4_C1 0xFA3C
#define B_AX_ANT_DIVERSITY_SEL_1 BIT(9)
#define B_AX_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8)
#define B_AX_WLACT_LOW_GNTWL_EN_1 BIT(2)
#define B_AX_WLACT_HIGH_GNTBT_EN_1 BIT(1)
#define B_AX_NAV_UPPER_1_V1 BIT(0)
#define R_AX_CSR_MODE 0xDA40
#define R_AX_CSR_MODE_C1 0xFA40
#define B_AX_BT_CNT_REST BIT(16)
#define B_AX_BT_STAT_DELAY_SH 12
#define B_AX_BT_STAT_DELAY_MSK 0xf
#define B_AX_BT_TRX_INIT_DETECT_SH 8
#define B_AX_BT_TRX_INIT_DETECT_MSK 0xf
#define B_AX_BT_PRI_DETECT_TO_SH 4
#define B_AX_BT_PRI_DETECT_TO_MSK 0xf
#define B_AX_WL_ACT_MSK BIT(3)
#define B_AX_STATIS_BT_EN BIT(2)
#define B_AX_WL_ACT_MASK_ENABLE BIT(1)
#define B_AX_ENHANCED_BT BIT(0)
#define R_AX_BT_STAST_HIGH 0xDA44
#define R_AX_BT_STAST_HIGH_C1 0xFA44
#define B_AX_STATIS_BT_HI_RX_SH 16
#define B_AX_STATIS_BT_HI_RX_MSK 0xffff
#define B_AX_STATIS_BT_HI_TX_SH 0
#define B_AX_STATIS_BT_HI_TX_MSK 0xffff
#define R_AX_GNT_SW_CTRL 0xDA48
#define R_AX_BT_STAST_LOW 0xDA48
#define R_AX_BT_STAST_LOW_C1 0xFA48
#define B_AX_STATIS_BT_LO_RX_1_SH 16
#define B_AX_STATIS_BT_LO_RX_1_MSK 0xffff
#define B_AX_STATIS_BT_LO_TX_1_SH 0
#define B_AX_STATIS_BT_LO_TX_1_MSK 0xffff
#define R_AX_TDMA_MODE 0xDA4C
#define R_AX_TDMA_MODE_C1 0xFA4C
#define B_AX_R_BT_CMD_RPT_SH 16
#define B_AX_R_BT_CMD_RPT_MSK 0xffff
#define B_AX_R_RPT_FROM_BT_SH 8
#define B_AX_R_RPT_FROM_BT_MSK 0xff
#define B_AX_BT_HID_ISR_SET_SH 6
#define B_AX_BT_HID_ISR_SET_MSK 0x3
#define B_AX_TDMA_BT_START_NOTIFY BIT(5)
#define B_AX_ENABLE_TDMA_FW_MODE BIT(4)
#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3)
#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
#define B_AX_RTK_BT_ENABLE BIT(0)
#define R_AX_RTK_MODE_RPT 0xDA50
#define R_AX_RTK_MODE_RPT_C1 0xFA50
#define B_AX_BT_PROFILE_SH 24
#define B_AX_BT_PROFILE_MSK 0xff
#define B_AX_BT_POWER_SH 16
#define B_AX_BT_POWER_MSK 0xff
#define B_AX_BT_PREDECT_STATUS_SH 8
#define B_AX_BT_PREDECT_STATUS_MSK 0xff
#define B_AX_BT_CMD_INFO_SH 0
#define B_AX_BT_CMD_INFO_MSK 0xff
#define R_AX_RTK_MODE_CFG 0xDA54
#define R_AX_RTK_MODE_CFG_C1 0xFA54
#define B_AX_EN_MAC_NULL_PKT_NOTIFY BIT(31)
#define B_AX_EN_WLAN_RPT_AND_BT_QUERY BIT(30)
#define B_AX_EN_BT_STSTUS_RPT BIT(29)
#define B_AX_EN_BT_POWER BIT(28)
#define B_AX_EN_BT_CHANNEL BIT(27)
#define B_AX_EN_BT_SLOT_CHANGE BIT(26)
#define B_AX_EN_BT_PROFILE_OR_HID BIT(25)
#define B_AX_WLAN_RPT_NOTIFY BIT(24)
#define B_AX_WLAN_RPT_DATA_SH 16
#define B_AX_WLAN_RPT_DATA_MSK 0xff
#define B_AX_CMD_ID_SH 8
#define B_AX_CMD_ID_MSK 0xff
#define B_AX_BT_DATA_SH 0
#define B_AX_BT_DATA_MSK 0xff
#define R_AX_RTK_MODE_TO 0xDA58
#define R_AX_RTK_MODE_TO_C1 0xFA58
#define B_AX_WLAN_RPT_TO_SH 0
#define B_AX_WLAN_RPT_TO_MSK 0xff
#define R_AX_BT_COEX_ISO 0xDA5C
#define R_AX_BT_COEX_ISO_C1 0xFA5C
#define B_AX_ISOLATION_CHK_0_SH 1
#define B_AX_ISOLATION_CHK_0_MSK 0x7fffff
#define B_AX_ISOLATION_EN BIT(0)
#define R_AX_BT_COEX_ISO_CHK_1 0xDA60
#define R_AX_BT_COEX_ISO_CHK_1_C1 0xFA60
#define B_AX_ISOLATION_CHK_1_SH 0
#define B_AX_ISOLATION_CHK_1_MSK 0xffffffffL
#define R_AX_BT_COEX_ISO_CHK_2 0xDA64
#define R_AX_BT_COEX_ISO_CHK_2_C1 0xFA64
#define B_AX_BT_HID_ISR BIT(31)
#define B_AX_BT_QUERY_ISR BIT(30)
#define B_AX_MAC_NULL_PKT_NOTIFY_ISR BIT(29)
#define B_AX_WLAN_RPT_ISR BIT(28)
#define B_AX_BT_POWER_ISR BIT(27)
#define B_AX_BT_CHANNEL_ISR BIT(26)
#define B_AX_BT_SLOT_CHANGE_ISR BIT(25)
#define B_AX_BT_PROFILE_ISR BIT(24)
#define B_AX_ISOLATION_CHK_2_SH 0
#define B_AX_ISOLATION_CHK_2_MSK 0xffffff
#define R_AX_BT_COEX_CFG_5 0xDA6C
#define R_AX_BT_COEX_CFG_5_C1 0xFA6C
#define B_AX_BT_TIME_SH 6
#define B_AX_BT_TIME_MSK 0x3ffffff
#define B_AX_BT_RPT_SAMPLE_RATE_SH 0
#define B_AX_BT_RPT_SAMPLE_RATE_MSK 0x3f
#define R_AX_BT_ACT_CFG 0xDA70
#define R_AX_BT_ACT_CFG_C1 0xFA70
#define B_AX_BT_EISR_EN_SH 16
#define B_AX_BT_EISR_EN_MSK 0xff
#define B_AX_BT_ACT_FALLING_ISR BIT(10)
#define B_AX_BT_ACT_RISING_ISR BIT(9)
#define B_AX_TDMA_TO_ISR BIT(8)
#define B_AX_BT_CH_SH 0
#define B_AX_BT_CH_MSK 0x7f
#define R_AX_BT_TIME_CNT 0xDA74
#define R_AX_BT_TIME_CNT_C1 0xFA74
#define B_AX_BT_TIME_CNT_SH 0
#define B_AX_BT_TIME_CNT_MSK 0xff
#define R_AX_WLACT_MASK_CTRL 0xDA7C
#define R_AX_WLACT_MASK_CTRL_C1 0xFA7C
#define B_AX_RX_RTS_NAV_SH 8
#define B_AX_RX_RTS_NAV_MSK 0xff
#define B_AX_RESET_RTS_SH 0
#define B_AX_RESET_RTS_MSK 0xff
#define R_AX_LTE_CTRL 0xDAF0
#define R_AX_LTE_CTRL_C1 0xFAF0
#define B_AX_LTE_SET BIT(31)
#define B_AX_LTE_RW BIT(30)
#define B_AX_LTE_RDY BIT(29)
#define B_AX_LTE_BYTE_EN_SH 16
#define B_AX_LTE_BYTE_EN_MSK 0xf
#define B_AX_LTE_ADDR_SH 0
#define B_AX_LTE_ADDR_MSK 0xffff
#define R_AX_LTE_WDATA 0xDAF4
#define R_AX_LTE_WDATA_C1 0xFAF4
#define B_AX_LTE_WDATA_SH 0
#define B_AX_LTE_WDATA_MSK 0xffffffffL
#define R_AX_LTE_RDATA 0xDAF8
#define R_AX_LTE_RDATA_C1 0xFAF8
#define B_AX_LTE_RDATA_SH 0
#define B_AX_LTE_RDATA_MSK 0xffffffffL
//
// LTECOEX
//
#define R_AX_LTE_SW_CFG_1 0x0038
#define R_AX_LTE_SW_CFG_1_C1 0x2038
#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30)
#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29)
#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28)
#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27)
#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26)
#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25)
#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24)
#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19)
#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18)
#define B_AX_LTE_PATTERN_2_EN BIT(17)
#define B_AX_LTE_PATTERN_1_EN BIT(16)
#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15)
#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14)
#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13)
#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12)
#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11)
#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10)
#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9)
#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8)
#define B_AX_LTECOEX_FUN_EN BIT(7)
#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6)
#define B_AX_LTECOEX_OP_MODE_SEL_SH 4
#define B_AX_LTECOEX_OP_MODE_SEL_MSK 0x3
#define B_AX_LTECOEX_UART_MUX BIT(3)
#define B_AX_LTECOEX_UART_MODE_SEL_SH 0
#define B_AX_LTECOEX_UART_MODE_SEL_MSK 0x7
#define R_AX_LTE_SW_CFG_2 0x003C
#define R_AX_LTE_SW_CFG_2_C1 0x203C
#define B_AX_WL_RX_CTRL BIT(8)
#define B_AX_GNT_WL_RX_SW_VAL BIT(7)
#define B_AX_GNT_WL_RX_SW_CTRL BIT(6)
#define B_AX_GNT_WL_TX_SW_VAL BIT(5)
#define B_AX_GNT_WL_TX_SW_CTRL BIT(4)
#define B_AX_GNT_BT_RX_SW_VAL BIT(3)
#define B_AX_GNT_BT_RX_SW_CTRL BIT(2)
#define B_AX_GNT_BT_TX_SW_VAL BIT(1)
#define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
//
// WL_AX_Reg_HIOE.xls
//
//
// HIOE_Reg_Spec
//
#define R_PL_HIOE_CTRL 0x0000
#define B_PL_HIOE_RESTORE_REQ BIT(31)
#define B_PL_HIOE_RETAIN_REQ BIT(30)
#define B_PL_HIOE_DDMA_CH1_REQ BIT(29)
#define B_PL_HIOE_DDMA_CH2_REQ BIT(28)
#define B_PL_HIOE_DDMA_CH1_CHKSUM_STATUS BIT(27)
#define B_PL_HIOE_DDMA_CH2_CHKSUM_STATUS BIT(26)
#define B_PL_HIOE_INST_FORMAT_ERR BIT(25)
#define B_PL_HIOE_OP_TIMEOUT_ERR BIT(24)
#define B_PL_HIOE_OP_TIMEOUT_SH 16
#define B_PL_HIOE_OP_TIMEOUT_MSK 0xff
#define B_PL_HIOE_ADDR_CHECKSUM_SH 0
#define B_PL_HIOE_ADDR_CHECKSUM_MSK 0xffff
#define R_PL_HIOE_CFG_FILE_START 0x0004
#define B_PL_HIOE_CFG_FILE_START_SH 0
#define B_PL_HIOE_CFG_FILE_START_MSK 0xffffffffL
#define R_PL_HIOE_CFG_FILE_END 0x0008
#define B_PL_HIOE_CFG_FILE_END_SH 0
#define B_PL_HIOE_CFG_FILE_END_MSK 0xffffffffL
#define R_PL_HIOE_CUR_INST_ADDR 0x000C
#define B_PL_HIOE_CUR_INST_ADDR_SH 0
#define B_PL_HIOE_CUR_INST_ADDR_MSK 0xffffffffL
//
// WL_AX_Reg_IDDMA.xls
//
//
// IDDMA_Reg_Spec
//
#define R_PL_IDDMA_CH0_SA 0x0000
#define B_PL_IDDMA_CH0_SA_SH 0
#define B_PL_IDDMA_CH0_SA_MSK 0xffffffffL
#define R_PL_IDDMA_CH0_DA 0x0004
#define B_PL_IDDMA_CH0_DA_SH 0
#define B_PL_IDDMA_CH0_DA_MSK 0xffffffffL
#define R_PL_IDDMA_CH0_CTRL 0x0008
#define B_PL_IDDMA_CH0_OWN BIT(31)
#define B_PL_IDDMA_CH0_CHKSUM_EN BIT(29)
#define B_PL_IDDMA_CH0_DA_W_DISABLE BIT(28)
#define B_PL_IDDMA_CH0_CHKSUM_STATUS BIT(27)
#define B_PL_IDDMA_CH0_CHKSUM_CONT BIT(24)
#define B_PL_IDDMA_CH0_DLEN_SH 0
#define B_PL_IDDMA_CH0_DLEN_MSK 0x3ffff
#define R_PL_IDDMA_CH1_SA 0x0010
#define B_PL_IDDMA_CH1_SA_SH 0
#define B_PL_IDDMA_CH1_SA_MSK 0xffffffffL
#define R_PL_IDDMA_CH1_DA 0x0014
#define B_PL_IDDMA_CH1_DA_SH 0
#define B_PL_IDDMA_CH1_DA_MSK 0xffffffffL
#define R_PL_IDDMA_CH1_CTRL 0x0018
#define B_PL_IDDMA_CH1_OWN BIT(31)
#define B_PL_IDDMA_CH1_CHKSUM_EN BIT(29)
#define B_PL_IDDMA_CH1_DA_W_DISABLE BIT(28)
#define B_PL_IDDMA_CH1_CHKSUM_STATUS BIT(27)
#define B_PL_IDDMA_CH1_DLEN_SH 0
#define B_PL_IDDMA_CH1_DLEN_MSK 0x3ffff
#define R_PL_IDDMA_CH2_SA 0x0020
#define B_PL_IDDMA_CH2_SA_SH 0
#define B_PL_IDDMA_CH2_SA_MSK 0xffffffffL
#define R_PL_IDDMA_CH2_DA 0x0024
#define B_PL_IDDMA_CH2_DA_SH 0
#define B_PL_IDDMA_CH2_DA_MSK 0xffffffffL
#define R_PL_IDDMA_CH2_CTRL 0x0028
#define B_PL_IDDMA_CH2_OWN BIT(31)
#define B_PL_IDDMA_CH2_CHKSUM_EN BIT(29)
#define B_PL_IDDMA_CH2_DA_W_DISABLE BIT(28)
#define B_PL_IDDMA_CH2_CHKSUM_STATUS BIT(27)
#define B_PL_IDDMA_CH2_DLEN_SH 0
#define B_PL_IDDMA_CH2_DLEN_MSK 0x3ffff
#define R_PL_IDDMA_CH3_SA 0x0030
#define B_PL_IDDMA_CH3_SA_SH 0
#define B_PL_IDDMA_CH3_SA_MSK 0xffffffffL
#define R_PL_IDDMA_CH3_DA 0x0034
#define B_PL_IDDMA_CH3_DA_SH 0
#define B_PL_IDDMA_CH3_DA_MSK 0xffffffffL
#define R_PL_IDDMA_CH3_CTRL 0x0038
#define B_PL_IDDMA_CH3_OWN BIT(31)
#define B_PL_IDDMA_CH3_CHKSUM_EN BIT(29)
#define B_PL_IDDMA_CH3_DA_W_DISABLE BIT(28)
#define B_PL_IDDMA_CH3_CHKSUM_STATUS BIT(27)
#define B_PL_IDDMA_CH3_DLEN_SH 0
#define B_PL_IDDMA_CH3_DLEN_MSK 0x3ffff
#define R_PL_IDDMA_CH4_SA 0x0040
#define B_PL_IDDMA_CH4_SA_SH 0
#define B_PL_IDDMA_CH4_SA_MSK 0xffffffffL
#define R_PL_IDDMA_CH4_DA 0x0044
#define B_PL_IDDMA_CH4_DA_SH 0
#define B_PL_IDDMA_CH4_DA_MSK 0xffffffffL
#define R_PL_IDDMA_CH4_CTRL 0x0048
#define B_PL_IDDMA_CH4_OWN BIT(31)
#define B_PL_IDDMA_CH4_CHKSUM_EN BIT(29)
#define B_PL_IDDMA_CH4_DA_W_DISABLE BIT(28)
#define B_PL_IDDMA_CH4_CHKSUM_STATUS BIT(27)
#define B_PL_IDDMA_CH4_DLEN_SH 0
#define B_PL_IDDMA_CH4_DLEN_MSK 0x3ffff
#define R_PL_IDDMA_CH5_SA 0x0050
#define B_PL_IDDMA_CH5_SA_SH 0
#define B_PL_IDDMA_CH5_SA_MSK 0xffffffffL
#define R_PL_IDDMA_CH5_DA 0x0054
#define B_PL_IDDMA_CH5_DA_SH 0
#define B_PL_IDDMA_CH5_DA_MSK 0xffffffffL
#define R_PL_IDDMA_CH5_CTRL 0x0058
#define B_PL_IDDMA_CH5_OWN BIT(31)
#define B_PL_IDDMA_CH5_CHKSUM_EN BIT(29)
#define B_PL_IDDMA_CH5_DA_W_DISABLE BIT(28)
#define B_PL_IDDMA_CH5_CHKSUM_STATUS BIT(27)
#define B_PL_IDDMA_CH5_DLEN_SH 0
#define B_PL_IDDMA_CH5_DLEN_MSK 0x3ffff
#define R_PL_IDDMA_FWIMR 0x00E0
#define B_PL_IDDMA_CH5_INT_MSK BIT(5)
#define B_PL_IDDMA_CH4_INT_MSK BIT(4)
#define B_PL_IDDMA_CH3_INT_MSK BIT(3)
#define B_PL_IDDMA_CH2_INT_MSK BIT(2)
#define B_PL_IDDMA_CH1_INT_MSK BIT(1)
#define B_PL_IDDMA_CH0_INT_MSK BIT(0)
#define R_PL_IDDMA_FWISR 0x00E4
#define B_PL_IDDMA_CH5_INT BIT(5)
#define B_PL_IDDMA_CH4_INT BIT(4)
#define B_PL_IDDMA_CH3_INT BIT(3)
#define B_PL_IDDMA_CH2_INT BIT(2)
#define B_PL_IDDMA_CH1_INT BIT(1)
#define B_PL_IDDMA_CH0_INT BIT(0)
#define R_PL_IDDMA_CH_STATUS 0x00E8
#define B_PL_IDDMA_CH5_BUSY BIT(5)
#define B_PL_IDDMA_CH4_BUSY BIT(4)
#define B_PL_IDDMA_CH3_BUSY BIT(3)
#define B_PL_IDDMA_CH2_BUSY BIT(2)
#define B_PL_IDDMA_CH1_BUSY BIT(1)
#define B_PL_IDDMA_CH0_BUSY BIT(0)
#define R_PL_IDDMA_CHKSUM_CONTROL 0x00EC
#define B_PL_IDDMA_CHKSUM_RESET BIT(0)
#define R_PL_IDDMA_CHKSUM 0x00F0
#define B_PL_IDDMA_CHKSUM_RESULT_SH 0
#define B_PL_IDDMA_CHKSUM_RESULT_MSK 0xffff
#define R_PL_IDDMA_MONITOR 0x00FC
#define B_PL_IDDMA_CH5_DOK BIT(21)
#define B_PL_IDDMA_CH4_DOK BIT(20)
#define B_PL_IDDMA_CH3_DOK BIT(19)
#define B_PL_IDDMA_CH2_DOK BIT(18)
#define B_PL_IDDMA_CH1_DOK BIT(17)
#define B_PL_IDDMA_CH0_DOK BIT(16)
#define B_PL_IDDMA_DATA_UNDERFLOW BIT(14)
#define B_PL_IDDMA_FIFO_UNDERFLOW BIT(13)
#define B_PL_IDDMA_FIFO_OVERFLOW BIT(12)
#define B_PL_IDDMA_CH5_ERROR BIT(5)
#define B_PL_IDDMA_CH4_ERROR BIT(4)
#define B_PL_IDDMA_CH3_ERROR BIT(3)
#define B_PL_IDDMA_CH2_ERROR BIT(2)
#define B_PL_IDDMA_CH1_ERROR BIT(1)
#define B_PL_IDDMA_CH0_ERROR BIT(0)
//
// WL_AX_Reg_IPSec.xls
//
//
// IPSec_Reg
//
#define R_PL_REG_SDSR 0x0000
#define B_PL_SRC_RST BIT(31)
#define B_PL_PK_UP BIT(30)
#define B_PL_SRC_FAIL_STATUS_SH 25
#define B_PL_SRC_FAIL_STATUS_MSK 0x3
#define B_PL_SRC_FAIL BIT(24)
#define B_PL_SRPTR_SH 16
#define B_PL_SRPTR_MSK 0xff
#define B_PL_SWPTR_SH 8
#define B_PL_SWPTR_MSK 0xff
#define B_PL_FIFO_EMPTY_CNT_SH 0
#define B_PL_FIFO_EMPTY_CNT_MSK 0xff
#define R_PL_REG_SDFWR 0x0004
#define B_PL_SDFW_SH 0
#define B_PL_SDFW_MSK 0xffffffffL
#define R_PL_REG_SDSWR 0x0008
#define B_PL_SDSW_SH 0
#define B_PL_SDSW_MSK 0xffffffffL
#define R_PL_REG_IPSCSR_RSTEACONFISR 0x0010
#define B_PL_IPSEC_RST BIT(31)
#define B_PL_CLEAR_OK_INT_NUM_SH 16
#define B_PL_CLEAR_OK_INT_NUM_MSK 0xff
#define B_PL_OK_INTR_CNT_SH 8
#define B_PL_OK_INTR_CNT_MSK 0xff
#define B_PL_INTR_MODE BIT(7)
#define B_PL_CMD_OK BIT(4)
#define B_PL_DMA_BUSY BIT(3)
#define B_PL_SOFT_RST BIT(0)
#define R_PL_REG_IPSCSR_INTM 0x0014
#define B_PL_DES_ERR5_M BIT(18)
#define B_PL_DES_ERR4_M BIT(17)
#define B_PL_DES_ERR3_M BIT(16)
#define B_PL_DES_ERR2_M BIT(15)
#define B_PL_DES_ERR1_M BIT(14)
#define B_PL_DES_ERR0_M BIT(13)
#define B_PL_SRC_ERR9_M BIT(12)
#define B_PL_SRC_ERR8_M BIT(11)
#define B_PL_SRC_ERR7_M BIT(10)
#define B_PL_SRC_ERR6_M BIT(9)
#define B_PL_SRC_ERR5_M BIT(8)
#define B_PL_SRC_ERR4_M BIT(7)
#define B_PL_SRC_ERR3_M BIT(6)
#define B_PL_SRC_ERR2_M BIT(5)
#define B_PL_SRC_ERR1_M BIT(4)
#define B_PL_SRC_ERR0_M BIT(3)
#define B_PL_DES_FAIL_M BIT(2)
#define B_PL_SRC_FAIL_M BIT(1)
#define B_PL_CMD_OK_M BIT(0)
#define R_PL_REG_IPSCSR_DBG 0x0018
#define B_PL_DEBUG_WB BIT(31)
#define B_PL_MST_BAD_SEL_SH 28
#define B_PL_MST_BAD_SEL_MSK 0x3
#define B_PL_ENGINE_CLK_EN BIT(24)
#define B_PL_DEBUG_PORT_SEL_SH 20
#define B_PL_DEBUG_PORT_SEL_MSK 0xf
#define B_PL_ARBITER_MODE BIT(16)
#define B_PL_DMA_WAIT_CYCLE_SH 0
#define B_PL_DMA_WAIT_CYCLE_MSK 0xffff
#define R_PL_REG_IPSCSR_ERR_INT 0x001C
#define B_PL_DES_ERR5 BIT(15)
#define B_PL_DES_ERR4 BIT(14)
#define B_PL_DES_ERR3 BIT(13)
#define B_PL_DES_ERR2 BIT(12)
#define B_PL_DES_ERR1 BIT(11)
#define B_PL_DES_ERR0 BIT(10)
#define B_PL_SRC_ERR9 BIT(9)
#define B_PL_SRC_ERR8 BIT(8)
#define B_PL_SRC_ERR7 BIT(7)
#define B_PL_SRC_ERR6 BIT(6)
#define B_PL_SRC_ERR5 BIT(5)
#define B_PL_SRC_ERR4 BIT(4)
#define B_PL_SRC_ERR3 BIT(3)
#define B_PL_SRC_ERR2 BIT(2)
#define B_PL_SRC_ERR1 BIT(1)
#define B_PL_SRC_ERR0 BIT(0)
#define R_PL_REG_IPSCSR_SAADLR 0x0020
#define B_PL_A2EO_SUM_SH 0
#define B_PL_A2EO_SUM_MSK 0x7ff
#define R_PL_REG_IPSCSR_SENLR 0x0024
#define B_PL_ENL_SUM_SH 0
#define B_PL_ENL_SUM_MSK 0xffffff
#define R_PL_REG_IPSCSR_SAPLR 0x0028
#define B_PL_APL_SUM_SH 0
#define B_PL_APL_SUM_MSK 0xfff
#define R_PL_REG_IPSCSR_SEPLR 0x002C
#define B_PL_EPL_SUM_SH 0
#define B_PL_EPL_SUM_MSK 0x3f
#define R_PL_REG_IPSCSR_SWAPABURSTR 0x0030
#define B_PL_MD5_INPUT_DATA_BYTE_SWAP BIT(25)
#define B_PL_MD5_OUTPUT_DATA_BYTE_SWAP BIT(24)
#define B_PL_DMA_BURST_LENGTH_SH 16
#define B_PL_DMA_BURST_LENGTH_MSK 0x3f
#define B_PL_AUTO_PADDING_SWAP BIT(13)
#define B_PL_TX_WD_SWAP BIT(12)
#define B_PL_RX_WD_SWAP BIT(11)
#define B_PL_MAC_OUT_LITTLE_ENDIAN BIT(10)
#define B_PL_DATA_OUT_LITTLE_ENDIAN BIT(9)
#define B_PL_TX_BYTE_SWAP BIT(8)
#define B_PL_DATA_IN_LITTLE_ENDIAN BIT(4)
#define B_PL_HASH_INITIAL_VALUE_SWAP BIT(3)
#define B_PL_KEY_PAD_SWAP BIT(2)
#define B_PL_KEY_IV_SWAP BIT(1)
#define B_PL_SET_SWAP BIT(0)
#define R_PL_REG_DDSR 0x1000
#define B_PL_DES_RST BIT(31)
#define B_PL_DES_FAIL_STATUS_SH 25
#define B_PL_DES_FAIL_STATUS_MSK 0x3
#define B_PL_DES_FAIL BIT(24)
#define B_PL_DRPTR_SH 16
#define B_PL_DRPTR_MSK 0xff
#define B_PL_DWPTR_SH 8
#define B_PL_DWPTR_MSK 0xff
#define R_PL_REG_DDFWR 0x1004
#define B_PL_DDFW_SH 0
#define B_PL_DDFW_MSK 0xffffffffL
#define R_PL_REG_DDSWR 0x1008
#define B_PL_DDSW_SH 0
#define B_PL_DDSW_MSK 0xffffffffL
#define R_PL_REG_DES_PKTCONF 0x100C
#define B_PL_DBG_DPTR_SH 8
#define B_PL_DBG_DPTR_MSK 0xff
#define B_PL_DBG_SPTR_SH 0
#define B_PL_DBG_SPTR_MSK 0xff
#define R_PL_REG_DBGSDR 0x1010
#define B_PL_DBG_SD_SH 0
#define B_PL_DBG_SD_MSK 0xffffffffL
#define R_PL_REG_DBGDDR 0x1014
#define B_PL_DBG_DD_SH 0
#define B_PL_DBG_DD_MSK 0xffffffffL
//
// WL_AX_Reg_HAXIDMA.xls
//
//
// PCIE
//
#define R_AX_HAXI_INIT_CFG1 0x1000
#define B_AX_WD_ITVL_IDLE_V1_SH 28
#define B_AX_WD_ITVL_IDLE_V1_MSK 0xf
#define B_AX_WD_ITVL_ACT_V1_SH 24
#define B_AX_WD_ITVL_ACT_V1_MSK 0xf
#define B_AX_DMA_MODE_SH 18
#define B_AX_DMA_MODE_MSK 0x3
#define B_AX_STOP_AXI_MST BIT(17)
#define B_AX_HAXI_RST_KEEP_REG BIT(16)
#define B_AX_RXHCI_EN_V1 BIT(15)
#define B_AX_RXBD_MODE_V1 BIT(14)
#define B_AX_HAXI_MAX_RXDMA_SH 8
#define B_AX_HAXI_MAX_RXDMA_MSK 0x3
#define B_AX_TXHCI_EN_V1 BIT(7)
#define B_AX_FLUSH_AXI_MST BIT(4)
#define B_AX_RST_BDRAM BIT(3)
#define B_AX_HAXI_MAX_TXDMA_SH 0
#define B_AX_HAXI_MAX_TXDMA_MSK 0x3
#define R_AX_HAXI_DMA_STOP1 0x1010
#define B_AX_STOP_WPDMA BIT(19)
#define B_AX_STOP_CH12 BIT(18)
#define B_AX_STOP_CH9 BIT(17)
#define B_AX_STOP_CH8 BIT(16)
#define B_AX_STOP_ACH7 BIT(15)
#define B_AX_STOP_ACH6 BIT(14)
#define B_AX_STOP_ACH5 BIT(13)
#define B_AX_STOP_ACH4 BIT(12)
#define B_AX_STOP_ACH3 BIT(11)
#define B_AX_STOP_ACH2 BIT(10)
#define B_AX_STOP_ACH1 BIT(9)
#define B_AX_STOP_ACH0 BIT(8)
#define R_AX_TXBD_RWPTR_CLR1 0x1014
#define B_AX_CLR_CH12_IDX BIT(10)
#define B_AX_CLR_CH9_IDX BIT(9)
#define B_AX_CLR_CH8_IDX BIT(8)
#define B_AX_CLR_ACH7_IDX BIT(7)
#define B_AX_CLR_ACH6_IDX BIT(6)
#define B_AX_CLR_ACH5_IDX BIT(5)
#define B_AX_CLR_ACH4_IDX BIT(4)
#define B_AX_CLR_ACH3_IDX BIT(3)
#define B_AX_CLR_ACH2_IDX BIT(2)
#define B_AX_CLR_ACH1_IDX BIT(1)
#define B_AX_CLR_ACH0_IDX BIT(0)
#define R_AX_HAXI_DMA_BUSY1 0x101C
#define B_AX_HAXIIO_BUSY BIT(20)
#define B_AX_WPDMA_BUSY BIT(19)
#define B_AX_CH12_BUSY BIT(18)
#define B_AX_CH9_BUSY BIT(17)
#define B_AX_CH8_BUSY BIT(16)
#define B_AX_ACH7_BUSY BIT(15)
#define B_AX_ACH6_BUSY BIT(14)
#define B_AX_ACH5_BUSY BIT(13)
#define B_AX_ACH4_BUSY BIT(12)
#define B_AX_ACH3_BUSY BIT(11)
#define B_AX_ACH2_BUSY BIT(10)
#define B_AX_ACH1_BUSY BIT(9)
#define B_AX_ACH0_BUSY BIT(8)
#define R_AX_HAXI_DMA_STOP2 0x11C0
#define B_AX_STOP_CH11 BIT(1)
#define B_AX_STOP_CH10 BIT(0)
#define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
#define B_AX_CLR_CH11_IDX BIT(1)
#define B_AX_CLR_CH10_IDX BIT(0)
#define R_AX_HAXI_DMA_BUSY2 0x11C8
#define B_AX_CH11_BUSY BIT(1)
#define B_AX_CH10_BUSY BIT(0)
#define R_AX_RXBD_RWPTR_CLR_V1 0x1200
#define B_AX_CLR_RPQ_IDX BIT(1)
#define B_AX_CLR_RXQ_IDX BIT(0)
#define R_AX_HAXI_EXP_CTRL 0x1204
#define B_AX_MAX_TAG_NUM_V1_SH 0
#define B_AX_MAX_TAG_NUM_V1_MSK 0x7
#define R_AX_HAXI_DMA_BUSY3 0x1208
#define B_AX_RPQ_BUSY BIT(1)
#define B_AX_RXQ_BUSY BIT(0)
#define R_AX_RXQ_RXBD_NUM_V1 0x1210
#define R_AX_RPQ_RXBD_NUM_V1 0x1212
#define R_AX_RXQ_RXBD_IDX_V1 0x1218
#define R_AX_RPQ_RXBD_IDX_V1 0x121C
#define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
#define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
#define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
#define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
#define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
#define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
#define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
#define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
#define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
#define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
#define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
#define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
#define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
#define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
#define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
#define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
#define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
#define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
#define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
#define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
#define R_AX_CH8_TXBD_DESA_L_V1 0x1270
#define R_AX_CH8_TXBD_DESA_H_V1 0x1274
#define R_AX_CH9_TXBD_DESA_L_V1 0x1278
#define R_AX_CH9_TXBD_DESA_H_V1 0x127C
#define R_AX_CH12_TXBD_DESA_L_V1 0x1280
#define R_AX_CH12_TXBD_DESA_H_V1 0x1284
#define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
#define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
#define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
#define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
#define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
#define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
#define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
#define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
#define R_AX_CH8_BDRAM_CTRL_V1 0x1320
#define R_AX_CH9_BDRAM_CTRL_V1 0x1324
#define R_AX_CH12_BDRAM_CTRL_V1 0x1328
#define R_AX_CH10_BDRAM_CTRL_V1 0x1420
#define R_AX_CH11_BDRAM_CTRL_V1 0x1424
#define R_AX_CH10_TXBD_NUM_V1 0x1438
#define R_AX_CH11_TXBD_NUM_V1 0x143A
#define R_AX_CH10_TXBD_DESA_L_V1 0x1458
#define R_AX_CH10_TXBD_DESA_H_V1 0x145C
#define R_AX_CH11_TXBD_DESA_L_V1 0x1460
#define R_AX_CH11_TXBD_DESA_H_V1 0x1464
//
// WL_AX_Reg_PCIE.xls
//
//
// PCIE
//
#define R_AX_PCIE_INIT_CFG1 0x1000
#define B_AX_PCIE_RXRST_KEEP_REG BIT(23)
#define B_AX_PCIE_TXRST_KEEP_REG BIT(22)
#define B_AX_PCIE_PERST_KEEP_REG BIT(21)
#define B_AX_PCIE_FLR_KEEP_REG BIT(20)
#define B_AX_PCIE_TRAIN_KEEP_REG BIT(19)
#define B_AX_RXBD_MODE BIT(18)
#define B_AX_PCIE_MAX_RXDMA_SH 14
#define B_AX_PCIE_MAX_RXDMA_MSK 0x7
#define B_AX_RXHCI_EN BIT(13)
#define B_AX_LATENCY_CONTROL BIT(12)
#define B_AX_TXHCI_EN BIT(11)
#define B_AX_PCIE_MAX_TXDMA_SH 8
#define B_AX_PCIE_MAX_TXDMA_MSK 0x7
#define B_AX_TX_TRUNC_MODE BIT(5)
#define B_AX_RX_TRUNC_MODE BIT(4)
#define B_AX_RST_BDRAM BIT(3)
#define B_AX_DIS_RXDMA_PRE BIT(2)
#define R_AX_PCIE_INIT_CFG2 0x1004
#define B_AX_WD_ITVL_IDLE_SH 24
#define B_AX_WD_ITVL_IDLE_MSK 0xf
#define B_AX_WD_ITVL_ACT_SH 16
#define B_AX_WD_ITVL_ACT_MSK 0xf
#define B_AX_PCIE_RX_APPLEN_SH 0
#define B_AX_PCIE_RX_APPLEN_MSK 0x3fff
#define R_AX_PCIE_PS_CTRL 0x1008
#define B_AX_TXON_EXIT_L1_EN BIT(7)
#define B_AX_WD_NO_EMP_EXIT_L1_EN BIT(6)
#define B_AX_L1OFF_PWR_OFF_EN BIT(5)
#define B_AX_PCIE_FORCE_L0 BIT(4)
#define B_AX_TXFLAG_EXIT_L1_EN BIT(3)
#define B_AX_EN_HWENTR_L1 BIT(2)
#define B_AX_PCIE_EN_SWENT_L23 BIT(1)
#define B_AX_PCIE_EN_HWEXT_L1 BIT(0)
#define R_AX_PCIE_MIX_CFG 0x100C
#define B_AX_PCIE_T3_TIME_SH 22
#define B_AX_PCIE_T3_TIME_MSK 0x3
#define B_AX_PCIE_T2_TIME_SH 20
#define B_AX_PCIE_T2_TIME_MSK 0x3
#define B_AX_HOTRST_EN BIT(19)
#define B_AX_MDIO_MODE BIT(18)
#define B_AX_CHANGE_PCIE_SPEED BIT(16)
#define B_AX_GEN1_GEN2_SH 14
#define B_AX_GEN1_GEN2_MSK 0x3
#define B_AX_HPS_CLKR_PCIE_SH 12
#define B_AX_HPS_CLKR_PCIE_MSK 0x3
#define B_AX_PCIE_INT BIT(11)
#define B_AX_PCIEIO_PERSTB_SEL BIT(10)
#define B_AX_EPHY_RX50_EN BIT(8)
#define B_AX_MSI_TIMEOUT_ID_V1_SH 5
#define B_AX_MSI_TIMEOUT_ID_V1_MSK 0x7
#define B_AX_RADDR_RD BIT(4)
#define B_AX_ECRC_EN BIT(3)
#define B_AX_EN_SLOW_MAC_TX BIT(2)
#define B_AX_EN_SLOW_MAC_RX BIT(1)
#define B_AX_EN_SLOW_MAC_HW BIT(0)
#define R_AX_PCIE_DMA_STOP1 0x1010
#define B_AX_STOP_PCIEIO BIT(20)
#define B_AX_STOP_WPDMA BIT(19)
#define B_AX_STOP_CH12 BIT(18)
#define B_AX_STOP_CH9 BIT(17)
#define B_AX_STOP_CH8 BIT(16)
#define B_AX_STOP_ACH7 BIT(15)
#define B_AX_STOP_ACH6 BIT(14)
#define B_AX_STOP_ACH5 BIT(13)
#define B_AX_STOP_ACH4 BIT(12)
#define B_AX_STOP_ACH3 BIT(11)
#define B_AX_STOP_ACH2 BIT(10)
#define B_AX_STOP_ACH1 BIT(9)
#define B_AX_STOP_ACH0 BIT(8)
#define R_AX_TXBD_RWPTR_CLR1 0x1014
#define B_AX_CLR_CH12_IDX BIT(10)
#define B_AX_CLR_CH9_IDX BIT(9)
#define B_AX_CLR_CH8_IDX BIT(8)
#define B_AX_CLR_ACH7_IDX BIT(7)
#define B_AX_CLR_ACH6_IDX BIT(6)
#define B_AX_CLR_ACH5_IDX BIT(5)
#define B_AX_CLR_ACH4_IDX BIT(4)
#define B_AX_CLR_ACH3_IDX BIT(3)
#define B_AX_CLR_ACH2_IDX BIT(2)
#define B_AX_CLR_ACH1_IDX BIT(1)
#define B_AX_CLR_ACH0_IDX BIT(0)
#define R_AX_RXBD_RWPTR_CLR 0x1018
#define B_AX_CLR_RPQ_IDX BIT(1)
#define B_AX_CLR_RXQ_IDX BIT(0)
#define R_AX_PCIE_DMA_BUSY1 0x101C
#define B_AX_PCIEIO_RX_BUSY BIT(22)
#define B_AX_PCIEIO_TX_BUSY BIT(21)
#define B_AX_PCIEIO_BUSY BIT(20)
#define B_AX_WPDMA_BUSY BIT(19)
#define B_AX_CH12_BUSY BIT(18)
#define B_AX_CH9_BUSY BIT(17)
#define B_AX_CH8_BUSY BIT(16)
#define B_AX_ACH7_BUSY BIT(15)
#define B_AX_ACH6_BUSY BIT(14)
#define B_AX_ACH5_BUSY BIT(13)
#define B_AX_ACH4_BUSY BIT(12)
#define B_AX_ACH3_BUSY BIT(11)
#define B_AX_ACH2_BUSY BIT(10)
#define B_AX_ACH1_BUSY BIT(9)
#define B_AX_ACH0_BUSY BIT(8)
#define B_AX_RPQ_BUSY BIT(1)
#define B_AX_RXQ_BUSY BIT(0)
#define R_AX_RXQ_RXBD_NUM 0x1020
#define B_AX_RXQ_DESC_NUM_SH 0
#define B_AX_RXQ_DESC_NUM_MSK 0xfff
#define R_AX_RPQ_RXBD_NUM 0x1022
#define B_AX_RPQ_DESC_NUM_SH 0
#define B_AX_RPQ_DESC_NUM_MSK 0xfff
#define R_AX_ACH0_TXBD_NUM 0x1024
#define B_AX_PCIE_ACH0_FLAG BIT(14)
#define B_AX_ACH0_DESC_NUM_SH 0
#define B_AX_ACH0_DESC_NUM_MSK 0xfff
#define R_AX_ACH1_TXBD_NUM 0x1026
#define B_AX_PCIE_ACH1_FLAG BIT(14)
#define B_AX_ACH1_DESC_NUM_SH 0
#define B_AX_ACH1_DESC_NUM_MSK 0xfff
#define R_AX_ACH2_TXBD_NUM 0x1028
#define B_AX_PCIE_ACH2_FLAG BIT(14)
#define B_AX_ACH2_DESC_NUM_SH 0
#define B_AX_ACH2_DESC_NUM_MSK 0xfff
#define R_AX_ACH3_TXBD_NUM 0x102A
#define B_AX_PCIE_ACH3_FLAG BIT(14)
#define B_AX_ACH3_DESC_NUM_SH 0
#define B_AX_ACH3_DESC_NUM_MSK 0xfff
#define R_AX_ACH4_TXBD_NUM 0x102C
#define B_AX_PCIE_ACH4_FLAG BIT(14)
#define B_AX_ACH4_DESC_NUM_SH 0
#define B_AX_ACH4_DESC_NUM_MSK 0xfff
#define R_AX_ACH5_TXBD_NUM 0x102E
#define B_AX_PCIE_ACH5_FLAG BIT(14)
#define B_AX_ACH5_DESC_NUM_SH 0
#define B_AX_ACH5_DESC_NUM_MSK 0xfff
#define R_AX_ACH6_TXBD_NUM 0x1030
#define B_AX_PCIE_ACH6_FLAG BIT(14)
#define B_AX_ACH6_DESC_NUM_SH 0
#define B_AX_ACH6_DESC_NUM_MSK 0xfff
#define R_AX_ACH7_TXBD_NUM 0x1032
#define B_AX_PCIE_ACH7_FLAG BIT(14)
#define B_AX_ACH7_DESC_NUM_SH 0
#define B_AX_ACH7_DESC_NUM_MSK 0xfff
#define R_AX_CH8_TXBD_NUM 0x1034
#define B_AX_PCIE_CH8_FLAG BIT(14)
#define B_AX_CH8_DESC_NUM_SH 0
#define B_AX_CH8_DESC_NUM_MSK 0xfff
#define R_AX_CH9_TXBD_NUM 0x1036
#define B_AX_PCIE_CH9_FLAG BIT(14)
#define B_AX_CH9_DESC_NUM_SH 0
#define B_AX_CH9_DESC_NUM_MSK 0xfff
#define R_AX_CH12_TXBD_NUM 0x1038
#define B_AX_PCIE_CH12_FLAG BIT(14)
#define B_AX_CH12_DESC_NUM_SH 0
#define B_AX_CH12_DESC_NUM_MSK 0xfff
#define R_AX_RXQ_RXBD_IDX 0x1050
#define B_AX_RXQ_HW_IDX_SH 16
#define B_AX_RXQ_HW_IDX_MSK 0xfff
#define B_AX_RXQ_HOST_IDX_SH 0
#define B_AX_RXQ_HOST_IDX_MSK 0xfff
#define R_AX_RPQ_RXBD_IDX 0x1054
#define B_AX_RPQ_HW_IDX_SH 16
#define B_AX_RPQ_HW_IDX_MSK 0xfff
#define B_AX_RPQ_HOST_IDX_SH 0
#define B_AX_RPQ_HOST_IDX_MSK 0xfff
#define R_AX_ACH0_TXBD_IDX 0x1058
#define B_AX_ACH0_HW_IDX_SH 16
#define B_AX_ACH0_HW_IDX_MSK 0xfff
#define B_AX_ACH0_HOST_IDX_SH 0
#define B_AX_ACH0_HOST_IDX_MSK 0xfff
#define R_AX_ACH1_TXBD_IDX 0x105C
#define B_AX_ACH1_HW_IDX_SH 16
#define B_AX_ACH1_HW_IDX_MSK 0xfff
#define B_AX_ACH1_HOST_IDX_SH 0
#define B_AX_ACH1_HOST_IDX_MSK 0xfff
#define R_AX_ACH2_TXBD_IDX 0x1060
#define B_AX_ACH2_HW_IDX_SH 16
#define B_AX_ACH2_HW_IDX_MSK 0xfff
#define B_AX_ACH2_HOST_IDX_SH 0
#define B_AX_ACH2_HOST_IDX_MSK 0xfff
#define R_AX_ACH3_TXBD_IDX 0x1064
#define B_AX_ACH3_HW_IDX_SH 16
#define B_AX_ACH3_HW_IDX_MSK 0xfff
#define B_AX_ACH3_HOST_IDX_SH 0
#define B_AX_ACH3_HOST_IDX_MSK 0xfff
#define R_AX_ACH4_TXBD_IDX 0x1068
#define B_AX_ACH4_HW_IDX_SH 16
#define B_AX_ACH4_HW_IDX_MSK 0xfff
#define B_AX_ACH4_HOST_IDX_SH 0
#define B_AX_ACH4_HOST_IDX_MSK 0xfff
#define R_AX_ACH5_TXBD_IDX 0x106C
#define B_AX_ACH5_HW_IDX_SH 16
#define B_AX_ACH5_HW_IDX_MSK 0xfff
#define B_AX_ACH5_HOST_IDX_SH 0
#define B_AX_ACH5_HOST_IDX_MSK 0xfff
#define R_AX_ACH6_TXBD_IDX 0x1070
#define B_AX_ACH6_HW_IDX_SH 16
#define B_AX_ACH6_HW_IDX_MSK 0xfff
#define B_AX_ACH6_HOST_IDX_SH 0
#define B_AX_ACH6_HOST_IDX_MSK 0xfff
#define R_AX_ACH7_TXBD_IDX 0x1074
#define B_AX_ACH7_HW_IDX_SH 16
#define B_AX_ACH7_HW_IDX_MSK 0xfff
#define B_AX_ACH7_HOST_IDX_SH 0
#define B_AX_ACH7_HOST_IDX_MSK 0xfff
#define R_AX_CH8_TXBD_IDX 0x1078
#define B_AX_CH8_HW_IDX_SH 16
#define B_AX_CH8_HW_IDX_MSK 0xfff
#define B_AX_CH8_HOST_IDX_SH 0
#define B_AX_CH8_HOST_IDX_MSK 0xfff
#define R_AX_CH9_TXBD_IDX 0x107C
#define B_AX_CH9_HW_IDX_SH 16
#define B_AX_CH9_HW_IDX_MSK 0xfff
#define B_AX_CH9_HOST_IDX_SH 0
#define B_AX_CH9_HOST_IDX_MSK 0xfff
#define R_AX_CH12_TXBD_IDX 0x1080
#define B_AX_CH12_HW_IDX_SH 16
#define B_AX_CH12_HW_IDX_MSK 0xfff
#define B_AX_CH12_HOST_IDX_SH 0
#define B_AX_CH12_HOST_IDX_MSK 0xfff
#define R_AX_DBI_FLAG 0x1090
#define B_AX_DBI_RFLAG BIT(17)
#define B_AX_DBI_WFLAG BIT(16)
#define B_AX_DBI_WREN_SH 12
#define B_AX_DBI_WREN_MSK 0xf
#define B_AX_DBI_ADDR_SH 0
#define B_AX_DBI_ADDR_MSK 0xfff
#define R_AX_DBI_WDATA 0x1094
#define B_AX_DBI_WDATA_SH 0
#define B_AX_DBI_WDATA_MSK 0xffffffffL
#define R_AX_DBI_RDATA 0x1098
#define B_AX_DBI_RDATA_SH 0
#define B_AX_DBI_RDATA_MSK 0xffffffffL
#define R_AX_MDIO_CFG 0x10A0
#define B_AX_MDIO_PHY_ADDR_SH 12
#define B_AX_MDIO_PHY_ADDR_MSK 0x3
#define B_AX_MDIO_RFLAG BIT(9)
#define B_AX_MDIO_WFLAG BIT(8)
#define B_AX_MDIO_ADDR_SH 0
#define B_AX_MDIO_ADDR_MSK 0x1f
#define R_AX_MDIO_WDATA 0x10A4
#define B_AX_MDIO_WDATA_SH 0
#define B_AX_MDIO_WDATA_MSK 0xffff
#define R_AX_MDIO_RDATA 0x10A6
#define B_AX_MDIO_RDATA_SH 0
#define B_AX_MDIO_RDATA_MSK 0xffff
#define R_AX_PCIE_HIMR00 0x10B0
#define B_AX_HC00ISR_IND_INT_EN BIT(27)
#define B_AX_HD1ISR_IND_INT_EN BIT(26)
#define B_AX_HD0ISR_IND_INT_EN BIT(25)
#define B_AX_HS0ISR_IND_INT_EN BIT(24)
#define B_AX_RETRAIN_INT_EN BIT(21)
#define B_AX_RPQBD_FULL_INT_EN BIT(20)
#define B_AX_RDU_INT_EN BIT(19)
#define B_AX_RXDMA_STUCK_INT_EN BIT(18)
#define B_AX_TXDMA_STUCK_INT_EN BIT(17)
#define B_AX_PCIE_HOTRST_INT_EN BIT(16)
#define B_AX_PCIE_FLR_INT_EN BIT(15)
#define B_AX_PCIE_PERST_INT_EN BIT(14)
#define B_AX_TXDMA_CH12_INT_EN BIT(13)
#define B_AX_TXDMA_CH9_INT_EN BIT(12)
#define B_AX_TXDMA_CH8_INT_EN BIT(11)
#define B_AX_TXDMA_ACH7_INT_EN BIT(10)
#define B_AX_TXDMA_ACH6_INT_EN BIT(9)
#define B_AX_TXDMA_ACH5_INT_EN BIT(8)
#define B_AX_TXDMA_ACH4_INT_EN BIT(7)
#define B_AX_TXDMA_ACH3_INT_EN BIT(6)
#define B_AX_TXDMA_ACH2_INT_EN BIT(5)
#define B_AX_TXDMA_ACH1_INT_EN BIT(4)
#define B_AX_TXDMA_ACH0_INT_EN BIT(3)
#define B_AX_RPQDMA_INT_EN BIT(2)
#define B_AX_RXP1DMA_INT_EN BIT(1)
#define B_AX_RXDMA_INT_EN BIT(0)
#define R_AX_PCIE_HISR00 0x10B4
#define B_AX_HC00ISR_IND_INT BIT(27)
#define B_AX_HD1ISR_IND_INT BIT(26)
#define B_AX_HD0ISR_IND_INT BIT(25)
#define B_AX_HS0ISR_IND_INT BIT(24)
#define B_AX_RETRAIN_INT BIT(21)
#define B_AX_RPQBD_FULL_INT BIT(20)
#define B_AX_RDU_INT BIT(19)
#define B_AX_RXDMA_STUCK_INT BIT(18)
#define B_AX_TXDMA_STUCK_INT BIT(17)
#define B_AX_PCIE_HOTRST_INT BIT(16)
#define B_AX_PCIE_FLR_INT BIT(15)
#define B_AX_PCIE_PERST_INT BIT(14)
#define B_AX_TXDMA_CH12_INT BIT(13)
#define B_AX_TXDMA_CH9_INT BIT(12)
#define B_AX_TXDMA_CH8_INT BIT(11)
#define B_AX_TXDMA_ACH7_INT BIT(10)
#define B_AX_TXDMA_ACH6_INT BIT(9)
#define B_AX_TXDMA_ACH5_INT BIT(8)
#define B_AX_TXDMA_ACH4_INT BIT(7)
#define B_AX_TXDMA_ACH3_INT BIT(6)
#define B_AX_TXDMA_ACH2_INT BIT(5)
#define B_AX_TXDMA_ACH1_INT BIT(4)
#define B_AX_TXDMA_ACH0_INT BIT(3)
#define B_AX_RPQDMA_INT BIT(2)
#define B_AX_RXP1DMA_INT BIT(1)
#define B_AX_RXDMA_INT BIT(0)
#define R_AX_PCIE_HRPWM 0x10C0
#define B_AX_PCIE_HRPWM_SH 0
#define B_AX_PCIE_HRPWM_MSK 0xffff
#define R_AX_INT_MIT_TX 0x10D0
#define B_AX_TXMIT_CH12_SEL BIT(31)
#define B_AX_TXMIT_CH11_SEL BIT(30)
#define B_AX_TXMIT_CH10_SEL BIT(29)
#define B_AX_TXMIT_CH9_SEL BIT(28)
#define B_AX_TXMIT_CH8_SEL BIT(27)
#define B_AX_TXMIT_ACH7_SEL BIT(26)
#define B_AX_TXMIT_ACH6_SEL BIT(25)
#define B_AX_TXMIT_ACH5_SEL BIT(24)
#define B_AX_TXMIT_ACH4_SEL BIT(23)
#define B_AX_TXMIT_ACH3_SEL BIT(22)
#define B_AX_TXMIT_ACH2_SEL BIT(21)
#define B_AX_TXMIT_ACH1_SEL BIT(20)
#define B_AX_TXMIT_ACH0_SEL BIT(19)
#define B_AX_TXTIMER_UNIT_SH 16
#define B_AX_TXTIMER_UNIT_MSK 0x3
#define B_AX_TXCOUNTER_MATCH_SH 8
#define B_AX_TXCOUNTER_MATCH_MSK 0xff
#define B_AX_TXTIMER_MATCH_SH 0
#define B_AX_TXTIMER_MATCH_MSK 0xff
#define R_AX_INT_MIT_RX 0x10D4
#define B_AX_RXMIT_RXP2_SEL BIT(19)
#define B_AX_RXMIT_RXP1_SEL BIT(18)
#define B_AX_RXTIMER_UNIT_SH 16
#define B_AX_RXTIMER_UNIT_MSK 0x3
#define B_AX_RXCOUNTER_MATCH_SH 8
#define B_AX_RXCOUNTER_MATCH_MSK 0xff
#define B_AX_RXTIMER_MATCH_SH 0
#define B_AX_RXTIMER_MATCH_MSK 0xff
#define R_AX_TXDMA_ADDR_H 0x10F0
#define B_AX_TXDMA_ADDR_H_SH 0
#define B_AX_TXDMA_ADDR_H_MSK 0xffffffffL
#define R_AX_RXDMA_ADDR_H 0x10F4
#define B_AX_RXDMA_ADDR_H_SH 0
#define B_AX_RXDMA_ADDR_H_MSK 0xffffffffL
#define R_AX_PCIE_INFO 0x10F8
#define B_AX_HOST_GEN2_SUPPORT BIT(4)
#define B_AX_ACT_LINK_OFF BIT(2)
#define B_AX_PCIERX_IDLE BIT(1)
#define B_AX_PCIETX_IDLE BIT(0)
#define R_AX_TSFTIMER_HCI 0x10FC
#define B_AX_TSFT2_HCI_SH 16
#define B_AX_TSFT2_HCI_MSK 0xffff
#define B_AX_TSFT1_HCI_SH 0
#define B_AX_TSFT1_HCI_MSK 0xffff
#define R_AX_RXQ_RXBD_DESA_L 0x1100
#define B_AX_RXQ_RXBD_DESA_L_SH 0
#define B_AX_RXQ_RXBD_DESA_L_MSK 0xffffffffL
#define R_AX_RXQ_RXBD_DESA_H 0x1104
#define B_AX_RXQ_RXBD_DESA_H_SH 0
#define B_AX_RXQ_RXBD_DESA_H_MSK 0xffffffffL
#define R_AX_RPQ_RXBD_DESA_L 0x1108
#define B_AX_RPQ_RXBD_DESA_L_SH 0
#define B_AX_RPQ_RXBD_DESA_L_MSK 0xffffffffL
#define R_AX_RPQ_RXBD_DESA_H 0x110C
#define B_AX_RPQ_RXBD_DESA_H_SH 0
#define B_AX_RPQ_RXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH0_TXBD_DESA_L 0x1110
#define B_AX_ACH0_TXBD_DESA_L_SH 0
#define B_AX_ACH0_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH0_TXBD_DESA_H 0x1114
#define B_AX_ACH0_TXBD_DESA_H_SH 0
#define B_AX_ACH0_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH1_TXBD_DESA_L 0x1118
#define B_AX_ACH1_TXBD_DESA_L_SH 0
#define B_AX_ACH1_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH1_TXBD_DESA_H 0x111C
#define B_AX_ACH1_TXBD_DESA_H_SH 0
#define B_AX_ACH1_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH2_TXBD_DESA_L 0x1120
#define B_AX_ACH2_TXBD_DESA_L_SH 0
#define B_AX_ACH2_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH2_TXBD_DESA_H 0x1124
#define B_AX_ACH2_TXBD_DESA_H_SH 0
#define B_AX_ACH2_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH3_TXBD_DESA_L 0x1128
#define B_AX_ACH3_TXBD_DESA_L_SH 0
#define B_AX_ACH3_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH3_TXBD_DESA_H 0x112C
#define B_AX_ACH3_TXBD_DESA_H_SH 0
#define B_AX_ACH3_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH4_TXBD_DESA_L 0x1130
#define B_AX_ACH4_TXBD_DESA_L_SH 0
#define B_AX_ACH4_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH4_TXBD_DESA_H 0x1134
#define B_AX_ACH4_TXBD_DESA_H_SH 0
#define B_AX_ACH4_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH5_TXBD_DESA_L 0x1138
#define B_AX_ACH5_TXBD_DESA_L_SH 0
#define B_AX_ACH5_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH5_TXBD_DESA_H 0x113C
#define B_AX_ACH5_TXBD_DESA_H_SH 0
#define B_AX_ACH5_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH6_TXBD_DESA_L 0x1140
#define B_AX_ACH6_TXBD_DESA_L_SH 0
#define B_AX_ACH6_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH6_TXBD_DESA_H 0x1144
#define B_AX_ACH6_TXBD_DESA_H_SH 0
#define B_AX_ACH6_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_ACH7_TXBD_DESA_L 0x1148
#define B_AX_ACH7_TXBD_DESA_L_SH 0
#define B_AX_ACH7_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_ACH7_TXBD_DESA_H 0x114C
#define B_AX_ACH7_TXBD_DESA_H_SH 0
#define B_AX_ACH7_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_CH8_TXBD_DESA_L 0x1150
#define B_AX_CH8_TXBD_DESA_L_SH 0
#define B_AX_CH8_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_CH8_TXBD_DESA_H 0x1154
#define B_AX_CH8_TXBD_DESA_H_SH 0
#define B_AX_CH8_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_CH9_TXBD_DESA_L 0x1158
#define B_AX_CH9_TXBD_DESA_L_SH 0
#define B_AX_CH9_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_CH9_TXBD_DESA_H 0x115C
#define B_AX_CH9_TXBD_DESA_H_SH 0
#define B_AX_CH9_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_CH12_TXBD_DESA_L 0x1160
#define B_AX_CH12_TXBD_DESA_L_SH 0
#define B_AX_CH12_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_CH12_TXBD_DESA_H 0x1164
#define B_AX_CH12_TXBD_DESA_H_SH 0
#define B_AX_CH12_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_PCIE_DBG_CTRL 0x11C0
#define B_AX_DBG_DUMMY_SH 16
#define B_AX_DBG_DUMMY_MSK 0xff
#define B_AX_DBG_SEL_SH 13
#define B_AX_DBG_SEL_MSK 0x7
#define B_AX_PCIE_DBG_SEL BIT(12)
#define B_AX_MRD_TIMEOUT_EN BIT(10)
#define B_AX_ASFF_FULL_NO_STK BIT(1)
#define B_AX_EN_STUCK_DBG BIT(0)
#define R_AX_DBG_ERR_FLAG 0x11C4
#define B_AX_PCIE_RPQ_FULL BIT(29)
#define B_AX_PCIE_RXQ_FULL BIT(28)
#define B_AX_CPL_STATUS_SH 25
#define B_AX_CPL_STATUS_MSK 0x7
#define B_AX_RX_STUCK BIT(22)
#define B_AX_TX_STUCK BIT(21)
#define B_AX_PCIEDBG_TXERR0 BIT(16)
#define B_AX_PCIE_RXP1_ERR0 BIT(4)
#define B_AX_PCIE_TXBD_LEN0 BIT(1)
#define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
#define R_AX_PCIE_LPWR_DBG 0x11C8
#define B_AX_PCIE_L1_COND_CFG_SPC BIT(10)
#define B_AX_PCIE_L1_COND_MAC_REG BIT(9)
#define B_AX_PCIE_L1_COND_HISR BIT(8)
#define B_AX_PCIE_L1_COND_RX BIT(7)
#define B_AX_PCIE_L1_COND_TX BIT(6)
#define B_AX_PCIE_L1_COND_HDP_RX BIT(5)
#define B_AX_PCIE_L1_COND_LTR BIT(4)
#define B_AX_PCIE_L1_COND_FORC_L0 BIT(3)
#define B_AX_PCIE_L1_COND_WD_EMPY BIT(2)
#define B_AX_PCIE_L1_COND_TXFLAG1 BIT(1)
#define B_AX_PCIE_L1_COND_TXFLAG0 BIT(0)
#define R_AX_STC_INT_CS 0x11D0
#define B_AX_STC_INT_EN BIT(31)
#define B_AX_STC_INT_FLAG_SH 16
#define B_AX_STC_INT_FLAG_MSK 0xff
#define B_AX_STC_INT_IDX_SH 8
#define B_AX_STC_INT_IDX_MSK 0x7
#define B_AX_STC_INT_REALTIME_CS_SH 0
#define B_AX_STC_INT_REALTIME_CS_MSK 0x3f
#define R_AX_ST_INT_CFG 0x11D4
#define B_AX_STC_INT_GRP_EN BIT(31)
#define B_AX_STC_INT_EXPECT_LS_SH 8
#define B_AX_STC_INT_EXPECT_LS_MSK 0x3f
#define B_AX_STC_INT_EXPECT_CS_SH 0
#define B_AX_STC_INT_EXPECT_CS_MSK 0x3f
#define R_AX_LBC_WATCHDOG 0x11D8
#define B_AX_LBC_ADDR_SH 10
#define B_AX_LBC_ADDR_MSK 0x3ffff
#define B_AX_LBC_TIMER_SH 4
#define B_AX_LBC_TIMER_MSK 0xf
#define B_AX_LBC_FLAG BIT(1)
#define B_AX_LBC_EN BIT(0)
#define R_AX_DEBUG_STATE1 0x11E0
#define B_AX_DEBUG_STATE1_SH 0
#define B_AX_DEBUG_STATE1_MSK 0xffffffffL
#define R_AX_DEBUG_STATE2 0x11E4
#define B_AX_DEBUG_STATE2_SH 0
#define B_AX_DEBUG_STATE2_MSK 0xffffffffL
#define R_AX_DEBUG_STATE3 0x11E8
#define B_AX_DEBUG_STATE3_SH 0
#define B_AX_DEBUG_STATE3_MSK 0xffffffffL
#define R_AX_ACH0_BDRAM_CTRL 0x1200
#define B_AX_ACH0_BDRAM_MIN_SH 16
#define B_AX_ACH0_BDRAM_MIN_MSK 0xff
#define B_AX_ACH0_BDRAM_MAX_SH 8
#define B_AX_ACH0_BDRAM_MAX_MSK 0xff
#define B_AX_ACH0_BDRAM_SIDX_SH 0
#define B_AX_ACH0_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH1_BDRAM_CTRL 0x1204
#define B_AX_ACH1_BDRAM_MIN_SH 16
#define B_AX_ACH1_BDRAM_MIN_MSK 0xff
#define B_AX_ACH1_BDRAM_MAX_SH 8
#define B_AX_ACH1_BDRAM_MAX_MSK 0xff
#define B_AX_ACH1_BDRAM_SIDX_SH 0
#define B_AX_ACH1_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH2_BDRAM_CTRL 0x1208
#define B_AX_ACH2_BDRAM_MIN_SH 16
#define B_AX_ACH2_BDRAM_MIN_MSK 0xff
#define B_AX_ACH2_BDRAM_MAX_SH 8
#define B_AX_ACH2_BDRAM_MAX_MSK 0xff
#define B_AX_ACH2_BDRAM_SIDX_SH 0
#define B_AX_ACH2_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH3_BDRAM_CTRL 0x120C
#define B_AX_ACH3_BDRAM_MIN_SH 16
#define B_AX_ACH3_BDRAM_MIN_MSK 0xff
#define B_AX_ACH3_BDRAM_MAX_SH 8
#define B_AX_ACH3_BDRAM_MAX_MSK 0xff
#define B_AX_ACH3_BDRAM_SIDX_SH 0
#define B_AX_ACH3_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH4_BDRAM_CTRL 0x1210
#define B_AX_ACH4_BDRAM_MIN_SH 16
#define B_AX_ACH4_BDRAM_MIN_MSK 0xff
#define B_AX_ACH4_BDRAM_MAX_SH 8
#define B_AX_ACH4_BDRAM_MAX_MSK 0xff
#define B_AX_ACH4_BDRAM_SIDX_SH 0
#define B_AX_ACH4_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH5_BDRAM_CTRL 0x1214
#define B_AX_ACH5_BDRAM_MIN_SH 16
#define B_AX_ACH5_BDRAM_MIN_MSK 0xff
#define B_AX_ACH5_BDRAM_MAX_SH 8
#define B_AX_ACH5_BDRAM_MAX_MSK 0xff
#define B_AX_ACH5_BDRAM_SIDX_SH 0
#define B_AX_ACH5_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH6_BDRAM_CTRL 0x1218
#define B_AX_ACH6_BDRAM_MIN_SH 16
#define B_AX_ACH6_BDRAM_MIN_MSK 0xff
#define B_AX_ACH6_BDRAM_MAX_SH 8
#define B_AX_ACH6_BDRAM_MAX_MSK 0xff
#define B_AX_ACH6_BDRAM_SIDX_SH 0
#define B_AX_ACH6_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH7_BDRAM_CTRL 0x121C
#define B_AX_ACH7_BDRAM_MIN_SH 16
#define B_AX_ACH7_BDRAM_MIN_MSK 0xff
#define B_AX_ACH7_BDRAM_MAX_SH 8
#define B_AX_ACH7_BDRAM_MAX_MSK 0xff
#define B_AX_ACH7_BDRAM_SIDX_SH 0
#define B_AX_ACH7_BDRAM_SIDX_MSK 0xff
#define R_AX_CH8_BDRAM_CTRL 0x1220
#define B_AX_CH8_BDRAM_MIN_SH 16
#define B_AX_CH8_BDRAM_MIN_MSK 0xff
#define B_AX_CH8_BDRAM_MAX_SH 8
#define B_AX_CH8_BDRAM_MAX_MSK 0xff
#define B_AX_CH8_BDRAM_SIDX_SH 0
#define B_AX_CH8_BDRAM_SIDX_MSK 0xff
#define R_AX_CH9_BDRAM_CTRL 0x1224
#define B_AX_CH9_BDRAM_MIN_SH 16
#define B_AX_CH9_BDRAM_MIN_MSK 0xff
#define B_AX_CH9_BDRAM_MAX_SH 8
#define B_AX_CH9_BDRAM_MAX_MSK 0xff
#define B_AX_CH9_BDRAM_SIDX_SH 0
#define B_AX_CH9_BDRAM_SIDX_MSK 0xff
#define R_AX_CH12_BDRAM_CTRL 0x1228
#define B_AX_CH12_BDRAM_MIN_SH 16
#define B_AX_CH12_BDRAM_MIN_MSK 0xff
#define B_AX_CH12_BDRAM_MAX_SH 8
#define B_AX_CH12_BDRAM_MAX_MSK 0xff
#define B_AX_CH12_BDRAM_SIDX_SH 0
#define B_AX_CH12_BDRAM_SIDX_MSK 0xff
#define R_AX_ACH0_BDRAM_RWPTR 0x1230
#define B_AX_ACH0_BDRAM_WPTR_SH 8
#define B_AX_ACH0_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH0_BDRAM_RPTR_SH 0
#define B_AX_ACH0_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH1_BDRAM_RWPTR 0x1232
#define B_AX_ACH1_BDRAM_WPTR_SH 8
#define B_AX_ACH1_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH1_BDRAM_RPTR_SH 0
#define B_AX_ACH1_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH2_BDRAM_RWPTR 0x1234
#define B_AX_ACH2_BDRAM_WPTR_SH 8
#define B_AX_ACH2_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH2_BDRAM_RPTR_SH 0
#define B_AX_ACH2_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH3_BDRAM_RWPTR 0x1236
#define B_AX_ACH3_BDRAM_WPTR_SH 8
#define B_AX_ACH3_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH3_BDRAM_RPTR_SH 0
#define B_AX_ACH3_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH4_BDRAM_RWPTR 0x1238
#define B_AX_ACH4_BDRAM_WPTR_SH 8
#define B_AX_ACH4_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH4_BDRAM_RPTR_SH 0
#define B_AX_ACH4_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH5_BDRAM_RWPTR 0x123A
#define B_AX_ACH5_BDRAM_WPTR_SH 8
#define B_AX_ACH5_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH5_BDRAM_RPTR_SH 0
#define B_AX_ACH5_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH6_BDRAM_RWPTR 0x123C
#define B_AX_ACH6_BDRAM_WPTR_SH 8
#define B_AX_ACH6_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH6_BDRAM_RPTR_SH 0
#define B_AX_ACH6_BDRAM_RPTR_MSK 0xff
#define R_AX_ACH7_BDRAM_RWPTR 0x123E
#define B_AX_ACH7_BDRAM_WPTR_SH 8
#define B_AX_ACH7_BDRAM_WPTR_MSK 0xff
#define B_AX_ACH7_BDRAM_RPTR_SH 0
#define B_AX_ACH7_BDRAM_RPTR_MSK 0xff
#define R_AX_CH8_BDRAM_RWPTR 0x1240
#define B_AX_CH8_BDRAM_WPTR_SH 8
#define B_AX_CH8_BDRAM_WPTR_MSK 0xff
#define B_AX_CH8_BDRAM_RPTR_SH 0
#define B_AX_CH8_BDRAM_RPTR_MSK 0xff
#define R_AX_CH9_BDRAM_RWPTR 0x1242
#define B_AX_CH9_BDRAM_WPTR_SH 8
#define B_AX_CH9_BDRAM_WPTR_MSK 0xff
#define B_AX_CH9_BDRAM_RPTR_SH 0
#define B_AX_CH9_BDRAM_RPTR_MSK 0xff
#define R_AX_CH12_BDRAM_RWPTR 0x1244
#define B_AX_CH12_BDRAM_WPTR_SH 8
#define B_AX_CH12_BDRAM_WPTR_MSK 0xff
#define B_AX_CH12_BDRAM_RPTR_SH 0
#define B_AX_CH12_BDRAM_RPTR_MSK 0xff
#define R_AX_PCIE_DMA_STOP2 0x1310
#define B_AX_STOP_CH11 BIT(1)
#define B_AX_STOP_CH10 BIT(0)
#define R_AX_TXBD_RWPTR_CLR2 0x1314
#define B_AX_CLR_CH11_IDX BIT(1)
#define B_AX_CLR_CH10_IDX BIT(0)
#define R_AX_PCIE_DMA_BUSY2 0x131C
#define B_AX_CH11_BUSY BIT(1)
#define B_AX_CH10_BUSY BIT(0)
#define R_AX_CH10_BDRAM_CTRL 0x1320
#define B_AX_CH10_BDRAM_MIN_SH 16
#define B_AX_CH10_BDRAM_MIN_MSK 0xff
#define B_AX_CH10_BDRAM_MAX_SH 8
#define B_AX_CH10_BDRAM_MAX_MSK 0xff
#define B_AX_CH10_BDRAM_SIDX_SH 0
#define B_AX_CH10_BDRAM_SIDX_MSK 0xff
#define R_AX_CH11_BDRAM_CTRL 0x1324
#define B_AX_CH11_BDRAM_MIN_SH 16
#define B_AX_CH11_BDRAM_MIN_MSK 0xff
#define B_AX_CH11_BDRAM_MAX_SH 8
#define B_AX_CH11_BDRAM_MAX_MSK 0xff
#define B_AX_CH11_BDRAM_SIDX_SH 0
#define B_AX_CH11_BDRAM_SIDX_MSK 0xff
#define R_AX_CH10_BDRAM_RWPTR 0x1340
#define B_AX_CH10_BDRAM_WPTR_SH 8
#define B_AX_CH10_BDRAM_WPTR_MSK 0xff
#define B_AX_CH10_BDRAM_RPTR_SH 0
#define B_AX_CH10_BDRAM_RPTR_MSK 0xff
#define R_AX_CH11_BDRAM_RWPTR 0x1342
#define B_AX_CH11_BDRAM_WPTR_SH 8
#define B_AX_CH11_BDRAM_WPTR_MSK 0xff
#define B_AX_CH11_BDRAM_RPTR_SH 0
#define B_AX_CH11_BDRAM_RPTR_MSK 0xff
#define R_AX_CH10_TXBD_NUM 0x1338
#define B_AX_PCIE_CH10_FLAG BIT(14)
#define B_AX_CH10_DESC_NUM_SH 0
#define B_AX_CH10_DESC_NUM_MSK 0xfff
#define R_AX_CH11_TXBD_NUM 0x133A
#define B_AX_PCIE_CH11_FLAG BIT(14)
#define B_AX_CH11_DESC_NUM_SH 0
#define B_AX_CH11_DESC_NUM_MSK 0xfff
#define R_AX_CH10_TXBD_DESA_L 0x1358
#define B_AX_CH10_TXBD_DESA_L_SH 0
#define B_AX_CH10_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_CH10_TXBD_DESA_H 0x135C
#define B_AX_CH10_TXBD_DESA_H_SH 0
#define B_AX_CH10_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_CH11_TXBD_DESA_L 0x1360
#define B_AX_CH11_TXBD_DESA_L_SH 0
#define B_AX_CH11_TXBD_DESA_L_MSK 0xffffffffL
#define R_AX_CH11_TXBD_DESA_H 0x1364
#define B_AX_CH11_TXBD_DESA_H_SH 0
#define B_AX_CH11_TXBD_DESA_H_MSK 0xffffffffL
#define R_AX_CH10_TXBD_IDX 0x137C
#define B_AX_CH10_HW_IDX_SH 16
#define B_AX_CH10_HW_IDX_MSK 0xfff
#define B_AX_CH10_HOST_IDX_SH 0
#define B_AX_CH10_HOST_IDX_MSK 0xfff
#define R_AX_CH11_TXBD_IDX 0x1380
#define B_AX_CH11_HW_IDX_SH 16
#define B_AX_CH11_HW_IDX_MSK 0xfff
#define B_AX_CH11_HOST_IDX_SH 0
#define B_AX_CH11_HOST_IDX_MSK 0xfff
#define R_AX_PCIE_HIMR10 0x13B0
#define B_AX_HC10ISR_IND_INT_EN BIT(28)
#define B_AX_TXDMA_CH11_INT_EN BIT(12)
#define B_AX_TXDMA_CH10_INT_EN BIT(11)
#define R_AX_PCIE_HISR10 0x13B4
#define B_AX_HC10ISR_IND_INT BIT(28)
#define B_AX_TXDMA_CH11_INT BIT(12)
#define B_AX_TXDMA_CH10_INT BIT(11)
#define R_AX_PCIE_EXP_CTRL 0x13F0
#define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20)
#define B_AX_MAX_TAG_NUM_SH 16
#define B_AX_MAX_TAG_NUM_MSK 0x7
#define B_AX_RET_STICKY_RST_N_KEEP_REG_PERST BIT(14)
#define B_AX_RET_NON_STICKY_RST_N_KEEP_REG_PERST BIT(13)
#define B_AX_RET_NON_STICKY_RST_N_KEEP_REG_LINKRST BIT(12)
#define B_AX_EN_LAT_PHYSTATUS BIT(11)
#define B_AX_EN_OLD_WAKE_MODE BIT(10)
#define B_AX_EN_TIMEOUT_T_PCLKACK BIT(9)
#define B_AX_EN_DIS_IO_MEM_EN BIT(8)
#define B_AX_FORCE_REG_CLK_EN BIT(5)
#define B_AX_SIC_EN_FORCE_CLKREQ BIT(4)
#define B_AX_DIS_L1_2_SUS BIT(3)
#define B_AX_IB_EN_FORCE BIT(2)
#define B_AX_PCIE_ACTIVE_FORCE BIT(1)
#define R_AX_PCIE_RX_PREF_ADV 0x13F4
#define B_AX_RXDMA_PREF_ADV_TH_SH 1
#define B_AX_RXDMA_PREF_ADV_TH_MSK 0x3
#define B_AX_RXDMA_PREF_ADV_EN BIT(0)
#define R_AX_PCIE_IO_RCY_M1 0x3100
#define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
#define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
#define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
#define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
#define R_AX_PCIE_WDT_TIMER_M1 0x3104
#define B_AX_PCIE_WDT_TIMER_M1_SH 0
#define B_AX_PCIE_WDT_TIMER_M1_MSK 0xffffffffL
#define R_AX_PCIE_PADDR_M1 0x3108
#define B_AX_PCIE_PADDR_M1_SH 0
#define B_AX_PCIE_PADDR_M1_MSK 0xffffffffL
#define R_AX_PCIE_IO_RCY_M2 0x310C
#define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
#define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
#define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
#define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
#define R_AX_PCIE_WDT_TIMER_M2 0x3110
#define B_AX_PCIE_WDT_TIMER_M2_SH 0
#define B_AX_PCIE_WDT_TIMER_M2_MSK 0xffffffffL
#define R_AX_PCIE_PADDR_M2 0x3114
#define B_AX_PCIE_PADDR_M2_SH 0
#define B_AX_PCIE_PADDR_M2_MSK 0xffffffffL
#define R_AX_PCIE_IO_RCY_E0 0x3118
#define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
#define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
#define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
#define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
#define R_AX_PCIE_WDT_TIMER_E0 0x311C
#define B_AX_PCIE_WDT_TIMER_E0_SH 0
#define B_AX_PCIE_WDT_TIMER_E0_MSK 0xffffffffL
#define R_AX_PCIE_PADDR_E0 0x3120
#define B_AX_PCIE_PADDR_E0_SH 0
#define B_AX_PCIE_PADDR_E0_MSK 0xffffffffL
#define R_AX_PCIE_IO_RCY_S1 0x3124
#define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
#define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
#define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
#define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
#define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
#define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
#define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
#define R_AX_PCIE_WDT_TIMER_S1 0x3128
#define B_AX_PCIE_WDT_TIMER_S1_SH 0
#define B_AX_PCIE_WDT_TIMER_S1_MSK 0xffffffffL
#define R_AX_PCIE_PADDR_W_S1 0x312C
#define B_AX_PCIE_PADDR_W_S1_SH 0
#define B_AX_PCIE_PADDR_W_S1_MSK 0xffffffffL
#define R_AX_PCIE_PADDR_R_S1 0x3130
#define B_AX_PCIE_PADDR_R_S1_SH 0
#define B_AX_PCIE_PADDR_R_S1_MSK 0xffffffffL
//
// WL_AX_Reg_Page_SDIO.xls
//
//
// SDIO_Local_Reg_Spec
//
#define R_AX_SDIO_TX_CTRL 0x1000
#define B_AX_SDIO_INT_TIMEOUT_SH 16
#define B_AX_SDIO_INT_TIMEOUT_MSK 0xffff
#define B_AX_IO_ERR_STATUS BIT(15)
#define B_AX_CMD53_W_MIX BIT(14)
#define B_AX_CMD53_TX_FORMAT BIT(13)
#define B_AX_CMD53_R_TIMEOUT_MASK BIT(12)
#define B_AX_CMD53_R_TIMEOUT_UNIT_SH 10
#define B_AX_CMD53_R_TIMEOUT_UNIT_MSK 0x3
#define B_AX_REPLY_ERRCRC_IN_DATA BIT(9)
#define B_AX_EN_CMD53_OVERLAP BIT(8)
#define B_AX_REPLY_ERR_IN_R5 BIT(7)
#define B_AX_R18A_EN BIT(6)
#define B_AX_SDIO_CMD_FORCE_VLD BIT(5)
#define B_AX_INIT_CMD_EN BIT(4)
#define B_AX_RXINT_READ_MASK_DIS BIT(3)
#define B_AX_EN_RXDMA_MASK_INT BIT(2)
#define B_AX_EN_MASK_TIMER BIT(1)
#define B_AX_CMD_ERR_STOP_INT_EN BIT(0)
#define R_AX_SDIO_CTRL 0x1004
#define B_AX_SDIO_DRV_TYPE_D_SH 28
#define B_AX_SDIO_DRV_TYPE_D_MSK 0xf
#define B_AX_SDIO_DRV_TYPE_C_SH 24
#define B_AX_SDIO_DRV_TYPE_C_MSK 0xf
#define B_AX_SDIO_DRV_TYPE_B_SH 20
#define B_AX_SDIO_DRV_TYPE_B_MSK 0xf
#define B_AX_SDIO_DRV_TYPE_A_SH 16
#define B_AX_SDIO_DRV_TYPE_A_MSK 0xf
#define B_AX_SIG_OUT_PH BIT(8)
#define B_AX_CMD11_SEQ_END_DELAY_SH 4
#define B_AX_CMD11_SEQ_END_DELAY_MSK 0xf
#define B_AX_CMD11_SEQ_SAMPLE_INTERVAL_SH 1
#define B_AX_CMD11_SEQ_SAMPLE_INTERVAL_MSK 0x7
#define B_AX_CMD11_SEQ_EN BIT(0)
#define R_AX_SDIO_MONITOR 0x1008
#define B_AX_SDIO_INT_START_SH 0
#define B_AX_SDIO_INT_START_MSK 0xffffffffL
#define R_AX_SDIO_MONITOR_2 0x100C
#define B_AX_CMD53_WT_EN BIT(23)
#define B_AX_SDIO_CLK_MONITOR_SH 21
#define B_AX_SDIO_CLK_MONITOR_MSK 0x3
#define B_AX_SDIO_CLK_CNT_SH 0
#define B_AX_SDIO_CLK_CNT_MSK 0x1fffff
#define R_AX_SDIO_CTRL_2 0x1010
#define B_AX_SDIO_CLK_SMT BIT(1)
#define B_AX_SDIO_DATA_SMT BIT(0)
#define R_AX_SDIO_MONITOR_3 0x1014
#define B_AX_SDIO_USER_DEF_SH 0
#define B_AX_SDIO_USER_DEF_MSK 0xffffffffL
#define R_AX_SDIO_HTSFR_INFO 0x1030
#define B_AX_HTSFR0_SH 0
#define B_AX_HTSFR0_MSK 0xffff
#define R_AX_SDIO_INDIRECT_ADDR 0x1040
#define B_AX_INDIRECT_RDY BIT(31)
#define B_AX_INDIRECT_ADDR_SH 0
#define B_AX_INDIRECT_ADDR_MSK 0x7fffffffL
#define R_AX_SDIO_INDIRECT_DATA 0x1044
#define B_AX_INDIRECT_DATA_SH 0
#define B_AX_INDIRECT_DATA_MSK 0xffffffffL
#define R_AX_SDIO_INDIRECT_CTRL 0x1048
#define B_AX_INDIRECT_REG_R BIT(3)
#define B_AX_INDIRECT_REG_W BIT(2)
#define B_AX_INDIRECT_REG_SIZE_SH 0
#define B_AX_INDIRECT_REG_SIZE_MSK 0x3
#define R_AX_SDIO_HRPWM1 0x1080
#define B_AX_HRPWM_SH 16
#define B_AX_HRPWM_MSK 0xffff
#define R_AX_SDIO_BUS_CTRL 0x1084
#define B_AX_SPI_PHASE BIT(21)
#define B_AX_INTR_CTRL BIT(20)
#define B_AX_SDIO_VOLTAGE BIT(19)
#define B_AX_BYPASS_INIT BIT(18)
#define B_AX_HCI_RESUME_RDY BIT(17)
#define B_AX_HCI_SUS_REQ BIT(16)
#define B_AX_CMD53_RDATA_EARLY BIT(14)
#define B_AX_HISR_W_CLR_EN BIT(13)
#define B_AX_INT_MASK_DIS BIT(12)
#define B_AX_PAD_CLK_XHGE_EN BIT(11)
#define B_AX_INTER_CLK_EN BIT(10)
#define B_AX_EN_RPT_TXCRC BIT(9)
#define B_AX_DIS_RXDMA_STS BIT(8)
#define R_AX_SDIO_RESPONSE_TIMER 0x1088
#define B_AX_SDIO_CMD_CRC_SH 16
#define B_AX_SDIO_CMD_CRC_MSK 0xff
#define B_AX_CMDIN_2RESP_TIMER_SH 0
#define B_AX_CMDIN_2RESP_TIMER_MSK 0xffff
#define R_AX_SDIO_HSISR 0x1090
#define B_AX_HISR_MASK BIT(8)
#define B_AX_DRV_WLAN_INT_CLR BIT(1)
#define B_AX_DRV_WLAN_INT BIT(0)
#define R_AX_SDIO_EXTEND_RBLOK_GAP 0x1094
#define B_AX_EXTEND_RBLOCK_GAP_SH 0
#define B_AX_EXTEND_RBLOCK_GAP_MSK 0x3f
#define R_AX_SDIO_DIOERR_RPT 0x10C0
#define B_AX_DATA_CRC_ERR_CNT_SH 24
#define B_AX_DATA_CRC_ERR_CNT_MSK 0xff
#define B_AX_CMD_CRC_ERR_CNT_SH 16
#define B_AX_CMD_CRC_ERR_CNT_MSK 0xff
#define B_AX_SDIO_PAGE_ERR BIT(0)
#define R_AX_SDIO_CMD_ERR_CONTENT_L 0x10C4
#define B_AX_SDIO_CMD_ERR_CONTENT_L_SH 0
#define B_AX_SDIO_CMD_ERR_CONTENT_L_MSK 0xffffffffL
#define R_AX_SDIO_CMD_ERR_CONTENT 0x10C8
#define B_AX_SDIO_DATA_CRC_SH 16
#define B_AX_SDIO_DATA_CRC_MSK 0xffff
#define B_AX_FN1_WDATA_TO_FLG BIT(15)
#define B_AX_FN1_WDATA_LEN_SHORT_FLG BIT(14)
#define B_AX_D3_CRC_ERR BIT(12)
#define B_AX_D2_CRC_ERR BIT(11)
#define B_AX_D1_CRC_ERR BIT(10)
#define B_AX_D0_CRC_ERR BIT(9)
#define B_AX_CMD_CRC_ERR BIT(8)
#define B_AX_SDIO_CMD_ERR_CONTENT_H_SH 0
#define B_AX_SDIO_CMD_ERR_CONTENT_H_MSK 0xff
//#define R_AX_SDIO_TRANS_FIFO_STATUS 0x10CC
//#define B_AX_TRANS_FIFO_UNDERFLOW BIT(1)
//#define B_AX_TRANS_FIFO_OVERFLOW BIT(0)
#define R_AX_SDIO_TXDMA_FIFO_STATUS 0x10CC
#define B_AX_TXDMA_FIFO_UNDERFLOW BIT(4)
#define B_AX_TXDMA_FIFO_OVERFLOW BIT(3)
#define R_AX_SDIO_HIMR 0x1100
#define B_AX_SDIO_BT_INT_EN BIT(24)
#define B_AX_SDIO_HS0ISR_IND_EN BIT(16)
#define B_AX_SDIO_HC10ISR_IND_EN BIT(9)
#define B_AX_SDIO_HC00ISR_IND_EN BIT(8)
#define B_AX_SDIO_HD1ISR_IND_EN BIT(3)
#define B_AX_SDIO_HD0ISR_IND_EN BIT(2)
#define B_AX_SDIO_AVAL_INT_EN BIT(1)
#define B_AX_RX_REQUEST_INT_EN BIT(0)
#define R_AX_SDIO_HISR 0x1104
#define B_AX_SDIO_BT_INT BIT(24)
#define B_AX_SDIO_HS0ISR_IND BIT(16)
#define B_AX_SDIO_HC10ISR_IND BIT(9)
#define B_AX_SDIO_HC00ISR_IND BIT(8)
#define B_AX_SDIO_HD1ISR_IND BIT(3)
#define B_AX_SDIO_HD0ISR_IND BIT(2)
#define B_AX_SDIO_AVAL_INT BIT(1)
#define B_AX_RX_REQUEST_INT BIT(0)
#define R_AX_SDIO_RX_REQ_LEN 0x1108
#define B_AX_RX_REQ_LEN_SH 0
#define B_AX_RX_REQ_LEN_MSK 0x3ffff
#define R_AX_SDIO_AVAL_INTRPT_STAT 0x110C
#define B_AX_SDIO_ACH11_INTRPT_STAT BIT(11)
#define B_AX_SDIO_ACH10_INTRPT_STAT BIT(10)
#define B_AX_SDIO_ACH9_INTRPT_STAT BIT(9)
#define B_AX_SDIO_ACH8_INTRPT_STAT BIT(8)
#define B_AX_SDIO_ACH7_INTRPT_STAT BIT(7)
#define B_AX_SDIO_ACH6_INTRPT_STAT BIT(6)
#define B_AX_SDIO_ACH5_INTRPT_STAT BIT(5)
#define B_AX_SDIO_ACH4_INTRPT_STAT BIT(4)
#define B_AX_SDIO_ACH3_INTRPT_STAT BIT(3)
#define B_AX_SDIO_ACH2_INTRPT_STAT BIT(2)
#define B_AX_SDIO_ACH1_INTRPT_STAT BIT(1)
#define B_AX_SDIO_ACH0_INTRPT_STAT BIT(0)
#define R_AX_SDIO_TXPG_WP 0x1110
#define B_AX_SDIO_ACH12_AVAL_PG_SH 16
#define B_AX_SDIO_ACH12_AVAL_PG_MSK 0x1fff
#define B_AX_SDIO_WP_AVAL_PG_SH 0
#define B_AX_SDIO_WP_AVAL_PG_MSK 0x1fff
#define R_AX_SDIO_TXPG_0 0x1114
#define B_AX_SDIO_ACH1_USE_PG_SH 16
#define B_AX_SDIO_ACH1_USE_PG_MSK 0x1fff
#define B_AX_SDIO_ACH0_USE_PG_SH 0
#define B_AX_SDIO_ACH0_USE_PG_MSK 0x1fff
#define R_AX_SDIO_TXPG_1 0x1118
#define B_AX_SDIO_ACH3_USE_PG_SH 16
#define B_AX_SDIO_ACH3_USE_PG_MSK 0x1fff
#define B_AX_SDIO_ACH2_USE_PG_SH 0
#define B_AX_SDIO_ACH2_USE_PG_MSK 0x1fff
#define R_AX_SDIO_TXPG_2 0x111C
#define B_AX_SDIO_ACH5_USE_PG_SH 16
#define B_AX_SDIO_ACH5_USE_PG_MSK 0x1fff
#define B_AX_SDIO_ACH4_USE_PG_SH 0
#define B_AX_SDIO_ACH4_USE_PG_MSK 0x1fff
#define R_AX_SDIO_TXPG_3 0x1120
#define B_AX_SDIO_ACH7_USE_PG_SH 16
#define B_AX_SDIO_ACH7_USE_PG_MSK 0x1fff
#define B_AX_SDIO_ACH6_USE_PG_SH 0
#define B_AX_SDIO_ACH6_USE_PG_MSK 0x1fff
#define R_AX_SDIO_TXPG_4 0x1124
#define B_AX_SDIO_ACH9_USE_PG_SH 16
#define B_AX_SDIO_ACH9_USE_PG_MSK 0x1fff
#define B_AX_SDIO_ACH8_USE_PG_SH 0
#define B_AX_SDIO_ACH8_USE_PG_MSK 0x1fff
#define R_AX_SDIO_TXPG_5 0x1128
#define B_AX_SDIO_ACH11_USE_PG_SH 16
#define B_AX_SDIO_ACH11_USE_PG_MSK 0x1fff
#define B_AX_SDIO_ACH10_USE_PG_SH 0
#define B_AX_SDIO_ACH10_USE_PG_MSK 0x1fff
//
// WL_AX_Reg_RXI300.xls
//
//
// RXI300
//
#define R_AX_RXI300_NAME 0x0000
#define B_AX_RXI300_NAME_SH 0
#define B_AX_RXI300_NAME_MSK 0xffffffffL
#define R_AX_RXI300_VER 0x0004
#define B_AX_RXI300_VER_SH 0
#define B_AX_RXI300_VER_MSK 0xffffffffL
#define R_AX_RXI300_REV 0x0008
#define B_AX_RXI300_REV_SH 0
#define B_AX_RXI300_REV_MSK 0xffffffffL
#define R_AX_RXI300_INST 0x000C
#define B_AX_RXI300_INST_SH 0
#define B_AX_RXI300_INST_MSK 0xffffffffL
#define R_AX_RXI300_IMPL_Y 0x0010
#define B_AX_RXI300_IMPL_Y_SH 0
#define B_AX_RXI300_IMPL_Y_MSK 0xffffffffL
#define R_AX_RXI300_IMPL_D 0x0014
#define B_AX_RXI300_IMPL_D_SH 0
#define B_AX_RXI300_IMPL_D_MSK 0xffffffffL
#define R_AX_RXI300_DEV 0x0018
#define B_AX_RXI300_DEV_SH 0
#define B_AX_RXI300_DEV_MSK 0xffffffffL
#define R_AX_RXI300_PRO_NUM 0x001C
#define B_AX_RXI300_PRO_NUM_SH 0
#define B_AX_RXI300_PRO_NUM_MSK 0xffffffffL
#define R_AX_RXI300_ELR_0_PLD0 0x0200
#define B_AX_ERR_BSTINDEX_SH 24
#define B_AX_ERR_BSTINDEX_MSK 0xff
#define B_AX_ERR_BSTLEN_SH 16
#define B_AX_ERR_BSTLEN_MSK 0xff
#define B_AX_ERR_BSTTYPE_SH 11
#define B_AX_ERR_BSTTYPE_MSK 0x7
#define B_AX_ERR_CMD_SH 8
#define B_AX_ERR_CMD_MSK 0x7
#define B_AX_ERR_SRC_SH 0
#define B_AX_ERR_SRC_MSK 0xff
#define R_AX_RXI300_ELR_0_PLD1 0x0204
#define B_AX_ERR_MREQINFO_SH 23
#define B_AX_ERR_MREQINFO_MSK 0x1ff
#define B_AX_ERR_SIZE_SH 16
#define B_AX_ERR_SIZE_MSK 0x7
#define B_AX_ERR_BYTEEN_SH 0
#define B_AX_ERR_BYTEEN_MSK 0xffff
#define R_AX_RXI300_ELR_0_ID 0x0208
#define B_AX_ERR_ID_SH 0
#define B_AX_ERR_ID_MSK 0xffffffffL
#define R_AX_RXI300_ELR_0_ADR0 0x020C
#define B_AX_ERR_ADR0_SH 0
#define B_AX_ERR_ADR0_MSK 0xffffffffL
#define R_AX_RXI300_ELR_0_ADR1 0x0210
#define B_AX_ERR_ADR1_SH 0
#define B_AX_ERR_ADR1_MSK 0xffffffffL
#define R_AX_RXI300_ELR_0_CODE 0x0230
#define B_AX_ELR_CODE_SH 0
#define B_AX_ELR_CODE_MSK 0xff
#define R_AX_RXI300_ELR_0_INTR_CLR 0x023C
#define B_AX_ELR_INTR_CLR BIT(0)
#define R_AX_RXI300_ICG_CTRL0 0x0300
#define B_AX_RXI300_ICG_CTRL0_SH 0
#define B_AX_RXI300_ICG_CTRL0_MSK 0xffffffffL
#define R_AX_RXI300_ICG_CTRL1 0x0304
#define B_AX_RXI300_ICG_CTRL1_SH 0
#define B_AX_RXI300_ICG_CTRL1_MSK 0xffffffffL
#define R_AX_RXI300_TIME_MON 0x0308
#define B_AX_RXI300_TM_AXI_APB_BBRF_RST BIT(26)
#define B_AX_RXI300_TM_AXI_APB_SA_RST BIT(25)
#define B_AX_RXI300_TM_AXI2AHB_RST BIT(24)
#define B_AX_RXI300_TM_AXI_APB_BBRF_EN BIT(18)
#define B_AX_RXI300_TM_AXI_APB_SA_EN BIT(17)
#define B_AX_RXI300_TM_AXI2AHB_EN BIT(16)
#define B_AX_RXI300_TM_GRADE_SH 8
#define B_AX_RXI300_TM_GRADE_MSK 0xf
#define B_AX_RXI300_TM_TRSH_SH 0
#define B_AX_RXI300_TM_TRSH_MSK 0xff
#define R_AX_RXI300_ICG_STAT0 0x0320
#define B_AX_RXI300_ICG_STAT0_SH 0
#define B_AX_RXI300_ICG_STAT0_MSK 0xffffffffL
#define R_AX_RXI300_ICG_STAT1 0x0324
#define B_AX_RXI300_ICG_STAT1_SH 0
#define B_AX_RXI300_ICG_STAT1_MSK 0xffffffffL
//
// WL_AX_Reg_SPIC.xls
//
//
// SPIC
//
#define R_AX_SPIC_CTRLR0 0x0000
#define B_AX_PRM_2ND_PHASE BIT(31)
#define B_AX_DDR_EN_SH 28
#define B_AX_DDR_EN_MSK 0x7
#define B_AX_CK_MTIMES_SH 23
#define B_AX_CK_MTIMES_MSK 0x1f
#define B_AX_FAST_RD BIT(22)
#define B_AX_CMD_CH_SH 20
#define B_AX_CMD_CH_MSK 0x3
#define B_AX_DATA_CH_SH 18
#define B_AX_DATA_CH_MSK 0x3
#define B_AX_ADDR_CH_SH 16
#define B_AX_ADDR_CH_MSK 0x3
#define B_AX_TMOD_SH 8
#define B_AX_TMOD_MSK 0x3
#define B_AX_SCPOL BIT(7)
#define B_AX_SCPH BIT(6)
#define R_AX_SPIC_CTRLR1 0x0004
#define B_AX_NDF_SH 0
#define B_AX_NDF_MSK 0xffff
#define R_AX_SPIC_SSIENR 0x0008
#define B_AX_PGM_RST_TEST_EN BIT(4)
#define B_AX_ATCK_CMD BIT(1)
#define B_AX_SPIC_FUNC_EN BIT(0)
#define R_AX_SPIC_SER 0x0010
#define B_AX_SER_SH 0
#define B_AX_SER_MSK 0xffffffffL
#define R_AX_SPIC_BAUDR 0x0014
#define B_AX_SCKDV_SH 0
#define B_AX_SCKDV_MSK 0xfff
#define R_AX_SPIC_TXFTLR 0x0018
#define B_AX_TFT_SH 0
#define B_AX_TFT_MSK 0xffffffffL
#define R_AX_SPIC_RXFTLR 0x001C
#define B_AX_RFT_SH 0
#define B_AX_RFT_MSK 0xffffffffL
#define R_AX_SPIC_TXFLR 0x0020
#define B_AX_TXFLR_SH 0
#define B_AX_TXFLR_MSK 0xffffffffL
#define R_AX_SPIC_RXFLR 0x0024
#define B_AX_RXFLR_SH 0
#define B_AX_RXFLR_MSK 0xffffffffL
#define R_AX_SPIC_SR 0x0028
#define B_AX_BOOT_FIN BIT(7)
#define B_AX_DCOL BIT(6)
#define B_AX_TXE BIT(5)
#define B_AX_RFF BIT(4)
#define B_AX_RFNE BIT(3)
#define B_AX_TFE BIT(2)
#define B_AX_TFNF BIT(1)
#define B_AX_BUSY BIT(0)
#define R_AX_SPIC_IMR 0x002C
#define B_AX_ACSIM BIT(11)
#define B_AX_RXSIM BIT(10)
#define B_AX_TXSIM BIT(9)
#define B_AX_ACEIM BIT(8)
#define B_AX_BYEIM BIT(7)
#define B_AX_WBEIM BIT(6)
#define B_AX_FSEIM BIT(5)
#define B_AX_RXFIM BIT(4)
#define B_AX_RXOIM BIT(3)
#define B_AX_RXUIM BIT(2)
#define B_AX_TXOIM BIT(1)
#define B_AX_TXEIM BIT(0)
#define R_AX_SPIC_ISR 0x0030
#define B_AX_ACSIS BIT(11)
#define B_AX_RXSIS BIT(10)
#define B_AX_TXSIS BIT(9)
#define B_AX_ACEIS BIT(8)
#define B_AX_BYEIS BIT(7)
#define B_AX_WBEIS BIT(6)
#define B_AX_FSEIS BIT(5)
#define B_AX_RXFIS BIT(4)
#define B_AX_RXOIS BIT(3)
#define B_AX_RXUIS BIT(2)
#define B_AX_TXOIS BIT(1)
#define B_AX_TXEIS BIT(0)
#define R_AX_SPIC_RISR 0x0034
#define B_AX_ACSIR BIT(11)
#define B_AX_RXSIR BIT(10)
#define B_AX_TXSIR BIT(9)
#define B_AX_ACEIR BIT(8)
#define B_AX_BYEIR BIT(7)
#define B_AX_WBEIR BIT(6)
#define B_AX_FSEIR BIT(5)
#define B_AX_RXFIR BIT(4)
#define B_AX_RXOIR BIT(3)
#define B_AX_RXUIR BIT(2)
#define B_AX_TXOIR BIT(1)
#define B_AX_TXEIR BIT(0)
#define R_AX_SPIC_TXOICR 0x0038
#define B_AX_TXOICR BIT(0)
#define R_AX_SPIC_RXOICR 0x003C
#define B_AX_RXOICR BIT(0)
#define R_AX_SPIC_RXUICR 0x0040
#define B_AX_RXUICR BIT(0)
#define R_AX_SPIC_MSTICR 0x0044
#define B_AX_MSTICR BIT(0)
#define R_AX_SPIC_ICR 0x0048
#define B_AX_ICR BIT(0)
#define R_AX_SPIC_DMACR 0x004C
#define B_AX_TX_DMAC_EN BIT(1)
#define B_AX_RX_DMAC_EN BIT(0)
#define R_AX_SPIC_DMATDLR 0x0050
#define B_AX_DMATDL_SH 0
#define B_AX_DMATDL_MSK 0xffffffffL
#define R_AX_SPIC_DMARDLR 0x0054
#define B_AX_DMARDL_SH 0
#define B_AX_DMARDL_MSK 0xffffffffL
#define R_AX_SPIC_IDR 0x0058
#define B_AX_IDCODE_SH 0
#define B_AX_IDCODE_MSK 0xffffffffL
#define R_AX_SPIC_VERSION 0x005C
#define B_AX_SPIC_VERSION_SH 0
#define B_AX_SPIC_VERSION_MSK 0xffffffffL
#define R_AX_SPIC_DR_WORD 0x0060
#define B_AX_DR_WORD_SH 0
#define B_AX_DR_WORD_MSK 0xffffffffL
#define R_AX_SPIC_DR_HALF_WORD 0x0060
#define B_AX_DR_HALF_WORD_SH 0
#define B_AX_DR_HALF_WORD_MSK 0xffff
#define R_AX_SPIC_DR_BYTE 0x0060
#define B_AX_DR_BYTE_SH 0
#define B_AX_DR_BYTE_MSK 0xff
#define R_AX_SPIC_READ_FAST_SINGLE 0x00E0
#define B_AX_FRD_CMD_SH 0
#define B_AX_FRD_CMD_MSK 0xffff
#define R_AX_SPIC_READ_DUAL_DATA 0x00E4
#define B_AX_RD_DUAL_O_CMD_SH 0
#define B_AX_RD_DUAL_O_CMD_MSK 0xff
#define R_AX_SPIC_READ_DUAL_ADDR_DATA 0x00E8
#define B_AX_RD_DUAL_IO_CMD_SH 0
#define B_AX_RD_DUAL_IO_CMD_MSK 0xff
#define R_AX_SPIC_READ_QUAD_DATA 0x00EC
#define B_AX_RD_QUAD_O_CMD_SH 0
#define B_AX_RD_QUAD_O_CMD_MSK 0xff
#define R_AX_SPIC_READ_QUAD_ADDR_DATA 0x00F0
#define B_AX_SPIC_PRM_VALUE_SH 16
#define B_AX_SPIC_PRM_VALUE_MSK 0xff
#define B_AX_RD_QUAD_IO_CMD_SH 0
#define B_AX_RD_QUAD_IO_CMD_MSK 0xff
#define R_AX_SPIC_WRITE_SINGLE 0x00F4
#define B_AX_WR_CMD_SH 0
#define B_AX_WR_CMD_MSK 0xffff
#define R_AX_SPIC_WRITE_DUAL_DATA 0x00F8
#define B_AX_WR_DUAL_I_CMD_SH 0
#define B_AX_WR_DUAL_I_CMD_MSK 0xff
#define R_AX_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC
#define B_AX_SPIC_WR_DUAL_II_CMD_SH 0
#define B_AX_SPIC_WR_DUAL_II_CMD_MSK 0xff
#define R_AX_SPIC_WRITE_QUAD_DATA 0x0100
#define B_AX_WR_QUAD_I_CMD_SH 0
#define B_AX_WR_QUAD_I_CMD_MSK 0xff
#define R_AX_SPIC_WRITE_QUAD_ADDR_DATA 0x0104
#define B_AX_WR_QUAD_II_CMD_SH 0
#define B_AX_WR_QUAD_II_CMD_MSK 0xff
#define R_AX_SPIC_WRITE_ENABLE 0x0108
#define B_AX_WR_EN_CMD_SH 0
#define B_AX_WR_EN_CMD_MSK 0xffff
#define R_AX_SPIC_READ_STATUS 0x010C
#define B_AX_ADDR_EN BIT(31)
#define B_AX_ADDR_LEN_SH 29
#define B_AX_ADDR_LEN_MSK 0x3
#define B_AX_ADDR_SEL BIT(28)
#define B_AX_INTERVAL_EN BIT(27)
#define B_AX_RD_ST_CMD_SH 0
#define B_AX_RD_ST_CMD_MSK 0xffff
#define R_AX_SPIC_CTRLR2 0x0110
#define B_AX_CS_ACTIVE_HOLD_SH 12
#define B_AX_CS_ACTIVE_HOLD_MSK 0x3
#define B_AX_RX_FIFO_ENTRY_SH 8
#define B_AX_RX_FIFO_ENTRY_MSK 0xf
#define B_AX_FIFO_ENTRY_SH 4
#define B_AX_FIFO_ENTRY_MSK 0xf
#define B_AX_SEQ_EN BIT(3)
#define B_AX_WPN_DNUM BIT(2)
#define B_AX_WPN_SET BIT(1)
#define B_AX_SO_DNUM BIT(0)
#define R_AX_SPIC_FBAUDR 0x0114
#define B_AX_FSCKDV_SH 0
#define B_AX_FSCKDV_MSK 0xfff
#define R_AX_SPIC_ADDR_LENGTH 0x0118
#define B_AX_ADDR_PHASE_LENGTH_SH 0
#define B_AX_ADDR_PHASE_LENGTH_MSK 0x7
#define R_AX_SPIC_AUTO_LENGTH 0x011C
#define B_AX_ADDR_CS_H_WR_DUM_LEN_SH 28
#define B_AX_ADDR_CS_H_WR_DUM_LEN_MSK 0xf
#define B_AX_ADDR_CS_H_RD_DUM_LEN_SH 26
#define B_AX_ADDR_CS_H_RD_DUM_LEN_MSK 0x3
#define B_AX_ADDR_AUTO_DUM_LEN_SH 18
#define B_AX_ADDR_AUTO_DUM_LEN_MSK 0xff
#define B_AX_ADDR_AUTO_ADDR_LENGTH_SH 16
#define B_AX_ADDR_AUTO_ADDR_LENGTH_MSK 0x3
#define B_AX_ADDR_IN_PHYSICAL_CYC_SH 12
#define B_AX_ADDR_IN_PHYSICAL_CYC_MSK 0xf
#define R_AX_SPIC_VALID_CMD 0x0120
#define B_AX_ADDR_SEQ_TRANS_EN BIT(14)
#define B_AX_ADDR_CTRLR0_CH BIT(12)
#define B_AX_ADDR_PRM_EN BIT(11)
#define B_AX_ADDR_WR_BLOCKING BIT(9)
#define B_AX_ADDR_WR_QUAD_II BIT(8)
#define B_AX_ADDR_WR_QUAD_I BIT(7)
#define B_AX_ADDR_WR_DUAL_II BIT(6)
#define B_AX_ADDR_WR_DUAL_I BIT(5)
#define B_AX_ADDR_RD_QUAD_IO BIT(4)
#define B_AX_ADDR_RD_QUAD_O BIT(3)
#define B_AX_ADDR_RD_DUAL_IO BIT(2)
#define B_AX_ADDR_RD_DUAL_I BIT(1)
#define B_AX_ADDR_FRD_SINGEL BIT(0)
#define R_AX_SPIC_FLASH_SIZE 0x0124
#define B_AX_FLASH_SIZE_SH 0
#define B_AX_FLASH_SIZE_MSK 0xfff
#define R_AX_SPIC_FLUSH_FIFO 0x0128
#define B_AX_FLUSH_PGM_RST_FIFO BIT(1)
#define B_AX_FLUSH_FIFO BIT(0)
#define R_AX_SPIC_PGM_RST_FIFO 0x0140
#define B_AX_PGM_RST_FIFO_SH 0
#define B_AX_PGM_RST_FIFO_MSK 0xffff
//
// WL_AX_Reg_UART.xls
//
//
// UART
//
#define R_AX_UART_RBR 0x0000
#define B_AX_RBR_SH 0
#define B_AX_RBR_MSK 0xff
#define R_AX_UART_THR 0x0000
#define B_AX_THR_SH 0
#define B_AX_THR_MSK 0xff
#define R_AX_UART_DLH 0x0004
#define B_AX_DLH_SH 0
#define B_AX_DLH_MSK 0xff
#define R_AX_UART_DLL 0x0000
#define B_AX_DLL_SH 0
#define B_AX_DLL_MSK 0xff
#define R_AX_UART_IER 0x0004
#define B_AX_IER_PTIME BIT(7)
#define B_AX_IER_EDSSI BIT(3)
#define B_AX_IER_ELSI BIT(2)
#define B_AX_IER_ETBEI BIT(1)
#define B_AX_IER_ERBFI BIT(0)
#define R_AX_UART_IIR 0x0008
#define B_AX_FIFOSE_SH 6
#define B_AX_FIFOSE_MSK 0x3
#define B_AX_IID_SH 0
#define B_AX_IID_MSK 0xf
#define R_AX_UART_FCR 0x0008
#define B_AX_RT_SH 6
#define B_AX_RT_MSK 0x3
#define B_AX_TET_SH 4
#define B_AX_TET_MSK 0x3
#define B_AX_DMAM BIT(3)
#define B_AX_XFIFOR BIT(2)
#define B_AX_RFIFOR BIT(1)
#define B_AX_FIFOE BIT(0)
#define R_AX_UART_LCR 0x000C
#define B_AX_DLAB BIT(7)
#define B_AX_BC BIT(6)
#define B_AX_EPS BIT(4)
#define B_AX_PEN BIT(3)
#define B_AX_STOP BIT(2)
#define B_AX_DLS_SH 0
#define B_AX_DLS_MSK 0x3
#define R_AX_UART_MCR 0x0010
#define B_AX_SIRE BIT(6)
#define B_AX_AFCE BIT(5)
#define B_AX_LB BIT(4)
#define B_AX_OUT2 BIT(3)
#define B_AX_OUT1 BIT(2)
#define B_AX_RTS BIT(1)
#define B_AX_DTR BIT(0)
#define R_AX_UART_LSR 0x0014
#define B_AX_RFE BIT(7)
#define B_AX_TEMT BIT(6)
#define B_AX_THRE BIT(5)
#define B_AX_BI BIT(4)
#define B_AX_FE BIT(3)
#define B_AX_PE BIT(2)
#define B_AX_OE BIT(1)
#define B_AX_DR BIT(0)
#define R_AX_UART_MSR 0x0018
#define B_AX_DCD BIT(7)
#define B_AX_RI BIT(6)
#define B_AX_DSR BIT(5)
#define B_AX_CTS BIT(4)
#define B_AX_DDCD BIT(3)
#define B_AX_TERI BIT(2)
#define B_AX_DDSR BIT(1)
#define B_AX_DCTS BIT(0)
#define R_AX_UART_SCR 0x001C
#define B_AX_SCR_SH 0
#define B_AX_SCR_MSK 0xff
#define R_AX_UART_LPDLL 0x001C
#define B_AX_LPDLL_SH 0
#define B_AX_LPDLL_MSK 0xff
#define R_AX_UART_LPDLH 0x001C
#define B_AX_LPDLH_SH 0
#define B_AX_LPDLH_MSK 0xff
#define R_AX_UART_FAR 0x0070
#define B_AX_FAR BIT(0)
#define R_AX_UART_TFR 0x0074
#define B_AX_TFR_SH 0
#define B_AX_TFR_MSK 0xff
#define R_AX_UART_RFW 0x0078
#define B_AX_RFFE BIT(9)
#define B_AX_RFPE BIT(8)
#define B_AX_RFWD_SH 0
#define B_AX_RFWD_MSK 0xff
#define R_AX_UART_USR 0x007C
#define B_AX_RFF BIT(4)
#define B_AX_RFNE BIT(3)
#define B_AX_TFE BIT(2)
#define B_AX_TFNF BIT(1)
#define B_AX_BUSY BIT(0)
#define R_AX_UART_TFL 0x0080
#define B_AX_TFL_SH 0
#define B_AX_TFL_MSK 0xffffffffL
#define R_AX_UART_RFL 0x0084
#define B_AX_RFL_SH 0
#define B_AX_RFL_MSK 0xffffffffL
#define R_AX_UART_SRR 0x0088
#define B_AX_XFR BIT(2)
#define B_AX_RFR BIT(1)
#define B_AX_UR BIT(0)
#define R_AX_UART_HTX 0x00A4
#define B_AX_HTX BIT(0)
#define R_AX_UART_DMASA 0x00A8
#define B_AX_DMASA BIT(0)
#define R_AX_UART_CPR 0x00F4
#define B_AX_FIFO_MODE_SH 16
#define B_AX_FIFO_MODE_MSK 0xff
#define B_AX_DMA_EXTRA BIT(13)
#define B_AX_UART_ADD_ENCODED_PARAMS BIT(12)
#define B_AX_SHADOW BIT(11)
#define B_AX_FIFO_STAT BIT(10)
#define B_AX_FIFO_ACCESS BIT(9)
#define B_AX_ADDITIONAL_FEAT BIT(8)
#define B_AX_SIR_LP_MODE BIT(7)
#define B_AX_SIR_MODE BIT(6)
#define B_AX_THRE_MODE BIT(5)
#define B_AX_AFCE_MODE BIT(4)
#define B_AX_APB_DATA_WIDTH_SH 0
#define B_AX_APB_DATA_WIDTH_MSK 0x3
#define R_AX_UART_UCV 0x00F8
#define B_AX_UCV_SH 0
#define B_AX_UCV_MSK 0xffffffffL
#define R_AX_UART_CTR 0x00FC
#define B_AX_PID_SH 0
#define B_AX_PID_MSK 0xffffffffL
//
// WL_AX_Reg_USB.xlsx
//
//
// USB_REG
//
#define R_AX_USB2_MAC_0 0x1000
#define B_AX_TOUT_DELAY_FS_SH 24
#define B_AX_TOUT_DELAY_FS_MSK 0xff
#define B_AX_TOUT_DELAY_HS_SH 16
#define B_AX_TOUT_DELAY_HS_MSK 0xff
#define B_AX_TOUT_DIS BIT(15)
#define B_AX_CRC_CHK_OPT BIT(14)
#define B_AX_FORCE_PCERST BIT(13)
#define B_AX_FORCE_TOGL BIT(12)
#define B_AX_FORCE_TOGLSEL BIT(11)
#define B_AX_FORCE_PIDSW BIT(10)
#define B_AX_FORCE_PCE_IN BIT(9)
#define B_AX_FORCE_PCE_OUT BIT(8)
#define B_AX_PID_FORCE_SH 0
#define B_AX_PID_FORCE_MSK 0xff
#define R_AX_USB2_MAC_1 0x1004
#define B_AX_FORCE_PCE_CMD BIT(31)
#define R_AX_USB2_LINK_PORT 0x1008
#define B_AX_R_HOST_PWR_CTRL BIT(23)
#define B_AX_R_USB2_CLR_TXVLD BIT(22)
#define B_AX_R_USB2_SE0 BIT(21)
#define B_AX_HOST_RESUME_EDGE_EN BIT(20)
#define B_AX_RESUME_SEL_SH 16
#define B_AX_RESUME_SEL_MSK 0xf
#define B_AX_DELAY_CHIRP_K_SH 14
#define B_AX_DELAY_CHIRP_K_MSK 0x3
#define B_AX_FORCE_TXVLD1 BIT(13)
#define B_AX_FORCE_TXVLD0 BIT(12)
#define B_AX_DORCE_DAT1 BIT(11)
#define B_AX_FORCE_DAT0 BIT(10)
#define B_AX_LS_TEST BIT(9)
#define B_AX_LS_CHANGE BIT(8)
#define B_AX_FORCE_HS_SW BIT(7)
#define B_AX_FORCE_FS_SW BIT(6)
#define B_AX_FORCE_HSXCVR BIT(5)
#define B_AX_FORCE_FSXCVR BIT(4)
#define B_AX_FORCE_HSTERM BIT(3)
#define B_AX_FORCE_FSTERM BIT(2)
#define B_AX_FORCE_NORM_SW BIT(1)
#define B_AX_FORCE_DBSN BIT(0)
#define R_AX_USB2_LPM_0 0x1010
#define B_AX_USBPHY_PLL_ALIVE BIT(17)
#define B_AX_USB_LPM_MAX_EN BIT(16)
#define B_AX_USB_LPM_MIN_EN BIT(15)
#define B_AX_BESL_EN BIT(14)
#define B_AX_USB_LPM_NYET_EN BIT(13)
#define B_AX_USB_LPM_MAX_ACK BIT(12)
#define B_AX_USB_LPM_EN BIT(11)
#define B_AX_USB2_SUSB BIT(10)
#define B_AX_LPM_PLL_ALIVE BIT(9)
#define B_AX_USB_LPS_OUT BIT(8)
#define B_AX_USB_LPM_WAKEUP_EN BIT(6)
#define B_AX_NEVER_SUSPEND BIT(5)
#define B_AX_SUSPND_EN BIT(4)
#define B_AX_WAKEUP_EN BIT(3)
#define B_AX_USB_SUS_WAKEUP_EN BIT(2)
#define B_AX_RESUME_SND BIT(1)
#define B_AX_CONNECT_EN BIT(0)
#define R_AX_USB2_LPM_1 0x1014
#define B_AX_USB_LPM_MAX_SH 20
#define B_AX_USB_LPM_MAX_MSK 0xf
#define B_AX_USB_LPM_MIN_SH 16
#define B_AX_USB_LPM_MIN_MSK 0xf
#define B_AX_R_WAKE_HOST_WT_H_SH 8
#define B_AX_R_WAKE_HOST_WT_H_MSK 0xff
#define B_AX_R_WAKE_HOST_WT_L_SH 0
#define B_AX_R_WAKE_HOST_WT_L_MSK 0xff
#define R_AX_USB2_MACRO_TEST_MODE 0x1018
#define B_AX_TXRDY_SLB_SEL BIT(14)
#define B_AX_SLB_EN BIT(13)
#define B_AX_SLB_RST BIT(12)
#define B_AX_SLB_FAIL BIT(11)
#define B_AX_SLB_DONE BIT(10)
#define B_AX_SLB_PS1_SW_SH 8
#define B_AX_SLB_PS1_SW_MSK 0x3
#define B_AX_PHY_LOOP_TEST BIT(3)
#define B_AX_USBTMOD_SH 0
#define B_AX_USBTMOD_MSK 0x7
#define R_AX_USB2_PHY_REG_0 0x1020
#define B_AX_USB2PHY_REG_EN BIT(17)
#define B_AX_VLPADM BIT(16)
#define B_AX_VSTATUS_IN_SH 8
#define B_AX_VSTATUS_IN_MSK 0xff
#define B_AX_VCONTROL_SH 0
#define B_AX_VCONTROL_MSK 0xff
#define R_AX_USB2_PHY_REG_1 0x1024
#define B_AX_USB2PHY_DELAY_SH 8
#define B_AX_USB2PHY_DELAY_MSK 0xff
#define B_AX_VSTATUS_OUT_SH 0
#define B_AX_VSTATUS_OUT_MSK 0xff
#define R_AX_USB2_PHY_REG_2 0x1028
#define B_AX_USB2_PHY_P0_E3_SH 24
#define B_AX_USB2_PHY_P0_E3_MSK 0xff
#define B_AX_USB2_PHY_P0_E2_SH 16
#define B_AX_USB2_PHY_P0_E2_MSK 0xff
#define B_AX_USB2_PHY_P0_E1_SH 8
#define B_AX_USB2_PHY_P0_E1_MSK 0xff
#define B_AX_USB2_PHY_P0_E0_SH 0
#define B_AX_USB2_PHY_P0_E0_MSK 0xff
#define R_AX_USB2_PHY_REG_3 0x102C
#define B_AX_USB2_PHY_P0_E7_SH 24
#define B_AX_USB2_PHY_P0_E7_MSK 0xff
#define B_AX_USB2_PHY_P0_E6_SH 16
#define B_AX_USB2_PHY_P0_E6_MSK 0xff
#define B_AX_USB2_PHY_P0_E5_SH 8
#define B_AX_USB2_PHY_P0_E5_MSK 0xff
#define B_AX_USB2_PHY_P0_E4_SH 0
#define B_AX_USB2_PHY_P0_E4_MSK 0xff
#define R_AX_USB2_PHY_REG_4 0x1030
#define B_AX_USB2_PHY_P1_E3_SH 24
#define B_AX_USB2_PHY_P1_E3_MSK 0xff
#define B_AX_USB2_PHY_P1_E2_SH 16
#define B_AX_USB2_PHY_P1_E2_MSK 0xff
#define B_AX_USB2_PHY_P1_E1_SH 8
#define B_AX_USB2_PHY_P1_E1_MSK 0xff
#define B_AX_USB2_PHY_P1_E0_SH 0
#define B_AX_USB2_PHY_P1_E0_MSK 0xff
#define R_AX_USB2_PHY_REG_5 0x1034
#define B_AX_USB2_PHY_P1_E7_SH 24
#define B_AX_USB2_PHY_P1_E7_MSK 0xff
#define B_AX_USB2_PHY_P1_E6_SH 16
#define B_AX_USB2_PHY_P1_E6_MSK 0xff
#define B_AX_USB2_PHY_P1_E5_SH 8
#define B_AX_USB2_PHY_P1_E5_MSK 0xff
#define B_AX_USB2_PHY_P1_E4_SH 0
#define B_AX_USB2_PHY_P1_E4_MSK 0xff
#define R_AX_USB2_PHY_REG_6 0x1038
#define B_AX_USB2_PHY_F3_SH 24
#define B_AX_USB2_PHY_F3_MSK 0xff
#define B_AX_USB2_PHY_F2_SH 16
#define B_AX_USB2_PHY_F2_MSK 0xff
#define B_AX_USB2_PHY_F1_SH 8
#define B_AX_USB2_PHY_F1_MSK 0xff
#define B_AX_USB2_PHY_F0_SH 0
#define B_AX_USB2_PHY_F0_MSK 0xff
#define R_AX_USB2_PHY_REG_7 0x103C
#define B_AX_USB2_PHY_F7_SH 24
#define B_AX_USB2_PHY_F7_MSK 0xff
#define B_AX_USB2_PHY_F6_SH 16
#define B_AX_USB2_PHY_F6_MSK 0xff
#define B_AX_USB2_PHY_F5_SH 8
#define B_AX_USB2_PHY_F5_MSK 0xff
#define B_AX_USB2_PHY_F4_SH 0
#define B_AX_USB2_PHY_F4_MSK 0xff
#define R_AX_USB2_PHY_REG_8 0x1040
#define R_AX_USB2_INTERRUPT_0 0x1050
#define B_AX_IE_ATTACHF BIT(30)
#define B_AX_IE_INITF BIT(29)
#define B_AX_IE_SE0RSTF BIT(28)
#define B_AX_IE_RESUMEF BIT(27)
#define B_AX_IE_SUSPNDF BIT(26)
#define B_AX_IE_EP0CSF BIT(25)
#define B_AX_IE_SOFF BIT(24)
#define B_AX_I_ATTACHF BIT(22)
#define B_AX_I_INITF BIT(21)
#define B_AX_I_SE0RSTF BIT(20)
#define B_AX_I_RESUMEF BIT(19)
#define B_AX_I_SUSPNDF BIT(18)
#define B_AX_I_EP0CSF BIT(17)
#define B_AX_I_SOFF BIT(16)
#define B_AX_IE_SETUP BIT(11)
#define B_AX_IE_EXREG_DMA BIT(10)
#define B_AX_I_SETUPF BIT(9)
#define B_AX_I_EXREG_DMA BIT(8)
#define B_AX_I_STANDARD_REQ BIT(7)
#define B_AX_I_CLASS_REQ BIT(6)
#define B_AX_I_DWEN_REQ BIT(5)
#define B_AX_I_VEND_REQ BIT(4)
#define B_AX_IE_STANDARD_REQ BIT(3)
#define B_AX_IE_CLASS_REQ BIT(2)
#define B_AX_IE_DWEN_REQ BIT(1)
#define B_AX_IE_VEND_REQ BIT(0)
#define R_AX_USB2_INTERRUPT_1 0x1054
#define B_AX_USB2_IB_LDO_DELAY_TIME_SH 8
#define B_AX_USB2_IB_LDO_DELAY_TIME_MSK 0xff
#define B_AX_VENDOR_INDEX_SH 0
#define B_AX_VENDOR_INDEX_MSK 0xff
#define R_AX_USB_ENDPOINT_0 0x1060
#define B_AX_EP_MAXPKT_SH 16
#define B_AX_EP_MAXPKT_MSK 0x3ff
#define B_AX_EP_EN BIT(15)
#define B_AX_EP_TYPE_SH 13
#define B_AX_EP_TYPE_MSK 0x3
#define B_AX_EP_ISTALL BIT(12)
#define B_AX_EP_OSTALL BIT(11)
#define B_AX_EP_STREAMEN BIT(10)
#define B_AX_EP_OUT BIT(9)
#define B_AX_EP_IN BIT(8)
#define B_AX_BT_INTR_SEL BIT(5)
#define B_AX_R_SIE_INIT_DONE BIT(4)
#define B_AX_EP_IDX_SH 0
#define B_AX_EP_IDX_MSK 0xf
#define R_AX_USB_ENDPOINT_1 0x1064
#define B_AX_EP_MAX_STREAM_SH 16
#define B_AX_EP_MAX_STREAM_MSK 0xff
#define B_AX_EP_MAX_BURST_SH 8
#define B_AX_EP_MAX_BURST_MSK 0xff
#define B_AX_EP_INT_INTERVAL_SH 0
#define B_AX_EP_INT_INTERVAL_MSK 0xff
#define R_AX_USB_ENDPOINT_2 0x1068
#define B_AX_EP_BPI_SH 16
#define B_AX_EP_BPI_MSK 0xffff
#define B_AX_USB3_EP_IN_ST_SH 8
#define B_AX_USB3_EP_IN_ST_MSK 0xff
#define B_AX_USB3_EP_OUT_ST_SH 0
#define B_AX_USB3_EP_OUT_ST_MSK 0xff
#define R_AX_USB_ENDPOINT_3 0x106C
#define B_AX_EP12_PAUSE_STATE BIT(31)
#define B_AX_EP11_PAUSE_STATE BIT(30)
#define B_AX_EP10_PAUSE_STATE BIT(29)
#define B_AX_EP9_PAUSE_STATE BIT(28)
#define B_AX_EP8_PAUSE_STATE BIT(27)
#define B_AX_EP7_PAUSE_STATE BIT(26)
#define B_AX_EP6_PAUSE_STATE BIT(25)
#define B_AX_EP5_PAUSE_STATE BIT(24)
#define B_AX_EP4_PAUSE_STATE BIT(23)
#define B_AX_EP12_TX_PAUSE BIT(22)
#define B_AX_EP11_TX_PAUSE BIT(21)
#define B_AX_EP10_TX_PAUSE BIT(20)
#define B_AX_EP9_TX_PAUSE BIT(19)
#define B_AX_EP8_RX_PAUSE BIT(18)
#define B_AX_EP7_TX_PAUSE BIT(17)
#define B_AX_EP6_TX_PAUSE BIT(16)
#define B_AX_EP5_TX_PAUSE BIT(15)
#define B_AX_EP4_RX_PAUSE BIT(14)
#define B_AX_INTERRUPT_BULK_IN BIT(11)
#define B_AX_BULKOUT1 BIT(9)
#define B_AX_BULKOUT0 BIT(8)
#define B_AX_AC_BULKOUT_SH 10
#define B_AX_AC_BULKOUT_MSK 0x3
#define B_AX_INTERRUPT_INTERVAL_SH 0
#define B_AX_INTERRUPT_INTERVAL_MSK 0xf
//
// 8852C ENDPOINT
//
#define R_AX_USB_ENDPOINT_3_V1 0x506C
#define R_AX_USB_HOST_REQUEST_0 0x1070
#define B_AX_ERR_STR2_LEN_SH 24
#define B_AX_ERR_STR2_LEN_MSK 0xff
#define B_AX_ERR_STR1_LEN_SH 8
#define B_AX_ERR_STR1_LEN_MSK 0xffff
#define B_AX_DEVADDR_SH 0
#define B_AX_DEVADDR_MSK 0x7f
#define R_AX_USB_HOST_REQUEST_1 0x1074
#define B_AX_USB_PID_SH 16
#define B_AX_USB_PID_MSK 0xffff
#define B_AX_USB_VID_SH 0
#define B_AX_USB_VID_MSK 0xffff
#define R_AX_USB_HOST_REQUEST_2 0x1078
#define B_AX_MAC_ADDR_1_SH 24
#define B_AX_MAC_ADDR_1_MSK 0xff
#define B_AX_MAC_ADDR_0_SH 16
#define B_AX_MAC_ADDR_0_MSK 0xff
#define B_AX_FORCE_LPM_BCD201 BIT(15)
#define B_AX_SELF_POWER_EN BIT(14)
#define B_AX_R_FORCE_U3MAC_HS_MODE BIT(13)
#define B_AX_LOAD_LTM_CAP BIT(12)
#define B_AX_USB3_DEV_CAP_DESC_EN BIT(11)
#define B_AX_AUTOLOAD_STRING_EN BIT(10)
#define B_AX_REMOTE_WAKEUP BIT(9)
#define B_AX_SQNUM_ROM BIT(8)
#define B_AX_ERR_STR2_LEN_FLAG BIT(7)
#define B_AX_ERR_STR1_LEN_FLAG_1 BIT(6)
#define B_AX_ERR_STR1_LEN_FLAG_0 BIT(5)
#define B_AX_R_USBIO_MODE BIT(4)
#define B_AX_EXREG_TO_EN BIT(3)
#define B_AX_EXREG_TO_SEL_SH 0
#define B_AX_EXREG_TO_SEL_MSK 0x7
#define R_AX_USB_HOST_REQUEST_3 0x107C
#define B_AX_MAC_ADDR_5_SH 24
#define B_AX_MAC_ADDR_5_MSK 0xff
#define B_AX_MAC_ADDR_4_SH 16
#define B_AX_MAC_ADDR_4_MSK 0xff
#define B_AX_MAC_ADDR_3_SH 8
#define B_AX_MAC_ADDR_3_MSK 0xff
#define B_AX_MAC_ADDR_2_SH 0
#define B_AX_MAC_ADDR_2_MSK 0xff
#define R_AX_USB_HOST_REQUEST_4 0x1080
#define B_AX__MANUFACTURE_STRING_3_SH 24
#define B_AX__MANUFACTURE_STRING_3_MSK 0xff
#define B_AX__MANUFACTURE_STRING_2_SH 16
#define B_AX__MANUFACTURE_STRING_2_MSK 0xff
#define B_AX__MANUFACTURE_STRING_1_SH 8
#define B_AX__MANUFACTURE_STRING_1_MSK 0xff
#define B_AX__MANUFACTURE_STRING_0_SH 0
#define B_AX__MANUFACTURE_STRING_0_MSK 0xff
#define R_AX_USB_HOST_REQUEST_5 0x1084
#define B_AX_MANUFACTURE_STRING_7_SH 24
#define B_AX_MANUFACTURE_STRING_7_MSK 0xff
#define B_AX_MANUFACTURE_STRING_6_SH 16
#define B_AX_MANUFACTURE_STRING_6_MSK 0xff
#define B_AX_MANUFACTURE_STRING_5_SH 8
#define B_AX_MANUFACTURE_STRING_5_MSK 0xff
#define B_AX_MANUFACTURE_STRING_4_SH 0
#define B_AX_MANUFACTURE_STRING_4_MSK 0xff
#define R_AX_USB_HOST_REQUEST_6 0x1088
#define B_AX_MANUFACTURE_STRING_B_SH 24
#define B_AX_MANUFACTURE_STRING_B_MSK 0xff
#define B_AX_MANUFACTURE_STRING_A_SH 16
#define B_AX_MANUFACTURE_STRING_A_MSK 0xff
#define B_AX_MANUFACTURE_STRING_9_SH 8
#define B_AX_MANUFACTURE_STRING_9_MSK 0xff
#define B_AX_MANUFACTURE_STRING_8_SH 0
#define B_AX_MANUFACTURE_STRING_8_MSK 0xff
#define R_AX_USB_HOST_REQUEST_7 0x108C
#define B_AX_MANUFACTURE_STRING_F_SH 24
#define B_AX_MANUFACTURE_STRING_F_MSK 0xff
#define B_AX_MANUFACTURE_STRING_E_SH 16
#define B_AX_MANUFACTURE_STRING_E_MSK 0xff
#define B_AX_MANUFACTURE_STRING_D_SH 8
#define B_AX_MANUFACTURE_STRING_D_MSK 0xff
#define B_AX_MANUFACTURE_STRING_C_SH 0
#define B_AX_MANUFACTURE_STRING_C_MSK 0xff
#define R_AX_USB_HOST_REQUEST_8 0x1090
#define B_AX_MANUFACTURE_STRING_13_SH 24
#define B_AX_MANUFACTURE_STRING_13_MSK 0xff
#define B_AX_MANUFACTURE_STRING_12_SH 16
#define B_AX_MANUFACTURE_STRING_12_MSK 0xff
#define B_AX_MANUFACTURE_STRING_11_SH 8
#define B_AX_MANUFACTURE_STRING_11_MSK 0xff
#define B_AX_MANUFACTURE_STRING_10_SH 0
#define B_AX_MANUFACTURE_STRING_10_MSK 0xff
#define R_AX_USB_HOST_REQUEST_9 0x1094
#define B_AX_MANUFACTURE_STRING_17_SH 24
#define B_AX_MANUFACTURE_STRING_17_MSK 0xff
#define B_AX_MANUFACTURE_STRING_16_SH 16
#define B_AX_MANUFACTURE_STRING_16_MSK 0xff
#define B_AX_MANUFACTURE_STRING_15_SH 8
#define B_AX_MANUFACTURE_STRING_15_MSK 0xff
#define B_AX_MANUFACTURE_STRING_14_SH 0
#define B_AX_MANUFACTURE_STRING_14_MSK 0xff
#define R_AX_USB_HOST_REQUEST_A 0x1098
#define B_AX_MANUFACTURE_STRING_1B_SH 24
#define B_AX_MANUFACTURE_STRING_1B_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1A_SH 16
#define B_AX_MANUFACTURE_STRING_1A_MSK 0xff
#define B_AX_MANUFACTURE_STRING_19_SH 8
#define B_AX_MANUFACTURE_STRING_19_MSK 0xff
#define B_AX_MANUFACTURE_STRING_18_SH 0
#define B_AX_MANUFACTURE_STRING_18_MSK 0xff
#define R_AX_USB_HOST_REQUEST_B 0x109C
#define B_AX_MANUFACTURE_STRING_1F_SH 24
#define B_AX_MANUFACTURE_STRING_1F_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1E_SH 16
#define B_AX_MANUFACTURE_STRING_1E_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1D_SH 8
#define B_AX_MANUFACTURE_STRING_1D_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1C_SH 0
#define B_AX_MANUFACTURE_STRING_1C_MSK 0xff
#define R_AX_USB_HOST_REQUEST_C 0x10A0
#define B_AX_PRODUCT_STRING_3_SH 24
#define B_AX_PRODUCT_STRING_3_MSK 0xff
#define B_AX_PRODUCT_STRING_2_SH 16
#define B_AX_PRODUCT_STRING_2_MSK 0xff
#define B_AX_PRODUCT_STRING_1_SH 8
#define B_AX_PRODUCT_STRING_1_MSK 0xff
#define B_AX_PRODUCT_STRING_0_SH 0
#define B_AX_PRODUCT_STRING_0_MSK 0xff
#define R_AX_USB_HOST_REQUEST_D 0x10A4
#define B_AX_PRODUCT_STRING_7_SH 24
#define B_AX_PRODUCT_STRING_7_MSK 0xff
#define B_AX_PRODUCT_STRING_6_SH 16
#define B_AX_PRODUCT_STRING_6_MSK 0xff
#define B_AX_PRODUCT_STRING_5_SH 8
#define B_AX_PRODUCT_STRING_5_MSK 0xff
#define B_AX_PRODUCT_STRING_4_SH 0
#define B_AX_PRODUCT_STRING_4_MSK 0xff
#define R_AX_USB_HOST_REQUEST_E 0x10A8
#define B_AX_PRODUCT_STRING_B_SH 24
#define B_AX_PRODUCT_STRING_B_MSK 0xff
#define B_AX_PRODUCT_STRING_A_SH 16
#define B_AX_PRODUCT_STRING_A_MSK 0xff
#define B_AX_PRODUCT_STRING_9_SH 8
#define B_AX_PRODUCT_STRING_9_MSK 0xff
#define B_AX_PRODUCT_STRING_8_SH 0
#define B_AX_PRODUCT_STRING_8_MSK 0xff
#define R_AX_USB_HOST_REQUEST_F 0x10AC
#define B_AX_PRODUCT_STRING_F_SH 24
#define B_AX_PRODUCT_STRING_F_MSK 0xff
#define B_AX_PRODUCT_STRING_E_SH 16
#define B_AX_PRODUCT_STRING_E_MSK 0xff
#define B_AX_PRODUCT_STRING_D_SH 8
#define B_AX_PRODUCT_STRING_D_MSK 0xff
#define B_AX_PRODUCT_STRING_C_SH 0
#define B_AX_PRODUCT_STRING_C_MSK 0xff
#define R_AX_USB_HOST_REQUEST_10 0x10B0
#define B_AX_PRODUCT_STRING_13_SH 24
#define B_AX_PRODUCT_STRING_13_MSK 0xff
#define B_AX_PRODUCT_STRING_12_SH 16
#define B_AX_PRODUCT_STRING_12_MSK 0xff
#define B_AX_PRODUCT_STRING_11_SH 8
#define B_AX_PRODUCT_STRING_11_MSK 0xff
#define B_AX_PRODUCT_STRING_10_SH 0
#define B_AX_PRODUCT_STRING_10_MSK 0xff
#define R_AX_USB_HOST_REQUEST_11 0x10B4
#define B_AX_PRODUCT_STRING_17_SH 24
#define B_AX_PRODUCT_STRING_17_MSK 0xff
#define B_AX_PRODUCT_STRING_16_SH 16
#define B_AX_PRODUCT_STRING_16_MSK 0xff
#define B_AX_PRODUCT_STRING_15_SH 8
#define B_AX_PRODUCT_STRING_15_MSK 0xff
#define B_AX_PRODUCT_STRING_14_SH 0
#define B_AX_PRODUCT_STRING_14_MSK 0xff
#define R_AX_USB_HOST_REQUEST_12 0x10B8
#define B_AX_PRODUCT_STRING_1B_SH 24
#define B_AX_PRODUCT_STRING_1B_MSK 0xff
#define B_AX_PRODUCT_STRING_1A_SH 16
#define B_AX_PRODUCT_STRING_1A_MSK 0xff
#define B_AX_PRODUCT_STRING_19_SH 8
#define B_AX_PRODUCT_STRING_19_MSK 0xff
#define B_AX_PRODUCT_STRING_18_SH 0
#define B_AX_PRODUCT_STRING_18_MSK 0xff
#define R_AX_USB_HOST_REQUEST_13 0x10BC
#define B_AX_PRODUCT_STRING_1F_SH 24
#define B_AX_PRODUCT_STRING_1F_MSK 0xff
#define B_AX_PRODUCT_STRING_1E_SH 16
#define B_AX_PRODUCT_STRING_1E_MSK 0xff
#define B_AX_PRODUCT_STRING_1D_SH 8
#define B_AX_PRODUCT_STRING_1D_MSK 0xff
#define B_AX_PRODUCT_STRING_1C_SH 0
#define B_AX_PRODUCT_STRING_1C_MSK 0xff
#define R_AX_USB_HOST_REQUEST_14 0x10C0
#define B_AX_PRODUCT_STRING_23_SH 24
#define B_AX_PRODUCT_STRING_23_MSK 0xff
#define B_AX_PRODUCT_STRING_22_SH 16
#define B_AX_PRODUCT_STRING_22_MSK 0xff
#define B_AX_PRODUCT_STRING_21_SH 8
#define B_AX_PRODUCT_STRING_21_MSK 0xff
#define B_AX_PRODUCT_STRING_20_SH 0
#define B_AX_PRODUCT_STRING_20_MSK 0xff
#define R_AX_USB_HOST_REQUEST_15 0x10C4
#define B_AX_PRODUCT_STRING_27_SH 24
#define B_AX_PRODUCT_STRING_27_MSK 0xff
#define B_AX_PRODUCT_STRING_26_SH 16
#define B_AX_PRODUCT_STRING_26_MSK 0xff
#define B_AX_PRODUCT_STRING_25_SH 8
#define B_AX_PRODUCT_STRING_25_MSK 0xff
#define B_AX_PRODUCT_STRING_24_SH 0
#define B_AX_PRODUCT_STRING_24_MSK 0xff
#define R_AX_USB_HOST_REQUEST_16 0x10C8
#define B_AX_PRODUCT_STRING_2B_SH 24
#define B_AX_PRODUCT_STRING_2B_MSK 0xff
#define B_AX_PRODUCT_STRING_2A_SH 16
#define B_AX_PRODUCT_STRING_2A_MSK 0xff
#define B_AX_PRODUCT_STRING_29_SH 8
#define B_AX_PRODUCT_STRING_29_MSK 0xff
#define B_AX_PRODUCT_STRING_28_SH 0
#define B_AX_PRODUCT_STRING_28_MSK 0xff
#define R_AX_USB_HOST_REQUEST_17 0x10CC
#define B_AX_PRODUCT_STRING_2F_SH 24
#define B_AX_PRODUCT_STRING_2F_MSK 0xff
#define B_AX_PRODUCT_STRING_2E_SH 16
#define B_AX_PRODUCT_STRING_2E_MSK 0xff
#define B_AX_PRODUCT_STRING_2D_SH 8
#define B_AX_PRODUCT_STRING_2D_MSK 0xff
#define B_AX_PRODUCT_STRING_2C_SH 0
#define B_AX_PRODUCT_STRING_2C_MSK 0xff
#define R_AX_USB_HOST_REQUEST_18 0x10D0
#define B_AX_SERIAL_NUMBER_STRING_3_SH 24
#define B_AX_SERIAL_NUMBER_STRING_3_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_2_SH 16
#define B_AX_SERIAL_NUMBER_STRING_2_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_1_SH 8
#define B_AX_SERIAL_NUMBER_STRING_1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_0_SH 0
#define B_AX_SERIAL_NUMBER_STRING_0_MSK 0xff
#define R_AX_USB_HOST_REQUEST_19 0x10D4
#define B_AX_SERIAL_NUMBER_STRING_7_SH 24
#define B_AX_SERIAL_NUMBER_STRING_7_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_6_SH 16
#define B_AX_SERIAL_NUMBER_STRING_6_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_5_SH 8
#define B_AX_SERIAL_NUMBER_STRING_5_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_4_SH 0
#define B_AX_SERIAL_NUMBER_STRING_4_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1A 0x10D8
#define B_AX_SERIAL_NUMBER_STRING_B_SH 24
#define B_AX_SERIAL_NUMBER_STRING_B_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_A_SH 16
#define B_AX_SERIAL_NUMBER_STRING_A_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_9_SH 8
#define B_AX_SERIAL_NUMBER_STRING_9_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_8_SH 0
#define B_AX_SERIAL_NUMBER_STRING_8_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1B 0x10DC
#define B_AX_SERIAL_NUMBER_STRING_F_SH 24
#define B_AX_SERIAL_NUMBER_STRING_F_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_E_SH 16
#define B_AX_SERIAL_NUMBER_STRING_E_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_D_SH 8
#define B_AX_SERIAL_NUMBER_STRING_D_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_C_SH 0
#define B_AX_SERIAL_NUMBER_STRING_C_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1C 0x10E0
#define B_AX_USB3_U2SEL_SH 16
#define B_AX_USB3_U2SEL_MSK 0xffff
#define B_AX_USB3_U1PEL_SH 0
#define B_AX_USB3_U1PEL_MSK 0xffff
#define R_AX_USB_HOST_REQUEST_1D 0x10E4
#define B_AX_HW_VENDOR_INDEX_SH 16
#define B_AX_HW_VENDOR_INDEX_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1E 0x10E8
#define B_AX_DIS_STALL_FUNC_WAKE BIT(24)
#define B_AX_USB3_U2_DEV_EXIT_LAT_SH 8
#define B_AX_USB3_U2_DEV_EXIT_LAT_MSK 0xffff
#define B_AX_USB3_U1_DEV_EXIT_LAT_SH 0
#define B_AX_USB3_U1_DEV_EXIT_LAT_MSK 0xff
#define R_AX_USB3_MAC_LINK_0 0x1100
#define B_AX_INTS_USB3_HRESET_EN BIT(31)
#define B_AX_INTS_USB3_RECOV_EN BIT(30)
#define B_AX_INTS_USB3_LPBK_EN BIT(29)
#define B_AX_INTS_USB3_RXDET_EN BIT(28)
#define B_AX_INTS_USB3_POLL_EN BIT(27)
#define B_AX_INTS_USB3_U3_EN BIT(26)
#define B_AX_INTS_USB3_U1U2_EN BIT(25)
#define B_AX_INTS_USB3_U0_EN BIT(24)
#define B_AX_INTS_USB3_RECOV2U0_EN BIT(23)
#define B_AX_INTS_USB3_SSINACT_EN BIT(22)
#define B_AX_INTS_USB3_SSDIS_EN BIT(21)
#define B_AX_INTS_USB3_CMPLY_EN BIT(20)
#define B_AX_INTS_USB3_RECOV2U0 BIT(19)
#define B_AX_INTS_USB3_SSINACT BIT(18)
#define B_AX_INTS_USB3_SSDIS BIT(17)
#define B_AX_INTS_USB3_CMPLY BIT(16)
#define B_AX_INTS_USB3_HRESET BIT(15)
#define B_AX_INTS_USB3_RECOV BIT(14)
#define B_AX_INTS_USB3_LPBK BIT(13)
#define B_AX_INTS_USB3_RXDET BIT(12)
#define B_AX_INTS_USB3_POLL BIT(11)
#define B_AX_INTS_USB3_U3 BIT(10)
#define B_AX_INTS_USB3_U1U2 BIT(9)
#define B_AX_INTS_USB3_U0 BIT(8)
#define B_AX_EN_ROVIDLE_TIMEOUT BIT(6)
#define B_AX_EN_UNFIN_RTY BIT(5)
#define B_AX_SSPHY_U1_QUICK_LFPS BIT(4)
#define B_AX_USB3_DIS_ISOC_TIME_GT BIT(3)
#define B_AX_R_DIS_USB3_U2_EN BIT(2)
#define B_AX_R_DIS_USB3_U1_EN BIT(1)
#define B_AX_LINK_ST_DETECT_TERM BIT(0)
#define R_AX_USB3_MAC_LINK_1 0x1104
#define B_AX_WARM_RESET_TIME_SH 0
#define B_AX_WARM_RESET_TIME_MSK 0x3
#define R_AX_USB3_MAC_PIU 0x1108
#define B_AX_SSPHY_CLR_TERM BIT(1)
#define B_AX_SSPHY_SET_TERM BIT(0)
#define R_AX_USB3_MAC_PTL 0x110C
#define B_AX_WLAN0_BUF_NUMP_EN BIT(1)
#define B_AX_IGNORE_RETRY_BIT BIT(0)
#define R_AX_USB3_MAC_PRTSM 0x1110
#define B_AX_EN_IMMED_POP_CREDIT BIT(0)
#define R_AX_USB3_MAC_NPI_CONFIG_INTF_0 0x1114
#define B_AX_SSPHY_LFPS_FILTER BIT(31)
#define B_AX_SSPHY_TX_SWING BIT(30)
#define B_AX_SSPHY_TXMARGIN_SH 27
#define B_AX_SSPHY_TXMARGIN_MSK 0x7
#define B_AX_SSPHY_TXDEEMPHASIS_SH 25
#define B_AX_SSPHY_TXDEEMPHASIS_MSK 0x3
#define B_AX_SSPHY_ELASTIC_BUF BIT(24)
#define B_AX_HIRD_THR_SH 19
#define B_AX_HIRD_THR_MSK 0x1f
#define B_AX_DEV_SPEED_SH 16
#define B_AX_DEV_SPEED_MSK 0x7
#define B_AX_U1_ACTIVE_TIMEOUT_SH 8
#define B_AX_U1_ACTIVE_TIMEOUT_MSK 0xff
#define B_AX_USB3_TARGET_LINK_STATE_SH 4
#define B_AX_USB3_TARGET_LINK_STATE_MSK 0xf
#define B_AX_APPL1RSP BIT(3)
#define B_AX_LPM_CAPABLE BIT(2)
#define B_AX_USB3_EOF_SH 0
#define B_AX_USB3_EOF_MSK 0x3
#define R_AX_USB3_MAC_NPI_CONFIG_INTF_1 0x1118
#define B_AX_NPI_SCALEDOWN_MODE_SH 24
#define B_AX_NPI_SCALEDOWN_MODE_MSK 0x3
#define B_AX_SSPHY_POWERDOWN_SCALE_SH 8
#define B_AX_SSPHY_POWERDOWN_SCALE_MSK 0x1fff
#define B_AX_SSPHY_U1_FAST_OUT BIT(7)
#define B_AX_SSPHY_P3_FOR_P2 BIT(6)
#define B_AX_SSPHY_U1_RXVALID BIT(5)
#define B_AX_SSPHY_DIS_SCAMBLE BIT(4)
#define B_AX_SSPHY_SKIP_RXDETECT BIT(3)
#define B_AX_SSPHY_LFPS_P0_ALIGN BIT(2)
#define B_AX_SSPHY_P3P2_TRANS BIT(1)
#define B_AX_SSPHY_P3_EXITIN_P2 BIT(0)
#define R_AX_USB3_MAC_NPI_CONFIG_INTF_2 0x111C
#define B_AX_SSPHY_U2EXIT_LPFS BIT(18)
#define B_AX_SSPHY_PHYSOFTRST BIT(17)
#define B_AX_SSPHY_HSTPRTCMPL BIT(16)
#define B_AX_SSPHY_U2SSINACTP3OK BIT(15)
#define B_AX_SSPHY_DISRXDETP3 BIT(14)
#define B_AX_SSPHY_UX_EXIT_IN_PX BIT(13)
#define B_AX_SSPHY_PING_ENH_EN BIT(12)
#define B_AX_SSPHY_U1U2EXITFAIL_TO_RECOV BIT(11)
#define B_AX_SSPHY_ALWAYS_REQ BIT(10)
#define B_AX_SSPHY_START_RX_DET BIT(9)
#define B_AX_SSPHY_DIS_RX_DET BIT(8)
#define B_AX_SSPHY_DELAY_P1P2P3_SH 5
#define B_AX_SSPHY_DELAY_P1P2P3_MSK 0x7
#define B_AX_SSPHY_SUSPEND_EN BIT(4)
#define B_AX_SSPHY_DATWIDTH_SH 2
#define B_AX_SSPHY_DATWIDTH_MSK 0x3
#define B_AX_SSPHY_ABORTRXDETLNU2 BIT(1)
#define B_AX_SSPHY_RX_DETECT_LPFS BIT(0)
#define R_AX_USB3_MAC_NPI_POWER_0 0x1120
#define B_AX_U3_LTM_EN BIT(28)
#define B_AX_LINK_STATE_REQ_SH 24
#define B_AX_LINK_STATE_REQ_MSK 0xf
#define B_AX_SUSCLK_RATIO_SH 8
#define B_AX_SUSCLK_RATIO_MSK 0x1fff
#define B_AX_TEST_CTRL_SH 4
#define B_AX_TEST_CTRL_MSK 0xf
#define B_AX_UFRAME_SCALE_SH 2
#define B_AX_UFRAME_SCALE_MSK 0x3
#define B_AX_LOCAL_LBK BIT(1)
#define B_AX_USB_EN_SLEEP BIT(0)
#define R_AX_USB3_MAC_NPI_POWER_1 0x1124
#define B_AX_WAKE_WAIT_XTAL BIT(27)
#define B_AX_WAKE_WAIT_CURRENT BIT(26)
#define B_AX_WAKEUP_NEG_SEL BIT(25)
#define B_AX_SSPHY_USB3_ATTEMPT BIT(24)
#define B_AX_WAIT_IDLE_TIME_SH 20
#define B_AX_WAIT_IDLE_TIME_MSK 0xf
#define B_AX_U2_EN_MAC_IDLE BIT(18)
#define B_AX_U1_EN_MAC_IDLE BIT(17)
#define B_AX_SWITCH_CLK_EN BIT(16)
#define B_AX_USB3_SAMPLE_RXELECIDLE_SH 8
#define B_AX_USB3_SAMPLE_RXELECIDLE_MSK 0xff
#define B_AX_U3_INIT_U2 BIT(7)
#define B_AX_U3_INIT_U1 BIT(6)
#define B_AX_SET_U3_WAKE BIT(5)
#define B_AX_U3_U2_EN BIT(4)
#define B_AX_U3_U1_EN BIT(3)
#define B_AX_U3_INIT_U2_EN BIT(2)
#define B_AX_U3_INIT_U1_EN BIT(1)
#define B_AX_USB3_RUN BIT(0)
#define R_AX_USB3_MAC_NPI_POWER_2 0x1128
#define B_AX_NPI_LINK_STATE_LATCH_SH 16
#define B_AX_NPI_LINK_STATE_LATCH_MSK 0xff
#define B_AX_NPI_HOST_RESUME_DETECTED BIT(15)
#define B_AX_NPI_DEV_CONNECT_SPEED_SH 12
#define B_AX_NPI_DEV_CONNECT_SPEED_MSK 0x7
#define B_AX_NPI_LINK_STATE_SH 8
#define B_AX_NPI_LINK_STATE_MSK 0xf
#define B_AX_POLL_EN BIT(7)
#define B_AX_POLL_SAMPLE_ON BIT(6)
#define B_AX_POLL_ACT_SH 4
#define B_AX_POLL_ACT_MSK 0x3
#define B_AX_POLL_NOACT_SH 0
#define B_AX_POLL_NOACT_MSK 0xf
#define R_AX_USB3_MAC_NPI_POWER_3 0x112C
#define B_AX_R_CNT_SWITCH_USB32_PARA_SH 0
#define B_AX_R_CNT_SWITCH_USB32_PARA_MSK 0xffff
#define R_AX_USB3_MAC_NPI_STATUS 0x1130
#define B_AX_NPI_DEV_CONNECTED BIT(0)
#define R_AX_USB3_MAC_NPI_DEVICE_NOTIFICATION 0x1134
#define B_AX_DEVNOTE_BIA_SH 16
#define B_AX_DEVNOTE_BIA_MSK 0xffff
#define B_AX_DEVNOTE_BELT_SH 0
#define B_AX_DEVNOTE_BELT_MSK 0xfff
#define R_AX_USB3_MAC_NPI_TRANSMIT 0x1138
#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_SH 0
#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_MSK 0xf
#define R_AX_USB3_MAC_NPI_OTHERS 0x113C
#define B_AX_EN_FIX_RX_ABORT BIT(8)
#define B_AX_FLADJ_30MHZ_REG_SH 0
#define B_AX_FLADJ_30MHZ_REG_MSK 0x3f
#define R_AX_USB3_WRAP_0 0x1140
#define B_AX_U1TOU2_TIMER_SH 24
#define B_AX_U1TOU2_TIMER_MSK 0xff
#define B_AX_WAKE_ST_DBG_SH 20
#define B_AX_WAKE_ST_DBG_MSK 0xf
#define B_AX_ARB_ST_DBG_SH 18
#define B_AX_ARB_ST_DBG_MSK 0x3
#define B_AX_BIA_REQ BIT(17)
#define B_AX_BELT_REQ BIT(16)
#define B_AX_USB3_VENDOR_LEN_TH_SH 0
#define B_AX_USB3_VENDOR_LEN_TH_MSK 0xffff
#define R_AX_USB3_WRAP_1 0x1144
#define B_AX_DIS_PKT_FUNC_WAKE BIT(0)
#define R_AX_USB3_PHY 0x1148
#define B_AX_USB3_PHY_RWDATA_SH 16
#define B_AX_USB3_PHY_RWDATA_MSK 0xffff
#define B_AX_USB3_PHY_ADR_SH 8
#define B_AX_USB3_PHY_ADR_MSK 0x1f
#define B_AX_USB3_PHY_REG_WRFLAG BIT(7)
#define B_AX_USB3_PHY_REG_RDFLAG BIT(6)
#define B_AX_USB3_PHY_REG_ADR_SH 0
#define B_AX_USB3_PHY_REG_ADR_MSK 0x1f
#define R_AX_USB3_OTHERS 0x1150
#define B_AX_R_REATTACH_TIMER_SH 28
#define B_AX_R_REATTACH_TIMER_MSK 0xf
#define B_AX_R_CNT_MS_SEL_SH 24
#define B_AX_R_CNT_MS_SEL_MSK 0x7
#define B_AX_VENDOR_LPM_TEST_SH 16
#define B_AX_VENDOR_LPM_TEST_MSK 0xff
#define B_AX_ISOC_DELAY_VALUE_SH 0
#define B_AX_ISOC_DELAY_VALUE_MSK 0xffff
#define R_AX_USB_APPLICATION_BT_0 0x1160
#define B_AX_BTRX0_BUFFER_WADDR_SH 24
#define B_AX_BTRX0_BUFFER_WADDR_MSK 0xff
#define B_AX_USB_INTOKEN_TIMEOUT_SH 20
#define B_AX_USB_INTOKEN_TIMEOUT_MSK 0x7
#define B_AX_BRX_BUF_CHK_SH 16
#define B_AX_BRX_BUF_CHK_MSK 0x7
#define B_AX_BTRX0_RPKT_SIZE_SH 0
#define B_AX_BTRX0_RPKT_SIZE_MSK 0xffff
#define R_AX_USB_APPLICATION_BT_1 0x1164
#define B_AX_USB2BT_PWR_INFO_REG_MASK_SH 20
#define B_AX_USB2BT_PWR_INFO_REG_MASK_MSK 0xf
#define B_AX_FUNCTION_SUSB_EN_BT BIT(19)
#define B_AX_LOWPOWER_BT BIT(18)
#define B_AX_FUNCTION_WAKE_EN_BT BIT(17)
#define B_AX_FUNCTION_WAKE_CAPABLE_BT BIT(16)
#define B_AX_BT_ISO_ZERO_EN BIT(14)
#define B_AX_R_RXDMA_MODE_SH 12
#define B_AX_R_RXDMA_MODE_MSK 0x3
#define B_AX_GPS_USB_ACTIVE BIT(11)
#define B_AX_BT_TXQ_STOP_SH 8
#define B_AX_BT_TXQ_STOP_MSK 0x7
#define R_AX_USB_APPLICATION_BT_2 0x1168
#define B_AX_BT_TX BIT(17)
#define B_AX_BT_RX BIT(16)
#define B_AX_BTTX_FIFO_OVER_EP3 BIT(13)
#define B_AX_BTTX_FIFO_OVER_EP2 BIT(12)
#define B_AX_BTTX_FIFO_OVER_EP0 BIT(11)
#define B_AX_BTRX_FIFO_OVER_EP3 BIT(10)
#define B_AX_BTRX_FIFO_OVER_EP2 BIT(9)
#define B_AX_BTRX_FIFO_OVER_EP1 BIT(8)
#define B_AX_BTTX_FIFO_UNDR_EP3 BIT(5)
#define B_AX_BTTX_FIFO_UNDR_EP2 BIT(4)
#define B_AX_BTTX_FIFO_UNDR_EP0 BIT(3)
#define B_AX_BTRX_FIFO_UNDR_EP3 BIT(2)
#define B_AX_BTRX_FIFO_UNDR_EP2 BIT(1)
#define B_AX_BTRX_FIFO_UNDR_EP1 BIT(0)
#define R_AX_USB_APPLICATION_BT_3 0x116C
#define B_AX_DBG_BTRX_WADDR_SH 16
#define B_AX_DBG_BTRX_WADDR_MSK 0xfff
#define B_AX_DBG_BTRX_RPKT_SIZE_SH 0
#define B_AX_DBG_BTRX_RPKT_SIZE_MSK 0xffff
#define R_AX_USB_WLAN0_0 0x1170
#define B_AX_WLAN_INT_LEN_SH 16
#define B_AX_WLAN_INT_LEN_MSK 0xffff
#define B_AX_WLAN0_TXQ_STALL_DIS BIT(4)
#define B_AX_FUNCTION_SUSB_EN_WLAN0 BIT(3)
#define B_AX_LOWPOWER_WLAN0 BIT(2)
#define B_AX_FUNCTION_WAKE_EN_WLAN0 BIT(1)
#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN0 BIT(0)
#define R_AX_USB_WLAN0_1 0x1174
#define B_AX_USBRX_RST BIT(9)
#define B_AX_USBTX_RST BIT(8)
#define B_AX_R_USBRX_SRAM_LS BIT(7)
#define B_AX_R_USBRX_SRAM_DS BIT(6)
#define B_AX_R_USBTX_SRAM_LS BIT(5)
#define B_AX_R_USBTX_SRAM_DS BIT(4)
#define B_AX_WLRX_FIFO_OVER_SH 2
#define B_AX_WLRX_FIFO_OVER_MSK 0x3
#define B_AX_WLRX_FIFO_UNDR_SH 0
#define B_AX_WLRX_FIFO_UNDR_MSK 0x3
#define R_AX_USB_AUTO_INSTALL_0 0x1180
#define B_AX_AINST_POLL_1 BIT(28)
#define B_AX_AINST_POLL_0 BIT(27)
#define B_AX_AINST_TX1_CLR_BUF BIT(26)
#define B_AX_AINST_TX0_CLR_BUF BIT(25)
#define B_AX_WLAN_FW_RDY BIT(24)
#define B_AX_RECONF_USBEP BIT(23)
#define B_AX_RECONF_USBEP_EN BIT(22)
#define B_AX_BULK_ONLY_MASS_STORAGE_RESET BIT(21)
#define B_AX_BULK_ONLY_MASS_STORAGE_RESET_EN BIT(20)
#define B_AX_AINST_RXLEN_SH 8
#define B_AX_AINST_RXLEN_MSK 0xfff
#define B_AX_AINST_RX1_INTR BIT(7)
#define B_AX_AINST_RX0_INTR BIT(6)
#define B_AX_AINXT_TX1_INTR BIT(5)
#define B_AX_AINST_TX0_INTR BIT(4)
#define B_AX_AUTO_INST_TXQ_STALL_DIS BIT(3)
#define B_AX_LOWPOWER_AINST BIT(2)
#define B_AX_FUNCTION_WANE_EN_AINST BIT(1)
#define R_AX_USB_AUTO_INSTALL_1 0x1184
#define B_AX_AINST_TX1LEN_SH 16
#define B_AX_AINST_TX1LEN_MSK 0xfff
#define B_AX_AINST_TX0LEN_SH 0
#define B_AX_AINST_TX0LEN_MSK 0xfff
#define R_AX_USB_AUTO_INSTALL_2 0x1188
#define B_AX_AINST_PID_SH 16
#define B_AX_AINST_PID_MSK 0xffff
#define B_AX_AINST_VID_SH 0
#define B_AX_AINST_VID_MSK 0xffff
#define R_AX_USB_AUTO_INSTALL_3 0x118C
#define B_AX_AINST_TXSTATUS_SH 8
#define B_AX_AINST_TXSTATUS_MSK 0xff
#define B_AX_AINST_RXSTATUS_SH 0
#define B_AX_AINST_RXSTATUS_MSK 0xff
#define R_AX_USB_BRIDGE_UART_0 0x1190
#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_SH 20
#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_MSK 0xfff
#define B_AX_BRIDGE_XFACTOR_SH 16
#define B_AX_BRIDGE_XFACTOR_MSK 0xf
#define B_AX_BRIDGE_BAUD_USB2_SH 0
#define B_AX_BRIDGE_BAUD_USB2_MSK 0xfff
#define R_AX_USB_BRIDGE_UART_1 0x1194
#define B_AX_BRIDGE_WAKEUP_EN_SH 30
#define B_AX_BRIDGE_WAKEUP_EN_MSK 0x3
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_SH 16
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_MSK 0xfff
#define B_AX_BRIDGE_LE_CON_HAN_VLD BIT(9)
#define B_AX_BRIDGE_LE_ON BIT(8)
#define B_AX_BRIDGE_DEBUG_PKTCNT_EN BIT(6)
#define B_AX_BRIDGE_RESET_RCV_SEL BIT(5)
#define B_AX_BRIDGE_WLS0 BIT(4)
#define B_AX_BRIDGE_STB BIT(3)
#define B_AX_BRIDGE_PEN BIT(2)
#define B_AX_BRIDGE_EPS BIT(1)
#define B_AX_BRIDGE_STKP BIT(0)
#define R_AX_USB_BRIDGE_UART_2 0x1198
#define B_AX_BRIDGE_DEBUG_SEL_SH 24
#define B_AX_BRIDGE_DEBUG_SEL_MSK 0xff
#define B_AX_R_BRIDGE_UARTEN BIT(23)
#define B_AX_BRIDGE_LPM_EN BIT(22)
#define B_AX_BRIDGE_TXSCO_TIME_INTERVAL_EN BIT(21)
#define B_AX_BRIDGE_TXSCO_PKT_LEN_MAT_EN BIT(20)
#define B_AX_BRIDGE_TXSCO_CON_HAN_MAT_EN BIT(19)
#define B_AX_BRIDGE_USB_TX_HCICMDLEN_SEL BIT(18)
#define B_AX_R_BRIDGE_JCIRXEN BIT(17)
#define B_AX_R_BRIDGE_HCITXEN BIT(16)
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_SH 0
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_MSK 0xfff
#define R_AX_USB_BRIDGE_UART_3 0x119C
#define B_AX_BRIDGE_URT_RXINDIC_ERR BIT(31)
#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_SH 24
#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_MSK 0x7f
#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_SH 16
#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_MSK 0xff
#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_SH 8
#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_MSK 0xff
#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_SH 0
#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_MSK 0xff
#define R_AX_USB_BRIDGE_UART_4 0x11A0
#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_SH 20
#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_MSK 0xfff
#define B_AX_BRIDGE_XFACTOR_USB3_SH 16
#define B_AX_BRIDGE_XFACTOR_USB3_MSK 0xf
#define B_AX_BRIDGE_BAUD_USB3_SH 0
#define B_AX_BRIDGE_BAUD_USB3_MSK 0xfff
#define R_AX_USB_BT_BRIDGE 0x11A8
#define B_AX_R_DIS_BTBRI_SS_SYSON BIT(2)
#define B_AX_R_DIS_BTBRI_SS_STS BIT(1)
#define B_AX_R_DIS_BTBRI_L1U2_STS BIT(0)
#define R_AX_USB_DMA_WRAPPER 0x11B0
#define B_AX_PKT_BASE_EN BIT(11)
#define B_AX_FUNCTION_SUSB_OPT BIT(8)
#define B_AX_TX7LEN_MISMATCH BIT(7)
#define B_AX_TX6LEN_MISMATCH BIT(6)
#define B_AX_TX5LEN_MISMATCH BIT(5)
#define B_AX_TX4LEN_MISMATCH BIT(4)
#define B_AX_TX3LEN_MISMATCH BIT(3)
#define B_AX_TX2LEN_MISMATCH BIT(2)
#define B_AX_TX1LEN_MISMATCH BIT(1)
#define B_AX_TX0LEN_MISMATCH BIT(0)
#define R_AX_USB_WLAN1 0x11B8
#define B_AX_WLAN_TX BIT(12)
#define B_AX_WLAN_RX BIT(11)
#define B_AX_WLAN1_TXQ_STALL_DIS BIT(10)
#define B_AX_WLAN1_RXQ_STOP_SH 8
#define B_AX_WLAN1_RXQ_STOP_MSK 0x3
#define B_AX_WLAN1_TXQ_STOP_SH 4
#define B_AX_WLAN1_TXQ_STOP_MSK 0xf
#define B_AX_FUNCTION_SUSB_EN_WLAN1 BIT(3)
#define B_AX_LOWPOWER_WLAN1 BIT(2)
#define B_AX_FUNCTION_WAKE_EN_WLAN1 BIT(1)
#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN1 BIT(0)
#define R_AX_USB_GPS 0x11C0
#define B_AX_FUNCTION_SUSB_EN_GPS BIT(3)
#define B_AX_LOWPOWER_GPS BIT(2)
#define B_AX_FUNCTION_WAKE_EN_GPS BIT(1)
#define B_AX_FUNCTION_WAKE_CAPABLE_GPS BIT(0)
#define R_AX_USB_DEBUG_0 0x11D0
#define B_AX_SLEEP_GNT_BT BIT(17)
#define B_AX_SLEEP_REQ_BT BIT(16)
#define B_AX_DEBUG_SIGNAL_001_SH 8
#define B_AX_DEBUG_SIGNAL_001_MSK 0xff
#define B_AX_USB_DBGO_SEL_SH 0
#define B_AX_USB_DBGO_SEL_MSK 0xff
#define R_AX_USB_DEBUG_1 0x11D4
#define B_AX_RXDMA_ENDPOINT_COUNTER_SH 24
#define B_AX_RXDMA_ENDPOINT_COUNTER_MSK 0xff
#define B_AX_RXDMA_DMA_COUNTER_SH 16
#define B_AX_RXDMA_DMA_COUNTER_MSK 0xff
#define B_AX_TXDMA_ENDPOINT_COUNTER_SH 8
#define B_AX_TXDMA_ENDPOINT_COUNTER_MSK 0xff
#define B_AX_TXDMA_DMA_COUNTER_SH 0
#define B_AX_TXDMA_DMA_COUNTER_MSK 0xff
#define R_AX_USB_DEBUG_2 0x11D8
#define B_AX_REGISTER_READ_COUNTER_SH 8
#define B_AX_REGISTER_READ_COUNTER_MSK 0xff
#define B_AX_REGISTER_WRITE_COUNTER_SH 0
#define B_AX_REGISTER_WRITE_COUNTER_MSK 0xff
#define R_AX_USB_DEBUG_3 0x11DC
#define B_AX_RX_PATH_STATE_MACHINE_SH 24
#define B_AX_RX_PATH_STATE_MACHINE_MSK 0xff
#define B_AX_TX_PATH_STATE_MACHINE_SH 16
#define B_AX_TX_PATH_STATE_MACHINE_MSK 0xff
#define B_AX_IO_PATH_STATE_MACHINE_SH 8
#define B_AX_IO_PATH_STATE_MACHINE_MSK 0xffffff
#define B_AX_TXVLD_TOGGLE_VAL_SH 8
#define B_AX_TXVLD_TOGGLE_VAL_MSK 0xf
#define B_AX_TXVLD_TOUT_VAL_SH 0
#define B_AX_TXVLD_TOUT_VAL_MSK 0xff
#define R_AX_USB_STATUS 0x11F0
#define B_AX_USB_EP_NUM_SH 4
#define B_AX_USB_EP_NUM_MSK 0xf
#define B_AX_R_SSIC_EN BIT(2)
#define B_AX_R_USB2_SEL BIT(1)
#define B_AX_MODE_HS BIT(0)
#define R_AX_USB_D2F_F2D_INFO 0x1200
#define B_AX_HRPWM2_SH 16
#define B_AX_HRPWM2_MSK 0xffff
#define B_AX_CPWM2_SH 0
#define B_AX_CPWM2_MSK 0xffff
#define R_AX_USB3 0x1220
#define B_AX_U3_STATE_SH 12
#define B_AX_U3_STATE_MSK 0xf
#define B_AX_U3_SUB_STATE_SH 8
#define B_AX_U3_SUB_STATE_MSK 0xf
#define B_AX_HPS_CLKR_USB_SH 0
#define B_AX_HPS_CLKR_USB_MSK 0xff
#define R_AX_USB_OTHERS_0 0x1230
#define B_AX_USBTX_EP3IF_OK_CNT_SH 24
#define B_AX_USBTX_EP3IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP2IF_OK_CNT_SH 16
#define B_AX_USBTX_EP2IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP1IF_OK_CNT_SH 8
#define B_AX_USBTX_EP1IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP0IF_OK_CNT_SH 0
#define B_AX_USBTX_EP0IF_OK_CNT_MSK 0xff
#define R_AX_USB_OTHERS_1 0x1234
#define B_AX_USBTX_EP7IF_OK_CNT_SH 24
#define B_AX_USBTX_EP7IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP6IF_OK_CNT_SH 16
#define B_AX_USBTX_EP6IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP5IF_OK_CNT_SH 8
#define B_AX_USBTX_EP5IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP4IF_OK_CNT_SH 0
#define B_AX_USBTX_EP4IF_OK_CNT_MSK 0xff
#define R_AX_USB_OTHERS_2 0x1238
#define B_AX_USBRX_DMAIF_OK_CNT_SH 24
#define B_AX_USBRX_DMAIF_OK_CNT_MSK 0xff
#define B_AX_USBRX_EPIF_OK_CNT_SH 16
#define B_AX_USBRX_EPIF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP9IF_OK_CNT_SH 8
#define B_AX_USBTX_EP9IF_OK_CNT_MSK 0xff
#define B_AX_USBTX_EP8IF_OK_CNT_SH 0
#define B_AX_USBTX_EP8IF_OK_CNT_MSK 0xff
#define R_AX_USB_OTHERS_3 0x123C
#define B_AX_VENDOR_LMP_LATCH_DATA_L_SH 0
#define B_AX_VENDOR_LMP_LATCH_DATA_L_MSK 0xffffffffL
#define R_AX_USB_OTHERS_4 0x1240
#define B_AX_VENDOR_LMP_LATCH_DATA_H_SH 0
#define B_AX_VENDOR_LMP_LATCH_DATA_H_MSK 0xffffffffL
#define R_AX_USB_OTHERS_5 0x1244
#define B_AX_APPEND_ZERO_PKT_SH 24
#define B_AX_APPEND_ZERO_PKT_MSK 0xff
#define B_AX_USB_AUTO_LOAD_EXTE_7_SH 21
#define B_AX_USB_AUTO_LOAD_EXTE_7_MSK 0x3
#define B_AX_USB_AUTO_LOAD_EXTE_0_SH 16
#define B_AX_USB_AUTO_LOAD_EXTE_0_MSK 0x1f
#define B_AX_USB_AUTO_LOAD_EXTE_2_SH 8
#define B_AX_USB_AUTO_LOAD_EXTE_2_MSK 0xff
#define B_AX_USB_AUTO_LOAD_EXTE_1_SH 0
#define B_AX_USB_AUTO_LOAD_EXTE_1_MSK 0xff
#define R_AX_USB_OTHERS_6 0x1248
#define B_AX_USB_AUTO_LOAD_STRING_3_SH 24
#define B_AX_USB_AUTO_LOAD_STRING_3_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_2_SH 16
#define B_AX_USB_AUTO_LOAD_STRING_2_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_1_SH 8
#define B_AX_USB_AUTO_LOAD_STRING_1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_0_SH 0
#define B_AX_USB_AUTO_LOAD_STRING_0_MSK 0xff
#define R_AX_USB_OTHERS_7 0x124C
#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_SH 22
#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_MSK 0xff
#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_SH 14
#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_FLAG BIT(13)
#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_SH 7
#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_MSK 0x3f
#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_SH 0
#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_MSK 0x7f
#define R_AX_USB_WATCHDOG 0x1260
#define B_AX_USBIO_WD_FLAG BIT(31)
#define B_AX_USBIO_WD_EN BIT(30)
#define B_AX_USBIO_WD_TIMER_SH 24
#define B_AX_USBIO_WD_TIMER_MSK 0xf
#define B_AX_USBIO_WD_ADDR_SH 0
#define B_AX_USBIO_WD_ADDR_MSK 0xffffff
#define R_AX_HUSBIMR 0x1270
#define B_AX_HD1ISR_B00_IND_INT_EN BIT(26)
#define B_AX_USBRX_INT_EN BIT(7)
#define B_AX_PUSBTX_CH12_INT_EN BIT(6)
#define B_AX_USBTX_CH10_INT_EN BIT(5)
#define B_AX_USBTX_CH8_INT_EN BIT(4)
#define B_AX_USBTX_ACH6_INT_EN BIT(3)
#define B_AX_USBTX_ACH4_INT_EN BIT(2)
#define B_AX_USBTX_ACH2_INT_EN BIT(1)
#define B_AX_USBTX_ACH0_INT_EN BIT(0)
#define R_AX_HUSBISR 0x1274
#define B_AX_HD1ISR_B00_IND_INT BIT(26)
#define B_AX_USBRX_INT BIT(7)
#define B_AX_PUSBTX_CH12_INT BIT(6)
#define B_AX_USBTX_CH10_INT BIT(5)
#define B_AX_USBTX_CH8_INT BIT(4)
#define B_AX_USBTX_ACH6_INT BIT(3)
#define B_AX_USBTX_ACH4_INT BIT(2)
#define B_AX_USBTX_ACH2_INT BIT(1)
#define B_AX_USBTX_ACH0_INT BIT(0)
//
// WL_AX_Reg_USB.xls
//
//
// 8852C USB_REG
//
#define R_AX_USB2_MAC_0_V1 0x5000
#define B_AX_TOUT_DELAY_FS_V1_SH 24
#define B_AX_TOUT_DELAY_FS_V1_MSK 0xff
#define B_AX_TOUT_DELAY_HS_V1_SH 16
#define B_AX_TOUT_DELAY_HS_V1_MSK 0xff
#define B_AX_TOUT_DIS_V1 BIT(15)
#define B_AX_CRC_CHK_OPT_V1 BIT(14)
#define B_AX_FORCE_PCERST_V1 BIT(13)
#define B_AX_FORCE_TOGL_V1 BIT(12)
#define B_AX_FORCE_TOGLSEL_V1 BIT(11)
#define B_AX_FORCE_PIDSW_V1 BIT(10)
#define B_AX_FORCE_PCE_IN_V1 BIT(9)
#define B_AX_FORCE_PCE_OUT_V1 BIT(8)
#define B_AX_PID_FORCE_V1_SH 0
#define B_AX_PID_FORCE_V1_MSK 0xff
#define R_AX_USB2_MAC_1_V1 0x5004
#define B_AX_FORCE_PCE_CMD_V1 BIT(31)
#define R_AX_USB2_LINK_PORT_V1 0x5008
#define B_AX_R_HOST_PWR_CTRL_V1 BIT(23)
#define B_AX_R_USB2_CLR_TXVLD_V1 BIT(22)
#define B_AX_R_USB2_SE0_V1 BIT(21)
#define B_AX_HOST_RESUME_EDGE_EN_V1 BIT(20)
#define B_AX_RESUME_SEL_V1_SH 16
#define B_AX_RESUME_SEL_V1_MSK 0xf
#define B_AX_DELAY_CHIRP_K_V1_SH 14
#define B_AX_DELAY_CHIRP_K_V1_MSK 0x3
#define B_AX_FORCE_TXVLD1_V1 BIT(13)
#define B_AX_FORCE_TXVLD0_V1 BIT(12)
#define B_AX_DORCE_DAT1_V1 BIT(11)
#define B_AX_FORCE_DAT0_V1 BIT(10)
#define B_AX_LS_TEST_V1 BIT(9)
#define B_AX_LS_CHANGE_V1 BIT(8)
#define B_AX_FORCE_HS_SW_V1 BIT(7)
#define B_AX_FORCE_FS_SW_V1 BIT(6)
#define B_AX_FORCE_HSXCVR_V1 BIT(5)
#define B_AX_FORCE_FSXCVR_V1 BIT(4)
#define B_AX_FORCE_HSTERM_V1 BIT(3)
#define B_AX_FORCE_FSTERM_V1 BIT(2)
#define B_AX_FORCE_NORM_SW_V1 BIT(1)
#define B_AX_FORCE_DBSN_V1 BIT(0)
#define R_AX_USB2_LPM_0_V1 0x5010
#define B_AX_USBPHY_PLL_ALIVE_V1 BIT(17)
#define B_AX_USB_LPM_MAX_EN_V1 BIT(16)
#define B_AX_USB_LPM_MIN_EN_V1 BIT(15)
#define B_AX_BESL_EN_V1 BIT(14)
#define B_AX_USB_LPM_NYET_EN_V1 BIT(13)
#define B_AX_USB_LPM_MAX_ACK_V1 BIT(12)
#define B_AX_USB_LPM_EN_V1 BIT(11)
#define B_AX_USB2_SUSB_V1 BIT(10)
#define B_AX_LPM_PLL_ALIVE_V1 BIT(9)
#define B_AX_USB_LPS_OUT_V1 BIT(8)
#define B_AX_USB_LPM_WAKEUP_EN_V1 BIT(6)
#define B_AX_NEVER_SUSPEND_V1 BIT(5)
#define B_AX_SUSPND_EN_V1 BIT(4)
#define B_AX_WAKEUP_EN_V1 BIT(3)
#define B_AX_USB_SUS_WAKEUP_EN_V1 BIT(2)
#define B_AX_RESUME_SND_V1 BIT(1)
#define B_AX_CONNECT_EN_V1 BIT(0)
#define R_AX_USB2_LPM_1_V1 0x5014
#define B_AX_USB_LPM_MAX_V1_SH 20
#define B_AX_USB_LPM_MAX_V1_MSK 0xf
#define B_AX_USB_LPM_MIN_V1_SH 16
#define B_AX_USB_LPM_MIN_V1_MSK 0xf
#define B_AX_R_WAKE_HOST_WT_H_V1_SH 8
#define B_AX_R_WAKE_HOST_WT_H_V1_MSK 0xff
#define B_AX_R_WAKE_HOST_WT_L_V1_SH 0
#define B_AX_R_WAKE_HOST_WT_L_V1_MSK 0xff
#define R_AX_USB2_MACRO_TEST_MODE_V1 0x5018
#define B_AX_TXRDY_SLB_SEL_V1 BIT(14)
#define B_AX_SLB_EN_V1 BIT(13)
#define B_AX_SLB_RST_V1 BIT(12)
#define B_AX_SLB_FAIL_V1 BIT(11)
#define B_AX_SLB_DONE_V1 BIT(10)
#define B_AX_SLB_PS1_SW_V1_SH 8
#define B_AX_SLB_PS1_SW_V1_MSK 0x3
#define B_AX_PHY_LOOP_TEST_V1 BIT(3)
#define B_AX_USBTMOD_V1_SH 0
#define B_AX_USBTMOD_V1_MSK 0x7
#define R_AX_USB2_PHY_REG_0_V1 0x5020
#define B_AX_USB2PHY_REG_EN_V1 BIT(17)
#define B_AX_VLPADM_V1 BIT(16)
#define B_AX_VSTATUS_IN_V1_SH 8
#define B_AX_VSTATUS_IN_V1_MSK 0xff
#define B_AX_VCONTROL_V1_SH 0
#define B_AX_VCONTROL_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_1_V1 0x5024
#define B_AX_USB2PHY_DELAY_V1_SH 8
#define B_AX_USB2PHY_DELAY_V1_MSK 0xff
#define B_AX_VSTATUS_OUT_V1_SH 0
#define B_AX_VSTATUS_OUT_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_2_V1 0x5028
#define B_AX_USB2_PHY_P0_E3_V1_SH 24
#define B_AX_USB2_PHY_P0_E3_V1_MSK 0xff
#define B_AX_USB2_PHY_P0_E2_V1_SH 16
#define B_AX_USB2_PHY_P0_E2_V1_MSK 0xff
#define B_AX_USB2_PHY_P0_E1_V1_SH 8
#define B_AX_USB2_PHY_P0_E1_V1_MSK 0xff
#define B_AX_USB2_PHY_P0_E0_V1_SH 0
#define B_AX_USB2_PHY_P0_E0_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_3_V1 0x502C
#define B_AX_USB2_PHY_P0_E7_V1_SH 24
#define B_AX_USB2_PHY_P0_E7_V1_MSK 0xff
#define B_AX_USB2_PHY_P0_E6_V1_SH 16
#define B_AX_USB2_PHY_P0_E6_V1_MSK 0xff
#define B_AX_USB2_PHY_P0_E5_V1_SH 8
#define B_AX_USB2_PHY_P0_E5_V1_MSK 0xff
#define B_AX_USB2_PHY_P0_E4_V1_SH 0
#define B_AX_USB2_PHY_P0_E4_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_4_V1 0x5030
#define B_AX_USB2_PHY_P1_E3_V1_SH 24
#define B_AX_USB2_PHY_P1_E3_V1_MSK 0xff
#define B_AX_USB2_PHY_P1_E2_V1_SH 16
#define B_AX_USB2_PHY_P1_E2_V1_MSK 0xff
#define B_AX_USB2_PHY_P1_E1_V1_SH 8
#define B_AX_USB2_PHY_P1_E1_V1_MSK 0xff
#define B_AX_USB2_PHY_P1_E0_V1_SH 0
#define B_AX_USB2_PHY_P1_E0_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_5_V1 0x5034
#define B_AX_USB2_PHY_P1_E7_V1_SH 24
#define B_AX_USB2_PHY_P1_E7_V1_MSK 0xff
#define B_AX_USB2_PHY_P1_E6_V1_SH 16
#define B_AX_USB2_PHY_P1_E6_V1_MSK 0xff
#define B_AX_USB2_PHY_P1_E5_V1_SH 8
#define B_AX_USB2_PHY_P1_E5_V1_MSK 0xff
#define B_AX_USB2_PHY_P1_E4_V1_SH 0
#define B_AX_USB2_PHY_P1_E4_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_6_V1 0x5038
#define B_AX_USB2_PHY_F3_V1_SH 24
#define B_AX_USB2_PHY_F3_V1_MSK 0xff
#define B_AX_USB2_PHY_F2_V1_SH 16
#define B_AX_USB2_PHY_F2_V1_MSK 0xff
#define B_AX_USB2_PHY_F1_V1_SH 8
#define B_AX_USB2_PHY_F1_V1_MSK 0xff
#define B_AX_USB2_PHY_F0_V1_SH 0
#define B_AX_USB2_PHY_F0_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_7_V1 0x503C
#define B_AX_USB2_PHY_F7_V1_SH 24
#define B_AX_USB2_PHY_F7_V1_MSK 0xff
#define B_AX_USB2_PHY_F6_V1_SH 16
#define B_AX_USB2_PHY_F6_V1_MSK 0xff
#define B_AX_USB2_PHY_F5_V1_SH 8
#define B_AX_USB2_PHY_F5_V1_MSK 0xff
#define B_AX_USB2_PHY_F4_V1_SH 0
#define B_AX_USB2_PHY_F4_V1_MSK 0xff
#define R_AX_USB2_PHY_REG_8_V1 0x5040
#define B_AX_USB2PHY_UPDATE_2_V1_SH 16
#define B_AX_USB2PHY_UPDATE_2_V1_MSK 0xff
#define B_AX_USB2PHY_UPDATE_1_V1_SH 8
#define B_AX_USB2PHY_UPDATE_1_V1_MSK 0xff
#define B_AX_USB2PHY_UPDATE_0_V1_SH 0
#define B_AX_USB2PHY_UPDATE_0_V1_MSK 0xff
#define R_AX_USB_ENDPOINT_0_V1 0x5060
#define B_AX_EP_MAXPKT_V1_SH 16
#define B_AX_EP_MAXPKT_V1_MSK 0x3ff
#define B_AX_EP_EN_V1 BIT(15)
#define B_AX_EP_TYPE_V1_SH 13
#define B_AX_EP_TYPE_V1_MSK 0x3
#define B_AX_EP_ISTALL_V1 BIT(12)
#define B_AX_EP_OSTALL_V1 BIT(11)
#define B_AX_EP_STREAMEN_V1 BIT(10)
#define B_AX_EP_OUT_V1 BIT(9)
#define B_AX_EP_IN_V1 BIT(8)
#define B_AX_BT_INTR_SEL_V1 BIT(5)
#define B_AX_R_SIE_INIT_DONE_V1 BIT(4)
#define B_AX_EP_IDX_V1_SH 0
#define B_AX_EP_IDX_V1_MSK 0xf
#define R_AX_USB_ENDPOINT_1_V1 0x5064
#define B_AX_EP_MAX_STREAM_V1_SH 16
#define B_AX_EP_MAX_STREAM_V1_MSK 0xff
#define B_AX_EP_MAX_BURST_V1_SH 8
#define B_AX_EP_MAX_BURST_V1_MSK 0xff
#define B_AX_EP_INT_INTERVAL_V1_SH 0
#define B_AX_EP_INT_INTERVAL_V1_MSK 0xff
#define R_AX_USB_ENDPOINT_2_V1 0x5068
#define B_AX_EP_BPI_V1_SH 16
#define B_AX_EP_BPI_V1_MSK 0xffff
#define B_AX_USB3_EP_IN_ST_V1_SH 8
#define B_AX_USB3_EP_IN_ST_V1_MSK 0xff
#define B_AX_USB3_EP_OUT_ST_V1_SH 0
#define B_AX_USB3_EP_OUT_ST_V1_MSK 0xff
#define R_AX_USB_ENDPOINT_3_V1 0x506C
#define B_AX_EP12_PAUSE_STATE_V1 BIT(31)
#define B_AX_EP11_PAUSE_STATE_V1 BIT(30)
#define B_AX_EP10_PAUSE_STATE_V1 BIT(29)
#define B_AX_EP9_PAUSE_STATE_V1 BIT(28)
#define B_AX_EP8_PAUSE_STATE_V1 BIT(27)
#define B_AX_EP7_PAUSE_STATE_V1 BIT(26)
#define B_AX_EP6_PAUSE_STATE_V1 BIT(25)
#define B_AX_EP5_PAUSE_STATE_V1 BIT(24)
#define B_AX_EP4_PAUSE_STATE_V1 BIT(23)
#define B_AX_EP12_TX_PAUSE_V1 BIT(22)
#define B_AX_EP11_TX_PAUSE_V1 BIT(21)
#define B_AX_EP10_TX_PAUSE_V1 BIT(20)
#define B_AX_EP9_TX_PAUSE_V1 BIT(19)
#define B_AX_EP8_RX_PAUSE_V1 BIT(18)
#define B_AX_EP7_TX_PAUSE_V1 BIT(17)
#define B_AX_EP6_TX_PAUSE_V1 BIT(16)
#define B_AX_EP5_TX_PAUSE_V1 BIT(15)
#define B_AX_EP4_RX_PAUSE_V1 BIT(14)
#define B_AX_INTERRUPT_BULK_IN_V1 BIT(12)
#define B_AX_AC_BULKOUT_V1_SH 10
#define B_AX_AC_BULKOUT_V1_MSK 0x3
#define B_AX_BULKOUT1_V1 BIT(9)
#define B_AX_BULKOUT0_V1 BIT(8)
#define B_AX_INTERRUPT_INTERVAL_V1_SH 0
#define B_AX_INTERRUPT_INTERVAL_V1_MSK 0xf
#define R_AX_USB_HOST_REQUEST_0_V1 0x5070
#define B_AX_ERR_STR2_LEN_V1_SH 24
#define B_AX_ERR_STR2_LEN_V1_MSK 0xff
#define B_AX_ERR_STR1_LEN_V1_SH 8
#define B_AX_ERR_STR1_LEN_V1_MSK 0xffff
#define B_AX_DEVADDR_V1_SH 0
#define B_AX_DEVADDR_V1_MSK 0x7f
#define R_AX_USB_HOST_REQUEST_1_V1 0x5074
#define B_AX_USB_PID_V1_SH 16
#define B_AX_USB_PID_V1_MSK 0xffff
#define B_AX_USB_VID_V1_SH 0
#define B_AX_USB_VID_V1_MSK 0xffff
#define R_AX_USB_HOST_REQUEST_2_V1 0x5078
#define B_AX_MAC_ADDR_1_V1_SH 24
#define B_AX_MAC_ADDR_1_V1_MSK 0xff
#define B_AX_MAC_ADDR_0_V1_SH 16
#define B_AX_MAC_ADDR_0_V1_MSK 0xff
#define B_AX_FORCE_LPM_BCD201_V1 BIT(15)
#define B_AX_SELF_POWER_EN_V1 BIT(14)
#define B_AX_R_FORCE_U3MAC_HS_MODE_V1 BIT(13)
#define B_AX_LOAD_LTM_CAP_V1 BIT(12)
#define B_AX_USB3_DEV_CAP_DESC_EN_V1 BIT(11)
#define B_AX_AUTOLOAD_STRING_EN_V1 BIT(10)
#define B_AX_REMOTE_WAKEUP_V1 BIT(9)
#define B_AX_SQNUM_ROM_V1 BIT(8)
#define B_AX_ERR_STR2_LEN_FLAG_V1 BIT(7)
#define B_AX_ERR_STR1_LEN_FLAG_V1 BIT(6)
#define B_AX_ERR_STR0_LEN_FLAG_V1 BIT(5)
#define B_AX_R_USBIO_MODE_V1 BIT(4)
#define B_AX_EXREG_TO_EN_V1 BIT(3)
#define B_AX_EXREG_TO_SEL_V1_SH 0
#define B_AX_EXREG_TO_SEL_V1_MSK 0x7
#define R_AX_USB_HOST_REQUEST_3_V1 0x507C
#define B_AX_MAC_ADDR_5_V1_SH 24
#define B_AX_MAC_ADDR_5_V1_MSK 0xff
#define B_AX_MAC_ADDR_4_V1_SH 16
#define B_AX_MAC_ADDR_4_V1_MSK 0xff
#define B_AX_MAC_ADDR_3_V1_SH 8
#define B_AX_MAC_ADDR_3_V1_MSK 0xff
#define B_AX_MAC_ADDR_2_V1_SH 0
#define B_AX_MAC_ADDR_2_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_4_V1 0x5080
#define B_AX__MANUFACTURE_STRING_3_V1_SH 24
#define B_AX__MANUFACTURE_STRING_3_V1_MSK 0xff
#define B_AX__MANUFACTURE_STRING_2_V1_SH 16
#define B_AX__MANUFACTURE_STRING_2_V1_MSK 0xff
#define B_AX__MANUFACTURE_STRING_1_V1_SH 8
#define B_AX__MANUFACTURE_STRING_1_V1_MSK 0xff
#define B_AX__MANUFACTURE_STRING_0_V1_SH 0
#define B_AX__MANUFACTURE_STRING_0_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_5_V1 0x5084
#define B_AX_MANUFACTURE_STRING_7_V1_SH 24
#define B_AX_MANUFACTURE_STRING_7_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_6_V1_SH 16
#define B_AX_MANUFACTURE_STRING_6_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_5_V1_SH 8
#define B_AX_MANUFACTURE_STRING_5_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_4_V1_SH 0
#define B_AX_MANUFACTURE_STRING_4_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_6_V1 0x5088
#define B_AX_MANUFACTURE_STRING_B_V1_SH 24
#define B_AX_MANUFACTURE_STRING_B_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_A_V1_SH 16
#define B_AX_MANUFACTURE_STRING_A_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_9_V1_SH 8
#define B_AX_MANUFACTURE_STRING_9_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_8_V1_SH 0
#define B_AX_MANUFACTURE_STRING_8_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_7_V1 0x508C
#define B_AX_MANUFACTURE_STRING_F_V1_SH 24
#define B_AX_MANUFACTURE_STRING_F_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_E_V1_SH 16
#define B_AX_MANUFACTURE_STRING_E_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_D_V1_SH 8
#define B_AX_MANUFACTURE_STRING_D_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_C_V1_SH 0
#define B_AX_MANUFACTURE_STRING_C_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_8_V1 0x5090
#define B_AX_MANUFACTURE_STRING_13_V1_SH 24
#define B_AX_MANUFACTURE_STRING_13_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_12_V1_SH 16
#define B_AX_MANUFACTURE_STRING_12_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_11_V1_SH 8
#define B_AX_MANUFACTURE_STRING_11_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_10_V1_SH 0
#define B_AX_MANUFACTURE_STRING_10_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_9_V1 0x5094
#define B_AX_MANUFACTURE_STRING_17_V1_SH 24
#define B_AX_MANUFACTURE_STRING_17_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_16_V1_SH 16
#define B_AX_MANUFACTURE_STRING_16_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_15_V1_SH 8
#define B_AX_MANUFACTURE_STRING_15_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_14_V1_SH 0
#define B_AX_MANUFACTURE_STRING_14_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_A_V1 0x5098
#define B_AX_MANUFACTURE_STRING_1B_V1_SH 24
#define B_AX_MANUFACTURE_STRING_1B_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1A_V1_SH 16
#define B_AX_MANUFACTURE_STRING_1A_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_19_V1_SH 8
#define B_AX_MANUFACTURE_STRING_19_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_18_V1_SH 0
#define B_AX_MANUFACTURE_STRING_18_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_B_V1 0x509C
#define B_AX_MANUFACTURE_STRING_1F_V1_SH 24
#define B_AX_MANUFACTURE_STRING_1F_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1E_V1_SH 16
#define B_AX_MANUFACTURE_STRING_1E_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1D_V1_SH 8
#define B_AX_MANUFACTURE_STRING_1D_V1_MSK 0xff
#define B_AX_MANUFACTURE_STRING_1C_V1_SH 0
#define B_AX_MANUFACTURE_STRING_1C_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_C_V1 0x50A0
#define B_AX_PRODUCT_STRING_3_V1_SH 24
#define B_AX_PRODUCT_STRING_3_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_2_V1_SH 16
#define B_AX_PRODUCT_STRING_2_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_1_V1_SH 8
#define B_AX_PRODUCT_STRING_1_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_0_V1_SH 0
#define B_AX_PRODUCT_STRING_0_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_D_V1 0x50A4
#define B_AX_PRODUCT_STRING_7_V1_SH 24
#define B_AX_PRODUCT_STRING_7_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_6_V1_SH 16
#define B_AX_PRODUCT_STRING_6_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_5_V1_SH 8
#define B_AX_PRODUCT_STRING_5_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_4_V1_SH 0
#define B_AX_PRODUCT_STRING_4_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_E_V1 0x50A8
#define B_AX_PRODUCT_STRING_B_V1_SH 24
#define B_AX_PRODUCT_STRING_B_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_A_V1_SH 16
#define B_AX_PRODUCT_STRING_A_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_9_V1_SH 8
#define B_AX_PRODUCT_STRING_9_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_8_V1_SH 0
#define B_AX_PRODUCT_STRING_8_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_F_V1 0x50AC
#define B_AX_PRODUCT_STRING_F_V1_SH 24
#define B_AX_PRODUCT_STRING_F_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_E_V1_SH 16
#define B_AX_PRODUCT_STRING_E_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_D_V1_SH 8
#define B_AX_PRODUCT_STRING_D_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_C_V1_SH 0
#define B_AX_PRODUCT_STRING_C_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_10_V1 0x50B0
#define B_AX_PRODUCT_STRING_13_V1_SH 24
#define B_AX_PRODUCT_STRING_13_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_12_V1_SH 16
#define B_AX_PRODUCT_STRING_12_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_11_V1_SH 8
#define B_AX_PRODUCT_STRING_11_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_10_V1_SH 0
#define B_AX_PRODUCT_STRING_10_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_11_V1 0x50B4
#define B_AX_PRODUCT_STRING_17_V1_SH 24
#define B_AX_PRODUCT_STRING_17_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_16_V1_SH 16
#define B_AX_PRODUCT_STRING_16_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_15_V1_SH 8
#define B_AX_PRODUCT_STRING_15_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_14_V1_SH 0
#define B_AX_PRODUCT_STRING_14_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_12_V1 0x50B8
#define B_AX_PRODUCT_STRING_1B_V1_SH 24
#define B_AX_PRODUCT_STRING_1B_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_1A_V1_SH 16
#define B_AX_PRODUCT_STRING_1A_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_19_V1_SH 8
#define B_AX_PRODUCT_STRING_19_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_18_V1_SH 0
#define B_AX_PRODUCT_STRING_18_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_13_V1 0x50BC
#define B_AX_PRODUCT_STRING_1F_V1_SH 24
#define B_AX_PRODUCT_STRING_1F_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_1E_V1_SH 16
#define B_AX_PRODUCT_STRING_1E_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_1D_V1_SH 8
#define B_AX_PRODUCT_STRING_1D_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_1C_V1_SH 0
#define B_AX_PRODUCT_STRING_1C_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_14_V1 0x50C0
#define B_AX_PRODUCT_STRING_23_V1_SH 24
#define B_AX_PRODUCT_STRING_23_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_22_V1_SH 16
#define B_AX_PRODUCT_STRING_22_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_21_V1_SH 8
#define B_AX_PRODUCT_STRING_21_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_20_V1_SH 0
#define B_AX_PRODUCT_STRING_20_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_15_V1 0x50C4
#define B_AX_PRODUCT_STRING_27_V1_SH 24
#define B_AX_PRODUCT_STRING_27_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_26_V1_SH 16
#define B_AX_PRODUCT_STRING_26_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_25_V1_SH 8
#define B_AX_PRODUCT_STRING_25_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_24_V1_SH 0
#define B_AX_PRODUCT_STRING_24_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_16_V1 0x50C8
#define B_AX_PRODUCT_STRING_2B_V1_SH 24
#define B_AX_PRODUCT_STRING_2B_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_2A_V1_SH 16
#define B_AX_PRODUCT_STRING_2A_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_29_V1_SH 8
#define B_AX_PRODUCT_STRING_29_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_28_V1_SH 0
#define B_AX_PRODUCT_STRING_28_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_17_V1 0x50CC
#define B_AX_PRODUCT_STRING_2F_V1_SH 24
#define B_AX_PRODUCT_STRING_2F_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_2E_V1_SH 16
#define B_AX_PRODUCT_STRING_2E_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_2D_V1_SH 8
#define B_AX_PRODUCT_STRING_2D_V1_MSK 0xff
#define B_AX_PRODUCT_STRING_2C_V1_SH 0
#define B_AX_PRODUCT_STRING_2C_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_18_V1 0x50D0
#define B_AX_SERIAL_NUMBER_STRING_3_V1_SH 24
#define B_AX_SERIAL_NUMBER_STRING_3_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_2_V1_SH 16
#define B_AX_SERIAL_NUMBER_STRING_2_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_1_V1_SH 8
#define B_AX_SERIAL_NUMBER_STRING_1_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_0_V1_SH 0
#define B_AX_SERIAL_NUMBER_STRING_0_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_19_V1 0x50D4
#define B_AX_SERIAL_NUMBER_STRING_7_V1_SH 24
#define B_AX_SERIAL_NUMBER_STRING_7_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_6_V1_SH 16
#define B_AX_SERIAL_NUMBER_STRING_6_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_5_V1_SH 8
#define B_AX_SERIAL_NUMBER_STRING_5_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_4_V1_SH 0
#define B_AX_SERIAL_NUMBER_STRING_4_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1A_V1 0x50D8
#define B_AX_SERIAL_NUMBER_STRING_B_V1_SH 24
#define B_AX_SERIAL_NUMBER_STRING_B_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_A_V1_SH 16
#define B_AX_SERIAL_NUMBER_STRING_A_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_9_V1_SH 8
#define B_AX_SERIAL_NUMBER_STRING_9_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_8_V1_SH 0
#define B_AX_SERIAL_NUMBER_STRING_8_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1B_V1 0x50DC
#define B_AX_SERIAL_NUMBER_STRING_F_V1_SH 24
#define B_AX_SERIAL_NUMBER_STRING_F_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_E_V1_SH 16
#define B_AX_SERIAL_NUMBER_STRING_E_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_D_V1_SH 8
#define B_AX_SERIAL_NUMBER_STRING_D_V1_MSK 0xff
#define B_AX_SERIAL_NUMBER_STRING_C_V1_SH 0
#define B_AX_SERIAL_NUMBER_STRING_C_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1C_V1 0x50E0
#define B_AX_USB3_U2SEL_V1_SH 16
#define B_AX_USB3_U2SEL_V1_MSK 0xffff
#define B_AX_USB3_U1PEL_V1_SH 0
#define B_AX_USB3_U1PEL_V1_MSK 0xffff
#define R_AX_USB_HOST_REQUEST_1D_V1 0x50E4
#define B_AX_HW_VENDOR_INDEX_V1_SH 16
#define B_AX_HW_VENDOR_INDEX_V1_MSK 0xff
#define R_AX_USB_HOST_REQUEST_1E_V1 0x50E8
#define B_AX_DIS_STALL_FUNC_WAKE_V1 BIT(24)
#define B_AX_USB3_U2_DEV_EXIT_LAT_V1_SH 8
#define B_AX_USB3_U2_DEV_EXIT_LAT_V1_MSK 0xffff
#define B_AX_USB3_U1_DEV_EXIT_LAT_V1_SH 0
#define B_AX_USB3_U1_DEV_EXIT_LAT_V1_MSK 0xff
#define R_AX_USB3_MAC_LINK_0_V1 0x5100
#define B_AX_INTS_USB3_HRESET_EN_V1 BIT(31)
#define B_AX_INTS_USB3_RECOV_EN_V1 BIT(30)
#define B_AX_INTS_USB3_LPBK_EN_V1 BIT(29)
#define B_AX_INTS_USB3_RXDET_EN_V1 BIT(28)
#define B_AX_INTS_USB3_POLL_EN_V1 BIT(27)
#define B_AX_INTS_USB3_U3_EN_V1 BIT(26)
#define B_AX_INTS_USB3_U1U2_EN_V1 BIT(25)
#define B_AX_INTS_USB3_U0_EN_V1 BIT(24)
#define B_AX_INTS_USB3_RECOV2U0_EN_V1 BIT(23)
#define B_AX_INTS_USB3_SSINACT_EN_V1 BIT(22)
#define B_AX_INTS_USB3_SSDIS_EN_V1 BIT(21)
#define B_AX_INTS_USB3_CMPLY_EN_V1 BIT(20)
#define B_AX_INTS_USB3_RECOV2U0_V1 BIT(19)
#define B_AX_INTS_USB3_SSINACT_V1 BIT(18)
#define B_AX_INTS_USB3_SSDIS_V1 BIT(17)
#define B_AX_INTS_USB3_CMPLY_V1 BIT(16)
#define B_AX_INTS_USB3_HRESET_V1 BIT(15)
#define B_AX_INTS_USB3_RECOV_V1 BIT(14)
#define B_AX_INTS_USB3_LPBK_V1 BIT(13)
#define B_AX_INTS_USB3_RXDET_V1 BIT(12)
#define B_AX_INTS_USB3_POLL_V1 BIT(11)
#define B_AX_INTS_USB3_U3_V1 BIT(10)
#define B_AX_INTS_USB3_U1U2_V1 BIT(9)
#define B_AX_INTS_USB3_U0_V1 BIT(8)
#define B_AX_EN_ROVIDLE_TIMEOUT_V1 BIT(6)
#define B_AX_EN_UNFIN_RTY_V1 BIT(5)
#define B_AX_SSPHY_U1_QUICK_LFPS_V1 BIT(4)
#define B_AX_USB3_DIS_ISOC_TIME_GT_V1 BIT(3)
#define B_AX_R_DIS_USB3_U2_EN_V1 BIT(2)
#define B_AX_R_DIS_USB3_U1_EN_V1 BIT(1)
#define B_AX_LINK_ST_DETECT_TERM_V1 BIT(0)
#define R_AX_USB3_MAC_LINK_1_V1 0x5104
#define B_AX_WARM_RESET_TIME_V1_SH 0
#define B_AX_WARM_RESET_TIME_V1_MSK 0x3
#define R_AX_USB3_MAC_PIU_V1 0x5108
#define B_AX_SSPHY_CLR_TERM_V1 BIT(1)
#define B_AX_SSPHY_SET_TERM_V1 BIT(0)
#define R_AX_USB3_MAC_PTL_V1 0x510C
#define B_AX_BCDVALUE_V1_SH 2
#define B_AX_BCDVALUE_V1_MSK 0x3
#define B_AX_WLAN0_BUF_NUMP_EN_V1 BIT(1)
#define B_AX_IGNORE_RETRY_BIT_V1 BIT(0)
#define R_AX_USB3_MAC_PRTSM_V1 0x5110
#define B_AX_EN_IMMED_POP_CREDIT_V1 BIT(0)
#define R_AX_USB3_MAC_NPI_CONFIG_INTF_0_V1 0x5114
#define B_AX_SSPHY_LFPS_FILTER_V1 BIT(31)
#define B_AX_SSPHY_TX_SWING_V1 BIT(30)
#define B_AX_SSPHY_TXMARGIN_V1_SH 27
#define B_AX_SSPHY_TXMARGIN_V1_MSK 0x7
#define B_AX_SSPHY_TXDEEMPHASIS_V1_SH 25
#define B_AX_SSPHY_TXDEEMPHASIS_V1_MSK 0x3
#define B_AX_SSPHY_ELASTIC_BUF_V1 BIT(24)
#define B_AX_HIRD_THR_V1_SH 19
#define B_AX_HIRD_THR_V1_MSK 0x1f
#define B_AX_DEV_SPEED_V1_SH 16
#define B_AX_DEV_SPEED_V1_MSK 0x7
#define B_AX_U1_ACTIVE_TIMEOUT_V1_SH 8
#define B_AX_U1_ACTIVE_TIMEOUT_V1_MSK 0xff
#define B_AX_USB3_TARGET_LINK_STATE_V1_SH 4
#define B_AX_USB3_TARGET_LINK_STATE_V1_MSK 0xf
#define B_AX_APPL1RSP_V1 BIT(3)
#define B_AX_LPM_CAPABLE_V1 BIT(2)
#define B_AX_USB3_EOF_V1_SH 0
#define B_AX_USB3_EOF_V1_MSK 0x3
#define R_AX_USB3_MAC_NPI_CONFIG_INTF_1_V1 0x5118
#define B_AX_NPI_SCALEDOWN_MODE_V1_SH 24
#define B_AX_NPI_SCALEDOWN_MODE_V1_MSK 0x3
#define B_AX_SSPHY_POWERDOWN_SCALE_V1_SH 8
#define B_AX_SSPHY_POWERDOWN_SCALE_V1_MSK 0x1fff
#define B_AX_SSPHY_U1_FAST_OUT_V1 BIT(7)
#define B_AX_SSPHY_P3_FOR_P2_V1 BIT(6)
#define B_AX_SSPHY_U1_RXVALID_V1 BIT(5)
#define B_AX_SSPHY_DIS_SCAMBLE_V1 BIT(4)
#define B_AX_SSPHY_SKIP_RXDETECT_V1 BIT(3)
#define B_AX_SSPHY_LFPS_P0_ALIGN_V1 BIT(2)
#define B_AX_SSPHY_P3P2_TRANS_V1 BIT(1)
#define B_AX_SSPHY_P3_EXITIN_P2_V1 BIT(0)
#define R_AX_USB3_MAC_NPI_CONFIG_INTF_2_V1 0x511C
#define B_AX_SSPHY_U2EXIT_LPFS_V1 BIT(18)
#define B_AX_SSPHY_PHYSOFTRST_V1 BIT(17)
#define B_AX_SSPHY_HSTPRTCMPL_V1 BIT(16)
#define B_AX_SSPHY_U2SSINACTP3OK_V1 BIT(15)
#define B_AX_SSPHY_DISRXDETP3_V1 BIT(14)
#define B_AX_SSPHY_UX_EXIT_IN_PX_V1 BIT(13)
#define B_AX_SSPHY_PING_ENH_EN_V1 BIT(12)
#define B_AX_SSPHY_U1U2EXITFAIL_TO_RECOV_V1 BIT(11)
#define B_AX_SSPHY_ALWAYS_REQ_V1 BIT(10)
#define B_AX_SSPHY_START_RX_DET_V1 BIT(9)
#define B_AX_SSPHY_DIS_RX_DET_V1 BIT(8)
#define B_AX_SSPHY_DELAY_P1P2P3_V1_SH 5
#define B_AX_SSPHY_DELAY_P1P2P3_V1_MSK 0x7
#define B_AX_SSPHY_SUSPEND_EN_V1 BIT(4)
#define B_AX_SSPHY_DATWIDTH_V1_SH 2
#define B_AX_SSPHY_DATWIDTH_V1_MSK 0x3
#define B_AX_SSPHY_ABORTRXDETLNU2_V1 BIT(1)
#define B_AX_SSPHY_RX_DETECT_LPFS_V1 BIT(0)
#define R_AX_USB3_MAC_NPI_POWER_0_V1 0x5120
#define B_AX_U3_LTM_EN_V1 BIT(28)
#define B_AX_LINK_STATE_REQ_V1_SH 24
#define B_AX_LINK_STATE_REQ_V1_MSK 0xf
#define B_AX_SUSCLK_RATIO_V1_SH 8
#define B_AX_SUSCLK_RATIO_V1_MSK 0x1fff
#define B_AX_TEST_CTRL_V1_SH 4
#define B_AX_TEST_CTRL_V1_MSK 0xf
#define B_AX_UFRAME_SCALE_V1_SH 2
#define B_AX_UFRAME_SCALE_V1_MSK 0x3
#define B_AX_LOCAL_LBK_V1 BIT(1)
#define B_AX_EN_SLEEP_USB_V1 BIT(0)
#define R_AX_USB3_MAC_NPI_POWER_1_V1 0x5124
#define B_AX_WAKE_WAIT_XTAL_V1 BIT(27)
#define B_AX_WAKE_WAIT_CURRENT_V1 BIT(26)
#define B_AX_WAKEUP_NEG_SEL_V1 BIT(25)
#define B_AX_SSPHY_USB3_ATTEMPT_V1 BIT(24)
#define B_AX_WAIT_IDLE_TIME_V1_SH 20
#define B_AX_WAIT_IDLE_TIME_V1_MSK 0xf
#define B_AX_U2_EN_MAC_IDLE_V1 BIT(18)
#define B_AX_U1_EN_MAC_IDLE_V1 BIT(17)
#define B_AX_SWITCH_CLK_EN_V1 BIT(16)
#define B_AX_USB3_SAMPLE_RXELECIDLE_V1_SH 8
#define B_AX_USB3_SAMPLE_RXELECIDLE_V1_MSK 0xff
#define B_AX_U3_INIT_U2_V1 BIT(7)
#define B_AX_U3_INIT_U1_V1 BIT(6)
#define B_AX_SET_U3_WAKE_V1 BIT(5)
#define B_AX_U3_U2_EN_V1 BIT(4)
#define B_AX_U3_U1_EN_V1 BIT(3)
#define B_AX_U3_INIT_U2_EN_V1 BIT(2)
#define B_AX_U3_INIT_U1_EN_V1 BIT(1)
#define B_AX_USB3_RUN_V1 BIT(0)
#define R_AX_USB3_MAC_NPI_POWER_2_V1 0x5128
#define B_AX_NPI_LINK_STATE_LATCH_V1_SH 16
#define B_AX_NPI_LINK_STATE_LATCH_V1_MSK 0xff
#define B_AX_NPI_HOST_RESUME_DETECTED_V1 BIT(15)
#define B_AX_NPI_DEV_CONNECT_SPEED_V1_SH 12
#define B_AX_NPI_DEV_CONNECT_SPEED_V1_MSK 0x7
#define B_AX_NPI_LINK_STATE_V1_SH 8
#define B_AX_NPI_LINK_STATE_V1_MSK 0xf
#define B_AX_POLL_EN_V1 BIT(7)
#define B_AX_POLL_SAMPLE_ON_V1 BIT(6)
#define B_AX_POLL_ACT_V1_SH 4
#define B_AX_POLL_ACT_V1_MSK 0x3
#define B_AX_POLL_NOACT_V1_SH 0
#define B_AX_POLL_NOACT_V1_MSK 0xf
#define R_AX_USB3_MAC_NPI_POWER_3_V1 0x512C
#define B_AX_R_CNT_SWITCH_USB32_PARA_V1_SH 0
#define B_AX_R_CNT_SWITCH_USB32_PARA_V1_MSK 0xffff
#define R_AX_USB3_MAC_NPI_STATUS_V1 0x5130
#define B_AX_NPI_DEV_CONNECTED_V1 BIT(0)
#define R_AX_USB3_MAC_NPI_DEVICE_NOTIFICATION_V1 0x5134
#define B_AX_DEVNOTE_BIA_V1_SH 16
#define B_AX_DEVNOTE_BIA_V1_MSK 0xffff
#define B_AX_DEVNOTE_BELT_V1_SH 0
#define B_AX_DEVNOTE_BELT_V1_MSK 0xfff
#define R_AX_USB3_MAC_NPI_TRANSMIT_V1 0x5138
#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_V1_SH 0
#define B_AX_NPI_TX_ACK_TP_DATA_WAIT_V1_MSK 0xf
#define R_AX_USB3_MAC_NPI_OTHERS_V1 0x513C
#define B_AX_EN_FIX_RX_ABORT_V1 BIT(8)
#define B_AX_FLADJ_30MHZ_REG_V1_SH 0
#define B_AX_FLADJ_30MHZ_REG_V1_MSK 0x3f
#define R_AX_USB3_WRAP_0_V1 0x5140
#define B_AX_U1TOU2_TIMER_V1_SH 24
#define B_AX_U1TOU2_TIMER_V1_MSK 0xff
#define B_AX_WAKE_ST_DBG_V1_SH 20
#define B_AX_WAKE_ST_DBG_V1_MSK 0xf
#define B_AX_ARB_ST_DBG_V1_SH 18
#define B_AX_ARB_ST_DBG_V1_MSK 0x3
#define B_AX_BIA_REQ_V1 BIT(17)
#define B_AX_BELT_REQ_V1 BIT(16)
#define B_AX_USB3_VENDOR_LEN_TH_V1_SH 0
#define B_AX_USB3_VENDOR_LEN_TH_V1_MSK 0xffff
#define R_AX_USB3_WRAP_1_V1 0x5144
#define B_AX_DIS_PKT_FUNC_WAKE_V1 BIT(0)
#define R_AX_USB3_PHY_V1 0x5148
#define B_AX_USB3_PHY_RWDATA_V1_SH 16
#define B_AX_USB3_PHY_RWDATA_V1_MSK 0xffff
#define B_AX_USB3_PHY_ADR_V1_SH 8
#define B_AX_USB3_PHY_ADR_V1_MSK 0x1f
#define B_AX_USB3_PHY_REG_WRFLAG_V1 BIT(7)
#define B_AX_USB3_PHY_REG_RDFLAG_V1 BIT(6)
#define B_AX_USB3_PHY_REG_ADR_V1_SH 0
#define B_AX_USB3_PHY_REG_ADR_V1_MSK 0x1f
#define R_AX_USB3_OTHERS_V1 0x5150
#define B_AX_R_REATTACH_TIMER_V1_SH 28
#define B_AX_R_REATTACH_TIMER_V1_MSK 0xf
#define B_AX_R_CNT_MS_SEL_V1_SH 24
#define B_AX_R_CNT_MS_SEL_V1_MSK 0x7
#define B_AX_VENDOR_LPM_TEST_V1_SH 16
#define B_AX_VENDOR_LPM_TEST_V1_MSK 0xff
#define B_AX_ISOC_DELAY_VALUE_V1_SH 0
#define B_AX_ISOC_DELAY_VALUE_V1_MSK 0xffff
#define R_AX_USB_APPLICATION_BT_0_V1 0x5160
#define B_AX_BTRX0_BUFFER_WADDR_V1_SH 24
#define B_AX_BTRX0_BUFFER_WADDR_V1_MSK 0xff
#define B_AX_USB_INTOKEN_TIMEOUT_V1_SH 20
#define B_AX_USB_INTOKEN_TIMEOUT_V1_MSK 0x7
#define B_AX_BRX_BUF_CHK_V1_SH 16
#define B_AX_BRX_BUF_CHK_V1_MSK 0x7
#define B_AX_BTRX0_RPKT_SIZE_V1_SH 0
#define B_AX_BTRX0_RPKT_SIZE_V1_MSK 0xffff
#define R_AX_USB_APPLICATION_BT_1_V1 0x5164
#define B_AX_USB2BT_PWR_INFO_REG_MASK_V1_SH 20
#define B_AX_USB2BT_PWR_INFO_REG_MASK_V1_MSK 0xf
#define B_AX_FUNCTION_SUSB_EN_BT_V1 BIT(19)
#define B_AX_LOWPOWER_BT_V1 BIT(18)
#define B_AX_FUNCTION_WAKE_EN_BT_V1 BIT(17)
#define B_AX_FUNCTION_WAKE_CAPABLE_BT_V1 BIT(16)
#define B_AX_BT_ISO_ZERO_EN_V1 BIT(14)
#define B_AX_R_RXDMA_MODE_V1_SH 12
#define B_AX_R_RXDMA_MODE_V1_MSK 0x3
#define B_AX_GPS_USB_ACTIVE_V1 BIT(11)
#define B_AX_BT_TXQ_STOP_V1_SH 8
#define B_AX_BT_TXQ_STOP_V1_MSK 0x7
#define R_AX_USB_APPLICATION_BT_2_V1 0x5168
#define B_AX_BT_TX_V1 BIT(17)
#define B_AX_BT_RX_V1 BIT(16)
#define B_AX_BTTX_FIFO_OVER_EP3_V1 BIT(13)
#define B_AX_BTTX_FIFO_OVER_EP2_V1 BIT(12)
#define B_AX_BTTX_FIFO_OVER_EP0_V1 BIT(11)
#define B_AX_BTRX_FIFO_OVER_EP3_V1 BIT(10)
#define B_AX_BTRX_FIFO_OVER_EP2_V1 BIT(9)
#define B_AX_BTRX_FIFO_OVER_EP1_V1 BIT(8)
#define B_AX_BTTX_FIFO_UNDR_EP3_V1 BIT(5)
#define B_AX_BTTX_FIFO_UNDR_EP2_V1 BIT(4)
#define B_AX_BTTX_FIFO_UNDR_EP0_V1 BIT(3)
#define B_AX_BTRX_FIFO_UNDR_EP3_V1 BIT(2)
#define B_AX_BTRX_FIFO_UNDR_EP2_V1 BIT(1)
#define B_AX_BTRX_FIFO_UNDR_EP1_V1 BIT(0)
#define R_AX_USB_APPLICATION_BT_3_V1 0x516C
#define B_AX_DBG_BTRX_WADDR_V1_SH 16
#define B_AX_DBG_BTRX_WADDR_V1_MSK 0xfff
#define B_AX_DBG_BTRX_RPKT_V1_SH 0
#define B_AX_DBG_BTRX_RPKT_V1_MSK 0xffff
#define R_AX_USB_WLAN0_0_V1 0x5170
#define B_AX_WLAN_INT_LEN_V1_SH 16
#define B_AX_WLAN_INT_LEN_V1_MSK 0xffff
#define B_AX_WLAN0_TXQ_STALL_DIS_V1 BIT(4)
#define B_AX_FUNCTION_SUSB_EN_WLAN0_V1 BIT(3)
#define B_AX_LOWPOWER_WLAN0_V1 BIT(2)
#define B_AX_FUNCTION_WAKE_EN_WLAN0_V1 BIT(1)
#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN0_V1 BIT(0)
#define R_AX_USB_WLAN0_1_V1 0x5174
#define B_AX_USBRX_RST_V1 BIT(9)
#define B_AX_USBTX_RST_V1 BIT(8)
#define B_AX_R_USBRX_SRAM_LS_V1 BIT(7)
#define B_AX_R_USBRX_SRAM_DS_V1 BIT(6)
#define B_AX_R_USBTX_SRAM_LS_V1 BIT(5)
#define B_AX_R_USBTX_SRAM_DS_V1 BIT(4)
#define B_AX_WLRX_FIFO_OVER_V1_SH 2
#define B_AX_WLRX_FIFO_OVER_V1_MSK 0x3
#define B_AX_WLRX_FIFO_UNDR_V1_SH 0
#define B_AX_WLRX_FIFO_UNDR_V1_MSK 0x3
#define R_AX_USB_AUTO_INSTALL_0_V1 0x5180
#define B_AX_AINST_POLL_1_V1 BIT(28)
#define B_AX_AINST_POLL_0_V1 BIT(27)
#define B_AX_AINST_TX1_CLR_BUF_V1 BIT(26)
#define B_AX_AINST_TX0_CLR_BUF_V1 BIT(25)
#define B_AX_WLAN_FW_RDY_V1 BIT(24)
#define B_AX_RECONF_USBEP_V1 BIT(23)
#define B_AX_RECONF_USBEP_EN_V1 BIT(22)
#define B_AX_BULK_ONLY_MASS_STORAGE_RESET_V1 BIT(21)
#define B_AX_BULK_ONLY_MASS_STORAGE_RESET_EN_V1 BIT(20)
#define B_AX_AINST_RXLEN_V1_SH 8
#define B_AX_AINST_RXLEN_V1_MSK 0xfff
#define B_AX_AINST_RX1_INTR_V1 BIT(7)
#define B_AX_AINST_RX0_INTR_V1 BIT(6)
#define B_AX_AINXT_TX1_INTR_V1 BIT(5)
#define B_AX_AINST_TX0_INTR_V1 BIT(4)
#define B_AX_AUTO_INST_TXQ_STALL_DIS_V1 BIT(3)
#define B_AX_LOWPOWER_AINST_V1 BIT(2)
#define B_AX_FUNCTION_WANE_EN_AINST_V1 BIT(1)
#define R_AX_USB_AUTO_INSTALL_1_V1 0x5184
#define B_AX_AINST_TX1LEN_V1_SH 16
#define B_AX_AINST_TX1LEN_V1_MSK 0xfff
#define B_AX_AINST_TX0LEN_V1_SH 0
#define B_AX_AINST_TX0LEN_V1_MSK 0xfff
#define R_AX_USB_AUTO_INSTALL_2_V1 0x5188
#define B_AX_AINST_PID_V1_SH 16
#define B_AX_AINST_PID_V1_MSK 0xffff
#define B_AX_AINST_VID_V1_SH 0
#define B_AX_AINST_VID_V1_MSK 0xffff
#define R_AX_USB_AUTO_INSTALL_3_V1 0x518C
#define B_AX_AINST_TXSTATUS_V1_SH 8
#define B_AX_AINST_TXSTATUS_V1_MSK 0xff
#define B_AX_AINST_RXSTATUS_V1_SH 0
#define B_AX_AINST_RXSTATUS_V1_MSK 0xff
#define R_AX_USB_BRIDGE_UART_0_V1 0x5190
#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_V1_SH 20
#define B_AX_BRIDGE_XFACTOR_ADJ_USB2_V1_MSK 0xfff
#define B_AX_BRIDGE_XFACTOR_V1_SH 16
#define B_AX_BRIDGE_XFACTOR_V1_MSK 0xf
#define B_AX_BRIDGE_BAUD_USB2_V1_SH 0
#define B_AX_BRIDGE_BAUD_USB2_V1_MSK 0xfff
#define R_AX_USB_BRIDGE_UART_1_V1 0x5194
#define B_AX_BRIDGE_WAKEUP_EN_V1_SH 30
#define B_AX_BRIDGE_WAKEUP_EN_V1_MSK 0x3
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_V1_SH 16
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_LOWERBOUND_V1_MSK 0xfff
#define B_AX_BRIDGE_LE_CON_HAN_VLD_V1 BIT(9)
#define B_AX_BRIDGE_LE_ON_V1 BIT(8)
#define B_AX_BRIDGE_DEBUG_PKTCNT_EN_V1 BIT(6)
#define B_AX_BRIDGE_RESET_RCV_SEL_V1 BIT(5)
#define B_AX_BRIDGE_WLS0_V1 BIT(4)
#define B_AX_BRIDGE_STB_V1 BIT(3)
#define B_AX_BRIDGE_PEN_V1 BIT(2)
#define B_AX_BRIDGE_EPS_V1 BIT(1)
#define B_AX_BRIDGE_STKP_V1 BIT(0)
#define R_AX_USB_BRIDGE_UART_2_V1 0x5198
#define B_AX_BRIDGE_DEBUG_SEL_V1_SH 24
#define B_AX_BRIDGE_DEBUG_SEL_V1_MSK 0xff
#define B_AX_R_BRIDGE_UARTEN_V1 BIT(23)
#define B_AX_BRIDGE_LPM_EN_V1 BIT(22)
#define B_AX_BRIDGE_TXSCO_TIME_INTERVAL_EN_V1 BIT(21)
#define B_AX_BRIDGE_TXSCO_PKT_LEN_MAT_EN_V1 BIT(20)
#define B_AX_BRIDGE_TXSCO_CON_HAN_MAT_EN_V1 BIT(19)
#define B_AX_BRIDGE_USB_TX_HCICMDLEN_SEL_V1 BIT(18)
#define B_AX_R_BRIDGE_JCIRXEN_V1 BIT(17)
#define B_AX_R_BRIDGE_HCITXEN_V1 BIT(16)
#define B_AX_BRIDGE_RXSCOBUF_FLOW_SEL_V1_SH 12
#define B_AX_BRIDGE_RXSCOBUF_FLOW_SEL_V1_MSK 0xf
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_V1_SH 0
#define B_AX_BRIDGE_LE_CON_HAN_VALUE_UPPERBOUND_V1_MSK 0xfff
#define R_AX_USB_BRIDGE_UART_3_V1 0x519C
#define B_AX_BRIDGE_URT_RXINDIC_ERR_V1 BIT(31)
#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_V1_SH 24
#define B_AX_BRIDGE_LE_SHORTPKTERR_CNT_V1_MSK 0x7f
#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_V1_SH 16
#define B_AX_BRIDGE_ACL_SHORTPKTERR_CNT_V1_MSK 0xff
#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_V1_SH 8
#define B_AX_BRIDGE_LE_LONGPKTERR_CNT_V1_MSK 0xff
#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_V1_SH 0
#define B_AX_BRIDGE_ACL_LONGPKTERR_CNT_V1_MSK 0xff
#define R_AX_USB_BRIDGE_UART_4_V1 0x51A0
#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_V1_SH 20
#define B_AX_BRIDGE_XFACTOR_ADJ_USB3_V1_MSK 0xfff
#define B_AX_BRIDGE_XFACTOR_USB3_V1_SH 16
#define B_AX_BRIDGE_XFACTOR_USB3_V1_MSK 0xf
#define B_AX_BRIDGE_BAUD_USB3_V1_SH 0
#define B_AX_BRIDGE_BAUD_USB3_V1_MSK 0xfff
#define R_AX_USB_BT_BRIDGE_V1 0x51A8
#define B_AX_R_DIS_BTBRI_SS_SYSON_V1 BIT(2)
#define B_AX_R_DIS_BTBRI_SS_STS_V1 BIT(1)
#define B_AX_R_DIS_BTBRI_L1U2_STS_V1 BIT(0)
#define R_AX_USB_DMA_WRAPPER_V1 0x51B0
#define B_AX_PKT_BASE_EN_V1 BIT(11)
#define B_AX_FUNCTION_SUSB_OPT_V1 BIT(8)
#define B_AX_TX7LEN_MISMATCH_V1 BIT(7)
#define B_AX_TX6LEN_MISMATCH_V1 BIT(6)
#define B_AX_TX5LEN_MISMATCH_V1 BIT(5)
#define B_AX_TX4LEN_MISMATCH_V1 BIT(4)
#define B_AX_TX3LEN_MISMATCH_V1 BIT(3)
#define B_AX_TX2LEN_MISMATCH_V1 BIT(2)
#define B_AX_TX1LEN_MISMATCH_V1 BIT(1)
#define B_AX_TX0LEN_MISMATCH_V1 BIT(0)
#define R_AX_USB_WLAN1_V1 0x51B8
#define B_AX_WLAN_TX_V1 BIT(12)
#define B_AX_WLAN_RX_V1 BIT(11)
#define B_AX_WLAN1_TXQ_STALL_DIS_V1 BIT(10)
#define B_AX_WLAN1_RXQ_STOP_V1_SH 8
#define B_AX_WLAN1_RXQ_STOP_V1_MSK 0x3
#define B_AX_WLAN1_TXQ_STOP_V1_SH 4
#define B_AX_WLAN1_TXQ_STOP_V1_MSK 0xf
#define B_AX_FUNCTION_SUSB_EN_WLAN1_V1 BIT(3)
#define B_AX_LOWPOWER_WLAN1_V1 BIT(2)
#define B_AX_FUNCTION_WAKE_EN_WLAN1_V1 BIT(1)
#define B_AX_FUNCTION_WAKE_CAPABLE_WLAN1_V1 BIT(0)
#define R_AX_USB_GPS_V1 0x51C0
#define B_AX_FUNCTION_SUSB_EN_GPS_V1 BIT(3)
#define B_AX_LOWPOWER_GPS_V1 BIT(2)
#define B_AX_FUNCTION_WAKE_EN_GPS_V1 BIT(1)
#define B_AX_FUNCTION_WAKE_CAPABLE_GPS_V1 BIT(0)
#define R_AX_USB_DEBUG_0_V1 0x51D0
#define B_AX_SLEEP_GNT_BT_V1 BIT(17)
#define B_AX_SLEEP_REQ_BT_V1 BIT(16)
#define B_AX_DEBUG_SIGNAL_001_V1_SH 8
#define B_AX_DEBUG_SIGNAL_001_V1_MSK 0xff
#define B_AX_USB_DBGO_SEL_V1_SH 0
#define B_AX_USB_DBGO_SEL_V1_MSK 0xff
#define R_AX_USB_DEBUG_1_V1 0x51D4
#define B_AX_EP7_COUNTER_V1_SH 28
#define B_AX_EP7_COUNTER_V1_MSK 0xf
#define B_AX_EP6_COUNTER_V1_SH 24
#define B_AX_EP6_COUNTER_V1_MSK 0xf
#define B_AX_EP5_COUNTER_V1_SH 20
#define B_AX_EP5_COUNTER_V1_MSK 0xf
#define B_AX_EP4_COUNTER_V1_SH 16
#define B_AX_EP4_COUNTER_V1_MSK 0xf
#define B_AX_EP3_COUNTER_V1_SH 12
#define B_AX_EP3_COUNTER_V1_MSK 0xf
#define B_AX_EP2_COUNTER_V1_SH 8
#define B_AX_EP2_COUNTER_V1_MSK 0xf
#define B_AX_EP1_COUNTER_V1_SH 4
#define B_AX_EP1_COUNTER_V1_MSK 0xf
#define B_AX_EP0_COUNTER_V1_SH 0
#define B_AX_EP0_COUNTER_V1_MSK 0xf
#define R_AX_USB_DEBUG_2_V1 0x51D8
#define B_AX_EP15_COUNTER_V1_SH 28
#define B_AX_EP15_COUNTER_V1_MSK 0xf
#define B_AX_EP14_COUNTER_V1_SH 24
#define B_AX_EP14_COUNTER_V1_MSK 0xf
#define B_AX_EP13_COUNTER_V1_SH 20
#define B_AX_EP13_COUNTER_V1_MSK 0xf
#define B_AX_EP12_COUNTER_V1_SH 16
#define B_AX_EP12_COUNTER_V1_MSK 0xf
#define B_AX_EP11_COUNTER_V1_SH 12
#define B_AX_EP11_COUNTER_V1_MSK 0xf
#define B_AX_EP10_COUNTER_V1_SH 8
#define B_AX_EP10_COUNTER_V1_MSK 0xf
#define B_AX_EP9_COUNTER_V1_SH 4
#define B_AX_EP9_COUNTER_V1_MSK 0xf
#define B_AX_EP8_COUNTER_V1_SH 0
#define B_AX_EP8_COUNTER_V1_MSK 0xf
#define R_AX_USB_DEBUG_3_V1 0x51DC
#define B_AX_RX_STATE_MACHINE_V1_SH 24
#define B_AX_RX_STATE_MACHINE_V1_MSK 0xff
#define B_AX_TX_STATE_MACHINE_V1_SH 16
#define B_AX_TX_STATE_MACHINE_V1_MSK 0xff
#define B_AX_IO_STATE_MACHINE_V1_SH 8
#define B_AX_IO_STATE_MACHINE_V1_MSK 0xff
#define B_AX_REG_WRITE_COUNTER_V1_SH 4
#define B_AX_REG_WRITE_COUNTER_V1_MSK 0xf
#define B_AX_REG_READ_COUNTER_V1_SH 0
#define B_AX_REG_READ_COUNTER_V1_MSK 0xf
#define R_AX_USB_DEBUG_4_V1 0x51E0
#define B_AX_EP15_CNT_DIRECT_V1 BIT(31)
#define B_AX_EP14_CNT_DIRECT_V1 BIT(30)
#define B_AX_EP13_CNT_DIRECT_V1 BIT(29)
#define B_AX_EP12_CNT_DIRECT_V1 BIT(28)
#define B_AX_EP11_CNT_DIRECT_V1 BIT(27)
#define B_AX_EP10_CNT_DIRECT_V1 BIT(26)
#define B_AX_EP9_CNT_DIRECT_V1 BIT(25)
#define B_AX_EP8_CNT_DIRECT_V1 BIT(24)
#define B_AX_EP7_CNT_DIRECT_V1 BIT(23)
#define B_AX_EP6_CNT_DIRECT_V1 BIT(22)
#define B_AX_EP5_CNT_DIRECT_V1 BIT(21)
#define B_AX_EP4_CNT_DIRECT_V1 BIT(20)
#define B_AX_EP3_CNT_DIRECT_V1 BIT(19)
#define B_AX_EP2_CNT_DIRECT_V1 BIT(18)
#define B_AX_EP1_CNT_DIRECT_V1 BIT(17)
#define B_AX_EP0_CNT_DIRECT_V1 BIT(16)
#define B_AX_HW_TXVLD_TOGGLE_EN_V1 BIT(15)
#define B_AX_HW_FORCE_TXRDY_EN_V1 BIT(14)
#define B_AX_TXVLD_TOGGLE_VAL_V1_SH 8
#define B_AX_TXVLD_TOGGLE_VAL_V1_MSK 0xf
#define B_AX_TXVLD_TOUT_VAL_V1_SH 0
#define B_AX_TXVLD_TOUT_VAL_V1_MSK 0xff
#define R_AX_USB_DEBUG_5_V1 0x51E4
#define B_AX_ON_IOH_ADDR_V1_SH 8
#define B_AX_ON_IOH_ADDR_V1_MSK 0xffffff
#define B_AX_ON_IOH_TIMER_V1_SH 4
#define B_AX_ON_IOH_TIMER_V1_MSK 0xf
#define B_AX_ON_IOH_EMPTY_V1 BIT(2)
#define B_AX_ON_IOH_FLAG_V1 BIT(1)
#define B_AX_ON_IOH_EN_V1 BIT(0)
#define R_AX_USB_DEBUG_6_V1 0x51E8
#define B_AX_OFF_IOH_ADDR_V1_SH 8
#define B_AX_OFF_IOH_ADDR_V1_MSK 0xffffff
#define B_AX_OFF_IOH_TIMER_V1_SH 4
#define B_AX_OFF_IOH_TIMER_V1_MSK 0xf
#define B_AX_OFF_IOH_FLAG_V1 BIT(1)
#define B_AX_OFF_IOH_EN_V1 BIT(0)
#define R_AX_USB_STATUS_V1 0x51F0
#define B_AX_USB_EP_NUM_V1_SH 4
#define B_AX_USB_EP_NUM_V1_MSK 0xf
#define B_AX_R_SSIC_EN_V1 BIT(2)
#define B_AX_R_USB2_SEL_V1 BIT(1)
#define B_AX_MODE_HS_V1 BIT(0)
#define R_AX_USB_D2F_F2D_INFO_V1 0x5200
#define B_AX_HRPWM2_V1_SH 16
#define B_AX_HRPWM2_V1_MSK 0xffff
#define B_AX_CPWM2_V1_SH 0
#define B_AX_CPWM2_V1_MSK 0xffff
#define R_AX_USB3_V1 0x5220
#define B_AX_U3_STATE_V1_SH 12
#define B_AX_U3_STATE_V1_MSK 0xf
#define B_AX_U3_SUB_STATE_V1_SH 8
#define B_AX_U3_SUB_STATE_V1_MSK 0xf
#define B_AX_HPS_CLKR_USB_V1_SH 0
#define B_AX_HPS_CLKR_USB_V1_MSK 0xff
#define R_AX_USB_OTHERS_0_V1 0x5230
#define B_AX_USBTX_EP3IF_OK_CNT_V1_SH 24
#define B_AX_USBTX_EP3IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP2IF_OK_CNT_V1_SH 16
#define B_AX_USBTX_EP2IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP1IF_OK_CNT_V1_SH 8
#define B_AX_USBTX_EP1IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP0IF_OK_CNT_V1_SH 0
#define B_AX_USBTX_EP0IF_OK_CNT_V1_MSK 0xff
#define R_AX_USB_OTHERS_1_V1 0x5234
#define B_AX_USBTX_EP7IF_OK_CNT_V1_SH 24
#define B_AX_USBTX_EP7IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP6IF_OK_CNT_V1_SH 16
#define B_AX_USBTX_EP6IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP5IF_OK_CNT_V1_SH 8
#define B_AX_USBTX_EP5IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP4IF_OK_CNT_V1_SH 0
#define B_AX_USBTX_EP4IF_OK_CNT_V1_MSK 0xff
#define R_AX_USB_OTHERS_2_V1 0x5238
#define B_AX_USBRX_DMAIF_OK_CNT_V1_SH 24
#define B_AX_USBRX_DMAIF_OK_CNT_V1_MSK 0xff
#define B_AX_USBRX_EPIF_OK_CNT_V1_SH 16
#define B_AX_USBRX_EPIF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP9IF_OK_CNT_V1_SH 8
#define B_AX_USBTX_EP9IF_OK_CNT_V1_MSK 0xff
#define B_AX_USBTX_EP8IF_OK_CNT_V1_SH 0
#define B_AX_USBTX_EP8IF_OK_CNT_V1_MSK 0xff
#define R_AX_USB_OTHERS_3_V1 0x523C
#define B_AX_VENDOR_LMP_LATCH_DATA_L_V1_SH 0
#define B_AX_VENDOR_LMP_LATCH_DATA_L_V1_MSK 0xffffffffL
#define R_AX_USB_OTHERS_4_V1 0x5240
#define B_AX_VENDOR_LMP_LATCH_DATA_H_V1_SH 0
#define B_AX_VENDOR_LMP_LATCH_DATA_H_V1_MSK 0xffffffffL
#define R_AX_USB_OTHERS_5_V1 0x5244
#define B_AX_APPEND_ZERO_PKT_V1_SH 24
#define B_AX_APPEND_ZERO_PKT_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_EXTE_7_V1_SH 21
#define B_AX_USB_AUTO_LOAD_EXTE_7_V1_MSK 0x3
#define B_AX_USB_AUTO_LOAD_EXTE_0_V1_SH 16
#define B_AX_USB_AUTO_LOAD_EXTE_0_V1_MSK 0x1f
#define B_AX_USB_AUTO_LOAD_EXTE_2_V1_SH 8
#define B_AX_USB_AUTO_LOAD_EXTE_2_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_EXTE_1_V1_SH 0
#define B_AX_USB_AUTO_LOAD_EXTE_1_V1_MSK 0xff
#define R_AX_USB_OTHERS_6_V1 0x5248
#define B_AX_USB_AUTO_LOAD_STRING_3_V1_SH 24
#define B_AX_USB_AUTO_LOAD_STRING_3_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_2_V1_SH 16
#define B_AX_USB_AUTO_LOAD_STRING_2_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_1_V1_SH 8
#define B_AX_USB_AUTO_LOAD_STRING_1_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_0_V1_SH 0
#define B_AX_USB_AUTO_LOAD_STRING_0_V1_MSK 0xff
#define R_AX_USB_OTHERS_7_V1 0x524C
#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_V1_SH 22
#define B_AX_USB_AUTO_LOAD_BRIDGE_FLAG_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_V1_SH 14
#define B_AX_USB_AUTO_LOAD_EXTE_FLAG_V1_MSK 0xff
#define B_AX_USB_AUTO_LOAD_STRING_FLAG_V1 BIT(13)
#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_V1_SH 7
#define B_AX_USB_AUTO_LOAD_INIT2_FLAG_V1_MSK 0x3f
#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_V1_SH 0
#define B_AX_USB_AUTO_LOAD_INIT1_FLAG_V1_MSK 0x7f
#define R_AX_USB_WATCHDOG_V1 0x5260
#define B_AX_USBIO_WD_FLAG_V1 BIT(31)
#define B_AX_USBIO_WD_EN_V1 BIT(30)
#define B_AX_USBIO_WD_TIMER_V1_SH 24
#define B_AX_USBIO_WD_TIMER_V1_MSK 0xf
#define B_AX_USBIO_WD_ADDR_V1_SH 0
#define B_AX_USBIO_WD_ADDR_V1_MSK 0xffffff
#define R_AX_HUSBIMR_V1 0x5270
#define B_AX_USB_CPUIO_TIMEOUT_INT_EN_V1 BIT(29)
#define B_AX_USB_HC1ISR_IDCT_INT_EN_V1 BIT(28)
#define B_AX_USB_HC0ISR_IDCT_INT_EN_V1 BIT(27)
#define B_AX_USB_HD1ISR_IDCT_INT_EN_V1 BIT(26)
#define B_AX_USB_HD0ISR_IDCT_INT_EN_V1 BIT(25)
#define B_AX_USB_HS1ISR_IDCT_INT_EN_V1 BIT(24)
#define B_AX_USB_HS0ISR_IDCT_INT_EN_V1 BIT(23)
#define B_AX_USB_TX_CH12_INT_EN_V1 BIT(7)
#define B_AX_USB_TX_CH10_INT_EN_V1 BIT(6)
#define B_AX_USB_TX_CH8_INT_EN_V1 BIT(5)
#define B_AX_USB_TX_CH6_INT_EN_V1 BIT(4)
#define B_AX_USB_TX_CH4_INT_EN_V1 BIT(3)
#define B_AX_USB_TX_CH2_INT_EN_V1 BIT(2)
#define B_AX_USB_TX_CH0_INT_EN_V1 BIT(1)
#define B_AX_USB_RX_INT_EN_V1 BIT(0)
#define R_AX_HUSBISR_V1 0x5274
#define B_AX_USB_CPUIO_TIMEOUT_INT_V1 BIT(29)
#define B_AX_USB_HC1ISR_IDCT_INT_V1 BIT(28)
#define B_AX_USB_HC0ISR_IDCT_INT_V1 BIT(27)
#define B_AX_USB_HD1ISR_IDCT_INT_V1 BIT(26)
#define B_AX_USB_HD0ISR_IDCT_INT_V1 BIT(25)
#define B_AX_USB_HS1ISR_IDCT_INT_V1 BIT(24)
#define B_AX_USB_HS0ISR_IDCT_INT_V1 BIT(23)
#define B_AX_USB_TX_CH12_INT_V1 BIT(7)
#define B_AX_USB_TX_CH10_INT_V1 BIT(6)
#define B_AX_USB_TX_CH8_INT_V1 BIT(5)
#define B_AX_USB_TX_CH6_INT_V1 BIT(4)
#define B_AX_USB_TX_CH4_INT_V1 BIT(3)
#define B_AX_USB_TX_CH2_INT_V1 BIT(2)
#define B_AX_USB_TX_CH0_INT_V1 BIT(1)
#define B_AX_USB_RX_INT_V1 BIT(0)
//
// WL_AX_Reg_WLCPU_Local.xls
//
//
// WLCPU_Local_Reg
//
#define R_AX_MAILBOX_WIFI2BT_DATA_L 0x0000
#define B_AX_MBOX_WIFI2BT_DATA_L_SH 0
#define B_AX_MBOX_WIFI2BT_DATA_L_MSK 0xffffffffL
#define R_AX_MAILBOX_WIFI2BT_DATA_H 0x0004
#define B_AX_MBOX_WIFI2BT_DATA_H_SH 0
#define B_AX_MBOX_WIFI2BT_DATA_H_MSK 0xffffffffL
#define R_AX_MAILBOX_WIFI2BT_READY 0x0008
#define B_AX_MBOX_OUT_ABORT BIT(7)
#define B_AX_MBOX_ACK_WIFI2BT BIT(0)
#define R_AX_MAILBOX_BT2WIFI_DATA_L 0x0010
#define B_AX_MBOX_BT2WIFI_DATA_L_SH 0
#define B_AX_MBOX_BT2WIFI_DATA_L_MSK 0xffffffffL
#define R_AX_MAILBOX_BT2WIFI_DATA_H 0x0014
#define B_AX_MBOX_BT2WIFI_DATA_H_SH 0
#define B_AX_MBOX_BT2WIFI_DATA_H_MSK 0xffffffffL
#define R_AX_MAILBOX_CTRL 0x0018
#define B_AX_I2C_MAILBOX_EN BIT(31)
#define R_AX_EXC_JUMP_ADDR 0x0020
#define B_AX_WLCPU_EXC_JUMP_ADDR_SH 0
#define B_AX_WLCPU_EXC_JUMP_ADDR_MSK 0xffffffffL
#define R_AX_CPU_BOOT_ADDR 0x0024
#define B_AX_WLCPU_BOOT_ADDR_SH 0
#define B_AX_WLCPU_BOOT_ADDR_MSK 0xffffffffL
#define R_AX_CPU_IDMEM_TO_CNT 0x0030
#define B_AX_CPU_DMEM_TO_CNT_TH_SH 16
#define B_AX_CPU_DMEM_TO_CNT_TH_MSK 0xffff
#define B_AX_CPU_IMEM_TO_CNT_TH_SH 0
#define B_AX_CPU_IMEM_TO_CNT_TH_MSK 0xffff
#define R_AX_WDT_CTRL 0x0040
#define B_AX_WDT_EN BIT(31)
#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
#define B_AX_WDT_CLR BIT(16)
#define B_AX_WDT_COUNT_SH 0
#define B_AX_WDT_COUNT_MSK 0xffff
#define B_AX_WDT_CTRL_ALL_DIS 0
#define R_AX_WDT_STATUS 0x0044
#define B_AX_FS_WDT_INT BIT(8)
#define B_AX_FS_WDT_INT_MSK BIT(0)
#define R_AX_WDT_CDC 0x0048
#define B_AX_WDT_CDC_SH 0
#define B_AX_WDT_CDC_MSK 0xffff
#define R_AX_INT1_CTRL_IND 0x0050
#define B_AX_FWC_INT_IND_SH 0
#define B_AX_FWC_INT_IND_MSK 0xfffff
#define R_AX_INT2_CTRL_IND 0x0054
#define B_AX_FWD_INT_IND_SH 0
#define B_AX_FWD_INT_IND_MSK 0x7
#define R_AX_INT3_CTRL_IND 0x0058
#define B_AX_FWS_INT_IND BIT(0)
#define R_AX_INT4_CTRL_IND 0x005C
#define B_AX_FWDA_INT_IND_SH 0
#define B_AX_FWDA_INT_IND_MSK 0x7
#define R_AX_INT5_CTRL_IND 0x0060
#define B_AX_SUB_SYS_ERR_IND_SH 29
#define B_AX_SUB_SYS_ERR_IND_MSK 0x7
#define B_AX_FWP_INT_IND_SH 0
#define B_AX_FWP_INT_IND_MSK 0x7
#define R_AX_USB_CTRL 0x0080
#define B_AX_USB2_SUSB_STS BIT(7)
#define B_AX_USB3_SUSB_STS BIT(6)
#define B_AX_ALLOW_WAKE_HOST BIT(5)
#define B_AX_WLCPU_WAKE_USB BIT(4)
#define B_AX_PD_REGU_L BIT(16)
#define B_AX_XTAL_OFF_A_DIE BIT(22)
#define B_AX_R_SYM_ISO_DMEM62PP BIT(29)
#define B_AX_R_SYM_ISO_DMEM52PP BIT(28)
#define B_AX_R_SYM_ISO_DMEM42PP BIT(27)
#define B_AX_R_SYM_ISO_DMEM32PP_V1 BIT(26)
#define B_AX_R_SYM_ISO_DMEM22PP_V1 BIT(25)
#define B_AX_R_SYM_ISO_DMEM12PP_V1 BIT(24)
#define R_AX_SDIO_HRPWM1_V1 0x4080
#define R_AX_FWD1ISR_V1 0x7804
#define R_AX_PCIE_HRPWM_V1 0x30C0
#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
#define R_AX_SPSLDO_ON_CTRL0 0x0200
#define B_AX_PFMCMP_IQ BIT(31)
#define B_AX_OFF_END_SEL BIT(29)
#define B_AX_POW_MINOFF_L BIT(28)
#define B_AX_COT_I_L_SH 26
#define B_AX_COT_I_L_MSK 0x3
#define B_AX_VREFPFM_L_SH 22
#define B_AX_VREFPFM_L_MSK 0xf
#define B_AX_FORCE_ZCD_BIAS BIT(21)
#define B_AX_ZCD_SDZ_L_SH 19
#define B_AX_ZCD_SDZ_L_MSK 0x3
#define B_AX_REG_ZCDC_H_SH 17
#define B_AX_REG_ZCDC_H_MSK 0x3
#define B_AX_POW_ZCD_L BIT(16)
#define B_AX_OCP_L1_SH 13
#define B_AX_OCP_L1_MSK 0x7
#define B_AX_POWOCP_L1 BIT(12)
#define B_AX_SAW_FREQ_L_SH 8
#define B_AX_SAW_FREQ_L_MSK 0xf
#define B_AX_REG_BYPASS_L BIT(7)
#define B_AX_FPWM_L1 BIT(6)
#define B_AX_STD_L1_SH 4
#define B_AX_STD_L1_MSK 0x3
#define B_AX_VOL_L1_SH 0
#define B_AX_VOL_L1_MSK 0xf
#define R_AX_SPS_DIG_ON_CTRL0 0x0200
#define B_AX_REG_BG_H BIT(30)
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_reg.h
|
C
|
agpl-3.0
| 615,737
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __HALMAC_PCIE_REG_H__
#define __HALMAC_PCIE_REG_H__
/* PCIE PHY register */
#define RAC_CTRL_PPR 0x00
#define RAC_ANA10 0x10
#define RAC_ANA19 0x19
#define RAC_REG_REV2 0x1B
#define RAC_REG_FLD_0 0x1D
#define RAC_ANA1F 0x1F
#define RAC_SET_PPR 0x20
#define RAC_TRG_PPR 0x21
#define RAC_ANA24 0x24
#define RAC_ANA26 0x26
#define RAC_CTRL_PPR_V1 0x30
#define RAC_SET_PPR_V1 0x31
/* PCIE CFG register */
#define PCIE_L1_STS 0x80
#define PCIE_PHY_RATE 0x82
#define PCIE_L1SS_CTRL 0x718
#define PCIE_L1_CTRL 0x719
#define PCIE_ACK_NFTS 0x70D
#define PCIE_COM_CLK_NFTS 0x70E
#define PCIE_FTS 0x80C
#define PCIE_ASPM_CTRL 0x70F
#define PCIE_CLK_CTRL 0x725
#define CFG_RST_MSTATE 0xB48
#define PCIE_L1SS_CAP 0x160
#define PCIE_L1SS_SUP 0x164
#define PCIE_L1SS_STS 0x168
/* PCIE CFG bit */
#define PCIE_BIT_STS_L0S BIT(0)
#define PCIE_BIT_STS_L1 BIT(1)
#define PCIE_BIT_WAKE BIT(2)
#define PCIE_BIT_L1 BIT(3)
#define PCIE_BIT_CLK BIT(4)
#define PCIE_BIT_L0S BIT(7)
#define PCIE_BIT_L1SS BIT(5)
#define PCIE_BIT_L1SSSUP BIT(4)
/* PCIE ASPM mask*/
#define SHFT_L1DLY 3
#define SHFT_L0SDLY 0
#define PCIE_ASPMDLY_MASK 0x07
#define PCIE_L1SS_MASK 0x0F
/* PCIE Capability */
#define PCIE_L1SS_ID 0x001E
/* PCIE MAC register */
#define LINK_CTRL2_REG_OFFSET 0xA0
#define GEN2_CTRL_OFFSET 0x80C
#define LINK_STATUS_REG_OFFSET 0x82
#define PCIE_GEN1_SPEED 0x01
#define PCIE_GEN2_SPEED 0x02
#endif/* __HALMAC_PCIE_REG_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/pcie_reg.h
|
C
|
agpl-3.0
| 2,194
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PLTFM_H_
#define _MAC_AX_PLTFM_H_
#ifndef __cplusplus /* for win/linux driver */
/* Include header file which contain the following definitions, */
/* or modify this file to meet your platform */
/*[Driver] use their own header files*/
#include "../hal_headers_le.h"
/*[Driver] provide the define of NULL, u8, u16, u32*/
#ifndef NULL
#define NULL ((void *)0)
#endif
/*[Driver] provide the type mutex*/
/* Mutex type */
#define mac_ax_mutex _os_mutex
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
#define _ASSERT_ BUG_ON
/* 1: enable MAC debug messages */
/* 0: disable MAC debug messages */
#define MAC_AX_DBG_MSG_EN 1
/* Set debug message level */
#define MAC_AX_MSG_LEVEL_TRACE 3
#define MAC_AX_MSG_LEVEL_WARNING 2
#define MAC_AX_MSG_LEVEL_ERR 1
#define MAC_AX_MSG_LEVEL_ALWAYS 0
#define MAC_AX_MSG_LEVEL MAC_AX_MSG_LEVEL_TRACE
#define SET_CLR_WORD(_w, _v, _f) \
(((_w) & ~((_f##_MSK) << (_f##_SH))) | \
(((_v) & (_f##_MSK)) << (_f##_SH)))
#define SET_WORD(_v, _f) (((_v) & (_f##_MSK)) << (_f##_SH))
#define GET_FIELD(_w, _f) (((_w) >> (_f##_SH)) & (_f##_MSK))
#define SET_CLR_WOR2(_w, _v, _sh, _msk) (((_w) & ~(_msk << _sh)) | \
(((_v) & _msk) << _sh))
#define SET_WOR2(_v, _sh, _msk) (((_v) & _msk) << _sh)
#define GET_FIEL2(_w, _sh, _msk) (((_w) >> _sh) & _msk)
#define GET_MSK(_f) ((_f##_MSK) << (_f##_SH))
#else /* for WD1 test program */
/* Include header file which contain the following definitions, */
/* or modify this file to meet your platform */
#include <Windows.h> // critical_section
#include <stdint.h>
#define BIT(x) (1 << (x))
#ifndef NULL
#define NULL ((void *)0)
#endif
typedef unsigned char u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef char s8;
typedef int16_t s16;
typedef int32_t s32;
#include "../hal_headers_le.h"
typedef u16 __le16;
typedef u32 __le32;
typedef u16 __be16;
typedef u32 __be32;
typedef CRITICAL_SECTION mac_ax_mutex;
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
/* 1: the platform is Little Endian. */
/* 0: the platform is Big Endian. */
#define MAC_AX_IS_LITTLE_ENDIAN 1
/* 1: enable MAC debug messages */
/* 0: disable MAC debug messages */
#define MAC_AX_DBG_MSG_EN 1
/* Set debug message level */
#define MAC_AX_MSG_LEVEL_TRACE 3
#define MAC_AX_MSG_LEVEL_WARNING 2
#define MAC_AX_MSG_LEVEL_ERR 1
#define MAC_AX_MSG_LEVEL_ALWAYS 0
#define MAC_AX_MSG_LEVEL MAC_AX_MSG_LEVEL_TRACE
#define SET_CLR_WORD(_w, _v, _f) \
(((_w) & ~((_f##_MSK) << (_f##_SH))) | \
(((_v) & (_f##_MSK)) << (_f##_SH)))
#define SET_WORD(_v, _f) (((_v) & (_f##_MSK)) << (_f##_SH))
#define GET_FIELD(_w, _f) (((_w) >> (_f##_SH)) & (_f##_MSK))
#define SET_CLR_WOR2(_w, _v, _sh, _msk) (((_w) & ~(_msk << _sh)) | \
(((_v) & _msk) << _sh))
#define SET_WOR2(_v, _sh, _msk) (((_v) & _msk) << _sh)
#define GET_FIEL2(_w, _sh, _msk) (((_w) >> _sh) & _msk)
#define GET_MSK(_f) ((_f##_MSK) << (_f##_SH))
#define SWAP32(x) \
((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \
(((u32)(x) & (u32)0x0000ff00) << 8) | \
(((u32)(x) & (u32)0x00ff0000) >> 8) | \
(((u32)(x) & (u32)0xff000000) >> 24)))
#define SWAP16(x) \
((u16)((((u16)(x) & (u16)0x00ff) << 8) | \
(((u16)(x) & (u16)0xff00) >> 8)))
#if MAC_AX_IS_LITTLE_ENDIAN
#define cpu_to_le32(x) ((u32)(x))
#define le32_to_cpu(x) ((u32)(x))
#define cpu_to_le16(x) ((u16)(x))
#define le16_to_cpu(x) ((u16)(x))
#define cpu_to_be32(x) SWAP32((x))
#define be32_to_cpu(x) SWAP32((x))
#define cpu_to_be16(x) SWAP16((x))
#define be16_to_cpu(x) SWAP16((x))
#else
#define cpu_to_le32(x) SWAP32((x))
#define le32_to_cpu(x) SWAP32((x))
#define cpu_to_le16(x) SWAP16((x))
#define le16_to_cpu(x) SWAP16((x))
#define cpu_to_be32(x) ((u32)(x))
#define be32_to_cpu(x) ((u32)(x))
#define cpu_to_be16(x) ((u16)(x))
#define be16_to_cpu(x) ((u16)(x))
#endif
#ifndef __func__
#define __func__ __FUNCTION__
#endif
#endif // end of #else /* for WD1 test program */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/pltfm_cfg.h
|
C
|
agpl-3.0
| 5,296
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PLTFM_H_
#define _MAC_AX_PLTFM_H_
/* Include header file which contain the following definitions, */
/* or modify this file to meet your platform */
/*[Driver] use their own header files*/
#include "../hal_headers_le.h"
/*[Driver] provide the define of NULL, u8, u16, u32*/
#ifndef NULL
#define NULL ((void *)0)
#endif
/*[Driver] provide the type mutex*/
/* Mutex type */
#define mac_ax_mutex _os_mutex
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
#define _ASSERT_ BUG_ON
typedef u16 __le16;
typedef u32 __le32;
typedef u16 __be16;
typedef u32 __be32;
/* 1: enable MAC debug messages */
/* 0: disable MAC debug messages */
#define MAC_AX_DBG_MSG_EN 1
/* Set debug message level */
#define MAC_AX_MSG_LEVEL_TRACE 3
#define MAC_AX_MSG_LEVEL_WARNING 2
#define MAC_AX_MSG_LEVEL_ERR 1
#define MAC_AX_MSG_LEVEL_ALWAYS 0
#define MAC_AX_MSG_LEVEL MAC_AX_MSG_LEVEL_TRACE
#define SET_CLR_WORD(_w, _v, _f) \
(((_w) & ~((_f##_MSK) << (_f##_SH))) | \
(((_v) & (_f##_MSK)) << (_f##_SH)))
#define SET_WORD(_v, _f) (((_v) & (_f##_MSK)) << (_f##_SH))
#define GET_FIELD(_w, _f) (((_w) >> (_f##_SH)) & (_f##_MSK))
#define SET_CLR_WOR2(_w, _v, _sh, _msk) (((_w) & ~(_msk << _sh)) | \
(((_v) & _msk) << _sh))
#define SET_WOR2(_v, _sh, _msk) (((_v) & _msk) << _sh)
#define GET_FIEL2(_w, _sh, _msk) (((_w) >> _sh) & _msk)
#define GET_MSK(_f) ((_f##_MSK) << (_f##_SH))
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/pltfm_cfg_drv.h
|
C
|
agpl-3.0
| 2,219
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_RXDESC_H_
#define _MAC_AX_RXDESC_H_
/* dword0 */
#define AX_RXD_RPKT_LEN_SH 0
#define AX_RXD_RPKT_LEN_MSK 0x3fff
#define AX_RXD_SHIFT_SH 14
#define AX_RXD_SHIFT_MSK 0x3
#define AX_RXD_WL_HD_IV_LEN_SH 16
#define AX_RXD_WL_HD_IV_LEN_MSK 0x3f
#define AX_RXD_BB_SEL BIT(22)
#define AX_RXD_MAC_INFO_VLD BIT(23)
#define AX_RXD_RPKT_TYPE_SH 24
#define AX_RXD_RPKT_TYPE_MSK 0xf
#define AX_RXD_DRV_INFO_SIZE_SH 28
#define AX_RXD_DRV_INFO_SIZE_MSK 0x7
#define AX_RXD_LONG_RXD BIT(31)
/* dword1 */
#define AX_RXD_PPDU_TYPE_SH 0
#define AX_RXD_PPDU_TYPE_MSK 0xf
#define AX_RXD_PPDU_CNT_SH 4
#define AX_RXD_PPDU_CNT_MSK 0x7
#define AX_RXD_SR_EN BIT(7)
#define AX_RXD_USER_ID_SH 8
#define AX_RXD_USER_ID_MSK 0xff
#define AX_RXD_USER_ID_v1_SH 8
#define AX_RXD_USER_ID_v1_MSK 0x3f
#define AX_RXD_RX_DATARATE_SH 16
#define AX_RXD_RX_DATARATE_MSK 0x1ff
#define AX_RXD_RX_GI_LTF_SH 25
#define AX_RXD_RX_GI_LTF_MSK 0x7
#define AX_RXD_NON_SRG_PPDU BIT(28)
#define AX_RXD_INTER_PPDU BIT(29)
#define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
#define AX_RXD_INTER_PPDU_v1 BIT(15)
#define AX_RXD_BW_SH 30
#define AX_RXD_BW_MSK 0x3
#define AX_RXD_BW_v1_SH 29
#define AX_RXD_BW_v1_MSK 0x7
/* dword2 */
#define AX_RXD_FREERUN_CNT_SH 0
#define AX_RXD_FREERUN_CNT_MSK 0xffffffff
/* dword3 */
#define AX_RXD_A1_MATCH BIT(0)
#define AX_RXD_SW_DEC BIT(1)
#define AX_RXD_HW_DEC BIT(2)
#define AX_RXD_AMPDU BIT(3)
#define AX_RXD_AMPDU_END_PKT BIT(4)
#define AX_RXD_AMSDU BIT(5)
#define AX_RXD_AMSDU_CUT BIT(6)
#define AX_RXD_LAST_MSDU BIT(7)
#define AX_RXD_BYPASS BIT(8)
#define AX_RXD_CRC32_ERR BIT(9)
#define AX_RXD_ICV_ERR BIT(10)
#define AX_RXD_MAGIC_WAKE BIT(11)
#define AX_RXD_UNICAST_WAKE BIT(12)
#define AX_RXD_PATTERN_WAKE BIT(13)
#define AX_RXD_GET_CH_INFO_SH 14
#define AX_RXD_GET_CH_INFO_MSK 0x3
#define AX_RXD_PATTERN_IDX_SH 16
#define AX_RXD_PATTERN_IDX_MSK 0x1f
#define AX_RXD_TARGET_IDC_SH 21
#define AX_RXD_TARGET_IDC_MSK 0x7
#define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
#define AX_RXD_WITH_LLC BIT(25)
#define AX_RXD_RX_STATISTICS BIT(26)
/* dword4 */
#define AX_RXD_TYPE_SH 0
#define AX_RXD_TYPE_MSK 0x3
#define AX_RXD_MC BIT(2)
#define AX_RXD_BC BIT(3)
#define AX_RXD_MD BIT(4)
#define AX_RXD_MF BIT(5)
#define AX_RXD_PWR BIT(6)
#define AX_RXD_QOS BIT(7)
#define AX_RXD_TID_SH 8
#define AX_RXD_TID_MSK 0xf
#define AX_RXD_EOSP BIT(12)
#define AX_RXD_HTC BIT(13)
#define AX_RXD_QNULL BIT(14)
#define AX_RXD_SEQ_SH 16
#define AX_RXD_SEQ_MSK 0xfff
#define AX_RXD_FRAG_SH 28
#define AX_RXD_FRAG_MSK 0xf
/* dword5 */
#define AX_RXD_SEC_CAM_IDX_SH 0
#define AX_RXD_SEC_CAM_IDX_MSK 0xff
#define AX_RXD_ADDR_CAM_SH 8
#define AX_RXD_ADDR_CAM_MSK 0xff
#define AX_RXD_MAC_ID_SH 16
#define AX_RXD_MAC_ID_MSK 0xff
#define AX_RXD_RX_PL_ID_SH 24
#define AX_RXD_RX_PL_ID_MSK 0xf
#define AX_RXD_ADDR_CAM_VLD BIT(28)
#define AX_RXD_ADDR_FWD_EN BIT(29)
#define AX_RXD_RX_PL_MATCH BIT(30)
/* dword6 */
#define AX_RXD_MAC_ADDR_SH 0
#define AX_RXD_MAC_ADDR_MSK 0xffffffff
/* dword7 */
#define AX_RXD_MAC_ADDR_H_SH 0
#define AX_RXD_MAC_ADDR_H_MSK 0xffff
#define AX_RXD_SMART_ANT BIT(16)
#define AX_RXD_SEC_TYPE_SH 17
#define AX_RXD_SEC_TYPE_MSK 0xf
#define AX_RXD_HDR_CNV BIT(21)
#define AX_RXD_HDR_OFFSET_SH 22
#define AX_RXD_HDR_OFFSET_MSK 0x1f
#define AX_RXD_BIP_KEYID BIT(27)
#define AX_RXD_BIP_ENC BIT(28)
#define RXD_S_RPKT_TYPE_WIFI 0
#define RXD_S_RPKT_TYPE_PPDU 1
#define RXD_S_RPKT_TYPE_CH_INFO 2
#define RXD_S_RPKT_TYPE_BB_SCORE 3
#define RXD_S_RPKT_TYPE_TXCMD_RPT 4
#define RXD_S_RPKT_TYPE_SS2FW_RPT 5
#define RXD_S_RPKT_TYPE_TXRPT 6
#define RXD_S_RPKT_TYPE_PLDREL_HOST 7
#define RXD_S_RPKT_TYPE_DFS_RPT 8
#define RXD_S_RPKT_TYPE_PLDREL_WLCPU 9
#define RXD_S_RPKT_TYPE_C2H 10
#define RXD_S_RPKT_TYPE_CSI 11
#define RXD_S_RPKT_TYPE_CQI 12
#define RXD_S_RPKT_TYPE_H2C 13
#define RXD_S_RPKT_TYPE_FWDL 14
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/rxdesc.h
|
C
|
agpl-3.0
| 4,590
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_TXDESC_H_
#define _MAC_AX_TXDESC_H_
#if MAC_AX_8852A_SUPPORT
/* dword0 */
#define AX_TXD_WP_OFFSET_SH 24
#define AX_TXD_WP_OFFSET_MSK 0xff
#define AX_TXD_MOREDATA BIT(23)
#define AX_TXD_WDINFO_EN BIT(22)
#define AX_TXD_PKT_OFFSET BIT(21)
#define AX_TXD_FWDL_EN BIT(20)
#define AX_TXD_CH_DMA_SH 16
#define AX_TXD_CH_DMA_MSK 0xf
#define AX_TXD_HDR_LLC_LEN_SH 11
#define AX_TXD_HDR_LLC_LEN_MSK 0x1f
#define AX_TXD_STF_MODE BIT(10)
#define AX_TXD_WP_INT BIT(9)
#define AX_TXD_CHK_EN BIT(8)
#define AX_TXD_WD_PAGE BIT(7)
#define AX_TXD_HW_AES_IV BIT(6)
#define AX_TXD_HWAMSDU BIT(5)
#define AX_TXD_SMH_EN BIT(4)
#define AX_TXD_HW_SSN_SEL_SH 2
#define AX_TXD_HW_SSN_SEL_MSK 0x3
#define AX_TXD_EN_HWSEQ_MODE_SH 0
#define AX_TXD_EN_HWSEQ_MODE_MSK 0x3
/* dword1 */
#define AX_TXD_PLD_SH 16
#define AX_TXD_PLD_MSK 0xffff
#define AX_TXD_DMA_TXAGG_NUM_SH 8
#define AX_TXD_DMA_TXAGG_NUM_MSK 0xff
#define AX_TXD_SHCUT_CAMID_SH 0
#define AX_TXD_SHCUT_CAMID_MSK 0xff
/* dword2 */
#define AX_TXD_MACID_SH 24
#define AX_TXD_MACID_MSK 0x7f
#define AX_TXD_TID_IND BIT(23)
#define AX_TXD_QSEL_SH 17
#define AX_TXD_QSEL_MSK 0x3f
#define AX_TXD_RU_TC_SH 14
#define AX_TXD_RU_TC_MSK 0x7
#define AX_TXD_TXPKTSIZE_SH 0
#define AX_TXD_TXPKTSIZE_MSK 0x3fff
/* dword3 */
#define AX_TXD_MU_TC_SH 29
#define AX_TXD_MU_TC_MSK 0x7
#define AX_TXD_MU_2ND_TC_SH 26
#define AX_TXD_MU_2ND_TC_MSK 0x7
#define AX_TXD_DATA_TC_SH 20
#define AX_TXD_DATA_TC_MSK 0x3f
#define AX_TXD_RTS_TC_SH 14
#define AX_TXD_RTS_TC_MSK 0x3f
#define AX_TXD_BK BIT(13)
#define AX_TXD_AGG_EN BIT(12)
#define AX_TXD_WIFI_SEQ_SH 0
#define AX_TXD_WIFI_SEQ_MSK 0xfff
/* dword4 */
#define AX_TXD_AES_IV_L_SH 16
#define AX_TXD_AES_IV_L_MSK 0xffff
#define AX_TXD_TXDESC_CHECKSUM_SH 0
#define AX_TXD_TXDESC_CHECKSUM_MSK 0xffff
/* dword5 */
#define AX_TXD_AES_IV_H_SH 0
#define AX_TXD_AES_IV_H_MSK 0xffffffff
/* dword6 */
#define AX_TXD_ACK_CH_INFO BIT(31)
#define AX_TXD_USERATE_SEL BIT(30)
#define AX_TXD_DATA_BW_SH 28
#define AX_TXD_DATA_BW_MSK 0x3
#define AX_TXD_GI_LTF_SH 25
#define AX_TXD_GI_LTF_MSK 0x7
#define AX_TXD_DATARATE_SH 16
#define AX_TXD_DATARATE_MSK 0x1ff
#define AX_TXD_DATA_ER BIT(15)
#define AX_TXD_DATA_DCM BIT(14)
#define AX_TXD_DATA_STBC BIT(12)
#define AX_TXD_DATA_LDPC BIT(11)
#define AX_TXD_DISDATAFB BIT(10)
#define AX_TXD_DISRTSFB BIT(9)
#define AX_TXD_DATA_BW_ER BIT(8)
#define AX_TXD_MULTIPORT_ID_SH 4
#define AX_TXD_MULTIPORT_ID_MSK 0x7
#define AX_TXD_MBSSID_SH 0
#define AX_TXD_MBSSID_MSK 0xf
/* dword7 */
#define AX_TXD_DATA_TXCNT_LMT_SEL BIT(31)
#define AX_TXD_DATA_TXCNT_LMT_SH 25
#define AX_TXD_DATA_TXCNT_LMT_MSK 0x3f
#define AX_TXD_DATA_RTY_LOWEST_RATE_SH 16
#define AX_TXD_DATA_RTY_LOWEST_RATE_MSK 0x1ff
#define AX_TXD_A_CTRL_CAS BIT(15)
#define AX_TXD_A_CTRL_BSR BIT(14)
#define AX_TXD_A_CTRL_UPH BIT(13)
#define AX_TXD_A_CTRL_BQR BIT(12)
#define AX_TXD_BMC BIT(11)
#define AX_TXD_NAVUSEHDR BIT(10)
#define AX_TXD_BCN_SRCH_SEQ_SH 8
#define AX_TXD_BCN_SRCH_SEQ_MSK 0x3
#define AX_TXD_MAX_AGG_NUM_SH 0
#define AX_TXD_MAX_AGG_NUM_MSK 0xff
/* dword8 */
#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_SH 26
#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_MSK 0xf
#define AX_TXD_TXPWR_OFSET_TYPE_SH 22
#define AX_TXD_TXPWR_OFSET_TYPE_MSK 0x7
#define AX_TXD_LSIG_TXOP_EN BIT(21)
#define AX_TXD_AMPDU_DENSITY_SH 18
#define AX_TXD_AMPDU_DENSITY_MSK 0x7
#define AX_TXD_FORCE_TXOP BIT(17)
#define AX_TXD_LIFETIME_SEL_SH 13
#define AX_TXD_LIFETIME_SEL_MSK 0x7
#define AX_TXD_SECTYPE_SH 9
#define AX_TXD_SECTYPE_MSK 0xf
#define AX_TXD_SEC_HW_ENC BIT(8)
#define AX_TXD_SEC_CAM_IDX_SH 0
#define AX_TXD_SEC_CAM_IDX_MSK 0xff
/* dword9 */
#define AX_TXD_FORCE_BSS_CLR BIT(31)
#define AX_TXD_SIGNALING_TA_PKT_SC_SH 27
#define AX_TXD_SIGNALING_TA_PKT_SC_MSK 0xf
#define AX_TXD_BCNPKT_TSF_CTRL BIT(26)
#define AX_TXD_GROUP_BIT_IE_OFFSET_SH 16
#define AX_TXD_GROUP_BIT_IE_OFFSET_MSK 0xff
#define AX_TXD_RAW BIT(15)
#define AX_TXD_NULL_1 BIT(14)
#define AX_TXD_NULL_0 BIT(13)
#define AX_TXD_TRI_FRAME BIT(12)
#define AX_TXD_BT_NULL BIT(11)
#define AX_TXD_SPE_RPT BIT(10)
#define AX_TXD_RTT_EN BIT(9)
#define AX_TXD_HT_DATA_SND BIT(7)
#define AX_TXD_SIFS_TX BIT(6)
#define AX_TXD_SND_PKT_SEL_SH 3
#define AX_TXD_SND_PKT_SEL_MSK 0x7
#define AX_TXD_NDPA_SH 1
#define AX_TXD_NDPA_MSK 0x3
#define AX_TXD_SIGNALING_TA_PKT_EN BIT(0)
/* dword10 */
#define AX_TXD_HW_RTS_EN BIT(31)
#define AX_TXD_CCA_RTS_SH 29
#define AX_TXD_CCA_RTS_MSK 0x3
#define AX_TXD_CTS2SELF BIT(28)
#define AX_TXD_RTS_EN BIT(27)
#define AX_TXD_SW_DEFINE_SH 0
#define AX_TXD_SW_DEFINE_MSK 0xf
/* dword11 */
#define AX_TXD_NDPA_DURATION_SH 16
#define AX_TXD_NDPA_DURATION_MSK 0xffff
/* dword12 */
#define AX_TXD_VALID_1 BIT(31)
#define AX_TXD_PCIE_SEQ_NUM_1_SH 16
#define AX_TXD_PCIE_SEQ_NUM_1_MSK 0x7fff
#define AX_TXD_VALID_0 BIT(15)
#define AX_TXD_PCIE_SEQ_NUM_0_SH 0
#define AX_TXD_PCIE_SEQ_NUM_0_MSK 0x7fff
/* dword13 */
#define AX_TXD_VALID_3 BIT(31)
#define AX_TXD_PCIE_SEQ_NUM_3_SH 16
#define AX_TXD_PCIE_SEQ_NUM_3_MSK 0x7fff
#define AX_TXD_VALID_2 BIT(15)
#define AX_TXD_PCIE_SEQ_NUM_2_SH 0
#define AX_TXD_PCIE_SEQ_NUM_2_MSK 0x7fff
#endif
#if MAC_AX_8852B_SUPPORT
/* dword0 */
#define AX_TXD_WP_OFFSET_SH 24
#define AX_TXD_WP_OFFSET_MSK 0xff
#define AX_TXD_MOREDATA BIT(23)
#define AX_TXD_WDINFO_EN BIT(22)
#define AX_TXD_PKT_OFFSET BIT(21)
#define AX_TXD_FWDL_EN BIT(20)
#define AX_TXD_CH_DMA_SH 16
#define AX_TXD_CH_DMA_MSK 0xf
#define AX_TXD_HDR_LLC_LEN_SH 11
#define AX_TXD_HDR_LLC_LEN_MSK 0x1f
#define AX_TXD_STF_MODE BIT(10)
#define AX_TXD_WP_INT BIT(9)
#define AX_TXD_CHK_EN BIT(8)
#define AX_TXD_WD_PAGE BIT(7)
#define AX_TXD_HW_AES_IV BIT(6)
#define AX_TXD_HWAMSDU BIT(5)
#define AX_TXD_SMH_EN BIT(4)
#define AX_TXD_HW_SSN_SEL_SH 2
#define AX_TXD_HW_SSN_SEL_MSK 0x3
#define AX_TXD_EN_HWSEQ_MODE_SH 0
#define AX_TXD_EN_HWSEQ_MODE_MSK 0x3
/* dword1 */
#define AX_TXD_PLD_SH 16
#define AX_TXD_PLD_MSK 0xffff
#define AX_TXD_DMA_TXAGG_NUM_SH 8
#define AX_TXD_DMA_TXAGG_NUM_MSK 0xff
#define AX_TXD_SHCUT_CAMID_SH 0
#define AX_TXD_SHCUT_CAMID_MSK 0xff
/* dword2 */
#define AX_TXD_MACID_SH 24
#define AX_TXD_MACID_MSK 0x7f
#define AX_TXD_TID_IND BIT(23)
#define AX_TXD_QSEL_SH 17
#define AX_TXD_QSEL_MSK 0x3f
#define AX_TXD_RU_TC_SH 14
#define AX_TXD_RU_TC_MSK 0x7
#define AX_TXD_TXPKTSIZE_SH 0
#define AX_TXD_TXPKTSIZE_MSK 0x3fff
/* dword3 */
#define AX_TXD_MU_TC_SH 29
#define AX_TXD_MU_TC_MSK 0x7
#define AX_TXD_MU_2ND_TC_SH 26
#define AX_TXD_MU_2ND_TC_MSK 0x7
#define AX_TXD_DATA_TC_SH 20
#define AX_TXD_DATA_TC_MSK 0x3f
#define AX_TXD_RTS_TC_SH 14
#define AX_TXD_RTS_TC_MSK 0x3f
#define AX_TXD_BK BIT(13)
#define AX_TXD_AGG_EN BIT(12)
#define AX_TXD_WIFI_SEQ_SH 0
#define AX_TXD_WIFI_SEQ_MSK 0xfff
/* dword4 */
#define AX_TXD_AES_IV_L_SH 16
#define AX_TXD_AES_IV_L_MSK 0xffff
#define AX_TXD_TXDESC_CHECKSUM_SH 0
#define AX_TXD_TXDESC_CHECKSUM_MSK 0xffff
/* dword5 */
#define AX_TXD_AES_IV_H_SH 0
#define AX_TXD_AES_IV_H_MSK 0xffffffff
/* dword6 */
#define AX_TXD_ACK_CH_INFO BIT(31)
#define AX_TXD_USERATE_SEL BIT(30)
#define AX_TXD_DATA_BW_SH 28
#define AX_TXD_DATA_BW_MSK 0x3
#define AX_TXD_GI_LTF_SH 25
#define AX_TXD_GI_LTF_MSK 0x7
#define AX_TXD_DATARATE_SH 16
#define AX_TXD_DATARATE_MSK 0x1ff
#define AX_TXD_DATA_ER BIT(15)
#define AX_TXD_DATA_DCM BIT(14)
#define AX_TXD_DATA_STBC BIT(12)
#define AX_TXD_DATA_LDPC BIT(11)
#define AX_TXD_DISDATAFB BIT(10)
#define AX_TXD_DISRTSFB BIT(9)
#define AX_TXD_DATA_BW_ER BIT(8)
#define AX_TXD_MULTIPORT_ID_SH 4
#define AX_TXD_MULTIPORT_ID_MSK 0x7
#define AX_TXD_MBSSID_SH 0
#define AX_TXD_MBSSID_MSK 0xf
/* dword7 */
#define AX_TXD_DATA_TXCNT_LMT_SEL BIT(31)
#define AX_TXD_DATA_TXCNT_LMT_SH 25
#define AX_TXD_DATA_TXCNT_LMT_MSK 0x3f
#define AX_TXD_DATA_RTY_LOWEST_RATE_SH 16
#define AX_TXD_DATA_RTY_LOWEST_RATE_MSK 0x1ff
#define AX_TXD_A_CTRL_CAS BIT(15)
#define AX_TXD_A_CTRL_BSR BIT(14)
#define AX_TXD_A_CTRL_UPH BIT(13)
#define AX_TXD_A_CTRL_BQR BIT(12)
#define AX_TXD_BMC BIT(11)
#define AX_TXD_NAVUSEHDR BIT(10)
#define AX_TXD_BCN_SRCH_SEQ_SH 8
#define AX_TXD_BCN_SRCH_SEQ_MSK 0x3
#define AX_TXD_MAX_AGG_NUM_SH 0
#define AX_TXD_MAX_AGG_NUM_MSK 0xff
/* dword8 */
#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_SH 26
#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_MSK 0xf
#define AX_TXD_TXPWR_OFSET_TYPE_SH 22
#define AX_TXD_TXPWR_OFSET_TYPE_MSK 0x7
#define AX_TXD_LSIG_TXOP_EN BIT(21)
#define AX_TXD_AMPDU_DENSITY_SH 18
#define AX_TXD_AMPDU_DENSITY_MSK 0x7
#define AX_TXD_FORCE_TXOP BIT(17)
#define AX_TXD_LIFETIME_SEL_SH 13
#define AX_TXD_LIFETIME_SEL_MSK 0x7
#define AX_TXD_SECTYPE_SH 9
#define AX_TXD_SECTYPE_MSK 0xf
#define AX_TXD_SEC_HW_ENC BIT(8)
#define AX_TXD_SEC_CAM_IDX_SH 0
#define AX_TXD_SEC_CAM_IDX_MSK 0xff
/* dword9 */
#define AX_TXD_FORCE_BSS_CLR BIT(31)
#define AX_TXD_SIGNALING_TA_PKT_SC_SH 27
#define AX_TXD_SIGNALING_TA_PKT_SC_MSK 0xf
#define AX_TXD_BCNPKT_TSF_CTRL BIT(26)
#define AX_TXD_GROUP_BIT_IE_OFFSET_SH 16
#define AX_TXD_GROUP_BIT_IE_OFFSET_MSK 0xff
#define AX_TXD_RAW BIT(15)
#define AX_TXD_NULL_1 BIT(14)
#define AX_TXD_NULL_0 BIT(13)
#define AX_TXD_TRI_FRAME BIT(12)
#define AX_TXD_BT_NULL BIT(11)
#define AX_TXD_SPE_RPT BIT(10)
#define AX_TXD_RTT_EN BIT(9)
#define AX_TXD_HT_DATA_SND BIT(7)
#define AX_TXD_SIFS_TX BIT(6)
#define AX_TXD_SND_PKT_SEL_SH 3
#define AX_TXD_SND_PKT_SEL_MSK 0x7
#define AX_TXD_NDPA_SH 1
#define AX_TXD_NDPA_MSK 0x3
#define AX_TXD_SIGNALING_TA_PKT_EN BIT(0)
/* dword10 */
#define AX_TXD_HW_RTS_EN BIT(31)
#define AX_TXD_CCA_RTS_SH 29
#define AX_TXD_CCA_RTS_MSK 0x3
#define AX_TXD_CTS2SELF BIT(28)
#define AX_TXD_RTS_EN BIT(27)
#define AX_TXD_SW_DEFINE_SH 0
#define AX_TXD_SW_DEFINE_MSK 0xf
/* dword11 */
#define AX_TXD_NDPA_DURATION_SH 16
#define AX_TXD_NDPA_DURATION_MSK 0xffff
/* dword12 */
#define AX_TXD_VALID_1 BIT(31)
#define AX_TXD_PCIE_SEQ_NUM_1_SH 16
#define AX_TXD_PCIE_SEQ_NUM_1_MSK 0x7fff
#define AX_TXD_VALID_0 BIT(15)
#define AX_TXD_PCIE_SEQ_NUM_0_SH 0
#define AX_TXD_PCIE_SEQ_NUM_0_MSK 0x7fff
/* dword13 */
#define AX_TXD_VALID_3 BIT(31)
#define AX_TXD_PCIE_SEQ_NUM_3_SH 16
#define AX_TXD_PCIE_SEQ_NUM_3_MSK 0x7fff
#define AX_TXD_VALID_2 BIT(15)
#define AX_TXD_PCIE_SEQ_NUM_2_SH 0
#define AX_TXD_PCIE_SEQ_NUM_2_MSK 0x7fff
#endif
#if MAC_AX_8852C_SUPPORT
/* dword0 */
#define AX_TXD_NO_ACK BIT(31)
#define AX_TXD_UPD_WLAN_HDR BIT(30)
#define AX_TXD_WP_OFFSET_V1_SH 24
#define AX_TXD_WP_OFFSET_V1_MSK 0x1f
#define AX_TXD_MOREDATA BIT(23)
#define AX_TXD_WDINFO_EN BIT(22)
#define AX_TXD_PKT_OFFSET BIT(21)
#define AX_TXD_FWDL_EN BIT(20)
#define AX_TXD_CH_DMA_SH 16
#define AX_TXD_CH_DMA_MSK 0xf
#define AX_TXD_HDR_LLC_LEN_SH 11
#define AX_TXD_HDR_LLC_LEN_MSK 0x1f
#define AX_TXD_STF_MODE BIT(10)
#define AX_TXD_WP_INT BIT(9)
#define AX_TXD_CHK_EN BIT(8)
#define AX_TXD_WD_PAGE BIT(7)
#define AX_TXD_HW_SEC_IV BIT(6)
#define AX_TXD_HWAMSDU BIT(5)
#define AX_TXD_SMH_EN BIT(4)
#define AX_TXD_HW_SSN_SEL_SH 2
#define AX_TXD_HW_SSN_SEL_MSK 0x3
#define AX_TXD_EN_HWSEQ_MODE_SH 0
#define AX_TXD_EN_HWSEQ_MODE_MSK 0x3
/* dword1 */
#define AX_TXD_ADDR_INFO_NUM_SH 26
#define AX_TXD_ADDR_INFO_NUM_MSK 0x3f
#define AX_TXD_REUSE_START_NUM_SH 24
#define AX_TXD_REUSE_START_NUM_MSK 0x3
#define AX_TXD_REUSE_SIZE_SH 20
#define AX_TXD_REUSE_SIZE_MSK 0xf
#define AX_TXD_DMA_TXAGG_NUM_V1_SH 8
#define AX_TXD_DMA_TXAGG_NUM_V1_MSK 0x7f
#define AX_TXD_SW_SEC_IV BIT(6)
#define AX_TXD_SEC_KEYID_SH 4
#define AX_TXD_SEC_KEYID_MSK 0x3
#define AX_TXD_SEC_TYPE_SH 0
#define AX_TXD_SEC_TYPE_MSK 0xf
/* dword2 */
#define AX_TXD_MACID_SH 24
#define AX_TXD_MACID_MSK 0x7f
#define AX_TXD_TID_IND BIT(23)
#define AX_TXD_QSEL_SH 17
#define AX_TXD_QSEL_MSK 0x3f
#define AX_TXD_MU_2ND_RTY BIT(16)
#define AX_TXD_MU_PRI_RTY BIT(15)
#define AX_TXD_RU_RTY BIT(14)
#define AX_TXD_TXPKTSIZE_SH 0
#define AX_TXD_TXPKTSIZE_MSK 0x3fff
/* dword3 */
#define AX_TXD_TB_SR_RTY BIT(31)
#define AX_TXD_DATA_TC_SH 20
#define AX_TXD_DATA_TC_MSK 0x3f
#define AX_TXD_RTS_TC_SH 14
#define AX_TXD_RTS_TC_MSK 0x3f
#define AX_TXD_BK BIT(13)
#define AX_TXD_AGG_EN BIT(12)
#define AX_TXD_WIFI_SEQ_SH 0
#define AX_TXD_WIFI_SEQ_MSK 0xfff
/* dword4 */
#define AX_TXD_SEC_IV_L_SH 16
#define AX_TXD_SEC_IV_L_MSK 0xffff
#define AX_TXD_TXDESC_CHECKSUM_SH 0
#define AX_TXD_TXDESC_CHECKSUM_MSK 0xffff
/* dword5 */
#define AX_TXD_SEC_IV_H_SH 0
#define AX_TXD_SEC_IV_H_MSK 0xffffffff
/* dword6 */
#define AX_TXD_RU_POS_SH 24
#define AX_TXD_RU_POS_MSK 0xff
#define AX_TXD_S_IDX_SH 16
#define AX_TXD_S_IDX_MSK 0xff
#define AX_TXD_RU_TC_V1_SH 5
#define AX_TXD_RU_TC_V1_MSK 0x1f
#define AX_TXD_MU_TC_V1_SH 0
#define AX_TXD_MU_TC_V1_MSK 0x1f
/* dword7 */
#define AX_TXD_USERATE_SEL_V1 BIT(31)
#define AX_TXD_DATA_DCM_V1 BIT(30)
#define AX_TXD_DATA_BW_SH 28
#define AX_TXD_DATA_BW_MSK 0x3
#define AX_TXD_GI_LTF_SH 25
#define AX_TXD_GI_LTF_MSK 0x7
#define AX_TXD_DATARATE_SH 16
#define AX_TXD_DATARATE_MSK 0x1ff
/* dword8 */
#define AX_TXD_ACK_CH_INFO BIT(31)
#define AX_TXD_RLS_TO_CPUIO BIT(30)
#define AX_TXD_GI_LTF_SH 25
#define AX_TXD_GI_LTF_MSK 0x7
#define AX_TXD_DATA_ER BIT(15)
#define AX_TXD_DATA_STBC BIT(12)
#define AX_TXD_DATA_LDPC BIT(11)
#define AX_TXD_DISDATAFB BIT(10)
#define AX_TXD_DISRTSFB BIT(9)
#define AX_TXD_DATA_BW_ER BIT(8)
#define AX_TXD_MULTIPORT_ID_SH 4
#define AX_TXD_MULTIPORT_ID_MSK 0x7
#define AX_TXD_MBSSID_SH 0
#define AX_TXD_MBSSID_MSK 0xf
/* dword9 */
#define AX_TXD_DATA_TXCNT_LMT_SEL BIT(31)
#define AX_TXD_DATA_TXCNT_LMT_SH 25
#define AX_TXD_DATA_TXCNT_LMT_MSK 0x3f
#define AX_TXD_DATA_RTY_LOWEST_RATE_SH 16
#define AX_TXD_DATA_RTY_LOWEST_RATE_MSK 0x1ff
#define AX_TXD_A_CTRL_CAS BIT(15)
#define AX_TXD_A_CTRL_BSR BIT(14)
#define AX_TXD_A_CTRL_UPH BIT(13)
#define AX_TXD_A_CTRL_BQR BIT(12)
#define AX_TXD_BMC BIT(11)
#define AX_TXD_NAVUSEHDR BIT(10)
#define AX_TXD_BCN_SRCH_SEQ_SH 8
#define AX_TXD_BCN_SRCH_SEQ_MSK 0x3
#define AX_TXD_MAX_AGG_NUM_SH 0
#define AX_TXD_MAX_AGG_NUM_MSK 0xff
/* dword10 */
#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_SH 26
#define AX_TXD_OBW_CTS2SELF_DUP_TYPE_MSK 0xf
#define AX_TXD_TXPWR_OFSET_TYPE_SH 22
#define AX_TXD_TXPWR_OFSET_TYPE_MSK 0x7
#define AX_TXD_LSIG_TXOP_EN BIT(21)
#define AX_TXD_AMPDU_DENSITY_SH 18
#define AX_TXD_AMPDU_DENSITY_MSK 0x7
#define AX_TXD_FORCE_TXOP BIT(17)
#define AX_TXD_LIFETIME_SEL_SH 13
#define AX_TXD_LIFETIME_SEL_MSK 0x7
#define AX_TXD_FORCE_KEY_EN BIT(8)
#define AX_TXD_SEC_CAM_IDX_SH 0
#define AX_TXD_SEC_CAM_IDX_MSK 0xff
/* dword11 */
#define AX_TXD_FORCE_BSS_CLR BIT(31)
#define AX_TXD_SIGNALING_TA_PKT_SC_SH 27
#define AX_TXD_SIGNALING_TA_PKT_SC_MSK 0xf
#define AX_TXD_BCNPKT_TSF_CTRL BIT(26)
#define AX_TXD_GROUP_BIT_IE_OFFSET_SH 16
#define AX_TXD_GROUP_BIT_IE_OFFSET_MSK 0xff
#define AX_TXD_RAW BIT(15)
#define AX_TXD_NULL_1 BIT(14)
#define AX_TXD_NULL_0 BIT(13)
#define AX_TXD_TRI_FRAME BIT(12)
#define AX_TXD_BT_NULL BIT(11)
#define AX_TXD_SPE_RPT BIT(10)
#define AX_TXD_RTT_EN BIT(9)
#define AX_TXD_HT_DATA_SND BIT(7)
#define AX_TXD_SIFS_TX BIT(6)
#define AX_TXD_SND_PKT_SEL_SH 3
#define AX_TXD_SND_PKT_SEL_MSK 0x7
#define AX_TXD_NDPA_SH 1
#define AX_TXD_NDPA_MSK 0x3
#define AX_TXD_SIGNALING_TA_PKT_EN BIT(0)
/* dword12 */
#define AX_TXD_HW_RTS_EN BIT(31)
#define AX_TXD_CCA_RTS_SH 29
#define AX_TXD_CCA_RTS_MSK 0x3
#define AX_TXD_CTS2SELF BIT(28)
#define AX_TXD_RTS_EN BIT(27)
#define AX_TXD_SW_DEFINE_SH 0
#define AX_TXD_SW_DEFINE_MSK 0xf
/* dword13 */
#define AX_TXD_NDPA_DURATION_SH 16
#define AX_TXD_NDPA_DURATION_MSK 0xffff
/* dword14 */
#define AX_TXD_VALID_1 BIT(31)
#define AX_TXD_PCIE_SEQ_NUM_1_SH 16
#define AX_TXD_PCIE_SEQ_NUM_1_MSK 0x7fff
#define AX_TXD_VALID_0 BIT(15)
#define AX_TXD_PCIE_SEQ_NUM_0_SH 0
#define AX_TXD_PCIE_SEQ_NUM_0_MSK 0x7fff
/* dword15 */
#define AX_TXD_VALID_3 BIT(31)
#define AX_TXD_PCIE_SEQ_NUM_3_SH 16
#define AX_TXD_PCIE_SEQ_NUM_3_MSK 0x7fff
#define AX_TXD_VALID_2 BIT(15)
#define AX_TXD_PCIE_SEQ_NUM_2_SH 0
#define AX_TXD_PCIE_SEQ_NUM_2_MSK 0x7fff
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/txdesc.h
|
C
|
agpl-3.0
| 16,838
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_TYPE_H_
#define _MAC_AX_TYPE_H_
#include "mac_def.h"
#include "mac_reg.h"
#include "mac_hw_info.h"
#include "txdesc.h"
#include "rxdesc.h"
#include "mac_ax/mac_ax_dfs.h"
#include "mac_ax/mac_ax_mac_info.h"
#include "mac_ax/mac_txccxrpt.h"
#if MAC_AX_FEATURE_DBGPKG
#include "mac_ax/dbgpkg.h"
#endif
#if MAC_AX_FEATURE_HV
#include "hv_type.h"
#endif
/*--------------------Define -------------------------------------------*/
#ifdef CONFIG_NEW_HALMAC_INTERFACE
#define PLTFM_SDIO_CMD52_R8(addr) \
hal_sdio_cmd52_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R8(addr) \
hal_sdio_cmd53_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R16(addr) \
hal_sdio_cmd53_r16(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R32(addr) \
hal_sdio_cmd53_r32(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_RN(addr, size, val) \
hal_sdio_cmd53_rn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD52_W8(addr, val) \
hal_sdio_cmd52_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W8(addr, val) \
hal_sdio_cmd53_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_WN(addr, size, val) \
hal_sdio_cmd53_wn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD53_W16(addr, val) \
hal_sdio_cmd53_w16(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W32(addr, val) \
hal_sdio_cmd53_w32(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD52_CIA_R8(addr) \
hal_sdio_read_cia_r8(adapter->drv_adapter, addr)
#define PLTFM_TX(buf, len) \
hal_tx(adapter->drv_adapter, buf, len)
#define PLTFM_FREE(buf, size) \
hal_mem_free(adapter->drv_adapter, buf, size)
#define PLTFM_MALLOC(size) \
hal_mem_alloc(adapter->drv_adapter, size)
#define PLTFM_MEMCPY(dest, src, size) \
hal_mem_cpy(adapter->drv_adapter, dest, src, size)
#define PLTFM_MEMSET(addr, value, size) \
hal_mem_set(adapter->drv_adapter, addr, value, size)
#define PLTFM_MEMCMP(ptr1, ptr2, num) \
hal_mem_cmp(adapter->drv_adapter, ptr1, ptr2, num)
#define PLTFM_DELAY_US(us) \
hal_udelay(adapter->drv_adapter, us)
#define PLTFM_DELAY_MS(ms) \
hal_mdelay(adapter->drv_adapter, ms)
#define PLTFM_MUTEX_INIT(mutex) \
hal_mutex_init(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_DEINIT(mutex) \
hal_mutex_deinit(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_LOCK(mutex) \
hal_mutex_lock(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_UNLOCK(mutex) \
hal_mutex_unlock(adapter->drv_adapter, mutex)
#define PLTFM_MSG_PRINT(...) \
hal_mac_msg_print(drv_adapter, __VA_ARGS__)
#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops))
#define adapter_to_intf_ops(adapter) \
((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops))
#define PLTFM_REG_R8(addr) \
hal_read8(adapter->drv_adapter, addr)
#define PLTFM_REG_R16(addr) \
hal_read16(adapter->drv_adapter, addr)
#define PLTFM_REG_R32(addr) \
hal_read32(adapter->drv_adapter, addr)
#define PLTFM_REG_W8(addr, val) \
hal_write8(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W16(addr, val) \
hal_write16(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W32(addr, val) \
hal_write32(adapter->drv_adapter, addr, val)
#define MAC_REG_R8(addr) hal_read8(adapter->drv_adapter, addr)
#define MAC_REG_R16(addr) hal_read16(adapter->drv_adapter, addr)
#define MAC_REG_R32(addr) hal_read32(adapter->drv_adapter, addr)
#define MAC_REG_W8(addr, val) hal_write8(adapter->drv_adapter, addr, val)
#define MAC_REG_W16(addr, val) hal_write16(adapter->drv_adapter, addr, val)
#define MAC_REG_W32(addr, val) hal_write32(adapter->drv_adapter, addr, val)
#if MAC_AX_FEATURE_DBGCMD
#define PLTFM_SNPRINTF(s, sz, fmt, ...) \
hal_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__)
#define PLTFM_STRCMP(s1, s2) \
hal_strcmp(adapter->drv_adapter, s1, s2)
#define PLTFM_STRSEP(s, ct) \
hal_strsep(adapter->drv_adapter, s, ct)
#define PLTFM_STRLEN(s) \
hal_strlen(adapter->drv_adapter, s)
#define PLTFM_STRCPY(dest, src) \
hal_strcpy(adapter->drv_adapter, dest, src)
#define PLTFM_STRPBRK(cs, ct) \
hal_strpbrk(adapter->drv_adapter, cs, ct)
#define PLTFM_STRTOUL(buf, base) \
hal_strtoul(adapter->drv_adapter, buf, base)
#endif
#else
/* platform callback */
#define PLTFM_SDIO_CMD52_R8(addr) \
adapter->pltfm_cb->sdio_cmd52_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R8(addr) \
adapter->pltfm_cb->sdio_cmd53_r8(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R16(addr) \
adapter->pltfm_cb->sdio_cmd53_r16(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_R32(addr) \
adapter->pltfm_cb->sdio_cmd53_r32(adapter->drv_adapter, addr)
#define PLTFM_SDIO_CMD53_RN(addr, size, val) \
adapter->pltfm_cb->sdio_cmd53_rn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD52_W8(addr, val) \
adapter->pltfm_cb->sdio_cmd52_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W8(addr, val) \
adapter->pltfm_cb->sdio_cmd53_w8(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W16(addr, val) \
adapter->pltfm_cb->sdio_cmd53_w16(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_W32(addr, val) \
adapter->pltfm_cb->sdio_cmd53_w32(adapter->drv_adapter, addr, val)
#define PLTFM_SDIO_CMD53_WN(addr, size, val) \
adapter->pltfm_cb->sdio_cmd53_wn(adapter->drv_adapter, addr, size, val)
#define PLTFM_SDIO_CMD52_CIA_R8(addr) \
adapter->pltfm_cb->sdio_cmd52_cia_r8(adapter->drv_adapter, addr)
#define PLTFM_REG_R8(addr) \
adapter->pltfm_cb->reg_r8(adapter->drv_adapter, addr)
#define PLTFM_REG_R16(addr) \
adapter->pltfm_cb->reg_r16(adapter->drv_adapter, addr)
#define PLTFM_REG_R32(addr) \
adapter->pltfm_cb->reg_r32(adapter->drv_adapter, addr)
#define PLTFM_REG_W8(addr, val) \
adapter->pltfm_cb->reg_w8(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W16(addr, val) \
adapter->pltfm_cb->reg_w16(adapter->drv_adapter, addr, val)
#define PLTFM_REG_W32(addr, val) \
adapter->pltfm_cb->reg_w32(adapter->drv_adapter, addr, val)
#if MAC_AX_PHL_H2C
#define PLTFM_TX(buf) \
adapter->pltfm_cb->tx(adapter->phl_adapter, adapter->drv_adapter, buf)
#define PLTFM_QUERY_H2C(type) \
adapter->pltfm_cb->rtl_query_h2c(adapter->phl_adapter, \
adapter->drv_adapter, type)
#else
#define PLTFM_TX(buf, len) \
adapter->pltfm_cb->tx(adapter->drv_adapter, buf, len)
#endif
#define PLTFM_FREE(buf, size) \
adapter->pltfm_cb->rtl_free(adapter->drv_adapter, buf, size)
#define PLTFM_MALLOC(size) \
adapter->pltfm_cb->rtl_malloc(adapter->drv_adapter, size)
#define PLTFM_MEMCPY(dest, src, size) \
adapter->pltfm_cb->rtl_memcpy(adapter->drv_adapter, dest, src, size)
#define PLTFM_MEMSET(addr, value, size) \
adapter->pltfm_cb->rtl_memset(adapter->drv_adapter, addr, value, size)
#define PLTFM_MEMCMP(ptr1, ptr2, num) \
adapter->pltfm_cb->rtl_memcmp(adapter->drv_adapter, ptr1, ptr2, num)
#define PLTFM_DELAY_US(us) \
adapter->pltfm_cb->rtl_delay_us(adapter->drv_adapter, us)
#define PLTFM_DELAY_MS(ms) \
adapter->pltfm_cb->rtl_delay_ms(adapter->drv_adapter, ms)
#define PLTFM_MUTEX_INIT(mutex) \
adapter->pltfm_cb->rtl_mutex_init(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_DEINIT(mutex) \
adapter->pltfm_cb->rtl_mutex_deinit(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_LOCK(mutex) \
adapter->pltfm_cb->rtl_mutex_lock(adapter->drv_adapter, mutex)
#define PLTFM_MUTEX_UNLOCK(mutex) \
adapter->pltfm_cb->rtl_mutex_unlock(adapter->drv_adapter, mutex)
#define PLTFM_EVENT_NOTIFY(mac_ft, stat, buf, size) \
adapter->pltfm_cb->event_notify(adapter->drv_adapter, mac_ft, stat, \
buf, size)
#define PLTFM_L2_NOTIFY(void) \
adapter->pltfm_cb->ser_l2_notify(adapter->phl_adapter, adapter->drv_adapter)
#define PLTFM_LD_FW_SYMBOL(name, buf, buf_size) \
adapter->pltfm_cb->ld_fw_symbol(adapter->phl_adapter, adapter->drv_adapter,\
name, buf, buf_size)
#define adapter_to_mac_ops(adapter) ((struct mac_ax_ops *)((adapter)->ops))
#define adapter_to_intf_ops(adapter) \
((struct mac_ax_intf_ops *)((adapter)->ops->intf_ops))
#define MAC_REG_R8(addr) ops->reg_read8(adapter, addr)
#define MAC_REG_R16(addr) ops->reg_read16(adapter, addr)
#define MAC_REG_R32(addr) ops->reg_read32(adapter, addr)
#define MAC_REG_W8(addr, val) ops->reg_write8(adapter, addr, val)
#define MAC_REG_W16(addr, val) ops->reg_write16(adapter, addr, val)
#define MAC_REG_W32(addr, val) ops->reg_write32(adapter, addr, val)
#if MAC_AX_FEATURE_DBGCMD
#define PLTFM_SNPRINTF(s, sz, fmt, ...) \
adapter->pltfm_cb->rtl_sprintf(adapter->drv_adapter, s, sz, fmt, ##__VA_ARGS__)
#define PLTFM_STRCMP(s1, s2) \
adapter->pltfm_cb->rtl_strcmp(adapter->drv_adapter, s1, s2)
#define PLTFM_STRSEP(s, ct) \
adapter->pltfm_cb->rtl_strsep(adapter->drv_adapter, s, ct)
#define PLTFM_STRLEN(s) \
adapter->pltfm_cb->rtl_strlen(adapter->drv_adapter, s)
#define PLTFM_STRCPY(dest, src) \
adapter->pltfm_cb->rtl_strcpy(adapter->drv_adapter, dest, src)
#define PLTFM_STRPBRK(cs, ct) \
adapter->pltfm_cb->rtl_strpbrk(adapter->drv_adapter, cs, ct)
#define PLTFM_STRTOUL(buf, base) \
adapter->pltfm_cb->rtl_strtoul(adapter->drv_adapter, buf, base)
#endif
#endif /*CONFIG_NEW_HALMAC_INTERFACE*/
#define MAC_AX_WMM0_SEL 0
#define MAC_AX_WMM1_SEL 1
#define MAC_AX_WMM2_SEL 2
#define MAC_AX_WMM3_SEL 3
#define MAC_AX_HI0_SEL 17
#define MAC_AX_MG0_SEL 18
#define MAC_AX_HI1_SEL 25
#define MAC_AX_MG1_SEL 26
#define MAC_AX_HFC_CH_NUM 12
#define MAC_AX_IECAM_NUM 12
#define MAC_AX_R32_EA 0xEAEAEAEA
#define MAC_AX_R32_DEAD 0xDEADBEEF
#define MAC_AX_R32_DEAD2 0xDEADDEAD
#define MAC_AX_R32_FF 0xFFFFFFFF
#define MAC_AX_R16_DEAD 0xDEAD
#define MAC_REG_POOL_COUNT 10
#define MAC_REG_OFFSET16 2
#define MAC_REG_OFFSET 4
#define MAC_REG_OFFSET_SH 8
#define MAC_REG_OFFSET_SH_2 3
#define R_AX_CMAC_REG_END 0xFFFF
/* SRAM mem dump */
#define R_AX_INDIR_ACCESS_ENTRY 0x40000
#define MAC_MEM_DUMP_PAGE_SIZE 0x40000
#define CPU_LOCAL_BASE_ADDR 0x18003000
#define AXIDMA_BASE_ADDR 0x18006000
#define STA_SCHED_BASE_ADDR 0x18808000
#define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
#define SEC_CAM_BASE_ADDR 0x18814000
#define WOW_CAM_BASE_ADDR 0x18815000
#define CMAC_TBL_BASE_ADDR 0x18840000
#define ADDR_CAM_BASE_ADDR 0x18850000
#define BSSID_CAM_BASE_ADDR 0x18853000
#define BA_CAM_BASE_ADDR 0x18854000
#define BCN_IE_CAM0_BASE_ADDR 0x18855000
#define SHARED_BUF_BASE_ADDR 0x18700000
#define DMAC_TBL_BASE_ADDR 0x18800000
#define SHCUT_MACHDR_BASE_ADDR 0x18800800
#define BCN_IE_CAM1_BASE_ADDR 0x188A0000
#define TXD_FIFO_0_BASE_ADDR 0x18856200
#define TXD_FIFO_1_BASE_ADDR 0x188A1080
#define CCTL_INFO_SIZE 32
#define DCTL_INFO_SIZE 16
#define DCTL_INFO_SIZE_V1 32
#define MACHDR_SIZE 56
#define BA_CAM_SIZE 64
#define BA_CAM_NUM_SH 3
#define BCN_IE_CAM_SIZE 8
#define BCN_IE_CAM_NUM 12
#define AXIDMA_REG_SIZE 0x1000
/*--------------------Define Enum---------------------------------------*/
/**
* @enum mac_ax_dma_ch
*
* @brief mac_ax_dma_ch
*
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH0
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH1
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH2
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH3
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH4
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH5
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH6
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_ACH7
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_B0MG
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_B0HI
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_B1MG
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_B1HI
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_H2C
* Please Place Description here.
* @var mac_ax_dma_ch::MAC_AX_DMA_CH_NUM
* Please Place Description here.
*/
enum mac_ax_dma_ch {
MAC_AX_DMA_ACH0 = 0,
MAC_AX_DMA_ACH1,
MAC_AX_DMA_ACH2,
MAC_AX_DMA_ACH3,
MAC_AX_DMA_ACH4,
MAC_AX_DMA_ACH5,
MAC_AX_DMA_ACH6,
MAC_AX_DMA_ACH7,
MAC_AX_DMA_B0MG,
MAC_AX_DMA_B0HI,
MAC_AX_DMA_B1MG,
MAC_AX_DMA_B1HI,
MAC_AX_DMA_H2C,
MAC_AX_DMA_CH_NUM
};
/**
* @enum mac_ax_data_ch
*
* @brief mac_ax_data_ch
*
* @var mac_ax_data_ch::MAC_AX_DATA_CH0
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH1
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH2
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH3
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH4
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH5
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH6
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH7
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_HIQ
* Please Place Description here.
*/
/**
* @enum mac_ax_data_ch
*
* @brief mac_ax_data_ch
*
* @var mac_ax_data_ch::MAC_AX_DATA_CH0
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH1
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH2
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH3
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH4
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH5
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH6
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_CH7
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_MGN
* Please Place Description here.
* @var mac_ax_data_ch::MAC_AX_DATA_HIQ
* Please Place Description here.
*/
enum mac_ax_data_ch {
MAC_AX_DATA_CH0 = 0,
MAC_AX_DATA_CH1 = 1,
MAC_AX_DATA_CH2 = 2,
MAC_AX_DATA_CH3 = 3,
MAC_AX_DATA_CH4 = 4,
MAC_AX_DATA_CH5 = 5,
MAC_AX_DATA_CH6 = 6,
MAC_AX_DATA_CH7 = 7,
MAC_AX_DATA_MGN = 8,
MAC_AX_DATA_HIQ = 9
};
/**
* @enum mac_ax_pcie_phy
*
* @brief mac_ax_pcie_phy
*
* @var mac_ax_pcie_phy::MAC_AX_PCIE_PHY_GEN1
* Please Place Description here.
* @var mac_ax_pcie_phy::MAC_AX_PCIE_PHY_GEN2
* Please Place Description here.
* @var mac_ax_pcie_phy::MAC_AX_PCIE_PHY_GEN1_UNDEFINE
* Please Place Description here.
*/
enum mac_ax_pcie_phy {
MAC_AX_PCIE_PHY_GEN1,
MAC_AX_PCIE_PHY_GEN2,
MAC_AX_PCIE_PHY_GEN1_UNDEFINE = 0x7F,
};
/**
* @enum mac_ax_data_rate
*
* @brief mac_ax_data_rate
*
* @var mac_ax_data_rate::MAC_AX_CCK1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_CCK2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_CCK5_5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_CCK11
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM12
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM18
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM24
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM36
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM48
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_OFDM54
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS10
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS11
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS12
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS13
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS14
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS15
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS16
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS17
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS18
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS19
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS20
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS21
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS22
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS23
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS24
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS25
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS26
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS27
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS28
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS29
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS30
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_MCS31
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS1_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS2_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS3_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_VHT_NSS4_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS10
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS1_MCS11
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS10
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS2_MCS11
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS10
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS3_MCS11
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS0
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS1
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS2
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS3
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS4
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS5
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS6
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS7
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS8
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS9
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS10
* Please Place Description here.
* @var mac_ax_data_rate::MAC_AX_HE_NSS4_MCS11
* Please Place Description here.
*/
enum mac_ax_data_rate {
MAC_AX_CCK1 = 0x0,
MAC_AX_CCK2 = 0x1,
MAC_AX_CCK5_5 = 0x2,
MAC_AX_CCK11 = 0x3,
MAC_AX_OFDM6 = 0x4,
MAC_AX_OFDM9 = 0x5,
MAC_AX_OFDM12 = 0x6,
MAC_AX_OFDM18 = 0x7,
MAC_AX_OFDM24 = 0x8,
MAC_AX_OFDM36 = 0x9,
MAC_AX_OFDM48 = 0xA,
MAC_AX_OFDM54 = 0xB,
MAC_AX_MCS0 = 0x80,
MAC_AX_MCS1 = 0x81,
MAC_AX_MCS2 = 0x82,
MAC_AX_MCS3 = 0x83,
MAC_AX_MCS4 = 0x84,
MAC_AX_MCS5 = 0x85,
MAC_AX_MCS6 = 0x86,
MAC_AX_MCS7 = 0x87,
MAC_AX_MCS8 = 0x88,
MAC_AX_MCS9 = 0x89,
MAC_AX_MCS10 = 0x8A,
MAC_AX_MCS11 = 0x8B,
MAC_AX_MCS12 = 0x8C,
MAC_AX_MCS13 = 0x8D,
MAC_AX_MCS14 = 0x8E,
MAC_AX_MCS15 = 0x8F,
MAC_AX_MCS16 = 0x90,
MAC_AX_MCS17 = 0x91,
MAC_AX_MCS18 = 0x92,
MAC_AX_MCS19 = 0x93,
MAC_AX_MCS20 = 0x94,
MAC_AX_MCS21 = 0x95,
MAC_AX_MCS22 = 0x96,
MAC_AX_MCS23 = 0x97,
MAC_AX_MCS24 = 0x98,
MAC_AX_MCS25 = 0x99,
MAC_AX_MCS26 = 0x9A,
MAC_AX_MCS27 = 0x9B,
MAC_AX_MCS28 = 0x9C,
MAC_AX_MCS29 = 0x9D,
MAC_AX_MCS30 = 0x9E,
MAC_AX_MCS31 = 0x9F,
MAC_AX_VHT_NSS1_MCS0 = 0x100,
MAC_AX_VHT_NSS1_MCS1 = 0x101,
MAC_AX_VHT_NSS1_MCS2 = 0x102,
MAC_AX_VHT_NSS1_MCS3 = 0x103,
MAC_AX_VHT_NSS1_MCS4 = 0x104,
MAC_AX_VHT_NSS1_MCS5 = 0x105,
MAC_AX_VHT_NSS1_MCS6 = 0x106,
MAC_AX_VHT_NSS1_MCS7 = 0x107,
MAC_AX_VHT_NSS1_MCS8 = 0x108,
MAC_AX_VHT_NSS1_MCS9 = 0x109,
MAC_AX_VHT_NSS2_MCS0 = 0x110,
MAC_AX_VHT_NSS2_MCS1 = 0x111,
MAC_AX_VHT_NSS2_MCS2 = 0x112,
MAC_AX_VHT_NSS2_MCS3 = 0x113,
MAC_AX_VHT_NSS2_MCS4 = 0x114,
MAC_AX_VHT_NSS2_MCS5 = 0x115,
MAC_AX_VHT_NSS2_MCS6 = 0x116,
MAC_AX_VHT_NSS2_MCS7 = 0x117,
MAC_AX_VHT_NSS2_MCS8 = 0x118,
MAC_AX_VHT_NSS2_MCS9 = 0x119,
MAC_AX_VHT_NSS3_MCS0 = 0x120,
MAC_AX_VHT_NSS3_MCS1 = 0x121,
MAC_AX_VHT_NSS3_MCS2 = 0x122,
MAC_AX_VHT_NSS3_MCS3 = 0x123,
MAC_AX_VHT_NSS3_MCS4 = 0x124,
MAC_AX_VHT_NSS3_MCS5 = 0x125,
MAC_AX_VHT_NSS3_MCS6 = 0x126,
MAC_AX_VHT_NSS3_MCS7 = 0x127,
MAC_AX_VHT_NSS3_MCS8 = 0x128,
MAC_AX_VHT_NSS3_MCS9 = 0x129,
MAC_AX_VHT_NSS4_MCS0 = 0x130,
MAC_AX_VHT_NSS4_MCS1 = 0x131,
MAC_AX_VHT_NSS4_MCS2 = 0x132,
MAC_AX_VHT_NSS4_MCS3 = 0x133,
MAC_AX_VHT_NSS4_MCS4 = 0x134,
MAC_AX_VHT_NSS4_MCS5 = 0x135,
MAC_AX_VHT_NSS4_MCS6 = 0x136,
MAC_AX_VHT_NSS4_MCS7 = 0x137,
MAC_AX_VHT_NSS4_MCS8 = 0x138,
MAC_AX_VHT_NSS4_MCS9 = 0x139,
MAC_AX_HE_NSS1_MCS0 = 0x180,
MAC_AX_HE_NSS1_MCS1 = 0x181,
MAC_AX_HE_NSS1_MCS2 = 0x182,
MAC_AX_HE_NSS1_MCS3 = 0x183,
MAC_AX_HE_NSS1_MCS4 = 0x184,
MAC_AX_HE_NSS1_MCS5 = 0x185,
MAC_AX_HE_NSS1_MCS6 = 0x186,
MAC_AX_HE_NSS1_MCS7 = 0x187,
MAC_AX_HE_NSS1_MCS8 = 0x188,
MAC_AX_HE_NSS1_MCS9 = 0x189,
MAC_AX_HE_NSS1_MCS10 = 0x18A,
MAC_AX_HE_NSS1_MCS11 = 0x18B,
MAC_AX_HE_NSS2_MCS0 = 0x190,
MAC_AX_HE_NSS2_MCS1 = 0x191,
MAC_AX_HE_NSS2_MCS2 = 0x192,
MAC_AX_HE_NSS2_MCS3 = 0x193,
MAC_AX_HE_NSS2_MCS4 = 0x194,
MAC_AX_HE_NSS2_MCS5 = 0x195,
MAC_AX_HE_NSS2_MCS6 = 0x196,
MAC_AX_HE_NSS2_MCS7 = 0x197,
MAC_AX_HE_NSS2_MCS8 = 0x198,
MAC_AX_HE_NSS2_MCS9 = 0x199,
MAC_AX_HE_NSS2_MCS10 = 0x19A,
MAC_AX_HE_NSS2_MCS11 = 0x19B,
MAC_AX_HE_NSS3_MCS0 = 0x1A0,
MAC_AX_HE_NSS3_MCS1 = 0x1A1,
MAC_AX_HE_NSS3_MCS2 = 0x1A2,
MAC_AX_HE_NSS3_MCS3 = 0x1A3,
MAC_AX_HE_NSS3_MCS4 = 0x1A4,
MAC_AX_HE_NSS3_MCS5 = 0x1A5,
MAC_AX_HE_NSS3_MCS6 = 0x1A6,
MAC_AX_HE_NSS3_MCS7 = 0x1A7,
MAC_AX_HE_NSS3_MCS8 = 0x1A8,
MAC_AX_HE_NSS3_MCS9 = 0x1A9,
MAC_AX_HE_NSS3_MCS10 = 0x1AA,
MAC_AX_HE_NSS3_MCS11 = 0x1AB,
MAC_AX_HE_NSS4_MCS0 = 0x1B0,
MAC_AX_HE_NSS4_MCS1 = 0x1B1,
MAC_AX_HE_NSS4_MCS2 = 0x1B2,
MAC_AX_HE_NSS4_MCS3 = 0x1B3,
MAC_AX_HE_NSS4_MCS4 = 0x1B4,
MAC_AX_HE_NSS4_MCS5 = 0x1B5,
MAC_AX_HE_NSS4_MCS6 = 0x1B6,
MAC_AX_HE_NSS4_MCS7 = 0x1B7,
MAC_AX_HE_NSS4_MCS8 = 0x1B8,
MAC_AX_HE_NSS4_MCS9 = 0x1B9,
MAC_AX_HE_NSS4_MCS10 = 0x1BA,
MAC_AX_HE_NSS4_MCS11 = 0x1BB
};
/**
* @struct wd_body_t
* @brief wd_body_t
*
* @var wd_body_t::dword0
* Please Place Description here.
* @var wd_body_t::dword1
* Please Place Description here.
* @var wd_body_t::dword2
* Please Place Description here.
* @var wd_body_t::dword3
* Please Place Description here.
* @var wd_body_t::dword4
* Please Place Description here.
* @var wd_body_t::dword5
* Please Place Description here.
*/
struct wd_body_t {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
/**
* @struct wd_info_t
* @brief wd_info_t
*
* @var wd_info_t::dword0
* Please Place Description here.
* @var wd_info_t::dword1
* Please Place Description here.
* @var wd_info_t::dword2
* Please Place Description here.
* @var wd_info_t::dword3
* Please Place Description here.
* @var wd_info_t::dword4
* Please Place Description here.
* @var wd_info_t::dword5
* Please Place Description here.
*/
struct wd_info_t {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
#define WD_BODY_LEN (sizeof(struct wd_body_t))
#define WD_INFO_LEN (sizeof(struct wd_info_t))
/**
* @struct wd_body_t_v1
* @brief wd_body_t_v1
*
* @var wd_body_t::dword0
* Please Place Description here.
* @var wd_body_t::dword1
* Please Place Description here.
* @var wd_body_t::dword2
* Please Place Description here.
* @var wd_body_t::dword3
* Please Place Description here.
* @var wd_body_t::dword4
* Please Place Description here.
* @var wd_body_t::dword5
* Please Place Description here.
* @var wd_body_t::dword6
* Please Place Description here.
* @var wd_body_t::dword7
* Please Place Description here.
*/
struct wd_body_t_v1 {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
};
#define WD_BODY_LEN_V1 (sizeof(struct wd_body_t_v1))
/**
* @struct rxd_short_t
* @brief rxd_short_t
*
* @var rxd_short_t::dword0
* Please Place Description here.
* @var rxd_short_t::dword1
* Please Place Description here.
* @var rxd_short_t::dword2
* Please Place Description here.
* @var rxd_short_t::dword3
* Please Place Description here.
*/
struct rxd_short_t {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
/**
* @struct rxd_long_t
* @brief rxd_long_t
*
* @var rxd_long_t::dword0
* Please Place Description here.
* @var rxd_long_t::dword1
* Please Place Description here.
* @var rxd_long_t::dword2
* Please Place Description here.
* @var rxd_long_t::dword3
* Please Place Description here.
* @var rxd_long_t::dword4
* Please Place Description here.
* @var rxd_long_t::dword5
* Please Place Description here.
* @var rxd_long_t::dword6
* Please Place Description here.
* @var rxd_long_t::dword7
* Please Place Description here.
*/
struct rxd_long_t {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
};
#define RXD_SHORT_LEN (sizeof(struct rxd_short_t))
#define RXD_LONG_LEN (sizeof(struct rxd_long_t))
/**
* @struct txd_proc_type
* @brief txd_proc_type
*
* @var txd_proc_type::type
* Please Place Description here.
* @var txd_proc_type::handler
* Please Place Description here.
*/
struct txd_proc_type {
enum rtw_packet_type type;
u32 (*handler)(struct mac_ax_adapter *adapter,
struct rtw_t_meta_data *info, u8 *buf, u32 len);
};
/**
* @struct rxd_parse_type
* @brief rxd_parse_type
*
* @var rxd_parse_type::type
* Please Place Description here.
* @var rxd_parse_type::handler
* Please Place Description here.
*/
struct rxd_parse_type {
u8 type;
u32 (*handler)(struct mac_ax_adapter *adapter,
struct mac_ax_rxpkt_info *info, u8 *buf, u32 len);
};
/**
* @enum mac_ax_bw
*
* @brief mac_ax_bw
*
* @var mac_ax_bw::MAC_AX_BW_20M
* Please Place Description here.
* @var mac_ax_bw::MAC_AX_BW_40M
* Please Place Description here.
* @var mac_ax_bw::MAC_AX_BW_80M
* Please Place Description here.
* @var mac_ax_bw::MAC_AX_BW_160M
* Please Place Description here.
* @var mac_ax_bw::MAC_AX_BW_UNDEFINE
* Please Place Description here.
*/
enum mac_ax_bw {
MAC_AX_BW_20M = 0,
MAC_AX_BW_40M = 1,
MAC_AX_BW_80M = 2,
MAC_AX_BW_160M = 3,
MAC_AX_BW_UNDEFINE = 0x7F
};
/**
* @enum mac_ax_gi_ltf
*
* @brief mac_ax_gi_ltf
*
* @var mac_ax_gi_ltf::MAC_AX_LGI_4XHE32
* Please Place Description here.
* @var mac_ax_gi_ltf::MAC_AX_SGI_4XHE08
* Please Place Description here.
* @var mac_ax_gi_ltf::MAC_AX_2XHE16
* Please Place Description here.
* @var mac_ax_gi_ltf::MAC_AX_2XHE08
* Please Place Description here.
* @var mac_ax_gi_ltf::MAC_AX_1XHE16
* Please Place Description here.
* @var mac_ax_gi_ltf::MAC_AX_1XHE08
* Please Place Description here.
*/
enum mac_ax_gi_ltf {
MAC_AX_LGI_4XHE32 = 0,
MAC_AX_SGI_4XHE08 = 1,
MAC_AX_2XHE16 = 2,
MAC_AX_2XHE08 = 3,
MAC_AX_1XHE16 = 4,
MAC_AX_1XHE08 = 5
};
/**
* @enum mac_ax_stbc
*
* @brief mac_ax_stbc
*
* @var mac_ax_stbc::MAC_AX_STBC_DIS
* Please Place Description here.
* @var mac_ax_stbc::MAC_AX_STBC_EN
* Please Place Description here.
* @var mac_ax_stbc::MAC_AX_STBC_HT2
* Please Place Description here.
*/
enum mac_ax_stbc {
MAC_AX_STBC_DIS = 0,
MAC_AX_STBC_EN = 1,
MAC_AX_STBC_HT2 = 2
};
/**
* @enum mac_ax_delay_tx_en
*
* @brief mac_ax_delay_tx_en
*
* @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_DIS
* Please Place Description here.
* @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_B0
* Please Place Description here.
* @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_B1
* Please Place Description here.
* @var mac_ax_delay_tx_en::MAC_AX_DELAY_TX_BOTH
* Please Place Description here.
*/
enum mac_ax_delay_tx_en {
MAC_AX_DELAY_TX_DIS = 0,
MAC_AX_DELAY_TX_B0 = 1,
MAC_AX_DELAY_TX_B1 = 2,
MAC_AX_DELAY_TX_BOTH = 3,
};
/**
* @enum mac_ax_hcifc_mode
*
* @brief mac_ax_hcifc_mode
*
* @var mac_ax_hcifc_mode::MAC_AX_HCIFC_POH
* Please Place Description here.
* @var mac_ax_hcifc_mode::MAC_AX_HCIFC_STF
* Please Place Description here.
* @var mac_ax_hcifc_mode::MAC_AX_HCIFC_SDIO
* Please Place Description here.
* @var mac_ax_hcifc_mode::MAC_AX_HCIFC_LAST
* Please Place Description here.
* @var mac_ax_hcifc_mode::MAC_AX_HCIFC_MODE_MAX
* Please Place Description here.
* @var mac_ax_hcifc_mode::MAC_AX_HCIFC_MODE_INVALID
* Please Place Description here.
*/
enum mac_ax_hcifc_mode {
MAC_AX_HCIFC_POH = 0,
MAC_AX_HCIFC_STF = 1,
MAC_AX_HCIFC_SDIO = 2,
/* keep last */
MAC_AX_HCIFC_LAST,
MAC_AX_HCIFC_MODE_MAX = MAC_AX_HCIFC_LAST,
MAC_AX_HCIFC_MODE_INVALID = MAC_AX_HCIFC_LAST,
};
/**
* @enum mac_ax_bcn_hit_rule
*
* @brief mac_ax_bcn_hit_rule
*
* @var mac_ax_bcn_hit_rule::MAC_AX_A3
* Please Place Description here.
* @var mac_ax_bcn_hit_rule::MAC_AX_A2
* Please Place Description here.
* @var mac_ax_bcn_hit_rule::MAC_AX_A2_AND_A3
* Please Place Description here.
* @var mac_ax_bcn_hit_rule::MAC_AX_A2_OR_A3
* Please Place Description here.
*/
enum mac_ax_bcn_hit_rule {
MAC_AX_A3,
MAC_AX_A2,
MAC_AX_A2_AND_A3,
MAC_AX_A2_OR_A3
};
/**
* @enum mac_ax_hit_rule
*
* @brief mac_ax_hit_rule
*
* @var mac_ax_hit_rule::MAC_AX_A1_AND_A2
* Please Place Description here.
* @var mac_ax_hit_rule::MAC_AX_A1_AND_A3
* Please Place Description here.
*/
enum mac_ax_hit_rule {
MAC_AX_A1_AND_A2,
MAC_AX_A1_AND_A3
};
/**
* @enum mac_ax_bb_sel
*
* @brief mac_ax_bb_sel
*
* @var mac_ax_bb_sel::MAC_AX_PHY_0
* Please Place Description here.
* @var mac_ax_bb_sel::MAC_AX_PHY_1
* Please Place Description here.
*/
enum mac_ax_bb_sel {
MAC_AX_PHY_0,
MAC_AX_PHY_1
};
/**
* @enum mac_ax_pps_sel
*
* @brief mac_ax_pps_sel
*
* @var mac_ax_pps_sel::MAC_AX_PPS_0
* Please Place Description here.
* @var mac_ax_pps_sel::MAC_AX_PPS_1
* Please Place Description here.
* @var mac_ax_pps_sel::MAC_AX_PPS_LAST
* Please Place Description here.
* @var mac_ax_pps_sel::MAC_AX_PPS_MAX
* Please Place Description here.
* @var mac_ax_pps_sel::MAC_AX_PPS_INVALID
* Please Place Description here.
*/
enum mac_ax_pps_sel {
MAC_AX_PPS_0 = 0,
MAC_AX_PPS_1,
/* keep last */
MAC_AX_PPS_LAST,
MAC_AX_PPS_MAX = MAC_AX_PPS_LAST,
MAC_AX_PPS_INVALID = MAC_AX_PPS_LAST,
};
/**
* @enum mac_ax_tgt_ind
*
* @brief mac_ax_tgt_ind
*
* @var mac_ax_tgt_ind::MAC_AX_TO_HOST
* Please Place Description here.
* @var mac_ax_tgt_ind::MAC_AX_TO_WLAN_CPU
* Please Place Description here.
* @var mac_ax_tgt_ind::MAC_AX_TO_DRIVER
* Please Place Description here.
*/
enum mac_ax_tgt_ind {
MAC_AX_TO_HOST,
MAC_AX_TO_WLAN_CPU,
MAC_AX_TO_DRIVER
};
/**
* @enum mac_ax_frm_tgt_ind
*
* @brief mac_ax_frm_tgt_ind
*
* @var mac_ax_frm_tgt_ind::MAC_AX_DIS_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_MGT_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_CTL_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_MGT_CTL_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_DATA_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_MGT_DATA_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_CTL_DATA_FRAM_TGT
* Please Place Description here.
* @var mac_ax_frm_tgt_ind::MAC_AX_MGT_CTL_DATA_FRAM_TGT
* Please Place Description here.
*/
enum mac_ax_frm_tgt_ind {
MAC_AX_DIS_FRAM_TGT,
MAC_AX_MGT_FRAM_TGT,
MAC_AX_CTL_FRAM_TGT,
MAC_AX_MGT_CTL_FRAM_TGT,
MAC_AX_DATA_FRAM_TGT,
MAC_AX_MGT_DATA_FRAM_TGT,
MAC_AX_CTL_DATA_FRAM_TGT,
MAC_AX_MGT_CTL_DATA_FRAM_TGT,
};
/**
* @enum mac_ax_txcnt_sel
*
* @brief mac_ax_txcnt_sel
*
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_LCCK
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_SCCK
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_OFDM
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HT
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HTGF
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_VHTSU
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_VHTMU
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HESU
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HEERSU
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HEMU
* Please Place Description here.
* @var mac_ax_txcnt_sel::MAC_AX_TXCNT_HETB
* Please Place Description here.
*/
enum mac_ax_txcnt_sel {
MAC_AX_TXCNT_LCCK = 0,
MAC_AX_TXCNT_SCCK = 1,
MAC_AX_TXCNT_OFDM = 2,
MAC_AX_TXCNT_HT = 3,
MAC_AX_TXCNT_HTGF = 4,
MAC_AX_TXCNT_VHTSU = 5,
MAC_AX_TXCNT_VHTMU = 6,
MAC_AX_TXCNT_HESU = 7,
MAC_AX_TXCNT_HEERSU = 8,
MAC_AX_TXCNT_HEMU = 9,
MAC_AX_TXCNT_HETB = 0xA
};
/**
* @enum mac_ax_rxcnt_sel
*
* @brief mac_ax_rxcnt_sel
*
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_OFDM_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_OFDM_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_OFDM_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CCK_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CCK_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CCK_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_PPDU
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HT_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_PPDU
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTSU_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_PPDU
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_VHTMU_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_PPDU
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HESU_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_PPDU
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HEMU_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_FAIL
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_PPDU
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_HETB_FAM
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_INVD
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_RECCA
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_FULLDRP
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_FULLDRP_PKT
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_RXDMA
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER0
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER1
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER2
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_USER3
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CONT_FCS
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_PKTFLTR_DRP
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CSIPKT_DMA_OK
* Please Place Description here.
* @var mac_ax_rxcnt_sel::MAC_AX_RXCNT_CSIPKT_DMA_DROP
* Please Place Description here.
*/
enum mac_ax_rxcnt_sel {
MAC_AX_RXCNT_OFDM_OK = 0,
MAC_AX_RXCNT_OFDM_FAIL = 1,
MAC_AX_RXCNT_OFDM_FAM = 2,
MAC_AX_RXCNT_CCK_OK = 3,
MAC_AX_RXCNT_CCK_FAIL = 4,
MAC_AX_RXCNT_CCK_FAM = 5,
MAC_AX_RXCNT_HT_OK = 6,
MAC_AX_RXCNT_HT_FAIL = 7,
MAC_AX_RXCNT_HT_PPDU = 8,
MAC_AX_RXCNT_HT_FAM = 9,
MAC_AX_RXCNT_VHTSU_OK = 0xA,
MAC_AX_RXCNT_VHTSU_FAIL = 0xB,
MAC_AX_RXCNT_VHTSU_PPDU = 0xC,
MAC_AX_RXCNT_VHTSU_FAM = 0xD,
MAC_AX_RXCNT_VHTMU_OK = 0xE,
MAC_AX_RXCNT_VHTMU_FAIL = 0xF,
MAC_AX_RXCNT_VHTMU_PPDU = 0x10,
MAC_AX_RXCNT_VHTMU_FAM = 0x11,
MAC_AX_RXCNT_HESU_OK = 0x12,
MAC_AX_RXCNT_HESU_FAIL = 0x13,
MAC_AX_RXCNT_HESU_PPDU = 0x14,
MAC_AX_RXCNT_HESU_FAM = 0x15,
MAC_AX_RXCNT_HEMU_OK = 0x16,
MAC_AX_RXCNT_HEMU_FAIL = 0x17,
MAC_AX_RXCNT_HEMU_PPDU = 0x18,
MAC_AX_RXCNT_HEMU_FAM = 0x19,
MAC_AX_RXCNT_HETB_OK = 0x1A,
MAC_AX_RXCNT_HETB_FAIL = 0x1B,
MAC_AX_RXCNT_HETB_PPDU = 0x1C,
MAC_AX_RXCNT_HETB_FAM = 0x1D,
MAC_AX_RXCNT_INVD = 0x1E,
MAC_AX_RXCNT_RECCA = 0x1F,
MAC_AX_RXCNT_FULLDRP = 0x20,
MAC_AX_RXCNT_FULLDRP_PKT = 0x21,
MAC_AX_RXCNT_RXDMA = 0x22,
MAC_AX_RXCNT_USER0 = 0x23,
MAC_AX_RXCNT_USER1 = 0x24,
MAC_AX_RXCNT_USER2 = 0x25,
MAC_AX_RXCNT_USER3 = 0x26,
MAC_AX_RXCNT_CONT_FCS = 0x27,
MAC_AX_RXCNT_PKTFLTR_DRP = 0x28,
MAC_AX_RXCNT_CSIPKT_DMA_OK = 0x29,
MAC_AX_RXCNT_CSIPKT_DMA_DROP = 0x2A
};
/**
* @enum mac_ax_wde_pg_size
*
* @brief mac_ax_wde_pg_size
*
* @var mac_ax_wde_pg_size::MAC_AX_WDE_PG_64
* Please Place Description here.
* @var mac_ax_wde_pg_size::MAC_AX_WDE_PG_128
* Please Place Description here.
* @var mac_ax_wde_pg_size::MAC_AX_WDE_PG_256
* Please Place Description here.
*/
enum mac_ax_wde_pg_size {
MAC_AX_WDE_PG_64 = 64,
MAC_AX_WDE_PG_128 = 128,
MAC_AX_WDE_PG_256 = 256
};
/**
* @enum mac_ax_ple_pg_size
*
* @brief mac_ax_ple_pg_size
*
* @var mac_ax_ple_pg_size::MAC_AX_PLE_PG_64
* Please Place Description here.
* @var mac_ax_ple_pg_size::MAC_AX_PLE_PG_128
* Please Place Description here.
* @var mac_ax_ple_pg_size::MAC_AX_PLE_PG_256
* Please Place Description here.
*/
enum mac_ax_ple_pg_size {
MAC_AX_PLE_PG_64 = 64,
MAC_AX_PLE_PG_128 = 128,
MAC_AX_PLE_PG_256 = 256
};
/**
* @enum mac_ax_iecam_type
*
* @brief mac_ax_iecam_type
*
* @var mac_ax_iecam_type::MAC_AX_IECAM_UNAVAL
* Please Place Description here.
* @var mac_ax_iecam_type::MAC_AX_IECAM_IESHW
* Please Place Description here.
* @var mac_ax_iecam_type::MAC_AX_IECAM_SPEOFT
* Please Place Description here.
* @var mac_ax_iecam_type::MAC_AX_IECAM_CRC
* Please Place Description here.
*/
enum mac_ax_iecam_type {
MAC_AX_IECAM_UNAVAL = 0,
MAC_AX_IECAM_IESHW = 1,
MAC_AX_IECAM_SPEOFT = 2,
MAC_AX_IECAM_CRC = 3
};
/**
* @enum mac_ax_tcpip_chksum_ofd_status
*
* @brief mac_ax_tcpip_chksum_ofd_status
*
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV4_TCP_OK
* Please Place Description here.
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV6_TCP_OK
* Please Place Description here.
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV4_UDP_OK
* Please Place Description here.
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_IPV6_UDP_OK
* Please Place Description here.
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_CHKSUM_ERR
* Please Place Description here.
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_HW_NO_SUPPORT
* Please Place Description here.
* @var mac_ax_tcpip_chksum_ofd_status::MAC_AX_CHKSUM_OFD_INVALID
* Please Place Description here.
*/
enum mac_ax_tcpip_chksum_ofd_status {
MAC_AX_CHKSUM_OFD_IPV4_TCP_OK = 0,
MAC_AX_CHKSUM_OFD_IPV6_TCP_OK = 1,
MAC_AX_CHKSUM_OFD_IPV4_UDP_OK = 2,
MAC_AX_CHKSUM_OFD_IPV6_UDP_OK = 3,
MAC_AX_CHKSUM_OFD_CHKSUM_ERR = 4,
MAC_AX_CHKSUM_OFD_HW_NO_SUPPORT = 5,
MAC_AX_CHKSUM_OFD_INVALID = 6,
};
/**
* @enum mac_ax_io_byte_sel
*
* @brief mac_ax_io_byte_sel
*
* @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_1
* Please Place Description here.
* @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_2
* Please Place Description here.
* @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_4
* Please Place Description here.
* @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_LAST
* Please Place Description here.
* @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_MAX
* Please Place Description here.
* @var mac_ax_io_byte_sel::MAC_AX_BYTE_SEL_INVALID
* Please Place Description here.
*/
enum mac_ax_io_byte_sel {
MAC_AX_BYTE_SEL_1 = 0,
MAC_AX_BYTE_SEL_2,
MAC_AX_BYTE_SEL_4,
/* keep last */
MAC_AX_BYTE_SEL_LAST,
MAC_AX_BYTE_SEL_MAX = MAC_AX_BYTE_SEL_LAST,
MAC_AX_BYTE_SEL_INVALID = MAC_AX_BYTE_SEL_LAST,
};
/**
* @enum RW_OFLD_BLOCK_ID
*
* @brief RW_OFLD_BLOCK_ID
*
* @var RW_OFLD_BLOCK_ID::RW_OFLD_UART
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_CPU_LOCAL
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_SPIC
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_RXI300
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_AXIDMA
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_HIOE
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_IDDMA
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_IPSEC
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_DMAC_CTRL
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_SCR_MACHDR
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_SCH_AIRTIME
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_SCH_CAP
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_DL_GRP_TBL
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_STA_UL_GRP_TBL
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_RX_FILTER_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_SEC_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_WOW_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_CMAC_CTRL
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_ADDR_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_BSSID_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_BA_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_BCN_IE_CAM
* Please Place Description here.
* @var RW_OFLD_BLOCK_ID::RW_OFLD_MAX
* Please Place Description here.
*/
enum RW_OFLD_BLOCK_ID {
RW_OFLD_UART = 0,
RW_OFLD_CPU_LOCAL = 1,
RW_OFLD_SPIC,
RW_OFLD_RXI300,
RW_OFLD_AXIDMA,
RW_OFLD_HIOE,
RW_OFLD_IDDMA,
RW_OFLD_IPSEC,
RW_OFLD_DMAC_CTRL,
RW_OFLD_SCR_MACHDR,
RW_OFLD_STA_SCH_AIRTIME,
RW_OFLD_STA_SCH_CAP,
RW_OFLD_STA_DL_GRP_TBL,
RW_OFLD_STA_UL_GRP_TBL,
RW_OFLD_RX_FILTER_CAM,
RW_OFLD_SEC_CAM,
RW_OFLD_WOW_CAM,
RW_OFLD_CMAC_CTRL,
RW_OFLD_ADDR_CAM,
RW_OFLD_BSSID_CAM,
RW_OFLD_BA_CAM,
RW_OFLD_BCN_IE_CAM,
RW_OFLD_MAX
};
/**
* @enum mac_ax_cca
*
* @brief mac_ax_cca
*
* @var mac_ax_cca::MAC_AX_CCA
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_SEC20_CCA
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_SEC40_CCA
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_SEC80_CCA
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_EDCCA
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_BTCCA
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_CCA_LAST
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_CCA_MAX
* Please Place Description here.
* @var mac_ax_cca::MAC_AX_CCA_INVALID
* Please Place Description here.
*/
enum mac_ax_block_tx_sel {
MAC_AX_CCA,
MAC_AX_SEC20_CCA,
MAC_AX_SEC40_CCA,
MAC_AX_SEC80_CCA,
MAC_AX_EDCCA,
MAC_AX_BTCCA,
MAC_AX_TX_NAV,
/* keep last */
MAC_AX_CCA_LAST,
MAC_AX_CCA_MAX = MAC_AX_CCA_LAST,
MAC_AX_CCA_INVALID = MAC_AX_CCA_LAST,
};
/**
* struct mac_ax_pkt_data - packet information of data type
* @hdr_len: Length of header+LLC.
* For example,
* 1. 802.11 MPDU without encryption
* HEADERwLLC_LEN = (MAC header (without IV ) + LLC ) / 2
* 2. 802.11 MPDU encryption without HW_AES_IV
* HEADERwLLC_LEN = (MAC header (without IV ) + LLC ) / 2
* 3.802.11MPDU encryption with HW_AES_IV
* HEADERwLLC_LEN = (MAC header(reserved IV length)+LLC)/2
* 4.ETHERNET II MSDU without encryption
* HEADERwLLC_LEN = (DA+SA+TYPE) /2
* 5.ETHERNET II MSDU encryption without HW_AES_IV
* HEADERwLLC_LEN = (DA+SA+TYPE) /2
* 6.ETHERNET II MSDU encryption with HW_AES_IV
* HEADERwLLC_LEN = (DA+SA+TYPE) /2
* 7.SNAP MSDU without encryption
* HEADERwLLC_LEN = (DA+SA+LEN+LLC) /2
* 8.SNAP MSDU encryption without HW_AES_IV
* HEADERwLLC_LEN = (DA+SA+LEN+LLC) /2
* 9.SNAP MSDU encryption with HW_AES_IV
* HEADERwLLC_LEN = (DA+SA+LEN+LLC) /2
* @ch: Channel index, MAC_AX_CH_DMA_CH0~MAC_AX_CH_DMA_CH11.
* @macid: MAC ID.
*/
/*--------------------Define Struct-------------------------------------*/
/**
* @struct sec_checker
* @brief sec_checker
*
* @var sec_checker::rx_desc_hw_dec
* Please Place Description here.
* @var sec_checker::rx_desc_sec_type
* Please Place Description here.
* @var sec_checker::rx_desc_icv_err
* Please Place Description here.
*/
struct sec_checker {
u8 rx_desc_hw_dec;
u8 rx_desc_sec_type;
u8 rx_desc_icv_err;
};
/**
* @struct mac_ax_delay_tx_cfg
* @brief mac_ax_delay_tx_cfg
*
* @var mac_ax_delay_tx_cfg::en
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::vovi_to_b0
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::bebk_to_b0
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::vovi_to_b1
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::bebk_to_b1
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::vovi_len_b0
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::bebk_len_b0
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::vovi_len_b1
* Please Place Description here.
* @var mac_ax_delay_tx_cfg::bebk_len_b1
* Please Place Description here.
*/
struct mac_ax_delay_tx_cfg {
enum mac_ax_delay_tx_en en;
u8 vovi_to_b0;
u8 bebk_to_b0;
u8 vovi_to_b1;
u8 bebk_to_b1;
u8 vovi_len_b0;
u8 bebk_len_b0;
u8 vovi_len_b1;
u8 bebk_len_b1;
};
/**
* @struct mac_ax_ofld_hdr
* @brief mac_ax_ofld_hdr
*
* @var mac_ax_ofld_hdr::ls
* Please Place Description here.
* @var mac_ax_ofld_hdr::masken
* Please Place Description here.
* @var mac_ax_ofld_hdr::polling
* Please Place Description here.
* @var mac_ax_ofld_hdr::rsvd1
* Please Place Description here.
* @var mac_ax_ofld_hdr::value_len
* Please Place Description here.
* @var mac_ax_ofld_hdr::ofld_id
* Please Place Description here.
* @var mac_ax_ofld_hdr::entry_num
* Please Place Description here.
* @var mac_ax_ofld_hdr::offset
* Please Place Description here.
* @var mac_ax_ofld_hdr::rsvd2
* Please Place Description here.
*/
struct mac_ax_ofld_hdr {
//Segment Hdr
u16 ls:1;
u16 masken:1;
u16 polling:1;
u16 rsvd1:2;
u16 value_len:11;
u8 ofld_id;
u8 entry_num;
u16 offset;
u16 rsvd2;
};
/**
* @struct mac_ax_outsrc_h2c_hdr
* @brief mac_ax_outsrc_h2c_hdr
*
* @var mac_ax_outsrc_h2c_hdr::h2c_class
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::h2c_func
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::seq_valid
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::seq
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::seq_stop
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::rec_ack
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::done_ack
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::rsvd1
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::content_len
* Please Place Description here.
* @var mac_ax_outsrc_h2c_hdr::rsvd2
* Please Place Description here.
*/
struct mac_ax_outsrc_h2c_hdr {
u8 h2c_class; //0x0~0x7: Phydm; 0x8~0xF: RF; 0x10~0x17: BTC
u8 h2c_func;
u8 seq_valid:1;
u8 seq:3;
u8 seq_stop:1;
u8 rec_ack:1; //Ack when receive H2C
u8 done_ack:1; //Ack when FW execute H2C cmd done
u8 rsvd1:1;
u16 content_len:12;
u16 rsvd2:4;
};
/**
* @struct mac_ax_lps_info
* @brief mac_ax_lps_info
*
* @var mac_ax_lps_info::listen_bcn_mode
* Please Place Description here.
* @var mac_ax_lps_info::awake_interval
* Please Place Description here.
* @var mac_ax_lps_info::smart_ps_mode
* Please Place Description here.
*/
struct mac_ax_lps_info {
enum mac_ax_listern_bcn_mode listen_bcn_mode;
u8 awake_interval;
enum mac_ax_smart_ps_mode smart_ps_mode;
};
/**
* @struct mac_ax_wmmps_info
* @brief mac_ax_wmmps_info
*
* @var mac_ax_wmmps_info::listen_bcn_mode
* Please Place Description here.
* @var mac_ax_wmmps_info::awake_interval
* Please Place Description here.
* @var mac_ax_wmmps_info::vo_uapsd_en
* Please Place Description here.
* @var mac_ax_wmmps_info::vi_uapsd_en
* Please Place Description here.
* @var mac_ax_wmmps_info::be_uapsd_en
* Please Place Description here.
* @var mac_ax_wmmps_info::bk_uapsd_en
* Please Place Description here.
* @var mac_ax_wmmps_info::rsvd
* Please Place Description here.
*/
struct mac_ax_wmmps_info {
enum mac_ax_listern_bcn_mode listen_bcn_mode;
u8 awake_interval;
u8 vo_uapsd_en: 1;
u8 vi_uapsd_en: 1;
u8 be_uapsd_en: 1;
u8 bk_uapsd_en: 1;
u8 rsvd: 4;
};
/**
* @struct mac_ax_err_status
* @brief mac_ax_err_status
*
* @var mac_ax_err_status::err
* Please Place Description here.
* @var mac_ax_err_status::rst_en
* Please Place Description here.
*/
struct mac_ax_err_status {
enum mac_ax_err_info err;
u8 rst_en;
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/type.h
|
C
|
agpl-3.0
| 60,503
|
# All needed files would be added to _HAL_INTFS_FILES, and it would include
# hal_g6/phy/bb and all related files in directory hal_g6/phy/bb/.
# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC
# (CONFIG_RTL*) setting are all ready!
HAL = hal_g6
ifeq ($(CONFIG_PHL_ARCH), y)
phl_path := phl/hal_g6
phl_path_d1 := $(src)/phl/$(HAL)
else
phl_path := hal_g6
phl_path_d1 := $(src)/$(HAL)
endif
# Base directory
path_halbb_d1 := $(phl_path)/phy/bb
halbb-y += $(path_halbb_d1)/halbb.o \
$(path_halbb_d1)/halbb_api.o \
$(path_halbb_d1)/halbb_rua_tbl.o \
$(path_halbb_d1)/halbb_auto_dbg.o\
$(path_halbb_d1)/halbb_cfo_trk.o \
$(path_halbb_d1)/halbb_ch_info.o \
$(path_halbb_d1)/halbb_cmn_rpt.o \
$(path_halbb_d1)/halbb_dbcc.o \
$(path_halbb_d1)/halbb_dbg.o \
$(path_halbb_d1)/halbb_dbg_cmd.o \
$(path_halbb_d1)/halbb_dfs.o \
$(path_halbb_d1)/halbb_edcca.o \
$(path_halbb_d1)/halbb_env_mntr.o \
$(path_halbb_d1)/halbb_hw_cfg.o \
$(path_halbb_d1)/halbb_init.o \
$(path_halbb_d1)/halbb_interface.o \
$(path_halbb_d1)/halbb_la_mode.o \
$(path_halbb_d1)/halbb_math_lib.o \
$(path_halbb_d1)/halbb_mp.o \
$(path_halbb_d1)/halbb_plcp_gen.o \
$(path_halbb_d1)/halbb_plcp_tx.o \
$(path_halbb_d1)/halbb_pmac_setting.o \
$(path_halbb_d1)/halbb_psd.o \
$(path_halbb_d1)/halbb_physts.o \
$(path_halbb_d1)/halbb_pwr_ctrl.o \
$(path_halbb_d1)/halbb_ra.o \
$(path_halbb_d1)/halbb_statistics.o \
$(path_halbb_d1)/halbb_ant_div.o \
$(path_halbb_d1)/halbb_dig.o \
$(path_halbb_d1)/halbb_fwofld.o \
$(path_halbb_d1)/halbb_dyn_csi_rsp.o
ifeq ($(CONFIG_RTL8852A), y)
ic := 8852a
# Level 2 directory
path_halbb_8852a := $(path_halbb_d1)/halbb_$(ic)
halbb-y += $(path_halbb_8852a)/halbb_8852a.o \
$(path_halbb_8852a)/halbb_8852a_api.o \
$(path_halbb_8852a)/halbb_hwimg_8852a.o \
$(path_halbb_8852a)/halbb_reg_cfg_8852a.o
endif
ifeq ($(CONFIG_RTL8852A), y)
ic := 8852a_2
# Level 2 directory
path_halbb_8852a_2 := $(path_halbb_d1)/halbb_$(ic)
halbb-y += $(path_halbb_8852a_2)/halbb_8852a_2.o \
$(path_halbb_8852a_2)/halbb_8852a_2_api.o \
$(path_halbb_8852a_2)/halbb_hwimg_8852a_2.o \
$(path_halbb_8852a_2)/halbb_reg_cfg_8852a_2.o
endif
ifeq ($(CONFIG_RTL8852B), y)
ic := 8852b
# Level 2 directory
path_halbb_8852b := $(path_halbb_d1)/halbb_$(ic)
halbb-y += $(path_halbb_8852b)/halbb_8852b.o \
$(path_halbb_8852b)/halbb_8852b_api.o \
$(path_halbb_8852b)/halbb_hwimg_8852b.o \
$(path_halbb_8852b)/halbb_reg_cfg_8852b.o
endif
ifeq ($(CONFIG_RTL8852C), y)
ic := 8852c
# Level 2 directory
path_halbb_8852c := $(path_halbb_d1)/halbb_$(ic)
halbb-y += $(path_halbb_8852c)/halbb_8852c.o \
$(path_halbb_8852c)/halbb_8852c_api.o \
$(path_halbb_8852c)/halbb_hwimg_8852c.o \
$(path_halbb_8852c)/halbb_reg_cfg_8852c.o
endif
_HAL_BB_FILES += $(halbb-y)
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/bb.mk
|
Makefile
|
agpl-3.0
| 2,862
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u64 pre_support_ability, one = 1;
u64 comp = 0;
u32 used = *_used;
u32 out_len = *_out_len;
u8 i;
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
pre_support_ability = bb->support_ability;
comp = bb->support_ability;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n================================\n");
if (val[0] == 100) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[Supportability] Selection\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"================================\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"00. (( %s ))RA\n",
((comp & BB_RA) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"01. (( %s ))FA_CNT\n",
((comp & BB_FA_CNT) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"02. (( %s ))RSSI_MNTR\n",
((comp & HALBB_FUN_RSVD_2) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"03. (( %s ))DFS\n",
((comp & BB_DFS) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"04. (( %s ))EDCCA\n",
((comp & BB_EDCCA) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"05. (( %s ))ENV_MNTR\n",
((comp & BB_ENVMNTR) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"06. (( %s ))CFO_TRK\n",
((comp & BB_CFO_TRK) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"07. (( %s ))PWR_CTRL\n",
((comp & BB_PWR_CTRL) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"10. (( %s ))ANT_DIV\n",
((comp & DBG_ANT_DIV) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"11. (( %s ))DIG\n",
((comp & BB_DIG) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"31. (( %s ))Dyn CSI RSP\n",
((comp & BB_DCR) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"================================\n");
} else if (val[0] == 101) {
bb->support_ability = 0;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Disable all support_ability components\n");
} else {
if (val[1] == 1) { /* @enable */
bb->support_ability |= (one << val[0]);
} else if (val[1] == 2) {/* @disable */
bb->support_ability &= ~(one << val[0]);
} else {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[Warning!!!] 1:enable, 2:disable\n");
}
}
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"pre-supportability = 0x%llx\n", pre_support_ability);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Cur-supportability = 0x%llx\n", bb->support_ability);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"================================\n");
*_used = used;
*_out_len = out_len;
}
bool halbb_sta_info_init(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info)
{
struct bb_sta_info *bb_sta;
if (!bb) {
BB_WARNING("[%s]*bb = NULL\n", __func__);
return false;
}
if (!phl_sta_info)
return false;
if (!phl_sta_info->hal_sta)
return false;
bb_sta = halbb_mem_alloc(bb, sizeof(struct bb_sta_info));
if (!bb_sta) {
BB_WARNING("*bb_sta = NULL\n");
return RTW_HAL_STATUS_BB_INIT_FAILURE;
}
phl_sta_info->hal_sta->bb_sta = (void *)bb_sta;
return true;
}
bool halbb_sta_info_deinit(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info)
{
if (!bb) {
BB_WARNING("*bb = NULL\n");
return false;
}
if (!phl_sta_info)
return false;
if (!phl_sta_info->hal_sta)
return false;
if (!phl_sta_info->hal_sta->bb_sta)
return false;
halbb_mem_free(bb, phl_sta_info->hal_sta->bb_sta, sizeof(struct bb_sta_info));
return true;
}
bool halbb_sta_info_add_entry(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info)
{
if (!bb) {
BB_WARNING("[%s]*bb = NULL\n", __func__);
return false;
}
if (!phl_sta_info)
return false;
if ((phl_sta_info->macid) >= PHL_MAX_STA_NUM)
return false;
bb->phl2bb_macid_table[phl_sta_info->macid] = (u8)phl_sta_info->macid;
bb->phl_sta_info[phl_sta_info->macid] = phl_sta_info;
return true;
}
bool halbb_sta_info_delete_entry(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info)
{
if (!bb) {
BB_WARNING("*bb = NULL\n");
return false;
}
if (!phl_sta_info)
return false;
if ((phl_sta_info->macid) >= PHL_MAX_STA_NUM)
return false;
if (!phl_sta_info->hal_sta)
return false;
if (!phl_sta_info->hal_sta->bb_sta)
return false;
bb->sta_exist[phl_sta_info->macid] = false;
bb->phl_sta_info[phl_sta_info->macid] = NULL;
return true;
}
void halbb_media_status_update(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info,
bool is_connected)
{
bb->sta_exist[phl_sta_info->macid] = is_connected;
/*Reset MA RSSI*/
if (!is_connected) {
phl_sta_info->hal_sta->rssi_stat.rssi = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_ma = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[0] = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[1] = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[2] = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_ma_path[3] = 0;
phl_sta_info->hal_sta->rssi_stat.pkt_cnt_data = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_bcn = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_bcn_ma = 0;
phl_sta_info->hal_sta->rssi_stat.pkt_cnt_bcn = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_ofdm = 0;
phl_sta_info->hal_sta->rssi_stat.rssi_cck = 0;
phl_sta_info->hal_sta->rssi_stat.snr_ma = 0;
} else {
phl_sta_info->hal_sta->rssi_stat.ma_factor = RSSI_MA_L;
phl_sta_info->hal_sta->rssi_stat.ma_factor_bcn = RSSI_MA_L;
}
}
void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal = bb->hal_com;
struct rtw_phl_stainfo_t *phl_sta;
struct rtw_rssi_info *rssi_t = NULL;
struct rtw_ra_sta_info *ra;
char dbg_buf[HALBB_SNPRINT_SIZE] = {0};
u32 val[10] = {0};
u32 tmp = 0;
u16 curr_tx_rt = 0;
u8 i = 0, j = 0;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"all\n");
return;
}
if (_os_strcmp(input[1], "all") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
" Assoc_sta_cnt=%d\n\n", hal->assoc_sta_cnt);
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
phl_sta = bb->phl_sta_info[i];
if (!is_sta_active(phl_sta))
continue;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%d][active=%d] PHL_macid=%d =====================\n",
i, phl_sta->active, phl_sta->macid);
rssi_t = &phl_sta->hal_sta->rssi_stat;
halbb_print_sign_frac_digit(bb, rssi_t->rssi_ma, 16, 5, dbg_buf, HALBB_SNPRINT_SIZE_S);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Data] rssi_avg=%s, MA=1/%02d\n",
dbg_buf, 1 << rssi_t->ma_factor);
for (j = 0; j < HALBB_MAX_PATH; j++) {
halbb_print_sign_frac_digit(bb, rssi_t->rssi_ma_path[j], 16, 5, dbg_buf, HALBB_SNPRINT_SIZE_S);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
" rssi[%d]= %s\n", j, dbg_buf);
}
halbb_print_sign_frac_digit(bb, rssi_t->rssi_bcn_ma, 16, 5, dbg_buf, HALBB_SNPRINT_SIZE_S);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Bcn] rssi_avg=%s, MA=1/%02d\n",
dbg_buf, 1 << rssi_t->ma_factor_bcn);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"rssi_cck=%02d.%d, rssi_ofdm=%02d.%d\n",
rssi_t->rssi_cck >> 1, (rssi_t->rssi_cck & 1) * 5,
rssi_t->rssi_ofdm >> 1, (rssi_t->rssi_ofdm & 1) * 5);
halbb_print_sign_frac_digit(bb, rssi_t->snr_ma, 16, 4, dbg_buf, HALBB_SNPRINT_SIZE_S);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"SNR_avg=%s dB\n", dbg_buf);
ra = &phl_sta->hal_sta->ra_info;
curr_tx_rt = (u16)(ra->rpt_rt_i.mcs_ss_idx) | ((u16)(ra->rpt_rt_i.mode) << 7);
halbb_print_rate_2_buff(bb, curr_tx_rt, ra->rpt_rt_i.gi_ltf, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Tx_Rate=%s (0x%x-%d), PER=(%d), TXBW=(%d)\n",
bb->dbg_buf, curr_tx_rt, ra->rpt_rt_i.gi_ltf,
ra->curr_retry_ratio, (20 << ra->rpt_rt_i.bw));
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"======================================\n");
}
}
}
void halbb_traffic_load_decision(struct bb_info *bb)
{
struct rtw_stats *stat = &bb->phl_com->phl_stats;
struct bb_link_info *link = &bb->bb_link_i;
u32 max_tp; /*Mbps*/
/*@---TP & Trafic-load caln---*/
link->tx_tp = KB_2_MB(stat->tx_tp_kbits);
link->rx_tp = KB_2_MB(stat->rx_tp_kbits);
link->total_tp = link->tx_tp + link->rx_tp;
max_tp = MAX_2(link->tx_tp, link->rx_tp); /*Mbps*/
BB_DBG(bb, DBG_COMMON_FLOW,
"byte_uni{tx,rx}={%llu,%llu}, byte_total{tx,rx}={%llu,%llu}\n",
stat->tx_byte_uni, stat->rx_byte_uni,
stat->tx_byte_total, stat->rx_byte_total);
BB_DBG(bb, DBG_COMMON_FLOW,
"TP_kbit{tx,rx}={%d,%d}, TP_MA{tx,rx}={%d,%d}\n",
stat->tx_tp_kbits, stat->rx_tp_kbits,
stat->tx_moving_average_tp, stat->rx_moving_average_tp);
/*@[Calculate TX/RX state]*/
if (link->tx_tp > (link->rx_tp << 1))
link->txrx_state_all = BB_TX_STATE;
else if (link->rx_tp > (link->tx_tp << 1))
link->txrx_state_all = BB_RX_STATE;
else
link->txrx_state_all = BB_BI_DIR_STATE;
/*@[Traffic load decision]*/
link->traffic_load_pre = link->traffic_load;
if (max_tp > 20) {
link->traffic_load = TRAFFIC_HIGH;
} else if (max_tp > 5) {
link->traffic_load = TRAFFIC_MID;
} else if (max_tp > 1) {
link->traffic_load = TRAFFIC_LOW;
} else if (stat->tx_tp_kbits > 100 || stat->rx_tp_kbits > 100) { /*100Kb*/
link->traffic_load = TRAFFIC_ULTRA_LOW;
} else {
link->traffic_load = TRAFFIC_NO_TP;
}
/*@[Calculate consecutive idlel time]*/
if (link->traffic_load == TRAFFIC_NO_TP)
link->consecutive_idle_time = 0;
else
link->consecutive_idle_time += HALBB_WATCHDOG_PERIOD;
}
void halbb_cmn_info_self_reset(struct bb_info *bb) {
struct bb_link_info *link = &bb->bb_link_i;
bb->bb_ch_i.rssi_max = 0;
bb->bb_ch_i.rssi_min = 0;
link->is_one_entry_only = false;
link->one_entry_macid = 0;
link->one_entry_tp = 0;
link->one_entry_tp_active_occur = false;
link->one_entry_tp_pre = 0;
link->num_linked_client_pre = 0;
link->num_active_client_pre = 0;
link->num_linked_client = 0;
link->num_active_client = 0;
}
u8 halbb_get_rssi_min(struct bb_info *bb)
{
struct rtw_hal_com_t *hal = bb->hal_com;
struct rtw_phl_stainfo_t *sta;
struct rtw_rssi_info *sta_rssi = NULL;
u8 sta_cnt = 0;
u8 rssi_min = 0xff, rssi_curr = 0;
u32 i = 0;
if (hal->assoc_sta_cnt == 0) {
BB_WARNING("[%s] assoc_sta_cnt=0\n", __func__);
return 0;
}
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
sta = bb->phl_sta_info[i];
if (!is_sta_active(sta))
continue;
BB_DBG(bb, DBG_COMMON_FLOW, "[%d] macid=%d\n", i, sta->macid);
sta_cnt++;
sta_rssi = &sta->hal_sta->rssi_stat;
if (sta_rssi->rssi != 0)
rssi_curr = sta_rssi->rssi;
else
rssi_curr = sta_rssi->rssi_bcn;
/*[RSSI min]*/
if (rssi_curr <= rssi_min) {
rssi_min = rssi_curr;
}
BB_DBG(bb, DBG_COMMON_FLOW,
"rssi_min = %d", rssi_min);
if (sta_cnt >= hal->assoc_sta_cnt)
break;
}
if (sta_cnt == 0) {
BB_WARNING("[%s] sta_cnt=0\n", __func__);
return 0;
}
return rssi_min;
}
void halbb_cmn_info_self_update(struct bb_info *bb)
{
struct rtw_hal_com_t *hal = bb->hal_com;
struct bb_link_info *link = &bb->bb_link_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
struct rtw_phl_stainfo_t *sta;
struct rtw_rssi_info *sta_rssi = NULL;
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
u8 sta_cnt = 0, num_active_client = 0;
u8 rssi_min = 0xff, rssi_max = 0, rssi_curr = 0;
u8 mcc_rssi_min[MCC_BAND_NUM], mcc_sta_cnt[MCC_BAND_NUM];
u8 j = 0, band_idx = MCC_BAND_NUM, role_ch = 0;
u32 i = 0, one_entry_macid_tmp = 0;
u32 trx_tp = 0;
u32 tp_diff = 0;
/*[Link Status Check]*/
link->is_linked = (hal->assoc_sta_cnt != 0) ? true : false;
link->first_connect = link->is_linked && !link->is_linked_pre;
link->first_disconnect = !link->is_linked && link->is_linked_pre;
link->is_linked_pre = link->is_linked;
BB_DBG(bb, DBG_COMMON_FLOW, "is_linked = %d, 1st_connect=%d, 1st_disconnect=%d, assoc_sta_cnt=%d\n",
link->is_linked, link->first_connect,
link->first_disconnect, hal->assoc_sta_cnt);
/*[Traffic load information]*/
halbb_traffic_load_decision(bb);
link->rx_rate_plurality = halbb_get_plurality_rx_rate_su(bb);
link->rx_rate_plurality_mu = halbb_get_plurality_rx_rate_mu(bb);
if (!link->is_linked) {
if (link->first_disconnect)
halbb_cmn_info_self_reset(bb);
return;
}
if (mcc_dm->mcc_status_en) {
for (i = 0; i < MCC_BAND_NUM; i++) {
mcc_rssi_min[i] = rssi_min;
mcc_sta_cnt[i] = 0;
}
}
bb->bb_ch_i.pre_rssi_min = bb->bb_ch_i.rssi_min;
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
sta = bb->phl_sta_info[i];
if (!is_sta_active(sta))
continue;
if ((dev->rfe_type >= 50) && (sta->macid == 0))
continue;
BB_DBG(bb, DBG_COMMON_FLOW, "[%d] macid=%d\n", i, sta->macid);
sta_cnt++;
if (sta_cnt == 1)
one_entry_macid_tmp = i;
trx_tp = KB_2_MB(sta->stats.tx_tp_kbits +
sta->stats.rx_tp_kbits); /*Mbit*/
sta_rssi = &sta->hal_sta->rssi_stat;
if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL) {
rssi_curr = sta_rssi->rssi_bcn;
} else {
if (sta_rssi->rssi == 0 && sta_rssi->rssi_bcn != 0)
rssi_curr = sta_rssi->rssi_bcn;
else
rssi_curr = sta_rssi->rssi;
}
if (sta_rssi->pkt_cnt_data > 100)
sta_rssi->ma_factor = RSSI_MA_H;
else if (sta_rssi->pkt_cnt_data > 20)
sta_rssi->ma_factor = RSSI_MA_M;
else if (sta_rssi->pkt_cnt_data > 5)
sta_rssi->ma_factor = RSSI_MA_L;
else
sta_rssi->ma_factor = RSSI_MA_UL;
if (sta_rssi->pkt_cnt_bcn > 5)
sta_rssi->ma_factor_bcn = RSSI_MA_L;
else
sta_rssi->ma_factor_bcn = RSSI_MA_UL;
BB_DBG(bb, DBG_COMMON_FLOW,
"pkt_cnt_data=%d, pkt_cnt_bcn=%d, ma_factor=%d, ma_factor_bcn=%d\n",
sta_rssi->pkt_cnt_data, sta_rssi->pkt_cnt_bcn,
sta_rssi->ma_factor, sta_rssi->ma_factor_bcn);
sta_rssi->pkt_cnt_data = 0;
sta_rssi->pkt_cnt_bcn = 0;
BB_DBG(bb, DBG_COMMON_FLOW,
"rssi = %d, rssi_ma = %d",
sta->hal_sta->rssi_stat.rssi,
sta->hal_sta->rssi_stat.rssi_ma);
/*[RSSI min]*/
if (rssi_curr <= rssi_min) {
bb->bb_ch_i.rssi_min = rssi_curr;
bb->bb_ch_i.rssi_min_macid = sta->macid;
rssi_min = rssi_curr;
}
/*[RSSI max]*/
if (rssi_curr >= rssi_max) {
bb->bb_ch_i.rssi_max = rssi_curr;
bb->bb_ch_i.rssi_max_macid = sta->macid;
rssi_max = rssi_curr;
}
//BB_DBG(bb, DBG_COMMON_FLOW, "TP: TRX=%d Mb/sec\n", trx_tp);
//BB_DBG(bb, DBG_COMMON_FLOW, "TP: TX=%d, RX=%d, kb/sec\n",
// sta->stats.tx_tp_kbits, sta->stats.rx_tp_kbits);
BB_DBG(bb, DBG_COMMON_FLOW,
"rssi_min = %d, rssi_max = %d", rssi_min, rssi_max);
if (mcc_dm->mcc_status_en) {
if (i == mcc_dm->softap_macid)
continue;
band_idx = MCC_BAND_NUM;
role_ch = sta->wrole->chandef.center_ch;
for (j = 0; j < MCC_BAND_NUM; j++) {
if (mcc_dm->mcc_rf_ch[j].center_ch == role_ch) {
band_idx = j;
break;
}
}
if (band_idx == MCC_BAND_NUM) {
BB_WARNING("%s, band_idx = %d", __func__,
band_idx);
continue;
}
if (rssi_curr <= mcc_rssi_min[band_idx])
mcc_rssi_min[band_idx] = rssi_curr;
mcc_sta_cnt[band_idx]++;
}
if (trx_tp > ACTIVE_TP_THRESHOLD)
num_active_client++;
if (sta_cnt >= bb->hal_com->assoc_sta_cnt)
break;
}
if (mcc_dm->mcc_status_en) {
for (i = 0; i < MCC_BAND_NUM; i++) {
mcc_dm->rssi_min[i] = mcc_rssi_min[i];
mcc_dm->sta_cnt[i] = mcc_sta_cnt[i];
}
}
link->is_one_entry_only = (hal->assoc_sta_cnt == 1) ? true : false;
if (link->is_one_entry_only) {
link->one_entry_macid = one_entry_macid_tmp;
link->one_entry_tp = trx_tp;
link->one_entry_tp_active_occur = false;
//BB_DBG(bb, DBG_COMMON_FLOW, "one_entry_tp=((%d)), one_entry_tp_pre=((%d))\n",
// link->one_entry_tp, link->one_entry_tp_pre);
if (link->one_entry_tp > link->one_entry_tp_pre &&
link->one_entry_tp_pre <= 2) {
tp_diff = link->one_entry_tp - link->one_entry_tp_pre;
if (tp_diff > link->tp_active_th)
link->one_entry_tp_active_occur = true;
}
link->one_entry_tp_pre = link->one_entry_tp;
}
link->num_linked_client_pre = link->num_linked_client;
link->num_active_client_pre = link->num_active_client;
link->num_linked_client = sta_cnt;
link->num_active_client = num_active_client;
}
void halbb_watchdog_reset(struct bb_info *bb)
{
}
void halbb_update_hal_info(struct bb_info *bb)
{
struct rtw_hal_com_t *hal = bb->hal_com;
hal->trx_stat.rx_rate_plurality = bb->bb_link_i.rx_rate_plurality;
}
void halbb_store_data(struct bb_info *bb)
{
halbb_cmn_info_rpt_store_data(bb);
}
void halbb_reset(struct bb_info *bb)
{
halbb_store_data(bb);
#ifdef HALBB_STATISTICS_SUPPORT
halbb_statistics_reset(bb);
#endif
halbb_cmn_info_rpt_reset(bb);
}
void halbb_watchdog_normal(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
halbb_cmn_info_self_update(bb);
halbb_ic_hw_setting(bb);
#ifdef HALBB_ENV_MNTR_SUPPORT
halbb_env_mntr(bb);
#endif
#ifdef HALBB_DIG_SUPPORT
halbb_dig(bb);
#endif
#ifdef HALBB_STATISTICS_SUPPORT
halbb_statistics(bb);
#endif
halbb_basic_dbg_message(bb);
halbb_physts_watchdog(bb);
if (!bb->adv_bb_dm_en) {
BB_DBG(bb, DBG_COMMON_FLOW, "Disable adv halbb dm\n");
halbb_reset(bb);
return;
}
#ifdef HALBB_EDCCA_SUPPORT
halbb_edcca(bb);
#endif
#ifdef HALBB_DFS_SUPPORT
halbb_dfs(bb);
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfo_watchdog(bb);
#endif
#ifdef HALBB_RA_SUPPORT
halbb_ra_watchdog(bb);
#endif
#ifdef HALBB_PWR_CTRL_SUPPORT
halbb_pwr_ctrl(bb);
#endif
#ifdef HALBB_LA_MODE_SUPPORT
halbb_la_re_trig_watchdog(bb);
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_antenna_diversity(bb);
#endif
halbb_update_hal_info(bb);
#ifdef HALBB_DIG_MCC_SUPPORT
halbb_mccdm_switch(bb);
#endif
/*[Rest all counter]*/
halbb_reset(bb);
}
void halbb_watchdog_low_io(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
halbb_cmn_info_self_update(bb);
halbb_ic_hw_setting_low_io(bb);
halbb_basic_dbg_message(bb);
#ifdef HALBB_DIG_SUPPORT
halbb_dig_lps(bb);
#endif
#if 0//def HALBB_EDCCA_SUPPORT
halbb_edcca(bb);
#endif
#if 0//def HALBB_DFS_SUPPORT
halbb_dfs(bb);
#endif
/*[Rest all counter]*/
halbb_reset(bb);
}
void halbb_watchdog_non_io(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
halbb_cmn_info_self_update(bb);
halbb_ic_hw_setting_non_io(bb);
halbb_basic_dbg_message(bb);
/*[Rest all counter]*/
halbb_reset(bb);
}
void halbb_watchdog(struct bb_info *bb, enum bb_watchdog_mode_t mode, enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DBCC_SUPPORT
#ifdef HALBB_DBCC_DVLP_FLAG
if (phy_idx == HW_PHY_1)
return;
#endif
bb = halbb_get_curr_bb_pointer(bb, phy_idx);
BB_DBG(bb, DBG_COMMON_FLOW, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
#endif
bb->bb_sys_up_time += BB_WATCH_DOG_PERIOD;
if ((bb->bb_sys_up_time % bb->bb_watchdog_period) != 0)
return;
if (bb->bb_dbg_i.cr_recorder_en)
BB_TRACE("[%s] up_time:%d \n", __func__, bb->bb_sys_up_time);
bb->bb_watchdog_mode = mode;
BB_DBG(bb, DBG_COMMON_FLOW, "mode=%s\n",
((mode == BB_WATCHDOG_NORMAL) ? "Normal" :
((mode == BB_WATCHDOG_LOW_IO) ? "LowIO" : "NonIO")));
/*=== [HALBB Watchdog] ===============================================*/
if (mode == BB_WATCHDOG_NORMAL) {
if(phl_is_mp_mode(bb->phl_com)) {
BB_WARNING("[%s] mode=%d", __func__,
bb->phl_com->drv_mode);
return;
}
halbb_watchdog_normal(bb, phy_idx);
} else if (mode == BB_WATCHDOG_LOW_IO) {
halbb_watchdog_low_io(bb, phy_idx);
} else { /*if (mode == BB_WATCHDOG_NON_IO)*/
halbb_watchdog_non_io(bb, phy_idx);
}
if (bb->bb_dbg_i.cr_recorder_en)
BB_TRACE("[%s] end\n", __func__);
}
void halbb_bb_cmd_notify(struct bb_info *bb, void *bb_cmd, enum phl_phy_idx phy_idx)
{
enum halbb_event_idx_t event_idx = *((enum halbb_event_idx_t *)bb_cmd);
BB_DBG(bb, DBG_COMMON_FLOW, "[%s][phy_idx=%d] event_idx=%d\n", __func__, phy_idx, event_idx);
if (event_idx == BB_EVENT_TIMER_DIG) {
#ifdef HALBB_DIG_TDMA_SUPPORT
halbb_tdmadig_io_en(bb);
#endif
} else if (event_idx == BB_EVENT_TIMER_CFO) {
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfo_acc_io_en(bb);
#endif
} else if (event_idx == BB_EVENT_TIMER_ANTDIV) {
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_antdiv_io_en(bb);
#endif
} else if (event_idx == BB_EVENT_TIMER_TDMA_CR) {
#ifdef HALBB_TDMA_CR_SUPPORT
halbb_tdma_cr_sel_io_en(bb);
#endif
} else {
BB_WARNING("[%s] event_idx=%d\n", __func__, event_idx);
}
}
u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func,
enum halbb_pause_type pause_type,
enum halbb_pause_lv_type lv,
u8 val_lehgth,
u32 *val_buf)
{
struct bb_func_hooker_info *func_t = &bb->bb_cmn_hooker->bb_func_hooker_i;
s8 *pause_lv_pre = &bb->u8_dummy;
u32 *bkp_val = &bb->u32_dummy;
u32 ori_val[5] = {0};
u64 pause_func_bitmap = (u64)BIT(pause_func);
u8 i = 0;
u8 pause_result = PAUSE_FAIL;
BB_DBG(bb, DBG_DBG_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
((pause_type == HALBB_PAUSE) ? "Pause" :
((pause_type == HALBB_RESUME) ? "Resume" :
((pause_type == HALBB_PAUSE_NO_SET) ? "Pause no_set" : "Resume_no_recovery"))),
lv, val_lehgth);
if (lv >= HALBB_PAUSE_MAX_NUM) {
BB_WARNING("[%s] LV=%d\n", __func__, lv);
return PAUSE_FAIL;
}
if (pause_func == F_CFO_TRK) {
BB_DBG(bb, DBG_DBG_API, "[CFO]\n");
if (val_lehgth > 1) {
BB_WARNING("CFO length > 1\n");
return PAUSE_FAIL;
}
ori_val[0] = (u32)(bb->bb_cfo_trk_i.crystal_cap); //which value?
pause_lv_pre = &bb->pause_lv_table.lv_cfo;
bkp_val = (u32 *)(&bb->bb_cfo_trk_i.rvrt_val);
/*@function pointer hook*/
func_t->pause_bb_dm_handler = halbb_set_cfo_pause_val;
}
#ifdef HALBB_DIG_SUPPORT
else if (pause_func == F_DIG) {
BB_DBG(bb, DBG_DBG_API, "[DIG]\n");
if (val_lehgth > DIG_PAUSE_INFO_SIZE) {
BB_WARNING("DIG length > %d\n", DIG_PAUSE_INFO_SIZE);
return PAUSE_FAIL;
}
/* {equivalent_rssi, en_pause_by_igi, en_pause_by_pd_low} */
ori_val[0] = (u32)(RSSI_MAX - bb->bb_dig_i.p_cur_dig_unit->igi_fa_rssi);
ori_val[1] = val_buf[1];
pause_lv_pre = &bb->pause_lv_table.lv_dig;
bkp_val = (u32 *)(&bb->bb_dig_i.rvrt_val);
/*@function pointer hook*/
func_t->pause_bb_dm_handler = halbb_set_dig_pause_val;
}
#endif
#ifdef HALBB_EDCCA_SUPPORT
else if (pause_func == F_EDCCA) {
BB_DBG(bb, DBG_DBG_API, "[EDCCA]\n");
if (val_lehgth > 1) {
BB_WARNING("EDCCA length > 1\n");
return PAUSE_FAIL;
}
ori_val[0] = (u32)(bb->bb_edcca_i.th_h);
pause_lv_pre = &bb->pause_lv_table.lv_edcca;
bkp_val = (u32 *)(&bb->bb_edcca_i.rvrt_val);
/*@function pointer hook*/
func_t->pause_bb_dm_handler = halbb_set_edcca_pause_val;
}
#endif
else {
BB_WARNING("Error func idx\n");
return PAUSE_FAIL;
}
BB_DBG(bb, DBG_DBG_API, "Pause_LV{new , pre} = {%d ,%d}\n",
lv, *pause_lv_pre);
if (pause_type == HALBB_PAUSE || pause_type == HALBB_PAUSE_NO_SET) {
if (lv <= *pause_lv_pre) {
BB_DBG(bb, DBG_DBG_API, "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
return PAUSE_FAIL;
}
if (!(bb->pause_ability & pause_func_bitmap)) {
for (i = 0; i < val_lehgth; i++)
bkp_val[i] = ori_val[i];
}
bb->pause_ability |= pause_func_bitmap;
BB_DBG(bb, DBG_DBG_API, "pause_ability=0x%llx\n", bb->pause_ability);
if (pause_type == HALBB_PAUSE) {
for (i = 0; i < val_lehgth; i++)
BB_DBG(bb, DBG_DBG_API,
"[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
i, val_buf[i], bkp_val[i]);
func_t->pause_bb_dm_handler(bb, val_buf, val_lehgth);
} else {
for (i = 0; i < val_lehgth; i++)
BB_DBG(bb, DBG_DBG_API,
"[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
i, bkp_val[i]);
}
*pause_lv_pre = lv;
pause_result = PAUSE_SUCCESS;
} else if (pause_type == HALBB_RESUME) {
if (lv < *pause_lv_pre) {
BB_DBG(bb, DBG_DBG_API, "[Resume FAIL] Pre_LV >= Curr_LV\n");
return PAUSE_FAIL;
}
if ((bb->pause_ability & pause_func_bitmap) == 0) {
BB_DBG(bb, DBG_DBG_API, "[RESUME] No Need to Revert\n");
return PAUSE_SUCCESS;
}
bb->pause_ability &= ~pause_func_bitmap;
BB_DBG(bb, DBG_DBG_API, "pause_ability=0x%llx\n", bb->pause_ability);
*pause_lv_pre = HALBB_PAUSE_RELEASE;
for (i = 0; i < val_lehgth; i++) {
BB_DBG(bb, DBG_DBG_API,
"[RESUME] val_idx[%d]={0x%x}\n", i, bkp_val[i]);
}
func_t->pause_bb_dm_handler(bb, bkp_val, val_lehgth);
pause_result = PAUSE_SUCCESS;
} else if (pause_type == HALBB_RESUME_NO_RECOVERY) {
if (lv < *pause_lv_pre) {
BB_DBG(bb, DBG_DBG_API, "[Resume FAIL] Pre_LV >= Curr_LV\n");
return PAUSE_FAIL;
}
if ((bb->pause_ability & pause_func_bitmap) == 0) {
BB_DBG(bb, DBG_DBG_API, "[RESUME] No Need to Revert\n");
return PAUSE_SUCCESS;
}
bb->pause_ability &= ~pause_func_bitmap;
BB_DBG(bb, DBG_DBG_API, "pause_ability=0x%llx\n", bb->pause_ability);
*pause_lv_pre = HALBB_PAUSE_RELEASE;
pause_result = PAUSE_SUCCESS;
} else {
BB_WARNING("error pause_type\n");
pause_result = PAUSE_FAIL;
}
return pause_result;
}
void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 i;
u8 len = 0;
u32 buf[5] = {0};
u8 pause_result = 0;
enum halbb_pause_type type = 0;
enum halbb_pause_lv_type lv = 0;
u8 halbb_ary_size = bb->bb_cmn_hooker->bb_dm_number;
enum habb_fun_t id = F_DEFAULT;
/* ==== [Help] ====]*/
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{Func} {p:pause, pn:pause_no_set, r:Resume, rnc: Resume_no_recov} {lv:0~3} Val[0],...,Val[5]\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{dig} {p/pn/r} {lv} {Pwr(|dBm|),hex} {0:apply to ofdm, 1:apply to cck and ofdm}\n");
for (i = 0; i < halbb_ary_size; i++)
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"*%s\n", halbb_func_i[i].name);
return;
}
/* ==== [Function] ====]*/
for (i = 0; i < halbb_ary_size; i++) {
if (_os_strcmp(halbb_func_i[i].name, input[1]) == 0) {
id = halbb_func_i[i].id;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%s]===>\n", halbb_func_i[i].name);
break;
}
}
if (i == halbb_ary_size) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Func not found!\n");
return;
}
/* ==== [Type] ====]*/
if (_os_strcmp(input[2], "p") == 0) {
type = HALBB_PAUSE;
} else if (_os_strcmp(input[2], "pn") == 0) {
type = HALBB_PAUSE_NO_SET;
} else if (_os_strcmp(input[2], "r") == 0) {
type = HALBB_RESUME;
} else if (_os_strcmp(input[2], "rnc") == 0) {
type = HALBB_RESUME_NO_RECOVERY;
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
for (i = 1; i < 10; i++) {
HALBB_SCAN(input[i + 1], DCMD_HEX, &val[i]);
}
lv = (enum halbb_pause_lv_type)val[2];
for (i = 0; i < 5; i++)
buf[i] = val[3 + i];
if (id == F_CFO_TRK) {
len = 1;
} else if (id == F_DIG) {
len = DIG_PAUSE_INFO_SIZE;
} else if (id == F_EDCCA) {
len = 1;
} else {
return;
}
if (len) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{%s in lv=%d}, pause_val = {%d, %d}\n",
((type == HALBB_PAUSE) ? "Pause" :
((type == HALBB_RESUME) ? "Resume" : "Pause no set")),
lv, val[3], val[4]);
pause_result = halbb_pause_func(bb, id, type, lv, len, buf);
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set %s\n", (pause_result) ? "Success" : "Fail");
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb.c
|
C
|
agpl-3.0
| 29,431
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_H__
#define __HALBB_H__
/*@--------------------------[Define] ---------------------------------------*/
#define ACTIVE_TP_THRESHOLD 1
#define BB_WATCH_DOG_PERIOD 2 /*sec*/
#define is_sta_active(sta) ((sta) && (sta->active))
#define HALBB_SNPRINT_SIZE 200
#define HALBB_SNPRINT_SIZE_S 20
#define BB_EFUSE_BAND_NUM 5
#define IC_LNA_NUM 7
#define IC_TIA_NUM 2
#define EFUSE_OFST_NUM 1
/*@--------------------------[Enum]------------------------------------------*/
enum bb_trx_state_t {
BB_TX_STATE = 0,
BB_RX_STATE = 1,
BB_BI_DIR_STATE = 2
};
enum bb_trafic_t {
TRAFFIC_NO_TP = 0,
TRAFFIC_ULTRA_LOW = 1,
TRAFFIC_LOW = 2,
TRAFFIC_MID = 3,
TRAFFIC_HIGH = 4
};
enum efuse_bit_mask {
LOW_MASK = 0,
HIGH_MASK = 1
};
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_pause_lv {
s8 lv_dig;
s8 lv_cfo;
s8 lv_edcca;
};
struct bb_func_hooker_info {
void (*pause_bb_dm_handler)(struct bb_info *bb, u32 *val_buf, u8 val_len);
};
struct bb_iot_info {
u8 is_linked_cmw500:1;
u8 patch_id_00000000:1;
u8 rsvd:6;
};
struct bb_path_info {
/*[Path info]*/
u8 tx_path_en; /*TX path enable*/
u8 rx_path_en; /*RX path enable*/
#ifdef HALBB_COMPILE_ABOVE_4SS
enum bb_path tx_4ss_path_map; /*@Use N-X for 4STS rate*/
#endif
#ifdef HALBB_COMPILE_ABOVE_3SS
enum bb_path tx_3ss_path_map; /*@Use N-X for 3STS rate*/
#endif
#ifdef HALBB_COMPILE_ABOVE_2SS
enum bb_path tx_2ss_path_map; /*@Use N-X for 2STS rate*/
#endif
enum bb_path tx_1ss_path_map; /*@Use N-X for 1STS rate*/
};
struct bb_link_info {
/*[Link Info]*/
bool is_linked;
bool is_linked_pre;
bool first_connect;
bool first_disconnect;
enum bb_trx_state_t txrx_state_all;
/*[One Entry TP Info]*/
bool is_one_entry_only;
u32 one_entry_macid;
u32 one_entry_tp;
u32 one_entry_tp_pre;
u16 tp_active_th;
bool one_entry_tp_active_occur;
bool is_match_bssid;
/*[Client Number]*/
u8 num_linked_client;
u8 num_linked_client_pre;
u8 num_active_client;
u8 num_active_client_pre;
/*[TP & Traffic]*/
u8 traffic_load;
u8 traffic_load_pre;
u16 tx_rate;
u16 rx_rate_plurality;
u16 rx_rate_plurality_mu;
u32 tx_tp; /*@Mbps*/
u32 rx_tp; /*@Mbps*/
u32 total_tp; /*@Mbps*/
u16 consecutive_idle_time; /*@unit: second*/
};
struct bb_ch_info {
u8 rssi_min;
u16 rssi_min_macid;
u8 pre_rssi_min;
u8 rssi_max;
u16 rssi_max_macid;
u8 rxsc_160;
u8 rxsc_80;
u8 rxsc_40;
u8 rxsc_20;
u8 rxsc_l;
u8 is_noisy;
u8 rf_central_ch_cfg; /*report in phy-sts*/
};
struct bb_cmn_backup_info {
u8 cur_tx_path;
u8 cur_rx_path;
s16 cur_tx_pwr;
u8 cur_pd_lower_bound;
u8 last_rssi;
struct rssi_physts last_rssi_rpt;
struct rxevm_physts last_rxevm_rpt;
};
struct bb_gain_info {
s8 lna_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
s8 tia_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_TIA_NUM];
s8 efuse_ofst[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][EFUSE_OFST_NUM];
s8 rpl_ofst_20[BB_GAIN_BAND_NUM][HALBB_MAX_PATH];
s8 rpl_ofst_40[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_40];
s8 rpl_ofst_80[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_80];
};
struct bb_efuse_info{
bool normal_efuse_check;
bool hidden_efuse_check;
s8 gain_offset[HALBB_MAX_PATH][BB_EFUSE_BAND_NUM]; // S(8,0)
s8 gain_cs[HALBB_MAX_PATH][BB_GAIN_BAND_NUM]; // S(8,0)
s8 gain_cg[HALBB_MAX_PATH][BB_GAIN_BAND_NUM]; // S(8,0)
s8 lna_err_2g[HALBB_MAX_PATH][7]; // S(6,2)
s8 lna_err_5g[HALBB_MAX_PATH][7]; // S(6,2)
s8 frontend_loss[HALBB_MAX_PATH];
s8 rpl_bias_comp[HALBB_MAX_PATH];
s8 rssi_bias_comp[HALBB_MAX_PATH];
s8 efuse_ofst; // 8852A:S(5,2) 8852B:S(8,4)
s8 efuse_ofst_tb; // 8852A:S(7,4) 8852B:S(8,4)
};
struct bb_cmn_info {
u8 bb_dm_number;
#ifdef HALBB_PSD_SUPPORT
struct bb_psd_info bb_psd_i;
#endif
#ifdef HALBB_LA_MODE_SUPPORT
struct bb_la_mode_info bb_la_mode_i;
#endif
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
struct bf_ch_raw_info bf_ch_raw_i;
#endif
struct bb_echo_cmd_info bb_echo_cmd_i;
struct bb_func_hooker_info bb_func_hooker_i;
};
#ifdef HALBB_DIG_MCC_SUPPORT
#define PD_IDX_MIN 0
#define NUM_MAX_IGI_CNT 7
#define INVALID_INIT_VAL 0xff
/*For 2G/5G/6G*/
enum mcc_band {
MCC_BAND_1 = 0,
MCC_BAND_2,
MCC_BAND_NUM
};
struct halbb_mcc_dm {
bool mcc_pre_status_en;
u8 mcc_reg_id[NUM_MAX_IGI_CNT];
u8 sta_cnt[MCC_BAND_NUM];
u16 mcc_dm_reg[NUM_MAX_IGI_CNT];
u16 mcc_dm_mask[NUM_MAX_IGI_CNT];
u16 mcc_dm_val[NUM_MAX_IGI_CNT][MCC_BAND_NUM];
/*mcc DIG*/
u8 rssi_min[MCC_BAND_NUM];
/* need to be config by driver*/
bool mcc_status_en;
u8 softap_macid;
struct rtw_chan_def mcc_rf_ch[MCC_BAND_NUM];
};
/**
* @struct _mcc_h2c_
* @brief _mcc_h2c_
*
*/
struct mcc_h2c_reg_content {
// MCCDM
u8 addr_lsb;
u8 addr_msb;
u8 bmask_lsb;
u8 bmask_msb;
u8 val_lsb;
u8 val_msb;
};
struct mcc_h2c {
// MCCDM
u8 reg_cnt;
u8 mcc_dm_en: 1;
u8 mcc_ch_idx: 1;
u8 mcc_set: 1;
u8 phy0_en: 1;
u8 phy1_en: 1;
u8 rsvd0: 3;
u8 ch_lsb;
u8 ch_msb;
struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_IGI_CNT];
};
#endif
struct bb_info {
struct rtw_phl_com_t *phl_com;
struct rtw_hal_com_t *hal_com;
struct rtw_phl_stainfo_t *phl_sta_info[PHL_MAX_STA_NUM];
u8 phl2bb_macid_table[PHL_MAX_STA_NUM];
bool sta_exist[PHL_MAX_STA_NUM];
/*[DBCC]*/
#ifdef HALBB_DBCC_SUPPORT
struct bb_info *bb_phy_hooker;
#endif
enum phl_phy_idx bb_phy_idx;
struct bb_cmn_info *bb_cmn_hooker;
/*[Common Info]*/
struct bb_gain_info bb_gain_i;
struct bb_efuse_info bb_efuse_i;
enum bb_ic_t ic_type;
enum bb_cr_t cr_type;
u8 num_rf_path;
/*[System Info]*/
enum bb_watchdog_mode_t bb_watchdog_mode;
bool bb_cmn_info_init_ready;
bool bb_dm_init_ready;
u32 bb_sys_up_time;
bool bb_watchdog_en;
u8 bb_watchdog_period; /*2s, 4s, 8s...,254s*/
bool bb_ic_api_en;
u8 pre_dbg_priority;
char dbg_buf[HALBB_SNPRINT_SIZE];
/*[DM Info]*/
bool is_noisy;
bool adv_bb_dm_en;
u64 support_ability; /*HALBB function Supportability*/
u64 manual_support_ability;
u64 pause_ability; /*HALBB function pause Supportability*/
struct halbb_pause_lv pause_lv_table;
/*[FW Info]*/
u8 fwofld_last_cmd;
u64 fw_dbg_component;
/*[Drv Dbg Info]*/
u64 dbg_component;
u8 cmn_dbg_msg_period;
u8 cmn_dbg_msg_cnt;
bool is_disable_phy_api;
/*[Dummy]*/
bool bool_dummy;
u8 u8_dummy;
u16 u16_dummy;
u32 u32_dummy;
/*[Link Info]*/
enum rf_path tx_path; /*PMAC Tx Path*/
enum rf_path rx_path;
/*@=== [HALBB Structure] ============================================*/
#ifdef BB_8852A_CAV_SUPPORT
struct bb_8852a_info bb_8852a_i;
#endif
#ifdef BB_8852A_2_SUPPORT
struct bb_8852a_2_info bb_8852a_2_i;
struct bb_h2c_fw_cmw bb_fw_cmw_i;
#endif
#ifdef HALBB_RA_SUPPORT
struct bb_ra_info bb_ra_i[PHL_MAX_STA_NUM];
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
struct bb_env_mntr_info bb_env_mntr_i;
#endif
#ifdef HALBB_EDCCA_SUPPORT
struct bb_edcca_info bb_edcca_i;
#endif
#ifdef HALBB_DFS_SUPPORT
struct bb_dfs_info bb_dfs_i;
#endif
#ifdef HALBB_STATISTICS_SUPPORT
struct bb_stat_info bb_stat_i;
#endif
#ifdef HALBB_DIG_SUPPORT
struct bb_dig_info bb_dig_i;
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
struct bb_cfo_trk_info bb_cfo_trk_i;
#endif
#ifdef HALBB_PHYSTS_PARSING_SUPPORT
struct bb_physts_info bb_physts_i;
#endif
#ifdef HALBB_LA_MODE_SUPPORT
struct bb_la_mode_info bb_la_mode_i;
#endif
#ifdef HALBB_PWR_CTRL_SUPPORT
struct bb_pwr_ctrl_info bb_pwr_ctrl_i;
struct bb_dyncca_info bb_dyncca_i;
#endif
#ifdef HALBB_PMAC_TX_SUPPORT
struct bb_plcp_info bb_plcp_i;
#endif
struct bb_link_info bb_link_i;
struct bb_path_info bb_path_i;
struct bb_ch_info bb_ch_i;
struct bb_api_info bb_api_i;
struct bb_iot_info bb_iot_i;
struct bb_dbg_info bb_dbg_i;
struct bb_c2h_fw_tx_rpt bb_fwtx_c2h_i;
struct bb_h2c_fw_tx_setting bb_fwtx_h2c_i;
struct bb_h2c_fw_edcca bb_fw_edcca_i;
struct bb_h2c_he_sigb bb_h2c_he_sigb_i;
struct bb_fw_dbg_cmn_info bb_fwdbg_i;
struct bb_cmn_rpt_info bb_cmn_rpt_i;
struct bb_rpt_info bb_rpt_i;
struct rxevm_physts rxevm;
struct bb_cmn_backup_info bb_cmn_backup_i;
#ifdef HALBB_CH_INFO_SUPPORT
struct bb_ch_rpt_info bb_ch_rpt_i;
#endif
#ifdef HALBB_AUTO_DBG_SUPPORT
struct bb_auto_dbg_info bb_auto_dbg_i;
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
struct bb_antdiv_info bb_ant_div_i;
#endif
#ifdef HALBB_DYN_L2H_SUPPORT
struct bb_dyn_l2h_info bb_dyn_l2h_i;
#endif
/*@=== [HALBB Timer] ================================================*/
#ifdef HALBB_RUA_SUPPORT
/*struct rtw_rua_tbl rtw_rua_t;*/
#endif
#ifdef HALBB_DIG_MCC_SUPPORT
struct halbb_mcc_dm mcc_dm;
#endif
};
/*@--------------------------[Prptotype]-------------------------------------*/
u8 halbb_get_rssi_min(struct bb_info *bb);
void halbb_cmn_info_self_reset(struct bb_info *bb);
void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb.h
|
C
|
agpl-3.0
| 10,094
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852B_SUPPORT
bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver)
{
bool valid = true;
#if 0
if (bb_ver >= X && rf_ver >= Y)
valid = true;
else if (bb_ver < X && rf_ver < Y)
valid = true;
else
valid = false;
#endif
if (!valid) {
/*halbb_set_reg(bb, 0x1c3c, (BIT(0) | BIT(1)), 0x0);*/
BB_WARNING("[%s] Pkg_ver{bb, rf}={%d, %d} disable all BB block\n",
__func__, bb_ver, rf_ver);
}
return valid;
}
void halbb_stop_pmac_tx_8852b(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
if (tx_info->is_cck) { // CCK
if (tx_info->mode == CONT_TX) {
halbb_set_reg(bb, 0x2300, BIT(26), 1);
halbb_set_reg(bb, 0x2338, BIT(17), 0);
halbb_set_reg(bb, 0x2300, BIT(28), 0);
halbb_set_reg(bb, 0x2300, BIT(26), 0);
} else if (tx_info->mode == PKTS_TX) {
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
}
} else { // OFDM
if (tx_info->mode == CONT_TX)
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx);
else if (tx_info->mode == PKTS_TX)
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
}
}
void halbb_start_pmac_tx_8852b(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum halbb_pmac_mode mode, u32 pkt_cnt,u16 period,
enum phl_phy_idx phy_idx)
{
if (mode == CONT_TX) {
if (tx_info->is_cck) {
halbb_set_reg(bb, 0x2338, BIT(17), 1);
halbb_set_reg(bb, 0x2300, BIT(28), 0);
} else {
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx);
}
} else if (mode == PKTS_TX) {
/*Tx_N_PACKET_EN */
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
/*Tx_N_PERIOD */
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
/*Tx_N_PACKET */
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
} else if (mode == CCK_CARRIER_SIPPRESSION_TX) {
if (tx_info->is_cck) {
/*Carrier Suppress Tx*/
halbb_set_reg(bb, 0x2338, BIT(18), 1);
/*Disable scrambler at payload part*/
halbb_set_reg(bb, 0x2304, BIT(26), 1);
} else {
return;
}
/*Tx_N_PACKET_EN */
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
/*Tx_N_PERIOD */
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
/*Tx_N_PACKET */
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
}
/*Tx_EN */
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 0, phy_idx);
}
void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (!tx_info->en_pmac_tx) {
halbb_stop_pmac_tx_8852b(bb, tx_info, phy_idx);
/* PD hit enable */
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx);
halbb_set_reg(bb, 0x2344, BIT(31), 0);
return;
}
/*Turn on PMAC */
/* Tx */
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 1, phy_idx);
/* Rx */
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x0988, 0x3f, 0x3f, phy_idx);
/* PD hit enable */
halbb_set_reg(bb, 0x704, BIT(1), 0);
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx);
halbb_set_reg(bb, 0x2344, BIT(31), 1);
halbb_set_reg(bb, 0x704, BIT(1), 1);
halbb_start_pmac_tx_8852b(bb, tx_info, tx_info->mode, tx_info->tx_cnt,
tx_info->period, phy_idx);
}
void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
/* To do: 0x0d80[16] [25] / 0x0d88[5:0] Should be set to default value in parameter package*/
/* Turn on TMAC */
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0988, 0xfff, 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0994, 0xf0, 0, phy_idx);
// PDP bypass from TMAC
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 0, phy_idx);
// TMAC Tx path
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0, phy_idx);
// TMAC Tx power
halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 0, phy_idx);
}
void halbb_ic_hw_setting_init_8852b(struct bb_info *bb)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if(phl_is_mp_mode(bb->phl_com)) {
// r_en_sound_wo_ndp
halbb_set_reg(bb, 0xd7c, BIT(1), 1);
halbb_set_reg(bb, 0x2d7c, BIT(1), 1);
} else {
// r_en_sound_wo_ndp
halbb_set_reg(bb, 0xd7c, BIT(1), 0);
halbb_set_reg(bb, 0x2d7c, BIT(1), 0);
}
}
bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx)
{
/*
Range of bound value:
BW20: 95~33
BW40: 92~30
BW80: 89~27
*/
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 7;
u8 bound_idx = 0;
bool rpt = true;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bound == 0) {
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Set Boundary to default!\n");
return true;
}
bb->bb_cmn_backup_i.cur_pd_lower_bound = bound;
if (bw == CHANNEL_WIDTH_20) {
bw_attenuation = 0;
} else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
} else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
} else {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Only support BW20/40/80 !\n");
return false;
}
bound += (bw_attenuation + subband_filter_atteniation);
// If Boundary dbm is odd, set it to even number
bound = bound % 2 ? bound + 1 : bound;
if (bound < 40) {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Threshold too high, set to highest level!\n");
bound = 40;
rpt = false;
}
if (bound > 102) {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Threshold too low, disable PD lower bound function!\n");
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx);
return true;
}
bound_idx = (102 - bound) >> 1;
halbb_set_reg_cmn(bb, 0x4860, 0x7c0, bound_idx, phy_idx);
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 1, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set Boundary Success!\n");
return rpt;
}
bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx)
{
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 5;
s8 bound_tmp = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bb->hal_com->cv < CBV) {
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] CCK pd_lower_bound CV not support!\n");
return false;
}
if (bound == 0) {
halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Set Boundary to default!\n");
return true;
}
if (bw == CHANNEL_WIDTH_20) {
bw_attenuation = 0;
}
else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
}
else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
}
else {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Only support BW20/40/80 !\n");
return true;
}
bound += (bw_attenuation + subband_filter_atteniation);
bound_tmp = (-1) * MIN_2(bound, 128);
halbb_set_reg_cmn(bb, 0x23b0, 0xff000000, bound_tmp, phy_idx);
halbb_set_reg_cmn(bb, 0x23b4, 0xff000000, 0x7f, phy_idx);
halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 1, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set CCK Boundary Success!\n");
return true;
}
u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info, enum phl_phy_idx phy_idx)
{
u8 tmp;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (get_en_info)
tmp = (u8)halbb_get_reg_cmn(bb, 0x4860, BIT(30), phy_idx);
else
tmp = bb->bb_cmn_backup_i.cur_pd_lower_bound;
return tmp;
}
void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (en) {
halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 1, phy_idx);
} else {
halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 0, phy_idx);
}
}
bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
bool en;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
en = (bool)halbb_get_reg_cmn(bb, 0x47D4, BIT(8), phy_idx);
return en;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.c
|
C
|
agpl-3.0
| 8,939
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_H__
#define __HALBB_8852B_H__
#ifdef BB_8852B_SUPPORT
#include "../halbb_pmac_setting_ex.h"
struct bb_info;
bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver);
void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx);
void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_ic_hw_setting_init_8852b(struct bb_info *bb);
bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx);
u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info,
enum phl_phy_idx phy_idx);
void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
#endif
#endif /* __HALBB_8852b_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b.h
|
C
|
agpl-3.0
| 2,013
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852B_SUPPORT
bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb,
s16 pw_ofst, enum phl_phy_idx phy_idx)
{
/*S(5,0) for 8852A/8852B*/
if (pw_ofst < -16 || pw_ofst > 15) {
BB_WARNING("[%s] ofst=%d\n", __func__, pw_ofst);
return false;
}
/*ECO en*/
rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1);
/*1 TX*/
rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst);
/*2 TX*/
if (pw_ofst < -13)
pw_ofst = -13;
rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3);
return true;
}
void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx,
enum phl_phy_idx phy_idx) {
halbb_set_reg(bb, 0x4494, 0x3000000, shape_idx);
/*0:0dB 1:-4dB 2:-5dB 3:-6dB*/
}
void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx,
enum phl_phy_idx phy_idx) {
u32 para_flat[8] = {0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5};
u32 para_sharp[8] = {0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5};
u32 para_sharp_14[8] = {0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A};
u32 *para = NULL;
u8 i = 0;
BB_DBG(bb, DBG_DBG_API, "[%s] ch=%d, shape_idx=%d\n", __func__, ch, shape_idx);
if (ch > 14)
return;
if (ch == 14) {
para = para_sharp_14;
} else {
if (shape_idx == 0) {
/*flat CH1~14*/
para = para_flat;
} else {
/*Sharp( b mode tx dfir)*/
para = para_sharp;
}
}
for (i = 0; i < 8; i++) {
halbb_set_reg_cmn(bb, 0x2300 + (i << 2), MASKDWORD, para[i], phy_idx);
BB_DBG(bb, DBG_DBG_API, "Reg0x%08x = 0x%08x\n", 0x2300 + (i << 2), para[i]);
}
}
void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
// === [TSSI protect on] === //
halbb_set_reg(bb, 0x58dc, BIT(30), 0x1);
halbb_set_reg(bb, 0x5818, BIT(30), 0x1);
halbb_set_reg(bb, 0x78dc, BIT(30), 0x1);
halbb_set_reg(bb, 0x7818, BIT(30), 0x1);
// === [BB reset] === //
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
// === [TSSI protect off] === //
halbb_set_reg(bb, 0x58dc, BIT(30), 0x0);
halbb_set_reg(bb, 0x5818, BIT(30), 0x0);
halbb_set_reg(bb, 0x78dc, BIT(30), 0x0);
halbb_set_reg(bb, 0x7818, BIT(30), 0x0);
}
void halbb_dfs_en_8852b(struct bb_info *bb, bool en)
{
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
if (en)
halbb_set_reg(bb, 0x0, BIT(31), 1);
else
halbb_set_reg(bb, 0x0, BIT(31), 0);
}
void halbb_adc_en_8852b(struct bb_info *bb, bool en)
{
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
if (en)
halbb_set_reg(bb, 0x20fc, 0xff000000, 0x0);
else
halbb_set_reg(bb, 0x20fc, 0xff000000, 0xf);
}
void halbb_tssi_cont_en_8852b(struct bb_info *bb, bool en, enum rf_path path)
{
u32 tssi_trk_man[2] = {0x5818, 0x7818};
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
if (en) {
halbb_set_reg(bb, tssi_trk_man[path], BIT(30), 0x0);
rtw_hal_rf_tssi_scan_ch(bb->hal_com, HW_PHY_0, path);
} else {
halbb_set_reg(bb, tssi_trk_man[path], BIT(30), 0x1);
}
}
void halbb_bb_reset_all_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
//Protest SW-SI
halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx);
halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx);
halbb_delay_us(bb, 1);
// === [BB reset] === //
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx);
halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx);
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
}
void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
if (en) {
halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx);
halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx);
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
//PD Enable
if(bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G)
halbb_set_reg(bb,0x2344, BIT(31), 0x0);
halbb_set_reg(bb,0xc3c, BIT(9), 0x0);
} else {
//PD Disable
halbb_set_reg(bb,0x2344, BIT(31), 0x1);
halbb_set_reg(bb,0xc3c, BIT(9), 0x1);
//Protest SW-SI
halbb_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx);
halbb_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx);
halbb_delay_us(bb, 1);
halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx);
}
}
u32 halbb_read_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask)
{
u8 path_tmp=0;
u32 i = 0, j = 0, readback_value = INVALID_RF_DATA, r_reg = 0;
bool is_r_busy = true, is_w_busy = true, is_r_done = false;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
while (is_w_busy || is_r_busy) {
is_w_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(24));
is_r_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(25));
halbb_delay_us(bb, 1);
/*BB_WARNING("[%s] is_w_busy = %d, is_r_busy = %d\n",
__func__, is_w_busy, is_r_busy);*/
i++;
if (i > 30)
break;
}
if (is_w_busy || is_r_busy) {
BB_WARNING("[%s] is_w_busy = (%d), is_r_busy = (%d)\n",
__func__, is_w_busy, is_r_busy);
return INVALID_RF_DATA;
}
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return INVALID_RF_DATA;
}
/*==== Calculate offset ====*/
path_tmp = (u8)path & 0x7;
reg_addr &= 0xff;
/*==== RF register only has 20bits ====*/
bit_mask &= RFREGOFFSETMASK;
r_reg = (path_tmp << 8 | reg_addr) & 0x7ff;
halbb_set_reg(bb, 0x378, 0x7ff, r_reg);
halbb_delay_us(bb, 2);
/*==== Read RF register ====*/
while (!is_r_done) {
is_r_done = (bool)halbb_get_reg(bb, 0x174c, BIT(26));
halbb_delay_us(bb, 1);
j++;
if (j > 30)
break;
}
if (is_r_done) {
readback_value = halbb_get_reg(bb, 0x174c, bit_mask);
} else {
BB_WARNING("[%s] is_r_done = (%d)\n", __func__, is_r_done);
return INVALID_RF_DATA;
}
BB_DBG(bb, DBG_PHY_CONFIG, "A die RF-%d 0x%x = 0x%x, bit mask = 0x%x, i=%x, j =%x\n",
path_tmp, reg_addr, readback_value, bit_mask,i,j);
return readback_value;
}
u32 halbb_read_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask)
{
u32 readback_value = 0, direct_addr = 0;
u32 offset_read_rf[2] = {0xe000, 0xf000};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return INVALID_RF_DATA;
}
/*==== Calculate offset ====*/
reg_addr &= 0xff;
direct_addr = offset_read_rf[path] + (reg_addr << 2);
/*==== RF register only has 20bits ====*/
bit_mask &= RFREGOFFSETMASK;
/*==== Read RF register directly ====*/
readback_value = halbb_get_reg(bb, direct_addr, bit_mask);
BB_DBG(bb, DBG_PHY_CONFIG, "D die RF-%d 0x100%x = 0x%x, bit mask = 0x%x\n",
path, reg_addr, readback_value, bit_mask);
return readback_value;
}
u32 halbb_read_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask)
{
u32 readback_value = INVALID_RF_DATA;
enum rtw_dv_sel ad_sel = (enum rtw_dv_sel)((reg_addr & 0x10000) >> 16);
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return INVALID_RF_DATA;
}
if (ad_sel == DAV) {
readback_value = halbb_read_rf_reg_8852b_a(bb, path, reg_addr,
bit_mask);
/*BB_DBG(bb, DBG_PHY_CONFIG, "A-die RF-%d 0x%x = 0x%x, bit mask = 0x%x\n",
path, reg_addr, readback_value, bit_mask);*/
} else if (ad_sel == DDV) {
readback_value = halbb_read_rf_reg_8852b_d(bb, path, reg_addr,
bit_mask);
/*BB_DBG(bb, DBG_PHY_CONFIG, "D-die RF-%d 0x%x = 0x%x, bit mask = 0x%x\n",
path, reg_addr, readback_value, bit_mask);*/
} else {
BB_DBG(bb, DBG_PHY_CONFIG, "Fail Read RF RF-%d 0x%x = 0x%x, bit mask = 0x%x\n",
path, reg_addr, readback_value, bit_mask);
return INVALID_RF_DATA;
}
return readback_value;
}
void halbb_5m_mask_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx)
{
bool mask_5m_low = false;
bool mask_5m_en = false;
switch (bw) {
case CHANNEL_WIDTH_40:
/* Prich=1 : Mask 5M High
Prich=2 : Mask 5M Low */
mask_5m_en = true;
mask_5m_low = pri_ch == 2 ? true : false;
break;
case CHANNEL_WIDTH_80:
/* Prich=3 : Mask 5M High
Prich=4 : Mask 5M Low
Else : Mask 5M Disable */
mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)) ? true : false;
mask_5m_low = pri_ch == 4 ? true : false;
break;
default:
mask_5m_en = false;
break;
}
BB_DBG(bb, DBG_PHY_CONFIG, "[5M Mask] pri_ch = %d, bw = %d", pri_ch, bw);
if (!mask_5m_en) {
halbb_set_reg(bb, 0x46f8, BIT(12), 0x0);
halbb_set_reg(bb, 0x47b8, BIT(12), 0x0);
halbb_set_reg_cmn(bb, 0x4440, BIT(31), 0x0, phy_idx);
} else {
if (mask_5m_low) {
halbb_set_reg(bb, 0x46f8, 0x3f, 0x4);
halbb_set_reg(bb, 0x46f8, BIT(12), 0x1);
halbb_set_reg(bb, 0x46f8, BIT(8), 0x0);
halbb_set_reg(bb, 0x46f8, BIT(6), 0x1);
halbb_set_reg(bb, 0x47b8, 0x3f, 0x4);
halbb_set_reg(bb, 0x47b8, BIT(12), 0x1);
halbb_set_reg(bb, 0x47b8, BIT(8), 0x0);
halbb_set_reg(bb, 0x47b8, BIT(6), 0x1);
} else {
halbb_set_reg(bb, 0x46f8, 0x3f, 0x4);
halbb_set_reg(bb, 0x46f8, BIT(12), 0x1);
halbb_set_reg(bb, 0x46f8, BIT(8), 0x1);
halbb_set_reg(bb, 0x46f8, BIT(6), 0x0);
halbb_set_reg(bb, 0x47b8, 0x3f, 0x4);
halbb_set_reg(bb, 0x47b8, BIT(12), 0x1);
halbb_set_reg(bb, 0x47b8, BIT(8), 0x1);
halbb_set_reg(bb, 0x47b8, BIT(6), 0x0);
}
halbb_set_reg_cmn(bb, 0x4440, BIT(31), 0x1, phy_idx);
}
}
u8 halbb_sco_mapping_8852b(struct bb_info *bb, u8 central_ch)
{
/*=== SCO compensate : (BIT(0) << 18) / central_ch ===*/
if (central_ch == 1)
/*=== 2G ===*/
return 109;
else if (central_ch >= 2 && central_ch <= 6)
return 108;
else if (central_ch >= 7 && central_ch <= 10)
return 107;
else if (central_ch >= 11 && central_ch <= 14)
return 106;
else if (central_ch == 36 || central_ch == 38)
return 51;
else if (central_ch >= 40 && central_ch <= 58)
return 50;
else if (central_ch >= 60 && central_ch <= 64)
return 49;
else if (central_ch == 100 || central_ch == 102)
return 48;
else if (central_ch >= 104 && central_ch <= 126)
return 47;
else if (central_ch >= 128 && central_ch <= 151)
return 46;
else if (central_ch >= 153 && central_ch <= 177)
return 45;
else
return 0;
}
bool halbb_ctrl_sco_cck_8852b(struct bb_info *bb, u8 pri_ch)
{
u32 sco_barker_threshold[14] = {0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd,
0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
0x1d79c, 0x1d892, 0x1d988, 0x1da7f,
0x1db75, 0x1ddc4};
u32 sco_cck_threshold[14] = {0x27de3, 0x27f35, 0x28088, 0x281da,
0x2832d, 0x2847f, 0x285d2, 0x28724,
0x28877, 0x289c9, 0x28b1c, 0x28c6e,
0x28dc1, 0x290ed};
if (pri_ch > 14) {
BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Fail]");
return false;
}
halbb_set_reg(bb, 0x23b0, 0x7ffff, sco_barker_threshold[pri_ch - 1]);
halbb_set_reg(bb, 0x23b4, 0x7ffff, sco_cck_threshold[pri_ch - 1]);
BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Success]");
return true;
}
bool halbb_write_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data)
{
u8 path_tmp = 0, b_msk_en = 0, bit_shift = 0;
u32 i =0, w_reg = 0;
bool is_r_busy = true, is_w_busy = true;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
while (is_w_busy || is_r_busy) {
is_w_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(24));
is_r_busy = (bool)halbb_get_reg(bb, 0x174c, BIT(25));
halbb_delay_us(bb, 1);
/*BB_WARNING("[%s] is_w_busy = %d, is_r_busy = %d\n",
__func__, is_w_busy, is_r_busy);*/
i++;
if (i > 30)
break;
}
if (is_w_busy || is_r_busy) {
BB_WARNING("[%s] is_w_busy = (%d), is_r_busy = (%d)\n",
__func__, is_w_busy, is_r_busy);
return false;
}
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return false;
}
/*==== Calculate offset ====*/
path_tmp = (u8)path & 0x7;
reg_addr &= 0xff;
/*==== RF register only has 20bits ====*/
data &= RFREGOFFSETMASK;
bit_mask &= RFREGOFFSETMASK;
/*==== Check if mask needed ====*/
if (bit_mask != RFREGOFFSETMASK) {
b_msk_en = 1;
halbb_set_reg(bb, 0x374, RFREGOFFSETMASK, bit_mask);
for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
if ((bit_mask >> bit_shift) & 0x1)
break;
}
data = (data << bit_shift) & RFREGOFFSETMASK;
}
w_reg = b_msk_en << 31 | path_tmp << 28 | reg_addr << 20 | data;
/*==== Write RF register ====*/
halbb_set_reg(bb, 0x370, MASKDWORD, w_reg);
//halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_PHY_CONFIG, "A die RF-%d 0x%x = 0x%x , bit mask = 0x%x, i=%x\n",
path_tmp, reg_addr, data, bit_mask,i);
return true;
}
bool halbb_write_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data)
{
u32 direct_addr = 0;
u32 offset_write_rf[2] = {0xe000, 0xf000};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return false;
}
/*==== Calculate offset ====*/
reg_addr &= 0xff;
direct_addr = offset_write_rf[path] + (reg_addr << 2);
/*==== RF register only has 20bits ====*/
bit_mask &= RFREGOFFSETMASK;
/*==== Write RF register directly ====*/
halbb_set_reg(bb, direct_addr, bit_mask, data);
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_PHY_CONFIG, "D die RF-%d 0x%x = 0x%x , bit mask = 0x%x\n",
path, reg_addr, data, bit_mask);
return true;
}
bool halbb_write_rf_reg_8852b(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data)
{
u8 path_tmp = 0, b_msk_en = 0;
u32 w_reg = 0;
bool rpt = true;
enum rtw_dv_sel ad_sel = (enum rtw_dv_sel)((reg_addr & 0x10000) >> 16);
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return false;
}
if (ad_sel == DAV) {
rpt = halbb_write_rf_reg_8852b_a(bb, path, reg_addr, bit_mask,
data);
/*BB_DBG(bb, DBG_PHY_CONFIG, "A-die RF-%d 0x%x = 0x%x , bit mask = 0x%x\n",
path, reg_addr, data, bit_mask);*/
} else if (ad_sel == DDV) {
rpt = halbb_write_rf_reg_8852b_d(bb, path, reg_addr, bit_mask,
data);
/*BB_DBG(bb, DBG_PHY_CONFIG, "D-die RF-%d 0x%x = 0x%x , bit mask = 0x%x\n",
path, reg_addr, data, bit_mask);*/
} else {
rpt = false;
BB_DBG(bb, DBG_PHY_CONFIG, "Fail Write RF-%d 0x%x = 0x%x , bit mask = 0x%x\n",
path, reg_addr, data, bit_mask);
}
return rpt;
}
void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg)
{
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if(bb->hal_com->band[0].cur_chandef.band != BAND_ON_24G)
return;
if (btg) {
// Path A
halbb_set_reg(bb, 0x4738, BIT(19), 0x1);
halbb_set_reg(bb, 0x4738, BIT(22), 0x0);
// Path B
halbb_set_reg(bb, 0x4AA4, BIT(19), 0x1);
halbb_set_reg(bb, 0x4AA4, BIT(22), 0x1);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply BTG Setting\n");
// Apply Grant BT by TMAC Setting
halbb_set_reg(bb, 0x980, 0x1e0000, 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply Grant BT by TMAC Setting\n");
// Add BT share
halbb_set_reg(bb, 0x49C4, BIT(14), 0x1);
halbb_set_reg(bb, 0x49C0, 0x3c00000, 0x2);
/* To avoid abnormal 1R CCA without BT, set rtl only 0xc6c[21] = 0x1 */
halbb_set_reg(bb, 0x4420, BIT(31), 0x1);
halbb_set_reg(bb, 0xc6c, BIT(21), 0x1);
} else {
// Path A
halbb_set_reg(bb, 0x4738, BIT(19), 0x0);
halbb_set_reg(bb, 0x4738, BIT(22), 0x0);
// Path B
halbb_set_reg(bb, 0x4AA4, BIT(19), 0x0);
halbb_set_reg(bb, 0x4AA4, BIT(22), 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Disable BTG Setting\n");
// Ignore Grant BT by PMAC Setting
halbb_set_reg(bb, 0x980, 0x1e0000, 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Ignore Grant BT by PMAC Setting\n");
// Reset BT share
halbb_set_reg(bb, 0x49C4, BIT(14), 0x0);
halbb_set_reg(bb, 0x49C0, 0x3c00000, 0x0);
/* To avoid abnormal 1R CCA without BT, set rtl only 0xc6c[21] = 0x1 */
halbb_set_reg(bb, 0x4420, BIT(31), 0x1);
halbb_set_reg(bb, 0xc6c, BIT(21), 0x0);
}
}
void halbb_ctrl_btc_preagc_8852b(struct bb_info *bb, bool bt_en)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bt_en) {
// DFIR Corner
halbb_set_reg(bb, 0x46D0, BIT(1) | BIT(0), 0x3);
halbb_set_reg(bb, 0x4790, BIT(1) | BIT(0), 0x3);
// LNA Backoff at Normal
halbb_set_reg(bb, 0x46a0, 0x3f, 0x8);
halbb_set_reg(bb, 0x49f4, 0x3f, 0x8);
// LNA, TIA, ADC backoff at BT TX
halbb_set_reg(bb, 0x4ae4, 0xffffff, 0x78899e);
halbb_set_reg(bb, 0x4aec, 0xffffff, 0x78899e);
} else {
// DFIR Corner
halbb_set_reg(bb, 0x46D0, BIT(1) | BIT(0), 0x0);
halbb_set_reg(bb, 0x4790, BIT(1) | BIT(0), 0x0);
// LNA Backoff at Normal
halbb_set_reg(bb, 0x46a0, 0x3f, 0x1e);
halbb_set_reg(bb, 0x49f4, 0x3f, 0x1e);
// LNA, TIA, ADC backoff at BT TX
halbb_set_reg(bb, 0x4ae4, 0xffffff, 0x4d34d2);
halbb_set_reg(bb, 0x4aec, 0xffffff, 0x4d34d2);
}
}
bool halbb_bw_setting_8852b(struct bb_info *bb, enum channel_width bw,
enum rf_path path)
{
u32 rf_reg18 = 0;
u32 adc_sel[2] = {0xC0EC, 0xC1EC};
u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
//rf_reg18 = halbb_read_rf_reg_8852b(bb, path, 0x18, RFREGOFFSETMASK);
/*==== [Error handling] ====*/
//if (rf_reg18 == INVALID_RF_DATA) {
// BB_WARNING("Invalid RF_0x18 for Path-%d\n", path);
// return false;
//}
//rf_reg18 &= ~(BIT(11) | BIT(10));
/*==== [Switch bandwidth] ====*/
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
if (bw == CHANNEL_WIDTH_5) {
/*ADC clock = 20M & WB ADC clock = 40M for BW5 */
halbb_set_reg(bb, adc_sel[path], 0x6000, 0x1);
halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x0);
} else if (bw == CHANNEL_WIDTH_10) {
/*ADC clock = 40M & WB ADC clock = 80M for BW10 */
halbb_set_reg(bb, adc_sel[path], 0x6000, 0x2);
halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x1);
} else if (bw == CHANNEL_WIDTH_20) {
/*ADC clock = 80M & WB ADC clock = 160M for BW20 */
halbb_set_reg(bb, adc_sel[path], 0x6000, 0x0);
halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x2);
}
/*RF bandwidth */
//rf_reg18 |= (BIT(11) | BIT(10));
break;
case CHANNEL_WIDTH_40:
/*ADC clock = 80M & WB ADC clock = 160M for BW40 */
halbb_set_reg(bb, adc_sel[path], 0x6000, 0x0);
halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x2);
/*RF bandwidth */
//rf_reg18 |= BIT(11);
break;
case CHANNEL_WIDTH_80:
/*ADC clock = 160M & WB ADC clock = 160M for BW40 */
halbb_set_reg(bb, adc_sel[path], 0x6000, 0x0);
halbb_set_reg(bb, wbadc_sel[path], 0x30, 0x2);
/*RF bandwidth */
//rf_reg18 |= BIT(10);
break;
default:
BB_WARNING("Fail to set ADC\n");
}
/*==== [Write RF register] ====*/
//Already Move to RF API
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success][bw_setting] ADC setting for Path-%d\n", path);
return true;
}
bool halbb_ctrl_bw_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bb->is_disable_phy_api) {
BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__);
return true;
}
/*==== Error handling ====*/
if (bw >= CHANNEL_WIDTH_MAX || (bw == CHANNEL_WIDTH_40 && pri_ch > 2) ||
(bw == CHANNEL_WIDTH_80 && pri_ch > 4)) {
BB_WARNING("Fail to switch bw(bw:%d, pri ch:%d)\n", bw,
pri_ch);
return false;
}
/*==== Switch bandwidth ====*/
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
if (bw == CHANNEL_WIDTH_5) {
/*RF_BW:[31:30]=0x0 */
halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x0,
phy_idx);
/*small BW:[13:12]=0x1 */
halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x1, phy_idx);
/*Pri ch:[11:8]=0x0 */
halbb_set_reg_cmn(bb, 0x49C4, 0xf00, 0x0, phy_idx);
} else if (bw == CHANNEL_WIDTH_10) {
/*RF_BW:[31:30]=0x0 */
halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x0,
phy_idx);
/*small BW:[13:12]=0x2 */
halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x2, phy_idx);
/*Pri ch:[11:8]=0x0 */
halbb_set_reg_cmn(bb, 0x49C4, 0xf00, 0x0, phy_idx);
} else if (bw == CHANNEL_WIDTH_20) {
/*RF_BW:[31:30]=0x0 */
halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x0,
phy_idx);
/*small BW:[13:12]=0x0 */
halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x0, phy_idx);
/*Pri ch:[11:8]=0x0 */
halbb_set_reg_cmn(bb, 0x49C4, 0xf00, 0x0, phy_idx);
}
break;
case CHANNEL_WIDTH_40:
/*RF_BW:[31:30]=0x1 */
halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x1, phy_idx);
/*small BW:[13:12]=0x0 */
halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x0, phy_idx);
/*Pri ch:[11:8] */
halbb_set_reg_cmn(bb, 0x49C4, 0xf00, pri_ch, phy_idx);
/*CCK primary channel */
if (pri_ch == 1)
halbb_set_reg(bb, 0x237c, BIT(0), 1);
else
halbb_set_reg(bb, 0x237c, BIT(0), 0);
break;
case CHANNEL_WIDTH_80:
/*RF_BW:[31:30]=0x2 */
halbb_set_reg_cmn(bb, 0x49C0, 0xC0000000, 0x2, phy_idx);
/*small BW:[13:12]=0x0 */
halbb_set_reg_cmn(bb, 0x49C4, 0x3000, 0x0, phy_idx);
/*Pri ch:[11:8] */
halbb_set_reg_cmn(bb, 0x49C4, 0xf00, pri_ch, phy_idx);
break;
default:
BB_WARNING("Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
pri_ch);
}
/*============== [Path A] ==============*/
halbb_bw_setting_8852b(bb, bw, RF_PATH_A);
/*============== [Path B] ==============*/
halbb_bw_setting_8852b(bb, bw, RF_PATH_B);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Switch BW Success] BW: %d for PHY%d\n", bw, phy_idx);
return true;
}
bool halbb_ch_setting_8852b(struct bb_info *bb, u8 central_ch, enum rf_path path,
bool *is_2g_ch)
{
u32 rf_reg18 = 0;
*is_2g_ch = (central_ch <= 14) ? true : false;
//RF_18 R/W already move to RF API
BB_DBG(bb, DBG_PHY_CONFIG, "[Success][ch_setting] CH: %d for Path-%d\n",
central_ch, path);
return true;
}
bool halbb_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch,
enum phl_phy_idx phy_idx)
{
u8 sco_comp;
bool is_2g_ch;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bb->is_disable_phy_api) {
BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__);
return true;
}
/*==== Error handling ====*/
if ((central_ch > 14 && central_ch < 36) ||
(central_ch > 64 && central_ch < 100) ||
(central_ch > 144 && central_ch < 149) ||
central_ch > 177 ||
central_ch== 0) {
BB_WARNING("Invalid CH:%d for PHY%d\n", central_ch,
phy_idx);
return false;
}
/*============== [Path A] ==============*/
halbb_ch_setting_8852b(bb, central_ch, RF_PATH_A, &is_2g_ch);
//------------- [Mode Sel - Path A] ------------//
if (is_2g_ch)
halbb_set_reg_cmn(bb, 0x4738, BIT(17), 1, phy_idx);
else
halbb_set_reg_cmn(bb, 0x4738, BIT(17), 0, phy_idx);
/*============== [Path B] ==============*/
halbb_ch_setting_8852b(bb, central_ch, RF_PATH_B, &is_2g_ch);
//------------- [Mode Sel - Path B] ------------//
if (is_2g_ch)
halbb_set_reg_cmn(bb, 0x4AA4, BIT(17), 1, phy_idx);
else
halbb_set_reg_cmn(bb, 0x4AA4, BIT(17), 0, phy_idx);
/*==== [SCO compensate fc setting] ====*/
sco_comp = halbb_sco_mapping_8852b(bb, central_ch);
halbb_set_reg_cmn(bb, 0x49C0, 0x7f, sco_comp, phy_idx);
/* === CCK Parameters === */
if (central_ch == 14) {
halbb_set_reg(bb, 0x2300, 0xffffff, 0x3b13ff);
halbb_set_reg(bb, 0x2304, 0xffffff, 0x1c42de);
halbb_set_reg(bb, 0x2308, 0xffffff, 0xfdb0ad);
halbb_set_reg(bb, 0x230c, 0xffffff, 0xf60f6e);
halbb_set_reg(bb, 0x2310, 0xffffff, 0xfd8f92);
halbb_set_reg(bb, 0x2314, 0xffffff, 0x2d011);
halbb_set_reg(bb, 0x2318, 0xffffff, 0x1c02c);
halbb_set_reg(bb, 0x231c, 0xffffff, 0xfff00a);
} else {
halbb_set_reg(bb, 0x2300, 0xffffff, 0x3d23ff);
halbb_set_reg(bb, 0x2304, 0xffffff, 0x29b354);
halbb_set_reg(bb, 0x2308, 0xffffff, 0xfc1c8);
halbb_set_reg(bb, 0x230c, 0xffffff, 0xfdb053);
halbb_set_reg(bb, 0x2310, 0xffffff, 0xf86f9a);
halbb_set_reg(bb, 0x2314, 0xffffff, 0xfaef92);
halbb_set_reg(bb, 0x2318, 0xffffff, 0xfe5fcc);
halbb_set_reg(bb, 0x231c, 0xffffff, 0xffdff5);
}
/* === Set Gain Error === */
halbb_set_gain_error_8852b(bb, central_ch);
/* === Set Efuse === */
halbb_set_efuse_8852b(bb, central_ch, HW_PHY_0);
/* === Set RXSC RPL Comp === */
halbb_set_rxsc_rpl_comp_8852b(bb, central_ch);
/* === Set Ch idx report in phy-sts === */
halbb_set_reg_cmn(bb, 0x0734, 0x0ff0000, central_ch, phy_idx);
bb->bb_ch_i.rf_central_ch_cfg = central_ch;
BB_DBG(bb, DBG_PHY_CONFIG, "[Switch CH Success] CH: %d for PHY%d\n",
central_ch, phy_idx);
return true;
}
void halbb_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx)
{
if (cck_en) {
//halbb_set_reg(bb, 0x2300, BIT(27), 0);
halbb_set_reg(bb, 0x700, BIT(5), 1);
halbb_set_reg(bb, 0x2344, BIT(31), 0);
} else {
//halbb_set_reg(bb, 0x2300, BIT(27), 1);
halbb_set_reg(bb, 0x700, BIT(5), 0);
halbb_set_reg(bb, 0x2344, BIT(31), 1);
}
BB_DBG(bb, DBG_PHY_CONFIG, "[CCK Enable for PHY%d]\n", phy_idx);
}
bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx)
{
bool rpt = true;
bool cck_en = false;
u8 pri_ch_idx = 0;
bool is_2g_ch;
is_2g_ch = (band == BAND_ON_24G) ? true : false;
/*==== [Set pri_ch idx] ====*/
if (central_ch <= 14) {
#ifdef BANDEDGE_FILTER_CFG_FOR_ULOFDMA
/*==== [UL-OFDMA 2x 1p6 Tx WA] ====*/
halbb_set_reg(bb, 0x4498, BIT(30), 1);
#endif
// === 2G === //
switch (bw) {
case CHANNEL_WIDTH_20:
break;
case CHANNEL_WIDTH_40:
pri_ch_idx = pri_ch > central_ch ? 1 : 2;
break;
default:
break;
}
/*==== [CCK SCO Compesate] ====*/
rpt &= halbb_ctrl_sco_cck_8852b(bb, pri_ch);
cck_en = true;
} else {
// === 5G === //
switch (bw) {
case CHANNEL_WIDTH_20:
#ifdef BANDEDGE_FILTER_CFG_FOR_ULOFDMA
/*==== [UL-OFDMA 2x 1p6 Tx WA] ====*/
halbb_set_reg(bb, 0x4498, BIT(30), 1);
#endif
break;
case CHANNEL_WIDTH_40:
case CHANNEL_WIDTH_80:
if (pri_ch > central_ch)
pri_ch_idx = (pri_ch - central_ch) >> 1;
else
pri_ch_idx = ((central_ch - pri_ch) >> 1) + 1;
#ifdef BANDEDGE_FILTER_CFG_FOR_ULOFDMA
/*==== [UL-OFDMA 2x 1p6 Tx WA] ====*/
halbb_set_reg(bb, 0x4498, BIT(30), 0);
#endif
break;
default:
break;
}
cck_en = false;
}
/*==== [Switch CH] ====*/
rpt &= halbb_ctrl_ch_8852b(bb, central_ch, phy_idx);
/*==== [Switch BW] ====*/
rpt &= halbb_ctrl_bw_8852b(bb, pri_ch_idx, bw, phy_idx);
/*==== [CCK Enable / Disable] ====*/
halbb_ctrl_cck_en_8852b(bb, cck_en, phy_idx);
/*==== [Spur elimination] ====*/
//TBD
if (is_2g_ch && ((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB))){
halbb_ctrl_btg_8852b(bb, true);
} else if (is_2g_ch && (bb->rx_path == RF_PATH_A)) {
halbb_ctrl_btg_8852b(bb, false);
} else {
// Path A
halbb_set_reg(bb, 0x4738, BIT(19), 0x0);
halbb_set_reg(bb, 0x4738, BIT(22), 0x0);
// Path B
halbb_set_reg(bb, 0x4AA4, BIT(19), 0x0);
halbb_set_reg(bb, 0x4AA4, BIT(22), 0x0);
// Ignore Grant BT by PMAC Setting
halbb_set_reg(bb, 0x980, 0x1e0000, 0xf);
// Reset BT share
halbb_set_reg(bb, 0x49C4, BIT(14), 0x0);
halbb_set_reg(bb, 0x49C0, 0x3c00000, 0x0);
/* To avoid abnormal 1R CCA without BT, set rtl only 0xc6c[21] = 0x1 */
halbb_set_reg(bb, 0x4420, BIT(31), 0x0);
halbb_set_reg(bb, 0xc6c, BIT(21), 0x0);
}
/* Dynamic 5M Mask Setting */
halbb_5m_mask_8852b(bb, pri_ch, bw, phy_idx);
/*==== [BB reset] ====*/
halbb_bb_reset_all_8852b(bb, phy_idx);
return rpt;
}
bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path)
{
u32 ofdm_rx = 0x0;
ofdm_rx = (u32)rx_path;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
bb->rx_path = rx_path;
if (ofdm_rx == RF_PATH_A) {
halbb_set_reg(bb, 0x49C4, 0xf, 0x1);
/*==== 1rcca ====*/
halbb_set_reg(bb, 0x49C0, 0x3C000, 1);
halbb_set_reg(bb, 0x49C0, 0x3C0000, 1);
/*==== Rx HT nss_limit / mcs_limit ====*/
halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 0);
halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 0);
/*==== Rx HE n_user_max / tb_max_nss ====*/
halbb_set_reg(bb, 0xd80, 0x3fc0, 4);
halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 0);
halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 0);
} else if (ofdm_rx == RF_PATH_B) {
halbb_set_reg(bb, 0x49C4, 0xf, 0x2);
/*==== 1rcca ====*/
halbb_set_reg(bb, 0x49C0, 0x3C000, 0x2);
halbb_set_reg(bb, 0x49C0, 0x3C0000, 0x2);
/*==== Rx HT nss_limit / mcs_limit ====*/
halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 0);
halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 0);
/*==== Rx HE n_user_max / tb_max_nss ====*/
halbb_set_reg(bb, 0xd80, 0x3fc0, 4);
halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 0);
halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 0);
} else if (ofdm_rx == RF_PATH_AB) {
halbb_set_reg(bb, 0x49C4, 0xf, 0x3);
/*==== 1rcca ====*/
halbb_set_reg(bb, 0x49C0, 0x3C000, 0x3);
halbb_set_reg(bb, 0x49C0, 0x3C0000, 0x3);
/*==== Rx HT nss_limit / mcs_limit ====*/
halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 1);
halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 1);
/*==== Rx HE n_user_max / tb_max_nss ====*/
halbb_set_reg(bb, 0xd80, 0x3fc0, 4);
halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 1);
halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 1);
}
/*==== [Set Efuse] =====*/
halbb_set_efuse_8852b(bb, bb->hal_com->band[0].cur_chandef.center_ch, HW_PHY_0);
/* === [BTG setting] === */
if ((bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) && ((rx_path == RF_PATH_B) || (rx_path == RF_PATH_AB)))
halbb_ctrl_btg_8852b(bb, true);
else
halbb_ctrl_btg_8852b(bb, false);
/*==== [TSSI reset] ====*/
if (rx_path == RF_PATH_A) {
halbb_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x1);
halbb_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x3);
} else {
halbb_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x1);
halbb_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x3);
}
/*==== [BB reset] ====*/
//halbb_bb_reset_all_8852b(bb, HW_PHY_0);
BB_DBG(bb, DBG_PHY_CONFIG, "[Rx Success]RX_en=%x\n", rx_path);
return true;
}
bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== [P-MAC] Path & Path_map Enable ====*/
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0x7, HW_PHY_0);
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0x7, HW_PHY_1);
if (tx_path == RF_PATH_A) {
halbb_set_reg(bb, 0x458C, 0xf0000000, 0x1);
halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x0);
} else if (tx_path == RF_PATH_B) {
halbb_set_reg(bb, 0x458C, 0xf0000000, 0x2);
halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x0);
} else if (tx_path == RF_PATH_AB) {
halbb_set_reg(bb, 0x458C, 0xf0000000, 0x3);
halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x4);
} else {
BB_WARNING("Invalid Tx Path\n");
return false;
}
/*==== [BB reset] ====*/
halbb_bb_reset_all_8852b(bb, HW_PHY_0);
BB_DBG(bb, DBG_PHY_CONFIG, "[Success] [P-MAC] Tx Path Config\n");
return true;
}
void halbb_ctrl_rf_mode_8852b(struct bb_info *bb, enum phl_rf_mode mode)
{
if (mode == RF_MODE_STANDBY) {
halbb_set_reg(bb, 0x12ac, 0xfffffff0, 0x1111111);
halbb_set_reg(bb, 0x12b0, 0xfff, 0x111);
halbb_set_reg(bb, 0x32ac, 0xfffffff0, 0x1111111);
halbb_set_reg(bb, 0x32b0, 0xfff, 0x111);
} else if (mode == RF_MODE_SHUTDOWN) {
halbb_set_reg(bb, 0x12ac, 0xfffffff0, 0x0);
halbb_set_reg(bb, 0x12b0, 0xfff, 0x0);
halbb_set_reg(bb, 0x32ac, 0xfffffff0, 0x0);
halbb_set_reg(bb, 0x32b0, 0xfff, 0x0);
} else {
halbb_set_reg(bb, 0x12ac, 0xfffffff0, 0x233302);
halbb_set_reg(bb, 0x12b0, 0xfff, 0x333);
halbb_set_reg(bb, 0x32ac, 0xfffffff0, 0x233302);
halbb_set_reg(bb, 0x32b0, 0xfff, 0x333);
}
BB_DBG(bb, DBG_PHY_CONFIG, "[RF Mode] Mode = %d", mode);
}
u16 halbb_cfg_cmac_tx_ant_8852b(struct bb_info *bb, enum rf_path tx_path)
{
// Return CMAC [OFST 20] Tx settings //
/* [19:16] path_en[3:0] ||
|| [21:20] map_a[1:0] ||
|| [23:22] map_b[1:0] ||
|| [25:24] map_c[1:0] ||
|| [27:26] map_d[1:0] ||
|| [28] ant_sel_a[0] ||
|| [29] ant_sel_b[0] ||
|| [30] ant_sel_c[0] ||
|| [31] ant_sel_d[0] */
u16 cmac_tx_info = 0;
if (tx_path == RF_PATH_A) {
cmac_tx_info = 0x1;
} else if (tx_path == RF_PATH_B) {
cmac_tx_info = 0x2;
} else if (tx_path == RF_PATH_AB) {
cmac_tx_info = 0x43;
} else {
cmac_tx_info = 0xffff;
BB_WARNING("Invalid Tx Path: %d\n", tx_path);
}
return cmac_tx_info;
}
void halbb_ctrl_trx_path_8852b(struct bb_info *bb, enum rf_path tx_path,
u8 tx_nss, enum rf_path rx_path, u8 rx_nss)
{
// Rx Config
halbb_ctrl_rx_path_8852b(bb, rx_path);
if ((rx_nss > 2) || (tx_nss > 2)) {
BB_WARNING("[Invalid Nss]Tx Nss: %d, Rx Nss: %d\n", tx_nss,
rx_nss);
return;
}
if (rx_nss == 1) {
/*==== [PHY0] Rx HT nss_limit / mcs_limit ====*/
halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 0);
halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 0);
/*==== [PHY0] Rx HE n_user_max / tb_max_nss ====*/
halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 0);
halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 0);
} else {
/*==== [PHY0] Rx HT nss_limit / mcs_limit ====*/
halbb_set_reg(bb, 0xd18, BIT(9) | BIT(8), 1);
halbb_set_reg(bb, 0xd18, BIT(22) | BIT(21), 1);
/*==== [PHY0] Rx HE n_user_max / tb_max_nss ====*/
halbb_set_reg(bb, 0xd80, BIT(16) | BIT(15) | BIT(14), 1);
halbb_set_reg(bb, 0xd80, BIT(25) | BIT(24) | BIT(23), 1);
}
// Tx Config (to do)
// Need to Add MP flag for Tx_path API since Normal Drv will also call this function
// ==== [T-MAC] Path & Path_map Enable ==== //
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0x0, HW_PHY_0);
}
void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx)
{
if (cca_en) {
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx);
halbb_set_reg(bb, 0x2344, BIT(31), 0);
} else {
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx);
halbb_set_reg(bb, 0x2344, BIT(31), 1);
}
BB_DBG(bb, DBG_PHY_CONFIG, "[Rx CCA] CCA_EN = %d\n", cca_en);
}
void halbb_ctrl_ofdm_en_8852b(struct bb_info *bb, bool ofdm_en,
enum phl_phy_idx phy_idx)
{
if (ofdm_en)
halbb_set_reg_cmn(bb, 0x700, BIT(4), 1, phy_idx);
else
halbb_set_reg_cmn(bb, 0x700, BIT(4), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[OFDM Enable for PHY%d]\n", phy_idx);
}
// =================== [Power Module] =================== //
bool halbb_set_txpwr_dbm_8852b(struct bb_info *bb, s16 power_dbm,
enum phl_phy_idx phy_idx)
{
bool tmp = false;
power_dbm &= 0x1ff;
halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x4594, 0x7fc00000, power_dbm, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] Set Tx pwr(dBm) for [PHY-%d] : %d\n", phy_idx,
power_dbm);
tmp = true;
return tmp;
}
s16 halbb_get_txpwr_dbm_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u32 txpwr_dbm;
s16 output;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
txpwr_dbm = halbb_get_reg_cmn(bb, 0x4594, 0x7fc00000, phy_idx);
output = (s16)halbb_cnvrt_2_sign(txpwr_dbm, 9);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] Get Tx pwr(dBm) for [PHY-%d] : %d\n", phy_idx,
output);
return output;
}
s16 halbb_get_txinfo_txpwr_dbm_8852b(struct bb_info *bb)
{
u32 txpwr_dbm;
s16 output;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
txpwr_dbm = halbb_get_reg(bb, 0x1804, 0x7FC0000);
output = (s16)halbb_cnvrt_2_sign(txpwr_dbm, 9);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] Get TxInfo pwr(dBm) : %d\n", output);
return output;
}
bool halbb_set_cck_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path)
{
u32 pwr_idx_addr[2] = {0x5808, 0x7808};
/*==== Power index Check ====*/
if ((power_idx & ~0x1ff) != 0) {
BB_WARNING("Power Idx: %x\n", power_idx);
return false;
}
/*==== Tx Path Check ====*/
if (tx_path > RF_PATH_B) {
BB_WARNING("Invalid Tx Path for CCK Txpwr_idx setting (52A)\n");
return false;
}
halbb_set_reg(bb, pwr_idx_addr[tx_path], 0x3fe00, power_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [CCK] Set Tx pwr idx for [Path-%d] : %x\n",
tx_path, power_idx);
return true;
}
u16 halbb_get_cck_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path)
{
u16 cck_pwr_idx;
u32 pwr_idx_addr[2] = {0x5808, 0x7808};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
cck_pwr_idx = (u16)halbb_get_reg(bb, pwr_idx_addr[tx_path], 0x3fe00);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [CCK] Get Tx pwr idx for [Path-%d] : %x\n",
tx_path, cck_pwr_idx);
return cck_pwr_idx;
}
s16 halbb_get_cck_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path)
{
u32 cck_ref_dbm;
u32 pwr_ref_addr[2] = {0x5808, 0x7808};
s16 output;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
cck_ref_dbm = halbb_get_reg(bb, pwr_ref_addr[tx_path], 0x1ff);
output = (s16)halbb_cnvrt_2_sign(cck_ref_dbm, 9);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [CCK] Get Tx ref pwr(dBm) for [Path-%d] : %d\n",
tx_path, output);
return output;
}
bool halbb_set_ofdm_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path)
{
u32 pwr_idx_addr[2] = {0x5804, 0x7804};
/*==== Power index Check ====*/
if ((power_idx & ~0x1ff) != 0) {
BB_WARNING("Power Idx: %x\n", power_idx);
return false;
}
/*==== Tx Path Check ====*/
if (tx_path > RF_PATH_B) {
BB_WARNING("Invalid Tx Path for CCK Txpwr_idx setting (52A)\n");
return false;
}
halbb_set_reg(bb, pwr_idx_addr[tx_path], 0x3fe00, power_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [OFDM] Set Tx pwr idx for [Path-%d] : %x\n",
tx_path, power_idx);
return true;
}
u16 halbb_get_ofdm_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path)
{
u16 ofdm_pwr_idx;
u32 pwr_idx_addr[2] = {0x5804, 0x7804};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
ofdm_pwr_idx = (u16)halbb_get_reg(bb, pwr_idx_addr[tx_path], 0x3fe00);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [OFDM] Get Tx pwr idx for [Path-%d] : %x\n",
tx_path, ofdm_pwr_idx);
return ofdm_pwr_idx;
}
s16 halbb_get_ofdm_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path)
{
u32 ofdm_ref_dbm;
u32 pwr_ref_addr[2] = {0x5804, 0x7804};
s16 output;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
ofdm_ref_dbm = halbb_get_reg(bb, pwr_ref_addr[tx_path], 0x1ff);
output = (s16)halbb_cnvrt_2_sign(ofdm_ref_dbm, 9);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [OFDM] Get Tx ref pwr(dBm) for [Path-%d] : %d\n",
tx_path, output);
return output;
}
void halbb_reset_bb_hw_cnt_8852b(struct bb_info *bb)
{
/*@ Reset all counter*/
halbb_set_reg(bb, 0x730, BIT(0), 1);
halbb_set_reg(bb, 0x730, BIT(0), 0);
}
void halbb_backup_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
/*==== This Backup info is for RF TSSI calibration =====*/
bb->bb_cmn_backup_i.cur_tx_path = (u8)halbb_get_reg_cmn(bb, 0x458c, 0xf0000000, phy_idx);
bb->bb_cmn_backup_i.cur_rx_path = (u8)halbb_get_reg_cmn(bb, 0x49c4, 0xf, phy_idx);
bb->bb_cmn_backup_i.cur_tx_pwr = halbb_get_txpwr_dbm_8852b(bb, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[Backup Info] [PHY%d] Tx path = %x\n", phy_idx, bb->bb_cmn_backup_i.cur_tx_path);
BB_DBG(bb, DBG_PHY_CONFIG, "[Backup Info] [PHY%d] Tx pwr = %x\n", phy_idx, (u16)bb->bb_cmn_backup_i.cur_tx_pwr);
}
void halbb_restore_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
/*==== This Restore info is for RF TSSI calibration =====*/
halbb_set_reg_cmn(bb, 0x458c, 0xf0000000, bb->bb_cmn_backup_i.cur_tx_path, phy_idx);
if (bb->bb_cmn_backup_i.cur_tx_path == 0x3) {
halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x4);
} else {
halbb_set_reg(bb, 0x45B4, 0x1e0000, 0x0);
}
halbb_set_reg_cmn(bb, 0x49c4, 0xf, bb->bb_cmn_backup_i.cur_rx_path, phy_idx);
halbb_set_txpwr_dbm_8852b(bb, bb->bb_cmn_backup_i.cur_tx_pwr, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[Restore Info] [PHY%d] Tx path = %x\n", phy_idx, bb->bb_cmn_backup_i.cur_tx_path);
BB_DBG(bb, DBG_PHY_CONFIG, "[Restore Info] [PHY%d] Tx pwr = %x\n", phy_idx, (u16)bb->bb_cmn_backup_i.cur_tx_pwr);
}
bool halbb_set_txsc_8852b(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx)
{
/*==== txsc Check ====*/
if ((txsc & ~0xf) != 0) {
BB_WARNING("TXSC: %x\n", txsc);
return false;
}
halbb_set_reg_cmn(bb, 0x45ac, 0x7800000, txsc, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [P-MAC] TXSC for [PHY-%d] : %x\n", phy_idx,
txsc);
return true;
}
#if 0
void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (btg) {
// Path A
halbb_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x1);
// Path B
halbb_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x3);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply BTG Setting\n");
// Apply Grant BT by TMAC Setting
halbb_set_reg(bb, 0x980, 0x1e0000, 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply Grant BT by TMAC Setting\n");
} else {
// Path A
halbb_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x0);
// Path B
halbb_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Disable BTG Setting\n");
// Ignore Grant BT by PMAC Setting
halbb_set_reg(bb, 0x980, 0x1e0000, 0xf);
halbb_set_reg(bb, 0x980, 0x3c000000, 0x4);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Ignore Grant BT by PMAC Setting\n");
}
}
#endif
bool halbb_set_bss_color_8852b(struct bb_info *bb, u8 bss_color,
enum phl_phy_idx phy_idx)
{
/*==== BSS color Check ====*/
if ((bss_color & ~0x3f) != 0) {
BB_WARNING("BSS color: %x\n", bss_color);
return false;
}
//=== [Enable BSS color mapping] ===//
halbb_set_reg_cmn(bb, 0x43b0, BIT(28), 0x1, phy_idx);
halbb_set_reg_cmn(bb, 0x43b0, 0xfc00000, bss_color, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [P-MAC] BSS Color for [PHY-%d] : %x\n", phy_idx,
bss_color);
return true;
}
bool halbb_set_sta_id_8852b(struct bb_info *bb, u16 sta_id,
enum phl_phy_idx phy_idx)
{
/*==== Station ID Check ====*/
if ((sta_id & ~0x7ff) != 0) {
BB_WARNING("Station ID: %x\n", sta_id);
return false;
}
//=== [Set Station ID] ===//
halbb_set_reg_cmn(bb, 0x43b0, 0x3ff800, sta_id, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Success] [P-MAC] Station ID for [PHY-%d] : %x\n", phy_idx,
sta_id);
return true;
}
void halbb_set_igi_8852b(struct bb_info *bb, u8 lna_idx, bool tia_idx,
u8 rxbb_idx, enum rf_path path)
{
u8 lna = 0;
bool tia = 0;
u8 rxbb = 0;
u32 lna_addr[2] = {0x472c, 0x4a80};
u32 tia_addr[2] = {0x473c, 0x4aa8};
u32 rxbb_addr[2] = {0x46a8, 0x4a5c};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
halbb_set_reg(bb, lna_addr[path], 0x7000000, lna_idx);
halbb_set_reg(bb, tia_addr[path], BIT(9), tia_idx);
halbb_set_reg(bb, rxbb_addr[path], 0x7c00, rxbb_idx);
lna = (u8)halbb_get_reg(bb, lna_addr[path], BIT(26) | BIT(25) | BIT(24));
tia = (bool)halbb_get_reg(bb, tia_addr[path], BIT(9));
rxbb = (u8)halbb_get_reg(bb, rxbb_addr[path], 0x7c00);
BB_DBG(bb, DBG_PHY_CONFIG, "[IGI] LNA for [Path-%d] : %d\n", path, lna);
BB_DBG(bb, DBG_PHY_CONFIG, "[IGI] TIA for [Path-%d] : %d\n", path, tia);
BB_DBG(bb, DBG_PHY_CONFIG, "[IGI] RxBB for [Path-%d] : %d\n", path, rxbb);
}
void halbb_set_tx_pow_ref_8852b(struct bb_info *bb, s16 pw_dbm_ofdm, /*s(9,2)*/
s16 pw_dbm_cck, s8 ofst,
u8 base_cw_0db, u16 tssi_16dBm_cw,
u16 *ofdm_cw, u16 *cck_cw,
enum phl_phy_idx phy_idx)
{
s16 rf_pw_cw = 0;
u32 pw_cw = 0;
u32 val = 0;
s16 pw_s10_3 = 0;
u32 tssi_ofst_cw = 0;
/*OFDM*/
pw_s10_3 = (pw_dbm_ofdm * 2) + (s16)(ofst) + (s16)(base_cw_0db * 8);
pw_cw = pw_s10_3;
rf_pw_cw = (pw_s10_3 & 0x1F8) >> 3;
if (rf_pw_cw > 63)
pw_cw = (63 << 3) | (pw_s10_3 & 0x7); /*upper bound (+24dBm)*/
else if (rf_pw_cw < 15)
pw_cw = (15 << 3) | (pw_s10_3 & 0x7); /*lower bound (-24dBm)*/
/* ===[Set TSSI Offset]===============================================*/
/*
172 = 300 - (55 - 39) * 8;
tssi_ofst_cw = tssi_16dBm_cw - (tx_pow_16dBm_ref_cw - tx_pow_ref_cw) * 8;
= tssi_16dBm_cw + tx_pow_ref * 8 - tx_pow_16dBm_ref * 8
*/
tssi_ofst_cw = (u32)((s16)tssi_16dBm_cw + (pw_dbm_ofdm * 2) - (16 * 8));
BB_DBG(bb, DBG_DBG_API, "[OFDM]tssi_ofst_cw=%d, rf_cw=0x%x, bb_cw=0x%x\n", tssi_ofst_cw, pw_cw >> 3, pw_cw & 0x7);
*ofdm_cw = (u16)pw_cw;
val = tssi_ofst_cw << 18 | pw_cw << 9 | (u32)(pw_dbm_ofdm & 0x1ff);
halbb_set_reg_cmn(bb, 0x5804, 0x7FFFFFF, val, phy_idx);
halbb_set_reg_cmn(bb, 0x7804, 0x7FFFFFF, val, phy_idx);
/*CCK*/
pw_s10_3 = (pw_dbm_cck * 2) + (s16)(ofst) + (s16)(base_cw_0db * 8);
pw_cw = pw_s10_3;
rf_pw_cw = (pw_s10_3 & 0x1F8) >> 3;
if (rf_pw_cw > 63)
pw_cw = (63 << 3) | (pw_s10_3 & 0x7); /*upper bound (+24dBm)*/
else if (rf_pw_cw < 15)
pw_cw = (15 << 3) | (pw_s10_3 & 0x7); /*lower bound (-24dBm)*/
/* ===[Set TSSI Offset]===============================================*/
/*
172 = 300 - (55 - 39) * 8;
tssi_ofst_cw = tssi_16dBm_cw - (tx_pow_16dBm_ref_cw - tx_pow_ref_cw) * 8;
= tssi_16dBm_cw + tx_pow_ref * 8 - tx_pow_16dBm_ref * 8
*/
tssi_ofst_cw = (u32)((s16)tssi_16dBm_cw + (pw_dbm_cck * 2) - (16 * 8));
BB_DBG(bb, DBG_DBG_API, "[CCK] tssi_ofst_cw=%d, rf_cw=0x%x, bb_cw=0x%x\n", tssi_ofst_cw, pw_cw >> 3, pw_cw & 0x7);
*cck_cw = (u16)pw_cw;
val = tssi_ofst_cw << 18 | pw_cw << 9 | (u32)(pw_dbm_cck & 0x1ff);
halbb_set_reg_cmn(bb, 0x5808, 0x7FFFFFF, val, phy_idx);
halbb_set_reg_cmn(bb, 0x7808, 0x7FFFFFF, val, phy_idx);
}
void halbb_dump_bb_reg_8852b(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff)
{
u32 i = 0, addr = 0;
u32 cr_start = 0, cr_end = 0;
u32 dump_cr_table[][2] = {{0x0000, 0x04FC},
{0x0600, 0x0DFC},
{0x1000, 0x10FC},
{0x1200, 0x13FC},
{0x1700, 0x20FC},
{0x2200, 0x24FC},
{0x2600, 0x2DFC},
{0x3000, 0x30FC},
{0x3200, 0x33FC},
{0x3900, 0x4FFC},
{0x5800, 0x6FFC},
{0x7800, 0x7FFC}};
u32 table_len = sizeof(dump_cr_table)/(sizeof(u32) * 2);
BB_TRACE("BBCR: dump all ==>\n");
BB_TRACE("table_len=%d\n", table_len);
for (i = 0; i < table_len; i ++) {
if (dump_2_buff)
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%02d] Reg[0x%04x ~ 0x%04x]\n\n",
i, dump_cr_table[i][0], dump_cr_table[i][1]);
else
BB_TRACE("[%02d] Reg[0x%04x ~ 0x%04x]\n\n",
i, dump_cr_table[i][0], dump_cr_table[i][1]);
}
for (i = 0; i < table_len; i ++) {
cr_start = dump_cr_table[i][0];
cr_end = dump_cr_table[i][1];
for (addr = cr_start; addr <= cr_end; addr += 4) {
if (dump_2_buff)
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"0x%04x 0x%08x\n",
addr, halbb_get_reg(bb, addr, MASKDWORD));
else
BB_TRACE("0x%04x 0x%08x\n",
addr, halbb_get_reg(bb, addr, MASKDWORD));
}
}
}
void halbb_dbgport_dump_all_8852b(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len)
{
const u32 dump_dbgport_table[][3] = {
{DBGPORT_IP_TD, 0x001, 0x026},
{DBGPORT_IP_TD, 0x200, 0x2ff},
{DBGPORT_IP_TD, 0xb01, 0xb27},
{DBGPORT_IP_RX_INNER, 0x0, 0x29},
{DBGPORT_IP_TX_INNER, 0x0, 0x8},
{DBGPORT_IP_OUTER, 0x0, 0xaa},
{DBGPORT_IP_OUTER, 0xc0, 0xc4},
{DBGPORT_IP_INTF, 0x0, 0x40},
{DBGPORT_IP_CCK, 0x0, 0x3e},
{DBGPORT_IP_BF, 0x0, 0x59},
{DBGPORT_IP_RX_OUTER, 0x00, 0x63},
{DBGPORT_IP_RX_OUTER, 0x90, 0x98},
{DBGPORT_IP_RX_OUTER, 0xc0, 0xc3},
{DBGPORT_IP_RX_OUTER, 0xe0, 0xe3}};
u32 table_len;
u32 dp = 0; /*debug port value*/
u8 i;
u32 j;
u32 dbg_start = 0, dbg_end = 0;
table_len = sizeof(dump_dbgport_table) / (sizeof(u32) * 3);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"BB DBG Port: dump all ==>\n");
for (i = 0; i < table_len; i++) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%02d][IP=%02d] Dbgport[0x%03x ~ 0x%03x]\n",
i, dump_dbgport_table[i][0],
dump_dbgport_table[i][1], dump_dbgport_table[i][2]);
}
for (i = 0; i < table_len; i++) {
halbb_set_bb_dbg_port_ip(bb, dump_dbgport_table[i][0]);
dbg_start = dump_dbgport_table[i][1];
dbg_end = dump_dbgport_table[i][2];
for (j = dbg_start; j <= dbg_end; j ++) {
halbb_set_bb_dbg_port(bb, j);
dp = halbb_get_bb_dbg_port_val(bb);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[0x%02x, 0x%03x] = 0x%08x\n",
dump_dbgport_table[i][0], j, dp);
}
}
halbb_release_bb_dbg_port(bb);
}
void halbb_physts_brk_fail_pkt_rpt_8852b(struct bb_info *bb, bool enable,
enum phl_phy_idx phy_idx)
{
u32 val32 = (enable) ? 0 : 0x3;
halbb_set_reg_cmn(bb, 0x0738, 0xC, 0x3, phy_idx);
}
bool halbb_rf_write_bb_reg_8852b(struct bb_info *bb, u32 addr, u32 mask, u32 data)
{
u32 page = (addr & 0xff00) >> 8;
if (page != 0x0c && page != 0x20 && page != 0x2c &&
page != 0x58 && page != 0x78 &&
addr != 0x0700 && addr != 0x12a0 && addr != 0x12b8 &&
addr != 0x2320 && addr != 0x2700 &&
addr != 0x32a0 && addr != 0x32b8) {
return false;
}
halbb_set_reg(bb, addr, mask, data);
return true;
}
void halbb_pre_agc_en_8852b(struct bb_info *bb, bool enable)
{
u8 en = 0;
en = (enable == true) ? 1 : 0;
halbb_set_reg(bb, 0x4730, BIT(31), en);
halbb_set_reg(bb, 0x4A9C, BIT(31), en);
BB_DBG(bb, DBG_DBG_API, "PreAGC en: 0x4730C[31]=(0x%x),0x4A9C[31]=(0x%x)\n",
en, en);
}
s8 halbb_efuse_exchange_8852b(struct bb_info *bb, u8 value,
enum efuse_bit_mask mask)
{
s8 tmp = 0;
if (mask == LOW_MASK) {
tmp = value & 0xf;
if (tmp & BIT(3))
tmp = tmp | 0xf0;
} else {
tmp = (value & 0xf0) >> 4;
if (tmp & BIT(3))
tmp = tmp | 0xf0;
}
return tmp;
}
void halbb_get_normal_efuse_init_8852b(struct bb_info *bb)
{
struct bb_efuse_info *gain = &bb->bb_efuse_i;
u8 tmp;
u8 tmp_ofst;
u32 check_tmp = 0, i, j;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
tmp_ofst = (u8)halbb_get_reg(bb, 0x49B0, 0xff);
bb->bb_efuse_i.efuse_ofst = (s8)halbb_cnvrt_2_sign(tmp_ofst, 8);
tmp_ofst = (u8)halbb_get_reg(bb, 0x4A00, 0xff);
bb->bb_efuse_i.efuse_ofst_tb = (s8)halbb_cnvrt_2_sign(tmp_ofst, 8);
halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK, &tmp, 1);
gain->gain_offset[RF_PATH_A][0] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK);
gain->gain_offset[RF_PATH_B][0] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD, &tmp, 1);
gain->gain_offset[RF_PATH_A][1] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK);
gain->gain_offset[RF_PATH_B][1] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_5GL, &tmp, 1);
gain->gain_offset[RF_PATH_A][2] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK);
gain->gain_offset[RF_PATH_B][2] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_5GM, &tmp, 1);
gain->gain_offset[RF_PATH_A][3] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK);
gain->gain_offset[RF_PATH_B][3] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_efuse_get_info(bb, EFUSE_INFO_RF_RX_GAIN_K_A_5GH, &tmp, 1);
gain->gain_offset[RF_PATH_A][4] = halbb_efuse_exchange_8852b(bb, tmp, HIGH_MASK);
gain->gain_offset[RF_PATH_B][4] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
for (i = 0; i < HALBB_MAX_PATH; i++) {
for (j = 0; j < BB_EFUSE_BAND_NUM; j++) {
BB_DBG(bb, DBG_INIT, "[Efuse]gain->gain_offset[%d][%d]=0x%x\n", i, j, gain->gain_offset[i][j]);
if ((gain->gain_offset[i][j] & 0xf) == 0xf)
check_tmp++;
}
}
BB_DBG(bb, DBG_INIT, "[Efuse]check_tmp = %d\n", check_tmp);
BB_DBG(bb, DBG_INIT, "[Efuse]HALBB_MAX_PATH * BB_EFUSE_BAND_NUM = %d\n", HALBB_MAX_PATH * BB_EFUSE_BAND_NUM);
if (check_tmp == HALBB_MAX_PATH * BB_EFUSE_BAND_NUM)
bb->bb_efuse_i.normal_efuse_check = false;
else
bb->bb_efuse_i.normal_efuse_check = true;
/*
BB_DBG(bb, DBG_INIT,
"[Efuse][Gain 2G][CCK] Path-A: %d, Path-B: %d\n",
gain->gain_offset[RF_PATH_A][0], gain->gain_offset[RF_PATH_B][0]);
BB_DBG(bb, DBG_INIT,
"[Efuse][Gain 2G][OFDM] Path-A: %d, Path-B: %d\n",
gain->gain_offset[RF_PATH_A][1], gain->gain_offset[RF_PATH_B][1]);
BB_DBG(bb, DBG_INIT,
"[Efuse][Gain 5GL] Path-A: %d, Path-B: %d\n",
gain->gain_offset[RF_PATH_A][2], gain->gain_offset[RF_PATH_B][2]);
BB_DBG(bb, DBG_INIT,
"[Efuse][Gain 5GM] Path-A: %d, Path-B: %d\n",
gain->gain_offset[RF_PATH_A][3], gain->gain_offset[RF_PATH_B][3]);
BB_DBG(bb, DBG_INIT,
"[Efuse][Gain 5GH] Path-A: %d, Path-B: %d\n",
gain->gain_offset[RF_PATH_A][4], gain->gain_offset[RF_PATH_B][4]);
*/
}
void halbb_get_hide_efuse_init_8852b(struct bb_info *bb)
{
struct bb_efuse_info *gain = &bb->bb_efuse_i;
u8 tmp;
u32 check_tmp = 0, i , j;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_2G_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_A][0] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_5GL_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_A][1] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_5GM_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_A][2] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_A_5GH_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_A][3] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_2G_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_B][0] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_5GL_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_B][1] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_5GM_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_B][2] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
halbb_phy_efuse_get_info(bb, GAIN_HIDE_EFUSE_B_5GH_8852B, 1, &tmp);
gain->gain_cs[RF_PATH_B][3] = halbb_efuse_exchange_8852b(bb, tmp, LOW_MASK);
for (i = 0; i < HALBB_MAX_PATH; i++) {
for (j = 0; j < BB_GAIN_BAND_NUM; j++) {
BB_DBG(bb, DBG_INIT, "[Efuse]gain->gain_cs[%d][%d]=0x%x\n", i, j, gain->gain_cs[i][j]);
if ((gain->gain_cs[i][j] & 0xf) == 0xf)
check_tmp++;
}
}
BB_DBG(bb, DBG_INIT, "[Efuse]check_tmp = %d\n", check_tmp);
BB_DBG(bb, DBG_INIT, "[Efuse]HALBB_MAX_PATH * BB_GAIN_BAND_NUM = %d\n", HALBB_MAX_PATH * BB_GAIN_BAND_NUM);
if (check_tmp == HALBB_MAX_PATH * BB_GAIN_BAND_NUM)
bb->bb_efuse_i.hidden_efuse_check = false;
else
bb->bb_efuse_i.hidden_efuse_check = true;
/*
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 2G][Path-A] CS: %d , %d, %x\n",
gain->gain_cs[RF_PATH_A][0],gain->gain_cs[RF_PATH_A][0]<<2,gain->gain_cs[RF_PATH_A][0]<<2);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 5GL][Path-A] CS: %d, %d, %x\n",
gain->gain_cs[RF_PATH_A][1],gain->gain_cs[RF_PATH_A][1]<<2,gain->gain_cs[RF_PATH_A][1]<<2);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 5GM][Path-A] CS: %d, %d, %x\n",
gain->gain_cs[RF_PATH_A][2],gain->gain_cs[RF_PATH_A][2]<<2,gain->gain_cs[RF_PATH_A][2]<<2);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 5GH][Path-A] CS: %d, %d, %x\n",
gain->gain_cs[RF_PATH_A][3],gain->gain_cs[RF_PATH_A][3]<<2,gain->gain_cs[RF_PATH_A][3]<<2);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 2G][Path-B] CS: %d\n",
gain->gain_cs[RF_PATH_B][0]);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 5GL][Path-B] CS: %d\n",
gain->gain_cs[RF_PATH_B][1]);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 5GM][Path-B] CS: %d\n",
gain->gain_cs[RF_PATH_B][2]);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Hidden Efuse][Gain 5GH][Path-B] CS: %d\n",
gain->gain_cs[RF_PATH_B][3]);
*/
}
void halbb_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx)
{
u8 band;
u8 gain_val = 0;
s32 hidden_efuse = 0, normal_efuse = 0, normal_efuse_cck = 0;
s32 tmp = 0;
u8 path = 0;
u32 gain_err_addr[2] = {0x4ACC, 0x4AD8}; //Wait for Bcut Def
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// 2G Band: (0)
// 5G Band: (1):Low, (2): Mid, (3):High
if (central_ch >= 0 && central_ch <= 14)
band = 0;
else if (central_ch >= 36 && central_ch <= 64)
band = 1;
else if (central_ch >= 100 && central_ch <= 144)
band = 2;
else if (central_ch >= 149 && central_ch <= 177)
band = 3;
else
band = 0;
// === [Set hidden efuse] === //
if (bb->bb_efuse_i.hidden_efuse_check) {
for (path = RF_PATH_A; path < BB_PATH_MAX_8852B; path++) {
gain_val = bb->bb_efuse_i.gain_cs[path][band] << 2;
halbb_set_reg(bb, gain_err_addr[path], 0xff, gain_val);
}
BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Hidden efuse dynamic setting!!\n");
} else {
BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Values of hidden efuse are all 0xff, bypass dynamic setting!!\n");
}
// === [Set normal efuse] === //
if (bb->bb_efuse_i.normal_efuse_check) {
if ((bb->rx_path == RF_PATH_A) || (bb->rx_path == RF_PATH_AB)) {
normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_A][band + 1];
normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_A][0];
} else if (bb->rx_path == RF_PATH_B) {
normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_B][band + 1];
normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_B][0];
}
normal_efuse *= (-1);
normal_efuse_cck *= (-1);
// OFDM normal efuse
// r_1_rpl_bias_comp
tmp = (normal_efuse << 4) + bb->bb_efuse_i.efuse_ofst;
halbb_set_reg_cmn(bb, 0x49B0, 0xff, (tmp & 0xff), phy_idx);
// r_tb_rssi_bias_comp
tmp = (normal_efuse << 4) + bb->bb_efuse_i.efuse_ofst_tb;
halbb_set_reg_cmn(bb, 0x4A00, 0xff, (tmp & 0xff), phy_idx);
// CCK normal efuse
if (band == 0) {
tmp = (normal_efuse_cck << 3) + (bb->bb_efuse_i.efuse_ofst >>1);
halbb_set_reg(bb, 0x23ac, 0x7f, (tmp & 0x7f));
}
BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Normal efuse dynamic setting!!\n");
} else {
BB_DBG(bb, DBG_PHY_CONFIG, "[Efuse] Values of normal efuse are all 0xff, bypass dynamic setting!!\n");
}
}
void halbb_set_gain_error_8852b(struct bb_info *bb, u8 central_ch)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u8 band;
u8 path = 0, lna_idx = 0, tia_idx = 0;
s32 tmp = 0;
u32 lna_gain_g[BB_PATH_MAX_8852B][7] = {{0x4678, 0x4678, 0x467C,
0x467C, 0x467C, 0x467C,
0x4680}, {0x475C, 0x475C,
0x4760, 0x4760, 0x4760,
0x4760, 0x4764}};
u32 lna_gain_a[BB_PATH_MAX_8852B][7] = {{0x45DC, 0x45DC, 0x4660,
0x4660, 0x4660, 0x4660,
0x4664}, {0x4740, 0x4740,
0x4744, 0x4744, 0x4744,
0x4744, 0x4748}};
u32 lna_gain_mask[7] = {0x00ff0000, 0xff000000, 0x000000ff,
0x0000ff00, 0x00ff0000, 0xff000000,
0x000000ff};
u32 tia_gain_g[BB_PATH_MAX_8852B][2] = {{0x4680, 0x4680}, {0x4764,
0x4764}};
u32 tia_gain_a[BB_PATH_MAX_8852B][2] = {{0x4664, 0x4664}, {0x4748,
0x4748}};
u32 tia_gain_mask[2] = {0x00ff0000, 0xff000000};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// 2G Band: (0)
// 5G Band: (1):Low, (2): Mid, (3):High
if (central_ch >= 0 && central_ch <= 14)
band = 0;
else if (central_ch >= 36 && central_ch <= 64)
band = 1;
else if (central_ch >= 100 && central_ch <= 144)
band = 2;
else if (central_ch >= 149 && central_ch <= 177)
band = 3;
else
band = 0;
for (path = RF_PATH_A; path < BB_PATH_MAX_8852B; path++) {
for (lna_idx = 0; lna_idx < 7; lna_idx++) {
if (central_ch >= 0 && central_ch <= 14) {
tmp = gain->lna_gain[band][path][lna_idx];
halbb_set_reg(bb, lna_gain_g[path][lna_idx], lna_gain_mask[lna_idx], tmp);
} else {
tmp = gain->lna_gain[band][path][lna_idx];
halbb_set_reg(bb, lna_gain_a[path][lna_idx], lna_gain_mask[lna_idx], tmp);
}
}
for (tia_idx = 0; tia_idx < 2; tia_idx++) {
if (central_ch >= 0 && central_ch <= 14) {
tmp = gain->tia_gain[band][path][tia_idx];
halbb_set_reg(bb, tia_gain_g[path][tia_idx], tia_gain_mask[tia_idx], tmp);
} else {
tmp = gain->tia_gain[band][path][tia_idx];
halbb_set_reg(bb, tia_gain_a[path][tia_idx], tia_gain_mask[tia_idx], tmp);
}
}
}
}
void halbb_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u8 band;
u8 path = 0;
u8 i = 0;
u8 rxsc = 0;
s8 ofst = 0;
s8 bw20_avg = 0;
s8 bw40_avg = 0, bw40_avg_1 = 0, bw40_avg_2 = 0;
s8 bw80_avg = 0;
s8 bw80_avg_1 = 0, bw80_avg_2 = 0, bw80_avg_3 = 0, bw80_avg_4 = 0;
s8 bw80_avg_9 = 0, bw80_avg_10 = 0;
u32 tmp_val1 = 0, tmp_val2 = 0, tmp_val3 = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (central_ch >= 0 && central_ch <= 14) {
band = 0;
} else if (central_ch >= 36 && central_ch <= 64) {
band = 1;
} else if (central_ch >= 100 && central_ch <= 144) {
band = 2;
} else if (central_ch >= 149 && central_ch <= 177) {
band = 3;
} else {
band = 0;
}
//20M RPL
bw20_avg = (gain->rpl_ofst_20[band][RF_PATH_A] +
gain->rpl_ofst_20[band][RF_PATH_B]) >> 1;
tmp_val1 |= (((u32)bw20_avg & 0xff) << 8);
//40M RPL
bw40_avg = (gain->rpl_ofst_40[band][RF_PATH_A][0] +
gain->rpl_ofst_40[band][RF_PATH_B][0]) >> 1;
tmp_val1 |= (((u32)bw40_avg & 0xff) << 16);
bw40_avg_1 = (gain->rpl_ofst_40[band][RF_PATH_A][1] +
gain->rpl_ofst_40[band][RF_PATH_B][1]) >> 1;
tmp_val1 |= (((u32)bw40_avg_1 & 0xff) << 24);
bw40_avg_2 = (gain->rpl_ofst_40[band][RF_PATH_A][2] +
gain->rpl_ofst_40[band][RF_PATH_B][2]) >> 1;
tmp_val2 |= ((u32)bw40_avg_2 & 0xff);
//80M RPL
bw80_avg = (gain->rpl_ofst_80[band][RF_PATH_A][0] +
gain->rpl_ofst_80[band][RF_PATH_B][0]) >> 1;
tmp_val2 |= ((u32)(bw80_avg & 0xff) << 8);
bw80_avg_1 = (gain->rpl_ofst_80[band][RF_PATH_A][1] +
gain->rpl_ofst_80[band][RF_PATH_B][1]) >> 1;
tmp_val2 |= (((u32)bw80_avg_1 & 0xff) << 16);
bw80_avg_10 = (gain->rpl_ofst_80[band][RF_PATH_A][10] +
gain->rpl_ofst_80[band][RF_PATH_B][10]) >> 1;
tmp_val2 |= (((u32)bw80_avg_10 & 0xff) << 24);
bw80_avg_2 = (gain->rpl_ofst_80[band][RF_PATH_A][2] +
gain->rpl_ofst_80[band][RF_PATH_B][2]) >> 1;
tmp_val3 |= ((u32)bw80_avg_2 & 0xff);
bw80_avg_3 = (gain->rpl_ofst_80[band][RF_PATH_A][3] +
gain->rpl_ofst_80[band][RF_PATH_B][3]) >> 1;
tmp_val3 |= (((u32)bw80_avg_3 & 0xff) << 8);
bw80_avg_4 = (gain->rpl_ofst_80[band][RF_PATH_A][4] +
gain->rpl_ofst_80[band][RF_PATH_B][4]) >> 1;
tmp_val3 |= (((u32)bw80_avg_4 & 0xff) << 16);
bw80_avg_9 = (gain->rpl_ofst_80[band][RF_PATH_A][9] +
gain->rpl_ofst_80[band][RF_PATH_B][9]) >> 1;
tmp_val3 |= (((u32)bw80_avg_9 & 0xff) << 24);
BB_DBG(bb, DBG_PHY_CONFIG, "[20M RPL] gain ofst = 0x%2x\n",
bw20_avg&0xff);
BB_DBG(bb, DBG_PHY_CONFIG, "[40M RPL] gain ofst = 0x%2x, 0x%2x, 0x%2x\n",
bw40_avg&0xff, bw40_avg_1&0xff, bw40_avg_2&0xff);
BB_DBG(bb, DBG_PHY_CONFIG, "[80M RPL] gain ofst = 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x\n",
bw80_avg&0xff,bw80_avg_1&0xff,bw80_avg_2&0xff,bw80_avg_3&0xff,bw80_avg_4&0xff,bw80_avg_9&0xff,bw80_avg_10&0xff);
BB_DBG(bb, DBG_PHY_CONFIG, "tmp1 = 0x%x, tmp2 = 0x%x, tmp3 = 0x%x\n",
tmp_val1, tmp_val2, tmp_val3);
halbb_set_reg(bb, 0x49b0, 0xffffff00, tmp_val1 >> 8);
halbb_set_reg(bb, 0x4a00, 0xffffff00, tmp_val1 >> 8);
halbb_set_reg(bb, 0x49b4, MASKDWORD, tmp_val2);
halbb_set_reg(bb, 0x4a04, MASKDWORD, tmp_val2);
halbb_set_reg(bb, 0x49b8, MASKDWORD, tmp_val3);
halbb_set_reg(bb, 0x4a08, MASKDWORD, tmp_val3);
}
void halbb_normal_efuse_verify_8852b(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx)
{
s32 normal_efuse = 0;
s32 tmp = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] rx_gain_offset = %d\n",
rx_gain_offset);
rx_gain_offset *= (-1);
// === [Set normal efuse] === //
// r_1_rpl_bias_comp
tmp = (rx_gain_offset << 4) + bb->bb_efuse_i.efuse_ofst;
halbb_set_reg_cmn(bb, 0x49B0, 0xff, (tmp & 0xff), phy_idx);
// r_tb_rssi_bias_comp
tmp = (rx_gain_offset << 4) + bb->bb_efuse_i.efuse_ofst_tb;
halbb_set_reg_cmn(bb, 0x4A00, 0xff, (bb->bb_efuse_i.efuse_ofst_tb & 0xff), phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] 0x49B0[7:0] = 0x%x\n",
halbb_get_reg(bb, 0x49B0, 0xff));
BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] 0x4A00[7:0] = 0x%x\n",
halbb_get_reg(bb, 0x4A00, 0xff));
}
void halbb_normal_efuse_verify_cck_8852b(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx)
{
s32 tmp = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
rx_gain_offset *= (-1);
tmp = (rx_gain_offset << 3) + (bb->bb_efuse_i.efuse_ofst >>1);
halbb_set_reg(bb, 0x23ac, 0x7f, (tmp & 0x7f));
BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] gain ofst = 0x%x\n",
rx_gain_offset);
BB_DBG(bb, DBG_PHY_CONFIG, "[Normal Efuse] 0x23ac[6:0] = 0x%x\n",
halbb_get_reg(bb, 0x23ac, 0x7f));
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.c
|
C
|
agpl-3.0
| 66,803
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_API_H__
#define __HALBB_8852B_API_H__
#ifdef BB_8852B_SUPPORT
#ifdef HALBB_CONFIG_RUN_IN_DRV
#include "../halbb_api.h"
#endif
/*@--------------------------[Define]-------------------------------------*/
#define INVALID_RF_DATA 0xffffffff
#define BB_PATH_MAX_8852B 2
#define GAIN_HIDE_EFUSE_A_2G_8852B 0x5BB
#define GAIN_HIDE_EFUSE_A_5GL_8852B 0x5BA
#define GAIN_HIDE_EFUSE_A_5GM_8852B 0x5B9
#define GAIN_HIDE_EFUSE_A_5GH_8852B 0x5B8
#define GAIN_HIDE_EFUSE_B_2G_8852B 0x590
#define GAIN_HIDE_EFUSE_B_5GL_8852B 0x58F
#define GAIN_HIDE_EFUSE_B_5GM_8852B 0x58E
#define GAIN_HIDE_EFUSE_B_5GH_8852B 0x58D
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb,
s16 pw_ofst, enum phl_phy_idx phy_idx);
void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx,
enum phl_phy_idx phy_idx);
void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path);
bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path);
#ifdef HALBB_CONFIG_RUN_IN_DRV
void halbb_gpio_ctrl_dump_8852b(struct bb_info *bb);
void halbb_gpio_rfm_8852b(struct bb_info *bb, enum bb_path path,
enum bb_rfe_src_sel src, bool dis_tx_gnt_wl,
bool active_tx_opt, bool act_bt_en, u8 rfm_output_val);
void halbb_gpio_trsw_table_8852b(struct bb_info *bb, enum bb_path path,
bool path_en, bool trsw_tx,
bool trsw_rx, bool trsw, bool trsw_b);
void halbb_gpio_setting_8852b(struct bb_info *bb, u8 gpio_idx,
enum bb_path path, bool inv,
enum bb_rfe_src_sel src);
void halbb_gpio_setting_all_8852b(struct bb_info *bb, u8 rfe_idx);
void halbb_gpio_setting_init_8852b(struct bb_info *bb);
void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_dfs_en_8852b(struct bb_info *bb, bool en);
void halbb_adc_en_8852b(struct bb_info *bb, bool en);
void halbb_tssi_cont_en_8852b(struct bb_info *bb, bool en, enum rf_path path);
void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
u32 halbb_read_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask);
u32 halbb_read_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask);
u32 halbb_read_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask);
bool halbb_write_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data);
bool halbb_write_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data);
bool halbb_write_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask, u32 data);
bool halbb_ctrl_bw_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch,
enum phl_phy_idx phy_idx);
void halbb_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx);
void halbb_ctrl_trx_path_8852b(struct bb_info *bb, enum rf_path tx_path,
u8 tx_nss, enum rf_path rx_path, u8 rx_nss);
void halbb_tssi_bb_reset_8852b(struct bb_info *bb);
u8 halbb_sco_mapping_8852b(struct bb_info *bb, u8 central_ch);
bool halbb_ctrl_sco_cck_8852b(struct bb_info *bb, u8 pri_ch);
bool halbb_bw_setting_8852b(struct bb_info *bb, enum channel_width bw,
enum rf_path path);
bool halbb_ch_setting_8852b(struct bb_info *bb, u8 central_ch, enum rf_path path,
bool *is_2g_ch);
void halbb_ctrl_rf_mode_8852b(struct bb_info *bb, enum phl_rf_mode mode);
bool halbb_ctrl_ch2_80p80_8852b(struct bb_info *bb, u8 central_ch);
void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
void halbb_ctrl_ofdm_en_8852b(struct bb_info *bb, bool ofdm_en,
enum phl_phy_idx phy_idx);
bool halbb_set_txpwr_dbm_8852b(struct bb_info *bb, s16 power_dbm,
enum phl_phy_idx phy_idx);
void halbb_reset_bb_hw_cnt_8852b(struct bb_info *bb);
s16 halbb_get_txpwr_dbm_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
s16 halbb_get_txinfo_txpwr_dbm_8852b(struct bb_info *bb);
bool halbb_set_cck_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path);
u16 halbb_get_cck_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_cck_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path);
bool halbb_set_ofdm_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path);
u16 halbb_get_ofdm_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_ofdm_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path);
void halbb_backup_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_restore_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg);
void halbb_ctrl_btc_preagc_8852b(struct bb_info *bb, bool bt_en);
bool halbb_set_txsc_8852b(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx);
bool halbb_set_bss_color_8852b(struct bb_info *bb, u8 bss_color,
enum phl_phy_idx phy_idx);
bool halbb_set_sta_id_8852b(struct bb_info *bb, u16 sta_id,
enum phl_phy_idx phy_idx);
void halbb_set_igi_8852b(struct bb_info *bb, u8 lna_idx, bool tia_idx,
u8 rxbb_idx, enum rf_path path);
void halbb_set_tx_pow_ref_8852b(struct bb_info *bb, s16 pw_dbm_ofdm,
s16 pw_dbm_cck, s8 ofst,
u8 base_cw_0db, u16 tssi_16dBm_cw,
u16 *ofdm_cw, u16 *cck_cw,
enum phl_phy_idx phy_idx);
void halbb_dump_bb_reg_8852b(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff);
void halbb_dbgport_dump_all_8852b(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len);
void halbb_physts_brk_fail_pkt_rpt_8852b(struct bb_info *bb, bool enable,
enum phl_phy_idx phy_idx);
bool halbb_rf_write_bb_reg_8852b(struct bb_info *bb, u32 addr, u32 mask, u32 data);
void halbb_pre_agc_en_8852b(struct bb_info *bb, bool enable);
void halbb_set_gain_error_8852b(struct bb_info *bb, u8 central_ch);
void halbb_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx);
void halbb_get_normal_efuse_init_8852b(struct bb_info *bb);
void halbb_get_hide_efuse_init_8852b(struct bb_info *bb);
void halbb_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch);
void halbb_normal_efuse_verify_8852b(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
void halbb_normal_efuse_verify_cck_8852b(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
#endif
#endif
#endif /* __INC_PHYDM_API_H_8852A__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api.h
|
C
|
agpl-3.0
| 8,110
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_API_EX_H__
#define __HALBB_8852B_API_EX_H__
#ifdef BB_8852B_SUPPORT
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u16 halbb_cfg_cmac_tx_ant_8852b(struct bb_info *bb, enum rf_path tx_path);
#endif
#endif /* __INC_PHYDM_API_H_8852A__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_8852b_api_ex.h
|
C
|
agpl-3.0
| 1,279
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_CR_INFO_8852B_H_
#define _HALBB_CR_INFO_8852B_H_
#define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
#define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
#define UPD_5MHZ_CNT_EN_C 0x0000
#define UPD_5MHZ_CNT_EN_C_M 0x2
#define CLK_640M_EN_C 0x0000
#define CLK_640M_EN_C_M 0x4
#define RFC_CK_PHASE_SEL_C 0x0000
#define RFC_CK_PHASE_SEL_C_M 0x8
#define RFC_CKEN_C 0x0000
#define RFC_CKEN_C_M 0x10
#define DFS_PATH1_EN_C 0x0000
#define DFS_PATH1_EN_C_M 0x80
#define UPD_5MHZ_PHASE_SEL_P0_C 0x0000
#define UPD_5MHZ_PHASE_SEL_P0_C_M 0x7F00
#define UPD_5MHZ_PHASE_SEL_P0_EN_C 0x0000
#define UPD_5MHZ_PHASE_SEL_P0_EN_C_M 0x8000
#define UPD_5MHZ_PHASE_SEL_P1_C 0x0000
#define UPD_5MHZ_PHASE_SEL_P1_C_M 0x7F0000
#define UPD_5MHZ_PHASE_SEL_P1_EN_C 0x0000
#define UPD_5MHZ_PHASE_SEL_P1_EN_C_M 0x800000
#define CLK_640M_P0_EN_C 0x0000
#define CLK_640M_P0_EN_C_M 0x1000000
#define CLK_640M_P1_EN_C 0x0000
#define CLK_640M_P1_EN_C_M 0x2000000
#define UPD_TOP_CNT_P0_EN_C 0x0000
#define UPD_TOP_CNT_P0_EN_C_M 0x4000000
#define UPD_TOP_CNT_P1_EN_C 0x0000
#define UPD_TOP_CNT_P1_EN_C_M 0x8000000
#define P0_SMALL_BW_EN_C 0x0000
#define P0_SMALL_BW_EN_C_M 0x10000000
#define P1_SMALL_BW_EN_C 0x0000
#define P1_SMALL_BW_EN_C_M 0x20000000
#define EN_UPD_5MHZ_INV_C 0x0000
#define EN_UPD_5MHZ_INV_C_M 0x40000000
#define DFS_EN_C 0x0000
#define DFS_EN_C_M 0x80000000
#define UPD_TD_PHASE_SEL_P0_C 0x0004
#define UPD_TD_PHASE_SEL_P0_C_M 0x1F
#define UPD_TD_PHASE_SEL_P0_EN_C 0x0004
#define UPD_TD_PHASE_SEL_P0_EN_C_M 0x80
#define UPD_TD_PHASE_SEL_P1_C 0x0004
#define UPD_TD_PHASE_SEL_P1_C_M 0x1F00
#define UPD_TD_PHASE_SEL_P1_EN_C 0x0004
#define UPD_TD_PHASE_SEL_P1_EN_C_M 0x8000
#define UPD_IN_PHASE_SEL_P0_C 0x0004
#define UPD_IN_PHASE_SEL_P0_C_M 0x1F0000
#define UPD_IN_PHASE_SEL_P0_EN_C 0x0004
#define UPD_IN_PHASE_SEL_P0_EN_C_M 0x800000
#define UPD_IN_PHASE_SEL_P1_C 0x0004
#define UPD_IN_PHASE_SEL_P1_C_M 0x1F000000
#define UPD_IN_PHASE_SEL_P1_EN_C 0x0004
#define UPD_IN_PHASE_SEL_P1_EN_C_M 0x80000000
#define UPD_OUT_PHASE_SEL_P0_C 0x0008
#define UPD_OUT_PHASE_SEL_P0_C_M 0x1F
#define UPD_OUT_PHASE_SEL_P0_EN_C 0x0008
#define UPD_OUT_PHASE_SEL_P0_EN_C_M 0x80
#define UPD_OUT_PHASE_SEL_P1_C 0x0008
#define UPD_OUT_PHASE_SEL_P1_C_M 0x1F00
#define UPD_OUT_PHASE_SEL_P1_EN_C 0x0008
#define UPD_OUT_PHASE_SEL_P1_EN_C_M 0x8000
#define UPD_MCU_PHASE_SEL_P0_C 0x0008
#define UPD_MCU_PHASE_SEL_P0_C_M 0x1F0000
#define UPD_MCU_PHASE_SEL_P0_EN_C 0x0008
#define UPD_MCU_PHASE_SEL_P0_EN_C_M 0x800000
#define UPD_MCU_PHASE_SEL_P1_C 0x0008
#define UPD_MCU_PHASE_SEL_P1_C_M 0x1F000000
#define UPD_MCU_PHASE_SEL_P1_EN_C 0x0008
#define UPD_MCU_PHASE_SEL_P1_EN_C_M 0x80000000
#define RSTB_WATCH_DOG_P0_EN_C 0x000C
#define RSTB_WATCH_DOG_P0_EN_C_M 0x1
#define RSTB_WATCH_DOG_P1_EN_C 0x000C
#define RSTB_WATCH_DOG_P1_EN_C_M 0x2
#define MAC_RST_P0_EN_C 0x000C
#define MAC_RST_P0_EN_C_M 0x4
#define MAC_RST_P1_EN_C 0x000C
#define MAC_RST_P1_EN_C_M 0x8
#define WMAC_RST_P0_EN_C 0x000C
#define WMAC_RST_P0_EN_C_M 0x10
#define WMAC_RST_P1_EN_C 0x000C
#define WMAC_RST_P1_EN_C_M 0x20
#define P0_PATH_EN_C 0x0010
#define P0_PATH_EN_C_M 0xF
#define P1_PATH_EN_C 0x0010
#define P1_PATH_EN_C_M 0xF0
#define DBG_CKEN_C 0x0010
#define DBG_CKEN_C_M 0x100
#define RX_CKEN_CCK_P0_C 0x0010
#define RX_CKEN_CCK_P0_C_M 0x200
#define RX_CKEN_CCK_P1_C 0x0010
#define RX_CKEN_CCK_P1_C_M 0x400
#define TX_CKEN_CCK_P0_C 0x0010
#define TX_CKEN_CCK_P0_C_M 0x800
#define TX_CKEN_CCK_P1_C 0x0010
#define TX_CKEN_CCK_P1_C_M 0x1000
#define RX_TD_CKEN_OFDM_P0_C 0x0010
#define RX_TD_CKEN_OFDM_P0_C_M 0x2000
#define RX_TD_CKEN_OFDM_P1_C 0x0010
#define RX_TD_CKEN_OFDM_P1_C_M 0x4000
#define TX_TD_CKEN_OFDM_P0_C 0x0010
#define TX_TD_CKEN_OFDM_P0_C_M 0x8000
#define TX_TD_CKEN_OFDM_P1_C 0x0010
#define TX_TD_CKEN_OFDM_P1_C_M 0x10000
#define FORCE_GNT_WL_ON_C 0x0010
#define FORCE_GNT_WL_ON_C_M 0x20000
#define FORCE_GNT_WL_VAL_C 0x0010
#define FORCE_GNT_WL_VAL_C_M 0x40000
#define LA_CKEN_C 0x0014
#define LA_CKEN_C_M 0x1
#define PSD_CKEN_C 0x0014
#define PSD_CKEN_C_M 0x2
#define CCX_CKEN_C 0x0014
#define CCX_CKEN_C_M 0x4
#define IFS_CKEN_C 0x0014
#define IFS_CKEN_C_M 0x8
#define DFS_CKEN_C 0x0014
#define DFS_CKEN_C_M 0x10
#define FTM_CKEN_P0_C 0x0014
#define FTM_CKEN_P0_C_M 0x20
#define FTM_CKEN_P1_C 0x0014
#define FTM_CKEN_P1_C_M 0x40
#define TX_IN_CKEN_P0_C 0x0014
#define TX_IN_CKEN_P0_C_M 0x80
#define TX_IN_CKEN_P1_C 0x0014
#define TX_IN_CKEN_P1_C_M 0x100
#define BF_CKEN_P0_C 0x0014
#define BF_CKEN_P0_C_M 0x200
#define BF_CKEN_P1_C 0x0014
#define BF_CKEN_P1_C_M 0x400
#define SW_SI_CKEN_C 0x0014
#define SW_SI_CKEN_C_M 0x800
#define SW_SI_CK_PHASE_SEL_C 0x0014
#define SW_SI_CK_PHASE_SEL_C_M 0x1000
#define FTM_CKEN_C 0x0014
#define FTM_CKEN_C_M 0x2000
#define SNDCCA_S80_TIE1_C 0x0014
#define SNDCCA_S80_TIE1_C_M 0x80000000
#define PAGE00_18_DUMMY_C 0x0018
#define PAGE00_18_DUMMY_C_M 0xFFFFFFFF
#define PAGE00_1C_DUMMY_C 0x001C
#define PAGE00_1C_DUMMY_C_M 0xFFFFFFFF
#define RSTN_ADC_FIFO_PATH0_C 0x0020
#define RSTN_ADC_FIFO_PATH0_C_M 0xFFFF
#define PAGE00_20_RSV_C 0x0020
#define PAGE00_20_RSV_C_M 0xFFFF0000
#define RSTN_ADC_FIFO_PATH1_C 0x0024
#define RSTN_ADC_FIFO_PATH1_C_M 0xFFFF
#define PAGE00_24_RSV_C 0x0024
#define PAGE00_24_RSV_C_M 0xFFFF0000
#define RSTN_ADC_FIFO_PATH2_C 0x0028
#define RSTN_ADC_FIFO_PATH2_C_M 0xFFFF
#define PAGE00_28_RSV_C 0x0028
#define PAGE00_28_RSV_C_M 0xFFFF0000
#define RSTN_ADC_FIFO_PATH3_C 0x002C
#define RSTN_ADC_FIFO_PATH3_C_M 0xFFFF
#define PAGE00_2C_RSV_C 0x002C
#define PAGE00_2C_RSV_C_M 0xFFFF0000
#define VERSION0_C 0x00F0
#define VERSION0_C_M 0xFFFFFFFF
#define VERSION1_C 0x00F4
#define VERSION1_C_M 0xFFFFFFFF
#define VERSION2_C 0x00F8
#define VERSION2_C_M 0xFFFFFFFF
#define VERSION3_C 0x00FC
#define VERSION3_C_M 0xFFFFFFFF
#define TOP1_ALL_C 0x0100
#define TOP1_ALL_C_M 0xFFFFFFFF
#define INTF_R_MAC_SEL_DMA_C 0x0200
#define INTF_R_MAC_SEL_DMA_C_M 0x3
#define INTF_R_PMAC_CH_INFO_ON_C 0x0200
#define INTF_R_PMAC_CH_INFO_ON_C_M 0x10
#define INTF_R_PMAC_CH_INFO_C 0x0200
#define INTF_R_PMAC_CH_INFO_C_M 0x100
#define INTF_R_INTF_RPT_SEL_P1_C 0x0200
#define INTF_R_INTF_RPT_SEL_P1_C_M 0x1000
#define INTF_R_CH_INFO_EN_P0_C 0x025C
#define INTF_R_CH_INFO_EN_P0_C_M 0x1
#define INTF_R_CH_INFO_EN_P1_C 0x025C
#define INTF_R_CH_INFO_EN_P1_C_M 0x2
#define INTF_R_CH_INFO_DATA_SRC_C 0x025C
#define INTF_R_CH_INFO_DATA_SRC_C_M 0x4
#define INTF_R_COMPRESSION_C 0x025C
#define INTF_R_COMPRESSION_C_M 0x8
#define INTF_R_GRP_NUM_NON_HE_C 0x025C
#define INTF_R_GRP_NUM_NON_HE_C_M 0x30
#define INTF_R_GRP_NUM_HE_C 0x025C
#define INTF_R_GRP_NUM_HE_C_M 0xC0
#define INTF_R_BLOCK_START_IDX_C 0x025C
#define INTF_R_BLOCK_START_IDX_C_M 0xF00
#define INTF_R_BLOCK_END_IDX_C 0x025C
#define INTF_R_BLOCK_END_IDX_C_M 0xF000
#define INTF_R_TEST_CH_INFO_EN_C 0x025C
#define INTF_R_TEST_CH_INFO_EN_C_M 0x10000
#define INTF_R_TEST_SEG_LEN_C 0x025C
#define INTF_R_TEST_SEG_LEN_C_M 0x60000
#define INTF_R_TEST_SEG_NUM_C 0x025C
#define INTF_R_TEST_SEG_NUM_C_M 0x3F80000
#define INTF_R_TEST_VLD_BIT_C 0x025C
#define INTF_R_TEST_VLD_BIT_C_M 0x4000000
#define INTF_R_TEST_DFS_EN_C 0x025C
#define INTF_R_TEST_DFS_EN_C_M 0x8000000
#define INTF_R_TEST_DFS_PERIOD_C 0x025C
#define INTF_R_TEST_DFS_PERIOD_C_M 0xF0000000
#define INTF_R_ELE_BITMAP_C 0x0260
#define INTF_R_ELE_BITMAP_C_M 0xFFFFFFFF
#define INTF_R_TEST_DFS_START_DATA_31_0__C 0x0264
#define INTF_R_TEST_DFS_START_DATA_31_0__C_M 0xFFFFFFFF
#define INTF_R_TEST_DFS_START_DATA_63_32__C 0x0268
#define INTF_R_TEST_DFS_START_DATA_63_32__C_M 0xFFFFFFFF
#define INTF_R_TEST_CH_INFO_START_DATA_31_0__C 0x026C
#define INTF_R_TEST_CH_INFO_START_DATA_31_0__C_M 0xFFFFFFFF
#define INTF_R_TEST_CH_INFO_START_DATA_63_32__C 0x0270
#define INTF_R_TEST_CH_INFO_START_DATA_63_32__C_M 0xFFFFFFFF
#define ANAPAR_PW_0_C 0x0300
#define ANAPAR_PW_0_C_M 0xFF
#define ANAPAR_PW_1_C 0x0300
#define ANAPAR_PW_1_C_M 0xFF00
#define ANAPAR_PW_2_C 0x0300
#define ANAPAR_PW_2_C_M 0xFF0000
#define ANAPAR_PW_3_C 0x0300
#define ANAPAR_PW_3_C_M 0xFF000000
#define ANAPAR_PW_4_C 0x0304
#define ANAPAR_PW_4_C_M 0xFF
#define ANAPAR_PW_5_C 0x0304
#define ANAPAR_PW_5_C_M 0xFF00
#define ANAPAR_PW_6_C 0x0304
#define ANAPAR_PW_6_C_M 0xFF0000
#define ANAPAR_PW_7_C 0x0304
#define ANAPAR_PW_7_C_M 0xFF000000
#define ANAPAR_PW_8_C 0x0308
#define ANAPAR_PW_8_C_M 0xFF
#define ANAPAR_PW_9_C 0x0308
#define ANAPAR_PW_9_C_M 0xFF00
#define ANAPAR_PW_10_C 0x0308
#define ANAPAR_PW_10_C_M 0xFF0000
#define ANAPAR_PW_11_C 0x0308
#define ANAPAR_PW_11_C_M 0xFF000000
#define ANAPAR_PW_12_C 0x030C
#define ANAPAR_PW_12_C_M 0xFF
#define ANAPAR_PW_13_C 0x030C
#define ANAPAR_PW_13_C_M 0xFF00
#define ANAPAR_PW_14_C 0x030C
#define ANAPAR_PW_14_C_M 0xFF0000
#define ANAPAR_PW_15_C 0x030C
#define ANAPAR_PW_15_C_M 0xFF000000
#define ANAPAR_0_C 0x0310
#define ANAPAR_0_C_M 0xFFFF
#define ANAPAR_1_C 0x0310
#define ANAPAR_1_C_M 0xFFFF0000
#define ANAPAR_2_C 0x0314
#define ANAPAR_2_C_M 0xFFFF
#define ANAPAR_3_C 0x0314
#define ANAPAR_3_C_M 0xFFFF0000
#define ANAPAR_4_C 0x0318
#define ANAPAR_4_C_M 0xFFFF
#define ANAPAR_5_C 0x0318
#define ANAPAR_5_C_M 0xFFFF0000
#define ANAPAR_6_C 0x031C
#define ANAPAR_6_C_M 0xFFFF
#define ANAPAR_7_C 0x031C
#define ANAPAR_7_C_M 0xFFFF0000
#define ANAPAR_8_C 0x0320
#define ANAPAR_8_C_M 0xFFFF
#define ANAPAR_9_C 0x0320
#define ANAPAR_9_C_M 0xFFFF0000
#define ANAPAR_10_C 0x0324
#define ANAPAR_10_C_M 0xFFFF
#define ANAPAR_11_C 0x0324
#define ANAPAR_11_C_M 0xFFFF0000
#define ANAPAR_12_C 0x0328
#define ANAPAR_12_C_M 0xFFFF
#define ANAPAR_13_C 0x0328
#define ANAPAR_13_C_M 0xFFFF0000
#define ANAPAR_14_C 0x032C
#define ANAPAR_14_C_M 0xFFFF
#define ANAPAR_15_C 0x032C
#define ANAPAR_15_C_M 0xFFFF0000
#define RFE_E_C 0x0334
#define RFE_E_C_M 0xFFFFFFFF
#define RFE_O_SEL_DBG_C 0x0338
#define RFE_O_SEL_DBG_C_M 0xFFFFFFFF
#define RFE_SEL_PATH_31_0__C 0x033C
#define RFE_SEL_PATH_31_0__C_M 0xFFFFFFFF
#define RFE_SEL_PATH_63_32__C 0x0340
#define RFE_SEL_PATH_63_32__C_M 0xFFFFFFFF
#define RFE_SEL_DBG_MAC1_C 0x0344
#define RFE_SEL_DBG_MAC1_C_M 0xFFFFFFFF
#define DLYSEL0_PINMUX_I_C 0x034C
#define DLYSEL0_PINMUX_I_C_M 0xFFFF
#define DLYSEL1_PINMUX_I_C 0x034C
#define DLYSEL1_PINMUX_I_C_M 0xFFFF0000
#define DLYSEL0_PINMUX_O_C 0x0350
#define DLYSEL0_PINMUX_O_C_M 0xFFFF
#define DLYSEL1_PINMUX_O_C 0x0350
#define DLYSEL1_PINMUX_O_C_M 0xFFFF0000
#define DBG_GPIO_SEL_P0_C 0x0354
#define DBG_GPIO_SEL_P0_C_M 0xF
#define DBG_GPIO_SEL_P1_C 0x0354
#define DBG_GPIO_SEL_P1_C_M 0xF0
#define DBG_GPIO_MAC_SEL_C 0x0354
#define DBG_GPIO_MAC_SEL_C_M 0xFF00
#define TEST_PIN_OE_C 0x0354
#define TEST_PIN_OE_C_M 0xFFFF0000
#define PINMUX_SEL_C 0x0358
#define PINMUX_SEL_C_M 0x1F
#define AFE_DEB_INFILTER_MSB_LSB_C 0x0358
#define AFE_DEB_INFILTER_MSB_LSB_C_M 0x20
#define AFE_DEB_PREFILTER_MSB_LSB_C 0x0358
#define AFE_DEB_PREFILTER_MSB_LSB_C_M 0x40
#define MBIST_PINMUX_SEL_C 0x0358
#define MBIST_PINMUX_SEL_C_M 0x1F00
#define AFE_UPD80_PHASE_C 0x0358
#define AFE_UPD80_PHASE_C_M 0x2000
#define AFE_DBG_SRAM_FREQ_C 0x0358
#define AFE_DBG_SRAM_FREQ_C_M 0xC000
#define LO_SEL_80P80_C 0x035C
#define LO_SEL_80P80_C_M 0x3
#define LO_SEL_2X2_C 0x035C
#define LO_SEL_2X2_C_M 0xC
#define LO_SEL_1X1_C 0x035C
#define LO_SEL_1X1_C_M 0x30
#define LO_SEL_DBCC_C 0x035C
#define LO_SEL_DBCC_C_M 0xC0
#define LO_SEL_HWEN_C 0x035C
#define LO_SEL_HWEN_C_M 0x100
#define LO_SEL_SW_C 0x035C
#define LO_SEL_SW_C_M 0xC00
#define LO_SEL_CH20_INV_C 0x035C
#define LO_SEL_CH20_INV_C_M 0x1000
#define DIS_CCK_CCA_TO_RFC_C 0x035C
#define DIS_CCK_CCA_TO_RFC_C_M 0x10000
#define DIS_OFDM_CCA_TO_RFC_C 0x035C
#define DIS_OFDM_CCA_TO_RFC_C_M 0x20000
#define RSTB_AFC_3WIRE_C 0x0360
#define RSTB_AFC_3WIRE_C_M 0x1
#define AFC_SI_WADDR_C 0x0360
#define AFC_SI_WADDR_C_M 0x3FF0
#define RST_AFC_SI_CONFLICT_CNT_C 0x0360
#define RST_AFC_SI_CONFLICT_CNT_C_M 0x80000000
#define AFC_SI_RADDR_C 0x0364
#define AFC_SI_RADDR_C_M 0x3FF
#define AFC_SI_WDATA_C 0x0368
#define AFC_SI_WDATA_C_M 0xFFFFFFFF
#define HW_SI_CLK_START_PHASE_C 0x036C
#define HW_SI_CLK_START_PHASE_C_M 0x1
#define RSTB_HW_SI_CLK_C 0x036C
#define RSTB_HW_SI_CLK_C_M 0x2
#define HW_SI_HALF_SPEED_EN_C 0x036C
#define HW_SI_HALF_SPEED_EN_C_M 0x10
#define SW_SI_HALF_SPEED_EN_C 0x036C
#define SW_SI_HALF_SPEED_EN_C_M 0x20
#define SW_SI_DATA_C 0x0370
#define SW_SI_DATA_C_M 0xFFFFFFFF
#define SW_SI_BIT_MASK_C 0x0374
#define SW_SI_BIT_MASK_C_M 0xFFFFF
#define RSTB_SW_SI_C 0x0374
#define RSTB_SW_SI_C_M 0x100000
#define SW_SI_CLK_START_PHASE_C 0x0374
#define SW_SI_CLK_START_PHASE_C_M 0x200000
#define SW_SI_DATA_E_INV_C 0x0374
#define SW_SI_DATA_E_INV_C_M 0x400000
#define SW_SI_ZERO_PADDING_EN_C 0x0374
#define SW_SI_ZERO_PADDING_EN_C_M 0x800000
#define SW_SI_ZERO_PADDING_NUM_C 0x0374
#define SW_SI_ZERO_PADDING_NUM_C_M 0x3F000000
#define RST_SW_SI_CONFLICT_CNT_C 0x0374
#define RST_SW_SI_CONFLICT_CNT_C_M 0x80000000
#define SW_SI_READ_ADDR_C 0x0378
#define SW_SI_READ_ADDR_C_M 0x7FF
#define SW_SI_WAIT_TIMING_C 0x037C
#define SW_SI_WAIT_TIMING_C_M 0xF
#define SW_SI_READ_EDGE_OPT_C 0x037C
#define SW_SI_READ_EDGE_OPT_C_M 0x30
#define SW_SI_DIS_W_TRIG_C 0x037C
#define SW_SI_DIS_W_TRIG_C_M 0x1000
#define SW_SI_DIS_R_TRIG_C 0x037C
#define SW_SI_DIS_R_TRIG_C_M 0x2000
#define HWSI_KEEPER_RSTB_C 0x0380
#define HWSI_KEEPER_RSTB_C_M 0x1
#define SWSI_KEEPER_RSTB_C 0x0380
#define SWSI_KEEPER_RSTB_C_M 0x2
#define HWSI_KEEPER_SEL_PATH_C 0x0380
#define HWSI_KEEPER_SEL_PATH_C_M 0x30
#define CCA_MASK_EN_C 0x0600
#define CCA_MASK_EN_C_M 0xFFFFFFFF
#define TIME_CCA_MASK_RX_I_C 0x0604
#define TIME_CCA_MASK_RX_I_C_M 0x3F
#define TIME_CCA_MASK_BRK_I_C 0x0604
#define TIME_CCA_MASK_BRK_I_C_M 0x3F00
#define TIME_CCA_MASK_BRK_CCK_I_C 0x0604
#define TIME_CCA_MASK_BRK_CCK_I_C_M 0x3F0000
#define TIME_CCA_MASK_RIFS_I_C 0x0604
#define TIME_CCA_MASK_RIFS_I_C_M 0x3F000000
#define TIME_CCA_MASK_HT_I_C 0x0608
#define TIME_CCA_MASK_HT_I_C_M 0x3F
#define TIME_CCA_MASK_T2R_I_C 0x0608
#define TIME_CCA_MASK_T2R_I_C_M 0x3F00
#define TIME_CCA_MASK_T2R_TB_I_C 0x0608
#define TIME_CCA_MASK_T2R_TB_I_C_M 0x3F0000
#define TIME_CCA_MASK_T2R_TXTP_I_C 0x0608
#define TIME_CCA_MASK_T2R_TXTP_I_C_M 0x3F000000
#define TIME_CCA_MASK_RX_NDP_I_C 0x060C
#define TIME_CCA_MASK_RX_NDP_I_C_M 0x3F
#define CCA_MASK_T2R_TXTP_I_C 0x060C
#define CCA_MASK_T2R_TXTP_I_C_M 0x3F0000
#define CCA_MASK_T2R_EN_I_C 0x060C
#define CCA_MASK_T2R_EN_I_C_M 0x400000
#define CCA_MASK_T2R_TB_EN_I_C 0x060C
#define CCA_MASK_T2R_TB_EN_I_C_M 0x800000
#define CCA_MASK_T2R_MURTS_EN_I_C 0x060C
#define CCA_MASK_T2R_MURTS_EN_I_C_M 0x1000000
#define CCA_MASK_T2R_TXTP_EN_I_C 0x060C
#define CCA_MASK_T2R_TXTP_EN_I_C_M 0x2000000
#define CCA_MASK_BRK_EN_I_C 0x060C
#define CCA_MASK_BRK_EN_I_C_M 0x4000000
#define CCA_MASK_BRK_CCK_EN_I_C 0x060C
#define CCA_MASK_BRK_CCK_EN_I_C_M 0x8000000
#define CCA_MASK_SEARCH_FAILED_EN_I_C 0x060C
#define CCA_MASK_SEARCH_FAILED_EN_I_C_M 0x10000000
#define CCA_MASK_RIFS_EN_I_C 0x060C
#define CCA_MASK_RIFS_EN_I_C_M 0x20000000
#define CCA_MASK_HT_EN_I_C 0x060C
#define CCA_MASK_HT_EN_I_C_M 0x40000000
#define R1B_CCA_MASK_EN_C 0x0610
#define R1B_CCA_MASK_EN_C_M 0xFFFFFFFF
#define TIME_B_CCA_MASK_RX_I_C 0x0614
#define TIME_B_CCA_MASK_RX_I_C_M 0x3F
#define TIME_B_CCA_MASK_BRK_I_C 0x0614
#define TIME_B_CCA_MASK_BRK_I_C_M 0x3F00
#define TIME_B_CCA_MASK_BRK_CCK_I_C 0x0614
#define TIME_B_CCA_MASK_BRK_CCK_I_C_M 0x3F0000
#define TIME_B_CCA_MASK_RIFS_I_C 0x0614
#define TIME_B_CCA_MASK_RIFS_I_C_M 0x3F000000
#define TIME_B_CCA_MASK_HT_I_C 0x0618
#define TIME_B_CCA_MASK_HT_I_C_M 0x3F
#define TIME_B_CCA_MASK_T2R_I_C 0x0618
#define TIME_B_CCA_MASK_T2R_I_C_M 0x3F00
#define TIME_B_CCA_MASK_T2R_TB_I_C 0x0618
#define TIME_B_CCA_MASK_T2R_TB_I_C_M 0x3F0000
#define TIME_B_CCA_MASK_T2R_TXTP_I_C 0x0618
#define TIME_B_CCA_MASK_T2R_TXTP_I_C_M 0x3F000000
#define TIME_B_CCA_MASK_RX_NDP_I_C 0x061C
#define TIME_B_CCA_MASK_RX_NDP_I_C_M 0x3F
#define R1B_CCA_MASK_T2R_TXTP_I_C 0x061C
#define R1B_CCA_MASK_T2R_TXTP_I_C_M 0x3F0000
#define R1B_CCA_MASK_T2R_EN_I_C 0x061C
#define R1B_CCA_MASK_T2R_EN_I_C_M 0x400000
#define R1B_CCA_MASK_T2R_TB_EN_I_C 0x061C
#define R1B_CCA_MASK_T2R_TB_EN_I_C_M 0x800000
#define R1B_CCA_MASK_T2R_MURTS_EN_I_C 0x061C
#define R1B_CCA_MASK_T2R_MURTS_EN_I_C_M 0x1000000
#define R1B_CCA_MASK_T2R_TXTP_EN_I_C 0x061C
#define R1B_CCA_MASK_T2R_TXTP_EN_I_C_M 0x2000000
#define R1B_CCA_MASK_BRK_EN_I_C 0x061C
#define R1B_CCA_MASK_BRK_EN_I_C_M 0x4000000
#define R1B_CCA_MASK_BRK_CCK_EN_I_C 0x061C
#define R1B_CCA_MASK_BRK_CCK_EN_I_C_M 0x8000000
#define R1B_CCA_MASK_SEARCH_FAILED_EN_I_C 0x061C
#define R1B_CCA_MASK_SEARCH_FAILED_EN_I_C_M 0x10000000
#define R1B_CCA_MASK_RIFS_EN_I_C 0x061C
#define R1B_CCA_MASK_RIFS_EN_I_C_M 0x20000000
#define R1B_CCA_MASK_HT_EN_I_C 0x061C
#define R1B_CCA_MASK_HT_EN_I_C_M 0x40000000
#define EN_RXHP_H2L_C 0x0620
#define EN_RXHP_H2L_C_M 0x1
#define EN_KEEP_AGC_FOR_RIFS_C 0x0620
#define EN_KEEP_AGC_FOR_RIFS_C_M 0x2
#define PWSAV_RIFS_C 0x0620
#define PWSAV_RIFS_C_M 0x4
#define EN_TB_FAIL_C 0x0620
#define EN_TB_FAIL_C_M 0x8
#define RFON_END_CCK_C 0x0620
#define RFON_END_CCK_C_M 0xF0
#define RFON_END_OFDM_C 0x0620
#define RFON_END_OFDM_C_M 0x3F00
#define RIFS_END_C 0x0620
#define RIFS_END_C_M 0x3F0000
#define TIME_TX_TO_RX_END_C 0x0624
#define TIME_TX_TO_RX_END_C_M 0x3F
#define TIME_RXHP_H2L_C 0x0624
#define TIME_RXHP_H2L_C_M 0x3F00
#define TIME_RX_NDP_END_C 0x0624
#define TIME_RX_NDP_END_C_M 0x3F0000
#define TIME_RX_CCK_END_C 0x0624
#define TIME_RX_CCK_END_C_M 0x3F000000
#define TIME_RX_OFDM_END_C 0x0628
#define TIME_RX_OFDM_END_C_M 0x3F
#define TIME_RX_BRK_END_C 0x0628
#define TIME_RX_BRK_END_C_M 0x3F00
#define TIME_RX2RX_HE_TB_END_C 0x0628
#define TIME_RX2RX_HE_TB_END_C_M 0x3F0000
#define TIME_HE_PE04U_I_C 0x062C
#define TIME_HE_PE04U_I_C_M 0x7FF
#define TIME_HE_PE08U_I_C 0x062C
#define TIME_HE_PE08U_I_C_M 0x7FF0000
#define TIME_HE_PE12U_I_C 0x0630
#define TIME_HE_PE12U_I_C_M 0x7FF
#define TIME_HE_PE16U_I_C 0x0630
#define TIME_HE_PE16U_I_C_M 0x7FF0000
#define RX_TD_CKEN_C 0x0634
#define RX_TD_CKEN_C_M 0xFFFF
#define RX_T2F_CKEN_C 0x0634
#define RX_T2F_CKEN_C_M 0xFFFF0000
#define RX_IN_CKEN_C 0x0638
#define RX_IN_CKEN_C_M 0x1
#define RX_OUT_CKEN_C 0x0638
#define RX_OUT_CKEN_C_M 0x2
#define TX_CKEN_CCK_C 0x0638
#define TX_CKEN_CCK_C_M 0x4
#define TX_CKEN_OFDM_C 0x0638
#define TX_CKEN_OFDM_C_M 0x8
#define TX_OFDM_DLY_C 0x063C
#define TX_OFDM_DLY_C_M 0xF
#define TX_CCK_DLY_C 0x063C
#define TX_CCK_DLY_C_M 0xF0
#define TX_OFDM_RF_DLY_160_C 0x0640
#define TX_OFDM_RF_DLY_160_C_M 0x7F
#define TX_OFDM_RF_DLY_80_C 0x0640
#define TX_OFDM_RF_DLY_80_C_M 0x7F00
#define TX_OFDM_RF_DLY_40_C 0x0640
#define TX_OFDM_RF_DLY_40_C_M 0x7F0000
#define TX_OFDM_RF_DLY_20_C 0x0640
#define TX_OFDM_RF_DLY_20_C_M 0x7F000000
#define TX_OFDM_PATH_DLY_160_C 0x0644
#define TX_OFDM_PATH_DLY_160_C_M 0x7F
#define TX_OFDM_PATH_DLY_80_C 0x0644
#define TX_OFDM_PATH_DLY_80_C_M 0x7F00
#define TX_OFDM_PATH_DLY_40_C 0x0644
#define TX_OFDM_PATH_DLY_40_C_M 0x7F0000
#define TX_OFDM_PATH_DLY_20_C 0x0644
#define TX_OFDM_PATH_DLY_20_C_M 0x7F000000
#define TX_CCK_RF_DLY_160_C 0x0648
#define TX_CCK_RF_DLY_160_C_M 0x7F
#define TX_CCK_RF_DLY_80_C 0x0648
#define TX_CCK_RF_DLY_80_C_M 0x7F00
#define TX_CCK_RF_DLY_40_C 0x0648
#define TX_CCK_RF_DLY_40_C_M 0x7F0000
#define TX_CCK_RF_DLY_20_C 0x0648
#define TX_CCK_RF_DLY_20_C_M 0x7F000000
#define TX_CCK_PATH_DLY_160_C 0x064C
#define TX_CCK_PATH_DLY_160_C_M 0x7F
#define TX_CCK_PATH_DLY_80_C 0x064C
#define TX_CCK_PATH_DLY_80_C_M 0x7F00
#define TX_CCK_PATH_DLY_40_C 0x064C
#define TX_CCK_PATH_DLY_40_C_M 0x7F0000
#define TX_CCK_PATH_DLY_20_C 0x064C
#define TX_CCK_PATH_DLY_20_C_M 0x7F000000
#define AFE_DATA_MASK_EN_C 0x0650
#define AFE_DATA_MASK_EN_C_M 0xFFFFFFFF
#define AFE_DATA_MASK_TH_SEL_C 0x0654
#define AFE_DATA_MASK_TH_SEL_C_M 0xFFFFFFFF
#define AFE_DATA_MASK_TH0_C 0x0658
#define AFE_DATA_MASK_TH0_C_M 0xFF
#define AFE_DATA_MASK_TH1_C 0x0658
#define AFE_DATA_MASK_TH1_C_M 0xFF00
#define AFE_DATA_MASK_TH2_C 0x0658
#define AFE_DATA_MASK_TH2_C_M 0xFF0000
#define AFE_DATA_MASK_TH3_C 0x0658
#define AFE_DATA_MASK_TH3_C_M 0xFF000000
#define MONITOR_SEL0_C 0x065C
#define MONITOR_SEL0_C_M 0xF
#define MONITOR_SEL1_C 0x065C
#define MONITOR_SEL1_C_M 0xF0
#define MONITOR_KEEP_C 0x065C
#define MONITOR_KEEP_C_M 0x80000000
#define REDUCE_PEAK_PW_EN_C 0x0660
#define REDUCE_PEAK_PW_EN_C_M 0x1
#define STOP_CLK_C 0x0700
#define STOP_CLK_C_M 0x1
#define SYNC_UPD_5MHZ_C 0x0700
#define SYNC_UPD_5MHZ_C_M 0x2
#define SMALL_BW_C 0x0700
#define SMALL_BW_C_M 0xC
#define ENABLE_OFDM_C 0x0700
#define ENABLE_OFDM_C_M 0x10
#define ENABLE_CCK_C 0x0700
#define ENABLE_CCK_C_M 0x20
#define ENABKE_LPS_CCK_C 0x0700
#define ENABKE_LPS_CCK_C_M 0x40
#define ENABLE_LPS_OFDM_C 0x0700
#define ENABLE_LPS_OFDM_C_M 0x80
#define R55MHZ_PHASE_C 0x0700
#define R55MHZ_PHASE_C_M 0x7F00
#define DIS_CLK_SOURCE_C 0x0700
#define DIS_CLK_SOURCE_C_M 0xFF0000
#define UPD_CLK_ADC_FORCE_ON_C 0x0700
#define UPD_CLK_ADC_FORCE_ON_C_M 0x1000000
#define UPD_CLK_ADC_FORCE_VAL_C 0x0700
#define UPD_CLK_ADC_FORCE_VAL_C_M 0x6000000
#define TD_UPD_GEN_FORCE_ON_C 0x0700
#define TD_UPD_GEN_FORCE_ON_C_M 0x8000000
#define RSTN_EARLY_RELEASE_C 0x0700
#define RSTN_EARLY_RELEASE_C_M 0xF0000000
#define RSTB_ASYNC_UPDGEN_C 0x0704
#define RSTB_ASYNC_UPDGEN_C_M 0x1
#define RSTB_ASYNC_ALL_C 0x0704
#define RSTB_ASYNC_ALL_C_M 0x2
#define RSTB_ASYNC_RXTD_C 0x0704
#define RSTB_ASYNC_RXTD_C_M 0x4
#define RSTB_ASYNC_TXTD_C 0x0704
#define RSTB_ASYNC_TXTD_C_M 0x8
#define RSTB_ASYNC_RXFD_C 0x0704
#define RSTB_ASYNC_RXFD_C_M 0x10
#define RSTB_ASYNC_TXFD_C 0x0704
#define RSTB_ASYNC_TXFD_C_M 0x20
#define RSTB_ASYNC_TX_OUT_C 0x0704
#define RSTB_ASYNC_TX_OUT_C_M 0x40
#define RSTB_ASYNC_RX_OUT_C 0x0704
#define RSTB_ASYNC_RX_OUT_C_M 0x80
#define UPD_CLK_ADC_TX_C 0x0704
#define UPD_CLK_ADC_TX_C_M 0x300
#define FTM_LBK_RFTXEN_CTL_EN_C 0x0704
#define FTM_LBK_RFTXEN_CTL_EN_C_M 0x400
#define RFTXEN_START_DLY_50NS_EN_C 0x0704
#define RFTXEN_START_DLY_50NS_EN_C_M 0x800
#define RST_HIT_ON_TX_EN_C 0x0704
#define RST_HIT_ON_TX_EN_C_M 0x1000
#define RSTN_DAC_FIFO_C 0x0704
#define RSTN_DAC_FIFO_C_M 0xFFFF0000
#define EN_POP_PRD_RST_ADC_FIFO_I_C 0x0708
#define EN_POP_PRD_RST_ADC_FIFO_I_C_M 0x1
#define RSTB_ASYNC_DAC_C 0x070C
#define RSTB_ASYNC_DAC_C_M 0xFFFFFFFF
#define PERIOD_CNT_EN_C 0x0710
#define PERIOD_CNT_EN_C_M 0x1
#define PERIOD_CNT_RST_C 0x0710
#define PERIOD_CNT_RST_C_M 0x2
#define PERIOD_UNIT_SEL_S1_C 0x0710
#define PERIOD_UNIT_SEL_S1_C_M 0x30
#define PERIOD_UNIT_SEL_S2_C 0x0710
#define PERIOD_UNIT_SEL_S2_C_M 0xC0
#define PERIOD_UNIT_SEL_S3_C 0x0710
#define PERIOD_UNIT_SEL_S3_C_M 0x300
#define PERIOD_UNIT_SEL_S4_C 0x0710
#define PERIOD_UNIT_SEL_S4_C_M 0xC00
#define PERIOD_KEEP_COND_S1_C 0x0710
#define PERIOD_KEEP_COND_S1_C_M 0x1000
#define PERIOD_KEEP_COND_S2_C 0x0710
#define PERIOD_KEEP_COND_S2_C_M 0x2000
#define PERIOD_KEEP_COND_S3_C 0x0710
#define PERIOD_KEEP_COND_S3_C_M 0x4000
#define PERIOD_KEEP_COND_S4_C 0x0710
#define PERIOD_KEEP_COND_S4_C_M 0x8000
#define RSTN_ADC_FIFO_C 0x0710
#define RSTN_ADC_FIFO_C_M 0xFFFF0000
#define IDX_EN_BY_MUX_ST_C 0x0714
#define IDX_EN_BY_MUX_ST_C_M 0x3F
#define EN_BY_MUX_ST_C 0x0714
#define EN_BY_MUX_ST_C_M 0x40
#define FILL_EN_BY_MUX_ST_C 0x0714
#define FILL_EN_BY_MUX_ST_C_M 0x80
#define VAL_EN_BY_MUX_ST_C 0x0714
#define VAL_EN_BY_MUX_ST_C_M 0xFF00
#define APPLY_MUX_ST_C 0x0714
#define APPLY_MUX_ST_C_M 0x10000
#define LBK_C 0x0714
#define LBK_C_M 0x20000
#define LBK_MODE_C 0x0714
#define LBK_MODE_C_M 0x40000
#define ST_CCA_BYPASS_C 0x0714
#define ST_CCA_BYPASS_C_M 0x80000
#define PMAC_MOD_C 0x0714
#define PMAC_MOD_C_M 0x100000
#define PMAC_C 0x0714
#define PMAC_C_M 0x200000
#define PMAC_CORX_C 0x0714
#define PMAC_CORX_C_M 0x400000
#define PMAC_TX_C 0x0714
#define PMAC_TX_C_M 0x800000
#define PERIOD_R2R_C 0x0714
#define PERIOD_R2R_C_M 0xFF000000
#define DLY_EN_BY_MUX_ST_C 0x0718
#define DLY_EN_BY_MUX_ST_C_M 0xFFFFFFFF
#define SYMB_NUM_PKT_FMT_C 0x071C
#define SYMB_NUM_PKT_FMT_C_M 0xFF
#define SAMPLE_NUM_PKT_FMT_C 0x071C
#define SAMPLE_NUM_PKT_FMT_C_M 0xFF00
#define SYMB_NUM_CCA_C 0x071C
#define SYMB_NUM_CCA_C_M 0xFF0000
#define SAMPLE_NUM_CCA_C 0x071C
#define SAMPLE_NUM_CCA_C_M 0xFF000000
#define DBG_FPGA_C 0x0720
#define DBG_FPGA_C_M 0xFFF
#define RSTB_FPGA_C 0x0720
#define RSTB_FPGA_C_M 0x1000
#define CBW_FPGA_C 0x0720
#define CBW_FPGA_C_M 0xE000
#define PRICH_FPGA_C 0x0720
#define PRICH_FPGA_C_M 0xF0000
#define PATH_EN_FPGA_C 0x0720
#define PATH_EN_FPGA_C_M 0xF00000
#define PATH_EN_1RCCA_FPGA_C 0x0720
#define PATH_EN_1RCCA_FPGA_C_M 0xF000000
#define INVERSE_ADC_SIGN_BIT_C 0x0720
#define INVERSE_ADC_SIGN_BIT_C_M 0x10000000
#define INVERSE_WB_ADC_SIGN_BIT_C 0x0720
#define INVERSE_WB_ADC_SIGN_BIT_C_M 0x20000000
#define CHANGE_PHASE_FPGA_ADC_C 0x0720
#define CHANGE_PHASE_FPGA_ADC_C_M 0x40000000
#define CHANGE_PHASE_FPGA_WB_ADC_C 0x0720
#define CHANGE_PHASE_FPGA_WB_ADC_C_M 0x80000000
#define RFTXEN_START_C 0x0724
#define RFTXEN_START_C_M 0xF
#define RFTXEN_END_C 0x0724
#define RFTXEN_END_C_M 0xF0
#define PAPE_START_C 0x0724
#define PAPE_START_C_M 0xF00
#define PAPE_END_C 0x0724
#define PAPE_END_C_M 0xF000
#define TRSW_START_C 0x0724
#define TRSW_START_C_M 0xF0000
#define TRSW_END_C 0x0724
#define TRSW_END_C_M 0xF00000
#define LNAOFF_START_C 0x0724
#define LNAOFF_START_C_M 0xF000000
#define LNAOFF_END_C 0x0724
#define LNAOFF_END_C_M 0xF0000000
#define TRSW_TX_EXTEND_C 0x0728
#define TRSW_TX_EXTEND_C_M 0xF
#define PMAC_GNT_BT_C 0x0728
#define PMAC_GNT_BT_C_M 0x10
#define GNT_BT_C 0x0728
#define GNT_BT_C_M 0x20
#define GNT_BT_TX_C 0x0728
#define GNT_BT_TX_C_M 0x40
#define GNT_WL_C 0x0728
#define GNT_WL_C_M 0x80
#define RFAFE_PWSAV_EN_C 0x0728
#define RFAFE_PWSAV_EN_C_M 0x100
#define RFAFE_PWSAV_SEL_SLEEP_C 0x0728
#define RFAFE_PWSAV_SEL_SLEEP_C_M 0x200
#define RSTB_STANDBY_C 0x0728
#define RSTB_STANDBY_C_M 0x400
#define CCAMASK_TXDIS_C 0x0728
#define CCAMASK_TXDIS_C_M 0x800
#define HW_ANTSW_DIS_BY_GNT_BT_C 0x0728
#define HW_ANTSW_DIS_BY_GNT_BT_C_M 0x1000
#define NOTRSW_BT_C 0x0728
#define NOTRSW_BT_C_M 0x2000
#define IGNORE_MAC_ID_C 0x0728
#define IGNORE_MAC_ID_C_M 0x4000
#define ANTSEL_WATCHDOG_EN_C 0x0728
#define ANTSEL_WATCHDOG_EN_C_M 0x8000
#define ANTSEL_WATCHDOG_OPT_C 0x0728
#define ANTSEL_WATCHDOG_OPT_C_M 0x30000
#define ANTSEL_WATCHDOG_TH_EXT_C 0x0728
#define ANTSEL_WATCHDOG_TH_EXT_C_M 0xC0000
#define ANTSEL_WATCHDOG_TH_C 0x0728
#define ANTSEL_WATCHDOG_TH_C_M 0x300000
#define MAC_ID_MATCH_C 0x0728
#define MAC_ID_MATCH_C_M 0x400000
#define LTE_RX_C 0x0728
#define LTE_RX_C_M 0x800000
#define CCK_HIGHPW_C 0x0728
#define CCK_HIGHPW_C_M 0x1000000
#define AAGC_BY_TABLE_C 0x0728
#define AAGC_BY_TABLE_C_M 0x2000000
#define EN_LNA_TRSW_C 0x0728
#define EN_LNA_TRSW_C_M 0x4000000
#define EN_ANTSEL_CCK_C 0x0728
#define EN_ANTSEL_CCK_C_M 0x8000000
#define IBADC_SHIFT_FPGA_C 0x0728
#define IBADC_SHIFT_FPGA_C_M 0x30000000
#define WBADC_SHIFT_FPGA_C 0x0728
#define WBADC_SHIFT_FPGA_C_M 0xC0000000
#define BT_TRXMODE_C 0x072C
#define BT_TRXMODE_C_M 0xFFFF
#define BT_TXMODE_C 0x072C
#define BT_TXMODE_C_M 0xFFFF0000
#define RST_ALL_CNT_C 0x0730
#define RST_ALL_CNT_C_M 0x1
#define ENABLE_ALL_CNT_C 0x0730
#define ENABLE_ALL_CNT_C_M 0x2
#define PERIOD_KEEP_EN_S1_C 0x0730
#define PERIOD_KEEP_EN_S1_C_M 0x10
#define PERIOD_KEEP_EN_S2_C 0x0730
#define PERIOD_KEEP_EN_S2_C_M 0x20
#define PERIOD_KEEP_EN_S3_C 0x0730
#define PERIOD_KEEP_EN_S3_C_M 0x40
#define PERIOD_KEEP_EN_S4_C 0x0730
#define PERIOD_KEEP_EN_S4_C_M 0x80
#define BRK_SEL_FOR_CNT_C 0x0730
#define BRK_SEL_FOR_CNT_C_M 0xFF00
#define CNT_PWDB_TH_C 0x0730
#define CNT_PWDB_TH_C_M 0xFFFF0000
#define MAC_PIN_SEL_C 0x0734
#define MAC_PIN_SEL_C_M 0xFFFF
#define CH_IDX_SEG0_C 0x0734
#define CH_IDX_SEG0_C_M 0xFF0000
#define CH_IDX_SEG1_C 0x0734
#define CH_IDX_SEG1_C_M 0xFF000000
#define PLCP_HISTOGRAM_EN_C 0x0738
#define PLCP_HISTOGRAM_EN_C_M 0x1
#define PLCP_HIST_TYPE_SEL_C 0x0738
#define PLCP_HIST_TYPE_SEL_C_M 0x2
#define STS_DIS_TRIG_BY_BRK_C 0x0738
#define STS_DIS_TRIG_BY_BRK_C_M 0x4
#define STS_DIS_TRIG_BY_FAIL_C 0x0738
#define STS_DIS_TRIG_BY_FAIL_C_M 0x8
#define STS_KEEPER_EN_C 0x0738
#define STS_KEEPER_EN_C_M 0x10
#define STS_KEEPER_READ_C 0x0738
#define STS_KEEPER_READ_C_M 0x20
#define STS_KEEPER_TRIG_COND_C 0x0738
#define STS_KEEPER_TRIG_COND_C_M 0xC0
#define STS_KEEPER_ADDR_C 0x0738
#define STS_KEEPER_ADDR_C_M 0xFF00
#define DATAON_TO_STS_FLAG_C 0x0738
#define DATAON_TO_STS_FLAG_C_M 0xF0000
#define STS_FLAG_GUARD_C 0x0738
#define STS_FLAG_GUARD_C_M 0xF00000
#define PHYSTS_INCR_DBG_EN_C 0x0738
#define PHYSTS_INCR_DBG_EN_C_M 0x1000000
#define STS_USER_SEL_C 0x0738
#define STS_USER_SEL_C_M 0x6000000
#define STS_SEG_SEL_C 0x0738
#define STS_SEG_SEL_C_M 0x8000000
#define STS_DBG_SEL_C 0x0738
#define STS_DBG_SEL_C_M 0x70000000
#define STS_TRIG_BY_FEQ_END_IN_NDP_C 0x0738
#define STS_TRIG_BY_FEQ_END_IN_NDP_C_M 0x80000000
#define PHY_STS_BITMAP_SEARCH_FAIL_C 0x073C
#define PHY_STS_BITMAP_SEARCH_FAIL_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_R2T_C 0x0740
#define PHY_STS_BITMAP_R2T_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_CCA_SPOOF_C 0x0744
#define PHY_STS_BITMAP_CCA_SPOOF_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_OFDM_BRK_C 0x0748
#define PHY_STS_BITMAP_OFDM_BRK_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_CCK_BRK_C 0x074C
#define PHY_STS_BITMAP_CCK_BRK_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_DL_MU_SPOOF_C 0x0750
#define PHY_STS_BITMAP_DL_MU_SPOOF_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_HE_MU_C 0x0754
#define PHY_STS_BITMAP_HE_MU_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_VHT_MU_C 0x0758
#define PHY_STS_BITMAP_VHT_MU_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_UL_TB_SPOOF_C 0x075C
#define PHY_STS_BITMAP_UL_TB_SPOOF_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_TRIGBASE_C 0x0760
#define PHY_STS_BITMAP_TRIGBASE_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_CCK_C 0x0764
#define PHY_STS_BITMAP_CCK_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_LEGACY_C 0x0768
#define PHY_STS_BITMAP_LEGACY_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_HT_C 0x076C
#define PHY_STS_BITMAP_HT_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_VHT_C 0x0770
#define PHY_STS_BITMAP_VHT_C_M 0xFFFFFFFF
#define PHY_STS_BITMAP_HE_C 0x0774
#define PHY_STS_BITMAP_HE_C_M 0xFFFFFFFF
#define PW_CUT_R2T_C 0x0778
#define PW_CUT_R2T_C_M 0xFF
#define PW_CUT_TXON_C 0x0778
#define PW_CUT_TXON_C_M 0xFF00
#define PW_CUT_WAIT_CCA_C 0x0778
#define PW_CUT_WAIT_CCA_C_M 0xFF0000
#define PW_CUT_RX_LEGACY_C 0x0778
#define PW_CUT_RX_LEGACY_C_M 0xFF000000
#define PW_CUT_RX_HTDATA_TIME_C 0x077C
#define PW_CUT_RX_HTDATA_TIME_C_M 0xFF
#define PW_CUT_RX_HTDATA_IORD_BCC_C 0x077C
#define PW_CUT_RX_HTDATA_IORD_BCC_C_M 0xFF00
#define PW_CUT_RX_HTDATA_IORD_LDPC_C 0x077C
#define PW_CUT_RX_HTDATA_IORD_LDPC_C_M 0xFF0000
#define PW_CUT_RX_HTDATA_CSI_RPT_C 0x077C
#define PW_CUT_RX_HTDATA_CSI_RPT_C_M 0xFF000000
#define SEL_V_COLUMN_VAL_EN_C 0x0800
#define SEL_V_COLUMN_VAL_EN_C_M 0x1
#define SEL_V_COLUMN_VAL_C 0x0800
#define SEL_V_COLUMN_VAL_C_M 0x3E
#define TXBF_SCAL_FCTR_C 0x0800
#define TXBF_SCAL_FCTR_C_M 0xFFC0
#define TXBF_SCAL_FCTR_EN_C 0x0800
#define TXBF_SCAL_FCTR_EN_C_M 0x10000
#define RST_BFER_EDGE_CNT_C 0x0800
#define RST_BFER_EDGE_CNT_C_M 0x20000
#define RST_BFEE_EDGE_CNT_C 0x0800
#define RST_BFEE_EDGE_CNT_C_M 0x40000
#define CSI_PARA_SEL_TO_RPT_C 0x0800
#define CSI_PARA_SEL_TO_RPT_C_M 0x7F80000
#define DIS_MU_GOUPING_TRIG_FB_CHK_C 0x0800
#define DIS_MU_GOUPING_TRIG_FB_CHK_C_M 0x8000000
#define GRPING_SEARCH_NUM_C 0x0804
#define GRPING_SEARCH_NUM_C_M 0xFF
#define GRP_USER_EN_C 0x0804
#define GRP_USER_EN_C_M 0x3FF00
#define DIS_MU_GRPING_C 0x0804
#define DIS_MU_GRPING_C_M 0x40000
#define DIS_BF_USER_CHK_C 0x0804
#define DIS_BF_USER_CHK_C_M 0x80000
#define SOUND_DONE_MUX_C 0x0804
#define SOUND_DONE_MUX_C_M 0x300000
#define ALWAYS_LAT_GRP_GMER_C 0x0804
#define ALWAYS_LAT_GRP_GMER_C_M 0x400000
#define BFEE_NR_NSTS_SEL_C 0x0808
#define BFEE_NR_NSTS_SEL_C_M 0x1
#define CAL_FEEDBACK_CSI_EN_C 0x0808
#define CAL_FEEDBACK_CSI_EN_C_M 0x2
#define RST_TXBF_COMPRESSOR_C 0x0808
#define RST_TXBF_COMPRESSOR_C_M 0x4
#define EN_SNR_RPT_COMP_C 0x0808
#define EN_SNR_RPT_COMP_C_M 0x8
#define TXBF_SNR_RPT_LIMT_EN_C 0x0808
#define TXBF_SNR_RPT_LIMT_EN_C_M 0x10
#define EN_DEF_SNR_C 0x0808
#define EN_DEF_SNR_C_M 0x20
#define DIS_BFEE_GCLK_C 0x0808
#define DIS_BFEE_GCLK_C_M 0x40
#define DIS_MAC_P_C 0x0808
#define DIS_MAC_P_C_M 0x80
#define DIS_CSI_CHKSUM_C 0x0808
#define DIS_CSI_CHKSUM_C_M 0x100
#define DIS_BFEE_CB_LMT_C 0x0808
#define DIS_BFEE_CB_LMT_C_M 0x200
#define BFMX_NDP_TRIG_SEL_C 0x0808
#define BFMX_NDP_TRIG_SEL_C_M 0x400
#define NDP_STANDBY_MUX_C 0x0808
#define NDP_STANDBY_MUX_C_M 0x1800
#define CSI_RPT_RATE_SEL_C 0x0808
#define CSI_RPT_RATE_SEL_C_M 0xE000
#define DIS_BFER_GCLK_C 0x0808
#define DIS_BFER_GCLK_C_M 0x10000
#define CSI_PARA_DBG_SEL_C 0x0808
#define CSI_PARA_DBG_SEL_C_M 0xFE0000
#define DIS_BF_CLK_C 0x0808
#define DIS_BF_CLK_C_M 0x1000000
#define DEF_DSNR_C 0x080C
#define DEF_DSNR_C_M 0xFFFF
#define BF_MIMO_BUS_DBG_EN_C 0x080C
#define BF_MIMO_BUS_DBG_EN_C_M 0x7F0000
#define BF_MIMO_BUS_DBG_SEL_C 0x080C
#define BF_MIMO_BUS_DBG_SEL_C_M 0x800000
#define DEF_SNR0_C 0x0810
#define DEF_SNR0_C_M 0xFF
#define DEF_SNR1_C 0x0810
#define DEF_SNR1_C_M 0xFF00
#define DEF_SNR2_C 0x0810
#define DEF_SNR2_C_M 0xFF0000
#define DEF_SNR3_C 0x0810
#define DEF_SNR3_C_M 0xFF000000
#define CSI_PARA_USER_EN_0_C 0x0814
#define CSI_PARA_USER_EN_0_C_M 0xFFFFFFFF
#define CSI_PARA_USER_EN_1_C 0x0818
#define CSI_PARA_USER_EN_1_C_M 0xFFFFFFFF
#define CSI_PARA_USER_EN_2_C 0x081C
#define CSI_PARA_USER_EN_2_C_M 0xFFFFFFFF
#define CSI_PARA_USER_EN_3_C 0x0820
#define CSI_PARA_USER_EN_3_C_M 0xFFFFFFFF
#define CSI_PARA_PARA_EN_C 0x0824
#define CSI_PARA_PARA_EN_C_M 0xFFFF
#define CSI_PARA_USE_EN_C 0x0824
#define CSI_PARA_USE_EN_C_M 0xF0000
#define CSI_PARA_READY_TIMEOUT_C 0x0824
#define CSI_PARA_READY_TIMEOUT_C_M 0x700000
#define CSI_PARA_END_SEL_C 0x0824
#define CSI_PARA_END_SEL_C_M 0x3800000
#define BFEE_CSI_DEF_MODE_C 0x0824
#define BFEE_CSI_DEF_MODE_C_M 0xC000000
#define CSI_PARA_IDX_0_C 0x0828
#define CSI_PARA_IDX_0_C_M 0xFFFFFFFF
#define CSI_PARA_IDX_1_C 0x082C
#define CSI_PARA_IDX_1_C_M 0xFFFF
#define CSI_PARA_C 0x082C
#define CSI_PARA_C_M 0xFFFF0000
#define BFEE_CSI_DEF_VAL_C 0x0830
#define BFEE_CSI_DEF_VAL_C_M 0xFFFFFFFF
#define DIS_BFEE_RST_CRTL_C 0x0834
#define DIS_BFEE_RST_CRTL_C_M 0xFF
#define CSI_RDRDY_TIME_OUT_SEL_C 0x0834
#define CSI_RDRDY_TIME_OUT_SEL_C_M 0xF00
#define INTF_R_CNT_RATE_C 0x0900
#define INTF_R_CNT_RATE_C_M 0xF
#define INTF_R_CNT_MCS_C 0x0900
#define INTF_R_CNT_MCS_C_M 0x7F0
#define INTF_R_CNT_VHT_MCS_C 0x0900
#define INTF_R_CNT_VHT_MCS_C_M 0x7800
#define INTF_R_CNT_HE_MCS_C 0x0900
#define INTF_R_CNT_HE_MCS_C_M 0x78000
#define INTF_R_CNT_VHT_NSS_C 0x0900
#define INTF_R_CNT_VHT_NSS_C_M 0x180000
#define INTF_R_CNT_HE_NSS_C 0x0900
#define INTF_R_CNT_HE_NSS_C_M 0x600000
#define INTF_R_MAC_HDR_TYPE_C 0x0900
#define INTF_R_MAC_HDR_TYPE_C_M 0x1F800000
#define INTF_R_PKT_TYPE_C 0x0904
#define INTF_R_PKT_TYPE_C_M 0xF
#define INTF_R_CRC32_TARGET_UID_C 0x0904
#define INTF_R_CRC32_TARGET_UID_C_M 0xFF0
#define INTF_R_CRC32_TARGET_UID_EN_C 0x0904
#define INTF_R_CRC32_TARGET_UID_EN_C_M 0x1000
#define INTF_R_RX_LBK_MODE_USER_EN_C 0x0904
#define INTF_R_RX_LBK_MODE_USER_EN_C_M 0x2000
#define INTF_R_RX_LBK_MODE_N_USER_C 0x0904
#define INTF_R_RX_LBK_MODE_N_USER_C_M 0x1C000
#define INTF_R_RX_LBK_MODE_AMPDU_EN_C 0x0904
#define INTF_R_RX_LBK_MODE_AMPDU_EN_C_M 0x20000
#define INTF_R_DIS_TB_BRK_PROTECT_C 0x0908
#define INTF_R_DIS_TB_BRK_PROTECT_C_M 0x1
#define INTF_R_DIS_TB_FIFO_CLR_C 0x0908
#define INTF_R_DIS_TB_FIFO_CLR_C_M 0x2
#define INTF_R_PMAC_TB_N_USER_CLR_TARGET_C 0x0908
#define INTF_R_PMAC_TB_N_USER_CLR_TARGET_C_M 0xF0
#define INTF_R_PMAC_TB_RSSI_C 0x0908
#define INTF_R_PMAC_TB_RSSI_C_M 0x7F00
#define INTF_R_TX_PMAC_EN_C 0x0980
#define INTF_R_TX_PMAC_EN_C_M 0x1
#define INTF_R_PMAC_TX_U_ID_PHASE_OPT_C 0x0980
#define INTF_R_PMAC_TX_U_ID_PHASE_OPT_C_M 0x30
#define INTF_R_PMAC_TXD_PHASE_OPT_C 0x0980
#define INTF_R_PMAC_TXD_PHASE_OPT_C_M 0xC0
#define INTF_R_PMAC_TX_INFO_DLY_CNT_C 0x0980
#define INTF_R_PMAC_TX_INFO_DLY_CNT_C_M 0x700
#define INTF_R_PMAC_TDRDY_EXT_CNT_C 0x0980
#define INTF_R_PMAC_TDRDY_EXT_CNT_C_M 0x7000
#define INTF_R_MAC_SEL_C 0x0980
#define INTF_R_MAC_SEL_C_M 0xFF0000
#define INTF_R_PMAC_TBTT_C 0x0980
#define INTF_R_PMAC_TBTT_C_M 0x1000000
#define INTF_R_PMAC_PMAC_MOD_C 0x0980
#define INTF_R_PMAC_PMAC_MOD_C_M 0x2000000
#define INTF_R_PMAC_GNT_BT_C 0x0980
#define INTF_R_PMAC_GNT_BT_C_M 0x4000000
#define INTF_R_PMAC_GNT_BT_TX_C 0x0980
#define INTF_R_PMAC_GNT_BT_TX_C_M 0x8000000
#define INTF_R_PMAC_GNT_WL_C 0x0980
#define INTF_R_PMAC_GNT_WL_C_M 0x10000000
#define INTF_R_PMAC_LTE_RX_C 0x0980
#define INTF_R_PMAC_LTE_RX_C_M 0x20000000
#define INTF_R_PMAC_RXPKT_OK_C 0x0980
#define INTF_R_PMAC_RXPKT_OK_C_M 0x40000000
#define INTF_R_PMAC_RXPKT_FAIL_C 0x0980
#define INTF_R_PMAC_RXPKT_FAIL_C_M 0x80000000
#define INTF_R_MAC_SEL_FTM_C 0x0984
#define INTF_R_MAC_SEL_FTM_C_M 0x3
#define INTF_R_PMAC_FTM_EN_C 0x0984
#define INTF_R_PMAC_FTM_EN_C_M 0x10
#define INTF_R_PMAC_FTM_RPT_TRIG_C 0x0984
#define INTF_R_PMAC_FTM_RPT_TRIG_C_M 0x100
#define INTF_R_MAC_SEL_RXD_C 0x0988
#define INTF_R_MAC_SEL_RXD_C_M 0x3F
#define INTF_R_RX_PMAC_EN_C 0x0988
#define INTF_R_RX_PMAC_EN_C_M 0x100
#define INTF_R_PMAC_RX_INVLD_PKT_C 0x0988
#define INTF_R_PMAC_RX_INVLD_PKT_C_M 0x200
#define INTF_R_PMAC_RX_ID_MATCH_C 0x0988
#define INTF_R_PMAC_RX_ID_MATCH_C_M 0x400
#define INTF_R_PMAC_DONT_RST_MAC_C 0x0988
#define INTF_R_PMAC_DONT_RST_MAC_C_M 0x800
#define INTF_R_PMAC_RX_TB_PPDU_STANDBY_C 0x0988
#define INTF_R_PMAC_RX_TB_PPDU_STANDBY_C_M 0x1000
#define INTF_R_PMAC_RX_TB_EN_C 0x0988
#define INTF_R_PMAC_RX_TB_EN_C_M 0x2000
#define INTF_R_MAC_RXD_PHASE_OPT_C 0x0988
#define INTF_R_MAC_RXD_PHASE_OPT_C_M 0xC000
#define INTF_R_TIME_RX_AIR_END_C 0x0988
#define INTF_R_TIME_RX_AIR_END_C_M 0x3F0000
#define INTF_R_TIME_RX_AIR_END_CCA_LAT_C 0x0988
#define INTF_R_TIME_RX_AIR_END_CCA_LAT_C_M 0x3F000000
#define INTF_R_PMAC_RX_TB_BUS_31_0_C 0x098C
#define INTF_R_PMAC_RX_TB_BUS_31_0_C_M 0xFFFFFFFF
#define INTF_R_PMAC_RX_TB_BUS_63_32_C 0x0990
#define INTF_R_PMAC_RX_TB_BUS_63_32_C_M 0xFFFFFFFF
#define INTF_R_MAC_SEL_BFMU_C 0x0994
#define INTF_R_MAC_SEL_BFMU_C_M 0xFF
#define INTF_R_PMAC_CSI_DATA_PAUSE_C 0x0994
#define INTF_R_PMAC_CSI_DATA_PAUSE_C_M 0x100
#define INTF_R_PMAC_NDP_STANDBY_C 0x0994
#define INTF_R_PMAC_NDP_STANDBY_C_M 0x200
#define INTF_R_PMAC_CSI_STANDBY_C 0x0994
#define INTF_R_PMAC_CSI_STANDBY_C_M 0x400
#define INTF_R_PMAC_SOUND_DONE_C 0x0994
#define INTF_R_PMAC_SOUND_DONE_C_M 0x800
#define INTF_R_PMAC_VHT_MU_USER_IDX_C 0x0994
#define INTF_R_PMAC_VHT_MU_USER_IDX_C_M 0x3000
#define INTF_R_PMAC_MIMO_PARA_EN_C 0x0994
#define INTF_R_PMAC_MIMO_PARA_EN_C_M 0x10000
#define INTF_R_PMAC_MIMO_FIELD_31_0_C 0x0998
#define INTF_R_PMAC_MIMO_FIELD_31_0_C_M 0xFFFFFFFF
#define INTF_R_PMAC_MIMO_FIELD_63_32_C 0x099C
#define INTF_R_PMAC_MIMO_FIELD_63_32_C_M 0xFFFFFFFF
#define INTF_R_PMAC_MIMO_FIELD_66_64_C 0x09A0
#define INTF_R_PMAC_MIMO_FIELD_66_64_C_M 0xFFFFFFFF
#define INTF_R_MAC_SEL_TXINFO_C 0x09A4
#define INTF_R_MAC_SEL_TXINFO_C_M 0xFFFFFFFF
#define INTF_R_TIME_RX_AIR_END_B_BW005_I_C 0x09A8
#define INTF_R_TIME_RX_AIR_END_B_BW005_I_C_M 0xFF
#define INTF_R_TIME_RX_AIR_END_B_BW010_I_C 0x09A8
#define INTF_R_TIME_RX_AIR_END_B_BW010_I_C_M 0xFF00
#define INTF_R_TIME_RX_AIR_END_B_BW020_I_C 0x09A8
#define INTF_R_TIME_RX_AIR_END_B_BW020_I_C_M 0xFF0000
#define INTF_R_TIME_RX_AIR_END_B_BW040_I_C 0x09A8
#define INTF_R_TIME_RX_AIR_END_B_BW040_I_C_M 0xFF000000
#define INTF_R_TIME_RX_AIR_END_B_BW080_I_C 0x09AC
#define INTF_R_TIME_RX_AIR_END_B_BW080_I_C_M 0xFF
#define INTF_R_TIME_RX_AIR_END_B_BW160_I_C 0x09AC
#define INTF_R_TIME_RX_AIR_END_B_BW160_I_C_M 0xFF00
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW005_I_C 0x09AC
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW005_I_C_M 0xFF0000
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW010_I_C 0x09AC
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW010_I_C_M 0xFF000000
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW020_I_C 0x09B0
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW020_I_C_M 0xFF
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW040_I_C 0x09B0
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW040_I_C_M 0xFF00
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW080_I_C 0x09B0
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW080_I_C_M 0xFF0000
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW160_I_C 0x09B0
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW160_I_C_M 0xFF000000
#define INTF_R_TIME_RX_AIR_END_BW005_I_C 0x09B4
#define INTF_R_TIME_RX_AIR_END_BW005_I_C_M 0xFF
#define INTF_R_TIME_RX_AIR_END_BW010_I_C 0x09B4
#define INTF_R_TIME_RX_AIR_END_BW010_I_C_M 0xFF00
#define INTF_R_TIME_RX_AIR_END_BW020_I_C 0x09B4
#define INTF_R_TIME_RX_AIR_END_BW020_I_C_M 0xFF0000
#define INTF_R_TIME_RX_AIR_END_BW040_I_C 0x09B4
#define INTF_R_TIME_RX_AIR_END_BW040_I_C_M 0xFF000000
#define INTF_R_TIME_RX_AIR_END_BW080_I_C 0x09B8
#define INTF_R_TIME_RX_AIR_END_BW080_I_C_M 0xFF
#define INTF_R_TIME_RX_AIR_END_BW160_I_C 0x09B8
#define INTF_R_TIME_RX_AIR_END_BW160_I_C_M 0xFF00
#define INTF_R_EN_CLR_CCA_BKUP_BY_DROP_I_C 0x09B8
#define INTF_R_EN_CLR_CCA_BKUP_BY_DROP_I_C_M 0x10000
#define INTF_R_EN_CCA_OPT_I_C 0x09B8
#define INTF_R_EN_CCA_OPT_I_C_M 0x20000
#define INTF_R_EN_RECCA_I_C 0x09B8
#define INTF_R_EN_RECCA_I_C_M 0x40000
#define INTF_R_PMAC_TRIG_TB_C 0x09BC
#define INTF_R_PMAC_TRIG_TB_C_M 0x1
#define INTF_R_PMAC_TB_TRIG_MODE_C 0x09BC
#define INTF_R_PMAC_TB_TRIG_MODE_C_M 0x6
#define INTF_R_MAC_INFO_RPT_SEL_C 0x09BC
#define INTF_R_MAC_INFO_RPT_SEL_C_M 0x10
#define INTF_R_TX_EN_C 0x09C0
#define INTF_R_TX_EN_C_M 0x1
#define INTF_R_TX_CONTINUOUS_EN_C 0x09C4
#define INTF_R_TX_CONTINUOUS_EN_C_M 0x1
#define INTF_R_TX_ACK_EN_C 0x09C4
#define INTF_R_TX_ACK_EN_C_M 0x2
#define INTF_R_TX_N_PACKET_EN_C 0x09C4
#define INTF_R_TX_N_PACKET_EN_C_M 0x10
#define INTF_R_TX_N_PACKET_PERIOD_50NS_C 0x09C4
#define INTF_R_TX_N_PACKET_PERIOD_50NS_C_M 0xFFFFFF00
#define INTF_R_TX_N_PACKET_C 0x09C8
#define INTF_R_TX_N_PACKET_C_M 0xFFFFFFFF
#define INTF_R_TAR_TXINFO_TXTP_EN_C 0x09CC
#define INTF_R_TAR_TXINFO_TXTP_EN_C_M 0x1
#define INTF_R_TAR_TXINFO_TXTP_C 0x09CC
#define INTF_R_TAR_TXINFO_TXTP_C_M 0x3F0
#define INTF_R_TX_20M_MODE_EN_C 0x09D0
#define INTF_R_TX_20M_MODE_EN_C_M 0x1
#define INTF_R_TXBF_DIS_C 0x09D0
#define INTF_R_TXBF_DIS_C_M 0x10
#define NOT_SUPPORT_STBC_NSS_LMT_C 0x0A00
#define NOT_SUPPORT_STBC_NSS_LMT_C_M 0xF
#define NOT_SUPPORT_DCM_NSS_LMT_C 0x0A00
#define NOT_SUPPORT_DCM_NSS_LMT_C_M 0xF0
#define NOT_SUPPORT_NSS_LMT_C 0x0A00
#define NOT_SUPPORT_NSS_LMT_C_M 0xF00
#define NOT_SUPPORT_MU_BCC_NSS_LMT_C 0x0A00
#define NOT_SUPPORT_MU_BCC_NSS_LMT_C_M 0xF000
#define EN_LDPC_RX_IN_C 0x0A00
#define EN_LDPC_RX_IN_C_M 0x10000
#define HEMUR_MUMIMO_EN_C 0x0A00
#define HEMUR_MUMIMO_EN_C_M 0x20000
#define BYPASS_HE_ERR_BCC_UP242_C 0x0A00
#define BYPASS_HE_ERR_BCC_UP242_C_M 0x40000
#define BYPASS_HE_ERR_BCC_MCS_C 0x0A00
#define BYPASS_HE_ERR_BCC_MCS_C_M 0x80000
#define BYPASS_HE_ERR_MCS_C 0x0A00
#define BYPASS_HE_ERR_MCS_C_M 0x100000
#define BYPASS_HE_ERR_NSTS_TOT_C 0x0A00
#define BYPASS_HE_ERR_NSTS_TOT_C_M 0x200000
#define BYPASS_HE_ERR_SPATIAL_CONFIG_C 0x0A00
#define BYPASS_HE_ERR_SPATIAL_CONFIG_C_M 0x400000
#define BYPASS_HE_ERR_STBC_MIMO_C 0x0A00
#define BYPASS_HE_ERR_STBC_MIMO_C_M 0x800000
#define BYPASS_HE_ERR_DCM_MIMO_C 0x0A00
#define BYPASS_HE_ERR_DCM_MIMO_C_M 0x1000000
#define BYPASS_HE_ERR_STBC_DCM_C 0x0A00
#define BYPASS_HE_ERR_STBC_DCM_C_M 0x2000000
#define BYPASS_HE_NOT_SUPPORT_STBC_NSS_C 0x0A00
#define BYPASS_HE_NOT_SUPPORT_STBC_NSS_C_M 0x4000000
#define BYPASS_HE_NOT_SUPPORT_DCM_NSS_C 0x0A00
#define BYPASS_HE_NOT_SUPPORT_DCM_NSS_C_M 0x8000000
#define BYPASS_HE_NOT_SUPPORT_NSS_C 0x0A00
#define BYPASS_HE_NOT_SUPPORT_NSS_C_M 0x10000000
#define BYPASS_HE_NOT_SUPPORT_MU_BCC_NSS_C 0x0A00
#define BYPASS_HE_NOT_SUPPORT_MU_BCC_NSS_C_M 0x20000000
#define BYPASS_HE_NOT_SUPPORT_MU_MIMO_C 0x0A00
#define BYPASS_HE_NOT_SUPPORT_MU_MIMO_C_M 0x40000000
#define BYPASS_SMO_NDP_SEL_C 0x0A04
#define BYPASS_SMO_NDP_SEL_C_M 0x1
#define FORCE_LS_NDP_C 0x0A04
#define FORCE_LS_NDP_C_M 0x2
#define CQI_DD_OPT_C 0x0A04
#define CQI_DD_OPT_C_M 0x3FC
#define EN_PILOT_TRACKING_ONLY_C 0x0A04
#define EN_PILOT_TRACKING_ONLY_C_M 0x800
#define HE_SIGB_STF_DELAY_SPACING_C 0x0A04
#define HE_SIGB_STF_DELAY_SPACING_C_M 0xFF000
#define TB_LTF_TRACK_CNT_START_VAL_C 0x0A04
#define TB_LTF_TRACK_CNT_START_VAL_C_M 0x700000
#define PILOT_DC_ALIGN_SEL_C 0x0A04
#define PILOT_DC_ALIGN_SEL_C_M 0x800000
#define RESERVED_C 0x0A04
#define RESERVED_C_M 0xFF000000
#define STS_NDP_KEEP_COND_IN_IN_C 0x0A08
#define STS_NDP_KEEP_COND_IN_IN_C_M 0x1
#define FTM_T_OFF_PKT_CNT_TO_BRK_C 0x0A08
#define FTM_T_OFF_PKT_CNT_TO_BRK_C_M 0x3800
#define CCX_EN_C 0x0C00
#define CCX_EN_C_M 0x1
#define CCX_TRIG_OPT_C 0x0C00
#define CCX_TRIG_OPT_C_M 0x2
#define MEASUREMENT_TRIG_C 0x0C00
#define MEASUREMENT_TRIG_C_M 0x4
#define CCX_EDCCA_OPT_C 0x0C00
#define CCX_EDCCA_OPT_C_M 0x70
#define CCX_TXON_OPT_C 0x0C00
#define CCX_TXON_OPT_C_M 0x80
#define CLM_COUNTER_UNIT_C 0x0C00
#define CLM_COUNTER_UNIT_C_M 0xC00
#define CLM_EN_C 0x0C00
#define CLM_EN_C_M 0x1000
#define CLM_CCA_OPT_C 0x0C00
#define CLM_CCA_OPT_C_M 0xE000
#define CLM_PERIOD_C 0x0C00
#define CLM_PERIOD_C_M 0xFFFF0000
#define CLM_EDCCA_PERIOD_C 0x0C04
#define CLM_EDCCA_PERIOD_C_M 0xFFFF
#define CLM_EDCCA_COUNTER_UNIT_C 0x0C04
#define CLM_EDCCA_COUNTER_UNIT_C_M 0x30000
#define CLM_EDCCA_EN_C 0x0C04
#define CLM_EDCCA_EN_C_M 0x40000
#define CLM_FROM_DBG_SEL_C 0x0C04
#define CLM_FROM_DBG_SEL_C_M 0x3F00000
#define NHM_PERIOD_C 0x0C08
#define NHM_PERIOD_C_M 0xFFFF
#define NHM_COUNTER_UNIT_C 0x0C08
#define NHM_COUNTER_UNIT_C_M 0x30000
#define NHM_EN_C 0x0C08
#define NHM_EN_C_M 0x40000
#define NHM_IGNORE_CCA_C 0x0C08
#define NHM_IGNORE_CCA_C_M 0x80000
#define NHM_TH0_C 0x0C08
#define NHM_TH0_C_M 0xFF000000
#define NHM_TH1_C 0x0C0C
#define NHM_TH1_C_M 0xFF
#define NHM_TH2_C 0x0C0C
#define NHM_TH2_C_M 0xFF00
#define NHM_TH3_C 0x0C0C
#define NHM_TH3_C_M 0xFF0000
#define NHM_TH4_C 0x0C0C
#define NHM_TH4_C_M 0xFF000000
#define NHM_TH5_C 0x0C10
#define NHM_TH5_C_M 0xFF
#define NHM_TH6_C 0x0C10
#define NHM_TH6_C_M 0xFF00
#define NHM_TH7_C 0x0C10
#define NHM_TH7_C_M 0xFF0000
#define NHM_TH8_C 0x0C10
#define NHM_TH8_C_M 0xFF000000
#define NHM_TH9_C 0x0C14
#define NHM_TH9_C_M 0xFF
#define NHM_TH10_C 0x0C14
#define NHM_TH10_C_M 0xFF00
#define NHM_PWDB_METHOD_SEL_C 0x0C14
#define NHM_PWDB_METHOD_SEL_C_M 0x30000
#define NHM_PWDB_PATH_SEL_C 0x0C14
#define NHM_PWDB_PATH_SEL_C_M 0xF00000
#define AVG_IDLE_PW_IDX_C 0x0C14
#define AVG_IDLE_PW_IDX_C_M 0x7000000
#define T2F_BRK_CNT_END_C 0x0C14
#define T2F_BRK_CNT_END_C_M 0x38000000
#define T2F_IDLE_CNT_BRK_SWITCH_C 0x0C14
#define T2F_IDLE_CNT_BRK_SWITCH_C_M 0x40000000
#define T2F_HE_CDD_SKIP_EN_C 0x0C14
#define T2F_HE_CDD_SKIP_EN_C_M 0x80000000
#define FAHM_EN_C 0x0C18
#define FAHM_EN_C_M 0x1
#define FAHM_EN_OFDM_C 0x0C18
#define FAHM_EN_OFDM_C_M 0x2
#define FAHM_EN_CCK_C 0x0C18
#define FAHM_EN_CCK_C_M 0x4
#define FAHM_NUM_CANDIDATE_C 0x0C18
#define FAHM_NUM_CANDIDATE_C_M 0x38
#define FAHM_DEN_CANDIDATE_C 0x0C18
#define FAHM_DEN_CANDIDATE_C_M 0x1C0
#define FAHM_EN_TH_LMT_C 0x0C18
#define FAHM_EN_TH_LMT_C_M 0x200
#define FAHM_COUNTER_UNIT_C 0x0C18
#define FAHM_COUNTER_UNIT_C_M 0xC00
#define FAHM_TH_UP_LMT_C 0x0C18
#define FAHM_TH_UP_LMT_C_M 0xF000
#define FAHM_PERIOD_C 0x0C18
#define FAHM_PERIOD_C_M 0xFFFF0000
#define FAHM_CRC32_ERR_LEGACY_C 0x0C1C
#define FAHM_CRC32_ERR_LEGACY_C_M 0x1
#define FAHM_AMPDU_CRC32_OPT_C 0x0C1C
#define FAHM_AMPDU_CRC32_OPT_C_M 0x2
#define RX_TD_CKEN_OFDM_C 0x0C1C
#define RX_TD_CKEN_OFDM_C_M 0x4
#define FAHM_PWDB_SEL_C 0x0C1C
#define FAHM_PWDB_SEL_C_M 0x70
#define FAHM_TH0_C 0x0C1C
#define FAHM_TH0_C_M 0xFF0000
#define FAHM_TH1_C 0x0C1C
#define FAHM_TH1_C_M 0xFF000000
#define FAHM_TH2_C 0x0C20
#define FAHM_TH2_C_M 0xFF
#define FAHM_TH3_C 0x0C20
#define FAHM_TH3_C_M 0xFF00
#define FAHM_TH4_C 0x0C20
#define FAHM_TH4_C_M 0xFF0000
#define FAHM_TH5_C 0x0C20
#define FAHM_TH5_C_M 0xFF000000
#define FAHM_TH6_C 0x0C24
#define FAHM_TH6_C_M 0xFF
#define FAHM_TH7_C 0x0C24
#define FAHM_TH7_C_M 0xFF00
#define FAHM_TH8_C 0x0C24
#define FAHM_TH8_C_M 0xFF0000
#define FAHM_TH9_C 0x0C24
#define FAHM_TH9_C_M 0xFF000000
#define FAHM_TH10_C 0x0C28
#define FAHM_TH10_C_M 0xFF
#define FAHM_DIS_COUNT_EACH_MPDU_C 0x0C28
#define FAHM_DIS_COUNT_EACH_MPDU_C_M 0x100
#define IFS_COLLECT_EN_C 0x0C28
#define IFS_COLLECT_EN_C_M 0x1000
#define IFS_COUNTER_CLR_C 0x0C28
#define IFS_COUNTER_CLR_C_M 0x2000
#define IFS_COUNTER_UNIT_C 0x0C28
#define IFS_COUNTER_UNIT_C_M 0xC000
#define IFS_COLLECT_TOTAL_TIME_C 0x0C28
#define IFS_COLLECT_TOTAL_TIME_C_M 0xFFFF0000
#define IFS_T1_TH_LOW_C 0x0C2C
#define IFS_T1_TH_LOW_C_M 0x7FFF
#define IFS_T1_EN_C 0x0C2C
#define IFS_T1_EN_C_M 0x8000
#define IFS_T1_TH_HIGH_C 0x0C2C
#define IFS_T1_TH_HIGH_C_M 0xFFFF0000
#define IFS_T2_TH_LOW_C 0x0C30
#define IFS_T2_TH_LOW_C_M 0x7FFF
#define IFS_T2_EN_C 0x0C30
#define IFS_T2_EN_C_M 0x8000
#define IFS_T2_TH_HIGH_C 0x0C30
#define IFS_T2_TH_HIGH_C_M 0xFFFF0000
#define IFS_T3_TH_LOW_C 0x0C34
#define IFS_T3_TH_LOW_C_M 0x7FFF
#define IFS_T3_EN_C 0x0C34
#define IFS_T3_EN_C_M 0x8000
#define IFS_T3_TH_HIGH_C 0x0C34
#define IFS_T3_TH_HIGH_C_M 0xFFFF0000
#define IFS_T4_TH_LOW_C 0x0C38
#define IFS_T4_TH_LOW_C_M 0x7FFF
#define IFS_T4_EN_C 0x0C38
#define IFS_T4_EN_C_M 0x8000
#define IFS_T4_TH_HIGH_C 0x0C38
#define IFS_T4_TH_HIGH_C_M 0xFFFF0000
#define EN_AGC_C 0x0C3C
#define EN_AGC_C_M 0x1
#define EN_DFIR_TMP_C 0x0C3C
#define EN_DFIR_TMP_C_M 0x2
#define EN_ACI_DET_TMP_C 0x0C3C
#define EN_ACI_DET_TMP_C_M 0x4
#define EN_DCCL_TMP_C 0x0C3C
#define EN_DCCL_TMP_C_M 0x8
#define EN_NBIFLT_TMP_C 0x0C3C
#define EN_NBIFLT_TMP_C_M 0x10
#define EN_SUBFLT_TMP_C 0x0C3C
#define EN_SUBFLT_TMP_C_M 0x20
#define OPT_PW_C 0x0C3C
#define OPT_PW_C_M 0x40
#define DC_EN_C 0x0C3C
#define DC_EN_C_M 0x80
#define SMF_EN_C 0x0C3C
#define SMF_EN_C_M 0x100
#define DIS_PD_FLAG_C 0x0C3C
#define DIS_PD_FLAG_C_M 0x200
#define DBG_OPT_SYNC_C 0x0C3C
#define DBG_OPT_SYNC_C_M 0x400
#define DIS_GATE_SYNC_PATH_BY_TXON_C 0x0C3C
#define DIS_GATE_SYNC_PATH_BY_TXON_C_M 0x800
#define DIS_RST_SYNC_PATH_BY_TXON_C 0x0C3C
#define DIS_RST_SYNC_PATH_BY_TXON_C_M 0x1000
#define EN_2ND20_C 0x0C3C
#define EN_2ND20_C_M 0x2000
#define SYNC_RST_OPT_C 0x0C3C
#define SYNC_RST_OPT_C_M 0xC000
#define BYPASS_BW20_INDICATE_C 0x0C3C
#define BYPASS_BW20_INDICATE_C_M 0x10000
#define FORCE_RXSC_EN_C 0x0C3C
#define FORCE_RXSC_EN_C_M 0x20000
#define FORCE_RXSC_C 0x0C3C
#define FORCE_RXSC_C_M 0x40000
#define FINE_TUNE_PROCESS_DELAY_EXT_C 0x0C3C
#define FINE_TUNE_PROCESS_DELAY_EXT_C_M 0x80000
#define FINE_TUNE_STOP_LMT_EXT_C 0x0C3C
#define FINE_TUNE_STOP_LMT_EXT_C_M 0x100000
#define DIS_RST_CR_OFST_BY_RFGC_C 0x0C3C
#define DIS_RST_CR_OFST_BY_RFGC_C_M 0x200000
#define LONG_CFO_EST_EN_C 0x0C3C
#define LONG_CFO_EST_EN_C_M 0x400000
#define LONG_CFO_EST_SEL_C 0x0C3C
#define LONG_CFO_EST_SEL_C_M 0x800000
#define RST_AGC_DCNF_BY_TRIG_C 0x0C3C
#define RST_AGC_DCNF_BY_TRIG_C_M 0x1000000
#define DIS_RST_CNT_BY_AGCSTS_CHANGE_C 0x0C3C
#define DIS_RST_CNT_BY_AGCSTS_CHANGE_C_M 0x2000000
#define SYNC_ALWAYS_ON_C 0x0C3C
#define SYNC_ALWAYS_ON_C_M 0x4000000
#define SBFLT5M_EN_TMP_C 0x0C3C
#define SBFLT5M_EN_TMP_C_M 0x8000000
#define SBDFT_FINE_CFO_EN_C 0x0C3C
#define SBDFT_FINE_CFO_EN_C_M 0x10000000
#define CFO_ANT_SUM_RTL_C 0x0C3C
#define CFO_ANT_SUM_RTL_C_M 0x20000000
#define MANUAL_COARSE_CFO_EN_C 0x0C3C
#define MANUAL_COARSE_CFO_EN_C_M 0x40000000
#define MANUAL_FINE_CFO_EN_C 0x0C3C
#define MANUAL_FINE_CFO_EN_C_M 0x80000000
#define CDD0_COUNT_LMT_RTL_C 0x0C40
#define CDD0_COUNT_LMT_RTL_C_M 0x1F
#define CDD0_JUMP_SUB_TUNE_RTL_C 0x0C40
#define CDD0_JUMP_SUB_TUNE_RTL_C_M 0x3E0
#define CDD0_DELAY_SPREAD_SIZE_RTL_C 0x0C40
#define CDD0_DELAY_SPREAD_SIZE_RTL_C_M 0x3C00
#define SYNC_DATA_DELAY_DIFF_C 0x0C40
#define SYNC_DATA_DELAY_DIFF_C_M 0x1FC000
#define MANUAL_COARSE_CFO_C 0x0C40
#define MANUAL_COARSE_CFO_C_M 0xFFE00000
#define L1_L2_PROCESS_DELAY_CFO_C 0x0C44
#define L1_L2_PROCESS_DELAY_CFO_C_M 0xF
#define SYNC_DATA_DELAY_DIFF_CFO_C 0x0C44
#define SYNC_DATA_DELAY_DIFF_CFO_C_M 0x7F0
#define FIX_SYNC_DGAIN_EN_C 0x0C44
#define FIX_SYNC_DGAIN_EN_C_M 0x800
#define OFST_SYNC_DAGC_C 0x0C44
#define OFST_SYNC_DAGC_C_M 0xF000
#define SYNC_DAGC_FREE_RUN_C 0x0C44
#define SYNC_DAGC_FREE_RUN_C_M 0x10000
#define FIX_SYNC_DGAIN_PWDB_C 0x0C44
#define FIX_SYNC_DGAIN_PWDB_C_M 0xFE0000
#define FIX_SYNC_DGAIN_C 0x0C44
#define FIX_SYNC_DGAIN_C_M 0xFF000000
#define MANUAL_FINE_CFO_C 0x0C48
#define MANUAL_FINE_CFO_C_M 0x3FFF
#define L1_CFO_CMP_EN_RTL_C 0x0C48
#define L1_CFO_CMP_EN_RTL_C_M 0x4000
#define DIS_CCA_MASK_C 0x0C48
#define DIS_CCA_MASK_C_M 0x8000
#define FOLLOW_MAC_NDP_C 0x0C48
#define FOLLOW_MAC_NDP_C_M 0x10000
#define EN_LDPC_RX_C 0x0C48
#define EN_LDPC_RX_C_M 0x20000
#define VHTLEN_USE_LSIG_RX_BCC_C 0x0C48
#define VHTLEN_USE_LSIG_RX_BCC_C_M 0x40000
#define VHTLEN_USE_LSIG_RX_LDPC_C 0x0C48
#define VHTLEN_USE_LSIG_RX_LDPC_C_M 0x80000
#define RFC_TX_RATE_BIAS_AT_DL_OFDMA_C 0x0C48
#define RFC_TX_RATE_BIAS_AT_DL_OFDMA_C_M 0x300000
#define EN_SYNCDAGC_RFGCUP_C 0x0C48
#define EN_SYNCDAGC_RFGCUP_C_M 0x400000
#define RST_AGC_RPT_C 0x0C48
#define RST_AGC_RPT_C_M 0x800000
#define EN_AGC_RPT_C 0x0C48
#define EN_AGC_RPT_C_M 0x1000000
#define EN_FREERUN_C 0x0C48
#define EN_FREERUN_C_M 0x2000000
#define OPT_FREERUN_C 0x0C48
#define OPT_FREERUN_C_M 0x4000000
#define SIZE_PWCAL_FREERUN_C 0x0C48
#define SIZE_PWCAL_FREERUN_C_M 0x18000000
#define HE_TB_RTL_C 0x0C48
#define HE_TB_RTL_C_M 0x20000000
#define SNDCCA_GNTBT_EN_C 0x0C48
#define SNDCCA_GNTBT_EN_C_M 0x40000000
#define DIS_RST_BY_OFDM_ENABLE_C 0x0C48
#define DIS_RST_BY_OFDM_ENABLE_C_M 0x80000000
#define NCLKWAIT_LGY_C 0x0C4C
#define NCLKWAIT_LGY_C_M 0x3F
#define NCLKWAIT_HE_C 0x0C4C
#define NCLKWAIT_HE_C_M 0xFC0
#define NCLKWAIT_ANTSW_C 0x0C4C
#define NCLKWAIT_ANTSW_C_M 0x3F000
#define NCLKWAIT_CCK_C 0x0C4C
#define NCLKWAIT_CCK_C_M 0xFC0000
#define NCLKWAIT_PRE_C 0x0C4C
#define NCLKWAIT_PRE_C_M 0x3F000000
#define NCLKWAIT_MANUAL_EN_C 0x0C4C
#define NCLKWAIT_MANUAL_EN_C_M 0x40000000
#define NCLKPW_MANUAL_EN_C 0x0C4C
#define NCLKPW_MANUAL_EN_C_M 0x80000000
#define NCLKWAIT_TIAEXTRA_C 0x0C50
#define NCLKWAIT_TIAEXTRA_C_M 0x3F
#define NCLKPW_MANUAL_PRE0_C 0x0C50
#define NCLKPW_MANUAL_PRE0_C_M 0xC0
#define NCLKPW_MANUAL_PRE1_C 0x0C50
#define NCLKPW_MANUAL_PRE1_C_M 0x300
#define MASK_POP_START_C 0x0C50
#define MASK_POP_START_C_M 0x1C00
#define MASK_POP_STOP_C 0x0C50
#define MASK_POP_STOP_C_M 0xFE000
#define DLY_FINETUNE_STF_C 0x0C50
#define DLY_FINETUNE_STF_C_M 0xFF00000
#define CG_RSSI_C 0x0C54
#define CG_RSSI_C_M 0x1
#define CG_SYNC_COMM_C 0x0C54
#define CG_SYNC_COMM_C_M 0x2
#define CG_BY_B_CCA_0_C 0x0C54
#define CG_BY_B_CCA_0_C_M 0x4
#define CG_BY_B_CCA_1_C 0x0C54
#define CG_BY_B_CCA_1_C_M 0x8
#define DIS_RST_SYNC_FSM_BY_B_PD_HIT_C 0x0C54
#define DIS_RST_SYNC_FSM_BY_B_PD_HIT_C_M 0x10
#define EN_PPDU_FIX_GAIN_C 0x0C54
#define EN_PPDU_FIX_GAIN_C_M 0x20
#define EN_CCA_PW_TH_C 0x0C54
#define EN_CCA_PW_TH_C_M 0x40
#define DIS_1RCCA_CCK_C 0x0C54
#define DIS_1RCCA_CCK_C_M 0x80
#define PATH_EN_NOT_FIND_80P80_C 0x0C54
#define PATH_EN_NOT_FIND_80P80_C_M 0xF00
#define DIS_CHANGE_PATH_80P80_C 0x0C54
#define DIS_CHANGE_PATH_80P80_C_M 0x1000
#define DIS_BRK_NOT_FIND_80P80_C 0x0C54
#define DIS_BRK_NOT_FIND_80P80_C_M 0x2000
#define BW80P80_C 0x0C54
#define BW80P80_C_M 0x1C000
#define HALT_WAIT_80P80_BY_RFGC_SEG0_C 0x0C54
#define HALT_WAIT_80P80_BY_RFGC_SEG0_C_M 0x20000
#define HALT_WAIT_80P80_BY_RFGC_SEG1_C 0x0C54
#define HALT_WAIT_80P80_BY_RFGC_SEG1_C_M 0x40000
#define DIS_1RCCA_OFDM_C 0x0C54
#define DIS_1RCCA_OFDM_C_M 0x80000
#define NSS_DEFINE_OPT_C 0x0C54
#define NSS_DEFINE_OPT_C_M 0x100000
#define BRK_RXTD_OPT_C 0x0C54
#define BRK_RXTD_OPT_C_M 0xFE00000
#define EN_SBDFT_C 0x0C54
#define EN_SBDFT_C_M 0x10000000
#define DIS_RST_BY_DIS_PD_FLAG_C 0x0C54
#define DIS_RST_BY_DIS_PD_FLAG_C_M 0x20000000
#define EN_RST_CHANGE_CORNER_C 0x0C54
#define EN_RST_CHANGE_CORNER_C_M 0x40000000
#define EN_POP_WHEN_TB_C 0x0C54
#define EN_POP_WHEN_TB_C_M 0x80000000
#define MASK_LSB_RXDFIR_C 0x0C58
#define MASK_LSB_RXDFIR_C_M 0xF
#define MASK_LSB_SYNC_PATH_C 0x0C58
#define MASK_LSB_SYNC_PATH_C_M 0xF0
#define TB_STS_ON_C 0x0C58
#define TB_STS_ON_C_M 0xFF00
#define SEL_RPTREG_C 0x0C58
#define SEL_RPTREG_C_M 0x30000
#define PW_HIT_OPT_C 0x0C58
#define PW_HIT_OPT_C_M 0x40000
#define PREAGC_RPT_OPT_C 0x0C58
#define PREAGC_RPT_OPT_C_M 0x80000
#define PATH_EN_FIX_C 0x0C58
#define PATH_EN_FIX_C_M 0x100000
#define TB_SYNC_PATH_END_OPT_C 0x0C58
#define TB_SYNC_PATH_END_OPT_C_M 0x200000
#define EN_SYNC_WHEN_TB_FIX_MODE_C 0x0C58
#define EN_SYNC_WHEN_TB_FIX_MODE_C_M 0x400000
#define TB_BW_COMB_OPT_C 0x0C58
#define TB_BW_COMB_OPT_C_M 0x800000
#define ELNA_INIT_IDX_C 0x0C58
#define ELNA_INIT_IDX_C_M 0x1000000
#define DIS_CCA_SPOOF_C 0x0C58
#define DIS_CCA_SPOOF_C_M 0x2000000
#define FORCE_CCA_SPOOF_C 0x0C58
#define FORCE_CCA_SPOOF_C_M 0x4000000
#define OPT_TB_KEEP_C 0x0C58
#define OPT_TB_KEEP_C_M 0x8000000
#define ON_SYNC_PATH_COMM_C 0x0C58
#define ON_SYNC_PATH_COMM_C_M 0x10000000
#define CONTI_CCA_PW_TH_C 0x0C58
#define CONTI_CCA_PW_TH_C_M 0x20000000
#define OPT_LMT_CCA_PW_TH_C 0x0C58
#define OPT_LMT_CCA_PW_TH_C_M 0xC0000000
#define LMT_PPDU_FIX_GAIN_C 0x0C5C
#define LMT_PPDU_FIX_GAIN_C_M 0xFF
#define LMT_CCA_PW_TH_C 0x0C5C
#define LMT_CCA_PW_TH_C_M 0xFF00
#define AGC_BT_SEL_PATH0_C 0x0C5C
#define AGC_BT_SEL_PATH0_C_M 0x30000
#define AGC_BT_SEL_PATH1_C 0x0C5C
#define AGC_BT_SEL_PATH1_C_M 0xC0000
#define AGC_BT_SEL_PATH2_C 0x0C5C
#define AGC_BT_SEL_PATH2_C_M 0x300000
#define AGC_BT_SEL_PATH3_C 0x0C5C
#define AGC_BT_SEL_PATH3_C_M 0xC00000
#define EN_TB_CCA_LMT_C 0x0C5C
#define EN_TB_CCA_LMT_C_M 0x1000000
#define TB_CCA_LMT_C 0x0C5C
#define TB_CCA_LMT_C_M 0xFE000000
#define IQK_DPK_CLK_ON_C 0x0C60
#define IQK_DPK_CLK_ON_C_M 0x1
#define EN_IOQ_IQK_DPK_C 0x0C60
#define EN_IOQ_IQK_DPK_C_M 0x2
#define IQK_OFDM_CCA_FORCE_ON_C 0x0C60
#define IQK_OFDM_CCA_FORCE_ON_C_M 0x4
#define IQK_CCK_CCA_FORCE_ON_C 0x0C60
#define IQK_CCK_CCA_FORCE_ON_C_M 0x8
#define RST_COMM_3_0__C 0x0C60
#define RST_COMM_3_0__C_M 0xF0
#define RST_COMM_SYNC_3_0__C 0x0C60
#define RST_COMM_SYNC_3_0__C_M 0xF00
#define RST_SYNC_3_0__C 0x0C60
#define RST_SYNC_3_0__C_M 0xF000
#define RST_COMM_5_4__C 0x0C60
#define RST_COMM_5_4__C_M 0x30000
#define RST_COMM_SYNC_5_4__C 0x0C60
#define RST_COMM_SYNC_5_4__C_M 0xC0000
#define RST_SYNC_5_4__C 0x0C60
#define RST_SYNC_5_4__C_M 0x300000
#define DLY_DET_OUT_C 0x0C60
#define DLY_DET_OUT_C_M 0xC00000
#define DLY_NORMAL_DET_OUT_C 0x0C60
#define DLY_NORMAL_DET_OUT_C_M 0x3000000
#define SNIFFER_MODE_C 0x0C60
#define SNIFFER_MODE_C_M 0x3C000000
#define OPT_LMT_PPDU_FIX_GAIN_C 0x0C60
#define OPT_LMT_PPDU_FIX_GAIN_C_M 0xC0000000
#define RFC_TX_CCK_IND_DIS_SEL_C 0x0C64
#define RFC_TX_CCK_IND_DIS_SEL_C_M 0xF
#define OPT_EN_CCA_PW_TH_C 0x0C64
#define OPT_EN_CCA_PW_TH_C_M 0x30
#define EN_2ND20_BW_C 0x0C64
#define EN_2ND20_BW_C_M 0x40
#define CG_BY_OFDM_ENABLE_0_C 0x0C64
#define CG_BY_OFDM_ENABLE_0_C_M 0x80
#define CG_BY_OFDM_ENABLE_1_C 0x0C64
#define CG_BY_OFDM_ENABLE_1_C_M 0x100
#define DIS_SBDFT_C 0x0C64
#define DIS_SBDFT_C_M 0x200
#define FPGA_OPT_PRD_C 0x0C64
#define FPGA_OPT_PRD_C_M 0xC00
#define MUX_ST_POP_C 0x0C64
#define MUX_ST_POP_C_M 0xF000
#define MUX_ST_VLD_POP_C 0x0C64
#define MUX_ST_VLD_POP_C_M 0xF0000
#define EN_CFIR_MODEL_C 0x0C64
#define EN_CFIR_MODEL_C_M 0x100000
#define LOCK_NBIFLT_C 0x0C64
#define LOCK_NBIFLT_C_M 0x200000
#define MANUAL_EN_CCA_PW_TH_C 0x0C64
#define MANUAL_EN_CCA_PW_TH_C_M 0x400000
#define CCA_PW_TH_C 0x0C64
#define CCA_PW_TH_C_M 0x7F800000
#define CCA_PW_TH_PRIORITY_C 0x0C64
#define CCA_PW_TH_PRIORITY_C_M 0x80000000
#define MAX_CNT_POP_C 0x0C68
#define MAX_CNT_POP_C_M 0xFF
#define CCA_MASK_CNT_POP_C 0x0C68
#define CCA_MASK_CNT_POP_C_M 0xFF00
#define OPT_ANT_EN_RSSI_C 0x0C68
#define OPT_ANT_EN_RSSI_C_M 0x10000
#define EN_NCLKWAIT_BY_IDX_C 0x0C68
#define EN_NCLKWAIT_BY_IDX_C_M 0x20000
#define OPT_MASK_POP_C 0x0C68
#define OPT_MASK_POP_C_M 0x40000
#define SYNCDLY_OFST_C 0x0C68
#define SYNCDLY_OFST_C_M 0xF80000
#define EN_SYNCDLY_OFST_PRIM_C 0x0C68
#define EN_SYNCDLY_OFST_PRIM_C_M 0x1000000
#define EN_SYNCDLY_OFST_DFE_C 0x0C68
#define EN_SYNCDLY_OFST_DFE_C_M 0x2000000
#define EN_SYNCDLY_OFST_DCCL_C 0x0C68
#define EN_SYNCDLY_OFST_DCCL_C_M 0x4000000
#define EN_SYNCDLY_OFST_SYNC_C 0x0C68
#define EN_SYNCDLY_OFST_SYNC_C_M 0x8000000
#define SBD_FAIL_OPT_C 0x0C68
#define SBD_FAIL_OPT_C_M 0x10000000
#define EN_POP_CFOE_LATE_C 0x0C68
#define EN_POP_CFOE_LATE_C_M 0x20000000
#define DIS_POP_CFOE_C 0x0C68
#define DIS_POP_CFOE_C_M 0x40000000
#define FORCE_SBD_BY_SYNC_DAGC_C 0x0C68
#define FORCE_SBD_BY_SYNC_DAGC_C_M 0x80000000
#define IQK_DPK_COM_RST_C 0x0C6C
#define IQK_DPK_COM_RST_C_M 0x1
#define FAGCRDY_DLY_C 0x0C6C
#define FAGCRDY_DLY_C_M 0x1E
#define INITRST_BY_BACKINIT_C 0x0C6C
#define INITRST_BY_BACKINIT_C_M 0x20
#define POP_MISS_BRK_EN_C 0x0C6C
#define POP_MISS_BRK_EN_C_M 0x40
#define RPT_CNT_OPT_C 0x0C6C
#define RPT_CNT_OPT_C_M 0x380
#define OPT_VLD_POP_C 0x0C6C
#define OPT_VLD_POP_C_M 0x400
#define CH_MUX_ST_MANUAL_C 0x0C6C
#define CH_MUX_ST_MANUAL_C_M 0x800
#define BT_GNT_SEG_OPT_C 0x0C6C
#define BT_GNT_SEG_OPT_C_M 0x3000
#define EN_PRERDY_BY_MAXITER_C 0x0C6C
#define EN_PRERDY_BY_MAXITER_C_M 0x4000
#define RXTD_RESERVED_1_C 0x0C6C
#define RXTD_RESERVED_1_C_M 0xFFFF8000
#define IQK_COM_TX_PATH_EN_FORCE_VAL_C 0x0C70
#define IQK_COM_TX_PATH_EN_FORCE_VAL_C_M 0xF
#define IQK_COM_TX_PATH_EN_FORCE_ON_C 0x0C70
#define IQK_COM_TX_PATH_EN_FORCE_ON_C_M 0x10
#define IQK_COM_RX_PATH_EN_FORCE_VAL_C 0x0C70
#define IQK_COM_RX_PATH_EN_FORCE_VAL_C_M 0x1E0
#define IQK_COM_RX_PATH_EN_FORCE_ON_C 0x0C70
#define IQK_COM_RX_PATH_EN_FORCE_ON_C_M 0x200
#define COLLISION_DET_EN_C 0x0C70
#define COLLISION_DET_EN_C_M 0x400
#define COLLISION_R2T_TH_C 0x0C70
#define COLLISION_R2T_TH_C_M 0xF800
#define COLLISION_R2T_PW_TIMING_C 0x0C70
#define COLLISION_R2T_PW_TIMING_C_M 0x30000
#define COLLISION_T2R_PW_TIMING_C 0x0C70
#define COLLISION_T2R_PW_TIMING_C_M 0x40000
#define COLLISION_PRIMARY_FLAG_C 0x0C70
#define COLLISION_PRIMARY_FLAG_C_M 0x80000
#define TX_COLLISION_T2R_ST_C 0x0C70
#define TX_COLLISION_T2R_ST_C_M 0x3F00000
#define TX_COLLISION_R2T_ST_C 0x0C70
#define TX_COLLISION_R2T_ST_C_M 0xFC000000
#define COLLISION_T2R_TH_MCS0_C 0x0C74
#define COLLISION_T2R_TH_MCS0_C_M 0x1F
#define COLLISION_T2R_TH_MCS1_C 0x0C74
#define COLLISION_T2R_TH_MCS1_C_M 0x3E0
#define COLLISION_T2R_TH_MCS2_C 0x0C74
#define COLLISION_T2R_TH_MCS2_C_M 0x7C00
#define COLLISION_T2R_TH_MCS3_C 0x0C74
#define COLLISION_T2R_TH_MCS3_C_M 0xF8000
#define COLLISION_T2R_TH_MCS4_C 0x0C74
#define COLLISION_T2R_TH_MCS4_C_M 0x1F00000
#define COLLISION_T2R_TH_MCS5_C 0x0C74
#define COLLISION_T2R_TH_MCS5_C_M 0x3E000000
#define TX_COLLISION_OR_CCA_MASK_C 0x0C74
#define TX_COLLISION_OR_CCA_MASK_C_M 0x80000000
#define COLLISION_T2R_TH_MCS6_C 0x0C78
#define COLLISION_T2R_TH_MCS6_C_M 0x1F
#define COLLISION_T2R_TH_MCS7_C 0x0C78
#define COLLISION_T2R_TH_MCS7_C_M 0x3E0
#define COLLISION_T2R_TH_MCS8_C 0x0C78
#define COLLISION_T2R_TH_MCS8_C_M 0x7C00
#define COLLISION_T2R_TH_MCS9_C 0x0C78
#define COLLISION_T2R_TH_MCS9_C_M 0xF8000
#define COLLISION_T2R_TH_MCS10_C 0x0C78
#define COLLISION_T2R_TH_MCS10_C_M 0x1F00000
#define COLLISION_T2R_TH_MCS11_C 0x0C78
#define COLLISION_T2R_TH_MCS11_C_M 0x3E000000
#define TXDAGC_DEF_N_RU0_3_C 0x0C78
#define TXDAGC_DEF_N_RU0_3_C_M 0x80000000
#define COLLISION_T2R_TH_CCK_C 0x0C7C
#define COLLISION_T2R_TH_CCK_C_M 0x1F
#define TXDAGC_DBG_EN_C 0x0C7C
#define TXDAGC_DBG_EN_C_M 0x20
#define DPD_OFF_BY_TXPW_TH_C 0x0C7C
#define DPD_OFF_BY_TXPW_TH_C_M 0x7FC0
#define DPD_OFF_BY_TXPW_OV_C 0x0C7C
#define DPD_OFF_BY_TXPW_OV_C_M 0x8000
#define DPD_OFF_BY_TXPW_BELOW_C 0x0C7C
#define DPD_OFF_BY_TXPW_BELOW_C_M 0x10000
#define T2F_ST_HANG_PROTECT_C 0x0C7C
#define T2F_ST_HANG_PROTECT_C_M 0x100000
#define TXRFC_RSTB_C 0x0C7C
#define TXRFC_RSTB_C_M 0x200000
#define DIS_TXRFC_IOWE_C 0x0C7C
#define DIS_TXRFC_IOWE_C_M 0x400000
#define DIS_TXRFC_IOQ_C 0x0C7C
#define DIS_TXRFC_IOQ_C_M 0x800000
#define T2F_BRK_PDHIT_AT_SAME_TIME_C 0x0C7C
#define T2F_BRK_PDHIT_AT_SAME_TIME_C_M 0x1000000
#define T2F_NEG_GI2OFST_CNT_TH_C 0x0C7C
#define T2F_NEG_GI2OFST_CNT_TH_C_M 0xFE000000
#define BRK_R_HT_BW020_1SS_BOUND_C 0x0D00
#define BRK_R_HT_BW020_1SS_BOUND_C_M 0xF
#define BRK_R_HT_BW020_2SS_BOUND_C 0x0D00
#define BRK_R_HT_BW020_2SS_BOUND_C_M 0xF0
#define BRK_R_HT_BW020_3SS_BOUND_C 0x0D00
#define BRK_R_HT_BW020_3SS_BOUND_C_M 0xF00
#define BRK_R_HT_BW020_4SS_BOUND_C 0x0D00
#define BRK_R_HT_BW020_4SS_BOUND_C_M 0xF000
#define BRK_R_HT_BW040_1SS_BOUND_C 0x0D00
#define BRK_R_HT_BW040_1SS_BOUND_C_M 0xF0000
#define BRK_R_HT_BW040_2SS_BOUND_C 0x0D00
#define BRK_R_HT_BW040_2SS_BOUND_C_M 0xF00000
#define BRK_R_HT_BW040_3SS_BOUND_C 0x0D00
#define BRK_R_HT_BW040_3SS_BOUND_C_M 0xF000000
#define BRK_R_HT_BW040_4SS_BOUND_C 0x0D00
#define BRK_R_HT_BW040_4SS_BOUND_C_M 0xF0000000
#define BRK_R_VHT_BW020_1SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW020_1SS_BOUND_C_M 0xF
#define BRK_R_VHT_BW020_2SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW020_2SS_BOUND_C_M 0xF0
#define BRK_R_VHT_BW020_3SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW020_3SS_BOUND_C_M 0xF00
#define BRK_R_VHT_BW020_4SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW020_4SS_BOUND_C_M 0xF000
#define BRK_R_VHT_BW040_1SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW040_1SS_BOUND_C_M 0xF0000
#define BRK_R_VHT_BW040_2SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW040_2SS_BOUND_C_M 0xF00000
#define BRK_R_VHT_BW040_3SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW040_3SS_BOUND_C_M 0xF000000
#define BRK_R_VHT_BW040_4SS_BOUND_C 0x0D04
#define BRK_R_VHT_BW040_4SS_BOUND_C_M 0xF0000000
#define BRK_R_VHT_BW080_1SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW080_1SS_BOUND_C_M 0xF
#define BRK_R_VHT_BW080_2SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW080_2SS_BOUND_C_M 0xF0
#define BRK_R_VHT_BW080_3SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW080_3SS_BOUND_C_M 0xF00
#define BRK_R_VHT_BW080_4SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW080_4SS_BOUND_C_M 0xF000
#define BRK_R_VHT_BW160_1SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW160_1SS_BOUND_C_M 0xF0000
#define BRK_R_VHT_BW160_2SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW160_2SS_BOUND_C_M 0xF00000
#define BRK_R_VHT_BW160_3SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW160_3SS_BOUND_C_M 0xF000000
#define BRK_R_VHT_BW160_4SS_BOUND_C 0x0D08
#define BRK_R_VHT_BW160_4SS_BOUND_C_M 0xF0000000
#define BRK_R_CHK_NDP_LSIG_VHT_C 0x0D0C
#define BRK_R_CHK_NDP_LSIG_VHT_C_M 0x1
#define BRK_R_CHK_NDP_LSIG_N_C 0x0D0C
#define BRK_R_CHK_NDP_LSIG_N_C_M 0x2
#define BRK_R_CHK_NDP_LSIG_VHT_34SS_C 0x0D0C
#define BRK_R_CHK_NDP_LSIG_VHT_34SS_C_M 0x4
#define BRK_R_CHK_NDP_LSIG_N_34SS_C 0x0D0C
#define BRK_R_CHK_NDP_LSIG_N_34SS_C_M 0x8
#define BRK_R_VHT_MU_NSTS_LMT_C 0x0D0C
#define BRK_R_VHT_MU_NSTS_LMT_C_M 0x70
#define BRK_R_NSTS_SPEC_MU_SEL_C 0x0D0C
#define BRK_R_NSTS_SPEC_MU_SEL_C_M 0x780
#define BRK_R_L_LEN_OVER_TH_C 0x0D10
#define BRK_R_L_LEN_OVER_TH_C_M 0xFFF
#define BRK_R_L_LEN_UNDER_TH_C 0x0D10
#define BRK_R_L_LEN_UNDER_TH_C_M 0xF000
#define BRK_R_HT_LEN_UNDER_TH_C 0x0D10
#define BRK_R_HT_LEN_UNDER_TH_C_M 0xF0000
#define BRK_R_VHT_LEN_UNDER_TH_C 0x0D10
#define BRK_R_VHT_LEN_UNDER_TH_C_M 0xF00000
#define BRK_R_VHT_BW_SUPPORT_C 0x0D10
#define BRK_R_VHT_BW_SUPPORT_C_M 0x3000000
#define BRK_R_VHT_BW_SUPPORT_FORCE_C 0x0D10
#define BRK_R_VHT_BW_SUPPORT_FORCE_C_M 0x4000000
#define BRK_R_RX_SUPPORT_BW_C 0x0D10
#define BRK_R_RX_SUPPORT_BW_C_M 0x38000000
#define BRK_R_BRK_SEL_FOR_CNT_C 0x0D14
#define BRK_R_BRK_SEL_FOR_CNT_C_M 0xFF
#define BRK_R_HT_LEN_MAX_C 0x0D14
#define BRK_R_HT_LEN_MAX_C_M 0xFF00
#define BRK_R_VHT_LEN_MAX_C 0x0D14
#define BRK_R_VHT_LEN_MAX_C_M 0x3FFF0000
#define BRK_R_LRATE_DIS_C 0x0D18
#define BRK_R_LRATE_DIS_C_M 0xFF
#define BRK_R_HT_MCS_LMT_C 0x0D18
#define BRK_R_HT_MCS_LMT_C_M 0x300
#define BRK_R_EN_HT_MCS32_C 0x0D18
#define BRK_R_EN_HT_MCS32_C_M 0x400
#define BRK_R_EN_LDPC_RX_C 0x0D18
#define BRK_R_EN_LDPC_RX_C_M 0x800
#define BRK_R_EN_HT_SHORTGI_C 0x0D18
#define BRK_R_EN_HT_SHORTGI_C_M 0x1000
#define BRK_R_DIS_MASK_ILL_RATE_C 0x0D18
#define BRK_R_DIS_MASK_ILL_RATE_C_M 0x2000
#define BRK_R_EN_VHT_SHORTGI_C 0x0D18
#define BRK_R_EN_VHT_SHORTGI_C_M 0x8000
#define BRK_R_EN_VHT_LEN_LMT_C 0x0D18
#define BRK_R_EN_VHT_LEN_LMT_C_M 0x10000
#define BRK_R_HT_NOT_SUPPORT_C 0x0D18
#define BRK_R_HT_NOT_SUPPORT_C_M 0x20000
#define BRK_R_VHT_NOT_SUPPORT_C 0x0D18
#define BRK_R_VHT_NOT_SUPPORT_C_M 0x40000
#define BRK_R_OFDM_VBON_NEG_BRK_OPT_C 0x0D18
#define BRK_R_OFDM_VBON_NEG_BRK_OPT_C_M 0x180000
#define BRK_R_VHT_NSS_LMT_C 0x0D18
#define BRK_R_VHT_NSS_LMT_C_M 0x600000
#define BRK_R_EN_HT_STBC_1SS_C 0x0D18
#define BRK_R_EN_HT_STBC_1SS_C_M 0x10000000
#define BRK_R_EN_HT_STBC_2SS_C 0x0D18
#define BRK_R_EN_HT_STBC_2SS_C_M 0x20000000
#define BRK_R_EN_VHT_STBC_1SS_C 0x0D18
#define BRK_R_EN_VHT_STBC_1SS_C_M 0x40000000
#define BRK_R_EN_VHT_STBC_2SS_C 0x0D18
#define BRK_R_EN_VHT_STBC_2SS_C_M 0x80000000
#define BRK_R_ILL_ST0_C 0x0D20
#define BRK_R_ILL_ST0_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST1_C 0x0D24
#define BRK_R_ILL_ST1_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST2_C 0x0D28
#define BRK_R_ILL_ST2_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST3_C 0x0D2C
#define BRK_R_ILL_ST3_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST0_EN_C 0x0D30
#define BRK_R_ILL_ST0_EN_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST1_EN_C 0x0D34
#define BRK_R_ILL_ST1_EN_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST2_EN_C 0x0D38
#define BRK_R_ILL_ST2_EN_C_M 0xFFFFFFFF
#define BRK_R_ILL_ST3_EN_C 0x0D3C
#define BRK_R_ILL_ST3_EN_C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_31_0__C 0x0D40
#define BRK_R_BRK_OPT_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_63_32__C 0x0D44
#define BRK_R_BRK_OPT_63_32__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_95_64__C 0x0D48
#define BRK_R_BRK_OPT_95_64__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_127_96__C 0x0D4C
#define BRK_R_BRK_OPT_127_96__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_NDP_31_0__C 0x0D50
#define BRK_R_BRK_OPT_NDP_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_NDP_63_32__C 0x0D54
#define BRK_R_BRK_OPT_NDP_63_32__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_NDP_95_64__C 0x0D58
#define BRK_R_BRK_OPT_NDP_95_64__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_NDP_127_96__C 0x0D5C
#define BRK_R_BRK_OPT_NDP_127_96__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT5_C 0x0D60
#define BRK_R_BRK_OPT5_C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT5_NDP_C 0x0D64
#define BRK_R_BRK_OPT5_NDP_C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT_MU_C 0x0D70
#define BRK_R_BRK_OPT_MU_C_M 0xFFFFFFFF
#define BRK_R_T2F_PDHIT_ST_LMT_IDX_C 0x0D78
#define BRK_R_T2F_PDHIT_ST_LMT_IDX_C_M 0x3
#define BRK_R_T2F_PFD3_ST_LMT_IDX_C 0x0D78
#define BRK_R_T2F_PFD3_ST_LMT_IDX_C_M 0x4
#define BRK_R_WATCH_DOG_ALWAYS_CHK_TXEN_C 0x0D78
#define BRK_R_WATCH_DOG_ALWAYS_CHK_TXEN_C_M 0x10
#define BRK_R_EN_HT_N_ESS_C 0x0D7C
#define BRK_R_EN_HT_N_ESS_C_M 0x1
#define BRK_R_EN_SOUND_WO_NDP_C 0x0D7C
#define BRK_R_EN_SOUND_WO_NDP_C_M 0x2
#define BRK_R_WATCH_DOG_TX_DUR_DATA_ON_C 0x0D7C
#define BRK_R_WATCH_DOG_TX_DUR_DATA_ON_C_M 0x4
#define BRK_R_WATCH_DOG_STBC_EXT_US_C 0x0D7C
#define BRK_R_WATCH_DOG_STBC_EXT_US_C_M 0x8
#define BRK_R_NORMAL_CCA_LMT_C 0x0D7C
#define BRK_R_NORMAL_CCA_LMT_C_M 0x7F0
#define BRK_R_EXTEND_CCA_LMT_C 0x0D7C
#define BRK_R_EXTEND_CCA_LMT_C_M 0x7F000
#define BRK_R_SPOOF_IVLD_PKT_EN_C 0x0D7C
#define BRK_R_SPOOF_IVLD_PKT_EN_C_M 0x80000
#define BRK_R_SPOOF_RXTD_EN_C 0x0D7C
#define BRK_R_SPOOF_RXTD_EN_C_M 0x100000
#define BRK_R_WATCH_DOG_NDP_EXT_US_C 0x0D7C
#define BRK_R_WATCH_DOG_NDP_EXT_US_C_M 0x800000
#define BRK_R_NDP_CCA_LMT_C 0x0D7C
#define BRK_R_NDP_CCA_LMT_C_M 0x7F000000
#define BRK_R_HE_SU_NOT_SUPPORT_C 0x0D80
#define BRK_R_HE_SU_NOT_SUPPORT_C_M 0x1
#define BRK_R_HE_MU_NOT_SUPPORT_C 0x0D80
#define BRK_R_HE_MU_NOT_SUPPORT_C_M 0x2
#define BRK_R_HE_ERSU_NOT_SUPPORT_C 0x0D80
#define BRK_R_HE_ERSU_NOT_SUPPORT_C_M 0x4
#define BRK_R_HE_TB_NOT_SUPPORT_C 0x0D80
#define BRK_R_HE_TB_NOT_SUPPORT_C_M 0x8
#define BRK_R_HE_STBC_NOT_SUPPORT_C 0x0D80
#define BRK_R_HE_STBC_NOT_SUPPORT_C_M 0x10
#define BRK_R_HE_DCM_NOT_SUPPORT_C 0x0D80
#define BRK_R_HE_DCM_NOT_SUPPORT_C_M 0x20
#define BRK_R_HE_N_USER_MAX_C 0x0D80
#define BRK_R_HE_N_USER_MAX_C_M 0x3FC0
#define BRK_R_HE_MAX_NSS_C 0x0D80
#define BRK_R_HE_MAX_NSS_C_M 0x1C000
#define BRK_R_HE_STBC_NSS_LMT_C 0x0D80
#define BRK_R_HE_STBC_NSS_LMT_C_M 0xE0000
#define BRK_R_HE_DCM_NSS_LMT_C 0x0D80
#define BRK_R_HE_DCM_NSS_LMT_C_M 0x700000
#define BRK_R_TB_MAX_NSS_C 0x0D80
#define BRK_R_TB_MAX_NSS_C_M 0x3800000
#define BRK_R_TB_STBC_NSS_LMT_C 0x0D80
#define BRK_R_TB_STBC_NSS_LMT_C_M 0x1C000000
#define BRK_R_TB_DCM_NSS_LMT_C 0x0D80
#define BRK_R_TB_DCM_NSS_LMT_C_M 0xE0000000
#define BRK_R_EN_HE_GI_0P8_C 0x0D84
#define BRK_R_EN_HE_GI_0P8_C_M 0x1
#define BRK_R_EN_HE_GI_1P6_C 0x0D84
#define BRK_R_EN_HE_GI_1P6_C_M 0x2
#define BRK_R_EN_HE_GI_3P2_C 0x0D84
#define BRK_R_EN_HE_GI_3P2_C_M 0x4
#define BRK_R_EN_HE_DOPPLER_C 0x0D84
#define BRK_R_EN_HE_DOPPLER_C_M 0x8
#define BRK_R_HE_MU_BCC_NSS_LMT_C 0x0D84
#define BRK_R_HE_MU_BCC_NSS_LMT_C_M 0x70
#define BRK_R_HEMU_MULTI_USER_MUMIMO_EN_C 0x0D84
#define BRK_R_HEMU_MULTI_USER_MUMIMO_EN_C_M 0x80
#define BRK_R_TB_MUMIMO_EN_C 0x0D84
#define BRK_R_TB_MUMIMO_EN_C_M 0x100
#define BRK_R_EN_HE_BEAM_CHANGE_C 0x0D84
#define BRK_R_EN_HE_BEAM_CHANGE_C_M 0x200
#define BRK_R_EN_HE_PREAMBLE_PUNC_C 0x0D84
#define BRK_R_EN_HE_PREAMBLE_PUNC_C_M 0x400
#define BRK_R_EN_HE_ZERO_USER_C 0x0D84
#define BRK_R_EN_HE_ZERO_USER_C_M 0x800
#define BRK_R_EN_HESU_TB_TYPE_C 0x0D84
#define BRK_R_EN_HESU_TB_TYPE_C_M 0x1000
#define BRK_R_CHK_20M_RU_ALLOC_EN_C 0x0D84
#define BRK_R_CHK_20M_RU_ALLOC_EN_C_M 0x2000
#define BRK_R_EN_NDP_NEG_CLR_COND_C 0x0D84
#define BRK_R_EN_NDP_NEG_CLR_COND_C_M 0x4000
#define BRK_R_SPOOF_FOR_ASYNC_RST_EN_C 0x0D84
#define BRK_R_SPOOF_FOR_ASYNC_RST_EN_C_M 0x8000
#define BRK_R_CHK_ST_IDX_T2F_C 0x0D88
#define BRK_R_CHK_ST_IDX_T2F_C_M 0x3F
#define BRK_R_ST_HANG_LMT_T2F_C 0x0D88
#define BRK_R_ST_HANG_LMT_T2F_C_M 0x7F00
#define BRK_R_CHK_ST_IDX_RX_FEQ_C 0x0D88
#define BRK_R_CHK_ST_IDX_RX_FEQ_C_M 0x1F0000
#define BRK_R_ST_HANG_LMT_RX_FEQ_C 0x0D88
#define BRK_R_ST_HANG_LMT_RX_FEQ_C_M 0x7F000000
#define BRK_R_BRK_OPT6_HE_USER_31_0__C 0x0D90
#define BRK_R_BRK_OPT6_HE_USER_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_31_0__C 0x0D94
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT8_TB_USER_31_0__C 0x0D98
#define BRK_R_BRK_OPT8_TB_USER_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_31_0__C 0x0D9C
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT6_HE_USER_NDP_31_0__C 0x0DA0
#define BRK_R_BRK_OPT6_HE_USER_NDP_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_NDP_31_0__C 0x0DA4
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_NDP_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT8_TB_USER_NDP_31_0__C 0x0DA8
#define BRK_R_BRK_OPT8_TB_USER_NDP_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_NDP_31_0__C 0x0DAC
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_NDP_31_0__C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_1_C 0x0DC0
#define BRK_R_BRK_FOR_ASYNC_RST_EN_1_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_2_C 0x0DC4
#define BRK_R_BRK_FOR_ASYNC_RST_EN_2_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_3_C 0x0DC8
#define BRK_R_BRK_FOR_ASYNC_RST_EN_3_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_4_C 0x0DCC
#define BRK_R_BRK_FOR_ASYNC_RST_EN_4_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_5_C 0x0DD0
#define BRK_R_BRK_FOR_ASYNC_RST_EN_5_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_6_C 0x0DD4
#define BRK_R_BRK_FOR_ASYNC_RST_EN_6_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_7_C 0x0DD8
#define BRK_R_BRK_FOR_ASYNC_RST_EN_7_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_8_C 0x0DDC
#define BRK_R_BRK_FOR_ASYNC_RST_EN_8_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_9_C 0x0DE0
#define BRK_R_BRK_FOR_ASYNC_RST_EN_9_C_M 0xFFFFFFFF
#define BRK_R_BRK_FOR_ASYNC_RST_EN_MU_C 0x0DE4
#define BRK_R_BRK_FOR_ASYNC_RST_EN_MU_C_M 0xFFFFFFFF
#define PATH0_R_DAC_QINV_C 0x1000
#define PATH0_R_DAC_QINV_C_M 0x1
#define PATH0_R_FIFO_CLR_ENB_C 0x1000
#define PATH0_R_FIFO_CLR_ENB_C_M 0x10
#define PATH0_R_T2F_FREERUN_BUF_EN_C 0x1004
#define PATH0_R_T2F_FREERUN_BUF_EN_C_M 0x1
#define PATH0_R_T2F_L1_LATE_EN_C 0x1004
#define PATH0_R_T2F_L1_LATE_EN_C_M 0x2
#define PATH0_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C 0x1004
#define PATH0_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C_M 0x10
#define PATH0_R_T2F_DCCL_FILT_EN_C 0x1004
#define PATH0_R_T2F_DCCL_FILT_EN_C_M 0x100
#define PATH0_R_BT_GNT_RXTD_LATCH_EN_C 0x1004
#define PATH0_R_BT_GNT_RXTD_LATCH_EN_C_M 0x1000
#define PATH0_R_TD_CLK_GCK_EN_C 0x1008
#define PATH0_R_TD_CLK_GCK_EN_C_M 0x1
#define PATH0_R_1RCCA_CLK_GCK_ON_C 0x1008
#define PATH0_R_1RCCA_CLK_GCK_ON_C_M 0x10
#define PATH0_R_SYNC_RST_EN_TD_PATH_C 0x100C
#define PATH0_R_SYNC_RST_EN_TD_PATH_C_M 0x1
#define PATH0_R_SYNC_RST_EN_FFT_C 0x100C
#define PATH0_R_SYNC_RST_EN_FFT_C_M 0x10
#define PATH0_R_SYNC_RST_EN_TXBUF_C 0x100C
#define PATH0_R_SYNC_RST_EN_TXBUF_C_M 0x100
#define PATH0_R_SYNC_RST_EN_RXBUF_C 0x100C
#define PATH0_R_SYNC_RST_EN_RXBUF_C_M 0x1000
#define PATH0_R_SYNC_RST_EN_DCCL_C 0x100C
#define PATH0_R_SYNC_RST_EN_DCCL_C_M 0x10000
#define PATH0_R_SYNC_RST_EN_T2F_C 0x100C
#define PATH0_R_SYNC_RST_EN_T2F_C_M 0x100000
#define PATH0_R_SYNC_RST_EN_RXFIR_COMP_C 0x100C
#define PATH0_R_SYNC_RST_EN_RXFIR_COMP_C_M 0x1000000
#define PATH0_R_DCCL_CFO_TH_EN_C 0x1010
#define PATH0_R_DCCL_CFO_TH_EN_C_M 0x1
#define PATH0_R_DCCL_52B_SYMB_TH_EN_C 0x1010
#define PATH0_R_DCCL_52B_SYMB_TH_EN_C_M 0x10
#define PATH0_R_DCCL_52B_SYMB_TH_SEL_C 0x1010
#define PATH0_R_DCCL_52B_SYMB_TH_SEL_C_M 0x20
#define PATH0_R_TX_STO_TRIG_SELECT_C 0x1014
#define PATH0_R_TX_STO_TRIG_SELECT_C_M 0x1
#define PATH0_R_TX_STO_FIRST_PE_SELECT_C 0x1014
#define PATH0_R_TX_STO_FIRST_PE_SELECT_C_M 0x2
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_L_C_M 0x7
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_L_C_M 0x70
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_L_C_M 0x700
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_L_C_M 0x7000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_L_C_M 0x70000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_L_C_M 0x700000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_L_C_M 0x7000000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_L_C 0x1018
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_L_C_M 0x70000000
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_L_C 0x101C
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_L_C_M 0x8
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C 0x101C
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C_M 0x10
#define PATH0_R_STO_INT_SEL_L_C 0x101C
#define PATH0_R_STO_INT_SEL_L_C_M 0x20
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C 0x101C
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C_M 0x380
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_L_C 0x101C
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_L_C_M 0x400
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_L_C 0x101C
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_L_C_M 0x800
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_L_C 0x101C
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_L_C_M 0x1000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HT_C_M 0x7
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HT_C_M 0x70
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HT_C_M 0x700
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HT_C_M 0x7000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HT_C_M 0x70000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HT_C_M 0x700000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HT_C_M 0x7000000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HT_C 0x1020
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HT_C_M 0x70000000
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HT_C 0x1024
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HT_C_M 0x8
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C 0x1024
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C_M 0x10
#define PATH0_R_STO_INT_SEL_HT_C 0x1024
#define PATH0_R_STO_INT_SEL_HT_C_M 0x20
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C 0x1024
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C_M 0x380
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HT_C 0x1024
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HT_C_M 0x400
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HT_C 0x1024
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HT_C_M 0x800
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HT_C 0x1024
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HT_C_M 0x1000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_VHT_C_M 0x7
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_VHT_C_M 0x70
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_VHT_C_M 0x700
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_VHT_C_M 0x7000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_VHT_C_M 0x70000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_VHT_C_M 0x700000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_VHT_C_M 0x7000000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_VHT_C 0x1028
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_VHT_C_M 0x70000000
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_VHT_C 0x102C
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_VHT_C_M 0x8
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C 0x102C
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C_M 0x10
#define PATH0_R_STO_INT_SEL_VHT_C 0x102C
#define PATH0_R_STO_INT_SEL_VHT_C_M 0x20
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C 0x102C
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C_M 0x380
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C 0x102C
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C_M 0x400
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C 0x102C
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C_M 0x800
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C 0x102C
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C_M 0x1000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HE_C_M 0x7
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HE_C_M 0x70
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HE_C_M 0x700
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HE_C_M 0x7000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HE_C_M 0x70000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HE_C_M 0x700000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HE_C_M 0x7000000
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HE_C 0x1030
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HE_C_M 0x70000000
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HE_C 0x1034
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HE_C_M 0x8
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C 0x1034
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C_M 0x10
#define PATH0_R_STO_INT_SEL_HE_C 0x1034
#define PATH0_R_STO_INT_SEL_HE_C_M 0x20
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C 0x1034
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C_M 0x380
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HE_C 0x1034
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HE_C_M 0x400
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HE_C 0x1034
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HE_C_M 0x800
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HE_C 0x1034
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HE_C_M 0x1000
#define PATH0_R_HW_SI_READ_ADDR_C 0x1200
#define PATH0_R_HW_SI_READ_ADDR_C_M 0xFF
#define PATH0_R_HW_SI_READ_EDGE_OPT_C 0x1200
#define PATH0_R_HW_SI_READ_EDGE_OPT_C_M 0x300
#define PATH0_R_HW_SI_ZERO_PADDING_EN_C 0x1200
#define PATH0_R_HW_SI_ZERO_PADDING_EN_C_M 0x8000
#define PATH0_R_HW_SI_BYPASS_ST_MASK_C 0x1200
#define PATH0_R_HW_SI_BYPASS_ST_MASK_C_M 0x10000
#define PATH0_R_HW_SI_DATA_E_INV_C 0x1200
#define PATH0_R_HW_SI_DATA_E_INV_C_M 0x20000
#define PATH0_R_HW_SI_SEL_DBG_C 0x1200
#define PATH0_R_HW_SI_SEL_DBG_C_M 0xC0000
#define PATH0_R_HW_SI_DBG_MODE_C 0x1200
#define PATH0_R_HW_SI_DBG_MODE_C_M 0x100000
#define PATH0_R_HW_SI_ZERO_PADDING_NUM_C 0x1200
#define PATH0_R_HW_SI_ZERO_PADDING_NUM_C_M 0x3E00000
#define PATH0_R_HW_SI_DBG_TX_TRIG_C 0x1200
#define PATH0_R_HW_SI_DBG_TX_TRIG_C_M 0x4000000
#define PATH0_R_HW_SI_DIS_W_RX_TRIG_C 0x1200
#define PATH0_R_HW_SI_DIS_W_RX_TRIG_C_M 0x10000000
#define PATH0_R_HW_SI_DIS_W_TX_TRIG_C 0x1200
#define PATH0_R_HW_SI_DIS_W_TX_TRIG_C_M 0x20000000
#define PATH0_R_HW_SI_DIS_R_TRIG_C 0x1200
#define PATH0_R_HW_SI_DIS_R_TRIG_C_M 0x40000000
#define PATH0_R_HW_SI_DBG_RX_CMD_0_C 0x1204
#define PATH0_R_HW_SI_DBG_RX_CMD_0_C_M 0xFFFF
#define PATH0_R_HW_SI_DBG_RX_CMD_1_C 0x1204
#define PATH0_R_HW_SI_DBG_RX_CMD_1_C_M 0xFFFF0000
#define PATH0_R_HW_SI_DBG_TX_CMD_0_C 0x1208
#define PATH0_R_HW_SI_DBG_TX_CMD_0_C_M 0xFFFF
#define PATH0_R_HW_SI_DBG_TX_CMD_1_C 0x1208
#define PATH0_R_HW_SI_DBG_TX_CMD_1_C_M 0xFFFF0000
#define PATH0_R_ANAPAR_ST1P5_SEL_C 0x120C
#define PATH0_R_ANAPAR_ST1P5_SEL_C_M 0xF
#define PATH0_R_ANAPAR_ST3P5_SEL_C 0x120C
#define PATH0_R_ANAPAR_ST3P5_SEL_C_M 0xF0
#define PATH0_R_ANAPAR_DIS_TSSI_DCK_ST_C 0x120C
#define PATH0_R_ANAPAR_DIS_TSSI_DCK_ST_C_M 0x80000000
#define PATH0_R_RFMODE_RSTB_EQ0_EN_C 0x1210
#define PATH0_R_RFMODE_RSTB_EQ0_EN_C_M 0x1
#define PATH0_R_PW_RSTB_EQ0_EN_C 0x1210
#define PATH0_R_PW_RSTB_EQ0_EN_C_M 0x2
#define PATH0_R_RSTB_EQ0_EN_C 0x1210
#define PATH0_R_RSTB_EQ0_EN_C_M 0x4
#define PATH0_R_RFMODE_RSTB_EQ0_C 0x1210
#define PATH0_R_RFMODE_RSTB_EQ0_C_M 0xF0
#define PATH0_R_PW_RSTB_EQ0_C 0x1210
#define PATH0_R_PW_RSTB_EQ0_C_M 0xFF00
#define PATH0_R_RSTB_EQ0_C 0x1210
#define PATH0_R_RSTB_EQ0_C_M 0xFFFF0000
#define PATH0_R_RFC_SI_SEL_0_C 0x1214
#define PATH0_R_RFC_SI_SEL_0_C_M 0x1
#define PATH0_R_RFC_SI_SEL_1_C 0x1214
#define PATH0_R_RFC_SI_SEL_1_C_M 0x10
#define PATH0_R_HW_SI_W_RX_TRIG_DLY_EN_C 0x1218
#define PATH0_R_HW_SI_W_RX_TRIG_DLY_EN_C_M 0x1
#define PATH0_R_HW_SI_W_TX_TRIG_DLY_EN_C 0x1218
#define PATH0_R_HW_SI_W_TX_TRIG_DLY_EN_C_M 0x2
#define PATH0_R_HW_SI_R_TRIG_DLY_EN_C 0x1218
#define PATH0_R_HW_SI_R_TRIG_DLY_EN_C_M 0x4
#define PATH0_R_HW_SI_W_RX_TRIG_DLY_C 0x1218
#define PATH0_R_HW_SI_W_RX_TRIG_DLY_C_M 0xF0
#define PATH0_R_HW_SI_W_TX_TRIG_DLY_C 0x1218
#define PATH0_R_HW_SI_W_TX_TRIG_DLY_C_M 0xF00
#define PATH0_R_HW_SI_R_TRIG_DLY_C 0x1218
#define PATH0_R_HW_SI_R_TRIG_DLY_C_M 0xF000
#define PATH0_R_ANAPAR_RST_SEL_C 0x12A0
#define PATH0_R_ANAPAR_RST_SEL_C_M 0xF
#define PATH0_R_ANAPAR_RST_TX_SEL_C 0x12A0
#define PATH0_R_ANAPAR_RST_TX_SEL_C_M 0xF0
#define PATH0_R_ANAPAR_CTSDM_131_128__C 0x12A0
#define PATH0_R_ANAPAR_CTSDM_131_128__C_M 0xF00
#define PATH0_R_TXCK_FORCE_VAL_C 0x12A0
#define PATH0_R_TXCK_FORCE_VAL_C_M 0x7000
#define PATH0_R_TXCK_FORCE_ON_C 0x12A0
#define PATH0_R_TXCK_FORCE_ON_C_M 0x8000
#define PATH0_R_RXCK_FORCE_VAL_C 0x12A0
#define PATH0_R_RXCK_FORCE_VAL_C_M 0x70000
#define PATH0_R_RXCK_FORCE_ON_C 0x12A0
#define PATH0_R_RXCK_FORCE_ON_C_M 0x80000
#define PATH0_R_RXCK_RFBW0_C 0x12A0
#define PATH0_R_RXCK_RFBW0_C_M 0x700000
#define PATH0_R_RXCK_RFBW1_C 0x12A0
#define PATH0_R_RXCK_RFBW1_C_M 0x3800000
#define PATH0_R_RXCK_RFBW2_C 0x12A0
#define PATH0_R_RXCK_RFBW2_C_M 0x1C000000
#define PATH0_R_RXCK_RFBW3_C 0x12A0
#define PATH0_R_RXCK_RFBW3_C_M 0xE0000000
#define PATH0_R_RXCK_RFBW4_C 0x12A4
#define PATH0_R_RXCK_RFBW4_C_M 0x7
#define PATH0_R_RXCK_RFBW5_C 0x12A4
#define PATH0_R_RXCK_RFBW5_C_M 0x38
#define PATH0_R_RXCK_RFBW6_C 0x12A4
#define PATH0_R_RXCK_RFBW6_C_M 0x1C0
#define PATH0_R_TXCK_RFBW0_C 0x12A4
#define PATH0_R_TXCK_RFBW0_C_M 0x3800
#define PATH0_R_TXCK_RFBW1_C 0x12A4
#define PATH0_R_TXCK_RFBW1_C_M 0x1C000
#define PATH0_R_TXCK_RFBW2_C 0x12A4
#define PATH0_R_TXCK_RFBW2_C_M 0xE0000
#define PATH0_R_TXCK_RFBW3_C 0x12A4
#define PATH0_R_TXCK_RFBW3_C_M 0x700000
#define PATH0_R_TXCK_RFBW4_C 0x12A4
#define PATH0_R_TXCK_RFBW4_C_M 0x3800000
#define PATH0_R_TXCK_RFBW5_C 0x12A4
#define PATH0_R_TXCK_RFBW5_C_M 0x1C000000
#define PATH0_R_TXCK_RFBW6_C 0x12A4
#define PATH0_R_TXCK_RFBW6_C_M 0xE0000000
#define PATH0_R_EN_RXCK_TX_C 0x12A8
#define PATH0_R_EN_RXCK_TX_C_M 0x1
#define PATH0_R_RXCK_TX_C 0x12A8
#define PATH0_R_RXCK_TX_C_M 0xE
#define PATH0_R_RXCK_TX_FTM_C 0x12A8
#define PATH0_R_RXCK_TX_FTM_C_M 0x70
#define PATH0_R_CLK_RFC_GCK_EN_C 0x12A8
#define PATH0_R_CLK_RFC_GCK_EN_C_M 0x80
#define PATH0_R_RF0_GEN_DBG_SEL_C 0x12A8
#define PATH0_R_RF0_GEN_DBG_SEL_C_M 0x300
#define PATH0_R_RFMODE_GNT_WL_DIS_TX_OPT_C 0x12A8
#define PATH0_R_RFMODE_GNT_WL_DIS_TX_OPT_C_M 0x800
#define PATH0_R_RFAFE_PWSAV_EN_C 0x12A8
#define PATH0_R_RFAFE_PWSAV_EN_C_M 0xF000
#define PATH0_R_RFMODE_ORI_RXB_OFF_C 0x12A8
#define PATH0_R_RFMODE_ORI_RXB_OFF_C_M 0xF0000
#define PATH0_R_RFMODE_ORI_RXB_LOWPW_C 0x12A8
#define PATH0_R_RFMODE_ORI_RXB_LOWPW_C_M 0xF00000
#define PATH0_R_RFMODE_FTM_RXB_OFF_C 0x12A8
#define PATH0_R_RFMODE_FTM_RXB_OFF_C_M 0xF000000
#define PATH0_R_RFMODE_FTM_RXB_LOWPW_C 0x12A8
#define PATH0_R_RFMODE_FTM_RXB_LOWPW_C_M 0xF0000000
#define PATH0_R_RSTB_3WIRE_C 0x12AC
#define PATH0_R_RSTB_3WIRE_C_M 0x1
#define PATH0_R_EN_NRBW_AT_TX_C 0x12AC
#define PATH0_R_EN_NRBW_AT_TX_C_M 0x4
#define PATH0_R_RFMODE_ORI_TX_C 0x12AC
#define PATH0_R_RFMODE_ORI_TX_C_M 0xF0
#define PATH0_R_RFMODE_ORI_TX_TXOFF_C 0x12AC
#define PATH0_R_RFMODE_ORI_TX_TXOFF_C_M 0xF00
#define PATH0_R_RFMODE_ORI_RX_OFDM_CCA_C 0x12AC
#define PATH0_R_RFMODE_ORI_RX_OFDM_CCA_C_M 0xF000
#define PATH0_R_RFMODE_ORI_RX_CCK_CCA_C 0x12AC
#define PATH0_R_RFMODE_ORI_RX_CCK_CCA_C_M 0xF0000
#define PATH0_R_RFMODE_ORI_RX_IDLE_C 0x12AC
#define PATH0_R_RFMODE_ORI_RX_IDLE_C_M 0xF00000
#define PATH0_R_RFMODE_FTM_TX_C 0x12AC
#define PATH0_R_RFMODE_FTM_TX_C_M 0xF000000
#define PATH0_R_RFMODE_FTM_TX_TXOFF_C 0x12AC
#define PATH0_R_RFMODE_FTM_TX_TXOFF_C_M 0xF0000000
#define PATH0_R_RFMODE_FTM_RX_OFDM_CCA_C 0x12B0
#define PATH0_R_RFMODE_FTM_RX_OFDM_CCA_C_M 0xF
#define PATH0_R_RFMODE_FTM_RX_CCK_CCA_C 0x12B0
#define PATH0_R_RFMODE_FTM_RX_CCK_CCA_C_M 0xF0
#define PATH0_R_RFMODE_FTM_RX_IDLE_C 0x12B0
#define PATH0_R_RFMODE_FTM_RX_IDLE_C_M 0xF00
#define PATH0_R_RXB_IDX_AT_TX_C 0x12B0
#define PATH0_R_RXB_IDX_AT_TX_C_M 0x1F000
#define PATH0_R_TIA_IDX_AT_TX_C 0x12B0
#define PATH0_R_TIA_IDX_AT_TX_C_M 0x20000
#define PATH0_R_LNA_IDX_AT_TX_C 0x12B0
#define PATH0_R_LNA_IDX_AT_TX_C_M 0x1C0000
#define PATH0_R_TIA_EXT_BW_AT_TX_C 0x12B0
#define PATH0_R_TIA_EXT_BW_AT_TX_C_M 0x200000
#define PATH0_R_SI_RADDR_C 0x12B0
#define PATH0_R_SI_RADDR_C_M 0x3FC00000
#define PATH0_R_RST_3WIRE_CONFLICT_CNT_C 0x12B0
#define PATH0_R_RST_3WIRE_CONFLICT_CNT_C_M 0x80000000
#define PATH0_R_SOFT3WIRE_DATA_C 0x12B4
#define PATH0_R_SOFT3WIRE_DATA_C_M 0xFFFFFFF
#define PATH0_R_TXAGC_AT_SLEEP_C 0x12B8
#define PATH0_R_TXAGC_AT_SLEEP_C_M 0x3F
#define PATH0_R_RXB_IDX_AT_SLEEP_C 0x12B8
#define PATH0_R_RXB_IDX_AT_SLEEP_C_M 0x7C0
#define PATH0_R_TIA_IDX_AT_SLEEP_C 0x12B8
#define PATH0_R_TIA_IDX_AT_SLEEP_C_M 0x800
#define PATH0_R_LNA_IDX_AT_SLEEP_C 0x12B8
#define PATH0_R_LNA_IDX_AT_SLEEP_C_M 0x7000
#define PATH0_R_TIA_EXT_BW_AT_SLEEP_C 0x12B8
#define PATH0_R_TIA_EXT_BW_AT_SLEEP_C_M 0x8000
#define PATH0_R_EN_NRBW_AT_SLEEP_C 0x12B8
#define PATH0_R_EN_NRBW_AT_SLEEP_C_M 0x10000
#define PATH0_R_RFMODE_AT_SLEEP_C 0x12B8
#define PATH0_R_RFMODE_AT_SLEEP_C_M 0x1E0000
#define PATH0_R_TXAGC_BYPASS_C 0x12B8
#define PATH0_R_TXAGC_BYPASS_C_M 0x200000
#define PATH0_R_RXB_BYPASS_C 0x12B8
#define PATH0_R_RXB_BYPASS_C_M 0x400000
#define PATH0_R_TIA_BYPASS_C 0x12B8
#define PATH0_R_TIA_BYPASS_C_M 0x800000
#define PATH0_R_LNA_BYPASS_C 0x12B8
#define PATH0_R_LNA_BYPASS_C_M 0x1000000
#define PATH0_R_TIA_EXT_BYPASS_C 0x12B8
#define PATH0_R_TIA_EXT_BYPASS_C_M 0x2000000
#define PATH0_R_EN_NRBW_BYPASS_C 0x12B8
#define PATH0_R_EN_NRBW_BYPASS_C_M 0x4000000
#define PATH0_R_RFREG_DIS_GATING_C 0x12B8
#define PATH0_R_RFREG_DIS_GATING_C_M 0x8000000
#define PATH0_R_RSTB_ANAPAR_C 0x12B8
#define PATH0_R_RSTB_ANAPAR_C_M 0x10000000
#define PATH0_R_ANAPAR_SEL_OPT_C 0x12B8
#define PATH0_R_ANAPAR_SEL_OPT_C_M 0x20000000
#define PATH0_R_ANAPAR_DBG_MODE_C 0x12B8
#define PATH0_R_ANAPAR_DBG_MODE_C_M 0x40000000
#define PATH0_R_ANAPAR_DIS_GATING_C 0x12B8
#define PATH0_R_ANAPAR_DIS_GATING_C_M 0x80000000
#define PATH0_R_ANAPAR_ST0_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST0_SEL_C_M 0xF
#define PATH0_R_ANAPAR_ST1_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST1_SEL_C_M 0xF0
#define PATH0_R_ANAPAR_ST2_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST2_SEL_C_M 0xF00
#define PATH0_R_ANAPAR_ST3_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST3_SEL_C_M 0xF000
#define PATH0_R_ANAPAR_ST4_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST4_SEL_C_M 0xF0000
#define PATH0_R_ANAPAR_ST5_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST5_SEL_C_M 0xF00000
#define PATH0_R_ANAPAR_ST6_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST6_SEL_C_M 0xF000000
#define PATH0_R_ANAPAR_ST7_SEL_C 0x12BC
#define PATH0_R_ANAPAR_ST7_SEL_C_M 0xF0000000
#define PATH0_R_ANAPAR_ST8_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST8_SEL_C_M 0xF
#define PATH0_R_ANAPAR_ST9_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST9_SEL_C_M 0xF0
#define PATH0_R_ANAPAR_ST10_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST10_SEL_C_M 0xF00
#define PATH0_R_ANAPAR_ST11_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST11_SEL_C_M 0xF000
#define PATH0_R_ANAPAR_ST12_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST12_SEL_C_M 0xF0000
#define PATH0_R_ANAPAR_ST13_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST13_SEL_C_M 0xF00000
#define PATH0_R_ANAPAR_ST14_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST14_SEL_C_M 0xF000000
#define PATH0_R_ANAPAR_ST15_SEL_C 0x12C0
#define PATH0_R_ANAPAR_ST15_SEL_C_M 0xF0000000
#define PATH0_R_ANAPAR_ST16_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST16_SEL_C_M 0xF
#define PATH0_R_ANAPAR_ST17_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST17_SEL_C_M 0xF0
#define PATH0_R_ANAPAR_ST18_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST18_SEL_C_M 0xF00
#define PATH0_R_ANAPAR_ST19_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST19_SEL_C_M 0xF000
#define PATH0_R_ANAPAR_ST20_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST20_SEL_C_M 0xF0000
#define PATH0_R_ANAPAR_ST21_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST21_SEL_C_M 0xF00000
#define PATH0_R_ANAPAR_ST22_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST22_SEL_C_M 0xF000000
#define PATH0_R_ANAPAR_ST23_SEL_C 0x12C4
#define PATH0_R_ANAPAR_ST23_SEL_C_M 0xF0000000
#define PATH0_R_ANAPAR_ST24_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST24_SEL_C_M 0xF
#define PATH0_R_ANAPAR_ST25_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST25_SEL_C_M 0xF0
#define PATH0_R_ANAPAR_ST26_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST26_SEL_C_M 0xF00
#define PATH0_R_ANAPAR_ST27_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST27_SEL_C_M 0xF000
#define PATH0_R_ANAPAR_ST28_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST28_SEL_C_M 0xF0000
#define PATH0_R_ANAPAR_ST29_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST29_SEL_C_M 0xF00000
#define PATH0_R_ANAPAR_ST30_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST30_SEL_C_M 0xF000000
#define PATH0_R_ANAPAR_ST31_SEL_C 0x12C8
#define PATH0_R_ANAPAR_ST31_SEL_C_M 0xF0000000
#define PATH0_R_ANAPAR_CTSDM_31_0__C 0x12CC
#define PATH0_R_ANAPAR_CTSDM_31_0__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_CTSDM_63_32__C 0x12D0
#define PATH0_R_ANAPAR_CTSDM_63_32__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_CTSDM_95_64__C 0x12D4
#define PATH0_R_ANAPAR_CTSDM_95_64__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_CTSDM_127_96__C 0x12D8
#define PATH0_R_ANAPAR_CTSDM_127_96__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_31_0__C 0x12DC
#define PATH0_R_ANAPAR_31_0__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_63_32__C 0x12E0
#define PATH0_R_ANAPAR_63_32__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_95_64__C 0x12E4
#define PATH0_R_ANAPAR_95_64__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_127_96__C 0x12E8
#define PATH0_R_ANAPAR_127_96__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_143_128__C 0x12EC
#define PATH0_R_ANAPAR_143_128__C_M 0xFFFF
#define PATH0_R_ANAPAR_LBK_15_0__C 0x12EC
#define PATH0_R_ANAPAR_LBK_15_0__C_M 0xFFFF0000
#define PATH0_R_ANAPAR_LBK_47_16__C 0x12F0
#define PATH0_R_ANAPAR_LBK_47_16__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_LBK_79_48__C 0x12F4
#define PATH0_R_ANAPAR_LBK_79_48__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_LBK_111_80__C 0x12F8
#define PATH0_R_ANAPAR_LBK_111_80__C_M 0xFFFFFFFF
#define PATH0_R_ANAPAR_LBK_143_112__C 0x12FC
#define PATH0_R_ANAPAR_LBK_143_112__C_M 0xFFFFFFFF
#define CNT_LA_TRIG_C 0x1700
#define CNT_LA_TRIG_C_M 0xFFFF
#define CNT_CCKTXEN_C 0x1700
#define CNT_CCKTXEN_C_M 0xFFFF0000
#define CNT_CCKTXON_C 0x1704
#define CNT_CCKTXON_C_M 0xFFFF
#define CNT_DBG_BIT_C 0x1704
#define CNT_DBG_BIT_C_M 0xFFFF0000
#define CNT_CCK_CCA_P0_C 0x1710
#define CNT_CCK_CCA_P0_C_M 0xFFFF
#define CNT_CCK_CRC16FAIL_P0_C 0x1710
#define CNT_CCK_CRC16FAIL_P0_C_M 0xFFFF0000
#define CNT_CCK_CRC32OK_P0_C 0x1714
#define CNT_CCK_CRC32OK_P0_C_M 0xFFFF
#define CNT_CCK_CRC32FAIL_P0_C 0x1714
#define CNT_CCK_CRC32FAIL_P0_C_M 0xFFFF0000
#define CNT_CCK_CCA_P1_C 0x1718
#define CNT_CCK_CCA_P1_C_M 0xFFFF
#define CNT_CCK_CRC16FAIL_P1_C 0x1718
#define CNT_CCK_CRC16FAIL_P1_C_M 0xFFFF0000
#define CNT_CCK_CRC32OK_P1_C 0x171C
#define CNT_CCK_CRC32OK_P1_C_M 0xFFFF
#define CNT_CCK_CRC32FAIL_P1_C 0x171C
#define CNT_CCK_CRC32FAIL_P1_C_M 0xFFFF0000
#define AXTOP_BIST_C 0x1720
#define AXTOP_BIST_C_M 0xFFFFFFFF
#define AXRX_IN_BIST_C 0x1724
#define AXRX_IN_BIST_C_M 0xFFFFFFFF
#define AXTD_BIST_C 0x1728
#define AXTD_BIST_C_M 0xFFFFFFFF
#define AXOUT_BIST_C 0x172C
#define AXOUT_BIST_C_M 0xFFFFFFFF
#define DBG32_D_C 0x1730
#define DBG32_D_C_M 0xFFFFFFFF
#define PSD_PW_C 0x1734
#define PSD_PW_C_M 0x1FFFFFF
#define PSD_OK_FLAG_C 0x1734
#define PSD_OK_FLAG_C_M 0x2000000
#define EDCCA_IOQ_P0_A_C 0x1738
#define EDCCA_IOQ_P0_A_C_M 0xFFFFFFFF
#define EDCCA_IOQ_P0_B_C 0x173C
#define EDCCA_IOQ_P0_B_C_M 0xFFFFFFFF
#define EDCCA_IOQ_P1_A_C 0x1740
#define EDCCA_IOQ_P1_A_C_M 0xFFFFFFFF
#define EDCCA_IOQ_P1_B_C 0x1744
#define EDCCA_IOQ_P1_B_C_M 0xFFFFFFFF
#define RO_SI_R_DATA_AFC_C 0x1748
#define RO_SI_R_DATA_AFC_C_M 0xFFFFFFFF
#define SW_SI_READ_DATA_C 0x174C
#define SW_SI_READ_DATA_C_M 0xFFFFF
#define SW_SI_CNT_CONFLICT_C 0x174C
#define SW_SI_CNT_CONFLICT_C_M 0xF00000
#define SW_SI_W_BUSY_C 0x174C
#define SW_SI_W_BUSY_C_M 0x1000000
#define SW_SI_R_BUSY_C 0x174C
#define SW_SI_R_BUSY_C_M 0x2000000
#define SW_SI_READ_DATA_DONE_C 0x174C
#define SW_SI_READ_DATA_DONE_C_M 0x4000000
#define CNT_SW_SI_R_C 0x1750
#define CNT_SW_SI_R_C_M 0xFFFF
#define CNT_SW_SI_W_C 0x1750
#define CNT_SW_SI_W_C_M 0xFFFF0000
#define SWSI_RECORD_1ST_C 0x1758
#define SWSI_RECORD_1ST_C_M 0x3FFFFF
#define SWSI_RECORD_2ND_C 0x1760
#define SWSI_RECORD_2ND_C_M 0x3FFFFF
#define SWSI_CMD_CNT_C 0x1764
#define SWSI_CMD_CNT_C_M 0x3F
#define SWSI_NOW_IS_1ST_C 0x1764
#define SWSI_NOW_IS_1ST_C_M 0x40000000
#define SWSI_NOW_IS_2ND_C 0x1764
#define SWSI_NOW_IS_2ND_C_M 0x80000000
#define HWSI_RECORD_1ST_0_C 0x1768
#define HWSI_RECORD_1ST_0_C_M 0x1FFF
#define HWSI_RECORD_1ST_1_C 0x1768
#define HWSI_RECORD_1ST_1_C_M 0x1FFF0000
#define HWSI_RECORD_2ND_0_C 0x176C
#define HWSI_RECORD_2ND_0_C_M 0x1FFF
#define HWSI_RECORD_2ND_1_C 0x176C
#define HWSI_RECORD_2ND_1_C_M 0x1FFF0000
#define HWSI_RECORD_3RD_0_C 0x1770
#define HWSI_RECORD_3RD_0_C_M 0x1FFF
#define HWSI_RECORD_3RD_1_C 0x1770
#define HWSI_RECORD_3RD_1_C_M 0x1FFF0000
#define HWSI_RECORD_4TH_0_C 0x1774
#define HWSI_RECORD_4TH_0_C_M 0x1FFF
#define HWSI_RECORD_4TH_1_C 0x1774
#define HWSI_RECORD_4TH_1_C_M 0x1FFF0000
#define HWSI_CMD_CNT_C 0x1778
#define HWSI_CMD_CNT_C_M 0x3F
#define HWSI_NOW_IS_1ST_C 0x1778
#define HWSI_NOW_IS_1ST_C_M 0x10000000
#define HWSI_NOW_IS_2ND_C 0x1778
#define HWSI_NOW_IS_2ND_C_M 0x20000000
#define HWSI_NOW_IS_3RD_C 0x1778
#define HWSI_NOW_IS_3RD_C_M 0x40000000
#define HWSI_NOW_IS_4TH_C 0x1778
#define HWSI_NOW_IS_4TH_C_M 0x80000000
#define WLS0_RFMODE_C 0x177C
#define WLS0_RFMODE_C_M 0xF
#define WLS0_TSSI_OFST_C 0x177C
#define WLS0_TSSI_OFST_C_M 0x1F0
#define WLS0_TX_CCK_IND_C 0x177C
#define WLS0_TX_CCK_IND_C_M 0x200
#define WLS0_TX_GAIN_C 0x177C
#define WLS0_TX_GAIN_C_M 0xFC00
#define WLS0_EN_PAD_GAPK_C 0x177C
#define WLS0_EN_PAD_GAPK_C_M 0x10000
#define WLS0_EN_PA_GAPK_C 0x177C
#define WLS0_EN_PA_GAPK_C_M 0x20000
#define WLS0_PAD_GAPK_IDX_C 0x177C
#define WLS0_PAD_GAPK_IDX_C_M 0x1FC0000
#define WLS0_PA_GAPK_IDX_C 0x177C
#define WLS0_PA_GAPK_IDX_C_M 0x7E000000
#define WLS1_RFMODE_C 0x1780
#define WLS1_RFMODE_C_M 0xF
#define WLS1_TSSI_OFST_C 0x1780
#define WLS1_TSSI_OFST_C_M 0x1F0
#define WLS1_TX_CCK_IND_C 0x1780
#define WLS1_TX_CCK_IND_C_M 0x200
#define WLS1_TX_GAIN_C 0x1780
#define WLS1_TX_GAIN_C_M 0xFC00
#define WLS1_EN_PAD_GAPK_C 0x1780
#define WLS1_EN_PAD_GAPK_C_M 0x10000
#define WLS1_EN_PA_GAPK_C 0x1780
#define WLS1_EN_PA_GAPK_C_M 0x20000
#define WLS1_PAD_GAPK_IDX_C 0x1780
#define WLS1_PAD_GAPK_IDX_C_M 0x1FC0000
#define WLS1_PA_GAPK_IDX_C 0x1780
#define WLS1_PA_GAPK_IDX_C_M 0x7E000000
#define BW_TXS0_C 0x1784
#define BW_TXS0_C_M 0x7
#define DAC_0P5DB_S0_C 0x1784
#define DAC_0P5DB_S0_C_M 0x8
#define GAIN_TX_S0_C 0x1784
#define GAIN_TX_S0_C_M 0x1F0
#define GAIN_TX_GAPK_S0_C 0x1784
#define GAIN_TX_GAPK_S0_C_M 0x1E00
#define BW_TXS1_C 0x1784
#define BW_TXS1_C_M 0x70000
#define DAC_0P5DB_S1_C 0x1784
#define DAC_0P5DB_S1_C_M 0x80000
#define GAIN_TX_S1_C 0x1784
#define GAIN_TX_S1_C_M 0x1F00000
#define GAIN_TX_GAPK_S1_C 0x1784
#define GAIN_TX_GAPK_S1_C_M 0x1E000000
#define LO_SEL_C 0x1784
#define LO_SEL_C_M 0xC0000000
#define INTF_TXINFO_PPDU_TYPE_3_0__C 0x1800
#define INTF_TXINFO_PPDU_TYPE_3_0__C_M 0xF
#define INTF_TXINFO_CH20_WITH_DATA_7_0__C 0x1800
#define INTF_TXINFO_CH20_WITH_DATA_7_0__C_M 0xFF0
#define INTF_TXINFO_PATH_EN_3_0__C 0x1800
#define INTF_TXINFO_PATH_EN_3_0__C_M 0xF000
#define INTF_TXINFO_PATH_MAP_A_1_0__C 0x1800
#define INTF_TXINFO_PATH_MAP_A_1_0__C_M 0x30000
#define INTF_TXINFO_PATH_MAP_B_1_0__C 0x1800
#define INTF_TXINFO_PATH_MAP_B_1_0__C_M 0xC0000
#define INTF_TXINFO_PATH_MAP_C_1_0__C 0x1800
#define INTF_TXINFO_PATH_MAP_C_1_0__C_M 0x300000
#define INTF_TXINFO_PATH_MAP_D_1_0__C 0x1800
#define INTF_TXINFO_PATH_MAP_D_1_0__C_M 0xC00000
#define INTF_TXINFO_TXCMD_TXTP_5_0__C 0x1800
#define INTF_TXINFO_TXCMD_TXTP_5_0__C_M 0x3F000000
#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_1_0__C 0x1800
#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_1_0__C_M 0xC0000000
#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_3_2__C 0x1804
#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_3_2__C_M 0x3
#define INTF_TXINFO_CFIR_BY_RATE_OFF_0__C 0x1804
#define INTF_TXINFO_CFIR_BY_RATE_OFF_0__C_M 0x4
#define INTF_TXINFO_DPD_BY_RATE_OFF_0__C 0x1804
#define INTF_TXINFO_DPD_BY_RATE_OFF_0__C_M 0x8
#define INTF_TXINFO_TXSC_3_0__C 0x1804
#define INTF_TXINFO_TXSC_3_0__C_M 0xF0
#define INTF_TXINFO_TX_SWING_3_0__C 0x1804
#define INTF_TXINFO_TX_SWING_3_0__C_M 0xF00
#define INTF_TXINFO_RATE_BIAS_1_0__C 0x1804
#define INTF_TXINFO_RATE_BIAS_1_0__C_M 0x3000
#define INTF_TXINFO_DBW_IDX_1_0__C 0x1804
#define INTF_TXINFO_DBW_IDX_1_0__C_M 0x30000
#define INTF_TXINFO_TX_PW_DBM_8_0__C 0x1804
#define INTF_TXINFO_TX_PW_DBM_8_0__C_M 0x7FC0000
#define INTF_TXINFO_CFO_COMP_2_0__C 0x1804
#define INTF_TXINFO_CFO_COMP_2_0__C_M 0x38000000
#define INTF_TXINFO_ANTIDX_ANT_SEL_A_0__C 0x1808
#define INTF_TXINFO_ANTIDX_ANT_SEL_A_0__C_M 0x1
#define INTF_TXINFO_ANTIDX_ANT_SEL_B_0__C 0x1808
#define INTF_TXINFO_ANTIDX_ANT_SEL_B_0__C_M 0x2
#define INTF_TXINFO_ANTIDX_ANT_SEL_C_0__C 0x1808
#define INTF_TXINFO_ANTIDX_ANT_SEL_C_0__C_M 0x4
#define INTF_TXINFO_ANTIDX_ANT_SEL_D_0__C 0x1808
#define INTF_TXINFO_ANTIDX_ANT_SEL_D_0__C_M 0x8
#define INTF_TXINFO_N_USR_7_0__C 0x1808
#define INTF_TXINFO_N_USR_7_0__C_M 0xFF0
#define INTF_TXINFO_CCA_PW_TH_7_0__C 0x1808
#define INTF_TXINFO_CCA_PW_TH_7_0__C_M 0xFF000
#define INTF_TXINFO_CCA_PW_TH_EN_0__C 0x1808
#define INTF_TXINFO_CCA_PW_TH_EN_0__C_M 0x100000
#define INTF_TXINFO_RF_GAIN_IDX_9_0__C 0x1808
#define INTF_TXINFO_RF_GAIN_IDX_9_0__C_M 0x7FE00000
#define INTF_TXINFO_RF_FIXED_GAIN_EN_0__C 0x1808
#define INTF_TXINFO_RF_FIXED_GAIN_EN_0__C_M 0x80000000
#define INTF_TXINFO_UL_CQI_RPT_TRI_0__C 0x180C
#define INTF_TXINFO_UL_CQI_RPT_TRI_0__C_M 0x1
#define INTF_TXCOMCT_STBC_EN_0__C 0x1810
#define INTF_TXCOMCT_STBC_EN_0__C_M 0x1
#define INTF_TXCOMCT_DOPPLER_EN_0__C 0x1810
#define INTF_TXCOMCT_DOPPLER_EN_0__C_M 0x4
#define INTF_TXCOMCT_MIDAMBLE_MODE_0__C 0x1810
#define INTF_TXCOMCT_MIDAMBLE_MODE_0__C_M 0x8
#define INTF_TXCOMCT_GI_TYPE_1_0__C 0x1810
#define INTF_TXCOMCT_GI_TYPE_1_0__C_M 0x30
#define INTF_TXCOMCT_LTF_TYPE_1_0__C 0x1810
#define INTF_TXCOMCT_LTF_TYPE_1_0__C_M 0xC0
#define INTF_TXCOMCT_N_LTF_2_0__C 0x1810
#define INTF_TXCOMCT_N_LTF_2_0__C_M 0x700
#define INTF_TXCOMCT_FB_MUMIMO_EN_0__C 0x1810
#define INTF_TXCOMCT_FB_MUMIMO_EN_0__C_M 0x800
#define INTF_TXCOMCT_MUMIMO_LTF_MODE_EN_0__C 0x1814
#define INTF_TXCOMCT_MUMIMO_LTF_MODE_EN_0__C_M 0x8
#define INTF_TXCOMCT_NDP_0__C 0x1814
#define INTF_TXCOMCT_NDP_0__C_M 0x10
#define INTF_TXCOMCT_FEEDBACK_STATUS_0__C 0x1814
#define INTF_TXCOMCT_FEEDBACK_STATUS_0__C_M 0x20
#define INTF_TXCOMCT_BEAM_CHANGE_EN_0__C 0x1814
#define INTF_TXCOMCT_BEAM_CHANGE_EN_0__C_M 0x40
#define INTF_TXCOMCT_HE_SIGB_MCS_2_0__C 0x1814
#define INTF_TXCOMCT_HE_SIGB_MCS_2_0__C_M 0x380
#define INTF_TXCOMCT_HE_SIGB_DCM_EN_0__C 0x1814
#define INTF_TXCOMCT_HE_SIGB_DCM_EN_0__C_M 0x400
#define INTF_TXUSRCT0_U_ID_7_0__C 0x1818
#define INTF_TXUSRCT0_U_ID_7_0__C_M 0xFF
#define INTF_TXUSRCT0_RU_ALLOC_7_0__C 0x1818
#define INTF_TXUSRCT0_RU_ALLOC_7_0__C_M 0xFF00
#define INTF_TXUSRCT0_N_STS_RU_TOT_2_0__C 0x1818
#define INTF_TXUSRCT0_N_STS_RU_TOT_2_0__C_M 0x70000
#define INTF_TXUSRCT0_STRT_STS_2_0__C 0x1818
#define INTF_TXUSRCT0_STRT_STS_2_0__C_M 0xE00000
#define INTF_TXUSRCT0_N_STS_2_0__C 0x1818
#define INTF_TXUSRCT0_N_STS_2_0__C_M 0x7000000
#define INTF_TXUSRCT0_FEC_TYPE_0__C 0x1818
#define INTF_TXUSRCT0_FEC_TYPE_0__C_M 0x8000000
#define INTF_TXUSRCT0_MCS_3_0__C 0x1818
#define INTF_TXUSRCT0_MCS_3_0__C_M 0xF0000000
#define INTF_TXUSRCT0_MCS_5_4__C 0x181C
#define INTF_TXUSRCT0_MCS_5_4__C_M 0x3
#define INTF_TXUSRCT0_DCM_EN_0__C 0x181C
#define INTF_TXUSRCT0_DCM_EN_0__C_M 0x4
#define INTF_TXUSRCT0_CSI_BUF_ID_10_0__C 0x181C
#define INTF_TXUSRCT0_CSI_BUF_ID_10_0__C_M 0x3FF8
#define INTF_TXUSRCT0_TXBF_EN_0__C 0x181C
#define INTF_TXUSRCT0_TXBF_EN_0__C_M 0x4000
#define INTF_TXUSRCT0_PW_BOOST_FCTR_DB_4_0__C 0x181C
#define INTF_TXUSRCT0_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
#define INTF_TXUSRCT1_U_ID_7_0__C 0x1820
#define INTF_TXUSRCT1_U_ID_7_0__C_M 0xFF
#define INTF_TXUSRCT1_RU_ALLOC_7_0__C 0x1820
#define INTF_TXUSRCT1_RU_ALLOC_7_0__C_M 0xFF00
#define INTF_TXUSRCT1_N_STS_RU_TOT_2_0__C 0x1820
#define INTF_TXUSRCT1_N_STS_RU_TOT_2_0__C_M 0x70000
#define INTF_TXUSRCT1_STRT_STS_2_0__C 0x1820
#define INTF_TXUSRCT1_STRT_STS_2_0__C_M 0xE00000
#define INTF_TXUSRCT1_N_STS_2_0__C 0x1820
#define INTF_TXUSRCT1_N_STS_2_0__C_M 0x7000000
#define INTF_TXUSRCT1_FEC_TYPE_0__C 0x1820
#define INTF_TXUSRCT1_FEC_TYPE_0__C_M 0x8000000
#define INTF_TXUSRCT1_MCS_3_0__C 0x1820
#define INTF_TXUSRCT1_MCS_3_0__C_M 0xF0000000
#define INTF_TXUSRCT1_MCS_5_4__C 0x1824
#define INTF_TXUSRCT1_MCS_5_4__C_M 0x3
#define INTF_TXUSRCT1_DCM_EN_0__C 0x1824
#define INTF_TXUSRCT1_DCM_EN_0__C_M 0x4
#define INTF_TXUSRCT1_CSI_BUF_ID_10_0__C 0x1824
#define INTF_TXUSRCT1_CSI_BUF_ID_10_0__C_M 0x3FF8
#define INTF_TXUSRCT1_TXBF_EN_0__C 0x1824
#define INTF_TXUSRCT1_TXBF_EN_0__C_M 0x4000
#define INTF_TXUSRCT1_PW_BOOST_FCTR_DB_4_0__C 0x1824
#define INTF_TXUSRCT1_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
#define INTF_TXUSRCT2_U_ID_7_0__C 0x1828
#define INTF_TXUSRCT2_U_ID_7_0__C_M 0xFF
#define INTF_TXUSRCT2_RU_ALLOC_7_0__C 0x1828
#define INTF_TXUSRCT2_RU_ALLOC_7_0__C_M 0xFF00
#define INTF_TXUSRCT2_N_STS_RU_TOT_2_0__C 0x1828
#define INTF_TXUSRCT2_N_STS_RU_TOT_2_0__C_M 0x70000
#define INTF_TXUSRCT2_STRT_STS_2_0__C 0x1828
#define INTF_TXUSRCT2_STRT_STS_2_0__C_M 0xE00000
#define INTF_TXUSRCT2_N_STS_2_0__C 0x1828
#define INTF_TXUSRCT2_N_STS_2_0__C_M 0x7000000
#define INTF_TXUSRCT2_FEC_TYPE_0__C 0x1828
#define INTF_TXUSRCT2_FEC_TYPE_0__C_M 0x8000000
#define INTF_TXUSRCT2_MCS_3_0__C 0x1828
#define INTF_TXUSRCT2_MCS_3_0__C_M 0xF0000000
#define INTF_TXUSRCT2_MCS_5_4__C 0x182C
#define INTF_TXUSRCT2_MCS_5_4__C_M 0x3
#define INTF_TXUSRCT2_DCM_EN_0__C 0x182C
#define INTF_TXUSRCT2_DCM_EN_0__C_M 0x4
#define INTF_TXUSRCT2_CSI_BUF_ID_10_0__C 0x182C
#define INTF_TXUSRCT2_CSI_BUF_ID_10_0__C_M 0x3FF8
#define INTF_TXUSRCT2_TXBF_EN_0__C 0x182C
#define INTF_TXUSRCT2_TXBF_EN_0__C_M 0x4000
#define INTF_TXUSRCT2_PW_BOOST_FCTR_DB_4_0__C 0x182C
#define INTF_TXUSRCT2_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
#define INTF_TXUSRCT3_U_ID_7_0__C 0x1830
#define INTF_TXUSRCT3_U_ID_7_0__C_M 0xFF
#define INTF_TXUSRCT3_RU_ALLOC_7_0__C 0x1830
#define INTF_TXUSRCT3_RU_ALLOC_7_0__C_M 0xFF00
#define INTF_TXUSRCT3_N_STS_RU_TOT_2_0__C 0x1830
#define INTF_TXUSRCT3_N_STS_RU_TOT_2_0__C_M 0x70000
#define INTF_TXUSRCT3_STRT_STS_2_0__C 0x1830
#define INTF_TXUSRCT3_STRT_STS_2_0__C_M 0xE00000
#define INTF_TXUSRCT3_N_STS_2_0__C 0x1830
#define INTF_TXUSRCT3_N_STS_2_0__C_M 0x7000000
#define INTF_TXUSRCT3_FEC_TYPE_0__C 0x1830
#define INTF_TXUSRCT3_FEC_TYPE_0__C_M 0x8000000
#define INTF_TXUSRCT3_MCS_3_0__C 0x1830
#define INTF_TXUSRCT3_MCS_3_0__C_M 0xF0000000
#define INTF_TXUSRCT3_MCS_5_4__C 0x1834
#define INTF_TXUSRCT3_MCS_5_4__C_M 0x3
#define INTF_TXUSRCT3_DCM_EN_0__C 0x1834
#define INTF_TXUSRCT3_DCM_EN_0__C_M 0x4
#define INTF_TXUSRCT3_CSI_BUF_ID_10_0__C 0x1834
#define INTF_TXUSRCT3_CSI_BUF_ID_10_0__C_M 0x3FF8
#define INTF_TXUSRCT3_TXBF_EN_0__C 0x1834
#define INTF_TXUSRCT3_TXBF_EN_0__C_M 0x4000
#define INTF_TXUSRCT3_PW_BOOST_FCTR_DB_4_0__C 0x1834
#define INTF_TXUSRCT3_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
#define INTF_TXTIMCT_N_SYM_10_0__C 0x1838
#define INTF_TXTIMCT_N_SYM_10_0__C_M 0x7FF
#define INTF_TXTIMCT_N_SYM_HESIGB_5_0__C 0x1838
#define INTF_TXTIMCT_N_SYM_HESIGB_5_0__C_M 0x3F0000
#define INTF_TXTIMCT_LDPC_EXTR_0__C 0x1838
#define INTF_TXTIMCT_LDPC_EXTR_0__C_M 0x1000000
#define INTF_TXTIMCT_PKT_EXT_IDX_2_0__C 0x1838
#define INTF_TXTIMCT_PKT_EXT_IDX_2_0__C_M 0xE000000
#define INTF_TXTIMCT_PRE_FEC_FCTR_1_0__C 0x1838
#define INTF_TXTIMCT_PRE_FEC_FCTR_1_0__C_M 0x30000000
#define INTF_TX_LSIG_LATCH_31_0__C 0x1840
#define INTF_TX_LSIG_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_LSIG_LATCH_63_32__C 0x1844
#define INTF_TX_LSIG_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_SIGA_LATCH_31_0__C 0x1848
#define INTF_TX_SIGA_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_SIGA_LATCH_63_32__C 0x184C
#define INTF_TX_SIGA_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_VHT_SIGB0_LATCH_31_0__C 0x1850
#define INTF_TX_VHT_SIGB0_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_VHT_SIGB0_LATCH_63_32__C 0x1854
#define INTF_TX_VHT_SIGB0_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_VHT_SIGB1_LATCH_31_0__C 0x1858
#define INTF_TX_VHT_SIGB1_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_VHT_SIGB1_LATCH_63_32__C 0x185C
#define INTF_TX_VHT_SIGB1_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_0_LATCH_31_0__C 0x1860
#define INTF_TX_HE_SIGB_CH0_0_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_0_LATCH_63_32__C 0x1864
#define INTF_TX_HE_SIGB_CH0_0_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_1_LATCH_31_0__C 0x1868
#define INTF_TX_HE_SIGB_CH0_1_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_1_LATCH_63_32__C 0x186C
#define INTF_TX_HE_SIGB_CH0_1_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_2_LATCH_31_0__C 0x1870
#define INTF_TX_HE_SIGB_CH0_2_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_2_LATCH_63_32__C 0x1874
#define INTF_TX_HE_SIGB_CH0_2_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_3_LATCH_31_0__C 0x1878
#define INTF_TX_HE_SIGB_CH0_3_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_3_LATCH_63_32__C 0x187C
#define INTF_TX_HE_SIGB_CH0_3_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_4_LATCH_31_0__C 0x1880
#define INTF_TX_HE_SIGB_CH0_4_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_4_LATCH_63_32__C 0x1884
#define INTF_TX_HE_SIGB_CH0_4_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_5_LATCH_31_0__C 0x1888
#define INTF_TX_HE_SIGB_CH0_5_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_5_LATCH_63_32__C 0x188C
#define INTF_TX_HE_SIGB_CH0_5_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_6_LATCH_31_0__C 0x1890
#define INTF_TX_HE_SIGB_CH0_6_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_6_LATCH_63_32__C 0x1894
#define INTF_TX_HE_SIGB_CH0_6_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_7_LATCH_31_0__C 0x1898
#define INTF_TX_HE_SIGB_CH0_7_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH0_7_LATCH_63_32__C 0x189C
#define INTF_TX_HE_SIGB_CH0_7_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_0_LATCH_31_0__C 0x18A0
#define INTF_TX_HE_SIGB_CH1_0_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_0_LATCH_63_32__C 0x18A4
#define INTF_TX_HE_SIGB_CH1_0_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_1_LATCH_31_0__C 0x18A8
#define INTF_TX_HE_SIGB_CH1_1_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_1_LATCH_63_32__C 0x18AC
#define INTF_TX_HE_SIGB_CH1_1_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_2_LATCH_31_0__C 0x18B0
#define INTF_TX_HE_SIGB_CH1_2_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_2_LATCH_63_32__C 0x18B4
#define INTF_TX_HE_SIGB_CH1_2_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_3_LATCH_31_0__C 0x18B8
#define INTF_TX_HE_SIGB_CH1_3_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_3_LATCH_63_32__C 0x18BC
#define INTF_TX_HE_SIGB_CH1_3_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_4_LATCH_31_0__C 0x18C0
#define INTF_TX_HE_SIGB_CH1_4_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_4_LATCH_63_32__C 0x18C4
#define INTF_TX_HE_SIGB_CH1_4_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_5_LATCH_31_0__C 0x18C8
#define INTF_TX_HE_SIGB_CH1_5_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_5_LATCH_63_32__C 0x18CC
#define INTF_TX_HE_SIGB_CH1_5_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_6_LATCH_31_0__C 0x18D0
#define INTF_TX_HE_SIGB_CH1_6_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_6_LATCH_63_32__C 0x18D4
#define INTF_TX_HE_SIGB_CH1_6_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_7_LATCH_31_0__C 0x18D8
#define INTF_TX_HE_SIGB_CH1_7_LATCH_31_0__C_M 0xFFFFFFFF
#define INTF_TX_HE_SIGB_CH1_7_LATCH_63_32__C 0x18DC
#define INTF_TX_HE_SIGB_CH1_7_LATCH_63_32__C_M 0xFFFFFFFF
#define INTF_MAC_PHY_TXEN_C 0x18E0
#define INTF_MAC_PHY_TXEN_C_M 0x1
#define INTF_MAC_PHY_TXON_C 0x18E0
#define INTF_MAC_PHY_TXON_C_M 0x10
#define CNT_CCA_SPOOFING_C 0x1A00
#define CNT_CCA_SPOOFING_C_M 0xFFFF
#define CNT_LSIG_BRK_S_TH_C 0x1A00
#define CNT_LSIG_BRK_S_TH_C_M 0xFFFF0000
#define CNT_LSIG_BRK_L_TH_C 0x1A04
#define CNT_LSIG_BRK_L_TH_C_M 0xFFFF
#define CNT_HTSIG_CRC8_ERR_S_TH_C 0x1A04
#define CNT_HTSIG_CRC8_ERR_S_TH_C_M 0xFFFF0000
#define CNT_HTSIG_CRC8_ERR_L_TH_C 0x1A08
#define CNT_HTSIG_CRC8_ERR_L_TH_C_M 0xFFFF
#define CNT_BRK_C 0x1A08
#define CNT_BRK_C_M 0xFFFF0000
#define CNT_BRK_SEL_C 0x1A0C
#define CNT_BRK_SEL_C_M 0xFFFF
#define CNT_RXL_ERR_PARITY_C 0x1A0C
#define CNT_RXL_ERR_PARITY_C_M 0xFFFF0000
#define CNT_RXL_ERR_RATE_C 0x1A10
#define CNT_RXL_ERR_RATE_C_M 0xFFFF
#define CNT_HT_ERR_CRC8_C 0x1A10
#define CNT_HT_ERR_CRC8_C_M 0xFFFF0000
#define CNT_VHT_ERR_SIGA_CRC8_C 0x1A14
#define CNT_VHT_ERR_SIGA_CRC8_C_M 0xFFFF
#define CNT_HT_NOT_SUPPORT_MCS_C 0x1A18
#define CNT_HT_NOT_SUPPORT_MCS_C_M 0xFFFF
#define CNT_VHT_NOT_SUPPORT_MCS_C 0x1A18
#define CNT_VHT_NOT_SUPPORT_MCS_C_M 0xFFFF0000
#define CNT_ERR_DURING_BT_TX_C 0x1A1C
#define CNT_ERR_DURING_BT_TX_C_M 0xFFFF
#define CNT_ERR_DURING_BT_RX_C 0x1A1C
#define CNT_ERR_DURING_BT_RX_C_M 0xFFFF0000
#define CNT_EDGE_MURX_NSTS0_C 0x1A20
#define CNT_EDGE_MURX_NSTS0_C_M 0xFFFF
#define CNT_SEARCH_FAIL_C 0x1A20
#define CNT_SEARCH_FAIL_C_M 0xFFFF0000
#define CNT_OFDM_CCA_C 0x1A24
#define CNT_OFDM_CCA_C_M 0xFFFF
#define CNT_OFDM_CCA_S20_C 0x1A24
#define CNT_OFDM_CCA_S20_C_M 0xFFFF0000
#define CNT_OFDM_CCA_S40_C 0x1A28
#define CNT_OFDM_CCA_S40_C_M 0xFFFF
#define CNT_OFDM_CCA_S80_C 0x1A28
#define CNT_OFDM_CCA_S80_C_M 0xFFFF0000
#define CNT_INVLD_CCA1_CCK_PKT_C 0x1A2C
#define CNT_INVLD_CCA1_CCK_PKT_C_M 0xFFFF
#define CNT_INVLD_CCA1_OFDM_PKT_C 0x1A2C
#define CNT_INVLD_CCA1_OFDM_PKT_C_M 0xFFFF0000
#define CNT_INVLD_PKT_C 0x1A30
#define CNT_INVLD_PKT_C_M 0xFFFF
#define CNT_INVLD_CCA0_PKT_C 0x1A30
#define CNT_INVLD_CCA0_PKT_C_M 0xFFFF0000
#define CNT_OFDM_CCA_MAC_C 0x1A34
#define CNT_OFDM_CCA_MAC_C_M 0xFFFF
#define CNT_CCK_CCA_MAC_C 0x1A34
#define CNT_CCK_CCA_MAC_C_M 0xFFFF0000
#define CNT_MAC_PIN_C 0x1A38
#define CNT_MAC_PIN_C_M 0xFFFF
#define CNT_GNT_CONFLICT_TX_C 0x1A38
#define CNT_GNT_CONFLICT_TX_C_M 0xFFFF0000
#define CNT_GNT_CONFLICT_RX_C 0x1A3C
#define CNT_GNT_CONFLICT_RX_C_M 0xFFFF
#define CNT_FTM_LBK_C 0x1A3C
#define CNT_FTM_LBK_C_M 0xFFFF0000
#define CNT_OFDMTXON_C 0x1A40
#define CNT_OFDMTXON_C_M 0xFFFF
#define CNT_OFDMTXEN_C 0x1A40
#define CNT_OFDMTXEN_C_M 0xFFFF0000
#define CNT_DROP_TRIG_C 0x1A44
#define CNT_DROP_TRIG_C_M 0xFFFF
#define CNT_POP_TRIG_C 0x1A44
#define CNT_POP_TRIG_C_M 0xFFFF0000
#define CNT_TX_CONFLICT_C 0x1A48
#define CNT_TX_CONFLICT_C_M 0xFFFF
#define CNT_WMAC_RSTB_C 0x1A48
#define CNT_WMAC_RSTB_C_M 0xFFFF0000
#define CNT_EN_TB_PPDU_FIX_GAIN_C 0x1A4C
#define CNT_EN_TB_PPDU_FIX_GAIN_C_M 0xFFFF
#define CNT_EN_TB_CCA_PW_TH_C 0x1A4C
#define CNT_EN_TB_CCA_PW_TH_C_M 0xFFFF0000
#define CNT_TB_FAIL_FREERUN_C 0x1A50
#define CNT_TB_FAIL_FREERUN_C_M 0xFFFF
#define CNT_TB_PD_HIT_SEG0_C 0x1A50
#define CNT_TB_PD_HIT_SEG0_C_M 0xFFFF0000
#define CNT_TB_SBDRDY_SEG0_C 0x1A54
#define CNT_TB_SBDRDY_SEG0_C_M 0xFFFF
#define CNT_FAIL_FORCE_CCA_PW_TB_C 0x1A54
#define CNT_FAIL_FORCE_CCA_PW_TB_C_M 0xFF0000
#define CNT_FAIL_FORCE_GAIN_TB_C 0x1A54
#define CNT_FAIL_FORCE_GAIN_TB_C_M 0xFF000000
#define CNT_HE_CRC_OK_C 0x1A58
#define CNT_HE_CRC_OK_C_M 0xFFFF
#define CNT_HE_CRC_ERR_C 0x1A58
#define CNT_HE_CRC_ERR_C_M 0xFFFF0000
#define CNT_VHT_CRC_OK_C 0x1A5C
#define CNT_VHT_CRC_OK_C_M 0xFFFF
#define CNT_VHT_CRC_ERR_C 0x1A5C
#define CNT_VHT_CRC_ERR_C_M 0xFFFF0000
#define CNT_HT_CRC_OK_C 0x1A60
#define CNT_HT_CRC_OK_C_M 0xFFFF
#define CNT_HT_CRC_ERR_C 0x1A60
#define CNT_HT_CRC_ERR_C_M 0xFFFF0000
#define CNT_L_CRC_OK_C 0x1A64
#define CNT_L_CRC_OK_C_M 0xFFFF
#define CNT_L_CRC_ERR_C 0x1A64
#define CNT_L_CRC_ERR_C_M 0xFFFF0000
#define CNT_HE_CRC_OK2_C 0x1A68
#define CNT_HE_CRC_OK2_C_M 0xFFFF
#define CNT_HE_CRC_ERR2_C 0x1A68
#define CNT_HE_CRC_ERR2_C_M 0xFFFF0000
#define CNT_VHT_CRC_OK2_C 0x1A6C
#define CNT_VHT_CRC_OK2_C_M 0xFFFF
#define CNT_VHT_CRC_ERR2_C 0x1A6C
#define CNT_VHT_CRC_ERR2_C_M 0xFFFF0000
#define CNT_HT_CRC_OK2_C 0x1A70
#define CNT_HT_CRC_OK2_C_M 0xFFFF
#define CNT_HT_CRC_ERR2_C 0x1A70
#define CNT_HT_CRC_ERR2_C_M 0xFFFF0000
#define CNT_L_CRC_OK2_C 0x1A74
#define CNT_L_CRC_OK2_C_M 0xFFFF
#define CNT_L_CRC_ERR2_C 0x1A74
#define CNT_L_CRC_ERR2_C_M 0xFFFF0000
#define CNT_L_CRC_OK3_C 0x1A78
#define CNT_L_CRC_OK3_C_M 0xFFFF
#define CNT_L_CRC_ERR3_C 0x1A78
#define CNT_L_CRC_ERR3_C_M 0xFFFF0000
#define CNT_AMPDU_RXON_C 0x1A7C
#define CNT_AMPDU_RXON_C_M 0xFFFF
#define CNT_AMPDU_MISS_C 0x1A7C
#define CNT_AMPDU_MISS_C_M 0xFFFF0000
#define CNT_AMPDU_RX_CRC32_OK_C 0x1A80
#define CNT_AMPDU_RX_CRC32_OK_C_M 0xFFFF
#define CNT_AMPDU_RX_CRC32_ERR_C 0x1A80
#define CNT_AMPDU_RX_CRC32_ERR_C_M 0xFFFF0000
#define CNT_PKT_FMT_MATCH_C 0x1A84
#define CNT_PKT_FMT_MATCH_C_M 0xFFFF
#define CNT_LA_FRAME_CTRL_MATCH_C 0x1A84
#define CNT_LA_FRAME_CTRL_MATCH_C_M 0xFFFF0000
#define NHM_CNT0_C 0x1A88
#define NHM_CNT0_C_M 0xFFFF
#define NHM_CNT1_C 0x1A88
#define NHM_CNT1_C_M 0xFFFF0000
#define NHM_CNT2_C 0x1A8C
#define NHM_CNT2_C_M 0xFFFF
#define NHM_CNT3_C 0x1A8C
#define NHM_CNT3_C_M 0xFFFF0000
#define NHM_CNT4_C 0x1A90
#define NHM_CNT4_C_M 0xFFFF
#define NHM_CNT5_C 0x1A90
#define NHM_CNT5_C_M 0xFFFF0000
#define NHM_CNT6_C 0x1A94
#define NHM_CNT6_C_M 0xFFFF
#define NHM_CNT7_C 0x1A94
#define NHM_CNT7_C_M 0xFFFF0000
#define NHM_CNT8_C 0x1A98
#define NHM_CNT8_C_M 0xFFFF
#define NHM_CNT9_C 0x1A98
#define NHM_CNT9_C_M 0xFFFF0000
#define NHM_CNT10_C 0x1A9C
#define NHM_CNT10_C_M 0xFFFF
#define NHM_CNT11_C 0x1A9C
#define NHM_CNT11_C_M 0xFFFF0000
#define NHM_CCA_CNT_C 0x1AA0
#define NHM_CCA_CNT_C_M 0xFFFF
#define NHM_TXON_CNT_C 0x1AA0
#define NHM_TXON_CNT_C_M 0xFFFF0000
#define NHM_IDLE_CNT_C 0x1AA4
#define NHM_IDLE_CNT_C_M 0xFFFF
#define NHM_RDY_C 0x1AA4
#define NHM_RDY_C_M 0x10000
#define RO_FAHM_NUM0_C 0x1AA8
#define RO_FAHM_NUM0_C_M 0xFFFF
#define RO_FAHM_NUM1_C 0x1AA8
#define RO_FAHM_NUM1_C_M 0xFFFF0000
#define RO_FAHM_NUM2_C 0x1AAC
#define RO_FAHM_NUM2_C_M 0xFFFF
#define RO_FAHM_NUM3_C 0x1AAC
#define RO_FAHM_NUM3_C_M 0xFFFF0000
#define RO_FAHM_NUM4_C 0x1AB0
#define RO_FAHM_NUM4_C_M 0xFFFF
#define RO_FAHM_NUM5_C 0x1AB0
#define RO_FAHM_NUM5_C_M 0xFFFF0000
#define RO_FAHM_NUM6_C 0x1AB4
#define RO_FAHM_NUM6_C_M 0xFFFF
#define RO_FAHM_NUM7_C 0x1AB4
#define RO_FAHM_NUM7_C_M 0xFFFF0000
#define RO_FAHM_NUM8_C 0x1AB8
#define RO_FAHM_NUM8_C_M 0xFFFF
#define RO_FAHM_NUM9_C 0x1AB8
#define RO_FAHM_NUM9_C_M 0xFFFF0000
#define RO_FAHM_NUM10_C 0x1ABC
#define RO_FAHM_NUM10_C_M 0xFFFF
#define RO_FAHM_NUM11_C 0x1ABC
#define RO_FAHM_NUM11_C_M 0xFFFF0000
#define RO_FAHM_DEN_C 0x1AC0
#define RO_FAHM_DEN_C_M 0xFFFF
#define RO_FAHM_RDY_C 0x1AC0
#define RO_FAHM_RDY_C_M 0x10000
#define RO_CLM_RESULT_C 0x1AC4
#define RO_CLM_RESULT_C_M 0xFFFF
#define RO_CLM_RDY_C 0x1AC4
#define RO_CLM_RDY_C_M 0x10000
#define RO_CLM_EDCCA_RESULT_C 0x1AC8
#define RO_CLM_EDCCA_RESULT_C_M 0xFFFF
#define RO_CLM_EDCCA_RDY_C 0x1AC8
#define RO_CLM_EDCCA_RDY_C_M 0x10000
#define IFSCNT_CNT_TX_C 0x1ACC
#define IFSCNT_CNT_TX_C_M 0xFFFF
#define IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C 0x1ACC
#define IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C_M 0xFFFF0000
#define IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C 0x1AD0
#define IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C_M 0xFFFF
#define IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C 0x1AD0
#define IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C_M 0xFFFF0000
#define IFSCNT_CNT_CCKFA_C 0x1AD4
#define IFSCNT_CNT_CCKFA_C_M 0xFFFF
#define IFSCNT_CNT_OFDMFA_C 0x1AD4
#define IFSCNT_CNT_OFDMFA_C_M 0xFFFF0000
#define IFS_T1_AVG_C 0x1ADC
#define IFS_T1_AVG_C_M 0xFFFF
#define IFS_T2_AVG_C 0x1ADC
#define IFS_T2_AVG_C_M 0xFFFF0000
#define IFS_T3_AVG_C 0x1AE0
#define IFS_T3_AVG_C_M 0xFFFF
#define IFS_T4_AVG_C 0x1AE0
#define IFS_T4_AVG_C_M 0xFFFF0000
#define IFS_T1_CLM_C 0x1AE4
#define IFS_T1_CLM_C_M 0xFFFF
#define IFS_T2_CLM_C 0x1AE4
#define IFS_T2_CLM_C_M 0xFFFF0000
#define IFS_T3_CLM_C 0x1AE8
#define IFS_T3_CLM_C_M 0xFFFF
#define IFS_T4_CLM_C 0x1AE8
#define IFS_T4_CLM_C_M 0xFFFF0000
#define IFS_TOTAL_C 0x1AEC
#define IFS_TOTAL_C_M 0xFFFF
#define IFSCNT_DONE_C 0x1AEC
#define IFSCNT_DONE_C_M 0x10000
#define IFS_COUNTING_C 0x1AEC
#define IFS_COUNTING_C_M 0x20000
#define STS_KEEPER_DATA_C 0x1AF0
#define STS_KEEPER_DATA_C_M 0xFFFFFFFF
#define PERIOD_S1_C 0x1AF4
#define PERIOD_S1_C_M 0xFFFF
#define PERIOD_S2_C 0x1AF4
#define PERIOD_S2_C_M 0xFFFF0000
#define PERIOD_S3_C 0x1AF8
#define PERIOD_S3_C_M 0xFFFF
#define PERIOD_S4_C 0x1AF8
#define PERIOD_S4_C_M 0xFFFF0000
#define OFDM_CRC32_OK_OR_C 0x1AFC
#define OFDM_CRC32_OK_OR_C_M 0xFFFF
#define CNT_NO_DATA_RECEIVED_C 0x1AFC
#define CNT_NO_DATA_RECEIVED_C_M 0xFFFF0000
#define CNT_HESU_ERR_SIG_A_CRC4_C 0x1B00
#define CNT_HESU_ERR_SIG_A_CRC4_C_M 0xFFFF
#define CNT_HEERSU_ERR_SIG_A_CRC4_C 0x1B00
#define CNT_HEERSU_ERR_SIG_A_CRC4_C_M 0xFFFF0000
#define CNT_HEMU_ERR_SIG_A_CRC4_C 0x1B04
#define CNT_HEMU_ERR_SIG_A_CRC4_C_M 0xFFFF
#define CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C 0x1B04
#define CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C_M 0xFFFF0000
#define CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C 0x1B08
#define CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C_M 0xFFFF
#define CNT_HE_U0_ERR_BCC_MCS_C 0x1B08
#define CNT_HE_U0_ERR_BCC_MCS_C_M 0xFFFF0000
#define CNT_HE_U0_ERR_MCS_C 0x1B0C
#define CNT_HE_U0_ERR_MCS_C_M 0xFFFF
#define CNT_HE_U0_ERR_DCM_MCS_C 0x1B0C
#define CNT_HE_U0_ERR_DCM_MCS_C_M 0xFFFF0000
#define MONITOR0_C 0x1B10
#define MONITOR0_C_M 0xFFFFFFFF
#define MONITOR1_C 0x1B14
#define MONITOR1_C_M 0xFFFFFFFF
#define CNT_TXINFO_TXTP_MATCH_C 0x1B18
#define CNT_TXINFO_TXTP_MATCH_C_M 0xFFFF
#define CNT_RX_PMAC_CRC32_OK_USER0_C 0x1B1C
#define CNT_RX_PMAC_CRC32_OK_USER0_C_M 0xFFFF
#define CNT_RX_PMAC_CRC32_OK_USER1_C 0x1B1C
#define CNT_RX_PMAC_CRC32_OK_USER1_C_M 0xFFFF0000
#define CNT_RX_PMAC_CRC32_OK_USER2_C 0x1B20
#define CNT_RX_PMAC_CRC32_OK_USER2_C_M 0xFFFF
#define CNT_RX_PMAC_CRC32_OK_USER3_C 0x1B20
#define CNT_RX_PMAC_CRC32_OK_USER3_C_M 0xFFFF0000
#define CNT_PFD_STAGE2B_MISS_C 0x1B24
#define CNT_PFD_STAGE2B_MISS_C_M 0xFF
#define CNT_PFD_STAGE2A_MISS_C 0x1B24
#define CNT_PFD_STAGE2A_MISS_C_M 0xFF00
#define CNT_PFD_STAGE0_MISS_C 0x1B24
#define CNT_PFD_STAGE0_MISS_C_M 0xFF0000
#define CNT_RX_IN_HT_DET_C 0x1B28
#define CNT_RX_IN_HT_DET_C_M 0xFFFF
#define CNT_RX_IN_NHT_DET_C 0x1B28
#define CNT_RX_IN_NHT_DET_C_M 0xFFFF0000
#define CNT_RX_IN_HE_DET_C 0x1B2C
#define CNT_RX_IN_HE_DET_C_M 0xFFFF
#define CNT_RX_IN_VHT_DET_C 0x1B2C
#define CNT_RX_IN_VHT_DET_C_M 0xFFFF0000
#define CNT_BRK_IN_HE_TB_C 0x1B30
#define CNT_BRK_IN_HE_TB_C_M 0xFFFF
#define CNT_NEG_GI2_OFST_OCCUR_C 0x1B34
#define CNT_NEG_GI2_OFST_OCCUR_C_M 0xFFFF
#define P0_L_TOT_PW_DBFS_RX0_C 0x1B38
#define P0_L_TOT_PW_DBFS_RX0_C_M 0xFFF
#define P0_L_TOT_PW_DBFS_RX1_C 0x1B38
#define P0_L_TOT_PW_DBFS_RX1_C_M 0xFFF000
#define P0_ANT_GAIN_DBM_RX_0_C 0x1B3C
#define P0_ANT_GAIN_DBM_RX_0_C_M 0x3FF
#define P0_ANT_GAIN_DBM_RX_1_C 0x1B3C
#define P0_ANT_GAIN_DBM_RX_1_C_M 0xFFC00
#define P0_PWINFO_RPL_DBM_TO_RPT_C 0x1B3C
#define P0_PWINFO_RPL_DBM_TO_RPT_C_M 0x1FF00000
#define P0_TOT_PW_DBFS_RX0_C 0x1B40
#define P0_TOT_PW_DBFS_RX0_C_M 0xFFF
#define P0_TOT_PW_DBFS_RX1_C 0x1B40
#define P0_TOT_PW_DBFS_RX1_C_M 0xFFF000
#define P0_RPL_COM_TERM_C 0x1B44
#define P0_RPL_COM_TERM_C_M 0x3FFF
#define P0_TB_RSSI_COM_TERM_C 0x1B44
#define P0_TB_RSSI_COM_TERM_C_M 0xFFFC000
#define P0_L_TOT_PW_DBM_RX0_C 0x1B48
#define P0_L_TOT_PW_DBM_RX0_C_M 0x1FFF
#define P0_L_TOT_PW_DBM_RX1_C 0x1B48
#define P0_L_TOT_PW_DBM_RX1_C_M 0x3FFE000
#define P0_TX_TD_CFO_C 0x1B4C
#define P0_TX_TD_CFO_C_M 0xFFF
#define IFS_T1_HIS_C 0x1B50
#define IFS_T1_HIS_C_M 0xFFFF
#define IFS_T2_HIS_C 0x1B50
#define IFS_T2_HIS_C_M 0xFFFF0000
#define IFS_T3_HIS_C 0x1B54
#define IFS_T3_HIS_C_M 0xFFFF
#define IFS_T4_HIS_C 0x1B54
#define IFS_T4_HIS_C_M 0xFFFF0000
#define PATH0_TSSI_DBG_PORT_C 0x1C00
#define PATH0_TSSI_DBG_PORT_C_M 0xFFFFFFFF
#define PATH0_DCK_AUTO_AVG_DC_C 0x1C04
#define PATH0_DCK_AUTO_AVG_DC_C_M 0xFFF000
#define PATH0_HE_LSTF_PW_OFST_C 0x1C04
#define PATH0_HE_LSTF_PW_OFST_C_M 0xFF000000
#define PATH0_DCK_AUTO_MAX_DC_C 0x1C08
#define PATH0_DCK_AUTO_MAX_DC_C_M 0xFFF
#define PATH0_DCK_AUTO_MIN_DC_C 0x1C08
#define PATH0_DCK_AUTO_MIN_DC_C_M 0xFFF000
#define PATH0_TMETER_F_C 0x1C08
#define PATH0_TMETER_F_C_M 0xFF000000
#define PATH0_TSSI_AVG_R_C 0x1C10
#define PATH0_TSSI_AVG_R_C_M 0xFFF
#define PATH0_TSSI_MAX_R_C 0x1C10
#define PATH0_TSSI_MAX_R_C_M 0xFFF000
#define PATH0_TSSI_F_NOW_C 0x1C10
#define PATH0_TSSI_F_NOW_C_M 0xFF000000
#define PATH0_TSSI_MID_R_C 0x1C14
#define PATH0_TSSI_MID_R_C_M 0xFFF
#define PATH0_TSSI_LAST_R_C 0x1C14
#define PATH0_TSSI_LAST_R_C_M 0xFFF000
#define PATH0_GAIN_TX_IPA_MX_C 0x1C14
#define PATH0_GAIN_TX_IPA_MX_C_M 0x7000000
#define PATH0_TSSI_VAL_AVG_C 0x1C18
#define PATH0_TSSI_VAL_AVG_C_M 0x3FF
#define PATH0_TSSI_VAL_AVG_OUT_VLD_C 0x1C18
#define PATH0_TSSI_VAL_AVG_OUT_VLD_C_M 0x10000
#define PATH0_ADC_RE_C 0x1C18
#define PATH0_ADC_RE_C_M 0xFFF00000
#define PATH0_TSSI_VAL_D00_C 0x1C1C
#define PATH0_TSSI_VAL_D00_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_0_C 0x1C1C
#define PATH0_TSSI_VAL_VLD_IDX_0_C_M 0x8000
#define PATH0_TSSI_VAL_D01_C 0x1C1C
#define PATH0_TSSI_VAL_D01_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_1_C 0x1C1C
#define PATH0_TSSI_VAL_VLD_IDX_1_C_M 0x80000000
#define PATH0_TSSI_VAL_D02_C 0x1C20
#define PATH0_TSSI_VAL_D02_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_2_C 0x1C20
#define PATH0_TSSI_VAL_VLD_IDX_2_C_M 0x8000
#define PATH0_TSSI_VAL_D03_C 0x1C20
#define PATH0_TSSI_VAL_D03_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_3_C 0x1C20
#define PATH0_TSSI_VAL_VLD_IDX_3_C_M 0x80000000
#define PATH0_TSSI_VAL_D04_C 0x1C24
#define PATH0_TSSI_VAL_D04_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_4_C 0x1C24
#define PATH0_TSSI_VAL_VLD_IDX_4_C_M 0x8000
#define PATH0_TSSI_VAL_D05_C 0x1C24
#define PATH0_TSSI_VAL_D05_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_5_C 0x1C24
#define PATH0_TSSI_VAL_VLD_IDX_5_C_M 0x80000000
#define PATH0_TSSI_VAL_D06_C 0x1C28
#define PATH0_TSSI_VAL_D06_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_6_C 0x1C28
#define PATH0_TSSI_VAL_VLD_IDX_6_C_M 0x8000
#define PATH0_TSSI_VAL_D07_C 0x1C28
#define PATH0_TSSI_VAL_D07_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_7_C 0x1C28
#define PATH0_TSSI_VAL_VLD_IDX_7_C_M 0x80000000
#define PATH0_TSSI_VAL_D08_C 0x1C2C
#define PATH0_TSSI_VAL_D08_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_8_C 0x1C2C
#define PATH0_TSSI_VAL_VLD_IDX_8_C_M 0x8000
#define PATH0_TSSI_VAL_D09_C 0x1C2C
#define PATH0_TSSI_VAL_D09_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_9_C 0x1C2C
#define PATH0_TSSI_VAL_VLD_IDX_9_C_M 0x80000000
#define PATH0_TSSI_VAL_D10_C 0x1C30
#define PATH0_TSSI_VAL_D10_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_10_C 0x1C30
#define PATH0_TSSI_VAL_VLD_IDX_10_C_M 0x8000
#define PATH0_TSSI_VAL_D11_C 0x1C30
#define PATH0_TSSI_VAL_D11_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_11_C 0x1C30
#define PATH0_TSSI_VAL_VLD_IDX_11_C_M 0x80000000
#define PATH0_TSSI_VAL_D12_C 0x1C34
#define PATH0_TSSI_VAL_D12_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_12_C 0x1C34
#define PATH0_TSSI_VAL_VLD_IDX_12_C_M 0x8000
#define PATH0_TSSI_VAL_D13_C 0x1C34
#define PATH0_TSSI_VAL_D13_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_13_C 0x1C34
#define PATH0_TSSI_VAL_VLD_IDX_13_C_M 0x80000000
#define PATH0_TSSI_VAL_D14_C 0x1C38
#define PATH0_TSSI_VAL_D14_C_M 0x3FF
#define PATH0_TSSI_VAL_VLD_IDX_14_C 0x1C38
#define PATH0_TSSI_VAL_VLD_IDX_14_C_M 0x8000
#define PATH0_TSSI_VAL_D15_C 0x1C38
#define PATH0_TSSI_VAL_D15_C_M 0x3FF0000
#define PATH0_TSSI_VAL_VLD_IDX_15_C 0x1C38
#define PATH0_TSSI_VAL_VLD_IDX_15_C_M 0x80000000
#define PATH0_TSSI_OSCILLATION_CNT_C 0x1C3C
#define PATH0_TSSI_OSCILLATION_CNT_C_M 0xFFFF
#define PATH0_TSSI_VAL_VLD_IDX_C 0x1C3C
#define PATH0_TSSI_VAL_VLD_IDX_C_M 0xFFFF0000
#define PATH0_PRE_TXAGC_OFST_C 0x1C40
#define PATH0_PRE_TXAGC_OFST_C_M 0xFF00
#define PATH0_DELTA_TSSI_PW_C 0x1C40
#define PATH0_DELTA_TSSI_PW_C_M 0xFF0000
#define PATH0SWING_MIN_C 0x1C40
#define PATH0SWING_MIN_C_M 0xF000000
#define PATH0SWING_MAX_C 0x1C40
#define PATH0SWING_MAX_C_M 0xF0000000
#define PATH0_TSSI_C_RAW0_C 0x1C44
#define PATH0_TSSI_C_RAW0_C_M 0x1FF000
#define PATH0_TSSI_F_C 0x1C48
#define PATH0_TSSI_F_C_M 0xFF
#define PATH0_TSSI_G_C 0x1C48
#define PATH0_TSSI_G_C_M 0x3FF00
#define PATH0_TSSI_S_C 0x1C48
#define PATH0_TSSI_S_C_M 0x1FF00000
#define PATH0_AVG_R_SQUARE_C 0x1C4C
#define PATH0_AVG_R_SQUARE_C_M 0xFFFFFF
#define PATH0_TSSI_F_RDY_C 0x1C4C
#define PATH0_TSSI_F_RDY_C_M 0x20000000
#define PATH0_TSSI_G_RDY_C 0x1C4C
#define PATH0_TSSI_G_RDY_C_M 0x40000000
#define PATH0_TSSI_C_RDY_C 0x1C4C
#define PATH0_TSSI_C_RDY_C_M 0x80000000
#define PATH0_IN_R_SQUARE_MAX_C 0x1C50
#define PATH0_IN_R_SQUARE_MAX_C_M 0xFFFFFF
#define PATH0_SPEC_IDX_C 0x1C50
#define PATH0_SPEC_IDX_C_M 0x7000000
#define PATH0_IN_R_SQUARE_MIN_C 0x1C54
#define PATH0_IN_R_SQUARE_MIN_C_M 0xFFFFFF
#define PATH0_AVG_R_RMS_C 0x1C58
#define PATH0_AVG_R_RMS_C_M 0xFFF
#define PATH0_AVG_R_RMS_RDY_C 0x1C58
#define PATH0_AVG_R_RMS_RDY_C_M 0x80000000
#define PATH0_DAC_GAIN_COMP_TBL_IDX_C 0x1C5C
#define PATH0_DAC_GAIN_COMP_TBL_IDX_C_M 0xFF
#define PATH0_DAC_GAIN_COMP_DBG_C 0x1C5C
#define PATH0_DAC_GAIN_COMP_DBG_C_M 0xFFFFF00
#define PATH0_TXAGC_RF_C 0x1C60
#define PATH0_TXAGC_RF_C_M 0x3F
#define PATH0_TSSI_OFST_C 0x1C60
#define PATH0_TSSI_OFST_C_M 0x1F00
#define PATH0_TXAGC_C 0x1C60
#define PATH0_TXAGC_C_M 0xFF0000
#define PATH0_TXAGC_ORIG_C 0x1C64
#define PATH0_TXAGC_ORIG_C_M 0x1FF
#define PATH0_TXAGC_ORIG_RAW_C 0x1C64
#define PATH0_TXAGC_ORIG_RAW_C_M 0x1FF000
#define PATH0_TXAGC_OFST_SEL_NONRFC_RPT_C 0x1C64
#define PATH0_TXAGC_OFST_SEL_NONRFC_RPT_C_M 0xFF000000
#define PATH0_TXAGC_TO_TSSI_CW_RPT_C 0x1C68
#define PATH0_TXAGC_TO_TSSI_CW_RPT_C_M 0xFFFFFFFF
#define PATH0_TSSI_C_RAW1_C 0x1C6C
#define PATH0_TSSI_C_RAW1_C_M 0x1FF
#define PATH0_DAC_GAIN_COMP_MX_C 0x1C70
#define PATH0_DAC_GAIN_COMP_MX_C_M 0xFF0000
#define PATH0_TSSI_CW_COMP_MX_C 0x1C70
#define PATH0_TSSI_CW_COMP_MX_C_M 0xFF000000
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_C 0x1C74
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_C_M 0x1FF
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_C 0x1C74
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_C_M 0x1FF000
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x1C74
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x1000000
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x1C74
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x2000000
#define PATH0_RFC_PREAMLE_PW_TYPE_C 0x1C74
#define PATH0_RFC_PREAMLE_PW_TYPE_C_M 0x70000000
#define PATH0_TXPW_C 0x1C78
#define PATH0_TXPW_C_M 0x1FF
#define PATH0_TXAGCSWING_C 0x1C78
#define PATH0_TXAGCSWING_C_M 0x1E00
#define PATH0_HE_ER_SU_EN_C 0x1C78
#define PATH0_HE_ER_SU_EN_C_M 0x2000
#define PATH0_HE_TB_EN_C 0x1C78
#define PATH0_HE_TB_EN_C_M 0x4000
#define PATH0_CCK_PPDU_C 0x1C78
#define PATH0_CCK_PPDU_C_M 0x8000
#define PATH0_TXINFO_CH_WITH_DATA_C 0x1C78
#define PATH0_TXINFO_CH_WITH_DATA_C_M 0xFF0000
#define PATH0_TXSC_C 0x1C78
#define PATH0_TXSC_C_M 0xF000000
#define PATH0_RF_BW_IDX_C 0x1C78
#define PATH0_RF_BW_IDX_C_M 0x30000000
#define PATH0_ISOFDM_PREAMBLE_C 0x1C78
#define PATH0_ISOFDM_PREAMBLE_C_M 0x40000000
#define PATH0_ISCCK_PREAMBLE_C 0x1C78
#define PATH0_ISCCK_PREAMBLE_C_M 0x80000000
#define PATH0_TXAGC_OFST_MX_C 0x1C7C
#define PATH0_TXAGC_OFST_MX_C_M 0xFF
#define PATH0_TXAGC_OFST_C 0x1C7C
#define PATH0_TXAGC_OFST_C_M 0xFF00
#define PATH0_TXAGC_OFST_VARIATION_POS_FLAG_C 0x1C7C
#define PATH0_TXAGC_OFST_VARIATION_POS_FLAG_C_M 0x10000
#define PATH0_TXAGC_OFST_VARIATION_NEG_FLAG_C 0x1C7C
#define PATH0_TXAGC_OFST_VARIATION_NEG_FLAG_C_M 0x20000
#define PATH0_BYPASS_TSSI_BY_C_C 0x1C7C
#define PATH0_BYPASS_TSSI_BY_C_C_M 0x40000
#define PATH0_ADC_VARIATION_C 0x1C7C
#define PATH0_ADC_VARIATION_C_M 0xFFF00000
#define PATH0_DBG_IQK_PATH_C 0x1C80
#define PATH0_DBG_IQK_PATH_C_M 0xFFFFFFFF
#define PATH0_FTM_RFLBK_BYPASS_C 0x1C84
#define PATH0_FTM_RFLBK_BYPASS_C_M 0x1
#define PATH0_FTM_LBK_BYPASS_C 0x1C84
#define PATH0_FTM_LBK_BYPASS_C_M 0x2
#define PATH0_FTM_A2A_AFELBK_BYPASS_C 0x1C84
#define PATH0_FTM_A2A_AFELBK_BYPASS_C_M 0x4
#define PATH0_GNT_BT_TX_BYPASS_C 0x1C84
#define PATH0_GNT_BT_TX_BYPASS_C_M 0x8
#define PATH0_GNT_BT_BYPASS_C 0x1C84
#define PATH0_GNT_BT_BYPASS_C_M 0x10
#define PATH0_GNT_WL_BYPASS_C 0x1C84
#define PATH0_GNT_WL_BYPASS_C_M 0x20
#define PATH0_LTE_RX_BYPASS_C 0x1C84
#define PATH0_LTE_RX_BYPASS_C_M 0x40
#define PATH0_TSSI_BYPASS_TXPW_MIN_C 0x1C84
#define PATH0_TSSI_BYPASS_TXPW_MIN_C_M 0x80
#define PATH0_TSSI_BYPASS_TXPW_MAX_C 0x1C84
#define PATH0_TSSI_BYPASS_TXPW_MAX_C_M 0x100
#define PATH0_BYPASS_TSSI_BY_RATE_CCK_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_CCK_C_M 0x200
#define PATH0_BYPASS_TSSI_BY_RATE_LEGACY_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_LEGACY_C_M 0x400
#define PATH0_BYPASS_TSSI_BY_RATE_HT_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_HT_C_M 0x800
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_C_M 0x1000
#define PATH0_BYPASS_TSSI_BY_RATE_HE_SU_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_HE_SU_C_M 0x2000
#define PATH0_BYPASS_TSSI_BY_RATE_HE_ER_SU_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_HE_ER_SU_C_M 0x4000
#define PATH0_BYPASS_TSSI_BY_RATE_HE_TB_EN_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_HE_TB_EN_C_M 0x8000
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_MU_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_MU_C_M 0x10000
#define PATH0_BYPASS_TSSI_BY_RATE_HE_MU_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_HE_MU_C_M 0x20000
#define PATH0_BYPASS_TSSI_BY_RATE_HE_RU_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RATE_HE_RU_C_M 0x40000
#define PATH0_BYPASS_TSSI_BY_TXBF_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_TXBF_C_M 0x80000
#define PATH0_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x1C84
#define PATH0_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x100000
#define PATH0_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x1C84
#define PATH0_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x200000
#define PATH0_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C 0x1C84
#define PATH0_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x400000
#define PATH0_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C 0x1C84
#define PATH0_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x800000
#define PATH0_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C 0x1C84
#define PATH0_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C_M 0x40000000
#define PATH0_BYPASS_TSSI_C 0x1C84
#define PATH0_BYPASS_TSSI_C_M 0x80000000
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_C 0x1C88
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_C_M 0xF
#define PATH0_DIGI_AGC_C 0x1C88
#define PATH0_DIGI_AGC_C_M 0x3FF0
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_MX_C 0x1C88
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_MX_C_M 0xF0000
#define PATH0_WLS_WL_GAIN_TX_PAD_BUF_MX_C 0x1C88
#define PATH0_WLS_WL_GAIN_TX_PAD_BUF_MX_C_M 0x1F00000
#define PATH0_WLS_WL_GAIN_TX_BUF_MX_C 0x1C88
#define PATH0_WLS_WL_GAIN_TX_BUF_MX_C_M 0x3E000000
#define PATH0_RX_CFIR_TAP_DEC_C 0x1C88
#define PATH0_RX_CFIR_TAP_DEC_C_M 0x40000000
#define PATH0_CLK_HIGH_RATE_MX_C 0x1C88
#define PATH0_CLK_HIGH_RATE_MX_C_M 0x80000000
#define PATH0_CFIR_OUT_IM_DBG_C 0x1C8C
#define PATH0_CFIR_OUT_IM_DBG_C_M 0xFFF
#define PATH0_CFIR_OUT_RE_DBG_C 0x1C8C
#define PATH0_CFIR_OUT_RE_DBG_C_M 0xFFF000
#define PATH0_EN_RX_CFIR_C 0x1C8C
#define PATH0_EN_RX_CFIR_C_M 0x1000000
#define PATH0_CLK_HIGH_RATE_C 0x1C8C
#define PATH0_CLK_HIGH_RATE_C_M 0x2000000
#define PATH0_EN_TX_CFIR_C 0x1C8C
#define PATH0_EN_TX_CFIR_C_M 0x4000000
#define PATH0_TX_CCK_IND_C 0x1C8C
#define PATH0_TX_CCK_IND_C_M 0x8000000
#define PATH0_CFIR_IN_IM_DBG_C 0x1C90
#define PATH0_CFIR_IN_IM_DBG_C_M 0xFFF
#define PATH0_CFIR_IN_RE_DBG_C 0x1C90
#define PATH0_CFIR_IN_RE_DBG_C_M 0xFFF000
#define PATH0_CCK_CCA_C 0x1C90
#define PATH0_CCK_CCA_C_M 0x80000000
#define PATH0_RX_C 0x1C94
#define PATH0_RX_C_M 0x1F
#define PATH0_LNA_SETTING_C 0x1C94
#define PATH0_LNA_SETTING_C_M 0x700
#define PATH0_TIA_C 0x1C94
#define PATH0_TIA_C_M 0x1000
#define PATH0_DB2FLT_O_C 0x1C94
#define PATH0_DB2FLT_O_C_M 0x7FF8000
#define PATH0_LSTF_SUM_LINEAR_PW_C 0x1C98
#define PATH0_LSTF_SUM_LINEAR_PW_C_M 0xFFFFFFFF
#define PATH0_LSTF_MAX_LINEAR_PW_C 0x1C9C
#define PATH0_LSTF_MAX_LINEAR_PW_C_M 0x7FFFFF
#define PATH0_TSSI_C_C 0x1CA0
#define PATH0_TSSI_C_C_M 0x1FF
#define PATH0_TSSI_C_SRC_C 0x1CA0
#define PATH0_TSSI_C_SRC_C_M 0x3FF000
#define PATH0_TXAGC_TP_C 0x1CA0
#define PATH0_TXAGC_TP_C_M 0xFF000000
#define PATH0_LOG_VAL_O_C 0x1CA4
#define PATH0_LOG_VAL_O_C_M 0xFFFFF
#define PATH0_TXAGC_OFST_ADJ_C 0x1CA4
#define PATH0_TXAGC_OFST_ADJ_C_M 0xFF000000
#define PATH0_TX_GAIN_FOR_DPD_DB2FLOAT_C 0x1CA8
#define PATH0_TX_GAIN_FOR_DPD_DB2FLOAT_C_M 0xFF
#define PATH0_TX_GAIN_FOR_DPD_DBAGC_COMB_C 0x1CA8
#define PATH0_TX_GAIN_FOR_DPD_DBAGC_COMB_C_M 0xFF00
#define PATH0_TMETER_TX_C 0x1CAC
#define PATH0_TMETER_TX_C_M 0x3F
#define PATH0_TMETER_CCA_POS_C 0x1CAC
#define PATH0_TMETER_CCA_POS_C_M 0x3F00
#define PATH0_TMETER_CCA_NEG_C 0x1CAC
#define PATH0_TMETER_CCA_NEG_C_M 0x3F0000
#define PATH0_AFE_ANAPAR_PW_O_C 0x1CB0
#define PATH0_AFE_ANAPAR_PW_O_C_M 0xFF
#define PATH0_AFE_ANAPAR_CTRL_O_C 0x1CB0
#define PATH0_AFE_ANAPAR_CTRL_O_C_M 0xFFFF00
#define PATH0_MUX_ST_PATH_C 0x1CB0
#define PATH0_MUX_ST_PATH_C_M 0xF000000
#define PATH0_TSSI_J_CCK_C 0x1CB4
#define PATH0_TSSI_J_CCK_C_M 0x3FF
#define PATH0_TSSI_J_OFDM_C 0x1CB4
#define PATH0_TSSI_J_OFDM_C_M 0xFFC00
#define PATH0_TSSI_CURVE_C 0x1CB4
#define PATH0_TSSI_CURVE_C_M 0x70000000
#define PATH0_R_TXAGC_OFDM_REF_CW_CMB_C 0x1CB8
#define PATH0_R_TXAGC_OFDM_REF_CW_CMB_C_M 0x1FF
#define PATH0_R_TXAGC_CCK_REF_CW_CMB_C 0x1CB8
#define PATH0_R_TXAGC_CCK_REF_CW_CMB_C_M 0x1FF000
#define PATH0_AFE_ANAPAR_CTSDM_OUT_I_C 0x1E00
#define PATH0_AFE_ANAPAR_CTSDM_OUT_I_C_M 0xFFFFF
#define PATH0_RO_SI_R_DATA_P_C 0x1E04
#define PATH0_RO_SI_R_DATA_P_C_M 0xFFFFF
#define PATH0_NLGC_STEP_CNT_AT_AGC_RDY_C 0x1E08
#define PATH0_NLGC_STEP_CNT_AT_AGC_RDY_C_M 0x7
#define PATH0_POST_PD_STEP_CNT_AT_AGC_RDY_C 0x1E08
#define PATH0_POST_PD_STEP_CNT_AT_AGC_RDY_C_M 0x38
#define PATH0_LINEAR_STEP_CNT_AT_AGC_RDY_C 0x1E08
#define PATH0_LINEAR_STEP_CNT_AT_AGC_RDY_C_M 0x1C0
#define PATH0_PRE_PD_STEP_CNT_AT_AGC_RDY_C 0x1E08
#define PATH0_PRE_PD_STEP_CNT_AT_AGC_RDY_C_M 0xE00
#define PATH0_TIA_SAT_DET_AT_AGC_RDY_C 0x1E08
#define PATH0_TIA_SAT_DET_AT_AGC_RDY_C_M 0x1000
#define PATH0_LNA_SAT_DET_AT_AGC_RDY_C 0x1E08
#define PATH0_LNA_SAT_DET_AT_AGC_RDY_C_M 0x2000
#define PATH0_NRBW_AT_AGC_RDY_C 0x1E08
#define PATH0_NRBW_AT_AGC_RDY_C_M 0x4000
#define PATH0_TIA_SHRINK_AT_AGC_RDY_C 0x1E08
#define PATH0_TIA_SHRINK_AT_AGC_RDY_C_M 0x8000
#define PATH0_P_DIFF_AT_AGC_RDY_C 0x1E08
#define PATH0_P_DIFF_AT_AGC_RDY_C_M 0xFF0000
#define PATH0_ELNA_IDX_AT_AGC_RDY_C 0x1E0C
#define PATH0_ELNA_IDX_AT_AGC_RDY_C_M 0x1
#define PATH0_ELNA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_ELNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x2
#define PATH0_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x4
#define PATH0_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x8
#define PATH0_NRBW_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_NRBW_AT_PRE_PD_AGC_RDY_C_M 0x10
#define PATH0_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C_M 0x20
#define PATH0_P_DIFF_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_P_DIFF_AT_PRE_PD_AGC_RDY_C_M 0x7FC0
#define PATH0_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C_M 0x7F8000
#define PATH0_RXIDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_RXIDX_AT_PRE_PD_AGC_RDY_C_M 0xF800000
#define PATH0_TIA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_TIA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x10000000
#define PATH0_LNA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
#define PATH0_LNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0xE0000000
#define PATH0_ELNA_IDX_AT_PD_HIT_C 0x1E10
#define PATH0_ELNA_IDX_AT_PD_HIT_C_M 0x2
#define PATH0_TIA_SAT_DET_AT_PD_HIT_C 0x1E10
#define PATH0_TIA_SAT_DET_AT_PD_HIT_C_M 0x4
#define PATH0_LNA_SAT_DET_AT_PD_HIT_C 0x1E10
#define PATH0_LNA_SAT_DET_AT_PD_HIT_C_M 0x8
#define PATH0_NRBW_AT_PD_HIT_C 0x1E10
#define PATH0_NRBW_AT_PD_HIT_C_M 0x10
#define PATH0_TIA_SHRINK_AT_PD_HIT_C 0x1E10
#define PATH0_TIA_SHRINK_AT_PD_HIT_C_M 0x20
#define PATH0_P_DIFF_AT_PD_HIT_C 0x1E10
#define PATH0_P_DIFF_AT_PD_HIT_C_M 0x7FC0
#define PATH0_G_NLGC_DAGC_AT_PD_HIT_C 0x1E10
#define PATH0_G_NLGC_DAGC_AT_PD_HIT_C_M 0x7F8000
#define PATH0_RXIDX_AT_PD_HIT_C 0x1E10
#define PATH0_RXIDX_AT_PD_HIT_C_M 0xF800000
#define PATH0_TIA_IDX_AT_PD_HIT_C 0x1E10
#define PATH0_TIA_IDX_AT_PD_HIT_C_M 0x10000000
#define PATH0_LNA_IDX_AT_PD_HIT_C 0x1E10
#define PATH0_LNA_IDX_AT_PD_HIT_C_M 0xE0000000
#define PATH0_ELNA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_ELNA_IDX_AT_POST_PD_AGC_RDY_C_M 0x2
#define PATH0_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x4
#define PATH0_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x8
#define PATH0_NRBW_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_NRBW_AT_POST_PD_AGC_RDY_C_M 0x10
#define PATH0_TIA_SHRINK_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_TIA_SHRINK_AT_POST_PD_AGC_RDY_C_M 0x20
#define PATH0_P_DIFF_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_P_DIFF_AT_POST_PD_AGC_RDY_C_M 0x7FC0
#define PATH0_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C_M 0x7F8000
#define PATH0_RXIDX_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_RXIDX_AT_POST_PD_AGC_RDY_C_M 0xF800000
#define PATH0_TIA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_TIA_IDX_AT_POST_PD_AGC_RDY_C_M 0x10000000
#define PATH0_LNA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14
#define PATH0_LNA_IDX_AT_POST_PD_AGC_RDY_C_M 0xE0000000
#define PATH0_ELNA_IDX_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_ELNA_IDX_AT_NLGC_AGC_RDY_C_M 0x2
#define PATH0_TIA_SAT_DET_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_TIA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x4
#define PATH0_LNA_SAT_DET_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_LNA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x8
#define PATH0_NRBW_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_NRBW_AT_NLGC_AGC_RDY_C_M 0x10
#define PATH0_TIA_SHRINK_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_TIA_SHRINK_AT_NLGC_AGC_RDY_C_M 0x20
#define PATH0_P_DIFF_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_P_DIFF_AT_NLGC_AGC_RDY_C_M 0x7FC0
#define PATH0_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C_M 0x7F8000
#define PATH0_RXIDX_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_RXIDX_AT_NLGC_AGC_RDY_C_M 0xF800000
#define PATH0_TIA_IDX_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_TIA_IDX_AT_NLGC_AGC_RDY_C_M 0x10000000
#define PATH0_LNA_IDX_AT_NLGC_AGC_RDY_C 0x1E18
#define PATH0_LNA_IDX_AT_NLGC_AGC_RDY_C_M 0xE0000000
#define PATH0_RSSI_AT_AGC_RDY_C 0x1E1C
#define PATH0_RSSI_AT_AGC_RDY_C_M 0x3FF
#define PATH0_G_TOTAL_AT_AGC_RDY_C 0x1E1C
#define PATH0_G_TOTAL_AT_AGC_RDY_C_M 0x7FC00
#define PATH0_P_DFIR_DBM_AT_AGC_RDY_C 0x1E1C
#define PATH0_P_DFIR_DBM_AT_AGC_RDY_C_M 0xFF80000
#define PATH0_TIA_IDX_AT_AGC_RDY_C 0x1E1C
#define PATH0_TIA_IDX_AT_AGC_RDY_C_M 0x10000000
#define PATH0_LNA_IDX_AT_AGC_RDY_C 0x1E1C
#define PATH0_LNA_IDX_AT_AGC_RDY_C_M 0xE0000000
#define PATH0_RSSI_ALWAYS_RUN_C 0x1E20
#define PATH0_RSSI_ALWAYS_RUN_C_M 0x3FF
#define PATH0_TIA_SAT_DET_C 0x1E20
#define PATH0_TIA_SAT_DET_C_M 0x400
#define PATH0_LNA_SAT_DET_C 0x1E20
#define PATH0_LNA_SAT_DET_C_M 0x800
#define PATH0_NRBW_C 0x1E20
#define PATH0_NRBW_C_M 0x1000
#define PATH0_TIA_SHRINK_C 0x1E20
#define PATH0_TIA_SHRINK_C_M 0x2000
#define PATH0_G_LGC_DAGC_C 0x1E20
#define PATH0_G_LGC_DAGC_C_M 0x3FC000
#define PATH0_G_TOTAL_C 0x1E20
#define PATH0_G_TOTAL_C_M 0xFFC00000
#define PATH0_HW_SI_READ_DATA_C 0x1E24
#define PATH0_HW_SI_READ_DATA_C_M 0xFFFFF
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C_M 0x1
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C_M 0x2
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C_M 0x4
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C_M 0x8
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C_M 0x10
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C_M 0x20
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C_M 0x40
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C_M 0x80
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C_M 0x100
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C_M 0x200
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C_M 0x400
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C 0x1E28
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C_M 0x800
#define PATH0_CNT_HW_SI_W_TX_CMD_START_PATH_C 0x1E2C
#define PATH0_CNT_HW_SI_W_TX_CMD_START_PATH_C_M 0xFFFF
#define PATH0_CNT_HW_SI_W_RX_CMD_START_PATH_C 0x1E2C
#define PATH0_CNT_HW_SI_W_RX_CMD_START_PATH_C_M 0xFFFF0000
#define PATH0_CNT_HW_SI_R_CMD_START_PATH_C 0x1E30
#define PATH0_CNT_HW_SI_R_CMD_START_PATH_C_M 0xFFFF
#define RFMOD_C 0x2000
#define RFMOD_C_M 0x3
#define DFS_MASK_RX_OPT_C 0x2000
#define DFS_MASK_RX_OPT_C_M 0xC
#define DFS_MASK_TRANSIENT_OPT_C 0x2000
#define DFS_MASK_TRANSIENT_OPT_C_M 0xF0
#define PXP_SEL_SNR_C 0x2000
#define PXP_SEL_SNR_C_M 0x3F00
#define CH_INFO_TYPE_C 0x2000
#define CH_INFO_TYPE_C_M 0x4000
#define DFS_MASK_TRANSIENT_EN_C 0x2000
#define DFS_MASK_TRANSIENT_EN_C_M 0x8000
#define DFS_MASK_TRANSIENT_TH_C 0x2000
#define DFS_MASK_TRANSIENT_TH_C_M 0xFF0000
#define DFS_CHIRP_FLAG_ACC_TH_C 0x2000
#define DFS_CHIRP_FLAG_ACC_TH_C_M 0xFF000000
#define BIST_SEL_C 0x2004
#define BIST_SEL_C_M 0x1F
#define TX_CKEN_BOTH_PATH_FORCE_VAL_C 0x2008
#define TX_CKEN_BOTH_PATH_FORCE_VAL_C_M 0xF
#define TD_CLK_GEN_RX_PATH_EN_FORCE_VAL_C 0x2008
#define TD_CLK_GEN_RX_PATH_EN_FORCE_VAL_C_M 0xF0
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_VAL_C 0x2008
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_VAL_C_M 0xF00
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_VAL_C 0x2008
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_VAL_C_M 0xF000
#define TD_CLK_GEN_TX_PATH_EN_FORCE_VAL_C 0x2008
#define TD_CLK_GEN_TX_PATH_EN_FORCE_VAL_C_M 0xF0000
#define TX_CKEN_BOTH_PATH_FORCE_ON_C 0x2008
#define TX_CKEN_BOTH_PATH_FORCE_ON_C_M 0x100000
#define TD_CLK_GEN_RX_PATH_EN_FORCE_ON_C 0x2008
#define TD_CLK_GEN_RX_PATH_EN_FORCE_ON_C_M 0x200000
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_ON_C 0x2008
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_ON_C_M 0x400000
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_ON_C 0x2008
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_ON_C_M 0x800000
#define TD_CLK_GEN_TX_PATH_EN_FORCE_ON_C 0x2008
#define TD_CLK_GEN_TX_PATH_EN_FORCE_ON_C_M 0x1000000
#define CH_INFO_SEG_LEN_C 0x2008
#define CH_INFO_SEG_LEN_C_M 0x6000000
#define CH_INFO_MASK_OPT_C 0x2008
#define CH_INFO_MASK_OPT_C_M 0x8000000
#define BIST_RSTB_C 0x200C
#define BIST_RSTB_C_M 0x2
#define TEST_RESUME_C 0x200C
#define TEST_RESUME_C_M 0x10
#define BIST_VDDR_TEST_C 0x200C
#define BIST_VDDR_TEST_C_M 0x100
#define BIST_EN_7_0__C 0x200C
#define BIST_EN_7_0__C_M 0xFF000000
#define BIST_MOD_31_0__C 0x2010
#define BIST_MOD_31_0__C_M 0xFFFFFFFF
#define BIST_MOD_63_32__C 0x2014
#define BIST_MOD_63_32__C_M 0xFFFFFFFF
#define BIST_MOD_95_64__C 0x2018
#define BIST_MOD_95_64__C_M 0xFFFFFFFF
#define BIST_MOD_127_96__C 0x201C
#define BIST_MOD_127_96__C_M 0xFFFFFFFF
#define BIST_MOD_159_128__C 0x2020
#define BIST_MOD_159_128__C_M 0xFFFFFFFF
#define BIST_MOD_191_160__C 0x2024
#define BIST_MOD_191_160__C_M 0xFFFFFFFF
#define DRF_BIST_MOD_31_0__C 0x2028
#define DRF_BIST_MOD_31_0__C_M 0xFFFFFFFF
#define DRF_BIST_MOD_63_32__C 0x202C
#define DRF_BIST_MOD_63_32__C_M 0xFFFFFFFF
#define DRF_BIST_MOD_95_64__C 0x2030
#define DRF_BIST_MOD_95_64__C_M 0xFFFFFFFF
#define DRF_BIST_MOD_127_96__C 0x2034
#define DRF_BIST_MOD_127_96__C_M 0xFFFFFFFF
#define DRF_BIST_MOD_159_128__C 0x2038
#define DRF_BIST_MOD_159_128__C_M 0xFFFFFFFF
#define DRF_BIST_MOD_191_160__C 0x203C
#define DRF_BIST_MOD_191_160__C_M 0xFFFFFFFF
#define BIST_DVSE_31_0__C 0x2040
#define BIST_DVSE_31_0__C_M 0xFFFFFFFF
#define BIST_DVSE_63_32__C 0x2044
#define BIST_DVSE_63_32__C_M 0xFFFFFFFF
#define BIST_DVSE_95_64__C 0x2048
#define BIST_DVSE_95_64__C_M 0xFFFFFFFF
#define BIST_DVSE_127_96__C 0x204C
#define BIST_DVSE_127_96__C_M 0xFFFFFFFF
#define BIST_DVSE_159_128__C 0x2050
#define BIST_DVSE_159_128__C_M 0xFFFFFFFF
#define BIST_DVSE_191_160__C 0x2054
#define BIST_DVSE_191_160__C_M 0xFFFFFFFF
#define BIST_DVS_31_0__C 0x2058
#define BIST_DVS_31_0__C_M 0xFFFFFFFF
#define BIST_DVS_63_32__C 0x205C
#define BIST_DVS_63_32__C_M 0xFFFFFFFF
#define BIST_DVS_95_64__C 0x2060
#define BIST_DVS_95_64__C_M 0xFFFFFFFF
#define BIST_DVS_127_96__C 0x2064
#define BIST_DVS_127_96__C_M 0xFFFFFFFF
#define BIST_DVS_159_128__C 0x2068
#define BIST_DVS_159_128__C_M 0xFFFFFFFF
#define BIST_DVS_191_160__C 0x206C
#define BIST_DVS_191_160__C_M 0xFFFFFFFF
#define BIST_TEST1_31_0__C 0x2070
#define BIST_TEST1_31_0__C_M 0xFFFFFFFF
#define BIST_TEST1_63_32__C 0x2074
#define BIST_TEST1_63_32__C_M 0xFFFFFFFF
#define BIST_TEST1_95_64__C 0x2078
#define BIST_TEST1_95_64__C_M 0xFFFFFFFF
#define BIST_TEST1_127_96__C 0x207C
#define BIST_TEST1_127_96__C_M 0xFFFFFFFF
#define BIST_TEST1_159_128__C 0x2080
#define BIST_TEST1_159_128__C_M 0xFFFFFFFF
#define BIST_TEST1_191_160__C 0x2084
#define BIST_TEST1_191_160__C_M 0xFFFFFFFF
#define BIST_GRP_EN_31_0__C 0x2088
#define BIST_GRP_EN_31_0__C_M 0xFFFFFFFF
#define BIST_GRP_EN_63_32__C 0x208C
#define BIST_GRP_EN_63_32__C_M 0xFFFFFFFF
#define LA_EN_C 0x2090
#define LA_EN_C_M 0x1
#define LA_DBGPORT_BASE_N_C 0x2090
#define LA_DBGPORT_BASE_N_C_M 0x3E
#define LA_TYPEA_PATH_SEL_C 0x2090
#define LA_TYPEA_PATH_SEL_C_M 0xC0
#define LA_TYPEB_PATH_SEL_C 0x2090
#define LA_TYPEB_PATH_SEL_C_M 0x300
#define LA_TYPEC_PATH_SEL_C 0x2090
#define LA_TYPEC_PATH_SEL_C_M 0xC00
#define LA_TYPED_PATH_SEL_C 0x2090
#define LA_TYPED_PATH_SEL_C_M 0x3000
#define LA_TYPEA_SRC_SEL_C 0x2090
#define LA_TYPEA_SRC_SEL_C_M 0x1C000
#define LA_TYPEB_SRC_SEL_C 0x2090
#define LA_TYPEB_SRC_SEL_C_M 0xE0000
#define LA_TYPEC_SRC_SEL_C 0x2090
#define LA_TYPEC_SRC_SEL_C_M 0x700000
#define LA_TYPED_SRC_SEL_C 0x2090
#define LA_TYPED_SRC_SEL_C_M 0x3800000
#define LA_SMP_RT_SEL_C 0x2090
#define LA_SMP_RT_SEL_C_M 0x1C000000
#define LA_RDRDY_3PHASE_EN_C 0x2090
#define LA_RDRDY_3PHASE_EN_C_M 0x20000000
#define LA_EDGE_SEL_C 0x2090
#define LA_EDGE_SEL_C_M 0x40000000
#define LA_HDR_SEL_63_C 0x2094
#define LA_HDR_SEL_63_C_M 0xF
#define LA_HDR_SEL_62_C 0x2094
#define LA_HDR_SEL_62_C_M 0xF0
#define LA_HDR_SEL_61_C 0x2094
#define LA_HDR_SEL_61_C_M 0xF00
#define LA_HDR_SEL_60_C 0x2094
#define LA_HDR_SEL_60_C_M 0xF000
#define LA_TYPEA_CK160_DLY_EN_C 0x2094
#define LA_TYPEA_CK160_DLY_EN_C_M 0x10000
#define LA_TYPEB_CK160_DLY_EN_C 0x2094
#define LA_TYPEB_CK160_DLY_EN_C_M 0x20000
#define LA_DBGPORT_SRC_SEL_C 0x2094
#define LA_DBGPORT_SRC_SEL_C_M 0x40000
#define LA_DATA_C 0x2094
#define LA_DATA_C_M 0x1F80000
#define LA_RDRDY_C 0x2094
#define LA_RDRDY_C_M 0x6000000
#define LA_IQSHFT_C 0x2094
#define LA_IQSHFT_C_M 0x18000000
#define LA_MONITOR_SEL_C 0x2094
#define LA_MONITOR_SEL_C_M 0x60000000
#define LA_SEL_P1_C 0x2094
#define LA_SEL_P1_C_M 0x80000000
#define LA_TRIG_C 0x2098
#define LA_TRIG_C_M 0x1F
#define LA_TRIG_CNT_C 0x2098
#define LA_TRIG_CNT_C_M 0x1FE0
#define LA_TRIG_NEW_ONLY_C 0x2098
#define LA_TRIG_NEW_ONLY_C_M 0x2000
#define LA_TRIG_AND1_INV_C 0x2098
#define LA_TRIG_AND1_INV_C_M 0x4000
#define LA_TRIG_AND2_EN_C 0x2098
#define LA_TRIG_AND2_EN_C_M 0x8000
#define LA_TRIG_AND2_INV_C 0x2098
#define LA_TRIG_AND2_INV_C_M 0x10000
#define LA_TRIG_AND3_EN_C 0x2098
#define LA_TRIG_AND3_EN_C_M 0x20000
#define LA_TRIG_AND3_INV_C 0x2098
#define LA_TRIG_AND3_INV_C_M 0x40000
#define LA_TRIG_AND4_EN_C 0x2098
#define LA_TRIG_AND4_EN_C_M 0x80000
#define LA_TRIG_AND4_VAL_C 0x2098
#define LA_TRIG_AND4_VAL_C_M 0x1FF00000
#define LA_TRIG_AND4_INV_C 0x2098
#define LA_TRIG_AND4_INV_C_M 0x20000000
#define LA_TRIG_AND1_BIT_EN_C 0x209C
#define LA_TRIG_AND1_BIT_EN_C_M 0xFFFFFFFF
#define LA_TRIG_AND1_VAL_C 0x20A0
#define LA_TRIG_AND1_VAL_C_M 0xFFFFFFFF
#define LA_TRIG_AND2_MASK_C 0x20A4
#define LA_TRIG_AND2_MASK_C_M 0xFFFFFFFF
#define LA_TRIG_AND2_VAL_C 0x20A8
#define LA_TRIG_AND2_VAL_C_M 0xFFFFFFFF
#define LA_TRIG_AND3_MASK_C 0x20AC
#define LA_TRIG_AND3_MASK_C_M 0xFFFFFFFF
#define LA_TRIG_AND3_VAL_C 0x20B0
#define LA_TRIG_AND3_VAL_C_M 0xFFFFFFFF
#define LA_TRIG_AND5_C 0x20B4
#define LA_TRIG_AND5_C_M 0xF
#define LA_TRIG_AND5_VAL_C 0x20B4
#define LA_TRIG_AND5_VAL_C_M 0x1F0
#define LA_TRIG_AND5_INV_C 0x20B4
#define LA_TRIG_AND5_INV_C_M 0x200
#define LA_TRIG_AND6_C 0x20B4
#define LA_TRIG_AND6_C_M 0x3C00
#define LA_TRIG_AND6_VAL_C 0x20B4
#define LA_TRIG_AND6_VAL_C_M 0x7C000
#define LA_TRIG_AND6_INV_C 0x20B4
#define LA_TRIG_AND6_INV_C_M 0x80000
#define LA_TRIG_AND7_C 0x20B4
#define LA_TRIG_AND7_C_M 0xF00000
#define LA_TRIG_AND7_VAL_C 0x20B4
#define LA_TRIG_AND7_VAL_C_M 0x1F000000
#define LA_TRIG_AND7_INV_C 0x20B4
#define LA_TRIG_AND7_INV_C_M 0x20000000
#define LA_M_AND1_EN_C 0x20B4
#define LA_M_AND1_EN_C_M 0x40000000
#define LA_M_AND2_EN_C 0x20B4
#define LA_M_AND2_EN_C_M 0x80000000
#define LA_DBG_EN_C 0x20B8
#define LA_DBG_EN_C_M 0x1
#define LA_DBG_POLARITY_C 0x20B8
#define LA_DBG_POLARITY_C_M 0x2
#define LA_DBG_TRIG_SEL_C 0x20B8
#define LA_DBG_TRIG_SEL_C_M 0xFC
#define LA_DBG_INTERVAL_C 0x20B8
#define LA_DBG_INTERVAL_C_M 0x700
#define LA_DBG_SEL_0_C 0x20B8
#define LA_DBG_SEL_0_C_M 0x7FF800
#define LA_M_AND0_SEL_C 0x20B8
#define LA_M_AND0_SEL_C_M 0x3800000
#define LA_M_AND0_EN_C 0x20B8
#define LA_M_AND0_EN_C_M 0x4000000
#define LA_SIGN2_C 0x20B8
#define LA_SIGN2_C_M 0x18000000
#define LA_SIGN3_C 0x20B8
#define LA_SIGN3_C_M 0x60000000
#define LA_DBG_SEL_1_C 0x20BC
#define LA_DBG_SEL_1_C_M 0xFFF
#define LA_DBG_SEL_2_C 0x20BC
#define LA_DBG_SEL_2_C_M 0xFFF000
#define LA_DBG_SEL_3_C 0x20C0
#define LA_DBG_SEL_3_C_M 0xFFF
#define LA_DBG_SEL_4_C 0x20C0
#define LA_DBG_SEL_4_C_M 0xFFF000
#define WIFI_LOC_P1_C 0x20C0
#define WIFI_LOC_P1_C_M 0xFF000000
#define LA_DBG_SEL_5_C 0x20C4
#define LA_DBG_SEL_5_C_M 0xFFF
#define LA_DBG_SEL_6_C 0x20C4
#define LA_DBG_SEL_6_C_M 0xFFF000
#define WIFI_LOC_C 0x20C4
#define WIFI_LOC_C_M 0xFF000000
#define LA_DBG_SEL_7_C 0x20C8
#define LA_DBG_SEL_7_C_M 0xFFF
#define LA_RE_INIT_POLARITY_C 0x20C8
#define LA_RE_INIT_POLARITY_C_M 0x1000
#define LA_RE_INIT_AND1_C 0x20C8
#define LA_RE_INIT_AND1_C_M 0x1E000
#define LA_RE_INIT_AND1_VAL_C 0x20C8
#define LA_RE_INIT_AND1_VAL_C_M 0x3E0000
#define LA_RE_INIT_AND1_INV_C 0x20C8
#define LA_RE_INIT_AND1_INV_C_M 0x400000
#define PSD_DD_OPT_C 0x20C8
#define PSD_DD_OPT_C_M 0xFF800000
#define EDCCA_RPTREG_SEL_P0_C 0x20CC
#define EDCCA_RPTREG_SEL_P0_C_M 0x7
#define EDCCA_RPTREG_SEL_P1_C 0x20CC
#define EDCCA_RPTREG_SEL_P1_C_M 0x38
#define FTM_C 0x20CC
#define FTM_C_M 0xFF0000
#define DIS_IOQ_RFC_C 0x20D0
#define DIS_IOQ_RFC_C_M 0x1
#define DIS_IOQ_AFE_C 0x20D0
#define DIS_IOQ_AFE_C_M 0x2
#define BT_WL_RF_MODEAGH_C 0x20D0
#define BT_WL_RF_MODEAGH_C_M 0xC
#define FTM_T_LBK_FORCE_EN_C 0x20D0
#define FTM_T_LBK_FORCE_EN_C_M 0x2000
#define FTM_T_LBK_FORCE_VAL_C 0x20D0
#define FTM_T_LBK_FORCE_VAL_C_M 0xFFFFC000
#define MAC0_PIN_SEL_C 0x20D4
#define MAC0_PIN_SEL_C_M 0xFFFF
#define MAC1_PIN_SEL_C 0x20D4
#define MAC1_PIN_SEL_C_M 0xFFFF0000
#define PWDB_CNT_TH_P0_C 0x20D8
#define PWDB_CNT_TH_P0_C_M 0xFF
#define PWDB_CNT_TH_P1_C 0x20D8
#define PWDB_CNT_TH_P1_C_M 0xFF00
#define LBK_SEL_C 0x20EC
#define LBK_SEL_C_M 0x7
#define MUX_ST_BYPASS_TXEN_C 0x20EC
#define MUX_ST_BYPASS_TXEN_C_M 0x10
#define DUMMY_P09_EC_C 0x20EC
#define DUMMY_P09_EC_C_M 0xFFFFFFE0
#define DBG_PORT_SEL_C 0x20F0
#define DBG_PORT_SEL_C_M 0xFFFF
#define DBG_PORT_IP_SEL_C 0x20F0
#define DBG_PORT_IP_SEL_C_M 0xFF0000
#define DUMMY_P09_F0_C 0x20F0
#define DUMMY_P09_F0_C_M 0xFF000000
#define DBG_CNT_SEL_C 0x20F4
#define DBG_CNT_SEL_C_M 0x1F
#define DUMMY_P09_F4_0_C 0x20F4
#define DUMMY_P09_F4_0_C_M 0xE0
#define DBG_PORT_REF_CLK_SEL_C 0x20F4
#define DBG_PORT_REF_CLK_SEL_C_M 0xFF00
#define DBG_PORT_REF_CLK_RATE_C 0x20F4
#define DBG_PORT_REF_CLK_RATE_C_M 0xFF0000
#define DBG_PORT_REF_CLK_EN_C 0x20F4
#define DBG_PORT_REF_CLK_EN_C_M 0x1000000
#define DBG32_UPD_SEL_C 0x20F4
#define DBG32_UPD_SEL_C_M 0x6000000
#define DBG_PORT_REF_CLK_SYNC_EN_C 0x20F4
#define DBG_PORT_REF_CLK_SYNC_EN_C_M 0x8000000
#define DUMMY_P09_F4_1_C 0x20F4
#define DUMMY_P09_F4_1_C_M 0xF0000000
#define DUMMY_P09_F8_C 0x20F8
#define DUMMY_P09_F8_C_M 0x7FFFFFFF
#define DBG_PORT_EN_C 0x20F8
#define DBG_PORT_EN_C_M 0x80000000
#define DBG_PORT_CKEN_TOP_C 0x20FC
#define DBG_PORT_CKEN_TOP_C_M 0x1
#define DBG_PORT_CKEN_TD_C 0x20FC
#define DBG_PORT_CKEN_TD_C_M 0x10
#define DBG_PORT_CKEN_IN_C 0x20FC
#define DBG_PORT_CKEN_IN_C_M 0x100
#define DBG_PORT_CKEN_OUT_C 0x20FC
#define DBG_PORT_CKEN_OUT_C_M 0x1000
#define DA2AD_SEL_C 0x20FC
#define DA2AD_SEL_C_M 0x2000
#define FORCE_DAC_FIFO_PATH_RST_ON_C 0x20FC
#define FORCE_DAC_FIFO_PATH_RST_ON_C_M 0xF0000
#define FORCE_DAC_FIFO_PATH_RST_C 0x20FC
#define FORCE_DAC_FIFO_PATH_RST_C_M 0xF00000
#define FORCE_ADC_FIFO_PATH_RST_ON_C 0x20FC
#define FORCE_ADC_FIFO_PATH_RST_ON_C_M 0xF000000
#define FORCE_ADC_FIFO_PATH_RST_C 0x20FC
#define FORCE_ADC_FIFO_PATH_RST_C_M 0xF0000000
#define TXBF_MEM_C 0x2214
#define TXBF_MEM_C_M 0xFFFFFFFF
#define TXBF_MEM_DIN_C 0x2218
#define TXBF_MEM_DIN_C_M 0xFFFFFFFF
#define TXBF_MEM_ADDR_C 0x221C
#define TXBF_MEM_ADDR_C_M 0xFFFFFFFF
#define TXBF_MEM_EN_C 0x2220
#define TXBF_MEM_EN_C_M 0xFFFFFFFF
#define R1B_TX_FIR_COEF0_C 0x2300
#define R1B_TX_FIR_COEF0_C_M 0xFFF
#define R1B_TX_FIR_COEF1_C 0x2300
#define R1B_TX_FIR_COEF1_C_M 0xFFF000
#define R1B_TX_FIR_SCALE_OPT_C 0x2300
#define R1B_TX_FIR_SCALE_OPT_C_M 0x3000000
#define R1B_TX_STOP_TX_C 0x2300
#define R1B_TX_STOP_TX_C_M 0x4000000
#define R1B_TX_BLOCK_TX_C 0x2300
#define R1B_TX_BLOCK_TX_C_M 0x8000000
#define R1B_TX_CONTINUOUS_TX_C 0x2300
#define R1B_TX_CONTINUOUS_TX_C_M 0x10000000
#define R1B_TX_TERMINATE_OPT_C 0x2300
#define R1B_TX_TERMINATE_OPT_C_M 0xE0000000
#define R1B_TX_FIR_COEF2_C 0x2304
#define R1B_TX_FIR_COEF2_C_M 0xFFF
#define R1B_TX_FIR_COEF3_C 0x2304
#define R1B_TX_FIR_COEF3_C_M 0xFFF000
#define R1B_TX_DUMMY_TDRDY64_OPT_C 0x2304
#define R1B_TX_DUMMY_TDRDY64_OPT_C_M 0x3000000
#define R1B_TX_DIS_SCRAMBLER_C 0x2304
#define R1B_TX_DIS_SCRAMBLER_C_M 0x4000000
#define R1B_TX_IFMOD_5M_OPT_C 0x2304
#define R1B_TX_IFMOD_5M_OPT_C_M 0x18000000
#define R1B_TX_FIR_COEF4_C 0x2308
#define R1B_TX_FIR_COEF4_C_M 0xFFF
#define R1B_TX_FIR_COEF5_C 0x2308
#define R1B_TX_FIR_COEF5_C_M 0xFFF000
#define R1B_TX_SCRAMBLER_OPT_C 0x2308
#define R1B_TX_SCRAMBLER_OPT_C_M 0xFF000000
#define R1B_TX_FIR_COEF6_C 0x230C
#define R1B_TX_FIR_COEF6_C_M 0xFFF
#define R1B_TX_FIR_COEF7_C 0x230C
#define R1B_TX_FIR_COEF7_C_M 0xFFF000
#define R1B_TX_FORCE_PATH_EN_ON_C 0x230C
#define R1B_TX_FORCE_PATH_EN_ON_C_M 0x1000000
#define R1B_TX_FORCE_PATH_EN_PATH0_C 0x230C
#define R1B_TX_FORCE_PATH_EN_PATH0_C_M 0x2000000
#define R1B_TX_FORCE_PATH_EN_PATH1_C 0x230C
#define R1B_TX_FORCE_PATH_EN_PATH1_C_M 0x4000000
#define R1B_TX_FORCE_PATH_EN_PATH2_C 0x230C
#define R1B_TX_FORCE_PATH_EN_PATH2_C_M 0x8000000
#define R1B_TX_FORCE_PATH_EN_PATH3_C 0x230C
#define R1B_TX_FORCE_PATH_EN_PATH3_C_M 0x10000000
#define R1B_TX_FIR_COEF8_C 0x2310
#define R1B_TX_FIR_COEF8_C_M 0xFFF
#define R1B_TX_FIR_COEF9_C 0x2310
#define R1B_TX_FIR_COEF9_C_M 0xFFF000
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH0_C 0x2310
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH0_C_M 0x3000000
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH1_C 0x2310
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH1_C_M 0xC000000
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH2_C 0x2310
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH2_C_M 0x30000000
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH3_C 0x2310
#define R1B_TX_DELAY_DIVERSITY_OPT_PATH3_C_M 0xC0000000
#define R1B_TX_FIR_COEFA_C 0x2314
#define R1B_TX_FIR_COEFA_C_M 0xFFF
#define R1B_TX_FIR_COEFB_C 0x2314
#define R1B_TX_FIR_COEFB_C_M 0xFFF000
#define R1B_TX_NORM_FCTR_C 0x2314
#define R1B_TX_NORM_FCTR_C_M 0x3F000000
#define R1B_TX_FIR_COEFC_C 0x2318
#define R1B_TX_FIR_COEFC_C_M 0xFFF
#define R1B_TX_FIR_COEFD_C 0x2318
#define R1B_TX_FIR_COEFD_C_M 0xFFF000
#define R1B_TX_FIR_COEFE_C 0x231C
#define R1B_TX_FIR_COEFE_C_M 0xFFF
#define R1B_TX_FIR_COEFF_C 0x231C
#define R1B_TX_FIR_COEFF_C_M 0xFFF000
#define R1B_TX_PMAC_HEADER_0_C 0x2320
#define R1B_TX_PMAC_HEADER_0_C_M 0xFFFFFFFF
#define R1B_TX_PMAC_HEADER_1_C 0x2324
#define R1B_TX_PMAC_HEADER_1_C_M 0xFFFFFFFF
#define R1B_TX_PMAC_HEADER_2_C 0x2328
#define R1B_TX_PMAC_HEADER_2_C_M 0xFFFFFFFF
#define R1B_TX_PMAC_HEADER_3_C 0x232C
#define R1B_TX_PMAC_HEADER_3_C_M 0xFFFFFFFF
#define R1B_TX_PMAC_HEADER_4_C 0x2330
#define R1B_TX_PMAC_HEADER_4_C_M 0xFFFFFFFF
#define R1B_TX_PMAC_HEADER_5_C 0x2334
#define R1B_TX_PMAC_HEADER_5_C_M 0xFFFFFFFF
#define R1B_TX_PMAC_PSDU_BYTE_C 0x2338
#define R1B_TX_PMAC_PSDU_BYTE_C_M 0x1FFFF
#define R1B_TX_PMAC_CONTINUOUS_TX_C 0x2338
#define R1B_TX_PMAC_CONTINUOUS_TX_C_M 0x20000
#define R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C 0x2338
#define R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C_M 0x40000
#define R1B_TX_PMAC_PPDU_TYPE_C 0x2338
#define R1B_TX_PMAC_PPDU_TYPE_C_M 0x80000
#define R1B_TX_PMAC_PSDU_RATE_C 0x2338
#define R1B_TX_PMAC_PSDU_RATE_C_M 0x300000
#define R1B_TX_PMAC_SERVICE_BIT2_C 0x2338
#define R1B_TX_PMAC_SERVICE_BIT2_C_M 0x400000
#define R1B_TX_PMAC_PAYLOAD_INITIAL_VAL_C 0x2338
#define R1B_TX_PMAC_PAYLOAD_INITIAL_VAL_C_M 0x7F800000
#define R1B_FPGA_LBK_EN_C 0x2338
#define R1B_FPGA_LBK_EN_C_M 0x80000000
#define R1B_RX_CS_RATIO_BW20_1R_C 0x233C
#define R1B_RX_CS_RATIO_BW20_1R_C_M 0x1F
#define R1B_RX_CS_RATIO_BW20_2R_C 0x233C
#define R1B_RX_CS_RATIO_BW20_2R_C_M 0x3E0
#define R1B_RX_CS_RATIO_BW20_3R_C 0x233C
#define R1B_RX_CS_RATIO_BW20_3R_C_M 0x7C00
#define R1B_RX_CS_RATIO_BW20_4R_C 0x233C
#define R1B_RX_CS_RATIO_BW20_4R_C_M 0xF8000
#define R1B_RX_CCA_IN_SHIFT_C 0x233C
#define R1B_RX_CCA_IN_SHIFT_C_M 0x1E00000
#define R1B_RX_PRECCA_WGT_EN_C 0x233C
#define R1B_RX_PRECCA_WGT_EN_C_M 0x2000000
#define R1B_RX_FORCE_PRECCA_WGT_EN_C 0x233C
#define R1B_RX_FORCE_PRECCA_WGT_EN_C_M 0x4000000
#define R1B_RX_CCA_SMEN_C 0x233C
#define R1B_RX_CCA_SMEN_C_M 0x8000000
#define R1B_RX_MBC_RATIO_C 0x233C
#define R1B_RX_MBC_RATIO_C_M 0x30000000
#define R1B_RX_MDC_RATIO_C 0x233C
#define R1B_RX_MDC_RATIO_C_M 0xC0000000
#define R1B_RX_CS_RATIO_BW40_1R_C 0x2340
#define R1B_RX_CS_RATIO_BW40_1R_C_M 0x1F
#define R1B_RX_CS_RATIO_BW40_2R_C 0x2340
#define R1B_RX_CS_RATIO_BW40_2R_C_M 0x3E0
#define R1B_RX_CS_RATIO_BW40_3R_C 0x2340
#define R1B_RX_CS_RATIO_BW40_3R_C_M 0x7C00
#define R1B_RX_CS_RATIO_BW40_4R_C 0x2340
#define R1B_RX_CS_RATIO_BW40_4R_C_M 0xF8000
#define R1B_RX_FORCE_PRECCA_WGT_PATH0_C 0x2340
#define R1B_RX_FORCE_PRECCA_WGT_PATH0_C_M 0x700000
#define R1B_RX_FORCE_PRECCA_WGT_PATH1_C 0x2340
#define R1B_RX_FORCE_PRECCA_WGT_PATH1_C_M 0x3800000
#define R1B_RX_FORCE_PRECCA_WGT_PATH2_C 0x2340
#define R1B_RX_FORCE_PRECCA_WGT_PATH2_C_M 0x1C000000
#define R1B_RX_FORCE_PRECCA_WGT_PATH3_C 0x2340
#define R1B_RX_FORCE_PRECCA_WGT_PATH3_C_M 0xE0000000
#define R1B_RX_DC_RATIO_BW20_1R_C 0x2344
#define R1B_RX_DC_RATIO_BW20_1R_C_M 0x1F
#define R1B_RX_DC_RATIO_BW20_2R_C 0x2344
#define R1B_RX_DC_RATIO_BW20_2R_C_M 0x3E0
#define R1B_RX_DC_RATIO_BW20_3R_C 0x2344
#define R1B_RX_DC_RATIO_BW20_3R_C_M 0x7C00
#define R1B_RX_DC_RATIO_BW20_4R_C 0x2344
#define R1B_RX_DC_RATIO_BW20_4R_C_M 0xF8000
#define R1B_RX_FORCE_DC_CMP_EN_C 0x2344
#define R1B_RX_FORCE_DC_CMP_EN_C_M 0x100000
#define R1B_RX_FORCE_DC_CMP_C 0x2344
#define R1B_RX_FORCE_DC_CMP_C_M 0x1FE00000
#define R1B_RX_MBC_WIN_C 0x2344
#define R1B_RX_MBC_WIN_C_M 0x60000000
#define R1B_RX_DIS_CCA_C 0x2344
#define R1B_RX_DIS_CCA_C_M 0x80000000
#define R1B_RX_DC_RATIO_BW40_1R_C 0x2348
#define R1B_RX_DC_RATIO_BW40_1R_C_M 0x1F
#define R1B_RX_DC_RATIO_BW40_2R_C 0x2348
#define R1B_RX_DC_RATIO_BW40_2R_C_M 0x3E0
#define R1B_RX_DC_RATIO_BW40_3R_C 0x2348
#define R1B_RX_DC_RATIO_BW40_3R_C_M 0x7C00
#define R1B_RX_DC_RATIO_BW40_4R_C 0x2348
#define R1B_RX_DC_RATIO_BW40_4R_C_M 0xF8000
#define R1B_RX_CCA_PIN_DET_OPT_C 0x2348
#define R1B_RX_CCA_PIN_DET_OPT_C_M 0x100000
#define R1B_RX_CCA_PIN_DET_TH_C 0x2348
#define R1B_RX_CCA_PIN_DET_TH_C_M 0x1FE00000
#define R1B_RX_CCS_MODE_C 0x2348
#define R1B_RX_CCS_MODE_C_M 0xE0000000
#define R1B_RX_PD_TH_BW20_1R_C 0x234C
#define R1B_RX_PD_TH_BW20_1R_C_M 0x1F
#define R1B_RX_PD_TH_BW20_2R_C 0x234C
#define R1B_RX_PD_TH_BW20_2R_C_M 0x3E0
#define R1B_RX_PD_TH_BW20_3R_C 0x234C
#define R1B_RX_PD_TH_BW20_3R_C_M 0x7C00
#define R1B_RX_PD_TH_BW20_4R_C 0x234C
#define R1B_RX_PD_TH_BW20_4R_C_M 0xF8000
#define R1B_RX_FORCE_PD_CMP_EN_C 0x234C
#define R1B_RX_FORCE_PD_CMP_EN_C_M 0x100000
#define R1B_RX_FORCE_PD_CMP_C 0x234C
#define R1B_RX_FORCE_PD_CMP_C_M 0x1FE00000
#define R1B_RX_MF_OPT_C 0x234C
#define R1B_RX_MF_OPT_C_M 0xE0000000
#define R1B_RX_PD_TH_BW40_1R_C 0x2350
#define R1B_RX_PD_TH_BW40_1R_C_M 0x1F
#define R1B_RX_PD_TH_BW40_2R_C 0x2350
#define R1B_RX_PD_TH_BW40_2R_C_M 0x3E0
#define R1B_RX_PD_TH_BW40_3R_C 0x2350
#define R1B_RX_PD_TH_BW40_3R_C_M 0x7C00
#define R1B_RX_PD_TH_BW40_4R_C 0x2350
#define R1B_RX_PD_TH_BW40_4R_C_M 0xF8000
#define R1B_RX_FORCE_ANT_CCA_EN_C 0x2350
#define R1B_RX_FORCE_ANT_CCA_EN_C_M 0x100000
#define R1B_RX_FORCE_ANT_CCA_PATH0_C 0x2350
#define R1B_RX_FORCE_ANT_CCA_PATH0_C_M 0x200000
#define R1B_RX_FORCE_ANT_CCA_PATH1_C 0x2350
#define R1B_RX_FORCE_ANT_CCA_PATH1_C_M 0x400000
#define R1B_RX_FORCE_ANT_CCA_PATH2_C 0x2350
#define R1B_RX_FORCE_ANT_CCA_PATH2_C_M 0x800000
#define R1B_RX_FORCE_ANT_CCA_PATH3_C 0x2350
#define R1B_RX_FORCE_ANT_CCA_PATH3_C_M 0x1000000
#define R1B_RX_CCA_TRIG_DLY_C 0x2350
#define R1B_RX_CCA_TRIG_DLY_C_M 0x1E000000
#define R1B_RX_NULL_POINT_IDX_OFST_C 0x2350
#define R1B_RX_NULL_POINT_IDX_OFST_C_M 0xE0000000
#define R1B_RX_BTTX_CS_RATIO_BW20_1R_C 0x2354
#define R1B_RX_BTTX_CS_RATIO_BW20_1R_C_M 0x1F
#define R1B_RX_BTTX_CS_RATIO_BW20_2R_C 0x2354
#define R1B_RX_BTTX_CS_RATIO_BW20_2R_C_M 0x3E0
#define R1B_RX_BTTX_CS_RATIO_BW20_3R_C 0x2354
#define R1B_RX_BTTX_CS_RATIO_BW20_3R_C_M 0x7C00
#define R1B_RX_BTTX_CS_RATIO_BW20_4R_C 0x2354
#define R1B_RX_BTTX_CS_RATIO_BW20_4R_C_M 0xF8000
#define R1B_RX_BTTX_CCA_TH_EN_C 0x2354
#define R1B_RX_BTTX_CCA_TH_EN_C_M 0x80000000
#define R1B_RX_BTTX_CS_RATIO_BW40_1R_C 0x2358
#define R1B_RX_BTTX_CS_RATIO_BW40_1R_C_M 0x1F
#define R1B_RX_BTTX_CS_RATIO_BW40_2R_C 0x2358
#define R1B_RX_BTTX_CS_RATIO_BW40_2R_C_M 0x3E0
#define R1B_RX_BTTX_CS_RATIO_BW40_3R_C 0x2358
#define R1B_RX_BTTX_CS_RATIO_BW40_3R_C_M 0x7C00
#define R1B_RX_BTTX_CS_RATIO_BW40_4R_C 0x2358
#define R1B_RX_BTTX_CS_RATIO_BW40_4R_C_M 0xF8000
#define R1B_RX_CCA_DIS_5M_EN_C 0x2358
#define R1B_RX_CCA_DIS_5M_EN_C_M 0x100000
#define R1B_RX_CCA_DIS_TB_OFF_C 0x2358
#define R1B_RX_CCA_DIS_TB_OFF_C_M 0x200000
#define R1B_RX_CCA_DIS_NDP_OFF_C 0x2358
#define R1B_RX_CCA_DIS_NDP_OFF_C_M 0x400000
#define R1B_RX_DAGC_TARGET_LVL_C 0x235C
#define R1B_RX_DAGC_TARGET_LVL_C_M 0x1F
#define R1B_RX_DAGC_MIN_VAL_C 0x235C
#define R1B_RX_DAGC_MIN_VAL_C_M 0x3E0
#define R1B_RX_DAGC_MAX_VAL_C 0x235C
#define R1B_RX_DAGC_MAX_VAL_C_M 0x7C00
#define R1B_RX_DAGC_STANDBY_OPT_C 0x235C
#define R1B_RX_DAGC_STANDBY_OPT_C_M 0xF8000
#define R1B_RX_DAGC_FORCE_VAL_C 0x235C
#define R1B_RX_DAGC_FORCE_VAL_C_M 0x1F00000
#define R1B_RX_DAGC_FORCE_EN_C 0x235C
#define R1B_RX_DAGC_FORCE_EN_C_M 0x2000000
#define R1B_RX_DAGC_EN_C 0x235C
#define R1B_RX_DAGC_EN_C_M 0x4000000
#define R1B_RX_DAGC_OPT_C 0x235C
#define R1B_RX_DAGC_OPT_C_M 0x8000000
#define R1B_RX_DAGC_TWO_STAGE_EN_C 0x235C
#define R1B_RX_DAGC_TWO_STAGE_EN_C_M 0x10000000
#define R1B_RX_SBD_SYMBOL_OPT_C 0x2360
#define R1B_RX_SBD_SYMBOL_OPT_C_M 0x3
#define R1B_RX_SBD_SMOOTH_EN_C 0x2360
#define R1B_RX_SBD_SMOOTH_EN_C_M 0x4
#define R1B_RX_SBD_SQUARE_EN_C 0x2360
#define R1B_RX_SBD_SQUARE_EN_C_M 0x8
#define R1B_RX_SBD_FINE_TUNE_OPT_C 0x2360
#define R1B_RX_SBD_FINE_TUNE_OPT_C_M 0x30
#define R1B_RX_SBD_FINE_TUNE_MODE_C 0x2360
#define R1B_RX_SBD_FINE_TUNE_MODE_C_M 0xC0
#define R1B_RX_SBD_RSSI_HIGH_PIN_TH_C 0x2360
#define R1B_RX_SBD_RSSI_HIGH_PIN_TH_C_M 0xFF00
#define R1B_RX_DAGC_TO_SBD_C 0x2360
#define R1B_RX_DAGC_TO_SBD_C_M 0x3F0000
#define R1B_RX_SBD_MODE_C 0x2360
#define R1B_RX_SBD_MODE_C_M 0x400000
#define R1B_RX_SBD_ANALYZER_EN_C 0x2360
#define R1B_RX_SBD_ANALYZER_EN_C_M 0x800000
#define R1B_RX_SBD_SMOOTH_FCTR_C 0x2360
#define R1B_RX_SBD_SMOOTH_FCTR_C_M 0x3000000
#define R1B_RX_SBD_ANALYZER_OPT_C 0x2360
#define R1B_RX_SBD_ANALYZER_OPT_C_M 0x4000000
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH0_C 0x2364
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH0_C_M 0x1F
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH1_C 0x2364
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH1_C_M 0x3E0
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH2_C 0x2364
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH2_C_M 0x7C00
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH3_C 0x2364
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH3_C_M 0xF8000
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH4_C 0x2364
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH4_C_M 0x1F00000
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH5_C 0x2364
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH5_C_M 0x3E000000
#define R1B_RX_ANT_WGT_EN_C 0x2364
#define R1B_RX_ANT_WGT_EN_C_M 0x40000000
#define R1B_RX_ANT_WGT_MODE_C 0x2364
#define R1B_RX_ANT_WGT_MODE_C_M 0x80000000
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH6_C 0x2368
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH6_C_M 0x1F
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH7_C 0x2368
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH7_C_M 0x3E0
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH8_C 0x2368
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH8_C_M 0x7C00
#define R1B_RX_RSSI_HIGH_PIN_TH_C 0x2368
#define R1B_RX_RSSI_HIGH_PIN_TH_C_M 0x7F8000
#define R1B_RX_ANT_WGT_NULL_CONNECT_RSSI_TH_C 0x2368
#define R1B_RX_ANT_WGT_NULL_CONNECT_RSSI_TH_C_M 0x7F800000
#define R1B_RX_ANT_WGT_EQUAL_EN_C 0x2368
#define R1B_RX_ANT_WGT_EQUAL_EN_C_M 0x80000000
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH0_C 0x236C
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH0_C_M 0x1FF
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH1_C 0x236C
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH1_C_M 0x3FE00
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH2_C 0x236C
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH2_C_M 0x7FC0000
#define R1B_RX_ANT_WGT_NULL_CONNECT_CHK_EN_C 0x236C
#define R1B_RX_ANT_WGT_NULL_CONNECT_CHK_EN_C_M 0x8000000
#define R1B_RX_ANT_WGT_FORCE_EN_C 0x236C
#define R1B_RX_ANT_WGT_FORCE_EN_C_M 0x10000000
#define R1B_RX_ANT_PW_SAVE_EN_C 0x236C
#define R1B_RX_ANT_PW_SAVE_EN_C_M 0x20000000
#define R1B_RX_MRC_OPT_C 0x236C
#define R1B_RX_MRC_OPT_C_M 0xC0000000
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH3_C 0x2370
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH3_C_M 0x1FF
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH0_C 0x2370
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH0_C_M 0x3FE00
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH1_C 0x2370
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH1_C_M 0x7FC0000
#define R1B_RX_ANT_WGT_BCC_CHK_RATIO_C 0x2370
#define R1B_RX_ANT_WGT_BCC_CHK_RATIO_C_M 0x78000000
#define R1B_RX_I_ONLY_EN_C 0x2370
#define R1B_RX_I_ONLY_EN_C_M 0x80000000
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH2_C 0x2374
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH2_C_M 0x1FF
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH3_C 0x2374
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH3_C_M 0x3FE00
#define R1B_RX_RSSI_OFST_C 0x2374
#define R1B_RX_RSSI_OFST_C_M 0x3FC0000
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_OPT_C 0x2374
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_OPT_C_M 0xC000000
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_DIS_C 0x2374
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_DIS_C_M 0x10000000
#define R1B_RX_ANT_PW_SAVE_RSSI_TH_C 0x2378
#define R1B_RX_ANT_PW_SAVE_RSSI_TH_C_M 0xFF
#define R1B_RX_LPF1_EN_C 0x2378
#define R1B_RX_LPF1_EN_C_M 0x100
#define R1B_RX_LPF1_MODE_BEFORE_CCA_C 0x2378
#define R1B_RX_LPF1_MODE_BEFORE_CCA_C_M 0x600
#define R1B_RX_LPF1_MODE_AFTER_CCA_C 0x2378
#define R1B_RX_LPF1_MODE_AFTER_CCA_C_M 0x1800
#define R1B_RX_GAIN_IS_READY_TO_EN_INTP_C 0x2378
#define R1B_RX_GAIN_IS_READY_TO_EN_INTP_C_M 0xFF0000
#define R1B_RX_INTP_UPD044_OPT_C 0x2378
#define R1B_RX_INTP_UPD044_OPT_C_M 0x1F000000
#define R1B_RX_INTP_SCO_DELAY_EN_C 0x2378
#define R1B_RX_INTP_SCO_DELAY_EN_C_M 0x20000000
#define R1B_RX_INTP_DOWNSAMPLE_PHASE_OPT_C 0x2378
#define R1B_RX_INTP_DOWNSAMPLE_PHASE_OPT_C_M 0x40000000
#define R1B_RX_RXSC_C 0x237C
#define R1B_RX_RXSC_C_M 0x1
#define R1B_RX_DCEST_EN_C 0x237C
#define R1B_RX_DCEST_EN_C_M 0x2
#define R1B_RX_DCCOMP_EN_C 0x237C
#define R1B_RX_DCCOMP_EN_C_M 0x4
#define R1B_RX_AAGC_DONE_TO_DCEST_C 0x237C
#define R1B_RX_AAGC_DONE_TO_DCEST_C_M 0x18
#define R1B_RX_DCNF_EN_C 0x237C
#define R1B_RX_DCNF_EN_C_M 0x10000
#define R1B_RX_DCNF_MODE_1_C 0x237C
#define R1B_RX_DCNF_MODE_1_C_M 0xE0000
#define R1B_RX_DCNF_MODE_2_C 0x237C
#define R1B_RX_DCNF_MODE_2_C_M 0x700000
#define R1B_RX_DCNF_MODE_3_C 0x237C
#define R1B_RX_DCNF_MODE_3_C_M 0x3800000
#define R1B_RX_LF_K1_HD_C 0x2380
#define R1B_RX_LF_K1_HD_C_M 0xFF
#define R1B_RX_LF_K1_PD_C 0x2380
#define R1B_RX_LF_K1_PD_C_M 0xFF00
#define R1B_RX_LF_K0_HD_C 0x2380
#define R1B_RX_LF_K0_HD_C_M 0xFF0000
#define R1B_RX_LF_K0_PD_C 0x2380
#define R1B_RX_LF_K0_PD_C_M 0xFF000000
#define R1B_RX_FREQ_EST_NUM_C 0x2384
#define R1B_RX_FREQ_EST_NUM_C_M 0x3
#define R1B_RX_DC_WIN_EN_C 0x2384
#define R1B_RX_DC_WIN_EN_C_M 0x4
#define R1B_RX_PHASE_COMP_EN_C 0x2384
#define R1B_RX_PHASE_COMP_EN_C_M 0x8
#define R1B_RX_PHROT_IDX_BKC_C 0x2384
#define R1B_RX_PHROT_IDX_BKC_C_M 0xF0
#define R1B_RX_PHROT_IDX_CCK_C 0x2384
#define R1B_RX_PHROT_IDX_CCK_C_M 0xF00
#define R1B_RX_SCO_QWQ_C 0x2384
#define R1B_RX_SCO_QWQ_C_M 0x8000
#define R1B_RX_SCO_EN_C 0x2384
#define R1B_RX_SCO_EN_C_M 0x10000
#define R1B_RX_SBD_TO_SCO_C 0x2384
#define R1B_RX_SBD_TO_SCO_C_M 0x60000
#define R1B_RX_SCO_PLCP_MODE_C 0x2384
#define R1B_RX_SCO_PLCP_MODE_C_M 0x80000
#define R1B_RX_SCO_PSDU_MODE_C 0x2384
#define R1B_RX_SCO_PSDU_MODE_C_M 0x300000
#define R1B_RX_SCO_BC_NON_SYNC_MODE_TH_C 0x2384
#define R1B_RX_SCO_BC_NON_SYNC_MODE_TH_C_M 0x7C00000
#define R1B_RX_SCO_CCK_NON_SYNC_MODE_TH_C 0x2384
#define R1B_RX_SCO_CCK_NON_SYNC_MODE_TH_C_M 0xF8000000
#define R1B_RX_CHEST_TARGET_TH_C 0x2388
#define R1B_RX_CHEST_TARGET_TH_C_M 0xFF
#define R1B_RX_CHEST_ANT_GAIN_DIFF_TH_C 0x2388
#define R1B_RX_CHEST_ANT_GAIN_DIFF_TH_C_M 0x1F00
#define R1B_RX_RAKE_EN_C 0x2388
#define R1B_RX_RAKE_EN_C_M 0x2000
#define R1B_RX_EQISI_EN_C 0x2388
#define R1B_RX_EQISI_EN_C_M 0x4000
#define R1B_RX_RPT_RST_C 0x2388
#define R1B_RX_RPT_RST_C_M 0x8000
#define R1B_TRX_DBG_SEL_C 0x2388
#define R1B_TRX_DBG_SEL_C_M 0x3F0000
#define R1B_DBG_PORT_SWITCH_C 0x2388
#define R1B_DBG_PORT_SWITCH_C_M 0x400000
#define R1B_RR_SEL_C 0x2388
#define R1B_RR_SEL_C_M 0x1800000
#define R1B_RXIN_MUL_OPT_C 0x2388
#define R1B_RXIN_MUL_OPT_C_M 0x6000000
#define R1B_RX_CHEST_MULTIPLY_OPT_C 0x2388
#define R1B_RX_CHEST_MULTIPLY_OPT_C_M 0x18000000
#define R1B_RX_CHEST_INVLD_SYMBOL_DOUBLE_CHK_DIS_C 0x2388
#define R1B_RX_CHEST_INVLD_SYMBOL_DOUBLE_CHK_DIS_C_M 0x20000000
#define R1B_RX_EDCCA_EN_C 0x238C
#define R1B_RX_EDCCA_EN_C_M 0x1
#define R1B_RX_FORCE_EDCCA_PATH_EN_C 0x238C
#define R1B_RX_FORCE_EDCCA_PATH_EN_C_M 0x2
#define R1B_RX_FORCE_EDCCA_PATH_C 0x238C
#define R1B_RX_FORCE_EDCCA_PATH_C_M 0xC
#define R1B_RX_EDCCA_PERIOD_C 0x238C
#define R1B_RX_EDCCA_PERIOD_C_M 0x30
#define R1B_RX_EDCCA_VLD_TH_C 0x238C
#define R1B_RX_EDCCA_VLD_TH_C_M 0xC0
#define R1B_RX_EDCCA_ENERGY_TH_C 0x238C
#define R1B_RX_EDCCA_ENERGY_TH_C_M 0xFF00
#define R1B_RX_EDCCA_OFST_C 0x238C
#define R1B_RX_EDCCA_OFST_C_M 0x1F0000
#define R1B_RX_EDCCA_WGTSEL_EN_C 0x238C
#define R1B_RX_EDCCA_WGTSEL_EN_C_M 0x200000
#define R1B_RX_EDCCA_BTTX_OFF_C 0x238C
#define R1B_RX_EDCCA_BTTX_OFF_C_M 0x400000
#define R1B_RX_EVM_TH_5M_1R_C 0x2390
#define R1B_RX_EVM_TH_5M_1R_C_M 0x1F
#define R1B_RX_EVM_TH_5M_2R_C 0x2390
#define R1B_RX_EVM_TH_5M_2R_C_M 0x3E0
#define R1B_RX_EVM_TH_5M_3R_C 0x2390
#define R1B_RX_EVM_TH_5M_3R_C_M 0x7C00
#define R1B_RX_EVM_TH_5M_4R_C 0x2390
#define R1B_RX_EVM_TH_5M_4R_C_M 0xF8000
#define R1B_RX_EVM_SIG_OPT_C 0x2390
#define R1B_RX_EVM_SIG_OPT_C_M 0x300000
#define R1B_RX_EVM_DATA_OPT_C 0x2390
#define R1B_RX_EVM_DATA_OPT_C_M 0xC00000
#define R1B_RX_EVM_SYM_C 0x2390
#define R1B_RX_EVM_SYM_C_M 0x7000000
#define R1B_RX_EVM_SCALE_C 0x2390
#define R1B_RX_EVM_SCALE_C_M 0x38000000
#define R1B_RX_EVM_ABANDON_EN_C 0x2390
#define R1B_RX_EVM_ABANDON_EN_C_M 0x40000000
#define R1B_RX_EVM_TH_11M_1R_C 0x2394
#define R1B_RX_EVM_TH_11M_1R_C_M 0x1F
#define R1B_RX_EVM_TH_11M_2R_C 0x2394
#define R1B_RX_EVM_TH_11M_2R_C_M 0x3E0
#define R1B_RX_EVM_TH_11M_3R_C 0x2394
#define R1B_RX_EVM_TH_11M_3R_C_M 0x7C00
#define R1B_RX_EVM_TH_11M_4R_C 0x2394
#define R1B_RX_EVM_TH_11M_4R_C_M 0xF8000
#define R1B_RX_EVM_BCC_OFST_C 0x2394
#define R1B_RX_EVM_BCC_OFST_C_M 0x1F00000
#define R1B_RX_EVM_CCK_OFST_C 0x2394
#define R1B_RX_EVM_CCK_OFST_C_M 0x3E000000
#define R1B_RX_DUMMY_RDRDY_OPT_C 0x2398
#define R1B_RX_DUMMY_RDRDY_OPT_C_M 0x3
#define R1B_RX_SFD_SEARCH_OPT_C 0x2398
#define R1B_RX_SFD_SEARCH_OPT_C_M 0xC
#define R1B_RX_SUPPORT_RATE_C 0x2398
#define R1B_RX_SUPPORT_RATE_C_M 0xF0
#define R1B_RX_SPOOF_LEN_C 0x2398
#define R1B_RX_SPOOF_LEN_C_M 0xFFFFF00
#define R1B_RX_SUPPORT_MAX_LEN_C 0x239C
#define R1B_RX_SUPPORT_MAX_LEN_C_M 0xFFFF
#define R1B_RX_SUPPORT_MIN_LEN_C 0x239C
#define R1B_RX_SUPPORT_MIN_LEN_C_M 0xFFFF0000
#define R1B_RX_SCOREBOARD_LEN_0_C 0x23A0
#define R1B_RX_SCOREBOARD_LEN_0_C_M 0xFFFF
#define R1B_RX_SCOREBOARD_LEN_1_C 0x23A0
#define R1B_RX_SCOREBOARD_LEN_1_C_M 0xFFFF0000
#define R1B_RX_SCOREBOARD_LEN_2_C 0x23A4
#define R1B_RX_SCOREBOARD_LEN_2_C_M 0xFFFF
#define R1B_RX_SCOREBOARD_LEN_3_C 0x23A4
#define R1B_RX_SCOREBOARD_LEN_3_C_M 0xFFFF0000
#define R1B_RX_SUICIDE_OPT_C 0x23A8
#define R1B_RX_SUICIDE_OPT_C_M 0xFF
#define R1B_RX_AIR_DELAY_BCC_C 0x23A8
#define R1B_RX_AIR_DELAY_BCC_C_M 0x7F00
#define R1B_RX_IDLE_HANG_LEN_C 0x23A8
#define R1B_RX_IDLE_HANG_LEN_C_M 0x3F8000
#define R1B_RX_SYNC_RST_LEN_C 0x23A8
#define R1B_RX_SYNC_RST_LEN_C_M 0x3C00000
#define R1B_RX_CCA_RST_LEN_C 0x23A8
#define R1B_RX_CCA_RST_LEN_C_M 0x3C000000
#define R1B_RX_RPL_OFST_C 0x23AC
#define R1B_RX_RPL_OFST_C_M 0x7F
#define R1B_RX_RPL_BW_OFST_C 0x23AC
#define R1B_RX_RPL_BW_OFST_C_M 0x180
#define R1B_RX_AGC_CCA_ILLEGAL_EN_C 0x23AC
#define R1B_RX_AGC_CCA_ILLEGAL_EN_C_M 0x200
#define R1B_RX_AGC_CCA_ILLEGAL_ST_1_C 0x23AC
#define R1B_RX_AGC_CCA_ILLEGAL_ST_1_C_M 0x3C00
#define R1B_RX_AGC_CCA_ILLEGAL_ST_2_C 0x23AC
#define R1B_RX_AGC_CCA_ILLEGAL_ST_2_C_M 0x3C000
#define R1B_RX_AGC_CCA_ILLEGAL_ST_3_C 0x23AC
#define R1B_RX_AGC_CCA_ILLEGAL_ST_3_C_M 0x3C0000
#define R1B_RX_AGC_CCA_ILLEGAL_ST_4_C 0x23AC
#define R1B_RX_AGC_CCA_ILLEGAL_ST_4_C_M 0x3C00000
#define R1B_RX_POP_MASK_SRC_OPT_C 0x23AC
#define R1B_RX_POP_MASK_SRC_OPT_C_M 0x4000000
#define R1B_RX_FAGCRDY_FIX_OFF_C 0x23AC
#define R1B_RX_FAGCRDY_FIX_OFF_C_M 0x8000000
#define R1B_RX_SCO_BC_SYNC_MODE_TH_C 0x23B0
#define R1B_RX_SCO_BC_SYNC_MODE_TH_C_M 0x7FFFF
#define R1B_RX_SCO_FPGA_DOWNRATE4_C 0x23B0
#define R1B_RX_SCO_FPGA_DOWNRATE4_C_M 0x80000
#define R1B_RX_SCO_CCK_SYNC_MODE_TH_C 0x23B4
#define R1B_RX_SCO_CCK_SYNC_MODE_TH_C_M 0x7FFFF
#define HOLD_LDPC_MIN_TIME_C 0x2400
#define HOLD_LDPC_MIN_TIME_C_M 0x3FF
#define HOLD_LDPC_MIN_TIME_EN_C 0x2400
#define HOLD_LDPC_MIN_TIME_EN_C_M 0x10000
#define RXVB_OFF_PKT_END_C 0x2404
#define RXVB_OFF_PKT_END_C_M 0x1
#define LDPC_LBK_MODE_C 0x2404
#define LDPC_LBK_MODE_C_M 0x2
#define TX_OUT_BUFFER_FSM_RD_COND_C 0x2404
#define TX_OUT_BUFFER_FSM_RD_COND_C_M 0x4
#define RX_PHY_ST_DELAY_C 0x2408
#define RX_PHY_ST_DELAY_C_M 0xFF
#define HE_TB_PLCP_BYPASS_I_C 0x2408
#define HE_TB_PLCP_BYPASS_I_C_M 0x100
#define LDPC_0_CLOCK_EN_C 0x240C
#define LDPC_0_CLOCK_EN_C_M 0x1
#define LDPC_1_CLOCK_EN_C 0x240C
#define LDPC_1_CLOCK_EN_C_M 0x2
#define DIS_NEW_REPT_ERROR_FIX_C 0x2410
#define DIS_NEW_REPT_ERROR_FIX_C_M 0x1
#define USER_TXBF_TYPE_C 0x2410
#define USER_TXBF_TYPE_C_M 0x10
#define DIS_TX_HE_RU26_FLAG_C 0x2410
#define DIS_TX_HE_RU26_FLAG_C_M 0x100
#define TX_HE_RU26_ACTIVE_FLAG_C 0x2410
#define TX_HE_RU26_ACTIVE_FLAG_C_M 0x1000
#define PATH1_R_DAC_QINV_C 0x3000
#define PATH1_R_DAC_QINV_C_M 0x1
#define PATH1_R_FIFO_CLR_ENB_C 0x3000
#define PATH1_R_FIFO_CLR_ENB_C_M 0x10
#define PATH1_R_T2F_FREERUN_BUF_EN_C 0x3004
#define PATH1_R_T2F_FREERUN_BUF_EN_C_M 0x1
#define PATH1_R_T2F_L1_LATE_EN_C 0x3004
#define PATH1_R_T2F_L1_LATE_EN_C_M 0x2
#define PATH1_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C 0x3004
#define PATH1_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C_M 0x10
#define PATH1_R_T2F_DCCL_FILT_EN_C 0x3004
#define PATH1_R_T2F_DCCL_FILT_EN_C_M 0x100
#define PATH1_R_BT_GNT_RXTD_LATCH_EN_C 0x3004
#define PATH1_R_BT_GNT_RXTD_LATCH_EN_C_M 0x1000
#define PATH1_R_TD_CLK_GCK_EN_C 0x3008
#define PATH1_R_TD_CLK_GCK_EN_C_M 0x1
#define PATH1_R_1RCCA_CLK_GCK_ON_C 0x3008
#define PATH1_R_1RCCA_CLK_GCK_ON_C_M 0x10
#define PATH1_R_SYNC_RST_EN_TD_PATH_C 0x300C
#define PATH1_R_SYNC_RST_EN_TD_PATH_C_M 0x1
#define PATH1_R_SYNC_RST_EN_FFT_C 0x300C
#define PATH1_R_SYNC_RST_EN_FFT_C_M 0x10
#define PATH1_R_SYNC_RST_EN_TXBUF_C 0x300C
#define PATH1_R_SYNC_RST_EN_TXBUF_C_M 0x100
#define PATH1_R_SYNC_RST_EN_RXBUF_C 0x300C
#define PATH1_R_SYNC_RST_EN_RXBUF_C_M 0x1000
#define PATH1_R_SYNC_RST_EN_DCCL_C 0x300C
#define PATH1_R_SYNC_RST_EN_DCCL_C_M 0x10000
#define PATH1_R_SYNC_RST_EN_T2F_C 0x300C
#define PATH1_R_SYNC_RST_EN_T2F_C_M 0x100000
#define PATH1_R_SYNC_RST_EN_RXFIR_COMP_C 0x300C
#define PATH1_R_SYNC_RST_EN_RXFIR_COMP_C_M 0x1000000
#define PATH1_R_DCCL_CFO_TH_EN_C 0x3010
#define PATH1_R_DCCL_CFO_TH_EN_C_M 0x1
#define PATH1_R_DCCL_52B_SYMB_TH_EN_C 0x3010
#define PATH1_R_DCCL_52B_SYMB_TH_EN_C_M 0x10
#define PATH1_R_DCCL_52B_SYMB_TH_SEL_C 0x3010
#define PATH1_R_DCCL_52B_SYMB_TH_SEL_C_M 0x20
#define PATH1_R_TX_STO_TRIG_SELECT_C 0x3014
#define PATH1_R_TX_STO_TRIG_SELECT_C_M 0x1
#define PATH1_R_TX_STO_FIRST_PE_SELECT_C 0x3014
#define PATH1_R_TX_STO_FIRST_PE_SELECT_C_M 0x2
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_L_C_M 0x7
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_L_C_M 0x70
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_L_C_M 0x700
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_L_C_M 0x7000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_L_C_M 0x70000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_L_C_M 0x700000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_L_C_M 0x7000000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_L_C 0x3018
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_L_C_M 0x70000000
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_L_C 0x301C
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_L_C_M 0x8
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C 0x301C
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C_M 0x10
#define PATH1_R_STO_INT_SEL_L_C 0x301C
#define PATH1_R_STO_INT_SEL_L_C_M 0x20
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C 0x301C
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C_M 0x380
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_L_C 0x301C
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_L_C_M 0x400
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_L_C 0x301C
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_L_C_M 0x800
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_L_C 0x301C
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_L_C_M 0x1000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HT_C_M 0x7
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HT_C_M 0x70
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HT_C_M 0x700
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HT_C_M 0x7000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HT_C_M 0x70000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HT_C_M 0x700000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HT_C_M 0x7000000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HT_C 0x3020
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HT_C_M 0x70000000
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HT_C 0x3024
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HT_C_M 0x8
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C 0x3024
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C_M 0x10
#define PATH1_R_STO_INT_SEL_HT_C 0x3024
#define PATH1_R_STO_INT_SEL_HT_C_M 0x20
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C 0x3024
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C_M 0x380
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HT_C 0x3024
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HT_C_M 0x400
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HT_C 0x3024
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HT_C_M 0x800
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HT_C 0x3024
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HT_C_M 0x1000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_VHT_C_M 0x7
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_VHT_C_M 0x70
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_VHT_C_M 0x700
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_VHT_C_M 0x7000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_VHT_C_M 0x70000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_VHT_C_M 0x700000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_VHT_C_M 0x7000000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_VHT_C 0x3028
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_VHT_C_M 0x70000000
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_VHT_C 0x302C
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_VHT_C_M 0x8
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C 0x302C
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C_M 0x10
#define PATH1_R_STO_INT_SEL_VHT_C 0x302C
#define PATH1_R_STO_INT_SEL_VHT_C_M 0x20
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C 0x302C
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C_M 0x380
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C 0x302C
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C_M 0x400
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C 0x302C
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C_M 0x800
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C 0x302C
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C_M 0x1000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HE_C_M 0x7
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HE_C_M 0x70
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HE_C_M 0x700
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HE_C_M 0x7000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HE_C_M 0x70000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HE_C_M 0x700000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HE_C_M 0x7000000
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HE_C 0x3030
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HE_C_M 0x70000000
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HE_C 0x3034
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HE_C_M 0x8
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C 0x3034
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C_M 0x10
#define PATH1_R_STO_INT_SEL_HE_C 0x3034
#define PATH1_R_STO_INT_SEL_HE_C_M 0x20
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C 0x3034
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C_M 0x380
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HE_C 0x3034
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HE_C_M 0x400
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HE_C 0x3034
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HE_C_M 0x800
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HE_C 0x3034
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HE_C_M 0x1000
#define PATH1_R_HW_SI_READ_ADDR_C 0x3200
#define PATH1_R_HW_SI_READ_ADDR_C_M 0xFF
#define PATH1_R_HW_SI_READ_EDGE_OPT_C 0x3200
#define PATH1_R_HW_SI_READ_EDGE_OPT_C_M 0x300
#define PATH1_R_HW_SI_ZERO_PADDING_EN_C 0x3200
#define PATH1_R_HW_SI_ZERO_PADDING_EN_C_M 0x8000
#define PATH1_R_HW_SI_BYPASS_ST_MASK_C 0x3200
#define PATH1_R_HW_SI_BYPASS_ST_MASK_C_M 0x10000
#define PATH1_R_HW_SI_DATA_E_INV_C 0x3200
#define PATH1_R_HW_SI_DATA_E_INV_C_M 0x20000
#define PATH1_R_HW_SI_SEL_DBG_C 0x3200
#define PATH1_R_HW_SI_SEL_DBG_C_M 0xC0000
#define PATH1_R_HW_SI_DBG_MODE_C 0x3200
#define PATH1_R_HW_SI_DBG_MODE_C_M 0x100000
#define PATH1_R_HW_SI_ZERO_PADDING_NUM_C 0x3200
#define PATH1_R_HW_SI_ZERO_PADDING_NUM_C_M 0x3E00000
#define PATH1_R_HW_SI_DBG_TX_TRIG_C 0x3200
#define PATH1_R_HW_SI_DBG_TX_TRIG_C_M 0x4000000
#define PATH1_R_HW_SI_DIS_W_RX_TRIG_C 0x3200
#define PATH1_R_HW_SI_DIS_W_RX_TRIG_C_M 0x10000000
#define PATH1_R_HW_SI_DIS_W_TX_TRIG_C 0x3200
#define PATH1_R_HW_SI_DIS_W_TX_TRIG_C_M 0x20000000
#define PATH1_R_HW_SI_DIS_R_TRIG_C 0x3200
#define PATH1_R_HW_SI_DIS_R_TRIG_C_M 0x40000000
#define PATH1_R_HW_SI_DBG_RX_CMD_0_C 0x3204
#define PATH1_R_HW_SI_DBG_RX_CMD_0_C_M 0xFFFF
#define PATH1_R_HW_SI_DBG_RX_CMD_1_C 0x3204
#define PATH1_R_HW_SI_DBG_RX_CMD_1_C_M 0xFFFF0000
#define PATH1_R_HW_SI_DBG_TX_CMD_0_C 0x3208
#define PATH1_R_HW_SI_DBG_TX_CMD_0_C_M 0xFFFF
#define PATH1_R_HW_SI_DBG_TX_CMD_1_C 0x3208
#define PATH1_R_HW_SI_DBG_TX_CMD_1_C_M 0xFFFF0000
#define PATH1_R_ANAPAR_ST1P5_SEL_C 0x320C
#define PATH1_R_ANAPAR_ST1P5_SEL_C_M 0xF
#define PATH1_R_ANAPAR_ST3P5_SEL_C 0x320C
#define PATH1_R_ANAPAR_ST3P5_SEL_C_M 0xF0
#define PATH1_R_ANAPAR_DIS_TSSI_DCK_ST_C 0x320C
#define PATH1_R_ANAPAR_DIS_TSSI_DCK_ST_C_M 0x80000000
#define PATH1_R_RFMODE_RSTB_EQ0_EN_C 0x3210
#define PATH1_R_RFMODE_RSTB_EQ0_EN_C_M 0x1
#define PATH1_R_PW_RSTB_EQ0_EN_C 0x3210
#define PATH1_R_PW_RSTB_EQ0_EN_C_M 0x2
#define PATH1_R_RSTB_EQ0_EN_C 0x3210
#define PATH1_R_RSTB_EQ0_EN_C_M 0x4
#define PATH1_R_RFMODE_RSTB_EQ0_C 0x3210
#define PATH1_R_RFMODE_RSTB_EQ0_C_M 0xF0
#define PATH1_R_PW_RSTB_EQ0_C 0x3210
#define PATH1_R_PW_RSTB_EQ0_C_M 0xFF00
#define PATH1_R_RSTB_EQ0_C 0x3210
#define PATH1_R_RSTB_EQ0_C_M 0xFFFF0000
#define PATH1_R_RFC_SI_SEL_0_C 0x3214
#define PATH1_R_RFC_SI_SEL_0_C_M 0x1
#define PATH1_R_RFC_SI_SEL_1_C 0x3214
#define PATH1_R_RFC_SI_SEL_1_C_M 0x10
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_EN_C 0x3218
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_EN_C_M 0x1
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_EN_C 0x3218
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_EN_C_M 0x2
#define PATH1_R_HW_SI_R_TRIG_DLY_EN_C 0x3218
#define PATH1_R_HW_SI_R_TRIG_DLY_EN_C_M 0x4
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_C 0x3218
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_C_M 0xF0
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_C 0x3218
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_C_M 0xF00
#define PATH1_R_HW_SI_R_TRIG_DLY_C 0x3218
#define PATH1_R_HW_SI_R_TRIG_DLY_C_M 0xF000
#define PATH1_R_ANAPAR_RST_SEL_C 0x32A0
#define PATH1_R_ANAPAR_RST_SEL_C_M 0xF
#define PATH1_R_ANAPAR_RST_TX_SEL_C 0x32A0
#define PATH1_R_ANAPAR_RST_TX_SEL_C_M 0xF0
#define PATH1_R_ANAPAR_CTSDM_131_128__C 0x32A0
#define PATH1_R_ANAPAR_CTSDM_131_128__C_M 0xF00
#define PATH1_R_TXCK_FORCE_VAL_C 0x32A0
#define PATH1_R_TXCK_FORCE_VAL_C_M 0x7000
#define PATH1_R_TXCK_FORCE_ON_C 0x32A0
#define PATH1_R_TXCK_FORCE_ON_C_M 0x8000
#define PATH1_R_RXCK_FORCE_VAL_C 0x32A0
#define PATH1_R_RXCK_FORCE_VAL_C_M 0x70000
#define PATH1_R_RXCK_FORCE_ON_C 0x32A0
#define PATH1_R_RXCK_FORCE_ON_C_M 0x80000
#define PATH1_R_RXCK_RFBW0_C 0x32A0
#define PATH1_R_RXCK_RFBW0_C_M 0x700000
#define PATH1_R_RXCK_RFBW1_C 0x32A0
#define PATH1_R_RXCK_RFBW1_C_M 0x3800000
#define PATH1_R_RXCK_RFBW2_C 0x32A0
#define PATH1_R_RXCK_RFBW2_C_M 0x1C000000
#define PATH1_R_RXCK_RFBW3_C 0x32A0
#define PATH1_R_RXCK_RFBW3_C_M 0xE0000000
#define PATH1_R_RXCK_RFBW4_C 0x32A4
#define PATH1_R_RXCK_RFBW4_C_M 0x7
#define PATH1_R_RXCK_RFBW5_C 0x32A4
#define PATH1_R_RXCK_RFBW5_C_M 0x38
#define PATH1_R_RXCK_RFBW6_C 0x32A4
#define PATH1_R_RXCK_RFBW6_C_M 0x1C0
#define PATH1_R_TXCK_RFBW0_C 0x32A4
#define PATH1_R_TXCK_RFBW0_C_M 0x3800
#define PATH1_R_TXCK_RFBW1_C 0x32A4
#define PATH1_R_TXCK_RFBW1_C_M 0x1C000
#define PATH1_R_TXCK_RFBW2_C 0x32A4
#define PATH1_R_TXCK_RFBW2_C_M 0xE0000
#define PATH1_R_TXCK_RFBW3_C 0x32A4
#define PATH1_R_TXCK_RFBW3_C_M 0x700000
#define PATH1_R_TXCK_RFBW4_C 0x32A4
#define PATH1_R_TXCK_RFBW4_C_M 0x3800000
#define PATH1_R_TXCK_RFBW5_C 0x32A4
#define PATH1_R_TXCK_RFBW5_C_M 0x1C000000
#define PATH1_R_TXCK_RFBW6_C 0x32A4
#define PATH1_R_TXCK_RFBW6_C_M 0xE0000000
#define PATH1_R_EN_RXCK_TX_C 0x32A8
#define PATH1_R_EN_RXCK_TX_C_M 0x1
#define PATH1_R_RXCK_TX_C 0x32A8
#define PATH1_R_RXCK_TX_C_M 0xE
#define PATH1_R_RXCK_TX_FTM_C 0x32A8
#define PATH1_R_RXCK_TX_FTM_C_M 0x70
#define PATH1_R_CLK_RFC_GCK_EN_C 0x32A8
#define PATH1_R_CLK_RFC_GCK_EN_C_M 0x80
#define PATH1_R_RF0_GEN_DBG_SEL_C 0x32A8
#define PATH1_R_RF0_GEN_DBG_SEL_C_M 0x300
#define PATH1_R_RFMODE_GNT_WL_DIS_TX_OPT_C 0x32A8
#define PATH1_R_RFMODE_GNT_WL_DIS_TX_OPT_C_M 0x800
#define PATH1_R_RFAFE_PWSAV_EN_C 0x32A8
#define PATH1_R_RFAFE_PWSAV_EN_C_M 0xF000
#define PATH1_R_RFMODE_ORI_RXB_OFF_C 0x32A8
#define PATH1_R_RFMODE_ORI_RXB_OFF_C_M 0xF0000
#define PATH1_R_RFMODE_ORI_RXB_LOWPW_C 0x32A8
#define PATH1_R_RFMODE_ORI_RXB_LOWPW_C_M 0xF00000
#define PATH1_R_RFMODE_FTM_RXB_OFF_C 0x32A8
#define PATH1_R_RFMODE_FTM_RXB_OFF_C_M 0xF000000
#define PATH1_R_RFMODE_FTM_RXB_LOWPW_C 0x32A8
#define PATH1_R_RFMODE_FTM_RXB_LOWPW_C_M 0xF0000000
#define PATH1_R_RSTB_3WIRE_C 0x32AC
#define PATH1_R_RSTB_3WIRE_C_M 0x1
#define PATH1_R_EN_NRBW_AT_TX_C 0x32AC
#define PATH1_R_EN_NRBW_AT_TX_C_M 0x4
#define PATH1_R_RFMODE_ORI_TX_C 0x32AC
#define PATH1_R_RFMODE_ORI_TX_C_M 0xF0
#define PATH1_R_RFMODE_ORI_TX_TXOFF_C 0x32AC
#define PATH1_R_RFMODE_ORI_TX_TXOFF_C_M 0xF00
#define PATH1_R_RFMODE_ORI_RX_OFDM_CCA_C 0x32AC
#define PATH1_R_RFMODE_ORI_RX_OFDM_CCA_C_M 0xF000
#define PATH1_R_RFMODE_ORI_RX_CCK_CCA_C 0x32AC
#define PATH1_R_RFMODE_ORI_RX_CCK_CCA_C_M 0xF0000
#define PATH1_R_RFMODE_ORI_RX_IDLE_C 0x32AC
#define PATH1_R_RFMODE_ORI_RX_IDLE_C_M 0xF00000
#define PATH1_R_RFMODE_FTM_TX_C 0x32AC
#define PATH1_R_RFMODE_FTM_TX_C_M 0xF000000
#define PATH1_R_RFMODE_FTM_TX_TXOFF_C 0x32AC
#define PATH1_R_RFMODE_FTM_TX_TXOFF_C_M 0xF0000000
#define PATH1_R_RFMODE_FTM_RX_OFDM_CCA_C 0x32B0
#define PATH1_R_RFMODE_FTM_RX_OFDM_CCA_C_M 0xF
#define PATH1_R_RFMODE_FTM_RX_CCK_CCA_C 0x32B0
#define PATH1_R_RFMODE_FTM_RX_CCK_CCA_C_M 0xF0
#define PATH1_R_RFMODE_FTM_RX_IDLE_C 0x32B0
#define PATH1_R_RFMODE_FTM_RX_IDLE_C_M 0xF00
#define PATH1_R_RXB_IDX_AT_TX_C 0x32B0
#define PATH1_R_RXB_IDX_AT_TX_C_M 0x1F000
#define PATH1_R_TIA_IDX_AT_TX_C 0x32B0
#define PATH1_R_TIA_IDX_AT_TX_C_M 0x20000
#define PATH1_R_LNA_IDX_AT_TX_C 0x32B0
#define PATH1_R_LNA_IDX_AT_TX_C_M 0x1C0000
#define PATH1_R_TIA_EXT_BW_AT_TX_C 0x32B0
#define PATH1_R_TIA_EXT_BW_AT_TX_C_M 0x200000
#define PATH1_R_SI_RADDR_C 0x32B0
#define PATH1_R_SI_RADDR_C_M 0x3FC00000
#define PATH1_R_RST_3WIRE_CONFLICT_CNT_C 0x32B0
#define PATH1_R_RST_3WIRE_CONFLICT_CNT_C_M 0x80000000
#define PATH1_R_SOFT3WIRE_DATA_C 0x32B4
#define PATH1_R_SOFT3WIRE_DATA_C_M 0xFFFFFFF
#define PATH1_R_TXAGC_AT_SLEEP_C 0x32B8
#define PATH1_R_TXAGC_AT_SLEEP_C_M 0x3F
#define PATH1_R_RXB_IDX_AT_SLEEP_C 0x32B8
#define PATH1_R_RXB_IDX_AT_SLEEP_C_M 0x7C0
#define PATH1_R_TIA_IDX_AT_SLEEP_C 0x32B8
#define PATH1_R_TIA_IDX_AT_SLEEP_C_M 0x800
#define PATH1_R_LNA_IDX_AT_SLEEP_C 0x32B8
#define PATH1_R_LNA_IDX_AT_SLEEP_C_M 0x7000
#define PATH1_R_TIA_EXT_BW_AT_SLEEP_C 0x32B8
#define PATH1_R_TIA_EXT_BW_AT_SLEEP_C_M 0x8000
#define PATH1_R_EN_NRBW_AT_SLEEP_C 0x32B8
#define PATH1_R_EN_NRBW_AT_SLEEP_C_M 0x10000
#define PATH1_R_RFMODE_AT_SLEEP_C 0x32B8
#define PATH1_R_RFMODE_AT_SLEEP_C_M 0x1E0000
#define PATH1_R_TXAGC_BYPASS_C 0x32B8
#define PATH1_R_TXAGC_BYPASS_C_M 0x200000
#define PATH1_R_RXB_BYPASS_C 0x32B8
#define PATH1_R_RXB_BYPASS_C_M 0x400000
#define PATH1_R_TIA_BYPASS_C 0x32B8
#define PATH1_R_TIA_BYPASS_C_M 0x800000
#define PATH1_R_LNA_BYPASS_C 0x32B8
#define PATH1_R_LNA_BYPASS_C_M 0x1000000
#define PATH1_R_TIA_EXT_BYPASS_C 0x32B8
#define PATH1_R_TIA_EXT_BYPASS_C_M 0x2000000
#define PATH1_R_EN_NRBW_BYPASS_C 0x32B8
#define PATH1_R_EN_NRBW_BYPASS_C_M 0x4000000
#define PATH1_R_RFREG_DIS_GATING_C 0x32B8
#define PATH1_R_RFREG_DIS_GATING_C_M 0x8000000
#define PATH1_R_RSTB_ANAPAR_C 0x32B8
#define PATH1_R_RSTB_ANAPAR_C_M 0x10000000
#define PATH1_R_ANAPAR_SEL_OPT_C 0x32B8
#define PATH1_R_ANAPAR_SEL_OPT_C_M 0x20000000
#define PATH1_R_ANAPAR_DBG_MODE_C 0x32B8
#define PATH1_R_ANAPAR_DBG_MODE_C_M 0x40000000
#define PATH1_R_ANAPAR_DIS_GATING_C 0x32B8
#define PATH1_R_ANAPAR_DIS_GATING_C_M 0x80000000
#define PATH1_R_ANAPAR_ST0_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST0_SEL_C_M 0xF
#define PATH1_R_ANAPAR_ST1_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST1_SEL_C_M 0xF0
#define PATH1_R_ANAPAR_ST2_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST2_SEL_C_M 0xF00
#define PATH1_R_ANAPAR_ST3_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST3_SEL_C_M 0xF000
#define PATH1_R_ANAPAR_ST4_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST4_SEL_C_M 0xF0000
#define PATH1_R_ANAPAR_ST5_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST5_SEL_C_M 0xF00000
#define PATH1_R_ANAPAR_ST6_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST6_SEL_C_M 0xF000000
#define PATH1_R_ANAPAR_ST7_SEL_C 0x32BC
#define PATH1_R_ANAPAR_ST7_SEL_C_M 0xF0000000
#define PATH1_R_ANAPAR_ST8_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST8_SEL_C_M 0xF
#define PATH1_R_ANAPAR_ST9_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST9_SEL_C_M 0xF0
#define PATH1_R_ANAPAR_ST10_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST10_SEL_C_M 0xF00
#define PATH1_R_ANAPAR_ST11_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST11_SEL_C_M 0xF000
#define PATH1_R_ANAPAR_ST12_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST12_SEL_C_M 0xF0000
#define PATH1_R_ANAPAR_ST13_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST13_SEL_C_M 0xF00000
#define PATH1_R_ANAPAR_ST14_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST14_SEL_C_M 0xF000000
#define PATH1_R_ANAPAR_ST15_SEL_C 0x32C0
#define PATH1_R_ANAPAR_ST15_SEL_C_M 0xF0000000
#define PATH1_R_ANAPAR_ST16_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST16_SEL_C_M 0xF
#define PATH1_R_ANAPAR_ST17_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST17_SEL_C_M 0xF0
#define PATH1_R_ANAPAR_ST18_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST18_SEL_C_M 0xF00
#define PATH1_R_ANAPAR_ST19_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST19_SEL_C_M 0xF000
#define PATH1_R_ANAPAR_ST20_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST20_SEL_C_M 0xF0000
#define PATH1_R_ANAPAR_ST21_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST21_SEL_C_M 0xF00000
#define PATH1_R_ANAPAR_ST22_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST22_SEL_C_M 0xF000000
#define PATH1_R_ANAPAR_ST23_SEL_C 0x32C4
#define PATH1_R_ANAPAR_ST23_SEL_C_M 0xF0000000
#define PATH1_R_ANAPAR_ST24_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST24_SEL_C_M 0xF
#define PATH1_R_ANAPAR_ST25_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST25_SEL_C_M 0xF0
#define PATH1_R_ANAPAR_ST26_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST26_SEL_C_M 0xF00
#define PATH1_R_ANAPAR_ST27_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST27_SEL_C_M 0xF000
#define PATH1_R_ANAPAR_ST28_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST28_SEL_C_M 0xF0000
#define PATH1_R_ANAPAR_ST29_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST29_SEL_C_M 0xF00000
#define PATH1_R_ANAPAR_ST30_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST30_SEL_C_M 0xF000000
#define PATH1_R_ANAPAR_ST31_SEL_C 0x32C8
#define PATH1_R_ANAPAR_ST31_SEL_C_M 0xF0000000
#define PATH1_R_ANAPAR_CTSDM_31_0__C 0x32CC
#define PATH1_R_ANAPAR_CTSDM_31_0__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_CTSDM_63_32__C 0x32D0
#define PATH1_R_ANAPAR_CTSDM_63_32__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_CTSDM_95_64__C 0x32D4
#define PATH1_R_ANAPAR_CTSDM_95_64__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_CTSDM_127_96__C 0x32D8
#define PATH1_R_ANAPAR_CTSDM_127_96__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_31_0__C 0x32DC
#define PATH1_R_ANAPAR_31_0__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_63_32__C 0x32E0
#define PATH1_R_ANAPAR_63_32__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_95_64__C 0x32E4
#define PATH1_R_ANAPAR_95_64__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_127_96__C 0x32E8
#define PATH1_R_ANAPAR_127_96__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_143_128__C 0x32EC
#define PATH1_R_ANAPAR_143_128__C_M 0xFFFF
#define PATH1_R_ANAPAR_LBK_15_0__C 0x32EC
#define PATH1_R_ANAPAR_LBK_15_0__C_M 0xFFFF0000
#define PATH1_R_ANAPAR_LBK_47_16__C 0x32F0
#define PATH1_R_ANAPAR_LBK_47_16__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_LBK_79_48__C 0x32F4
#define PATH1_R_ANAPAR_LBK_79_48__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_LBK_111_80__C 0x32F8
#define PATH1_R_ANAPAR_LBK_111_80__C_M 0xFFFFFFFF
#define PATH1_R_ANAPAR_LBK_143_112__C 0x32FC
#define PATH1_R_ANAPAR_LBK_143_112__C_M 0xFFFFFFFF
#define PATH1_TSSI_DBG_PORT_C 0x3C00
#define PATH1_TSSI_DBG_PORT_C_M 0xFFFFFFFF
#define PATH1_DCK_AUTO_AVG_DC_C 0x3C04
#define PATH1_DCK_AUTO_AVG_DC_C_M 0xFFF000
#define PATH1_HE_LSTF_PW_OFST_C 0x3C04
#define PATH1_HE_LSTF_PW_OFST_C_M 0xFF000000
#define PATH1_DCK_AUTO_MAX_DC_C 0x3C08
#define PATH1_DCK_AUTO_MAX_DC_C_M 0xFFF
#define PATH1_DCK_AUTO_MIN_DC_C 0x3C08
#define PATH1_DCK_AUTO_MIN_DC_C_M 0xFFF000
#define PATH1_TMETER_F_C 0x3C08
#define PATH1_TMETER_F_C_M 0xFF000000
#define PATH1_TSSI_AVG_R_C 0x3C10
#define PATH1_TSSI_AVG_R_C_M 0xFFF
#define PATH1_TSSI_MAX_R_C 0x3C10
#define PATH1_TSSI_MAX_R_C_M 0xFFF000
#define PATH1_TSSI_F_NOW_C 0x3C10
#define PATH1_TSSI_F_NOW_C_M 0xFF000000
#define PATH1_TSSI_MID_R_C 0x3C14
#define PATH1_TSSI_MID_R_C_M 0xFFF
#define PATH1_TSSI_LAST_R_C 0x3C14
#define PATH1_TSSI_LAST_R_C_M 0xFFF000
#define PATH1_GAIN_TX_IPA_MX_C 0x3C14
#define PATH1_GAIN_TX_IPA_MX_C_M 0x7000000
#define PATH1_TSSI_VAL_AVG_C 0x3C18
#define PATH1_TSSI_VAL_AVG_C_M 0x3FF
#define PATH1_TSSI_VAL_AVG_OUT_VLD_C 0x3C18
#define PATH1_TSSI_VAL_AVG_OUT_VLD_C_M 0x10000
#define PATH1_ADC_RE_C 0x3C18
#define PATH1_ADC_RE_C_M 0xFFF00000
#define PATH1_TSSI_VAL_D00_C 0x3C1C
#define PATH1_TSSI_VAL_D00_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_0_C 0x3C1C
#define PATH1_TSSI_VAL_VLD_IDX_0_C_M 0x8000
#define PATH1_TSSI_VAL_D01_C 0x3C1C
#define PATH1_TSSI_VAL_D01_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_1_C 0x3C1C
#define PATH1_TSSI_VAL_VLD_IDX_1_C_M 0x80000000
#define PATH1_TSSI_VAL_D02_C 0x3C20
#define PATH1_TSSI_VAL_D02_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_2_C 0x3C20
#define PATH1_TSSI_VAL_VLD_IDX_2_C_M 0x8000
#define PATH1_TSSI_VAL_D03_C 0x3C20
#define PATH1_TSSI_VAL_D03_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_3_C 0x3C20
#define PATH1_TSSI_VAL_VLD_IDX_3_C_M 0x80000000
#define PATH1_TSSI_VAL_D04_C 0x3C24
#define PATH1_TSSI_VAL_D04_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_4_C 0x3C24
#define PATH1_TSSI_VAL_VLD_IDX_4_C_M 0x8000
#define PATH1_TSSI_VAL_D05_C 0x3C24
#define PATH1_TSSI_VAL_D05_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_5_C 0x3C24
#define PATH1_TSSI_VAL_VLD_IDX_5_C_M 0x80000000
#define PATH1_TSSI_VAL_D06_C 0x3C28
#define PATH1_TSSI_VAL_D06_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_6_C 0x3C28
#define PATH1_TSSI_VAL_VLD_IDX_6_C_M 0x8000
#define PATH1_TSSI_VAL_D07_C 0x3C28
#define PATH1_TSSI_VAL_D07_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_7_C 0x3C28
#define PATH1_TSSI_VAL_VLD_IDX_7_C_M 0x80000000
#define PATH1_TSSI_VAL_D08_C 0x3C2C
#define PATH1_TSSI_VAL_D08_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_8_C 0x3C2C
#define PATH1_TSSI_VAL_VLD_IDX_8_C_M 0x8000
#define PATH1_TSSI_VAL_D09_C 0x3C2C
#define PATH1_TSSI_VAL_D09_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_9_C 0x3C2C
#define PATH1_TSSI_VAL_VLD_IDX_9_C_M 0x80000000
#define PATH1_TSSI_VAL_D10_C 0x3C30
#define PATH1_TSSI_VAL_D10_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_10_C 0x3C30
#define PATH1_TSSI_VAL_VLD_IDX_10_C_M 0x8000
#define PATH1_TSSI_VAL_D11_C 0x3C30
#define PATH1_TSSI_VAL_D11_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_11_C 0x3C30
#define PATH1_TSSI_VAL_VLD_IDX_11_C_M 0x80000000
#define PATH1_TSSI_VAL_D12_C 0x3C34
#define PATH1_TSSI_VAL_D12_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_12_C 0x3C34
#define PATH1_TSSI_VAL_VLD_IDX_12_C_M 0x8000
#define PATH1_TSSI_VAL_D13_C 0x3C34
#define PATH1_TSSI_VAL_D13_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_13_C 0x3C34
#define PATH1_TSSI_VAL_VLD_IDX_13_C_M 0x80000000
#define PATH1_TSSI_VAL_D14_C 0x3C38
#define PATH1_TSSI_VAL_D14_C_M 0x3FF
#define PATH1_TSSI_VAL_VLD_IDX_14_C 0x3C38
#define PATH1_TSSI_VAL_VLD_IDX_14_C_M 0x8000
#define PATH1_TSSI_VAL_D15_C 0x3C38
#define PATH1_TSSI_VAL_D15_C_M 0x3FF0000
#define PATH1_TSSI_VAL_VLD_IDX_15_C 0x3C38
#define PATH1_TSSI_VAL_VLD_IDX_15_C_M 0x80000000
#define PATH1_TSSI_OSCILLATION_CNT_C 0x3C3C
#define PATH1_TSSI_OSCILLATION_CNT_C_M 0xFFFF
#define PATH1_TSSI_VAL_VLD_IDX_C 0x3C3C
#define PATH1_TSSI_VAL_VLD_IDX_C_M 0xFFFF0000
#define PATH1_PRE_TXAGC_OFST_C 0x3C40
#define PATH1_PRE_TXAGC_OFST_C_M 0xFF00
#define PATH1_DELTA_TSSI_PW_C 0x3C40
#define PATH1_DELTA_TSSI_PW_C_M 0xFF0000
#define PATH1SWING_MIN_C 0x3C40
#define PATH1SWING_MIN_C_M 0xF000000
#define PATH1SWING_MAX_C 0x3C40
#define PATH1SWING_MAX_C_M 0xF0000000
#define PATH1_TSSI_C_RAW0_C 0x3C44
#define PATH1_TSSI_C_RAW0_C_M 0x1FF000
#define PATH1_TSSI_F_C 0x3C48
#define PATH1_TSSI_F_C_M 0xFF
#define PATH1_TSSI_G_C 0x3C48
#define PATH1_TSSI_G_C_M 0x3FF00
#define PATH1_TSSI_S_C 0x3C48
#define PATH1_TSSI_S_C_M 0x1FF00000
#define PATH1_AVG_R_SQUARE_C 0x3C4C
#define PATH1_AVG_R_SQUARE_C_M 0xFFFFFF
#define PATH1_TSSI_F_RDY_C 0x3C4C
#define PATH1_TSSI_F_RDY_C_M 0x20000000
#define PATH1_TSSI_G_RDY_C 0x3C4C
#define PATH1_TSSI_G_RDY_C_M 0x40000000
#define PATH1_TSSI_C_RDY_C 0x3C4C
#define PATH1_TSSI_C_RDY_C_M 0x80000000
#define PATH1_IN_R_SQUARE_MAX_C 0x3C50
#define PATH1_IN_R_SQUARE_MAX_C_M 0xFFFFFF
#define PATH1_SPEC_IDX_C 0x3C50
#define PATH1_SPEC_IDX_C_M 0x7000000
#define PATH1_IN_R_SQUARE_MIN_C 0x3C54
#define PATH1_IN_R_SQUARE_MIN_C_M 0xFFFFFF
#define PATH1_AVG_R_RMS_C 0x3C58
#define PATH1_AVG_R_RMS_C_M 0xFFF
#define PATH1_AVG_R_RMS_RDY_C 0x3C58
#define PATH1_AVG_R_RMS_RDY_C_M 0x80000000
#define PATH1_DAC_GAIN_COMP_TBL_IDX_C 0x3C5C
#define PATH1_DAC_GAIN_COMP_TBL_IDX_C_M 0xFF
#define PATH1_DAC_GAIN_COMP_DBG_C 0x3C5C
#define PATH1_DAC_GAIN_COMP_DBG_C_M 0xFFFFF00
#define PATH1_TXAGC_RF_C 0x3C60
#define PATH1_TXAGC_RF_C_M 0x3F
#define PATH1_TSSI_OFST_C 0x3C60
#define PATH1_TSSI_OFST_C_M 0x1F00
#define PATH1_TXAGC_C 0x3C60
#define PATH1_TXAGC_C_M 0xFF0000
#define PATH1_TXAGC_ORIG_C 0x3C64
#define PATH1_TXAGC_ORIG_C_M 0x1FF
#define PATH1_TXAGC_ORIG_RAW_C 0x3C64
#define PATH1_TXAGC_ORIG_RAW_C_M 0x1FF000
#define PATH1_TXAGC_OFST_SEL_NONRFC_RPT_C 0x3C64
#define PATH1_TXAGC_OFST_SEL_NONRFC_RPT_C_M 0xFF000000
#define PATH1_TXAGC_TO_TSSI_CW_RPT_C 0x3C68
#define PATH1_TXAGC_TO_TSSI_CW_RPT_C_M 0xFFFFFFFF
#define PATH1_TSSI_C_RAW1_C 0x3C6C
#define PATH1_TSSI_C_RAW1_C_M 0x1FF
#define PATH1_DAC_GAIN_COMP_MX_C 0x3C70
#define PATH1_DAC_GAIN_COMP_MX_C_M 0xFF0000
#define PATH1_TSSI_CW_COMP_MX_C 0x3C70
#define PATH1_TSSI_CW_COMP_MX_C_M 0xFF000000
#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_C 0x3C74
#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_C_M 0x1FF
#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_C 0x3C74
#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_C_M 0x1FF000
#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x3C74
#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x1000000
#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x3C74
#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x2000000
#define PATH1_RFC_PREAMLE_PW_TYPE_C 0x3C74
#define PATH1_RFC_PREAMLE_PW_TYPE_C_M 0x70000000
#define PATH1_TXPW_C 0x3C78
#define PATH1_TXPW_C_M 0x1FF
#define PATH1_TXAGCSWING_C 0x3C78
#define PATH1_TXAGCSWING_C_M 0x1E00
#define PATH1_HE_ER_SU_EN_C 0x3C78
#define PATH1_HE_ER_SU_EN_C_M 0x2000
#define PATH1_HE_TB_EN_C 0x3C78
#define PATH1_HE_TB_EN_C_M 0x4000
#define PATH1_CCK_PPDU_C 0x3C78
#define PATH1_CCK_PPDU_C_M 0x8000
#define PATH1_TXINFO_CH_WITH_DATA_C 0x3C78
#define PATH1_TXINFO_CH_WITH_DATA_C_M 0xFF0000
#define PATH1_TXSC_C 0x3C78
#define PATH1_TXSC_C_M 0xF000000
#define PATH1_RF_BW_IDX_C 0x3C78
#define PATH1_RF_BW_IDX_C_M 0x30000000
#define PATH1_ISOFDM_PREAMBLE_C 0x3C78
#define PATH1_ISOFDM_PREAMBLE_C_M 0x40000000
#define PATH1_ISCCK_PREAMBLE_C 0x3C78
#define PATH1_ISCCK_PREAMBLE_C_M 0x80000000
#define PATH1_TXAGC_OFST_MX_C 0x3C7C
#define PATH1_TXAGC_OFST_MX_C_M 0xFF
#define PATH1_TXAGC_OFST_C 0x3C7C
#define PATH1_TXAGC_OFST_C_M 0xFF00
#define PATH1_TXAGC_OFST_VARIATION_POS_FLAG_C 0x3C7C
#define PATH1_TXAGC_OFST_VARIATION_POS_FLAG_C_M 0x10000
#define PATH1_TXAGC_OFST_VARIATION_NEG_FLAG_C 0x3C7C
#define PATH1_TXAGC_OFST_VARIATION_NEG_FLAG_C_M 0x20000
#define PATH1_BYPASS_TSSI_BY_C_C 0x3C7C
#define PATH1_BYPASS_TSSI_BY_C_C_M 0x40000
#define PATH1_ADC_VARIATION_C 0x3C7C
#define PATH1_ADC_VARIATION_C_M 0xFFF00000
#define PATH1_DBG_IQK_PATH_C 0x3C80
#define PATH1_DBG_IQK_PATH_C_M 0xFFFFFFFF
#define PATH1_FTM_RFLBK_BYPASS_C 0x3C84
#define PATH1_FTM_RFLBK_BYPASS_C_M 0x1
#define PATH1_FTM_LBK_BYPASS_C 0x3C84
#define PATH1_FTM_LBK_BYPASS_C_M 0x2
#define PATH1_FTM_A2A_AFELBK_BYPASS_C 0x3C84
#define PATH1_FTM_A2A_AFELBK_BYPASS_C_M 0x4
#define PATH1_GNT_BT_TX_BYPASS_C 0x3C84
#define PATH1_GNT_BT_TX_BYPASS_C_M 0x8
#define PATH1_GNT_BT_BYPASS_C 0x3C84
#define PATH1_GNT_BT_BYPASS_C_M 0x10
#define PATH1_GNT_WL_BYPASS_C 0x3C84
#define PATH1_GNT_WL_BYPASS_C_M 0x20
#define PATH1_LTE_RX_BYPASS_C 0x3C84
#define PATH1_LTE_RX_BYPASS_C_M 0x40
#define PATH1_TSSI_BYPASS_TXPW_MIN_C 0x3C84
#define PATH1_TSSI_BYPASS_TXPW_MIN_C_M 0x80
#define PATH1_TSSI_BYPASS_TXPW_MAX_C 0x3C84
#define PATH1_TSSI_BYPASS_TXPW_MAX_C_M 0x100
#define PATH1_BYPASS_TSSI_BY_RATE_CCK_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_CCK_C_M 0x200
#define PATH1_BYPASS_TSSI_BY_RATE_LEGACY_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_LEGACY_C_M 0x400
#define PATH1_BYPASS_TSSI_BY_RATE_HT_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_HT_C_M 0x800
#define PATH1_BYPASS_TSSI_BY_RATE_VHT_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_VHT_C_M 0x1000
#define PATH1_BYPASS_TSSI_BY_RATE_HE_SU_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_HE_SU_C_M 0x2000
#define PATH1_BYPASS_TSSI_BY_RATE_HE_ER_SU_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_HE_ER_SU_C_M 0x4000
#define PATH1_BYPASS_TSSI_BY_RATE_HE_TB_EN_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_HE_TB_EN_C_M 0x8000
#define PATH1_BYPASS_TSSI_BY_RATE_VHT_MU_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_VHT_MU_C_M 0x10000
#define PATH1_BYPASS_TSSI_BY_RATE_HE_MU_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_HE_MU_C_M 0x20000
#define PATH1_BYPASS_TSSI_BY_RATE_HE_RU_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RATE_HE_RU_C_M 0x40000
#define PATH1_BYPASS_TSSI_BY_TXBF_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_TXBF_C_M 0x80000
#define PATH1_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x3C84
#define PATH1_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x100000
#define PATH1_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x3C84
#define PATH1_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x200000
#define PATH1_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C 0x3C84
#define PATH1_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x400000
#define PATH1_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C 0x3C84
#define PATH1_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x800000
#define PATH1_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C 0x3C84
#define PATH1_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C_M 0x40000000
#define PATH1_BYPASS_TSSI_C 0x3C84
#define PATH1_BYPASS_TSSI_C_M 0x80000000
#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_C 0x3C88
#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_C_M 0xF
#define PATH1_DIGI_AGC_C 0x3C88
#define PATH1_DIGI_AGC_C_M 0x3FF0
#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_MX_C 0x3C88
#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_MX_C_M 0xF0000
#define PATH1_WLS_WL_GAIN_TX_PAD_BUF_MX_C 0x3C88
#define PATH1_WLS_WL_GAIN_TX_PAD_BUF_MX_C_M 0x1F00000
#define PATH1_WLS_WL_GAIN_TX_BUF_MX_C 0x3C88
#define PATH1_WLS_WL_GAIN_TX_BUF_MX_C_M 0x3E000000
#define PATH1_RX_CFIR_TAP_DEC_C 0x3C88
#define PATH1_RX_CFIR_TAP_DEC_C_M 0x40000000
#define PATH1_CLK_HIGH_RATE_MX_C 0x3C88
#define PATH1_CLK_HIGH_RATE_MX_C_M 0x80000000
#define PATH1_CFIR_OUT_IM_DBG_C 0x3C8C
#define PATH1_CFIR_OUT_IM_DBG_C_M 0xFFF
#define PATH1_CFIR_OUT_RE_DBG_C 0x3C8C
#define PATH1_CFIR_OUT_RE_DBG_C_M 0xFFF000
#define PATH1_EN_RX_CFIR_C 0x3C8C
#define PATH1_EN_RX_CFIR_C_M 0x1000000
#define PATH1_CLK_HIGH_RATE_C 0x3C8C
#define PATH1_CLK_HIGH_RATE_C_M 0x2000000
#define PATH1_EN_TX_CFIR_C 0x3C8C
#define PATH1_EN_TX_CFIR_C_M 0x4000000
#define PATH1_TX_CCK_IND_C 0x3C8C
#define PATH1_TX_CCK_IND_C_M 0x8000000
#define PATH1_CFIR_IN_IM_DBG_C 0x3C90
#define PATH1_CFIR_IN_IM_DBG_C_M 0xFFF
#define PATH1_CFIR_IN_RE_DBG_C 0x3C90
#define PATH1_CFIR_IN_RE_DBG_C_M 0xFFF000
#define PATH1_CCK_CCA_C 0x3C90
#define PATH1_CCK_CCA_C_M 0x80000000
#define PATH1_RX_C 0x3C94
#define PATH1_RX_C_M 0x1F
#define PATH1_LNA_SETTING_C 0x3C94
#define PATH1_LNA_SETTING_C_M 0x700
#define PATH1_TIA_C 0x3C94
#define PATH1_TIA_C_M 0x1000
#define PATH1_DB2FLT_O_C 0x3C94
#define PATH1_DB2FLT_O_C_M 0x7FF8000
#define PATH1_LSTF_SUM_LINEAR_PW_C 0x3C98
#define PATH1_LSTF_SUM_LINEAR_PW_C_M 0xFFFFFFFF
#define PATH1_LSTF_MAX_LINEAR_PW_C 0x3C9C
#define PATH1_LSTF_MAX_LINEAR_PW_C_M 0x7FFFFF
#define PATH1_TSSI_C_C 0x3CA0
#define PATH1_TSSI_C_C_M 0x1FF
#define PATH1_TSSI_C_SRC_C 0x3CA0
#define PATH1_TSSI_C_SRC_C_M 0x3FF000
#define PATH1_TXAGC_TP_C 0x3CA0
#define PATH1_TXAGC_TP_C_M 0xFF000000
#define PATH1_LOG_VAL_O_C 0x3CA4
#define PATH1_LOG_VAL_O_C_M 0xFFFFF
#define PATH1_TXAGC_OFST_ADJ_C 0x3CA4
#define PATH1_TXAGC_OFST_ADJ_C_M 0xFF000000
#define PATH1_TX_GAIN_FOR_DPD_DB2FLOAT_C 0x3CA8
#define PATH1_TX_GAIN_FOR_DPD_DB2FLOAT_C_M 0xFF
#define PATH1_TX_GAIN_FOR_DPD_DBAGC_COMB_C 0x3CA8
#define PATH1_TX_GAIN_FOR_DPD_DBAGC_COMB_C_M 0xFF00
#define PATH1_TMETER_TX_C 0x3CAC
#define PATH1_TMETER_TX_C_M 0x3F
#define PATH1_TMETER_CCA_POS_C 0x3CAC
#define PATH1_TMETER_CCA_POS_C_M 0x3F00
#define PATH1_TMETER_CCA_NEG_C 0x3CAC
#define PATH1_TMETER_CCA_NEG_C_M 0x3F0000
#define PATH1_AFE_ANAPAR_PW_O_C 0x3CB0
#define PATH1_AFE_ANAPAR_PW_O_C_M 0xFF
#define PATH1_AFE_ANAPAR_CTRL_O_C 0x3CB0
#define PATH1_AFE_ANAPAR_CTRL_O_C_M 0xFFFF00
#define PATH1_MUX_ST_PATH_C 0x3CB0
#define PATH1_MUX_ST_PATH_C_M 0xF000000
#define PATH1_TSSI_J_CCK_C 0x3CB4
#define PATH1_TSSI_J_CCK_C_M 0x3FF
#define PATH1_TSSI_J_OFDM_C 0x3CB4
#define PATH1_TSSI_J_OFDM_C_M 0xFFC00
#define PATH1_TSSI_CURVE_C 0x3CB4
#define PATH1_TSSI_CURVE_C_M 0x70000000
#define PATH1_R_TXAGC_OFDM_REF_CW_CMB_C 0x3CB8
#define PATH1_R_TXAGC_OFDM_REF_CW_CMB_C_M 0x1FF
#define PATH1_R_TXAGC_CCK_REF_CW_CMB_C 0x3CB8
#define PATH1_R_TXAGC_CCK_REF_CW_CMB_C_M 0x1FF000
#define PATH1_AFE_ANAPAR_CTSDM_OUT_I_C 0x3E00
#define PATH1_AFE_ANAPAR_CTSDM_OUT_I_C_M 0xFFFFF
#define PATH1_RO_SI_R_DATA_P_C 0x3E04
#define PATH1_RO_SI_R_DATA_P_C_M 0xFFFFF
#define PATH1_NLGC_STEP_CNT_AT_AGC_RDY_C 0x3E08
#define PATH1_NLGC_STEP_CNT_AT_AGC_RDY_C_M 0x7
#define PATH1_POST_PD_STEP_CNT_AT_AGC_RDY_C 0x3E08
#define PATH1_POST_PD_STEP_CNT_AT_AGC_RDY_C_M 0x38
#define PATH1_LINEAR_STEP_CNT_AT_AGC_RDY_C 0x3E08
#define PATH1_LINEAR_STEP_CNT_AT_AGC_RDY_C_M 0x1C0
#define PATH1_PRE_PD_STEP_CNT_AT_AGC_RDY_C 0x3E08
#define PATH1_PRE_PD_STEP_CNT_AT_AGC_RDY_C_M 0xE00
#define PATH1_TIA_SAT_DET_AT_AGC_RDY_C 0x3E08
#define PATH1_TIA_SAT_DET_AT_AGC_RDY_C_M 0x1000
#define PATH1_LNA_SAT_DET_AT_AGC_RDY_C 0x3E08
#define PATH1_LNA_SAT_DET_AT_AGC_RDY_C_M 0x2000
#define PATH1_NRBW_AT_AGC_RDY_C 0x3E08
#define PATH1_NRBW_AT_AGC_RDY_C_M 0x4000
#define PATH1_TIA_SHRINK_AT_AGC_RDY_C 0x3E08
#define PATH1_TIA_SHRINK_AT_AGC_RDY_C_M 0x8000
#define PATH1_P_DIFF_AT_AGC_RDY_C 0x3E08
#define PATH1_P_DIFF_AT_AGC_RDY_C_M 0xFF0000
#define PATH1_ELNA_IDX_AT_AGC_RDY_C 0x3E0C
#define PATH1_ELNA_IDX_AT_AGC_RDY_C_M 0x1
#define PATH1_ELNA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_ELNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x2
#define PATH1_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x4
#define PATH1_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x8
#define PATH1_NRBW_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_NRBW_AT_PRE_PD_AGC_RDY_C_M 0x10
#define PATH1_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C_M 0x20
#define PATH1_P_DIFF_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_P_DIFF_AT_PRE_PD_AGC_RDY_C_M 0x7FC0
#define PATH1_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C_M 0x7F8000
#define PATH1_RXIDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_RXIDX_AT_PRE_PD_AGC_RDY_C_M 0xF800000
#define PATH1_TIA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_TIA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x10000000
#define PATH1_LNA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
#define PATH1_LNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0xE0000000
#define PATH1_ELNA_IDX_AT_PD_HIT_C 0x3E10
#define PATH1_ELNA_IDX_AT_PD_HIT_C_M 0x2
#define PATH1_TIA_SAT_DET_AT_PD_HIT_C 0x3E10
#define PATH1_TIA_SAT_DET_AT_PD_HIT_C_M 0x4
#define PATH1_LNA_SAT_DET_AT_PD_HIT_C 0x3E10
#define PATH1_LNA_SAT_DET_AT_PD_HIT_C_M 0x8
#define PATH1_NRBW_AT_PD_HIT_C 0x3E10
#define PATH1_NRBW_AT_PD_HIT_C_M 0x10
#define PATH1_TIA_SHRINK_AT_PD_HIT_C 0x3E10
#define PATH1_TIA_SHRINK_AT_PD_HIT_C_M 0x20
#define PATH1_P_DIFF_AT_PD_HIT_C 0x3E10
#define PATH1_P_DIFF_AT_PD_HIT_C_M 0x7FC0
#define PATH1_G_NLGC_DAGC_AT_PD_HIT_C 0x3E10
#define PATH1_G_NLGC_DAGC_AT_PD_HIT_C_M 0x7F8000
#define PATH1_RXIDX_AT_PD_HIT_C 0x3E10
#define PATH1_RXIDX_AT_PD_HIT_C_M 0xF800000
#define PATH1_TIA_IDX_AT_PD_HIT_C 0x3E10
#define PATH1_TIA_IDX_AT_PD_HIT_C_M 0x10000000
#define PATH1_LNA_IDX_AT_PD_HIT_C 0x3E10
#define PATH1_LNA_IDX_AT_PD_HIT_C_M 0xE0000000
#define PATH1_ELNA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_ELNA_IDX_AT_POST_PD_AGC_RDY_C_M 0x2
#define PATH1_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x4
#define PATH1_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x8
#define PATH1_NRBW_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_NRBW_AT_POST_PD_AGC_RDY_C_M 0x10
#define PATH1_TIA_SHRINK_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_TIA_SHRINK_AT_POST_PD_AGC_RDY_C_M 0x20
#define PATH1_P_DIFF_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_P_DIFF_AT_POST_PD_AGC_RDY_C_M 0x7FC0
#define PATH1_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C_M 0x7F8000
#define PATH1_RXIDX_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_RXIDX_AT_POST_PD_AGC_RDY_C_M 0xF800000
#define PATH1_TIA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_TIA_IDX_AT_POST_PD_AGC_RDY_C_M 0x10000000
#define PATH1_LNA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14
#define PATH1_LNA_IDX_AT_POST_PD_AGC_RDY_C_M 0xE0000000
#define PATH1_ELNA_IDX_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_ELNA_IDX_AT_NLGC_AGC_RDY_C_M 0x2
#define PATH1_TIA_SAT_DET_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_TIA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x4
#define PATH1_LNA_SAT_DET_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_LNA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x8
#define PATH1_NRBW_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_NRBW_AT_NLGC_AGC_RDY_C_M 0x10
#define PATH1_TIA_SHRINK_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_TIA_SHRINK_AT_NLGC_AGC_RDY_C_M 0x20
#define PATH1_P_DIFF_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_P_DIFF_AT_NLGC_AGC_RDY_C_M 0x7FC0
#define PATH1_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C_M 0x7F8000
#define PATH1_RXIDX_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_RXIDX_AT_NLGC_AGC_RDY_C_M 0xF800000
#define PATH1_TIA_IDX_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_TIA_IDX_AT_NLGC_AGC_RDY_C_M 0x10000000
#define PATH1_LNA_IDX_AT_NLGC_AGC_RDY_C 0x3E18
#define PATH1_LNA_IDX_AT_NLGC_AGC_RDY_C_M 0xE0000000
#define PATH1_RSSI_AT_AGC_RDY_C 0x3E1C
#define PATH1_RSSI_AT_AGC_RDY_C_M 0x3FF
#define PATH1_G_TOTAL_AT_AGC_RDY_C 0x3E1C
#define PATH1_G_TOTAL_AT_AGC_RDY_C_M 0x7FC00
#define PATH1_P_DFIR_DBM_AT_AGC_RDY_C 0x3E1C
#define PATH1_P_DFIR_DBM_AT_AGC_RDY_C_M 0xFF80000
#define PATH1_TIA_IDX_AT_AGC_RDY_C 0x3E1C
#define PATH1_TIA_IDX_AT_AGC_RDY_C_M 0x10000000
#define PATH1_LNA_IDX_AT_AGC_RDY_C 0x3E1C
#define PATH1_LNA_IDX_AT_AGC_RDY_C_M 0xE0000000
#define PATH1_RSSI_ALWAYS_RUN_C 0x3E20
#define PATH1_RSSI_ALWAYS_RUN_C_M 0x3FF
#define PATH1_TIA_SAT_DET_C 0x3E20
#define PATH1_TIA_SAT_DET_C_M 0x400
#define PATH1_LNA_SAT_DET_C 0x3E20
#define PATH1_LNA_SAT_DET_C_M 0x800
#define PATH1_NRBW_C 0x3E20
#define PATH1_NRBW_C_M 0x1000
#define PATH1_TIA_SHRINK_C 0x3E20
#define PATH1_TIA_SHRINK_C_M 0x2000
#define PATH1_G_LGC_DAGC_C 0x3E20
#define PATH1_G_LGC_DAGC_C_M 0x3FC000
#define PATH1_G_TOTAL_C 0x3E20
#define PATH1_G_TOTAL_C_M 0xFFC00000
#define PATH1_HW_SI_READ_DATA_C 0x3E24
#define PATH1_HW_SI_READ_DATA_C_M 0xFFFFF
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C_M 0x1
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C_M 0x2
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C_M 0x4
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C_M 0x8
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C_M 0x10
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C_M 0x20
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C_M 0x40
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C_M 0x80
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C_M 0x100
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C_M 0x200
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C_M 0x400
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C 0x3E28
#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C_M 0x800
#define PATH1_CNT_HW_SI_W_TX_CMD_START_PATH_C 0x3E2C
#define PATH1_CNT_HW_SI_W_TX_CMD_START_PATH_C_M 0xFFFF
#define PATH1_CNT_HW_SI_W_RX_CMD_START_PATH_C 0x3E2C
#define PATH1_CNT_HW_SI_W_RX_CMD_START_PATH_C_M 0xFFFF0000
#define PATH1_CNT_HW_SI_R_CMD_START_PATH_C 0x3E30
#define PATH1_CNT_HW_SI_R_CMD_START_PATH_C_M 0xFFFF
#define TX_ACC_EN_C 0x4000
#define TX_ACC_EN_C_M 0x1
#define BWD_SNR_THD_1_C 0x4004
#define BWD_SNR_THD_1_C_M 0x3FF
#define BWD_SNR_THD_2_C 0x4004
#define BWD_SNR_THD_2_C_M 0xFFC00
#define BWD_SNR_THD_3_C 0x4004
#define BWD_SNR_THD_3_C_M 0x3FF00000
#define BWD_SEL_CONSERVE_EN_C 0x4004
#define BWD_SEL_CONSERVE_EN_C_M 0x40000000
#define DATA_BW_FLAG_S0_C 0x4004
#define DATA_BW_FLAG_S0_C_M 0x80000000
#define BWD_SNR_THD_4_C 0x4008
#define BWD_SNR_THD_4_C_M 0x3FF
#define BWD_THD_1_C 0x4008
#define BWD_THD_1_C_M 0xFFC00
#define BWD_THD_2_C 0x4008
#define BWD_THD_2_C_M 0x3FF00000
#define DATA_BW_FLAG_S1_C 0x4008
#define DATA_BW_FLAG_S1_C_M 0x40000000
#define DATA_BW_FLAG_S2_C 0x4008
#define DATA_BW_FLAG_S2_C_M 0x80000000
#define BWD_THD_3_C 0x400C
#define BWD_THD_3_C_M 0x3FF
#define BWD_THD_4_C 0x400C
#define BWD_THD_4_C_M 0xFFC00
#define BWD_THD_5_C 0x400C
#define BWD_THD_5_C_M 0x3FF00000
#define DATA_BW_FLAG_S3_C 0x400C
#define DATA_BW_FLAG_S3_C_M 0x40000000
#define MANUAL_DATA_BW_EN_C 0x400C
#define MANUAL_DATA_BW_EN_C_M 0x80000000
#define BWD_RESERVED_1_C 0x4010
#define BWD_RESERVED_1_C_M 0x3FF
#define BWD_RESERVED_2_C 0x4010
#define BWD_RESERVED_2_C_M 0xFFC00
#define BWD_RESERVED_3_C 0x4010
#define BWD_RESERVED_3_C_M 0x3FF00000
#define BWD_RESERVED_4_C 0x4014
#define BWD_RESERVED_4_C_M 0x3FF
#define BWD_RESERVED_5_C 0x4014
#define BWD_RESERVED_5_C_M 0xFFC00
#define BWD_RESERVED_6_C 0x4014
#define BWD_RESERVED_6_C_M 0x3FF00000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR0_C 0x4018
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR1_C 0x4018
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR2_C 0x4018
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR3_C 0x4018
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR4_C 0x401C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR5_C 0x401C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR0_C 0x401C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR1_C 0x401C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR2_C 0x4020
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR3_C 0x4020
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR4_C 0x4020
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR5_C 0x4020
#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR0_C 0x4024
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR1_C 0x4024
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR2_C 0x4024
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR3_C 0x4024
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR4_C 0x4028
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR5_C 0x4028
#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR0_C 0x4028
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR1_C 0x4028
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR2_C 0x402C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR3_C 0x402C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR4_C 0x402C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR5_C 0x402C
#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR0_C 0x4030
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR1_C 0x4030
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR2_C 0x4030
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR3_C 0x4030
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR4_C 0x4034
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR5_C 0x4034
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR0_C 0x4034
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR1_C 0x4034
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR2_C 0x4038
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR3_C 0x4038
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR4_C 0x4038
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR5_C 0x4038
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR0_C 0x403C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR1_C 0x403C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR2_C 0x403C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR3_C 0x403C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR4_C 0x4040
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR5_C 0x4040
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR0_C 0x4040
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR1_C 0x4040
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR2_C 0x4044
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR3_C 0x4044
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR4_C 0x4044
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR5_C 0x4044
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR0_C 0x4048
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR1_C 0x4048
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR2_C 0x4048
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR3_C 0x4048
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR4_C 0x404C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR5_C 0x404C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR0_C 0x404C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR1_C 0x404C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR2_C 0x4050
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR3_C 0x4050
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR4_C 0x4050
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR5_C 0x4050
#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR0_C 0x4054
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR1_C 0x4054
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR2_C 0x4054
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR3_C 0x4054
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR4_C 0x4058
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR5_C 0x4058
#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR0_C 0x4058
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR1_C 0x4058
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR2_C 0x405C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR3_C 0x405C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR4_C 0x405C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR5_C 0x405C
#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR0_C 0x4060
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR1_C 0x4060
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR2_C 0x4060
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR3_C 0x4060
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR4_C 0x4064
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR5_C 0x4064
#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR0_C 0x4064
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR1_C 0x4064
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR2_C 0x4068
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR3_C 0x4068
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR4_C 0x4068
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR5_C 0x4068
#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR0_C 0x406C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR1_C 0x406C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR2_C 0x406C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR3_C 0x406C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR4_C 0x4070
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR5_C 0x4070
#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR0_C 0x4070
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR1_C 0x4070
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR2_C 0x4074
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR3_C 0x4074
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR4_C 0x4074
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR5_C 0x4074
#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR0_C 0x4078
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR1_C 0x4078
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR2_C 0x4078
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR3_C 0x4078
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR4_C 0x407C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR5_C 0x407C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR0_C 0x407C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR1_C 0x407C
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR2_C 0x4080
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR3_C 0x4080
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR4_C 0x4080
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR5_C 0x4080
#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR0_C 0x4084
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR1_C 0x4084
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR2_C 0x4084
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR3_C 0x4084
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR4_C 0x4088
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR5_C 0x4088
#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR0_C 0x4088
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR1_C 0x4088
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR2_C 0x408C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR3_C 0x408C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR4_C 0x408C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR5_C 0x408C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR0_C 0x4090
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR1_C 0x4090
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR2_C 0x4090
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR3_C 0x4090
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR4_C 0x4094
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR5_C 0x4094
#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR0_C 0x4094
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR1_C 0x4094
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR2_C 0x4098
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR3_C 0x4098
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR4_C 0x4098
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR5_C 0x4098
#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR0_C 0x409C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR1_C 0x409C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR2_C 0x409C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR3_C 0x409C
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR4_C 0x40A0
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR5_C 0x40A0
#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR0_C 0x40A0
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR1_C 0x40A0
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR2_C 0x40A4
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR3_C 0x40A4
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR4_C 0x40A4
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR5_C 0x40A4
#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR0_C 0x40A8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR1_C 0x40A8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR2_C 0x40A8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR3_C 0x40A8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR4_C 0x40AC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR5_C 0x40AC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR0_C 0x40AC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR1_C 0x40AC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR2_C 0x40B0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR3_C 0x40B0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR4_C 0x40B0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR5_C 0x40B0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR0_C 0x40B4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR1_C 0x40B4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR2_C 0x40B4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR3_C 0x40B4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR4_C 0x40B8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR5_C 0x40B8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR0_C 0x40B8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR1_C 0x40B8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR2_C 0x40BC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR3_C 0x40BC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR4_C 0x40BC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR5_C 0x40BC
#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR0_C 0x40C0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR1_C 0x40C0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR2_C 0x40C0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR3_C 0x40C0
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR4_C 0x40C4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR5_C 0x40C4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR0_C 0x40C4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR1_C 0x40C4
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR2_C 0x40C8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR3_C 0x40C8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR4_C 0x40C8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR5_C 0x40C8
#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR0_C 0x40CC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR1_C 0x40CC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR2_C 0x40CC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR3_C 0x40CC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR4_C 0x40D0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR5_C 0x40D0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR0_C 0x40D0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR1_C 0x40D0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR2_C 0x40D4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR3_C 0x40D4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR4_C 0x40D4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR5_C 0x40D4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR0_C 0x40D8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR1_C 0x40D8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR2_C 0x40D8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR3_C 0x40D8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR4_C 0x40DC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR5_C 0x40DC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR0_C 0x40DC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR1_C 0x40DC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR2_C 0x40E0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR3_C 0x40E0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR4_C 0x40E0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR5_C 0x40E0
#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR5_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR0_C 0x40E4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR0_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR1_C 0x40E4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR1_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR2_C 0x40E4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR2_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR3_C 0x40E4
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR3_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR4_C 0x40E8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR4_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR5_C 0x40E8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR5_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR0_C 0x40E8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR0_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR1_C 0x40E8
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR1_C_M 0xFF000000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR2_C 0x40EC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR2_C_M 0xFF
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR3_C 0x40EC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR3_C_M 0xFF00
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR4_C 0x40EC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR4_C_M 0xFF0000
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR5_C 0x40EC
#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR5_C_M 0xFF000000
#define NOISE_EST_COUNT_THR_C 0x40F0
#define NOISE_EST_COUNT_THR_C_M 0x3F
#define ZERO_HOLD_FOR_1X_EN_C 0x40F0
#define ZERO_HOLD_FOR_1X_EN_C_M 0x40
#define ZERO_HOLD_FOR_2X_EN_C 0x40F0
#define ZERO_HOLD_FOR_2X_EN_C_M 0x80
#define SMOOTH_COEFF_SEL_C 0x40F4
#define SMOOTH_COEFF_SEL_C_M 0x3
#define V_MATRIX_INTPL_EN_C 0x40F4
#define V_MATRIX_INTPL_EN_C_M 0x4
#define V_MATRIX_SMO_EN_C 0x40F4
#define V_MATRIX_SMO_EN_C_M 0x8
#define MUIC_EN_C 0x40F8
#define MUIC_EN_C_M 0x1
#define DEV1_TH_NG1_BW20_C 0x40FC
#define DEV1_TH_NG1_BW20_C_M 0x3F
#define DEV1_TH_NG1_BW40_C 0x40FC
#define DEV1_TH_NG1_BW40_C_M 0xFC0
#define DEV1_TH_NG1_BW80_C 0x40FC
#define DEV1_TH_NG1_BW80_C_M 0x3F000
#define DEV1_TH_NG2_BW20_C 0x40FC
#define DEV1_TH_NG2_BW20_C_M 0xFC0000
#define DEV1_TH_NG2_BW40_C 0x40FC
#define DEV1_TH_NG2_BW40_C_M 0x3F000000
#define NONCON160M_C 0x40FC
#define NONCON160M_C_M 0x40000000
#define AVGSNR_DIFF_EN_C 0x40FC
#define AVGSNR_DIFF_EN_C_M 0x80000000
#define DEV1_TH_NG2_BW80_C 0x4100
#define DEV1_TH_NG2_BW80_C_M 0x3F
#define DEV1_TH_NG4_BW20_C 0x4100
#define DEV1_TH_NG4_BW20_C_M 0xFC0
#define DEV1_TH_NG4_BW40_C 0x4100
#define DEV1_TH_NG4_BW40_C_M 0x3F000
#define DEV1_TH_NG4_BW80_C 0x4100
#define DEV1_TH_NG4_BW80_C_M 0xFC0000
#define DEV2_TH_NG1_BW20_C 0x4100
#define DEV2_TH_NG1_BW20_C_M 0x3F000000
#define BADTONE_COUNT_TH_SRC_GRPING_C 0x4100
#define BADTONE_COUNT_TH_SRC_GRPING_C_M 0x40000000
#define DEV2_TH_NG1_BW40_C 0x4104
#define DEV2_TH_NG1_BW40_C_M 0x3F
#define DEV2_TH_NG1_BW80_C 0x4104
#define DEV2_TH_NG1_BW80_C_M 0xFC0
#define DEV2_TH_NG2_BW20_C 0x4104
#define DEV2_TH_NG2_BW20_C_M 0x3F000
#define DEV2_TH_NG2_BW40_C 0x4104
#define DEV2_TH_NG2_BW40_C_M 0xFC0000
#define DEV2_TH_NG2_BW80_C 0x4104
#define DEV2_TH_NG2_BW80_C_M 0x3F000000
#define DEV2_TH_NG4_BW20_C 0x4108
#define DEV2_TH_NG4_BW20_C_M 0x3F
#define DEV2_TH_NG4_BW40_C 0x4108
#define DEV2_TH_NG4_BW40_C_M 0xFC0
#define DEV2_TH_NG4_BW80_C 0x4108
#define DEV2_TH_NG4_BW80_C_M 0x3F000
#define HE_DEV1_TH_NG16_BW20_C 0x4108
#define HE_DEV1_TH_NG16_BW20_C_M 0xFC0000
#define HE_DEV1_TH_NG16_BW40_C 0x4108
#define HE_DEV1_TH_NG16_BW40_C_M 0x3F000000
#define HE_DEV1_TH_NG16_BW80_C 0x410C
#define HE_DEV1_TH_NG16_BW80_C_M 0x3F
#define HE_DEV1_TH_NG4_BW20_C 0x410C
#define HE_DEV1_TH_NG4_BW20_C_M 0xFC0
#define HE_DEV1_TH_NG4_BW40_C 0x410C
#define HE_DEV1_TH_NG4_BW40_C_M 0x3F000
#define HE_DEV1_TH_NG4_BW80_C 0x410C
#define HE_DEV1_TH_NG4_BW80_C_M 0xFC0000
#define HE_DEV2_TH_NG16_BW20_C 0x410C
#define HE_DEV2_TH_NG16_BW20_C_M 0x3F000000
#define HE_DEV2_TH_NG16_BW40_C 0x4110
#define HE_DEV2_TH_NG16_BW40_C_M 0x3F
#define HE_DEV2_TH_NG16_BW80_C 0x4110
#define HE_DEV2_TH_NG16_BW80_C_M 0xFC0
#define HE_DEV2_TH_NG4_BW20_C 0x4110
#define HE_DEV2_TH_NG4_BW20_C_M 0x3F000
#define HE_DEV2_TH_NG4_BW40_C 0x4110
#define HE_DEV2_TH_NG4_BW40_C_M 0xFC0000
#define HE_DEV2_TH_NG4_BW80_C 0x4110
#define HE_DEV2_TH_NG4_BW80_C_M 0x3F000000
#define HE_SNR1_MIN_CNT_TH_NG16_BW20_C 0x4114
#define HE_SNR1_MIN_CNT_TH_NG16_BW20_C_M 0x3F
#define HE_SNR1_MIN_CNT_TH_NG16_BW40_C 0x4114
#define HE_SNR1_MIN_CNT_TH_NG16_BW40_C_M 0xFC0
#define HE_SNR1_MIN_CNT_TH_NG16_BW80_C 0x4114
#define HE_SNR1_MIN_CNT_TH_NG16_BW80_C_M 0x3F000
#define HE_SNR1_MIN_CNT_TH_NG4_BW20_C 0x4114
#define HE_SNR1_MIN_CNT_TH_NG4_BW20_C_M 0xFC0000
#define HE_SNR1_MIN_CNT_TH_NG4_BW40_C 0x4114
#define HE_SNR1_MIN_CNT_TH_NG4_BW40_C_M 0x3F000000
#define HE_SNR1_MIN_CNT_TH_NG4_BW80_C 0x4118
#define HE_SNR1_MIN_CNT_TH_NG4_BW80_C_M 0x3F
#define HE_SNR2_MIN_CNT_TH_NG16_BW20_C 0x4118
#define HE_SNR2_MIN_CNT_TH_NG16_BW20_C_M 0xFC0
#define HE_SNR2_MIN_CNT_TH_NG16_BW40_C 0x4118
#define HE_SNR2_MIN_CNT_TH_NG16_BW40_C_M 0x3F000
#define HE_SNR2_MIN_CNT_TH_NG16_BW80_C 0x4118
#define HE_SNR2_MIN_CNT_TH_NG16_BW80_C_M 0xFC0000
#define HE_SNR2_MIN_CNT_TH_NG4_BW20_C 0x4118
#define HE_SNR2_MIN_CNT_TH_NG4_BW20_C_M 0x3F000000
#define HE_SNR2_MIN_CNT_TH_NG4_BW40_C 0x411C
#define HE_SNR2_MIN_CNT_TH_NG4_BW40_C_M 0x3F
#define HE_SNR2_MIN_CNT_TH_NG4_BW80_C 0x411C
#define HE_SNR2_MIN_CNT_TH_NG4_BW80_C_M 0xFC0
#define SNR1_MIN_CNT_TH_NG1_BW20_C 0x411C
#define SNR1_MIN_CNT_TH_NG1_BW20_C_M 0x3F000
#define SNR1_MIN_CNT_TH_NG1_BW40_C 0x411C
#define SNR1_MIN_CNT_TH_NG1_BW40_C_M 0xFC0000
#define SNR1_MIN_CNT_TH_NG1_BW80_C 0x411C
#define SNR1_MIN_CNT_TH_NG1_BW80_C_M 0x3F000000
#define SNR1_MIN_CNT_TH_NG2_BW20_C 0x4120
#define SNR1_MIN_CNT_TH_NG2_BW20_C_M 0x3F
#define SNR1_MIN_CNT_TH_NG2_BW40_C 0x4120
#define SNR1_MIN_CNT_TH_NG2_BW40_C_M 0xFC0
#define SNR1_MIN_CNT_TH_NG2_BW80_C 0x4120
#define SNR1_MIN_CNT_TH_NG2_BW80_C_M 0x3F000
#define SNR1_MIN_CNT_TH_NG4_BW20_C 0x4120
#define SNR1_MIN_CNT_TH_NG4_BW20_C_M 0xFC0000
#define SNR1_MIN_CNT_TH_NG4_BW40_C 0x4120
#define SNR1_MIN_CNT_TH_NG4_BW40_C_M 0x3F000000
#define SNR1_MIN_CNT_TH_NG4_BW80_C 0x4124
#define SNR1_MIN_CNT_TH_NG4_BW80_C_M 0x3F
#define SNR2_MIN_CNT_TH_NG1_BW20_C 0x4124
#define SNR2_MIN_CNT_TH_NG1_BW20_C_M 0xFC0
#define SNR2_MIN_CNT_TH_NG1_BW40_C 0x4124
#define SNR2_MIN_CNT_TH_NG1_BW40_C_M 0x3F000
#define SNR2_MIN_CNT_TH_NG1_BW80_C 0x4124
#define SNR2_MIN_CNT_TH_NG1_BW80_C_M 0xFC0000
#define SNR2_MIN_CNT_TH_NG2_BW20_C 0x4124
#define SNR2_MIN_CNT_TH_NG2_BW20_C_M 0x3F000000
#define SNR2_MIN_CNT_TH_NG2_BW40_C 0x4128
#define SNR2_MIN_CNT_TH_NG2_BW40_C_M 0x3F
#define SNR2_MIN_CNT_TH_NG2_BW80_C 0x4128
#define SNR2_MIN_CNT_TH_NG2_BW80_C_M 0xFC0
#define SNR2_MIN_CNT_TH_NG4_BW20_C 0x4128
#define SNR2_MIN_CNT_TH_NG4_BW20_C_M 0x3F000
#define SNR2_MIN_CNT_TH_NG4_BW40_C 0x4128
#define SNR2_MIN_CNT_TH_NG4_BW40_C_M 0xFC0000
#define SNR2_MIN_CNT_TH_NG4_BW80_C 0x4128
#define SNR2_MIN_CNT_TH_NG4_BW80_C_M 0x3F000000
#define SNRLOSS_WGT_C 0x412C
#define SNRLOSS_WGT_C_M 0x1F
#define HE_SNR1_TH_NG16_BW20_C 0x412C
#define HE_SNR1_TH_NG16_BW20_C_M 0x1E0
#define HE_SNR1_TH_NG16_BW40_C 0x412C
#define HE_SNR1_TH_NG16_BW40_C_M 0x1E00
#define HE_SNR1_TH_NG16_BW80_C 0x412C
#define HE_SNR1_TH_NG16_BW80_C_M 0x1E000
#define HE_SNR1_TH_NG4_BW20_C 0x412C
#define HE_SNR1_TH_NG4_BW20_C_M 0x1E0000
#define HE_SNR1_TH_NG4_BW40_C 0x412C
#define HE_SNR1_TH_NG4_BW40_C_M 0x1E00000
#define HE_SNR1_TH_NG4_BW80_C 0x412C
#define HE_SNR1_TH_NG4_BW80_C_M 0x1E000000
#define HE_SNR2_TH_NG16_BW20_C 0x4130
#define HE_SNR2_TH_NG16_BW20_C_M 0xF
#define HE_SNR2_TH_NG16_BW40_C 0x4130
#define HE_SNR2_TH_NG16_BW40_C_M 0xF0
#define HE_SNR2_TH_NG16_BW80_C 0x4130
#define HE_SNR2_TH_NG16_BW80_C_M 0xF00
#define HE_SNR2_TH_NG4_BW20_C 0x4130
#define HE_SNR2_TH_NG4_BW20_C_M 0xF000
#define HE_SNR2_TH_NG4_BW40_C 0x4130
#define HE_SNR2_TH_NG4_BW40_C_M 0xF0000
#define HE_SNR2_TH_NG4_BW80_C 0x4130
#define HE_SNR2_TH_NG4_BW80_C_M 0xF00000
#define SNR1_TH_NG1_BW20_C 0x4130
#define SNR1_TH_NG1_BW20_C_M 0xF000000
#define SNR1_TH_NG1_BW40_C 0x4130
#define SNR1_TH_NG1_BW40_C_M 0xF0000000
#define SNR1_TH_NG1_BW80_C 0x4134
#define SNR1_TH_NG1_BW80_C_M 0xF
#define SNR1_TH_NG2_BW20_C 0x4134
#define SNR1_TH_NG2_BW20_C_M 0xF0
#define SNR1_TH_NG2_BW40_C 0x4134
#define SNR1_TH_NG2_BW40_C_M 0xF00
#define SNR1_TH_NG2_BW80_C 0x4134
#define SNR1_TH_NG2_BW80_C_M 0xF000
#define SNR1_TH_NG4_BW20_C 0x4134
#define SNR1_TH_NG4_BW20_C_M 0xF0000
#define SNR1_TH_NG4_BW40_C 0x4134
#define SNR1_TH_NG4_BW40_C_M 0xF00000
#define SNR1_TH_NG4_BW80_C 0x4134
#define SNR1_TH_NG4_BW80_C_M 0xF000000
#define SNR2_TH_NG1_BW20_C 0x4134
#define SNR2_TH_NG1_BW20_C_M 0xF0000000
#define SNR2_TH_NG1_BW40_C 0x4138
#define SNR2_TH_NG1_BW40_C_M 0xF
#define SNR2_TH_NG1_BW80_C 0x4138
#define SNR2_TH_NG1_BW80_C_M 0xF0
#define SNR2_TH_NG2_BW20_C 0x4138
#define SNR2_TH_NG2_BW20_C_M 0xF00
#define SNR2_TH_NG2_BW40_C 0x4138
#define SNR2_TH_NG2_BW40_C_M 0xF000
#define SNR2_TH_NG2_BW80_C 0x4138
#define SNR2_TH_NG2_BW80_C_M 0xF0000
#define SNR2_TH_NG4_BW20_C 0x4138
#define SNR2_TH_NG4_BW20_C_M 0xF00000
#define SNR2_TH_NG4_BW40_C 0x4138
#define SNR2_TH_NG4_BW40_C_M 0xF000000
#define SNR2_TH_NG4_BW80_C 0x4138
#define SNR2_TH_NG4_BW80_C_M 0xF0000000
#define AVGSNR_DIFF_TH_C 0x413C
#define AVGSNR_DIFF_TH_C_M 0xF
#define OTHERSNR_WGT_C 0x413C
#define OTHERSNR_WGT_C_M 0xF0
#define PDP_AWGN_FLAG_SUB_TUNE_C 0x4140
#define PDP_AWGN_FLAG_SUB_TUNE_C_M 0x3FF
#define PDP_SNR_SHIFT_FOR_NONLEGACY_C 0x4140
#define PDP_SNR_SHIFT_FOR_NONLEGACY_C_M 0xFFC00
#define PDP_CORR_DIST1_W0_C 0x4140
#define PDP_CORR_DIST1_W0_C_M 0x3FF00000
#define GI_COMB_EN_C 0x4140
#define GI_COMB_EN_C_M 0x40000000
#define PDP_ALL_COMBINE_EN_C 0x4140
#define PDP_ALL_COMBINE_EN_C_M 0x80000000
#define PDP_CORR_DIST1_W1_C 0x4144
#define PDP_CORR_DIST1_W1_C_M 0x3FF
#define PDP_CORR_DIST1_W10_C 0x4144
#define PDP_CORR_DIST1_W10_C_M 0xFFC00
#define PDP_CORR_DIST1_W11_C 0x4144
#define PDP_CORR_DIST1_W11_C_M 0x3FF00000
#define MANUAL_GD_PHASE_EN_C 0x4144
#define MANUAL_GD_PHASE_EN_C_M 0x40000000
#define MANUAL_SNR_IDX_EN_C 0x4144
#define MANUAL_SNR_IDX_EN_C_M 0x80000000
#define PDP_CORR_DIST1_W12_C 0x4148
#define PDP_CORR_DIST1_W12_C_M 0x3FF
#define PDP_CORR_DIST1_W13_C 0x4148
#define PDP_CORR_DIST1_W13_C_M 0xFFC00
#define PDP_CORR_DIST1_W14_C 0x4148
#define PDP_CORR_DIST1_W14_C_M 0x3FF00000
#define MANUAL_TMAX_IDX_EN_C 0x4148
#define MANUAL_TMAX_IDX_EN_C_M 0x40000000
#define PDP_CORR_DIST1_W15_C 0x414C
#define PDP_CORR_DIST1_W15_C_M 0x3FF
#define PDP_CORR_DIST1_W16_C 0x414C
#define PDP_CORR_DIST1_W16_C_M 0xFFC00
#define PDP_CORR_DIST1_W17_C 0x414C
#define PDP_CORR_DIST1_W17_C_M 0x3FF00000
#define PDP_CORR_DIST1_W18_C 0x4150
#define PDP_CORR_DIST1_W18_C_M 0x3FF
#define PDP_CORR_DIST1_W19_C 0x4150
#define PDP_CORR_DIST1_W19_C_M 0xFFC00
#define PDP_CORR_DIST1_W2_C 0x4150
#define PDP_CORR_DIST1_W2_C_M 0x3FF00000
#define PDP_CORR_DIST1_W20_C 0x4154
#define PDP_CORR_DIST1_W20_C_M 0x3FF
#define PDP_CORR_DIST1_W21_C 0x4154
#define PDP_CORR_DIST1_W21_C_M 0xFFC00
#define PDP_CORR_DIST1_W22_C 0x4154
#define PDP_CORR_DIST1_W22_C_M 0x3FF00000
#define PDP_CORR_DIST1_W23_C 0x4158
#define PDP_CORR_DIST1_W23_C_M 0x3FF
#define PDP_CORR_DIST1_W24_C 0x4158
#define PDP_CORR_DIST1_W24_C_M 0xFFC00
#define PDP_CORR_DIST1_W25_C 0x4158
#define PDP_CORR_DIST1_W25_C_M 0x3FF00000
#define PDP_CORR_DIST1_W26_C 0x415C
#define PDP_CORR_DIST1_W26_C_M 0x3FF
#define PDP_CORR_DIST1_W27_C 0x415C
#define PDP_CORR_DIST1_W27_C_M 0xFFC00
#define PDP_CORR_DIST1_W28_C 0x415C
#define PDP_CORR_DIST1_W28_C_M 0x3FF00000
#define PDP_CORR_DIST1_W29_C 0x4160
#define PDP_CORR_DIST1_W29_C_M 0x3FF
#define PDP_CORR_DIST1_W3_C 0x4160
#define PDP_CORR_DIST1_W3_C_M 0xFFC00
#define PDP_CORR_DIST1_W30_C 0x4160
#define PDP_CORR_DIST1_W30_C_M 0x3FF00000
#define PDP_CORR_DIST1_W31_C 0x4164
#define PDP_CORR_DIST1_W31_C_M 0x3FF
#define PDP_CORR_DIST1_W32_C 0x4164
#define PDP_CORR_DIST1_W32_C_M 0xFFC00
#define PDP_CORR_DIST1_W33_C 0x4164
#define PDP_CORR_DIST1_W33_C_M 0x3FF00000
#define PDP_CORR_DIST1_W34_C 0x4168
#define PDP_CORR_DIST1_W34_C_M 0x3FF
#define PDP_CORR_DIST1_W35_C 0x4168
#define PDP_CORR_DIST1_W35_C_M 0xFFC00
#define PDP_CORR_DIST1_W36_C 0x4168
#define PDP_CORR_DIST1_W36_C_M 0x3FF00000
#define PDP_CORR_DIST1_W37_C 0x416C
#define PDP_CORR_DIST1_W37_C_M 0x3FF
#define PDP_CORR_DIST1_W38_C 0x416C
#define PDP_CORR_DIST1_W38_C_M 0xFFC00
#define PDP_CORR_DIST1_W39_C 0x416C
#define PDP_CORR_DIST1_W39_C_M 0x3FF00000
#define PDP_CORR_DIST1_W4_C 0x4170
#define PDP_CORR_DIST1_W4_C_M 0x3FF
#define PDP_CORR_DIST1_W40_C 0x4170
#define PDP_CORR_DIST1_W40_C_M 0xFFC00
#define PDP_CORR_DIST1_W41_C 0x4170
#define PDP_CORR_DIST1_W41_C_M 0x3FF00000
#define PDP_CORR_DIST1_W42_C 0x4174
#define PDP_CORR_DIST1_W42_C_M 0x3FF
#define PDP_CORR_DIST1_W43_C 0x4174
#define PDP_CORR_DIST1_W43_C_M 0xFFC00
#define PDP_CORR_DIST1_W44_C 0x4174
#define PDP_CORR_DIST1_W44_C_M 0x3FF00000
#define PDP_CORR_DIST1_W45_C 0x4178
#define PDP_CORR_DIST1_W45_C_M 0x3FF
#define PDP_CORR_DIST1_W46_C 0x4178
#define PDP_CORR_DIST1_W46_C_M 0xFFC00
#define PDP_CORR_DIST1_W47_C 0x4178
#define PDP_CORR_DIST1_W47_C_M 0x3FF00000
#define PDP_CORR_DIST1_W5_C 0x417C
#define PDP_CORR_DIST1_W5_C_M 0x3FF
#define PDP_CORR_DIST1_W6_C 0x417C
#define PDP_CORR_DIST1_W6_C_M 0xFFC00
#define PDP_CORR_DIST1_W7_C 0x417C
#define PDP_CORR_DIST1_W7_C_M 0x3FF00000
#define PDP_CORR_DIST1_W8_C 0x4180
#define PDP_CORR_DIST1_W8_C_M 0x3FF
#define PDP_CORR_DIST1_W9_C 0x4180
#define PDP_CORR_DIST1_W9_C_M 0xFFC00
#define PDP_CORR_DIST2_W0_C 0x4180
#define PDP_CORR_DIST2_W0_C_M 0x3FF00000
#define PDP_CORR_DIST2_W1_C 0x4184
#define PDP_CORR_DIST2_W1_C_M 0x3FF
#define PDP_CORR_DIST2_W10_C 0x4184
#define PDP_CORR_DIST2_W10_C_M 0xFFC00
#define PDP_CORR_DIST2_W11_C 0x4184
#define PDP_CORR_DIST2_W11_C_M 0x3FF00000
#define PDP_CORR_DIST2_W12_C 0x4188
#define PDP_CORR_DIST2_W12_C_M 0x3FF
#define PDP_CORR_DIST2_W13_C 0x4188
#define PDP_CORR_DIST2_W13_C_M 0xFFC00
#define PDP_CORR_DIST2_W14_C 0x4188
#define PDP_CORR_DIST2_W14_C_M 0x3FF00000
#define PDP_CORR_DIST2_W15_C 0x418C
#define PDP_CORR_DIST2_W15_C_M 0x3FF
#define PDP_CORR_DIST2_W16_C 0x418C
#define PDP_CORR_DIST2_W16_C_M 0xFFC00
#define PDP_CORR_DIST2_W17_C 0x418C
#define PDP_CORR_DIST2_W17_C_M 0x3FF00000
#define PDP_CORR_DIST2_W18_C 0x4190
#define PDP_CORR_DIST2_W18_C_M 0x3FF
#define PDP_CORR_DIST2_W19_C 0x4190
#define PDP_CORR_DIST2_W19_C_M 0xFFC00
#define PDP_CORR_DIST2_W2_C 0x4190
#define PDP_CORR_DIST2_W2_C_M 0x3FF00000
#define PDP_CORR_DIST2_W20_C 0x4194
#define PDP_CORR_DIST2_W20_C_M 0x3FF
#define PDP_CORR_DIST2_W21_C 0x4194
#define PDP_CORR_DIST2_W21_C_M 0xFFC00
#define PDP_CORR_DIST2_W22_C 0x4194
#define PDP_CORR_DIST2_W22_C_M 0x3FF00000
#define PDP_CORR_DIST2_W23_C 0x4198
#define PDP_CORR_DIST2_W23_C_M 0x3FF
#define PDP_CORR_DIST2_W24_C 0x4198
#define PDP_CORR_DIST2_W24_C_M 0xFFC00
#define PDP_CORR_DIST2_W25_C 0x4198
#define PDP_CORR_DIST2_W25_C_M 0x3FF00000
#define PDP_CORR_DIST2_W26_C 0x419C
#define PDP_CORR_DIST2_W26_C_M 0x3FF
#define PDP_CORR_DIST2_W27_C 0x419C
#define PDP_CORR_DIST2_W27_C_M 0xFFC00
#define PDP_CORR_DIST2_W28_C 0x419C
#define PDP_CORR_DIST2_W28_C_M 0x3FF00000
#define PDP_CORR_DIST2_W29_C 0x41A0
#define PDP_CORR_DIST2_W29_C_M 0x3FF
#define PDP_CORR_DIST2_W3_C 0x41A0
#define PDP_CORR_DIST2_W3_C_M 0xFFC00
#define PDP_CORR_DIST2_W30_C 0x41A0
#define PDP_CORR_DIST2_W30_C_M 0x3FF00000
#define PDP_CORR_DIST2_W31_C 0x41A4
#define PDP_CORR_DIST2_W31_C_M 0x3FF
#define PDP_CORR_DIST2_W32_C 0x41A4
#define PDP_CORR_DIST2_W32_C_M 0xFFC00
#define PDP_CORR_DIST2_W33_C 0x41A4
#define PDP_CORR_DIST2_W33_C_M 0x3FF00000
#define PDP_CORR_DIST2_W34_C 0x41A8
#define PDP_CORR_DIST2_W34_C_M 0x3FF
#define PDP_CORR_DIST2_W35_C 0x41A8
#define PDP_CORR_DIST2_W35_C_M 0xFFC00
#define PDP_CORR_DIST2_W36_C 0x41A8
#define PDP_CORR_DIST2_W36_C_M 0x3FF00000
#define PDP_CORR_DIST2_W37_C 0x41AC
#define PDP_CORR_DIST2_W37_C_M 0x3FF
#define PDP_CORR_DIST2_W38_C 0x41AC
#define PDP_CORR_DIST2_W38_C_M 0xFFC00
#define PDP_CORR_DIST2_W39_C 0x41AC
#define PDP_CORR_DIST2_W39_C_M 0x3FF00000
#define PDP_CORR_DIST2_W4_C 0x41B0
#define PDP_CORR_DIST2_W4_C_M 0x3FF
#define PDP_CORR_DIST2_W40_C 0x41B0
#define PDP_CORR_DIST2_W40_C_M 0xFFC00
#define PDP_CORR_DIST2_W41_C 0x41B0
#define PDP_CORR_DIST2_W41_C_M 0x3FF00000
#define PDP_CORR_DIST2_W42_C 0x41B4
#define PDP_CORR_DIST2_W42_C_M 0x3FF
#define PDP_CORR_DIST2_W43_C 0x41B4
#define PDP_CORR_DIST2_W43_C_M 0xFFC00
#define PDP_CORR_DIST2_W44_C 0x41B4
#define PDP_CORR_DIST2_W44_C_M 0x3FF00000
#define PDP_CORR_DIST2_W45_C 0x41B8
#define PDP_CORR_DIST2_W45_C_M 0x3FF
#define PDP_CORR_DIST2_W46_C 0x41B8
#define PDP_CORR_DIST2_W46_C_M 0xFFC00
#define PDP_CORR_DIST2_W47_C 0x41B8
#define PDP_CORR_DIST2_W47_C_M 0x3FF00000
#define PDP_CORR_DIST2_W5_C 0x41BC
#define PDP_CORR_DIST2_W5_C_M 0x3FF
#define PDP_CORR_DIST2_W6_C 0x41BC
#define PDP_CORR_DIST2_W6_C_M 0xFFC00
#define PDP_CORR_DIST2_W7_C 0x41BC
#define PDP_CORR_DIST2_W7_C_M 0x3FF00000
#define PDP_CORR_DIST2_W8_C 0x41C0
#define PDP_CORR_DIST2_W8_C_M 0x3FF
#define PDP_CORR_DIST2_W9_C 0x41C0
#define PDP_CORR_DIST2_W9_C_M 0xFFC00
#define PDP_CORR_DIST3_W0_C 0x41C0
#define PDP_CORR_DIST3_W0_C_M 0x3FF00000
#define PDP_CORR_DIST3_W1_C 0x41C4
#define PDP_CORR_DIST3_W1_C_M 0x3FF
#define PDP_CORR_DIST3_W10_C 0x41C4
#define PDP_CORR_DIST3_W10_C_M 0xFFC00
#define PDP_CORR_DIST3_W11_C 0x41C4
#define PDP_CORR_DIST3_W11_C_M 0x3FF00000
#define PDP_CORR_DIST3_W12_C 0x41C8
#define PDP_CORR_DIST3_W12_C_M 0x3FF
#define PDP_CORR_DIST3_W13_C 0x41C8
#define PDP_CORR_DIST3_W13_C_M 0xFFC00
#define PDP_CORR_DIST3_W14_C 0x41C8
#define PDP_CORR_DIST3_W14_C_M 0x3FF00000
#define PDP_CORR_DIST3_W15_C 0x41CC
#define PDP_CORR_DIST3_W15_C_M 0x3FF
#define PDP_CORR_DIST3_W16_C 0x41CC
#define PDP_CORR_DIST3_W16_C_M 0xFFC00
#define PDP_CORR_DIST3_W17_C 0x41CC
#define PDP_CORR_DIST3_W17_C_M 0x3FF00000
#define PDP_CORR_DIST3_W18_C 0x41D0
#define PDP_CORR_DIST3_W18_C_M 0x3FF
#define PDP_CORR_DIST3_W19_C 0x41D0
#define PDP_CORR_DIST3_W19_C_M 0xFFC00
#define PDP_CORR_DIST3_W2_C 0x41D0
#define PDP_CORR_DIST3_W2_C_M 0x3FF00000
#define PDP_CORR_DIST3_W20_C 0x41D4
#define PDP_CORR_DIST3_W20_C_M 0x3FF
#define PDP_CORR_DIST3_W21_C 0x41D4
#define PDP_CORR_DIST3_W21_C_M 0xFFC00
#define PDP_CORR_DIST3_W22_C 0x41D4
#define PDP_CORR_DIST3_W22_C_M 0x3FF00000
#define PDP_CORR_DIST3_W23_C 0x41D8
#define PDP_CORR_DIST3_W23_C_M 0x3FF
#define PDP_CORR_DIST3_W24_C 0x41D8
#define PDP_CORR_DIST3_W24_C_M 0xFFC00
#define PDP_CORR_DIST3_W25_C 0x41D8
#define PDP_CORR_DIST3_W25_C_M 0x3FF00000
#define PDP_CORR_DIST3_W26_C 0x41DC
#define PDP_CORR_DIST3_W26_C_M 0x3FF
#define PDP_CORR_DIST3_W27_C 0x41DC
#define PDP_CORR_DIST3_W27_C_M 0xFFC00
#define PDP_CORR_DIST3_W28_C 0x41DC
#define PDP_CORR_DIST3_W28_C_M 0x3FF00000
#define PDP_CORR_DIST3_W29_C 0x41E0
#define PDP_CORR_DIST3_W29_C_M 0x3FF
#define PDP_CORR_DIST3_W3_C 0x41E0
#define PDP_CORR_DIST3_W3_C_M 0xFFC00
#define PDP_CORR_DIST3_W30_C 0x41E0
#define PDP_CORR_DIST3_W30_C_M 0x3FF00000
#define PDP_CORR_DIST3_W31_C 0x41E4
#define PDP_CORR_DIST3_W31_C_M 0x3FF
#define PDP_CORR_DIST3_W32_C 0x41E4
#define PDP_CORR_DIST3_W32_C_M 0xFFC00
#define PDP_CORR_DIST3_W33_C 0x41E4
#define PDP_CORR_DIST3_W33_C_M 0x3FF00000
#define PDP_CORR_DIST3_W34_C 0x41E8
#define PDP_CORR_DIST3_W34_C_M 0x3FF
#define PDP_CORR_DIST3_W35_C 0x41E8
#define PDP_CORR_DIST3_W35_C_M 0xFFC00
#define PDP_CORR_DIST3_W36_C 0x41E8
#define PDP_CORR_DIST3_W36_C_M 0x3FF00000
#define PDP_CORR_DIST3_W37_C 0x41EC
#define PDP_CORR_DIST3_W37_C_M 0x3FF
#define PDP_CORR_DIST3_W38_C 0x41EC
#define PDP_CORR_DIST3_W38_C_M 0xFFC00
#define PDP_CORR_DIST3_W39_C 0x41EC
#define PDP_CORR_DIST3_W39_C_M 0x3FF00000
#define PDP_CORR_DIST3_W4_C 0x41F0
#define PDP_CORR_DIST3_W4_C_M 0x3FF
#define PDP_CORR_DIST3_W40_C 0x41F0
#define PDP_CORR_DIST3_W40_C_M 0xFFC00
#define PDP_CORR_DIST3_W41_C 0x41F0
#define PDP_CORR_DIST3_W41_C_M 0x3FF00000
#define PDP_CORR_DIST3_W42_C 0x41F4
#define PDP_CORR_DIST3_W42_C_M 0x3FF
#define PDP_CORR_DIST3_W43_C 0x41F4
#define PDP_CORR_DIST3_W43_C_M 0xFFC00
#define PDP_CORR_DIST3_W44_C 0x41F4
#define PDP_CORR_DIST3_W44_C_M 0x3FF00000
#define PDP_CORR_DIST3_W45_C 0x41F8
#define PDP_CORR_DIST3_W45_C_M 0x3FF
#define PDP_CORR_DIST3_W46_C 0x41F8
#define PDP_CORR_DIST3_W46_C_M 0xFFC00
#define PDP_CORR_DIST3_W47_C 0x41F8
#define PDP_CORR_DIST3_W47_C_M 0x3FF00000
#define PDP_CORR_DIST3_W5_C 0x41FC
#define PDP_CORR_DIST3_W5_C_M 0x3FF
#define PDP_CORR_DIST3_W6_C 0x41FC
#define PDP_CORR_DIST3_W6_C_M 0xFFC00
#define PDP_CORR_DIST3_W7_C 0x41FC
#define PDP_CORR_DIST3_W7_C_M 0x3FF00000
#define PDP_CORR_DIST3_W8_C 0x4200
#define PDP_CORR_DIST3_W8_C_M 0x3FF
#define PDP_CORR_DIST3_W9_C 0x4200
#define PDP_CORR_DIST3_W9_C_M 0xFFC00
#define GD_PHASE_LEG_R0S0_C 0x4200
#define GD_PHASE_LEG_R0S0_C_M 0xFF00000
#define TMAX_IDX_LEG_R0_C 0x4200
#define TMAX_IDX_LEG_R0_C_M 0xF0000000
#define GD_PHASE_LEG_R0S1_C 0x4204
#define GD_PHASE_LEG_R0S1_C_M 0xFF
#define GD_PHASE_LEG_R0S2_C 0x4204
#define GD_PHASE_LEG_R0S2_C_M 0xFF00
#define GD_PHASE_LEG_R0S3_C 0x4204
#define GD_PHASE_LEG_R0S3_C_M 0xFF0000
#define GD_PHASE_LEG_R1S0_C 0x4204
#define GD_PHASE_LEG_R1S0_C_M 0xFF000000
#define GD_PHASE_LEG_R1S1_C 0x4208
#define GD_PHASE_LEG_R1S1_C_M 0xFF
#define GD_PHASE_LEG_R1S2_C 0x4208
#define GD_PHASE_LEG_R1S2_C_M 0xFF00
#define GD_PHASE_LEG_R1S3_C 0x4208
#define GD_PHASE_LEG_R1S3_C_M 0xFF0000
#define GD_PHASE_NON_LEG_R0S0_C 0x4208
#define GD_PHASE_NON_LEG_R0S0_C_M 0xFF000000
#define GD_PHASE_NON_LEG_R0S1_C 0x420C
#define GD_PHASE_NON_LEG_R0S1_C_M 0xFF
#define GD_PHASE_NON_LEG_R1S0_C 0x420C
#define GD_PHASE_NON_LEG_R1S0_C_M 0xFF00
#define GD_PHASE_NON_LEG_R1S1_C 0x420C
#define GD_PHASE_NON_LEG_R1S1_C_M 0xFF0000
#define GI_FCTR_LEGACY_0_C 0x420C
#define GI_FCTR_LEGACY_0_C_M 0x7F000000
#define GI_FCTR_LEGACY_1_C 0x4210
#define GI_FCTR_LEGACY_1_C_M 0x7F
#define GI_FCTR_LEGACY_2_C 0x4210
#define GI_FCTR_LEGACY_2_C_M 0x3F80
#define GI_FCTR_LEGACY_3_C 0x4210
#define GI_FCTR_LEGACY_3_C_M 0x1FC000
#define GI_FCTR_LEGACY_4_C 0x4210
#define GI_FCTR_LEGACY_4_C_M 0xFE00000
#define TMAX_IDX_LEG_R1_C 0x4210
#define TMAX_IDX_LEG_R1_C_M 0xF0000000
#define GI_FCTR_LEGACY_5_C 0x4214
#define GI_FCTR_LEGACY_5_C_M 0x7F
#define GI_FCTR_NONLEGACY_0_C 0x4214
#define GI_FCTR_NONLEGACY_0_C_M 0x3F80
#define GI_FCTR_NONLEGACY_1_C 0x4214
#define GI_FCTR_NONLEGACY_1_C_M 0x1FC000
#define GI_FCTR_NONLEGACY_2_C 0x4214
#define GI_FCTR_NONLEGACY_2_C_M 0xFE00000
#define TMAX_IDX_NON_LEG_R0_C 0x4214
#define TMAX_IDX_NON_LEG_R0_C_M 0xF0000000
#define GI_FCTR_NONLEGACY_3_C 0x4218
#define GI_FCTR_NONLEGACY_3_C_M 0x7F
#define GI_FCTR_NONLEGACY_4_C 0x4218
#define GI_FCTR_NONLEGACY_4_C_M 0x3F80
#define GI_FCTR_NONLEGACY_5_C 0x4218
#define GI_FCTR_NONLEGACY_5_C_M 0x1FC000
#define SNR_LVL_0_C 0x4218
#define SNR_LVL_0_C_M 0x7E00000
#define HE_NUM_BAND_EDGE_TONE_C 0x4218
#define HE_NUM_BAND_EDGE_TONE_C_M 0xF8000000
#define SNR_LVL_1_C 0x421C
#define SNR_LVL_1_C_M 0x3F
#define SNR_LVL_2_C 0x421C
#define SNR_LVL_2_C_M 0xFC0
#define SNR_LVL_3_C 0x421C
#define SNR_LVL_3_C_M 0x3F000
#define SNR_LVL_4_C 0x421C
#define SNR_LVL_4_C_M 0xFC0000
#define SNR_LVL_5_C 0x421C
#define SNR_LVL_5_C_M 0x3F000000
#define SNR_SMO_THR_C 0x4220
#define SNR_SMO_THR_C_M 0x3F
#define SNR_SMO_THR_1XLTF_C 0x4220
#define SNR_SMO_THR_1XLTF_C_M 0xFC0
#define SNR_SMO_THR_2XLTF_C 0x4220
#define SNR_SMO_THR_2XLTF_C_M 0x3F000
#define PDP_INSIDE_PHASE_ROTATE_C 0x4220
#define PDP_INSIDE_PHASE_ROTATE_C_M 0x7C0000
#define PDP_WGT_DIST_1X_C 0x4220
#define PDP_WGT_DIST_1X_C_M 0xF800000
#define TMAX_IDX_NON_LEG_R0S0_C 0x4220
#define TMAX_IDX_NON_LEG_R0S0_C_M 0xF0000000
#define PDP_WGT_DIST_2X_C 0x4224
#define PDP_WGT_DIST_2X_C_M 0x1F
#define PDP_WGT_DIST_3X_C 0x4224
#define PDP_WGT_DIST_3X_C_M 0x3E0
#define TMAX_IDX_NON_LEG_R0S1_C 0x4224
#define TMAX_IDX_NON_LEG_R0S1_C_M 0x3C00
#define TMAX_IDX_NON_LEG_R1S0_C 0x4224
#define TMAX_IDX_NON_LEG_R1S0_C_M 0x3C000
#define TMAX_IDX_NON_LEG_R1S1_C 0x4224
#define TMAX_IDX_NON_LEG_R1S1_C_M 0x3C0000
#define SNR_IDX_LEG_R0_C 0x4224
#define SNR_IDX_LEG_R0_C_M 0x1C00000
#define SNR_IDX_LEG_R1_C 0x4224
#define SNR_IDX_LEG_R1_C_M 0xE000000
#define SNR_IDX_NON_LEG_R0S0_C 0x4224
#define SNR_IDX_NON_LEG_R0S0_C_M 0x70000000
#define SNR_IDX_NON_LEG_R0S1_C 0x4228
#define SNR_IDX_NON_LEG_R0S1_C_M 0x7
#define SNR_IDX_NON_LEG_R1S0_C 0x4228
#define SNR_IDX_NON_LEG_R1S0_C_M 0x38
#define SNR_IDX_NON_LEG_R1S1_C 0x4228
#define SNR_IDX_NON_LEG_R1S1_C_M 0x1C0
#define NUM_BAND_EDGE_TONE_C 0x4228
#define NUM_BAND_EDGE_TONE_C_M 0xE00
#define PHYSTS_PDP_HE_AND_GI_TYPE_0_C 0x4228
#define PHYSTS_PDP_HE_AND_GI_TYPE_0_C_M 0x7000
#define PHYSTS_PDP_HE_AND_GI_TYPE_1_C 0x4228
#define PHYSTS_PDP_HE_AND_GI_TYPE_1_C_M 0x38000
#define PHYSTS_PDP_HE_AND_GI_TYPE_2_C 0x4228
#define PHYSTS_PDP_HE_AND_GI_TYPE_2_C_M 0x1C0000
#define PHYSTS_PDP_HE_AND_GI_TYPE_3_C 0x4228
#define PHYSTS_PDP_HE_AND_GI_TYPE_3_C_M 0xE00000
#define PHYSTS_PDP_HE_AND_GI_TYPE_4_C 0x4228
#define PHYSTS_PDP_HE_AND_GI_TYPE_4_C_M 0x7000000
#define PSD_FFT_IDX_C 0x422C
#define PSD_FFT_IDX_C_M 0x7FF
#define PSD_IQ_SEL_C 0x422C
#define PSD_IQ_SEL_C_M 0x1800
#define PSD_L_AVG_C 0x422C
#define PSD_L_AVG_C_M 0x6000
#define PSD_N_DFT_C 0x422C
#define PSD_N_DFT_C_M 0x18000
#define PSD_IN_PATH_SEL_C 0x422C
#define PSD_IN_PATH_SEL_C_M 0x60000
#define PSD_IN_SOURCE_SEL_C 0x422C
#define PSD_IN_SOURCE_SEL_C_M 0x180000
#define PSD_START_C 0x422C
#define PSD_START_C_M 0x200000
#define PSD_ENABLE_C 0x422C
#define PSD_ENABLE_C_M 0x400000
#define K_SEL_1024QAM_SNR_TH1_C 0x4230
#define K_SEL_1024QAM_SNR_TH1_C_M 0x3F
#define K_SEL_1024QAM_SNR_TH2_C 0x4230
#define K_SEL_1024QAM_SNR_TH2_C_M 0xFC0
#define K_SEL_1024QAM_SNR_TH3_C 0x4230
#define K_SEL_1024QAM_SNR_TH3_C_M 0x3F000
#define K_SEL_1024QAM_SNR_TH4_C 0x4230
#define K_SEL_1024QAM_SNR_TH4_C_M 0xFC0000
#define K_SEL_1024QAM_SNR_TH5_C 0x4230
#define K_SEL_1024QAM_SNR_TH5_C_M 0x3F000000
#define K_SEL_EN_C 0x4230
#define K_SEL_EN_C_M 0x40000000
#define K_SEL_USE_CONDNUM_EN_C 0x4230
#define K_SEL_USE_CONDNUM_EN_C_M 0x80000000
#define K_SEL_16QAM_SNR_TH1_C 0x4234
#define K_SEL_16QAM_SNR_TH1_C_M 0x3F
#define K_SEL_16QAM_SNR_TH2_C 0x4234
#define K_SEL_16QAM_SNR_TH2_C_M 0xFC0
#define K_SEL_16QAM_SNR_TH3_C 0x4234
#define K_SEL_16QAM_SNR_TH3_C_M 0x3F000
#define K_SEL_256QAM_SNR_TH1_C 0x4234
#define K_SEL_256QAM_SNR_TH1_C_M 0xFC0000
#define K_SEL_256QAM_SNR_TH2_C 0x4234
#define K_SEL_256QAM_SNR_TH2_C_M 0x3F000000
#define MANUAL_SET_K_FCTR_C 0x4234
#define MANUAL_SET_K_FCTR_C_M 0x40000000
#define K_SEL_256QAM_SNR_TH3_C 0x4238
#define K_SEL_256QAM_SNR_TH3_C_M 0x3F
#define K_SEL_256QAM_SNR_TH4_C 0x4238
#define K_SEL_256QAM_SNR_TH4_C_M 0xFC0
#define K_SEL_256QAM_SNR_TH5_C 0x4238
#define K_SEL_256QAM_SNR_TH5_C_M 0x3F000
#define K_SEL_64QAM_SNR_TH1_C 0x4238
#define K_SEL_64QAM_SNR_TH1_C_M 0xFC0000
#define K_SEL_64QAM_SNR_TH2_C 0x4238
#define K_SEL_64QAM_SNR_TH2_C_M 0x3F000000
#define K_SEL_64QAM_SNR_TH3_C 0x423C
#define K_SEL_64QAM_SNR_TH3_C_M 0x3F
#define K_SEL_64QAM_SNR_TH4_C 0x423C
#define K_SEL_64QAM_SNR_TH4_C_M 0xFC0
#define K_SEL_64QAM_SNR_TH5_C 0x423C
#define K_SEL_64QAM_SNR_TH5_C_M 0x3F000
#define K_SEL_1024QAM_CH_C 0x423C
#define K_SEL_1024QAM_CH_C_M 0x1C0000
#define K_SEL_1024QAM_L1_C 0x423C
#define K_SEL_1024QAM_L1_C_M 0xE00000
#define K_SEL_1024QAM_L2_C 0x423C
#define K_SEL_1024QAM_L2_C_M 0x7000000
#define K_SEL_1024QAM_L3_C 0x423C
#define K_SEL_1024QAM_L3_C_M 0x38000000
#define K_SEL_1024QAM_L4_C 0x4240
#define K_SEL_1024QAM_L4_C_M 0x7
#define K_SEL_1024QAM_L5_C 0x4240
#define K_SEL_1024QAM_L5_C_M 0x38
#define K_SEL_1024QAM_CONDNUM_TH_C 0x4240
#define K_SEL_1024QAM_CONDNUM_TH_C_M 0x1C0
#define K_SEL_16QAM_CH_C 0x4240
#define K_SEL_16QAM_CH_C_M 0xE00
#define K_SEL_16QAM_L1_C 0x4240
#define K_SEL_16QAM_L1_C_M 0x7000
#define K_SEL_16QAM_L2_C 0x4240
#define K_SEL_16QAM_L2_C_M 0x38000
#define K_SEL_16QAM_L3_C 0x4240
#define K_SEL_16QAM_L3_C_M 0x1C0000
#define K_SEL_16QAM_CONDNUM_TH_C 0x4240
#define K_SEL_16QAM_CONDNUM_TH_C_M 0xE00000
#define K_SEL_256QAM_CH_C 0x4240
#define K_SEL_256QAM_CH_C_M 0x7000000
#define K_SEL_256QAM_L1_C 0x4240
#define K_SEL_256QAM_L1_C_M 0x38000000
#define K_SEL_256QAM_L2_C 0x4244
#define K_SEL_256QAM_L2_C_M 0x7
#define K_SEL_256QAM_L3_C 0x4244
#define K_SEL_256QAM_L3_C_M 0x38
#define K_SEL_256QAM_L4_C 0x4244
#define K_SEL_256QAM_L4_C_M 0x1C0
#define K_SEL_256QAM_L5_C 0x4244
#define K_SEL_256QAM_L5_C_M 0xE00
#define K_SEL_256QAM_CONDNUM_TH_C 0x4244
#define K_SEL_256QAM_CONDNUM_TH_C_M 0x7000
#define K_SEL_64QAM_CH_C 0x4244
#define K_SEL_64QAM_CH_C_M 0x38000
#define K_SEL_64QAM_L1_C 0x4244
#define K_SEL_64QAM_L1_C_M 0x1C0000
#define K_SEL_64QAM_L2_C 0x4244
#define K_SEL_64QAM_L2_C_M 0xE00000
#define K_SEL_64QAM_L3_C 0x4244
#define K_SEL_64QAM_L3_C_M 0x7000000
#define K_SEL_64QAM_L4_C 0x4244
#define K_SEL_64QAM_L4_C_M 0x38000000
#define K_SEL_64QAM_L5_C 0x4248
#define K_SEL_64QAM_L5_C_M 0x7
#define K_SEL_64QAM_CONDNUM_TH_C 0x4248
#define K_SEL_64QAM_CONDNUM_TH_C_M 0x38
#define INDI_QBPSK_CHK_EN_C 0x424C
#define INDI_QBPSK_CHK_EN_C_M 0x1
#define CHK_BFSNR_QUANTIZATION_ERROR_EN_C 0x4250
#define CHK_BFSNR_QUANTIZATION_ERROR_EN_C_M 0x1
#define MPDU_OK_CNT_USR0_TAR_CONTENT_C 0x4258
#define MPDU_OK_CNT_USR0_TAR_CONTENT_C_M 0xFFFF
#define MPDU_OK_CNT_USR1_TAR_CONTENT_C 0x4258
#define MPDU_OK_CNT_USR1_TAR_CONTENT_C_M 0xFFFF0000
#define MPDU_OK_CNT_USR2_TAR_CONTENT_C 0x425C
#define MPDU_OK_CNT_USR2_TAR_CONTENT_C_M 0xFFFF
#define MPDU_OK_CNT_USR3_TAR_CONTENT_C 0x425C
#define MPDU_OK_CNT_USR3_TAR_CONTENT_C_M 0xFFFF0000
#define TARGET_FRAME_TYPE_C 0x4260
#define TARGET_FRAME_TYPE_C_M 0xFF
#define TARGET_MAC_ADDRESS_8BITS_C 0x4260
#define TARGET_MAC_ADDRESS_8BITS_C_M 0xFF00
#define MPDU_OK_CNT_MODE_C 0x4260
#define MPDU_OK_CNT_MODE_C_M 0x70000
#define VHT_USR_POSITION_C 0x4260
#define VHT_USR_POSITION_C_M 0x180000
#define MPDU_OK_CNT_USR0_EN_C 0x4260
#define MPDU_OK_CNT_USR0_EN_C_M 0x200000
#define MPDU_OK_CNT_USR1_EN_C 0x4260
#define MPDU_OK_CNT_USR1_EN_C_M 0x400000
#define MPDU_OK_CNT_USR2_EN_C 0x4260
#define MPDU_OK_CNT_USR2_EN_C_M 0x800000
#define MPDU_OK_CNT_USR3_EN_C 0x4260
#define MPDU_OK_CNT_USR3_EN_C_M 0x1000000
#define TARGET_FRAME_TYPE_EN_C 0x4260
#define TARGET_FRAME_TYPE_EN_C_M 0x2000000
#define TARGET_MAC_ADDRESS_LSB_EN_C 0x4260
#define TARGET_MAC_ADDRESS_LSB_EN_C_M 0x4000000
#define MANUAL_TD_CFO_SEG0_C 0x426C
#define MANUAL_TD_CFO_SEG0_C_M 0xFFF
#define MANUAL_TD_CFO_SEG1_C 0x426C
#define MANUAL_TD_CFO_SEG1_C_M 0xFFF000
#define SBDRDY_WINDOW_LEN_C 0x426C
#define SBDRDY_WINDOW_LEN_C_M 0x7000000
#define MANUAL_TD_CFO_EN_C 0x426C
#define MANUAL_TD_CFO_EN_C_M 0x8000000
#define EARLY_TERMINATION_TH_0_C 0x4270
#define EARLY_TERMINATION_TH_0_C_M 0xF
#define EARLY_TERMINATION_TH_1_C 0x4270
#define EARLY_TERMINATION_TH_1_C_M 0xF0
#define EARLY_TERMINATION_TH_2_C 0x4270
#define EARLY_TERMINATION_TH_2_C_M 0xF00
#define EARLY_TERMINATION_TH_3_C 0x4270
#define EARLY_TERMINATION_TH_3_C_M 0xF000
#define ED_C1_TH_C 0x4270
#define ED_C1_TH_C_M 0xF0000
#define ED_C0_TH_C 0x4270
#define ED_C0_TH_C_M 0x700000
#define LDPC_SCAL_FCTR_C 0x4270
#define LDPC_SCAL_FCTR_C_M 0x1800000
#define EARLY_TERMINATION_BACKWARD_STEP_C 0x4270
#define EARLY_TERMINATION_BACKWARD_STEP_C_M 0x6000000
#define EARLY_TERMINATION_FORWARD_STEP_C 0x4270
#define EARLY_TERMINATION_FORWARD_STEP_C_M 0x18000000
#define LLR_SYNDROME_CHK_EN_C 0x4270
#define LLR_SYNDROME_CHK_EN_C_M 0x20000000
#define EARLY_DROP_C0_EN_C 0x4270
#define EARLY_DROP_C0_EN_C_M 0x40000000
#define EARLY_DROP_C1_EN_C 0x4270
#define EARLY_DROP_C1_EN_C_M 0x80000000
#define EARLY_DROP_C2_EN_C 0x4274
#define EARLY_DROP_C2_EN_C_M 0x1
#define EARLY_TERMINATION_EN_C 0x4274
#define EARLY_TERMINATION_EN_C_M 0x2
#define TBCOMCT_RXTIME_C 0x4278
#define TBCOMCT_RXTIME_C_M 0x7FFF
#define TBCOMCT_N_SYM_C 0x4278
#define TBCOMCT_N_SYM_C_M 0x3FF8000
#define TBUSRCT0_MCS_C 0x4278
#define TBUSRCT0_MCS_C_M 0x3C000000
#define TBCOMCT_DBW_IDX_C 0x4278
#define TBCOMCT_DBW_IDX_C_M 0xC0000000
#define TBCOMCT_N_USR_C 0x427C
#define TBCOMCT_N_USR_C_M 0xFF
#define TBUSRCT0_RU_ALLOC_C 0x427C
#define TBUSRCT0_RU_ALLOC_C_M 0xFF00
#define TBUSRCT0_U_ID_C 0x427C
#define TBUSRCT0_U_ID_C_M 0xFF0000
#define TBUSRCT1_RU_ALLOC_C 0x427C
#define TBUSRCT1_RU_ALLOC_C_M 0xFF000000
#define TBUSRCT1_U_ID_C 0x4280
#define TBUSRCT1_U_ID_C_M 0xFF
#define TBUSRCT2_RU_ALLOC_C 0x4280
#define TBUSRCT2_RU_ALLOC_C_M 0xFF00
#define TBUSRCT2_U_ID_C 0x4280
#define TBUSRCT2_U_ID_C_M 0xFF0000
#define TBUSRCT3_RU_ALLOC_C 0x4280
#define TBUSRCT3_RU_ALLOC_C_M 0xFF000000
#define TBUSRCT3_U_ID_C 0x4284
#define TBUSRCT3_U_ID_C_M 0xFF
#define TBUSRCT1_MCS_C 0x4284
#define TBUSRCT1_MCS_C_M 0xF00
#define TBUSRCT2_MCS_C 0x4284
#define TBUSRCT2_MCS_C_M 0xF000
#define TBUSRCT3_MCS_C 0x4284
#define TBUSRCT3_MCS_C_M 0xF0000
#define TBCOMCT_N_LTF_C 0x4284
#define TBCOMCT_N_LTF_C_M 0x700000
#define TBCOMCT_PKT_EXT_IDX_C 0x4284
#define TBCOMCT_PKT_EXT_IDX_C_M 0x3800000
#define TBUSRCT0_N_STS_C 0x4284
#define TBUSRCT0_N_STS_C_M 0x1C000000
#define TBUSRCT0_N_STS_RU_TOT_C 0x4284
#define TBUSRCT0_N_STS_RU_TOT_C_M 0xE0000000
#define TBUSRCT0_STRT_STS_C 0x4288
#define TBUSRCT0_STRT_STS_C_M 0x7
#define TBUSRCT1_N_STS_C 0x4288
#define TBUSRCT1_N_STS_C_M 0x38
#define TBUSRCT1_N_STS_RU_TOT_C 0x4288
#define TBUSRCT1_N_STS_RU_TOT_C_M 0x1C0
#define TBUSRCT1_STRT_STS_C 0x4288
#define TBUSRCT1_STRT_STS_C_M 0xE00
#define TBUSRCT2_N_STS_C 0x4288
#define TBUSRCT2_N_STS_C_M 0x7000
#define TBUSRCT2_N_STS_RU_TOT_C 0x4288
#define TBUSRCT2_N_STS_RU_TOT_C_M 0x38000
#define TBUSRCT2_STRT_STS_C 0x4288
#define TBUSRCT2_STRT_STS_C_M 0x1C0000
#define TBUSRCT3_N_STS_C 0x4288
#define TBUSRCT3_N_STS_C_M 0xE00000
#define TBUSRCT3_N_STS_RU_TOT_C 0x4288
#define TBUSRCT3_N_STS_RU_TOT_C_M 0x7000000
#define TBUSRCT3_STRT_STS_C 0x4288
#define TBUSRCT3_STRT_STS_C_M 0x38000000
#define TBCOMCT_GI_TYPE_C 0x4288
#define TBCOMCT_GI_TYPE_C_M 0xC0000000
#define TBCOMCT_LTF_TYPE_C 0x428C
#define TBCOMCT_LTF_TYPE_C_M 0x3
#define TBCOMCT_PRE_FEC_FCTR_C 0x428C
#define TBCOMCT_PRE_FEC_FCTR_C_M 0xC
#define PPDU_STANDBY_C 0x428C
#define PPDU_STANDBY_C_M 0x10
#define TBCOMCT_DOPPLER_EN_C 0x428C
#define TBCOMCT_DOPPLER_EN_C_M 0x20
#define TBCOMCT_LDPC_EXTR_C 0x428C
#define TBCOMCT_LDPC_EXTR_C_M 0x40
#define TBCOMCT_MIDAMBLE_MODE_C 0x428C
#define TBCOMCT_MIDAMBLE_MODE_C_M 0x80
#define TBCOMCT_MUMIMO_LTF_MODE_EN_C 0x428C
#define TBCOMCT_MUMIMO_LTF_MODE_EN_C_M 0x100
#define TBCOMCT_NDP_C 0x428C
#define TBCOMCT_NDP_C_M 0x200
#define TBCOMCT_STBC_EN_C 0x428C
#define TBCOMCT_STBC_EN_C_M 0x400
#define TBUSRCT0_DCM_EN_C 0x428C
#define TBUSRCT0_DCM_EN_C_M 0x800
#define TBUSRCT0_FEC_TYPE_C 0x428C
#define TBUSRCT0_FEC_TYPE_C_M 0x1000
#define TBUSRCT1_DCM_EN_C 0x428C
#define TBUSRCT1_DCM_EN_C_M 0x2000
#define TBUSRCT1_FEC_TYPE_C 0x428C
#define TBUSRCT1_FEC_TYPE_C_M 0x4000
#define TBUSRCT2_DCM_EN_C 0x428C
#define TBUSRCT2_DCM_EN_C_M 0x8000
#define TBUSRCT2_FEC_TYPE_C 0x428C
#define TBUSRCT2_FEC_TYPE_C_M 0x10000
#define TBUSRCT3_DCM_EN_C 0x428C
#define TBUSRCT3_DCM_EN_C_M 0x20000
#define TBUSRCT3_FEC_TYPE_C 0x428C
#define TBUSRCT3_FEC_TYPE_C_M 0x40000
#define COLLISION_USR_SNR_DET_TH_C 0x429C
#define COLLISION_USR_SNR_DET_TH_C_M 0x3FF
#define COLLISION_USR_PW_DET_TH_C 0x429C
#define COLLISION_USR_PW_DET_TH_C_M 0x7FC00
#define EMPTY_USR_PW_DET_TH_C 0x429C
#define EMPTY_USR_PW_DET_TH_C_M 0xFF80000
#define HESIGB_EXTRA_PHASE_SCAL_FCTR_C 0x429C
#define HESIGB_EXTRA_PHASE_SCAL_FCTR_C_M 0xF0000000
#define LLR_NVAR_SCAL_C 0x42A0
#define LLR_NVAR_SCAL_C_M 0x3F
#define HE_20M_STA_CH_ALLOC_C 0x42A0
#define HE_20M_STA_CH_ALLOC_C_M 0x3C0
#define BWD_S80_THD_C 0x42A0
#define BWD_S80_THD_C_M 0x1C00
#define LLR_NVAR_SEL_C 0x42A0
#define LLR_NVAR_SEL_C_M 0x6000
#define CHSMO_EN_C 0x42A0
#define CHSMO_EN_C_M 0x8000
#define CHSMO_IDX_MOD_EN_C 0x42A0
#define CHSMO_IDX_MOD_EN_C_M 0x10000
#define HE_20M_STA_EN_C 0x42A0
#define HE_20M_STA_EN_C_M 0x20000
#define HE_TB_STF_CFO_EST_EN_C 0x42A0
#define HE_TB_STF_CFO_EST_EN_C_M 0x40000
#define L2_CFO_TRACKING_EN_C 0x42A0
#define L2_CFO_TRACKING_EN_C_M 0x80000
#define LNA_BASED_TRK_UPD_EN_C 0x42A0
#define LNA_BASED_TRK_UPD_EN_C_M 0x100000
#define COLLISION_USR_STAT_DET_EN_C 0x42A0
#define COLLISION_USR_STAT_DET_EN_C_M 0x200000
#define EMPTY_USR_PW_DET_NON_TB_EN_C 0x42A0
#define EMPTY_USR_PW_DET_NON_TB_EN_C_M 0x400000
#define SIGVAL_RPT_EN_C 0x42A0
#define SIGVAL_RPT_EN_C_M 0x800000
#define STBC_CH_CONSIST_EN_C 0x42A0
#define STBC_CH_CONSIST_EN_C_M 0x1000000
#define TRK_UPD_EN_PLCP_FORCE_ON_C 0x42A0
#define TRK_UPD_EN_PLCP_FORCE_ON_C_M 0x2000000
#define RU_END_IDX_C 0x42A4
#define RU_END_IDX_C_M 0x7F
#define RU_START_IDX_C 0x42A4
#define RU_START_IDX_C_M 0x3F80
#define RX_NR_C 0x42A4
#define RX_NR_C_M 0x1C000
#define HT_CB_C 0x42A4
#define HT_CB_C_M 0x60000
#define NDPA_FEEDBACK_TYPE_C 0x42A4
#define NDPA_FEEDBACK_TYPE_C_M 0x180000
#define RX_NG_C 0x42A4
#define RX_NG_C_M 0x600000
#define RX_NC_C 0x42A4
#define RX_NC_C_M 0x800000
#define VHT_HE_CB_C 0x42A4
#define VHT_HE_CB_C_M 0x1000000
#define CSI_PARA_EN_C 0x42A4
#define CSI_PARA_EN_C_M 0x2000000
#define SEG0_SET1_CSI_WGT_TONE_IDX_C 0x42B0
#define SEG0_SET1_CSI_WGT_TONE_IDX_C_M 0x7FF
#define SEG0_SET2_CSI_WGT_TONE_IDX_C 0x42B0
#define SEG0_SET2_CSI_WGT_TONE_IDX_C_M 0x3FF800
#define CFO_CSI_WGT_TH_C 0x42B0
#define CFO_CSI_WGT_TH_C_M 0x1C00000
#define CFO_CSI_WGT_VAL_C 0x42B0
#define CFO_CSI_WGT_VAL_C_M 0xE000000
#define CSI_MASK_TH_C 0x42B0
#define CSI_MASK_TH_C_M 0x70000000
#define CFO_CSI_WGT_EN_C 0x42B0
#define CFO_CSI_WGT_EN_C_M 0x80000000
#define SEG1_SET1_CSI_WGT_TONE_IDX_C 0x42B4
#define SEG1_SET1_CSI_WGT_TONE_IDX_C_M 0x7FF
#define SEG1_SET2_CSI_WGT_TONE_IDX_C 0x42B4
#define SEG1_SET2_CSI_WGT_TONE_IDX_C_M 0x3FF800
#define CSI_WGT_RSSI_TH_C 0x42B4
#define CSI_WGT_RSSI_TH_C_M 0x1C00000
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE0_C 0x42B4
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE0_C_M 0xE000000
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE1_C 0x42B4
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE1_C_M 0x70000000
#define CSI_WGT_4X_MORE_EN_C 0x42B4
#define CSI_WGT_4X_MORE_EN_C_M 0x80000000
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE2_C 0x42B8
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE2_C_M 0x7
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE3_C 0x42B8
#define SEG0_SET1_CSI_WGT_1X_VAL_TONE3_C_M 0x38
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE0_C 0x42B8
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE0_C_M 0x1C0
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE1_C 0x42B8
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE1_C_M 0xE00
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE2_C 0x42B8
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE2_C_M 0x7000
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE3_C 0x42B8
#define SEG0_SET1_CSI_WGT_2X_VAL_TONE3_C_M 0x38000
#define SEG0_SET1_CSI_WGT_4X_MORE_LFT_TONES_C 0x42B8
#define SEG0_SET1_CSI_WGT_4X_MORE_LFT_TONES_C_M 0x1C0000
#define SEG0_SET1_CSI_WGT_4X_MORE_RHT_TONES_C 0x42B8
#define SEG0_SET1_CSI_WGT_4X_MORE_RHT_TONES_C_M 0xE00000
#define SEG0_SET1_CSI_WGT_VAL_TONE0_C 0x42B8
#define SEG0_SET1_CSI_WGT_VAL_TONE0_C_M 0x7000000
#define SEG0_SET1_CSI_WGT_VAL_TONE1_C 0x42B8
#define SEG0_SET1_CSI_WGT_VAL_TONE1_C_M 0x38000000
#define SEG0_SET1_CSI_WGT_1X_LFT_TONES_C 0x42B8
#define SEG0_SET1_CSI_WGT_1X_LFT_TONES_C_M 0xC0000000
#define SEG0_SET1_CSI_WGT_VAL_TONE2_C 0x42BC
#define SEG0_SET1_CSI_WGT_VAL_TONE2_C_M 0x7
#define SEG0_SET1_CSI_WGT_VAL_TONE3_C 0x42BC
#define SEG0_SET1_CSI_WGT_VAL_TONE3_C_M 0x38
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE0_C 0x42BC
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE0_C_M 0x1C0
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE1_C 0x42BC
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE1_C_M 0xE00
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE2_C 0x42BC
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE2_C_M 0x7000
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE3_C 0x42BC
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE3_C_M 0x38000
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE0_C 0x42BC
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE0_C_M 0x1C0000
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE1_C 0x42BC
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE1_C_M 0xE00000
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE2_C 0x42BC
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE2_C_M 0x7000000
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE3_C 0x42BC
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE3_C_M 0x38000000
#define SEG0_SET1_CSI_WGT_1X_RHT_TONES_C 0x42BC
#define SEG0_SET1_CSI_WGT_1X_RHT_TONES_C_M 0xC0000000
#define SEG0_SET2_CSI_WGT_4X_MORE_LFT_TONES_C 0x42C0
#define SEG0_SET2_CSI_WGT_4X_MORE_LFT_TONES_C_M 0x7
#define SEG0_SET2_CSI_WGT_4X_MORE_RHT_TONES_C 0x42C0
#define SEG0_SET2_CSI_WGT_4X_MORE_RHT_TONES_C_M 0x38
#define SEG0_SET2_CSI_WGT_VAL_TONE0_C 0x42C0
#define SEG0_SET2_CSI_WGT_VAL_TONE0_C_M 0x1C0
#define SEG0_SET2_CSI_WGT_VAL_TONE1_C 0x42C0
#define SEG0_SET2_CSI_WGT_VAL_TONE1_C_M 0xE00
#define SEG0_SET2_CSI_WGT_VAL_TONE2_C 0x42C0
#define SEG0_SET2_CSI_WGT_VAL_TONE2_C_M 0x7000
#define SEG0_SET2_CSI_WGT_VAL_TONE3_C 0x42C0
#define SEG0_SET2_CSI_WGT_VAL_TONE3_C_M 0x38000
#define SEG1_SET1_CSI_WGT_VAL_TONE0_C 0x42C0
#define SEG1_SET1_CSI_WGT_VAL_TONE0_C_M 0x1C0000
#define SEG1_SET1_CSI_WGT_VAL_TONE1_C 0x42C0
#define SEG1_SET1_CSI_WGT_VAL_TONE1_C_M 0xE00000
#define SEG1_SET1_CSI_WGT_VAL_TONE2_C 0x42C0
#define SEG1_SET1_CSI_WGT_VAL_TONE2_C_M 0x7000000
#define SEG1_SET1_CSI_WGT_VAL_TONE3_C 0x42C0
#define SEG1_SET1_CSI_WGT_VAL_TONE3_C_M 0x38000000
#define SEG0_SET1_CSI_WGT_2X_LFT_TONES_C 0x42C0
#define SEG0_SET1_CSI_WGT_2X_LFT_TONES_C_M 0xC0000000
#define SEG1_SET2_CSI_WGT_VAL_TONE0_C 0x42C4
#define SEG1_SET2_CSI_WGT_VAL_TONE0_C_M 0x7
#define SEG1_SET2_CSI_WGT_VAL_TONE1_C 0x42C4
#define SEG1_SET2_CSI_WGT_VAL_TONE1_C_M 0x38
#define SEG1_SET2_CSI_WGT_VAL_TONE2_C 0x42C4
#define SEG1_SET2_CSI_WGT_VAL_TONE2_C_M 0x1C0
#define SEG1_SET2_CSI_WGT_VAL_TONE3_C 0x42C4
#define SEG1_SET2_CSI_WGT_VAL_TONE3_C_M 0xE00
#define SEG0_SET1_CSI_WGT_2X_RHT_TONES_C 0x42C4
#define SEG0_SET1_CSI_WGT_2X_RHT_TONES_C_M 0x3000
#define SEG0_SET1_CSI_WGT_LFT_TONES_C 0x42C4
#define SEG0_SET1_CSI_WGT_LFT_TONES_C_M 0xC000
#define SEG0_SET1_CSI_WGT_RHT_TONES_C 0x42C4
#define SEG0_SET1_CSI_WGT_RHT_TONES_C_M 0x30000
#define SEG0_SET2_CSI_WGT_1X_LFT_TONES_C 0x42C4
#define SEG0_SET2_CSI_WGT_1X_LFT_TONES_C_M 0xC0000
#define SEG0_SET2_CSI_WGT_1X_RHT_TONES_C 0x42C4
#define SEG0_SET2_CSI_WGT_1X_RHT_TONES_C_M 0x300000
#define SEG0_SET2_CSI_WGT_2X_LFT_TONES_C 0x42C4
#define SEG0_SET2_CSI_WGT_2X_LFT_TONES_C_M 0xC00000
#define SEG0_SET2_CSI_WGT_2X_RHT_TONES_C 0x42C4
#define SEG0_SET2_CSI_WGT_2X_RHT_TONES_C_M 0x3000000
#define SEG0_SET2_CSI_WGT_LFT_TONES_C 0x42C4
#define SEG0_SET2_CSI_WGT_LFT_TONES_C_M 0xC000000
#define SEG0_SET2_CSI_WGT_RHT_TONES_C 0x42C4
#define SEG0_SET2_CSI_WGT_RHT_TONES_C_M 0x30000000
#define SEG1_SET1_CSI_WGT_1X_LFT_TONES_C 0x42C4
#define SEG1_SET1_CSI_WGT_1X_LFT_TONES_C_M 0xC0000000
#define SEG1_SET1_CSI_WGT_1X_RHT_TONES_C 0x42C8
#define SEG1_SET1_CSI_WGT_1X_RHT_TONES_C_M 0x3
#define SEG1_SET1_CSI_WGT_2X_LFT_TONES_C 0x42C8
#define SEG1_SET1_CSI_WGT_2X_LFT_TONES_C_M 0xC
#define SEG1_SET1_CSI_WGT_2X_RHT_TONES_C 0x42C8
#define SEG1_SET1_CSI_WGT_2X_RHT_TONES_C_M 0x30
#define SEG1_SET1_CSI_WGT_LFT_TONES_C 0x42C8
#define SEG1_SET1_CSI_WGT_LFT_TONES_C_M 0xC0
#define SEG1_SET1_CSI_WGT_RHT_TONES_C 0x42C8
#define SEG1_SET1_CSI_WGT_RHT_TONES_C_M 0x300
#define SEG1_SET2_CSI_WGT_1X_LFT_TONES_C 0x42C8
#define SEG1_SET2_CSI_WGT_1X_LFT_TONES_C_M 0xC00
#define SEG1_SET2_CSI_WGT_1X_RHT_TONES_C 0x42C8
#define SEG1_SET2_CSI_WGT_1X_RHT_TONES_C_M 0x3000
#define SEG1_SET2_CSI_WGT_2X_LFT_TONES_C 0x42C8
#define SEG1_SET2_CSI_WGT_2X_LFT_TONES_C_M 0xC000
#define SEG1_SET2_CSI_WGT_2X_RHT_TONES_C 0x42C8
#define SEG1_SET2_CSI_WGT_2X_RHT_TONES_C_M 0x30000
#define SEG1_SET2_CSI_WGT_LFT_TONES_C 0x42C8
#define SEG1_SET2_CSI_WGT_LFT_TONES_C_M 0xC0000
#define SEG1_SET2_CSI_WGT_RHT_TONES_C 0x42C8
#define SEG1_SET2_CSI_WGT_RHT_TONES_C_M 0x300000
#define CSI_WGT_RSSI_BYPASS_EN_C 0x42C8
#define CSI_WGT_RSSI_BYPASS_EN_C_M 0x400000
#define SEG0_SET1_CSI_WGT_EN_C 0x42C8
#define SEG0_SET1_CSI_WGT_EN_C_M 0x800000
#define SEG0_SET2_CSI_WGT_EN_C 0x42C8
#define SEG0_SET2_CSI_WGT_EN_C_M 0x1000000
#define SEG1_SET1_CSI_WGT_EN_C 0x42C8
#define SEG1_SET1_CSI_WGT_EN_C_M 0x2000000
#define SEG1_SET2_CSI_WGT_EN_C 0x42C8
#define SEG1_SET2_CSI_WGT_EN_C_M 0x4000000
#define PROCR_MAX_NSTS_SMO_HW_C 0x42D4
#define PROCR_MAX_NSTS_SMO_HW_C_M 0x3
#define PROCR_NOISE_RE_EST_HE_TB_EN_C 0x42D4
#define PROCR_NOISE_RE_EST_HE_TB_EN_C_M 0x4
#define PROCR_NOISE_RE_EST_HE_EN_C 0x42D4
#define PROCR_NOISE_RE_EST_HE_EN_C_M 0x8
#define PROCR_NOISE_RE_EST_HT_EN_C 0x42D4
#define PROCR_NOISE_RE_EST_HT_EN_C_M 0x10
#define PROCR_NOISE_RE_EST_VHT_EN_C 0x42D4
#define PROCR_NOISE_RE_EST_VHT_EN_C_M 0x20
#define HE_EXTRA_TONE_CHSMO_EN_C 0x42D8
#define HE_EXTRA_TONE_CHSMO_EN_C_M 0x1
#define RPT_TONE_EVM_IDX_C 0x42DC
#define RPT_TONE_EVM_IDX_C_M 0x7FF
#define SFCTR_AWGN_BCC_1SS_MCS0_C 0x42DC
#define SFCTR_AWGN_BCC_1SS_MCS0_C_M 0x1F800
#define SFCTR_AWGN_BCC_1SS_MCS1_C 0x42DC
#define SFCTR_AWGN_BCC_1SS_MCS1_C_M 0x7E0000
#define SFCTR_AWGN_BCC_1SS_MCS2_C 0x42DC
#define SFCTR_AWGN_BCC_1SS_MCS2_C_M 0x1F800000
#define LLR_COEF_C 0x42DC
#define LLR_COEF_C_M 0xE0000000
#define SFCTR_AWGN_BCC_1SS_MCS3_C 0x42E0
#define SFCTR_AWGN_BCC_1SS_MCS3_C_M 0x3F
#define SFCTR_AWGN_BCC_1SS_MCS4_C 0x42E0
#define SFCTR_AWGN_BCC_1SS_MCS4_C_M 0xFC0
#define SFCTR_AWGN_BCC_1SS_MCS5_C 0x42E0
#define SFCTR_AWGN_BCC_1SS_MCS5_C_M 0x3F000
#define SFCTR_AWGN_BCC_1SS_MCS6_C 0x42E0
#define SFCTR_AWGN_BCC_1SS_MCS6_C_M 0xFC0000
#define SFCTR_AWGN_BCC_1SS_MCS7_C 0x42E0
#define SFCTR_AWGN_BCC_1SS_MCS7_C_M 0x3F000000
#define UPD_SYM_EVM_C 0x42E0
#define UPD_SYM_EVM_C_M 0xC0000000
#define SFCTR_AWGN_BCC_1SS_MCS8_C 0x42E4
#define SFCTR_AWGN_BCC_1SS_MCS8_C_M 0x3F
#define SFCTR_AWGN_BCC_1SS_MCS9_C 0x42E4
#define SFCTR_AWGN_BCC_1SS_MCS9_C_M 0xFC0
#define SFCTR_AWGN_BCC_2SS_MCS0_C 0x42E4
#define SFCTR_AWGN_BCC_2SS_MCS0_C_M 0x3F000
#define SFCTR_AWGN_BCC_2SS_MCS1_C 0x42E4
#define SFCTR_AWGN_BCC_2SS_MCS1_C_M 0xFC0000
#define SFCTR_AWGN_BCC_2SS_MCS2_C 0x42E4
#define SFCTR_AWGN_BCC_2SS_MCS2_C_M 0x3F000000
#define DCM_BINARY_CSI_WGT_C 0x42E4
#define DCM_BINARY_CSI_WGT_C_M 0x40000000
#define DCM_COMBINE_EN_C 0x42E4
#define DCM_COMBINE_EN_C_M 0x80000000
#define SFCTR_AWGN_BCC_2SS_MCS3_C 0x42E8
#define SFCTR_AWGN_BCC_2SS_MCS3_C_M 0x3F
#define SFCTR_AWGN_BCC_2SS_MCS4_C 0x42E8
#define SFCTR_AWGN_BCC_2SS_MCS4_C_M 0xFC0
#define SFCTR_AWGN_BCC_2SS_MCS5_C 0x42E8
#define SFCTR_AWGN_BCC_2SS_MCS5_C_M 0x3F000
#define SFCTR_AWGN_BCC_2SS_MCS6_C 0x42E8
#define SFCTR_AWGN_BCC_2SS_MCS6_C_M 0xFC0000
#define SFCTR_AWGN_BCC_2SS_MCS7_C 0x42E8
#define SFCTR_AWGN_BCC_2SS_MCS7_C_M 0x3F000000
#define EVM_RPT_OFST_EN_C 0x42E8
#define EVM_RPT_OFST_EN_C_M 0x40000000
#define LEGACY_2R_ANOTHER_SFCTR_EN_C 0x42E8
#define LEGACY_2R_ANOTHER_SFCTR_EN_C_M 0x80000000
#define SFCTR_AWGN_BCC_2SS_MCS8_C 0x42EC
#define SFCTR_AWGN_BCC_2SS_MCS8_C_M 0x3F
#define SFCTR_AWGN_BCC_2SS_MCS9_C 0x42EC
#define SFCTR_AWGN_BCC_2SS_MCS9_C_M 0xFC0
#define SFCTR_AWGN_BCC_3SS_MCS0_C 0x42EC
#define SFCTR_AWGN_BCC_3SS_MCS0_C_M 0x3F000
#define SFCTR_AWGN_BCC_3SS_MCS1_C 0x42EC
#define SFCTR_AWGN_BCC_3SS_MCS1_C_M 0xFC0000
#define SFCTR_AWGN_BCC_3SS_MCS2_C 0x42EC
#define SFCTR_AWGN_BCC_3SS_MCS2_C_M 0x3F000000
#define DIFF_NLM_FOR_CHANNEL_EN_C 0x42EC
#define DIFF_NLM_FOR_CHANNEL_EN_C_M 0x40000000
#define SFCTR_AWGN_BCC_3SS_MCS3_C 0x42F0
#define SFCTR_AWGN_BCC_3SS_MCS3_C_M 0x3F
#define SFCTR_AWGN_BCC_3SS_MCS4_C 0x42F0
#define SFCTR_AWGN_BCC_3SS_MCS4_C_M 0xFC0
#define SFCTR_AWGN_BCC_3SS_MCS5_C 0x42F0
#define SFCTR_AWGN_BCC_3SS_MCS5_C_M 0x3F000
#define SFCTR_AWGN_BCC_3SS_MCS6_C 0x42F0
#define SFCTR_AWGN_BCC_3SS_MCS6_C_M 0xFC0000
#define SFCTR_AWGN_BCC_3SS_MCS7_C 0x42F0
#define SFCTR_AWGN_BCC_3SS_MCS7_C_M 0x3F000000
#define SFCTR_AWGN_BCC_3SS_MCS8_C 0x42F4
#define SFCTR_AWGN_BCC_3SS_MCS8_C_M 0x3F
#define SFCTR_AWGN_BCC_3SS_MCS9_C 0x42F4
#define SFCTR_AWGN_BCC_3SS_MCS9_C_M 0xFC0
#define SFCTR_AWGN_BCC_4SS_MCS0_C 0x42F4
#define SFCTR_AWGN_BCC_4SS_MCS0_C_M 0x3F000
#define SFCTR_AWGN_BCC_4SS_MCS1_C 0x42F4
#define SFCTR_AWGN_BCC_4SS_MCS1_C_M 0xFC0000
#define SFCTR_AWGN_BCC_4SS_MCS2_C 0x42F4
#define SFCTR_AWGN_BCC_4SS_MCS2_C_M 0x3F000000
#define SFCTR_AWGN_BCC_4SS_MCS3_C 0x42F8
#define SFCTR_AWGN_BCC_4SS_MCS3_C_M 0x3F
#define SFCTR_AWGN_BCC_4SS_MCS4_C 0x42F8
#define SFCTR_AWGN_BCC_4SS_MCS4_C_M 0xFC0
#define SFCTR_AWGN_BCC_4SS_MCS5_C 0x42F8
#define SFCTR_AWGN_BCC_4SS_MCS5_C_M 0x3F000
#define SFCTR_AWGN_BCC_4SS_MCS6_C 0x42F8
#define SFCTR_AWGN_BCC_4SS_MCS6_C_M 0xFC0000
#define SFCTR_AWGN_BCC_4SS_MCS7_C 0x42F8
#define SFCTR_AWGN_BCC_4SS_MCS7_C_M 0x3F000000
#define SFCTR_AWGN_BCC_4SS_MCS8_C 0x42FC
#define SFCTR_AWGN_BCC_4SS_MCS8_C_M 0x3F
#define SFCTR_AWGN_BCC_4SS_MCS9_C 0x42FC
#define SFCTR_AWGN_BCC_4SS_MCS9_C_M 0xFC0
#define SFCTR_AWGN_LDPC_1SS_MCS0_C 0x42FC
#define SFCTR_AWGN_LDPC_1SS_MCS0_C_M 0x3F000
#define SFCTR_AWGN_LDPC_1SS_MCS1_C 0x42FC
#define SFCTR_AWGN_LDPC_1SS_MCS1_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_1SS_MCS10_C 0x42FC
#define SFCTR_AWGN_LDPC_1SS_MCS10_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_1SS_MCS11_C 0x4300
#define SFCTR_AWGN_LDPC_1SS_MCS11_C_M 0x3F
#define SFCTR_AWGN_LDPC_1SS_MCS2_C 0x4300
#define SFCTR_AWGN_LDPC_1SS_MCS2_C_M 0xFC0
#define SFCTR_AWGN_LDPC_1SS_MCS3_C 0x4300
#define SFCTR_AWGN_LDPC_1SS_MCS3_C_M 0x3F000
#define SFCTR_AWGN_LDPC_1SS_MCS4_C 0x4300
#define SFCTR_AWGN_LDPC_1SS_MCS4_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_1SS_MCS5_C 0x4300
#define SFCTR_AWGN_LDPC_1SS_MCS5_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_1SS_MCS6_C 0x4304
#define SFCTR_AWGN_LDPC_1SS_MCS6_C_M 0x3F
#define SFCTR_AWGN_LDPC_1SS_MCS7_C 0x4304
#define SFCTR_AWGN_LDPC_1SS_MCS7_C_M 0xFC0
#define SFCTR_AWGN_LDPC_1SS_MCS8_C 0x4304
#define SFCTR_AWGN_LDPC_1SS_MCS8_C_M 0x3F000
#define SFCTR_AWGN_LDPC_1SS_MCS9_C 0x4304
#define SFCTR_AWGN_LDPC_1SS_MCS9_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_2SS_MCS0_C 0x4304
#define SFCTR_AWGN_LDPC_2SS_MCS0_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_2SS_MCS1_C 0x4308
#define SFCTR_AWGN_LDPC_2SS_MCS1_C_M 0x3F
#define SFCTR_AWGN_LDPC_2SS_MCS10_C 0x4308
#define SFCTR_AWGN_LDPC_2SS_MCS10_C_M 0xFC0
#define SFCTR_AWGN_LDPC_2SS_MCS11_C 0x4308
#define SFCTR_AWGN_LDPC_2SS_MCS11_C_M 0x3F000
#define SFCTR_AWGN_LDPC_2SS_MCS2_C 0x4308
#define SFCTR_AWGN_LDPC_2SS_MCS2_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_2SS_MCS3_C 0x4308
#define SFCTR_AWGN_LDPC_2SS_MCS3_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_2SS_MCS4_C 0x430C
#define SFCTR_AWGN_LDPC_2SS_MCS4_C_M 0x3F
#define SFCTR_AWGN_LDPC_2SS_MCS5_C 0x430C
#define SFCTR_AWGN_LDPC_2SS_MCS5_C_M 0xFC0
#define SFCTR_AWGN_LDPC_2SS_MCS6_C 0x430C
#define SFCTR_AWGN_LDPC_2SS_MCS6_C_M 0x3F000
#define SFCTR_AWGN_LDPC_2SS_MCS7_C 0x430C
#define SFCTR_AWGN_LDPC_2SS_MCS7_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_2SS_MCS8_C 0x430C
#define SFCTR_AWGN_LDPC_2SS_MCS8_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_2SS_MCS9_C 0x4310
#define SFCTR_AWGN_LDPC_2SS_MCS9_C_M 0x3F
#define SFCTR_AWGN_LDPC_3SS_MCS0_C 0x4310
#define SFCTR_AWGN_LDPC_3SS_MCS0_C_M 0xFC0
#define SFCTR_AWGN_LDPC_3SS_MCS1_C 0x4310
#define SFCTR_AWGN_LDPC_3SS_MCS1_C_M 0x3F000
#define SFCTR_AWGN_LDPC_3SS_MCS10_C 0x4310
#define SFCTR_AWGN_LDPC_3SS_MCS10_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_3SS_MCS11_C 0x4310
#define SFCTR_AWGN_LDPC_3SS_MCS11_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_3SS_MCS2_C 0x4314
#define SFCTR_AWGN_LDPC_3SS_MCS2_C_M 0x3F
#define SFCTR_AWGN_LDPC_3SS_MCS3_C 0x4314
#define SFCTR_AWGN_LDPC_3SS_MCS3_C_M 0xFC0
#define SFCTR_AWGN_LDPC_3SS_MCS4_C 0x4314
#define SFCTR_AWGN_LDPC_3SS_MCS4_C_M 0x3F000
#define SFCTR_AWGN_LDPC_3SS_MCS5_C 0x4314
#define SFCTR_AWGN_LDPC_3SS_MCS5_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_3SS_MCS6_C 0x4314
#define SFCTR_AWGN_LDPC_3SS_MCS6_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_3SS_MCS7_C 0x4318
#define SFCTR_AWGN_LDPC_3SS_MCS7_C_M 0x3F
#define SFCTR_AWGN_LDPC_3SS_MCS8_C 0x4318
#define SFCTR_AWGN_LDPC_3SS_MCS8_C_M 0xFC0
#define SFCTR_AWGN_LDPC_3SS_MCS9_C 0x4318
#define SFCTR_AWGN_LDPC_3SS_MCS9_C_M 0x3F000
#define SFCTR_AWGN_LDPC_4SS_MCS0_C 0x4318
#define SFCTR_AWGN_LDPC_4SS_MCS0_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_4SS_MCS1_C 0x4318
#define SFCTR_AWGN_LDPC_4SS_MCS1_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_4SS_MCS10_C 0x431C
#define SFCTR_AWGN_LDPC_4SS_MCS10_C_M 0x3F
#define SFCTR_AWGN_LDPC_4SS_MCS11_C 0x431C
#define SFCTR_AWGN_LDPC_4SS_MCS11_C_M 0xFC0
#define SFCTR_AWGN_LDPC_4SS_MCS2_C 0x431C
#define SFCTR_AWGN_LDPC_4SS_MCS2_C_M 0x3F000
#define SFCTR_AWGN_LDPC_4SS_MCS3_C 0x431C
#define SFCTR_AWGN_LDPC_4SS_MCS3_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_4SS_MCS4_C 0x431C
#define SFCTR_AWGN_LDPC_4SS_MCS4_C_M 0x3F000000
#define SFCTR_AWGN_LDPC_4SS_MCS5_C 0x4320
#define SFCTR_AWGN_LDPC_4SS_MCS5_C_M 0x3F
#define SFCTR_AWGN_LDPC_4SS_MCS6_C 0x4320
#define SFCTR_AWGN_LDPC_4SS_MCS6_C_M 0xFC0
#define SFCTR_AWGN_LDPC_4SS_MCS7_C 0x4320
#define SFCTR_AWGN_LDPC_4SS_MCS7_C_M 0x3F000
#define SFCTR_AWGN_LDPC_4SS_MCS8_C 0x4320
#define SFCTR_AWGN_LDPC_4SS_MCS8_C_M 0xFC0000
#define SFCTR_AWGN_LDPC_4SS_MCS9_C 0x4320
#define SFCTR_AWGN_LDPC_4SS_MCS9_C_M 0x3F000000
#define SFCTR_AWGN_LAGCY_12M_C 0x4324
#define SFCTR_AWGN_LAGCY_12M_C_M 0x3F
#define SFCTR_AWGN_LAGCY_18M_C 0x4324
#define SFCTR_AWGN_LAGCY_18M_C_M 0xFC0
#define SFCTR_AWGN_LAGCY_24M_C 0x4324
#define SFCTR_AWGN_LAGCY_24M_C_M 0x3F000
#define SFCTR_AWGN_LAGCY_36M_C 0x4324
#define SFCTR_AWGN_LAGCY_36M_C_M 0xFC0000
#define SFCTR_AWGN_LAGCY_48M_C 0x4324
#define SFCTR_AWGN_LAGCY_48M_C_M 0x3F000000
#define SFCTR_AWGN_LAGCY_54M_C 0x4328
#define SFCTR_AWGN_LAGCY_54M_C_M 0x3F
#define SFCTR_AWGN_LAGCY_6M_C 0x4328
#define SFCTR_AWGN_LAGCY_6M_C_M 0xFC0
#define SFCTR_AWGN_LAGCY_9M_C 0x4328
#define SFCTR_AWGN_LAGCY_9M_C_M 0x3F000
#define SFCTR_CH_BCC_1SS_MCS0_C 0x4328
#define SFCTR_CH_BCC_1SS_MCS0_C_M 0xFC0000
#define SFCTR_CH_BCC_1SS_MCS1_C 0x4328
#define SFCTR_CH_BCC_1SS_MCS1_C_M 0x3F000000
#define SFCTR_CH_BCC_1SS_MCS2_C 0x432C
#define SFCTR_CH_BCC_1SS_MCS2_C_M 0x3F
#define SFCTR_CH_BCC_1SS_MCS3_C 0x432C
#define SFCTR_CH_BCC_1SS_MCS3_C_M 0xFC0
#define SFCTR_CH_BCC_1SS_MCS4_C 0x432C
#define SFCTR_CH_BCC_1SS_MCS4_C_M 0x3F000
#define SFCTR_CH_BCC_1SS_MCS5_C 0x432C
#define SFCTR_CH_BCC_1SS_MCS5_C_M 0xFC0000
#define SFCTR_CH_BCC_1SS_MCS6_C 0x432C
#define SFCTR_CH_BCC_1SS_MCS6_C_M 0x3F000000
#define SFCTR_CH_BCC_1SS_MCS7_C 0x4330
#define SFCTR_CH_BCC_1SS_MCS7_C_M 0x3F
#define SFCTR_CH_BCC_1SS_MCS8_C 0x4330
#define SFCTR_CH_BCC_1SS_MCS8_C_M 0xFC0
#define SFCTR_CH_BCC_1SS_MCS9_C 0x4330
#define SFCTR_CH_BCC_1SS_MCS9_C_M 0x3F000
#define SFCTR_CH_BCC_2SS_MCS0_C 0x4330
#define SFCTR_CH_BCC_2SS_MCS0_C_M 0xFC0000
#define SFCTR_CH_BCC_2SS_MCS1_C 0x4330
#define SFCTR_CH_BCC_2SS_MCS1_C_M 0x3F000000
#define SFCTR_CH_BCC_2SS_MCS2_C 0x4334
#define SFCTR_CH_BCC_2SS_MCS2_C_M 0x3F
#define SFCTR_CH_BCC_2SS_MCS3_C 0x4334
#define SFCTR_CH_BCC_2SS_MCS3_C_M 0xFC0
#define SFCTR_CH_BCC_2SS_MCS4_C 0x4334
#define SFCTR_CH_BCC_2SS_MCS4_C_M 0x3F000
#define SFCTR_CH_BCC_2SS_MCS5_C 0x4334
#define SFCTR_CH_BCC_2SS_MCS5_C_M 0xFC0000
#define SFCTR_CH_BCC_2SS_MCS6_C 0x4334
#define SFCTR_CH_BCC_2SS_MCS6_C_M 0x3F000000
#define SFCTR_CH_BCC_2SS_MCS7_C 0x4338
#define SFCTR_CH_BCC_2SS_MCS7_C_M 0x3F
#define SFCTR_CH_BCC_2SS_MCS8_C 0x4338
#define SFCTR_CH_BCC_2SS_MCS8_C_M 0xFC0
#define SFCTR_CH_BCC_2SS_MCS9_C 0x4338
#define SFCTR_CH_BCC_2SS_MCS9_C_M 0x3F000
#define SFCTR_CH_BCC_3SS_MCS0_C 0x4338
#define SFCTR_CH_BCC_3SS_MCS0_C_M 0xFC0000
#define SFCTR_CH_BCC_3SS_MCS1_C 0x4338
#define SFCTR_CH_BCC_3SS_MCS1_C_M 0x3F000000
#define SFCTR_CH_BCC_3SS_MCS2_C 0x433C
#define SFCTR_CH_BCC_3SS_MCS2_C_M 0x3F
#define SFCTR_CH_BCC_3SS_MCS3_C 0x433C
#define SFCTR_CH_BCC_3SS_MCS3_C_M 0xFC0
#define SFCTR_CH_BCC_3SS_MCS4_C 0x433C
#define SFCTR_CH_BCC_3SS_MCS4_C_M 0x3F000
#define SFCTR_CH_BCC_3SS_MCS5_C 0x433C
#define SFCTR_CH_BCC_3SS_MCS5_C_M 0xFC0000
#define SFCTR_CH_BCC_3SS_MCS6_C 0x433C
#define SFCTR_CH_BCC_3SS_MCS6_C_M 0x3F000000
#define SFCTR_CH_BCC_3SS_MCS7_C 0x4340
#define SFCTR_CH_BCC_3SS_MCS7_C_M 0x3F
#define SFCTR_CH_BCC_3SS_MCS8_C 0x4340
#define SFCTR_CH_BCC_3SS_MCS8_C_M 0xFC0
#define SFCTR_CH_BCC_3SS_MCS9_C 0x4340
#define SFCTR_CH_BCC_3SS_MCS9_C_M 0x3F000
#define SFCTR_CH_BCC_4SS_MCS0_C 0x4340
#define SFCTR_CH_BCC_4SS_MCS0_C_M 0xFC0000
#define SFCTR_CH_BCC_4SS_MCS1_C 0x4340
#define SFCTR_CH_BCC_4SS_MCS1_C_M 0x3F000000
#define SFCTR_CH_BCC_4SS_MCS2_C 0x4344
#define SFCTR_CH_BCC_4SS_MCS2_C_M 0x3F
#define SFCTR_CH_BCC_4SS_MCS3_C 0x4344
#define SFCTR_CH_BCC_4SS_MCS3_C_M 0xFC0
#define SFCTR_CH_BCC_4SS_MCS4_C 0x4344
#define SFCTR_CH_BCC_4SS_MCS4_C_M 0x3F000
#define SFCTR_CH_BCC_4SS_MCS5_C 0x4344
#define SFCTR_CH_BCC_4SS_MCS5_C_M 0xFC0000
#define SFCTR_CH_BCC_4SS_MCS6_C 0x4344
#define SFCTR_CH_BCC_4SS_MCS6_C_M 0x3F000000
#define SFCTR_CH_BCC_4SS_MCS7_C 0x4348
#define SFCTR_CH_BCC_4SS_MCS7_C_M 0x3F
#define SFCTR_CH_BCC_4SS_MCS8_C 0x4348
#define SFCTR_CH_BCC_4SS_MCS8_C_M 0xFC0
#define SFCTR_CH_BCC_4SS_MCS9_C 0x4348
#define SFCTR_CH_BCC_4SS_MCS9_C_M 0x3F000
#define SFCTR_CH_LDPC_1SS_MCS0_C 0x4348
#define SFCTR_CH_LDPC_1SS_MCS0_C_M 0xFC0000
#define SFCTR_CH_LDPC_1SS_MCS1_C 0x4348
#define SFCTR_CH_LDPC_1SS_MCS1_C_M 0x3F000000
#define SFCTR_CH_LDPC_1SS_MCS10_C 0x434C
#define SFCTR_CH_LDPC_1SS_MCS10_C_M 0x3F
#define SFCTR_CH_LDPC_1SS_MCS11_C 0x434C
#define SFCTR_CH_LDPC_1SS_MCS11_C_M 0xFC0
#define SFCTR_CH_LDPC_1SS_MCS2_C 0x434C
#define SFCTR_CH_LDPC_1SS_MCS2_C_M 0x3F000
#define SFCTR_CH_LDPC_1SS_MCS3_C 0x434C
#define SFCTR_CH_LDPC_1SS_MCS3_C_M 0xFC0000
#define SFCTR_CH_LDPC_1SS_MCS4_C 0x434C
#define SFCTR_CH_LDPC_1SS_MCS4_C_M 0x3F000000
#define SFCTR_CH_LDPC_1SS_MCS5_C 0x4350
#define SFCTR_CH_LDPC_1SS_MCS5_C_M 0x3F
#define SFCTR_CH_LDPC_1SS_MCS6_C 0x4350
#define SFCTR_CH_LDPC_1SS_MCS6_C_M 0xFC0
#define SFCTR_CH_LDPC_1SS_MCS7_C 0x4350
#define SFCTR_CH_LDPC_1SS_MCS7_C_M 0x3F000
#define SFCTR_CH_LDPC_1SS_MCS8_C 0x4350
#define SFCTR_CH_LDPC_1SS_MCS8_C_M 0xFC0000
#define SFCTR_CH_LDPC_1SS_MCS9_C 0x4350
#define SFCTR_CH_LDPC_1SS_MCS9_C_M 0x3F000000
#define SFCTR_CH_LDPC_2SS_MCS0_C 0x4354
#define SFCTR_CH_LDPC_2SS_MCS0_C_M 0x3F
#define SFCTR_CH_LDPC_2SS_MCS1_C 0x4354
#define SFCTR_CH_LDPC_2SS_MCS1_C_M 0xFC0
#define SFCTR_CH_LDPC_2SS_MCS10_C 0x4354
#define SFCTR_CH_LDPC_2SS_MCS10_C_M 0x3F000
#define SFCTR_CH_LDPC_2SS_MCS11_C 0x4354
#define SFCTR_CH_LDPC_2SS_MCS11_C_M 0xFC0000
#define SFCTR_CH_LDPC_2SS_MCS2_C 0x4354
#define SFCTR_CH_LDPC_2SS_MCS2_C_M 0x3F000000
#define SFCTR_CH_LDPC_2SS_MCS3_C 0x4358
#define SFCTR_CH_LDPC_2SS_MCS3_C_M 0x3F
#define SFCTR_CH_LDPC_2SS_MCS4_C 0x4358
#define SFCTR_CH_LDPC_2SS_MCS4_C_M 0xFC0
#define SFCTR_CH_LDPC_2SS_MCS5_C 0x4358
#define SFCTR_CH_LDPC_2SS_MCS5_C_M 0x3F000
#define SFCTR_CH_LDPC_2SS_MCS6_C 0x4358
#define SFCTR_CH_LDPC_2SS_MCS6_C_M 0xFC0000
#define SFCTR_CH_LDPC_2SS_MCS7_C 0x4358
#define SFCTR_CH_LDPC_2SS_MCS7_C_M 0x3F000000
#define SFCTR_CH_LDPC_2SS_MCS8_C 0x435C
#define SFCTR_CH_LDPC_2SS_MCS8_C_M 0x3F
#define SFCTR_CH_LDPC_2SS_MCS9_C 0x435C
#define SFCTR_CH_LDPC_2SS_MCS9_C_M 0xFC0
#define SFCTR_CH_LDPC_3SS_MCS0_C 0x435C
#define SFCTR_CH_LDPC_3SS_MCS0_C_M 0x3F000
#define SFCTR_CH_LDPC_3SS_MCS1_C 0x435C
#define SFCTR_CH_LDPC_3SS_MCS1_C_M 0xFC0000
#define SFCTR_CH_LDPC_3SS_MCS10_C 0x435C
#define SFCTR_CH_LDPC_3SS_MCS10_C_M 0x3F000000
#define SFCTR_CH_LDPC_3SS_MCS11_C 0x4360
#define SFCTR_CH_LDPC_3SS_MCS11_C_M 0x3F
#define SFCTR_CH_LDPC_3SS_MCS2_C 0x4360
#define SFCTR_CH_LDPC_3SS_MCS2_C_M 0xFC0
#define SFCTR_CH_LDPC_3SS_MCS3_C 0x4360
#define SFCTR_CH_LDPC_3SS_MCS3_C_M 0x3F000
#define SFCTR_CH_LDPC_3SS_MCS4_C 0x4360
#define SFCTR_CH_LDPC_3SS_MCS4_C_M 0xFC0000
#define SFCTR_CH_LDPC_3SS_MCS5_C 0x4360
#define SFCTR_CH_LDPC_3SS_MCS5_C_M 0x3F000000
#define SFCTR_CH_LDPC_3SS_MCS6_C 0x4364
#define SFCTR_CH_LDPC_3SS_MCS6_C_M 0x3F
#define SFCTR_CH_LDPC_3SS_MCS7_C 0x4364
#define SFCTR_CH_LDPC_3SS_MCS7_C_M 0xFC0
#define SFCTR_CH_LDPC_3SS_MCS8_C 0x4364
#define SFCTR_CH_LDPC_3SS_MCS8_C_M 0x3F000
#define SFCTR_CH_LDPC_3SS_MCS9_C 0x4364
#define SFCTR_CH_LDPC_3SS_MCS9_C_M 0xFC0000
#define SFCTR_CH_LDPC_4SS_MCS0_C 0x4364
#define SFCTR_CH_LDPC_4SS_MCS0_C_M 0x3F000000
#define SFCTR_CH_LDPC_4SS_MCS1_C 0x4368
#define SFCTR_CH_LDPC_4SS_MCS1_C_M 0x3F
#define SFCTR_CH_LDPC_4SS_MCS10_C 0x4368
#define SFCTR_CH_LDPC_4SS_MCS10_C_M 0xFC0
#define SFCTR_CH_LDPC_4SS_MCS11_C 0x4368
#define SFCTR_CH_LDPC_4SS_MCS11_C_M 0x3F000
#define SFCTR_CH_LDPC_4SS_MCS2_C 0x4368
#define SFCTR_CH_LDPC_4SS_MCS2_C_M 0xFC0000
#define SFCTR_CH_LDPC_4SS_MCS3_C 0x4368
#define SFCTR_CH_LDPC_4SS_MCS3_C_M 0x3F000000
#define SFCTR_CH_LDPC_4SS_MCS4_C 0x436C
#define SFCTR_CH_LDPC_4SS_MCS4_C_M 0x3F
#define SFCTR_CH_LDPC_4SS_MCS5_C 0x436C
#define SFCTR_CH_LDPC_4SS_MCS5_C_M 0xFC0
#define SFCTR_CH_LDPC_4SS_MCS6_C 0x436C
#define SFCTR_CH_LDPC_4SS_MCS6_C_M 0x3F000
#define SFCTR_CH_LDPC_4SS_MCS7_C 0x436C
#define SFCTR_CH_LDPC_4SS_MCS7_C_M 0xFC0000
#define SFCTR_CH_LDPC_4SS_MCS8_C 0x436C
#define SFCTR_CH_LDPC_4SS_MCS8_C_M 0x3F000000
#define SFCTR_CH_LDPC_4SS_MCS9_C 0x4370
#define SFCTR_CH_LDPC_4SS_MCS9_C_M 0x3F
#define SFCTR_CH_LAGCY_12M_C 0x4370
#define SFCTR_CH_LAGCY_12M_C_M 0xFC0
#define SFCTR_CH_LAGCY_18M_C 0x4370
#define SFCTR_CH_LAGCY_18M_C_M 0x3F000
#define SFCTR_CH_LAGCY_24M_C 0x4370
#define SFCTR_CH_LAGCY_24M_C_M 0xFC0000
#define SFCTR_CH_LAGCY_36M_C 0x4370
#define SFCTR_CH_LAGCY_36M_C_M 0x3F000000
#define SFCTR_CH_LAGCY_48M_C 0x4374
#define SFCTR_CH_LAGCY_48M_C_M 0x3F
#define SFCTR_CH_LAGCY_54M_C 0x4374
#define SFCTR_CH_LAGCY_54M_C_M 0xFC0
#define SFCTR_CH_LAGCY_6M_C 0x4374
#define SFCTR_CH_LAGCY_6M_C_M 0x3F000
#define SFCTR_CH_LAGCY_9M_C 0x4374
#define SFCTR_CH_LAGCY_9M_C_M 0xFC0000
#define FCTR_AWGN_LAGCY_2R_C 0x4374
#define FCTR_AWGN_LAGCY_2R_C_M 0xF000000
#define FCTR_CH_LAGCY_2R_C 0x4374
#define FCTR_CH_LAGCY_2R_C_M 0xF0000000
#define FCTR_BCC_STBC_CH_16QAM_C 0x4378
#define FCTR_BCC_STBC_CH_16QAM_C_M 0xF
#define FCTR_BCC_STBC_CH_256QAM_C 0x4378
#define FCTR_BCC_STBC_CH_256QAM_C_M 0xF0
#define FCTR_BCC_STBC_CH_64QAM_C 0x4378
#define FCTR_BCC_STBC_CH_64QAM_C_M 0xF00
#define FCTR_BCC_STBC_CH_BPSK_C 0x4378
#define FCTR_BCC_STBC_CH_BPSK_C_M 0xF000
#define FCTR_BCC_STBC_CH_QPSK_C 0x4378
#define FCTR_BCC_STBC_CH_QPSK_C_M 0xF0000
#define FCTR_BCC_STBC_I_16QAM_C 0x4378
#define FCTR_BCC_STBC_I_16QAM_C_M 0xF00000
#define FCTR_BCC_STBC_I_256QAM_C 0x4378
#define FCTR_BCC_STBC_I_256QAM_C_M 0xF000000
#define FCTR_BCC_STBC_I_64QAM_C 0x4378
#define FCTR_BCC_STBC_I_64QAM_C_M 0xF0000000
#define FCTR_BCC_STBC_I_BPSK_C 0x437C
#define FCTR_BCC_STBC_I_BPSK_C_M 0xF
#define FCTR_BCC_STBC_I_QPSK_C 0x437C
#define FCTR_BCC_STBC_I_QPSK_C_M 0xF0
#define FCTR_HE_BCC_1SS_CH_16QAM_C 0x437C
#define FCTR_HE_BCC_1SS_CH_16QAM_C_M 0xF00
#define FCTR_HE_BCC_1SS_CH_256QAM_C 0x437C
#define FCTR_HE_BCC_1SS_CH_256QAM_C_M 0xF000
#define FCTR_HE_BCC_1SS_CH_64QAM_C 0x437C
#define FCTR_HE_BCC_1SS_CH_64QAM_C_M 0xF0000
#define FCTR_HE_BCC_1SS_CH_BPSK_C 0x437C
#define FCTR_HE_BCC_1SS_CH_BPSK_C_M 0xF00000
#define FCTR_HE_BCC_1SS_CH_QPSK_C 0x437C
#define FCTR_HE_BCC_1SS_CH_QPSK_C_M 0xF000000
#define FCTR_HE_BCC_1SS_I_16QAM_C 0x437C
#define FCTR_HE_BCC_1SS_I_16QAM_C_M 0xF0000000
#define FCTR_HE_BCC_1SS_I_256QAM_C 0x4380
#define FCTR_HE_BCC_1SS_I_256QAM_C_M 0xF
#define FCTR_HE_BCC_1SS_I_64QAM_C 0x4380
#define FCTR_HE_BCC_1SS_I_64QAM_C_M 0xF0
#define FCTR_HE_BCC_1SS_I_BPSK_C 0x4380
#define FCTR_HE_BCC_1SS_I_BPSK_C_M 0xF00
#define FCTR_HE_BCC_1SS_I_QPSK_C 0x4380
#define FCTR_HE_BCC_1SS_I_QPSK_C_M 0xF000
#define FCTR_HE_BCC_2SS_CH_16QAM_C 0x4380
#define FCTR_HE_BCC_2SS_CH_16QAM_C_M 0xF0000
#define FCTR_HE_BCC_2SS_CH_256QAM_C 0x4380
#define FCTR_HE_BCC_2SS_CH_256QAM_C_M 0xF00000
#define FCTR_HE_BCC_2SS_CH_64QAM_C 0x4380
#define FCTR_HE_BCC_2SS_CH_64QAM_C_M 0xF000000
#define FCTR_HE_BCC_2SS_CH_BPSK_C 0x4380
#define FCTR_HE_BCC_2SS_CH_BPSK_C_M 0xF0000000
#define FCTR_HE_BCC_2SS_CH_QPSK_C 0x4384
#define FCTR_HE_BCC_2SS_CH_QPSK_C_M 0xF
#define FCTR_HE_BCC_2SS_I_16QAM_C 0x4384
#define FCTR_HE_BCC_2SS_I_16QAM_C_M 0xF0
#define FCTR_HE_BCC_2SS_I_256QAM_C 0x4384
#define FCTR_HE_BCC_2SS_I_256QAM_C_M 0xF00
#define FCTR_HE_BCC_2SS_I_64QAM_C 0x4384
#define FCTR_HE_BCC_2SS_I_64QAM_C_M 0xF000
#define FCTR_HE_BCC_2SS_I_BPSK_C 0x4384
#define FCTR_HE_BCC_2SS_I_BPSK_C_M 0xF0000
#define FCTR_HE_BCC_2SS_I_QPSK_C 0x4384
#define FCTR_HE_BCC_2SS_I_QPSK_C_M 0xF00000
#define FCTR_HE_BCC_STBC_CH_16QAM_C 0x4384
#define FCTR_HE_BCC_STBC_CH_16QAM_C_M 0xF000000
#define FCTR_HE_BCC_STBC_CH_256QAM_C 0x4384
#define FCTR_HE_BCC_STBC_CH_256QAM_C_M 0xF0000000
#define FCTR_HE_BCC_STBC_CH_64QAM_C 0x4388
#define FCTR_HE_BCC_STBC_CH_64QAM_C_M 0xF
#define FCTR_HE_BCC_STBC_CH_BPSK_C 0x4388
#define FCTR_HE_BCC_STBC_CH_BPSK_C_M 0xF0
#define FCTR_HE_BCC_STBC_CH_QPSK_C 0x4388
#define FCTR_HE_BCC_STBC_CH_QPSK_C_M 0xF00
#define FCTR_HE_BCC_STBC_I_16QAM_C 0x4388
#define FCTR_HE_BCC_STBC_I_16QAM_C_M 0xF000
#define FCTR_HE_BCC_STBC_I_256QAM_C 0x4388
#define FCTR_HE_BCC_STBC_I_256QAM_C_M 0xF0000
#define FCTR_HE_BCC_STBC_I_64QAM_C 0x4388
#define FCTR_HE_BCC_STBC_I_64QAM_C_M 0xF00000
#define FCTR_HE_BCC_STBC_I_BPSK_C 0x4388
#define FCTR_HE_BCC_STBC_I_BPSK_C_M 0xF000000
#define FCTR_HE_BCC_STBC_I_QPSK_C 0x4388
#define FCTR_HE_BCC_STBC_I_QPSK_C_M 0xF0000000
#define FCTR_HE_LDPC_1SS_CH_C 0x438C
#define FCTR_HE_LDPC_1SS_CH_C_M 0xF
#define FCTR_HE_LDPC_1SS_I_C 0x438C
#define FCTR_HE_LDPC_1SS_I_C_M 0xF0
#define FCTR_HE_LDPC_2SS_CH_C 0x438C
#define FCTR_HE_LDPC_2SS_CH_C_M 0xF00
#define FCTR_HE_LDPC_2SS_I_C 0x438C
#define FCTR_HE_LDPC_2SS_I_C_M 0xF000
#define FCTR_HE_LDPC_STBC_CH_C 0x438C
#define FCTR_HE_LDPC_STBC_CH_C_M 0xF0000
#define FCTR_HE_LDPC_STBC_I_C 0x438C
#define FCTR_HE_LDPC_STBC_I_C_M 0xF00000
#define FCTR_HE_MU_BCC_CH_C 0x438C
#define FCTR_HE_MU_BCC_CH_C_M 0xF000000
#define FCTR_HE_MU_BCC_I_C 0x438C
#define FCTR_HE_MU_BCC_I_C_M 0xF0000000
#define FCTR_HE_MU_LDPC_CH_C 0x4390
#define FCTR_HE_MU_LDPC_CH_C_M 0xF
#define FCTR_HE_MU_LDPC_I_C 0x4390
#define FCTR_HE_MU_LDPC_I_C_M 0xF0
#define FCTR_HE_MU_NOMUIC_BCC_CH_C 0x4390
#define FCTR_HE_MU_NOMUIC_BCC_CH_C_M 0xF00
#define FCTR_HE_MU_NOMUIC_BCC_I_C 0x4390
#define FCTR_HE_MU_NOMUIC_BCC_I_C_M 0xF000
#define FCTR_HE_MU_NOMUIC_LDPC_CH_C 0x4390
#define FCTR_HE_MU_NOMUIC_LDPC_CH_C_M 0xF0000
#define FCTR_HE_MU_NOMUIC_LDPC_I_C 0x4390
#define FCTR_HE_MU_NOMUIC_LDPC_I_C_M 0xF00000
#define FCTR_LDPC_STBC_CH_C 0x4390
#define FCTR_LDPC_STBC_CH_C_M 0xF000000
#define FCTR_LDPC_STBC_I_C 0x4390
#define FCTR_LDPC_STBC_I_C_M 0xF0000000
#define LLR_COEF_H_DELAY_SPREAD_C 0x4394
#define LLR_COEF_H_DELAY_SPREAD_C_M 0x7
#define LLR_COEF_L_DELAY_SPREAD_C 0x4394
#define LLR_COEF_L_DELAY_SPREAD_C_M 0x38
#define LLR_COEF_TH_C 0x4394
#define LLR_COEF_TH_C_M 0x1C0
#define LLR_SCAL_MODE_C 0x4394
#define LLR_SCAL_MODE_C_M 0xE00
#define LDPC_R12_MAX_ITER_C 0x4398
#define LDPC_R12_MAX_ITER_C_M 0xF
#define LDPC_R23_MAX_ITER_C 0x4398
#define LDPC_R23_MAX_ITER_C_M 0xF0
#define LDPC_R34_MAX_ITER_C 0x4398
#define LDPC_R34_MAX_ITER_C_M 0xF00
#define LDPC_R56_MAX_ITER_C 0x4398
#define LDPC_R56_MAX_ITER_C_M 0xF000
#define LDPC_STBC_MAX_ITER_C 0x4398
#define LDPC_STBC_MAX_ITER_C_M 0xF0000
#define SEL_DEFAULT_ITER_C 0x4398
#define SEL_DEFAULT_ITER_C_M 0x100000
#define PACKET_FMT_C 0x43A0
#define PACKET_FMT_C_M 0x7
#define PFD_EN_C 0x43A0
#define PFD_EN_C_M 0x8
#define PFD_HE_ER_BLOCK_C 0x43A0
#define PFD_HE_ER_BLOCK_C_M 0x10
#define PFD_HE_MU_BLOCK_C 0x43A0
#define PFD_HE_MU_BLOCK_C_M 0x20
#define PFD_HE_SU_BLOCK_C 0x43A0
#define PFD_HE_SU_BLOCK_C_M 0x40
#define PFD_HE_TB_BLOCK_C 0x43A0
#define PFD_HE_TB_BLOCK_C_M 0x80
#define PFD_HT_BLOCK_C 0x43A0
#define PFD_HT_BLOCK_C_M 0x100
#define PFD_LEG_BLOCK_C 0x43A0
#define PFD_LEG_BLOCK_C_M 0x200
#define PFD_VHT_BLOCK_C 0x43A0
#define PFD_VHT_BLOCK_C_M 0x400
#define MANUAL_SIMI_FLAG_EN_C 0x43A0
#define MANUAL_SIMI_FLAG_EN_C_M 0x800
#define SIMI_FLAG_C 0x43A0
#define SIMI_FLAG_C_M 0x1000
#define LDPC_SU_SHARE_ITER_EN_C 0x43A8
#define LDPC_SU_SHARE_ITER_EN_C_M 0x1
#define BOARDCAST_STA_ID_C 0x43B0
#define BOARDCAST_STA_ID_C_M 0x7FF
#define TARGET_STA_ID_0_C 0x43B0
#define TARGET_STA_ID_0_C_M 0x3FF800
#define TARGET_BSS_COLOR_0_C 0x43B0
#define TARGET_BSS_COLOR_0_C_M 0xFC00000
#define BSS_COLOR_MAP_VLD_0_C 0x43B0
#define BSS_COLOR_MAP_VLD_0_C_M 0x10000000
#define BSS_COLOR_MAP_VLD_1_C 0x43B0
#define BSS_COLOR_MAP_VLD_1_C_M 0x20000000
#define BSS_COLOR_MAP_VLD_2_C 0x43B0
#define BSS_COLOR_MAP_VLD_2_C_M 0x40000000
#define BSS_COLOR_MAP_VLD_3_C 0x43B0
#define BSS_COLOR_MAP_VLD_3_C_M 0x80000000
#define TARGET_STA_ID_1_C 0x43B4
#define TARGET_STA_ID_1_C_M 0x7FF
#define TARGET_STA_ID_2_C 0x43B4
#define TARGET_STA_ID_2_C_M 0x3FF800
#define TARGET_BSS_COLOR_1_C 0x43B4
#define TARGET_BSS_COLOR_1_C_M 0xFC00000
#define VHT_SIGB_NDP_CHK_EN_C 0x43B4
#define VHT_SIGB_NDP_CHK_EN_C_M 0x10000000
#define SNIFFER_MODE_EN_C 0x43B4
#define SNIFFER_MODE_EN_C_M 0x20000000
#define TARGET_STA_ID_3_C 0x43B8
#define TARGET_STA_ID_3_C_M 0x7FF
#define TARGET_BSS_COLOR_2_C 0x43B8
#define TARGET_BSS_COLOR_2_C_M 0x1F800
#define TARGET_BSS_COLOR_3_C 0x43B8
#define TARGET_BSS_COLOR_3_C_M 0x7E0000
#define MIN_SIVAL_TH_C 0x43BC
#define MIN_SIVAL_TH_C_M 0xFF
#define COND_TH_C 0x43BC
#define COND_TH_C_M 0x3F00
#define COND_NUM_COUNT_NORM_FCTR_C 0x43BC
#define COND_NUM_COUNT_NORM_FCTR_C_M 0x4000
#define MIN_SIGVAL_COUNT_NORM_FCTR_C 0x43BC
#define MIN_SIGVAL_COUNT_NORM_FCTR_C_M 0x8000
#define SIG_RPT_GRP_FCTR_C 0x43BC
#define SIG_RPT_GRP_FCTR_C_M 0x10000
#define TRACKING_RSV_C 0x43C0
#define TRACKING_RSV_C_M 0xFFFFFFFF
#define NOISE_VAR_TH_0_C 0x43C4
#define NOISE_VAR_TH_0_C_M 0xFFFFFF
#define USER_EXIST_N1_C 0x43C4
#define USER_EXIST_N1_C_M 0xFF000000
#define NOISE_VAR_TH_1_C 0x43C8
#define NOISE_VAR_TH_1_C_M 0xFFFFFF
#define USER_EXIST_N2_C 0x43C8
#define USER_EXIST_N2_C_M 0xFF000000
#define FORCE_RCFO_VAL_C 0x43CC
#define FORCE_RCFO_VAL_C_M 0xFFFF
#define LPBW_KI_E_C 0x43CC
#define LPBW_KI_E_C_M 0xFFFF0000
#define LPBW_KP_E_C 0x43D0
#define LPBW_KP_E_C_M 0xFFF
#define CH_TRACKING_NST_C 0x43D0
#define CH_TRACKING_NST_C_M 0x3FF000
#define EVM_RPT_SCIDX_C 0x43D0
#define EVM_RPT_SCIDX_C_M 0xFFC00000
#define LPBW_OUT_LMT_C 0x43D4
#define LPBW_OUT_LMT_C_M 0x3FF
#define USER_EXIST_CSI_C 0x43D4
#define USER_EXIST_CSI_C_M 0xFFC00
#define USER_EXIST_N3_C 0x43D4
#define USER_EXIST_N3_C_M 0xFF00000
#define USER_EXIST_T1_C 0x43D4
#define USER_EXIST_T1_C_M 0xF0000000
#define USER_EXIST_N4_C 0x43D8
#define USER_EXIST_N4_C_M 0xFF
#define USER_EXIST_N9_C 0x43D8
#define USER_EXIST_N9_C_M 0xFF00
#define USER_EXIST_NU_C 0x43D8
#define USER_EXIST_NU_C_M 0xFF0000
#define ALPHA_FOR_CFO_DATA_00_C 0x43D8
#define ALPHA_FOR_CFO_DATA_00_C_M 0x3F000000
#define EVM_RPT_NSC0_C 0x43D8
#define EVM_RPT_NSC0_C_M 0xC0000000
#define ALPHA_FOR_CFO_DATA_01_C 0x43DC
#define ALPHA_FOR_CFO_DATA_01_C_M 0x3F
#define ALPHA_FOR_CFO_DATA_02_C 0x43DC
#define ALPHA_FOR_CFO_DATA_02_C_M 0xFC0
#define ALPHA_FOR_CFO_DATA_03_C 0x43DC
#define ALPHA_FOR_CFO_DATA_03_C_M 0x3F000
#define ALPHA_FOR_CFO_DATA_10_C 0x43DC
#define ALPHA_FOR_CFO_DATA_10_C_M 0xFC0000
#define ALPHA_FOR_CFO_DATA_11_C 0x43DC
#define ALPHA_FOR_CFO_DATA_11_C_M 0x3F000000
#define EVM_RPT_NSC1_C 0x43DC
#define EVM_RPT_NSC1_C_M 0xC0000000
#define ALPHA_FOR_CFO_DATA_12_C 0x43E0
#define ALPHA_FOR_CFO_DATA_12_C_M 0x3F
#define ALPHA_FOR_CFO_DATA_13_C 0x43E0
#define ALPHA_FOR_CFO_DATA_13_C_M 0xFC0
#define ALPHA_FOR_CFO_DATA_20_C 0x43E0
#define ALPHA_FOR_CFO_DATA_20_C_M 0x3F000
#define ALPHA_FOR_CFO_DATA_21_C 0x43E0
#define ALPHA_FOR_CFO_DATA_21_C_M 0xFC0000
#define ALPHA_FOR_CFO_DATA_22_C 0x43E0
#define ALPHA_FOR_CFO_DATA_22_C_M 0x3F000000
#define EVM_RPT_ALPHA0_C 0x43E0
#define EVM_RPT_ALPHA0_C_M 0xC0000000
#define ALPHA_FOR_CFO_DATA_23_C 0x43E4
#define ALPHA_FOR_CFO_DATA_23_C_M 0x3F
#define ALPHA_FOR_CFO_PILOT_00_C 0x43E4
#define ALPHA_FOR_CFO_PILOT_00_C_M 0xFC0
#define ALPHA_FOR_CFO_PILOT_01_C 0x43E4
#define ALPHA_FOR_CFO_PILOT_01_C_M 0x3F000
#define ALPHA_FOR_CFO_PILOT_02_C 0x43E4
#define ALPHA_FOR_CFO_PILOT_02_C_M 0xFC0000
#define ALPHA_FOR_CFO_PILOT_03_C 0x43E4
#define ALPHA_FOR_CFO_PILOT_03_C_M 0x3F000000
#define EVM_RPT_ALPHA1_C 0x43E4
#define EVM_RPT_ALPHA1_C_M 0xC0000000
#define ALPHA_FOR_CFO_PILOT_10_C 0x43E8
#define ALPHA_FOR_CFO_PILOT_10_C_M 0x3F
#define ALPHA_FOR_CFO_PILOT_11_C 0x43E8
#define ALPHA_FOR_CFO_PILOT_11_C_M 0xFC0
#define ALPHA_FOR_CFO_PILOT_12_C 0x43E8
#define ALPHA_FOR_CFO_PILOT_12_C_M 0x3F000
#define ALPHA_FOR_CFO_PILOT_13_C 0x43E8
#define ALPHA_FOR_CFO_PILOT_13_C_M 0xFC0000
#define ALPHA_FOR_CFO_PILOT_20_C 0x43E8
#define ALPHA_FOR_CFO_PILOT_20_C_M 0x3F000000
#define N_HESYM_EXT_EN_C 0x43E8
#define N_HESYM_EXT_EN_C_M 0x40000000
#define CH_TRACKING_COEF_SEL_C 0x43E8
#define CH_TRACKING_COEF_SEL_C_M 0x80000000
#define ALPHA_FOR_CFO_PILOT_21_C 0x43EC
#define ALPHA_FOR_CFO_PILOT_21_C_M 0x3F
#define ALPHA_FOR_CFO_PILOT_22_C 0x43EC
#define ALPHA_FOR_CFO_PILOT_22_C_M 0xFC0
#define ALPHA_FOR_CFO_PILOT_23_C 0x43EC
#define ALPHA_FOR_CFO_PILOT_23_C_M 0x3F000
#define ALPHA_FOR_H_00_C 0x43EC
#define ALPHA_FOR_H_00_C_M 0xFC0000
#define ALPHA_FOR_H_01_C 0x43EC
#define ALPHA_FOR_H_01_C_M 0x3F000000
#define CH_TRACKING_EN_C 0x43EC
#define CH_TRACKING_EN_C_M 0x40000000
#define CSI_WGT_BYPASS_CPE_EN_C 0x43EC
#define CSI_WGT_BYPASS_CPE_EN_C_M 0x80000000
#define ALPHA_FOR_H_02_C 0x43F0
#define ALPHA_FOR_H_02_C_M 0x3F
#define ALPHA_FOR_H_03_C 0x43F0
#define ALPHA_FOR_H_03_C_M 0xFC0
#define ALPHA_FOR_H_10_C 0x43F0
#define ALPHA_FOR_H_10_C_M 0x3F000
#define ALPHA_FOR_H_11_C 0x43F0
#define ALPHA_FOR_H_11_C_M 0xFC0000
#define ALPHA_FOR_H_12_C 0x43F0
#define ALPHA_FOR_H_12_C_M 0x3F000000
#define DATA_TRACKING_EN_C 0x43F0
#define DATA_TRACKING_EN_C_M 0x40000000
#define EVM_RPT_MODE_C 0x43F0
#define EVM_RPT_MODE_C_M 0x80000000
#define ALPHA_FOR_H_13_C 0x43F4
#define ALPHA_FOR_H_13_C_M 0x3F
#define ALPHA_FOR_H_20_C 0x43F4
#define ALPHA_FOR_H_20_C_M 0xFC0
#define ALPHA_FOR_H_21_C 0x43F4
#define ALPHA_FOR_H_21_C_M 0x3F000
#define ALPHA_FOR_H_22_C 0x43F4
#define ALPHA_FOR_H_22_C_M 0xFC0000
#define ALPHA_FOR_H_23_C 0x43F4
#define ALPHA_FOR_H_23_C_M 0x3F000000
#define FORCE_RCFO_EN_C 0x43F4
#define FORCE_RCFO_EN_C_M 0x40000000
#define LGY80_TRACKING_EN_C 0x43F4
#define LGY80_TRACKING_EN_C_M 0x80000000
#define ALPHA_FOR_NOISE_VAR_0_C 0x43F8
#define ALPHA_FOR_NOISE_VAR_0_C_M 0x3F
#define ALPHA_FOR_NOISE_VAR_1_C 0x43F8
#define ALPHA_FOR_NOISE_VAR_1_C_M 0xFC0
#define CH_TRACKING_A0_C 0x43F8
#define CH_TRACKING_A0_C_M 0x3F000
#define CH_TRACKING_A1_C 0x43F8
#define CH_TRACKING_A1_C_M 0xFC0000
#define CH_TRACKING_A1_LGY80_C 0x43F8
#define CH_TRACKING_A1_LGY80_C_M 0x3F000000
#define LOOP_DATA_EN_C 0x43F8
#define LOOP_DATA_EN_C_M 0x40000000
#define LOOP_FILTER_EN_C 0x43F8
#define LOOP_FILTER_EN_C_M 0x80000000
#define CH_TRACKING_A1_STBC_C 0x43FC
#define CH_TRACKING_A1_STBC_C_M 0x3F
#define CH_TRACKING_A2_C 0x43FC
#define CH_TRACKING_A2_C_M 0xFC0
#define CH_TRACKING_A2_LGY80_C 0x43FC
#define CH_TRACKING_A2_LGY80_C_M 0x3F000
#define CH_TRACKING_A2_STBC_C 0x43FC
#define CH_TRACKING_A2_STBC_C_M 0xFC0000
#define USER_EXIST_R1_C 0x43FC
#define USER_EXIST_R1_C_M 0x3F000000
#define NOISE_TRACKING_EN_C 0x43FC
#define NOISE_TRACKING_EN_C_M 0x40000000
#define SYMBOL_COUNT_SEL_C 0x43FC
#define SYMBOL_COUNT_SEL_C_M 0x80000000
#define USER_EXIST_R2_C 0x4400
#define USER_EXIST_R2_C_M 0x3F
#define USER_EXIST_R3_C 0x4400
#define USER_EXIST_R3_C_M 0xFC0
#define USER_EXIST_R4_C 0x4400
#define USER_EXIST_R4_C_M 0x3F000
#define USER_EXIST_R9_C 0x4400
#define USER_EXIST_R9_C_M 0xFC0000
#define CH_TRACKING_SYMB0_C 0x4400
#define CH_TRACKING_SYMB0_C_M 0x1F000000
#define CSI_WGT_BYPASS_CPE_TH_C 0x4400
#define CSI_WGT_BYPASS_CPE_TH_C_M 0xE0000000
#define CH_TRACKING_SYMB1_C 0x4404
#define CH_TRACKING_SYMB1_C_M 0x1F
#define LPBW_SEL_D0_C 0x4404
#define LPBW_SEL_D0_C_M 0x3E0
#define LPBW_SEL_D0_TB_C 0x4404
#define LPBW_SEL_D0_TB_C_M 0x7C00
#define LPBW_SEL_D1_C 0x4404
#define LPBW_SEL_D1_C_M 0xF8000
#define LPBW_SEL_D1_HESU_C 0x4404
#define LPBW_SEL_D1_HESU_C_M 0x1F00000
#define LPBW_SEL_D1_TB_C 0x4404
#define LPBW_SEL_D1_TB_C_M 0x3E000000
#define LPBW_SEL_D1_LGY_C 0x4408
#define LPBW_SEL_D1_LGY_C_M 0x1F
#define LPBW_SEL_D1_STBC_C 0x4408
#define LPBW_SEL_D1_STBC_C_M 0x3E0
#define LPBW_SEL_D2_C 0x4408
#define LPBW_SEL_D2_C_M 0x7C00
#define LPBW_SEL_D2_HESU_C 0x4408
#define LPBW_SEL_D2_HESU_C_M 0xF8000
#define LPBW_SEL_D2_TB_C 0x4408
#define LPBW_SEL_D2_TB_C_M 0x1F00000
#define LPBW_SEL_D2_LGY_C 0x4408
#define LPBW_SEL_D2_LGY_C_M 0x3E000000
#define LPBW_SEL_D2_STBC_C 0x440C
#define LPBW_SEL_D2_STBC_C_M 0x1F
#define LPBW_SEL_P0_C 0x440C
#define LPBW_SEL_P0_C_M 0x3E0
#define LPBW_SEL_P0_TB_C 0x440C
#define LPBW_SEL_P0_TB_C_M 0x7C00
#define LPBW_SEL_P1_C 0x440C
#define LPBW_SEL_P1_C_M 0xF8000
#define LPBW_SEL_P1_HESU_C 0x440C
#define LPBW_SEL_P1_HESU_C_M 0x1F00000
#define LPBW_SEL_P1_TB_C 0x440C
#define LPBW_SEL_P1_TB_C_M 0x3E000000
#define LPBW_SEL_P1_LGY_C 0x4410
#define LPBW_SEL_P1_LGY_C_M 0x1F
#define LPBW_SEL_P1_STBC_C 0x4410
#define LPBW_SEL_P1_STBC_C_M 0x3E0
#define LPBW_SEL_P2_C 0x4410
#define LPBW_SEL_P2_C_M 0x7C00
#define LPBW_SEL_P2_HESU_C 0x4410
#define LPBW_SEL_P2_HESU_C_M 0xF8000
#define LPBW_SEL_P2_TB_C 0x4410
#define LPBW_SEL_P2_TB_C_M 0x1F00000
#define LPBW_SEL_P2_LGY_C 0x4410
#define LPBW_SEL_P2_LGY_C_M 0x3E000000
#define LPBW_SEL_P2_STBC_C 0x4414
#define LPBW_SEL_P2_STBC_C_M 0x1F
#define LPBW_SW_SYMB0_C 0x4414
#define LPBW_SW_SYMB0_C_M 0x3E0
#define LPBW_SW_SYMB1_C 0x4414
#define LPBW_SW_SYMB1_C_M 0x7C00
#define USER_EXIST_T4_C 0x4414
#define USER_EXIST_T4_C_M 0x78000
#define EVM_RPT_RUIDX_C 0x4414
#define EVM_RPT_RUIDX_C_M 0x380000
#define T2F_R_DC_EST_FORCE_I_C 0x4420
#define T2F_R_DC_EST_FORCE_I_C_M 0xFFF
#define T2F_R_DC_EST_FORCE_Q_C 0x4420
#define T2F_R_DC_EST_FORCE_Q_C_M 0xFFF000
#define T2F_R_GI2_COMB_THR_C 0x4420
#define T2F_R_GI2_COMB_THR_C_M 0x7F000000
#define T2F_R_BT_DYN_DC_EST_EN_C 0x4420
#define T2F_R_BT_DYN_DC_EST_EN_C_M 0x80000000
#define T2F_R_MANUAL_N_GI2_COMB_C 0x4424
#define T2F_R_MANUAL_N_GI2_COMB_C_M 0x7F
#define T2F_R_MANUAL_N_GI_COMB_C 0x4424
#define T2F_R_MANUAL_N_GI_COMB_C_M 0x1F80
#define T2F_R_MANUAL_N_SGI_COMB_C 0x4424
#define T2F_R_MANUAL_N_SGI_COMB_C_M 0x3E000
#define T2F_R_EXTRA_CH_LEN_C 0x4424
#define T2F_R_EXTRA_CH_LEN_C_M 0x3C0000
#define T2F_R_MANUAL_N_CDD_OFST_C 0x4424
#define T2F_R_MANUAL_N_CDD_OFST_C_M 0x3C00000
#define T2F_R_SBDRDY_WINDOW_LEN_C 0x4424
#define T2F_R_SBDRDY_WINDOW_LEN_C_M 0x1C000000
#define T2F_R_DC_EST_VHT_L1_C 0x4424
#define T2F_R_DC_EST_VHT_L1_C_M 0x20000000
#define T2F_R_GI2_COMB_LVL_C 0x4424
#define T2F_R_GI2_COMB_LVL_C_M 0x40000000
#define T2F_R_LNA_BASED_DC_UPD_EN_C 0x4424
#define T2F_R_LNA_BASED_DC_UPD_EN_C_M 0x80000000
#define T2F_R_VHT_LTF_DCCL_MODE_C 0x4428
#define T2F_R_VHT_LTF_DCCL_MODE_C_M 0x1
#define T2F_R_DC_EST_FORCE_EN_C 0x4428
#define T2F_R_DC_EST_FORCE_EN_C_M 0x2
#define T2F_R_MANUAL_GI_COMB_EN_C 0x4428
#define T2F_R_MANUAL_GI_COMB_EN_C_M 0x4
#define T2F_R_MANUAL_CDD_OFST_EN_C 0x4428
#define T2F_R_MANUAL_CDD_OFST_EN_C_M 0x8
#define T2F_R_RXFIR_COMP_BW20_FIR0_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW20_FIR0_EN_C_M 0x10
#define T2F_R_RXFIR_COMP_BW20_FIR1_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW20_FIR1_EN_C_M 0x20
#define T2F_R_RXFIR_COMP_BW20_FIR2_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW20_FIR2_EN_C_M 0x40
#define T2F_R_RXFIR_COMP_BW40_FIR0_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW40_FIR0_EN_C_M 0x80
#define T2F_R_RXFIR_COMP_BW40_FIR1_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW40_FIR1_EN_C_M 0x100
#define T2F_R_RXFIR_COMP_BW40_FIR2_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW40_FIR2_EN_C_M 0x200
#define T2F_R_RXFIR_COMP_BW80_FIR0_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW80_FIR0_EN_C_M 0x400
#define T2F_R_RXFIR_COMP_BW80_FIR1_EN_C 0x4428
#define T2F_R_RXFIR_COMP_BW80_FIR1_EN_C_M 0x800
#define T2F_R_RXFIR_COMP_EN_C 0x4428
#define T2F_R_RXFIR_COMP_EN_C_M 0x1000
#define DUMMY_0_C 0x442C
#define DUMMY_0_C_M 0xFFFFFFFF
#define DUMMY_1_C 0x4430
#define DUMMY_1_C_M 0xFFFFFFFF
#define DUMMY_2_C 0x4434
#define DUMMY_2_C_M 0xFFFFFFFF
#define DUMMY_3_C 0x4438
#define DUMMY_3_C_M 0xFFFFFFFF
#define HE_TB_CCA_END_C 0x443C
#define HE_TB_CCA_END_C_M 0x3FF
#define HE_TB_CCA_ON_C 0x443C
#define HE_TB_CCA_ON_C_M 0xFFC00
#define HE_TB_PD_COUNT_C 0x443C
#define HE_TB_PD_COUNT_C_M 0x3FF00000
#define MIMO_PS_OPT_C 0x443C
#define MIMO_PS_OPT_C_M 0xC0000000
#define HE_TB_RX_ON_C 0x4440
#define HE_TB_RX_ON_C_M 0x3FF
#define HE_TB_SBD_COUNT_C 0x4440
#define HE_TB_SBD_COUNT_C_M 0xFFC00
#define MAXOFST_C 0x4440
#define MAXOFST_C_M 0x3FF00000
#define R11RCCA_EN_C 0x4440
#define R11RCCA_EN_C_M 0x40000000
#define R55M_DET_EN_C 0x4440
#define R55M_DET_EN_C_M 0x80000000
#define MINOFST_C 0x4444
#define MINOFST_C_M 0xFF
#define FGT_FCTR_C 0x4444
#define FGT_FCTR_C_M 0x7F00
#define OFDMA_STF_OFST_C 0x4444
#define OFDMA_STF_OFST_C_M 0x1F8000
#define RF2SYNC_DLY_C 0x4444
#define RF2SYNC_DLY_C_M 0x7E00000
#define DFEDLY_BW20_C 0x4444
#define DFEDLY_BW20_C_M 0xF8000000
#define DFEDLY_BW40_C 0x4448
#define DFEDLY_BW40_C_M 0x1F
#define DFEDLY_BW80_C 0x4448
#define DFEDLY_BW80_C_M 0x3E0
#define OPPDLY_C 0x4448
#define OPPDLY_C_M 0x7C00
#define SYNCDLY_BW20_C 0x4448
#define SYNCDLY_BW20_C_M 0xF8000
#define SYNCDLY_BW40_C 0x4448
#define SYNCDLY_BW40_C_M 0x1F00000
#define SYNCDLY_BW80_C 0x4448
#define SYNCDLY_BW80_C_M 0x3E000000
#define PSD_TOP_EN_C 0x4448
#define PSD_TOP_EN_C_M 0x40000000
#define ACI_DET_EN_C 0x4448
#define ACI_DET_EN_C_M 0x80000000
#define NBIDLY_C 0x444C
#define NBIDLY_C_M 0xF
#define WAIT_SBD_TIME_C 0x444C
#define WAIT_SBD_TIME_C_M 0xF0
#define WAIT_SEG0_PD_TIME_C 0x444C
#define WAIT_SEG0_PD_TIME_C_M 0xF00
#define WAIT_SEG1_PD_TIME_C 0x444C
#define WAIT_SEG1_PD_TIME_C_M 0xF000
#define CCX_SOURCE_SEL_C 0x444C
#define CCX_SOURCE_SEL_C_M 0x70000
#define DATADLY_BW20_C 0x444C
#define DATADLY_BW20_C_M 0x380000
#define DATADLY_BW40_C 0x444C
#define DATADLY_BW40_C_M 0x1C00000
#define DATADLY_BW80_C 0x444C
#define DATADLY_BW80_C_M 0xE000000
#define SNR_REQ_1SS_MCS0_C 0x444C
#define SNR_REQ_1SS_MCS0_C_M 0x70000000
#define AGC_LPW_C 0x444C
#define AGC_LPW_C_M 0x80000000
#define SNR_REQ_1SS_MCS1_C 0x4450
#define SNR_REQ_1SS_MCS1_C_M 0x7
#define SNR_REQ_1SS_MCS10_C 0x4450
#define SNR_REQ_1SS_MCS10_C_M 0x38
#define SNR_REQ_1SS_MCS11_C 0x4450
#define SNR_REQ_1SS_MCS11_C_M 0x1C0
#define SNR_REQ_1SS_MCS2_C 0x4450
#define SNR_REQ_1SS_MCS2_C_M 0xE00
#define SNR_REQ_1SS_MCS3_C 0x4450
#define SNR_REQ_1SS_MCS3_C_M 0x7000
#define SNR_REQ_1SS_MCS4_C 0x4450
#define SNR_REQ_1SS_MCS4_C_M 0x38000
#define SNR_REQ_1SS_MCS5_C 0x4450
#define SNR_REQ_1SS_MCS5_C_M 0x1C0000
#define SNR_REQ_1SS_MCS6_C 0x4450
#define SNR_REQ_1SS_MCS6_C_M 0xE00000
#define SNR_REQ_1SS_MCS7_C 0x4450
#define SNR_REQ_1SS_MCS7_C_M 0x7000000
#define SNR_REQ_1SS_MCS8_C 0x4450
#define SNR_REQ_1SS_MCS8_C_M 0x38000000
#define ASSIGN_SBD_OPT_C 0x4450
#define ASSIGN_SBD_OPT_C_M 0x40000000
#define DCCL4SYNC_EN_C 0x4450
#define DCCL4SYNC_EN_C_M 0x80000000
#define SNR_REQ_1SS_MCS9_C 0x4454
#define SNR_REQ_1SS_MCS9_C_M 0x7
#define DFIR_EN_C 0x4454
#define DFIR_EN_C_M 0x8
#define HE_TB_CFO_EN_C 0x4454
#define HE_TB_CFO_EN_C_M 0x10
#define HE_TB_SYNC_FREE_C 0x4454
#define HE_TB_SYNC_FREE_C_M 0x20
#define I_ONLY_C 0x4454
#define I_ONLY_C_M 0x40
#define I_ONLY_S_C 0x4454
#define I_ONLY_S_C_M 0x80
#define IF_SEG0_PRIM80_C 0x4454
#define IF_SEG0_PRIM80_C_M 0x100
#define MIMO_PS_EN_C 0x4454
#define MIMO_PS_EN_C_M 0x200
#define NBI_EN_C 0x4454
#define NBI_EN_C_M 0x400
#define OFDMA_COMB_EN_C 0x4454
#define OFDMA_COMB_EN_C_M 0x800
#define POP_PD_FIRST_EN_C 0x4454
#define POP_PD_FIRST_EN_C_M 0x1000
#define SBDSEL_C 0x4454
#define SBDSEL_C_M 0x2000
#define SBDSEL_OFDMA_C 0x4454
#define SBDSEL_OFDMA_C_M 0x4000
#define SBF_EN_C 0x4454
#define SBF_EN_C_M 0x8000
#define SIMI_THD_0_C 0x445C
#define SIMI_THD_0_C_M 0x3FF
#define SIMI_THD_1_C 0x445C
#define SIMI_THD_1_C_M 0xFFC00
#define SIMI_THD_2_C 0x445C
#define SIMI_THD_2_C_M 0x3FF00000
#define EXTRATONE_PW_WGT_C 0x445C
#define EXTRATONE_PW_WGT_C_M 0xC0000000
#define SIMI_THD_3_C 0x4460
#define SIMI_THD_3_C_M 0x3FF
#define COMBINE_GAIN_GAP_DB_C 0x4460
#define COMBINE_GAIN_GAP_DB_C_M 0x7C00
#define EXTRATONE_PW_CHK_SNR_THR_C 0x4460
#define EXTRATONE_PW_CHK_SNR_THR_C_M 0x38000
#define SNR_COMB_IDX_C 0x4460
#define SNR_COMB_IDX_C_M 0xC0000
#define EXTRATONE_PW_CHK_EN_C 0x4460
#define EXTRATONE_PW_CHK_EN_C_M 0x100000
#define MANUL_SNR_COMB_IDX_EN_C 0x4460
#define MANUL_SNR_COMB_IDX_EN_C_M 0x200000
#define POSITIVE_SIMI_DET_EN_C 0x4460
#define POSITIVE_SIMI_DET_EN_C_M 0x400000
#define REAL_OR_ABS_SIMI_DET_C 0x4460
#define REAL_OR_ABS_SIMI_DET_C_M 0x800000
#define PATHA_T2F_R_DCCL_DATA_BKP1_C 0x4464
#define PATHA_T2F_R_DCCL_DATA_BKP1_C_M 0xFFFFFFFF
#define PATHA_T2F_R_DCCL_DATA_BKP2_C 0x4468
#define PATHA_T2F_R_DCCL_DATA_BKP2_C_M 0xFFFFFFFF
#define PATHA_T2F_R_DC_EST_FILT_EN_C 0x446C
#define PATHA_T2F_R_DC_EST_FILT_EN_C_M 0x1
#define PATHB_T2F_R_DCCL_DATA_BKP1_C 0x4470
#define PATHB_T2F_R_DCCL_DATA_BKP1_C_M 0xFFFFFFFF
#define PATHB_T2F_R_DCCL_DATA_BKP2_C 0x4474
#define PATHB_T2F_R_DCCL_DATA_BKP2_C_M 0xFFFFFFFF
#define PATHB_T2F_R_DC_EST_FILT_EN_C 0x4478
#define PATHB_T2F_R_DC_EST_FILT_EN_C_M 0x1
#define SNR_LOSS_RPT_BUFFER_IDX_SEL_C 0x447C
#define SNR_LOSS_RPT_BUFFER_IDX_SEL_C_M 0x3F
#define SNR_LOSS_RPT_TYPE_C 0x447C
#define SNR_LOSS_RPT_TYPE_C_M 0xC0
#define NV_TYPE_C 0x447C
#define NV_TYPE_C_M 0x100
#define PRECODING_SCHEME_C 0x447C
#define PRECODING_SCHEME_C_M 0x200
#define TXBF_PL_2NSTS_TH0_STS0_C 0x4480
#define TXBF_PL_2NSTS_TH0_STS0_C_M 0x7F
#define TXBF_PL_2NSTS_TH0_STS1_C 0x4480
#define TXBF_PL_2NSTS_TH0_STS1_C_M 0x3F80
#define TXBF_PL_2NSTS_TH1_STS0_C 0x4480
#define TXBF_PL_2NSTS_TH1_STS0_C_M 0x1FC000
#define TXBF_PL_2NSTS_TH1_STS1_C 0x4480
#define TXBF_PL_2NSTS_TH1_STS1_C_M 0xFE00000
#define TXBF_PL_TH_SCAL_C 0x4480
#define TXBF_PL_TH_SCAL_C_M 0x10000000
#define TXBF_PL_EN_C 0x4480
#define TXBF_PL_EN_C_M 0x20000000
#define TXBF_PL_2NSTS_TH2_STS0_C 0x4484
#define TXBF_PL_2NSTS_TH2_STS0_C_M 0x7F
#define TXBF_PL_2NSTS_TH2_STS1_C 0x4484
#define TXBF_PL_2NSTS_TH2_STS1_C_M 0x3F80
#define TXBF_PL_2NSTS_TH3_STS0_C 0x4484
#define TXBF_PL_2NSTS_TH3_STS0_C_M 0x1FC000
#define TXBF_PL_2NSTS_TH3_STS1_C 0x4484
#define TXBF_PL_2NSTS_TH3_STS1_C_M 0xFE00000
#define STEER_MATRIX_INTERPOLATION_EN_C 0x4488
#define STEER_MATRIX_INTERPOLATION_EN_C_M 0x4
#define CFO_COMP_SEG0_312P5KHZ_0_C 0x448C
#define CFO_COMP_SEG0_312P5KHZ_0_C_M 0xFFF
#define CFO_COMP_SEG0_312P5KHZ_1_C 0x448C
#define CFO_COMP_SEG0_312P5KHZ_1_C_M 0xFFF000
#define TX_TIMING_C 0x448C
#define TX_TIMING_C_M 0xFF000000
#define CFO_COMP_SEG0_312P5KHZ_2_C 0x4490
#define CFO_COMP_SEG0_312P5KHZ_2_C_M 0xFFF
#define CFO_COMP_SEG0_312P5KHZ_3_C 0x4490
#define CFO_COMP_SEG0_312P5KHZ_3_C_M 0xFFF000
#define CFO_WGTING_C 0x4490
#define CFO_WGTING_C_M 0xF000000
#define PRIM_CH_C 0x4490
#define PRIM_CH_C_M 0x70000000
#define DAC_CLK_IDX_C 0x4490
#define DAC_CLK_IDX_C_M 0x80000000
#define CFO_COMP_SEG1_312P5KHZ_0_C 0x4494
#define CFO_COMP_SEG1_312P5KHZ_0_C_M 0xFFF
#define CFO_COMP_SEG1_312P5KHZ_1_C 0x4494
#define CFO_COMP_SEG1_312P5KHZ_1_C_M 0xFFF000
#define TX_BANDEDGE_CFG_C 0x4494
#define TX_BANDEDGE_CFG_C_M 0x3000000
#define SPATIAL_MAP_MODE_IDX_C 0x4494
#define SPATIAL_MAP_MODE_IDX_C_M 0xC000000
#define TXBF_BYPASS_EN_C 0x4494
#define TXBF_BYPASS_EN_C_M 0x10000000
#define CFO_COMP_SEG0_VLD_0_C 0x4494
#define CFO_COMP_SEG0_VLD_0_C_M 0x20000000
#define CFO_COMP_SEG0_VLD_1_C 0x4494
#define CFO_COMP_SEG0_VLD_1_C_M 0x40000000
#define CFO_COMP_SEG0_VLD_2_C 0x4494
#define CFO_COMP_SEG0_VLD_2_C_M 0x80000000
#define CFO_COMP_SEG1_312P5KHZ_2_C 0x4498
#define CFO_COMP_SEG1_312P5KHZ_2_C_M 0xFFF
#define CFO_COMP_SEG1_312P5KHZ_3_C 0x4498
#define CFO_COMP_SEG1_312P5KHZ_3_C_M 0xFFF000
#define CFO_COMP_SEG0_VLD_3_C 0x4498
#define CFO_COMP_SEG0_VLD_3_C_M 0x1000000
#define CFO_COMP_SEG1_VLD_0_C 0x4498
#define CFO_COMP_SEG1_VLD_0_C_M 0x2000000
#define CFO_COMP_SEG1_VLD_1_C 0x4498
#define CFO_COMP_SEG1_VLD_1_C_M 0x4000000
#define CFO_COMP_SEG1_VLD_2_C 0x4498
#define CFO_COMP_SEG1_VLD_2_C_M 0x8000000
#define CFO_COMP_SEG1_VLD_3_C 0x4498
#define CFO_COMP_SEG1_VLD_3_C_M 0x10000000
#define IDFT_OVER_SAMPLING_EN_C 0x4498
#define IDFT_OVER_SAMPLING_EN_C_M 0x20000000
#define IF_BANDEDGE_C 0x4498
#define IF_BANDEDGE_C_M 0x40000000
#define L_STF_TD_MODE_EN_C 0x4498
#define L_STF_TD_MODE_EN_C_M 0x80000000
#define TX_DAGC_PW_TOR_DB_C 0x449C
#define TX_DAGC_PW_TOR_DB_C_M 0x7
#define TX_DAGC_EN_C 0x449C
#define TX_DAGC_EN_C_M 0x8
#define TX_DAGC_MODE_IDX_C 0x449C
#define TX_DAGC_MODE_IDX_C_M 0x10
#define TX_SCALE_C 0x44A0
#define TX_SCALE_C_M 0x7F
#define TX_CCK_BACKOFF_C 0x44A0
#define TX_CCK_BACKOFF_C_M 0xF80
#define TX_NORMAL_BACKOFF_C 0x44A0
#define TX_NORMAL_BACKOFF_C_M 0x1F000
#define TX_BACKOFF_OFST1_C 0x44A0
#define TX_BACKOFF_OFST1_C_M 0xE0000
#define TX_BACKOFF_OFST2_C 0x44A0
#define TX_BACKOFF_OFST2_C_M 0x700000
#define TX_BACKOFF_OFST3_C 0x44A0
#define TX_BACKOFF_OFST3_C_M 0x3800000
#define TX_BACKOFF_BITMAP0_C 0x44A0
#define TX_BACKOFF_BITMAP0_C_M 0xC000000
#define TX_BACKOFF_BITMAP1_C 0x44A0
#define TX_BACKOFF_BITMAP1_C_M 0x30000000
#define TX_BACKOFF_BITMAP2_C 0x44A0
#define TX_BACKOFF_BITMAP2_C_M 0xC0000000
#define TX_BACKOFF_BITMAP3_C 0x44A4
#define TX_BACKOFF_BITMAP3_C_M 0x3
#define TX_BACKOFF_BITMAP4_C 0x44A4
#define TX_BACKOFF_BITMAP4_C_M 0xC
#define TX_BACKOFF_BITMAP5_C 0x44A4
#define TX_BACKOFF_BITMAP5_C_M 0x30
#define TX_BACKOFF_BITMAP6_C 0x44A4
#define TX_BACKOFF_BITMAP6_C_M 0xC0
#define TX_BACKOFF_BITMAP7_C 0x44A4
#define TX_BACKOFF_BITMAP7_C_M 0x300
#define OV_RPT_RST_C 0x44A4
#define OV_RPT_RST_C_M 0x400
#define OBW_TX_EN_C 0x44A8
#define OBW_TX_EN_C_M 0x1
#define TX_N_PACKET_C 0x44AC
#define TX_N_PACKET_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_0_C 0x44B0
#define TXD_HE_SIGB_CH1_0_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_1_C 0x44B4
#define TXD_HE_SIGB_CH1_1_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_10_C 0x44B8
#define TXD_HE_SIGB_CH1_10_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_11_C 0x44BC
#define TXD_HE_SIGB_CH1_11_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_12_C 0x44C0
#define TXD_HE_SIGB_CH1_12_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_13_C 0x44C4
#define TXD_HE_SIGB_CH1_13_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_14_C 0x44C8
#define TXD_HE_SIGB_CH1_14_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_15_C 0x44CC
#define TXD_HE_SIGB_CH1_15_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_2_C 0x44D0
#define TXD_HE_SIGB_CH1_2_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_3_C 0x44D4
#define TXD_HE_SIGB_CH1_3_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_4_C 0x44D8
#define TXD_HE_SIGB_CH1_4_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_5_C 0x44DC
#define TXD_HE_SIGB_CH1_5_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_6_C 0x44E0
#define TXD_HE_SIGB_CH1_6_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_7_C 0x44E4
#define TXD_HE_SIGB_CH1_7_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_8_C 0x44E8
#define TXD_HE_SIGB_CH1_8_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH1_9_C 0x44EC
#define TXD_HE_SIGB_CH1_9_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_0_C 0x44F0
#define TXD_HE_SIGB_CH2_0_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_1_C 0x44F4
#define TXD_HE_SIGB_CH2_1_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_10_C 0x44F8
#define TXD_HE_SIGB_CH2_10_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_11_C 0x44FC
#define TXD_HE_SIGB_CH2_11_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_12_C 0x4500
#define TXD_HE_SIGB_CH2_12_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_13_C 0x4504
#define TXD_HE_SIGB_CH2_13_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_14_C 0x4508
#define TXD_HE_SIGB_CH2_14_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_15_C 0x450C
#define TXD_HE_SIGB_CH2_15_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_2_C 0x4510
#define TXD_HE_SIGB_CH2_2_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_3_C 0x4514
#define TXD_HE_SIGB_CH2_3_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_4_C 0x4518
#define TXD_HE_SIGB_CH2_4_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_5_C 0x451C
#define TXD_HE_SIGB_CH2_5_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_6_C 0x4520
#define TXD_HE_SIGB_CH2_6_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_7_C 0x4524
#define TXD_HE_SIGB_CH2_7_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_8_C 0x4528
#define TXD_HE_SIGB_CH2_8_C_M 0xFFFFFFFF
#define TXD_HE_SIGB_CH2_9_C 0x452C
#define TXD_HE_SIGB_CH2_9_C_M 0xFFFFFFFF
#define USER0_DELMTER_C 0x4530
#define USER0_DELMTER_C_M 0xFFFFFFFF
#define USER0_EOF_PADDING_LEN_C 0x4534
#define USER0_EOF_PADDING_LEN_C_M 0xFFFFFFFF
#define USER0_INIT_SEED_C 0x4538
#define USER0_INIT_SEED_C_M 0xFFFFFFFF
#define USER1_DELMTER_C 0x453C
#define USER1_DELMTER_C_M 0xFFFFFFFF
#define USER1_EOF_PADDING_LEN_C 0x4540
#define USER1_EOF_PADDING_LEN_C_M 0xFFFFFFFF
#define USER1_INIT_SEED_C 0x4544
#define USER1_INIT_SEED_C_M 0xFFFFFFFF
#define USER2_DELMTER_C 0x4548
#define USER2_DELMTER_C_M 0xFFFFFFFF
#define USER2_EOF_PADDING_LEN_C 0x454C
#define USER2_EOF_PADDING_LEN_C_M 0xFFFFFFFF
#define USER2_INIT_SEED_C 0x4550
#define USER2_INIT_SEED_C_M 0xFFFFFFFF
#define USER3_DELMTER_C 0x4554
#define USER3_DELMTER_C_M 0xFFFFFFFF
#define USER3_EOF_PADDING_LEN_C 0x4558
#define USER3_EOF_PADDING_LEN_C_M 0xFFFFFFFF
#define USER3_INIT_SEED_C 0x455C
#define USER3_INIT_SEED_C_M 0xFFFFFFFF
#define TXD_VHT_SIGB0_C 0x4560
#define TXD_VHT_SIGB0_C_M 0x1FFFFFFF
#define MAC_TDRDY_EXT_CNT_I_C 0x4560
#define MAC_TDRDY_EXT_CNT_I_C_M 0xE0000000
#define TXD_VHT_SIGB1_C 0x4564
#define TXD_VHT_SIGB1_C_M 0x1FFFFFFF
#define MAC_TX_INFO_DLY_CNT_I_C 0x4564
#define MAC_TX_INFO_DLY_CNT_I_C_M 0xE0000000
#define TXD_VHT_SIGB2_C 0x4568
#define TXD_VHT_SIGB2_C_M 0x1FFFFFFF
#define TXCOMCT_HE_SIGB_MCS_C 0x4568
#define TXCOMCT_HE_SIGB_MCS_C_M 0xE0000000
#define TXD_VHT_SIGB3_C 0x456C
#define TXD_VHT_SIGB3_C_M 0x1FFFFFFF
#define TXCOMCT_N_LTF_C 0x456C
#define TXCOMCT_N_LTF_C_M 0xE0000000
#define TXD_SIGA1_C 0x4570
#define TXD_SIGA1_C_M 0x3FFFFFF
#define TAR_TXINFO_TXTP_C 0x4570
#define TAR_TXINFO_TXTP_C_M 0xFC000000
#define TXD_SIGA2_C 0x4574
#define TXD_SIGA2_C_M 0x3FFFFFF
#define TXINFO_RATE_BIAS_C 0x4574
#define TXINFO_RATE_BIAS_C_M 0xFC000000
#define TXD_LSIG_C 0x4578
#define TXD_LSIG_C_M 0xFFFFFF
#define TXINFO_CCA_PW_TH_C 0x4578
#define TXINFO_CCA_PW_TH_C_M 0xFF000000
#define TX_PADDING_ZEROS_50NS_C 0x457C
#define TX_PADDING_ZEROS_50NS_C_M 0x1FFFFF
#define TXTIMCT_N_SYM_C 0x457C
#define TXTIMCT_N_SYM_C_M 0xFFE00000
#define USER0_SERVICE_C 0x4580
#define USER0_SERVICE_C_M 0xFFFF
#define USER1_SERVICE_C 0x4580
#define USER1_SERVICE_C_M 0xFFFF0000
#define USER2_SERVICE_C 0x4584
#define USER2_SERVICE_C_M 0xFFFF
#define USER3_SERVICE_C 0x4584
#define USER3_SERVICE_C_M 0xFFFF0000
#define USER0_MDPU_LEN_BYTE_C 0x4588
#define USER0_MDPU_LEN_BYTE_C_M 0x3FFF
#define USER1_MDPU_LEN_BYTE_C 0x4588
#define USER1_MDPU_LEN_BYTE_C_M 0xFFFC000
#define TXINFO_OBW_CTS2SELF_DUP_TYPE_C 0x4588
#define TXINFO_OBW_CTS2SELF_DUP_TYPE_C_M 0xF0000000
#define USER2_MDPU_LEN_BYTE_C 0x458C
#define USER2_MDPU_LEN_BYTE_C_M 0x3FFF
#define USER3_MDPU_LEN_BYTE_C 0x458C
#define USER3_MDPU_LEN_BYTE_C_M 0xFFFC000
#define TXINFO_PATH_EN_C 0x458C
#define TXINFO_PATH_EN_C_M 0xF0000000
#define TXUSRCT0_CSI_BUF_ID_C 0x4590
#define TXUSRCT0_CSI_BUF_ID_C_M 0x7FF
#define TXUSRCT1_CSI_BUF_ID_C 0x4590
#define TXUSRCT1_CSI_BUF_ID_C_M 0x3FF800
#define TXINFO_RF_GAIN_IDX_C 0x4590
#define TXINFO_RF_GAIN_IDX_C_M 0xFFC00000
#define TXUSRCT2_CSI_BUF_ID_C 0x4594
#define TXUSRCT2_CSI_BUF_ID_C_M 0x7FF
#define TXUSRCT3_CSI_BUF_ID_C 0x4594
#define TXUSRCT3_CSI_BUF_ID_C_M 0x3FF800
#define TXINFO_TX_PW_DBM_C 0x4594
#define TXINFO_TX_PW_DBM_C_M 0x7FC00000
#define AMPDU_4BYTES_ALIGN_EN_C 0x4594
#define AMPDU_4BYTES_ALIGN_EN_C_M 0x80000000
#define USER0_N_MPDU_C 0x4598
#define USER0_N_MPDU_C_M 0x1FF
#define USER1_N_MPDU_C 0x4598
#define USER1_N_MPDU_C_M 0x3FE00
#define USER2_N_MPDU_C 0x4598
#define USER2_N_MPDU_C_M 0x7FC0000
#define TXUSRCT0_PW_BOOST_FCTR_DB_C 0x4598
#define TXUSRCT0_PW_BOOST_FCTR_DB_C_M 0xF8000000
#define USER3_N_MPDU_C 0x459C
#define USER3_N_MPDU_C_M 0x1FF
#define TXINFO_CH20_WITH_DATA_C 0x459C
#define TXINFO_CH20_WITH_DATA_C_M 0x1FE00
#define TXINFO_N_USR_C 0x459C
#define TXINFO_N_USR_C_M 0x1FE0000
#define TXINFO_TXCMD_TXTP_C 0x459C
#define TXINFO_TXCMD_TXTP_C_M 0x7E000000
#define BMODE_LOCKED_CLK_EN_C 0x459C
#define BMODE_LOCKED_CLK_EN_C_M 0x80000000
#define TXUSRCT0_RU_ALLOC_C 0x45A0
#define TXUSRCT0_RU_ALLOC_C_M 0xFF
#define TXUSRCT0_U_ID_C 0x45A0
#define TXUSRCT0_U_ID_C_M 0xFF00
#define TXUSRCT1_RU_ALLOC_C 0x45A0
#define TXUSRCT1_RU_ALLOC_C_M 0xFF0000
#define TXUSRCT1_U_ID_C 0x45A0
#define TXUSRCT1_U_ID_C_M 0xFF000000
#define TXUSRCT2_RU_ALLOC_C 0x45A4
#define TXUSRCT2_RU_ALLOC_C_M 0xFF
#define TXUSRCT2_U_ID_C 0x45A4
#define TXUSRCT2_U_ID_C_M 0xFF00
#define TXUSRCT3_RU_ALLOC_C 0x45A4
#define TXUSRCT3_RU_ALLOC_C_M 0xFF0000
#define TXUSRCT3_U_ID_C 0x45A4
#define TXUSRCT3_U_ID_C_M 0xFF000000
#define TXTIMCT_N_SYM_HESIGB_C 0x45A8
#define TXTIMCT_N_SYM_HESIGB_C_M 0x3F
#define TXUSRCT0_MCS_C 0x45A8
#define TXUSRCT0_MCS_C_M 0xFC0
#define TXUSRCT1_MCS_C 0x45A8
#define TXUSRCT1_MCS_C_M 0x3F000
#define TXUSRCT2_MCS_C 0x45A8
#define TXUSRCT2_MCS_C_M 0xFC0000
#define TXUSRCT3_MCS_C 0x45A8
#define TXUSRCT3_MCS_C_M 0x3F000000
#define BMODE_RATE_IDX_C 0x45A8
#define BMODE_RATE_IDX_C_M 0xC0000000
#define TXUSRCT1_PW_BOOST_FCTR_DB_C 0x45AC
#define TXUSRCT1_PW_BOOST_FCTR_DB_C_M 0x1F
#define TXUSRCT2_PW_BOOST_FCTR_DB_C 0x45AC
#define TXUSRCT2_PW_BOOST_FCTR_DB_C_M 0x3E0
#define TXUSRCT3_PW_BOOST_FCTR_DB_C 0x45AC
#define TXUSRCT3_PW_BOOST_FCTR_DB_C_M 0x7C00
#define TXINFO_PPDU_TYPE_C 0x45AC
#define TXINFO_PPDU_TYPE_C_M 0x78000
#define TXINFO_TX_SWING_C 0x45AC
#define TXINFO_TX_SWING_C_M 0x780000
#define TXINFO_TXSC_C 0x45AC
#define TXINFO_TXSC_C_M 0x7800000
#define TXINFO_CFO_COMP_C 0x45AC
#define TXINFO_CFO_COMP_C_M 0x38000000
#define MAC_TX_U_ID_PHASE_OPT_T_C 0x45AC
#define MAC_TX_U_ID_PHASE_OPT_T_C_M 0xC0000000
#define TXTIMCT_PKT_EXT_IDX_C 0x45B0
#define TXTIMCT_PKT_EXT_IDX_C_M 0x7
#define TXUSRCT0_N_STS_C 0x45B0
#define TXUSRCT0_N_STS_C_M 0x38
#define TXUSRCT0_N_STS_RU_TOT_C 0x45B0
#define TXUSRCT0_N_STS_RU_TOT_C_M 0x1C0
#define TXUSRCT0_STRT_STS_C 0x45B0
#define TXUSRCT0_STRT_STS_C_M 0xE00
#define TXUSRCT1_N_STS_C 0x45B0
#define TXUSRCT1_N_STS_C_M 0x7000
#define TXUSRCT1_N_STS_RU_TOT_C 0x45B0
#define TXUSRCT1_N_STS_RU_TOT_C_M 0x38000
#define TXUSRCT1_STRT_STS_C 0x45B0
#define TXUSRCT1_STRT_STS_C_M 0x1C0000
#define TXUSRCT2_N_STS_C 0x45B0
#define TXUSRCT2_N_STS_C_M 0xE00000
#define TXUSRCT2_N_STS_RU_TOT_C 0x45B0
#define TXUSRCT2_N_STS_RU_TOT_C_M 0x7000000
#define TXUSRCT2_STRT_STS_C 0x45B0
#define TXUSRCT2_STRT_STS_C_M 0x38000000
#define MAC_TXD_PHASE_OPT_I_C 0x45B0
#define MAC_TXD_PHASE_OPT_I_C_M 0xC0000000
#define TXUSRCT3_N_STS_C 0x45B4
#define TXUSRCT3_N_STS_C_M 0x7
#define TXUSRCT3_N_STS_RU_TOT_C 0x45B4
#define TXUSRCT3_N_STS_RU_TOT_C_M 0x38
#define TXUSRCT3_STRT_STS_C 0x45B4
#define TXUSRCT3_STRT_STS_C_M 0x1C0
#define SOURCE_GEN_MODE_IDX_C 0x45B4
#define SOURCE_GEN_MODE_IDX_C_M 0x600
#define TXCOMCT_GI_TYPE_C 0x45B4
#define TXCOMCT_GI_TYPE_C_M 0x1800
#define TXCOMCT_LTF_TYPE_C 0x45B4
#define TXCOMCT_LTF_TYPE_C_M 0x6000
#define TXINFO_DBW_IDX_C 0x45B4
#define TXINFO_DBW_IDX_C_M 0x18000
#define TXINFO_PATH_MAP_A_C 0x45B4
#define TXINFO_PATH_MAP_A_C_M 0x60000
#define TXINFO_PATH_MAP_B_C 0x45B4
#define TXINFO_PATH_MAP_B_C_M 0x180000
#define TXINFO_PATH_MAP_C_C 0x45B4
#define TXINFO_PATH_MAP_C_C_M 0x600000
#define TXINFO_PATH_MAP_D_C 0x45B4
#define TXINFO_PATH_MAP_D_C_M 0x1800000
#define TXTIMCT_PRE_FEC_FCTR_C 0x45B4
#define TXTIMCT_PRE_FEC_FCTR_C_M 0x6000000
#define BMODE_LONG_PREAMBLE_EN_C 0x45B4
#define BMODE_LONG_PREAMBLE_EN_C_M 0x8000000
#define MAC_TX_PMAC_EN_I_C 0x45B4
#define MAC_TX_PMAC_EN_I_C_M 0x10000000
#define TAR_TXINFO_TXTP_EN_C 0x45B4
#define TAR_TXINFO_TXTP_EN_C_M 0x20000000
#define TX_N_PACKET_EN_C 0x45B4
#define TX_N_PACKET_EN_C_M 0x40000000
#define TX_CONTINUOUS_C 0x45B4
#define TX_CONTINUOUS_C_M 0x80000000
#define TX_EN_C 0x45B8
#define TX_EN_C_M 0x1
#define TXCOMCT_BEAM_CHANGE_EN_C 0x45B8
#define TXCOMCT_BEAM_CHANGE_EN_C_M 0x2
#define TXCOMCT_DOPPLER_EN_C 0x45B8
#define TXCOMCT_DOPPLER_EN_C_M 0x4
#define TXCOMCT_FB_MUMIMO_EN_C 0x45B8
#define TXCOMCT_FB_MUMIMO_EN_C_M 0x8
#define TXCOMCT_FEEDBACK_STATUS_C 0x45B8
#define TXCOMCT_FEEDBACK_STATUS_C_M 0x10
#define TXCOMCT_HE_SIGB_DCM_EN_C 0x45B8
#define TXCOMCT_HE_SIGB_DCM_EN_C_M 0x20
#define TXCOMCT_MIDAMBLE_MODE_C 0x45B8
#define TXCOMCT_MIDAMBLE_MODE_C_M 0x40
#define TXCOMCT_MUMIMO_LTF_MODE_EN_C 0x45B8
#define TXCOMCT_MUMIMO_LTF_MODE_EN_C_M 0x80
#define TXCOMCT_NDP_C 0x45B8
#define TXCOMCT_NDP_C_M 0x100
#define TXCOMCT_STBC_EN_C 0x45B8
#define TXCOMCT_STBC_EN_C_M 0x200
#define TXINFO_ANT_SEL_A_C 0x45B8
#define TXINFO_ANT_SEL_A_C_M 0x400
#define TXINFO_ANT_SEL_B_C 0x45B8
#define TXINFO_ANT_SEL_B_C_M 0x800
#define TXINFO_ANT_SEL_C_C 0x45B8
#define TXINFO_ANT_SEL_C_C_M 0x1000
#define TXINFO_ANT_SEL_D_C 0x45B8
#define TXINFO_ANT_SEL_D_C_M 0x2000
#define TXINFO_CCA_PW_TH_EN_C 0x45B8
#define TXINFO_CCA_PW_TH_EN_C_M 0x4000
#define TXINFO_CFIR_BY_RATE_OFF_C 0x45B8
#define TXINFO_CFIR_BY_RATE_OFF_C_M 0x8000
#define TXINFO_DPD_BY_RATE_OFF_C 0x45B8
#define TXINFO_DPD_BY_RATE_OFF_C_M 0x10000
#define TXINFO_RF_FIXED_GAIN_EN_C 0x45B8
#define TXINFO_RF_FIXED_GAIN_EN_C_M 0x20000
#define TXINFO_UL_CQI_RPT_TRI_C 0x45B8
#define TXINFO_UL_CQI_RPT_TRI_C_M 0x40000
#define TXTIMCT_LDPC_EXTR_C 0x45B8
#define TXTIMCT_LDPC_EXTR_C_M 0x80000
#define TXUSRCT0_DCM_EN_C 0x45B8
#define TXUSRCT0_DCM_EN_C_M 0x100000
#define TXUSRCT0_FEC_TYPE_C 0x45B8
#define TXUSRCT0_FEC_TYPE_C_M 0x200000
#define TXUSRCT0_TXBF_EN_C 0x45B8
#define TXUSRCT0_TXBF_EN_C_M 0x400000
#define TXUSRCT1_DCM_EN_C 0x45B8
#define TXUSRCT1_DCM_EN_C_M 0x800000
#define TXUSRCT1_FEC_TYPE_C 0x45B8
#define TXUSRCT1_FEC_TYPE_C_M 0x1000000
#define TXUSRCT1_TXBF_EN_C 0x45B8
#define TXUSRCT1_TXBF_EN_C_M 0x2000000
#define TXUSRCT2_DCM_EN_C 0x45B8
#define TXUSRCT2_DCM_EN_C_M 0x4000000
#define TXUSRCT2_FEC_TYPE_C 0x45B8
#define TXUSRCT2_FEC_TYPE_C_M 0x8000000
#define TXUSRCT2_TXBF_EN_C 0x45B8
#define TXUSRCT2_TXBF_EN_C_M 0x10000000
#define TXUSRCT3_DCM_EN_C 0x45B8
#define TXUSRCT3_DCM_EN_C_M 0x20000000
#define TXUSRCT3_FEC_TYPE_C 0x45B8
#define TXUSRCT3_FEC_TYPE_C_M 0x40000000
#define TXUSRCT3_TXBF_EN_C 0x45B8
#define TXUSRCT3_TXBF_EN_C_M 0x80000000
#define PCOEFF0_C 0x45BC
#define PCOEFF0_C_M 0xFFF
#define PCOEFF1_C 0x45BC
#define PCOEFF1_C_M 0xFFF000
#define NORM_FCTR_C 0x45BC
#define NORM_FCTR_C_M 0x3F000000
#define DELAY_SAMPLE0_C 0x45BC
#define DELAY_SAMPLE0_C_M 0xC0000000
#define PCOEFF10_C 0x45C0
#define PCOEFF10_C_M 0xFFF
#define PCOEFF11_C 0x45C0
#define PCOEFF11_C_M 0xFFF000
#define DELAY_SAMPLE1_C 0x45C0
#define DELAY_SAMPLE1_C_M 0x3000000
#define DELAY_SAMPLE2_C 0x45C0
#define DELAY_SAMPLE2_C_M 0xC000000
#define DELAY_SAMPLE3_C 0x45C0
#define DELAY_SAMPLE3_C_M 0x30000000
#define TXPSF_SCALE_OPT_C 0x45C0
#define TXPSF_SCALE_OPT_C_M 0xC0000000
#define PCOEFF12_C 0x45C4
#define PCOEFF12_C_M 0xFFF
#define PCOEFF13_C 0x45C4
#define PCOEFF13_C_M 0xFFF000
#define PCOEFF14_C 0x45C8
#define PCOEFF14_C_M 0xFFF
#define PCOEFF15_C 0x45C8
#define PCOEFF15_C_M 0xFFF000
#define PCOEFF2_C 0x45CC
#define PCOEFF2_C_M 0xFFF
#define PCOEFF3_C 0x45CC
#define PCOEFF3_C_M 0xFFF000
#define PCOEFF4_C 0x45D0
#define PCOEFF4_C_M 0xFFF
#define PCOEFF5_C 0x45D0
#define PCOEFF5_C_M 0xFFF000
#define PCOEFF6_C 0x45D4
#define PCOEFF6_C_M 0xFFF
#define PCOEFF7_C 0x45D4
#define PCOEFF7_C_M 0xFFF000
#define PCOEFF8_C 0x45D8
#define PCOEFF8_C_M 0xFFF
#define PCOEFF9_C 0x45D8
#define PCOEFF9_C_M 0xFFF000
#define PATH0_R_A_G_ELNA0_C 0x45DC
#define PATH0_R_A_G_ELNA0_C_M 0xFF
#define PATH0_R_A_G_ELNA1_C 0x45DC
#define PATH0_R_A_G_ELNA1_C_M 0xFF00
#define PATH0_R_A_G_LNA0_C 0x45DC
#define PATH0_R_A_G_LNA0_C_M 0xFF0000
#define PATH0_R_A_G_LNA1_C 0x45DC
#define PATH0_R_A_G_LNA1_C_M 0xFF000000
#define ANTWGT_HIGH_PIN_TH_C 0x45E0
#define ANTWGT_HIGH_PIN_TH_C_M 0xFF
#define CCK_RSSI_OFST_C 0x45E0
#define CCK_RSSI_OFST_C_M 0xFF00
#define NULL_CONNECT_PIN_TH_C 0x45E0
#define NULL_CONNECT_PIN_TH_C_M 0xFF0000
#define GAIN_DIFF_TH_0_C 0x45E0
#define GAIN_DIFF_TH_0_C_M 0x1F000000
#define ANTWGT_MAX_TOTAL_THRESH_C 0x45E0
#define ANTWGT_MAX_TOTAL_THRESH_C_M 0x60000000
#define ANTWGT_ENABLE_C 0x45E0
#define ANTWGT_ENABLE_C_M 0x80000000
#define GAIN_DIFF_TH_1_C 0x45E4
#define GAIN_DIFF_TH_1_C_M 0x1F
#define GAIN_DIFF_TH_2_C 0x45E4
#define GAIN_DIFF_TH_2_C_M 0x3E0
#define GAIN_DIFF_TH_3_C 0x45E4
#define GAIN_DIFF_TH_3_C_M 0x7C00
#define GAIN_DIFF_TH_4_C 0x45E4
#define GAIN_DIFF_TH_4_C_M 0xF8000
#define GAIN_DIFF_TH_5_C 0x45E4
#define GAIN_DIFF_TH_5_C_M 0x1F00000
#define GAIN_DIFF_TH_6_C 0x45E4
#define GAIN_DIFF_TH_6_C_M 0x3E000000
#define FORCE_EQUAL_WGT_C 0x45E4
#define FORCE_EQUAL_WGT_C_M 0x40000000
#define HW_ANTWGT_EN_C 0x45E4
#define HW_ANTWGT_EN_C_M 0x80000000
#define GAIN_DIFF_TH_7_C 0x45E8
#define GAIN_DIFF_TH_7_C_M 0x1F
#define GAIN_DIFF_TH_8_C 0x45E8
#define GAIN_DIFF_TH_8_C_M 0x3E0
#define ANTWGT_PEAK_RATIO_THRESH_OPT_C 0x45E8
#define ANTWGT_PEAK_RATIO_THRESH_OPT_C_M 0x3C00
#define NULL_CONNECT_CHK_ENABLE_C 0x45E8
#define NULL_CONNECT_CHK_ENABLE_C_M 0x4000
#define ANT_PW_SAVE_RSSI_TH_C 0x45F4
#define ANT_PW_SAVE_RSSI_TH_C_M 0xFF
#define ANT_PW_SAVE_EN_C 0x45F4
#define ANT_PW_SAVE_EN_C_M 0x100
#define EDCCA_ENERGY_TH_C 0x4604
#define EDCCA_ENERGY_TH_C_M 0xFF
#define EDCCA_OFST_C 0x4604
#define EDCCA_OFST_C_M 0x1F00
#define EDCCA_FORCE_PATH_C 0x4604
#define EDCCA_FORCE_PATH_C_M 0x6000
#define EDCCA_PERIOD_C 0x4604
#define EDCCA_PERIOD_C_M 0x18000
#define EDCCA_VLD_TH_C 0x4604
#define EDCCA_VLD_TH_C_M 0x60000
#define EDCCA_EN_C 0x4604
#define EDCCA_EN_C_M 0x80000
#define EDCCA_FORCE_PATH_EN_C 0x4604
#define EDCCA_FORCE_PATH_EN_C_M 0x100000
#define EDCCA_WGTSEL_EN_C 0x4604
#define EDCCA_WGTSEL_EN_C_M 0x200000
#define RAKE_EN_C 0x4628
#define RAKE_EN_C_M 0x1
#define DC_WIN_EN_C 0x462C
#define DC_WIN_EN_C_M 0x1
#define FTM_1ST_SPA_C 0x4638
#define FTM_1ST_SPA_C_M 0xF
#define FTM_ALPHA_RATIO_C 0x4638
#define FTM_ALPHA_RATIO_C_M 0xF0
#define FTM_SEARCH_MP_C 0x4638
#define FTM_SEARCH_MP_C_M 0xF00
#define FTM_SIR_C 0x4638
#define FTM_SIR_C_M 0x7000
#define FTM_L_C 0x4638
#define FTM_L_C_M 0xC0000
#define FTM_N_PRO_C 0x4638
#define FTM_N_PRO_C_M 0x300000
#define FTM_1ST_MODE_C 0x4638
#define FTM_1ST_MODE_C_M 0x800000
#define FTM_MASK_C 0x4638
#define FTM_MASK_C_M 0x1000000
#define FTM_SEARCH_RANGE_20_C 0x4638
#define FTM_SEARCH_RANGE_20_C_M 0x2000000
#define FTM_SEARCH_RANGE_40_C 0x4638
#define FTM_SEARCH_RANGE_40_C_M 0x4000000
#define FTM_SEARCH_RANGE_80_C 0x4638
#define FTM_SEARCH_RANGE_80_C_M 0x8000000
#define PATH0_R_ACI_DET_BKP1_C 0x463C
#define PATH0_R_ACI_DET_BKP1_C_M 0xFFFFFFFF
#define PATH0_R_ACI_DET_BKP2_C 0x4640
#define PATH0_R_ACI_DET_BKP2_C_M 0xFFFFFFFF
#define PATH0_R_ACI_TH_DB_BW20_C 0x4644
#define PATH0_R_ACI_TH_DB_BW20_C_M 0xFF
#define PATH0_R_ACI_TH_DB_BW40_C 0x4644
#define PATH0_R_ACI_TH_DB_BW40_C_M 0xFF00
#define PATH0_R_ACI_TH_DB_BW80_C 0x4644
#define PATH0_R_ACI_TH_DB_BW80_C_M 0xFF0000
#define PATH0_R_LARGE_ACI_ACT_TH_BW20_C 0x4644
#define PATH0_R_LARGE_ACI_ACT_TH_BW20_C_M 0xFF000000
#define PATH0_R_LARGE_ACI_ACT_TH_BW40_C 0x4648
#define PATH0_R_LARGE_ACI_ACT_TH_BW40_C_M 0xFF
#define PATH0_R_LARGE_ACI_ACT_TH_BW80_C 0x4648
#define PATH0_R_LARGE_ACI_ACT_TH_BW80_C_M 0xFF00
#define PATH0_R_NORMAL_ACI_ACT_TH_BW20_C 0x4648
#define PATH0_R_NORMAL_ACI_ACT_TH_BW20_C_M 0xFF0000
#define PATH0_R_NORMAL_ACI_ACT_TH_BW40_C 0x4648
#define PATH0_R_NORMAL_ACI_ACT_TH_BW40_C_M 0xFF000000
#define PATH0_R_NORMAL_ACI_ACT_TH_BW80_C 0x464C
#define PATH0_R_NORMAL_ACI_ACT_TH_BW80_C_M 0xFF
#define PATH0_R_LARGE_ACI_DB_C 0x464C
#define PATH0_R_LARGE_ACI_DB_C_M 0x7F00
#define PATH0_R_ACI_NRBW_OFST_BW20_C 0x464C
#define PATH0_R_ACI_NRBW_OFST_BW20_C_M 0x78000
#define PATH0_R_ACI_NRBW_OFST_BW40_C 0x464C
#define PATH0_R_ACI_NRBW_OFST_BW40_C_M 0x780000
#define PATH0_R_ACI_NRBW_OFST_BW80_C 0x464C
#define PATH0_R_ACI_NRBW_OFST_BW80_C_M 0x7800000
#define PATH0_R_ACI_HIT_CNT_TH_C 0x464C
#define PATH0_R_ACI_HIT_CNT_TH_C_M 0x38000000
#define PATH0_R_ACI_NRBW_OFST_EN_C 0x464C
#define PATH0_R_ACI_NRBW_OFST_EN_C_M 0x40000000
#define PATH0_R_BYPASS_RFGC_EN_C 0x464C
#define PATH0_R_BYPASS_RFGC_EN_C_M 0x80000000
#define PATH0_R_ADC_DC_OFST_RXLOW_IM_C 0x4650
#define PATH0_R_ADC_DC_OFST_RXLOW_IM_C_M 0x3FFF
#define PATH0_R_ADC_DC_OFST_RXLOW_RE_C 0x4650
#define PATH0_R_ADC_DC_OFST_RXLOW_RE_C_M 0xFFFC000
#define PATH0_R_DC_COMP_EN_C 0x4650
#define PATH0_R_DC_COMP_EN_C_M 0x10000000
#define PATH0_R_ADC_DC_OFST_RXMID_IM_C 0x4654
#define PATH0_R_ADC_DC_OFST_RXMID_IM_C_M 0x3FFF
#define PATH0_R_ADC_DC_OFST_RXMID_RE_C 0x4654
#define PATH0_R_ADC_DC_OFST_RXMID_RE_C_M 0xFFFC000
#define PATH0_R_DC_OFST_IM_C 0x4658
#define PATH0_R_DC_OFST_IM_C_M 0x3FFF
#define PATH0_R_DC_OFST_RE_C 0x4658
#define PATH0_R_DC_OFST_RE_C_M 0xFFFC000
#define PATH0_R_RXTH1_C 0x465C
#define PATH0_R_RXTH1_C_M 0x1F
#define PATH0_R_RXTH2_C 0x465C
#define PATH0_R_RXTH2_C_M 0x3E0
#define PATH0_R_A_G_LNA2_C 0x4660
#define PATH0_R_A_G_LNA2_C_M 0xFF
#define PATH0_R_A_G_LNA3_C 0x4660
#define PATH0_R_A_G_LNA3_C_M 0xFF00
#define PATH0_R_A_G_LNA4_C 0x4660
#define PATH0_R_A_G_LNA4_C_M 0xFF0000
#define PATH0_R_A_G_LNA5_C 0x4660
#define PATH0_R_A_G_LNA5_C_M 0xFF000000
#define PATH0_R_A_G_LNA6_C 0x4664
#define PATH0_R_A_G_LNA6_C_M 0xFF
#define PATH0_R_A_G_RX0_C 0x4664
#define PATH0_R_A_G_RX0_C_M 0xFF00
#define PATH0_R_A_G_TIA0_C 0x4664
#define PATH0_R_A_G_TIA0_C_M 0xFF0000
#define PATH0_R_A_G_TIA1_C 0x4664
#define PATH0_R_A_G_TIA1_C_M 0xFF000000
#define PATH0_R_A_LNA0_OP1DB_C 0x4668
#define PATH0_R_A_LNA0_OP1DB_C_M 0xFF
#define PATH0_R_A_LNA1_OP1DB_C 0x4668
#define PATH0_R_A_LNA1_OP1DB_C_M 0xFF00
#define PATH0_R_A_LNA2_OP1DB_C 0x4668
#define PATH0_R_A_LNA2_OP1DB_C_M 0xFF0000
#define PATH0_R_A_LNA3_OP1DB_C 0x4668
#define PATH0_R_A_LNA3_OP1DB_C_M 0xFF000000
#define PATH0_R_A_LNA4_OP1DB_C 0x466C
#define PATH0_R_A_LNA4_OP1DB_C_M 0xFF
#define PATH0_R_A_LNA5_OP1DB_C 0x466C
#define PATH0_R_A_LNA5_OP1DB_C_M 0xFF00
#define PATH0_R_A_LNA6_OP1DB_C 0x466C
#define PATH0_R_A_LNA6_OP1DB_C_M 0xFF0000
#define PATH0_R_A_RXOP1DB_C 0x466C
#define PATH0_R_A_RXOP1DB_C_M 0xFF000000
#define PATH0_R_A_TIA0_LNA0_OP1DB_C 0x4670
#define PATH0_R_A_TIA0_LNA0_OP1DB_C_M 0xFF
#define PATH0_R_A_TIA0_LNA1_OP1DB_C 0x4670
#define PATH0_R_A_TIA0_LNA1_OP1DB_C_M 0xFF00
#define PATH0_R_A_TIA0_LNA2_OP1DB_C 0x4670
#define PATH0_R_A_TIA0_LNA2_OP1DB_C_M 0xFF0000
#define PATH0_R_A_TIA0_LNA3_OP1DB_C 0x4670
#define PATH0_R_A_TIA0_LNA3_OP1DB_C_M 0xFF000000
#define PATH0_R_A_TIA0_LNA4_OP1DB_C 0x4674
#define PATH0_R_A_TIA0_LNA4_OP1DB_C_M 0xFF
#define PATH0_R_A_TIA0_LNA5_OP1DB_C 0x4674
#define PATH0_R_A_TIA0_LNA5_OP1DB_C_M 0xFF00
#define PATH0_R_A_TIA0_LNA6_OP1DB_C 0x4674
#define PATH0_R_A_TIA0_LNA6_OP1DB_C_M 0xFF0000
#define PATH0_R_A_TIA1_LNA6_OP1DB_C 0x4674
#define PATH0_R_A_TIA1_LNA6_OP1DB_C_M 0xFF000000
#define PATH0_R_G_G_ELNA0_C 0x4678
#define PATH0_R_G_G_ELNA0_C_M 0xFF
#define PATH0_R_G_G_ELNA1_C 0x4678
#define PATH0_R_G_G_ELNA1_C_M 0xFF00
#define PATH0_R_G_G_LNA0_C 0x4678
#define PATH0_R_G_G_LNA0_C_M 0xFF0000
#define PATH0_R_G_G_LNA1_C 0x4678
#define PATH0_R_G_G_LNA1_C_M 0xFF000000
#define PATH0_R_G_G_LNA2_C 0x467C
#define PATH0_R_G_G_LNA2_C_M 0xFF
#define PATH0_R_G_G_LNA3_C 0x467C
#define PATH0_R_G_G_LNA3_C_M 0xFF00
#define PATH0_R_G_G_LNA4_C 0x467C
#define PATH0_R_G_G_LNA4_C_M 0xFF0000
#define PATH0_R_G_G_LNA5_C 0x467C
#define PATH0_R_G_G_LNA5_C_M 0xFF000000
#define PATH0_R_G_G_LNA6_C 0x4680
#define PATH0_R_G_G_LNA6_C_M 0xFF
#define PATH0_R_G_G_RX0_C 0x4680
#define PATH0_R_G_G_RX0_C_M 0xFF00
#define PATH0_R_G_G_TIA0_C 0x4680
#define PATH0_R_G_G_TIA0_C_M 0xFF0000
#define PATH0_R_G_G_TIA1_C 0x4680
#define PATH0_R_G_G_TIA1_C_M 0xFF000000
#define PATH0_R_G_LGC_DAGC_C 0x4684
#define PATH0_R_G_LGC_DAGC_C_M 0xFF
#define PATH0_R_G_LNA0_OP1DB_C 0x4684
#define PATH0_R_G_LNA0_OP1DB_C_M 0xFF00
#define PATH0_R_G_LNA1_OP1DB_C 0x4684
#define PATH0_R_G_LNA1_OP1DB_C_M 0xFF0000
#define PATH0_R_G_LNA2_OP1DB_C 0x4684
#define PATH0_R_G_LNA2_OP1DB_C_M 0xFF000000
#define PATH0_R_G_LNA3_OP1DB_C 0x4688
#define PATH0_R_G_LNA3_OP1DB_C_M 0xFF
#define PATH0_R_G_LNA4_OP1DB_C 0x4688
#define PATH0_R_G_LNA4_OP1DB_C_M 0xFF00
#define PATH0_R_G_LNA5_OP1DB_C 0x4688
#define PATH0_R_G_LNA5_OP1DB_C_M 0xFF0000
#define PATH0_R_G_LNA6_OP1DB_C 0x4688
#define PATH0_R_G_LNA6_OP1DB_C_M 0xFF000000
#define PATH0_R_G_NLGC_DAGC_C 0x468C
#define PATH0_R_G_NLGC_DAGC_C_M 0xFF
#define PATH0_R_G_RXOP1DB_C 0x468C
#define PATH0_R_G_RXOP1DB_C_M 0xFF00
#define PATH0_R_G_TIA0_LNA0_OP1DB_C 0x468C
#define PATH0_R_G_TIA0_LNA0_OP1DB_C_M 0xFF0000
#define PATH0_R_G_TIA0_LNA1_OP1DB_C 0x468C
#define PATH0_R_G_TIA0_LNA1_OP1DB_C_M 0xFF000000
#define PATH0_R_G_TIA0_LNA2_OP1DB_C 0x4690
#define PATH0_R_G_TIA0_LNA2_OP1DB_C_M 0xFF
#define PATH0_R_G_TIA0_LNA3_OP1DB_C 0x4690
#define PATH0_R_G_TIA0_LNA3_OP1DB_C_M 0xFF00
#define PATH0_R_G_TIA0_LNA4_OP1DB_C 0x4690
#define PATH0_R_G_TIA0_LNA4_OP1DB_C_M 0xFF0000
#define PATH0_R_G_TIA0_LNA5_OP1DB_C 0x4690
#define PATH0_R_G_TIA0_LNA5_OP1DB_C_M 0xFF000000
#define PATH0_R_G_TIA0_LNA6_OP1DB_C 0x4694
#define PATH0_R_G_TIA0_LNA6_OP1DB_C_M 0xFF
#define PATH0_R_G_TIA1_LNA6_OP1DB_C 0x4694
#define PATH0_R_G_TIA1_LNA6_OP1DB_C_M 0xFF00
#define PATH0_R_G_OFST_C 0x4694
#define PATH0_R_G_OFST_C_M 0xFF0000
#define PATH0_R_IBADC_SAT_TH_C 0x4694
#define PATH0_R_IBADC_SAT_TH_C_M 0xFF000000
#define PATH0_R_IBADC_UNDER_TH_C 0x4698
#define PATH0_R_IBADC_UNDER_TH_C_M 0xFF
#define PATH0_R_WBADC_SAT_TH_C 0x4698
#define PATH0_R_WBADC_SAT_TH_C_M 0xFF00
#define PATH0_R_WBADC_SAT_TH_ANTWGT_C 0x4698
#define PATH0_R_WBADC_SAT_TH_ANTWGT_C_M 0xFF0000
#define PATH0_R_WBADC_UNDER_TH_C 0x4698
#define PATH0_R_WBADC_UNDER_TH_C_M 0xFF000000
#define PATH0_R_P_PEAK_IBADC_DBM_C 0x469C
#define PATH0_R_P_PEAK_IBADC_DBM_C_M 0x7F
#define PATH0_R_P_PEAK_WBADC_DBM_C 0x469C
#define PATH0_R_P_PEAK_WBADC_DBM_C_M 0x3F80
#define PATH0_R_ACI_NRBW_TH_C 0x469C
#define PATH0_R_ACI_NRBW_TH_C_M 0xFC000
#define PATH0_R_BACKOFF_BMODE_C 0x469C
#define PATH0_R_BACKOFF_BMODE_C_M 0x3F00000
#define PATH0_R_BACKOFF_IBADC_C 0x469C
#define PATH0_R_BACKOFF_IBADC_C_M 0xFC000000
#define PATH0_R_BACKOFF_LNA_C 0x46A0
#define PATH0_R_BACKOFF_LNA_C_M 0x3F
#define PATH0_R_BACKOFF_TIA_C 0x46A0
#define PATH0_R_BACKOFF_TIA_C_M 0xFC0
#define PATH0_R_BACKOFF_WBADC_C 0x46A0
#define PATH0_R_BACKOFF_WBADC_C_M 0x3F000
#define PATH0_R_G_IBADC_IN_C 0x46A0
#define PATH0_R_G_IBADC_IN_C_M 0xFC0000
#define PATH0_R_A_GS_SAT_IDX_RX_C 0x46A0
#define PATH0_R_A_GS_SAT_IDX_RX_C_M 0x1F000000
#define PATH0_R_A_WB_GIDX_00_LNA_TIA_C 0x46A0
#define PATH0_R_A_WB_GIDX_00_LNA_TIA_C_M 0xE0000000
#define PATH0_R_A_GS_UND_IDX_RX_C 0x46A4
#define PATH0_R_A_GS_UND_IDX_RX_C_M 0x1F
#define PATH0_R_G_GS_SAT_IDX_RX_C 0x46A4
#define PATH0_R_G_GS_SAT_IDX_RX_C_M 0x3E0
#define PATH0_R_G_GS_UND_IDX_RX_C 0x46A4
#define PATH0_R_G_GS_UND_IDX_RX_C_M 0x7C00
#define PATH0_R_DLY_DCCL_C 0x46A4
#define PATH0_R_DLY_DCCL_C_M 0x1F00000
#define PATH0_R_DLY_DFE_C 0x46A4
#define PATH0_R_DLY_DFE_C_M 0x3E000000
#define PATH0_R_G_MIXER_C 0x46A4
#define PATH0_R_G_MIXER_C_M 0xC0000000
#define PATH0_R_DLY_PRIM_C 0x46A8
#define PATH0_R_DLY_PRIM_C_M 0x1F
#define PATH0_R_DLY_SYNC_C 0x46A8
#define PATH0_R_DLY_SYNC_C_M 0x3E0
#define PATH0_R_RXIDX_INIT_C 0x46A8
#define PATH0_R_RXIDX_INIT_C_M 0x7C00
#define PATH0_R_A_GS_SAT_IDX_H_C 0x46A8
#define PATH0_R_A_GS_SAT_IDX_H_C_M 0x78000
#define PATH0_R_A_GS_SAT_IDX_L_C 0x46A8
#define PATH0_R_A_GS_SAT_IDX_L_C_M 0x780000
#define PATH0_R_A_GS_SAT_IDX_PP1_C 0x46A8
#define PATH0_R_A_GS_SAT_IDX_PP1_C_M 0x7800000
#define PATH0_R_A_GS_SAT_IDX_PP2_C 0x46A8
#define PATH0_R_A_GS_SAT_IDX_PP2_C_M 0x78000000
#define PATH0_R_1RCCA_PRE_PD_MODE_C 0x46A8
#define PATH0_R_1RCCA_PRE_PD_MODE_C_M 0x80000000
#define PATH0_R_A_GS_SAT_TH_H_C 0x46AC
#define PATH0_R_A_GS_SAT_TH_H_C_M 0xF
#define PATH0_R_A_GS_SAT_TH_L_C 0x46AC
#define PATH0_R_A_GS_SAT_TH_L_C_M 0xF0
#define PATH0_R_A_GS_UND_IDX_C 0x46AC
#define PATH0_R_A_GS_UND_IDX_C_M 0xF00
#define PATH0_R_A_GS_UND_IDX_PP1_C 0x46AC
#define PATH0_R_A_GS_UND_IDX_PP1_C_M 0xF000
#define PATH0_R_A_GS_UND_IDX_PP2_C 0x46AC
#define PATH0_R_A_GS_UND_IDX_PP2_C_M 0xF0000
#define PATH0_R_A_GS_UND_TH_H_C 0x46AC
#define PATH0_R_A_GS_UND_TH_H_C_M 0xF00000
#define PATH0_R_A_GS_UND_TH_L_C 0x46AC
#define PATH0_R_A_GS_UND_TH_L_C_M 0xF000000
#define PATH0_R_GC1_TIME_C 0x46AC
#define PATH0_R_GC1_TIME_C_M 0xF0000000
#define PATH0_R_GC1_TIME_NLGC_C 0x46B0
#define PATH0_R_GC1_TIME_NLGC_C_M 0xF
#define PATH0_R_GC2_TIME_C 0x46B0
#define PATH0_R_GC2_TIME_C_M 0xF0
#define PATH0_R_GC2_TIME_NLGC_C 0x46B0
#define PATH0_R_GC2_TIME_NLGC_C_M 0xF00
#define PATH0_R_GC3_TIME_C 0x46B0
#define PATH0_R_GC3_TIME_C_M 0xF000
#define PATH0_R_GC4_TIME_C 0x46B0
#define PATH0_R_GC4_TIME_C_M 0xF0000
#define PATH0_R_GC5_TIME_C 0x46B0
#define PATH0_R_GC5_TIME_C_M 0xF00000
#define PATH0_R_GC_TIME_LESS_80M_C 0x46B0
#define PATH0_R_GC_TIME_LESS_80M_C_M 0xF000000
#define PATH0_R_GC_TIME_LESS_NLINEAR_C 0x46B0
#define PATH0_R_GC_TIME_LESS_NLINEAR_C_M 0xF0000000
#define PATH0_R_G_GS_SAT_IDX_H_C 0x46B4
#define PATH0_R_G_GS_SAT_IDX_H_C_M 0xF
#define PATH0_R_G_GS_SAT_IDX_L_C 0x46B4
#define PATH0_R_G_GS_SAT_IDX_L_C_M 0xF0
#define PATH0_R_G_GS_SAT_IDX_PP1_C 0x46B4
#define PATH0_R_G_GS_SAT_IDX_PP1_C_M 0xF00
#define PATH0_R_G_GS_SAT_IDX_PP2_C 0x46B4
#define PATH0_R_G_GS_SAT_IDX_PP2_C_M 0xF000
#define PATH0_R_G_GS_SAT_TH_H_C 0x46B4
#define PATH0_R_G_GS_SAT_TH_H_C_M 0xF0000
#define PATH0_R_G_GS_SAT_TH_L_C 0x46B4
#define PATH0_R_G_GS_SAT_TH_L_C_M 0xF00000
#define PATH0_R_G_GS_UND_IDX_C 0x46B4
#define PATH0_R_G_GS_UND_IDX_C_M 0xF000000
#define PATH0_R_G_GS_UND_IDX_PP1_C 0x46B4
#define PATH0_R_G_GS_UND_IDX_PP1_C_M 0xF0000000
#define PATH0_R_G_GS_UND_IDX_PP2_C 0x46B8
#define PATH0_R_G_GS_UND_IDX_PP2_C_M 0xF
#define PATH0_R_G_GS_UND_TH_H_C 0x46B8
#define PATH0_R_G_GS_UND_TH_H_C_M 0xF0
#define PATH0_R_G_GS_UND_TH_L_C 0x46B8
#define PATH0_R_G_GS_UND_TH_L_C_M 0xF00
#define PATH0_R_ACI_NRBW_RATIO_C 0x46B8
#define PATH0_R_ACI_NRBW_RATIO_C_M 0xF000
#define PATH0_R_AGC_RESTART_TH_IB_C 0x46B8
#define PATH0_R_AGC_RESTART_TH_IB_C_M 0xF0000
#define PATH0_R_AGC_RESTART_TH_WB_C 0x46B8
#define PATH0_R_AGC_RESTART_TH_WB_C_M 0xF00000
#define PATH0_R_DCCL_ALPHA_80_C 0x46B8
#define PATH0_R_DCCL_ALPHA_80_C_M 0xF000000
#define PATH0_R_DCCL_ALPHA_N80_C 0x46B8
#define PATH0_R_DCCL_ALPHA_N80_C_M 0xF0000000
#define PATH0_R_LGC_FREEZE_TH_H_C 0x46BC
#define PATH0_R_LGC_FREEZE_TH_H_C_M 0xF
#define PATH0_R_LGC_FREEZE_TH_L_C 0x46BC
#define PATH0_R_LGC_FREEZE_TH_L_C_M 0xF0
#define PATH0_R_NLGC_FREEZE_TH_H_C 0x46BC
#define PATH0_R_NLGC_FREEZE_TH_H_C_M 0xF00
#define PATH0_R_NLGC_FREEZE_TH_L_C 0x46BC
#define PATH0_R_NLGC_FREEZE_TH_L_C_M 0xF000
#define PATH0_R_WB_GAIN_IDX_INIT_C 0x46BC
#define PATH0_R_WB_GAIN_IDX_INIT_C_M 0xF0000
#define PATH0_R_A_WB_GIDX_01_LNA_TIA_C 0x46BC
#define PATH0_R_A_WB_GIDX_01_LNA_TIA_C_M 0x7000000
#define PATH0_R_A_WB_GIDX_02_LNA_TIA_C 0x46BC
#define PATH0_R_A_WB_GIDX_02_LNA_TIA_C_M 0x38000000
#define PATH0_R_G_WBADC_IN_C 0x46BC
#define PATH0_R_G_WBADC_IN_C_M 0xC0000000
#define PATH0_R_DCCL_SYNC_BKP1_C 0x46C0
#define PATH0_R_DCCL_SYNC_BKP1_C_M 0xFFFFFFFF
#define PATH0_R_DCCL_SYNC_BKP2_C 0x46C4
#define PATH0_R_DCCL_SYNC_BKP2_C_M 0xFFFFFFFF
#define PATH0_R_ALPHA_END_IDX_C 0x46C8
#define PATH0_R_ALPHA_END_IDX_C_M 0xF
#define PATH0_R_ALPHA_START_IDX_C 0x46C8
#define PATH0_R_ALPHA_START_IDX_C_M 0xF0
#define PATH0_R_TIME_CONST_IDX_C 0x46C8
#define PATH0_R_TIME_CONST_IDX_C_M 0x700
#define PATH0_R_RXFIR_BKP_C 0x46CC
#define PATH0_R_RXFIR_BKP_C_M 0xFFFFFFFF
#define PATH0_R_FORCE_FIR_TYPE_C 0x46D0
#define PATH0_R_FORCE_FIR_TYPE_C_M 0x3
#define PATH0_R_CCK_CCA_SHRINK_EN_C 0x46D0
#define PATH0_R_CCK_CCA_SHRINK_EN_C_M 0x4
#define PATH0_P20_R_L1_CFO_CMP_EN_C 0x46D4
#define PATH0_P20_R_L1_CFO_CMP_EN_C_M 0x1
#define PATH0_S20_R_L1_CFO_CMP_EN_C 0x46D8
#define PATH0_S20_R_L1_CFO_CMP_EN_C_M 0x1
#define PATH0_R_NBI_NOTCH_BKP1_C 0x46DC
#define PATH0_R_NBI_NOTCH_BKP1_C_M 0xFFFFFFFF
#define PATH0_R_NBI_NOTCH_BKP2_C 0x46E0
#define PATH0_R_NBI_NOTCH_BKP2_C_M 0xFFFFFFFF
#define PATH0_R_NBI_IDX_C 0x46E4
#define PATH0_R_NBI_IDX_C_M 0xFF
#define PATH0_R_CORNER_IDX_C 0x46E4
#define PATH0_R_CORNER_IDX_C_M 0x300
#define PATH0_R_NBI_FRAC_IDX_C 0x46E4
#define PATH0_R_NBI_FRAC_IDX_C_M 0xC00
#define PATH0_R_NBI_NOTCH_EN_C 0x46E4
#define PATH0_R_NBI_NOTCH_EN_C_M 0x1000
#define PATH0_P20_R_DAGC_EXTRA_SETTLING_TIME_C 0x46E8
#define PATH0_P20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
#define PATH0_P20_R_DAGC_SETTLING_TIME_C 0x46E8
#define PATH0_P20_R_DAGC_SETTLING_TIME_C_M 0x18
#define PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C 0x46E8
#define PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
#define PATH0_P20_R_PW_EST_SHORT_TIME_FAGC_C 0x46E8
#define PATH0_P20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
#define PATH0_P20_R_PW_EST_TIME_FAGC_C 0x46E8
#define PATH0_P20_R_PW_EST_TIME_FAGC_C_M 0x80
#define PATH0_P20_R_PW_EST_TIME_PAGC_C 0x46E8
#define PATH0_P20_R_PW_EST_TIME_PAGC_C_M 0x100
#define PATH0_P20_R_PW_EST_TIME_RFGC_C 0x46E8
#define PATH0_P20_R_PW_EST_TIME_RFGC_C_M 0x200
#define PATH0_P20_R_SDAGC_EN_C 0x46E8
#define PATH0_P20_R_SDAGC_EN_C_M 0x400
#define PATH0_S20_R_DAGC_EXTRA_SETTLING_TIME_C 0x46EC
#define PATH0_S20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
#define PATH0_S20_R_DAGC_SETTLING_TIME_C 0x46EC
#define PATH0_S20_R_DAGC_SETTLING_TIME_C_M 0x18
#define PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C 0x46EC
#define PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
#define PATH0_S20_R_PW_EST_SHORT_TIME_FAGC_C 0x46EC
#define PATH0_S20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
#define PATH0_S20_R_PW_EST_TIME_FAGC_C 0x46EC
#define PATH0_S20_R_PW_EST_TIME_FAGC_C_M 0x80
#define PATH0_S20_R_PW_EST_TIME_PAGC_C 0x46EC
#define PATH0_S20_R_PW_EST_TIME_PAGC_C_M 0x100
#define PATH0_S20_R_PW_EST_TIME_RFGC_C 0x46EC
#define PATH0_S20_R_PW_EST_TIME_RFGC_C_M 0x200
#define PATH0_S20_R_SDAGC_EN_C 0x46EC
#define PATH0_S20_R_SDAGC_EN_C_M 0x400
#define PATH0_R_5MDET_BKP1_C 0x46F0
#define PATH0_R_5MDET_BKP1_C_M 0xFFFFFFFF
#define PATH0_R_5MDET_BKP2_C 0x46F4
#define PATH0_R_5MDET_BKP2_C_M 0xFFFFFFFF
#define PATH0_R_5MDET_TH_DB_C 0x46F8
#define PATH0_R_5MDET_TH_DB_C_M 0x3F
#define PATH0_R_5MDET_MASK_SB0_C 0x46F8
#define PATH0_R_5MDET_MASK_SB0_C_M 0x40
#define PATH0_R_5MDET_MASK_SB1_C 0x46F8
#define PATH0_R_5MDET_MASK_SB1_C_M 0x80
#define PATH0_R_5MDET_MASK_SB2_C 0x46F8
#define PATH0_R_5MDET_MASK_SB2_C_M 0x100
#define PATH0_R_5MDET_MASK_SB3_C 0x46F8
#define PATH0_R_5MDET_MASK_SB3_C_M 0x200
#define PATH0_R_5MDET_MODE_C 0x46F8
#define PATH0_R_5MDET_MODE_C_M 0x400
#define PATH0_R_IIR_PW_AVG_EN_C 0x46F8
#define PATH0_R_IIR_PW_AVG_EN_C_M 0x800
#define PATH0_R_SBF5M_EN_C 0x46F8
#define PATH0_R_SBF5M_EN_C_M 0x1000
#define PATH1_R_ACI_DET_BKP1_C 0x46FC
#define PATH1_R_ACI_DET_BKP1_C_M 0xFFFFFFFF
#define PATH1_R_ACI_DET_BKP2_C 0x4700
#define PATH1_R_ACI_DET_BKP2_C_M 0xFFFFFFFF
#define PATH1_R_ACI_TH_DB_BW20_C 0x4704
#define PATH1_R_ACI_TH_DB_BW20_C_M 0xFF
#define PATH1_R_ACI_TH_DB_BW40_C 0x4704
#define PATH1_R_ACI_TH_DB_BW40_C_M 0xFF00
#define PATH1_R_ACI_TH_DB_BW80_C 0x4704
#define PATH1_R_ACI_TH_DB_BW80_C_M 0xFF0000
#define PATH1_R_LARGE_ACI_ACT_TH_BW20_C 0x4704
#define PATH1_R_LARGE_ACI_ACT_TH_BW20_C_M 0xFF000000
#define PATH1_R_LARGE_ACI_ACT_TH_BW40_C 0x4708
#define PATH1_R_LARGE_ACI_ACT_TH_BW40_C_M 0xFF
#define PATH1_R_LARGE_ACI_ACT_TH_BW80_C 0x4708
#define PATH1_R_LARGE_ACI_ACT_TH_BW80_C_M 0xFF00
#define PATH1_R_NORMAL_ACI_ACT_TH_BW20_C 0x4708
#define PATH1_R_NORMAL_ACI_ACT_TH_BW20_C_M 0xFF0000
#define PATH1_R_NORMAL_ACI_ACT_TH_BW40_C 0x4708
#define PATH1_R_NORMAL_ACI_ACT_TH_BW40_C_M 0xFF000000
#define PATH1_R_NORMAL_ACI_ACT_TH_BW80_C 0x470C
#define PATH1_R_NORMAL_ACI_ACT_TH_BW80_C_M 0xFF
#define PATH1_R_LARGE_ACI_DB_C 0x470C
#define PATH1_R_LARGE_ACI_DB_C_M 0x7F00
#define PATH1_R_ACI_NRBW_OFST_BW20_C 0x470C
#define PATH1_R_ACI_NRBW_OFST_BW20_C_M 0x78000
#define PATH1_R_ACI_NRBW_OFST_BW40_C 0x470C
#define PATH1_R_ACI_NRBW_OFST_BW40_C_M 0x780000
#define PATH1_R_ACI_NRBW_OFST_BW80_C 0x470C
#define PATH1_R_ACI_NRBW_OFST_BW80_C_M 0x7800000
#define PATH1_R_ACI_HIT_CNT_TH_C 0x470C
#define PATH1_R_ACI_HIT_CNT_TH_C_M 0x38000000
#define PATH1_R_ACI_NRBW_OFST_EN_C 0x470C
#define PATH1_R_ACI_NRBW_OFST_EN_C_M 0x40000000
#define PATH1_R_BYPASS_RFGC_EN_C 0x470C
#define PATH1_R_BYPASS_RFGC_EN_C_M 0x80000000
#define PATH1_R_ADC_DC_OFST_RXLOW_IM_C 0x4710
#define PATH1_R_ADC_DC_OFST_RXLOW_IM_C_M 0x3FFF
#define PATH1_R_ADC_DC_OFST_RXLOW_RE_C 0x4710
#define PATH1_R_ADC_DC_OFST_RXLOW_RE_C_M 0xFFFC000
#define PATH1_R_DC_COMP_EN_C 0x4710
#define PATH1_R_DC_COMP_EN_C_M 0x10000000
#define PATH1_R_ADC_DC_OFST_RXMID_IM_C 0x4714
#define PATH1_R_ADC_DC_OFST_RXMID_IM_C_M 0x3FFF
#define PATH1_R_ADC_DC_OFST_RXMID_RE_C 0x4714
#define PATH1_R_ADC_DC_OFST_RXMID_RE_C_M 0xFFFC000
#define PATH1_R_DC_OFST_IM_C 0x4718
#define PATH1_R_DC_OFST_IM_C_M 0x3FFF
#define PATH1_R_DC_OFST_RE_C 0x4718
#define PATH1_R_DC_OFST_RE_C_M 0xFFFC000
#define PATH1_R_RXTH1_C 0x471C
#define PATH1_R_RXTH1_C_M 0x1F
#define PATH1_R_RXTH2_C 0x471C
#define PATH1_R_RXTH2_C_M 0x3E0
#define PATH0_R_A_WB_GIDX_03_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_03_LNA_TIA_C_M 0x7
#define PATH0_R_A_WB_GIDX_04_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_04_LNA_TIA_C_M 0x38
#define PATH0_R_A_WB_GIDX_05_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_05_LNA_TIA_C_M 0x1C0
#define PATH0_R_A_WB_GIDX_06_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_06_LNA_TIA_C_M 0xE00
#define PATH0_R_A_WB_GIDX_07_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_07_LNA_TIA_C_M 0x7000
#define PATH0_R_A_WB_GIDX_08_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_08_LNA_TIA_C_M 0x38000
#define PATH0_R_A_WB_GIDX_09_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_09_LNA_TIA_C_M 0x1C0000
#define PATH0_R_A_WB_GIDX_10_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_10_LNA_TIA_C_M 0xE00000
#define PATH0_R_A_WB_GIDX_11_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_11_LNA_TIA_C_M 0x7000000
#define PATH0_R_A_WB_GIDX_12_LNA_TIA_C 0x4720
#define PATH0_R_A_WB_GIDX_12_LNA_TIA_C_M 0x38000000
#define PATH0_R_IBADC_PW_ALPHA_H_C 0x4720
#define PATH0_R_IBADC_PW_ALPHA_H_C_M 0xC0000000
#define PATH0_R_A_WB_GIDX_13_LNA_TIA_C 0x4724
#define PATH0_R_A_WB_GIDX_13_LNA_TIA_C_M 0x7
#define PATH0_R_A_WB_GIDX_14_LNA_TIA_C 0x4724
#define PATH0_R_A_WB_GIDX_14_LNA_TIA_C_M 0x38
#define PATH0_R_A_WB_GIDX_15_LNA_TIA_C 0x4724
#define PATH0_R_A_WB_GIDX_15_LNA_TIA_C_M 0x1C0
#define PATH0_R_G_WB_GIDX_00_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_00_LNA_TIA_C_M 0xE00
#define PATH0_R_G_WB_GIDX_01_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_01_LNA_TIA_C_M 0x7000
#define PATH0_R_G_WB_GIDX_02_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_02_LNA_TIA_C_M 0x38000
#define PATH0_R_G_WB_GIDX_03_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_03_LNA_TIA_C_M 0x1C0000
#define PATH0_R_G_WB_GIDX_04_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_04_LNA_TIA_C_M 0xE00000
#define PATH0_R_G_WB_GIDX_05_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_05_LNA_TIA_C_M 0x7000000
#define PATH0_R_G_WB_GIDX_06_LNA_TIA_C 0x4724
#define PATH0_R_G_WB_GIDX_06_LNA_TIA_C_M 0x38000000
#define PATH0_R_IBADC_PW_ALPHA_L_C 0x4724
#define PATH0_R_IBADC_PW_ALPHA_L_C_M 0xC0000000
#define PATH0_R_G_WB_GIDX_07_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_07_LNA_TIA_C_M 0x7
#define PATH0_R_G_WB_GIDX_08_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_08_LNA_TIA_C_M 0x38
#define PATH0_R_G_WB_GIDX_09_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_09_LNA_TIA_C_M 0x1C0
#define PATH0_R_G_WB_GIDX_10_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_10_LNA_TIA_C_M 0xE00
#define PATH0_R_G_WB_GIDX_11_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_11_LNA_TIA_C_M 0x7000
#define PATH0_R_G_WB_GIDX_12_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_12_LNA_TIA_C_M 0x38000
#define PATH0_R_G_WB_GIDX_13_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_13_LNA_TIA_C_M 0x1C0000
#define PATH0_R_G_WB_GIDX_14_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_14_LNA_TIA_C_M 0xE00000
#define PATH0_R_G_WB_GIDX_15_LNA_TIA_C 0x4728
#define PATH0_R_G_WB_GIDX_15_LNA_TIA_C_M 0x7000000
#define PATH0_R_BT_LNA_IDX0_C 0x4728
#define PATH0_R_BT_LNA_IDX0_C_M 0x38000000
#define PATH0_R_LINEAR_STEP_LIM_C 0x4728
#define PATH0_R_LINEAR_STEP_LIM_C_M 0xC0000000
#define PATH0_R_BT_LNA_IDX1_C 0x472C
#define PATH0_R_BT_LNA_IDX1_C_M 0x7
#define PATH0_R_BT_LNA_IDX2_C 0x472C
#define PATH0_R_BT_LNA_IDX2_C_M 0x38
#define PATH0_R_BT_LNA_IDX3_C 0x472C
#define PATH0_R_BT_LNA_IDX3_C_M 0x1C0
#define PATH0_R_ELNA_SEL_MARGIN_LGC_C 0x472C
#define PATH0_R_ELNA_SEL_MARGIN_LGC_C_M 0xE00
#define PATH0_R_ELNA_SEL_MARGIN_NLGC_C 0x472C
#define PATH0_R_ELNA_SEL_MARGIN_NLGC_C_M 0x7000
#define PATH0_R_IBADC_CLIP_RATIO_C 0x472C
#define PATH0_R_IBADC_CLIP_RATIO_C_M 0x38000
#define PATH0_R_IBADC_CLIP_TH_C 0x472C
#define PATH0_R_IBADC_CLIP_TH_C_M 0x1C0000
#define PATH0_R_LGC_STEP_LIM_C 0x472C
#define PATH0_R_LGC_STEP_LIM_C_M 0xE00000
#define PATH0_R_LNA_IDX_INIT_C 0x472C
#define PATH0_R_LNA_IDX_INIT_C_M 0x7000000
#define PATH0_R_LNA_SEL_MARGIN_LGC_C 0x472C
#define PATH0_R_LNA_SEL_MARGIN_LGC_C_M 0x38000000
#define PATH0_R_LINEAR_STEP_MIN_C 0x472C
#define PATH0_R_LINEAR_STEP_MIN_C_M 0xC0000000
#define PATH0_R_LNA_SEL_MARGIN_NLGC_C 0x4730
#define PATH0_R_LNA_SEL_MARGIN_NLGC_C_M 0x7
#define PATH0_R_RXSEL_MARGIN_LGC_C 0x4730
#define PATH0_R_RXSEL_MARGIN_LGC_C_M 0x38
#define PATH0_R_RXSEL_MARGIN_NLGC_C 0x4730
#define PATH0_R_RXSEL_MARGIN_NLGC_C_M 0x1C0
#define PATH0_R_TIA_SEL_MARGIN_LGC_C 0x4730
#define PATH0_R_TIA_SEL_MARGIN_LGC_C_M 0xE00
#define PATH0_R_TIA_SEL_MARGIN_NLGC_C 0x4730
#define PATH0_R_TIA_SEL_MARGIN_NLGC_C_M 0x7000
#define PATH0_R_WBADC_CLIP_RATIO_C 0x4730
#define PATH0_R_WBADC_CLIP_RATIO_C_M 0x38000
#define PATH0_R_WBADC_CLIP_TH_C 0x4730
#define PATH0_R_WBADC_CLIP_TH_C_M 0x1C0000
#define PATH0_R_NLGC_STEP_LIM_C 0x4730
#define PATH0_R_NLGC_STEP_LIM_C_M 0x600000
#define PATH0_R_NLGC_STEP_MIN_C 0x4730
#define PATH0_R_NLGC_STEP_MIN_C_M 0x1800000
#define PATH0_R_POST_PD_STEP_LIM_C 0x4730
#define PATH0_R_POST_PD_STEP_LIM_C_M 0x6000000
#define PATH0_R_POST_PD_STEP_MIN_C 0x4730
#define PATH0_R_POST_PD_STEP_MIN_C_M 0x18000000
#define PATH0_R_PRE_PD_STEP_LIM_C 0x4730
#define PATH0_R_PRE_PD_STEP_LIM_C_M 0x60000000
#define PATH0_R_AGC_EN_C 0x4730
#define PATH0_R_AGC_EN_C_M 0x80000000
#define PATH0_R_PRE_PD_STEP_MIN_C 0x4734
#define PATH0_R_PRE_PD_STEP_MIN_C_M 0x3
#define PATH0_R_WBADC_PW_ALPHA_H_C 0x4734
#define PATH0_R_WBADC_PW_ALPHA_H_C_M 0xC
#define PATH0_R_WBADC_PW_ALPHA_L_C 0x4734
#define PATH0_R_WBADC_PW_ALPHA_L_C_M 0x30
#define PATH0_R_A_WB_GIDX_00_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_00_ELNA_C_M 0x40
#define PATH0_R_A_WB_GIDX_01_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_01_ELNA_C_M 0x80
#define PATH0_R_A_WB_GIDX_02_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_02_ELNA_C_M 0x100
#define PATH0_R_A_WB_GIDX_03_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_03_ELNA_C_M 0x200
#define PATH0_R_A_WB_GIDX_04_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_04_ELNA_C_M 0x400
#define PATH0_R_A_WB_GIDX_05_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_05_ELNA_C_M 0x800
#define PATH0_R_A_WB_GIDX_06_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_06_ELNA_C_M 0x1000
#define PATH0_R_A_WB_GIDX_07_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_07_ELNA_C_M 0x2000
#define PATH0_R_A_WB_GIDX_08_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_08_ELNA_C_M 0x4000
#define PATH0_R_A_WB_GIDX_09_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_09_ELNA_C_M 0x8000
#define PATH0_R_A_WB_GIDX_10_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_10_ELNA_C_M 0x10000
#define PATH0_R_A_WB_GIDX_11_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_11_ELNA_C_M 0x20000
#define PATH0_R_A_WB_GIDX_12_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_12_ELNA_C_M 0x40000
#define PATH0_R_A_WB_GIDX_13_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_13_ELNA_C_M 0x80000
#define PATH0_R_A_WB_GIDX_14_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_14_ELNA_C_M 0x100000
#define PATH0_R_A_WB_GIDX_15_ELNA_C 0x4734
#define PATH0_R_A_WB_GIDX_15_ELNA_C_M 0x200000
#define PATH0_R_GC_TIME_1T_MORE_C 0x4734
#define PATH0_R_GC_TIME_1T_MORE_C_M 0x400000
#define PATH0_R_G_WB_GIDX_00_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_00_ELNA_C_M 0x800000
#define PATH0_R_G_WB_GIDX_01_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_01_ELNA_C_M 0x1000000
#define PATH0_R_G_WB_GIDX_02_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_02_ELNA_C_M 0x2000000
#define PATH0_R_G_WB_GIDX_03_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_03_ELNA_C_M 0x4000000
#define PATH0_R_G_WB_GIDX_04_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_04_ELNA_C_M 0x8000000
#define PATH0_R_G_WB_GIDX_05_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_05_ELNA_C_M 0x10000000
#define PATH0_R_G_WB_GIDX_06_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_06_ELNA_C_M 0x20000000
#define PATH0_R_G_WB_GIDX_07_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_07_ELNA_C_M 0x40000000
#define PATH0_R_G_WB_GIDX_08_ELNA_C 0x4734
#define PATH0_R_G_WB_GIDX_08_ELNA_C_M 0x80000000
#define PATH0_R_G_WB_GIDX_09_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_09_ELNA_C_M 0x1
#define PATH0_R_G_WB_GIDX_10_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_10_ELNA_C_M 0x2
#define PATH0_R_G_WB_GIDX_11_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_11_ELNA_C_M 0x4
#define PATH0_R_G_WB_GIDX_12_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_12_ELNA_C_M 0x8
#define PATH0_R_G_WB_GIDX_13_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_13_ELNA_C_M 0x10
#define PATH0_R_G_WB_GIDX_14_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_14_ELNA_C_M 0x20
#define PATH0_R_G_WB_GIDX_15_ELNA_C 0x4738
#define PATH0_R_G_WB_GIDX_15_ELNA_C_M 0x40
#define PATH0_R_SE1_TIME_C 0x4738
#define PATH0_R_SE1_TIME_C_M 0x80
#define PATH0_R_SE1_TIME_NLGC_C 0x4738
#define PATH0_R_SE1_TIME_NLGC_C_M 0x100
#define PATH0_R_SE2_TIME_C 0x4738
#define PATH0_R_SE2_TIME_C_M 0x200
#define PATH0_R_SE2_TIME_NLGC_C 0x4738
#define PATH0_R_SE2_TIME_NLGC_C_M 0x400
#define PATH0_R_SE3_TIME_C 0x4738
#define PATH0_R_SE3_TIME_C_M 0x800
#define PATH0_R_SE4_TIME_C 0x4738
#define PATH0_R_SE4_TIME_C_M 0x1000
#define PATH0_R_SE5_TIME_C 0x4738
#define PATH0_R_SE5_TIME_C_M 0x2000
#define PATH0_R_SE_TIME_DONE_C 0x4738
#define PATH0_R_SE_TIME_DONE_C_M 0x4000
#define PATH0_R_SE_TIME_LINEAR_EXT_C 0x4738
#define PATH0_R_SE_TIME_LINEAR_EXT_C_M 0x8000
#define PATH0_R_ACI_NRBW_EN_C 0x4738
#define PATH0_R_ACI_NRBW_EN_C_M 0x10000
#define PATH0_R_BAND_SEL_C 0x4738
#define PATH0_R_BAND_SEL_C_M 0x20000
#define PATH0_R_BT_RX_MODE_EN_C 0x4738
#define PATH0_R_BT_RX_MODE_EN_C_M 0x40000
#define PATH0_R_BT_SHARE_C 0x4738
#define PATH0_R_BT_SHARE_C_M 0x80000
#define PATH0_R_BT_TX_FORCE_NRBW_C 0x4738
#define PATH0_R_BT_TX_FORCE_NRBW_C_M 0x100000
#define PATH0_R_BT_TX_MODE_EN_C 0x4738
#define PATH0_R_BT_TX_MODE_EN_C_M 0x200000
#define PATH0_R_BTG_PATH_C 0x4738
#define PATH0_R_BTG_PATH_C_M 0x400000
#define PATH0_R_CCK_FORCE_NRBW_C 0x4738
#define PATH0_R_CCK_FORCE_NRBW_C_M 0x800000
#define PATH0_R_DCCL_EN_C 0x4738
#define PATH0_R_DCCL_EN_C_M 0x1000000
#define PATH0_R_ELNA_BYPASS_EN_C 0x4738
#define PATH0_R_ELNA_BYPASS_EN_C_M 0x2000000
#define PATH0_R_ELNA_EN_C 0x4738
#define PATH0_R_ELNA_EN_C_M 0x4000000
#define PATH0_R_ELNA_IDX_INIT_C 0x4738
#define PATH0_R_ELNA_IDX_INIT_C_M 0x8000000
#define PATH0_R_FORCE_BT_COEX_C 0x4738
#define PATH0_R_FORCE_BT_COEX_C_M 0x10000000
#define PATH0_R_FORCE_NRBW_C 0x4738
#define PATH0_R_FORCE_NRBW_C_M 0x20000000
#define PATH0_R_I_ONLY_C 0x4738
#define PATH0_R_I_ONLY_C_M 0x40000000
#define PATH0_R_LGC_DAGC_EN_C 0x4738
#define PATH0_R_LGC_DAGC_EN_C_M 0x80000000
#define PATH0_R_LINEAR_AGC_EN_C 0x473C
#define PATH0_R_LINEAR_AGC_EN_C_M 0x1
#define PATH0_R_LINEAR_MARGIN_MODE_C 0x473C
#define PATH0_R_LINEAR_MARGIN_MODE_C_M 0x2
#define PATH0_R_NLGC_AGC_EN_C 0x473C
#define PATH0_R_NLGC_AGC_EN_C_M 0x4
#define PATH0_R_NLGC_DAGC_EN_C 0x473C
#define PATH0_R_NLGC_DAGC_EN_C_M 0x8
#define PATH0_R_NRBW_DEF_C 0x473C
#define PATH0_R_NRBW_DEF_C_M 0x10
#define PATH0_R_POST_PD_AGC_EN_C 0x473C
#define PATH0_R_POST_PD_AGC_EN_C_M 0x20
#define PATH0_R_PRE_PD_AGC_EN_C 0x473C
#define PATH0_R_PRE_PD_AGC_EN_C_M 0x40
#define PATH0_R_PURE_POST_PD_MODE_C 0x473C
#define PATH0_R_PURE_POST_PD_MODE_C_M 0x80
#define PATH0_R_SYNC_PRE_PD_STEP_C 0x473C
#define PATH0_R_SYNC_PRE_PD_STEP_C_M 0x100
#define PATH0_R_TIA_IDX_INIT_C 0x473C
#define PATH0_R_TIA_IDX_INIT_C_M 0x200
#define PATH0_R_TIA_SHRINK_DEF_C 0x473C
#define PATH0_R_TIA_SHRINK_DEF_C_M 0x400
#define PATH0_R_TIA_SHRINK_EN_C 0x473C
#define PATH0_R_TIA_SHRINK_EN_C_M 0x800
#define PATH0_R_TIA_SHRINK_INIT_C 0x473C
#define PATH0_R_TIA_SHRINK_INIT_C_M 0x1000
#define PATH1_R_A_G_ELNA0_C 0x4740
#define PATH1_R_A_G_ELNA0_C_M 0xFF
#define PATH1_R_A_G_ELNA1_C 0x4740
#define PATH1_R_A_G_ELNA1_C_M 0xFF00
#define PATH1_R_A_G_LNA0_C 0x4740
#define PATH1_R_A_G_LNA0_C_M 0xFF0000
#define PATH1_R_A_G_LNA1_C 0x4740
#define PATH1_R_A_G_LNA1_C_M 0xFF000000
#define PATH1_R_A_G_LNA2_C 0x4744
#define PATH1_R_A_G_LNA2_C_M 0xFF
#define PATH1_R_A_G_LNA3_C 0x4744
#define PATH1_R_A_G_LNA3_C_M 0xFF00
#define PATH1_R_A_G_LNA4_C 0x4744
#define PATH1_R_A_G_LNA4_C_M 0xFF0000
#define PATH1_R_A_G_LNA5_C 0x4744
#define PATH1_R_A_G_LNA5_C_M 0xFF000000
#define PATH1_R_A_G_LNA6_C 0x4748
#define PATH1_R_A_G_LNA6_C_M 0xFF
#define PATH1_R_A_G_RX0_C 0x4748
#define PATH1_R_A_G_RX0_C_M 0xFF00
#define PATH1_R_A_G_TIA0_C 0x4748
#define PATH1_R_A_G_TIA0_C_M 0xFF0000
#define PATH1_R_A_G_TIA1_C 0x4748
#define PATH1_R_A_G_TIA1_C_M 0xFF000000
#define PATH1_R_A_LNA0_OP1DB_C 0x474C
#define PATH1_R_A_LNA0_OP1DB_C_M 0xFF
#define PATH1_R_A_LNA1_OP1DB_C 0x474C
#define PATH1_R_A_LNA1_OP1DB_C_M 0xFF00
#define PATH1_R_A_LNA2_OP1DB_C 0x474C
#define PATH1_R_A_LNA2_OP1DB_C_M 0xFF0000
#define PATH1_R_A_LNA3_OP1DB_C 0x474C
#define PATH1_R_A_LNA3_OP1DB_C_M 0xFF000000
#define PATH1_R_A_LNA4_OP1DB_C 0x4750
#define PATH1_R_A_LNA4_OP1DB_C_M 0xFF
#define PATH1_R_A_LNA5_OP1DB_C 0x4750
#define PATH1_R_A_LNA5_OP1DB_C_M 0xFF00
#define PATH1_R_A_LNA6_OP1DB_C 0x4750
#define PATH1_R_A_LNA6_OP1DB_C_M 0xFF0000
#define PATH1_R_A_RXOP1DB_C 0x4750
#define PATH1_R_A_RXOP1DB_C_M 0xFF000000
#define PATH1_R_A_TIA0_LNA0_OP1DB_C 0x4754
#define PATH1_R_A_TIA0_LNA0_OP1DB_C_M 0xFF
#define PATH1_R_A_TIA0_LNA1_OP1DB_C 0x4754
#define PATH1_R_A_TIA0_LNA1_OP1DB_C_M 0xFF00
#define PATH1_R_A_TIA0_LNA2_OP1DB_C 0x4754
#define PATH1_R_A_TIA0_LNA2_OP1DB_C_M 0xFF0000
#define PATH1_R_A_TIA0_LNA3_OP1DB_C 0x4754
#define PATH1_R_A_TIA0_LNA3_OP1DB_C_M 0xFF000000
#define PATH1_R_A_TIA0_LNA4_OP1DB_C 0x4758
#define PATH1_R_A_TIA0_LNA4_OP1DB_C_M 0xFF
#define PATH1_R_A_TIA0_LNA5_OP1DB_C 0x4758
#define PATH1_R_A_TIA0_LNA5_OP1DB_C_M 0xFF00
#define PATH1_R_A_TIA0_LNA6_OP1DB_C 0x4758
#define PATH1_R_A_TIA0_LNA6_OP1DB_C_M 0xFF0000
#define PATH1_R_A_TIA1_LNA6_OP1DB_C 0x4758
#define PATH1_R_A_TIA1_LNA6_OP1DB_C_M 0xFF000000
#define PATH1_R_G_G_ELNA0_C 0x475C
#define PATH1_R_G_G_ELNA0_C_M 0xFF
#define PATH1_R_G_G_ELNA1_C 0x475C
#define PATH1_R_G_G_ELNA1_C_M 0xFF00
#define PATH1_R_G_G_LNA0_C 0x475C
#define PATH1_R_G_G_LNA0_C_M 0xFF0000
#define PATH1_R_G_G_LNA1_C 0x475C
#define PATH1_R_G_G_LNA1_C_M 0xFF000000
#define PATH1_R_G_G_LNA2_C 0x4760
#define PATH1_R_G_G_LNA2_C_M 0xFF
#define PATH1_R_G_G_LNA3_C 0x4760
#define PATH1_R_G_G_LNA3_C_M 0xFF00
#define PATH1_R_G_G_LNA4_C 0x4760
#define PATH1_R_G_G_LNA4_C_M 0xFF0000
#define PATH1_R_G_G_LNA5_C 0x4760
#define PATH1_R_G_G_LNA5_C_M 0xFF000000
#define PATH1_R_G_G_LNA6_C 0x4764
#define PATH1_R_G_G_LNA6_C_M 0xFF
#define PATH1_R_G_G_RX0_C 0x4764
#define PATH1_R_G_G_RX0_C_M 0xFF00
#define PATH1_R_G_G_TIA0_C 0x4764
#define PATH1_R_G_G_TIA0_C_M 0xFF0000
#define PATH1_R_G_G_TIA1_C 0x4764
#define PATH1_R_G_G_TIA1_C_M 0xFF000000
#define PATH1_R_G_LGC_DAGC_C 0x4768
#define PATH1_R_G_LGC_DAGC_C_M 0xFF
#define PATH1_R_G_LNA0_OP1DB_C 0x4768
#define PATH1_R_G_LNA0_OP1DB_C_M 0xFF00
#define PATH1_R_G_LNA1_OP1DB_C 0x4768
#define PATH1_R_G_LNA1_OP1DB_C_M 0xFF0000
#define PATH1_R_G_LNA2_OP1DB_C 0x4768
#define PATH1_R_G_LNA2_OP1DB_C_M 0xFF000000
#define PATH1_R_G_LNA3_OP1DB_C 0x476C
#define PATH1_R_G_LNA3_OP1DB_C_M 0xFF
#define PATH1_R_G_LNA4_OP1DB_C 0x476C
#define PATH1_R_G_LNA4_OP1DB_C_M 0xFF00
#define PATH1_R_G_LNA5_OP1DB_C 0x476C
#define PATH1_R_G_LNA5_OP1DB_C_M 0xFF0000
#define PATH1_R_G_LNA6_OP1DB_C 0x476C
#define PATH1_R_G_LNA6_OP1DB_C_M 0xFF000000
#define PATH1_R_G_NLGC_DAGC_C 0x4770
#define PATH1_R_G_NLGC_DAGC_C_M 0xFF
#define PATH1_R_G_RXOP1DB_C 0x4770
#define PATH1_R_G_RXOP1DB_C_M 0xFF00
#define PATH1_R_G_TIA0_LNA0_OP1DB_C 0x4770
#define PATH1_R_G_TIA0_LNA0_OP1DB_C_M 0xFF0000
#define PATH1_R_G_TIA0_LNA1_OP1DB_C 0x4770
#define PATH1_R_G_TIA0_LNA1_OP1DB_C_M 0xFF000000
#define PATH1_R_G_TIA0_LNA2_OP1DB_C 0x4774
#define PATH1_R_G_TIA0_LNA2_OP1DB_C_M 0xFF
#define PATH1_R_G_TIA0_LNA3_OP1DB_C 0x4774
#define PATH1_R_G_TIA0_LNA3_OP1DB_C_M 0xFF00
#define PATH1_R_G_TIA0_LNA4_OP1DB_C 0x4774
#define PATH1_R_G_TIA0_LNA4_OP1DB_C_M 0xFF0000
#define PATH1_R_G_TIA0_LNA5_OP1DB_C 0x4774
#define PATH1_R_G_TIA0_LNA5_OP1DB_C_M 0xFF000000
#define PATH1_R_G_TIA0_LNA6_OP1DB_C 0x4778
#define PATH1_R_G_TIA0_LNA6_OP1DB_C_M 0xFF
#define PATH1_R_G_TIA1_LNA6_OP1DB_C 0x4778
#define PATH1_R_G_TIA1_LNA6_OP1DB_C_M 0xFF00
#define PATH1_R_G_OFST_C 0x4778
#define PATH1_R_G_OFST_C_M 0xFF0000
#define PATH1_R_IBADC_SAT_TH_C 0x4778
#define PATH1_R_IBADC_SAT_TH_C_M 0xFF000000
#define PATH1_R_IBADC_UNDER_TH_C 0x477C
#define PATH1_R_IBADC_UNDER_TH_C_M 0xFF
#define PATH1_R_WBADC_SAT_TH_C 0x477C
#define PATH1_R_WBADC_SAT_TH_C_M 0xFF00
#define PATH1_R_WBADC_SAT_TH_ANTWGT_C 0x477C
#define PATH1_R_WBADC_SAT_TH_ANTWGT_C_M 0xFF0000
#define PATH1_R_WBADC_UNDER_TH_C 0x477C
#define PATH1_R_WBADC_UNDER_TH_C_M 0xFF000000
#define PATH1_R_DCCL_SYNC_BKP1_C 0x4780
#define PATH1_R_DCCL_SYNC_BKP1_C_M 0xFFFFFFFF
#define PATH1_R_DCCL_SYNC_BKP2_C 0x4784
#define PATH1_R_DCCL_SYNC_BKP2_C_M 0xFFFFFFFF
#define PATH1_R_ALPHA_END_IDX_C 0x4788
#define PATH1_R_ALPHA_END_IDX_C_M 0xF
#define PATH1_R_ALPHA_START_IDX_C 0x4788
#define PATH1_R_ALPHA_START_IDX_C_M 0xF0
#define PATH1_R_TIME_CONST_IDX_C 0x4788
#define PATH1_R_TIME_CONST_IDX_C_M 0x700
#define PATH1_R_RXFIR_BKP_C 0x478C
#define PATH1_R_RXFIR_BKP_C_M 0xFFFFFFFF
#define PATH1_R_FORCE_FIR_TYPE_C 0x4790
#define PATH1_R_FORCE_FIR_TYPE_C_M 0x3
#define PATH1_R_CCK_CCA_SHRINK_EN_C 0x4790
#define PATH1_R_CCK_CCA_SHRINK_EN_C_M 0x4
#define PATH1_P20_R_L1_CFO_CMP_EN_C 0x4794
#define PATH1_P20_R_L1_CFO_CMP_EN_C_M 0x1
#define PATH1_S20_R_L1_CFO_CMP_EN_C 0x4798
#define PATH1_S20_R_L1_CFO_CMP_EN_C_M 0x1
#define PATH1_R_NBI_NOTCH_BKP1_C 0x479C
#define PATH1_R_NBI_NOTCH_BKP1_C_M 0xFFFFFFFF
#define PATH1_R_NBI_NOTCH_BKP2_C 0x47A0
#define PATH1_R_NBI_NOTCH_BKP2_C_M 0xFFFFFFFF
#define PATH1_R_NBI_IDX_C 0x47A4
#define PATH1_R_NBI_IDX_C_M 0xFF
#define PATH1_R_CORNER_IDX_C 0x47A4
#define PATH1_R_CORNER_IDX_C_M 0x300
#define PATH1_R_NBI_FRAC_IDX_C 0x47A4
#define PATH1_R_NBI_FRAC_IDX_C_M 0xC00
#define PATH1_R_NBI_NOTCH_EN_C 0x47A4
#define PATH1_R_NBI_NOTCH_EN_C_M 0x1000
#define PATH1_P20_R_DAGC_EXTRA_SETTLING_TIME_C 0x47A8
#define PATH1_P20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
#define PATH1_P20_R_DAGC_SETTLING_TIME_C 0x47A8
#define PATH1_P20_R_DAGC_SETTLING_TIME_C_M 0x18
#define PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C 0x47A8
#define PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
#define PATH1_P20_R_PW_EST_SHORT_TIME_FAGC_C 0x47A8
#define PATH1_P20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
#define PATH1_P20_R_PW_EST_TIME_FAGC_C 0x47A8
#define PATH1_P20_R_PW_EST_TIME_FAGC_C_M 0x80
#define PATH1_P20_R_PW_EST_TIME_PAGC_C 0x47A8
#define PATH1_P20_R_PW_EST_TIME_PAGC_C_M 0x100
#define PATH1_P20_R_PW_EST_TIME_RFGC_C 0x47A8
#define PATH1_P20_R_PW_EST_TIME_RFGC_C_M 0x200
#define PATH1_P20_R_SDAGC_EN_C 0x47A8
#define PATH1_P20_R_SDAGC_EN_C_M 0x400
#define PATH1_S20_R_DAGC_EXTRA_SETTLING_TIME_C 0x47AC
#define PATH1_S20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
#define PATH1_S20_R_DAGC_SETTLING_TIME_C 0x47AC
#define PATH1_S20_R_DAGC_SETTLING_TIME_C_M 0x18
#define PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C 0x47AC
#define PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
#define PATH1_S20_R_PW_EST_SHORT_TIME_FAGC_C 0x47AC
#define PATH1_S20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
#define PATH1_S20_R_PW_EST_TIME_FAGC_C 0x47AC
#define PATH1_S20_R_PW_EST_TIME_FAGC_C_M 0x80
#define PATH1_S20_R_PW_EST_TIME_PAGC_C 0x47AC
#define PATH1_S20_R_PW_EST_TIME_PAGC_C_M 0x100
#define PATH1_S20_R_PW_EST_TIME_RFGC_C 0x47AC
#define PATH1_S20_R_PW_EST_TIME_RFGC_C_M 0x200
#define PATH1_S20_R_SDAGC_EN_C 0x47AC
#define PATH1_S20_R_SDAGC_EN_C_M 0x400
#define PATH1_R_5MDET_BKP1_C 0x47B0
#define PATH1_R_5MDET_BKP1_C_M 0xFFFFFFFF
#define PATH1_R_5MDET_BKP2_C 0x47B4
#define PATH1_R_5MDET_BKP2_C_M 0xFFFFFFFF
#define PATH1_R_5MDET_TH_DB_C 0x47B8
#define PATH1_R_5MDET_TH_DB_C_M 0x3F
#define PATH1_R_5MDET_MASK_SB0_C 0x47B8
#define PATH1_R_5MDET_MASK_SB0_C_M 0x40
#define PATH1_R_5MDET_MASK_SB1_C 0x47B8
#define PATH1_R_5MDET_MASK_SB1_C_M 0x80
#define PATH1_R_5MDET_MASK_SB2_C 0x47B8
#define PATH1_R_5MDET_MASK_SB2_C_M 0x100
#define PATH1_R_5MDET_MASK_SB3_C 0x47B8
#define PATH1_R_5MDET_MASK_SB3_C_M 0x200
#define PATH1_R_5MDET_MODE_C 0x47B8
#define PATH1_R_5MDET_MODE_C_M 0x400
#define PATH1_R_IIR_PW_AVG_EN_C 0x47B8
#define PATH1_R_IIR_PW_AVG_EN_C_M 0x800
#define PATH1_R_SBF5M_EN_C 0x47B8
#define PATH1_R_SBF5M_EN_C_M 0x1000
#define POP_RSV_C 0x47C4
#define POP_RSV_C_M 0xFFFFFFFF
#define CLIPPING_LVL_C 0x47C8
#define CLIPPING_LVL_C_M 0x3FF
#define CLIPPING_OBS_C 0x47C8
#define CLIPPING_OBS_C_M 0x1FC00
#define CLIPPING_RATIO_C 0x47C8
#define CLIPPING_RATIO_C_M 0xFE0000
#define B_THD_C 0x47C8
#define B_THD_C_M 0x3F000000
#define BT_GNT_POP_EN_C 0x47C8
#define BT_GNT_POP_EN_C_M 0x40000000
#define CCK_EN_C 0x47C8
#define CCK_EN_C_M 0x80000000
#define M_THD_C 0x47CC
#define M_THD_C_M 0x3F
#define CCK_DROP_TH_C 0x47CC
#define CCK_DROP_TH_C_M 0x7C0
#define CCK_POP_H_TH_C 0x47CC
#define CCK_POP_H_TH_C_M 0xF800
#define CCK_POP_L_TH_C 0x47CC
#define CCK_POP_L_TH_C_M 0x1F0000
#define D_CNT_C 0x47CC
#define D_CNT_C_M 0x3E00000
#define D_THD_C 0x47CC
#define D_THD_C_M 0x7C000000
#define D_EN_C 0x47CC
#define D_EN_C_M 0x80000000
#define H_THD_C 0x47D0
#define H_THD_C_M 0x1F
#define L_THD_C 0x47D0
#define L_THD_C_M 0x3E0
#define OFDM_DROP_TH_C 0x47D0
#define OFDM_DROP_TH_C_M 0x7C00
#define OFDM_POP_H_TH_C 0x47D0
#define OFDM_POP_H_TH_C_M 0xF8000
#define OFDM_POP_L_TH_C 0x47D0
#define OFDM_POP_L_TH_C_M 0x1F00000
#define P_CNT_C 0x47D0
#define P_CNT_C_M 0x3E000000
#define D_LSIG_RDY_C 0x47D0
#define D_LSIG_RDY_C_M 0x40000000
#define DL_EN_C 0x47D0
#define DL_EN_C_M 0x80000000
#define O_THD_C 0x47D4
#define O_THD_C_M 0x7
#define REFPW_LB_C 0x47D4
#define REFPW_LB_C_M 0x38
#define M_40_C 0x47D4
#define M_40_C_M 0x40
#define OFDM_EN_C 0x47D4
#define OFDM_EN_C_M 0x80
#define P_EN_C 0x47D4
#define P_EN_C_M 0x100
#define P_LSIG_RDY_C 0x47D4
#define P_LSIG_RDY_C_M 0x200
#define REFPW_LB_EN_C 0x47D4
#define REFPW_LB_EN_C_M 0x400
#define P20_SEG0R_PINTHD_C 0x47D8
#define P20_SEG0R_PINTHD_C_M 0xFF
#define P20_SEG0R_PWDIF_C 0x47D8
#define P20_SEG0R_PWDIF_C_M 0x3F00
#define P20_SEG0R_P20TAR_C 0x47D8
#define P20_SEG0R_P20TAR_C_M 0x7C000
#define P20_SEG0R_BT_WGT_C 0x47D8
#define P20_SEG0R_BT_WGT_C_M 0x380000
#define P20_SEG0R_UNIT_WGT_OPT_C 0x47D8
#define P20_SEG0R_UNIT_WGT_OPT_C_M 0x400000
#define P20_SEG0R_WGT_EN_C 0x47D8
#define P20_SEG0R_WGT_EN_C_M 0x800000
#define P20_SEG0R_ZERO_WGT_EN_C 0x47D8
#define P20_SEG0R_ZERO_WGT_EN_C_M 0x1000000
#define S20_SEG0R_PINTHD_C 0x47DC
#define S20_SEG0R_PINTHD_C_M 0xFF
#define S20_SEG0R_PWDIF_C 0x47DC
#define S20_SEG0R_PWDIF_C_M 0x3F00
#define S20_SEG0R_P20TAR_C 0x47DC
#define S20_SEG0R_P20TAR_C_M 0x7C000
#define S20_SEG0R_BT_WGT_C 0x47DC
#define S20_SEG0R_BT_WGT_C_M 0x380000
#define S20_SEG0R_UNIT_WGT_OPT_C 0x47DC
#define S20_SEG0R_UNIT_WGT_OPT_C_M 0x400000
#define S20_SEG0R_WGT_EN_C 0x47DC
#define S20_SEG0R_WGT_EN_C_M 0x800000
#define S20_SEG0R_ZERO_WGT_EN_C 0x47DC
#define S20_SEG0R_ZERO_WGT_EN_C_M 0x1000000
#define BW_INDSEG0R_BW_GAIN_CHK_THD_C 0x47E0
#define BW_INDSEG0R_BW_GAIN_CHK_THD_C_M 0x3F
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_C 0x47E0
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_C_M 0x7C0
#define BW_INDSEG0R_CBW20_HIGH_PIN_TH_BWD_C 0x47E0
#define BW_INDSEG0R_CBW20_HIGH_PIN_TH_BWD_C_M 0xF800
#define BW_INDSEG0R_CBW20_LOW_PIN_TH_BW_C 0x47E0
#define BW_INDSEG0R_CBW20_LOW_PIN_TH_BW_C_M 0x1F0000
#define BW_INDSEG0R_CBW40_HIGH_PIN_TH_BWD_C 0x47E0
#define BW_INDSEG0R_CBW40_HIGH_PIN_TH_BWD_C_M 0x3E00000
#define BW_INDSEG0R_CBW40_LOW_PIN_TH_BW_C 0x47E0
#define BW_INDSEG0R_CBW40_LOW_PIN_TH_BW_C_M 0x7C000000
#define BW_INDSEG0R_BW_GAIN_CHK_EN_C 0x47E0
#define BW_INDSEG0R_BW_GAIN_CHK_EN_C_M 0x80000000
#define BW_INDSEG0R_CBW80_HIGH_PIN_TH_BWD_C 0x47E4
#define BW_INDSEG0R_CBW80_HIGH_PIN_TH_BWD_C_M 0x1F
#define BW_INDSEG0R_CBW80_LOW_PIN_TH_BW_C 0x47E4
#define BW_INDSEG0R_CBW80_LOW_PIN_TH_BW_C_M 0x3E0
#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX1_C 0x47E4
#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX1_C_M 0x7C00
#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX2_C 0x47E4
#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX2_C_M 0xF8000
#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX1_C 0x47E4
#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX1_C_M 0x1F00000
#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX2_C 0x47E4
#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX2_C_M 0x3E000000
#define BW_INDSEG0R_BW_START_CHK_EN_C 0x47E4
#define BW_INDSEG0R_BW_START_CHK_EN_C_M 0x40000000
#define BW_INDSEG0R_BW_TIMING_CTRL_OPT_C 0x47E4
#define BW_INDSEG0R_BW_TIMING_CTRL_OPT_C_M 0x80000000
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX1_C 0x47E8
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX1_C_M 0x1F
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX2_C 0x47E8
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX2_C_M 0x3E0
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX1_C 0x47E8
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX1_C_M 0x7C00
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX2_C 0x47E8
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX2_C_M 0xF8000
#define BW_INDSEG0R_BW_COUNT_MAX_BY_FALLING_C 0x47E8
#define BW_INDSEG0R_BW_COUNT_MAX_BY_FALLING_C_M 0xF00000
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_AFTER_L1_IS_FOUND_C 0x47E8
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_AFTER_L1_IS_FOUND_C_M 0xF000000
#define BW_INDSEG0R_BW_START_HALF_SYM_COUNT_C 0x47E8
#define BW_INDSEG0R_BW_START_HALF_SYM_COUNT_C_M 0xF0000000
#define BW_INDSEG0R_INDICATOR_TH_OFST_0_C 0x47EC
#define BW_INDSEG0R_INDICATOR_TH_OFST_0_C_M 0xF
#define BW_INDSEG0R_INDICATOR_TH_OFST_1_C 0x47EC
#define BW_INDSEG0R_INDICATOR_TH_OFST_1_C_M 0xF0
#define BW_INDSEG0R_INDICATOR_TH_OFST_BY_RSSI_C 0x47EC
#define BW_INDSEG0R_INDICATOR_TH_OFST_BY_RSSI_C_M 0xF00
#define BW_INDSEG0R_INTF_TH_0_C 0x47EC
#define BW_INDSEG0R_INTF_TH_0_C_M 0xF000
#define BW_INDSEG0R_INTF_TH_1_C 0x47EC
#define BW_INDSEG0R_INTF_TH_1_C_M 0xF0000
#define BW_INDSEG0R_START_HALF_SYM_OFST_BY_RSSI_C 0x47EC
#define BW_INDSEG0R_START_HALF_SYM_OFST_BY_RSSI_C_M 0xF00000
#define BW_INDSEG0R_CR_SWITCH_BY_PIN_C 0x47EC
#define BW_INDSEG0R_CR_SWITCH_BY_PIN_C_M 0x7000000
#define BW_INDSEG0R_SUB20_SEARCH_TH_C 0x47EC
#define BW_INDSEG0R_SUB20_SEARCH_TH_C_M 0x38000000
#define BW_INDSEG0R_CR_SWITCH_BY_ACI_EN_C 0x47EC
#define BW_INDSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x40000000
#define BW_INDSEG0R_CR_SWITCH_BY_RSSI_EN_C 0x47EC
#define BW_INDSEG0R_CR_SWITCH_BY_RSSI_EN_C_M 0x80000000
#define BW_INDSEG0R_EARLY_DROP_BY_L1_C 0x47F0
#define BW_INDSEG0R_EARLY_DROP_BY_L1_C_M 0x1
#define BW_INDSEG0R_FORCE_BW_EN_C 0x47F0
#define BW_INDSEG0R_FORCE_BW_EN_C_M 0x2
#define BW_INDSEG0R_FORCE_BW_MODE_C 0x47F0
#define BW_INDSEG0R_FORCE_BW_MODE_C_M 0x4
#define SEG0R_HIGH_PIN_TH_CFO_C 0x47F4
#define SEG0R_HIGH_PIN_TH_CFO_C_M 0x1F
#define SEG0R_HIGH_PIN_TH_CFOE_C 0x47F4
#define SEG0R_HIGH_PIN_TH_CFOE_C_M 0x1E0
#define SEG0R_CFO_START_OFST_C 0x47F4
#define SEG0R_CFO_START_OFST_C_M 0xE00
#define SEG0R_CFO_SIZE_OPT_C 0x47F4
#define SEG0R_CFO_SIZE_OPT_C_M 0x3000
#define SEG0R_COUNT_INI_PH_C 0x47F4
#define SEG0R_COUNT_INI_PH_C_M 0xC000
#define SEG0R_ZERO_CRO_CNT_DIFF_AVG_TH_C 0x47F8
#define SEG0R_ZERO_CRO_CNT_DIFF_AVG_TH_C_M 0x3FF
#define SEG0R_ZERO_CRO_CNT_DIFF_VAR_TH_C 0x47F8
#define SEG0R_ZERO_CRO_CNT_DIFF_VAR_TH_C_M 0xFFC00
#define SEG0R_H2L_TH_C 0x47F8
#define SEG0R_H2L_TH_C_M 0xFF00000
#define SEG0R_ZERO_CRO_OBS_INTRVL_C 0x47F8
#define SEG0R_ZERO_CRO_OBS_INTRVL_C_M 0xF0000000
#define SEG0R_L2H_TH_C 0x47FC
#define SEG0R_L2H_TH_C_M 0xFF
#define SEG0R_RXI_CHK_TH_C 0x47FC
#define SEG0R_RXI_CHK_TH_C_M 0xFF00
#define SEG0R_ADCPW_C 0x47FC
#define SEG0R_ADCPW_C_M 0x7F0000
#define SEG0R_ZERO_CRO_HIGH_TH_C 0x47FC
#define SEG0R_ZERO_CRO_HIGH_TH_C_M 0x3F800000
#define SEG0R_DCRM_EN_C 0x47FC
#define SEG0R_DCRM_EN_C_M 0x40000000
#define SEG0R_RFGC_EN_C 0x47FC
#define SEG0R_RFGC_EN_C_M 0x80000000
#define SEG0R_DC_COUNT_MAX_C 0x4800
#define SEG0R_DC_COUNT_MAX_C_M 0xF
#define SEG0R_DC_HIGH_TH_20_NRX1_C 0x4800
#define SEG0R_DC_HIGH_TH_20_NRX1_C_M 0xF0
#define SEG0R_DC_HIGH_TH_20_NRX2_C 0x4800
#define SEG0R_DC_HIGH_TH_20_NRX2_C_M 0xF00
#define SEG0R_DC_HIGH_TH_40_NRX1_C 0x4800
#define SEG0R_DC_HIGH_TH_40_NRX1_C_M 0xF000
#define SEG0R_DC_HIGH_TH_40_NRX2_C 0x4800
#define SEG0R_DC_HIGH_TH_40_NRX2_C_M 0xF0000
#define SEG0R_DC_HIGH_TH_80_NRX1_C 0x4800
#define SEG0R_DC_HIGH_TH_80_NRX1_C_M 0xF00000
#define SEG0R_DC_HIGH_TH_80_NRX2_C 0x4800
#define SEG0R_DC_HIGH_TH_80_NRX2_C_M 0xF000000
#define SEG0R_DC_HIGH_TH_80P80_NRX1_C 0x4800
#define SEG0R_DC_HIGH_TH_80P80_NRX1_C_M 0xF0000000
#define SEG0R_DC_HIGH_TH_80P80_NRX2_C 0x4804
#define SEG0R_DC_HIGH_TH_80P80_NRX2_C_M 0xF
#define SEG0R_DC_LOW_TH_20_NRX1_C 0x4804
#define SEG0R_DC_LOW_TH_20_NRX1_C_M 0xF0
#define SEG0R_DC_LOW_TH_20_NRX2_C 0x4804
#define SEG0R_DC_LOW_TH_20_NRX2_C_M 0xF00
#define SEG0R_DC_LOW_TH_40_NRX1_C 0x4804
#define SEG0R_DC_LOW_TH_40_NRX1_C_M 0xF000
#define SEG0R_DC_LOW_TH_40_NRX2_C 0x4804
#define SEG0R_DC_LOW_TH_40_NRX2_C_M 0xF0000
#define SEG0R_DC_LOW_TH_80_NRX1_C 0x4804
#define SEG0R_DC_LOW_TH_80_NRX1_C_M 0xF00000
#define SEG0R_DC_LOW_TH_80_NRX2_C 0x4804
#define SEG0R_DC_LOW_TH_80_NRX2_C_M 0xF000000
#define SEG0R_DC_LOW_TH_80P80_NRX1_C 0x4804
#define SEG0R_DC_LOW_TH_80P80_NRX1_C_M 0xF0000000
#define SEG0R_DC_LOW_TH_80P80_NRX2_C 0x4808
#define SEG0R_DC_LOW_TH_80P80_NRX2_C_M 0xF
#define SEG0R_DC_TH_OFST_C 0x4808
#define SEG0R_DC_TH_OFST_C_M 0xF0
#define SEG0R_DCFI_COUNT_MAX_C 0x4808
#define SEG0R_DCFI_COUNT_MAX_C_M 0xF00
#define SEG0R_DCFI_HIGH_TH_20_NRX1_C 0x4808
#define SEG0R_DCFI_HIGH_TH_20_NRX1_C_M 0xF000
#define SEG0R_DCFI_HIGH_TH_20_NRX2_C 0x4808
#define SEG0R_DCFI_HIGH_TH_20_NRX2_C_M 0xF0000
#define SEG0R_DCFI_HIGH_TH_40_NRX1_C 0x4808
#define SEG0R_DCFI_HIGH_TH_40_NRX1_C_M 0xF00000
#define SEG0R_DCFI_HIGH_TH_40_NRX2_C 0x4808
#define SEG0R_DCFI_HIGH_TH_40_NRX2_C_M 0xF000000
#define SEG0R_DCFI_HIGH_TH_80_NRX1_C 0x4808
#define SEG0R_DCFI_HIGH_TH_80_NRX1_C_M 0xF0000000
#define SEG0R_DCFI_HIGH_TH_80_NRX2_C 0x480C
#define SEG0R_DCFI_HIGH_TH_80_NRX2_C_M 0xF
#define SEG0R_DCFI_HIGH_TH_80P80_NRX1_C 0x480C
#define SEG0R_DCFI_HIGH_TH_80P80_NRX1_C_M 0xF0
#define SEG0R_DCFI_HIGH_TH_80P80_NRX2_C 0x480C
#define SEG0R_DCFI_HIGH_TH_80P80_NRX2_C_M 0xF00
#define SEG0R_DCFI_LOW_TH_20_NRX1_C 0x480C
#define SEG0R_DCFI_LOW_TH_20_NRX1_C_M 0xF000
#define SEG0R_DCFI_LOW_TH_20_NRX2_C 0x480C
#define SEG0R_DCFI_LOW_TH_20_NRX2_C_M 0xF0000
#define SEG0R_DCFI_LOW_TH_40_NRX1_C 0x480C
#define SEG0R_DCFI_LOW_TH_40_NRX1_C_M 0xF00000
#define SEG0R_DCFI_LOW_TH_40_NRX2_C 0x480C
#define SEG0R_DCFI_LOW_TH_40_NRX2_C_M 0xF000000
#define SEG0R_DCFI_LOW_TH_80_NRX1_C 0x480C
#define SEG0R_DCFI_LOW_TH_80_NRX1_C_M 0xF0000000
#define SEG0R_DCFI_LOW_TH_80_NRX2_C 0x4810
#define SEG0R_DCFI_LOW_TH_80_NRX2_C_M 0xF
#define SEG0R_DCFI_LOW_TH_80P80_NRX1_C 0x4810
#define SEG0R_DCFI_LOW_TH_80P80_NRX1_C_M 0xF0
#define SEG0R_DCFI_LOW_TH_80P80_NRX2_C 0x4810
#define SEG0R_DCFI_LOW_TH_80P80_NRX2_C_M 0xF00
#define SEG0R_DCFI_REF_COUNT_MAX_C 0x4810
#define SEG0R_DCFI_REF_COUNT_MAX_C_M 0xF000
#define SEG0R_DCFI_TH_OFST_C 0x4810
#define SEG0R_DCFI_TH_OFST_C_M 0xF0000
#define SEG0R_DCPR_HIGH_TH_20_NRX1_C 0x4810
#define SEG0R_DCPR_HIGH_TH_20_NRX1_C_M 0xF00000
#define SEG0R_DCPR_HIGH_TH_20_NRX2_C 0x4810
#define SEG0R_DCPR_HIGH_TH_20_NRX2_C_M 0xF000000
#define SEG0R_DCPR_HIGH_TH_40_NRX1_C 0x4810
#define SEG0R_DCPR_HIGH_TH_40_NRX1_C_M 0xF0000000
#define SEG0R_DCPR_HIGH_TH_40_NRX2_C 0x4814
#define SEG0R_DCPR_HIGH_TH_40_NRX2_C_M 0xF
#define SEG0R_DCPR_HIGH_TH_80_NRX1_C 0x4814
#define SEG0R_DCPR_HIGH_TH_80_NRX1_C_M 0xF0
#define SEG0R_DCPR_HIGH_TH_80_NRX2_C 0x4814
#define SEG0R_DCPR_HIGH_TH_80_NRX2_C_M 0xF00
#define SEG0R_DCPR_HIGH_TH_80P80_NRX1_C 0x4814
#define SEG0R_DCPR_HIGH_TH_80P80_NRX1_C_M 0xF000
#define SEG0R_DCPR_HIGH_TH_80P80_NRX2_C 0x4814
#define SEG0R_DCPR_HIGH_TH_80P80_NRX2_C_M 0xF0000
#define SEG0R_DCPR_LOW_TH_20_NRX1_C 0x4814
#define SEG0R_DCPR_LOW_TH_20_NRX1_C_M 0xF00000
#define SEG0R_DCPR_LOW_TH_20_NRX2_C 0x4814
#define SEG0R_DCPR_LOW_TH_20_NRX2_C_M 0xF000000
#define SEG0R_DCPR_LOW_TH_40_NRX1_C 0x4814
#define SEG0R_DCPR_LOW_TH_40_NRX1_C_M 0xF0000000
#define SEG0R_DCPR_LOW_TH_40_NRX2_C 0x4818
#define SEG0R_DCPR_LOW_TH_40_NRX2_C_M 0xF
#define SEG0R_DCPR_LOW_TH_80_NRX1_C 0x4818
#define SEG0R_DCPR_LOW_TH_80_NRX1_C_M 0xF0
#define SEG0R_DCPR_LOW_TH_80_NRX2_C 0x4818
#define SEG0R_DCPR_LOW_TH_80_NRX2_C_M 0xF00
#define SEG0R_DCPR_LOW_TH_80P80_NRX1_C 0x4818
#define SEG0R_DCPR_LOW_TH_80P80_NRX1_C_M 0xF000
#define SEG0R_DCPR_LOW_TH_80P80_NRX2_C 0x4818
#define SEG0R_DCPR_LOW_TH_80P80_NRX2_C_M 0xF0000
#define SEG0R_DCPR_RST_TH_C 0x4818
#define SEG0R_DCPR_RST_TH_C_M 0xF00000
#define SEG0R_DCPR_COUNT_MAX_C 0x4818
#define SEG0R_DCPR_COUNT_MAX_C_M 0x3000000
#define SEG0R_DCPR_RESEARCH_COUNT_MAX_C 0x4818
#define SEG0R_DCPR_RESEARCH_COUNT_MAX_C_M 0xC000000
#define SEG0R_DCPR_RST_COUNT_MAX_C 0x4818
#define SEG0R_DCPR_RST_COUNT_MAX_C_M 0x30000000
#define SEG0R_CBW20_LOW_PIN_TH_FINE_TUNE_C 0x481C
#define SEG0R_CBW20_LOW_PIN_TH_FINE_TUNE_C_M 0x1F
#define SEG0R_CBW40_LOW_PIN_TH_FINE_TUNE_C 0x481C
#define SEG0R_CBW40_LOW_PIN_TH_FINE_TUNE_C_M 0x3E0
#define SEG0R_CBW80_LOW_PIN_TH_FINE_TUNE_C 0x481C
#define SEG0R_CBW80_LOW_PIN_TH_FINE_TUNE_C_M 0x7C00
#define SEG0R_CBW80P80_LOW_PIN_TH_FINE_TUNE_C 0x481C
#define SEG0R_CBW80P80_LOW_PIN_TH_FINE_TUNE_C_M 0xF8000
#define SEG0R_FINE_TUNE_STOP_LMT_C 0x481C
#define SEG0R_FINE_TUNE_STOP_LMT_C_M 0x1F00000
#define SEG0R_CBW20_DC_MAX_RATIO_C 0x481C
#define SEG0R_CBW20_DC_MAX_RATIO_C_M 0x1E000000
#define SEG0R_FINE_TUNE_DELTA_C 0x481C
#define SEG0R_FINE_TUNE_DELTA_C_M 0xE0000000
#define SEG0R_CBW40_DC_MAX_RATIO_C 0x4820
#define SEG0R_CBW40_DC_MAX_RATIO_C_M 0xF
#define SEG0R_CBW80_DC_MAX_RATIO_C 0x4820
#define SEG0R_CBW80_DC_MAX_RATIO_C_M 0xF0
#define SEG0R_CBW80P80_DC_MAX_RATIO_C 0x4820
#define SEG0R_CBW80P80_DC_MAX_RATIO_C_M 0xF00
#define SEG0R_DC_MAX_RATIO_20_NRX1_C 0x4820
#define SEG0R_DC_MAX_RATIO_20_NRX1_C_M 0xF000
#define SEG0R_DC_MAX_RATIO_20_NRX2_C 0x4820
#define SEG0R_DC_MAX_RATIO_20_NRX2_C_M 0xF0000
#define SEG0R_DC_MAX_RATIO_40_NRX1_C 0x4820
#define SEG0R_DC_MAX_RATIO_40_NRX1_C_M 0xF00000
#define SEG0R_DC_MAX_RATIO_40_NRX2_C 0x4820
#define SEG0R_DC_MAX_RATIO_40_NRX2_C_M 0xF000000
#define SEG0R_DC_MAX_RATIO_80_NRX1_C 0x4820
#define SEG0R_DC_MAX_RATIO_80_NRX1_C_M 0xF0000000
#define SEG0R_DC_MAX_RATIO_80_NRX2_C 0x4824
#define SEG0R_DC_MAX_RATIO_80_NRX2_C_M 0xF
#define SEG0R_DC_MAX_RATIO_80P80_NRX1_C 0x4824
#define SEG0R_DC_MAX_RATIO_80P80_NRX1_C_M 0xF0
#define SEG0R_DC_MAX_RATIO_80P80_NRX2_C 0x4824
#define SEG0R_DC_MAX_RATIO_80P80_NRX2_C_M 0xF00
#define SEG0R_FINE_TUNE_LMT_C 0x4824
#define SEG0R_FINE_TUNE_LMT_C_M 0xF000
#define SEG0R_FINE_TUNE_PROCESS_DELAY_C 0x4824
#define SEG0R_FINE_TUNE_PROCESS_DELAY_C_M 0xF0000
#define SEG0R_FINE_TUNE_STEP_BY_CDD_DETECT_C 0x4824
#define SEG0R_FINE_TUNE_STEP_BY_CDD_DETECT_C_M 0xF00000
#define SEG0R_FINE_TUNE_TRUNC_HIGH_TH_C 0x4824
#define SEG0R_FINE_TUNE_TRUNC_HIGH_TH_C_M 0xF000000
#define SEG0R_FINE_TUNE_TRUNC_LOW_TH_C 0x4824
#define SEG0R_FINE_TUNE_TRUNC_LOW_TH_C_M 0xF0000000
#define SEG0R_FINE_TUNE_OPT_C 0x4828
#define SEG0R_FINE_TUNE_OPT_C_M 0x3
#define SEG0R_FINE_TUNE_TRUNC_EN_C 0x4828
#define SEG0R_FINE_TUNE_TRUNC_EN_C_M 0x4
#define SEG0R_FORCE_CDD_REFINE_OFF_C 0x4828
#define SEG0R_FORCE_CDD_REFINE_OFF_C_M 0x8
#define P20_SEG0R_L1_L2_AVG_START_TIME_C 0x482C
#define P20_SEG0R_L1_L2_AVG_START_TIME_C_M 0x3
#define P20_SEG0R_L1_L2_ALLOW_AVG_EN_C 0x482C
#define P20_SEG0R_L1_L2_ALLOW_AVG_EN_C_M 0x4
#define P20_SEG0R_L1_L2_AVG_OPT_C 0x482C
#define P20_SEG0R_L1_L2_AVG_OPT_C_M 0x8
#define S20_SEG0R_L1_L2_AVG_START_TIME_C 0x4830
#define S20_SEG0R_L1_L2_AVG_START_TIME_C_M 0x3
#define S20_SEG0R_L1_L2_ALLOW_AVG_EN_C 0x4830
#define S20_SEG0R_L1_L2_ALLOW_AVG_EN_C_M 0x4
#define S20_SEG0R_L1_L2_AVG_OPT_C 0x4830
#define S20_SEG0R_L1_L2_AVG_OPT_C_M 0x8
#define PROCSEG0R_ADV_SINR_WGT_20_NRX1_C 0x4834
#define PROCSEG0R_ADV_SINR_WGT_20_NRX1_C_M 0x7FF
#define PROCSEG0R_ADV_SINR_WGT_20_NRX2_C 0x4834
#define PROCSEG0R_ADV_SINR_WGT_20_NRX2_C_M 0x3FF800
#define PROCSEG0R_ADV_SINR_TH_C 0x4834
#define PROCSEG0R_ADV_SINR_TH_C_M 0x3FC00000
#define PROCSEG0R_CH_AVG_SIZE_C 0x4834
#define PROCSEG0R_CH_AVG_SIZE_C_M 0xC0000000
#define PROCSEG0R_ADV_SINR_WGT_40_NRX1_C 0x4838
#define PROCSEG0R_ADV_SINR_WGT_40_NRX1_C_M 0x7FF
#define PROCSEG0R_ADV_SINR_WGT_40_NRX2_C 0x4838
#define PROCSEG0R_ADV_SINR_WGT_40_NRX2_C_M 0x3FF800
#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX1_C 0x4838
#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX1_C_M 0x7C00000
#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX2_C 0x4838
#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX2_C_M 0xF8000000
#define PROCSEG0R_ADV_SINR_WGT_80_NRX1_C 0x483C
#define PROCSEG0R_ADV_SINR_WGT_80_NRX1_C_M 0x7FF
#define PROCSEG0R_ADV_SINR_WGT_80_NRX2_C 0x483C
#define PROCSEG0R_ADV_SINR_WGT_80_NRX2_C_M 0x3FF800
#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX1_C 0x483C
#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX1_C_M 0x7C00000
#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX2_C 0x483C
#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX2_C_M 0xF8000000
#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX1_C 0x4840
#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX1_C_M 0x7FF
#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX2_C 0x4840
#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX2_C_M 0x3FF800
#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX1_C 0x4840
#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX1_C_M 0x7C00000
#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX2_C 0x4840
#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX2_C_M 0xF8000000
#define PROCSEG0R_INT_SINR_WGT_20_NRX1_C 0x4844
#define PROCSEG0R_INT_SINR_WGT_20_NRX1_C_M 0x7FF
#define PROCSEG0R_INT_SINR_WGT_20_NRX2_C 0x4844
#define PROCSEG0R_INT_SINR_WGT_20_NRX2_C_M 0x3FF800
#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX1_C 0x4844
#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX1_C_M 0x7C00000
#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX2_C 0x4844
#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX2_C_M 0xF8000000
#define PROCSEG0R_INT_SINR_WGT_40_NRX1_C 0x4848
#define PROCSEG0R_INT_SINR_WGT_40_NRX1_C_M 0x7FF
#define PROCSEG0R_INT_SINR_WGT_40_NRX2_C 0x4848
#define PROCSEG0R_INT_SINR_WGT_40_NRX2_C_M 0x3FF800
#define PROCSEG0R_SBD_FAIL_HALF_SYM_COUNT_C 0x4848
#define PROCSEG0R_SBD_FAIL_HALF_SYM_COUNT_C_M 0x7C00000
#define PROCSEG0R_CBW20_HIGH_PIN_TH_MAX_SINR_C 0x4848
#define PROCSEG0R_CBW20_HIGH_PIN_TH_MAX_SINR_C_M 0xF8000000
#define PROCSEG0R_INT_SINR_WGT_80_NRX1_C 0x484C
#define PROCSEG0R_INT_SINR_WGT_80_NRX1_C_M 0x7FF
#define PROCSEG0R_INT_SINR_WGT_80_NRX2_C 0x484C
#define PROCSEG0R_INT_SINR_WGT_80_NRX2_C_M 0x3FF800
#define PROCSEG0R_CBW40_HIGH_PIN_TH_MAX_SINR_C 0x484C
#define PROCSEG0R_CBW40_HIGH_PIN_TH_MAX_SINR_C_M 0x7C00000
#define PROCSEG0R_CBW80_HIGH_PIN_TH_MAX_SINR_C 0x484C
#define PROCSEG0R_CBW80_HIGH_PIN_TH_MAX_SINR_C_M 0xF8000000
#define PROCSEG0R_INT_SINR_WGT_80P80_NRX1_C 0x4850
#define PROCSEG0R_INT_SINR_WGT_80P80_NRX1_C_M 0x7FF
#define PROCSEG0R_INT_SINR_WGT_80P80_NRX2_C 0x4850
#define PROCSEG0R_INT_SINR_WGT_80P80_NRX2_C_M 0x3FF800
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX1_C 0x4850
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX1_C_M 0x7C00000
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX2_C 0x4850
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX2_C_M 0xF8000000
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX1_C 0x4854
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX1_C_M 0x1F
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX2_C 0x4854
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX2_C_M 0x3E0
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX1_C 0x4854
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX1_C_M 0x7C00
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX2_C 0x4854
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX2_C_M 0xF8000
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX1_C 0x4854
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX1_C_M 0x1F00000
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX2_C 0x4854
#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX2_C_M 0x3E000000
#define PROCSEG0R_CDD0_SUB_TUNE_OPT_C 0x4854
#define PROCSEG0R_CDD0_SUB_TUNE_OPT_C_M 0x40000000
#define PROCSEG0R_CR_SWITCH_BY_ACI_EN_C 0x4854
#define PROCSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x80000000
#define PROCSEG0R_FS_WGT_OFST_0_C 0x4858
#define PROCSEG0R_FS_WGT_OFST_0_C_M 0xF
#define PROCSEG0R_FS_WGT_OFST_1_C 0x4858
#define PROCSEG0R_FS_WGT_OFST_1_C_M 0xF0
#define PROCSEG0R_L1_L2_PROCESS_DELAY_C 0x4858
#define PROCSEG0R_L1_L2_PROCESS_DELAY_C_M 0xF00
#define PROCSEG0R_SBD_START_HALF_SYM_COUNT_C 0x4858
#define PROCSEG0R_SBD_START_HALF_SYM_COUNT_C_M 0xF000
#define PROCSEG0R_CDD0_JUMP_SUB_TUNE_C 0x4858
#define PROCSEG0R_CDD0_JUMP_SUB_TUNE_C_M 0xF0000
#define PROCSEG0R_CDD0_WGT_OFST_0_C 0x4858
#define PROCSEG0R_CDD0_WGT_OFST_0_C_M 0xF00000
#define PROCSEG0R_CDD0_WGT_OFST_1_C 0x4858
#define PROCSEG0R_CDD0_WGT_OFST_1_C_M 0xF000000
#define PROCSEG0R_CH_BEGIN_COUNT_MAX_C 0x4858
#define PROCSEG0R_CH_BEGIN_COUNT_MAX_C_M 0xF0000000
#define PROCSEG0R_CH_FALLING_COUNT_MAX_C 0x485C
#define PROCSEG0R_CH_FALLING_COUNT_MAX_C_M 0xF
#define PROCSEG0R_INTF_TH_0_C 0x485C
#define PROCSEG0R_INTF_TH_0_C_M 0xF0
#define PROCSEG0R_INTF_TH_1_C 0x485C
#define PROCSEG0R_INTF_TH_1_C_M 0xF00
#define PROCSEG0R_TARGET_COUNT_MAX_C 0x485C
#define PROCSEG0R_TARGET_COUNT_MAX_C_M 0xF000
#define PROCSEG0R_FS_PEAK_WGT_C 0x485C
#define PROCSEG0R_FS_PEAK_WGT_C_M 0x70000
#define PROCSEG0R_CDD0_COUNT_LMT_C 0x485C
#define PROCSEG0R_CDD0_COUNT_LMT_C_M 0x380000
#define PROCSEG0R_CDD0_DELAY_SPREAD_SIZE_C 0x485C
#define PROCSEG0R_CDD0_DELAY_SPREAD_SIZE_C_M 0x1C00000
#define PROCSEG0R_CH_BEGIN_TH_C 0x485C
#define PROCSEG0R_CH_BEGIN_TH_C_M 0xE000000
#define PROCSEG0R_CR_SWITCH_BY_PIN_C 0x485C
#define PROCSEG0R_CR_SWITCH_BY_PIN_C_M 0x70000000
#define SEG0R_PW_TH_C 0x4860
#define SEG0R_PW_TH_C_M 0x3F
#define SEG0R_PD_LOWER_BOUND_C 0x4860
#define SEG0R_PD_LOWER_BOUND_C_M 0x7C0
#define SEG0R_PD_UPPER_BOUND_C 0x4860
#define SEG0R_PD_UPPER_BOUND_C_M 0xF800
#define SEG0R_HIGH_PIN_TH_DCFI_C 0x4860
#define SEG0R_HIGH_PIN_TH_DCFI_C_M 0x1F0000
#define SEG0R_VERY_HIGH_PIN_TH_C 0x4860
#define SEG0R_VERY_HIGH_PIN_TH_C_M 0x3E00000
#define SEG0R_DCFI_FALLING_TH_20_C 0x4860
#define SEG0R_DCFI_FALLING_TH_20_C_M 0x3C000000
#define SEG0R_PD_SPATIAL_REUSE_EN_C 0x4860
#define SEG0R_PD_SPATIAL_REUSE_EN_C_M 0x40000000
#define SEG0R_DCFI_EN_C 0x4860
#define SEG0R_DCFI_EN_C_M 0x80000000
#define SEG0R_DCFI_FALLING_TH_40_C 0x4864
#define SEG0R_DCFI_FALLING_TH_40_C_M 0xF
#define SEG0R_DCFI_FALLING_TH_80_C 0x4864
#define SEG0R_DCFI_FALLING_TH_80_C_M 0xF0
#define SEG0R_DCFI_FALLING_TH_80P80_C 0x4864
#define SEG0R_DCFI_FALLING_TH_80P80_C_M 0xF00
#define SEG0R_DCFI_RISING_TH_20_C 0x4864
#define SEG0R_DCFI_RISING_TH_20_C_M 0xF000
#define SEG0R_DCFI_RISING_TH_40_C 0x4864
#define SEG0R_DCFI_RISING_TH_40_C_M 0xF0000
#define SEG0R_DCFI_RISING_TH_80_C 0x4864
#define SEG0R_DCFI_RISING_TH_80_C_M 0xF00000
#define SEG0R_DCFI_RISING_TH_80P80_C 0x4864
#define SEG0R_DCFI_RISING_TH_80P80_C_M 0xF000000
#define SEG0R_FALLING_COUNT_MAX_C 0x4864
#define SEG0R_FALLING_COUNT_MAX_C_M 0xF0000000
#define SEG0R_FALLING_TH_C 0x4868
#define SEG0R_FALLING_TH_C_M 0xF
#define SEG0R_RISING_COUNT_MAX_C 0x4868
#define SEG0R_RISING_COUNT_MAX_C_M 0xF0
#define SEG0R_WAIT_SETTLE_PERIOD_C 0x4868
#define SEG0R_WAIT_SETTLE_PERIOD_C_M 0xF00
#define SEG0R_DCPR_EN_C 0x4868
#define SEG0R_DCPR_EN_C_M 0x1000
#define SEG0R_DYN_PW_EN_C 0x4868
#define SEG0R_DYN_PW_EN_C_M 0x2000
#define SEG0R_FALLING_EDGE_OPT_C 0x4868
#define SEG0R_FALLING_EDGE_OPT_C_M 0x4000
#define SEG0R_FORCE_DCFI_EN_C 0x4868
#define SEG0R_FORCE_DCFI_EN_C_M 0x8000
#define SEG0R_SB5M_BLK_EN_C 0x4868
#define SEG0R_SB5M_BLK_EN_C_M 0x10000
#define P20_SEG0R_PW_DBM_TH_C 0x486C
#define P20_SEG0R_PW_DBM_TH_C_M 0x7F
#define P20_SEG0R_PW_TH_C 0x486C
#define P20_SEG0R_PW_TH_C_M 0x1F80
#define P20_SEG0R_DYN_FALLING_TH_C 0x486C
#define P20_SEG0R_DYN_FALLING_TH_C_M 0x7E000
#define P20_SEG0R_DYN_RISING_TH_C 0x486C
#define P20_SEG0R_DYN_RISING_TH_C_M 0x1F80000
#define P20_SEG0R_DYN_TH_MAX_C 0x486C
#define P20_SEG0R_DYN_TH_MAX_C_M 0x7E000000
#define P20_SEG0R_DYN_TH_EN_C 0x486C
#define P20_SEG0R_DYN_TH_EN_C_M 0x80000000
#define P20_SEG0R_DYN_TH_MIN_C 0x4870
#define P20_SEG0R_DYN_TH_MIN_C_M 0x3F
#define P20_SEG0R_DYN_COVER_FCTR_C 0x4870
#define P20_SEG0R_DYN_COVER_FCTR_C_M 0x3C0
#define P20_SEG0R_DYN_LAMBDA_C 0x4870
#define P20_SEG0R_DYN_LAMBDA_C_M 0x1C00
#define P20_SEG0R_DYN_WAIT_PERIOD_C 0x4870
#define P20_SEG0R_DYN_WAIT_PERIOD_C_M 0xE000
#define P20_SEG0R_VLD_CHK_COUNT_MAX_C 0x4870
#define P20_SEG0R_VLD_CHK_COUNT_MAX_C_M 0x70000
#define P20_SEG0R_DYN_OBSER_SIZE_C 0x4870
#define P20_SEG0R_DYN_OBSER_SIZE_C_M 0x180000
#define P20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C 0x4870
#define P20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C_M 0x600000
#define P20_SEG0R_PATH_SEL_C 0x4870
#define P20_SEG0R_PATH_SEL_C_M 0x1800000
#define P20_SEG0R_PATH_SEL_EN_C 0x4870
#define P20_SEG0R_PATH_SEL_EN_C_M 0x2000000
#define S20_SEG0R_PW_DBM_TH_C 0x4874
#define S20_SEG0R_PW_DBM_TH_C_M 0x7F
#define S20_SEG0R_PW_TH_C 0x4874
#define S20_SEG0R_PW_TH_C_M 0x1F80
#define S20_SEG0R_DYN_FALLING_TH_C 0x4874
#define S20_SEG0R_DYN_FALLING_TH_C_M 0x7E000
#define S20_SEG0R_DYN_RISING_TH_C 0x4874
#define S20_SEG0R_DYN_RISING_TH_C_M 0x1F80000
#define S20_SEG0R_DYN_TH_MAX_C 0x4874
#define S20_SEG0R_DYN_TH_MAX_C_M 0x7E000000
#define S20_SEG0R_DYN_TH_EN_C 0x4874
#define S20_SEG0R_DYN_TH_EN_C_M 0x80000000
#define S20_SEG0R_DYN_TH_MIN_C 0x4878
#define S20_SEG0R_DYN_TH_MIN_C_M 0x3F
#define S20_SEG0R_DYN_COVER_FCTR_C 0x4878
#define S20_SEG0R_DYN_COVER_FCTR_C_M 0x3C0
#define S20_SEG0R_DYN_LAMBDA_C 0x4878
#define S20_SEG0R_DYN_LAMBDA_C_M 0x1C00
#define S20_SEG0R_DYN_WAIT_PERIOD_C 0x4878
#define S20_SEG0R_DYN_WAIT_PERIOD_C_M 0xE000
#define S20_SEG0R_VLD_CHK_COUNT_MAX_C 0x4878
#define S20_SEG0R_VLD_CHK_COUNT_MAX_C_M 0x70000
#define S20_SEG0R_DYN_OBSER_SIZE_C 0x4878
#define S20_SEG0R_DYN_OBSER_SIZE_C_M 0x180000
#define S20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C 0x4878
#define S20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C_M 0x600000
#define S20_SEG0R_PATH_SEL_C 0x4878
#define S20_SEG0R_PATH_SEL_C_M 0x1800000
#define S20_SEG0R_PATH_SEL_EN_C 0x4878
#define S20_SEG0R_PATH_SEL_EN_C_M 0x2000000
#define SMFSEG0R_MF_TH_OFST_0_C 0x487C
#define SMFSEG0R_MF_TH_OFST_0_C_M 0xF
#define SMFSEG0R_MF_TH_OFST_1_C 0x487C
#define SMFSEG0R_MF_TH_OFST_1_C_M 0xF0
#define SMFSEG0R_MF_TH_20_NRX1_C 0x487C
#define SMFSEG0R_MF_TH_20_NRX1_C_M 0xF00
#define SMFSEG0R_MF_TH_20_NRX2_C 0x487C
#define SMFSEG0R_MF_TH_20_NRX2_C_M 0xF000
#define SMFSEG0R_MF_TH_40_NRX1_C 0x487C
#define SMFSEG0R_MF_TH_40_NRX1_C_M 0xF0000
#define SMFSEG0R_MF_TH_40_NRX2_C 0x487C
#define SMFSEG0R_MF_TH_40_NRX2_C_M 0xF00000
#define SMFSEG0R_MF_TH_80_NRX1_C 0x487C
#define SMFSEG0R_MF_TH_80_NRX1_C_M 0xF000000
#define SMFSEG0R_MF_TH_80_NRX2_C 0x487C
#define SMFSEG0R_MF_TH_80_NRX2_C_M 0xF0000000
#define SMFSEG0R_MF_TH_80P80_NRX1_C 0x4880
#define SMFSEG0R_MF_TH_80P80_NRX1_C_M 0xF
#define SMFSEG0R_MF_TH_80P80_NRX2_C 0x4880
#define SMFSEG0R_MF_TH_80P80_NRX2_C_M 0xF0
#define SMFSEG0R_INTF_TH_0_C 0x4880
#define SMFSEG0R_INTF_TH_0_C_M 0xF00
#define SMFSEG0R_INTF_TH_1_C 0x4880
#define SMFSEG0R_INTF_TH_1_C_M 0xF000
#define SMFSEG0R_MF_HOLD_C 0x4880
#define SMFSEG0R_MF_HOLD_C_M 0x70000
#define SMFSEG0R_MF_WIN_L_C 0x4880
#define SMFSEG0R_MF_WIN_L_C_M 0x380000
#define SMFSEG0R_CR_SWITCH_BY_PIN_C 0x4880
#define SMFSEG0R_CR_SWITCH_BY_PIN_C_M 0x1C00000
#define SMFSEG0R_MF_PEAK_OPT_C 0x4880
#define SMFSEG0R_MF_PEAK_OPT_C_M 0x6000000
#define SMFSEG0R_NULL_POINT_IDX_C 0x4880
#define SMFSEG0R_NULL_POINT_IDX_C_M 0x18000000
#define SMFSEG0R_CR_SWITCH_BY_ACI_EN_C 0x4880
#define SMFSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x20000000
#define SEG0R_EDCCA_LVL_C 0x4884
#define SEG0R_EDCCA_LVL_C_M 0xFF
#define SEG0R_EDCCA_LVL_P_C 0x4884
#define SEG0R_EDCCA_LVL_P_C_M 0xFF00
#define SEG0R_OBSS_LVL_C 0x4884
#define SEG0R_OBSS_LVL_C_M 0xFF0000
#define SEG0R_PPDU_LVL_C 0x4884
#define SEG0R_PPDU_LVL_C_M 0xFF000000
#define SEG0R_PPDU_LVL_P_C 0x4888
#define SEG0R_PPDU_LVL_P_C_M 0xFF
#define SEG0R_DCV_C 0x4888
#define SEG0R_DCV_C_M 0x7F00
#define SEG0R_PWLMT_C 0x4888
#define SEG0R_PWLMT_C_M 0x3F8000
#define SEG0R_WGTHD_C 0x4888
#define SEG0R_WGTHD_C_M 0x1FC00000
#define SEG0R_PATHSEL_C 0x4888
#define SEG0R_PATHSEL_C_M 0x60000000
#define SEG0R_DROP_EN_C 0x4888
#define SEG0R_DROP_EN_C_M 0x80000000
#define SEG0R_ADCPKPW_C 0x488C
#define SEG0R_ADCPKPW_C_M 0x3F
#define SEG0R_LTFTHD_C 0x488C
#define SEG0R_LTFTHD_C_M 0xFC0
#define SEG0R_DWN_LVL_C 0x488C
#define SEG0R_DWN_LVL_C_M 0x1F000
#define SEG0R_PWOFST_C 0x488C
#define SEG0R_PWOFST_C_M 0x3E0000
#define SEG0R_DROP_NC_C 0x488C
#define SEG0R_DROP_NC_C_M 0x3C00000
#define SEG0R_FORCE_EN_C 0x488C
#define SEG0R_FORCE_EN_C_M 0x4000000
#define SEG0R_FORGETTING_C 0x488C
#define SEG0R_FORGETTING_C_M 0x8000000
#define SEG0R_GCRST_C 0x488C
#define SEG0R_GCRST_C_M 0x10000000
#define SEG0R_PWSLOT_C 0x488C
#define SEG0R_PWSLOT_C_M 0x20000000
#define SEG0R_SND_EN_C 0x488C
#define SEG0R_SND_EN_C_M 0x40000000
#define SEG0R_WGTSEL_EN_C 0x488C
#define SEG0R_WGTSEL_EN_C_M 0x80000000
#define SEG0R_SDAGC_CHK_PIN_THD_C 0x4890
#define SEG0R_SDAGC_CHK_PIN_THD_C_M 0x3F
#define SEG0R_ALPHA_STEP_C 0x4890
#define SEG0R_ALPHA_STEP_C_M 0xC0
#define SEG0R_CBW40_RSSI_SHIFT_C 0x4890
#define SEG0R_CBW40_RSSI_SHIFT_C_M 0x300
#define SEG0R_CBW80_RSSI_SHIFT_C 0x4890
#define SEG0R_CBW80_RSSI_SHIFT_C_M 0xC00
#define SEG0R_ALPHA_FILTER_EN_C 0x4890
#define SEG0R_ALPHA_FILTER_EN_C_M 0x1000
#define SEG0R_LTF_RSSI_CMP_EN_C 0x4890
#define SEG0R_LTF_RSSI_CMP_EN_C_M 0x2000
#define SEG0R_PD_RSSI_CMP_EN_C 0x4890
#define SEG0R_PD_RSSI_CMP_EN_C_M 0x4000
#define SEG0R_SDAGC_CHK_PIN_EN_C 0x4890
#define SEG0R_SDAGC_CHK_PIN_EN_C_M 0x8000
#define SEG0R_COMB_WGT_C 0x4894
#define SEG0R_COMB_WGT_C_M 0xF
#define L_NOISE_VAR_PER_RX_R0_C 0x4958
#define L_NOISE_VAR_PER_RX_R0_C_M 0x3FFFF
#define MANUAL_NOISE_RESCAL_FCTR_R0_C 0x4958
#define MANUAL_NOISE_RESCAL_FCTR_R0_C_M 0x7FFC0000
#define FD_ANT_WGT_EN_C 0x4958
#define FD_ANT_WGT_EN_C_M 0x80000000
#define L_NOISE_VAR_PER_RX_R1_C 0x495C
#define L_NOISE_VAR_PER_RX_R1_C_M 0x3FFFF
#define MANUAL_NOISE_RESCAL_FCTR_R1_C 0x495C
#define MANUAL_NOISE_RESCAL_FCTR_R1_C_M 0x7FFC0000
#define FD_PW_NORM_EN_C 0x495C
#define FD_PW_NORM_EN_C_M 0x80000000
#define NOISE_VAR_PER_RX_R0_C 0x4960
#define NOISE_VAR_PER_RX_R0_C_M 0x3FFFF
#define NOISE_VAR_PER_RX_DB_THD_C 0x4960
#define NOISE_VAR_PER_RX_DB_THD_C_M 0x3FFC0000
#define RPL_CAL_EN_C 0x4960
#define RPL_CAL_EN_C_M 0x40000000
#define TB_RSSI_M_CAL_EN_C 0x4960
#define TB_RSSI_M_CAL_EN_C_M 0x80000000
#define NOISE_VAR_PER_RX_R1_C 0x4964
#define NOISE_VAR_PER_RX_R1_C_M 0x3FFFF
#define PER_RX_DIFF_MAX_NOISE_PW_THD_C 0x4964
#define PER_RX_DIFF_MAX_NOISE_PW_THD_C_M 0x3FFC0000
#define ANT_WGT_MANUAL_EN_C 0x4964
#define ANT_WGT_MANUAL_EN_C_M 0x40000000
#define ANT_WGT_NORMALIZE_MODE_EN_C 0x4964
#define ANT_WGT_NORMALIZE_MODE_EN_C_M 0x80000000
#define FD_AMP_WGT_LEG_R0_C 0x4968
#define FD_AMP_WGT_LEG_R0_C_M 0xFFFF
#define FD_AMP_WGT_LEG_R1_C 0x4968
#define FD_AMP_WGT_LEG_R1_C_M 0xFFFF0000
#define FD_AMP_WGT_NON_LEG_R0_C 0x496C
#define FD_AMP_WGT_NON_LEG_R0_C_M 0xFFFF
#define FD_AMP_WGT_NON_LEG_R1_C 0x496C
#define FD_AMP_WGT_NON_LEG_R1_C_M 0xFFFF0000
#define L_SNR_ALL_COMB_C 0x4978
#define L_SNR_ALL_COMB_C_M 0x3FF
#define L_SNR_PER_RX_R0_C 0x4978
#define L_SNR_PER_RX_R0_C_M 0xFFC00
#define L_SNR_PER_RX_R1_C 0x4978
#define L_SNR_PER_RX_R1_C_M 0x3FF00000
#define MANUAL_FD_AMP_WGT_EN_C 0x4978
#define MANUAL_FD_AMP_WGT_EN_C_M 0x40000000
#define MANUAL_SNR_EN_C 0x4978
#define MANUAL_SNR_EN_C_M 0x80000000
#define SNR_ALL_COMB_C 0x497C
#define SNR_ALL_COMB_C_M 0x3FF
#define SNR_PER_RX_STS_R0_S0_C 0x497C
#define SNR_PER_RX_STS_R0_S0_C_M 0xFFC00
#define SNR_PER_RX_STS_R0_S1_C 0x497C
#define SNR_PER_RX_STS_R0_S1_C_M 0x3FF00000
#define MANUAL_NOISE_RESCAL_EN_C 0x497C
#define MANUAL_NOISE_RESCAL_EN_C_M 0x40000000
#define MANUAL_NOISE_VAR_EN_C 0x497C
#define MANUAL_NOISE_VAR_EN_C_M 0x80000000
#define SNR_PER_RX_STS_R1_S0_C 0x4980
#define SNR_PER_RX_STS_R1_S0_C_M 0x3FF
#define SNR_PER_RX_STS_R1_S1_C 0x4980
#define SNR_PER_RX_STS_R1_S1_C_M 0xFFC00
#define SNR_PER_RX_SUB_R0_S0_C 0x4980
#define SNR_PER_RX_SUB_R0_S0_C_M 0x3FF00000
#define NOISE_RESCAL_EN_C 0x4980
#define NOISE_RESCAL_EN_C_M 0x40000000
#define SNR_PER_RX_SUB_R0_S1_C 0x4984
#define SNR_PER_RX_SUB_R0_S1_C_M 0x3FF
#define SNR_PER_RX_SUB_R0_S2_C 0x4984
#define SNR_PER_RX_SUB_R0_S2_C_M 0xFFC00
#define SNR_PER_RX_SUB_R0_S3_C 0x4984
#define SNR_PER_RX_SUB_R0_S3_C_M 0x3FF00000
#define SNR_PER_RX_SUB_R1_S0_C 0x4988
#define SNR_PER_RX_SUB_R1_S0_C_M 0x3FF
#define SNR_PER_RX_SUB_R1_S1_C 0x4988
#define SNR_PER_RX_SUB_R1_S1_C_M 0xFFC00
#define SNR_PER_RX_SUB_R1_S2_C 0x4988
#define SNR_PER_RX_SUB_R1_S2_C_M 0x3FF00000
#define SNR_PER_RX_SUB_R1_S3_C 0x498C
#define SNR_PER_RX_SUB_R1_S3_C_M 0x3FF
#define SNR_PER_STS_S0_C 0x498C
#define SNR_PER_STS_S0_C_M 0xFFC00
#define SNR_PER_STS_S1_C 0x498C
#define SNR_PER_STS_S1_C_M 0x3FF00000
#define SNR_PER_SUB_S0_C 0x4990
#define SNR_PER_SUB_S0_C_M 0x3FF
#define SNR_PER_SUB_S1_C 0x4990
#define SNR_PER_SUB_S1_C_M 0xFFC00
#define SNR_PER_SUB_S2_C 0x4990
#define SNR_PER_SUB_S2_C_M 0x3FF00000
#define SNR_PER_SUB_S3_C 0x4994
#define SNR_PER_SUB_S3_C_M 0x3FF
#define RX_DB_SAME_THD_C 0x4994
#define RX_DB_SAME_THD_C_M 0x7FC00
#define ANT_WGT_MANUAL_RX0_C 0x4994
#define ANT_WGT_MANUAL_RX0_C_M 0xFF80000
#define ANT_WGT_MANUAL_RX1_C 0x4998
#define ANT_WGT_MANUAL_RX1_C_M 0x1FF
#define FORBT_FD_ANT_WGT_OFF_C 0x4998
#define FORBT_FD_ANT_WGT_OFF_C_M 0x3FE00
#define FORBT_FD_ANT_WGT_ON_C 0x4998
#define FORBT_FD_ANT_WGT_ON_C_M 0x7FC0000
#define DIFF_SAME_THD_C 0x499C
#define DIFF_SAME_THD_C_M 0x7F
#define RX_DB_DISCONNECT_THD_0_C 0x499C
#define RX_DB_DISCONNECT_THD_0_C_M 0x3F80
#define RX_DB_DISCONNECT_THD_1_C 0x499C
#define RX_DB_DISCONNECT_THD_1_C_M 0x1FC000
#define RX_DB_DISCONNECT_THD_2_C 0x499C
#define RX_DB_DISCONNECT_THD_2_C_M 0xFE00000
#define RX_DB_DISCONNECT_THD_3_C 0x49A0
#define RX_DB_DISCONNECT_THD_3_C_M 0x7F
#define RX_DB_DISCONNECT_THD_4_C 0x49A0
#define RX_DB_DISCONNECT_THD_4_C_M 0x3F80
#define RX_DB_DISCONNECT_THD_5_C 0x49A0
#define RX_DB_DISCONNECT_THD_5_C_M 0x1FC000
#define RX_DB_DISCONNECT_THD_6_C 0x49A0
#define RX_DB_DISCONNECT_THD_6_C_M 0xFE00000
#define ANT_WGT_NSS2_LOW_BOUND_C 0x49A4
#define ANT_WGT_NSS2_LOW_BOUND_C_M 0x7F
#define ANT_WGT_NSS2_LOW_BOUND_THD_C 0x49A4
#define ANT_WGT_NSS2_LOW_BOUND_THD_C_M 0x3F80
#define DISCONNECT_ANT_WGT_0_C 0x49A4
#define DISCONNECT_ANT_WGT_0_C_M 0x1FC000
#define DISCONNECT_ANT_WGT_1_C 0x49A4
#define DISCONNECT_ANT_WGT_1_C_M 0xFE00000
#define DISCONNECT_ANT_WGT_2_C 0x49A8
#define DISCONNECT_ANT_WGT_2_C_M 0x7F
#define DISCONNECT_ANT_WGT_3_C 0x49A8
#define DISCONNECT_ANT_WGT_3_C_M 0x3F80
#define DISCONNECT_ANT_WGT_4_C 0x49A8
#define DISCONNECT_ANT_WGT_4_C_M 0x1FC000
#define DISCONNECT_ANT_WGT_5_C 0x49A8
#define DISCONNECT_ANT_WGT_5_C_M 0xFE00000
#define DISCONNECT_ANT_WGT_6_C 0x49AC
#define DISCONNECT_ANT_WGT_6_C_M 0x7F
#define DISCONNECT_ANT_WGT_7_C 0x49AC
#define DISCONNECT_ANT_WGT_7_C_M 0x3F80
#define L_RPL_BIAS_COMP_C 0x49B0
#define L_RPL_BIAS_COMP_C_M 0xFF
#define L_RPL_BIAS_COMP_BW20_C 0x49B0
#define L_RPL_BIAS_COMP_BW20_C_M 0xFF00
#define L_RPL_BIAS_COMP_BW40_C 0x49B0
#define L_RPL_BIAS_COMP_BW40_C_M 0xFF0000
#define L_RPL_BIAS_COMP_BW40_1_C 0x49B0
#define L_RPL_BIAS_COMP_BW40_1_C_M 0xFF000000
#define L_RPL_BIAS_COMP_BW40_2_C 0x49B4
#define L_RPL_BIAS_COMP_BW40_2_C_M 0xFF
#define L_RPL_BIAS_COMP_BW80_C 0x49B4
#define L_RPL_BIAS_COMP_BW80_C_M 0xFF00
#define L_RPL_BIAS_COMP_BW80_1_C 0x49B4
#define L_RPL_BIAS_COMP_BW80_1_C_M 0xFF0000
#define L_RPL_BIAS_COMP_BW80_10_C 0x49B4
#define L_RPL_BIAS_COMP_BW80_10_C_M 0xFF000000
#define L_RPL_BIAS_COMP_BW80_2_C 0x49B8
#define L_RPL_BIAS_COMP_BW80_2_C_M 0xFF
#define L_RPL_BIAS_COMP_BW80_3_C 0x49B8
#define L_RPL_BIAS_COMP_BW80_3_C_M 0xFF00
#define L_RPL_BIAS_COMP_BW80_4_C 0x49B8
#define L_RPL_BIAS_COMP_BW80_4_C_M 0xFF0000
#define L_RPL_BIAS_COMP_BW80_9_C 0x49B8
#define L_RPL_BIAS_COMP_BW80_9_C_M 0xFF000000
#define DBCC_C 0x49BC
#define DBCC_C_M 0x1
#define DBCC_2P4G_BAND_SEL_C 0x49BC
#define DBCC_2P4G_BAND_SEL_C_M 0x2
#define NONCON160_C 0x49BC
#define NONCON160_C_M 0x4
#define FC0_INV_C 0x49C0
#define FC0_INV_C_M 0x7F
#define FC1_INV_C 0x49C0
#define FC1_INV_C_M 0x3F80
#define ANT_RX_1RCCA_SEG0_C 0x49C0
#define ANT_RX_1RCCA_SEG0_C_M 0x3C000
#define ANT_RX_1RCCA_SEG1_C 0x49C0
#define ANT_RX_1RCCA_SEG1_C_M 0x3C0000
#define ANT_RX_BT_SEG0_C 0x49C0
#define ANT_RX_BT_SEG0_C_M 0x3C00000
#define ANT_RX_BT_SEG1_C 0x49C0
#define ANT_RX_BT_SEG1_C_M 0x3C000000
#define BW_C 0x49C0
#define BW_C_M 0xC0000000
#define ANT_RX_SEG0_C 0x49C4
#define ANT_RX_SEG0_C_M 0xF
#define ANT_RX_SEG1_C 0x49C4
#define ANT_RX_SEG1_C_M 0xF0
#define PRICH_C 0x49C4
#define PRICH_C_M 0xF00
#define SMALL_BW_MODE_C 0x49C4
#define SMALL_BW_MODE_C_M 0x3000
#define BT_SHARE_C 0x49C4
#define BT_SHARE_C_M 0x4000
#define PROC0_PROCQ_MATRIX_00_IM_C 0x49C8
#define PROC0_PROCQ_MATRIX_00_IM_C_M 0xFFFF
#define PROC0_PROCQ_MATRIX_00_RE_C 0x49C8
#define PROC0_PROCQ_MATRIX_00_RE_C_M 0xFFFF0000
#define PROC0_PROCQ_MATRIX_01_IM_C 0x49CC
#define PROC0_PROCQ_MATRIX_01_IM_C_M 0xFFFF
#define PROC0_PROCQ_MATRIX_01_RE_C 0x49CC
#define PROC0_PROCQ_MATRIX_01_RE_C_M 0xFFFF0000
#define PROC0_PROCQ_MATRIX_10_IM_C 0x49D0
#define PROC0_PROCQ_MATRIX_10_IM_C_M 0xFFFF
#define PROC0_PROCQ_MATRIX_10_RE_C 0x49D0
#define PROC0_PROCQ_MATRIX_10_RE_C_M 0xFFFF0000
#define PROC0_PROCQ_MATRIX_11_IM_C 0x49D4
#define PROC0_PROCQ_MATRIX_11_IM_C_M 0xFFFF
#define PROC0_PROCQ_MATRIX_11_RE_C 0x49D4
#define PROC0_PROCQ_MATRIX_11_RE_C_M 0xFFFF0000
#define PROC0_PROCCUSTOMIZE_Q_MATRIX_EN_C 0x49D8
#define PROC0_PROCCUSTOMIZE_Q_MATRIX_EN_C_M 0x1
#define PRPC1_PROCQ_MATRIX_00_IM_C 0x49DC
#define PRPC1_PROCQ_MATRIX_00_IM_C_M 0xFFFF
#define PRPC1_PROCQ_MATRIX_00_RE_C 0x49DC
#define PRPC1_PROCQ_MATRIX_00_RE_C_M 0xFFFF0000
#define PRPC1_PROCQ_MATRIX_01_IM_C 0x49E0
#define PRPC1_PROCQ_MATRIX_01_IM_C_M 0xFFFF
#define PRPC1_PROCQ_MATRIX_01_RE_C 0x49E0
#define PRPC1_PROCQ_MATRIX_01_RE_C_M 0xFFFF0000
#define PRPC1_PROCQ_MATRIX_10_IM_C 0x49E4
#define PRPC1_PROCQ_MATRIX_10_IM_C_M 0xFFFF
#define PRPC1_PROCQ_MATRIX_10_RE_C 0x49E4
#define PRPC1_PROCQ_MATRIX_10_RE_C_M 0xFFFF0000
#define PRPC1_PROCQ_MATRIX_11_IM_C 0x49E8
#define PRPC1_PROCQ_MATRIX_11_IM_C_M 0xFFFF
#define PRPC1_PROCQ_MATRIX_11_RE_C 0x49E8
#define PRPC1_PROCQ_MATRIX_11_RE_C_M 0xFFFF0000
#define PRPC1_PROCCUSTOMIZE_Q_MATRIX_EN_C 0x49EC
#define PRPC1_PROCCUSTOMIZE_Q_MATRIX_EN_C_M 0x1
#define PATH1_R_P_PEAK_IBADC_DBM_C 0x49F0
#define PATH1_R_P_PEAK_IBADC_DBM_C_M 0x7F
#define PATH1_R_P_PEAK_WBADC_DBM_C 0x49F0
#define PATH1_R_P_PEAK_WBADC_DBM_C_M 0x3F80
#define PATH1_R_ACI_NRBW_TH_C 0x49F0
#define PATH1_R_ACI_NRBW_TH_C_M 0xFC000
#define PATH1_R_BACKOFF_BMODE_C 0x49F0
#define PATH1_R_BACKOFF_BMODE_C_M 0x3F00000
#define PATH1_R_BACKOFF_IBADC_C 0x49F0
#define PATH1_R_BACKOFF_IBADC_C_M 0xFC000000
#define PATH1_R_BACKOFF_LNA_C 0x49F4
#define PATH1_R_BACKOFF_LNA_C_M 0x3F
#define PATH1_R_BACKOFF_TIA_C 0x49F4
#define PATH1_R_BACKOFF_TIA_C_M 0xFC0
#define PATH1_R_BACKOFF_WBADC_C 0x49F4
#define PATH1_R_BACKOFF_WBADC_C_M 0x3F000
#define PATH1_R_G_IBADC_IN_C 0x49F4
#define PATH1_R_G_IBADC_IN_C_M 0xFC0000
#define PATH1_R_A_GS_SAT_IDX_RX_C 0x49F4
#define PATH1_R_A_GS_SAT_IDX_RX_C_M 0x1F000000
#define PATH1_R_A_WB_GIDX_00_LNA_TIA_C 0x49F4
#define PATH1_R_A_WB_GIDX_00_LNA_TIA_C_M 0xE0000000
#define FTM_EN_C 0x49F8
#define FTM_EN_C_M 0x1
#define PATH1_R_A_GS_UND_IDX_RX_C 0x49FC
#define PATH1_R_A_GS_UND_IDX_RX_C_M 0x1F
#define PATH1_R_G_GS_SAT_IDX_RX_C 0x49FC
#define PATH1_R_G_GS_SAT_IDX_RX_C_M 0x3E0
#define PATH1_R_G_GS_UND_IDX_RX_C 0x49FC
#define PATH1_R_G_GS_UND_IDX_RX_C_M 0x7C00
#define PATH1_R_DLY_DCCL_C 0x49FC
#define PATH1_R_DLY_DCCL_C_M 0x1F00000
#define PATH1_R_DLY_DFE_C 0x49FC
#define PATH1_R_DLY_DFE_C_M 0x3E000000
#define PATH1_R_G_MIXER_C 0x49FC
#define PATH1_R_G_MIXER_C_M 0xC0000000
#define TB_RSSI_M_BIAS_COMP_C 0x4A00
#define TB_RSSI_M_BIAS_COMP_C_M 0xFF
#define TB_RSSI_M_BIAS_COMP_BW20_C 0x4A00
#define TB_RSSI_M_BIAS_COMP_BW20_C_M 0xFF00
#define TB_RSSI_M_BIAS_COMP_BW40_C 0x4A00
#define TB_RSSI_M_BIAS_COMP_BW40_C_M 0xFF0000
#define TB_RSSI_M_BIAS_COMP_BW40_1_C 0x4A00
#define TB_RSSI_M_BIAS_COMP_BW40_1_C_M 0xFF000000
#define TB_RSSI_M_BIAS_COMP_BW40_2_C 0x4A04
#define TB_RSSI_M_BIAS_COMP_BW40_2_C_M 0xFF
#define TB_RSSI_M_BIAS_COMP_BW80_C 0x4A04
#define TB_RSSI_M_BIAS_COMP_BW80_C_M 0xFF00
#define TB_RSSI_M_BIAS_COMP_BW80_1_C 0x4A04
#define TB_RSSI_M_BIAS_COMP_BW80_1_C_M 0xFF0000
#define TB_RSSI_M_BIAS_COMP_BW80_10_C 0x4A04
#define TB_RSSI_M_BIAS_COMP_BW80_10_C_M 0xFF000000
#define TB_RSSI_M_BIAS_COMP_BW80_2_C 0x4A08
#define TB_RSSI_M_BIAS_COMP_BW80_2_C_M 0xFF
#define TB_RSSI_M_BIAS_COMP_BW80_3_C 0x4A08
#define TB_RSSI_M_BIAS_COMP_BW80_3_C_M 0xFF00
#define TB_RSSI_M_BIAS_COMP_BW80_4_C 0x4A08
#define TB_RSSI_M_BIAS_COMP_BW80_4_C_M 0xFF0000
#define TB_RSSI_M_BIAS_COMP_BW80_9_C 0x4A08
#define TB_RSSI_M_BIAS_COMP_BW80_9_C_M 0xFF000000
#define TIME2EN_INTP_C 0x4A18
#define TIME2EN_INTP_C_M 0xFF
#define LSIGMRLSIG_NOISE_EST_DIFF_THR_C 0x4A24
#define LSIGMRLSIG_NOISE_EST_DIFF_THR_C_M 0x3FF
#define LSIGMRLSIG_NOISE_EST_ORG_THR_C 0x4A24
#define LSIGMRLSIG_NOISE_EST_ORG_THR_C_M 0xFFC00
#define LSIGMRLSIG_NOISE_EST_FOR_PFD_EN_C 0x4A24
#define LSIGMRLSIG_NOISE_EST_FOR_PFD_EN_C_M 0x100000
#define LSIGMRLSIG_NOISE_EST_FOR_IN_EN_C 0x4A24
#define LSIGMRLSIG_NOISE_EST_FOR_IN_EN_C_M 0x200000
#define PDP_TAU_FIX_FOR_LOWSNR_C 0x4A48
#define PDP_TAU_FIX_FOR_LOWSNR_C_M 0x7
#define LPBW_SEL_D1_HEER_C 0x4A4C
#define LPBW_SEL_D1_HEER_C_M 0x1F
#define LPBW_SEL_D2_HEER_C 0x4A4C
#define LPBW_SEL_D2_HEER_C_M 0x3E0
#define LPBW_SEL_P1_HEER_C 0x4A4C
#define LPBW_SEL_P1_HEER_C_M 0x7C00
#define LPBW_SEL_P2_HEER_C 0x4A4C
#define LPBW_SEL_P2_HEER_C_M 0xF8000
#define CCK_ABANDON_TH_11M_1R_DB_C 0x4A50
#define CCK_ABANDON_TH_11M_1R_DB_C_M 0x1F
#define CCK_ABANDON_TH_11M_2R_DB_C 0x4A50
#define CCK_ABANDON_TH_11M_2R_DB_C_M 0x3E0
#define CCK_ABANDON_TH_11M_3R_DB_C 0x4A50
#define CCK_ABANDON_TH_11M_3R_DB_C_M 0x7C00
#define CCK_ABANDON_TH_11M_4R_DB_C 0x4A50
#define CCK_ABANDON_TH_11M_4R_DB_C_M 0xF8000
#define CCK_ABANDON_TH_5M_1R_DB_C 0x4A50
#define CCK_ABANDON_TH_5M_1R_DB_C_M 0x1F00000
#define CCK_ABANDON_TH_5M_2R_DB_C 0x4A50
#define CCK_ABANDON_TH_5M_2R_DB_C_M 0x3E000000
#define EVM_DATA_OPT_C 0x4A50
#define EVM_DATA_OPT_C_M 0xC0000000
#define CCK_ABANDON_TH_5M_3R_DB_C 0x4A54
#define CCK_ABANDON_TH_5M_3R_DB_C_M 0x1F
#define CCK_ABANDON_TH_5M_4R_DB_C 0x4A54
#define CCK_ABANDON_TH_5M_4R_DB_C_M 0x3E0
#define EVM_SIG_OPT_C 0x4A54
#define EVM_SIG_OPT_C_M 0xC00
#define CCK_ABANDON_EN_C 0x4A54
#define CCK_ABANDON_EN_C_M 0x1000
#define PATH1_R_DLY_PRIM_C 0x4A5C
#define PATH1_R_DLY_PRIM_C_M 0x1F
#define PATH1_R_DLY_SYNC_C 0x4A5C
#define PATH1_R_DLY_SYNC_C_M 0x3E0
#define PATH1_R_RXIDX_INIT_C 0x4A5C
#define PATH1_R_RXIDX_INIT_C_M 0x7C00
#define PATH1_R_A_GS_SAT_IDX_H_C 0x4A5C
#define PATH1_R_A_GS_SAT_IDX_H_C_M 0x78000
#define PATH1_R_A_GS_SAT_IDX_L_C 0x4A5C
#define PATH1_R_A_GS_SAT_IDX_L_C_M 0x780000
#define PATH1_R_A_GS_SAT_IDX_PP1_C 0x4A5C
#define PATH1_R_A_GS_SAT_IDX_PP1_C_M 0x7800000
#define PATH1_R_A_GS_SAT_IDX_PP2_C 0x4A5C
#define PATH1_R_A_GS_SAT_IDX_PP2_C_M 0x78000000
#define PATH1_R_1RCCA_PRE_PD_MODE_C 0x4A5C
#define PATH1_R_1RCCA_PRE_PD_MODE_C_M 0x80000000
#define PATH1_R_A_GS_SAT_TH_H_C 0x4A60
#define PATH1_R_A_GS_SAT_TH_H_C_M 0xF
#define PATH1_R_A_GS_SAT_TH_L_C 0x4A60
#define PATH1_R_A_GS_SAT_TH_L_C_M 0xF0
#define PATH1_R_A_GS_UND_IDX_C 0x4A60
#define PATH1_R_A_GS_UND_IDX_C_M 0xF00
#define PATH1_R_A_GS_UND_IDX_PP1_C 0x4A60
#define PATH1_R_A_GS_UND_IDX_PP1_C_M 0xF000
#define PATH1_R_A_GS_UND_IDX_PP2_C 0x4A60
#define PATH1_R_A_GS_UND_IDX_PP2_C_M 0xF0000
#define PATH1_R_A_GS_UND_TH_H_C 0x4A60
#define PATH1_R_A_GS_UND_TH_H_C_M 0xF00000
#define PATH1_R_A_GS_UND_TH_L_C 0x4A60
#define PATH1_R_A_GS_UND_TH_L_C_M 0xF000000
#define PATH1_R_GC1_TIME_C 0x4A60
#define PATH1_R_GC1_TIME_C_M 0xF0000000
#define PATH1_R_GC1_TIME_NLGC_C 0x4A64
#define PATH1_R_GC1_TIME_NLGC_C_M 0xF
#define PATH1_R_GC2_TIME_C 0x4A64
#define PATH1_R_GC2_TIME_C_M 0xF0
#define PATH1_R_GC2_TIME_NLGC_C 0x4A64
#define PATH1_R_GC2_TIME_NLGC_C_M 0xF00
#define PATH1_R_GC3_TIME_C 0x4A64
#define PATH1_R_GC3_TIME_C_M 0xF000
#define PATH1_R_GC4_TIME_C 0x4A64
#define PATH1_R_GC4_TIME_C_M 0xF0000
#define PATH1_R_GC5_TIME_C 0x4A64
#define PATH1_R_GC5_TIME_C_M 0xF00000
#define PATH1_R_GC_TIME_LESS_80M_C 0x4A64
#define PATH1_R_GC_TIME_LESS_80M_C_M 0xF000000
#define PATH1_R_GC_TIME_LESS_NLINEAR_C 0x4A64
#define PATH1_R_GC_TIME_LESS_NLINEAR_C_M 0xF0000000
#define PATH1_R_G_GS_SAT_IDX_H_C 0x4A68
#define PATH1_R_G_GS_SAT_IDX_H_C_M 0xF
#define PATH1_R_G_GS_SAT_IDX_L_C 0x4A68
#define PATH1_R_G_GS_SAT_IDX_L_C_M 0xF0
#define PATH1_R_G_GS_SAT_IDX_PP1_C 0x4A68
#define PATH1_R_G_GS_SAT_IDX_PP1_C_M 0xF00
#define PATH1_R_G_GS_SAT_IDX_PP2_C 0x4A68
#define PATH1_R_G_GS_SAT_IDX_PP2_C_M 0xF000
#define PATH1_R_G_GS_SAT_TH_H_C 0x4A68
#define PATH1_R_G_GS_SAT_TH_H_C_M 0xF0000
#define PATH1_R_G_GS_SAT_TH_L_C 0x4A68
#define PATH1_R_G_GS_SAT_TH_L_C_M 0xF00000
#define PATH1_R_G_GS_UND_IDX_C 0x4A68
#define PATH1_R_G_GS_UND_IDX_C_M 0xF000000
#define PATH1_R_G_GS_UND_IDX_PP1_C 0x4A68
#define PATH1_R_G_GS_UND_IDX_PP1_C_M 0xF0000000
#define PATH1_R_G_GS_UND_IDX_PP2_C 0x4A6C
#define PATH1_R_G_GS_UND_IDX_PP2_C_M 0xF
#define PATH1_R_G_GS_UND_TH_H_C 0x4A6C
#define PATH1_R_G_GS_UND_TH_H_C_M 0xF0
#define PATH1_R_G_GS_UND_TH_L_C 0x4A6C
#define PATH1_R_G_GS_UND_TH_L_C_M 0xF00
#define PATH1_R_ACI_NRBW_RATIO_C 0x4A6C
#define PATH1_R_ACI_NRBW_RATIO_C_M 0xF000
#define PATH1_R_AGC_RESTART_TH_IB_C 0x4A6C
#define PATH1_R_AGC_RESTART_TH_IB_C_M 0xF0000
#define PATH1_R_AGC_RESTART_TH_WB_C 0x4A6C
#define PATH1_R_AGC_RESTART_TH_WB_C_M 0xF00000
#define PATH1_R_DCCL_ALPHA_80_C 0x4A6C
#define PATH1_R_DCCL_ALPHA_80_C_M 0xF000000
#define PATH1_R_DCCL_ALPHA_N80_C 0x4A6C
#define PATH1_R_DCCL_ALPHA_N80_C_M 0xF0000000
#define PATH1_R_LGC_FREEZE_TH_H_C 0x4A70
#define PATH1_R_LGC_FREEZE_TH_H_C_M 0xF
#define PATH1_R_LGC_FREEZE_TH_L_C 0x4A70
#define PATH1_R_LGC_FREEZE_TH_L_C_M 0xF0
#define PATH1_R_NLGC_FREEZE_TH_H_C 0x4A70
#define PATH1_R_NLGC_FREEZE_TH_H_C_M 0xF00
#define PATH1_R_NLGC_FREEZE_TH_L_C 0x4A70
#define PATH1_R_NLGC_FREEZE_TH_L_C_M 0xF000
#define PATH1_R_WB_GAIN_IDX_INIT_C 0x4A70
#define PATH1_R_WB_GAIN_IDX_INIT_C_M 0xF0000
#define PATH1_R_A_WB_GIDX_01_LNA_TIA_C 0x4A70
#define PATH1_R_A_WB_GIDX_01_LNA_TIA_C_M 0x7000000
#define PATH1_R_A_WB_GIDX_02_LNA_TIA_C 0x4A70
#define PATH1_R_A_WB_GIDX_02_LNA_TIA_C_M 0x38000000
#define PATH1_R_G_WBADC_IN_C 0x4A70
#define PATH1_R_G_WBADC_IN_C_M 0xC0000000
#define PATH1_R_A_WB_GIDX_03_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_03_LNA_TIA_C_M 0x7
#define PATH1_R_A_WB_GIDX_04_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_04_LNA_TIA_C_M 0x38
#define PATH1_R_A_WB_GIDX_05_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_05_LNA_TIA_C_M 0x1C0
#define PATH1_R_A_WB_GIDX_06_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_06_LNA_TIA_C_M 0xE00
#define PATH1_R_A_WB_GIDX_07_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_07_LNA_TIA_C_M 0x7000
#define PATH1_R_A_WB_GIDX_08_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_08_LNA_TIA_C_M 0x38000
#define PATH1_R_A_WB_GIDX_09_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_09_LNA_TIA_C_M 0x1C0000
#define PATH1_R_A_WB_GIDX_10_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_10_LNA_TIA_C_M 0xE00000
#define PATH1_R_A_WB_GIDX_11_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_11_LNA_TIA_C_M 0x7000000
#define PATH1_R_A_WB_GIDX_12_LNA_TIA_C 0x4A74
#define PATH1_R_A_WB_GIDX_12_LNA_TIA_C_M 0x38000000
#define PATH1_R_IBADC_PW_ALPHA_H_C 0x4A74
#define PATH1_R_IBADC_PW_ALPHA_H_C_M 0xC0000000
#define PATH1_R_A_WB_GIDX_13_LNA_TIA_C 0x4A78
#define PATH1_R_A_WB_GIDX_13_LNA_TIA_C_M 0x7
#define PATH1_R_A_WB_GIDX_14_LNA_TIA_C 0x4A78
#define PATH1_R_A_WB_GIDX_14_LNA_TIA_C_M 0x38
#define PATH1_R_A_WB_GIDX_15_LNA_TIA_C 0x4A78
#define PATH1_R_A_WB_GIDX_15_LNA_TIA_C_M 0x1C0
#define PATH1_R_G_WB_GIDX_00_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_00_LNA_TIA_C_M 0xE00
#define PATH1_R_G_WB_GIDX_01_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_01_LNA_TIA_C_M 0x7000
#define PATH1_R_G_WB_GIDX_02_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_02_LNA_TIA_C_M 0x38000
#define PATH1_R_G_WB_GIDX_03_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_03_LNA_TIA_C_M 0x1C0000
#define PATH1_R_G_WB_GIDX_04_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_04_LNA_TIA_C_M 0xE00000
#define PATH1_R_G_WB_GIDX_05_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_05_LNA_TIA_C_M 0x7000000
#define PATH1_R_G_WB_GIDX_06_LNA_TIA_C 0x4A78
#define PATH1_R_G_WB_GIDX_06_LNA_TIA_C_M 0x38000000
#define PATH1_R_IBADC_PW_ALPHA_L_C 0x4A78
#define PATH1_R_IBADC_PW_ALPHA_L_C_M 0xC0000000
#define PATH1_R_G_WB_GIDX_07_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_07_LNA_TIA_C_M 0x7
#define PATH1_R_G_WB_GIDX_08_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_08_LNA_TIA_C_M 0x38
#define PATH1_R_G_WB_GIDX_09_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_09_LNA_TIA_C_M 0x1C0
#define PATH1_R_G_WB_GIDX_10_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_10_LNA_TIA_C_M 0xE00
#define PATH1_R_G_WB_GIDX_11_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_11_LNA_TIA_C_M 0x7000
#define PATH1_R_G_WB_GIDX_12_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_12_LNA_TIA_C_M 0x38000
#define PATH1_R_G_WB_GIDX_13_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_13_LNA_TIA_C_M 0x1C0000
#define PATH1_R_G_WB_GIDX_14_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_14_LNA_TIA_C_M 0xE00000
#define PATH1_R_G_WB_GIDX_15_LNA_TIA_C 0x4A7C
#define PATH1_R_G_WB_GIDX_15_LNA_TIA_C_M 0x7000000
#define PATH1_R_BT_LNA_IDX0_C 0x4A7C
#define PATH1_R_BT_LNA_IDX0_C_M 0x38000000
#define PATH1_R_LINEAR_STEP_LIM_C 0x4A7C
#define PATH1_R_LINEAR_STEP_LIM_C_M 0xC0000000
#define PATH1_R_BT_LNA_IDX1_C 0x4A80
#define PATH1_R_BT_LNA_IDX1_C_M 0x7
#define PATH1_R_BT_LNA_IDX2_C 0x4A80
#define PATH1_R_BT_LNA_IDX2_C_M 0x38
#define PATH1_R_BT_LNA_IDX3_C 0x4A80
#define PATH1_R_BT_LNA_IDX3_C_M 0x1C0
#define PATH1_R_ELNA_SEL_MARGIN_LGC_C 0x4A80
#define PATH1_R_ELNA_SEL_MARGIN_LGC_C_M 0xE00
#define PATH1_R_ELNA_SEL_MARGIN_NLGC_C 0x4A80
#define PATH1_R_ELNA_SEL_MARGIN_NLGC_C_M 0x7000
#define PATH1_R_IBADC_CLIP_RATIO_C 0x4A80
#define PATH1_R_IBADC_CLIP_RATIO_C_M 0x38000
#define PATH1_R_IBADC_CLIP_TH_C 0x4A80
#define PATH1_R_IBADC_CLIP_TH_C_M 0x1C0000
#define PATH1_R_LGC_STEP_LIM_C 0x4A80
#define PATH1_R_LGC_STEP_LIM_C_M 0xE00000
#define PATH1_R_LNA_IDX_INIT_C 0x4A80
#define PATH1_R_LNA_IDX_INIT_C_M 0x7000000
#define PATH1_R_LNA_SEL_MARGIN_LGC_C 0x4A80
#define PATH1_R_LNA_SEL_MARGIN_LGC_C_M 0x38000000
#define PATH1_R_LINEAR_STEP_MIN_C 0x4A80
#define PATH1_R_LINEAR_STEP_MIN_C_M 0xC0000000
#define SEG0R_DFS_MSKNPW_TH_C 0x4A84
#define SEG0R_DFS_MSKNPW_TH_C_M 0x7F
#define SEG0R_DFS_MSKNPW_EN_C 0x4A84
#define SEG0R_DFS_MSKNPW_EN_C_M 0x80
#define PATH0_R_IB_PW_DIFF_OFST_BW20_C 0x4A8C
#define PATH0_R_IB_PW_DIFF_OFST_BW20_C_M 0xF
#define PATH0_R_IB_PW_DIFF_OFST_BW40_C 0x4A8C
#define PATH0_R_IB_PW_DIFF_OFST_BW40_C_M 0xF0
#define PATH0_R_IB_PW_DIFF_OFST_BW80_C 0x4A8C
#define PATH0_R_IB_PW_DIFF_OFST_BW80_C_M 0xF00
#define PATH1_R_IB_PW_DIFF_OFST_BW20_C 0x4A90
#define PATH1_R_IB_PW_DIFF_OFST_BW20_C_M 0xF
#define PATH1_R_IB_PW_DIFF_OFST_BW40_C 0x4A90
#define PATH1_R_IB_PW_DIFF_OFST_BW40_C_M 0xF0
#define PATH1_R_IB_PW_DIFF_OFST_BW80_C 0x4A90
#define PATH1_R_IB_PW_DIFF_OFST_BW80_C_M 0xF00
#define SEG0R_SB5M_BLK_PATH_COMB_TYPE_C 0x4A94
#define SEG0R_SB5M_BLK_PATH_COMB_TYPE_C_M 0x1
#define PATH1_R_LNA_SEL_MARGIN_NLGC_C 0x4A9C
#define PATH1_R_LNA_SEL_MARGIN_NLGC_C_M 0x7
#define PATH1_R_RXSEL_MARGIN_LGC_C 0x4A9C
#define PATH1_R_RXSEL_MARGIN_LGC_C_M 0x38
#define PATH1_R_RXSEL_MARGIN_NLGC_C 0x4A9C
#define PATH1_R_RXSEL_MARGIN_NLGC_C_M 0x1C0
#define PATH1_R_TIA_SEL_MARGIN_LGC_C 0x4A9C
#define PATH1_R_TIA_SEL_MARGIN_LGC_C_M 0xE00
#define PATH1_R_TIA_SEL_MARGIN_NLGC_C 0x4A9C
#define PATH1_R_TIA_SEL_MARGIN_NLGC_C_M 0x7000
#define PATH1_R_WBADC_CLIP_RATIO_C 0x4A9C
#define PATH1_R_WBADC_CLIP_RATIO_C_M 0x38000
#define PATH1_R_WBADC_CLIP_TH_C 0x4A9C
#define PATH1_R_WBADC_CLIP_TH_C_M 0x1C0000
#define PATH1_R_NLGC_STEP_LIM_C 0x4A9C
#define PATH1_R_NLGC_STEP_LIM_C_M 0x600000
#define PATH1_R_NLGC_STEP_MIN_C 0x4A9C
#define PATH1_R_NLGC_STEP_MIN_C_M 0x1800000
#define PATH1_R_POST_PD_STEP_LIM_C 0x4A9C
#define PATH1_R_POST_PD_STEP_LIM_C_M 0x6000000
#define PATH1_R_POST_PD_STEP_MIN_C 0x4A9C
#define PATH1_R_POST_PD_STEP_MIN_C_M 0x18000000
#define PATH1_R_PRE_PD_STEP_LIM_C 0x4A9C
#define PATH1_R_PRE_PD_STEP_LIM_C_M 0x60000000
#define PATH1_R_AGC_EN_C 0x4A9C
#define PATH1_R_AGC_EN_C_M 0x80000000
#define PATH1_R_PRE_PD_STEP_MIN_C 0x4AA0
#define PATH1_R_PRE_PD_STEP_MIN_C_M 0x3
#define PATH1_R_WBADC_PW_ALPHA_H_C 0x4AA0
#define PATH1_R_WBADC_PW_ALPHA_H_C_M 0xC
#define PATH1_R_WBADC_PW_ALPHA_L_C 0x4AA0
#define PATH1_R_WBADC_PW_ALPHA_L_C_M 0x30
#define PATH1_R_A_WB_GIDX_00_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_00_ELNA_C_M 0x40
#define PATH1_R_A_WB_GIDX_01_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_01_ELNA_C_M 0x80
#define PATH1_R_A_WB_GIDX_02_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_02_ELNA_C_M 0x100
#define PATH1_R_A_WB_GIDX_03_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_03_ELNA_C_M 0x200
#define PATH1_R_A_WB_GIDX_04_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_04_ELNA_C_M 0x400
#define PATH1_R_A_WB_GIDX_05_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_05_ELNA_C_M 0x800
#define PATH1_R_A_WB_GIDX_06_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_06_ELNA_C_M 0x1000
#define PATH1_R_A_WB_GIDX_07_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_07_ELNA_C_M 0x2000
#define PATH1_R_A_WB_GIDX_08_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_08_ELNA_C_M 0x4000
#define PATH1_R_A_WB_GIDX_09_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_09_ELNA_C_M 0x8000
#define PATH1_R_A_WB_GIDX_10_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_10_ELNA_C_M 0x10000
#define PATH1_R_A_WB_GIDX_11_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_11_ELNA_C_M 0x20000
#define PATH1_R_A_WB_GIDX_12_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_12_ELNA_C_M 0x40000
#define PATH1_R_A_WB_GIDX_13_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_13_ELNA_C_M 0x80000
#define PATH1_R_A_WB_GIDX_14_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_14_ELNA_C_M 0x100000
#define PATH1_R_A_WB_GIDX_15_ELNA_C 0x4AA0
#define PATH1_R_A_WB_GIDX_15_ELNA_C_M 0x200000
#define PATH1_R_GC_TIME_1T_MORE_C 0x4AA0
#define PATH1_R_GC_TIME_1T_MORE_C_M 0x400000
#define PATH1_R_G_WB_GIDX_00_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_00_ELNA_C_M 0x800000
#define PATH1_R_G_WB_GIDX_01_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_01_ELNA_C_M 0x1000000
#define PATH1_R_G_WB_GIDX_02_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_02_ELNA_C_M 0x2000000
#define PATH1_R_G_WB_GIDX_03_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_03_ELNA_C_M 0x4000000
#define PATH1_R_G_WB_GIDX_04_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_04_ELNA_C_M 0x8000000
#define PATH1_R_G_WB_GIDX_05_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_05_ELNA_C_M 0x10000000
#define PATH1_R_G_WB_GIDX_06_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_06_ELNA_C_M 0x20000000
#define PATH1_R_G_WB_GIDX_07_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_07_ELNA_C_M 0x40000000
#define PATH1_R_G_WB_GIDX_08_ELNA_C 0x4AA0
#define PATH1_R_G_WB_GIDX_08_ELNA_C_M 0x80000000
#define PATH1_R_G_WB_GIDX_09_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_09_ELNA_C_M 0x1
#define PATH1_R_G_WB_GIDX_10_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_10_ELNA_C_M 0x2
#define PATH1_R_G_WB_GIDX_11_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_11_ELNA_C_M 0x4
#define PATH1_R_G_WB_GIDX_12_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_12_ELNA_C_M 0x8
#define PATH1_R_G_WB_GIDX_13_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_13_ELNA_C_M 0x10
#define PATH1_R_G_WB_GIDX_14_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_14_ELNA_C_M 0x20
#define PATH1_R_G_WB_GIDX_15_ELNA_C 0x4AA4
#define PATH1_R_G_WB_GIDX_15_ELNA_C_M 0x40
#define PATH1_R_SE1_TIME_C 0x4AA4
#define PATH1_R_SE1_TIME_C_M 0x80
#define PATH1_R_SE1_TIME_NLGC_C 0x4AA4
#define PATH1_R_SE1_TIME_NLGC_C_M 0x100
#define PATH1_R_SE2_TIME_C 0x4AA4
#define PATH1_R_SE2_TIME_C_M 0x200
#define PATH1_R_SE2_TIME_NLGC_C 0x4AA4
#define PATH1_R_SE2_TIME_NLGC_C_M 0x400
#define PATH1_R_SE3_TIME_C 0x4AA4
#define PATH1_R_SE3_TIME_C_M 0x800
#define PATH1_R_SE4_TIME_C 0x4AA4
#define PATH1_R_SE4_TIME_C_M 0x1000
#define PATH1_R_SE5_TIME_C 0x4AA4
#define PATH1_R_SE5_TIME_C_M 0x2000
#define PATH1_R_SE_TIME_DONE_C 0x4AA4
#define PATH1_R_SE_TIME_DONE_C_M 0x4000
#define PATH1_R_SE_TIME_LINEAR_EXT_C 0x4AA4
#define PATH1_R_SE_TIME_LINEAR_EXT_C_M 0x8000
#define PATH1_R_ACI_NRBW_EN_C 0x4AA4
#define PATH1_R_ACI_NRBW_EN_C_M 0x10000
#define PATH1_R_BAND_SEL_C 0x4AA4
#define PATH1_R_BAND_SEL_C_M 0x20000
#define PATH1_R_BT_RX_MODE_EN_C 0x4AA4
#define PATH1_R_BT_RX_MODE_EN_C_M 0x40000
#define PATH1_R_BT_SHARE_C 0x4AA4
#define PATH1_R_BT_SHARE_C_M 0x80000
#define PATH1_R_BT_TX_FORCE_NRBW_C 0x4AA4
#define PATH1_R_BT_TX_FORCE_NRBW_C_M 0x100000
#define PATH1_R_BT_TX_MODE_EN_C 0x4AA4
#define PATH1_R_BT_TX_MODE_EN_C_M 0x200000
#define PATH1_R_BTG_PATH_C 0x4AA4
#define PATH1_R_BTG_PATH_C_M 0x400000
#define PATH1_R_CCK_FORCE_NRBW_C 0x4AA4
#define PATH1_R_CCK_FORCE_NRBW_C_M 0x800000
#define PATH1_R_DCCL_EN_C 0x4AA4
#define PATH1_R_DCCL_EN_C_M 0x1000000
#define PATH1_R_ELNA_BYPASS_EN_C 0x4AA4
#define PATH1_R_ELNA_BYPASS_EN_C_M 0x2000000
#define PATH1_R_ELNA_EN_C 0x4AA4
#define PATH1_R_ELNA_EN_C_M 0x4000000
#define PATH1_R_ELNA_IDX_INIT_C 0x4AA4
#define PATH1_R_ELNA_IDX_INIT_C_M 0x8000000
#define PATH1_R_FORCE_BT_COEX_C 0x4AA4
#define PATH1_R_FORCE_BT_COEX_C_M 0x10000000
#define PATH1_R_FORCE_NRBW_C 0x4AA4
#define PATH1_R_FORCE_NRBW_C_M 0x20000000
#define PATH1_R_I_ONLY_C 0x4AA4
#define PATH1_R_I_ONLY_C_M 0x40000000
#define PATH1_R_LGC_DAGC_EN_C 0x4AA4
#define PATH1_R_LGC_DAGC_EN_C_M 0x80000000
#define PATH1_R_LINEAR_AGC_EN_C 0x4AA8
#define PATH1_R_LINEAR_AGC_EN_C_M 0x1
#define PATH1_R_LINEAR_MARGIN_MODE_C 0x4AA8
#define PATH1_R_LINEAR_MARGIN_MODE_C_M 0x2
#define PATH1_R_NLGC_AGC_EN_C 0x4AA8
#define PATH1_R_NLGC_AGC_EN_C_M 0x4
#define PATH1_R_NLGC_DAGC_EN_C 0x4AA8
#define PATH1_R_NLGC_DAGC_EN_C_M 0x8
#define PATH1_R_NRBW_DEF_C 0x4AA8
#define PATH1_R_NRBW_DEF_C_M 0x10
#define PATH1_R_POST_PD_AGC_EN_C 0x4AA8
#define PATH1_R_POST_PD_AGC_EN_C_M 0x20
#define PATH1_R_PRE_PD_AGC_EN_C 0x4AA8
#define PATH1_R_PRE_PD_AGC_EN_C_M 0x40
#define PATH1_R_PURE_POST_PD_MODE_C 0x4AA8
#define PATH1_R_PURE_POST_PD_MODE_C_M 0x80
#define PATH1_R_SYNC_PRE_PD_STEP_C 0x4AA8
#define PATH1_R_SYNC_PRE_PD_STEP_C_M 0x100
#define PATH1_R_TIA_IDX_INIT_C 0x4AA8
#define PATH1_R_TIA_IDX_INIT_C_M 0x200
#define PATH1_R_TIA_SHRINK_DEF_C 0x4AA8
#define PATH1_R_TIA_SHRINK_DEF_C_M 0x400
#define PATH1_R_TIA_SHRINK_EN_C 0x4AA8
#define PATH1_R_TIA_SHRINK_EN_C_M 0x800
#define PATH1_R_TIA_SHRINK_INIT_C 0x4AA8
#define PATH1_R_TIA_SHRINK_INIT_C_M 0x1000
#define LDPC_MCS0_MAX_ITER_C 0x4AAC
#define LDPC_MCS0_MAX_ITER_C_M 0xF
#define LDPC_MCS10_MAX_ITER_C 0x4AAC
#define LDPC_MCS10_MAX_ITER_C_M 0xF0
#define LDPC_MCS11_MAX_ITER_C 0x4AAC
#define LDPC_MCS11_MAX_ITER_C_M 0xF00
#define LDPC_MCS1_MAX_ITER_C 0x4AAC
#define LDPC_MCS1_MAX_ITER_C_M 0xF000
#define LDPC_MCS2_MAX_ITER_C 0x4AAC
#define LDPC_MCS2_MAX_ITER_C_M 0xF0000
#define LDPC_MCS3_MAX_ITER_C 0x4AAC
#define LDPC_MCS3_MAX_ITER_C_M 0xF00000
#define LDPC_MCS4_MAX_ITER_C 0x4AAC
#define LDPC_MCS4_MAX_ITER_C_M 0xF000000
#define LDPC_MCS5_MAX_ITER_C 0x4AAC
#define LDPC_MCS5_MAX_ITER_C_M 0xF0000000
#define LDPC_MCS6_MAX_ITER_C 0x4AB0
#define LDPC_MCS6_MAX_ITER_C_M 0xF
#define LDPC_MCS7_MAX_ITER_C 0x4AB0
#define LDPC_MCS7_MAX_ITER_C_M 0xF0
#define LDPC_MCS8_MAX_ITER_C 0x4AB0
#define LDPC_MCS8_MAX_ITER_C_M 0xF00
#define LDPC_MCS9_MAX_ITER_C 0x4AB0
#define LDPC_MCS9_MAX_ITER_C_M 0xF000
#define CFO_COMP_PHASE_MODE_C 0x4AB4
#define CFO_COMP_PHASE_MODE_C_M 0x1
#define PROCR_POST_RX_PROC_DLY_TIME_C 0x4ABC
#define PROCR_POST_RX_PROC_DLY_TIME_C_M 0x7F
#define T2F_R_HE_1SS_CDDREFINE_TIE_0_C 0x4AC8
#define T2F_R_HE_1SS_CDDREFINE_TIE_0_C_M 0x1
#define PATH0_R_AGC_RESERVED_1_C 0x4ACC
#define PATH0_R_AGC_RESERVED_1_C_M 0xFFFFFFFF
#define PATH0_R_AGC_RESERVED_2_C 0x4AD0
#define PATH0_R_AGC_RESERVED_2_C_M 0xFFFFFFFF
#define PATH0_R_RXBY_WBADC_TH_C 0x4AD4
#define PATH0_R_RXBY_WBADC_TH_C_M 0xF
#define PATH0_R_ALWAYS_RXBY_WBADC_C 0x4AD4
#define PATH0_R_ALWAYS_RXBY_WBADC_C_M 0x10
#define PATH0_R_BT_RXBY_WBADC_C 0x4AD4
#define PATH0_R_BT_RXBY_WBADC_C_M 0x20
#define PATH0_R_BT_TRACKING_OFF_EN_C 0x4AD4
#define PATH0_R_BT_TRACKING_OFF_EN_C_M 0x40
#define PATH1_R_AGC_RESERVED_1_C 0x4AD8
#define PATH1_R_AGC_RESERVED_1_C_M 0xFFFFFFFF
#define PATH1_R_AGC_RESERVED_2_C 0x4ADC
#define PATH1_R_AGC_RESERVED_2_C_M 0xFFFFFFFF
#define PATH1_R_RXBY_WBADC_TH_C 0x4AE0
#define PATH1_R_RXBY_WBADC_TH_C_M 0xF
#define PATH1_R_ALWAYS_RXBY_WBADC_C 0x4AE0
#define PATH1_R_ALWAYS_RXBY_WBADC_C_M 0x10
#define PATH1_R_BT_RXBY_WBADC_C 0x4AE0
#define PATH1_R_BT_RXBY_WBADC_C_M 0x20
#define PATH1_R_BT_TRACKING_OFF_EN_C 0x4AE0
#define PATH1_R_BT_TRACKING_OFF_EN_C_M 0x40
#define PATH0_R_BT_BACKOFF_BMODE_C 0x4AE4
#define PATH0_R_BT_BACKOFF_BMODE_C_M 0x3F
#define PATH0_R_BT_BACKOFF_IBADC_C 0x4AE4
#define PATH0_R_BT_BACKOFF_IBADC_C_M 0xFC0
#define PATH0_R_BT_BACKOFF_LNA_C 0x4AE4
#define PATH0_R_BT_BACKOFF_LNA_C_M 0x3F000
#define PATH0_R_BT_BACKOFF_TIA_C 0x4AE4
#define PATH0_R_BT_BACKOFF_TIA_C_M 0xFC0000
#define PATH0_R_GC_TIME_LESS_160M_C 0x4AE4
#define PATH0_R_GC_TIME_LESS_160M_C_M 0xF000000
#define PATH0_R_DCCL_ALPHA_160_C 0x4AE4
#define PATH0_R_DCCL_ALPHA_160_C_M 0xF0000000
#define PATH0_R_WBADC_DLY_160M_C 0x4AE8
#define PATH0_R_WBADC_DLY_160M_C_M 0xF
#define PATH0_R_WBADC_DLY_80M_C 0x4AE8
#define PATH0_R_WBADC_DLY_80M_C_M 0xF0
#define PATH0_R_WBADC_DLY_N80M_C 0x4AE8
#define PATH0_R_WBADC_DLY_N80M_C_M 0xF00
#define PATH0_R_RSSI_SOURCE_C 0x4AE8
#define PATH0_R_RSSI_SOURCE_C_M 0x1000
#define PATH1_R_BT_BACKOFF_BMODE_C 0x4AEC
#define PATH1_R_BT_BACKOFF_BMODE_C_M 0x3F
#define PATH1_R_BT_BACKOFF_IBADC_C 0x4AEC
#define PATH1_R_BT_BACKOFF_IBADC_C_M 0xFC0
#define PATH1_R_BT_BACKOFF_LNA_C 0x4AEC
#define PATH1_R_BT_BACKOFF_LNA_C_M 0x3F000
#define PATH1_R_BT_BACKOFF_TIA_C 0x4AEC
#define PATH1_R_BT_BACKOFF_TIA_C_M 0xFC0000
#define PATH1_R_GC_TIME_LESS_160M_C 0x4AEC
#define PATH1_R_GC_TIME_LESS_160M_C_M 0xF000000
#define PATH1_R_DCCL_ALPHA_160_C 0x4AEC
#define PATH1_R_DCCL_ALPHA_160_C_M 0xF0000000
#define PATH1_R_WBADC_DLY_160M_C 0x4AF0
#define PATH1_R_WBADC_DLY_160M_C_M 0xF
#define PATH1_R_WBADC_DLY_80M_C 0x4AF0
#define PATH1_R_WBADC_DLY_80M_C_M 0xF0
#define PATH1_R_WBADC_DLY_N80M_C 0x4AF0
#define PATH1_R_WBADC_DLY_N80M_C_M 0xF00
#define PATH1_R_RSSI_SOURCE_C 0x4AF0
#define PATH1_R_RSSI_SOURCE_C_M 0x1000
#define SEG0R_SNDCCA_RSV_C 0x4AFC
#define SEG0R_SNDCCA_RSV_C_M 0xFFFFFFFF
#define GD_PHASE_NON_LEG_R0S2_C 0x4B04
#define GD_PHASE_NON_LEG_R0S2_C_M 0xFF
#define GD_PHASE_NON_LEG_R0S3_C 0x4B04
#define GD_PHASE_NON_LEG_R0S3_C_M 0xFF00
#define GD_PHASE_NON_LEG_R1S2_C 0x4B04
#define GD_PHASE_NON_LEG_R1S2_C_M 0xFF0000
#define GD_PHASE_NON_LEG_R1S3_C 0x4B04
#define GD_PHASE_NON_LEG_R1S3_C_M 0xFF000000
#define MANUAL_GD_PHASE_LEGACY_EN_C 0x4B08
#define MANUAL_GD_PHASE_LEGACY_EN_C_M 0x1
#define PATH0_R_TSSI_CURVE_P0_C 0x5600
#define PATH0_R_TSSI_CURVE_P0_C_M 0x3F
#define PATH0_R_TSSI_CURVE_P1_C 0x5600
#define PATH0_R_TSSI_CURVE_P1_C_M 0x3F00
#define PATH0_R_TSSI_CURVE_P2_C 0x5600
#define PATH0_R_TSSI_CURVE_P2_C_M 0x3F0000
#define PATH0_R_TSSI_CURVE_P3_C 0x5600
#define PATH0_R_TSSI_CURVE_P3_C_M 0x3F000000
#define PATH0_R_TSSI_CURVE_P4_C 0x5604
#define PATH0_R_TSSI_CURVE_P4_C_M 0x3F
#define PATH0_R_TSSI_CURVE_P5_C 0x5604
#define PATH0_R_TSSI_CURVE_P5_C_M 0x3F00
#define PATH0_R_TSSI_CURVE_P6_C 0x5604
#define PATH0_R_TSSI_CURVE_P6_C_M 0x3F0000
#define PATH0_R_TSSI_CURVE_EN_C 0x5604
#define PATH0_R_TSSI_CURVE_EN_C_M 0x80000000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C 0x5608
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C_M 0x1FF
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C 0x5608
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C_M 0x3FE00
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C 0x5608
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C_M 0x7FC0000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C 0x560C
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C_M 0x1FF
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C 0x560C
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C_M 0x3FE00
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C 0x560C
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C_M 0x7FC0000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C 0x5610
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C_M 0x1FF
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C 0x5610
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C_M 0x3FE00
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C 0x5610
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C_M 0x7FC0000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C 0x5614
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C_M 0x1FF
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C 0x5614
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C_M 0x3FE00
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C 0x5614
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C_M 0x7FC0000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C 0x5618
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C_M 0x1FF
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C 0x5618
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C_M 0x3FE00
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C 0x5618
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C_M 0x7FC0000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C 0x561C
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C_M 0x1FF
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C 0x561C
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C_M 0xFF0000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C 0x561C
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C_M 0xFF000000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C 0x5620
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C_M 0xFF
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C 0x5620
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C_M 0xFF00
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C 0x5620
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C_M 0xFF0000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C 0x5620
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C_M 0xFF000000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C 0x5624
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C_M 0xFF
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C 0x5624
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C_M 0xFF00
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C 0x5624
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C_M 0xFF0000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C 0x5624
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C_M 0xFF000000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C 0x5628
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C_M 0xFF
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C 0x5628
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C_M 0xFF00
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C 0x5628
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C_M 0xFF0000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C 0x5628
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C_M 0xFF000000
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C 0x562C
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C_M 0xFF
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C 0x562C
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C_M 0xFF00
#define PATH0_R_TSSI_J_OFDM_G0_C 0x5630
#define PATH0_R_TSSI_J_OFDM_G0_C_M 0x3FF
#define PATH0_R_TSSI_J_OFDM_G1_C 0x5630
#define PATH0_R_TSSI_J_OFDM_G1_C_M 0xFFC00
#define PATH0_R_TSSI_J_OFDM_G2_C 0x5630
#define PATH0_R_TSSI_J_OFDM_G2_C_M 0x3FF00000
#define PATH0_R_TSSI_J_OFDM_G3_C 0x5634
#define PATH0_R_TSSI_J_OFDM_G3_C_M 0x3FF
#define PATH0_R_TSSI_J_OFDM_G4_C 0x5634
#define PATH0_R_TSSI_J_OFDM_G4_C_M 0xFFC00
#define PATH0_R_TSSI_J_OFDM_G5_C 0x5634
#define PATH0_R_TSSI_J_OFDM_G5_C_M 0x3FF00000
#define PATH0_R_TSSI_J_OFDM_G6_C 0x5638
#define PATH0_R_TSSI_J_OFDM_G6_C_M 0x3FF
#define PATH0_R_TSSI_J_OFDM_G7_C 0x5638
#define PATH0_R_TSSI_J_OFDM_G7_C_M 0xFFC00
#define PATH0_R_TSSI_J_CCK_G0_C 0x563C
#define PATH0_R_TSSI_J_CCK_G0_C_M 0x3FF
#define PATH0_R_TSSI_J_CCK_G1_C 0x563C
#define PATH0_R_TSSI_J_CCK_G1_C_M 0xFFC00
#define PATH0_R_TSSI_J_CCK_G2_C 0x563C
#define PATH0_R_TSSI_J_CCK_G2_C_M 0x3FF00000
#define PATH0_R_TSSI_J_CCK_G3_C 0x5640
#define PATH0_R_TSSI_J_CCK_G3_C_M 0x3FF
#define PATH0_R_TSSI_J_CCK_G4_C 0x5640
#define PATH0_R_TSSI_J_CCK_G4_C_M 0xFFC00
#define PATH0_R_TSSI_J_CCK_G5_C 0x5640
#define PATH0_R_TSSI_J_CCK_G5_C_M 0x3FF00000
#define PATH0_R_TSSI_J_CCK_G6_C 0x5644
#define PATH0_R_TSSI_J_CCK_G6_C_M 0x3FF
#define PATH0_R_TSSI_J_CCK_G7_C 0x5644
#define PATH0_R_TSSI_J_CCK_G7_C_M 0xFFC00
#define PATH0_R_TXRFC_RFMODE_FORCE_VAL_C 0x5648
#define PATH0_R_TXRFC_RFMODE_FORCE_VAL_C_M 0xF
#define PATH0_R_TXRFC_RFMODE_FORCE_ON_C 0x5648
#define PATH0_R_TXRFC_RFMODE_FORCE_ON_C_M 0x10
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_VAL_C 0x5648
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_VAL_C_M 0x3E0
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_ON_C 0x5648
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_ON_C_M 0x400
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_VAL_C 0x5648
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_VAL_C_M 0x800
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_ON_C 0x5648
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_ON_C_M 0x1000
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_VAL_C 0x5648
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_VAL_C_M 0x7E000
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_ON_C 0x5648
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_ON_C_M 0x80000
#define PATH0_R_TXRFC_GAIN_TX_FORCE_VAL_C 0x564C
#define PATH0_R_TXRFC_GAIN_TX_FORCE_VAL_C_M 0x1F
#define PATH0_R_TXRFC_GAIN_TX_FORCE_ON_C 0x564C
#define PATH0_R_TXRFC_GAIN_TX_FORCE_ON_C_M 0x20
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C 0x564C
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C_M 0xC0
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C 0x564C
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C_M 0x100
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C 0x564C
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C_M 0x600
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C 0x564C
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C_M 0x800
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C 0x564C
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C_M 0xE000
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C 0x564C
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C_M 0x10000
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_VAL_C 0x564C
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_VAL_C_M 0xE0000
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_ON_C 0x564C
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_ON_C_M 0x100000
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C 0x5650
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C_M 0x1F
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_C 0x5650
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_C_M 0x3E0
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C 0x5650
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C_M 0x7C00
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C 0x5650
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C_M 0xF8000
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C 0x5650
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C_M 0x1F00000
#define PATH0_R_TSSI_DCK_BY_CURVE_EN_C 0x5650
#define PATH0_R_TSSI_DCK_BY_CURVE_EN_C_M 0x80000000
#define PATH0_R_TSSI_DCK_BY_CURVE_0_C 0x5654
#define PATH0_R_TSSI_DCK_BY_CURVE_0_C_M 0xFFF
#define PATH0_R_TSSI_DCK_BY_CURVE_1_C 0x5654
#define PATH0_R_TSSI_DCK_BY_CURVE_1_C_M 0xFFF000
#define PATH0_R_TSSI_DCK_BY_CURVE_2_C 0x5658
#define PATH0_R_TSSI_DCK_BY_CURVE_2_C_M 0xFFF
#define PATH0_R_TSSI_DCK_BY_CURVE_3_C 0x5658
#define PATH0_R_TSSI_DCK_BY_CURVE_3_C_M 0xFFF000
#define PATH0_R_TSSI_DCK_BY_CURVE_4_C 0x565C
#define PATH0_R_TSSI_DCK_BY_CURVE_4_C_M 0xFFF
#define PATH0_R_TSSI_DCK_BY_CURVE_5_C 0x565C
#define PATH0_R_TSSI_DCK_BY_CURVE_5_C_M 0xFFF000
#define PATH0_R_TSSI_DCK_BY_CURVE_6_C 0x5660
#define PATH0_R_TSSI_DCK_BY_CURVE_6_C_M 0xFFF
#define PATH0_R_TSSI_DCK_BY_CURVE_7_C 0x5660
#define PATH0_R_TSSI_DCK_BY_CURVE_7_C_M 0xFFF000
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C 0x5664
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C_M 0x7
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C 0x5664
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C_M 0x38
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C 0x5664
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C_M 0x1C0
#define PATH0_R_TSSI_DCK_MOVING_AVG_LEN_C 0x5664
#define PATH0_R_TSSI_DCK_MOVING_AVG_LEN_C_M 0x7000
#define PATH0_R_TSSI_DCK_MOVING_AVG_CLR_C 0x5664
#define PATH0_R_TSSI_DCK_MOVING_AVG_CLR_C_M 0x8000
#define PATH0_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C 0x5664
#define PATH0_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C_M 0xF0000
#define PATH0_R_TSSI_DCK_MOVING_AVG_INI_DIS_C 0x5664
#define PATH0_R_TSSI_DCK_MOVING_AVG_INI_DIS_C_M 0x100000
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C 0x5668
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C_M 0x1
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C 0x5668
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C_M 0x2
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C 0x5668
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C_M 0x4
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_ON_C 0x5668
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_ON_C_M 0x8
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C 0x5668
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C_M 0x7F0
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C 0x5668
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C_M 0x800
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C 0x5668
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C_M 0x3F000
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C 0x5668
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C_M 0x40000
#define PATH0_R_TSSI_TIMEOUT_TIME_C 0x566C
#define PATH0_R_TSSI_TIMEOUT_TIME_C_M 0xFFF
#define PATH0_R_TSSI_TIMEOUT_UNIT_C 0x566C
#define PATH0_R_TSSI_TIMEOUT_UNIT_C_M 0x3000
#define PATH0_R_TXAGC_MAX_C 0x5800
#define PATH0_R_TXAGC_MAX_C_M 0xFF
#define PATH0_R_TXAGC_MIN_C 0x5800
#define PATH0_R_TXAGC_MIN_C_M 0xFF00
#define PATH0_R_TXAGC_RF_MAX_C 0x5800
#define PATH0_R_TXAGC_RF_MAX_C_M 0x3F0000
#define PATH0_R_TXAGC_RF_MIN_C 0x5800
#define PATH0_R_TXAGC_RF_MIN_C_M 0xFC00000
#define PATH0_R_DPD_OFST_EN_C 0x5800
#define PATH0_R_DPD_OFST_EN_C_M 0x10000000
#define PATH0_R_TXAGCSWING_EN_C 0x5800
#define PATH0_R_TXAGCSWING_EN_C_M 0x20000000
#define PATH0_R_DIS_CCK_SWING_TSSI_OFST_C 0x5800
#define PATH0_R_DIS_CCK_SWING_TSSI_OFST_C_M 0x40000000
#define PATH0_R_DIS_CCK_SWING_TXAGC_C 0x5800
#define PATH0_R_DIS_CCK_SWING_TXAGC_C_M 0x80000000
#define PATH0_R_TXAGC_OFDM_REF_DBM_C 0x5804
#define PATH0_R_TXAGC_OFDM_REF_DBM_C_M 0x1FF
#define PATH0_R_TXAGC_OFDM_REF_CW_C 0x5804
#define PATH0_R_TXAGC_OFDM_REF_CW_C_M 0x3FE00
#define PATH0_R_TSSI_MAP_OFST_OFDM_C 0x5804
#define PATH0_R_TSSI_MAP_OFST_OFDM_C_M 0x7FC0000
#define PATH0_R_DPD_OFST_C 0x5804
#define PATH0_R_DPD_OFST_C_M 0xF8000000
#define PATH0_R_TXAGC_CCK_REF_DBM_C 0x5808
#define PATH0_R_TXAGC_CCK_REF_DBM_C_M 0x1FF
#define PATH0_R_TXAGC_CCK_REF_CW_C 0x5808
#define PATH0_R_TXAGC_CCK_REF_CW_C_M 0x3FE00
#define PATH0_R_TSSI_MAP_OFST_CCK_C 0x5808
#define PATH0_R_TSSI_MAP_OFST_CCK_C_M 0x7FC0000
#define PATH0_R_TSSI_MAP_SLOPE_OFDM_C 0x580C
#define PATH0_R_TSSI_MAP_SLOPE_OFDM_C_M 0x7F
#define PATH0_R_TSSI_MAP_SLOPE_CCK_C 0x580C
#define PATH0_R_TSSI_MAP_SLOPE_CCK_C_M 0x7F00
#define PATH0_R_TXPW_FORCE_RDY_C 0x580C
#define PATH0_R_TXPW_FORCE_RDY_C_M 0x8000
#define PATH0_R_TSSI_ADC_DC_OFST_RE_C 0x580C
#define PATH0_R_TSSI_ADC_DC_OFST_RE_C_M 0xFFF0000
#define PATH0_R_TSSI_PARAM_OFDM_20M_ONLY_C 0x580C
#define PATH0_R_TSSI_PARAM_OFDM_20M_ONLY_C_M 0x10000000
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C 0x580C
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C_M 0x20000000
#define PATH0_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C 0x580C
#define PATH0_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x40000000
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C 0x580C
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x80000000
#define PATH0_R_TXAGC_PSEUDO_CW_C 0x5810
#define PATH0_R_TXAGC_PSEUDO_CW_C_M 0x1FF
#define PATH0_R_TXAGC_PSEUDO_CW_EN_C 0x5810
#define PATH0_R_TXAGC_PSEUDO_CW_EN_C_M 0x200
#define PATH0_R_TMETER_T0_C 0x5810
#define PATH0_R_TMETER_T0_C_M 0xFC00
#define PATH0_R_DIS_TSSI_F_C 0x5810
#define PATH0_R_DIS_TSSI_F_C_M 0x10000
#define PATH0_R_TMETER_TBL_RA_C 0x5810
#define PATH0_R_TMETER_TBL_RA_C_M 0x7E0000
#define PATH0_R_TMETER_TBL_RD_C 0x5810
#define PATH0_R_TMETER_TBL_RD_C_M 0x800000
#define PATH0_R_TSSI_THERMAL_PW_TRK_EN_C 0x5810
#define PATH0_R_TSSI_THERMAL_PW_TRK_EN_C_M 0x1000000
#define PATH0_R_TMETER_TBL_FORCE_WEN_C 0x5810
#define PATH0_R_TMETER_TBL_FORCE_WEN_C_M 0x2000000
#define PATH0_R_TMETER_TBL_FORCE_REN_C 0x5810
#define PATH0_R_TMETER_TBL_FORCE_REN_C_M 0x4000000
#define PATH0_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C 0x5810
#define PATH0_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C_M 0x8000000
#define PATH0_R_TSSI_DONT_USE_UPD_ADC_C 0x5810
#define PATH0_R_TSSI_DONT_USE_UPD_ADC_C_M 0x10000000
#define PATH0_R_TSSI_BYPASS_TSSI_FORCE_OFF_C 0x5810
#define PATH0_R_TSSI_BYPASS_TSSI_FORCE_OFF_C_M 0x20000000
#define PATH0_R_TSSI_DBG_PORT_EN_C 0x5810
#define PATH0_R_TSSI_DBG_PORT_EN_C_M 0x40000000
#define PATH0_R_TSSI_DONT_BND_ALOGK_TO_POS_C 0x5810
#define PATH0_R_TSSI_DONT_BND_ALOGK_TO_POS_C_M 0x80000000
#define PATH0_R_TSSI_RF_GAP_TBL_RA_C 0x5814
#define PATH0_R_TSSI_RF_GAP_TBL_RA_C_M 0x3F
#define PATH0_R_TSSI_RF_GAP_EN_C 0x5814
#define PATH0_R_TSSI_RF_GAP_EN_C_M 0x40
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_WEN_C 0x5814
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_WEN_C_M 0x80
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_REN_C 0x5814
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_REN_C_M 0x100
#define PATH0_R_TSSI_RF_GAP_TBL_RD_C 0x5814
#define PATH0_R_TSSI_RF_GAP_TBL_RD_C_M 0x200
#define PATH0_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C 0x5814
#define PATH0_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C_M 0x400
#define PATH0_R_TSSI_BYPASS_TSSI_C_C 0x5814
#define PATH0_R_TSSI_BYPASS_TSSI_C_C_M 0x800
#define PATH0_R_TSSI_DCK_AUTO_BYPASS_UPD_C 0x5814
#define PATH0_R_TSSI_DCK_AUTO_BYPASS_UPD_C_M 0x1000
#define PATH0_R_TSSI_DCK_AUTO_EN_C 0x5814
#define PATH0_R_TSSI_DCK_AUTO_EN_C_M 0x2000
#define PATH0_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C 0x5814
#define PATH0_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C_M 0x4000
#define PATH0_R_TSSI_DCK_AUTO_AVG_POINT_C 0x5814
#define PATH0_R_TSSI_DCK_AUTO_AVG_POINT_C_M 0x38000
#define PATH0_R_TSSI_DCK_AUTO_START_DLY_C 0x5814
#define PATH0_R_TSSI_DCK_AUTO_START_DLY_C_M 0x3C0000
#define PATH0_R_TSSI_ADC_AMPLIFY_C 0x5814
#define PATH0_R_TSSI_ADC_AMPLIFY_C_M 0xC00000
#define PATH0_R_TSSI_PW_TRK_USE_025DB_C 0x5814
#define PATH0_R_TSSI_PW_TRK_USE_025DB_C_M 0x1000000
#define PATH0_R_TSSI_DCK_SEL_C 0x5814
#define PATH0_R_TSSI_DCK_SEL_C_M 0x18000000
#define PATH0_R_TSSI_TXADC_PW_SV_EN_C 0x5814
#define PATH0_R_TSSI_TXADC_PW_SV_EN_C_M 0x20000000
#define PATH0_R_TSSI_RF_GAP_DE_CMB_OPT_C 0x5814
#define PATH0_R_TSSI_RF_GAP_DE_CMB_OPT_C_M 0x40000000
#define PATH0_R_TSSI_RF_GAP_DE_OFST_EN_C 0x5814
#define PATH0_R_TSSI_RF_GAP_DE_OFST_EN_C_M 0x80000000
#define PATH0_R_TXAGC_OFST_C 0x5818
#define PATH0_R_TXAGC_OFST_C_M 0xFF
#define PATH0_R_HE_ER_STF_PW_OFST_C 0x5818
#define PATH0_R_HE_ER_STF_PW_OFST_C_M 0x1FF00
#define PATH0_R_HE_STF_PW_OFST_C 0x5818
#define PATH0_R_HE_STF_PW_OFST_C_M 0x3FE0000
#define PATH0_R_TSSI_OSCILLATION_CNT_CLR_C 0x5818
#define PATH0_R_TSSI_OSCILLATION_CNT_CLR_C_M 0x4000000
#define PATH0_R_TSSI_OFST_BY_RFC_C 0x5818
#define PATH0_R_TSSI_OFST_BY_RFC_C_M 0x8000000
#define PATH0_R_TSSI_PW_TRK_AUTO_EN_C 0x5818
#define PATH0_R_TSSI_PW_TRK_AUTO_EN_C_M 0x10000000
#define PATH0_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C 0x5818
#define PATH0_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C_M 0x20000000
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_EN_C 0x5818
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_EN_C_M 0x40000000
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C 0x5818
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C_M 0x80000000
#define PATH0_R_TSSI_ADC_AVG_POINT_CCK_C 0x581C
#define PATH0_R_TSSI_ADC_AVG_POINT_CCK_C_M 0x3FF
#define PATH0_R_TSSI_ADC_AVG_POINT_OFDM_C 0x581C
#define PATH0_R_TSSI_ADC_AVG_POINT_OFDM_C_M 0xFFC00
#define PATH0_R_TSSI_SLOPE_CAL_EN_C 0x581C
#define PATH0_R_TSSI_SLOPE_CAL_EN_C_M 0x100000
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C 0x581C
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C_M 0x1E00000
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C 0x581C
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C_M 0x1E000000
#define PATH0_R_TSSI_ADC_NON_SQUARE_EN_C 0x581C
#define PATH0_R_TSSI_ADC_NON_SQUARE_EN_C_M 0x20000000
#define PATH0_R_TSSI_PSEUDO_TRK_MOD_EN_C 0x581C
#define PATH0_R_TSSI_PSEUDO_TRK_MOD_EN_C_M 0x80000000
#define PATH0_R_TSSI_SLOPE_A_C 0x5820
#define PATH0_R_TSSI_SLOPE_A_C_M 0xFFF
#define PATH0_R_TSSI_PKT_AVG_NUM_C 0x5820
#define PATH0_R_TSSI_PKT_AVG_NUM_C_M 0xF000
#define PATH0_R_TSSI_PW_TRK_SWING_LIM_C 0x5820
#define PATH0_R_TSSI_PW_TRK_SWING_LIM_C_M 0x1F0000
#define PATH0_R_TSSI_PW_TRK_SW_OFST_C 0x5820
#define PATH0_R_TSSI_PW_TRK_SW_OFST_C_M 0x1FE00000
#define PATH0_R_TSSI_ISEPA_C 0x5820
#define PATH0_R_TSSI_ISEPA_C_M 0x40000000
#define PATH0_R_TSSI_EN_C 0x5820
#define PATH0_R_TSSI_EN_C_M 0x80000000
#define PATH0_R_TSSI_A_OFDM_5M_C 0x5824
#define PATH0_R_TSSI_A_OFDM_5M_C_M 0x3FFFF
#define PATH0_R_TSSI_B_OFDM_5M_C 0x5824
#define PATH0_R_TSSI_B_OFDM_5M_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_OFDM_5M_C 0x5828
#define PATH0_R_TSSI_K_OFDM_5M_C_M 0xFFF
#define PATH0_R_TSSI_DE_OFDM_5M_C 0x5828
#define PATH0_R_TSSI_DE_OFDM_5M_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C 0x5828
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C_M 0x7FC00000
#define PATH0_R_TSSI_A_OFDM_10M_C 0x582C
#define PATH0_R_TSSI_A_OFDM_10M_C_M 0x3FFFF
#define PATH0_R_TSSI_B_OFDM_10M_C 0x582C
#define PATH0_R_TSSI_B_OFDM_10M_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_OFDM_10M_C 0x5830
#define PATH0_R_TSSI_K_OFDM_10M_C_M 0xFFF
#define PATH0_R_TSSI_DE_OFDM_10M_C 0x5830
#define PATH0_R_TSSI_DE_OFDM_10M_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C 0x5830
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C_M 0x7FC00000
#define PATH0_R_TSSI_A_OFDM_20M_C 0x5834
#define PATH0_R_TSSI_A_OFDM_20M_C_M 0x3FFFF
#define PATH0_R_TSSI_B_OFDM_20M_C 0x5834
#define PATH0_R_TSSI_B_OFDM_20M_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_OFDM_20M_C 0x5838
#define PATH0_R_TSSI_K_OFDM_20M_C_M 0xFFF
#define PATH0_R_TSSI_DE_OFDM_20M_C 0x5838
#define PATH0_R_TSSI_DE_OFDM_20M_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C 0x5838
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C_M 0x7FC00000
#define PATH0_R_TSSI_A_OFDM_40M_C 0x583C
#define PATH0_R_TSSI_A_OFDM_40M_C_M 0x3FFFF
#define PATH0_R_TSSI_B_OFDM_40M_C 0x583C
#define PATH0_R_TSSI_B_OFDM_40M_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_OFDM_40M_C 0x5840
#define PATH0_R_TSSI_K_OFDM_40M_C_M 0xFFF
#define PATH0_R_TSSI_DE_OFDM_40M_C 0x5840
#define PATH0_R_TSSI_DE_OFDM_40M_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C 0x5840
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C_M 0x7FC00000
#define PATH0_R_TSSI_A_OFDM_80M_C 0x5844
#define PATH0_R_TSSI_A_OFDM_80M_C_M 0x3FFFF
#define PATH0_R_TSSI_B_OFDM_80M_C 0x5844
#define PATH0_R_TSSI_B_OFDM_80M_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_OFDM_80M_C 0x5848
#define PATH0_R_TSSI_K_OFDM_80M_C_M 0xFFF
#define PATH0_R_TSSI_DE_OFDM_80M_C 0x5848
#define PATH0_R_TSSI_DE_OFDM_80M_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C 0x5848
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C_M 0x7FC00000
#define PATH0_R_TSSI_A_OFDM_80_80M_C 0x584C
#define PATH0_R_TSSI_A_OFDM_80_80M_C_M 0x3FFFF
#define PATH0_R_TSSI_B_OFDM_80_80M_C 0x584C
#define PATH0_R_TSSI_B_OFDM_80_80M_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_OFDM_80_80M_C 0x5850
#define PATH0_R_TSSI_K_OFDM_80_80M_C_M 0xFFF
#define PATH0_R_TSSI_DE_OFDM_80_80M_C 0x5850
#define PATH0_R_TSSI_DE_OFDM_80_80M_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C 0x5850
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C_M 0x7FC00000
#define PATH0_R_TSSI_A_CCK_LONG_C 0x5854
#define PATH0_R_TSSI_A_CCK_LONG_C_M 0x3FFFF
#define PATH0_R_TSSI_B_CCK_LONG_C 0x5854
#define PATH0_R_TSSI_B_CCK_LONG_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_CCK_LONG_C 0x5858
#define PATH0_R_TSSI_K_CCK_LONG_C_M 0xFFF
#define PATH0_R_TSSI_DE_CCK_LONG_C 0x5858
#define PATH0_R_TSSI_DE_CCK_LONG_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C 0x5858
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C_M 0x7FC00000
#define PATH0_R_TSSI_A_CCK_SHORT_C 0x585C
#define PATH0_R_TSSI_A_CCK_SHORT_C_M 0x3FFFF
#define PATH0_R_TSSI_B_CCK_SHORT_C 0x585C
#define PATH0_R_TSSI_B_CCK_SHORT_C_M 0x3FFC0000
#define PATH0_R_TSSI_K_CCK_SHORT_C 0x5860
#define PATH0_R_TSSI_K_CCK_SHORT_C_M 0xFFF
#define PATH0_R_TSSI_DE_CCK_SHORT_C 0x5860
#define PATH0_R_TSSI_DE_CCK_SHORT_C_M 0x3FF000
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C 0x5860
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C_M 0x7FC00000
#define PATH0_RSWING_NO_LIM_C 0x5860
#define PATH0_RSWING_NO_LIM_C_M 0x80000000
#define PATH0_R_TSSI_DELTA_CODE_MAX_C 0x5864
#define PATH0_R_TSSI_DELTA_CODE_MAX_C_M 0x3FF
#define PATH0_R_TSSI_DELTA_CODE_MIN_C 0x5864
#define PATH0_R_TSSI_DELTA_CODE_MIN_C_M 0xFFC00
#define PATH0_R_RFC_TMETER_T1_FORCE_VAL_C 0x5864
#define PATH0_R_RFC_TMETER_T1_FORCE_VAL_C_M 0x3F00000
#define PATH0_R_RFC_TMETER_T1_FORCE_ON_C 0x5864
#define PATH0_R_RFC_TMETER_T1_FORCE_ON_C_M 0x4000000
#define PATH0_R_GOTHROUGH_TX_IQKDPK_C 0x5864
#define PATH0_R_GOTHROUGH_TX_IQKDPK_C_M 0x8000000
#define PATH0_R_GOTHROUGH_RX_IQKDPK_C 0x5864
#define PATH0_R_GOTHROUGH_RX_IQKDPK_C_M 0x10000000
#define PATH0_R_IQK_IO_RFC_EN_C 0x5864
#define PATH0_R_IQK_IO_RFC_EN_C_M 0x20000000
#define PATH0_R_TX_IMFIR2_FORCE_RDY_C 0x5864
#define PATH0_R_TX_IMFIR2_FORCE_RDY_C_M 0x40000000
#define PATH0_R_CLK_GATING_TD_PATH_FORCE_ON_C 0x5864
#define PATH0_R_CLK_GATING_TD_PATH_FORCE_ON_C_M 0x80000000
#define PATH0_R_ANT_TRAIN_EN_C 0x5868
#define PATH0_R_ANT_TRAIN_EN_C_M 0x1
#define PATH0_R_TX_ANT_SEL_C 0x5868
#define PATH0_R_TX_ANT_SEL_C_M 0x2
#define PATH0_R_RFE_BUF_EN_C 0x5868
#define PATH0_R_RFE_BUF_EN_C_M 0x4
#define PATH0_R_LNAON_AGC_C 0x5868
#define PATH0_R_LNAON_AGC_C_M 0x8
#define PATH0_R_TRSW_BIT_BT_C 0x5868
#define PATH0_R_TRSW_BIT_BT_C_M 0x10
#define PATH0_R_TRSW_S_C 0x5868
#define PATH0_R_TRSW_S_C_M 0x20
#define PATH0_R_TRSW_O_C 0x5868
#define PATH0_R_TRSW_O_C_M 0x40
#define PATH0_R_TRSWB_O_C 0x5868
#define PATH0_R_TRSWB_O_C_M 0x80
#define PATH0_R_BT_FORCE_ANTIDX_C 0x5868
#define PATH0_R_BT_FORCE_ANTIDX_C_M 0xF00
#define PATH0_R_BT_FORCE_ANTIDX_EN_C 0x5868
#define PATH0_R_BT_FORCE_ANTIDX_EN_C_M 0x1000
#define PATH0_R_ANT_MODULE_RFE_OPT_C 0x5868
#define PATH0_R_ANT_MODULE_RFE_OPT_C_M 0xC000
#define PATH0_R_RFSW_TR_C 0x5868
#define PATH0_R_RFSW_TR_C_M 0xFFFF0000
#define PATH0_R_ANTSEL_C 0x586C
#define PATH0_R_ANTSEL_C_M 0xFFFFFFFF
#define PATH0_R_RFSW_ANT_31_0__C 0x5870
#define PATH0_R_RFSW_ANT_31_0__C_M 0xFFFFFFFF
#define PATH0_R_RFSW_ANT_63_32__C 0x5874
#define PATH0_R_RFSW_ANT_63_32__C_M 0xFFFFFFFF
#define PATH0_R_RFSW_ANT_95_64__C 0x5878
#define PATH0_R_RFSW_ANT_95_64__C_M 0xFFFFFFFF
#define PATH0_R_RFSW_ANT_127_96__C 0x587C
#define PATH0_R_RFSW_ANT_127_96__C_M 0xFFFFFFFF
#define PATH0_R_RFE_SEL_31_0__C 0x5880
#define PATH0_R_RFE_SEL_31_0__C_M 0xFFFFFFFF
#define PATH0_R_RFE_SEL_63_32__C 0x5884
#define PATH0_R_RFE_SEL_63_32__C_M 0xFFFFFFFF
#define PATH0_R_RFE_SEL_95_64__C 0x5888
#define PATH0_R_RFE_SEL_95_64__C_M 0xFFFFFFFF
#define PATH0_R_RFE_SEL_127_96__C 0x588C
#define PATH0_R_RFE_SEL_127_96__C_M 0xFFFFFFFF
#define PATH0_R_RFE_INV_C 0x5890
#define PATH0_R_RFE_INV_C_M 0xFFFFFFFF
#define PATH0_R_RFE_OPT_C 0x5894
#define PATH0_R_RFE_OPT_C_M 0xFFFFFFF
#define PATH0_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C 0x5894
#define PATH0_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C_M 0x10000000
#define PATH0_R_PATH_NOTRSW_BT_C 0x5894
#define PATH0_R_PATH_NOTRSW_BT_C_M 0x20000000
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C 0x5898
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C_M 0xFF
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C 0x5898
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C_M 0xFF00
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C 0x5898
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C_M 0xFF0000
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C 0x5898
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C_M 0xFF000000
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C 0x589C
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C_M 0xFF
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C 0x589C
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C_M 0xFF00
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C 0x589C
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C_M 0xFF0000
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C 0x589C
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C_M 0xFF000000
#define PATH0_R_HE_LSTF_PW_OFST_52_56_C 0x58A0
#define PATH0_R_HE_LSTF_PW_OFST_52_56_C_M 0xFF
#define PATH0_R_HE_LSTF_PW_OFST_52_56_2_C 0x58A0
#define PATH0_R_HE_LSTF_PW_OFST_52_56_2_C_M 0xFF00
#define PATH0_R_HE_LSTF_PW_OFST_52_56_4_C 0x58A0
#define PATH0_R_HE_LSTF_PW_OFST_52_56_4_C_M 0xFF0000
#define PATH0_R_HE_LSTF_PW_OFST_52_56_8_C 0x58A0
#define PATH0_R_HE_LSTF_PW_OFST_52_56_8_C_M 0xFF000000
#define PATH0_R_HE_LSTF_PW_OFST_52_56X2_C 0x58A4
#define PATH0_R_HE_LSTF_PW_OFST_52_56X2_C_M 0xFF
#define PATH0_R_TSSI_GAP_S0_C 0x58A4
#define PATH0_R_TSSI_GAP_S0_C_M 0x1FF00
#define PATH0_R_TSSI_GAP_S1_C 0x58A4
#define PATH0_R_TSSI_GAP_S1_C_M 0x3FE0000
#define PATH0_R_TSSI_GAP_S2_C 0x58A8
#define PATH0_R_TSSI_GAP_S2_C_M 0x1FF
#define PATH0_R_TSSI_GAP_S3_C 0x58A8
#define PATH0_R_TSSI_GAP_S3_C_M 0x3FE00
#define PATH0_R_TSSI_GAP_S4_C 0x58A8
#define PATH0_R_TSSI_GAP_S4_C_M 0x7FC0000
#define PATH0_R_TSSI_GAP_S5_C 0x58AC
#define PATH0_R_TSSI_GAP_S5_C_M 0x1FF
#define PATH0_R_TSSI_GAP_S6_C 0x58AC
#define PATH0_R_TSSI_GAP_S6_C_M 0x3FE00
#define PATH0_R_TSSI_GAP_S7_C 0x58AC
#define PATH0_R_TSSI_GAP_S7_C_M 0x7FC0000
#define PATH0_R_IQK_DPK_PATH_RST_C 0x58AC
#define PATH0_R_IQK_DPK_PATH_RST_C_M 0x8000000
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HT_C 0x58AC
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x10000000
#define PATH0_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x58AC
#define PATH0_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x20000000
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HE_C 0x58AC
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x40000000
#define PATH0_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x58AC
#define PATH0_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x80000000
#define PATH0_R_DAC_GAIN_COMP_TBL_RA_C 0x58B0
#define PATH0_R_DAC_GAIN_COMP_TBL_RA_C_M 0x7F
#define PATH0_R_DAC_GAIN_COMP_TBL_RD_C 0x58B0
#define PATH0_R_DAC_GAIN_COMP_TBL_RD_C_M 0x80
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C 0x58B0
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C_M 0x100
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_REN_C 0x58B0
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_REN_C_M 0x200
#define PATH0_R_DAC_GAIN_COMP_EN_C 0x58B0
#define PATH0_R_DAC_GAIN_COMP_EN_C_M 0x400
#define PATH0_R_TSSI_CW_COMP_EN_C 0x58B0
#define PATH0_R_TSSI_CW_COMP_EN_C_M 0x800
#define PATH0_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C 0x58B0
#define PATH0_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C_M 0x8000
#define PATH0_R_TSSI_OSCILLATION_HALT_TRK_TH_C 0x58B0
#define PATH0_R_TSSI_OSCILLATION_HALT_TRK_TH_C_M 0xFFFF0000
#define PATH0_R_TSSI_DBG_SEL_C 0x58B4
#define PATH0_R_TSSI_DBG_SEL_C_M 0x1F
#define PATH0_R_GAIN_TX_IPA_FORCE_ON_C 0x58B4
#define PATH0_R_GAIN_TX_IPA_FORCE_ON_C_M 0x20
#define PATH0_R_GAIN_TX_IPA_FORCE_VAL_C 0x58B4
#define PATH0_R_GAIN_TX_IPA_FORCE_VAL_C_M 0x1C0
#define PATH0_R_TXPW_TBL_IOQ_DIS_C 0x58B4
#define PATH0_R_TXPW_TBL_IOQ_DIS_C_M 0x200
#define PATH0_R_RFTXEN_SAMPLING_SHIFT_C 0x58B4
#define PATH0_R_RFTXEN_SAMPLING_SHIFT_C_M 0xF000
#define PATH0_R_TMETER_T0_CW_C 0x58B4
#define PATH0_R_TMETER_T0_CW_C_M 0xFF0000
#define PATH0_R_TSSI_F_WAIT_UPD_OFDM_C 0x58B4
#define PATH0_R_TSSI_F_WAIT_UPD_OFDM_C_M 0x7F000000
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_SHORT_C 0x58B8
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_SHORT_C_M 0x7F
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_LONG_C 0x58B8
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_LONG_C_M 0x7F00
#define PATH0_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C 0x58B8
#define PATH0_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C_M 0x7F0000
#define PATH0_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C 0x58B8
#define PATH0_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C_M 0x7F000000
#define PATH0_R_TXAGC_OFST_MAX_C 0x58BC
#define PATH0_R_TXAGC_OFST_MAX_C_M 0xFF
#define PATH0_R_TXAGC_OFST_MIN_C 0x58BC
#define PATH0_R_TXAGC_OFST_MIN_C_M 0xFF00
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_C_M 0x10000
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C_M 0x20000
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_C_M 0x40000
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C_M 0x80000
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_C_M 0x100000
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C_M 0x200000
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C_M 0x400000
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C_M 0x800000
#define PATH0_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C_M 0x1000000
#define PATH0_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C_M 0x2000000
#define PATH0_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C 0x58BC
#define PATH0_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C_M 0x4000000
#define PATH0_R_GAIN_TX_GAPK_FORCE_VAL_C 0x58C0
#define PATH0_R_GAIN_TX_GAPK_FORCE_VAL_C_M 0xF
#define PATH0_R_GAIN_TX_GAPK_FORCE_ON_C 0x58C0
#define PATH0_R_GAIN_TX_GAPK_FORCE_ON_C_M 0x10
#define PATH0_R_GAIN_TX_PAD_FORCE_VAL_C 0x58C0
#define PATH0_R_GAIN_TX_PAD_FORCE_VAL_C_M 0x3E0
#define PATH0_R_GAIN_TX_PAD_FORCE_ON_C 0x58C0
#define PATH0_R_GAIN_TX_PAD_FORCE_ON_C_M 0x400
#define PATH0_R_GAIN_TX_FORCE_VAL_C 0x58C0
#define PATH0_R_GAIN_TX_FORCE_VAL_C_M 0xF800
#define PATH0_R_GAIN_TX_FORCE_ON_C 0x58C0
#define PATH0_R_GAIN_TX_FORCE_ON_C_M 0x10000
#define PATH0_R_TSSISWING_LIM_PEAK_OFDM_C 0x58C0
#define PATH0_R_TSSISWING_LIM_PEAK_OFDM_C_M 0xE0000
#define PATH0_R_TSSISWING_LIM_PEAK_CCK_C 0x58C0
#define PATH0_R_TSSISWING_LIM_PEAK_CCK_C_M 0x700000
#define PATH0_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C 0x58C0
#define PATH0_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C_M 0x800000
#define PATH0_R_TSSI_TRACK_AT_SMALL_SWING_C 0x58C0
#define PATH0_R_TSSI_TRACK_AT_SMALL_SWING_C_M 0x1000000
#define PATH0_R_BYPASS_TSSI_CCK_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_CCK_EN_C_M 0x2000000
#define PATH0_R_BYPASS_TSSI_LEGACY_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_LEGACY_EN_C_M 0x4000000
#define PATH0_R_BYPASS_TSSI_HT_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_HT_EN_C_M 0x8000000
#define PATH0_R_BYPASS_TSSI_VHT_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_VHT_EN_C_M 0x10000000
#define PATH0_R_BYPASS_TSSI_HE_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_HE_EN_C_M 0x20000000
#define PATH0_R_BYPASS_TSSI_HE_ER_SU_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_HE_ER_SU_EN_C_M 0x40000000
#define PATH0_R_BYPASS_TSSI_HE_TB_EN_C 0x58C0
#define PATH0_R_BYPASS_TSSI_HE_TB_EN_C_M 0x80000000
#define PATH0_R_RF_GAP_CAL_BND0_C 0x58C4
#define PATH0_R_RF_GAP_CAL_BND0_C_M 0x3F
#define PATH0_R_RF_GAP_CAL_BND1_C 0x58C4
#define PATH0_R_RF_GAP_CAL_BND1_C_M 0xFC0
#define PATH0_R_RF_GAP_CAL_BND2_C 0x58C4
#define PATH0_R_RF_GAP_CAL_BND2_C_M 0x3F000
#define PATH0_R_TSSI_ADC_OFST_BND01_C 0x58C4
#define PATH0_R_TSSI_ADC_OFST_BND01_C_M 0x3FFC0000
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_EN_C 0x58C4
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_EN_C_M 0x40000000
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C 0x58C4
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C_M 0x80000000
#define PATH0_R_TSSI_ADC_OFST_BND12_C 0x58C8
#define PATH0_R_TSSI_ADC_OFST_BND12_C_M 0xFFF
#define PATH0_R_TSSI_ADC_OFST_BND22_C 0x58C8
#define PATH0_R_TSSI_ADC_OFST_BND22_C_M 0xFFF000
#define PATH0_R_ADC_FIFO_PATH_EN_FORCE_ON_C 0x58C8
#define PATH0_R_ADC_FIFO_PATH_EN_FORCE_ON_C_M 0x1000000
#define PATH0_R_TXINFO_CH_WITH_DATA_DECODE_C 0x58C8
#define PATH0_R_TXINFO_CH_WITH_DATA_DECODE_C_M 0x6000000
#define PATH0_R_BYPASS_TSSI_VHT_MU_EN_C 0x58C8
#define PATH0_R_BYPASS_TSSI_VHT_MU_EN_C_M 0x10000000
#define PATH0_R_BYPASS_TSSI_HE_MU_EN_C 0x58C8
#define PATH0_R_BYPASS_TSSI_HE_MU_EN_C_M 0x20000000
#define PATH0_R_BYPASS_TSSI_HE_RU_EN_C 0x58C8
#define PATH0_R_BYPASS_TSSI_HE_RU_EN_C_M 0x40000000
#define PATH0_R_BYPASS_TSSI_TXBF_EN_C 0x58C8
#define PATH0_R_BYPASS_TSSI_TXBF_EN_C_M 0x80000000
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL0_C 0x58CC
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL0_C_M 0x7
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL1_C 0x58CC
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL1_C_M 0x38
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL2_C 0x58CC
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL2_C_M 0x1C0
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL3_C 0x58CC
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL3_C_M 0xE00
#define PATH0_R_TSSI_SLOPE_CAL_SEL_IPA_C 0x58CC
#define PATH0_R_TSSI_SLOPE_CAL_SEL_IPA_C_M 0x1000
#define PATH0_R_TX_GAIN_CCK_MORE_ADJ_C 0x58CC
#define PATH0_R_TX_GAIN_CCK_MORE_ADJ_C_M 0xFF000000
#define PATH0_R_TX_GAIN_SCALE_FORCE_VAL_C 0x58D0
#define PATH0_R_TX_GAIN_SCALE_FORCE_VAL_C_M 0xFFF
#define PATH0_R_TX_GAIN_SCALE_FORCE_ON_C 0x58D0
#define PATH0_R_TX_GAIN_SCALE_FORCE_ON_C_M 0x1000
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_C 0x58D0
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_C_M 0x1E000
#define PATH0_R_TX_LSTF_PW_EST_LEN_C 0x58D0
#define PATH0_R_TX_LSTF_PW_EST_LEN_C_M 0x3FE0000
#define PATH0_R_TX_LSTF_PW_EST_SEL_EVEN_C 0x58D0
#define PATH0_R_TX_LSTF_PW_EST_SEL_EVEN_C_M 0x4000000
#define PATH0_R_TSSI_C_MAP_UNFIX_C 0x58D0
#define PATH0_R_TSSI_C_MAP_UNFIX_C_M 0x80000000
#define PATH0_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C 0x58D4
#define PATH0_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C_M 0xFF
#define PATH0_R_TSSI_BYPASS_TXPW_MAX_C 0x58D4
#define PATH0_R_TSSI_BYPASS_TXPW_MAX_C_M 0x3FE00
#define PATH0_R_TSSI_BYPASS_TXPW_MIN_C 0x58D4
#define PATH0_R_TSSI_BYPASS_TXPW_MIN_C_M 0x7FC0000
#define PATH0_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C 0x58D4
#define PATH0_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C_M 0x8000000
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C 0x58D4
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C_M 0x10000000
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_POST_C 0x58D4
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_POST_C_M 0x20000000
#define PATH0_R_TXPW_SPLIT_FOR_DPD_C 0x58D4
#define PATH0_R_TXPW_SPLIT_FOR_DPD_C_M 0x40000000
#define PATH0_R_TXAGC_TP_MASK_EN_C 0x58D4
#define PATH0_R_TXAGC_TP_MASK_EN_C_M 0x80000000
#define PATH0_R_TSSI_BYPASS_BY_C_MAX_C 0x58D8
#define PATH0_R_TSSI_BYPASS_BY_C_MAX_C_M 0x1FF
#define PATH0_R_TSSI_BYPASS_BY_C_MIN_C 0x58D8
#define PATH0_R_TSSI_BYPASS_BY_C_MIN_C_M 0x3FE00
#define PATH0_R_TSSI_BYPASS_BY_C_SEL_C 0x58D8
#define PATH0_R_TSSI_BYPASS_BY_C_SEL_C_M 0xC0000
#define PATH0_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C 0x58D8
#define PATH0_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C_M 0xFFF00000
#define PATH0_R_TXAGC_OFST_FIX_ERR_MAX_C 0x58DC
#define PATH0_R_TXAGC_OFST_FIX_ERR_MAX_C_M 0xFF
#define PATH0_R_TXAGC_OFST_FIX_ERR_MIN_C 0x58DC
#define PATH0_R_TXAGC_OFST_FIX_ERR_MIN_C_M 0xFF00
#define PATH0_R_TXAGC_OFST_FIX_C 0x58DC
#define PATH0_R_TXAGC_OFST_FIX_C_M 0x10000
#define PATH0_R_TSSI_C_FORCE_VAL_C 0x58DC
#define PATH0_R_TSSI_C_FORCE_VAL_C_M 0x1FF00000
#define PATH0_R_TSSI_C_FORCE_ON_C 0x58DC
#define PATH0_R_TSSI_C_FORCE_ON_C_M 0x20000000
#define PATH0_R_TXPW_RSTB_MAN_ON_C 0x58DC
#define PATH0_R_TXPW_RSTB_MAN_ON_C_M 0x40000000
#define PATH0_R_TXPW_RSTB_MAN_C 0x58DC
#define PATH0_R_TXPW_RSTB_MAN_C_M 0x80000000
#define PATH0_R_TXAGC_OFDM_REF_CW_OFST_C 0x58E0
#define PATH0_R_TXAGC_OFDM_REF_CW_OFST_C_M 0x3FF
#define PATH0_R_TXAGC_CCK_REF_CW_OFST_C 0x58E0
#define PATH0_R_TXAGC_CCK_REF_CW_OFST_C_M 0x3FF000
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C 0x58E0
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C_M 0x7F000000
#define PATH0_R_TXPW_RDY_NO_DLY_C 0x58E0
#define PATH0_R_TXPW_RDY_NO_DLY_C_M 0x80000000
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C 0x58E4
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C_M 0x7F
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C 0x58E4
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C_M 0x80
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C 0x58E4
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C_M 0x700
#define PATH0_R_TXAGC_OFST_MOVING_AVG_LEN_C 0x58E4
#define PATH0_R_TXAGC_OFST_MOVING_AVG_LEN_C_M 0x3800
#define PATH0_R_TXAGC_OFST_MOVING_AVG_CLR_C 0x58E4
#define PATH0_R_TXAGC_OFST_MOVING_AVG_CLR_C_M 0x4000
#define PATH0_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C 0x58E4
#define PATH0_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C_M 0x8000
#define PATH0_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C 0x58E4
#define PATH0_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C_M 0xF0000
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C 0x58E4
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C_M 0x7F00000
#define PATH0_R_TXPW_RSTB_SUB_SEL_C 0x58E4
#define PATH0_R_TXPW_RSTB_SUB_SEL_C_M 0x8000000
#define PATH0_R_TXPW_RSTB_SUB_C 0x58E4
#define PATH0_R_TXPW_RSTB_SUB_C_M 0x10000000
#define PATH0_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C 0x58E4
#define PATH0_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C_M 0x20000000
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MAX_C 0x58F0
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MAX_C_M 0x1FF
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MIN_C 0x58F0
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MIN_C_M 0x3FE00
#define PATH0_R_GOTHROUGH_TX_GAIN_POST_DPD_C 0x58F0
#define PATH0_R_GOTHROUGH_TX_GAIN_POST_DPD_C_M 0x40000
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C 0x58F0
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C_M 0x80000
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C 0x58F0
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C_M 0xFFF00000
#define PATH0_R_RF_GAP_CAL_OFST_BND00_10BITS_C 0x58F4
#define PATH0_R_RF_GAP_CAL_OFST_BND00_10BITS_C_M 0x3FF
#define PATH0_R_RF_GAP_CAL_OFST_BND01_10BITS_C 0x58F4
#define PATH0_R_RF_GAP_CAL_OFST_BND01_10BITS_C_M 0xFFC00
#define PATH0_R_RF_GAP_CAL_OFST_BND12_10BITS_C 0x58F4
#define PATH0_R_RF_GAP_CAL_OFST_BND12_10BITS_C_M 0x3FF00000
#define PATH0_R_RF_GAP_CAL_OFST_BND22_10BITS_C 0x58F8
#define PATH0_R_RF_GAP_CAL_OFST_BND22_10BITS_C_M 0x3FF
#define PATH0_R_LOG_VAL_OFST_CCK_C 0x58F8
#define PATH0_R_LOG_VAL_OFST_CCK_C_M 0x3FFFFC00
#define PATH0_R_TSSI_ADC_PATH_Q_C 0x58F8
#define PATH0_R_TSSI_ADC_PATH_Q_C_M 0x40000000
#define PATH0_R_DAC_COMP_POST_DPD_EN_C 0x58F8
#define PATH0_R_DAC_COMP_POST_DPD_EN_C_M 0x80000000
#define PATH0_R_LOG_VAL_OFST_OFDM_C 0x58FC
#define PATH0_R_LOG_VAL_OFST_OFDM_C_M 0xFFFFF
#define PATH0_R_UPD_TXAGC_OFST_LATENCY_C 0x58FC
#define PATH0_R_UPD_TXAGC_OFST_LATENCY_C_M 0x700000
#define PATH0_R_TSSI_UPD_TMETER_EN_C 0x58FC
#define PATH0_R_TSSI_UPD_TMETER_EN_C_M 0x800000
#define PATH0_R_TXRFC_BW_TXFORCE_VAL_C 0x58FC
#define PATH0_R_TXRFC_BW_TXFORCE_VAL_C_M 0x3000000
#define PATH0_R_TXRFC_BW_TXFORCE_ON_C 0x58FC
#define PATH0_R_TXRFC_BW_TXFORCE_ON_C_M 0x4000000
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_ON_C 0x58FC
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_ON_C_M 0x8000000
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_VAL_C 0x58FC
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_VAL_C_M 0x10000000
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C 0x5A00
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C 0x5A00
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C 0x5A04
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C 0x5A04
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C 0x5A08
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C 0x5A08
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C 0x5A0C
#define PATH0_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C 0x5A0C
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C 0x5A10
#define PATH0_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C 0x5A10
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C 0x5A14
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C 0x5A14
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C 0x5A18
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C 0x5A18
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C 0x5A1C
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C 0x5A1C
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C 0x5A20
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C 0x5A20
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_VHT_80_TXSC0_C 0x5A24
#define PATH0_R_DAC_GAIN_COMP_VHT_80_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C 0x5A24
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C 0x5A28
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C 0x5A28
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C 0x5A2C
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C 0x5A2C
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C 0x5A30
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C 0x5A30
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C 0x5A34
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C 0x5A34
#define PATH0_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C 0x5A38
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C 0x5A38
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C 0x5A3C
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C 0x5A3C
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C 0x5A40
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C 0x5A40
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C 0x5A44
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C 0x5A44
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C 0x5A48
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C 0x5A48
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C 0x5A4C
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C 0x5A4C
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C 0x5A50
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C 0x5A50
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C 0x5A54
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C 0x5A54
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C 0x5A58
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C 0x5A58
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C 0x5A5C
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C 0x5A5C
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C 0x5A60
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C 0x5A60
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C 0x5A64
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C 0x5A64
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C 0x5A68
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C 0x5A68
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C 0x5A6C
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C 0x5A6C
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C 0x5A70
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C 0x5A70
#define PATH0_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C 0x5A74
#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C 0x5A74
#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C 0x5A78
#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C 0x5A78
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C 0x5A7C
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C 0x5A7C
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C 0x5A80
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C 0x5A80
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C 0x5A84
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C 0x5A84
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C 0x5A88
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C 0x5A88
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C 0x5A8C
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C 0x5A8C
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C 0x5A90
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C 0x5A90
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C 0x5A94
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C 0x5A94
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C 0x5A98
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C 0x5A98
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C 0x5A9C
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C 0x5A9C
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C 0x5AA0
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C 0x5AA0
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C 0x5AA4
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C 0x5AA4
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C 0x5AA8
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C 0x5AA8
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C 0x5AAC
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C 0x5AAC
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C 0x5AB0
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C 0x5AB0
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C 0x5AB4
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C 0x5AB4
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C 0x5AB8
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C 0x5AB8
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C 0x5ABC
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C 0x5ABC
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C_M 0xFFFF0000
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C 0x5AC0
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C_M 0xFFFF
#define PATH0_R_DAC_GAIN_COMP_UNEXPECTED_C 0x5AC0
#define PATH0_R_DAC_GAIN_COMP_UNEXPECTED_C_M 0xFFFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS0_C 0x5C00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS0_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS1_C 0x5C00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS1_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS2_C 0x5C00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS2_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS3_C 0x5C00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS3_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS4_C 0x5C04
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS4_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS5_C 0x5C04
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS5_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS6_C 0x5C04
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS6_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS7_C 0x5C04
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS7_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS8_C 0x5C08
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS8_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS9_C 0x5C08
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS9_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS10_C 0x5C08
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS10_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS11_C 0x5C08
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS11_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS12_C 0x5C0C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS12_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS13_C 0x5C0C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS13_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS14_C 0x5C0C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS14_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS15_C 0x5C0C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS15_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS16_C 0x5C10
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS16_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS17_C 0x5C10
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS17_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS18_C 0x5C10
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS18_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS19_C 0x5C10
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS19_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS20_C 0x5C14
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS20_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS21_C 0x5C14
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS21_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS22_C 0x5C14
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS22_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS23_C 0x5C14
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS23_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS24_C 0x5C18
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS24_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS25_C 0x5C18
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS25_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS26_C 0x5C18
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS26_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS27_C 0x5C18
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS27_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS28_C 0x5C1C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS28_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS29_C 0x5C1C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS29_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS30_C 0x5C1C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS30_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS31_C 0x5C1C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS31_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG32_C 0x5C20
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG32_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG31_C 0x5C20
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG31_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG30_C 0x5C20
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG30_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG29_C 0x5C20
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG29_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG28_C 0x5C24
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG28_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG27_C 0x5C24
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG27_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG26_C 0x5C24
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG26_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG25_C 0x5C24
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG25_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG24_C 0x5C28
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG24_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG23_C 0x5C28
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG23_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG22_C 0x5C28
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG22_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG21_C 0x5C28
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG21_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG20_C 0x5C2C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG20_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG19_C 0x5C2C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG19_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG18_C 0x5C2C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG18_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG17_C 0x5C2C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG17_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG16_C 0x5C30
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG16_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG15_C 0x5C30
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG15_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG14_C 0x5C30
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG14_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG13_C 0x5C30
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG13_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG12_C 0x5C34
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG12_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG11_C 0x5C34
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG11_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG10_C 0x5C34
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG10_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG9_C 0x5C34
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG9_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG8_C 0x5C38
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG8_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG7_C 0x5C38
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG7_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG6_C 0x5C38
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG6_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG5_C 0x5C38
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG5_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG4_C 0x5C3C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG4_C_M 0xFF
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG3_C 0x5C3C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG3_C_M 0xFF00
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG2_C 0x5C3C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG2_C_M 0xFF0000
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG1_C 0x5C3C
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG1_C_M 0xFF000000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_0_C 0x5C40
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_0_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_1_C 0x5C40
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_1_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_2_C 0x5C44
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_2_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_3_C 0x5C44
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_3_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_4_C 0x5C48
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_4_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_5_C 0x5C48
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_5_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_6_C 0x5C4C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_6_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_7_C 0x5C4C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_7_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_8_C 0x5C50
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_8_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_9_C 0x5C50
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_9_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_10_C 0x5C54
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_10_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_11_C 0x5C54
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_11_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_12_C 0x5C58
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_12_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_13_C 0x5C58
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_13_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_14_C 0x5C5C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_14_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_15_C 0x5C5C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_15_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_16_C 0x5C60
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_16_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_17_C 0x5C60
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_17_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_18_C 0x5C64
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_18_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_19_C 0x5C64
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_19_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_20_C 0x5C68
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_20_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_21_C 0x5C68
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_21_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_22_C 0x5C6C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_22_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_23_C 0x5C6C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_23_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_24_C 0x5C70
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_24_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_25_C 0x5C70
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_25_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_26_C 0x5C74
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_26_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_27_C 0x5C74
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_27_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_28_C 0x5C78
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_28_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_29_C 0x5C78
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_29_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_30_C 0x5C7C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_30_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_31_C 0x5C7C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_31_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_32_C 0x5C80
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_32_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_33_C 0x5C80
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_33_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_34_C 0x5C84
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_34_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_35_C 0x5C84
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_35_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_36_C 0x5C88
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_36_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_37_C 0x5C88
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_37_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_38_C 0x5C8C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_38_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_39_C 0x5C8C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_39_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_40_C 0x5C90
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_40_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_41_C 0x5C90
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_41_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_42_C 0x5C94
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_42_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_43_C 0x5C94
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_43_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_44_C 0x5C98
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_44_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_45_C 0x5C98
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_45_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_46_C 0x5C9C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_46_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_47_C 0x5C9C
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_47_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_48_C 0x5CA0
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_48_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_49_C 0x5CA0
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_49_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_50_C 0x5CA4
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_50_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_51_C 0x5CA4
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_51_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_52_C 0x5CA8
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_52_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_53_C 0x5CA8
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_53_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_54_C 0x5CAC
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_54_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_55_C 0x5CAC
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_55_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_56_C 0x5CB0
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_56_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_57_C 0x5CB0
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_57_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_58_C 0x5CB4
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_58_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_59_C 0x5CB4
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_59_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_60_C 0x5CB8
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_60_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_61_C 0x5CB8
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_61_C_M 0x3FF0000
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_62_C 0x5CBC
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_62_C_M 0x3FF
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_63_C 0x5CBC
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_63_C_M 0x3FF0000
#define PATH1_R_TSSI_CURVE_P0_C 0x7600
#define PATH1_R_TSSI_CURVE_P0_C_M 0x3F
#define PATH1_R_TSSI_CURVE_P1_C 0x7600
#define PATH1_R_TSSI_CURVE_P1_C_M 0x3F00
#define PATH1_R_TSSI_CURVE_P2_C 0x7600
#define PATH1_R_TSSI_CURVE_P2_C_M 0x3F0000
#define PATH1_R_TSSI_CURVE_P3_C 0x7600
#define PATH1_R_TSSI_CURVE_P3_C_M 0x3F000000
#define PATH1_R_TSSI_CURVE_P4_C 0x7604
#define PATH1_R_TSSI_CURVE_P4_C_M 0x3F
#define PATH1_R_TSSI_CURVE_P5_C 0x7604
#define PATH1_R_TSSI_CURVE_P5_C_M 0x3F00
#define PATH1_R_TSSI_CURVE_P6_C 0x7604
#define PATH1_R_TSSI_CURVE_P6_C_M 0x3F0000
#define PATH1_R_TSSI_CURVE_EN_C 0x7604
#define PATH1_R_TSSI_CURVE_EN_C_M 0x80000000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C 0x7608
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C_M 0x1FF
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C 0x7608
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C_M 0x3FE00
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C 0x7608
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C_M 0x7FC0000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C 0x760C
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C_M 0x1FF
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C 0x760C
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C_M 0x3FE00
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C 0x760C
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C_M 0x7FC0000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C 0x7610
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C_M 0x1FF
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C 0x7610
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C_M 0x3FE00
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C 0x7610
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C_M 0x7FC0000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C 0x7614
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C_M 0x1FF
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C 0x7614
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C_M 0x3FE00
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C 0x7614
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C_M 0x7FC0000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C 0x7618
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C_M 0x1FF
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C 0x7618
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C_M 0x3FE00
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C 0x7618
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C_M 0x7FC0000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C 0x761C
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C_M 0x1FF
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C 0x761C
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C_M 0xFF0000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C 0x761C
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C_M 0xFF000000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C 0x7620
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C_M 0xFF
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C 0x7620
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C_M 0xFF00
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C 0x7620
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C_M 0xFF0000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C 0x7620
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C_M 0xFF000000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C 0x7624
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C_M 0xFF
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C 0x7624
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C_M 0xFF00
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C 0x7624
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C_M 0xFF0000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C 0x7624
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C_M 0xFF000000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C 0x7628
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C_M 0xFF
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C 0x7628
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C_M 0xFF00
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C 0x7628
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C_M 0xFF0000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C 0x7628
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C_M 0xFF000000
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C 0x762C
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C_M 0xFF
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C 0x762C
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C_M 0xFF00
#define PATH1_R_TSSI_J_OFDM_G0_C 0x7630
#define PATH1_R_TSSI_J_OFDM_G0_C_M 0x3FF
#define PATH1_R_TSSI_J_OFDM_G1_C 0x7630
#define PATH1_R_TSSI_J_OFDM_G1_C_M 0xFFC00
#define PATH1_R_TSSI_J_OFDM_G2_C 0x7630
#define PATH1_R_TSSI_J_OFDM_G2_C_M 0x3FF00000
#define PATH1_R_TSSI_J_OFDM_G3_C 0x7634
#define PATH1_R_TSSI_J_OFDM_G3_C_M 0x3FF
#define PATH1_R_TSSI_J_OFDM_G4_C 0x7634
#define PATH1_R_TSSI_J_OFDM_G4_C_M 0xFFC00
#define PATH1_R_TSSI_J_OFDM_G5_C 0x7634
#define PATH1_R_TSSI_J_OFDM_G5_C_M 0x3FF00000
#define PATH1_R_TSSI_J_OFDM_G6_C 0x7638
#define PATH1_R_TSSI_J_OFDM_G6_C_M 0x3FF
#define PATH1_R_TSSI_J_OFDM_G7_C 0x7638
#define PATH1_R_TSSI_J_OFDM_G7_C_M 0xFFC00
#define PATH1_R_TSSI_J_CCK_G0_C 0x763C
#define PATH1_R_TSSI_J_CCK_G0_C_M 0x3FF
#define PATH1_R_TSSI_J_CCK_G1_C 0x763C
#define PATH1_R_TSSI_J_CCK_G1_C_M 0xFFC00
#define PATH1_R_TSSI_J_CCK_G2_C 0x763C
#define PATH1_R_TSSI_J_CCK_G2_C_M 0x3FF00000
#define PATH1_R_TSSI_J_CCK_G3_C 0x7640
#define PATH1_R_TSSI_J_CCK_G3_C_M 0x3FF
#define PATH1_R_TSSI_J_CCK_G4_C 0x7640
#define PATH1_R_TSSI_J_CCK_G4_C_M 0xFFC00
#define PATH1_R_TSSI_J_CCK_G5_C 0x7640
#define PATH1_R_TSSI_J_CCK_G5_C_M 0x3FF00000
#define PATH1_R_TSSI_J_CCK_G6_C 0x7644
#define PATH1_R_TSSI_J_CCK_G6_C_M 0x3FF
#define PATH1_R_TSSI_J_CCK_G7_C 0x7644
#define PATH1_R_TSSI_J_CCK_G7_C_M 0xFFC00
#define PATH1_R_TXRFC_RFMODE_FORCE_VAL_C 0x7648
#define PATH1_R_TXRFC_RFMODE_FORCE_VAL_C_M 0xF
#define PATH1_R_TXRFC_RFMODE_FORCE_ON_C 0x7648
#define PATH1_R_TXRFC_RFMODE_FORCE_ON_C_M 0x10
#define PATH1_R_TXRFC_TSSI_OFST_FORCE_VAL_C 0x7648
#define PATH1_R_TXRFC_TSSI_OFST_FORCE_VAL_C_M 0x3E0
#define PATH1_R_TXRFC_TSSI_OFST_FORCE_ON_C 0x7648
#define PATH1_R_TXRFC_TSSI_OFST_FORCE_ON_C_M 0x400
#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_VAL_C 0x7648
#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_VAL_C_M 0x800
#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_ON_C 0x7648
#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_ON_C_M 0x1000
#define PATH1_R_TXRFC_TXAGC_RF_FORCE_VAL_C 0x7648
#define PATH1_R_TXRFC_TXAGC_RF_FORCE_VAL_C_M 0x7E000
#define PATH1_R_TXRFC_TXAGC_RF_FORCE_ON_C 0x7648
#define PATH1_R_TXRFC_TXAGC_RF_FORCE_ON_C_M 0x80000
#define PATH1_R_TXRFC_GAIN_TX_FORCE_VAL_C 0x764C
#define PATH1_R_TXRFC_GAIN_TX_FORCE_VAL_C_M 0x1F
#define PATH1_R_TXRFC_GAIN_TX_FORCE_ON_C 0x764C
#define PATH1_R_TXRFC_GAIN_TX_FORCE_ON_C_M 0x20
#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C 0x764C
#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C_M 0xC0
#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C 0x764C
#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C_M 0x100
#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C 0x764C
#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C_M 0x600
#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C 0x764C
#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C_M 0x800
#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C 0x764C
#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C_M 0xE000
#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C 0x764C
#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C_M 0x10000
#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_VAL_C 0x764C
#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_VAL_C_M 0xE0000
#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_ON_C 0x764C
#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_ON_C_M 0x100000
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C 0x7650
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C_M 0x1F
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_C 0x7650
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_C_M 0x3E0
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C 0x7650
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C_M 0x7C00
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C 0x7650
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C_M 0xF8000
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C 0x7650
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C_M 0x1F00000
#define PATH1_R_TSSI_DCK_BY_CURVE_EN_C 0x7650
#define PATH1_R_TSSI_DCK_BY_CURVE_EN_C_M 0x80000000
#define PATH1_R_TSSI_DCK_BY_CURVE_0_C 0x7654
#define PATH1_R_TSSI_DCK_BY_CURVE_0_C_M 0xFFF
#define PATH1_R_TSSI_DCK_BY_CURVE_1_C 0x7654
#define PATH1_R_TSSI_DCK_BY_CURVE_1_C_M 0xFFF000
#define PATH1_R_TSSI_DCK_BY_CURVE_2_C 0x7658
#define PATH1_R_TSSI_DCK_BY_CURVE_2_C_M 0xFFF
#define PATH1_R_TSSI_DCK_BY_CURVE_3_C 0x7658
#define PATH1_R_TSSI_DCK_BY_CURVE_3_C_M 0xFFF000
#define PATH1_R_TSSI_DCK_BY_CURVE_4_C 0x765C
#define PATH1_R_TSSI_DCK_BY_CURVE_4_C_M 0xFFF
#define PATH1_R_TSSI_DCK_BY_CURVE_5_C 0x765C
#define PATH1_R_TSSI_DCK_BY_CURVE_5_C_M 0xFFF000
#define PATH1_R_TSSI_DCK_BY_CURVE_6_C 0x7660
#define PATH1_R_TSSI_DCK_BY_CURVE_6_C_M 0xFFF
#define PATH1_R_TSSI_DCK_BY_CURVE_7_C 0x7660
#define PATH1_R_TSSI_DCK_BY_CURVE_7_C_M 0xFFF000
#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C 0x7664
#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C_M 0x7
#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C 0x7664
#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C_M 0x38
#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C 0x7664
#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C_M 0x1C0
#define PATH1_R_TSSI_DCK_MOVING_AVG_LEN_C 0x7664
#define PATH1_R_TSSI_DCK_MOVING_AVG_LEN_C_M 0x7000
#define PATH1_R_TSSI_DCK_MOVING_AVG_CLR_C 0x7664
#define PATH1_R_TSSI_DCK_MOVING_AVG_CLR_C_M 0x8000
#define PATH1_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C 0x7664
#define PATH1_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C_M 0xF0000
#define PATH1_R_TSSI_DCK_MOVING_AVG_INI_DIS_C 0x7664
#define PATH1_R_TSSI_DCK_MOVING_AVG_INI_DIS_C_M 0x100000
#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C 0x7668
#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C_M 0x1
#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C 0x7668
#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C_M 0x2
#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C 0x7668
#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C_M 0x4
#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_ON_C 0x7668
#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_ON_C_M 0x8
#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C 0x7668
#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C_M 0x7F0
#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C 0x7668
#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C_M 0x800
#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C 0x7668
#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C_M 0x3F000
#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C 0x7668
#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C_M 0x40000
#define PATH1_R_TSSI_TIMEOUT_TIME_C 0x766C
#define PATH1_R_TSSI_TIMEOUT_TIME_C_M 0xFFF
#define PATH1_R_TSSI_TIMEOUT_UNIT_C 0x766C
#define PATH1_R_TSSI_TIMEOUT_UNIT_C_M 0x3000
#define PATH1_R_TXAGC_MAX_C 0x7800
#define PATH1_R_TXAGC_MAX_C_M 0xFF
#define PATH1_R_TXAGC_MIN_C 0x7800
#define PATH1_R_TXAGC_MIN_C_M 0xFF00
#define PATH1_R_TXAGC_RF_MAX_C 0x7800
#define PATH1_R_TXAGC_RF_MAX_C_M 0x3F0000
#define PATH1_R_TXAGC_RF_MIN_C 0x7800
#define PATH1_R_TXAGC_RF_MIN_C_M 0xFC00000
#define PATH1_R_DPD_OFST_EN_C 0x7800
#define PATH1_R_DPD_OFST_EN_C_M 0x10000000
#define PATH1_R_TXAGCSWING_EN_C 0x7800
#define PATH1_R_TXAGCSWING_EN_C_M 0x20000000
#define PATH1_R_DIS_CCK_SWING_TSSI_OFST_C 0x7800
#define PATH1_R_DIS_CCK_SWING_TSSI_OFST_C_M 0x40000000
#define PATH1_R_DIS_CCK_SWING_TXAGC_C 0x7800
#define PATH1_R_DIS_CCK_SWING_TXAGC_C_M 0x80000000
#define PATH1_R_TXAGC_OFDM_REF_DBM_C 0x7804
#define PATH1_R_TXAGC_OFDM_REF_DBM_C_M 0x1FF
#define PATH1_R_TXAGC_OFDM_REF_CW_C 0x7804
#define PATH1_R_TXAGC_OFDM_REF_CW_C_M 0x3FE00
#define PATH1_R_TSSI_MAP_OFST_OFDM_C 0x7804
#define PATH1_R_TSSI_MAP_OFST_OFDM_C_M 0x7FC0000
#define PATH1_R_DPD_OFST_C 0x7804
#define PATH1_R_DPD_OFST_C_M 0xF8000000
#define PATH1_R_TXAGC_CCK_REF_DBM_C 0x7808
#define PATH1_R_TXAGC_CCK_REF_DBM_C_M 0x1FF
#define PATH1_R_TXAGC_CCK_REF_CW_C 0x7808
#define PATH1_R_TXAGC_CCK_REF_CW_C_M 0x3FE00
#define PATH1_R_TSSI_MAP_OFST_CCK_C 0x7808
#define PATH1_R_TSSI_MAP_OFST_CCK_C_M 0x7FC0000
#define PATH1_R_TSSI_MAP_SLOPE_OFDM_C 0x780C
#define PATH1_R_TSSI_MAP_SLOPE_OFDM_C_M 0x7F
#define PATH1_R_TSSI_MAP_SLOPE_CCK_C 0x780C
#define PATH1_R_TSSI_MAP_SLOPE_CCK_C_M 0x7F00
#define PATH1_R_TXPW_FORCE_RDY_C 0x780C
#define PATH1_R_TXPW_FORCE_RDY_C_M 0x8000
#define PATH1_R_TSSI_ADC_DC_OFST_RE_C 0x780C
#define PATH1_R_TSSI_ADC_DC_OFST_RE_C_M 0xFFF0000
#define PATH1_R_TSSI_PARAM_OFDM_20M_ONLY_C 0x780C
#define PATH1_R_TSSI_PARAM_OFDM_20M_ONLY_C_M 0x10000000
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C 0x780C
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C_M 0x20000000
#define PATH1_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C 0x780C
#define PATH1_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x40000000
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C 0x780C
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x80000000
#define PATH1_R_TXAGC_PSEUDO_CW_C 0x7810
#define PATH1_R_TXAGC_PSEUDO_CW_C_M 0x1FF
#define PATH1_R_TXAGC_PSEUDO_CW_EN_C 0x7810
#define PATH1_R_TXAGC_PSEUDO_CW_EN_C_M 0x200
#define PATH1_R_TMETER_T0_C 0x7810
#define PATH1_R_TMETER_T0_C_M 0xFC00
#define PATH1_R_DIS_TSSI_F_C 0x7810
#define PATH1_R_DIS_TSSI_F_C_M 0x10000
#define PATH1_R_TMETER_TBL_RA_C 0x7810
#define PATH1_R_TMETER_TBL_RA_C_M 0x7E0000
#define PATH1_R_TMETER_TBL_RD_C 0x7810
#define PATH1_R_TMETER_TBL_RD_C_M 0x800000
#define PATH1_R_TSSI_THERMAL_PW_TRK_EN_C 0x7810
#define PATH1_R_TSSI_THERMAL_PW_TRK_EN_C_M 0x1000000
#define PATH1_R_TMETER_TBL_FORCE_WEN_C 0x7810
#define PATH1_R_TMETER_TBL_FORCE_WEN_C_M 0x2000000
#define PATH1_R_TMETER_TBL_FORCE_REN_C 0x7810
#define PATH1_R_TMETER_TBL_FORCE_REN_C_M 0x4000000
#define PATH1_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C 0x7810
#define PATH1_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C_M 0x8000000
#define PATH1_R_TSSI_DONT_USE_UPD_ADC_C 0x7810
#define PATH1_R_TSSI_DONT_USE_UPD_ADC_C_M 0x10000000
#define PATH1_R_TSSI_BYPASS_TSSI_FORCE_OFF_C 0x7810
#define PATH1_R_TSSI_BYPASS_TSSI_FORCE_OFF_C_M 0x20000000
#define PATH1_R_TSSI_DBG_PORT_EN_C 0x7810
#define PATH1_R_TSSI_DBG_PORT_EN_C_M 0x40000000
#define PATH1_R_TSSI_DONT_BND_ALOGK_TO_POS_C 0x7810
#define PATH1_R_TSSI_DONT_BND_ALOGK_TO_POS_C_M 0x80000000
#define PATH1_R_TSSI_RF_GAP_TBL_RA_C 0x7814
#define PATH1_R_TSSI_RF_GAP_TBL_RA_C_M 0x3F
#define PATH1_R_TSSI_RF_GAP_EN_C 0x7814
#define PATH1_R_TSSI_RF_GAP_EN_C_M 0x40
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_WEN_C 0x7814
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_WEN_C_M 0x80
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_REN_C 0x7814
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_REN_C_M 0x100
#define PATH1_R_TSSI_RF_GAP_TBL_RD_C 0x7814
#define PATH1_R_TSSI_RF_GAP_TBL_RD_C_M 0x200
#define PATH1_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C 0x7814
#define PATH1_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C_M 0x400
#define PATH1_R_TSSI_BYPASS_TSSI_C_C 0x7814
#define PATH1_R_TSSI_BYPASS_TSSI_C_C_M 0x800
#define PATH1_R_TSSI_DCK_AUTO_BYPASS_UPD_C 0x7814
#define PATH1_R_TSSI_DCK_AUTO_BYPASS_UPD_C_M 0x1000
#define PATH1_R_TSSI_DCK_AUTO_EN_C 0x7814
#define PATH1_R_TSSI_DCK_AUTO_EN_C_M 0x2000
#define PATH1_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C 0x7814
#define PATH1_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C_M 0x4000
#define PATH1_R_TSSI_DCK_AUTO_AVG_POINT_C 0x7814
#define PATH1_R_TSSI_DCK_AUTO_AVG_POINT_C_M 0x38000
#define PATH1_R_TSSI_DCK_AUTO_START_DLY_C 0x7814
#define PATH1_R_TSSI_DCK_AUTO_START_DLY_C_M 0x3C0000
#define PATH1_R_TSSI_ADC_AMPLIFY_C 0x7814
#define PATH1_R_TSSI_ADC_AMPLIFY_C_M 0xC00000
#define PATH1_R_TSSI_PW_TRK_USE_025DB_C 0x7814
#define PATH1_R_TSSI_PW_TRK_USE_025DB_C_M 0x1000000
#define PATH1_R_TSSI_DCK_SEL_C 0x7814
#define PATH1_R_TSSI_DCK_SEL_C_M 0x18000000
#define PATH1_R_TSSI_TXADC_PW_SV_EN_C 0x7814
#define PATH1_R_TSSI_TXADC_PW_SV_EN_C_M 0x20000000
#define PATH1_R_TSSI_RF_GAP_DE_CMB_OPT_C 0x7814
#define PATH1_R_TSSI_RF_GAP_DE_CMB_OPT_C_M 0x40000000
#define PATH1_R_TSSI_RF_GAP_DE_OFST_EN_C 0x7814
#define PATH1_R_TSSI_RF_GAP_DE_OFST_EN_C_M 0x80000000
#define PATH1_R_TXAGC_OFST_C 0x7818
#define PATH1_R_TXAGC_OFST_C_M 0xFF
#define PATH1_R_HE_ER_STF_PW_OFST_C 0x7818
#define PATH1_R_HE_ER_STF_PW_OFST_C_M 0x1FF00
#define PATH1_R_HE_STF_PW_OFST_C 0x7818
#define PATH1_R_HE_STF_PW_OFST_C_M 0x3FE0000
#define PATH1_R_TSSI_OSCILLATION_CNT_CLR_C 0x7818
#define PATH1_R_TSSI_OSCILLATION_CNT_CLR_C_M 0x4000000
#define PATH1_R_TSSI_OFST_BY_RFC_C 0x7818
#define PATH1_R_TSSI_OFST_BY_RFC_C_M 0x8000000
#define PATH1_R_TSSI_PW_TRK_AUTO_EN_C 0x7818
#define PATH1_R_TSSI_PW_TRK_AUTO_EN_C_M 0x10000000
#define PATH1_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C 0x7818
#define PATH1_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C_M 0x20000000
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_EN_C 0x7818
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_EN_C_M 0x40000000
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C 0x7818
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C_M 0x80000000
#define PATH1_R_TSSI_ADC_AVG_POINT_CCK_C 0x781C
#define PATH1_R_TSSI_ADC_AVG_POINT_CCK_C_M 0x3FF
#define PATH1_R_TSSI_ADC_AVG_POINT_OFDM_C 0x781C
#define PATH1_R_TSSI_ADC_AVG_POINT_OFDM_C_M 0xFFC00
#define PATH1_R_TSSI_SLOPE_CAL_EN_C 0x781C
#define PATH1_R_TSSI_SLOPE_CAL_EN_C_M 0x100000
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C 0x781C
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C_M 0x1E00000
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C 0x781C
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C_M 0x1E000000
#define PATH1_R_TSSI_ADC_NON_SQUARE_EN_C 0x781C
#define PATH1_R_TSSI_ADC_NON_SQUARE_EN_C_M 0x20000000
#define PATH1_R_TSSI_PSEUDO_TRK_MOD_EN_C 0x781C
#define PATH1_R_TSSI_PSEUDO_TRK_MOD_EN_C_M 0x80000000
#define PATH1_R_TSSI_SLOPE_A_C 0x7820
#define PATH1_R_TSSI_SLOPE_A_C_M 0xFFF
#define PATH1_R_TSSI_PKT_AVG_NUM_C 0x7820
#define PATH1_R_TSSI_PKT_AVG_NUM_C_M 0xF000
#define PATH1_R_TSSI_PW_TRK_SWING_LIM_C 0x7820
#define PATH1_R_TSSI_PW_TRK_SWING_LIM_C_M 0x1F0000
#define PATH1_R_TSSI_PW_TRK_SW_OFST_C 0x7820
#define PATH1_R_TSSI_PW_TRK_SW_OFST_C_M 0x1FE00000
#define PATH1_R_TSSI_ISEPA_C 0x7820
#define PATH1_R_TSSI_ISEPA_C_M 0x40000000
#define PATH1_R_TSSI_EN_C 0x7820
#define PATH1_R_TSSI_EN_C_M 0x80000000
#define PATH1_R_TSSI_A_OFDM_5M_C 0x7824
#define PATH1_R_TSSI_A_OFDM_5M_C_M 0x3FFFF
#define PATH1_R_TSSI_B_OFDM_5M_C 0x7824
#define PATH1_R_TSSI_B_OFDM_5M_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_OFDM_5M_C 0x7828
#define PATH1_R_TSSI_K_OFDM_5M_C_M 0xFFF
#define PATH1_R_TSSI_DE_OFDM_5M_C 0x7828
#define PATH1_R_TSSI_DE_OFDM_5M_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C 0x7828
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C_M 0x7FC00000
#define PATH1_R_TSSI_A_OFDM_10M_C 0x782C
#define PATH1_R_TSSI_A_OFDM_10M_C_M 0x3FFFF
#define PATH1_R_TSSI_B_OFDM_10M_C 0x782C
#define PATH1_R_TSSI_B_OFDM_10M_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_OFDM_10M_C 0x7830
#define PATH1_R_TSSI_K_OFDM_10M_C_M 0xFFF
#define PATH1_R_TSSI_DE_OFDM_10M_C 0x7830
#define PATH1_R_TSSI_DE_OFDM_10M_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C 0x7830
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C_M 0x7FC00000
#define PATH1_R_TSSI_A_OFDM_20M_C 0x7834
#define PATH1_R_TSSI_A_OFDM_20M_C_M 0x3FFFF
#define PATH1_R_TSSI_B_OFDM_20M_C 0x7834
#define PATH1_R_TSSI_B_OFDM_20M_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_OFDM_20M_C 0x7838
#define PATH1_R_TSSI_K_OFDM_20M_C_M 0xFFF
#define PATH1_R_TSSI_DE_OFDM_20M_C 0x7838
#define PATH1_R_TSSI_DE_OFDM_20M_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C 0x7838
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C_M 0x7FC00000
#define PATH1_R_TSSI_A_OFDM_40M_C 0x783C
#define PATH1_R_TSSI_A_OFDM_40M_C_M 0x3FFFF
#define PATH1_R_TSSI_B_OFDM_40M_C 0x783C
#define PATH1_R_TSSI_B_OFDM_40M_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_OFDM_40M_C 0x7840
#define PATH1_R_TSSI_K_OFDM_40M_C_M 0xFFF
#define PATH1_R_TSSI_DE_OFDM_40M_C 0x7840
#define PATH1_R_TSSI_DE_OFDM_40M_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C 0x7840
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C_M 0x7FC00000
#define PATH1_R_TSSI_A_OFDM_80M_C 0x7844
#define PATH1_R_TSSI_A_OFDM_80M_C_M 0x3FFFF
#define PATH1_R_TSSI_B_OFDM_80M_C 0x7844
#define PATH1_R_TSSI_B_OFDM_80M_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_OFDM_80M_C 0x7848
#define PATH1_R_TSSI_K_OFDM_80M_C_M 0xFFF
#define PATH1_R_TSSI_DE_OFDM_80M_C 0x7848
#define PATH1_R_TSSI_DE_OFDM_80M_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C 0x7848
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C_M 0x7FC00000
#define PATH1_R_TSSI_A_OFDM_80_80M_C 0x784C
#define PATH1_R_TSSI_A_OFDM_80_80M_C_M 0x3FFFF
#define PATH1_R_TSSI_B_OFDM_80_80M_C 0x784C
#define PATH1_R_TSSI_B_OFDM_80_80M_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_OFDM_80_80M_C 0x7850
#define PATH1_R_TSSI_K_OFDM_80_80M_C_M 0xFFF
#define PATH1_R_TSSI_DE_OFDM_80_80M_C 0x7850
#define PATH1_R_TSSI_DE_OFDM_80_80M_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C 0x7850
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C_M 0x7FC00000
#define PATH1_R_TSSI_A_CCK_LONG_C 0x7854
#define PATH1_R_TSSI_A_CCK_LONG_C_M 0x3FFFF
#define PATH1_R_TSSI_B_CCK_LONG_C 0x7854
#define PATH1_R_TSSI_B_CCK_LONG_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_CCK_LONG_C 0x7858
#define PATH1_R_TSSI_K_CCK_LONG_C_M 0xFFF
#define PATH1_R_TSSI_DE_CCK_LONG_C 0x7858
#define PATH1_R_TSSI_DE_CCK_LONG_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C 0x7858
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C_M 0x7FC00000
#define PATH1_R_TSSI_A_CCK_SHORT_C 0x785C
#define PATH1_R_TSSI_A_CCK_SHORT_C_M 0x3FFFF
#define PATH1_R_TSSI_B_CCK_SHORT_C 0x785C
#define PATH1_R_TSSI_B_CCK_SHORT_C_M 0x3FFC0000
#define PATH1_R_TSSI_K_CCK_SHORT_C 0x7860
#define PATH1_R_TSSI_K_CCK_SHORT_C_M 0xFFF
#define PATH1_R_TSSI_DE_CCK_SHORT_C 0x7860
#define PATH1_R_TSSI_DE_CCK_SHORT_C_M 0x3FF000
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C 0x7860
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C_M 0x7FC00000
#define PATH1_RSWING_NO_LIM_C 0x7860
#define PATH1_RSWING_NO_LIM_C_M 0x80000000
#define PATH1_R_TSSI_DELTA_CODE_MAX_C 0x7864
#define PATH1_R_TSSI_DELTA_CODE_MAX_C_M 0x3FF
#define PATH1_R_TSSI_DELTA_CODE_MIN_C 0x7864
#define PATH1_R_TSSI_DELTA_CODE_MIN_C_M 0xFFC00
#define PATH1_R_RFC_TMETER_T1_FORCE_VAL_C 0x7864
#define PATH1_R_RFC_TMETER_T1_FORCE_VAL_C_M 0x3F00000
#define PATH1_R_RFC_TMETER_T1_FORCE_ON_C 0x7864
#define PATH1_R_RFC_TMETER_T1_FORCE_ON_C_M 0x4000000
#define PATH1_R_GOTHROUGH_TX_IQKDPK_C 0x7864
#define PATH1_R_GOTHROUGH_TX_IQKDPK_C_M 0x8000000
#define PATH1_R_GOTHROUGH_RX_IQKDPK_C 0x7864
#define PATH1_R_GOTHROUGH_RX_IQKDPK_C_M 0x10000000
#define PATH1_R_IQK_IO_RFC_EN_C 0x7864
#define PATH1_R_IQK_IO_RFC_EN_C_M 0x20000000
#define PATH1_R_TX_IMFIR2_FORCE_RDY_C 0x7864
#define PATH1_R_TX_IMFIR2_FORCE_RDY_C_M 0x40000000
#define PATH1_R_CLK_GATING_TD_PATH_FORCE_ON_C 0x7864
#define PATH1_R_CLK_GATING_TD_PATH_FORCE_ON_C_M 0x80000000
#define PATH1_R_ANT_TRAIN_EN_C 0x7868
#define PATH1_R_ANT_TRAIN_EN_C_M 0x1
#define PATH1_R_TX_ANT_SEL_C 0x7868
#define PATH1_R_TX_ANT_SEL_C_M 0x2
#define PATH1_R_RFE_BUF_EN_C 0x7868
#define PATH1_R_RFE_BUF_EN_C_M 0x4
#define PATH1_R_LNAON_AGC_C 0x7868
#define PATH1_R_LNAON_AGC_C_M 0x8
#define PATH1_R_TRSW_BIT_BT_C 0x7868
#define PATH1_R_TRSW_BIT_BT_C_M 0x10
#define PATH1_R_TRSW_S_C 0x7868
#define PATH1_R_TRSW_S_C_M 0x20
#define PATH1_R_TRSW_O_C 0x7868
#define PATH1_R_TRSW_O_C_M 0x40
#define PATH1_R_TRSWB_O_C 0x7868
#define PATH1_R_TRSWB_O_C_M 0x80
#define PATH1_R_BT_FORCE_ANTIDX_C 0x7868
#define PATH1_R_BT_FORCE_ANTIDX_C_M 0xF00
#define PATH1_R_BT_FORCE_ANTIDX_EN_C 0x7868
#define PATH1_R_BT_FORCE_ANTIDX_EN_C_M 0x1000
#define PATH1_R_ANT_MODULE_RFE_OPT_C 0x7868
#define PATH1_R_ANT_MODULE_RFE_OPT_C_M 0xC000
#define PATH1_R_RFSW_TR_C 0x7868
#define PATH1_R_RFSW_TR_C_M 0xFFFF0000
#define PATH1_R_ANTSEL_C 0x786C
#define PATH1_R_ANTSEL_C_M 0xFFFFFFFF
#define PATH1_R_RFSW_ANT_31_0__C 0x7870
#define PATH1_R_RFSW_ANT_31_0__C_M 0xFFFFFFFF
#define PATH1_R_RFSW_ANT_63_32__C 0x7874
#define PATH1_R_RFSW_ANT_63_32__C_M 0xFFFFFFFF
#define PATH1_R_RFSW_ANT_95_64__C 0x7878
#define PATH1_R_RFSW_ANT_95_64__C_M 0xFFFFFFFF
#define PATH1_R_RFSW_ANT_127_96__C 0x787C
#define PATH1_R_RFSW_ANT_127_96__C_M 0xFFFFFFFF
#define PATH1_R_RFE_SEL_31_0__C 0x7880
#define PATH1_R_RFE_SEL_31_0__C_M 0xFFFFFFFF
#define PATH1_R_RFE_SEL_63_32__C 0x7884
#define PATH1_R_RFE_SEL_63_32__C_M 0xFFFFFFFF
#define PATH1_R_RFE_SEL_95_64__C 0x7888
#define PATH1_R_RFE_SEL_95_64__C_M 0xFFFFFFFF
#define PATH1_R_RFE_SEL_127_96__C 0x788C
#define PATH1_R_RFE_SEL_127_96__C_M 0xFFFFFFFF
#define PATH1_R_RFE_INV_C 0x7890
#define PATH1_R_RFE_INV_C_M 0xFFFFFFFF
#define PATH1_R_RFE_OPT_C 0x7894
#define PATH1_R_RFE_OPT_C_M 0xFFFFFFF
#define PATH1_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C 0x7894
#define PATH1_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C_M 0x10000000
#define PATH1_R_PATH_NOTRSW_BT_C 0x7894
#define PATH1_R_PATH_NOTRSW_BT_C_M 0x20000000
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C 0x7898
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C_M 0xFF
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C 0x7898
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C_M 0xFF00
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C 0x7898
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C_M 0xFF0000
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C 0x7898
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C_M 0xFF000000
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C 0x789C
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C_M 0xFF
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C 0x789C
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C_M 0xFF00
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C 0x789C
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C_M 0xFF0000
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C 0x789C
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C_M 0xFF000000
#define PATH1_R_HE_LSTF_PW_OFST_52_56_C 0x78A0
#define PATH1_R_HE_LSTF_PW_OFST_52_56_C_M 0xFF
#define PATH1_R_HE_LSTF_PW_OFST_52_56_2_C 0x78A0
#define PATH1_R_HE_LSTF_PW_OFST_52_56_2_C_M 0xFF00
#define PATH1_R_HE_LSTF_PW_OFST_52_56_4_C 0x78A0
#define PATH1_R_HE_LSTF_PW_OFST_52_56_4_C_M 0xFF0000
#define PATH1_R_HE_LSTF_PW_OFST_52_56_8_C 0x78A0
#define PATH1_R_HE_LSTF_PW_OFST_52_56_8_C_M 0xFF000000
#define PATH1_R_HE_LSTF_PW_OFST_52_56X2_C 0x78A4
#define PATH1_R_HE_LSTF_PW_OFST_52_56X2_C_M 0xFF
#define PATH1_R_TSSI_GAP_S0_C 0x78A4
#define PATH1_R_TSSI_GAP_S0_C_M 0x1FF00
#define PATH1_R_TSSI_GAP_S1_C 0x78A4
#define PATH1_R_TSSI_GAP_S1_C_M 0x3FE0000
#define PATH1_R_TSSI_GAP_S2_C 0x78A8
#define PATH1_R_TSSI_GAP_S2_C_M 0x1FF
#define PATH1_R_TSSI_GAP_S3_C 0x78A8
#define PATH1_R_TSSI_GAP_S3_C_M 0x3FE00
#define PATH1_R_TSSI_GAP_S4_C 0x78A8
#define PATH1_R_TSSI_GAP_S4_C_M 0x7FC0000
#define PATH1_R_TSSI_GAP_S5_C 0x78AC
#define PATH1_R_TSSI_GAP_S5_C_M 0x1FF
#define PATH1_R_TSSI_GAP_S6_C 0x78AC
#define PATH1_R_TSSI_GAP_S6_C_M 0x3FE00
#define PATH1_R_TSSI_GAP_S7_C 0x78AC
#define PATH1_R_TSSI_GAP_S7_C_M 0x7FC0000
#define PATH1_R_IQK_DPK_PATH_RST_C 0x78AC
#define PATH1_R_IQK_DPK_PATH_RST_C_M 0x8000000
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HT_C 0x78AC
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x10000000
#define PATH1_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x78AC
#define PATH1_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x20000000
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HE_C 0x78AC
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x40000000
#define PATH1_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x78AC
#define PATH1_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x80000000
#define PATH1_R_DAC_GAIN_COMP_TBL_RA_C 0x78B0
#define PATH1_R_DAC_GAIN_COMP_TBL_RA_C_M 0x7F
#define PATH1_R_DAC_GAIN_COMP_TBL_RD_C 0x78B0
#define PATH1_R_DAC_GAIN_COMP_TBL_RD_C_M 0x80
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C 0x78B0
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C_M 0x100
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_REN_C 0x78B0
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_REN_C_M 0x200
#define PATH1_R_DAC_GAIN_COMP_EN_C 0x78B0
#define PATH1_R_DAC_GAIN_COMP_EN_C_M 0x400
#define PATH1_R_TSSI_CW_COMP_EN_C 0x78B0
#define PATH1_R_TSSI_CW_COMP_EN_C_M 0x800
#define PATH1_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C 0x78B0
#define PATH1_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C_M 0x8000
#define PATH1_R_TSSI_OSCILLATION_HALT_TRK_TH_C 0x78B0
#define PATH1_R_TSSI_OSCILLATION_HALT_TRK_TH_C_M 0xFFFF0000
#define PATH1_R_TSSI_DBG_SEL_C 0x78B4
#define PATH1_R_TSSI_DBG_SEL_C_M 0x1F
#define PATH1_R_GAIN_TX_IPA_FORCE_ON_C 0x78B4
#define PATH1_R_GAIN_TX_IPA_FORCE_ON_C_M 0x20
#define PATH1_R_GAIN_TX_IPA_FORCE_VAL_C 0x78B4
#define PATH1_R_GAIN_TX_IPA_FORCE_VAL_C_M 0x1C0
#define PATH1_R_TXPW_TBL_IOQ_DIS_C 0x78B4
#define PATH1_R_TXPW_TBL_IOQ_DIS_C_M 0x200
#define PATH1_R_RFTXEN_SAMPLING_SHIFT_C 0x78B4
#define PATH1_R_RFTXEN_SAMPLING_SHIFT_C_M 0xF000
#define PATH1_R_TMETER_T0_CW_C 0x78B4
#define PATH1_R_TMETER_T0_CW_C_M 0xFF0000
#define PATH1_R_TSSI_F_WAIT_UPD_OFDM_C 0x78B4
#define PATH1_R_TSSI_F_WAIT_UPD_OFDM_C_M 0x7F000000
#define PATH1_R_TSSI_F_WAIT_UPD_CCK_SHORT_C 0x78B8
#define PATH1_R_TSSI_F_WAIT_UPD_CCK_SHORT_C_M 0x7F
#define PATH1_R_TSSI_F_WAIT_UPD_CCK_LONG_C 0x78B8
#define PATH1_R_TSSI_F_WAIT_UPD_CCK_LONG_C_M 0x7F00
#define PATH1_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C 0x78B8
#define PATH1_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C_M 0x7F0000
#define PATH1_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C 0x78B8
#define PATH1_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C_M 0x7F000000
#define PATH1_R_TXAGC_OFST_MAX_C 0x78BC
#define PATH1_R_TXAGC_OFST_MAX_C_M 0xFF
#define PATH1_R_TXAGC_OFST_MIN_C 0x78BC
#define PATH1_R_TXAGC_OFST_MIN_C_M 0xFF00
#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_C_M 0x10000
#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C_M 0x20000
#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_C_M 0x40000
#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C_M 0x80000
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_C_M 0x100000
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C_M 0x200000
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C_M 0x400000
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C_M 0x800000
#define PATH1_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C_M 0x1000000
#define PATH1_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C_M 0x2000000
#define PATH1_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C 0x78BC
#define PATH1_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C_M 0x4000000
#define PATH1_R_GAIN_TX_GAPK_FORCE_VAL_C 0x78C0
#define PATH1_R_GAIN_TX_GAPK_FORCE_VAL_C_M 0xF
#define PATH1_R_GAIN_TX_GAPK_FORCE_ON_C 0x78C0
#define PATH1_R_GAIN_TX_GAPK_FORCE_ON_C_M 0x10
#define PATH1_R_GAIN_TX_PAD_FORCE_VAL_C 0x78C0
#define PATH1_R_GAIN_TX_PAD_FORCE_VAL_C_M 0x3E0
#define PATH1_R_GAIN_TX_PAD_FORCE_ON_C 0x78C0
#define PATH1_R_GAIN_TX_PAD_FORCE_ON_C_M 0x400
#define PATH1_R_GAIN_TX_FORCE_VAL_C 0x78C0
#define PATH1_R_GAIN_TX_FORCE_VAL_C_M 0xF800
#define PATH1_R_GAIN_TX_FORCE_ON_C 0x78C0
#define PATH1_R_GAIN_TX_FORCE_ON_C_M 0x10000
#define PATH1_R_TSSISWING_LIM_PEAK_OFDM_C 0x78C0
#define PATH1_R_TSSISWING_LIM_PEAK_OFDM_C_M 0xE0000
#define PATH1_R_TSSISWING_LIM_PEAK_CCK_C 0x78C0
#define PATH1_R_TSSISWING_LIM_PEAK_CCK_C_M 0x700000
#define PATH1_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C 0x78C0
#define PATH1_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C_M 0x800000
#define PATH1_R_TSSI_TRACK_AT_SMALL_SWING_C 0x78C0
#define PATH1_R_TSSI_TRACK_AT_SMALL_SWING_C_M 0x1000000
#define PATH1_R_BYPASS_TSSI_CCK_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_CCK_EN_C_M 0x2000000
#define PATH1_R_BYPASS_TSSI_LEGACY_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_LEGACY_EN_C_M 0x4000000
#define PATH1_R_BYPASS_TSSI_HT_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_HT_EN_C_M 0x8000000
#define PATH1_R_BYPASS_TSSI_VHT_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_VHT_EN_C_M 0x10000000
#define PATH1_R_BYPASS_TSSI_HE_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_HE_EN_C_M 0x20000000
#define PATH1_R_BYPASS_TSSI_HE_ER_SU_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_HE_ER_SU_EN_C_M 0x40000000
#define PATH1_R_BYPASS_TSSI_HE_TB_EN_C 0x78C0
#define PATH1_R_BYPASS_TSSI_HE_TB_EN_C_M 0x80000000
#define PATH1_R_RF_GAP_CAL_BND0_C 0x78C4
#define PATH1_R_RF_GAP_CAL_BND0_C_M 0x3F
#define PATH1_R_RF_GAP_CAL_BND1_C 0x78C4
#define PATH1_R_RF_GAP_CAL_BND1_C_M 0xFC0
#define PATH1_R_RF_GAP_CAL_BND2_C 0x78C4
#define PATH1_R_RF_GAP_CAL_BND2_C_M 0x3F000
#define PATH1_R_TSSI_ADC_OFST_BND01_C 0x78C4
#define PATH1_R_TSSI_ADC_OFST_BND01_C_M 0x3FFC0000
#define PATH1_R_TSSI_RF_GAP_BY_RANGE_EN_C 0x78C4
#define PATH1_R_TSSI_RF_GAP_BY_RANGE_EN_C_M 0x40000000
#define PATH1_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C 0x78C4
#define PATH1_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C_M 0x80000000
#define PATH1_R_TSSI_ADC_OFST_BND12_C 0x78C8
#define PATH1_R_TSSI_ADC_OFST_BND12_C_M 0xFFF
#define PATH1_R_TSSI_ADC_OFST_BND22_C 0x78C8
#define PATH1_R_TSSI_ADC_OFST_BND22_C_M 0xFFF000
#define PATH1_R_ADC_FIFO_PATH_EN_FORCE_ON_C 0x78C8
#define PATH1_R_ADC_FIFO_PATH_EN_FORCE_ON_C_M 0x1000000
#define PATH1_R_TXINFO_CH_WITH_DATA_DECODE_C 0x78C8
#define PATH1_R_TXINFO_CH_WITH_DATA_DECODE_C_M 0x6000000
#define PATH1_R_BYPASS_TSSI_VHT_MU_EN_C 0x78C8
#define PATH1_R_BYPASS_TSSI_VHT_MU_EN_C_M 0x10000000
#define PATH1_R_BYPASS_TSSI_HE_MU_EN_C 0x78C8
#define PATH1_R_BYPASS_TSSI_HE_MU_EN_C_M 0x20000000
#define PATH1_R_BYPASS_TSSI_HE_RU_EN_C 0x78C8
#define PATH1_R_BYPASS_TSSI_HE_RU_EN_C_M 0x40000000
#define PATH1_R_BYPASS_TSSI_TXBF_EN_C 0x78C8
#define PATH1_R_BYPASS_TSSI_TXBF_EN_C_M 0x80000000
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL0_C 0x78CC
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL0_C_M 0x7
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL1_C 0x78CC
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL1_C_M 0x38
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL2_C 0x78CC
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL2_C_M 0x1C0
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL3_C 0x78CC
#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL3_C_M 0xE00
#define PATH1_R_TSSI_SLOPE_CAL_SEL_IPA_C 0x78CC
#define PATH1_R_TSSI_SLOPE_CAL_SEL_IPA_C_M 0x1000
#define PATH1_R_TX_GAIN_CCK_MORE_ADJ_C 0x78CC
#define PATH1_R_TX_GAIN_CCK_MORE_ADJ_C_M 0xFF000000
#define PATH1_R_TX_GAIN_SCALE_FORCE_VAL_C 0x78D0
#define PATH1_R_TX_GAIN_SCALE_FORCE_VAL_C_M 0xFFF
#define PATH1_R_TX_GAIN_SCALE_FORCE_ON_C 0x78D0
#define PATH1_R_TX_GAIN_SCALE_FORCE_ON_C_M 0x1000
#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_C 0x78D0
#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_C_M 0x1E000
#define PATH1_R_TX_LSTF_PW_EST_LEN_C 0x78D0
#define PATH1_R_TX_LSTF_PW_EST_LEN_C_M 0x3FE0000
#define PATH1_R_TX_LSTF_PW_EST_SEL_EVEN_C 0x78D0
#define PATH1_R_TX_LSTF_PW_EST_SEL_EVEN_C_M 0x4000000
#define PATH1_R_TSSI_C_MAP_UNFIX_C 0x78D0
#define PATH1_R_TSSI_C_MAP_UNFIX_C_M 0x80000000
#define PATH1_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C 0x78D4
#define PATH1_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C_M 0xFF
#define PATH1_R_TSSI_BYPASS_TXPW_MAX_C 0x78D4
#define PATH1_R_TSSI_BYPASS_TXPW_MAX_C_M 0x3FE00
#define PATH1_R_TSSI_BYPASS_TXPW_MIN_C 0x78D4
#define PATH1_R_TSSI_BYPASS_TXPW_MIN_C_M 0x7FC0000
#define PATH1_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C 0x78D4
#define PATH1_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C_M 0x8000000
#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C 0x78D4
#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C_M 0x10000000
#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_POST_C 0x78D4
#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_POST_C_M 0x20000000
#define PATH1_R_TXPW_SPLIT_FOR_DPD_C 0x78D4
#define PATH1_R_TXPW_SPLIT_FOR_DPD_C_M 0x40000000
#define PATH1_R_TXAGC_TP_MASK_EN_C 0x78D4
#define PATH1_R_TXAGC_TP_MASK_EN_C_M 0x80000000
#define PATH1_R_TSSI_BYPASS_BY_C_MAX_C 0x78D8
#define PATH1_R_TSSI_BYPASS_BY_C_MAX_C_M 0x1FF
#define PATH1_R_TSSI_BYPASS_BY_C_MIN_C 0x78D8
#define PATH1_R_TSSI_BYPASS_BY_C_MIN_C_M 0x3FE00
#define PATH1_R_TSSI_BYPASS_BY_C_SEL_C 0x78D8
#define PATH1_R_TSSI_BYPASS_BY_C_SEL_C_M 0xC0000
#define PATH1_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C 0x78D8
#define PATH1_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C_M 0xFFF00000
#define PATH1_R_TXAGC_OFST_FIX_ERR_MAX_C 0x78DC
#define PATH1_R_TXAGC_OFST_FIX_ERR_MAX_C_M 0xFF
#define PATH1_R_TXAGC_OFST_FIX_ERR_MIN_C 0x78DC
#define PATH1_R_TXAGC_OFST_FIX_ERR_MIN_C_M 0xFF00
#define PATH1_R_TXAGC_OFST_FIX_C 0x78DC
#define PATH1_R_TXAGC_OFST_FIX_C_M 0x10000
#define PATH1_R_TSSI_C_FORCE_VAL_C 0x78DC
#define PATH1_R_TSSI_C_FORCE_VAL_C_M 0x1FF00000
#define PATH1_R_TSSI_C_FORCE_ON_C 0x78DC
#define PATH1_R_TSSI_C_FORCE_ON_C_M 0x20000000
#define PATH1_R_TXPW_RSTB_MAN_ON_C 0x78DC
#define PATH1_R_TXPW_RSTB_MAN_ON_C_M 0x40000000
#define PATH1_R_TXPW_RSTB_MAN_C 0x78DC
#define PATH1_R_TXPW_RSTB_MAN_C_M 0x80000000
#define PATH1_R_TXAGC_OFDM_REF_CW_OFST_C 0x78E0
#define PATH1_R_TXAGC_OFDM_REF_CW_OFST_C_M 0x3FF
#define PATH1_R_TXAGC_CCK_REF_CW_OFST_C 0x78E0
#define PATH1_R_TXAGC_CCK_REF_CW_OFST_C_M 0x3FF000
#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C 0x78E0
#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C_M 0x7F000000
#define PATH1_R_TXPW_RDY_NO_DLY_C 0x78E0
#define PATH1_R_TXPW_RDY_NO_DLY_C_M 0x80000000
#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C 0x78E4
#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C_M 0x7F
#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C 0x78E4
#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C_M 0x80
#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C 0x78E4
#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C_M 0x700
#define PATH1_R_TXAGC_OFST_MOVING_AVG_LEN_C 0x78E4
#define PATH1_R_TXAGC_OFST_MOVING_AVG_LEN_C_M 0x3800
#define PATH1_R_TXAGC_OFST_MOVING_AVG_CLR_C 0x78E4
#define PATH1_R_TXAGC_OFST_MOVING_AVG_CLR_C_M 0x4000
#define PATH1_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C 0x78E4
#define PATH1_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C_M 0x8000
#define PATH1_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C 0x78E4
#define PATH1_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C_M 0xF0000
#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C 0x78E4
#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C_M 0x7F00000
#define PATH1_R_TXPW_RSTB_SUB_SEL_C 0x78E4
#define PATH1_R_TXPW_RSTB_SUB_SEL_C_M 0x8000000
#define PATH1_R_TXPW_RSTB_SUB_C 0x78E4
#define PATH1_R_TXPW_RSTB_SUB_C_M 0x10000000
#define PATH1_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C 0x78E4
#define PATH1_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C_M 0x20000000
#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MAX_C 0x78F0
#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MAX_C_M 0x1FF
#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MIN_C 0x78F0
#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MIN_C_M 0x3FE00
#define PATH1_R_GOTHROUGH_TX_GAIN_POST_DPD_C 0x78F0
#define PATH1_R_GOTHROUGH_TX_GAIN_POST_DPD_C_M 0x40000
#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C 0x78F0
#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C_M 0x80000
#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C 0x78F0
#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C_M 0xFFF00000
#define PATH1_R_RF_GAP_CAL_OFST_BND00_10BITS_C 0x78F4
#define PATH1_R_RF_GAP_CAL_OFST_BND00_10BITS_C_M 0x3FF
#define PATH1_R_RF_GAP_CAL_OFST_BND01_10BITS_C 0x78F4
#define PATH1_R_RF_GAP_CAL_OFST_BND01_10BITS_C_M 0xFFC00
#define PATH1_R_RF_GAP_CAL_OFST_BND12_10BITS_C 0x78F4
#define PATH1_R_RF_GAP_CAL_OFST_BND12_10BITS_C_M 0x3FF00000
#define PATH1_R_RF_GAP_CAL_OFST_BND22_10BITS_C 0x78F8
#define PATH1_R_RF_GAP_CAL_OFST_BND22_10BITS_C_M 0x3FF
#define PATH1_R_LOG_VAL_OFST_CCK_C 0x78F8
#define PATH1_R_LOG_VAL_OFST_CCK_C_M 0x3FFFFC00
#define PATH1_R_TSSI_ADC_PATH_Q_C 0x78F8
#define PATH1_R_TSSI_ADC_PATH_Q_C_M 0x40000000
#define PATH1_R_DAC_COMP_POST_DPD_EN_C 0x78F8
#define PATH1_R_DAC_COMP_POST_DPD_EN_C_M 0x80000000
#define PATH1_R_LOG_VAL_OFST_OFDM_C 0x78FC
#define PATH1_R_LOG_VAL_OFST_OFDM_C_M 0xFFFFF
#define PATH1_R_UPD_TXAGC_OFST_LATENCY_C 0x78FC
#define PATH1_R_UPD_TXAGC_OFST_LATENCY_C_M 0x700000
#define PATH1_R_TSSI_UPD_TMETER_EN_C 0x78FC
#define PATH1_R_TSSI_UPD_TMETER_EN_C_M 0x800000
#define PATH1_R_TXRFC_BW_TXFORCE_VAL_C 0x78FC
#define PATH1_R_TXRFC_BW_TXFORCE_VAL_C_M 0x3000000
#define PATH1_R_TXRFC_BW_TXFORCE_ON_C 0x78FC
#define PATH1_R_TXRFC_BW_TXFORCE_ON_C_M 0x4000000
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_ON_C 0x78FC
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_ON_C_M 0x8000000
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_VAL_C 0x78FC
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_VAL_C_M 0x10000000
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C 0x7A00
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C 0x7A00
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C 0x7A04
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C 0x7A04
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C 0x7A08
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C 0x7A08
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C 0x7A0C
#define PATH1_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C 0x7A0C
#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C 0x7A10
#define PATH1_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C 0x7A10
#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C 0x7A14
#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C 0x7A14
#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C 0x7A18
#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C 0x7A18
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C 0x7A1C
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C 0x7A1C
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C 0x7A20
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C 0x7A20
#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_VHT_80_TXSC0_C 0x7A24
#define PATH1_R_DAC_GAIN_COMP_VHT_80_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C 0x7A24
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C 0x7A28
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C 0x7A28
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C 0x7A2C
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C 0x7A2C
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C 0x7A30
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C 0x7A30
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C 0x7A34
#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C 0x7A34
#define PATH1_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C 0x7A38
#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C 0x7A38
#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C 0x7A3C
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C 0x7A3C
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C 0x7A40
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C 0x7A40
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C 0x7A44
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C 0x7A44
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C 0x7A48
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C 0x7A48
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C 0x7A4C
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C 0x7A4C
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C 0x7A50
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C 0x7A50
#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C 0x7A54
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C 0x7A54
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C 0x7A58
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C 0x7A58
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C 0x7A5C
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C 0x7A5C
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C 0x7A60
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C 0x7A60
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C 0x7A64
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C 0x7A64
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C 0x7A68
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C 0x7A68
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C 0x7A6C
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C 0x7A6C
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C 0x7A70
#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C 0x7A70
#define PATH1_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C 0x7A74
#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C 0x7A74
#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C 0x7A78
#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C 0x7A78
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C 0x7A7C
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C 0x7A7C
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C 0x7A80
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C 0x7A80
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C 0x7A84
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C 0x7A84
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C 0x7A88
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C 0x7A88
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C 0x7A8C
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C 0x7A8C
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C 0x7A90
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C 0x7A90
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C 0x7A94
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C 0x7A94
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C 0x7A98
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C 0x7A98
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C 0x7A9C
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C 0x7A9C
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C 0x7AA0
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C 0x7AA0
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C 0x7AA4
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C 0x7AA4
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C 0x7AA8
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C 0x7AA8
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C 0x7AAC
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C 0x7AAC
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C 0x7AB0
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C 0x7AB0
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C 0x7AB4
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C 0x7AB4
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C 0x7AB8
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C 0x7AB8
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C 0x7ABC
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C 0x7ABC
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C_M 0xFFFF0000
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C 0x7AC0
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C_M 0xFFFF
#define PATH1_R_DAC_GAIN_COMP_UNEXPECTED_C 0x7AC0
#define PATH1_R_DAC_GAIN_COMP_UNEXPECTED_C_M 0xFFFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS0_C 0x7C00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS0_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS1_C 0x7C00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS1_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS2_C 0x7C00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS2_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS3_C 0x7C00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS3_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS4_C 0x7C04
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS4_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS5_C 0x7C04
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS5_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS6_C 0x7C04
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS6_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS7_C 0x7C04
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS7_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS8_C 0x7C08
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS8_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS9_C 0x7C08
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS9_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS10_C 0x7C08
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS10_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS11_C 0x7C08
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS11_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS12_C 0x7C0C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS12_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS13_C 0x7C0C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS13_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS14_C 0x7C0C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS14_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS15_C 0x7C0C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS15_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS16_C 0x7C10
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS16_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS17_C 0x7C10
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS17_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS18_C 0x7C10
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS18_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS19_C 0x7C10
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS19_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS20_C 0x7C14
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS20_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS21_C 0x7C14
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS21_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS22_C 0x7C14
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS22_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS23_C 0x7C14
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS23_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS24_C 0x7C18
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS24_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS25_C 0x7C18
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS25_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS26_C 0x7C18
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS26_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS27_C 0x7C18
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS27_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS28_C 0x7C1C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS28_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS29_C 0x7C1C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS29_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS30_C 0x7C1C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS30_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS31_C 0x7C1C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS31_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG32_C 0x7C20
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG32_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG31_C 0x7C20
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG31_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG30_C 0x7C20
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG30_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG29_C 0x7C20
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG29_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG28_C 0x7C24
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG28_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG27_C 0x7C24
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG27_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG26_C 0x7C24
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG26_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG25_C 0x7C24
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG25_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG24_C 0x7C28
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG24_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG23_C 0x7C28
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG23_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG22_C 0x7C28
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG22_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG21_C 0x7C28
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG21_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG20_C 0x7C2C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG20_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG19_C 0x7C2C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG19_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG18_C 0x7C2C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG18_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG17_C 0x7C2C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG17_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG16_C 0x7C30
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG16_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG15_C 0x7C30
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG15_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG14_C 0x7C30
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG14_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG13_C 0x7C30
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG13_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG12_C 0x7C34
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG12_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG11_C 0x7C34
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG11_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG10_C 0x7C34
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG10_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG9_C 0x7C34
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG9_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG8_C 0x7C38
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG8_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG7_C 0x7C38
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG7_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG6_C 0x7C38
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG6_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG5_C 0x7C38
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG5_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG4_C 0x7C3C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG4_C_M 0xFF
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG3_C 0x7C3C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG3_C_M 0xFF00
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG2_C 0x7C3C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG2_C_M 0xFF0000
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG1_C 0x7C3C
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG1_C_M 0xFF000000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_0_C 0x7C40
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_0_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_1_C 0x7C40
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_1_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_2_C 0x7C44
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_2_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_3_C 0x7C44
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_3_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_4_C 0x7C48
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_4_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_5_C 0x7C48
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_5_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_6_C 0x7C4C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_6_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_7_C 0x7C4C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_7_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_8_C 0x7C50
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_8_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_9_C 0x7C50
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_9_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_10_C 0x7C54
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_10_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_11_C 0x7C54
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_11_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_12_C 0x7C58
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_12_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_13_C 0x7C58
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_13_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_14_C 0x7C5C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_14_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_15_C 0x7C5C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_15_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_16_C 0x7C60
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_16_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_17_C 0x7C60
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_17_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_18_C 0x7C64
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_18_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_19_C 0x7C64
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_19_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_20_C 0x7C68
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_20_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_21_C 0x7C68
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_21_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_22_C 0x7C6C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_22_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_23_C 0x7C6C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_23_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_24_C 0x7C70
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_24_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_25_C 0x7C70
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_25_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_26_C 0x7C74
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_26_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_27_C 0x7C74
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_27_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_28_C 0x7C78
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_28_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_29_C 0x7C78
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_29_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_30_C 0x7C7C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_30_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_31_C 0x7C7C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_31_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_32_C 0x7C80
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_32_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_33_C 0x7C80
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_33_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_34_C 0x7C84
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_34_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_35_C 0x7C84
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_35_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_36_C 0x7C88
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_36_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_37_C 0x7C88
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_37_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_38_C 0x7C8C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_38_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_39_C 0x7C8C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_39_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_40_C 0x7C90
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_40_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_41_C 0x7C90
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_41_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_42_C 0x7C94
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_42_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_43_C 0x7C94
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_43_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_44_C 0x7C98
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_44_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_45_C 0x7C98
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_45_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_46_C 0x7C9C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_46_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_47_C 0x7C9C
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_47_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_48_C 0x7CA0
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_48_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_49_C 0x7CA0
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_49_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_50_C 0x7CA4
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_50_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_51_C 0x7CA4
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_51_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_52_C 0x7CA8
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_52_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_53_C 0x7CA8
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_53_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_54_C 0x7CAC
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_54_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_55_C 0x7CAC
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_55_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_56_C 0x7CB0
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_56_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_57_C 0x7CB0
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_57_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_58_C 0x7CB4
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_58_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_59_C 0x7CB4
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_59_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_60_C 0x7CB8
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_60_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_61_C 0x7CB8
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_61_C_M 0x3FF0000
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_62_C 0x7CBC
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_62_C_M 0x3FF
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_63_C 0x7CBC
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_63_C_M 0x3FF0000
#define FPGA_DC_OFST_0_C 0xC000
#define FPGA_DC_OFST_0_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_1_C 0xC004
#define FPGA_DC_OFST_1_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_2_C 0xC008
#define FPGA_DC_OFST_2_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_3_C 0xC00C
#define FPGA_DC_OFST_3_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_4_C 0xC010
#define FPGA_DC_OFST_4_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_5_C 0xC014
#define FPGA_DC_OFST_5_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_6_C 0xC018
#define FPGA_DC_OFST_6_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_7_C 0xC01C
#define FPGA_DC_OFST_7_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_8_C 0xC020
#define FPGA_DC_OFST_8_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_9_C 0xC024
#define FPGA_DC_OFST_9_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_10_C 0xC028
#define FPGA_DC_OFST_10_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_11_C 0xC02C
#define FPGA_DC_OFST_11_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_12_C 0xC030
#define FPGA_DC_OFST_12_C_M 0xFFFFFFFF
#define FPGA_DC_OFST_13_C 0xC034
#define FPGA_DC_OFST_13_C_M 0xFFFFFFFF
#define INV_TIASHRINK_C 0xC038
#define INV_TIASHRINK_C_M 0x1
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_cr_info_8852b.h
|
C
|
agpl-3.0
| 602,503
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#include "halbb_hwimg_raw_data_8852b.h"
#include "halbb_hwimg_raw_data_8852b_gain.h"
#ifdef BB_8852B_SUPPORT
bool halbb_sel_headline_8852b(struct bb_info *bb, u32 *array, u32 array_len,
u8 *headline_size, u8 *headline_idx)
{
bool case_match = false;
u32 cut_drv = (u32)bb->hal_com->cv;
u32 rfe_drv = (u32)bb->phl_com->dev_cap.rfe_type;
u32 cut_para = 0, rfe_para = 0;
u32 compare_target = 0;
u32 cut_max = 0;
u32 i = 0;
*headline_idx = 0;
*headline_size = 0;
if (bb->bb_dbg_i.cr_dbg_mode_en) {
rfe_drv = bb->bb_dbg_i.rfe_type_curr_dbg;
cut_drv = bb->bb_dbg_i.cut_curr_dbg;
}
BB_DBG(bb, DBG_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n",
rfe_drv, cut_drv, bb->bb_dbg_i.cr_dbg_mode_en);
while ((i + 1) < array_len) {
if ((array[i] >> 28) != 0xf) {
*headline_size = (u8)i;
break;
}
BB_DBG(bb, DBG_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n",
i, array[i], i+1, array[i+1]);
i += 2;
}
BB_DBG(bb, DBG_INIT, "headline_size=%d\n", i);
if (i == 0)
return true;
/*case_idx:1 {RFE:Match, CV:Match}*/
compare_target = ((rfe_drv & 0xff) << 16) | (cut_drv & 0xff);
BB_DBG(bb, DBG_INIT, "[1] CHK {RFE:Match, CV:Match}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:2 {RFE:Match, CV:Dont care}*/
compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852B & 0xff);
BB_DBG(bb, DBG_INIT, "[2] CHK {RFE:Match, CV:Dont_Care}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:3 {RFE:Match, CV:Max_in_Table}*/
BB_DBG(bb, DBG_INIT, "[3] CHK {RFE:Match, CV:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cut_para = array[i] & 0x0ff;
if (rfe_para == rfe_drv) {
if (cut_para > cut_max) {
cut_max = cut_para;
*headline_idx = (u8)(i >> 1);
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:4 {RFE:Dont Care, CV:Max_in_Table}*/
BB_DBG(bb, DBG_INIT, "[4] CHK {RFE:Dont_Care, CV:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cut_para = array[i] & 0x0ff;
if (rfe_para == DONT_CARE_8852B) {
if (cut_para >= cut_max) {
cut_max = cut_para;
*headline_idx = (u8)(i >> 1);
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:5 {RFE:Not_Match, CV:Not_Match}*/
BB_DBG(bb, DBG_INIT, "[5] CHK {RFE:Not_Match, CV:Not_Match}\n");
BB_DBG(bb, DBG_INIT, "\t all fail\n");
return false;
}
void halbb_flag_2_default_8852b(bool *is_matched, bool *find_target)
{
*is_matched = true;
*find_target = false;
}
bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array,
enum phl_phy_idx phy_idx)
{
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852b_phy_reg;
}
BB_DBG(bb, DBG_INIT, "BBCR_form_folder=%d, len=%d, phy_idx=%d\n",
is_form_folder, array_len, phy_idx);
if (!halbb_sel_headline_8852b(bb, array, array_len, &h_size, &h_idx)) {
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
return false;
}
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halbb_flag_2_default_8852b(&is_matched, &find_target);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852B:
case ELSE_IF_8852B:
cfg_para = v1 & 0x0fffffff;
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852B:
BB_DBG(bb, DBG_INIT, "*else\n");
is_matched = false;
if (!find_target) {
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
return false;
}
break;
case END_8852B:
BB_DBG(bb, DBG_INIT, "*endif\n");
halbb_flag_2_default_8852b(&is_matched, &find_target);
break;
case CHK_8852B:
/*Check this para meets driver's requirement or not*/
if (find_target) {
BB_DBG(bb, DBG_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched)
halbb_cfg_bb_phy_8852b(bb, v1, v2, phy_idx);
break;
}
}
BB_DBG(bb, DBG_INIT, "BBCR Init Success\n\n");
return true;
}
bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852b_phy_reg_gain;
}
BB_DBG(bb, DBG_INIT, "GAIN_TABLE_form_folder=%d, len=%d\n",
is_form_folder, array_len);
if (!halbb_sel_headline_8852b(bb, array, array_len, &h_size, &h_idx)) {
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
return false;
}
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halbb_flag_2_default_8852b(&is_matched, &find_target);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852B:
case ELSE_IF_8852B:
cfg_para = v1 & 0x0fffffff;
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852B:
BB_DBG(bb, DBG_INIT, "*else\n");
is_matched = false;
if (!find_target) {
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
return false;
}
break;
case END_8852B:
BB_DBG(bb, DBG_INIT, "*endif\n");
halbb_flag_2_default_8852b(&is_matched, &find_target);
break;
case CHK_8852B:
/*Check this para meets driver's requirement or not*/
if (find_target) {
BB_DBG(bb, DBG_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched)
halbb_cfg_bb_gain_8852b(bb, v1, v2);
break;
}
}
BB_DBG(bb, DBG_INIT, "BBCR gain Init Success\n\n");
return true;
}
u32
halbb_get_8852b_phy_reg_ver(void)
{
return (u32)BB_REG_RELEASE_VERSION_8852B;
}
#endif /* end of HWIMG_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.c
|
C
|
agpl-3.0
| 8,757
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_HW_IMG_8852B_H_
#define _HALBB_HW_IMG_8852B_H_
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
#define DONT_CARE_8852B 0xff
#define IF_8852B 0x8
#define ELSE_IF_8852B 0x9
#define ELSE_8852B 0xa
#define END_8852B 0xb
#define CHK_8852B 0x4
bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array,
enum phl_phy_idx phy_idx);
bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array);
u32 halbb_get_8852b_phy_reg_ver(void);
#endif /* end of HWIMG_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_8852b.h
|
C
|
agpl-3.0
| 1,714
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 2.0.1.2*/
#ifndef _HALBB_HWIMG_RAW_DATA_8852B_H
#define _HALBB_HWIMG_RAW_DATA_8852B_H
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
const u32 array_mp_8852b_phy_reg[] = {
0x704, 0x601E0100,
0x4000, 0x00000000,
0x4004, 0xCA014000,
0x4008, 0xC751D4F0,
0x400C, 0x44511475,
0x4010, 0x00000000,
0x4014, 0x00000000,
0x4018, 0x4F4C084B,
0x401C, 0x084A4E52,
0x4020, 0x4D504E4B,
0x4024, 0x4F4C0849,
0x4028, 0x08484C50,
0x402C, 0x4C50504C,
0x4030, 0x5454084A,
0x4034, 0x084B5654,
0x4038, 0x6A6C605A,
0x403C, 0x4C4C084C,
0x4040, 0x084B4E4D,
0x4044, 0x4E4C4B4B,
0x4048, 0x4B4B084A,
0x404C, 0x084A4E4C,
0x4050, 0x514F4C4A,
0x4054, 0x524E084A,
0x4058, 0x084A5154,
0x405C, 0x53555554,
0x4060, 0x45450845,
0x4064, 0x08454144,
0x4068, 0x40434445,
0x406C, 0x44450845,
0x4070, 0x08444043,
0x4074, 0x42434444,
0x4078, 0x46450844,
0x407C, 0x08444843,
0x4080, 0x4B4E4A47,
0x4084, 0x4F4C084B,
0x4088, 0x084A4E52,
0x408C, 0x4D504E4B,
0x4090, 0x4F4C0849,
0x4094, 0x08484C50,
0x4098, 0x4C50504C,
0x409C, 0x5454084A,
0x40A0, 0x084B5654,
0x40A4, 0x6A6C605A,
0x40A8, 0x4C4C084C,
0x40AC, 0x084B4E4D,
0x40B0, 0x4E4C4B4B,
0x40B4, 0x4B4B084A,
0x40B8, 0x084A4E4C,
0x40BC, 0x514F4C4A,
0x40C0, 0x524E084A,
0x40C4, 0x084A5154,
0x40C8, 0x53555554,
0x40CC, 0x45450845,
0x40D0, 0x08454144,
0x40D4, 0x40434445,
0x40D8, 0x44450845,
0x40DC, 0x08444043,
0x40E0, 0x42434444,
0x40E4, 0x46450844,
0x40E8, 0x08444843,
0x40EC, 0x4B4E4A47,
0x40F0, 0x00000000,
0x40F4, 0x00000006,
0x40F8, 0x00000000,
0x40FC, 0x8C30C30C,
0x4100, 0x4C30C30C,
0x4104, 0x0C30C30C,
0x4108, 0x0C30C30C,
0x410C, 0x0C30C30C,
0x4110, 0x0C30C30C,
0x4114, 0x28A28A28,
0x4118, 0x28A28A28,
0x411C, 0x28A28A28,
0x4120, 0x28A28A28,
0x4124, 0x28A28A28,
0x4128, 0x28A28A28,
0x412C, 0x06666666,
0x4130, 0x33333333,
0x4134, 0x33333333,
0x4138, 0x33333333,
0x413C, 0x00000031,
0x4140, 0x5100600A,
0x4144, 0x18363113,
0x4148, 0x1D976DDC,
0x414C, 0x1C072DD7,
0x4150, 0x1127CDF4,
0x4154, 0x1E37BDF1,
0x4158, 0x1FB7F1D6,
0x415C, 0x1EA7DDF9,
0x4160, 0x1FE445DD,
0x4164, 0x1F97F1FE,
0x4168, 0x1FF781ED,
0x416C, 0x1FA7F5FE,
0x4170, 0x1E07B913,
0x4174, 0x1FD7FDFF,
0x4178, 0x1E17B9FA,
0x417C, 0x19A66914,
0x4180, 0x10F65598,
0x4184, 0x14A5A111,
0x4188, 0x1D3765DB,
0x418C, 0x17C685CA,
0x4190, 0x1107C5F3,
0x4194, 0x1B5785EB,
0x4198, 0x1F97ED8F,
0x419C, 0x1BC7A5F3,
0x41A0, 0x1FE43595,
0x41A4, 0x1EB7D9FC,
0x41A8, 0x1FE65DBE,
0x41AC, 0x1EC7D9FC,
0x41B0, 0x1976FCFF,
0x41B4, 0x1F77F5FF,
0x41B8, 0x1976FDEC,
0x41BC, 0x198664EF,
0x41C0, 0x11062D93,
0x41C4, 0x10C4E910,
0x41C8, 0x1CA759DB,
0x41CC, 0x1335A9B5,
0x41D0, 0x1097B9F3,
0x41D4, 0x17B72DE1,
0x41D8, 0x1F67ED42,
0x41DC, 0x18074DE9,
0x41E0, 0x1FD40547,
0x41E4, 0x1D57ADF9,
0x41E8, 0x1FE52182,
0x41EC, 0x1D67B1F9,
0x41F0, 0x14860CE1,
0x41F4, 0x1EC7E9FE,
0x41F8, 0x14860DD6,
0x41FC, 0x195664C7,
0x4200, 0x0005E58A,
0x4204, 0x00000000,
0x4208, 0x00000000,
0x420C, 0x7A000000,
0x4210, 0x0F9F3D7A,
0x4214, 0x0040817C,
0x4218, 0x00E10204,
0x421C, 0x227D94CD,
0x4220, 0x08028A28,
0x4224, 0x00000210,
0x4228, 0x04688000,
0x4A48, 0x00000002,
0x422C, 0x0060B002,
0x4230, 0x9A8249A8,
0x4234, 0x26A1469E,
0x4238, 0x2099A824,
0x423C, 0x2359461C,
0x4240, 0x1631A675,
0x4244, 0x2C6B1D63,
0x4248, 0x0000000E,
0x424C, 0x00000001,
0x4250, 0x00000001,
0x4254, 0x00000000,
0x4258, 0x00000000,
0x425C, 0x00000000,
0x4260, 0x0020000C,
0x4264, 0x00000000,
0x4268, 0x00000000,
0x426C, 0x0418317C,
0x4270, 0x2B33135C,
0x4274, 0x00000002,
0x4278, 0x00000000,
0x427C, 0x00000000,
0x4280, 0x00000000,
0x4284, 0x00000000,
0x4288, 0x00000000,
0x428C, 0x00000000,
0x4290, 0x00000000,
0x4294, 0x00000000,
0x4298, 0x00000000,
0x429C, 0x84026000,
0x42A0, 0x0051AC20,
0x4A24, 0x0010C040,
0x42A4, 0x02024008,
0x42A8, 0x00000000,
0x42AC, 0x00000000,
0x42B0, 0x22CE803C,
0x42B4, 0x32000000,
0x42B8, 0x996FD67D,
0x42BC, 0xBD67D67D,
0x42C0, 0x7D67D65B,
0x42C4, 0x28029F59,
0x42C8, 0x00280280,
0x42CC, 0x00000000,
0x42D0, 0x00000000,
0x42D4, 0x00000003,
0x42D8, 0x00000001,
0x42DC, 0x61861800,
0x42E0, 0x830C30C3,
0x42E4, 0xC30C30C3,
0x42E8, 0x830C30C3,
0x42EC, 0x451450C3,
0x42F0, 0x05145145,
0x42F4, 0x05145145,
0x42F8, 0x05145145,
0x42FC, 0x0F0C3145,
0x4300, 0x030C30CF,
0x4304, 0x030C30C3,
0x4308, 0x030CF3C3,
0x430C, 0x030C30C3,
0x4310, 0x0F3CF3C3,
0x4314, 0x0F3CF3CF,
0x4318, 0x0F3CF3CF,
0x431C, 0x0F3CF3CF,
0x4320, 0x0F3CF3CF,
0x4324, 0x030C10C3,
0x4328, 0x051430C3,
0x432C, 0x051490CB,
0x4330, 0x030CD151,
0x4334, 0x050C50C7,
0x4338, 0x051492CB,
0x433C, 0x05145145,
0x4340, 0x05145145,
0x4344, 0x05145145,
0x4348, 0x05145145,
0x434C, 0x090CD3CF,
0x4350, 0x071491C5,
0x4354, 0x073CF143,
0x4358, 0x071431C3,
0x435C, 0x0F3CF1C5,
0x4360, 0x0F3CF3CF,
0x4364, 0x0F3CF3CF,
0x4368, 0x0F3CF3CF,
0x436C, 0x0F3CF3CF,
0x4370, 0x090C91CF,
0x4374, 0x11243143,
0x4378, 0x9777A777,
0x437C, 0xBB7BAC95,
0x4380, 0xB667B889,
0x4384, 0x7B9B8899,
0x4388, 0x7A5567C8,
0x438C, 0x2278CCCC,
0x4390, 0x7C222222,
0x4394, 0x0000069B,
0x4398, 0x001CCCCC,
0x4AAC, 0xCCCCC88C,
0x4AB0, 0x0000AACC,
0x439C, 0x00000000,
0x43A0, 0x00000008,
0x43A4, 0x00000000,
0x43A8, 0x00000000,
0x43AC, 0x00000000,
0x43B0, 0x10000000,
0x43B4, 0x00401001,
0x43B8, 0x00061003,
0x43BC, 0x000024D8,
0x43C0, 0x00000000,
0x43C4, 0x10000020,
0x43C8, 0x20000200,
0x43CC, 0x00000000,
0x43D0, 0x04000000,
0x43D4, 0x44000100,
0x43D8, 0x60804060,
0x43DC, 0x44204210,
0x43E0, 0x82108082,
0x43E4, 0x82108402,
0x43E8, 0xC8082108,
0x43EC, 0xC8202084,
0x43F0, 0x44208208,
0x43F4, 0x84108204,
0x43F8, 0xD0108104,
0x43FC, 0xF8210108,
0x4400, 0x6431E930,
0x4404, 0x02309468,
0x4408, 0x10C61C22,
0x440C, 0x02109469,
0x4410, 0x10C61C22,
0x4414, 0x00041049,
0x4A4C, 0x00060581,
0x4418, 0x00000000,
0x441C, 0x00000000,
0x4420, 0x6C000000,
0x4424, 0xB0200020,
0x4428, 0x00001FF0,
0x442C, 0x00000000,
0x4430, 0x00000000,
0x4434, 0x00000000,
0x4438, 0x00000000,
0x443C, 0x190642D0,
0x4440, 0xA80668A0,
0x4444, 0x60900820,
0x4448, 0x9F28518C,
0x444C, 0x32488A62,
0x4450, 0x9C6E36DC,
0x4454, 0x0000F52B,
0x4458, 0x00000000,
0x445C, 0x4801442E,
0x4460, 0x0051A0B8,
0x4464, 0x00000000,
0x4468, 0x00000000,
0x446C, 0x00000000,
0x4470, 0x00000000,
0x4474, 0x00000000,
0x4478, 0x00000000,
0x447C, 0x00000000,
0x4480, 0x2A0A6040,
0x4484, 0x0A0A6829,
0x4488, 0x00000004,
0x448C, 0x00000000,
0x4490, 0x80000000,
0x4494, 0x13000000,
0x4498, 0xE0000000,
0x4AB4, 0x00000000,
0x449C, 0x0000001E,
0x44A0, 0x02B2C3A6,
0x44A4, 0x00000400,
0x44A8, 0x00000001,
0x44AC, 0x000190C0,
0x44B0, 0x00000000,
0x44B4, 0x00000000,
0x44B8, 0x00000000,
0x44BC, 0x00000000,
0x44C0, 0x00000000,
0x44C4, 0x00000000,
0x44C8, 0x00000000,
0x44CC, 0x00000000,
0x44D0, 0x00000000,
0x44D4, 0x00000000,
0x44D8, 0x00000000,
0x44DC, 0x00000000,
0x44E0, 0x00000000,
0x44E4, 0x00000000,
0x44E8, 0x00000000,
0x44EC, 0x00000000,
0x44F0, 0x00000000,
0x44F4, 0x00000000,
0x44F8, 0x00000000,
0x44FC, 0x00000000,
0x4500, 0x00000000,
0x4504, 0x00000000,
0x4508, 0x00000000,
0x450C, 0x00000000,
0x4510, 0x00000000,
0x4514, 0x00000000,
0x4518, 0x00000000,
0x451C, 0x00000000,
0x4520, 0x00000000,
0x4524, 0x00000000,
0x4528, 0x00000000,
0x452C, 0x00000000,
0x4530, 0x4E830171,
0x4534, 0x00000870,
0x4538, 0x000000FF,
0x453C, 0x00000000,
0x4540, 0x00000000,
0x4544, 0x00000000,
0x4548, 0x00000000,
0x454C, 0x00000000,
0x4550, 0x00000000,
0x4554, 0x00000000,
0x4558, 0x00000000,
0x455C, 0x00000000,
0x4560, 0x40000000,
0x4564, 0x40000000,
0x4568, 0x00000000,
0x456C, 0x20000000,
0x4570, 0x04F040BB,
0x4574, 0x000E53FF,
0x4578, 0x000205CB,
0x457C, 0x00200000,
0x4580, 0x00000040,
0x4584, 0x00000000,
0x4588, 0x00000017,
0x458C, 0x30000000,
0x4590, 0x00000000,
0x4594, 0x00000000,
0x4598, 0x00000001,
0x459C, 0x0003FE00,
0x45A0, 0x00000086,
0x45A4, 0x00000000,
0x45A8, 0xC00001C0,
0x45AC, 0x78038000,
0x45B0, 0x8000004A,
0x45B4, 0x04094800,
0x45B8, 0x00280002,
0x45BC, 0x06748790,
0x45C0, 0x80000000,
0x45C4, 0x00000000,
0x45C8, 0x00000000,
0x45CC, 0x00558670,
0x45D0, 0x002883F0,
0x45D4, 0x00090120,
0x45D8, 0x00000000,
0x45E0, 0xA3A6D3C4,
0x45E4, 0xAB27B126,
0x45E8, 0x00006778,
0x45F4, 0x000001B5,
0x45EC, 0x11110F0A,
0x45F0, 0x00000003,
0x4A0C, 0x0000000A,
0x45F8, 0x0058BC3F,
0x45FC, 0x00000003,
0x462C, 0x00000020,
0x4600, 0x000003D9,
0x45F0, 0x00000004,
0x4604, 0x002B1CB0,
0x4A50, 0xC0000000,
0x4A54, 0x00001000,
0x4A58, 0x00000000,
0x4A18, 0x00000024,
0x4608, 0x00000001,
0x460C, 0x00000000,
0x4A10, 0x00000001,
0x4610, 0x00000001,
0x4614, 0x16E5298F,
0x4618, 0x18C6294A,
0x461C, 0x0E06318A,
0x4620, 0x0E539CE5,
0x4624, 0x00019287,
0x4A14, 0x000000BF,
0x4628, 0x00000001,
0x4630, 0x000001AA,
0x4A18, 0x00001900,
0x4A1C, 0x000002A6,
0x4634, 0x000000A3,
0x4A20, 0x00000086,
0x4638, 0x01986456,
0x49F8, 0x00000000,
0x463C, 0x00000000,
0x4640, 0x00000000,
0x4644, 0x00C8CC00,
0x4648, 0xC400B6B6,
0x464C, 0xDC400FC0,
0x4A8C, 0x00000110,
0x4650, 0x08882550,
0x4654, 0x08CC2660,
0x4658, 0x09102660,
0x465C, 0x00000154,
0x45DC, 0xC39E38E8,
0x4660, 0x452607E6,
0x4664, 0x6750DC65,
0x4668, 0xF3F0F1ED,
0x466C, 0x30141506,
0x4670, 0x2C2B2B2B,
0x4674, 0x2C2C2C2C,
0x4678, 0xDDB738E8,
0x467C, 0x543618FB,
0x4680, 0x4F31DC6F,
0x4684, 0xFBEBDA00,
0x4688, 0x1A10FF04,
0x468C, 0x282A3000,
0x4690, 0x2A29292A,
0x4694, 0x04FA2A2A,
0x4698, 0xEE0F04D1,
0x469C, 0x99E91436,
0x46A0, 0x0701E79E,
0x46A4, 0x08D77CFF,
0x46A8, 0x2212FF14,
0x46AC, 0x60322437,
0x46B0, 0x63666666,
0x46B4, 0x35374425,
0x46B8, 0x35883042,
0x46BC, 0x5177C252,
0x4720, 0x7FFFFD63,
0x4724, 0xB58D11FF,
0x4728, 0x07FFFFFF,
0x472C, 0x0E7893B6,
0x4730, 0xE0391201,
0x4734, 0x00000020,
0x4738, 0x8325C500,
0x473C, 0x00000B7F,
0x46C0, 0x00000000,
0x46C4, 0x00000000,
0x46C8, 0x00000219,
0x46CC, 0x00000000,
0x46D0, 0x00000000,
0x46D4, 0x00000001,
0x46D8, 0x00000001,
0x46DC, 0x00000000,
0x46E0, 0x00000000,
0x46E4, 0x00000151,
0x46E8, 0x00000498,
0x46EC, 0x00000498,
0x46F0, 0x00000000,
0x46F4, 0x00000000,
0x46F8, 0x00001146,
0x46FC, 0x00000000,
0x4700, 0x00000000,
0x4704, 0x00C8CC00,
0x4708, 0xC400B6B6,
0x470C, 0xDC400FC0,
0x4A90, 0x00000110,
0x4710, 0x08882550,
0x4714, 0x08CC2660,
0x4718, 0x09102660,
0x471C, 0x00000154,
0x4740, 0xC69F38E8,
0x4744, 0x462709E9,
0x4748, 0x6750DC67,
0x474C, 0xF3F0F1ED,
0x4750, 0x30141506,
0x4754, 0x2C2B2B2B,
0x4758, 0x2C2C2C2C,
0x475C, 0xE0B738E8,
0x4760, 0x52381BFE,
0x4764, 0x5031DC6C,
0x4768, 0xFBEBDA00,
0x476C, 0x1A10FF04,
0x4770, 0x282A3000,
0x4774, 0x2A29292A,
0x4778, 0x04FA2A2A,
0x477C, 0xEE0F04D1,
0x49F0, 0x99E91436,
0x49F4, 0x0701E79E,
0x49FC, 0x08D77CFF,
0x4A5C, 0x2212FF14,
0x4A60, 0x60322437,
0x4A64, 0x63666666,
0x4A68, 0x35374425,
0x4A6C, 0x35883042,
0x4A70, 0x5177C252,
0x4A74, 0x7FFFFD63,
0x4A78, 0xB58D11FF,
0x4A7C, 0x07FFFFFF,
0x4A80, 0x0E7893B6,
0x4A9C, 0xE0391201,
0x4AA0, 0x00000020,
0x4AA4, 0x8325C500,
0x4AA8, 0x00000B7F,
0x4780, 0x00000000,
0x4784, 0x00000000,
0x4788, 0x00000219,
0x478C, 0x00000000,
0x4790, 0x00000000,
0x4794, 0x00000001,
0x4798, 0x00000001,
0x479C, 0x00000000,
0x47A0, 0x00000000,
0x47A4, 0x00000151,
0x47A8, 0x00000498,
0x47AC, 0x00000498,
0x47B0, 0x00000000,
0x47B4, 0x00000000,
0x47B8, 0x00001146,
0x47BC, 0x00000002,
0x47C0, 0x00000002,
0x47C4, 0x00000000,
0x47C8, 0xA32103FE,
0x47CC, 0xB20A5328,
0x47D0, 0xC686314F,
0x47D4, 0x000005D7,
0x47D8, 0x009B902A,
0x47DC, 0x009B902A,
0x47E0, 0x98682C18,
0x47E4, 0x6308C4C1,
0x47E8, 0x6248C631,
0x47EC, 0x922A8253,
0x47F0, 0x00000005,
0x47F4, 0x00001759,
0x47F8, 0x4BB02000,
0x47FC, 0x831408BE,
0x4A84, 0x000000E9,
0x4800, 0x9ABBCACB,
0x4804, 0x56767578,
0x4808, 0xBCCBBB13,
0x480C, 0x7889989B,
0x4810, 0xBBB0F455,
0x4814, 0x777BBBBB,
0x4818, 0x15277777,
0x481C, 0x27039CE9,
0x4820, 0x42424432,
0x4824, 0x36058342,
0x4828, 0x00000006,
0x482C, 0x00000005,
0x4830, 0x00000005,
0x4834, 0xC7013016,
0x4838, 0x84413016,
0x483C, 0x84413016,
0x4840, 0x8C413016,
0x4844, 0x8C40B028,
0x4848, 0x3140B028,
0x484C, 0x2940B028,
0x4850, 0x8440B028,
0x4854, 0x2318C610,
0x4858, 0x45344753,
0x485C, 0x236A6A88,
0x4860, 0xAC8DF814,
0x4864, 0x08877ACB,
0x4868, 0x000107AA,
0x4A94, 0x00000000,
0x486C, 0xBCEB4A14,
0x4870, 0x000A3A4A,
0x4874, 0xBCEB4A14,
0x4878, 0x000A3A4A,
0x487C, 0xBCBDBD85,
0x4880, 0x0CABB99A,
0x4884, 0x38384242,
0x4888, 0x0086102E,
0x488C, 0xCA24C82A,
0x4890, 0x00008A62,
0x4894, 0x00000008,
0x4898, 0x009B902A,
0x489C, 0x009B902A,
0x48A0, 0x98682C18,
0x48A4, 0x6308C4C1,
0x48A8, 0x6248C631,
0x48AC, 0x922A8253,
0x48B0, 0x00000005,
0x48B4, 0x00001759,
0x48B8, 0x4BA02000,
0x48BC, 0x831408BE,
0x4A88, 0x000000E9,
0x48C0, 0x9898A8BB,
0x48C4, 0x54535368,
0x48C8, 0x99999B13,
0x48CC, 0x55555899,
0x48D0, 0xBBB07453,
0x48D4, 0x777BBBBB,
0x48D8, 0x15277777,
0x48DC, 0x27039CE9,
0x48E0, 0x31413432,
0x48E4, 0x36058342,
0x48E8, 0x00000006,
0x48EC, 0x00000005,
0x48F0, 0x00000005,
0x48F4, 0xC7013016,
0x48F8, 0x84413016,
0x48FC, 0x84413016,
0x4900, 0x8C413016,
0x4904, 0x8C40B028,
0x4908, 0x3140B028,
0x490C, 0x2940B028,
0x4910, 0x8440B028,
0x4914, 0x2318C610,
0x4918, 0x45334753,
0x491C, 0x236A6A88,
0x4920, 0xAC8DF814,
0x4924, 0x08877ACB,
0x4928, 0x000007AA,
0x4A98, 0x00000000,
0x492C, 0xBCEB4A14,
0x4930, 0x000A3A4A,
0x4934, 0xBCEB4A14,
0x4938, 0x000A3A4A,
0x493C, 0x9A8A8A85,
0x4940, 0x0CA3B99A,
0x4944, 0x38384242,
0x4948, 0x8086102E,
0x494C, 0xCA24C82A,
0x4950, 0x00008A62,
0x4954, 0x00000008,
0x4958, 0x80040000,
0x495C, 0x80040000,
0x4960, 0xFE800000,
0x4964, 0x834C0000,
0x4968, 0x00000000,
0x496C, 0x00000000,
0x4970, 0x00000000,
0x4974, 0x00000000,
0x4978, 0x00000000,
0x497C, 0x00000000,
0x4980, 0x40000000,
0x4984, 0x00000000,
0x4988, 0x00000000,
0x498C, 0x00000000,
0x4990, 0x00000000,
0x4994, 0x04065800,
0x4998, 0x02004080,
0x499C, 0x0E1E3E05,
0x49A0, 0x0A163068,
0x49A4, 0x00206040,
0x49A8, 0x02020202,
0x49AC, 0x00002020,
0x49B0, 0xF8F8F418,
0x49B4, 0x28E8F8F8,
0x49B8, 0x280808E8,
0x4A00, 0xF8F8FA00,
0x4A04, 0xFAFAFAF8,
0x4A08, 0xFAFAFAFA,
0x4A28, 0xFAFAFAFA,
0x4A2C, 0xFAFAFAFA,
0x4A30, 0xFAFAFAFA,
0x4A34, 0xFAFAFAFA,
0x4A38, 0xFAFAFAFA,
0x4A3C, 0xFAFAFAFA,
0x4A40, 0xFAFAFAFA,
0x4A44, 0x0000FAFA,
0x49BC, 0x00000000,
0x49C0, 0x800CD62D,
0x49C4, 0x00000103,
0x49C8, 0x00000000,
0x49CC, 0x00000000,
0x49D0, 0x00000000,
0x49D4, 0x00000000,
0x49D8, 0x00000000,
0x49DC, 0x00000000,
0x49E0, 0x00000000,
0x49E4, 0x00000000,
0x49E8, 0x00000000,
0x49EC, 0x00000000,
0x994, 0x00000010,
0x904, 0x00000005,
0xC3C, 0x2840E1BF,
0xC40, 0x00000000,
0xC44, 0x00000007,
0xC48, 0x410E4000,
0xC54, 0x1EE14368,
0xC58, 0x41000000,
0x730, 0x00000002,
0xC60, 0x017FFFF2,
0xC64, 0x0010A130,
0xC68, 0x10000050,
0xC6C, 0x10001021,
0x708, 0x00000000,
0x884, 0x0043F01D,
0x704, 0x601E0100,
0x710, 0xEF810000,
0x704, 0x601E0100,
0xD40, 0xF64FA0F7,
0xD44, 0x0400063F,
0xD48, 0x0003FF7F,
0xD4C, 0x00000000,
0xD50, 0xF64FA0F7,
0xD54, 0x04100437,
0xD58, 0x0000FF7F,
0xD5C, 0x00000000,
0xD60, 0x00000000,
0xD64, 0x00000000,
0xD70, 0x00000015,
0xD90, 0x000003FF,
0xD94, 0x00000000,
0xD98, 0x0000003F,
0xD9C, 0x00000000,
0xDA0, 0x000003FE,
0xDA4, 0x00000000,
0xDA8, 0x0000003F,
0xDAC, 0x00000000,
0xD00, 0x77777777,
0xD04, 0xBBBBBBBB,
0xD08, 0xBBBBBBBB,
0xD0C, 0x00000070,
0xD10, 0x20110900,
0xD10, 0x20110FFF,
0xD78, 0x00000001,
0xD7C, 0x001D050E,
0xD84, 0x00004207,
0xD18, 0x50209900,
0xD80, 0x00804100,
0x718, 0x1333233F,
0x604, 0x041E1E1E,
0x714, 0x00010000,
0x586C, 0x000000F0,
0x586C, 0x000000E0,
0x586C, 0x000000D0,
0x586C, 0x000000C0,
0x586C, 0x000000B0,
0x586C, 0x000000A0,
0x586C, 0x00000090,
0x586C, 0x00000080,
0x586C, 0x00000070,
0x586C, 0x00000060,
0x586C, 0x00000050,
0x586C, 0x00000040,
0x586C, 0x00000030,
0x586C, 0x00000020,
0x586C, 0x00000010,
0x586C, 0x00000000,
0x786C, 0x000000F0,
0x786C, 0x000000E0,
0x786C, 0x000000D0,
0x786C, 0x000000C0,
0x786C, 0x000000B0,
0x786C, 0x000000A0,
0x786C, 0x00000090,
0x786C, 0x00000080,
0x786C, 0x00000070,
0x786C, 0x00000060,
0x786C, 0x00000050,
0x786C, 0x00000040,
0x786C, 0x00000030,
0x786C, 0x00000020,
0x786C, 0x00000010,
0x786C, 0x00000000,
0xC0D4, 0x4486888C,
0xC0D8, 0xC6BA10E1,
0xC0DC, 0x30C52868,
0xC0E0, 0x05008128,
0xC0E4, 0x0000A72B,
0xC1D4, 0x4486888C,
0xC1D8, 0xC6BA10E1,
0xC1DC, 0x30C52868,
0xC1E0, 0x05008128,
0xC1E4, 0x0000A72B,
0xC0EC, 0x00000000,
0xC0E4, 0x0000272B,
0xC1EC, 0x00000000,
0xC1E4, 0x0000272B,
0x334, 0xFFFFFFFF,
0x33C, 0x55000000,
0x340, 0x00005555,
0x724, 0x00111200,
0x5868, 0xA9550000,
0x5870, 0x33221100,
0x5874, 0x77665544,
0x5878, 0xBBAA9988,
0x587C, 0xFFEEDDCC,
0x5880, 0x76543210,
0x5884, 0xFEDCBA98,
0x5888, 0x00000000,
0x588C, 0x00000000,
0x5894, 0x00000008,
0x7868, 0xA9550000,
0x7870, 0x33221100,
0x7874, 0x77665544,
0x7878, 0xBBAA9988,
0x787C, 0xFFEEDDCC,
0x7880, 0x76543210,
0x7884, 0xFEDCBA98,
0x7888, 0x00000000,
0x788C, 0x00000000,
0x7894, 0x00000008,
0x650, 0x00200888,
0x710, 0xF3810000,
0x020, 0x0000F381,
0x024, 0x0000F381,
0x000, 0xC580801E,
0xC70, 0x00000400,
0x980, 0x10002250,
0x988, 0x3C3C4107,
0x994, 0x00000010,
0x2994, 0x00000010,
0x000, 0x0580801F,
0x240C, 0x00000000,
0x640, 0x140A141E,
0x640, 0x1414141E,
0x640, 0x1414141E,
0x644, 0x3414283C,
0x644, 0x3425283C,
0x644, 0x3426283C,
0x2640, 0x140A141E,
0x2640, 0x1414141E,
0x2640, 0x1414141E,
0x2644, 0x3414283C,
0x2644, 0x3425283C,
0x2644, 0x3425183C,
0x2300, 0x02748790,
0x2304, 0x00558670,
0x2308, 0x002883F0,
0x230C, 0x00090120,
0x2310, 0x00000000,
0x2314, 0x06000000,
0x2318, 0x00000000,
0x231C, 0x00000000,
0x2320, 0x03020100,
0x2324, 0x07060504,
0x2328, 0x0B0A0908,
0x232C, 0x0F0E0D0C,
0x2330, 0x13121110,
0x2334, 0x17161514,
0x2338, 0x0C700022,
0x233C, 0x0A0529D0,
0x2340, 0x000529D0,
0x2344, 0x0006318A,
0x2348, 0xB7E6318A,
0x234C, 0x80039CE7,
0x2350, 0x80039CE7,
0x2354, 0x0005298F,
0x2358, 0x0015296E,
0x235C, 0x0C07FC31,
0x2360, 0x0219AAAE,
0x2364, 0xE4F624C3,
0x2368, 0x53626F15,
0x236C, 0x48000000,
0x2370, 0x48000000,
0x2374, 0x07540000,
0x2378, 0x202401B9,
0x237C, 0x00F7000E,
0x2380, 0x0F0A1111,
0x2384, 0x30D9000F,
0x2388, 0x0200EA02,
0x238C, 0x003CB061,
0x2390, 0x69C00000,
0x2394, 0x00000000,
0x2398, 0x000000F0,
0x239C, 0x0001FFFF,
0x23A0, 0x00C80064,
0x23A4, 0x0190012C,
0x23A8, 0x001917BE,
0x23AC, 0x0B30880C,
0x23B0, 0xB501CE00,
0x23B4, 0xDD027C00,
0x704, 0x601E0102,
0x704, 0x601E0102,
0x5864, 0x080801FF,
0x7864, 0x080801FF,
0xC60, 0x017FFFF3,
0x58AC, 0x08000000,
0x78AC, 0x08000000,
0x8088, 0x007F0000,
0x81A4, 0x003F3A00,
0x81B4, 0x0100007F,
0x81C0, 0x0060010B,
0x81A0, 0x00000010,
0x8138, 0x00000002,
0x82A4, 0x003F3A00,
0x82B4, 0x0100007F,
0x82C0, 0x0060010B,
0x82A0, 0x00000010,
0x81A0, 0x00000010,
0x8238, 0x00000002,
0x8088, 0x00000000,
0x8020, 0x00000000,
0x8120, 0x00000000,
0x8220, 0x00000000,
0x8124, 0x00000F0F,
0x8224, 0x00000F0F,
0x5864, 0x180801FF,
0x7864, 0x180801FF,
0xC60, 0x017FFFF3,
0xC70, 0x00000600,
0xC70, 0x00000660,
0x58AC, 0x08000000,
0x78AC, 0x08000000,
0x8120, 0x10000000,
0x8120, 0x10030000,
0x8124, 0x00000F0F,
0x8124, 0x00000F0F,
0x8224, 0x00000F0F,
0x8224, 0x00000F0F,
0x8220, 0x10000000,
0x8220, 0x10030000,
0x704, 0x601E0100,
0x5864, 0x100801FF,
0x7864, 0x100801FF,
0x5864, 0x180801FF,
0x7864, 0x180801FF,
0x58D4, 0x7401FE00,
0x78D4, 0x7401FE00,
0x58F0, 0x400401FF,
0x78F0, 0x400401FF,
0x58F0, 0x400401FF,
0x78F0, 0x400401FF,
0x704, 0x601E0102,
0xC7C, 0x0020BFE0,
0x58C0, 0x00FE0000,
0x58FC, 0x00000000,
0x566C, 0x00000005,
0x566C, 0x00001005,
0x78C0, 0x00FE0000,
0x78FC, 0x00000000,
0x700, 0x00000030,
0x704, 0x601E0102,
0x704, 0x601E0100,
0x704, 0x601E0502,
0x20FC, 0x00000000,
0x20F8, 0x00000000,
0x20F0, 0x00000000,
0x9C0, 0x00000001,
0x9C0, 0x00000000,
0x9C0, 0x00000001,
0x9C0, 0x00000000,
0x4AE8, 0x00000744,
0x4AF0, 0x00000744,
0x1010, 0x00000010,
0x3010, 0x00000010,
0x4AD4, 0x00000060,
0x4AE0, 0x00000060,
0x4AE4, 0x0079E99E,
0x4AEC, 0x0079E99E,
0x300, 0xF30CE31C,
0x304, 0x13EF1F19,
0x308, 0x0C0CF3F3,
0x30C, 0x0C0C0C0C,
0x310, 0x80496000,
0x314, 0x0041E000,
0x318, 0x20022042,
0x31C, 0x20448009,
0x320, 0x00010031,
0x324, 0xE000E000,
0x328, 0xE000E000,
0x32C, 0xE000E000,
0x12BC, 0x10104041,
0x12C0, 0x14411111,
0x32BC, 0x10104041,
0x32C0, 0x14411111,
0x010, 0x0005FFFF,
0x028, 0x0000F381,
0x02C, 0x0000F381,
0x620, 0x00141230,
0x704, 0x601C05FF,
0x720, 0x20000000,
0x738, 0x004100CC,
0x12A0, 0x24903056,
0x12AC, 0x12333121,
0x12B8, 0x30020000,
0x12E4, 0x30D52A68,
0x2000, 0x18BBBF84,
0x32A0, 0x24903056,
0x32AC, 0x12333121,
0x32B8, 0x30020000,
0x32E4, 0x30D52A68,
0x5800, 0x03FF807F,
0x5804, 0x04237040,
0x5808, 0x04237040,
0x7800, 0x03FF807F,
0x7804, 0x04237040,
0x7808, 0x04237040,
0x73C, 0x00000002,
0x74C, 0x00000001,
0x748, 0x00000002,
0x5818, 0x082C1800,
0x7818, 0x082C1800,
0x624, 0x0101030A,
0xC14, 0x85010000,
0xDD4, 0x00000001,
0x241C, 0x00000001,
0x1200, 0x00010142,
0x3200, 0x00010142,
0xC0F8, 0x00000001,
0xC1F8, 0x00000001,
0x35C, 0x000004C4,
0x0F0, 0x00000002,
0x0F4, 0x00000023,
0x0F8, 0x20210903,
};
/******************************************************************************
* phy_reg_gain.TXT
******************************************************************************/
const u32 array_mp_8852b_phy_reg_gain[] = {
0x000, 0x18FBDDB7,
0x001, 0x006F5436,
0x002, 0x00004F31,
0x100, 0x1BFEE0B7,
0x101, 0x006C5238,
0x102, 0x00005031,
0x10000, 0x07E6C39E,
0x10001, 0x00654526,
0x10002, 0x00006750,
0x10100, 0x09E9C69F,
0x10101, 0x00674627,
0x10102, 0x00006750,
0x20000, 0x06E8C49F,
0x20001, 0x00654526,
0x20002, 0x00006750,
0x20100, 0x07E9C6A0,
0x20101, 0x00674728,
0x20102, 0x00006850,
0x30000, 0x04E5C39D,
0x30001, 0x00634325,
0x30002, 0x00006750,
0x30100, 0x06E9C69F,
0x30101, 0x00654527,
0x30102, 0x00006750,
0x1000000, 0x000000F4,
0x1000010, 0x000000F8,
0x1000011, 0x0000F8F8,
0x1000100, 0x000000F8,
0x1000110, 0x00000000,
0x1000111, 0x00000000,
0x1010000, 0x000000F4,
0x1010010, 0x000000F8,
0x1010011, 0x0000F8F8,
0x1010020, 0x000000F8,
0x1010021, 0x0808E8E8,
0x1010029, 0x00002828,
0x1010100, 0x000000F4,
0x1010110, 0x000000F8,
0x1010111, 0x0000F8F8,
0x1010120, 0x000000F8,
0x1010121, 0x0808E8E8,
0x1010129, 0x00002828,
0x1020000, 0x000000F4,
0x1020010, 0x000000F8,
0x1020011, 0x0000F8F8,
0x1020020, 0x000000F8,
0x1020021, 0x0808E8E8,
0x1020029, 0x00002828,
0x1020100, 0x000000F4,
0x1020110, 0x000000F8,
0x1020111, 0x0000F8F8,
0x1020120, 0x000000F8,
0x1020121, 0x0808E8E8,
0x1020129, 0x00002828,
0x1030000, 0x000000F4,
0x1030010, 0x000000F8,
0x1030011, 0x0000F8F8,
0x1030020, 0x000000F8,
0x1030021, 0x0808E8E8,
0x1030029, 0x00002828,
0x1030100, 0x000000F4,
0x1030110, 0x000000F8,
0x1030111, 0x0000F8F8,
0x1030120, 0x000000F8,
0x1030121, 0x0808E8E8,
0x1030129, 0x00002828,
};
#endif /* _HALBB_HWIMG_RAW_DATA_8852B_H */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b.h
|
C
|
agpl-3.0
| 25,388
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 2.0.1.2*/
#ifndef _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H
#define _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H
#endif /* _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_hwimg_raw_data_8852b_gain.h
|
C
|
agpl-3.0
| 1,139
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852B_SUPPORT
void halbb_cfg_rf_reg_8852b(struct bb_info *bb, u32 addr, u32 data,
enum rf_path rf_path, u32 reg_addr)
{
}
void halbb_cfg_rf_radio_a_8852b(struct bb_info *bb, u32 addr, u32 data)
{
}
void halbb_cfg_rf_radio_b_8852b(struct bb_info *bb, u32 addr, u32 data)
{
}
void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DBCC_SUPPORT
u32 ofst = 0;
#endif
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else {
#ifdef HALBB_DBCC_SUPPORT
if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) &&
phy_idx == HW_PHY_1) {
ofst = halbb_phy0_to_phy1_ofst(bb, addr);
if (ofst == 0)
return;
addr += ofst;
} else {
phy_idx = HW_PHY_0;
}
BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data);
#else
BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data);
#endif
halbb_set_reg(bb, addr, MASKDWORD, data);
}
}
void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u8 cfg_type = (u8)((addr & 0xff000000) >> 24);
enum bb_band_t band_idx = (enum bb_band_t)((addr & 0xff0000) >> 16);
u8 path = (u8)((addr & 0xff00) >> 8);
u8 type;
u8 i = 0;
if (band_idx >= BB_GAIN_BAND_NUM)
return;
if (path >= HALBB_MAX_PATH)
return;
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else if (cfg_type ==0) { /*GAIN ERROR*/
type = (u8)(addr & 0xff);
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 2; i++)
gain->tia_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
}
} else if (cfg_type == 1) { /*RPL Offset*/
halbb_cfg_bb_rpl_ofst(bb, band_idx, path, addr, data);
} else {
BB_WARNING("cfg_type=%d\n", cfg_type);
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.c
|
C
|
agpl-3.0
| 3,998
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_REG_CFG_8852B_H_
#define _HALBB_REG_CFG_8852B_H_
#ifdef BB_8852B_SUPPORT
void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data);
#endif
#endif /* RTL8852B_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_reg_cfg_8852b.h
|
C
|
agpl-3.0
| 1,266
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852B BB Parameters*/
#ifndef _HALBB_VERSION_8852B_H_
#define _HALBB_VERSION_8852B_H_
#define BB_REG_RELEASE_DATE_8852B 20210903
#define BB_REG_RELEASE_VERSION_8852B 23
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_8852b/halbb_version_rtl8852b.h
|
C
|
agpl-3.0
| 1,152
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_ANT_DIV_SUPPORT
void halbb_antdiv_reset_training_stat(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i;
struct bb_antdiv_rssi_info *bb_rssi_i = &bb_ant_div->bb_rssi_i;
struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i;
halbb_mem_set(bb, bb_rate_i, 0, sizeof(struct bb_antdiv_rate_info));
halbb_mem_set(bb, bb_cn_i, 0, sizeof(struct bb_antdiv_cn_info));
halbb_mem_set(bb, bb_evm_i, 0, sizeof(struct bb_antdiv_evm_info));
halbb_mem_set(bb, bb_rssi_i, 0, sizeof(struct bb_antdiv_rssi_info));
}
void halbb_antdiv_reset(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i;
/* Reset stat */
halbb_antdiv_reset_training_stat(bb);
}
void halbb_antdiv_reg_init(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i;
/* dis r_ant_train_en */
halbb_set_reg_cmn(bb, cr->path0_r_ant_train_en, cr->path0_r_ant_train_en_m, 0x0, HW_PHY_0);
/* force r_tx_ant_sel instead of from FW CMAC table */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(1), 0x0, HW_PHY_0);
#ifdef BB_8852A_CAV_SUPPORT
/* r_trsw_tx_extend = 0us */
halbb_set_reg_cmn(bb, 0x828, 0xf, 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE
/* dis r_hw_antsw_dis_by_gnt_bt */
halbb_set_reg_cmn(bb, 0x828, BIT(12), 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE
#endif
#ifdef HALBB_COMPILE_AP_SERIES
/* r_trsw_tx_extend = 0us */
halbb_set_reg_cmn(bb, 0x2728, 0xf, 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE
/* dis r_hw_antsw_dis_by_gnt_bt */
halbb_set_reg_cmn(bb, 0x2728, BIT(12), 0x0, HW_PHY_0); // CAV:0x8; CBV:0x27 JOE
#endif
/* dis r_bt_force_en */
halbb_set_reg_cmn(bb, cr->path0_r_bt_force_antidx_en, cr->path0_r_bt_force_antidx_en_m, 0x0, HW_PHY_0);
/* r_rfsw_ctrl_antenna (Antenna mapping) */
halbb_set_reg_cmn(bb, cr->path0_r_rfsw_ant_31_0, 0xFFFF, 0x0100, HW_PHY_0);
/* dis r_BB_SEL_BTG_TRX_S */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(21), 0x1, HW_PHY_0);
/* "antsel" is controlled by HWs*/
halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(16), 0x0, HW_PHY_0);
/* r_ANT_DIV_SW_2G_S, 2G "CS/CG switching" is controlled by HWs */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(23), 0x0, HW_PHY_0);
/* r_ANT_DIV_SW_5G_S, 5G "CS/CG switching" is controlled by HWs */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(25), 0x0, HW_PHY_0);
}
void halbb_antdiv_init(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
if (dev->rfe_type != 50)
return;
/* HW reg. init to set mux & ctrler for antdiv */
halbb_antdiv_reg_init(bb);
/* Mode setting*/
bb_ant_div->antdiv_mode = AUTO_ANT;
bb_ant_div->pre_antdiv_mode = AUTO_ANT;
bb_ant_div->antdiv_method = EVM_BASED_ANTDIV;
bb_ant_div->tp_decision_method = TP_HIGHEST_DOMINATION;
bb_ant_div->evm_decision_method = EVM_LINEAR_AVG;
/* Algorithm parameter setting */
bb_ant_div->antdiv_period = ANTDIV_PERIOD;
bb_ant_div->antdiv_train_num = ANTDIV_TRAINING_NUM;
bb_ant_div->antdiv_delay = ANTDIV_DELAY;
bb_ant_div->antdiv_intvl = ANTDIV_INTVL;
bb_ant_div->tp_diff_th_high = ANTDIV_DEC_TP_HIGH;
bb_ant_div->tp_diff_th_low = ANTDIV_DEC_TP_LOW;
bb_ant_div->evm_diff_th = ANTDIV_DEC_EVM;
bb_ant_div->tp_lb = TP_LOWER_BOUND;
/* variable init */
bb_ant_div->antdiv_wd_cnt = 0;
bb_ant_div->antdiv_training_state_cnt = 0;
bb_ant_div->get_stats = false;
bb_ant_div->antdiv_use_ctrl_frame = true;
bb_ant_div->target_ant = ANTDIV_INIT;
bb_ant_div->target_ant_evm = ANTDIV_INIT;
bb_ant_div->target_ant_tp = ANTDIV_INIT;
bb_ant_div->training_ant = ANTDIV_INIT;
bb_ant_div->pre_target_ant = MAIN_ANT;
halbb_antdiv_reset(bb);
BB_DBG(bb, DBG_INIT, "Init ant_diversity timer");
}
void halbb_antdiv_deinit(struct bb_info *bb)
{
#if 0
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i;
struct bb_antdiv_rssi_info *bb_rssi_i = &bb_ant_div->bb_rssi_i;
struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i;
if (&bb_rate_i)
halbb_mem_free(bb, bb_rate_i, sizeof(struct bb_antdiv_rate_info));
if (&bb_cn_i)
halbb_mem_free(bb, bb_cn_i, sizeof(struct bb_antdiv_cn_info));
if (&bb_evm_i)
halbb_mem_free(bb, bb_evm_i, sizeof(struct bb_antdiv_evm_info));
if (&bb_rssi_i)
halbb_mem_free(bb, bb_rssi_i, sizeof(struct bb_antdiv_rssi_info));
#endif
}
void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i;
u8 band = bb->hal_com->band[0].cur_chandef.band;
u8 default_ant, optional_ant;
struct rtw_hal_com_t *hal = bb->hal_com;
if ((bb_ant_div->pre_target_ant != ant) || (bb_ant_div->training_ant != ant) ) {
BB_DBG(bb, DBG_ANT_DIV, "Set Antenna =%s\n",
(ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
if(ant == MAIN_ANT) {
default_ant = ANT1_2G;
optional_ant = ANT2_2G;
} else {
default_ant = ANT2_2G;
optional_ant = ANT1_2G;
}
/* Original Rx antenna */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0x20000, default_ant, HW_PHY_0);
halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0xf0, default_ant, HW_PHY_0);
/* Alternative Rx antenna */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0xf00, optional_ant, HW_PHY_0);
/* Tx antenna, same as orig. rx ant. */
halbb_set_reg_cmn(bb, cr->path0_r_antsel, 0xf000, default_ant, HW_PHY_0);
rtw_hal_rf_rx_ant(hal, ant);
} else {
BB_DBG(bb, DBG_ANT_DIV, "Stay in Ori-ant\n");
}
}
void halbb_antdiv_get_rssi(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_rssi_info *rssi = &bb_ant_div->bb_rssi_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
rssi->rssi_cck_avg = (u8)HALBB_DIV(rssi->rssi_cck_avg_acc, rssi->pkt_cnt_cck);
rssi->rssi_ofdm_avg = (u8)HALBB_DIV(rssi->rssi_ofdm_avg_acc, rssi->pkt_cnt_ofdm);
rssi->rssi_t_avg = (u8)HALBB_DIV(rssi->rssi_t_avg_acc, rssi->pkt_cnt_t);
if (rate_i->mode == BB_LEGACY_MODE) {
if (cmn_rpt->is_cck_rate) {
rssi->rssi_final = rssi->rssi_cck_avg;
} else {
rssi->rssi_final = rssi->rssi_ofdm_avg;
}
} else {
rssi->rssi_final = rssi->rssi_t_avg;
}
}
void halbb_antdiv_get_cn_target_ant(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
u32 main_cn, aux_cn;
u8 target_ant_cn;
/* CN */
main_cn = (u8)HALBB_DIV(bb_cn_i->main_cn_avg_acc, (bb_rate_i->main_pkt_cnt_t + bb_rate_i->main_pkt_cnt_ofdm));
aux_cn = (u8)HALBB_DIV(bb_cn_i->aux_cn_avg_acc, (bb_rate_i->aux_pkt_cnt_t+ bb_rate_i->aux_pkt_cnt_ofdm));
if (aux_cn == 0)
target_ant_cn = MAIN_ANT;
else if (main_cn == 0)
target_ant_cn = AUX_ANT;
else
target_ant_cn = (main_cn == aux_cn) ? (bb_ant_div->pre_target_ant) : ((main_cn >= aux_cn) ? AUX_ANT : MAIN_ANT);
BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Main-Ant CN_avg]",
(main_cn >> 1),
halbb_show_fraction_num(main_cn & 0x1, 1));
BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Aux-Ant CN_avg]",
(aux_cn >> 1),
halbb_show_fraction_num(aux_cn & 0x1, 1));
bb_ant_div->target_ant_cn = target_ant_cn;
BB_DBG(bb, DBG_ANT_DIV, "CN based TargetAnt= [%s]\n", (bb_ant_div->target_ant_cn == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
void halbb_antdiv_get_highest_mcs(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
u16 main_max_cnt = 0;
u16 aux_max_cnt = 0;
u16 main_max_idx = 0;
u16 aux_max_idx = 0;
u8 ss_ofst = 0;
u8 i;
BB_DBG(bb, DBG_ANT_DIV, "*Main-Ant CCK cnt:{%d, %d, %d, %d}\n",
bb_rate_i->main_pkt_cnt_legacy[0], bb_rate_i->main_pkt_cnt_legacy[1],
bb_rate_i->main_pkt_cnt_legacy[2], bb_rate_i->main_pkt_cnt_legacy[3]);
BB_DBG(bb, DBG_ANT_DIV, "*Aux-Ant CCK cnt:{%d, %d, %d, %d}\n",
bb_rate_i->aux_pkt_cnt_legacy[0], bb_rate_i->aux_pkt_cnt_legacy[1],
bb_rate_i->aux_pkt_cnt_legacy[2], bb_rate_i->aux_pkt_cnt_legacy[3]);
BB_DBG(bb, DBG_ANT_DIV, "*Main-Ant OFDM cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n",
bb_rate_i->main_pkt_cnt_legacy[4], bb_rate_i->main_pkt_cnt_legacy[5],
bb_rate_i->main_pkt_cnt_legacy[6], bb_rate_i->main_pkt_cnt_legacy[7],
bb_rate_i->main_pkt_cnt_legacy[8], bb_rate_i->main_pkt_cnt_legacy[9],
bb_rate_i->main_pkt_cnt_legacy[10], bb_rate_i->main_pkt_cnt_legacy[11]);
BB_DBG(bb, DBG_ANT_DIV, "*Aux-Ant OFDM cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n",
bb_rate_i->aux_pkt_cnt_legacy[4], bb_rate_i->aux_pkt_cnt_legacy[5],
bb_rate_i->aux_pkt_cnt_legacy[6], bb_rate_i->aux_pkt_cnt_legacy[7],
bb_rate_i->aux_pkt_cnt_legacy[8], bb_rate_i->aux_pkt_cnt_legacy[9],
bb_rate_i->aux_pkt_cnt_legacy[10], bb_rate_i->aux_pkt_cnt_legacy[11]);
if ((bb_rate_i->main_he_pkt_not_zero == true) || (bb_rate_i->aux_he_pkt_not_zero == true)) {
for (i = 0; i < HE_RATE_NUM; i++) {
if (bb_ant_div->tp_decision_method == TP_MAX_DOMINATION) {
if (bb_rate_i->main_pkt_cnt_he[i] >= main_max_cnt) {
main_max_cnt = bb_rate_i->main_pkt_cnt_he[i];
main_max_idx = i;
}
if (bb_rate_i->aux_pkt_cnt_he[i] >= aux_max_cnt) {
aux_max_cnt = bb_rate_i->aux_pkt_cnt_he[i];
aux_max_idx = i;
}
} else if (bb_ant_div->tp_decision_method == TP_HIGHEST_DOMINATION) {
if (bb_rate_i->main_pkt_cnt_he[i] > 0) {
main_max_cnt = bb_rate_i->main_pkt_cnt_he[i];
main_max_idx = i;
}
if (bb_rate_i->aux_pkt_cnt_he[i] > 0) {
aux_max_cnt = bb_rate_i->aux_pkt_cnt_he[i];
aux_max_idx = i;
}
}
}
for (i = 0; i < bb->num_rf_path; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
BB_DBG(bb, DBG_ANT_DIV,
"*Main-Ant HE %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
bb_rate_i->main_pkt_cnt_he[ss_ofst + 0],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 1],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 2],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 3],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 4],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 5],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 6],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 7],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 8],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 9],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 10],
bb_rate_i->main_pkt_cnt_he[ss_ofst + 11]);
BB_DBG(bb, DBG_ANT_DIV,
"*Aux-Ant HE %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 0],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 1],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 2],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 3],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 4],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 5],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 6],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 7],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 8],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 9],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 10],
bb_rate_i->aux_pkt_cnt_he[ss_ofst + 11]);
}
} else if ((bb_rate_i->main_vht_pkt_not_zero == true) || (bb_rate_i->aux_vht_pkt_not_zero == true)) {
for (i = 0; i < VHT_RATE_NUM; i++) {
if (bb_ant_div->tp_decision_method == TP_MAX_DOMINATION) {
if (bb_rate_i->main_pkt_cnt_vht[i] >= main_max_cnt) {
main_max_cnt = bb_rate_i->main_pkt_cnt_vht[i];
main_max_idx = i;
}
if (bb_rate_i->aux_pkt_cnt_vht[i] >= aux_max_cnt) {
aux_max_cnt = bb_rate_i->aux_pkt_cnt_vht[i];
aux_max_idx = i;
}
} else if (bb_ant_div->tp_decision_method == TP_HIGHEST_DOMINATION) {
if (bb_rate_i->main_pkt_cnt_vht[i] > 0) {
main_max_cnt = bb_rate_i->main_pkt_cnt_vht[i];
main_max_idx = i;
}
if (bb_rate_i->aux_pkt_cnt_vht[i] > 0) {
aux_max_cnt = bb_rate_i->aux_pkt_cnt_vht[i];
aux_max_idx = i;
}
}
}
for (i = 0; i < bb->num_rf_path; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
BB_DBG(bb, DBG_ANT_DIV,
"*Main-Ant VHT %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 0],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 1],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 2],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 3],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 4],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 5],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 6],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 7],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 8],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 9],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 10],
bb_rate_i->main_pkt_cnt_vht[ss_ofst + 11]);
BB_DBG(bb, DBG_ANT_DIV,
"*Aux-Ant VHT %d-SS cnt:{%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 0],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 1],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 2],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 3],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 4],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 5],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 6],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 7],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 8],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 9],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 10],
bb_rate_i->aux_pkt_cnt_vht[ss_ofst + 11]);
}
} else if ((bb_rate_i->main_ht_pkt_not_zero == true) || (bb_rate_i->aux_ht_pkt_not_zero == true)) {
for (i = 0; i < HT_RATE_NUM; i++) {
if (bb_ant_div->tp_decision_method == TP_MAX_DOMINATION) {
if (bb_rate_i->main_pkt_cnt_ht[i] >= main_max_cnt) {
main_max_cnt = bb_rate_i->main_pkt_cnt_ht[i];
main_max_idx = i;
}
if (bb_rate_i->aux_pkt_cnt_ht[i] >= aux_max_cnt) {
aux_max_cnt = bb_rate_i->aux_pkt_cnt_ht[i];
aux_max_idx = i;
}
} else if (bb_ant_div->tp_decision_method == TP_HIGHEST_DOMINATION) {
if (bb_rate_i->main_pkt_cnt_ht[i] > 0) {
main_max_cnt = bb_rate_i->main_pkt_cnt_ht[i];
main_max_idx = i;
}
if (bb_rate_i->aux_pkt_cnt_ht[i] > 0) {
aux_max_cnt = bb_rate_i->aux_pkt_cnt_ht[i];
aux_max_idx = i;
}
}
}
for (i = 0; i < bb->num_rf_path; i++) {
ss_ofst = (i << 3);
BB_DBG(bb, DBG_ANT_DIV,
"*HT%02d:%02d cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_ofst), (ss_ofst + 7),
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 0],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 1],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 2],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 3],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 4],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 5],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 6],
bb_rate_i->main_pkt_cnt_ht[ss_ofst + 7]);
BB_DBG(bb, DBG_ANT_DIV,
"*HT%02d:%02d cnt:{%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_ofst), (ss_ofst + 7),
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 0],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 1],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 2],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 3],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 4],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 5],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 6],
bb_rate_i->aux_pkt_cnt_ht[ss_ofst + 7]);
}
}
/* Compute all throughput*/
if (bb_ant_div->tp_decision_method == TP_AVG_DOMINATION) {
BB_DBG(bb, DBG_ANT_DIV, "Main_tp = %lld, Aux_tp = %lld\n",
bb_rate_i->main_tp, bb_rate_i->aux_tp);
if (bb_rate_i->main_tp > bb_rate_i->aux_tp) {
bb_ant_div->target_ant_tp = MAIN_ANT;
bb_rate_i->tp_diff = bb_rate_i->main_tp - bb_rate_i->aux_tp;
} else if (bb_rate_i->main_tp < bb_rate_i->aux_tp) {
bb_ant_div->target_ant_tp = AUX_ANT;
bb_rate_i->tp_diff = bb_rate_i->aux_tp - bb_rate_i->main_tp;
} else {
bb_ant_div->target_ant_tp = bb_ant_div->pre_target_ant;
bb_rate_i->no_change_flag = true;
BB_DBG(bb, DBG_ANT_DIV, "TP based TargetAnt= Pre-TargetAnt\n");
}
BB_DBG(bb, DBG_ANT_DIV, "MCS based TargetAnt= [%s]\n",
(bb_ant_div->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
BB_DBG(bb, DBG_ANT_DIV, "TP Confidence= [%lld]\n", bb_rate_i->tp_diff);
return;
}
bb_rate_i->main_max_cnt = main_max_cnt;
bb_rate_i->main_max_idx = main_max_idx;
bb_rate_i->aux_max_cnt = aux_max_cnt;
bb_rate_i->aux_max_idx = aux_max_idx;
/* Decision Tput based target ant using MCS rate instead of phy data rate */
if ((main_max_cnt > bb_ant_div->tp_lb) || (aux_max_cnt > bb_ant_div->tp_lb)) {
if (main_max_idx > aux_max_idx) {
bb_ant_div->target_ant_tp = MAIN_ANT;
bb_rate_i->tp_diff = 100;
} else if (main_max_idx < aux_max_idx) {
bb_ant_div->target_ant_tp = AUX_ANT;
bb_rate_i->tp_diff = 100;
} else {
if (main_max_cnt > aux_max_cnt)
bb_ant_div->target_ant_tp = MAIN_ANT;
else if (main_max_cnt < aux_max_cnt)
bb_ant_div->target_ant_tp = AUX_ANT;
else {
bb_ant_div->target_ant_tp = bb_ant_div->pre_target_ant;
bb_rate_i->no_change_flag = true;
}
/* Calc. TP confidence*/
bb_rate_i->tp_diff = DIFF_2(main_max_cnt, aux_max_cnt);
}
} else {
bb_ant_div->target_ant_tp = bb_ant_div->pre_target_ant;
bb_rate_i->no_change_flag = true;
BB_DBG(bb, DBG_ANT_DIV, "MCS based TargetAnt= Pre-TargetAnt\n");
}
if (bb_rate_i->no_change_flag == true)
bb_rate_i->tp_diff = 0;
if (bb_rate_i->tp_diff > 100)
bb_rate_i->tp_diff = 100;
BB_DBG(bb, DBG_ANT_DIV, "MCS based TargetAnt= [%s]\n",
(bb_ant_div->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
BB_DBG(bb, DBG_ANT_DIV, "TP Confidence= [%lld]\n", bb_rate_i->tp_diff);
}
void halbb_antdiv_get_evm_target_ant(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
u8 main_2ss_evm_min = 0;
u8 aux_2ss_evm_min = 0;
//u8 main_2ss_evm_avg, aux_2ss_evm_avg;
u8 main_1ss_evm = 0;
u8 aux_1ss_evm = 0;
u8 target_ant_evm_1ss, target_ant_evm_2ss;
u8 decision_evm_ss;
u8 evm_diff_1ss, evm_diff_2ss;
bool no_change_flag_1ss = false;
bool no_change_flag_2ss = false;
/* 1ss EVM */
if (bb_ant_div->evm_decision_method == EVM_LINEAR_AVG) {
/* Modify db to linear (*10)*/
bb_evm_i->main_evm_1ss = HALBB_DIV(bb_evm_i->main_evm_1ss, 10);
bb_evm_i->aux_evm_1ss = HALBB_DIV(bb_evm_i->aux_evm_1ss, 10);
main_1ss_evm = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->main_evm_1ss,
(u64)(bb_rate_i->main_pkt_cnt_1ss + bb_rate_i->main_pkt_cnt_ofdm)));
aux_1ss_evm = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->aux_evm_1ss,
(u64)(bb_rate_i->aux_pkt_cnt_1ss + bb_rate_i->aux_pkt_cnt_ofdm)));
main_1ss_evm = main_1ss_evm << 2;
aux_1ss_evm = aux_1ss_evm << 2;
} else {
main_1ss_evm = (u8)HALBB_DIV(bb_evm_i->main_evm_1ss,
(u64)(bb_rate_i->main_pkt_cnt_1ss + bb_rate_i->main_pkt_cnt_ofdm));
aux_1ss_evm = (u8)HALBB_DIV(bb_evm_i->aux_evm_1ss,
(u64)(bb_rate_i->aux_pkt_cnt_1ss + bb_rate_i->aux_pkt_cnt_ofdm));
}
target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ?
(bb_ant_div->pre_target_ant) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
if (main_1ss_evm == aux_1ss_evm) {
target_ant_evm_1ss = bb_ant_div->pre_target_ant;
no_change_flag_1ss = true;
} else if (main_1ss_evm > aux_1ss_evm) {
target_ant_evm_1ss = MAIN_ANT;
} else {
target_ant_evm_1ss = AUX_ANT;
}
/* Calc. EVM confindece*/
evm_diff_1ss = DIFF_2(main_1ss_evm, aux_1ss_evm);
BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Main-Ant 1ss-EVM_avg]",
(main_1ss_evm >> 2),
halbb_show_fraction_num(main_1ss_evm & 0x3, 2));
BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d)\n", "[Aux-Ant 1ss-EVM_avg]",
(aux_1ss_evm >> 2),
halbb_show_fraction_num(aux_1ss_evm & 0x3, 2));
/* 2ss EVM */
if ((bb_rate_i->main_pkt_cnt_2ss + bb_rate_i->aux_pkt_cnt_2ss) != 0) {
if (bb_ant_div->evm_decision_method == EVM_LINEAR_AVG) {
bb_evm_i->main_evm_min_acc = HALBB_DIV(bb_evm_i->main_evm_min_acc, 10);
bb_evm_i->aux_evm_min_acc = HALBB_DIV(bb_evm_i->aux_evm_min_acc, 10);
main_2ss_evm_min = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->main_evm_min_acc,
(u64)bb_rate_i->main_pkt_cnt_2ss));
aux_2ss_evm_min = (u8)halbb_convert_to_db(HALBB_DIV(bb_evm_i->aux_evm_min_acc,
(u64)bb_rate_i->aux_pkt_cnt_2ss));
main_2ss_evm_min = main_2ss_evm_min << 2;
aux_2ss_evm_min = aux_2ss_evm_min << 2;
} else {
main_2ss_evm_min = (u8)HALBB_DIV(bb_evm_i->main_evm_min_acc,
(u64)bb_rate_i->main_pkt_cnt_2ss);
aux_2ss_evm_min = (u8)HALBB_DIV(bb_evm_i->aux_evm_min_acc,
(u64)bb_rate_i->aux_pkt_cnt_2ss);
}
if (main_2ss_evm_min == aux_2ss_evm_min) {
target_ant_evm_2ss = bb_ant_div->pre_target_ant;
no_change_flag_2ss = true;
} else if (main_2ss_evm_min > aux_2ss_evm_min) {
target_ant_evm_2ss = MAIN_ANT;
} else {
target_ant_evm_2ss = AUX_ANT;
}
/* Calc. EVM confindece*/
evm_diff_2ss = DIFF_2(main_2ss_evm_min, aux_2ss_evm_min);
}
/*-----For Debug-----*/
BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d) (%d)\n", "[Main-Ant 2ss-EVM_avg]",
(main_2ss_evm_min >> 2),
halbb_show_fraction_num(main_2ss_evm_min & 0x3, 2),main_2ss_evm_min);
BB_DBG(bb, DBG_ANT_DIV, "%-9s (%02d.%03d) (%d)\n", "[Aux-Ant 2ss-EVM_avg]",
(aux_2ss_evm_min >> 2),
halbb_show_fraction_num(aux_2ss_evm_min & 0x3, 2), aux_2ss_evm_min);
/*-------------------*/
if ((bb_rate_i->main_pkt_cnt_2ss + bb_rate_i->aux_pkt_cnt_2ss) != 0) {
decision_evm_ss = 2;
bb_evm_i->evm_diff = evm_diff_2ss;
bb_ant_div->target_ant_evm = target_ant_evm_2ss;
bb_evm_i->no_change_flag = no_change_flag_2ss;
} else {
decision_evm_ss = 1;
bb_evm_i->evm_diff = evm_diff_1ss;
bb_ant_div->target_ant_evm = target_ant_evm_1ss;
bb_evm_i->no_change_flag = no_change_flag_1ss;
}
if (bb_evm_i->no_change_flag == true) {
bb_evm_i->evm_diff = 0;
BB_DBG(bb, DBG_ANT_DIV, "EVM based TargetAnt= Pre-TargetAnt\n");
}
if (bb_evm_i->evm_diff > 100)
bb_evm_i->evm_diff = 100;
BB_DBG(bb, DBG_ANT_DIV, "%d-ss EVM based TargetAnt= [%s]\n",
decision_evm_ss, (bb_ant_div->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
BB_DBG(bb, DBG_ANT_DIV, "EVM Confidence= [%d]\n", bb_evm_i->evm_diff);
}
void halbb_antdiv_training_state(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
u8 next_ant;
if (bb_ant_div->antdiv_training_state_cnt == 0) {
bb_ant_div->get_stats = false;
halbb_antdiv_reset_training_stat(bb);
bb_ant_div->training_ant = bb_ant_div->pre_target_ant;
next_ant = (bb_ant_div->training_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
BB_DBG(bb, DBG_ANT_DIV, "Next training ant =%s\n",
(next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
halbb_antdiv_set_ant(bb, next_ant);
bb_ant_div->training_ant = next_ant;
//bb_ant_div->pre_target_ant = next_ant;
bb_ant_div->antdiv_training_state_cnt++;
BB_DBG(bb, DBG_ANT_DIV, "%s Statistics Interval=%d ms\n",
((next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"), bb_ant_div->antdiv_intvl);
bb_ant_div->get_stats = true;
bb_ant_div->antdiv_timer_ms = bb_ant_div->antdiv_intvl;
halbb_antdiv_timers(bb, BB_SET_TIMER);
} else if ((bb_ant_div->antdiv_training_state_cnt % 2) == 0) {
bb_ant_div->antdiv_training_state_cnt++;
next_ant = bb_ant_div->training_ant;
BB_DBG(bb, DBG_ANT_DIV, "%s Statistics Interval=%d ms\n",
((next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"), bb_ant_div->antdiv_intvl);
bb_ant_div->get_stats = true;
bb_ant_div->antdiv_timer_ms = bb_ant_div->antdiv_intvl;
halbb_antdiv_timers(bb, BB_SET_TIMER);
} else if ((bb_ant_div->antdiv_training_state_cnt % 2) != 0) {
bb_ant_div->get_stats = false;
next_ant = (bb_ant_div->training_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
BB_DBG(bb, DBG_ANT_DIV, "Next training ant =%s\n",
(next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
halbb_antdiv_set_ant(bb, next_ant);
bb_ant_div->training_ant = next_ant;
bb_ant_div->antdiv_training_state_cnt++;
BB_DBG(bb, DBG_ANT_DIV, "%s Delay=%d ms\n",
((next_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"), bb_ant_div->antdiv_delay);
bb_ant_div->antdiv_timer_ms = bb_ant_div->antdiv_delay;
halbb_antdiv_timers(bb, BB_SET_TIMER);
}
}
void halbb_antdiv_decision_state(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i;
BB_DBG(bb, DBG_ANT_DIV, "[Decisoin state]\n");
bb_ant_div->get_stats = false;
bb_ant_div->antdiv_training_state_cnt = 0;
/* Check highest MCS idx of main & aux antenna*/
halbb_antdiv_get_highest_mcs(bb);
/* EVM based antenna diversity */
halbb_antdiv_get_evm_target_ant(bb);
/* Final Decision */
if ((bb_rate_i->main_cnt_all + bb_rate_i->aux_cnt_all) == 0) {
BB_DBG(bb, DBG_ANT_DIV, "Not enough count, remain previous antenna\n");
bb_ant_div->target_ant = bb_ant_div->pre_target_ant;
BB_DBG(bb, DBG_ANT_DIV, "Make decision again ASAP\n");
bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period;
return;
}
if (bb_rate_i->no_change_flag && bb_evm_i->no_change_flag) {
BB_DBG(bb, DBG_ANT_DIV, "No Decision, remain previous antenna\n");
bb_ant_div->target_ant = bb_ant_div->pre_target_ant;
BB_DBG(bb, DBG_ANT_DIV, "Make decision again ASAP\n");
bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period;
return;
}
if ((bb_ant_div->target_ant_evm == bb_ant_div->target_ant_tp) &&
(!bb_rate_i->no_change_flag) && (!bb_evm_i->no_change_flag)) {
BB_DBG(bb, DBG_ANT_DIV, "Decision confidence is enough\n");
bb_ant_div->target_ant = bb_ant_div->target_ant_evm;
} else {
if (bb_rate_i->tp_diff >= bb_ant_div->tp_diff_th_high) {
BB_DBG(bb, DBG_ANT_DIV, "TP confidence is %lld > %d, Decided by MCS based\n"
,bb_rate_i->tp_diff, bb_ant_div->tp_diff_th_low);
bb_ant_div->target_ant = bb_ant_div->target_ant_tp;
} else if (bb_evm_i->evm_diff >= bb_ant_div->evm_diff_th) {
BB_DBG(bb, DBG_ANT_DIV, "EVM confidence is more than %d, Decided by EVM based\n"
,bb_ant_div->evm_diff_th);
bb_ant_div->target_ant = bb_ant_div->target_ant_evm;
} else if (bb_rate_i->tp_diff >= bb_ant_div->tp_diff_th_low) {
BB_DBG(bb, DBG_ANT_DIV, "TP confidence is %lld > %d, Decided by MCS based\n"
,bb_rate_i->tp_diff, bb_ant_div->tp_diff_th_low);
bb_ant_div->target_ant = bb_ant_div->target_ant_tp;
} else {
BB_DBG(bb, DBG_ANT_DIV, "Decision confidence is not enough, remain previous antenna\n");
bb_ant_div->target_ant = bb_ant_div->pre_target_ant;
BB_DBG(bb, DBG_ANT_DIV, "Make decision again ASAP\n");
bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period;
}
}
BB_DBG(bb, DBG_ANT_DIV, "TargetAnt= [%s]\n", (bb_ant_div->target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
void halbb_evm_based_antdiv(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rssi_su_avg_info *avg = &cmn_rpt->bb_rssi_su_avg_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
/* Main function */
if (bb_ant_div->antdiv_training_state_cnt <= ((bb_ant_div->antdiv_train_num << 1) - 2)) {
BB_DBG(bb, DBG_ANT_DIV, "Ant_diversity training state = %d \n",
bb_ant_div->antdiv_training_state_cnt);
halbb_antdiv_training_state(bb);
return;
} else {
halbb_antdiv_decision_state(bb);
halbb_antdiv_reset_training_stat(bb);
}
/* Set new target antenna */
BB_DBG(bb, DBG_ANT_DIV, "Ant_diversity done\n");
halbb_antdiv_set_ant(bb, bb_ant_div->target_ant);
/* Re-assign to next step reqired variable */
bb_ant_div->target_ant_evm = bb_ant_div->target_ant;
bb_ant_div->target_ant_tp = bb_ant_div->target_ant;
bb_ant_div->target_ant_cn = bb_ant_div->target_ant;
bb_ant_div->pre_target_ant = bb_ant_div->target_ant;
}
void halbb_antenna_diversity(struct bb_info *bb)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_antdiv_rssi_info *rssi_stat = &bb_ant_div->bb_rssi_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
u8 rssi;
halbb_antdiv_get_rssi(bb);
rssi = rssi_stat->rssi_final;
BB_DBG(bb, DBG_ANT_DIV, "%s ======>\n", __func__);
/* Early return */
if(phl_is_mp_mode(bb->phl_com)) {
BB_DBG(bb, DBG_ANT_DIV, "Early return - MP mode\n");
return;
}
if (dev->rfe_type != 50)
return;
if (!(bb->support_ability & BB_ANT_DIV)) {
BB_DBG(bb, DBG_ANT_DIV, "Early return - Not support antenna diversity\n");
return;
}
if (!(bb_link->is_linked) && !(bb_link->is_one_entry_only)) {
BB_DBG(bb, DBG_ANT_DIV, "Early return - is_linked=%d, one_entry_only=%d\n",
bb_link->is_linked, bb_link->is_one_entry_only);
return;
}
if (rssi < ANTDIV_RSSI_TH_HIGH) {
BB_DBG(bb, DBG_ANT_DIV, "RSSI=%d is too low to do Ant_diveristy\n", rssi >> 1);
return;
}
if (bb_link->one_entry_tp_active_occur) { // if TP > th., do antdiv per watchdog
BB_DBG(bb, DBG_ANT_DIV, "TP occur, do antdv immediately\n");
bb_ant_div->antdiv_wd_cnt = bb_ant_div->antdiv_period;
}
if (bb_ant_div->antdiv_wd_cnt < bb_ant_div->antdiv_period) { // else, do antdiv after specific watchdog
BB_DBG(bb, DBG_ANT_DIV, "Ant-div period = %d, watchdog count = %d\n",
bb_ant_div->antdiv_period, bb_ant_div->antdiv_wd_cnt);
bb_ant_div->antdiv_wd_cnt++;
return;
} else {
bb_ant_div->antdiv_wd_cnt = 0;
}
/* Fixed-antenna diversity mode */
if (bb_ant_div->antdiv_mode != AUTO_ANT) {
BB_DBG(bb, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
(bb_ant_div->antdiv_mode == FIX_MAIN_ANT) ? "MAIN" : "AUX");
if (bb_ant_div->antdiv_mode != bb_ant_div->pre_antdiv_mode) {
if (bb_ant_div->antdiv_mode == FIX_MAIN_ANT) {
halbb_antdiv_set_ant(bb, MAIN_ANT);
}
else if (bb_ant_div->antdiv_mode == FIX_AUX_ANT) {
halbb_antdiv_set_ant(bb, AUX_ANT);
}
}
bb_ant_div->pre_antdiv_mode = bb_ant_div->antdiv_mode;
return;
}
/* Main section of EVM/TP based antenna diversity*/
BB_DBG(bb, DBG_ANT_DIV, "RSSI=%d, Ant_diversity start\n", rssi >> 1);
halbb_evm_based_antdiv(bb);
}
void halbb_antdiv_get_rssi_stat(struct bb_info *bb)
{
struct bb_physts_rslt_hdr_info *psts_h = &bb->bb_physts_i.bb_physts_rslt_hdr_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_rssi_info *rssi = &bb_ant_div->bb_rssi_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
u8 i = 0;
if (rate_i->mode == BB_LEGACY_MODE) {
if (cmn_rpt->is_cck_rate) {
rssi->rssi_cck_avg_acc += psts_h->rssi_avg;
rssi->pkt_cnt_cck++;
} else {
rssi->rssi_ofdm_avg_acc += psts_h->rssi_avg;
rssi->pkt_cnt_ofdm++;
}
} else {
rssi->rssi_t_avg_acc+= psts_h->rssi_avg;
rssi->pkt_cnt_t++;
}
}
void halbb_antdiv_get_evm_stat(struct bb_info *bb)
{
struct bb_physts_rslt_1_info *psts_1 = &bb->bb_physts_i.bb_physts_rslt_1_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_evm_info *bb_evm_i = &bb_ant_div->bb_evm_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
/* Only get stats @ training period */
if (!bb_ant_div->get_stats)
return;
/* No EVM info. @ cck rate */
if (cmn_rpt->is_cck_rate)
return;
if (bb_ant_div->evm_decision_method == EVM_LINEAR_AVG) {
if(bb_ant_div->training_ant == MAIN_ANT) {
if (rate_i->ss == 1) {
bb_evm_i->main_evm_1ss += halbb_db_2_linear((psts_1->evm_min >> 2));
} else {
bb_evm_i->main_evm_min_acc += halbb_db_2_linear((psts_1->evm_min>> 2));
bb_evm_i->main_evm_max_acc += halbb_db_2_linear((psts_1->evm_max >> 2));
}
} else if(bb_ant_div->training_ant == AUX_ANT) {
if (rate_i->ss == 1) {
bb_evm_i->aux_evm_1ss += halbb_db_2_linear((psts_1->evm_min >> 2));
} else {
bb_evm_i->aux_evm_min_acc += halbb_db_2_linear((psts_1->evm_min >> 2));
bb_evm_i->aux_evm_max_acc += halbb_db_2_linear((psts_1->evm_max >> 2));
}
}
} else {
if(bb_ant_div->training_ant == MAIN_ANT) {
if (rate_i->ss == 1) {
bb_evm_i->main_evm_1ss += psts_1->evm_min;
} else {
bb_evm_i->main_evm_min_acc += psts_1->evm_min;
bb_evm_i->main_evm_max_acc += psts_1->evm_max;
}
} else if(bb_ant_div->training_ant == AUX_ANT) {
if (rate_i->ss == 1) {
bb_evm_i->aux_evm_1ss += psts_1->evm_min;
} else {
bb_evm_i->aux_evm_min_acc += psts_1->evm_min;
bb_evm_i->aux_evm_max_acc += psts_1->evm_max;
}
}
}
}
void halbb_antdiv_get_cn_stat(struct bb_info *bb)
{
struct bb_physts_rslt_1_info *psts_1 = &bb->bb_physts_i.bb_physts_rslt_1_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_cn_info *bb_cn_i = &bb_ant_div->bb_cn_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
/* Only get stats @ training period */
if (!bb_ant_div->get_stats)
return;
/* Data frame only */
#if 0
if (bb_ant_div->antdiv_use_ctrl_frame) {
if (!bb_link->is_match_bssid)
return;
}
#endif
/* No CN info. @ cck rate */
if (cmn_rpt->is_cck_rate)
return;
if (rate_i->ss == 0)
return;
if(bb_ant_div->training_ant == MAIN_ANT) {
bb_cn_i->main_cn_avg_acc += psts_1->cn_avg;
} else if(bb_ant_div->training_ant == AUX_ANT) {
bb_cn_i->aux_cn_avg_acc += psts_1->cn_avg;
}
}
void halbb_antdiv_get_rate_stat(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
//struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_rate_info *bb_rate_i = &bb_ant_div->bb_rate_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
u8 ofst = rate_i->idx;
/* Only get stats @ training period */
if (!bb_ant_div->get_stats)
return;
/* Data frame only */
#if 0
if (bb_ant_div->antdiv_use_ctrl_frame) {
if (!bb_link->is_match_bssid)
return;
}
#endif
//BB_DBG(bb, DBG_ANT_DIV, "Rate mode= %d\n", rate_i->mode);
//BB_DBG(bb, DBG_ANT_DIV, "Training antenna= %d\n", bb_ant_div->training_ant);
if(bb_ant_div->training_ant == MAIN_ANT) {
/* pkt_cnt acc */
//BB_DBG(bb, DBG_ANT_DIV, "MAIN_ANT rate!\n");
bb_rate_i->main_cnt_all++;
if (rate_i->mode == BB_LEGACY_MODE) {
if (cmn_rpt->is_cck_rate)
bb_rate_i->main_pkt_cnt_cck++;
else
bb_rate_i->main_pkt_cnt_ofdm++;
} else {
bb_rate_i->main_pkt_cnt_t++;
if (rate_i->ss == 1)
bb_rate_i->main_pkt_cnt_1ss++;
else if (rate_i->ss == 2)
bb_rate_i->main_pkt_cnt_2ss++;
}
/* rate cnt acc*/
if (rate_i->mode == BB_LEGACY_MODE) {
bb_rate_i->main_pkt_cnt_legacy[ofst]++;
return;
}
if (rate_i->ss >= 2 && rate_i->mode >= BB_VHT_MODE)
ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1));
if (rate_i->mode == BB_HT_MODE) {
bb_rate_i->main_ht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HT_RATE_NUM - 1);
bb_rate_i->main_pkt_cnt_ht[ofst]++;
/* shift ofst due to mismatch of HT/VHT rate num*/
ofst += ((ofst << 3) >> 2);
bb_rate_i->main_tp +=
bb_phy_rate_table[ofst + LEGACY_RATE_NUM];
} else if (rate_i->mode == BB_VHT_MODE) {
bb_rate_i->main_vht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1);
bb_rate_i->main_pkt_cnt_vht[ofst]++;
bb_rate_i->main_tp +=
bb_phy_rate_table[ofst + LEGACY_RATE_NUM];
} else if (rate_i->mode == BB_HE_MODE) {
bb_rate_i->main_he_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1);
bb_rate_i->main_pkt_cnt_he[ofst]++;
bb_rate_i->main_tp +=
bb_phy_rate_table[ofst + LEGACY_RATE_NUM];
}
} else if(bb_ant_div->training_ant == AUX_ANT) {
bb_rate_i->aux_cnt_all++;
//BB_DBG(bb, DBG_ANT_DIV, "Aux_ANT rate!\n");
/* pkt_cnt acc */
if (rate_i->mode == BB_LEGACY_MODE) {
if (cmn_rpt->is_cck_rate)
bb_rate_i->aux_pkt_cnt_cck++;
else
bb_rate_i->aux_pkt_cnt_ofdm++;
} else {
bb_rate_i->aux_pkt_cnt_t++;
if (rate_i->ss == 1)
bb_rate_i->aux_pkt_cnt_1ss++;
else if (rate_i->ss == 2)
bb_rate_i->aux_pkt_cnt_2ss++;
}
if (rate_i->mode == BB_LEGACY_MODE) {
bb_rate_i->aux_pkt_cnt_legacy[ofst]++;
return;
}
if (rate_i->ss >= 2 && rate_i->mode >= BB_VHT_MODE)
ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1));
if (rate_i->mode == BB_HT_MODE) {
bb_rate_i->aux_ht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HT_RATE_NUM - 1);
bb_rate_i->aux_pkt_cnt_ht[ofst]++;
/* shift ofst due to mismatch of HT/VHT rate num*/
ofst += ((ofst >> 3) << 2);
bb_rate_i->aux_tp +=
bb_phy_rate_table[ofst + LEGACY_RATE_NUM];
} else if (rate_i->mode == BB_VHT_MODE) {
bb_rate_i->aux_vht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1);
bb_rate_i->aux_pkt_cnt_vht[ofst]++;
bb_rate_i->aux_tp +=
bb_phy_rate_table[ofst + LEGACY_RATE_NUM];
} else if (rate_i->mode == BB_HE_MODE) {
bb_rate_i->aux_he_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1);
bb_rate_i->aux_pkt_cnt_he[ofst]++;
bb_rate_i->aux_tp +=
bb_phy_rate_table[ofst + LEGACY_RATE_NUM];
}
}
}
void halbb_antdiv_phy_sts(struct bb_info *bb) {
halbb_antdiv_get_rssi_stat(bb);
halbb_antdiv_get_rate_stat(bb);
halbb_antdiv_get_evm_stat(bb);
halbb_antdiv_get_cn_stat(bb);
}
void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i;
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Antenna Diversity Mode: {1} {0}: Auto-mode {1}: Fix main ant. {2}: Fix aux ant.\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Antenna Diversity Method: {2} {0}: EVM based {1}: CN based\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set training period: {3} {num of watchdog} (How much watchdog to do one ant-div)\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set training state number: {4} {num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set training interval: {5} {ms} (how long for one training state)\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set training delay: {6} {ms} (how long to wait RA stable)\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set decision threshold: {7} {TP high th.} {TP low th.} {EVM th.}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"TP lower bound: {8} {th.}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"TP decision method: {9} {0}: Max cnt domination {1}: highest rate domination {2}: Avg. TP domination\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"EVM decision method: {10} {0}:Linear avg. {1}: dB avg.\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Show all parameter: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[ONLY DEBUG] {101} 0x586c[16]={0,1}\n");
} else {
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if (var[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->antdiv_mode = (u8)var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div Mode=%d\n", bb_ant_div->antdiv_mode);
if (bb_ant_div->antdiv_mode == FIX_MAIN_ANT) {
halbb_antdiv_set_ant(bb, MAIN_ANT);
bb_ant_div->pre_target_ant = MAIN_ANT;
} else if (bb_ant_div->antdiv_mode == FIX_AUX_ANT) {
halbb_antdiv_set_ant(bb, AUX_ANT);
bb_ant_div->pre_target_ant = AUX_ANT;
} else if (bb_ant_div->antdiv_mode == AUTO_ANT)
halbb_antdiv_set_ant(bb, bb_ant_div->pre_target_ant);
} else if (var[0] == 2) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->antdiv_method = var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training method=%d\n", bb_ant_div->antdiv_method);
} else if (var[0] == 3) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->antdiv_period = (u8)var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div period=%d watchdog\n", bb_ant_div->antdiv_period);
} else if (var[0] == 4) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->antdiv_train_num = var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training state num=%d\n", bb_ant_div->antdiv_train_num);
} else if (var[0] == 5) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->antdiv_intvl = var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training interval=%d\n", bb_ant_div->antdiv_intvl);
} else if (var[0] == 6) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->antdiv_delay = var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training delay=%d\n", bb_ant_div->antdiv_delay);
} else if (var[0] == 7) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]);
bb_ant_div->tp_diff_th_high = (u16)var[1];
bb_ant_div->tp_diff_th_low = (u16)var[2];
bb_ant_div->evm_diff_th = (u8)var[3];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Decision threshold: {TP high = %d} {TP low = %d} {EVM = %d}\n",
bb_ant_div->tp_diff_th_high,
bb_ant_div->tp_diff_th_low,
bb_ant_div->evm_diff_th);
} else if (var[0] == 8) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->tp_lb = (u8)var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"TP lower bound=%d\n", bb_ant_div->tp_lb);
} else if (var[0] == 9) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->tp_decision_method = (u8)var[1];
BB_DBG(bb, DBG_ANT_DIV, "TP decision method=(( %d ))\n",
bb_ant_div->tp_decision_method);
} else if (var[0] == 10) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_ant_div->evm_decision_method = (u8)var[1];
BB_DBG(bb, DBG_ANT_DIV, "EVM decision method=(( %d ))\n",
bb_ant_div->evm_decision_method);
} else if (var[0] == 100) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div Mode = {%d}\n", bb_ant_div->antdiv_mode);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training method = {%d}\n", bb_ant_div->antdiv_method);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"TP decision method = {%d}\n", bb_ant_div->tp_decision_method);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"EVM decision method = {%d}\n", bb_ant_div->evm_decision_method);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div period = {#%d-watchdog}\n", bb_ant_div->antdiv_period);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training state num = {%d}\n", bb_ant_div->antdiv_train_num);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training interval = {%d}\n", bb_ant_div->antdiv_intvl);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Ant-Div training delay = {%d}\n", bb_ant_div->antdiv_delay);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Decision threshold: {TP high = %d} {TP low = %d} {EVM = %d}\n",
bb_ant_div->tp_diff_th_high,
bb_ant_div->tp_diff_th_low,
bb_ant_div->evm_diff_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"TP lower bound = {%d}\n", bb_ant_div->tp_lb);
} else if (var[0] == 101) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
halbb_set_reg_cmn(bb, cr->path0_r_antsel, BIT(16), var[1], HW_PHY_0);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[ONLY DEBUG] 0x1586c[16] = %d\n", var[1]);
}
}
*_used = used;
*_out_len = out_len;
}
void halbb_antdiv_callback(void *context)
{
struct bb_info *bb = (struct bb_info *)context;
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
halbb_evm_based_antdiv(bb);
}
void halbb_antdiv_timers(struct bb_info *bb, enum bb_timer_cfg_t bb_antdiv_timer_state)
{
struct bb_antdiv_info *bb_ant_div = &bb->bb_ant_div_i;
u8 state = bb_antdiv_timer_state;
if (state == BB_SET_TIMER) {
halbb_set_timer(bb, &bb->antdiv_timer, bb_ant_div->antdiv_timer_ms);
} else if (state == BB_INIT_TIMER) {
halbb_init_timer(bb, &bb->antdiv_timer, halbb_antdiv_callback, bb, "halbb_antdiv_timers");
} else if (state == BB_CANCEL_TIMER) {
halbb_cancel_timer(bb, &bb->antdiv_timer);
} else if (state == BB_RELEASE_TIMER) {
halbb_release_timer(bb, &bb->antdiv_timer);
}
}
void halbb_cr_cfg_antdiv_init(struct bb_info *bb)
{
struct bb_antdiv_cr_info *cr = &bb->bb_ant_div_i.bb_antdiv_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_52AA:
cr->path0_r_ant_train_en = PATH0_R_ANT_TRAIN_EN_52AA;
cr->path0_r_ant_train_en_m = PATH0_R_ANT_TRAIN_EN_52AA_M;
cr->path0_r_tx_ant_sel = PATH0_R_TX_ANT_SEL_52AA;
cr->path0_r_tx_ant_sel_m = PATH0_R_TX_ANT_SEL_52AA_M;
cr->path0_r_rfe_buf_en = PATH0_R_RFE_BUF_EN_52AA;
cr->path0_r_rfe_buf_en_m = PATH0_R_RFE_BUF_EN_52AA_M;
cr->path0_r_lnaon_agc = PATH0_R_LNAON_AGC_52AA;
cr->path0_r_lnaon_agc_m = PATH0_R_LNAON_AGC_52AA_M;
cr->path0_r_trsw_bit_bt = PATH0_R_TRSW_BIT_BT_52AA;
cr->path0_r_trsw_bit_bt_m = PATH0_R_TRSW_BIT_BT_52AA_M;
cr->path0_r_trsw_s = PATH0_R_TRSW_S_52AA;
cr->path0_r_trsw_s_m = PATH0_R_TRSW_S_52AA_M;
cr->path0_r_trsw_o = PATH0_R_TRSW_O_52AA;
cr->path0_r_trsw_o_m = PATH0_R_TRSW_O_52AA_M;
cr->path0_r_trswb_o = PATH0_R_TRSWB_O_52AA;
cr->path0_r_trswb_o_m = PATH0_R_TRSWB_O_52AA_M;
cr->path0_r_bt_force_antidx = PATH0_R_BT_FORCE_ANTIDX_52AA;
cr->path0_r_bt_force_antidx_m = PATH0_R_BT_FORCE_ANTIDX_52AA_M;
cr->path0_r_bt_force_antidx_en = PATH0_R_BT_FORCE_ANTIDX_EN_52AA;
cr->path0_r_bt_force_antidx_en_m = PATH0_R_BT_FORCE_ANTIDX_EN_52AA_M;
cr->path0_r_ant_module_rfe_opt = PATH0_R_ANT_MODULE_RFE_OPT_52AA;
cr->path0_r_ant_module_rfe_opt_m = PATH0_R_ANT_MODULE_RFE_OPT_52AA_M;
cr->path0_r_rfsw_tr = PATH0_R_RFSW_TR_52AA;
cr->path0_r_rfsw_tr_m = PATH0_R_RFSW_TR_52AA_M;
cr->path0_r_antsel = PATH0_R_ANTSEL_52AA;
cr->path0_r_antsel_m = PATH0_R_ANTSEL_52AA_M;
cr->path0_r_rfsw_ant_31_0 = PATH0_R_RFSW_ANT_31_0__52AA;
cr->path0_r_rfsw_ant_31_0_m = PATH0_R_RFSW_ANT_31_0__52AA_M;
cr->path0_r_rfsw_ant_63_32 = PATH0_R_RFSW_ANT_63_32__52AA;
cr->path0_r_rfsw_ant_63_32_m = PATH0_R_RFSW_ANT_63_32__52AA_M;
cr->path0_r_rfsw_ant_95_64 = PATH0_R_RFSW_ANT_95_64__52AA;
cr->path0_r_rfsw_ant_95_64_m = PATH0_R_RFSW_ANT_95_64__52AA_M;
cr->path0_r_rfsw_ant_127_96 = PATH0_R_RFSW_ANT_127_96__52AA;
cr->path0_r_rfsw_ant_127_96_m = PATH0_R_RFSW_ANT_127_96__52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->path0_r_ant_train_en = PATH0_R_ANT_TRAIN_EN_A;
cr->path0_r_ant_train_en_m = PATH0_R_ANT_TRAIN_EN_A_M;
cr->path0_r_tx_ant_sel = PATH0_R_TX_ANT_SEL_A;
cr->path0_r_tx_ant_sel_m = PATH0_R_TX_ANT_SEL_A_M;
cr->path0_r_rfe_buf_en = PATH0_R_RFE_BUF_EN_A;
cr->path0_r_rfe_buf_en_m = PATH0_R_RFE_BUF_EN_A_M;
cr->path0_r_lnaon_agc = PATH0_R_LNAON_AGC_A;
cr->path0_r_lnaon_agc_m = PATH0_R_LNAON_AGC_A_M;
cr->path0_r_trsw_bit_bt = PATH0_R_TRSW_BIT_BT_A;
cr->path0_r_trsw_bit_bt_m = PATH0_R_TRSW_BIT_BT_A_M;
cr->path0_r_trsw_s = PATH0_R_TRSW_S_A;
cr->path0_r_trsw_s_m = PATH0_R_TRSW_S_A_M;
cr->path0_r_trsw_o = PATH0_R_TRSW_O_A;
cr->path0_r_trsw_o_m = PATH0_R_TRSW_O_A_M;
cr->path0_r_trswb_o = PATH0_R_TRSWB_O_A;
cr->path0_r_trswb_o_m = PATH0_R_TRSWB_O_A_M;
cr->path0_r_bt_force_antidx = PATH0_R_BT_FORCE_ANTIDX_A;
cr->path0_r_bt_force_antidx_m = PATH0_R_BT_FORCE_ANTIDX_A_M;
cr->path0_r_bt_force_antidx_en = PATH0_R_BT_FORCE_ANTIDX_EN_A;
cr->path0_r_bt_force_antidx_en_m = PATH0_R_BT_FORCE_ANTIDX_EN_A_M;
cr->path0_r_ant_module_rfe_opt = PATH0_R_ANT_MODULE_RFE_OPT_A;
cr->path0_r_ant_module_rfe_opt_m = PATH0_R_ANT_MODULE_RFE_OPT_A_M;
cr->path0_r_rfsw_tr = PATH0_R_RFSW_TR_A;
cr->path0_r_rfsw_tr_m = PATH0_R_RFSW_TR_A_M;
cr->path0_r_antsel = PATH0_R_ANTSEL_A;
cr->path0_r_antsel_m = PATH0_R_ANTSEL_A_M;
cr->path0_r_rfsw_ant_31_0 = PATH0_R_RFSW_ANT_31_0__A;
cr->path0_r_rfsw_ant_31_0_m = PATH0_R_RFSW_ANT_31_0__A_M;
cr->path0_r_rfsw_ant_63_32 = PATH0_R_RFSW_ANT_63_32__A;
cr->path0_r_rfsw_ant_63_32_m = PATH0_R_RFSW_ANT_63_32__A_M;
cr->path0_r_rfsw_ant_95_64 = PATH0_R_RFSW_ANT_95_64__A;
cr->path0_r_rfsw_ant_95_64_m = PATH0_R_RFSW_ANT_95_64__A_M;
cr->path0_r_rfsw_ant_127_96 = PATH0_R_RFSW_ANT_127_96__A;
cr->path0_r_rfsw_ant_127_96_m = PATH0_R_RFSW_ANT_127_96__A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->path0_r_ant_train_en = PATH0_R_ANT_TRAIN_EN_C;
cr->path0_r_ant_train_en_m = PATH0_R_ANT_TRAIN_EN_C_M;
cr->path0_r_tx_ant_sel = PATH0_R_TX_ANT_SEL_C;
cr->path0_r_tx_ant_sel_m = PATH0_R_TX_ANT_SEL_C_M;
cr->path0_r_rfe_buf_en = PATH0_R_RFE_BUF_EN_C;
cr->path0_r_rfe_buf_en_m = PATH0_R_RFE_BUF_EN_C_M;
cr->path0_r_lnaon_agc = PATH0_R_LNAON_AGC_C;
cr->path0_r_lnaon_agc_m = PATH0_R_LNAON_AGC_C_M;
cr->path0_r_trsw_bit_bt = PATH0_R_TRSW_BIT_BT_C;
cr->path0_r_trsw_bit_bt_m = PATH0_R_TRSW_BIT_BT_C_M;
cr->path0_r_trsw_s = PATH0_R_TRSW_S_C;
cr->path0_r_trsw_s_m = PATH0_R_TRSW_S_C_M;
cr->path0_r_trsw_o = PATH0_R_TRSW_O_C;
cr->path0_r_trsw_o_m = PATH0_R_TRSW_O_C_M;
cr->path0_r_trswb_o = PATH0_R_TRSWB_O_C;
cr->path0_r_trswb_o_m = PATH0_R_TRSWB_O_C_M;
cr->path0_r_bt_force_antidx = PATH0_R_BT_FORCE_ANTIDX_C;
cr->path0_r_bt_force_antidx_m = PATH0_R_BT_FORCE_ANTIDX_C_M;
cr->path0_r_bt_force_antidx_en = PATH0_R_BT_FORCE_ANTIDX_EN_C;
cr->path0_r_bt_force_antidx_en_m = PATH0_R_BT_FORCE_ANTIDX_EN_C_M;
cr->path0_r_ant_module_rfe_opt = PATH0_R_ANT_MODULE_RFE_OPT_C;
cr->path0_r_ant_module_rfe_opt_m = PATH0_R_ANT_MODULE_RFE_OPT_C_M;
cr->path0_r_rfsw_tr = PATH0_R_RFSW_TR_C;
cr->path0_r_rfsw_tr_m = PATH0_R_RFSW_TR_C_M;
cr->path0_r_antsel = PATH0_R_ANTSEL_C;
cr->path0_r_antsel_m = PATH0_R_ANTSEL_C_M;
cr->path0_r_rfsw_ant_31_0 = PATH0_R_RFSW_ANT_31_0__C;
cr->path0_r_rfsw_ant_31_0_m = PATH0_R_RFSW_ANT_31_0__C_M;
cr->path0_r_rfsw_ant_63_32 = PATH0_R_RFSW_ANT_63_32__C;
cr->path0_r_rfsw_ant_63_32_m = PATH0_R_RFSW_ANT_63_32__C_M;
cr->path0_r_rfsw_ant_95_64 = PATH0_R_RFSW_ANT_95_64__C;
cr->path0_r_rfsw_ant_95_64_m = PATH0_R_RFSW_ANT_95_64__C_M;
cr->path0_r_rfsw_ant_127_96 = PATH0_R_RFSW_ANT_127_96__C;
cr->path0_r_rfsw_ant_127_96_m = PATH0_R_RFSW_ANT_127_96__C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ant_div.c
|
C
|
agpl-3.0
| 53,370
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ANT_DIV_H__
#define __HALBB_ANT_DIV_H__
/*@--------------------------[Define] ---------------------------------------*/
#define EVM_BASED_ANTDIV 0
#define CN_BASED_ANTDIV 1
#define TP_MAX_DOMINATION 0
#define TP_HIGHEST_DOMINATION 1
#define TP_AVG_DOMINATION 2
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 /*@ant A or ant Main or S1*/
#define AUX_ANT 2 /*@AntB or ant Aux or S0*/
#define MAX_ANT 3 /* @3 for AP using*/
#define ANT1_2G 0
/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT2_2G 1
/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANTDIV_MAX_STA_NUM PHL_MAX_STA_NUM
#define ANTDIV_RSSI_TH_HIGH 25
#define ANTDIV_RSSI_TH_LOW 20
#define ANTDIV_PERIOD 1
#define ANTDIV_TRAINING_NUM 6
#define FORCE_RSSI_DIFF 10
#define ANTDIV_DELAY 1
#define ANTDIV_INTVL 10
#define ANTDIV_DEC_TP_HIGH 100
#define ANTDIV_DEC_TP_LOW 5
#define ANTDIV_DEC_EVM 4
#define TP_LOWER_BOUND 1
/* @Antenna Diversty Control type */
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define ANT_PATH_A 0
#define ANT_PATH_B 1
#define ANT_PATH_AB 2
/*@--------------------------[Enum]------------------------------------------*/
enum bb_antdiv_mode_t {
AUTO_ANT = 0,
FIX_MAIN_ANT = 1,
FIX_AUX_ANT = 2,
};
enum bb_tp_method_t {
TP_MAX = 0,
TP_HIGHEST = 1,
TP_AVG = 2,
};
enum bb_evm_method_t {
EVM_LINEAR_AVG = 0,
EVM_DB_AVG = 1,
};
enum bb_antdiv_method_t {
EVM_BASED = 0,
CN_BASED = 1,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_antdiv_rssi_info { /*all in U(8,1)*/
/*acc value*/
u32 rssi_cck_avg_acc;
u32 rssi_ofdm_avg_acc;
u32 rssi_t_avg_acc;
u8 rssi_cck_avg;
u8 rssi_ofdm_avg;
u8 rssi_t_avg;
u8 rssi_final;
u16 pkt_cnt_t;
u16 pkt_cnt_cck;
u16 pkt_cnt_ofdm;
};
struct bb_antdiv_cn_info {
u32 main_cn_avg_acc; /*U(7,1)*/
u32 aux_cn_avg_acc; /*U(7,1)*/
};
struct bb_antdiv_evm_info {
u64 main_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
u64 main_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
u64 main_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
u64 aux_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
u64 aux_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
u64 aux_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
u8 evm_diff;
bool no_change_flag;
};
struct bb_antdiv_rate_info {
/*====[Phy rate counter main ant]=============================================*/
u16 main_pkt_cnt_cck;
u16 main_pkt_cnt_ofdm; /*L-OFDM*/
u16 main_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 main_pkt_cnt_1ss; /*HT, VHT, HE*/
u16 main_pkt_cnt_2ss; /*HT, VHT, HE*/
/*Legacy*/
u16 main_pkt_cnt_legacy[LEGACY_RATE_NUM];
/*HT*/
u16 main_pkt_cnt_ht[HT_RATE_NUM];
/*VHT*/
u16 main_pkt_cnt_vht[VHT_RATE_NUM];
/*HE*/
u16 main_pkt_cnt_he[HE_RATE_NUM];
u16 main_max_cnt;
u16 main_max_idx;
/*====[Phy rate counter] aux ant=============================================*/
u16 aux_pkt_cnt_cck;
u16 aux_pkt_cnt_ofdm; /*L-OFDM*/
u16 aux_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 aux_pkt_cnt_1ss; /*HT, VHT, HE*/
u16 aux_pkt_cnt_2ss; /*HT, VHT, HE*/
/*Legacy*/
u16 aux_pkt_cnt_legacy[LEGACY_RATE_NUM];
/*HT*/
u16 aux_pkt_cnt_ht[HT_RATE_NUM];
/*VHT*/
u16 aux_pkt_cnt_vht[VHT_RATE_NUM];
/*HE*/
u16 aux_pkt_cnt_he[HE_RATE_NUM];
u16 aux_max_cnt;
u16 aux_max_idx;
u16 main_cnt_all;
u16 aux_cnt_all;
u64 main_tp;
u64 aux_tp;
u64 tp_diff;
bool no_change_flag;
bool main_ht_pkt_not_zero;
bool main_vht_pkt_not_zero;
bool main_he_pkt_not_zero;
bool aux_ht_pkt_not_zero;
bool aux_vht_pkt_not_zero;
bool aux_he_pkt_not_zero;
};
struct bb_antdiv_cr_info {
u32 path0_r_ant_train_en;
u32 path0_r_ant_train_en_m;
u32 path0_r_tx_ant_sel;
u32 path0_r_tx_ant_sel_m;
u32 path0_r_rfe_buf_en;
u32 path0_r_rfe_buf_en_m;
u32 path0_r_lnaon_agc;
u32 path0_r_lnaon_agc_m;
u32 path0_r_trsw_bit_bt;
u32 path0_r_trsw_bit_bt_m;
u32 path0_r_trsw_s;
u32 path0_r_trsw_s_m;
u32 path0_r_trsw_o;
u32 path0_r_trsw_o_m;
u32 path0_r_trswb_o;
u32 path0_r_trswb_o_m;
u32 path0_r_bt_force_antidx;
u32 path0_r_bt_force_antidx_m;
u32 path0_r_bt_force_antidx_en;
u32 path0_r_bt_force_antidx_en_m;
u32 path0_r_ant_module_rfe_opt;
u32 path0_r_ant_module_rfe_opt_m;
u32 path0_r_rfsw_tr;
u32 path0_r_rfsw_tr_m;
u32 path0_r_antsel;
u32 path0_r_antsel_m;
u32 path0_r_rfsw_ant_31_0;
u32 path0_r_rfsw_ant_31_0_m;
u32 path0_r_rfsw_ant_63_32;
u32 path0_r_rfsw_ant_63_32_m;
u32 path0_r_rfsw_ant_95_64;
u32 path0_r_rfsw_ant_95_64_m;
u32 path0_r_rfsw_ant_127_96;
u32 path0_r_rfsw_ant_127_96_m;
};
struct bb_antdiv_info {
struct bb_antdiv_cr_info bb_antdiv_cr_i;
/* For CN cacluation */
struct bb_antdiv_cn_info bb_cn_i;
/* For EVM cacluation */
struct bb_antdiv_evm_info bb_evm_i;
/* For MCS cacluation */
struct bb_antdiv_rate_info bb_rate_i;
/* For RSSI */
struct bb_antdiv_rssi_info bb_rssi_i;
enum bb_antdiv_mode_t antdiv_mode;
enum bb_antdiv_method_t antdiv_method;
enum bb_antdiv_mode_t pre_antdiv_mode;
enum bb_timer_cfg_t bb_antdiv_timer_state;
enum bb_tp_method_t tp_decision_method;
enum bb_evm_method_t evm_decision_method;
/* Training state & period related*/
u8 antdiv_wd_cnt;
u8 antdiv_training_state_cnt;
u32 antdiv_intvl;
u32 antdiv_timer_ms;
u32 antdiv_delay;
u32 antdiv_train_num;
u8 antdiv_period;
u8 tp_lb;
/* antenna setting */
u8 pre_target_ant;
u8 training_ant;
u8 target_ant;
u8 target_ant_cn;
u8 target_ant_evm;
u8 target_ant_tp;
/* Decision*/
u16 tp_diff_th_high;
u16 tp_diff_th_low;
u8 evm_diff_th;
/*Phy-sts related */
bool get_stats;
bool antdiv_use_ctrl_frame;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_antdiv_timers(struct bb_info *bb, enum bb_timer_cfg_t bb_antdiv_timer_state);
void halbb_cr_cfg_antdiv_init(struct bb_info *bb);
void halbb_antdiv_reg_init(struct bb_info *bb);
void halbb_antdiv_deinit(struct bb_info *bb);
void halbb_antdiv_init(struct bb_info *bb);
void halbb_antdiv_reset(struct bb_info *bb);
void halbb_antdiv_reset_training_stat(struct bb_info *bb);
void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant);
void halbb_antdiv_get_highest_mcs(struct bb_info *bb);
void halbb_antdiv_get_evm_target_ant(struct bb_info *bb);
void halbb_antdiv_training_state(struct bb_info *bb);
void halbb_antdiv_decision_state(struct bb_info *bb);
void halbb_evm_based_antdiv(struct bb_info *bb);
void halbb_antenna_diversity(struct bb_info *bb);
void halbb_antdiv_phy_sts(struct bb_info *bb);
void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ant_div.h
|
C
|
agpl-3.0
| 7,802
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halbb_precomp.h"
void halbb_dyn_1r_cca_en(struct bb_info *bb, bool en)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_dyn_1r_cca_en_8852a_2(bb, en);
break;
#endif
default:
break;
}
}
u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx)
{
struct rtw_hw_band *hw_band = &bb->hal_com->band[phy_idx];
u8 pause_result = 0;
u32 val[5] = {0};
char val_char = '0';
BB_DBG(bb, DBG_DIG, "[%s] event=%d\n", __func__, event);
if (event == MSG_EVT_SCAN_START || event == MSG_EVT_CONNECT_START) {
val[0] = 90;
if (hw_band->cur_chandef.band == BAND_ON_24G)
val[1] = PAUSE_OFDM_CCK;
else
val[1] = PAUSE_OFDM;
pause_result = halbb_pause_func(bb, F_DIG, HALBB_PAUSE, HALBB_PAUSE_LV_2, 2, val);
halbb_edcca_event_nofity(bb, HALBB_PAUSE);
} else if (event == MSG_EVT_SCAN_END) {
pause_result = halbb_pause_func(bb, F_DIG, HALBB_RESUME, HALBB_PAUSE_LV_2, 2, val);
halbb_edcca_event_nofity(bb, HALBB_RESUME);
} else if (event == MSG_EVT_CONNECT_END) {
pause_result = halbb_pause_func(bb, F_DIG, HALBB_RESUME_NO_RECOVERY, HALBB_PAUSE_LV_2, 2, val);
halbb_edcca_event_nofity(bb, HALBB_RESUME_NO_RECOVERY);
halbb_dig_new_entry_connect(bb);
} else if (event == MSG_EVT_DBG_RX_DUMP || event == MSG_EVT_DBG_TX_DUMP) {
halbb_dump_bb_reg(bb, &val[0], &val_char, &val[0], false);
halbb_dump_bb_reg(bb, &val[0], &val_char, &val[0], false);
}
return pause_result;
}
#ifdef BB_8852B_SUPPORT
bool halbb_rf_sw_si_test(struct bb_info *bb, enum rf_path rx_path, u8 reg_addr, int ch_idx)
{
u32 channel_change[3] = {0x1, 0x24, 0x99};
u32 ofdm_rx = 0x0, reg_value_0 = 0x0, reg_value_1 = 0x0;
ofdm_rx = (u32)rx_path;
ch_idx = ch_idx % 3;
if (ofdm_rx == RF_PATH_A) {
halbb_write_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff, channel_change[ch_idx]);
reg_value_0 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff);
BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_0);
if (reg_value_0 == channel_change[ch_idx]){
return true;
} else {
return false;
}
} else if (ofdm_rx == RF_PATH_B) {
halbb_write_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff, channel_change[ch_idx]);
reg_value_1 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff);
BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_1);
if (reg_value_1 == channel_change[ch_idx]){
return true;
} else {
return false;
}
} else {
halbb_write_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff, channel_change[ch_idx]);
halbb_write_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff, channel_change[ch_idx]);
reg_value_0 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_A, reg_addr, 0x3ff);
reg_value_1 = halbb_read_rf_reg_8852b_a(bb, RF_PATH_B, reg_addr, 0x3ff);
BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_0);
BB_DBG(bb, DBG_PHY_CONFIG, "read_value (%d) = %x\n", ofdm_rx, reg_value_1);
if ((reg_value_0 == channel_change[ch_idx]) && (reg_value_1 == channel_change[ch_idx])) {
return true;
} else {
return false;
}
}
}
#endif
u16 halbb_get_csi_buf_idx(struct bb_info *bb, u8 buf_idx, u8 txsc_idx)
{
u8 table_size = 0;
u8 i;
u8 txsc_2_buf_idx_160[][2] = {{0, 0}, //BW all
{8, 1}, //20M
{6, 3},
{4, 2},
{2, 4},
{1, 5},
{3, 7},
{5, 6},
{7, 8},
{12, 9}, //40M
{10, 10},
{9, 11},
{11, 12},
{14, 13}, //80M
{13, 14}};
u8 txsc_2_buf_idx_080[][2] = {{0, 0}, //BW all
{4, 1}, //20M
{2, 3},
{1, 2},
{3, 4},
{10, 9}, //40M
{9, 10}};
u8 csi_sub_idx = 0xff;
u16 rpt_val = 0;
if (bb->ic_type & BB_IC_MAX_BW_160) {
table_size = sizeof(txsc_2_buf_idx_160) / (sizeof(u8) * 2);
for (i = 0; i < table_size; i++) {
if (txsc_2_buf_idx_160[i][0] == txsc_idx) {
csi_sub_idx = txsc_2_buf_idx_160[i][1];
break;
}
}
} else {
table_size = sizeof(txsc_2_buf_idx_080) / (sizeof(u8) * 2);
for (i = 0; i < table_size; i++) {
if (txsc_2_buf_idx_080[i][0] == txsc_idx) {
csi_sub_idx = txsc_2_buf_idx_080[i][1];
break;
}
}
}
BB_DBG(bb, DBG_DBG_API, "%02d -> %02d\n", txsc_idx, csi_sub_idx);
if (csi_sub_idx == 0xff) {
rpt_val = 0xff;
} else {
rpt_val = (buf_idx << 6) | (csi_sub_idx << 2);
}
return rpt_val;
}
u16 halbb_cfg_cmac_tx_ant(struct bb_info *bb, enum rf_path tx_path)
{
u16 val = 0;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
val = halbb_cfg_cmac_tx_ant_8852a(bb, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
val = halbb_cfg_cmac_tx_ant_8852a_2(bb, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
val = halbb_cfg_cmac_tx_ant_8852b(bb, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
val = halbb_cfg_cmac_tx_ant_8852c(bb, tx_path);
break;
#endif
default:
break;
}
return val;
}
void halbb_gpio_ctrl_dump(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_gpio_ctrl_dump_8852a(bb);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_gpio_ctrl_dump_8852a_2(bb);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
//halbb_gpio_ctrl_dump_8852b(bb);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_gpio_ctrl_dump_8852c(bb);
break;
#endif
default:
break;
}
}
void halbb_gpio_rfm(struct bb_info *bb, enum bb_path path,
enum bb_rfe_src_sel src, bool dis_tx_gnt_wl,
bool active_tx_opt, bool act_bt_en, u8 rfm_output_val)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_gpio_rfm_8852a(bb, path, src, dis_tx_gnt_wl, active_tx_opt,
act_bt_en, rfm_output_val);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_gpio_rfm_8852a_2(bb, path, src, dis_tx_gnt_wl, active_tx_opt,
act_bt_en, rfm_output_val);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_gpio_rfm_8852c(bb, path, src, dis_tx_gnt_wl, active_tx_opt,
act_bt_en, rfm_output_val);
break;
#endif
default:
break;
}
}
void halbb_gpio_trsw_table(struct bb_info *bb, enum bb_path path,
bool path_en, bool trsw_tx, bool trsw_rx,
bool trsw, bool trsw_b)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_gpio_trsw_table_8852a(bb, path, path_en, trsw_tx, trsw_rx,
trsw, trsw_b);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_gpio_trsw_table_8852a_2(bb, path, path_en, trsw_tx,
trsw_rx, trsw, trsw_b);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_gpio_trsw_table_8852c(bb, path, path_en, trsw_tx,
trsw_rx, trsw, trsw_b);
break;
#endif
default:
break;
}
}
void halbb_gpio_setting_all(struct bb_info *bb, u8 rfe_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_gpio_setting_init_8852a(bb);
halbb_gpio_setting_all_8852a(bb, rfe_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_gpio_setting_init_8852a_2(bb);
halbb_gpio_setting_all_8852a_2(bb, rfe_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_gpio_setting_init_8852c(bb);
halbb_gpio_setting_all_8852c(bb, rfe_idx);
break;
#endif
default:
break;
}
}
void halbb_gpio_setting(struct bb_info *bb, u8 gpio_idx, enum bb_path path,
bool inv, enum bb_rfe_src_sel src)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_gpio_setting_8852a(bb, gpio_idx, path, inv, src);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_gpio_setting_8852a_2(bb, gpio_idx, path, inv, src);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_gpio_setting_8852c(bb, gpio_idx, path, inv, src);
break;
#endif
default:
break;
}
}
void halbb_gpio_setting_init(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_gpio_setting_init_8852a(bb);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_gpio_setting_init_8852a_2(bb);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_gpio_setting_init_8852c(bb);
break;
#endif
default:
break;
}
}
void halbb_pre_agc_en(struct bb_info *bb, bool enable)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_pre_agc_en_8852a(bb, enable);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_pre_agc_en_8852a_2(bb, enable);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_pre_agc_en_8852b(bb, enable);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_pre_agc_en_8852c(bb, enable);
break;
#endif
default:
break;
}
}
void halbb_set_gain_error(struct bb_info *bb, u8 central_ch)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_set_gain_error_8852a_2(bb, central_ch);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_set_gain_error_8852b(bb, central_ch);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_set_gain_error_8852c(bb, central_ch);
break;
#endif
default:
break;
}
}
u8 halbb_stop_ic_trx(struct bb_info *bb, u8 set_type)
{
struct rtw_hal_com_t *hal_i = bb->hal_com;
u8 i = 0;
bool trx_idle_success = false;
u32 dp = 0;
if (set_type == HALBB_SET) {
/*[Stop TRX]---------------------------------------------------------*/
if (bb->ic_type & BB_IC_AX_SERIES) {
/*set debug port to 0x0*/
if (!halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
return HALBB_SET_FAIL;
}
halbb_set_bb_dbg_port_ip(bb, DBGPORT_IP_TD);
halbb_set_bb_dbg_port(bb, 0x205);
for (i = 0; i < 100; i++) {
dp = halbb_get_bb_dbg_port_val(bb);
/* CCA_all && mux_state*/
if ((dp & 0x80000f00) == 0) {
BB_DBG(bb, DBG_DBG_API, "Stop trx wait for (%d) times\n", i);
trx_idle_success = true;
break;
}
halbb_delay_ms(bb, 1);
}
halbb_release_bb_dbg_port(bb);
}
if (trx_idle_success) {
/*pause all TX queue*/
rtw_hal_tx_pause(hal_i, 0, true, PAUSE_RSON_PSD);
rtw_hal_tx_pause(hal_i, 1, true, PAUSE_RSON_PSD);
halbb_ctrl_rx_cca(bb, false, HW_PHY_0);
halbb_ctrl_rx_cca(bb, false, HW_PHY_1);
} else {
return HALBB_SET_FAIL;
}
return HALBB_SET_SUCCESS;
} else { /*@if (set_type == HALBB_REVERT)*/
/*Release all TX queue*/
rtw_hal_tx_pause(hal_i, 0, false, PAUSE_RSON_PSD);
rtw_hal_tx_pause(hal_i, 1, false, PAUSE_RSON_PSD);
halbb_ctrl_rx_cca(bb, true, HW_PHY_0);
halbb_ctrl_rx_cca(bb, true, HW_PHY_1);
return HALBB_SET_SUCCESS;
}
}
u8 halbb_get_txsc(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width cbw, enum channel_width dbw)
{
u8 txsc_idx = 0;
u8 tmp = 0;
u8 ofst = 0;
if ((cbw == dbw) || (cbw == CHANNEL_WIDTH_20)) {
txsc_idx = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "[TXSC] TxSC_idx = %d\n", txsc_idx);
return txsc_idx;
}
switch (cbw) {
case CHANNEL_WIDTH_40:
txsc_idx = pri_ch > central_ch ? 1 : 2;
break;
case CHANNEL_WIDTH_80:
if (dbw == CHANNEL_WIDTH_20) {
if (pri_ch > central_ch)
txsc_idx = (pri_ch - central_ch) >> 1;
else
txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
} else {
txsc_idx = pri_ch > central_ch ? 9 : 10;
}
break;
case CHANNEL_WIDTH_160:
if (pri_ch > central_ch)
tmp = (pri_ch - central_ch) >> 1;
else
tmp = ((central_ch - pri_ch) >> 1) + 1;
if (dbw == CHANNEL_WIDTH_20) {
txsc_idx = tmp;
} else if (dbw == CHANNEL_WIDTH_40) {
if ((tmp == 1) || (tmp == 3))
txsc_idx = 9;
else if ((tmp == 5) || (tmp == 7))
txsc_idx = 11;
else if ((tmp == 2) || (tmp == 4))
txsc_idx = 10;
else if ((tmp == 6) || (tmp == 8))
txsc_idx = 12;
else
return 0xff;
} else {
txsc_idx = pri_ch > central_ch ? 13 : 14;
}
break;
case CHANNEL_WIDTH_80_80:
if (dbw == CHANNEL_WIDTH_20) {
if (pri_ch > central_ch)
txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
else
txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
} else if (dbw == CHANNEL_WIDTH_40) {
txsc_idx = pri_ch > central_ch ? 10 : 12;
} else {
txsc_idx = 14;
}
default:
break;
}
BB_DBG(bb, DBG_PHY_CONFIG, "[TXSC] TxSC_idx = %d\n", txsc_idx);
return txsc_idx;
}
void halbb_reset_adc(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_adc_rst_8852a(bb);
break;
#endif
default:
break;
}
}
void halbb_reset_bb_phy(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_bb_reset_8852a(bb);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_bb_reset_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_bb_reset_8852b(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_bb_reset_8852c(bb, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_reset_bb(struct bb_info *bb)
{
halbb_reset_bb_phy(bb, HW_PHY_0);
if (bb->hal_com->dbcc_en)
halbb_reset_bb_phy(bb, HW_PHY_1);
}
void halbb_tssi_bb_reset(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_tssi_bb_reset_8852a(bb);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_tssi_bb_reset_8852a_2(bb);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_tssi_bb_reset_8852c(bb);
break;
#endif
default:
break;
}
}
u32 halbb_read_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask)
{
u32 val = 0;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
val = halbb_read_rf_reg_8852a(bb, path, addr, mask);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
val = halbb_read_rf_reg_8852a_2(bb, path, addr, mask);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
val = halbb_read_rf_reg_8852b(bb, path, addr, mask);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
val = halbb_read_rf_reg_8852c(bb, path, addr, mask);
break;
#endif
default:
val = 0;
break;
}
return val;
}
bool halbb_write_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask,
u32 data)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_write_rf_reg_8852a(bb, path, addr, mask, data);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_write_rf_reg_8852a_2(bb, path, addr, mask, data);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_write_rf_reg_8852b(bb, path, addr, mask, data);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_write_rf_reg_8852c(bb, path, addr, mask, data);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_rf_set_bb_reg(struct bb_info *bb, u32 addr, u32 mask, u32 data)
{
bool rpt = false;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_rf_write_bb_reg_8852a_2(bb, addr, mask, data);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_rf_write_bb_reg_8852b(bb, addr, mask, data);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_rf_write_bb_reg_8852c(bb, addr, mask, data);
break;
#endif
default:
break;
}
if (bb->bb_dbg_i.cr_recorder_rf_en)
BB_TRACE("[RF][W] 0x%04x[0x%08x] = 0x%08x\n", addr, mask, data);
if (!rpt)
BB_WARNING("[%s][IQK]error IO 0x%x\n", __func__, addr);
return rpt;
}
u32 halbb_rf_get_bb_reg(struct bb_info *bb, u32 addr, u32 mask)
{
u32 val = 0;
val = halbb_get_reg(bb, addr, mask);
if (bb->bb_dbg_i.cr_recorder_rf_en)
BB_TRACE("[RF][R] 0x%04x[0x%08x] = 0x%08x\n", addr, mask, val);
return val;
}
void halbb_dfs_en(struct bb_info *bb, bool en)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_dfs_en_8852a_2(bb, en);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
//halbb_dfs_en_8852b(bb, en);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_dfs_en_8852c(bb, en);
break;
#endif
default:
break;
}
}
void halbb_adc_en(struct bb_info *bb, bool en)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_adc_en_8852a_2(bb, en);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_adc_en_8852b(bb, en);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_adc_en_8852c(bb, en);
break;
#endif
default:
break;
}
}
void halbb_tssi_cont_en(struct bb_info *bb, bool en, enum rf_path path)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_tssi_cont_en_8852a_2(bb, en, path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_tssi_cont_en_8852b(bb, en, path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_tssi_cont_en_8852c(bb, en, path);
break;
#endif
default:
break;
}
}
void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_bb_reset_en_8852a_2(bb, en, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_bb_reset_en_8852b(bb, en, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_bb_reset_en_8852a_2(bb, en, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_ctrl_rf_mode(struct bb_info *bb, enum phl_rf_mode mode)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ctrl_rf_mode_8852a(bb, mode);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_rf_mode_8852a_2(bb, mode);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_rf_mode_8852b(bb, mode);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_rf_mode_8852c(bb, mode);
break;
#endif
default:
break;
}
}
bool halbb_ctrl_rx_path(struct bb_info *bb, enum rf_path rx_path)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_ctrl_rx_path_8852a(bb, rx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_ctrl_rx_path_8852a_2(bb, rx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_ctrl_rx_path_8852b(bb, rx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_ctrl_rx_path_8852c(bb, rx_path);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_ctrl_tx_path(struct bb_info *bb, enum rf_path tx_path)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_ctrl_tx_path_8852a(bb, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_ctrl_tx_path_8852a_2(bb, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_ctrl_tx_path_8852b(bb, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_ctrl_tx_path_8852c(bb, tx_path);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
void halbb_ctrl_trx_path(struct bb_info *bb, enum rf_path tx_path, u8 tx_nss,
enum rf_path rx_path, u8 rx_nss)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ctrl_trx_path_8852a(bb, tx_path, tx_nss, rx_path, rx_nss);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_trx_path_8852a_2(bb, tx_path, tx_nss, rx_path, rx_nss);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_trx_path_8852b(bb, tx_path, tx_nss, rx_path, rx_nss);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_trx_path_8852c(bb, tx_path, tx_nss, rx_path, rx_nss);
break;
#endif
default:
break;
}
}
bool halbb_ctrl_bw(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx)
{
bool rpt = true;
struct bb_api_info *bb_api = &bb->bb_api_i;
bb_api->pri_ch_idx = pri_ch;
bb_api->bw = bw;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_ctrl_bw_8852a(bb, pri_ch, bw, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_ctrl_bw_8852a_2(bb, pri_ch, bw, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_ctrl_bw_8852b(bb, pri_ch, bw, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_ctrl_bw_8852c(bb, pri_ch, bw, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_ctrl_ch(struct bb_info *bb, u8 central_ch, enum band_type band,
enum phl_phy_idx phy_idx)
{
bool rpt = true;
struct bb_api_info *bb_api = &bb->bb_api_i;
bb_api->central_ch = central_ch;
bb_api->band = band;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_ctrl_ch_8852a(bb, central_ch, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_ctrl_ch_8852a_2(bb, central_ch, band, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_ctrl_ch_8852b(bb, central_ch, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_ctrl_ch_8852c(bb, central_ch, band, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_ctrl_ch2_80p80(struct bb_info *bb, u8 central_ch)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_ctrl_ch2_80p80_8852a(bb, central_ch);
break;
#endif
#if 0//def BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_ctrl_ch2_80p80_8852a_2(bb, central_ch);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_ctrl_bw_ch(struct bb_info *bb, u8 pri_ch, u8 central_ch_seg0,
u8 central_ch_seg1, enum band_type band,
enum channel_width bw, enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_ctrl_bw_ch_8852a(bb, pri_ch, central_ch_seg0, bw,
phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
#ifdef HALBB_FW_OFLD_SUPPORT
if (halbb_check_fw_ofld(bb)) {
BB_WARNING("Do FW offload at Channel switch\n");
rpt = halbb_fwofld_bw_ch_8852a_2(bb, pri_ch, central_ch_seg0,
bw, phy_idx);
}
else
rpt = halbb_ctrl_bw_ch_8852a_2(bb, pri_ch,
central_ch_seg0, bw,
band, phy_idx);
#else
rpt = halbb_ctrl_bw_ch_8852a_2(bb, pri_ch, central_ch_seg0, bw,
band, phy_idx);
#endif
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_ctrl_bw_ch_8852b(bb, pri_ch, central_ch_seg0, bw,
band, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_ctrl_bw_ch_8852c(bb, pri_ch, central_ch_seg0, bw,
band, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
void halbb_ctrl_dbcc(struct bb_info *bb, bool dbcc_enable)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ctrl_dbcc_8852a(bb, dbcc_enable);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_dbcc_8852a_2(bb, dbcc_enable);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_dbcc_8852c(bb, dbcc_enable);
break;
#endif
default:
break;
}
}
void halbb_cfg_dbcc(struct bb_info *bb, bool dbcc_enable)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_cfg_dbcc_8852a(bb, dbcc_enable);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_cfg_dbcc_8852a_2(bb, dbcc_enable);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_cfg_dbcc_8852c(bb, dbcc_enable);
break;
#endif
default:
break;
}
}
void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ctrl_rx_cca_8852a(bb, cca_en, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_rx_cca_8852a_2(bb, cca_en, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_rx_cca_8852b(bb, cca_en, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_rx_cca_8852c(bb, cca_en, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_ctrl_cck_en(struct bb_info *bb, bool cck_enable,
enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ctrl_cck_en_8852a(bb, cck_enable, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_cck_en_8852a_2(bb, cck_enable, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_cck_en_8852b(bb, cck_enable, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_cck_en_8852c(bb, cck_enable, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_ctrl_ofdm_en(struct bb_info *bb, bool ofdm_enable,
enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ctrl_ofdm_en_8852a(bb, ofdm_enable, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_ofdm_en_8852a_2(bb, ofdm_enable, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_ofdm_en_8852b(bb, ofdm_enable, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_ofdm_en_8852c(bb, ofdm_enable, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_ctrl_btg(struct bb_info *bb, bool btg)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_btg_8852a_2(bb, btg);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_btg_8852b(bb, btg);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_btg_8852c(bb, btg);
break;
#endif
default:
break;
}
}
void halbb_ctrl_btc_preagc(struct bb_info *bb, bool bt_en)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ctrl_btc_preagc_8852a_2(bb, bt_en);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ctrl_btc_preagc_8852b(bb, bt_en);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ctrl_btc_preagc_8852c(bb, bt_en);
break;
#endif
default:
break;
}
}
void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_pop_en_8852a_2(bb, en, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_pop_en_8852b(bb, en, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_pop_en_8852c(bb, en, phy_idx);
break;
#endif
default:
break;
}
}
bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_querry_pop_en_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_querry_pop_en_8852b(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_querry_pop_en_8852c(bb, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_set_pd_lower_bound(struct bb_info *bb, u8 bound,
enum channel_width bw, enum phl_phy_idx phy_idx)
{
bool rpt = true;
struct bb_api_info *bb_api = &bb->bb_api_i;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_pd_lower_bound_8852a_2(bb, bound, bw, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_pd_lower_bound_8852b(bb, bound, bw, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_pd_lower_bound_8852c(bb, bound, bw, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_set_pd_lower_bound_cck(struct bb_info *bb, u8 bound,
enum channel_width bw, enum phl_phy_idx phy_idx)
{
bool rpt = true;
struct bb_api_info *bb_api = &bb->bb_api_i;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_pd_lower_bound_cck_8852a_2(bb, bound, bw, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_pd_lower_bound_cck_8852b(bb, bound, bw, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_pd_lower_bound_cck_8852c(bb, bound, bw, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
u8 halbb_querry_pd_lower_bound(struct bb_info *bb, bool get_en_info,
enum phl_phy_idx phy_idx)
{
u8 rpt = 0;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_querry_pd_lower_bound_8852a_2(bb, get_en_info, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_querry_pd_lower_bound_8852b(bb, get_en_info, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_querry_pd_lower_bound_8852c(bb, get_en_info, phy_idx);
break;
#endif
default:
rpt = 0;
break;
}
return rpt;
}
u8 halbb_get_losel(struct bb_info *bb)
{
u8 rpt = 0xff;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_losel_8852a_2(bb);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_losel_8852c(bb);
break;
#endif
default:
rpt = 0xff;
break;
}
return rpt;
}
void halbb_set_igi(struct bb_info *bb, u8 lna_idx, bool tia_idx, u8 rxbb_idx,
enum rf_path path)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_set_igi_8852a(bb, lna_idx, tia_idx, rxbb_idx, path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_set_igi_8852a_2(bb, lna_idx, tia_idx, rxbb_idx, path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_set_igi_8852b(bb, lna_idx, tia_idx, rxbb_idx, path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_set_igi_8852c(bb, lna_idx, tia_idx, rxbb_idx, path);
break;
#endif
default:
break;
}
}
void halbb_set_tx_pow_pattern_shap(struct bb_info *bb, u8 ch,
bool is_ofdm, enum phl_phy_idx phy_idx) {
struct rtw_tpu_info *tpu = &bb->hal_com->band[phy_idx].rtw_tpu_i;
u8 shape_idx = tpu->tx_ptrn_shap_idx;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
if (is_ofdm)
halbb_tx_triangular_shap_cfg_8852a_2(bb, shape_idx, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
if (is_ofdm)
halbb_tx_triangular_shap_cfg_8852b(bb, shape_idx, phy_idx);
else
halbb_tx_dfir_shap_cck_8852b(bb, ch, shape_idx, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
if (is_ofdm)
halbb_tx_triangular_shap_cfg_8852c(bb, shape_idx, phy_idx);
//else
// halbb_tx_dfir_shap_cck_8852c(bb, ch, shape_idx, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_set_tx_pow_ref(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
struct rtw_tpu_info *tpu = &bb->hal_com->band[phy_idx].rtw_tpu_i;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rtw_hal_mac_write_pwr_ref_reg(bb->hal_com, (enum phl_band_idx)phy_idx);
halbb_set_tx_pow_ref_8852a_2(bb, tpu->ref_pow_ofdm,
tpu->ref_pow_cck,
tpu->ofst_int,
tpu->base_cw_0db,
tpu->tssi_16dBm_cw,
&tpu->ref_pow_ofdm_cw,
&tpu->ref_pow_cck_cw,
phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rtw_hal_mac_write_pwr_ref_reg(bb->hal_com, (enum phl_band_idx)phy_idx);
halbb_set_tx_pow_ref_8852b(bb, tpu->ref_pow_ofdm,
tpu->ref_pow_cck,
tpu->ofst_int,
tpu->base_cw_0db,
tpu->tssi_16dBm_cw,
&tpu->ref_pow_ofdm_cw,
&tpu->ref_pow_cck_cw,
phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rtw_hal_mac_write_pwr_ref_reg(bb->hal_com, (enum phl_band_idx)phy_idx);
halbb_set_tx_pow_ref_8852c(bb, tpu->ref_pow_ofdm,
tpu->ref_pow_cck,
tpu->ofst_int,
tpu->base_cw_0db,
tpu->tssi_16dBm_cw,
&tpu->ref_pow_ofdm_cw,
&tpu->ref_pow_cck_cw,
phy_idx);
break;
#endif
default:
break;
}
}
void halbb_normal_efuse_verify(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path, enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_normal_efuse_verify_8852a_2(bb, rx_gain_offset, rx_path, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_normal_efuse_verify_8852b(bb, rx_gain_offset, rx_path, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_normal_efuse_verify_8852c(bb, rx_gain_offset, rx_path, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_normal_efuse_verify_cck(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_normal_efuse_verify_cck_8852a_2(bb, rx_gain_offset,
rx_path, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_normal_efuse_verify_cck_8852b(bb, rx_gain_offset,
rx_path, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_normal_efuse_verify_cck_8852c(bb, rx_gain_offset,
rx_path, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_rx_setting(struct bb_info *bb, u8 patch_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_rx_setting_8852a(bb, patch_idx);
break;
#endif
#if 0//def BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_rx_setting_8852b(bb, patch_idx)
break;
#endif
#if 0//def BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_rx_setting_8852c(bb, patch_idx)
break;
#endif
default:
break;
}
}
void halbb_ic_hw_setting_non_io(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
#ifdef BB_DYN_1R_CCA
bb->bb_8852a_2_i.dyn_1r_cca_cfg = RF_PATH_ABCD;
#endif
break;
#endif
default:
break;
}
}
void halbb_ic_hw_setting_low_io(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
#ifdef BB_DYN_1R_CCA
bb->bb_8852a_2_i.dyn_1r_cca_cfg = RF_PATH_ABCD;
#endif
break;
#endif
default:
break;
}
}
void halbb_ic_hw_setting(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ic_hw_setting_8852a_2(bb);
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
halbb_dyn_csi_rsp_main(bb);
#endif
#ifdef BB_DYN_1R_CCA
halbb_dyn_1r_cca_8852a_2(bb);
#endif
#ifdef BB_DYN_CFO_TRK_LOP
halbb_dyn_cfo_trk_loop(bb);
#endif
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
//halbb_ic_hw_setting_8852b(bb);
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
halbb_dyn_csi_rsp_main(bb);
#endif
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ic_hw_setting_8852c(bb);
break;
#endif
default:
break;
}
}
void halbb_ic_hw_setting_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len)
{
u32 val[5] = {0};
u8 i = 0, j = 0;
enum rf_path cca_path;
#ifdef BB_DYN_CFO_TRK_LOP
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i;
#endif
if (_os_strcmp(input[1], "-h") == 0) {
#ifdef BB_DYN_1R_CCA
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"1r_cca en {0/1}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"1r_cca force {1:A, 2:B, 3:AB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"1r_cca diff_th {val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"1r_cca min_th {val}\n");
#endif
#ifdef BB_DYN_CFO_TRK_LOP
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_trk en {0/1}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_trk force {0:SNR, 1:link}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_trk para {0:SNR, 1:link} {data_val} {pilot_val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_trk snr_th {th_l} {th_h}\n");
#endif
return;
}
#ifdef BB_DYN_CFO_TRK_LOP
if (_os_strcmp(input[1], "cfo_trk") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[2], "en") == 0) {
halbb_dyn_cfo_trk_loop_en(bb, (bool)val[0]);
} else if (_os_strcmp(input[2], "force") == 0) {
halbb_dyn_cfo_trk_loop_en(bb, false);
if (val[0] == 0)
halbb_cfo_trk_loop_cr_cfg(bb, DCTL_SNR);
else if (val[0] == 1)
halbb_cfo_trk_loop_cr_cfg(bb, DCTL_LINK);
else
return;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Force state=%d\n", val[0]);
} else if (_os_strcmp(input[2], "para") == 0) {
HALBB_SCAN(input[4], DCMD_HEX, &val[1]);
HALBB_SCAN(input[5], DCMD_HEX, &val[2]);
if (val[0] >= 2)
return;
dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_data = (u8)val[1];
dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_pilot = (u8)val[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"state:%d, dctl_data=0x%x, dctl_pilot=0x%x\n", val[0],
dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_data,
dctl->bb_cfo_trk_lop_cr_i[val[0]].dctl_pilot);
} else if (_os_strcmp(input[2], "snr_th") == 0) {
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
dctl->dctl_snr_th_l = (u16)val[0] << RSSI_MA_H;
dctl->dctl_snr_th_h = (u16)val[1] << RSSI_MA_H;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dctl_snr_th_{l/h}={%d/%d}\n",
val[0], val[1]);
}
} else
#endif
#ifdef BB_DYN_1R_CCA
if (_os_strcmp(input[1], "1r_cca") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[2], "en") == 0) {
halbb_dyn_1r_cca_en_8852a_2(bb, (bool)val[0]);
} else if (_os_strcmp(input[2], "force") == 0) {
halbb_dyn_1r_cca_en_8852a_2(bb, false);
if (val[0] == 1)
cca_path = RF_PATH_A;
else if (val[0] == 2)
cca_path = RF_PATH_B;
else if (val[0] == 3)
cca_path = RF_PATH_AB;
else
return;
halbb_dyn_1r_cca_cfg_8852a_2(bb, cca_path);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Force cca_path=%d\n", cca_path);
} else if (_os_strcmp(input[2], "diff_th") == 0) {
bb->bb_8852a_2_i.dyn_1r_cca_rssi_diff_th= (u16)(val[0] << 5);
} else if (_os_strcmp(input[2], "min_th") == 0) {
bb->bb_8852a_2_i.dyn_1r_cca_rssi_min_th= (u16)(val[0] << 5);
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Dyn 1R CCA]en=%d, diff_th=%d, min_th=%d\n",
bb->bb_8852a_2_i.dyn_1r_cca_en,
bb->bb_8852a_2_i.dyn_1r_cca_rssi_diff_th >> 5,
bb->bb_8852a_2_i.dyn_1r_cca_rssi_min_th >> 5);
} else
#endif
{
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
}
}
void halbb_ic_api_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 tmp = 0, i = 0;
u32 j = 0;
#ifdef BB_8852B_SUPPORT
bool judge_f;
#endif
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"trx_path {tx_path} {tx_nss} {rx_path} {rx_nss}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"igi ({lna_idx (0~6)} {tia_idx (0~1)} {rxbb_idx (0~31)} {path (0~1)})\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Rx_setting({patch_idx (0:default, 1:patch-1, 2:patch-2)})\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rfe dump\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rfe all {rfe_idx}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rfe cmn {gpio_idx} {path} {inv} {src}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rfe rfm {path} {src} {dis_tx} {ac_tx} {ac_bt} {val}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rfe trsw {path} {path_en} {trsw_tx} {trsw_rx} {trsw} {trsw_b}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rf sw_si rw {run_idx} {rx_path} {reg_addr}\n");
} else if (_os_strcmp(input[1], "trx_path") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]);
halbb_ctrl_trx_path(bb, (enum rf_path)val[0], (u8)val[1],
(enum rf_path)val[2], (u8)val[3]);
} else if (_os_strcmp(input[1], "igi") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]);
if (val[0] > 6) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Invalid LNA index!\n");
} else if (val[1] > 1) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Invalid TIA index!\n");
} else if (val[2] > 31) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Invalid RxBB index!\n");
} else {
halbb_set_igi(bb, (u8)val[0], (bool)val[1], (u8)val[2],
(enum rf_path)val[3]);
}
} else if (_os_strcmp(input[1], "rx_setting") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
if (val[0] > 2) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Invalid Patch index!\n");
return;
}
halbb_rx_setting(bb, (u8)val[0]);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Rx setting Patch-%d Success!\n", val[0]);
} else if (_os_strcmp(input[1], "rfe") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[6], DCMD_DECIMAL, &val[3]);
HALBB_SCAN(input[7], DCMD_DECIMAL, &val[4]);
HALBB_SCAN(input[8], DCMD_DECIMAL, &val[5]);
if (_os_strcmp(input[2], "dump") == 0) {
halbb_gpio_ctrl_dump(bb);
} else if (_os_strcmp(input[2], "all") == 0) {
//HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
halbb_gpio_setting_all(bb, (u8)val[0]);
} else if (_os_strcmp(input[2], "trsw") == 0) {
halbb_gpio_trsw_table(bb, (enum bb_path)val[0],
(bool)val[1], (bool)val[2],
(bool)val[3], (bool)val[4],
(bool)val[5]);
} else if (_os_strcmp(input[2], "rfm") == 0) {
halbb_gpio_rfm(bb, (enum bb_path)val[0],
(enum bb_rfe_src_sel)val[1], (bool)val[2],
(bool)val[3], (bool)val[4], (u8)val[5]);
} else if (_os_strcmp(input[2], "cmn") == 0) {
halbb_gpio_setting(bb, (u8)val[0], (enum bb_path)val[1],
(bool)val[2],
(enum bb_rfe_src_sel)val[3]);
}
} else if (_os_strcmp(input[1], "dbg") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]);
#ifdef BB_8852A_2_SUPPORT
if (_os_strcmp(input[2], "pop_en") == 0) {
halbb_pop_en(bb, (bool)val[0],
(enum phl_phy_idx)val[1]);
} else if (_os_strcmp(input[2], "set_pd_low") == 0) {
halbb_set_pd_lower_bound(bb, (u8)val[0],
(enum channel_width)val[1],
(enum phl_phy_idx)val[2]);
} else if (_os_strcmp(input[2], "per") == 0) {
halbb_get_per_8852a_2(bb, (enum phl_phy_idx)val[0]);
}
#endif
} else if (_os_strcmp(input[1], "gain_ofst") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
halbb_normal_efuse_verify(bb, (s8)val[0], (enum rf_path)val[1], (enum phl_phy_idx)val[2]);
#ifdef BB_8852B_SUPPORT
} else if (_os_strcmp(input[1], "rf_sw_si_rw") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[5], DCMD_HEX, &val[3]);
if (val[0] > 2) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[SW_SI] Do not run test!\n");
return;
} else if (val[1] > 10000) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[SW_SI] Out-of test range!\n");
return;
} else if (val[2] > 3) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[SW_SI] Wrong path setting!\n");
return;
} else if (val[3] > 0xff) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[SW_SI] Wrong addr setting!\n");
return;
} else {
while (j < val[1]) {
judge_f = halbb_rf_sw_si_test(bb, (enum rf_path)val[2], (u8)val[3], j);
if (!judge_f){
BB_WARNING("[%s] while ocunter = %d\n", __func__, j);
break;
} else {
BB_WARNING("[%s] while ocunter = %d\n", __func__, j);
}
j++;
}
}
#endif
}
#if 0
else if (_os_strcmp(input[1], "sc_idx") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
for (i = 0; i <= 15; i++) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"rpt(0, %d) = 0x%x\n", i,
halbb_get_csi_buf_idx(bb, (u8)val[0], i));
}
}
#endif
*_used = used;
*_out_len = out_len;
}
#ifdef HALBB_DIG_MCC_SUPPORT
u8 halbb_upd_mcc_macid(struct bb_info *bb, struct bb_mcc_i *mi)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
u8 i = 0, role_ch = 0, band_idx = MCC_BAND_NUM;
BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__);
role_ch = mi->chandef->center_ch;
for (i = 0; i < MCC_BAND_NUM; i++) {
if (mcc_dm->mcc_rf_ch[i].center_ch == role_ch) {
band_idx = i;
break;
}
}
if (band_idx == MCC_BAND_NUM) {
BB_WARNING("%s, band_idx = %d", __func__, band_idx);
return HALBB_SET_FAIL;
}
if (mi->type == PHL_RTYPE_AP) {
mcc_dm->softap_macid = mi->self_macid;
BB_DBG(bb, DBG_DIG, "SoftAP macid = %d\n",
mcc_dm->softap_macid);
}
return HALBB_SET_SUCCESS;
}
void halbb_mcc_stop(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
u8 i = 0, j = 0;
BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__);
if (mcc_dm->mcc_status_en == false)
return;
mcc_dm->mcc_status_en = false;
for (i = 0; i < MCC_BAND_NUM; i++) {
mcc_dm->sta_cnt[i] = 0;
mcc_dm->mcc_rf_ch[i].chan = INVALID_INIT_VAL;
mcc_dm->mcc_rf_ch[i].center_ch = INVALID_INIT_VAL;
}
}
u8 halbb_mcc_start(struct bb_info *bb, struct bb_mcc_i *mi_1,
struct bb_mcc_i *mi_2)
{
u8 ret = HALBB_SET_FAIL;
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__);
halbb_mem_cpy(bb, &mcc_dm->mcc_rf_ch[MCC_BAND_1], mi_1->chandef,
sizeof(struct rtw_chan_def));
halbb_mem_cpy(bb, &mcc_dm->mcc_rf_ch[MCC_BAND_2], mi_2->chandef,
sizeof(struct rtw_chan_def));
ret = halbb_upd_mcc_macid(bb, mi_1);
if (ret != HALBB_SET_SUCCESS)
goto exit;
ret = halbb_upd_mcc_macid(bb, mi_2);
if (ret != HALBB_SET_SUCCESS)
goto exit;
mcc_dm->mcc_status_en = true;
ret = HALBB_SET_SUCCESS;
exit:
return ret;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_api.c
|
C
|
agpl-3.0
| 49,438
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_H_
#define _HALBB_API_H_
#include "halbb_ic_hw_info.h"
/*@--------------------------[Define] ---------------------------------------*/
#define IGI_2_RSSI(igi) (igi - 10)
#define FUNC_ENABLE 1
#define FUNC_DISABLE 2
/*@--------------------------[Enum]------------------------------------------*/
enum bb_rfe_src_sel {
PAPE_RFM = 0,
GNT_BT_INV = 1,
LNA0N = 2,
LNAON_RFM = 3,
TRSW_RFM = 4,
TRSW_RFM_B = 5,
GNT_BT = 6,
ZERO = 7,
ANTSEL_0 = 8,
ANTSEL_1 = 9,
ANTSEL_2 = 0xa,
ANTSEL_3 = 0xb,
ANTSEL_4 = 0xc,
ANTSEL_5 = 0xd,
ANTSEL_6 = 0xe,
ANTSEL_7 = 0xf
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_api_info {
u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
u8 tx_queue_bitmap; /*REG0x520[23:16]*/
u8 ccktx_path;
u8 pri_ch_idx;
u8 central_ch;
u8 bw;
enum band_type band;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_reset_bb_phy(struct bb_info *bb, enum phl_phy_idx phy_idx);
u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
void halbb_gpio_setting_init(struct bb_info *bb);
void halbb_pre_agc_en(struct bb_info *bb, bool enable);
void halbb_set_gain_error(struct bb_info *bb, u8 central_ch);
u8 halbb_stop_ic_trx(struct bb_info *bb, u8 set_type);
void halbb_ic_api_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_reset_adc(struct bb_info *bb);
void halbb_ic_hw_setting_non_io(struct bb_info *bb);
void halbb_ic_hw_setting_low_io(struct bb_info *bb);
void halbb_ic_hw_setting(struct bb_info *bb);
void halbb_ic_hw_setting_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_api.h
|
C
|
agpl-3.0
| 2,494
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_EX_H_
#define _HALBB_API_EX_H_
#include "halbb_ic_hw_info.h"
#include "halbb_api.h"
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
struct bb_mcc_i {
enum role_type type;
struct rtw_chan_def *chandef;
u32 *macid_bitmap;
u8 macid_map_len;
u8 self_macid;
};
void halbb_dyn_1r_cca_en(struct bb_info *bb, bool en);
u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
u16 halbb_get_csi_buf_idx(struct bb_info *bb, u8 buf_idx, u8 txsc_idx);
u16 halbb_cfg_cmac_tx_ant(struct bb_info *bb, enum rf_path tx_path);
void halbb_gpio_setting_all(struct bb_info *bb, u8 rfe_idx);
void halbb_gpio_setting(struct bb_info *bb, u8 gpio_idx, enum bb_path path,
bool inv, enum bb_rfe_src_sel src);
u8 halbb_get_txsc(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width cbw, enum channel_width dbw);
void halbb_reset_bb(struct bb_info *bb);
u32 halbb_read_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask);
bool halbb_write_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask,
u32 data);
bool halbb_rf_set_bb_reg(struct bb_info *bb, u32 addr, u32 bit_mask, u32 data);
u32 halbb_rf_get_bb_reg(struct bb_info *bb, u32 addr, u32 mask);
void halbb_ctrl_rf_mode(struct bb_info *bb, enum phl_rf_mode mode);
bool halbb_ctrl_rx_path(struct bb_info *bb, enum rf_path rx_path);
bool halbb_ctrl_tx_path(struct bb_info *bb, enum rf_path rx_path);
void halbb_ctrl_trx_path(struct bb_info *bb, enum rf_path tx_path, u8 tx_nss,
enum rf_path rx_path, u8 rx_nss);
void halbb_tssi_bb_reset(struct bb_info *bb);
void halbb_dfs_en(struct bb_info *bb, bool en);
void halbb_adc_en(struct bb_info *bb, bool en);
void halbb_tssi_cont_en(struct bb_info *bb, bool en, enum rf_path path);
void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_ctrl_bw(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_ch(struct bb_info *bb, u8 central_ch, enum band_type band,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_ch2_80p80(struct bb_info *bb, u8 central_ch);
bool halbb_ctrl_bw_ch(struct bb_info *bb, u8 pri_ch, u8 central_ch_seg0,
u8 central_ch_seg1, enum band_type band,
enum channel_width bw, enum phl_phy_idx phy_idx);
void halbb_ctrl_dbcc(struct bb_info *bb, bool dbcc_enable);
void halbb_cfg_dbcc(struct bb_info *bb, bool dbcc_enable);
void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
void halbb_ctrl_cck_en(struct bb_info *bb, bool cck_enable,
enum phl_phy_idx phy_idx);
void halbb_ctrl_ofdm_en(struct bb_info *bb, bool ofdm_enable,
enum phl_phy_idx phy_idx);
void halbb_rx_setting(struct bb_info *bb, u8 patch_idx);
void halbb_ctrl_btg(struct bb_info *bb, bool btg);
void halbb_ctrl_btc_preagc(struct bb_info *bb, bool bt_en);
void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound(struct bb_info *bb, u8 bound,
enum channel_width bw, enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound_cck(struct bb_info *bb, u8 bound,
enum channel_width bw, enum phl_phy_idx phy_idx);
u8 halbb_querry_pd_lower_bound(struct bb_info *bb, bool get_en_info,
enum phl_phy_idx phy_idx);
u8 halbb_get_losel(struct bb_info *bb);
void halbb_set_igi(struct bb_info *bb, u8 lna_idx, bool tia_idx, u8 rxbb_idx,
enum rf_path path);
void halbb_set_tx_pow_pattern_shap(struct bb_info *bb, u8 ch,
bool is_ofdm, enum phl_phy_idx phy_idx);
void halbb_set_tx_pow_ref(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_normal_efuse_verify(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path, enum phl_phy_idx phy_idx);
u8 halbb_upd_mcc_macid(struct bb_info *bb, struct bb_mcc_i *mi);
void halbb_mcc_stop(struct bb_info *bb);
u8 halbb_mcc_start(struct bb_info *bb, struct bb_mcc_i *mi_1,
struct bb_mcc_i *mi_2);
void halbb_normal_efuse_verify_cck(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_api_ex.h
|
C
|
agpl-3.0
| 4,880
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_AUTO_DBG_SUPPORT
#define HALBB_CHK_HANG_APIS
#ifdef HALBB_CHK_HANG_APIS
void halbb_auto_chk_hang_reset(struct bb_info *bb)
{
struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i;
struct bb_chk_hang_info *chk_hang = &a_dbg->bb_chk_hang_i;
halbb_mem_set(bb, chk_hang->dbg_port_val, 0, chk_hang->table_size);
}
void halbb_auto_chk_hang(struct bb_info *bb)
{
struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i;
struct bb_chk_hang_info *chk_hang = &a_dbg->bb_chk_hang_i;
u32 dbg_port = 0;
u32 dbg_port_value = 0;
u32 i = 0;
BB_DBG(bb, DBG_AUTO_DBG, "[%s]\n", __func__);
/*=== Get check hang Information ===============================*/
/*Get packet counter Report*/
/*Get BB Register*/
/*Get RF Register*/
/*Get Debug Port*/
for (i = 0; i < chk_hang->table_size; i++) {
dbg_port = chk_hang->dbg_port_table[i];
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
halbb_set_bb_dbg_port_ip(bb, (dbg_port & 0xff0000) >> 16);
halbb_set_bb_dbg_port(bb, dbg_port & 0xffff);
dbg_port_value = halbb_get_bb_dbg_port_val(bb);
halbb_release_bb_dbg_port(bb);
BB_DBG(bb, DBG_AUTO_DBG, "dbg_port[0x%x]=(0x%x)\n",
dbg_port, dbg_port_value);
} else {
BB_DBG(bb, DBG_AUTO_DBG, "Dbg_port Racing Fail!\n");
return;
}
}
/*=== Make check hang decision ===============================*/
BB_DBG(bb, DBG_AUTO_DBG, "Check Hang Decision\n");
halbb_auto_chk_hang_reset(bb);
}
void halbb_auto_chk_hang_init(struct bb_info *bb)
{
struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i;
struct bb_chk_hang_info *chk_hang = &a_dbg->bb_chk_hang_i;
u32 dbg_port_table[] = {0x0, 0x803, 0x208, 0xab0};
u32 table_size = sizeof(dbg_port_table);
chk_hang->table_size = table_size;
chk_hang->dbg_port_table = halbb_mem_alloc(bb, table_size);
halbb_mem_cpy(bb, chk_hang->dbg_port_table, dbg_port_table, table_size);
chk_hang->dbg_port_val= halbb_mem_alloc(bb, table_size);
a_dbg->auto_dbg_type |= AUTO_DBG_CHECK_HANG;
}
#endif
void halbb_auto_debug(struct bb_info *bb)
{
struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i;
if (!(bb->support_ability & BB_AUTO_DBG))
return;
/*check hang*/
if (a_dbg->auto_dbg_type & AUTO_DBG_CHECK_HANG)
halbb_auto_chk_hang(bb);
/*check RX Part*/
/*check TX Part*/
}
void halbb_auto_debug_init(struct bb_info *bb)
{
//struct bb_auto_dbg_info *a_dbg = &bb->bb_auto_dbg_i;
/*check hang*/
halbb_auto_chk_hang_init(bb);
/*check RX Part*/
/*check TX Part*/
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_auto_dbg.c
|
C
|
agpl-3.0
| 3,462
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_AUTO_DBG_H__
#define __HALBB_AUTO_DBG_H__
#ifdef HALBB_AUTO_DBG_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_auto_dbg_t {
AUTO_DBG_CHECK_HANG = BIT(0),
AUTO_DBG_CHECK_TX = BIT(1)
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_chk_hang_info {
u32 table_size;
u32 *dbg_port_table;
u32 *dbg_port_val;
};
struct bb_auto_dbg_info {
enum bb_auto_dbg_t auto_dbg_type;
struct bb_chk_hang_info bb_chk_hang_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_auto_debug(struct bb_info *bb);
void halbb_auto_debug_init(struct bb_info *bb);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_auto_dbg.h
|
C
|
agpl-3.0
| 1,778
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CFG_IC_H__
#define __HALBB_CFG_IC_H__
#ifdef CONFIG_RTL8852A
//#define BB_8852A_CAV_SUPPORT /*CAV*/
#define BB_8852A_2_SUPPORT /*> CBV*/
#endif
#ifdef CONFIG_RTL8852B
#define BB_8852B_SUPPORT
#endif
#ifdef CONFIG_RTL8852C
#define BB_8852C_SUPPORT
#endif
#ifdef CONFIG_RTL8192XB
#define BB_8192XB_SUPPORT
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_cfg_ic.h
|
C
|
agpl-3.0
| 1,313
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_CFO_TRK_SUPPORT
#ifdef BB_DYN_CFO_TRK_LOP
void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en)
{
bb->bb_cfo_trk_i.bb_dyn_cfo_trk_lop_i.dyn_cfo_trk_loop_en = en;
}
void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i;
struct bb_cfo_trk_lop_cr_info *cr;
if (state >= DCTL_NUM)
return;
if (state == dctl->dyn_cfo_trk_loop_state) {
dctl->dctl_hold_cnt++;
BB_DBG(bb, DBG_IC_API, "hold_cnt = %d", dctl->dctl_hold_cnt);
return;
}
dctl->dyn_cfo_trk_loop_state = state;
dctl->dctl_hold_cnt = 0;
cr = &dctl->bb_cfo_trk_lop_cr_i[state];
halbb_set_reg(bb, 0x4404, 0x7C00, cr->dctl_data); /*8852a CR*/
halbb_set_reg(bb, 0x440c, 0x7C00, cr->dctl_pilot);
BB_DBG(bb, DBG_IC_API, "dctl_data = 0x%x, dctl_pilot = 0x%x", cr->dctl_data, cr->dctl_pilot);
}
void halbb_dyn_cfo_trk_loop(struct bb_info *bb)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i;
struct bb_link_info *link = &bb->bb_link_i;
struct rtw_phl_stainfo_t *sta;
u16 snr_tmp = 0;
if (!dctl->dyn_cfo_trk_loop_en) {
BB_DBG(bb, DBG_IC_API, "dyn_cfo_trk_loop_en = %d",
dctl->dyn_cfo_trk_loop_en);
return;
}
if (!link->is_linked)
return;
if (!link->is_one_entry_only)
return;
sta = bb->phl_sta_info[bb->bb_link_i.one_entry_macid];
if (!sta)
return;
snr_tmp = sta->hal_sta->rssi_stat.snr_ma;
BB_DBG(bb, DBG_IC_API, "macid=%d, SNR = %s",
bb->bb_link_i.one_entry_macid,
halbb_print_sign_frac_digit2(bb, snr_tmp, 16, 4));
BB_DBG(bb, DBG_IC_API, "snr_th{L, H} = {%d, %d}",
dctl->dctl_snr_th_l >> RSSI_MA_H, dctl->dctl_snr_th_h >> RSSI_MA_H);
if (snr_tmp >= dctl->dctl_snr_th_h)
halbb_cfo_trk_loop_cr_cfg(bb, DCTL_LINK);
else if (snr_tmp <= dctl->dctl_snr_th_l)
halbb_cfo_trk_loop_cr_cfg(bb, DCTL_SNR);
}
void halbb_dyn_cfo_trk_loop_init(struct bb_info *bb)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_dyn_cfo_trk_lop_info *dctl = &cfo_trk->bb_dyn_cfo_trk_lop_i;
dctl->dyn_cfo_trk_loop_en = false;
dctl->dyn_cfo_trk_loop_state = DCTL_SNR;
dctl->dctl_snr_th_l = (u16)5 << RSSI_MA_H;
dctl->dctl_snr_th_h = (u16)7 << RSSI_MA_H;
dctl->bb_cfo_trk_lop_cr_i[DCTL_SNR].dctl_data = 0x1f;
dctl->bb_cfo_trk_lop_cr_i[DCTL_SNR].dctl_pilot = 0x7;
dctl->bb_cfo_trk_lop_cr_i[DCTL_LINK].dctl_data = 0x1f;
dctl->bb_cfo_trk_lop_cr_i[DCTL_LINK].dctl_pilot = 0x9;
}
#endif
void halbb_digital_cfo_comp(struct bb_info *bb, s32 curr_cfo)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_cfo_trk_cr_info *cr = &bb->bb_cfo_trk_i.bb_cfo_trk_cr_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct rtw_hal_com_t *hal = bb->hal_com;
//u32 r_ax_pwr_ul_ctrl2;
s32 cfo_avg_312; /*in unit of sub-carrier spacing*/
s32 digital_cfo_comp_offset;
bool is_positive = IS_GREATER(curr_cfo, 0);
if (!bb_link->is_linked) {
BB_DBG(bb, DBG_CFO_TRK, "[%s] is_linked=%d\n", __func__,
bb_link->is_linked);
return;
}
if (curr_cfo == 0) {
BB_DBG(bb, DBG_CFO_TRK, "curr_cfo=0\n");
return;
}
BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__);
// For manually fine tune digital cfo
digital_cfo_comp_offset = halbb_get_reg(bb, 0x4264, 0x00000003);
/*CR{S(12,11} = (CFO_avg{S(12,2)} << 9) / 312.5*/
/*CR = X(KHz) << 9 / 312.5(KHz) = X << 10 / 625 ~= X*(1000/625) = (X*8)/5 = (X << 3)/5 */
if(is_positive) {
cfo_avg_312 = HALBB_DIV(curr_cfo << 3, 5) + digital_cfo_comp_offset;
} else {
cfo_avg_312 = HALBB_DIV(curr_cfo << 3, 5) - digital_cfo_comp_offset;
}
halbb_print_sign_frac_digit(bb, curr_cfo, 32, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CFO_TRK, "[CFO_DBG] [Digital Comp] cfo: %s KHz\n", bb->dbg_buf);
halbb_print_sign_frac_digit(bb, cfo_avg_312, 32, 11, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CFO_TRK, "[CFO_DBG] cfo_avg_312: %s * 312.5KHz\n", bb->dbg_buf);
#ifdef BB_8852A_2_SUPPORT
if (bb->ic_type == BB_RTL8852A && hal->cv == CBV)
cfo_avg_312 = cfo_avg_312 * (-1); /* 8852A bug*/
#endif
// 0x448C[11:0] CFO compensation value in unit of sub-carrier spacing
halbb_set_reg(bb, cr->r_cfo_comp_seg0_312p5khz, cr->r_cfo_comp_seg0_312p5khz_m, cfo_avg_312);
}
void halbb_digital_cfo_comp_init(struct bb_info *bb)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_cfo_trk_cr_info *cr = &bb->bb_cfo_trk_i.bb_cfo_trk_cr_i;
// 0x4494[29] Whether the memory of r_cfo_comp_312p5khz is valid
halbb_set_reg(bb, cr->r_cfo_comp_seg0_vld, cr->r_cfo_comp_seg0_vld_m, 1);
// 0x4490[27:24] r_cfo_weighting
halbb_set_reg(bb, cr->r_cfo_wgting, cr->r_cfo_wgting_m, 8);
/* 0xD248 */
/* All scenario set CFO comp.*/
rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 0, 0xd248, 0x7, 0);
}
void halbb_cfo_trk_reset(struct bb_info *bb)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
BB_DBG(bb, DBG_CFO_TRK, "%s ======>\n", __func__);
bb_cfo_trk->is_adjust = false;
if (bb_cfo_trk->crystal_cap > bb_cfo_trk->def_x_cap) {
halbb_set_crystal_cap(bb, bb_cfo_trk->crystal_cap - 1);
} else if (bb_cfo_trk->crystal_cap < bb_cfo_trk->def_x_cap) {
halbb_set_crystal_cap(bb, bb_cfo_trk->crystal_cap + 1);
}
BB_DBG(bb, DBG_CFO_TRK, "(0x%x) approach to dflt_val=(0x%x)\n",
bb_cfo_trk->crystal_cap, bb_cfo_trk->def_x_cap);
}
void halbb_cfo_acc_io_en(struct bb_info *bb)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
BB_DBG(bb, DBG_CFO_TRK, "[%s]===>\n", __func__);
if (!cfo_trk->cfo_trig_by_timer_en)
return;
halbb_cfo_dm(bb);
halbb_cfg_timers(bb, BB_SET_TIMER, &bb->bb_cfo_trk_i.cfo_timer_i);
}
void halbb_cfo_acc_callback(void *context)
{
struct bb_info *bb = (struct bb_info *)context;
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct halbb_timer_info *timer = &cfo_trk->cfo_timer_i;
BB_DBG(bb, DBG_CFO_TRK, "[%s]===>\n", __func__);
timer->timer_state = BB_TIMER_IDLE;
if (bb->phl_com->hci_type == RTW_HCI_PCIE)
halbb_cfo_acc_io_en(bb);
else
rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx);
}
void halbb_cfo_acc_timer_init(struct bb_info *bb)
{
struct halbb_timer_info *timer = &bb->bb_cfo_trk_i.cfo_timer_i;
BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__);
timer->event_idx = BB_EVENT_TIMER_CFO;
timer->timer_state = BB_TIMER_IDLE;
halbb_init_timer(bb, &timer->timer_list, halbb_cfo_acc_callback, bb, "halbb_cfo_timer");
}
void halbb_cfo_deinit(struct bb_info *bb)
{
BB_DBG(bb, DBG_CFO_TRK, "halbb_cfo_deinit");
}
void halbb_cfo_trk_init(struct bb_info *bb)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
BB_DBG(bb, DBG_CFO_TRK, "[%s]=========>\n", __func__);
/* Init crystal cap from efuse */
bb_cfo_trk->def_x_cap = bb->phl_com->dev_cap.xcap & 0x7f;
bb_cfo_trk->crystal_cap = bb_cfo_trk->def_x_cap;
bb_cfo_trk->is_adjust = false;
bb_cfo_trk->x_cap_ofst = 0;
bb_cfo_trk->cfo_th[0] = CFO_TRK_TH_1 << 2;
bb_cfo_trk->cfo_th[1] = CFO_TRK_TH_2 << 2;
bb_cfo_trk->cfo_th[2] = CFO_TRK_TH_3 << 2;
bb_cfo_trk->cfo_th[3] = CFO_TRK_TH_4 << 2;
bb_cfo_trk->cfo_th_en = CFO_TRK_ENABLE_TH << 2;
bb_cfo_trk->cfo_th_stop = CFO_TRK_STOP_TH << 2;
bb_cfo_trk->sw_comp_fine_tune = CFO_SW_COMP_FINE_TUNE << 2;
bb_cfo_trk->multi_sta_cfo_mode = TP_BASED_AVG_MODE;
bb_cfo_trk->man_cfo_tol = false;
BB_DBG(bb, DBG_CFO_TRK, "Default xcap=0x%x\n", bb_cfo_trk->def_x_cap);
// For manually fine tune digital cfo
halbb_set_reg(bb, 0x4264, 0x00000003, 1);
bb_cfo_trk->tb_tx_comp_cfo_th = DIGI_CFO_COMP_LIMIT << 2;
halbb_digital_cfo_comp_init(bb);
bb_cfo_trk->cfo_timer_i.cb_time = 2000;
bb_cfo_trk->cfo_trig_by_timer_en = false;
bb_cfo_trk->bb_cfo_trk_state = CFO_STATE_0;
bb_cfo_trk->bb_cfo_trk_cnt = 0;
bb_cfo_trk->cfo_src = CFO_SRC_PREAMBLE;
// For NIC only, to speed up sw CFO compensation
bb_cfo_trk->cfo_dyn_acc_en = (dev->rfe_type < 50) ? true : false;
bb_cfo_trk->cfo_trk_by_data_en = false;
}
void halbb_set_crystal_cap(struct bb_info *bb, u8 crystal_cap)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct rtw_hal_com_t *hal = bb->hal_com;
u32 sc_xi_val = 0, sc_xo_val = 0;
if (bb_cfo_trk->crystal_cap == crystal_cap)
return;
if (crystal_cap > 0x7F) {
BB_DBG(bb, DBG_CFO_TRK, "crystal_cap(0x%x) > 0x7F\n", crystal_cap);
crystal_cap = 0x7F;
}
rtw_hal_mac_set_xcap(hal, SC_XO, (u32)crystal_cap & 0x7F);
rtw_hal_mac_set_xcap(hal, SC_XI, (u32)crystal_cap & 0x7F);
rtw_hal_mac_get_xcap(hal, SC_XO, &sc_xo_val);
rtw_hal_mac_get_xcap(hal, SC_XI, &sc_xi_val);
BB_DBG(bb, DBG_CFO_TRK, "Set sc_xi/xo= {0x%x, 0x%x}\n", sc_xi_val, sc_xo_val);
bb_cfo_trk->crystal_cap = (u8)sc_xi_val;
bb_cfo_trk->x_cap_ofst = (s8)DIFF_2(bb_cfo_trk->crystal_cap, bb_cfo_trk->def_x_cap);
if (bb_cfo_trk->crystal_cap < bb_cfo_trk->def_x_cap)
bb_cfo_trk->x_cap_ofst = bb_cfo_trk->x_cap_ofst * (-1);
}
void halbb_crystal_cap_adjust(struct bb_info *bb, s32 curr_cfo)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct bb_path_info *bb_path = &bb->bb_path_i;
u8 x_cap = bb_cfo_trk->crystal_cap;
u8 step = 0;
s32 cfo_abs = ABS_32(curr_cfo);
bool is_positive = IS_GREATER(curr_cfo, 0);
BB_DBG(bb, DBG_CFO_TRK, "[CFO_DBG] %s ======>\n", __func__);
if (!bb_cfo_trk->is_adjust) {
/* If cfo_avg > th, enable tracking */
if (cfo_abs > bb_cfo_trk->cfo_th_en)
bb_cfo_trk->is_adjust = true;
} else {
if (cfo_abs < bb_cfo_trk->cfo_th_stop)
bb_cfo_trk->is_adjust = false;
}
if (!bb_cfo_trk->is_adjust) {
BB_DBG(bb, DBG_CFO_TRK, "Stop Tracking\n");
/*halbb_digital_cfo_comp(bb);*/
return;
}
/*Adjust Crystal Cap. */
if (cfo_abs > bb_cfo_trk->cfo_th[3])
step = 7;
else if (cfo_abs > bb_cfo_trk->cfo_th[2])
step = 5;
else if (cfo_abs > bb_cfo_trk->cfo_th[1])
step = 3;
else if (cfo_abs > bb_cfo_trk->cfo_th[0])
step = 1;
else
return;
if (is_positive)
x_cap += step;
else if (x_cap > step)
x_cap -= step;
//x_cap = (is_positive) ? (x_cap + step) : (x_cap - step);
BB_DBG(bb, DBG_CFO_TRK, "TH[en, stop]={%d, %d}, TH[3:0]={%d, %d, %d, %d}\n",
bb_cfo_trk->cfo_th_en >> 2, bb_cfo_trk->cfo_th_en >> 2,
bb_cfo_trk->cfo_th[3] >> 2, bb_cfo_trk->cfo_th[2] >> 2,
bb_cfo_trk->cfo_th[1] >> 2, bb_cfo_trk->cfo_th[0] >> 2);
BB_DBG(bb, DBG_CFO_TRK, "step=%s%d\n",
(is_positive) ? "+" : "-", step);
halbb_set_crystal_cap(bb, x_cap);
}
s32 halbb_avg_cfo_calc(struct bb_info *bb)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct rtw_phl_stainfo_t *sta;
struct rtw_cfo_info *cfo_t = NULL;
s32 cfo_all_avg = 0;
u16 macid;
sta = bb->phl_sta_info[bb_link->one_entry_macid];
if (!sta)
return bb_cfo_trk->cfo_avg_pre;
macid = sta->macid;
cfo_t = &sta->hal_sta->cfo_stat;
BB_DBG(bb, DBG_CFO_TRK, "one-entry-only macid=%d\n", macid);
cfo_all_avg = HALBB_DIV(cfo_t->cfo_tail, (s32)cfo_t->cfo_cnt);
BB_DBG(bb, DBG_CFO_TRK, "Total cfo=(%d), pkt_cnt=(%d), avg_cfo=(%d)\n",
cfo_t->cfo_tail >> 2, cfo_t->cfo_cnt, cfo_all_avg >> 2);
return cfo_all_avg;
}
s32 halbb_multi_sta_avg_cfo_calc(struct bb_info *bb)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct rtw_hal_com_t *hal = bb->hal_com;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
u8 band = bb->hal_com->band[0].cur_chandef.band;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct rtw_phl_stainfo_t *sta;
struct rtw_cfo_info *cfo_t = NULL;
s32 target_cfo = 0;
s32 cfo_khz_all = 0;
s32 cfo_khz_all_tp_wgt = 0;
s32 cfo_avg = 0;
s32 max_cfo_lb= 0x80000000;
s32 min_cfo_ub = 0x7fffffff;
u16 cfo_cnt_all = 0;
u8 active_entry_cnt = 0, sta_cnt = 0;
u32 tp_all = 0;
u16 active_entry = 0;
u8 i;
u8 cfo_tol = 0;
u16 macid;
BB_DBG(bb, DBG_CFO_TRK, "Multi entry cfo_trk\n");
if (!bb_cfo_trk->man_cfo_tol) {
if (band == BAND_ON_24G)
bb_cfo_trk->sta_cfo_tolerance = STA_CFO_TOLERANCE_2G;
else
bb_cfo_trk->sta_cfo_tolerance = STA_CFO_TOLERANCE_5G;
}
BB_DBG(bb, DBG_CFO_TRK, "Default multi-sta cfo_trk tolerance=%d\n",
bb_cfo_trk->sta_cfo_tolerance);
/* There are two extra multi-sta strategies remaining as references*/
#if 0
if (bb_cfo_trk->multi_sta_cfo_mode == PKT_BASED_AVG_MODE) {
/* Method-1: Centroid pkt based cfo tracking: Compute average cfo from all sta PPDUs */
/* Just like one entry only method*/
BB_DBG(bb, DBG_CFO_TRK, "Pkt based average mode\n");
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
if (bb_cfo_trk->cfo_cnt[i] == 0)
continue;
//BB_DBG(bb, DBG_CFO_TRK, "Macid=%d\n", i);
cfo_khz_all += bb_cfo_trk->cfo_tail[i];
cfo_cnt_all += bb_cfo_trk->cfo_cnt[i];
cfo_avg = HALBB_DIV(cfo_khz_all, (s32)cfo_cnt_all);
BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Multi-sta total cfo=(%d), pkt_cnt=(%d), avg_cfo=(%d)\n",
cfo_khz_all, cfo_cnt_all, cfo_avg);
target_cfo = cfo_avg;
}
} else if (bb_cfo_trk->multi_sta_cfo_mode == ENTRY_BASED_AVG_MODE) {
/* Method-2: Entry based cfo tracking: Compute average cfo of ertries */
BB_DBG(bb, DBG_CFO_TRK, "Entry based average mode\n");
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
if (bb_cfo_trk->cfo_cnt[i] == 0)
continue;
active_entry |= BIT(i);
bb_cfo_trk->cfo_avg[i] = HALBB_DIV(bb_cfo_trk->cfo_tail[i],
(s32)bb_cfo_trk->cfo_cnt[i]);
cfo_khz_all += bb_cfo_trk->cfo_avg[i];
BB_DBG(bb, DBG_CFO_TRK, "Macid=%d, cfo_avg=%d\n",
i, bb_cfo_trk->cfo_avg[i]);
}
/* Average of all entries */
sta_cnt = (u8) halbb_ones_num_in_bitmap(active_entry, sizeof(active_entry) * 8);
cfo_avg = HALBB_DIV(cfo_khz_all, (s32)sta_cnt);
BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Multi-sta cfo_acc=(%d), entry_cnt=(%d), avg_cfo=(%d)\n",
cfo_khz_all, sta_cnt, cfo_avg);
target_cfo = cfo_avg;
}
#endif
/* Method-3: Tp based cfo tracking: With Tp_wgt */
BB_DBG(bb, DBG_CFO_TRK, "Throughput based average mode\n");
cfo_tol = bb_cfo_trk->sta_cfo_tolerance;
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
sta = bb->phl_sta_info[i];
macid = sta->macid;
if (!is_sta_active(sta))
continue;
if ((dev->rfe_type >= 50) && (sta->macid == 0))
continue;
cfo_t = &sta->hal_sta->cfo_stat;
sta_cnt++;
if (cfo_t->cfo_cnt != 0) {
cfo_t->cfo_avg =
HALBB_DIV(cfo_t->cfo_tail, (s32)cfo_t->cfo_cnt);
active_entry_cnt++;
} else { /* Linked, but no pkts received*/
cfo_t->cfo_avg = cfo_t->pre_cfo_avg;
}
/* Calculate the cfo torlence window */
if ((cfo_t->cfo_avg - cfo_tol) > max_cfo_lb)
max_cfo_lb = cfo_t->cfo_avg - cfo_tol;
if ((cfo_t->cfo_avg + cfo_tol) < min_cfo_ub)
min_cfo_ub = cfo_t->cfo_avg + cfo_tol;
cfo_khz_all += cfo_t->cfo_avg;
/* Acc throuhgput of all entries */
tp_all += cfo_t->tp;
/* Multiple tp_wgt first*/
cfo_khz_all_tp_wgt += cfo_t->cfo_avg * cfo_t->tp;
BB_DBG(bb, DBG_CFO_TRK, "[%d] Macid=%d, cfo_avg=%d, tp=%d\n",
i, macid, cfo_t->cfo_avg, cfo_t->tp);
cfo_t->pre_cfo_avg = cfo_t->cfo_avg;
if (sta_cnt >= bb->hal_com->assoc_sta_cnt)
break;
}
/* Average of all entries with tp_wgt */
BB_DBG(bb, DBG_CFO_TRK, "Assoc. sta cnt(%d)\n", sta_cnt);
BB_DBG(bb, DBG_CFO_TRK, "Active sta cnt(%d)\n", active_entry_cnt);
/* Div. tp_all to normalize wgt*/
cfo_avg = HALBB_DIV(cfo_khz_all_tp_wgt, (s32)tp_all);
BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Multi-sta cfo with tp_wgt=(%d), avg_cfo=(%d)\n",
cfo_khz_all_tp_wgt, cfo_avg);
/* The target cfo need inside the cfo torlence window*/
BB_DBG(bb, DBG_CFO_TRK, "max_cfo_lb=%d, min_cfo_ub=%d\n",
max_cfo_lb, min_cfo_ub);
if (max_cfo_lb <= min_cfo_ub) {
BB_DBG(bb, DBG_CFO_TRK, "cfo torlence win. size = %d\n",
min_cfo_ub - max_cfo_lb);
if (cfo_avg < max_cfo_lb) {
BB_DBG(bb, DBG_CFO_TRK, "cfo_avg < win_lb\n");
target_cfo = max_cfo_lb;
} else if (cfo_avg > min_cfo_ub) {
BB_DBG(bb, DBG_CFO_TRK, "cfo_avg > win_ub\n");
target_cfo = min_cfo_ub;
} else {
target_cfo = cfo_avg;
}
} else { /* No intersection of multi-sta cfo torlence, avg. of all cfo of entries */
BB_DBG(bb, DBG_CFO_TRK, "No intersection of cfo torlence windows\n");
target_cfo = HALBB_DIV(cfo_khz_all, (s32)sta_cnt);
}
BB_DBG(bb, DBG_CFO_TRK, "s(32,2) Final target cfo=(%d)\n", target_cfo);
return target_cfo;
}
void halbb_set_cfo_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len)
{
if (val_len != 1) {
BB_DBG(bb, DBG_CFO_TRK, "[Error][CFO]Need val_len=1\n");
return;
}
BB_DBG(bb, DBG_CFO_TRK, "[%s] len=%d, val[0]=0x%x\n", __func__, val_len, val_buf[0]);
halbb_set_crystal_cap(bb, (u8)(val_buf[0] & 0xff));
}
void
halbb_cfo_counter_rst(struct bb_info *bb)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct rtw_phl_stainfo_t *sta;
struct rtw_cfo_info *cfo_t = NULL;
u8 i, sta_cnt = 0;
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
sta = bb->phl_sta_info[i];
if (!is_sta_active(sta))
continue;
cfo_t = &sta->hal_sta->cfo_stat;
cfo_t->cfo_tail = 0;
cfo_t->cfo_cnt = 0;
cfo_t->cfo_avg = 0;
cfo_t->tp = 0;
sta_cnt++;
if (sta_cnt >= bb->hal_com->assoc_sta_cnt)
break;
}
bb_cfo_trk->cfo_pkt_cnt = 0;
}
bool
halbb_cfo_trk_abort(struct bb_info *bb)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
s32 cfo_avg = 0;
/* support_ability */
if (!(bb->support_ability & BB_CFO_TRK)) {
BB_DBG(bb, DBG_CFO_TRK, "[%s] DISABLED\n", __func__);
halbb_cfo_trk_reset(bb);
return true;
}
if (bb->pause_ability & BB_CFO_TRK) {
cfo_avg = halbb_avg_cfo_calc(bb);
halbb_print_sign_frac_digit(bb, cfo_avg, 32, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CFO_TRK, "Return: Pause CFO_TRK in LV=%d\n",
bb->pause_lv_table.lv_cfo);
BB_DBG(bb, DBG_CFO_TRK, "Xcap=0x%x, cfo_avg=%s\n",
cfo_trk->crystal_cap, bb->dbg_buf);
halbb_cfo_counter_rst(bb);
return true;
}
return false;
}
void halbb_cfo_trk(struct bb_info *bb, s32 curr_cfo)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
if (halbb_cfo_trk_abort(bb))
return;
BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__);
if (!bb_link->is_linked) {
BB_DBG(bb, DBG_CFO_TRK, "is_linked=%d\n",bb_link->is_linked);
halbb_cfo_trk_reset(bb); /*xcap to default value */
return;
}
/* To avoid NIC soft-AP going to multi-sta cfo until AP side is verified for a long time*/
if ((!bb_link->is_one_entry_only) && (dev->rfe_type < 50)) {
BB_DBG(bb, DBG_CFO_TRK, "rfe_type=%d, is_one_entry_only=%d\n",
dev->rfe_type, bb_link->is_one_entry_only);
halbb_cfo_trk_reset(bb); /*xcap to default value */
return;
}
if (bb_link->first_connect)
return;
if (curr_cfo == 0) {
BB_DBG(bb, DBG_CFO_TRK, "curr_cfo=0\n");
return;
}
halbb_crystal_cap_adjust(bb, curr_cfo); /*Decide xcap need to adjust or not */
}
bool halbb_cfo_acc_mode_en(struct bb_info *bb) {
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_link_info *link = &bb->bb_link_i;
if (!cfo_trk->cfo_dyn_acc_en)
return false;
// Check TP, switch compensation period
switch (cfo_trk->bb_cfo_trk_state) {
case CFO_STATE_0:
if (link->total_tp >= CFO_TP_UPPER) {
cfo_trk->bb_cfo_trk_state = CFO_STATE_1;
cfo_trk->cfo_trig_by_timer_en = true;
// cfo_trk speed up
cfo_trk->cfo_timer_i.cb_time = CFO_COMP_PERIOD;
halbb_cfo_acc_io_en(bb);
}
break;
case CFO_STATE_1:
if (cfo_trk->bb_cfo_trk_cnt >= CFO_PERIOD_CNT) {
cfo_trk->bb_cfo_trk_cnt = 0;
cfo_trk->cfo_trig_by_timer_en = false;
}
if (cfo_trk->cfo_trig_by_timer_en) {
cfo_trk->bb_cfo_trk_cnt++;
}
if (link->total_tp <= CFO_TP_LOWER) {
cfo_trk->bb_cfo_trk_state = CFO_STATE_0;
cfo_trk->bb_cfo_trk_cnt = 0;
cfo_trk->cfo_trig_by_timer_en = false;
}
break;
default:
cfo_trk->bb_cfo_trk_state = CFO_STATE_0;
cfo_trk->bb_cfo_trk_cnt = 0;
break;
}
BB_DBG(bb, DBG_CFO_TRK, "[CFO_COMP] WD, total_tp = %d, cfo_trk_state = %d, timer_en = %d, trk_cnt = %d\n",
link->total_tp, cfo_trk->bb_cfo_trk_state, cfo_trk->cfo_trig_by_timer_en, cfo_trk->bb_cfo_trk_cnt);
return cfo_trk->cfo_trig_by_timer_en;
}
void halbb_cfo_dm(struct bb_info *bb)
{
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
bool x_cap_update = false;
u8 pre_x_cap = cfo_trk->crystal_cap;
s32 new_cfo = 0;
//s8 xtal_th_ofst;
//u8 thermal;
BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__);
#if 0
rtw_hal_rf_xtal_tracking_offset(bb->hal_com, &xtal_th_ofst);
rtw_hal_rf_get_thermal(bb->hal_com, 0, &thermal);
BB_DBG(bb, DBG_CFO_TRK, "xtal_th_ofst=%d, thermal=%d\n", xtal_th_ofst, thermal);
#endif
/* No new packet */
if (bb_link->is_linked && cfo_trk->cfo_pkt_cnt != 0) {
/* NEED MODIFY*/
if (bb_link->is_one_entry_only) {
new_cfo = halbb_avg_cfo_calc(bb);
} else {
/* To avoid NIC soft-AP going to multi-sta cfo until AP side is verified for a long time*/
if (dev->rfe_type >= 50) {
/* Multi-sta cfo tracking -> calc. centroid cfo first*/
new_cfo = halbb_multi_sta_avg_cfo_calc(bb);
}
}
}
halbb_cfo_trk(bb, new_cfo);
cfo_trk->cfo_avg_pre = new_cfo;
halbb_print_sign_frac_digit(bb, cfo_trk->cfo_avg_pre, 32, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CFO_TRK, "cfo_avg=(%s) Khz\n", bb->dbg_buf);
BB_DBG(bb, DBG_CFO_TRK, "X_cap {Default:0x%x} {Curr: 0x%x -> 0x%x}, x_cap_ofst=%d step\n",
cfo_trk->def_x_cap, pre_x_cap, cfo_trk->crystal_cap,
cfo_trk->x_cap_ofst);
x_cap_update = (cfo_trk->crystal_cap == pre_x_cap) ? false : true;
BB_DBG(bb, DBG_CFO_TRK, "Xcap_up=%d\n", x_cap_update);
if (x_cap_update) {
if (IS_GREATER(new_cfo, 0))
new_cfo -= cfo_trk->sw_comp_fine_tune;
else
new_cfo += cfo_trk->sw_comp_fine_tune;
}
halbb_digital_cfo_comp(bb, new_cfo);
halbb_cfo_counter_rst(bb);
}
void halbb_cfo_watchdog(struct bb_info *bb)
{
if (halbb_cfo_acc_mode_en(bb))
return;
BB_DBG(bb, DBG_CFO_TRK, "[%s]\n", __func__);
halbb_cfo_dm(bb);
BB_DBG(bb, DBG_CFO_TRK, "\n");
}
void halbb_parsing_cfo(struct bb_info *bb, u32 physts_bitmap,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
struct bb_rate_info *rate_info = &bb->bb_cmn_rpt_i.bb_rate_i;
struct dev_cap_t *dev = &bb->phl_com->dev_cap;
struct rtw_phl_stainfo_t *sta;
struct rtw_cfo_info *cfo_t = NULL;
s16 cfo;
u8 fw_rate_idx = rate_info->fw_rate_idx;
u8 bb_macid;
if (!(physts_bitmap & BIT(IE01_CMN_OFDM) &&
physts->bb_physts_rslt_hdr_i.ie_map_type >= LEGACY_OFDM_PKT))
return;
if (bb_cfo_trk->cfo_trk_by_data_en) {
if (!desc->user_i[0].is_data)
return;
}
if (bb_cfo_trk->cfo_src == CFO_SRC_FD)
cfo = physts->bb_physts_rslt_1_i.cfo_avg;
else
cfo = physts->bb_physts_rslt_1_i.cfo_pab_avg;
if (desc->macid_su > PHL_MAX_STA_NUM)
BB_WARNING("[%s] macid_su=%d\n", __func__, desc->macid_su);
bb_macid = bb->phl2bb_macid_table[desc->macid_su];
if (bb_macid > PHL_MAX_STA_NUM)
BB_WARNING("[%s] bb_macid=%d\n", __func__, bb_macid);
sta = bb->phl_sta_info[bb_macid];
if (!is_sta_active(sta))
return;
if (sta->macid > PHL_MAX_STA_NUM)
return;
if (!sta->hal_sta)
return;
cfo_t = &sta->hal_sta->cfo_stat;
if ((dev->rfe_type >= 50) && (bb_macid == 0)) /* No need to cnt AP Rx boardcast pkt*/
return;
/* CFO info. of all path from phy-status have been averaged */
cfo_t->cfo_tail += cfo;
cfo_t->cfo_cnt++;
bb_cfo_trk->cfo_pkt_cnt++;
/*BB_DBG(bb, DBG_CFO_TRK, "cfo_cnt[%d]=%d, all_cfo_cnt=%d\n", desc->macid_su, cfo_t->cfo_cnt, bb_cfo_trk->cfo_pkt_cnt);*/
/* Calcute throughput from rx rate idx*/
if (rate_info->mode == BB_HE_MODE) {
/* HE[3.2] = VHT[LGI]x1.25*/
cfo_t->tp +=
((bb_phy_rate_table[fw_rate_idx - MAX_RATE_VHT - MAX_RATE_HT] << 2)
+ bb_phy_rate_table[fw_rate_idx - MAX_RATE_VHT - MAX_RATE_HT]) >> 2;
} else if (rate_info->mode == BB_VHT_MODE) {
cfo_t->tp += bb_phy_rate_table[fw_rate_idx - MAX_RATE_HT];
} else {
cfo_t->tp += bb_phy_rate_table[fw_rate_idx];
}
}
void halbb_cfo_trk_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
u32 var[10] = {0};
bool timer_en_pre;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"src {0:fd, 1:preamble}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"data_only {en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dyn_acc {en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set Xcap: {1} {val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"show Xcap: {100}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"th {en, stop, 0~3} {s(8,2)}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tb_comp {s(8,2)}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"sw_comp {Xcap_enable_th (kHz)} {sw_comp_fine_tune (kHz)}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"period {en} {ms}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set_mode {multi-sta cfo_trk mode - 0:Pkts averaged mode, 1: Entry averaged mode, 2: TP based mode}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_tol {manually adjust hypothetical sta_cfo_tolerance in decimal kHz}\n");
return;
}
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if (var[0] == 1) {
HALBB_SCAN(input[2], DCMD_HEX, &var[1]);
halbb_set_crystal_cap(bb, (u8)var[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set X_cap=0x%x\n", bb_cfo_trk->crystal_cap);
} else if (var[0] == 100) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"X_cap=0x%x\n", bb_cfo_trk->crystal_cap);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Xcap_enable_th = %d (kHz)\n", bb_cfo_trk->cfo_th_en >> 2);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"sw_comp_fine_tune = %d (kHz)\n", bb_cfo_trk->sw_comp_fine_tune >> 2);
} else if (_os_strcmp(input[1], "data_only") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
bb_cfo_trk->cfo_trk_by_data_en = (bool)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_trk_by_data_en: %d\n", bb_cfo_trk->cfo_trk_by_data_en);
} else if (_os_strcmp(input[1], "dyn_acc") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
bb_cfo_trk->cfo_dyn_acc_en = (bool)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_dyn_acc_en: %d\n", bb_cfo_trk->cfo_dyn_acc_en);
} else if (_os_strcmp(input[1], "src") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
bb_cfo_trk->cfo_src = (enum bb_cfo_trk_src_t)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfo_src: %s\n",
((bb_cfo_trk->cfo_src == CFO_SRC_FD) ? "FD" : "PAB"));
} else if (_os_strcmp(input[1], "period") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]);
timer_en_pre = bb_cfo_trk->cfo_trig_by_timer_en;
bb_cfo_trk->cfo_trig_by_timer_en = (bool)var[0];
if (var[1] > 2000)
bb_cfo_trk->cfo_timer_i.cb_time = 2000;
else if (var[1] < 5)
bb_cfo_trk->cfo_timer_i.cb_time = 5;
else
bb_cfo_trk->cfo_timer_i.cb_time = (u16)var[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"timer=%d ms, trig_by_timer_en=%d\n",
bb_cfo_trk->cfo_timer_i.cb_time, bb_cfo_trk->cfo_trig_by_timer_en);
if (!timer_en_pre && bb_cfo_trk->cfo_trig_by_timer_en) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Start callback]\n");
halbb_cfo_acc_io_en(bb);
}
} else if (_os_strcmp(input[1], "th") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]);
if (_os_strcmp(input[2], "en") == 0) {
bb_cfo_trk->cfo_th_en = (u8)var[1];
} else if (_os_strcmp(input[2], "stop") == 0) {
bb_cfo_trk->cfo_th_stop = (u8)var[1];
} else {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
if (var[0] < CFO_TRK_TH_SIZE)
bb_cfo_trk->cfo_th[var[0]] = (u8)var[1];
else
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"TH[en, stop]={%d, %d}, TH[3:0]={%d, %d, %d, %d}\n",
bb_cfo_trk->cfo_th_en, bb_cfo_trk->cfo_th_en,
bb_cfo_trk->cfo_th[3], bb_cfo_trk->cfo_th[2],
bb_cfo_trk->cfo_th[1], bb_cfo_trk->cfo_th[0]);
} else if (_os_strcmp(input[1], "tb_comp") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
bb_cfo_trk->tb_tx_comp_cfo_th = (u8)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tb_tx_comp_cfo_th = %d\n",
bb_cfo_trk->tb_tx_comp_cfo_th);
} else if (_os_strcmp(input[1], "sw_comp") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]);
bb_cfo_trk->cfo_th_en = (u8)var[0] << 2;
bb_cfo_trk->sw_comp_fine_tune = (u8)var[1] << 2;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"xcap_enable_th = %d,sw_comp_fine_tune = %d\n",
bb_cfo_trk->cfo_th_en >> 2, bb_cfo_trk->sw_comp_fine_tune >> 2);
} else if (_os_strcmp(input[1], "set_mode") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
bb_cfo_trk->multi_sta_cfo_mode= (u8)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"multi_sta_cfo_mode = %d\n",
bb_cfo_trk->multi_sta_cfo_mode);
} else if (_os_strcmp(input[1], "cfo_tol") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
bb_cfo_trk->man_cfo_tol= true;
bb_cfo_trk->sta_cfo_tolerance = (u8)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"manually adjust hypothetical sta_cfo_tolerance = %d\n",
bb_cfo_trk->sta_cfo_tolerance);
}
}
void halbb_cr_cfg_cfo_trk_init(struct bb_info *bb)
{
struct bb_cfo_trk_cr_info *cr = &bb->bb_cfo_trk_i.bb_cfo_trk_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->r_cfo_comp_seg0_312p5khz = CFO_COMP_SEG0_312P5KHZ_0_A;
cr->r_cfo_comp_seg0_312p5khz_m = CFO_COMP_SEG0_312P5KHZ_0_A_M;
cr->r_cfo_comp_seg0_vld = CFO_COMP_SEG0_VLD_0_A;
cr->r_cfo_comp_seg0_vld_m = CFO_COMP_SEG0_VLD_0_A_M;
cr->r_cfo_wgting = CFO_WGTING_A;
cr->r_cfo_wgting_m = CFO_WGTING_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->r_cfo_comp_seg0_312p5khz = CFO_COMP_SEG0_312P5KHZ_0_C;
cr->r_cfo_comp_seg0_312p5khz_m = CFO_COMP_SEG0_312P5KHZ_0_C_M;
cr->r_cfo_comp_seg0_vld = CFO_COMP_SEG0_VLD_0_C;
cr->r_cfo_comp_seg0_vld_m = CFO_COMP_SEG0_VLD_0_C_M;
cr->r_cfo_wgting = CFO_WGTING_C;
cr->r_cfo_wgting_m = CFO_WGTING_C_M;
break;
#endif
#ifdef HALBB_COMPILE_AP2_SERIES
case BB_AP2:
cr->r_cfo_comp_seg0_312p5khz = CFO_COMP_SEG0_312P5KHZ_0_A2;
cr->r_cfo_comp_seg0_312p5khz_m = CFO_COMP_SEG0_312P5KHZ_0_A2_M;
cr->r_cfo_comp_seg0_vld = CFO_COMP_SEG0_VLD_0_A2;
cr->r_cfo_comp_seg0_vld_m = CFO_COMP_SEG0_VLD_0_A2_M;
cr->r_cfo_wgting = CFO_WGTING_A2;
cr->r_cfo_wgting_m = CFO_WGTING_A2_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_cfo_trk.c
|
C
|
agpl-3.0
| 32,935
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CFO_TRK_H__
#define __HALBB_CFO_TRK_H__
/*@--------------------------[Define] ---------------------------------------*/
#define CFO_TRK_TH_SIZE 4
#define CFO_TRK_TH_4 30 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_TH_3 20 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_TH_2 10 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_TH_1 0 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_ENABLE_TH 2 /* @kHz enable CFO_Track threshold*/
#define CFO_TRK_STOP_TH 2 /* @kHz disable CFO_Track threshold*/
#define CFO_SW_COMP_FINE_TUNE 2 /* @kHz expected CFO Comp. per Xcap ofst*/
#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
#define SC_XO 1 /* xcap setting output value */
#define SC_XI 0 /* xcap setting input value */
#define STA_CFO_TOLERANCE_2G 30 /* kHz */
#define STA_CFO_TOLERANCE_5G 80 /* kHz */
#define CFO_HW_RPT_2_KHZ(val) (((val) << 1) + ((val) >> 1))
#define CFO_PERIOD_CNT 15
#define CFO_TP_UPPER 100 /*MHz*/
#define CFO_TP_LOWER 50 /*MHz*/
#define CFO_COMP_PERIOD 250 /*ms*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_cfo_trk_src_t {
CFO_SRC_FD = 0,
CFO_SRC_PREAMBLE = 1
};
enum bb_cfo_trk_st_t {
CFO_STATE_0 = 0,
CFO_STATE_1 = 1
};
enum multi_sta_cfo_mode_t {
PKT_BASED_AVG_MODE = 0,
ENTRY_BASED_AVG_MODE = 1,
TP_BASED_AVG_MODE = 2,
};
#ifdef BB_DYN_CFO_TRK_LOP
enum bb_dctl_state_t {
DCTL_SNR = 0,
DCTL_LINK = 1,
DCTL_NUM
};
#endif
/*@--------------------------[Structure]-------------------------------------*/
#ifdef BB_DYN_CFO_TRK_LOP
struct bb_cfo_trk_lop_cr_info {
u8 dctl_data; /*data tracking loop filter bandwidth selection for 3rd step*/
u8 dctl_pilot; /*pilot tracking loop filter bandwidth selection for 3rd step*/
};
struct bb_dyn_cfo_trk_lop_info {
bool dyn_cfo_trk_loop_en;
enum bb_dctl_state_t dyn_cfo_trk_loop_state;
u16 dctl_snr_th_l;
u16 dctl_snr_th_h;
u8 dctl_hold_cnt;
struct bb_cfo_trk_lop_cr_info bb_cfo_trk_lop_cr_i[DCTL_NUM];
};
#endif
struct bb_cfo_trk_cr_info {
u32 r_cfo_comp_seg0_312p5khz;
u32 r_cfo_comp_seg0_312p5khz_m;
u32 r_cfo_comp_seg0_vld;
u32 r_cfo_comp_seg0_vld_m;
u32 r_cfo_wgting;
u32 r_cfo_wgting_m;
};
struct bb_cfo_trk_info {
struct bb_cfo_trk_cr_info bb_cfo_trk_cr_i;
bool cfo_trig_by_timer_en;
bool is_adjust; /*@already modify crystal cap*/
u8 cfo_th[CFO_TRK_TH_SIZE]; /*u(8,2)*/
u8 cfo_th_en;
u8 cfo_th_stop; /*u(8,2)*/
s8 x_cap_ofst;
u8 crystal_cap;
u8 def_x_cap;
s32 cfo_avg_pre; /*S(12,2), -512~+511.75 kHz*/
u32 cfo_pkt_cnt;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 tb_tx_comp_cfo_th; /*u(8,2)*/
u8 sw_comp_fine_tune; /*u(8,2)*/
u8 bb_cfo_trk_cnt;
u8 sta_cfo_tolerance;
bool man_cfo_tol;
bool cfo_dyn_acc_en;
bool cfo_trk_by_data_en;
enum bb_cfo_trk_src_t cfo_src;
enum bb_cfo_trk_st_t bb_cfo_trk_state;
enum multi_sta_cfo_mode_t multi_sta_cfo_mode;
#ifdef BB_DYN_CFO_TRK_LOP
struct bb_dyn_cfo_trk_lop_info bb_dyn_cfo_trk_lop_i;
#endif
struct halbb_timer_info cfo_timer_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef BB_DYN_CFO_TRK_LOP
void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en);
void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state);
void halbb_dyn_cfo_trk_loop(struct bb_info *bb);
void halbb_dyn_cfo_trk_loop_init(struct bb_info *bb);
#endif
void halbb_cfo_deinit(struct bb_info *bb);
void halbb_cfo_trk_init(struct bb_info *bb);
void halbb_set_crystal_cap(struct bb_info *bb, u8 crystal_cap);
void halbb_set_cfo_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
void halbb_cfo_acc_io_en(struct bb_info *bb);
void halbb_cfo_acc_timer_init(struct bb_info *bb);
void halbb_cfo_dm(struct bb_info *bb);
void halbb_cfo_watchdog(struct bb_info *bb);
void halbb_parsing_cfo(struct bb_info *bb, u32 physts_bitmap,
struct physts_rxd *desc);
void halbb_cfo_trk_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_cfo_trk_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_cfo_trk.h
|
C
|
agpl-3.0
| 5,193
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_CH_INFO_SUPPORT
bool halbb_ch_info_wait_from_physts(struct bb_info *bb, u32 dly, u32 dly_max,
enum bb_physts_bitmap_t type)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_physts_info *ch_physts = &ch_rpt->bb_ch_info_physts_i;
struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i;
bool get_ch_rpt_success = false;
u32 wait_time = 0;
BB_DBG(bb, DBG_IC_API, "dly=%d, dly_max=%d ms\n", dly, dly_max);
if (type == LEGACY_OFDM_PKT)
cfg->ch_i_type = 0;
else
cfg->ch_i_type = 1;
halbb_cfg_ch_info_cr(bb, cfg);
ch_physts->ch_info_state = CH_RPT_START_TO_WAIT;
halbb_cfg_ch_info_en(bb, CH_INFO_FROM_PHY_STS, type, bb->bb_phy_idx);
while (wait_time <= dly_max) {
//Delay for get physts
BB_DBG(bb, DBG_IC_API, "wait=%d ms\n", wait_time);
halbb_delay_ms(bb, dly);
wait_time += dly;
if (ch_physts->ch_info_state == CH_RPT_GETTED) {
get_ch_rpt_success = true;
break;
}
}
halbb_cfg_ch_info_en(bb, CH_INFO_DISABLE, type, bb->bb_phy_idx);
return get_ch_rpt_success;
}
bool halbb_chk_ch_info_cr_valid(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_rpt_size_info *ch_rpt_size = &ch_rpt->bb_ch_rpt_size_i;
u8 ch_matrix_nr[4];
u8 i = 0, j = 0;
u8 nc = 1, nr = 1;
u8 msb_bit = 0;
u8 mask_tmp = 0;
u16 per_tone_size;
u16 tone_num_table[] = {64, 128, 256, 512};
u16 tone_num_table_he[] = {64, 128, 256, 512};
u8 ofst_table[] = {0, 1, 2, 4};
/*{Data_bit}*/
if (cfg->ch_i_cmprs == 0)
ch_rpt_size->data_byte = 1;
else
ch_rpt_size->data_byte = 2;
BB_DBG(bb, DBG_IC_API, "ch_i_ele_bitmap = 0x%x\n", cfg->ch_i_ele_bitmap);
/*{Nc}*/
for (i = 0; i < 4; i++) {
ch_matrix_nr[i] = (cfg->ch_i_ele_bitmap >> (8 * i)) & 0xff;
if (i == 0 && ch_matrix_nr[i] == 0) {
BB_WARNING("ch_matrix_nr[0] = 0\n");
return false;
} else if (i >= 1) {
if (ch_matrix_nr[i] != 0) {
nc++;
if (ch_matrix_nr[i] != ch_matrix_nr[i - 1]) {
BB_WARNING("matrix_nr[%d]/[%d]=0x%x/0x%x\n",
i - 1, i, ch_matrix_nr[i-1], ch_matrix_nr[i]);
return false;
}
}
}
}
/*{Nr}*/
for (i = 0; i < 8; i++) {
if (ch_matrix_nr[0] & BIT(i))
msb_bit = i;
}
nr = msb_bit + 1;
mask_tmp = (u8)halbb_gen_mask_from_0(nr);
if (ch_matrix_nr[0] != mask_tmp) {
BB_WARNING("ch_matrix_nr[0]=0x%x, mask_tmp = 0x%x\n",
ch_matrix_nr[0], mask_tmp);
return false;
}
ch_rpt_size->n_c = nc;
ch_rpt_size->n_r = nr;
/*
Length = {Data_bit} * {I,Q} * {Nc * Nr} * {N_tone(BW) / group_num}
= {8 or 16} * 2 * {1'number in ele_bitmap} * {N_tone} / {1/2/4/16}
*/
per_tone_size = ch_rpt_size->data_byte * 2 * nc * nr;
ch_rpt_size->per_tone_ch_rpt_size = per_tone_size;
ch_rpt_size->ch_info_rpt_len_legcy = per_tone_size >> ofst_table[cfg->ch_i_grp_num_non_he];
for (i = 0; i < 4; i++) {
//N_tone;
ch_rpt_size->ch_info_rpt_len[i] = per_tone_size >> ofst_table[cfg->ch_i_grp_num_non_he];
ch_rpt_size->ch_info_rpt_len_he[i] = per_tone_size >> ofst_table[cfg->ch_i_grp_num_he];
}
return true;
}
void halbb_cfg_ch_info_cr(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg)
{
struct bb_ch_info_cr_info *cr = &bb->bb_ch_rpt_i.bb_ch_info_cr_i;
u32 val_32;
BB_DBG(bb, DBG_IC_API,
"en_0/1=%d/%d, src=%d, cmprs=%d, grp_num_nhe/he=%d/%d\n",
cfg->ch_i_phy0_en, cfg->ch_i_phy1_en,
cfg->ch_i_data_src, cfg->ch_i_cmprs,
cfg->ch_i_grp_num_non_he, cfg->ch_i_grp_num_he);
BB_DBG(bb, DBG_IC_API,
"blk_start/end_=%d/%d, bitmap=0x%x, type=%d, seg_len=%d,\n",
cfg->ch_i_blk_start_idx, cfg->ch_i_blk_end_idx,
cfg->ch_i_ele_bitmap, cfg->ch_i_type, cfg->ch_i_seg_len);
if (!halbb_chk_ch_info_cr_valid(bb, cfg)) {
BB_DBG(bb, DBG_IC_API, "[%s] invalid\n", __func__);
//return;
}
/*CH-info Common Settings*/
val_32 = (cfg->ch_i_data_src & 0x1) |
((cfg->ch_i_cmprs & 0x1) << 1) |
((cfg->ch_i_grp_num_non_he & 0x3) << 2) |
((cfg->ch_i_grp_num_he & 0x3) << 4);
halbb_set_reg(bb, cr->ch_info_en_0, 0xfc, val_32);
halbb_set_reg(bb, cr->ele_bitmap, MASKDWORD, cfg->ch_i_ele_bitmap);
halbb_set_reg(bb, cr->ch_info_type, cr->ch_info_type_m, cfg->ch_i_type);
}
void halbb_cfg_ch_info_en(struct bb_info *bb, enum bb_ch_info_en_t en,
enum bb_physts_bitmap_t bitmap, enum phl_phy_idx phy_idx)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_cr_info *cr = &ch_rpt->bb_ch_info_cr_i;
u32 val_32;
BB_DBG(bb, DBG_IC_API, "[%s] en=%d, bitmap=0x%x\n", __func__, en, bitmap);
/*CH Report Enable*/
val_32 = (en == CH_INFO_DISABLE) ? 0 : 1;
if (phy_idx == HW_PHY_0)
halbb_set_reg(bb, cr->ch_info_en_0, BIT0, val_32);
else
halbb_set_reg(bb, cr->ch_info_en_0, BIT1, val_32);
/*Phy-sts IE 8 Enable*/
if(en == CH_INFO_DISABLE || en == CH_INFO_FROM_CH_STS)
halbb_physts_ie_bitmap_en(bb, bitmap, IE08_FTR_CH, false);
else
halbb_physts_ie_bitmap_en(bb, bitmap, IE08_FTR_CH, true);
}
void halbb_cfg_ch_info_buff(struct bb_info *bb, struct bb_ch_info_buf_cfg_info *cfg)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_cr_info *cr = &ch_rpt->bb_ch_info_cr_i;
u32 val_32;
BB_DBG(bb, DBG_IC_API, "[%s]\n", __func__);
val_32 = (cfg->ch_i_blk_start_idx & 0xf) |
((cfg->ch_i_blk_end_idx & 0xf) << 4);
halbb_set_reg(bb, cr->ch_info_en_0, 0xff00, val_32);
halbb_set_reg(bb, cr->seg_len, cr->seg_len_m, cfg->ch_i_seg_len);
}
void halbb_chanifo_self_test(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
BB_DBG(bb, DBG_IC_API, "[%s]ch_rpt = %d\n", __func__, ch_rpt->seg_idx_pre);
}
enum bb_ch_info_t halbb_ch_info_parsing(struct bb_info *bb, u8 *addr, u32 len,
u8 *rpt_buf,
struct bb_ch_rpt_hdr_info *hdr,
struct bb_phy_info_rpt *phy_info,
struct bb_ch_info_drv_rpt *drv)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
u32 last_seg_size = 0;
u32 len_tmp = 0;
drv->raw_data_len = len; /*@TEST_CH_SEG_LEN (12 * 8 = 96)*/
if (!addr)
return BB_CH_INFO_FAIL;
if (len == 0)
return BB_CH_INFO_FAIL;
halbb_mem_cpy(bb, hdr, addr, ch_rpt->ch_rpt_hdr_len);
if (hdr->set_valid == 0)
return BB_CH_INFO_FAIL;
drv->raw_data_len -= ch_rpt->ch_rpt_hdr_len;
addr += ch_rpt->ch_rpt_hdr_len;
BB_DBG(bb, DBG_IC_API, "[IN] skip=%d\n", ch_rpt->skip_ch_info);
BB_DBG(bb, DBG_IC_API, "[Hdr]lenth_curr: %d = %d - %d\n",
drv->raw_data_len, len, ch_rpt->ch_rpt_hdr_len); /*@88 = 96 - 8*/
if (hdr->is_pkt_end) {
/*SEG = N-1 (LAST SEG)*/
drv->seg_idx_curr = hdr->total_seg_num - 1; /*@3*/
ch_rpt->seg_idx_pre = drv->seg_idx_curr;/*@3*/
ch_rpt->seg_total_num = hdr->total_seg_num; /*4*/
ch_rpt->total_len = (hdr->total_len_m << 16 | hdr->total_len_l)
- ch_rpt->ch_rpt_hdr_len - ch_rpt->phy_info_len; /*@320 - 16 = 304*/
BB_DBG(bb, DBG_IC_API,
"[SEG_%d Last] seg_total_num=%d, total_len_l=%d, total_len=%d, remnant=%d, skip=%d\n",
drv->seg_idx_curr, ch_rpt->seg_total_num, hdr->total_len_l,
ch_rpt->total_len, ch_rpt->total_len_remnant, ch_rpt->skip_ch_info);
if (ch_rpt->skip_ch_info) {
ch_rpt->skip_ch_info = false;
ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/
return BB_CH_INFO_FAIL;
} else if (drv->seg_idx_curr != hdr->seq_num) {
BB_DBG(bb, DBG_IC_API, "[LAST][FAIL]drv_idx=%d != hdr_idx=%d\n",
drv->seg_idx_curr, hdr->seq_num);
ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/
ch_rpt->skip_ch_info = false;
return BB_CH_INFO_FAIL;
} else if (drv->raw_data_len < ch_rpt->total_len_remnant) {
BB_DBG(bb, DBG_IC_API, "[LAST][FAIL]raw_data_len=%d < total_len_remnant=%d\n",
drv->raw_data_len, ch_rpt->total_len_remnant);
ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/
ch_rpt->skip_ch_info = false;
return BB_CH_INFO_FAIL;
} else {
BB_DBG(bb, DBG_IC_API, "[LAST] len_remnant=%d\n", ch_rpt->total_len_remnant);
drv->raw_data_len = ch_rpt->total_len_remnant; /*Last remnant raw data*/
ch_rpt->total_len_remnant = ch_rpt->total_len; /*@304*/
halbb_mem_cpy(bb, rpt_buf, addr, drv->raw_data_len);
return BB_CH_INFO_LAST_SEG;
}
}
if (ch_rpt->skip_ch_info) {
BB_DBG(bb, DBG_IC_API, "[OUT]skip=%d\n", ch_rpt->skip_ch_info);
return BB_CH_INFO_FAIL;
}
BB_DBG(bb, DBG_IC_API, "seg_idx_pre=%d\n", ch_rpt->seg_idx_pre);
if (ch_rpt->seg_idx_pre == (hdr->total_seg_num - 1)) { /*@3 = 4 - 1*/
/*SEG = 0*/
drv->seg_idx_curr = 0;
ch_rpt->seg_idx_pre = 0;
//phy_info = (struct bb_phy_info_rpt *)addr;
halbb_mem_cpy(bb, phy_info, addr, ch_rpt->phy_info_len);
addr += ch_rpt->phy_info_len;
len_tmp = drv->raw_data_len;
drv->raw_data_len -= ch_rpt->phy_info_len; /*@80 = 88 - 8*/
BB_DBG(bb, DBG_IC_API, "[PHY_info]lenth_curr: %d = %d - %d\n",
drv->raw_data_len, len_tmp, ch_rpt->phy_info_len);
BB_DBG(bb, DBG_IC_API, "[PHY_info]RSSI= {%d, %d, %d}\n",
phy_info->rssi[0], phy_info->rssi[1], phy_info->rssi_avg);
BB_DBG(bb, DBG_IC_API,
"[SEG_0 Fist] total{num, len}={%d, %d}, remnant=%d, skip=%d\n",
ch_rpt->seg_total_num, ch_rpt->total_len, ch_rpt->total_len_remnant, ch_rpt->skip_ch_info);
if (drv->raw_data_len > ch_rpt->total_len_remnant) {
BB_DBG(bb, DBG_IC_API, "[FAIL]raw_data_len > total_len_remnant\n");
ch_rpt->skip_ch_info = true;
return BB_CH_INFO_FAIL;
} else if (phy_info->rsvd_0 != 0 || phy_info->rsvd_1 != 0 ||
phy_info->rsvd_2 != 0) {
BB_DBG(bb, DBG_IC_API, "[FAIL]rsvd_0,1,2: %d, %d, %d\n",
phy_info->rsvd_0, phy_info->rsvd_1, phy_info->rsvd_2);
ch_rpt->skip_ch_info = true;
return BB_CH_INFO_FAIL;
} else if (drv->seg_idx_curr != hdr->seq_num) {
BB_DBG(bb, DBG_IC_API, "[FAIL]drv_idx=%d != hdr_idx=%d\n",
drv->seg_idx_curr, hdr->seq_num);
ch_rpt->skip_ch_info = true;
return BB_CH_INFO_FAIL;
} else {
ch_rpt->total_len_remnant -= drv->raw_data_len;
halbb_mem_cpy(bb, rpt_buf, addr, drv->raw_data_len);
return BB_CH_INFO_SUCCESS;
}
} else {
/*SEG = 1~N-2*/
drv->seg_idx_curr = ch_rpt->seg_idx_pre + 1;
ch_rpt->seg_idx_pre = drv->seg_idx_curr;
if (drv->seg_idx_curr >= (hdr->total_seg_num - 1)) { /*@ >= 3*/
BB_DBG(bb, DBG_IC_API, "[FAIL]Los Last Seg\n");
ch_rpt->skip_ch_info = true;
return BB_CH_INFO_FAIL;
}
BB_DBG(bb, DBG_IC_API,
"[SEG_%d Mid] total{num, len}={%d, %d}, remnant=%d, skip=%d\n",
drv->seg_idx_curr, ch_rpt->seg_total_num, ch_rpt->total_len, ch_rpt->total_len_remnant, ch_rpt->skip_ch_info);
BB_DBG(bb, DBG_IC_API, "lenth_curr: %d\n", drv->raw_data_len); /*@88 = 96 - 8*/
if (drv->raw_data_len > ch_rpt->total_len_remnant) {
BB_DBG(bb, DBG_IC_API, "[FAIL]raw_data_len > total_len_remnant\n");
ch_rpt->skip_ch_info = true;
return BB_CH_INFO_FAIL;
} else if (drv->seg_idx_curr != hdr->seq_num) {
BB_DBG(bb, DBG_IC_API, "[FAIL]drv_idx=%d != hdr_idx=%d\n",
drv->seg_idx_curr, hdr->seq_num);
ch_rpt->skip_ch_info = true;
return BB_CH_INFO_FAIL;
} else {
ch_rpt->total_len_remnant -= drv->raw_data_len;
halbb_mem_cpy(bb, rpt_buf, addr, drv->raw_data_len);
return BB_CH_INFO_SUCCESS;
}
}
}
void halbb_ch_info_bbcr_init(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i;
BB_DBG(bb, DBG_IC_API, "[%s]\n", __func__);
cfg->ch_i_data_src = 0;
cfg->ch_i_cmprs = 1;
cfg->ch_i_grp_num_non_he = 3;
cfg->ch_i_grp_num_he = 3;
cfg->ch_i_blk_start_idx = 9;
cfg->ch_i_blk_end_idx = 10;
cfg->ch_i_ele_bitmap = 0x303; /*Nr X Nc: 2 X 2*/
cfg->ch_i_type = 1;
cfg->ch_i_seg_len = 0;
halbb_cfg_ch_info_cr(bb, cfg);
}
void halbb_ch_info_init(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_physts_info *physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i;
struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i;
halbb_ch_info_bbcr_init(bb);
ch_rpt->ch_rpt_hdr_len = sizeof(struct bb_ch_rpt_hdr_info); /*8852A: 8Byte*/
ch_rpt->phy_info_len = sizeof(struct bb_phy_info_rpt); /*8852A: 8Byte*/
ch_rpt->skip_ch_info = true;
//Init Parameter
buf->ch_info_buf_len = 1024;
physts->bitmap_type_auto_en = true;
BB_DBG(bb, DBG_IC_API, "[%s] hdr_len = %d, phy_info_len=%d\n", __func__, ch_rpt->ch_rpt_hdr_len, ch_rpt->phy_info_len);
}
void halbb_ch_info_print_buf(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
u16 i = 0;
u8 *buf_tmp;
if (!ch_rpt->test_buf)
return;
buf_tmp = ch_rpt->test_buf;
BB_DBG(bb, DBG_IC_API, "----------------------------\n");
for (i = 0; i < ((TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN) >> 3); i++) {
BB_DBG(bb, DBG_IC_API, "[%02d] 0x%016llx\n", i, *(u64 *)buf_tmp);
buf_tmp += 8;
if (i == 9 || i == 20 || i == 31 || i == 37 || i == 42)
BB_DBG(bb, DBG_IC_API, "----------------------------\n");
}
BB_DBG(bb, DBG_IC_API, "----------------------------\n");
}
void halbb_ch_info_buf_rls(struct bb_info *bb)
{
struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i;
if (!buf->octet)
return;
BB_DBG(bb, DBG_IC_API,"[%s]\n", __func__);
halbb_mem_free(bb, buf->octet, buf->ch_info_buf_len);
buf->octet = 0;
}
bool halbb_ch_info_buf_alloc(struct bb_info *bb)
{
struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i;
if (buf->octet)
return true;
BB_DBG(bb, DBG_IC_API,"[%s]\n", __func__);
buf->octet = (s16 *)halbb_mem_alloc(bb, buf->ch_info_buf_len);
if (!buf->octet)
return false;
return true;
}
void halbb_ch_info_reset(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
if (ch_rpt->test_buf)
halbb_mem_set(bb, ch_rpt->test_buf, 0, (TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN));
}
void halbb_ch_info_deinit(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
halbb_ch_info_buf_rls(bb);
if (ch_rpt->test_buf)
halbb_mem_free(bb, ch_rpt->test_buf, (TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN));
}
void halbb_ch_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_raw_info *buf = &ch_rpt->bb_ch_info_raw_i;
struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i;
struct bb_ch_rpt_size_info *ch_rpt_size = &ch_rpt->bb_ch_rpt_size_i;
struct bb_ch_info_physts_info *ch_physts = &ch_rpt->bb_ch_info_physts_i;
struct bb_pkt_cnt_su_store_info *store = &bb->bb_cmn_rpt_i.bb_pkt_cnt_su_store_i;
struct bb_ch_rpt_hdr_info ch_rpt_hdr = {0};
struct bb_phy_info_rpt phy_rpt_in;
struct bb_ch_rpt_hdr_info hdr; /*output*/
struct bb_phy_info_rpt phy_rpt; /*output*/
struct bb_ch_info_drv_rpt drv_rpt; /*output*/
enum bb_ch_info_t rpt; /*output*/
enum bb_physts_bitmap_t bitmap_type;
u8 grp_num_tab[4] = {1, 2, 4, 16};
bool val_bool;
u8 seg_idx;
u8 *addr, *addr_tmp, *addr_ori;
u32 len = TEST_CH_SEG_LEN; /*Byte*/
u32 val[11] = {0};
u16 i = 0;
u16 tone_num = 0;
halbb_mem_set(bb, &phy_rpt_in, 0, sizeof(phy_rpt_in));
halbb_mem_set(bb, &hdr, 0, sizeof(hdr));
halbb_mem_set(bb, &phy_rpt, 0, sizeof(phy_rpt));
halbb_mem_set(bb, &drv_rpt, 0, sizeof(drv_rpt));
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{self_test}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{print}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{rst}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{test} {seg_idx:0~3}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"trig_psts\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfg show\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfg para0 {0: auto, 6~7: HE/VHT_MU, 12~15: Lgcy/HT/VHT/HE}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfg para1 {0/1: 1/2 Byte} {grp: 0~3:1/2/4/16} {H_map(Hex)}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfg para2 {seg_len}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfg para3 {0:LS, 1:CS}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cfg blk {start_idx} {end_idx}\n");
return;
}
if (_os_strcmp(input[1], "self_test") == 0) {
halbb_chanifo_self_test(bb);
} else if (_os_strcmp(input[1], "print") == 0) {
halbb_ch_info_print_buf(bb);
} else if (_os_strcmp(input[1], "rst") == 0) {
halbb_ch_info_reset(bb);
} else if (_os_strcmp(input[1], "trig_physts") == 0) {
if(!halbb_ch_info_buf_alloc(bb)) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Buff alloc fail\n");
return;
}
if (ch_physts->bitmap_type_auto_en) {
if (store->he_pkt_not_zero)
bitmap_type = HE_PKT;
else if (store->vht_pkt_not_zero)
bitmap_type = VHT_PKT;
else if (store->ht_pkt_not_zero)
bitmap_type = HT_PKT;
else
bitmap_type = LEGACY_OFDM_PKT;
} else {
bitmap_type = ch_physts->force_bitmap_type;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Auto Type=%d\n", ch_physts->bitmap_type_auto_en);
val_bool = halbb_ch_info_wait_from_physts(bb, 100, 500, bitmap_type);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Trigger Type[%s], BW=%d, success=%d\n",
bb_physts_bitmap_type_t[bitmap_type],
20 << bb->hal_com->band[0].cur_chandef.bw, val_bool);
if (!val_bool)
return;
tone_num = HALBB_DIV(ch_physts->ch_info_len, ch_rpt_size->per_tone_ch_rpt_size);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[CH-Info Rpt][%s] len:%d, per_tone_size=%d, tone_num=%d\n",
bb_physts_bitmap_type_t[ch_physts->bitmap_type_rpt],
ch_physts->ch_info_len, ch_rpt_size->per_tone_ch_rpt_size,
tone_num);
#if 0
if (buf->octet &&
buf->ch_info_buf_len > ch_physts->ch_info_len &&
ch_physts->ch_info_len != 0) {
halbb_print_buff_64(bb, (u8*)buf->octet, ch_physts->ch_info_len);
}
#endif
} else if (_os_strcmp(input[1], "cfg") == 0) {
for (i = 0; i <= 4; i++)
HALBB_SCAN(input[3 + i], DCMD_DECIMAL, &val[i]);
if (_os_strcmp(input[2], "show") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"src=%d, cmprs=%d, grp_num_nhe/he=%d/%d\n",
cfg->ch_i_data_src, cfg->ch_i_cmprs,
cfg->ch_i_grp_num_non_he, cfg->ch_i_grp_num_he);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"blk_start/end_=%d/%d, bitmap=0x%x, type=%d, seg_len=%d\n",
cfg->ch_i_blk_start_idx, cfg->ch_i_blk_end_idx,
cfg->ch_i_ele_bitmap, cfg->ch_i_type, cfg->ch_i_seg_len);
return;
} else if (_os_strcmp(input[2], "para0") == 0) {
if (val[0] == 0) {
ch_physts->bitmap_type_auto_en = true;
return;
}
ch_physts->bitmap_type_auto_en = false;
ch_physts->force_bitmap_type = (enum bb_physts_bitmap_t)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"force_bitmap_type=%s\n",
bb_physts_bitmap_type_t[ch_physts->force_bitmap_type]);
} else if (_os_strcmp(input[2], "para1") == 0) {
HALBB_SCAN(input[5], DCMD_HEX, &val[2]);
cfg->ch_i_cmprs = (bool)val[0];
if (val[1] < 4) {
cfg->ch_i_grp_num_non_he = (u8)val[1];
cfg->ch_i_grp_num_he = (u8)val[1];
}
cfg->ch_i_ele_bitmap = val[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"data_wl=%d Byte, grp_num=%d, H_map=0x%x\n",
1 << cfg->ch_i_cmprs, grp_num_tab[val[1]],
cfg->ch_i_ele_bitmap);
} else if (_os_strcmp(input[2], "para2") == 0) {
cfg->ch_i_seg_len = (u8)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"seg_len=%d\n",
cfg->ch_i_seg_len);
} else if (_os_strcmp(input[2], "para3") == 0) {
cfg->ch_i_data_src = (bool)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"src=%d\n", cfg->ch_i_data_src);
} else if (_os_strcmp(input[2], "blk") == 0) {
cfg->ch_i_blk_start_idx = (u8)val[0];
cfg->ch_i_blk_end_idx = (u8)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"blk_start/end_=%d/%d\n",
cfg->ch_i_blk_start_idx, cfg->ch_i_blk_end_idx);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
halbb_cfg_ch_info_cr(bb, cfg);
} else if (_os_strcmp(input[1], "test") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
seg_idx = (u8)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[SEG:%d] Input\n", seg_idx);
/*Rpt Buff*/
if (!ch_rpt->test_buf)
ch_rpt->test_buf = (u8 *)halbb_mem_alloc(bb, (TEST_CH_INFO_MAX_SEG * TEST_CH_SEG_LEN));
/*Data Buff*/
addr = (u8 *)halbb_mem_alloc(bb, len);
addr_ori = addr;
if (!addr)
return;
/*HDR Info*/
/*seg_0:[2(hdr) + 10(data)] + seg_1:11(data) + seg_2:11(data) + seg_3:6(data) = 40, 40*8=320*/
ch_rpt_hdr.total_len_l = 320;
ch_rpt_hdr.total_seg_num = TEST_CH_INFO_MAX_SEG;
ch_rpt_hdr.set_valid = 1;
ch_rpt_hdr.segment_size = TEST_CH_SEG_LEN >> 3;
ch_rpt_hdr.seq_num= seg_idx;
if (seg_idx == TEST_CH_INFO_MAX_SEG - 1) {
ch_rpt_hdr.is_pkt_end = 1;
} else {
ch_rpt_hdr.is_pkt_end = 0;
}
halbb_mem_cpy(bb, addr, &ch_rpt_hdr, ch_rpt->ch_rpt_hdr_len);
addr += ch_rpt->ch_rpt_hdr_len;
if (seg_idx == 0) {
phy_rpt_in.rssi[0] = 50;
phy_rpt_in.rssi[1] = 70;
phy_rpt_in.rssi_avg = 60;
phy_rpt_in.rsvd_0 = 0;
phy_rpt_in.rsvd_1 = 0;
phy_rpt_in.rsvd_2 = 0;
halbb_mem_cpy(bb, addr, &phy_rpt_in, ch_rpt->phy_info_len);
addr += ch_rpt->phy_info_len;
ch_rpt->test_buf_curr = ch_rpt->test_buf;
}
if (seg_idx == TEST_CH_INFO_MAX_SEG - 1) {
/*SEG3 (LAST)*/
for (i = 0; i < (TEST_CH_SEG_LEN - 8 - 40); i++) {
*addr = (u8)i;
addr++;
}
} else if (seg_idx == 0) {
/*SEG 0*/
for (i = 0; i < (TEST_CH_SEG_LEN - 16); i++) {
*addr = (u8)i;
addr++;
}
} else {
/*SEG 1,2*/
for (i = 0; i < (TEST_CH_SEG_LEN - 8); i++) {
*addr = (u8)i;
addr++;
}
}
addr_tmp = addr_ori;
for (i = 0; i < (TEST_CH_SEG_LEN >> 3); i++) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%02d] 0x%016llx\n", i, *(u64 *)addr_tmp);
addr_tmp += 8;
}
rpt = halbb_ch_info_parsing(bb, addr_ori, len, ch_rpt->test_buf_curr, &hdr, &phy_rpt, &drv_rpt);
ch_rpt->raw_data_len_acc += drv_rpt.raw_data_len;
ch_rpt->test_buf_curr += drv_rpt.raw_data_len;
if (rpt == BB_CH_INFO_SUCCESS) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Result] Success\n");
} else {
if (rpt == BB_CH_INFO_LAST_SEG) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Result] Success, Last Seg\n");
halbb_ch_info_print_buf(bb);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Result] Fail\n");
}
halbb_ch_info_reset(bb);
ch_rpt->raw_data_len_acc = 0;
ch_rpt->test_buf_curr = ch_rpt->test_buf;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[ACC] remnant=%d, raw_data_len_acc=%d\n",
ch_rpt->total_len_remnant, ch_rpt->raw_data_len_acc);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[SEG] all_len=%d = Hdr_len + raw_data_len=%d\n",
len, drv_rpt.raw_data_len);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[SEG] total_len=%d, seg_size=%d, end=%d, sts0_evm=%d, seq_num=%d\n",
hdr.total_len_l, hdr.segment_size, hdr.is_pkt_end, hdr.sts0_evm, hdr.seq_num);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[IN] SEG[%d]: rssi{0,1,avg}={%02d,%02d,%02d}, sts1_evm=%d, rsvd{0,1,2}={%d,%d,%d}\n",
ch_rpt_hdr.seq_num,
phy_rpt_in.rssi[0], phy_rpt_in.rssi[1],
phy_rpt_in.rssi_avg, (phy_rpt_in.sts1_evm_m << 4 | phy_rpt_in.sts1_evm_l) ,
phy_rpt_in.rsvd_0, phy_rpt_in.rsvd_1,
phy_rpt_in.rsvd_2);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[OUT] SEG[%d]: rssi{0,1,avg}={%02d,%02d,%02d}, sts1_evm=%d, rsvd{0,1,2}={%d,%d,%d}\n\n",
drv_rpt.seg_idx_curr,
phy_rpt.rssi[0], phy_rpt.rssi[1],
phy_rpt.rssi_avg, (phy_rpt.sts1_evm_m << 4 | phy_rpt.sts1_evm_l),
phy_rpt.rsvd_0, phy_rpt.rsvd_1,
phy_rpt.rsvd_2);
halbb_mem_free(bb, addr_ori, len);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
}
}
void halbb_cr_cfg_ch_info_init(struct bb_info *bb)
{
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_cr_info *cr = &ch_rpt->bb_ch_info_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->ch_info_en_0 = INTF_R_CH_INFO_EN_P0_A;
cr->ele_bitmap = INTF_R_ELE_BITMAP_A;
cr->ch_info_type = CH_INFO_TYPE_A;
cr->ch_info_type_m = CH_INFO_TYPE_A_M;
cr->seg_len = CH_INFO_SEG_LEN_A;
cr->seg_len_m = CH_INFO_SEG_LEN_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->ch_info_en_0 = INTF_R_CH_INFO_EN_P0_C;
cr->ele_bitmap = INTF_R_ELE_BITMAP_C;
cr->ch_info_type = CH_INFO_TYPE_C;
cr->ch_info_type_m = CH_INFO_TYPE_C_M;
cr->seg_len = CH_INFO_SEG_LEN_C;
cr->seg_len_m = CH_INFO_SEG_LEN_C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ch_info.c
|
C
|
agpl-3.0
| 26,526
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CH_INFO_H__
#define __HALBB_CH_INFO_H__
#ifdef HALBB_CH_INFO_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
#define TEST_CH_INFO_MAX_SEG 4
#define TEST_CH_SEG_LEN (12 * 8) /*Byte*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
enum bb_ch_info_state_type {
CH_RPT_START_TO_WAIT = 0,
CH_RPT_GETTED = 1
};
struct bb_ch_info_physts_info {
enum bb_ch_info_state_type ch_info_state;
enum bb_physts_bitmap_t force_bitmap_type; /*force setting*/
enum bb_physts_bitmap_t bitmap_type_rpt; /*report*/
bool bitmap_type_auto_en;
u16 ch_info_len;
};
struct bb_ch_info_raw_info {
s16 *octet;
u32 ch_info_buf_len; /*Byte*/
};
struct bb_ch_info_cr_info {
u32 ch_info_en_0;
u32 ele_bitmap;
u32 ch_info_type;
u32 ch_info_type_m;
u32 seg_len;
u32 seg_len_m;
};
struct bb_ch_rpt_size_info {
u8 data_byte;
u8 n_c;
u8 n_r;
u16 n_tone;
u8 n_group;
u16 ch_info_rpt_len_legcy; /*Lgacy; Byte; ch_info rpt length calculated by BB CR configuration*/
u16 ch_info_rpt_len[4]; /*HT/VHT 20,40,80; Byte; ch_info rpt length calculated by BB CR configuration*/
u16 ch_info_rpt_len_he[4]; /*HE 20,40,80; Byte; ch_info rpt length calculated by BB CR configuration*/
u16 per_tone_ch_rpt_size;
};
struct bb_ch_rpt_info {
u8 seg_idx_pre;
u8 seg_total_num;
u32 total_len; /*Raw data length(Unit: byte) = total_len - 16*/
u32 total_len_remnant;
u16 ch_rpt_hdr_len;
u16 phy_info_len;
bool skip_ch_info;
u32 raw_data_len_acc;
u8 *test_buf;
u8 *test_buf_curr;
struct bb_ch_info_cr_cfg_info bb_ch_info_cr_cfg_i;
struct bb_ch_info_cr_info bb_ch_info_cr_i; /*CR callback table*/
struct bb_ch_rpt_size_info bb_ch_rpt_size_i;
struct bb_ch_info_raw_info bb_ch_info_raw_i;
struct bb_ch_info_physts_info bb_ch_info_physts_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
bool halbb_ch_info_wait_from_physts(struct bb_info *bb, u32 dly, u32 dly_max,
enum bb_physts_bitmap_t type);
void halbb_ch_info_buf_rls(struct bb_info *bb);
bool halbb_ch_info_buf_alloc(struct bb_info *bb);
void halbb_ch_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_ch_info_deinit(struct bb_info *bb);
void halbb_ch_info_init(struct bb_info *bb);
void halbb_cr_cfg_ch_info_init(struct bb_info *bb);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ch_info.h
|
C
|
agpl-3.0
| 3,442
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CH_INFO_EX_H__
#define __HALBB_CH_INFO_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_ch_info_en_t {
CH_INFO_DISABLE = 0,
CH_INFO_FROM_PHY_STS = 1,
CH_INFO_FROM_CH_STS = 2
};
enum bb_ch_info_t {
BB_CH_INFO_SUCCESS = 0,
BB_CH_INFO_LAST_SEG,
BB_CH_INFO_FAIL,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_ch_info_cr_cfg_info {
bool ch_i_phy0_en;
bool ch_i_phy1_en;
bool ch_i_data_src; /*0~1: CH-estimation, CH-smoothing*/
bool ch_i_cmprs; /*0~1: 8/16 bit*/
u8 ch_i_grp_num_non_he; /*0~3: 1/2/4/16*/
u8 ch_i_grp_num_he; /*0~3: 1/2/4/16*/
u8 ch_i_blk_start_idx; /*1~10*/
u8 ch_i_blk_end_idx; /*1~10*/
u32 ch_i_ele_bitmap;
bool ch_i_type; /*0~1: L-CH, MIMO-CH*/
u8 ch_i_seg_len; /*0~3: 12/28/60/124 (8byte)*/
};
struct bb_ch_info_buf_cfg_info {
u8 ch_i_blk_start_idx; /*1~10*/
u8 ch_i_blk_end_idx; /*1~10*/
u8 ch_i_seg_len; /*0~3: 12/28/60/124 (8byte)*/
};
struct bb_ch_rpt_hdr_info {
u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 total_len_m:1;
u8 total_seg_num:7;
#else
u8 total_seg_num:7;
u8 total_len_m:1;
#endif
u8 avg_noise_pow;
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 is_pkt_end:1;
u8 set_valid:1;
u8 n_rx:3;
u8 n_sts:3;
#else
u8 n_sts:3;
u8 n_rx:3;
u8 set_valid:1;
u8 is_pkt_end:1;
#endif
u8 segment_size; /*unit (8Byte)*/
u8 sts0_evm;
u8 seq_num;
};
struct bb_phy_info_rpt {
u8 rssi[2];
u16 rsvd_0;
u8 rssi_avg;
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 rxsc:4;
u8 sts1_evm_l:4;
u8 sts1_evm_m:4;
u8 rsvd_1:4;
#else
u8 rsvd_1:4;
u8 sts1_evm_m:4;
u8 sts1_evm_l:4;
u8 rxsc:4;
#endif
u8 rsvd_2;
};
struct bb_ch_info_drv_rpt {
u32 raw_data_len;
u8 seg_idx_curr;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_cfg_ch_info_cr(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg);
void halbb_cfg_ch_info_en(struct bb_info *bb, enum bb_ch_info_en_t en,
enum bb_physts_bitmap_t bitmap, enum phl_phy_idx phy_idx);
void halbb_cfg_ch_info_buff(struct bb_info *bb, struct bb_ch_info_buf_cfg_info *cfg);
enum bb_ch_info_t halbb_ch_info_parsing(struct bb_info *bb, u8 *addr, u32 len,
u8 *rpt_buf,
struct bb_ch_rpt_hdr_info *hdr,
struct bb_phy_info_rpt *phy_info,
struct bb_ch_info_drv_rpt *drv);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ch_info_ex.h
|
C
|
agpl-3.0
| 3,453
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#if 1
void halbb_print_hist_2_buf_u8(struct bb_info *bb, u8 *val, u16 len, char *buf,
u16 buf_size)
{
if (len == PHY_HIST_SIZE) {
halbb_snprintf(buf, buf_size,
"[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
val[0], val[1], val[2], val[3], val[4],
val[5], val[6], val[7], val[8], val[9],
val[10], val[11]);
} else if (len == (PHY_HIST_SIZE - 1)) {
halbb_snprintf(buf, buf_size,
"[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
val[0], val[1], val[2], val[3], val[4],
val[5], val[6], val[7], val[8], val[9],
val[10]);
}
}
void halbb_print_hist_2_buf(struct bb_info *bb, u16 *val, u16 len, char *buf,
u16 buf_size)
{
if (len == PHY_HIST_SIZE) {
halbb_snprintf(buf, buf_size,
"[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
val[0], val[1], val[2], val[3], val[4],
val[5], val[6], val[7], val[8], val[9],
val[10], val[11]);
} else if (len == (PHY_HIST_SIZE - 1)) {
halbb_snprintf(buf, buf_size,
"[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
val[0], val[1], val[2], val[3], val[4],
val[5], val[6], val[7], val[8], val[9],
val[10]);
}
}
void halbb_rx_pop_hist(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
u8 pop_idx = 0;
bool is_cck = cmn_rpt->is_cck_rate;
if (is_cck)
pop_idx = bb->bb_physts_i.bb_physts_rslt_0_i.pop_idx_cck;
else
pop_idx = bb->bb_physts_i.bb_physts_rslt_1_i.pop_idx;
if (pop_idx >= POP_HIST_SIZE)
pop_idx = POP_HIST_SIZE - 1;
if (is_cck)
cmn_rpt->bb_physts_pop_i.pop_hist_cck[pop_idx]++;
else
cmn_rpt->bb_physts_pop_i.pop_hist_ofdm[pop_idx]++;
}
void halbb_rx_pkt_cnt_rpt_beacon(struct bb_info *bb, struct physts_rxd *desc)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
if (desc->user_i[0].is_bcn) {
cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon++;
cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate= desc->data_rate;
}
}
void halbb_rx_pkt_cnt_rpt_reset(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
//halbb_mem_set(bb, cmn_rpt, 0, sizeof(struct bb_cmn_rpt_info));
cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon = 0;
halbb_mem_set(bb, &cmn_rpt->bb_pkt_cnt_all_i, 0, sizeof(struct bb_pkt_cnt_cap_info));
halbb_mem_set(bb, &cmn_rpt->bb_pkt_cnt_su_i, 0, sizeof(struct bb_pkt_cnt_su_info));
halbb_mem_set(bb, &cmn_rpt->bb_rssi_su_acc_i, 0, sizeof(struct bb_rssi_su_acc_info));
halbb_mem_set(bb, &cmn_rpt->bb_physts_hist_i, 0, sizeof(struct bb_physts_hist_info));
halbb_mem_set(bb, &cmn_rpt->bb_physts_acc_i, 0, sizeof(struct bb_physts_acc_info));
/*[POP cnt reset]*/
halbb_mem_set(bb, &cmn_rpt->bb_physts_pop_i, 0, sizeof(struct bb_physts_pop_info));
/*[MU]*/
halbb_mem_set(bb, &cmn_rpt->bb_pkt_cnt_mu_i, 0, sizeof(struct bb_pkt_cnt_mu_info));
halbb_mem_set(bb, &cmn_rpt->bb_rssi_mu_acc_i, 0, sizeof(struct bb_rssi_mu_acc_info));
}
#define CMN_RPT_MU
#ifdef CMN_RPT_MU
u16 halbb_get_plurality_rx_rate_mu(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i;
u16 max_num_tmp = 0;
u16 rx_rate_plurality = 0;
u16 i = 0;
u16 *pkt_cnt_tmp;
u8 rate_num_tmp;
u16 ofst_mode = 0;
u16 ofst_ss = 0;
u16 idx = 0;
bool plurality_is_legacy_rate = true;
if (pkt_cnt->pkt_cnt_all == 0) {
return rx_rate_plurality;
}
//BB_DBG(bb, DBG_CMN, "cnt_t= (%d)\n", pkt_cnt->pkt_cnt_all);
/*HT, VHT, HE*/
if (pkt_cnt->he_pkt_not_zero) {
pkt_cnt_tmp = pkt_cnt->pkt_cnt_he;
rate_num_tmp = HE_RATE_NUM;
ofst_mode = BB_HE_1SS_MCS0;
} else if (pkt_cnt->vht_pkt_not_zero) {
pkt_cnt_tmp = pkt_cnt->pkt_cnt_vht;
rate_num_tmp = VHT_RATE_NUM;
ofst_mode = BB_VHT_1SS_MCS0;
} else {
return rx_rate_plurality;
}
for (i = 0; i < rate_num_tmp; i++) {
if (pkt_cnt_tmp[i] >= max_num_tmp) {
max_num_tmp = pkt_cnt_tmp[i];
idx = i;
plurality_is_legacy_rate = false;
}
}
if (plurality_is_legacy_rate)
return rx_rate_plurality;
//BB_DBG(bb, DBG_CMN, "[T]idx_ori= (%d)\n", idx);
ofst_ss = idx / HE_VHT_NUM_MCS;
if (ofst_ss >= 0) /*>=2SS*/
idx -= (ofst_ss * HE_VHT_NUM_MCS);
//BB_DBG(bb, DBG_CMN, "ofst_ss= (%d), idx=%d\n", ofst_ss, idx);
rx_rate_plurality = ofst_mode + (ofst_ss << 4) + idx;
//BB_DBG(bb, DBG_CMN, "[T]rx_rate_plurality= (0x%x), max_num_tmp=%d\n", rx_rate_plurality, max_num_tmp);
return rx_rate_plurality;
}
void halbb_mu_rate_idx_generate(struct bb_info *bb, struct physts_rxd *desc, u8 bw_idx, struct bb_rate_info *ra_i)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
struct bb_physts_rslt_13_info *psts_13 = &physts->bb_physts_rslt_13_i;
u8 user = desc->user_num;
if (user > MU_USER_MAX) {
BB_WARNING("[%s] user = %d\n", __func__, user);
return;
}
ra_i->gi_ltf = desc->gi_ltf;
ra_i->bw = bw_idx;
ra_i->ss = psts_13->bb_physts_uer_info[user].n_sts;
ra_i->idx = psts_13->bb_physts_uer_info[user].mcs;
if (psts_h->ie_map_type == VHT_MU) {
ra_i->mode = BB_VHT_MODE;
ra_i->rate_idx = GEN_VHT_RATE_IDX(ra_i->ss, ra_i->idx);
} else if (psts_h->ie_map_type == HE_MU) {
ra_i->mode = BB_HE_MODE;
ra_i->rate_idx = GEN_HE_RATE_IDX(ra_i->ss, ra_i->idx);
} else {
BB_WARNING("[%s] ie_map_type = %d", __func__, psts_h->ie_map_type);
return;
}
ra_i->rate_idx_all = ra_i->rate_idx | (((u16)desc->gi_ltf & 0xf) << 12);
}
void halbb_show_rssi_and_rate_distribution_mu(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i;
struct bb_rssi_mu_acc_info *acc = &cmn_rpt->bb_rssi_mu_acc_i;
struct bb_rssi_mu_avg_info *avg = &cmn_rpt->bb_rssi_mu_avg_i;
u8 rssi_avg_tmp = 0;
u8 rssi_tmp[HALBB_MAX_PATH];
u16 pkt_cnt_ss = 0;
u8 i = 0, j =0;
u8 rate_num = bb->num_rf_path, ss_ofst = 0;
avg->rssi_t_avg = (u8)HALBB_DIV(acc->rssi_t_avg_acc, pkt_cnt->pkt_cnt_all);
for (i = 0; i < HALBB_MAX_PATH; i++) {
if (i >= bb->num_rf_path)
break;
avg->rssi_t[i] = (u8)HALBB_DIV(acc->rssi_t_acc[i], pkt_cnt->pkt_cnt_all);
}
/*@======VHT==========================================================*/
if (pkt_cnt->vht_pkt_not_zero) {
for (i = 0; i < rate_num; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
for (j = 0; j < HE_VHT_NUM_MCS ; j++) {
pkt_cnt_ss += pkt_cnt->pkt_cnt_vht[ss_ofst + j];
}
if (pkt_cnt_ss == 0) {
rssi_avg_tmp = 0;
rssi_tmp[0] = 0;
rssi_tmp[1] = 0;
} else {
rssi_avg_tmp = avg->rssi_t_avg >> 1;
rssi_tmp[0] = avg->rssi_t[0] >> 1;
rssi_tmp[1] = avg->rssi_t[1] >> 1;
}
BB_DBG(bb, DBG_CMN,
"*[MU] VHT %d-S RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1],
pkt_cnt_ss,
pkt_cnt->pkt_cnt_vht[ss_ofst + 0],
pkt_cnt->pkt_cnt_vht[ss_ofst + 1],
pkt_cnt->pkt_cnt_vht[ss_ofst + 2],
pkt_cnt->pkt_cnt_vht[ss_ofst + 3],
pkt_cnt->pkt_cnt_vht[ss_ofst + 4],
pkt_cnt->pkt_cnt_vht[ss_ofst + 5],
pkt_cnt->pkt_cnt_vht[ss_ofst + 6],
pkt_cnt->pkt_cnt_vht[ss_ofst + 7],
pkt_cnt->pkt_cnt_vht[ss_ofst + 8],
pkt_cnt->pkt_cnt_vht[ss_ofst + 9],
pkt_cnt->pkt_cnt_vht[ss_ofst + 10],
pkt_cnt->pkt_cnt_vht[ss_ofst + 11]);
pkt_cnt_ss = 0;
}
}
/*@======HE==========================================================*/
if (pkt_cnt->he_pkt_not_zero) {
for (i = 0; i < rate_num; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
for (j = 0; j < HE_VHT_NUM_MCS ; j++) {
pkt_cnt_ss += pkt_cnt->pkt_cnt_he[ss_ofst + j];
}
if (pkt_cnt_ss == 0) {
rssi_avg_tmp = 0;
rssi_tmp[0] = 0;
rssi_tmp[1] = 0;
} else {
rssi_avg_tmp = avg->rssi_t_avg >> 1;
rssi_tmp[0] = avg->rssi_t[0] >> 1;
rssi_tmp[1] = avg->rssi_t[1] >> 1;
}
BB_DBG(bb, DBG_CMN,
"*[MU] HE %d-SS RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1],
pkt_cnt_ss,
pkt_cnt->pkt_cnt_he[ss_ofst + 0],
pkt_cnt->pkt_cnt_he[ss_ofst + 1],
pkt_cnt->pkt_cnt_he[ss_ofst + 2],
pkt_cnt->pkt_cnt_he[ss_ofst + 3],
pkt_cnt->pkt_cnt_he[ss_ofst + 4],
pkt_cnt->pkt_cnt_he[ss_ofst + 5],
pkt_cnt->pkt_cnt_he[ss_ofst + 6],
pkt_cnt->pkt_cnt_he[ss_ofst + 7],
pkt_cnt->pkt_cnt_he[ss_ofst + 8],
pkt_cnt->pkt_cnt_he[ss_ofst + 9],
pkt_cnt->pkt_cnt_he[ss_ofst + 10],
pkt_cnt->pkt_cnt_he[ss_ofst + 11]);
pkt_cnt_ss = 0;
}
}
/*@======SC_BW========================================================*/
if (pkt_cnt->sc20_occur) {
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG(bb, DBG_CMN,
"*[MU][Low BW 20M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_sc20[ss_ofst + 0],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 1],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 2],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 3],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 4],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 5],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 6],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 7],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 8],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 9],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 10],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 11]);
}
}
if (pkt_cnt->sc40_occur) {
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG(bb, DBG_CMN,
"*[MU][Low BW 40M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_sc40[ss_ofst + 0],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 1],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 2],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 3],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 4],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 5],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 6],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 7],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 8],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 9],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 10],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 11]);
}
}
}
void halbb_rx_pkt_mu_cnt_rpt(struct bb_info *bb, struct physts_rxd *desc, enum channel_width rx_bw)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
enum channel_width bw_curr;
u8 band_idx;
u8 ofst = rate_i->idx;
if (rate_i->mode <= BB_HT_MODE) {
BB_WARNING("[%s] mode = %d", __func__, rate_i->mode);
return;
}
pkt_cnt->pkt_cnt_all++;
if (rate_i->ss == 1)
pkt_cnt->pkt_cnt_1ss++;
else if (rate_i->ss == 2)
pkt_cnt->pkt_cnt_2ss++;
band_idx = (desc->phy_idx == HW_PHY_0) ? 0 : 1;
bw_curr = bb->hal_com->band[band_idx].cur_chandef.bw;
rx_bw = bw_curr; /*Will be removed, just for tmp debug using*/
if (rate_i->ss >= 2)
ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1));
if (rate_i->mode == BB_VHT_MODE) {
pkt_cnt->vht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1);
if (rx_bw == bw_curr) {
pkt_cnt->pkt_cnt_vht[ofst]++;
return;
}
} else if (rate_i->mode == BB_HE_MODE) {
pkt_cnt->he_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1);
if (rx_bw == bw_curr) {
pkt_cnt->pkt_cnt_he[ofst]++;
return;
}
}
/*SC BW*/
if (rx_bw != bw_curr) {
ofst = NOT_GREATER(ofst, LOW_BW_RATE_NUM - 1);
if (rx_bw == CHANNEL_WIDTH_20) {
pkt_cnt->pkt_cnt_sc20[ofst]++;
pkt_cnt->sc20_occur = true;
} else {
pkt_cnt->pkt_cnt_sc40[ofst]++;
pkt_cnt->sc40_occur = true;
}
}
}
void halbb_rx_pkt_mu_rssi_statistic(struct bb_info *bb)
{
struct bb_physts_rslt_hdr_info *psts_h = &bb->bb_physts_i.bb_physts_rslt_hdr_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rssi_mu_acc_info *rssi_mu_acc = &cmn_rpt->bb_rssi_mu_acc_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
u32 *rssi_acc;
u8 i = 0;
if (rate_i->mode <= BB_HT_MODE) {
BB_WARNING("[%s] mode = %d", __func__, rate_i->mode);
return;
}
rssi_mu_acc->rssi_t_avg_acc += psts_h->rssi_avg;
rssi_acc = &rssi_mu_acc->rssi_t_acc[0];
//BB_DBG(bb, DBG_PHY_STS, "Xt = %d\n", rssi_su_acc->rssi_t_avg_acc);
/*HT/VHT/HE*/
for (i = 0; i < HALBB_MAX_PATH; i++) {
if (i >= bb->num_rf_path)
break;
rssi_acc[i] += (u32)psts_h->rssi[i];
}
//BB_DBG(bb, DBG_PHY_STS, "rssi_acc = %d, %d\n", rssi_acc[0], rssi_acc[1]);
}
#endif
#define CMN_RPT_SU
#ifdef CMN_RPT_SU
void halbb_show_phy_hitogram_su(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_physts_acc_info *acc = &cmn_rpt->bb_physts_acc_i;
struct bb_physts_avg_info *avg = &cmn_rpt->bb_physts_avg_i;
struct bb_physts_hist_info *hist = &cmn_rpt->bb_physts_hist_i;
struct bb_physts_hist_th_info *hist_th = &cmn_rpt->bb_physts_hist_th_i;
char buf[HALBB_SNPRINT_SIZE] = {0};
u16 valid_cnt = pkt_cnt->pkt_cnt_t + pkt_cnt->pkt_cnt_ofdm;
/*=== [EVM, SNR] =====================================================*/
/*Threshold*/
//BB_DBG(bb, DBG_CMN, "[RESULT ACC] cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n",
// acc->cfo_avg_acc, acc->evm_max_acc, acc->evm_min_acc, acc->cn_avg_acc);
//BB_DBG(bb, DBG_CMN, "valid_cnt=%d\n", valid_cnt);
halbb_print_hist_2_buf_u8(bb, hist_th->evm_hist_th, BB_HIST_TH_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, " %-8s %-9s %s\n", "[TH]", "(Avg)", bb->dbg_buf);
/*val*/
avg->evm_1ss = (u8)HALBB_DIV(acc->evm_1ss, (pkt_cnt->pkt_cnt_1ss + pkt_cnt->pkt_cnt_ofdm));
halbb_print_hist_2_buf(bb, hist->evm_1ss, BB_HIST_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[EVM_1ss]",
(avg->evm_1ss >> 2),
halbb_show_fraction_num(avg->evm_1ss & 0x3, 2), bb->dbg_buf);
avg->evm_max = (u8)HALBB_DIV(acc->evm_max_acc, pkt_cnt->pkt_cnt_2ss);
halbb_print_hist_2_buf(bb, hist->evm_max_hist, BB_HIST_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[EVM_max]",
(avg->evm_max >> 2),
halbb_show_fraction_num(avg->evm_max & 0x3, 2), bb->dbg_buf);
avg->evm_min = (u8)HALBB_DIV(acc->evm_min_acc, pkt_cnt->pkt_cnt_2ss);
halbb_print_hist_2_buf(bb, hist->evm_min_hist, BB_HIST_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[EVM_min]",
(avg->evm_min >> 2),
halbb_show_fraction_num(avg->evm_min & 0x3, 2), bb->dbg_buf);
avg->snr_avg = (u8)HALBB_DIV(acc->snr_avg_acc, valid_cnt);
halbb_print_hist_2_buf(bb, hist->snr_avg_hist, BB_HIST_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "%-9s (%02d.000) %s\n", "[SNR_avg]",
avg->snr_avg, bb->dbg_buf);
/*=== [CN] ===========================================================*/
/*Threshold*/
halbb_print_hist_2_buf_u8(bb, hist_th->cn_hist_th, BB_HIST_TH_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, " %-8s %-9s %s\n", "[TH]", "(Avg)", bb->dbg_buf);
/*val*/
avg->cn_avg = (u8)HALBB_DIV(acc->cn_avg_acc, valid_cnt);
halbb_print_hist_2_buf(bb, hist->cn_avg_hist, BB_HIST_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "%-9s (%02d.%03d) %s\n", "[CN_avg]",
(avg->cn_avg >> 1),
halbb_show_fraction_num(avg->cn_avg & 0x1, 1), bb->dbg_buf);
/*=== [CFO] ==========================================================*/
/*Threshold*/
halbb_print_hist_2_buf_u8(bb, hist_th->cfo_hist_th, BB_HIST_TH_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, " %-8s %-9s %s\n", "[TH]", "(Avg)", bb->dbg_buf);
/*val*/
avg->cfo_avg = (s16)HALBB_DIV(acc->cfo_avg_acc, valid_cnt);
halbb_print_sign_frac_digit(bb, avg->cfo_avg, 16, 2, buf, HALBB_SNPRINT_SIZE);
halbb_print_hist_2_buf(bb, hist->cfo_avg_hist, BB_HIST_SIZE, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "%-9s (%s K) %s\n", "[CFO_avg]",
buf, bb->dbg_buf);
BB_DBG(bb, DBG_CMN, "CFO_src: %s\n",
(bb->bb_cfo_trk_i.cfo_src == CFO_SRC_FD) ? "FD" : "Preamble");
BB_DBG(bb, DBG_CMN, "valid_cnt = %d\n", valid_cnt);
}
u16 halbb_get_plurality_rx_rate_su(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
u16 max_num_tmp = 0;
u16 rx_rate_plurality = 0;
u16 i = 0;
u16 *pkt_cnt_tmp;
u8 rate_num_tmp;
u16 ofst_mode = 0;
u16 ofst_ss = 0;
u16 idx = 0;
bool is_ht_mode = false;
bool plurality_is_legacy_rate = true;
/*Legacy rate*/
if (pkt_cnt->pkt_cnt_cck || pkt_cnt->pkt_cnt_ofdm) {
for (i = 0; i < LEGACY_RATE_NUM; i++) {
if (pkt_cnt->pkt_cnt_legacy[i] >= max_num_tmp) {
max_num_tmp = pkt_cnt->pkt_cnt_legacy[i];
rx_rate_plurality = i;
}
}
}
//BB_DBG(bb, DBG_CMN, "[LEGACY]rx_rate_plurality= (0x%x), max_num_tmp=%d\n", rx_rate_plurality, max_num_tmp);
if (pkt_cnt->pkt_cnt_t == 0) {
return rx_rate_plurality;
}
//BB_DBG(bb, DBG_CMN, "cnt_t= (%d)\n", pkt_cnt->pkt_cnt_t);
/*HT, VHT, HE*/
if (pkt_cnt->he_pkt_not_zero) {
pkt_cnt_tmp = pkt_cnt->pkt_cnt_he;
rate_num_tmp = HE_RATE_NUM;
ofst_mode = BB_HE_1SS_MCS0;
} else if (pkt_cnt->vht_pkt_not_zero) {
pkt_cnt_tmp = pkt_cnt->pkt_cnt_vht;
rate_num_tmp = VHT_RATE_NUM;
ofst_mode = BB_VHT_1SS_MCS0;
} else if (pkt_cnt->ht_pkt_not_zero) {
pkt_cnt_tmp = pkt_cnt->pkt_cnt_ht;
rate_num_tmp = HT_RATE_NUM;
ofst_mode = BB_HT_MCS0;
is_ht_mode = true;
} else {
return rx_rate_plurality;
}
for (i = 0; i < rate_num_tmp; i++) {
if (pkt_cnt_tmp[i] >= max_num_tmp) {
max_num_tmp = pkt_cnt_tmp[i];
idx = i;
plurality_is_legacy_rate = false;
}
}
if (plurality_is_legacy_rate)
return rx_rate_plurality;
//BB_DBG(bb, DBG_CMN, "[T]idx_ori= (%d)\n", idx);
if (!is_ht_mode) {
ofst_ss = idx / HE_VHT_NUM_MCS;
if (ofst_ss >= 0) /*>=2SS*/
idx -= (ofst_ss * HE_VHT_NUM_MCS);
//BB_DBG(bb, DBG_CMN, "ofst_ss= (%d), idx=%d\n", ofst_ss, idx);
}
rx_rate_plurality = ofst_mode + (ofst_ss << 4) + idx;
//BB_DBG(bb, DBG_CMN, "[T]rx_rate_plurality= (0x%x), max_num_tmp=%d\n", rx_rate_plurality, max_num_tmp);
return rx_rate_plurality;
}
void halbb_show_rssi_and_rate_distribution_su(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_rssi_su_acc_info *acc = &cmn_rpt->bb_rssi_su_acc_i;
struct bb_rssi_su_avg_info *avg = &cmn_rpt->bb_rssi_su_avg_i;
u8 rssi_avg_tmp = 0;
u8 rssi_tmp[HALBB_MAX_PATH];
u16 pkt_cnt_ss = 0;
u8 i = 0, j =0;
u8 rate_num = bb->num_rf_path, ss_ofst = 0;
avg->rssi_cck_avg = (u8)HALBB_DIV(acc->rssi_cck_avg_acc, pkt_cnt->pkt_cnt_cck);
avg->rssi_ofdm_avg = (u8)HALBB_DIV(acc->rssi_ofdm_avg_acc, pkt_cnt->pkt_cnt_ofdm);
avg->rssi_t_avg = (u8)HALBB_DIV(acc->rssi_t_avg_acc, pkt_cnt->pkt_cnt_t);
for (i = 0; i < HALBB_MAX_PATH; i++) {
if (i >= bb->num_rf_path)
break;
avg->rssi_cck[i] = (u8)HALBB_DIV(acc->rssi_cck_acc[i], pkt_cnt->pkt_cnt_cck);
avg->rssi_ofdm[i] = (u8)HALBB_DIV(acc->rssi_ofdm_acc[i], pkt_cnt->pkt_cnt_ofdm);
avg->rssi_t[i] = (u8)HALBB_DIV(acc->rssi_t_acc[i], pkt_cnt->pkt_cnt_t);
//BB_DBG(bb, DBG_CMN, "*rssi_ofdm_avg %02d = rssi_ofdm_acc %02d / pkt_cnt_ofdm%02d}\n",
// avg->rssi_ofdm_avg, avg->rssi_ofdm[i], acc->rssi_ofdm_acc[i], pkt_cnt->pkt_cnt_ofdm);
}
/*@======[Lgcy-non-data]=============================================*/
BB_DBG(bb, DBG_CMN, "[Lgcy-non-data] {%d, %d, %d, %d | %d, %d, %d, %d, %d, %d, %d, %d} {%d}\n",
pkt_cnt->pkt_cnt_legacy_non_data[0], pkt_cnt->pkt_cnt_legacy_non_data[1],
pkt_cnt->pkt_cnt_legacy_non_data[2], pkt_cnt->pkt_cnt_legacy_non_data[3],
pkt_cnt->pkt_cnt_legacy_non_data[4], pkt_cnt->pkt_cnt_legacy_non_data[5],
pkt_cnt->pkt_cnt_legacy_non_data[6], pkt_cnt->pkt_cnt_legacy_non_data[7],
pkt_cnt->pkt_cnt_legacy_non_data[8], pkt_cnt->pkt_cnt_legacy_non_data[9],
pkt_cnt->pkt_cnt_legacy_non_data[10], pkt_cnt->pkt_cnt_legacy_non_data[11],
pkt_cnt->pkt_cnt_else_non_data);
/*@======CCK=========================================================*/
BB_DBG(bb, DBG_CMN, "*CCK RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d}\n",
avg->rssi_cck_avg >> 1,
avg->rssi_cck[0] >> 1, avg->rssi_cck[1] >> 1,
pkt_cnt->pkt_cnt_cck,
pkt_cnt->pkt_cnt_legacy[0], pkt_cnt->pkt_cnt_legacy[1],
pkt_cnt->pkt_cnt_legacy[2], pkt_cnt->pkt_cnt_legacy[3]);
/*@======OFDM========================================================*/
BB_DBG(bb, DBG_CMN, "*OFDM RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d}\n",
avg->rssi_ofdm_avg >> 1,
avg->rssi_ofdm[0] >> 1, avg->rssi_ofdm[1] >> 1,
pkt_cnt->pkt_cnt_ofdm,
pkt_cnt->pkt_cnt_legacy[4], pkt_cnt->pkt_cnt_legacy[5],
pkt_cnt->pkt_cnt_legacy[6], pkt_cnt->pkt_cnt_legacy[7],
pkt_cnt->pkt_cnt_legacy[8], pkt_cnt->pkt_cnt_legacy[9],
pkt_cnt->pkt_cnt_legacy[10], pkt_cnt->pkt_cnt_legacy[11]);
/*@======HT==========================================================*/
if (pkt_cnt->ht_pkt_not_zero) {
for (i = 0; i < rate_num; i++) {
ss_ofst = (i << 3);
for (j = 0; j < HT_NUM_MCS ; j++) {
pkt_cnt_ss += pkt_cnt->pkt_cnt_ht[ss_ofst + j];
}
if (pkt_cnt_ss == 0) {
rssi_avg_tmp = 0;
rssi_tmp[0] = 0;
rssi_tmp[1] = 0;
} else {
rssi_avg_tmp = avg->rssi_t_avg >> 1;
rssi_tmp[0] = avg->rssi_t[0] >> 1;
rssi_tmp[1] = avg->rssi_t[1] >> 1;
}
BB_DBG(bb, DBG_CMN,
"*HT%02d:%02d RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_ofst), (ss_ofst + 7),
rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1],
pkt_cnt_ss,
pkt_cnt->pkt_cnt_ht[ss_ofst + 0],
pkt_cnt->pkt_cnt_ht[ss_ofst + 1],
pkt_cnt->pkt_cnt_ht[ss_ofst + 2],
pkt_cnt->pkt_cnt_ht[ss_ofst + 3],
pkt_cnt->pkt_cnt_ht[ss_ofst + 4],
pkt_cnt->pkt_cnt_ht[ss_ofst + 5],
pkt_cnt->pkt_cnt_ht[ss_ofst + 6],
pkt_cnt->pkt_cnt_ht[ss_ofst + 7]);
pkt_cnt_ss = 0;
}
}
/*@======VHT==========================================================*/
if (pkt_cnt->vht_pkt_not_zero) {
for (i = 0; i < rate_num; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
for (j = 0; j < HE_VHT_NUM_MCS ; j++) {
pkt_cnt_ss += pkt_cnt->pkt_cnt_vht[ss_ofst + j];
}
if (pkt_cnt_ss == 0) {
rssi_avg_tmp = 0;
rssi_tmp[0] = 0;
rssi_tmp[1] = 0;
} else {
rssi_avg_tmp = avg->rssi_t_avg >> 1;
rssi_tmp[0] = avg->rssi_t[0] >> 1;
rssi_tmp[1] = avg->rssi_t[1] >> 1;
}
BB_DBG(bb, DBG_CMN,
"*VHT %d-S RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1],
pkt_cnt_ss,
pkt_cnt->pkt_cnt_vht[ss_ofst + 0],
pkt_cnt->pkt_cnt_vht[ss_ofst + 1],
pkt_cnt->pkt_cnt_vht[ss_ofst + 2],
pkt_cnt->pkt_cnt_vht[ss_ofst + 3],
pkt_cnt->pkt_cnt_vht[ss_ofst + 4],
pkt_cnt->pkt_cnt_vht[ss_ofst + 5],
pkt_cnt->pkt_cnt_vht[ss_ofst + 6],
pkt_cnt->pkt_cnt_vht[ss_ofst + 7],
pkt_cnt->pkt_cnt_vht[ss_ofst + 8],
pkt_cnt->pkt_cnt_vht[ss_ofst + 9],
pkt_cnt->pkt_cnt_vht[ss_ofst + 10],
pkt_cnt->pkt_cnt_vht[ss_ofst + 11]);
pkt_cnt_ss = 0;
}
}
/*@======HE==========================================================*/
if (pkt_cnt->he_pkt_not_zero) {
for (i = 0; i < rate_num; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
for (j = 0; j < HE_VHT_NUM_MCS ; j++) {
pkt_cnt_ss += pkt_cnt->pkt_cnt_he[ss_ofst + j];
}
if (pkt_cnt_ss == 0) {
rssi_avg_tmp = 0;
rssi_tmp[0] = 0;
rssi_tmp[1] = 0;
} else {
rssi_avg_tmp = avg->rssi_t_avg >> 1;
rssi_tmp[0] = avg->rssi_t[0] >> 1;
rssi_tmp[1] = avg->rssi_t[1] >> 1;
}
BB_DBG(bb, DBG_CMN,
"*HE %d-SS RSSI:{%02d| %02d,%02d} cnt:{%03d| %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
rssi_avg_tmp, rssi_tmp[0], rssi_tmp[1],
pkt_cnt_ss,
pkt_cnt->pkt_cnt_he[ss_ofst + 0],
pkt_cnt->pkt_cnt_he[ss_ofst + 1],
pkt_cnt->pkt_cnt_he[ss_ofst + 2],
pkt_cnt->pkt_cnt_he[ss_ofst + 3],
pkt_cnt->pkt_cnt_he[ss_ofst + 4],
pkt_cnt->pkt_cnt_he[ss_ofst + 5],
pkt_cnt->pkt_cnt_he[ss_ofst + 6],
pkt_cnt->pkt_cnt_he[ss_ofst + 7],
pkt_cnt->pkt_cnt_he[ss_ofst + 8],
pkt_cnt->pkt_cnt_he[ss_ofst + 9],
pkt_cnt->pkt_cnt_he[ss_ofst + 10],
pkt_cnt->pkt_cnt_he[ss_ofst + 11]);
pkt_cnt_ss = 0;
}
}
/*@======SC_BW========================================================*/
if (pkt_cnt->sc20_occur) {
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG(bb, DBG_CMN,
"*[Low BW 20M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_sc20[ss_ofst + 0],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 1],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 2],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 3],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 4],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 5],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 6],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 7],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 8],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 9],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 10],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 11]);
}
}
if (pkt_cnt->sc40_occur) {
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG(bb, DBG_CMN,
"*[Low BW 40M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_sc40[ss_ofst + 0],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 1],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 2],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 3],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 4],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 5],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 6],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 7],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 8],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 9],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 10],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 11]);
}
}
}
void halbb_rx_pkt_su_non_data_cnt_rpt(struct bb_info *bb, struct physts_rxd *desc, enum channel_width rx_bw)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
u8 ofst = rate_i->idx;
if (rate_i->mode == BB_LEGACY_MODE) {
pkt_cnt->pkt_cnt_legacy_non_data[ofst]++;
} else {
pkt_cnt->pkt_cnt_else_non_data++;
}
}
void halbb_rx_pkt_su_cnt_rpt(struct bb_info *bb, struct physts_rxd *desc, enum channel_width rx_bw)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
enum channel_width bw_curr; /*max bw in current link mode*/
u8 band_idx;
u8 ofst = rate_i->idx;
pkt_cnt->pkt_cnt_all++;
if (rate_i->mode == BB_LEGACY_MODE) {
if (cmn_rpt->is_cck_rate)
pkt_cnt->pkt_cnt_cck++;
else
pkt_cnt->pkt_cnt_ofdm++;
} else {
pkt_cnt->pkt_cnt_t++;
if (rate_i->ss == 1)
pkt_cnt->pkt_cnt_1ss++;
else if (rate_i->ss == 2)
pkt_cnt->pkt_cnt_2ss++;
}
band_idx = (desc->phy_idx == HW_PHY_0) ? 0 : 1;
bw_curr = bb->hal_com->band[band_idx].cur_chandef.bw;
if (rate_i->mode == BB_LEGACY_MODE) {
pkt_cnt->pkt_cnt_legacy[ofst]++;
return;
}
if (rate_i->ss >= 2 && rate_i->mode >= BB_VHT_MODE)
ofst += (HE_VHT_NUM_MCS * (rate_i->ss - 1));
if (rate_i->mode == BB_HT_MODE) {
pkt_cnt->ht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HT_RATE_NUM - 1);
if (rx_bw == bw_curr) {
pkt_cnt->pkt_cnt_ht[ofst]++;
return;
}
} else if (rate_i->mode == BB_VHT_MODE) {
pkt_cnt->vht_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, VHT_RATE_NUM - 1);
if (rx_bw == bw_curr) {
pkt_cnt->pkt_cnt_vht[ofst]++;
return;
}
} else if (rate_i->mode == BB_HE_MODE) {
pkt_cnt->he_pkt_not_zero = true;
ofst = NOT_GREATER(ofst, HE_RATE_NUM - 1);
if (rx_bw == bw_curr) {
pkt_cnt->pkt_cnt_he[ofst]++;
return;
}
}
/*SC BW*/
if (rx_bw != bw_curr) {
ofst = NOT_GREATER(ofst, LOW_BW_RATE_NUM - 1);
if (rx_bw == CHANNEL_WIDTH_20) {
pkt_cnt->pkt_cnt_sc20[ofst]++;
pkt_cnt->sc20_occur = true;
} else if (rx_bw == CHANNEL_WIDTH_40) {
pkt_cnt->pkt_cnt_sc40[ofst]++;
pkt_cnt->sc40_occur = true;
} else {
pkt_cnt->pkt_cnt_sc80[ofst]++;
pkt_cnt->sc80_occur = true;
}
}
}
void halbb_rx_pkt_su_phy_hist(struct bb_info *bb)
{
struct bb_physts_rslt_1_info *psts_1 = &bb->bb_physts_i.bb_physts_rslt_1_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_physts_acc_info *acc = &cmn_rpt->bb_physts_acc_i;
struct bb_physts_hist_info *hist = &cmn_rpt->bb_physts_hist_i;
struct bb_physts_hist_th_info *hist_th = &cmn_rpt->bb_physts_hist_th_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
struct bb_cfo_trk_info *bb_cfo_trk = &bb->bb_cfo_trk_i;
u16 tmp_u16;
u8 intvl = 0;
s16 cfo;
if (cmn_rpt->is_cck_rate)
return;
//BB_DBG(bb, DBG_CMN, "[2]cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n",
// psts_1->cfo_avg, psts_1->evm_max, psts_1->evm_min, psts_1->cn_avg);
if (rate_i->ss == 1) {
acc->evm_1ss += psts_1->evm_min;
intvl = halbb_find_intrvl(bb, (psts_1->evm_min >> 2), hist_th->evm_hist_th, BB_HIST_TH_SIZE);
hist->evm_1ss[intvl]++;
} else {
/*EVM min/max Histogram*/
acc->evm_min_acc += psts_1->evm_min;
intvl = halbb_find_intrvl(bb, (psts_1->evm_min >> 2), hist_th->evm_hist_th, BB_HIST_TH_SIZE);
hist->evm_min_hist[intvl]++;
acc->evm_max_acc += psts_1->evm_max;
intvl = halbb_find_intrvl(bb, (psts_1->evm_max >> 2), hist_th->evm_hist_th, BB_HIST_TH_SIZE);
hist->evm_max_hist[intvl]++;
//BB_DBG(bb, DBG_CMN, "evm_max_hist[%d]=%d\n", intvl, hist->evm_max_hist[intvl]);
}
/*SNR_avg Histogram*/
acc->snr_avg_acc += psts_1->snr_avg;
intvl = halbb_find_intrvl(bb, psts_1->snr_avg, hist_th->evm_hist_th, BB_HIST_TH_SIZE);
hist->snr_avg_hist[intvl]++;
/*CN_avg Histogram*/
acc->cn_avg_acc += psts_1->cn_avg;
intvl = halbb_find_intrvl(bb, (psts_1->cn_avg >> 1), hist_th->cn_hist_th, BB_HIST_TH_SIZE);
hist->cn_avg_hist[intvl]++;
/*CFO_avg Histogram*/
if (bb_cfo_trk->cfo_src == CFO_SRC_FD)
cfo = psts_1->cfo_avg;
else
cfo = psts_1->cfo_pab_avg;
tmp_u16 = (u16)ABS_16(cfo);
acc->cfo_avg_acc += cfo;
intvl = halbb_find_intrvl(bb, (tmp_u16 >> 2), hist_th->cfo_hist_th, BB_HIST_TH_SIZE);
hist->cfo_avg_hist[intvl]++;
//BB_DBG(bb, DBG_CMN, "[ACC] cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n",
// acc->cfo_avg_acc, acc->evm_max_acc, acc->evm_min_acc, acc->cn_avg_acc);
}
void halbb_rx_pkt_su_rssi_statistic(struct bb_info *bb)
{
struct bb_physts_rslt_hdr_info *psts_h = &bb->bb_physts_i.bb_physts_rslt_hdr_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_rssi_su_acc_info *rssi_su_acc = &cmn_rpt->bb_rssi_su_acc_i;
struct bb_rate_info *rate_i = &cmn_rpt->bb_rate_i;
u32 *rssi_acc;
u8 i = 0;
if (rate_i->mode == BB_LEGACY_MODE) {
if (cmn_rpt->is_cck_rate) {
rssi_su_acc->rssi_cck_avg_acc += psts_h->rssi_avg;
rssi_acc = &rssi_su_acc->rssi_cck_acc[0];
//BB_DBG(bb, DBG_PHY_STS, "cck = %d\n", rssi_su_acc->rssi_cck_avg_acc);
} else {
rssi_su_acc->rssi_ofdm_avg_acc += psts_h->rssi_avg;
rssi_acc = &rssi_su_acc->rssi_ofdm_acc[0];
//BB_DBG(bb, DBG_PHY_STS, "ofdm = %d\n", rssi_su_acc->rssi_ofdm_avg_acc);
}
} else {
rssi_su_acc->rssi_t_avg_acc += psts_h->rssi_avg;
rssi_acc = &rssi_su_acc->rssi_t_acc[0];
//BB_DBG(bb, DBG_PHY_STS, "Xt = %d\n", rssi_su_acc->rssi_t_avg_acc);
}
/*HT/VHT/HE*/
for (i = 0; i < HALBB_MAX_PATH; i++) {
if (i >= bb->num_rf_path)
break;
rssi_acc[i] += (u32)psts_h->rssi[i];
}
//BB_DBG(bb, DBG_PHY_STS, "rssi_acc = %d, %d\n", rssi_acc[0], rssi_acc[1]);
}
//#define ORI_RSSI_FLAG
void halbb_rx_pkt_su_store_in_sta_info(struct bb_info *bb, struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i;
struct rtw_phl_stainfo_t *phl_sta;
struct rtw_rssi_info *rssi_t = NULL;
u8 ma_fac = 2;
u8 bb_macid;
u8 i = 0;
if (desc->macid_su > PHL_MAX_STA_NUM)
BB_WARNING("[%s] macid_su=%d\n", __func__, desc->macid_su);
bb_macid = bb->phl2bb_macid_table[desc->macid_su];
if (bb_macid > PHL_MAX_STA_NUM)
BB_WARNING("[%s] bb_macid=%d\n", __func__, bb_macid);
phl_sta = bb->phl_sta_info[bb_macid];
if (!is_sta_active(phl_sta))
return;
if (phl_sta->macid > PHL_MAX_STA_NUM)
return;
if (!phl_sta->hal_sta)
return;
rssi_t = &phl_sta->hal_sta->rssi_stat;
//BB_DBG(bb, DBG_PHY_STS, "desc->macid_su=%d, bb_macid=%d, phl_sta->macid=%d\n",
// desc->macid_su, bb_macid, phl_sta->macid);
//BB_DBG(bb, DBG_PHY_STS, "[pre] psts_h->rssi_avg = %d, rssi_ma=%d\n", psts_h->rssi_avg, rssi_t->rssi_ma);
if (desc->user_i[0].is_bcn) {
ma_fac = rssi_t->ma_factor_bcn;
if (rssi_t->rssi_bcn_ma == 0) {
rssi_t->rssi_bcn_ma = (s16)(psts_h->rssi_avg << RSSI_MA_H);
rssi_t->rssi_bcn = (s8)psts_h->rssi_avg;
} else {
rssi_t->rssi_bcn_ma = MA_ACC(rssi_t->rssi_bcn_ma, (u16)psts_h->rssi_avg, ma_fac, RSSI_MA_H);
rssi_t->rssi_bcn = (u8)GET_MA_VAL(rssi_t->rssi_bcn_ma, RSSI_MA_H);
}
rssi_t->pkt_cnt_bcn++;
} else {
ma_fac = rssi_t->ma_factor;
if (rssi_t->rssi_ma == 0) {
rssi_t->rssi_ma = (s16)(psts_h->rssi_avg << RSSI_MA_H);
rssi_t->rssi = (s8)psts_h->rssi_avg;
if (!bb->bb_cmn_rpt_i.is_cck_rate)
rssi_t->snr_ma = (u16)psts_1->snr_avg << RSSI_MA_H;
//BB_DBG(bb, DBG_BIT21, "[First][macid:%d] snr=%d, rssi_ori=%d, rssi_ma=%d, rssi_ma16=%d\n", bb_macid, rssi_t->snr_ma, psts_h->rssi_avg, rssi_t->rssi, rssi_t->rssi_ma);
} else {
rssi_t->rssi_ma = MA_ACC(rssi_t->rssi_ma, (u16)psts_h->rssi_avg, ma_fac, RSSI_MA_H);
rssi_t->rssi = (u8)GET_MA_VAL(rssi_t->rssi_ma, RSSI_MA_H);
if (!bb->bb_cmn_rpt_i.is_cck_rate)
rssi_t->snr_ma = MA_ACC(rssi_t->snr_ma, (u16)psts_1->snr_avg, ma_fac, RSSI_MA_H);
//BB_DBG(bb, DBG_BIT21, "[NORML][macid:%d] snr=%d, rssi_ori=%d, rssi_ma=%d, rssi_ma16=%d\n", bb_macid, rssi_t->snr_ma, psts_h->rssi_avg, rssi_t->rssi, rssi_t->rssi_ma);
}
for (i = 0; i < HALBB_MAX_PATH; i++) {
if (!(physts->rx_path_en & BIT(i)))
continue;
if (rssi_t->rssi_ma_path[i] == 0) {
rssi_t->rssi_ma_path[i] = (u16)(psts_h->rssi[i] << RSSI_MA_H);
} else {
rssi_t->rssi_ma_path[i] = MA_ACC(rssi_t->rssi_ma_path[i], (u16)psts_h->rssi[i], ma_fac, RSSI_MA_H);
}
}
rssi_t->pkt_cnt_data++;
}
//BB_DBG(bb, DBG_PHY_STS, "[%d] rssi = %d, rssi_ma=%d\n", bb_macid, rssi_t->rssi, rssi_t->rssi_ma);
if (bb->bb_cmn_rpt_i.is_cck_rate)
rssi_t->rssi_cck = psts_h->rssi_avg;
else
rssi_t->rssi_ofdm = psts_h->rssi_avg;
//BB_DBG(bb, DBG_PHY_STS, "[%d] rssi_cck = %d, rssi_ofdm=%d\n", bb_macid, rssi_t->rssi_cck, rssi_t->rssi_ofdm);
}
void halbb_get_rx_pkt_cnt_rpt_su(struct bb_info *bb, struct bb_pkt_cnt_su_info *pkt_cnt_rpt)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
halbb_mem_cpy(bb, pkt_cnt_rpt, pkt_cnt, sizeof(struct bb_pkt_cnt_su_info));
}
#endif
void halbb_cmn_info_rpt_store_data(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bb_pkt_cnt_su_store_info *store = &cmn_rpt->bb_pkt_cnt_su_store_i;
store->ht_pkt_not_zero = pkt_cnt->ht_pkt_not_zero;
store->vht_pkt_not_zero = pkt_cnt->vht_pkt_not_zero;
store->he_pkt_not_zero = pkt_cnt->he_pkt_not_zero;
}
void halbb_cmn_info_rpt_reset(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
cmn_rpt->bb_pkt_cnt_bcn_i.beacon_cnt_in_period = cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon;
cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon = 0;
bb->bb_ch_i.rxsc_l = 0xff;
bb->bb_ch_i.rxsc_20 = 0xff;
bb->bb_ch_i.rxsc_40 = 0xff;
bb->bb_ch_i.rxsc_80 = 0xff;
halbb_rx_pkt_cnt_rpt_reset(bb);
}
void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i;
struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i;
enum channel_width rx_bw = psts_1->bw_idx;
if (desc->is_su) {
halbb_rate_idx_parsor(bb, desc->data_rate, (enum rtw_gi_ltf)desc->gi_ltf, &cmn_rpt->bb_rate_i);
} else if (physts->physts_bitmap_recv & BIT(IE13_DL_MU_DEF)) {
halbb_mu_rate_idx_generate(bb, desc, psts_1->bw_idx, &cmn_rpt->bb_rate_i);
} else {
BB_DBG(bb, DBG_PHY_STS, "[MU] physts_bitmap_recv=%d\n", physts->physts_bitmap_recv);
return;
}
cmn_rpt->is_cck_rate = halbb_is_cck_rate(bb, desc->data_rate);
physts->rx_path_en = (cmn_rpt->is_cck_rate) ? psts_0->rx_path_en_cck : psts_1->rx_path_en;
if (cmn_rpt->bb_rate_i.mode == BB_LEGACY_MODE)
bb->bb_ch_i.rxsc_l = psts_1->rxsc;
else if (psts_1->bw_idx == CHANNEL_WIDTH_20)
bb->bb_ch_i.rxsc_20 = psts_1->rxsc;
else if (psts_1->bw_idx == CHANNEL_WIDTH_40)
bb->bb_ch_i.rxsc_40 = psts_1->rxsc;
else if (psts_1->bw_idx == CHANNEL_WIDTH_80)
bb->bb_ch_i.rxsc_80 = psts_1->rxsc;
else if (psts_1->bw_idx == CHANNEL_WIDTH_160)
bb->bb_ch_i.rxsc_160 = psts_1->rxsc;
BB_DBG(bb, DBG_PHY_STS, "is_su = %d\n", desc->is_su);
if (desc->is_su) {
if (desc->user_i[0].is_data || desc->user_i[0].is_bcn) {/*@data frame only*/
halbb_rx_pkt_su_store_in_sta_info(bb, desc);
halbb_rx_pkt_su_cnt_rpt(bb, desc, rx_bw);
halbb_rx_pkt_su_rssi_statistic(bb);
halbb_rx_pkt_su_phy_hist(bb);
if (desc->user_i[0].is_bcn)
halbb_rx_pkt_cnt_rpt_beacon(bb, desc);
} else {
halbb_rx_pkt_su_non_data_cnt_rpt(bb, desc, rx_bw);
}
} else {
halbb_rx_pkt_mu_cnt_rpt(bb, desc, rx_bw);
halbb_rx_pkt_mu_rssi_statistic(bb);
}
halbb_rx_pop_hist(bb);
halbb_idle_time_pwr_physts(bb, desc, cmn_rpt->is_cck_rate);
}
void halbb_physts_hist_init(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_physts_hist_th_info *hist_th = &cmn_rpt->bb_physts_hist_th_i;
u8 evm_hist_th[BB_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35};
u8 cn_hist_th[BB_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 18};
u8 cfo_hist_th[BB_HIST_TH_SIZE] = {1, 5, 10, 15, 20, 30, 60, 90, 120, 150, 200};
halbb_mem_cpy(bb, hist_th->evm_hist_th, evm_hist_th, BB_HIST_TH_SIZE);
halbb_mem_cpy(bb, hist_th->cn_hist_th, cn_hist_th, BB_HIST_TH_SIZE);
halbb_mem_cpy(bb, hist_th->cfo_hist_th, cfo_hist_th, BB_HIST_TH_SIZE);
}
void halbb_cmn_rpt_init(struct bb_info *bb)
{
BB_DBG(bb, DBG_DBG_API, "%s\n", __func__);
halbb_physts_hist_init(bb);
halbb_rx_pkt_cnt_rpt_reset(bb);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_cmn_rpt.c
|
C
|
agpl-3.0
| 40,021
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CMN_RPT_H__
#define __HALBB_CMN_RPT_H__
/*@--------------------------[Define] ---------------------------------------*/
#define RSSI_MA_H 4 /*moving average factor for RSSI: 2^4=16 */
#define RSSI_MA_M 3
#define RSSI_MA_L 2
#define RSSI_MA_UL 1
#define BB_HIST_SIZE 12
#define BB_HIST_TH_SIZE (BB_HIST_SIZE - 1)
#define POP_HIST_SIZE 4
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_rssi_mu_acc_info { /*all in U(8,1)*/
/*acc value*/
u32 rssi_t_avg_acc;
u32 rssi_t_acc[HALBB_MAX_PATH]; /*VHT, HE*/
};
struct bb_pkt_cnt_bcn_info {
u8 pkt_cnt_beacon;
u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
u16 beacon_phy_rate;
};
struct bb_rssi_su_acc_info { /*all in U(8,1)*/
/*acc value*/
u32 rssi_cck_avg_acc;
u32 rssi_cck_acc[HALBB_MAX_PATH];
u32 rssi_ofdm_avg_acc;
u32 rssi_ofdm_acc[HALBB_MAX_PATH]; /*L-OFDM*/
u32 rssi_t_avg_acc;
u32 rssi_t_acc[HALBB_MAX_PATH]; /*HT, VHT, HE*/
};
struct bb_pkt_cnt_cap_info {
u32 pkt_cnt_ldpc; /*pkt_cnt_ofdm = pkt_cnt_ldpc + pkt_cnt_bcc*/
u32 pkt_cnt_bcc;
u32 pkt_cnt_stbc;
u32 pkt_cnt_subf;
u32 pkt_cnt_mubf;
};
struct bb_physts_hist_info {
u16 evm_1ss[BB_HIST_SIZE];
u16 evm_min_hist[BB_HIST_SIZE];
u16 evm_max_hist[BB_HIST_SIZE];
u16 snr_avg_hist[BB_HIST_SIZE];
u16 cn_avg_hist[BB_HIST_SIZE];
u16 cfo_avg_hist[BB_HIST_SIZE]; /*ABS(cfo) 0~256 Khz*/
};
struct bb_physts_hist_th_info {
u8 evm_hist_th[BB_HIST_TH_SIZE]; /*threshold*/
u8 cn_hist_th[BB_HIST_TH_SIZE]; /*threshold*/
u8 cfo_hist_th[BB_HIST_TH_SIZE]; /*threshold*/
};
struct bb_physts_acc_info {
u32 evm_1ss; /*U(8,2)*/ /*only for 1SS & L-OFDM*/
u32 evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 snr_avg_acc; /*U(6,0)*/
u32 cn_avg_acc; /*U(7,1)*/
s32 cfo_avg_acc; /*U(8,2)*/
};
struct bb_physts_avg_info {
u8 evm_1ss; /*U(8,2) 0~63*/
u8 evm_min; /*U(8,2) 0~63*/
u8 evm_max; /*U(8,2) 0~63*/
u8 snr_avg; /*U(6,0) 0~63*/
u8 cn_avg; /*U(7,1) 0~63*/
s16 cfo_avg; /*U(16,2) 0~512*/
};
struct bb_physts_pop_info {
u16 pop_hist_cck[POP_HIST_SIZE]; /*U(8,0) pop_idx histogram*/
u16 pop_hist_ofdm[POP_HIST_SIZE]; /*U(8,0) pop_idx histogram*/
};
struct bb_cmn_rpt_info {
bool is_cck_rate;
u8 consec_idle_prd_su; /*consecutive idle period*/
u8 consec_idle_prd_mu;
struct bb_rate_info bb_rate_i;
struct bb_pkt_cnt_bcn_info bb_pkt_cnt_bcn_i; /*beacon info*/
struct bb_pkt_cnt_cap_info bb_pkt_cnt_all_i; /*capibility info*/
struct bb_pkt_cnt_su_info bb_pkt_cnt_su_i; /*Packet count*/
struct bb_rssi_su_acc_info bb_rssi_su_acc_i; /*acc RSSI*/
struct bb_rssi_su_avg_info bb_rssi_su_avg_i; /*avg RSSI*/
struct bb_physts_hist_th_info bb_physts_hist_th_i;
struct bb_physts_hist_info bb_physts_hist_i; /*phy-sts histogram*/
struct bb_physts_acc_info bb_physts_acc_i; /*acc phy-sts*/
struct bb_physts_avg_info bb_physts_avg_i; /*avg phy-sts*/
struct bb_physts_pop_info bb_physts_pop_i; /*pop info*/
/*[MU]*/
struct bb_pkt_cnt_mu_info bb_pkt_cnt_mu_i; /*Packet count*/
struct bb_rssi_mu_acc_info bb_rssi_mu_acc_i; /*acc RSSI*/
struct bb_rssi_mu_avg_info bb_rssi_mu_avg_i; /*avg RSSI*/
struct bb_pkt_cnt_su_store_info bb_pkt_cnt_su_store_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
u16 halbb_get_plurality_rx_rate_mu(struct bb_info *bb);
u16 halbb_get_plurality_rx_rate_su(struct bb_info *bb);
void halbb_show_phy_hitogram_su(struct bb_info *bb);
void halbb_show_rssi_and_rate_distribution_mu(struct bb_info *bb);
void halbb_show_rssi_and_rate_distribution_su(struct bb_info *bb);
void halbb_rx_pkt_cnt_rpt_reset(struct bb_info *bb);
void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc);
void halbb_cmn_info_rpt_store_data(struct bb_info *bb);
void halbb_cmn_info_rpt_reset(struct bb_info *bb);
void halbb_cmn_rpt_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_cmn_rpt.h
|
C
|
agpl-3.0
| 4,954
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CMN_RPT_EX_H__
#define __HALBB_CMN_RPT_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_rssi_mu_avg_info { /*all in U(8,1)*/
u8 rssi_t_avg;
u8 rssi_t[HALBB_MAX_PATH]; /*VHT, HE*/
};
struct bb_rssi_su_avg_info { /*all in U(8,1)*/
u8 rssi_cck_avg;
u8 rssi_cck[HALBB_MAX_PATH];
u8 rssi_ofdm_avg;
u8 rssi_ofdm[HALBB_MAX_PATH]; /*L-OFDM*/
u8 rssi_t_avg;
u8 rssi_t[HALBB_MAX_PATH]; /*HT, VHT, HE*/
};
struct bb_pkt_cnt_mu_info {
/*====[Phy rate counter]=============================================*/
u16 pkt_cnt_all; /*VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 pkt_cnt_1ss; /*VHT, HE*/
u16 pkt_cnt_2ss; /*VHT, HE*/
u16 pkt_cnt_sc20[LOW_BW_RATE_NUM]; /*@20M SC*/
bool sc20_occur;
/*VHT*/
u16 pkt_cnt_vht[VHT_RATE_NUM];
u16 pkt_cnt_sc40[LOW_BW_RATE_NUM]; /*@40M SC*/
bool vht_pkt_not_zero;
bool sc40_occur;
/*HE*/
u16 pkt_cnt_he[HE_RATE_NUM];
bool he_pkt_not_zero;
};
struct bb_pkt_cnt_su_store_info {
bool ht_pkt_not_zero;
bool vht_pkt_not_zero;
bool he_pkt_not_zero;
};
struct bb_pkt_cnt_su_info {
/*====[Phy rate counter]=============================================*/
u16 pkt_cnt_all; /*CCK + OFDM + HT, VHT, HE*/
u16 pkt_cnt_cck;
u16 pkt_cnt_ofdm; /*L-OFDM*/
u16 pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 pkt_cnt_1ss; /*HT, VHT, HE*/
u16 pkt_cnt_2ss; /*HT, VHT, HE*/
/*Legacy*/
u16 pkt_cnt_legacy[LEGACY_RATE_NUM];
/*HT*/
u16 pkt_cnt_ht[HT_RATE_NUM];
u16 pkt_cnt_sc20[LOW_BW_RATE_NUM]; /*@20M SC*/
bool ht_pkt_not_zero;
bool sc20_occur;
/*VHT*/
u16 pkt_cnt_vht[VHT_RATE_NUM];
u16 pkt_cnt_sc40[LOW_BW_RATE_NUM]; /*@40M SC*/
bool vht_pkt_not_zero;
bool sc40_occur;
/*HE*/
u16 pkt_cnt_he[HE_RATE_NUM];
u16 pkt_cnt_sc80[LOW_BW_RATE_NUM]; /*@80M SC*/
bool he_pkt_not_zero;
bool sc80_occur;
/*non_data packet*/
u16 pkt_cnt_legacy_non_data[LEGACY_RATE_NUM];
u16 pkt_cnt_else_non_data;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_get_rx_pkt_cnt_rpt_su(struct bb_info *bb, struct bb_pkt_cnt_su_info *pkt_cnt_rpt);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_cmn_rpt_ex.h
|
C
|
agpl-3.0
| 3,283
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_DBCC_SUPPORT
struct bb_info *halbb_get_curr_bb_pointer(struct bb_info *bb,
enum phl_phy_idx phy_idx)
{
if (phy_idx == bb->bb_phy_idx) {
BB_DBG(bb, DBG_DBCC, "new_phy_idx(%d) = curr_bb_phy_idx(%d)\n", phy_idx, bb->bb_phy_idx);
return bb;
} else {
BB_DBG(bb, DBG_DBCC, "new_phy_idx(%d) != curr_bb_phy_idx(%d)\n", phy_idx, bb->bb_phy_idx);
if (bb->bb_phy_hooker) {
return bb->bb_phy_hooker;
} else {
BB_WARNING("[%s] bb_phy_hooker==NULL", __func__);
return bb;
}
}
}
void halbb_dbcc_demo_func(struct bb_info *bb)
{
BB_DBG(bb, DBG_DBCC, "[%s]phy_idx={%d}\n", __func__, bb->bb_phy_idx);
}
u32
halbb_buffer_init_phy1(struct bb_info *bb_0)
{
struct bb_info *bb_1 = NULL;
if (!bb_0) {
BB_WARNING("[%s]*bb_phy_0 = NULL\n", __func__);
return RTW_HAL_STATUS_BB_INIT_FAILURE;
}
bb_1 = halbb_mem_alloc(bb_0, sizeof(struct bb_info));
if (!bb_1) {
BB_WARNING("[%s]*bb_phy_1 = NULL\n", __func__);
return RTW_HAL_STATUS_BB_INIT_FAILURE;
}
bb_1->bb_phy_hooker = bb_0;
bb_1->bb_phy_idx = HW_PHY_1;
bb_0->bb_phy_hooker = bb_1;
bb_1->bb_phy_hooker = bb_0;
bb_1->bb_cmn_hooker = bb_0->bb_cmn_hooker;
bb_1->phl_com = bb_0->phl_com;/*shared memory for all components*/
bb_1->hal_com = bb_0->hal_com;/*shared memory for phl and hal*/
//bb_phy_1->phl_sta_info = bb_phy_0->phl_sta_info;
halbb_dbg_comp_init(bb_1);
halbb_cmn_info_self_init(bb_1);
//halbb_timer_ctrl(bb_1, BB_INIT_TIMER);
//halbb_dm_init(bb_1, bb->bb_phy_idx);
BB_DBG(bb_0, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_0->bb_phy_idx, bb_1->bb_phy_idx);
BB_DBG(bb_1, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_0->bb_phy_idx, bb_1->bb_phy_idx);
BB_DBG(bb_0, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_1->bb_phy_hooker->bb_phy_idx, bb_0->bb_phy_hooker->bb_phy_idx);
BB_DBG(bb_1, DBG_DBCC, "phy_idx[0,1]={%d, %d}\n", bb_1->bb_phy_hooker->bb_phy_idx, bb_0->bb_phy_hooker->bb_phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
void halbb_dbcc_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u16 i = 0;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"phy {0/1}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"init\n");
return;
}
if (_os_strcmp(input[1], "phy") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
if (val[0] == 1)
bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx = HW_PHY_1;
else
bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx = HW_PHY_0;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"echo cmd convert to phy-%d mode\n",
bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx);
bb = halbb_get_curr_bb_pointer(bb, bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb_phy_idx=%d\n", bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "init") == 0) {
//for (i = 0; i < 4; i++) {
// HALBB_SCAN(input[2 + i], DCMD_DECIMAL, &val[i]);
//}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[DBG]phy_idx={%d}\n", bb->bb_phy_idx);
BB_DBG(bb, DBG_DBCC, "phy0->phy1\n");
bb = halbb_get_curr_bb_pointer(bb, HW_PHY_1); /*phy0->phy1*/
BB_DBG(bb, DBG_DBCC, "phy1->phy1\n");
bb = halbb_get_curr_bb_pointer(bb, HW_PHY_1); /*phy1->phy1*/
BB_DBG(bb, DBG_DBCC, "phy1->phy0\n");
bb = halbb_get_curr_bb_pointer(bb, HW_PHY_0); /*phy1->phy0*/
BB_DBG(bb, DBG_DBCC, "phy0->phy0\n");
bb = halbb_get_curr_bb_pointer(bb, HW_PHY_0); /*phy0->phy0*/
BB_DBG(bb, DBG_DBCC, "phy0->phy1\n");
bb = halbb_get_curr_bb_pointer(bb, HW_PHY_1); /*phy0->phy1*/
//halbb_buffer_init_phy1(bb);
//halbb_dbg_comp_init(bb);
//halbb_dm_init(bb, bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[DBG]phy_idx={%d} Init OK\n", bb->bb_phy_idx);
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbcc.c
|
C
|
agpl-3.0
| 4,916
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBCC_H__
#define __HALBB_DBCC_H__
#ifdef HALBB_DBCC_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_dbcc_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
struct bb_info *halbb_get_curr_bb_pointer(struct bb_info *bb,
enum phl_phy_idx phy_idx);
u32 halbb_buffer_init_phy1(struct bb_info *bb_phy_0);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbcc.h
|
C
|
agpl-3.0
| 1,640
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBCC_EX_H__
#define __HALBB_DBCC_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbcc_ex.h
|
C
|
agpl-3.0
| 1,356
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#define HALBB_DBG_DVLP_FLAG 1
void halbb_dbg_comp_init(struct bb_info *bb)
{
#if 0
if (bb->phl_com->bb_dbg_comp_manual_cfg != 0xffffffff) {
bb->dbg_component = bb->phl_com->bb_dbg_comp_manual_cfg;
return;
}
#endif
bb->dbg_component =
/*DBG_RA | */
/*DBG_FA_CNT | */
/*DBG_RSSI_MNTR | */
/*DBG_DFS | */
/*DBG_EDCCA | */
/*DBG_ENV_MNTR | */
/*DBG_CFO_TRK | */
/*DBG_PHY_STATUS | */
/*DBG_COMMON_FLOW | */
/*DBG_IC_API | */
/*DBG_DBG_API | */
/*DBG_DBCC | */
/*DBG_DM_SUMMARY | */
/*DBG_PHY_CONFIG | */
/*DBG_INIT | */
/*DBG_DIG | */
/*DBG_CMN | */
0;
BB_DBG(bb, DBG_INIT, "dbg_comp = 0x%llx\n", bb->dbg_component);
}
#ifdef HALBB_TDMA_CR_SUPPORT
void halbb_tdma_cr_sel_io_en(struct bb_info *bb)
{
BB_DBG(bb, DBG_DBG_API, "[%s]===>\n", __func__);
halbb_tdma_cr_sel_main(bb);
}
void halbb_tdma_cr_sel_callback(void *context)
{
struct bb_info *bb = (struct bb_info *)context;
struct halbb_timer_info *timer = &bb->bb_dbg_i.tdma_cr_timer_i;
BB_DBG(bb, DBG_DBG_API, "[%s]===>\n", __func__);
timer->timer_state = BB_TIMER_IDLE;
if (bb->phl_com->hci_type == RTW_HCI_PCIE)
halbb_tdma_cr_sel_io_en(bb);
else
rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx);
}
void halbb_tdma_cr_timer_init(struct bb_info *bb)
{
struct halbb_timer_info *timer = &bb->bb_dbg_i.tdma_cr_timer_i;
BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__);
timer->event_idx = BB_EVENT_TIMER_TDMA_CR;
timer->timer_state = BB_TIMER_IDLE;
halbb_init_timer(bb, &timer->timer_list, halbb_tdma_cr_sel_callback, bb, "halbb_tdma_cr");
}
void halbb_tdma_cr_sel_main(struct bb_info *bb)
{
struct bb_dbg_info *dbg = &bb->bb_dbg_i;
u32 period = 0;
u32 val_new = 0, val_old = 0;
if (!dbg->tdma_cr_en) {
BB_DBG(bb, DBG_DBG_API, "[%s] tdma_cr_en = %d\n", __func__, dbg->tdma_cr_en);
return;
}
if (dbg->tdma_cr_state == 0) {
val_old = dbg->tdma_cr_val_1;
val_new = dbg->tdma_cr_val_0;
period = dbg->tdma_cr_period_0;
dbg->tdma_cr_state = 1; /*CR0*/
} else { /*PFD_LEGACY*/
val_old = dbg->tdma_cr_val_0;
val_new = dbg->tdma_cr_val_1;
period = dbg->tdma_cr_period_1;
dbg->tdma_cr_state= 0; /*CR1*/
}
halbb_set_reg(bb, dbg->tdma_cr_idx, dbg->tdma_cr_mask, val_new);
dbg->tdma_cr_timer_i.cb_time = period;
halbb_cfg_timers(bb, BB_SET_TIMER, &dbg->tdma_cr_timer_i);
BB_DBG(bb, DBG_DBG_API, "Reg 0x%x[0x%x] = {0x%x -> 0x%x}, period=%d ms\n",
dbg->tdma_cr_idx, dbg->tdma_cr_mask,
val_old , val_new, period);
}
void halbb_tdma_cr_sel_deinit(struct bb_info *bb)
{
BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__);
}
void halbb_tdma_cr_sel_init(struct bb_info *bb)
{
struct bb_dbg_info *dbg = &bb->bb_dbg_i;
BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__);
dbg->tdma_cr_en = false;
dbg->tdma_cr_period_0 = 50;
dbg->tdma_cr_period_1 = 50;
dbg->tdma_cr_idx = 0;
dbg->tdma_cr_state = 0;
}
#endif
#if 1 /*debug port - relative*/
void halbb_bb_dbg_port_clock_en(struct bb_info *bb, u8 enable)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
u32 reg_value = 0;
reg_value = enable ? 1 : 0;
halbb_set_reg(bb, cr->clk_en, cr->clk_en_m, reg_value);
halbb_set_reg(bb, cr->dbgport_en, cr->dbgport_en_m, reg_value);
}
u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
u32 val = 0;
u32 dbg_port, ip;
ip = halbb_get_reg(bb, cr->dbgport_ip, cr->dbgport_ip_m);
dbg_port = halbb_get_reg(bb, cr->dbgport_idx, cr->dbgport_idx_m);
val = (ip << 8) | (dbg_port & 0xff);
return val;
}
void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
halbb_set_reg(bb, cr->dbgport_ip, cr->dbgport_ip_m, ip);
}
void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
halbb_set_reg(bb, cr->dbgport_idx, cr->dbgport_idx_m, dbg_port);
}
bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority)
{
bool dbg_port_result = false;
if (curr_dbg_priority > bb->pre_dbg_priority) {
halbb_bb_dbg_port_clock_en(bb, true);
BB_DBG(bb, DBG_DBG_API,
"DbgPort racing success, Cur_priority=((%d)), Pre_priority=((%d))\n",
curr_dbg_priority, bb->pre_dbg_priority);
bb->pre_dbg_priority = curr_dbg_priority;
dbg_port_result = true;
}
return dbg_port_result;
}
void halbb_release_bb_dbg_port(struct bb_info *bb)
{
halbb_bb_dbg_port_clock_en(bb, false);
bb->pre_dbg_priority = DBGPORT_RELEASE;
BB_DBG(bb, DBG_DBG_API, "Release BB dbg_port\n");
}
u32 halbb_get_bb_dbg_port_val(struct bb_info *bb)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
u32 dbg_port_value = 0;
dbg_port_value = halbb_get_reg(bb, cr->dbgport_val, cr->dbgport_val_m);
BB_DBG(bb, DBG_DBG_API, "dbg_port_value = 0x%x\n", dbg_port_value);
return dbg_port_value;
}
void halbb_dbgport_dump_all(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_dbgport_dump_all_8852a(bb, _used, output, _out_len);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_dbgport_dump_all_8852a_2(bb, _used, output, _out_len);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_dbgport_dump_all_8852b(bb, _used, output, _out_len);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_dbgport_dump_all_8852c(bb, _used, output, _out_len);
break;
#endif
default:
break;
}
}
void halbb_dbgport_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u32 dp = 0; /*debug port value*/
u8 dbg[32];
u8 tmp = 0;
u8 i;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{dbg_port_ip} {dbg_port_idx}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{dump_all}\n");
return;
}
if (!halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{Racing Fail}\n");
return;
}
if (_os_strcmp(input[1], "dump_all") == 0) {
halbb_dbgport_dump_all(bb, _used, output, _out_len);
return;
} else {
HALBB_SCAN(input[1], DCMD_HEX, &val[0]);
HALBB_SCAN(input[2], DCMD_HEX, &val[1]);
halbb_set_bb_dbg_port_ip(bb, (enum bb_dbg_port_ip_t)val[0]);
halbb_set_bb_dbg_port(bb, val[1]);
dp = halbb_get_bb_dbg_port_val(bb);
halbb_release_bb_dbg_port(bb);
for (i = 0; i < 32; i++)
dbg[i] = (u8)((dp & BIT(i)) >> i);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Dbg Port[0x%02x, 0x%03x] = 0x08%x\n", val[0], val[1], dp);
for (i = 4; i != 0; i--) {
tmp = 8 * (i - 1);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"val[%02d:%02d] = 8b'%d %d %d %d %d %d %d %d\n",
tmp + 7, tmp, dbg[tmp + 7], dbg[tmp + 6],
dbg[tmp + 5], dbg[tmp + 4], dbg[tmp + 3],
dbg[tmp + 2], dbg[tmp + 1], dbg[tmp + 0]);
}
}
}
#endif
#if HALBB_DBG_DVLP_FLAG /*Common debug message - relative*/
void halbb_rx_rate_distribution_su_cnsl(struct bb_info *bb, u32 *_used,
char *output, u32 *_out_len)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
u8 i = 0;
u8 rate_num = bb->num_rf_path, ss_ofst = 0;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, "[RxRate Cnt] =============>\n");
/*@======CCK=========================================================*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"* CCK = {%d, %d, %d, %d}\n",
pkt_cnt->pkt_cnt_legacy[0], pkt_cnt->pkt_cnt_legacy[1],
pkt_cnt->pkt_cnt_legacy[2], pkt_cnt->pkt_cnt_legacy[3]);
/*@======OFDM========================================================*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
pkt_cnt->pkt_cnt_legacy[4], pkt_cnt->pkt_cnt_legacy[5],
pkt_cnt->pkt_cnt_legacy[6], pkt_cnt->pkt_cnt_legacy[7],
pkt_cnt->pkt_cnt_legacy[8], pkt_cnt->pkt_cnt_legacy[9],
pkt_cnt->pkt_cnt_legacy[10], pkt_cnt->pkt_cnt_legacy[11]);
/*@======HT==========================================================*/
for (i = 0; i < rate_num; i++) {
ss_ofst = (i << 3);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_ofst), (ss_ofst + 7),
pkt_cnt->pkt_cnt_ht[ss_ofst + 0],
pkt_cnt->pkt_cnt_ht[ss_ofst + 1],
pkt_cnt->pkt_cnt_ht[ss_ofst + 2],
pkt_cnt->pkt_cnt_ht[ss_ofst + 3],
pkt_cnt->pkt_cnt_ht[ss_ofst + 4],
pkt_cnt->pkt_cnt_ht[ss_ofst + 5],
pkt_cnt->pkt_cnt_ht[ss_ofst + 6],
pkt_cnt->pkt_cnt_ht[ss_ofst + 7]);
}
/*@======VHT==========================================================*/
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"* VHT-%d ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_vht[ss_ofst + 0],
pkt_cnt->pkt_cnt_vht[ss_ofst + 1],
pkt_cnt->pkt_cnt_vht[ss_ofst + 2],
pkt_cnt->pkt_cnt_vht[ss_ofst + 3],
pkt_cnt->pkt_cnt_vht[ss_ofst + 4],
pkt_cnt->pkt_cnt_vht[ss_ofst + 5],
pkt_cnt->pkt_cnt_vht[ss_ofst + 6],
pkt_cnt->pkt_cnt_vht[ss_ofst + 7],
pkt_cnt->pkt_cnt_vht[ss_ofst + 8],
pkt_cnt->pkt_cnt_vht[ss_ofst + 9],
pkt_cnt->pkt_cnt_vht[ss_ofst + 10],
pkt_cnt->pkt_cnt_vht[ss_ofst + 11]);
}
/*@======HE==========================================================*/
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"* HE-%d ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_he[ss_ofst + 0],
pkt_cnt->pkt_cnt_he[ss_ofst + 1],
pkt_cnt->pkt_cnt_he[ss_ofst + 2],
pkt_cnt->pkt_cnt_he[ss_ofst + 3],
pkt_cnt->pkt_cnt_he[ss_ofst + 4],
pkt_cnt->pkt_cnt_he[ss_ofst + 5],
pkt_cnt->pkt_cnt_he[ss_ofst + 6],
pkt_cnt->pkt_cnt_he[ss_ofst + 7],
pkt_cnt->pkt_cnt_he[ss_ofst + 8],
pkt_cnt->pkt_cnt_he[ss_ofst + 9],
pkt_cnt->pkt_cnt_he[ss_ofst + 10],
pkt_cnt->pkt_cnt_he[ss_ofst + 11]);
}
/*@======SC_BW========================================================*/
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"*[Low BW 20M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_sc20[ss_ofst + 0],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 1],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 2],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 3],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 4],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 5],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 6],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 7],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 8],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 9],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 10],
pkt_cnt->pkt_cnt_sc20[ss_ofst + 11]);
}
for (i = 0; i < rate_num; i++) {
ss_ofst = 12 * i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"*[Low BW 40M] %d-ss MCS[0:11] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
pkt_cnt->pkt_cnt_sc40[ss_ofst + 0],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 1],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 2],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 3],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 4],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 5],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 6],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 7],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 8],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 9],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 10],
pkt_cnt->pkt_cnt_sc40[ss_ofst + 11]);
}
}
u16 halbb_rx_utility(struct bb_info *bb, u16 avg_phy_rate, u8 rx_max_ss,
enum channel_width bw)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
u16 utility_primitive = 0, utility = 0;
if (pkt_cnt->he_pkt_not_zero) {
/*@ HE 1SS MCS11[3.2] 20M: tp = 122, 1000/122 = 8.2, 122*8.25 = 1006.5*/
utility_primitive = avg_phy_rate * 8 + (avg_phy_rate >> 2);
} else if (pkt_cnt->vht_pkt_not_zero) {
/*@ VHT 1SS MCS9(fake) 20M: tp = 87, 1000/87 = 11.49, 87*11.5 = 1000.5*/
utility_primitive = avg_phy_rate * 11 + (avg_phy_rate >> 1);
} else if (pkt_cnt->ht_pkt_not_zero) {
/*@ MCS7 20M: tp = 65, 1000/65 = 15.38, 65*15.5 = 1007*/
utility_primitive = avg_phy_rate * 15 + (avg_phy_rate >> 1);
} else {
/*@ 54M, 1000/54 = 18.5, 54*18.5 = 999*/
utility_primitive = avg_phy_rate * 18 + (avg_phy_rate >> 1);
}
utility = (utility_primitive / rx_max_ss) >> bw;
if (utility > 1000)
utility = 1000;
return utility;
}
u16 halbb_rx_avg_phy_rate(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
u16 i = 0;
u8 base = LEGACY_RATE_NUM;
u16 rate = 0;
u32 pkt_cnt_tmp = 0, phy_rate_sum = 0;
enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw;
//BB_DBG(bb, DBG_CMN, "bw=%d\n", bb->hal_com->band[0].cur_chandef.bw);
if (pkt_cnt->he_pkt_not_zero) {
/*HE Mode*/
for (i = 0; i < HE_RATE_NUM; i++) {
if (pkt_cnt->pkt_cnt_he[i] == 0)
continue;
rate = VHT_2_HE32_RATE(bb_phy_rate_table[i + base] << bw);
phy_rate_sum += pkt_cnt->pkt_cnt_he[i] * rate;
pkt_cnt_tmp += pkt_cnt->pkt_cnt_he[i];
//BB_DBG(bb, DBG_CMN, "HE sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_he[i], rate, i + base, pkt_cnt_tmp);
}
} else if (pkt_cnt->vht_pkt_not_zero) {
/*VHT Mode*/
for (i = 0; i < VHT_RATE_NUM; i++) {
if (pkt_cnt->pkt_cnt_vht[i] == 0)
continue;
rate = bb_phy_rate_table[i + base] << bw;
phy_rate_sum += pkt_cnt->pkt_cnt_vht[i] * rate;
pkt_cnt_tmp += pkt_cnt->pkt_cnt_vht[i];
//BB_DBG(bb, DBG_CMN, "VHT sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_vht[i], rate, i + base, pkt_cnt_tmp);
}
} else if (pkt_cnt->ht_pkt_not_zero) {
/*HT Mode*/
for (i = 0; i < HT_RATE_NUM; i++) {
if (pkt_cnt->pkt_cnt_ht[i] == 0)
continue;
rate = bb_phy_rate_table[i + base] << bw;
phy_rate_sum += pkt_cnt->pkt_cnt_ht[i] * rate;
pkt_cnt_tmp += pkt_cnt->pkt_cnt_ht[i];
//BB_DBG(bb, DBG_CMN, "HT sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_ht[i], rate, i + base, pkt_cnt_tmp);
}
} else {
/*Legacy mode*/
for (i = BB_01M; i <= BB_54M; i++) {
/*SKIP beacon*/
if (i == cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate)
continue;
if (pkt_cnt->pkt_cnt_legacy[i] == 0)
continue;
rate = bb_phy_rate_table[i];
phy_rate_sum += pkt_cnt->pkt_cnt_legacy[i] * rate;
pkt_cnt_tmp += pkt_cnt->pkt_cnt_legacy[i];
//BB_DBG(bb, DBG_CMN, "LAG sum:%d +={%d * %d} idx=%d cnt=%d\n", phy_rate_sum, pkt_cnt->pkt_cnt_legacy[i], rate, i + base, pkt_cnt_tmp);
}
}
/*SC Data*/
if (pkt_cnt->sc40_occur) {
for (i = 0; i < LOW_BW_RATE_NUM; i++) {
if (pkt_cnt->pkt_cnt_sc40[i] == 0)
continue;
rate = bb_phy_rate_table[i + base] << CHANNEL_WIDTH_40;
phy_rate_sum += pkt_cnt->pkt_cnt_sc40[i] * rate;
pkt_cnt_tmp += pkt_cnt->pkt_cnt_sc40[i];
}
}
if (pkt_cnt->sc20_occur) {
for (i = 0; i < LOW_BW_RATE_NUM; i++) {
if (pkt_cnt->pkt_cnt_sc20[i] == 0)
continue;
rate = bb_phy_rate_table[i + base];
phy_rate_sum += pkt_cnt->pkt_cnt_sc20[i] * rate;
pkt_cnt_tmp += pkt_cnt->pkt_cnt_sc20[i];
}
}
//BB_DBG(bb, DBG_CMN, "sum=%d, cnt=%d\n", phy_rate_sum, pkt_cnt_tmp);
return (u16)HALBB_DIV(phy_rate_sum, pkt_cnt_tmp); /*avg_phy_rate*/
}
void halbb_basic_dbg_msg_mac_phy_intf(struct bb_info *bb)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
s32 pw = 0;
//u8 i = 0, usr_ofst = 0;
u32 tmp_32 = 0;
u32 tx_pw = 0, l_sig = 0, sig_a1 = 0, sig_a2 = 0;
u8 txpath_en =0, type = 0, mcs = 0;
char ppdu[][10] = {{"L-CCK"}, {"S-CCK"}, {"Legacy"}, {"HT"},
{"HT GF"}, {"VHT SU"}, {"VHT MU"}, {"HE SU"},
{"HE ER SU"}, {"HE MU"}, {"HE TB"}};
char gi_type[][4] = {{"0.4"}, {"0.8"}, {"1.6"}, {"3.2"}};
char fec_type[][5] = {{"BCC"}, {"LDPC"}};
char *txcmd = NULL;
u8 txcmd2 = 0;
bool no_txcmd_hit = false;
if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL)
return;
txpath_en = (u8)halbb_get_reg(bb, cr->mac_phy_txpath_en, 0xF000);
l_sig = halbb_get_reg(bb, cr->mac_phy_lsig, MASKDWORD);
tx_pw = halbb_get_reg(bb, cr->mac_phy_tx_pw, 0x7FC0000);
if ((txpath_en == 0) && (l_sig == 0) && (tx_pw == 0)) {
BB_DBG(bb, DBG_CMN,
"[MAC/PHY Intf]Txinfo is empty!BB reset has been probably toggled.\n");
return;
}
type = (u8)halbb_get_reg(bb, cr->mac_phy_ppdu_type, 0xf);
mcs = (u8)(halbb_get_reg(bb, cr->mac_phy_mcs_3_0, 0xf0000000) +
(halbb_get_reg(bb, cr->mac_phy_mcs_5_4, 0x3) << 4));
halbb_print_sign_frac_digit(bb, tx_pw, 9, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE);
tmp_32 = halbb_get_reg(bb, cr->mac_phy_txcmd, 0x3f000000);
switch (tmp_32) {
case 0:
txcmd = "data";
break;
case 1:
txcmd = "beacon";
break;
case 2:
txcmd = "HT-NDPA";
break;
case 3:
txcmd = "VHT-NDPA";
break;
case 4:
txcmd = "HE-NDPA";
break;
case 8:
txcmd = "RTS";
break;
case 9:
txcmd = "CTS2self";
break;
case 10:
txcmd = "CF_end";
break;
case 11:
txcmd = "compressed-BAR";
break;
case 12:
txcmd = "BFRP";
break;
case 13:
txcmd = "NDP";
break;
case 14:
txcmd = "QoS_Null";
break;
case 16:
txcmd = "ACK";
break;
case 17:
txcmd = "CTS";
break;
case 18:
txcmd = "compressed-BA";
break;
case 19:
txcmd = "Multi-STA-BA";
break;
case 20:
txcmd = "HT-CSI";
break;
case 21:
txcmd = "VHT-CSI";
break;
case 22:
txcmd = "HE-CSI";
break;
case 31:
txcmd = "TB_PPDU";
break;
case 32:
txcmd = "TRIG-BASIC";
break;
case 33:
txcmd = "TRIG-BFRP";
break;
case 34:
txcmd = "TRIG-MUBAR";
break;
case 35:
txcmd = "TRIG-MU-RTS";
break;
case 36:
txcmd = "TRIG-BSRP";
break;
case 37:
txcmd = "TRIG-BQRP";
break;
case 38:
txcmd = "TRIG-NFRP";
break;
case 48:
txcmd = "TRIG-BASIC-DATA";
break;
default:
txcmd = "RSVD";
txcmd2 = (u8)tmp_32;
no_txcmd_hit = true;
break;
}
if (no_txcmd_hit)
BB_DBG(bb, DBG_CMN,
"[MAC/PHY Intf][%s][RSVD-%d] BW=%dM, TxSC=%d, TxPw=%s dBm, TxPathEn=%d\n",
ppdu[type], txcmd2,
20 << (halbb_get_reg(bb, cr->mac_phy_bw, 0x30000)),
halbb_get_reg(bb, cr->mac_phy_txsc, 0xf0),
bb->dbg_buf, txpath_en);
else
BB_DBG(bb, DBG_CMN,
"[MAC/PHY Intf][%s][%s] BW=%dM, TxSC=%d, TxPw=%s dBm, TxPathEn=%d\n",
ppdu[type], txcmd,
20 << (halbb_get_reg(bb, cr->mac_phy_bw, 0x30000)),
halbb_get_reg(bb, cr->mac_phy_txsc, 0xf0),
bb->dbg_buf, txpath_en);
BB_DBG(bb, DBG_CMN,
"User_num=%d, STBC=%d, FEC=%s, GILTF=%dx%s, NDP_en=%d, N_sts=%d, MCS=%d\n",
halbb_get_reg(bb, cr->mac_phy_n_usr, 0xff0),
halbb_get_reg(bb, cr->mac_phy_stbc, BIT(0)),
fec_type[halbb_get_reg(bb, cr->mac_phy_fec, BIT(27))],
1 << halbb_get_reg(bb, cr->mac_phy_ltf, 0xC0),
gi_type[halbb_get_reg(bb, cr->mac_phy_gi, 0x30)],
halbb_get_reg(bb, cr->mac_phy_ndp_en, BIT(4)),
halbb_get_reg(bb, cr->mac_phy_n_sts, 0x7000000), mcs);
/*SIG*/
tmp_32 = halbb_get_reg(bb, cr->mac_phy_siga_0, MASKDWORD);
if (type > 6) { // === HE === //
sig_a1 = tmp_32 & 0x3ffffff;
sig_a2 = (halbb_get_reg(bb, cr->mac_phy_siga_1, 0xfffff) << 6) |
((tmp_32 & 0xfc000000) >> 26);
} else if (type > 2) { // === HT / VHT === //
sig_a1 = tmp_32 & 0xffffff;
sig_a2 = (halbb_get_reg(bb, cr->mac_phy_siga_1, 0xffff) << 8) |
((tmp_32 & 0xff000000) >> 24);
}
BB_DBG(bb, DBG_CMN, "SIG-L/A1/A2= {0x%08x, 0x%08x, 0x%08x}\n", l_sig, sig_a1,
sig_a2);
#if 0
BB_DBG(bb, DBG_CMN, "============ [User-specified Info] ============\n");
for (i = 0; i < n_user; i++) {
BB_DBG(bb, DBG_CMN, "------------- [User-%d] -------------\n", i);
usr_ofst = i << 3;
/* FEC */
txinfo_value = halbb_get_reg(bb, 0x4718 + usr_ofst, BIT(27));
BB_DBG(bb, DBG_CMN, "FEC: %s\n", fec_type[txinfo_value]);
/* MCS */
txinfo_value = (halbb_get_reg(bb, 0x471c + usr_ofst, BIT(1) |
BIT(0)) << 4) + halbb_get_reg(bb, 0x4718 +
usr_ofst,
0xf0000000);
BB_DBG(bb, DBG_CMN, "MCS: %d\n", txinfo_value);
/* DCM */
txinfo_value = halbb_get_reg(bb, 0x471c + usr_ofst, BIT(2));
BB_DBG(bb, DBG_CMN, "DCM En: %d\n", txinfo_value);
/* TxBF */
txinfo_value = halbb_get_reg(bb, 0x471c + usr_ofst, BIT(14));
BB_DBG(bb, DBG_CMN, "TxBF En: %d\n", txinfo_value);
}
#endif
}
void halbb_basic_dbg_msg_pmac(struct bb_info *bb)
{
#ifdef HALBB_STATISTICS_SUPPORT
struct bb_stat_info *stat = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat->bb_fa_i;
struct bb_cck_fa_info *cck_fa = &fa->bb_cck_fa_i;
struct bb_legacy_fa_info *legacy_fa = &fa->bb_legacy_fa_i;
struct bb_ht_fa_info *ht_fa = &fa->bb_ht_fa_i;
struct bb_vht_fa_info *vht_fa = &fa->bb_vht_fa_i;
struct bb_he_fa_info *he_fa = &fa->bb_he_fa_i;
struct bb_cca_info *cca = &stat->bb_cca_i;
struct bb_crc_info *crc = &stat->bb_crc_i;
//struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL)
return;
BB_DBG(bb, DBG_CMN,
"[Tx]{CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON}: {%d, %d, %d, %d}\n",
stat->bb_tx_cnt_i.cck_mac_txen, stat->bb_tx_cnt_i.cck_phy_txon,
stat->bb_tx_cnt_i.ofdm_mac_txen,
stat->bb_tx_cnt_i.ofdm_phy_txon);
BB_DBG(bb, DBG_CMN,
"[CRC]{B/G/N/AC/AX/All} OK:{%d, %d, %d, %d, %d, %d} Err:{%d, %d, %d, %d, %d, %d}\n",
crc->cnt_cck_crc32_ok, crc->cnt_ofdm_crc32_ok,
crc->cnt_ht_crc32_ok, crc->cnt_vht_crc32_ok,
crc->cnt_he_crc32_ok, crc->cnt_crc32_ok_all,
crc->cnt_cck_crc32_error, crc->cnt_ofdm_crc32_error,
crc->cnt_ht_crc32_error, crc->cnt_vht_crc32_error,
crc->cnt_he_crc32_error, crc->cnt_crc32_error_all);
BB_DBG(bb, DBG_CMN,
"[CCA]{CCK, OFDM, All}: %d, %d, %d\n",
cca->cnt_cck_cca, cca->cnt_ofdm_cca, cca->cnt_cca_all);
BB_DBG(bb, DBG_CMN,
"[FA]{CCK, OFDM, All}: %d, %d, %d\n",
fa->cnt_cck_fail, fa->cnt_ofdm_fail, fa->cnt_fail_all);
BB_DBG(bb, DBG_CMN,
" *[CCK]sfd/sig_GG=%d/%d, *[OFDM]Prty=%d, Rate=%d, LSIG_brk_s/l=%d/%d, SBD=%d\n",
cck_fa->sfd_gg_cnt, cck_fa->sig_gg_cnt,
legacy_fa->cnt_parity_fail, legacy_fa->cnt_rate_illegal,
legacy_fa->cnt_lsig_brk_s_th, legacy_fa->cnt_lsig_brk_l_th,
legacy_fa->cnt_sb_search_fail);
BB_DBG(bb, DBG_CMN,
" *[HT]CRC8=%d, MCS=%d, *[VHT]SIGA_CRC8=%d, MCS=%d\n",
ht_fa->cnt_crc8_fail, ht_fa->cnt_mcs_fail,
vht_fa->cnt_crc8_fail_vhta, vht_fa->cnt_mcs_fail_vht);
BB_DBG(bb, DBG_CMN,
" *[HE]SIGA_CRC4{SU/ERSU/MU}=%d/%d/%d, SIGB_CRC4{ch1/ch2}=%d/%d, MCS{nrml/bcc/dcm}=%d/%d/%d\n",
he_fa->cnt_crc4_fail_hea_su, he_fa->cnt_crc4_fail_hea_ersu,
he_fa->cnt_crc4_fail_hea_mu, he_fa->cnt_crc4_fail_heb_ch1_mu,
he_fa->cnt_crc4_fail_heb_ch2_mu, he_fa->cnt_mcs_fail_he,
he_fa->cnt_mcs_fail_he_bcc, he_fa->cnt_mcs_fail_he_dcm);
#endif
}
void halbb_basic_dbg_msg_rx_info(struct bb_info *bb)
{
struct bb_ch_info *ch = &bb->bb_ch_i;
#ifdef HALBB_CFO_TRK_SUPPORT
struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i;
#endif
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_cap_info *pkt_cnt_cap = &cmn_rpt->bb_pkt_cnt_all_i;
struct bb_physts_pop_info *pop_info = &cmn_rpt->bb_physts_pop_i;
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
u8 tmp = 0;
u32 bb_monitor1 = 0;
if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL)
return;
BB_DBG(bb, DBG_CMN, "rxsc_idx {Lgcy, 20, 40, 80} = {%d, %d, %d, %d}\n",
ch->rxsc_l, ch->rxsc_20, ch->rxsc_40, ch->rxsc_80);
BB_DBG(bb, DBG_CMN, "RX Pkt Cnt: LDPC=(%d), BCC=(%d), STBC=(%d), SU_BF=(%d), MU_BF=(%d), \n",
pkt_cnt_cap->pkt_cnt_ldpc, pkt_cnt_cap->pkt_cnt_bcc,
pkt_cnt_cap->pkt_cnt_stbc, pkt_cnt_cap->pkt_cnt_subf,
pkt_cnt_cap->pkt_cnt_mubf);
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_print_sign_frac_digit(bb, cfo_trk->cfo_avg_pre, 16, 2, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "CFO[T-1]=(%s kHz), cryst_cap=(%s%d), cfo_ofst=%d\n",
bb->dbg_buf,
((cfo_trk->crystal_cap > cfo_trk->def_x_cap) ? "+" : "-"),
DIFF_2(cfo_trk->crystal_cap, cfo_trk->def_x_cap),
cfo_trk->x_cap_ofst);
#endif
BB_DBG(bb, DBG_CMN, "Dly_sprd=(%d)\n", tmp);
BB_DBG(bb, DBG_CMN,
"[POP] cnt=%d, hist_cck/ofdm[0:3]={%d | %d, %d, %d}/{%d | %d, %d, %d}\n",
bb->bb_stat_i.bb_cca_i.pop_cnt,
pop_info->pop_hist_cck[0], pop_info->pop_hist_cck[1],
pop_info->pop_hist_cck[2], pop_info->pop_hist_cck[3],
pop_info->pop_hist_ofdm[0], pop_info->pop_hist_ofdm[1],
pop_info->pop_hist_ofdm[2], pop_info->pop_hist_ofdm[3]);
halbb_set_reg(bb, cr->bb_monitor_sel1, cr->bb_monitor_sel1_m, 1);
bb_monitor1 = halbb_get_reg(bb, cr->bb_monitor1, cr->bb_monitor1_m);
BB_DBG(bb, DBG_CMN, "BB monitor1 = (0x%x)\n", bb_monitor1);
}
void halbb_basic_dbg_msg_tx_info(struct bb_info *bb)
{
struct bb_ch_info *ch = &bb->bb_ch_i;
struct rtw_phl_stainfo_t *sta;
struct rtw_ra_sta_info *ra;
//char dbg_buf[HALBB_SNPRINT_SIZE] = {0};
u16 sta_cnt = 0;
u8 i = 0;
u8 tmp = 0;
u16 curr_tx_rt = 0;
enum rtw_gi_ltf curr_gi_ltf = RTW_GILTF_LGI_4XHE32;
enum hal_rate_bw curr_bw = HAL_RATE_BW_20;
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i])
continue;
sta = bb->phl_sta_info[i];
if (!is_sta_active(sta))
continue;
ra = &sta->hal_sta->ra_info;
curr_tx_rt = (u16)(ra->rpt_rt_i.mcs_ss_idx) | ((u16)(ra->rpt_rt_i.mode) << 7);
curr_gi_ltf = ra->rpt_rt_i.gi_ltf;
curr_bw = ra->rpt_rt_i.bw;
halbb_print_rate_2_buff(bb, curr_tx_rt, curr_gi_ltf, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "TxRate[%d]=%s (0x%x-%d), PER=(%d), TXBW=(%d)\n",
i, bb->dbg_buf, curr_tx_rt, curr_gi_ltf,
ra->curr_retry_ratio, (20<<curr_bw));
sta_cnt++;
if (sta_cnt >= bb->hal_com->assoc_sta_cnt)
break;
}
//BB_DBG(bb, DBG_CMN, "TSSI val=(%d)\n", tmp);
//BB_DBG(bb, DBG_CMN, "EDCA val=(%d)\n", tmp);
}
void halbb_basic_dbg_msg_physts_mu(struct bb_info *bb)
{
struct bb_ch_info *ch = &bb->bb_ch_i;
struct bb_link_info *link = &bb->bb_link_i;
if (bb->bb_cmn_rpt_i.bb_pkt_cnt_mu_i.pkt_cnt_all == 0) {
BB_DBG(bb, DBG_CMN, "NO MU pkt\n");
return;
}
/*RX Rate*/
halbb_print_rate_2_buff(bb, link->rx_rate_plurality_mu,
RTW_GILTF_LGI_4XHE32, bb->dbg_buf, 32);
BB_DBG(bb, DBG_CMN, "Plurality_RxRate:%s (0x%x)\n",
bb->dbg_buf, link->rx_rate_plurality);
/*RX Rate Distribution & RSSI*/
halbb_show_rssi_and_rate_distribution_mu(bb);
}
void halbb_basic_dbg_msg_physts_su(struct bb_info *bb)
{
struct bb_ch_info *ch = &bb->bb_ch_i;
struct bb_link_info *link = &bb->bb_link_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
//struct rtw_phl_stainfo_t *sta;
//char dbg_buf[HALBB_SNPRINT_SIZE] = {0};
char dbg_buf2[32] = {0};
u16 avg_phy_rate = 0, utility = 0;
/*RX Rate*/
halbb_print_rate_2_buff(bb, link->rx_rate_plurality,
RTW_GILTF_LGI_4XHE32, dbg_buf2, 32);
halbb_print_rate_2_buff(bb, cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate,
RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_CMN, "Plurality_RxRate:%s (0x%x), Bcn_Rate=%s (0x%x), Bcn_cnt=%d\n",
dbg_buf2, link->rx_rate_plurality,
bb->dbg_buf ,cmn_rpt->bb_pkt_cnt_bcn_i.beacon_phy_rate,
cmn_rpt->bb_pkt_cnt_bcn_i.pkt_cnt_beacon);
/*RX Rate Distribution & RSSI*/
halbb_show_rssi_and_rate_distribution_su(bb);
/*RX Utility*/
avg_phy_rate = halbb_rx_avg_phy_rate(bb);
utility = halbb_rx_utility(bb, avg_phy_rate, bb->num_rf_path, bb->hal_com->band[0].cur_chandef.bw);
BB_DBG(bb, DBG_CMN, "Avg_rx_rate = %d, rx_utility=( %d / 1000 )\n",
avg_phy_rate, utility);
}
void halbb_basic_dbg_message(struct bb_info *bb)
{
struct bb_link_info *link = &bb->bb_link_i;
struct bb_ch_info *ch = &bb->bb_ch_i;
struct bb_dbg_info *dbg = &bb->bb_dbg_i;
struct bb_physts_info *physts = &bb->bb_physts_i;
enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw;
u8 fc = bb->hal_com->band[0].cur_chandef.center_ch;
u8 sta_cnt = 0;
u8 i;
#ifdef HALBB_DBG_TRACE_SUPPORT
if (!(bb->dbg_component & DBG_CMN))
return;
if (bb->cmn_dbg_msg_cnt >= bb->cmn_dbg_msg_period) { /*unit: Sec*/
bb->cmn_dbg_msg_cnt = HALBB_WATCHDOG_PERIOD;
} else {
bb->cmn_dbg_msg_cnt += HALBB_WATCHDOG_PERIOD;
return;
}
#endif
BB_DBG(bb, DBG_CMN, "[%s]%s %s\n", __func__, HLABB_CODE_BASE, HALBB_RELEASE_DATE);
BB_DBG(bb, DBG_CMN, "====[1. System] (%08d sec) (Ability=0x%08llx)\n",
bb->bb_sys_up_time, bb->support_ability);
BB_DBG(bb, DBG_CMN, "[%s mode], TP{T,R,ALL}={%d, %d, %d}, BW:%d, CH_fc:%d\n",
((bb->bb_watchdog_mode == BB_WATCHDOG_NORMAL) ? "Normal" :
((bb->bb_watchdog_mode == BB_WATCHDOG_LOW_IO) ? "LowIO" : "NonIO")),
link->tx_tp, link->rx_tp, link->total_tp, 20 << bw, fc);
BB_DBG(bb, DBG_CMN,
"Phy:%d, linked: %d, Num_sta: %d, rssi_max/min= {%02d.%d, %02d.%d}, Noisy:%d\n",
bb->bb_phy_idx,
link->is_linked, bb->hal_com->assoc_sta_cnt,
ch->rssi_max >> 1, (ch->rssi_max & 1) * 5,
ch->rssi_min >> 1, (ch->rssi_min & 1) * 5,
ch->is_noisy);
BB_DBG(bb, DBG_CMN, "physts_cnt{all, 2_self, err_len, ok_ie, err_ie}={%d,%d,%d,%d,%d}\n",
physts->bb_physts_cnt_i.all_cnt, physts->bb_physts_cnt_i.is_2_self_cnt,
physts->bb_physts_cnt_i.ok_ie_cnt, physts->bb_physts_cnt_i.err_ie_cnt,
physts->bb_physts_cnt_i.err_len_cnt);
for (i = 0; i< PHL_MAX_STA_NUM; i++) {
BB_DBG(bb, DBG_CMN, "[%d] Linked macid=%d\n",
i, bb->sta_exist[i]);
sta_cnt++;
if (sta_cnt >= bb->hal_com->assoc_sta_cnt)
break;
}
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[2. ENV Mntr]\n");
halbb_env_mntr_log(bb, DBG_CMN);
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[3. PMAC]\n");
halbb_basic_dbg_msg_pmac(bb);
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[4. TX General]\n");
halbb_basic_dbg_msg_mac_phy_intf(bb);
if (bb->bb_link_i.is_linked) {
halbb_basic_dbg_msg_tx_info(bb);
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[5. RX General]\n");
halbb_basic_dbg_msg_rx_info(bb);
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[6. AVG RSSI/RxRate]\n");
halbb_basic_dbg_msg_physts_su(bb);
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[7. BB Hist]\n");
halbb_show_phy_hitogram_su(bb);
BB_DBG(bb, DBG_CMN, "\n");
BB_DBG(bb, DBG_CMN, "====[8. [MU] AVG RSSI/RxRate]\n");
halbb_basic_dbg_msg_physts_mu(bb);
}
BB_DBG(bb, DBG_CMN, "============================================\n");
BB_DBG(bb, DBG_CMN, "\n");
}
void halbb_dm_summary(struct bb_info *bb, u8 macid)
{
}
#endif
void halbb_basic_profile_dbg(struct bb_info *bb, u32 *_used, char *output, u32 *_out_len)
{
char *cv = NULL;
char *ic_type = NULL;
char *support = NULL;
u32 used = *_used;
u32 out_len = *_out_len;
u32 date = 0;
u32 release_ver = 0;
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "%s\n",
"% [Basic Info] %");
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
ic_type = "RTL8852A(Acut)";
date = BB_REG_RELEASE_DATE_8852A;
release_ver = BB_REG_RELEASE_VERSION_8852A;
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
ic_type = "RTL8852A(>Bcut)";
date = BB_REG_RELEASE_DATE_8852A_2;
release_ver = BB_REG_RELEASE_VERSION_8852A_2;
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
ic_type = "RTL8852B";
date = BB_REG_RELEASE_DATE_8852B;
release_ver = BB_REG_RELEASE_VERSION_8852B;
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
ic_type = "RTL8852C";
date = BB_REG_RELEASE_DATE_8852C;
release_ver = BB_REG_RELEASE_VERSION_8852C;
break;
#endif
default:
BB_WARNING("[%s]\n", __func__);
break;
}
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"IC", ic_type);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
" %-25s: %s \n", "Normal Mode",
(bb->phl_com->drv_mode == RTW_DRV_MODE_NORMAL)? "Y" : "N");
if (bb->hal_com->cv == CAV)
cv = "CAV";
else if (bb->hal_com->cv == CBV)
cv = "CBV";
else if (bb->hal_com->cv == CCV)
cv = "CCV";
else if (bb->hal_com->cv == CDV)
cv = "CDV";
else if (bb->hal_com->cv == CEV)
cv = "CEV";
else
cv = "NA";
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %d\n",
"RFE", bb->phl_com->dev_cap.rfe_type);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %d\n",
"PKG", bb->phl_com->dev_cap.pkg_type);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"CV", cv);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
" %-25s: %d.%d\n", "FW Ver", bb->u8_dummy,
bb->u8_dummy); /*TBD*/
/*[HALBB Info]*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "%s\n",
"% [HALBB Info] %");
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s (%s)\n",
"Branch", HLABB_CODE_BASE, HALBB_RELEASE_DATE);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %02d (%d)\n",
"BB CR Ver", release_ver, date);
/*Feature Compile List*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "%s\n",
"% [Support List] %");
#ifdef HALBB_DBG_TRACE_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"DBG_TRACE", support);
#ifdef HALBB_TIMER_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"TIMER", support);
#ifdef HALBB_PHYSTS_PARSING_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"PHYSTS", support);
#ifdef HALBB_ENV_MNTR_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"ENV_MNTR", support);
#ifdef HALBB_STATISTICS_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"STATISTICS", support);
#ifdef HALBB_RA_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"RA", support);
#ifdef HALBB_EDCCA_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"EDCCA", support);
#ifdef HALBB_CFO_TRK_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"CFO_TRK", support);
#ifdef HALBB_LA_MODE_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"LA_MODE", support);
#ifdef HALBB_PSD_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"PSD", support);
#ifdef HALBB_PWR_CTRL_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"PWR_CTRL", support);
#ifdef HALBB_RUA_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"RUA", support);
#ifdef HALBB_PMAC_TX_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"PMAC_TX", support);
#ifdef HALBB_CH_INFO_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"CH_INFO", support);
#ifdef HALBB_AUTO_DBG_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"AUTO_DBG", support);
#ifdef HALBB_ANT_DIV_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"ANT_DIV", support);
#ifdef HALBB_DBCC_SUPPORT
support = "Y";
#else
support = ".";
#endif
BB_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s: %s\n",
"DBCC", support);
*_used = used;
*_out_len = out_len;
}
#if HALBB_DBG_DVLP_FLAG /*Dump register - relative*/
void halbb_dump_bb_reg(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff)
{
if (dump_2_buff) {
if (*_out_len < 100) {
BB_WARNING("[%s] out_len=%d", __func__, *_out_len);
return;
}
}
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_dump_bb_reg_8852a(bb, _used, output, _out_len);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_dump_bb_reg_8852a_2(bb, _used, output, _out_len, dump_2_buff);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_dump_bb_reg_8852b(bb, _used, output, _out_len, dump_2_buff);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_dump_bb_reg_8852c(bb, _used, output, _out_len, dump_2_buff);
break;
#endif
default:
break;
}
}
void halbb_dump_reg_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output,
u32 *_out_len)
{
char help[] = "-h";
u32 val[10] = {0};
u32 addr = 0;
if (input[1])
HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[1], help) == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dumpreg 0\n");
} else {
halbb_dump_bb_reg(bb, _used, output, _out_len, true);
}
}
void halbb_dd_dump_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char help[] = "-h";
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[1], help) == 0) {
BB_DBG_CNSL(out_len, *_used, output + *_used, out_len - *_used,
"{dd_dbg}\n");
return;
}
/*[Reg]*/
halbb_dump_bb_reg(bb, &used, output, &out_len, true);
/*[Dbg Port]*/
halbb_dbgport_dump_all(bb, _used, output, _out_len);
/*[Analog Parameters]*/
//halbb_get_anapar_table(bb, &used, output, &out_len);
}
#endif
void halbb_show_rx_rate(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
HALBB_SCAN(input[2], DCMD_HEX, &val[0]);
if (val[0] == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[SU RX Rate]\n");
halbb_rx_rate_distribution_su_cnsl(bb, _used, output, _out_len);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[MU RX Rate]\n");
}
}
void halbb_cmn_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 cr = 0;
bool rpt = true;
enum phl_phy_idx phy_idx;
struct rtw_para_info_t *reg = NULL;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{cr_rec, cr_rec_rf} {en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"wd {0:Normal/1:LowIo/2:NonIO}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"event {phl_evt_id}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"period {val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"init {cr, gain} {phy_idx}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"init dbg_mode {en} {rfe} {cv}\n");
} else if (_os_strcmp(input[1], "event") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
halbb_wifi_event_notify(bb, (enum phl_msg_evt_id)val[0], bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"phl_evt_id=%d\n", val[0]);
} else if (_os_strcmp(input[1], "period") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
bb->bb_watchdog_period = (u8)(val[0] & 0xfe);
if (bb->bb_watchdog_period < 2)
bb->bb_watchdog_period = 2;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"wd_period=%d\n", bb->bb_watchdog_period);
} else if (_os_strcmp(input[1], "cr_rec") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
bb->bb_dbg_i.cr_recorder_en = (bool)val[0];
} else if (_os_strcmp(input[1], "cr_rec_rf") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
bb->bb_dbg_i.cr_recorder_rf_en = (bool)val[0];
} else if (_os_strcmp(input[1], "wd") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
halbb_watchdog(bb, (enum bb_watchdog_mode_t)val[0], bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Watchdog trigger, mode=%d\n", val[0]);
} else if (_os_strcmp(input[1], "init") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]);
if (_os_strcmp(input[2], "cr") == 0) {
phy_idx = (enum phl_phy_idx)val[0];
reg = &bb->phl_com->phy_sw_cap[phy_idx].bb_phy_reg_info;
rpt = halbb_init_cr_default(bb, false, 0, &val[0], phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"CR init Success=%d\n", rpt);
} else if (_os_strcmp(input[2], "gain") == 0) {
phy_idx = (enum phl_phy_idx)val[0];
reg = &bb->phl_com->phy_sw_cap[phy_idx].bb_phy_reg_gain_info;
rpt = halbb_init_gain_table(bb, false, 0, &val[0], phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Gain init Success=%d\n", rpt);
} else if (_os_strcmp(input[2], "dbg_mode") == 0) {
bb->bb_dbg_i.cr_dbg_mode_en = (bool)val[0];
bb->bb_dbg_i.rfe_type_curr_dbg = val[1];
bb->bb_dbg_i.cut_curr_dbg = val[2];
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Err\n");
return;
}
} else if (_os_strcmp(input[1], "1") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
bb->hal_com->assoc_sta_cnt = (u8)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"assoc_sta_cnt=%d\n", bb->hal_com->assoc_sta_cnt);
} else if (_os_strcmp(input[1], "cr_demo") == 0) {
cr = halbb_get_reg(bb, LA_CLK_EN, LA_CLK_EN_M);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Old] cr = %d\n", cr);
HALBB_SET_CR(bb, LA_CLK_EN, ~cr);
cr = HALBB_GET_CR(bb, LA_CLK_EN);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[New] ~cr = %d\n", cr);
HALBB_SET_CR(bb, LA_CLK_EN, ~cr);
cr = HALBB_GET_CR(bb, LA_CLK_EN);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[New] cr = %d\n", cr);
}
}
void halbb_dbg_setting_init(struct bb_info *bb)
{
halbb_cmd_parser_init(bb);
bb->fw_dbg_component = 0;
bb->cmn_dbg_msg_cnt = HALBB_WATCHDOG_PERIOD;
bb->cmn_dbg_msg_period = HALBB_WATCHDOG_PERIOD;
halbb_bb_dbg_port_clock_en(bb, true);
bb->bb_dbg_i.cr_recorder_en = false;
bb->bb_dbg_i.cr_dbg_mode_en = false;
}
void halbb_cr_cfg_dbg_init(struct bb_info *bb)
{
struct bb_dbg_cr_info *cr = &bb->bb_dbg_i.bb_dbg_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_52AA_SERIES
case BB_52AA:
cr->dbgport_ip = 0x09F4;
cr->dbgport_ip_m = 0xff;
cr->dbgport_idx = 0x09F0;
cr->dbgport_idx_m = MASKLWORD;
cr->dbgport_val = 0x40B0;
cr->dbgport_val_m = MASKDWORD;
cr->clk_en = 0x09F4;
cr->clk_en_m = BIT(24);
cr->dbgport_en = 0x09F8;
cr->dbgport_en_m = BIT(31);
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->dbgport_ip = DBG_PORT_IP_SEL_A;
cr->dbgport_ip_m = DBG_PORT_IP_SEL_A_M;
cr->dbgport_idx = DBG_PORT_SEL_A;
cr->dbgport_idx_m = DBG_PORT_SEL_A_M;
cr->dbgport_val = DBG32_D_A;
cr->dbgport_val_m = DBG32_D_A_M;
cr->clk_en = DBG_PORT_REF_CLK_EN_A;
cr->clk_en_m = DBG_PORT_REF_CLK_EN_A_M;
cr->dbgport_en = DBG_PORT_EN_A;
cr->dbgport_en_m = DBG_PORT_EN_A_M;
cr->bb_monitor_sel1 = MONITOR_SEL1_A;
cr->bb_monitor_sel1_m = MONITOR_SEL1_A_M;
cr->bb_monitor1 = 0x1b14;
cr->bb_monitor1_m = MASKDWORD;
/*mac_phy_intf*/
cr->mac_phy_ppdu_type = 0x1800;
cr->mac_phy_txpath_en = 0x1800;
cr->mac_phy_txcmd = 0x1800;
cr->mac_phy_txsc = 0x1804;
cr->mac_phy_bw = 0x1804;
cr->mac_phy_tx_pw = 0x1804;
cr->mac_phy_n_usr = 0x1808;
cr->mac_phy_stbc = 0x1810;
cr->mac_phy_gi = 0x1810;
cr->mac_phy_ltf = 0x1810;
cr->mac_phy_ndp_en = 0x1814;
cr->mac_phy_n_sts = 0x1818;
cr->mac_phy_fec = 0x1818;
cr->mac_phy_mcs_3_0 = 0x1818;
cr->mac_phy_mcs_5_4 = 0x181c;
cr->mac_phy_lsig = 0x1840;
cr->mac_phy_siga_0 = 0x1848;
cr->mac_phy_siga_1 = 0x184c;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->dbgport_ip = DBG_PORT_IP_SEL_C;
cr->dbgport_ip_m = DBG_PORT_IP_SEL_C_M;
cr->dbgport_idx = DBG_PORT_SEL_C;
cr->dbgport_idx_m = DBG_PORT_SEL_C_M;
cr->dbgport_val = DBG32_D_C;
cr->dbgport_val_m = DBG32_D_C_M;
cr->clk_en = DBG_PORT_REF_CLK_EN_C;
cr->clk_en_m = DBG_PORT_REF_CLK_EN_C_M;
cr->dbgport_en = DBG_PORT_EN_C;
cr->dbgport_en_m = DBG_PORT_EN_C_M;
cr->bb_monitor_sel1 = MONITOR_SEL1_C;
cr->bb_monitor_sel1_m = MONITOR_SEL1_C_M;
cr->bb_monitor1 = 0x1b14;
cr->bb_monitor1_m = MASKDWORD;
/*mac_phy_intf*/
cr->mac_phy_ppdu_type = 0x1800;
cr->mac_phy_txpath_en = 0x1800;
cr->mac_phy_txcmd = 0x1800;
cr->mac_phy_txsc = 0x1804;
cr->mac_phy_bw = 0x1804;
cr->mac_phy_tx_pw = 0x1804;
cr->mac_phy_n_usr = 0x1808;
cr->mac_phy_stbc = 0x1810;
cr->mac_phy_gi = 0x1810;
cr->mac_phy_ltf = 0x1810;
cr->mac_phy_ndp_en = 0x1814;
cr->mac_phy_n_sts = 0x1818;
cr->mac_phy_fec = 0x1818;
cr->mac_phy_mcs_3_0 = 0x1818;
cr->mac_phy_mcs_5_4 = 0x181c;
cr->mac_phy_lsig = 0x1840;
cr->mac_phy_siga_0 = 0x1848;
cr->mac_phy_siga_1 = 0x184c;
break;
#endif
default:
break;
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbg.c
|
C
|
agpl-3.0
| 47,301
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_H__
#define __HALBB_DBG_H__
#include "../../hal_headers_le.h"
/*@--------------------------[Define] ---------------------------------------*/
#define HALBB_WATCHDOG_PERIOD 2 /*second*/
#define PHY_HIST_SIZE 12
#define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1)
#define LA_CLK_EN 0x014 /*Just for dbg, will be removed*/
#define LA_CLK_EN_M 0x1 /*Just for dbg, will be removed*/
#ifdef HALBB_DBG_TRACE_SUPPORT
#ifdef HALBB_DBCC_SUPPORT
#define BB_DBG(bb, comp, fmt, ...) \
do {\
if(bb->dbg_component & comp) {\
_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
} \
} while (0)
#else
#define BB_DBG(bb, comp, fmt, ...) \
do {\
if(bb->dbg_component & comp) {\
_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
} \
} while (0)
#endif
#define BB_TRACE(fmt, ...) \
do {\
_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
} while (0)
#define BB_WARNING(fmt, ...) \
do {\
_os_dbgdump("[WARNING][BB]" fmt, ##__VA_ARGS__);\
} while (0)
#define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
u32 len_tmp = 0; \
if (*used_len_tmp < max_buff_len) { \
len_tmp = _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__); \
if (in_cnsl) { \
*used_len_tmp += len_tmp; \
} else { \
BB_TRACE("%s\n", buff_addr); \
} \
}\
} while (0)
#else
#define BB_DBG
#define BB_TRACE
#define BB_WARNING
#define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
#endif
#define BB_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do {\
_os_dbgdump("[CNSL]" fmt, ##__VA_ARGS__);\
} while (0)
#define BB_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/
#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/
#define DBGPORT_PRI_1 1 /*Watch dog function*/
#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_dbg_port_ip_t
{
DBGPORT_IP_TD = 1,
DBGPORT_IP_RX_INNER = 2,
DBGPORT_IP_TX_INNER = 3,
DBGPORT_IP_OUTER = 4,
DBGPORT_IP_INTF = 5,
DBGPORT_IP_CCK = 6,
DBGPORT_IP_BF = 7,
DBGPORT_IP_RX_OUTER = 8,
DBGPORT_IP_RFC0 = 0X1B,
DBGPORT_IP_RFC1 = 0X1C,
DBGPORT_IP_RFC2 = 0X1D,
DBGPORT_IP_RFC3 = 0X1E,
DBGPORT_IP_TST = 0X1F,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dbg_cr_info {
u32 dbgport_ip;
u32 dbgport_ip_m;
u32 dbgport_idx;
u32 dbgport_idx_m;
u32 dbgport_val;
u32 dbgport_val_m;
u32 clk_en;
u32 clk_en_m;
u32 dbgport_en;
u32 dbgport_en_m;
u32 bb_monitor_sel1;
u32 bb_monitor_sel1_m;
u32 bb_monitor1;
u32 bb_monitor1_m;
/*mac_phy_intf*/
u32 mac_phy_ppdu_type;
u32 mac_phy_txpath_en;
u32 mac_phy_txcmd;
u32 mac_phy_txsc;
u32 mac_phy_bw;
u32 mac_phy_tx_pw;
u32 mac_phy_ndp_en;
u32 mac_phy_n_usr;
u32 mac_phy_gi;
u32 mac_phy_ltf;
u32 mac_phy_n_sts;
u32 mac_phy_fec;
u32 mac_phy_mcs_3_0;
u32 mac_phy_mcs_5_4;
u32 mac_phy_stbc;
u32 mac_phy_lsig;
u32 mac_phy_siga_0;
u32 mac_phy_siga_1;
};
struct bb_dbg_info {
bool cr_recorder_en;
bool cr_recorder_rf_en; /*HALRF write BB CR*/
/*CR init debug control*/
bool cr_dbg_mode_en;
u32 cut_curr_dbg;
u32 rfe_type_curr_dbg;
#ifdef HALBB_TDMA_CR_SUPPORT
struct halbb_timer_info tdma_cr_timer_i;
bool tdma_cr_en;
u8 tdma_cr_state;
u32 tdma_cr_idx;
u32 tdma_cr_mask;
u32 tdma_cr_val_0;
u32 tdma_cr_val_1;
u32 tdma_cr_period_0;
u32 tdma_cr_period_1;
#endif
struct bb_dbg_cr_info bb_dbg_cr_i;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
#ifdef HALBB_TDMA_CR_SUPPORT
void halbb_tdma_cr_sel_io_en(struct bb_info *bb);
void halbb_tdma_cr_timer_init(struct bb_info *bb);
void halbb_tdma_cr_sel_main(struct bb_info *bb);
void halbb_tdma_cr_sel_deinit(struct bb_info *bb);
void halbb_tdma_cr_sel_init(struct bb_info *bb);
#endif
void halbb_dbg_comp_init(struct bb_info *bb);
void halbb_bb_dbg_port_clock_en(struct bb_info *bb, u8 enable);
u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb);
void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port);
void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip);
void halbb_release_bb_dbg_port(struct bb_info *bb);
bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority);
u32 halbb_get_bb_dbg_port_val(struct bb_info *bb);
void halbb_basic_dbg_message(struct bb_info *bb);
void halbb_basic_profile_dbg(struct bb_info *bb, u32 *_used, char *output, u32 *_out_len);
void halbb_dump_reg_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_dd_dump_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_dump_bb_reg(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff);
void halbb_show_rx_rate(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cmn_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_dbg_setting_init(struct bb_info *bb);
void halbb_cr_cfg_dbg_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbg.h
|
C
|
agpl-3.0
| 6,708
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halbb_precomp.h"
#include "halbb_dbg_cmd_table.h"
void halbb_bbcr_rw_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 addr = 0 , mask = MASKDWORD, val_32 = 0;
u32 write_val = 0;
u8 mask_m = 31, mask_l = 0;
HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"r dw {reg_DW}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"r {bit_M} {bit_L} {reg_DW}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"w dw {reg_DW} {val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"w {bit_M} {bit_L} {reg_DW} {val}\n");
return;
}
if (_os_strcmp(input[2], "dw") == 0) {
HALBB_SCAN(input[3], DCMD_HEX, &val[0]);
HALBB_SCAN(input[4], DCMD_HEX, &val[1]);
addr = val[0];
write_val = val[1];
} else {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_HEX, &val[2]);
HALBB_SCAN(input[5], DCMD_HEX, &val[3]);
mask_m = (u8)val[0];
mask_l = (u8)val[1];
addr = val[2];
write_val = val[3];
mask = (u32)halbb_gen_mask(mask_m, mask_l);
if (mask == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Error mask = 0x%x\n", mask);
}
}
if (addr % 4) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Error DW offset = 0x%x\n", addr);
return;
}
if (_os_strcmp(input[1], "r") == 0) {
val_32 = halbb_get_reg(bb, addr, mask);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[R] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, val_32);
} else if (_os_strcmp(input[1], "w") == 0) {
halbb_set_reg(bb, addr, mask, write_val);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[W] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, write_val);
halbb_delay_ms(bb, 1);
val_32 = halbb_get_reg(bb, addr, mask);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[READ_BACK] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, val_32);
}
#if 0
else if (_os_strcmp(input[1], "rf_r") == 0) {
val_32 = halbb_rf_get_bb_reg(bb, addr, mask);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[RFR] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, val_32);
} else if (_os_strcmp(input[1], "rf_w") == 0) {
halbb_rf_set_bb_reg(bb, addr, mask, write_val);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[RFW] Reg0x%x[%02d:%02d] = 0x%x\n", addr, mask_m, mask_l, write_val);
halbb_delay_ms(bb, 1);
val_32 = halbb_get_reg(bb, addr, mask);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[READ_BACK] Reg0x%x[%02d:%02d] = 0x%x\n", mask_m, mask_l, addr, val_32);
}
#endif
}
void halbb_bb_td_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_dbg_info *dbg = &bb->bb_dbg_i;
u32 val[10] = {0};
u32 tmp = 0;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"pop_en {en} {phl_phy_idx}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set_pd_low {val} {bw} {phl_phy_idx}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"per {phl_phy_idx}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"pfd set {type}\n");
#ifdef HALBB_TDMA_CR_SUPPORT
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tdma_cr en\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tdma_cr cr {cr_idx} {cr_mask} {val_0} {val_1}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tdma_cr period {p0_ms} {p1_ms}\n");
#endif
return;
}
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
if (_os_strcmp(input[1], "pop_en") == 0) {
halbb_pop_en(bb, (bool)val[0], bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "set_pd_low") == 0) {
halbb_set_pd_lower_bound(bb, (u8)val[0], (enum channel_width)val[1], bb->bb_phy_idx);
#ifdef HALBB_TDMA_CR_SUPPORT
} else if (_os_strcmp(input[1], "tdma_cr") == 0) {
if (_os_strcmp(input[2], "en") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
if (dbg->tdma_cr_idx == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Err tdma_cr_idx = 0\n");
return;
}
dbg->tdma_cr_en = (bool)val[0];
halbb_tdma_cr_sel_main(bb);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tdma_cr_en=%d\n", dbg->tdma_cr_en);
} else if (_os_strcmp(input[2], "period") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
dbg->tdma_cr_period_0 = val[0];
dbg->tdma_cr_period_1 = val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"period 0/1= {%d, %d} ms\n",
dbg->tdma_cr_period_0,
dbg->tdma_cr_period_1);
} else if (_os_strcmp(input[2], "cr") == 0) {
HALBB_SCAN(input[3], DCMD_HEX, &val[0]);
HALBB_SCAN(input[4], DCMD_HEX, &val[1]);
HALBB_SCAN(input[5], DCMD_HEX, &val[2]);
HALBB_SCAN(input[6], DCMD_HEX, &val[3]);
dbg->tdma_cr_idx = val[0];
dbg->tdma_cr_mask = val[1];
dbg->tdma_cr_val_0 = val[2];
dbg->tdma_cr_val_1 = val[3];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Reg 0x%x[0x%x] = {0x%x, 0x%x}\n",
dbg->tdma_cr_idx, dbg->tdma_cr_mask,
dbg->tdma_cr_val_0, dbg->tdma_cr_val_1);
}
#endif
#ifdef BB_8852A_2_SUPPORT
} else if (_os_strcmp(input[1], "per") == 0) {
halbb_get_per_8852a_2(bb, bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "pfd") == 0) {
if (bb->ic_type != BB_RTL8852A)
return;
if (_os_strcmp(input[2], "set") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
halbb_manual_pkt_fmt_sel_8852a_2(bb, (enum bb_pfd_fmt_type)val[0]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"pfd_fmt_type=%d\n", val[0]);
}
#endif
}
}
void halbb_bb_fd_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{fd dbg}\n");
return;
}
}
/*void halbb_fw_trace_en_h2c(struct bb_info *bb, bool enable,
u32 fw_dbg_comp, u32 monitor_mode, u32 macid)
{
u8 h2c_parameter[7] = {0};
u8 cmd_length;
h2c_parameter[0] = enable;
h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0);
h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8);
h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16);
h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24);
h2c_parameter[5] = (u8)monitor_mode;
h2c_parameter[6] = (u8)macid;
cmd_length = 7;
BB_DBG(bb, DBG_FW_INFO,
"[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n",
enable, monitor_mode, macid);
//odm_fill_h2c_cmd(bb, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);
}*/
void halbb_cmn_msg_setting(struct bb_info *bb, u32 *val, u32 *_used,
char *output, u32 *_out_len)
{
u32 used = *_used;
u32 out_len = *_out_len;
if (val[1] == 1) {
bb->cmn_dbg_msg_period = (u8)val[2];
if (bb->cmn_dbg_msg_period < HALBB_WATCHDOG_PERIOD)
bb->cmn_dbg_msg_period = HALBB_WATCHDOG_PERIOD;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"cmn_dbg_msg_period=%d\n", bb->cmn_dbg_msg_period);
}
*_used = used;
*_out_len = out_len;
}
void halbb_trace_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u64 pre_debug_components, one = 1;
u64 comp = 0;
u32 used = *_used;
u32 out_len = *_out_len;
u32 val[10] = {0};
u8 i = 0;
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
comp = bb->dbg_component;
pre_debug_components = bb->dbg_component;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n================================\n");
if (val[0] == 100) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[DBG MSG] Component Selection\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"================================\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"00. (( %s ))RA\n",
((comp & DBG_RA) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"01. (( %s ))FA_CNT\n",
((comp & DBG_FA_CNT) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"02. (( %s ))RSSI_MNTR\n",
((comp & DBG_HALBB_FUN_RSVD_2) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"03. (( %s ))DFS\n",
((comp & DBG_DFS) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"04. (( %s ))EDCCA\n",
((comp & DBG_EDCCA) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"05. (( %s ))ENV_MNTR\n",
((comp & DBG_ENV_MNTR) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"06. (( %s ))CFO_TRK\n",
((comp & DBG_CFO_TRK) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"07. (( %s ))PWR_CTRL\n",
((comp & DBG_PWR_CTRL) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"08. (( %s ))RUA_TBL\n",
((comp & DBG_RUA_TBL) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"09. (( %s ))F_AUTO_DBG\n",
((comp & DBG_AUTO_DBG) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"10. (( %s ))ANT_DIV\n",
((comp & DBG_ANT_DIV) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"11. (( %s ))DIG\n",
((comp & DBG_DIG) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"12. (( %s ))TBD\n",
((comp & BIT(12)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"13. (( %s ))TBD\n",
((comp & BIT(13)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"14. (( %s ))TBD\n",
((comp & BIT(14)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"15. (( %s ))TBD\n",
((comp & BIT(15)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"16. (( %s ))TBD\n",
((comp & BIT(16)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"17. (( %s ))TBD\n",
((comp & BIT(17)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"18. (( %s ))TBD\n",
((comp & BIT(18)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"19. (( %s ))TBD\n",
((comp & BIT(19)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"20. (( %s ))PHY_STATUS\n",
((comp & DBG_PHY_STS) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"21. (( %s ))TBD\n",
((comp & BIT(21)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"22. (( %s ))FW_INFO\n",
((comp & DBG_FW_INFO) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"23. (( %s ))COMMON_FLOW\n",
((comp & DBG_COMMON_FLOW) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"24. (( %s ))IC_API\n",
((comp & DBG_IC_API) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"25. (( %s ))DBG_API\n",
((comp & DBG_DBG_API) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"26. (( %s ))DBCC\n",
((comp & DBG_DBCC) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"27. (( %s ))DM_SUMMARY\n",
((comp & DBG_DM_SUMMARY) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"28. (( %s ))PHY_CONFIG\n",
((comp & DBG_PHY_CONFIG) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"29. (( %s ))INIT\n",
((comp & DBG_INIT) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"30. (( %s ))COMMON\n",
((comp & DBG_CMN) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"31. (( %s ))TBD\n",
((comp & BIT(31)) ? ("V") : (".")));
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"================================\n");
} else if (val[0] == 101) {
bb->dbg_component = 0;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Disable all debug components\n");
} else {
if (val[1] == 1) /*@enable*/
bb->dbg_component |= (one << val[0]);
else if (val[1] == 2) /*@disable*/
bb->dbg_component &= ~(one << val[0]);
else
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[Warning] 1:on, 2:off\n");
if (BIT(val[0]) == DBG_CMN) {
halbb_cmn_msg_setting(bb, val, &used, output, &out_len);
}
}
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"pre-DbgComponents = 0x%llx\n", pre_debug_components);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Curr-DbgComponents = 0x%llx\n", bb->dbg_component);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"================================\n");
*_used = used;
*_out_len = out_len;
}
u32 halbb_get_multiple(u8 pow, u8 base)
{
u8 i;
u32 return_value = 1;
for (i = 0; i < pow; i++)
return_value *= base; /*base ^ pow*/
return return_value;
}
u32 halbb_str_2_dec(u8 val)
{
if (val >= 0x30 && val <= 0x39) /*0~9*/
return (val - 0x30);
else if (val >= 0x41 && val <= 0x46) /*A~F*/
return (val - 0x41 + 10);
else if (val >= 0x61 && val <= 0x66) /*a~f*/
return (val - 0x61 + 10);
else
return 1;
}
void halbb_scanf(char *in, enum bb_scanf_type type, u32 *out)
{
char buff[DCMD_SCAN_LIMIT];
u32 multiple = 1;
u8 text_num = 0;
u8 base = 10;
u8 i = 0, j = 0;
*out = 0;
for (i = 0; i < DCMD_SCAN_LIMIT; i++) {
/*BB_TRACE("pInput[%d] = %x\n", i, in[i]);*/
if (in[i] != 0x0) { /* 0x0 = NULL. */
buff[i] = in[i];
continue;
}
if (type == DCMD2_CHAR) {
*out = *in;
break;
}
base = (type == DCMD2_DECIMAL) ? 10 : 16;
text_num = i;
for (j = 0; j < text_num; j++) {
/*BB_TRACE("text_num=%d, sbuff[j]=%d, j=%d, value=%d\n",text_num, buff[j], j, base);*/
multiple = halbb_get_multiple(text_num - 1 - j, base);
*out += halbb_str_2_dec(buff[j]) * multiple;
/*BB_TRACE("[%d]*pOutput = %d\n", j, *out);*/
}
break;
}
}
void halbb_cmd_parser(struct bb_info *bb, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct bb_echo_cmd_info *echo_cmd = &bb->bb_cmn_hooker->bb_echo_cmd_i;
u32 used = 0;
u8 id = 0;
u32 var1[10] = {0};
u32 i;
u32 halbb_ary_size = echo_cmd->cmd_size;
u32 directory = 0;
char char_temp = ' ';
//u32 val_tmp;
if (halbb_ary_size == 0)
return;
/* Parsing Cmd ID */
if (input_num) {
for (i = 0; i < halbb_ary_size; i++) {
if (_os_strcmp(halbb_cmd_i[i].name, input[0]) == 0) {
id = halbb_cmd_i[i].id;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[%s]===>\n", halbb_cmd_i[i].name);
break;
}
}
if (i == halbb_ary_size) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"HALBB command not found!\n");
return;
}
}
#ifdef HALBB_DBCC_SUPPORT
bb = halbb_get_curr_bb_pointer(bb, bb->bb_cmn_hooker->bb_echo_cmd_i.echo_phy_idx);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[BB echo cmd] Phy-%d\n", bb->bb_phy_idx);
#endif
switch (id) {
case HALBB_HELP: {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"BB cmd ==>\n");
for (i = 0; i < halbb_ary_size - 2; i++)
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
" %-5d: %s\n", i, halbb_cmd_i[i + 2].name);
} break;
case HALBB_DEMO:
/*echo bb demo 12 3b abcde -10*/
HALBB_SCAN(input[1], DCMD_DECIMAL, &directory);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Decimal value = %d\n", directory);
HALBB_SCAN(input[2], DCMD_HEX, &directory);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Hex value = 0x%x\n", directory);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"String = %s\n", input[3]);
HALBB_SCAN(input[4], "%d", &directory);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"value_u32 = %d\n", (u32)directory);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"value_s32 = %d\n", (s32)directory);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"value_hex = 0x%x\n", directory);
break;
case HALBB_CMN_DBG:
halbb_cmn_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_REG_RW:
halbb_bbcr_rw_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_STASISTICS:
#ifdef HALBB_STATISTICS_SUPPORT
halbb_crc32_cnt_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_DBG_PORT:
halbb_dbgport_dbg(bb, input, &used, output, &out_len);
break;
#ifdef HALBB_RA_SUPPORT
case HALBB_RA:
halbb_ra_dbg(bb, input, &used, output, &out_len);
break;
#endif
case HALBB_TRACE:
halbb_trace_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_MP_DBG:
halbb_mp_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_SUPPORT_ABILITY:
halbb_supportability_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_IC_API:
halbb_ic_api_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_PROFILE:
halbb_basic_profile_dbg(bb, &used, output, &out_len);
break;
case HALBB_TX_PW:
halbb_pwr_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_LA_MODE:
#ifdef HALBB_LA_MODE_SUPPORT
halbb_la_cmd_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_PSD:
#ifdef HALBB_PSD_SUPPORT
halbb_psd_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_DUMP_REG:
halbb_dump_reg_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_CFO_TRK:
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfo_trk_dbg(bb, input, &used, output, &out_len);
#endif
break;
#if 0
case HALBB_AUTO_DBG:
#ifdef HALBB_AUTO_DEGBUG
halbb_auto_dbg_console(bb, input, &used, output, &out_len);
#endif
break;
#endif
case HALBB_DD_DBG:
halbb_dd_dump_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_SHOW_RXRATE:
halbb_show_rx_rate(bb, input, &used, output, &out_len);
break;
#if 0
case HALBB_NBI_EN:
halbb_nbi_debug(bb, input, &used, output, &out_len);
break;
case HALBB_CSI_MASK_EN:
halbb_csi_debug(bb, input, &used, output, &out_len);
break;
#endif
case HALBB_DFS_DBG:
#ifdef HALBB_DFS_SUPPORT
halbb_dfs_debug(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_DIG:
#ifdef HALBB_DIG_SUPPORT
halbb_dig_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_NHM:
#ifdef NHM_SUPPORT
halbb_nhm_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_CLM:
#ifdef CLM_SUPPORT
halbb_clm_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_IFS_CLM:
#ifdef IFS_CLM_SUPPORT
halbb_ifs_clm_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_FAHM:
#ifdef FAHM_SUPPORT
halbb_fahm_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_EDCCA_CLM:
#ifdef EDCCA_CLM_SUPPORT
halbb_edcca_clm_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_EDCCA:
#ifdef HALBB_EDCCA_SUPPORT
halbb_edcca_dbg(bb, input, &used, output, &out_len);
#endif
break;
case HALBB_ENV_MNTR:
#ifdef HALBB_ENV_MNTR_SUPPORT
halbb_env_mntr_dbg(bb, input, &used, output, &out_len);
#endif
break;
#if 0
case HALBB_BB_INFO:
halbb_bb_hw_dbg_info(bb, input, &used, output, &out_len);
break;
case HALBB_H2C:
halbb_h2C_debug(bb, input, &used, output, &out_len);
break;
case HALBB_ADAPTIVITY_DBG:
#ifdef HALBB_SUPPORT_ADAPTIVITY
halbb_adaptivity_debug(bb, input, &used, output, &out_len);
#endif
break;
#endif
case HALBB_STA_INFO:
halbb_sta_info_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_PAUSE_FUNC:
halbb_pause_func_dbg(bb, input, &used, output, &out_len);
break;
#if 0
case HALBB_PER_TONE_EVM:
halbb_per_tone_evm(bb, input, &used, output, &out_len);
break;
#ifdef CONFIG_DYNAMIC_TX_TWR
case HALBB_DYN_TXPWR:
halbb_dtp_debug(bb, input, &used, output, &out_len);
break;
#endif
#endif
case HALBB_PHY_STATUS:
halbb_physts_dbg(bb, input, &used, output, &out_len);
break;
#if 0
#ifdef HALBB_DCC_ENHANCE
case HALBB_DCC:
halbb_dig_cckpd_coex_dbg(bb, input, &used, output, &out_len);
break;
#endif
#endif
#ifdef HALBB_PMAC_TX_SETTING_SUPPORT
case HALBB_PMAC_TX:
halbb_pmac_tx_dbg(bb, input, &used, output, &out_len);
break;
#endif
case HALBB_FW_DBG:
halbb_fw_dbg(bb, input, &used, output, &out_len);
break;
#ifdef HALBB_CH_INFO_SUPPORT
case HALBB_CH_INFO:
halbb_ch_info_dbg(bb, input, &used, output, &out_len);
break;
#endif
#ifdef HALBB_RUA_SUPPORT
case HALBB_RUA_TBL:
halbb_rua_tbl_dbg(bb, input, &used, output, &out_len);
break;
#endif
case HALBB_TD_CFG:
halbb_bb_td_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_FD_CFG:
halbb_bb_fd_dbg(bb, input, &used, output, &out_len);
break;
#ifdef HALBB_DBCC_SUPPORT
case HALBB_DBCC:
halbb_dbcc_dbg(bb, input, &used, output, &out_len);
break;
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
case HALBB_ANT_DIV:
halbb_antdiv_dbg(bb, input, &used, output, &out_len);
break;
#endif
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
case HALBB_DCR_DBG:
halbb_dyn_csi_rsp_dbg(bb, input, &used, output, &out_len);
break;
#endif
case HALBB_RX_GAIN_TABLE:
halbb_rx_gain_table_dbg(bb, input, &used, output, &out_len);
break;
case HALBB_HW_SETTING:
halbb_ic_hw_setting_dbg(bb, input, &used, output, &out_len);
break;
default:
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Do not support this command\n");
break;
}
//BB_DBG_CNSL(out_len, used, output + used, out_len - used,
// "[OUT] bb_phy_idx=%d\n", bb->bb_phy_idx);
}
void halbb_cmd_parser_init(struct bb_info *bb)
{
struct bb_echo_cmd_info *echo_cmd = &bb->bb_cmn_hooker->bb_echo_cmd_i;
echo_cmd->cmd_size = sizeof(halbb_cmd_i) / sizeof(struct halbb_cmd_info);
echo_cmd->echo_phy_idx = HW_PHY_0;
}
s32 halbb_cmd(struct bb_info *bb, char *input, char *output, u32 out_len)
{
char *token;
u32 argc = 0;
char argv[MAX_ARGC][MAX_ARGV];
do {
token = _os_strsep(&input, ", ");
if (token) {
if (_os_strlen(token) <= MAX_ARGV)
_os_strcpy(argv[argc], token);
argc++;
} else {
break;
}
} while (argc < MAX_ARGC);
halbb_cmd_parser(bb, argv, argc, output, out_len);
return 0;
}
void halbb_fwdbg_trace(struct bb_info *bb, u32 dbg_comp, u8 fw_trace_en)
{
struct bb_fw_dbg_cmn_info *bb_fwdbg = &bb->bb_fwdbg_i;
u32 *bb_h2c = (u32 *) bb_fwdbg;
u8 cmdlen = sizeof(struct bb_fw_dbg_cmn_info);
bool ret_val = false;
u8 ret_v0, ret_v1, ret_v2;
/* Set fwdbg api, mac api need driver package*/
ret_v0 = rtw_hal_fw_log_cfg(bb->hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_LEVEL, FL_LV_LOUD);
ret_v1 = rtw_hal_fw_log_cfg(bb->hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_OUTPUT, FL_OP_C2H);
ret_v2 = rtw_hal_fw_log_cfg(bb->hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_COMP, FL_COMP_BB);
/* Set fwbb debug component */
bb_fwdbg->fw_dbg_comp[0] = (u8) (dbg_comp&0x000000ff);
bb_fwdbg->fw_dbg_comp[1] = (u8) (dbg_comp&0x0000ff00);
bb_fwdbg->fw_dbg_comp[2] = (u8) (dbg_comp&0x00ff0000);
bb_fwdbg->fw_dbg_comp[3] = (u8) (dbg_comp&0xff000000);
bb_fwdbg->fw_dbg_trace = fw_trace_en;
BB_DBG(bb, DBG_FW_INFO, "FW TRACE: %x %x\n", bb_h2c[0], bb_h2c[1]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FWTRACE, HALBB_H2C_DM, bb_h2c);
}
void halbb_fw_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char help[] = "-h";
u8 i;
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if (_os_strcmp(input[1], help) == 0) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{fw_dbg (dbg_trace=> 1:enable, 2:disable) (dbg_comp)}\n");
goto out;
}
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
if (val[0] == 1) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[fw_dbg] Enable : dbg_comp = %x\n", val[1]);
halbb_fwdbg_trace(bb, val[1], 1);
} else if (val[0] == 2) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[fw_dbg] Disable : dbg_comp clear\n");
halbb_fwdbg_trace(bb, 0, 0);
} else if (val[0] == 3) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[fw_dbg] Trigger h2c ==> c2h debug\n");
halbb_test_h2c_c2h_flow(bb);
} else if (val[0] == 4) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[fw_dbg] Set h2c get tx statistic\n");
rtw_halbb_query_txsts(bb, (u16)val[1], (u16)val[2]);
}
out:
*_used = used;
*_out_len = out_len;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbg_cmd.c
|
C
|
agpl-3.0
| 26,076
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_DBG_CMD_H_
#define _HALBB_DBG_CMD_H_
/*@--------------------------[Define] ---------------------------------------*/
#define MAX_ARGC 20
#define MAX_ARGV 16
#if 1
#define HALBB_SCAN _os_sscanf
#define DCMD_DECIMAL "%d"
#define DCMD_HEX "%x"
#define DCMD_HEX64 "%llx"
#define DCMD_CHAR "%s"
#else
#define HALBB_SCAN halbb_scanf
enum bb_scanf_type
{
DCMD_DECIMAL = 1,
DCMD_HEX = 2,
DCMD_CHAR = 3,
};
#endif
#define DCMD_SCAN_LIMIT 10
/*@--------------------------[Enum]------------------------------------------*/
enum bb_scanf_type
{
DCMD2_DECIMAL = 1,
DCMD2_HEX = 2,
DCMD2_CHAR = 3,
};
enum FWBB_DBG_COMP_SET {
FWBBDBG_H2C = BIT0,
FWBBDBG_RA = BIT8,
FWBBDBG_RUA = BIT16,
FWBBDBG_ULPWR_CTRL = BIT24,
FWBBDBG_ULRA = BIT25,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_echo_cmd_info {
u8 cmd_size;
enum phl_phy_idx echo_phy_idx;
};
struct bb_fw_dbg_cmn_info {
u8 fw_dbg_comp[4];
u8 fw_dbg_trace;
u8 fw_cmn_info;
u8 fw_rty_rpt_ctrl;
u8 rsvd0;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_dbgport_dump_all(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len);
void halbb_dbgport_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_scanf(char *in, enum bb_scanf_type type, u32 *out);
void halbb_cmd_parser_init(struct bb_info *bb);
void halbb_fw_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbg_cmd.h
|
C
|
agpl-3.0
| 2,212
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_CMD_EX_H__
#define __HALBB_DBG_CMD_EX_H__
#define MAX_ARGV 16
struct bb_info;
s32 halbb_cmd(struct bb_info *bb, char *input, char *output, u32 out_len);
void halbb_cmd_parser(struct bb_info *bb, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbg_cmd_ex.h
|
C
|
agpl-3.0
| 1,270
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_DBG_CMD_TABLE_H_
#define _HALBB_DBG_CMD_TABLE_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum HALBB_CMD_ID {
HALBB_HELP,
HALBB_DEMO,
HALBB_REG_RW,
HALBB_CMN_DBG,
HALBB_RA,
HALBB_PROFILE,
HALBB_TRACE,
HALBB_MP_DBG,
HALBB_SUPPORT_ABILITY,
HALBB_TX_PW,
HALBB_IC_API,
HALBB_LA_MODE,
HALBB_DUMP_REG,
HALBB_AUTO_DBG,
HALBB_DD_DBG,
HALBB_SHOW_RXRATE,
HALBB_NBI_EN,
HALBB_CSI_MASK_EN,
HALBB_DFS_DBG,
HALBB_DIG,
HALBB_NHM,
HALBB_CLM,
HALBB_IFS_CLM,
HALBB_FAHM,
HALBB_EDCCA_CLM,
HALBB_EDCCA,
HALBB_ENV_MNTR,
HALBB_BB_INFO,
HALBB_H2C,
HALBB_STASISTICS,
HALBB_PSD,
HALBB_DBG_PORT,
HALBB_CFO_TRK,
HALBB_ADAPTIVITY_DBG,
HALBB_STA_INFO,
HALBB_PAUSE_FUNC,
HALBB_PER_TONE_EVM,
HALBB_DYN_TXPWR,
HALBB_PHY_STATUS,
HALBB_DCC,
HALBB_PMAC_TX,
HALBB_FW_DBG,
HALBB_CH_INFO,
HALBB_RUA_TBL,
HALBB_TD_CFG,
HALBB_FD_CFG,
HALBB_DBCC,
HALBB_ANT_DIV,
HALBB_DCR_DBG,
HALBB_RX_GAIN_TABLE,
HALBB_HW_SETTING
};
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_cmd_info {
char name[16];
u8 id;
};
static const struct halbb_cmd_info halbb_cmd_i[] = {
{"-h", HALBB_HELP}, /*@do not move this element to other position*/
{"demo", HALBB_DEMO}, /*@do not move this element to other position*/
{"cr", HALBB_REG_RW},
{"cmn", HALBB_CMN_DBG},
{"ra", HALBB_RA},
{"profile", HALBB_PROFILE},
{"dbg", HALBB_TRACE},
{"mp_dbg", HALBB_MP_DBG},
{"ability", HALBB_SUPPORT_ABILITY},
{"tx_pw", HALBB_TX_PW},
{"ic_api", HALBB_IC_API},
{"lamode", HALBB_LA_MODE},
{"psd", HALBB_PSD},
{"dumpreg", HALBB_DUMP_REG},
//{"auto_dbg", HALBB_AUTO_DBG},
{"dd_dbg", HALBB_DD_DBG},
{"cfo_trk", HALBB_CFO_TRK},
{"rxrate", HALBB_SHOW_RXRATE},
//{"nbi", HALBB_NBI_EN},
//{"csi_mask", HALBB_CSI_MASK_EN},
{"dfs", HALBB_DFS_DBG},
{"dig", HALBB_DIG},
{"nhm", HALBB_NHM},
{"clm", HALBB_CLM},
{"ifs_clm", HALBB_IFS_CLM},
{"fahm", HALBB_FAHM},
{"edcca_clm", HALBB_EDCCA_CLM},
{"edcca", HALBB_EDCCA},
{"env_mntr", HALBB_ENV_MNTR},
//{"bbinfo", HALBB_BB_INFO},
//{"h2c", HALBB_H2C},
{"stat", HALBB_STASISTICS},
{"dbgport", HALBB_DBG_PORT},
{"sta_info", HALBB_STA_INFO},
{"pause", HALBB_PAUSE_FUNC},
{"physts", HALBB_PHY_STATUS},
{"pmac_tx", HALBB_PMAC_TX},
{"fw_dbg", HALBB_FW_DBG},
{"ch_info", HALBB_CH_INFO},
{"td", HALBB_TD_CFG},
{"fd", HALBB_FD_CFG},
{"dbcc", HALBB_DBCC},
{"rua", HALBB_RUA_TBL},
{"ant_div", HALBB_ANT_DIV},
{"dcr", HALBB_DCR_DBG},
{"gain_table", HALBB_RX_GAIN_TABLE},
{"hw_set", HALBB_HW_SETTING}
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dbg_cmd_table.h
|
C
|
agpl-3.0
| 3,366
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_DFS_SUPPORT
void halbb_dfs(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__);
if (!(bb->support_ability & BB_DFS))
return;
if (bb_dfs->dfs_dyn_setting_en)
halbb_dfs_dyn_setting(bb);
}
void halbb_dfs_init(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__);
/*DFS Parameter Initialization*/
bb_dfs->dfs_rgn_domain = bb->phl_com->dfs_info.region_domain;
halbb_dfs_rgn_dmn_dflt_cnfg(bb);
bb_dfs->chrp_obsrv_flag = false;
bb_dfs->dfs_sw_trgr_mode = false;
bb_dfs->dfs_dbg_mode = false;
bb_dfs->dfs_dyn_setting_en = true;
bb_dfs->dbg_prnt_en = false;
bb_dfs->is_mic_w53 = false;
bb_dfs->is_mic_w56 = false;
bb_dfs->chrp_th = DFS_CHIRP_TH;
bb_dfs->ppb_prcnt = DFS_PPB_IDLE_PRCNT;
bb_dfs->fk_dfs_num_th = 5;
bb_dfs->dfs_tp_th = 2;
bb_dfs->dfs_idle_prd_th = 50;
bb_dfs->dfs_fa_th = 20;
bb_dfs->dfs_nhm_th = 2;
bb_dfs->dfs_n_cnfd_lvl_th = 5;
}
void halbb_radar_detect_reset(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i;
halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 0);
halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 1);
}
void halbb_radar_detect_disable(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i;
halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 0);
}
void halbb_radar_detect_enable(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i;
halbb_set_reg_phy0_1(bb, cr->dfs_en, cr->dfs_en_m, 1);
}
bool halbb_is_dfs_band(struct bb_info *bb, u8 ch, u8 bw)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
bool is_w53_band = false, is_w56_band = false;
if ((ch >= 52) && (ch <= 64))
is_w53_band = true;
else if ((ch >= 100) && (ch <= 144))
is_w56_band = true;
#ifdef CONFIG_PHL_DFS_REGD_JAP
if (bb_dfs->dfs_rgn_domain == DFS_REGD_JAP)
halbb_dfs_rgn_dmn_cnfg_by_ch(bb, is_w53_band, is_w56_band);
#endif
if ((is_w53_band) || (is_w56_band))
return true;
else
return false;
}
void halbb_dfs_rgn_dmn_dflt_cnfg(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
u8 i;
/* PW unit: 200ns ; PRI unit: 25us */
#ifdef CONFIG_PHL_DFS_REGD_FCC
/*Type {0,1,2,3,4,6,L}*/
u8 pw_min_fcc_tab[DFS_RDR_TYP_NUM] = {5,5,5,30,55,5,250,0};
u16 pw_max_fcc_tab[DFS_RDR_TYP_NUM] = {5,5,25,50,100,5,500,1000};
u8 pri_min_fcc_tab[DFS_RDR_TYP_NUM] = {57,20,6,8,8,13,40,0};
u8 pri_max_fcc_tab[DFS_RDR_TYP_NUM] = {58,123,10,20,20,14,80,0};
u8 ppb_fcc_tab[DFS_RDR_TYP_NUM] = {18,18,23,16,12,9,8,255};
#endif
#ifdef CONFIG_PHL_DFS_REGD_ETSI
/*Type {1,2,3,4,5,6,R}*/
u8 pw_min_etsi_tab[DFS_RDR_TYP_NUM] = {2,2,2,100,2,2,5,0};
u16 pw_max_etsi_tab[DFS_RDR_TYP_NUM] = {25,75,75,150,10,10,5,1000};
u8 pri_min_etsi_tab[DFS_RDR_TYP_NUM] = {40,25,10,10,100,33,57,0};
u8 pri_max_etsi_tab[DFS_RDR_TYP_NUM] = {200,200,18,20,134,100,58,0};
u8 ppb_etsi_tab[DFS_RDR_TYP_NUM] = {10,15,25,20,10,15,18,255};
/*
etsi 302 Type {1,2,3,4,5,X,L}
u8 pw_min_etsi2_tab[DFS_RDR_TYP_NUM] = {5,5,50,5,5,0,100,0};
u16 pw_max_etsi2_tab[DFS_RDR_TYP_NUM] = {5,25,75,75,75,1000,150,1000};
u8 pri_min_etsi2_tab[DFS_RDR_TYP_NUM] = {53,40,40,25,10,0,10,0};
u8 pri_max_etsi2_tab[DFS_RDR_TYP_NUM] = {54,200,200,34,18,0,20,0};
u8 ppb_etsi2_tab[DFS_RDR_TYP_NUM] = {15,10,15,15,25,255,20,255};
*/
#endif
#ifdef CONFIG_PHL_DFS_REGD_FCC
if (bb_dfs->dfs_rgn_domain == DFS_REGD_FCC) {
bb_dfs->l_rdr_exst_flag = true;
for (i = 0; i < DFS_RDR_TYP_NUM ; i++) {
bb_dfs->pw_min_tab[i] = pw_min_fcc_tab[i];
bb_dfs->pw_max_tab[i] = pw_max_fcc_tab[i];
bb_dfs->pri_min_tab[i] = pri_min_fcc_tab[i];
bb_dfs->pri_max_tab[i] = pri_max_fcc_tab[i];
bb_dfs->ppb_tab[i] = ppb_fcc_tab[i];
}
}
#endif
#ifdef CONFIG_PHL_DFS_REGD_ETSI
if (bb_dfs->dfs_rgn_domain == DFS_REGD_ETSI) {
for (i = 0; i < DFS_RDR_TYP_NUM ; i++) {
bb_dfs->pw_min_tab[i] = pw_min_etsi_tab[i];
bb_dfs->pw_max_tab[i] = pw_max_etsi_tab[i];
bb_dfs->pri_min_tab[i] = pri_min_etsi_tab[i];
bb_dfs->pri_max_tab[i] = pri_max_etsi_tab[i];
bb_dfs->ppb_tab[i] = ppb_etsi_tab[i];
}
}
#endif
}
void halbb_dfs_rgn_dmn_cnfg_by_ch(struct bb_info *bb, bool w53_band,
bool w56_band)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
u8 i;
/* PW unit: 200ns ; PRI unit: 25us */
/*Type {1,2,3,4,5,6,7,8}*/
u8 pw_min_mic_w53_tab[DFS_RDR_TYP_NUM] = {2,2,2,2,2,2,2,2};
u16 pw_max_mic_w53_tab[DFS_RDR_TYP_NUM] = {25,75,25,75,8,8,8,8};
u8 pri_min_mic_w53_tab[DFS_RDR_TYP_NUM] = {40,25,40,25,35,42,44,53};
u8 pri_max_mic_w53_tab[DFS_RDR_TYP_NUM] = {200,200,200,200,36,44,46,55};
u8 ppb_mic_w53_tab[DFS_RDR_TYP_NUM] = {10,15,22,22,30,25,24,20};
/*Type {1,2,3,4,5,6,L,8}, ,ppb of Type3 is set as 15 due to RPT TO*/
u8 pw_min_mic_w56_tab[DFS_RDR_TYP_NUM] = {2,5,10,5,30,55,250,5};
u16 pw_max_mic_w56_tab[DFS_RDR_TYP_NUM] = {3,5,10,25,50,100,500,5};
u8 pri_min_mic_w56_tab[DFS_RDR_TYP_NUM] = {55,57,160,6,8,8,40,13};
u8 pri_max_mic_w56_tab[DFS_RDR_TYP_NUM] = {56,58,160,10,20,20,80,14};
u8 ppb_mic_w56_tab[DFS_RDR_TYP_NUM] = {18,18,15,23,16,12,8,9};
if (bb_dfs->dfs_rgn_domain == DFS_REGD_JAP) {
if (w53_band) {
bb_dfs->is_mic_w53 = true;
bb_dfs->l_rdr_exst_flag = false;
for (i = 0; i < DFS_RDR_TYP_NUM ; i++) {
bb_dfs->pw_min_tab[i] = pw_min_mic_w53_tab[i];
bb_dfs->pw_max_tab[i] = pw_max_mic_w53_tab[i];
bb_dfs->pri_min_tab[i] = pri_min_mic_w53_tab[i];
bb_dfs->pri_max_tab[i] = pri_max_mic_w53_tab[i];
bb_dfs->ppb_tab[i] = ppb_mic_w53_tab[i];
}
} else if (w56_band) {
bb_dfs->is_mic_w56 = true;
bb_dfs->l_rdr_exst_flag = true;
for (i = 0; i < DFS_RDR_TYP_NUM ; i++) {
bb_dfs->pw_min_tab[i] = pw_min_mic_w56_tab[i];
bb_dfs->pw_max_tab[i] = pw_max_mic_w56_tab[i];
bb_dfs->pri_min_tab[i] = pri_min_mic_w56_tab[i];
bb_dfs->pri_max_tab[i] = pri_max_mic_w56_tab[i];
bb_dfs->ppb_tab[i] = ppb_mic_w56_tab[i];
}
}
}
}
void halbb_radar_chrp_mntr(struct bb_info *bb, bool chrp_flag)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
u8 i = 0;
if (bb->bb_sys_up_time - bb_dfs->chrp_srt_t >= DFS_FCC_LP_LNGTH) {
bb_dfs->chrp_obsrv_flag = false;
bb_dfs->chrp_srt_t = 0;
bb_dfs->chrp_cnt = 0;
bb_dfs->lng_rdr_cnt = 0;
}
if ((chrp_flag) && !(bb_dfs->chrp_obsrv_flag)) {
bb_dfs->chrp_srt_t = bb->bb_sys_up_time;
bb_dfs->chrp_obsrv_flag = true;
}
if (bb_dfs->dbg_prnt_en)
BB_DBG(bb, DBG_DFS, "[mntr_prd, sys_t, chrp_srt_t]: [%d, %d, %d]\n",
(bb->bb_sys_up_time - bb_dfs->chrp_srt_t),
bb->bb_sys_up_time, bb_dfs->chrp_srt_t);
}
void halbb_radar_seq_inspctn(struct bb_info *bb, u16 dfs_rpt_idx,
u8 c_num, u8 p_num)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
if (dfs_rpt_idx != 0) {
if (p_num == DFS_MAX_SEQ_NUM) {
if (c_num != 0)
bb_dfs->n_seq_flag = true;
} else {
if (ABS_8(c_num - p_num) > 1)
bb_dfs->n_seq_flag = true;
}
}
if (bb_dfs->dbg_prnt_en) {
if (bb_dfs->n_seq_flag)
BB_DBG(bb, DBG_DFS, "[cur_seq_num, pre_seq_num] = [%d, %d]\n",
c_num, p_num);
}
bb_dfs->lst_seq_num = c_num;
}
void halbb_radar_ptrn_cmprn(struct bb_info *bb, u16 dfs_rpt_idx,
u8 pri, u16 pw, bool chrp_flag)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
u8 j = 0, pw_lbd = 0, pri_lbd = 0, pri_ubd = 0;
u16 pw_ubd = 0;
u8 pw_factor = 0,pri_factor = 0;
if (bb_dfs->l_rdr_exst_flag)
halbb_radar_chrp_mntr(bb, chrp_flag);
if (!bb_dfs->idle_flag ){
pw_factor = PW_FTR ;
pri_factor = PRI_FTR;
}
else {
pw_factor = PW_FTR_IDLE;
pri_factor = PRI_FTR_IDLE;
}
for (j = 0; j < DFS_RDR_TYP_NUM ; j++) {
pw_lbd = (bb_dfs->pw_min_tab[j] * (8 - pw_factor) >> 3);
pw_ubd = (bb_dfs->pw_max_tab[j] * (8 + pw_factor) >> 3);
pri_lbd = (bb_dfs->pri_min_tab[j] * (8 - pri_factor) >> 3);
if ((bb_dfs->pri_max_tab[j] * (8 + pri_factor) >> 3) <= 0xDC)
pri_ubd = (bb_dfs->pri_max_tab[j] * (8 + pri_factor) >> 3);
else
pri_ubd = 0xDC;
if (bb_dfs->is_mic_w53) {
if (j < 2) {
if ((pw_lbd <= pw) && (pw_ubd >= pw) &&
(pri_lbd <= pri) && (pri_ubd >= pri))
bb_dfs->srt_rdr_cnt[j]++;
} else if (j < 4) {
if ((pw_lbd <= pw) && (pw_ubd >= pw)) {
if (bb_dfs->pw_tmp >= 100 &&
bb_dfs->pw_tmp <= 550 &&
ABS_16(pw - bb_dfs->pw_tmp) >= 15 &&
pri + bb_dfs->pri_tmp >= pri_lbd &&
pri + bb_dfs->pri_tmp <= pri_ubd)
bb_dfs->srt_rdr_cnt[j]++;
}
} else {
if ((pw_lbd <= pw) && (pw_ubd >= pw)) {
if (bb_dfs->pw_tmp >= 150 &&
bb_dfs->pw_tmp <= 160 &&
pri + bb_dfs->pri_tmp >= pri_lbd &&
pri + bb_dfs->pri_tmp <= pri_ubd)
bb_dfs->srt_rdr_cnt[j]++;
}
}
} else {
if ((j == DFS_L_RDR_IDX) && (bb_dfs->l_rdr_exst_flag)) {
if ((pw_lbd <= pw) && (pw_ubd >= pw))
bb_dfs->lng_rdr_cnt++;
} else {
if ((pw_lbd <= pw) && (pw_ubd >= pw) &&
(pri_lbd <= pri) && (pri_ubd >= pri))
bb_dfs->srt_rdr_cnt[j]++;
}
}
if (dfs_rpt_idx == 0) {
if (bb_dfs->dbg_prnt_en) {
BB_DBG(bb, DBG_DFS, "pw_factor = %d, pri_factor = %d\n", pw_factor,pri_factor);
BB_DBG(bb, DBG_DFS, "Type %d: [pw_lbd-pw_ubd], [pri_lbd-pri_ubd] = [%d-%d], [%d-%d]\n",
(j + 1), pw_lbd, pw_ubd, pri_lbd, pri_ubd);
}
}
bb_dfs->pw_lbd[j] = pw_lbd;
bb_dfs->pw_ubd[j] = pw_ubd;
bb_dfs->pri_lbd[j] = pri_lbd;
bb_dfs->pri_ubd[j] = pri_ubd;
}
if (chrp_flag)
bb_dfs->chrp_cnt++;
bb_dfs->pri_tmp = pri;
bb_dfs->pw_tmp = pw;
}
void halbb_radar_info_processing(struct bb_info *bb,
struct hal_dfs_rpt *rpt, u16 dfs_rpt_idx)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
struct bb_rdr_info *dfs_rdr_info = NULL;
u8 pri = 0, cur_seq_num = 0, pre_seq_num = 0;
u16 pw = 0;
bool chrp_flag = false;
dfs_rdr_info = (struct bb_rdr_info *)rpt->dfs_ptr;
cur_seq_num = dfs_rdr_info->rdr_info_seq;
pre_seq_num = bb_dfs->lst_seq_num;
if (rpt->phy_idx == HW_PHY_0) {
pw = (dfs_rdr_info->rdr_info_sg0_pw_m << 7) |
(dfs_rdr_info->rdr_info_sg0_pw_l);
pri = (dfs_rdr_info->rdr_info_sg0_pri_m << 7) |
(dfs_rdr_info->rdr_info_sg0_pri_l);
chrp_flag = dfs_rdr_info->rdr_info_sg0_chirp_flag;
} else if (rpt->phy_idx == HW_PHY_1) {
pw = (dfs_rdr_info->rdr_info_sg1_pw_m << 4) |
(dfs_rdr_info->rdr_info_sg1_pw_l);
pri = (dfs_rdr_info->rdr_info_sg1_pri_m << 4) |
(dfs_rdr_info->rdr_info_sg1_pri_l);
chrp_flag = dfs_rdr_info->rdr_info_sg1_chirp_flag;
}
halbb_radar_ptrn_cmprn(bb, dfs_rpt_idx, pri, pw, chrp_flag);
halbb_radar_seq_inspctn(bb, dfs_rpt_idx, cur_seq_num, pre_seq_num);
if (bb_dfs->dbg_prnt_en)
BB_DBG(bb, DBG_DFS, "DFS_RPT: [pw, pri, c_flag] = [%d, %d, %d]\n",
pw, pri, chrp_flag);
if (dfs_rpt_idx == (rpt->dfs_num - 1)) {
if (bb_dfs->dbg_prnt_en) {
BB_DBG(bb, DBG_DFS, "\n");
BB_DBG(bb, DBG_DFS, "lng_rdr_cnt = %d\n", bb_dfs->lng_rdr_cnt);
BB_DBG(bb, DBG_DFS, "srt_rdr_cnt = [%d, %d, %d, %d, %d, %d, %d, %d]\n",
bb_dfs->srt_rdr_cnt[0], bb_dfs->srt_rdr_cnt[1],
bb_dfs->srt_rdr_cnt[2], bb_dfs->srt_rdr_cnt[3],
bb_dfs->srt_rdr_cnt[4], bb_dfs->srt_rdr_cnt[5],
bb_dfs->srt_rdr_cnt[6], bb_dfs->srt_rdr_cnt[7]);
BB_DBG(bb, DBG_DFS, "\n");
}
}
if (pri == 0)
bb_dfs->n_cnfd_lvl++;
if (bb_dfs->n_cnfd_lvl > bb_dfs->dfs_n_cnfd_lvl_th)
bb_dfs->n_cnfd_flag = true;
bb_dfs->pw_rpt[dfs_rpt_idx] = pw;
bb_dfs->pri_rpt[dfs_rpt_idx] = pri;
bb_dfs->chrp_rpt[dfs_rpt_idx] = chrp_flag;
rpt->dfs_ptr += DFS_RPT_LENGTH;
/* BB_DBG(bb, DBG_DFS, "dfs_ptr = %p\n", rpt->dfs_ptr); */
}
bool halbb_radar_detect(struct bb_info *bb, struct hal_dfs_rpt *dfs_rpt)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
bool rdr_detected = false;
u8 ppb_typ_th;
u16 i = 0;
if (bb_dfs->ppb_prcnt == DFS_PPB_ADPTV_PRCNT){
if (bb_dfs->dbg_prnt_en)
BB_DBG(bb, DBG_DFS, "Enable NHM-aided DFS!\n");
return rdr_detected;
}
if (!(bb->support_ability & BB_DFS)) {
BB_DBG(bb, DBG_DFS, "Not support DFS function!\n");
return false;
}
if (!(bb_dfs->l_rdr_exst_flag)) {
/* Check Fake DFS rpt */
if (dfs_rpt->dfs_num < bb_dfs->fk_dfs_num_th) {
if (bb_dfs->dbg_prnt_en) {
BB_DBG(bb, DBG_DFS, "Non-existent form of DFS!\n");
BB_DBG(bb, DBG_DFS, "\n");
}
return false;
}
}
if (bb_dfs->dbg_prnt_en) {
BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__);
BB_DBG(bb, DBG_DFS, "phy_idx = %d, dfs_num = %d\n",
dfs_rpt->phy_idx, dfs_rpt->dfs_num);
}
/* DFS Info Parsing/Processing*/
for (i = 0; i < (dfs_rpt->dfs_num) ; i++)
halbb_radar_info_processing(bb, dfs_rpt, i);
for (i = 0; i < DFS_RDR_TYP_NUM ; i++) {
ppb_typ_th = ((bb_dfs->ppb_tab[i] * bb_dfs->ppb_prcnt) >> 3);
if ((i == DFS_L_RDR_IDX) && (bb_dfs->l_rdr_exst_flag)) {
if ((bb_dfs->lng_rdr_cnt >= ppb_typ_th) &&
(bb_dfs->chrp_cnt >= bb_dfs->chrp_th)) {
rdr_detected = true;
BB_DBG(bb, DBG_DFS, "Chrp Rdr Appeared!\n");
BB_DBG(bb, DBG_DFS, "Long Rdr reaches threshold (ppb_th:%d / chirp_th:%d)!\n",
ppb_typ_th,bb_dfs->chrp_th);
}
} else {
if (bb_dfs->srt_rdr_cnt[i] >= ppb_typ_th) {
if (bb_dfs->n_seq_flag) {
rdr_detected = false;
BB_DBG(bb, DBG_DFS, "Non-sequential DFS Dropped!\n");
} else if (bb_dfs->n_cnfd_flag) {
rdr_detected = false;
BB_DBG(bb, DBG_DFS, "Non-confidential DFS Blocked!\n");
} else {
rdr_detected = true;
BB_DBG(bb, DBG_DFS, "Rdr Type %d reaches threshold (ppb_th:%d)!\n",
(i+1), ppb_typ_th);
}
}
}
}
/* Debug Mode */
if (rdr_detected) {
if (!(bb_dfs->dbg_prnt_en)) {
BB_DBG(bb, DBG_DFS, "[%s]===>\n", __func__);
BB_DBG(bb, DBG_DFS, "phy_idx = %d, dfs_num = %d\n",
dfs_rpt->phy_idx, dfs_rpt->dfs_num);
for (i = 0; i < DFS_RDR_TYP_NUM ; i++) {
BB_DBG(bb, DBG_DFS, "Type %d: [pw_lbd-pw_ubd], [pri_lbd-pri_ubd] = [%d-%d], [%d-%d]\n",
(i+1), bb_dfs->pw_lbd[i],
bb_dfs->pw_ubd[i], bb_dfs->pri_lbd[i],
bb_dfs->pri_ubd[i]);
}
for (i = 0; i < dfs_rpt->dfs_num ; i++) {
BB_DBG(bb, DBG_DFS, "DFS_RPT %d: [pw, pri, c_flag] = [%d, %d, %d]\n",
(i + 1), bb_dfs->pw_rpt[i], bb_dfs->pri_rpt[i],
bb_dfs->chrp_rpt[i]);
}
BB_DBG(bb, DBG_DFS, "lng_rdr_cnt = %d, chrp_cnt = %d\n", bb_dfs->lng_rdr_cnt,bb_dfs->chrp_cnt);
BB_DBG(bb, DBG_DFS, "srt_rdr_cnt = [%d, %d, %d, %d, %d, %d, %d, %d]\n",
bb_dfs->srt_rdr_cnt[0], bb_dfs->srt_rdr_cnt[1],
bb_dfs->srt_rdr_cnt[2], bb_dfs->srt_rdr_cnt[3],
bb_dfs->srt_rdr_cnt[4], bb_dfs->srt_rdr_cnt[5],
bb_dfs->srt_rdr_cnt[6], bb_dfs->srt_rdr_cnt[7]);
}
if (bb_dfs->dfs_dbg_mode) {
rdr_detected = false;
BB_DBG(bb, DBG_DFS, "Radar is detected in DFS debug mode!\n");
}
}
/* SW Trigger Mode */
if (bb_dfs->dfs_sw_trgr_mode) {
rdr_detected = true;
BB_DBG(bb, DBG_DFS, "[HALBB] Radar SW-Trigger Mode!\n");
}
/* Reset SW Counter/Flag */
bb_dfs->n_seq_flag = false;
bb_dfs->n_cnfd_flag = false;
bb_dfs->n_cnfd_lvl = 0;
for (i = 0; i < DFS_RDR_TYP_NUM ; i++)
bb_dfs->srt_rdr_cnt[i] = 0;
for (i = 0; i < dfs_rpt->dfs_num ; i++) {
bb_dfs->pw_rpt[i] = 0;
bb_dfs->pri_rpt[i] = 0;
bb_dfs->chrp_rpt[i] = 0;
}
return rdr_detected;
}
void halbb_dfs_dyn_setting(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
struct bb_link_info *link = &bb->bb_link_i;
struct bb_env_mntr_info *env_mntr = &bb->bb_env_mntr_i;
#ifdef HALBB_STATISTICS_SUPPORT
struct bb_stat_info *stat = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat->bb_fa_i;
#endif
if (link->total_tp < bb_dfs->dfs_tp_th)
bb_dfs->idle_flag = true;
else
bb_dfs->idle_flag = false;
if ((env_mntr->nhm_idle_ratio > bb_dfs->dfs_idle_prd_th) &&
(fa->cnt_fail_all < bb_dfs->dfs_fa_th) &&
(env_mntr->nhm_ratio < bb_dfs->dfs_nhm_th)) {
if (bb_dfs->idle_flag)
bb_dfs->ppb_prcnt = DFS_PPB_IDLE_PRCNT;
else
bb_dfs->ppb_prcnt = DFS_PPB_PRCNT;
BB_DBG(bb, DBG_DFS, "[DFS Status] Normal DFS Mode\n");
} else {
bb_dfs->ppb_prcnt = DFS_PPB_ADPTV_PRCNT;
BB_DBG(bb, DBG_DFS, "[DFS Status] Adaptive DFS Mode\n");
}
BB_DBG(bb, DBG_DFS, "[T_TP / I_RTO / FA_CNT / N_RTO] = [%d, %d, %d, %d]\n",
link->total_tp, env_mntr->nhm_idle_ratio,
fa->cnt_fail_all, env_mntr->nhm_ratio);
}
void halbb_dfs_debug(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{1} Set DFS_SW_TRGR_MODE => {0}: Disable, {1}: Enable\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{2} Set DFS_DBG_MODE => {0}: Disable, {1}: Enable\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{3} Set DBG_PRINT => {0}: Disable, {1}: Enable\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{4} Set DYN_SETTING_EN => {0}: Disable, {1}: Enable\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{5} Set Detection Parameter => \n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{1} Set the threshold of fake DFS number => {Num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{2} Set the threshold of chirp number => {Num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{3} Set the threshold of ppb percent => {Percent: 1-8}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{4} Set the threshold of DFS_TP Threshold => {Mbps}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{5} Set the threshold of DFS_Idle_Period Threshold => {Percent: 0-100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{6} Set the threshold of DFS_FA Threshold => {Num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{7} Set the threshold of DFS_NHM Threshold => {Percent: 0-100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---{8} Set the threshold of DFS_N_CNFD_Level Threshold => {Num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{100} Show all parameter\n");
} else if (var[0] == 100) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS Region Domain: %s\n",
(bb_dfs->dfs_rgn_domain > 1) ?
(bb_dfs->dfs_rgn_domain > 2) ?
"ETSI": "MIC" : "FCC");
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_SW_TRGR_MODE = %d\n",
bb_dfs->dfs_sw_trgr_mode);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_DBG_MODE = %d\n",
bb_dfs->dfs_dbg_mode);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DBG_PRINT = %d\n",
bb_dfs->dbg_prnt_en);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DYN_SETTING_EN = %d\n",
bb_dfs->dfs_dyn_setting_en);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "Fake DFS Num Threshold = %d\n",
bb_dfs->fk_dfs_num_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "Chirp Number = %d\n",
bb_dfs->chrp_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "PPB Percent = %d\n",
bb_dfs->ppb_prcnt);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_TP Threshold = %d\n",
bb_dfs->dfs_tp_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_Idle_Period Threshold = %d\n",
bb_dfs->dfs_idle_prd_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_FA Threshold = %d\n",
bb_dfs->dfs_fa_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_NHM Threshold = %d\n",
bb_dfs->dfs_nhm_th);
BB_DBG_CNSL(out_len, used, output + used, out_len - used, "DFS_N_CNFD_Level Threshold = %d\n",
bb_dfs->dfs_n_cnfd_lvl_th);
} else {
if (var[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dfs->dfs_sw_trgr_mode = (bool)var[1];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "DFS_SW_TRGR_MODE = %d\n",
bb_dfs->dfs_sw_trgr_mode);
} else if (var[0] == 2) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dfs->dfs_dbg_mode = (bool)var[1];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "DFS_DBG_MODE = %d\n",
bb_dfs->dfs_dbg_mode);
} else if (var[0] == 3) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dfs->dbg_prnt_en = (bool)var[1];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "DBG_PRINT = %d\n",
bb_dfs->dbg_prnt_en);
} else if (var[0] == 4) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dfs->dfs_dyn_setting_en = (bool)var[1];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "DYN_SETTING_EN = %d\n",
bb_dfs->dfs_dyn_setting_en);
} else if (var[0] == 5) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
if (var[1] == 1) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->fk_dfs_num_th = (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "fk_dfs_num_th = %d\n",
bb_dfs->fk_dfs_num_th);
} else if (var[1] == 2) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->chrp_th= (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "chrp_th = %d\n",
bb_dfs->chrp_th);
} else if (var[1] == 3) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->ppb_prcnt = (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "ppb_prcnt = %d\n",
bb_dfs->ppb_prcnt);
} else if (var[1] == 4) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->dfs_tp_th = (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "dfs_tp_th = %d\n",
bb_dfs->dfs_tp_th);
} else if (var[1] == 5) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->dfs_idle_prd_th = (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "dfs_idle_prd_th = %d\n",
bb_dfs->dfs_idle_prd_th);
} else if (var[1] == 6) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->dfs_fa_th= (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "dfs_fa_th = %d\n",
bb_dfs->dfs_fa_th);
} else if (var[1] == 7) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->dfs_nhm_th= (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "dfs_nhm_th = %d\n",
bb_dfs->dfs_nhm_th);
} else if (var[1] == 8) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
bb_dfs->dfs_n_cnfd_lvl_th= (u8)var[2];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "dfs_n_cnfd_lvl_th = %d\n",
bb_dfs->dfs_n_cnfd_lvl_th);
}
}
}
*_used = used;
*_out_len = out_len;
}
void halbb_cr_cfg_dfs_init(struct bb_info *bb)
{
struct bb_dfs_info *bb_dfs = &bb->bb_dfs_i;
struct bb_dfs_cr_info *cr = &bb_dfs->bb_dfs_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_52AA:
/*cr->dfs_en = DFS_EN_52AA;
cr->dfs_en_m = DFS_EN_52AA_M;
*/
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->dfs_en = DFS_EN_A;
cr->dfs_en_m = DFS_EN_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->dfs_en = DFS_EN_C;
cr->dfs_en_m = DFS_EN_C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dfs.c
|
C
|
agpl-3.0
| 24,585
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DFS_H__
#define __HALBB_DFS_H__
/*@--------------------------[Define] ---------------------------------------*/
#define DFS_RPT_LENGTH 8
#define DFS_RDR_TYP_NUM 8
#define DFS_L_RDR_IDX 6
#define PW_FTR_IDLE 1
#define PRI_FTR_IDLE 1
#define PW_FTR 3
#define PRI_FTR 3
#define DFS_PPB_PRCNT 4
#define DFS_PPB_IDLE_PRCNT 5
#define DFS_PPB_ADPTV_PRCNT 8
#define DFS_CHIRP_TH 3
#define DFS_FCC_LP_LNGTH 12 /*Real Waveform length of FCC-LP is 12 secs*/
#define DFS_MAX_SEQ_NUM 127
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dfs_cr_info {
u32 dfs_en;
u32 dfs_en_m;
};
struct bb_dfs_info {
struct bb_dfs_cr_info bb_dfs_cr_i;
u8 dfs_rgn_domain;
u8 ppb_prcnt;
u16 pw_rpt[DFS_MAX_SEQ_NUM];
u8 pri_rpt[DFS_MAX_SEQ_NUM];
bool chrp_rpt[DFS_MAX_SEQ_NUM];
u8 chrp_cnt;
u8 chrp_th;
u32 chrp_srt_t;
u8 n_cnfd_lvl;
u8 lng_rdr_cnt;
u8 srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 pw_lbd[DFS_RDR_TYP_NUM];
u16 pw_ubd[DFS_RDR_TYP_NUM];
u8 pri_lbd[DFS_RDR_TYP_NUM];
u8 pri_ubd[DFS_RDR_TYP_NUM];
u8 pw_min_tab[DFS_RDR_TYP_NUM];
u16 pw_max_tab[DFS_RDR_TYP_NUM];
u8 pri_min_tab[DFS_RDR_TYP_NUM];
u8 pri_max_tab[DFS_RDR_TYP_NUM];
u8 ppb_tab[DFS_RDR_TYP_NUM];
u8 lst_seq_num;
u8 pri_tmp;
u16 pw_tmp;
bool is_mic_w53;
bool is_mic_w56;
bool l_rdr_exst_flag;
bool chrp_obsrv_flag;
bool n_cnfd_flag;
bool n_seq_flag;
bool idle_flag;
bool dfs_sw_trgr_mode;
bool dfs_dbg_mode;
bool dbg_prnt_en;
u8 fk_dfs_num_th;
u8 dfs_tp_th;
u8 dfs_idle_prd_th;
u8 dfs_fa_th;
u8 dfs_nhm_th;
u8 dfs_n_cnfd_lvl_th;
bool dfs_dyn_setting_en;
};
struct bb_dfs_rpt {
u8 *dfs_ptr;
u16 dfs_num;
u8 phy_idx; /*phy0,phy1*/
};
#if (PLATFOM_IS_LITTLE_ENDIAN)
struct bb_rdr_info {
u8 rdr_info_sg0_chirp_flag:1; /*[18:9],[8:1],[0]*/
u8 rdr_info_sg0_pri_l:7;
u8 rdr_info_sg0_pri_m:1;
u8 rdr_info_sg0_pw_l:7;
u8 rdr_info_sg0_pw_m:3;
u8 rdr_info_sg1_chirp_flag:1; /*[37:28],[27:20],[19]*/
u8 rdr_info_sg1_pri_l:4;
u8 rdr_info_sg1_pri_m:4;
u8 rdr_info_sg1_pw_l:4;
u8 rdr_info_sg1_pw_m:6;
u8 rdr_info_zw_chirp_flag:1; /*[56:47],[46:39],[38]*/
u8 rdr_info_zw_pri_l:1;
u8 rdr_info_zw_pri_m:7;
u8 rdr_info_zw_pw_l:1;
u8 rdr_info_zw_pw_m;
u8 rdr_info_zw_pw_h:1;
u8 rdr_info_seq:7;
};
#else
struct bb_rdr_info {
u8 rdr_info_sg0_pri_l:7;
u8 rdr_info_sg0_chirp_flag:1;
u8 rdr_info_sg0_pw_l:7;
u8 rdr_info_sg0_pri_m:1;
u8 rdr_info_sg1_pri_l:4;
u8 rdr_info_sg1_chirp_flag:1;
u8 rdr_info_sg0_pw_m:3;
u8 rdr_info_sg1_pw_l:4;
u8 rdr_info_sg1_pri_m:4;
u8 rdr_info_zw_pri_l:1;
u8 rdr_info_zw_chirp_flag:1;
u8 rdr_info_sg1_pw_m:6;
u8 rdr_info_zw_pw_l:1;
u8 rdr_info_zw_pri_m:7;
u8 rdr_info_zw_pw_m;
u8 rdr_info_seq:7;
u8 rdr_info_zw_pw_h:1;
};
#endif
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
struct hal_dfs_rpt;
void halbb_dfs(struct bb_info *bb);
void halbb_dfs_rgn_dmn_dflt_cnfg(struct bb_info *bb);
void halbb_dfs_rgn_dmn_cnfg_by_ch(struct bb_info *bb, bool w53_band,
bool w56_band);
void halbb_radar_chrp_mntr(struct bb_info *bb, bool chrp_flag);
void halbb_radar_seq_inspctn(struct bb_info *bb, u16 dfs_rpt_idx,
u8 c_num, u8 p_num);
void halbb_radar_ptrn_cmprn(struct bb_info *bb, u16 dfs_rpt_idx,
u8 pri, u16 pw, bool chrp_flag);
void halbb_radar_info_processing(struct bb_info *bb,
struct hal_dfs_rpt *dfs_rpt, u16 dfs_rpt_idx);
void halbb_dfs_dyn_setting(struct bb_info *bb);
void halbb_dfs_debug(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_dfs_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dfs.h
|
C
|
agpl-3.0
| 4,643
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DFS_EX_H__
#define __HALBB_DFS_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
struct hal_dfs_rpt;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_dfs_init(struct bb_info *bb);
void halbb_radar_detect_reset(struct bb_info *bb);
void halbb_radar_detect_disable(struct bb_info *bb);
void halbb_radar_detect_enable(struct bb_info *bb);
bool halbb_is_dfs_band(struct bb_info *bb, u8 ch, u8 pri_ch);
bool halbb_radar_detect(struct bb_info *bb, struct hal_dfs_rpt *rpt);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dfs_ex.h
|
C
|
agpl-3.0
| 1,713
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_DIG_SUPPORT
#ifdef BB_8852A_2_SUPPORT
u8 halbb_lna_idx_by_rssi(struct bb_info *bb, u8 rssi)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
u8 lna_idx = LNA_IDX_MAX;
if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[0])
lna_idx = 6;
else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[1])
lna_idx = 5;
else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[2])
lna_idx = 4;
else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[3])
lna_idx = 3;
else if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[4])
lna_idx = 2;
else
lna_idx = 1;
return lna_idx;
}
u8 halbb_tia_idx_by_rssi(struct bb_info *bb, u8 rssi)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
u8 tia_idx = TIA_IDX_MAX;
if (rssi < bb_dig_u->dig_op_para.igi_rssi_th[0])
tia_idx = 1;
else
tia_idx = 0;
return tia_idx;
}
u8 halbb_rxb_idx_by_rssi(struct bb_info *bb,
struct agc_gaincode_set *set, u8 rssi)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
u8 rxb_idx = RXB_IDX_MAX;
s8 lna_gain = bb_dig->lna_gain[set->lna_idx];
s8 tia_gain = bb_dig->tia_gain[set->tia_idx];
s32 rxb_idx_tmp = RXB_IDX_MAX;
s32 wb_rssi = rssi + lna_gain + tia_gain;
rxb_idx_tmp = (bb_dig->ib_pkpwr - bb_dig->ib_pbk + 110) - wb_rssi + 10;
if (rxb_idx_tmp > RXB_IDX_MAX)
rxb_idx = RXB_IDX_MAX;
else if (rxb_idx_tmp < RXB_IDX_MIN)
rxb_idx = RXB_IDX_MIN;
else
rxb_idx = (u8)rxb_idx_tmp;
BB_DIG_DBG(bb, DIG_DBG_LV2, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
wb_rssi, rxb_idx_tmp);
return rxb_idx;
}
void halbb_dig_set_igi_cr_8852a(struct bb_info *bb, const struct agc_gaincode_set set)
{
if (bb->ic_type != BB_RTL8852A)
return;
halbb_set_igi_8852a_2(bb, set.lna_idx, set.tia_idx, set.rxb_idx, RF_PATH_A);
halbb_set_igi_8852a_2(bb, set.lna_idx, set.tia_idx, set.rxb_idx, RF_PATH_B);
BB_DIG_DBG(bb, DIG_DBG_LV1, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
set.lna_idx, set.tia_idx, set.rxb_idx);
}
void halbb_dig_agc_update_8852a(struct bb_info *bb, struct bb_dig_op_para_unit *para)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
u8 igi_rssi_th_ifem[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
u8 igi_rssi_th_efem[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
u8 *igi_rssi_th;
if (bb->ic_type != BB_RTL8852A)
return;
/* gain para update */
bb_dig->lna_gain = bb_dig->lna_gain_g;
bb_dig->tia_gain = bb_dig->tia_gain_g;
/* igi rssi th update */
switch (bb->phl_com->dev_cap.rfe_type) {
case 51:
case 52:
case 53:
case 54:
igi_rssi_th = igi_rssi_th_efem;
break;
default:
igi_rssi_th = igi_rssi_th_ifem;
}
halbb_mem_cpy(bb, ¶->igi_rssi_th, igi_rssi_th, sizeof(u8) * IGI_RSSI_TH_NUM);
BB_DIG_DBG(bb, DIG_DBG_LV1, "Sigi_rssi_th[4:0] = %d,%d,%d,%d,%d\n",
para->igi_rssi_th[4], para->igi_rssi_th[3],
para->igi_rssi_th[2], para->igi_rssi_th[1],
para->igi_rssi_th[0]);
}
#if 0
void halbb_dig_write_igi_8852a(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode);
}
#endif
void halbb_gaincode_by_rssi_8852a(struct bb_info *bb,
struct agc_gaincode_set *set, u8 rssi) {
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
if (bb->ic_type != BB_RTL8852A)
return;
set->lna_idx = halbb_lna_idx_by_rssi(bb, rssi);
set->tia_idx = halbb_tia_idx_by_rssi(bb, rssi);
set->rxb_idx = halbb_rxb_idx_by_rssi(bb, set, rssi);
BB_DIG_DBG(bb, DIG_DBG_LV1, "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
}
bool halbb_dig_gaincode_update_en_8852a(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
struct rtw_hw_band *hw_band = &bb->hal_com->band[bb->bb_phy_idx];
if ((bb->ic_type != BB_RTL8852A) || (bb->hal_com->cv >= CCV))
return false;
if (hw_band->cur_chandef.band != BAND_ON_24G)
return false;
halbb_gaincode_by_rssi_8852a(bb, &bb_dig_u->cur_gaincode, bb_dig_u->igi_fa_rssi);
return true;
}
#endif
#ifdef HALBB_DIG_DAMPING_CHK
void halbb_dig_recorder_reset(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i;
BB_DBG(bb, DBG_DIG, "%s ======>\n", __func__);
halbb_mem_set(bb, dig_rc, 0, sizeof(struct bb_dig_record_info));
}
void halbb_dig_recorder(struct bb_info *bb, u8 igi_curr, u32 fa_metrics)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i;
u8 igi_pre = dig_rc->igi_history[0];
u8 igi_up = 0;
// if (!bb->bb_link_i.is_linked)
// return;
BB_DBG(bb, DBG_DIG, "%s ======>\n", __func__);
#if 0
if (bb->bb_link_i.first_connect) {
BB_DBG(bb, DBG_DIG, "first_connect\n");
halbb_dig_recorder_reset(bb);
dig_rc->igi_history[0] = igi_curr;
dig_rc->fa_history[0] = fa_metrics;
return;
}
#endif
igi_pre = dig_rc->igi_history[0];
igi_up = (igi_curr > igi_pre) ? 1 : 0;
dig_rc->igi_bitmap = (dig_rc->igi_bitmap << 1) | igi_up;
dig_rc->igi_history[5] = dig_rc->igi_history[4];
dig_rc->igi_history[4] = dig_rc->igi_history[3];
dig_rc->igi_history[3] = dig_rc->igi_history[2];
dig_rc->igi_history[2] = dig_rc->igi_history[1];
dig_rc->igi_history[1] = dig_rc->igi_history[0];
dig_rc->igi_history[0] = igi_curr;
dig_rc->fa_history[5] = dig_rc->fa_history[4];
dig_rc->fa_history[4] = dig_rc->fa_history[3];
dig_rc->fa_history[3] = dig_rc->fa_history[2];
dig_rc->fa_history[2] = dig_rc->fa_history[1];
dig_rc->fa_history[1] = dig_rc->fa_history[0];
dig_rc->fa_history[0] = fa_metrics;
BB_DBG(bb, DBG_DIG, "igi_history[5:0] = {%02d, %02d, %02d, %02d, %02d, %02d}\n",
dig_rc->igi_history[5], dig_rc->igi_history[4], dig_rc->igi_history[3], dig_rc->igi_history[2],
dig_rc->igi_history[1], dig_rc->igi_history[0]);
BB_DBG(bb, DBG_DIG, "fa_history[5:0] = {%02d, %02d, %02d, %02d, %02d, %02d}\n",
dig_rc->fa_history[5], dig_rc->fa_history[4], dig_rc->fa_history[3], dig_rc->fa_history[2],
dig_rc->fa_history[1], dig_rc->fa_history[0]);
BB_DBG(bb, DBG_DIG, "igi_bitmap[5:0]=0x%x{ %d, %d, %d, %d, %d, %d}\n",
dig_rc->igi_bitmap,
(dig_rc->igi_bitmap & BIT5) >> 5,
(dig_rc->igi_bitmap & BIT4) >> 4,
(dig_rc->igi_bitmap & BIT3) >> 3,
(dig_rc->igi_bitmap & BIT2) >> 2,
(dig_rc->igi_bitmap & BIT1) >> 1,
dig_rc->igi_bitmap & BIT0);
}
void halbb_dig_damping_chk(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i;
struct bb_dig_op_unit *bb_dig_u = dig->p_cur_dig_unit;
u8 diff1 = 0, diff2 = 0;
u32 fa_low_th = bb_dig_u->dig_op_para.fa_th[0];
u32 fa_high_th = bb_dig_u->dig_op_para.fa_th[1];
u32 fa_high_th2 = bb_dig_u->dig_op_para.fa_th[2];
u32 fa_high_th3 = bb_dig_u->dig_op_para.fa_th[3];
bool fa_pattern_match = false;
u32 time_tmp = 0;
if (!bb->bb_link_i.is_linked)
return;
BB_DBG(bb, DBG_DIG, "%s ======>\n", __func__);
/*@== Release Damping ================================================*/
if (dig_rc->damping_lock_en) {
BB_DBG(bb, DBG_DIG,
"[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
dig_rc->limit_time, bb->bb_sys_up_time);
time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
if (DIFF_2(bb->bb_ch_i.rssi_min, dig_rc->limit_rssi) > dig->rls_rssi_diff_th ||
time_tmp < bb->bb_sys_up_time) {
dig_rc->damping_lock_en = false;
BB_DBG(bb, DBG_DIG, "[Rls] rssi=%d.%d, limit_rssi=%d.%d, th=%d.%d\n",
bb->bb_ch_i.rssi_min >> 1,
(bb->bb_ch_i.rssi_min & 1) * 5,
dig_rc->limit_rssi >> 1,
(dig_rc->limit_rssi & 1) * 5,
dig->rls_rssi_diff_th >> 1,
(dig->rls_rssi_diff_th & 1) * 5);
}
return;
}
/*@== Damping Pattern Check===========================================*/
BB_DBG(bb, DBG_DIG, "fa_th{H2, H2, H1, L}= {%d,%d,%d,%d}\n",
fa_high_th3, fa_high_th2, fa_high_th, fa_low_th);
if ((dig_rc->igi_bitmap & 0xf) == 0x5) {
BB_DBG(bb, DBG_DIG, "[Type:0] map=0x5\n");
/*@ 4b'0101
* IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
* FA: [3] >high1 ->[2] <low ->[1] >high1 ->[0] <low ->[new] <low
*
* IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
* FA: [3] >high2 ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
*/
if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
if (dig_rc->fa_history[0] < fa_low_th &&
dig_rc->fa_history[1] >= fa_high_th &&
dig_rc->fa_history[2] < fa_low_th &&
dig_rc->fa_history[3] >= fa_high_th) {
/*@Check each fa element*/
fa_pattern_match = true;
}
} else if ((dig_rc->igi_bitmap & 0x1f) == 0x9) {
BB_DBG(bb, DBG_DIG, "[Type:1] map=0x9\n");
/*@ 5b'01001
* IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
* FA: [3] <low ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
*/
if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
if (dig_rc->igi_history[3] > dig_rc->igi_history[4])
diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[4];
if (dig_rc->fa_history[0] < fa_low_th &&
dig_rc->fa_history[1] >= fa_high_th2 &&
dig_rc->fa_history[2] < fa_low_th &&
dig_rc->fa_history[3] < fa_low_th) {
/*@Check each fa element*/
fa_pattern_match = true;
}
} else if ((dig_rc->igi_bitmap & 0x3f) == 0x11) {
BB_DBG(bb, DBG_DIG, "[Type:2] map=0x11\n");
/*@ 6b'010001
* IGI:[4]up(0x28)->[3]down(0x26)->[2]down(0x24)->[1]down(0x22)->[0]up(0x28)->[new](Lock @ 0x28)
* FA: [4] <low ->[3] <low ->[2] <low ->[1] >high3 ->[0] <low ->[new] <low
*/
if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
if (dig_rc->igi_history[4] > dig_rc->igi_history[5])
diff2 = dig_rc->igi_history[4] - dig_rc->igi_history[5];
if (dig_rc->fa_history[0] < fa_low_th &&
dig_rc->fa_history[1] >= fa_high_th3 &&
dig_rc->fa_history[2] < fa_low_th &&
dig_rc->fa_history[3] < fa_low_th &&
dig_rc->fa_history[4] < fa_low_th) {
/*@Check each fa element*/
fa_pattern_match = true;
}
}
if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
dig_rc->damping_lock_en = true;
dig_rc->damping_limit_val = dig_rc->igi_history[0];
dig_rc->limit_time = bb->bb_sys_up_time;
dig_rc->limit_rssi = bb->bb_ch_i.rssi_min;
BB_DBG(bb, DBG_DIG,
"[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
dig_rc->damping_limit_val,
dig_rc->limit_time, dig_rc->limit_rssi >> 1);
}
BB_DBG(bb, DBG_DIG, "[lock_en=%d] ptrn_match=%d, diff1=%d, diff2=%d\n",
dig_rc->damping_lock_en, fa_pattern_match, diff1, diff2);
}
void halbb_dig_damping_chk_init(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i;
halbb_dig_recorder_reset(bb);
dig->dig_dl_en = true;
dig->rls_rssi_diff_th = 6; /*6 >> 1 = 3dB*/
}
#endif
u8 halbb_get_lna_idx(struct bb_info *bb, enum rf_path path)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u8 lna_idx = LNA_IDX_MAX;
/*lna initial gain index*/
switch (path) {
case RF_PATH_A:
lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_lna_init_idx,
cr->path0_lna_init_idx_m,
bb->bb_phy_idx);
break;
case RF_PATH_B:
lna_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_lna_init_idx,
cr->path1_lna_init_idx_m,
bb->bb_phy_idx);
break;
default:
break;
}
return lna_idx;
}
u8 halbb_get_tia_idx(struct bb_info *bb, enum rf_path path)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u8 tia_idx = TIA_IDX_MAX;
switch (path) {
case RF_PATH_A:
tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path0_tia_init_idx,
cr->path0_tia_init_idx_m,
bb->bb_phy_idx);
break;
case RF_PATH_B:
tia_idx = (u8)halbb_get_reg_cmn(bb, cr->path1_tia_init_idx,
cr->path1_tia_init_idx_m,
bb->bb_phy_idx);
break;
default:
break;
}
return tia_idx;
}
u8 halbb_get_rxb_idx(struct bb_info *bb, enum rf_path path)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u8 rxb_idx = RXB_IDX_MAX;
switch (path) {
case RF_PATH_A:
rxb_idx = (u8)halbb_get_reg_cmn(bb,
cr->path0_rxb_init_idx,
cr->path0_rxb_init_idx_m,
bb->bb_phy_idx);
break;
case RF_PATH_B:
rxb_idx = (u8)halbb_get_reg_cmn(bb,
cr->path1_rxb_init_idx,
cr->path1_rxb_init_idx_m,
bb->bb_phy_idx);
break;
default:
break;
}
return rxb_idx;
}
u8 halbb_igi_by_edcca(struct bb_info *bb, u8 igi)
{
#ifdef HALBB_EDCCA_SUPPORT
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
const u8 margin = IGI_EDCCA_GAP_LIMIT - 18; /* -128(dBm)+110(RSSI) */
u8 bound = bb->bb_edcca_i.th_h;
bound = margin > (EDCCA_MAX - bound) ? EDCCA_MAX : (bound + margin);
if (igi > bound) {
igi = bound;
BB_DIG_DBG(bb, DIG_DBG_LV0, "EDCCA th_h = %d, IGI upper clamp to %d.\n",
bb->bb_edcca_i.th_h, bound);
}
#endif
return igi;
}
void halbb_dig_noisy_lv_decision(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
struct bb_dig_op_para_unit *para = &bb_dig_u->dig_op_para;
u16 fa_ratio = bb_dig_u->fa_r_avg;
if (bb_dig_u->fa_valid_state_cnt == 0) {
bb_dig_u->cur_noisy_lv = DIG_NOISY_LV1;
BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_ratio N/A, set noisy_lv=%d\n", DIG_NOISY_LV1);
return;
}
if (fa_ratio < para->fa_th[0])
bb_dig_u->cur_noisy_lv = DIG_NOISY_LV0;
else if (fa_ratio < para->fa_th[1])
bb_dig_u->cur_noisy_lv = DIG_NOISY_LV1;
else if (fa_ratio < para->fa_th[2])
bb_dig_u->cur_noisy_lv = DIG_NOISY_LV2;
else if (fa_ratio < para->fa_th[3])
bb_dig_u->cur_noisy_lv = DIG_NOISY_LV3;
else
bb_dig_u->cur_noisy_lv = DIG_NOISY_LV_MAX;
BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
para->fa_th[3], para->fa_th[2], para->fa_th[1], para->fa_th[0]);
BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_avg=%d, noisy_lv=%d\n",
bb_dig_u->fa_r_avg, bb_dig_u->cur_noisy_lv);
bb_dig_u->fa_valid_state_cnt = 0;
}
s8 halbb_dig_ofst_by_fa(struct bb_info *bb, u16 fa)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_para_unit *para = &bb_dig->p_cur_dig_unit->dig_op_para;
//enum dig_noisy_level noisy_lv;
s8 ofst = 0;
if (fa < para->fa_th[0]) {
//noisy_lv = DIG_NOISY_LV0;
ofst = -2;
} else if (fa < para->fa_th[1]) {
//noisy_lv = DIG_NOISY_LV1;
ofst = 0;
} else if (fa < para->fa_th[2]) {
//noisy_lv = DIG_NOISY_LV2;
ofst = 2;
} else if (fa < para->fa_th[3]) {
//noisy_lv = DIG_NOISY_LV3;
ofst = 4;
} else {
//noisy_lv = DIG_NOISY_LV_MAX;
ofst = 6;
}
BB_DIG_DBG(bb, DIG_DBG_LV1, "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
para->fa_th[3], para->fa_th[2], para->fa_th[1], para->fa_th[0]);
BB_DIG_DBG(bb, DIG_DBG_LV1, "fa=%d, ofst=%d\n", fa, ofst);
return ofst;
}
u8 halbb_dig_igi_by_ofst(struct bb_info *bb, u8 igi_pre, s8 ofst)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_op_unit *dig_u = dig->p_cur_dig_unit;
#ifdef HALBB_DIG_DAMPING_CHK
struct bb_dig_record_info *dig_rc = &dig->bb_dig_record_i;
#endif
u8 joint_max, joint_min;
u8 dyn_min, dyn_max;
u8 igi_new;
igi_new = (u8)((s8)igi_pre + ofst);
dyn_min = SUBTRACT_TO_0(dig->igi_rssi, 10);
dyn_max = dyn_min + IGI_OFFSET_MAX;
#ifdef HALBB_DIG_DAMPING_CHK
/*@Limit Dyn min by damping*/
if (dig->dig_dl_en &&
dig_rc->damping_lock_en &&
dyn_min < dig_rc->damping_limit_val) {
BB_DBG(bb, DBG_DIG, "[Limit by Damping] Dyn_min=0x%x -> 0x%x\n",
dyn_min, dig_rc->damping_limit_val);
dyn_min = dig_rc->damping_limit_val;
}
#endif
joint_max = MIN_2(dyn_max, dig_u->abs_igi_max);
joint_min = MAX_2(dyn_min, dig_u->abs_igi_min);
if (joint_max >= joint_min) {
/*Check IGI exceed the max/in boundary or not*/
if (igi_new > joint_max)
igi_new = joint_max;
else if (igi_new < joint_min)
igi_new = joint_min;
} else {
igi_new = joint_max;
}
BB_DIG_DBG(bb, DIG_DBG_LV0,
"rssi=%02d, dyn(max,min)=(%d,%d), abs(max,min)=(%d,%d), Joint(max,min)=(%d,%d), igi=%d\n",
dig->igi_rssi,
dyn_max, dyn_min,
dig_u->abs_igi_max, dig_u->abs_igi_min,
joint_max, joint_min,
igi_new);
return igi_new;
}
void halbb_dig_igi_ofst_by_env(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
u8 fa_rssi_ofst_pre = bb_dig_u->fa_rssi_ofst;
switch (bb_dig_u->cur_noisy_lv) {
case DIG_NOISY_LV0:
if (bb_dig_u->fa_rssi_ofst < 2)
bb_dig_u->fa_rssi_ofst = 0;
else
bb_dig_u->fa_rssi_ofst -= 2;
break;
case DIG_NOISY_LV2:
bb_dig_u->fa_rssi_ofst += 2;
break;
case DIG_NOISY_LV3:
bb_dig_u->fa_rssi_ofst += 4;
break;
case DIG_NOISY_LV_MAX:
bb_dig_u->fa_rssi_ofst += 6;
break;
default:
break;
}
if (bb_dig_u->fa_rssi_ofst > IGI_OFFSET_MAX)
bb_dig_u->fa_rssi_ofst = IGI_OFFSET_MAX;
BB_DIG_DBG(bb, DIG_DBG_LV0, "[noisy_lv=%d] ofst: %d -> %d (max: %d)\n",
bb_dig_u->cur_noisy_lv, fa_rssi_ofst_pre, bb_dig_u->fa_rssi_ofst, IGI_OFFSET_MAX);
}
u8 halbb_dig_igi_bound_decision(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
#ifdef HALBB_DIG_DAMPING_CHK
struct bb_dig_record_info *dig_rc = &bb_dig->bb_dig_record_i;
#endif
u8 tmp_max_bound = bb_dig_u->abs_igi_max;
u8 tmp_min_bound = bb_dig_u->abs_igi_min;
u8 igi_new;
if (bb_dig->igi_rssi < 10)
bb_dig_u->dyn_igi_min = 0;
else
bb_dig_u->dyn_igi_min = bb_dig->igi_rssi - 10;
bb_dig_u->dyn_igi_max = bb_dig_u->dyn_igi_min + IGI_OFFSET_MAX;
igi_new = bb_dig_u->dyn_igi_min + bb_dig_u->fa_rssi_ofst;
#ifdef HALBB_DIG_DAMPING_CHK
/*@Limit Dyn min by damping*/
if (bb_dig->dig_dl_en &&
dig_rc->damping_lock_en &&
bb_dig_u->dyn_igi_min < dig_rc->damping_limit_val) {
BB_DBG(bb, DBG_DIG,
"[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
bb_dig_u->dyn_igi_min, dig_rc->damping_limit_val);
bb_dig_u->dyn_igi_min = dig_rc->damping_limit_val;
}
#endif
tmp_max_bound = MIN_2(bb_dig_u->dyn_igi_max, tmp_max_bound);
tmp_min_bound = MAX_2(bb_dig_u->dyn_igi_min, tmp_min_bound);
if (igi_new > tmp_max_bound)
igi_new = tmp_max_bound;
else if (igi_new < tmp_min_bound)
igi_new = tmp_min_bound;
BB_DIG_DBG(bb, DIG_DBG_LV0, "rssi_min=%02d, dyn(max,min)=(%d,%d), abs(max,min)=(%d,%d), igi=%d\n",
bb_dig->igi_rssi,
bb_dig_u->dyn_igi_max, bb_dig_u->dyn_igi_min,
bb_dig_u->abs_igi_max, bb_dig_u->abs_igi_min,
igi_new);
return igi_new;
}
bool halbb_dig_ifs_clm_trig(struct bb_info *bb, u16 mntr_time)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
bool is_trig_success = false;
#ifdef HALBB_ENV_MNTR_SUPPORT
struct env_trig_rpt rpt = {0};
/* trigger env_mntr_rpt */
bb_dig->ccx_para_i.mntr_time = mntr_time - 15;
if (halbb_env_mntr_trigger(bb, &bb_dig->ccx_para_i, &rpt)
& IFS_CLM_SUCCESS) {
BB_DIG_DBG(bb, DIG_DBG_LV2, "ifs_clm trigger ok, timestamp %d, mntr_time %d ms.\n",
rpt.ccx_rpt_stamp, bb_dig->ccx_para_i.mntr_time);
bb_dig->ccx_timestamp = rpt.ccx_rpt_stamp;
bb_dig->ccx_is_triggered = true;
is_trig_success = true;
} else {
BB_DIG_DBG(bb, DIG_DBG_LV1, "ifs_clm trigger fail.\n");
}
#endif
return is_trig_success;
}
bool halbb_dig_ifs_clm_latch(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_op_unit *dig_u = dig->p_cur_dig_unit;
#ifdef HALBB_ENV_MNTR_SUPPORT
struct env_mntr_rpt rpt = {0};
u8 ifs_clm_rpt = halbb_env_mntr_result(bb, &rpt) & IFS_CLM_SUCCESS;
/* get env_mntr_rpt and accumulate */
if (!dig->ccx_is_triggered) {
BB_DIG_DBG(bb, DIG_DBG_LV1, "[Latch Err] DIG not trigger.\n");
return false;
} else {
dig->ccx_is_triggered = false;
}
if (ifs_clm_rpt == 0) {
BB_DIG_DBG(bb, DIG_DBG_LV1, "[Latch Err] FA rpt not valid.\n");
return false;
}
if (dig->ccx_timestamp != rpt.ccx_rpt_stamp) {
BB_DIG_DBG(bb, DIG_DBG_LV1, "[Stamp Err] %d, mine: %d.\n",
rpt.ccx_rpt_stamp, dig->ccx_timestamp);
return false;
}
dig_u->fa_r_acc += (rpt.ifs_clm_ofdm_fa_permil + rpt.ifs_clm_cck_fa_permil);
dig_u->fa_valid_state_cnt++;
BB_DIG_DBG(bb, DIG_DBG_LV2, "[FA] CCK(%d) + OFDM(%d) = ALL(%d)\n",
rpt.ifs_clm_cck_fa_permil, rpt.ifs_clm_ofdm_fa_permil,
rpt.ifs_clm_cck_fa_permil + rpt.ifs_clm_ofdm_fa_permil);
BB_DIG_DBG(bb, DIG_DBG_LV2, "[FA] acc: %d, cnt: %d\n",
dig_u->fa_r_acc, dig_u->fa_valid_state_cnt);
#endif
return true;
}
void halbb_sdagc_follow_pagc_config(struct bb_info *bb, bool set_en)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u32 val = (set_en) ? 1 : 0;
u8 i = 0;
if (bb_dig->p_cur_dig_unit->sdagc_follow_pagc_en == set_en)
return;
bb_dig->p_cur_dig_unit->sdagc_follow_pagc_en = set_en;
halbb_set_reg_cmn(bb, cr->path0_p20_follow_by_pagcugc_en_a,
cr->path0_p20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx);
halbb_set_reg_cmn(bb, cr->path0_s20_follow_by_pagcugc_en_a,
cr->path0_s20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx);
halbb_set_reg_cmn(bb, cr->path1_p20_follow_by_pagcugc_en_a,
cr->path1_p20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx);
halbb_set_reg_cmn(bb, cr->path1_s20_follow_by_pagcugc_en_a,
cr->path1_s20_follow_by_pagcugc_en_a_m, val, bb->bb_phy_idx);
BB_DIG_DBG(bb, DIG_DBG_LV1, "sdagc_follow_pagc=%d\n", val);
}
void halbb_dyn_pd_th_cck(struct bb_info *bb, u8 rssi, bool set_en)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u8 pd_dyn_max = bb_dig->igi_rssi + 5; /* PD_low upper bound */
u8 margin = bb_dig_u->pd_low_th_ofst; /* backoff of CCA ability */
u8 phy = bb->bb_phy_idx == HW_PHY_1 ? 1 : 0;
enum channel_width cbw = bb->hal_com->band[phy].cur_chandef.bw;
BB_DIG_DBG(bb, DIG_DBG_LV1, "%s ======>\n", __func__);
rssi = MIN_2(rssi, pd_dyn_max);
rssi -= MIN_2(rssi, margin);
if(!set_en) {
halbb_set_pd_lower_bound_cck(bb, RSSI_MIN, cbw, bb->bb_phy_idx);
BB_DIG_DBG(bb, DIG_DBG_LV0, "Dynamic CCK PD th dsiabled\n");
} else {
if(!halbb_set_pd_lower_bound_cck(bb, RSSI_MAX - rssi, cbw,
bb->bb_phy_idx))
BB_DIG_DBG(bb, DIG_DBG_LV0, "CCK PD th set warning.\n");
else
BB_DIG_DBG(bb, DIG_DBG_LV1, "dyn_max=%d, backoff=%d, pd_th=%d(-%ddBm)\n",
pd_dyn_max, margin, rssi, RSSI_MAX - rssi);
}
}
void halbb_dyn_pd_th_ofdm(struct bb_info *bb, u8 rssi, bool set_en)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
const struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u8 pd_dyn_max = bb_dig->igi_rssi + 5; /* PD_low upper bound */
u8 margin = bb_dig_u->pd_low_th_ofst; /* backoff of CCA ability */
u8 phy = bb->bb_phy_idx == HW_PHY_1 ? 1 : 0;
enum channel_width cbw = bb->hal_com->band[phy].cur_chandef.bw;
BB_DIG_DBG(bb, DIG_DBG_LV1, "%s ======>\n", __func__);
rssi = MIN_2(rssi, pd_dyn_max);
rssi -= MIN_2(rssi, margin);
if(!set_en) {
halbb_set_pd_lower_bound(bb, RSSI_MIN, cbw, bb->bb_phy_idx);
BB_DIG_DBG(bb, DIG_DBG_LV0, "Dynamic PD th dsiabled\n");
} else {
if(!halbb_set_pd_lower_bound(bb, RSSI_MAX - rssi, cbw,
bb->bb_phy_idx))
BB_DIG_DBG(bb, DIG_DBG_LV0, "PD th set warning.\n");
else
BB_DIG_DBG(bb, DIG_DBG_LV1, "pd_dyn_max=%d, backoff=%d, pd_th_eq_rssi=%d(-%ddBm)\n",
pd_dyn_max, margin, rssi, RSSI_MAX - rssi);
}
}
void halbb_dig_mode_update(struct bb_info *bb, enum dig_op_mode mode)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
switch (mode) {
case DIG_ORIGIN:
case DIG_SIMPLE:
#ifdef HALBB_DIG_TDMA_SUPPORT
case DIG_TDMA:
case DIG_TDMA_ADV:
#endif
bb_dig->dig_mode = mode;
break;
default:
bb_dig->dig_mode = DIG_ORIGIN;
}
BB_DIG_DBG(bb, DIG_DBG_LV0, "Set DIG op mode %d\n", bb_dig->dig_mode);
}
void halbb_dig_gain_para_init(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
s8 *gain_arr = NULL;
u32 tmp_val, i = 0;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_ib_pkpwr,
cr->path0_ib_pkpwr_m, bb->bb_phy_idx);
bb_dig->ib_pkpwr = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 8);
bb_dig->ib_pbk = (u8)halbb_get_reg_cmn(bb, cr->path0_ib_pbk,
cr->path0_ib_pbk_m,
bb->bb_phy_idx);
/*=== [2G Gain Table] =================*/
/*LNA*/
gain_arr = bb_dig->lna_gain_g;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g0_g,
cr->path0_lna_err_g0_g_m, bb->bb_phy_idx);
gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA0_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g1_g,
cr->path0_lna_err_g1_g_m, bb->bb_phy_idx);
gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA1_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g2_g,
cr->path0_lna_err_g2_g_m, bb->bb_phy_idx);
gain_arr[2] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA2_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g3_g,
cr->path0_lna_err_g3_g_m, bb->bb_phy_idx);
gain_arr[3] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA3_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g4_g,
cr->path0_lna_err_g4_g_m, bb->bb_phy_idx);
gain_arr[4] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA4_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g5_g,
cr->path0_lna_err_g5_g_m, bb->bb_phy_idx);
gain_arr[5] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA5_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g6_g,
cr->path0_lna_err_g6_g_m, bb->bb_phy_idx);
gain_arr[6] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA6_GAIN;
/*TIA*/
gain_arr = bb_dig->tia_gain_g;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g0_g,
cr->path0_tia_err_g0_g_m, bb->bb_phy_idx);
gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA0_GAIN_G;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g1_g,
cr->path0_tia_err_g1_g_m, bb->bb_phy_idx);
gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA1_GAIN_G;
/*=== [5G Gain Table] =================*/
/*LNA*/
gain_arr = bb_dig->lna_gain_a;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g0_a,
cr->path0_lna_err_g0_a_m, bb->bb_phy_idx);
gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA0_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g1_a,
cr->path0_lna_err_g1_a_m, bb->bb_phy_idx);
gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA1_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g2_a,
cr->path0_lna_err_g2_a_m, bb->bb_phy_idx);
gain_arr[2] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA2_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g3_a,
cr->path0_lna_err_g3_a_m, bb->bb_phy_idx);
gain_arr[3] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA3_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g4_a,
cr->path0_lna_err_g4_a_m, bb->bb_phy_idx);
gain_arr[4] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA4_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g5_a,
cr->path0_lna_err_g5_a_m, bb->bb_phy_idx);
gain_arr[5] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA5_GAIN;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_lna_err_g6_a,
cr->path0_lna_err_g6_a_m, bb->bb_phy_idx);
gain_arr[6] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + LNA6_GAIN;
/*TIA*/
gain_arr = bb_dig->tia_gain_a;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g0_a,
cr->path0_tia_err_g0_a_m, bb->bb_phy_idx);
gain_arr[0] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA0_GAIN_A;
tmp_val = halbb_get_reg_cmn(bb, cr->path0_tia_err_g1_a,
cr->path0_tia_err_g1_a_m, bb->bb_phy_idx);
gain_arr[1] = (s8)halbb_cnvrt_2_sign(tmp_val >> 2, 4) + TIA1_GAIN_A;
BB_DIG_DBG(bb, DIG_DBG_LV0, "ib_pkpwr=%d, ib_pbk=%d\n",
bb_dig->ib_pkpwr, bb_dig->ib_pbk);
for (i = 0; i < BB_LNA_SIZE; i++)
BB_DIG_DBG(bb, DIG_DBG_LV0, "lna_gain_g[%d]=%d\n",
i, bb_dig->lna_gain_g[i]);
for (i = 0; i < BB_TIA_SIZE; i++)
BB_DIG_DBG(bb, DIG_DBG_LV0, "tia_gain_g[%d]=%d\n",
i, bb_dig->tia_gain_g[i]);
for (i = 0; i < BB_LNA_SIZE; i++)
BB_DIG_DBG(bb, DIG_DBG_LV0, "lna_gain_a[%d]=%d\n",
i, bb_dig->lna_gain_a[i]);
for (i = 0; i < BB_TIA_SIZE; i++)
BB_DIG_DBG(bb, DIG_DBG_LV0, "tia_gain_a[%d]=%d\n",
i, bb_dig->tia_gain_a[i]);
/*lna initial gain index*/
bb_dig->max_gaincode.lna_idx = halbb_get_lna_idx(bb, RF_PATH_A);
bb_dig->max_gaincode.tia_idx = halbb_get_tia_idx(bb, RF_PATH_A);
bb_dig->max_gaincode.rxb_idx = halbb_get_rxb_idx(bb, RF_PATH_A);
BB_DIG_DBG(bb, DIG_DBG_LV0, "Read max gaincode = (%d,%d,%2d)\n",
bb_dig->max_gaincode.lna_idx, bb_dig->max_gaincode.tia_idx,
bb_dig->max_gaincode.rxb_idx);
}
/* fa_cnt 2000/4000/5000/8000 */
static const u16 fa_th_no_link[FA_TH_NUM] = {196, 352, 440, 528};
static const u16 fa_th_linked[FA_TH_NUM] = {4, 8, 12, 16};
void halbb_dig_para_update(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
struct bb_dig_op_para_unit *para_dst;
BB_DIG_DBG(bb, DIG_DBG_LV1, "%s ======>\n", __func__);
/* IGI and PT_low enable control */
para_dst = &bb_dig->dig_state_h_i.dig_op_para;
para_dst->dyn_pd_th_en = true;
#ifdef BB_8852A_2_SUPPORT
if (bb->ic_type == BB_RTL8852A)
halbb_dig_agc_update_8852a(bb, para_dst);
#endif
/* fa th update */
if (!bb->bb_link_i.is_linked)
halbb_mem_cpy(bb, ¶_dst->fa_th, fa_th_no_link,
sizeof(u16) * FA_TH_NUM);
else
halbb_mem_cpy(bb, ¶_dst->fa_th, fa_th_linked,
sizeof(u16) * FA_TH_NUM);
BB_DIG_DBG(bb, DIG_DBG_LV1, "is_linked=%d, fa_th[3:0] = %d,%d,%d,%d\n",
bb->bb_link_i.is_linked,
para_dst->fa_th[3], para_dst->fa_th[2], para_dst->fa_th[1],
para_dst->fa_th[0]);
#ifdef HALBB_DIG_TDMA_SUPPORT
para_dst = &bb_dig->dig_state_l_i.dig_op_para;
halbb_mem_cpy(bb, para_dst, &bb_dig->dig_state_h_i.dig_op_para,
sizeof(struct bb_dig_op_para_unit));
#endif
}
void halbb_dig_fa_info_update(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
/* average from env_mntr_rpt */
bb_dig_u->fa_r_avg = HALBB_DIV(bb_dig_u->fa_r_acc, bb_dig_u->fa_valid_state_cnt);
bb_dig_u->fa_r_acc = 0;
}
void halbb_dig_op_unit_para_reset_h(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *unit_cur = &bb_dig->dig_state_h_i;
u8 i = 0;
unit_cur->cur_gaincode = bb_dig->max_gaincode;
unit_cur->force_gaincode = bb_dig->max_gaincode;
unit_cur->abs_igi_max = IGI_MAX_PERFORMANCE_MODE;
unit_cur->abs_igi_min = 0xc;
unit_cur->pd_low_th_ofst = 16;
#ifdef HALBB_DIG_TDMA_SUPPORT
unit_cur->state_identifier = DIG_TDMA_HIGH;
#endif
}
#ifdef HALBB_DIG_TDMA_SUPPORT
void halbb_dig_op_unit_para_reset_l(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *unit_cur = &bb_dig->dig_state_l_i;
u8 i = 0;
unit_cur->cur_gaincode = bb_dig->max_gaincode;
unit_cur->force_gaincode = bb_dig->max_gaincode;
unit_cur->abs_igi_max = 0x26;
unit_cur->abs_igi_min = 0xc;
unit_cur->pd_low_th_ofst = 16;
unit_cur->state_identifier = DIG_TDMA_LOW;
}
#endif
void halbb_dig_ifs_clm_para_init(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
#ifdef HALBB_ENV_MNTR_SUPPORT
struct ccx_para_info *para = &dig->ccx_para_i;
para->rac_lv = RAC_LV_2;
para->mntr_time = DIG_CCX_WD_TRIGTIME;
para->clm_app = CLM_DIG;
para->clm_input_opt = CLM_CCA_S80_S40_S20;
para->nhm_app = NHM_DIG;
para->nhm_incld_cca = NHM_EXCLUDE_CCA;
para->fahm_app = FAHM_DIG;
para->fahm_numer_opt = FAHM_INCLU_FA;
para->fahm_denom_opt = FAHM_INCLU_CRC_ERR;
para->ifs_clm_app = IFS_CLM_DIG;
para->edcca_clm_app = EDCCA_CLM_DIG;
para->ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0;
#endif
dig->ccx_is_triggered = false;
}
void halbb_dig_para_reset(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
bb_dig->pre_dig_mode = bb_dig->dig_mode;
bb_dig->p_cur_dig_unit = &bb_dig->dig_state_h_i;
bb_dig->need_update = false;
halbb_dig_op_unit_para_reset_h(bb); /* dig_op_unit para reset */
#ifdef HALBB_DIG_TDMA_SUPPORT
halbb_dig_op_unit_para_reset_l(bb); /* dig_op_unit para reset */
bb_dig->gaincode_update_en = false;
bb_dig->tdma_passed_time_acc = 0;
bb_dig->tdma_timestamp_cur = 0;
bb_dig->tdma_timestamp_pre = bb_dig->tdma_timestamp_cur;
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
bb_dig->ccx_timestamp = 0;
bb_dig->ccx_is_triggered = false;
#endif
}
void halbb_dig_reset(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s]=========>\n", __func__);
halbb_mem_set(bb, &bb_dig->dig_fa_i, 0, sizeof(struct bb_dig_fa_info));
halbb_dig_para_reset(bb);
#ifdef BB_8852A_2_SUPPORT
halbb_dig_set_igi_cr_8852a(bb, bb_dig->max_gaincode);
#endif
halbb_dyn_pd_th_ofdm(bb, IGI_NOLINK, false);
halbb_dyn_pd_th_cck(bb, IGI_NOLINK, false);
halbb_sdagc_follow_pagc_config(bb, false);
}
void halbb_dig_init(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
u8 igi_new;
if(phl_is_mp_mode(bb->phl_com))
return;
BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s]=========>\n", __func__);
/* DIG sub-DM configurations */
halbb_dig_mode_update(bb, DIG_ORIGIN);
bb_dig->igi_pause_cnt = 0;
bb_dig->le_igi_ofst = 10;
bb_dig->dbg_lv = DIG_DBG_LV2;
bb_dig->dig_state_h_i.state_num_lmt = 3;
bb_dig->dig_state_h_i.sdagc_follow_pagc_en = false;
#ifdef HALBB_DIG_TDMA_SUPPORT
bb_dig->dig_state_l_i.state_num_lmt = 1;
bb_dig->dig_state_l_i.sdagc_follow_pagc_en = false;
bb_dig->dig_timer_i.cb_time = 50;
#endif
halbb_dig_ifs_clm_para_init(bb);
halbb_dig_gain_para_init(bb);
halbb_dig_reset(bb);
bb_dig->dig_state_h_i.igi_fa_rssi = 1; /*init state*/
halbb_dig_para_update(bb);
#ifdef HALBB_DIG_DAMPING_CHK
halbb_dig_damping_chk_init(bb);
#endif
igi_new = halbb_dig_igi_by_ofst(bb, IGI_NOLINK, 0);
halbb_dig_cfg_bbcr(bb, igi_new);
}
void halbb_dig_deinit(struct bb_info *bb)
{
#ifdef HALBB_DIG_TDMA_SUPPORT
BB_DBG(bb, DBG_INIT, "halbb_dig_deinit");
#endif
}
bool halbb_dig_abort(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
/* support_ability */
if (!(bb->support_ability & BB_DIG)) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======> DISABLED\n", __func__);
return true;
}
if (bb->pause_ability & BB_DIG) {
dig->igi_pause_cnt++;
BB_DIG_DBG(bb, DIG_DBG_LV0, "Return: Pause DIG in LV=%d, cnt=%d\n",
bb->pause_lv_table.lv_dig,
dig->igi_pause_cnt);
return true;
}
if (dig->igi_pause_cnt) {
dig->igi_pause_cnt = 0;
BB_DIG_DBG(bb, DIG_DBG_LV0, "Skip 1 time after pause DIG\n");
return true;
}
return false;
}
void halbb_dig_lps(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
s16 final_rssi = bb_dig->igi_rssi + bb_dig->le_igi_ofst;
BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======>\n", __func__);
final_rssi = MIN_2(final_rssi, RSSI_MAX);
final_rssi = MAX_2(final_rssi, RSSI_MIN);
BB_DIG_DBG(bb, DIG_DBG_LV0, "rssi=%03d, le_ofst=(%03d), final_rssi=%d\n",
bb_dig->igi_rssi, bb_dig->le_igi_ofst, (s8)final_rssi);
#ifdef BB_8852A_2_SUPPORT
/* IGI decision */
if (halbb_dig_gaincode_update_en_8852a(bb))
halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode);
#endif
/* Dynamic sync-dagc follow pagc*/
halbb_sdagc_follow_pagc_config(bb, false);
}
void halbb_dig_cfg_bbcr(struct bb_info *bb, u8 igi_new)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = dig->p_cur_dig_unit;
struct bb_dig_op_unit *dig_u = &dig->dig_state_h_i;
struct bb_dig_op_para_unit *para = &dig_u->dig_op_para;
if (igi_new == dig_u->igi_fa_rssi) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "[IGI][hold_cnt:%d] %d\n", dig->dig_hold_cnt, igi_new);
dig->dig_hold_cnt++;
return;
} else {
BB_DIG_DBG(bb, DIG_DBG_LV0, "[IGI] %d -> %d\n", dig_u->igi_fa_rssi, igi_new);
dig->dig_hold_cnt = 0;
}
dig_u->igi_fa_rssi = igi_new;
#ifdef BB_8852A_2_SUPPORT
/* IGI decision */
if (halbb_dig_gaincode_update_en_8852a(bb))
halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode);
#endif
/* Dynamic PD lower bound */
halbb_dyn_pd_th_ofdm(bb, igi_new, para->dyn_pd_th_en);
/* Dynamic CCK PD TH */
halbb_dyn_pd_th_cck(bb, igi_new, para->dyn_pd_th_en);
/* Dynamic sync-dagc follow pagc*/
if (para->dyn_pd_th_en && igi_new > dig->igi_rssi)
halbb_sdagc_follow_pagc_config(bb, true);
else
halbb_sdagc_follow_pagc_config(bb, false);
}
void halbb_dig_new_entry_connect(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
u8 igi_new;
u8 rssi_min_new = halbb_get_rssi_min(bb);
BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======>\n", __func__);
if (rssi_min_new == 0)
return;
BB_DIG_DBG(bb, DIG_DBG_LV0, "rssi_min_new=%d\n", rssi_min_new);
/* Update igi_rssi */
dig->igi_rssi = rssi_min_new >> 1;
igi_new = halbb_dig_igi_by_ofst(bb, dig->igi_rssi, 0);
halbb_dig_cfg_bbcr(bb, igi_new);
/*Update EDCCA threshold*/
halbb_edcca_thre_calc(bb);
}
void halbb_dig(struct bb_info *bb)
{
struct bb_dig_info *dig = &bb->bb_dig_i;
struct bb_dig_op_unit *dig_u = &dig->dig_state_h_i;
struct bb_dig_op_para_unit *para = &dig_u->dig_op_para;
struct bb_link_info *bb_link = &bb->bb_link_i;
u16 fa_avg;
u8 igi_new, igi_pre = dig_u->igi_fa_rssi;
s8 ofst;
BB_DIG_DBG(bb, DIG_DBG_LV0, "%s ======>\n", __func__);
dig->need_update |= (bb_link->first_connect | bb_link->first_disconnect);
if (halbb_dig_abort(bb))
return;
/* Update igi_rssi */
dig->igi_rssi = (bb_link->is_linked) ? (bb->bb_ch_i.rssi_min >> 1) : IGI_NOLINK;
BB_DIG_DBG(bb, DIG_DBG_LV0, "link=%d, rssi=%d\n", bb_link->is_linked, dig->igi_rssi);
if (dig->need_update) {
halbb_dig_para_update(bb);
#ifdef HALBB_DIG_DAMPING_CHK
halbb_dig_recorder_reset(bb);
#endif
BB_DIG_DBG(bb, DIG_DBG_LV0, "Connect/Disconnect\n");
igi_new = halbb_dig_igi_by_ofst(bb, dig->igi_rssi, 0);
halbb_dig_cfg_bbcr(bb, igi_new);
dig->need_update = false;
return;
}
#ifdef HALBB_DIG_TDMA_SUPPORT
if (dig->dig_mode == DIG_TDMA && bb_link->is_linked) {
halbb_dig_timercheck_watchdog(bb);
return;
}
dig->p_cur_dig_unit = &dig->dig_state_h_i;
#endif
if (dig->dig_mode == DIG_SIMPLE) {
halbb_dig_lps(bb);
return;
}
/* FA info handling */
if (!halbb_dig_ifs_clm_latch(bb)) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "IFS CLM Get Rpt Fail\n");
goto DIG_END;
}
fa_avg = HALBB_DIV(dig_u->fa_r_acc, dig_u->fa_valid_state_cnt);
dig_u->fa_r_acc = 0;
dig_u->fa_valid_state_cnt = 0;
#ifdef HALBB_DIG_DAMPING_CHK
/*Record IGI History*/
halbb_dig_recorder(bb, igi_pre, fa_avg);
/*DIG Damping Check*/
halbb_dig_damping_chk(bb);
#endif
ofst = halbb_dig_ofst_by_fa(bb, fa_avg);
igi_new = halbb_dig_igi_by_ofst(bb, igi_pre, ofst);
halbb_dig_cfg_bbcr(bb, igi_new);
DIG_END:
if (!halbb_dig_ifs_clm_trig(bb, DIG_CCX_WD_TRIGTIME))
BB_DIG_DBG(bb, DIG_DBG_LV0, "IFS CLM Trig Fail\n");
}
#ifdef HALBB_DIG_TDMA_SUPPORT
void halbb_tdma_dig(struct bb_info *bb) {
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
bool ifs_clm_op_status = false;
bool igi_update_en_h = false, igi_update_en_l = false;
bb_dig->tdma_timestamp_cur++;
bb_dig->tdma_passed_time_acc += (u16)bb_dig->dig_timer_i.cb_time;
BB_DIG_DBG(bb, DIG_DBG_LV2, "[IN]state_cnt=%d, state_lmt=%d\n",
bb_dig_u->passed_state_cnt, bb_dig_u->state_num_lmt);
/* FA info handling */
ifs_clm_op_status = halbb_dig_ifs_clm_latch(bb);
/* Two seconds periodic procedure */
if (bb_dig->tdma_passed_time_acc >= WACHDOG_PERIOD_IN_MS) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "Two seconds reached.\n");
BB_DIG_DBG(bb, DIG_DBG_LV0, "[TDMA-H]============>\n");
bb_dig->p_cur_dig_unit = &bb_dig->dig_state_h_i;
/* FA info handling */
halbb_dig_fa_info_update(bb);
/* Noisy level decision */
halbb_dig_noisy_lv_decision(bb);
halbb_dig_igi_ofst_by_env(bb);
/* IGI and boundary decision */
bb_dig_u->igi_fa_rssi = halbb_dig_igi_bound_decision(bb);
#ifdef BB_8852A_2_SUPPORT
/* IGI decision */
igi_update_en_h = halbb_dig_gaincode_update_en_8852a(bb);
#endif
BB_DIG_DBG(bb, DIG_DBG_LV0, "[TDMA-L]============>\n");
bb_dig->p_cur_dig_unit = &bb_dig->dig_state_l_i;
/* FA info handling */
halbb_dig_fa_info_update(bb);
/* Noisy level decision */
halbb_dig_noisy_lv_decision(bb);
halbb_dig_igi_ofst_by_env(bb);
/* IGI and boundary decision */
bb_dig_u->igi_fa_rssi = halbb_dig_igi_bound_decision(bb);
#ifdef BB_8852A_2_SUPPORT
/* IGI decision */
igi_update_en_l = halbb_dig_gaincode_update_en_8852a(bb);
#endif
bb_dig->gaincode_update_en = igi_update_en_h | igi_update_en_l;
bb_dig->p_cur_dig_unit = bb_dig_u;
bb_dig->tdma_passed_time_acc = 0;
}
/* TDMA state transition */
if (++bb_dig_u->passed_state_cnt >= bb_dig_u->state_num_lmt) {
BB_DIG_DBG(bb, DIG_DBG_LV2, "[OUT]state_cnt=%d, state_lmt=%d\n",
bb_dig_u->passed_state_cnt,
bb_dig_u->state_num_lmt);
bb_dig_u->passed_state_cnt = 0;
switch (bb_dig_u->state_identifier) {
case DIG_TDMA_LOW:
bb_dig->p_cur_dig_unit = &bb_dig->dig_state_h_i;
BB_DIG_DBG(bb, DIG_DBG_LV1, "[TDMA-L]->[TDMA-H].\n");
break;
case DIG_TDMA_HIGH:
bb_dig->p_cur_dig_unit = &bb_dig->dig_state_l_i;
BB_DIG_DBG(bb, DIG_DBG_LV1, "[TDMA-H]->[TDMA-L].\n");
break;
default:
break;
}
bb_dig_u = bb_dig->p_cur_dig_unit;
#ifdef BB_8852A_2_SUPPORT
/* To set lna, tia, rxbb index */
if (bb_dig->gaincode_update_en)
halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->cur_gaincode);
#endif
/* Dynamic PD lower bound */
halbb_dyn_pd_th_ofdm(bb, bb_dig_u->igi_fa_rssi,
bb_dig_u->dig_op_para.dyn_pd_th_en);
/* Dynamic CCK PD TH */
halbb_dyn_pd_th_cck(bb, bb_dig_u->igi_fa_rssi,
bb_dig_u->dig_op_para.dyn_pd_th_en);
/* Dynamic sync-dagc follow pagc*/
if (bb_dig_u->dig_op_para.dyn_pd_th_en &&
(bb_dig_u->igi_fa_rssi > bb_dig->igi_rssi))
halbb_sdagc_follow_pagc_config(bb, true);
else
halbb_sdagc_follow_pagc_config(bb, false);
}
ifs_clm_op_status = halbb_dig_ifs_clm_trig(bb, (u16)bb_dig->dig_timer_i.cb_time);
}
void halbb_dig_timercheck_watchdog(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
if (bb_dig->tdma_timestamp_cur == bb_dig->tdma_timestamp_pre) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "DIG TDMA timer check FAIL. Restart.\n");
halbb_dig_reset(bb);
halbb_cfg_timers(bb, BB_SET_TIMER, &bb->bb_dig_i.dig_timer_i);
}
bb_dig->tdma_timestamp_pre = bb_dig->tdma_timestamp_cur;
}
void halbb_tdmadig_io_en(struct bb_info *bb)
{
struct bb_link_info *bb_link = &bb->bb_link_i;
if (halbb_dig_abort(bb)) {
return;
}
if (!bb_link->is_linked) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "is_linked=%d, one_entry_only=%d\n",
bb_link->is_linked, bb_link->is_one_entry_only);
return;
}
if ((bb->bb_dig_i.dig_mode != DIG_TDMA) &&
(bb->bb_dig_i.dig_mode != DIG_TDMA_ADV))
return;
halbb_tdma_dig(bb);
halbb_cfg_timers(bb, BB_SET_TIMER, &bb->bb_dig_i.dig_timer_i);
}
void halbb_tdmadig_callback(void *context)
{
struct bb_info *bb = (struct bb_info *)context;
struct halbb_timer_info *timer = &bb->bb_dig_i.dig_timer_i;
BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s]===>\n", __func__);
timer->timer_state = BB_TIMER_IDLE;
if (bb->phl_com->hci_type == RTW_HCI_PCIE)
halbb_tdmadig_io_en(bb);
else
rtw_hal_cmd_notify(bb->phl_com, MSG_EVT_NOTIFY_BB, (void *)(&timer->event_idx), bb->bb_phy_idx);
}
void halbb_dig_timer_init(struct bb_info *bb)
{
struct halbb_timer_info *timer = &bb->bb_dig_i.dig_timer_i;
BB_DBG(bb, DBG_DIG, "[%s]\n", __func__);
timer->event_idx = BB_EVENT_TIMER_DIG;
timer->timer_state = BB_TIMER_IDLE;
halbb_init_timer(bb, &timer->timer_list, halbb_tdmadig_callback, bb, "halbb_dig_timer");
}
#endif /*#ifdef HALBB_DIG_TDMA_SUPPORT*/
void halbb_set_dig_pause_val(struct bb_info *bb, u32 *buf, u8 val_len)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *dig_u = bb_dig->p_cur_dig_unit;
struct agc_gaincode_set gaincode = bb_dig->max_gaincode;
u8 phy = bb->bb_phy_idx == HW_PHY_1 ? 1 : 0;
enum channel_width cbw = bb->hal_com->band[phy].cur_chandef.bw;
u8 target_pwr, margin = dig_u->pd_low_th_ofst;
if (val_len != DIG_PAUSE_INFO_SIZE) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "[Error][DIG]Need val_len=%d\n",
DIG_PAUSE_INFO_SIZE);
return;
}
BB_DIG_DBG(bb, DIG_DBG_LV0, "[%s] Pd=-%d dB\n", __func__, buf[0]);
#ifdef BB_8852A_2_SUPPORT
/* write igi or keep max gaincode */
if (bb->ic_type == BB_RTL8852A) {
if ((buf[1] == PAUSE_OFDM_CCK) && (bb->hal_com->cv < CCV)) {
BB_DIG_DBG(bb, DIG_DBG_LV0, "[52A] igi_en=1\n");
halbb_gaincode_by_rssi_8852a(bb, &gaincode, RSSI_MAX - (u8)buf[0]);
}
halbb_dig_set_igi_cr_8852a(bb, gaincode);
}
#endif
/* write pd lower bound anyway */
target_pwr = MIN_2((u8)buf[0] + margin, RSSI_MAX);
halbb_set_pd_lower_bound(bb, target_pwr, cbw, bb->bb_phy_idx);
if (buf[1] == PAUSE_OFDM)
target_pwr = 0;
halbb_set_pd_lower_bound_cck(bb, target_pwr, cbw, bb->bb_phy_idx);
}
void* halbb_get_dig_fa_statistic(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
return &bb_dig->dig_fa_i;
}
void halbb_dig_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = &bb_dig->dig_state_h_i;
struct agc_gaincode_set set_tmp;
u32 var[10] = {0};
u8 i = 0;
if (_os_strcmp(input[1], "-h") == 0) {
#ifdef HALBB_DIG_TDMA_SUPPORT
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"DIG-H state\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{0} {dig op mode = %d(0:DIG,1:TDMA,2:A-TDMA,3:low IO)}\n",
bb_dig->dig_mode);
#else
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{0} {dig op mode = %d(0:DIG,3:low IO)}\n",
bb_dig->dig_mode);
#endif
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{1} {fix_lna = %d} {fix_tia = %d} {fix_rxb = %d}\n",
bb_dig_u->force_gaincode.lna_idx,
bb_dig_u->force_gaincode.tia_idx,
bb_dig_u->force_gaincode.rxb_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{2: get current IGI} {path(0/1)}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{3: show rssi threshold of IGI}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{4: modify rssi threshold} {TH idx(0-4)} {value}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{5: show fa ratio vs. noisy level.}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{6: modify fa ratio threshold} {TH idx(0-3)} {value}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{7: dyn PD low bound en = %d} {0:disable, 1:enable}\n",
bb_dig_u->dig_op_para.dyn_pd_th_en);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{8: dyn PD low bound backoff = %d} {value}\n",
bb_dig_u->pd_low_th_ofst);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{9: reset rssi, fa_ratio TH}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{10: show AGC table}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{11: Update gain parameters}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{12: simple mode IGI offset = (%d)} {0:-, 1:+} {val}\n",
bb_dig->le_igi_ofst);
#ifdef HALBB_DIG_TDMA_SUPPORT
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{13: tdma timer = %d ms} {val(ms)}\n",
bb_dig->dig_timer_i.cb_time);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{14: state limit (L,H) = (%d,%d)} {0:L,1:H} {state num}\n",
bb_dig->dig_state_l_i.state_num_lmt,
bb_dig->dig_state_h_i.state_num_lmt);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{15} {0:L,1:H} {fix_lna = %d} {fix_tia = %d} {fix_rxb = %d}\n",
bb_dig_u->force_gaincode.lna_idx,
bb_dig_u->force_gaincode.tia_idx,
bb_dig_u->force_gaincode.rxb_idx);
#endif
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{20: dbg level = %d} {0/1/2}\n",
bb_dig->dbg_lv);
#ifdef HALBB_DIG_DAMPING_CHK
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"damping en {val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"damping th {s(8,1)}\n");
#endif
return;
}
#ifdef HALBB_DIG_DAMPING_CHK
if (_os_strcmp(input[1], "damping") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[0]);
if (_os_strcmp(input[2], "en") == 0) {
bb_dig->dig_dl_en = (bool)var[0];
if (!bb_dig->dig_dl_en)
halbb_dig_recorder_reset(bb);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dig_dl_en = %d\n", bb_dig->dig_dl_en);
} else if (_os_strcmp(input[2], "th") == 0) {
bb_dig->rls_rssi_diff_th = (u8)var[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"rls_rssi_diff_th = %d.%d\n",
var[0] >> 1, (var[0] & 1) * 5);
}
return;
}
#endif
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if (var[0] == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
halbb_dig_mode_update(bb, (enum dig_op_mode)var[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set DIG op mode = %d\n", bb_dig->dig_mode);
} else if (var[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]);
bb_dig_u->force_gaincode.lna_idx = (u8)var[1];
bb_dig_u->force_gaincode.tia_idx = (u8)var[2];
bb_dig_u->force_gaincode.rxb_idx = (u8)var[3];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"IGI: fix(lna,tia,rxb)=(%d,%d,%d)\n",
bb_dig_u->force_gaincode.lna_idx,
bb_dig_u->force_gaincode.tia_idx,
bb_dig_u->force_gaincode.rxb_idx);
#ifdef BB_8852A_2_SUPPORT
halbb_dig_set_igi_cr_8852a(bb, bb_dig_u->force_gaincode);
#endif
} else if (var[0] == 2) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"current(lna,tia,rxb)=((%d,%d,%d))\n",
halbb_get_lna_idx(bb,(enum rf_path)var[1]),
halbb_get_tia_idx(bb,(enum rf_path)var[1]),
halbb_get_rxb_idx(bb,(enum rf_path)var[1]));
} else if (var[0] == 3) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"rssi TH: -----%03d-----%03d-----%03d-----%03d-----%03d-----\n",
bb_dig_u->dig_op_para.igi_rssi_th[0],
bb_dig_u->dig_op_para.igi_rssi_th[1],
bb_dig_u->dig_op_para.igi_rssi_th[2],
bb_dig_u->dig_op_para.igi_rssi_th[3],
bb_dig_u->dig_op_para.igi_rssi_th[4]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"lna idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n",
6,5,4,3,2,1);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tia idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n",
1,0,0,0,0,0);
} else if (var[0] == 4) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
if (var[1] < 5) {
bb_dig_u->dig_op_para.igi_rssi_th[var[1]] = (u8)var[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set rssi_TH[%d]=%d\n", var[1],
bb_dig_u->dig_op_para.igi_rssi_th[var[1]]);
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"rssi TH: -----%03d-----%03d-----%03d-----%03d-----%03d-----\n",
bb_dig_u->dig_op_para.igi_rssi_th[0],
bb_dig_u->dig_op_para.igi_rssi_th[1],
bb_dig_u->dig_op_para.igi_rssi_th[2],
bb_dig_u->dig_op_para.igi_rssi_th[3],
bb_dig_u->dig_op_para.igi_rssi_th[4]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"lna idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n",
6,5,4,3,2,1);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tia idx: --%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--|||--%1d--\n",
1,0,0,0,0,0);
} else if (var[0] == 5) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"fa ratio TH: -----%03d-----%03d-----%03d-----%03d-----\n",
bb_dig_u->dig_op_para.fa_th[0],
bb_dig_u->dig_op_para.fa_th[1],
bb_dig_u->dig_op_para.fa_th[2],
bb_dig_u->dig_op_para.fa_th[3]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"noisy level: --%1d--|||--%1d--|||--%1d--|||--%1d--|||-%s-\n",
0,1,2,3,"MAX");
} else if (var[0] == 6) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
if (var[1] < 4) {
bb_dig_u->dig_op_para.fa_th[var[1]] = (u16)var[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set FA ratio TH[%d]=%d\n", var[1],
bb_dig_u->dig_op_para.fa_th[var[1]]);
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"fa ratio TH: -----%03d-----%03d-----%03d-----%03d-----\n",
bb_dig_u->dig_op_para.fa_th[0],
bb_dig_u->dig_op_para.fa_th[1],
bb_dig_u->dig_op_para.fa_th[2],
bb_dig_u->dig_op_para.fa_th[3]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"noisy level: --%1d--|||--%1d--|||--%1d--|||--%1d--|||-%s-\n",
0,1,2,3,"MAX");
} else if (var[0] == 7) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dig_u->dig_op_para.dyn_pd_th_en = (bool)var[1];
if (bb_dig_u->dig_op_para.dyn_pd_th_en)
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Enabled dyn PD low bound\n");
else
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Disabled dyn PD low bound\n");
} else if (var[0] == 8) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dig_u->pd_low_th_ofst = (u8)var[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set dyn PD low bound backoff=%d\n",
bb_dig_u->pd_low_th_ofst);
} else if (var[0] == 9) {
halbb_dig_reset(bb);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Reset state machine parameters\n");
#ifdef BB_8852A_2_SUPPORT
} else if (var[0] == 10) {
for (i = RSSI_MIN; i <= RSSI_MAX; i++)
halbb_gaincode_by_rssi_8852a(bb, &set_tmp, i);
#endif
} else if (var[0] == 11) {
halbb_dig_gain_para_init(bb);
} else if (var[0] == 12) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
if (var[1] == 0)
bb_dig->le_igi_ofst = -(s8)var[2];
else if (var[1] == 1)
bb_dig->le_igi_ofst = (s8)var[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"simple mode IGI offset set to (%d)\n",
bb_dig->le_igi_ofst);
#ifdef HALBB_DIG_TDMA_SUPPORT
} else if (var[0] == 13) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_dig->dig_timer_i.cb_time = (u16)var[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tdma timer set to %d ms\n",
bb_dig->dig_timer_i.cb_time);
} else if (var[0] == 14) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
if (var[1] == 0)
bb_dig_u = &bb_dig->dig_state_l_i;
else if (var[1] == 1)
bb_dig_u = &bb_dig->dig_state_h_i;
bb_dig_u->state_num_lmt = (u8)var[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set TDMA-%d state limit to %d\n",
bb_dig_u->state_identifier,
bb_dig_u->state_num_lmt);
} else if (var[0] == 15) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &var[4]);
HALBB_SCAN(input[6], DCMD_DECIMAL, &var[5]);
if (var[1] == 0)
bb_dig_u = &bb_dig->dig_state_l_i;
else if (var[1] == 1)
bb_dig_u = &bb_dig->dig_state_h_i;
bb_dig_u->force_gaincode.lna_idx = (u8)var[2];
bb_dig_u->force_gaincode.tia_idx = (u8)var[3];
bb_dig_u->force_gaincode.rxb_idx = (u8)var[4];
bb_dig_u = &bb_dig->dig_state_l_i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[TDMA-L]IGI: fix(lna,tia,rxb)=(%d,%d,%d)\n",
bb_dig_u->force_gaincode.lna_idx,
bb_dig_u->force_gaincode.tia_idx,
bb_dig_u->force_gaincode.rxb_idx);
bb_dig_u = &bb_dig->dig_state_h_i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[TDMA-H]IGI: fix(lna,tia,rxb)=(%d,%d,%d)\n",
bb_dig_u->force_gaincode.lna_idx,
bb_dig_u->force_gaincode.tia_idx,
bb_dig_u->force_gaincode.rxb_idx);
#endif
} else if (var[0] == 20) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
if ((enum dig_dbg_level)var[1] <= DIG_DBG_LV2)
bb_dig->dbg_lv = (enum dig_dbg_level)var[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dbg level set to lv%d\n",
bb_dig->dbg_lv);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
}
}
void halbb_cr_cfg_dig_init(struct bb_info *bb)
{
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_52AA:
/*cr->path0_ib_pbk = PATH0_R_IB_PBK_52AA;
*cr->path0_ib_pbk_m = PATH0_R_IB_PBK_52AA_M;
*cr->path0_ib_pkpwr = PATH0_R_IB_PKPW_52AA;
*cr->path0_ib_pkpwr_m = PATH0_R_IB_PKPW_52AA_M;
*cr->path1_ib_pbk = PATH1_R_IB_PBK_52AA;
*cr->path1_ib_pbk_m = PATH1_R_IB_PBK_52AA_M;
*cr->path1_ib_pkpwr = PATH1_R_IB_PKPW_52AA;
*cr->path1_ib_pkpwr_m = PATH1_R_IB_PKPW_52AA_M;
*/
cr->path0_lna_init_idx = PATH0_R_LNA_INIT_IDX_52AA;
cr->path0_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_52AA_M;
cr->path1_lna_init_idx = PATH0_R_LNA_INIT_IDX_52AA;
cr->path1_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_52AA_M;
cr->path0_tia_init_idx = PATH0_R_TIA_INIT_IDX_52AA;
cr->path0_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_52AA_M;
cr->path1_tia_init_idx = PATH0_R_TIA_INIT_IDX_52AA;
cr->path1_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_52AA_M;
cr->path0_rxb_init_idx = PATH0_R_RXB_INIT_IDX_52AA;
cr->path0_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_52AA_M;
cr->path1_rxb_init_idx = PATH0_R_RXB_INIT_IDX_52AA;
cr->path1_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_52AA_M;
/*cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_52AA;
*cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_52AA_M;
*cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_52AA;
*cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_52AA_M;
*cr->path0_p20_follow_by_pagcugc_en_a = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA;
*cr->path0_p20_follow_by_pagcugc_en_a_m = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M;
*cr->path0_s20_follow_by_pagcugc_en_a = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA;
*cr->path0_s20_follow_by_pagcugc_en_a_m = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M;
*cr->path1_p20_follow_by_pagcugc_en_a = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA;
*cr->path1_p20_follow_by_pagcugc_en_a_m = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M;
*cr->path1_s20_follow_by_pagcugc_en_a = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA;
*cr->path1_s20_follow_by_pagcugc_en_a_m = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_52AA_M;
*cr->path0_lna_err_g0_a = PATH0_R_LNA_ERR_G0_A_52AA;
*cr->path0_lna_err_g0_a_m = PATH0_R_LNA_ERR_G0_A_52AA_M;
*cr->path0_lna_err_g0_g = PATH0_R_LNA_ERR_G0_G_52AA;
*cr->path0_lna_err_g0_g_m = PATH0_R_LNA_ERR_G0_G_52AA_M;
*cr->path0_lna_err_g1_a = PATH0_R_LNA_ERR_G1_A_52AA;
*cr->path0_lna_err_g1_a_m = PATH0_R_LNA_ERR_G1_A_52AA_M;
*cr->path0_lna_err_g1_g = PATH0_R_LNA_ERR_G1_G_52AA;
*cr->path0_lna_err_g1_g_m = PATH0_R_LNA_ERR_G1_G_52AA_M;
*cr->path0_lna_err_g2_a = PATH0_R_LNA_ERR_G2_A_52AA;
*cr->path0_lna_err_g2_a_m = PATH0_R_LNA_ERR_G2_A_52AA_M;
*cr->path0_lna_err_g2_g = PATH0_R_LNA_ERR_G2_G_52AA;
*cr->path0_lna_err_g2_g_m = PATH0_R_LNA_ERR_G2_G_52AA_M;
*cr->path0_lna_err_g3_a = PATH0_R_LNA_ERR_G3_A_52AA;
*cr->path0_lna_err_g3_a_m = PATH0_R_LNA_ERR_G3_A_52AA_M;
*cr->path0_lna_err_g3_g = PATH0_R_LNA_ERR_G3_G_52AA;
*cr->path0_lna_err_g3_g_m = PATH0_R_LNA_ERR_G3_G_52AA_M;
*cr->path0_lna_err_g4_a = PATH0_R_LNA_ERR_G4_A_52AA;
*cr->path0_lna_err_g4_a_m = PATH0_R_LNA_ERR_G4_A_52AA_M;
*cr->path0_lna_err_g4_g = PATH0_R_LNA_ERR_G4_G_52AA;
*cr->path0_lna_err_g4_g_m = PATH0_R_LNA_ERR_G4_G_52AA_M;
*cr->path0_lna_err_g5_a = PATH0_R_LNA_ERR_G5_A_52AA;
*cr->path0_lna_err_g5_a_m = PATH0_R_LNA_ERR_G5_A_52AA_M;
*cr->path0_lna_err_g5_g = PATH0_R_LNA_ERR_G5_G_52AA;
*cr->path0_lna_err_g5_g_m = PATH0_R_LNA_ERR_G5_G_52AA_M;
*cr->path0_lna_err_g6_a = PATH0_R_LNA_ERR_G6_A_52AA;
*cr->path0_lna_err_g6_a_m = PATH0_R_LNA_ERR_G6_A_52AA_M;
*cr->path0_lna_err_g6_g = PATH0_R_LNA_ERR_G6_G_52AA;
*cr->path0_lna_err_g6_g_m = PATH0_R_LNA_ERR_G6_G_52AA_M;
*cr->path0_tia_err_g0_a = PATH0_R_TIA_ERR_G0_A_52AA;
*cr->path0_tia_err_g0_a_m = PATH0_R_TIA_ERR_G0_A_52AA_M;
*cr->path0_tia_err_g0_g = PATH0_R_TIA_ERR_G0_G_52AA;
*cr->path0_tia_err_g0_g_m = PATH0_R_TIA_ERR_G0_G_52AA_M;
*cr->path0_tia_err_g1_a = PATH0_R_TIA_ERR_G1_A_52AA;
*cr->path0_tia_err_g1_a_m = PATH0_R_TIA_ERR_G1_A_52AA_M;
*cr->path0_tia_err_g1_g = PATH0_R_TIA_ERR_G1_G_52AA;
*cr->path0_tia_err_g1_g_m = PATH0_R_TIA_ERR_G1_G_52AA_M;
*cr->path1_lna_err_g0_a = PATH1_R_LNA_ERR_G0_A_52AA;
*cr->path1_lna_err_g0_a_m = PATH1_R_LNA_ERR_G0_A_52AA_M;
*cr->path1_lna_err_g0_g = PATH1_R_LNA_ERR_G0_G_52AA;
*cr->path1_lna_err_g0_g_m = PATH1_R_LNA_ERR_G0_G_52AA_M;
*cr->path1_lna_err_g1_a = PATH1_R_LNA_ERR_G1_A_52AA;
*cr->path1_lna_err_g1_a_m = PATH1_R_LNA_ERR_G1_A_52AA_M;
*cr->path1_lna_err_g1_g = PATH1_R_LNA_ERR_G1_G_52AA;
*cr->path1_lna_err_g1_g_m = PATH1_R_LNA_ERR_G1_G_52AA_M;
*cr->path1_lna_err_g2_a = PATH1_R_LNA_ERR_G2_A_52AA;
*cr->path1_lna_err_g2_a_m = PATH1_R_LNA_ERR_G2_A_52AA_M;
*cr->path1_lna_err_g2_g = PATH1_R_LNA_ERR_G2_G_52AA;
*cr->path1_lna_err_g2_g_m = PATH1_R_LNA_ERR_G2_G_52AA_M;
*cr->path1_lna_err_g3_a = PATH1_R_LNA_ERR_G3_A_52AA;
*cr->path1_lna_err_g3_a_m = PATH1_R_LNA_ERR_G3_A_52AA_M;
*cr->path1_lna_err_g3_g = PATH1_R_LNA_ERR_G3_G_52AA;
*cr->path1_lna_err_g3_g_m = PATH1_R_LNA_ERR_G3_G_52AA_M;
*cr->path1_lna_err_g4_a = PATH1_R_LNA_ERR_G4_A_52AA;
*cr->path1_lna_err_g4_a_m = PATH1_R_LNA_ERR_G4_A_52AA_M;
*cr->path1_lna_err_g4_g = PATH1_R_LNA_ERR_G4_G_52AA;
*cr->path1_lna_err_g4_g_m = PATH1_R_LNA_ERR_G4_G_52AA_M;
*cr->path1_lna_err_g5_a = PATH1_R_LNA_ERR_G5_A_52AA;
*cr->path1_lna_err_g5_a_m = PATH1_R_LNA_ERR_G5_A_52AA_M;
*cr->path1_lna_err_g5_g = PATH1_R_LNA_ERR_G5_G_52AA;
*cr->path1_lna_err_g5_g_m = PATH1_R_LNA_ERR_G5_G_52AA_M;
*cr->path1_lna_err_g6_a = PATH1_R_LNA_ERR_G6_A_52AA;
*cr->path1_lna_err_g6_a_m = PATH1_R_LNA_ERR_G6_A_52AA_M;
*cr->path1_lna_err_g6_g = PATH1_R_LNA_ERR_G6_G_52AA;
*cr->path1_lna_err_g6_g_m = PATH1_R_LNA_ERR_G6_G_52AA_M;
*cr->path1_tia_err_g0_a = PATH1_R_TIA_ERR_G0_A_52AA;
*cr->path1_tia_err_g0_a_m = PATH1_R_TIA_ERR_G0_A_52AA_M;
*cr->path1_tia_err_g0_g = PATH1_R_TIA_ERR_G0_G_52AA;
*cr->path1_tia_err_g0_g_m = PATH1_R_TIA_ERR_G0_G_52AA_M;
*cr->path1_tia_err_g1_a = PATH1_R_TIA_ERR_G1_A_52AA;
*cr->path1_tia_err_g1_a_m = PATH1_R_TIA_ERR_G1_A_52AA_M;
*cr->path1_tia_err_g1_g = PATH1_R_TIA_ERR_G1_G_52AA;
*cr->path1_tia_err_g1_g_m = PATH1_R_TIA_ERR_G1_G_52AA_M;
*/
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->path0_ib_pbk = PATH0_R_IB_PBK_A;
cr->path0_ib_pbk_m = PATH0_R_IB_PBK_A_M;
cr->path0_ib_pkpwr = PATH0_R_IB_PKPW_A;
cr->path0_ib_pkpwr_m = PATH0_R_IB_PKPW_A_M;
cr->path1_ib_pbk = PATH1_R_IB_PBK_A;
cr->path1_ib_pbk_m = PATH1_R_IB_PBK_A_M;
cr->path1_ib_pkpwr = PATH1_R_IB_PKPW_A;
cr->path1_ib_pkpwr_m = PATH1_R_IB_PKPW_A_M;
cr->path0_lna_init_idx = PATH0_R_LNA_INIT_IDX_A;
cr->path0_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_A_M;
cr->path1_lna_init_idx = PATH1_R_LNA_INIT_IDX_A;
cr->path1_lna_init_idx_m = PATH1_R_LNA_INIT_IDX_A_M;
cr->path0_tia_init_idx = PATH0_R_TIA_INIT_IDX_A;
cr->path0_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_A_M;
cr->path1_tia_init_idx = PATH1_R_TIA_INIT_IDX_A;
cr->path1_tia_init_idx_m = PATH1_R_TIA_INIT_IDX_A_M;
cr->path0_rxb_init_idx = PATH0_R_RXB_INIT_IDX_A;
cr->path0_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_A_M;
cr->path1_rxb_init_idx = PATH1_R_RXB_INIT_IDX_A;
cr->path1_rxb_init_idx_m = PATH1_R_RXB_INIT_IDX_A_M;
cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_A;
cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_A_M;
cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_A;
cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_A_M;
cr->path0_p20_follow_by_pagcugc_en_a = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_A;
cr->path0_p20_follow_by_pagcugc_en_a_m = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_A_M;
cr->path0_s20_follow_by_pagcugc_en_a = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_A;
cr->path0_s20_follow_by_pagcugc_en_a_m = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_A_M;
cr->path1_p20_follow_by_pagcugc_en_a = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_A;
cr->path1_p20_follow_by_pagcugc_en_a_m = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_A_M;
cr->path1_s20_follow_by_pagcugc_en_a = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_A;
cr->path1_s20_follow_by_pagcugc_en_a_m = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_A_M;
cr->path0_lna_err_g0_a = PATH0_R_LNA_ERR_G0_A_A;
cr->path0_lna_err_g0_a_m = PATH0_R_LNA_ERR_G0_A_A_M;
cr->path0_lna_err_g0_g = PATH0_R_LNA_ERR_G0_G_A;
cr->path0_lna_err_g0_g_m = PATH0_R_LNA_ERR_G0_G_A_M;
cr->path0_lna_err_g1_a = PATH0_R_LNA_ERR_G1_A_A;
cr->path0_lna_err_g1_a_m = PATH0_R_LNA_ERR_G1_A_A_M;
cr->path0_lna_err_g1_g = PATH0_R_LNA_ERR_G1_G_A;
cr->path0_lna_err_g1_g_m = PATH0_R_LNA_ERR_G1_G_A_M;
cr->path0_lna_err_g2_a = PATH0_R_LNA_ERR_G2_A_A;
cr->path0_lna_err_g2_a_m = PATH0_R_LNA_ERR_G2_A_A_M;
cr->path0_lna_err_g2_g = PATH0_R_LNA_ERR_G2_G_A;
cr->path0_lna_err_g2_g_m = PATH0_R_LNA_ERR_G2_G_A_M;
cr->path0_lna_err_g3_a = PATH0_R_LNA_ERR_G3_A_A;
cr->path0_lna_err_g3_a_m = PATH0_R_LNA_ERR_G3_A_A_M;
cr->path0_lna_err_g3_g = PATH0_R_LNA_ERR_G3_G_A;
cr->path0_lna_err_g3_g_m = PATH0_R_LNA_ERR_G3_G_A_M;
cr->path0_lna_err_g4_a = PATH0_R_LNA_ERR_G4_A_A;
cr->path0_lna_err_g4_a_m = PATH0_R_LNA_ERR_G4_A_A_M;
cr->path0_lna_err_g4_g = PATH0_R_LNA_ERR_G4_G_A;
cr->path0_lna_err_g4_g_m = PATH0_R_LNA_ERR_G4_G_A_M;
cr->path0_lna_err_g5_a = PATH0_R_LNA_ERR_G5_A_A;
cr->path0_lna_err_g5_a_m = PATH0_R_LNA_ERR_G5_A_A_M;
cr->path0_lna_err_g5_g = PATH0_R_LNA_ERR_G5_G_A;
cr->path0_lna_err_g5_g_m = PATH0_R_LNA_ERR_G5_G_A_M;
cr->path0_lna_err_g6_a = PATH0_R_LNA_ERR_G6_A_A;
cr->path0_lna_err_g6_a_m = PATH0_R_LNA_ERR_G6_A_A_M;
cr->path0_lna_err_g6_g = PATH0_R_LNA_ERR_G6_G_A;
cr->path0_lna_err_g6_g_m = PATH0_R_LNA_ERR_G6_G_A_M;
cr->path0_tia_err_g0_a = PATH0_R_TIA_ERR_G0_A_A;
cr->path0_tia_err_g0_a_m = PATH0_R_TIA_ERR_G0_A_A_M;
cr->path0_tia_err_g0_g = PATH0_R_TIA_ERR_G0_G_A;
cr->path0_tia_err_g0_g_m = PATH0_R_TIA_ERR_G0_G_A_M;
cr->path0_tia_err_g1_a = PATH0_R_TIA_ERR_G1_A_A;
cr->path0_tia_err_g1_a_m = PATH0_R_TIA_ERR_G1_A_A_M;
cr->path0_tia_err_g1_g = PATH0_R_TIA_ERR_G1_G_A;
cr->path0_tia_err_g1_g_m = PATH0_R_TIA_ERR_G1_G_A_M;
cr->path1_lna_err_g0_a = PATH1_R_LNA_ERR_G0_A_A;
cr->path1_lna_err_g0_a_m = PATH1_R_LNA_ERR_G0_A_A_M;
cr->path1_lna_err_g0_g = PATH1_R_LNA_ERR_G0_G_A;
cr->path1_lna_err_g0_g_m = PATH1_R_LNA_ERR_G0_G_A_M;
cr->path1_lna_err_g1_a = PATH1_R_LNA_ERR_G1_A_A;
cr->path1_lna_err_g1_a_m = PATH1_R_LNA_ERR_G1_A_A_M;
cr->path1_lna_err_g1_g = PATH1_R_LNA_ERR_G1_G_A;
cr->path1_lna_err_g1_g_m = PATH1_R_LNA_ERR_G1_G_A_M;
cr->path1_lna_err_g2_a = PATH1_R_LNA_ERR_G2_A_A;
cr->path1_lna_err_g2_a_m = PATH1_R_LNA_ERR_G2_A_A_M;
cr->path1_lna_err_g2_g = PATH1_R_LNA_ERR_G2_G_A;
cr->path1_lna_err_g2_g_m = PATH1_R_LNA_ERR_G2_G_A_M;
cr->path1_lna_err_g3_a = PATH1_R_LNA_ERR_G3_A_A;
cr->path1_lna_err_g3_a_m = PATH1_R_LNA_ERR_G3_A_A_M;
cr->path1_lna_err_g3_g = PATH1_R_LNA_ERR_G3_G_A;
cr->path1_lna_err_g3_g_m = PATH1_R_LNA_ERR_G3_G_A_M;
cr->path1_lna_err_g4_a = PATH1_R_LNA_ERR_G4_A_A;
cr->path1_lna_err_g4_a_m = PATH1_R_LNA_ERR_G4_A_A_M;
cr->path1_lna_err_g4_g = PATH1_R_LNA_ERR_G4_G_A;
cr->path1_lna_err_g4_g_m = PATH1_R_LNA_ERR_G4_G_A_M;
cr->path1_lna_err_g5_a = PATH1_R_LNA_ERR_G5_A_A;
cr->path1_lna_err_g5_a_m = PATH1_R_LNA_ERR_G5_A_A_M;
cr->path1_lna_err_g5_g = PATH1_R_LNA_ERR_G5_G_A;
cr->path1_lna_err_g5_g_m = PATH1_R_LNA_ERR_G5_G_A_M;
cr->path1_lna_err_g6_a = PATH1_R_LNA_ERR_G6_A_A;
cr->path1_lna_err_g6_a_m = PATH1_R_LNA_ERR_G6_A_A_M;
cr->path1_lna_err_g6_g = PATH1_R_LNA_ERR_G6_G_A;
cr->path1_lna_err_g6_g_m = PATH1_R_LNA_ERR_G6_G_A_M;
cr->path1_tia_err_g0_a = PATH1_R_TIA_ERR_G0_A_A;
cr->path1_tia_err_g0_a_m = PATH1_R_TIA_ERR_G0_A_A_M;
cr->path1_tia_err_g0_g = PATH1_R_TIA_ERR_G0_G_A;
cr->path1_tia_err_g0_g_m = PATH1_R_TIA_ERR_G0_G_A_M;
cr->path1_tia_err_g1_a = PATH1_R_TIA_ERR_G1_A_A;
cr->path1_tia_err_g1_a_m = PATH1_R_TIA_ERR_G1_A_A_M;
cr->path1_tia_err_g1_g = PATH1_R_TIA_ERR_G1_G_A;
cr->path1_tia_err_g1_g_m = PATH1_R_TIA_ERR_G1_G_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->path0_lna_init_idx = PATH0_R_LNA_IDX_INIT_C;
cr->path0_lna_init_idx_m = PATH0_R_LNA_IDX_INIT_C_M;
cr->path1_lna_init_idx = PATH1_R_LNA_IDX_INIT_C;
cr->path1_lna_init_idx_m = PATH1_R_LNA_IDX_INIT_C_M;
cr->path0_tia_init_idx = PATH0_R_TIA_IDX_INIT_C;
cr->path0_tia_init_idx_m = PATH0_R_TIA_IDX_INIT_C_M;
cr->path1_tia_init_idx = PATH1_R_TIA_IDX_INIT_C;
cr->path1_tia_init_idx_m = PATH1_R_TIA_IDX_INIT_C_M;
cr->path0_rxb_init_idx = PATH0_R_RXIDX_INIT_C;
cr->path0_rxb_init_idx_m = PATH0_R_RXIDX_INIT_C_M;
cr->path1_rxb_init_idx = PATH1_R_RXIDX_INIT_C;
cr->path1_rxb_init_idx_m = PATH1_R_RXIDX_INIT_C_M;
cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_C;
cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_C_M;
cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_C;
cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_C_M;
#if 0
cr->path0_ib_pbk = PATH0_R_IB_PBK_C;
cr->path0_ib_pbk_m = PATH0_R_IB_PBK_C_M;
cr->path0_ib_pkpwr = PATH0_R_IB_PKPW_C;
cr->path0_ib_pkpwr_m = PATH0_R_IB_PKPW_C_M;
cr->path1_ib_pbk = PATH1_R_IB_PBK_C;
cr->path1_ib_pbk_m = PATH1_R_IB_PBK_C_M;
cr->path1_ib_pkpwr = PATH1_R_IB_PKPW_C;
cr->path1_ib_pkpwr_m = PATH1_R_IB_PKPW_C_M;
cr->path0_lna_init_idx = PATH0_R_LNA_INIT_IDX_C;
cr->path0_lna_init_idx_m = PATH0_R_LNA_INIT_IDX_C_M;
cr->path1_lna_init_idx = PATH1_R_LNA_INIT_IDX_C;
cr->path1_lna_init_idx_m = PATH1_R_LNA_INIT_IDX_C_M;
cr->path0_tia_init_idx = PATH0_R_TIA_INIT_IDX_C;
cr->path0_tia_init_idx_m = PATH0_R_TIA_INIT_IDX_C_M;
cr->path1_tia_init_idx = PATH1_R_TIA_INIT_IDX_C;
cr->path1_tia_init_idx_m = PATH1_R_TIA_INIT_IDX_C_M;
cr->path0_rxb_init_idx = PATH0_R_RXB_INIT_IDX_C;
cr->path0_rxb_init_idx_m = PATH0_R_RXB_INIT_IDX_C_M;
cr->path1_rxb_init_idx = PATH1_R_RXB_INIT_IDX_C;
cr->path1_rxb_init_idx_m = PATH1_R_RXB_INIT_IDX_C_M;
cr->seg0r_pd_spatial_reuse_en_a = SEG0R_PD_SPATIAL_REUSE_EN_C;
cr->seg0r_pd_spatial_reuse_en_a_m = SEG0R_PD_SPATIAL_REUSE_EN_C_M;
cr->seg0r_pd_lower_bound_a = SEG0R_PD_LOWER_BOUND_C;
cr->seg0r_pd_lower_bound_a_m = SEG0R_PD_LOWER_BOUND_C_M;
cr->path0_p20_follow_by_pagcugc_en_a = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C;
cr->path0_p20_follow_by_pagcugc_en_a_m = PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M;
cr->path0_s20_follow_by_pagcugc_en_a = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C;
cr->path0_s20_follow_by_pagcugc_en_a_m = PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M;
cr->path1_p20_follow_by_pagcugc_en_a = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C;
cr->path1_p20_follow_by_pagcugc_en_a_m = PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M;
cr->path1_s20_follow_by_pagcugc_en_a = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C;
cr->path1_s20_follow_by_pagcugc_en_a_m = PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M;
cr->path0_lna_err_g0_a = PATH0_R_LNA_ERR_G0_C_C;
cr->path0_lna_err_g0_a_m = PATH0_R_LNA_ERR_G0_C_C_M;
cr->path0_lna_err_g0_g = PATH0_R_LNA_ERR_G0_G_C;
cr->path0_lna_err_g0_g_m = PATH0_R_LNA_ERR_G0_G_C_M;
cr->path0_lna_err_g1_a = PATH0_R_LNA_ERR_G1_C_C;
cr->path0_lna_err_g1_a_m = PATH0_R_LNA_ERR_G1_C_C_M;
cr->path0_lna_err_g1_g = PATH0_R_LNA_ERR_G1_G_C;
cr->path0_lna_err_g1_g_m = PATH0_R_LNA_ERR_G1_G_C_M;
cr->path0_lna_err_g2_a = PATH0_R_LNA_ERR_G2_C_C;
cr->path0_lna_err_g2_a_m = PATH0_R_LNA_ERR_G2_C_C_M;
cr->path0_lna_err_g2_g = PATH0_R_LNA_ERR_G2_G_C;
cr->path0_lna_err_g2_g_m = PATH0_R_LNA_ERR_G2_G_C_M;
cr->path0_lna_err_g3_a = PATH0_R_LNA_ERR_G3_C_C;
cr->path0_lna_err_g3_a_m = PATH0_R_LNA_ERR_G3_C_C_M;
cr->path0_lna_err_g3_g = PATH0_R_LNA_ERR_G3_G_C;
cr->path0_lna_err_g3_g_m = PATH0_R_LNA_ERR_G3_G_C_M;
cr->path0_lna_err_g4_a = PATH0_R_LNA_ERR_G4_C_C;
cr->path0_lna_err_g4_a_m = PATH0_R_LNA_ERR_G4_C_C_M;
cr->path0_lna_err_g4_g = PATH0_R_LNA_ERR_G4_G_C;
cr->path0_lna_err_g4_g_m = PATH0_R_LNA_ERR_G4_G_C_M;
cr->path0_lna_err_g5_a = PATH0_R_LNA_ERR_G5_C_C;
cr->path0_lna_err_g5_a_m = PATH0_R_LNA_ERR_G5_C_C_M;
cr->path0_lna_err_g5_g = PATH0_R_LNA_ERR_G5_G_C;
cr->path0_lna_err_g5_g_m = PATH0_R_LNA_ERR_G5_G_C_M;
cr->path0_lna_err_g6_a = PATH0_R_LNA_ERR_G6_C_C;
cr->path0_lna_err_g6_a_m = PATH0_R_LNA_ERR_G6_C_C_M;
cr->path0_lna_err_g6_g = PATH0_R_LNA_ERR_G6_G_C;
cr->path0_lna_err_g6_g_m = PATH0_R_LNA_ERR_G6_G_C_M;
cr->path0_tia_err_g0_a = PATH0_R_TIA_ERR_G0_C_C;
cr->path0_tia_err_g0_a_m = PATH0_R_TIA_ERR_G0_C_C_M;
cr->path0_tia_err_g0_g = PATH0_R_TIA_ERR_G0_G_C;
cr->path0_tia_err_g0_g_m = PATH0_R_TIA_ERR_G0_G_C_M;
cr->path0_tia_err_g1_a = PATH0_R_TIA_ERR_G1_C_C;
cr->path0_tia_err_g1_a_m = PATH0_R_TIA_ERR_G1_C_C_M;
cr->path0_tia_err_g1_g = PATH0_R_TIA_ERR_G1_G_C;
cr->path0_tia_err_g1_g_m = PATH0_R_TIA_ERR_G1_G_C_M;
cr->path1_lna_err_g0_a = PATH1_R_LNA_ERR_G0_C_C;
cr->path1_lna_err_g0_a_m = PATH1_R_LNA_ERR_G0_C_C_M;
cr->path1_lna_err_g0_g = PATH1_R_LNA_ERR_G0_G_C;
cr->path1_lna_err_g0_g_m = PATH1_R_LNA_ERR_G0_G_C_M;
cr->path1_lna_err_g1_a = PATH1_R_LNA_ERR_G1_C_C;
cr->path1_lna_err_g1_a_m = PATH1_R_LNA_ERR_G1_C_C_M;
cr->path1_lna_err_g1_g = PATH1_R_LNA_ERR_G1_G_C;
cr->path1_lna_err_g1_g_m = PATH1_R_LNA_ERR_G1_G_C_M;
cr->path1_lna_err_g2_a = PATH1_R_LNA_ERR_G2_C_C;
cr->path1_lna_err_g2_a_m = PATH1_R_LNA_ERR_G2_C_C_M;
cr->path1_lna_err_g2_g = PATH1_R_LNA_ERR_G2_G_C;
cr->path1_lna_err_g2_g_m = PATH1_R_LNA_ERR_G2_G_C_M;
cr->path1_lna_err_g3_a = PATH1_R_LNA_ERR_G3_C_C;
cr->path1_lna_err_g3_a_m = PATH1_R_LNA_ERR_G3_C_C_M;
cr->path1_lna_err_g3_g = PATH1_R_LNA_ERR_G3_G_C;
cr->path1_lna_err_g3_g_m = PATH1_R_LNA_ERR_G3_G_C_M;
cr->path1_lna_err_g4_a = PATH1_R_LNA_ERR_G4_C_C;
cr->path1_lna_err_g4_a_m = PATH1_R_LNA_ERR_G4_C_C_M;
cr->path1_lna_err_g4_g = PATH1_R_LNA_ERR_G4_G_C;
cr->path1_lna_err_g4_g_m = PATH1_R_LNA_ERR_G4_G_C_M;
cr->path1_lna_err_g5_a = PATH1_R_LNA_ERR_G5_C_C;
cr->path1_lna_err_g5_a_m = PATH1_R_LNA_ERR_G5_C_C_M;
cr->path1_lna_err_g5_g = PATH1_R_LNA_ERR_G5_G_C;
cr->path1_lna_err_g5_g_m = PATH1_R_LNA_ERR_G5_G_C_M;
cr->path1_lna_err_g6_a = PATH1_R_LNA_ERR_G6_C_C;
cr->path1_lna_err_g6_a_m = PATH1_R_LNA_ERR_G6_C_C_M;
cr->path1_lna_err_g6_g = PATH1_R_LNA_ERR_G6_G_C;
cr->path1_lna_err_g6_g_m = PATH1_R_LNA_ERR_G6_G_C_M;
cr->path1_tia_err_g0_a = PATH1_R_TIA_ERR_G0_C_C;
cr->path1_tia_err_g0_a_m = PATH1_R_TIA_ERR_G0_C_C_M;
cr->path1_tia_err_g0_g = PATH1_R_TIA_ERR_G0_G_C;
cr->path1_tia_err_g0_g_m = PATH1_R_TIA_ERR_G0_G_C_M;
cr->path1_tia_err_g1_a = PATH1_R_TIA_ERR_G1_C_C;
cr->path1_tia_err_g1_a_m = PATH1_R_TIA_ERR_G1_C_C_M;
cr->path1_tia_err_g1_g = PATH1_R_TIA_ERR_G1_G_C;
cr->path1_tia_err_g1_g_m = PATH1_R_TIA_ERR_G1_G_C_M;
#endif
break;
#endif
default:
break;
}
}
#endif
#ifdef HALBB_DIG_MCC_SUPPORT
void Halbb_init_mccdm(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
u8 i = 0;
BB_DBG(bb, DBG_DIG, "[%s]=========>\n", __func__);
mcc_dm->softap_macid = INVALID_INIT_VAL;
for (i = 0; i < MCC_BAND_NUM; i++) {
mcc_dm->mcc_reg_id[i] = INVALID_INIT_VAL;
mcc_dm->mcc_dm_reg[i] = 0;
mcc_dm->mcc_dm_val[i][0] = 0;
mcc_dm->mcc_dm_val[i][1] = 0;
}
}
u32 halbb_c2h_mccdm_check(struct bb_info *bb, u16 len, u8 *c2h)
{
bool fw_mccdm_en = false;
if (!c2h) {
BB_WARNING("Error fw mcc dig c2h failed!!\n");
return _FAIL;
}
fw_mccdm_en = (bool)c2h[0];
BB_DBG(bb, DBG_DIG, "FW MCC DIG : %s\n", fw_mccdm_en ? "true" : "false");
return _SUCCESS;
}
void halbb_mccdm_h2ccmd_rst(struct bb_info *bb)
{
struct mcc_h2c *mcc_cfg;
bool ret_val = false;
u8 cmdlen = sizeof(struct mcc_h2c);
u32 *bb_h2c;
mcc_cfg = hal_mem_alloc(bb->hal_com, cmdlen);
if (!mcc_cfg) {
BB_WARNING(" Error mcc_cfg allocat failed!!\n");
return;
}
halbb_mem_set(bb, mcc_cfg, 0, cmdlen);
bb_h2c = (u32*) mcc_cfg;
//u8 h2c_mcc[H2C_MAX_LENGTH];
/* RST MCC */
mcc_cfg->mcc_dm_en = 0;
mcc_cfg->reg_cnt = 0;
mcc_cfg->mcc_set = 0;
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_MCC,
HALBB_H2C_DM, bb_h2c);
BB_DBG(bb, DBG_DIG, "MCC H2C RST\n");
if (mcc_cfg)
hal_mem_free(bb->hal_com, mcc_cfg, cmdlen);
}
void Halbb_mccdm_h2c_handler(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
struct mcc_h2c_reg_content *reg_cont;
struct mcc_h2c *mcc_cfg;
bool ret_val = false;
u8 cmdlen = sizeof(struct mcc_h2c);
u8 i;
u8 regid;
u8 ch_idx;
u8 reg_cnt;
u32 *bb_h2c;
mcc_cfg = hal_mem_alloc(bb->hal_com, cmdlen);
if (!mcc_cfg) {
BB_WARNING(" Error mcc_cfg allocat failed!!\n");
return;
}
bb_h2c = (u32*) mcc_cfg;
if (mcc_dm->mcc_rf_ch[0].center_ch == INVALID_INIT_VAL &&
mcc_dm->mcc_rf_ch[1].center_ch == INVALID_INIT_VAL) {
BB_DBG(bb, DBG_DIG, "MCC channel Error\n");
mcc_cfg->mcc_dm_en = 0;
mcc_cfg->reg_cnt = 0;
mcc_cfg->mcc_set = 0;
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_MCC,
HALBB_H2C_DM, bb_h2c);
if (mcc_cfg)
hal_mem_free(bb->hal_com, mcc_cfg, cmdlen);
return;
}
/* Set Channel number, reg, and val*/
for (ch_idx = 0; ch_idx < MCC_BAND_NUM; ch_idx++) {
halbb_mem_set(bb, mcc_cfg, 0, cmdlen);
reg_cnt = 0;
mcc_cfg->mcc_dm_en = 1;
mcc_cfg->mcc_ch_idx = ch_idx;
mcc_cfg->mcc_set = 1;
mcc_cfg->phy0_en = 1;
mcc_cfg->phy1_en = 0;
mcc_cfg->ch_lsb = (u8)mcc_dm->mcc_rf_ch[ch_idx].center_ch;
mcc_cfg->ch_msb = (u8)mcc_dm->mcc_rf_ch[ch_idx].band;
for (i = 0; i < NUM_MAX_IGI_CNT; i++) {
regid = mcc_dm->mcc_reg_id[i];
if (regid == INVALID_INIT_VAL)
break;
reg_cont = &mcc_cfg->mcc_reg_content[i];
reg_cont->addr_lsb = (u8)mcc_dm->mcc_dm_reg[i];
reg_cont->addr_msb = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
reg_cont->bmask_lsb = (u8)(mcc_dm->mcc_dm_mask[i]);
reg_cont->bmask_msb = (u8)(mcc_dm->mcc_dm_mask[i] >> 8);
reg_cont->val_lsb = (u8)(mcc_dm->mcc_dm_val[i][ch_idx]);
reg_cont->val_msb = (u8)(mcc_dm->mcc_dm_val[i][ch_idx] >> 8);
reg_cnt++;
}
mcc_cfg->reg_cnt = reg_cnt;
BB_DBG(bb, DBG_DIG, "MCC H2C SetCH: 0x%x 0x%x 0x%x\n",
bb_h2c[0], bb_h2c[1], bb_h2c[2]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_MCC,
HALBB_H2C_DM, bb_h2c);
}
if (mcc_cfg)
hal_mem_free(bb->hal_com, mcc_cfg, cmdlen);
}
void halbb_mccdm_ctrl(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
u32 val[2] = {0};
BB_DBG(bb, DBG_DIG, "MCC status: %x\n", mcc_dm->mcc_status_en);
/*MCC stage no change*/
if (mcc_dm->mcc_status_en == mcc_dm->mcc_pre_status_en)
return;
/*Not in MCC stage*/
if (mcc_dm->mcc_status_en != 0) {
/* Disable normal DIG */
halbb_pause_func(bb, F_DIG, HALBB_PAUSE_NO_SET, HALBB_PAUSE_LV_2,
2, val);
}
if (mcc_dm->mcc_status_en == 0 && mcc_dm->mcc_pre_status_en != 0) {
Halbb_init_mccdm(bb);
halbb_mccdm_h2ccmd_rst(bb);
/* Enable normal DIG */
halbb_pause_func(bb, F_DIG, HALBB_RESUME, HALBB_PAUSE_LV_2, 2,
val);
}
mcc_dm->mcc_pre_status_en = mcc_dm->mcc_status_en;
}
void halbb_fill_mcccmd(struct bb_info *bb, u8 regid, u16 reg_add, u16 mask,
u8 band, u16 val)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
mcc_dm->mcc_reg_id[regid] = regid;
mcc_dm->mcc_dm_reg[regid] = reg_add;
mcc_dm->mcc_dm_mask[regid] = mask;
mcc_dm->mcc_dm_val[regid][band] = val;
}
void halbb_mccdm_igi_rst(struct bb_info *bb, u8 clr_port)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
mcc_dm->mcc_dm_val[0][clr_port] = PD_IDX_MIN; //-102dBm
//mcc_dm->mcc_dm_val[1][clr_port] = 0xff;
}
#if 0
void halbb_mcc_igi_chk(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
if (mcc_dm->mcc_dm_val[0][0] == 0xffff &&
mcc_dm->mcc_dm_val[0][1] == 0xffff) {
mcc_dm->mcc_dm_reg[0] = 0xffff;
mcc_dm->mcc_reg_id[0] = 0xff;
}
if (mcc_dm->mcc_dm_val[1][0] == 0xffff &&
mcc_dm->mcc_dm_val[1][1] == 0xffff) {
mcc_dm->mcc_dm_reg[1] = 0xffff;
mcc_dm->mcc_reg_id[1] = 0xff;
}
}
#endif
u8 halbb_mccdm_pd_lower_bound_cal(struct bb_info *bb, u8 bound,
enum channel_width bw)
{
/*
Range of bound value:
BW20: 95~33
BW40: 92~30
BW80: 89~27
*/
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 7;
u8 bound_idx = 0;
if (bound == 0) {
BB_DBG(bb, DBG_DIG,
"[PD Bound] Set Boundary to default!\n");
return 0;
}
if (bw == CHANNEL_WIDTH_20) {
bw_attenuation = 0;
} else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
} else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
} else {
BB_DBG(bb, DBG_DIG,
"[PD Bound] Only support BW20/40/80 !\n");
return 0;
}
bound += (bw_attenuation + subband_filter_atteniation);
// If Boundary dbm is odd, set it to even number
bound = bound % 2 ? bound + 1 : bound;
if (bound < 40) {
BB_DBG(bb, DBG_DIG,
"[PD Bound] Threshold too high, set to highest level!\n");
bound = 40;
}
if (bound > 102) {
BB_DBG(bb, DBG_DIG,
"[PD Bound] Threshold too low, disable PD lower bound function!\n");
bound = 102;
}
bound_idx = (102 - bound) >> 1;
return bound_idx;
}
void halbb_mccdm_pd_cal(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
struct bb_dig_cr_info *cr = &bb_dig->bb_dig_cr_i;
u8 shift = 10;
u8 igi_val;
u8 pd_val;
u8 i;
u16 mask0;
u16 reg0;
enum channel_width cbw = CHANNEL_WIDTH_20;
for (i = 0; i < MCC_BAND_NUM; i++) {
igi_val = mcc_dm->rssi_min[i] >> 1;
igi_val = SUBTRACT_TO_0(igi_val, shift);
igi_val = MIN_2(igi_val, IGI_MAX_PERFORMANCE_MODE);
igi_val = MAX_2(igi_val, 0xc);
igi_val -= MIN_2(igi_val, bb_dig_u->pd_low_th_ofst);
cbw = mcc_dm->mcc_rf_ch[i].bw;
pd_val = halbb_mccdm_pd_lower_bound_cal(bb, RSSI_MAX - igi_val,
cbw);
reg0 = (u16)cr->seg0r_pd_lower_bound_a;
mask0 = (u16)cr->seg0r_pd_lower_bound_a_m;
halbb_fill_mcccmd(bb, 0, reg0, mask0, i, (u16)pd_val);
if (mcc_dm->sta_cnt[i] == 0)
halbb_mccdm_igi_rst(bb, i);
}
BB_DBG(bb, DBG_DIG, "STA cnt %d %d, RSSI_min: %d %d, BW: %d %d, MCC_pd_idx: %d %d\n",
mcc_dm->sta_cnt[0], mcc_dm->sta_cnt[1],
mcc_dm->rssi_min[0] >> 1, mcc_dm->rssi_min[1] >> 1,
mcc_dm->mcc_rf_ch[0].bw, mcc_dm->mcc_rf_ch[1].bw,
mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
}
void halbb_mccdm_switch(struct bb_info *bb)
{
struct halbb_mcc_dm *mcc_dm = &bb->mcc_dm;
if (!(bb->ic_type & HALBB_DIG_MCC_SUPPORT_IC)) {
BB_DBG(bb, DBG_DIG, "IC type is not supported\n");
return;
}
halbb_mccdm_ctrl(bb);
if (mcc_dm->mcc_status_en == 0)
return;
BB_DBG(bb, DBG_DIG, "<====== %s ======>\n", __func__);
/* Set IGI*/
halbb_mccdm_pd_cal(bb);
/* Set H2C Cmd*/
Halbb_mccdm_h2c_handler(bb);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dig.c
|
C
|
agpl-3.0
| 85,552
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DIG_H__
#define __HALBB_DIG_H__
#define DIG_VERSION "4.0"
/*@--------------------------[Define] ---------------------------------------*/
#define BB_LNA_SIZE 7
#define BB_TIA_SIZE 2
#define IGI_RSSI_TH_NUM 5
#define FA_TH_NUM 4
#define RSSI_MAX 110
#define RSSI_MIN 0
#define IGI_NOLINK 38
#define LNA_IDX_MAX 6
#define LNA_IDX_MIN 0
#define TIA_IDX_MAX 1
#define TIA_IDX_MIN 0
#define RXB_IDX_MAX 31
#define RXB_IDX_MIN 0
#define LNA6_GAIN 24
#define LNA5_GAIN 16
#define LNA4_GAIN 8
#define LNA3_GAIN 0
#define LNA2_GAIN (-8)
#define LNA1_GAIN (-16)
#define LNA0_GAIN (-24)
#define TIA1_GAIN_A 20
#define TIA0_GAIN_A 12
#define TIA1_GAIN_G 24
#define TIA0_GAIN_G 16
#define IGI_OFFSET_MAX 25 /* IGI window size */
#define IGI_MAX_PERFORMANCE_MODE 0x5a
#define IGI_MAX_BALANCE_MODE 0x3e
#define PD_TH_MAX_RSSI 70 /* -40dBm */
#define PD_TH_MIN_RSSI 8 /* -102dBm */
#define PD_TH_BW80_CMP_VAL 6
#define PD_TH_BW40_CMP_VAL 3
#define PD_TH_BW20_CMP_VAL 0
#define PD_TH_SB_FLTR_CMP_VAL 7
#define DIG_CCX_WD_TRIGTIME 1900
#define IGI_EDCCA_GAP_LIMIT 35
#ifdef HALBB_DIG_TDMA_SUPPORT
#define IGI_MAX_AT_STATE_L 0x26
#define WACHDOG_PERIOD_IN_MS 2000
#define H_STATE_NUM_MAX 20
#define L_STATE_NUM_MAX 10
#endif
#define DIG_RECORD_NUM 6
#define DIG_LIMIT_PERIOD 60 /*60 sec*/
#ifdef HALBB_DBG_TRACE_SUPPORT
#define BB_DIG_DBG(bb, lv, fmt, ...)\
do {\
if(bb->dbg_component & DBG_DIG && bb->bb_dig_i.dbg_lv >= lv) {\
_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
}\
} while (0)
#else
#define BB_DIG_DBG(bb, lv, fmt, ...)
#endif
/*@--------------------------[Enum]------------------------------------------*/
enum dig_noisy_level {
DIG_NOISY_LV0 = 0, /*FA free*/
DIG_NOISY_LV1 = 1,
DIG_NOISY_LV2 = 2,
DIG_NOISY_LV3 = 3,
DIG_NOISY_LV_MAX = 4
};
#ifdef HALBB_DIG_TDMA_SUPPORT
enum dig_tdma_state {
DIG_TDMA_LOW = 0,
DIG_TDMA_HIGH = 1
};
#endif
enum dig_dbg_level {
DIG_DBG_LV0 = 0,
DIG_DBG_LV1 = 1,
DIG_DBG_LV2 = 2
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dig_cr_info {
u32 path0_ib_pbk;
u32 path0_ib_pbk_m;
u32 path0_ib_pkpwr;
u32 path0_ib_pkpwr_m;
u32 path1_ib_pbk;
u32 path1_ib_pbk_m;
u32 path1_ib_pkpwr;
u32 path1_ib_pkpwr_m;
u32 path0_lna_init_idx;
u32 path0_lna_init_idx_m;
u32 path1_lna_init_idx;
u32 path1_lna_init_idx_m;
u32 path0_tia_init_idx;
u32 path0_tia_init_idx_m;
u32 path1_tia_init_idx;
u32 path1_tia_init_idx_m;
u32 path0_rxb_init_idx;
u32 path0_rxb_init_idx_m;
u32 path1_rxb_init_idx;
u32 path1_rxb_init_idx_m;
u32 seg0r_pd_spatial_reuse_en_a;
u32 seg0r_pd_spatial_reuse_en_a_m;
u32 seg0r_pd_lower_bound_a;
u32 seg0r_pd_lower_bound_a_m;
u32 path0_p20_follow_by_pagcugc_en_a;
u32 path0_s20_follow_by_pagcugc_en_a;
u32 path1_p20_follow_by_pagcugc_en_a;
u32 path1_s20_follow_by_pagcugc_en_a;
u32 path0_p20_follow_by_pagcugc_en_a_m;
u32 path0_s20_follow_by_pagcugc_en_a_m;
u32 path1_p20_follow_by_pagcugc_en_a_m;
u32 path1_s20_follow_by_pagcugc_en_a_m;
u32 path0_lna_err_g0_a;
u32 path0_lna_err_g0_a_m;
u32 path0_lna_err_g0_g;
u32 path0_lna_err_g0_g_m;
u32 path0_lna_err_g1_a;
u32 path0_lna_err_g1_a_m;
u32 path0_lna_err_g1_g;
u32 path0_lna_err_g1_g_m;
u32 path0_lna_err_g2_a;
u32 path0_lna_err_g2_a_m;
u32 path0_lna_err_g2_g;
u32 path0_lna_err_g2_g_m;
u32 path0_lna_err_g3_a;
u32 path0_lna_err_g3_a_m;
u32 path0_lna_err_g3_g;
u32 path0_lna_err_g3_g_m;
u32 path0_lna_err_g4_a;
u32 path0_lna_err_g4_a_m;
u32 path0_lna_err_g4_g;
u32 path0_lna_err_g4_g_m;
u32 path0_lna_err_g5_a;
u32 path0_lna_err_g5_a_m;
u32 path0_lna_err_g5_g;
u32 path0_lna_err_g5_g_m;
u32 path0_lna_err_g6_a;
u32 path0_lna_err_g6_a_m;
u32 path0_lna_err_g6_g;
u32 path0_lna_err_g6_g_m;
u32 path0_tia_err_g0_a;
u32 path0_tia_err_g0_a_m;
u32 path0_tia_err_g0_g;
u32 path0_tia_err_g0_g_m;
u32 path0_tia_err_g1_a;
u32 path0_tia_err_g1_a_m;
u32 path0_tia_err_g1_g;
u32 path0_tia_err_g1_g_m;
u32 path1_lna_err_g0_a;
u32 path1_lna_err_g0_a_m;
u32 path1_lna_err_g0_g;
u32 path1_lna_err_g0_g_m;
u32 path1_lna_err_g1_a;
u32 path1_lna_err_g1_a_m;
u32 path1_lna_err_g1_g;
u32 path1_lna_err_g1_g_m;
u32 path1_lna_err_g2_a;
u32 path1_lna_err_g2_a_m;
u32 path1_lna_err_g2_g;
u32 path1_lna_err_g2_g_m;
u32 path1_lna_err_g3_a;
u32 path1_lna_err_g3_a_m;
u32 path1_lna_err_g3_g;
u32 path1_lna_err_g3_g_m;
u32 path1_lna_err_g4_a;
u32 path1_lna_err_g4_a_m;
u32 path1_lna_err_g4_g;
u32 path1_lna_err_g4_g_m;
u32 path1_lna_err_g5_a;
u32 path1_lna_err_g5_a_m;
u32 path1_lna_err_g5_g;
u32 path1_lna_err_g5_g_m;
u32 path1_lna_err_g6_a;
u32 path1_lna_err_g6_a_m;
u32 path1_lna_err_g6_g;
u32 path1_lna_err_g6_g_m;
u32 path1_tia_err_g0_a;
u32 path1_tia_err_g0_a_m;
u32 path1_tia_err_g0_g;
u32 path1_tia_err_g0_g_m;
u32 path1_tia_err_g1_a;
u32 path1_tia_err_g1_a_m;
u32 path1_tia_err_g1_g;
u32 path1_tia_err_g1_g_m;
};
struct agc_gaincode_set {
u8 lna_idx;
u8 tia_idx;
u8 rxb_idx;
};
struct bb_dig_fa_info {
u16 fa_r_cck_onesec;
u16 fa_r_ofdm_onesec;
u16 fa_r_onesec; /* overall fa_ratio */
};
struct bb_dig_op_para_unit {
bool dyn_pd_th_en;
u8 igi_rssi_th[IGI_RSSI_TH_NUM];
u16 fa_th[FA_TH_NUM]; /* permil */
};
#ifdef HALBB_DIG_DAMPING_CHK
struct bb_dig_record_info {
u8 igi_bitmap; /*@Don't add any new parameter before this*/
u8 igi_history[DIG_RECORD_NUM];
u32 fa_history[DIG_RECORD_NUM];
bool damping_lock_en;
u8 damping_limit_val; /*@Limit IGI_dyn_min*/
u32 limit_time;
u8 limit_rssi; /*s(8,1)*/
};
#endif
/* struct for state unit, i.e., L/H */
struct bb_dig_op_unit {
#ifdef HALBB_DIG_TDMA_SUPPORT
enum dig_tdma_state state_identifier; /* L/H */
#endif
struct agc_gaincode_set cur_gaincode;
enum dig_noisy_level cur_noisy_lv;
struct agc_gaincode_set force_gaincode;
struct bb_dig_op_para_unit dig_op_para;
u16 fa_r_acc; /* acced one shot fa_ratio */
u16 fa_r_avg; /* acced one shot fa_ratio */
u8 fa_valid_state_cnt;
u8 state_num_lmt;
u8 passed_state_cnt;
u8 igi_fa_rssi; /*final IGI calaulated by FA & RSSI*/
u8 fa_rssi_ofst;
u8 abs_igi_max;
u8 abs_igi_min;
u8 dyn_igi_max;
u8 dyn_igi_min;
u8 pd_low_th_ofst; /* pd low safe cca region */
bool sdagc_follow_pagc_en;
};
struct bb_dig_info {
enum dig_op_mode dig_mode;
enum dig_op_mode pre_dig_mode;
struct bb_dig_cr_info bb_dig_cr_i;
struct agc_gaincode_set max_gaincode;
u8 igi_rssi; //rssi_min
u8 ib_pbk;
s8 ib_pkpwr;
s8 lna_gain_a[BB_LNA_SIZE];
s8 lna_gain_g[BB_LNA_SIZE];
s8 *lna_gain;
s8 tia_gain_a[BB_TIA_SIZE];
s8 tia_gain_g[BB_TIA_SIZE];
s8 *tia_gain;
s8 le_igi_ofst; /* low end mode IGI offset */
struct bb_dig_op_unit *p_cur_dig_unit;
struct bb_dig_op_unit dig_state_h_i; /* high state */
#ifdef HALBB_DIG_TDMA_SUPPORT
struct bb_dig_op_unit dig_state_l_i; /* low state */
bool gaincode_update_en;
u16 tdma_passed_time_acc; /* check if 1sec reach */
u8 tdma_timestamp_pre;
u8 tdma_timestamp_cur;
struct halbb_timer_info dig_timer_i;
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
u8 ccx_timestamp;
struct ccx_para_info ccx_para_i;
bool ccx_is_triggered;
#endif
struct bb_dig_fa_info dig_fa_i;
enum dig_dbg_level dbg_lv;
u32 rvrt_val[DIG_PAUSE_INFO_SIZE]; /*[Pause fucntion] must set to u32*/
u16 igi_pause_cnt; /*consective pause counter*/
bool need_update;
u16 dig_hold_cnt;
#ifdef HALBB_DIG_DAMPING_CHK
struct bb_dig_record_info bb_dig_record_i;
u8 rls_rssi_diff_th; /*s(8,1)*/
bool dig_dl_en; /*@damping limit function enable*/
#endif
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_DIG_TDMA_SUPPORT
void halbb_dig_timercheck_watchdog(struct bb_info*);
void halbb_tdmadig_io_en(struct bb_info *bb);
void halbb_dig_timer_init(struct bb_info *bb);
#endif
void halbb_dig_lps(struct bb_info *bb);
void halbb_dig_cfg_bbcr(struct bb_info *bb, u8 igi_new);
void halbb_dig_new_entry_connect(struct bb_info *bb);
void halbb_dig(struct bb_info *bb);
void halbb_dig_init(struct bb_info *bb);
void halbb_dig_deinit(struct bb_info *bb);
void halbb_dig_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_dig_init(struct bb_info *bb);
void* halbb_get_dig_fa_statistic(struct bb_info *bb);
void halbb_set_dig_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
#ifdef HALBB_DIG_MCC_SUPPORT
void Halbb_init_mccdm(struct bb_info *bb);
void halbb_mccdm_switch(struct bb_info *bb);
u32 halbb_c2h_mccdm_check(struct bb_info *bb, u16 len, u8 *c2h);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dig.h
|
C
|
agpl-3.0
| 9,516
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DIG_EX_H__
#define __HALBB_DIG_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
#define DIG_PAUSE_INFO_SIZE 2
/*@--------------------------[Enum]------------------------------------------*/
enum dig_op_mode {
DIG_ORIGIN = 0,
#ifdef HALBB_DIG_TDMA_SUPPORT
DIG_TDMA = 1,
DIG_TDMA_ADV = 2,
#endif
DIG_SIMPLE = 3,
DIG_NONE
};
enum dig_pause_case {
PAUSE_OFDM = 0,
PAUSE_OFDM_CCK = 1
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_dig_mode_update(struct bb_info *bb, enum dig_op_mode mode);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dig_ex.h
|
C
|
agpl-3.0
| 1,668
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
bool halbb_dyn_csi_rsp_rlt_get(struct bb_info *bb){
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
BB_DBG(bb, DBG_DCR, "CSI Rsp Rlt = %d.\n", bf->is_csi_rsp_en);
return bf->is_csi_rsp_en;
}
void halbb_csi_rsp_rlt(struct bb_info *bb, bool en)
{
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
enum dcr_csi_rsp;
bool ret=false;
if (en == bf->is_csi_rsp_en)
return;
bf->is_csi_rsp_en = en;
#if 0
if (en) {
BB_DBG(bb, DBG_DCR,"[Enable CSI Rsp.]\n");
//Enable CSI Rsp.
//val = hal_read8(bb->hal_com, 0xcd80);
//val = val | 0x7;
//hal_write8(bb->hal_com, 0xcd80, val);
//ret = rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, bb->bb_phy_idx);
//return dcr_csi_rsp_dis;
} else {
BB_DBG(bb, DBG_DCR,"[Disable CSI Rsp.]\n");
//Disable CSI Rsp.
//val = hal_read8(bb->hal_com, 0xcd80);
//val = val & ~(0x7);
//hal_write8(bb->hal_com, 0xcd80, val);
//ret = rtw_hal_mac_ax_deinit_bfee(bb->hal_com, bb->bb_phy_idx);
//return dcr_csi_rsp_en;
}
#endif
}
bool halbb_dcr_is_he_connect(struct bb_info *bb) {
struct rtw_phl_stainfo_t *sta;
struct bb_link_info *link = &bb->bb_link_i;
bool rlt = false;
if (!link->is_linked) {
return false;
}
if (!link->is_one_entry_only)
return false;
sta = bb->phl_sta_info[bb->bb_link_i.one_entry_macid];
if (sta && sta->wmode & WLAN_MD_11AX) {
BB_DBG(bb, DBG_DCR, "AX Support!!!!");
rlt = true;
}
return rlt;
}
void halbb_dcr_config_ch_info_he(struct bb_info *bb) {
struct bb_ch_rpt_info *ch_rpt = &bb->bb_ch_rpt_i;
struct bb_ch_info_cr_cfg_info *cfg = &ch_rpt->bb_ch_info_cr_cfg_i;
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw;
if (bf->dcr_bw == bw)
return;
bf->dcr_bw = bw;
BB_DBG(bb, DBG_IC_API, "dcr_bw=%d\n", bf->dcr_bw);
if (bw == CHANNEL_WIDTH_80) {
cfg->ch_i_grp_num_he = 3;
} else if (bw == CHANNEL_WIDTH_40) {
cfg->ch_i_grp_num_he = 2;
} else { /*if (bw == CHANNEL_WIDTH_20)*/
if (bb->ic_type == BB_RTL8852B)
cfg->ch_i_grp_num_he = 1;
else
cfg->ch_i_grp_num_he = 2;
}
BB_DBG(bb, DBG_IC_API, "grp_num_he=%d\n", cfg->ch_i_grp_num_he);
cfg->ch_i_cmprs = 1;
cfg->ch_i_ele_bitmap = 0x303; /*Nr X Nc: 2 X 2*/
halbb_cfg_ch_info_cr(bb, cfg);
}
bool halbb_dcr_get_ch_raw_info(struct bb_info *bb, bool is_csi_en)
{
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
struct bb_ch_info_physts_info *ch_physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i;
bool get_ch_rpt_success = false;
if (is_csi_en) {
BB_DBG(bb, DBG_DCR, "CSI Rsp enable need to disable for CH Est.\n");
/* Disable CSI Rsp*/
rtw_hal_mac_ax_deinit_bfee(bb->hal_com, bb->bb_phy_idx);
halbb_delay_ms(bb, bf->ch_est_dly);
}
get_ch_rpt_success = halbb_ch_info_wait_from_physts(bb, bf->get_phy_sts_dly, bf->get_phy_sts_dly, HE_PKT);
if (get_ch_rpt_success && ch_physts->ch_info_len < 200)
get_ch_rpt_success = false;
if (is_csi_en) {
BB_DBG(bb, DBG_DCR, "Restore CSI Rsp.\n");
/* enable CSI Rsp*/
rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, bb->bb_phy_idx);
}
return get_ch_rpt_success;
}
bool halbb_dcr_en(struct bb_info *bb, bool en){
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
bool ret = true;
u32 id = bb->phl_com->id.id & 0xFFFF;
if (id == 0x209 || id == 0x309) {
BB_DBG(bb, DBG_DCR, "DCR_en=%d, cid=0x%x\n", en, id);
} else {
return false;
}
if (en) {
//Allocate Buffer
ret = halbb_ch_info_buf_alloc(bb);
if (ret) {
bf->dyn_csi_rsp_en = true;
}
} else {
halbb_ch_info_buf_rls(bb);
halbb_dcr_reset(bb);
bf->dyn_csi_rsp_en = false;
}
return ret;
}
void halbb_dcr_init(struct bb_info *bb)
{
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
BB_DBG(bb, DBG_DCR, "%s\n", __func__);
bf->dyn_csi_rsp_en = false;
bf->is_csi_rsp_en = true;
bf->ch_est_dly= 50;
bf->get_phy_sts_dly = 5;
bf->max_est_tone_num = 54;
bf->ch_chk_cnt = 0;
bf->dyn_csi_rsp_dbg_en = 0;
bf->dcr_bw = CHANNEL_WIDTH_MAX;
}
void halbb_dcr_reset(struct bb_info *bb)
{
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
bf->ch_chk_cnt = 0;
bf->is_csi_rsp_en = true;
}
bool halbb_dcr_abort(struct bb_info *bb)
{
struct bb_link_info *link = &bb->bb_link_i;
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
if (!bf->dyn_csi_rsp_en) {
BB_DBG(bb, DBG_DCR,"[Dyn CSI RSP DISABLE]\n");
halbb_csi_rsp_rlt(bb, true);
return true;
}
if (!link->is_one_entry_only) {
BB_DBG(bb, DBG_DCR,"[is_one_entry_only = 0]\n");
halbb_csi_rsp_rlt(bb, true);
return true;
}
if (!link->is_linked) {
if (link->first_disconnect)
halbb_dcr_reset(bb);
return true;
}
if(bf->dyn_csi_rsp_dbg_en == 1){
BB_DBG(bb, DBG_DCR,"[Disable by echo cmd for dbg]\n");
halbb_csi_rsp_rlt(bb, true);
return true;
}
if (!halbb_dcr_is_he_connect(bb)) {
//Disable if not HE Mode
BB_DBG(bb, DBG_DCR, "DCR disable cause not in HE mode!\n");
halbb_csi_rsp_rlt(bb, true);
return true;
}
return false;
}
bool halbb_dcr_ch_est(struct bb_info *bb, u16 *addr)
{
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
u32 ix;
u32 h11h22, h12h21, chdiff;
s32 utility = 0;
bool iscablelink = false;
for (ix = 0; ix < bf->max_est_tone_num; ix++) {
#if 0
BB_DBG(bb, DBG_DCR,"Tone Group Idx = %d\n",ix);
BB_DBG(bb, DBG_DCR,"H11 = %s%d.%d + %sj%d.%d",
((addr[ix*8+0] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+0]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+0]) & 0xfff, 12),
((addr[ix*8+1] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+1]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+1]) & 0xfff, 12));
BB_DBG(bb, DBG_DCR,"H22 = %s%d.%d + %sj%d.%d",
((addr[ix*8+6] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+6]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+6]) & 0xfff, 12),
((addr[ix*8+7] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+7]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+7]) & 0xfff, 12));
BB_DBG(bb, DBG_DCR,"H12 = %s%d.%d + %sj%d.%d",
((addr[ix*8+2] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+2]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+2]) & 0xfff, 12),
((addr[ix*8+3] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+3]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+3]) & 0xfff, 12));
BB_DBG(bb, DBG_DCR,"H21 = %s%d.%d + %sj%d.%d",
((addr[ix*8+4] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+4]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+4]) & 0xfff, 12),
((addr[ix*8+4] & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(addr[ix*8+5]) >> 12),
halbb_show_fraction_num((u16)ABS_16(addr[ix*8+5]) & 0xfff, 12));
#endif
h11h22 = ((u16)ABS_16(addr[ix*8+0]))+((u16)ABS_16(addr[ix*8+1]))
+((u16)ABS_16(addr[ix*8+6]))+((u16)ABS_16(addr[ix*8+7]));
h12h21 =((u16)ABS_16(addr[ix*8+2]))+((u16)ABS_16(addr[ix*8+3]))
+((u16)ABS_16(addr[ix*8+4]))+((u16)ABS_16(addr[ix*8+5]));
if (h11h22 != 0 && h12h21 != 0) {
chdiff = DIFF_2(h11h22, h12h21);
//BB_DBG(bb, DBG_DCR, "H11H22 = %d, H12H22= %d ,Diff= %d\n", h11h22, h12h21, chdiff);
if (chdiff > 10000)
utility += 2;
else if (chdiff > 5000)
utility += 1;
else
utility -= 2;
}
}
if (utility > 0)
iscablelink = true;
BB_DBG(bb, DBG_DCR, "utility = %d, isCableLink = %d\n",
utility, iscablelink);
return iscablelink;
}
void halbb_dyn_csi_rsp_main(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_su_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_su_i;
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i;
struct bb_ch_info_physts_info *physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i;
u16 pkt_cnt_ss = 0;
//u8 i = 0, j =0;
//u8 rate_num = bb->num_rf_path, ss_ofst = 0;
u8 ret = dcr_csi_rsp_en;
bool iscablelink = false, is_csi_rsp_en = true;
if (halbb_dcr_abort(bb))
return;
#if 1
if (pkt_cnt->he_pkt_not_zero) {
halbb_dcr_config_ch_info_he(bb);
pkt_cnt_ss = pkt_cnt->pkt_cnt_t;
}
#else
//Cal HE RX PKT CNT
for (i = 0; i < rate_num; i++) {
ss_ofst = HE_VHT_NUM_MCS * i;
for (j = 0; j < HE_VHT_NUM_MCS ; j++) {
pkt_cnt_ss += pkt_cnt->pkt_cnt_he[ss_ofst + j];
}
}
#endif
BB_DBG(bb, DBG_DCR,"[CH Est. dly = %d,Get Physts dly = %d, rpt get = %d, CH chk cnt =%d, HE Pkt=%03d]\n",
bf->ch_est_dly, bf->get_phy_sts_dly, physts->ch_info_state,
bf->ch_chk_cnt, pkt_cnt_ss);
if ((bf->ch_chk_cnt >= 3) && (pkt_cnt_ss > 400)) {
BB_DBG(bb, DBG_DCR,"[No Need to Chk Ch and Rx Cnt > 400]\n");
halbb_csi_rsp_rlt(bb, true);
return;
}
if (!halbb_dcr_get_ch_raw_info(bb, bf->is_csi_rsp_en)) { /*get report fail*/
BB_DBG(bb, DBG_DCR,"[Failed To Get Report]\n");
if (bf->ch_chk_cnt > 0)
bf->ch_chk_cnt--;
//halbb_csi_rsp_rlt(bb, true);
return;
}
//CSI RAW INFO Get
BB_DBG(bb, DBG_DCR,"[Rpt Get !!!]\n");
if (bf->ch_chk_cnt >= 3) {
BB_DBG(bb, DBG_DCR,"[No Need to Check Channel]\n");
halbb_csi_rsp_rlt(bb, true);
return;
}
//check if cable link
iscablelink = halbb_dcr_ch_est(bb, buf->octet);
halbb_mem_set(bb, buf->octet, 0, buf->ch_info_buf_len);
if (iscablelink) {
BB_DBG(bb, DBG_DCR,"[CSI Rsp. Disable !!!]\n");
is_csi_rsp_en = false;
if (bf->ch_chk_cnt > 0)
bf->ch_chk_cnt--;
ret = dcr_csi_rsp_dis;
} else {
BB_DBG(bb, DBG_DCR,"[CSI Rsp. Enable !!!]\n");
is_csi_rsp_en = true;
if (bf->ch_chk_cnt < 3)
bf->ch_chk_cnt++;
ret = dcr_csi_rsp_en;
}
halbb_csi_rsp_rlt(bb, is_csi_rsp_en);
}
void halbb_dyn_csi_rsp_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len)
{
struct bb_ch_info_physts_info *physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i;
struct bf_ch_raw_info *bf = &bb->bb_cmn_hooker->bf_ch_raw_i;
u32 val[10] = {0};
bool dcr_en = false;
bool bool_tmp;
HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{0: Config Channel Est Delay Unit:ms\n");
} else if (val[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
if (val[1] == 1){
bf->dyn_csi_rsp_dbg_en = 0;
} else {
bf->dyn_csi_rsp_dbg_en = 1;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "Dynamic CSI Rsp Enable = %d\n",
bf->dyn_csi_rsp_dbg_en);
} else if (val[0] == 2) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "Config Trainning Delay \n");
bf->ch_est_dly = (u32)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "Trainning Delay = %d ms \n",
bf->ch_est_dly);
} else if (val[0] == 3) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "Config Get PHY STS Delay \n");
bf->get_phy_sts_dly = (u32)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "GetPhySTS = %d ms \n",
bf->get_phy_sts_dly);
} else if (val[0] == 4) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "Config Max Tone Cnt \n");
bf->max_est_tone_num = (u32)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "Config Max Tone Cnt = %d \n",
bf->max_est_tone_num);
} else if (val[0] == 5) {
bool_tmp = halbb_dcr_is_he_connect(bb);
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used, "is_he_connect=%d\n", bool_tmp);
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.c
|
C
|
agpl-3.0
| 12,754
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_CSI_RSP_H__
#define __HALBB_DYN_CSI_RSP_H__
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
struct bf_ch_raw_info {
/*result*/
bool is_csi_rsp_en;
/*state machine*/
u8 dyn_csi_rsp_dbg_en;
u8 dyn_csi_rsp_en;
u8 ch_chk_cnt;
/*set val*/
u32 ch_est_dly;
u32 get_phy_sts_dly;
u32 max_est_tone_num;
s32 cablelink_cnt_th;
enum channel_width dcr_bw;
};
struct bb_info;
/*@--------------------------[Enum]------------------------------------------*/
enum dcr_csi_rsp {
dcr_csi_rsp_dis = 0, /*Disale*/
dcr_csi_rsp_en = 1, /*Enable*/
};
void halbb_dcr_init(struct bb_info *bb);
void halbb_dcr_reset(struct bb_info *bb);
void halbb_dyn_csi_rsp_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
void halbb_dyn_csi_rsp_main(struct bb_info *bb);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dyn_csi_rsp.h
|
C
|
agpl-3.0
| 1,801
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_CSI_RSP_EX_H__
#define __HALBB_DYN_CSI_RSP_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
bool halbb_dcr_en(struct bb_info *bb, bool en);
bool halbb_dyn_csi_rsp_rlt_get(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_dyn_csi_rsp_ex.h
|
C
|
agpl-3.0
| 1,471
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_EDCCA_SUPPORT
bool halbb_edcca_abort(struct bb_info *bb)
{
if (!(bb->support_ability & BB_EDCCA)) {
BB_DBG(bb, DBG_EDCCA, "edcca disable\n");
return true;
}
if (bb->pause_ability & BB_EDCCA) {
BB_DBG(bb, DBG_EDCCA, "Return edcca pause\n");
return true;
}
return false;
}
void halbb_set_edcca_thre(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i;
u32 l2h = bb_edcca->th_h;
halbb_set_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m, l2h);
halbb_set_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m, l2h);
halbb_set_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m, (u32)bb_edcca->th_hl_diff);
}
u8 halbb_edcca_thre_transfer_rssi(struct bb_info *bb)
{
u8 rssi_min = bb->bb_ch_i.rssi_min >> 1;
u8 edcca_thre = 0;
/*mapping between rssi and edcca thre */
edcca_thre = rssi_min -110 + 128;
if (edcca_thre <= EDCCA_TH_L2H_LB)
edcca_thre = EDCCA_TH_L2H_LB;
return edcca_thre;
}
void halbb_edcca_thre_calc(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
u8 band = bb->hal_com->band[0].cur_chandef.band;
u8 th_h = 0;
BB_DBG(bb, DBG_EDCCA, "[EDCCA] Mode=%d, Band=%d\n",
bb_edcca->edcca_mode, band);
BB_DBG(bb, DBG_EDCCA,
"[EDCCA] Adapt-5G_th=%d(dBm), Adapt-2.4G_th=%d(dBm),Carrier-sense_th=%d(dBm)\n",
bb_edcca->th_h_5g - 128, bb_edcca->th_h_2p4g - 128,
bb_edcca->th_h_cs - 128);
if (bb_edcca->edcca_mode == EDCCA_NORMAL_MODE) {
BB_DBG(bb, DBG_EDCCA, "Normal Mode without EDCCA\n");
th_h = halbb_edcca_thre_transfer_rssi(bb);
bb_edcca->th_hl_diff = EDCCA_HL_DIFF_NORMAL;
} else if (bb_edcca->edcca_mode == EDCCA_ADAPT_MODE) {
if (band == BAND_ON_24G)
th_h = bb_edcca->th_h_2p4g;
else
th_h = bb_edcca->th_h_5g;
bb_edcca->th_hl_diff = EDCCA_HL_DIFF_ADPTVTY;
} else if (bb_edcca->edcca_mode == EDCCA_CARRIER_SENSE_MODE) {
th_h = bb_edcca->th_h_cs;
bb_edcca->th_hl_diff = EDCCA_HL_DIFF_ADPTVTY;
}
bb_edcca->th_h = th_h;
bb_edcca->th_l = bb_edcca->th_h - bb_edcca->th_hl_diff;
halbb_set_edcca_thre(bb);
}
void halbb_set_edcca_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
if (val_len != 1) {
BB_DBG(bb, DBG_EDCCA, "[Error][EDCCA]Need val_len=1\n");
return;
}
BB_DBG(bb, DBG_EDCCA, "[%s] len=%d, val[0]=0x%x\n", __func__, val_len, val_buf[0]);
bb_edcca->th_h = (u8)val_buf[0];
halbb_set_edcca_thre(bb);
}
void halbb_edcca_event_nofity(struct bb_info *bb, u8 pause_type)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
u8 pause_result = 0;
u32 val[5] = {0};
if (bb_edcca->edcca_mode != EDCCA_NORMAL_MODE)
return;
val[0] = EDCCA_MAX;
pause_result = halbb_pause_func(bb, F_EDCCA, pause_type, HALBB_PAUSE_LV_2, 1, val);
}
void halbb_edcca_log(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct edcca_hw_rpt *rpt = &bb_edcca->edcca_rpt;
struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i;
enum channel_width bw = 0;
u8 edcca_p_th = 0;
u8 edcca_s_th = 0;
u8 edcca_diff = 0;
bool edcca_en = 0;
bw = bb->hal_com->band[0].cur_chandef.bw;
switch (bw) {
case CHANNEL_WIDTH_80_80:
case CHANNEL_WIDTH_160:
BB_DBG(bb, DBG_EDCCA,
"pwdb per20{0,1,2,3,4,5,6,7}={%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2, rpt->pwdb_3,
rpt->pwdb_4, rpt->pwdb_5, rpt->pwdb_6, rpt->pwdb_7);
BB_DBG(bb, DBG_EDCCA,
"path=%d, flag {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20, rpt->flag_s20,
rpt->flag_s40, rpt->flag_s80);
BB_DBG(bb, DBG_EDCCA,
"pwdb {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20, rpt->pwdb_s20, rpt->pwdb_s40,
rpt->pwdb_s80);
break;
case CHANNEL_WIDTH_80:
BB_DBG(bb, DBG_EDCCA,
"pwdb per20{0,1,2,3}={%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2, rpt->pwdb_3);
BB_DBG(bb, DBG_EDCCA, "path=%d, flag {FB,p20,s20,s40}={%d,%d,%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20, rpt->flag_s20,
rpt->flag_s40);
BB_DBG(bb, DBG_EDCCA,
"pwdb {FB,p20,s20,s40}={%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20, rpt->pwdb_s20, rpt->pwdb_s40);
break;
case CHANNEL_WIDTH_40:
BB_DBG(bb, DBG_EDCCA, "pwdb per20{0,1}={%d,%d}(dBm)\n", rpt->pwdb_0,
rpt->pwdb_1);
BB_DBG(bb, DBG_EDCCA, "path=%d, flag {FB,p20,s20}={%d,%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20, rpt->flag_s20);
BB_DBG(bb, DBG_EDCCA, "pwdb {FB,p20,s20}={%d,%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20, rpt->pwdb_s20);
break;
case CHANNEL_WIDTH_20:
BB_DBG(bb, DBG_EDCCA, "pwdb per20{0}={%d}(dBm)\n", rpt->pwdb_0);
BB_DBG(bb, DBG_EDCCA, "path=%d, flag {FB,p20}={%d,%d}\n", rpt->path,
rpt->flag_fb, rpt->flag_p20);
BB_DBG(bb, DBG_EDCCA, "pwdb {FB,p20}={%d,%d}(dBm)\n", rpt->pwdb_fb,
rpt->pwdb_p20);
break;
default:
break;
}
edcca_en = (bool)halbb_get_reg(bb, cr->r_snd_en, cr->r_snd_en_m);
edcca_p_th = (u8)halbb_get_reg(bb, cr->r_edcca_level_p, cr->r_edcca_level_p_m);
edcca_s_th = (u8)halbb_get_reg(bb, cr->r_edcca_level, cr->r_edcca_level_m);
edcca_diff = (u8)halbb_get_reg(bb, cr->r_dwn_level, cr->r_dwn_level_m);
BB_DBG(bb, DBG_EDCCA,
"reg val{en, p20_h_th, sec_h_th, diff}:{%d, %d, %d, %d}\n",
edcca_en, edcca_p_th, edcca_s_th, edcca_diff);
}
void halbb_edcca_get_result(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct edcca_hw_rpt *rpt = &bb_edcca->edcca_rpt;
struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i;
u32 tmp = 0;
u64 tmp_linear = 0;
enum channel_width bw = 0;
bw = bb->hal_com->band[0].cur_chandef.bw;
halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m, 0x0);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m);
rpt->pwdb_1 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
rpt->pwdb_0 = (s8)(((tmp & MASKBYTE3) >> 24) - 256);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_b, cr->r_edcca_rpt_b_m);
rpt->path = (u8)((tmp & 0x6) >> 1);
rpt->flag_s80 = (bool)((tmp & BIT(3)) >> 3);
rpt->flag_s40 = (bool)((tmp & BIT(4)) >> 4);
rpt->flag_s20 = (bool)((tmp & BIT(5)) >> 5);
rpt->flag_p20 = (bool)((tmp & BIT(6)) >> 6);
rpt->flag_fb = (bool)((tmp & BIT(7)) >> 7);
rpt->pwdb_s20 = (s8)(((tmp & MASKBYTE1) >> 8) - 256);
rpt->pwdb_p20 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
rpt->pwdb_fb = (s8)(((tmp & MASKBYTE3) >> 24) - 256);
switch (bw) {
case CHANNEL_WIDTH_80_80:
case CHANNEL_WIDTH_160:
halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m,
0x5);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m);
rpt->pwdb_3 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
rpt->pwdb_2 = (s8)(((tmp & MASKBYTE3) >> 24) - 256);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_b, cr->r_edcca_rpt_b_m);
rpt->pwdb_s80 = (s8)(((tmp & MASKBYTE1) >> 8) - 256);
rpt->pwdb_s40 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m,
0x2);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m);
rpt->pwdb_5 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
rpt->pwdb_4 = (s8)(((tmp & MASKBYTE3) >> 24) - 256);
halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m,
0x3);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m);
rpt->pwdb_7 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
rpt->pwdb_6 = (s8)(((tmp & MASKBYTE3) >> 24) - 256);
break;
case CHANNEL_WIDTH_80:
halbb_set_reg(bb, cr->r_edcca_rpt_sel, cr->r_edcca_rpt_sel_m,
0x5);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_a, cr->r_edcca_rpt_a_m);
rpt->pwdb_3 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
rpt->pwdb_2 = (s8)(((tmp & MASKBYTE3) >> 24) - 256);
tmp = halbb_get_reg(bb, cr->r_edcca_rpt_b, cr->r_edcca_rpt_b_m);
rpt->pwdb_s80 = (s8)(((tmp & MASKBYTE1) >> 8) - 256);
rpt->pwdb_s40 = (s8)(((tmp & MASKBYTE2) >> 16) - 256);
break;
case CHANNEL_WIDTH_40:
/*52A/52B/52C has hw bug of pwdb-FB is 0 when bw=40M*/
if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
if ((rpt->pwdb_p20 == (s8)(EDCCA_PWDB_EXCLU_TX)) ||
(rpt->pwdb_s20 == (s8)(EDCCA_PWDB_EXCLU_TX))) {
rpt->pwdb_fb = (s8)(EDCCA_PWDB_EXCLU_TX);
} else {
tmp = (u32)EDCCA_PWDB_TO_RSSI(rpt->pwdb_p20);
tmp_linear = halbb_db_2_linear(tmp);
tmp = (u32)EDCCA_PWDB_TO_RSSI(rpt->pwdb_s20);
tmp_linear += halbb_db_2_linear(tmp);
tmp_linear = (tmp_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
tmp = halbb_convert_to_db(tmp_linear);
rpt->pwdb_fb = (s8)(tmp - 110);
}
}
break;
default:
break;
}
}
void halbb_edcca(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
if (halbb_edcca_abort(bb))
return;
bb_edcca->edcca_mode = bb->phl_com->edcca_mode;
halbb_edcca_thre_calc(bb);
BB_DBG(bb, DBG_EDCCA, "th_h=%d(dBm), th_l=%d(dBm)\n",
bb_edcca->th_h - 128, bb_edcca->th_l - 128);
halbb_edcca_get_result(bb);
halbb_edcca_log(bb);
}
void halbb_fw_edcca(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct rtw_phl_com_t *phl = bb->phl_com;
struct rtw_hal_com_t *hal = bb->hal_com;
u8 band = bb->hal_com->band[0].cur_chandef.band;
struct bb_h2c_fw_edcca *fw_edcca_i = &bb->bb_fw_edcca_i;
u8 cmdlen;
bool ret_val = false;
u32 *bb_h2c = (u32 *)fw_edcca_i;
cmdlen = sizeof(struct bb_h2c_fw_edcca);
bb_edcca->edcca_mode = phl->edcca_mode;
//bb_edcca->edcca_mode = EDCCA_ADAPT_MODE;
if (halbb_edcca_abort(bb))
return;
/* FW workaround only for 8852A CAV */
if (!((hal->cv == CAV) && (hal->chip_id == CHIP_WIFI6_8852A)))
return;
if (bb_edcca->edcca_mode == EDCCA_NORMAL_MODE) {
BB_DBG(bb, DBG_EDCCA, "Normal Mode without FW EDCCA\n");
return;
}
BB_DBG(bb, DBG_EDCCA, "FW EDCCA start\n");
fw_edcca_i->mode = bb_edcca->edcca_mode;
fw_edcca_i->band = bb->hal_com->band[0].cur_chandef.band;
BB_DBG(bb, DBG_EDCCA, "[EDCCA] Mode=%d, Band=%d\n",
fw_edcca_i->mode, fw_edcca_i->band);
BB_DBG(bb, DBG_EDCCA, "[EDCCA] Adapt-5G_th=-%d, Adapt-2.4G_th=-%d,Carrier-sense_th=-%d\n",
fw_edcca_i->pwr_th_5g, fw_edcca_i->pwr_th_2p4,
fw_edcca_i->pwr_th_cs);
BB_DBG(bb, DBG_FW_INFO, "[FW][H2C] h2c conent[0]=%x\n", bb_h2c[0]);
BB_DBG(bb, DBG_FW_INFO, "[FW][H2C] h2c conent[1]=%x\n", bb_h2c[1]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_EDCCA,
HALBB_H2C_DM, bb_h2c);
if (ret_val == false)
BB_WARNING(" H2C cmd: FW Tx error!!\n");
}
void halbb_edcca_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct edcca_hw_rpt *rpt = &bb_edcca->edcca_rpt;
struct bb_h2c_fw_edcca *fw_edcca_i = &bb->bb_fw_edcca_i;
enum channel_width bw = 0;
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
bw = bb->hal_com->band[0].cur_chandef.bw;
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[EDCCA] Set power threshold(-dBm): {1} {Adapt-5G_th} {Adapt-2.4G_th} {Carrier-sense_th}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[FW EDCCA][8852A CAV] Set power threshold(-dBm): {2} {Adapt-5G_th} {Adapt-2.4G_th} {Carrier-sense_th}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[EDCCA] Set EDCCA mode: {3} {mode 0:normal mode, 1:Adaptivity, 2: Carrier sense}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Show Power threshold: {100}\n");
} else {
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if (var[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]);
bb_edcca->th_h_5g = (u8)var[1];
bb_edcca->th_h_2p4g = (u8)var[2];
bb_edcca->th_h_cs = (u8)var[3];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Adapt-5G_th=-%d(dBm), Adapt-2.4G_th=-%d(dBm), Carrier-sense_th=-%d(dBm)\n",
bb_edcca->th_h_5g, bb_edcca->th_h_2p4g,
bb_edcca->th_h_cs);
bb_edcca->th_h_5g = 0 - (bb_edcca->th_h_5g) + 128;
bb_edcca->th_h_2p4g = 0 - (bb_edcca->th_h_2p4g) + 128;
bb_edcca->th_h_cs = 0 - (bb_edcca->th_h_cs) + 128;
} else if (var[0] == 2) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[3]);
fw_edcca_i->pwr_th_5g = (u8)var[1];
fw_edcca_i->pwr_th_2p4 = (u8)var[2];
fw_edcca_i->pwr_th_cs = (u8)var[3];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set FW Adapt-5G_th=-%d, Adapt-2.4G_th=-%d, Carrier-sense_th=-%d\n",
fw_edcca_i->pwr_th_5g, fw_edcca_i->pwr_th_2p4,
fw_edcca_i->pwr_th_cs);
halbb_fw_edcca(bb);
} else if (var[0] == 3) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
bb_edcca->edcca_mode = (u8)var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set FW EDCCA mode = %s\n", (bb_edcca->edcca_mode == EDCCA_NORMAL_MODE) ? "Normal mode" : "Adaptivity/Carrier Sense mode");
halbb_fw_edcca(bb);
} else if (var[0] == 100) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adapt-5G_th=%d(dBm), Adapt-2.4G_th=%d(dBm), Carrier-sense_th=%d(dBm)\n",
bb_edcca->th_h_5g - 128,
bb_edcca->th_h_2p4g -128,
bb_edcca->th_h_cs - 128);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Mode=%d, th_h=%d(dBm), th_l=%d(dBm)\n",
bb_edcca->edcca_mode, bb_edcca->th_h - 128,
bb_edcca->th_l - 128);
halbb_edcca_get_result(bb);
switch (bw) {
case CHANNEL_WIDTH_80_80:
case CHANNEL_WIDTH_160:
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb per20{0,1,2,3,4,5,6,7}={%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2,
rpt->pwdb_3, rpt->pwdb_4, rpt->pwdb_5,
rpt->pwdb_6, rpt->pwdb_7);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"path-%d, flag {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20,
rpt->flag_s20, rpt->flag_s40,
rpt->flag_s80);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb {FB,p20,s20,s40,s80}={%d,%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20,
rpt->pwdb_s20, rpt->pwdb_s40,
rpt->pwdb_s80);
break;
case CHANNEL_WIDTH_80:
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb per20{0,1,2,3}={%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_0, rpt->pwdb_1, rpt->pwdb_2,
rpt->pwdb_3);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"path-%d, flag {FB,p20,s20,s40}={%d,%d,%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20,
rpt->flag_s20, rpt->flag_s40);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb {FB,p20,s20,s40}={%d,%d,%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20,
rpt->pwdb_s20, rpt->pwdb_s40);
break;
case CHANNEL_WIDTH_40:
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb per20{0,1}={%d,%d}(dBm)\n",
rpt->pwdb_0, rpt->pwdb_1);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"path-%d, flag {FB,p20,s20}={%d,%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20,
rpt->flag_s20);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb {FB,p20,s20}={%d,%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20,
rpt->pwdb_s20);
break;
case CHANNEL_WIDTH_20:
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb per20{0}={%d}(dBm)\n",
rpt->pwdb_0);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"path-%d, flag {FB,p20}={%d,%d}\n",
rpt->path, rpt->flag_fb, rpt->flag_p20);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"pwdb {FB,p20}={%d,%d}(dBm)\n",
rpt->pwdb_fb, rpt->pwdb_p20);
break;
default:
break;
}
#ifdef BB_8852A_52AA_CUT_SUPPORT
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"FW Adapt-5G_th=-%d, Adapt-2.4G_th=-%d, Carrier-sense_th=-%d\n",
fw_edcca_i->pwr_th_5g, fw_edcca_i->pwr_th_2p4,
fw_edcca_i->pwr_th_cs);
#endif
}
}
*_used = used;
*_out_len = out_len;
}
void halbb_edcca_dev_hw_cap(struct bb_info *bb)
{
struct rtw_hal_com_t *hal = bb->hal_com;
hal->dev_hw_cap.edcca_cap.edcca_adap_th_5g = EDCCA_5G;
hal->dev_hw_cap.edcca_cap.edcca_adap_th_2g = EDCCA_2G;
if (bb->ic_type == BB_RTL8852B) /*[HALBB-126] for SingleTone shift 1MHz*/
hal->dev_hw_cap.edcca_cap.edcca_carrier_sense_th = CARRIER_SENSE - 6;
else
hal->dev_hw_cap.edcca_cap.edcca_carrier_sense_th = CARRIER_SENSE;
}
void halbb_edcca_init(struct bb_info *bb)
{
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct bb_h2c_fw_edcca *fw_edcca_i = &bb->bb_fw_edcca_i;
struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i;
struct rtw_phl_com_t *phl = bb->phl_com;
if(phl_is_mp_mode(bb->phl_com))
return;
bb_edcca->edcca_mode = phl->edcca_mode;
bb_edcca->th_h = EDCCA_MAX;
bb_edcca->th_l = EDCCA_MAX;
bb_edcca->th_h_lb = 46;
// EDCCA
bb_edcca->th_h_5g = phl->dev_cap.edcca_cap.edcca_adap_th_5g;
bb_edcca->th_h_2p4g = phl->dev_cap.edcca_cap.edcca_adap_th_2g;
bb_edcca->th_h_cs = phl->dev_cap.edcca_cap.edcca_carrier_sense_th;
// FW EDCCA
fw_edcca_i->pwr_th_5g = EDCCA_5G_TH;
fw_edcca_i->pwr_th_2p4 = EDCCA_2p4G_TH;
fw_edcca_i->pwr_th_cs = CARRIER_SENSE_TH;
}
void halbb_cr_cfg_edcca_init(struct bb_info *bb)
{
struct bb_edcca_cr_info *cr = &bb->bb_edcca_i.bb_edcca_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_52AA_CUT_SUPPORT
case BB_52AA:
cr->r_snd_en = SEG0R_SND_EN_52AA;
cr->r_snd_en_m = SEG0R_SND_EN_52AA_M;
cr->r_dwn_level = SEG0R_DWN_LVL_52AA;
cr->r_dwn_level_m = SEG0R_DWN_LVL_52AA_M;
cr->r_edcca_level = SEG0R_EDCCA_LVL_52AA;
cr->r_edcca_level_m = SEG0R_EDCCA_LVL_52AA_M;
cr->r_edcca_level_p = SEG0R_EDCCA_LVL_P_52AA;
cr->r_edcca_level_p_m = SEG0R_EDCCA_LVL_P_52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->r_snd_en = SEG0R_SND_EN_A;
cr->r_snd_en_m = SEG0R_SND_EN_A_M;
cr->r_dwn_level = SEG0R_DWN_LVL_A;
cr->r_dwn_level_m = SEG0R_DWN_LVL_A_M;
cr->r_edcca_level = SEG0R_EDCCA_LVL_A;
cr->r_edcca_level_m = SEG0R_EDCCA_LVL_A_M;
cr->r_edcca_level_p = SEG0R_EDCCA_LVL_P_A;
cr->r_edcca_level_p_m = SEG0R_EDCCA_LVL_P_A_M;
cr->r_edcca_rpt_a = EDCCA_IOQ_P0_A_A;
cr->r_edcca_rpt_a_m = EDCCA_IOQ_P0_A_A_M;
cr->r_edcca_rpt_b = EDCCA_IOQ_P0_B_A;
cr->r_edcca_rpt_b_m = EDCCA_IOQ_P0_B_A_M;
cr->r_edcca_rpt_sel = EDCCA_RPTREG_SEL_P0_A;
cr->r_edcca_rpt_sel_m = EDCCA_RPTREG_SEL_P0_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->r_snd_en = SEG0R_SND_EN_C;
cr->r_snd_en_m = SEG0R_SND_EN_C_M;
cr->r_dwn_level = SEG0R_DWN_LVL_C;
cr->r_dwn_level_m = SEG0R_DWN_LVL_C_M;
cr->r_edcca_level = SEG0R_EDCCA_LVL_C;
cr->r_edcca_level_m = SEG0R_EDCCA_LVL_C_M;
cr->r_edcca_level_p = SEG0R_EDCCA_LVL_P_C;
cr->r_edcca_level_p_m = SEG0R_EDCCA_LVL_P_C_M;
cr->r_edcca_rpt_a = EDCCA_IOQ_P0_A_C;
cr->r_edcca_rpt_a_m = EDCCA_IOQ_P0_A_C_M;
cr->r_edcca_rpt_b = EDCCA_IOQ_P0_B_C;
cr->r_edcca_rpt_b_m = EDCCA_IOQ_P0_B_C_M;
cr->r_edcca_rpt_sel = EDCCA_RPTREG_SEL_P0_C;
cr->r_edcca_rpt_sel_m = EDCCA_RPTREG_SEL_P0_C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_edcca.c
|
C
|
agpl-3.0
| 20,780
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EDCCA_H__
#define __HALBB_EDCCA_H__
/*@--------------------------[Define] ---------------------------------------*/
#define EDCCA_HL_DIFF_ADPTVTY 7
#define EDCCA_HL_DIFF_NORMAL 8
// EDCCA
#define EDCCA_5G 63 /*@-62 dBm -3 dB margin*/
#define EDCCA_2G 68 /*@-57 dBm -3 dB margin*/
#define CARRIER_SENSE 75 /*@-50dBm -3 dB margin*/
#define EDCCA_MAX 249 /*@ 127dBm for normal mode*/
#define EDCCA_PWDB_EXCLU_TX 128 /*128 - 256 = -128dBm when Tx*/
#define EDCCA_PWDB_TO_RSSI(pwdb) ((pwdb + 110) < 0 ? 0 : (pwdb + 110))
#define EDCCA_TH_L2H_LB 66 /*@ -62 dBm from IEEE*/
// FW EDCCA
#define EDCCA_5G_TH 70 // -62
#define EDCCA_2p4G_TH 65// -57
#define CARRIER_SENSE_TH 58 // -50
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_h2c_fw_edcca {
u8 mode;
u8 band;
u8 pwr_th_5g;
u8 pwr_th_2p4;
u8 pwr_th_cs;
u8 rsvd0;
u8 rsvd1;
u8 rsvd2;
};
struct bb_edcca_cr_info {
u32 r_snd_en;
u32 r_snd_en_m;
u32 r_dwn_level;
u32 r_dwn_level_m;
u32 r_edcca_level;
u32 r_edcca_level_m;
u32 r_edcca_level_p;
u32 r_edcca_level_p_m;
u32 r_edcca_rpt_a;
u32 r_edcca_rpt_a_m;
u32 r_edcca_rpt_b;
u32 r_edcca_rpt_b_m;
u32 r_edcca_rpt_sel;
u32 r_edcca_rpt_sel_m;
};
struct edcca_hw_rpt {
s8 pwdb_fb; /*52A/52B is 0 when BW=40, 92XB would fix*/
s8 pwdb_p20;
s8 pwdb_s20;
s8 pwdb_s40;
s8 pwdb_s80;
bool flag_fb;
bool flag_p20;
bool flag_s20;
bool flag_s40;
bool flag_s80;
s8 pwdb_0;
s8 pwdb_1;
s8 pwdb_2;
s8 pwdb_3;
s8 pwdb_4;
s8 pwdb_5;
s8 pwdb_6;
s8 pwdb_7;
s8 pwdb_8;
u8 path;
};
struct bb_edcca_info {
struct bb_edcca_cr_info bb_edcca_cr_i;
u8 th_l;
u8 th_h;
u8 th_hl_diff;
u8 edcca_mode;
u8 th_h_lb;
u8 th_h_5g;
u8 th_h_2p4g;
u8 th_h_cs;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
struct edcca_hw_rpt edcca_rpt;
};
#ifdef HALBB_DYN_L2H_SUPPORT
struct bb_dyn_l2h_info {
bool en_dyn_l2h;
u32 low_rate_rty_cnt;
u32 drop_cnt;
u8 l2h_th;
};
#endif
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_edcca(struct bb_info *bb);
void halbb_edcca_thre_calc(struct bb_info * bb);
void halbb_set_edcca_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
void halbb_edcca_event_nofity(struct bb_info * bb, u8 pause_type);
void halbb_edcca_dev_hw_cap(struct bb_info * bb);
void halbb_edcca_init(struct bb_info *bb);
void halbb_cr_cfg_edcca_init(struct bb_info *bb);
void halbb_edcca_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_edcca.h
|
C
|
agpl-3.0
| 3,776
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EDCCA_EX_H__
#define __HALBB_EDCCA_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_edcca_mode {
EDCCA_NORMAL_MODE = 0,
EDCCA_ADAPT_MODE = 1,
EDCCA_CARRIER_SENSE_MODE = 2,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_fw_edcca(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_edcca_ex.h
|
C
|
agpl-3.0
| 1,515
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_ENV_MNTR_SUPPORT
u16 halbb_ccx_get_ratio(struct bb_info *bb, u16 rpt, u16 score)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u32 numer = 0;
u16 ratio = 0;
u16 ret = 0;
if (rpt == env->ccx_period) {
ret = score;
} else {
numer = rpt * score + (env->ccx_period >> 1);
ratio = (u16)HALBB_DIV(numer, env->ccx_period);
ret = (ratio == score) ? (score - 1) : ratio;
}
return ret;
}
void halbb_ccx_ms_2_period_unit(struct bb_info *bb, u16 time_ms, u32 *period,
u32 *unit_idx)
{
if (time_ms >= 2097)
time_ms = 2097;
if (time_ms < 263)
*unit_idx = CCX_04_US;
else if (time_ms < 525)
*unit_idx = CCX_08_US;
else if (time_ms < 1049)
*unit_idx = CCX_16_US;
else
*unit_idx = CCX_32_US;
*period = (u32)((time_ms * MS_TO_4US_RATIO) >> *unit_idx);
BB_DBG(bb, DBG_ENV_MNTR, "[Trigger Time] period:%d, unit_idx:%d\n",
*period, *unit_idx);
}
u32 halbb_ccx_idx_cnt_2_us(struct bb_info *bb, u16 idx_cnt)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u32 time_us = 0;
time_us = (u32)(idx_cnt << (2 + env->ccx_unit_idx));
return time_us;
}
u16 halbb_ccx_us_2_idx_cnt(struct bb_info *bb, u32 time_us)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u16 idx_cnt = 0;
idx_cnt = (u16)(time_us >> (2 + env->ccx_unit_idx));
return idx_cnt;
}
void halbb_ccx_top_setting_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
env->ccx_manual_ctrl = false;
env->ccx_ongoing = false;
env->ccx_rac_lv = RAC_RELEASE;
env->ccx_rpt_stamp = 0;
env->ccx_period = 0;
env->ccx_unit_idx = CCX_32_US;
env->ccx_trigger_time = 0;
env->ccx_edcca_opt_bw_idx = CCX_EDCCA_BW20_0;
halbb_set_reg_phy0_1(bb, cr->ccx_en, cr->ccx_en_m, 1);
halbb_set_reg_phy0_1(bb, cr->ccx_trig_opt, cr->ccx_trig_opt_m, 1);
halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1);
halbb_set_reg_phy0_1(bb, cr->ccx_edcca_opt, cr->ccx_edcca_opt_m,
CCX_EDCCA_BW20_0);
}
void halbb_ccx_racing_release(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
BB_DBG(bb, DBG_ENV_MNTR, "lv:(%d)->(0)\n", env->ccx_rac_lv);
env->ccx_ongoing = false;
env->ccx_rac_lv = RAC_RELEASE;
env->clm_app = CLM_INIT;
env->nhm_app = NHM_INIT;
env->ifs_clm_app = IFS_CLM_INIT;
env->fahm_app = FAHM_INIT;
env->edcca_clm_app = EDCCA_CLM_INIT;
}
u8 halbb_ccx_racing_ctrl(struct bb_info *bb, enum halbb_racing_lv rac_lv)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 set_result = HALBB_SET_SUCCESS;
if (rac_lv >= RAC_MAX_NUM) {
BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n", rac_lv);
return HALBB_SET_FAIL;
}
BB_DBG(bb, DBG_ENV_MNTR, "ccx_ongoing=%d, lv:(%d)->(%d)\n",
env->ccx_ongoing, env->ccx_rac_lv, rac_lv);
if (env->ccx_ongoing) {
if (rac_lv <= env->ccx_rac_lv)
set_result = HALBB_SET_FAIL;
else
env->ccx_ongoing = false;
}
if (set_result)
env->ccx_rac_lv = rac_lv;
BB_DBG(bb, DBG_ENV_MNTR, "ccx racing success=%d\n", set_result);
return set_result;
}
void halbb_ccx_trigger(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
/*Due to IFS_CLM clock gating : [HALBB-58]*/
halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 0);
halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 0);
halbb_set_reg_phy0_1(bb, cr->ifs_clm_clr, cr->ifs_clm_clr_m, 1);
halbb_set_reg_phy0_1(bb, cr->ccx_trig, cr->ccx_trig_m, 1);
env->ccx_trigger_time = bb->bb_sys_up_time;
env->ccx_rpt_stamp++;
env->ccx_ongoing = true;
}
void halbb_ccx_edcca_opt_set(struct bb_info *bb, enum ccx_edcca_opt_sc_idx sc)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u8 pri_ch = 0;
u8 central_ch = 0;
enum channel_width bw = 0;
u8 pri_ch_idx = 0;
u8 bw_idx = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
pri_ch = bb->hal_com->band[0].cur_chandef.chan;
central_ch = bb->hal_com->band[0].cur_chandef.center_ch;
bw = bb->hal_com->band[0].cur_chandef.bw;
/*==== [search pri_ch idx] ====*/
if (central_ch <= 14) {
// === 2G === //
switch (bw) {
case CHANNEL_WIDTH_20:
break;
case CHANNEL_WIDTH_40:
pri_ch_idx = pri_ch > central_ch ? 1 : 2;
break;
default:
break;
}
} else {
// === 5G === //
switch (bw) {
case CHANNEL_WIDTH_20:
break;
case CHANNEL_WIDTH_40:
case CHANNEL_WIDTH_80:
if (pri_ch > central_ch)
pri_ch_idx = (pri_ch - central_ch) >> 1;
else
pri_ch_idx = ((central_ch - pri_ch) >> 1) + 1;
break;
default:
break;
}
}
BB_DBG(bb, DBG_ENV_MNTR,
"sc_idx=%d, pri_ch=%d, cen_ch=%d, bw=%d, pri_ch_idx=%d\n", sc,
pri_ch, central_ch, bw, pri_ch_idx);
/*sc_idx => 4|2|1|3*/
/*bw_idx => 0|1|2|3*/
switch (pri_ch_idx) {
case 4: /*p0|s1|s3|s2*/
if (sc == CCX_EDCCA_SEG0_P0)
bw_idx = CCX_EDCCA_BW20_0;
else if (sc == CCX_EDCCA_SEG0_S1)
bw_idx = CCX_EDCCA_BW20_1;
else if (sc == CCX_EDCCA_SEG0_S2)
bw_idx = CCX_EDCCA_BW20_3;
else if (sc == CCX_EDCCA_SEG0_S3)
bw_idx = CCX_EDCCA_BW20_2;
break;
case 2: /*s1|p0|s2|s3*/
if (sc == CCX_EDCCA_SEG0_P0)
bw_idx = CCX_EDCCA_BW20_1;
else if (sc == CCX_EDCCA_SEG0_S1)
bw_idx = CCX_EDCCA_BW20_0;
else if (sc == CCX_EDCCA_SEG0_S2)
bw_idx = CCX_EDCCA_BW20_2;
else if (sc == CCX_EDCCA_SEG0_S3)
bw_idx = CCX_EDCCA_BW20_3;
break;
case 1: /*s3|s2|p0|s1*/
if (sc == CCX_EDCCA_SEG0_P0)
bw_idx = CCX_EDCCA_BW20_2;
else if (sc == CCX_EDCCA_SEG0_S1)
bw_idx = CCX_EDCCA_BW20_3;
else if (sc == CCX_EDCCA_SEG0_S2)
bw_idx = CCX_EDCCA_BW20_1;
else if (sc == CCX_EDCCA_SEG0_S3)
bw_idx = CCX_EDCCA_BW20_0;
break;
case 3: /*s2|s3|s1|p0*/
if (sc == CCX_EDCCA_SEG0_P0)
bw_idx = CCX_EDCCA_BW20_3;
else if (sc == CCX_EDCCA_SEG0_S1)
bw_idx = CCX_EDCCA_BW20_2;
else if (sc == CCX_EDCCA_SEG0_S2)
bw_idx = CCX_EDCCA_BW20_0;
else if (sc == CCX_EDCCA_SEG0_S3)
bw_idx = CCX_EDCCA_BW20_1;
break;
default:
bw_idx = CCX_EDCCA_BW20_0;
break;
}
if (env->ccx_edcca_opt_bw_idx != bw_idx) {
halbb_set_reg_phy0_1(bb, cr->ccx_edcca_opt, cr->ccx_edcca_opt_m,
bw_idx);
BB_DBG(bb, DBG_ENV_MNTR,
"Update EDCCA_OPT_BW_IDX ((%d)) -> ((%d))\n",
env->ccx_edcca_opt_bw_idx, bw_idx);
env->ccx_edcca_opt_bw_idx = bw_idx;
}
}
#ifdef NHM_SUPPORT
void halbb_nhm_cal_wgt(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
for (i = 0; i < NHM_RPT_NUM; i++) {
if (i == 0)
env->nhm_wgt[i] = (u8)(MAX_2(env->nhm_th[i] - 2, 0));
else if (i == (NHM_RPT_NUM - 1))
env->nhm_wgt[i] = (u8)(env->nhm_th[i - 1] + 2);
else
env->nhm_wgt[i] = (u8)((env->nhm_th[i - 1] +
env->nhm_th[i]) >> 1);
}
}
u8 halbb_nhm_cal_wgt_avg(struct bb_info *bb, u8 start_i, u8 end_i, u16 n_sum)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
u32 tmp = 0;
u8 wgt_avg = 0;
u8 nhm_valid = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (n_sum == 0) {
BB_DBG(bb, DBG_ENV_MNTR,
"result_sum = 0, don't need to update\n");
return 0;
} else if (end_i > NHM_RPT_NUM - 1) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING]nhm_end_idx is larger than 11!!\n");
return 0;
}
for (i = start_i; i <= end_i; i++)
tmp += env->nhm_sw_result[i] * env->nhm_wgt[i];
wgt_avg = (u8)(NHM_TH_2_RSSI(HALBB_DIV(tmp, n_sum)));
nhm_valid = (u8)halbb_ccx_get_ratio(bb, n_sum, 100);
BB_DBG(bb, DBG_ENV_MNTR,
"valid: ((%d)) percent, wgt_avg(RSSI)=((%d))\n",
nhm_valid, wgt_avg);
return wgt_avg;
}
u16 halbb_nhm_exclu_noise_figure(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct rtw_hw_band *hw_band = &bb->hal_com->band[bb->bb_phy_idx];
u8 first_idx = 255;
u8 second_idx = 255;
u16 non_noise_f = 0;
u8 i = 0;
non_noise_f = env->nhm_result_sum;
/*search first & second cluster*/
for (i = 0; i < NHM_RPT_NUM; i++) {
if (env->nhm_sw_result[i]) {
if (first_idx == 255) {
first_idx = i;
} else if (second_idx == 255) {
second_idx = i;
break;
}
}
}
/*exclude first cluster under -80dBm, ranging from i ~ i+2 (9dB)*/
for (i = 0; i < 3; i++) {
if (((first_idx + i) < NHM_RPT_NUM) &&
(env->nhm_wgt[first_idx + i] <= NHM_NOISE_F_TH))
non_noise_f -= env->nhm_sw_result[first_idx + i];
}
/*exclude first_idx and second_idx above -80dBm for 52A 2.4G DIG issue*/
if ((bb->ic_type == BB_RTL8852A) &&
(hw_band->cur_chandef.band == BAND_ON_24G)) {
if ((first_idx != 255) &&
(env->nhm_wgt[first_idx] > NHM_NOISE_F_TH))
non_noise_f -= env->nhm_sw_result[first_idx];
if ((second_idx != 255) &&
(env->nhm_wgt[second_idx] > NHM_NOISE_F_TH))
non_noise_f -= env->nhm_sw_result[second_idx];
}
BB_DBG(bb, DBG_ENV_MNTR,
"cal non_noise_f: 1st_i=%d, 2nd_i=%d, non_noise_f=%d\n",
first_idx, second_idx, non_noise_f);
return non_noise_f;
}
void halbb_nhm_get_utility(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_edcca_info *bb_edcca = &bb->bb_edcca_i;
struct edcca_hw_rpt *edcca_r = &bb_edcca->edcca_rpt;
u16 non_noise_f = 0;
u8 i = 0;
halbb_nhm_cal_wgt(bb);
for (i = 0; i < NHM_RPT_NUM; i++) {
if (((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) &&
(i == (NHM_RPT_NUM - 1))) {
env->nhm_sw_result[0] += env->nhm_result[i];
env->nhm_sw_result[i] = 0;
} else {
env->nhm_sw_result[i] = env->nhm_result[i];
}
}
BB_DBG(bb, DBG_ENV_MNTR,
"NHM sw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
env->ccx_rpt_stamp, env->nhm_sw_result[11],
env->nhm_sw_result[10], env->nhm_sw_result[9],
env->nhm_sw_result[8], env->nhm_sw_result[7],
env->nhm_sw_result[6], env->nhm_sw_result[5],
env->nhm_sw_result[4], env->nhm_sw_result[3],
env->nhm_sw_result[2], env->nhm_sw_result[1],
env->nhm_sw_result[0]);
/*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
non_noise_f = halbb_nhm_exclu_noise_figure(bb);
env->nhm_ratio = (u8)halbb_ccx_get_ratio(bb, non_noise_f, 100);
env->nhm_tx_ratio = (u8)halbb_ccx_get_ratio(bb, env->nhm_tx_cnt, 100);
env->nhm_cca_ratio = (u8)halbb_ccx_get_ratio(bb, env->nhm_cca_cnt, 100);
env->nhm_idle_ratio = (u8)halbb_ccx_get_ratio(bb, env->nhm_idle_cnt,
100);
env->nhm_pwr = halbb_nhm_cal_wgt_avg(bb, 0, NHM_RPT_NUM - 1,
env->nhm_result_sum);
if (bb->ic_type == BB_RTL8852A) {
if ((edcca_r->pwdb_fb != (s8)(EDCCA_PWDB_EXCLU_TX)) &&
(EDCCA_PWDB_TO_RSSI(edcca_r->pwdb_fb) <= NHM_WA_PWR))
env->edcca_noise_bg = EDCCA_PWDB_TO_RSSI(edcca_r->pwdb_fb);
BB_DBG(bb, DBG_ENV_MNTR, "edcca_noise_bg, nhm_pwr = {%d, %d}\n",
env->edcca_noise_bg, env->nhm_pwr);
if (env->nhm_pwr <= NHM_WA_PWR)
env->nhm_pwr = env->edcca_noise_bg;
}
for (i = 0; i < NHM_RPT_NUM; i++)
env->nhm_rpt[i] = (u8)halbb_ccx_get_ratio(bb,
env->nhm_sw_result[i], 100);
BB_DBG(bb, DBG_ENV_MNTR, "cnt ratio{cca, tx, idle} = {%d, %d, %d}\n",
env->nhm_cca_ratio, env->nhm_tx_ratio, env->nhm_idle_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "nhm_ratio=%d, nhm_pwr(RSSI)=%d\n",
env->nhm_ratio, env->nhm_pwr);
}
bool halbb_nhm_get_result(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u8 i = 0;
u32 result_sum_tmp = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (!(halbb_get_reg(bb, cr->nhm_rdy, cr->nhm_rdy_m))) {
BB_DBG(bb, DBG_ENV_MNTR, "Get NHM report Fail\n");
return false;
}
env->nhm_result[0] = (u16)halbb_get_reg(bb, cr->nhm_cnt0,
cr->nhm_cnt0_m);
env->nhm_result[1] = (u16)halbb_get_reg(bb, cr->nhm_cnt1,
cr->nhm_cnt1_m);
env->nhm_result[2] = (u16)halbb_get_reg(bb, cr->nhm_cnt2,
cr->nhm_cnt2_m);
env->nhm_result[3] = (u16)halbb_get_reg(bb, cr->nhm_cnt3,
cr->nhm_cnt3_m);
env->nhm_result[4] = (u16)halbb_get_reg(bb, cr->nhm_cnt4,
cr->nhm_cnt4_m);
env->nhm_result[5] = (u16)halbb_get_reg(bb, cr->nhm_cnt5,
cr->nhm_cnt5_m);
env->nhm_result[6] = (u16)halbb_get_reg(bb, cr->nhm_cnt6,
cr->nhm_cnt6_m);
env->nhm_result[7] = (u16)halbb_get_reg(bb, cr->nhm_cnt7,
cr->nhm_cnt7_m);
env->nhm_result[8] = (u16)halbb_get_reg(bb, cr->nhm_cnt8,
cr->nhm_cnt8_m);
env->nhm_result[9] = (u16)halbb_get_reg(bb, cr->nhm_cnt9,
cr->nhm_cnt9_m);
env->nhm_result[10] = (u16)halbb_get_reg(bb, cr->nhm_cnt10,
cr->nhm_cnt10_m);
env->nhm_result[11] = (u16)halbb_get_reg(bb, cr->nhm_cnt11,
cr->nhm_cnt11_m);
for (i = 0; i < NHM_RPT_NUM; i++)
result_sum_tmp += (u32)env->nhm_result[i];
env->nhm_result_sum = (u16)result_sum_tmp;
BB_DBG(bb, DBG_ENV_MNTR, "nhm_result_sum=%d\n", env->nhm_result_sum);
/*Get NHM cnt*/
env->nhm_cca_cnt = (u16)halbb_get_reg(bb, cr->nhm_cca_cnt,
cr->nhm_cca_cnt_m);
env->nhm_tx_cnt = (u16)halbb_get_reg(bb, cr->nhm_tx_cnt,
cr->nhm_tx_cnt_m);
env->nhm_idle_cnt = (u16)halbb_get_reg(bb, cr->nhm_idle_cnt,
cr->nhm_idle_cnt_m);
BB_DBG(bb, DBG_ENV_MNTR, "cnt{cca, tx, idle} = {%d, %d, %d}\n",
env->nhm_cca_cnt, env->nhm_tx_cnt, env->nhm_idle_cnt);
BB_DBG(bb, DBG_ENV_MNTR,
"NHM hw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
env->ccx_rpt_stamp, env->nhm_result[11], env->nhm_result[10],
env->nhm_result[9], env->nhm_result[8], env->nhm_result[7],
env->nhm_result[6], env->nhm_result[5], env->nhm_result[4],
env->nhm_result[3], env->nhm_result[2], env->nhm_result[1],
env->nhm_result[0]);
halbb_nhm_get_utility(bb);
return true;
}
void halbb_nhm_set_th_reg(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
/*Set NHM threshold*/ /*Unit: RSSI U(8,1)*/
halbb_set_reg_phy0_1(bb, cr->nhm_th0, cr->nhm_th0_m, env->nhm_th[0]);
halbb_set_reg_phy0_1(bb, cr->nhm_th1, cr->nhm_th1_m, env->nhm_th[1]);
halbb_set_reg_phy0_1(bb, cr->nhm_th2, cr->nhm_th2_m, env->nhm_th[2]);
halbb_set_reg_phy0_1(bb, cr->nhm_th3, cr->nhm_th3_m, env->nhm_th[3]);
halbb_set_reg_phy0_1(bb, cr->nhm_th4, cr->nhm_th4_m, env->nhm_th[4]);
halbb_set_reg_phy0_1(bb, cr->nhm_th5, cr->nhm_th5_m, env->nhm_th[5]);
halbb_set_reg_phy0_1(bb, cr->nhm_th6, cr->nhm_th6_m, env->nhm_th[6]);
halbb_set_reg_phy0_1(bb, cr->nhm_th7, cr->nhm_th7_m, env->nhm_th[7]);
halbb_set_reg_phy0_1(bb, cr->nhm_th8, cr->nhm_th8_m, env->nhm_th[8]);
halbb_set_reg_phy0_1(bb, cr->nhm_th9, cr->nhm_th9_m, env->nhm_th[9]);
halbb_set_reg_phy0_1(bb, cr->nhm_th10, cr->nhm_th10_m, env->nhm_th[10]);
BB_DBG(bb, DBG_ENV_MNTR,
"Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n",
env->nhm_th[10], env->nhm_th[9], env->nhm_th[8], env->nhm_th[7],
env->nhm_th[6], env->nhm_th[5], env->nhm_th[4], env->nhm_th[3],
env->nhm_th[2], env->nhm_th[1], env->nhm_th[0]);
}
bool
halbb_nhm_th_update_chk(struct bb_info *bb, struct ccx_para_info *para,
u8 *nhm_th)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
bool is_app_change = (env->nhm_app == para->nhm_app) ? false : true;
bool is_update = is_app_change;
u8 nhm_th_11k[NHM_TH_NUM] = {18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60}; /*Unit RSSI*/
u8 i = 0;
u8 th_ofst = 3;
u8 th0 = 0;
BB_DBG(bb, DBG_ENV_MNTR, "nhm_App=%d\n", para->nhm_app);
if (!is_app_change)
goto CHK_NHM_UPDATE_FINISHED;
switch (para->nhm_app) {
case NHM_INIT:
case NHM_BACKGROUND: /* IEEE 11K*/
case NHM_DBG_11K:
case NHM_ACS:
case NHM_DIG:
case NHM_TDMA_DIG:
is_update = true;
for (i = 0; i < NHM_TH_NUM; i++) {
if (((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) &&
(i == (NHM_TH_NUM - 1)))
nhm_th[i] = RSSI_2_NHM_TH(NHM_WA_TH);
else
nhm_th[i] = RSSI_2_NHM_TH(nhm_th_11k[i]);
}
break;
case NHM_DBG_RSSI:
if (DIFF_2(bb->bb_ch_i.rssi_min, env->ccx_pre_rssi) < 3)
goto CHK_NHM_UPDATE_FINISHED;
is_update = true;
env->ccx_pre_rssi = bb->bb_ch_i.rssi_min;
th_ofst = 3;
/*nhm th[0] lower bound is 0*/
th0 = MAX_2(bb->bb_ch_i.rssi_min - NHM_PWR_OFST, 0);
/*nhm_th[0] upper bound is 127 - 10 * th_ofst*/
th0 = MIN_2(bb->bb_ch_i.rssi_min - NHM_PWR_OFST,
127 - th_ofst * (NHM_TH_NUM - 1));
for (i = 0; i < NHM_TH_NUM; i++)
nhm_th[i] = RSSI_2_NHM_TH(th0 + (th_ofst * i));
break;
case NHM_DBG_MANUAL:
is_update = true;
th_ofst = para->nhm_manual_th_ofst;
if ((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
/*nhm_th[0] upper bound is 109 - 10 * th_ofst*/
th0 = MIN_2(para->nhm_manual_th0,
NHM_WA_TH - th_ofst * (NHM_TH_NUM - 1));
for (i = 0; i < NHM_TH_NUM; i++) {
if (i == (NHM_TH_NUM - 1))
nhm_th[i] = RSSI_2_NHM_TH(NHM_WA_TH);
else
nhm_th[i] = RSSI_2_NHM_TH(th0 + (th_ofst * i));
}
} else {
/*nhm_th[0] upper bound is 127 - 10 * th_ofst*/
th0 = MIN_2(para->nhm_manual_th0,
127 - th_ofst * (NHM_TH_NUM - 1));
for (i = 0; i < NHM_TH_NUM; i++)
nhm_th[i] = RSSI_2_NHM_TH(th0 + (th_ofst * i));
}
break;
default:
break;
}
CHK_NHM_UPDATE_FINISHED:
if (!is_update)
BB_DBG(bb, DBG_ENV_MNTR, "No need to update NHM_TH\n");
return is_update;
}
bool halbb_nhm_set(struct bb_info *bb, struct ccx_para_info *para)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_link_info *link = &bb->bb_link_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u32 period = 65535;
u32 unit_idx = 0;
u8 nhm_th[NHM_TH_NUM] = {0};
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (para->mntr_time == 0) {
BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n");
return HALBB_SET_FAIL;
}
if (para->nhm_app == NHM_DBG_RSSI && !(link->is_linked)) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING] is_linked = false when nhm_app = rssi\n");
return HALBB_SET_FAIL;
}
if (para->nhm_app == NHM_DBG_MANUAL && para->nhm_manual_th_ofst == 0) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING] th_ofst is 0 when nhm_app = manual\n");
return HALBB_SET_FAIL;
}
if (para->nhm_app == NHM_DBG_MANUAL && para->nhm_manual_th_ofst > 12) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING] th_ofst is larger than 12 when nhm_app = manual\n");
return HALBB_SET_FAIL;
}
if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL)
return HALBB_SET_FAIL;
BB_DBG(bb, DBG_ENV_MNTR, "nhm_incld_cca=%d, mntr_time=%d ms\n",
para->nhm_incld_cca, para->mntr_time);
/*Set unit & period*/
if (para->mntr_time != env->nhm_mntr_time) {
halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period,
&unit_idx);
halbb_set_reg_phy0_1(bb, cr->nhm_period, cr->nhm_period_m,
period);
halbb_set_reg_phy0_1(bb, cr->nhm_unit_idx, cr->nhm_unit_idx_m,
unit_idx);
BB_DBG(bb, DBG_ENV_MNTR, "Update NHM time ((%d)) -> ((%d))\n",
env->nhm_mntr_time, para->mntr_time);
env->nhm_mntr_time = para->mntr_time;
env->ccx_period = (u16)period;
env->ccx_unit_idx = (u8)unit_idx;
}
/*Set include cca*/
if (para->nhm_incld_cca != env->nhm_include_cca) {
halbb_set_reg_phy0_1(bb, cr->nhm_inclu_cca, cr->nhm_inclu_cca_m,
para->nhm_incld_cca);
BB_DBG(bb, DBG_ENV_MNTR,
"Update NHM include cca ((%d)) -> ((%d))\n",
env->nhm_include_cca, para->nhm_incld_cca);
env->nhm_include_cca = para->nhm_incld_cca;
}
/*Set NHM threshold*/
if (halbb_nhm_th_update_chk(bb, para, &nhm_th[0])) {
env->nhm_app = para->nhm_app;
halbb_mem_cpy(bb, &env->nhm_th[0], &nhm_th, NHM_TH_NUM);
/*Set NHM th*/
halbb_nhm_set_th_reg(bb);
}
return HALBB_SET_SUCCESS;
}
void halbb_nhm_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
struct ccx_para_info para = {0};
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
env->nhm_app = NHM_INIT;
env->nhm_include_cca = NHM_CCA_INIT;
env->nhm_mntr_time = 0;
env->nhm_pwr = 0;
/*if r_nhm_en = 0, nhm report will always be 0.*/
halbb_set_reg_phy0_1(bb, cr->nhm_en, cr->nhm_en_m, true);
/*r_nhm_pwdb_method_sel[0]=1 : select max path*/
/*r_nhm_pwdb_method_sel[1] is dummy*/
halbb_set_reg_phy0_1(bb, cr->nhm_method_sel, cr->nhm_method_sel_m, 0x1);
}
void halbb_nhm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct ccx_para_info para = {0};
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
u8 end_i = 0;
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if ((_os_strcmp(input[1], "-h") == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"NHM Get Result: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Basic-Trigger(11k/1900ms): {1}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger(11k): {2} {0~2097ms} {Include CCA}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger(RSSI): {3} {0~2097ms} {Include CCA}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger(Manual): {4} {0~2097ms} {Include CCA} {th[0]} {th_ofst:1~12}\n");
} else if (var[0] == 100) { /*Get NHM results*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ccx_rpt_stamp=%d, ccx_period=%d\n",
env->ccx_rpt_stamp, env->ccx_period);
if (halbb_nhm_get_result(bb)) {
if ((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C))
end_i = NHM_RPT_NUM - 1;
else
end_i = NHM_RPT_NUM;
for (i = 0; i < end_i; i++)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"nhm_sw_result[%d] = %d (%d percent)\n",
i, env->nhm_sw_result[i],
env->nhm_rpt[i]);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"nhm_cca_cnt = %d (%d percent)\n",
env->nhm_cca_cnt, env->nhm_cca_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"nhm_tx_cnt = %d (%d percent)\n",
env->nhm_tx_cnt, env->nhm_tx_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"nhm_idle_cnt = %d (%d percent)\n",
env->nhm_idle_cnt, env->nhm_idle_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"nhm_ratio=%d, nhm_pwr(RSSI)=%d\n",
env->nhm_ratio, env->nhm_pwr);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "Get NHM result Fail\n");
}
halbb_ccx_racing_release(bb);
env->ccx_manual_ctrl = false;
} else { /*NMH trigger*/
env->ccx_manual_ctrl = true;
for (i = 1; i < 9; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]);
}
if (var[0] == 1) {
para.nhm_app = NHM_DBG_11K;
para.mntr_time = 1900;
para.nhm_incld_cca = NHM_EXCLUDE_CCA;
} else if (var[0] == 2) {
para.nhm_app = NHM_DBG_11K;
para.mntr_time = (u16)var[1];
para.nhm_incld_cca = (enum nhm_option_cca_all)var[2];
} else if (var[0] == 3) {
para.nhm_app = NHM_DBG_RSSI;
para.mntr_time = (u16)var[1];
para.nhm_incld_cca = (enum nhm_option_cca_all)var[2];
} else {
para.nhm_app = NHM_DBG_MANUAL;
para.mntr_time = (u16)var[1];
para.nhm_incld_cca = (enum nhm_option_cca_all)var[2];
para.nhm_manual_th0 = (u8)var[3];
para.nhm_manual_th_ofst = (u8)var[4];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"manual_th_ofst=%d, manaul_th0=%d\n",
para.nhm_manual_th_ofst,
para.nhm_manual_th0);
}
para.rac_lv = RAC_LV_4;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"app=%d, lv=%d, time=%d ms, inclu_cca=%d\n",
para.nhm_app, para.rac_lv, para.mntr_time,
para.nhm_incld_cca);
if (halbb_nhm_set(bb, ¶) == HALBB_SET_SUCCESS) {
halbb_ccx_trigger(bb);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "ccx_rpt_stamp=%d\n",
env->ccx_rpt_stamp);
for (i = 0; i < NHM_TH_NUM; i++)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"NHM_th[%d] RSSI = %d\n", i,
NHM_TH_2_RSSI(env->nhm_th[i]));
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "NHM mntr set fail!\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif /*#ifdef NHM_SUPPORT*/
#ifdef CLM_SUPPORT
void halbb_clm_get_utility(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
env->clm_ratio = (u8)halbb_ccx_get_ratio(bb, env->clm_result, 100);
}
bool
halbb_clm_get_result(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
if (!(halbb_get_reg(bb, cr->clm_rdy, cr->clm_rdy_m))) {
BB_DBG(bb, DBG_ENV_MNTR, "Get CLM report Fail\n");
return false;
}
env->clm_result = (u16)halbb_get_reg(bb, cr->clm_cnt, cr->clm_cnt_m);
BB_DBG(bb, DBG_ENV_MNTR, "CLM result = %d\n", env->clm_result);
halbb_clm_get_utility(bb);
return true;
}
bool halbb_clm_set(struct bb_info *bb, struct ccx_para_info *para)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u32 period = 0;
u32 unit_idx = 0;
if (para->mntr_time == 0) {
BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n");
return HALBB_SET_FAIL;
}
if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL)
return HALBB_SET_FAIL;
/*Set unit & period*/
if (para->mntr_time != env->clm_mntr_time) {
halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period,
&unit_idx);
halbb_set_reg_phy0_1(bb, cr->clm_period, cr->clm_period_m,
period);
halbb_set_reg_phy0_1(bb, cr->clm_unit_idx, cr->clm_unit_idx_m,
unit_idx);
BB_DBG(bb, DBG_ENV_MNTR, "Update CLM time ((%d)) -> ((%d))\n",
env->clm_mntr_time, para->mntr_time);
env->clm_mntr_time = para->mntr_time;
env->ccx_period = (u16)period;
env->ccx_unit_idx = (u8)unit_idx;
}
/*Set input option*/
if (para->clm_input_opt != env->clm_input_opt) {
halbb_set_reg_phy0_1(bb, cr->clm_opt, cr->clm_opt_m,
para->clm_input_opt);
BB_DBG(bb, DBG_ENV_MNTR,
"Update CLM input opt ((%d)) -> ((%d))\n",
env->clm_input_opt, para->clm_input_opt);
env->clm_input_opt = para->clm_input_opt;
}
env->clm_app = para->clm_app;
return HALBB_SET_SUCCESS;
}
void halbb_clm_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
env->clm_input_opt = CLM_CCA_INIT;
env->clm_app = CLM_INIT;
env->clm_mntr_time = 0;
}
void halbb_clm_set_dbg_sel(struct bb_info *bb, u8 dbg_sel)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
/*r_clm_from_dbg_sel[5](0xa04[25]) is dummy*/
halbb_set_reg_phy0_1(bb, cr->clm_dbg_sel, cr->clm_dbg_sel_m, dbg_sel);
}
void halbb_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct ccx_para_info para = {0};
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]);
}
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"CLM Get Result: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"CLM Basic-Trigger(1900ms): {1}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"CLM Adv-Trigger: {2} {0~2097ms} {input:0(p20)/1(s20)/2(s40)/3(s80)/4(dbg)/5(txon_cca)/6(s20_s40_s80)/7(s20_s40_s80_p20)}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"CLM set dbg_sel: {3} {bit:0~31}\n");
} else if (var[0] == 100) { /*Get CLM results */
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ccx_rpt_stamp=%d, ccx_period=%d\n",
env->ccx_rpt_stamp, env->ccx_period);
if (halbb_clm_get_result(bb)) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"clm_result = %d (%d percent)\n",
env->clm_result, env->clm_ratio);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "Get CLM_rpt Fail\n");
}
halbb_ccx_racing_release(bb);
env->ccx_manual_ctrl = false;
} else if (var[0] == 3) { /* Set dbg_bit_sel */
halbb_clm_set_dbg_sel(bb, (u8)var[1]);
} else { /* Set & trigger CLM */
env->ccx_manual_ctrl = true;
if (var[0] == 1) {
para.mntr_time = 1900;
para.clm_input_opt = CLM_CCA_P20;
} else if (var[0] == 2) {
para.mntr_time = (u16)var[1];
para.clm_input_opt = (enum clm_opt_input)var[2];
}
para.clm_app = CLM_DBG;
para.rac_lv = RAC_LV_4;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"app=%d, lv=%d, time=%d ms, input_opt=%d\n",
para.clm_app, para.rac_lv, para.mntr_time,
para.clm_input_opt);
if (halbb_clm_set(bb, ¶) == HALBB_SET_SUCCESS) {
halbb_ccx_trigger(bb);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "ccx_rpt_stamp=%d\n",
env->ccx_rpt_stamp);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "CLM mntr set fail!\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif /*#ifdef CLM_SUPPORT*/
#ifdef IFS_CLM_SUPPORT
void halbb_ifs_clm_get_utility(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
u32 numer = 0;
u16 denom = 0;
env->ifs_clm_tx_ratio = (u8)halbb_ccx_get_ratio(bb, env->ifs_clm_tx,
100);
env->ifs_clm_edcca_excl_cca_ratio = (u8)halbb_ccx_get_ratio(bb,
env->ifs_clm_edcca_excl_cca, 100);
env->ifs_clm_cck_fa_ratio = (u8)halbb_ccx_get_ratio(bb,
env->ifs_clm_cckfa, 100);
env->ifs_clm_ofdm_fa_ratio = (u8)halbb_ccx_get_ratio(bb,
env->ifs_clm_ofdmfa, 100);
env->ifs_clm_cck_cca_excl_fa_ratio = (u8)halbb_ccx_get_ratio(bb,
env->ifs_clm_cckcca_excl_fa, 100);
env->ifs_clm_ofdm_cca_excl_fa_ratio = (u8)halbb_ccx_get_ratio(bb,
env->ifs_clm_ofdmcca_excl_fa,
100);
env->ifs_clm_cck_fa_permil = halbb_ccx_get_ratio(bb, env->ifs_clm_cckfa,
1000);
env->ifs_clm_ofdm_fa_permil = halbb_ccx_get_ratio(bb,
env->ifs_clm_ofdmfa, 1000);
for (i = 0; i < IFS_CLM_NUM; i++) {
if ((env->ifs_clm_his[i] > 127) && (bb->ic_type == BB_RTL8852A))
env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
else
env->ifs_clm_ifs_avg[i] = halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_avg[i]);
numer = halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_cca[i]) +
(env->ifs_clm_his[i] >> 1);
denom = env->ifs_clm_his[i];
env->ifs_clm_cca_avg[i] = HALBB_DIV(numer, denom);
}
BB_DBG(bb, DBG_ENV_MNTR,
"IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
BB_DBG(bb, DBG_ENV_MNTR,
"IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
BB_DBG(bb, DBG_ENV_MNTR,
"IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
BB_DBG(bb, DBG_ENV_MNTR,
"IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
env->ifs_clm_cck_cca_excl_fa_ratio,
env->ifs_clm_ofdm_cca_excl_fa_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "Time:[his, ifs_avg(us), cca_avg(us)]\n");
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG(bb, DBG_ENV_MNTR, "T%d:[%d, %d, %d]\n", i + 1,
env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
env->ifs_clm_cca_avg[i]);
}
bool
halbb_ifs_clm_get_result(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u8 i = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (!(halbb_get_reg(bb, cr->ifs_clm_rdy, cr->ifs_clm_rdy_m))) {
BB_DBG(bb, DBG_ENV_MNTR, "Get IFS_CLM report Fail\n");
return false;
}
/*CLM result*/
env->ifs_clm_tx = (u16)halbb_get_reg(bb, cr->ifs_clm_tx_cnt,
cr->ifs_clm_tx_cnt_m);
env->ifs_clm_edcca_excl_cca = (u16)halbb_get_reg(bb,
cr->ifs_clm_edcca_exclu_cca,
cr->ifs_clm_edcca_exclu_cca_m);
env->ifs_clm_cckcca_excl_fa = (u16)halbb_get_reg(bb,
cr->ifs_clm_cckcca_exclu_fa,
cr->ifs_clm_cckcca_exclu_fa_m);
env->ifs_clm_ofdmcca_excl_fa = (u16)halbb_get_reg(bb,
cr->ifs_clm_ofdmcca_exclu_fa,
cr->ifs_clm_ofdmcca_exclu_fa_m);
env->ifs_clm_cckfa = (u16)halbb_get_reg(bb, cr->ifs_clm_cck_fa,
cr->ifs_clm_cck_fa_m);
env->ifs_clm_ofdmfa = (u16)halbb_get_reg(bb, cr->ifs_clm_ofdm_fa,
cr->ifs_clm_ofdm_fa_m);
/* IFS result */
env->ifs_clm_his[0] = (u16)halbb_get_reg(bb, cr->ifs_clm_t1_his,
cr->ifs_clm_t1_his_m);
env->ifs_clm_his[1] = (u16)halbb_get_reg(bb, cr->ifs_clm_t2_his,
cr->ifs_clm_t2_his_m);
env->ifs_clm_his[2] = (u16)halbb_get_reg(bb, cr->ifs_clm_t3_his,
cr->ifs_clm_t3_his_m);
env->ifs_clm_his[3] = (u16)halbb_get_reg(bb, cr->ifs_clm_t4_his,
cr->ifs_clm_t4_his_m);
env->ifs_clm_avg[0] = (u16)halbb_get_reg(bb, cr->ifs_clm_t1_avg,
cr->ifs_clm_t1_avg_m);
env->ifs_clm_avg[1] = (u16)halbb_get_reg(bb, cr->ifs_clm_t2_avg,
cr->ifs_clm_t2_avg_m);
env->ifs_clm_avg[2] = (u16)halbb_get_reg(bb, cr->ifs_clm_t3_avg,
cr->ifs_clm_t3_avg_m);
env->ifs_clm_avg[3] = (u16)halbb_get_reg(bb, cr->ifs_clm_t4_avg,
cr->ifs_clm_t4_avg_m);
env->ifs_clm_cca[0] = (u16)halbb_get_reg(bb, cr->ifs_clm_t1_cca,
cr->ifs_clm_t1_cca_m);
env->ifs_clm_cca[1] = (u16)halbb_get_reg(bb, cr->ifs_clm_t2_cca,
cr->ifs_clm_t2_cca_m);
env->ifs_clm_cca[2] = (u16)halbb_get_reg(bb, cr->ifs_clm_t3_cca,
cr->ifs_clm_t3_cca_m);
env->ifs_clm_cca[3] = (u16)halbb_get_reg(bb, cr->ifs_clm_t4_cca,
cr->ifs_clm_t4_cca_m);
env->ifs_clm_total_ifs = (u16)halbb_get_reg(bb, cr->ifs_total_cnt,
cr->ifs_total_cnt_m);
/*Print Result*/
BB_DBG(bb, DBG_ENV_MNTR, "IFS-CLM total_ifs = %d\n",
env->ifs_clm_total_ifs);
BB_DBG(bb, DBG_ENV_MNTR, "IFS-CLM {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
BB_DBG(bb, DBG_ENV_MNTR, "IFS-CLM FA {CCK, OFDM} = {%d, %d}\n",
env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
BB_DBG(bb, DBG_ENV_MNTR,
"IFS-CLM CCA_exclu_FA {CCK, OFDM} = {%d, %d}\n",
env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
BB_DBG(bb, DBG_ENV_MNTR, "Time:[his, avg, cca]\n");
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG(bb, DBG_ENV_MNTR, "T%d:[%d, %d, %d]\n", i + 1,
env->ifs_clm_his[i], env->ifs_clm_avg[i],
env->ifs_clm_cca[i]);
halbb_ifs_clm_get_utility(bb);
return true;
}
void halbb_ifs_clm_set_th_reg(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u8 i = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
/*Set IFS for en/th_low/th_high T1~T4*/
halbb_set_reg_phy0_1(bb, cr->ifs_t1_th_l, cr->ifs_t1_th_l_m,
env->ifs_clm_th_l[0]);
halbb_set_reg_phy0_1(bb, cr->ifs_t2_th_l, cr->ifs_t2_th_l_m,
env->ifs_clm_th_l[1]);
halbb_set_reg_phy0_1(bb, cr->ifs_t3_th_l, cr->ifs_t3_th_l_m,
env->ifs_clm_th_l[2]);
halbb_set_reg_phy0_1(bb, cr->ifs_t4_th_l, cr->ifs_t4_th_l_m,
env->ifs_clm_th_l[3]);
halbb_set_reg_phy0_1(bb, cr->ifs_t1_th_h, cr->ifs_t1_th_h_m,
env->ifs_clm_th_h[0]);
halbb_set_reg_phy0_1(bb, cr->ifs_t2_th_h, cr->ifs_t2_th_h_m,
env->ifs_clm_th_h[1]);
halbb_set_reg_phy0_1(bb, cr->ifs_t3_th_h, cr->ifs_t3_th_h_m,
env->ifs_clm_th_h[2]);
halbb_set_reg_phy0_1(bb, cr->ifs_t4_th_h, cr->ifs_t4_th_h_m,
env->ifs_clm_th_h[3]);
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG(bb, DBG_ENV_MNTR,
"Update IFS_T%d_th{low, high} : {%d, %d}\n",
i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
}
bool halbb_ifs_clm_th_update_chk(struct bb_info *bb, struct ccx_para_info *para,
u16 *ifs_th_l, u16 *ifs_th_h)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
bool is_app_change = (env->ifs_clm_app == para->ifs_clm_app) ? false : true;
bool is_update = false;
u8 i = 0;
u32 ifs_th0_us = 0;
u32 ifs_th_times = 0;
u32 ifs_th_h_us[IFS_CLM_NUM] = {0};
BB_DBG(bb, DBG_ENV_MNTR, "ifs_clm_App=%d\n", para->ifs_clm_app);
if (!is_app_change)
goto CHK_IFS_UPDATE_FINISHED;
is_update = true;
switch (para->ifs_clm_app) {
case IFS_CLM_INIT:
case IFS_CLM_BACKGROUND:
case IFS_CLM_ACS:
case IFS_CLM_DBG:
case IFS_CLM_DIG:
case IFS_CLM_TDMA_DIG:
/*ifs_th_h_us = {4096 , 1024 , 256 , 64}*/
/*ifs_th_l_us = {1024+unit, 256+unit, 64+unit, 0}*/
ifs_th0_us = 64;
ifs_th_times = 4;
break;
case IFS_CLM_DBG_MANUAL:
/*ifs_th_h_us[0] = ifs_th0_us*/
/*ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times, i = 1 ~ 3*/
/*ifs_th_l_us[0] = 0*/
/*ifs_th_l_us[i] = ifs_th_h_us[i - 1] + unit, i = 1 ~ 3*/
ifs_th0_us = para->ifs_clm_manual_th0;
ifs_th_times = para->ifs_clm_manual_th_times;
break;
default:
break;
}
for (i = 0; i < IFS_CLM_NUM; i++) {
ifs_th_l[i] = (i == 0) ? 0 : ifs_th_h[i - 1] + 1;
ifs_th_h_us[i] = (i == 0) ? ifs_th0_us : ifs_th_h_us[i - 1] *
ifs_th_times;
ifs_th_h[i] = halbb_ccx_us_2_idx_cnt(bb, ifs_th_h_us[i]);
}
CHK_IFS_UPDATE_FINISHED:
if (!is_update)
BB_DBG(bb, DBG_ENV_MNTR, "No need to update IFS_TH\n");
return is_update;
}
bool halbb_ifs_clm_set(struct bb_info *bb, struct ccx_para_info *para)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u32 period = 0;
u32 unit_idx = 0;
u16 ccx_mntr_time = 0;
u16 ifs_th_l[IFS_CLM_NUM] = {0};
u16 ifs_th_h[IFS_CLM_NUM] = {0};
u8 i = 0;
if (para->mntr_time == 0) {
BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n");
return HALBB_SET_FAIL;
}
if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL)
return HALBB_SET_FAIL;
/*Set unit & period*/
if (para->mntr_time != env->ifs_clm_mntr_time) {
halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period,
&unit_idx);
halbb_set_reg_phy0_1(bb, cr->ifs_clm_period,
cr->ifs_clm_period_m, period);
halbb_set_reg_phy0_1(bb, cr->ifs_clm_unit_idx,
cr->ifs_clm_unit_idx_m, unit_idx);
BB_DBG(bb, DBG_ENV_MNTR,
"Update IFS-CLM time ((%d)) -> ((%d))\n",
env->ifs_clm_mntr_time, para->mntr_time);
env->ifs_clm_mntr_time = para->mntr_time;
env->ccx_period = (u16)period;
env->ccx_unit_idx = (u8)unit_idx;
}
/*Set IFS CLM threshold*/
if (halbb_ifs_clm_th_update_chk(bb, para, &ifs_th_l[0], &ifs_th_h[0])) {
env->ifs_clm_app = para->ifs_clm_app;
for (i = 0; i < IFS_CLM_NUM; i++) {
env->ifs_clm_th_l[i] = ifs_th_l[i];
env->ifs_clm_th_h[i] = ifs_th_h[i];
}
halbb_ifs_clm_set_th_reg(bb);
}
return HALBB_SET_SUCCESS;
}
void halbb_ifs_clm_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
struct ccx_para_info para = {0};
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
env->ifs_clm_app = IFS_CLM_INIT;
env->ifs_clm_mntr_time = 0;
/*if r_IFS_collect_en = 0, ifs_clm ready bit will always be 0.*/
halbb_set_reg_phy0_1(bb, cr->ifs_clm_en, cr->ifs_clm_en_m, true);
/*Enable IFS cnt*/
halbb_set_reg_phy0_1(bb, cr->ifs_t1_en, cr->ifs_t1_en_m, true);
halbb_set_reg_phy0_1(bb, cr->ifs_t2_en, cr->ifs_t2_en_m, true);
halbb_set_reg_phy0_1(bb, cr->ifs_t3_en, cr->ifs_t3_en_m, true);
halbb_set_reg_phy0_1(bb, cr->ifs_t4_en, cr->ifs_t4_en_m, true);
}
void halbb_ifs_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct ccx_para_info para = {0};
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]);
}
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"IFS-CLM Get Result: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"IFS-CLM Basic-Trigger 1900ms: {1}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"IFS-CLM Adv-Trigger: {2} {0~2097ms}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"IFS-CLM Adv-Trigger(manual): {3} {0~2097ms} {ifs_th0(us)} {ifs_th_times}\n");
} else if (var[0] == 100) { /*Get IFS_CLM results*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ccx_rpt_stamp=%d, ccx_period=%d\n",
env->ccx_rpt_stamp, env->ccx_period);
if (halbb_ifs_clm_get_result(bb)) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_CLM Tx cnt = %d (%d percent)\n",
env->ifs_clm_tx, env->ifs_clm_tx_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_CLM EDCCA_excl_cca cnt = %d (%d percent)\n",
env->ifs_clm_edcca_excl_cca,
env->ifs_clm_edcca_excl_cca_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_CLM CCK FA cnt = %d (%d percent/%d permil)\n",
env->ifs_clm_cckfa,
env->ifs_clm_cck_fa_ratio,
env->ifs_clm_cck_fa_permil);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_CLM OFDM FA cnt = %d (%d percent/%d permil)\n",
env->ifs_clm_ofdmfa,
env->ifs_clm_ofdm_fa_ratio,
env->ifs_clm_ofdm_fa_permil);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_CLM CCK CCA_excl_fa cnt = %d (%d percent)\n",
env->ifs_clm_cckcca_excl_fa,
env->ifs_clm_cck_cca_excl_fa_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_CLM OFDM CCA_excl_fa cnt = %d (%d percent)\n",
env->ifs_clm_ofdmcca_excl_fa,
env->ifs_clm_ofdm_cca_excl_fa_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "IFS_total cnt = %d\n",
env->ifs_clm_total_ifs);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Time(us):[his, ifs_avg(us), cca_avg(us)]\n");
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"T%d(%d ~ %d):[%d, %d, %d]\n",
i + 1, halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_th_l[i]),
halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_th_h[i]),
env->ifs_clm_his[i],
env->ifs_clm_ifs_avg[i],
env->ifs_clm_cca_avg[i]);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "Get ICS-CLM_rpt Fail\n");
}
halbb_ccx_racing_release(bb);
env->ccx_manual_ctrl = false;
} else { /*IFS_CLM trigger*/
env->ccx_manual_ctrl = true;
if (var[0] == 1) {
para.ifs_clm_app = IFS_CLM_DBG;
para.mntr_time = 1900;
para.ifs_clm_manual_th0 = 0;
para.ifs_clm_manual_th_times = 0;
} else if (var[0] == 2) {
para.ifs_clm_app = IFS_CLM_DBG;
para.mntr_time = (u16)var[1];
para.ifs_clm_manual_th0 = 0;
para.ifs_clm_manual_th_times = 0;
} else {
para.ifs_clm_app = IFS_CLM_DBG_MANUAL;
para.mntr_time = (u16)var[1];
para.ifs_clm_manual_th0 = (u32)var[2];
para.ifs_clm_manual_th_times = (u32)var[3];
}
para.rac_lv = RAC_LV_4;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"app=%d, lv=%d, time=%d ms, manual_th0=%d(us), manual_th_times=%d\n",
para.ifs_clm_app, para.rac_lv, para.mntr_time,
para.ifs_clm_manual_th0,
para.ifs_clm_manual_th_times);
if (halbb_ifs_clm_set(bb, ¶) == HALBB_SET_SUCCESS) {
halbb_ccx_trigger(bb);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "ccx_rpt_stamp=%d\n",
env->ccx_rpt_stamp);
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"IFS_T%d_th(us){low, high} : {%d, %d}\n",
i + 1,halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_th_l[i]),
halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_th_h[i]));
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "IFS_CLM mntr set fail!\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif
#ifdef FAHM_SUPPORT
void halbb_fahm_cal_wgt(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
for (i = 0; i < FAHM_RPT_NUM; i++) {
if (i == 0)
env->fahm_wgt[i] = (u8)(MAX_2(env->fahm_th[i] - 2, 0));
else if (i == (FAHM_RPT_NUM - 1))
env->fahm_wgt[i] = (u8)(env->fahm_th[i - 1] + 2);
else
env->fahm_wgt[i] = (u8)((env->fahm_th[i - 1] +
env->fahm_th[i]) >> 1);
}
}
u8 halbb_fahm_cal_wgt_avg(struct bb_info *bb, u8 start_i, u8 end_i, u16 n_sum)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
u32 tmp = 0;
u8 wgt_avg = 0;
u8 fahm_valid = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (n_sum == 0) {
BB_DBG(bb, DBG_ENV_MNTR,
"fahm_rpt_sum = 0, don't need to update noise\n");
return 0;
} else if (end_i > FAHM_RPT_NUM - 1) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING]fahm_rpt_end_idx is larger than 11!!\n");
return 0;
}
for (i = start_i; i <= end_i; i++)
tmp += env->fahm_sw_result[i] * env->fahm_wgt[i];
wgt_avg = (u8)(FAHM_TH_2_RSSI(HALBB_DIV(tmp, n_sum)));
fahm_valid = (u8)halbb_ccx_get_ratio(bb, n_sum, 100);
BB_DBG(bb, DBG_ENV_MNTR,
"valid: ((%d)) percent, wgt_avg(RSSI)=((%d))\n",
fahm_valid, wgt_avg);
return wgt_avg;
}
void halbb_fahm_get_utility(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
halbb_fahm_cal_wgt(bb);
for (i = 0; i < FAHM_RPT_NUM; i++) {
if (((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) &&
(i == (FAHM_RPT_NUM - 1))) {
env->fahm_sw_result[0] += env->fahm_result[i];
env->fahm_sw_result[i] = 0;
} else {
env->fahm_sw_result[i] = env->fahm_result[i];
}
}
BB_DBG(bb, DBG_ENV_MNTR,
"FAHM sw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
env->ccx_rpt_stamp, env->fahm_sw_result[11],
env->fahm_sw_result[10], env->fahm_sw_result[9],
env->fahm_sw_result[8], env->fahm_sw_result[7],
env->fahm_sw_result[6], env->fahm_sw_result[5],
env->fahm_sw_result[4], env->fahm_sw_result[3],
env->fahm_sw_result[2], env->fahm_sw_result[1],
env->fahm_sw_result[0]);
env->fahm_ratio = (u8)halbb_ccx_get_ratio(bb, env->fahm_result_sum,
100);
env->fahm_denom_ratio = (u8)halbb_ccx_get_ratio(bb,
env->fahm_denom_result, 100);
env->fahm_pwr = halbb_fahm_cal_wgt_avg(bb, 0, FAHM_RPT_NUM - 1,
env->fahm_result_sum);
for (i = 0; i < FAHM_RPT_NUM; i++)
env->fahm_rpt[i] = (u8)halbb_ccx_get_ratio(bb,
env->fahm_sw_result[i], 100);
BB_DBG(bb, DBG_ENV_MNTR, "fahm_ratio=%d, fahm_pwr(RSSI)=%d\n",
env->fahm_ratio, env->fahm_pwr);
}
bool halbb_fahm_get_result(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u8 i = 0;
u32 result_sum_tmp = 0;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (!(halbb_get_reg(bb, cr->fahm_rdy, cr->fahm_rdy_m))) {
BB_DBG(bb, DBG_ENV_MNTR, "Get FAHM report Fail\n");
return false;
}
env->fahm_result[0] = (u16)halbb_get_reg(bb, cr->fahm_cnt0,
cr->fahm_cnt0_m);
env->fahm_result[1] = (u16)halbb_get_reg(bb, cr->fahm_cnt1,
cr->fahm_cnt1_m);
env->fahm_result[2] = (u16)halbb_get_reg(bb, cr->fahm_cnt2,
cr->fahm_cnt2_m);
env->fahm_result[3] = (u16)halbb_get_reg(bb, cr->fahm_cnt3,
cr->fahm_cnt3_m);
env->fahm_result[4] = (u16)halbb_get_reg(bb, cr->fahm_cnt4,
cr->fahm_cnt4_m);
env->fahm_result[5] = (u16)halbb_get_reg(bb, cr->fahm_cnt5,
cr->fahm_cnt5_m);
env->fahm_result[6] = (u16)halbb_get_reg(bb, cr->fahm_cnt6,
cr->fahm_cnt6_m);
env->fahm_result[7] = (u16)halbb_get_reg(bb, cr->fahm_cnt7,
cr->fahm_cnt7_m);
env->fahm_result[8] = (u16)halbb_get_reg(bb, cr->fahm_cnt8,
cr->fahm_cnt8_m);
env->fahm_result[9] = (u16)halbb_get_reg(bb, cr->fahm_cnt9,
cr->fahm_cnt9_m);
env->fahm_result[10] = (u16)halbb_get_reg(bb, cr->fahm_cnt10,
cr->fahm_cnt10_m);
env->fahm_result[11] = (u16)halbb_get_reg(bb, cr->fahm_cnt11,
cr->fahm_cnt11_m);
for (i = 0; i < FAHM_RPT_NUM; i++)
result_sum_tmp += (u32)env->fahm_result[i];
env->fahm_result_sum = (u16)result_sum_tmp;
BB_DBG(bb, DBG_ENV_MNTR, "fahm_result_sum=%d\n", env->fahm_result_sum);
/*Get FAHM denominator*/
env->fahm_denom_result = (u16)halbb_get_reg(bb, cr->fahm_denom_cnt,
cr->fahm_denom_cnt_m);
BB_DBG(bb, DBG_ENV_MNTR, "fahm_denominator result = %d\n",
env->fahm_denom_result);
BB_DBG(bb, DBG_ENV_MNTR,
"FAHM hw result[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
env->ccx_rpt_stamp, env->fahm_result[11], env->fahm_result[10],
env->fahm_result[9], env->fahm_result[8], env->fahm_result[7],
env->fahm_result[6], env->fahm_result[5], env->fahm_result[4],
env->fahm_result[3], env->fahm_result[2], env->fahm_result[1],
env->fahm_result[0]);
halbb_fahm_get_utility(bb);
return true;
}
void halbb_fahm_set_th_reg(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
/*Set FAHM threshold*/ /*Unit: RSSI U(8,1)*/
halbb_set_reg_phy0_1(bb, cr->fahm_th0, cr->fahm_th0_m, env->fahm_th[0]);
halbb_set_reg_phy0_1(bb, cr->fahm_th1, cr->fahm_th1_m, env->fahm_th[1]);
halbb_set_reg_phy0_1(bb, cr->fahm_th2, cr->fahm_th2_m, env->fahm_th[2]);
halbb_set_reg_phy0_1(bb, cr->fahm_th3, cr->fahm_th3_m, env->fahm_th[3]);
halbb_set_reg_phy0_1(bb, cr->fahm_th4, cr->fahm_th4_m, env->fahm_th[4]);
halbb_set_reg_phy0_1(bb, cr->fahm_th5, cr->fahm_th5_m, env->fahm_th[5]);
halbb_set_reg_phy0_1(bb, cr->fahm_th6, cr->fahm_th6_m, env->fahm_th[6]);
halbb_set_reg_phy0_1(bb, cr->fahm_th7, cr->fahm_th7_m, env->fahm_th[7]);
halbb_set_reg_phy0_1(bb, cr->fahm_th8, cr->fahm_th8_m, env->fahm_th[8]);
halbb_set_reg_phy0_1(bb, cr->fahm_th9, cr->fahm_th9_m, env->fahm_th[9]);
halbb_set_reg_phy0_1(bb, cr->fahm_th10, cr->fahm_th10_m,
env->fahm_th[10]);
BB_DBG(bb, DBG_ENV_MNTR,
"Update FAHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n",
env->fahm_th[10], env->fahm_th[9], env->fahm_th[8],
env->fahm_th[7], env->fahm_th[6], env->fahm_th[5],
env->fahm_th[4], env->fahm_th[3], env->fahm_th[2],
env->fahm_th[1], env->fahm_th[0]);
}
bool
halbb_fahm_th_update_chk(struct bb_info *bb, struct ccx_para_info *para,
u8 *fahm_th)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
bool is_app_change = (env->fahm_app == para->fahm_app) ? false : true;
bool is_update = is_app_change;
u8 fahm_th_11k[FAHM_TH_NUM] = {18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60}; /*Unit RSSI*/
u8 i = 0;
u8 th_ofst = 3;
u8 th0 = 0;
BB_DBG(bb, DBG_ENV_MNTR, "fahm_App=%d\n", para->fahm_app);
if (!is_app_change)
goto CHK_FAHM_UPDATE_FINISHED;
switch (para->fahm_app) {
case FAHM_INIT:
case FAHM_BACKGROUND: /* IEEE 11K*/
case FAHM_DBG_11K:
case FAHM_ACS:
case FAHM_DIG:
case FAHM_TDMA_DIG:
is_update = true;
for (i = 0; i < FAHM_TH_NUM; i++) {
if (((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) &&
(i == (FAHM_TH_NUM - 1)))
fahm_th[i] = RSSI_2_FAHM_TH(FAHM_WA_TH);
else
fahm_th[i] = RSSI_2_FAHM_TH(fahm_th_11k[i]);
}
break;
case FAHM_DBG_RSSI:
if (DIFF_2(bb->bb_ch_i.rssi_min, env->ccx_pre_rssi) < 3)
goto CHK_FAHM_UPDATE_FINISHED;
is_update = true;
env->ccx_pre_rssi = bb->bb_ch_i.rssi_min;
th_ofst = 3;
/*fahm th[0] lower bound is 0*/
th0 = MAX_2(bb->bb_ch_i.rssi_min - FAHM_PWR_OFST, 0);
/*fahm_th[0] upper bound is 127 - 10 * th_ofst*/
th0 = MIN_2(bb->bb_ch_i.rssi_min - FAHM_PWR_OFST,
127 - th_ofst * (FAHM_TH_NUM - 1));
for (i = 0; i < FAHM_TH_NUM; i++)
fahm_th[i] = RSSI_2_FAHM_TH(th0 + (th_ofst * i));
break;
case FAHM_DBG_MANUAL:
is_update = true;
th_ofst = para->fahm_manual_th_ofst;
if ((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
/*fahm_th[0] upper bound is 109 - 10 * th_ofst*/
th0 = MIN_2(para->fahm_manual_th0,
FAHM_WA_TH - th_ofst * (FAHM_TH_NUM - 1));
for (i = 0; i < FAHM_TH_NUM; i++) {
if (i == (FAHM_TH_NUM - 1))
fahm_th[i] = RSSI_2_FAHM_TH(FAHM_WA_TH);
else
fahm_th[i] = RSSI_2_FAHM_TH(th0 + (th_ofst * i));
}
} else {
/*fahm_th[0] upper bound is 127 - 10 * th_ofst*/
th0 = MIN_2(para->fahm_manual_th0,
127 - th_ofst * (FAHM_TH_NUM - 1));
for (i = 0; i < FAHM_TH_NUM; i++)
fahm_th[i] = RSSI_2_FAHM_TH(th0 + (th_ofst * i));
}
break;
default:
break;
}
CHK_FAHM_UPDATE_FINISHED:
if (!is_update)
BB_DBG(bb, DBG_ENV_MNTR, "No need to update FAHM_TH\n");
return is_update;
}
bool halbb_fahm_set(struct bb_info *bb, struct ccx_para_info *para)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_link_info *link = &bb->bb_link_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u32 period = 65535;
u32 unit_idx = 0;
u8 fahm_th[FAHM_TH_NUM] = {0};
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (para->mntr_time == 0) {
BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n");
return HALBB_SET_FAIL;
}
if (para->fahm_app == FAHM_DBG_RSSI && !(link->is_linked)) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING] is_linked = false when fahm_app = rssi\n");
return HALBB_SET_FAIL;
}
if (para->fahm_app == FAHM_DBG_MANUAL &&
para->fahm_manual_th_ofst == 0) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING] th_ofst is 0 when fahm_app = manual\n");
return HALBB_SET_FAIL;
}
if (para->fahm_app == FAHM_DBG_MANUAL &&
para->fahm_manual_th_ofst > 12) {
BB_DBG(bb, DBG_ENV_MNTR,
"[WARNING] th_ofst is larger than 12 when fahm_app = manual\n");
return HALBB_SET_FAIL;
}
if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL)
return HALBB_SET_FAIL;
BB_DBG(bb, DBG_ENV_MNTR, "mntr_time=%d ms\n", para->mntr_time);
/*Set unit & period*/
if (para->mntr_time != env->fahm_mntr_time) {
halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period,
&unit_idx);
halbb_set_reg_phy0_1(bb, cr->fahm_period, cr->fahm_period_m,
period);
halbb_set_reg_phy0_1(bb, cr->fahm_unit_idx, cr->fahm_unit_idx_m,
unit_idx);
BB_DBG(bb, DBG_ENV_MNTR, "Update FAHM time ((%d)) -> ((%d))\n",
env->fahm_mntr_time, para->mntr_time);
env->fahm_mntr_time = para->mntr_time;
env->ccx_period = (u16)period;
env->ccx_unit_idx = (u8)unit_idx;
}
/*Set numerator_opt*/
if (para->fahm_numer_opt != env->fahm_numer_opt) {
halbb_set_reg_phy0_1(bb, cr->fahm_numer_opt,
cr->fahm_numer_opt_m,
para->fahm_numer_opt);
BB_DBG(bb, DBG_ENV_MNTR,
"Update FAHM numer_opt ((%d)) -> ((%d))\n",
env->fahm_numer_opt, para->fahm_numer_opt);
env->fahm_numer_opt = para->fahm_numer_opt;
}
/*Set denominator_opt*/
if (para->fahm_denom_opt != env->fahm_denom_opt) {
halbb_set_reg_phy0_1(bb, cr->fahm_denom_opt,
cr->fahm_denom_opt_m,
para->fahm_denom_opt);
BB_DBG(bb, DBG_ENV_MNTR,
"Update FAHM denom_opt ((%d)) -> ((%d))\n",
env->fahm_denom_opt, para->fahm_denom_opt);
env->fahm_denom_opt = para->fahm_denom_opt;
}
/*Set FAHM threshold*/
if (halbb_fahm_th_update_chk(bb, para, &fahm_th[0])) {
env->fahm_app = para->fahm_app;
halbb_mem_cpy(bb, &env->fahm_th[0], &fahm_th, FAHM_TH_NUM);
/*Set FAHM th*/
halbb_fahm_set_th_reg(bb);
}
return HALBB_SET_SUCCESS;
}
void halbb_fahm_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
struct ccx_para_info para = {0};
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
env->fahm_app = FAHM_INIT;
env->fahm_numer_opt = 0;
env->fahm_denom_opt = 0;
env->fahm_mntr_time = 0;
/*r_fahm_en_ofdm = r_fahm_en_cck = 1, or fahm report will be 0.*/
halbb_set_reg_phy0_1(bb, cr->fahm_ofdm_en, cr->fahm_ofdm_en_m, true);
halbb_set_reg_phy0_1(bb, cr->fahm_cck_en, cr->fahm_cck_en_m, true);
/*r_fahm_pwdb_sel = 1:select max path*/
halbb_set_reg_phy0_1(bb, cr->fahm_method_sel, cr->fahm_method_sel_m,
0x1);
/*r_fahm_dis_count_each_mpdu = 1, or fa report will abnormal*/
halbb_set_reg_phy0_1(bb, cr->fahm_dis_count_each_mpdu,
cr->fahm_dis_count_each_mpdu_m, true);
}
void halbb_fahm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct ccx_para_info para;
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
u8 end_i = 0;
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if ((_os_strcmp(input[1], "-h") == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"FAHM Get Result: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Basic-Trigger(11k/1900ms): {1}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger(11k): {2} {0~2097ms} {numer_opt} {denom_opt}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger(RSSI): {3} {0~2097ms} {numer_opt} {denom_opt}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger(Manual): {4} {0~2097ms} {numer_opt} {denom_opt} {th[0]} {th_ofst:1~12}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"numer_opt/denom_opt: {BIT 0/1/2} = {FA/CRC32_OK/CRC32_ERR}\n");
} else if (var[0] == 100) { /*Get FAHM results*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ccx_rpt_stamp=%d, ccx_period=%d\n",
env->ccx_rpt_stamp, env->ccx_period);
if (halbb_fahm_get_result(bb)) {
if ((bb->ic_type == BB_RTL8852A) ||
(bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C))
end_i = FAHM_RPT_NUM - 1;
else
end_i = FAHM_RPT_NUM;
for (i = 0; i < end_i; i++)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"fahm_sw_result[%d] = %d (%d percent)\n",
i, env->fahm_sw_result[i],
env->fahm_rpt[i]);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"fahm_ratio=%d, fahm_pwr(RSSI)=%d\n",
env->fahm_ratio, env->fahm_pwr);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"fahm_denominator result = %d (%d percent)\n",
env->fahm_denom_result,
env->fahm_denom_ratio);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "Get FAHM_rpt Fail\n");
}
halbb_ccx_racing_release(bb);
env->ccx_manual_ctrl = false;
} else { /*FAMH trigger*/
env->ccx_manual_ctrl = true;
for (i = 1; i < 9; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]);
}
if (var[0] == 1) {
para.fahm_app = FAHM_DBG_11K;
para.mntr_time = 1900;
para.fahm_numer_opt = FAHM_INCLU_FA;
para.fahm_denom_opt = FAHM_INCLU_CRC_ERR;
} else if (var[0] == 2) {
para.fahm_app = FAHM_DBG_11K;
para.mntr_time = (u16)var[1];
para.fahm_numer_opt = (u8)var[2];
para.fahm_denom_opt = (u8)var[3];
} else if (var[0] == 3) {
para.fahm_app = FAHM_DBG_RSSI;
para.mntr_time = (u16)var[1];
para.fahm_numer_opt = (u8)var[2];
para.fahm_denom_opt = (u8)var[3];
} else {
para.fahm_app = FAHM_DBG_MANUAL;
para.mntr_time = (u16)var[1];
para.fahm_numer_opt = (u8)var[2];
para.fahm_denom_opt = (u8)var[3];
para.fahm_manual_th0 = (u8)var[4];
para.fahm_manual_th_ofst = (u8)var[5];
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"manual_th_ofst=%d, manaul_th_0=%d\n",
para.fahm_manual_th_ofst,
para.fahm_manual_th0);
}
para.rac_lv = RAC_LV_4;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"app=%d, lv=%d, time=%d ms, numer_opt=%d, denom_opt=%d\n",
para.fahm_app, para.rac_lv, para.mntr_time,
para.fahm_numer_opt, para.fahm_denom_opt);
if (halbb_fahm_set(bb, ¶) == HALBB_SET_SUCCESS) {
halbb_ccx_trigger(bb);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "ccx_rpt_stamp=%d\n",
env->ccx_rpt_stamp);
for (i = 0; i < FAHM_TH_NUM; i++) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"FAHM_th[%d] RSSI = %d\n", i,
FAHM_TH_2_RSSI(env->fahm_th[i]));
}
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "FAHM mntr set fail!\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif
#ifdef EDCCA_CLM_SUPPORT
void halbb_edcca_clm_get_utility(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
env->edcca_clm_ratio = (u8)halbb_ccx_get_ratio(bb,
env->edcca_clm_result, 100);
}
bool
halbb_edcca_clm_get_result(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
if (!(halbb_get_reg(bb, cr->edcca_clm_rdy, cr->edcca_clm_rdy_m))) {
BB_DBG(bb, DBG_ENV_MNTR, "Get EDCCA_CLM report Fail\n");
return false;
}
env->edcca_clm_result = (u16)halbb_get_reg(bb, cr->edcca_clm_cnt,
cr->edcca_clm_cnt_m);
BB_DBG(bb, DBG_ENV_MNTR, "EDCCA_CLM result = %d\n",
env->edcca_clm_result);
halbb_edcca_clm_get_utility(bb);
return true;
}
bool halbb_edcca_clm_set(struct bb_info *bb, struct ccx_para_info *para)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
u32 period = 0;
u32 unit_idx = 0;
if (para->mntr_time == 0) {
BB_DBG(bb, DBG_ENV_MNTR, "[WARNING] MNTR_TIME is 0\n");
return HALBB_SET_FAIL;
}
if (halbb_ccx_racing_ctrl(bb, para->rac_lv) == HALBB_SET_FAIL)
return HALBB_SET_FAIL;
/*Set unit & period*/
if (para->mntr_time != env->edcca_clm_mntr_time) {
halbb_ccx_ms_2_period_unit(bb, para->mntr_time, &period,
&unit_idx);
halbb_set_reg_phy0_1(bb, cr->edcca_clm_period,
cr->edcca_clm_period_m, period);
halbb_set_reg_phy0_1(bb, cr->edcca_clm_unit_idx,
cr->edcca_clm_unit_idx_m, unit_idx);
BB_DBG(bb, DBG_ENV_MNTR,
"Update EDCCA-CLM time ((%d)) -> ((%d))\n",
env->edcca_clm_mntr_time, para->mntr_time);
env->edcca_clm_mntr_time = para->mntr_time;
env->ccx_period = (u16)period;
env->ccx_unit_idx = (u8)unit_idx;
}
halbb_ccx_edcca_opt_set(bb, para->ccx_edcca_opt_sc_idx);
env->edcca_clm_app = para->edcca_clm_app;
return HALBB_SET_SUCCESS;
}
void halbb_edcca_clm_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
env->edcca_clm_app = EDCCA_CLM_INIT;
env->edcca_clm_mntr_time = 0;
}
void halbb_edcca_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
struct ccx_para_info para = {0};
u8 i = 0;
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]);
}
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"EDCCA-CLM Get Result: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"EDCCA-CLM Basic-Trigger(1900ms): {1}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"EDCCA-CLM Adv-Trigger: {2} {0~2097ms} {edcca_opt:0(seg0_p0), 1~7(others)}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"edcca_opt: 0~3:seg0(p0/s1/s2/s3), 4~7:seg1(p0/s1/s2/s3)\n");
} else if (var[0] == 100) { /*Get EDCCA-CLM results */
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ccx_rpt_stamp=%d, ccx_period=%d\n",
env->ccx_rpt_stamp, env->ccx_period);
if (halbb_edcca_clm_get_result(bb)) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"edcca_clm_result = %d (%d percent)\n",
env->edcca_clm_result,
env->edcca_clm_ratio);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"Get EDCCA_CLM_rpt Fail\n");
}
halbb_ccx_racing_release(bb);
env->ccx_manual_ctrl = false;
} else { /* Set & trigger CLM */
env->ccx_manual_ctrl = true;
if (var[0] == 1) {
para.mntr_time = 1900;
para.ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0;
} else if (var[0] == 2) {
para.mntr_time = (u16)var[1];
para.ccx_edcca_opt_sc_idx = (enum ccx_edcca_opt_sc_idx)var[2];
}
para.edcca_clm_app = EDCCA_CLM_DBG;
para.rac_lv = RAC_LV_4;
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"app=%d, lv=%d, time=%d ms, edcca_opt=%d\n",
para.edcca_clm_app, para.rac_lv, para.mntr_time,
para.ccx_edcca_opt_sc_idx);
if (halbb_edcca_clm_set(bb, ¶) == HALBB_SET_SUCCESS) {
halbb_ccx_trigger(bb);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "ccx_rpt_stamp=%d\n",
env->ccx_rpt_stamp);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"EDCCA_CLM mntr set fail!\n");
}
}
*_used = used;
*_out_len = out_len;
}
#endif
bool
halbb_env_mntr_init_app_chk(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
bool chk_result = HALBB_SET_FAIL;
if ((env->clm_app == CLM_INIT) && (env->nhm_app == NHM_INIT) &&
(env->fahm_app == FAHM_INIT) &&
(env->ifs_clm_app == IFS_CLM_INIT) &&
(env->edcca_clm_app == EDCCA_CLM_INIT))
chk_result = HALBB_SET_SUCCESS;
return chk_result;
}
bool
halbb_env_mntr_dig_app_chk(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
bool is_dig = false;
bool is_tdma_dig = false;
bool chk_result = HALBB_SET_FAIL;
if ((env->clm_app == CLM_DIG) && (env->nhm_app == NHM_DIG) &&
(env->fahm_app == FAHM_DIG) && (env->ifs_clm_app == IFS_CLM_DIG) &&
(env->edcca_clm_app == EDCCA_CLM_DIG))
is_dig = true;
if ((env->clm_app == CLM_TDMA_DIG) && (env->nhm_app == NHM_TDMA_DIG) &&
(env->fahm_app == FAHM_TDMA_DIG) &&
(env->ifs_clm_app == IFS_CLM_TDMA_DIG) &&
(env->edcca_clm_app == EDCCA_CLM_TDMA_DIG))
is_tdma_dig = true;
if (is_dig || is_tdma_dig)
chk_result = HALBB_SET_SUCCESS;
return chk_result;
}
bool
halbb_env_mntr_bg_app_chk(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
bool chk_result = HALBB_SET_FAIL;
if ((env->clm_app == CLM_BACKGROUND) &&
(env->nhm_app == NHM_BACKGROUND) &&
(env->fahm_app == FAHM_BACKGROUND) &&
(env->ifs_clm_app == IFS_CLM_BACKGROUND) &&
(env->edcca_clm_app == EDCCA_CLM_BACKGROUND))
chk_result = HALBB_SET_SUCCESS;
return chk_result;
}
void halbb_env_mntr_cmn_log(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
if ((env->ccx_watchdog_result == CCX_FAIL) &&
(!halbb_env_mntr_dig_app_chk(bb))) {
BB_DBG(bb, DBG_CMN,
"Env_mntr get CCX result failed and app is not DIG!\n");
return;
}
BB_DBG(bb, DBG_CMN,
"{Tx, Idle, CCA_p20, CCA_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n",
env->nhm_tx_ratio, env->nhm_idle_ratio, env->nhm_cca_ratio,
env->clm_ratio, env->edcca_clm_ratio);
BB_DBG(bb, DBG_CMN, "{FA, CRC_err} = {%d, %d} %%\n", env->fahm_ratio,
env->fahm_denom_ratio);
BB_DBG(bb, DBG_CMN, "FA{CCK, OFDM} = {%d, %d} %%\n",env->ifs_clm_cck_fa_ratio,
env->ifs_clm_ofdm_fa_ratio);
BB_DBG(bb, DBG_CMN, "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n",
env->ifs_clm_cck_cca_excl_fa_ratio,
env->ifs_clm_ofdm_cca_excl_fa_ratio);
if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
BB_DBG(bb, DBG_CMN,
"%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
" Th", NHM_TH_2_RSSI(env->nhm_th[9]),
NHM_TH_2_RSSI(env->nhm_th[8]), NHM_TH_2_RSSI(env->nhm_th[7]),
NHM_TH_2_RSSI(env->nhm_th[6]), NHM_TH_2_RSSI(env->nhm_th[5]),
NHM_TH_2_RSSI(env->nhm_th[4]), NHM_TH_2_RSSI(env->nhm_th[3]),
NHM_TH_2_RSSI(env->nhm_th[2]), NHM_TH_2_RSSI(env->nhm_th[1]),
NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG(bb, DBG_CMN,
"[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->nhm_pwr, env->nhm_rpt[10],env->nhm_rpt[9],
env->nhm_rpt[8], env->nhm_rpt[7],env->nhm_rpt[6],
env->nhm_rpt[5], env->nhm_rpt[4], env->nhm_rpt[3],
env->nhm_rpt[2], env->nhm_rpt[1], env->nhm_rpt[0]);
BB_DBG(bb, DBG_CMN,
"[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->fahm_pwr, env->fahm_rpt[10], env->fahm_rpt[9],
env->fahm_rpt[8], env->fahm_rpt[7], env->fahm_rpt[6],
env->fahm_rpt[5], env->fahm_rpt[4], env->fahm_rpt[3],
env->fahm_rpt[2], env->fahm_rpt[1], env->fahm_rpt[0]);
} else {
BB_DBG(bb, DBG_CMN,
"%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
" Th", NHM_TH_2_RSSI(env->nhm_th[10]),
NHM_TH_2_RSSI(env->nhm_th[9]), NHM_TH_2_RSSI(env->nhm_th[8]),
NHM_TH_2_RSSI(env->nhm_th[7]), NHM_TH_2_RSSI(env->nhm_th[6]),
NHM_TH_2_RSSI(env->nhm_th[5]), NHM_TH_2_RSSI(env->nhm_th[4]),
NHM_TH_2_RSSI(env->nhm_th[3]), NHM_TH_2_RSSI(env->nhm_th[2]),
NHM_TH_2_RSSI(env->nhm_th[1]), NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG(bb, DBG_CMN,
"[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->nhm_pwr, env->nhm_rpt[11], env->nhm_rpt[10],
env->nhm_rpt[9], env->nhm_rpt[8], env->nhm_rpt[7],
env->nhm_rpt[6], env->nhm_rpt[5], env->nhm_rpt[4],
env->nhm_rpt[3], env->nhm_rpt[2], env->nhm_rpt[1],
env->nhm_rpt[0]);
BB_DBG(bb, DBG_CMN,
"[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->fahm_pwr, env->fahm_rpt[11], env->fahm_rpt[10],
env->fahm_rpt[9], env->fahm_rpt[8], env->fahm_rpt[7],
env->fahm_rpt[6], env->fahm_rpt[5], env->fahm_rpt[4],
env->fahm_rpt[3], env->fahm_rpt[2], env->fahm_rpt[1],
env->fahm_rpt[0]);
}
BB_DBG(bb, DBG_CMN, "nhm_ratio = %d %%\n", env->nhm_ratio);
BB_DBG(bb, DBG_CMN,
"[IFS] Time(us):[his, ifs_avg(us), cca_avg(us)], total cnt=%d\n",
env->ifs_clm_total_ifs);
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG(bb, DBG_CMN,
" *[%d](%04d~%04d):[%03d, %04d, %04d]\n",
i + 1, halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_l[i]),
halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_h[i]),
env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
env->ifs_clm_cca_avg[i]);
}
void halbb_env_mntr_log(struct bb_info *bb, u32 dbg_comp)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 i = 0;
if (bb->bb_watchdog_mode != BB_WATCHDOG_NORMAL)
return;
if (dbg_comp == DBG_CMN) {
halbb_env_mntr_cmn_log(bb);
return;
}
if ((env->ccx_watchdog_result == CCX_FAIL) &&
(!halbb_env_mntr_dig_app_chk(bb))) {
BB_DBG(bb, DBG_ENV_MNTR,
"Env_mntr get CCX result failed and app is not DIG!\n");
return;
}
BB_DBG(bb, DBG_ENV_MNTR,
"{Tx, Idle, CCA_p20, CCA_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n",
env->nhm_tx_ratio, env->nhm_idle_ratio, env->nhm_cca_ratio,
env->clm_ratio, env->edcca_clm_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "{FA, CRC_err} = {%d, %d} %%\n", env->fahm_ratio,
env->fahm_denom_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "FA{CCK, OFDM} = {%d, %d} %%\n",
env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n",
env->ifs_clm_cck_cca_excl_fa_ratio,
env->ifs_clm_ofdm_cca_excl_fa_ratio);
if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
BB_DBG(bb, DBG_ENV_MNTR,
"%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
" Th", NHM_TH_2_RSSI(env->nhm_th[9]),
NHM_TH_2_RSSI(env->nhm_th[8]), NHM_TH_2_RSSI(env->nhm_th[7]),
NHM_TH_2_RSSI(env->nhm_th[6]), NHM_TH_2_RSSI(env->nhm_th[5]),
NHM_TH_2_RSSI(env->nhm_th[4]), NHM_TH_2_RSSI(env->nhm_th[3]),
NHM_TH_2_RSSI(env->nhm_th[2]), NHM_TH_2_RSSI(env->nhm_th[1]),
NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG(bb, DBG_ENV_MNTR,
"[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->nhm_pwr, env->nhm_rpt[10],env->nhm_rpt[9],
env->nhm_rpt[8], env->nhm_rpt[7],env->nhm_rpt[6],
env->nhm_rpt[5], env->nhm_rpt[4], env->nhm_rpt[3],
env->nhm_rpt[2], env->nhm_rpt[1], env->nhm_rpt[0]);
BB_DBG(bb, DBG_ENV_MNTR,
"[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->fahm_pwr, env->fahm_rpt[10], env->fahm_rpt[9],
env->fahm_rpt[8], env->fahm_rpt[7], env->fahm_rpt[6],
env->fahm_rpt[5], env->fahm_rpt[4], env->fahm_rpt[3],
env->fahm_rpt[2], env->fahm_rpt[1], env->fahm_rpt[0]);
} else {
BB_DBG(bb, DBG_ENV_MNTR,
"%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
" Th", NHM_TH_2_RSSI(env->nhm_th[10]),
NHM_TH_2_RSSI(env->nhm_th[9]), NHM_TH_2_RSSI(env->nhm_th[8]),
NHM_TH_2_RSSI(env->nhm_th[7]), NHM_TH_2_RSSI(env->nhm_th[6]),
NHM_TH_2_RSSI(env->nhm_th[5]), NHM_TH_2_RSSI(env->nhm_th[4]),
NHM_TH_2_RSSI(env->nhm_th[3]), NHM_TH_2_RSSI(env->nhm_th[2]),
NHM_TH_2_RSSI(env->nhm_th[1]), NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG(bb, DBG_ENV_MNTR,
"[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->nhm_pwr, env->nhm_rpt[11], env->nhm_rpt[10],
env->nhm_rpt[9], env->nhm_rpt[8], env->nhm_rpt[7],
env->nhm_rpt[6], env->nhm_rpt[5], env->nhm_rpt[4],
env->nhm_rpt[3], env->nhm_rpt[2], env->nhm_rpt[1],
env->nhm_rpt[0]);
BB_DBG(bb, DBG_ENV_MNTR,
"[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
env->fahm_pwr, env->fahm_rpt[11], env->fahm_rpt[10],
env->fahm_rpt[9], env->fahm_rpt[8], env->fahm_rpt[7],
env->fahm_rpt[6], env->fahm_rpt[5], env->fahm_rpt[4],
env->fahm_rpt[3], env->fahm_rpt[2], env->fahm_rpt[1],
env->fahm_rpt[0]);
}
BB_DBG(bb, DBG_ENV_MNTR, "nhm_ratio = %d %%\n", env->nhm_ratio);
BB_DBG(bb, DBG_ENV_MNTR,
"[IFS] Time(us):[his, ifs_avg(us), cca_avg(us)], total cnt=%d\n",
env->ifs_clm_total_ifs);
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG(bb, DBG_ENV_MNTR,
" *[%d](%04d~%04d):[%03d, %04d, %04d]\n",
i + 1, halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_l[i]),
halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_h[i]),
env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
env->ifs_clm_cca_avg[i]);
}
void halbb_env_mntr_get_bg_result(struct bb_info *bb,
struct env_mntr_rpt *bg_rpt,
enum phl_phy_idx phy_idx)
{
struct bb_env_mntr_info *env = NULL;
#ifdef HALBB_DBCC_SUPPORT
bb = halbb_get_curr_bb_pointer(bb, phy_idx);
BB_DBG(bb, DBG_ENV_MNTR, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
#endif
env = &bb->bb_env_mntr_i;
halbb_mem_cpy(bb, bg_rpt, &env->env_mntr_rpt_bg,
sizeof(struct env_mntr_rpt));
}
void halbb_env_mntr_get_bg_setting(struct bb_info *bb,
struct ccx_para_info *bg_para,
enum phl_phy_idx phy_idx)
{
struct bb_env_mntr_info *env = NULL;
#ifdef HALBB_DBCC_SUPPORT
bb = halbb_get_curr_bb_pointer(bb, phy_idx);
BB_DBG(bb, DBG_ENV_MNTR, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
#endif
env = &bb->bb_env_mntr_i;
halbb_mem_cpy(bb, bg_para, &env->ccx_para_info_bg,
sizeof(struct ccx_para_info));
}
u8 halbb_env_mntr_trigger(struct bb_info *bb, struct ccx_para_info *para,
struct env_trig_rpt *trig_rpt)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u8 trigger_result = CCX_FAIL;
BB_DBG(bb, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
if (halbb_clm_set(bb, para))
trigger_result |= CLM_SUCCESS;
if (halbb_nhm_set(bb, para))
trigger_result |= NHM_SUCCESS;
if (halbb_fahm_set(bb, para))
trigger_result |= FAHM_SUCCESS;
if (halbb_ifs_clm_set(bb, para))
trigger_result |= IFS_CLM_SUCCESS;
if (halbb_edcca_clm_set(bb, para))
trigger_result |= EDCCA_CLM_SUCCESS;
if (trigger_result)
halbb_ccx_trigger(bb);
/*monitor for the test duration*/
env->start_time = halbb_get_sys_time(bb);
trig_rpt->ccx_rpt_stamp = env->ccx_rpt_stamp;
/*update bg structure*/
if (halbb_env_mntr_bg_app_chk(bb) || halbb_env_mntr_dig_app_chk(bb))
halbb_mem_cpy(bb, &env->ccx_para_info_bg, para,
sizeof(struct ccx_para_info));
BB_DBG(bb, DBG_ENV_MNTR, "ccx_rpt_stamp=%d, trigger_result=0x%x\n",
trig_rpt->ccx_rpt_stamp, trigger_result);
return trigger_result;
}
u8 halbb_env_mntr_result(struct bb_info *bb, struct env_mntr_rpt *rpt)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u64 progressing_time = 0;
u8 i = 0;
/*monitor for the test duration*/
progressing_time = halbb_get_sys_time(bb);
BB_DBG(bb, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
BB_DBG(bb, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time);
rpt->ccx_rpt_result = CCX_FAIL;
/*Get CLM result*/
if (halbb_clm_get_result(bb)) {
rpt->clm_ratio = env->clm_ratio;
rpt->clm_result = env->clm_result;
rpt->ccx_rpt_result |= CLM_SUCCESS;
} else {
rpt->clm_ratio = ENV_MNTR_FAIL_BYTE;
rpt->clm_result = ENV_MNTR_FAIL_WORD;
}
/*Get NHM result*/
if (halbb_nhm_get_result(bb)) {
rpt->nhm_ratio = env->nhm_ratio;
rpt->nhm_tx_ratio = env->nhm_tx_ratio;
rpt->nhm_cca_ratio = env->nhm_cca_ratio;
rpt->nhm_idle_ratio = env->nhm_idle_ratio;
rpt->nhm_tx_cnt = env->nhm_tx_cnt;
rpt->nhm_cca_cnt = env->nhm_cca_cnt;
rpt->nhm_idle_cnt = env->nhm_idle_cnt;
rpt->nhm_pwr = env->nhm_pwr;
rpt->ccx_rpt_result |= NHM_SUCCESS;
halbb_mem_cpy(bb, &rpt->nhm_rpt[0], &env->nhm_rpt[0],
NHM_RPT_NUM);
} else {
rpt->nhm_ratio = ENV_MNTR_FAIL_BYTE;
rpt->nhm_tx_ratio = ENV_MNTR_FAIL_BYTE;
rpt->nhm_cca_ratio = ENV_MNTR_FAIL_BYTE;
rpt->nhm_idle_ratio = ENV_MNTR_FAIL_BYTE;
rpt->nhm_pwr = ENV_MNTR_FAIL_BYTE;
for (i = 0; i < NHM_RPT_NUM; i++)
rpt->nhm_rpt[i] = ENV_MNTR_FAIL_BYTE;
}
/*Get FAHM result*/
if (halbb_fahm_get_result(bb)) {
rpt->fahm_ratio = env->fahm_ratio;
rpt->fahm_denom_ratio = env->fahm_denom_ratio;
rpt->fahm_pwr = env->fahm_pwr;
rpt->ccx_rpt_result |= FAHM_SUCCESS;
halbb_mem_cpy(bb, &rpt->fahm_rpt[0], &env->fahm_rpt[0],
FAHM_RPT_NUM);
} else {
rpt->fahm_ratio = ENV_MNTR_FAIL_BYTE;
rpt->fahm_denom_ratio = ENV_MNTR_FAIL_BYTE;
rpt->fahm_pwr = ENV_MNTR_FAIL_BYTE;
for (i = 0; i < FAHM_RPT_NUM; i++)
rpt->fahm_rpt[i] = ENV_MNTR_FAIL_BYTE;
}
/*Get IFS_CLM result*/
if (halbb_ifs_clm_get_result(bb)) {
rpt->ifs_clm_tx_ratio = env->ifs_clm_tx_ratio;
rpt->ifs_clm_edcca_excl_cca_ratio = env->ifs_clm_edcca_excl_cca_ratio;
rpt->ifs_clm_cck_fa_ratio = env->ifs_clm_cck_fa_ratio;
rpt->ifs_clm_ofdm_fa_ratio = env->ifs_clm_ofdm_fa_ratio;
rpt->ifs_clm_cck_cca_excl_fa_ratio = env->ifs_clm_cck_cca_excl_fa_ratio;
rpt->ifs_clm_ofdm_cca_excl_fa_ratio = env->ifs_clm_ofdm_cca_excl_fa_ratio;
rpt->ifs_clm_cck_fa_permil = env->ifs_clm_cck_fa_permil;
rpt->ifs_clm_ofdm_fa_permil = env->ifs_clm_ofdm_fa_permil;
rpt->ifs_clm_total_ifs = env->ifs_clm_total_ifs;
for (i = 0; i < IFS_CLM_NUM; i++) {
rpt->ifs_clm_his[i] = env->ifs_clm_his[i];
rpt->ifs_clm_ifs_avg[i] = env->ifs_clm_ifs_avg[i];
rpt->ifs_clm_cca_avg[i] = env->ifs_clm_cca_avg[i];
}
rpt->ccx_rpt_result |= IFS_CLM_SUCCESS;
} else {
rpt->ifs_clm_tx_ratio = ENV_MNTR_FAIL_BYTE;
rpt->ifs_clm_edcca_excl_cca_ratio = ENV_MNTR_FAIL_BYTE;
rpt->ifs_clm_cck_fa_ratio = ENV_MNTR_FAIL_BYTE;
rpt->ifs_clm_ofdm_fa_ratio = ENV_MNTR_FAIL_BYTE;
rpt->ifs_clm_cck_cca_excl_fa_ratio = ENV_MNTR_FAIL_BYTE;
rpt->ifs_clm_ofdm_cca_excl_fa_ratio = ENV_MNTR_FAIL_BYTE;
rpt->ifs_clm_cck_fa_permil = ENV_MNTR_FAIL_WORD;
rpt->ifs_clm_ofdm_fa_permil = ENV_MNTR_FAIL_WORD;
rpt->ifs_clm_total_ifs = ENV_MNTR_FAIL_WORD;
for (i = 0; i < IFS_CLM_NUM; i++) {
rpt->ifs_clm_his[i] = ENV_MNTR_FAIL_WORD;
rpt->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
rpt->ifs_clm_cca_avg[i] = ENV_MNTR_FAIL_DWORD;
}
}
/*Get EDCCA_CLM result*/
if (halbb_edcca_clm_get_result(bb)) {
rpt->edcca_clm_ratio = env->edcca_clm_ratio;
rpt->ccx_rpt_result |= EDCCA_CLM_SUCCESS;
} else {
rpt->edcca_clm_ratio = ENV_MNTR_FAIL_BYTE;
}
rpt->ccx_rpt_stamp = env->ccx_rpt_stamp;
BB_DBG(bb, DBG_ENV_MNTR, "ccx_rpt_stamp=%d, ccx_rpt_result=0x%x\n",
rpt->ccx_rpt_stamp, rpt->ccx_rpt_result);
/*update bg structure*/
if (halbb_env_mntr_bg_app_chk(bb) || halbb_env_mntr_dig_app_chk(bb))
halbb_mem_cpy(bb, &env->env_mntr_rpt_bg, rpt,
sizeof(struct env_mntr_rpt));
halbb_ccx_racing_release(bb);
return rpt->ccx_rpt_result;
}
/*Environment Monitor*/
bool
halbb_env_mntr_watchdog_chk(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
u32 sys_return_time = 0;
bool chk_result = HALBB_SET_FAIL;
sys_return_time = env->ccx_trigger_time + MAX_ENV_MNTR_TIME;
if ((!halbb_env_mntr_bg_app_chk(bb)) &&
(!halbb_env_mntr_init_app_chk(bb)) &&
(sys_return_time > bb->bb_sys_up_time)) {
BB_DBG(bb, DBG_ENV_MNTR,
"APP:{CLM, NHM, FAHM, IFS_CLM, EDCCA} = {%d, %d, %d, %d, %d}\n",
env->clm_app, env->nhm_app, env->fahm_app,
env->ifs_clm_app, env->edcca_clm_app);
BB_DBG(bb, DBG_ENV_MNTR, "trigger_time=%d, sys_time=%d\n",
env->ccx_trigger_time, bb->bb_sys_up_time);
} else {
chk_result = HALBB_SET_SUCCESS;
}
return chk_result;
}
void halbb_idle_time_pwr_physts(struct bb_info *bb, struct physts_rxd *desc, bool is_cck_rate)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_physts_info *physts = &bb->bb_physts_i;
u16 idle_pwr = 0; /*u(8,1)*/
if (is_cck_rate)
idle_pwr = physts->bb_physts_rslt_0_i.avg_idle_noise_pwr_cck;
else
idle_pwr = physts->bb_physts_rslt_1_i.avg_idle_noise_pwr;
BB_DBG(bb, DBG_PHY_STS, "cck=%d, idle_pwr=%d.%d, nhm_pwr=%d\n",
is_cck_rate, idle_pwr >> 1, (idle_pwr & 1) * 5, env->nhm_pwr);
if (idle_pwr > (env->nhm_pwr + 10) && env->nhm_pwr != 0)
return;
if (env->idle_pwr_physts != 0)
env->idle_pwr_physts = MA_ACC(env->idle_pwr_physts, idle_pwr, 2, RSSI_MA_L);
else
env->idle_pwr_physts = idle_pwr << RSSI_MA_L;
BB_DBG(bb, DBG_PHY_STS, "idle_pwr_physts=%d (%d.%03d)\n",
env->idle_pwr_physts, env->idle_pwr_physts >> 3, (env->idle_pwr_physts & 0x7) * 125);
}
void halbb_env_mntr(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct ccx_para_info para = {0};
struct env_mntr_rpt rpt = {0};
struct env_trig_rpt trig_rpt = {0};
u8 chk_result = CCX_FAIL;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
env->ccx_watchdog_result = CCX_FAIL;
if (!(bb->support_ability & BB_ENVMNTR))
return;
if (env->ccx_manual_ctrl) {
BB_DBG(bb, DBG_ENV_MNTR, "CCX in manual ctrl\n");
return;
}
if (halbb_env_mntr_watchdog_chk(bb)) {
/*get result*/
env->ccx_watchdog_result = halbb_env_mntr_result(bb, &rpt);
/*set parameter*/
para.mntr_time = 1900;
para.rac_lv = RAC_LV_1;
para.ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0;
para.clm_app = CLM_BACKGROUND;
para.clm_input_opt = CLM_CCA_S80_S40_S20;
para.nhm_app = NHM_BACKGROUND;
para.nhm_incld_cca = NHM_EXCLUDE_CCA;
para.fahm_app = FAHM_BACKGROUND;
para.fahm_numer_opt = FAHM_INCLU_FA;
para.fahm_denom_opt = FAHM_INCLU_CRC_ERR;
para.ifs_clm_app = IFS_CLM_BACKGROUND;
para.edcca_clm_app = EDCCA_CLM_BACKGROUND;
chk_result = halbb_env_mntr_trigger(bb, ¶, &trig_rpt);
}
BB_DBG(bb, DBG_ENV_MNTR, "get_result=0x%x, chk_result:0x%x\n",
env->ccx_watchdog_result, chk_result);
BB_DBG(bb, DBG_ENV_MNTR, "CCX Summary:\n");
halbb_env_mntr_log(bb, DBG_ENV_MNTR);
}
void halbb_env_mntr_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
BB_DBG(bb, DBG_ENV_MNTR, "[%s]===>\n", __func__);
halbb_ccx_top_setting_init(bb);
halbb_clm_init(bb);
halbb_nhm_init(bb);
halbb_ifs_clm_init(bb);
halbb_fahm_init(bb);
halbb_edcca_clm_init(bb);
env->idle_pwr_physts= 0;
}
void halbb_env_mntr_bg_log(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct ccx_para_info para = {0};
struct env_mntr_rpt rpt = {0};
u8 i = 0;
halbb_env_mntr_get_bg_setting(bb, ¶, phy_idx);
halbb_env_mntr_get_bg_result(bb, &rpt, phy_idx);
/*bg_para*/
BB_DBG(bb, DBG_ENV_MNTR,
"rac_lv = %d, mntr_time = %d, edcca_opt_sc_idx = %d\n",
para.rac_lv, para.mntr_time, para.ccx_edcca_opt_sc_idx);
BB_DBG(bb, DBG_ENV_MNTR,
"APP:{CLM, NHM, FAHM, IFS_CLM, EDCCA} = {%d, %d, %d, %d, %d}\n",
para.clm_app, para.nhm_app, para.fahm_app, para.ifs_clm_app,
para.edcca_clm_app);
BB_DBG(bb, DBG_ENV_MNTR, "clm_input_opt = %d, nhm_inclu_cca = %d\n",
para.clm_input_opt, para.nhm_incld_cca);
BB_DBG(bb, DBG_ENV_MNTR, "fahm_numer_opt = %d, fahm_denom_opt = %d\n",
para.fahm_numer_opt, para.fahm_denom_opt);
/*bg_rpt*/
BB_DBG(bb, DBG_ENV_MNTR, "ccx_rpt_stamp = %d\n", rpt.ccx_rpt_stamp);
BB_DBG(bb, DBG_ENV_MNTR,
"{Tx, Idle, CCA_p20, CCA_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n",
rpt.nhm_tx_ratio, rpt.nhm_idle_ratio, rpt.nhm_cca_ratio,
rpt.clm_ratio, rpt.edcca_clm_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "{FA, CRC_err} = {%d, %d} %%\n",
rpt.fahm_ratio, rpt.fahm_denom_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "FA{CCK, OFDM} = {%d, %d} %%\n",
rpt.ifs_clm_cck_fa_ratio, rpt.ifs_clm_ofdm_fa_ratio);
BB_DBG(bb, DBG_ENV_MNTR, "CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n",
rpt.ifs_clm_cck_cca_excl_fa_ratio,
rpt.ifs_clm_ofdm_cca_excl_fa_ratio);
if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
BB_DBG(bb, DBG_ENV_MNTR,
"%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
" Th", NHM_TH_2_RSSI(env->nhm_th[9]),
NHM_TH_2_RSSI(env->nhm_th[8]),
NHM_TH_2_RSSI(env->nhm_th[7]),
NHM_TH_2_RSSI(env->nhm_th[6]),
NHM_TH_2_RSSI(env->nhm_th[5]),
NHM_TH_2_RSSI(env->nhm_th[4]),
NHM_TH_2_RSSI(env->nhm_th[3]),
NHM_TH_2_RSSI(env->nhm_th[2]),
NHM_TH_2_RSSI(env->nhm_th[1]),
NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG(bb, DBG_ENV_MNTR,
"[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.nhm_pwr, rpt.nhm_rpt[10], rpt.nhm_rpt[9],
rpt.nhm_rpt[8], rpt.nhm_rpt[7], rpt.nhm_rpt[6],
rpt.nhm_rpt[5], rpt.nhm_rpt[4], rpt.nhm_rpt[3],
rpt.nhm_rpt[2], rpt.nhm_rpt[1], rpt.nhm_rpt[0]);
BB_DBG(bb, DBG_ENV_MNTR,
"[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.fahm_pwr, rpt.fahm_rpt[10], rpt.fahm_rpt[9],
rpt.fahm_rpt[8], rpt.fahm_rpt[7], rpt.fahm_rpt[6],
rpt.fahm_rpt[5], rpt.fahm_rpt[4], rpt.fahm_rpt[3],
rpt.fahm_rpt[2], rpt.fahm_rpt[1], rpt.fahm_rpt[0]);
} else {
BB_DBG(bb, DBG_ENV_MNTR,
"%-16s[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
" Th", NHM_TH_2_RSSI(env->nhm_th[10]),
NHM_TH_2_RSSI(env->nhm_th[9]),
NHM_TH_2_RSSI(env->nhm_th[8]),
NHM_TH_2_RSSI(env->nhm_th[7]),
NHM_TH_2_RSSI(env->nhm_th[6]),
NHM_TH_2_RSSI(env->nhm_th[5]),
NHM_TH_2_RSSI(env->nhm_th[4]),
NHM_TH_2_RSSI(env->nhm_th[3]),
NHM_TH_2_RSSI(env->nhm_th[2]),
NHM_TH_2_RSSI(env->nhm_th[1]),
NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG(bb, DBG_ENV_MNTR,
"[NHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.nhm_pwr, rpt.nhm_rpt[11], rpt.nhm_rpt[10],
rpt.nhm_rpt[9], rpt.nhm_rpt[8], rpt.nhm_rpt[7],
rpt.nhm_rpt[6], rpt.nhm_rpt[5], rpt.nhm_rpt[4],
rpt.nhm_rpt[3], rpt.nhm_rpt[2], rpt.nhm_rpt[1],
rpt.nhm_rpt[0]);
BB_DBG(bb, DBG_ENV_MNTR,
"[FAHM] (pwr:%02d)[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.fahm_pwr, rpt.fahm_rpt[11], rpt.fahm_rpt[10],
rpt.fahm_rpt[9], rpt.fahm_rpt[8], rpt.fahm_rpt[7],
rpt.fahm_rpt[6], rpt.fahm_rpt[5], rpt.fahm_rpt[4],
rpt.fahm_rpt[3], rpt.fahm_rpt[2], rpt.fahm_rpt[1],
rpt.fahm_rpt[0]);
}
BB_DBG(bb, DBG_ENV_MNTR, "nhm_ratio = %d %%\n", rpt.nhm_ratio);
BB_DBG(bb, DBG_ENV_MNTR,
"[IFS] Time(us):[his, ifs_avg(us), cca_avg(us)], total cnt=%d\n",
rpt.ifs_clm_total_ifs);
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG(bb, DBG_ENV_MNTR,
" *[%d](%04d~%04d):[%03d, %04d, %04d]\n", i + 1,
halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_l[i]),
halbb_ccx_idx_cnt_2_us(bb, env->ifs_clm_th_h[i]),
rpt.ifs_clm_his[i], rpt.ifs_clm_ifs_avg[i],
rpt.ifs_clm_cca_avg[i]);
}
void halbb_env_mntr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
struct ccx_para_info para = {0};
struct env_mntr_rpt rpt = {0};
struct env_trig_rpt trig_rpt = {0};
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
enum phl_phy_idx phy_idx = HW_PHY_0;
u8 set_result = CCX_FAIL;
u8 i = 0;
for (i = 0; i < 2; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &var[i]);
}
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Basic-Trigger(1900ms): {1}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Adv-Trigger: {2} {0~2097ms}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Get Result: {100}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Get Background Result: {101} {phy_idx}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Show noise {noise}\n");
} else if (var[0] == 100) { /* Get results */
set_result = halbb_env_mntr_result(bb, &rpt);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Result=0x%x, ccx_rpt_stamp=%d\n",
set_result, rpt.ccx_rpt_stamp);
if (set_result) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"{tx, idle, cca_p20, cca_sec, EDCCA_p20} = {%d, %d, %d, %d, %d} %%\n",
rpt.nhm_tx_ratio, rpt.nhm_idle_ratio,
rpt.nhm_cca_ratio, rpt.clm_ratio,
rpt.edcca_clm_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"{FA, CRC32 error} = {%d, %d} %%\n",
rpt.fahm_ratio, rpt.fahm_denom_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"FA{CCK, OFDM} = {%d, %d} %%\n",
rpt.ifs_clm_cck_fa_ratio,
rpt.ifs_clm_ofdm_fa_ratio);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"CCA_exclu_FA{CCK, OFDM} = {%d, %d} %%\n",
rpt.ifs_clm_cck_cca_excl_fa_ratio,
rpt.ifs_clm_ofdm_cca_excl_fa_ratio);
if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B) ||
(bb->ic_type == BB_RTL8852C)) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"NHM/FAHM_th(RSSI)[H->L] = [%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
NHM_TH_2_RSSI(env->nhm_th[9]),
NHM_TH_2_RSSI(env->nhm_th[8]),
NHM_TH_2_RSSI(env->nhm_th[7]),
NHM_TH_2_RSSI(env->nhm_th[6]),
NHM_TH_2_RSSI(env->nhm_th[5]),
NHM_TH_2_RSSI(env->nhm_th[4]),
NHM_TH_2_RSSI(env->nhm_th[3]),
NHM_TH_2_RSSI(env->nhm_th[2]),
NHM_TH_2_RSSI(env->nhm_th[1]),
NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"NHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.nhm_rpt[10], rpt.nhm_rpt[9],
rpt.nhm_rpt[8], rpt.nhm_rpt[7],
rpt.nhm_rpt[6], rpt.nhm_rpt[5],
rpt.nhm_rpt[4], rpt.nhm_rpt[3],
rpt.nhm_rpt[2], rpt.nhm_rpt[1],
rpt.nhm_rpt[0]);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"FAHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.fahm_rpt[10], rpt.fahm_rpt[9],
rpt.fahm_rpt[8], rpt.fahm_rpt[7],
rpt.fahm_rpt[6], rpt.fahm_rpt[5],
rpt.fahm_rpt[4], rpt.fahm_rpt[3],
rpt.fahm_rpt[2], rpt.fahm_rpt[1],
rpt.fahm_rpt[0]);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"NHM/FAHM_th(RSSI)[H->L] = [%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
NHM_TH_2_RSSI(env->nhm_th[10]),
NHM_TH_2_RSSI(env->nhm_th[9]),
NHM_TH_2_RSSI(env->nhm_th[8]),
NHM_TH_2_RSSI(env->nhm_th[7]),
NHM_TH_2_RSSI(env->nhm_th[6]),
NHM_TH_2_RSSI(env->nhm_th[5]),
NHM_TH_2_RSSI(env->nhm_th[4]),
NHM_TH_2_RSSI(env->nhm_th[3]),
NHM_TH_2_RSSI(env->nhm_th[2]),
NHM_TH_2_RSSI(env->nhm_th[1]),
NHM_TH_2_RSSI(env->nhm_th[0]));
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"NHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.nhm_rpt[11], rpt.nhm_rpt[10],
rpt.nhm_rpt[9], rpt.nhm_rpt[8],
rpt.nhm_rpt[7], rpt.nhm_rpt[6],
rpt.nhm_rpt[5], rpt.nhm_rpt[4],
rpt.nhm_rpt[3], rpt.nhm_rpt[2],
rpt.nhm_rpt[1], rpt.nhm_rpt[0]);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"FAHM rpt(percent)[H->L]=[%.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d %.2d]\n",
rpt.fahm_rpt[11], rpt.fahm_rpt[10],
rpt.fahm_rpt[9], rpt.fahm_rpt[8],
rpt.fahm_rpt[7], rpt.fahm_rpt[6],
rpt.fahm_rpt[5], rpt.fahm_rpt[4],
rpt.fahm_rpt[3], rpt.fahm_rpt[2],
rpt.fahm_rpt[1], rpt.fahm_rpt[0]);
}
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"nhm_ratio = %d %%, nhm_pwr(RSSI) = %d, fahm_pwr(RSSI)=%d\n",
rpt.nhm_ratio, rpt.nhm_pwr, rpt.fahm_pwr);
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "IFS_total cnt = %d\n",
rpt.ifs_clm_total_ifs);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Time(us):[his, ifs_avg(us), cca_avg(us)]\n");
for (i = 0; i < IFS_CLM_NUM; i++)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used,
"T%d(%d ~ %d):[%d, %d, %d]\n",
i + 1, halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_th_l[i]),
halbb_ccx_idx_cnt_2_us(bb,
env->ifs_clm_th_h[i]),
rpt.ifs_clm_his[i],
rpt.ifs_clm_ifs_avg[i],
rpt.ifs_clm_cca_avg[i]);
} else {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "Get CCX_rpt all Fail\n");
}
env->ccx_manual_ctrl = false;
} else if (var[0] == 101) { /* Get bg results */
phy_idx = (enum phl_phy_idx)var[1];
halbb_env_mntr_bg_log(bb, phy_idx);
} else if (_os_strcmp(input[1], "noise") == 0) {
/*This command is used for customers, do not modify it arbitrarily*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"noise=%d(dBm)\n", env->nhm_pwr - 110);
} else { /* Set & trigger*/
env->ccx_manual_ctrl = true;
if (var[0] == 1)
para.mntr_time = 1900;
else if (var[0] == 2)
para.mntr_time = (u16)var[1];
para.rac_lv = RAC_LV_4;
/*clm para*/
para.clm_app = CLM_DBG;
para.clm_input_opt = CLM_CCA_S80_S40_S20;
/*nhm para*/
para.nhm_app = NHM_DBG_11K;
para.nhm_incld_cca = NHM_EXCLUDE_CCA;
/*fahm para*/
para.fahm_app = FAHM_DBG_11K;
para.fahm_numer_opt = FAHM_INCLU_FA;
para.fahm_denom_opt = FAHM_INCLU_CRC_ERR;
/*ifs_clm para*/
para.ifs_clm_app = IFS_CLM_DBG;
/*edcca_clm para*/
para.edcca_clm_app = EDCCA_CLM_DBG;
para.ccx_edcca_opt_sc_idx = CCX_EDCCA_SEG0_P0;
set_result = halbb_env_mntr_trigger(bb, ¶, &trig_rpt);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Result=0x%x, ccx_rpt_stamp=%d\n",
set_result, trig_rpt.ccx_rpt_stamp);
}
*_used = used;
*_out_len = out_len;
}
u8 halbb_env_mntr_get_802_11_k_rsni(struct bb_info *bb, s8 rcpi, s8 anpi)
{
u8 rsni = 0;
u8 signal = 0;
u8 sig_to_rsni[13] = {0, 8, 15, 20, 24, 27, 30, 32, 35, 37, 39, 41, 43};
/*rcpi = signal + noise + interference = rssi*/
/*anpi = noise + interferecne = nhm*/
/*signal = rcpi - anpi*/
/*rsni = 2*(10*log10((rcpi_lin/anpi_lin)-1)+10), unit = 0.5dB*/
/*rcpi_lin/anpi_lin=10^((rcpi_dB-anpi_db)/10)*/
/*rsni is approximated as 2*((rcpi_db-anpi_db)+10) when signal >= 13*/
if (rcpi <= anpi)
signal = 0;
else if (rcpi - anpi >= 117)
signal = 117;
else
signal = rcpi - anpi;
if (signal < 13)
rsni = sig_to_rsni[signal];
else
rsni = 2 * (signal + 10);
return rsni;
}
void halbb_cr_cfg_env_mntr_init(struct bb_info *bb)
{
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_env_mntr_cr_info *cr = &env->bb_env_mntr_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->ccx_en = CCX_EN_A;
cr->ccx_en_m = CCX_EN_A_M;
cr->ccx_trig_opt = CCX_TRIG_OPT_A;
cr->ccx_trig_opt_m = CCX_TRIG_OPT_A_M;
cr->ccx_trig = MEASUREMENT_TRIG_A;
cr->ccx_trig_m = MEASUREMENT_TRIG_A_M;
cr->ccx_edcca_opt = CCX_EDCCA_OPT_A;
cr->ccx_edcca_opt_m = CCX_EDCCA_OPT_A_M;
cr->clm_unit_idx = CLM_COUNTER_UNIT_A;
cr->clm_unit_idx_m = CLM_COUNTER_UNIT_A_M;
cr->clm_opt = CLM_CCA_OPT_A;
cr->clm_opt_m = CLM_CCA_OPT_A_M;
cr->clm_period = CLM_PERIOD_A;
cr->clm_period_m = CLM_PERIOD_A_M;
cr->clm_dbg_sel = CLM_FROM_DBG_SEL_A;
cr->clm_dbg_sel_m = CLM_FROM_DBG_SEL_A_M;
cr->clm_cnt = RO_CLM_RESULT_A;
cr->clm_cnt_m = RO_CLM_RESULT_A_M;
cr->clm_rdy = RO_CLM_RDY_A;
cr->clm_rdy_m = RO_CLM_RDY_A_M;
cr->edcca_clm_period = CLM_EDCCA_PERIOD_A;
cr->edcca_clm_period_m = CLM_EDCCA_PERIOD_A_M;
cr->edcca_clm_unit_idx = CLM_EDCCA_COUNTER_UNIT_A;
cr->edcca_clm_unit_idx_m = CLM_EDCCA_COUNTER_UNIT_A_M;
cr->edcca_clm_cnt = RO_CLM_EDCCA_RESULT_A;
cr->edcca_clm_cnt_m = RO_CLM_EDCCA_RESULT_A_M;
cr->edcca_clm_rdy = RO_CLM_EDCCA_RDY_A;
cr->edcca_clm_rdy_m = RO_CLM_EDCCA_RDY_A_M;
cr->nhm_en = NHM_EN_A;
cr->nhm_en_m = NHM_EN_A_M;
cr->nhm_method_sel = NHM_PWDB_METHOD_SEL_A;
cr->nhm_method_sel_m = NHM_PWDB_METHOD_SEL_A_M;
cr->nhm_period = NHM_PERIOD_A;
cr->nhm_period_m = NHM_PERIOD_A_M;
cr->nhm_unit_idx = NHM_COUNTER_UNIT_A;
cr->nhm_unit_idx_m = NHM_COUNTER_UNIT_A_M;
cr->nhm_inclu_cca = NHM_IGNORE_CCA_A;
cr->nhm_inclu_cca_m = NHM_IGNORE_CCA_A_M;
cr->nhm_th0 = NHM_TH0_A;
cr->nhm_th0_m = NHM_TH0_A_M;
cr->nhm_th1 = NHM_TH1_A;
cr->nhm_th1_m = NHM_TH1_A_M;
cr->nhm_th2 = NHM_TH2_A;
cr->nhm_th2_m = NHM_TH2_A_M;
cr->nhm_th3 = NHM_TH3_A;
cr->nhm_th3_m = NHM_TH3_A_M;
cr->nhm_th4 = NHM_TH4_A;
cr->nhm_th4_m = NHM_TH4_A_M;
cr->nhm_th5 = NHM_TH5_A;
cr->nhm_th5_m = NHM_TH5_A_M;
cr->nhm_th6 = NHM_TH6_A;
cr->nhm_th6_m = NHM_TH6_A_M;
cr->nhm_th7 = NHM_TH7_A;
cr->nhm_th7_m = NHM_TH7_A_M;
cr->nhm_th8 = NHM_TH8_A;
cr->nhm_th8_m = NHM_TH8_A_M;
cr->nhm_th9 = NHM_TH9_A;
cr->nhm_th9_m = NHM_TH9_A_M;
cr->nhm_th10 = NHM_TH10_A;
cr->nhm_th10_m = NHM_TH10_A_M;
cr->nhm_cnt0 = NHM_CNT0_A;
cr->nhm_cnt0_m = NHM_CNT0_A_M;
cr->nhm_cnt1 = NHM_CNT1_A;
cr->nhm_cnt1_m = NHM_CNT1_A_M;
cr->nhm_cnt2 = NHM_CNT2_A;
cr->nhm_cnt2_m = NHM_CNT2_A_M;
cr->nhm_cnt3 = NHM_CNT3_A;
cr->nhm_cnt3_m = NHM_CNT3_A_M;
cr->nhm_cnt4 = NHM_CNT4_A;
cr->nhm_cnt4_m = NHM_CNT4_A_M;
cr->nhm_cnt5 = NHM_CNT5_A;
cr->nhm_cnt5_m = NHM_CNT5_A_M;
cr->nhm_cnt6 = NHM_CNT6_A;
cr->nhm_cnt6_m = NHM_CNT6_A_M;
cr->nhm_cnt7 = NHM_CNT7_A;
cr->nhm_cnt7_m = NHM_CNT7_A_M;
cr->nhm_cnt8 = NHM_CNT8_A;
cr->nhm_cnt8_m = NHM_CNT8_A_M;
cr->nhm_cnt9 = NHM_CNT9_A;
cr->nhm_cnt9_m = NHM_CNT9_A_M;
cr->nhm_cnt10 = NHM_CNT10_A;
cr->nhm_cnt10_m = NHM_CNT10_A_M;
cr->nhm_cnt11 = NHM_CNT11_A;
cr->nhm_cnt11_m = NHM_CNT11_A_M;
cr->nhm_cca_cnt = NHM_CCA_CNT_A;
cr->nhm_cca_cnt_m = NHM_CCA_CNT_A_M;
cr->nhm_tx_cnt = NHM_TXON_CNT_A;
cr->nhm_tx_cnt_m = NHM_TXON_CNT_A_M;
cr->nhm_idle_cnt = NHM_IDLE_CNT_A;
cr->nhm_idle_cnt_m = NHM_IDLE_CNT_A_M;
cr->nhm_rdy = NHM_RDY_A;
cr->nhm_rdy_m = NHM_RDY_A_M;
cr->fahm_ofdm_en = FAHM_EN_OFDM_A;
cr->fahm_ofdm_en_m = FAHM_EN_OFDM_A_M;
cr->fahm_cck_en = FAHM_EN_CCK_A;
cr->fahm_cck_en_m = FAHM_EN_CCK_A_M;
cr->fahm_numer_opt = FAHM_NUM_CANDIDATE_A;
cr->fahm_numer_opt_m = FAHM_NUM_CANDIDATE_A_M;
cr->fahm_denom_opt = FAHM_DEN_CANDIDATE_A;
cr->fahm_denom_opt_m = FAHM_DEN_CANDIDATE_A_M;
cr->fahm_period = FAHM_PERIOD_A;
cr->fahm_period_m = FAHM_PERIOD_A_M;
cr->fahm_unit_idx = FAHM_COUNTER_UNIT_A;
cr->fahm_unit_idx_m = FAHM_COUNTER_UNIT_A_M;
cr->fahm_method_sel = FAHM_PWDB_SEL_A;
cr->fahm_method_sel_m = FAHM_PWDB_SEL_A_M;
cr->fahm_th0 = FAHM_TH0_A;
cr->fahm_th0_m = FAHM_TH0_A_M;
cr->fahm_th1 = FAHM_TH1_A;
cr->fahm_th1_m = FAHM_TH1_A_M;
cr->fahm_th2 = FAHM_TH2_A;
cr->fahm_th2_m = FAHM_TH2_A_M;
cr->fahm_th3 = FAHM_TH3_A;
cr->fahm_th3_m = FAHM_TH3_A_M;
cr->fahm_th4 = FAHM_TH4_A;
cr->fahm_th4_m = FAHM_TH4_A_M;
cr->fahm_th5 = FAHM_TH5_A;
cr->fahm_th5_m = FAHM_TH5_A_M;
cr->fahm_th6 = FAHM_TH6_A;
cr->fahm_th6_m = FAHM_TH6_A_M;
cr->fahm_th7 = FAHM_TH7_A;
cr->fahm_th7_m = FAHM_TH7_A_M;
cr->fahm_th8 = FAHM_TH8_A;
cr->fahm_th8_m = FAHM_TH8_A_M;
cr->fahm_th9 = FAHM_TH9_A;
cr->fahm_th9_m = FAHM_TH9_A_M;
cr->fahm_th10 = FAHM_TH10_A;
cr->fahm_th10_m = FAHM_TH10_A_M;
cr->fahm_dis_count_each_mpdu = FAHM_DIS_COUNT_EACH_MPDU_A;
cr->fahm_dis_count_each_mpdu_m = FAHM_DIS_COUNT_EACH_MPDU_A_M;
cr->fahm_cnt0 = RO_FAHM_NUM0_A;
cr->fahm_cnt0_m = RO_FAHM_NUM0_A_M;
cr->fahm_cnt1 = RO_FAHM_NUM1_A;
cr->fahm_cnt1_m = RO_FAHM_NUM1_A_M;
cr->fahm_cnt2 = RO_FAHM_NUM2_A;
cr->fahm_cnt2_m = RO_FAHM_NUM2_A_M;
cr->fahm_cnt3 = RO_FAHM_NUM3_A;
cr->fahm_cnt3_m = RO_FAHM_NUM3_A_M;
cr->fahm_cnt4 = RO_FAHM_NUM4_A;
cr->fahm_cnt4_m = RO_FAHM_NUM4_A_M;
cr->fahm_cnt5 = RO_FAHM_NUM5_A;
cr->fahm_cnt5_m = RO_FAHM_NUM5_A_M;
cr->fahm_cnt6 = RO_FAHM_NUM6_A;
cr->fahm_cnt6_m = RO_FAHM_NUM6_A_M;
cr->fahm_cnt7 = RO_FAHM_NUM7_A;
cr->fahm_cnt7_m = RO_FAHM_NUM7_A_M;
cr->fahm_cnt8 = RO_FAHM_NUM8_A;
cr->fahm_cnt8_m = RO_FAHM_NUM8_A_M;
cr->fahm_cnt9 = RO_FAHM_NUM9_A;
cr->fahm_cnt9_m = RO_FAHM_NUM9_A_M;
cr->fahm_cnt10 = RO_FAHM_NUM10_A;
cr->fahm_cnt10_m = RO_FAHM_NUM10_A_M;
cr->fahm_cnt11 = RO_FAHM_NUM11_A;
cr->fahm_cnt11_m = RO_FAHM_NUM11_A_M;
cr->fahm_denom_cnt = RO_FAHM_DEN_A;
cr->fahm_denom_cnt_m = RO_FAHM_DEN_A_M;
cr->fahm_rdy = RO_FAHM_RDY_A;
cr->fahm_rdy_m = RO_FAHM_RDY_A_M;
cr->ifs_clm_en = IFS_COLLECT_EN_A;
cr->ifs_clm_en_m = IFS_COLLECT_EN_A_M;
cr->ifs_clm_clr = IFS_COUNTER_CLR_A;
cr->ifs_clm_clr_m = IFS_COUNTER_CLR_A_M;
cr->ifs_clm_period = IFS_COLLECT_TOTAL_TIME_A;
cr->ifs_clm_period_m = IFS_COLLECT_TOTAL_TIME_A_M;
cr->ifs_clm_unit_idx = IFS_COUNTER_UNIT_A;
cr->ifs_clm_unit_idx_m = IFS_COUNTER_UNIT_A_M;
cr->ifs_t1_en = IFS_T1_EN_A;
cr->ifs_t1_en_m = IFS_T1_EN_A_M;
cr->ifs_t2_en = IFS_T2_EN_A;
cr->ifs_t2_en_m = IFS_T2_EN_A_M;
cr->ifs_t3_en = IFS_T3_EN_A;
cr->ifs_t3_en_m = IFS_T3_EN_A_M;
cr->ifs_t4_en = IFS_T4_EN_A;
cr->ifs_t4_en_m = IFS_T4_EN_A_M;
cr->ifs_t1_th_l = IFS_T1_TH_LOW_A;
cr->ifs_t1_th_l_m = IFS_T1_TH_LOW_A_M;
cr->ifs_t2_th_l = IFS_T2_TH_LOW_A;
cr->ifs_t2_th_l_m = IFS_T2_TH_LOW_A_M;
cr->ifs_t3_th_l = IFS_T3_TH_LOW_A;
cr->ifs_t3_th_l_m = IFS_T3_TH_LOW_A_M;
cr->ifs_t4_th_l = IFS_T4_TH_LOW_A;
cr->ifs_t4_th_l_m = IFS_T4_TH_LOW_A_M;
cr->ifs_t1_th_h = IFS_T1_TH_HIGH_A;
cr->ifs_t1_th_h_m = IFS_T1_TH_HIGH_A_M;
cr->ifs_t2_th_h = IFS_T2_TH_HIGH_A;
cr->ifs_t2_th_h_m = IFS_T2_TH_HIGH_A_M;
cr->ifs_t3_th_h = IFS_T3_TH_HIGH_A;
cr->ifs_t3_th_h_m = IFS_T3_TH_HIGH_A_M;
cr->ifs_t4_th_h = IFS_T4_TH_HIGH_A;
cr->ifs_t4_th_h_m = IFS_T4_TH_HIGH_A_M;
cr->ifs_clm_tx_cnt = IFSCNT_CNT_TX_A;
cr->ifs_clm_tx_cnt_m = IFSCNT_CNT_TX_A_M;
cr->ifs_clm_edcca_exclu_cca = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_A;
cr->ifs_clm_edcca_exclu_cca_m = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_A_M;
cr->ifs_clm_cckcca_exclu_fa = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_A;
cr->ifs_clm_cckcca_exclu_fa_m = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_A_M;
cr->ifs_clm_ofdmcca_exclu_fa = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_A;
cr->ifs_clm_ofdmcca_exclu_fa_m = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_A_M;
cr->ifs_clm_cck_fa = IFSCNT_CNT_CCKFA_A;
cr->ifs_clm_cck_fa_m = IFSCNT_CNT_CCKFA_A_M;
cr->ifs_clm_ofdm_fa = IFSCNT_CNT_OFDMFA_A;
cr->ifs_clm_ofdm_fa_m = IFSCNT_CNT_OFDMFA_A_M;
cr->ifs_clm_t1_his = IFS_T1_HIS_A;
cr->ifs_clm_t1_his_m = IFS_T1_HIS_A_M;
cr->ifs_clm_t2_his = IFS_T2_HIS_A;
cr->ifs_clm_t2_his_m = IFS_T2_HIS_A_M;
cr->ifs_clm_t3_his = IFS_T3_HIS_A;
cr->ifs_clm_t3_his_m = IFS_T3_HIS_A_M;
cr->ifs_clm_t4_his = IFS_T4_HIS_A;
cr->ifs_clm_t4_his_m = IFS_T4_HIS_A_M;
cr->ifs_clm_t1_avg = IFS_T1_AVG_A;
cr->ifs_clm_t1_avg_m = IFS_T1_AVG_A_M;
cr->ifs_clm_t2_avg = IFS_T2_AVG_A;
cr->ifs_clm_t2_avg_m = IFS_T2_AVG_A_M;
cr->ifs_clm_t3_avg = IFS_T3_AVG_A;
cr->ifs_clm_t3_avg_m = IFS_T3_AVG_A_M;
cr->ifs_clm_t4_avg = IFS_T4_AVG_A;
cr->ifs_clm_t4_avg_m = IFS_T4_AVG_A_M;
cr->ifs_clm_t1_cca = IFS_T1_CLM_A;
cr->ifs_clm_t1_cca_m = IFS_T1_CLM_A_M;
cr->ifs_clm_t2_cca = IFS_T2_CLM_A;
cr->ifs_clm_t2_cca_m = IFS_T2_CLM_A_M;
cr->ifs_clm_t3_cca = IFS_T3_CLM_A;
cr->ifs_clm_t3_cca_m = IFS_T3_CLM_A_M;
cr->ifs_clm_t4_cca = IFS_T4_CLM_A;
cr->ifs_clm_t4_cca_m = IFS_T4_CLM_A_M;
cr->ifs_total_cnt = IFS_TOTAL_A;
cr->ifs_total_cnt_m = IFS_TOTAL_A_M;
cr->ifs_clm_rdy = IFSCNT_DONE_A;
cr->ifs_clm_rdy_m = IFSCNT_DONE_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->ccx_en = CCX_EN_C;
cr->ccx_en_m = CCX_EN_C_M;
cr->ccx_trig_opt = CCX_TRIG_OPT_C;
cr->ccx_trig_opt_m = CCX_TRIG_OPT_C_M;
cr->ccx_trig = MEASUREMENT_TRIG_C;
cr->ccx_trig_m = MEASUREMENT_TRIG_C_M;
cr->ccx_edcca_opt = CCX_EDCCA_OPT_C;
cr->ccx_edcca_opt_m = CCX_EDCCA_OPT_C_M;
cr->clm_unit_idx = CLM_COUNTER_UNIT_C;
cr->clm_unit_idx_m = CLM_COUNTER_UNIT_C_M;
cr->clm_opt = CLM_CCA_OPT_C;
cr->clm_opt_m = CLM_CCA_OPT_C_M;
cr->clm_period = CLM_PERIOD_C;
cr->clm_period_m = CLM_PERIOD_C_M;
cr->clm_dbg_sel = CLM_FROM_DBG_SEL_C;
cr->clm_dbg_sel_m = CLM_FROM_DBG_SEL_C_M;
cr->clm_cnt = RO_CLM_RESULT_C;
cr->clm_cnt_m = RO_CLM_RESULT_C_M;
cr->clm_rdy = RO_CLM_RDY_C;
cr->clm_rdy_m = RO_CLM_RDY_C_M;
cr->edcca_clm_period = CLM_EDCCA_PERIOD_C;
cr->edcca_clm_period_m = CLM_EDCCA_PERIOD_C_M;
cr->edcca_clm_unit_idx = CLM_EDCCA_COUNTER_UNIT_C;
cr->edcca_clm_unit_idx_m = CLM_EDCCA_COUNTER_UNIT_C_M;
cr->edcca_clm_cnt = RO_CLM_EDCCA_RESULT_C;
cr->edcca_clm_cnt_m = RO_CLM_EDCCA_RESULT_C_M;
cr->edcca_clm_rdy = RO_CLM_EDCCA_RDY_C;
cr->edcca_clm_rdy_m = RO_CLM_EDCCA_RDY_C_M;
cr->nhm_en = NHM_EN_C;
cr->nhm_en_m = NHM_EN_C_M;
cr->nhm_method_sel = NHM_PWDB_METHOD_SEL_C;
cr->nhm_method_sel_m = NHM_PWDB_METHOD_SEL_C_M;
cr->nhm_period = NHM_PERIOD_C;
cr->nhm_period_m = NHM_PERIOD_C_M;
cr->nhm_unit_idx = NHM_COUNTER_UNIT_C;
cr->nhm_unit_idx_m = NHM_COUNTER_UNIT_C_M;
cr->nhm_inclu_cca = NHM_IGNORE_CCA_C;
cr->nhm_inclu_cca_m = NHM_IGNORE_CCA_C_M;
cr->nhm_th0 = NHM_TH0_C;
cr->nhm_th0_m = NHM_TH0_C_M;
cr->nhm_th1 = NHM_TH1_C;
cr->nhm_th1_m = NHM_TH1_C_M;
cr->nhm_th2 = NHM_TH2_C;
cr->nhm_th2_m = NHM_TH2_C_M;
cr->nhm_th3 = NHM_TH3_C;
cr->nhm_th3_m = NHM_TH3_C_M;
cr->nhm_th4 = NHM_TH4_C;
cr->nhm_th4_m = NHM_TH4_C_M;
cr->nhm_th5 = NHM_TH5_C;
cr->nhm_th5_m = NHM_TH5_C_M;
cr->nhm_th6 = NHM_TH6_C;
cr->nhm_th6_m = NHM_TH6_C_M;
cr->nhm_th7 = NHM_TH7_C;
cr->nhm_th7_m = NHM_TH7_C_M;
cr->nhm_th8 = NHM_TH8_C;
cr->nhm_th8_m = NHM_TH8_C_M;
cr->nhm_th9 = NHM_TH9_C;
cr->nhm_th9_m = NHM_TH9_C_M;
cr->nhm_th10 = NHM_TH10_C;
cr->nhm_th10_m = NHM_TH10_C_M;
cr->fahm_dis_count_each_mpdu = FAHM_DIS_COUNT_EACH_MPDU_C;
cr->fahm_dis_count_each_mpdu_m = FAHM_DIS_COUNT_EACH_MPDU_C_M;
cr->nhm_cnt0 = NHM_CNT0_C;
cr->nhm_cnt0_m = NHM_CNT0_C_M;
cr->nhm_cnt1 = NHM_CNT1_C;
cr->nhm_cnt1_m = NHM_CNT1_C_M;
cr->nhm_cnt2 = NHM_CNT2_C;
cr->nhm_cnt2_m = NHM_CNT2_C_M;
cr->nhm_cnt3 = NHM_CNT3_C;
cr->nhm_cnt3_m = NHM_CNT3_C_M;
cr->nhm_cnt4 = NHM_CNT4_C;
cr->nhm_cnt4_m = NHM_CNT4_C_M;
cr->nhm_cnt5 = NHM_CNT5_C;
cr->nhm_cnt5_m = NHM_CNT5_C_M;
cr->nhm_cnt6 = NHM_CNT6_C;
cr->nhm_cnt6_m = NHM_CNT6_C_M;
cr->nhm_cnt7 = NHM_CNT7_C;
cr->nhm_cnt7_m = NHM_CNT7_C_M;
cr->nhm_cnt8 = NHM_CNT8_C;
cr->nhm_cnt8_m = NHM_CNT8_C_M;
cr->nhm_cnt9 = NHM_CNT9_C;
cr->nhm_cnt9_m = NHM_CNT9_C_M;
cr->nhm_cnt10 = NHM_CNT10_C;
cr->nhm_cnt10_m = NHM_CNT10_C_M;
cr->nhm_cnt11 = NHM_CNT11_C;
cr->nhm_cnt11_m = NHM_CNT11_C_M;
cr->nhm_cca_cnt = NHM_CCA_CNT_C;
cr->nhm_cca_cnt_m = NHM_CCA_CNT_C_M;
cr->nhm_tx_cnt = NHM_TXON_CNT_C;
cr->nhm_tx_cnt_m = NHM_TXON_CNT_C_M;
cr->nhm_idle_cnt = NHM_IDLE_CNT_C;
cr->nhm_idle_cnt_m = NHM_IDLE_CNT_C_M;
cr->nhm_rdy = NHM_RDY_C;
cr->nhm_rdy_m = NHM_RDY_C_M;
cr->fahm_ofdm_en = FAHM_EN_OFDM_C;
cr->fahm_ofdm_en_m = FAHM_EN_OFDM_C_M;
cr->fahm_cck_en = FAHM_EN_CCK_C;
cr->fahm_cck_en_m = FAHM_EN_CCK_C_M;
cr->fahm_numer_opt = FAHM_NUM_CANDIDATE_C;
cr->fahm_numer_opt_m = FAHM_NUM_CANDIDATE_C_M;
cr->fahm_denom_opt = FAHM_DEN_CANDIDATE_C;
cr->fahm_denom_opt_m = FAHM_DEN_CANDIDATE_C_M;
cr->fahm_period = FAHM_PERIOD_C;
cr->fahm_period_m = FAHM_PERIOD_C_M;
cr->fahm_unit_idx = FAHM_COUNTER_UNIT_C;
cr->fahm_unit_idx_m = FAHM_COUNTER_UNIT_C_M;
cr->fahm_method_sel = FAHM_PWDB_SEL_C;
cr->fahm_method_sel_m = FAHM_PWDB_SEL_C_M;
cr->fahm_th0 = FAHM_TH0_C;
cr->fahm_th0_m = FAHM_TH0_C_M;
cr->fahm_th1 = FAHM_TH1_C;
cr->fahm_th1_m = FAHM_TH1_C_M;
cr->fahm_th2 = FAHM_TH2_C;
cr->fahm_th2_m = FAHM_TH2_C_M;
cr->fahm_th3 = FAHM_TH3_C;
cr->fahm_th3_m = FAHM_TH3_C_M;
cr->fahm_th4 = FAHM_TH4_C;
cr->fahm_th4_m = FAHM_TH4_C_M;
cr->fahm_th5 = FAHM_TH5_C;
cr->fahm_th5_m = FAHM_TH5_C_M;
cr->fahm_th6 = FAHM_TH6_C;
cr->fahm_th6_m = FAHM_TH6_C_M;
cr->fahm_th7 = FAHM_TH7_C;
cr->fahm_th7_m = FAHM_TH7_C_M;
cr->fahm_th8 = FAHM_TH8_C;
cr->fahm_th8_m = FAHM_TH8_C_M;
cr->fahm_th9 = FAHM_TH9_C;
cr->fahm_th9_m = FAHM_TH9_C_M;
cr->fahm_th10 = FAHM_TH10_C;
cr->fahm_th10_m = FAHM_TH10_C_M;
cr->fahm_cnt0 = RO_FAHM_NUM0_C;
cr->fahm_cnt0_m = RO_FAHM_NUM0_C_M;
cr->fahm_cnt1 = RO_FAHM_NUM1_C;
cr->fahm_cnt1_m = RO_FAHM_NUM1_C_M;
cr->fahm_cnt2 = RO_FAHM_NUM2_C;
cr->fahm_cnt2_m = RO_FAHM_NUM2_C_M;
cr->fahm_cnt3 = RO_FAHM_NUM3_C;
cr->fahm_cnt3_m = RO_FAHM_NUM3_C_M;
cr->fahm_cnt4 = RO_FAHM_NUM4_C;
cr->fahm_cnt4_m = RO_FAHM_NUM4_C_M;
cr->fahm_cnt5 = RO_FAHM_NUM5_C;
cr->fahm_cnt5_m = RO_FAHM_NUM5_C_M;
cr->fahm_cnt6 = RO_FAHM_NUM6_C;
cr->fahm_cnt6_m = RO_FAHM_NUM6_C_M;
cr->fahm_cnt7 = RO_FAHM_NUM7_C;
cr->fahm_cnt7_m = RO_FAHM_NUM7_C_M;
cr->fahm_cnt8 = RO_FAHM_NUM8_C;
cr->fahm_cnt8_m = RO_FAHM_NUM8_C_M;
cr->fahm_cnt9 = RO_FAHM_NUM9_C;
cr->fahm_cnt9_m = RO_FAHM_NUM9_C_M;
cr->fahm_cnt10 = RO_FAHM_NUM10_C;
cr->fahm_cnt10_m = RO_FAHM_NUM10_C_M;
cr->fahm_cnt11 = RO_FAHM_NUM11_C;
cr->fahm_cnt11_m = RO_FAHM_NUM11_C_M;
cr->fahm_denom_cnt = RO_FAHM_DEN_C;
cr->fahm_denom_cnt_m = RO_FAHM_DEN_C_M;
cr->fahm_rdy = RO_FAHM_RDY_C;
cr->fahm_rdy_m = RO_FAHM_RDY_C_M;
cr->ifs_clm_en = IFS_COLLECT_EN_C;
cr->ifs_clm_en_m = IFS_COLLECT_EN_C_M;
cr->ifs_clm_clr = IFS_COUNTER_CLR_C;
cr->ifs_clm_clr_m = IFS_COUNTER_CLR_C_M;
cr->ifs_clm_period = IFS_COLLECT_TOTAL_TIME_C;
cr->ifs_clm_period_m = IFS_COLLECT_TOTAL_TIME_C_M;
cr->ifs_clm_unit_idx = IFS_COUNTER_UNIT_C;
cr->ifs_clm_unit_idx_m = IFS_COUNTER_UNIT_C_M;
cr->ifs_t1_en = IFS_T1_EN_C;
cr->ifs_t1_en_m = IFS_T1_EN_C_M;
cr->ifs_t2_en = IFS_T2_EN_C;
cr->ifs_t2_en_m = IFS_T2_EN_C_M;
cr->ifs_t3_en = IFS_T3_EN_C;
cr->ifs_t3_en_m = IFS_T3_EN_C_M;
cr->ifs_t4_en = IFS_T4_EN_C;
cr->ifs_t4_en_m = IFS_T4_EN_C_M;
cr->ifs_t1_th_l = IFS_T1_TH_LOW_C;
cr->ifs_t1_th_l_m = IFS_T1_TH_LOW_C_M;
cr->ifs_t2_th_l = IFS_T2_TH_LOW_C;
cr->ifs_t2_th_l_m = IFS_T2_TH_LOW_C_M;
cr->ifs_t3_th_l = IFS_T3_TH_LOW_C;
cr->ifs_t3_th_l_m = IFS_T3_TH_LOW_C_M;
cr->ifs_t4_th_l = IFS_T4_TH_LOW_C;
cr->ifs_t4_th_l_m = IFS_T4_TH_LOW_C_M;
cr->ifs_t1_th_h = IFS_T1_TH_HIGH_C;
cr->ifs_t1_th_h_m = IFS_T1_TH_HIGH_C_M;
cr->ifs_t2_th_h = IFS_T2_TH_HIGH_C;
cr->ifs_t2_th_h_m = IFS_T2_TH_HIGH_C_M;
cr->ifs_t3_th_h = IFS_T3_TH_HIGH_C;
cr->ifs_t3_th_h_m = IFS_T3_TH_HIGH_C_M;
cr->ifs_t4_th_h = IFS_T4_TH_HIGH_C;
cr->ifs_t4_th_h_m = IFS_T4_TH_HIGH_C_M;
cr->ifs_clm_tx_cnt = IFSCNT_CNT_TX_C;
cr->ifs_clm_tx_cnt_m = IFSCNT_CNT_TX_C_M;
cr->ifs_clm_edcca_exclu_cca = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C;
cr->ifs_clm_edcca_exclu_cca_m = IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C_M;
cr->ifs_clm_cckcca_exclu_fa = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C;
cr->ifs_clm_cckcca_exclu_fa_m = IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C_M;
cr->ifs_clm_ofdmcca_exclu_fa = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C;
cr->ifs_clm_ofdmcca_exclu_fa_m = IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C_M;
cr->ifs_clm_cck_fa = IFSCNT_CNT_CCKFA_C;
cr->ifs_clm_cck_fa_m = IFSCNT_CNT_CCKFA_C_M;
cr->ifs_clm_ofdm_fa = IFSCNT_CNT_OFDMFA_C;
cr->ifs_clm_ofdm_fa_m = IFSCNT_CNT_OFDMFA_C_M;
cr->ifs_clm_t1_his = IFS_T1_HIS_C;
cr->ifs_clm_t1_his_m = IFS_T1_HIS_C_M;
cr->ifs_clm_t2_his = IFS_T2_HIS_C;
cr->ifs_clm_t2_his_m = IFS_T2_HIS_C_M;
cr->ifs_clm_t3_his = IFS_T3_HIS_C;
cr->ifs_clm_t3_his_m = IFS_T3_HIS_C_M;
cr->ifs_clm_t4_his = IFS_T4_HIS_C;
cr->ifs_clm_t4_his_m = IFS_T4_HIS_C_M;
cr->ifs_clm_t1_avg = IFS_T1_AVG_C;
cr->ifs_clm_t1_avg_m = IFS_T1_AVG_C_M;
cr->ifs_clm_t2_avg = IFS_T2_AVG_C;
cr->ifs_clm_t2_avg_m = IFS_T2_AVG_C_M;
cr->ifs_clm_t3_avg = IFS_T3_AVG_C;
cr->ifs_clm_t3_avg_m = IFS_T3_AVG_C_M;
cr->ifs_clm_t4_avg = IFS_T4_AVG_C;
cr->ifs_clm_t4_avg_m = IFS_T4_AVG_C_M;
cr->ifs_clm_t1_cca = IFS_T1_CLM_C;
cr->ifs_clm_t1_cca_m = IFS_T1_CLM_C_M;
cr->ifs_clm_t2_cca = IFS_T2_CLM_C;
cr->ifs_clm_t2_cca_m = IFS_T2_CLM_C_M;
cr->ifs_clm_t3_cca = IFS_T3_CLM_C;
cr->ifs_clm_t3_cca_m = IFS_T3_CLM_C_M;
cr->ifs_clm_t4_cca = IFS_T4_CLM_C;
cr->ifs_clm_t4_cca_m = IFS_T4_CLM_C_M;
cr->ifs_total_cnt = IFS_TOTAL_C;
cr->ifs_total_cnt_m = IFS_TOTAL_C_M;
cr->ifs_clm_rdy = IFSCNT_DONE_C;
cr->ifs_clm_rdy_m = IFSCNT_DONE_C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_env_mntr.c
|
C
|
agpl-3.0
| 116,856
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ENV_MNTR_H__
#define __HALBB_ENV_MNTR_H__
/*--------------------------[Define] ---------------------------------------*/
#define ENV_MNTR_FAIL_BYTE 0xff
#define ENV_MNTR_FAIL_WORD 0xffff
#define ENV_MNTR_FAIL_DWORD 0xffffffff
#define MAX_ENV_MNTR_TIME 8 /*second*/
#define MS_TO_4US_RATIO 250
/*NHM*/
#define RSSI_2_NHM_TH(rssi) ((rssi) << 1) /*NHM_threshold = u(8,1)*/
#define NHM_TH_2_RSSI(th) (th >> 1)
#define NHM_PWR_OFST 20
#define NHM_NOISE_F_TH 60 /*60/2 = 30 = -80 dBm*/
#define NHM_WA_TH 109 /*109 = -1 dBm*/
#define NHM_WA_PWR 26 /*26 - 110 = -84dBm, only for 52A*/
/*FAHM*/
#define RSSI_2_FAHM_TH(rssi) ((rssi) << 1) /*FAHM_threshold = u(8,1)*/
#define FAHM_TH_2_RSSI(th) (th >> 1)
#define FAHM_PWR_OFST 20
#define FAHM_WA_TH 109 /*109 = -1 dBm*/
/*--------------------------[Enum]------------------------------------------*/
enum ccx_unit {
CCX_04_US = 0, /*4us*/
CCX_08_US = 1, /*8us*/
CCX_16_US = 2, /*16us*/
CCX_32_US = 3 /*32us*/
};
enum ccx_func_sel {
NHM_SEL = BIT(0),
CLM_SEL = BIT(1),
FAHM_SEL = BIT(2),
IFS_CLM_SEL = BIT(3),
EDCCA_CLM_SEL = BIT(4),
};
enum ccx_edcca_opt_bw_idx {
CCX_EDCCA_BW20_0 = 0, /*seg0:SC=4*/
CCX_EDCCA_BW20_1 = 1, /*seg0:SC=2*/
CCX_EDCCA_BW20_2 = 2, /*seg0:SC=1*/
CCX_EDCCA_BW20_3 = 3, /*seg0:SC=3*/
CCX_EDCCA_BW20_4 = 4, /*seg1:SC=4*/
CCX_EDCCA_BW20_5 = 5, /*seg1:SC=2*/
CCX_EDCCA_BW20_6 = 6, /*seg1:SC=1*/
CCX_EDCCA_BW20_7 = 7 /*seg2:SC=3*/
};
/*--------------------------[Structure]-------------------------------------*/
struct bb_env_mntr_cr_info {
u32 ccx_en;
u32 ccx_en_m;
u32 ccx_trig_opt;
u32 ccx_trig_opt_m;
u32 ccx_trig;
u32 ccx_trig_m;
u32 ccx_edcca_opt;
u32 ccx_edcca_opt_m;
u32 clm_unit_idx;
u32 clm_unit_idx_m;
u32 clm_opt;
u32 clm_opt_m;
u32 clm_period;
u32 clm_period_m;
u32 clm_dbg_sel;
u32 clm_dbg_sel_m;
u32 clm_cnt;
u32 clm_cnt_m;
u32 clm_rdy;
u32 clm_rdy_m;
u32 edcca_clm_period;
u32 edcca_clm_period_m;
u32 edcca_clm_unit_idx;
u32 edcca_clm_unit_idx_m;
u32 edcca_clm_cnt;
u32 edcca_clm_cnt_m;
u32 edcca_clm_rdy;
u32 edcca_clm_rdy_m;
u32 nhm_en;
u32 nhm_en_m;
u32 nhm_method_sel;
u32 nhm_method_sel_m;
u32 nhm_period;
u32 nhm_period_m;
u32 nhm_unit_idx;
u32 nhm_unit_idx_m;
u32 nhm_inclu_cca;
u32 nhm_inclu_cca_m;
u32 nhm_th0;
u32 nhm_th0_m;
u32 nhm_th1;
u32 nhm_th1_m;
u32 nhm_th2;
u32 nhm_th2_m;
u32 nhm_th3;
u32 nhm_th3_m;
u32 nhm_th4;
u32 nhm_th4_m;
u32 nhm_th5;
u32 nhm_th5_m;
u32 nhm_th6;
u32 nhm_th6_m;
u32 nhm_th7;
u32 nhm_th7_m;
u32 nhm_th8;
u32 nhm_th8_m;
u32 nhm_th9;
u32 nhm_th9_m;
u32 nhm_th10;
u32 nhm_th10_m;
u32 nhm_cnt0;
u32 nhm_cnt0_m;
u32 nhm_cnt1;
u32 nhm_cnt1_m;
u32 nhm_cnt2;
u32 nhm_cnt2_m;
u32 nhm_cnt3;
u32 nhm_cnt3_m;
u32 nhm_cnt4;
u32 nhm_cnt4_m;
u32 nhm_cnt5;
u32 nhm_cnt5_m;
u32 nhm_cnt6;
u32 nhm_cnt6_m;
u32 nhm_cnt7;
u32 nhm_cnt7_m;
u32 nhm_cnt8;
u32 nhm_cnt8_m;
u32 nhm_cnt9;
u32 nhm_cnt9_m;
u32 nhm_cnt10;
u32 nhm_cnt10_m;
u32 nhm_cnt11;
u32 nhm_cnt11_m;
u32 nhm_cca_cnt;
u32 nhm_cca_cnt_m;
u32 nhm_tx_cnt;
u32 nhm_tx_cnt_m;
u32 nhm_idle_cnt;
u32 nhm_idle_cnt_m;
u32 nhm_rdy;
u32 nhm_rdy_m;
u32 fahm_ofdm_en;
u32 fahm_ofdm_en_m;
u32 fahm_cck_en;
u32 fahm_cck_en_m;
u32 fahm_numer_opt;
u32 fahm_numer_opt_m;
u32 fahm_denom_opt;
u32 fahm_denom_opt_m;
u32 fahm_dis_count_each_mpdu;
u32 fahm_dis_count_each_mpdu_m;
u32 fahm_period;
u32 fahm_period_m;
u32 fahm_unit_idx;
u32 fahm_unit_idx_m;
u32 fahm_method_sel;
u32 fahm_method_sel_m;
u32 fahm_th0;
u32 fahm_th0_m;
u32 fahm_th1;
u32 fahm_th1_m;
u32 fahm_th2;
u32 fahm_th2_m;
u32 fahm_th3;
u32 fahm_th3_m;
u32 fahm_th4;
u32 fahm_th4_m;
u32 fahm_th5;
u32 fahm_th5_m;
u32 fahm_th6;
u32 fahm_th6_m;
u32 fahm_th7;
u32 fahm_th7_m;
u32 fahm_th8;
u32 fahm_th8_m;
u32 fahm_th9;
u32 fahm_th9_m;
u32 fahm_th10;
u32 fahm_th10_m;
u32 fahm_cnt0;
u32 fahm_cnt0_m;
u32 fahm_cnt1;
u32 fahm_cnt1_m;
u32 fahm_cnt2;
u32 fahm_cnt2_m;
u32 fahm_cnt3;
u32 fahm_cnt3_m;
u32 fahm_cnt4;
u32 fahm_cnt4_m;
u32 fahm_cnt5;
u32 fahm_cnt5_m;
u32 fahm_cnt6;
u32 fahm_cnt6_m;
u32 fahm_cnt7;
u32 fahm_cnt7_m;
u32 fahm_cnt8;
u32 fahm_cnt8_m;
u32 fahm_cnt9;
u32 fahm_cnt9_m;
u32 fahm_cnt10;
u32 fahm_cnt10_m;
u32 fahm_cnt11;
u32 fahm_cnt11_m;
u32 fahm_denom_cnt;
u32 fahm_denom_cnt_m;
u32 fahm_rdy;
u32 fahm_rdy_m;
u32 ifs_clm_en;
u32 ifs_clm_en_m;
u32 ifs_clm_clr;
u32 ifs_clm_clr_m;
u32 ifs_clm_period;
u32 ifs_clm_period_m;
u32 ifs_clm_unit_idx;
u32 ifs_clm_unit_idx_m;
u32 ifs_t1_en;
u32 ifs_t1_en_m;
u32 ifs_t2_en;
u32 ifs_t2_en_m;
u32 ifs_t3_en;
u32 ifs_t3_en_m;
u32 ifs_t4_en;
u32 ifs_t4_en_m;
u32 ifs_t1_th_l;
u32 ifs_t1_th_l_m;
u32 ifs_t2_th_l;
u32 ifs_t2_th_l_m;
u32 ifs_t3_th_l;
u32 ifs_t3_th_l_m;
u32 ifs_t4_th_l;
u32 ifs_t4_th_l_m;
u32 ifs_t1_th_h;
u32 ifs_t1_th_h_m;
u32 ifs_t2_th_h;
u32 ifs_t2_th_h_m;
u32 ifs_t3_th_h;
u32 ifs_t3_th_h_m;
u32 ifs_t4_th_h;
u32 ifs_t4_th_h_m;
u32 ifs_clm_tx_cnt;
u32 ifs_clm_tx_cnt_m;
u32 ifs_clm_edcca_exclu_cca;
u32 ifs_clm_edcca_exclu_cca_m;
u32 ifs_clm_cckcca_exclu_fa;
u32 ifs_clm_cckcca_exclu_fa_m;
u32 ifs_clm_ofdmcca_exclu_fa;
u32 ifs_clm_ofdmcca_exclu_fa_m;
u32 ifs_clm_cck_fa;
u32 ifs_clm_cck_fa_m;
u32 ifs_clm_ofdm_fa;
u32 ifs_clm_ofdm_fa_m;
u32 ifs_clm_t1_his;
u32 ifs_clm_t1_his_m;
u32 ifs_clm_t2_his;
u32 ifs_clm_t2_his_m;
u32 ifs_clm_t3_his;
u32 ifs_clm_t3_his_m;
u32 ifs_clm_t4_his;
u32 ifs_clm_t4_his_m;
u32 ifs_clm_t1_avg;
u32 ifs_clm_t1_avg_m;
u32 ifs_clm_t2_avg;
u32 ifs_clm_t2_avg_m;
u32 ifs_clm_t3_avg;
u32 ifs_clm_t3_avg_m;
u32 ifs_clm_t4_avg;
u32 ifs_clm_t4_avg_m;
u32 ifs_clm_t1_cca;
u32 ifs_clm_t1_cca_m;
u32 ifs_clm_t2_cca;
u32 ifs_clm_t2_cca_m;
u32 ifs_clm_t3_cca;
u32 ifs_clm_t3_cca_m;
u32 ifs_clm_t4_cca;
u32 ifs_clm_t4_cca_m;
u32 ifs_total_cnt;
u32 ifs_total_cnt_m;
u32 ifs_clm_rdy;
u32 ifs_clm_rdy_m;
};
struct bb_env_mntr_info {
struct bb_env_mntr_cr_info bb_env_mntr_cr_i;
/*sw ctrl*/
u32 ccx_trigger_time;
u64 start_time;
u8 ccx_rpt_stamp;
u8 ccx_watchdog_result;
bool ccx_ongoing;
u8 ccx_rac_lv;
bool ccx_manual_ctrl;
u8 ccx_pre_rssi;
u16 clm_mntr_time; /*0~2097 ms*/
enum clm_application clm_app;
u16 nhm_mntr_time; /*0~2097 ms*/
enum nhm_application nhm_app;
u16 ifs_clm_mntr_time; /*0~2097 ms*/
enum ifs_clm_application ifs_clm_app;
u16 fahm_mntr_time; /*0~2097 ms*/
enum fahm_application fahm_app;
u16 edcca_clm_mntr_time; /*0~2097 ms*/
enum edcca_clm_application edcca_clm_app;
/*hw ctrl*/
u16 ccx_period;
u8 ccx_unit_idx; /*0/1/2/3 : 4/8/16/32 us*/
enum ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
enum clm_opt_input clm_input_opt;
enum nhm_option_cca_all nhm_include_cca;
u8 nhm_th[NHM_TH_NUM];
u16 ifs_clm_th_l[IFS_CLM_NUM];
u16 ifs_clm_th_h[IFS_CLM_NUM];
u8 fahm_numer_opt;
u8 fahm_denom_opt;
u8 fahm_th[FAHM_TH_NUM];
/*hw report*/
u16 clm_result; /*sample cnt*/
u16 nhm_result[NHM_RPT_NUM]; /*sample cnt*/
u16 nhm_tx_cnt; /*sample cnt*/
u16 nhm_cca_cnt; /*sample cnt*/
u16 nhm_idle_cnt; /*sample cnt*/
u16 ifs_clm_tx; /*sample cnt*/
u16 ifs_clm_edcca_excl_cca; /*sample cnt*/
u16 ifs_clm_ofdmfa; /*sample cnt*/
u16 ifs_clm_ofdmcca_excl_fa; /*sample cnt*/
u16 ifs_clm_cckfa; /*sample cnt*/
u16 ifs_clm_cckcca_excl_fa; /*sample cnt*/
u16 ifs_clm_total_ifs; /*cnt*/
u16 ifs_clm_his[IFS_CLM_NUM]; /*cnt*/
u16 ifs_clm_avg[IFS_CLM_NUM]; /*sample cnt*/
u16 ifs_clm_cca[IFS_CLM_NUM]; /*sample cnt*/
u16 fahm_result[FAHM_RPT_NUM]; /*sample cnt*/
u16 fahm_denom_result; /*sample cnt*/
u16 edcca_clm_result; /*sample cnt*/
/*sw report*/
u8 clm_ratio; /*percent*/
u16 nhm_sw_result[NHM_RPT_NUM]; /*sample cnt*/
u8 nhm_wgt[NHM_RPT_NUM]; /*dBm+110*/
u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/
u8 nhm_tx_ratio; /*percent*/
u8 nhm_cca_ratio; /*percent*/
u8 nhm_idle_ratio; /*percent*/
u8 nhm_ratio; /*percent*/
u16 nhm_result_sum; /*sample cnt*/
u8 nhm_pwr; /*dBm+110*/
u8 ifs_clm_tx_ratio; /*percent*/
u8 ifs_clm_edcca_excl_cca_ratio; /*percent*/
u8 ifs_clm_cck_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_fa_ratio; /*percent*/
u8 ifs_clm_cck_cca_excl_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_cca_excl_fa_ratio; /*percent*/
u16 ifs_clm_cck_fa_permil; /*permil*/
u16 ifs_clm_ofdm_fa_permil; /*permil*/
u32 ifs_clm_ifs_avg[IFS_CLM_NUM]; /*us*/
u32 ifs_clm_cca_avg[IFS_CLM_NUM]; /*us*/
u16 fahm_sw_result[FAHM_RPT_NUM]; /*sample cnt*/
u8 fahm_wgt[FAHM_RPT_NUM]; /*dBm+110*/
u8 fahm_rpt[FAHM_RPT_NUM]; /*percent*/
u16 fahm_result_sum; /*sample cnt*/
u8 fahm_ratio; /*percent*/
u8 fahm_denom_ratio; /*percent*/
u8 fahm_pwr; /*dBm+110*/
u8 edcca_clm_ratio; /*percent*/
u8 edcca_noise_bg; /*dBm+110, only for 52A*/
struct env_mntr_rpt env_mntr_rpt_bg;
struct ccx_para_info ccx_para_info_bg;
u16 idle_pwr_physts; /*RSSI u(16,3) Idle time pwr from physts*/
};
/*--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u32 halbb_ccx_idx_cnt_2_us(struct bb_info *bb, u16 idx_cnt);
#ifdef CLM_SUPPORT
void halbb_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef NHM_SUPPORT
void halbb_nhm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef IFS_CLM_SUPPORT
void halbb_ifs_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef FAHM_SUPPORT
void halbb_fahm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef EDCCA_CLM_SUPPORT
void halbb_edcca_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
void halbb_env_mntr_log(struct bb_info *bb, u32 dbg_comp);
void halbb_idle_time_pwr_physts(struct bb_info *bb, struct physts_rxd *desc, bool is_cck_rate);
void halbb_env_mntr(struct bb_info *bb);
void halbb_env_mntr_init(struct bb_info *bb);
void halbb_env_mntr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_env_mntr_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_env_mntr.h
|
C
|
agpl-3.0
| 11,169
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ENV_MNTR_EX_H__
#define __HALBB_ENV_MNTR_EX_H__
/*--------------------------[Define] ---------------------------------------*/
/*NHM*/
#define NHM_TH_NUM 11 /*threshold number of NHM*/
#define NHM_RPT_NUM 12
/*FAHM*/
#define FAHM_INCLU_FA BIT(0)
#define FAHM_INCLU_CRC_OK BIT(1)
#define FAHM_INCLU_CRC_ERR BIT(2)
#define FAHM_TH_NUM 11 /*threshold number of FAHM*/
#define FAHM_RPT_NUM 12
/*IFS-CLM*/
#define IFS_CLM_NUM 4
/*--------------------------[Enum]------------------------------------------*/
enum mntr_result_lv {
CCX_FAIL = 0,
NHM_SUCCESS = BIT(0),
CLM_SUCCESS = BIT(1),
FAHM_SUCCESS = BIT(2),
IFS_CLM_SUCCESS = BIT(3),
EDCCA_CLM_SUCCESS = BIT(4),
CCX_SUCCESS = 0x1f,
};
enum halbb_racing_lv {
RAC_RELEASE = 0,
RAC_LV_1 = 1, /* Low Priority function */
RAC_LV_2 = 2, /* Middle Priority function */
RAC_LV_3 = 3, /* High priority function (ex: Check hang function) */
RAC_LV_4 = 4, /* Debug function (the highest priority) */
RAC_MAX_NUM = 5
};
enum ccx_edcca_opt_sc_idx {
CCX_EDCCA_SEG0_P0 = 0, /*seg0:p20*/
CCX_EDCCA_SEG0_S1 = 1, /*seg0:s20*/
CCX_EDCCA_SEG0_S2 = 2, /*seg0:s40, opposite of p20*/
CCX_EDCCA_SEG0_S3 = 3, /*seg0:s40, opposite of s20*/
CCX_EDCCA_SEG1_P0 = 4, /*seg1:p20*/
CCX_EDCCA_SEG1_S1 = 5, /*seg1:s20*/
CCX_EDCCA_SEG1_S2 = 6, /*seg1:s40, opposite of p20*/
CCX_EDCCA_SEG1_S3 = 7 /*seg1:s40, opposite of s20*/
};
enum nhm_option_cca_all {
NHM_EXCLUDE_CCA = 0,
NHM_INCLUDE_CCA = 1,
NHM_CCA_INIT
};
enum clm_opt_input {
CLM_CCA_P20 = 0,
CLM_CCA_S20 = 1,
CLM_CCA_S40 = 2,
CLM_CCA_S80 = 3,
CLM_FROM_DBG = 4,
CLM_TXON_CCA = 5,
CLM_CCA_S80_S40_S20 = 6,
CLM_CCA_S80_S40_S20_P20 = 7,
CLM_CCA_INIT
};
enum nhm_application {
NHM_INIT = 0,
NHM_BACKGROUND = 1, /*IEEE 11K for background*/
NHM_ACS = 2,
NHM_DIG = 3,
NHM_TDMA_DIG = 4,
NHM_DBG_11K = 5, /*IEEE 11K for dbg cmd*/
NHM_DBG_RSSI = 6, /*nhm_th[0]=rssi-20, th_ofst=3dB*/
NHM_DBG_MANUAL = 7 /*nhm_th[0] & th_ofst is manual*/
};
enum clm_application {
CLM_INIT = 0,
CLM_BACKGROUND = 1,/*default*/
CLM_ACS = 2,
CLM_DIG = 3,
CLM_TDMA_DIG = 4,
CLM_DBG = 5
};
enum ifs_clm_application {
IFS_CLM_INIT = 0,
IFS_CLM_BACKGROUND = 1,/*default*/
IFS_CLM_ACS = 2,
IFS_CLM_DIG = 3,
IFS_CLM_TDMA_DIG = 4,
IFS_CLM_DBG = 5,
IFS_CLM_DBG_MANUAL = 6
};
enum fahm_application {
FAHM_INIT = 0,
FAHM_BACKGROUND = 1, /*IEEE 11K for background*/
FAHM_ACS = 2,
FAHM_DIG = 3,
FAHM_TDMA_DIG = 4,
FAHM_DBG_11K = 5, /*IEEE 11K for dbg cmd*/
FAHM_DBG_RSSI = 6, /*fahm_th[0]=rssi-20, th_ofst=3dB*/
FAHM_DBG_MANUAL = 7 /*fahm_th[0] & th_ofst is manual*/
};
enum edcca_clm_application {
EDCCA_CLM_INIT = 0,
EDCCA_CLM_BACKGROUND = 1,/*default*/
EDCCA_CLM_ACS = 2,
EDCCA_CLM_DIG = 3,
EDCCA_CLM_TDMA_DIG = 4,
EDCCA_CLM_DBG = 5
};
/*--------------------------[Structure]-------------------------------------*/
struct bb_info;
struct env_trig_rpt {
u8 ccx_rpt_stamp;
};
struct env_mntr_rpt {
u8 ccx_rpt_stamp;
u8 ccx_rpt_result;
u8 clm_ratio; /*percent*/
u16 clm_result; /*sample cnt*/
u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/
u8 nhm_ratio; /*percent*/
u8 nhm_tx_ratio; /*percent*/
u8 nhm_cca_ratio; /*percent*/
u8 nhm_idle_ratio; /*percent*/
u16 nhm_tx_cnt; /*sample cnt*/
u16 nhm_cca_cnt; /*sample cnt*/
u16 nhm_idle_cnt; /*sample cnt*/
u8 nhm_pwr; /*dBm+110*/
u8 ifs_clm_tx_ratio; /*percent*/
u8 ifs_clm_edcca_excl_cca_ratio; /*percent*/
u8 ifs_clm_cck_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_fa_ratio; /*percent*/
u8 ifs_clm_cck_cca_excl_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_cca_excl_fa_ratio; /*percent*/
u16 ifs_clm_cck_fa_permil; /*permil*/
u16 ifs_clm_ofdm_fa_permil; /*permil*/
u16 ifs_clm_total_ifs; /*cnt*/
u16 ifs_clm_his[IFS_CLM_NUM]; /*cnt*/
u32 ifs_clm_ifs_avg[IFS_CLM_NUM]; /*us*/
u32 ifs_clm_cca_avg[IFS_CLM_NUM]; /*us*/
u8 fahm_rpt[FAHM_RPT_NUM]; /*percent*/
u8 fahm_ratio; /*percent*/
u8 fahm_denom_ratio; /*percent*/
u8 fahm_pwr; /*dBm+110*/
u8 edcca_clm_ratio; /*percent*/
};
struct ccx_para_info {
enum halbb_racing_lv rac_lv;
u16 mntr_time; /*0~2097ms*/
enum ccx_edcca_opt_sc_idx ccx_edcca_opt_sc_idx;
enum clm_application clm_app;
enum clm_opt_input clm_input_opt;
enum nhm_application nhm_app;
u8 nhm_manual_th_ofst;
u8 nhm_manual_th0; /*dbg manual mode*/
enum nhm_option_cca_all nhm_incld_cca; /*Include CCA*/
enum ifs_clm_application ifs_clm_app;
u32 ifs_clm_manual_th_times;
u32 ifs_clm_manual_th0;/*us*/
enum fahm_application fahm_app;
u8 fahm_manual_th_ofst;
u8 fahm_manual_th0; /*dbg manual mode*/
u8 fahm_numer_opt;
u8 fahm_denom_opt;
enum edcca_clm_application edcca_clm_app;
};
/*--------------------------[Prptotype]-------------------------------------*/
void halbb_env_mntr_get_bg_result(struct bb_info *bb,
struct env_mntr_rpt *bg_rpt,
enum phl_phy_idx phy_idx);
void halbb_env_mntr_get_bg_setting(struct bb_info *bb,
struct ccx_para_info *bg_para,
enum phl_phy_idx phy_idx);
u8 halbb_env_mntr_trigger(struct bb_info *bb, struct ccx_para_info *para,
struct env_trig_rpt *trig_rpt);
u8 halbb_env_mntr_result(struct bb_info *bb, struct env_mntr_rpt *rpt);
u8 halbb_env_mntr_get_802_11_k_rsni(struct bb_info *bb, s8 rcpi, s8 anpi);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_env_mntr_ex.h
|
C
|
agpl-3.0
| 6,313
|