code
stringlengths 1
1.05M
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stringlengths 6
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stringlengths 3
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stringclasses 222
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stringclasses 20
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/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "hal_str_proc.h"
bool hal_is_comment_string(
char *szStr
)
{
if (*szStr == '/' && *(szStr + 1) == '/')
return true;
else
return false;
}
bool hal_get_fractionvalue_fromstring(
char *szStr,
u8 *pInteger,
u8 *pFraction,
u32 *pu4bMove
)
{
char *szScan = szStr;
/* Initialize output. */
*pu4bMove = 0;
*pInteger = 0;
*pFraction = 0;
/* Skip leading space. */
while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
++szScan;
++(*pu4bMove);
}
if (*szScan < '0' || *szScan > '9')
return false;
/* Parse each digit. */
do {
(*pInteger) *= 10;
*pInteger += (*szScan - '0');
++szScan;
++(*pu4bMove);
if (*szScan == '.') {
++szScan;
++(*pu4bMove);
if (*szScan < '0' || *szScan > '9')
return false;
*pFraction += (*szScan - '0') * 10;
++szScan;
++(*pu4bMove);
if (*szScan >= '0' && *szScan <= '9') {
*pFraction += *szScan - '0';
++szScan;
++(*pu4bMove);
}
return true;
}
} while (*szScan >= '0' && *szScan <= '9');
return true;
}
bool hal_is_alpha(char ch_tmp)
{
if ((ch_tmp >= 'a' && ch_tmp <= 'z') ||
(ch_tmp >= 'A' && ch_tmp <= 'Z'))
return true;
else
return false;
}
bool hal_ishexdigit(char ch_tmp)
{
if ((ch_tmp >= '0' && ch_tmp <= '9') ||
(ch_tmp >= 'a' && ch_tmp <= 'f') ||
(ch_tmp >= 'A' && ch_tmp <= 'F'))
return true;
else
return false;
}
bool hal_get_hexvalue_fromstring(
char *szStr,
u32 *pu4bVal,
u32 *pu4bMove
)
{
char *szScan = szStr;
/* Check input parameter. */
if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
PHL_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove);
return false;
}
/* Initialize output. */
*pu4bMove = 0;
*pu4bVal = 0;
/* Skip leading space. */
while (*szScan != '\0' &&
(*szScan == ' ' || *szScan == '\t')) {
szScan++;
(*pu4bMove)++;
}
/* Skip leading '0x' or '0X'. */
if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) {
szScan += 2;
(*pu4bMove) += 2;
}
/* Check if szScan is now pointer to a character for hex digit, */
/* if not, it means this is not a valid hex number. */
if (!hal_ishexdigit(*szScan))
return false;
/* Parse each digit. */
do {
(*pu4bVal) <<= 4;
*pu4bVal += hal_mapchar_tohexdigit(*szScan);
szScan++;
(*pu4bMove)++;
} while (hal_ishexdigit(*szScan));
return true;
}
bool hal_is_allspace_tab(
char *data,
u8 size
)
{
u8 cnt = 0, NumOfSpaceAndTab = 0;
while (size > cnt) {
if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
++NumOfSpaceAndTab;
++cnt;
}
return size == NumOfSpaceAndTab;
}
u32 hal_mapchar_tohexdigit(
char chTmp
)
{
if (chTmp >= '0' && chTmp <= '9')
return chTmp - '0';
else if (chTmp >= 'a' && chTmp <= 'f')
return 10 + (chTmp - 'a');
else if (chTmp >= 'A' && chTmp <= 'F')
return 10 + (chTmp - 'A');
else
return 0;
}
bool hal_parse_fiedstring(char *in_str, u32 *start, char *out_str, char lqualifier, char rqualifier)
{
u32 i = 0, j = 0;
char c = in_str[(*start)++];
if (c != lqualifier)
return false;
i = (*start);
c = in_str[(*start)++];
while (c != rqualifier && c != '\0')
c = in_str[(*start)++];
if (c == '\0')
return false;
j = (*start) - 2;
_os_strncpy((char *)out_str, (const char *)(in_str + i), j - i + 1);
return true;
}
bool hal_get_u1bint_fromstr_indec(char *str, u8 *pint)
{
u16 i = 0;
*pint = 0;
while (str[i] != '\0') {
if (str[i] >= '0' && str[i] <= '9') {
*pint *= 10;
*pint += (str[i] - '0');
} else
return false;
++i;
}
return true;
}
bool hal_get_s1bint_fromstr_indec(char *str, s8 *val)
{
u8 negative = 0;
u16 i = 0;
*val = 0;
while (str[i] != '\0') {
if (i == 0 && (str[i] == '+' || str[i] == '-')) {
if (str[i] == '-')
negative = 1;
} else if (str[i] >= '0' && str[i] <= '9') {
*val *= 10;
*val += (str[i] - '0');
} else
return false;
++i;
}
if (negative)
*val = -*val;
return true;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_str_proc.c
|
C
|
agpl-3.0
| 4,665
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "hal_headers.h"
#define hal_getLinefrombuffer(buffer) _os_strsep(&buffer, "\r\n")
bool hal_is_comment_string(char *szStr);
bool hal_is_alpha(char ch_tmp);
bool hal_ishexdigit(char chTmp);
bool hal_get_hexvalue_fromstring(char *szStr, u32 *pu4bVal, u32 *pu4bMove);
bool hal_get_fractionvalue_fromstring(
char *szStr,
u8 *pInteger,
u8 *pFraction,
u32 *pu4bMove);
bool hal_is_allspace_tab(char *data, u8 size);
u32 hal_mapchar_tohexdigit(char chTmp);
bool hal_parse_fiedstring(char *in_str, u32 *start, char *out_str, char lqualifier, char rqualifier);
bool hal_get_u1bint_fromstr_indec(char *str, u8 *pint);
bool hal_get_s1bint_fromstr_indec(char *str, s8 *val);
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_str_proc.h
|
C
|
agpl-3.0
| 1,352
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_STRUCT_H_
#define _HAL_STRUCT_H_
struct hal_info_t;
#define hal_get_trx_ops(_halinfo) (_halinfo->trx_ops)
/**
* struct hal_trx_ops - hw ic specific operations
*
* @init: the function for initializing IC specific data and hw configuration
* @deinit: the function for deinitializing IC specific data and hw configuration
* @query_tx_res: the function for querying hw tx resource
* @query_rx_res: the function for querying hw rx resource
* @map_hw_tx_chnl: the function for getting mapping hw tx channel
* @qsel_to_tid: the function for converting hw qsel to tid value
* @query_txch_num: the function for querying total hw tx dma channels number
* @query_rxch_num: the function for querying total hw rx dma channels number
* @update_wd: the function for updating wd page for xmit packet
* @update_txbd: the function for updating tx bd for xmit packet
* @tx_start: the function to trigger hw to start tx
* @get_fwcmd_queue_idx: the function to get fwcmd queue idx
* @check_rxrdy: the function check if hw rx buffer is ready to access
* @handle_rxbd_info: the function handling hw rxbd information
* @handle_rx_buffer: the function handling hw rx buffer
* @update_rxbd: the function for updating rx bd for recv packet
* @notify_rxdone: the function to notify hw rx done
* @handle_wp_rpt: the function parsing wp report content
*/
struct hal_trx_ops {
u8 (*map_hw_tx_chnl)(u16 macid, enum rtw_phl_ring_cat cat, u8 band);
u8 (*query_txch_num)(void);
u8 (*query_rxch_num)(void);
#ifdef CONFIG_PCI_HCI
enum rtw_hal_status (*init)(struct hal_info_t *hal, u8 *txbd_buf, u8 *rxbd_buf);
void (*deinit)(struct hal_info_t *hal);
u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
u16 *host_idx, u16 *hw_idx);
u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
u16 *host_idx, u16 *hw_idx);
void (*cfg_dma_io)(struct hal_info_t *hal, u8 en);
void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch);
void (*cfg_wow_txdma)(struct hal_info_t *hal, u8 en);
void (*cfg_txhci)(struct hal_info_t *hal, u8 en);
void (*cfg_rxhci)(struct hal_info_t *hal, u8 en);
void (*clr_rwptr)(struct hal_info_t *hal);
void (*rst_bdram)(struct hal_info_t *hal);
u8 (*poll_txdma_idle)(struct hal_info_t *hal);
void (*cfg_rsvd_ctrl)(struct hal_info_t *hal);
u8 (*qsel_to_tid)(struct hal_info_t *hal, u8 qsel_id, u8 tid_indic);
enum rtw_hal_status
(*update_wd)(struct hal_info_t *hal, struct rtw_phl_pkt_req *req);
enum rtw_hal_status
(*update_txbd)(struct hal_info_t *hal,
struct tx_base_desc *txbd_ring,
struct rtw_wd_page *wd_page,
u8 ch_idx, u16 wd_num);
enum rtw_hal_status
(*tx_start)(struct hal_info_t *hal,
struct tx_base_desc *txbd, u8 dma_ch);
u8 (*get_fwcmd_queue_idx)(void);
u8 (*check_rxrdy)(struct rtw_phl_com_t *phl_com, u8 *rxbuf, u8 dma_ch);
enum rtw_hal_status
(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
u8 *buf, u32 buf_size,
struct rtw_phl_rx_pkt *rxpkt);
u8 (*handle_rxbd_info)(struct hal_info_t *hal, u8 *rxbuf, u16 *buf_size);
enum rtw_hal_status
(*update_rxbd)(struct hal_info_t *hal,
struct rx_base_desc *rxbd,
struct rtw_rx_buf *rx_buf);
enum rtw_hal_status
(*notify_rxdone)(struct hal_info_t *hal,
struct rx_base_desc *rxbd, u8 ch, u16 rxcnt);
u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len,
u8 *sw_retry, u8 *dma_ch, u16 *wp_seq, u8 *txsts);
#endif /*CONFIG_PCI_HCI*/
#ifdef CONFIG_USB_HCI
enum rtw_hal_status (*init)(struct hal_info_t *hal);
void (*deinit)(struct hal_info_t *hal);
enum rtw_hal_status
(*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req,
u8 *wd_buf, u32 *wd_len);
u8 (*get_bulkout_id)(struct hal_info_t *hal, u8 ch_dma, u8 mode);
enum rtw_hal_status
(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
u8 *buf, u32 buf_size,
struct rtw_phl_rx_pkt *rxpkt);
enum rtw_hal_status
(*query_hal_info)(struct hal_info_t *hal, u8 info_id, void *value);
enum rtw_hal_status
(*usb_tx_agg_cfg)(struct hal_info_t *hal, u8* wd_buf, u8 agg_num);
enum rtw_hal_status
(*usb_rx_agg_cfg)(struct hal_info_t *hal, u8 mode, u8 agg_mode,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num);
u8 (*get_fwcmd_queue_idx)(void);
u8 (*get_max_bulkout_wd_num)(struct hal_info_t *hal);
void (*cfg_dma_io)(struct hal_info_t *hal, u8 en);
void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch);
void (*cfg_txhci)(struct hal_info_t *hal, u8 en);
void (*cfg_rxhci)(struct hal_info_t *hal, u8 en);
void (*clr_rwptr)(struct hal_info_t *hal);
void (*rst_bdram)(struct hal_info_t *hal);
void (*cfg_rsvd_ctrl)(struct hal_info_t *hal);
u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len,
u8 *mac_id, u8 *ac_queue, u8 *txsts);
#endif /*CONFIG_USB_HCI*/
#ifdef CONFIG_SDIO_HCI
enum rtw_hal_status (*init)(struct hal_info_t *hal);
void (*deinit)(struct hal_info_t *hal);
u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
u16 *host_idx, u16 *hw_idx);
u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
u16 *host_idx, u16 *hw_idx);
enum rtw_hal_status
(*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req,
u8 *wd_buf, u32 *wd_len);
u8 (*get_fwcmd_queue_idx)(void);
void (*cfg_dma_io)(struct hal_info_t *hal, u8 en);
void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch);
void (*cfg_txhci)(struct hal_info_t *hal, u8 en);
void (*cfg_rxhci)(struct hal_info_t *hal, u8 en);
void (*clr_rwptr)(struct hal_info_t *hal);
void (*rst_bdram)(struct hal_info_t *hal);
void (*cfg_rsvd_ctrl)(struct hal_info_t *hal);
enum rtw_hal_status(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
u8 *buf, u32 buf_size,
struct rtw_phl_rx_pkt *rxpkt);
#endif
};
#define hal_get_ops(_halinfo) (&_halinfo->hal_ops)
struct hal_ops_t {
/*** initialize section ***/
void (*read_chip_version)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
void (*init_hal_spec)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
void (*init_default_value)(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg);
u32 (*hal_hci_configure)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
struct rtw_ic_info *ic_info);
enum rtw_hal_status (*hal_get_efuse)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status (*hal_init)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
void (*hal_deinit)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status (*hal_start)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status (*hal_stop)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status (*hal_cfg_fw)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
char *ic_name,
enum rtw_fw_type fw_type);
#ifdef CONFIG_WOWLAN
enum rtw_hal_status (*hal_wow_init)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status (*hal_wow_deinit)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
#endif /* CONFIG_WOWLAN */
/* MP */
enum rtw_hal_status (*hal_mp_init)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status (*hal_mp_deinit)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
/*IO ops*/
u32 (*read_macreg)(struct hal_info_t *hal,
u32 offset, u32 bit_mask);
void (*write_macreg)(struct hal_info_t *hal,
u32 offset, u32 bit_mask, u32 data);
u32 (*read_bbreg)(struct hal_info_t *hal,
u32 offset, u32 bit_mask);
void (*write_bbreg)(struct hal_info_t *hal,
u32 offset, u32 bit_mask, u32 data);
u32 (*read_rfreg)(struct hal_info_t *hal,
enum rf_path path, u32 offset, u32 bit_mask);
void (*write_rfreg)(struct hal_info_t *hal,
enum rf_path path, u32 offset, u32 bit_mask, u32 data);
#ifdef RTW_WKARD_BUS_WRITE
enum rtw_hal_status (*write_reg_post_cfg)(struct hal_info_t *hal_info,
u32 offset, u32 value);
#endif
/*** interrupt hdl section ***/
void (*enable_interrupt)(struct hal_info_t *hal);
void (*disable_interrupt)(struct hal_info_t *hal);
void (*config_interrupt)(struct hal_info_t *hal, enum rtw_phl_config_int int_mode);
bool (*recognize_interrupt)(struct hal_info_t *hal);
bool (*recognize_halt_c2h_interrupt)(struct hal_info_t *hal);
void (*clear_interrupt)(struct hal_info_t *hal);
u32 (*interrupt_handler)(struct hal_info_t *hal);
void (*restore_interrupt)(struct hal_info_t *hal);
void (*restore_rx_interrupt)(struct hal_info_t *hal);
#ifdef RTW_PHL_BCN //hal_ops_t
enum rtw_hal_status (*cfg_bcn)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
enum rtw_hal_status (*upt_bcn)(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
#endif
enum rtw_hal_status (*pkt_ofld)(struct hal_info_t *hal, u8 *id, u8 op,
u8 *pkt, u16 *len);
enum rtw_hal_status (*pkt_update_ids)(struct hal_info_t *hal,
struct pkt_ofld_entry *entry);
};
struct hal_info_t {
struct rtw_hal_com_t *hal_com;
_os_atomic hal_mac_mem;
struct hal_trx_ops *trx_ops;
struct hal_ops_t hal_ops;
#ifdef CONFIG_PCI_HCI
void *txch_map;
#endif
void *rpr_cfg;
void *mac; /*halmac*/
void *bb;
void *rf;
void *btc;
void *efuse;
enum rtw_rx_fltr_mode rx_fltr_mode;
u8 monitor_mode; /* default: 0 */
};
struct hal_c2h_hdl {
u8 cat;
u8 cls_min;
u8 cls_max;
u32 (*c2h_hdl)(void *hal, struct rtw_c2h_info *c2h);
};
#ifdef CONFIG_PHL_CHANNEL_INFO
struct chinfo_bbcr_cfg {
bool ch_i_phy0_en;
bool ch_i_phy1_en;
bool ch_i_data_src;
bool ch_i_cmprs;
u8 ch_i_grp_num_non_he;
u8 ch_i_grp_num_he;
u8 ch_i_blk_start_idx;
u8 ch_i_blk_end_idx;
u32 ch_i_ele_bitmap;
bool ch_i_type;
u8 ch_i_seg_len;
};
struct ch_rpt_hdr_info {
u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 total_len_m:1;
u8 total_seg_num:7;
#else
u8 total_seg_num:7;
u8 total_len_m:1;
#endif
u8 avg_noise_pow;
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 is_pkt_end:1;
u8 set_valid:1;
u8 n_rx:3;
u8 n_sts:3;
#else
u8 n_sts:3;
u8 n_rx:3;
u8 set_valid:1;
u8 is_pkt_end:1;
#endif
u8 segment_size; /*unit (8Byte)*/
u8 evm[2];
};
struct phy_info_rpt {
u8 rssi[2];
u16 rsvd_0;
u8 rssi_avg;
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 rxsc:4;
u8 rsvd_1:4;
#else
u8 rsvd_1:4;
u8 rxsc:4;
#endif
u16 rsvd_2;
};
struct ch_info_drv_rpt {
u32 raw_data_len;
u8 seg_idx_curr;
};
#endif /* CONFIG_PHL_CHANNEL_INFO */
#endif /*_HAL_STRUCT_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_struct.h
|
C
|
agpl-3.0
| 11,342
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_THERMAL_C_
#include "hal_headers.h"
#ifdef CONFIG_PHL_THERMAL_PROTECT
enum rtw_hal_status
rtw_hal_thermal_protect_cfg_tx_ampdu(
void *hal,
struct rtw_phl_stainfo_t *sta,
u8 ratio)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
u8 num_ampdu = 0, tx_time = 0;
if (64 == sta->asoc_cap.num_ampdu)
tx_time = 0xA5;
else if (128 == sta->asoc_cap.num_ampdu)
tx_time = 0xAB;
if(sta->asoc_cap.num_ampdu_bk == 0)
sta->asoc_cap.num_ampdu_bk = sta->asoc_cap.num_ampdu;
sta->asoc_cap.num_ampdu = sta->asoc_cap.num_ampdu_bk * ratio / 100;
num_ampdu = sta->asoc_cap.num_ampdu;
if(num_ampdu == 0)
num_ampdu = 1;
hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, 0, num_ampdu, tx_time);
PHL_INFO("%s: bk_num_ampdu = %d num_ampdu = %d, tx_time = %x\n",
__FUNCTION__, sta->asoc_cap.num_ampdu_bk, num_ampdu, tx_time);
if (RTW_HAL_STATUS_SUCCESS != hsts)
goto out;
out:
return hsts;
}
bool rtw_hal_check_thermal_protect(
struct rtw_phl_com_t *phl_com,
void *hal
)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum halrf_thermal_status status = HALRF_THERMAL_STATUS_BELOW_THRESHOLD;
bool action_changed = false;
status = rtw_hal_rf_get_ther_protected_threshold(hal_info);
PHL_INFO("%s: Cur action = %x\n", __FUNCTION__, phl_com->thermal_protect_action);
PHL_INFO("%s: status = %x\n", __FUNCTION__, status);
switch (phl_com->thermal_protect_action){
case PHL_THERMAL_PROTECT_ACTION_NONE:
if(status == HALRF_THERMAL_STATUS_ABOVE_THRESHOLD){
phl_com->thermal_protect_action =
PHL_THERMAL_PROTECT_ACTION_LEVEL1;
phl_com->drv_mode = RTW_DRV_MODE_HIGH_THERMAL;
action_changed = true;
}
else if(status == HALRF_THERMAL_STATUS_BELOW_THRESHOLD ||
status == HALRF_THERMAL_STATUS_STAY_THRESHOLD){
/* Do nothing */
}
else{
PHL_ERR("Unknown thermal status(%x)!\n", status);
}
break;
case PHL_THERMAL_PROTECT_ACTION_LEVEL1:
if(status == HALRF_THERMAL_STATUS_BELOW_THRESHOLD){
phl_com->thermal_protect_action =
PHL_THERMAL_PROTECT_ACTION_NONE;
phl_com->drv_mode = RTW_DRV_MODE_NORMAL;
action_changed = true;
}
else if(status == HALRF_THERMAL_STATUS_ABOVE_THRESHOLD){
phl_com->thermal_protect_action =
PHL_THERMAL_PROTECT_ACTION_LEVEL2;
action_changed = true;
}
else if(status == HALRF_THERMAL_STATUS_STAY_THRESHOLD){
/* Do nothing */
}
else{
PHL_ERR("Unknown thermal status(%x)!\n", status);
}
break;
case PHL_THERMAL_PROTECT_ACTION_LEVEL2:
if(status == HALRF_THERMAL_STATUS_BELOW_THRESHOLD){
phl_com->thermal_protect_action =
PHL_THERMAL_PROTECT_ACTION_LEVEL1;
action_changed = true;
}
else if(status == HALRF_THERMAL_STATUS_ABOVE_THRESHOLD){
/* No next action */
}
else if(status == HALRF_THERMAL_STATUS_STAY_THRESHOLD){
/* Do nothing */
}
else{
PHL_ERR("Unknown thermal status(%x)!\n", status);
}
break;
default:
PHL_ERR("Unknown thermal protect action(%x)!\n",
phl_com->thermal_protect_action);
break;
}
if(action_changed)
PHL_INFO("%s: Next action = %x\n", __FUNCTION__, phl_com->thermal_protect_action);
return action_changed;
}
#endif /* CONFIG_PHL_THERMAL_PROTECT */
enum rtw_hal_status
rtw_hal_thermal_protect_cfg_tx_duty(
void *hal,
u16 tx_duty_interval,
u8 ratio)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
u16 pause_duration = 0, tx_duration = 0;
tx_duration = tx_duty_interval * ratio / 100;
pause_duration = tx_duty_interval - tx_duration;
PHL_INFO("%s: tx duty interval = %d tx duration = %d, pause duration = %d\n",
__FUNCTION__, tx_duty_interval, tx_duration, pause_duration);
hsts = rtw_hal_mac_set_tx_duty(hal_info, pause_duration, tx_duration);
return hsts;
}
enum rtw_hal_status
rtw_hal_thermal_protect_stop_tx_duty(
void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: Stop tx duty!\n", __FUNCTION__);
hsts = rtw_hal_mac_stop_tx_duty(hal_info);
return hsts;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_thermal.c
|
C
|
agpl-3.0
| 4,795
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TRX_MIT_C_
#include "hal_headers.h"
static void
_hal_trx_mit_timer_convert(u32 timer, u8 *mul_ptr,
enum mac_ax_trx_mitigation_timer_unit *unit_ptr)
{
/* timer = mul * unit */
const enum mac_ax_trx_mitigation_timer_unit UNIT_ARR[] = {
MAC_AX_MIT_64US, MAC_AX_MIT_128US, MAC_AX_MIT_256US,
MAC_AX_MIT_512US};
const u8 UNIT_EXP_ARR[] = {6, 7, 8, 9}; /* 2^exp = unit */
const u8 UNIT_ARR_LEN = 4;
const u8 MUL_MAX = 0xff; /* 8 bits for mul */
u32 timer_ = 0;
u8 idx;
for (idx = 0; idx < UNIT_ARR_LEN; idx++) {
timer_ = timer >> UNIT_EXP_ARR[idx];
if (timer_ <= MUL_MAX)
break;
}
if (timer_ > MUL_MAX)
*mul_ptr = MUL_MAX;
else
*mul_ptr = (u8)timer_;
if (idx < UNIT_ARR_LEN)
*unit_ptr = UNIT_ARR[idx];
else
*unit_ptr = UNIT_ARR[UNIT_ARR_LEN - 1];
}
enum rtw_hal_status rtw_hal_pcie_trx_mit(void *hal, u32 tx_timer, u8 tx_counter,
u32 rx_timer, u8 rx_counter)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_pcie_trx_mitigation mit_info;
struct mac_ax_txdma_ch_map txch_map;
struct mac_ax_rxdma_ch_map rxch_map;
/* tx */
txch_map.ch0 = MAC_AX_PCIE_DISABLE;
txch_map.ch1 = MAC_AX_PCIE_DISABLE;
txch_map.ch2 = MAC_AX_PCIE_DISABLE;
txch_map.ch3 = MAC_AX_PCIE_DISABLE;
txch_map.ch4 = MAC_AX_PCIE_DISABLE;
txch_map.ch5 = MAC_AX_PCIE_DISABLE;
txch_map.ch6 = MAC_AX_PCIE_DISABLE;
txch_map.ch7 = MAC_AX_PCIE_DISABLE;
txch_map.ch8 = MAC_AX_PCIE_DISABLE;
txch_map.ch9 = MAC_AX_PCIE_DISABLE;
txch_map.ch10 = MAC_AX_PCIE_DISABLE;
txch_map.ch11 = MAC_AX_PCIE_DISABLE;
txch_map.ch12 = MAC_AX_PCIE_DISABLE;
mit_info.txch_map = &txch_map;
mit_info.tx_counter = tx_counter;
_hal_trx_mit_timer_convert(tx_timer, &(mit_info.tx_timer),
&(mit_info.tx_timer_unit));
PHL_INFO(
"%s :: mit_info.tx_timer == %d, mit_info.tx_timer_unit == %d\n",
__func__, mit_info.tx_timer, mit_info.tx_timer_unit);
/* tx - END */
/* rx */
rxch_map.rxq = MAC_AX_PCIE_ENABLE;
rxch_map.rpq = MAC_AX_PCIE_ENABLE;
mit_info.rxch_map = &rxch_map;
mit_info.rx_counter = rx_counter;
_hal_trx_mit_timer_convert(rx_timer, &(mit_info.rx_timer),
&(mit_info.rx_timer_unit));
PHL_INFO(
"%s :: mit_info.rx_timer == %d, mit_info.rx_timer_unit == %d\n",
__func__, mit_info.rx_timer, mit_info.rx_timer_unit);
/* rx - END */
if (rtw_hal_mac_pcie_trx_mit(hal_info, &mit_info) !=
RTW_HAL_STATUS_SUCCESS) {
PHL_INFO(
"%s :: failed to config pcie trx interrupt mitigation\n",
__func__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_trx_mit.c
|
C
|
agpl-3.0
| 3,230
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TWT_C_
#include "hal_headers.h"
#ifdef CONFIG_PHL_TWT
enum rtw_hal_status
rtw_hal_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, struct rtw_wifi_role_t *role, u8 action)
{
return rtw_hal_mac_twt_info_update(hal, twt_info, role, action);
}
enum rtw_hal_status
rtw_hal_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action)
{
return rtw_hal_mac_twt_sta_update(hal, macid, twt_id, action);
}
enum rtw_hal_status
rtw_hal_twt_sta_announce(void *hal, u8 macid)
{
return rtw_hal_mac_twt_sta_announce(hal, macid);
}
#endif /* CONFIG_PHL_TWT */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_twt.c
|
C
|
agpl-3.0
| 1,222
|
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TX_C_
#include "hal_headers.h"
/**
* this function will be used in read / write pointer mechanism and
* return the number of available read pointer
* @rptr: input, the read pointer
* @wptr: input, the write pointer
* @bndy: input, the boundary of read / write pointer mechanism
*/
u16 hal_calc_avail_rptr(u16 rptr, u16 wptr, u16 bndy)
{
u16 avail_rptr = 0;
if (wptr >= rptr)
avail_rptr = wptr - rptr;
else if (rptr > wptr)
avail_rptr = wptr + (bndy - rptr);
return avail_rptr;
}
/**
* this function will be used in read / write pointer mechanism and
* return the number of available write pointer
* @rptr: input, the read pointer
* @wptr: input, the write pointer
* @bndy: input, the boundary of read / write pointer mechanism
*/
u16 hal_calc_avail_wptr(u16 rptr, u16 wptr, u16 bndy)
{
u16 avail_wptr = 0;
if (rptr > wptr)
avail_wptr = rptr - wptr - 1;
else if (wptr >= rptr)
avail_wptr = rptr + (bndy - wptr) - 1;
return avail_wptr;
}
/**
* rtw_hal_tx_chnl_mapping - query hw tx dma channel mapping to the sw xmit ring
* identified by macid, tid and band
* @hal: see struct hal_info_t
* @macid: input target macid is 0 ~ 127
* @cat: input target packet category, see enum rtw_phl_ring_cat
* @band: input target band, 0 for band 0 / 1 for band 1
*
* returns the mapping hw tx dma channel
*/
u8 rtw_hal_tx_chnl_mapping(void *hal, u16 macid,
enum rtw_phl_ring_cat cat, u8 band)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u8 tx_chnl = 0;
tx_chnl = trx_ops->map_hw_tx_chnl(macid, cat, band);
return tx_chnl;
}
/**
* rtw_hal_get_fwcmd_queue_idx - get idx of fwcmd queue
* @hal: see struct hal_info_t
*
* returns u8 idx of fwcmd queue
*/
u8 rtw_hal_get_fwcmd_queue_idx(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
return trx_ops->get_fwcmd_queue_idx();
}
void rtw_hal_cfg_txhci(void *hal, u8 en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en);
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_txhci(hal_info, en))
PHL_ERR("%s failure \n", __func__);
}
enum rtw_hal_status rtw_hal_chk_allq_empty(void *hal, u8 *empty)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
FUNCIN();
return rtw_hal_mac_chk_allq_empty(hal_info, empty);
}
enum rtw_hal_status rtw_hal_fill_txdesc(void *hal, struct rtw_xmit_req *treq,
u8 *wd_buf, u32 *wd_len)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_ax_fill_txdesc(hal_info->mac, treq, wd_buf, wd_len);
}
enum rtw_hal_status
rtw_hal_poll_hw_tx_done(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
sts = rtw_hal_mac_poll_hw_tx_done(hal_info);
return sts;
}
enum rtw_hal_status
rtw_hal_hw_tx_resume(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
sts = rtw_hal_mac_hw_tx_resume(hal_info);
return sts;
}
#ifdef CONFIG_PCI_HCI
/**
* rtw_hal_convert_qsel_to_tid - convert qsel to tid value
* @hal: see struct hal_info_t
* @qsel: HW queue selection
*
* returns enum RTW_HAL_STATUS
*/
u8 rtw_hal_convert_qsel_to_tid(void *hal, u8 qsel_id, u8 tid_indic)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->qsel_to_tid(hal_info, qsel_id, tid_indic);
return hstatus;
}
/**
* rtw_hal_tx_res_query - query current HW tx resource with specifc dma channel
* @hal: see struct hal_info_t
* @dma_ch: the target dma channel
* @host_idx: current host index of this channel
* @hw_idx: current hw index of this channel
*
* this function returns the number of available tx resource
* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
*/
u16 rtw_hal_tx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u16 res_num = 0;
res_num = trx_ops->query_tx_res(hal_info->hal_com, dma_ch, host_idx,
hw_idx);
return res_num;
}
/**
* rtw_hal_query_txch_num - query total hw tx dma channels number
*
* returns the number of hw tx dma channel
*/
u8 rtw_hal_query_txch_num(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u8 ch_num = 0;
ch_num = trx_ops->query_txch_num();
return ch_num;
}
enum rtw_hal_status rtw_hal_trx_init(void *hal, u8 *txbd_buf, u8 *rxbd_buf)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->init(hal_info, txbd_buf, rxbd_buf);
return hstatus;
}
void rtw_hal_trx_deinit(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
trx_ops->deinit(hal_info);
}
/**
* rtw_hal_update_wd_page - update wd page for xmit packet
* @hal: see struct hal_info_t
* @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req
*
* returns enum RTW_HAL_STATUS
*/
enum rtw_hal_status rtw_hal_update_wd_page(void *hal, void *phl_pkt_req)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->update_wd(hal_info, phl_pkt_req);
return hstatus;
}
/**
* rtw_hal_update_txbd - update tx bd for xmit packet
* @hal: see struct hal_info_t
* @wd: buffer pointer of wd page to fill in txbd
*
* returns enum RTW_HAL_STATUS
* NOTE, this function is PCIe specific function
*/
enum rtw_hal_status rtw_hal_update_txbd(void *hal, void *txbd, void *wd, u8 dma_ch, u16 wd_num)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->update_txbd(hal, txbd, wd, dma_ch, wd_num);
return hstatus;
}
/**
* rtw_hal_update_trigger_txstart - trigger hw to start tx
* @hal: see struct hal_info_t
* @txbd: the target txbd to update
* @dma_ch: the dma channel index of this txbd_ring
*
* returns enum RTW_HAL_STATUS
*/
enum rtw_hal_status rtw_hal_trigger_txstart(void *hal, void *txbd, u8 dma_ch)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->tx_start(hal, txbd, dma_ch);
return hstatus;
}
u8 rtw_hal_poll_txdma_idle(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
FUNCIN();
return trx_ops->poll_txdma_idle(hal_info);
}
#endif /*CONFIG_PCI_HCI*/
#ifdef CONFIG_USB_HCI
enum rtw_hal_status rtw_hal_trx_init(void *hal)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->init(hal_info);
return hstatus;
}
void rtw_hal_trx_deinit(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
trx_ops->deinit(hal_info);
}
u8 rtw_hal_get_bulkout_id(void *hal, u8 dma_ch, u8 mode)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->get_bulkout_id(hal, dma_ch, mode);
return hstatus;
}
enum rtw_hal_status
rtw_hal_usb_tx_agg_cfg(void *hal, u8* wd_buf, u8 agg_num)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->usb_tx_agg_cfg(hal, wd_buf, agg_num);
return hstatus;
}
u8 rtw_hal_get_max_bulkout_wd_num(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
return trx_ops->get_max_bulkout_wd_num(hal);
}
/**
* rtw_hal_fill_wd - fill wd-info and wd-boddy for xmit packet
* @hal: see struct hal_info_t
* @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req
*
* returns enum RTW_HAL_STATUS
*/
enum rtw_hal_status rtw_hal_fill_wd(void *hal,
struct rtw_xmit_req *tx_req,
u8 *wd_buf, u32 *wd_len)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL
if (tx_req->mdata.spe_rpt) {
if (tx_req->mdata.data_tx_cnt_lmt_en)
hal_info->hal_com->spe_pkt_cnt_lmt = tx_req->mdata.data_tx_cnt_lmt;
}
#endif
hstatus = trx_ops->hal_fill_wd(hal_info, tx_req, wd_buf, wd_len);
return hstatus;
}
#endif
#ifdef CONFIG_SDIO_HCI
void rtw_hal_sdio_tx_cfg(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
rtw_hal_mac_sdio_tx_cfg(hal_info->hal_com);
}
enum rtw_hal_status rtw_hal_sdio_tx(void *hal, u8 dma_ch, u8 *buf, u32 buf_len,
u8 agg_count, u16 *pkt_len, u8 *wp_offset)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u32 txaddr;
u32 txlen;
bool ready;
ready = rtw_hal_mac_sdio_check_tx_allow(hal_info->hal_com, dma_ch,
buf, buf_len, agg_count,
pkt_len, wp_offset, &txaddr,
&txlen);
if (!ready)
return RTW_HAL_STATUS_RESOURCE;
hal_sdio_cmd53_w(hal_info->hal_com, txaddr, txlen, buf);
return RTW_HAL_STATUS_SUCCESS;
}
#endif /* CONFIG_SDIO_HCI */
#define TX_DBG_STATUS_DUMP_INTERVAL 30000 /* ms */
void rtw_hal_tx_dbg_status_dump(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_mac_dbg_dump_cfg cfg = {0};
static u32 last_dump_t = 0;
cfg.tx_flow_dbg = 1;
if (phl_get_passing_time_ms(last_dump_t) >= TX_DBG_STATUS_DUMP_INTERVAL) {
rtw_hal_mac_dbg_status_dump(hal_info, &cfg);
last_dump_t = _os_get_cur_time_ms();
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_tx.c
|
C
|
agpl-3.0
| 10,864
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_TX_H_
#define _HAL_TX_H_
/**
* this function will be used in read / write pointer mechanism and
* return the number of available read pointer
* @rptr: input, the read pointer
* @wptr: input, the write pointer
* @bndy: input, the boundary of read / write pointer mechanism
*/
u16 hal_calc_avail_rptr(u16 rptr, u16 wptr, u16 bndy);
/**
* this function will be used in read / write pointer mechanism and
* return the number of available write pointer
* @rptr: input, the read pointer
* @wptr: input, the write pointer
* @bndy: input, the boundary of read / write pointer mechanism
*/
u16 hal_calc_avail_wptr(u16 rptr, u16 wptr, u16 bndy);
#ifdef CONFIG_PCI_HCI
/**
* rtw_hal_query_txch_num - query total hw tx dma channels number
*
* returns the number of hw tx dma channel
*/
u8 rtw_hal_query_txch_num(void *hal);
#endif
#endif /*_HAL_TX_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_tx.h
|
C
|
agpl-3.0
| 1,524
|
/******************************************************************************
*
* Copyright(c) 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TXPWR_C_
#include "hal_headers.h"
const char *rtw_hal_get_pw_lmt_regu_type_str(void *hal, enum band_type band)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_rf_get_pw_lmt_regu_type_str(hal_info, band);
}
bool rtw_hal_get_pwr_lmt_en(void *hal, u8 band_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_get_pwr_lmt_en_val(hal_info->hal_com, band_idx);
}
enum rtw_hal_status rtw_hal_set_tx_power(void *hal, u8 band_idx,
enum phl_pwr_table pwr_table)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum phl_phy_idx phy_idx = HW_PHY_0;
if (band_idx == 1)
phy_idx = HW_PHY_1;
return rtw_hal_rf_set_power(hal_info, phy_idx, pwr_table);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_txpwr.c
|
C
|
agpl-3.0
| 1,386
|
/******************************************************************************
*
* Copyright(c)2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_TXPWR_H_
#define _HAL_TXPWR_H_
const char *rtw_hal_get_pw_lmt_regu_type_str(void *hal, enum band_type band);
bool rtw_hal_get_pwr_lmt_en(void *hal, u8 band_idx);
enum rtw_hal_status rtw_hal_set_tx_power(void *hal, u8 band_idx,
enum phl_pwr_table pwr_table);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_txpwr.h
|
C
|
agpl-3.0
| 934
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_WOW_C_
#include "hal_headers.h"
#ifdef CONFIG_WOWLAN
#define case_rsn(rsn) \
case MAC_AX_WOW_##rsn: return RTW_WOW_RSN_##rsn
u8 _trans_wake_rsn(u8 mac_rsn)
{
switch (mac_rsn) {
case_rsn(RX_PAIRWISEKEY);
case_rsn(RX_GTK);
case_rsn(RX_FOURWAY_HANDSHAKE);
case_rsn(RX_DISASSOC);
case_rsn(RX_DEAUTH);
case_rsn(RX_ARP_REQUEST);
case_rsn(RX_NS);
case_rsn(RX_EAPREQ_IDENTIFY);
case_rsn(FW_DECISION_DISCONNECT);
case_rsn(RX_MAGIC_PKT);
case_rsn(RX_UNICAST_PKT);
case_rsn(RX_PATTERN_PKT);
case_rsn(RTD3_SSID_MATCH);
case_rsn(RX_DATA_PKT);
case_rsn(RX_SSDP_MATCH);
case_rsn(RX_WSD_MATCH);
case_rsn(RX_SLP_MATCH);
case_rsn(RX_LLTD_MATCH);
case_rsn(RX_MDNS_MATCH);
case_rsn(RX_REALWOW_V2_WAKEUP_PKT);
case_rsn(RX_REALWOW_V2_ACK_LOST);
case_rsn(RX_REALWOW_V2_TX_KAPKT);
case_rsn(ENABLE_FAIL_DMA_IDLE);
case_rsn(ENABLE_FAIL_DMA_PAUSE);
case_rsn(RTIME_FAIL_DMA_IDLE);
case_rsn(RTIME_FAIL_DMA_PAUSE);
case_rsn(RX_SNMP_MISMATCHED_PKT);
case_rsn(RX_DESIGNATED_MAC_PKT);
case_rsn(NLO_SSID_MACH);
case_rsn(AP_OFFLOAD_WAKEUP);
case_rsn(DMAC_ERROR_OCCURRED);
case_rsn(EXCEPTION_OCCURRED);
case_rsn(L0_TO_L1_ERROR_OCCURRED);
case_rsn(ASSERT_OCCURRED);
case_rsn(L2_ERROR_OCCURRED);
case_rsn(WDT_TIMEOUT_WAKE);
case_rsn(RX_ACTION);
case_rsn(CLK_32K_UNLOCK);
case_rsn(CLK_32K_LOCK);
default:
return RTW_WOW_RSN_MAX;
}
}
#define MAX_POLLING_WOW_FW_STS_CNT 1000 /* 50ms */
static enum rtw_hal_status _hal_check_wow_fw_ready(void *hal, u8 func_en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE;
void* drv_priv = hal_to_drvpriv(hal_info);
u8 fw_status = 0;
u32 poll_cnt = 0;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : start polling... (func_en %d)\n", __func__, func_en);
/* polling fw status */
while (1) {
if (poll_cnt >= MAX_POLLING_WOW_FW_STS_CNT) {
PHL_ERR("%s polling fw status timeout !!!\n", __func__);
hstats = RTW_HAL_STATUS_FAILURE;
break;
}
hstats = rtw_hal_mac_get_wow_fw_status(hal_info, &fw_status,
func_en);
if (RTW_HAL_STATUS_SUCCESS != hstats) {
PHL_ERR("%s : status %u\n", __func__, fw_status);
break;
}
if (fw_status) {
hstats = RTW_HAL_STATUS_SUCCESS;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_,
"%s : polling count %u\n", __func__, poll_cnt);
break;
} else {
_os_delay_us(drv_priv, 50);
}
poll_cnt++;
}
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : finish polling... (func_en %d)\n", __func__, func_en);
return hstats;
}
enum rtw_hal_status rtw_hal_get_wake_rsn(void *hal, enum rtw_wow_wake_reason *wake_rsn, u8 *reset)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE;
u8 mac_rsn = 0;
hstats = rtw_hal_mac_get_wake_rsn(hal_info, &mac_rsn, reset);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : wake rsn from mac in hex 0x%x (reset %d).\n",
__func__, mac_rsn, *reset);
if (RTW_HAL_STATUS_SUCCESS != hstats) {
PHL_ERR("%s : rtw_hal_mac_get_wake_rsn failed.\n", __func__);
} else {
*wake_rsn = (mac_rsn == 0) ? RTW_WOW_RSN_UNKNOWN : _trans_wake_rsn(mac_rsn) ;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : wake reason %u.\n", __func__, *wake_rsn);
}
return hstats;
}
enum rtw_hal_status rtw_hal_cfg_wow_sleep(void *hal, u8 sleep)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE;
hstats = rtw_hal_mac_cfg_wow_sleep(hal_info, sleep);
if (RTW_HAL_STATUS_SUCCESS != hstats)
PHL_ERR("%s : sleep %u\n", __func__, sleep);
return hstats;
}
enum rtw_hal_status rtw_hal_get_wow_aoac_rpt(void *hal, struct rtw_aoac_report *aoac_info, u8 rx_ready)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
FUNCIN();
/* get aoac report */
hstatus = rtw_hal_mac_get_aoac_rpt(hal_info, aoac_info, rx_ready);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s(): failed with status(%u)\n", __func__, hstatus);
FUNCOUT();
return hstatus;
}
enum rtw_hal_status rtw_hal_reset_pkt_ofld_state(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE;
hstats = rtw_hal_mac_reset_pkt_ofld_state(hal_info);
if (RTW_HAL_STATUS_SUCCESS != hstats)
PHL_ERR("%s : failed \n", __func__);
return hstats;
}
#ifdef CONFIG_PCI_HCI
enum rtw_hal_status rtw_hal_wow_cfg_txdma(void *hal, u8 en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en);
trx_ops->cfg_wow_txdma(hal_info, en);
return RTW_HAL_STATUS_SUCCESS;
}
#endif
enum rtw_hal_status rtw_hal_wow_init(struct rtw_phl_com_t *phl_com, void *hal,
struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
FUNCIN_WSTS(hal_status);
/* download wowlan fw and do related tasks needed after redownload fw */
hal_status = hal_ops->hal_wow_init(phl_com, hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s successfully done.\n", __func__);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_wow_deinit(struct rtw_phl_com_t *phl_com, void *hal,
struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
FUNCIN_WSTS(hal_status);
/* download wowlan fw and do related tasks needed after redownload fw */
hal_status = hal_ops->hal_wow_deinit(phl_com, hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s successfully done.\n", __func__);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_wow_func_en(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
FUNCIN();
do {
/* config wow cam : pattern match */
#ifndef RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG
hstatus = rtw_hal_mac_cfg_wow_cam(hal_info, macid, true, cfg->pattern_match_info);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
#endif
/* gtk offload */
hstatus = rtw_hal_mac_cfg_gtk_ofld(hal_info, macid, true, cfg->gtk_ofld_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* arp offload */
hstatus = rtw_hal_mac_cfg_arp_ofld(hal_info, macid, true, cfg->arp_ofld_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* ndp offload */
hstatus = rtw_hal_mac_cfg_ndp_ofld(hal_info, macid, true, cfg->ndp_ofld_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* config keep alive */
hstatus = rtw_hal_mac_cfg_keep_alive(hal_info, macid, true, cfg->keep_alive_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* config disconnect detection */
hstatus = rtw_hal_mac_cfg_disc_dec(hal_info, macid, true, cfg->disc_det_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* realwow offload */
hstatus = rtw_hal_mac_cfg_realwow(hal_info, macid, true, cfg->realwow_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* config gpio */
hstatus = rtw_hal_mac_cfg_dev2hst_gpio(hal_info, true, cfg->wow_gpio);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
} while(0);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus);
FUNCOUT();
return hstatus;
}
enum rtw_hal_status rtw_hal_wow_func_dis(struct rtw_phl_com_t *phl_com, void *hal, u16 macid)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
FUNCIN();
/* cancel pattern match */
#ifndef RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG
hstatus = rtw_hal_mac_cfg_wow_cam(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_wow_cam failed \n");
#endif
/* cancel gtk offload */
hstatus = rtw_hal_mac_cfg_gtk_ofld(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_gtk_ofld failed \n");
/* cancel arp offload */
hstatus = rtw_hal_mac_cfg_arp_ofld(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_arp_ofld failed \n");
/* cancel ndp offload */
hstatus = rtw_hal_mac_cfg_ndp_ofld(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_ndp_ofld failed \n");
/* disable keep alive */
hstatus = rtw_hal_mac_cfg_keep_alive(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_keep_alive failed \n");
/* disable disconect detection */
hstatus = rtw_hal_mac_cfg_disc_dec(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_disc_dec failed \n");
/* realwow offload */
hstatus = rtw_hal_mac_cfg_realwow(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_realwow_ofld failed \n");
/* config gpio */
hstatus = rtw_hal_mac_cfg_dev2hst_gpio(hal_info, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_dev2hst_gpio failed \n");
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus);
FUNCOUT();
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_wow_func_start(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
do {
hstatus = rtw_hal_mac_cfg_wow_wake(hal_info, macid, true, cfg->wow_wake_cfg);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* poll fw status */
hstatus = _hal_check_wow_fw_ready(hal_info, 1);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
} while(0);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus);
return hstatus;
}
enum rtw_hal_status rtw_hal_wow_func_stop(struct rtw_phl_com_t *phl_com, void *hal, u16 macid)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
/* config wow ctrl */
hstatus = rtw_hal_mac_cfg_wow_wake(hal_info, macid, false, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] rtw_hal_mac_cfg_wow_wake failed \n");
hstatus = _hal_check_wow_fw_ready(hal_info, 0);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] _hal_poll_wow_fw_status failed \n");
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s status(%u).\n", __func__, hstatus);
return hstatus;
}
enum rtw_hal_status rtw_hal_set_wowlan(struct rtw_phl_com_t *phl_com, void *hal, u8 enter)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_set_wowlan(hal_info, enter);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
return hal_status;
}
static enum rtw_hal_status _wow_chk_txq_empty(struct hal_info_t *hal_info, u8 *empty)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_wow_chk_txq_empty(hal_info, empty);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
return hal_status;
}
static enum rtw_hal_status _wow_wde_drop(struct hal_info_t *hal_info, u8 band)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_wow_wde_drop(hal_info, band);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
return hal_status;
}
#define MAX_WOW_DROP_HWTX_TRYCNT 3
enum rtw_hal_status rtw_hal_wow_drop_tx(void *hal, u8 band)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 empty = 0;
u8 i = 0;
for (i = 0; i < MAX_WOW_DROP_HWTX_TRYCNT; i++) {
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : chk/drop for the %d time\n", __func__, i + 1);
if (RTW_HAL_STATUS_SUCCESS != _wow_chk_txq_empty(hal_info, &empty))
PHL_WARN("[wow] _wow_chk_txq_empty failed.\n");
/* force drop wde if txq is not empty */
if (!empty)
_wow_wde_drop(hal_info, band);
else
break;
}
if (!empty) {
PHL_WARN("[wow] %s : chk/drop fail!\n", __func__);
} else {
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "[wow] %s : chk/drop ok.\n", __func__);
hal_status = RTW_HAL_STATUS_SUCCESS;
}
return hal_status;
}
#endif /* CONFIG_WOWLAN */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_wow.c
|
C
|
agpl-3.0
| 13,699
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_WOW_H_
#define _HAL_WOW_H_
#ifdef CONFIG_WOWLAN
/* ... */
#endif /* CONFIG_WOWLAN */
#endif /* _HAL_WOW_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_wow.h
|
C
|
agpl-3.0
| 774
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_CHIP_CFG_H_
#define _MAC_AX_CHIP_CFG_H_
#ifndef __cplusplus /* for win/linux driver */
/* Modify MakeFile to reduce code size (chip & interface) */
#ifdef CONFIG_RTL8852A
#define MAC_AX_8852A_SUPPORT 1
#else
#define MAC_AX_8852A_SUPPORT 0
#endif
#ifdef CONFIG_RTL8852B
#define MAC_AX_8852B_SUPPORT 1
#else
#define MAC_AX_8852B_SUPPORT 0
#endif
#ifdef CONFIG_RTL8852C
#define MAC_AX_8852C_SUPPORT 1
#else
#define MAC_AX_8852C_SUPPORT 0
#endif
#ifdef CONFIG_RTL8192XB
#define MAC_AX_8192XB_SUPPORT 1
#else
#define MAC_AX_8192XB_SUPPORT 0
#endif
/* Interface support */
#ifdef CONFIG_SDIO_HCI
#define MAC_AX_SDIO_SUPPORT 1
#else
#define MAC_AX_SDIO_SUPPORT 0
#endif
#ifdef CONFIG_USB_HCI
#define MAC_AX_USB_SUPPORT 1
#else
#define MAC_AX_USB_SUPPORT 0
#endif
#ifdef CONFIG_PCI_HCI
#define MAC_AX_PCIE_SUPPORT 1
#else
#define MAC_AX_PCIE_SUPPORT 0
#endif
#else /* for WD1 test program */
/* Modify MakeFile to reduce code size (chip & interface) */
#define MAC_AX_8852A_SUPPORT 1
#define MAC_AX_8852B_SUPPORT 1
#define MAC_AX_8852C_SUPPORT 1
#define MAC_AX_8192XB_SUPPORT 1
/* Interface support */
#define MAC_AX_SDIO_SUPPORT 1
#define MAC_AX_USB_SUPPORT 1
#define MAC_AX_PCIE_SUPPORT 1
#endif // #else /* for WD1 test program */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/chip_cfg.h
|
C
|
agpl-3.0
| 1,947
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_CHIP_CFG_H_
#define _MAC_AX_CHIP_CFG_H_
/* Modify MakeFile to reduce code size (chip & interface) */
#ifdef CONFIG_RTL8852A
#define MAC_AX_8852A_SUPPORT 1
#else
#define MAC_AX_8852A_SUPPORT 0
#endif
#ifdef CONFIG_RTL8852B
#define MAC_AX_8852B_SUPPORT 1
#else
#define MAC_AX_8852B_SUPPORT 0
#endif
#ifdef CONFIG_RTL8852C
#define MAC_AX_8852C_SUPPORT 1
#else
#define MAC_AX_8852C_SUPPORT 0
#endif
#ifdef CONFIG_RTL8192XB
#define MAC_AX_8192XB_SUPPORT 1
#else
#define MAC_AX_8192XB_SUPPORT 0
#endif
/* Interface support */
#ifdef CONFIG_SDIO_HCI
#define MAC_AX_SDIO_SUPPORT 1
#else
#define MAC_AX_SDIO_SUPPORT 0
#endif
#ifdef CONFIG_USB_HCI
#define MAC_AX_USB_SUPPORT 1
#else
#define MAC_AX_USB_SUPPORT 0
#endif
#ifdef CONFIG_PCI_HCI
#define MAC_AX_PCIE_SUPPORT 1
#else
#define MAC_AX_PCIE_SUPPORT 0
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/chip_cfg_drv.h
|
C
|
agpl-3.0
| 1,518
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_ERR_H_
#define _MAC_AX_ERR_H_
#define MACSUCCESS 0 /* Success return value */
#define MACPFCB 1 /* Callback of platform is null */
#define MACPFED 2 /* Endian of platform error */
#define MACBADDR 3 /* Invalid base address */
#define MACLSUS 4 /* Leave suspend error */
#define MACNPTR 5 /* Pointer is null */
#define MACCHIPID 6 /* Chip ID is undefined */
#define MACADAPTER 7 /* Can not get MAC adapter */
#define MACSTCAL 8 /* Unexpected structure alignment */
#define MACNOBUF 9 /* Buffer space is not enough */
#define MACBUFSZ 10 /* Buffer size error */
#define MACNOITEM 11 /* Invalid item */
#define MACPOLLTO 12 /* Polling timeout */
#define MACPWRSW 13 /* Power switch fail */
#define MACBUFALLOC 14 /* Buffer allocation fail */
#define MACWQBUSY 15 /* Work queue is busy */
#define MACCMP 16 /* Failed compare result */
#define MACINTF 17 /* Wrong interface */
#define MACFWBIN 18 /* Incorrect FW bin file */
#define MACFFCFG 19 /* Wrong FIFO configuration */
#define MACSAMACID 20 /* Same MACID */
#define MACMACIDFL 21 /* MACID full */
#define MACNOFW 22 /* There is no FW */
#define MACPROCBUSY 23 /* Process is busy */
#define MACPROCERR 24 /* state machine error */
#define MACEFUSEBANK 25 /* switch efuse bank fail */
#define MACEFUSEREAD 26 /* read efuse fail */
#define MACEFUSEWRITE 27 /* write efuse fail */
#define MACEFUSESIZE 28 /* efuse size error */
#define MACEFUSEPARSE 29 /* eeprom parsing fail */
#define MACEFUSECMP 30 /* compare efuse fail */
#define MACSECUREON 31 /* secure on, no host indirect access */
#define MACTXCHDMA 32 /* invalid tx dma channel */
#define MACADDRCAMUPDERR 33 /* address cam update error */
#define MACPWRSTAT 34 /* Power state error */
#define MACSDIOMIXMODE 35 /* SDIO Tx mix mode */
#define MACSDIOSEQERR 36 /* SDIO Tx sequence error */
#define MACHFCH2CQTA 37 /* HCI FC invalid H2C quota */
#define MACHFCCH011QTA 38 /* HCI FC invalid CH0-11 quota */
#define MACHFCCH011GRP 39 /* HCI FC invalid CH0-11 group */
#define MACHFCPUBQTA 40 /* HCI FC invalid public quota */
#define MACHFCPUBINFO 41 /* HCI FC public info error */
#define MACRFPMCAM 42 /* RX forwarding PM CAM access fail */
#define MACHFSWDENOTNUF 43 /* HCI FC WDE page not enough */
#define MACHFSPLENOTNUF 44 /* HCI FC PLE page not enough */
#define MACMEMRO 45 /* Address is not writable */
#define MACFUNCINPUT 46 /* invalid function input */
#define MACALRDYON 47 /* MAC has already powered on */
#define MACADDRCAMFL 48 /* ADDRESS CAM full */
#define MACBSSIDCAMFL 49 /* BSSID CAM full */
#define MACGPIOUSED 50 /* GPIO is used */
#define MACDLELINK 51 /* DLE link error */
#define MACPOLLTXIDLE 52 /* polling Tx idle fail */
#define MACPARSEERR 53 /* parse report err */
#define MACROLEINITFL 54 /* Role API init fail or C2H notify role init fail */
#define MACPORTCFGTYPE 55 /* Port cfg type error */
#define MACPORTCFGPORT 56 /* Port cfg port error */
#define MACWNGKEYTYPE 57 /* Sec cam wrong key type*/
#define MACKEYNOTEXT 58 /* Delete key , key not exist*/
#define MACSECCAMFL 59 /* SEC CAM full*/
#define MACADDRCAMKEYFL 60 /* Addr CAM key full*/
#define MACNOROLE 61 /* SEC no this role*/
#define MACHWNOTEN 62 /* hw module not enable*/
#define MACPTMTXFAIL 63 /* platform TX fail*/
#define MACSSLINK 64 /* STA scheduler link error */
#define MACDBGPORTSEL 65 /* Debug port sel error */
#define MACDBGPORTDMP 66 /* Debug port dump error */
#define MACCPWMSEQERR 67 /* CPWM sequence mismatch */
#define MACCPWMSTATERR 68 /* CPWM state mismatch */
#define MACCPUSTATE 69 /* Incorrect CPU state */
#define MACPSSTATFAIL 70 /* protocol power state check fail */
#define MACLV1STEPERR 71 /* lv1 rcvy step sel error */
#define MACFWCHKSUM 72 /* FW checksum is incorrect */
#define MACFWSECBOOT 73 /* FW security boot is failed */
#define MACFWCUT 74 /* Mismatch chip and FW cut */
#define MACSUBSPCERR 75 /* Beacon sub-space setting fail */
#define MACLENCMP 76 /* Length is not match */
#define MACCHKSUMEMPTY 77 /* Checksum report empty */
#define MACCHKSUMFAIL 78 /* Checksum report fail */
#define MACVERERR 79 /* Map and mask version mismatch */
#define MACFWNONRDY 80 /* FW not ready h2c error*/
#define MACGPIONUM 81 /* The gpio number is wrong */
#define MACNOTSUP 82 /* The function is NOT supported */
#define MACCSIBUFIDERR 83 /* CSI buffer index is NOT supported */
#define MACSNDSTSIDERR 84 /* Sounding status ID is NOT supported */
#define MACCCTLWRFAIL 85 /* control info wrrite fail */
#define MACHWNOSUP 86 /* HW not support */
#define MACUNDEFCH 87 /* Channel is undefined */
#define MACHWERR 88 /* HW error */
#define MACFWTESTFAIL 89 /* FW auto test fail */
#define MACP2PSTFAIL 90 /* P2P state fail */
#define MACFLASHFAIL 91 /* FW auto test fail */
#define MACSETVALERR 92 /* Setting value error */
#define MACIOERRPWR 93 /* IO not allow when power not on */
#define MACIOERRSERL1 94 /* IO not allow when SER Lv1 */
#define MACIOERRLPS 95 /* IO not allow when LPS */
#define MACIOERRDMAC 96 /* IO not allow when dmac not en */
#define MACIOERRCMAC0 97 /* IO not allow when cmac0 not en */
#define MACIOERRCMAC1 98 /* IO not allow when cmac1 not en */
#define MACIOERRBB0 99 /* IO not allow when bb0 not en */
#define MACIOERRBB1 100 /* IO not allow when bb1 not en */
#define MACIOERRRF 101 /* IO not allow when rf not en */
#define MACIOERRIND 102 /* IO not allow when indirect access */
#define MACIOERRRSVD 103 /* IO not allow if address is rsvd */
#define MACC2HREGEMP 104 /* C2H reg empty */
#define MACBADC2HREG 105 /* received unexpected c2hreg */
#define MACFIOOFLD 106 /* IO offload fail */
#define MACROLEALOCFL 107 /* C2H notify alloc role failed */
#define MACROLEHWUPDFL 108 /* C2H notify addrcam upd failed*/
#define MACSDIOTXMODE 109 /* SDIO Tx mode undefined*/
#define MACSDIOOPNMODE 110 /* SDIO opn mode unknown*/
#define MACFWSTATUSFAIL 111 /* fw status command fail */
#define MACIOERRPLAT 112 /* IO not allow when platform not on */
#define MACCPWMPWRSTATERR 113 /* CPWM power state mismatch */
#define MACIOERRISH 114 /* IO not allow when io state hang */
#define MACHWDMACERR 115 /* DMAC_ERR_ISR */
#define MACHWCMAC0ERR 116 /* CMAC0_ERR_ISR */
#define MACHWCMAC1ERR 116 /* CMAC1_ERR_ISR */
#define MACDRVRM 117 /* driver is removed unexpectedly */
#define MACMCCGPFL 118 /* Get MCC Group index fail*/
#define MACFWSTATEERR 119 /* fw state error */
#define MACFWLOGINTERR 120 /*fw log parsing error*/
#define MACFWASSERT 123 /* FW Assertion error */
#define MACFWEXCEP 124 /* FW Exception error */
#define MACFWRXI300 125 /* FW RXI300 error */
#define MACFWPCHANG 126 /* FW PC hang error */
#define MACRXDMAHANG 127 /*USB RXDMA HANG */
#define MACUSBRXHANG 128 /*USB RX HANG */
/*MAC DBG Status Indication*/
#define MACSCH_NONEMPTY 1 /* MAC Scheduler non empty */
/* Debug Package Indication */
/* STA Scheduler 0, indirect */
#define SS_TX_LEN_BE BIT(0)
#define SS_TX_LEN_BK BIT(1)
#define SS_TX_LEN_VI BIT(2)
#define SS_TX_LEN_VO BIT(3)
#define SS_LINK_WMM0_BE BIT(4)
#define SS_LINK_WMM0_BK (SS_LINK_WMM0_BE << 1)
#define SS_LINK_WMM0_VI (SS_LINK_WMM0_BE << 2)
#define SS_LINK_WMM0_VO (SS_LINK_WMM0_BE << 3)
#define SS_LINK_WMM1_BE (SS_LINK_WMM0_BE << 4)
#define SS_LINK_WMM1_BK (SS_LINK_WMM0_BE << 5)
#define SS_LINK_WMM1_VI (SS_LINK_WMM0_BE << 6)
#define SS_LINK_WMM1_VO (SS_LINK_WMM0_BE << 7)
#define SS_LINK_WMM2_BE (SS_LINK_WMM0_BE << 8)
#define SS_LINK_WMM2_BK (SS_LINK_WMM0_BE << 9)
#define SS_LINK_WMM2_VI (SS_LINK_WMM0_BE << 10)
#define SS_LINK_WMM2_VO (SS_LINK_WMM0_BE << 11)
#define SS_LINK_WMM3_BE (SS_LINK_WMM0_BE << 12)
#define SS_LINK_WMM3_BK (SS_LINK_WMM0_BE << 13)
#define SS_LINK_WMM3_VI (SS_LINK_WMM0_BE << 14)
#define SS_LINK_WMM3_VO (SS_LINK_WMM0_BE << 15)
#define SS_LINK_UL (SS_LINK_WMM0_BE << 16)
#define SS_POLL_OWN_TX_LEN BIT(24)
#define SS_POLL_OWN_LINK BIT(25)
#define SS_POLL_STAT_TX_LEN BIT(26)
#define SS_POLL_STAT_LINK BIT(27)
/* STA Scheduler 1, direct */
#define SS_TX_HW_LEN_UDN BIT(0)
#define SS_TX_SW_LEN_UDN BIT(1)
#define SS_TX_HW_LEN_OVF BIT(2)
#define SS_STAT_FWTX BIT(8)
#define SS_STAT_RPTA BIT(9)
#define SS_STAT_WDEA BIT(10)
#define SS_STAT_PLEA BIT(11)
#define SS_STAT_ULRU BIT(12)
#define SS_STAT_DLTX BIT(13)
#ifdef CONFIG_NEW_HALMAC_INTERFACE
#define PLTFM_MSG_ALWAYS(...) \
_os_dbgdump("[MAC][ERR] " fmt, ##__VA_ARGS__)
#else
#define PLTFM_MSG_ALWAYS(...) \
adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_ALWAYS_, __VA_ARGS__)
#endif
#if MAC_AX_DBG_MSG_EN
#ifdef CONFIG_NEW_HALMAC_INTERFACE
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ALWAYS)
#define PLTFM_MSG_ALWAYS(...) \
_os_dbgdump("[MAC][LOG] " fmt, ##__VA_ARGS__)
#else
#define PLTFM_MSG_ALWAYS(...) do {} while (0)
#endif
/* Enable debug msg depends on HALMAC_MSG_LEVEL */
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ERR)
#define PLTFM_MSG_ERR(...) \
_os_dbgdump("[MAC][ERR] " fmt, ##__VA_ARGS__)
#else
#define PLTFM_MSG_ERR(...) do {} while (0)
#endif
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_WARNING)
#define PLTFM_MSG_WARN(...) \
_os_dbgdump("[MAC][WARN] " fmt, ##__VA_ARGS__)
#else
#define PLTFM_MSG_WARN(...) do {} while (0)
#endif
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_TRACE)
#define PLTFM_MSG_TRACE(...) \
_os_dbgdump("[MAC][TRACE] " fmt, ##__VA_ARGS__)
#else
#define PLTFM_MSG_TRACE(...) do {} while (0)
#endif
#else
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ALWAYS)
#define PLTFM_MSG_ALWAYS(...) \
adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_ALWAYS_, __VA_ARGS__)
#else
#define PLTFM_MSG_ALWAYS(...) do {} while (0)
#endif
/* Enable debug msg depends on HALMAC_MSG_LEVEL */
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_ERR)
#define PLTFM_MSG_ERR(...) \
adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_ERR_, __VA_ARGS__)
#else
#define PLTFM_MSG_ERR(...) do {} while (0)
#endif
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_WARNING)
#define PLTFM_MSG_WARN(...) \
adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_WARNING_, __VA_ARGS__)
#else
#define PLTFM_MSG_WARN(...) do {} while (0)
#endif
#if (MAC_AX_MSG_LEVEL >= MAC_AX_MSG_LEVEL_TRACE)
#define PLTFM_MSG_TRACE(...) \
adapter->pltfm_cb->msg_print(adapter->drv_adapter, _PHL_DEBUG_, __VA_ARGS__)
#else
#define PLTFM_MSG_TRACE(...) do {} while (0)
#endif
#endif /*CONFIG_NEW_HALMAC_INTERFACE*/
#else
/* Disable debug msg */
#define PLTFM_MSG_ALWAYS(...) do {} while (0)
#define PLTFM_MSG_ERR(...) do {} while (0)
#define PLTFM_MSG_WARN(...) do {} while (0)
#define PLTFM_MSG_TRACE(...) do {} while (0)
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/errors.h
|
C
|
agpl-3.0
| 11,648
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FEATURE_CFG_H_
#define _MAC_AX_FEATURE_CFG_H_
#ifndef __cplusplus /* for win/linux driver */
/* [Note] Modify MakeFile to reduce code size */
/* Debug package for debugging */
#define MAC_AX_FEATURE_DBGPKG 1
/* Hadrware verification module */
#define MAC_AX_FEATURE_HV 0
/* FW offload reg read/write */
#define MAC_AX_FW_REG_OFLD 0
/* Temp code for FPGA verification*/
#define MAC_AX_FPGA_TEST 0
/* Temp code for lack of BTC driver*/
#define MAC_AX_ASIC_TEMP 1
/* temp for h2c alloc move to phl layer*/
#define MAC_AX_PHL_H2C 1
/* Debug command */
#define MAC_AX_FEATURE_DBGCMD 1
/* Debug Log Decode */
#define MAC_AX_FEATURE_DBGDEC 1
#ifdef CONFIG_BTCOEX
#define MAC_AX_COEX_INIT_EN 0
#else
#define MAC_AX_COEX_INIT_EN 1
#endif
#else /* for WD1 test program */
/* [Note] Modify MakeFile to reduce code size */
/* Debug package for debugging */
#define MAC_AX_FEATURE_DBGPKG 1
/* Debug package for debugging */
#define MAC_AX_FW_REG_OFLD 0
/* Hadrware verification module */
#define MAC_AX_FEATURE_HV 1
#define MAC_AX_FPGA_TEST 1
#define MAC_AX_ASIC_TEMP 1
/* temp for h2c alloc move to phl layer */
#define MAC_AX_PHL_H2C 0
/* [HV] for SIC command generagor */
#define MAC_AX_HV_SIC_GEN 0
#define MAC_AX_COEX_INIT_EN 1
/* Debug command */
#define MAC_AX_FEATURE_DBGCMD 1
/* Debug Log Decode */
#define MAC_AX_FEATURE_DBGDEC 1
#endif // #else /* for WD1 test program */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/feature_cfg.h
|
C
|
agpl-3.0
| 2,110
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FEATURE_CFG_H_
#define _MAC_AX_FEATURE_CFG_H_
/* [Note] Modify MakeFile to reduce code size */
/* Debug package for debugging */
#define MAC_AX_FEATURE_DBGPKG 1
/* Hadrware verification module */
#define MAC_AX_FEATURE_HV 0
/* Debug package for debugging */
#define MAC_AX_FW_REG_OFLD 0
/* Temp code for FPGA verification*/
#define MAC_AX_FPGA_TEST 0
/* Temp code for lack of BTC driver*/
#define MAC_AX_ASIC_TEMP 1
/* temp for h2c alloc move to phl layer*/
#define MAC_AX_PHL_H2C 1
/* Debug command */
#define MAC_AX_FEATURE_DBGCMD 1
/* Debug Log Decode */
#define MAC_AX_FEATURE_DBGDEC 1
#ifdef CONFIG_BTCOEX
#define MAC_AX_COEX_INIT_EN 0
#else
#define MAC_AX_COEX_INIT_EN 1
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/feature_cfg_drv.h
|
C
|
agpl-3.0
| 1,407
|
#ifndef _MAC_FWCMD_INTF_H_
#define _MAC_FWCMD_INTF_H_
#define FWCMD_VER 0x0
// ID definition//
//
//H2CREG
//
#define FWCMD_H2CREG_FUNC_H2CREG_LB 0x0
#define FWCMD_H2CREG_FUNC_CNSL_CMD 0x1
#define FWCMD_H2CREG_FUNC_FWERR 0x2
#define FWCMD_H2CREG_FUNC_HIDDEN_GET 0x3
#define FWCMD_H2CREG_FUNC_GETPKT_INFORM 0x4
#define FWCMD_H2CREG_FUNC_SCH_TX_EN 0x5
#define FWCMD_H2CREG_FUNC_WOW_TRX_STOP 0x6
#define FWCMD_H2CREG_FUNC_AOAC_RPT_1 0x7
#define FWCMD_H2CREG_FUNC_AOAC_RPT_2 0x8
//
//C2HREG
//
#define FWCMD_C2HREG_FUNC_C2HREG_LB 0x0
#define FWCMD_C2HREG_FUNC_ERR_RPT 0x1
#define FWCMD_C2HREG_FUNC_ERR_MSG 0x2
#define FWCMD_C2HREG_FUNC_EFUSE_HIDDEN 0x3
#define FWCMD_C2HREG_FUNC_TX_PAUSE_RPT 0x4
#define FWCMD_C2HREG_FUNC_AOAC_RPT_1 0x5
#define FWCMD_C2HREG_FUNC_AOAC_RPT_2 0x6
#define FWCMD_C2HREG_FUNC_AOAC_RPT_3 0x7
#define FWCMD_C2HREG_FUNC_WOW_TRX_STOP 0x8
#define FWCMD_C2HREG_FUNC_IO_OFLD_RESULT 0x9
//
//H2CPKT - CAT(TEST)
//
#define FWCMD_H2C_CAT_TEST 0x0
#define FWCMD_H2C_CAT_MAC 0x1
#define FWCMD_H2C_CAT_OUTSRC 0x2
#define FWCMD_H2C_CL_CMD_PATH 0x0
#define FWCMD_H2C_CL_SND_TEST 0x1
#define FWCMD_H2C_CL_PLAT_AUTO_TEST 0x2
#define FWCMD_H2C_CL_MAC_TEST 0x3
#define FWCMD_H2C_CL_FW_AUTO_TEST 0x4
#define FWCMD_H2C_CL_FW_STATUS_TEST 0x5
// CLASS 0 - CMD_PATH
#define FWCMD_H2C_FUNC_H2C_LB 0x0
// CLASS 1 - SND_Test
// CLASS 2 - PLATFORM_AUTO_TEST
#define FWCMD_H2C_FUNC_PLAT_SPIC_TEST 0x0
#define FWCMD_H2C_FUNC_PLAT_CPU_PLATFORM 0x1
#define FWCMD_H2C_FUNC_PLAT_EFUSE_CTRL 0x2
#define FWCMD_H2C_FUNC_PLAT_IDDMA 0x3
#define FWCMD_H2C_FUNC_PLAT_AXIDMA 0x4
#define FWCMD_H2C_FUNC_PLAT_IPSEC 0x5
#define FWCMD_H2C_FUNC_PLAT_UART 0x6
#define FWCMD_H2C_FUNC_PLAT_HIOE 0x7
#define FWCMD_H2C_FUNC_PLAT_WATCHDOG 0x8
#define FWCMD_H2C_FUNC_PLAT_SECURITY 0x9
#define FWCMD_H2C_FUNC_PLAT_FL_WRITE 0xa
#define FWCMD_H2C_FUNC_PLAT_FL_ERASE 0xb
#define FWCMD_H2C_FUNC_PL_FLASH_READ 0xc
#define FWCMD_H2C_FUNC_PLAT_MODULE_MAX 0x10
#define FWCMD_H2C_FUNC_PLAT_INVALID 0x11
// CLASS 3 - MAC_TEST
#define FWCMD_H2C_FUNC_LONG_RUN 0x0
// CLASS 4 - FW_AUTO_TEST
#define FWCMD_H2C_FUNC_LPS_TEST 0x0
#define FWCMD_H2C_FUNC_LPS_ONOFF_TEST 0x1
// CLASS 5 - FW_STATUS_TEST
#define FWCMD_H2C_FUNC_FW_STATUS 0x0
//
//H2CPKT - CAT(MAC)
//
#define FWCMD_H2C_CAT_TEST 0x0
#define FWCMD_H2C_CAT_MAC 0x1
#define FWCMD_H2C_CAT_OUTSRC 0x2
#define FWCMD_H2C_CL_FW_INFO 0x0
#define FWCMD_H2C_CL_WOW 0x1
#define FWCMD_H2C_CL_PS 0x2
#define FWCMD_H2C_CL_FWDL 0x3
#define FWCMD_H2C_CL_TWT 0x4
#define FWCMD_H2C_CL_FR_EXCHG 0x5
#define FWCMD_H2C_CL_ADDR_CAM_UPDATE 0x6
#define FWCMD_H2C_CL_BSSID_CAM_UPDATE 0x7
#define FWCMD_H2C_CL_MEDIA_RPT 0x8
#define FWCMD_H2C_CL_FW_OFLD 0x9
#define FWCMD_H2C_CL_SEC_CAM 0xA
#define FWCMD_H2C_CL_SOUND 0xB
#define FWCMD_H2C_CL_BA_CAM 0xC
#define FWCMD_H2C_CL_IE_CAM 0xD
#define FWCMD_H2C_CL_MCC 0xE
#define FWCMD_H2C_CL_SCSI 0xF
#define FWCMD_H2C_CL_FLASH 0x10
#define FWCMD_H2C_CL_FCS 0x11
#define FWCMD_H2C_CL_MISC 0x12
#define FWCMD_H2C_CL_MPORT 0x13
// CLASS 0 - FW_INFO
#define FWCMD_H2C_FUNC_LOG_CFG 0x0
#define FWCMD_H2C_FUNC_GENERAL_PKT 0x1
#define FWCMD_H2C_FUNC_C2H_RPT_CFG 0x2
#define FWCMD_H2C_FUNC_WLAN_DUMP_CMD 0x2
#define FWCMD_H2C_FUNC_FW_DBGREG_CFG 0x3
// CLASS 1 - WOW
#define FWCMD_H2C_FUNC_KEEP_ALIVE 0x0
#define FWCMD_H2C_FUNC_DISCONNECT_DETECT 0x1
#define FWCMD_H2C_FUNC_WOW_GLOBAL 0x2
#define FWCMD_H2C_FUNC_GTK_OFLD 0x3
#define FWCMD_H2C_FUNC_ARP_OFLD 0x4
#define FWCMD_H2C_FUNC_NDP_OFLD 0x5
#define FWCMD_H2C_FUNC_REALWOW 0x6
#define FWCMD_H2C_FUNC_NLO 0x7
#define FWCMD_H2C_FUNC_WAKEUP_CTRL 0x8
#define FWCMD_H2C_FUNC_NEGATIVE_PATTERN 0x9
#define FWCMD_H2C_FUNC_DEV2HST_GPIO 0xA
#define FWCMD_H2C_FUNC_UPHY_CTRL 0xB
#define FWCMD_H2C_FUNC_WOW_CAM_UPD 0xC
#define FWCMD_H2C_FUNC_AOAC_REPORT_REQ 0xD
#define FWCMD_H2C_FUNC_WOW_STOP_FW_TRX 0xE
// CLASS 2 - PS
#define FWCMD_H2C_FUNC_LPS_PARM 0x0
#define FWCMD_H2C_FUNC_P2P_ACT 0x1
#define FWCMD_H2C_FUNC_P2P_MACID_CTRL 0x2
#define FWCMD_H2C_FUNC_IPS_PARM 0x3
// CLASS 3 - FWDL
#define FWCMD_H2C_FUNC_FWHDR_DL 0x0
#define FWCMD_H2C_FUNC_FWHDR_REDL 0x1
// CLASS 4 - TWT
#define FWCMD_H2C_FUNC_TWT_ANNOUNCE_UPD 0x00
#define FWCMD_H2C_FUNC_TWTINFO_UPD 0x1
#define FWCMD_H2C_FUNC_TWT_STANSP_UPD 0x2
// CLASS 5 - Frame Exchange
#define FWCMD_H2C_FUNC_TBLUD 0x0
#define FWCMD_H2C_FUNC_DCTLINFO_UD 0x1
#define FWCMD_H2C_FUNC_CCTLINFO_UD 0x2
#define FWCMD_H2C_FUNC_F2P_TEST 0x3
#define FWCMD_H2C_FUNC_SHCUT_UPDATE 0x4
#define FWCMD_H2C_FUNC_BCN_UPD 0x5
#define FWCMD_H2C_FUNC_SS_ULSTA_UPD 0x6
#define FWCMD_H2C_FUNC_F2PDBG_SET 0x7
#define FWCMD_H2C_FUNC_WLANINFO_GET 0x8
#define FWCMD_H2C_FUNC_FW_STS_PARA 0x9
// CLASS 6 - Address CAM
#define FWCMD_H2C_FUNC_ADDRCAM_INFO 0x0
// CLASS 8 - Media Status Report
#define FWCMD_H2C_FUNC_JOININFO 0x0
#define FWCMD_H2C_FUNC_DL_GRP_UPD 0x1
#define FWCMD_H2C_FUNC_UL_GRP_UPD 0x2
#define FWCMD_H2C_FUNC_MU_STA_UPD 0x3
#define FWCMD_H2C_FUNC_FWROLE_MAINTAIN 0x4
#define FWCMD_H2C_FUNC_NOTIFY_DBCC 0x5
// CLASS 9 - FW_OFLD
#define FWCMD_H2C_FUNC_DUMP_EFUSE 0x0
#define FWCMD_H2C_FUNC_PACKET_OFLD 0x1
#define FWCMD_H2C_FUNC_READ_OFLD 0x2
#define FWCMD_H2C_FUNC_WRITE_OFLD 0x3
#define FWCMD_H2C_FUNC_CONF_OFLD 0x4
#define FWCMD_H2C_FUNC_SYS_INIT 0x5
#define FWCMD_H2C_FUNC_TRX_INIT 0x6
#define FWCMD_H2C_FUNC_INTF_INIT 0x7
#define FWCMD_H2C_FUNC_MACID_PAUSE 0x8
#define FWCMD_H2C_FUNC_RX_FWD 0x9
#define FWCMD_H2C_FUNC_EN_MAC_HDR_CONV 0xB
#define FWCMD_H2C_FUNC_SET_HWSEQ_REG 0xA
#define FWCMD_H2C_FUNC_HWAMSDU_REG 0xC
#define FWCMD_H2C_FUNC_AMSDU_CUT_REG 0xD
#define FWCMD_H2C_FUNC_TCPIP_CHKSUM_OFFLOAD_REG 0xE
#define FWCMD_H2C_FUNC_USR_EDCA 0xF
#define FWCMD_H2C_FUNC_TSF32_TOGL 0x10
#define FWCMD_H2C_FUNC_CMD_OFLD_REG 0x11
#define FWCMD_H2C_FUNC_USR_TX_RPT 0x12
#define FWCMD_H2C_FUNC_CMD_OFLD_PKT 0x13
#define FWCMD_H2C_FUNC_OFLD_CFG 0x14
#define FWCMD_H2C_FUNC_H2C_AGG 0x15
#define FWCMD_H2C_FUNC_ADD_SCANOFLD_CH 0x16
#define FWCMD_H2C_FUNC_SCANOFLD 0x17
#define FWCMD_H2C_FUNC_TX_DUTY 0x18
#define FWCMD_H2C_FUNC_DISABLE_RF 0x19
// CLASS 10 - SECCAM
#define FWCMD_H2C_FUNC_SEC_CAM_INIT 0x0
#define FWCMD_H2C_FUNC_SECCAM_INFO 0x1
// CLASS 11 - Sound
#define FWCMD_H2C_FUNC_SET_SND_PARA 0x0
#define FWCMD_H2C_FUNC_GET_CSI_BUF 0x1
#define FWCMD_H2C_FUNC_SET_CSI_BUF 0x2
#define FWCMD_H2C_FUNC_GET_SND_STS 0x3
#define FWCMD_H2C_FUNC_SET_SND_STS 0x4
#define FWCMD_H2C_FUNC_INIT_SND_MER 0x5
#define FWCMD_H2C_FUNC_INIT_SND_MEE 0x6
#define FWCMD_H2C_FUNC_CSI_FIX_RATE 0x7
#define FWCMD_H2C_FUNC_CSI_RRSC 0x8
#define FWCMD_H2C_FUNC_SET_MU_TABLE 0x9
#define FWCMD_H2C_FUNC_SET_CSI_PARA_REG 0xA
#define FWCMD_H2C_FUNC_HW_SND_PR 0xB
#define FWCMD_H2C_FUNC_BYPASS_SND_STS 0xC
#define FWCMD_H2C_FUNC_SET_SND_PARA_V1 0xD
// CLASS 12 - BACAM
#define FWCMD_H2C_FUNC_BA_CAM 0x0
// CLASS 13 - IECAM
#define FWCMD_H2C_FUNC_IE_CAM 0x0
// CLASS 14 - MCC
#define FWCMD_H2C_FUNC_ADD_MCC 0x0
#define FWCMD_H2C_FUNC_START_MCC 0x1
#define FWCMD_H2C_FUNC_STOP_MCC 0x2
#define FWCMD_H2C_FUNC_DEL_MCC_GROUP 0x3
#define FWCMD_H2C_FUNC_RESET_MCC_GROUP 0x4
#define FWCMD_H2C_FUNC_MCC_REQ_TSF 0x5
#define FWCMD_H2C_FUNC_MCC_MACID_BITMAP 0x6
#define FWCMD_H2C_FUNC_MCC_SYNC 0x7
#define FWCMD_H2C_FUNC_MCC_SET_DURATION 0x8
// CLASS 15 - SCSI
#define FWCMD_H2C_FUNC_SCSI_TX 0x0
#define FWCMD_H2C_FUNC_USB_SWITCH 0x1
// CLASS 16 - FLASH
#define FWCMD_H2C_FUNC_PLAT_FLASH_WRITE 0x0
#define FWCMD_H2C_FUNC_PLAT_FLASH_ERASE 0x1
#define FWCMD_H2C_FUNC_PLAT_FLASH_READ 0x2
// CLASS 17 - FCS
#define FWCMD_H2C_FUNC_FCS 0x0
// CLASS 18 - MISC
#define FWCMD_H2C_FUNC_CFG_WPS 0x0
// CLASS 19 - MPORT
#define FWCMD_H2C_FUNC_PORT_INIT 0x0
#define FWCMD_H2C_FUNC_PORT_CFG 0x1
//
//H2CPKT - CAT(Table)
//
//
//H2CPKT - CAT(OutSrc,Phydm)
//
#define FWCMD_H2C_CAT_TEST 0x0
#define FWCMD_H2C_CAT_MAC 0x1
#define FWCMD_H2C_CAT_OUTSRC 0x2
#define FWCMD_H2C_CL_RUA 0x0
#define FWCMD_H2C_CL_RA 0x1
// CLASS 0 (RUA)
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 1 (RA)
#define FWCMD_H2C_FUNC_MACID_CFG 0x0
#define FWCMD_H2C_FUNC_RSSI_RA_CONFIG 0x1
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 2
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 3
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 4
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 5
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 6
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 7
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
//
//H2CPKT - CAT(OutSrc, RF)
//
#define FWCMD_H2C_CAT_TEST 0x0
#define FWCMD_H2C_CAT_MAC 0x1
#define FWCMD_H2C_CAT_OUTSRC 0x2
// CLASS 8
#define FWCMD_H2C_FUNC_RADIO_INIT_0 0x0
#define FWCMD_H2C_FUNC_RADIO_INIT_1 0x1
#define FWCMD_H2C_FUNC_RADIO_INIT_2 0x2
#define FWCMD_H2C_FUNC_RADIO_INIT_3 0x3
#define FWCMD_H2C_FUNC_RADIO_INIT_4 0x4
#define FWCMD_H2C_FUNC_RADIO_INIT_5 0x5
#define FWCMD_H2C_FUNC_RADIO_INIT_6 0x6
#define FWCMD_H2C_FUNC_RADIO_INIT_7 0x7
#define FWCMD_H2C_FUNC_RADIO_INIT_8 0x8
#define FWCMD_H2C_FUNC_RADIO_INIT_9 0x9
// CLASS 9
#define FWCMD_H2C_FUNC_DACK_BACKUP 0x0
#define FWCMD_H2C_FUNC_DACK_RELOAD 0x1
// CLASS 10
#define FWCMD_H2C_FUNC_FCS_BACKUP_RFK 0x0
#define FWCMD_H2C_FUNC_FCS_RELOAD_RFK 0x1
#define FWCMD_H2C_FUNC_GET_MCCCH 0x2
#define FWCMD_H2C_FUNC_FWIQK_TRIGGER 0x4
// CLASS 11
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 12
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 13
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 14
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
// CLASS 15
#define FWCMD_H2C_FUNC_EXAMPLE 0x0
//
//H2CPKT - CAT(OutSrc, BTC)
//
#define FWCMD_H2C_CAT_TEST 0x0
#define FWCMD_H2C_CAT_MAC 0x1
#define FWCMD_H2C_CAT_OUTSRC 0x2
// CLASS 16
#define FWCMD_H2C_FUNC_TDMA 0x0
//
//C2HPKT - CAT(TEST)
//
#define FWCMD_C2H_CAT_TEST 0x0
#define FWCMD_C2H_CAT_MAC 0x1
#define FWCMD_C2H_CAT_OUTSRC 0x2
#define FWCMD_C2H_CL_CMD_PATH 0x0
#define FWCMD_C2H_CL_PLAT_AUTO 0x2
#define FWCMD_C2H_CL_FW_AUTO 0x3
#define FWCMD_C2H_CL_FW_STATUS 0x4
// CLASS 0 - CMD_PATH
#define FWCMD_C2H_FUNC_C2H_LB 0x00
#define FWCMD_C2H_FUNC_TEST_PHY_RPT 0x01
// CLASS 2 - PLATFORM_AUTO_TEST
#define FWCMD_C2H_FUNC_SPIC 0x00
#define FWCMD_C2H_FUNC_SPIC2 0x01
// CLASS 3 - FW_AUTO_TEST
#define FWCMD_C2H_FUNC_LPS_TEST 0x00
#define FWCMD_C2H_FUNC_LPS_ONOFF_TEST 0x1
// CLASS 4 - FW_STATUS
#define FWCMD_C2H_FUNC_FW_STATUS 0x00
//
//C2HPKT - CAT(MAC)
//
#define FWCMD_C2H_CAT_TEST 0x0
#define FWCMD_C2H_CAT_MAC 0x1
#define FWCMD_C2H_CAT_OUTSRC 0x2
#define FWCMD_C2H_CL_FW_INFO 0x0
#define FWCMD_C2H_CL_FW_OFLD 0x1
#define FWCMD_C2H_CL_TWT 0x2
#define FWCMD_C2H_CL_WOW 0x3
#define FWCMD_C2H_CL_MCC 0x4
#define FWCMD_C2H_CL_FW_DBG 0x5
#define FWCMD_C2H_CL_FLASH 0x6
#define FWCMD_C2H_CL_SCSI 0x7
#define FWCMD_C2H_CL_FCS 0x8
#define FWCMD_C2H_CL_MISC 0x9
#define FWCMD_C2H_CL_MPORT 0xA
#define FWCMD_C2H_CL_OFDMA_INFO 0xB
// CLASS 0 - FW_INFO
#define FWCMD_C2H_FUNC_REC_ACK 0x00
#define FWCMD_C2H_FUNC_DONE_ACK 0x01
#define FWCMD_C2H_FUNC_C2H_LOG 0x02
#define FWCMD_C2H_FUNC_BCN_CNT 0x03
#define FWCMD_C2H_FUNC_BCN_CSAZERO 0x04
// CLASS 1 - FW_OFLD
#define FWCMD_C2H_FUNC_EFUSE_DUMP 0x00
#define FWCMD_C2H_FUNC_READ_RSP 0x01
#define FWCMD_C2H_FUNC_PKT_OFLD_RSP 0x02
#define FWCMD_C2H_FUNC_BEACON_RESEND 0x3
#define FWCMD_C2H_FUNC_MACID_PAUSE 0x4
#define FWCMD_C2H_FUNC_FW_GETPKT_RPT 0x5
#define FWCMD_C2H_FUNC_TSF32_TOGL_RPT 0x6
#define FWCMD_C2H_FUNC_USR_TX_RPT_INFO 0x7
#define FWCMD_C2H_FUNC_CMD_OFLD_RSP 0x8
#define FWCMD_C2H_FUNC_SCANOFLD_RSP 0x9
#define FWCMD_C2H_FUNC_TX_DUTY_RPT 0xA
// CLASS 2 - TWT
#define FWCMD_C2H_FUNC_WAIT_ANNOUNCE 0x00
// CLASS 3 - WOW
#define FWCMD_C2H_FUNC_AOAC_REPORT 0x00
#define FWCMD_C2H_FUNC_READ_WOW_CAM 0x01
// CLASS 4 - MCC
#define FWCMD_C2H_FUNC_MCC_RCV_ACK 0x00
#define FWCMD_C2H_FUNC_MCC_REQ_ACK 0x01
#define FWCMD_C2H_FUNC_MCC_TSF_RPT 0x02
#define FWCMD_C2H_FUNC_MCC_STATUS_RPT 0x03
// CLASS 5 - FW_DBG
#define FWCMD_C2H_FUNC_RX_DBG 0x00
// CLASS 6 - FLASH
#define FWCMD_C2H_FUNC_PLAT_FLASH_WRITE 0x0
#define FWCMD_C2H_FUNC_PLAT_FLASH_ERASE 0x1
#define FWCMD_C2H_FUNC_PLAT_FLASH_READ 0x2
// CLASS 7 - SCSI
#define FWCMD_C2H_FUNC_SCSI_RX 0x00
// CLASS 8 - FCS
#define FWCMD_C2H_FUNC_FCS_RPT 0x00
// CLASS 9 - MISC
#define FWCMD_C2H_FUNC_WPS_RPT 0x0
#define FWCMD_C2H_FUNC_CCXRPT 0x1
// CLASS 10 - MPORT
#define FWCMD_C2H_FUNC_PORT_INIT_STAT 0x0
#define FWCMD_C2H_FUNC_PORT_CFG_STAT 0x1
// CLASS 11 - OFDMA_STS
#define FWCMD_C2H_FUNC_OFDMA_STS 0x00
//
//C2HPKT - CAT(OutSrc, Phydm)
//
#define FWCMD_C2H_CAT_TEST 0x0
#define FWCMD_C2H_CAT_MAC 0x1
#define FWCMD_C2H_CAT_OUTSRC 0x2
#define FWCMD_C2H_CL_RUA 0x0
#define FWCMD_C2H_CL_RA 0x1
#define FWCMD_C2H_CL_HALBB 0x2
#define FWCMD_C2H_CL_DBG 0x7
// CLASS 0
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 1
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 2
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 3
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 4
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 5
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 6
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 7
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
//
//C2HPKT - CAT(OutSrc, RF)
//
#define FWCMD_C2H_CAT_TEST 0x0
#define FWCMD_C2H_CAT_MAC 0x1
#define FWCMD_C2H_CAT_OUTSRC 0x2
// CLASS 9
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 10
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 11
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 12
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 13
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 14
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// CLASS 15
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
//
//C2HPKT - CAT(OutSrc, BTC)
//
#define FWCMD_C2H_CAT_TEST 0x0
#define FWCMD_C2H_CAT_MAC 0x1
#define FWCMD_C2H_CAT_OUTSRC 0x2
// CLASS 16
#define FWCMD_C2H_FUNC_EXAMPLE 0x0
// Bit definition//
//
//H2CREG
//
#define FWCMD_H2CREG_H2CREG_HDR_FUNC_SH 0
#define FWCMD_H2CREG_H2CREG_HDR_FUNC_MSK 0x7f
#define FWCMD_H2CREG_H2CREG_HDR_ACK BIT(7)
#define FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_H2CREG_HDR_SEQ_NUM_SH 12
#define FWCMD_H2CREG_H2CREG_HDR_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_H2CREG_DWORD0_SH 0
#define FWCMD_H2CREG_H2CREG_DWORD0_MSK 0xffffffff
#define FWCMD_H2CREG_H2CREG_DWORD1_SH 0
#define FWCMD_H2CREG_H2CREG_DWORD1_MSK 0xffffffff
#define FWCMD_H2CREG_H2CREG_DWORD2_SH 0
#define FWCMD_H2CREG_H2CREG_DWORD2_MSK 0xffffffff
#define FWCMD_H2CREG_H2CREG_DWORD3_SH 0
#define FWCMD_H2CREG_H2CREG_DWORD3_MSK 0xffffffff
#define FWCMD_H2CREG_H2CREG_LB_FUNC_SH 0
#define FWCMD_H2CREG_H2CREG_LB_FUNC_MSK 0x7f
#define FWCMD_H2CREG_H2CREG_LB_ACK BIT(7)
#define FWCMD_H2CREG_H2CREG_LB_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_H2CREG_LB_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_H2CREG_LB_SEQ_NUM_SH 12
#define FWCMD_H2CREG_H2CREG_LB_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD0_SH 16
#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD0_MSK 0xffff
#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD1_SH 0
#define FWCMD_H2CREG_H2CREG_LB_PAYLOAD1_MSK 0xffffffff
#define FWCMD_H2CREG_CNSL_CMD_FUNC_SH 0
#define FWCMD_H2CREG_CNSL_CMD_FUNC_MSK 0x7f
#define FWCMD_H2CREG_CNSL_CMD_ACK BIT(7)
#define FWCMD_H2CREG_CNSL_CMD_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_CNSL_CMD_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_CNSL_CMD_SEQ_NUM_SH 12
#define FWCMD_H2CREG_CNSL_CMD_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_CNSL_CMD_CMD_ID_SH 16
#define FWCMD_H2CREG_CNSL_CMD_CMD_ID_MSK 0xff
#define FWCMD_H2CREG_CNSL_CMD_ARG_NUM_SH 24
#define FWCMD_H2CREG_CNSL_CMD_ARG_NUM_MSK 0xf
#define FWCMD_H2CREG_CNSL_CMD_ARG_UNIT_SH 28
#define FWCMD_H2CREG_CNSL_CMD_ARG_UNIT_MSK 0x3
#define FWCMD_H2CREG_FWERR_FUNC_SH 0
#define FWCMD_H2CREG_FWERR_FUNC_MSK 0x7f
#define FWCMD_H2CREG_FWERR_ACK BIT(7)
#define FWCMD_H2CREG_FWERR_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_FWERR_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_FWERR_SEQ_NUM_SH 12
#define FWCMD_H2CREG_FWERR_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_FWERR_OP_SH 16
#define FWCMD_H2CREG_FWERR_OP_MSK 0xf
#define FWCMD_H2CREG_FWERR_IDX_SH 0
#define FWCMD_H2CREG_FWERR_IDX_MSK 0xffffffff
#define FWCMD_H2CREG_HIDDEN_GET_FUNC_SH 0
#define FWCMD_H2CREG_HIDDEN_GET_FUNC_MSK 0x7f
#define FWCMD_H2CREG_HIDDEN_GET_ACK BIT(7)
#define FWCMD_H2CREG_HIDDEN_GET_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_HIDDEN_GET_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_HIDDEN_GET_SEQ_NUM_SH 12
#define FWCMD_H2CREG_HIDDEN_GET_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_GETPKT_INFORM_FUNC_SH 0
#define FWCMD_H2CREG_GETPKT_INFORM_FUNC_MSK 0x7f
#define FWCMD_H2CREG_GETPKT_INFORM_ACK BIT(7)
#define FWCMD_H2CREG_GETPKT_INFORM_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_GETPKT_INFORM_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_GETPKT_INFORM_SEQ_NUM_SH 12
#define FWCMD_H2CREG_GETPKT_INFORM_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_GETPKT_INFORM_MACID_SH 16
#define FWCMD_H2CREG_GETPKT_INFORM_MACID_MSK 0xff
#define FWCMD_H2CREG_GETPKT_INFORM_PKTTYPE_SH 24
#define FWCMD_H2CREG_GETPKT_INFORM_PKTTYPE_MSK 0xff
#define FWCMD_H2CREG_SCH_TX_EN_FUNC_SH 0
#define FWCMD_H2CREG_SCH_TX_EN_FUNC_MSK 0x7f
#define FWCMD_H2CREG_SCH_TX_EN_ACK BIT(7)
#define FWCMD_H2CREG_SCH_TX_EN_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_SCH_TX_EN_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_SCH_TX_EN_SEQ_NUM_SH 12
#define FWCMD_H2CREG_SCH_TX_EN_SEQ_NUM_MSK 0xf
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BE0 BIT(16)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BK0 BIT(17)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VI0 BIT(18)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VO0 BIT(19)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BE1 BIT(20)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BK1 BIT(21)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VI1 BIT(22)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_VO1 BIT(23)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_MG0 BIT(24)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_MG1 BIT(25)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_MG2 BIT(26)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_HI BIT(27)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_BCN BIT(28)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_UL BIT(29)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_TWT0 BIT(30)
#define FWCMD_H2CREG_SCH_TX_EN_TX_EN_TWT1 BIT(31)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_BE0 BIT(0)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_BK0 BIT(1)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_VI0 BIT(2)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_VO0 BIT(3)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_BE1 BIT(4)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_BK1 BIT(5)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_VI1 BIT(6)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_VO1 BIT(7)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_MG0 BIT(8)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_MG1 BIT(9)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_MG2 BIT(10)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_HI BIT(11)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_BCN BIT(12)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_UL BIT(13)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_TWT0 BIT(14)
#define FWCMD_H2CREG_SCH_TX_EN_MASK_TWT1 BIT(15)
#define FWCMD_H2CREG_SCH_TX_EN_BAND BIT(16)
#define FWCMD_H2CREG_WOW_TRX_STOP_FUNC_SH 0
#define FWCMD_H2CREG_WOW_TRX_STOP_FUNC_MSK 0x7f
#define FWCMD_H2CREG_WOW_TRX_STOP_ACK BIT(7)
#define FWCMD_H2CREG_WOW_TRX_STOP_TOTAL_LEN_SH 8
#define FWCMD_H2CREG_WOW_TRX_STOP_TOTAL_LEN_MSK 0xf
#define FWCMD_H2CREG_WOW_TRX_STOP_SEQ_NUM_SH 12
#define FWCMD_H2CREG_WOW_TRX_STOP_SEQ_NUM_MSK 0xf
//
//C2HREG
//
#define FWCMD_C2HREG_C2HREG_HDR_FUNC_SH 0
#define FWCMD_C2HREG_C2HREG_HDR_FUNC_MSK 0x7f
#define FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_C2HREG_HDR_SEQ_NUM_SH 12
#define FWCMD_C2HREG_C2HREG_HDR_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_C2HREG_DWORD0_SH 0
#define FWCMD_C2HREG_C2HREG_DWORD0_MSK 0xffffffff
#define FWCMD_C2HREG_C2HREG_DWORD1_SH 0
#define FWCMD_C2HREG_C2HREG_DWORD1_MSK 0xffffffff
#define FWCMD_C2HREG_C2HREG_DWORD2_SH 0
#define FWCMD_C2HREG_C2HREG_DWORD2_MSK 0xffffffff
#define FWCMD_C2HREG_C2HREG_DWORD3_SH 0
#define FWCMD_C2HREG_C2HREG_DWORD3_MSK 0xffffffff
#define FWCMD_C2HREG_C2HREG_LB_FUNC_SH 0
#define FWCMD_C2HREG_C2HREG_LB_FUNC_MSK 0x7f
#define FWCMD_C2HREG_C2HREG_LB_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_C2HREG_LB_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_C2HREG_LB_SEQ_NUM_SH 12
#define FWCMD_C2HREG_C2HREG_LB_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD0_SH 16
#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD0_MSK 0xffff
#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD1_SH 0
#define FWCMD_C2HREG_C2HREG_LB_PAYLOAD1_MSK 0xffffffff
#define FWCMD_C2HREG_ERR_RPT_FUNC_SH 0
#define FWCMD_C2HREG_ERR_RPT_FUNC_MSK 0x7f
#define FWCMD_C2HREG_ERR_RPT_ACK BIT(7)
#define FWCMD_C2HREG_ERR_RPT_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_ERR_RPT_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_ERR_RPT_SEQ_NUM_SH 12
#define FWCMD_C2HREG_ERR_RPT_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_ERR_RPT_IDX_SH 16
#define FWCMD_C2HREG_ERR_RPT_IDX_MSK 0xf
#define FWCMD_C2HREG_ERR_RPT_CODE_SH 0
#define FWCMD_C2HREG_ERR_RPT_CODE_MSK 0xffffffff
#define FWCMD_C2HREG_ERR_MSG_FUNC_SH 0
#define FWCMD_C2HREG_ERR_MSG_FUNC_MSK 0x7f
#define FWCMD_C2HREG_ERR_MSG_ACK BIT(7)
#define FWCMD_C2HREG_ERR_MSG_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_ERR_MSG_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_ERR_MSG_SEQ_NUM_SH 12
#define FWCMD_C2HREG_ERR_MSG_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_ERR_MSG_MSG_SH 16
#define FWCMD_C2HREG_ERR_MSG_MSG_MSK 0xffff
#define FWCMD_C2HREG_EFUSE_HIDDEN_FUNC_SH 0
#define FWCMD_C2HREG_EFUSE_HIDDEN_FUNC_MSK 0x7f
#define FWCMD_C2HREG_EFUSE_HIDDEN_ACK BIT(7)
#define FWCMD_C2HREG_EFUSE_HIDDEN_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_EFUSE_HIDDEN_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_EFUSE_HIDDEN_SEQ_NUM_SH 12
#define FWCMD_C2HREG_EFUSE_HIDDEN_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_EFUSE_HIDDEN_RX_NSS_SH 16
#define FWCMD_C2HREG_EFUSE_HIDDEN_RX_NSS_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_BW_SH 24
#define FWCMD_C2HREG_EFUSE_HIDDEN_BW_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_TX_NSS_SH 0
#define FWCMD_C2HREG_EFUSE_HIDDEN_TX_NSS_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_PROT80211_SH 8
#define FWCMD_C2HREG_EFUSE_HIDDEN_PROT80211_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_NIC_ROUTER_SH 16
#define FWCMD_C2HREG_EFUSE_HIDDEN_NIC_ROUTER_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_WL_FUNC_SUPPORT_SH 24
#define FWCMD_C2HREG_EFUSE_HIDDEN_WL_FUNC_SUPPORT_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_HW_SPECIAL_TYPE_SH 0
#define FWCMD_C2HREG_EFUSE_HIDDEN_HW_SPECIAL_TYPE_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_0_SH 8
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_0_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_1_SH 16
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_1_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_2_SH 24
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_2_MSK 0xff
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_3_SH 0
#define FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_3_MSK 0xff
#define FWCMD_C2HREG_TX_PAUSE_RPT_FUNC_SH 0
#define FWCMD_C2HREG_TX_PAUSE_RPT_FUNC_MSK 0x7f
#define FWCMD_C2HREG_TX_PAUSE_RPT_ACK BIT(7)
#define FWCMD_C2HREG_TX_PAUSE_RPT_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_TX_PAUSE_RPT_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_TX_PAUSE_RPT_SEQ_NUM_SH 12
#define FWCMD_C2HREG_TX_PAUSE_RPT_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_TX_PAUSE_RPT_RPT_SH 16
#define FWCMD_C2HREG_TX_PAUSE_RPT_RPT_MSK 0xffff
#define FWCMD_C2HREG_AOAC_RPT_1_FUNC_SH 0
#define FWCMD_C2HREG_AOAC_RPT_1_FUNC_MSK 0x7f
#define FWCMD_C2HREG_AOAC_RPT_1_ACK BIT(7)
#define FWCMD_C2HREG_AOAC_RPT_1_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_AOAC_RPT_1_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_AOAC_RPT_1_SEQ_NUM_SH 12
#define FWCMD_C2HREG_AOAC_RPT_1_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_AOAC_RPT_1_KEY_IDX_SH 16
#define FWCMD_C2HREG_AOAC_RPT_1_KEY_IDX_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_REKEY_OK_SH 24
#define FWCMD_C2HREG_AOAC_RPT_1_REKEY_OK_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_0_SH 0
#define FWCMD_C2HREG_AOAC_RPT_1_IV_0_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_1_SH 8
#define FWCMD_C2HREG_AOAC_RPT_1_IV_1_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_2_SH 16
#define FWCMD_C2HREG_AOAC_RPT_1_IV_2_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_3_SH 24
#define FWCMD_C2HREG_AOAC_RPT_1_IV_3_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_4_SH 0
#define FWCMD_C2HREG_AOAC_RPT_1_IV_4_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_5_SH 8
#define FWCMD_C2HREG_AOAC_RPT_1_IV_5_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_6_SH 16
#define FWCMD_C2HREG_AOAC_RPT_1_IV_6_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_IV_7_SH 24
#define FWCMD_C2HREG_AOAC_RPT_1_IV_7_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_0_SH 0
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_0_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_1_SH 8
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_1_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_2_SH 16
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_2_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_3_SH 24
#define FWCMD_C2HREG_AOAC_RPT_1_PKT_IV_3_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_FUNC_SH 0
#define FWCMD_C2HREG_AOAC_RPT_2_FUNC_MSK 0x7f
#define FWCMD_C2HREG_AOAC_RPT_2_ACK BIT(7)
#define FWCMD_C2HREG_AOAC_RPT_2_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_AOAC_RPT_2_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_AOAC_RPT_2_SEQ_NUM_SH 12
#define FWCMD_C2HREG_AOAC_RPT_2_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_4_SH 16
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_4_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_5_SH 24
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_5_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_6_SH 0
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_6_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_7_SH 8
#define FWCMD_C2HREG_AOAC_RPT_2_PKT_IV_7_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_0_SH 16
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_0_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_1_SH 24
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_1_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_2_SH 0
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_2_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_3_SH 8
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_3_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_4_SH 16
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_4_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_5_SH 24
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_5_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_6_SH 0
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_6_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_7_SH 8
#define FWCMD_C2HREG_AOAC_RPT_2_IGTK_IPN_7_MSK 0xff
#define FWCMD_C2HREG_AOAC_RPT_2_RPT_MSK 0xffff
#define FWCMD_C2HREG_AOAC_RPT_3_FUNC_SH 0
#define FWCMD_C2HREG_AOAC_RPT_3_FUNC_MSK 0x7f
#define FWCMD_C2HREG_AOAC_RPT_3_ACK BIT(7)
#define FWCMD_C2HREG_AOAC_RPT_3_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_AOAC_RPT_3_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_AOAC_RPT_3_SEQ_NUM_SH 12
#define FWCMD_C2HREG_AOAC_RPT_3_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_AOAC_RPT_3_RPT_SH 16
#define FWCMD_C2HREG_AOAC_RPT_3_RPT_MSK 0xffff
#define FWCMD_C2HREG_WOW_TRX_STOP_FUNC_SH 0
#define FWCMD_C2HREG_WOW_TRX_STOP_FUNC_MSK 0x7f
#define FWCMD_C2HREG_WOW_TRX_STOP_ACK BIT(7)
#define FWCMD_C2HREG_WOW_TRX_STOP_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_WOW_TRX_STOP_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_WOW_TRX_STOP_SEQ_NUM_SH 12
#define FWCMD_C2HREG_WOW_TRX_STOP_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_WOW_TRX_STOP_RPT_SH 16
#define FWCMD_C2HREG_WOW_TRX_STOP_RPT_MSK 0xffff
#define FWCMD_C2HREG_IO_OFLD_RESULT_FUNC_SH 0
#define FWCMD_C2HREG_IO_OFLD_RESULT_FUNC_MSK 0x7f
#define FWCMD_C2HREG_IO_OFLD_RESULT_TOTAL_LEN_SH 8
#define FWCMD_C2HREG_IO_OFLD_RESULT_TOTAL_LEN_MSK 0xf
#define FWCMD_C2HREG_IO_OFLD_RESULT_SEQ_NUM_SH 12
#define FWCMD_C2HREG_IO_OFLD_RESULT_SEQ_NUM_MSK 0xf
#define FWCMD_C2HREG_IO_OFLD_RESULT_RET_SH 16
#define FWCMD_C2HREG_IO_OFLD_RESULT_RET_MSK 0xff
#define FWCMD_C2HREG_IO_OFLD_RESULT_CMD_NUM_SH 24
#define FWCMD_C2HREG_IO_OFLD_RESULT_CMD_NUM_MSK 0xff
#define FWCMD_C2HREG_IO_OFLD_RESULT_OFFSET_SH 0
#define FWCMD_C2HREG_IO_OFLD_RESULT_OFFSET_MSK 0xffffffff
#define FWCMD_C2HREG_IO_OFLD_RESULT_EXP_VAL_SH 0
#define FWCMD_C2HREG_IO_OFLD_RESULT_EXP_VAL_MSK 0xffffffff
#define FWCMD_C2HREG_IO_OFLD_RESULT_R_VAL_SH 0
#define FWCMD_C2HREG_IO_OFLD_RESULT_R_VAL_MSK 0xffffffff
//
//H2CPKT - CAT(TEST)
//
#define H2C_HDR_CAT_SH 0
#define H2C_HDR_CAT_MSK 0x3
#define H2C_HDR_CLASS_SH 2
#define H2C_HDR_CLASS_MSK 0x3f
#define H2C_HDR_FUNC_SH 8
#define H2C_HDR_FUNC_MSK 0xff
#define H2C_HDR_DEL_TYPE_SH 16
#define H2C_HDR_DEL_TYPE_MSK 0xf
#define H2C_HDR_H2C_SEQ_SH 24
#define H2C_HDR_H2C_SEQ_MSK 0xff
#define H2C_HDR_TOTAL_LEN_SH 0
#define H2C_HDR_TOTAL_LEN_MSK 0x3fff
#define H2C_HDR_REC_ACK BIT(14)
#define H2C_HDR_DONE_ACK BIT(15)
#define H2C_HDR_SEQ_VALID BIT(16)
#define H2C_HDR_SEQ_SH 17
#define H2C_HDR_SEQ_MSK 0x7
#define H2C_HDR_SEQ_STOP BIT(20)
#define FWCMD_H2C_H2C_LB_PAYLOAD0_SH 0
#define FWCMD_H2C_H2C_LB_PAYLOAD0_MSK 0xffffffff
#define FWCMD_H2C_H2C_LB_PAYLOAD1_SH 0
#define FWCMD_H2C_H2C_LB_PAYLOAD1_MSK 0xffffffff
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD0_SH 0
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD0_MSK 0xffffffff
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD1_SH 0
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD1_MSK 0xffffffff
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD2_SH 0
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD2_MSK 0xffffffff
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD3_SH 0
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD3_MSK 0xffffffff
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD4_SH 0
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD4_MSK 0xffffffff
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD5_SH 0
#define FWCMD_H2C_PLAT_SPIC_TEST_PAYLOAD5_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FL_WRITE_ADDR_SH 0
#define FWCMD_H2C_PLAT_FL_WRITE_ADDR_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FL_WRITE_LENGTH_SH 0
#define FWCMD_H2C_PLAT_FL_WRITE_LENGTH_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FL_ERASE_ADDR_SH 0
#define FWCMD_H2C_PLAT_FL_ERASE_ADDR_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FL_ERASE_LENGTH_SH 0
#define FWCMD_H2C_PLAT_FL_ERASE_LENGTH_MSK 0xffffffff
#define FWCMD_H2C_PL_FLASH_READ_ADDR_SH 0
#define FWCMD_H2C_PL_FLASH_READ_ADDR_MSK 0xffffffff
#define FWCMD_H2C_PL_FLASH_READ_LENGTH_SH 0
#define FWCMD_H2C_PL_FLASH_READ_LENGTH_MSK 0xffffffff
#define FWCMD_H2C_LONG_RUN_PAYLOAD0_SH 0
#define FWCMD_H2C_LONG_RUN_PAYLOAD0_MSK 0xffffffff
#define FWCMD_H2C_LONG_RUN_PAYLOAD1_SH 0
#define FWCMD_H2C_LONG_RUN_PAYLOAD1_MSK 0xffffffff
#define FWCMD_H2C_LPS_TEST_COUNT_SH 0
#define FWCMD_H2C_LPS_TEST_COUNT_MSK 0xffffffff
#define FWCMD_H2C_LPS_ONOFF_TEST_TYPE_SH 0
#define FWCMD_H2C_LPS_ONOFF_TEST_TYPE_MSK 0xffffffff
#define FWCMD_H2C_LPS_ONOFF_TEST_PARA_SH 0
#define FWCMD_H2C_LPS_ONOFF_TEST_PARA_MSK 0xffffffff
#define FWCMD_H2C_FW_STATUS_COUNT_SH 0
#define FWCMD_H2C_FW_STATUS_COUNT_MSK 0xffffffff
//
//H2CPKT - CAT(MAC)
//
#define H2C_HDR_CAT_SH 0
#define H2C_HDR_CAT_MSK 0x3
#define H2C_HDR_CLASS_SH 2
#define H2C_HDR_CLASS_MSK 0x3f
#define H2C_HDR_FUNC_SH 8
#define H2C_HDR_FUNC_MSK 0xff
#define H2C_HDR_DEL_TYPE_SH 16
#define H2C_HDR_DEL_TYPE_MSK 0xf
#define H2C_HDR_H2C_SEQ_SH 24
#define H2C_HDR_H2C_SEQ_MSK 0xff
#define H2C_HDR_TOTAL_LEN_SH 0
#define H2C_HDR_TOTAL_LEN_MSK 0x3fff
#define H2C_HDR_REC_ACK BIT(14)
#define H2C_HDR_DONE_ACK BIT(15)
#define H2C_HDR_SEQ_VALID BIT(16)
#define H2C_HDR_SEQ_SH 17
#define H2C_HDR_SEQ_MSK 0x7
#define H2C_HDR_SEQ_STOP BIT(20)
#define FWCMD_H2C_LOG_CFG_DBG_LV_SH 0
#define FWCMD_H2C_LOG_CFG_DBG_LV_MSK 0xff
#define FWCMD_H2C_LOG_CFG_PATH_SH 8
#define FWCMD_H2C_LOG_CFG_PATH_MSK 0xff
#define FWCMD_H2C_LOG_CFG_COMP_SH 0
#define FWCMD_H2C_LOG_CFG_COMP_MSK 0xffffffff
#define FWCMD_H2C_LOG_CFG_COMP_EXT_SH 0
#define FWCMD_H2C_LOG_CFG_COMP_EXT_MSK 0xffffffff
#define FWCMD_H2C_GENERAL_PKT_MACID_SH 0
#define FWCMD_H2C_GENERAL_PKT_MACID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_PROBRSP_ID_SH 8
#define FWCMD_H2C_GENERAL_PKT_PROBRSP_ID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_PSPOLL_ID_SH 16
#define FWCMD_H2C_GENERAL_PKT_PSPOLL_ID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_NULL_ID_SH 24
#define FWCMD_H2C_GENERAL_PKT_NULL_ID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_QOS_NULL_ID_SH 0
#define FWCMD_H2C_GENERAL_PKT_QOS_NULL_ID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_CTS2SELF_ID_SH 8
#define FWCMD_H2C_GENERAL_PKT_CTS2SELF_ID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_PROBREQ_ID_SH 16
#define FWCMD_H2C_GENERAL_PKT_PROBREQ_ID_MSK 0xff
#define FWCMD_H2C_GENERAL_PKT_APCSA_ID_SH 24
#define FWCMD_H2C_GENERAL_PKT_APCSA_ID_MSK 0xff
#define FWCMD_H2C_C2H_RPT_CFG_TX_STATISTIC_EN BIT(0)
#define FWCMD_H2C_C2H_RPT_CFG_RX_STATISTIC_EN BIT(1)
#define FWCMD_H2C_C2H_RPT_CFG_BEACON_STATISTIC_EN BIT(2)
#define FWCMD_H2C_C2H_RPT_CFG_DL_STATISTIC_EN BIT(3)
#define FWCMD_H2C_C2H_RPT_CFG_RPT_INTERVAL_SH 0
#define FWCMD_H2C_C2H_RPT_CFG_RPT_INTERVAL_MSK 0xffff
#define FWCMD_H2C_WLAN_DUMP_CMD_CMD_ID_SH 0
#define FWCMD_H2C_WLAN_DUMP_CMD_CMD_ID_MSK 0xf
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV0_SH 8
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV0_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV1_SH 16
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV1_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV2_SH 24
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV2_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV3_SH 0
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV3_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV4_SH 8
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV4_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV5_SH 16
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV5_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV6_SH 24
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV6_MSK 0xff
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV7_SH 0
#define FWCMD_H2C_WLAN_DUMP_CMD_ARGV7_MSK 0xff
#define FWCMD_H2C_FW_DBGREG_CFG_FW_DBG_LOCK BIT(0)
#define FWCMD_H2C_KEEP_ALIVE_KEEPALIVE_EN BIT(0)
#define FWCMD_H2C_KEEP_ALIVE_PACKET_ID_SH 8
#define FWCMD_H2C_KEEP_ALIVE_PACKET_ID_MSK 0xff
#define FWCMD_H2C_KEEP_ALIVE_PERIOD_SH 16
#define FWCMD_H2C_KEEP_ALIVE_PERIOD_MSK 0xff
#define FWCMD_H2C_KEEP_ALIVE_MAC_ID_SH 24
#define FWCMD_H2C_KEEP_ALIVE_MAC_ID_MSK 0xff
#define FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_DETECT_EN BIT(0)
#define FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN BIT(1)
#define FWCMD_H2C_DISCONNECT_DETECT_DISCONNECT_EN BIT(2)
#define FWCMD_H2C_DISCONNECT_DETECT_MAC_ID_SH 8
#define FWCMD_H2C_DISCONNECT_DETECT_MAC_ID_MSK 0xff
#define FWCMD_H2C_DISCONNECT_DETECT_CHECK_PERIOD_SH 16
#define FWCMD_H2C_DISCONNECT_DETECT_CHECK_PERIOD_MSK 0xff
#define FWCMD_H2C_DISCONNECT_DETECT_TRY_PKT_COUNT_SH 24
#define FWCMD_H2C_DISCONNECT_DETECT_TRY_PKT_COUNT_MSK 0xff
#define FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT_SH 0
#define FWCMD_H2C_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT_MSK 0xff
#define FWCMD_H2C_WOW_GLOBAL_WOW_EN BIT(0)
#define FWCMD_H2C_WOW_GLOBAL_DROP_ALL_PKT BIT(1)
#define FWCMD_H2C_WOW_GLOBAL_RX_PARSE_AFTER_WAKE BIT(2)
#define FWCMD_H2C_WOW_GLOBAL_WAKE_BAR_PULLED BIT(3)
#define FWCMD_H2C_WOW_GLOBAL_MAC_ID_SH 8
#define FWCMD_H2C_WOW_GLOBAL_MAC_ID_MSK 0xff
#define FWCMD_H2C_WOW_GLOBAL_PAIRWISE_SEC_ALGO_SH 16
#define FWCMD_H2C_WOW_GLOBAL_PAIRWISE_SEC_ALGO_MSK 0xff
#define FWCMD_H2C_WOW_GLOBAL_GROUP_SEC_ALGO_SH 24
#define FWCMD_H2C_WOW_GLOBAL_GROUP_SEC_ALGO_MSK 0xff
#define FWCMD_H2C_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT_SH 0
#define FWCMD_H2C_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_GTK_OFLD_GTK_EN BIT(0)
#define FWCMD_H2C_GTK_OFLD_TKIP_EN BIT(1)
#define FWCMD_H2C_GTK_OFLD_IEEE80211W_EN BIT(2)
#define FWCMD_H2C_GTK_OFLD_PAIRWISE_WAKEUP BIT(3)
#define FWCMD_H2C_GTK_OFLD_AOAC_REPORT_ID_SH 8
#define FWCMD_H2C_GTK_OFLD_AOAC_REPORT_ID_MSK 0xff
#define FWCMD_H2C_GTK_OFLD_MAC_ID_SH 16
#define FWCMD_H2C_GTK_OFLD_MAC_ID_MSK 0xff
#define FWCMD_H2C_GTK_OFLD_GTK_RSP_ID_SH 24
#define FWCMD_H2C_GTK_OFLD_GTK_RSP_ID_MSK 0xff
#define FWCMD_H2C_GTK_OFLD_PMF_SA_QUERY_ID_SH 0
#define FWCMD_H2C_GTK_OFLD_PMF_SA_QUERY_ID_MSK 0xff
#define FWCMD_H2C_GTK_OFLD_PMF_BIP_SEC_ALGO_SH 8
#define FWCMD_H2C_GTK_OFLD_PMF_BIP_SEC_ALGO_MSK 0x3
#define FWCMD_H2C_GTK_OFLD_ALGO_AKM_SUIT_SH 10
#define FWCMD_H2C_GTK_OFLD_ALGO_AKM_SUIT_MSK 0xff
#define FWCMD_H2C_GTK_OFLD_GTK_INFO_CONTENT_SH 0
#define FWCMD_H2C_GTK_OFLD_GTK_INFO_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_ARP_OFLD_ARP_EN BIT(0)
#define FWCMD_H2C_ARP_OFLD_ARP_ACTION BIT(1)
#define FWCMD_H2C_ARP_OFLD_MAC_ID_SH 16
#define FWCMD_H2C_ARP_OFLD_MAC_ID_MSK 0xff
#define FWCMD_H2C_ARP_OFLD_ARP_RSP_ID_SH 24
#define FWCMD_H2C_ARP_OFLD_ARP_RSP_ID_MSK 0xff
#define FWCMD_H2C_ARP_OFLD_ARP_INFO_CONTENT_SH 0
#define FWCMD_H2C_ARP_OFLD_ARP_INFO_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_NDP_OFLD_NDP_EN BIT(0)
#define FWCMD_H2C_NDP_OFLD_MAC_ID_SH 16
#define FWCMD_H2C_NDP_OFLD_MAC_ID_MSK 0xff
#define FWCMD_H2C_NDP_OFLD_NA_ID_SH 24
#define FWCMD_H2C_NDP_OFLD_NA_ID_MSK 0xff
#define FWCMD_H2C_NDP_OFLD_NDP_INFO_CONTENT_SH 0
#define FWCMD_H2C_NDP_OFLD_NDP_INFO_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_REALWOW_REALWOW_EN BIT(0)
#define FWCMD_H2C_REALWOW_AUTO_WAKEUP BIT(1)
#define FWCMD_H2C_REALWOW_MAC_ID_SH 24
#define FWCMD_H2C_REALWOW_MAC_ID_MSK 0xff
#define FWCMD_H2C_REALWOW_KEEPALIVE_ID_SH 0
#define FWCMD_H2C_REALWOW_KEEPALIVE_ID_MSK 0xff
#define FWCMD_H2C_REALWOW_WAKEUP_PATTERN_ID_SH 8
#define FWCMD_H2C_REALWOW_WAKEUP_PATTERN_ID_MSK 0xff
#define FWCMD_H2C_REALWOW_ACK_PATTERN_ID_SH 16
#define FWCMD_H2C_REALWOW_ACK_PATTERN_ID_MSK 0xff
#define FWCMD_H2C_REALWOW_REALWOW_INFO_CONTENT_SH 0
#define FWCMD_H2C_REALWOW_REALWOW_INFO_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_NLO_NLO_EN BIT(0)
#define FWCMD_H2C_NLO_NLO_32K_EN BIT(1)
#define FWCMD_H2C_NLO_IGNORE_CIPHER_TYPE BIT(2)
#define FWCMD_H2C_NLO_MAC_ID_SH 24
#define FWCMD_H2C_NLO_MAC_ID_MSK 0xff
#define FWCMD_H2C_NLO_NLO_NETWORKLISTINFO_CONTENT_SH 0
#define FWCMD_H2C_NLO_NLO_NETWORKLISTINFO_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_WAKEUP_CTRL_PATTERN_MATCH_EN BIT(0)
#define FWCMD_H2C_WAKEUP_CTRL_MAGIC_EN BIT(1)
#define FWCMD_H2C_WAKEUP_CTRL_HW_UNICAST_EN BIT(2)
#define FWCMD_H2C_WAKEUP_CTRL_FW_UNICAST_EN BIT(3)
#define FWCMD_H2C_WAKEUP_CTRL_DEAUTH_WAKEUP BIT(4)
#define FWCMD_H2C_WAKEUP_CTRL_REKEY_WAKEUP BIT(5)
#define FWCMD_H2C_WAKEUP_CTRL_EAP_WAKEUP BIT(6)
#define FWCMD_H2C_WAKEUP_CTRL_ALL_DATA_WAKEUP BIT(7)
#define FWCMD_H2C_WAKEUP_CTRL_MAC_ID_SH 24
#define FWCMD_H2C_WAKEUP_CTRL_MAC_ID_MSK 0xff
#define FWCMD_H2C_NEGATIVE_PATTERN_NEGATIVE_PATTERN_EN BIT(0)
#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_COUNT_SH 20
#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_COUNT_MSK 0xf
#define FWCMD_H2C_NEGATIVE_PATTERN_MAC_ID_SH 24
#define FWCMD_H2C_NEGATIVE_PATTERN_MAC_ID_MSK 0xff
#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_CONTENT_SH 0
#define FWCMD_H2C_NEGATIVE_PATTERN_PATTERN_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_DEV2HST_GPIO_DEV2HST_GPIO_EN BIT(0)
#define FWCMD_H2C_DEV2HST_GPIO_DISABLE_INBAND BIT(1)
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_OUTPUT_INPUT BIT(2)
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_ACTIVE BIT(3)
#define FWCMD_H2C_DEV2HST_GPIO_TOGGLE_PULSE BIT(4)
#define FWCMD_H2C_DEV2HST_GPIO_DATA_PIN_WAKEUP BIT(5)
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_NONSTOP BIT(6)
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_TIME_UNIT BIT(7)
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_NUM_SH 8
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_NUM_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_DURATION_SH 16
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_DURATION_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_PERIOD_SH 24
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_PERIOD_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_COUNT_SH 0
#define FWCMD_H2C_DEV2HST_GPIO_GPIO_PULSE_COUNT_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_CUSTOMER_ID_SH 0
#define FWCMD_H2C_DEV2HST_GPIO_CUSTOMER_ID_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_EN BIT(0)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_TOGGLE_PULSE BIT(1)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_NONSTOP BIT(2)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_TIME_UNIT BIT(3)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_SH 0
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_DURATION_SH 8
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_DURATION_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_PERIOD_SH 16
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_PERIOD_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_COUNT_SH 24
#define FWCMD_H2C_DEV2HST_GPIO_RSN_A_PULSE_COUNT_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_EN BIT(0)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_TOGGLE_PULSE BIT(1)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_NONSTOP BIT(2)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_TIME_UNIT BIT(3)
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_SH 0
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_DURATION_SH 8
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_DURATION_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_PERIOD_SH 16
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_PERIOD_MSK 0xff
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_COUNT_SH 24
#define FWCMD_H2C_DEV2HST_GPIO_RSN_B_PULSE_COUNT_MSK 0xff
#define FWCMD_H2C_UPHY_CTRL_DISABLE_UPHY BIT(0)
#define FWCMD_H2C_UPHY_CTRL_HANDSHAKE_MODE_SH 1
#define FWCMD_H2C_UPHY_CTRL_HANDSHAKE_MODE_MSK 0x7
#define FWCMD_H2C_UPHY_CTRL_RISE_HST2DEV_DIS_UPHY BIT(8)
#define FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_UNIT BIT(9)
#define FWCMD_H2C_UPHY_CTRL_PDN_AS_UPHY_DIS BIT(10)
#define FWCMD_H2C_UPHY_CTRL_PDN_TO_ENABLE_UPHY BIT(11)
#define FWCMD_H2C_UPHY_CTRL_HST2DEV_GPIO_NUM_SH 16
#define FWCMD_H2C_UPHY_CTRL_HST2DEV_GPIO_NUM_MSK 0xff
#define FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_COUNT_SH 24
#define FWCMD_H2C_UPHY_CTRL_UPHY_DIS_DELAY_COUNT_MSK 0xff
#define FWCMD_H2C_WOW_CAM_UPD_R_W BIT(0)
#define FWCMD_H2C_WOW_CAM_UPD_IDX_SH 1
#define FWCMD_H2C_WOW_CAM_UPD_IDX_MSK 0x7f
#define FWCMD_H2C_WOW_CAM_UPD_WKFM1_SH 0
#define FWCMD_H2C_WOW_CAM_UPD_WKFM1_MSK 0xffffffff
#define FWCMD_H2C_WOW_CAM_UPD_WKFM2_SH 0
#define FWCMD_H2C_WOW_CAM_UPD_WKFM2_MSK 0xffffffff
#define FWCMD_H2C_WOW_CAM_UPD_WKFM3_SH 0
#define FWCMD_H2C_WOW_CAM_UPD_WKFM3_MSK 0xffffffff
#define FWCMD_H2C_WOW_CAM_UPD_WKFM4_SH 0
#define FWCMD_H2C_WOW_CAM_UPD_WKFM4_MSK 0xffffffff
#define FWCMD_H2C_WOW_CAM_UPD_CRC_SH 0
#define FWCMD_H2C_WOW_CAM_UPD_CRC_MSK 0xffff
#define FWCMD_H2C_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH BIT(22)
#define FWCMD_H2C_WOW_CAM_UPD_SKIP_MAC_HDR BIT(23)
#define FWCMD_H2C_WOW_CAM_UPD_UC BIT(24)
#define FWCMD_H2C_WOW_CAM_UPD_MC BIT(25)
#define FWCMD_H2C_WOW_CAM_UPD_BC BIT(26)
#define FWCMD_H2C_WOW_CAM_UPD_VALID BIT(31)
#define FWCMD_H2C_AOAC_REPORT_REQ_RX_READY BIT(0)
#define FWCMD_H2C_LPS_PARM_MACID_SH 0
#define FWCMD_H2C_LPS_PARM_MACID_MSK 0xff
#define FWCMD_H2C_LPS_PARM_PSMODE_SH 8
#define FWCMD_H2C_LPS_PARM_PSMODE_MSK 0xff
#define FWCMD_H2C_LPS_PARM_RLBM_SH 16
#define FWCMD_H2C_LPS_PARM_RLBM_MSK 0xf
#define FWCMD_H2C_LPS_PARM_SMARTPS_SH 20
#define FWCMD_H2C_LPS_PARM_SMARTPS_MSK 0xf
#define FWCMD_H2C_LPS_PARM_AWAKEINTERVAL_SH 24
#define FWCMD_H2C_LPS_PARM_AWAKEINTERVAL_MSK 0xff
#define FWCMD_H2C_LPS_PARM_VOUAPSD BIT(0)
#define FWCMD_H2C_LPS_PARM_VIUAPSD BIT(1)
#define FWCMD_H2C_LPS_PARM_BEUAPSD BIT(2)
#define FWCMD_H2C_LPS_PARM_BKUAPSD BIT(3)
#define FWCMD_H2C_LPS_PARM_LASTRPWM_SH 8
#define FWCMD_H2C_LPS_PARM_LASTRPWM_MSK 0xff
#define FWCMD_H2C_P2P_ACT_MACID_SH 0
#define FWCMD_H2C_P2P_ACT_MACID_MSK 0xff
#define FWCMD_H2C_P2P_ACT_P2PID_SH 8
#define FWCMD_H2C_P2P_ACT_P2PID_MSK 0xf
#define FWCMD_H2C_P2P_ACT_NOAID_SH 12
#define FWCMD_H2C_P2P_ACT_NOAID_MSK 0xf
#define FWCMD_H2C_P2P_ACT_ACT_SH 16
#define FWCMD_H2C_P2P_ACT_ACT_MSK 0xf
#define FWCMD_H2C_P2P_ACT_TYPE BIT(20)
#define FWCMD_H2C_P2P_ACT_ALL_SLEP BIT(21)
#define FWCMD_H2C_P2P_ACT_SRT_SH 0
#define FWCMD_H2C_P2P_ACT_SRT_MSK 0xffffffff
#define FWCMD_H2C_P2P_ACT_ITVL_SH 0
#define FWCMD_H2C_P2P_ACT_ITVL_MSK 0xffffffff
#define FWCMD_H2C_P2P_ACT_DUR_SH 0
#define FWCMD_H2C_P2P_ACT_DUR_MSK 0xffffffff
#define FWCMD_H2C_P2P_ACT_CNT_SH 0
#define FWCMD_H2C_P2P_ACT_CNT_MSK 0xff
#define FWCMD_H2C_P2P_ACT_CTW_SH 8
#define FWCMD_H2C_P2P_ACT_CTW_MSK 0xffff
#define FWCMD_H2C_P2P_MACID_CTRL_P2PID_SH 0
#define FWCMD_H2C_P2P_MACID_CTRL_P2PID_MSK 0xf
#define FWCMD_H2C_P2P_MACID_CTRL_CTRL_TYPE_SH 4
#define FWCMD_H2C_P2P_MACID_CTRL_CTRL_TYPE_MSK 0xf
#define FWCMD_H2C_P2P_MACID_CTRL_MACID_SRT_SH 8
#define FWCMD_H2C_P2P_MACID_CTRL_MACID_SRT_MSK 0xff
#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_LEN_SH 16
#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_LEN_MSK 0xff
#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_SRT_SH 0
#define FWCMD_H2C_P2P_MACID_CTRL_BMAP_SRT_MSK 0xffffffff
#define FWCMD_H2C_IPS_PARM_MACID_SH 0
#define FWCMD_H2C_IPS_PARM_MACID_MSK 0xff
#define FWCMD_H2C_IPS_PARM_ENABLE BIT(8)
#define FWCMD_H2C_FWHDR_DL_FWHDR_SH 0
#define FWCMD_H2C_FWHDR_DL_FWHDR_MSK 0xffffffff
#define FWCMD_H2C_FWHDR_REDL_FWHDR_SH 0
#define FWCMD_H2C_FWHDR_REDL_FWHDR_MSK 0xffffffff
#define FWCMD_H2C_TWT_ANNOUNCE_UPD_MACID_SH 0
#define FWCMD_H2C_TWT_ANNOUNCE_UPD_MACID_MSK 0xff
#define FWCMD_H2C_TWTINFO_UPD_NEGOTYPE_SH 0
#define FWCMD_H2C_TWTINFO_UPD_NEGOTYPE_MSK 0x3
#define FWCMD_H2C_TWTINFO_UPD_TRIGGER BIT(2)
#define FWCMD_H2C_TWTINFO_UPD_FLOWTYPE BIT(3)
#define FWCMD_H2C_TWTINFO_UPD_IMPT BIT(4)
#define FWCMD_H2C_TWTINFO_UPD_WAKEDURUNIT BIT(5)
#define FWCMD_H2C_TWTINFO_UPD_RSPPM BIT(6)
#define FWCMD_H2C_TWTINFO_UPD_FLOWID_SH 7
#define FWCMD_H2C_TWTINFO_UPD_FLOWID_MSK 0x7
#define FWCMD_H2C_TWTINFO_UPD_PROT BIT(10)
#define FWCMD_H2C_TWTINFO_UPD_ACT_SH 11
#define FWCMD_H2C_TWTINFO_UPD_ACT_MSK 0x7
#define FWCMD_H2C_TWTINFO_UPD_ID_SH 14
#define FWCMD_H2C_TWTINFO_UPD_ID_MSK 0x7
#define FWCMD_H2C_TWTINFO_UPD_BAND BIT(17)
#define FWCMD_H2C_TWTINFO_UPD_PORT_SH 18
#define FWCMD_H2C_TWTINFO_UPD_PORT_MSK 0x7
#define FWCMD_H2C_TWTINFO_UPD_WAKE_MAN_SH 0
#define FWCMD_H2C_TWTINFO_UPD_WAKE_MAN_MSK 0xffff
#define FWCMD_H2C_TWTINFO_UPD_WAKE_EXP_SH 16
#define FWCMD_H2C_TWTINFO_UPD_WAKE_EXP_MSK 0x1f
#define FWCMD_H2C_TWTINFO_UPD_ULFIXMODE_SH 21
#define FWCMD_H2C_TWTINFO_UPD_ULFIXMODE_MSK 0x7
#define FWCMD_H2C_TWTINFO_UPD_DUR_SH 24
#define FWCMD_H2C_TWTINFO_UPD_DUR_MSK 0xff
#define FWCMD_H2C_TWTINFO_UPD_TGT_L_SH 0
#define FWCMD_H2C_TWTINFO_UPD_TGT_L_MSK 0xffffffff
#define FWCMD_H2C_TWTINFO_UPD_TGT_H_SH 0
#define FWCMD_H2C_TWTINFO_UPD_TGT_H_MSK 0xffffffff
#define FWCMD_H2C_TWT_STANSP_UPD_MACID_SH 0
#define FWCMD_H2C_TWT_STANSP_UPD_MACID_MSK 0xff
#define FWCMD_H2C_TWT_STANSP_UPD_ID_SH 8
#define FWCMD_H2C_TWT_STANSP_UPD_ID_MSK 0x7
#define FWCMD_H2C_TWT_STANSP_UPD_ACT_SH 11
#define FWCMD_H2C_TWT_STANSP_UPD_ACT_MSK 0xf
#define FWCMD_H2C_TBLUD_R_W BIT(0)
#define FWCMD_H2C_TBLUD_MACID_GROUP_SH 1
#define FWCMD_H2C_TBLUD_MACID_GROUP_MSK 0x7f
#define FWCMD_H2C_TBLUD_OFFSET_SH 8
#define FWCMD_H2C_TBLUD_OFFSET_MSK 0x1f
#define FWCMD_H2C_TBLUD_LENGTH_SH 13
#define FWCMD_H2C_TBLUD_LENGTH_MSK 0x3ff
#define FWCMD_H2C_TBLUD_TYPE BIT(23)
#define FWCMD_H2C_TBLUD_TABLE_CLASS_SH 24
#define FWCMD_H2C_TBLUD_TABLE_CLASS_MSK 0xff
#define FWCMD_H2C_DCTLINFO_UD_MACID_SH 0
#define FWCMD_H2C_DCTLINFO_UD_MACID_MSK 0x7f
#define FWCMD_H2C_DCTLINFO_UD_OP BIT(7)
#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_VAL_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_VAL_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_VAL_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_VAL_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_VAL_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_VAL_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_VAL_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_VAL_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_MSK_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL0_MSK_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_MSK_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL1_MSK_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_MSK_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL2_MSK_MSK 0xffffffff
#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_MSK_SH 0
#define FWCMD_H2C_DCTLINFO_UD_DCTRL3_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_MACID_SH 0
#define FWCMD_H2C_CCTLINFO_UD_MACID_MSK 0x7f
#define FWCMD_H2C_CCTLINFO_UD_OP BIT(7)
#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_VAL_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_VAL_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL0_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL1_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL2_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL3_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL4_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL5_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL6_MSK_MSK 0xffffffff
#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_MSK_SH 0
#define FWCMD_H2C_CCTLINFO_UD_CCTRL7_MSK_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D0_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D0_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D1_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D1_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D2_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D2_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D3_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D3_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D4_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D4_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D5_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D5_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D6_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D6_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D7_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D7_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D8_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D8_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D9_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D9_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D10_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D10_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D11_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D11_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D12_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D12_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D13_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D13_MSK 0xffffffff
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D14_SH 0
#define FWCMD_H2C_SHCUT_UPDATE_SHCUT_UPDATE_D14_MSK 0xffffffff
#define FWCMD_H2C_BCN_UPD_PORT_SH 0
#define FWCMD_H2C_BCN_UPD_PORT_MSK 0xff
#define FWCMD_H2C_BCN_UPD_MBSSID_SH 8
#define FWCMD_H2C_BCN_UPD_MBSSID_MSK 0xff
#define FWCMD_H2C_BCN_UPD_BAND_SH 16
#define FWCMD_H2C_BCN_UPD_BAND_MSK 0xff
#define FWCMD_H2C_BCN_UPD_GRP_IE_OFST_SH 24
#define FWCMD_H2C_BCN_UPD_GRP_IE_OFST_MSK 0xff
#define FWCMD_H2C_BCN_UPD_MACID_SH 0
#define FWCMD_H2C_BCN_UPD_MACID_MSK 0xff
#define FWCMD_H2C_BCN_UPD_SSN_SEL_SH 8
#define FWCMD_H2C_BCN_UPD_SSN_SEL_MSK 0x3
#define FWCMD_H2C_BCN_UPD_SSN_MODE_SH 10
#define FWCMD_H2C_BCN_UPD_SSN_MODE_MSK 0x3
#define FWCMD_H2C_BCN_UPD_RATE_SH 12
#define FWCMD_H2C_BCN_UPD_RATE_MSK 0x1ff
#define FWCMD_H2C_BCN_UPD_TXPWR_SH 21
#define FWCMD_H2C_BCN_UPD_TXPWR_MSK 0x7
#define FWCMD_H2C_BCN_UPD_TXINFO_CTRL_EN BIT(0)
#define FWCMD_H2C_BCN_UPD_NTX_PATH_EN_SH 1
#define FWCMD_H2C_BCN_UPD_NTX_PATH_EN_MSK 0xf
#define FWCMD_H2C_BCN_UPD_PATH_MAP_A_SH 5
#define FWCMD_H2C_BCN_UPD_PATH_MAP_A_MSK 0x3
#define FWCMD_H2C_BCN_UPD_PATH_MAP_B_SH 7
#define FWCMD_H2C_BCN_UPD_PATH_MAP_B_MSK 0x3
#define FWCMD_H2C_BCN_UPD_PATH_MAP_C_SH 9
#define FWCMD_H2C_BCN_UPD_PATH_MAP_C_MSK 0x3
#define FWCMD_H2C_BCN_UPD_PATH_MAP_D_SH 11
#define FWCMD_H2C_BCN_UPD_PATH_MAP_D_MSK 0x3
#define FWCMD_H2C_BCN_UPD_ANTSEL_A BIT(13)
#define FWCMD_H2C_BCN_UPD_ANTSEL_B BIT(14)
#define FWCMD_H2C_BCN_UPD_ANTSEL_C BIT(15)
#define FWCMD_H2C_BCN_UPD_ANTSEL_D BIT(16)
#define FWCMD_H2C_BCN_UPD_CSA_OFST_SH 17
#define FWCMD_H2C_BCN_UPD_CSA_OFST_MSK 0x7fff
#define FWCMD_H2C_SS_ULSTA_UPD_MODE_SH 0
#define FWCMD_H2C_SS_ULSTA_UPD_MODE_MSK 0xff
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U0_SH 0
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U0_MSK 0xff
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U1_SH 8
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U1_MSK 0xff
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U2_SH 16
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U2_MSK 0xff
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U3_SH 24
#define FWCMD_H2C_SS_ULSTA_UPD_MACID_U3_MSK 0xff
#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U0_SH 0
#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U0_MSK 0xffff
#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U1_SH 16
#define FWCMD_H2C_SS_ULSTA_UPD_BSR_LEN_U1_MSK 0xffff
#define FWCMD_H2C_F2PDBG_SET_SET_TXDBG BIT(0)
#define FWCMD_H2C_F2PDBG_SET_TXDBG_EN BIT(1)
#define FWCMD_H2C_F2PDBG_SET_SET_TPPKTSIZE BIT(2)
#define FWCMD_H2C_F2PDBG_SET_PKT_SIZE_SH 3
#define FWCMD_H2C_F2PDBG_SET_PKT_SIZE_MSK 0xffff
#define FWCMD_H2C_WLANINFO_GET_INFO_SEL_SH 0
#define FWCMD_H2C_WLANINFO_GET_INFO_SEL_MSK 0xf
#define FWCMD_H2C_WLANINFO_GET_ARGV0_SH 8
#define FWCMD_H2C_WLANINFO_GET_ARGV0_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV1_SH 16
#define FWCMD_H2C_WLANINFO_GET_ARGV1_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV2_SH 24
#define FWCMD_H2C_WLANINFO_GET_ARGV2_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV3_SH 0
#define FWCMD_H2C_WLANINFO_GET_ARGV3_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV4_SH 8
#define FWCMD_H2C_WLANINFO_GET_ARGV4_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV5_SH 16
#define FWCMD_H2C_WLANINFO_GET_ARGV5_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV6_SH 24
#define FWCMD_H2C_WLANINFO_GET_ARGV6_MSK 0xff
#define FWCMD_H2C_WLANINFO_GET_ARGV7_SH 0
#define FWCMD_H2C_WLANINFO_GET_ARGV7_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_R_W BIT(0)
#define FWCMD_H2C_ADDRCAM_INFO_IDX_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_IDX_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_OFFSET_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_OFFSET_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_LEN_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_LEN_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_VALID BIT(0)
#define FWCMD_H2C_ADDRCAM_INFO_NET_TYPE_SH 1
#define FWCMD_H2C_ADDRCAM_INFO_NET_TYPE_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_BCN_HIT_COND_SH 3
#define FWCMD_H2C_ADDRCAM_INFO_BCN_HIT_COND_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_HIT_RULE_SH 5
#define FWCMD_H2C_ADDRCAM_INFO_HIT_RULE_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_BB_SEL BIT(7)
#define FWCMD_H2C_ADDRCAM_INFO_ADDR_MASK_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_ADDR_MASK_MSK 0x3f
#define FWCMD_H2C_ADDRCAM_INFO_MASK_SEL_SH 14
#define FWCMD_H2C_ADDRCAM_INFO_MASK_SEL_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SMA_HASH_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_SMA_HASH_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA_HASH_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_TMA_HASH_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_BSSID_CAM_IDX_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_BSSID_CAM_IDX_MSK 0x3f
#define FWCMD_H2C_ADDRCAM_INFO_IS_MUL_ENT BIT(8)
#define FWCMD_H2C_ADDRCAM_INFO_SMA0_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_SMA0_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SMA1_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_SMA1_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SMA2_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_SMA2_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SMA3_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_SMA3_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SMA4_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_SMA4_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SMA5_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_SMA5_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA0_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_TMA0_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA1_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_TMA1_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA2_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_TMA2_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA3_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_TMA3_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA4_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_TMA4_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_TMA5_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_TMA5_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_MACID_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_MACID_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_PORT_INT_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_PORT_INT_MSK 0x7
#define FWCMD_H2C_ADDRCAM_INFO_TSF_SYNC_SH 11
#define FWCMD_H2C_ADDRCAM_INFO_TSF_SYNC_MSK 0x7
#define FWCMD_H2C_ADDRCAM_INFO_TF_TRS BIT(14)
#define FWCMD_H2C_ADDRCAM_INFO_LSIG_TXOP BIT(15)
#define FWCMD_H2C_ADDRCAM_INFO_TGT_IND_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_TGT_IND_MSK 0x7
#define FWCMD_H2C_ADDRCAM_INFO_FRM_TGT_IND_SH 27
#define FWCMD_H2C_ADDRCAM_INFO_FRM_TGT_IND_MSK 0x7
#define FWCMD_H2C_ADDRCAM_INFO_AID12_0_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_AID12_0_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_AID12_1_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_AID12_1_MSK 0xf
#define FWCMD_H2C_ADDRCAM_INFO_WOL_PATTERN BIT(12)
#define FWCMD_H2C_ADDRCAM_INFO_WOL_UC BIT(13)
#define FWCMD_H2C_ADDRCAM_INFO_WOL_MAGIC BIT(14)
#define FWCMD_H2C_ADDRCAM_INFO_WAPI BIT(15)
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID_SH 18
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID_SH 20
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID_SH 22
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID_SH 26
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID_SH 28
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID_SH 30
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID_MSK 0x3
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_B_IDX_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_B_IDX_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_B_OFFSET_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_B_OFFSET_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_B_LEN_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_B_LEN_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_B_VALID BIT(0)
#define FWCMD_H2C_ADDRCAM_INFO_B_BB_SEL BIT(1)
#define FWCMD_H2C_ADDRCAM_INFO_BSS_COLOR_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_BSS_COLOR_MSK 0x7f
#define FWCMD_H2C_ADDRCAM_INFO_BSSID0_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_BSSID0_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_BSSID1_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_BSSID1_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_BSSID2_SH 0
#define FWCMD_H2C_ADDRCAM_INFO_BSSID2_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_BSSID3_SH 8
#define FWCMD_H2C_ADDRCAM_INFO_BSSID3_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_BSSID4_SH 16
#define FWCMD_H2C_ADDRCAM_INFO_BSSID4_MSK 0xff
#define FWCMD_H2C_ADDRCAM_INFO_BSSID5_SH 24
#define FWCMD_H2C_ADDRCAM_INFO_BSSID5_MSK 0xff
#define FWCMD_H2C_JOININFO_MACID_SH 0
#define FWCMD_H2C_JOININFO_MACID_MSK 0xff
#define FWCMD_H2C_JOININFO_OPMODE BIT(8)
#define FWCMD_H2C_JOININFO_BAND BIT(9)
#define FWCMD_H2C_JOININFO_WMM_SH 10
#define FWCMD_H2C_JOININFO_WMM_MSK 0x3
#define FWCMD_H2C_JOININFO_TRIGGER BIT(12)
#define FWCMD_H2C_JOININFO_ISHESTA BIT(13)
#define FWCMD_H2C_JOININFO_DL_BW_SH 14
#define FWCMD_H2C_JOININFO_DL_BW_MSK 0x3
#define FWCMD_H2C_JOININFO_TF_MAC_PADDING_SH 16
#define FWCMD_H2C_JOININFO_TF_MAC_PADDING_MSK 0x3
#define FWCMD_H2C_JOININFO_DL_T_PE_SH 18
#define FWCMD_H2C_JOININFO_DL_T_PE_MSK 0x7
#define FWCMD_H2C_JOININFO_PORT_ID_SH 21
#define FWCMD_H2C_JOININFO_PORT_ID_MSK 0x7
#define FWCMD_H2C_JOININFO_NET_TYPE_SH 24
#define FWCMD_H2C_JOININFO_NET_TYPE_MSK 0x3
#define FWCMD_H2C_JOININFO_WIFI_ROLE_SH 26
#define FWCMD_H2C_JOININFO_WIFI_ROLE_MSK 0xf
#define FWCMD_H2C_JOININFO_SELF_ROLE_SH 30
#define FWCMD_H2C_JOININFO_SELF_ROLE_MSK 0x3
#define FWCMD_H2C_DL_GRP_UPD_GRP_VALID BIT(0)
#define FWCMD_H2C_DL_GRP_UPD_GRP_ID_SH 1
#define FWCMD_H2C_DL_GRP_UPD_GRP_ID_MSK 0x1f
#define FWCMD_H2C_DL_GRP_UPD_IS_HWGRP BIT(6)
#define FWCMD_H2C_DL_GRP_UPD_MACID_U0_SH 8
#define FWCMD_H2C_DL_GRP_UPD_MACID_U0_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U1_SH 16
#define FWCMD_H2C_DL_GRP_UPD_MACID_U1_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U2_SH 24
#define FWCMD_H2C_DL_GRP_UPD_MACID_U2_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U3_SH 0
#define FWCMD_H2C_DL_GRP_UPD_MACID_U3_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U4_SH 8
#define FWCMD_H2C_DL_GRP_UPD_MACID_U4_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U5_SH 16
#define FWCMD_H2C_DL_GRP_UPD_MACID_U5_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U6_SH 24
#define FWCMD_H2C_DL_GRP_UPD_MACID_U6_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_MACID_U7_SH 0
#define FWCMD_H2C_DL_GRP_UPD_MACID_U7_MSK 0xff
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U0_SH 8
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U0_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U1_SH 12
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U1_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U2_SH 16
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U2_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U3_SH 20
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U3_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U4_SH 24
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U4_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U5_SH 28
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U5_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U6_SH 0
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U6_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U7_SH 4
#define FWCMD_H2C_DL_GRP_UPD_AC_BITMAP_U7_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_NEXT_PROTECTTYPE_SH 8
#define FWCMD_H2C_DL_GRP_UPD_NEXT_PROTECTTYPE_MSK 0xf
#define FWCMD_H2C_DL_GRP_UPD_NEXT_RSPTYPE_SH 12
#define FWCMD_H2C_DL_GRP_UPD_NEXT_RSPTYPE_MSK 0xf
#define FWCMD_H2C_UL_GRP_UPD_MACID_U0_SH 0
#define FWCMD_H2C_UL_GRP_UPD_MACID_U0_MSK 0xff
#define FWCMD_H2C_UL_GRP_UPD_MACID_U1_SH 8
#define FWCMD_H2C_UL_GRP_UPD_MACID_U1_MSK 0xff
#define FWCMD_H2C_UL_GRP_UPD_GRP_BITMAP_SH 16
#define FWCMD_H2C_UL_GRP_UPD_GRP_BITMAP_MSK 0xffff
#define FWCMD_H2C_MU_STA_UPD_MACID_SH 0
#define FWCMD_H2C_MU_STA_UPD_MACID_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_MU_IDX_SH 8
#define FWCMD_H2C_MU_STA_UPD_MU_IDX_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_0_SH 16
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_0_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_1_SH 24
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_1_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_2_SH 0
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_2_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_3_SH 8
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_3_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_4_SH 16
#define FWCMD_H2C_MU_STA_UPD_PROT_RSP_TYPE_4_MSK 0xff
#define FWCMD_H2C_MU_STA_UPD_MUGRP_BITMAP_SH 24
#define FWCMD_H2C_MU_STA_UPD_MUGRP_BITMAP_MSK 0x1f
#define FWCMD_H2C_MU_STA_UPD_DIS_256Q BIT(29)
#define FWCMD_H2C_MU_STA_UPD_DIS_1024Q BIT(30)
#define FWCMD_H2C_FWROLE_MAINTAIN_MACID_SH 0
#define FWCMD_H2C_FWROLE_MAINTAIN_MACID_MSK 0xff
#define FWCMD_H2C_FWROLE_MAINTAIN_SELF_ROLE_SH 8
#define FWCMD_H2C_FWROLE_MAINTAIN_SELF_ROLE_MSK 0x3
#define FWCMD_H2C_FWROLE_MAINTAIN_UPD_MODE_SH 10
#define FWCMD_H2C_FWROLE_MAINTAIN_UPD_MODE_MSK 0x7
#define FWCMD_H2C_FWROLE_MAINTAIN_WIFI_ROLE_SH 13
#define FWCMD_H2C_FWROLE_MAINTAIN_WIFI_ROLE_MSK 0xf
#define FWCMD_H2C_NOTIFY_DBCC_EN BIT(0)
#define FWCMD_H2C_DUMP_EFUSE_DUMP_SIZE_SH 0
#define FWCMD_H2C_DUMP_EFUSE_DUMP_SIZE_MSK 0x7ff
#define FWCMD_H2C_DUMP_EFUSE_IS_HIDDEN BIT(11)
#define FWCMD_H2C_PACKET_OFLD_PKT_IDX_SH 0
#define FWCMD_H2C_PACKET_OFLD_PKT_IDX_MSK 0xff
#define FWCMD_H2C_PACKET_OFLD_PKT_OP_SH 8
#define FWCMD_H2C_PACKET_OFLD_PKT_OP_MSK 0x7
#define FWCMD_H2C_PACKET_OFLD_PKT_LENGTH_SH 16
#define FWCMD_H2C_PACKET_OFLD_PKT_LENGTH_MSK 0xffff
#define FWCMD_H2C_PACKET_OFLD_PKT_START_SH 0
#define FWCMD_H2C_PACKET_OFLD_PKT_START_MSK 0xffffffff
#define FWCMD_H2C_READ_OFLD_VALUE_LEN_SH 0
#define FWCMD_H2C_READ_OFLD_VALUE_LEN_MSK 0x7ff
#define FWCMD_H2C_READ_OFLD_LS BIT(15)
#define FWCMD_H2C_READ_OFLD_OFLD_ID_SH 16
#define FWCMD_H2C_READ_OFLD_OFLD_ID_MSK 0xff
#define FWCMD_H2C_READ_OFLD_ENTRY_NUM_SH 24
#define FWCMD_H2C_READ_OFLD_ENTRY_NUM_MSK 0xff
#define FWCMD_H2C_READ_OFLD_OFFSET_SH 0
#define FWCMD_H2C_READ_OFLD_OFFSET_MSK 0xffff
#define FWCMD_H2C_WRITE_OFLD_VALUE_LEN_SH 0
#define FWCMD_H2C_WRITE_OFLD_VALUE_LEN_MSK 0x7ff
#define FWCMD_H2C_WRITE_OFLD_POLLING BIT(13)
#define FWCMD_H2C_WRITE_OFLD_MASK_EN BIT(14)
#define FWCMD_H2C_WRITE_OFLD_LS BIT(15)
#define FWCMD_H2C_WRITE_OFLD_OFLD_ID_SH 16
#define FWCMD_H2C_WRITE_OFLD_OFLD_ID_MSK 0xff
#define FWCMD_H2C_WRITE_OFLD_ENTRY_NUM_SH 24
#define FWCMD_H2C_WRITE_OFLD_ENTRY_NUM_MSK 0xff
#define FWCMD_H2C_WRITE_OFLD_OFFSET_SH 0
#define FWCMD_H2C_WRITE_OFLD_OFFSET_MSK 0xffff
#define FWCMD_H2C_WRITE_OFLD_START_SH 0
#define FWCMD_H2C_WRITE_OFLD_START_MSK 0xffffffff
#define FWCMD_H2C_CONF_OFLD_PATTERN_COUNT_SH 0
#define FWCMD_H2C_CONF_OFLD_PATTERN_COUNT_MSK 0xffff
#define FWCMD_H2C_CONF_OFLD_START_SH 0
#define FWCMD_H2C_CONF_OFLD_START_MSK 0xffffffff
#define FWCMD_H2C_TRX_INIT_TRX_MODE_SH 0
#define FWCMD_H2C_TRX_INIT_TRX_MODE_MSK 0xff
#define FWCMD_H2C_TRX_INIT_QTA_MODE_SH 8
#define FWCMD_H2C_TRX_INIT_QTA_MODE_MSK 0x1ff
#define FWCMD_H2C_INTF_INIT_TXBD_TRUNC_MODE BIT(0)
#define FWCMD_H2C_INTF_INIT_RXBD_TRUNC_MODE BIT(1)
#define FWCMD_H2C_INTF_INIT_RXBD_MODE BIT(2)
#define FWCMD_H2C_INTF_INIT_TAG_MODE BIT(3)
#define FWCMD_H2C_INTF_INIT_TX_BURST_MODE_SH 4
#define FWCMD_H2C_INTF_INIT_TX_BURST_MODE_MSK 0xf
#define FWCMD_H2C_INTF_INIT_RX_BURST_MODE_SH 8
#define FWCMD_H2C_INTF_INIT_RX_BURST_MODE_MSK 0xf
#define FWCMD_H2C_INTF_INIT_WD_DMA_IDLE_INTVL_SH 12
#define FWCMD_H2C_INTF_INIT_WD_DMA_IDLE_INTVL_MSK 0xf
#define FWCMD_H2C_INTF_INIT_WD_DMA_ACT_INTVL_SH 16
#define FWCMD_H2C_INTF_INIT_WD_DMA_ACT_INTVL_MSK 0xf
#define FWCMD_H2C_INTF_INIT_SKIP_ALL_SH 24
#define FWCMD_H2C_INTF_INIT_SKIP_ALL_MSK 0xff
#define FWCMD_H2C_INTF_INIT_RX_SEP_APPEND_LEN_SH 0
#define FWCMD_H2C_INTF_INIT_RX_SEP_APPEND_LEN_MSK 0xffff
#define FWCMD_H2C_INTF_INIT_TXBD_BUF_SH 16
#define FWCMD_H2C_INTF_INIT_TXBD_BUF_MSK 0xff
#define FWCMD_H2C_INTF_INIT_RXBD_BUF_SH 24
#define FWCMD_H2C_INTF_INIT_RXBD_BUF_MSK 0xff
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_1_SH 0
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_1_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_2_SH 0
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_2_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_3_SH 0
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_3_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_4_SH 0
#define FWCMD_H2C_MACID_PAUSE_PAUSE_GRP_4_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_1_SH 0
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_1_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_2_SH 0
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_2_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_3_SH 0
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_3_MSK 0xffffffff
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_4_SH 0
#define FWCMD_H2C_MACID_PAUSE_MASK_GRP_4_MSK 0xffffffff
#define FWCMD_H2C_RX_FWD_TYPE_SH 0
#define FWCMD_H2C_RX_FWD_TYPE_MSK 0xff
#define FWCMD_H2C_RX_FWD_FRAME_SH 8
#define FWCMD_H2C_RX_FWD_FRAME_MSK 0xff
#define FWCMD_H2C_RX_FWD_FWD_TG_SH 16
#define FWCMD_H2C_RX_FWD_FWD_TG_MSK 0xff
#define FWCMD_H2C_RX_FWD_AF_UD_INDEX_SH 0
#define FWCMD_H2C_RX_FWD_AF_UD_INDEX_MSK 0xff
#define FWCMD_H2C_RX_FWD_AF_UD_FWD_TG_SH 8
#define FWCMD_H2C_RX_FWD_AF_UD_FWD_TG_MSK 0xff
#define FWCMD_H2C_RX_FWD_AF_UD_CATEGORY_SH 16
#define FWCMD_H2C_RX_FWD_AF_UD_CATEGORY_MSK 0xff
#define FWCMD_H2C_RX_FWD_AF_UD_ACTION_FIELD_SH 24
#define FWCMD_H2C_RX_FWD_AF_UD_ACTION_FIELD_MSK 0xff
#define FWCMD_H2C_RX_FWD_PM_CAM_VALID BIT(0)
#define FWCMD_H2C_RX_FWD_PM_CAM_TYPE_SH 1
#define FWCMD_H2C_RX_FWD_PM_CAM_TYPE_MSK 0x3
#define FWCMD_H2C_RX_FWD_PM_CAM_SUBTYPE_SH 3
#define FWCMD_H2C_RX_FWD_PM_CAM_SUBTYPE_MSK 0xf
#define FWCMD_H2C_RX_FWD_PM_CAM_SKIP_MAC_IV_HDR BIT(7)
#define FWCMD_H2C_RX_FWD_PM_CAM_TARGET_IND_SH 8
#define FWCMD_H2C_RX_FWD_PM_CAM_TARGET_IND_MSK 0x7
#define FWCMD_H2C_RX_FWD_PM_CAM_INDEX_SH 12
#define FWCMD_H2C_RX_FWD_PM_CAM_INDEX_MSK 0xf
#define FWCMD_H2C_RX_FWD_PM_CAM_CRC16_SH 16
#define FWCMD_H2C_RX_FWD_PM_CAM_CRC16_MSK 0xffff
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK0_SH 0
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK0_MSK 0xffffffff
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK1_SH 0
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK1_MSK 0xffffffff
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK2_SH 0
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK2_MSK 0xffffffff
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK3_SH 0
#define FWCMD_H2C_RX_FWD_PM_CAM_PLD_MASK3_MSK 0xffffffff
#define FWCMD_H2C_EN_MAC_HDR_CONV_ENABLE BIT(0)
#define FWCMD_H2C_SET_HWSEQ_REG_REG_IDX_SH 0
#define FWCMD_H2C_SET_HWSEQ_REG_REG_IDX_MSK 0x3
#define FWCMD_H2C_SET_HWSEQ_REG_SEQ_VAL_SH 2
#define FWCMD_H2C_SET_HWSEQ_REG_SEQ_VAL_MSK 0xfff
#define FWCMD_H2C_HWAMSDU_REG_ENABLE BIT(0)
#define FWCMD_H2C_HWAMSDU_REG_MAX_AMSDU_SUBFRAME_NUMBER_SH 1
#define FWCMD_H2C_HWAMSDU_REG_MAX_AMSDU_SUBFRAME_NUMBER_MSK 0x3
#define FWCMD_H2C_HWAMSDU_REG_ENABLE_SINGLE_AMSDU BIT(3)
#define FWCMD_H2C_HWAMSDU_REG_ENABLE_LAST_AMSDU_PADDING BIT(4)
#define FWCMD_H2C_AMSDU_CUT_REG_ENABLE BIT(0)
#define FWCMD_H2C_AMSDU_CUT_REG_LOW_THRESHOLD_SH 1
#define FWCMD_H2C_AMSDU_CUT_REG_LOW_THRESHOLD_MSK 0x1ff
#define FWCMD_H2C_AMSDU_CUT_REG_HIGH_THRESHOLD_SH 10
#define FWCMD_H2C_AMSDU_CUT_REG_HIGH_THRESHOLD_MSK 0xffff
#define FWCMD_H2C_AMSDU_CUT_REG_EXTRA_SHIFT_SH 26
#define FWCMD_H2C_AMSDU_CUT_REG_EXTRA_SHIFT_MSK 0x3
#define FWCMD_H2C_TCPIP_CHKSUM_OFFLOAD_REG_ENABLE_TX_TCPIP_CHECKSUM_OFFLOAD BIT(0)
#define FWCMD_H2C_TCPIP_CHKSUM_OFFLOAD_REG_ENABLE_RX_TCPIP_CHECKSUM_OFFLOAD BIT(1)
#define FWCMD_H2C_USR_EDCA_PARAM_SEL_SH 0
#define FWCMD_H2C_USR_EDCA_PARAM_SEL_MSK 0x3
#define FWCMD_H2C_USR_EDCA_ENABLE BIT(2)
#define FWCMD_H2C_USR_EDCA_BAND BIT(3)
#define FWCMD_H2C_USR_EDCA_WMM BIT(4)
#define FWCMD_H2C_USR_EDCA_AC_SH 5
#define FWCMD_H2C_USR_EDCA_AC_MSK 0x3
#define FWCMD_H2C_USR_EDCA_AGGRESSIVE_SH 0
#define FWCMD_H2C_USR_EDCA_AGGRESSIVE_MSK 0xffffffff
#define FWCMD_H2C_USR_EDCA_MODERATE_SH 0
#define FWCMD_H2C_USR_EDCA_MODERATE_MSK 0xffffffff
#define FWCMD_H2C_TSF32_TOGL_BAND BIT(0)
#define FWCMD_H2C_TSF32_TOGL_EN BIT(1)
#define FWCMD_H2C_TSF32_TOGL_PORT_SH 2
#define FWCMD_H2C_TSF32_TOGL_PORT_MSK 0x7
#define FWCMD_H2C_TSF32_TOGL_EARLY_SH 16
#define FWCMD_H2C_TSF32_TOGL_EARLY_MSK 0xffff
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D0_SH 0
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D0_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D1_SH 0
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D1_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D2_SH 0
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D2_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D3_SH 0
#define FWCMD_H2C_CMD_OFLD_REG_CMD_OFLD_D3_MSK 0xffffffff
#define FWCMD_H2C_USR_TX_RPT_MODE_SH 0
#define FWCMD_H2C_USR_TX_RPT_MODE_MSK 0x7
#define FWCMD_H2C_USR_TX_RPT_RTP_START BIT(3)
#define FWCMD_H2C_USR_TX_RPT_MACID_SH 0
#define FWCMD_H2C_USR_TX_RPT_MACID_MSK 0xff
#define FWCMD_H2C_USR_TX_RPT_AC_SH 8
#define FWCMD_H2C_USR_TX_RPT_AC_MSK 0x3
#define FWCMD_H2C_USR_TX_RPT_BAND BIT(10)
#define FWCMD_H2C_USR_TX_RPT_PORT_SH 11
#define FWCMD_H2C_USR_TX_RPT_PORT_MSK 0x7
#define FWCMD_H2C_USR_TX_RPT_RPT_PERIOD_SH 0
#define FWCMD_H2C_USR_TX_RPT_RPT_PERIOD_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D0_SH 0
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D0_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D1_SH 0
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D1_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D2_SH 0
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D2_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D3_SH 0
#define FWCMD_H2C_CMD_OFLD_PKT_CMD_OFLD_D3_MSK 0xffffffff
#define FWCMD_H2C_OFLD_CFG_MODE_SH 0
#define FWCMD_H2C_OFLD_CFG_MODE_MSK 0x7
#define FWCMD_H2C_OFLD_CFG_USR_TXOP_BE BIT(3)
#define FWCMD_H2C_OFLD_CFG_USR_TXOP_BE_VAL_SH 0
#define FWCMD_H2C_OFLD_CFG_USR_TXOP_BE_VAL_MSK 0xffff
#define FWCMD_H2C_H2C_AGG_PLD_SH 0
#define FWCMD_H2C_H2C_AGG_PLD_MSK 0xffffffff
#define FWCMD_H2C_ADD_SCANOFLD_CH_NUM_OF_CH_SH 0
#define FWCMD_H2C_ADD_SCANOFLD_CH_NUM_OF_CH_MSK 0xff
#define FWCMD_H2C_SCANOFLD_MACID_SH 0
#define FWCMD_H2C_SCANOFLD_MACID_MSK 0xff
#define FWCMD_H2C_SCANOFLD_NORM_CY_SH 8
#define FWCMD_H2C_SCANOFLD_NORM_CY_MSK 0xff
#define FWCMD_H2C_SCANOFLD_PORT_ID_SH 16
#define FWCMD_H2C_SCANOFLD_PORT_ID_MSK 0x7
#define FWCMD_H2C_SCANOFLD_BAND BIT(19)
#define FWCMD_H2C_SCANOFLD_OPERATION_SH 20
#define FWCMD_H2C_SCANOFLD_OPERATION_MSK 0x3
#define FWCMD_H2C_SCANOFLD_C2H_NOTIFY_END BIT(0)
#define FWCMD_H2C_SCANOFLD_TARGET_CH_MODE BIT(1)
#define FWCMD_H2C_SCANOFLD_START_MODE BIT(2)
#define FWCMD_H2C_SCANOFLD_SCAN_TYPE_SH 3
#define FWCMD_H2C_SCANOFLD_SCAN_TYPE_MSK 0x3
#define FWCMD_H2C_SCANOFLD_TARGET_CH_BW_SH 5
#define FWCMD_H2C_SCANOFLD_TARGET_CH_BW_MSK 0x7
#define FWCMD_H2C_SCANOFLD_TARGET_PRI_CH_SH 8
#define FWCMD_H2C_SCANOFLD_TARGET_PRI_CH_MSK 0xff
#define FWCMD_H2C_SCANOFLD_TARGET_CENTRAL_CH_SH 16
#define FWCMD_H2C_SCANOFLD_TARGET_CENTRAL_CH_MSK 0xff
#define FWCMD_H2C_SCANOFLD_PROBE_REQ_PKT_ID_SH 24
#define FWCMD_H2C_SCANOFLD_PROBE_REQ_PKT_ID_MSK 0xff
#define FWCMD_H2C_SCANOFLD_NORM_PD_SH 0
#define FWCMD_H2C_SCANOFLD_NORM_PD_MSK 0x1ffff
#define FWCMD_H2C_SCANOFLD_SLOW_PD_SH 17
#define FWCMD_H2C_SCANOFLD_SLOW_PD_MSK 0x7fff
#define FWCMD_H2C_SCANOFLD_TSF_HIGH_SH 0
#define FWCMD_H2C_SCANOFLD_TSF_HIGH_MSK 0xffffffff
#define FWCMD_H2C_SCANOFLD_TSF_LOW_SH 0
#define FWCMD_H2C_SCANOFLD_TSF_LOW_MSK 0xffffffff
#define FWCMD_H2C_DISABLE_RF_FUNC_SH 0
#define FWCMD_H2C_DISABLE_RF_FUNC_MSK 0xf
#define FWCMD_H2C_DISABLE_RF_NET_TYPE_SH 4
#define FWCMD_H2C_DISABLE_RF_NET_TYPE_MSK 0x3
#define FWCMD_H2C_TX_DUTY_PAUSE_INTVL_SH 0
#define FWCMD_H2C_TX_DUTY_PAUSE_INTVL_MSK 0xffff
#define FWCMD_H2C_TX_DUTY_TX_INTVL_SH 16
#define FWCMD_H2C_TX_DUTY_TX_INTVL_MSK 0xffff
#define FWCMD_H2C_TX_DUTY_STOP BIT(0)
#define FWCMD_H2C_SECCAM_INFO_IDX_SH 0
#define FWCMD_H2C_SECCAM_INFO_IDX_MSK 0xff
#define FWCMD_H2C_SECCAM_INFO_OFFSET_SH 8
#define FWCMD_H2C_SECCAM_INFO_OFFSET_MSK 0xff
#define FWCMD_H2C_SECCAM_INFO_LEN_SH 16
#define FWCMD_H2C_SECCAM_INFO_LEN_MSK 0xff
#define FWCMD_H2C_SECCAM_INFO_TYPE_SH 0
#define FWCMD_H2C_SECCAM_INFO_TYPE_MSK 0xf
#define FWCMD_H2C_SECCAM_INFO_EXT_KEY BIT(4)
#define FWCMD_H2C_SECCAM_INFO_SPP_MODE BIT(5)
#define FWCMD_H2C_SECCAM_INFO_KEY_0_SH 0
#define FWCMD_H2C_SECCAM_INFO_KEY_0_MSK 0xffffffff
#define FWCMD_H2C_SECCAM_INFO_KEY_1_SH 0
#define FWCMD_H2C_SECCAM_INFO_KEY_1_MSK 0xffffffff
#define FWCMD_H2C_SECCAM_INFO_KEY_2_SH 0
#define FWCMD_H2C_SECCAM_INFO_KEY_2_MSK 0xffffffff
#define FWCMD_H2C_SECCAM_INFO_KEY_3_SH 0
#define FWCMD_H2C_SECCAM_INFO_KEY_3_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_FREXCH_TYPE_SH 0
#define FWCMD_H2C_SET_SND_PARA_FREXCH_TYPE_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_MODE_SH 6
#define FWCMD_H2C_SET_SND_PARA_MODE_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_USER_NUM_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_USER_NUM_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_USER_NUM_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_USER_NUM_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_MACID0_SH 0
#define FWCMD_H2C_SET_SND_PARA_MACID0_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID1_SH 8
#define FWCMD_H2C_SET_SND_PARA_MACID1_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID2_SH 16
#define FWCMD_H2C_SET_SND_PARA_MACID2_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID3_SH 24
#define FWCMD_H2C_SET_SND_PARA_MACID3_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID4_SH 0
#define FWCMD_H2C_SET_SND_PARA_MACID4_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID5_SH 8
#define FWCMD_H2C_SET_SND_PARA_MACID5_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID6_SH 16
#define FWCMD_H2C_SET_SND_PARA_MACID6_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_MACID7_SH 24
#define FWCMD_H2C_SET_SND_PARA_MACID7_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_NDPA_FRAME_CTRL_SH 0
#define FWCMD_H2C_SET_SND_PARA_NDPA_FRAME_CTRL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_NDPA_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_NDPA_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_NDPA_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_NDPA_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_HE BIT(0)
#define FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_DIALOG_SH 1
#define FWCMD_H2C_SET_SND_PARA_NDPA_SND_DLG_DIALOG_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_HT_NDPA_A3_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_HT_SEQ_CONTROL_SH 16
#define FWCMD_H2C_SET_SND_PARA_HT_SEQ_CONTROL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_FEEDBACK_TYPE BIT(12)
#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_NC_SH 13
#define FWCMD_H2C_SET_SND_PARA_VHT_STA0_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_AID12_SH 16
#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_FEEDBACK_TYPE BIT(28)
#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_VHT_STA1_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_FEEDBACK_TYPE BIT(12)
#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_NC_SH 13
#define FWCMD_H2C_SET_SND_PARA_VHT_STA2_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_AID12_SH 16
#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_FEEDBACK_TYPE BIT(28)
#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_VHT_STA3_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA0_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA1_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA2_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA3_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA4_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA5_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA6_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_HE_STA7_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP0_FRAME_CTL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_BFRP0_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP0_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_BFRP1_FRAME_CTL_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP1_FRAME_CTL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP1_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_BFRP1_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP1_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_BFRP2_FRAME_CTL_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP2_FRAME_CTL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP2_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_BFRP2_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_BFRP2_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_TRIGGER_INFO_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH_SH 4
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_LENGTH_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MORE_TF BIT(16)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_CS_REQUIRED BIT(17)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW_SH 18
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_BW_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF_SH 20
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_GI_LTF_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_MU_MIMO_LTF_MODE BIT(22)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF_SH 23
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_NUM_OF_HE_LTF_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_PKTEXT_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_STBC BIT(29)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_LDPC_EXTRA_SYMBOL BIT(30)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_DOPPLER BIT(31)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_AP_TX_POWER_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE_SH 6
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_UL_SPATIAL_REUSE_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U0_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U1_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U2_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP0_U3_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_TRIGGER_INFO_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_TRIGGER_INFO_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_LENGTH_SH 4
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_LENGTH_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_MORE_TF BIT(16)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_CS_REQUIRED BIT(17)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_BW_SH 18
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_BW_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_GI_LTF_SH 20
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_GI_LTF_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_MU_MIMO_LTF_MODE BIT(22)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_NUM_OF_HE_LTF_SH 23
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_NUM_OF_HE_LTF_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_PKTEXT_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_PKTEXT_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_STBC BIT(29)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_LDPC_EXTRA_SYMBOL BIT(30)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_DOPPLER BIT(31)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_AP_TX_POWER_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_AP_TX_POWER_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_SPATIAL_REUSE_SH 6
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_UL_SPATIAL_REUSE_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U0_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U1_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U2_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_HE_BFRP1_U3_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP0_FB_REXMIT_SH 0
#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP0_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP1_FB_REXMIT_SH 8
#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP1_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP2_FB_REXMIT_SH 16
#define FWCMD_H2C_SET_SND_PARA_VHT_BFRP2_FB_REXMIT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD0_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0_SH 16
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD0_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD0_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0_SH 9
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD0_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD0 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0_SH 19
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD0 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD0 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD0 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD0 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD0 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD0 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0_SH 28
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0_SH 4
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0_SH 8
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0_SH 11
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD0 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD0 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD0 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD0_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD0 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0_SH 24
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0_SH 27
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD1_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD1_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD1_SH 16
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD1_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD1_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD1_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD1_SH 9
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD1_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD1 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD1_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD1_SH 19
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD1 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD1 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD1 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD1 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD1 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD1 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD1_SH 28
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD1_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD1_SH 4
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD1_SH 8
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD1_SH 11
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD1 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD1 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD1 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD1_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD1_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD1 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD1_SH 24
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD1_SH 27
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD2_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD2_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD2_SH 16
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD2_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD2_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD2_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD2_SH 9
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD2_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD2 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD2_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD2_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD2_SH 19
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD2 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD2 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD2 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD2 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD2 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD2 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD2_SH 28
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD2_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD2_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD2_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD2_SH 4
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD2_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD2_SH 8
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD2_SH 11
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD2 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD2 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD2 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD2_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD2_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD2 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD2_SH 24
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD2_SH 27
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD2_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD3_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD3_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD3_SH 16
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD3_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD3_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD3_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD3_SH 9
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD3_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD3 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD3_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD3_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD3_SH 19
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD3 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD3 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD3 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD3 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD3 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD3 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD3_SH 28
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD3_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD3_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD3_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD3_SH 4
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD3_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD3_SH 8
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD3_SH 11
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD3 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD3 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD3 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD3_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD3_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD3 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD3_SH 24
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD3_SH 27
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD3_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD4_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_TXPKTSIZE_WD4_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD4_SH 16
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_DURATION_WD4_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD4_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_DATARATE_WD4_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD4_SH 9
#define FWCMD_H2C_SET_SND_PARA_WD_MACID_WD4_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_WD_FORCE_TXOP_WD4 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD4_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_WD4_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD4_SH 19
#define FWCMD_H2C_SET_SND_PARA_WD_GI_LTF_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_ER_WD4 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_DCM_WD4 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_STBC_WD4 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_LDPC_WD4 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_BW_ER_WD4 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_WD_MULTIPORT_ID_WD4 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD4_SH 28
#define FWCMD_H2C_SET_SND_PARA_WD_MBSSID_WD4_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD4_SH 0
#define FWCMD_H2C_SET_SND_PARA_WD_SIGNALING_TA_PKT_SC_WD4_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD4_SH 4
#define FWCMD_H2C_SET_SND_PARA_WD_SW_DEFINE_WD4_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD4_SH 8
#define FWCMD_H2C_SET_SND_PARA_WD_TXPWR_OFSET_TYPE_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD4_SH 11
#define FWCMD_H2C_SET_SND_PARA_WD_LIFETIME_SEL_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_STF_MODE_WD4 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_WD_DISDATAFB_WD4 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_SEL_WD4 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD4_SH 17
#define FWCMD_H2C_SET_SND_PARA_WD_DATA_TXCNT_LMT_WD4_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_WD_SIFS_TX_WD4 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD4_SH 24
#define FWCMD_H2C_SET_SND_PARA_WD_SND_PKT_SEL_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD4_SH 27
#define FWCMD_H2C_SET_SND_PARA_WD_NDPA_WD4_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0_SH 0
#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP0_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0_SH 12
#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0_SH 14
#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP0 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0_SH 17
#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP0_MSK 0x3ff
#define FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP0 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP1_SH 0
#define FWCMD_H2C_SET_SND_PARA_CSI_LEN_BFRP1_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP1_SH 12
#define FWCMD_H2C_SET_SND_PARA_TB_T_PE_BFRP1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP1_SH 14
#define FWCMD_H2C_SET_SND_PARA_TRI_PAD_BFRP1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_UL_CQI_RPT_TRI_BFRP1 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP1_SH 17
#define FWCMD_H2C_SET_SND_PARA_RF_GAIN_IDX_BFRP1_MSK 0x3ff
#define FWCMD_H2C_SET_SND_PARA_FIX_GAIN_EN_BFRP1 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_F2P_TYPE_SH 0
#define FWCMD_H2C_SET_SND_PARA_F2P_TYPE_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_F2P_INDEX_SH 8
#define FWCMD_H2C_SET_SND_PARA_F2P_INDEX_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_F2P_PERIOD_SH 16
#define FWCMD_H2C_SET_SND_PARA_F2P_PERIOD_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_F2P_UPDCNT_SH 0
#define FWCMD_H2C_SET_SND_PARA_F2P_UPDCNT_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_CR_IDX_SH 8
#define FWCMD_H2C_SET_SND_PARA_CR_IDX_MSK 0x3fffff
#define FWCMD_H2C_GET_CSI_BUF_BAND_SH 0
#define FWCMD_H2C_GET_CSI_BUF_BAND_MSK 0xff
#define FWCMD_H2C_GET_CSI_BUF_CSI_BUF_ID_SH 8
#define FWCMD_H2C_GET_CSI_BUF_CSI_BUF_ID_MSK 0xff
#define FWCMD_H2C_SET_CSI_BUF_BAND_SH 0
#define FWCMD_H2C_SET_CSI_BUF_BAND_MSK 0xff
#define FWCMD_H2C_SET_CSI_BUF_MACID_SH 8
#define FWCMD_H2C_SET_CSI_BUF_MACID_MSK 0xff
#define FWCMD_H2C_SET_CSI_BUF_CSI_BUF_ID_SH 16
#define FWCMD_H2C_SET_CSI_BUF_CSI_BUF_ID_MSK 0xffff
#define FWCMD_H2C_SET_CSI_BUF_BUF_IDX_SH 0
#define FWCMD_H2C_SET_CSI_BUF_BUF_IDX_MSK 0xffff
#define FWCMD_H2C_GET_SND_STS_BAND_SH 0
#define FWCMD_H2C_GET_SND_STS_BAND_MSK 0xff
#define FWCMD_H2C_GET_SND_STS_INDEX_SH 8
#define FWCMD_H2C_GET_SND_STS_INDEX_MSK 0xff
#define FWCMD_H2C_SET_SND_STS_BAND_SH 0
#define FWCMD_H2C_SET_SND_STS_BAND_MSK 0xff
#define FWCMD_H2C_SET_SND_STS_MACID_SH 8
#define FWCMD_H2C_SET_SND_STS_MACID_MSK 0xff
#define FWCMD_H2C_SET_SND_STS_INDEX_SH 16
#define FWCMD_H2C_SET_SND_STS_INDEX_MSK 0xff
#define FWCMD_H2C_INIT_SND_MER_BAND_SH 0
#define FWCMD_H2C_INIT_SND_MER_BAND_MSK 0xff
#define FWCMD_H2C_INIT_SND_MEE_BAND_SH 0
#define FWCMD_H2C_INIT_SND_MEE_BAND_MSK 0xff
#define FWCMD_H2C_CSI_FIX_RATE_BAND_SH 0
#define FWCMD_H2C_CSI_FIX_RATE_BAND_MSK 0xff
#define FWCMD_H2C_CSI_FIX_RATE_HT_RATE_SH 8
#define FWCMD_H2C_CSI_FIX_RATE_HT_RATE_MSK 0xff
#define FWCMD_H2C_CSI_FIX_RATE_VHT_RATE_SH 16
#define FWCMD_H2C_CSI_FIX_RATE_VHT_RATE_MSK 0xff
#define FWCMD_H2C_CSI_FIX_RATE_HE_RATE_SH 24
#define FWCMD_H2C_CSI_FIX_RATE_HE_RATE_MSK 0xff
#define FWCMD_H2C_CSI_RRSC_BAND_SH 0
#define FWCMD_H2C_CSI_RRSC_BAND_MSK 0xff
#define FWCMD_H2C_CSI_RRSC_RRSC_SH 0
#define FWCMD_H2C_CSI_RRSC_RRSC_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_CTRL_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_CTRL_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_0_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_0_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_1_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_1_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_2_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_2_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_3_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_3_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_4_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_4_MSK 0xffffffff
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_5_SH 0
#define FWCMD_H2C_SET_MU_TABLE_MU_TBL_5_MSK 0xffffffff
#define FWCMD_H2C_SET_CSI_PARA_REG_BAND BIT(0)
#define FWCMD_H2C_SET_CSI_PARA_REG_PORT_SEL BIT(1)
#define FWCMD_H2C_SET_CSI_PARA_REG_NC_SH 2
#define FWCMD_H2C_SET_CSI_PARA_REG_NC_MSK 0x7
#define FWCMD_H2C_SET_CSI_PARA_REG_NR_SH 5
#define FWCMD_H2C_SET_CSI_PARA_REG_NR_MSK 0x7
#define FWCMD_H2C_SET_CSI_PARA_REG_NG_SH 8
#define FWCMD_H2C_SET_CSI_PARA_REG_NG_MSK 0x3
#define FWCMD_H2C_SET_CSI_PARA_REG_CB_SH 10
#define FWCMD_H2C_SET_CSI_PARA_REG_CB_MSK 0x3
#define FWCMD_H2C_SET_CSI_PARA_REG_CS_SH 12
#define FWCMD_H2C_SET_CSI_PARA_REG_CS_MSK 0x3
#define FWCMD_H2C_SET_CSI_PARA_REG_LDPC_EN BIT(14)
#define FWCMD_H2C_SET_CSI_PARA_REG_STBC_EN BIT(15)
#define FWCMD_H2C_SET_CSI_PARA_REG_BF_EN BIT(16)
#define FWCMD_H2C_HW_SND_PR_BAND_SH 0
#define FWCMD_H2C_HW_SND_PR_BAND_MSK 0xff
#define FWCMD_H2C_HW_SND_PR_PR_SH 8
#define FWCMD_H2C_HW_SND_PR_PR_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_FREXCH_TYPE_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_FREXCH_TYPE_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_MODE_SH 6
#define FWCMD_H2C_SET_SND_PARA_V1_MODE_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_USER_NUM_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_USER_NUM_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_USER_NUM_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_USER_NUM_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID0_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_MACID0_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID1_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_MACID1_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID2_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_MACID2_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID3_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_MACID3_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID4_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_MACID4_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID5_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_MACID5_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID6_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_MACID6_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID7_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_MACID7_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID8_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_MACID8_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID9_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_MACID9_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID10_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_MACID10_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID11_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_MACID11_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_MACID12_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID13_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_MACID13_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID14_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_MACID14_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_MACID15_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_MACID15_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_FRAME_CTRL_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_FRAME_CTRL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_SND_DLG_HE BIT(0)
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_SND_DLG_DIALOG_SH 1
#define FWCMD_H2C_SET_SND_PARA_V1_NDPA_SND_DLG_DIALOG_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HT_NDPA_A3_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_HT_SEQ_CONTROL_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_HT_SEQ_CONTROL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_FEEDBACK_TYPE BIT(12)
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_NC_SH 13
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA0_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_AID12_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_FEEDBACK_TYPE BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA1_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_FEEDBACK_TYPE BIT(12)
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_NC_SH 13
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA2_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_AID12_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_FEEDBACK_TYPE BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_STA3_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA0_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA1_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA2_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA3_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA4_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA5_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA6_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA7_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA8_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA9_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA10_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA11_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA12_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA13_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA14_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_AID11_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_AID11_MSK 0x7ff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_BW_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_BW_MSK 0x3fff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_FB_NG_SH 25
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_FB_NG_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_DISAMBIGUATION BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_CB BIT(28)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_NC_SH 29
#define FWCMD_H2C_SET_SND_PARA_V1_HE_STA15_NC_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_FRAME_CTL_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_FRAME_CTL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP0_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_FRAME_CTL_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_FRAME_CTL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP1_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_FRAME_CTL_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_FRAME_CTL_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_DURATION_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_DURATION_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_L_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_L_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A1_H_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_L_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_L_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_H_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_BFRP2_A2_H_MSK 0xffffffff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_TRIGGER_INFO_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_TRIGGER_INFO_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_LENGTH_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_LENGTH_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_MORE_TF BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_CS_REQUIRED BIT(17)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_BW_SH 18
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_BW_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_GI_LTF_SH 20
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_GI_LTF_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_MU_MIMO_LTF_MODE BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_NUM_OF_HE_LTF_SH 23
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_NUM_OF_HE_LTF_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_PKTEXT_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_PKTEXT_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_STBC BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_LDPC_EXTRA_SYMBOL BIT(30)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_DOPPLER BIT(31)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_AP_TX_POWER_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_AP_TX_POWER_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_SPATIAL_REUSE_SH 6
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_UL_SPATIAL_REUSE_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U0_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U1_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U2_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U3_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U4_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U5_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U6_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP0_U7_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_TRIGGER_INFO_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_TRIGGER_INFO_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_LENGTH_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_LENGTH_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_MORE_TF BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_CS_REQUIRED BIT(17)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_BW_SH 18
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_BW_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_GI_LTF_SH 20
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_GI_LTF_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_MU_MIMO_LTF_MODE BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_NUM_OF_HE_LTF_SH 23
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_NUM_OF_HE_LTF_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_PKTEXT_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_PKTEXT_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_STBC BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_LDPC_EXTRA_SYMBOL BIT(30)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_DOPPLER BIT(31)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_AP_TX_POWER_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_AP_TX_POWER_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_SPATIAL_REUSE_SH 6
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_UL_SPATIAL_REUSE_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U0_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U1_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U2_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U3_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U4_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U5_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U6_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_AID12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_AID12_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_RU_POS_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_RU_POS_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_FEC_CODE BIT(20)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_MCS_SH 21
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_MCS_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_DCM BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_SS_ALLOC_SH 26
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_SS_ALLOC_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_TGT_RSSI_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_HE_BFRP1_U7_UL_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP0_FEEDBACKSEG_REXMIT_BITMAP_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP0_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP1_FEEDBACKSEG_REXMIT_BITMAP_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP1_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP2_FEEDBACKSEG_REXMIT_BITMAP_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_VHT_BFRP2_FEEDBACKSEG_REXMIT_BITMAP_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD0_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD0_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD0_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD0_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD0_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD0_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD0_SH 9
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD0_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD0 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD0_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD0_SH 19
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD0 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD0 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD0 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD0 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD0 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD0 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD0_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD0_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD0_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD0_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD0_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD0 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD0 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD0 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD0_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD0_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD0 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD0_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD0_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD0_SH 27
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD0 BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD1_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD1_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD1_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD1_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD1_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD1_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD1_SH 9
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD1_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD1 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD1_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD1_SH 19
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD1 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD1 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD1 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD1 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD1 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD1 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD1_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD1_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD1_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD1_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD1_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD1 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD1 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD1 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD1_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD1_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD1 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD1_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD1_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD1_SH 27
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD1 BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD2_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD2_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD2_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD2_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD2_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD2_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD2_SH 9
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD2_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD2 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD2_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD2_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD2_SH 19
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD2 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD2 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD2 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD2 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD2 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD2 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD2_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD2_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD2_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD2_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD2_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD2_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD2_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD2_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD2 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD2 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD2 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD2_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD2_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD2 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD2_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD2_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD2_SH 27
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD2_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD2 BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD3_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD3_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD3_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD3_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD3_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD3_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD3_SH 9
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD3_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD3 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD3_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD3_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD3_SH 19
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD3 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD3 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD3 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD3 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD3 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD3 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD3_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD3_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD3_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD3_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD3_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD3_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD3_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD3_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD3 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD3 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD3 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD3_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD3_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD3 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD3_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD3_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD3_SH 27
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD3_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD3 BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD4_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPKTSIZE_WD4_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD4_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_DURATION_WD4_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD4_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATARATE_WD4_MSK 0x1ff
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD4_SH 9
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MACID_WD4_MSK 0x7f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_FORCE_TXOP_WD4 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD4_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_WD4_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD4_SH 19
#define FWCMD_H2C_SET_SND_PARA_V1_WD_GI_LTF_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_ER_WD4 BIT(22)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_DCM_WD4 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_STBC_WD4 BIT(24)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_LDPC_WD4 BIT(25)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_BW_ER_WD4 BIT(26)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MULTIPORT_ID_WD4 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD4_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_WD_MBSSID_WD4_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD4_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIGNALING_TA_PKT_SC_WD4_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD4_SH 4
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SW_DEFINE_WD4_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD4_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_WD_TXPWR_OFSET_TYPE_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD4_SH 11
#define FWCMD_H2C_SET_SND_PARA_V1_WD_LIFETIME_SEL_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_STF_MODE_WD4 BIT(14)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DISDATAFB_WD4 BIT(15)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_SEL_WD4 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD4_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_WD_DATA_TXCNT_LMT_WD4_MSK 0x3f
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SIFS_TX_WD4 BIT(23)
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD4_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_WD_SND_PKT_SEL_WD4_MSK 0x7
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD4_SH 27
#define FWCMD_H2C_SET_SND_PARA_V1_WD_NDPA_WD4_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_WD_CQI_WD4 BIT(29)
#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP0_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP0_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP0_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP0_SH 14
#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP0_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_UL_CQI_RPT_TRI_BFRP0 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP0_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP0_MSK 0x3ff
#define FWCMD_H2C_SET_SND_PARA_V1_FIX_GAIN_EN_BFRP0 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP0_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP0_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP1_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_CSI_LEN_BFRP1_MSK 0xfff
#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP1_SH 12
#define FWCMD_H2C_SET_SND_PARA_V1_TB_T_PE_BFRP1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP1_SH 14
#define FWCMD_H2C_SET_SND_PARA_V1_TRI_PAD_BFRP1_MSK 0x3
#define FWCMD_H2C_SET_SND_PARA_V1_UL_CQI_RPT_TRI_BFRP1 BIT(16)
#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP1_SH 17
#define FWCMD_H2C_SET_SND_PARA_V1_RF_GAIN_IDX_BFRP1_MSK 0x3ff
#define FWCMD_H2C_SET_SND_PARA_V1_FIX_GAIN_EN_BFRP1 BIT(27)
#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP1_SH 28
#define FWCMD_H2C_SET_SND_PARA_V1_UL_LEN_REF_BFRP1_MSK 0xf
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_TYPE_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_TYPE_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_INDEX_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_INDEX_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_PERIOD_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_PERIOD_MSK 0xffff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX0_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX0_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX1_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX1_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX2_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX2_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX3_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX3_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX4_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX4_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX5_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX5_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX6_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX6_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX7_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX7_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX8_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX8_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX9_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX9_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX10_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX10_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX11_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX11_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX12_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX12_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX13_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX13_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX14_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX14_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX15_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX15_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX16_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX16_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX17_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX17_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX18_SH 16
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX18_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX19_SH 24
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX19_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX20_SH 0
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX20_MSK 0xff
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX21_SH 8
#define FWCMD_H2C_SET_SND_PARA_V1_F2P_IDX21_MSK 0xff
#define FWCMD_H2C_BA_CAM_VALID BIT(0)
#define FWCMD_H2C_BA_CAM_INIT_REQ BIT(1)
#define FWCMD_H2C_BA_CAM_ENTRY_IDX_SH 2
#define FWCMD_H2C_BA_CAM_ENTRY_IDX_MSK 0x3
#define FWCMD_H2C_BA_CAM_TID_SH 4
#define FWCMD_H2C_BA_CAM_TID_MSK 0xf
#define FWCMD_H2C_BA_CAM_MACID_SH 8
#define FWCMD_H2C_BA_CAM_MACID_MSK 0xff
#define FWCMD_H2C_BA_CAM_BMAP_SIZE_SH 16
#define FWCMD_H2C_BA_CAM_BMAP_SIZE_MSK 0xf
#define FWCMD_H2C_BA_CAM_SSN_SH 20
#define FWCMD_H2C_BA_CAM_SSN_MSK 0xfff
#define FWCMD_H2C_BA_CAM_UID_VALUE_SH 0
#define FWCMD_H2C_BA_CAM_UID_VALUE_MSK 0xff
#define FWCMD_H2C_BA_CAM_STD_ENTRY_EN BIT(8)
#define FWCMD_H2C_BA_CAM_BAND_SEL BIT(9)
#define FWCMD_H2C_BA_CAM_ENTRY_IDX_V1_SH 28
#define FWCMD_H2C_BA_CAM_ENTRY_IDX_V1_MSK 0xf
#define FWCMD_H2C_IE_CAM_BAND BIT(0)
#define FWCMD_H2C_IE_CAM_PORT_SH 1
#define FWCMD_H2C_IE_CAM_PORT_MSK 0x7
#define FWCMD_H2C_IE_CAM_CAM_EN BIT(4)
#define FWCMD_H2C_IE_CAM_HIT_FRWD_EN BIT(5)
#define FWCMD_H2C_IE_CAM_HIT_FRWD_SH 6
#define FWCMD_H2C_IE_CAM_HIT_FRWD_MSK 0x3
#define FWCMD_H2C_IE_CAM_MISS_FRWD_EN BIT(8)
#define FWCMD_H2C_IE_CAM_MISS_FRWD_SH 9
#define FWCMD_H2C_IE_CAM_MISS_FRWD_MSK 0x3
#define FWCMD_H2C_IE_CAM_UPD_NUM_SH 11
#define FWCMD_H2C_IE_CAM_UPD_NUM_MSK 0x1f
#define FWCMD_H2C_IE_CAM_RST BIT(16)
#define FWCMD_H2C_IE_CAM_IDX_SH 0
#define FWCMD_H2C_IE_CAM_IDX_MSK 0xff
#define FWCMD_H2C_IE_CAM_CAM_INFO0_SH 8
#define FWCMD_H2C_IE_CAM_CAM_INFO0_MSK 0xffffff
#define FWCMD_H2C_IE_CAM_CAM_INFO1_SH 0
#define FWCMD_H2C_IE_CAM_CAM_INFO1_MSK 0xffffffff
#define FWCMD_H2C_ADD_MCC_MACID_SH 0
#define FWCMD_H2C_ADD_MCC_MACID_MSK 0xff
#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG0_SH 8
#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG0_MSK 0xff
#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG1_SH 16
#define FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG1_MSK 0xff
#define FWCMD_H2C_ADD_MCC_PRIMARY_CH_SH 24
#define FWCMD_H2C_ADD_MCC_PRIMARY_CH_MSK 0xff
#define FWCMD_H2C_ADD_MCC_BANDWIDTH_SH 0
#define FWCMD_H2C_ADD_MCC_BANDWIDTH_MSK 0xf
#define FWCMD_H2C_ADD_MCC_GROUP_SH 4
#define FWCMD_H2C_ADD_MCC_GROUP_MSK 0x3
#define FWCMD_H2C_ADD_MCC_C2H_RPT_SH 6
#define FWCMD_H2C_ADD_MCC_C2H_RPT_MSK 0x3
#define FWCMD_H2C_ADD_MCC_DIS_TX_NULL BIT(8)
#define FWCMD_H2C_ADD_MCC_DIS_SW_RETRY BIT(9)
#define FWCMD_H2C_ADD_MCC_IN_CURR_CH BIT(10)
#define FWCMD_H2C_ADD_MCC_SW_RETRY_COUNT_SH 11
#define FWCMD_H2C_ADD_MCC_SW_RETRY_COUNT_MSK 0x7
#define FWCMD_H2C_ADD_MCC_TX_NULL_EARLY_SH 14
#define FWCMD_H2C_ADD_MCC_TX_NULL_EARLY_MSK 0xf
#define FWCMD_H2C_ADD_MCC_BTC_IN_2G BIT(18)
#define FWCMD_H2C_ADD_MCC_PTA_EN BIT(19)
#define FWCMD_H2C_ADD_MCC_RFK_BY_PASS BIT(20)
#define FWCMD_H2C_ADD_MCC_DURATION_SH 0
#define FWCMD_H2C_ADD_MCC_DURATION_MSK 0xffffffff
#define FWCMD_H2C_ADD_MCC_COURTESY_EN BIT(0)
#define FWCMD_H2C_ADD_MCC_COURTESY_NUM_SH 8
#define FWCMD_H2C_ADD_MCC_COURTESY_NUM_MSK 0xff
#define FWCMD_H2C_ADD_MCC_COURTESY_TARGET_SH 16
#define FWCMD_H2C_ADD_MCC_COURTESY_TARGET_MSK 0xff
#define FWCMD_H2C_START_MCC_GROUP_SH 0
#define FWCMD_H2C_START_MCC_GROUP_MSK 0x3
#define FWCMD_H2C_START_MCC_BTC_IN_GROUP BIT(2)
#define FWCMD_H2C_START_MCC_OLD_GROUP_ACTION_SH 3
#define FWCMD_H2C_START_MCC_OLD_GROUP_ACTION_MSK 0x3
#define FWCMD_H2C_START_MCC_OLD_GROUP_SH 5
#define FWCMD_H2C_START_MCC_OLD_GROUP_MSK 0x3
#define FWCMD_H2C_START_MCC_MACID_SH 24
#define FWCMD_H2C_START_MCC_MACID_MSK 0xff
#define FWCMD_H2C_START_MCC_TSF_LOW_SH 0
#define FWCMD_H2C_START_MCC_TSF_LOW_MSK 0xffffffff
#define FWCMD_H2C_START_MCC_TSF_HIGH_SH 0
#define FWCMD_H2C_START_MCC_TSF_HIGH_MSK 0xffffffff
#define FWCMD_H2C_STOP_MCC_MACID_SH 0
#define FWCMD_H2C_STOP_MCC_MACID_MSK 0xff
#define FWCMD_H2C_STOP_MCC_GROUP_SH 8
#define FWCMD_H2C_STOP_MCC_GROUP_MSK 0x3
#define FWCMD_H2C_STOP_MCC_PREV_GROUPS BIT(10)
#define FWCMD_H2C_DEL_MCC_GROUP_GROUP_SH 0
#define FWCMD_H2C_DEL_MCC_GROUP_GROUP_MSK 0x3
#define FWCMD_H2C_DEL_MCC_GROUP_PREV_GROUPS BIT(2)
#define FWCMD_H2C_RESET_MCC_GROUP_GROUP_SH 0
#define FWCMD_H2C_RESET_MCC_GROUP_GROUP_MSK 0x3
#define FWCMD_H2C_MCC_REQ_TSF_GROUP_SH 0
#define FWCMD_H2C_MCC_REQ_TSF_GROUP_MSK 0x3
#define FWCMD_H2C_MCC_REQ_TSF_MACID_X_SH 8
#define FWCMD_H2C_MCC_REQ_TSF_MACID_X_MSK 0xff
#define FWCMD_H2C_MCC_REQ_TSF_MACID_Y_SH 16
#define FWCMD_H2C_MCC_REQ_TSF_MACID_Y_MSK 0xff
#define FWCMD_H2C_MCC_MACID_BITMAP_GROUP_SH 0
#define FWCMD_H2C_MCC_MACID_BITMAP_GROUP_MSK 0x3
#define FWCMD_H2C_MCC_MACID_BITMAP_MACID_SH 8
#define FWCMD_H2C_MCC_MACID_BITMAP_MACID_MSK 0xff
#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_LENGTH_SH 16
#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_LENGTH_MSK 0xff
#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_SH 0
#define FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_MSK 0xffffffff
#define FWCMD_H2C_MCC_SYNC_GROUP_SH 0
#define FWCMD_H2C_MCC_SYNC_GROUP_MSK 0x3
#define FWCMD_H2C_MCC_SYNC_MACID_SOURCE_SH 8
#define FWCMD_H2C_MCC_SYNC_MACID_SOURCE_MSK 0xff
#define FWCMD_H2C_MCC_SYNC_MACID_TARGET_SH 16
#define FWCMD_H2C_MCC_SYNC_MACID_TARGET_MSK 0xff
#define FWCMD_H2C_MCC_SYNC_SYNC_OFFSET_SH 24
#define FWCMD_H2C_MCC_SYNC_SYNC_OFFSET_MSK 0xff
#define FWCMD_H2C_MCC_SET_DURATION_GROUP_SH 0
#define FWCMD_H2C_MCC_SET_DURATION_GROUP_MSK 0x3
#define FWCMD_H2C_MCC_SET_DURATION_BTC_IN_GROUP BIT(2)
#define FWCMD_H2C_MCC_SET_DURATION_START_MACID_SH 8
#define FWCMD_H2C_MCC_SET_DURATION_START_MACID_MSK 0xff
#define FWCMD_H2C_MCC_SET_DURATION_MACID_X_SH 16
#define FWCMD_H2C_MCC_SET_DURATION_MACID_X_MSK 0xff
#define FWCMD_H2C_MCC_SET_DURATION_MACID_Y_SH 24
#define FWCMD_H2C_MCC_SET_DURATION_MACID_Y_MSK 0xff
#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_LOW_SH 0
#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_LOW_MSK 0xffffffff
#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_HIGH_SH 0
#define FWCMD_H2C_MCC_SET_DURATION_START_TSF_HIGH_MSK 0xffffffff
#define FWCMD_H2C_MCC_SET_DURATION_DURATION_X_SH 0
#define FWCMD_H2C_MCC_SET_DURATION_DURATION_X_MSK 0xffffffff
#define FWCMD_H2C_MCC_SET_DURATION_DURATION_Y_SH 0
#define FWCMD_H2C_MCC_SET_DURATION_DURATION_Y_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_WRITE_ADDR_SH 0
#define FWCMD_H2C_PLAT_FLASH_WRITE_ADDR_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_WRITE_LENGTH_SH 0
#define FWCMD_H2C_PLAT_FLASH_WRITE_LENGTH_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_WRITE_PAYLOAD0_SH 0
#define FWCMD_H2C_PLAT_FLASH_WRITE_PAYLOAD0_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_ERASE_ADDR_SH 0
#define FWCMD_H2C_PLAT_FLASH_ERASE_ADDR_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_ERASE_LENGTH_SH 0
#define FWCMD_H2C_PLAT_FLASH_ERASE_LENGTH_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_READ_ADDR_SH 0
#define FWCMD_H2C_PLAT_FLASH_READ_ADDR_MSK 0xffffffff
#define FWCMD_H2C_PLAT_FLASH_READ_LENGTH_SH 0
#define FWCMD_H2C_PLAT_FLASH_READ_LENGTH_MSK 0xffffffff
#define FWCMD_H2C_FCS_AP_PORT_ID_SH 0
#define FWCMD_H2C_FCS_AP_PORT_ID_MSK 0xf
#define FWCMD_H2C_FCS_CH_IDX_SH 4
#define FWCMD_H2C_FCS_CH_IDX_MSK 0xf
#define FWCMD_H2C_FCS_THERMAL_IDX_SH 8
#define FWCMD_H2C_FCS_THERMAL_IDX_MSK 0xf
#define FWCMD_H2C_FCS_PAUSE_REL_MODE_SH 12
#define FWCMD_H2C_FCS_PAUSE_REL_MODE_MSK 0xf
#define FWCMD_H2C_FCS_CON_STA_NUM_SH 16
#define FWCMD_H2C_FCS_CON_STA_NUM_MSK 0xff
#define FWCMD_H2C_FCS_BAND BIT(24)
#define FWCMD_H2C_FCS_BANDWIDTH_SH 25
#define FWCMD_H2C_FCS_BANDWIDTH_MSK 0x3
#define FWCMD_H2C_FCS_PRI_CH_SH 0
#define FWCMD_H2C_FCS_PRI_CH_MSK 0xff
#define FWCMD_H2C_FCS_CENTRAL_CH_SH 8
#define FWCMD_H2C_FCS_CENTRAL_CH_MSK 0xff
#define FWCMD_H2C_FCS_REL_PAUSE_TSFL_SH 0
#define FWCMD_H2C_FCS_REL_PAUSE_TSFL_MSK 0xffffffff
#define FWCMD_H2C_FCS_REL_PAUSE_TSFH_SH 0
#define FWCMD_H2C_FCS_REL_PAUSE_TSFH_MSK 0xffffffff
#define FWCMD_H2C_FCS_REL_PAUSE_DELAY_TIME_SH 0
#define FWCMD_H2C_FCS_REL_PAUSE_DELAY_TIME_MSK 0xffffffff
#define FWCMD_H2C_FCS_CSA_PKT_ID0_SH 0
#define FWCMD_H2C_FCS_CSA_PKT_ID0_MSK 0xff
#define FWCMD_H2C_FCS_CSA_PKT_ID1_SH 8
#define FWCMD_H2C_FCS_CSA_PKT_ID1_MSK 0xff
#define FWCMD_H2C_FCS_CSA_PKT_ID2_SH 16
#define FWCMD_H2C_FCS_CSA_PKT_ID2_MSK 0xff
#define FWCMD_H2C_FCS_CSA_PKT_ID3_SH 24
#define FWCMD_H2C_FCS_CSA_PKT_ID3_MSK 0xff
#define FWCMD_H2C_CFG_WPS_EN BIT(0)
#define FWCMD_H2C_CFG_WPS_GPIO_SH 8
#define FWCMD_H2C_CFG_WPS_GPIO_MSK 0xff
#define FWCMD_H2C_CFG_WPS_INTL_SH 16
#define FWCMD_H2C_CFG_WPS_INTL_MSK 0xff
#define FWCMD_H2C_PORT_INIT_BAND BIT(0)
#define FWCMD_H2C_PORT_INIT_PORT_SH 1
#define FWCMD_H2C_PORT_INIT_PORT_MSK 0x7
#define FWCMD_H2C_PORT_INIT_NET_TYPE_SH 4
#define FWCMD_H2C_PORT_INIT_NET_TYPE_MSK 0x7
#define FWCMD_H2C_PORT_INIT_DTIM_PRD_SH 8
#define FWCMD_H2C_PORT_INIT_DTIM_PRD_MSK 0xff
#define FWCMD_H2C_PORT_INIT_MBSSID_NUM_SH 16
#define FWCMD_H2C_PORT_INIT_MBSSID_NUM_MSK 0xff
#define FWCMD_H2C_PORT_INIT_BSS_COLOR_SH 24
#define FWCMD_H2C_PORT_INIT_BSS_COLOR_MSK 0xff
#define FWCMD_H2C_PORT_INIT_BCN_ITVL_SH 0
#define FWCMD_H2C_PORT_INIT_BCN_ITVL_MSK 0xffff
#define FWCMD_H2C_PORT_INIT_HIQ_WND_SH 16
#define FWCMD_H2C_PORT_INIT_HIQ_WND_MSK 0xff
#define FWCMD_H2C_PORT_CFG_BAND BIT(0)
#define FWCMD_H2C_PORT_CFG_PORT_SH 1
#define FWCMD_H2C_PORT_CFG_PORT_MSK 0x7
#define FWCMD_H2C_PORT_CFG_MBSSID_IDX_SH 8
#define FWCMD_H2C_PORT_CFG_MBSSID_IDX_MSK 0xff
#define FWCMD_H2C_PORT_CFG_TYPE_SH 16
#define FWCMD_H2C_PORT_CFG_TYPE_MSK 0xff
#define FWCMD_H2C_PORT_CFG_VAL_SH 0
#define FWCMD_H2C_PORT_CFG_VAL_MSK 0xffffffff
//
//H2CPKT - CAT(Table)
//
#define FWCMD_H2C_MUDE_PARA_TBLUD_TBLUD_SH 0
#define FWCMD_H2C_MUDE_PARA_TBLUD_TBLUD_MSK 0xffffffff
#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA0_SH 0
#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA0_MSK 0xffffffff
#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA1_SH 0
#define FWCMD_H2C_MUDE_PARA_TBLUD_MUDECISION_PARA1_MSK 0xffffffff
#define FWCMD_H2C_MUDECISION_PARA_MUINFO_THOLD_SH 0
#define FWCMD_H2C_MUDECISION_PARA_MUINFO_THOLD_MSK 0x3fffffff
#define FWCMD_H2C_MUDECISION_PARA_BYPASS_THOLD BIT(30)
#define FWCMD_H2C_MUDECISION_PARA_BYPASS_TP BIT(31)
#define FWCMD_H2C_MUDECISION_PARA_INIT_RATE_SH 0
#define FWCMD_H2C_MUDECISION_PARA_INIT_RATE_MSK 0xf
#define FWCMD_H2C_MUDECISION_PARA_RETRY_TH_SH 4
#define FWCMD_H2C_MUDECISION_PARA_RETRY_TH_MSK 0x7
#define FWCMD_H2C_MU_FIXINFO_MUINFO_THOLDEN BIT(0)
#define FWCMD_H2C_MU_FIXINFO_MUINFO_THOLD_SH 1
#define FWCMD_H2C_MU_FIXINFO_MUINFO_THOLD_MSK 0x3fffffff
#define FWCMD_H2C_MU_FIXINFO_BYPASS_THOLD BIT(31)
#define FWCMD_H2C_MU_FIXINFO_FIXMU_EN BIT(0)
#define FWCMD_H2C_MU_FIXINFO_FIXMU_ID_SH 1
#define FWCMD_H2C_MU_FIXINFO_FIXMU_ID_MSK 0x7f
#define FWCMD_H2C_UL_FIXINFO_TBLUD_TBLUD_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_TBLUD_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D0_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D0_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D1_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D1_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D2_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D2_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D3_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D3_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D4_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D4_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D5_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D5_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D6_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D6_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D7_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D7_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D8_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D8_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D9_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D9_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D10_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D10_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D11_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D11_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D12_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D12_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D13_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D13_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D14_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D14_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D15_SH 0
#define FWCMD_H2C_UL_FIXINFO_TBLUD_UL_FIXINFO_D15_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_CFG_MODE_SH 0
#define FWCMD_H2C_UL_FIXINFO_CFG_MODE_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_CFG_INTERVAL_SH 2
#define FWCMD_H2C_UL_FIXINFO_CFG_INTERVAL_MSK 0x3f
#define FWCMD_H2C_UL_FIXINFO_CFG_BSR_THOLD_SH 8
#define FWCMD_H2C_UL_FIXINFO_CFG_BSR_THOLD_MSK 0xff
#define FWCMD_H2C_UL_FIXINFO_CFG_STOREMODE_SH 16
#define FWCMD_H2C_UL_FIXINFO_CFG_STOREMODE_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_DUR_SH 0
#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_DUR_MSK 0xffff
#define FWCMD_H2C_UL_FIXINFO_ULINFO_TF_TYPE_SH 16
#define FWCMD_H2C_UL_FIXINFO_ULINFO_TF_TYPE_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULINFO_SIGEN BIT(19)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_SIGSC_SH 20
#define FWCMD_H2C_UL_FIXINFO_ULINFO_SIGSC_MSK 0xf
#define FWCMD_H2C_UL_FIXINFO_ULINFO_MURTS BIT(24)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_SH 25
#define FWCMD_H2C_UL_FIXINFO_ULINFO_NDPA_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_SNDPKT_SH 27
#define FWCMD_H2C_UL_FIXINFO_ULINFO_SNDPKT_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_GI_LTF_SH 29
#define FWCMD_H2C_UL_FIXINFO_ULINFO_GI_LTF_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATART_SH 0
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATART_MSK 0x1ff
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATAER BIT(9)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATABW_SH 10
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATABW_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_STBC_SH 12
#define FWCMD_H2C_UL_FIXINFO_ULINFO_STBC_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_LDPC BIT(14)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATADCM BIT(15)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_APEPLEN_SH 16
#define FWCMD_H2C_UL_FIXINFO_ULINFO_APEPLEN_MSK 0xfff
#define FWCMD_H2C_UL_FIXINFO_ULINFO_MORETF BIT(28)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_DATA_VWER BIT(29)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_ISTWT BIT(30)
#define FWCMD_H2C_UL_FIXINFO_ULINFO_MULTIPORT_SH 0
#define FWCMD_H2C_UL_FIXINFO_ULINFO_MULTIPORT_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULINFO_MBSSID_SH 3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_MBSSID_MSK 0xf
#define FWCMD_H2C_UL_FIXINFO_ULINFO_TXPWR_MODE_SH 7
#define FWCMD_H2C_UL_FIXINFO_ULINFO_TXPWR_MODE_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULINFO_ULFIX_USAGE_SH 10
#define FWCMD_H2C_UL_FIXINFO_ULINFO_ULFIX_USAGE_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULINFO_TWTGRP_STANUM_SEL_SH 13
#define FWCMD_H2C_UL_FIXINFO_ULINFO_TWTGRP_STANUM_SEL_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULINFO_STORE_IDX_SH 15
#define FWCMD_H2C_UL_FIXINFO_ULINFO_STORE_IDX_MSK 0xf
#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_0_1_SH 0
#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_0_1_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_2_3_SH 0
#define FWCMD_H2C_UL_FIXINFO_UL_FIXINFO_STA_INFO_2_3_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_ULRUA_RU2SU BIT(0)
#define FWCMD_H2C_UL_FIXINFO_ULRUA_PPDU_BW_SH 1
#define FWCMD_H2C_UL_FIXINFO_ULRUA_PPDU_BW_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULRUA_GI_LTF_SH 3
#define FWCMD_H2C_UL_FIXINFO_ULRUA_GI_LTF_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULRUA_STBC BIT(6)
#define FWCMD_H2C_UL_FIXINFO_ULRUA_DOPPLER BIT(7)
#define FWCMD_H2C_UL_FIXINFO_ULRUA_LTF_MA_SH 8
#define FWCMD_H2C_UL_FIXINFO_ULRUA_LTF_MA_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_ULRUA_STANUM_SH 11
#define FWCMD_H2C_UL_FIXINFO_ULRUA_STANUM_MSK 0xf
#define FWCMD_H2C_UL_FIXINFO_ULRUA_RFGFIX BIT(16)
#define FWCMD_H2C_UL_FIXINFO_ULRUA_RFGIDX_SH 17
#define FWCMD_H2C_UL_FIXINFO_ULRUA_RFGIDX_MSK 0x3ff
#define FWCMD_H2C_UL_FIXINFO_ULRUA_TB_NOM_SH 27
#define FWCMD_H2C_UL_FIXINFO_ULRUA_TB_NOM_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_MODE BIT(0)
#define FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_ID_SH 1
#define FWCMD_H2C_UL_FIXINFO_ULRUA_GRP_ID_MSK 0x3f
#define FWCMD_H2C_UL_FIXINFO_ULRUA_FIX_MODE BIT(7)
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D0_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D0_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D1_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U0_D1_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D0_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D0_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D1_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U1_D1_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D0_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D0_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D1_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U2_D1_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D0_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D0_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D1_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_ENT_U3_D1_MSK 0xffffffff
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0_SH 0
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_0_MSK 0xff
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0_SH 8
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_0_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1_SH 16
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_MACID_1_MSK 0xff
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1_SH 24
#define FWCMD_H2C_UL_FIXINFO_STA_INFO_PREF_AC_1_MSK 0x3
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DROP BIT(0)
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI_SH 1
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_TGT_RSSI_MSK 0x7f
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID_SH 8
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MAC_ID_MSK 0xff
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS_SH 16
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RU_POS_MSK 0xff
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_CODE BIT(24)
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_VIP BIT(25)
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN_SH 0
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_BSRLEN_MSK 0x7fff
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_DCM BIT(16)
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS_SH 17
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_SS_MSK 0x7
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS_SH 20
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_MCS_MSK 0xf
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL_SH 24
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RT_TBLCOL_MSK 0x3f
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_PRTL_ALLOC BIT(30)
#define FWCMD_H2C_UL_FIXINFO_UL_RUA_STA_ENT_RATE_CHG BIT(31)
#define FWCMD_H2C_ADDR_CAM_VALID BIT(0)
#define FWCMD_H2C_ADDR_CAM_NET_TYPE_SH 1
#define FWCMD_H2C_ADDR_CAM_NET_TYPE_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_BCN_HIT_COND_SH 3
#define FWCMD_H2C_ADDR_CAM_BCN_HIT_COND_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_HIT_RULE_SH 5
#define FWCMD_H2C_ADDR_CAM_HIT_RULE_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_BB_SEL BIT(7)
#define FWCMD_H2C_ADDR_CAM_ADDR_MASK_SH 8
#define FWCMD_H2C_ADDR_CAM_ADDR_MASK_MSK 0x3f
#define FWCMD_H2C_ADDR_CAM_MASK_SEL_SH 14
#define FWCMD_H2C_ADDR_CAM_MASK_SEL_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SMA_HASH_SH 16
#define FWCMD_H2C_ADDR_CAM_SMA_HASH_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA_HASH_SH 24
#define FWCMD_H2C_ADDR_CAM_TMA_HASH_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_BSSID_CAM_IDX_SH 0
#define FWCMD_H2C_ADDR_CAM_BSSID_CAM_IDX_MSK 0x3f
#define FWCMD_H2C_ADDR_CAM_SMA0_SH 0
#define FWCMD_H2C_ADDR_CAM_SMA0_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SMA1_SH 8
#define FWCMD_H2C_ADDR_CAM_SMA1_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SMA2_SH 16
#define FWCMD_H2C_ADDR_CAM_SMA2_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SMA3_SH 24
#define FWCMD_H2C_ADDR_CAM_SMA3_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SMA4_SH 0
#define FWCMD_H2C_ADDR_CAM_SMA4_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SMA5_SH 8
#define FWCMD_H2C_ADDR_CAM_SMA5_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA0_SH 16
#define FWCMD_H2C_ADDR_CAM_TMA0_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA1_SH 24
#define FWCMD_H2C_ADDR_CAM_TMA1_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA2_SH 0
#define FWCMD_H2C_ADDR_CAM_TMA2_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA3_SH 8
#define FWCMD_H2C_ADDR_CAM_TMA3_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA4_SH 16
#define FWCMD_H2C_ADDR_CAM_TMA4_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_TMA5_SH 24
#define FWCMD_H2C_ADDR_CAM_TMA5_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_MACID_SH 0
#define FWCMD_H2C_ADDR_CAM_MACID_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_PORT_INT_SH 8
#define FWCMD_H2C_ADDR_CAM_PORT_INT_MSK 0x7
#define FWCMD_H2C_ADDR_CAM_TSF_SYNC_SH 11
#define FWCMD_H2C_ADDR_CAM_TSF_SYNC_MSK 0x7
#define FWCMD_H2C_ADDR_CAM_TF_TRS BIT(14)
#define FWCMD_H2C_ADDR_CAM_LSIG_TXOP BIT(15)
#define FWCMD_H2C_ADDR_CAM_TGT_IND_SH 24
#define FWCMD_H2C_ADDR_CAM_TGT_IND_MSK 0x7
#define FWCMD_H2C_ADDR_CAM_FRM_TGT_IND_SH 27
#define FWCMD_H2C_ADDR_CAM_FRM_TGT_IND_MSK 0x7
#define FWCMD_H2C_ADDR_CAM_AID12_0_SH 0
#define FWCMD_H2C_ADDR_CAM_AID12_0_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_AID12_1_SH 8
#define FWCMD_H2C_ADDR_CAM_AID12_1_MSK 0xf
#define FWCMD_H2C_ADDR_CAM_WOL_PATTERN BIT(12)
#define FWCMD_H2C_ADDR_CAM_WOL_UC BIT(13)
#define FWCMD_H2C_ADDR_CAM_WOL_MAGIC BIT(14)
#define FWCMD_H2C_ADDR_CAM_WAPI BIT(15)
#define FWCMD_H2C_ADDR_CAM_SEC_ENT_MODE_SH 16
#define FWCMD_H2C_ADDR_CAM_SEC_ENT_MODE_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_KEYID_SH 18
#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_KEYID_SH 20
#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_KEYID_SH 22
#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_KEYID_SH 24
#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_KEYID_SH 26
#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_KEYID_SH 28
#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_KEYID_SH 30
#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_KEYID_MSK 0x3
#define FWCMD_H2C_ADDR_CAM_SEC_ENT_VALID_SH 0
#define FWCMD_H2C_ADDR_CAM_SEC_ENT_VALID_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_SH 8
#define FWCMD_H2C_ADDR_CAM_SEC_ENT0_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_SH 16
#define FWCMD_H2C_ADDR_CAM_SEC_ENT1_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_SH 24
#define FWCMD_H2C_ADDR_CAM_SEC_ENT2_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_SH 0
#define FWCMD_H2C_ADDR_CAM_SEC_ENT3_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_SH 8
#define FWCMD_H2C_ADDR_CAM_SEC_ENT4_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_SH 16
#define FWCMD_H2C_ADDR_CAM_SEC_ENT5_MSK 0xff
#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_SH 24
#define FWCMD_H2C_ADDR_CAM_SEC_ENT6_MSK 0xff
#define FWCMD_H2C_BSSID_CAM_BSSID_VALID BIT(0)
#define FWCMD_H2C_BSSID_CAM_BB_SEL BIT(1)
#define FWCMD_H2C_BSSID_CAM_BSS_COLOR_SH 8
#define FWCMD_H2C_BSSID_CAM_BSS_COLOR_MSK 0x7f
#define FWCMD_H2C_BSSID_CAM_BSSID0_SH 16
#define FWCMD_H2C_BSSID_CAM_BSSID0_MSK 0xff
#define FWCMD_H2C_BSSID_CAM_BSSID1_SH 24
#define FWCMD_H2C_BSSID_CAM_BSSID1_MSK 0xff
#define FWCMD_H2C_BSSID_CAM_BSSID2_SH 0
#define FWCMD_H2C_BSSID_CAM_BSSID2_MSK 0xff
#define FWCMD_H2C_BSSID_CAM_BSSID3_SH 8
#define FWCMD_H2C_BSSID_CAM_BSSID3_MSK 0xff
#define FWCMD_H2C_BSSID_CAM_BSSID4_SH 16
#define FWCMD_H2C_BSSID_CAM_BSSID4_MSK 0xff
#define FWCMD_H2C_BSSID_CAM_BSSID5_SH 24
#define FWCMD_H2C_BSSID_CAM_BSSID5_MSK 0xff
#define FWCMD_H2C_SEC_CAM_SEC_TYPE_SH 0
#define FWCMD_H2C_SEC_CAM_SEC_TYPE_MSK 0xf
#define FWCMD_H2C_SEC_CAM_EXT_KEY BIT(4)
#define FWCMD_H2C_SEC_CAM_SPP_MODE BIT(5)
#define FWCMD_H2C_FIXMODE_PARA_TBLUD_TBLUD_SH 0
#define FWCMD_H2C_FIXMODE_PARA_TBLUD_TBLUD_MSK 0xffffffff
#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D0_SH 0
#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D0_MSK 0xffffffff
#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D1_SH 0
#define FWCMD_H2C_FIXMODE_PARA_TBLUD_FIXMODE_PARA_D1_MSK 0xffffffff
#define FWCMD_H2C_FIXMODE_PARA_FORCE_SUMURU_EN BIT(0)
#define FWCMD_H2C_FIXMODE_PARA_FORCESU BIT(1)
#define FWCMD_H2C_FIXMODE_PARA_FORCEMU BIT(2)
#define FWCMD_H2C_FIXMODE_PARA_FORCERU BIT(3)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_SU_EN BIT(4)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_VHTMU_EN BIT(5)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_HEMU_EN BIT(6)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_HERU_EN BIT(7)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FE_UL_EN BIT(8)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_SU BIT(9)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_VHTMU BIT(10)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HEMU BIT(11)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_HERU BIT(12)
#define FWCMD_H2C_FIXMODE_PARA_FIX_FRAME_SEQ_UL BIT(13)
#define FWCMD_H2C_FIXMODE_PARA_IS_DLRUHWGRP BIT(14)
#define FWCMD_H2C_FIXMODE_PARA_IS_ULRUHWGRP BIT(15)
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_SU_SH 16
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_SU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_VHTMU_SH 20
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_VHTMU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_VHTMU_SH 24
#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_VHTMU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HEMU_SH 28
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HEMU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HEMU_SH 0
#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HEMU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HERU_SH 4
#define FWCMD_H2C_FIXMODE_PARA_PROT_TYPE_HERU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HERU_SH 8
#define FWCMD_H2C_FIXMODE_PARA_RESP_TYPE_HERU_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_UL_PROT_TYPE_SH 12
#define FWCMD_H2C_FIXMODE_PARA_UL_PROT_TYPE_MSK 0xf
#define FWCMD_H2C_FIXMODE_PARA_RUGRPID_SH 16
#define FWCMD_H2C_FIXMODE_PARA_RUGRPID_MSK 0x1f
#define FWCMD_H2C_FIXMODE_PARA_MUGRPID_SH 21
#define FWCMD_H2C_FIXMODE_PARA_MUGRPID_MSK 0x1f
#define FWCMD_H2C_FIXMODE_PARA_ULGRPID_SH 26
#define FWCMD_H2C_FIXMODE_PARA_ULGRPID_MSK 0x1f
#define FWCMD_H2C_WRITE_OFLD_REQ_VALUE_LEN_SH 0
#define FWCMD_H2C_WRITE_OFLD_REQ_VALUE_LEN_MSK 0x7ff
#define FWCMD_H2C_WRITE_OFLD_REQ_POLLING BIT(13)
#define FWCMD_H2C_WRITE_OFLD_REQ_MASK_EN BIT(14)
#define FWCMD_H2C_WRITE_OFLD_REQ_LS BIT(15)
#define FWCMD_H2C_WRITE_OFLD_REQ_OFLD_ID_SH 16
#define FWCMD_H2C_WRITE_OFLD_REQ_OFLD_ID_MSK 0xff
#define FWCMD_H2C_WRITE_OFLD_REQ_ENTRY_NUM_SH 24
#define FWCMD_H2C_WRITE_OFLD_REQ_ENTRY_NUM_MSK 0xff
#define FWCMD_H2C_WRITE_OFLD_REQ_OFFSET_SH 0
#define FWCMD_H2C_WRITE_OFLD_REQ_OFFSET_MSK 0xffff
#define FWCMD_H2C_READ_OFLD_REQ_VALUE_LEN_SH 0
#define FWCMD_H2C_READ_OFLD_REQ_VALUE_LEN_MSK 0x7ff
#define FWCMD_H2C_READ_OFLD_REQ_LS BIT(15)
#define FWCMD_H2C_READ_OFLD_REQ_OFLD_ID_SH 16
#define FWCMD_H2C_READ_OFLD_REQ_OFLD_ID_MSK 0xff
#define FWCMD_H2C_READ_OFLD_REQ_ENTRY_NUM_SH 24
#define FWCMD_H2C_READ_OFLD_REQ_ENTRY_NUM_MSK 0xff
#define FWCMD_H2C_READ_OFLD_REQ_OFFSET_SH 0
#define FWCMD_H2C_READ_OFLD_REQ_OFFSET_MSK 0xffff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DEVICE_SH 0
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DEVICE_MSK 0xff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_HIOE_OP_SH 0
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_HIOE_OP_MSK 0xff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_INST_TYPE_SH 8
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_INST_TYPE_MSK 0xff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DATA_MODE_SH 24
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_DATA_MODE_MSK 0xff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_REGISTER_ADDR_SH 0
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_REGISTER_ADDR_MSK 0xffffffff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_H_SH 0
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_H_MSK 0xffff
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_L_SH 16
#define FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_L_MSK 0xffff
#define FWCMD_H2C_DCTRL_QOS_FIELD_H_SH 0
#define FWCMD_H2C_DCTRL_QOS_FIELD_H_MSK 0xff
#define FWCMD_H2C_DCTRL_HW_EXSEQ_MACID_SH 8
#define FWCMD_H2C_DCTRL_HW_EXSEQ_MACID_MSK 0x7f
#define FWCMD_H2C_DCTRL_QOS_FIELD_H_EN BIT(15)
#define FWCMD_H2C_DCTRL_AES_IV_L_SH 16
#define FWCMD_H2C_DCTRL_AES_IV_L_MSK 0xffff
#define FWCMD_H2C_DCTRL_AES_IV_H_SH 0
#define FWCMD_H2C_DCTRL_AES_IV_H_MSK 0xffffffff
#define FWCMD_H2C_DCTRL_SEQ0_SH 0
#define FWCMD_H2C_DCTRL_SEQ0_MSK 0xfff
#define FWCMD_H2C_DCTRL_SEQ1_SH 12
#define FWCMD_H2C_DCTRL_SEQ1_MSK 0xfff
#define FWCMD_H2C_DCTRL_AMSDU_MAX_LEN_SH 24
#define FWCMD_H2C_DCTRL_AMSDU_MAX_LEN_MSK 0x7
#define FWCMD_H2C_DCTRL_STA_AMSDU_EN BIT(27)
#define FWCMD_H2C_DCTRL_CHKSUM_OFLD_EN BIT(28)
#define FWCMD_H2C_DCTRL_WITH_LLC BIT(29)
#define FWCMD_H2C_DCTRL_SEC_HW_ENC BIT(31)
#define FWCMD_H2C_DCTRL_SEQ2_SH 0
#define FWCMD_H2C_DCTRL_SEQ2_MSK 0xfff
#define FWCMD_H2C_DCTRL_SEQ3_SH 12
#define FWCMD_H2C_DCTRL_SEQ3_MSK 0xfff
#define FWCMD_H2C_DCTRL_SEC_CAM_IDX_SH 24
#define FWCMD_H2C_DCTRL_SEC_CAM_IDX_MSK 0xff
#define FWCMD_H2C_CCTRL_DATARATE_SH 0
#define FWCMD_H2C_CCTRL_DATARATE_MSK 0x1ff
#define FWCMD_H2C_CCTRL_FORCE_TXOP BIT(9)
#define FWCMD_H2C_CCTRL_DATA_BW_SH 10
#define FWCMD_H2C_CCTRL_DATA_BW_MSK 0x3
#define FWCMD_H2C_CCTRL_DATA_GI_LTF_SH 12
#define FWCMD_H2C_CCTRL_DATA_GI_LTF_MSK 0x7
#define FWCMD_H2C_CCTRL_DARF_TC_INDEX BIT(15)
#define FWCMD_H2C_CCTRL_ARFR_CTRL_SH 16
#define FWCMD_H2C_CCTRL_ARFR_CTRL_MSK 0xf
#define FWCMD_H2C_CCTRL_ACQ_RPT_EN BIT(20)
#define FWCMD_H2C_CCTRL_MGQ_RPT_EN BIT(21)
#define FWCMD_H2C_CCTRL_ULQ_RPT_EN BIT(22)
#define FWCMD_H2C_CCTRL_TWTQ_RPT_EN BIT(23)
#define FWCMD_H2C_CCTRL_DISRTSFB BIT(25)
#define FWCMD_H2C_CCTRL_DISDATAFB BIT(26)
#define FWCMD_H2C_CCTRL_TRYRATE BIT(27)
#define FWCMD_H2C_CCTRL_AMPDU_DENSITY_SH 28
#define FWCMD_H2C_CCTRL_AMPDU_DENSITY_MSK 0xf
#define FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE_SH 0
#define FWCMD_H2C_CCTRL_DATA_RTY_LOWEST_RATE_MSK 0x1ff
#define FWCMD_H2C_CCTRL_AMPDU_TIME_SEL BIT(9)
#define FWCMD_H2C_CCTRL_AMPDU_LEN_SEL BIT(10)
#define FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SEL BIT(11)
#define FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_SH 12
#define FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_MSK 0xf
#define FWCMD_H2C_CCTRL_RTSRATE_SH 16
#define FWCMD_H2C_CCTRL_RTSRATE_MSK 0x1ff
#define FWCMD_H2C_CCTRL_VCS_STBC BIT(27)
#define FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE_SH 28
#define FWCMD_H2C_CCTRL_RTS_RTY_LOWEST_RATE_MSK 0xf
#define FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT_SH 0
#define FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT_MSK 0x3f
#define FWCMD_H2C_CCTRL_DATA_TXCNT_LMT_SEL BIT(6)
#define FWCMD_H2C_CCTRL_MAX_AGG_NUM_SEL BIT(7)
#define FWCMD_H2C_CCTRL_RTS_EN BIT(8)
#define FWCMD_H2C_CCTRL_CTS2SELF_EN BIT(9)
#define FWCMD_H2C_CCTRL_CCA_RTS_SH 10
#define FWCMD_H2C_CCTRL_CCA_RTS_MSK 0x3
#define FWCMD_H2C_CCTRL_HW_RTS_EN BIT(12)
#define FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE_SH 13
#define FWCMD_H2C_CCTRL_RTS_DROP_DATA_MODE_MSK 0x3
#define FWCMD_H2C_CCTRL_PRELD_EN BIT(15)
#define FWCMD_H2C_CCTRL_AMPDU_MAX_LEN_SH 16
#define FWCMD_H2C_CCTRL_AMPDU_MAX_LEN_MSK 0x7ff
#define FWCMD_H2C_CCTRL_UL_MU_DIS BIT(27)
#define FWCMD_H2C_CCTRL_AMPDU_MAX_TIME_SH 28
#define FWCMD_H2C_CCTRL_AMPDU_MAX_TIME_MSK 0xf
#define FWCMD_H2C_CCTRL_MAX_AGG_NUM_SH 0
#define FWCMD_H2C_CCTRL_MAX_AGG_NUM_MSK 0xff
#define FWCMD_H2C_CCTRL_BA_BMAP_SH 8
#define FWCMD_H2C_CCTRL_BA_BMAP_MSK 0x3
#define FWCMD_H2C_CCTRL_VO_LFTIME_SEL_SH 16
#define FWCMD_H2C_CCTRL_VO_LFTIME_SEL_MSK 0x7
#define FWCMD_H2C_CCTRL_VI_LFTIME_SEL_SH 19
#define FWCMD_H2C_CCTRL_VI_LFTIME_SEL_MSK 0x7
#define FWCMD_H2C_CCTRL_BE_LFTIME_SEL_SH 22
#define FWCMD_H2C_CCTRL_BE_LFTIME_SEL_MSK 0x7
#define FWCMD_H2C_CCTRL_BK_LFTIME_SEL_SH 25
#define FWCMD_H2C_CCTRL_BK_LFTIME_SEL_MSK 0x7
#define FWCMD_H2C_CCTRL_SECTYPE_SH 28
#define FWCMD_H2C_CCTRL_SECTYPE_MSK 0xf
#define FWCMD_H2C_CCTRL_MULTI_PORT_ID_SH 0
#define FWCMD_H2C_CCTRL_MULTI_PORT_ID_MSK 0x7
#define FWCMD_H2C_CCTRL_BMC BIT(3)
#define FWCMD_H2C_CCTRL_MBSSID_SH 4
#define FWCMD_H2C_CCTRL_MBSSID_MSK 0xf
#define FWCMD_H2C_CCTRL_NAVUSEHDR BIT(8)
#define FWCMD_H2C_CCTRL_TXPWR_MODE_SH 9
#define FWCMD_H2C_CCTRL_TXPWR_MODE_MSK 0x7
#define FWCMD_H2C_CCTRL_DATA_DCM BIT(12)
#define FWCMD_H2C_CCTRL_DATA_ER BIT(13)
#define FWCMD_H2C_CCTRL_DATA_LDPC BIT(14)
#define FWCMD_H2C_CCTRL_DATA_STBC BIT(15)
#define FWCMD_H2C_CCTRL_A_CTRL_BQR BIT(16)
#define FWCMD_H2C_CCTRL_A_CTRL_UPH BIT(17)
#define FWCMD_H2C_CCTRL_A_CTRL_BSR BIT(18)
#define FWCMD_H2C_CCTRL_A_CTRL_CAS BIT(19)
#define FWCMD_H2C_CCTRL_DATA_BW_ER BIT(20)
#define FWCMD_H2C_CCTRL_LSIG_TXOP_EN BIT(21)
#define FWCMD_H2C_CCTRL_CTRL_CNT_VLD BIT(27)
#define FWCMD_H2C_CCTRL_CTRL_CNT_SH 28
#define FWCMD_H2C_CCTRL_CTRL_CNT_MSK 0xf
#define FWCMD_H2C_CCTRL_RESP_REF_RATE_SH 0
#define FWCMD_H2C_CCTRL_RESP_REF_RATE_MSK 0x1ff
#define FWCMD_H2C_CCTRL_ALL_ACK_SUPPORT BIT(12)
#define FWCMD_H2C_CCTRL_BSR_QUEUE_SIZE_FORMAT BIT(13)
#define FWCMD_H2C_CCTRL_NTX_PATH_EN_SH 16
#define FWCMD_H2C_CCTRL_NTX_PATH_EN_MSK 0xf
#define FWCMD_H2C_CCTRL_PATH_MAP_A_SH 20
#define FWCMD_H2C_CCTRL_PATH_MAP_A_MSK 0x3
#define FWCMD_H2C_CCTRL_PATH_MAP_B_SH 22
#define FWCMD_H2C_CCTRL_PATH_MAP_B_MSK 0x3
#define FWCMD_H2C_CCTRL_PATH_MAP_C_SH 24
#define FWCMD_H2C_CCTRL_PATH_MAP_C_MSK 0x3
#define FWCMD_H2C_CCTRL_PATH_MAP_D_SH 26
#define FWCMD_H2C_CCTRL_PATH_MAP_D_MSK 0x3
#define FWCMD_H2C_CCTRL_ANTSEL_A BIT(28)
#define FWCMD_H2C_CCTRL_ANTSEL_B BIT(29)
#define FWCMD_H2C_CCTRL_ANTSEL_C BIT(30)
#define FWCMD_H2C_CCTRL_ANTSEL_D BIT(31)
#define FWCMD_H2C_CCTRL_ADDR_CAM_INDEX_SH 0
#define FWCMD_H2C_CCTRL_ADDR_CAM_INDEX_MSK 0xff
#define FWCMD_H2C_CCTRL_PAID_SH 8
#define FWCMD_H2C_CCTRL_PAID_MSK 0x1ff
#define FWCMD_H2C_CCTRL_ULDL BIT(17)
#define FWCMD_H2C_CCTRL_DOPPLER_CTRL_SH 18
#define FWCMD_H2C_CCTRL_DOPPLER_CTRL_MSK 0x3
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING_SH 20
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING_MSK 0x3
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40_SH 22
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING40_MSK 0x3
#define FWCMD_H2C_CCTRL_TXPWR_TOLERENCE_SH 24
#define FWCMD_H2C_CCTRL_TXPWR_TOLERENCE_MSK 0x3f
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80_SH 30
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING80_MSK 0x3
#define FWCMD_H2C_CCTRL_NC_SH 0
#define FWCMD_H2C_CCTRL_NC_MSK 0x7
#define FWCMD_H2C_CCTRL_NR_SH 3
#define FWCMD_H2C_CCTRL_NR_MSK 0x7
#define FWCMD_H2C_CCTRL_NG_SH 6
#define FWCMD_H2C_CCTRL_NG_MSK 0x3
#define FWCMD_H2C_CCTRL_CB_SH 8
#define FWCMD_H2C_CCTRL_CB_MSK 0x3
#define FWCMD_H2C_CCTRL_CS_SH 10
#define FWCMD_H2C_CCTRL_CS_MSK 0x3
#define FWCMD_H2C_CCTRL_CSI_TXBF_EN BIT(12)
#define FWCMD_H2C_CCTRL_CSI_STBC_EN BIT(13)
#define FWCMD_H2C_CCTRL_CSI_LDPC_EN BIT(14)
#define FWCMD_H2C_CCTRL_CSI_PARA_EN BIT(15)
#define FWCMD_H2C_CCTRL_CSI_FIX_RATE_SH 16
#define FWCMD_H2C_CCTRL_CSI_FIX_RATE_MSK 0x1ff
#define FWCMD_H2C_CCTRL_CSI_GI_LTF_SH 25
#define FWCMD_H2C_CCTRL_CSI_GI_LTF_MSK 0x7
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160_SH 28
#define FWCMD_H2C_CCTRL_NOMINAL_PKT_PADDING160_MSK 0x3
#define FWCMD_H2C_CCTRL_CSI_BW_SH 30
#define FWCMD_H2C_CCTRL_CSI_BW_MSK 0x3
#define FWCMD_H2C_IE_CAM_INFO_TYPE_SH 0
#define FWCMD_H2C_IE_CAM_INFO_TYPE_MSK 0xff
#define FWCMD_H2C_IE_CAM_INFO_DATA0_SH 8
#define FWCMD_H2C_IE_CAM_INFO_DATA0_MSK 0xff
#define FWCMD_H2C_IE_CAM_INFO_DATA1_SH 16
#define FWCMD_H2C_IE_CAM_INFO_DATA1_MSK 0xff
#define FWCMD_H2C_IE_CAM_INFO_DATA2_SH 24
#define FWCMD_H2C_IE_CAM_INFO_DATA2_MSK 0xff
#define FWCMD_H2C_IE_CAM_INFO_DATA3_SH 0
#define FWCMD_H2C_IE_CAM_INFO_DATA3_MSK 0xff
#define FWCMD_H2C_PLAT_AUTO_TEST_D0_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D0_MSK 0xffffffff
#define FWCMD_H2C_PLAT_AUTO_TEST_D1_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D1_MSK 0xffffffff
#define FWCMD_H2C_PLAT_AUTO_TEST_D2_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D2_MSK 0xffffffff
#define FWCMD_H2C_PLAT_AUTO_TEST_D3_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D3_MSK 0xffffffff
#define FWCMD_H2C_PLAT_AUTO_TEST_D4_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D4_MSK 0xffffffff
#define FWCMD_H2C_PLAT_AUTO_TEST_D5_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D5_MSK 0xffffffff
#define FWCMD_H2C_PLAT_AUTO_TEST_D6_SH 0
#define FWCMD_H2C_PLAT_AUTO_TEST_D6_MSK 0xffffffff
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_FUNC_SH 0
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_FUNC_MSK 0x7f
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_ACK BIT(7)
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TOTAL_LEN_SH 8
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TOTAL_LEN_MSK 0xf
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_SEQ_NUM_SH 12
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_SEQ_NUM_MSK 0xf
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TX_EN_SH 16
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TX_EN_MSK 0xffff
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_MASK_SH 0
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_MASK_MSK 0xffff
#define FWCMD_H2C_H2CREG_SCH_TX_PAUSE_BAND BIT(16)
#define FWCMD_H2C_CMD_OFLD_SRC_SH 0
#define FWCMD_H2C_CMD_OFLD_SRC_MSK 0x3
#define FWCMD_H2C_CMD_OFLD_TYPE_SH 2
#define FWCMD_H2C_CMD_OFLD_TYPE_MSK 0x3
#define FWCMD_H2C_CMD_OFLD_LC BIT(4)
#define FWCMD_H2C_CMD_OFLD_PATH_SH 5
#define FWCMD_H2C_CMD_OFLD_PATH_MSK 0x3
#define FWCMD_H2C_CMD_OFLD_CMD_NUM_SH 8
#define FWCMD_H2C_CMD_OFLD_CMD_NUM_MSK 0x7f
#define FWCMD_H2C_CMD_OFLD_OFFSET_SH 16
#define FWCMD_H2C_CMD_OFLD_OFFSET_MSK 0xffff
#define FWCMD_H2C_CMD_OFLD_ID_SH 0
#define FWCMD_H2C_CMD_OFLD_ID_MSK 0xffff
#define FWCMD_H2C_CMD_OFLD_VALUE_SH 0
#define FWCMD_H2C_CMD_OFLD_VALUE_MSK 0xffffffff
#define FWCMD_H2C_CMD_OFLD_MASK_SH 0
#define FWCMD_H2C_CMD_OFLD_MASK_MSK 0xffffffff
#define FWCMD_H2C_FW_STS_PARA_EN BIT(0)
#define FWCMD_H2C_FW_STS_PARA_INTVL_MS_SH 16
#define FWCMD_H2C_FW_STS_PARA_INTVL_MS_MSK 0xffff
//
//H2CPKT - CAT(OutSrc,Phydm)
//
#define H2C_HDR_CAT_SH 0
#define H2C_HDR_CAT_MSK 0x3
#define H2C_HDR_CLASS_SH 2
#define H2C_HDR_CLASS_MSK 0x3f
#define H2C_HDR_FUNC_SH 8
#define H2C_HDR_FUNC_MSK 0xff
#define H2C_HDR_DEL_TYPE_SH 16
#define H2C_HDR_DEL_TYPE_MSK 0xf
#define H2C_HDR_H2C_SEQ_SH 24
#define H2C_HDR_H2C_SEQ_MSK 0xff
#define H2C_HDR_TOTAL_LEN_SH 0
#define H2C_HDR_TOTAL_LEN_MSK 0x3fff
#define H2C_HDR_REC_ACK BIT(14)
#define H2C_HDR_DONE_ACK BIT(15)
#define H2C_HDR_SEQ_VALID BIT(16)
#define H2C_HDR_SEQ_SH 17
#define H2C_HDR_SEQ_MSK 0x7
#define H2C_HDR_SEQ_STOP BIT(20)
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_MACID_CFG_IS_DISRA BIT(0)
#define FWCMD_H2C_MACID_CFG_MODE_CTRL_SH 1
#define FWCMD_H2C_MACID_CFG_MODE_CTRL_MSK 0x1f
#define FWCMD_H2C_MACID_CFG_BW_CAP_SH 6
#define FWCMD_H2C_MACID_CFG_BW_CAP_MSK 0x3
#define FWCMD_H2C_MACID_CFG_MACID_SH 8
#define FWCMD_H2C_MACID_CFG_MACID_MSK 0xff
#define FWCMD_H2C_MACID_CFG_DCM_CAP BIT(16)
#define FWCMD_H2C_MACID_CFG_ER_CAP BIT(17)
#define FWCMD_H2C_MACID_CFG_INIT_RATE_LV_SH 18
#define FWCMD_H2C_MACID_CFG_INIT_RATE_LV_MSK 0x3
#define FWCMD_H2C_MACID_CFG_BW_NOUPDATE BIT(20)
#define FWCMD_H2C_MACID_CFG_EN_SGI BIT(21)
#define FWCMD_H2C_MACID_CFG_LDPC_CAP BIT(22)
#define FWCMD_H2C_MACID_CFG_STBC_CAP BIT(23)
#define FWCMD_H2C_MACID_CFG_SS_NUM_SH 24
#define FWCMD_H2C_MACID_CFG_SS_NUM_MSK 0x7
#define FWCMD_H2C_MACID_CFG_GI_LTF_SH 27
#define FWCMD_H2C_MACID_CFG_GI_LTF_MSK 0x7
#define FWCMD_H2C_MACID_CFG_RA_MASK_LOW_SH 0
#define FWCMD_H2C_MACID_CFG_RA_MASK_LOW_MSK 0xffffffff
#define FWCMD_H2C_MACID_CFG_RA_MASK_HI_SH 0
#define FWCMD_H2C_MACID_CFG_RA_MASK_HI_MSK 0xfffffff
#define FWCMD_H2C_RSSI_RA_CONFIG_IS_DISRA BIT(0)
#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_LOW_SH 0
#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_LOW_MSK 0xffffffff
#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_HI_SH 0
#define FWCMD_H2C_RSSI_RA_CONFIG_RA_MASK_HI_MSK 0xffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
//
//H2CPKT - CAT(OutSrc, RF)
//
#define H2C_HDR_CAT_SH 0
#define H2C_HDR_CAT_MSK 0x3
#define H2C_HDR_CLASS_SH 2
#define H2C_HDR_CLASS_MSK 0x3f
#define H2C_HDR_FUNC_SH 8
#define H2C_HDR_FUNC_MSK 0xff
#define H2C_HDR_DEL_TYPE_SH 16
#define H2C_HDR_DEL_TYPE_MSK 0xf
#define H2C_HDR_H2C_SEQ_SH 24
#define H2C_HDR_H2C_SEQ_MSK 0xff
#define H2C_HDR_TOTAL_LEN_SH 0
#define H2C_HDR_TOTAL_LEN_MSK 0x3fff
#define H2C_HDR_REC_ACK BIT(14)
#define H2C_HDR_DONE_ACK BIT(15)
#define H2C_HDR_SEQ_VALID BIT(16)
#define H2C_HDR_SEQ_SH 17
#define H2C_HDR_SEQ_MSK 0x7
#define H2C_HDR_SEQ_STOP BIT(20)
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_H2C_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
//
//H2CPKT - CAT(OutSrc, BTC)
//
#define H2C_HDR_CAT_SH 0
#define H2C_HDR_CAT_MSK 0x3
#define H2C_HDR_CLASS_SH 2
#define H2C_HDR_CLASS_MSK 0x3f
#define H2C_HDR_FUNC_SH 8
#define H2C_HDR_FUNC_MSK 0xff
#define H2C_HDR_DEL_TYPE_SH 16
#define H2C_HDR_DEL_TYPE_MSK 0xf
#define H2C_HDR_H2C_SEQ_SH 24
#define H2C_HDR_H2C_SEQ_MSK 0xff
#define H2C_HDR_TOTAL_LEN_SH 0
#define H2C_HDR_TOTAL_LEN_MSK 0x3fff
#define H2C_HDR_REC_ACK BIT(14)
#define H2C_HDR_DONE_ACK BIT(15)
#define H2C_HDR_SEQ_VALID BIT(16)
#define H2C_HDR_SEQ_SH 17
#define H2C_HDR_SEQ_MSK 0x7
#define H2C_HDR_SEQ_STOP BIT(20)
#define FWCMD_H2C_TDMA_EN BIT(0)
#define FWCMD_H2C_TDMA_PRO_PS BIT(1)
#define FWCMD_H2C_TDMA_NULL BIT(2)
#define FWCMD_H2C_TDMA_QOS_NULL BIT(3)
#define FWCMD_H2C_TDMA_WL_SLOT_SH 8
#define FWCMD_H2C_TDMA_WL_SLOT_MSK 0xff
//
//C2HPKT - CAT(TEST)
//
#define C2H_HDR_CAT_SH 0
#define C2H_HDR_CAT_MSK 0x3
#define C2H_HDR_CLASS_SH 2
#define C2H_HDR_CLASS_MSK 0x3f
#define C2H_HDR_FUNC_SH 8
#define C2H_HDR_FUNC_MSK 0xff
#define C2H_HDR_DEL_TYPE_SH 16
#define C2H_HDR_DEL_TYPE_MSK 0xf
#define C2H_HDR_C2H_SEQ_SH 24
#define C2H_HDR_C2H_SEQ_MSK 0xff
#define C2H_HDR_TOTAL_LEN_SH 0
#define C2H_HDR_TOTAL_LEN_MSK 0x3fff
#define FWCMD_C2H_C2H_LB_PAYLOAD_SH 0
#define FWCMD_C2H_C2H_LB_PAYLOAD_MSK 0xffffffff
#define FWCMD_C2H_TEST_PHY_RPT_PAYLOAD_SH 0
#define FWCMD_C2H_TEST_PHY_RPT_PAYLOAD_MSK 0xffffffff
#define FWCMD_C2H_SPIC_PAYLOAD0_SH 0
#define FWCMD_C2H_SPIC_PAYLOAD0_MSK 0xff
#define FWCMD_C2H_SPIC_PAYLOAD1_SH 8
#define FWCMD_C2H_SPIC_PAYLOAD1_MSK 0xff
#define FWCMD_C2H_SPIC_PAYLOAD2_SH 16
#define FWCMD_C2H_SPIC_PAYLOAD2_MSK 0xff
#define FWCMD_C2H_SPIC_PAYLOAD3_SH 24
#define FWCMD_C2H_SPIC_PAYLOAD3_MSK 0x1ff
#define FWCMD_C2H_SPIC_PAYLOAD4_SH 0
#define FWCMD_C2H_SPIC_PAYLOAD4_MSK 0xff
#define FWCMD_C2H_SPIC_PAYLOAD5_SH 8
#define FWCMD_C2H_SPIC_PAYLOAD5_MSK 0xff
#define FWCMD_C2H_SPIC_PAYLOAD6_SH 16
#define FWCMD_C2H_SPIC_PAYLOAD6_MSK 0xff
#define FWCMD_C2H_SPIC_PAYLOAD7_SH 24
#define FWCMD_C2H_SPIC_PAYLOAD7_MSK 0x1ff
#define FWCMD_C2H_SPIC2_PAYLOAD0_SH 0
#define FWCMD_C2H_SPIC2_PAYLOAD0_MSK 0xff
#define FWCMD_C2H_SPIC2_PAYLOAD1_SH 8
#define FWCMD_C2H_SPIC2_PAYLOAD1_MSK 0xff
#define FWCMD_C2H_SPIC2_PAYLOAD2_SH 16
#define FWCMD_C2H_SPIC2_PAYLOAD2_MSK 0xff
#define FWCMD_C2H_SPIC2_PAYLOAD3_SH 24
#define FWCMD_C2H_SPIC2_PAYLOAD3_MSK 0x1ff
#define FWCMD_C2H_SPIC2_PAYLOAD4_SH 0
#define FWCMD_C2H_SPIC2_PAYLOAD4_MSK 0xff
#define FWCMD_C2H_SPIC2_PAYLOAD5_SH 8
#define FWCMD_C2H_SPIC2_PAYLOAD5_MSK 0xff
#define FWCMD_C2H_SPIC2_PAYLOAD6_SH 16
#define FWCMD_C2H_SPIC2_PAYLOAD6_MSK 0xff
#define FWCMD_C2H_SPIC2_PAYLOAD7_SH 24
#define FWCMD_C2H_SPIC2_PAYLOAD7_MSK 0x1ff
#define FWCMD_C2H_LPS_ONOFF_TEST_TYPE_SH 0
#define FWCMD_C2H_LPS_ONOFF_TEST_TYPE_MSK 0xffffffff
#define FWCMD_C2H_LPS_ONOFF_TEST_RESULT_SH 0
#define FWCMD_C2H_LPS_ONOFF_TEST_RESULT_MSK 0xffffffff
//
//C2HPKT - CAT(MAC)
//
#define C2H_HDR_CAT_SH 0
#define C2H_HDR_CAT_MSK 0x3
#define C2H_HDR_CLASS_SH 2
#define C2H_HDR_CLASS_MSK 0x3f
#define C2H_HDR_FUNC_SH 8
#define C2H_HDR_FUNC_MSK 0xff
#define C2H_HDR_DEL_TYPE_SH 16
#define C2H_HDR_DEL_TYPE_MSK 0xf
#define C2H_HDR_C2H_SEQ_SH 24
#define C2H_HDR_C2H_SEQ_MSK 0xff
#define C2H_HDR_TOTAL_LEN_SH 0
#define C2H_HDR_TOTAL_LEN_MSK 0x3fff
#define FWCMD_C2H_REC_ACK_CAT_SH 0
#define FWCMD_C2H_REC_ACK_CAT_MSK 0x3
#define FWCMD_C2H_REC_ACK_CLASS_SH 2
#define FWCMD_C2H_REC_ACK_CLASS_MSK 0x3f
#define FWCMD_C2H_REC_ACK_FUNC_SH 8
#define FWCMD_C2H_REC_ACK_FUNC_MSK 0xff
#define FWCMD_C2H_REC_ACK_H2C_SEQ_SH 16
#define FWCMD_C2H_REC_ACK_H2C_SEQ_MSK 0xff
#define FWCMD_C2H_DONE_ACK_CAT_SH 0
#define FWCMD_C2H_DONE_ACK_CAT_MSK 0x3
#define FWCMD_C2H_DONE_ACK_CLASS_SH 2
#define FWCMD_C2H_DONE_ACK_CLASS_MSK 0x3f
#define FWCMD_C2H_DONE_ACK_FUNC_SH 8
#define FWCMD_C2H_DONE_ACK_FUNC_MSK 0xff
#define FWCMD_C2H_DONE_ACK_H2C_RETURN_SH 16
#define FWCMD_C2H_DONE_ACK_H2C_RETURN_MSK 0xff
#define FWCMD_C2H_DONE_ACK_H2C_SEQ_SH 24
#define FWCMD_C2H_DONE_ACK_H2C_SEQ_MSK 0xff
#define FWCMD_C2H_C2H_LOG_LOG_MSG_SH 0
#define FWCMD_C2H_C2H_LOG_LOG_MSG_MSK 0xffffffff
#define FWCMD_C2H_BCN_CNT_PORT_MBSSID_IDX_SH 0
#define FWCMD_C2H_BCN_CNT_PORT_MBSSID_IDX_MSK 0x7f
#define FWCMD_C2H_BCN_CNT_BAND_IDX BIT(7)
#define FWCMD_C2H_BCN_CNT_CCA_FAIL_CNT_SH 8
#define FWCMD_C2H_BCN_CNT_CCA_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_EDCCA_FAIL_CNT_SH 12
#define FWCMD_C2H_BCN_CNT_EDCCA_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_NAV_FAIL_CNT_SH 16
#define FWCMD_C2H_BCN_CNT_NAV_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_TXON_FAIL_CNT_SH 20
#define FWCMD_C2H_BCN_CNT_TXON_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_MAC_FAIL_CNT_SH 24
#define FWCMD_C2H_BCN_CNT_MAC_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_OTHERS_FAIL_CNT_SH 28
#define FWCMD_C2H_BCN_CNT_OTHERS_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_LOCK_FAIL_CNT_SH 0
#define FWCMD_C2H_BCN_CNT_LOCK_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_CMP_FAIL_CNT_SH 4
#define FWCMD_C2H_BCN_CNT_CMP_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_INVALID_FAIL_CNT_SH 8
#define FWCMD_C2H_BCN_CNT_INVALID_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_SRCHEND_FAIL_CNT_SH 12
#define FWCMD_C2H_BCN_CNT_SRCHEND_FAIL_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CNT_OK_CNT_SH 16
#define FWCMD_C2H_BCN_CNT_OK_CNT_MSK 0xf
#define FWCMD_C2H_BCN_CSAZERO_PORT_MBSSID_IDX_SH 0
#define FWCMD_C2H_BCN_CSAZERO_PORT_MBSSID_IDX_MSK 0x7f
#define FWCMD_C2H_BCN_CSAZERO_BAND_IDX BIT(7)
#define FWCMD_C2H_EFUSE_DUMP_UUID0_SH 16
#define FWCMD_C2H_EFUSE_DUMP_UUID0_MSK 0xff
#define FWCMD_C2H_EFUSE_DUMP_UUID2_SH 24
#define FWCMD_C2H_EFUSE_DUMP_UUID2_MSK 0xff
#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_REMARK_SH 24
#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_REMARK_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_SH 28
#define FWCMD_C2H_EFUSE_DUMP_RX_SPATIAL_STREAM_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_HCI_TYPE_SH 0
#define FWCMD_C2H_EFUSE_DUMP_HCI_TYPE_MSK 0xf
#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_SH 8
#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_SH 12
#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_SH 16
#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_SH 20
#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN0_SH 24
#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN0_MSK 0xff
#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN1_SH 0
#define FWCMD_C2H_EFUSE_DUMP_CP_TEST_PATTEN1_MSK 0xff
#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_REMARK_80211_SH 8
#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_REMARK_80211_MSK 0x3
#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_80211_SH 10
#define FWCMD_C2H_EFUSE_DUMP_PROTOCOL_80211_MSK 0x3
#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_REMARK_SH 12
#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_REMARK_MSK 0x3
#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_SH 14
#define FWCMD_C2H_EFUSE_DUMP_NIC_ROUTER_MSK 0x3
#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_REMARK_SH 16
#define FWCMD_C2H_EFUSE_DUMP_ANT_TX_NUM_REMARK_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_REMARK_SH 20
#define FWCMD_C2H_EFUSE_DUMP_ANT_RX_NUM_REMARK_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_REMARK_SH 24
#define FWCMD_C2H_EFUSE_DUMP_BANDWIDTH_REMARK_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_REMARK_SH 28
#define FWCMD_C2H_EFUSE_DUMP_TX_SPATIAL_STREAM_REMARK_MSK 0x7
#define FWCMD_C2H_EFUSE_DUMP_WL_FUNCTION_SUPPORT_SH 0
#define FWCMD_C2H_EFUSE_DUMP_WL_FUNCTION_SUPPORT_MSK 0xf
#define FWCMD_C2H_EFUSE_DUMP_HW_SPECIAL_TYPE_SH 4
#define FWCMD_C2H_EFUSE_DUMP_HW_SPECIAL_TYPE_MSK 0xf
#define FWCMD_C2H_EFUSE_DUMP_UUID3_SH 0
#define FWCMD_C2H_EFUSE_DUMP_UUID3_MSK 0xff
#define FWCMD_C2H_EFUSE_DUMP_UUID1_SH 8
#define FWCMD_C2H_EFUSE_DUMP_UUID1_MSK 0xff
#define FWCMD_C2H_EFUSE_DUMP_PFID_SH 16
#define FWCMD_C2H_EFUSE_DUMP_PFID_MSK 0xff
#define FWCMD_C2H_READ_RSP_VALUE_LEN_SH 0
#define FWCMD_C2H_READ_RSP_VALUE_LEN_MSK 0x7ff
#define FWCMD_C2H_READ_RSP_LS BIT(15)
#define FWCMD_C2H_READ_RSP_OFLD_ID_SH 16
#define FWCMD_C2H_READ_RSP_OFLD_ID_MSK 0xff
#define FWCMD_C2H_READ_RSP_ENTRY_NUM_SH 24
#define FWCMD_C2H_READ_RSP_ENTRY_NUM_MSK 0xff
#define FWCMD_C2H_READ_RSP_OFFSET_SH 0
#define FWCMD_C2H_READ_RSP_OFFSET_MSK 0xffff
#define FWCMD_C2H_READ_RSP_START_SH 0
#define FWCMD_C2H_READ_RSP_START_MSK 0xffffffff
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_ID_SH 0
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_ID_MSK 0xff
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_OP_SH 8
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_OP_MSK 0x7
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_LENGTH_SH 16
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_LENGTH_MSK 0xffff
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_CONTENT_SH 0
#define FWCMD_C2H_PKT_OFLD_RSP_PKT_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_1_SH 0
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_1_MSK 0xffffffff
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_2_SH 0
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_2_MSK 0xffffffff
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_3_SH 0
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_3_MSK 0xffffffff
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_4_SH 0
#define FWCMD_C2H_MACID_PAUSE_STATUS_GRP_4_MSK 0xffffffff
#define FWCMD_C2H_FW_GETPKT_RPT_MACID_SH 0
#define FWCMD_C2H_FW_GETPKT_RPT_MACID_MSK 0xff
#define FWCMD_C2H_FW_GETPKT_RPT_PKT_TYPE_SH 8
#define FWCMD_C2H_FW_GETPKT_RPT_PKT_TYPE_MSK 0xf
#define FWCMD_C2H_TSF32_TOGL_RPT_BAND BIT(0)
#define FWCMD_C2H_TSF32_TOGL_RPT_PORT_SH 1
#define FWCMD_C2H_TSF32_TOGL_RPT_PORT_MSK 0x7
#define FWCMD_C2H_TSF32_TOGL_RPT_STATUS_SH 4
#define FWCMD_C2H_TSF32_TOGL_RPT_STATUS_MSK 0xfff
#define FWCMD_C2H_TSF32_TOGL_RPT_EARLY_SH 16
#define FWCMD_C2H_TSF32_TOGL_RPT_EARLY_MSK 0xffff
#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_L_SH 0
#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_L_MSK 0xffffffff
#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_H_SH 0
#define FWCMD_C2H_TSF32_TOGL_RPT_TSF_H_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_RPT_MODE_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_RPT_MODE_MSK 0x7
#define FWCMD_C2H_USR_TX_RPT_INFO_MACID_SH 8
#define FWCMD_C2H_USR_TX_RPT_INFO_MACID_MSK 0xff
#define FWCMD_C2H_USR_TX_RPT_INFO_AC_SH 16
#define FWCMD_C2H_USR_TX_RPT_INFO_AC_MSK 0x3
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BE_1K_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BE_1K_MSK 0xffff
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BK_1K_SH 16
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_BK_1K_MSK 0xffff
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VI_1K_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VI_1K_MSK 0xffff
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VO_1K_SH 16
#define FWCMD_C2H_USR_TX_RPT_INFO_PENDING_VO_1K_MSK 0xffff
#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_IN_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_IN_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_OUT_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_FIRST_OUT_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_LAST_OUT_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_FREERUN_CNT_LAST_OUT_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BE_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BE_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BK_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_BK_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VI_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VI_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VO_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_DROP_NUM_VO_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BE_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BE_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BK_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_BK_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VI_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VI_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VO_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_TX_OK_NUM_VO_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_RX_CLEAR_US_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_RX_CLEAR_US_MSK 0xffffffff
#define FWCMD_C2H_USR_TX_RPT_INFO_BUSY_US_SH 0
#define FWCMD_C2H_USR_TX_RPT_INFO_BUSY_US_MSK 0xffffffff
#define FWCMD_C2H_CMD_OFLD_RSP_RESULT BIT(0)
#define FWCMD_C2H_CMD_OFLD_RSP_CMD_NUM_SH 8
#define FWCMD_C2H_CMD_OFLD_RSP_CMD_NUM_MSK 0xff
#define FWCMD_C2H_CMD_OFLD_RSP_OFFSET_SH 0
#define FWCMD_C2H_CMD_OFLD_RSP_OFFSET_MSK 0xffffffff
#define FWCMD_C2H_CMD_OFLD_RSP_EXP_VAL_SH 0
#define FWCMD_C2H_CMD_OFLD_RSP_EXP_VAL_MSK 0xffffffff
#define FWCMD_C2H_CMD_OFLD_RSP_R_VAL_SH 0
#define FWCMD_C2H_CMD_OFLD_RSP_R_VAL_MSK 0xffffffff
#define FWCMD_C2H_SCANOFLD_RSP_CENTRAL_CH_SH 0
#define FWCMD_C2H_SCANOFLD_RSP_CENTRAL_CH_MSK 0xff
#define FWCMD_C2H_SCANOFLD_RSP_SCANNED_CH_SH 8
#define FWCMD_C2H_SCANOFLD_RSP_SCANNED_CH_MSK 0xff
#define FWCMD_C2H_SCANOFLD_RSP_NOTIFY_REASON_SH 16
#define FWCMD_C2H_SCANOFLD_RSP_NOTIFY_REASON_MSK 0xf
#define FWCMD_C2H_SCANOFLD_RSP_STATUS_SH 20
#define FWCMD_C2H_SCANOFLD_RSP_STATUS_MSK 0xf
#define FWCMD_C2H_SCANOFLD_RSP_TSF_LOW_SH 0
#define FWCMD_C2H_SCANOFLD_RSP_TSF_LOW_MSK 0xffffffff
#define FWCMD_C2H_SCANOFLD_RSP_TSF_HIGH_SH 0
#define FWCMD_C2H_SCANOFLD_RSP_TSF_HIGH_MSK 0xffffffff
#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_LOW_SH 0
#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_LOW_MSK 0xffffffff
#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_HIGH_SH 0
#define FWCMD_C2H_SCANOFLD_RSP_SPENT_TIME_HIGH_MSK 0xffffffff
#define FWCMD_C2H_TX_DUTY_RPT_TIMER_ERR_SH 0
#define FWCMD_C2H_TX_DUTY_RPT_TIMER_ERR_MSK 0x7
#define FWCMD_C2H_WAIT_ANNOUNCE_WAIT_CASE_SH 0
#define FWCMD_C2H_WAIT_ANNOUNCE_WAIT_CASE_MSK 0xf
#define FWCMD_C2H_WAIT_ANNOUNCE_MACID0_SH 8
#define FWCMD_C2H_WAIT_ANNOUNCE_MACID0_MSK 0xff
#define FWCMD_C2H_WAIT_ANNOUNCE_MACID1_SH 16
#define FWCMD_C2H_WAIT_ANNOUNCE_MACID1_MSK 0xff
#define FWCMD_C2H_WAIT_ANNOUNCE_MACID2_SH 24
#define FWCMD_C2H_WAIT_ANNOUNCE_MACID2_MSK 0xff
#define FWCMD_C2H_AOAC_REPORT_AOAC_REPORT_SH 0
#define FWCMD_C2H_AOAC_REPORT_AOAC_REPORT_MSK 0xffffffff
#define FWCMD_C2H_READ_WOW_CAM_VALUE_LEN_SH 0
#define FWCMD_C2H_READ_WOW_CAM_VALUE_LEN_MSK 0x7ff
#define FWCMD_C2H_READ_WOW_CAM_IDX_SH 24
#define FWCMD_C2H_READ_WOW_CAM_IDX_MSK 0xff
#define FWCMD_C2H_READ_WOW_CAM_WOW_CAM_SH 0
#define FWCMD_C2H_READ_WOW_CAM_WOW_CAM_MSK 0xffffffff
#define FWCMD_C2H_MCC_RCV_ACK_GROUP_SH 0
#define FWCMD_C2H_MCC_RCV_ACK_GROUP_MSK 0x3
#define FWCMD_C2H_MCC_RCV_ACK_H2C_FUNC_SH 8
#define FWCMD_C2H_MCC_RCV_ACK_H2C_FUNC_MSK 0xff
#define FWCMD_C2H_MCC_REQ_ACK_GROUP_SH 0
#define FWCMD_C2H_MCC_REQ_ACK_GROUP_MSK 0x3
#define FWCMD_C2H_MCC_REQ_ACK_H2C_RETURN_SH 2
#define FWCMD_C2H_MCC_REQ_ACK_H2C_RETURN_MSK 0x3f
#define FWCMD_C2H_MCC_REQ_ACK_H2C_FUNC_SH 8
#define FWCMD_C2H_MCC_REQ_ACK_H2C_FUNC_MSK 0xff
#define FWCMD_C2H_MCC_TSF_RPT_MACID_X_SH 0
#define FWCMD_C2H_MCC_TSF_RPT_MACID_X_MSK 0xff
#define FWCMD_C2H_MCC_TSF_RPT_MACID_Y_SH 8
#define FWCMD_C2H_MCC_TSF_RPT_MACID_Y_MSK 0xff
#define FWCMD_C2H_MCC_TSF_RPT_GROUP_SH 16
#define FWCMD_C2H_MCC_TSF_RPT_GROUP_MSK 0x3
#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_X_SH 0
#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_X_MSK 0xffffffff
#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_X_SH 0
#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_X_MSK 0xffffffff
#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_Y_SH 0
#define FWCMD_C2H_MCC_TSF_RPT_TSF_LOW_Y_MSK 0xffffffff
#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_Y_SH 0
#define FWCMD_C2H_MCC_TSF_RPT_TSF_HIGH_Y_MSK 0xffffffff
#define FWCMD_C2H_MCC_STATUS_RPT_STATUS_SH 0
#define FWCMD_C2H_MCC_STATUS_RPT_STATUS_MSK 0x3f
#define FWCMD_C2H_MCC_STATUS_RPT_GROUP_SH 6
#define FWCMD_C2H_MCC_STATUS_RPT_GROUP_MSK 0x3
#define FWCMD_C2H_MCC_STATUS_RPT_MACID_SH 8
#define FWCMD_C2H_MCC_STATUS_RPT_MACID_MSK 0xff
#define FWCMD_C2H_MCC_STATUS_RPT_TSF_LOW_SH 0
#define FWCMD_C2H_MCC_STATUS_RPT_TSF_LOW_MSK 0xffffffff
#define FWCMD_C2H_MCC_STATUS_RPT_TSF_HIGH_SH 0
#define FWCMD_C2H_MCC_STATUS_RPT_TSF_HIGH_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_WRITE_ADDR_SH 0
#define FWCMD_C2H_PLAT_FLASH_WRITE_ADDR_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_WRITE_LENGTH_SH 0
#define FWCMD_C2H_PLAT_FLASH_WRITE_LENGTH_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_ERASE_ADDR_SH 0
#define FWCMD_C2H_PLAT_FLASH_ERASE_ADDR_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_ERASE_LENGTH_SH 0
#define FWCMD_C2H_PLAT_FLASH_ERASE_LENGTH_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_READ_ADDR_SH 0
#define FWCMD_C2H_PLAT_FLASH_READ_ADDR_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_READ_LENGTH_SH 0
#define FWCMD_C2H_PLAT_FLASH_READ_LENGTH_MSK 0xffffffff
#define FWCMD_C2H_PLAT_FLASH_READ_PAYLOAD_SH 0
#define FWCMD_C2H_PLAT_FLASH_READ_PAYLOAD_MSK 0xffffffff
#define FWCMD_C2H_FCS_RPT_STATUS_SH 0
#define FWCMD_C2H_FCS_RPT_STATUS_MSK 0xffffffff
#define FWCMD_C2H_WPS_RPT_STATE_SH 0
#define FWCMD_C2H_WPS_RPT_STATE_MSK 0xff
#define FWCMD_C2H_CCXRPT_DWORD0_SH 0
#define FWCMD_C2H_CCXRPT_DWORD0_MSK 0xffffffff
#define FWCMD_C2H_CCXRPT_DWORD1_SH 0
#define FWCMD_C2H_CCXRPT_DWORD1_MSK 0xffffffff
#define FWCMD_C2H_CCXRPT_DWORD2_SH 0
#define FWCMD_C2H_CCXRPT_DWORD2_MSK 0xffffffff
#define FWCMD_C2H_CCXRPT_DWORD3_SH 0
#define FWCMD_C2H_CCXRPT_DWORD3_MSK 0xffffffff
#define FWCMD_C2H_CCXRPT_DWORD4_SH 0
#define FWCMD_C2H_CCXRPT_DWORD4_MSK 0xffffffff
#define FWCMD_C2H_CCXRPT_DWORD5_SH 0
#define FWCMD_C2H_CCXRPT_DWORD5_MSK 0xffffffff
#define FWCMD_C2H_PORT_INIT_STAT_BAND BIT(0)
#define FWCMD_C2H_PORT_INIT_STAT_PORT_SH 1
#define FWCMD_C2H_PORT_INIT_STAT_PORT_MSK 0x7
#define FWCMD_C2H_PORT_INIT_STAT_CFG_MBID_IDX_SH 8
#define FWCMD_C2H_PORT_INIT_STAT_CFG_MBID_IDX_MSK 0xff
#define FWCMD_C2H_PORT_INIT_STAT_CFG_TYPE_SH 16
#define FWCMD_C2H_PORT_INIT_STAT_CFG_TYPE_MSK 0xff
#define FWCMD_C2H_PORT_INIT_STAT_STEP_SH 24
#define FWCMD_C2H_PORT_INIT_STAT_STEP_MSK 0xff
#define FWCMD_C2H_PORT_INIT_STAT_CFG_VAL_SH 0
#define FWCMD_C2H_PORT_INIT_STAT_CFG_VAL_MSK 0xffffffff
#define FWCMD_C2H_PORT_INIT_STAT_RET_SH 0
#define FWCMD_C2H_PORT_INIT_STAT_RET_MSK 0xffffffff
#define FWCMD_C2H_PORT_CFG_STAT_BAND BIT(0)
#define FWCMD_C2H_PORT_CFG_STAT_PORT_SH 1
#define FWCMD_C2H_PORT_CFG_STAT_PORT_MSK 0x7
#define FWCMD_C2H_PORT_CFG_STAT_MBSSID_IDX_SH 8
#define FWCMD_C2H_PORT_CFG_STAT_MBSSID_IDX_MSK 0xff
#define FWCMD_C2H_PORT_CFG_STAT_TYPE_SH 16
#define FWCMD_C2H_PORT_CFG_STAT_TYPE_MSK 0xff
#define FWCMD_C2H_PORT_CFG_STAT_VAL_SH 0
#define FWCMD_C2H_PORT_CFG_STAT_VAL_MSK 0xffffffff
#define FWCMD_C2H_PORT_CFG_STAT_RET_SH 0
#define FWCMD_C2H_PORT_CFG_STAT_RET_MSK 0xffffffff
#define FWCMD_C2H_OFDMA_STS_TFSTS_USER_NUM_SH 0
#define FWCMD_C2H_OFDMA_STS_TFSTS_USER_NUM_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_RU_SU_PER_SH 8
#define FWCMD_C2H_OFDMA_STS_TFSTS_RU_SU_PER_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_MACID_SH 0
#define FWCMD_C2H_OFDMA_STS_TFSTS_MACID_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_RATE_SH 8
#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_RATE_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_FAIL_PER_SH 16
#define FWCMD_C2H_OFDMA_STS_TFSTS_TB_FAIL_PER_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_RSSI_SH 24
#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_RSSI_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_CCA_MISS_PER_SH 0
#define FWCMD_C2H_OFDMA_STS_TFSTS_CCA_MISS_PER_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_UPH_SH 8
#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_UPH_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_MINFLAG_PER_SH 16
#define FWCMD_C2H_OFDMA_STS_TFSTS_MINFLAG_PER_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_EVM_SH 24
#define FWCMD_C2H_OFDMA_STS_TFSTS_AVG_TB_EVM_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_TFSTS_TF_NUM_SH 0
#define FWCMD_C2H_OFDMA_STS_TFSTS_TF_NUM_MSK 0xffffffff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_USER_NUM_SH 0
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_USER_NUM_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_RU_RATIO_SH 8
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_RU_RATIO_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_RU_FAIL_RATIO_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_RU_FAIL_RATIO_SH 16
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_FAIL_RATIO_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_TOTAL_SU_FAIL_RATIO_SH 24
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_MACID_SH 0
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_MACID_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_RU_RATIO_SH 8
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_RU_RATIO_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_FAIL_SH 16
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_SU_FAIL_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_FAIL_SH 24
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_FAIL_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_AVG_AGG_SH 0
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_AVG_AGG_MSK 0xff
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_RATE_SH 8
#define FWCMD_C2H_OFDMA_STS_DLRUSTS_RU_RATE_MSK 0xff
//
//C2HPKT - CAT(OutSrc, Phydm)
//
#define C2H_HDR_CAT_SH 0
#define C2H_HDR_CAT_MSK 0x3
#define C2H_HDR_CLASS_SH 2
#define C2H_HDR_CLASS_MSK 0x3f
#define C2H_HDR_FUNC_SH 8
#define C2H_HDR_FUNC_MSK 0xff
#define C2H_HDR_DEL_TYPE_SH 16
#define C2H_HDR_DEL_TYPE_MSK 0xf
#define C2H_HDR_C2H_SEQ_SH 24
#define C2H_HDR_C2H_SEQ_MSK 0xff
#define C2H_HDR_TOTAL_LEN_SH 0
#define C2H_HDR_TOTAL_LEN_MSK 0x3fff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
//
//C2HPKT - CAT(OutSrc, RF)
//
#define C2H_HDR_CAT_SH 0
#define C2H_HDR_CAT_MSK 0x3
#define C2H_HDR_CLASS_SH 2
#define C2H_HDR_CLASS_MSK 0x3f
#define C2H_HDR_FUNC_SH 8
#define C2H_HDR_FUNC_MSK 0xff
#define C2H_HDR_DEL_TYPE_SH 16
#define C2H_HDR_DEL_TYPE_MSK 0xf
#define C2H_HDR_C2H_SEQ_SH 24
#define C2H_HDR_C2H_SEQ_MSK 0xff
#define C2H_HDR_TOTAL_LEN_SH 0
#define C2H_HDR_TOTAL_LEN_MSK 0x3fff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
//
//C2HPKT - CAT(OutSrc, BTC)
//
#define C2H_HDR_CAT_SH 0
#define C2H_HDR_CAT_MSK 0x3
#define C2H_HDR_CLASS_SH 2
#define C2H_HDR_CLASS_MSK 0x3f
#define C2H_HDR_FUNC_SH 8
#define C2H_HDR_FUNC_MSK 0xff
#define C2H_HDR_DEL_TYPE_SH 16
#define C2H_HDR_DEL_TYPE_MSK 0xf
#define C2H_HDR_C2H_SEQ_SH 24
#define C2H_HDR_C2H_SEQ_MSK 0xff
#define C2H_HDR_TOTAL_LEN_SH 0
#define C2H_HDR_TOTAL_LEN_MSK 0x3fff
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_SH 0
#define FWCMD_C2H_EXAMPLE_EXAMPLE_CONTENT_MSK 0xffffffff
// struct for halmac//
struct fwcmd_hdr {
u32 hdr0;
u32 hdr1;
};
//
//H2CREG
//
struct fwcmd_h2creg_hdr {
u32 dword0;
};
struct fwcmd_h2creg {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_h2creg_lb {
u32 dword0;
u32 dword1;
};
struct fwcmd_cnsl_cmd {
u32 dword0;
};
struct fwcmd_fwerr {
u32 dword0;
u32 dword1;
};
struct fwcmd_hidden_get {
u32 dword0;
};
struct fwcmd_getpkt_inform {
u32 dword0;
};
struct fwcmd_sch_tx_en {
u32 dword0;
u32 dword1;
};
struct fwcmd_wow_trx_stop {
u32 dword0;
};
//
//C2HREG
//
struct fwcmd_c2hreg_hdr {
u32 dword0;
};
struct fwcmd_c2hreg {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_c2hreg_lb {
u32 dword0;
u32 dword1;
};
struct fwcmd_err_rpt {
u32 dword0;
u32 dword1;
};
struct fwcmd_err_msg {
u32 dword0;
};
struct fwcmd_efuse_hidden {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_tx_pause_rpt {
u32 dword0;
};
struct fwcmd_aoac_rpt_1 {
u32 dword0;
};
struct fwcmd_aoac_rpt_2 {
u32 dword0;
};
struct fwcmd_aoac_rpt_3 {
u32 dword0;
};
struct fwcmd_io_ofld_result {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
//
//H2CPKT - CAT(TEST)
//
struct fwcmd_h2c_lb {
u32 dword0;
u32 dword1;
};
struct fwcmd_plat_spic_test {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
struct fwcmd_plat_fl_write {
u32 dword0;
u32 dword1;
};
struct fwcmd_plat_fl_erase {
u32 dword0;
u32 dword1;
};
struct fwcmd_pl_flash_read {
u32 dword0;
u32 dword1;
};
struct fwcmd_long_run {
u32 dword0;
u32 dword1;
};
struct fwcmd_lps_test {
u32 dword0;
};
struct fwcmd_lps_onoff_test {
u32 dword0;
u32 dword1;
};
struct fwcmd_fw_status {
u32 dword0;
};
//
//H2CPKT - CAT(MAC)
//
struct fwcmd_log_cfg {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_general_pkt {
u32 dword0;
u32 dword1;
};
struct fwcmd_c2h_rpt_cfg {
u32 dword0;
u32 dword1;
};
struct fwcmd_wlan_dump_cmd {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_fw_dbgreg_cfg {
u32 dword0;
};
struct fwcmd_keep_alive {
u32 dword0;
};
struct fwcmd_disconnect_detect {
u32 dword0;
u32 dword1;
};
struct fwcmd_wow_global {
u32 dword0;
u32 dword1;
};
struct fwcmd_gtk_ofld {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_arp_ofld {
u32 dword0;
u32 dword1;
};
struct fwcmd_ndp_ofld {
u32 dword0;
u32 dword1;
};
struct fwcmd_realwow {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_nlo {
u32 dword0;
u32 dword1;
};
struct fwcmd_wakeup_ctrl {
u32 dword0;
};
struct fwcmd_negative_pattern {
u32 dword0;
u32 dword1;
};
struct fwcmd_dev2hst_gpio {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
};
struct fwcmd_uphy_ctrl {
u32 dword0;
};
struct fwcmd_wow_cam_upd {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
struct fwcmd_aoac_report_req {
u32 dword0;
};
struct fwcmd_wow_stop_fw_trx {
u32 dword0;
};
struct fwcmd_lps_parm {
u32 dword0;
u32 dword1;
};
struct fwcmd_p2p_act {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
};
struct fwcmd_p2p_macid_ctrl {
u32 dword0;
u32 dword1;
};
struct fwcmd_ips_parm {
u32 dword0;
};
struct fwcmd_fwhdr_dl {
u32 dword0;
};
struct fwcmd_fwhdr_redl {
u32 dword0;
};
struct fwcmd_twt_announce_upd {
u32 dword0;
};
struct fwcmd_twtinfo_upd {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_twt_stansp_upd {
u32 dword0;
};
struct fwcmd_tblud {
u32 dword0;
};
struct fwcmd_dctlinfo_ud {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
};
struct fwcmd_cctlinfo_ud {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
u32 dword15;
u32 dword16;
};
struct fwcmd_shcut_update {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
};
struct fwcmd_bcn_upd {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_ss_ulsta_upd {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_f2pdbg_set {
u32 dword0;
};
struct fwcmd_wlaninfo_get {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_addrcam_info {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
};
struct fwcmd_joininfo {
u32 dword0;
};
struct fwcmd_dl_grp_upd {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_ul_grp_upd {
u32 dword0;
};
struct fwcmd_mu_sta_upd {
u32 dword0;
u32 dword1;
};
struct fwcmd_fwrole_maintain {
u32 dword0;
};
struct fwcmd_dump_efuse {
u32 dword0;
};
struct fwcmd_packet_ofld {
u32 dword0;
u32 dword1;
};
struct fwcmd_read_ofld {
u32 dword0;
u32 dword1;
};
struct fwcmd_write_ofld {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_conf_ofld {
u32 dword0;
u32 dword1;
};
struct fwcmd_sys_init {
u32 dword0;
};
struct fwcmd_trx_init {
u32 dword0;
};
struct fwcmd_intf_init {
u32 dword0;
};
struct fwcmd_macid_pause {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
};
struct fwcmd_rx_fwd {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
};
struct fwcmd_en_mac_hdr_conv {
u32 dword0;
};
struct fwcmd_set_hwseq_reg {
u32 dword0;
};
struct fwcmd_hwamsdu_reg {
u32 dword0;
};
struct fwcmd_amsdu_cut_reg {
u32 dword0;
};
struct fwcmd_tcpip_chksum_offload_reg {
u32 dword0;
};
struct fwcmd_usr_edca {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_tsf32_togl {
u32 dword0;
};
struct fwcmd_cmd_ofld_reg {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_usr_tx_rpt {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_cmd_ofld_pkt {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_ofld_cfg {
u32 dword0;
u32 dword1;
};
struct fwcmd_h2c_agg {
u32 dword0;
};
struct fwcmd_add_scanofld_ch {
u32 dword0;
};
struct fwcmd_scanofld {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
};
struct fwcmd_tx_duty {
u32 dword0;
u32 dword1;
};
struct fwcmd_disable_rf {
u32 dword0;
};
struct fwcmd_seccam_info {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
struct fwcmd_set_snd_para {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
u32 dword15;
u32 dword16;
u32 dword17;
u32 dword18;
u32 dword19;
u32 dword20;
u32 dword21;
u32 dword22;
u32 dword23;
u32 dword24;
u32 dword25;
u32 dword26;
u32 dword27;
u32 dword28;
u32 dword29;
u32 dword30;
u32 dword31;
u32 dword32;
u32 dword33;
u32 dword34;
u32 dword35;
u32 dword36;
u32 dword37;
u32 dword38;
u32 dword39;
u32 dword40;
u32 dword41;
u32 dword42;
u32 dword43;
u32 dword44;
u32 dword45;
u32 dword46;
u32 dword47;
u32 dword48;
u32 dword49;
u32 dword50;
u32 dword51;
u32 dword52;
u32 dword53;
u32 dword54;
u32 dword55;
u32 dword56;
u32 dword57;
u32 dword58;
u32 dword59;
u32 dword60;
u32 dword61;
u32 dword62;
u32 dword63;
u32 dword64;
u32 dword65;
u32 dword66;
u32 dword67;
u32 dword68;
u32 dword69;
u32 dword70;
u32 dword71;
u32 dword72;
u32 dword73;
u32 dword74;
u32 dword75;
u32 dword76;
u32 dword77;
};
struct fwcmd_get_csi_buf {
u32 dword0;
};
struct fwcmd_set_csi_buf {
u32 dword0;
u32 dword1;
};
struct fwcmd_get_snd_sts {
u32 dword0;
};
struct fwcmd_set_snd_sts {
u32 dword0;
};
struct fwcmd_init_snd_mer {
u32 dword0;
};
struct fwcmd_init_snd_mee {
u32 dword0;
};
struct fwcmd_csi_fix_rate {
u32 dword0;
};
struct fwcmd_csi_rrsc {
u32 dword0;
u32 dword1;
};
struct fwcmd_set_mu_table {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
};
struct fwcmd_set_csi_para_reg {
u32 dword0;
};
struct fwcmd_hw_snd_pr {
u32 dword0;
};
struct fwcmd_set_snd_para_v1 {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
u32 dword15;
u32 dword16;
u32 dword17;
u32 dword18;
u32 dword19;
u32 dword20;
u32 dword21;
u32 dword22;
u32 dword23;
u32 dword24;
u32 dword25;
u32 dword26;
u32 dword27;
u32 dword28;
u32 dword29;
u32 dword30;
u32 dword31;
u32 dword32;
u32 dword33;
u32 dword34;
u32 dword35;
u32 dword36;
u32 dword37;
u32 dword38;
u32 dword39;
u32 dword40;
u32 dword41;
u32 dword42;
u32 dword43;
u32 dword44;
u32 dword45;
u32 dword46;
u32 dword47;
u32 dword48;
u32 dword49;
u32 dword50;
u32 dword51;
u32 dword52;
u32 dword53;
u32 dword54;
u32 dword55;
u32 dword56;
u32 dword57;
u32 dword58;
u32 dword59;
u32 dword60;
u32 dword61;
u32 dword62;
u32 dword63;
u32 dword64;
u32 dword65;
u32 dword66;
u32 dword67;
u32 dword68;
u32 dword69;
u32 dword70;
u32 dword71;
u32 dword72;
u32 dword73;
u32 dword74;
u32 dword75;
u32 dword76;
u32 dword77;
u32 dword78;
u32 dword79;
u32 dword80;
u32 dword81;
u32 dword82;
u32 dword83;
u32 dword84;
u32 dword85;
u32 dword86;
u32 dword87;
u32 dword88;
u32 dword89;
u32 dword90;
u32 dword91;
u32 dword92;
u32 dword93;
u32 dword94;
u32 dword95;
u32 dword96;
u32 dword97;
u32 dword98;
u32 dword99;
u32 dword100;
u32 dword101;
u32 dword102;
u32 dword103;
};
struct fwcmd_ba_cam {
u32 dword0;
u32 dword1;
};
struct fwcmd_ie_cam {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_add_mcc {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_start_mcc {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_stop_mcc {
u32 dword0;
};
struct fwcmd_del_mcc_group {
u32 dword0;
};
struct fwcmd_reset_mcc_group {
u32 dword0;
};
struct fwcmd_mcc_req_tsf {
u32 dword0;
};
struct fwcmd_mcc_macid_bitmap {
u32 dword0;
u32 dword1;
};
struct fwcmd_mcc_sync {
u32 dword0;
};
struct fwcmd_mcc_set_duration {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
};
struct fwcmd_scsi_tx {
u32 dword0;
};
struct fwcmd_usb_switch {
u32 dword0;
};
struct fwcmd_plat_flash_write {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_plat_flash_erase {
u32 dword0;
u32 dword1;
};
struct fwcmd_plat_flash_read {
u32 dword0;
u32 dword1;
};
struct fwcmd_fcs {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
struct fwcmd_cfg_wps {
u32 dword0;
};
struct fwcmd_port_init {
u32 dword0;
u32 dword1;
};
struct fwcmd_port_cfg {
u32 dword0;
u32 dword1;
};
//
//H2CPKT - CAT(Table)
//
struct fwcmd_mude_para_tblud {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_mudecision_para {
u32 dword0;
u32 dword1;
};
struct fwcmd_mu_fixinfo {
u32 dword0;
u32 dword1;
};
struct fwcmd_ul_fixinfo_tblud {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
u32 dword15;
u32 dword16;
};
struct fwcmd_ul_fixinfo {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
u32 dword15;
};
struct fwcmd_ul_fixinfo_sta_info {
u32 dword0;
};
struct fwcmd_ul_fixinfo_ul_rua_sta_ent {
u32 dword0;
u32 dword1;
};
struct fwcmd_addr_cam {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
};
struct fwcmd_bssid_cam {
u32 dword0;
u32 dword1;
};
struct fwcmd_sec_cam {
u32 dword0;
};
struct fwcmd_fixmode_para_tblud {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_fixmode_para {
u32 dword0;
u32 dword1;
};
struct fwcmd_write_ofld_req {
u32 dword0;
u32 dword1;
};
struct fwcmd_read_ofld_req {
u32 dword0;
u32 dword1;
};
struct fwcmd_conf_ofld_req_cmd {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_dctrl {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_cctrl {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
};
struct fwcmd_ie_cam_info {
u32 dword0;
u32 dword1;
};
struct fwcmd_plat_auto_test {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
};
struct fwcmd_h2creg_sch_tx_pause {
u32 dword0;
u32 dword1;
};
struct fwcmd_cmd_ofld {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
//
//H2CPKT - CAT(OutSrc,Phydm)
//
struct fwcmd_example {
u32 dword0;
};
struct fwcmd_macid_cfg {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_rssi_ra_config {
u32 dword0;
u32 dword1;
u32 dword2;
};
//
//H2CPKT - CAT(OutSrc, RF)
//
//
//H2CPKT - CAT(OutSrc, BTC)
//
struct fwcmd_tdma {
u32 dword0;
};
//
//C2HPKT - CAT(TEST)
//
struct fwcmd_c2h_lb {
u32 dword0;
};
struct fwcmd_test_phy_rpt {
u32 dword0;
};
struct fwcmd_spic {
u32 dword0;
u32 dword1;
};
struct fwcmd_spic2 {
u32 dword0;
u32 dword1;
};
//
//C2HPKT - CAT(MAC)
//
struct fwcmd_rec_ack {
u32 dword0;
};
struct fwcmd_done_ack {
u32 dword0;
};
struct fwcmd_c2h_log {
u32 dword0;
};
struct fwcmd_bcn_cnt {
u32 dword0;
u32 dword1;
};
struct fwcmd_bcn_csazero {
u32 dword0;
};
struct fwcmd_efuse_dump {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
};
struct fwcmd_read_rsp {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_pkt_ofld_rsp {
u32 dword0;
u32 dword1;
};
struct fwcmd_fw_getpkt_rpt {
u32 dword0;
};
struct fwcmd_tsf32_togl_rpt {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_usr_tx_rpt_info {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
u32 dword12;
u32 dword13;
u32 dword14;
u32 dword15;
};
struct fwcmd_cmd_ofld_rsp {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
struct fwcmd_scanofld_rsp {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
};
struct fwcmd_tx_duty_rpt {
u32 dword0;
};
struct fwcmd_wait_announce {
u32 dword0;
};
struct fwcmd_aoac_report {
u32 dword0;
};
struct fwcmd_read_wow_cam {
u32 dword0;
u32 dword1;
};
struct fwcmd_mcc_rcv_ack {
u32 dword0;
};
struct fwcmd_mcc_req_ack {
u32 dword0;
};
struct fwcmd_mcc_tsf_rpt {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
};
struct fwcmd_mcc_status_rpt {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_rx_dbg {
u32 dword0;
};
struct fwcmd_scsi_rx {
u32 dword0;
};
struct fwcmd_fcs_rpt {
u32 dword0;
};
struct fwcmd_wps_rpt {
u32 dword0;
};
struct fwcmd_ccxrpt {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
struct fwcmd_port_init_stat {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_port_cfg_stat {
u32 dword0;
u32 dword1;
u32 dword2;
};
struct fwcmd_notify_dbcc {
u32 dword0;
};
//
//C2HPKT - CAT(OutSrc, Phydm)
//
//
//C2HPKT - CAT(OutSrc, RF)
//
//
//C2HPKT - CAT(OutSrc, BTC)
//
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/fw_ax/inc_hdr/fwcmd_intf.h
|
C
|
agpl-3.0
| 237,527
|
/******************************************************************************
*
* Copyright(c) 2012 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifdef CONFIG_RTL8852B
#ifdef PHL_FEATURE_NIC
#ifdef MAC_FW_8852B_U2
extern u8 array_8852b_u2_nic[273880];
extern u32 array_length_8852b_u2_nic;
#endif /*MAC_FW_8852B_U2*/
#ifdef CONFIG_WOWLAN
#ifdef MAC_FW_8852B_U2
extern u8 array_8852b_u2_wowlan[225064];
extern u32 array_length_8852b_u2_wowlan;
#endif /*MAC_FW_8852B_U2*/
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
#endif /*CONFIG_RTL8852B*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw.h
|
C
|
agpl-3.0
| 1,065
|
/******************************************************************************
*
* Copyright(c) 2012 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "./hal8852b_fw_log.h"
struct mac_fw_msg fw_log_8852b[] = {
{MSG_8852B_FIRST, "RESERVED"},
{MSG_8852B_SAMPLE_NO_PARAMETER, "Sample without parameter.\n"},
{MSG_8852B_SAMPLE_PARAMETER, "Sample string:%s.\n"},
{MSG_8852B_SAMPLE_INTEGER, "Sample integer:%d.\n"},
{MSG_8852B_SAMPLE_INTEGER_X, "Sample integer:0x%x.\n"},
{MSG_8852B_SAMPLE_INTEGER_2, "Sample integer1:%d, integer2:%d.\n"},
{MSG_8852B_FCUN_NAME, "%s()\n"},
{MSG_8852B_MAIN_1, "FW from host\n"},
{MSG_8852B_MAIN_2, "Skip DL FW handler\n"},
{MSG_8852B_MAIN_3, "FW from flash\n"},
{MSG_8852B_MAIN_4, "Invalid boot mode\n"},
{MSG_8852B_FWDLHDL_1, "Invalid boot reason\n"},
{MSG_8852B_FWDLHDL_2, "Enter DL FW handler\n"},
{MSG_8852B_FWDLHDL_3, "FWHDR H2C done\n"},
{MSG_8852B_FLASHBOOT, "Enter flash FW loader\n"},
{MSG_8852B_IRAMENTRN, "Load FW RAM code OK\n"},
{MSG_8852B_FIRSTH2C_1, "First H2C Enqueue\n"},
{MSG_8852B_FIRSTH2C_2, "H2C node malloc fail\n"},
{MSG_8852B_FIRSTH2C_3, "H2C node content malloc fail\n"},
{MSG_8852B_H2CDEQ_1, "H2C Dequeue\n"},
{MSG_8852B_H2CDEQ_2, "H2CPKT enqueue fail\n"},
{MSG_8852B_H2CPKT_1, "content = 0x%x 0x%x 0x%x 0x%x\n"},
{MSG_8852B_RESERVED_ROM, "RESERVED"},
{MSG_8852B_CMDTABLE_NAME, "%s "},
{MSG_8852B_CMDTABLE_1, " ?\n"},
{MSG_8852B_CMDTABLE_2, " dump bytes, ex: DB 0xb8e00000\n"},
{MSG_8852B_CMDTABLE_3, " write bytes, ex: EB 0xb8e00000 0x1\n"},
{MSG_8852B_CMDTABLE_4, " dump words, ex: DW 0xb8e00000\n"},
{MSG_8852B_CMDTABLE_5, " write words, ex: EW 0xb8e00000, 0x12345678\n"},
{MSG_8852B_CMDTABLE_6, " jump to address, ex: j 0xb8900000\n"},
{MSG_8852B_CMDTABLE_7, " set debug level\n"},
{MSG_8852B_CMDTABLE_8, " set debug compoment bitmap\n"},
{MSG_8852B_CMDTABLE_9, " show task info\n"},
{MSG_8852B_CMDTABLE_10, " show heap info\n"},
{MSG_8852B_CMDTABLE_11, " show dynamic allocate memory info, <index>, <mode>\n"},
{MSG_8852B_CMDTABLE_12, " show task time state\n"},
{MSG_8852B_CMDTABLE_13, " AXIDMA test\n"},
{MSG_8852B_CMDTABLE_14, " SPIC test\n"},
{MSG_8852B_CMDTABLE_15, " IDDMA test\n"},
{MSG_8852B_CMDTABLE_16, " RXI300 test\n"},
{MSG_8852B_CMDTABLE_17, " DLE test\n"},
{MSG_8852B_CMDTABLE_18, " HIOE test\n"},
{MSG_8852B_CMDTABLE_19, " RPT test\n"},
{MSG_8852B_CMDTABLE_20, " MISC test\n"},
{MSG_8852B_CMDTABLE_21, " Update STA para for F2PTXCMD\n"},
{MSG_8852B_CMDTABLE_22, " Update Common para for F2PTXCMD\n"},
{MSG_8852B_CMDTABLE_23, " Wlan Flow Test\n"},
{MSG_8852B_CMDTABLE_24, " Wlan Test Mode Setting\n"},
{MSG_8852B_CMDTABLE_25, " Wlan Flow with RUA Test\n"},
{MSG_8852B_CMDTABLE_26, " Wlan UL Flow Test\n"},
{MSG_8852B_CMDTABLE_27, " IPSec test\n"},
{MSG_8852B_CMDTABLE_28, " CryptoSig test\n"},
{MSG_8852B_CMDTABLE_29, " SecureBoot test\n"},
{MSG_8852B_CMDTABLE_30, " Secure eFuse R/W test\n"},
{MSG_8852B_CMDTABLE_31, " Plat test\n"},
{MSG_8852B_CMDTABLE_32, " H2C/C2H test\n"},
{MSG_8852B_CMDTABLE_33, " UL F2PCMD test, <number of STAs>, <frame exchange type>, 0\n"},
{MSG_8852B_CMDTABLE_34, " Sounding test\n"},
{MSG_8852B_CMDTABLE_35, " security CAM test\n"},
{MSG_8852B_CMDTABLE_36, " Gtimer test, <id>, <mode>, <unit>, <duration>\n"},
{MSG_8852B_CMDTABLE_37, " PStimer test, <band>, <id>, <mode>, <tsf> (valid if mode = 0)\n"},
{MSG_8852B_CMDTABLE_38, " RPWM test\n"},
{MSG_8852B_CMDTABLE_39, " DLTXD test\n"},
{MSG_8852B_CMDTABLE_40, " PS test\n"},
{MSG_8852B_CMDTABLE_41, " 32K CAL test\n"},
{MSG_8852B_CMDTABLE_42, " WoW CAM test\n"},
{MSG_8852B_CMDTABLE_43, " PS ONOFF test\n"},
{MSG_8852B_CMDTABLE_44, " BTCoex test\n"},
{MSG_8852B_CMDTABLE_45, " DL Parameters Setting\n"},
{MSG_8852B_CMDTABLE_46, " Dump Wlan common info, f2pcmd result, decision result\n"},
{MSG_8852B_CMDTABLE_47, " Dump Wlan sta or muru grp info\n"},
{MSG_8852B_CMDTABLE_48, " Dump Wlan decision info\n"},
{MSG_8852B_CMDTABLE_49, " Dump FW info\n"},
{MSG_8852B_CMDTABLE_50, " TFDBG\n"},
{MSG_8852B_CMDTABLE_51, " CRT\n"},
{MSG_8852B_MALLOC_F, "malloc is failed\n"},
{MSG_8852B_STRING_0, "%s\n"},
{MSG_8852B_STRING_1, "%s"},
{MSG_8852B_PARA_INVALID, "Invalid parameters\n"},
{MSG_8852B_CMD_UNKNOWN, "Unknown cmd\n"},
{MSG_8852B_CONSOLE_1, "- CMD -\n"},
{MSG_8852B_CONSOLE_2, "0x%x: 0x%x\n"},
{MSG_8852B_CONSOLE_3, "Jump to 0x%x\n"},
{MSG_8852B_CONSOLE_4, "Set dbg level to: 0x%x\n"},
{MSG_8852B_CONSOLE_5, "Set dbg component bitmap to: 0x%x\n"},
{MSG_8852B_CONSOLE_6, "Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\tCnt\n"},
{MSG_8852B_CONSOLE_7, "--------------------------------------------------------------------------------\n"},
{MSG_8852B_CONSOLE_8, "Index\t\tStart\t\tTotal(B)\tFree(B)\tMin Free(B)\n"},
{MSG_8852B_CONSOLE_9, "------------------------------------------------------------------------\n"},
{MSG_8852B_CONSOLE_10, "Address\t\tOwner ID\tFunction\tType\t\tSize(B)\n"},
{MSG_8852B_CONSOLE_11, "Owner ID\tFunction\tType\t\tCounter\t\tTotalSize(B)\tHistorical High\n"},
{MSG_8852B_CONSOLE_12, "------------------------------------------------------------------------------------------------\n"},
{MSG_8852B_CONSOLE_13, "Owner ID\tType\t\tTotalSize(B)\n"},
{MSG_8852B_CONSOLE_14, "------------------------------------------------\n"},
{MSG_8852B_MCC_SEARCHMACID_1, "[MCC] pmcc_info is NULL!\n"},
{MSG_8852B_MCC_SEARCHMACID_2, "[MCC] pgroup_list is empty!\n"},
{MSG_8852B_MCC_STATUSRPTHDL_1, "[MCC] MCCStatusRptHDL macid: %d, group: %d, status: %d\n"},
{MSG_8852B_MCC_STATUSRPTHDL_2, "[MCC] tsf: 0x%x 0x%x\n"},
{MSG_8852B_MCC_TBTTSTATUSRPTHDL, "[MCC] B%dP%d TBTT TSF = 0x%x\n"},
{MSG_8852B_MCC_MACIDDROP, "[MCC] MACIDTxIdleCheck fail\n"},
{MSG_8852B_MCC_ISSUENULLWOLPS_1, "[MCC][%d][CXEVNT_ENULL]\n"},
{MSG_8852B_MCC_ISSUENULLWOLPS_2, "[MCC] Issue null %d fail!!!\n"},
{MSG_8852B_MCC_ISSUENULL_1, "[MCC] macid %d role not found\n"},
{MSG_8852B_MCC_ISSUENULL_2, "[MCC][%d]Macid %d Null %d, TSF = 0x%x, freerun = 0x%x\n"},
{MSG_8852B_MCC_TXNULLCHK_1, "[MCC] mcc group not found\n"},
{MSG_8852B_MCC_TXNULLCHK_2, "[MCC] take semaphore fail!\n"},
{MSG_8852B_MCC_TXNULLCHK_3, "[MCC][%d]Macid %d TxNull %d SUCCESS, freerun = 0x%x\n"},
{MSG_8852B_MCC_TXNULLCHK_4, "[MCC][%d]Macid %d TxNull %d FAIL, freerun = 0x%x\n"},
{MSG_8852B_MCC_SENDNULLCB_1, "[MCC][RPT] MACID DROP => macid (%d)\n"},
{MSG_8852B_MCC_SENDNULLCB_2, "[MCC][RPT] LIFE DROP => macid (%d)\n"},
{MSG_8852B_MCC_SENDNULLCB_3, "[MCC][RPT] invalid RPT (%d)\n"},
{MSG_8852B_MCC_SWITCHCH_1, "[MCC] cfg ch FAIL!!!\n"},
{MSG_8852B_MCC_SWITCHCH_2, "[MCC] CH SW, CH= %d\n"},
{MSG_8852B_MCC_SWITCHCH_3, "[MCC] CH SW WARNING (%d)\n"},
{MSG_8852B_MCC_SWITCHCH_4, "[MCC] RFK bypass\n"},
{MSG_8852B_MCC_CHANGEROLE_1, "[MCC] MCCMacidDrop fail\n"},
{MSG_8852B_MCC_CHANGEROLE_2, "[MCC](courtesy)macid %d => macid %d\n"},
{MSG_8852B_MCC_CHANGEROLE_3, "[MCC][%d][CXEVNT_EBT]\n"},
{MSG_8852B_MCC_CHANGEROLE_4, "[MCC][%d][CXEVNT_E5G]\n"},
{MSG_8852B_MCC_CHANGEROLE_5, "[MCC][%d][CXEVNT_E2G]\n"},
{MSG_8852B_MCC_CHANGEROLE_6, "[MCC][%d]Start BT TSF = 0x%x, freerun = 0x%x\n"},
{MSG_8852B_MCC_CHANGEROLE_7, "[MCC][%d]Start macid %d TSF = 0x%x, freerun = 0x%x\n"},
{MSG_8852B_MCC_CHANGEROLE_8, "[MCC] MCCMacidDropRel fail\n"},
{MSG_8852B_MCC_FIRSTDURATIONENDHDL_1, "[MCC] First duration running\n"},
{MSG_8852B_MCC_FIRSTDURATIONENDHDL_2, "[MCC][REP/STP] act: %d, deal with old schedule now...\n"},
{MSG_8852B_MCC_FIRSTDURATIONENDHDL_3, "[MCC] MCCGroupStop fail\n"},
{MSG_8852B_MCC_FIRSTDURATIONENDHDL_4, "[MCC] MCCGroupDel fail\n"},
{MSG_8852B_MCC_GROUPSTOP_1, "[MCC] FirstDuration timer del!\n"},
{MSG_8852B_MCC_GROUPSTOP_2, "[MCC] replace/pause mode, FirstDuration del bypass!\n"},
{MSG_8852B_MCC_NEWDURATIONHDL, "[MCC] Set duration\n"},
{MSG_8852B_MCC_BITMAPCMP_1, "[MCC] Release macid %d\n"},
{MSG_8852B_MCC_BITMAPCMP_2, "[MCC] Pause macid %d\n"},
{MSG_8852B_MCC_H2CADDMCCHDL_1, "[MCC] Add MCC macid %d to group %d\n"},
{MSG_8852B_MCC_H2CADDMCCHDL_2, "[MCC] macid: %d, duration: %d, bt_in_2g: %d\n"},
{MSG_8852B_MCC_H2CADDMCCHDL_3, "[MCC] Add MCC band %d port %d\n"},
{MSG_8852B_MCC_H2CSTARTMCCHDL_1, "[MCC] Start MCC group %d from macid %d\n"},
{MSG_8852B_MCC_H2CSTARTMCCHDL_2, "[MCC][REP/STP] Group new idx: %d, old idx: %d, act: %d\n"},
{MSG_8852B_MCC_H2CSTOPMCCHDL_1, "[MCC][stop]prev_groups: %d\n"},
{MSG_8852B_MCC_H2CSTOPMCCHDL_2, "[MCC][stop]stop group %d fail\n"},
{MSG_8852B_MCC_H2CSTOPMCCHDL_3, "[MCC][stop]group %d stop!\n"},
{MSG_8852B_MCC_H2CDELMCCGROUPHDL_1, "[MCC][Del] prev_groups: %d\n"},
{MSG_8852B_MCC_H2CDELMCCGROUPHDL_2, "[MCC][del]del group %d fail\n"},
{MSG_8852B_MCC_H2CDELMCCGROUPHDL_3, "[MCC][del]group %d del!\n"},
{MSG_8852B_MCC_H2CMCCREQTSFHDL_1, "[MCC] macid %d is not in role table\n"},
{MSG_8852B_DEBUGINFO_1, "ISR Name\tCount\t\tExec Time(historical high)\n"},
{MSG_8852B_DEBUGINFO_2, "------------------------------------------------\n"},
{MSG_8852B_DEBUGINFO_3, "\t%d\t\t%d_%d\n"},
{MSG_8852B_DEBUGINFO_4, "\t\t%d\t\t%d_%d\n"},
{MSG_8852B_DEBUGINFO_5, "[Error] ISRInfo len = %d!\n"},
{MSG_8852B_PROFILING_1, "func_name %s , "},
{MSG_8852B_PROFILING_2, "line %d , cycle %d , offset = %d\n"},
{MSG_8852B_WLANDUMP_0, "Tx ok packet cnt: %d\n Tx fail packet cnt: %d\n Txcmd success cnt: %d\n Txcmd abort (MU-RTS/RTS fail) cnt: %d\n Txcmd abort (over SP) cnt: %d\n"},
{MSG_8852B_WLANDUMP_1, "Txcmd sounding abort cnt: %d\n Txcmd abort (pri user fail) cnt: %d\n Txcmd abort ( cca or medium busy) cnt: %d\n Txcmd RU/MU2SU cnt: %d\n"},
{MSG_8852B_WLANDUMP_2, "chkcmd_sts cnt: %d %d %d %d %d %d\n"},
{MSG_8852B_WLANDUMP_3, "TBD"},
{MSG_8852B_WLANDUMP_4, "DL Txcmd in last TXOP cnt: %d\n UL Txcmd in last TXOP cnt: %d\n Empty DL SS2F report cnt: %d\n Empty UL SS2F report cnt: %d\n DL TxcmdQ empty cnt: %d\n"},
{MSG_8852B_WLANDUMP_5, "Issue DL SU Txcmd cnt: %d\n Issue DL MU Txcmd cnt: %d\n Issue DL RU Txcmd cnt: %d\n Issue UL Txcmd cnt: %d\n f2p_Triggerpkt_cnt=%d\n"},
{MSG_8852B_WLANDUMP_6, "Decision MU2SU cnt: %d\n Decision RU2SU cnt: %d\n DLDecision Result record: %x\n Decision SU_FORCESU cnt: %d\n Decision MU_FORCEMU cnt: %d\n"},
{MSG_8852B_WLANDUMP_7, "Decision SU_FORCEMU_FAIL cnt: %d\n Decision SU_FORCERU_FAIL cnt: %d\n Decision SU_FORCERU_RUARST_RU2SU cnt: %d\n Decision SU_NOT4_USER cnt: %d\n Decision RU_FORCERU_RUSRST_FIXTBL cnt: %d\n"},
{MSG_8852B_WLANDUMP_8, "Decision RU_FORCERU cnt: %d\n Decision SU_WDINFO_USERATE cnt: %d\n Decision SU_PRINULLWD cnt: %d\n ecision MU_BYPASS_MUTPCOMPARE cnt: %d\n Decision SU_MUTXTIME_PASS_MU_NOTSUPPORT cnt: %d\n"},
{MSG_8852B_WLANDUMP_9, "Decision SU_MUTXTIME_FAIL_RU_NOTSUPPORT cnt: %d\n Decision SU_RUARST_RU2SU cnt: %d\n Decision RU_RUARST_FIXTBL cnt: %d\n Decision MU_TPCOMPARE_RST cnt: %d\n Decision RU_TPCOMPARE_RST cnt: %d\n Decision SU_TPCOMPARE_RST cnt: %d\n"},
{MSG_8852B_WLANDUMP_10, "fw txcmdQ[0] cmd num: %d, fw txcmdQ[1] cmd num: %d,fw txcmdQ[2] cmd num: %d,fw txcmdQ[3] cmd num: %d,fw txcmdQ[4] cmd num: %d\n"},
{MSG_8852B_WLANDUMP_11, "fw txcmdQ[5] cmd num: %d, fw txcmdQ[6] cmd num: %d,fw txcmdQ[7] cmd num: %d,fw txcmdQ[8] cmd num: %d,fw txcmdQ[9] cmd num: %d, fw txcmdQ[10] cmd num: %d\n"},
{MSG_8852B_WLANDUMP_12, "TBD"},
{MSG_8852B_WLANDUMP_13, "mbid0~7: %d %d %d %d %d %d %d %d\n"},
{MSG_8852B_WLANDUMP_14, "macid %d info:\n isHESTA =%d\n AID12 =%d\n DL_BW =%d\n DL_T_PE =%d\n"},
{MSG_8852B_WLANDUMP_15, "TF_MAC_Padding =%d\n force tx su =%d\n force tx mu =%d\n fw force mu2su TH = %d\n force tx ru =%d\n"},
{MSG_8852B_WLANDUMP_16, "txok_pkt =%d\n txfail pkt cnt: %d\n retry_cnt =%d\n mbssid_idx =%d\n ulgroup_bitmap =%d\n null_wd_cnt =%d\n"},
{MSG_8852B_WLANDUMP_17, "ul_sw_grp_bitmap =%d\n AMPDU_max_txtime =%d\n mu_doppler_ctrl =%d\n mu_gi_ltf =%d\n mu decision txtime_bypass =%d\n mu decision mutp_bypass =%d\n"},
{MSG_8852B_WLANDUMP_18, "mu_maxinitrate = %x\n mu_maxfinalrate = %x\n mu_mininitrate = %x\n mu_minfinalrate = %x\n mu primary cnt = %d\n"},
{MSG_8852B_WLANDUMP_19, " PwrBit =%d\n TP =%d Mbps\n Max Txlen = %x (unit23 byte)\n Min Txlen = %x (unit23 byte)\n Last Txlen = %x (unit23 byte)\n Last BSRlen = %x (unit256 byte) AC=%d\n"},
{MSG_8852B_WLANDUMP_20, "mu sta %d info\n mu sta macid= %d\n"},
{MSG_8852B_WLANDUMP_21, "mu sta rate array(8bit) 0-4: %x %x %x %x %x"},
{MSG_8852B_WLANDUMP_22, "mu sta rate array(8bit) 5-9: %x %x %x %x %x"},
{MSG_8852B_WLANDUMP_23, "su ok pkt cnt = %d\n su fail pkt cnt = %d\n su_norsp_pktcnt = %d\n SU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n SU TXCNT 1/<6/<16/>=16 : %d %d %d %d\n"},
{MSG_8852B_WLANDUMP_24, "mu ok pkt cnt = %d\n mu fail pkt cnt = %d\n mu_norsp_pktcnt = %d\n mu2su ok pkt cnt = %d\n mu2su fail pkt cnt = %d\n"},
{MSG_8852B_WLANDUMP_25, "ru ok pkt cnt = %d\n ru fail pkt cnt = %d\n"},
{MSG_8852B_WLANDUMP_26, "MU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n MU DIFF <4/<8/<12/>=12 : %d %d %d %d\n"},
{MSG_8852B_WLANDUMP_27, "MU TXCNT 1/<6/<16/>=16: %d %d %d %d\n"},
{MSG_8852B_WLANDUMP_28, "pktmaxtxcnt(su base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu2nd base) [0]= %d [1]= %d [2]= %d \n"},
{MSG_8852B_WLANDUMP_30, "F2PTXCMDRPT cnt= %d, SS2FWRPT cnt =%d, TXRPT cnt =%d, PLDRLSRPT cnt = %d\n"},
{MSG_8852B_WLANDUMP_31, "pkt_max_queue_time = %x, pkt_min_queue_time=%x\n"},
{MSG_8852B_WLANDUMP_32, "TWT %d info:\n Txcmd overSP= %d\n Txcmd pri user fail= %d\n DL cmdCnt inSP= %d\n UL cmdCnt inSP= %d\n"},
{MSG_8852B_WLANDUMP_33, "DL cmdCnt all= %d\n UL cmdCnt all= %d\n UL fixmode = %x\n cur cmd num = %x\n SP 1st TF fail cnt = %x\n"},
{MSG_8852B_WLANDUMP_34, "start_d= %d\n start_t= %d\n endearly_d= %d\n endearly_t= %d\n end_d= %d\n"},
{MSG_8852B_WLANDUMP_35, "end_t= %d\n timer_qrydl= %d\n timer_qryul= %d\n start_qrydl= %d\n total_qryul=%d\n"},
{MSG_8852B_WLANDUMP_36, "firstTF_fail = %d,%d\n"},
{MSG_8852B_WLANDUMP_37, "twt_decision_brk = %d, %d, %d, %d, %d, %d, %d, %d\n"},
{MSG_8852B_WLANDUMP_38, "twt_decision_rst= %d, %d, %d\n"},
{MSG_8852B_WLANDUMP_39, "twt_ACdecision_rst= %d, %d, %d, %d\n"},
{MSG_8852B_WLANDUMP_40, "twt_validdlss2f_cnt= %d, twt_emptydlss2f_cnt= %d, twt_validulss2f_cnt= %d, twt_emptyulss2f_cnt= %d, twt_dlss2f_fromquery= %d, twt_dlss2f_fromtxcmd=%d, twt_ulss2f_fromquery= %d, twt_ulss2f_fromtxcmd=%d\n"},
{MSG_8852B_WLANDUMP_41, "TWT member: %d %d %d %d %d\n"},
{MSG_8852B_WLANDUMP_42, "twt_dlss2f_qrycnt[0]=%d,twt_dlss2f_qrycnt[1]=%d,twt_dlss2f_qrycnt[2]=%d,twt_dlss2f_qrycnt[3]=%d\n"},
{MSG_8852B_WLANDUMP_43, "reform_fail_rst[0]=%d, reform_fail_rst[1]=%d, reform_fail_rst[2]=%d, reform_fail_rst[3]=%d, reform_fail_rst[4]=%d\n"},
{MSG_8852B_WLANDUMP_44, "MACID WD count BE:%d BK:%d VI:%d VO:%d\n"},
{MSG_8852B_WLANDUMP_45, "PPS F2PCMD_PPS:%d/s TXRPT_PPS:%d/s TXPKT_PPS:%d/s SS2F_0_PPS:%d/s SS2F_1_PPS:%d/s SS2F_2_PPS:%d/s"},
{MSG_8852B_ROLE_1, "B%dP%d RXBCNOK\n"},
{MSG_8852B_ROLE_2, "B%dP%d BCNNOHIT\n"},
{MSG_8852B_ROLE_3, "Role idx search fail\n"},
{MSG_8852B_ROLE_4, "=>CreateRole\n"},
{MSG_8852B_ROLE_5, "[FAIL] Role info alloc fail!\n"},
{MSG_8852B_ROLE_6, "[FAIL] Role info - PPSDbgParm alloc fail!\n"},
{MSG_8852B_ROLE_7, "[FAIL] Role info - PTWTParam alloc fail!\n"},
{MSG_8852B_ROLE_8, "[CreateRole] ActRole=%d, LinkRole=%d.\n"},
{MSG_8852B_ROLE_9, "[CreateRole] band=%d, port=%d, macid=%d.\n"},
{MSG_8852B_ROLE_10, "=>DelRole\n"},
{MSG_8852B_ROLE_11, "[Warn] ROLE_NOT_EXIST for DelRole!\n"},
{MSG_8852B_ROLE_12, "[DelRole] ActRole=%d!role_idx=%d\n"},
{MSG_8852B_ROLE_13, "Role idx search by macid fail\n"},
{MSG_8852B_ROLE_14, "[WARN] Role exist for macid=0x%x! role_idx=0x%x\n"},
{MSG_8852B_ROLE_15, "[FAIL] Create Role idx > max_number!\n"},
{MSG_8852B_ROLE_16, "[FAIL] Create Role fail!\n"},
{MSG_8852B_ROLE_17, "[Warn] search role fail for JoinInfo!\n"},
{MSG_8852B_ROLE_18, "[FAIL] JoinInfo Role idx > max_number!\n"},
{MSG_8852B_ROLE_19, "[WARN] Role exist for macid=0x%x! role_idx=0x%x\n"},
{MSG_8852B_ROLE_20, "[Warn] search role fail for DelRole!\n"},
{MSG_8852B_ROLE_21, "[FAIL] Del Role idx > max_number!\n"},
{MSG_8852B_PMF_00, "start saquery timer fail\n"},
{MSG_8852B_PMF_01, "start saquery timer\n"},
{MSG_8852B_PMF_02, "creat saquery timer fail\n"},
{MSG_8852B_PMF_03, "saquery timer is lanched alread\n"},
{MSG_8852B_PMF_04, "SA Query timer deleted!\n"},
{MSG_8852B_PMF_05, "Deauth content\n"},
{MSG_8852B_PMF_06, "packet_len_no_fcs error\n"},
{MSG_8852B_PMF_07, "ICV Error ok\n"},
{MSG_8852B_PMF_08, "encrypted deauth frame, SEC_TYPE: 0x%x) \n"},
{MSG_8852B_PMF_09, "not Encrypted Deauth/Disassoc\n"},
{MSG_8852B_PMF_10, "deauth_reason = %x %x\n"},
{MSG_8852B_PMF_11, "tx_sa_query_result = 0x%x\n"},
{MSG_8852B_PMF_12, "issue saquery req fail\n"},
{MSG_8852B_PMF_13, "ignore the deauth frame\n"},
{MSG_8852B_PMF_14, "ICV Error\n"},
{MSG_8852B_PMF_15, "bip_result=0x%x\n"},
{MSG_8852B_PMF_16, "\npacket_len_no_fcs error\n"},
{MSG_8852B_PMF_17, "\nOn SA Query Req! (len=0x%x)\n"},
{MSG_8852B_PMF_18, "issue saquery rsp fail\n"},
{MSG_8852B_PMF_19, "\nOn SA Query Resp!(len=0x%x)\n"},
{MSG_8852B_PMF_20, "issue_sa_query_timeout_hdl!\n"},
{MSG_8852B_PMF_21, "Deauth wake up!\n"},
{MSG_8852B_PMF_22, "can't get offload PKT for saquery\n"},
{MSG_8852B_PMF_23, "can't allocate sendpkt_buff \n"},
{MSG_8852B_PMF_24, "FW IPN > pkt IPN\n"},
{MSG_8852B_PMF_25, "FW IPN < pkt IPN\n"},
{MSG_8852B_PMF_26, "FW IPN == pkt IPN\n"},
{MSG_8852B_PMF_27, "IPSecAESECBInit false\n"},
{MSG_8852B_PMF_28, "IPSecAESECBEncrypt false\n"},
{MSG_8852B_PMF_30, "key_len = %d, false\n"},
{MSG_8852B_PMF_31, "iv_len = %d, false\n"},
{MSG_8852B_PMF_32, "IPSecInitWithISRDisable false\n"},
{MSG_8852B_PMF_40, "MIC check fail\n"},
{MSG_8852B_PMF_41, "\n: aes_gmac fail!\n"},
{MSG_8852B_PMF_42, "\n: _bip_gcmp_protect(128) fail!\n"},
{MSG_8852B_PMF_43, "\n: _bip_gcmp_protect(256) fail!\n"},
{MSG_8852B_PMF_44, "\n: unsupport dot11wCipher !\n"},
{MSG_8852B_PMF_45, "not a management frame\n"},
{MSG_8852B_PMF_46, "is a beacon\n"},
{MSG_8852B_PMF_47, "not a broadcast frame\n"},
{MSG_8852B_PMF_48, "packet too small\n"},
{MSG_8852B_PMF_49, "elemnt_id != 0x4c\n"},
{MSG_8852B_PMF_50, "is_bip_enc_frameComm return TRUE\n"},
{MSG_8852B_PMF_51, "\nbip_verifyComm: PKT (len=0x%x)\n"},
{MSG_8852B_PMF_52, "BSSID not match\n"},
{MSG_8852B_PMF_53, "ori_len = 0x%x\n"},
{MSG_8852B_PMF_54, "SW BIP DEC FAIL\n"},
{MSG_8852B_PMF_55, "NOT encrypted\n"},
{MSG_8852B_PMF_56, "IPN verify Fail\n"},
{MSG_8852B_PMF_57, "bip_verifyComm return TRUE\n"},
{MSG_8852B_PMF_58, "protection bit is not 1\n"},
{MSG_8852B_PMF_59, "not a unicast frame\n"},
{MSG_8852B_PMF_60, "PairwiseEncAlg not GCMP\n"},
{MSG_8852B_PMF_61, "aes_gcm_ad fail\n"},
{MSG_8852B_PMF_62, "aes_gcm_ae fail\n"},
{MSG_8852B_RXFLOW_1, "can't allocate wlan pktbuf\n"},
{MSG_8852B_RXFLOW_2, "DD=%x\n"},
{MSG_8852B_RXFLOW_3, "A=%x\n"},
{MSG_8852B_RXFLOW_4, "B=%x\n"},
{MSG_8852B_RXFWD_1, "Unsupported index!\n"},
{MSG_8852B_WLAN_1, "SS Query Report HW stuck!!\n"},
{MSG_8852B_SECCAM_1, "Search key, mac_id : %d, key_id : %d, key_type : %d , fail\n"},
{MSG_8852B_SECCAM_2, "Search key success\nMac_id : %d, key_id : %d, key_type : %d, key cam index : %d\n"},
{MSG_8852B_SECCAM_3, "Wowlan rekey %d, %d, %d\n"},
{MSG_8852B_SECCAM_4, "check addr key index full\n"},
{MSG_8852B_SECCAM_5, "Free cam index: %d\n"},
{MSG_8852B_SECCAM_6, "insertKeyAddrCam ret : %d\n"},
{MSG_8852B_RPTHDL_1, "pldrlsrpt len %d not align\n"},
{MSG_8852B_RPTHDL_2, "RlsRptHDLRAM8852B,rpt_num=%x,len=%x\n"},
{MSG_8852B_RPTHDL_3, "ERR: TxCmdRptHDL get NULL txinfo node,rpt->QSEL=%x, (rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n"},
{MSG_8852B_RPTHDL_4, "ERR: TxRptHDL get NULL txinfo node,rpt->QSEL=%x,(rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n"},
{MSG_8852B_RPTHDL_5, "ERR: TfRptHDL get NULL txinfo node\n"},
{MSG_8852B_RPTHDL_6, "SS2FInfoDeQ8852B\n"},
{MSG_8852B_RPTHDL_7, "F2PTXCMDRPT HDL\n"},
{MSG_8852B_RPTHDL_8, "SS2FWRPT HDL\n"},
{MSG_8852B_RPTHDL_9, "TFRPT HDL\n"},
{MSG_8852B_RPTHDL_10, "TXBCNRPT HDL\n"},
{MSG_8852B_RPTHDL_11, "CCXRPT HDL\n"},
{MSG_8852B_RPTHDL_12, "TXRPT HDL\n"},
{MSG_8852B_RPTHDL_13, "PLDRLSRPT HDL\n"},
{MSG_8852B_ERRHDL_1, "[ERR]DLE Timeout(idx = %d)\n"},
{MSG_8852B_ERRHDL_2, "[ERR]AXIDMA is not idle!\n"},
{MSG_8852B_ERRHDL_3, "[ERR]STA scheduler init\n"},
{MSG_8852B_ERRHDL_4, "[ERR]WDE cfg ready\n"},
{MSG_8852B_ERRHDL_5, "[ERR]PLE cfg ready\n"},
{MSG_8852B_ERRHDL_6, "=>DmaTopStuck:FA sts: %d, data: %d!\n"},
{MSG_8852B_ERRHDL_7, "=>DmaTopStuck:FA!\n"},
{MSG_8852B_ERRHDL_8, "=>DmaTopStuck:know!\n"},
{MSG_8852B_ERRHDL_9, "=>RecoveryCMAC!\n"},
{MSG_8852B_ERRHDL_10, "[ERR]BBRPT CHIF\n"},
{MSG_8852B_ERRHDL_11, "[ERR]Check CMAC_idle\n"},
{MSG_8852B_ERRHDL_12, "[ERR]PTCL tx\n"},
{MSG_8852B_ERRHDL_13, "[ERR]L0 promote event %x\n"},
{MSG_8852B_ERRHDL_14, "[ERR][C2H]Previous: %x; Current: %x\n"},
{MSG_8852B_ERRHDL_15, "ErrHDL in!\n"},
{MSG_8852B_ERRHDL_16, "ErrHDL out!\n"},
{MSG_8852B_ERRHDL_17, "DMAC error: %x\n"},
{MSG_8852B_ERRHDL_18, "CMAC0 error: %x\n"},
{MSG_8852B_ERRHDL_19, "CMAC1 error: %x\n"},
{MSG_8852B_ERRHDL_20, "notify: %x\n"},
{MSG_8852B_ERRHDL_21, "--->\n err=%x\n"},
{MSG_8852B_ERRHDL_22, "R_AX_SER_DBG_INFO =%x\n"},
{MSG_8852B_ERRHDL_23, "R_AX_DMAC_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_24, "R_AX_WDE_ERR_FLAG_CFG_NUM1 =%x\n"},
{MSG_8852B_ERRHDL_25, "R_AX_PLE_ERR_FLAG_CFG_NUM1 =%x\n"},
{MSG_8852B_ERRHDL_26, "R_AX_WDRLS_ERR_IMR =%x "},
{MSG_8852B_ERRHDL_27, "R_AX_WDRLS_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_28, "R_AX_RPQ_RXBD_IDX =%x\n"},
{MSG_8852B_ERRHDL_29, "R_AX_SEC_DEBUG =%x\n"},
{MSG_8852B_ERRHDL_30, "R_AX_MPDU_TX_ERR_IMR =%x "},
{MSG_8852B_ERRHDL_31, "R_AX_MPDU_TX_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_32, "R_AX_MPDU_RX_ERR_IMR =%x "},
{MSG_8852B_ERRHDL_33, "R_AX_MPDU_RX_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_34, "R_AX_STA_SCHEDULER_ERR_IMR =%x "},
{MSG_8852B_ERRHDL_35, "R_AX_STA_SCHEDULER_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_36, "R_AX_WDE_ERR_IMR=%x "},
{MSG_8852B_ERRHDL_37, "R_AX_WDE_ERR_ISR=%x\n"},
{MSG_8852B_ERRHDL_38, "R_AX_PLE_ERR_IMR=%x "},
{MSG_8852B_ERRHDL_39, "R_AX_PLE_ERR_FLAG_ISR=%x\n"},
{MSG_8852B_ERRHDL_40, "R_AX_TXPKTCTL_ERR_IMR_ISR=%x\n"},
{MSG_8852B_ERRHDL_41, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=%x\n"},
{MSG_8852B_ERRHDL_42, "R_AX_PKTIN_ERR_IMR =%x "},
{MSG_8852B_ERRHDL_43, "R_AX_PKTIN_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_44, "R_AX_PKTIN_ERR_IMR =%x "},
{MSG_8852B_ERRHDL_45, "R_AX_PKTIN_ERR_ISR =%x\n"},
{MSG_8852B_ERRHDL_46, "R_AX_HOST_DISPATCHER_ERR_IMR=%x "},
{MSG_8852B_ERRHDL_47, "R_AX_HOST_DISPATCHER_ERR_ISR=%x\n"},
{MSG_8852B_ERRHDL_48, "R_AX_CPU_DISPATCHER_ERR_IMR=%x "},
{MSG_8852B_ERRHDL_49, "R_AX_CPU_DISPATCHER_ERR_ISR=%x\n"},
{MSG_8852B_ERRHDL_50, "R_AX_CPUIO_ERR_IMR=%x "},
{MSG_8852B_ERRHDL_51, "R_AX_CPUIO_ERR_ISR=%x\n"},
{MSG_8852B_ERRHDL_52, "R_AX_BBRPT_COM_ERR_IMR_ISR=%x\n"},
{MSG_8852B_ERRHDL_53, "0xC164=%x\n"},
{MSG_8852B_ERRHDL_54, "R_AX_SCHEDULE_ERR_IMR=%x "},
{MSG_8852B_ERRHDL_55, "R_AX_SCHEDULE_ERR_ISR=%x\n"},
{MSG_8852B_ERRHDL_56, "R_AX_PTCL_IMR0=%x "},
{MSG_8852B_ERRHDL_57, "R_AX_PTCL_ISR0=%x\n"},
{MSG_8852B_ERRHDL_58, "R_AX_DLE_CTRL=%x\n"},
{MSG_8852B_ERRHDL_59, "R_AX_PHYINFO_ERR_IMR=%x\n"},
{MSG_8852B_ERRHDL_60, "R_AX_TXPWR_IMR= N/A "},
{MSG_8852B_ERRHDL_61, "R_AX_TXPWR_ISR= N/A\n"},
{MSG_8852B_ERRHDL_62, "R_AX_DBGSEL_TRXPTCL=%x "},
{MSG_8852B_ERRHDL_63, "R_AX_PHYINFO_ERR_IMR=%x\n"},
{MSG_8852B_ERRHDL_64, "R_AX_TMAC_ERR_IMR_ISR=%x "},
{MSG_8852B_ERRHDL_65, "R_AX_DBGSEL_TRXPTCL=%x\n"},
{MSG_8852B_ERRHDL_66, "<---\n"},
{MSG_8852B_MAIN_00, "SW Queue reCreate\n"},
{MSG_8852B_MAIN_01, "Enter AXIDMA_init... \n"},
{MSG_8852B_MAIN_02, "WDT_timer start... \n"},
{MSG_8852B_MAIN_03, "InitHWPostDLRAM done\n"},
{MSG_8852B_MAIN_04, "InitFWFuncPostDL RAM done\n"},
{MSG_8852B_MAIN_05, "MAC per STAInfo %d bytes\n"},
{MSG_8852B_MAIN_06, "BB per STAInfo %d bytes\n"},
{MSG_8852B_MAIN_07, "InitWLANFuncRAM done\n"},
{MSG_8852B_MAIN_08, "Enter test id (0~7): "},
{MSG_8852B_MAIN_09, "%c\n"},
{MSG_8852B_MAIN_10, "Thread Metric: %d\n"},
{MSG_8852B_MAIN_11, "Test duration: %d seconds\n"},
{MSG_8852B_MAIN_14, "WDT_timer start fail \n"},
{MSG_8852B_MAIN_15, " SysMib.PInternal->PDebugInfo->DbgLvl =%x\n"},
{MSG_8852B_MAIN_16, "Enter flash FW loader\n"},
{MSG_8852B_IRAMENTRY_00, "Function ptr length :RAM %x,ROM %x\n"},
{MSG_8852B_IRAMENTRY_01, "Function ptr length not equal!!\n"},
{MSG_8852B_IRAMENTRY_02, "Start Init PLE memory\n"},
{MSG_8852B_IRAMENTRY_03, "PLE data check error!!!"},
{MSG_8852B_IRAMENTRY_04, "PLE usage :%x\n"},
{MSG_8852B_IRAMENTRY_05, "Initializing RAM bss ...\n"},
{MSG_8852B_IRAMENTRY_06, "_BSS_RAM_START_ : %x\t _BSS_RAM_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_07, "B cut\n"},
{MSG_8852B_IRAMENTRY_08, "_RAM_FUNCPTR_START_ : %x\t _RAM_FUNCPTR_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_09, "_ROM_FUNCPTR_START_ : %x\t _ROM_FUNCPTR_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_10, "C cut\n"},
{MSG_8852B_IRAMENTRY_11, "_RAM_CCUT_FUNCPTR_START_ : %x\t _RAM_CCUT_FUNCPTR_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_12, "_ROM_CCUT_FUNCPTR_START_ : %x\t _ROM_CCUT_FUNCPTR_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_13, "D cut\n"},
{MSG_8852B_IRAMENTRY_14, "_RAM_DCUT_FUNCPTR_START_ : %x\t _RAM_DCUT_FUNCPTR_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_15, "_ROM_DCUT_FUNCPTR_START_ : %x\t _ROM_DCUT_FUNCPTR_END_ : %x\n"},
{MSG_8852B_IRAMENTRY_16, "Load FW RAM code OK\n"},
{MSG_8852B_BACKTRACE_00, "Heap space is not enough for backtrace.......\n"},
{MSG_8852B_BACKTRACE_01, "Backtrace......\n"},
{MSG_8852B_BACKTRACE_02, "Next SP:%x, Next RA:%x\n"},
{MSG_8852B_BACKTRACE_03, "Backtrace is failed\n"},
{MSG_8852B_BACKTRACE_04, "Done\n"},
{MSG_8852B_BACKTRACE_05, "EPC: %x, Cause: %x, BADVADDR: %x, Status: %x\n"},
{MSG_8852B_BACKTRACE_06, "hi: %x, lo: %x, ra: %x, fp: %x\n"},
{MSG_8852B_BACKTRACE_07, "sp: %x, gp: %x, t9: %x, t8: %x\n"},
{MSG_8852B_BACKTRACE_08, "s7: %x, s6: %x, s5: %x, s4: %x\n"},
{MSG_8852B_BACKTRACE_09, "s3: %x, s2: %x, s1: %x, s0: %x\n"},
{MSG_8852B_BACKTRACE_10, "t7: %x, t6: %x, t5: %x, t4: %x\n"},
{MSG_8852B_BACKTRACE_11, "t3: %x, t2: %x, t1: %x, t0: %x\n"},
{MSG_8852B_BACKTRACE_12, "a3: %x, a2: %x, a1: %x, a0: %x\n"},
{MSG_8852B_BACKTRACE_13, "v1: %x, v0: %x, at: %x\n"},
{MSG_8852B_BACKTRACE_14, "not send c2hHalt\n"},
{MSG_8852B_BACKTRACE_15, "no loop\n"},
{MSG_8852B_BACKTRACE_16, "Something wrong when allocating backtrace memory\n"},
{MSG_8852B_BACKTRACE_17, "Backtrace memory is full!!\n"},
{MSG_8852B_BACKTRACE_18, "Init Backtrace Memory failed\n"},
{MSG_8852B_PSTIMER_00, "handle task:%x\n"},
{MSG_8852B_PSTIMER_01, "handle tsf: %x\n"},
{MSG_8852B_PSTIMER_02, "tsf in list: %x\n"},
{MSG_8852B_AXIDMA_00, "[ERR] AXIDMA is not idle!\n"},
{MSG_8852B_AXIDMA_01, "[ERR] AXIDMA is not enable\n"},
{MSG_8852B_AXIDMA_02, "[AXIDMA RX Init]Allocate H2C buffer fail 123\n"},
{MSG_8852B_AXIDMA_03, "[AXIDMA RX Init]Allocate PKT buffer fail\n"},
{MSG_8852B_AXIDMA_04, "[AXIDMA RX Init]Allocate RPT buffer fail\n"},
{MSG_8852B_PORT_00, "Assert at file: %s, line: %u\n"},
{MSG_8852B_PORT_01, "not send c2hHalt\n"},
{MSG_8852B_PORT_02, "no loop\n"},
{MSG_8852B_PORT_03, "Watch dog timeout in critical section\n"},
{MSG_8852B_PORT_04, "Watch dog remain: %d(us)\n"},
{MSG_8852B_PORT_05, "Exec Time %x ~ %x: %d(us)\n"},
{MSG_8852B_RXI300_00, "EPC Value: %x\n"},
{MSG_8852B_RXI300_01, "Error id is inexistent(%x)!\n"},
{MSG_8852B_RXI300_02, "Error code is inexistent(%x)!\n"},
{MSG_8852B_RXI300_03, "RXI300_ERR_SRC_APB_DEF_SLV"},
{MSG_8852B_RXI300_04, "RXI300_ERR_SRC_AXI_APB_SA"},
{MSG_8852B_RXI300_05, "Error source is inexistent(%x)!\n"},
{MSG_8852B_RXI300_06, "HaltC2H = %x, Error address = %x!\n"},
{MSG_8852B_RXI300_07, "Clear interrupt fail!\n"},
{MSG_8852B_RXI300_08, "RA/SP Value: %x, %x\n"},
{MSG_8852B_PS_CHK_PLATFORM_ERR_1, "DMAC error: %x\n"},
{MSG_8852B_PS_CHK_PLATFORM_ERR_2, "CMAC%d error: %x\n"},
{MSG_8852B_PS_DDMA_BUFFER_SIZE_OVERFLOW, "MAC%d DDMA buffer size (%x) is overflow!\n"},
{MSG_8852B_PS_HIOE_START_ADDR, "LPS HIOE start address = %x, size = %x\n"},
{MSG_8852B_PS_HIOE_END_ADDR, "LPS HIOE end address = %x\n"},
{MSG_8852B_PS_HIOE_INST_OVERFLOW, "LPS HIOE instruction is overflow! inst_size(%x).\n"},
{MSG_8852B_PS_HIOE_READ_PCIEMIO_FAIL, "[Err] ReadPCIEMIO Fail! reg = %x\n"},
{MSG_8852B_PS_HIOE_WRITE_PCIEMIO_FAIL, "[Err] WritePCIEMIO Fail! reg = %x\n"},
{MSG_8852B_PS_HIOE_BACKUP_FAIL, "BKP fail st.(%x)\n"},
{MSG_8852B_PS_HIOE_RESTORE_FAIL, "RES fail st.(%x)\n"},
{MSG_8852B_PS_HIOE_INVALID_STATE, "Invalid st.(%x)\n"},
{MSG_8852B_PS_HIOE_BACKUP_TIMEOUT, "Bkp (%d) polling timeout!\n"},
{MSG_8852B_PS_HIOE_RESTORE_TIMEOUT, "Res polling timeout!\n"},
{MSG_8852B_PS_ENTER_32K, ">C\n"},
{MSG_8852B_PS_LEAVE_32K, "<C\n"},
{MSG_8852B_PS_RESET_BD_POLLING_TIMEOUT, "Reset BD polling timeout! val(%d)\n"},
{MSG_8852B_PS_BACKUP_MAC_FAIL, "BkpMAC (%d) start fail!!\n"},
{MSG_8852B_PS_BACKUP_MAC_TIMEOUT, "BkpMAC (%d) polling timeout! idx=%x!\n"},
{MSG_8852B_PS_RESTORE_MAC_FAIL, "RestoreMAC (%d) start fail!!\n"},
{MSG_8852B_PS_RESTORE_MAC_TIMEOUT, "RestoreMAC (%d) polling timeout! idx=%x!\n"},
{MSG_8852B_PS_TIMER_STOP_FAIL, "[32K] timer (%d) stop FAIL!\n"},
{MSG_8852B_PS_TIMER_START_FAIL, "[32K] timer (%d) start FAIL!\n"},
{MSG_8852B_PS_DISABLE_HCIDMA_FAIL, "Disable HCI TX DMA FAIL!\n"},
{MSG_8852B_PS_READ_PCIEMIO_FAIL, "[Err] ReadPCIEMIO Fail! reg = %x\n"},
{MSG_8852B_PS_WRITE_PCIEMIO_FAIL, "[Err] WritePCIEMIO Fail! reg = %x\n"},
{MSG_8852B_PS_32K_STATUS, "LPS Status: %x\n"},
{MSG_8852B_PS_32K_ERROR, "LPS Error: %x\n"},
{MSG_8852B_PS_32K_INFO, "LPS Info: %x\n"},
{MSG_8852B_PS_SLEEP_TIME, "[Sleep Time] Expect=%x, Complete=%x\n"},
{MSG_8852B_PS_TIMING_LOG_1, "[PST] ResPG Analysis(us): %d, MAC: %d, BB: %d, RF: %d\n"},
{MSG_8852B_PS_TIMING_LOG_2, "[PST] Res timer(us): %d us, MAC1st backup: %d, MAC everytime backup: %d, Enable WDE/PLE: %d\n"},
{MSG_8852B_PS_TIMING_LOG_3, "[PST] RFK(us): %d, DACK: %d, Radio: %d, RFC: %d\n"},
{MSG_8852B_PS_TIMING_LOG_4, "[PST] T2 ClkUp to OpenRF: %d us\n"},
{MSG_8852B_PS_TIMING_LOG_5, "[PST] ResDone = %x us, OpenRF = %x us, TBTT = %x us, RxBcn = %x us\n"},
{MSG_8852B_PS_TIMING_LOG_6, "[PST] OpenRF to TBTT = %d us, TBTT to RxBcn = %d us, RxBcn to ClsRF = %d us, ClsRF to 32k = %d us\n"},
{MSG_8852B_PS_TIMING_LOG_7, "[PST] ResDone = %x us, OpenRF = %x us, TBTT = %x us\n,"},
{MSG_8852B_PS_TIMING_LOG_8, "[PST] ResDone to SetBcnTo = %d us, SetBcnTo to BcnTo = %d us, BcnTo to ClsRF = %d us, ClsRF to 32k = %d us\n"},
{MSG_8852B_PS_TIMING_LOG_9, "[PST] OpenRF = %x us, TBTT = %x us, RxBcn = %x us\n"},
{MSG_8852B_PS_TIMING_LOG_10, "[PST] OpenRF to TBTT = %d us, TBTT to RxBcn = %d us, RxBcn to ClsRF = %d us\n"},
{MSG_8852B_PS_TIMING_LOG_11, "[PST] OpenRF = %x us, TBTT = %x us, SetBcnTo to BcnTo = %d us, BcnTo to ClsRF = %d us\n"},
{MSG_8852B_PS_TIMING_LOG_12, "[PST] OpenRF to ClsRF = %d us, RxBcn to S4 = %d us, S4Cnt = %d\n"},
{MSG_8852B_PS_TIMING_LOG_13, "[PST] OpenRF to ClsRF = %d us, BcnTo to S4 = %d us, S4Cnt = %d\n"},
{MSG_8852B_PS_TIMING_LOG_14, "[PST] BcnLossRate = %d/100, BcnTimeoutCnt = %d, BcnErlyCnt = %d\n"},
{MSG_8852B_PS_TIMING_LOG_15, "[PST] S4Error[%d] = %d\n"},
{MSG_8852B_PS_INIT_FAIL, "[FAIL] lps_info alloc fail!\n"},
{MSG_8852B_PS_PLATFORM_ERR, "Platform error (%d)!\n"},
{MSG_8852B_PS_RESTORE_FLOW_FAIL, "RestoreFlow FAIL!\n"},
{MSG_8852B_PS_AXIDMA_NOT_EMPTY, "[32K] AXIDMA not empty (%d). host = %x, hw = %x\n"},
{MSG_8852B_PS_NO_ENTER_LPS, "0x90=%x, No Enter LPS! 0xC0=%x\n"},
{MSG_8852B_PS_TX_PACKT_IN, "TxPktIn\n"},
{MSG_8852B_PS_TXDMA_BUSY, "[Err] TXDMA is busy! dma_busy1 = %x, dma_busy2 = %x\n"},
{MSG_8852B_PS_TAKE_SEMAPHORE_FAIL, "Step(%d) Take RxModeLock FAIL!!!\n"},
{MSG_8852B_PS_NULL_SEMAPHORE, "Step(%d) RxModeLock == NULL!\n"},
{MSG_8852B_PS_CLOSE_RF, ">\n"},
{MSG_8852B_PS_OPEN_RF, "<\n"},
{MSG_8852B_PS_GRANT_WLAN_FAIL, "[PDCK] GNT WL FAIL!!\n"},
{MSG_8852B_PS_PDCK_CAL_FAIL, "PDCK CAL FAIL!!\n"},
{MSG_8852B_PS_ANACLK_CAL_FAIL, "ANACLK CAL FAIL!!\n"},
{MSG_8852B_PS_EN_RX_NORMAL_MODE_FAIL, "RF is OFF. EnRxNormMode FAIL!\n"},
{MSG_8852B_PS_EN_RX_NORMAL_MODE, "1->2"},
{MSG_8852B_PS_SET_RF_OFF_PERMISSION, "SetRfOffPermission: PhyRfOffPermission[%d]=%d\n"},
{MSG_8852B_PS_SET_32K_PERMISSION, "Set32KandPGPermission. 32K(%d), PG(%d)\n"},
{MSG_8852B_PS_ENABLE_LPS_FW_TEST, "Enable LPS FW test. Target LPS number (%x)\n"},
{MSG_8852B_PS_WAKE_BAR_PULL, "[RF OFF] Wake bar is pulled\n"},
{MSG_8852B_PS_RX_FAIL_KEEP_RF_ON, "[RF OFF] Rx FAIL! keep RF on.\n"},
{MSG_8852B_PS_CHECK_RF_CONDITION_FAIL, "Check RF OFF condition FAIL (%d)\n"},
{MSG_8852B_PS_TX_NULL_FAIL, "[Error] Cannot tx null%d\n"},
{MSG_8852B_PS_CREATE_ROLE_FAIL, "[FAIL] Create Role fail!\n"},
{MSG_8852B_PS_ALREADY_IN_PS_MODE, "[Error] Already in LPS/WMM PS (%x)!!\n"},
{MSG_8852B_PS_SET_POWER_MODE_1, "MAC ID = %d, PS Mode = %d, RLBM = %d\n"},
{MSG_8852B_PS_SET_POWER_MODE_2, "Smart PS = %d, Awake Interval = %d, Last RPWM = %d\n"},
{MSG_8852B_PS_BEACON_EARLY, "E\n"},
{MSG_8852B_PS_RX_BEACON, "R\n"},
{MSG_8852B_PS_RX_BEACON_NO_HIT, "N\n"},
{MSG_8852B_PS_INVALID_BEACON_REPORT, "[Error] Does not receive BCN Parser Rpt\n"},
{MSG_8852B_PS_KEEP_RF_ON, "Keep ON\n"},
{MSG_8852B_PS_ENABLE_BEACON_TIMEOUT_TIMER_FAIL, "EnBcnTimeOutCount fail!!\n"},
{MSG_8852B_PS_TIMER_VALUE_NOT_INIT, "Timer (%d) val is not init!! role_idx(%d)\n"},
{MSG_8852B_PS_CREATE_TIMER_FAIL, "Create timer (%d) fail!! role_idx(%d)\n"},
{MSG_8852B_PS_SEND_NULL_FAIL_RESULT, "TxNull %d FAIL! ret_type(%d), result(%d)\n"},
{MSG_8852B_PS_INVALID_POWER_BIT, "[PsSendNullCb] invalid pwr_bit(%d)\n"},
{MSG_8852B_PS_INIT_PS_PARAMETER, "InitPSParm, role_idx=%d\n"},
{MSG_8852B_PS_S2_CONDITION_MISMATCH, "[ChkS2 no match] Condition(%d), LpsDbgInfo = 0x%x\n"},
{MSG_8852B_PS_S4_CONDITION_MISMATCH, "[ChkS4 no match] Condition(%d), LpsDbgInfo = 0x%x\n"},
{MSG_8852B_PS_CHANGE_PS_STATE, "[ChangePSStateByRPWM] REQ State: %d, Cur State: %d\n"},
{MSG_8852B_PS_SET_POWER_MODE_ROLE_NOT_EXIST, "[SetPwrMode] Role not exist! Condition (%d)\n"},
{MSG_8852B_PS_SET_TBTT_AGG_NUM, "Step(%d), SetTbttAggNum(%d).\n"},
{MSG_8852B_PS_RX_BEACON_TIMEOUT, "PsBcnTimeOut\n"},
{MSG_8852B_PS_SET_POWER_STATE, "CURRENT_PS_STATE: %d, LASTRPWM: %d\n"},
{MSG_8852B_PS_RESET_PS_PARAMETER, "ResetPSParm\n"},
{MSG_8852B_PS_ACTIVATE_SETTING, "ActiveSetting\n"},
{MSG_8852B_PS_SEND_NULL_RESULT, "[PsSendNullCb] type(%d), result(%d)\n"},
{MSG_8852B_PACKET_TX_NOT_ENABLE, "[ERR]MGQ1 Txen = 0, TXEN(0xC348)=%x\n"},
{MSG_8852B_PACKET_MACID_SLEEP, "MACID_SLEEP_0(0xC2C0)=%x\n"},
{MSG_8852B_PACKET_TX_NULL, "Null %d\n"},
{MSG_8852B_PACKET_SEND_NULL_FAIL, "Send NULL FAIL! ret_type(%d), ret_result(%d).\n"},
{MSG_8852B_PACKET_INVALID_POWER_BIT, "Send NULL with invalid type(%d)!.\n"},
{MSG_8852B_PACKET_NULL_PKTID_NOT_EXIST, "Null PKTID No Exist!!\n"},
{MSG_8852B_PACKET_NULL_READ_PKT_OFFLOAD_FAIL, "[IssueNull]ReadFWOfldPKT FAIL!!\n"},
{MSG_8852B_PACKET_NULL_PKT_OFFLOAD, "Null ID=%d, pkt_len=%d, ppkt_content=%x\n"},
{MSG_8852B_PACKET_PROBE_REQ_PKTID_NOT_EXIST, "Probe req PKTID No Exist!!\n"},
{MSG_8852B_PACKET_PROBE_REQ_READ_PKT_OFFLOAD_FAIL, "[IssueProbeReq]ReadFWOfldPKT FAIL!!\n"},
{MSG_8852B_WOWLAN_1, "H2C wowlan, fun: %x"},
{MSG_8852B_WOWLAN_2, "H2C Keep Alive, Enable: %x\n"},
{MSG_8852B_WOWLAN_3, "H2C disconn, Enable: %x\n"},
{MSG_8852B_WOWLAN_4, "Wow stop AXIDMA failed\n"},
{MSG_8852B_WOWLAN_5, "H2C wow global, Enable: %x\n"},
{MSG_8852B_WOWLAN_6, "H2C wakeup ctrl, pattern match Enable: %x\n"},
{MSG_8852B_WOWLAN_7, "H2C , nlo Enable: %x\n"},
{MSG_8852B_WOWLAN_8, "H2C , wow cam: %x\n"},
{MSG_8852B_WOWLAN_9, "\nAppendTkipMICComm\n"},
{MSG_8852B_WOWLAN_10, "key[%d]=%bx\n"},
{MSG_8852B_WOWLAN_11, "DA[%d]=%bx\n"},
{MSG_8852B_WOWLAN_12, "SA[%d]=%bx\n"},
{MSG_8852B_WOWLAN_13, "Priority[%d]=%bx\n"},
{MSG_8852B_WOWLAN_14, "data[%d]=%bx\n"},
{MSG_8852B_WOWLAN_15, "miccode[%d]=%bx\n"},
{MSG_8852B_WOWLAN_16, "get 1st rx pktid fail\n"},
{MSG_8852B_WOWLAN_17, "(%d, %d) Parsed Failed!\n"},
{MSG_8852B_WOWLAN_18, "Magic Packet Parsed Done, reason_bits<%x>\n"},
{MSG_8852B_WOWLAN_19, "H2C , arp ofld Enable: %x\n"},
{MSG_8852B_WOWLAN_20, "Unexpected HCI type in togglewake\n"},
{MSG_8852B_BEACON_1, "req bcn mem err\n"},
{MSG_8852B_BEACON_2, "CPUIO rls bcn pld fail\n"},
{MSG_8852B_BEACON_3, "req bcn wp err %d\n"},
{MSG_8852B_BEACON_4, "bcnq lock fail\n"},
{MSG_8852B_BEACON_5, "CPUIO deq bcn fail\n"},
{MSG_8852B_BEACON_6, "bcn req wd fail %d\n"},
{MSG_8852B_BEACON_7, "enq bcn fail %d\n"},
{MSG_8852B_PPS_00, "B%d pps%d already enable\n"},
{MSG_8852B_PPS_01, "B%d pps%d already disable\n"},
{MSG_8852B_PPS_02, "B%d pps%d reg already enable\n"},
{MSG_8852B_PPS_03, "B%d pps%d reg already disable\n"},
{MSG_8852B_PPS_04, "invalid pps band %d\n"},
{MSG_8852B_PPS_05, "B%d pps%d is not enable yet\n"},
{MSG_8852B_PPS_06, "B%d pps%d pof%d already enable\n"},
{MSG_8852B_PPS_07, "B%d pps%d pof%d already disable\n"},
{MSG_8852B_PPS_08, "B%d pps%d pof%d reg already enable\n"},
{MSG_8852B_PPS_09, "B%d pps%d pof%d reg already disable\n"},
{MSG_8852B_PPS_10, "B%d pps%d pof%d running\n"},
{MSG_8852B_PPS_11, "pps no param ptr %d\n"},
{MSG_8852B_PPS_12, "invalid pps port %d\n"},
{MSG_8852B_PPS_13, "no valid pps id\n"},
{MSG_8852B_PPS_14, "pps is already running\n"},
{MSG_8852B_PS_TX_REQ, "PsTxReq. role(%d), feature(%d), en(%d)\n"},
{MSG_8852B_PS_TX_REQ_DUPLICATED_DISABLE, "[ERROR] role(%d), feature(%d) Tx has been disabled!\n"},
{MSG_8852B_CHSW_00, "[ChSw] Channel Switch Fail. (ctrl_bw_ch return false)\n"},
{MSG_8852B_P2P_00, "[P2P]no act info ptr\n"},
{MSG_8852B_P2P_01, "[P2P]act h2c init Role idx srch fail macid %d\n"},
{MSG_8852B_P2P_02, "[P2P]set pps param fail %d\n"},
{MSG_8852B_P2P_03, "[P2P]B%d pps%d en%d fail %d\n"},
{MSG_8852B_P2P_04, "[P2P]B%d pps%d pof%d en%d fail %d\n"},
{MSG_8852B_P2P_05, "[P2P]set pof param fail %d\n"},
{MSG_8852B_P2P_06, "[P2P]B%d P2P%d noa%d already disable\n"},
{MSG_8852B_P2P_07, "[P2P]B%d P2P%d has no running NoA sch\n"},
{MSG_8852B_P2P_08, "[P2P]no content ptr\n"},
{MSG_8852B_P2P_09, "[P2P]act h2c p2p%d over max\n"},
{MSG_8852B_P2P_10, "[P2P]act h2c noa%d over max\n"},
{MSG_8852B_P2P_11, "[P2P]p2p%d already running\n"},
{MSG_8852B_P2P_12, "[P2P]p2p%d not init yet\n"},
{MSG_8852B_P2P_13, "[P2P]act h2c init fail %d\n"},
{MSG_8852B_P2P_14, "[P2P]act h2c upd sch fail %d\n"},
{MSG_8852B_P2P_15, "[P2P]act h2c rm sch fail %d\n"},
{MSG_8852B_P2P_16, "[P2P]act h2c term fail %d\n"},
{MSG_8852B_P2P_17, "[P2P]illegal act h2c %d\n"},
{MSG_8852B_P2P_18, "[P2P] macid ctrl h2c p2p id %d over max\n"},
{MSG_8852B_P2P_19, "[P2P]macid ctrl type %d invalid\n"},
{MSG_8852B_P2P_20, "[P2P]no p2p info ptr\n"},
{MSG_8852B_P2P_21, "[P2P]P2P%d clear MACID ctrl all fail %d\n"},
{MSG_8852B_P2P_22, "[P2P]H2C Act fail %d\n"},
{MSG_8852B_P2P_23, "[P2P]H2C MACID ctrl fail %d\n"},
{MSG_8852B_NULL_RESULT, "TxNull %d result(%d)!!!\n"},
{MSG_8852B_PS_CREATE_TIMER_DUPLICATED, "[ERR][LPS] Create timer (%d) is existed!! role_idx(%d)\n"},
{MSG_8852B_PS_DELETE_TIMER_FAIL, "[ERR][LPS] Delete timer (%d) FAIL!! role_idx(%d)\n"},
{MSG_8852B_PS_DELETE_TIMER_NOT_EXIST, "[ERR][LPS] Delete timer (%d) is not existed!! role_idx(%d)\n"},
{MSG_8852B_PS_DTIM_TIMER_NOT_EXIST, "[ERR][LPS] Operation(%d) DTIM timer is not existed!! role_idx(%d)\n"},
{MSG_8852B_PS_BCN_TIMER_NOT_EXIST, "[ERR][LPS] Operation(%d) BCN timer is not existed!! role_idx(%d)\n"},
{MSG_8852B_PS_TRX_TIMER_NOT_EXIST, "[ERR][LPS] Operation(%d) TRX timer is not existed!! role_idx(%d)\n"},
{MSG_8852B_PS_ENABLE_DTIM_TIMEOUT_TIMER_FAIL, "[ERR][LPS] EnDTIMTimeOutCountComm FAIL!!\n"},
{MSG_8852B_PS_ENABLE_TRX_TIMEOUT_TIMER_FAIL, "[ERR][LPS] EnTRXTimeOutCount FAIL!!\n"},
{MSG_8852B_PS_DRFC_RESTORE_FAIL, "[ERR][LPS] Restore DRFC FAIL!! RF mode (%d)\n"},
{MSG_8852B_PS_S2TOS4_TX_BUSY, "[WARN][LPS][S2ToS4State] Macid TX busy, role_idx(%d)\n"},
{MSG_8852B_RPWM_SEQ_MISMATCH, "[ERR] RPWM Seq Num mismatch!\n"},
{MSG_8852B_RPWM_REQ_STATE_INVALID, "[ERR] Req Pwr state (%d) is invalid!\n"},
{MSG_8852B_READ_RPWM, "Read RPWM = %x\n"},
{MSG_8852B_WRITE_CPWM, "LDM = %x, cpwm_val = %x, CPWM = %x\n"},
{MSG_8852B_TASK_ERROR, "Task Error: %wx\n"},
{MSG_8852B_GETMEDIASTS_1, "GetMediaStatusbyMacid fail, macid = %bx!\n"},
{MSG_8852B_SETMEDIASTS_1, "SetMediaStatusbyMacid: macid number >= 32, macid = %bx!\n"},
{MSG_8852B_SETMEDIASTS_2, "SetMediaStatusbyMacid: Role_idx error, macid = %bx, role_idx = %bx!\n"},
{MSG_8852B_OUTSRC_START, " out source delimiter start"},
{MSG_8852B_OUTSRC_BB_SURA_0, "[RA]RateChange=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_1, "[RA]RDth=0x%x,RUth=0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_2, "[RA]r4=100\n"},
{MSG_8852B_OUTSRC_BB_SURA_3, "[RA]ForceRD\n"},
{MSG_8852B_OUTSRC_BB_SURA_4, "[RA]RDCnt=0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_5, "[RA]RUCnt=0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_6, "[RA]RS\n"},
{MSG_8852B_OUTSRC_BB_SURA_7, "[RA]SGIRD\n"},
{MSG_8852B_OUTSRC_BB_SURA_8, "[RA]BWRD\n"},
{MSG_8852B_OUTSRC_BB_SURA_9, "[RA]RDToLowest1\n"},
{MSG_8852B_OUTSRC_BB_SURA_10, "[RA]RDToLowest2\n"},
{MSG_8852B_OUTSRC_BB_SURA_11, "[RA]RD:crate=0x%x,mrate0=0x%x,mrate1=0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_12, "[RA]rate=0x%x,bw:0x%x,rate2=0x%x,bw2:0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_13, "[RA]Hit:bw=0x%x->0x%x,rate=0x%x->0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_14, "[RA]SR:rate0=0x%x,rate1=0x%x,rate2=0x%x,cnt=0x%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_15, "RSVD\n"},
{MSG_8852B_OUTSRC_BB_SURA_16, "[RA]SGIRU\n"},
{MSG_8852B_OUTSRC_BB_SURA_17, "[RA]BWRU\n"},
{MSG_8852B_OUTSRC_BB_SURA_18, "[RA]RUbw++\n"},
{MSG_8852B_OUTSRC_BB_SURA_19, "[RA]RUToHighest\n"},
{MSG_8852B_OUTSRC_BB_SURA_20, "[RA]NoUpRate\n"},
{MSG_8852B_OUTSRC_BB_SURA_21, "[RA]RU:crate=%x,mrate0=%x,mrate1=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_22, "[RA,W]macid:%x,mode:%x,rate_idx:%x,mcs:%x,ss:%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_23, "[RA][TRY]PER=%x,RDR=%x,R4=%x, pre_tp=%d, next_tp=%d\n"},
{MSG_8852B_OUTSRC_BB_SURA_24, "[RA][TRY]R4=100,cnt=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_25, "[RA][TRY]rate=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_26, "[RA]TryFail\n"},
{MSG_8852B_OUTSRC_BB_SURA_27, "[RA]TrySuccess\n"},
{MSG_8852B_OUTSRC_BB_SURA_28, "[RA]MtTryIdx=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_29, "[RA]TryFailCnt=%x,rate=%x,bw=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_30, "[RA]DrvFixRate\n"},
{MSG_8852B_OUTSRC_BB_SURA_31, "[RA]POLLUTED\n"},
{MSG_8852B_OUTSRC_BB_SURA_32, "[RA]Tot=0\n"},
{MSG_8852B_OUTSRC_BB_SURA_33, "[RA]Tx=0,Tot:%x,Ok:%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_34, "[RA]StaNull\n"},
{MSG_8852B_OUTSRC_BB_SURA_35, "[RA]NoHESU\n"},
{MSG_8852B_OUTSRC_BB_SURA_36, "[RA]WDNoRelease\n"},
{MSG_8852B_OUTSRC_BB_SURA_37, "[RA]TxRptTot=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_38, "[RA]Ovfl\n"},
{MSG_8852B_OUTSRC_BB_SURA_39, "RSVD\n"},
{MSG_8852B_OUTSRC_BB_SURA_40, "RSVD\n"},
{MSG_8852B_OUTSRC_BB_SURA_41, "RSVD\n"},
{MSG_8852B_OUTSRC_BB_SURA_42, "[RA]1 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"},
{MSG_8852B_OUTSRC_BB_SURA_43, "[RA]PER=%x,RDR=%x,r4=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_44, "[RA]2 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"},
{MSG_8852B_OUTSRC_BB_SURA_45, "[RA]3 chk_rate_up_lmt OK: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"},
{MSG_8852B_OUTSRC_BB_SURA_46, "[RA]rate_changed=%x @ rate_check_for_update\n"},
{MSG_8852B_OUTSRC_BB_SURA_47, "[RA]chk rate exist: rate_idx=%x->%x (%x,%x,%x)\n"},
{MSG_8852B_OUTSRC_BB_SURA_48, "[RA]chk_rate_up_lmt=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_49, "[RA]r_idx = %x => per_ma = %x, per_var == %x, decision_offset_n=%x, decision_offset_p=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_50, "[RA]UpFailLimitCnt:%x,m_rtae_up_fail_cnt_lmt:%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_51, "[RA][txrpt]Txcnt=%x, Try=%x, total=%x, OK=%x, Initrate,Giltf=%x,%x, Finalrate,Giltf=%x,%x, BW=%x,wd_not_released=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_52, "[RA][TBTT]ID=%x,Media:%x,Tot=%x,Ok=%x,OK=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_53, "[RA][TBTT][FWfixrate]ID=%x,Media:%x,Tot=%x,Ok=%x,a-OK%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_54, "[RA]Sgi_pending_cnt = %x\n"},
{MSG_8852B_OUTSRC_BB_SURA_55, "[RA][SGI]New rate = %x, Old gi = %x, New gi = %x\n"},
{MSG_8852B_OUTSRC_BB_SURA_56, "[RA][H2C]Mode_sel=%x, gi_ltf=%x, dcm_cap=%x, er_cap=%x, init_rate_lv=%x, ldpc_cap=%x, stbc_cap=%x, arfr_ctrl=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_57, "[RA][H2C]Initial_BW=%x, max_ss_support=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_58, "[RA][H2C]Ra_mask0=%x, ra_mask1=%x, highest_rate=%x, max_start_rate=%x, lowest_rate=%x\n"},
{MSG_8852B_OUTSRC_BB_SURA_59, "[RA][H2C]Initrate: rateidx=%x, mode=%x, gi_ltf=%x, bw_idx=%x\n"},
{MSG_8852B_OUTSRC_END, " out source delimiter end"},
{MSG_8852B_LAST, "Please add your log above."},
};
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.c
|
C
|
agpl-3.0
| 45,419
|
/******************************************************************************
*
* Copyright(c) 2012 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __HAL8852B_FW_LOG__
#define __HAL8852B_FW_LOG__
#include "../../type.h"
enum LOG_MSG_8852B_TABLE {
MSG_8852B_FIRST = 0, //"RESERVED"
MSG_8852B_SAMPLE_NO_PARAMETER, //"Sample without parameter.\n"
MSG_8852B_SAMPLE_PARAMETER, //"Sample string:%s.\n"
MSG_8852B_SAMPLE_INTEGER, //"Sample integer:%d.\n"
MSG_8852B_SAMPLE_INTEGER_X, //"Sample integer:0x%x.\n"
MSG_8852B_SAMPLE_INTEGER_2, //"Sample integer1:%d, integer2:%d.\n"
MSG_8852B_FCUN_NAME, //"%s()\n"
MSG_8852B_MAIN_1, //"FW from host\n"
MSG_8852B_MAIN_2, //"Skip DL FW handler\n"
MSG_8852B_MAIN_3, //"FW from flash\n"
MSG_8852B_MAIN_4, //"Invalid boot mode\n"
MSG_8852B_FWDLHDL_1, //"Invalid boot reason\n"
MSG_8852B_FWDLHDL_2, //"Enter DL FW handler\n"
MSG_8852B_FWDLHDL_3, //"FWHDR H2C done\n"
MSG_8852B_FLASHBOOT, //"Enter flash FW loader\n"
MSG_8852B_IRAMENTRN, //"Load FW RAM code OK\n"
MSG_8852B_FIRSTH2C_1, //"First H2C Enqueue\n"
MSG_8852B_FIRSTH2C_2, //"H2C node malloc fail\n"
MSG_8852B_FIRSTH2C_3, //"H2C node content malloc fail\n"
MSG_8852B_H2CDEQ_1, //"H2C Dequeue\n"
MSG_8852B_H2CDEQ_2, //"H2CPKT enqueue fail\n"
MSG_8852B_H2CPKT_1, //"content = 0x%x 0x%x 0x%x 0x%x\n"
MSG_8852B_RESERVED_ROM, //"RESERVED"
MSG_8852B_CMDTABLE_NAME, //"%s "
MSG_8852B_CMDTABLE_1, //" ?\n"
MSG_8852B_CMDTABLE_2, //" dump bytes, ex: DB 0xb8e00000\n"
MSG_8852B_CMDTABLE_3, //" write bytes, ex: EB 0xb8e00000 0x1\n"
MSG_8852B_CMDTABLE_4, //" dump words, ex: DW 0xb8e00000\n"
MSG_8852B_CMDTABLE_5, //" write words, ex: EW 0xb8e00000, 0x12345678\n"
MSG_8852B_CMDTABLE_6, //" jump to address, ex: j 0xb8900000\n"
MSG_8852B_CMDTABLE_7, //" set debug level\n"
MSG_8852B_CMDTABLE_8, //" set debug compoment bitmap\n"
MSG_8852B_CMDTABLE_9, //" show task info\n"
MSG_8852B_CMDTABLE_10, //" show heap info\n"
MSG_8852B_CMDTABLE_11, //" show dynamic allocate memory info, <index>, <mode>\n"
MSG_8852B_CMDTABLE_12, //" show task time state\n"
MSG_8852B_CMDTABLE_13, //" AXIDMA test\n"
MSG_8852B_CMDTABLE_14, //" SPIC test\n"
MSG_8852B_CMDTABLE_15, //" IDDMA test\n"
MSG_8852B_CMDTABLE_16, //" RXI300 test\n"
MSG_8852B_CMDTABLE_17, //" DLE test\n"
MSG_8852B_CMDTABLE_18, //" HIOE test\n"
MSG_8852B_CMDTABLE_19, //" RPT test\n"
MSG_8852B_CMDTABLE_20, //" MISC test\n"
MSG_8852B_CMDTABLE_21, //" Update STA para for F2PTXCMD\n"
MSG_8852B_CMDTABLE_22, //" Update Common para for F2PTXCMD\n"
MSG_8852B_CMDTABLE_23, //" Wlan Flow Test\n"
MSG_8852B_CMDTABLE_24, //" Wlan Test Mode Setting\n"
MSG_8852B_CMDTABLE_25, //" Wlan Flow with RUA Test\n"
MSG_8852B_CMDTABLE_26, //" Wlan UL Flow Test\n"
MSG_8852B_CMDTABLE_27, //" IPSec test\n"
MSG_8852B_CMDTABLE_28, //" CryptoSig test\n"
MSG_8852B_CMDTABLE_29, //" SecureBoot test\n"
MSG_8852B_CMDTABLE_30, //" Secure eFuse R/W test\n"
MSG_8852B_CMDTABLE_31, //" Plat test\n"
MSG_8852B_CMDTABLE_32, //" H2C/C2H test\n"
MSG_8852B_CMDTABLE_33, //" UL F2PCMD test, <number of STAs>, <frame exchange type>, 0\n"
MSG_8852B_CMDTABLE_34, //" Sounding test\n"
MSG_8852B_CMDTABLE_35, //" security CAM test\n"
MSG_8852B_CMDTABLE_36, //" Gtimer test, <id>, <mode>, <unit>, <duration>\n"
MSG_8852B_CMDTABLE_37, //" PStimer test, <band>, <id>, <mode>, <tsf> (valid if mode = 0)\n"
MSG_8852B_CMDTABLE_38, //" RPWM test\n"
MSG_8852B_CMDTABLE_39, //" DLTXD test\n"
MSG_8852B_CMDTABLE_40, //" PS test\n"
MSG_8852B_CMDTABLE_41, //" 32K CAL test\n"
MSG_8852B_CMDTABLE_42, //" WoW CAM test\n"
MSG_8852B_CMDTABLE_43, //" PS ONOFF test\n"
MSG_8852B_CMDTABLE_44, //" BTCoex test\n"
MSG_8852B_CMDTABLE_45, //" DL Parameters Setting\n"
MSG_8852B_CMDTABLE_46, //" Dump Wlan common info, f2pcmd result, decision result\n"
MSG_8852B_CMDTABLE_47, //" Dump Wlan sta or muru grp info\n"
MSG_8852B_CMDTABLE_48, //" Dump Wlan decision info\n"
MSG_8852B_CMDTABLE_49, //" Dump FW info\n"
MSG_8852B_CMDTABLE_50, //" TFDBG\n"
MSG_8852B_CMDTABLE_51, //" CRT\n"
MSG_8852B_MALLOC_F, //"malloc is failed\n"
MSG_8852B_STRING_0, //"%s\n"
MSG_8852B_STRING_1, //"%s"
MSG_8852B_PARA_INVALID, //"Invalid parameters\n"
MSG_8852B_CMD_UNKNOWN, //"Unknown cmd\n"
MSG_8852B_CONSOLE_1, //"- CMD -\n"
MSG_8852B_CONSOLE_2, //"0x%x: 0x%x\n"
MSG_8852B_CONSOLE_3, //"Jump to 0x%x\n"
MSG_8852B_CONSOLE_4, //"Set dbg level to: 0x%x\n"
MSG_8852B_CONSOLE_5, //"Set dbg component bitmap to: 0x%x\n"
MSG_8852B_CONSOLE_6, //"Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\tCnt\n"
MSG_8852B_CONSOLE_7, //"--------------------------------------------------------------------------------\n"
MSG_8852B_CONSOLE_8, //"Index\t\tStart\t\tTotal(B)\tFree(B)\tMin Free(B)\n"
MSG_8852B_CONSOLE_9, //"------------------------------------------------------------------------\n"
MSG_8852B_CONSOLE_10, //"Address\t\tOwner ID\tFunction\tType\t\tSize(B)\n"
MSG_8852B_CONSOLE_11, //"Owner ID\tFunction\tType\t\tCounter\t\tTotalSize(B)\tHistorical High\n"
MSG_8852B_CONSOLE_12, //"------------------------------------------------------------------------------------------------\n"
MSG_8852B_CONSOLE_13, //"Owner ID\tType\t\tTotalSize(B)\n"
MSG_8852B_CONSOLE_14, //"------------------------------------------------\n"
MSG_8852B_MCC_SEARCHMACID_1, //"[MCC] pmcc_info is NULL!\n"
MSG_8852B_MCC_SEARCHMACID_2, //"[MCC] pgroup_list is empty!\n"
MSG_8852B_MCC_STATUSRPTHDL_1, //"[MCC] MCCStatusRptHDL macid: %d, group: %d, status: %d\n"
MSG_8852B_MCC_STATUSRPTHDL_2, //"[MCC] tsf: 0x%x 0x%x\n"
MSG_8852B_MCC_TBTTSTATUSRPTHDL, //"[MCC] B%dP%d TBTT TSF = 0x%x\n"
MSG_8852B_MCC_MACIDDROP, //"[MCC] MACIDTxIdleCheck fail\n"
MSG_8852B_MCC_ISSUENULLWOLPS_1, //"[MCC][%d][CXEVNT_ENULL]\n"
MSG_8852B_MCC_ISSUENULLWOLPS_2, //"[MCC] Issue null %d fail!!!\n"
MSG_8852B_MCC_ISSUENULL_1, //"[MCC] macid %d role not found\n"
MSG_8852B_MCC_ISSUENULL_2, //"[MCC][%d]Macid %d Null %d, TSF = 0x%x, freerun = 0x%x\n"
MSG_8852B_MCC_TXNULLCHK_1, //"[MCC] mcc group not found\n"
MSG_8852B_MCC_TXNULLCHK_2, //"[MCC] take semaphore fail!\n"
MSG_8852B_MCC_TXNULLCHK_3, //"[MCC][%d]Macid %d TxNull %d SUCCESS, freerun = 0x%x\n"
MSG_8852B_MCC_TXNULLCHK_4, //"[MCC][%d]Macid %d TxNull %d FAIL, freerun = 0x%x\n"
MSG_8852B_MCC_SENDNULLCB_1, //"[MCC][RPT] MACID DROP => macid (%d)\n"
MSG_8852B_MCC_SENDNULLCB_2, //"[MCC][RPT] LIFE DROP => macid (%d)\n"
MSG_8852B_MCC_SENDNULLCB_3, //"[MCC][RPT] invalid RPT (%d)\n"
MSG_8852B_MCC_SWITCHCH_1, //"[MCC] cfg ch FAIL!!!\n"
MSG_8852B_MCC_SWITCHCH_2, //"[MCC] CH SW, CH= %d\n"
MSG_8852B_MCC_SWITCHCH_3, //"[MCC] CH SW WARNING (%d)\n"
MSG_8852B_MCC_SWITCHCH_4, //"[MCC] RFK bypass\n"
MSG_8852B_MCC_CHANGEROLE_1, //"[MCC] MCCMacidDrop fail\n"
MSG_8852B_MCC_CHANGEROLE_2, //"[MCC](courtesy)macid %d => macid %d\n"
MSG_8852B_MCC_CHANGEROLE_3, //"[MCC][%d][CXEVNT_EBT]\n"
MSG_8852B_MCC_CHANGEROLE_4, //"[MCC][%d][CXEVNT_E5G]\n"
MSG_8852B_MCC_CHANGEROLE_5, //"[MCC][%d][CXEVNT_E2G]\n"
MSG_8852B_MCC_CHANGEROLE_6, //"[MCC][%d]Start BT TSF = 0x%x, freerun = 0x%x\n"
MSG_8852B_MCC_CHANGEROLE_7, //"[MCC][%d]Start macid %d TSF = 0x%x, freerun = 0x%x\n"
MSG_8852B_MCC_CHANGEROLE_8, //"[MCC] MCCMacidDropRel fail\n"
MSG_8852B_MCC_FIRSTDURATIONENDHDL_1, //"[MCC] First duration running\n"
MSG_8852B_MCC_FIRSTDURATIONENDHDL_2, //"[MCC][REP/STP] act: %d, deal with old schedule now...\n"
MSG_8852B_MCC_FIRSTDURATIONENDHDL_3, //"[MCC] MCCGroupStop fail\n"
MSG_8852B_MCC_FIRSTDURATIONENDHDL_4, //"[MCC] MCCGroupDel fail\n"
MSG_8852B_MCC_GROUPSTOP_1, //"[MCC] FirstDuration timer del!\n"
MSG_8852B_MCC_GROUPSTOP_2, //"[MCC] replace/pause mode, FirstDuration del bypass!\n"
MSG_8852B_MCC_NEWDURATIONHDL, //"[MCC] Set duration\n"
MSG_8852B_MCC_BITMAPCMP_1, //"[MCC] Release macid %d\n"
MSG_8852B_MCC_BITMAPCMP_2, //"[MCC] Pause macid %d\n"
MSG_8852B_MCC_H2CADDMCCHDL_1, //"[MCC] Add MCC macid %d to group %d\n"
MSG_8852B_MCC_H2CADDMCCHDL_2, //"[MCC] macid: %d, duration: %d, bt_in_2g: %d\n"
MSG_8852B_MCC_H2CADDMCCHDL_3, //"[MCC] Add MCC band %d port %d\n"
MSG_8852B_MCC_H2CSTARTMCCHDL_1, //"[MCC] Start MCC group %d from macid %d\n"
MSG_8852B_MCC_H2CSTARTMCCHDL_2, //"[MCC][REP/STP] Group new idx: %d, old idx: %d, act: %d\n"
MSG_8852B_MCC_H2CSTOPMCCHDL_1, //"[MCC][stop]prev_groups: %d\n"
MSG_8852B_MCC_H2CSTOPMCCHDL_2, //"[MCC][stop]stop group %d fail\n"
MSG_8852B_MCC_H2CSTOPMCCHDL_3, //"[MCC][stop]group %d stop!\n"
MSG_8852B_MCC_H2CDELMCCGROUPHDL_1, //"[MCC][Del] prev_groups: %d\n"
MSG_8852B_MCC_H2CDELMCCGROUPHDL_2, //"[MCC][del]del group %d fail\n"
MSG_8852B_MCC_H2CDELMCCGROUPHDL_3, //"[MCC][del]group %d del!\n"
MSG_8852B_MCC_H2CMCCREQTSFHDL_1, //"[MCC] macid %d is not in role table\n"
MSG_8852B_DEBUGINFO_1, //"ISR Name\tCount\t\tExec Time(historical high)\n"
MSG_8852B_DEBUGINFO_2, //"------------------------------------------------\n"
MSG_8852B_DEBUGINFO_3, //"\t%d\t\t%d_%d\n"
MSG_8852B_DEBUGINFO_4, //"\t\t%d\t\t%d_%d\n"
MSG_8852B_DEBUGINFO_5, //"[Error] ISRInfo len = %d!\n"
MSG_8852B_PROFILING_1, //"func_name %s , "
MSG_8852B_PROFILING_2, //"line %d , cycle %d , offset = %d\n"
MSG_8852B_WLANDUMP_0, //"Tx ok packet cnt: %d\n Tx fail packet cnt: %d\n Txcmd success cnt: %d\n Txcmd abort (MU-RTS/RTS fail) cnt: %d\n Txcmd abort (over SP) cnt: %d\n"
MSG_8852B_WLANDUMP_1, //"Txcmd sounding abort cnt: %d\n Txcmd abort (pri user fail) cnt: %d\n Txcmd abort ( cca or medium busy) cnt: %d\n Txcmd RU/MU2SU cnt: %d\n"
MSG_8852B_WLANDUMP_2, //"chkcmd_sts cnt: %d %d %d %d %d %d\n"
MSG_8852B_WLANDUMP_3, //"TBD"
MSG_8852B_WLANDUMP_4, //"DL Txcmd in last TXOP cnt: %d\n UL Txcmd in last TXOP cnt: %d\n Empty DL SS2F report cnt: %d\n Empty UL SS2F report cnt: %d\n DL TxcmdQ empty cnt: %d\n"
MSG_8852B_WLANDUMP_5, //"Issue DL SU Txcmd cnt: %d\n Issue DL MU Txcmd cnt: %d\n Issue DL RU Txcmd cnt: %d\n Issue UL Txcmd cnt: %d\n f2p_Triggerpkt_cnt=%d\n"
MSG_8852B_WLANDUMP_6, //"Decision MU2SU cnt: %d\n Decision RU2SU cnt: %d\n DLDecision Result record: %x\n Decision SU_FORCESU cnt: %d\n Decision MU_FORCEMU cnt: %d\n"
MSG_8852B_WLANDUMP_7, //"Decision SU_FORCEMU_FAIL cnt: %d\n Decision SU_FORCERU_FAIL cnt: %d\n Decision SU_FORCERU_RUARST_RU2SU cnt: %d\n Decision SU_NOT4_USER cnt: %d\n Decision RU_FORCERU_RUSRST_FIXTBL cnt: %d\n"
MSG_8852B_WLANDUMP_8, //"Decision RU_FORCERU cnt: %d\n Decision SU_WDINFO_USERATE cnt: %d\n Decision SU_PRINULLWD cnt: %d\n ecision MU_BYPASS_MUTPCOMPARE cnt: %d\n Decision SU_MUTXTIME_PASS_MU_NOTSUPPORT cnt: %d\n"
MSG_8852B_WLANDUMP_9, //"Decision SU_MUTXTIME_FAIL_RU_NOTSUPPORT cnt: %d\n Decision SU_RUARST_RU2SU cnt: %d\n Decision RU_RUARST_FIXTBL cnt: %d\n Decision MU_TPCOMPARE_RST cnt: %d\n Decision RU_TPCOMPARE_RST cnt: %d\n Decision SU_TPCOMPARE_RST cnt: %d\n"
MSG_8852B_WLANDUMP_10, //"fw txcmdQ[0] cmd num: %d, fw txcmdQ[1] cmd num: %d,fw txcmdQ[2] cmd num: %d,fw txcmdQ[3] cmd num: %d,fw txcmdQ[4] cmd num: %d\n"
MSG_8852B_WLANDUMP_11, //"fw txcmdQ[5] cmd num: %d, fw txcmdQ[6] cmd num: %d,fw txcmdQ[7] cmd num: %d,fw txcmdQ[8] cmd num: %d,fw txcmdQ[9] cmd num: %d, fw txcmdQ[10] cmd num: %d\n"
MSG_8852B_WLANDUMP_12, //TBD
MSG_8852B_WLANDUMP_13, //"mbid0~7: %d %d %d %d %d %d %d %d\n"
MSG_8852B_WLANDUMP_14, //"macid %d info:\n isHESTA =%d\n AID12 =%d\n DL_BW =%d\n DL_T_PE =%d\n"
MSG_8852B_WLANDUMP_15, //"TF_MAC_Padding =%d\n force tx su =%d\n force tx mu =%d\n fw force mu2su TH = %d\n force tx ru =%d\n"
MSG_8852B_WLANDUMP_16, //"txok_pkt =%d\n txfail pkt cnt: %d\n retry_cnt =%d\n mbssid_idx =%d\n ulgroup_bitmap =%d\n null_wd_cnt =%d\n"
MSG_8852B_WLANDUMP_17, //"ul_sw_grp_bitmap =%d\n AMPDU_max_txtime =%d\n mu_doppler_ctrl =%d\n mu_gi_ltf =%d\n mu decision txtime_bypass =%d\n mu decision mutp_bypass =%d\n"
MSG_8852B_WLANDUMP_18, //"mu_maxinitrate = %x\n mu_maxfinalrate = %x\n mu_mininitrate = %x\n mu_minfinalrate = %x\n mu primary cnt = %d\n"
MSG_8852B_WLANDUMP_19, //" PwrBit =%d\n TP =%d Mbps\n Max Txlen = %x (unit23 byte)\n Min Txlen = %x (unit23 byte)\n Last Txlen = %x (unit23 byte)\n Last BSRlen = %x (unit256 byte) AC=%d\n"
MSG_8852B_WLANDUMP_20, //"mu sta %d info\n mu sta macid= %d\n"
MSG_8852B_WLANDUMP_21, //"mu sta rate array(8bit) 0-4: %x %x %x %x %x"
MSG_8852B_WLANDUMP_22, //"mu sta rate array(8bit) 5-9: %x %x %x %x %x"
MSG_8852B_WLANDUMP_23, //"su ok pkt cnt = %d\n su fail pkt cnt = %d\n su_norsp_pktcnt = %d\n SU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n SU TXCNT 1/<6/<16/>=16 : %d %d %d %d\n"
MSG_8852B_WLANDUMP_24, //"mu ok pkt cnt = %d\n mu fail pkt cnt = %d\n mu_norsp_pktcnt = %d\n mu2su ok pkt cnt = %d\n mu2su fail pkt cnt = %d\n"
MSG_8852B_WLANDUMP_25, //"ru ok pkt cnt = %d\n ru fail pkt cnt = %d\n"
MSG_8852B_WLANDUMP_26, //"MU TOTALPKTNUM 1~16/17~32/33~64/>65 : %d %d %d %d, OK=0: %d\n MU DIFF <4/<8/<12/>=12 : %d %d %d %d\n"
MSG_8852B_WLANDUMP_27, //"MU TXCNT 1/<6/<16/>=16: %d %d %d %d\n
MSG_8852B_WLANDUMP_28, //"pktmaxtxcnt(su base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu base) [0]= %d [1]= %d [2]= %d \n pktmaxtxcnt(mu2nd base) [0]= %d [1]= %d [2]= %d \n"
MSG_8852B_WLANDUMP_30, //"F2PTXCMDRPT cnt= %d, SS2FWRPT cnt =%d, TXRPT cnt =%d, PLDRLSRPT cnt = %d\n"
MSG_8852B_WLANDUMP_31, //"pkt_max_queue_time = %x, pkt_min_queue_time=%x\n"
MSG_8852B_WLANDUMP_32, //"TWT %d info:\n Txcmd overSP= %d\n Txcmd pri user fail= %d\n DL cmdCnt inSP= %d\n UL cmdCnt inSP= %d\n"
MSG_8852B_WLANDUMP_33, //"DL cmdCnt all= %d\n UL cmdCnt all= %d\n UL fixmode = %x\n cur cmd num = %x\n SP 1st TF fail cnt = %x\n"
MSG_8852B_WLANDUMP_34, //"start_d= %d\n start_t= %d\n endearly_d= %d\n endearly_t= %d\n end_d= %d\n"
MSG_8852B_WLANDUMP_35, //"end_t= %d\n timer_qrydl= %d\n timer_qryul= %d\n start_qrydl= %d\n total_qryul=%d\n"
MSG_8852B_WLANDUMP_36, //"firstTF_fail = %d,%d\n"
MSG_8852B_WLANDUMP_37, //"twt_decision_brk = %d, %d, %d, %d, %d, %d, %d, %d\n"
MSG_8852B_WLANDUMP_38, //"twt_decision_rst= %d, %d, %d\n"
MSG_8852B_WLANDUMP_39, //"twt_ACdecision_rst= %d, %d, %d, %d\n"
MSG_8852B_WLANDUMP_40, //"twt_validdlss2f_cnt= %d, twt_emptydlss2f_cnt= %d, twt_validulss2f_cnt= %d, twt_emptyulss2f_cnt= %d, twt_dlss2f_fromquery= %d, twt_dlss2f_fromtxcmd=%d, twt_ulss2f_fromquery= %d, twt_ulss2f_fromtxcmd=%d\n"
MSG_8852B_WLANDUMP_41, //"TWT member: %d %d %d %d %d\n"
MSG_8852B_WLANDUMP_42, //"twt_dlss2f_qrycnt[0]=%d,twt_dlss2f_qrycnt[1]=%d,twt_dlss2f_qrycnt[2]=%d,twt_dlss2f_qrycnt[3]=%d\n"
MSG_8852B_WLANDUMP_43, //"reform_fail_rst[0]=%d, reform_fail_rst[1]=%d, reform_fail_rst[2]=%d, reform_fail_rst[3]=%d, reform_fail_rst[4]=%d\n"
MSG_8852B_WLANDUMP_44, //"MACID WD count BE:%d BK:%d VI:%d VO:%d\n"
MSG_8852B_WLANDUMP_45, //"PPS F2PCMD_PPS:%d/s TXRPT_PPS:%d/s TXPKT_PPS:%d/s SS2F_0_PPS:%d/s SS2F_1_PPS:%d/s SS2F_2_PPS:%d/s"
MSG_8852B_ROLE_1, //"B%dP%d RXBCNOK\n"
MSG_8852B_ROLE_2, //"B%dP%d BCNNOHIT\n"
MSG_8852B_ROLE_3, //"Role idx search fail\n
MSG_8852B_ROLE_4, //"=>CreateRole\n"
MSG_8852B_ROLE_5, //"[FAIL] Role info alloc fail!\n"
MSG_8852B_ROLE_6, //"[FAIL] Role info - PPSDbgParm alloc fail!\n"
MSG_8852B_ROLE_7, //"[FAIL] Role info - PTWTParam alloc fail!\n"
MSG_8852B_ROLE_8, //"[CreateRole] ActRole=%d, LinkRole=%d.\n
MSG_8852B_ROLE_9, //"[CreateRole] band=%d, port=%d, macid=%d.\n"
MSG_8852B_ROLE_10, //"=>DelRole\n"
MSG_8852B_ROLE_11, //"[Warn] ROLE_NOT_EXIST for DelRole!\n"
MSG_8852B_ROLE_12, //"[DelRole] ActRole=%d!role_idx=%d\n"
MSG_8852B_ROLE_13, //"Role idx search by macid fail\n"
MSG_8852B_ROLE_14, //"[WARN] Role exist for macid=0x%x! role_idx=0x%x\n"
MSG_8852B_ROLE_15, //"[FAIL] Create Role idx > max_number!\n"
MSG_8852B_ROLE_16, //"[FAIL] Create Role fail!\n"
MSG_8852B_ROLE_17, //"[Warn] search role fail for JoinInfo!\n"
MSG_8852B_ROLE_18, //"[FAIL] JoinInfo Role idx > max_number!\n"
MSG_8852B_ROLE_19, //"[WARN] Role exist for macid=0x%x! role_idx=0x%x\n"
MSG_8852B_ROLE_20, //"[Warn] search role fail for DelRole!\n"
MSG_8852B_ROLE_21, //"[FAIL] Del Role idx > max_number!\n"
MSG_8852B_PMF_00, //"start saquery timer fail\n"
MSG_8852B_PMF_01, //"start saquery timer\n"
MSG_8852B_PMF_02, //"creat saquery timer fail\n"
MSG_8852B_PMF_03, //"saquery timer is lanched alread\n"
MSG_8852B_PMF_04, //"SA Query timer deleted!\n"
MSG_8852B_PMF_05, //"Deauth content\n"
MSG_8852B_PMF_06, //"packet_len_no_fcs error\n"
MSG_8852B_PMF_07, //"ICV Error ok\n"
MSG_8852B_PMF_08, //"encrypted deauth frame, SEC_TYPE: 0x%x) \n"
MSG_8852B_PMF_09, //"not Encrypted Deauth/Disassoc\n"
MSG_8852B_PMF_10, //"deauth_reason = %x %x\n"
MSG_8852B_PMF_11, //"tx_sa_query_result = 0x%x\n"
MSG_8852B_PMF_12, //"issue saquery req fail\n"
MSG_8852B_PMF_13, //"ignore the deauth frame\n"
MSG_8852B_PMF_14, //"ICV Error\n"
MSG_8852B_PMF_15, //"bip_result=0x%x\n"
MSG_8852B_PMF_16, //"\npacket_len_no_fcs error\n"
MSG_8852B_PMF_17, //"\nOn SA Query Req! (len=0x%x)\n"
MSG_8852B_PMF_18, //"issue saquery rsp fail\n"
MSG_8852B_PMF_19, //"\nOn SA Query Resp!(len=0x%x)\n"
MSG_8852B_PMF_20, //"issue_sa_query_timeout_hdl!\n"
MSG_8852B_PMF_21, //"Deauth wake up!\n"
MSG_8852B_PMF_22, //"can't get offload PKT for saquery\n"
MSG_8852B_PMF_23, //"can't allocate sendpkt_buff \n"
MSG_8852B_PMF_24, //"FW IPN > pkt IPN\n"
MSG_8852B_PMF_25, //"FW IPN < pkt IPN\n"
MSG_8852B_PMF_26, //"FW IPN == pkt IPN\n"
MSG_8852B_PMF_27, //"IPSecAESECBInit false\n"
MSG_8852B_PMF_28, //"IPSecAESECBEncrypt false\n"
MSG_8852B_PMF_30, //"key_len = %d, false\n"
MSG_8852B_PMF_31, //"iv_len = %d, false\n"
MSG_8852B_PMF_32, //"IPSecInitWithISRDisable false\n"
MSG_8852B_PMF_40, //"MIC check fail\n"
MSG_8852B_PMF_41, //"\n: aes_gmac fail!\n"
MSG_8852B_PMF_42, //"\n: _bip_gcmp_protect(128) fail!\n"
MSG_8852B_PMF_43, //"\n: _bip_gcmp_protect(256) fail!\n"
MSG_8852B_PMF_44, //"\n: unsupport dot11wCipher !\n"
MSG_8852B_PMF_45, //"not a management frame\n"
MSG_8852B_PMF_46, //"is a beacon\n"
MSG_8852B_PMF_47, //"not a broadcast frame\n"
MSG_8852B_PMF_48, //"packet too small\n"
MSG_8852B_PMF_49, //"elemnt_id != 0x4c\n"
MSG_8852B_PMF_50, //"is_bip_enc_frameComm return TRUE\n"
MSG_8852B_PMF_51, //"\nbip_verifyComm: PKT (len=0x%x)\n"
MSG_8852B_PMF_52, //"BSSID not match\n"
MSG_8852B_PMF_53, //"ori_len = 0x%x\n"
MSG_8852B_PMF_54, //"SW BIP DEC FAIL\n"
MSG_8852B_PMF_55, //"NOT encrypted\n"
MSG_8852B_PMF_56, //"IPN verify Fail\n"
MSG_8852B_PMF_57, //"bip_verifyComm return TRUE\n"
MSG_8852B_PMF_58, //"protection bit is not 1\n"
MSG_8852B_PMF_59, //"not a unicast frame\n"
MSG_8852B_PMF_60, //"PairwiseEncAlg not GCMP\n"
MSG_8852B_PMF_61, //"aes_gcm_ad fail\n"
MSG_8852B_PMF_62, //"aes_gcm_ae fail\n"
MSG_8852B_RXFLOW_1, //"can't allocate wlan pktbuf\n"
MSG_8852B_RXFLOW_2, //"DD=%x\n"
MSG_8852B_RXFLOW_3, //"A=%x\n"
MSG_8852B_RXFLOW_4, //"B=%x\n"
MSG_8852B_RXFWD_1, //"Unsupported index!\n"
MSG_8852B_WLAN_1, //"SS Query Report HW stuck!!\n"
MSG_8852B_SECCAM_1, //"Search key, mac_id : %d, key_id : %d, key_type : %d , fail\n"
MSG_8852B_SECCAM_2, //"Search key success\nMac_id : %d, key_id : %d, key_type : %d, key cam index : %d\n"
MSG_8852B_SECCAM_3, //"Wowlan rekey %d, %d, %d\n"
MSG_8852B_SECCAM_4, //"check addr key index full\n"
MSG_8852B_SECCAM_5, //"Free cam index: %d\n"
MSG_8852B_SECCAM_6, //"insertKeyAddrCam ret : %d\n"
MSG_8852B_RPTHDL_1, //"pldrlsrpt len %d not align\n"
MSG_8852B_RPTHDL_2, //"RlsRptHDLRAM8852B,rpt_num=%x,len=%x\n"
MSG_8852B_RPTHDL_3, //"ERR: TxCmdRptHDL get NULL txinfo node,rpt->QSEL=%x, (rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n"
MSG_8852B_RPTHDL_4, //"ERR: TxRptHDL get NULL txinfo node,rpt->QSEL=%x,(rpt->FW_DEFINE & MAX_TXCMD_SEQ_MSK)=%x\n"
MSG_8852B_RPTHDL_5, //"ERR: TfRptHDL get NULL txinfo node\n"
MSG_8852B_RPTHDL_6, //"SS2FInfoDeQ8852B\n"
MSG_8852B_RPTHDL_7, //"F2PTXCMDRPT HDL\n"
MSG_8852B_RPTHDL_8, //"SS2FWRPT HDL\n"
MSG_8852B_RPTHDL_9, //"TFRPT HDL\n"
MSG_8852B_RPTHDL_10, //"TXBCNRPT HDL\n"
MSG_8852B_RPTHDL_11, //"CCXRPT HDL\n"
MSG_8852B_RPTHDL_12, //"TXRPT HDL\n"
MSG_8852B_RPTHDL_13, //"PLDRLSRPT HDL\n"
MSG_8852B_ERRHDL_1, //"[ERR]DLE Timeout(idx = %d)\n"
MSG_8852B_ERRHDL_2, //"[ERR]AXIDMA is not idle!\n"
MSG_8852B_ERRHDL_3, //"[ERR]STA scheduler init\n"
MSG_8852B_ERRHDL_4, //"[ERR]WDE cfg ready\n"
MSG_8852B_ERRHDL_5, //"[ERR]PLE cfg ready\n"
MSG_8852B_ERRHDL_6, //"=>DmaTopStuck:FA sts: %d, data: %d!\n"
MSG_8852B_ERRHDL_7, //"=>DmaTopStuck:FA!\n"
MSG_8852B_ERRHDL_8, //"=>DmaTopStuck:know!\n"
MSG_8852B_ERRHDL_9, //"=>RecoveryCMAC!\n"
MSG_8852B_ERRHDL_10, //"[ERR]BBRPT CHIF\n"
MSG_8852B_ERRHDL_11, //"[ERR]Check CMAC_idle\n"
MSG_8852B_ERRHDL_12, //"[ERR]PTCL tx\n"
MSG_8852B_ERRHDL_13, //"[ERR]L0 promote event %x\n"
MSG_8852B_ERRHDL_14, //"[ERR][C2H]Previous: %x; Current: %x\n"
MSG_8852B_ERRHDL_15, //"ErrHDL in!\n"
MSG_8852B_ERRHDL_16, //"ErrHDL out!\n"
MSG_8852B_ERRHDL_17, //"DMAC error: %x\n"
MSG_8852B_ERRHDL_18, //"CMAC0 error: %x\n"
MSG_8852B_ERRHDL_19, //"CMAC1 error: %x\n"
MSG_8852B_ERRHDL_20, //"notify: %x\n"
MSG_8852B_ERRHDL_21, //"--->\n err=%x\n"
MSG_8852B_ERRHDL_22, //"R_AX_SER_DBG_INFO =%x\n"
MSG_8852B_ERRHDL_23, //"R_AX_DMAC_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_24, //"R_AX_WDE_ERR_FLAG_CFG_NUM1 =%x\n"
MSG_8852B_ERRHDL_25, //"R_AX_PLE_ERR_FLAG_CFG_NUM1 =%x\n"
MSG_8852B_ERRHDL_26, //"R_AX_WDRLS_ERR_IMR =%x "
MSG_8852B_ERRHDL_27, //"R_AX_WDRLS_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_28, //"R_AX_RPQ_RXBD_IDX =%x\n"
MSG_8852B_ERRHDL_29, //"R_AX_SEC_DEBUG =%x\n"
MSG_8852B_ERRHDL_30, //"R_AX_MPDU_TX_ERR_IMR =%x "
MSG_8852B_ERRHDL_31, //"R_AX_MPDU_TX_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_32, //"R_AX_MPDU_RX_ERR_IMR =%x "
MSG_8852B_ERRHDL_33, //"R_AX_MPDU_RX_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_34, //"R_AX_STA_SCHEDULER_ERR_IMR =%x "
MSG_8852B_ERRHDL_35, //"R_AX_STA_SCHEDULER_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_36, //"R_AX_WDE_ERR_IMR=%x "
MSG_8852B_ERRHDL_37, //"R_AX_WDE_ERR_ISR=%x\n"
MSG_8852B_ERRHDL_38, //"R_AX_PLE_ERR_IMR=%x "
MSG_8852B_ERRHDL_39, //"R_AX_PLE_ERR_FLAG_ISR=%x\n"
MSG_8852B_ERRHDL_40, //"R_AX_TXPKTCTL_ERR_IMR_ISR=%x\n"
MSG_8852B_ERRHDL_41, //"R_AX_TXPKTCTL_ERR_IMR_ISR_B1=%x\n"
MSG_8852B_ERRHDL_42, //"R_AX_PKTIN_ERR_IMR =%x "
MSG_8852B_ERRHDL_43, //"R_AX_PKTIN_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_44, //"R_AX_PKTIN_ERR_IMR =%x "
MSG_8852B_ERRHDL_45, //"R_AX_PKTIN_ERR_ISR =%x\n"
MSG_8852B_ERRHDL_46, //"R_AX_HOST_DISPATCHER_ERR_IMR=%x "
MSG_8852B_ERRHDL_47, //"R_AX_HOST_DISPATCHER_ERR_ISR=%x\n"
MSG_8852B_ERRHDL_48, //"R_AX_CPU_DISPATCHER_ERR_IMR=%x "
MSG_8852B_ERRHDL_49, //"R_AX_CPU_DISPATCHER_ERR_ISR=%x\n"
MSG_8852B_ERRHDL_50, //"R_AX_CPUIO_ERR_IMR=%x "
MSG_8852B_ERRHDL_51, //"R_AX_CPUIO_ERR_ISR=%x\n"
MSG_8852B_ERRHDL_52, //"R_AX_BBRPT_COM_ERR_IMR_ISR=%x\n"
MSG_8852B_ERRHDL_53, //"0xC164=%x\n"
MSG_8852B_ERRHDL_54, //"R_AX_SCHEDULE_ERR_IMR=%x "
MSG_8852B_ERRHDL_55, //"R_AX_SCHEDULE_ERR_ISR=%x\n"
MSG_8852B_ERRHDL_56, //"R_AX_PTCL_IMR0=%x "
MSG_8852B_ERRHDL_57, //"R_AX_PTCL_ISR0=%x\n"
MSG_8852B_ERRHDL_58, //"R_AX_DLE_CTRL=%x\n"
MSG_8852B_ERRHDL_59, //"R_AX_PHYINFO_ERR_IMR=%x\n"
MSG_8852B_ERRHDL_60, //"R_AX_TXPWR_IMR= N/A "
MSG_8852B_ERRHDL_61, //"R_AX_TXPWR_ISR= N/A\n"
MSG_8852B_ERRHDL_62, //"R_AX_DBGSEL_TRXPTCL=%x "
MSG_8852B_ERRHDL_63, //"R_AX_PHYINFO_ERR_IMR=%x\n"
MSG_8852B_ERRHDL_64, //"R_AX_TMAC_ERR_IMR_ISR=%x "
MSG_8852B_ERRHDL_65, //"R_AX_DBGSEL_TRXPTCL=%x\n"
MSG_8852B_ERRHDL_66, //"<---\n"
MSG_8852B_MAIN_00, //"SW Queue reCreate\n"
MSG_8852B_MAIN_01, //"Enter AXIDMA_init... \n"
MSG_8852B_MAIN_02, //"WDT_timer start... \n"
MSG_8852B_MAIN_03, //"InitHWPostDLRAM done\n"
MSG_8852B_MAIN_04, //"InitFWFuncPostDL RAM done\n"
MSG_8852B_MAIN_05, //"MAC per STAInfo %d bytes\n"
MSG_8852B_MAIN_06, //"BB per STAInfo %d bytes\n"
MSG_8852B_MAIN_07, //"InitWLANFuncRAM done\n"
MSG_8852B_MAIN_08, //"Enter test id (0~7): "
MSG_8852B_MAIN_09, //"%c\n"
MSG_8852B_MAIN_10, //"Thread Metric: %d\n"
MSG_8852B_MAIN_11, //"Test duration: %d seconds\n"
MSG_8852B_MAIN_14, //"WDT_timer start fail \n"
MSG_8852B_MAIN_15, //" SysMib.PInternal->PDebugInfo->DbgLvl =%x\n"
MSG_8852B_MAIN_16, //"Enter flash FW loader\n
MSG_8852B_IRAMENTRY_00, //"Function ptr length :RAM %x,ROM %x\n"
MSG_8852B_IRAMENTRY_01, //"Function ptr length not equal!!\n"
MSG_8852B_IRAMENTRY_02, //"Start Init PLE memory\n"
MSG_8852B_IRAMENTRY_03, //"PLE data check error!!!"
MSG_8852B_IRAMENTRY_04, //"PLE usage :%x\n"
MSG_8852B_IRAMENTRY_05, //"Initializing RAM bss ...\n"
MSG_8852B_IRAMENTRY_06, //"_BSS_RAM_START_ : %x\t _BSS_RAM_END_ : %x\n"
MSG_8852B_IRAMENTRY_07, //"B cut\n"
MSG_8852B_IRAMENTRY_08, //"_RAM_FUNCPTR_START_ : %x\t _RAM_FUNCPTR_END_ : %x\n"
MSG_8852B_IRAMENTRY_09, //"_ROM_FUNCPTR_START_ : %x\t _ROM_FUNCPTR_END_ : %x\n"
MSG_8852B_IRAMENTRY_10, //"C cut\n"
MSG_8852B_IRAMENTRY_11, //"_RAM_CCUT_FUNCPTR_START_ : %x\t _RAM_CCUT_FUNCPTR_END_ : %x\n"
MSG_8852B_IRAMENTRY_12, //"_ROM_CCUT_FUNCPTR_START_ : %x\t _ROM_CCUT_FUNCPTR_END_ : %x\n"
MSG_8852B_IRAMENTRY_13, //"D cut\n"
MSG_8852B_IRAMENTRY_14, //"_RAM_DCUT_FUNCPTR_START_ : %x\t _RAM_DCUT_FUNCPTR_END_ : %x\n"
MSG_8852B_IRAMENTRY_15, //"_ROM_DCUT_FUNCPTR_START_ : %x\t _ROM_DCUT_FUNCPTR_END_ : %x\n"
MSG_8852B_IRAMENTRY_16, //"Load FW RAM code OK\n"
MSG_8852B_BACKTRACE_00, //"Heap space is not enough for backtrace.......\n"
MSG_8852B_BACKTRACE_01, //"Backtrace......\n"
MSG_8852B_BACKTRACE_02, //"Next SP:%x, Next RA:%x\n"
MSG_8852B_BACKTRACE_03, //"Backtrace is failed\n"
MSG_8852B_BACKTRACE_04, //"Done\n"
MSG_8852B_BACKTRACE_05, //"EPC: %x, Cause: %x, BADVADDR: %x, Status: %x\n"
MSG_8852B_BACKTRACE_06, //"hi: %x, lo: %x, ra: %x, fp: %x\n"
MSG_8852B_BACKTRACE_07, //"sp: %x, gp: %x, t9: %x, t8: %x\n"
MSG_8852B_BACKTRACE_08, //"s7: %x, s6: %x, s5: %x, s4: %x\n"
MSG_8852B_BACKTRACE_09, //"s3: %x, s2: %x, s1: %x, s0: %x\n"
MSG_8852B_BACKTRACE_10, //"t7: %x, t6: %x, t5: %x, t4: %x\n"
MSG_8852B_BACKTRACE_11, //"t3: %x, t2: %x, t1: %x, t0: %x\n"
MSG_8852B_BACKTRACE_12, //"a3: %x, a2: %x, a1: %x, a0: %x\n"
MSG_8852B_BACKTRACE_13, //"v1: %x, v0: %x, at: %x\n"
MSG_8852B_BACKTRACE_14, //"not send c2hHalt\n"
MSG_8852B_BACKTRACE_15, //"no loop\n"
MSG_8852B_BACKTRACE_16, //"Something wrong when allocating backtrace memory\n"
MSG_8852B_BACKTRACE_17, //"Backtrace memory is full!!\n"
MSG_8852B_BACKTRACE_18, //"Init Backtrace Memory failed\n"
MSG_8852B_PSTIMER_00, //"handle task:%x\n"
MSG_8852B_PSTIMER_01, //"handle tsf: %x\n"
MSG_8852B_PSTIMER_02, //"tsf in list: %x\n"
MSG_8852B_AXIDMA_00, //"[ERR] AXIDMA is not idle!\n"
MSG_8852B_AXIDMA_01, //"[ERR] AXIDMA is not enable\n"
MSG_8852B_AXIDMA_02, //"[AXIDMA RX Init]Allocate H2C buffer fail 123\n"
MSG_8852B_AXIDMA_03, //"[AXIDMA RX Init]Allocate PKT buffer fail\n"
MSG_8852B_AXIDMA_04, //"[AXIDMA RX Init]Allocate RPT buffer fail\n"
MSG_8852B_PORT_00, //"Assert at file: %s, line: %u\n"
MSG_8852B_PORT_01, //"not send c2hHalt\n"
MSG_8852B_PORT_02, //"no loop\n"
MSG_8852B_PORT_03, //"Watch dog timeout in critical section\n"
MSG_8852B_PORT_04, //"Watch dog remain: %d(us)\n"
MSG_8852B_PORT_05, //"Exec Time %x ~ %x: %d(us)\n"
MSG_8852B_RXI300_00, //"EPC Value: %x\n"
MSG_8852B_RXI300_01, //"Error id is inexistent(%x)!\n"
MSG_8852B_RXI300_02, //"Error code is inexistent(%x)!\n"
MSG_8852B_RXI300_03, //"RXI300_ERR_SRC_APB_DEF_SLV"
MSG_8852B_RXI300_04, //"RXI300_ERR_SRC_AXI_APB_SA"
MSG_8852B_RXI300_05, //"Error source is inexistent(%x)!\n"
MSG_8852B_RXI300_06, //"HaltC2H = %x, Error address = %x!\n"
MSG_8852B_RXI300_07, //"Clear interrupt fail!\n"
MSG_8852B_RXI300_08, //"RA/SP Value: %x, %x\n"
MSG_8852B_PS_CHK_PLATFORM_ERR_1, //"DMAC error: %x\n"
MSG_8852B_PS_CHK_PLATFORM_ERR_2, //"CMAC%d error: %x\n"
MSG_8852B_PS_DDMA_BUFFER_SIZE_OVERFLOW, //"MAC%d DDMA buffer size (%x) is overflow!\n"
MSG_8852B_PS_HIOE_START_ADDR, //"LPS HIOE start address = %x, size = %x\n"
MSG_8852B_PS_HIOE_END_ADDR, //"LPS HIOE end address = %x\n"
MSG_8852B_PS_HIOE_INST_OVERFLOW, //"LPS HIOE instruction is overflow! inst_size(%x).\n"
MSG_8852B_PS_HIOE_READ_PCIEMIO_FAIL, //"[Err] ReadPCIEMIO Fail! reg = %x\n"
MSG_8852B_PS_HIOE_WRITE_PCIEMIO_FAIL, //"[Err] WritePCIEMIO Fail! reg = %x\n"
MSG_8852B_PS_HIOE_BACKUP_FAIL, //"BKP fail st.(%x)\n"
MSG_8852B_PS_HIOE_RESTORE_FAIL, //"RES fail st.(%x)\n"
MSG_8852B_PS_HIOE_INVALID_STATE, //"Invalid st.(%x)\n"
MSG_8852B_PS_HIOE_BACKUP_TIMEOUT, //"Bkp (%d) polling timeout!\n"
MSG_8852B_PS_HIOE_RESTORE_TIMEOUT, //"Res polling timeout!\n"
MSG_8852B_PS_ENTER_32K, //">C\n"
MSG_8852B_PS_LEAVE_32K, //"<C\n"
MSG_8852B_PS_RESET_BD_POLLING_TIMEOUT, //"Reset BD polling timeout! val(%d)\n"
MSG_8852B_PS_BACKUP_MAC_FAIL, //"BkpMAC (%d) start fail!!\n"
MSG_8852B_PS_BACKUP_MAC_TIMEOUT, //"BkpMAC (%d) polling timeout! idx=%x!\n"
MSG_8852B_PS_RESTORE_MAC_FAIL, //"RestoreMAC (%d) start fail!!\n"
MSG_8852B_PS_RESTORE_MAC_TIMEOUT, //"RestoreMAC (%d) polling timeout! idx=%x!\n"
MSG_8852B_PS_TIMER_STOP_FAIL, //"[32K] timer (%d) stop FAIL!\n"
MSG_8852B_PS_TIMER_START_FAIL, //"[32K] timer (%d) start FAIL!\n"
MSG_8852B_PS_DISABLE_HCIDMA_FAIL, //"Disable HCI TX DMA FAIL!\n"
MSG_8852B_PS_READ_PCIEMIO_FAIL, //"[Err] ReadPCIEMIO Fail! reg = %x\n"
MSG_8852B_PS_WRITE_PCIEMIO_FAIL, //"[Err] WritePCIEMIO Fail! reg = %x\n"
MSG_8852B_PS_32K_STATUS, //"LPS Status: %x\n"
MSG_8852B_PS_32K_ERROR, //"LPS Error: %x\n"
MSG_8852B_PS_32K_INFO, //"LPS Info: %x\n"
MSG_8852B_PS_SLEEP_TIME, //"[Sleep Time] Expect=%x, Complete=%x\n"
MSG_8852B_PS_TIMING_LOG_1, //"[PST] ResPG Analysis(us): %d, MAC: %d, BB: %d, RF: %d\n"
MSG_8852B_PS_TIMING_LOG_2, //"[PST] Res timer(us): %d us, MAC1st backup: %d, MAC everytime backup: %d, Enable WDE/PLE: %d\n"
MSG_8852B_PS_TIMING_LOG_3, //"[PST] RFK(us): %d, DACK: %d, Radio: %d, RFC: %d\n"
MSG_8852B_PS_TIMING_LOG_4, //"[PST] T2 ClkUp to OpenRF: %d us\n"
MSG_8852B_PS_TIMING_LOG_5, //"[PST] ResDone = %x us, OpenRF = %x us, TBTT = %x us, RxBcn = %x us\n"
MSG_8852B_PS_TIMING_LOG_6, //"[PST] OpenRF to TBTT = %d us, TBTT to RxBcn = %d us, RxBcn to ClsRF = %d us, ClsRF to 32k = %d us\n"
MSG_8852B_PS_TIMING_LOG_7, //"[PST] ResDone = %x us, OpenRF = %x us, TBTT = %x us\n",
MSG_8852B_PS_TIMING_LOG_8, //"[PST] ResDone to SetBcnTo = %d us, SetBcnTo to BcnTo = %d us, BcnTo to ClsRF = %d us, ClsRF to 32k = %d us\n"
MSG_8852B_PS_TIMING_LOG_9, //"[PST] OpenRF = %x us, TBTT = %x us, RxBcn = %x us\n"
MSG_8852B_PS_TIMING_LOG_10, //"[PST] OpenRF to TBTT = %d us, TBTT to RxBcn = %d us, RxBcn to ClsRF = %d us\n"
MSG_8852B_PS_TIMING_LOG_11, //"[PST] OpenRF = %x us, TBTT = %x us, SetBcnTo to BcnTo = %d us, BcnTo to ClsRF = %d us\n"
MSG_8852B_PS_TIMING_LOG_12, //"[PST] OpenRF to ClsRF = %d us, RxBcn to S4 = %d us, S4Cnt = %d\n"
MSG_8852B_PS_TIMING_LOG_13, //"[PST] OpenRF to ClsRF = %d us, BcnTo to S4 = %d us, S4Cnt = %d\n"
MSG_8852B_PS_TIMING_LOG_14, //"[PST] BcnLossRate = %d/100, BcnTimeoutCnt = %d, BcnErlyCnt = %d\n"
MSG_8852B_PS_TIMING_LOG_15, //"[PST] S4Error[%d] = %d\n"
MSG_8852B_PS_INIT_FAIL, //"[FAIL] lps_info alloc fail!\n"
MSG_8852B_PS_PLATFORM_ERR, //"Platform error (%d)!\n"
MSG_8852B_PS_RESTORE_FLOW_FAIL, //"RestoreFlow FAIL!\n"
MSG_8852B_PS_AXIDMA_NOT_EMPTY, //"[32K] AXIDMA not empty (%d). host = %x, hw = %x\n"
MSG_8852B_PS_NO_ENTER_LPS, //"0x90=%x, No Enter LPS! 0xC0=%x\n"
MSG_8852B_PS_TX_PACKT_IN, //"TxPktIn\n"
MSG_8852B_PS_TXDMA_BUSY, //"[Err] TXDMA is busy! dma_busy1 = %x, dma_busy2 = %x\n"
MSG_8852B_PS_TAKE_SEMAPHORE_FAIL, //"Step(%d) Take RxModeLock FAIL!!!\n"
MSG_8852B_PS_NULL_SEMAPHORE, //"Step(%d) RxModeLock == NULL!\n"
MSG_8852B_PS_CLOSE_RF, //">\n"
MSG_8852B_PS_OPEN_RF, //"<\n"
MSG_8852B_PS_GRANT_WLAN_FAIL, //"[PDCK] GNT WL FAIL!!\n"
MSG_8852B_PS_PDCK_CAL_FAIL, //"PDCK CAL FAIL!!\n"
MSG_8852B_PS_ANACLK_CAL_FAIL, //"ANACLK CAL FAIL!!\n"
MSG_8852B_PS_EN_RX_NORMAL_MODE_FAIL, //"RF is OFF. EnRxNormMode FAIL!\n"
MSG_8852B_PS_EN_RX_NORMAL_MODE, //"1->2"
MSG_8852B_PS_SET_RF_OFF_PERMISSION, //"SetRfOffPermission: PhyRfOffPermission[%d]=%d\n"
MSG_8852B_PS_SET_32K_PERMISSION, //"Set32KandPGPermission. 32K(%d), PG(%d)\n"
MSG_8852B_PS_ENABLE_LPS_FW_TEST, //"Enable LPS FW test. Target LPS number (%x)\n"
MSG_8852B_PS_WAKE_BAR_PULL, //"[RF OFF] Wake bar is pulled\n"
MSG_8852B_PS_RX_FAIL_KEEP_RF_ON, //"[RF OFF] Rx FAIL! keep RF on.\n"
MSG_8852B_PS_CHECK_RF_CONDITION_FAIL, //"Check RF OFF condition FAIL (%d)\n"
MSG_8852B_PS_TX_NULL_FAIL, //"[Error] Cannot tx null%d\n"
MSG_8852B_PS_CREATE_ROLE_FAIL, //"[FAIL] Create Role fail!\n"
MSG_8852B_PS_ALREADY_IN_PS_MODE, //"[Error] Already in LPS/WMM PS (%x)!!\n"
MSG_8852B_PS_SET_POWER_MODE_1, //"MAC ID = %d, PS Mode = %d, RLBM = %d\n"
MSG_8852B_PS_SET_POWER_MODE_2, //"Smart PS = %d, Awake Interval = %d, Last RPWM = %d\n"
MSG_8852B_PS_BEACON_EARLY, //"E\n"
MSG_8852B_PS_RX_BEACON, //"R\n"
MSG_8852B_PS_RX_BEACON_NO_HIT, //"N\n"
MSG_8852B_PS_INVALID_BEACON_REPORT, //"[Error] Does not receive BCN Parser Rpt\n"
MSG_8852B_PS_KEEP_RF_ON, //"Keep ON\n"
MSG_8852B_PS_ENABLE_BEACON_TIMEOUT_TIMER_FAIL, //"EnBcnTimeOutCount fail!!\n"
MSG_8852B_PS_TIMER_VALUE_NOT_INIT, //"Timer (%d) val is not init!! role_idx(%d)\n"
MSG_8852B_PS_CREATE_TIMER_FAIL, //"Create timer (%d) fail!! role_idx(%d)\n"
MSG_8852B_PS_SEND_NULL_FAIL_RESULT, //"TxNull %d FAIL! ret_type(%d), result(%d)\n"
MSG_8852B_PS_INVALID_POWER_BIT, //"[PsSendNullCb] invalid pwr_bit(%d)\n"
MSG_8852B_PS_INIT_PS_PARAMETER, //"InitPSParm, role_idx=%d\n"
MSG_8852B_PS_S2_CONDITION_MISMATCH, //"[ChkS2 no match] Condition(%d), LpsDbgInfo = 0x%x\n"
MSG_8852B_PS_S4_CONDITION_MISMATCH, //"[ChkS4 no match] Condition(%d), LpsDbgInfo = 0x%x\n"
MSG_8852B_PS_CHANGE_PS_STATE, //"[ChangePSStateByRPWM] REQ State: %d, Cur State: %d\n"
MSG_8852B_PS_SET_POWER_MODE_ROLE_NOT_EXIST, //"[SetPwrMode] Role not exist! Condition (%d)\n"
MSG_8852B_PS_SET_TBTT_AGG_NUM, //"Step(%d), SetTbttAggNum(%d).\n"
MSG_8852B_PS_RX_BEACON_TIMEOUT, //"PsBcnTimeOut\n"
MSG_8852B_PS_SET_POWER_STATE, //"CURRENT_PS_STATE: %d, LASTRPWM: %d\n"
MSG_8852B_PS_RESET_PS_PARAMETER, //"ResetPSParm\n"
MSG_8852B_PS_ACTIVATE_SETTING, //"ActiveSetting\n"
MSG_8852B_PS_SEND_NULL_RESULT, //"[PsSendNullCb] type(%d), result(%d)\n"
MSG_8852B_PACKET_TX_NOT_ENABLE, //"[ERR]MGQ1 Txen = 0, TXEN(0xC348)=%x\n"
MSG_8852B_PACKET_MACID_SLEEP, //"MACID_SLEEP_0(0xC2C0)=%x\n"
MSG_8852B_PACKET_TX_NULL, //"Null %d\n"
MSG_8852B_PACKET_SEND_NULL_FAIL, //"Send NULL FAIL! ret_type(%d), ret_result(%d).\n"
MSG_8852B_PACKET_INVALID_POWER_BIT, //"Send NULL with invalid type(%d)!.\n"
MSG_8852B_PACKET_NULL_PKTID_NOT_EXIST, //"Null PKTID No Exist!!\n"
MSG_8852B_PACKET_NULL_READ_PKT_OFFLOAD_FAIL, //"[IssueNull]ReadFWOfldPKT FAIL!!\n"
MSG_8852B_PACKET_NULL_PKT_OFFLOAD, //"Null ID=%d, pkt_len=%d, ppkt_content=%x\n"
MSG_8852B_PACKET_PROBE_REQ_PKTID_NOT_EXIST, //"Probe req PKTID No Exist!!\n"
MSG_8852B_PACKET_PROBE_REQ_READ_PKT_OFFLOAD_FAIL, //"[IssueProbeReq]ReadFWOfldPKT FAIL!!\n"
MSG_8852B_WOWLAN_1, //"H2C wowlan, fun: %x"
MSG_8852B_WOWLAN_2, //"H2C Keep Alive, Enable: %x\n"
MSG_8852B_WOWLAN_3, //"H2C disconn, Enable: %x\n"
MSG_8852B_WOWLAN_4, //"Wow stop AXIDMA failed\n"
MSG_8852B_WOWLAN_5, //"H2C wow global, Enable: %x\n"
MSG_8852B_WOWLAN_6, //"H2C wakeup ctrl, pattern match Enable: %x\n"
MSG_8852B_WOWLAN_7, //"H2C , nlo Enable: %x\n"
MSG_8852B_WOWLAN_8, //"H2C , wow cam: %x\n"
MSG_8852B_WOWLAN_9, //"\nAppendTkipMICComm\n"
MSG_8852B_WOWLAN_10, //"key[%d]=%bx\n"
MSG_8852B_WOWLAN_11, //"DA[%d]=%bx\n"
MSG_8852B_WOWLAN_12, //"SA[%d]=%bx\n"
MSG_8852B_WOWLAN_13, //"Priority[%d]=%bx\n"
MSG_8852B_WOWLAN_14, //"data[%d]=%bx\n"
MSG_8852B_WOWLAN_15, //"miccode[%d]=%bx\n"
MSG_8852B_WOWLAN_16, //"get 1st rx pktid fail\n"
MSG_8852B_WOWLAN_17, //"(%d, %d) Parsed Failed!\n"
MSG_8852B_WOWLAN_18, //"Magic Packet Parsed Done, reason_bits<%x>\n"
MSG_8852B_WOWLAN_19, //"H2C , arp ofld Enable: %x\n"
MSG_8852B_WOWLAN_20, //"Unexpected HCI type in togglewake\n"
MSG_8852B_BEACON_1, //"req bcn mem err\n"
MSG_8852B_BEACON_2, //"CPUIO rls bcn pld fail\n"
MSG_8852B_BEACON_3, //"req bcn wp err %d\n"
MSG_8852B_BEACON_4, //"bcnq lock fail\n"
MSG_8852B_BEACON_5, //"CPUIO deq bcn fail\n"
MSG_8852B_BEACON_6, //"bcn req wd fail %d\n"
MSG_8852B_BEACON_7, //"enq bcn fail %d\n"
MSG_8852B_PPS_00, //"B%d pps%d already enable\n"
MSG_8852B_PPS_01, //"B%d pps%d already disable\n"
MSG_8852B_PPS_02, //"B%d pps%d reg already enable\n"
MSG_8852B_PPS_03, //"B%d pps%d reg already disable\n"
MSG_8852B_PPS_04, //"invalid pps band %d\n"
MSG_8852B_PPS_05, //"B%d pps%d is not enable yet\n"
MSG_8852B_PPS_06, //"B%d pps%d pof%d already enable\n"
MSG_8852B_PPS_07, //"B%d pps%d pof%d already disable\n"
MSG_8852B_PPS_08, //"B%d pps%d pof%d reg already enable\n"
MSG_8852B_PPS_09, //"B%d pps%d pof%d reg already disable\n"
MSG_8852B_PPS_10, //"B%d pps%d pof%d running\n"
MSG_8852B_PPS_11, //"pps no param ptr %d\n"
MSG_8852B_PPS_12, //"invalid pps port %d\n"
MSG_8852B_PPS_13, //"no valid pps id\n"
MSG_8852B_PPS_14, //"pps is already running\n"
MSG_8852B_PS_TX_REQ, //"PsTxReq. role(%d), feature(%d), en(%d)\n"
MSG_8852B_PS_TX_REQ_DUPLICATED_DISABLE, //"[ERROR] role(%d), feature(%d) Tx has been disabled!\n"
MSG_8852B_CHSW_00, //"[ChSw] Channel Switch Fail. (ctrl_bw_ch return false)\n"
MSG_8852B_P2P_00, //"[P2P]no act info ptr\n"
MSG_8852B_P2P_01, //"[P2P]act h2c init Role idx srch fail macid %d\n"
MSG_8852B_P2P_02, //"[P2P]set pps param fail %d\n"
MSG_8852B_P2P_03, //"[P2P]B%d pps%d en%d fail %d\n"
MSG_8852B_P2P_04, //"[P2P]B%d pps%d pof%d en%d fail %d\n"
MSG_8852B_P2P_05, //"[P2P]set pof param fail %d\n"
MSG_8852B_P2P_06, //"[P2P]B%d P2P%d noa%d already disable\n"
MSG_8852B_P2P_07, //"[P2P]B%d P2P%d has no running NoA sch\n"
MSG_8852B_P2P_08, //"[P2P]no content ptr\n"
MSG_8852B_P2P_09, //"[P2P]act h2c p2p%d over max\n"
MSG_8852B_P2P_10, //"[P2P]act h2c noa%d over max\n"
MSG_8852B_P2P_11, //"[P2P]p2p%d already running\n"
MSG_8852B_P2P_12, //"[P2P]p2p%d not init yet\n"
MSG_8852B_P2P_13, //"[P2P]act h2c init fail %d\n"
MSG_8852B_P2P_14, //"[P2P]act h2c upd sch fail %d\n"
MSG_8852B_P2P_15, //"[P2P]act h2c rm sch fail %d\n"
MSG_8852B_P2P_16, //"[P2P]act h2c term fail %d\n"
MSG_8852B_P2P_17, //"[P2P]illegal act h2c %d\n"
MSG_8852B_P2P_18, //"[P2P] macid ctrl h2c p2p id %d over max\n"
MSG_8852B_P2P_19, //"[P2P]macid ctrl type %d invalid\n"
MSG_8852B_P2P_20, //"[P2P]no p2p info ptr\n"
MSG_8852B_P2P_21, //"[P2P]P2P%d clear MACID ctrl all fail %d\n"
MSG_8852B_P2P_22, //"[P2P]H2C Act fail %d\n"
MSG_8852B_P2P_23, //"[P2P]H2C MACID ctrl fail %d\n"
MSG_8852B_NULL_RESULT, //"TxNull %d result(%d)!!!\n"
MSG_8852B_PS_CREATE_TIMER_DUPLICATED, //"[ERR][LPS] Create timer (%d) is existed!! role_idx(%d)\n"
MSG_8852B_PS_DELETE_TIMER_FAIL, //"[ERR][LPS] Delete timer (%d) FAIL!! role_idx(%d)\n"
MSG_8852B_PS_DELETE_TIMER_NOT_EXIST, //"[ERR][LPS] Delete timer (%d) is not existed!! role_idx(%d)\n"
MSG_8852B_PS_DTIM_TIMER_NOT_EXIST, //"[ERR][LPS] Operation(%d) DTIM timer is not existed!! role_idx(%d)\n"
MSG_8852B_PS_BCN_TIMER_NOT_EXIST, //"[ERR][LPS] Operation(%d) BCN timer is not existed!! role_idx(%d)\n"
MSG_8852B_PS_TRX_TIMER_NOT_EXIST, //"[ERR][LPS] Operation(%d) TRX timer is not existed!! role_idx(%d)\n"
MSG_8852B_PS_ENABLE_DTIM_TIMEOUT_TIMER_FAIL, //"[ERR][LPS] EnDTIMTimeOutCountComm FAIL!!\n"
MSG_8852B_PS_ENABLE_TRX_TIMEOUT_TIMER_FAIL, //"[ERR][LPS] EnTRXTimeOutCount FAIL!!\n"
MSG_8852B_PS_DRFC_RESTORE_FAIL, //"[ERR][LPS] Restore DRFC FAIL!! RF mode (%d)\n"
MSG_8852B_PS_S2TOS4_TX_BUSY, //"[WARN][LPS][S2ToS4State] Macid TX busy, role_idx(%d)\n"
MSG_8852B_RPWM_SEQ_MISMATCH, //"[ERR] RPWM Seq Num mismatch!\n"
MSG_8852B_RPWM_REQ_STATE_INVALID, //"[ERR] Req Pwr state (%d) is invalid!\n"
MSG_8852B_READ_RPWM, //"Read RPWM = %x\n"
MSG_8852B_WRITE_CPWM, //"LDM = %x, cpwm_val = %x, CPWM = %x\n"
MSG_8852B_TASK_ERROR, //"Task Error: %wx\n"
MSG_8852B_GETMEDIASTS_1, //"GetMediaStatusbyMacid fail, macid = %bx!\n"
MSG_8852B_SETMEDIASTS_1, //"SetMediaStatusbyMacid: macid number >= 32, macid = %bx!\n"
MSG_8852B_SETMEDIASTS_2, //"SetMediaStatusbyMacid: Role_idx error, macid = %bx, role_idx = %bx!\n"
MSG_8852B_OUTSRC_START = 20000, // "out source delimiter start"
MSG_8852B_OUTSRC_BB_SURA_0, //"[RA]RateChange=%x\n"
MSG_8852B_OUTSRC_BB_SURA_1, //"[RA]RDth=0x%x,RUth=0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_2, //"[RA]r4=100\n"
MSG_8852B_OUTSRC_BB_SURA_3, //"[RA]ForceRD\n"
MSG_8852B_OUTSRC_BB_SURA_4, //"[RA]RDCnt=0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_5, //"[RA]RUCnt=0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_6, //"[RA]RS\n"
MSG_8852B_OUTSRC_BB_SURA_7, //"[RA]SGIRD\n"
MSG_8852B_OUTSRC_BB_SURA_8, //"[RA]BWRD\n"
MSG_8852B_OUTSRC_BB_SURA_9, //"[RA]RDToLowest1\n"
MSG_8852B_OUTSRC_BB_SURA_10, //"[RA]RDToLowest2\n"
MSG_8852B_OUTSRC_BB_SURA_11, //"[RA]RD:crate=0x%x,mrate0=0x%x,mrate1=0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_12, //"[RA]rate=0x%x,bw:0x%x,rate2=0x%x,bw2:0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_13, //"[RA]Hit:bw=0x%x->0x%x,rate=0x%x->0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_14, //"[RA]SR:rate0=0x%x,rate1=0x%x,rate2=0x%x,cnt=0x%x\n"
MSG_8852B_OUTSRC_BB_SURA_15, //"RSVD\n"
MSG_8852B_OUTSRC_BB_SURA_16, //"[RA]SGIRU\n"
MSG_8852B_OUTSRC_BB_SURA_17, //"[RA]BWRU\n"
MSG_8852B_OUTSRC_BB_SURA_18, //"[RA]RUbw++\n"
MSG_8852B_OUTSRC_BB_SURA_19, //"[RA]RUToHighest\n"
MSG_8852B_OUTSRC_BB_SURA_20, //"[RA]NoUpRate\n"
MSG_8852B_OUTSRC_BB_SURA_21, //"[RA]RU:crate=%x,mrate0=%x,mrate1=%x\n"
MSG_8852B_OUTSRC_BB_SURA_22, //"[RA,W]macid:%x,mode:%x,rate_idx:%x,mcs:%x,ss:%x\n"
MSG_8852B_OUTSRC_BB_SURA_23, //"[RA][TRY]PER=%x,RDR=%x,R4=%x, pre_tp=%d, next_tp=%d\n"
MSG_8852B_OUTSRC_BB_SURA_24, //"[RA][TRY]R4=100,cnt=%x\n"
MSG_8852B_OUTSRC_BB_SURA_25, //"[RA][TRY]rate=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n"
MSG_8852B_OUTSRC_BB_SURA_26, //"[RA]TryFail\n"
MSG_8852B_OUTSRC_BB_SURA_27, //"[RA]TrySuccess\n"
MSG_8852B_OUTSRC_BB_SURA_28, //"[RA]MtTryIdx=%x\n"
MSG_8852B_OUTSRC_BB_SURA_29, //"[RA]TryFailCnt=%x,rate=%x,bw=%x\n"
MSG_8852B_OUTSRC_BB_SURA_30, //"[RA]DrvFixRate\n"
MSG_8852B_OUTSRC_BB_SURA_31, //"[RA]POLLUTED\n"
MSG_8852B_OUTSRC_BB_SURA_32, //"[RA]Tot=0\n"
MSG_8852B_OUTSRC_BB_SURA_33, //"[RA]Tx=0,Tot:%x,Ok:%x\n"
MSG_8852B_OUTSRC_BB_SURA_34, //"[RA]StaNull\n"
MSG_8852B_OUTSRC_BB_SURA_35, //"[RA]NoHESU\n"
MSG_8852B_OUTSRC_BB_SURA_36, //"[RA]WDNoRelease\n"
MSG_8852B_OUTSRC_BB_SURA_37, //"[RA]TxRptTot=%x\n"
MSG_8852B_OUTSRC_BB_SURA_38, //"[RA]Ovfl\n"
MSG_8852B_OUTSRC_BB_SURA_39, //"RSVD\n"
MSG_8852B_OUTSRC_BB_SURA_40, //"RSVD\n"
MSG_8852B_OUTSRC_BB_SURA_41, //"RSVD\n"
MSG_8852B_OUTSRC_BB_SURA_42, //"[RA]1 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"
MSG_8852B_OUTSRC_BB_SURA_43, //"[RA]PER=%x,RDR=%x,r4=%x\n"
MSG_8852B_OUTSRC_BB_SURA_44, //"[RA]2 chk_rate_up_lmt return: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"
MSG_8852B_OUTSRC_BB_SURA_45, //"[RA]3 chk_rate_up_lmt OK: r_idx = %x, c_mcs = %x >= l_mcs = %x\n"
MSG_8852B_OUTSRC_BB_SURA_46, //"[RA]rate_changed=%x @ rate_check_for_update\n"
MSG_8852B_OUTSRC_BB_SURA_47, //"[RA]chk rate exist: rate_idx=%x->%x (%x,%x,%x)\n"
MSG_8852B_OUTSRC_BB_SURA_48, //"[RA]chk_rate_up_lmt=%x,sta->up_fail_limit_rate[0]=%x,sta->up_fail_limit_rate[1]=%x\n"
MSG_8852B_OUTSRC_BB_SURA_49, //"[RA]r_idx = %x => per_ma = %x, per_var == %x, decision_offset_n=%x, decision_offset_p=%x\n"
MSG_8852B_OUTSRC_BB_SURA_50, //"[RA]UpFailLimitCnt:%x,m_rtae_up_fail_cnt_lmt:%x\n"
MSG_8852B_OUTSRC_BB_SURA_51, //"[RA][txrpt]Txcnt=%x, Try=%x, total=%x, OK=%x, Initrate,Giltf=%x,%x, Finalrate,Giltf=%x,%x, BW=%x,wd_not_released=%x\n"
MSG_8852B_OUTSRC_BB_SURA_52, //"[RA][TBTT]ID=%x,Media:%x,Tot=%x,Ok=%x,OK=%x\n"
MSG_8852B_OUTSRC_BB_SURA_53, //"[RA][TBTT][FWfixrate]ID=%x,Media:%x,Tot=%x,Ok=%x,a-OK%x\n"
MSG_8852B_OUTSRC_BB_SURA_54, //"[RA]Sgi_pending_cnt = %x\n"
MSG_8852B_OUTSRC_BB_SURA_55, //"[RA][SGI]New rate = %x, Old gi = %x, New gi = %x\n"
MSG_8852B_OUTSRC_BB_SURA_56, //"[RA][H2C]Mode_sel=%x, gi_ltf=%x, dcm_cap=%x, er_cap=%x, init_rate_lv=%x, ldpc_cap=%x, stbc_cap=%x, arfr_ctrl=%x\n"
MSG_8852B_OUTSRC_BB_SURA_57, //"[RA][H2C]Initial_BW=%x, max_ss_support=%x\n"
MSG_8852B_OUTSRC_BB_SURA_58, //"[RA][H2C]Ra_mask0=%x, ra_mask1=%x, highest_rate=%x, max_start_rate=%x, lowest_rate=%x\n"
MSG_8852B_OUTSRC_BB_SURA_59, //"[RA][H2C]Initrate: rateidx=%x, mode=%x, gi_ltf=%x, bw_idx=%x\n"
MSG_8852B_OUTSRC_END, // "out source delimiter end"
MSG_8852B_LAST, //"Please add your log above."
};
extern struct mac_fw_msg fw_log_8852b[];
#endif //__HAL8852B_FW_LOG__
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_log.h
|
C
|
agpl-3.0
| 75,077
|
/******************************************************************************
*
* Copyright(c) 2012 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifdef CONFIG_RTL8852B
#ifdef PHL_FEATURE_AP
#ifdef MAC_FW_8852B_U1
extern u8 array_8852b_u1_ap_mp[147224];
extern u32 array_length_8852b_u1_ap_mp;
#endif /*MAC_FW_8852B_U1*/
#endif /*PHL_FEATURE_AP*/
#ifdef PHL_FEATURE_NIC
#ifdef MAC_FW_8852B_U1
extern u8 array_8852b_u1_nic[253560];
extern u32 array_length_8852b_u1_nic;
#endif /*MAC_FW_8852B_U1*/
#ifdef MAC_FW_8852B_U1
extern u8 array_8852b_u1_nic_mp[253560];
extern u32 array_length_8852b_u1_nic_mp;
#endif /*MAC_FW_8852B_U1*/
#ifdef CONFIG_WOWLAN
#ifdef MAC_FW_8852B_U1
extern u8 array_8852b_u1_wowlan[135912];
extern u32 array_length_8852b_u1_wowlan;
#endif /*MAC_FW_8852B_U1*/
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
#endif /*CONFIG_RTL8852B*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/fw_ax/rtl8852b/hal8852b_fw_u1.h
|
C
|
agpl-3.0
| 1,375
|
/******************************************************************************
*
* Copyright(c) 2007 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_WPP_H__
#define __HALMAC_WPP_H__
#define HALMAC_WPP_CONTROL_GUIDS \
WPP_DEFINE_CONTROL_GUID( \
halMacGuid, (9f9d9e5b, 3854, 4b87, 8bc6, 4ce1f284d34b), \
WPP_DEFINE_BIT(COMP_HALMAC_MSG_INIT) \
WPP_DEFINE_BIT(COMP_HALMAC_MSG_EFUSE) \
WPP_DEFINE_BIT(COMP_HALMAC_MSG_FW) \
WPP_DEFINE_BIT(COMP_HALMAC_MSG_H2C) \
WPP_DEFINE_BIT(COMP_HALMAC_MSG_PWR) \
)
#endif /* __HALBB_TYPES_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/halmac_wpp.h
|
C
|
agpl-3.0
| 1,379
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _HV_AX_TYPE_H_
#define _HV_AX_TYPE_H_
#include "pltfm_cfg.h"
typedef unsigned long long u64;
#define SS_LINK_SIZE 256
#define DL_RUGRP_SIZE 8
#define DL_MUTBL_SIZE 5
#define HV_AX_FPGA 0
#define HV_AX_ASIC 1
/**
* @enum hv_ax_ss_wmm
*
* @brief hv_ax_ss_wmm
*
* @var hv_ax_ss_wmm::HV_AX_SS_WMM0
* Please Place Description here.
* @var hv_ax_ss_wmm::HV_AX_SS_WMM1
* Please Place Description here.
* @var hv_ax_ss_wmm::HV_AX_SS_WMM2
* Please Place Description here.
* @var hv_ax_ss_wmm::HV_AX_SS_WMM3
* Please Place Description here.
* @var hv_ax_ss_wmm::HV_AX_SS_UL
* Please Place Description here.
*/
enum hv_ax_ss_wmm {
HV_AX_SS_WMM0,
HV_AX_SS_WMM1,
HV_AX_SS_WMM2,
HV_AX_SS_WMM3,
HV_AX_SS_UL,
};
/**
* @enum hv_ax_freerun_cfg
*
* @brief hv_ax_freerun_cfg
*
* @var hv_ax_freerun_cfg::HV_AX_FREERUN_EN
* Please Place Description here.
* @var hv_ax_freerun_cfg::HV_AX_FREERUN_DIS
* Please Place Description here.
* @var hv_ax_freerun_cfg::HV_AX_FREERUN_RST
* Please Place Description here.
*/
enum hv_ax_freerun_cfg {
HV_AX_FREERUN_EN,
HV_AX_FREERUN_DIS,
HV_AX_FREERUN_RST,
};
/**
* @enum hv_ax_ss_quota_mode_cfg
*
* @brief hv_ax_ss_quota_mode_cfg
*
* @var hv_ax_ss_quota_mode_cfg::HV_AX_SS_QUOTA_MODE_GET
* Please Place Description here.
* @var hv_ax_ss_quota_mode_cfg::HV_AX_SS_QUOTA_MODE_SET
* Please Place Description here.
*/
enum hv_ax_ss_quota_mode_cfg {
HV_AX_SS_QUOTA_MODE_GET,
HV_AX_SS_QUOTA_MODE_SET,
};
/**
* @enum hv_ax_ss_wmm_tbl_cfg
*
* @brief hv_ax_ss_wmm_tbl_cfg
*
* @var hv_ax_ss_wmm_tbl_cfg::HV_AX_SS_WMM_TBL_SET
* Please Place Description here.
*/
enum hv_ax_ss_wmm_tbl_cfg {
HV_AX_SS_WMM_TBL_SET,
};
/**
* @enum hv_ax_sta_len_cmd
*
* @brief hv_ax_sta_len_cmd
*
* @var hv_ax_sta_len_cmd::HV_AX_STA_LEN_INCR
* Please Place Description here.
* @var hv_ax_sta_len_cmd::HV_AX_STA_LEN_DECR
* Please Place Description here.
*/
enum hv_ax_sta_len_cmd {
HV_AX_STA_LEN_INCR,
HV_AX_STA_LEN_DECR,
};
/**
* @enum hv_ax_sta_len_cfg
*
* @brief hv_ax_sta_len_cfg
*
* @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_GET
* Please Place Description here.
* @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_SET
* Please Place Description here.
* @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_GET_INDIR
* Please Place Description here.
* @var hv_ax_sta_len_cfg::HV_AX_STA_LEN_CFG_SET_INDIR
* Please Place Description here.
*/
enum hv_ax_sta_len_cfg {
HV_AX_STA_LEN_CFG_GET,
HV_AX_STA_LEN_CFG_SET,
HV_AX_STA_LEN_CFG_GET_INDIR,
HV_AX_STA_LEN_CFG_SET_INDIR,
};
/**
* @enum hv_ax_sta_quota_cfg
*
* @brief hv_ax_sta_quota_cfg
*
* @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_VAL_GET
* Please Place Description here.
* @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_VAL_SET
* Please Place Description here.
* @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_SETTING_GET
* Please Place Description here.
* @var hv_ax_sta_quota_cfg::HV_AX_STA_QUOTA_CFG_SETTING_SET
* Please Place Description here.
*/
enum hv_ax_sta_quota_cfg {
HV_AX_STA_QUOTA_CFG_VAL_GET,
HV_AX_STA_QUOTA_CFG_VAL_SET,
HV_AX_STA_QUOTA_CFG_SETTING_GET,
HV_AX_STA_QUOTA_CFG_SETTING_SET,
};
/**
* @enum hv_ax_sta_muru_cfg
*
* @brief hv_ax_sta_muru_cfg
*
* @var hv_ax_sta_muru_cfg::HV_AX_STA_MURU_CFG_GET
* Please Place Description here.
* @var hv_ax_sta_muru_cfg::HV_AX_STA_MURU_CFG_SET
* Please Place Description here.
*/
enum hv_ax_sta_muru_cfg {
HV_AX_STA_MURU_CFG_GET,
HV_AX_STA_MURU_CFG_SET,
};
/**
* @enum hv_ax_ss_quota_mode
*
* @brief hv_ax_ss_quota_mode
*
* @var hv_ax_ss_quota_mode::HV_AX_SS_QUOTA_MODE_TIME
* Please Place Description here.
* @var hv_ax_ss_quota_mode::HV_AX_SS_QUOTA_MODE_CNT
* Please Place Description here.
*/
enum hv_ax_ss_quota_mode {
HV_AX_SS_QUOTA_MODE_TIME = 0,
HV_AX_SS_QUOTA_MODE_CNT = 1,
};
/**
* @enum hv_ax_ss_link_cfg
*
* @brief hv_ax_ss_link_cfg
*
* @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_GET
* Please Place Description here.
* @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_ADD
* Please Place Description here.
* @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_DEL
* Please Place Description here.
* @var hv_ax_ss_link_cfg::HV_AX_SS_LINK_CFG_CLEAN
* Please Place Description here.
*/
enum hv_ax_ss_link_cfg {
HV_AX_SS_LINK_CFG_GET,
HV_AX_SS_LINK_CFG_ADD,
HV_AX_SS_LINK_CFG_DEL,
HV_AX_SS_LINK_CFG_CLEAN,
};
/**
* @enum hv_ax_sta_bmp_cfg
*
* @brief hv_ax_sta_bmp_cfg
*
* @var hv_ax_sta_bmp_cfg::HV_AX_STA_BMP_CFG_GET
* Please Place Description here.
* @var hv_ax_sta_bmp_cfg::HV_AX_STA_BMP_CFG_SET
* Please Place Description here.
*/
enum hv_ax_sta_bmp_cfg {
HV_AX_STA_BMP_CFG_GET,
HV_AX_STA_BMP_CFG_SET,
};
/**
* @enum hv_ax_ss_rpt_cfg
*
* @brief hv_ax_ss_rpt_cfg
*
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_UL_RPT_CFG_GET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_UL_RPT_CFG_SET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_SU_RPT_CFG_GET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_SU_RPT_CFG_SET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_MU_RPT_CFG_GET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_MU_RPT_CFG_SET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_RU_RPT_CFG_GET
* Please Place Description here.
* @var hv_ax_ss_rpt_cfg::HV_AX_SS_DL_RU_RPT_CFG_SET
* Please Place Description here.
*/
enum hv_ax_ss_rpt_cfg {
HV_AX_SS_UL_RPT_CFG_GET,
HV_AX_SS_UL_RPT_CFG_SET,
HV_AX_SS_DL_SU_RPT_CFG_GET,
HV_AX_SS_DL_SU_RPT_CFG_SET,
HV_AX_SS_DL_MU_RPT_CFG_GET,
HV_AX_SS_DL_MU_RPT_CFG_SET,
HV_AX_SS_DL_RU_RPT_CFG_GET,
HV_AX_SS_DL_RU_RPT_CFG_SET,
};
/**
* @enum hv_ax_ss_rpt_path_cfg
*
* @brief hv_ax_ss_rpt_path_cfg
*
* @var hv_ax_ss_rpt_path_cfg::HV_AX_SS_RPT_PATH_CPU
* Please Place Description here.
* @var hv_ax_ss_rpt_path_cfg::HV_AX_SS_RPT_PATH_HOST
* Please Place Description here.
*/
enum hv_ax_ss_rpt_path_cfg {
HV_AX_SS_RPT_PATH_CPU,
HV_AX_SS_RPT_PATH_HOST,
};
/**
* @enum hv_ax_ss_dlru_search_mode
*
* @brief hv_ax_ss_dlru_search_mode
*
* @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_LINK_THEN_AC
* Please Place Description here.
* @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_AC
* Please Place Description here.
* @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_LINK_THEN_LEN
* Please Place Description here.
* @var hv_ax_ss_dlru_search_mode::HV_AX_SS_DLRU_SEARCH_LEN
* Please Place Description here.
*/
enum hv_ax_ss_dlru_search_mode {
HV_AX_SS_DLRU_SEARCH_LINK_THEN_AC = 0,
HV_AX_SS_DLRU_SEARCH_AC = 1,
HV_AX_SS_DLRU_SEARCH_LINK_THEN_LEN = 2,
HV_AX_SS_DLRU_SEARCH_LEN = 3,
};
/**
* @enum hv_ax_ss_delay_tx_band
*
* @brief hv_ax_ss_delay_tx_band
*
* @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_DIS
* Please Place Description here.
* @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_B0
* Please Place Description here.
* @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_B1
* Please Place Description here.
* @var hv_ax_ss_delay_tx_band::HV_AX_SS_DELAY_TX_B0_B1
* Please Place Description here.
*/
enum hv_ax_ss_delay_tx_band {
HV_AX_SS_DELAY_TX_DIS = 0,
HV_AX_SS_DELAY_TX_B0 = 1,
HV_AX_SS_DELAY_TX_B1 = 2,
HV_AX_SS_DELAY_TX_B0_B1 = 3,
};
/**
* @enum mac_ax_plat_module
*
* @brief mac_ax_plat_module
*
* @var mac_ax_plat_module::SPIC
* Please Place Description here.
* @var mac_ax_plat_module::CPU_PLATFORM
* Please Place Description here.
* @var mac_ax_plat_module::EFUSE_CTRL
* Please Place Description here.
* @var mac_ax_plat_module::IDDMA
* Please Place Description here.
* @var mac_ax_plat_module::AXIDMA
* Please Place Description here.
* @var mac_ax_plat_module::IPSEC
* Please Place Description here.
* @var mac_ax_plat_module::UART
* Please Place Description here.
* @var mac_ax_plat_module::HIOE
* Please Place Description here.
* @var mac_ax_plat_module::WATCHDOG
* Please Place Description here.
* @var mac_ax_plat_module::SECURITY
* Please Place Description here.
* @var mac_ax_plat_module::PLAT_MODULE_MAX
* Please Place Description here.
*/
enum mac_ax_plat_module {
SPIC,
CPU_PLATFORM,
EFUSE_CTRL,
IDDMA,
AXIDMA,
IPSEC,
UART,
HIOE,
WATCHDOG,
SECURITY,
PLAT_MODULE_MAX
};
/**
* @struct hv_ax_lifetime_mg2_cfg
* @brief hv_ax_lifetime_mg2_cfg
*
* @var hv_ax_lifetime_mg2_cfg::band
* Please Place Description here.
* @var hv_ax_lifetime_mg2_cfg::en
* Please Place Description here.
* @var hv_ax_lifetime_mg2_cfg::val
* Please Place Description here.
*/
struct hv_ax_lifetime_mg2_cfg {
u8 band;
u8 en;
u16 val;
};
/**
* @struct hv_ax_ss_delay_tx_info
* @brief hv_ax_ss_delay_tx_info
*
* @var hv_ax_ss_delay_tx_info::band_sel
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::vovi_to_0
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::bebk_to_0
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::vovi_to_1
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::bebk_to_1
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::vovi_len_0
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::bebk_len_0
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::vovi_len_1
* Please Place Description here.
* @var hv_ax_ss_delay_tx_info::bebk_len_1
* Please Place Description here.
*/
struct hv_ax_ss_delay_tx_info {
enum hv_ax_ss_delay_tx_band band_sel;
u8 vovi_to_0;
u8 bebk_to_0;
u8 vovi_to_1;
u8 bebk_to_1;
u8 vovi_len_0;
u8 bebk_len_0;
u8 vovi_len_1;
u8 bebk_len_1;
};
/**
* @struct hv_ax_ss_search_info
* @brief hv_ax_ss_search_info
*
* @var hv_ax_ss_search_info::wmm
* Please Place Description here.
* @var hv_ax_ss_search_info::ac
* Please Place Description here.
* @var hv_ax_ss_search_info::ul
* Please Place Description here.
* @var hv_ax_ss_search_info::twt_grp
* Please Place Description here.
* @var hv_ax_ss_search_info::mode_sel
* Please Place Description here.
* @var hv_ax_ss_search_info::macid
* Please Place Description here.
* @var hv_ax_ss_search_info::search_fail
* Please Place Description here.
*/
struct hv_ax_ss_search_info {
u8 wmm;
u8 ac;
u8 ul;
u8 twt_grp;
u8 mode_sel;
u8 macid;
u8 search_fail;
};
/**
* @struct hv_ax_ss_dl_rpt_info
* @brief hv_ax_ss_dl_rpt_info
*
* @var hv_ax_ss_dl_rpt_info::wmm0_max
* Please Place Description here.
* @var hv_ax_ss_dl_rpt_info::wmm1_max
* Please Place Description here.
* @var hv_ax_ss_dl_rpt_info::twt_wmm0_max
* Please Place Description here.
* @var hv_ax_ss_dl_rpt_info::twt_wmm1_max
* Please Place Description here.
*/
struct hv_ax_ss_dl_rpt_info {
u8 wmm0_max;
u8 wmm1_max;
u8 twt_wmm0_max;
u8 twt_wmm1_max;
};
/**
* @struct hv_ax_ss_ul_rpt_info
* @brief hv_ax_ss_ul_rpt_info
*
* @var hv_ax_ss_ul_rpt_info::ul_wmm_sel
* Please Place Description here.
* @var hv_ax_ss_ul_rpt_info::ul_su_max
* Please Place Description here.
* @var hv_ax_ss_ul_rpt_info::twt_ul_su_max
* Please Place Description here.
* @var hv_ax_ss_ul_rpt_info::ul_ru_max
* Please Place Description here.
*/
struct hv_ax_ss_ul_rpt_info {
u8 ul_wmm_sel;
u8 ul_su_max;
u8 twt_ul_su_max;
u8 ul_ru_max;
};
/**
* @struct hv_ax_ss_link_info
* @brief hv_ax_ss_link_info
*
* @var hv_ax_ss_link_info::wmm
* Please Place Description here.
* @var hv_ax_ss_link_info::ac
* Please Place Description here.
* @var hv_ax_ss_link_info::ul
* Please Place Description here.
* @var hv_ax_ss_link_info::link_list
* Please Place Description here.
* @var hv_ax_ss_link_info::link_head
* Please Place Description here.
* @var hv_ax_ss_link_info::link_tail
* Please Place Description here.
* @var hv_ax_ss_link_info::link_len
* Please Place Description here.
* @var hv_ax_ss_link_info::macid0
* Please Place Description here.
* @var hv_ax_ss_link_info::macid1
* Please Place Description here.
* @var hv_ax_ss_link_info::macid2
* Please Place Description here.
* @var hv_ax_ss_link_info::link_bitmap
* Please Place Description here.
*/
struct hv_ax_ss_link_info {
u8 wmm;
u8 ac;
u8 ul;
u8 link_list[SS_LINK_SIZE];
u8 link_head;
u8 link_tail;
u8 link_len;
u8 macid0;
u8 macid1;
u8 macid2;
u8 link_bitmap[SS_LINK_SIZE];
};
/**
* @struct hv_ax_sta_dl_rugrp_ctrl
* @brief hv_ax_sta_dl_rugrp_ctrl
*
* @var hv_ax_sta_dl_rugrp_ctrl::grpid
* Please Place Description here.
* @var hv_ax_sta_dl_rugrp_ctrl::grp_vld
* Please Place Description here.
* @var hv_ax_sta_dl_rugrp_ctrl::macid
* Please Place Description here.
* @var hv_ax_sta_dl_rugrp_ctrl::dis_ac
* Please Place Description here.
*/
struct hv_ax_sta_dl_rugrp_ctrl {
u8 grpid;
u8 grp_vld;
u8 macid[DL_RUGRP_SIZE];
u8 dis_ac[DL_RUGRP_SIZE];
};
/**
* @struct hv_ax_sta_dl_mutbl_ctrl
* @brief hv_ax_sta_dl_mutbl_ctrl
*
* @var hv_ax_sta_dl_mutbl_ctrl::tbl_id
* Please Place Description here.
* @var hv_ax_sta_dl_mutbl_ctrl::tbl_vld
* Please Place Description here.
* @var hv_ax_sta_dl_mutbl_ctrl::macid
* Please Place Description here.
* @var hv_ax_sta_dl_mutbl_ctrl::score
* Please Place Description here.
*/
struct hv_ax_sta_dl_mutbl_ctrl {
u8 tbl_id;
u8 tbl_vld;
u8 macid;
u8 score[DL_MUTBL_SIZE];
};
/**
* @struct hv_ax_ss_quota_mode_ctrl
* @brief hv_ax_ss_quota_mode_ctrl
*
* @var hv_ax_ss_quota_mode_ctrl::wmm
* Please Place Description here.
* @var hv_ax_ss_quota_mode_ctrl::mode
* Please Place Description here.
*/
struct hv_ax_ss_quota_mode_ctrl {
enum hv_ax_ss_wmm wmm;
enum hv_ax_ss_quota_mode mode;
};
/**
* @struct hv_ax_sta_muru_ctrl
* @brief hv_ax_sta_muru_ctrl
*
* @var hv_ax_sta_muru_ctrl::macid
* Please Place Description here.
* @var hv_ax_sta_muru_ctrl::ul_tbl
* Please Place Description here.
* @var hv_ax_sta_muru_ctrl::dl_muru_dis
* Please Place Description here.
*/
struct hv_ax_sta_muru_ctrl {
u8 macid;
u32 ul_tbl;
u32 dl_muru_dis;
};
/**
* @struct hv_ax_sta_bmp_ctrl
* @brief hv_ax_sta_bmp_ctrl
*
* @var hv_ax_sta_bmp_ctrl::macid
* Please Place Description here.
* @var hv_ax_sta_bmp_ctrl::bmp
* Please Place Description here.
* @var hv_ax_sta_bmp_ctrl::mask
* Please Place Description here.
*/
struct hv_ax_sta_bmp_ctrl {
u8 macid;
u32 bmp;
u32 mask;
};
/**
* @struct hv_ax_sta_quota
* @brief hv_ax_sta_quota
*
* @var hv_ax_sta_quota::macid
* Please Place Description here.
* @var hv_ax_sta_quota::vo_quota
* Please Place Description here.
* @var hv_ax_sta_quota::vi_quota
* Please Place Description here.
* @var hv_ax_sta_quota::be_quota
* Please Place Description here.
* @var hv_ax_sta_quota::bk_quota
* Please Place Description here.
* @var hv_ax_sta_quota::ul_quota
* Please Place Description here.
*/
struct hv_ax_sta_quota {
u8 macid;
u32 vo_quota;
u32 vi_quota;
u32 be_quota;
u32 bk_quota;
u32 ul_quota;
};
/**
* @struct hv_ax_sta_len_ctrl
* @brief hv_ax_sta_len_ctrl
*
* @var hv_ax_sta_len_ctrl::macid
* Please Place Description here.
* @var hv_ax_sta_len_ctrl::len
* Please Place Description here.
* @var hv_ax_sta_len_ctrl::ac
* Please Place Description here.
* @var hv_ax_sta_len_ctrl::cmd
* Please Place Description here.
*/
struct hv_ax_sta_len_ctrl {
u8 macid;
u32 len;
enum mac_ax_cmac_ac_sel ac;
enum hv_ax_sta_len_cmd cmd;
};
/**
* @struct hv_ax_sta_len
* @brief hv_ax_sta_len
*
* @var hv_ax_sta_len::macid
* Please Place Description here.
* @var hv_ax_sta_len::vo_len
* Please Place Description here.
* @var hv_ax_sta_len::vi_len
* Please Place Description here.
* @var hv_ax_sta_len::be_len
* Please Place Description here.
* @var hv_ax_sta_len::bk_len
* Please Place Description here.
* @var hv_ax_sta_len::bsr_len
* Please Place Description here.
* @var hv_ax_sta_len::bsr_ac_type
* Please Place Description here.
*/
struct hv_ax_sta_len {
u8 macid;
u32 vo_len;
u32 vi_len;
u32 be_len;
u32 bk_len;
u32 bsr_len;
u8 bsr_ac_type;
};
/**
* @struct hv_aggregator_t
* @brief hv_aggregator_t
*
* @var hv_aggregator_t::pkt
* Please Place Description here.
* @var hv_aggregator_t::len
* Please Place Description here.
* @var hv_aggregator_t::agg_num
* Please Place Description here.
*/
struct hv_aggregator_t {
u8 *pkt;
u32 len;
u32 agg_num;
};
/**
* @struct hv_dbg_port
* @brief hv_dbg_port
*
* @var hv_dbg_port::info
* Please Place Description here.
* @var hv_dbg_port::len
* Please Place Description here.
* @var hv_dbg_port::read_addr
* Please Place Description here.
* @var hv_dbg_port::sel_addr
* Please Place Description here.
* @var hv_dbg_port::dbg_sel
* Please Place Description here.
*/
struct hv_dbg_port {
struct hv_dbg_port_info *info;
u32 len;
u32 read_addr;
u32 sel_addr;
u32 dbg_sel;
};
/**
* @struct hv_dbg_port_info
* @brief hv_dbg_port_info
*
* @var hv_dbg_port_info::addr
* Please Place Description here.
* @var hv_dbg_port_info::val
* Please Place Description here.
*/
struct hv_dbg_port_info {
u32 addr;
u32 val;
};
/**
* @struct mac_ax_mac_test
* @brief mac_ax_mac_test
*
* @var mac_ax_mac_test::dword0
* Please Place Description here.
* @var mac_ax_mac_test::dword1
* Please Place Description here.
*/
struct mac_ax_mac_test {
u32 dword0;
u32 dword1;
};
/**
* @struct mac_ax_plat_auto_test
* @brief mac_ax_plat_auto_test
*
* @var mac_ax_plat_auto_test::dword0
* Please Place Description here.
* @var mac_ax_plat_auto_test::dword1
* Please Place Description here.
* @var mac_ax_plat_auto_test::dword2
* Please Place Description here.
* @var mac_ax_plat_auto_test::dword3
* Please Place Description here.
* @var mac_ax_plat_auto_test::dword4
* Please Place Description here.
* @var mac_ax_plat_auto_test::dword5
* Please Place Description here.
*/
struct mac_ax_plat_auto_test {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
/**
* @struct hv_ctrl_frame_cnt
* @brief hv_ctrl_frame_cnt
*
* @var hv_ctrl_frame_cnt::band
* Please Place Description here.
* @var hv_ctrl_frame_cnt::op
* Please Place Description here.
* @var hv_ctrl_frame_cnt::stype
* Please Place Description here.
* @var hv_ctrl_frame_cnt::idx
* Please Place Description here.
* @var hv_ctrl_frame_cnt::rval
* Please Place Description here.
* @var hv_ctrl_frame_cnt::tval
* Please Place Description here.
*/
struct hv_ctrl_frame_cnt {
#define MAC_HV_CTRL_CNT_R 0
#define MAC_HV_CTRL_CNT_W 1
#define MAC_HV_CTRL_CNT_RST 2
#define MAC_HV_CTRL_CNT_RST_ALL 3
u8 band;
u8 op;
u8 stype;
#define MAC_HV_CTRL_CNT_NUM 16
u8 idx;
u16 rval;
u16 tval;
};
/**
* @struct hv_rx_cnt
* @brief hv_rx_cnt
*
* @var hv_rx_cnt::op
* Please Place Description here.
* @var hv_rx_cnt::idx
* Please Place Description here.
* @var hv_rx_cnt::band
* Please Place Description here.
* @var hv_rx_cnt::type
* Please Place Description here.
* @var hv_rx_cnt::val
* Please Place Description here.
* @var hv_rx_cnt::subtype
* Please Place Description here.
* @var hv_rx_cnt::bssid
* Please Place Description here.
* @var hv_rx_cnt::rate
* Please Place Description here.
* @var hv_rx_cnt::gi_ltf
* Please Place Description here.
* @var hv_rx_cnt::ru
* Please Place Description here.
* @var hv_rx_cnt::msk
* Please Place Description here.
*/
struct hv_rx_cnt {
#define MAC_HV_RX_CNT_R 0
#define MAC_HV_RX_CNT_W 1
#define MAC_HV_RX_CNT_RST 2
u8 op;
#define MAC_HV_RX_CNT_NUM 48
u8 idx;
u8 band;
u8 type;
u16 val;
u8 subtype;
u8 bssid;
u16 rate;
u8 gi_ltf;
u8 ru;
#define MAC_HV_RX_CNT_MSK_FC BIT(0)
#define MAC_HV_RX_CNT_MSK_BSSID BIT(1)
#define MAC_HV_RX_CNT_MSK_RATE BIT(2)
#define MAC_HV_RX_CNT_MSK_RU BIT(3)
u8 msk;
};
struct hv_txpkt_info {
u8 null_0;
u8 null_1;
u8 tri_frame;
u8 ht_data_snd;
u8 chk_en;
u16 ndpa_dur;
};
/**
* @struct hv_ax_ops
* @brief hv_ax_ops
*
* @var hv_ax_ops::tx_post_desc
* Please Place Description here.
* @var hv_ax_ops::get_ppdu
* Please Place Description here.
* @var hv_ax_ops::chk_ps_dfs
* Please Place Description here.
* @var hv_ax_ops::chk_ps_ppdu
* Please Place Description here.
* @var hv_ax_ops::chk_ps_ch_info
* Please Place Description here.
* @var hv_ax_ops::phy_cfg
* Please Place Description here.
* @var hv_ax_ops::sta_bmp_cfg
* Please Place Description here.
* @var hv_ax_ops::sta_len_cfg
* Please Place Description here.
* @var hv_ax_ops::sta_dl_rugrp_cfg
* Please Place Description here.
* @var hv_ax_ops::sta_muru_cfg
* Please Place Description here.
* @var hv_ax_ops::sta_quota_cfg
* Please Place Description here.
* @var hv_ax_ops::sta_link_cfg
* Please Place Description here.
* @var hv_ax_ops::ss_dl_rpt_cfg
* Please Place Description here.
* @var hv_ax_ops::ss_ul_rpt_cfg
* Please Place Description here.
* @var hv_ax_ops::ss_query_search
* Please Place Description here.
* @var hv_ax_ops::ss_rpt_path_cfg
* Please Place Description here.
* @var hv_ax_ops::ss_set_bsr_thold
* Please Place Description here.
* @var hv_ax_ops::ss_dlru_search_mode
* Please Place Description here.
* @var hv_ax_ops::ss_set_delay_tx
* Please Place Description here.
* @var hv_ax_ops::sta_dl_mutbl_cfg
* Please Place Description here.
* @var hv_ax_ops::ss_dlmu_search_mode
* Please Place Description here.
* @var hv_ax_ops::ss_quota_mode
* Please Place Description here.
* @var hv_ax_ops::get_dbg_port_info
* Please Place Description here.
* @var hv_ax_ops::get_dle_dfi_info
* Please Place Description here.
* @var hv_ax_ops::ss_wmm_tbl_cfg
* Please Place Description here.
* @var hv_ax_ops::ss_wmm_sta_move
* Please Place Description here.
* @var hv_ax_ops::ss_set_wmm_bmp
* Please Place Description here.
* @var hv_ax_ops::cfg_btc_dbg_port
* Please Place Description here.
* @var hv_ax_ops::en_btc_rtk_mode
* Please Place Description here.
* @var hv_ax_ops::set_ctrl_frame_cnt
* Please Place Description here.
* @var hv_ax_ops::set_rx_cnt
* Please Place Description here.
* @var hv_ax_ops::set_freerun_cfg
* Please Place Description here.
* @var hv_ax_ops::get_freerun_info
* Please Place Description here.
* @var hv_ax_ops::set_lifetime_mg2
* Please Place Description here.
* @var hv_ax_ops::get_lifetime_mg2
* Please Place Description here.
* @var hv_ax_ops::ptn_h2c_common
* Please Place Description here.
* @var hv_ax_ops::get_mac_err_isr
* Please Place Description here.
* @var hv_ax_ops::get_gpio_status
* Please Place Description here.
* @var hv_ax_ops::get_gpio_val
* Please Place Description here.
*/
struct hv_ax_ops {
u32 (*tx_post_desc)(struct mac_ax_adapter *adapter,
struct hv_aggregator_t *agg);
u32 (*get_ppdu)(struct mac_ax_adapter *adapter, enum mac_ax_band band);
u32 (*chk_ps_dfs)(struct mac_ax_adapter *adapter, u8 *data, u32 len);
u32 (*chk_ps_ppdu)(struct mac_ax_adapter *adapter, u8 *data, u32 len);
u32 (*chk_ps_ch_info)(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
u32 (*phy_cfg)(struct mac_ax_adapter *adapter);
u32 (*sta_bmp_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_sta_bmp_ctrl *ctrl,
enum hv_ax_sta_bmp_cfg cfg);
u32 (*sta_len_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_sta_len *len,
enum hv_ax_sta_len_cfg cfg);
u32 (*sta_dl_rugrp_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_sta_dl_rugrp_ctrl *rugrp,
enum hv_ax_sta_muru_cfg cfg);
u32 (*sta_muru_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_sta_muru_ctrl *muru,
enum hv_ax_sta_muru_cfg cfg);
u32 (*sta_quota_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_sta_quota *quota,
enum hv_ax_sta_quota_cfg cfg);
u32 (*sta_link_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_ss_link_info *link,
enum hv_ax_ss_link_cfg cfg);
void (*ss_dl_rpt_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_ss_dl_rpt_info *info,
enum hv_ax_ss_rpt_cfg cfg);
void (*ss_ul_rpt_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_ss_ul_rpt_info *info,
enum hv_ax_ss_rpt_cfg cfg);
u32 (*ss_query_search)(struct mac_ax_adapter *adapter,
struct hv_ax_ss_search_info *info);
void (*ss_rpt_path_cfg)(struct mac_ax_adapter *adapter,
enum hv_ax_ss_rpt_path_cfg cfg);
void (*ss_set_bsr_thold)(struct mac_ax_adapter *adapter, u16 thold_0,
u16 thold_1);
void (*ss_dlru_search_mode)(struct mac_ax_adapter *adapter,
enum hv_ax_ss_dlru_search_mode mode);
void (*ss_set_delay_tx)(struct mac_ax_adapter *adapter,
struct hv_ax_ss_delay_tx_info *info);
u32 (*sta_dl_mutbl_cfg)(struct mac_ax_adapter *adapter,
struct hv_ax_sta_dl_mutbl_ctrl *mutbl,
enum hv_ax_sta_muru_cfg cfg);
void (*ss_dlmu_search_mode)(struct mac_ax_adapter *adapter, u8 mode,
u8 score_thr);
u32 (*ss_quota_mode)(struct mac_ax_adapter *adapter,
struct hv_ax_ss_quota_mode_ctrl *ctrl,
enum hv_ax_ss_quota_mode_cfg cfg);
u32 (*get_dbg_port_info)(struct mac_ax_adapter *adapter,
struct hv_dbg_port *dbg);
u32 (*get_dle_dfi_info)(struct mac_ax_adapter *adapter,
struct hv_dbg_port *dbg);
void (*ss_wmm_tbl_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_ss_wmm_tbl_ctrl *ctrl,
enum hv_ax_ss_wmm_tbl_cfg cfg);
u32 (*ss_wmm_sta_move)(struct mac_ax_adapter *adapter,
enum hv_ax_ss_wmm src_wmm,
enum mac_ax_ss_wmm_tbl dst_link);
u32 (*ss_set_wmm_bmp)(struct mac_ax_adapter *adapter, u8 wmm, u8 macid);
u32 (*cfg_btc_dbg_port)(struct mac_ax_adapter *adapter);
u32 (*en_btc_rtk_mode)(struct mac_ax_adapter *adapter);
u32 (*set_ctrl_frame_cnt)(struct mac_ax_adapter *adapter,
struct hv_ctrl_frame_cnt *ctrl);
u32 (*set_rx_cnt)(struct mac_ax_adapter *adapter,
struct hv_rx_cnt *cnt);
u32 (*set_freerun_cfg)(struct mac_ax_adapter *adapter,
enum hv_ax_freerun_cfg cfg);
u32 (*get_freerun_info)(struct mac_ax_adapter *adapter, u32 *cnt_low,
u32 *cnt_high);
u32 (*set_lifetime_mg2)(struct mac_ax_adapter *adapter,
struct hv_ax_lifetime_mg2_cfg *cfg);
u32 (*get_lifetime_mg2)(struct mac_ax_adapter *adapter,
struct hv_ax_lifetime_mg2_cfg *cfg);
u32 (*ptn_h2c_common)(struct mac_ax_adapter *adapter,
struct rtw_g6_h2c_hdr *hdr,
u32 *pvalue);
u32 (*get_mac_err_isr)(struct mac_ax_adapter *adapter);
u32 (*get_gpio_status)(struct mac_ax_adapter *adapter,
enum rtw_mac_gfunc *func, u8 gpio);
u32 (*get_gpio_val)(struct mac_ax_adapter *adapter, u8 gpio, u8 *val);
u32 (*get_rxd_drv_info_unit)(struct mac_ax_adapter *adapter);
u32 (*get_ampdu_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_ampdu_cfg *cfg);
u32 (*get_edca_param)(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param);
u32 (*get_muedca_param)(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_param *param);
u32 (*get_muedca_timer)(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_timer *timer);
u32 (*get_muedca_ctrl)(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_cfg *cfg);
u32 (*get_ch_stat_cnt)(struct mac_ax_adapter *adapter,
struct mac_ax_ch_stat_cnt *cnt);
u32 (*get_lifetime_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_lifetime_cfg *cfg);
u32 (*get_hw_edcca_param)(struct mac_ax_adapter *adapter,
struct mac_ax_edcca_param *param);
u32 (*set_ofld_cfg)(struct mac_ax_adapter *adapter,
struct mac_ax_ofld_cfg *param);
u32 (*get_macid_pause)(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_cfg *cfg);
u32 (*get_hw_sch_tx_en)(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *cfg);
u32 (*set_hw_muedca_timer)(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_timer *timer);
u32 (*set_hw_ch_busy_cnt)(struct mac_ax_adapter *adapter,
struct mac_ax_ch_busy_cnt_cfg *cfg);
};
#endif
/**
* @brief mac_plat_auto_test
*
* @param *adapter
* @param *info
* @param test_module
* @return Please Place Description here.
* @retval u32
*/
u32 mac_plat_auto_test(struct mac_ax_adapter *adapter,
struct mac_ax_plat_auto_test *info,
enum mac_ax_plat_module test_module);
/**
* @brief mac_long_run_test
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_long_run_test(struct mac_ax_adapter *adapter,
struct mac_ax_mac_test *info);
/**
* @brief mac_flash_burn_test
*
* @param *adapter
* @param *fw
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_flash_burn_test(struct mac_ax_adapter *adapter,
u8 *fw, u32 len);
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/hv_type.h
|
C
|
agpl-3.0
| 29,039
|
# All needed files would be added to _HAL_INTFS_FILES, and it would include
# hal/hal_halmac.c and all related files in directory hal/halmac/.
# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC
# (CONFIG_RTL*) setting are all ready!
HAL = hal_g6
ifeq ($(CONFIG_PHL_ARCH), y)
phl_path := phl/hal_g6
phl_path_d1 := $(src)/phl/$(HAL)
else
phl_path := hal_g6
phl_path_d1 := $(src)/$(HAL)
endif
# Base directory
path_hm := $(phl_path)/mac
# Level 1 directory
path_hm_d1 := $(path_hm)/mac_ax
path_fw_d1 := $(path_hm)/fw_ax
ifeq ($(CONFIG_PCI_HCI), y)
pci := y
endif
ifeq ($(CONFIG_SDIO_HCI), y)
sdio := y
endif
ifeq ($(CONFIG_USB_HCI), y)
usb := y
endif
halmac-y += $(path_hm)/mac_ax.o
# Modify level 1 directory if needed
# $(path_hm_d1)/fwdl.o
halmac-y += $(path_hm_d1)/addr_cam.o \
$(path_hm_d1)/cmac_tx.o \
$(path_hm_d1)/coex.o \
$(path_hm_d1)/cpuio.o \
$(path_hm_d1)/dbgpkg.o \
$(path_hm_d1)/dbgport_hw.o \
$(path_hm_d1)/dbg_cmd.o \
$(path_hm_d1)/dle.o \
$(path_hm_d1)/efuse.o \
$(path_hm_d1)/fwcmd.o \
$(path_hm_d1)/fwdl.o \
$(path_hm_d1)/fwofld.o \
$(path_hm_d1)/gpio.o \
$(path_hm_d1)/hci_fc.o \
$(path_hm_d1)/hdr_conv.o \
$(path_hm_d1)/hw_seq.o \
$(path_hm_d1)/h2c_agg.o \
$(path_hm_d1)/hw.o \
$(path_hm_d1)/hwamsdu.o \
$(path_hm_d1)/init.o \
$(path_hm_d1)/la_mode.o \
$(path_hm_d1)/mcc.o \
$(path_hm_d1)/mport.o \
$(path_hm_d1)/phy_rpt.o \
$(path_hm_d1)/power_saving.o \
$(path_hm_d1)/pwr.o \
$(path_hm_d1)/p2p.o \
$(path_hm_d1)/role.o \
$(path_hm_d1)/rx_filter.o \
$(path_hm_d1)/rx_forwarding.o \
$(path_hm_d1)/rrsr.o \
$(path_hm_d1)/ser.o \
$(path_hm_d1)/security_cam.o \
$(path_hm_d1)/sounding.o \
$(path_hm_d1)/status.o \
$(path_hm_d1)/tblupd.o \
$(path_hm_d1)/tcpip_checksum_offload.o \
$(path_hm_d1)/trx_desc.o \
$(path_hm_d1)/trxcfg.o \
$(path_hm_d1)/twt.o \
$(path_hm_d1)/wowlan.o \
$(path_hm_d1)/flash.o \
$(path_hm_d1)/spatial_reuse.o \
$(path_hm_d1)/pwr_seq_func.o \
$(path_hm_d1)/phy_misc.o \
halmac-$(pci) += $(path_hm_d1)/_pcie.o
halmac-$(usb) += $(path_hm_d1)/_usb.o
halmac-$(sdio) += $(path_hm_d1)/_sdio.o
ifeq ($(CONFIG_RTL8852A), y)
ic := 8852a
endif
ifeq ($(CONFIG_RTL8852B), y)
ic := 8852b
endif
ifeq ($(CONFIG_RTL8852C), y)
ic := 8852c
endif
# Level 2 directory
path_hm2 := $(path_hm_d1)/mac_$(ic)
halmac-y += $(path_hm2)/gpio_$(ic).o \
$(path_hm2)/init_$(ic).o \
$(path_hm2)/pwr_seq_$(ic).o
halmac-$(usb) += $(path_hm2)/_usb_$(ic).o
ifeq ($(CONFIG_RTL8852B), y)
halmac-y += $(path_hm2)/pwr_seq_func_$(ic).o
endif
ifeq ($(CONFIG_RTL8852C), y)
halmac-y += $(path_hm2)/pwr_seq_func_$(ic).o \
$(path_hm2)/trx_desc_$(ic).o
endif
# fw files
path_fw := $(path_fw_d1)/rtl$(ic)
halmac-y += $(path_fw)/hal$(ic)_fw.o \
$(path_fw)/hal$(ic)_fw_log.o
ifeq ($(CONFIG_RTL8852B), y)
halmac-y += $(path_fw)/hal$(ic)_fw_u1.o
endif
_HAL_MAC_FILES += $(halmac-y)
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac.mk
|
Makefile
|
agpl-3.0
| 2,972
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "_pcie.h"
#include "pwr.h"
#if MAC_AX_PCIE_SUPPORT
static u32 init_cfg_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_INIT_CFG1, R_AX_PCIE_INIT_CFG1,
R_AX_HAXI_INIT_CFG1, R_AX_HAXI_INIT_CFG1
};
static u32 rxbd_mode_bit[MAC_AX_CHIP_ID_MAX] = {
B_AX_RXBD_MODE, B_AX_RXBD_MODE,
B_AX_RXBD_MODE_V1, B_AX_RXBD_MODE_V1
};
static u32 txhci_en_bit[MAC_AX_CHIP_ID_MAX] = {
B_AX_TXHCI_EN, B_AX_TXHCI_EN,
B_AX_TXHCI_EN_V1, B_AX_TXHCI_EN_V1
};
static u32 rxhci_en_bit[MAC_AX_CHIP_ID_MAX] = {
B_AX_RXHCI_EN, B_AX_RXHCI_EN,
B_AX_RXHCI_EN_V1, B_AX_RXHCI_EN_V1
};
static u32 dma_stop1_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_DMA_STOP1, R_AX_PCIE_DMA_STOP1,
R_AX_HAXI_DMA_STOP1, R_AX_HAXI_DMA_STOP1
};
static u32 dma_stop2_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_DMA_STOP2, R_AX_PCIE_DMA_STOP2,
R_AX_HAXI_DMA_STOP2, R_AX_HAXI_DMA_STOP2
};
static u32 dma_busy1_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_DMA_BUSY1, R_AX_PCIE_DMA_BUSY1,
R_AX_HAXI_DMA_BUSY1, R_AX_HAXI_DMA_BUSY1
};
static u32 txbd_rwptr_clr2_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_TXBD_RWPTR_CLR2, R_AX_TXBD_RWPTR_CLR2,
R_AX_TXBD_RWPTR_CLR2_V1, R_AX_TXBD_RWPTR_CLR2_V1
};
static u32 dma_busy2_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_DMA_BUSY2, R_AX_PCIE_DMA_BUSY2,
R_AX_HAXI_DMA_BUSY2, R_AX_HAXI_DMA_BUSY2
};
static u32 rxbd_rwptr_clr_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RXBD_RWPTR_CLR, R_AX_RXBD_RWPTR_CLR,
R_AX_RXBD_RWPTR_CLR_V1, R_AX_RXBD_RWPTR_CLR_V1
};
static u32 exp_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_EXP_CTRL, R_AX_PCIE_EXP_CTRL,
R_AX_HAXI_EXP_CTRL, R_AX_HAXI_EXP_CTRL
};
static u32 max_tag_num_sh[MAC_AX_CHIP_ID_MAX] = {
B_AX_MAX_TAG_NUM_SH, B_AX_MAX_TAG_NUM_SH,
B_AX_MAX_TAG_NUM_V1_SH, B_AX_MAX_TAG_NUM_V1_SH
};
static u32 max_tag_num_msk[MAC_AX_CHIP_ID_MAX] = {
B_AX_MAX_TAG_NUM_MSK, B_AX_MAX_TAG_NUM_MSK,
B_AX_MAX_TAG_NUM_V1_MSK, B_AX_MAX_TAG_NUM_V1_MSK
};
static u32 dma_busy3_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_PCIE_DMA_BUSY1, R_AX_PCIE_DMA_BUSY1,
R_AX_HAXI_DMA_BUSY3, R_AX_HAXI_DMA_BUSY3
};
static u32 ch10_txbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH10_TXBD_NUM, R_AX_CH10_TXBD_NUM,
R_AX_CH10_TXBD_NUM_V1, R_AX_CH10_TXBD_NUM_V1
};
static u32 ch11_txbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH11_TXBD_NUM, R_AX_CH11_TXBD_NUM,
R_AX_CH11_TXBD_NUM_V1, R_AX_CH11_TXBD_NUM_V1
};
static u32 ach0_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH0_TXBD_DESA_L, R_AX_ACH0_TXBD_DESA_L,
R_AX_ACH0_TXBD_DESA_L_V1, R_AX_ACH0_TXBD_DESA_L_V1
};
static u32 ach0_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH0_TXBD_DESA_H, R_AX_ACH0_TXBD_DESA_H,
R_AX_ACH0_TXBD_DESA_H_V1, R_AX_ACH0_TXBD_DESA_H_V1
};
static u32 ach1_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH1_TXBD_DESA_L, R_AX_ACH1_TXBD_DESA_L,
R_AX_ACH1_TXBD_DESA_L_V1, R_AX_ACH1_TXBD_DESA_L_V1
};
static u32 ach1_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH1_TXBD_DESA_H, R_AX_ACH1_TXBD_DESA_H,
R_AX_ACH1_TXBD_DESA_H_V1, R_AX_ACH1_TXBD_DESA_H_V1
};
static u32 ach2_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH2_TXBD_DESA_L, R_AX_ACH2_TXBD_DESA_L,
R_AX_ACH2_TXBD_DESA_L_V1, R_AX_ACH2_TXBD_DESA_L_V1
};
static u32 ach2_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH2_TXBD_DESA_H, R_AX_ACH2_TXBD_DESA_H,
R_AX_ACH2_TXBD_DESA_H_V1, R_AX_ACH2_TXBD_DESA_H_V1
};
static u32 ach3_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH3_TXBD_DESA_L, R_AX_ACH3_TXBD_DESA_L,
R_AX_ACH3_TXBD_DESA_L_V1, R_AX_ACH3_TXBD_DESA_L_V1
};
static u32 ach3_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH3_TXBD_DESA_H, R_AX_ACH3_TXBD_DESA_H,
R_AX_ACH3_TXBD_DESA_H_V1, R_AX_ACH3_TXBD_DESA_H_V1
};
static u32 ach4_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH4_TXBD_DESA_L, R_AX_ACH4_TXBD_DESA_L,
R_AX_ACH4_TXBD_DESA_L_V1, R_AX_ACH4_TXBD_DESA_L_V1
};
static u32 ach4_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH4_TXBD_DESA_H, R_AX_ACH4_TXBD_DESA_H,
R_AX_ACH4_TXBD_DESA_H_V1, R_AX_ACH4_TXBD_DESA_H_V1
};
static u32 ach5_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH5_TXBD_DESA_L, R_AX_ACH5_TXBD_DESA_L,
R_AX_ACH5_TXBD_DESA_L_V1, R_AX_ACH5_TXBD_DESA_L_V1
};
static u32 ach5_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH5_TXBD_DESA_H, R_AX_ACH5_TXBD_DESA_H,
R_AX_ACH5_TXBD_DESA_H_V1, R_AX_ACH5_TXBD_DESA_H_V1
};
static u32 ach6_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH6_TXBD_DESA_L, R_AX_ACH6_TXBD_DESA_L,
R_AX_ACH6_TXBD_DESA_L_V1, R_AX_ACH6_TXBD_DESA_L_V1
};
static u32 ach6_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH6_TXBD_DESA_H, R_AX_ACH6_TXBD_DESA_H,
R_AX_ACH6_TXBD_DESA_H_V1, R_AX_ACH6_TXBD_DESA_H_V1
};
static u32 ach7_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH7_TXBD_DESA_L, R_AX_ACH7_TXBD_DESA_L,
R_AX_ACH7_TXBD_DESA_L_V1, R_AX_ACH7_TXBD_DESA_L_V1
};
static u32 ach7_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH7_TXBD_DESA_H, R_AX_ACH7_TXBD_DESA_H,
R_AX_ACH7_TXBD_DESA_H_V1, R_AX_ACH7_TXBD_DESA_H_V1
};
static u32 ch8_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH8_TXBD_DESA_L, R_AX_CH8_TXBD_DESA_L,
R_AX_CH8_TXBD_DESA_L_V1, R_AX_CH8_TXBD_DESA_L_V1
};
static u32 ch8_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH8_TXBD_DESA_H, R_AX_CH8_TXBD_DESA_H,
R_AX_CH8_TXBD_DESA_H_V1, R_AX_CH8_TXBD_DESA_H_V1
};
static u32 ch9_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH9_TXBD_DESA_L, R_AX_CH9_TXBD_DESA_L,
R_AX_CH9_TXBD_DESA_L_V1, R_AX_CH9_TXBD_DESA_L_V1
};
static u32 ch9_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH9_TXBD_DESA_H, R_AX_CH9_TXBD_DESA_H,
R_AX_CH9_TXBD_DESA_H_V1, R_AX_CH9_TXBD_DESA_H_V1
};
static u32 ch10_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH10_TXBD_DESA_L, R_AX_CH10_TXBD_DESA_L,
R_AX_CH10_TXBD_DESA_L_V1, R_AX_CH10_TXBD_DESA_L_V1
};
static u32 ch10_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH10_TXBD_DESA_H, R_AX_CH10_TXBD_DESA_H,
R_AX_CH10_TXBD_DESA_H_V1, R_AX_CH10_TXBD_DESA_H_V1
};
static u32 ch11_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH11_TXBD_DESA_L, R_AX_CH11_TXBD_DESA_L,
R_AX_CH11_TXBD_DESA_L_V1, R_AX_CH11_TXBD_DESA_L_V1
};
static u32 ch11_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH11_TXBD_DESA_H, R_AX_CH11_TXBD_DESA_H,
R_AX_CH11_TXBD_DESA_H_V1, R_AX_CH11_TXBD_DESA_H_V1
};
static u32 ch12_txbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH12_TXBD_DESA_L, R_AX_CH12_TXBD_DESA_L,
R_AX_CH12_TXBD_DESA_L_V1, R_AX_CH12_TXBD_DESA_L_V1
};
static u32 ch12_txbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH12_TXBD_DESA_H, R_AX_CH12_TXBD_DESA_H,
R_AX_CH12_TXBD_DESA_H_V1, R_AX_CH12_TXBD_DESA_H_V1
};
static u32 ach0_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH0_BDRAM_CTRL, R_AX_ACH0_BDRAM_CTRL,
R_AX_ACH0_BDRAM_CTRL_V1, R_AX_ACH0_BDRAM_CTRL_V1
};
static u32 ach1_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH1_BDRAM_CTRL, R_AX_ACH1_BDRAM_CTRL,
R_AX_ACH1_BDRAM_CTRL_V1, R_AX_ACH1_BDRAM_CTRL_V1
};
static u32 ach2_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH2_BDRAM_CTRL, R_AX_ACH2_BDRAM_CTRL,
R_AX_ACH2_BDRAM_CTRL_V1, R_AX_ACH2_BDRAM_CTRL_V1
};
static u32 ach3_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH3_BDRAM_CTRL, R_AX_ACH3_BDRAM_CTRL,
R_AX_ACH3_BDRAM_CTRL_V1, R_AX_ACH3_BDRAM_CTRL_V1
};
static u32 ach4_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH4_BDRAM_CTRL, R_AX_ACH4_BDRAM_CTRL,
R_AX_ACH4_BDRAM_CTRL_V1, R_AX_ACH4_BDRAM_CTRL_V1
};
static u32 ach5_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH5_BDRAM_CTRL, R_AX_ACH5_BDRAM_CTRL,
R_AX_ACH5_BDRAM_CTRL_V1, R_AX_ACH5_BDRAM_CTRL_V1
};
static u32 ach6_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH6_BDRAM_CTRL, R_AX_ACH6_BDRAM_CTRL,
R_AX_ACH6_BDRAM_CTRL_V1, R_AX_ACH6_BDRAM_CTRL_V1
};
static u32 ach7_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_ACH7_BDRAM_CTRL, R_AX_ACH7_BDRAM_CTRL,
R_AX_ACH7_BDRAM_CTRL_V1, R_AX_ACH7_BDRAM_CTRL_V1
};
static u32 ch8_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH8_BDRAM_CTRL, R_AX_CH8_BDRAM_CTRL,
R_AX_CH8_BDRAM_CTRL_V1, R_AX_CH8_BDRAM_CTRL_V1
};
static u32 ch9_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH9_BDRAM_CTRL, R_AX_CH9_BDRAM_CTRL,
R_AX_CH9_BDRAM_CTRL_V1, R_AX_CH9_BDRAM_CTRL_V1
};
static u32 ch10_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH10_BDRAM_CTRL, R_AX_CH10_BDRAM_CTRL,
R_AX_CH10_BDRAM_CTRL_V1, R_AX_CH10_BDRAM_CTRL_V1
};
static u32 ch11_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH11_BDRAM_CTRL, R_AX_CH11_BDRAM_CTRL,
R_AX_CH11_BDRAM_CTRL_V1, R_AX_CH11_BDRAM_CTRL_V1
};
static u32 ch12_bdram_ctrl_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_CH12_BDRAM_CTRL, R_AX_CH12_BDRAM_CTRL,
R_AX_CH12_BDRAM_CTRL_V1, R_AX_CH12_BDRAM_CTRL_V1
};
static u32 rxq_rxbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RXQ_RXBD_DESA_L, R_AX_RXQ_RXBD_DESA_L,
R_AX_RXQ_RXBD_DESA_L_V1, R_AX_RXQ_RXBD_DESA_L_V1
};
static u32 rxq_rxbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RXQ_RXBD_DESA_H, R_AX_RXQ_RXBD_DESA_H,
R_AX_RXQ_RXBD_DESA_H_V1, R_AX_RXQ_RXBD_DESA_H_V1
};
static u32 rpq_rxbd_desa_l_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RPQ_RXBD_DESA_L, R_AX_RPQ_RXBD_DESA_L,
R_AX_RPQ_RXBD_DESA_L_V1, R_AX_RPQ_RXBD_DESA_L_V1
};
static u32 rpq_rxbd_desa_h_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RPQ_RXBD_DESA_H, R_AX_RPQ_RXBD_DESA_H,
R_AX_RPQ_RXBD_DESA_H_V1, R_AX_RPQ_RXBD_DESA_H_V1
};
static u32 rxq_rxbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RXQ_RXBD_NUM, R_AX_RXQ_RXBD_NUM,
R_AX_RXQ_RXBD_NUM_V1, R_AX_RXQ_RXBD_NUM_V1
};
static u32 rpq_rxbd_num_reg[MAC_AX_CHIP_ID_MAX] = {
R_AX_RPQ_RXBD_NUM, R_AX_RPQ_RXBD_NUM,
R_AX_RPQ_RXBD_NUM_V1, R_AX_RPQ_RXBD_NUM_V1
};
struct txbd_ram mac_bdram_tbl_8852a[] = {
/* ACH0_QUEUE_IDX_8852AE */ {0, 5, 2},
/* ACH1_QUEUE_IDX_8852AE */ {5, 5, 2},
/* ACH2_QUEUE_IDX_8852AE */ {10, 5, 2},
/* ACH3_QUEUE_IDX_8852AE */ {15, 5, 2},
/* ACH4_QUEUE_IDX_8852AE */ {20, 5, 2},
/* ACH5_QUEUE_IDX_8852AE */ {25, 5, 2},
/* ACH6_QUEUE_IDX_8852AE */ {30, 5, 2},
/* ACH7_QUEUE_IDX_8852AE */ {35, 5, 2},
/* MGQ_B0_QUEUE_IDX_8852AE */ {40, 5, 1},
/* HIQ_B0_QUEUE_IDX_8852AE */ {45, 5, 1},
/* MGQ_B1_QUEUE_IDX_8852AE */ {50, 5, 1},
/* HIQ_B1_QUEUE_IDX_8852AE */ {55, 5, 1},
/* FWCMD_QUEUE_IDX_8852AE */ {60, 4, 1}
};
struct txbd_ram mac_bdram_tbl_8852b[] = {
/* ACH0_QUEUE_IDX_8852BE */ {0, 5, 2},
/* ACH1_QUEUE_IDX_8852BE */ {5, 5, 2},
/* ACH2_QUEUE_IDX_8852BE */ {10, 5, 2},
/* ACH3_QUEUE_IDX_8852BE */ {15, 5, 2},
/* MGQ_B0_QUEUE_IDX_8852BE */ {20, 4, 1},
/* HIQ_B0_QUEUE_IDX_8852BE */ {24, 4, 1},
/* FWCMD_QUEUE_IDX_8852BE */ {28, 4, 1}
};
struct txbd_ram mac_bdram_tbl_8852c[] = {
/* ACH0_QUEUE_IDX_8852AE */ {0, 5, 2},
/* ACH1_QUEUE_IDX_8852AE */ {5, 5, 2},
/* ACH2_QUEUE_IDX_8852AE */ {10, 5, 2},
/* ACH3_QUEUE_IDX_8852AE */ {15, 5, 2},
/* ACH4_QUEUE_IDX_8852AE */ {20, 5, 2},
/* ACH5_QUEUE_IDX_8852AE */ {25, 5, 2},
/* ACH6_QUEUE_IDX_8852AE */ {30, 5, 2},
/* ACH7_QUEUE_IDX_8852AE */ {35, 5, 2},
/* MGQ_B0_QUEUE_IDX_8852AE */ {40, 5, 1},
/* HIQ_B0_QUEUE_IDX_8852AE */ {45, 5, 1},
/* MGQ_B1_QUEUE_IDX_8852AE */ {50, 5, 1},
/* HIQ_B1_QUEUE_IDX_8852AE */ {55, 5, 1},
/* FWCMD_QUEUE_IDX_8852AE */ {60, 4, 1}
};
struct txbd_ram mac_bdram_tbl_8192xb[] = {
/* ACH0_QUEUE_IDX_8852AE */ {0, 5, 2},
/* ACH1_QUEUE_IDX_8852AE */ {5, 5, 2},
/* ACH2_QUEUE_IDX_8852AE */ {10, 5, 2},
/* ACH3_QUEUE_IDX_8852AE */ {15, 5, 2},
/* ACH4_QUEUE_IDX_8852AE */ {20, 5, 2},
/* ACH5_QUEUE_IDX_8852AE */ {25, 5, 2},
/* ACH6_QUEUE_IDX_8852AE */ {30, 5, 2},
/* ACH7_QUEUE_IDX_8852AE */ {35, 5, 2},
/* MGQ_B0_QUEUE_IDX_8852AE */ {40, 5, 1},
/* HIQ_B0_QUEUE_IDX_8852AE */ {45, 5, 1},
/* MGQ_B1_QUEUE_IDX_8852AE */ {50, 5, 1},
/* HIQ_B1_QUEUE_IDX_8852AE */ {55, 5, 1},
/* FWCMD_QUEUE_IDX_8852AE */ {60, 4, 1}
};
static struct mac_ax_intf_info intf_info_def_8852a = {
MAC_AX_BD_TRUNC,
MAC_AX_BD_TRUNC,
MAC_AX_RXBD_PKT,
MAC_AX_TAG_MULTI,
MAC_AX_TX_BURST_2048B,
MAC_AX_RX_BURST_128B,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_TAG_NUM_8,
0,
NULL,
NULL,
0,
NULL,
MAC_AX_PCIE_ENABLE,
MAC_AX_LBC_TMR_2MS,
MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_DISABLE,
MAC_AX_IO_RCY_ANA_TMR_60US
};
static struct mac_ax_intf_info intf_info_def_8852b = {
MAC_AX_BD_TRUNC,
MAC_AX_BD_TRUNC,
MAC_AX_RXBD_PKT,
MAC_AX_TAG_MULTI,
MAC_AX_TX_BURST_2048B,
MAC_AX_RX_BURST_128B,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_TAG_NUM_8,
0,
NULL,
NULL,
0,
NULL,
MAC_AX_PCIE_ENABLE,
MAC_AX_LBC_TMR_2MS,
MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_DISABLE,
MAC_AX_IO_RCY_ANA_TMR_60US
};
static struct mac_ax_intf_info intf_info_def_8852c = {
MAC_AX_BD_NORM,
MAC_AX_BD_NORM,
MAC_AX_RXBD_SEP,
MAC_AX_TAG_MULTI,
MAC_AX_TX_BURST_V1_256B,
MAC_AX_RX_BURST_V1_128B,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_TAG_NUM_8,
0,
NULL,
NULL,
0,
NULL,
MAC_AX_PCIE_ENABLE,
MAC_AX_LBC_TMR_2MS,
MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_ENABLE,
MAC_AX_IO_RCY_ANA_TMR_60US
};
static struct mac_ax_intf_info intf_info_def_8192xb = {
MAC_AX_BD_NORM,
MAC_AX_BD_NORM,
MAC_AX_RXBD_SEP,
MAC_AX_TAG_MULTI,
MAC_AX_TX_BURST_V1_256B,
MAC_AX_RX_BURST_V1_128B,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_WD_DMA_INTVL_256NS,
MAC_AX_TAG_NUM_8,
0,
NULL,
NULL,
0,
NULL,
MAC_AX_PCIE_ENABLE,
MAC_AX_LBC_TMR_2MS,
};
static struct mac_ax_pcie_cfgspc_param pcie_cfgspc_param_def = {
0,
0,
MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_ENABLE,
MAC_AX_PCIE_ENABLE,
MAC_AX_PCIE_ENABLE,
MAC_AX_PCIE_ENABLE,
MAC_AX_PCIE_CLKDLY_30US,
MAC_AX_PCIE_L0SDLY_4US,
MAC_AX_PCIE_L1DLY_16US
};
static struct mac_ax_pcie_ltr_param pcie_ltr_param_def = {
0,
0,
MAC_AX_PCIE_ENABLE,
MAC_AX_PCIE_ENABLE,
MAC_AX_PCIE_LTR_SPC_500US,
MAC_AX_PCIE_LTR_IDLE_TIMER_3_2MS,
{MAC_AX_PCIE_ENABLE, 0x28},
{MAC_AX_PCIE_ENABLE, 0x28},
{MAC_AX_PCIE_ENABLE, 0x90039003},
{MAC_AX_PCIE_ENABLE, 0x880b880b}
};
u8 reg_read8_pcie(struct mac_ax_adapter *adapter, u32 addr)
{
u8 offset, count = 0, val8;
u32 val, addr_shift;
if (addr >= R_AX_CMAC_FUNC_EN && addr <= R_AX_CMAC_REG_END) {
offset = addr & (MAC_REG_OFFSET - 1);
addr_shift = addr - offset;
val = PLTFM_REG_R32(addr_shift);
while (count < MAC_REG_POOL_COUNT) {
if (val != MAC_AX_R32_DEAD)
break;
PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
val = PLTFM_REG_R32(addr_shift);
count++;
}
val8 = (u8)(val >> (offset << MAC_REG_OFFSET_SH_2));
} else {
val8 = PLTFM_REG_R8(addr);
}
if (count == MAC_REG_POOL_COUNT && adapter->sm.l2_st == MAC_AX_L2_EN) {
adapter->sm.l2_st = MAC_AX_L2_TRIG;
PLTFM_L2_NOTIFY(void);
}
return val8;
}
void reg_write8_pcie(struct mac_ax_adapter *adapter, u32 addr, u8 val)
{
PLTFM_REG_W8(addr, val);
}
u16 reg_read16_pcie(struct mac_ax_adapter *adapter, u32 addr)
{
u8 offset, count = 0;
u16 val16;
u32 val, addr_shift;
if ((addr & (MAC_REG_OFFSET16 - 1)) != 0) {
PLTFM_MSG_ERR("[ERR]read16 failaddr 0x%x\n", addr);
return MAC_AX_R16_DEAD;
}
if (addr >= R_AX_CMAC_FUNC_EN && addr <= R_AX_CMAC_REG_END) {
offset = addr & (MAC_REG_OFFSET - 1);
addr_shift = addr - offset;
val = PLTFM_REG_R32(addr_shift);
while (count < MAC_REG_POOL_COUNT) {
if (val != MAC_AX_R32_DEAD)
break;
PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
val = PLTFM_REG_R32(addr_shift);
count++;
}
val16 = (u16)(val >> (offset << MAC_REG_OFFSET_SH_2));
} else {
val16 = PLTFM_REG_R16(addr);
}
if (count == MAC_REG_POOL_COUNT && adapter->sm.l2_st == MAC_AX_L2_EN) {
adapter->sm.l2_st = MAC_AX_L2_TRIG;
PLTFM_L2_NOTIFY(void);
}
return val16;
}
void reg_write16_pcie(struct mac_ax_adapter *adapter, u32 addr, u16 val)
{
PLTFM_REG_W16(addr, val);
}
u32 reg_read32_pcie(struct mac_ax_adapter *adapter, u32 addr)
{
u8 count = 0;
u32 val = PLTFM_REG_R32(addr);
if (addr >= R_AX_CMAC_FUNC_EN && addr <= R_AX_CMAC_REG_END) {
while (count < MAC_REG_POOL_COUNT) {
if (val != MAC_AX_R32_DEAD)
break;
PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
val = PLTFM_REG_R32(addr);
count++;
}
}
if (count == MAC_REG_POOL_COUNT && adapter->sm.l2_st == MAC_AX_L2_EN) {
adapter->sm.l2_st = MAC_AX_L2_TRIG;
PLTFM_L2_NOTIFY(void);
}
return val;
}
void reg_write32_pcie(struct mac_ax_adapter *adapter, u32 addr, u32 val)
{
PLTFM_REG_W32(addr, val);
}
u32 dbi_r32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 r_addr = addr & DBI_ADDR_MASK;
u32 val32, cnt;
u32 ret = MACSUCCESS;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
if (addr & DBI_ADDR_2LSB_MASK) {
PLTFM_MSG_ERR("[ERR]DBI R32 addr 0x%X not 4B align\n", addr);
return MACFUNCINPUT;
}
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
val32 = 0;
val32 = SET_CLR_WORD(val32, r_addr, B_AX_DBI_ADDR);
MAC_REG_W32(R_AX_DBI_FLAG, val32);
val32 |= B_AX_DBI_RFLAG;
MAC_REG_W32(R_AX_DBI_FLAG, val32);
cnt = DBI_DLY_CNT;
while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_RFLAG && cnt) {
PLTFM_DELAY_US(DBI_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]DBI R32 0x%X timeout\n", r_addr);
ret = MACPOLLTO;
goto end;
}
*val = MAC_REG_R32(R_AX_DBI_RDATA);
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
return ret;
}
u32 dbi_w32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 data)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 w_addr = addr & DBI_ADDR_MASK;
u32 val32, cnt;
u32 ret = MACSUCCESS;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
MAC_REG_W32(R_AX_DBI_WDATA, data);
val32 = 0;
val32 = SET_CLR_WORD(val32, w_addr, B_AX_DBI_ADDR);
val32 = SET_CLR_WORD(val32, DBI_WEN_DW, B_AX_DBI_WREN);
MAC_REG_W32(R_AX_DBI_FLAG, val32);
val32 |= B_AX_DBI_WFLAG;
MAC_REG_W32(R_AX_DBI_FLAG, val32);
cnt = DBI_DLY_CNT;
while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_WFLAG && cnt) {
PLTFM_DELAY_US(DBI_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]DBI W32 0x%X = 0x%x timeout\n", w_addr, data);
ret = MACPOLLTO;
goto end;
}
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
return ret;
}
u32 dbi_r8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 r_addr = addr & DBI_ADDR_MASK;
u32 addr_2lsb = addr & DBI_ADDR_2LSB_MASK;
u32 val32, cnt;
u32 ret = MACSUCCESS;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
val32 = 0;
val32 = SET_CLR_WORD(val32, r_addr, B_AX_DBI_ADDR);
MAC_REG_W32(R_AX_DBI_FLAG, val32);
val32 |= B_AX_DBI_RFLAG;
MAC_REG_W32(R_AX_DBI_FLAG, val32);
cnt = DBI_DLY_CNT;
while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_RFLAG && cnt) {
PLTFM_DELAY_US(DBI_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]DBI R8 0x%X timeout\n", r_addr);
ret = MACPOLLTO;
goto end;
}
*val = MAC_REG_R8(R_AX_DBI_RDATA + addr_2lsb);
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
return ret;
}
u32 dbi_w8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 data)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 w_addr = addr & DBI_ADDR_MASK;
u32 addr_2lsb = addr & DBI_ADDR_2LSB_MASK;
u32 val32, cnt;
u32 ret = MACSUCCESS;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbi_lock);
MAC_REG_W8(R_AX_DBI_WDATA + addr_2lsb, data);
val32 = 0;
val32 = SET_CLR_WORD(val32, w_addr, B_AX_DBI_ADDR);
val32 = SET_CLR_WORD(val32, DBI_WEN_B << addr_2lsb, B_AX_DBI_WREN);
MAC_REG_W32(R_AX_DBI_FLAG, val32);
val32 |= B_AX_DBI_WFLAG;
MAC_REG_W32(R_AX_DBI_FLAG, val32);
cnt = DBI_DLY_CNT;
while (MAC_REG_R32(R_AX_DBI_FLAG) & B_AX_DBI_WFLAG && cnt) {
PLTFM_DELAY_US(DBI_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]DBI W8 0x%X = 0x%x timeout\n", w_addr, data);
ret = MACPOLLTO;
goto end;
}
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbi_lock);
return ret;
}
u32 mdio_r16_pcie(struct mac_ax_adapter *adapter, u8 addr, u8 speed, u16 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u16 val16;
u32 cnt;
u32 ret = MACSUCCESS;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
PLTFM_MUTEX_LOCK(&adapter->hw_info->mdio_lock);
MAC_REG_W8(R_AX_MDIO_CFG, addr & B_AX_MDIO_ADDR_MSK);
val16 = MAC_REG_R16(R_AX_MDIO_CFG);
if (speed == MAC_AX_PCIE_PHY_GEN1 && addr < MDIO_ADDR_PG1) {
val16 = SET_CLR_WORD(val16, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR);
} else if (speed == MAC_AX_PCIE_PHY_GEN1) {
val16 = SET_CLR_WORD(val16, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR);
} else if (speed == MAC_AX_PCIE_PHY_GEN2 && addr < MDIO_ADDR_PG1) {
val16 = SET_CLR_WORD(val16, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR);
} else if (speed == MAC_AX_PCIE_PHY_GEN2) {
val16 = SET_CLR_WORD(val16, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR);
} else {
PLTFM_MSG_ERR("[ERR]Error MDIO PHY Speed %d!\n", speed);
ret = MACFUNCINPUT;
goto end;
}
MAC_REG_W16(R_AX_MDIO_CFG, val16);
MAC_REG_W16(R_AX_MDIO_CFG,
MAC_REG_R16(R_AX_MDIO_CFG) | B_AX_MDIO_RFLAG);
cnt = MDIO_DLY_CNT;
while (MAC_REG_R16(R_AX_MDIO_CFG) & B_AX_MDIO_RFLAG && cnt) {
PLTFM_DELAY_US(MDIO_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]MDIO R16 0x%X timeout\n", addr);
ret = MACPOLLTO;
goto end;
}
*val = MAC_REG_R16(R_AX_MDIO_RDATA);
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->mdio_lock);
return ret;
}
u32 mdio_w16_pcie(struct mac_ax_adapter *adapter, u8 addr, u16 data, u8 speed)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u16 val16;
u32 cnt;
u32 ret = MACSUCCESS;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
PLTFM_MUTEX_LOCK(&adapter->hw_info->mdio_lock);
MAC_REG_W16(R_AX_MDIO_WDATA, data);
MAC_REG_W8(R_AX_MDIO_CFG, addr & B_AX_MDIO_ADDR_MSK);
val16 = MAC_REG_R16(R_AX_MDIO_CFG);
if (speed == MAC_AX_PCIE_PHY_GEN1 && addr < MDIO_ADDR_PG1) {
val16 = SET_CLR_WORD(val16, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR);
} else if (speed == MAC_AX_PCIE_PHY_GEN1) {
val16 = SET_CLR_WORD(val16, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR);
} else if (speed == MAC_AX_PCIE_PHY_GEN2 && addr < MDIO_ADDR_PG1) {
val16 = SET_CLR_WORD(val16, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR);
} else if (speed == MAC_AX_PCIE_PHY_GEN2) {
val16 = SET_CLR_WORD(val16, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR);
} else {
PLTFM_MSG_ERR("[ERR]Error MDIO PHY Speed %d!\n", speed);
ret = MACFUNCINPUT;
goto end;
}
MAC_REG_W16(R_AX_MDIO_CFG, val16);
MAC_REG_W16(R_AX_MDIO_CFG,
MAC_REG_R16(R_AX_MDIO_CFG) | B_AX_MDIO_WFLAG);
cnt = MDIO_DLY_CNT;
while (MAC_REG_R16(R_AX_MDIO_CFG) & B_AX_MDIO_WFLAG && cnt) {
PLTFM_DELAY_US(MDIO_DLY_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]MDIO W16 0x%X = 0x%x timeout!\n", addr, data);
ret = MACPOLLTO;
goto end;
}
end:
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->mdio_lock);
return ret;
}
static u32 get_target(struct mac_ax_adapter *adapter, u16 *target,
enum mac_ax_pcie_phy phy_rate)
{
u16 tmp_u16, count;
u16 tar;
u32 ret = MACSUCCESS;
/* Enable counter */
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
if (ret != MACSUCCESS)
return ret;
ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16 & ~B_AX_CLK_CALIB_EN,
phy_rate);
if (ret != MACSUCCESS)
return ret;
ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16 | B_AX_CLK_CALIB_EN,
phy_rate);
if (ret != MACSUCCESS)
return ret;
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tar);
if (ret != MACSUCCESS)
return ret;
count = PCIE_POLL_AUTOK_CNT;
while (count && (tar & B_AX_CLK_CALIB_EN)) {
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tar);
if (ret != MACSUCCESS)
return ret;
count--;
PLTFM_DELAY_US(PCIE_POLL_AUTOK_DLY_US);
}
if (!count) {
PLTFM_MSG_ERR("[ERR]AutoK get target timeout: %X\n", tar);
return MACPOLLTO;
}
tar = tar & 0x0FFF;
if (tar == 0 || tar == 0x0FFF) {
PLTFM_MSG_ERR("[ERR]Get target failed.\n");
return MACHWERR;
}
*target = tar;
return MACSUCCESS;
}
static u32 mac_auto_refclk_cal_pcie(struct mac_ax_adapter *adapter,
enum mac_ax_pcie_func_ctrl en)
{
u8 bdr_ori, val8;
u16 tmp_u16;
u16 div_set;
u16 mgn_tmp;
u16 mgn_set;
u16 tar;
u8 l1_flag = 0;
u32 ret = MACSUCCESS;
enum mac_ax_pcie_phy phy_rate = MAC_AX_PCIE_PHY_GEN1;
#if MAC_AX_FEATURE_HV
if (adapter->env == HV_AX_FPGA)
return MACSUCCESS;
#endif
#if (INTF_INTGRA_HOSTREF_V1 <= INTF_INTGRA_MINREF_V1)
PLTFM_MSG_ERR("[ERR]INTF_INTGRA_MINREF_V1 define fail\n");
return MACCMP;
#endif
ret = dbi_r8_pcie(adapter, PCIE_PHY_RATE, &val8);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dbi_r8_pcie 0x%x\n", PCIE_PHY_RATE);
return ret;
}
if ((val8 & (BIT1 | BIT0)) == 0x1) {
phy_rate = MAC_AX_PCIE_PHY_GEN1;
} else if ((val8 & (BIT1 | BIT0)) == 0x2) {
phy_rate = MAC_AX_PCIE_PHY_GEN2;
} else {
PLTFM_MSG_ERR("[ERR]PCIe PHY rate not support\n");
return MACHWNOSUP;
}
/* Disable L1BD */
ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &bdr_ori);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dbi_r8_pcie 0x%X\n", PCIE_L1_CTRL);
return ret;
}
if (bdr_ori & PCIE_BIT_L1) {
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL,
bdr_ori & ~(PCIE_BIT_L1));
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dbi_w8_pcie 0x%X\n", PCIE_L1_CTRL);
return ret;
}
l1_flag = 1;
}
/* Disable function */
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
if (tmp_u16 & BIT(13)) {
ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1,
tmp_u16 & ~(BIT(13)), phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n",
RAC_CTRL_PPR_V1);
goto end;
}
}
if (en != MAC_AX_PCIE_ENABLE)
goto end;
/* Set div */
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1,
tmp_u16 & ~(BIT(15) | BIT(14)), phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
/* Obtain div and margin */
ret = get_target(adapter, &tar, phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]1st get target fail %d\n", ret);
goto end;
}
mgn_tmp = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar;
if (mgn_tmp >= 128) {
div_set = 0x0003;
mgn_set = 0x000F;
} else if (mgn_tmp >= 64) {
div_set = 0x0003;
mgn_set = mgn_tmp >> 3;
} else if (mgn_tmp >= 32) {
div_set = 0x0002;
mgn_set = mgn_tmp >> 2;
} else if (mgn_tmp >= 16) {
div_set = 0x0001;
mgn_set = mgn_tmp >> 1;
} else if (mgn_tmp == 0) {
PLTFM_MSG_ERR("[ERR]cal mgn is 0,tar = %d\n", tar);
goto end;
} else {
div_set = 0x0000;
mgn_set = mgn_tmp;
}
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
tmp_u16 = (tmp_u16 & ~(BIT(15) | BIT(14))) | (div_set << 14);
ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16, phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
ret = get_target(adapter, &tar, phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]2nd get target fail %d\n", ret);
goto end;
}
PLTFM_MSG_TRACE("[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n",
tar, div_set, mgn_set);
ret = mdio_w16_pcie(adapter, RAC_SET_PPR_V1,
(tar & 0x0FFF) | (mgn_set << 12), phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_SET_PPR_V1);
goto end;
}
/* Enable function */
ret = mdio_r16_pcie(adapter, RAC_CTRL_PPR_V1, phy_rate, &tmp_u16);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_r16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
ret = mdio_w16_pcie(adapter, RAC_CTRL_PPR_V1, tmp_u16 | BIT(13),
phy_rate);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]mdio_w16_pcie 0x%X\n", RAC_CTRL_PPR_V1);
goto end;
}
/* CLK delay = 0 */
ret = dbi_w8_pcie(adapter, PCIE_CLK_CTRL, PCIE_CLKDLY_HW_0);
end:
/* Set L1BD to ori */
if (l1_flag == 1) {
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, bdr_ori);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dbi_w8_pcie 0x%X\n", PCIE_L1_CTRL);
return ret;
}
}
PLTFM_MSG_TRACE("[TRACE]%s: <==\n", __func__);
return ret;
}
static void update_pcie_func(u8 *val, u8 bitmask,
enum mac_ax_pcie_func_ctrl ctrl,
enum mac_ax_pcie_func_ctrl def_ctrl)
{
if ((ctrl == MAC_AX_PCIE_DEFAULT &&
(def_ctrl == MAC_AX_PCIE_IGNORE ||
def_ctrl == MAC_AX_PCIE_DEFAULT)) || ctrl == MAC_AX_PCIE_IGNORE)
return;
if ((ctrl == MAC_AX_PCIE_DEFAULT && def_ctrl == MAC_AX_PCIE_DISABLE) ||
ctrl == MAC_AX_PCIE_DISABLE)
*val &= ~(bitmask);
else
*val |= bitmask;
}
static u32 chk_stus_l1ss(struct mac_ax_adapter *adapter, u8 *val)
{
u16 cap_val;
u8 stus_val;
u8 sup_val;
u32 ret;
u8 val8_1, val8_2;
ret = dbi_r8_pcie(adapter, PCIE_L1SS_CAP + 1, &val8_1);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_L1SS_CAP, &val8_2);
if (ret != MACSUCCESS)
return ret;
cap_val = (u16)((val8_1 << 8) | val8_2);
ret = dbi_r8_pcie(adapter, PCIE_L1SS_SUP, &sup_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_L1SS_STS, &stus_val);
if (ret != MACSUCCESS)
return ret;
if (cap_val == PCIE_L1SS_ID &&
(sup_val & PCIE_BIT_L1SSSUP) &&
(sup_val & PCIE_L1SS_MASK) != 0 &&
(stus_val & PCIE_L1SS_MASK) != 0)
*val = 1;
else
*val = 0;
return ret;
}
u32 update_clkdly(struct mac_ax_adapter *adapter, u8 *val,
enum mac_ax_pcie_clkdly ctrl,
enum mac_ax_pcie_clkdly def_ctrl)
{
u8 tmp;
if (ctrl == MAC_AX_PCIE_CLKDLY_IGNORE ||
def_ctrl == MAC_AX_PCIE_CLKDLY_IGNORE)
return MACSUCCESS;
tmp = (ctrl == MAC_AX_PCIE_CLKDLY_DEF) ? def_ctrl : ctrl;
switch (tmp) {
case MAC_AX_PCIE_CLKDLY_0:
*val = PCIE_CLKDLY_HW_0;
break;
case MAC_AX_PCIE_CLKDLY_30US:
*val = PCIE_CLKDLY_HW_30US;
break;
case MAC_AX_PCIE_CLKDLY_50US:
*val = PCIE_CLKDLY_HW_50US;
break;
case MAC_AX_PCIE_CLKDLY_100US:
*val = PCIE_CLKDLY_HW_100US;
break;
case MAC_AX_PCIE_CLKDLY_150US:
*val = PCIE_CLKDLY_HW_150US;
break;
case MAC_AX_PCIE_CLKDLY_200US:
*val = PCIE_CLKDLY_HW_200US;
break;
case MAC_AX_PCIE_CLKDLY_300US:
*val = PCIE_CLKDLY_HW_300US;
break;
case MAC_AX_PCIE_CLKDLY_400US:
*val = PCIE_CLKDLY_HW_400US;
break;
case MAC_AX_PCIE_CLKDLY_500US:
*val = PCIE_CLKDLY_HW_500US;
break;
case MAC_AX_PCIE_CLKDLY_1MS:
*val = PCIE_CLKDLY_HW_1MS;
break;
case MAC_AX_PCIE_CLKDLY_3MS:
*val = PCIE_CLKDLY_HW_3MS;
break;
default:
PLTFM_MSG_ERR("[ERR]CLKDLY wt val illegal!\n");
return MACSTCAL;
}
return MACSUCCESS;
}
static u32 update_pcie_clk(struct mac_ax_adapter *adapter, u8 *val)
{
u32 ret = MACSUCCESS;
if (*val & PCIE_BIT_CLK)
return MACSUCCESS;
if (*val & PCIE_BIT_L1) {
*val &= ~(PCIE_BIT_L1);
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
if (ret != MACSUCCESS)
return ret;
*val |= PCIE_BIT_CLK;
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
if (ret != MACSUCCESS)
return ret;
*val |= PCIE_BIT_L1;
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
if (ret != MACSUCCESS)
return ret;
PLTFM_MSG_WARN("[WARN] L1 enable & CLKREQ disable!\n");
}
*val |= PCIE_BIT_CLK;
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, *val);
return ret;
}
u32 update_aspmdly(struct mac_ax_adapter *adapter, u8 *val,
struct mac_ax_pcie_cfgspc_param *param,
struct mac_ax_pcie_cfgspc_param *param_def)
{
u8 l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;
u8 l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;
u8 l1updval = param->l1dly_ctrl;
u8 l0supdval = param->l0sdly_ctrl;
u8 l1defval = param_def->l1dly_ctrl;
u8 l0sdefval = param_def->l0sdly_ctrl;
u8 tmp;
u8 hwval;
if (l1updval != MAC_AX_PCIE_L1DLY_IGNORE) {
tmp = (l1updval == MAC_AX_PCIE_L1DLY_DEF) ? l1defval : l1updval;
switch (tmp) {
case MAC_AX_PCIE_L1DLY_16US:
hwval = PCIE_L1DLY_HW_16US;
break;
case MAC_AX_PCIE_L1DLY_32US:
hwval = PCIE_L1DLY_HW_32US;
break;
case MAC_AX_PCIE_L1DLY_64US:
hwval = PCIE_L1DLY_HW_64US;
break;
case MAC_AX_PCIE_L1DLY_INFI:
hwval = PCIE_L1DLY_HW_INFI;
break;
default:
PLTFM_MSG_ERR("[ERR]L1DLY wt val illegal!\n");
return MACSTCAL;
}
tmp = (hwval << SHFT_L1DLY) & l1mask;
*val = (*val & ~(l1mask)) | tmp;
}
if (l0supdval != MAC_AX_PCIE_L0SDLY_IGNORE) {
tmp = (l0supdval == MAC_AX_PCIE_L0SDLY_DEF) ?
l0sdefval : l0supdval;
switch (tmp) {
case MAC_AX_PCIE_L0SDLY_1US:
hwval = PCIE_L0SDLY_HW_1US;
break;
case MAC_AX_PCIE_L0SDLY_2US:
hwval = PCIE_L0SDLY_HW_2US;
break;
case MAC_AX_PCIE_L0SDLY_3US:
hwval = PCIE_L0SDLY_HW_3US;
break;
case MAC_AX_PCIE_L0SDLY_4US:
hwval = PCIE_L0SDLY_HW_4US;
break;
case MAC_AX_PCIE_L0SDLY_5US:
hwval = PCIE_L0SDLY_HW_5US;
break;
case MAC_AX_PCIE_L0SDLY_6US:
hwval = PCIE_L0SDLY_HW_6US;
break;
case MAC_AX_PCIE_L0SDLY_7US:
hwval = PCIE_L0SDLY_HW_7US;
break;
default:
PLTFM_MSG_ERR("[ERR]L0SDLY wt val illegal!\n");
return MACSTCAL;
}
tmp = (hwval << SHFT_L0SDLY) & l0smask;
*val = (*val & ~(l0smask)) | tmp;
}
return MACSUCCESS;
}
static u32 pcie_cfgspc_write(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_cfgspc_param *param)
{
u8 l1_val;
u8 aspm_val;
u8 l1ss_val;
u8 clk_val;
u8 tmp8;
struct mac_ax_pcie_cfgspc_param *param_def = &pcie_cfgspc_param_def;
u32 ret = MACSUCCESS;
u8 val8;
ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &l1_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_ASPM_CTRL, &aspm_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_L1SS_CTRL, &l1ss_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_CLK_CTRL, &clk_val);
if (ret != MACSUCCESS)
return ret;
if (l1_val == 0xFF || aspm_val == 0xFF || l1ss_val == 0xFF ||
clk_val == 0xFF) {
PLTFM_MSG_ERR("[ERR] PCIE CFG reg read 0xFF!\n");
return MACCMP;
}
ret = dbi_r8_pcie(adapter, PCIE_L1_STS, &tmp8);
if (ret != MACSUCCESS)
return ret;
if (((tmp8 & PCIE_BIT_STS_L0S) && param->l0s_ctrl ==
MAC_AX_PCIE_DEFAULT) || (param->l0s_ctrl != MAC_AX_PCIE_DEFAULT &&
param->l0s_ctrl != MAC_AX_PCIE_IGNORE))
update_pcie_func(&aspm_val, PCIE_BIT_L0S,
param->l0s_ctrl, param_def->l0s_ctrl);
if (((tmp8 & PCIE_BIT_STS_L1) && param->l1_ctrl ==
MAC_AX_PCIE_DEFAULT) || (param->l1_ctrl != MAC_AX_PCIE_DEFAULT &&
param->l1_ctrl != MAC_AX_PCIE_IGNORE))
update_pcie_func(&l1_val, PCIE_BIT_L1,
param->l1_ctrl, param_def->l1_ctrl);
update_pcie_func(&l1_val, PCIE_BIT_WAKE,
param->wake_ctrl, param_def->wake_ctrl);
update_pcie_func(&l1_val, PCIE_BIT_CLK,
param->crq_ctrl, param_def->crq_ctrl);
ret = chk_stus_l1ss(adapter, &val8);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] PCIE chk_stus_l1ss\n");
return ret;
}
if ((val8 && param->l1ss_ctrl == MAC_AX_PCIE_DEFAULT) ||
(param->l1ss_ctrl != MAC_AX_PCIE_DEFAULT &&
param->l1ss_ctrl != MAC_AX_PCIE_IGNORE))
update_pcie_func(&l1ss_val, PCIE_BIT_L1SS,
param->l1ss_ctrl, param_def->l1ss_ctrl);
ret = update_clkdly(adapter, &clk_val, param->clkdly_ctrl,
param_def->clkdly_ctrl);
if (ret != MACSUCCESS)
return ret;
ret = update_aspmdly(adapter, &aspm_val, param, param_def);
if (ret != MACSUCCESS)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (param->clkdly_ctrl != MAC_AX_PCIE_CLKDLY_IGNORE) {
ret = dbi_w8_pcie(adapter, PCIE_CLK_CTRL, clk_val);
if (ret != MACSUCCESS)
return ret;
}
if (param->crq_ctrl != MAC_AX_PCIE_IGNORE) {
ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &tmp8);
if (ret != MACSUCCESS)
return ret;
tmp8 = (tmp8 & PCIE_BIT_CLK) & l1_val;
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, l1_val);
if (ret != MACSUCCESS)
return ret;
}
}
if (param->l0s_ctrl != MAC_AX_PCIE_IGNORE ||
param->l1dly_ctrl != MAC_AX_PCIE_L1DLY_IGNORE ||
param->l0sdly_ctrl != MAC_AX_PCIE_L0SDLY_IGNORE) {
ret = dbi_w8_pcie(adapter, PCIE_ASPM_CTRL, aspm_val);
if (ret != MACSUCCESS)
return ret;
}
if (param->l1_ctrl != MAC_AX_PCIE_IGNORE ||
param->wake_ctrl != MAC_AX_PCIE_IGNORE) {
ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &tmp8);
if (ret != MACSUCCESS)
return ret;
tmp8 = (tmp8 & PCIE_BIT_L1 & PCIE_BIT_WAKE) & l1_val;
ret = dbi_w8_pcie(adapter, PCIE_L1_CTRL, l1_val);
if (ret != MACSUCCESS)
return ret;
}
if (param->l1ss_ctrl != MAC_AX_PCIE_IGNORE) {
ret = dbi_w8_pcie(adapter, PCIE_L1SS_CTRL, l1ss_val);
if (ret != MACSUCCESS)
return ret;
}
return ret;
}
u32 pcie_cfgspc_read(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_cfgspc_param *param)
{
u8 l1_val;
u8 aspm_val;
u8 l1ss_val;
u8 clk_val;
u8 l0smask;
u8 l1mask;
u32 ret;
ret = dbi_r8_pcie(adapter, PCIE_L1_CTRL, &l1_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_ASPM_CTRL, &aspm_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_L1SS_CTRL, &l1ss_val);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, PCIE_CLK_CTRL, &clk_val);
if (ret != MACSUCCESS)
return ret;
if (l1_val == 0xFF || aspm_val == 0xFF ||
l1ss_val == 0xFF || clk_val == 0xFF) {
PLTFM_MSG_ERR("[ERR] (2nd)PCIE CFG reg read 0xFF!\n");
return MACCMP;
}
param->l0s_ctrl = GET_PCIE_FUNC_STUS(aspm_val, PCIE_BIT_L0S);
param->l1_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_L1);
param->l1ss_ctrl = GET_PCIE_FUNC_STUS(l1ss_val, PCIE_BIT_L1SS);
param->wake_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_WAKE);
param->crq_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_CLK);
switch (clk_val) {
case PCIE_CLKDLY_HW_0:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_0;
break;
case PCIE_CLKDLY_HW_30US:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_30US;
break;
case PCIE_CLKDLY_HW_50US:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_50US;
break;
case PCIE_CLKDLY_HW_100US:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_100US;
break;
case PCIE_CLKDLY_HW_150US:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_150US;
break;
case PCIE_CLKDLY_HW_200US:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_200US;
break;
default:
param->clkdly_ctrl = MAC_AX_PCIE_CLKDLY_R_ERR;
break;
}
l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;
l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;
switch ((aspm_val & l0smask) >> SHFT_L0SDLY) {
case PCIE_L0SDLY_HW_1US:
param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_1US;
break;
case PCIE_L0SDLY_HW_3US:
param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_3US;
break;
case PCIE_L0SDLY_HW_5US:
param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_5US;
break;
case PCIE_L0SDLY_HW_7US:
param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_7US;
break;
default:
param->l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_R_ERR;
break;
}
switch ((aspm_val & l1mask) >> SHFT_L1DLY) {
case PCIE_L1DLY_HW_16US:
param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_16US;
break;
case PCIE_L1DLY_HW_32US:
param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_32US;
break;
case PCIE_L1DLY_HW_64US:
param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_64US;
break;
case PCIE_L1DLY_HW_INFI:
param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_INFI;
break;
default:
param->l1dly_ctrl = MAC_AX_PCIE_L1DLY_R_ERR;
break;
}
return ret;
}
u32 cfgspc_set_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_cfgspc_param *param)
{
u32 status = MACSUCCESS;
if (param->write == 1)
status = pcie_cfgspc_write(adapter, param);
if (param->read == 1)
status = pcie_cfgspc_read(adapter, param);
return status;
}
static u32 pcie_ltr_write(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_ltr_param *param)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ltr_ctrl0, ltr_ctrl1, ltr_idle_ltcy, ltr_act_ltcy;
u32 status = MACSUCCESS;
struct mac_ax_pcie_ltr_param *param_def = &pcie_ltr_param_def;
u32 val32;
enum mac_ax_pcie_func_ctrl ctrl;
ltr_ctrl0 = MAC_REG_R32(R_AX_LTR_CTRL_0);
ltr_ctrl1 = MAC_REG_R32(R_AX_LTR_CTRL_1);
ltr_idle_ltcy = MAC_REG_R32(R_AX_LTR_IDLE_LATENCY);
ltr_act_ltcy = MAC_REG_R32(R_AX_LTR_ACTIVE_LATENCY);
if (ltr_ctrl0 == MAC_AX_R32_FF || ltr_ctrl0 == MAC_AX_R32_EA ||
ltr_ctrl1 == MAC_AX_R32_FF || ltr_ctrl1 == MAC_AX_R32_EA ||
ltr_idle_ltcy == MAC_AX_R32_FF || ltr_idle_ltcy == MAC_AX_R32_EA ||
ltr_act_ltcy == MAC_AX_R32_FF || ltr_act_ltcy == MAC_AX_R32_EA) {
PLTFM_MSG_ERR("[ERR] LTR reg read nothing!\n");
return MACCMP;
}
if (!(param_def->ltr_ctrl == MAC_AX_PCIE_IGNORE ||
param->ltr_ctrl == MAC_AX_PCIE_IGNORE ||
param_def->ltr_ctrl == MAC_AX_PCIE_DEFAULT)) {
ctrl = param->ltr_ctrl == MAC_AX_PCIE_DEFAULT ?
param_def->ltr_ctrl : param->ltr_ctrl;
ltr_ctrl0 = ctrl == MAC_AX_PCIE_ENABLE ?
(ltr_ctrl0 | B_AX_LTR_EN) :
(ltr_ctrl0 & ~B_AX_LTR_EN);
}
if (!(param_def->ltr_hw_ctrl == MAC_AX_PCIE_IGNORE ||
param->ltr_hw_ctrl == MAC_AX_PCIE_IGNORE ||
param_def->ltr_hw_ctrl == MAC_AX_PCIE_DEFAULT)) {
ctrl = param->ltr_hw_ctrl == MAC_AX_PCIE_DEFAULT ?
param_def->ltr_hw_ctrl : param->ltr_hw_ctrl;
ltr_ctrl0 = ctrl == MAC_AX_PCIE_ENABLE ?
(ltr_ctrl0 | B_AX_LTR_HW_EN | B_AX_LTR_WD_NOEMP_CHK) :
(ltr_ctrl0 & ~(B_AX_LTR_HW_EN | B_AX_LTR_WD_NOEMP_CHK));
}
if (!(param_def->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_IGNORE ||
param->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_IGNORE ||
param_def->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_DEF)) {
val32 = param->ltr_spc_ctrl == MAC_AX_PCIE_LTR_SPC_DEF ?
param_def->ltr_spc_ctrl : param->ltr_spc_ctrl;
ltr_ctrl0 = SET_CLR_WORD(ltr_ctrl0, val32, B_AX_LTR_SPACE_IDX);
}
if (!(param_def->ltr_idle_timer_ctrl ==
MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE ||
param->ltr_idle_timer_ctrl ==
MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE ||
param_def->ltr_idle_timer_ctrl ==
MAC_AX_PCIE_LTR_IDLE_TIMER_DEF)) {
val32 = param->ltr_idle_timer_ctrl ==
MAC_AX_PCIE_LTR_IDLE_TIMER_DEF ?
param_def->ltr_idle_timer_ctrl :
param->ltr_idle_timer_ctrl;
ltr_ctrl0 = SET_CLR_WORD(ltr_ctrl0, val32,
B_AX_LTR_IDLE_TIMER_IDX);
}
if (!(param_def->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param_def->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
val32 = param->ltr_rx0_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
param_def->ltr_rx0_th_ctrl.val :
param->ltr_rx0_th_ctrl.val;
ltr_ctrl1 = SET_CLR_WORD(ltr_ctrl1, val32, B_AX_LTR_RX0_TH);
}
if (!(param_def->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param_def->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
val32 = param->ltr_rx1_th_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
param_def->ltr_rx1_th_ctrl.val :
param->ltr_rx1_th_ctrl.val;
ltr_ctrl1 = SET_CLR_WORD(ltr_ctrl1, val32, B_AX_LTR_RX1_TH);
}
if (!(param_def->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param_def->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
val32 = param->ltr_idle_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
param_def->ltr_idle_lat_ctrl.val :
param->ltr_idle_lat_ctrl.val;
ltr_idle_ltcy =
SET_CLR_WORD(ltr_idle_ltcy, val32, B_AX_LTR_IDLE_LTCY);
}
if (!(param_def->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_IGNORE ||
param_def->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT)) {
val32 = param->ltr_act_lat_ctrl.ctrl == MAC_AX_PCIE_DEFAULT ?
param_def->ltr_act_lat_ctrl.val :
param->ltr_act_lat_ctrl.val;
ltr_act_ltcy =
SET_CLR_WORD(ltr_act_ltcy, val32, B_AX_LTR_ACT_LTCY);
}
MAC_REG_W32(R_AX_LTR_CTRL_0, ltr_ctrl0);
MAC_REG_W32(R_AX_LTR_CTRL_1, ltr_ctrl1);
MAC_REG_W32(R_AX_LTR_IDLE_LATENCY, ltr_idle_ltcy);
MAC_REG_W32(R_AX_LTR_ACTIVE_LATENCY, ltr_act_ltcy);
return status;
}
static u32 pcie_ltr_read(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_ltr_param *param)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 status = MACSUCCESS;
u32 ltr_ctrl0, ltr_ctrl1, ltr_idle_ltcy, ltr_act_ltcy;
ltr_ctrl0 = MAC_REG_R32(R_AX_LTR_CTRL_0);
ltr_ctrl1 = MAC_REG_R32(R_AX_LTR_CTRL_1);
ltr_idle_ltcy = MAC_REG_R32(R_AX_LTR_IDLE_LATENCY);
ltr_act_ltcy = MAC_REG_R32(R_AX_LTR_ACTIVE_LATENCY);
if (ltr_ctrl0 == MAC_AX_R32_FF || ltr_ctrl0 == MAC_AX_R32_EA ||
ltr_ctrl1 == MAC_AX_R32_FF || ltr_ctrl1 == MAC_AX_R32_EA ||
ltr_idle_ltcy == MAC_AX_R32_FF || ltr_idle_ltcy == MAC_AX_R32_EA ||
ltr_act_ltcy == MAC_AX_R32_FF || ltr_act_ltcy == MAC_AX_R32_EA) {
PLTFM_MSG_ERR("[ERR] LTR reg read nothing!\n");
return MACCMP;
}
param->ltr_ctrl = ltr_ctrl0 & B_AX_LTR_EN ?
MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
param->ltr_hw_ctrl = ltr_ctrl0 & B_AX_LTR_HW_EN ?
MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
param->ltr_spc_ctrl =
(enum mac_ax_pcie_ltr_spc)
GET_FIELD(ltr_ctrl0, B_AX_LTR_SPACE_IDX);
param->ltr_idle_timer_ctrl =
(enum mac_ax_pcie_ltr_idle_timer)
GET_FIELD(ltr_ctrl0, B_AX_LTR_IDLE_TIMER_IDX);
param->ltr_rx0_th_ctrl.val =
(u16)GET_FIELD(ltr_ctrl1, B_AX_LTR_RX0_TH);
param->ltr_rx1_th_ctrl.val =
(u16)GET_FIELD(ltr_ctrl1, B_AX_LTR_RX1_TH);
param->ltr_idle_lat_ctrl.val =
GET_FIELD(ltr_idle_ltcy, B_AX_LTR_IDLE_LTCY);
param->ltr_act_lat_ctrl.val =
GET_FIELD(ltr_act_ltcy, B_AX_LTR_ACT_LTCY);
return status;
}
u32 ltr_set_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_ltr_param *param)
{
u32 ret = MACSUCCESS;
if (param->write) {
ret = pcie_ltr_write(adapter, param);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie ltr write fail %d\n", ret);
return ret;
}
}
if (param->read) {
ret = pcie_ltr_read(adapter, param);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie ltr read fail %d\n", ret);
return ret;
}
}
return ret;
}
u32 ltr_sw_trigger(struct mac_ax_adapter *adapter,
enum mac_ax_pcie_ltr_sw_ctrl ctrl)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_LTR_CTRL_0);
if (val32 & B_AX_LTR_HW_EN) {
PLTFM_MSG_ERR("[ERR]LTR HW mode running\n");
return MACPROCERR;
} else if (!(val32 & B_AX_LTR_EN)) {
PLTFM_MSG_ERR("[ERR]LTR not enable\n");
return MACHWNOTEN;
}
switch (ctrl) {
case MAC_AX_PCIE_LTR_SW_ACT:
MAC_REG_W32(R_AX_LTR_CTRL_0, val32 | B_AX_APP_LTR_ACT);
break;
case MAC_AX_PCIE_LTR_SW_IDLE:
MAC_REG_W32(R_AX_LTR_CTRL_0, val32 | B_AX_APP_LTR_IDLE);
break;
default:
PLTFM_MSG_ERR("Invalid input for %s\n", __func__);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 pcie_set_sic(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACSUCCESS;
MAC_REG_W32(R_AX_PCIE_EXP_CTRL, MAC_REG_R32(R_AX_PCIE_EXP_CTRL) &
~B_AX_SIC_EN_FORCE_CLKREQ);
return MACSUCCESS;
}
static u32 pcie_set_lbc(struct mac_ax_adapter *adapter,
enum mac_ax_pcie_func_ctrl ctrl,
enum mac_ax_lbc_tmr tmr)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_intf_info *intf_info_def;
u32 val32;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
intf_info_def = &intf_info_def_8852a;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
intf_info_def = &intf_info_def_8852b;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
intf_info_def = &intf_info_def_8852c;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
intf_info_def = &intf_info_def_8192xb;
} else {
PLTFM_MSG_ERR("Chip ID is undefined\n");
return MACCHIPID;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(R_AX_LBC_WATCHDOG);
if (ctrl == MAC_AX_PCIE_ENABLE ||
(ctrl == MAC_AX_PCIE_DEFAULT &&
intf_info_def->lbc_en == MAC_AX_PCIE_ENABLE)) {
val32 = SET_CLR_WORD(val32, tmr == MAC_AX_LBC_TMR_DEF ?
intf_info_def->lbc_tmr : tmr,
B_AX_LBC_TIMER);
val32 |= B_AX_LBC_FLAG | B_AX_LBC_EN;
} else {
val32 &= ~B_AX_LBC_EN;
}
MAC_REG_W32(R_AX_LBC_WATCHDOG, val32);
}
return MACSUCCESS;
}
static u32 pcie_set_dbg(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACSUCCESS;
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, MAC_REG_R32(R_AX_PCIE_DBG_CTRL) |
B_AX_ASFF_FULL_NO_STK |
B_AX_EN_STUCK_DBG);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
MAC_REG_W32(R_AX_PCIE_EXP_CTRL,
MAC_REG_R32(R_AX_PCIE_EXP_CTRL) |
B_AX_EN_CHKDSC_NO_RX_STUCK);
return MACSUCCESS;
}
static u32 pcie_set_keep_reg(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, MAC_REG_R32(R_AX_PCIE_INIT_CFG1) |
B_AX_PCIE_TXRST_KEEP_REG |
B_AX_PCIE_RXRST_KEEP_REG);
return MACSUCCESS;
}
static u32 pcie_set_io_rcy(struct mac_ax_adapter *adapter,
enum mac_ax_pcie_func_ctrl ctrl,
enum mac_ax_io_rcy_tmr tmr)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_intf_info *intf_info_def;
u32 val32;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
intf_info_def = &intf_info_def_8852a;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
intf_info_def = &intf_info_def_8852b;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
intf_info_def = &intf_info_def_8852c;
} else {
PLTFM_MSG_ERR("Chip ID is undefined\n");
return MACCHIPID;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
val32 = 0;
if (ctrl == MAC_AX_PCIE_ENABLE ||
(ctrl == MAC_AX_PCIE_DEFAULT &&
intf_info_def->io_rcy_en == MAC_AX_PCIE_ENABLE)) {
val32 = SET_CLR_WORD(val32,
tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?
intf_info_def->io_rcy_tmr : tmr,
B_AX_PCIE_WDT_TIMER_M1);
MAC_REG_W32(R_AX_PCIE_WDT_TIMER_M1, val32);
MAC_REG_W32(R_AX_PCIE_WDT_TIMER_M2, val32);
MAC_REG_W32(R_AX_PCIE_WDT_TIMER_E0, val32);
MAC_REG_W32(R_AX_PCIE_WDT_TIMER_S1, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M1);
val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_M1;
MAC_REG_W32(R_AX_PCIE_IO_RCY_M1, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M2);
val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_M2;
MAC_REG_W32(R_AX_PCIE_IO_RCY_M2, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_E0);
val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_E0;
MAC_REG_W32(R_AX_PCIE_IO_RCY_E0, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_S1);
val32 |= B_AX_PCIE_IO_RCY_WDT_MODE_S1;
MAC_REG_W32(R_AX_PCIE_IO_RCY_S1, val32);
} else {
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M1);
val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_M1;
MAC_REG_W32(R_AX_PCIE_IO_RCY_M1, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_M2);
val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_M2;
MAC_REG_W32(R_AX_PCIE_IO_RCY_M2, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_E0);
val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_E0;
MAC_REG_W32(R_AX_PCIE_IO_RCY_E0, val32);
val32 = MAC_REG_R32(R_AX_PCIE_IO_RCY_S1);
val32 &= ~B_AX_PCIE_IO_RCY_WDT_MODE_S1;
MAC_REG_W32(R_AX_PCIE_IO_RCY_S1, val32);
}
}
return MACSUCCESS;
}
static void ctrl_hci_dma_en_pcie(struct mac_ax_adapter *adapter,
enum mac_ax_func_sw en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (en == MAC_AX_FUNC_EN)
MAC_REG_W32(R_AX_HCI_FUNC_EN,
MAC_REG_R32(R_AX_HCI_FUNC_EN) | B_AX_HCI_TXDMA_EN |
B_AX_HCI_RXDMA_EN);
else
MAC_REG_W32(R_AX_HCI_FUNC_EN,
MAC_REG_R32(R_AX_HCI_FUNC_EN) &
~(B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN));
}
static u32 poll_io_idle_pcie(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 cnt;
cnt = PCIE_POLL_IO_IDLE_CNT;
val32 = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY;
while (cnt && (MAC_REG_R32(R_AX_PCIE_DMA_BUSY1) & val32)) {
cnt--;
PLTFM_DELAY_US(PCIE_POLL_IO_IDLE_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]PCIE dmach busy1 0x%X\n",
MAC_REG_R32(R_AX_PCIE_DMA_BUSY1));
return MACPOLLTO;
}
return MACSUCCESS;
}
static u32 get_txbd_desc_reg(struct mac_ax_adapter *adapter, u8 dma_ch,
u32 *addr_l, u32 *addr_h)
{
u8 c_id = adapter->hw_info->chip_id;
if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
(dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
PLTFM_MSG_ERR("[ERR] TXBD desc CH%d not support in 8852B\n",
dma_ch);
return MACHWNOSUP;
}
switch (dma_ch) {
case MAC_AX_DMA_ACH0:
*addr_l = ach0_txbd_desa_l_reg[c_id];
*addr_h = ach0_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH1:
*addr_l = ach1_txbd_desa_l_reg[c_id];
*addr_h = ach1_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH2:
*addr_l = ach2_txbd_desa_l_reg[c_id];
*addr_h = ach2_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH3:
*addr_l = ach3_txbd_desa_l_reg[c_id];
*addr_h = ach3_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH4:
*addr_l = ach4_txbd_desa_l_reg[c_id];
*addr_h = ach4_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH5:
*addr_l = ach5_txbd_desa_l_reg[c_id];
*addr_h = ach5_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH6:
*addr_l = ach6_txbd_desa_l_reg[c_id];
*addr_h = ach6_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_ACH7:
*addr_l = ach7_txbd_desa_l_reg[c_id];
*addr_h = ach7_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_B0MG:
*addr_l = ch8_txbd_desa_l_reg[c_id];
*addr_h = ch8_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_B0HI:
*addr_l = ch9_txbd_desa_l_reg[c_id];
*addr_h = ch9_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_B1MG:
*addr_l = ch10_txbd_desa_l_reg[c_id];
*addr_h = ch10_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_B1HI:
*addr_l = ch11_txbd_desa_l_reg[c_id];
*addr_h = ch11_txbd_desa_h_reg[c_id];
break;
case MAC_AX_DMA_H2C:
*addr_l = ch12_txbd_desa_l_reg[c_id];
*addr_h = ch12_txbd_desa_h_reg[c_id];
break;
default:
PLTFM_MSG_ERR("[ERR] TXBD desc CH%d invalid\n", dma_ch);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 get_rxbd_desc_reg(struct mac_ax_adapter *adapter, u8 dma_ch,
u32 *addr_l, u32 *addr_h)
{
u8 c_id = adapter->hw_info->chip_id;
switch (dma_ch) {
case MAC_AX_RX_CH_RXQ:
*addr_l = rxq_rxbd_desa_l_reg[c_id];
*addr_h = rxq_rxbd_desa_h_reg[c_id];
break;
case MAC_AX_RX_CH_RPQ:
*addr_l = rpq_rxbd_desa_l_reg[c_id];
*addr_h = rpq_rxbd_desa_h_reg[c_id];
break;
default:
PLTFM_MSG_ERR("[ERR] RXBD desc CH%d invalid\n", dma_ch);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 get_txbd_num_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
{
u8 c_id = adapter->hw_info->chip_id;
if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
(dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
PLTFM_MSG_ERR("[ERR] TXBD num CH%d not support in 8852B\n",
dma_ch);
return MACHWNOSUP;
}
switch (dma_ch) {
case MAC_AX_DMA_ACH0:
*reg = R_AX_ACH0_TXBD_NUM;
break;
case MAC_AX_DMA_ACH1:
*reg = R_AX_ACH1_TXBD_NUM;
break;
case MAC_AX_DMA_ACH2:
*reg = R_AX_ACH2_TXBD_NUM;
break;
case MAC_AX_DMA_ACH3:
*reg = R_AX_ACH3_TXBD_NUM;
break;
case MAC_AX_DMA_ACH4:
*reg = R_AX_ACH4_TXBD_NUM;
break;
case MAC_AX_DMA_ACH5:
*reg = R_AX_ACH5_TXBD_NUM;
break;
case MAC_AX_DMA_ACH6:
*reg = R_AX_ACH6_TXBD_NUM;
break;
case MAC_AX_DMA_ACH7:
*reg = R_AX_ACH7_TXBD_NUM;
break;
case MAC_AX_DMA_B0MG:
*reg = R_AX_CH8_TXBD_NUM;
break;
case MAC_AX_DMA_B0HI:
*reg = R_AX_CH9_TXBD_NUM;
break;
case MAC_AX_DMA_B1MG:
*reg = ch10_txbd_num_reg[c_id];
break;
case MAC_AX_DMA_B1HI:
*reg = ch11_txbd_num_reg[c_id];
break;
case MAC_AX_DMA_H2C:
*reg = R_AX_CH12_TXBD_NUM;
break;
default:
PLTFM_MSG_ERR("[ERR] TXBD num CH%d invalid\n", dma_ch);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 get_rxbd_num_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
{
u8 c_id = adapter->hw_info->chip_id;
switch (dma_ch) {
case MAC_AX_RX_CH_RXQ:
*reg = rxq_rxbd_num_reg[c_id];
break;
case MAC_AX_RX_CH_RPQ:
*reg = rpq_rxbd_num_reg[c_id];
break;
default:
PLTFM_MSG_ERR("[ERR] RXBD num CH%d invalid\n", dma_ch);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 get_txbd_ram_reg(struct mac_ax_adapter *adapter, u8 dma_ch, u32 *reg)
{
u8 c_id = adapter->hw_info->chip_id;
if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
((dma_ch >= MAC_AX_DMA_ACH4 && dma_ch <= MAC_AX_DMA_ACH7) ||
(dma_ch >= MAC_AX_DMA_B1MG && dma_ch <= MAC_AX_DMA_B1HI))) {
PLTFM_MSG_ERR("[ERR] TXBD ram CH%d not support in 8852B\n",
dma_ch);
return MACHWNOSUP;
}
switch (dma_ch) {
case MAC_AX_DMA_ACH0:
*reg = ach0_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH1:
*reg = ach1_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH2:
*reg = ach2_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH3:
*reg = ach3_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH4:
*reg = ach4_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH5:
*reg = ach5_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH6:
*reg = ach6_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_ACH7:
*reg = ach7_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_B0MG:
*reg = ch8_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_B0HI:
*reg = ch9_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_B1MG:
*reg = ch10_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_B1HI:
*reg = ch11_bdram_ctrl_reg[c_id];
break;
case MAC_AX_DMA_H2C:
*reg = ch12_bdram_ctrl_reg[c_id];
break;
default:
PLTFM_MSG_ERR("[ERR] TXBD ram CH%d invalid\n", dma_ch);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 mode_op(struct mac_ax_adapter *adapter,
struct mac_ax_intf_info *intf_info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 c_id = adapter->hw_info->chip_id;
u32 val32;
struct tx_base_desc *txbd = (struct tx_base_desc *)intf_info->txbd_buf;
struct rx_base_desc *rxbd = (struct rx_base_desc *)intf_info->rxbd_buf;
enum mac_ax_bd_trunc_mode *txbd_trunc_mode =
(&intf_info->txbd_trunc_mode);
enum mac_ax_bd_trunc_mode *rxbd_trunc_mode =
(&intf_info->rxbd_trunc_mode);
enum mac_ax_rxbd_mode *rxbd_mode = (&intf_info->rxbd_mode);
enum mac_ax_tag_mode *tag_mode = (&intf_info->tag_mode);
enum mac_ax_multi_tag_num *multi_tag_num = (&intf_info->multi_tag_num);
enum mac_ax_wd_dma_intvl *wd_dma_idle_intvl =
(&intf_info->wd_dma_idle_intvl);
enum mac_ax_wd_dma_intvl *wd_dma_act_intvl =
(&intf_info->wd_dma_act_intvl);
enum mac_ax_tx_burst *tx_burst = &intf_info->tx_burst;
enum mac_ax_rx_burst *rx_burst = &intf_info->rx_burst;
struct mac_ax_intf_info *intf_info_def;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
intf_info_def = &intf_info_def_8852a;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
intf_info_def = &intf_info_def_8852b;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
intf_info_def = &intf_info_def_8852c;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
intf_info_def = &intf_info_def_8192xb;
} else {
PLTFM_MSG_ERR("Chip ID is undefined\n");
return MACCHIPID;
}
if (intf_info->txbd_trunc_mode == MAC_AX_BD_DEF)
txbd_trunc_mode = (&intf_info_def->txbd_trunc_mode);
if (intf_info->rxbd_trunc_mode == MAC_AX_BD_DEF)
rxbd_trunc_mode = (&intf_info_def->rxbd_trunc_mode);
if ((*txbd_trunc_mode) == MAC_AX_BD_TRUNC) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
is_cv(adapter, CBV)) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_TX_TRUNC_MODE;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
MAC_REG_W32(R_AX_TXDMA_ADDR_H, txbd->phy_addr_h);
}
} else if ((*txbd_trunc_mode) == MAC_AX_BD_NORM) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_TX_TRUNC_MODE;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
}
}
if ((*rxbd_trunc_mode) == MAC_AX_BD_TRUNC) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
is_cv(adapter, CBV)) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_RX_TRUNC_MODE;
PLTFM_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
PLTFM_REG_W32(R_AX_RXDMA_ADDR_H, rxbd->phy_addr_h);
}
} else if ((*rxbd_trunc_mode) == MAC_AX_BD_NORM) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_RX_TRUNC_MODE;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
}
}
if (intf_info->rxbd_mode == MAC_AX_RXBD_DEF)
rxbd_mode = (&intf_info_def->rxbd_mode);
if ((*rxbd_mode) == MAC_AX_RXBD_PKT) {
val32 = MAC_REG_R32(init_cfg_reg[c_id]) & ~rxbd_mode_bit[c_id];
MAC_REG_W32(init_cfg_reg[c_id], val32);
} else if ((*rxbd_mode) == MAC_AX_RXBD_SEP) {
val32 = MAC_REG_R32(init_cfg_reg[c_id]) | rxbd_mode_bit[c_id];
MAC_REG_W32(init_cfg_reg[c_id], val32);
if (intf_info->rx_sep_append_len > 0x3FFF) {
PLTFM_MSG_ERR("rx sep app len %d\n",
intf_info->rx_sep_append_len);
return MACFUNCINPUT;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG2);
val32 = SET_CLR_WORD(val32, intf_info->rx_sep_append_len,
B_AX_PCIE_RX_APPLEN);
MAC_REG_W32(R_AX_PCIE_INIT_CFG2, val32);
}
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (intf_info->tx_burst == MAC_AX_TX_BURST_DEF)
tx_burst = &intf_info_def->tx_burst;
if (intf_info->rx_burst == MAC_AX_RX_BURST_DEF)
rx_burst = &intf_info_def->rx_burst;
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
val32 = SET_CLR_WORD(val32, *tx_burst, B_AX_PCIE_MAX_TXDMA);
val32 = SET_CLR_WORD(val32, *rx_burst, B_AX_PCIE_MAX_RXDMA);
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
if (intf_info->tx_burst == MAC_AX_TX_BURST_DEF)
tx_burst = &intf_info_def->tx_burst;
if (intf_info->rx_burst == MAC_AX_RX_BURST_DEF)
rx_burst = &intf_info_def->rx_burst;
val32 = MAC_REG_R32(R_AX_HAXI_INIT_CFG1);
val32 = SET_CLR_WORD(val32, *tx_burst, B_AX_HAXI_MAX_TXDMA);
val32 = SET_CLR_WORD(val32, *rx_burst, B_AX_HAXI_MAX_RXDMA);
MAC_REG_W32(R_AX_HAXI_INIT_CFG1, val32);
} else {
PLTFM_MSG_ERR("Chip ID is undefined\n");
return MACCHIPID;
}
if (intf_info->tag_mode == MAC_AX_TAG_DEF)
tag_mode = (&intf_info_def->tag_mode);
if (intf_info->multi_tag_num == MAC_AX_TAG_NUM_DEF)
multi_tag_num = (&intf_info_def->multi_tag_num);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if ((*tag_mode) == MAC_AX_TAG_SGL) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) &
~B_AX_LATENCY_CONTROL;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
} else if ((*tag_mode) == MAC_AX_TAG_MULTI) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1) |
B_AX_LATENCY_CONTROL;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
}
}
val32 = MAC_REG_R32(exp_ctrl_reg[c_id]);
val32 = SET_CLR_WOR2(val32, *multi_tag_num, max_tag_num_sh[c_id],
max_tag_num_msk[c_id]);
MAC_REG_W32(exp_ctrl_reg[c_id], val32);
if (intf_info->wd_dma_act_intvl == MAC_AX_WD_DMA_INTVL_DEF)
wd_dma_act_intvl = (&intf_info_def->wd_dma_act_intvl);
if (intf_info->wd_dma_idle_intvl == MAC_AX_WD_DMA_INTVL_DEF)
wd_dma_idle_intvl = (&intf_info_def->wd_dma_idle_intvl);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG2);
val32 = SET_CLR_WORD(val32, *wd_dma_idle_intvl,
B_AX_WD_ITVL_IDLE);
val32 = SET_CLR_WORD(val32, *wd_dma_act_intvl,
B_AX_WD_ITVL_ACT);
MAC_REG_W32(R_AX_PCIE_INIT_CFG2, val32);
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = MAC_REG_R32(R_AX_HAXI_INIT_CFG1);
val32 = SET_CLR_WORD(val32, *wd_dma_idle_intvl,
B_AX_WD_ITVL_IDLE_V1);
val32 = SET_CLR_WORD(val32, *wd_dma_act_intvl,
B_AX_WD_ITVL_ACT_V1);
MAC_REG_W32(R_AX_HAXI_INIT_CFG1, val32);
} else {
PLTFM_MSG_ERR("Chip ID is undefined\n");
return MACCHIPID;
}
return MACSUCCESS;
}
static u32 trx_init_bd(struct mac_ax_adapter *adapter,
struct mac_ax_intf_info *intf_info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct tx_base_desc *txbd = (struct tx_base_desc *)intf_info->txbd_buf;
struct rx_base_desc *rxbd = (struct rx_base_desc *)intf_info->rxbd_buf;
enum mac_ax_bd_trunc_mode *txbd_trunc_mode =
(&intf_info->txbd_trunc_mode);
enum mac_ax_bd_trunc_mode *rxbd_trunc_mode =
(&intf_info->rxbd_trunc_mode);
enum mac_ax_rxbd_mode *rxbd_mode = (&intf_info->rxbd_mode);
struct txbd_ram *bdram_tbl;
struct mac_ax_intf_info *intf_info_def;
u32 reg_addr_l, reg_addr_h, reg32, val32, bd_num;
u16 val16;
u8 ch, bdram_idx;
u32 ret = MACSUCCESS;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
bdram_tbl = mac_bdram_tbl_8852a;
intf_info_def = &intf_info_def_8852a;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
bdram_tbl = mac_bdram_tbl_8852b;
intf_info_def = &intf_info_def_8852b;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
bdram_tbl = mac_bdram_tbl_8852c;
intf_info_def = &intf_info_def_8852c;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
bdram_tbl = mac_bdram_tbl_8192xb;
intf_info_def = &intf_info_def_8192xb;
} else {
PLTFM_MSG_ERR("Chip ID is undefined\n");
return MACCHIPID;
}
if (intf_info->txbd_trunc_mode == MAC_AX_BD_DEF)
txbd_trunc_mode = (&intf_info_def->txbd_trunc_mode);
if (intf_info->rxbd_trunc_mode == MAC_AX_BD_DEF)
rxbd_trunc_mode = (&intf_info_def->rxbd_trunc_mode);
if (intf_info->rxbd_mode == MAC_AX_RXBD_DEF)
rxbd_mode = (&intf_info_def->rxbd_mode);
if (*txbd_trunc_mode == MAC_AX_BD_TRUNC) {
val32 = MAC_REG_R32(R_AX_TX_ADDRESS_INFO_MODE_SETTING) |
B_AX_HOST_ADDR_INFO_8B_SEL;
MAC_REG_W32(R_AX_TX_ADDRESS_INFO_MODE_SETTING, val32);
val32 = MAC_REG_R32(R_AX_PKTIN_SETTING) &
~B_AX_WD_ADDR_INFO_LENGTH;
MAC_REG_W32(R_AX_PKTIN_SETTING, val32);
} else if (*txbd_trunc_mode == MAC_AX_BD_NORM) {
val32 = MAC_REG_R32(R_AX_TX_ADDRESS_INFO_MODE_SETTING) &
~B_AX_HOST_ADDR_INFO_8B_SEL;
MAC_REG_W32(R_AX_TX_ADDRESS_INFO_MODE_SETTING, val32);
val32 = MAC_REG_R32(R_AX_PKTIN_SETTING) |
B_AX_WD_ADDR_INFO_LENGTH;
MAC_REG_W32(R_AX_PKTIN_SETTING, val32);
} else {
PLTFM_MSG_ERR("pcie init txbd_trunc_mode %d illegal\n",
intf_info->txbd_trunc_mode);
return MACFUNCINPUT;
}
bdram_idx = 0;
for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_CH_NUM; ch++) {
if ((is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) &&
((ch >= MAC_AX_DMA_ACH4 && ch <= MAC_AX_DMA_ACH7) ||
(ch >= MAC_AX_DMA_B1MG && ch <= MAC_AX_DMA_B1HI)))
continue;
if (txbd[ch].phy_addr_l % TXBD_BYTE_ALIGN) {
PLTFM_MSG_ERR("[ERR]ch%d txbd phyaddr 0x%X not %dB align\n",
ch, txbd[ch].phy_addr_l, TXBD_BYTE_ALIGN);
return MACBADDR;
}
ret = get_txbd_desc_reg(adapter, ch, ®_addr_l, ®_addr_h);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get_txbd_desc_reg\n");
return ret;
}
MAC_REG_W32(reg_addr_l, txbd[ch].phy_addr_l);
MAC_REG_W32(reg_addr_h, txbd[ch].phy_addr_h);
bd_num = (*txbd_trunc_mode == MAC_AX_BD_TRUNC) ?
(txbd[ch].buf_len / BD_TRUNC_SIZE) :
(txbd[ch].buf_len / BD_NORM_SIZE);
if (bd_num > BD_MAX_NUM) {
PLTFM_MSG_ERR("ch%d txbd num %d\n", ch, bd_num);
return MACFUNCINPUT;
}
ret = get_txbd_num_reg(adapter, ch, ®32);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get_txbd_num_reg\n");
return ret;
}
val16 = SET_CLR_WORD(MAC_REG_R16(reg32), bd_num,
B_AX_ACH0_DESC_NUM);
MAC_REG_W16(reg32, val16);
ret = get_txbd_ram_reg(adapter, ch, ®32);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get_txbd_ram_reg\n");
return ret;
}
val32 = MAC_REG_R32(reg32);
val32 = SET_CLR_WORD(val32, bdram_tbl[bdram_idx].sidx,
B_AX_ACH0_BDRAM_SIDX);
val32 = SET_CLR_WORD(val32, bdram_tbl[bdram_idx].max,
B_AX_ACH0_BDRAM_MAX);
val32 = SET_CLR_WORD(val32, bdram_tbl[bdram_idx].min,
B_AX_ACH0_BDRAM_MIN);
MAC_REG_W32(reg32, val32);
bdram_idx++;
}
for (ch = MAC_AX_RX_CH_RXQ; ch < MAC_AX_RX_CH_NUM; ch++) {
if (rxbd[ch].phy_addr_l % RXBD_BYTE_ALIGN) {
PLTFM_MSG_ERR("[ERR]ch%d rxbd phyaddr 0x%X not %dB align\n",
ch, rxbd[ch].phy_addr_l, RXBD_BYTE_ALIGN);
return MACBADDR;
}
ret = get_rxbd_desc_reg(adapter, ch, ®_addr_l, ®_addr_h);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get_rxbd_desc_reg\n");
return ret;
}
MAC_REG_W32(reg_addr_l, rxbd[ch].phy_addr_l);
MAC_REG_W32(reg_addr_h, rxbd[ch].phy_addr_h);
ret = get_rxbd_num_reg(adapter, ch, ®32);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get_rxbd_num_reg\n");
return ret;
}
if (ch == MAC_AX_RX_CH_RXQ) {
bd_num = (*rxbd_mode == MAC_AX_RXBD_PKT) ?
(rxbd[ch].buf_len / BD_TRUNC_SIZE) :
(rxbd[ch].buf_len / RXBD_SEP_TRUNC_NEW_SIZE);
} else {
bd_num = (*rxbd_trunc_mode == MAC_AX_BD_TRUNC) ?
(rxbd[ch].buf_len / BD_TRUNC_SIZE) :
(rxbd[ch].buf_len / BD_NORM_SIZE);
}
if (bd_num > BD_MAX_NUM) {
PLTFM_MSG_ERR("ch%d rxbd num %d\n", ch, bd_num);
return MACFUNCINPUT;
}
val16 = SET_CLR_WORD(MAC_REG_R16(reg32), bd_num,
B_AX_RXQ_DESC_NUM);
MAC_REG_W16(reg32, val16);
}
return MACSUCCESS;
}
static u32 _patch_pcie_power_wake(struct mac_ax_adapter *adapter, u8 pwr_state)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (pwr_state == PC_POWER_UP) {
MAC_REG_W32(R_AX_HCI_OPT_CTRL, MAC_REG_R32(R_AX_HCI_OPT_CTRL)
| BIT_WAKE_CTRL);
} else if (pwr_state == PC_POWER_DOWN) {
MAC_REG_W32(R_AX_HCI_OPT_CTRL, MAC_REG_R32(R_AX_HCI_OPT_CTRL)
& ~BIT_WAKE_CTRL);
} else {
PLTFM_MSG_ERR("[ERR] patch power wake input: %d\n", pwr_state);
return MACFUNCINPUT;
}
return MACSUCCESS;
}
static u32 _patch_pcie_refclk_autok(struct mac_ax_adapter *adapter,
struct mac_ax_intf_info *intf_info)
{
u32 ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV))
return MACSUCCESS;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
return MACSUCCESS;
} else {
//cut_ver_checker
}
if (intf_info->autok_en == MAC_AX_PCIE_DEFAULT)
intf_info->autok_en = MAC_AX_PCIE_DISABLE;
if (intf_info->autok_en != MAC_AX_PCIE_IGNORE) {
ret = mac_auto_refclk_cal_pcie(adapter, intf_info->autok_en);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] pcie autok fail %d\n", ret);
return ret;
}
}
return MACSUCCESS;
}
static u32 _patch_pcie_deglitch(struct mac_ax_adapter *adapter)
{
u32 ret;
u16 val16, bit_set;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACSUCCESS;
bit_set = BIT11 | BIT10 | BIT9 | BIT8;
ret = mdio_r16_pcie(adapter, RAC_ANA24, MAC_AX_PCIE_PHY_GEN1, &val16);
if (ret != MACSUCCESS)
return ret;
val16 &= ~bit_set;
ret = mdio_w16_pcie(adapter, RAC_ANA24, val16, MAC_AX_PCIE_PHY_GEN1);
if (ret != MACSUCCESS)
return ret;
ret = mdio_r16_pcie(adapter, RAC_ANA24, MAC_AX_PCIE_PHY_GEN2, &val16);
if (ret != MACSUCCESS)
return ret;
val16 &= ~bit_set;
ret = mdio_w16_pcie(adapter, RAC_ANA24, val16, MAC_AX_PCIE_PHY_GEN2);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
static u32 _patch_pcie_l2_rxen_lat(struct mac_ax_adapter *adapter)
{
u32 ret;
u16 val16, bit_set;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACSUCCESS;
bit_set = BIT15 | BIT14;
ret = mdio_r16_pcie(adapter, RAC_ANA26, MAC_AX_PCIE_PHY_GEN1, &val16);
if (ret != MACSUCCESS)
return ret;
val16 &= ~bit_set;
ret = mdio_w16_pcie(adapter, RAC_ANA26, val16, MAC_AX_PCIE_PHY_GEN1);
if (ret != MACSUCCESS)
return ret;
ret = mdio_r16_pcie(adapter, RAC_ANA26, MAC_AX_PCIE_PHY_GEN2, &val16);
if (ret != MACSUCCESS)
return ret;
val16 &= ~bit_set;
ret = mdio_w16_pcie(adapter, RAC_ANA26, val16, MAC_AX_PCIE_PHY_GEN2);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
static u32 _patch_pcie_l1off_pwroff(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACSUCCESS;
MAC_REG_W32(R_AX_PCIE_PS_CTRL,
MAC_REG_R32(R_AX_PCIE_PS_CTRL) & ~B_AX_L1OFF_PWR_OFF_EN);
return MACSUCCESS;
}
static u32 _patch_pcie_aphy_pwrcut(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
return MACSUCCESS;
MAC_REG_W32(R_AX_SYS_PW_CTRL,
MAC_REG_R32(R_AX_SYS_PW_CTRL) & ~B_AX_PSUS_OFF_CAPC_EN);
return MACSUCCESS;
}
static u32 _patch_pcie_hci_ldo(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
return MACSUCCESS;
val32 = MAC_REG_R32(R_AX_SYS_SDIO_CTRL);
val32 |= B_AX_PCIE_DIS_L2_CTRL_LDO_HCI;
val32 &= ~B_AX_PCIE_DIS_WLSUS_AFT_PDN;
MAC_REG_W32(R_AX_SYS_SDIO_CTRL, val32);
return MACSUCCESS;
}
static u32 _patch_pcie_l2_hci_ldo(struct mac_ax_adapter *adapter)
{
u32 ret;
u16 bit_set;
u8 val8;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return MACSUCCESS;
bit_set = BIT0;
ret = dbi_r8_pcie(adapter, CFG_RST_MSTATE, &val8);
if (ret != MACSUCCESS)
return ret;
val8 |= bit_set;
ret = dbi_w8_pcie(adapter, CFG_RST_MSTATE, val8);
if (ret != MACSUCCESS)
return ret;
ret = dbi_r8_pcie(adapter, CFG_RST_MSTATE, &val8);
if (ret != MACSUCCESS)
return ret;
val8 |= bit_set;
ret = dbi_w8_pcie(adapter, CFG_RST_MSTATE, val8);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
static u32 _patch_pcie_rxdma_prefth(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
return MACSUCCESS;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_DIS_RXDMA_PRE);
return MACSUCCESS;
}
static u32 _patch_pcie_sw_ltr_setparm(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_ltr_param *param)
{
if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
is_cv(adapter, CBV)))
return MACSUCCESS;
param->ltr_hw_ctrl = MAC_AX_PCIE_DISABLE;
return MACSUCCESS;
}
static u32 _patch_pcie_sw_ltr(struct mac_ax_adapter *adapter,
enum mac_ax_pcie_ltr_sw_ctrl ctrl)
{
u32 ret;
if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
is_cv(adapter, CBV)))
return MACSUCCESS;
ret = ltr_sw_trigger(adapter, ctrl);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie ltr sw trig %d %d\n", ctrl, ret);
return ret;
}
return MACSUCCESS;
}
void ctrl_dma_all_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 c_id = adapter->hw_info->chip_id;
if (en == MAC_AX_FUNC_EN) {
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
MAC_REG_R32(R_AX_PCIE_DMA_STOP1) &
~B_AX_STOP_PCIEIO);
}
MAC_REG_W32(init_cfg_reg[adapter->hw_info->chip_id],
MAC_REG_R32(init_cfg_reg[c_id]) |
txhci_en_bit[c_id] | rxhci_en_bit[c_id]);
} else {
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
MAC_REG_R32(R_AX_PCIE_DMA_STOP1) |
B_AX_STOP_PCIEIO);
}
MAC_REG_W32(init_cfg_reg[adapter->hw_info->chip_id],
MAC_REG_R32(init_cfg_reg[c_id]) &
~(txhci_en_bit[c_id] | rxhci_en_bit[c_id]));
}
}
u32 clr_idx_all_pcie(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 c_id = adapter->hw_info->chip_id;
u32 val32;
val32 = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX |
B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX |
B_AX_CLR_CH12_IDX;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
val32 |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX |
B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX;
MAC_REG_W32(R_AX_TXBD_RWPTR_CLR1, val32);
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX;
MAC_REG_W32(txbd_rwptr_clr2_reg[c_id], val32);
}
val32 = B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX;
MAC_REG_W32(rxbd_rwptr_clr_reg[c_id], val32);
PLTFM_MSG_ALWAYS("Clear all bd index done.\n");
return MACSUCCESS;
}
u32 ctrl_txdma_ch_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_txdma_ch_map *ch_map)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 c_id = adapter->hw_info->chip_id;
u32 val32;
val32 = MAC_REG_R32(dma_stop1_reg[c_id]);
if (ch_map->ch0 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH0;
else if (ch_map->ch0 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH0;
if (ch_map->ch1 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH1;
else if (ch_map->ch1 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH1;
if (ch_map->ch2 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH2;
else if (ch_map->ch2 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH2;
if (ch_map->ch3 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH3;
else if (ch_map->ch3 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH3;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (ch_map->ch4 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH4;
else if (ch_map->ch4 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH4;
if (ch_map->ch5 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH5;
else if (ch_map->ch5 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH5;
if (ch_map->ch6 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH6;
else if (ch_map->ch6 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH6;
if (ch_map->ch7 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_ACH7;
else if (ch_map->ch7 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_ACH7;
}
if (ch_map->ch8 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_CH8;
else if (ch_map->ch8 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_CH8;
if (ch_map->ch9 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_CH9;
else if (ch_map->ch9 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_CH9;
if (ch_map->ch12 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_CH12;
else if (ch_map->ch12 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_CH12;
MAC_REG_W32(dma_stop1_reg[c_id], val32);
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(dma_stop2_reg[c_id]);
if (ch_map->ch10 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_CH10;
else if (ch_map->ch10 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_CH10;
if (ch_map->ch11 == MAC_AX_PCIE_ENABLE)
val32 &= ~B_AX_STOP_CH11;
else if (ch_map->ch11 == MAC_AX_PCIE_DISABLE)
val32 |= B_AX_STOP_CH11;
MAC_REG_W32(dma_stop2_reg[c_id], val32);
}
return MACSUCCESS;
}
u32 poll_txdma_ch_idle_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_txdma_ch_map *ch_map)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 c_id = adapter->hw_info->chip_id;
u32 val32;
u32 cnt;
val32 = 0;
if (ch_map->ch0 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH0_BUSY;
if (ch_map->ch1 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH1_BUSY;
if (ch_map->ch2 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH2_BUSY;
if (ch_map->ch3 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH3_BUSY;
if (ch_map->ch8 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_CH8_BUSY;
if (ch_map->ch9 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_CH9_BUSY;
if (ch_map->ch12 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_CH12_BUSY;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (ch_map->ch4 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH4_BUSY;
if (ch_map->ch5 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH5_BUSY;
if (ch_map->ch6 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH6_BUSY;
if (ch_map->ch7 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_ACH7_BUSY;
}
cnt = PCIE_POLL_DMACH_IDLE_CNT;
while (cnt && (MAC_REG_R32(dma_busy1_reg[c_id]) & val32)) {
cnt--;
PLTFM_DELAY_US(PCIE_POLL_DMACH_IDLE_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]PCIE dmach busy1 0x%X\n",
MAC_REG_R32(dma_busy1_reg[c_id]));
return MACPOLLTO;
}
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = 0;
if (ch_map->ch10 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_CH10_BUSY;
if (ch_map->ch11 == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_CH11_BUSY;
cnt = PCIE_POLL_DMACH_IDLE_CNT;
while (cnt && (MAC_REG_R32(dma_busy2_reg[c_id]) & val32)) {
cnt--;
PLTFM_DELAY_US(PCIE_POLL_DMACH_IDLE_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]PCIE dmach busy2 0x%X\n",
MAC_REG_R32(dma_busy2_reg[c_id]));
return MACPOLLTO;
}
}
return MACSUCCESS;
}
u32 poll_rxdma_ch_idle_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_rxdma_ch_map *ch_map)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 c_id = adapter->hw_info->chip_id;
u32 val32;
u32 cnt;
val32 = 0;
if (ch_map->rxq == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_RXQ_BUSY;
if (ch_map->rpq == MAC_AX_PCIE_ENABLE)
val32 |= B_AX_RPQ_BUSY;
cnt = PCIE_POLL_DMACH_IDLE_CNT;
while (cnt && (MAC_REG_R32(dma_busy3_reg[c_id]) & val32)) {
cnt--;
PLTFM_DELAY_US(PCIE_POLL_DMACH_IDLE_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]PCIE dmach busy1 0x%X\n",
MAC_REG_R32(dma_busy3_reg[c_id]));
return MACPOLLTO;
}
return MACSUCCESS;
}
u32 poll_dma_all_idle_pcie(struct mac_ax_adapter *adapter)
{
struct mac_ax_txdma_ch_map txch_map;
struct mac_ax_rxdma_ch_map rxch_map;
u32 ret;
txch_map.ch0 = MAC_AX_PCIE_ENABLE;
txch_map.ch1 = MAC_AX_PCIE_ENABLE;
txch_map.ch2 = MAC_AX_PCIE_ENABLE;
txch_map.ch3 = MAC_AX_PCIE_ENABLE;
txch_map.ch4 = MAC_AX_PCIE_ENABLE;
txch_map.ch5 = MAC_AX_PCIE_ENABLE;
txch_map.ch6 = MAC_AX_PCIE_ENABLE;
txch_map.ch7 = MAC_AX_PCIE_ENABLE;
txch_map.ch8 = MAC_AX_PCIE_ENABLE;
txch_map.ch9 = MAC_AX_PCIE_ENABLE;
txch_map.ch10 = MAC_AX_PCIE_ENABLE;
txch_map.ch11 = MAC_AX_PCIE_ENABLE;
txch_map.ch12 = MAC_AX_PCIE_ENABLE;
ret = poll_txdma_ch_idle_pcie(adapter, &txch_map);
if (ret) {
PLTFM_MSG_ERR("[ERR]PCIE poll txdma all ch idle\n");
return ret;
}
rxch_map.rxq = MAC_AX_PCIE_ENABLE;
rxch_map.rpq = MAC_AX_PCIE_ENABLE;
ret = poll_rxdma_ch_idle_pcie(adapter, &rxch_map);
if (ret) {
PLTFM_MSG_ERR("[ERR]PCIE poll rxdma all ch idle\n");
return ret;
}
return ret;
}
u32 ctrl_txhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (en == MAC_AX_FUNC_EN) {
MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_TXHCI_EN);
} else if (en == MAC_AX_FUNC_DIS) {
MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_TXHCI_EN);
} else {
PLTFM_MSG_ERR("[ERR]Wrong Input for Ctrl TX HCI\n");
return MACFUNCINPUT;
}
return MACSUCCESS;
}
u32 ctrl_rxhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (en == MAC_AX_FUNC_EN) {
MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_RXHCI_EN);
} else if (en == MAC_AX_FUNC_DIS) {
MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
MAC_REG_R32(R_AX_PCIE_INIT_CFG1) & ~B_AX_RXHCI_EN);
} else {
PLTFM_MSG_ERR("[ERR]Wrong Input for Ctrl RX HCI\n");
return MACFUNCINPUT;
}
return MACSUCCESS;
}
u32 ctrl_dma_io_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (en == MAC_AX_FUNC_EN) {
MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
MAC_REG_R32(R_AX_PCIE_DMA_STOP1)
& ~B_AX_STOP_PCIEIO);
} else if (en == MAC_AX_FUNC_DIS) {
MAC_REG_W32(R_AX_PCIE_DMA_STOP1,
MAC_REG_R32(R_AX_PCIE_DMA_STOP1)
| B_AX_STOP_PCIEIO);
} else {
PLTFM_MSG_ERR("[ERR]Wrong Input for DMA IO\n");
return MACFUNCINPUT;
}
return MACSUCCESS;
}
u32 pcie_pre_init(struct mac_ax_adapter *adapter, void *param)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_intf_info *intf_info = (struct mac_ax_intf_info *)param;
struct mac_ax_txdma_ch_map ch_map;
u32 ret = MACSUCCESS;
ret = _patch_pcie_rxdma_prefth(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie dis rxdma prefth %d\n", ret);
return ret;
}
ret = _patch_pcie_l1off_pwroff(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie dis l1off pwroff %d\n", ret);
return ret;
}
ret = _patch_pcie_deglitch(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie deglitch %d\n", ret);
return ret;
}
ret = _patch_pcie_l2_rxen_lat(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie l2 rxen latency %d\n", ret);
return ret;
}
ret = _patch_pcie_aphy_pwrcut(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie aphy pwrcut %d\n", ret);
return ret;
}
ret = _patch_pcie_hci_ldo(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie hci ldo %d\n", ret);
return ret;
}
ret = _patch_pcie_refclk_autok(adapter, intf_info);
if (ret) {
PLTFM_MSG_ERR("[ERR]patch pcie refclk autok %d\n", ret);
return ret;
}
ret = _patch_pcie_power_wake(adapter, PC_POWER_UP);
if (ret) {
PLTFM_MSG_ERR("[ERR]patch pcie power wake %d\n", ret);
return ret;
}
ret = pcie_set_sic(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie sic %d\n", ret);
return ret;
}
ret = pcie_set_lbc(adapter, intf_info->lbc_en, intf_info->lbc_tmr);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie set lbc %d\n", ret);
return ret;
}
ret = pcie_set_io_rcy(adapter, intf_info->io_rcy_en,
intf_info->io_rcy_tmr);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie set io rcy %d\n", ret);
return ret;
}
ret = pcie_set_dbg(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie set dbg %d\n", ret);
return ret;
}
ret = pcie_set_keep_reg(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie set keep reg %d\n", ret);
return ret;
}
if (intf_info->skip_all)
return ret;
if (!intf_info->txbd_buf || !intf_info->rxbd_buf ||
!intf_info->txch_map)
return MACNPTR;
MAC_REG_W32(dma_stop1_reg[adapter->hw_info->chip_id],
MAC_REG_R32(dma_stop1_reg[adapter->hw_info->chip_id]) |
B_AX_STOP_WPDMA);
ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
ret = clr_idx_all_pcie(adapter);
if (ret)
return ret;
ret = poll_dma_all_idle_pcie(adapter);
if (ret)
return ret;
ret = mode_op(adapter, intf_info);
if (ret)
return ret;
ret = trx_init_bd(adapter, intf_info);
if (ret)
return ret;
ret = rst_bdram_pcie(adapter, 0);
if (ret)
return ret;
ch_map.ch0 = MAC_AX_PCIE_DISABLE;
ch_map.ch1 = MAC_AX_PCIE_DISABLE;
ch_map.ch2 = MAC_AX_PCIE_DISABLE;
ch_map.ch3 = MAC_AX_PCIE_DISABLE;
ch_map.ch4 = MAC_AX_PCIE_DISABLE;
ch_map.ch5 = MAC_AX_PCIE_DISABLE;
ch_map.ch6 = MAC_AX_PCIE_DISABLE;
ch_map.ch7 = MAC_AX_PCIE_DISABLE;
ch_map.ch8 = MAC_AX_PCIE_DISABLE;
ch_map.ch9 = MAC_AX_PCIE_DISABLE;
ch_map.ch10 = MAC_AX_PCIE_DISABLE;
ch_map.ch11 = MAC_AX_PCIE_DISABLE;
ch_map.ch12 = MAC_AX_PCIE_ENABLE;
ret = ctrl_txdma_ch_pcie(adapter, &ch_map);
if (ret)
return ret;
ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_EN);
return MACSUCCESS;
}
u32 pcie_init(struct mac_ax_adapter *adapter, void *param)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_intf_info *intf_info = (struct mac_ax_intf_info *)param;
u8 c_id = adapter->hw_info->chip_id;
u32 val32, ret = MACSUCCESS;
struct mac_ax_pcie_ltr_param ltr_param = {
1,
0,
MAC_AX_PCIE_DEFAULT,
MAC_AX_PCIE_DEFAULT,
MAC_AX_PCIE_LTR_SPC_DEF,
MAC_AX_PCIE_LTR_IDLE_TIMER_DEF,
{MAC_AX_PCIE_DEFAULT, 0},
{MAC_AX_PCIE_DEFAULT, 0},
{MAC_AX_PCIE_DEFAULT, 0},
{MAC_AX_PCIE_DEFAULT, 0}
};
if (intf_info->skip_all)
return MACSUCCESS;
ret = _patch_pcie_sw_ltr_setparm(adapter, <r_param);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie sw ltr set param %d\n", ret);
return ret;
}
ret = ltr_set_pcie(adapter, <r_param);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie ltr set fail %d\n", ret);
return ret;
}
ret = _patch_pcie_sw_ltr(adapter, MAC_AX_PCIE_LTR_SW_ACT);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie sw ltr act %d\n", ret);
return ret;
}
if (!intf_info->txch_map) {
PLTFM_MSG_ERR("[ERR] pcie init no txch map\n");
return MACNPTR;
}
val32 = MAC_REG_R32(dma_stop1_reg[c_id]) &
~(B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO);
MAC_REG_W32(dma_stop1_reg[c_id], val32);
ret = ctrl_txdma_ch_pcie(adapter, intf_info->txch_map);
if (ret)
return ret;
return MACSUCCESS;
}
u32 pcie_deinit(struct mac_ax_adapter *adapter, void *param)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, ret = MACSUCCESS;
struct mac_ax_pcie_ltr_param ltr_param = {
1,
0,
MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_LTR_SPC_DEF,
MAC_AX_PCIE_LTR_IDLE_TIMER_DEF,
{MAC_AX_PCIE_DEFAULT, 0},
{MAC_AX_PCIE_DEFAULT, 0},
{MAC_AX_PCIE_DEFAULT, 0},
{MAC_AX_PCIE_DEFAULT, 0}
};
ret = _patch_pcie_power_wake(adapter, PC_POWER_DOWN);
if (ret) {
PLTFM_MSG_ERR("[ERR]patch pcie power wake %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(R_AX_IC_PWR_STATE);
val32 = GET_FIELD(val32, B_AX_WLMAC_PWR_STE);
if (val32 == MAC_AX_MAC_OFF) {
PLTFM_MSG_WARN("PCIe deinit when MAC off\n");
return MACSUCCESS;
}
ret = ltr_set_pcie(adapter, <r_param);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pcie ltr set fail %d\n", ret);
return ret;
}
ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
ret = clr_idx_all_pcie(adapter);
if (ret)
return ret;
return ret;
}
u32 rst_bdram_pcie(struct mac_ax_adapter *adapter, u8 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt, val32;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1,
MAC_REG_R32(R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM);
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
MAC_REG_W32(R_AX_PCIE_PS_CTRL, MAC_REG_R32(R_AX_PCIE_PS_CTRL) |
B_AX_PCIE_FORCE_L0);
cnt = PCIE_POLL_BDRAM_RST_CNT;
do {
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
if (!(val32 & B_AX_RST_BDRAM))
break;
cnt--;
PLTFM_DELAY_US(PCIE_POLL_BDRAM_RST_DLY_US);
} while (cnt);
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
MAC_REG_W32(R_AX_PCIE_PS_CTRL, MAC_REG_R32(R_AX_PCIE_PS_CTRL) &
~B_AX_PCIE_FORCE_L0);
if (!cnt) {
PLTFM_MSG_ERR("[ERR]rst bdram timeout 0x%X\n", val32);
return MACPOLLTO;
}
return MACSUCCESS;
}
u32 lv1rst_stop_dma_pcie(struct mac_ax_adapter *adapter, u8 val)
{
u32 ret, reg32, dma_rst = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
ret = poll_io_idle_pcie(adapter);
if (ret != MACSUCCESS) {
reg32 = MAC_REG_R32(R_AX_DBG_ERR_FLAG);
if ((reg32 & B_AX_TX_STUCK) ||
(reg32 & B_AX_PCIE_TXBD_LEN0))
dma_rst |= B_AX_HCI_TXDMA_EN;
if (reg32 & B_AX_RX_STUCK)
dma_rst |= B_AX_HCI_RXDMA_EN;
reg32 = MAC_REG_R32(R_AX_HCI_FUNC_EN);
MAC_REG_W32(R_AX_HCI_FUNC_EN, reg32 & ~dma_rst);
MAC_REG_W32(R_AX_HCI_FUNC_EN, reg32 | dma_rst);
ret = poll_io_idle_pcie(adapter);
}
return ret;
}
u32 lv1rst_start_dma_pcie(struct mac_ax_adapter *adapter, u8 val)
{
u32 ret;
ctrl_hci_dma_en_pcie(adapter, MAC_AX_FUNC_DIS);
ctrl_hci_dma_en_pcie(adapter, MAC_AX_FUNC_EN);
ret = clr_idx_all_pcie(adapter);
if (ret)
return ret;
ret = rst_bdram_pcie(adapter, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]rst bdram %d\n", ret);
return ret;
}
ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_EN);
return ret;
}
u32 pcie_pwr_switch(void *vadapter, u8 pre_switch, u8 on)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
if (pre_switch == PWR_PRE_SWITCH)
adapter->mac_pwr_info.pwr_seq_proc = 1;
else if (pre_switch == PWR_POST_SWITCH)
adapter->mac_pwr_info.pwr_seq_proc = 0;
return MACSUCCESS;
}
u32 pcie_trx_mit(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_trx_mitigation *mit_info)
{
u8 tmr_unit = 0;
u32 value32 = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (mit_info->txch_map->ch0 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH0_SEL;
else if (mit_info->txch_map->ch0 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH0_SEL;
if (mit_info->txch_map->ch1 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH1_SEL;
else if (mit_info->txch_map->ch1 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH1_SEL;
if (mit_info->txch_map->ch2 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH2_SEL;
else if (mit_info->txch_map->ch2 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH2_SEL;
if (mit_info->txch_map->ch3 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH3_SEL;
else if (mit_info->txch_map->ch3 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH3_SEL;
if (mit_info->txch_map->ch8 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_CH8_SEL;
else if (mit_info->txch_map->ch8 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_CH8_SEL;
if (mit_info->txch_map->ch9 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_CH9_SEL;
else if (mit_info->txch_map->ch9 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_CH9_SEL;
if (mit_info->txch_map->ch12 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_CH12_SEL;
else if (mit_info->txch_map->ch12 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_CH12_SEL;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (mit_info->txch_map->ch4 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH4_SEL;
else if (mit_info->txch_map->ch4 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH4_SEL;
if (mit_info->txch_map->ch5 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH5_SEL;
else if (mit_info->txch_map->ch5 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH5_SEL;
if (mit_info->txch_map->ch6 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH6_SEL;
else if (mit_info->txch_map->ch6 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH6_SEL;
if (mit_info->txch_map->ch7 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_ACH7_SEL;
else if (mit_info->txch_map->ch7 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_ACH7_SEL;
if (mit_info->txch_map->ch10 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_CH10_SEL;
else if (mit_info->txch_map->ch10 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_CH10_SEL;
if (mit_info->txch_map->ch11 == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_TXMIT_CH11_SEL;
else if (mit_info->txch_map->ch11 == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_TXMIT_CH11_SEL;
}
switch (mit_info->tx_timer_unit) {
case MAC_AX_MIT_64US:
tmr_unit = 0;
break;
case MAC_AX_MIT_128US:
tmr_unit = 1;
break;
case MAC_AX_MIT_256US:
tmr_unit = 2;
break;
case MAC_AX_MIT_512US:
tmr_unit = 3;
break;
default:
PLTFM_MSG_WARN("[WARN]Set TX MIT timer unit fail\n");
break;
}
value32 = SET_CLR_WOR2(value32, tmr_unit,
B_AX_TXTIMER_UNIT_SH,
B_AX_TXTIMER_UNIT_MSK);
value32 = SET_CLR_WOR2(value32, mit_info->tx_counter,
B_AX_TXCOUNTER_MATCH_SH,
B_AX_TXCOUNTER_MATCH_MSK);
value32 = SET_CLR_WOR2(value32, mit_info->tx_timer,
B_AX_TXTIMER_MATCH_SH,
B_AX_TXTIMER_MATCH_MSK);
MAC_REG_W32(R_AX_INT_MIT_TX, value32);
value32 = 0;
if (mit_info->rxch_map->rxq == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_RXMIT_RXP2_SEL;
else if (mit_info->rxch_map->rxq == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_RXMIT_RXP2_SEL;
if (mit_info->rxch_map->rpq == MAC_AX_PCIE_ENABLE)
value32 |= B_AX_RXMIT_RXP1_SEL;
else if (mit_info->rxch_map->rpq == MAC_AX_PCIE_DISABLE)
value32 &= ~B_AX_RXMIT_RXP1_SEL;
switch (mit_info->rx_timer_unit) {
case MAC_AX_MIT_64US:
tmr_unit = 0;
break;
case MAC_AX_MIT_128US:
tmr_unit = 1;
break;
case MAC_AX_MIT_256US:
tmr_unit = 2;
break;
case MAC_AX_MIT_512US:
tmr_unit = 3;
break;
default:
PLTFM_MSG_WARN("[WARN]Set RX MIT timer unit fail\n");
break;
}
value32 = SET_CLR_WOR2(value32, tmr_unit,
B_AX_RXTIMER_UNIT_SH,
B_AX_RXTIMER_UNIT_MSK);
value32 = SET_CLR_WOR2(value32, mit_info->rx_counter,
B_AX_RXCOUNTER_MATCH_SH,
B_AX_RXCOUNTER_MATCH_MSK);
value32 = SET_CLR_WOR2(value32, mit_info->rx_timer,
B_AX_RXTIMER_MATCH_SH,
B_AX_RXTIMER_MATCH_MSK);
MAC_REG_W32(R_AX_INT_MIT_RX, value32);
return MACSUCCESS;
}
u32 set_pcie_wowlan(struct mac_ax_adapter *adapter, enum mac_ax_wow_ctrl w_c)
{
u32 val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (w_c == MAC_AX_WOW_ENTER) {
MAC_REG_W32(R_AX_SYS_SDIO_CTRL,
MAC_REG_R32(R_AX_SYS_SDIO_CTRL) &
~B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
B_AX_WLOCK_1C_B6);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
B_AX_R_DIS_PRST);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
~B_AX_WLOCK_1C_B6);
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
val32 |= B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG;
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
} else if (w_c == MAC_AX_WOW_LEAVE) {
MAC_REG_W32(R_AX_SYS_SDIO_CTRL,
MAC_REG_R32(R_AX_SYS_SDIO_CTRL) |
B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
B_AX_WLOCK_1C_B6);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
~B_AX_R_DIS_PRST);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
~B_AX_WLOCK_1C_B6);
val32 = MAC_REG_R32(R_AX_PCIE_INIT_CFG1);
val32 &= (~B_AX_PCIE_PERST_KEEP_REG &
~B_AX_PCIE_TRAIN_KEEP_REG);
MAC_REG_W32(R_AX_PCIE_INIT_CFG1, val32);
ret = _patch_pcie_l2_hci_ldo(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]patch pcie l2 hci ldo %d\n", ret);
return ret;
}
} else {
PLTFM_MSG_ERR("[ERR] Invalid WoWLAN input.\n");
return MACFUNCINPUT;
}
return MACSUCCESS;
}
u32 set_pcie_l2_leave(struct mac_ax_adapter *adapter, u8 set)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (set) {
/* fix WoWLAN Power Consumption */
MAC_REG_W32(R_AX_SYS_SDIO_CTRL,
MAC_REG_R32(R_AX_SYS_SDIO_CTRL) &
~B_AX_PCIE_CALIB_EN_V1);
}
return MACSUCCESS;
}
u32 get_io_stat_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_io_stat *out_st)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, to_addr;
val32 = MAC_REG_R32(R_AX_LBC_WATCHDOG);
if (val32 & B_AX_LBC_FLAG) {
adapter->sm.io_st = MAC_AX_IO_ST_HANG;
to_addr = GET_FIELD(val32, B_AX_LBC_ADDR);
PLTFM_MSG_ERR("[ERR]pcie io timeout addr 0x%X\n", to_addr);
if (out_st) {
out_st->to_flag = 1;
out_st->io_st = adapter->sm.io_st;
out_st->addr = to_addr;
}
MAC_REG_W32(R_AX_LBC_WATCHDOG, val32);
} else if (out_st) {
out_st->to_flag = 0;
out_st->io_st = adapter->sm.io_st;
out_st->addr = 0;
}
return MACSUCCESS;
}
u32 pcie_get_txagg_num(struct mac_ax_adapter *adapter, u8 band)
{
return PCIE_DEFAULT_AGG_NUM;
}
#endif /* #if MAC_AX_PCIE_SUPPORT */
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/_pcie.c
|
C
|
agpl-3.0
| 99,904
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PCIE_H_
#define _MAC_AX_PCIE_H_
#include "../type.h"
#include "../pcie_reg.h"
#include "../mac_ax.h"
/*--------------------Define -------------------------------------------*/
#define INTF_INTGRA_MINREF_V1 90
#define INTF_INTGRA_HOSTREF_V1 100
#define GET_PCIE_FUNC_STUS(val, mask) (((val) & (mask)) ? \
MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE)
#define PCIE_POLL_IO_IDLE_CNT 100
#define PCIE_POLL_IO_IDLE_DLY_US 10
#define PCIE_POLL_DMACH_IDLE_CNT 100
#define PCIE_POLL_DMACH_IDLE_DLY_US 10
#define PCIE_POLL_BDRAM_RST_CNT 10000
#define PCIE_POLL_BDRAM_RST_DLY_US 50
#define PCIE_POLL_AUTOK_CNT 1000
#define PCIE_POLL_AUTOK_DLY_US 50
#define DBI_ADDR_MASK 0xFFC
#define DBI_ADDR_2LSB_MASK 0x3
#define DBI_WEN_DW 0xF
#define DBI_WEN_B 1
#define DBI_DLY_CNT 20
#define DBI_DLY_US 10
#define MDIO_ADDR_PG1 0x20
#define MDIO_DLY_CNT 20
#define MDIO_DLY_US 10
#define BDRAM_SIDX_MSK 0x1f
#define BDRAM_MAX_MSK 0x1f00
#define BDRAM_MIN_MSK 0x1f0000
#define MDIO_PG0_G1 0
#define MDIO_PG1_G1 1
#define MDIO_PG0_G2 2
#define MDIO_PG1_G2 3
#define BD_NORM_SIZE 12
#define BD_TRUNC_SIZE 8
#define RXBD_SEP_NORM_SIZE 20
#define RXBD_SEP_TRUNC_OLD_SIZE 12
#define RXBD_SEP_TRUNC_NEW_SIZE 16
#define BD_MAX_NUM 0x3FF
#define TXBD_BYTE_ALIGN 8
#define RXBD_BYTE_ALIGN 4
#define B_AX_CLK_CALIB_EN BIT12
#define CMAC_CLK_ALLEN 0xFFFFFFFF
#define PC_POWER_UP 1
#define PC_POWER_DOWN 0
#define BIT_WAKE_CTRL BIT5
#define PCIE_DEFAULT_AGG_NUM 0x40
/*--------------------Define MACRO--------------------------------------*/
/*--------------------Define Enum---------------------------------------*/
enum pcie_clkdly_hw {
PCIE_CLKDLY_HW_0 = 0,
PCIE_CLKDLY_HW_30US = 0x1,
PCIE_CLKDLY_HW_50US = 0x2,
PCIE_CLKDLY_HW_80US = 0x3,
PCIE_CLKDLY_HW_100US = 0x4,
PCIE_CLKDLY_HW_120US = 0x5,
PCIE_CLKDLY_HW_150US = 0x6,
PCIE_CLKDLY_HW_180US = 0x7,
PCIE_CLKDLY_HW_200US = 0x8,
PCIE_CLKDLY_HW_300US = 0x9,
PCIE_CLKDLY_HW_400US = 0xA,
PCIE_CLKDLY_HW_500US = 0xB,
PCIE_CLKDLY_HW_1MS = 0xC,
PCIE_CLKDLY_HW_3MS = 0xD,
PCIE_CLKDLY_HW_5MS = 0xE,
PCIE_CLKDLY_HW_10MS = 0xF
};
enum pcie_l1dly_hw {
PCIE_L1DLY_HW_16US = 4,
PCIE_L1DLY_HW_32US = 5,
PCIE_L1DLY_HW_64US = 6,
PCIE_L1DLY_HW_INFI = 7
};
enum pcie_l0sdly_hw {
PCIE_L0SDLY_HW_1US = 0,
PCIE_L0SDLY_HW_2US = 1,
PCIE_L0SDLY_HW_3US = 2,
PCIE_L0SDLY_HW_4US = 3,
PCIE_L0SDLY_HW_5US = 4,
PCIE_L0SDLY_HW_6US = 5,
PCIE_L0SDLY_HW_7US = 6
};
/*--------------------Define Struct-------------------------------------*/
struct txbd_ram {
u8 sidx;
u8 max;
u8 min;
};
/**
* @brief reg_read8_pcie
*
* @param *adapter
* @param addr
* @return Please Place Description here.
* @retval u8
*/
u8 reg_read8_pcie(struct mac_ax_adapter *adapter, u32 addr);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_write8_pcie
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval void
*/
void reg_write8_pcie(struct mac_ax_adapter *adapter, u32 addr, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_read16_pcie
*
* @param *adapter
* @param addr
* @return Please Place Description here.
* @retval u16
*/
u16 reg_read16_pcie(struct mac_ax_adapter *adapter, u32 addr);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_write16_pcie
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval void
*/
void reg_write16_pcie(struct mac_ax_adapter *adapter, u32 addr, u16 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_read32_pcie
*
* @param *adapter
* @param addr
* @return Please Place Description here.
* @retval u32
*/
u32 reg_read32_pcie(struct mac_ax_adapter *adapter, u32 addr);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_write32_pcie
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval void
*/
void reg_write32_pcie(struct mac_ax_adapter *adapter, u32 addr, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief dbi_r8_pcie
*
* @param *adapter
* @param addr
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 dbi_r8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 *val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief dbi_w8_pcie
*
* @param *adapter
* @param addr
* @param data
* @return Please Place Description here.
* @retval u32
*/
u32 dbi_w8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 data);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief dbi_r32_pcie
*
* @param *adapter
* @param addr
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 dbi_r32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 *val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief dbi_w32_pcie
*
* @param *adapter
* @param addr
* @param data
* @return Please Place Description here.
* @retval u32
*/
u32 dbi_w32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 data);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief mdio_r16_pcie
*
* @param *adapter
* @param addr
* @param speed
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mdio_r16_pcie(struct mac_ax_adapter *adapter, u8 addr, u8 speed, u16 *val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief mdio_w16_pcie
*
* @param *adapter
* @param addr
* @param data
* @param speed
* @return Please Place Description here.
* @retval u32
*/
u32 mdio_w16_pcie(struct mac_ax_adapter *adapter, u8 addr, u16 data, u8 speed);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief cfgspc_set_pcie
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 cfgspc_set_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_cfgspc_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ltr_set_pcie
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 ltr_set_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_ltr_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ltr_sw_trigger
*
* @param *adapter
* @param ctrl
* @return Please Place Description here.
* @retval u32
*/
u32 ltr_sw_trigger(struct mac_ax_adapter *adapter,
enum mac_ax_pcie_ltr_sw_ctrl ctrl);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ctrl_dma_all_pcie
*
* @param *adapter
* @param en
* @return Please Place Description here.
* @retval void
*/
void ctrl_dma_all_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief clr_idx_all_pcie
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 clr_idx_all_pcie(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ctrl_txdma_ch_pcie
*
* @param *adapter
* @param *ch_map
* @return Please Place Description here.
* @retval u32
*/
u32 ctrl_txdma_ch_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_txdma_ch_map *ch_map);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief poll_txdma_ch_idle_pcie
*
* @param *adapter
* @param *ch_map
* @return Please Place Description here.
* @retval u32
*/
u32 poll_txdma_ch_idle_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_txdma_ch_map *ch_map);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief poll_rxdma_ch_idle_pcie
*
* @param *adapter
* @param *ch_map
* @return Please Place Description here.
* @retval u32
*/
u32 poll_rxdma_ch_idle_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_rxdma_ch_map *ch_map);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief poll_dma_all_idle_pcie
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 poll_dma_all_idle_pcie(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ctrl_txhci_pcie
*
* @param *adapter
* @param en
* @return Please Place Description here.
* @retval u32
*/
u32 ctrl_txhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ctrl_rxhci_pcie
*
* @param *adapter
* @param en
* @return Please Place Description here.
* @retval u32
*/
u32 ctrl_rxhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief ctrl_dma_io_pcie
*
* @param *adapter
* @param en
* @return Please Place Description here.
* @retval u32
*/
u32 ctrl_dma_io_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief pcie_pre_init
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 pcie_pre_init(struct mac_ax_adapter *adapter, void *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief pcie_init
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 pcie_init(struct mac_ax_adapter *adapter, void *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief pcie_deinit
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 pcie_deinit(struct mac_ax_adapter *adapter, void *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief rst_bdram_pcie
*
* @param *adapter
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 rst_bdram_pcie(struct mac_ax_adapter *adapter, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief lv1rst_stop_dma_pcie
*
* @param *adapter
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 lv1rst_stop_dma_pcie(struct mac_ax_adapter *adapter, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief lv1rst_start_dma_pcie
*
* @param *adapter
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 lv1rst_start_dma_pcie(struct mac_ax_adapter *adapter, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief pcie_pwr_switch
*
* @param *vadapter
* @param pre_switch
* @param on
* @return Please Place Description here.
* @retval u32
*/
u32 pcie_pwr_switch(void *vadapter,
u8 pre_switch, u8 on);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief set_pcie_wowlan
*
* @param *adapter
* @param w_c
* @return Please Place Description here.
* @retval u32
*/
u32 set_pcie_wowlan(struct mac_ax_adapter *adapter, enum mac_ax_wow_ctrl w_c);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief pcie_trx_mit
*
* @param *adapter
* @param *mit_info
* @return Please Place Description here.
* @retval u32
*/
u32 pcie_trx_mit(struct mac_ax_adapter *adapter,
struct mac_ax_pcie_trx_mitigation *mit_info);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief set_pcie_l2_leave
*
* @param *adapter
* @param set
* @return Please Place Description here.
* @retval u32
*/
u32 set_pcie_l2_leave(struct mac_ax_adapter *adapter, u8 set);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup PCIE
* @{
*/
/**
* @brief get_io_stat_pcie
*
* @param *adapter
* @param *out_st
* @return Please Place Description here.
* @retval u32
*/
u32 get_io_stat_pcie(struct mac_ax_adapter *adapter,
struct mac_ax_io_stat *out_st);
/**
* @}
* @}
*/
/**
* @brief pcie_get_txagg_num
*
* @param *adapter
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 pcie_get_txagg_num(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/_pcie.h
|
C
|
agpl-3.0
| 13,529
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "addr_cam.h"
#define MAC_AX_NO_HIT_IDX 0xFF
static u8 get_set_bits_of_msk(u8 msk)
{
u8 set_bits;
if (msk == 0)
return 0;
set_bits = msk & (msk - 1);
if (set_bits == 0)
return 1;
return get_set_bits_of_msk(set_bits) + 1;
}
u32 find_avail_addr_cam_entry(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
u16 i;
for (i = 0; i < adapter->hw_info->macid_num; i++) {
if (!mac_role_srch_by_addr_cam(adapter, i))
break;
}
if (i == adapter->hw_info->macid_num)
return MACADDRCAMFL;
info->a_info.addr_cam_idx = (u8)i;
return MACSUCCESS;
}
u32 find_avail_bssid_cam_entry(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info)
{
u8 i;
struct mac_role_tbl *role;
u8 maddr_cmp_len = ETH_ALEN;
info->a_info.bssid_cam_idx = adapter->hw_info->bssid_num;
info->b_info.bssid_cam_idx = adapter->hw_info->bssid_num;
if (info->a_info.mask_sel == MAC_AX_BSSID_MSK)
maddr_cmp_len = get_set_bits_of_msk(info->a_info.addr_mask);
for (i = 0; i < adapter->hw_info->bssid_num; i++) {
role = mac_role_srch_by_bssid(adapter, i);
if (role &&
!PLTFM_MEMCMP(info->bssid,
role->info.bssid, maddr_cmp_len) &&
info->band == role->info.band) {
info->a_info.bssid_cam_idx =
role->info.a_info.bssid_cam_idx;
if (maddr_cmp_len < ETH_ALEN) {
PLTFM_MEMCPY(info->b_info.bssid,
role->info.b_info.bssid,
ETH_ALEN);
}
break;
} else if (!role) {
if (info->a_info.bssid_cam_idx ==
adapter->hw_info->bssid_num) {
info->a_info.bssid_cam_idx = i;
}
}
}
if (info->a_info.bssid_cam_idx == adapter->hw_info->bssid_num)
return MACBSSIDCAMFL;
info->b_info.bssid_cam_idx = info->a_info.bssid_cam_idx;
return MACSUCCESS;
}
u32 init_addr_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam)
{
u32 ret;
ret = find_avail_addr_cam_entry(adapter, info);
if (ret)
return ret;
ret = find_avail_bssid_cam_entry(adapter, info);
if (ret)
return ret;
fill_addr_cam_info(adapter, info, fw_addrcam);
fill_bssid_cam_info(adapter, info, fw_addrcam);
return MACSUCCESS;
}
u32 change_addr_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam)
{
u32 ret;
ret = find_avail_bssid_cam_entry(adapter, info);
if (ret)
return ret;
fill_addr_cam_info(adapter, info, fw_addrcam);
fill_bssid_cam_info(adapter, info, fw_addrcam);
return MACSUCCESS;
}
u32 fill_addr_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam)
{
struct mac_ax_addr_cam_info a_info;
u8 i;
u8 sma_hash = 0x00;
u8 tma_hash = 0x00;
u8 maddr_cmp_len;
maddr_cmp_len = get_set_bits_of_msk(info->a_info.addr_mask);
switch (info->a_info.mask_sel) {
case MAC_AX_SMA_MSK:
for (i = 0; i < maddr_cmp_len; i++)
sma_hash ^= info->a_info.sma[i];
for (i = 0; i < ETH_ALEN; i++)
tma_hash ^= info->a_info.tma[i];
break;
case MAC_AX_TMA_MSK:
for (i = 0; i < ETH_ALEN; i++)
sma_hash ^= info->a_info.sma[i];
for (i = 0; i < maddr_cmp_len; i++)
tma_hash ^= info->a_info.tma[i];
break;
case MAC_AX_NO_MSK:
case MAC_AX_BSSID_MSK:
default:
for (i = 0; i < ETH_ALEN; i++)
sma_hash ^= info->a_info.sma[i];
for (i = 0; i < ETH_ALEN; i++)
tma_hash ^= info->a_info.tma[i];
break;
}
a_info = info->a_info;
fw_addrcam->dword1 =
cpu_to_le32(SET_WORD(a_info.addr_cam_idx,
FWCMD_H2C_ADDRCAM_INFO_IDX) |
SET_WORD(a_info.offset, FWCMD_H2C_ADDRCAM_INFO_OFFSET) |
SET_WORD(a_info.len, FWCMD_H2C_ADDRCAM_INFO_LEN));
fw_addrcam->dword2 =
cpu_to_le32(((a_info.valid) ? FWCMD_H2C_ADDRCAM_INFO_VALID : 0) |
SET_WORD(a_info.net_type, FWCMD_H2C_ADDRCAM_INFO_NET_TYPE) |
SET_WORD(a_info.bcn_hit_cond, FWCMD_H2C_ADDRCAM_INFO_BCN_HIT_COND) |
SET_WORD(a_info.hit_rule, FWCMD_H2C_ADDRCAM_INFO_HIT_RULE) |
((a_info.bb_sel) ? FWCMD_H2C_ADDRCAM_INFO_BB_SEL : 0) |
SET_WORD(a_info.addr_mask, FWCMD_H2C_ADDRCAM_INFO_ADDR_MASK) |
SET_WORD(a_info.mask_sel, FWCMD_H2C_ADDRCAM_INFO_MASK_SEL) |
SET_WORD(sma_hash, FWCMD_H2C_ADDRCAM_INFO_SMA_HASH) |
SET_WORD(tma_hash, FWCMD_H2C_ADDRCAM_INFO_TMA_HASH));
fw_addrcam->dword3 =
cpu_to_le32(SET_WORD(a_info.bssid_cam_idx,
FWCMD_H2C_ADDRCAM_INFO_BSSID_CAM_IDX) |
((a_info.is_mul_ent) ? FWCMD_H2C_ADDRCAM_INFO_IS_MUL_ENT : 0));
fw_addrcam->dword4 =
cpu_to_le32(SET_WORD(a_info.sma[0], FWCMD_H2C_ADDRCAM_INFO_SMA0) |
SET_WORD(a_info.sma[1], FWCMD_H2C_ADDRCAM_INFO_SMA1) |
SET_WORD(a_info.sma[2], FWCMD_H2C_ADDRCAM_INFO_SMA2) |
SET_WORD(a_info.sma[3], FWCMD_H2C_ADDRCAM_INFO_SMA3));
fw_addrcam->dword5 =
cpu_to_le32(SET_WORD(a_info.sma[4], FWCMD_H2C_ADDRCAM_INFO_SMA4) |
SET_WORD(a_info.sma[5], FWCMD_H2C_ADDRCAM_INFO_SMA5) |
SET_WORD(a_info.tma[0], FWCMD_H2C_ADDRCAM_INFO_TMA0) |
SET_WORD(a_info.tma[1], FWCMD_H2C_ADDRCAM_INFO_TMA1));
fw_addrcam->dword6 =
cpu_to_le32(SET_WORD(a_info.tma[2], FWCMD_H2C_ADDRCAM_INFO_TMA2) |
SET_WORD(a_info.tma[3], FWCMD_H2C_ADDRCAM_INFO_TMA3) |
SET_WORD(a_info.tma[4], FWCMD_H2C_ADDRCAM_INFO_TMA4) |
SET_WORD(a_info.tma[5], FWCMD_H2C_ADDRCAM_INFO_TMA5));
// dword7 rsvd
fw_addrcam->dword8 =
cpu_to_le32(SET_WORD(a_info.macid, FWCMD_H2C_ADDRCAM_INFO_MACID) |
SET_WORD(a_info.port_int, FWCMD_H2C_ADDRCAM_INFO_PORT_INT) |
SET_WORD(a_info.tsf_sync, FWCMD_H2C_ADDRCAM_INFO_TSF_SYNC) |
((a_info.tf_trs) ? FWCMD_H2C_ADDRCAM_INFO_TF_TRS : 0) |
((a_info.lsig_txop) ? FWCMD_H2C_ADDRCAM_INFO_LSIG_TXOP : 0) |
SET_WORD(a_info.tgt_ind, FWCMD_H2C_ADDRCAM_INFO_TGT_IND) |
SET_WORD(a_info.frm_tgt_ind, FWCMD_H2C_ADDRCAM_INFO_FRM_TGT_IND));
fw_addrcam->dword9 =
cpu_to_le32((a_info.aid12 & 0xfff) |
((a_info.wol_pattern) ? FWCMD_H2C_ADDRCAM_INFO_WOL_PATTERN : 0) |
((a_info.wol_uc) ? FWCMD_H2C_ADDRCAM_INFO_WOL_UC : 0) |
((a_info.wol_magic) ? FWCMD_H2C_ADDRCAM_INFO_WOL_MAGIC : 0) |
((a_info.wapi) ? FWCMD_H2C_ADDRCAM_INFO_WAPI : 0) |
SET_WORD(a_info.sec_ent_mode, FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_MODE) |
SET_WORD(a_info.sec_ent_keyid[0],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0_KEYID) |
SET_WORD(a_info.sec_ent_keyid[1],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1_KEYID) |
SET_WORD(a_info.sec_ent_keyid[2],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2_KEYID) |
SET_WORD(a_info.sec_ent_keyid[3],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3_KEYID) |
SET_WORD(a_info.sec_ent_keyid[4],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4_KEYID) |
SET_WORD(a_info.sec_ent_keyid[5],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5_KEYID) |
SET_WORD(a_info.sec_ent_keyid[6],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6_KEYID));
fw_addrcam->dword10 =
cpu_to_le32(SET_WORD(a_info.sec_ent_valid,
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT_VALID) |
SET_WORD(a_info.sec_ent[0], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT0) |
SET_WORD(a_info.sec_ent[1], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT1) |
SET_WORD(a_info.sec_ent[2], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT2));
fw_addrcam->dword11 =
cpu_to_le32(SET_WORD(a_info.sec_ent[3],
FWCMD_H2C_ADDRCAM_INFO_SEC_ENT3) |
SET_WORD(a_info.sec_ent[4], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT4) |
SET_WORD(a_info.sec_ent[5], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT5) |
SET_WORD(a_info.sec_ent[6], FWCMD_H2C_ADDRCAM_INFO_SEC_ENT6));
return MACSUCCESS;
}
u32 fill_bssid_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *role_info,
struct fwcmd_addrcam_info *fw_addrcam)
{
struct mac_ax_bssid_cam_info b_info = role_info->b_info;
fw_addrcam->dword12 =
cpu_to_le32(SET_WORD(b_info.bssid_cam_idx,
FWCMD_H2C_ADDRCAM_INFO_B_IDX) |
SET_WORD(b_info.offset, FWCMD_H2C_ADDRCAM_INFO_B_OFFSET) |
SET_WORD(b_info.len, FWCMD_H2C_ADDRCAM_INFO_B_LEN));
fw_addrcam->dword13 =
cpu_to_le32(((b_info.valid) ? FWCMD_H2C_ADDRCAM_INFO_B_VALID : 0) |
((b_info.bb_sel) ? FWCMD_H2C_ADDRCAM_INFO_B_BB_SEL : 0) |
SET_WORD(b_info.bss_color, FWCMD_H2C_ADDRCAM_INFO_BSS_COLOR) |
SET_WORD(b_info.bssid[0], FWCMD_H2C_ADDRCAM_INFO_BSSID0) |
SET_WORD(b_info.bssid[1], FWCMD_H2C_ADDRCAM_INFO_BSSID1));
fw_addrcam->dword14 =
cpu_to_le32(SET_WORD(b_info.bssid[2], FWCMD_H2C_ADDRCAM_INFO_BSSID2) |
SET_WORD(b_info.bssid[3], FWCMD_H2C_ADDRCAM_INFO_BSSID3) |
SET_WORD(b_info.bssid[4], FWCMD_H2C_ADDRCAM_INFO_BSSID4) |
SET_WORD(b_info.bssid[5], FWCMD_H2C_ADDRCAM_INFO_BSSID5));
return MACSUCCESS;
}
u32 mac_upd_addr_cam(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
enum mac_ax_role_opmode op)
{
u32 tbl[21];
u32 ret;
u32 i;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct fwcmd_addrcam_info *fwcmd_tbl;
u8 ctlinfo_aidx_off;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_addrcam_info));
if (!buf) {
ret = MACNOBUF;
goto FWOFLD_END;
}
fwcmd_tbl = (struct fwcmd_addrcam_info *)buf;
if (op == CHG)
ret = change_addr_cam_info(adapter, info, fwcmd_tbl);
else
ret = init_addr_cam_info(adapter, info, fwcmd_tbl);
if (ret)
goto FWOFLD_END;
// dword 0
ret = h2c_pkt_set_hdr(adapter,
h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_ADDR_CAM_UPDATE,
FWCMD_H2C_FUNC_ADDRCAM_INFO,
0,
1);
if (ret)
goto FWOFLD_END;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto FWOFLD_END;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
FWOFLD_END:
h2cb_free(adapter, h2cb);
if (!ret)
h2c_end_flow(adapter);
return ret;
}
if (op == CHG)
ret = change_addr_cam_info(adapter,
info,
(struct fwcmd_addrcam_info *)
tbl);
else
ret = init_addr_cam_info(adapter, info,
(struct fwcmd_addrcam_info *)
tbl);
if (ret)
return ret;
// Indirect write addr cam
for (i = 0; i < (u32)((info->a_info.len)) / 4; i++)
mac_sram_dbg_write(adapter, (info->a_info.addr_cam_idx *
info->a_info.len) + (i * 4),
le32_to_cpu(tbl[i + 2]), ADDR_CAM_SEL);
// Indirect write BSSID cam
for (i = 0; i < (u32)((info->b_info.len)) / 4; i++)
mac_sram_dbg_write(adapter, (info->b_info.bssid_cam_idx *
info->b_info.len) + (i * 4),
le32_to_cpu(tbl[i + 13]), BSSID_CAM_SEL);
// Indirect write cmac table addr cam idx
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
ctlinfo_aidx_off = 0x18;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
ctlinfo_aidx_off = 0x18;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
ctlinfo_aidx_off = 0x17;
else
ctlinfo_aidx_off = 0xFF;
PLTFM_MSG_WARN("%s ind access cmac tbl start\n", __func__);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W8(R_AX_INDIR_ACCESS_ENTRY +
info->macid * CCTL_INFO_SIZE + ctlinfo_aidx_off,
info->a_info.addr_cam_idx);
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access cmac tbl end\n", __func__);
return MACSUCCESS;
}
static void addr_cam_opt_2_uint(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *opt,
u32 *val32)
{
*val32 = ((opt->addrcam_en) ? B_AX_ADDR_CAM_EN : 0) |
((opt->srch_per_mpdu) ? B_AX_ADDR_CAM_SRCH_PERPKT : 0) |
((opt->a2_bit0_cmp_en) ? B_AX_ADDR_CAM_A2_B0_CHK : 0) |
//opt->clr_all_content) ? B_AX_ADDR_CAM_CLR: 0) |
SET_WORD(opt->srch_time_lmt, B_AX_ADDR_CAM_CMPLIMT) |
SET_WORD(opt->srch_range_lmt, B_AX_ADDR_CAM_RANGE);
}
static void addr_cam_dis_opt_2_uint(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *opt,
u32 *val32)
{
*val32 = SET_WORD(opt->def_hit_idx, B_AX_ADDR_CAM_DIS_IDX) |
((opt->def_hit_result) ? B_AX_ADDR_CAM_DIS_CAM_HIT : 0) |
((opt->def_a1_hit_result) ? B_AX_ADDR_CAM_DIS_A1_HIT : 0) |
((opt->def_a2_hit_result) ? B_AX_ADDR_CAM_DIS_A2_HIT : 0) |
((opt->def_a3_hit_result) ? B_AX_ADDR_CAM_DIS_A3_HIT : 0) |
SET_WORD(opt->def_port, B_AX_ADDR_CAM_DIS_PORT) |
SET_WORD(opt->def_sec_idx, B_AX_ADDR_CAM_DIS_SEC_IDX) |
SET_WORD(opt->def_macid, B_AX_ADDR_CAM_DIS_MACID);
}
u32 mac_get_cfg_addr_cam(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *opt,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
if (!opt) {
PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__);
return MACNPTR;
}
val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return val32;
}
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL);
opt->addrcam_en = ((val32 & B_AX_ADDR_CAM_EN) != 0);
opt->srch_per_mpdu = ((val32 & B_AX_ADDR_CAM_SRCH_PERPKT) != 0);
opt->a2_bit0_cmp_en = ((val32 & B_AX_ADDR_CAM_A2_B0_CHK) != 0);
opt->srch_time_lmt = GET_FIELD(val32, B_AX_ADDR_CAM_CMPLIMT);
opt->srch_range_lmt = GET_FIELD(val32, B_AX_ADDR_CAM_RANGE);
return MACSUCCESS;
}
u32 mac_get_cfg_addr_cam_dis(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *opt,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
if (!opt) {
PLTFM_MSG_ERR("[ERR]%s opt is null\n", __func__);
return MACNPTR;
}
val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (val32 != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return val32;
}
val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ?
R_AX_ADDR_CAM_DIS_INFO_C1 :
R_AX_ADDR_CAM_DIS_INFO);
opt->def_hit_idx = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_IDX);
opt->def_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_CAM_HIT) != 0);
opt->def_a1_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_A1_HIT) != 0);
opt->def_a2_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_A2_HIT) != 0);
opt->def_a3_hit_result = ((val32 & B_AX_ADDR_CAM_DIS_A3_HIT) != 0);
opt->def_port = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_PORT);
opt->def_sec_idx = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_SEC_IDX);
opt->def_macid = GET_FIELD(val32, B_AX_ADDR_CAM_DIS_MACID);
return MACSUCCESS;
}
u32 mac_cfg_addr_cam(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *ctl_opt,
struct mac_ax_addrcam_ctrl_t *ctl_msk,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_addrcam_ctrl_t opt = {0};
u32 ctl_opt_val;
u32 ctl_msk_val;
u32 opt_val;
u32 reg;
u32 cnt;
u32 ret = MACSUCCESS;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return ret;
}
reg = (band == MAC_AX_BAND_1) ?
R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL;
mac_get_cfg_addr_cam(adapter, &opt, band);
addr_cam_opt_2_uint(adapter, ctl_opt, &ctl_opt_val);
addr_cam_opt_2_uint(adapter, ctl_msk, &ctl_msk_val);
addr_cam_opt_2_uint(adapter, &opt, &opt_val);
opt_val = (ctl_opt_val & ctl_msk_val) |
(~(~ctl_opt_val & ctl_msk_val) & opt_val);
MAC_REG_W32(reg, opt_val);
if (ctl_opt->clr_all_content & ctl_msk->clr_all_content) {
opt_val |= B_AX_ADDR_CAM_CLR;
MAC_REG_W32(reg, opt_val);
cnt = TRXCFG_WAIT_CNT;
while (cnt--) {
if (!(MAC_REG_R16(reg) & B_AX_ADDR_CAM_CLR))
break;
PLTFM_DELAY_US(TRXCFG_WAIT_US);
}
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]ADDR_CAM reset\n");
return MACPOLLTO;
}
}
return MACSUCCESS;
}
u32 mac_cfg_addr_cam_dis(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *ctl_opt,
struct mac_ax_addrcam_dis_ctrl_t *ctl_msk,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_addrcam_dis_ctrl_t opt = {0};
u32 ctl_opt_val;
u32 ctl_msk_val;
u32 opt_val;
u32 reg;
u32 ret = MACSUCCESS;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, band);
return ret;
}
reg = (band == MAC_AX_BAND_1) ?
R_AX_ADDR_CAM_DIS_INFO_C1 : R_AX_ADDR_CAM_DIS_INFO;
mac_get_cfg_addr_cam_dis(adapter, &opt, band);
addr_cam_dis_opt_2_uint(adapter, ctl_opt, &ctl_opt_val);
addr_cam_dis_opt_2_uint(adapter, ctl_msk, &ctl_msk_val);
addr_cam_dis_opt_2_uint(adapter, &opt, &opt_val);
opt_val = (ctl_opt_val & ctl_msk_val) |
(~(~ctl_opt_val & ctl_msk_val) & opt_val);
MAC_REG_W32(reg, opt_val);
return MACSUCCESS;
}
u32 addr_cam_init(struct mac_ax_adapter *adapter,
enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, reg;
u32 cnt = TRXCFG_WAIT_CNT;
u32 ret;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg = band == MAC_AX_BAND_1 ?
R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL;
val32 = MAC_REG_R32(reg);
val32 |= (SET_WORD(ADDR_CAM_SERCH_RANGE, B_AX_ADDR_CAM_RANGE) |
B_AX_ADDR_CAM_EN);
if (band == MAC_AX_BAND_0)
val32 |= B_AX_ADDR_CAM_CLR;
MAC_REG_W32(reg, val32);
cnt = TRXCFG_WAIT_CNT;
while (cnt--) {
if (!(MAC_REG_R16(band == MAC_AX_BAND_1 ?
R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL)
& B_AX_ADDR_CAM_CLR))
break;
PLTFM_DELAY_US(TRXCFG_WAIT_US);
}
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]ADDR_CAM reset\n");
return MACPOLLTO;
}
return MACSUCCESS;
}
static u32 _set_mac_resp_ack(struct mac_ax_adapter *adapter, u32 ack, u8 band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
u32 val32;
u32 offset_ctrl = band ? R_AX_ADDR_CAM_CTRL_C1 : R_AX_ADDR_CAM_CTRL;
u32 offset_hit = band ? R_AX_ADDR_CAM_DIS_INFO_C1 :
R_AX_ADDR_CAM_DIS_INFO;
if (ack) {
val8 = MAC_REG_R8(offset_ctrl);
MAC_REG_W8(offset_ctrl, val8 | B_AX_ADDR_CAM_EN);
} else {
val8 = MAC_REG_R8(offset_ctrl);
MAC_REG_W8(offset_ctrl, val8 & ~B_AX_ADDR_CAM_EN);
val32 = MAC_REG_R32(offset_hit);
val32 = SET_CLR_WORD(val32, MAC_AX_NO_HIT_IDX,
B_AX_ADDR_CAM_DIS_IDX);
val32 &= ~(B_AX_ADDR_CAM_DIS_CAM_HIT |
B_AX_ADDR_CAM_DIS_A1_HIT);
MAC_REG_W32(offset_hit, val32);
}
return MACSUCCESS;
}
#if MAC_AX_FW_REG_OFLD
u32 set_mac_do_resp_ack_ofld(struct mac_ax_adapter *adapter)
{
u32 ret;
u8 cmac1_en;
cmac1_en = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS ?
1 : 0;
ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL, B_AX_ADDR_CAM_EN,
1, cmac1_en ? 0 : 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
if (cmac1_en) {
ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL_C1,
B_AX_ADDR_CAM_EN,
1, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
}
return MACSUCCESS;
}
u32 set_mac_not_resp_ack_ofld(struct mac_ax_adapter *adapter)
{
u32 ret, msk;
u8 cmac1_en;
cmac1_en = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS ?
1 : 0;
/* set 0xCE34[0] = 0 */
ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL, B_AX_ADDR_CAM_EN,
0, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
/* set 0xCE38[9:0] = 0xFF */
msk = (B_AX_ADDR_CAM_DIS_IDX_MSK << B_AX_ADDR_CAM_DIS_IDX_SH) |
B_AX_ADDR_CAM_DIS_A1_HIT |
B_AX_ADDR_CAM_DIS_CAM_HIT;
ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_DIS_INFO, msk,
MAC_AX_NO_HIT_IDX, cmac1_en ? 0 : 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
if (cmac1_en) {
ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_CTRL_C1, B_AX_ADDR_CAM_EN,
0, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_ADDR_CAM_DIS_INFO_C1, msk,
MAC_AX_NO_HIT_IDX, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
}
return MACSUCCESS;
}
u32 set_mac_resp_ack_ofld(struct mac_ax_adapter *adapter, u32 ack)
{
u32 ret;
if (ack)
ret = set_mac_do_resp_ack_ofld(adapter);
else
ret = set_mac_not_resp_ack_ofld(adapter);
return ret;
}
#endif
u32 set_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack)
{
u32 ret;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY)
return ret = set_mac_resp_ack_ofld(adapter, *ack);
#endif
ret = _set_mac_resp_ack(adapter, *ack, 0);
if (ret == MACSUCCESS &&
check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS)
ret = _set_mac_resp_ack(adapter, *ack, 1);
return ret;
}
u32 get_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack)
{
#define MAC_AX_ACK_CMAC1_SH 1
#define MAC_AX_ACK_CMAC0_SH 0
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 cmac0 = 0, cmac1 = 0;
cmac0 = !!(MAC_REG_R8(R_AX_ADDR_CAM_CTRL) & B_AX_ADDR_CAM_EN);
if (check_mac_en(adapter, 1, MAC_AX_CMAC_SEL) == MACSUCCESS)
cmac1 = !!(MAC_REG_R8(R_AX_ADDR_CAM_CTRL_C1) &
B_AX_ADDR_CAM_EN);
*ack = cmac0 << MAC_AX_ACK_CMAC0_SH | cmac1 << MAC_AX_ACK_CMAC1_SH;
return MACSUCCESS;
}
u8 get_addr_cam_size(struct mac_ax_adapter *adapter)
{
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
return ADDR_CAM_ENT_LONG_SIZE;
else
return ADDR_CAM_ENT_SHORT_SIZE;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/addr_cam.c
|
C
|
agpl-3.0
| 22,352
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_ADDR_CAM_H_
#define _MAC_AX_ADDR_CAM_H_
#include "../type.h"
#include "fwcmd.h"
#include "../fw_ax/inc_hdr/fwcmd_intf.h"
#define ADDR_CAM_ENT_LONG_SIZE 0x40
#define ADDR_CAM_ENT_SHORT_SIZE 0x20
#define BSSID_CAM_ENT_SIZE 0x08
#define ETH_ALEN 6
#define DEFAULT_HIT_MACID 0x0
#define ADDR_CAM_SERCH_RANGE 0x7f
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief addr_cam_init
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 addr_cam_init(struct mac_ax_adapter *adapter,
enum mac_ax_band band);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief addr_cam_init
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_cfg_addr_cam(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *opt,
enum mac_ax_band band);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief addr_cam_init
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_cfg_addr_cam_dis(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *opt,
enum mac_ax_band band);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief mac_cfg_addrcam
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_addr_cam(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_ctrl_t *ctl_opt,
struct mac_ax_addrcam_ctrl_t *ctl_msk,
enum mac_ax_band band);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief mac_cfg_addrcam_dis
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_addr_cam_dis(struct mac_ax_adapter *adapter,
struct mac_ax_addrcam_dis_ctrl_t *ctl_opt,
struct mac_ax_addrcam_dis_ctrl_t *ctl_msk,
enum mac_ax_band band);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief fill_addr_cam_info
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 fill_addr_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief fill_bssid_cam_info
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 fill_bssid_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief init_addr_cam_info
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 init_addr_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief change_addr_cam_info
*
* @param *adapter
* @param *info
* @param *fw_addrcam
* @return Please Place Description here.
* @retval u32
*/
u32 change_addr_cam_info(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
struct fwcmd_addrcam_info *fw_addrcam);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief mac_upd_addr_cam
*
* @param *adapter
* @param *info
* @param change_role
* @return Please Place Description here.
* @retval u32
*/
u32 mac_upd_addr_cam(struct mac_ax_adapter *adapter,
struct mac_ax_role_info *info,
enum mac_ax_role_opmode op);
/**
* @}
* @}
*/
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief set_mac_resp_ack
*
* The function could contrl MAC resp ACK or not.
*
* @param *adapter
* @param ack
* @return 0 for success. Others are fail.
* @retval u32
*/
u32 set_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack);
/**
* @}
* @}
*/
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief get_mac_resp_ack
*
* The function could get MAC resp ACK ability
*
* @param *adapter
* @param ack
* @return 0 for success. Others are fail.
* @retval u32
*/
u32 get_mac_resp_ack(struct mac_ax_adapter *adapter, u32 *ack);
/**
* @}
* @}
*/
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup ADDRCAM
* @{
*/
/**
* @brief get_addr_cam_size
*
* Get the entry size of address CAM
*
* @param *adapter
* @return ret the size of address CAM.
* @retval u32
*/
u8 get_addr_cam_size(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/addr_cam.h
|
C
|
agpl-3.0
| 5,752
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "cmac_tx.h"
#define PTCL_IDLE_POLL_CNT 2200
#define SW_CVR_DUR_US 30
#define SW_CVR_CNT 8
#define TX_DLY_MAX 9
static u32 stop_macid_ctn(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role,
struct mac_ax_sch_tx_en_cfg *bak);
static u32 tx_idle_ck(struct mac_ax_adapter *adapter, u8 band);
static u32 tx_idle_sel_ck(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel,
u8 band);
static u32 tx_idle_sel_ck_b(struct mac_ax_adapter *adapter,
enum ptcl_tx_sel sel, u8 band);
static u32 macid_idle_ck(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role);
static u32 band_idle_ck(struct mac_ax_adapter *adapter, u8 band);
static void tx_on_dly(struct mac_ax_adapter *adapter, u8 band);
static void sch_2_u16(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en *tx_en, u16 *val16);
static void u16_2_sch(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en *tx_en, u16 val16);
static u32 h2c_usr_edca(struct mac_ax_adapter *adapter,
struct mac_ax_usr_edca_param *param);
static u32 h2c_usr_tx_rpt(struct mac_ax_adapter *adapter,
struct mac_ax_usr_tx_rpt_cfg *cfg);
static u32 tx_duty_h2c(struct mac_ax_adapter *adapter,
u16 pause_intvl, u16 tx_intvl);
u32 set_hw_ampdu_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_ampdu_cfg *cfg)
{
u16 max_agg_num;
u8 max_agg_time;
u8 band;
u32 ret;
u32 bk_addr, agg_addr;
u32 val32;
u8 val8;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
band = cfg->band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
max_agg_num = cfg->max_agg_num;
max_agg_time = cfg->max_agg_time_32us;
bk_addr = band ? R_AX_AGG_BK_0_C1 : R_AX_AGG_BK_0;
agg_addr = band ? R_AX_AMPDU_AGG_LIMIT_C1 : R_AX_AMPDU_AGG_LIMIT;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
switch (cfg->wdbk_mode) {
case MAC_AX_WDBK_MODE_SINGLE_BK:
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_WDBK_CFG, 0, 0);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_WDBK_MODE_GRP_BK:
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_WDBK_CFG, 1, 0);
if (ret != MACSUCCESS)
return ret;
break;
default:
return MACNOITEM;
}
switch (cfg->rty_bk_mode) {
case MAC_AX_RTY_BK_MODE_AGG:
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK, 0, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK_COD,
0, 0);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_RTY_BK_MODE_RATE_FB:
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK, 0, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK_COD,
1, 0);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_RTY_BK_MODE_BK:
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK, 1, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W_OFLD((u16)bk_addr, B_AX_EN_RTY_BK_COD,
1, 0);
if (ret != MACSUCCESS)
return ret;
break;
default:
return MACNOITEM;
}
val32 = 0;
if (max_agg_num > 0 && max_agg_num <= 0x100) {
ret = MAC_REG_W_OFLD((u16)agg_addr,
GET_MSK(B_AX_MAX_AGG_NUM),
max_agg_num - 1, 0);
if (ret != MACSUCCESS)
return ret;
} else {
return MACSETVALERR;
}
if (max_agg_time > 0 && max_agg_time <= 0xA5) {
ret = MAC_REG_W_OFLD((u16)agg_addr,
(u32)GET_MSK(B_AX_AMPDU_MAX_TIME),
max_agg_time, 1);
if (ret != MACSUCCESS)
return ret;
} else {
return MACSETVALERR;
}
return MACSUCCESS;
}
#endif
val8 = MAC_REG_R8(bk_addr);
switch (cfg->wdbk_mode) {
case MAC_AX_WDBK_MODE_SINGLE_BK:
val8 &= ~B_AX_WDBK_CFG;
break;
case MAC_AX_WDBK_MODE_GRP_BK:
val8 |= B_AX_WDBK_CFG;
break;
default:
return MACNOITEM;
}
switch (cfg->rty_bk_mode) {
case MAC_AX_RTY_BK_MODE_AGG:
val8 &= ~(B_AX_EN_RTY_BK | B_AX_EN_RTY_BK_COD);
break;
case MAC_AX_RTY_BK_MODE_RATE_FB:
val8 &= ~(B_AX_EN_RTY_BK);
val8 |= B_AX_EN_RTY_BK_COD;
break;
case MAC_AX_RTY_BK_MODE_BK:
val8 |= B_AX_EN_RTY_BK | B_AX_EN_RTY_BK_COD;
break;
default:
return MACNOITEM;
}
MAC_REG_W8(bk_addr, val8);
val32 = MAC_REG_R32(agg_addr);
if (max_agg_num > 0 && max_agg_num <= 0x100)
val32 = SET_CLR_WORD(val32, max_agg_num - 1, B_AX_MAX_AGG_NUM);
else
return MACSETVALERR;
if (max_agg_time > 0 && max_agg_time <= 0xA5)
val32 = SET_CLR_WORD(val32, max_agg_time, B_AX_AMPDU_MAX_TIME);
else
return MACSETVALERR;
MAC_REG_W32(agg_addr, val32);
return MACSUCCESS;
}
u32 set_hw_usr_tx_rpt_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_usr_tx_rpt_cfg *cfg)
{
u32 ret;
ret = h2c_usr_tx_rpt(adapter, cfg);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 set_hw_usr_edca_param(struct mac_ax_adapter *adapter,
struct mac_ax_usr_edca_param *param)
{
u32 ret;
ret = h2c_usr_edca(adapter, param);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 set_hw_edca_param(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param)
{
u32 val32;
u32 reg_edca;
u32 ret;
u16 val16;
enum mac_ax_cmac_path_sel path;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
ret = get_edca_addr(adapter, param, ®_edca);
if (ret != MACSUCCESS)
return ret;
path = param->path;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
if (path == MAC_AX_CMAC_PATH_SEL_MG0_1 ||
path == MAC_AX_CMAC_PATH_SEL_MG2 ||
path == MAC_AX_CMAC_PATH_SEL_BCN) {
val16 = SET_WORD((param->ecw_max << 4) | param->ecw_min,
B_AX_BE_0_CW) |
SET_WORD(param->aifs_us, B_AX_BE_0_AIFS);
ret = MAC_REG_W16_OFLD((u16)reg_edca, val16, 1);
if (ret != MACSUCCESS)
return ret;
} else {
val32 = SET_WORD(param->txop_32us, B_AX_BE_0_TXOPLMT) |
SET_WORD((param->ecw_max << 4) | param->ecw_min,
B_AX_BE_0_CW) |
SET_WORD(param->aifs_us, B_AX_BE_0_AIFS);
ret = MAC_REG_W32_OFLD((u16)reg_edca, val32, 1);
if (ret != MACSUCCESS)
return ret;
}
return MACSUCCESS;
}
#endif
if (path == MAC_AX_CMAC_PATH_SEL_MG0_1 ||
path == MAC_AX_CMAC_PATH_SEL_MG2 ||
path == MAC_AX_CMAC_PATH_SEL_BCN) {
val16 = SET_WORD((param->ecw_max << 4) | param->ecw_min,
B_AX_BE_0_CW) |
SET_WORD(param->aifs_us, B_AX_BE_0_AIFS);
MAC_REG_W16(reg_edca, val16);
} else {
val32 = SET_WORD(param->txop_32us, B_AX_BE_0_TXOPLMT) |
SET_WORD((param->ecw_max << 4) | param->ecw_min,
B_AX_BE_0_CW) |
SET_WORD(param->aifs_us, B_AX_BE_0_AIFS);
MAC_REG_W32(reg_edca, val32);
}
return MACSUCCESS;
}
u32 get_hw_edca_param(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param)
{
u32 val32;
u32 reg_edca;
u32 ret;
u16 val16;
enum mac_ax_cmac_path_sel path;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
ret = get_edca_addr(adapter, param, ®_edca);
if (ret != MACSUCCESS)
return ret;
path = param->path;
if (path == MAC_AX_CMAC_PATH_SEL_MG0_1 ||
path == MAC_AX_CMAC_PATH_SEL_MG2 ||
path == MAC_AX_CMAC_PATH_SEL_BCN) {
val16 = MAC_REG_R16(reg_edca);
param->txop_32us = 0;
param->aifs_us = GET_FIELD(val16, B_AX_BE_0_AIFS);
param->ecw_max = (GET_FIELD(val16, B_AX_BE_0_CW) & 0xF0) >> 4;
param->ecw_min = GET_FIELD(val16, B_AX_BE_0_CW) & 0x0F;
} else {
val32 = MAC_REG_R32(reg_edca);
param->txop_32us = GET_FIELD(val32, B_AX_BE_0_TXOPLMT);
param->aifs_us = GET_FIELD(val32, B_AX_BE_0_AIFS);
param->ecw_max = (GET_FIELD(val32, B_AX_BE_0_CW) & 0xF0) >> 4;
param->ecw_min = GET_FIELD(val32, B_AX_BE_0_CW) & 0x0F;
}
return MACSUCCESS;
}
u32 set_hw_edcca_param(struct mac_ax_adapter *adapter,
struct mac_ax_edcca_param *param)
{
u32 reg_cca_ctl = 0;
u32 ret;
enum mac_ax_edcca_sel sel;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL);
if (ret)
return ret;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
sel = param->sel;
if (sel == MAC_AX_EDCCA_IN_TB_CHK) {
if (param->tb_check_en)
reg_cca_ctl |= B_AX_TB_CHK_EDCCA;
else
reg_cca_ctl &= ~B_AX_TB_CHK_EDCCA;
}
if (sel == MAC_AX_EDCCA_IN_SIFS_CHK) {
if (param->sifs_check_en)
reg_cca_ctl |= B_AX_SIFS_CHK_EDCCA;
else
reg_cca_ctl &= ~B_AX_SIFS_CHK_EDCCA;
}
if (sel == MAC_AX_EDCCA_IN_CTN_CHK) {
if (param->ctn_check_en)
reg_cca_ctl |= B_AX_CTN_CHK_EDCCA;
else
reg_cca_ctl &= ~B_AX_CTN_CHK_EDCCA;
} else {
return MACNOITEM;
}
if (param->band)
ret = MAC_REG_W32_OFLD((u16)R_AX_CCA_CONTROL_C1,
reg_cca_ctl, 1);
else
ret = MAC_REG_W32_OFLD((u16)R_AX_CCA_CONTROL,
reg_cca_ctl, 1);
return ret;
}
#endif
if (param->band)
reg_cca_ctl = MAC_REG_R32(R_AX_CCA_CONTROL_C1);
else
reg_cca_ctl = MAC_REG_R32(R_AX_CCA_CONTROL);
sel = param->sel;
if (sel == MAC_AX_EDCCA_IN_TB_CHK) {
if (param->tb_check_en)
reg_cca_ctl |= B_AX_TB_CHK_EDCCA;
else
reg_cca_ctl &= ~B_AX_TB_CHK_EDCCA;
}
if (sel == MAC_AX_EDCCA_IN_SIFS_CHK) {
if (param->sifs_check_en)
reg_cca_ctl |= B_AX_SIFS_CHK_EDCCA;
else
reg_cca_ctl &= ~B_AX_SIFS_CHK_EDCCA;
}
if (sel == MAC_AX_EDCCA_IN_CTN_CHK) {
if (param->ctn_check_en)
reg_cca_ctl |= B_AX_CTN_CHK_EDCCA;
else
reg_cca_ctl &= ~B_AX_CTN_CHK_EDCCA;
} else {
return MACNOITEM;
}
if (param->band)
MAC_REG_W32(R_AX_CCA_CONTROL_C1, reg_cca_ctl);
else
MAC_REG_W32(R_AX_CCA_CONTROL, reg_cca_ctl);
return MACSUCCESS;
}
u32 set_hw_muedca_param(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_param *param)
{
u32 val32;
u32 reg_edca;
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, param->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
ret = get_muedca_param_addr(adapter, param, ®_edca);
if (ret != MACSUCCESS)
return ret;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
val32 = SET_WORD(param->muedca_timer_32us,
B_AX_MUEDCA_BE_PARAM_0_TIMER) |
SET_WORD((param->ecw_max << 4) | param->ecw_min,
B_AX_MUEDCA_BE_PARAM_0_CW) |
SET_WORD(param->aifs_us, B_AX_MUEDCA_BE_PARAM_0_AIFS);
ret = MAC_REG_W32_OFLD((u16)reg_edca, val32, 1);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
#endif
val32 = SET_WORD(param->muedca_timer_32us,
B_AX_MUEDCA_BE_PARAM_0_TIMER) |
SET_WORD((param->ecw_max << 4) | param->ecw_min,
B_AX_MUEDCA_BE_PARAM_0_CW) |
SET_WORD(param->aifs_us, B_AX_MUEDCA_BE_PARAM_0_AIFS);
MAC_REG_W32(reg_edca, val32);
return MACSUCCESS;
}
u32 set_hw_muedca_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_cfg *cfg)
{
u32 ret;
u8 band;
u16 val16;
u32 reg_en;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
band = cfg->band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg_en = band ? R_AX_MUEDCA_EN_C1 : R_AX_MUEDCA_EN;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
val16 = 0;
if (cfg->wmm_sel == MAC_AX_CMAC_WMM1_SEL) {
ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MUEDCA_WMM_SEL,
1, 0);
if (ret != MACSUCCESS)
return ret;
} else {
ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MUEDCA_WMM_SEL,
0, 0);
if (ret != MACSUCCESS)
return ret;
}
ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MUEDCA_EN_0,
cfg->countdown_en, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_SET_MUEDCATIMER_TF_0,
cfg->tb_update_en, 1);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
#endif
val16 = MAC_REG_R16(reg_en);
if (cfg->wmm_sel == MAC_AX_CMAC_WMM1_SEL)
val16 |= B_AX_MUEDCA_WMM_SEL;
else
val16 &= ~B_AX_MUEDCA_WMM_SEL;
if (cfg->countdown_en)
val16 |= B_AX_MUEDCA_EN_0;
else
val16 &= ~B_AX_MUEDCA_EN_0;
if (cfg->tb_update_en)
val16 |= B_AX_SET_MUEDCATIMER_TF_0;
else
val16 &= ~B_AX_SET_MUEDCATIMER_TF_0;
MAC_REG_W16(reg_en, val16);
return MACSUCCESS;
}
u32 set_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_tb_ppdu_ctrl *ctrl)
{
u16 val16;
u8 pri_ac;
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, ctrl->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
switch (ctrl->pri_ac) {
case MAC_AX_CMAC_AC_SEL_BE:
pri_ac = 0;
break;
case MAC_AX_CMAC_AC_SEL_BK:
pri_ac = 1;
break;
case MAC_AX_CMAC_AC_SEL_VI:
pri_ac = 2;
break;
case MAC_AX_CMAC_AC_SEL_VO:
pri_ac = 3;
break;
default:
return MACNOITEM;
}
val16 = MAC_REG_R16(ctrl->band ? R_AX_TB_PPDU_CTRL_C1 :
R_AX_TB_PPDU_CTRL);
val16 &= ~(B_AX_TB_PPDU_BE_DIS | B_AX_TB_PPDU_BK_DIS |
B_AX_TB_PPDU_VI_DIS | B_AX_TB_PPDU_VO_DIS);
val16 |= (ctrl->be_dis ? B_AX_TB_PPDU_BE_DIS : 0) |
(ctrl->bk_dis ? B_AX_TB_PPDU_BK_DIS : 0) |
(ctrl->vi_dis ? B_AX_TB_PPDU_VI_DIS : 0) |
(ctrl->vo_dis ? B_AX_TB_PPDU_VO_DIS : 0);
val16 = SET_CLR_WORD(val16, pri_ac, B_AX_SW_PREFER_AC);
MAC_REG_W16(ctrl->band ? R_AX_TB_PPDU_CTRL_C1 : R_AX_TB_PPDU_CTRL,
val16);
return MACSUCCESS;
}
u32 get_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_tb_ppdu_ctrl *ctrl)
{
u16 val16;
u8 pri_ac;
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, ctrl->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val16 = MAC_REG_R16(ctrl->band ? R_AX_TB_PPDU_CTRL_C1 :
R_AX_TB_PPDU_CTRL);
ctrl->be_dis = (val16 & B_AX_TB_PPDU_BE_DIS) ? 1 : 0;
ctrl->bk_dis = (val16 & B_AX_TB_PPDU_BK_DIS) ? 1 : 0;
ctrl->vi_dis = (val16 & B_AX_TB_PPDU_VI_DIS) ? 1 : 0;
ctrl->vo_dis = (val16 & B_AX_TB_PPDU_VO_DIS) ? 1 : 0;
pri_ac = GET_FIELD(val16, B_AX_SW_PREFER_AC);
switch (pri_ac) {
case 0:
ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_BE;
break;
case 1:
ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_BK;
break;
case 2:
ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_VI;
break;
case 3:
ctrl->pri_ac = MAC_AX_CMAC_AC_SEL_VO;
break;
}
return MACSUCCESS;
}
u32 set_hw_sch_tx_en(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *cfg)
{
u16 val16;
u8 band;
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u16 tx_en_u16;
u16 mask_u16;
struct mac_ax_sch_tx_en tx_en;
struct mac_ax_sch_tx_en tx_en_mask;
u8 chip_id = adapter->hw_info->chip_id;
band = cfg->band;
tx_en = cfg->tx_en;
tx_en_mask = cfg->tx_en_mask;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
sch_2_u16(adapter, &tx_en, &tx_en_u16);
sch_2_u16(adapter, &tx_en_mask, &mask_u16);
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY ||
chip_id == MAC_AX_CHIP_ID_8852C ||
chip_id == MAC_AX_CHIP_ID_8192XB) {
val16 = MAC_REG_R16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN);
val16 = (tx_en_u16 & mask_u16) | (~(~tx_en_u16 & mask_u16) & val16);
MAC_REG_W16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN, val16);
} else {
hw_sch_tx_en(adapter, band, tx_en_u16, mask_u16);
}
return MACSUCCESS;
}
u32 hw_sch_tx_en(struct mac_ax_adapter *adapter, u8 band,
u16 tx_en_u16, u16 mask_u16)
{
#define RETRY_WAIT_US 1
u32 ret;
struct mac_ax_h2creg_info h2c = {0};
struct mac_ax_c2hreg_poll c2h = {0};
h2c.id = FWCMD_H2CREG_FUNC_SCH_TX_EN;
h2c.content_len = sizeof(struct sch_tx_en_h2creg);
h2c.h2c_content.dword0 =
SET_WORD(tx_en_u16, FWCMD_H2C_H2CREG_SCH_TX_PAUSE_TX_EN);
h2c.h2c_content.dword1 =
SET_WORD(mask_u16, FWCMD_H2C_H2CREG_SCH_TX_PAUSE_MASK) |
(band ? FWCMD_H2C_H2CREG_SCH_TX_PAUSE_BAND : 0);
c2h.polling_id = FWCMD_C2HREG_FUNC_TX_PAUSE_RPT;
c2h.retry_cnt = TX_PAUSE_WAIT_CNT;
c2h.retry_wait_us = RETRY_WAIT_US;
ret = proc_msg_reg(adapter, &h2c, &c2h);
if (ret) {
PLTFM_MSG_ERR("[ERR]hw sch tx_en proc msg reg %d\n", ret);
return ret;
}
return MACSUCCESS;
}
u32 get_hw_sch_tx_en(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *cfg)
{
u8 band;
u32 ret;
u16 val16;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_sch_tx_en tx_en;
band = cfg->band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val16 = MAC_REG_R16(band ? R_AX_CTN_TXEN_C1 : R_AX_CTN_TXEN);
u16_2_sch(adapter, &tx_en, val16);
cfg->tx_en = tx_en;
return MACSUCCESS;
}
u32 set_hw_lifetime_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_lifetime_cfg *cfg)
{
u32 ret;
u8 band;
u8 val8;
u32 val32;
u32 reg_time_0, reg_time_1, reg_time_2, reg_en;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
band = cfg->band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
reg_time_0 = band ? R_AX_LIFETIME_0_C1 : R_AX_LIFETIME_0;
reg_time_1 = band ? R_AX_LIFETIME_1_C1 : R_AX_LIFETIME_1;
reg_time_2 = band ? R_AX_LIFETIME_2_C1 : R_AX_LIFETIME_2;
reg_en = band ? R_AX_PTCL_COMMON_SETTING_0_C1 :
R_AX_PTCL_COMMON_SETTING_0;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
if (cfg->en.acq_en || cfg->en.mgq_en) {
ret = MAC_REG_W_OFLD(R_AX_TX_PASTE_TIMESTAMP_SETTING,
B_AX_HDT_TIMESTAMP_EN, 1, 0);
if (ret != MACSUCCESS)
return ret;
}
val32 = SET_WORD(cfg->val.acq_val_1, B_AX_PKT_LIFETIME_1) |
SET_WORD(cfg->val.acq_val_2, B_AX_PKT_LIFETIME_2);
ret = MAC_REG_W32_OFLD((u16)reg_time_0, val32, 0);
if (ret != MACSUCCESS)
return ret;
val32 = SET_WORD(cfg->val.acq_val_3, B_AX_PKT_LIFETIME_3) |
SET_WORD(cfg->val.acq_val_4, B_AX_PKT_LIFETIME_4);
ret = MAC_REG_W32_OFLD((u16)reg_time_1, val32, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W16_OFLD((u16)reg_time_2, cfg->val.mgq_val, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_LIFETIME_EN,
cfg->en.acq_en, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W_OFLD((u16)reg_en, B_AX_MGQ_LIFETIME_EN,
cfg->en.mgq_en, 1);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
#endif
if (cfg->en.acq_en || cfg->en.mgq_en)
MAC_REG_W8(R_AX_TX_PASTE_TIMESTAMP_SETTING,
MAC_REG_R8(R_AX_TX_PASTE_TIMESTAMP_SETTING) |
B_AX_HDT_TIMESTAMP_EN);
val32 = SET_WORD(cfg->val.acq_val_1, B_AX_PKT_LIFETIME_1) |
SET_WORD(cfg->val.acq_val_2, B_AX_PKT_LIFETIME_2);
MAC_REG_W32(reg_time_0, val32);
val32 = SET_WORD(cfg->val.acq_val_3, B_AX_PKT_LIFETIME_3) |
SET_WORD(cfg->val.acq_val_4, B_AX_PKT_LIFETIME_4);
MAC_REG_W32(reg_time_1, val32);
MAC_REG_W16(reg_time_2, cfg->val.mgq_val);
val8 = MAC_REG_R8(reg_en);
val8 &= ~(B_AX_LIFETIME_EN | B_AX_MGQ_LIFETIME_EN);
val8 |= (cfg->en.acq_en ? B_AX_LIFETIME_EN : 0) |
(cfg->en.mgq_en ? B_AX_MGQ_LIFETIME_EN : 0);
MAC_REG_W8(reg_en, val8);
return MACSUCCESS;
}
u32 get_hw_lifetime_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_lifetime_cfg *cfg)
{
u32 ret;
u8 band;
u8 val8;
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
band = cfg->band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val8 = MAC_REG_R8(band ? R_AX_PTCL_COMMON_SETTING_0_C1 :
R_AX_PTCL_COMMON_SETTING_0);
cfg->en.acq_en = (val8 & B_AX_LIFETIME_EN) ? 1 : 0;
cfg->en.mgq_en = (val8 & B_AX_MGQ_LIFETIME_EN) ? 1 : 0;
val32 = MAC_REG_R32(band ? R_AX_LIFETIME_0_C1 : R_AX_LIFETIME_0);
cfg->val.acq_val_1 = GET_FIELD(val32, B_AX_PKT_LIFETIME_1);
cfg->val.acq_val_2 = GET_FIELD(val32, B_AX_PKT_LIFETIME_2);
val32 = MAC_REG_R32(band ? R_AX_LIFETIME_1_C1 : R_AX_LIFETIME_1);
cfg->val.acq_val_3 = GET_FIELD(val32, B_AX_PKT_LIFETIME_3);
cfg->val.acq_val_4 = GET_FIELD(val32, B_AX_PKT_LIFETIME_4);
cfg->val.mgq_val = MAC_REG_R16(band ? R_AX_LIFETIME_2_C1 :
R_AX_LIFETIME_2);
return MACSUCCESS;
}
u32 stop_sch_tx(struct mac_ax_adapter *adapter, enum sch_tx_sel sel,
struct mac_ax_sch_tx_en_cfg *bak)
{
struct mac_ax_sch_tx_en_cfg cfg;
u32 ret;
ret = get_hw_sch_tx_en(adapter, bak);
if (ret != MACSUCCESS)
return ret;
cfg.band = bak->band;
u16_2_sch(adapter, &cfg.tx_en_mask, 0);
switch (sel) {
case SCH_TX_SEL_ALL:
u16_2_sch(adapter, &cfg.tx_en, 0);
u16_2_sch(adapter, &cfg.tx_en_mask, 0xFFFF);
ret = set_hw_sch_tx_en(adapter, &cfg);
if (ret != MACSUCCESS)
return ret;
break;
case SCH_TX_SEL_HIQ:
cfg.tx_en.hi = 0;
cfg.tx_en_mask.hi = 1;
ret = set_hw_sch_tx_en(adapter, &cfg);
if (ret != MACSUCCESS)
return ret;
break;
case SCH_TX_SEL_MG0:
cfg.tx_en.mg0 = 0;
cfg.tx_en_mask.mg0 = 1;
ret = set_hw_sch_tx_en(adapter, &cfg);
if (ret != MACSUCCESS)
return ret;
break;
case SCH_TX_SEL_MACID:
u16_2_sch(adapter, &cfg.tx_en, 0);
u16_2_sch(adapter, &cfg.tx_en_mask, 0xFFFF);
cfg.tx_en_mask.mg1 = 0;
cfg.tx_en_mask.mg2 = 0;
cfg.tx_en_mask.hi = 0;
cfg.tx_en_mask.bcn = 0;
ret = set_hw_sch_tx_en(adapter, &cfg);
if (ret != MACSUCCESS)
return ret;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 resume_sch_tx(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *bak)
{
u32 ret;
u16_2_sch(adapter, &bak->tx_en_mask, 0xFFFF);
ret = set_hw_sch_tx_en(adapter, bak);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 stop_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role,
enum tb_stop_sel stop_sel, struct macid_tx_bak *bak)
{
u8 band;
u32 ret;
struct mac_ax_macid_pause_cfg pause;
band = role->info.band;
if (role->info.a_info.tf_trs) {
bak->ac_dis_bak.band = band;
ret = stop_ac_tb_tx(adapter, stop_sel, &bak->ac_dis_bak);
if (ret != MACSUCCESS)
return ret;
}
pause.macid = role->macid;
pause.pause = 1;
ret = set_macid_pause(adapter, &pause);
if (ret != MACSUCCESS)
return ret;
bak->sch_bak.band = band;
ret = stop_macid_ctn(adapter, role, &bak->sch_bak);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 resume_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role,
struct macid_tx_bak *bak)
{
u32 ret;
struct mac_ax_macid_pause_cfg pause_cfg;
if (role->info.band == MAC_AX_BAND_0) {
u16_2_sch(adapter, &bak->sch_bak.tx_en_mask, 0xFFFF);
ret = set_hw_sch_tx_en(adapter, &bak->sch_bak);
if (ret != MACSUCCESS)
return ret;
}
if (role->info.a_info.tf_trs) {
ret = set_hw_tb_ppdu_ctrl(adapter, &bak->ac_dis_bak);
if (ret != MACSUCCESS)
return ret;
}
pause_cfg.macid = role->macid;
pause_cfg.pause = 0;
ret = set_macid_pause(adapter, &pause_cfg);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 tx_idle_poll_macid(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role)
{
return macid_idle_ck(adapter, role);
}
u32 tx_idle_poll_band(struct mac_ax_adapter *adapter, u8 band, u8 txop_aware)
{
if (txop_aware)
return tx_idle_ck(adapter, band);
return band_idle_ck(adapter, band);
}
u32 tx_idle_poll_sel(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel,
u8 band)
{
return tx_idle_sel_ck_b(adapter, sel, band);
}
u32 stop_ac_tb_tx(struct mac_ax_adapter *adapter, enum tb_stop_sel stop_sel,
struct mac_ax_tb_ppdu_ctrl *ac_dis_bak)
{
u32 ret;
struct mac_ax_tb_ppdu_ctrl ctrl;
ret = get_hw_tb_ppdu_ctrl(adapter, ac_dis_bak);
if (ret != MACSUCCESS)
return ret;
ctrl.band = ac_dis_bak->band;
ctrl.pri_ac = ac_dis_bak->pri_ac;
ctrl.be_dis = 0;
ctrl.bk_dis = 0;
ctrl.vi_dis = 0;
ctrl.vo_dis = 0;
switch (stop_sel) {
case TB_STOP_SEL_ALL:
ctrl.be_dis = 1;
ctrl.bk_dis = 1;
ctrl.vi_dis = 1;
ctrl.vo_dis = 1;
ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS)
return ret;
break;
case TB_STOP_SEL_BE:
ctrl.be_dis = 1;
ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS)
return ret;
break;
case TB_STOP_SEL_BK:
ctrl.bk_dis = 1;
ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS)
return ret;
break;
case TB_STOP_SEL_VI:
ctrl.vi_dis = 1;
ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS)
return ret;
break;
case TB_STOP_SEL_VO:
ctrl.vo_dis = 1;
ret = set_hw_tb_ppdu_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS)
return ret;
break;
}
return MACSUCCESS;
}
u32 get_edca_addr(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param, u32 *reg_edca)
{
u8 band;
u32 ret;
enum mac_ax_cmac_path_sel path;
band = param->band;
path = param->path;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
switch (path) {
case MAC_AX_CMAC_PATH_SEL_BE0:
*reg_edca =
band ? R_AX_EDCA_BE_PARAM_0_C1 : R_AX_EDCA_BE_PARAM_0;
break;
case MAC_AX_CMAC_PATH_SEL_BK0:
*reg_edca =
band ? R_AX_EDCA_BK_PARAM_0_C1 : R_AX_EDCA_BK_PARAM_0;
break;
case MAC_AX_CMAC_PATH_SEL_VI0:
*reg_edca =
band ? R_AX_EDCA_VI_PARAM_0_C1 : R_AX_EDCA_VI_PARAM_0;
break;
case MAC_AX_CMAC_PATH_SEL_VO0:
*reg_edca =
band ? R_AX_EDCA_VO_PARAM_0_C1 : R_AX_EDCA_VO_PARAM_0;
break;
case MAC_AX_CMAC_PATH_SEL_BE1:
*reg_edca =
band ? R_AX_EDCA_BE_PARAM_1_C1 : R_AX_EDCA_BE_PARAM_1;
break;
case MAC_AX_CMAC_PATH_SEL_BK1:
*reg_edca =
band ? R_AX_EDCA_BK_PARAM_1_C1 : R_AX_EDCA_BK_PARAM_1;
break;
case MAC_AX_CMAC_PATH_SEL_VI1:
*reg_edca =
band ? R_AX_EDCA_VI_PARAM_1_C1 : R_AX_EDCA_VI_PARAM_1;
break;
case MAC_AX_CMAC_PATH_SEL_VO1:
*reg_edca =
band ? R_AX_EDCA_VO_PARAM_1_C1 : R_AX_EDCA_VO_PARAM_1;
break;
case MAC_AX_CMAC_PATH_SEL_MG0_1:
*reg_edca =
band ? R_AX_EDCA_MGQ_PARAM_C1 : R_AX_EDCA_MGQ_PARAM;
break;
case MAC_AX_CMAC_PATH_SEL_MG2:
*reg_edca =
band ? (R_AX_EDCA_MGQ_PARAM_C1 + 2) :
(R_AX_EDCA_MGQ_PARAM + 2);
break;
case MAC_AX_CMAC_PATH_SEL_BCN:
*reg_edca =
band ? (R_AX_EDCA_BCNQ_PARAM_C1 + 2) :
(R_AX_EDCA_BCNQ_PARAM + 2);
break;
case MAC_AX_CMAC_PATH_SEL_TF:
*reg_edca = R_AX_EDCA_ULQ_PARAM;
break;
case MAC_AX_CMAC_PATH_SEL_TWT0:
*reg_edca = R_AX_EDCA_TWT_PARAM_0;
break;
case MAC_AX_CMAC_PATH_SEL_TWT1:
*reg_edca = R_AX_EDCA_TWT_PARAM_1;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 get_muedca_param_addr(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_param *param,
u32 *reg_edca)
{
u8 band;
u32 ret;
enum mac_ax_cmac_ac_sel ac;
band = param->band;
ac = param->ac;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
switch (ac) {
case MAC_AX_CMAC_AC_SEL_BE:
*reg_edca =
band ? R_AX_MUEDCA_BE_PARAM_0_C1 :
R_AX_MUEDCA_BE_PARAM_0;
break;
case MAC_AX_CMAC_AC_SEL_BK:
*reg_edca =
band ? R_AX_MUEDCA_BK_PARAM_0_C1 :
R_AX_MUEDCA_BK_PARAM_0;
break;
case MAC_AX_CMAC_AC_SEL_VI:
*reg_edca =
band ? R_AX_MUEDCA_VI_PARAM_0_C1 :
R_AX_MUEDCA_VI_PARAM_0;
break;
case MAC_AX_CMAC_AC_SEL_VO:
*reg_edca =
band ? R_AX_MUEDCA_VO_PARAM_0_C1 :
R_AX_MUEDCA_VO_PARAM_0;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
/* for sw mode Tx, need to stop sch */
/* (for "F2PCMD.disable_sleep_chk"), soar 20200225*/
static u32 stop_macid_ctn(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role,
struct mac_ax_sch_tx_en_cfg *bak)
{
struct mac_ax_sch_tx_en_cfg cfg;
u32 ret;
ret = check_mac_en(adapter, role->info.band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
ret = get_hw_sch_tx_en(adapter, bak);
if (ret != MACSUCCESS)
return ret;
cfg.band = role->info.band;
u16_2_sch(adapter, &cfg.tx_en_mask, 0);
u16_2_sch(adapter, &cfg.tx_en, 0);
u16_2_sch(adapter, &cfg.tx_en_mask, 0xFFFF);
cfg.tx_en_mask.mg0 = 0;
cfg.tx_en_mask.mg1 = 0;
cfg.tx_en_mask.mg2 = 0;
cfg.tx_en_mask.hi = 0;
cfg.tx_en_mask.bcn = 0;
ret = set_hw_sch_tx_en(adapter, &cfg);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
static u32 tx_idle_ck(struct mac_ax_adapter *adapter, u8 band)
{
u32 cnt;
u8 val8;
u32 ret;
u32 poll_addr;
u32 i;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL;
cnt = PTCL_IDLE_POLL_CNT;
while (--cnt) {
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT) {
PLTFM_DELAY_US(SW_CVR_DUR_US);
} else {
for (i = 0; i < SW_CVR_CNT; i++) {
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT)
break;
PLTFM_DELAY_US(SW_CVR_DUR_US);
}
if (i >= SW_CVR_CNT)
break;
}
}
if (!cnt)
return MACPOLLTXIDLE;
return MACSUCCESS;
}
static u32 tx_idle_sel_ck(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel,
u8 band)
{
u32 cnt;
u8 val8;
u32 ret;
u32 poll_addr;
u32 i;
u8 ptcl_tx_qid;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL;
switch (sel) {
case PTCL_TX_SEL_HIQ:
ptcl_tx_qid = PTCL_TXQ_HIQ;
break;
case PTCL_TX_SEL_MG0:
ptcl_tx_qid = PTCL_TXQ_MG0;
break;
default:
return MACNOITEM;
}
cnt = PTCL_IDLE_POLL_CNT;
while (--cnt) {
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT) {
if (GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX) ==
ptcl_tx_qid)
PLTFM_DELAY_US(SW_CVR_DUR_US);
else
break;
} else {
for (i = 0; i < SW_CVR_CNT; i++) {
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT)
break;
PLTFM_DELAY_US(SW_CVR_DUR_US);
}
if ((val8 & B_AX_PTCL_TX_ON_STAT) &&
GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX) !=
ptcl_tx_qid)
break;
if (i >= SW_CVR_CNT)
break;
}
}
if (!cnt)
return MACPOLLTXIDLE;
return MACSUCCESS;
}
static u32 tx_idle_sel_ck_b(struct mac_ax_adapter *adapter,
enum ptcl_tx_sel sel, u8 band)
{
u32 cnt;
u8 val8;
u32 ret;
u8 ptcl_tx_qid;
u32 poll_addr;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL;
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT)
tx_on_dly(adapter, band);
else
return MACSUCCESS;
switch (sel) {
case PTCL_TX_SEL_HIQ:
ptcl_tx_qid = PTCL_TXQ_HIQ;
break;
case PTCL_TX_SEL_MG0:
ptcl_tx_qid = PTCL_TXQ_MG0;
break;
default:
return MACNOITEM;
}
cnt = PTCL_IDLE_POLL_CNT;
while (--cnt) {
val8 = MAC_REG_R8(poll_addr);
if ((val8 & B_AX_PTCL_TX_ON_STAT) && (val8 & B_AX_PTCL_DROP))
PLTFM_DELAY_US(SW_CVR_DUR_US);
else if ((val8 & B_AX_PTCL_TX_ON_STAT) &&
(GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX) ==
ptcl_tx_qid))
PLTFM_DELAY_US(SW_CVR_DUR_US);
else
break;
}
if (!cnt)
return MACPOLLTXIDLE;
return MACSUCCESS;
}
static u32 macid_idle_ck(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role)
{
u32 cnt;
u8 val8;
u32 ret;
u8 band;
u32 val32;
u8 macid;
u8 txq;
u32 poll_addr;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
band = role->info.band;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL;
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT)
tx_on_dly(adapter, band);
else
return MACSUCCESS;
macid = role->macid;
cnt = PTCL_IDLE_POLL_CNT;
while (--cnt) {
val8 = MAC_REG_R8(poll_addr);
txq = GET_FIELD(val8, B_AX_PTCL_TX_QUEUE_IDX);
if ((val8 & B_AX_PTCL_TX_ON_STAT) && (val8 & B_AX_PTCL_DROP)) {
PLTFM_DELAY_US(SW_CVR_DUR_US);
} else if ((val8 & B_AX_PTCL_TX_ON_STAT) &&
txq != PTCL_TXQ_HIQ && txq != PTCL_TXQ_BCNQ &&
txq != PTCL_TXQ_MG0 && txq != PTCL_TXQ_MG1 &&
txq != PTCL_TXQ_MG2 && txq != PTCL_TXQ_TB) {
PLTFM_DELAY_US(SW_CVR_DUR_US);
/* need to modify for 8852C, soar */
val32 = MAC_REG_R32(band ? R_AX_PTCL_TX_MACID_0_C1 :
R_AX_PTCL_TX_MACID_0);
if (macid == GET_FIELD(val32, B_AX_TX_MACID_0) ||
macid == GET_FIELD(val32, B_AX_TX_MACID_1) ||
macid == GET_FIELD(val32, B_AX_TX_MACID_2) ||
macid == GET_FIELD(val32, B_AX_TX_MACID_3))
PLTFM_DELAY_US(SW_CVR_DUR_US);
else
break;
} else {
break;
}
}
if (!cnt)
return MACPOLLTXIDLE;
return MACSUCCESS;
}
static u32 band_idle_ck(struct mac_ax_adapter *adapter, u8 band)
{
u32 cnt;
u8 val8;
u32 ret;
u32 poll_addr;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
poll_addr = band ? R_AX_PTCL_TX_CTN_SEL_C1 : R_AX_PTCL_TX_CTN_SEL;
cnt = PTCL_IDLE_POLL_CNT;
while (--cnt) {
val8 = MAC_REG_R8(poll_addr);
if (val8 & B_AX_PTCL_TX_ON_STAT)
PLTFM_DELAY_US(SW_CVR_DUR_US);
else
break;
}
if (!cnt)
return MACPOLLTXIDLE;
return MACSUCCESS;
}
static void tx_on_dly(struct mac_ax_adapter *adapter, u8 band)
{
u32 val32;
u32 drop_dly_max;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(band ? R_AX_TX_CTRL_C1 : R_AX_TX_CTRL);
drop_dly_max = GET_FIELD(val32, B_AX_DROP_CHK_MAX_NUM) >> 2;
PLTFM_DELAY_US((drop_dly_max > TX_DLY_MAX) ? drop_dly_max : TX_DLY_MAX);
}
static void sch_2_u16(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en *tx_en, u16 *val16)
{
*val16 = (tx_en->be0 ? B_AX_CTN_TXEN_BE_0 : 0) |
(tx_en->bk0 ? B_AX_CTN_TXEN_BK_0 : 0) |
(tx_en->vi0 ? B_AX_CTN_TXEN_VI_0 : 0) |
(tx_en->vo0 ? B_AX_CTN_TXEN_VO_0 : 0) |
(tx_en->be1 ? B_AX_CTN_TXEN_BE_1 : 0) |
(tx_en->bk1 ? B_AX_CTN_TXEN_BK_1 : 0) |
(tx_en->vi1 ? B_AX_CTN_TXEN_VI_1 : 0) |
(tx_en->vo1 ? B_AX_CTN_TXEN_VO_1 : 0) |
(tx_en->mg0 ? B_AX_CTN_TXEN_MGQ : 0) |
(tx_en->mg1 ? B_AX_CTN_TXEN_MGQ1 : 0) |
(tx_en->mg2 ? B_AX_CTN_TXEN_CPUMGQ : 0) |
(tx_en->hi ? B_AX_CTN_TXEN_HGQ : 0) |
(tx_en->bcn ? B_AX_CTN_TXEN_BCNQ : 0) |
(tx_en->ul ? B_AX_CTN_TXEN_ULQ : 0) |
(tx_en->twt0 ? B_AX_CTN_TXEN_TWT_0 : 0) |
(tx_en->twt1 ? B_AX_CTN_TXEN_TWT_1 : 0);
}
static void u16_2_sch(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en *tx_en, u16 val16)
{
tx_en->be0 = val16 & B_AX_CTN_TXEN_BE_0 ? 1 : 0;
tx_en->bk0 = val16 & B_AX_CTN_TXEN_BK_0 ? 1 : 0;
tx_en->vi0 = val16 & B_AX_CTN_TXEN_VI_0 ? 1 : 0;
tx_en->vo0 = val16 & B_AX_CTN_TXEN_VO_0 ? 1 : 0;
tx_en->be1 = val16 & B_AX_CTN_TXEN_BE_1 ? 1 : 0;
tx_en->bk1 = val16 & B_AX_CTN_TXEN_BK_1 ? 1 : 0;
tx_en->vi1 = val16 & B_AX_CTN_TXEN_VI_1 ? 1 : 0;
tx_en->vo1 = val16 & B_AX_CTN_TXEN_VO_1 ? 1 : 0;
tx_en->mg0 = val16 & B_AX_CTN_TXEN_MGQ ? 1 : 0;
tx_en->mg1 = val16 & B_AX_CTN_TXEN_MGQ1 ? 1 : 0;
tx_en->mg2 = val16 & B_AX_CTN_TXEN_CPUMGQ ? 1 : 0;
tx_en->hi = val16 & B_AX_CTN_TXEN_HGQ ? 1 : 0;
tx_en->bcn = val16 & B_AX_CTN_TXEN_BCNQ ? 1 : 0;
tx_en->ul = val16 & B_AX_CTN_TXEN_ULQ ? 1 : 0;
tx_en->twt0 = val16 & B_AX_CTN_TXEN_TWT_0 ? 1 : 0;
tx_en->twt1 = val16 & B_AX_CTN_TXEN_TWT_1 ? 1 : 0;
}
static u32 h2c_usr_edca(struct mac_ax_adapter *adapter,
struct mac_ax_usr_edca_param *param)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_usr_edca *fwcmd_tbl;
u32 ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_WARN("%s fw not ready\n", __func__);
return MACFWNONRDY;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_usr_edca));
if (!buf) {
ret = MACNOBUF;
goto usr_edca_fail;
}
fwcmd_tbl = (struct fwcmd_usr_edca *)buf;
fwcmd_tbl->dword0 =
cpu_to_le32(SET_WORD(param->idx, FWCMD_H2C_USR_EDCA_PARAM_SEL) |
(param->enable ? FWCMD_H2C_USR_EDCA_ENABLE : 0) |
(param->band ? FWCMD_H2C_USR_EDCA_BAND : 0) |
(param->wmm ? FWCMD_H2C_USR_EDCA_WMM : 0) |
SET_WORD(param->ac, FWCMD_H2C_USR_EDCA_AC));
fwcmd_tbl->dword1 =
cpu_to_le32(SET_WORD(param->aggressive.txop_32us, B_AX_BE_0_TXOPLMT) |
SET_WORD((param->aggressive.ecw_max << 4) |
param->aggressive.ecw_min, B_AX_BE_0_CW) |
SET_WORD(param->aggressive.aifs_us, B_AX_BE_0_AIFS));
fwcmd_tbl->dword2 =
cpu_to_le32(SET_WORD(param->moderate.txop_32us, B_AX_BE_0_TXOPLMT) |
SET_WORD((param->moderate.ecw_max << 4) |
param->moderate.ecw_min, B_AX_BE_0_CW) |
SET_WORD(param->moderate.aifs_us, B_AX_BE_0_AIFS));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_USR_EDCA,
0,
0);
if (ret != MACSUCCESS)
goto usr_edca_fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto usr_edca_fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto usr_edca_fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
usr_edca_fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 h2c_usr_tx_rpt(struct mac_ax_adapter *adapter,
struct mac_ax_usr_tx_rpt_cfg *param)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_usr_tx_rpt *fwcmd_tbl;
u32 ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_WARN("%s fw not ready\n", __func__);
return MACFWNONRDY;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_usr_tx_rpt));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_tbl = (struct fwcmd_usr_tx_rpt *)buf;
fwcmd_tbl->dword0 =
cpu_to_le32(SET_WORD(param->mode, FWCMD_H2C_USR_TX_RPT_MODE) |
(param->rpt_start ? FWCMD_H2C_USR_TX_RPT_RTP_START : 0));
fwcmd_tbl->dword1 =
cpu_to_le32(SET_WORD(param->macid, FWCMD_H2C_USR_TX_RPT_MACID) |
(param->band ? FWCMD_H2C_USR_TX_RPT_BAND : 0) |
SET_WORD(param->port, FWCMD_H2C_USR_TX_RPT_PORT));
fwcmd_tbl->dword2 = cpu_to_le32(param->rpt_period_us);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_USR_TX_RPT,
0,
0);
if (ret != MACSUCCESS)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_set_cctl_max_tx_time(struct mac_ax_adapter *adapter,
struct mac_ax_max_tx_time *tx_time)
{
#define MAC_AX_DFLT_TX_TIME 5280
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_cctl_info info, msk = {0};
u32 ret = MACSUCCESS;
struct mac_role_tbl *role;
u8 band;
u32 offset, max_tx_time;
role = mac_role_srch(adapter, tx_time->macid);
if (!role) {
PLTFM_MSG_ERR("%s: The MACID%d does not exist\n",
__func__, tx_time->macid);
return MACNOITEM;
}
max_tx_time = tx_time->max_tx_time == 0 ?
MAC_AX_DFLT_TX_TIME : tx_time->max_tx_time;
if (tx_time->is_cctrl) {
msk.ampdu_time_sel = 1;
info.ampdu_time_sel = 1;
msk.ampdu_max_time = FWCMD_H2C_CCTRL_AMPDU_MAX_TIME_MSK;
info.ampdu_max_time = (max_tx_time - 512) >> 9;
ret = mac_upd_cctl_info(adapter, &info, &msk, tx_time->macid, 1);
} else {
band = role->info.wmm < 2 ? 0 : 1;
offset = band == 0 ? R_AX_AMPDU_AGG_LIMIT + 3 :
R_AX_AMPDU_AGG_LIMIT_C1 + 3;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W8_OFLD((u16)offset,
max_tx_time >> 5,
1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: ofld fail %d\n",
__func__, ret);
return ret;
}
#endif
MAC_REG_W8(offset, max_tx_time >> 5);
}
return ret;
}
u32 mac_get_max_tx_time(struct mac_ax_adapter *adapter,
struct mac_ax_max_tx_time *tx_time)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS;
struct mac_role_tbl *role;
u32 offset;
u8 band;
role = mac_role_srch(adapter, tx_time->macid);
if (!role) {
PLTFM_MSG_ERR("%s: The MACID%d does not exist\n",
__func__, tx_time->macid);
return MACNOITEM;
}
if (role->info.c_info.ampdu_time_sel) {
tx_time->max_tx_time = (role->info.c_info.ampdu_max_time + 1) << 9;
tx_time->is_cctrl = 1;
} else {
band = role->info.wmm < 2 ? 0 : 1;
offset = band == 0 ? R_AX_AMPDU_AGG_LIMIT + 3 :
R_AX_AMPDU_AGG_LIMIT_C1 + 3;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret == MACSUCCESS)
tx_time->max_tx_time = MAC_REG_R8(offset) << 5;
tx_time->is_cctrl = 0;
}
return ret;
}
u32 mac_set_hw_rts_th(struct mac_ax_adapter *adapter,
struct mac_ax_hw_rts_th *th)
{
#define MAC_AX_MULT32_SH 5
#define MAC_AX_MULT16_SH 4
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret, offset;
u16 val;
ret = check_mac_en(adapter, th->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
offset = th->band ? R_AX_AGG_LEN_HT_0_C1 : R_AX_AGG_LEN_HT_0;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)offset,
B_AX_RTS_LEN_TH_MSK << B_AX_RTS_LEN_TH_SH,
th->len_th >> MAC_AX_MULT16_SH, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
ret = MAC_REG_W_OFLD((u16)offset,
B_AX_RTS_TXTIME_TH_MSK <<
B_AX_RTS_TXTIME_TH_SH,
th->time_th >> MAC_AX_MULT32_SH, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
return MACSUCCESS;
}
#endif
val = SET_WORD(th->len_th >> MAC_AX_MULT16_SH, B_AX_RTS_LEN_TH) |
SET_WORD(th->time_th >> MAC_AX_MULT32_SH, B_AX_RTS_TXTIME_TH);
MAC_REG_W16(offset, val);
return MACSUCCESS;
}
u32 mac_get_hw_rts_th(struct mac_ax_adapter *adapter,
struct mac_ax_hw_rts_th *th)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret, offset;
u16 val;
ret = check_mac_en(adapter, th->band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
offset = th->band ? R_AX_AGG_LEN_HT_0_C1 : R_AX_AGG_LEN_HT_0;
val = MAC_REG_R16(offset);
th->len_th = GET_FIELD(val, B_AX_RTS_LEN_TH);
th->len_th = th->len_th << MAC_AX_MULT16_SH;
th->time_th = GET_FIELD(val, B_AX_RTS_TXTIME_TH);
th->time_th = th->time_th << MAC_AX_MULT32_SH;
return MACSUCCESS;
#undef MAC_AX_MULT32_SH
#undef MAC_AX_MULT16_SH
}
u32 mac_tx_idle_poll(struct mac_ax_adapter *adapter,
struct mac_ax_tx_idle_poll_cfg *poll_cfg)
{
switch (poll_cfg->sel) {
case MAC_AX_TX_IDLE_POLL_SEL_BAND:
return tx_idle_poll_band(adapter, poll_cfg->band, 1);
default:
return MACNOITEM;
}
}
u32 mac_set_tx_ru26_tb(struct mac_ax_adapter *adapter,
u8 disable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
#if MAC_AX_FW_REG_OFLD
u32 ret;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
if (disable)
ret = MAC_REG_W_OFLD(R_AX_RXTRIG_TEST_USER_2, B_AX_RXTRIG_RU26_DIS, 1, 1);
else
ret = MAC_REG_W_OFLD(R_AX_RXTRIG_TEST_USER_2, B_AX_RXTRIG_RU26_DIS, 0, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__, R_AX_RXTRIG_TEST_USER_2);
return ret;
}
return MACSUCCESS;
}
#endif
val32 = MAC_REG_R32(R_AX_RXTRIG_TEST_USER_2) & (~B_AX_RXTRIG_RU26_DIS);
if (disable)
MAC_REG_W32(R_AX_RXTRIG_TEST_USER_2, val32 | B_AX_RXTRIG_RU26_DIS);
else
MAC_REG_W32(R_AX_RXTRIG_TEST_USER_2, val32);
return MACSUCCESS;
}
u32 mac_tx_duty(struct mac_ax_adapter *adapter,
u16 pause_intvl, u16 tx_intvl)
{
u32 ret;
if (!(pause_intvl) || !(tx_intvl))
return MACFUNCINPUT;
ret = tx_duty_h2c(adapter, pause_intvl, tx_intvl);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 mac_tx_duty_stop(struct mac_ax_adapter *adapter)
{
u32 ret;
ret = tx_duty_h2c(adapter, 0, 0);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
u32 tx_duty_h2c(struct mac_ax_adapter *adapter,
u16 pause_intvl, u16 tx_intvl)
{
u32 ret, size;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
struct fwcmd_tx_duty cfg;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
size = sizeof(struct fwcmd_tx_duty);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, size);
if (!buf) {
h2cb_free(adapter, h2cb);
return MACNOBUF;
}
cfg.dword0 =
cpu_to_le32(SET_WORD(pause_intvl, FWCMD_H2C_TX_DUTY_PAUSE_INTVL) |
SET_WORD(tx_intvl, FWCMD_H2C_TX_DUTY_TX_INTVL)
);
cfg.dword1 = cpu_to_le32(pause_intvl ? 0 : FWCMD_H2C_TX_DUTY_STOP);
PLTFM_MEMCPY(buf, &cfg, size);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_TX_DUTY,
0, 0);
if (ret != MACSUCCESS) {
h2cb_free(adapter, h2cb);
return ret;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS) {
h2cb_free(adapter, h2cb);
return ret;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
h2cb_free(adapter, h2cb);
return ret;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/cmac_tx.c
|
C
|
agpl-3.0
| 46,011
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_CMAC_TX_H_
#define _MAC_AX_CMAC_TX_H_
#include "../type.h"
#include "trxcfg.h"
#include "role.h"
#include "hw.h"
#include "dbgpkg.h"
/*--------------------Define ----------------------------------------*/
#define PTCL_TXQ_WMM0_BE 0
#define PTCL_TXQ_WMM0_BK 1
#define PTCL_TXQ_WMM0_VI 2
#define PTCL_TXQ_WMM0_VO 3
#define PTCL_TXQ_WMM1_BE 4
#define PTCL_TXQ_WMM1_BK 5
#define PTCL_TXQ_WMM1_VI 6
#define PTCL_TXQ_WMM1_VO 7
#define PTCL_TXQ_MG0 8
#define PTCL_TXQ_MG1 9
#define PTCL_TXQ_MG2 10
#define PTCL_TXQ_HIQ 11
#define PTCL_TXQ_BCNQ 12
#define PTCL_TXQ_UL 13
#define PTCL_TXQ_TWT0 14
#define PTCL_TXQ_TWT1 15
#define PTCL_TXQ_TB 16
#define TX_PAUSE_WAIT_CNT 5000
/*--------------------Define Enum------------------------------------*/
/**
* @enum tb_stop_sel
*
* @brief tb_stop_sel
*
* @var tb_stop_sel::TB_STOP_SEL_BE
* Please Place Description here.
* @var tb_stop_sel::TB_STOP_SEL_BK
* Please Place Description here.
* @var tb_stop_sel::TB_STOP_SEL_VI
* Please Place Description here.
* @var tb_stop_sel::TB_STOP_SEL_VO
* Please Place Description here.
* @var tb_stop_sel::TB_STOP_SEL_ALL
* Please Place Description here.
*/
enum tb_stop_sel {
TB_STOP_SEL_BE,
TB_STOP_SEL_BK,
TB_STOP_SEL_VI,
TB_STOP_SEL_VO,
TB_STOP_SEL_ALL,
};
/**
* @enum sch_tx_sel
*
* @brief sch_tx_sel
*
* @var sch_tx_sel::SCH_TX_SEL_ALL
* Please Place Description here.
* @var sch_tx_sel::SCH_TX_SEL_HIQ
* Please Place Description here.
* @var sch_tx_sel::SCH_TX_SEL_MG0
* Please Place Description here.
* @var sch_tx_sel::SCH_TX_SEL_MACID
* Please Place Description here.
*/
enum sch_tx_sel {
SCH_TX_SEL_ALL,
SCH_TX_SEL_HIQ,
SCH_TX_SEL_MG0,
SCH_TX_SEL_MACID,
};
/**
* @enum ptcl_tx_sel
*
* @brief ptcl_tx_sel
*
* @var ptcl_tx_sel::PTCL_TX_SEL_HIQ
* Please Place Description here.
* @var ptcl_tx_sel::PTCL_TX_SEL_MG0
* Please Place Description here.
*/
enum ptcl_tx_sel {
PTCL_TX_SEL_HIQ,
PTCL_TX_SEL_MG0,
};
/*--------------------Define MACRO----------------------------------*/
/*--------------------Define Struct----------------------------------*/
/**
* @struct sch_tx_en_h2creg
* @brief sch_tx_en_h2creg
*
* @var sch_tx_en_h2creg::tx_en
* Please Place Description here.
* @var sch_tx_en_h2creg::mask
* Please Place Description here.
* @var sch_tx_en_h2creg::band
* Please Place Description here.
* @var sch_tx_en_h2creg::rsvd
* Please Place Description here.
*/
struct sch_tx_en_h2creg {
/* dword0 */
u32 tx_en:16;
/* dword1 */
u32 mask:16;
u32 band:1;
u32 rsvd0:15;
};
/*--------------------Export global variable----------------------------*/
/*--------------------Function declaration-----------------------------*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_ampdu_cfg
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_ampdu_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_ampdu_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_usr_edca_param
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_usr_edca_param(struct mac_ax_adapter *adapter,
struct mac_ax_usr_edca_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_usr_tx_rpt_cfg
*
* @param *adapter
* @param *cfg
* @return MACSUCCESS
* @retval u32
*/
u32 set_hw_usr_tx_rpt_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_usr_tx_rpt_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_edca_param
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_edca_param(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief get_hw_edca_param
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 get_hw_edca_param(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_edcca_param
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_edcca_param(struct mac_ax_adapter *adapter,
struct mac_ax_edcca_param *param);
/**
* @}
* @}
*/
/**
* @brief set_hw_muedca_param
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_muedca_param(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_muedca_ctrl
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_muedca_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_tb_ppdu_ctrl
*
* @param *adapter
* @param *ctrl
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_tb_ppdu_ctrl *ctrl);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief get_hw_tb_ppdu_ctrl
*
* @param *adapter
* @param *ctrl
* @return Please Place Description here.
* @retval u32
*/
u32 get_hw_tb_ppdu_ctrl(struct mac_ax_adapter *adapter,
struct mac_ax_tb_ppdu_ctrl *ctrl);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_sch_tx_en
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_sch_tx_en(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief hw_sch_tx_en
*
* @param *adapter
* @param band
* @param tx_en_u16
* @param mask_u16
* @return Please Place Description here.
* @retval u32
*/
u32 hw_sch_tx_en(struct mac_ax_adapter *adapter, u8 band,
u16 tx_en_u16, u16 mask_u16);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief get_hw_sch_tx_en
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 get_hw_sch_tx_en(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief set_hw_lifetime_cfg
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_hw_lifetime_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_lifetime_cfg *cfg);
/**
* @}
* @}
*/
/**
* @brief get_hw_lifetime_cfg
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 get_hw_lifetime_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_lifetime_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief stop_sch_tx
*
* @param *adapter
* @param sel
* @param *bak
* @return Please Place Description here.
* @retval u32
*/
u32 stop_sch_tx(struct mac_ax_adapter *adapter, enum sch_tx_sel sel,
struct mac_ax_sch_tx_en_cfg *bak);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief resume_sch_tx
*
* @param *adapter
* @param *bak
* @return Please Place Description here.
* @retval u32
*/
u32 resume_sch_tx(struct mac_ax_adapter *adapter,
struct mac_ax_sch_tx_en_cfg *bak);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief stop_macid_tx
*
* @param *adapter
* @param *role
* @param stop_sel
* @param *bak
* @return Please Place Description here.
* @retval u32
*/
u32 stop_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role,
enum tb_stop_sel stop_sel, struct macid_tx_bak *bak);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief resume_macid_tx
*
* @param *adapter
* @param *role
* @param *bak
* @return Please Place Description here.
* @retval u32
*/
u32 resume_macid_tx(struct mac_ax_adapter *adapter, struct mac_role_tbl *role,
struct macid_tx_bak *bak);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief tx_idle_poll_macid
*
* @param *adapter
* @param *role
* @return Please Place Description here.
* @retval u32
*/
u32 tx_idle_poll_macid(struct mac_ax_adapter *adapter,
struct mac_role_tbl *role);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief tx_idle_poll_band
*
* @param *adapter
* @param band: 0/1 for band 0/1
* @param txop_aware: 1: polling until end of TXOP; 0: polling until end of Tx sequence
* @return MACSUCCESS
* @retval u32
*/
u32 tx_idle_poll_band(struct mac_ax_adapter *adapter, u8 band, u8 txop_aware);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief tx_idle_poll_sel
*
* @param *adapter
* @param sel
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 tx_idle_poll_sel(struct mac_ax_adapter *adapter, enum ptcl_tx_sel sel,
u8 band);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief stop_ac_tb_tx
*
* @param *adapter
* @param stop_sel
* @param *ac_dis_bak
* @return Please Place Description here.
* @retval u32
*/
u32 stop_ac_tb_tx(struct mac_ax_adapter *adapter, enum tb_stop_sel stop_sel,
struct mac_ax_tb_ppdu_ctrl *ac_dis_bak);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
u32 get_edca_addr(struct mac_ax_adapter *adapter,
struct mac_ax_edca_param *param, u32 *reg_edca);
u32 get_muedca_param_addr(struct mac_ax_adapter *adapter,
struct mac_ax_muedca_param *param,
u32 *reg_edca);
/**
* @brief mac_set_cctl_max_tx_time
*
* @param *adapter
* @param *tx_time
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_cctl_max_tx_time(struct mac_ax_adapter *adapter,
struct mac_ax_max_tx_time *tx_time);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_get_max_tx_time
*
* @param *adapter
* @param *tx_time
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_max_tx_time(struct mac_ax_adapter *adapter,
struct mac_ax_max_tx_time *tx_time);
/**
* @}
* @}
*/
u32 mac_tx_idle_poll(struct mac_ax_adapter *adapter,
struct mac_ax_tx_idle_poll_cfg *poll_cfg);
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_set_hw_rts_th
*
* @param *adapter
* @param *
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_hw_rts_th(struct mac_ax_adapter *adapter,
struct mac_ax_hw_rts_th *th);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_get_hw_rts_th
*
* @param *adapter
* @param *
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_hw_rts_th(struct mac_ax_adapter *adapter,
struct mac_ax_hw_rts_th *th);
/**
* @}
* @}
*/
/**
* @brief mac_set_tx_ru26_tb
*
* @param *adapter
* @param disable
* @return To enable or disable responding TB in RU26
* @retval u32
*/
u32 mac_set_tx_ru26_tb(struct mac_ax_adapter *adapter,
u8 disable);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_tx_duty
*
* @param *adapter
* @param pause_intvl
* @param tx_intvl
* @return Do tx_duty for Thermal Prodection
* @retval u32
*/
u32 mac_tx_duty(struct mac_ax_adapter *adapter,
u16 pause_intvl, u16 tx_intvl);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_Config
* @{
*/
/**
* @brief mac_tx_duty_stop
*
* @param *adapter
* @param pause_intvl
* @param tx_intvl
* @return Stop tx_duty for Thermal Prodection
* @retval u32
*/
u32 mac_tx_duty_stop(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/cmac_tx.h
|
C
|
agpl-3.0
| 13,313
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "coex.h"
#include "../mac_reg.h"
#include "hw.h"
#include "power_saving.h"
#define MAC_AX_RTK_RATE 5
#define MAC_AX_BT_MODE_0_3 0
#define MAC_AX_BT_MODE_2 2
#define MAC_AX_CSR_DELAY 0
#define MAC_AX_CSR_PRI_TO 5
#define MAC_AX_CSR_TRX_TO 4
#define MAC_AX_CSR_RATE 80
#define MAC_AX_SB_DRV_MSK 0xFFFFFF
#define MAC_AX_SB_DRV_SH 0
#define MAC_AX_SB_FW_MSK 0x7F
#define MAC_AX_SB_FW_SH 24
#define R_AX_LTECOEX_STATUS 0x54
#define B_AX_GNT_BT_RFC_S0_STA BIT(3)
#define B_AX_GNT_WL_RFC_S0_STA BIT(2)
#define B_AX_GNT_BT_RFC_S1_STA BIT(5)
#define B_AX_GNT_WL_RFC_S1_STA BIT(4)
#define MAC_AX_BTGS1_NOTIFY BIT(0)
u32 mac_coex_init(struct mac_ax_adapter *adapter,
struct mac_ax_coex *coex)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val;
u16 val16;
u32 ret, val32;
val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
MAC_REG_W8(R_AX_GPIO_MUXCFG, val | B_AX_ENBT);
switch (coex->direction) {
case MAC_AX_COEX_INNER:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1);
val = (val & ~BIT(2)) | BIT(1);
MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val);
break;
case MAC_AX_COEX_OUTPUT:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1);
val = val | BIT(1) | BIT(0);
MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val);
break;
case MAC_AX_COEX_INPUT:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG + 1);
val = val & ~(BIT(2) | BIT(1));
MAC_REG_W8(R_AX_GPIO_MUXCFG + 1, val);
break;
default:
return MACNOITEM;
}
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD(R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN,
1, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_BT_COEX_CFG_2,
B_AX_GNT_BT_BYPASS_PRIORITY,
1, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
B_AX_WL_ACT_MSK | B_AX_STATIS_BT_EN |
B_AX_BT_CNT_REST,
0x4003, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_TRXPTCL_RESP_0, B_AX_RSP_CHK_BTCCA,
0, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_CCA_CFG_0,
B_AX_BTCCA_BRK_TXOP_EN | B_AX_BTCCA_EN,
1, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
switch (coex->pta_mode) {
case MAC_AX_COEX_RTK_MODE:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3,
B_AX_BTMODE);
MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
ret = MAC_REG_W_OFLD(R_AX_TDMA_MODE,
B_AX_RTK_BT_ENABLE,
1, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_BT_COEX_CFG_5,
B_AX_BT_RPT_SAMPLE_RATE_MSK <<
B_AX_BT_RPT_SAMPLE_RATE_SH,
MAC_AX_RTK_RATE, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
break;
case MAC_AX_COEX_CSR_MODE:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE);
MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
B_AX_BT_PRI_DETECT_TO_MSK <<
B_AX_BT_PRI_DETECT_TO_SH,
MAC_AX_CSR_PRI_TO, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
B_AX_BT_TRX_INIT_DETECT_MSK <<
B_AX_BT_TRX_INIT_DETECT_SH,
MAC_AX_CSR_TRX_TO, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_CSR_MODE,
B_AX_BT_STAT_DELAY_MSK <<
B_AX_BT_STAT_DELAY_SH,
MAC_AX_CSR_DELAY, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W8_OFLD(R_AX_BT_COEX_CFG_2,
MAC_AX_CSR_RATE, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
break;
default:
return MACNOITEM;
}
return ret;
}
#endif
val = MAC_REG_R8(R_AX_BTC_FUNC_EN);
MAC_REG_W8(R_AX_BTC_FUNC_EN, val | B_AX_PTA_WL_TX_EN);
val = MAC_REG_R8(R_AX_BT_COEX_CFG_2 + 1);
MAC_REG_W8(R_AX_BT_COEX_CFG_2 + 1, val | BIT(0));
val = MAC_REG_R8(R_AX_CSR_MODE);
MAC_REG_W8(R_AX_CSR_MODE, val | B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
val = MAC_REG_R8(R_AX_CSR_MODE + 2);
MAC_REG_W8(R_AX_CSR_MODE + 2, val | BIT(0));
val = MAC_REG_R8(R_AX_TRXPTCL_RESP_0 + 3);
MAC_REG_W8(R_AX_TRXPTCL_RESP_0 + 3, val & ~BIT(1));
val16 = MAC_REG_R16(R_AX_CCA_CFG_0);
val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN;
MAC_REG_W16(R_AX_CCA_CFG_0, val16);
ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_2, &val32);
if (ret) {
PLTFM_MSG_ERR("%s: Read LTE fail!\n", __func__);
return ret;
}
val32 = val32 & B_AX_WL_RX_CTRL;
ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_2, val32);
if (ret) {
PLTFM_MSG_ERR("%s: Write LTE fail!\n", __func__);
return ret;
}
switch (coex->pta_mode) {
case MAC_AX_COEX_RTK_MODE:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3,
B_AX_BTMODE);
MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
val = MAC_REG_R8(R_AX_TDMA_MODE);
MAC_REG_W8(R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
val = MAC_REG_R8(R_AX_BT_COEX_CFG_5);
val = SET_CLR_WORD(val, MAC_AX_RTK_RATE,
B_AX_BT_RPT_SAMPLE_RATE);
MAC_REG_W8(R_AX_BT_COEX_CFG_5, val);
break;
case MAC_AX_COEX_CSR_MODE:
val = MAC_REG_R8(R_AX_GPIO_MUXCFG);
val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE);
MAC_REG_W8(R_AX_GPIO_MUXCFG, val);
val16 = MAC_REG_R16(R_AX_CSR_MODE);
val16 = SET_CLR_WORD(val16, MAC_AX_CSR_PRI_TO,
B_AX_BT_PRI_DETECT_TO);
val16 = SET_CLR_WORD(val16, MAC_AX_CSR_TRX_TO,
B_AX_BT_TRX_INIT_DETECT);
val16 = SET_CLR_WORD(val16, MAC_AX_CSR_DELAY,
B_AX_BT_STAT_DELAY);
val16 = val16 | B_AX_ENHANCED_BT;
MAC_REG_W16(R_AX_CSR_MODE, val16);
MAC_REG_W8(R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_get_gnt(struct mac_ax_adapter *adapter, struct mac_ax_coex_gnt *gnt_cfg)
{
u32 val, ret, status;
struct mac_ax_gnt *gnt;
ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_1, &val);
if (ret) {
PLTFM_MSG_ERR("Read LTE fail!\n");
return ret;
}
ret = mac_read_lte(adapter, R_AX_LTECOEX_STATUS, &status);
if (ret) {
PLTFM_MSG_ERR("Read LTE fail!\n");
return ret;
}
gnt = &gnt_cfg->band0;
gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S0_SW_CTRL);
gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S0_STA);
gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S0_SW_CTRL);
gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S0_STA);
gnt = &gnt_cfg->band1;
gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S1_SW_CTRL);
gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S1_STA);
gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S1_SW_CTRL);
gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S1_STA);
return MACSUCCESS;
}
u32 mac_cfg_gnt(struct mac_ax_adapter *adapter, struct mac_ax_coex_gnt *gnt_cfg)
{
u32 val, ret;
ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_1, &val);
if (ret) {
PLTFM_MSG_ERR("Read LTE fail!\n");
return ret;
}
val = (gnt_cfg->band0.gnt_bt ? (B_AX_GNT_BT_RFC_S0_SW_VAL |
B_AX_GNT_BT_BB_S0_SW_VAL) : 0) |
(gnt_cfg->band0.gnt_bt_sw_en ?
(B_AX_GNT_BT_RFC_S0_SW_CTRL |
B_AX_GNT_BT_BB_S0_SW_CTRL) : 0) |
(gnt_cfg->band0.gnt_wl ? (B_AX_GNT_WL_RFC_S0_SW_VAL |
B_AX_GNT_WL_BB_S0_SW_VAL) : 0) |
(gnt_cfg->band0.gnt_wl_sw_en ?
(B_AX_GNT_WL_RFC_S0_SW_CTRL |
B_AX_GNT_WL_BB_S0_SW_CTRL) : 0) |
(gnt_cfg->band1.gnt_bt ? (B_AX_GNT_BT_RFC_S1_SW_VAL |
B_AX_GNT_BT_BB_S1_SW_VAL) : 0) |
(gnt_cfg->band1.gnt_bt_sw_en ?
(B_AX_GNT_BT_RFC_S1_SW_CTRL |
B_AX_GNT_BT_BB_S1_SW_CTRL) : 0) |
(gnt_cfg->band1.gnt_wl ? (B_AX_GNT_WL_RFC_S1_SW_VAL |
B_AX_GNT_WL_BB_S1_SW_VAL) : 0) |
(gnt_cfg->band1.gnt_wl_sw_en ?
(B_AX_GNT_WL_RFC_S1_SW_CTRL |
B_AX_GNT_WL_BB_S1_SW_CTRL) : 0);
ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_1, val);
if (ret) {
PLTFM_MSG_ERR("Write LTE fail!\n");
return ret;
}
ret = mac_read_lte(adapter, R_AX_LTE_SW_CFG_2, &val);
if (ret) {
PLTFM_MSG_ERR("Read LTE fail!\n");
return ret;
}
val = val & B_AX_WL_RX_CTRL ? B_AX_WL_RX_CTRL : 0 |
((gnt_cfg->band0.gnt_bt_sw_en || gnt_cfg->band1.gnt_bt_sw_en) ?
(B_AX_GNT_BT_TX_SW_CTRL | B_AX_GNT_BT_RX_SW_CTRL) : 0) |
((gnt_cfg->band0.gnt_bt || gnt_cfg->band1.gnt_bt) ?
(B_AX_GNT_BT_TX_SW_VAL | B_AX_GNT_BT_RX_SW_VAL) : 0) |
((gnt_cfg->band0.gnt_wl_sw_en || gnt_cfg->band1.gnt_wl_sw_en) ?
(B_AX_GNT_WL_TX_SW_CTRL | B_AX_GNT_WL_RX_SW_CTRL) : 0) |
((gnt_cfg->band0.gnt_wl || gnt_cfg->band1.gnt_wl) ?
(B_AX_GNT_WL_TX_SW_VAL | B_AX_GNT_WL_RX_SW_VAL) : 0);
ret = mac_write_lte(adapter, R_AX_LTE_SW_CFG_2, val);
if (ret) {
PLTFM_MSG_ERR("Write LTE fail!\n");
return ret;
}
return MACSUCCESS;
}
u32 mac_cfg_plt(struct mac_ax_adapter *adapter, struct mac_ax_plt *plt)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg, ret;
u16 val;
ret = check_mac_en(adapter, plt->band, MAC_AX_CMAC_SEL);
if (ret)
return ret;
reg = plt->band == 0 ? R_AX_BT_PLT : R_AX_BT_PLT_C1;
val = (plt->tx & MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
(plt->tx & MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
(plt->tx & MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
(plt->tx & MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
(plt->rx & MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
(plt->rx & MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
(plt->rx & MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
(plt->rx & MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
(plt->rx || plt->tx ? B_AX_PLT_EN : 0);
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)reg,
B_AX_TX_PLT_GNT_LTE_RX |
B_AX_TX_PLT_GNT_BT_TX |
B_AX_TX_PLT_GNT_BT_RX |
B_AX_TX_PLT_GNT_WL |
B_AX_RX_PLT_GNT_LTE_RX |
B_AX_RX_PLT_GNT_BT_TX |
B_AX_RX_PLT_GNT_BT_RX |
B_AX_RX_PLT_GNT_WL,
val, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
#endif
MAC_REG_W16(reg, val);
return MACSUCCESS;
}
u32 mac_read_coex_reg(struct mac_ax_adapter *adapter,
const u32 offset, u32 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (offset > 0xFF) {
PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n");
return MACBADDR;
}
*val = MAC_REG_R32(R_AX_BTC_CFG + offset);
return MACSUCCESS;
}
u32 mac_write_coex_reg(struct mac_ax_adapter *adapter,
const u32 offset, const u32 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (offset > 0xFF) {
PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n");
return MACBADDR;
}
MAC_REG_W32(R_AX_BTC_CFG + offset, val);
return MACSUCCESS;
}
void mac_cfg_sb(struct mac_ax_adapter *adapter, u32 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 fw_sb;
fw_sb = MAC_REG_R32(R_AX_SCOREBOARD);
fw_sb = GET_FIELD(fw_sb, MAC_AX_SB_FW);
fw_sb = fw_sb & ~MAC_AX_BTGS1_NOTIFY;
if (adapter->sm.pwr == MAC_AX_PWR_OFF || _is_in_lps(adapter))
fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR;
else
fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR;
val = GET_FIELD(val, MAC_AX_SB_DRV);
val = B_AX_TOGGLE |
SET_WORD(val, MAC_AX_SB_DRV) |
SET_WORD(fw_sb, MAC_AX_SB_FW);
MAC_REG_W32(R_AX_SCOREBOARD, val);
}
u32 mac_cfg_ctrl_path(struct mac_ax_adapter *adapter, u32 wl)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3);
val = wl ? val | BIT(2) : val & ~BIT(2);
MAC_REG_W8(R_AX_SYS_SDIO_CTRL + 3, val);
return MACSUCCESS;
}
u32 mac_get_ctrl_path(struct mac_ax_adapter *adapter, u32 *wl)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val = MAC_REG_R8(R_AX_SYS_SDIO_CTRL + 3);
*wl = !!(val & BIT(2));
return MACSUCCESS;
}
u32 mac_get_bt_polt_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_bt_polt_cnt *cnt)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 offset = cnt->band ? R_AX_BT_PLT_C1 : R_AX_BT_PLT;
u8 val;
cnt->cnt = MAC_REG_R16(offset + 2);
val = MAC_REG_R8(offset + 1);
MAC_REG_W8(offset + 1, val | BIT(1));
return MACSUCCESS;
}
u32 mac_write_coex_mask(struct mac_ax_adapter *adapter,
u32 offset, u32 mask, u32 val)
{
u32 ret;
if (offset < R_AX_BTC_CFG || offset > R_AX_LTE_RDATA) {
PLTFM_MSG_ERR("[ERR]offset exceed coex reg\n");
return MACBADDR;
}
ret = MAC_REG_W_OFLD((u16)offset, mask, val, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s fail\n", __func__);
return ret;
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/coex.c
|
C
|
agpl-3.0
| 13,872
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_COEX_H_
#define _MAC_AX_COEX_H_
#include "../mac_def.h"
#define MAC_AX_NOTIFY_TP_MAJOR 0x81
#define MAC_AX_NOTIFY_PWR_MAJOR 0x80
#define MAC_AX_NOTIFY_SH 24
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_coex_init
*
* @param *adapter
* @param *coex
* @return Please Place Description here.
* @retval u32
*/
u32 mac_coex_init(struct mac_ax_adapter *adapter,
struct mac_ax_coex *coex);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_cfg_gnt
*
* @param *adapter
* @param *gnt_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_gnt(struct mac_ax_adapter *adapter,
struct mac_ax_coex_gnt *gnt_cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_get_gnt
*
* @param *adapter
* @param *gnt_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_gnt(struct mac_ax_adapter *adapter,
struct mac_ax_coex_gnt *gnt_cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_cfg_plt
*
* @param *adapter
* @param *plt
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_plt(struct mac_ax_adapter *adapter, struct mac_ax_plt *plt);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_write_coex_reg
*
* @param *adapter
* @param offset
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_coex_reg(struct mac_ax_adapter *adapter,
const u32 offset, const u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_read_coex_reg
*
* @param *adapter
* @param offset
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_coex_reg(struct mac_ax_adapter *adapter,
const u32 offset, u32 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_cfg_sb
*
* @param *adapter
* @param val
* @return Please Place Description here.
* @retval void
*/
void mac_cfg_sb(struct mac_ax_adapter *adapter, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_cfg_ctrl_path
*
* @param *adapter
* @param wl
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_ctrl_path(struct mac_ax_adapter *adapter, u32 wl);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_get_ctrl_path
*
* @param *adapter
* @param *wl
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_ctrl_path(struct mac_ax_adapter *adapter, u32 *wl);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_get_bt_polt_cnt
*
* @param *adapter
* @param *cnt
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_bt_polt_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_bt_polt_cnt *cnt);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BTCoex
* @{
*/
/**
* @brief mac_write_coex_mask
*
* Write coex reg with mask
*
* @param *adapter
* @param offset
* @param mask
* @param val
* @return 0 for success, others are fail
* @retval u32
*/
u32 mac_write_coex_mask(struct mac_ax_adapter *adapter,
u32 offset, u32 mask, u32 val);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/coex.h
|
C
|
agpl-3.0
| 4,212
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "cpuio.h"
#define MAX_MACID_NUM 256
static u32 band_pkt_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info, u8 once);
static u32 hw_link_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info);
static u32 macid_pkt_drop_all(struct mac_ax_adapter *adapter, u8 macid);
static u32 ac_pkt_drop(struct mac_ax_adapter *adapter, u8 macid,
enum pkt_drop_ac ac);
static u32 deq_enq_to_tail(struct mac_ax_adapter *adapter,
struct deq_enq_info *info);
static u32 deq_enq_all(struct mac_ax_adapter *adapter,
struct deq_enq_info *info);
static u32 get_1st_pktid(struct mac_ax_adapter *adapter,
struct first_pid_info *info);
static u32 get_next_pktid(struct mac_ax_adapter *adapter,
struct next_pid_info *info);
static void set_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid);
static void set_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid);
static void rel_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid);
static void rel_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid);
static u32 set_hiq_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info);
static u32 rel_hiq_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info);
static void ss_hw_len_udn_clr(struct mac_ax_adapter *adapter);
static u32 hiq_link_drop(struct mac_ax_adapter *adapter, u8 band);
static u32 mg0_link_drop(struct mac_ax_adapter *adapter, u8 band);
u32 mac_dle_buf_req_wd(struct mac_ax_adapter *adapter,
struct cpuio_buf_req_t *buf_req_p)
{
u32 val32, timeout;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = 0;
val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_WD_BUF_REQ_LEN);
val32 |= B_AX_WD_BUF_REQ_EXEC;
MAC_REG_W32(R_AX_WD_BUF_REQ, val32);
timeout = DLE_BUF_REQ_DLY_CNT;
while (timeout--) {
val32 = MAC_REG_R32(R_AX_WD_BUF_STATUS);
if (val32 & B_AX_WD_BUF_STAT_DONE)
break;
PLTFM_DELAY_US(DLE_BUF_REQ_DLY_US);
}
if (!++timeout) {
PLTFM_MSG_ERR("[ERR]dle buf req wd %d timeout\n",
buf_req_p->len);
return MACPOLLTO;
}
buf_req_p->pktid = GET_FIELD(val32, B_AX_WD_BUF_STAT_PKTID);
if (buf_req_p->pktid == 0xfff) {
PLTFM_MSG_ERR("[ERR]dle buf req wd %d no pktid\n",
buf_req_p->len);
return MACNOBUF;
}
return MACSUCCESS;
}
u32 mac_dle_buf_req_pl(struct mac_ax_adapter *adapter,
struct cpuio_buf_req_t *buf_req_p)
{
u32 val32, timeout;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = 0;
val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_PL_BUF_REQ_LEN);
val32 |= B_AX_PL_BUF_REQ_EXEC;
MAC_REG_W32(R_AX_PL_BUF_REQ, val32);
timeout = DLE_BUF_REQ_DLY_CNT;
while (timeout--) {
val32 = MAC_REG_R32(R_AX_PL_BUF_STATUS);
if (val32 & B_AX_PL_BUF_STAT_DONE)
break;
PLTFM_DELAY_US(DLE_BUF_REQ_DLY_US);
}
if (!++timeout) {
PLTFM_MSG_ERR("[ERR]dle buf req pl %d timeout\n",
buf_req_p->len);
return MACPOLLTO;
}
buf_req_p->pktid = GET_FIELD(val32, B_AX_PL_BUF_STAT_PKTID);
if (buf_req_p->pktid == 0xfff) {
PLTFM_MSG_ERR("[ERR]dle buf req pl %d no pktid\n",
buf_req_p->len);
return MACNOBUF;
}
return MACSUCCESS;
}
u32 mac_set_cpuio_wd(struct mac_ax_adapter *adapter,
struct cpuio_ctrl_t *ctrl_para_p)
{
u32 val_op0, val_op1, val_op2;
u32 val32, cmd_type, timeout;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
cmd_type = ctrl_para_p->cmd_type;
val_op2 = 0;
val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->start_pktid,
B_AX_WD_CPUQ_OP_STRT_PKTID);
val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->end_pktid,
B_AX_WD_CPUQ_OP_END_PKTID);
MAC_REG_W32(R_AX_WD_CPUQ_OP_2, val_op2);
val_op1 = 0;
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_pid,
B_AX_WD_CPUQ_OP_SRC_PID);
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_qid,
B_AX_WD_CPUQ_OP_SRC_QID);
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_pid,
B_AX_WD_CPUQ_OP_DST_PID);
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_qid,
B_AX_WD_CPUQ_OP_DST_QID);
MAC_REG_W32(R_AX_WD_CPUQ_OP_1, val_op1);
val_op0 = 0;
val_op0 = SET_CLR_WORD(val_op0, cmd_type,
B_AX_WD_CPUQ_OP_CMD_TYPE);
val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->macid,
B_AX_WD_CPUQ_OP_MACID);
val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->pkt_num,
B_AX_WD_CPUQ_OP_PKTNUM);
val_op0 |= B_AX_WD_CPUQ_OP_EXEC;
MAC_REG_W32(R_AX_WD_CPUQ_OP_0, val_op0);
timeout = SET_CPUIO_DLY_CNT;
do {
val32 = MAC_REG_R32(R_AX_WD_CPUQ_OP_STATUS);
if (val32 & B_AX_WD_CPUQ_OP_STAT_DONE)
break;
PLTFM_DELAY_US(SET_CPUIO_DLY_US);
timeout--;
} while (timeout);
if (!timeout) {
PLTFM_MSG_ERR("[ERR]set cpuio wd timeout\n");
PLTFM_MSG_ERR("[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n",
val_op0, val_op1, val_op2);
return MACPOLLTO;
}
if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID ||
cmd_type == CPUIO_OP_CMD_GET_NEXT_PID)
ctrl_para_p->pktid = GET_FIELD(val32, B_AX_WD_CPUQ_OP_PKTID);
return MACSUCCESS;
}
u32 mac_set_cpuio_pl(struct mac_ax_adapter *adapter,
struct cpuio_ctrl_t *ctrl_para_p)
{
u32 val_op0, val_op1, val_op2;
u32 val32, cmd_type, timeout;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
cmd_type = ctrl_para_p->cmd_type;
val_op2 = 0;
val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->start_pktid,
B_AX_PL_CPUQ_OP_STRT_PKTID);
val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->end_pktid,
B_AX_PL_CPUQ_OP_END_PKTID);
MAC_REG_W32(R_AX_PL_CPUQ_OP_2, val_op2);
val_op1 = 0;
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_pid,
B_AX_PL_CPUQ_OP_SRC_PID);
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_qid,
B_AX_PL_CPUQ_OP_SRC_QID);
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_pid,
B_AX_PL_CPUQ_OP_DST_PID);
val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_qid,
B_AX_PL_CPUQ_OP_DST_QID);
MAC_REG_W32(R_AX_PL_CPUQ_OP_1, val_op1);
val_op0 = 0;
val_op0 = SET_CLR_WORD(val_op0, cmd_type,
B_AX_PL_CPUQ_OP_CMD_TYPE);
val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->macid,
B_AX_PL_CPUQ_OP_MACID);
val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->pkt_num,
B_AX_PL_CPUQ_OP_PKTNUM);
val_op0 |= B_AX_PL_CPUQ_OP_EXEC;
MAC_REG_W32(R_AX_PL_CPUQ_OP_0, val_op0);
timeout = SET_CPUIO_DLY_CNT;
do {
val32 = MAC_REG_R32(R_AX_PL_CPUQ_OP_STATUS);
if (val32 & B_AX_PL_CPUQ_OP_STAT_DONE)
break;
PLTFM_DELAY_US(SET_CPUIO_DLY_US);
timeout--;
} while (timeout);
if (!timeout) {
PLTFM_MSG_ERR("[ERR]set cpuio pl timeout\n");
PLTFM_MSG_ERR("[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n",
val_op0, val_op1, val_op2);
return MACPOLLTO;
}
if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID ||
cmd_type == CPUIO_OP_CMD_GET_NEXT_PID)
ctrl_para_p->pktid = GET_FIELD(val32, B_AX_PL_CPUQ_OP_PKTID);
return MACSUCCESS;
}
u32 mac_wde_pkt_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info)
{
u32 ret;
switch (info->sel) {
case MAC_AX_PKT_DROP_SEL_MACID_BE_ONCE:
ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_BE);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_MACID_BK_ONCE:
ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_BK);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_MACID_VI_ONCE:
ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_VI);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_MACID_VO_ONCE:
ret = ac_pkt_drop(adapter, info->macid, PKT_DROP_VO);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_MACID_ALL:
ret = macid_pkt_drop_all(adapter, info->macid);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_BAND_ONCE:
ret = band_pkt_drop(adapter, info, 1);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_BAND:
ret = band_pkt_drop(adapter, info, 0);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_REL_MACID:
rel_dmac_macid_drop(adapter, info->macid);
rel_cmac_macid_drop(adapter, info->macid);
break;
case MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT:
case MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID:
ret = rel_hiq_drop(adapter, info);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_HIQ_ONCE:
case MAC_AX_PKT_DROP_SEL_MG0_ONCE:
ret = hw_link_drop(adapter, info);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_HIQ_PORT:
case MAC_AX_PKT_DROP_SEL_HIQ_MBSSID:
ret = set_hiq_drop(adapter, info);
if (ret != MACSUCCESS)
return ret;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
static u32 band_pkt_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info, u8 once)
{
u32 ret;
u32 qid;
u8 band = info->band;
u8 macid_grp_num = MAX_MACID_NUM >> 5;
u32 macid_band_sel[MAX_MACID_NUM >> 5] = {0};
u32 macid_ctrl_sel[MAX_MACID_NUM >> 5] = {0};
u32 macid_pause_bak[MAX_MACID_NUM >> 5] = {0};
u32 macid_sleep_bak[MAX_MACID_NUM >> 5] = {0};
u8 i_u8;
u16 i_u16;
u8 macid_grp;
u8 macid_sh;
u16 macid_num = adapter->hw_info->macid_num;
u8 dmac_macid_drop = 0;
struct mac_role_tbl *role;
struct deq_enq_info q_info;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_sch_tx_en_cfg sch_backup;
struct mac_ax_tb_ppdu_ctrl ac_dis_bak;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info));
for (i_u16 = 0; i_u16 < macid_num; i_u16++) {
role = mac_role_srch(adapter, (u8)i_u16);
if (role) {
macid_sh = i_u16 & (32 - 1);
macid_grp = i_u16 >> 5;
if (role->info.band)
macid_band_sel[macid_grp] |= BIT(macid_sh);
else
macid_band_sel[macid_grp] &= ~(BIT(macid_sh));
}
}
if (band == MAC_AX_BAND_1) {
for (i_u8 = 0; i_u8 < macid_grp_num; i_u8++)
macid_ctrl_sel[i_u8] = macid_band_sel[i_u8];
} else {
for (i_u8 = 0; i_u8 < macid_grp_num; i_u8++)
macid_ctrl_sel[i_u8] = ~macid_band_sel[i_u8];
}
/* TBD, pause H2C in val, mask format, Soar, 20200109 */
macid_sleep_bak[0] = MAC_REG_R32(R_AX_MACID_SLEEP_0);
MAC_REG_W32(R_AX_MACID_SLEEP_0, macid_sleep_bak[0] | macid_ctrl_sel[0]);
macid_pause_bak[0] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, macid_pause_bak[0] |
macid_ctrl_sel[0]);
macid_sleep_bak[1] = MAC_REG_R32(R_AX_MACID_SLEEP_1);
MAC_REG_W32(R_AX_MACID_SLEEP_1, macid_sleep_bak[1] | macid_ctrl_sel[1]);
macid_pause_bak[1] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, macid_pause_bak[1] |
macid_ctrl_sel[1]);
macid_sleep_bak[2] = MAC_REG_R32(R_AX_MACID_SLEEP_2);
MAC_REG_W32(R_AX_MACID_SLEEP_2, macid_sleep_bak[2] | macid_ctrl_sel[2]);
macid_pause_bak[2] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, macid_pause_bak[2] |
macid_ctrl_sel[2]);
macid_sleep_bak[3] = MAC_REG_R32(R_AX_MACID_SLEEP_3);
MAC_REG_W32(R_AX_MACID_SLEEP_3, macid_sleep_bak[3] | macid_ctrl_sel[3]);
macid_pause_bak[3] = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, macid_pause_bak[3] |
macid_ctrl_sel[3]);
sch_backup.band = band;
ret = stop_sch_tx(adapter, SCH_TX_SEL_ALL, &sch_backup);
if (ret != MACSUCCESS)
return ret;
ac_dis_bak.band = band;
ret = stop_ac_tb_tx(adapter, TB_STOP_SEL_ALL, &ac_dis_bak);
if (ret != MACSUCCESS)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV)) {
PLTFM_MSG_TRACE("[TRACE]:do not support DMAC drop\n");
dmac_macid_drop = 0;
} else {
dmac_macid_drop = 1;
}
} else {
dmac_macid_drop = 1;
}
if (once == 0 && dmac_macid_drop == 1) {
MAC_REG_W32(R_AX_DMAC_MACID_DROP_0,
MAC_REG_R32(R_AX_DMAC_MACID_DROP_0) |
macid_ctrl_sel[0]);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_1,
MAC_REG_R32(R_AX_DMAC_MACID_DROP_1) |
macid_ctrl_sel[1]);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_2,
MAC_REG_R32(R_AX_DMAC_MACID_DROP_2) |
macid_ctrl_sel[2]);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_3,
MAC_REG_R32(R_AX_DMAC_MACID_DROP_3) |
macid_ctrl_sel[3]);
}
ret = tx_idle_poll_band(adapter, band, 0);
if (ret != MACSUCCESS)
return ret;
q_info.dst_pid = WDE_DLE_PID_WDRLS;
q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP;
q_info.src_pid =
(band == MAC_AX_BAND_1) ? WDE_DLE_PID_C1 : WDE_DLE_PID_C0;
/* need to modify for 8852C, soar */
if (band == MAC_AX_BAND_1) {
for (qid = WDE_DLE_QID_BCN_C1; qid <= WDE_DLE_QID_MG2_C1;
qid++) {
if (qid == WDE_DLE_QID_HI_C1) {
ret = hiq_link_drop(adapter, band);
if (ret != MACSUCCESS)
return ret;
} else {
q_info.src_qid = (u8)qid;
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
}
}
} else {
for (qid = WDE_DLE_QID_BCN_C0; qid <= WDE_DLE_QID_MG2_C0;
qid++) {
if (qid == WDE_DLE_QID_HI_C0) {
ret = hiq_link_drop(adapter, band);
if (ret != MACSUCCESS)
return ret;
} else {
q_info.src_qid = (u8)qid;
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
}
}
}
for (i_u16 = 0; i_u16 < macid_num; i_u16++) {
macid_grp = i_u16 >> 5;
if (macid_ctrl_sel[macid_grp] & BIT(i_u16 & 31)) {
q_info.macid = (u8)i_u16;
q_info.src_pid = WDE_DLE_PID_C0;
q_info.dst_pid = WDE_DLE_PID_WDRLS;
q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP;
for (qid = WDE_DLE_QID_BE;
qid <= WDE_DLE_QID_VO; qid++) {
q_info.src_qid = (u8)qid;
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
}
}
}
PLTFM_DELAY_MS(1);
ss_hw_len_udn_clr(adapter);
/* TBD, pause H2C in val, mask format, Soar, 20200109 */
MAC_REG_W32(R_AX_MACID_SLEEP_0, macid_sleep_bak[0]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_0, macid_pause_bak[0]);
MAC_REG_W32(R_AX_MACID_SLEEP_1, macid_sleep_bak[1]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_1, macid_pause_bak[1]);
MAC_REG_W32(R_AX_MACID_SLEEP_2, macid_sleep_bak[2]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_2, macid_pause_bak[2]);
MAC_REG_W32(R_AX_MACID_SLEEP_3, macid_sleep_bak[3]);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_3, macid_pause_bak[3]);
ret = resume_sch_tx(adapter, &sch_backup);
if (ret != MACSUCCESS)
return ret;
ret = set_hw_tb_ppdu_ctrl(adapter, &ac_dis_bak);
if (ret != MACSUCCESS)
return ret;
return ret;
}
static u32 hw_link_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info)
{
u32 ret;
u8 band = info->band;
struct mac_ax_sch_tx_en_cfg sch_backup;
enum ptcl_tx_sel ptcl_sel;
enum sch_tx_sel sch_sel;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
switch (info->sel) {
case MAC_AX_PKT_DROP_SEL_MG0_ONCE:
ptcl_sel = PTCL_TX_SEL_MG0;
sch_sel = SCH_TX_SEL_MG0;
break;
case MAC_AX_PKT_DROP_SEL_HIQ_ONCE:
ptcl_sel = PTCL_TX_SEL_HIQ;
sch_sel = SCH_TX_SEL_HIQ;
break;
default:
return MACNOITEM;
}
sch_backup.band = band;
ret = stop_sch_tx(adapter, sch_sel, &sch_backup);
if (ret != MACSUCCESS)
return ret;
ret = tx_idle_poll_sel(adapter, ptcl_sel, band);
if (ret != MACSUCCESS)
return ret;
switch (info->sel) {
case MAC_AX_PKT_DROP_SEL_MG0_ONCE:
ret = mg0_link_drop(adapter, band);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_PKT_DROP_SEL_HIQ_ONCE:
ret = hiq_link_drop(adapter, band);
if (ret != MACSUCCESS)
return ret;
break;
default:
return MACNOITEM;
}
ret = resume_sch_tx(adapter, &sch_backup);
if (ret != MACSUCCESS)
return ret;
return ret;
}
static u32 macid_pkt_drop_all(struct mac_ax_adapter *adapter, u8 macid)
{
u32 ret;
u32 qid;
struct deq_enq_info info;
struct macid_tx_bak bak;
struct mac_role_tbl *role;
PLTFM_MEMSET(&info, 0, sizeof(struct deq_enq_info));
role = mac_role_srch(adapter, macid);
if (!role) {
PLTFM_MSG_ERR("[ERR]:role info is null\n");
return MACNOITEM;
}
ret = stop_macid_tx(adapter, role, TB_STOP_SEL_ALL, &bak);
if (ret != MACSUCCESS)
return ret;
set_dmac_macid_drop(adapter, macid);
set_cmac_macid_drop(adapter, macid);
ret = tx_idle_poll_macid(adapter, role);
if (ret != MACSUCCESS)
return ret;
info.macid = macid;
info.src_pid = WDE_DLE_PID_C0;
info.dst_pid = WDE_DLE_PID_WDRLS;
info.dst_qid = WDE_DLE_QID_WDRLS_DROP;
for (qid = WDE_DLE_QID_BE; qid <= WDE_DLE_QID_VO; qid++) {
info.src_qid = (u8)qid;
ret = deq_enq_all(adapter, &info);
if (ret != MACSUCCESS)
return ret;
}
ret = resume_macid_tx(adapter, role, &bak);
if (ret != MACSUCCESS)
return ret;
return ret;
}
static u32 ac_pkt_drop(struct mac_ax_adapter *adapter, u8 macid,
enum pkt_drop_ac ac)
{
u32 ret;
struct deq_enq_info info;
struct mac_role_tbl *role;
enum tb_stop_sel stop_sel;
struct macid_tx_bak bak;
PLTFM_MEMSET(&info, 0, sizeof(struct deq_enq_info));
role = mac_role_srch(adapter, macid);
if (!role) {
PLTFM_MSG_ERR("[ERR]:role info is null\n");
return MACNOITEM;
}
switch (ac) {
case PKT_DROP_BE:
stop_sel = TB_STOP_SEL_BE;
break;
case PKT_DROP_BK:
stop_sel = TB_STOP_SEL_BK;
break;
case PKT_DROP_VI:
stop_sel = TB_STOP_SEL_VI;
break;
case PKT_DROP_VO:
stop_sel = TB_STOP_SEL_VO;
break;
default:
return MACNOITEM;
}
ret = stop_macid_tx(adapter, role, stop_sel, &bak);
if (ret != MACSUCCESS)
return ret;
ret = tx_idle_poll_macid(adapter, role);
if (ret != MACSUCCESS)
return ret;
info.macid = macid;
info.src_pid = WDE_DLE_PID_C0;
info.src_qid = ac;
info.dst_pid = WDE_DLE_PID_WDRLS;
info.dst_qid = WDE_DLE_QID_WDRLS_DROP;
ret = deq_enq_all(adapter, &info);
if (ret != MACSUCCESS)
return ret;
ret = resume_macid_tx(adapter, role, &bak);
if (ret != MACSUCCESS)
return ret;
return ret;
}
static u32 deq_enq_to_tail(struct mac_ax_adapter *adapter,
struct deq_enq_info *info)
{
struct cpuio_ctrl_t cpuio;
u32 ret;
PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t));
cpuio.cmd_type = CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL;
cpuio.macid = info->macid;
cpuio.pkt_num = 0;
cpuio.src_pid = info->src_pid;
cpuio.src_qid = info->src_qid;
cpuio.dst_pid = info->dst_pid;
cpuio.dst_qid = info->dst_qid;
cpuio.start_pktid = info->pktid;
cpuio.end_pktid = info->pktid;
ret = mac_set_cpuio_wd(adapter, &cpuio);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
}
static u32 deq_enq_all(struct mac_ax_adapter *adapter,
struct deq_enq_info *info)
{
struct cpuio_ctrl_t cpuio;
struct first_pid_info pktid_info;
u32 ret;
PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t));
pktid_info.macid = info->macid;
pktid_info.src_pid = info->src_pid;
pktid_info.src_qid = info->src_qid;
ret = get_1st_pktid(adapter, &pktid_info);
if (ret != MACSUCCESS)
return ret;
if (pktid_info.pktid != 0xFFF) {
cpuio.cmd_type = CPUIO_OP_CMD_DEQ_ENQ_ALL;
cpuio.macid = info->macid;
cpuio.src_pid = info->src_pid;
cpuio.src_qid = info->src_qid;
cpuio.dst_pid = info->dst_pid;
cpuio.dst_qid = info->dst_qid;
ret = mac_set_cpuio_wd(adapter, &cpuio);
if (ret != MACSUCCESS)
return ret;
}
return MACSUCCESS;
}
static u32 get_1st_pktid(struct mac_ax_adapter *adapter,
struct first_pid_info *info)
{
u32 ret = MACSUCCESS;
struct cpuio_ctrl_t cpuio;
PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t));
cpuio.cmd_type = CPUIO_OP_CMD_GET_1ST_PID;
cpuio.macid = info->macid;
cpuio.src_pid = info->src_pid;
cpuio.src_qid = info->src_qid;
ret = mac_set_cpuio_wd(adapter, &cpuio);
info->pktid = cpuio.pktid;
return ret;
}
static u32 get_next_pktid(struct mac_ax_adapter *adapter,
struct next_pid_info *info)
{
u32 ret = MACSUCCESS;
struct cpuio_ctrl_t cpuio;
PLTFM_MEMSET(&cpuio, 0, sizeof(struct cpuio_ctrl_t));
cpuio.cmd_type = CPUIO_OP_CMD_GET_NEXT_PID;
cpuio.macid = info->macid;
cpuio.src_pid = info->src_pid;
cpuio.src_qid = info->src_qid;
cpuio.start_pktid = info->start_pktid;
ret = mac_set_cpuio_wd(adapter, &cpuio);
info->pktid = cpuio.pktid;
return ret;
}
static void set_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid)
{
u32 val32;
u8 macid_sh = macid & (32 - 1);
u8 macid_grp = macid >> 5;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV)) {
PLTFM_MSG_TRACE("hw do not support dmac drop!\n");
return;
} else {
if (MAC_REG_R32(R_AX_SS_DBG_3) &
B_AX_SS_HW_DECR_LEN_UDN)
PLTFM_MSG_WARN("STA len underflow bef drop\n");
}
} else {
if (MAC_REG_R32(R_AX_SS_DBG_3) &
B_AX_SS_HW_DECR_LEN_UDN)
PLTFM_MSG_WARN("STA len underflow bef drop\n");
}
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_0);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_0, val32 | BIT(macid_sh));
break;
case 1:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_1);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_1, val32 | BIT(macid_sh));
break;
case 2:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_2);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_2, val32 | BIT(macid_sh));
break;
case 3:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_3);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_3, val32 | BIT(macid_sh));
break;
default:
break;
}
}
static void set_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid)
{
u32 val32;
u8 macid_sh = macid & (32 - 1);
u8 macid_grp = macid >> 5;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_0);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_0, val32 | BIT(macid_sh));
break;
case 1:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_1);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_1, val32 | BIT(macid_sh));
break;
case 2:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_2);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_2, val32 | BIT(macid_sh));
break;
case 3:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_3);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_3, val32 | BIT(macid_sh));
break;
default:
break;
}
}
static void rel_dmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid)
{
u32 val32;
u8 macid_sh = macid & (32 - 1);
u8 macid_grp = macid >> 5;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_0);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_0, val32 & ~(BIT(macid_sh)));
break;
case 1:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_1);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_1, val32 & ~(BIT(macid_sh)));
break;
case 2:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_2);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_2, val32 & ~(BIT(macid_sh)));
break;
case 3:
val32 = MAC_REG_R32(R_AX_DMAC_MACID_DROP_3);
MAC_REG_W32(R_AX_DMAC_MACID_DROP_3, val32 & ~(BIT(macid_sh)));
break;
default:
break;
}
ss_hw_len_udn_clr(adapter);
}
static void rel_cmac_macid_drop(struct mac_ax_adapter *adapter, u8 macid)
{
u32 val32;
u8 macid_sh = macid & (32 - 1);
u8 macid_grp = macid >> 5;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_0);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_0, val32 & ~(BIT(macid_sh)));
break;
case 1:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_1);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_1, val32 & ~(BIT(macid_sh)));
break;
case 2:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_2);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_2, val32 & ~(BIT(macid_sh)));
break;
case 3:
val32 = MAC_REG_R32(R_AX_CMAC_MACID_DROP_3);
MAC_REG_W32(R_AX_CMAC_MACID_DROP_3, val32 & ~(BIT(macid_sh)));
break;
default:
break;
}
}
static u32 set_hiq_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info)
{
u32 val32;
u32 addr;
u16 mbssid_sh;
u8 port_sh;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
addr = info->band ? R_AX_MBSSID_DROP_0_C1 : R_AX_MBSSID_DROP_0;
mbssid_sh = BIT(0) << info->mbssid;
port_sh = BIT(0) << info->port;
val32 = MAC_REG_R32(addr);
switch (info->sel) {
case MAC_AX_PKT_DROP_SEL_HIQ_PORT:
val32 |= port_sh << B_AX_PORT_DROP_4_0_SH;
if (info->port == 0)
val32 |= BIT(0);
break;
case MAC_AX_PKT_DROP_SEL_HIQ_MBSSID:
val32 |= mbssid_sh;
break;
default:
return MACNOITEM;
}
MAC_REG_W32(addr, val32);
return MACSUCCESS;
}
static u32 rel_hiq_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info)
{
u32 val32;
u32 addr;
u16 mbssid_sh;
u8 port_sh;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
addr = info->band ? R_AX_MBSSID_DROP_0_C1 : R_AX_MBSSID_DROP_0;
mbssid_sh = BIT(0) << info->mbssid;
port_sh = BIT(0) << info->port;
val32 = MAC_REG_R32(addr);
switch (info->sel) {
case MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT:
val32 &= ~(port_sh << B_AX_PORT_DROP_4_0_SH);
if (info->port == 0)
val32 &= ~(BIT(0));
break;
case MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID:
val32 &= ~mbssid_sh;
break;
default:
return MACNOITEM;
}
MAC_REG_W32(addr, val32);
return MACSUCCESS;
}
static void ss_hw_len_udn_clr(struct mac_ax_adapter *adapter)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_SS_DBG_3);
if (val32 & B_AX_SS_HW_DECR_LEN_UDN) {
val32 &= ~(B_AX_SS_HW_ADD_LEN_OVF | B_AX_SS_SW_DECR_LEN_UDN |
B_AX_SS_HW_DECR_LEN_UDN | B_AX_SS_ATM_ERR |
B_AX_SS_DEL_STA_ERR | B_AX_SS_ADD_STA_ERR);
MAC_REG_W32(R_AX_SS_DBG_3, val32 | B_AX_SS_HW_DECR_LEN_UDN);
}
}
static u32 hiq_link_drop(struct mac_ax_adapter *adapter, u8 band)
{
u32 ret;
u8 mbid, port;
struct deq_enq_info q_info;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info));
q_info.dst_pid = WDE_DLE_PID_WDRLS;
q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP;
if (band == MAC_AX_BAND_1) {
q_info.src_pid = WDE_DLE_PID_C1;
q_info.src_qid = WDE_DLE_QID_HI_C1;
} else {
q_info.src_pid = WDE_DLE_PID_C0;
q_info.src_qid = WDE_DLE_QID_HI_C0;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
for (mbid = 0; mbid < adapter->hw_info->mbssid_num; mbid++) {
q_info.macid = mbid;
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
}
for (port = 1; port < adapter->hw_info->port_num; port++) {
q_info.macid = port << WDE_DLE_SUBQID_PORT_SH;
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
}
} else {
return MACNOITEM;
}
return ret;
}
static u32 mg0_link_drop(struct mac_ax_adapter *adapter, u8 band)
{
u32 ret;
struct deq_enq_info q_info;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
PLTFM_MEMSET(&q_info, 0, sizeof(struct deq_enq_info));
q_info.dst_pid = WDE_DLE_PID_WDRLS;
q_info.dst_qid = WDE_DLE_QID_WDRLS_DROP;
if (band == MAC_AX_BAND_1) {
q_info.src_pid = WDE_DLE_PID_C1;
q_info.src_qid = WDE_DLE_QID_MG0_C1;
} else {
q_info.src_pid = WDE_DLE_PID_C0;
q_info.src_qid = WDE_DLE_QID_MG0_C0;
}
ret = deq_enq_all(adapter, &q_info);
if (ret != MACSUCCESS)
return ret;
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/cpuio.c
|
C
|
agpl-3.0
| 27,937
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_CPUIO_H_
#define _MAC_AX_CPUIO_H_
#include "../type.h"
#include "trxcfg.h"
#include "role.h"
#include "hw.h"
/*--------------------Define ----------------------------------------*/
#define WDE_DLE_PID_C0 3
#define WDE_DLE_PID_C1 4
#define WDE_DLE_PID_WDRLS 7
#define WDE_DLE_QID_BE 0
#define WDE_DLE_QID_BK 1
#define WDE_DLE_QID_VI 2
#define WDE_DLE_QID_VO 3
#define WDE_DLE_QID_WDRLS_DROP 3
#define WDE_DLE_QID_BCN_C0 0x10
#define WDE_DLE_QID_HI_C0 0x11
#define WDE_DLE_QID_MG0_C0 0x12
#define WDE_DLE_QID_MG1_C0 0x13
#define WDE_DLE_QID_MG2_C0 0x14
#define WDE_DLE_QID_BCN_C1 0x18
#define WDE_DLE_QID_HI_C1 0x19
#define WDE_DLE_QID_MG0_C1 0x1A
#define WDE_DLE_QID_MG1_C1 0x1B
#define WDE_DLE_QID_MG2_C1 0x1C
#define WDE_DLE_SUBQID_PORT_SH 4
#define WDE_DLE_MAX_PKT_NUM 0xFFFF
#define WDE_DLE_NULL_PKTID 0xFFF
#define DLE_BUF_REQ_DLY_CNT 2000
#define DLE_BUF_REQ_DLY_US 1
#define SET_CPUIO_DLY_CNT 2000
#define SET_CPUIO_DLY_US 1
/*--------------------Define Enum------------------------------------*/
/**
* @enum WDE_DLE_PORT_ID
*
* @brief WDE_DLE_PORT_ID
*
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_DISPATCH
* Please Place Description here.
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_PKTIN
* Please Place Description here.
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_CMAC0
* Please Place Description here.
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_CMAC1
* Please Place Description here.
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_CPU_IO
* Please Place Description here.
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_WDRLS
* Please Place Description here.
* @var WDE_DLE_PORT_ID::WDE_DLE_PORT_ID_END
* Please Place Description here.
*/
enum WDE_DLE_PORT_ID {
WDE_DLE_PORT_ID_DISPATCH = 0,
WDE_DLE_PORT_ID_PKTIN = 1,
WDE_DLE_PORT_ID_CMAC0 = 3,
WDE_DLE_PORT_ID_CMAC1 = 4,
WDE_DLE_PORT_ID_CPU_IO = 6,
WDE_DLE_PORT_ID_WDRLS = 7,
WDE_DLE_PORT_ID_END = 8
};
/**
* @enum PLE_DLE_PORT_ID
*
* @brief PLE_DLE_PORT_ID
*
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_DISPATCH
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_MPDU
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_SEC
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_CMAC0
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_CMAC1
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_WDRLS
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_CPU_IO
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_PLRLS
* Please Place Description here.
* @var PLE_DLE_PORT_ID::PLE_DLE_PORT_ID_END
* Please Place Description here.
*/
enum PLE_DLE_PORT_ID {
PLE_DLE_PORT_ID_DISPATCH = 0,
PLE_DLE_PORT_ID_MPDU = 1,
PLE_DLE_PORT_ID_SEC = 2,
PLE_DLE_PORT_ID_CMAC0 = 3,
PLE_DLE_PORT_ID_CMAC1 = 4,
PLE_DLE_PORT_ID_WDRLS = 5,
PLE_DLE_PORT_ID_CPU_IO = 6,
PLE_DLE_PORT_ID_PLRLS = 7,
PLE_DLE_PORT_ID_END = 8
};
/**
* @enum WDE_DLE_QUEID_PKTIN
*
* @brief WDE_DLE_QUEID_PKTIN
*
* @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC0
* Please Place Description here.
* @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC1
* Please Place Description here.
* @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC2
* Please Place Description here.
* @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_AC3
* Please Place Description here.
* @var WDE_DLE_QUEID_PKTIN::WDE_DLE_QUEID_MSIC
* Please Place Description here.
*/
enum WDE_DLE_QUEID_PKTIN {
WDE_DLE_QUEID_AC0 = 0x0,
WDE_DLE_QUEID_AC1 = 0x1,
WDE_DLE_QUEID_AC2 = 0x2,
WDE_DLE_QUEID_AC3 = 0x3,
WDE_DLE_QUEID_MSIC = 0x4
};
/**
* @enum WDE_DLE_QUEID_CMAC
*
* @brief WDE_DLE_QUEID_CMAC
*
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_BE
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_BK
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_VI
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_ACQ_VO
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_BEACON
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_HIGH
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_MGN_NORMAL
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_MGN_NO_POWER_SAVE
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_MGN_FAST_EDCA
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_BEACON
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_HIGH
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_MGN_NORMAL
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_MGN_NO_POWER_SAVE
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B1_MGN_FAST_EDCA
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_VO
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_VI
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_BE
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM0_F2P_BK
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_VO
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_VI
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_BE
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_WMM1_F2P_BK
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_ULQ
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_TWTQ0
* Please Place Description here.
* @var WDE_DLE_QUEID_CMAC::WDE_DLE_QUEID_B0_TWTQ1
* Please Place Description here.
*/
enum WDE_DLE_QUEID_CMAC {
WDE_DLE_QUEID_ACQ_BE = 0,
WDE_DLE_QUEID_ACQ_BK = 1,
WDE_DLE_QUEID_ACQ_VI = 2,
WDE_DLE_QUEID_ACQ_VO = 3,
WDE_DLE_QUEID_B0_BEACON = 0x10,
WDE_DLE_QUEID_B0_HIGH = 0x11,
WDE_DLE_QUEID_B0_MGN_NORMAL = 0x12,
WDE_DLE_QUEID_B0_MGN_NO_POWER_SAVE = 0x13,
WDE_DLE_QUEID_B0_MGN_FAST_EDCA = 0x14,
WDE_DLE_QUEID_B1_BEACON = 0x18,
WDE_DLE_QUEID_B1_HIGH = 0x19,
WDE_DLE_QUEID_B1_MGN_NORMAL = 0x1A,
WDE_DLE_QUEID_B1_MGN_NO_POWER_SAVE = 0x1B,
WDE_DLE_QUEID_B1_MGN_FAST_EDCA = 0x1C,
WDE_DLE_QUEID_WMM0_F2P_VO = 0x20,
WDE_DLE_QUEID_WMM0_F2P_VI = 0x21,
WDE_DLE_QUEID_WMM0_F2P_BE = 0x22,
WDE_DLE_QUEID_WMM0_F2P_BK = 0x23,
WDE_DLE_QUEID_WMM1_F2P_VO = 0x24,
WDE_DLE_QUEID_WMM1_F2P_VI = 0x25,
WDE_DLE_QUEID_WMM1_F2P_BE = 0x26,
WDE_DLE_QUEID_WMM1_F2P_BK = 0x27,
WDE_DLE_QUEID_B0_ULQ = 0x30,
WDE_DLE_QUEID_B0_TWTQ0 = 0x31,
WDE_DLE_QUEID_B0_TWTQ1 = 0x32
};
/**
* @enum WDE_DLE_QUEID_CPUIO
*
* @brief WDE_DLE_QUEID_CPUIO
*
* @var WDE_DLE_QUEID_CPUIO::WDE_DLE_QUEID_CPUIO_0
* Please Place Description here.
* @var WDE_DLE_QUEID_CPUIO::WDE_DLE_QUEID_CPUIO_1
* Please Place Description here.
*/
enum WDE_DLE_QUEID_CPUIO {
WDE_DLE_QUEID_CPUIO_0 = 0x0,
WDE_DLE_QUEID_CPUIO_1 = 0x1
};
/**
* @enum PLE_DLE_QUEID_CPUIO
*
* @brief PLE_DLE_QUEID_CPUIO
*
* @var PLE_DLE_QUEID_CPUIO::PLE_DLE_QUEID_CPUIO_0
* Please Place Description here.
* @var PLE_DLE_QUEID_CPUIO::PLE_DLE_QUEID_CPUIO_1
* Please Place Description here.
*/
enum PLE_DLE_QUEID_CPUIO {
PLE_DLE_QUEID_CPUIO_0 = 0x0,
PLE_DLE_QUEID_CPUIO_1 = 0x1
};
/**
* @enum WDE_DLE_QUEID_WDRLS
*
* @brief WDE_DLE_QUEID_WDRLS
*
* @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_TXOK
* Please Place Description here.
* @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_DROP_RETRY_LIMIT
* Please Place Description here.
* @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_DROP_LIFETIME_TO
* Please Place Description here.
* @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_DROP_MACID_DROP
* Please Place Description here.
* @var WDE_DLE_QUEID_WDRLS::WDE_DLE_QUEID_NO_REPORT
* Please Place Description here.
*/
enum WDE_DLE_QUEID_WDRLS {
WDE_DLE_QUEID_TXOK = 0x0,
WDE_DLE_QUEID_DROP_RETRY_LIMIT = 0x1,
WDE_DLE_QUEID_DROP_LIFETIME_TO = 0x2,
WDE_DLE_QUEID_DROP_MACID_DROP = 0x3,
WDE_DLE_QUEID_NO_REPORT = 0x4
};
/**
* @enum PLE_DLE_QUEID_PLRLS
*
* @brief PLE_DLE_QUEID_PLRLS
*
* @var PLE_DLE_QUEID_PLRLS::PLE_DLE_QUEID_NO_REPORT
* Please Place Description here.
*/
enum PLE_DLE_QUEID_PLRLS {
PLE_DLE_QUEID_NO_REPORT = 0x0
};
/**
* @enum WDE_DLE_QUOTA_ID
*
* @brief WDE_DLE_QUOTA_ID
*
* @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_HOST_IF
* Please Place Description here.
* @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_WLAN_CPU
* Please Place Description here.
* @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_DATA_CPU
* Please Place Description here.
* @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_PKTIN
* Please Place Description here.
* @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_CPUIO
* Please Place Description here.
* @var WDE_DLE_QUOTA_ID::WDE_DLE_QUOTA_ID_END
* Please Place Description here.
*/
enum WDE_DLE_QUOTA_ID {
WDE_DLE_QUOTA_ID_HOST_IF = 0,
WDE_DLE_QUOTA_ID_WLAN_CPU = 1,
WDE_DLE_QUOTA_ID_DATA_CPU = 2,
WDE_DLE_QUOTA_ID_PKTIN = 3,
WDE_DLE_QUOTA_ID_CPUIO = 4,
WDE_DLE_QUOTA_ID_END = 5
};
/**
* @enum PLE_DLE_QUOTA_ID
*
* @brief PLE_DLE_QUOTA_ID
*
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_BAND0_TXPL
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_BAND1_TXPL
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_C2H
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_H2C
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_WLAN_CPU
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_MPDU
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CMAC0_RX
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CMAC1_RX
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CMAC1_BBRPT
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_WDRLS_RPT
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_CPUIO
* Please Place Description here.
* @var PLE_DLE_QUOTA_ID::PLE_DLE_QUOTA_ID_END
* Please Place Description here.
*/
enum PLE_DLE_QUOTA_ID {
PLE_DLE_QUOTA_ID_BAND0_TXPL = 0,
PLE_DLE_QUOTA_ID_BAND1_TXPL = 1,
PLE_DLE_QUOTA_ID_C2H = 2,
PLE_DLE_QUOTA_ID_H2C = 3,
PLE_DLE_QUOTA_ID_WLAN_CPU = 4,
PLE_DLE_QUOTA_ID_MPDU = 5,
PLE_DLE_QUOTA_ID_CMAC0_RX = 6,
PLE_DLE_QUOTA_ID_CMAC1_RX = 7,
PLE_DLE_QUOTA_ID_CMAC1_BBRPT = 8,
PLE_DLE_QUOTA_ID_WDRLS_RPT = 9,
PLE_DLE_QUOTA_ID_CPUIO = 10,
PLE_DLE_QUOTA_ID_END = 11
};
/**
* @enum CPUIO_CTRL_TYPE
*
* @brief CPUIO_CTRL_TYPE
*
* @var CPUIO_CTRL_TYPE::CPUIO_CTRL_TYPE_WD
* Please Place Description here.
* @var CPUIO_CTRL_TYPE::CPUIO_CTRL_TYPE_PLD
* Please Place Description here.
* @var CPUIO_CTRL_TYPE::CPUIO_CTRL_TYPE_NUM
* Please Place Description here.
*/
enum CPUIO_CTRL_TYPE {
CPUIO_CTRL_TYPE_WD = 0,
CPUIO_CTRL_TYPE_PLD = 1,
CPUIO_CTRL_TYPE_NUM = 2
};
/**
* @enum CPUIO_OP_COMMAND_TYPE
*
* @brief CPUIO_OP_COMMAND_TYPE
*
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_GET_1ST_PID
* Please Place Description here.
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_GET_NEXT_PID
* Please Place Description here.
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_ENQ_TO_TAIL
* Please Place Description here.
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_ENQ_TO_HEAD
* Please Place Description here.
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_DEQ
* Please Place Description here.
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_DEQ_ENQ_ALL
* Please Place Description here.
* @var CPUIO_OP_COMMAND_TYPE::CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL
* Please Place Description here.
*/
enum CPUIO_OP_COMMAND_TYPE {
CPUIO_OP_CMD_GET_1ST_PID = 0,
CPUIO_OP_CMD_GET_NEXT_PID = 1,
CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
CPUIO_OP_CMD_DEQ = 8,
CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
};
/**
* @enum pkt_drop_ac
*
* @brief pkt_drop_ac
*
* @var pkt_drop_ac::PKT_DROP_BE
* Please Place Description here.
* @var pkt_drop_ac::PKT_DROP_BK
* Please Place Description here.
* @var pkt_drop_ac::PKT_DROP_VI
* Please Place Description here.
* @var pkt_drop_ac::PKT_DROP_VO
* Please Place Description here.
* @var pkt_drop_ac::PKT_DROP_AC_LAST
* Please Place Description here.
* @var pkt_drop_ac::PKT_DROP_AC_MAX
* Please Place Description here.
* @var pkt_drop_ac::PKT_DROP_AC_INVALID
* Please Place Description here.
*/
enum pkt_drop_ac {
PKT_DROP_BE = WDE_DLE_QID_BE,
PKT_DROP_BK = WDE_DLE_QID_BK,
PKT_DROP_VI = WDE_DLE_QID_VI,
PKT_DROP_VO = WDE_DLE_QID_VO,
/* keep last */
PKT_DROP_AC_LAST,
PKT_DROP_AC_MAX = PKT_DROP_AC_LAST,
PKT_DROP_AC_INVALID = PKT_DROP_AC_LAST,
};
/*--------------------Define MACRO----------------------------------*/
#define VIRTUAL_ADDRESS_MAPPING(eng_sel, pkt_id, offset) \
(0x00000000 | (((eng_sel) & 0x1) << 27) | \
(((pkt_id) & 0xFFF) << 15) | ((offset) & 0xEFFF))
#define GET_VIRTUAL_ADDRESS_WD(pkt_id, offset)\
((((pkt_id) & 0xFFF) << 15) | ((offset) & 0xEFFF))
/*--------------------Define Struct----------------------------------*/
/**
* @struct cpuio_buf_req_t
* @brief cpuio_buf_req_t
*
* @var cpuio_buf_req_t::len
* Please Place Description here.
* @var cpuio_buf_req_t::pktid
* Please Place Description here.
*/
struct cpuio_buf_req_t {
// input
u16 len;
// output
u16 pktid;
};
/**
* @struct cpuio_ctrl_t
* @brief cpuio_ctrl_t
*
* @var cpuio_ctrl_t::pkt_num
* Please Place Description here.
* @var cpuio_ctrl_t::start_pktid
* Please Place Description here.
* @var cpuio_ctrl_t::end_pktid
* Please Place Description here.
* @var cpuio_ctrl_t::cmd_type
* Please Place Description here.
* @var cpuio_ctrl_t::macid
* Please Place Description here.
* @var cpuio_ctrl_t::src_pid
* Please Place Description here.
* @var cpuio_ctrl_t::src_qid
* Please Place Description here.
* @var cpuio_ctrl_t::dst_pid
* Please Place Description here.
* @var cpuio_ctrl_t::dst_qid
* Please Place Description here.
* @var cpuio_ctrl_t::pktid
* Please Place Description here.
*/
struct cpuio_ctrl_t {
// input
u16 pkt_num;
u16 start_pktid;
u16 end_pktid;
u8 cmd_type;
u8 macid;
u8 src_pid;
u8 src_qid;
u8 dst_pid;
u8 dst_qid;
// output
u16 pktid;
};
/**
* @struct deq_enq_info
* @brief deq_enq_info
*
* @var deq_enq_info::macid
* Please Place Description here.
* @var deq_enq_info::src_pid
* Please Place Description here.
* @var deq_enq_info::src_qid
* Please Place Description here.
* @var deq_enq_info::dst_pid
* Please Place Description here.
* @var deq_enq_info::dst_qid
* Please Place Description here.
* @var deq_enq_info::pktid
* Please Place Description here.
*/
struct deq_enq_info {
u8 macid;
u8 src_pid;
u8 src_qid;
u8 dst_pid;
u8 dst_qid;
u16 pktid;
};
/**
* @struct first_pid_info
* @brief first_pid_info
*
* @var first_pid_info::macid
* Please Place Description here.
* @var first_pid_info::src_pid
* Please Place Description here.
* @var first_pid_info::src_qid
* Please Place Description here.
* @var first_pid_info::pktid
* Please Place Description here.
*/
struct first_pid_info {
u8 macid;
u8 src_pid;
u8 src_qid;
u16 pktid;
};
/**
* @struct next_pid_info
* @brief next_pid_info
*
* @var next_pid_info::macid
* Please Place Description here.
* @var next_pid_info::src_pid
* Please Place Description here.
* @var next_pid_info::src_qid
* Please Place Description here.
* @var next_pid_info::start_pktid
* Please Place Description here.
* @var next_pid_info::pktid
* Please Place Description here.
*/
struct next_pid_info {
u8 macid;
u8 src_pid;
u8 src_qid;
u16 start_pktid;
u16 pktid;
};
/*--------------------Export global variable----------------------------*/
/*--------------------Function declaration-----------------------------*/
/**
* @addtogroup Firmware
* @{
* @addtogroup CPU_IO
* @{
*/
/**
* @brief mac_dle_buf_req_wd
*
* @param *adapter
* @param *buf_req_p
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dle_buf_req_wd(struct mac_ax_adapter *adapter,
struct cpuio_buf_req_t *buf_req_p);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup CPU_IO
* @{
*/
/**
* @brief mac_dle_buf_req_pl
*
* @param *adapter
* @param *buf_req_p
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dle_buf_req_pl(struct mac_ax_adapter *adapter,
struct cpuio_buf_req_t *buf_req_p);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup CPU_IO
* @{
*/
/**
* @brief mac_set_cpuio_wd
*
* @param *adapter
* @param *ctrl_para_p
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_cpuio_wd(struct mac_ax_adapter *adapter,
struct cpuio_ctrl_t *ctrl_para_p);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup CPU_IO
* @{
*/
/**
* @brief mac_set_cpuio_pl
*
* @param *adapter
* @param *ctrl_para_p
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_cpuio_pl(struct mac_ax_adapter *adapter,
struct cpuio_ctrl_t *ctrl_para_p);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup CPU_IO
* @{
*/
/**
* @brief mac_wde_pkt_drop
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_wde_pkt_drop(struct mac_ax_adapter *adapter,
struct mac_ax_pkt_drop_info *info);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/cpuio.h
|
C
|
agpl-3.0
| 18,188
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "dbg_cmd.h"
const char *MallocIDName[eMallocMAX] = {
"OS",
"Common",
"Task",
"AXIDMA",
"SPIC",
"Timer",
"UART",
"H2C",
"C2H",
"DBG",
"Role",
"PS",
"WoWLAN",
"Sec",
"Ofld",
"TX",
"RX",
"Report",
"PHYDM",
"RF",
"BTCoex",
"SCSI",
"Free"
};
const char *MallocTypeName[eMallocTypeMAX] = {
"N/A",
"Fixed",
"Dynamic"
};
const char *ISRName[ISRStatistic_MAX] = {
/* First layer */
// WDTISRROM8852A
"WDT",
// CMACISRROM8852A
"CMAC0",
"CMAC1",
"CMAC2",
"CMAC3",
"CMAC4",
"CMAC5",
"CMAC6",
"CMAC7",
"CMAC8",
"CMAC9",
"CMAC10",
// DMACISRROM8852A
"DMAC0",
"DMAC1",
"DMAC2",
// SysISRROM8852A
"SYS0",
// DataHDLISRROM8852A
"IPSec",
"AXIDMA",
"IDDMA",
// PlatISRROM8852A
"MACErr",
"UART",
"RXI300",
/* Second layer */
"DMAC0_GT0",
"DMAC0_GT1",
"DMAC0_GT2_3",
"DMAC0_H2C",
"SYS0_HALT_H2C",
"SYS0_GPIO",
"MACErr_DMAC",
"MACErr_CMAC0",
"MACErr_CMAC1"
};
// gerrit test 5
static const struct mac_hal_cmd_info mac_hal_cmd_i[] = {
{"-h", MAC_HAL_HELP, cmd_mac_help},
{"dd_dbg", MAC_MAC_DD_DBG, cmd_mac_dbg_dump},/*@do not move this element to other position*/
{"reg_dump", MAC_MAC_REG_DUMP, cmd_mac_reg_dump},
{"fw_dbg", MAC_MAC_FW_DBG, cmd_mac_fw_dump},
{"help", MAC_HAL_HELP, cmd_mac_help},
{"fw_log", MAC_MAC_FW_LOG, cmd_mac_fw_log_cfg},
{"fw_curtcb", MAC_MAC_FW_CURTCB, cmd_mac_fw_curtcb},
{"fw_info", MAC_MAC_FW_INFO, cmd_mac_fw_status_parser},
{"dl_sym", MAC_MAC_DL_SYM, cmd_mac_dl_sym}
/*@do not move this element to other position*/
};
static const struct mac_hal_cmd_info mac_fw_status_cmd_i[] = {
{"task", FW_STATUS_TASKINFO},
{"flash", FW_STATUS_FLASHINFO},
{"heap", FW_STATUS_HEAPINFO},
{"mem_fast", FW_STATUS_MEMINFO_FAST},
{"mem_slow", FW_STATUS_MEMINFO_SLOW},
{"ps", FW_STATUS_PSINFO},
{"h2c_c2h", FW_STATUS_H2C_C2HINFO},
{"isr", FW_STATUS_ISRINFO}
};
static const char * const type_names[] = {
"level",
"output",
"comp",
"comp_ext",
NULL
};
static struct fw_status_proc_class fw_status_proc_sys[] = {
{FW_STATUS_TASKINFO, fw_status_taskinfo_handler},
{FW_STATUS_FLASHINFO, fw_status_flashinfo_handler},
{FW_STATUS_HEAPINFO, fw_status_heapinfo_handler},
{FW_STATUS_MEMINFO_FAST, fw_status_meminfo_fast_handler},
{FW_STATUS_MEMINFO_SLOW, fw_status_meminfo_slow_handler},
{FW_STATUS_PSINFO, fw_status_psinfo_handler},
{FW_STATUS_H2C_C2HINFO, fw_status_h2c_c2hinfo_handler},
{FW_STATUS_ISRINFO, fw_status_isrinfo_handler},
{FW_STATUS_MAX, NULL},
};
u32 cmd_mac_help(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used)
{
u32 hal_cmd_ary_size = sizeof(mac_hal_cmd_i) / sizeof(struct mac_hal_cmd_info);
u32 i;
//PLTFM_MSG_TRACE("HAL cmd ==>\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, "HAL cmd ==>\n");
for (i = 0; i < hal_cmd_ary_size - 1; i++) {
//PLTFM_MSG_TRACE(" %-5d: %s\n",
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, " %-5d: %s\n",
i, mac_hal_cmd_i[i + 1].name);
}
return MACSUCCESS;
}
u32 cmd_mac_dbg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used)
{
//struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = adapter;
//struct mac_ax_ops *ops = mac->ops;
struct mac_ax_dbgpkg ss_dbg = {0};
struct mac_ax_dbgpkg_en dbg_msk = {0};
ss_dbg.ss_dbg_0 = 0;
ss_dbg.ss_dbg_1 = 0;
dbg_msk.ss_dbg = 1;
dbg_msk.dle_dbg = 1;
dbg_msk.dmac_dbg = 1;
dbg_msk.cmac_dbg = 1;
dbg_msk.mac_dbg_port = 1;
mac_dbg_status_dump(mac, &ss_dbg, &dbg_msk);
//PLTFM_MSG_TRACE("rtw_hal_mac_dbg_dump(): ss_dbg.ss_dbg_0 = 0x%08X,
// ss_dbg.ss_dbg_1 = 0x%08X\n",
// ss_dbg.ss_dbg_0, ss_dbg.ss_dbg_1);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"rtw_hal_mac_dbg_dump(): ss_dbg.ss_dbg_0 = 0x%08X,ss_dbg.ss_dbg_1 = 0x%08X\n",
ss_dbg.ss_dbg_0, ss_dbg.ss_dbg_1);
return MACSUCCESS;
}
u32 cmd_mac_reg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used)
{
u32 ret = MACSUCCESS, val = 0;
// input argument start from input[1], input[0] is mac_hal_cmd_info.name
if (input_num < 2) {
//PLTFM_MSG_TRACE("invalid argument\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"invalid argument\n");
return MACFWSTATUSFAIL;
}
//PLTFM_SSCANF(input[1], "%d", &val);
val = PLTFM_STRTOUL(input[1], 10);
//PLTFM_MSG_TRACE("%s: sel:%d\n", __func__, val);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s: sel:%d\n", __func__, val);
ret = mac_reg_dump(adapter, (enum mac_ax_reg_sel)val);
return ret;
}
void cmd_mac_get_version(struct mac_ax_adapter *adapter, char *ver_str, u16 len)
{
PLTFM_SNPRINTF(ver_str, len, "V%u.%u.%u.%u",
MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER,
MAC_AX_SUB_VER, MAC_AX_SUB_INDEX);
}
void cmd_mac_get_fw_ver(struct mac_ax_adapter *adapter, char *ver_str, u16 len)
{
PLTFM_SNPRINTF(ver_str, len, "V%u.%u.%u.%u",
adapter->fw_info.major_ver, adapter->fw_info.minor_ver,
adapter->fw_info.sub_ver, adapter->fw_info.sub_idx);
}
u32 cmd_mac_fw_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used)
{
//struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 i;
char mac_ver[20], fw_ver[20];
cmd_mac_get_version(adapter, mac_ver, sizeof(mac_ver));
//PLTFM_MSG_TRACE("HALMAC version %s\n", mac_ver);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"HALMAC version %s\n", mac_ver);
cmd_mac_get_fw_ver(adapter, fw_ver, sizeof(fw_ver));
//PLTFM_MSG_TRACE("FW version %s\n", fw_ver);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"FW version %s\n", fw_ver);
/* dump dbg reg */
//PLTFM_MSG_TRACE("0x01f4[31:0] = 0x%08x\n", MAC_REG_R32(0x01f4));
//PLTFM_MSG_TRACE("0x01fc[31:0] = 0x%08x\n", MAC_REG_R32(0x01fc));
//PLTFM_MSG_TRACE("0x8424[31:0] = 0x%08x\n", MAC_REG_R32(0x8424));
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"0x01f4[31:0] = 0x%08x\n", MAC_REG_R32(0x01f4));
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"0x01fc[31:0] = 0x%08x\n", MAC_REG_R32(0x01fc));
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"0x8424[31:0] = 0x%08x\n", MAC_REG_R32(0x8424));
/* dump fw pc */
MAC_REG_W32(0x58, 0xf200f2);
MAC_REG_W8(0xf6, 0x1);
for (i = 0; i < 15; i++) {
//PLTFM_MSG_TRACE("0x00c0[31:0] = 0x%08x\n", MAC_REG_R32(0xc0));
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"0x00c0[31:0] = 0x%08x\n", MAC_REG_R32(0xc0));
PLTFM_DELAY_MS(1);
}
return MACSUCCESS;
}
static void cmd_mac_fw_log_set(struct mac_ax_fw_log *fl_cfg, u8 type, u32 value)
{
switch (type) {
case FWDGB_CFG_TYPE_LEVEL:
fl_cfg->level = value;
break;
case FWDGB_CFG_TYPE_OUTPUT:
fl_cfg->output |= value;
break;
case FWDGB_CFG_TYPE_COMP:
fl_cfg->comp |= value;
break;
case FWDGB_CFG_TYPE_COMP_EXT:
fl_cfg->comp_ext |= value;
break;
default:
break;
}
}
static void cmd_mac_fw_log_clr(struct mac_ax_fw_log *fl_cfg, u8 type, u32 value)
{
switch (type) {
case FWDGB_CFG_TYPE_LEVEL:
break;
case FWDGB_CFG_TYPE_OUTPUT:
fl_cfg->output &= (~value);
break;
case FWDGB_CFG_TYPE_COMP:
fl_cfg->comp &= (~value);
break;
case FWDGB_CFG_TYPE_COMP_EXT:
fl_cfg->comp_ext &= (~value);
break;
default:
break;
}
}
u32 cmd_mac_fw_log_cfg_set(struct mac_ax_adapter *adapter,
struct mac_ax_fw_log *log_cfg, char *output, u32 out_len, u32 *used)
{
//struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = adapter;
//struct mac_ax_fw_log log_cfg = {0};
u32 status;
if (!mac)
return MACFWSTATUSFAIL;
//log_cfg.level = fl_cfg->level;
//log_cfg.output = fl_cfg->output;
//log_cfg.comp = fl_cfg->comp;
//log_cfg.comp_ext = fl_cfg->comp_ext;
/*
*PLTFM_MSG_TRACE("Configuring firmware log level %d, output 0x%08x, "
* "comp 0x%08x, comp ext 0x%08x.\n",
* log_cfg->level,
* log_cfg->output,
* log_cfg->comp,
* log_cfg->comp_ext);
*/
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Config firmware log level %d,output 0x%08x,comp 0x%08x,comp ext 0x%08x.\n",
log_cfg->level,
log_cfg->output,
log_cfg->comp,
log_cfg->comp_ext);
if (log_cfg->output & MAC_AX_FL_LV_UART) {
//PLTFM_MSG_TRACE("%s: Enabling UART...\n", __func__);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s: Enabling UART...\n", __func__);
mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_TX_GPIO5);
mac->ops->sel_uart_tx_pin(mac, MAC_AX_UART_TX_GPIO5);
mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_RX_GPIO6);
mac->ops->sel_uart_rx_pin(mac, MAC_AX_UART_RX_GPIO6);
}
status = mac->ops->fw_log_cfg(mac, log_cfg);
if (status != MACSUCCESS) {
//PLTFM_MSG_TRACE("%s fault, status = %d.\n", __func__, status);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s fault, status = %d.\n", __func__, status);
//return status;
}
return status;
}
u32 cmd_mac_fw_log_cfg(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used)
{
//struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)adapter->drv_adapter;
//struct rtw_hal_fw_log_cfg *fl_cfg = &hal_com->fw_log_cfg;
/* TYPE VALUE(HEX) 1(SET)|2(CLEAR) */
struct mac_ax_fw_log *plog_cfg = &adapter->log_cfg;
u8 type = 0;
u32 op = FWDGB_CFG_OP_INFO, value = 0;
if (input_num == 4) {
//PLTFM_MSG_TRACE("%s,%s,%s\n", input[1], input[2], input[3]);
while (type_names[type]) {
if (PLTFM_STRCMP(input[1], type_names[type]) == 0)
break;
type++;
}
if (!type_names[type]) {
//PLTFM_MSG_TRACE("Invalid type \"%s\"\n", input[1]);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Invalid type \"%s\"\n", input[1]);
return MACFWSTATUSFAIL;
}
//PLTFM_SSCANF(input[2], "%x", &value);
value = PLTFM_STRTOUL(input[2], 16);
//PLTFM_SSCANF(input[3], "%d", &op);
op = PLTFM_STRTOUL(input[3], 10);
//PLTFM_MSG_TRACE("value = 0x%x, op = %d\n", value, op);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"value = 0x%x, op = %d\n", value, op);
if (op == 1)
op = FWDGB_CFG_OP_SET;
else if (op == 2)
op = FWDGB_CFG_OP_CLR;
else
op = FWDGB_CFG_OP_INFO;
} else {
//PLTFM_MSG_TRACE("invalid argument\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"invalid argument\n");
return MACFWSTATUSFAIL;
}
switch (op) {
case FWDGB_CFG_OP_SET:
cmd_mac_fw_log_set(plog_cfg, type, value);
break;
case FWDGB_CFG_OP_CLR:
cmd_mac_fw_log_clr(plog_cfg, type, value);
break;
case FWDGB_CFG_OP_INFO:
//default:
//_hal_fw_log_info(&log_cfg);
//PLTFM_MSG_TRACE("fw_log invalid op\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"fw_log invalid op\n");
return MACFWSTATUSFAIL;
}
return cmd_mac_fw_log_cfg_set(adapter, plog_cfg, output, out_len, used);
}
u32 cmd_mac_fw_curtcb(struct mac_ax_adapter *adapter,
char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 curtcb, index, val32;
char task_name[FW_MAX_TASK_NAME_LEN];
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, FW_CURTCB_8852A);
} else {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Doesn't support this chip now!\n");
return MACSUCCESS;
}
curtcb = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY);
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, (curtcb & 0x1fffffff));
val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY +
FW_CURTCB_SP_START_OFFSET);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"[FW]Start of the stack = 0x%08x\n", val32);
for (index = 0; index < 16 ; index = index + 4) {
val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY +
FW_CURTCB_TASK_NAME_OFFSET + index);
PLTFM_MEMCPY((u8 *)&task_name[index], (u8 *)&val32, 4);
}
task_name[FW_MAX_TASK_NAME_LEN - 1] = '\0';
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"[FW]Current task name = %s\n", task_name);
return MACSUCCESS;
}
u32 cmd_mac_fw_status_parser(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV],
u32 input_num, char *output, u32 out_len, u32 *used)
{
u32 i, cmd_strlen;
char *fw_status_cmd;
u16 id = FWSTATUS_OPCODE_MASK;
struct mac_ax_fwstatus_payload data;
u32 hal_cmd_ary_size = sizeof(mac_fw_status_cmd_i) / sizeof(struct mac_hal_cmd_info);
if (input_num < 2) {
//PLTFM_MSG_TRACE("fw status invalid op code\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"fw status invalid op code\n");
return MACFWSTATUSFAIL;
}
/* Parsing Cmd ID */
fw_status_cmd = input[1];
cmd_strlen = PLTFM_STRLEN(fw_status_cmd);
for (i = 0; i < cmd_strlen; i++) {
if (*fw_status_cmd == '\n')
*fw_status_cmd = '\0';
fw_status_cmd++;
}
for (i = 0; i < hal_cmd_ary_size; i++) {
//PLTFM_MSG_TRACE("[FW STATUS]input string : [%s], input_num = %d\n",
// input[1], input_num);
//PLTFM_MSG_TRACE("mac_fw_status_cmd_i[i].name : [%s]",mac_fw_status_cmd_i[i].name);
//MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
// "[FW STATUS]input string : [%s], input_num = %d\n",
// input[1], input_num);
//MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
// "mac_fw_status_cmd_i[i].name : [%s]", mac_fw_status_cmd_i[i].name);
if (PLTFM_STRCMP(mac_fw_status_cmd_i[i].name, input[1]) == 0) {
id = mac_fw_status_cmd_i[i].id;
//PLTFM_MSG_TRACE("enter fw status dbg %s\n", mac_fw_status_cmd_i[i].name);
//MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
// "enter fw status dbg %s\n", mac_fw_status_cmd_i[i].name);
break;
}
}
if (i == hal_cmd_ary_size) {
//PLTFM_MSG_TRACE("FW STATUS command not found!\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"FW STATUS command not found!\n");
return MACFWSTATUSFAIL;
}
// gen h2c
data.dword0 = (u32)id;
data.dword1 = FWSTATUS_OPCODE_MASK;
if (mac_fw_status_cmd(adapter, &data)) {
//PLTFM_MSG_TRACE("FW STATUS H2C Fail!\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"FW STATUS H2C Fail!\n");
return MACFWSTATUSFAIL;
}
return MACSUCCESS;
}
u32 cmd_mac_dl_sym(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV],
u32 input_num, char *output, u32 out_len, u32 *used)
{
#if MAC_AX_FEATURE_DBGDEC
u32 val, ret;
struct mac_ax_adapter *mac = adapter;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 *symbol_ptr = NULL;
u32 file_size = 0;
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"down symbol.bin\n");
// input argument start from input[1], input[0] is mac_hal_cmd_info.name
if (input_num < 2) {
//PLTFM_MSG_TRACE("invalid argument\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"invalid argument\n");
return MACFWSTATUSFAIL;
}
//PLTFM_SSCANF(input[1], "%d", &val);
val = PLTFM_STRTOUL(input[1], 10);
if (val == 1) {
// download file
// PLTFM_DL file, assign symbol_ptr and file_size
switch (hw_info->chip_id) {
#if MAC_AX_8852A_SUPPORT
case MAC_AX_CHIP_ID_8852A:
ret = PLTFM_LD_FW_SYMBOL("hal8852a_msg_symbol.bin", &symbol_ptr,
&file_size);
break;
#endif
#if MAC_AX_8852B_SUPPORT
case MAC_AX_CHIP_ID_8852B:
ret = PLTFM_LD_FW_SYMBOL("hal8852b_msg_symbol.bin", &symbol_ptr,
&file_size);
break;
#endif
#if MAC_AX_8852C_SUPPORT
case MAC_AX_CHIP_ID_8852C:
ret = PLTFM_LD_FW_SYMBOL("hal8852c_msg_symbol.bin", &symbol_ptr,
&file_size);
break;
#endif
default:
return MACFWSTATUSFAIL;
break;
}
if (ret != MACSUCCESS) {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"reading fw failed !!!\n");
return MACFWSTATUSFAIL;
}
ret = mac->ops->fw_log_set_array(adapter, (void *)symbol_ptr, file_size);
if (ret != MACSUCCESS) {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"load symbol failed\n");
return MACFWSTATUSFAIL;
}
} else if (val == 0) {
//release file
ret = mac->ops->fw_log_unset_array(adapter);
if (ret != MACSUCCESS)
return MACFWSTATUSFAIL;
}
return MACSUCCESS;
#endif
}
s32 mac_halmac_cmd(struct mac_ax_adapter *adapter, char *input, char *output, u32 out_len)
{
char *token;
u32 argc = 0;
char argv[MAC_MAX_ARGC][MAC_MAX_ARGV];
if (output) {
adapter->fw_dbgcmd.buf = output;
adapter->fw_dbgcmd.out_len = out_len;
adapter->fw_dbgcmd.used = 0;
} else {
PLTFM_MSG_TRACE("%s invalid argument\n", __func__);
return MACFWSTATUSFAIL;
}
do {
token = PLTFM_STRSEP(&input, ", ");
if (token) {
if (PLTFM_STRLEN(token) <= MAC_MAX_ARGV)
PLTFM_STRCPY(argv[argc], token);
argc++;
} else {
break;
}
} while (argc < MAC_MAX_ARGC);
mac_halmac_cmd_parser(adapter, argv, argc, output, out_len);
return MACSUCCESS;
}
void mac_halmac_cmd_parser(struct mac_ax_adapter *adapter,
char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len)
{
u32 hal_cmd_ary_size = sizeof(mac_hal_cmd_i) / sizeof(struct mac_hal_cmd_info);
u32 i = 0;
u32 *used;
adapter->fw_dbgcmd.used = 0;
used = &adapter->fw_dbgcmd.used;
//struct mac_ax_fwstatus_payload data;
if (hal_cmd_ary_size == 0)
return;
/* Parsing Cmd ID */
if (input_num) {
for (i = 0; i < hal_cmd_ary_size; i++) {
//PLTFM_MSG_TRACE("input string : %s\n, input_num = %d",
// input[0], input_num);
if (PLTFM_STRCMP(mac_hal_cmd_i[i].name, input[0]) == 0) {
//PLTFM_MSG_TRACE("enter hal dbg %s\n", mac_hal_cmd_i[i].name);
//MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
//"enter hal dbg %s\n", mac_hal_cmd_i[i].name);
if (mac_hal_cmd_i[i].handler(adapter, input, input_num,
output, out_len, used)) {
//PLTFM_MSG_TRACE("%s command process error\n",
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
mac_hal_cmd_i[i].name);
}
PLTFM_DELAY_MS(200);
break;
}
}
if (i == hal_cmd_ary_size) {
//PLTFM_MSG_TRACE("HAL command not found!\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"HAL command not found!\n");
return;
}
}
PLTFM_MSG_TRACE("-----------------------%s function return\n", __func__);
}
u32 c2h_fw_status(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
//struct c2h_proc_func *proc = c2h_proc_sys_palt_autotest;
//u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
// struct rtw_c2h_info *info) = NULL;
u32 hdr0, ret = MACSUCCESS;
u32 func, pkt_cnt, i;
u8 *content;
struct fw_status_pkt pkt_info;
struct fw_status_proc_class *proc = fw_status_proc_sys;
//PLTFM_MSG_TRACE("[--------------------]%s\n", __func__);
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
//set info
info->c2h_cat = GET_FIELD(hdr0, C2H_HDR_CAT);
info->c2h_class = GET_FIELD(hdr0, C2H_HDR_CLASS);
info->c2h_func = GET_FIELD(hdr0, C2H_HDR_FUNC);
//info->done_ack = 0;
//info->rec_ack = 0;
info->content = buf + FWCMD_HDR_LEN;
//info->h2c_return = info->c2h_data[1];
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
if (func == FWCMD_C2H_FUNC_FW_STATUS) {
pkt_cnt = le32_to_cpu(*((u32 *)info->content));
//PLTFM_MSG_TRACE("[------------------pkt_cnt--] %d\n", pkt_cnt);
content = info->content + LEN_PKTCNT;
for (i = 0; i < pkt_cnt; i++) {
proc = fw_status_proc_sys;
pkt_info.op_code = le32_to_cpu(*((u32 *)(content)));
//PLTFM_MSG_TRACE("[------------------op_code--] %d\n", pkt_info.op_code);
content += LEN_OPCODE;
pkt_info.length = le32_to_cpu(*((u32 *)(content)));
//PLTFM_MSG_TRACE("[------------------length--] %d\n", pkt_info.length);
content += LEN_LENGTH;
pkt_info.data = content;
content += pkt_info.length;
for (; proc->id != FW_STATUS_MAX; proc++) {
if (GET_FIELD_OPCODE(pkt_info.op_code) == proc->id) {
ret = proc->handler(adapter, pkt_info.data,
pkt_info.length);
}
}
}
}
return ret;
}
u32 fw_status_taskinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
u32 ret = MACSUCCESS;
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
u32 remain_len = out_len - *used;
if (len > remain_len)
return MACFWSTATUSFAIL;
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\tCnt\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"-------------------------------------------\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s\n", (const char *)buf);
//PLTFM_MSG_TRACE("Task\t\tState\tPrio\tStack start\tMin Stack(DW)\tNum\n");
//PLTFM_MSG_TRACE("-------------------------------------------\n");
//PLTFM_MSG_TRACE("%s", (const char *)buf);
return ret;
}
u32 fw_status_flashinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
struct flash_info flashinfo;
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
u32 remain_len = out_len - *used;
if (len > remain_len)
return MACFWSTATUSFAIL;
//PLTFM_MSG_TRACE("[--------------------]%s\n", __func__);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"[--------------------]%s\n", __func__);
PLTFM_MEMCPY(&flashinfo, buf, sizeof(struct flash_info));
//PLTFM_MSG_TRACE("b1InitDone : %d\n", flashinfo.b1initdone);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"b1InitDone : %d\n", flashinfo.b1initdone);
//PLTFM_MSG_TRACE("u1FlashType : %d\n", flashinfo.u1flashtype);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"u1FlashType : %d\n", flashinfo.u1flashtype);
//PLTFM_MSG_TRACE("u4FlashSize : %d\n", flashinfo.u4flashsize);
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"u4FlashSize : %d\n", flashinfo.u4flashsize);
return MACSUCCESS;
}
u32 fw_status_heapinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
u32 ret = MACSUCCESS;
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
u32 remain_len = out_len - *used;
if (len > remain_len)
return MACFWSTATUSFAIL;
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Index\tStart\t\tTotal(B)\tFree(B)\tMin Free(B)\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"-------------------------------------------\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s", (const char *)buf);
return ret;
}
u32 fw_status_meminfo_fast_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
struct mem_info *mem_info;
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
u32 remain_len = out_len - *used;
if (len > remain_len)
return MACFWSTATUSFAIL;
mem_info = (struct mem_info *)buf;
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Fast Heap:\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Owner ID\tType\t\tTotalSize(B)\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"------------------------------------------------\n");
while (mem_info->total_size != 0) {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, "%s\t\t%s\t\t%u\r\n",
MallocIDName[mem_info->owner_id],
MallocTypeName[mem_info->owner_type],
mem_info->total_size);
mem_info++;
}
return MACSUCCESS;
}
u32 fw_status_meminfo_slow_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
struct mem_info *mem_info;
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
u32 remain_len = out_len - *used;
if (len > remain_len)
return MACFWSTATUSFAIL;
mem_info = (struct mem_info *)buf;
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Slow Heap:\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"Owner ID\tType\t\tTotalSize(B)\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"------------------------------------------------\n");
while (mem_info->total_size != 0) {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used, "%s\t\t%s\t\t%u\r\n",
MallocIDName[mem_info->owner_id],
MallocTypeName[mem_info->owner_type],
mem_info->total_size);
mem_info++;
}
return MACSUCCESS;
}
u32 fw_status_psinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
// Not support now
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"[Err]\n");
return MACFWSTATUSFAIL;
}
u32 fw_status_h2c_c2hinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
// Not support now
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"[Err]\n");
return MACFWSTATUSFAIL;
}
u32 fw_status_isrinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len)
{
struct isr_info *isr_info;
char *output = adapter->fw_dbgcmd.buf;
u32 *used = &adapter->fw_dbgcmd.used;
u32 out_len = adapter->fw_dbgcmd.out_len;
u32 remain_len = out_len - *used;
u32 i;
if (len > remain_len)
return MACFWSTATUSFAIL;
isr_info = (struct isr_info *)buf;
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"ISR Name\tCount\t\tExec Time(historical high)\n");
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"------------------------------------------------\n");
for (i = ISRStatistic_WDT; i < ISRStatistic_MAX; i++) {
if (i >= ISRStatistic_DMAC0_GT0) {
if (i == ISRStatistic_DMAC0_GT0) {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"------------------------------------------------\n");
}
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s\t%u\t\t%u_%u\n", ISRName[i],
isr_info->ISRCnt[i], isr_info->ISRExecTimeMax_hi[i],
isr_info->ISRExecTimeMax_lo[i]);
} else {
MAC_DBG_MSG(out_len, *used, output + *used, out_len - *used,
"%s\t\t%u\t\t%u_%u\n", ISRName[i],
isr_info->ISRCnt[i], isr_info->ISRExecTimeMax_hi[i],
isr_info->ISRExecTimeMax_lo[i]);
}
}
return MACSUCCESS;
}
#if MAC_AX_FEATURE_DBGDEC
static void fw_log_private_dump(struct mac_ax_adapter *adapter, u32 *buf, u32 msgno,
u8 para_num, u8 isint, char *str_buf)
{
// check data integrity
switch (para_num) {
case 1:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf));
break;
case 2:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)));
break;
case 3:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)));
break;
case 4:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)));
break;
case 5:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)));
break;
case 6:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)));
break;
case 7:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)));
break;
case 8:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)));
break;
case 9:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)));
break;
case 10:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)));
break;
case 11:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)));
break;
case 12:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)));
break;
case 13:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)));
break;
case 14:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)),
le32_to_cpu(*(u32 *)(buf + 13)));
break;
case 15:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)),
le32_to_cpu(*(u32 *)(buf + 13)),
le32_to_cpu(*(u32 *)(buf + 14)));
break;
case 16:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)",
msgno,
isint,
para_num,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)),
le32_to_cpu(*(u32 *)(buf + 13)),
le32_to_cpu(*(u32 *)(buf + 14)),
le32_to_cpu(*(u32 *)(buf + 15)));
break;
default:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d)",
msgno,
isint,
para_num);
break;
}
PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf);
//PLTFM_FREE(str_buf, H2C_LONG_DATA_LEN);
//return;
}
static void fw_log_int_dump(struct mac_ax_adapter *adapter, u32 *buf, u32 msg_array_idx,
u8 para_num, char *str_buf)
{
// check data integrity
switch (para_num) {
case 1:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf));
break;
case 2:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)));
break;
case 3:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)));
break;
case 4:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)));
break;
case 5:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)));
break;
case 6:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)));
break;
case 7:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)));
break;
case 8:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)));
break;
case 9:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)));
break;
case 10:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)));
break;
case 11:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)));
break;
case 12:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)));
break;
case 13:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)));
break;
case 14:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)),
le32_to_cpu(*(u32 *)(buf + 13)));
break;
case 15:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)),
le32_to_cpu(*(u32 *)(buf + 13)),
le32_to_cpu(*(u32 *)(buf + 14)));
break;
case 16:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
le32_to_cpu(*(u32 *)buf),
le32_to_cpu(*(u32 *)(buf + 1)),
le32_to_cpu(*(u32 *)(buf + 2)),
le32_to_cpu(*(u32 *)(buf + 3)),
le32_to_cpu(*(u32 *)(buf + 4)),
le32_to_cpu(*(u32 *)(buf + 5)),
le32_to_cpu(*(u32 *)(buf + 6)),
le32_to_cpu(*(u32 *)(buf + 7)),
le32_to_cpu(*(u32 *)(buf + 8)),
le32_to_cpu(*(u32 *)(buf + 9)),
le32_to_cpu(*(u32 *)(buf + 10)),
le32_to_cpu(*(u32 *)(buf + 11)),
le32_to_cpu(*(u32 *)(buf + 12)),
le32_to_cpu(*(u32 *)(buf + 13)),
le32_to_cpu(*(u32 *)(buf + 14)),
le32_to_cpu(*(u32 *)(buf + 15)));
break;
default:
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg);
break;
}
PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf);
//return;
}
u32 fw_log_scan_array(struct mac_ax_adapter *adapter, u32 msgno)
{
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u32 i = 0, msg_last, array_size;
if (adapter->fw_log_array_dl_size) {
array_size = adapter->fw_log_array_dl_size / sizeof(struct mac_fw_msg);
for (i = 0; i < array_size ; i++) {
if (adapter->fw_log_array[i].msgno == msgno)
return i;
}
return 0;
} else {
switch (hw_info->chip_id) {
#if MAC_AX_8852A_SUPPORT
case MAC_AX_CHIP_ID_8852A:
msg_last = MSG_8852A_LAST;
break;
#endif
#if MAC_AX_8852B_SUPPORT
case MAC_AX_CHIP_ID_8852B:
msg_last = MSG_8852B_LAST;
break;
#endif
#if MAC_AX_8852C_SUPPORT
case MAC_AX_CHIP_ID_8852C:
msg_last = MSG_8852C_LAST;
break;
#endif
default:
PLTFM_MSG_WARN("array not exist\n");
return 0;
}
if (msgno >= msg_last)
return 0;
while (adapter->fw_log_array[i].msgno != msg_last) {
if (adapter->fw_log_array[i].msgno == msgno)
return i;
i++;
}
return 0;
}
}
void fw_log_set_array(struct mac_ax_adapter *adapter)
{
struct mac_ax_hw_info *hw_info = adapter->hw_info;
switch (hw_info->chip_id) {
#if MAC_AX_8852A_SUPPORT
case MAC_AX_CHIP_ID_8852A:
adapter->fw_log_array = fw_log_8852a;
break;
#endif
#if MAC_AX_8852B_SUPPORT
case MAC_AX_CHIP_ID_8852B:
adapter->fw_log_array = fw_log_8852b;
break;
#endif
#if MAC_AX_8852C_SUPPORT
case MAC_AX_CHIP_ID_8852C:
adapter->fw_log_array = fw_log_8852c;
break;
#endif
default:
return;
}
}
void fw_log_dump(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u8 syntax_3, isint, fileno;
u32 msgno_0, msgno_1, msgno_2, msgno_3;
u16 lineno_0, lineno_1;
u8 para_num, paranum_idx, color;
u32 msgno, msg_array_idx;
u16 lineno;
u8 *para;
char str_buf[STR_BUF_SIZE];
if (!adapter->fw_log_array)
fw_log_set_array(adapter);
if (!adapter->fw_log_array) {
PLTFM_MSG_ERR("[ERR]unsupported fw_log_array\n");
return;
}
color = (*(buf + FWCMD_HDR_LEN + 2)) >> 1;
isint = (color & BIT1) >> 1;
paranum_idx = color & BIT0;
syntax_3 = *(buf + FWCMD_HDR_LEN + 3);
msgno_0 = (u32)*(buf + FWCMD_HDR_LEN + 4);
msgno_1 = (u32)*(buf + FWCMD_HDR_LEN + 5);
msgno_2 = (u32)*(buf + FWCMD_HDR_LEN + 6);
msgno_3 = (u32)*(buf + FWCMD_HDR_LEN + 7);
msgno = (msgno_0 & 0x000000ff) |
((msgno_1 & 0x000000ff) << 8) |
((msgno_2 & 0x000000ff) << 16) |
((msgno_3 & 0x000000ff) << 24);
fileno = *(buf + FWCMD_HDR_LEN + 8);
lineno_0 = (u16)*(buf + FWCMD_HDR_LEN + 9);
lineno_1 = (u16)*(buf + FWCMD_HDR_LEN + 10);
lineno = (lineno_0 & 0x00ff) | ((lineno_1 & 0x00ff) << 8);
if (paranum_idx) {
para_num = *(buf + FWCMD_HDR_LEN + 11);
para = (buf + FWCMD_HDR_LEN + 12);
} else {
para_num = 0;
para = NULL;
}
PLTFM_MEMSET(str_buf, 0, STR_BUF_SIZE);
#if 0
str_buf = (char *)PLTFM_MALLOC(H2C_LONG_DATA_LEN);
if (!str_buf) {
PLTFM_MSG_WARN("fw_log_int_dump str_buf 0\n");
return;
}
#endif
msg_array_idx = fw_log_scan_array(adapter, msgno);
//PLTFM_MSG_WARN("%s, msgno = %d, idx = %d, isint = %d, para_num = %d\n",
//__FUNCTION__, msgno, msg_array_idx, isint, para_num);
if (isint == 0 && para_num != 0 && msg_array_idx != 0) {
if (buf[len - 1] != '\0')
buf[len - 1] = '\0';
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
adapter->fw_log_array[msg_array_idx].msg,
(char *)(buf + FWCMD_HDR_LEN + 12));
PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf);
} else if (msg_array_idx != 0 && isint == 1) {
fw_log_int_dump(adapter, (u32 *)para, msg_array_idx, para_num, str_buf);
} else {
// print specific message and msgno, parameters
if (isint == 1) {
fw_log_private_dump(adapter, (u32 *)para, msgno, para_num, isint, str_buf);
} else if (para_num != 0) {
PLTFM_SNPRINTF(str_buf, STR_BUF_SIZE,
"fw_enc(%d,%d,%d,%s)",
msgno,
isint,
para_num,
(char *)(buf + FWCMD_HDR_LEN + 12));
PLTFM_MSG_ALWAYS("C2H log: %s\n", str_buf);
}
}
//return;
}
u8 *fw_log_skip_trailing_zero(u8 *s_ptr, u8 *end_ptr)
{
u8 charac;
while (s_ptr < end_ptr) {
charac = *(s_ptr);
if (charac != 0x00)
break;
s_ptr++;
}
return s_ptr;
}
u32 fw_log_check_integrity(u8 *symbol_tab, u8 *end_ptr)
{
u8 charac, i = 0;
u8 reserved[] = {'R', 'E', 'S', 'E', 'R', 'V', 'E', 'D', '\0'};
charac = *symbol_tab;
while (charac != 0x00) {
if (charac != reserved[i])
return MACFWLOGINTERR;// return fail
i++;
if ((symbol_tab + i) >= end_ptr)
return MACFWLOGINTERR;// return fail
charac = *(symbol_tab + i);
}
return MACSUCCESS;
}
u32 fw_log_create_array(struct mac_ax_adapter *adapter, struct mac_fw_msg *array_ptr,
u8 *symbol_tab, u8 *end_ptr, u32 enum_count, u8 *enum_list)
{
u32 i;
u8 charac;
for (i = 0; i < enum_count; i++) {
array_ptr[i].msgno = le32_to_cpu(*(u32 *)enum_list);
enum_list += 4;
// walk through symbol table
array_ptr[i].msg = (char *)symbol_tab;
//PLTFM_MSG_WARN("[test str] %s\n", (char *)symbol_tab);
//point to next msg
while (symbol_tab < end_ptr) {
charac = *(symbol_tab);
if (charac == 0x00)
break;
symbol_tab++;
}
symbol_tab = fw_log_skip_trailing_zero(symbol_tab, end_ptr);
if (symbol_tab > end_ptr)
return MACFWLOGINTERR;
}
return MACSUCCESS;
}
u32 mac_fw_log_set_array(struct mac_ax_adapter *adapter, void *symbol_ptr, u32 file_size)
{
u8 *sym_hdr, *enum_list, *symbol_tab, *end_ptr;
u32 enum_count, alignment_size, ret;
struct mac_fw_msg *new_fw_log_array = NULL;
sym_hdr = (u8 *)symbol_ptr;
enum_list = (u8 *)(sym_hdr + 8);
alignment_size = le32_to_cpu(*(u32 *)sym_hdr);
enum_count = le32_to_cpu(*(u32 *)(sym_hdr + 4));
symbol_tab = (u8 *)(enum_list + 4 * enum_count);
end_ptr = sym_hdr + file_size;
//PLTFM_MSG_WARN("alignment_size = %d, enum_count = %d\n", alignment_size, enum_count);
// alignment
symbol_tab = fw_log_skip_trailing_zero(symbol_tab, end_ptr);
// check integrity
ret = fw_log_check_integrity(symbol_tab, end_ptr);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]check symbol integrity\n");
return MACFWLOGINTERR;// return fail
}
//create array
new_fw_log_array = (struct mac_fw_msg *)PLTFM_MALLOC(enum_count *
sizeof(struct mac_fw_msg));
if (!new_fw_log_array) {
PLTFM_MSG_ERR("[ERR]malloc new_fw_log_array\n");
return MACBUFALLOC;
}
//PLTFM_MSG_WARN("addr of array = 0x%llx\n", (u64)new_fw_log_array);
ret = fw_log_create_array(adapter, new_fw_log_array, symbol_tab, end_ptr, enum_count,
enum_list);
if (ret != MACSUCCESS) {
PLTFM_MSG_WARN("unexpected symbol\n");
PLTFM_FREE((void *)new_fw_log_array, enum_count * sizeof(struct mac_fw_msg));
return MACFWLOGINTERR;// return fail
}
//PLTFM_FREE((void *)new_fw_log_array, enum_count * sizeof(struct mac_fw_msg));
adapter->fw_log_array = new_fw_log_array;
adapter->fw_log_array_dl = new_fw_log_array;
adapter->fw_log_array_dl_size = enum_count * sizeof(struct mac_fw_msg);
return MACSUCCESS;
}
u32 mac_fw_log_unset_array(struct mac_ax_adapter *adapter)
{
if (adapter->fw_log_array_dl) {
PLTFM_FREE(adapter->fw_log_array_dl, adapter->fw_log_array_dl_size);
adapter->fw_log_array = NULL;
adapter->fw_log_array_dl = NULL;
adapter->fw_log_array_dl_size = 0;
}
fw_log_set_array(adapter);
return MACSUCCESS;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dbg_cmd.c
|
C
|
agpl-3.0
| 51,243
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_DBG_CMD_H_
#define _MAC_AX_DBG_CMD_H_
#include "../type.h"
#include "../mac_def.h"
#include "../mac_ax.h"
#include "tblupd.h"
#if MAC_AX_8852A_SUPPORT
#include "../fw_ax/rtl8852a/hal8852a_fw_log.h"
#endif
#if MAC_AX_8852B_SUPPORT
#include "../fw_ax/rtl8852b/hal8852b_fw_log.h"
#endif
#if MAC_AX_8852C_SUPPORT
#include "../fw_ax/rtl8852c/hal8852c_fw_log.h"
#endif
#define FWDGB_CFG_OP_SET 0
#define FWDGB_CFG_OP_CLR 1
#define FWDGB_CFG_OP_INFO 2
#define FWDGB_CFG_TYPE_LEVEL 0
#define FWDGB_CFG_TYPE_OUTPUT 1
#define FWDGB_CFG_TYPE_COMP 2
#define FWDGB_CFG_TYPE_COMP_EXT 3
#define LEN_PKT_HDR 8
#define LEN_PKTCNT 4
#define LEN_OPCODE 4
#define LEN_LENGTH 4
#define FWSTATUS_OPCODE_MASK 0xFFFF
#define FW_CURTCB_8852A 0x18e0f5fc
#define FW_CURTCB_SP_START_OFFSET 0x30
#define FW_CURTCB_TASK_NAME_OFFSET 0x34
#define FW_MAX_TASK_NAME_LEN 16
#define eMallocMAX 23
#define eMallocTypeMAX 3
//STR_BUF_SIZE , -128 for driver stack size warning
#define STR_BUF_SIZE (1024 - 128)
#define GET_FIELD_OPCODE(opcode) ((opcode) & (FWSTATUS_OPCODE_MASK))
#define MAC_DBG_MSG(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += PLTFM_SNPRINTF(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
/**
* @enum mac_hal_cmd_id
*
* @brief mac_hal_cmd_id
*
* @var mac_hal_cmd_id::MAC_HAL_HELP
* Please Place Description here.
* @var mac_hal_cmd_id::MAC_MAC_DD_DBG
* Please Place Description here.
* @var mac_hal_cmd_id::MAC_MAC_REG_DUMP
* Please Place Description here.
* @var mac_hal_cmd_id::MAC_MAC_FW_DBG
* Please Place Description here.
* @var mac_hal_cmd_id::MAC_MAC_FW_LOG
* Please Place Description here.
* @var mac_hal_cmd_id::MAC_MAC_FW_CURTCB
* Please Place Description here.
* @var mac_hal_cmd_id::MAC_MAC_FW_INFO
* Please Place Description here.
*/
enum mac_hal_cmd_id {
MAC_HAL_HELP = 0,
MAC_MAC_DD_DBG,
MAC_MAC_REG_DUMP,
MAC_MAC_FW_DBG,
MAC_MAC_FW_LOG,
MAC_MAC_FW_CURTCB,
MAC_MAC_FW_INFO,
MAC_MAC_DL_SYM,
};
/**
* @enum mac_ax_fw_status
*
* @brief mac_ax_fw_status
*
* @var mac_ax_fw_status::FW_STATUS_TASKINFO
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_FLASHINFO
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_HEAPINFO
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_MEMINFO_FAST
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_MEMINFO_SLOW
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_PSINFO
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_H2C_C2HINFO
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_ISRINFO
* Please Place Description here.
* @var mac_ax_fw_status::FW_STATUS_MAX
* Please Place Description here.
*/
enum mac_ax_fw_status {
FW_STATUS_TASKINFO,
FW_STATUS_FLASHINFO,
FW_STATUS_HEAPINFO,
FW_STATUS_MEMINFO_FAST,
FW_STATUS_MEMINFO_SLOW,
FW_STATUS_PSINFO,
FW_STATUS_H2C_C2HINFO,
FW_STATUS_ISRINFO,
FW_STATUS_MAX
};
/**
* @enum ISRStatistic
*
* @brief ISRStatistic
*
* @var ISRStatistic::ISRStatistic_WDT
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC0
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC1
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC2
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC3
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC4
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC5
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC6
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC7
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC8
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC9
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_CMAC10
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC0
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC1
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC2
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_SYS0
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_IPSec
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_AXIDMA
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_IDDMA
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_MACErr
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_UART
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_RXI300
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC0_GT0
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC0_GT1
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC0_GT2_3
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_DMAC0_H2C
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_SYS0_HALT_H2C
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_SYS0_GPIO
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_MACErr_DMAC
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_MACErr_CMAC0
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_MACErr_CMAC1
* Please Place Description here.
* @var ISRStatistic::ISRStatistic_MAX
* Please Place Description here.
*/
enum ISRStatistic {
/* Fisrt layer */
// WDTISRROM8852A
ISRStatistic_WDT = 0, // no use currently
// CMACISRROM8852A
ISRStatistic_CMAC0 = 1,
ISRStatistic_CMAC1 = 2,
ISRStatistic_CMAC2 = 3,
ISRStatistic_CMAC3 = 4,
ISRStatistic_CMAC4 = 5,
ISRStatistic_CMAC5 = 6,
ISRStatistic_CMAC6 = 7,
ISRStatistic_CMAC7 = 8,
ISRStatistic_CMAC8 = 9,
ISRStatistic_CMAC9 = 10,
ISRStatistic_CMAC10 = 11,
// DMACISRROM8852A
ISRStatistic_DMAC0 = 12,
ISRStatistic_DMAC1 = 13,
ISRStatistic_DMAC2 = 14,
// SysISRROM8852A
ISRStatistic_SYS0 = 15,
// DataHDLISRROM8852A
ISRStatistic_IPSec = 16,
ISRStatistic_AXIDMA = 17,
ISRStatistic_IDDMA = 18,
// PlatISRROM8852A
ISRStatistic_MACErr = 19,
ISRStatistic_UART = 20,
ISRStatistic_RXI300 = 21,
// Second layer
ISRStatistic_DMAC0_GT0 = 22,
ISRStatistic_DMAC0_GT1 = 23,
ISRStatistic_DMAC0_GT2_3 = 24,
ISRStatistic_DMAC0_H2C = 25,
ISRStatistic_SYS0_HALT_H2C = 26,
ISRStatistic_SYS0_GPIO = 27,
ISRStatistic_MACErr_DMAC = 28,
ISRStatistic_MACErr_CMAC0 = 29,
ISRStatistic_MACErr_CMAC1 = 30,
ISRStatistic_MAX = 31
};
/**
* @struct mac_hal_cmd_info
* @brief mac_hal_cmd_info
*
* @var mac_hal_cmd_info::name
* Please Place Description here.
* @var mac_hal_cmd_info::id
* Please Place Description here.
*/
struct mac_hal_cmd_info {
char name[16];
u16 id;
u32 (*handler)(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV],
u32 input_num, char *output, u32 out_len, u32 *used);
};
/**
* @struct fw_status_pkt
* @brief fw_status_pkt
*
* @var fw_status_pkt::op_code
* Please Place Description here.
* @var fw_status_pkt::length
* Please Place Description here.
* @var fw_status_pkt::data
* Please Place Description here.
*/
struct fw_status_pkt {
u32 op_code;
u32 length;
u8 *data;
};
/**
* @struct flash_info
* @brief flash_info
*
* @var flash_info::b1initdone
* Please Place Description here.
* @var flash_info::b7rsvd
* Please Place Description here.
* @var flash_info::pid
* Please Place Description here.
*/
struct flash_info {
u8 b1initdone: 1;
u8 b7rsvd: 7;
u8 pid[3];
u8 u1flashtype;
u8 u1dienum;
u8 dieindex;
u8 pageindex;
u8 bsupportps; //PS is Page Switch. Page size is 16MB for 3-Bytes address mode.
u8 u1addressmode;
u8 u1dieunitsize; // unit is "Byte"
u8 rsvd1;
u32 u4dieunitnum; // unit number of die
u32 u4flashsize; // flash total size = u4DieUnitNum * DieNum * FlashUnit.
};
/**
* @struct mem_info
* @brief mem_info
*
* @var mem_info::owner_id
* Please Place Description here.
* @var mem_info::owner_type
* Please Place Description here.
* @var mem_info::total_size
* Please Place Description here.
*/
struct mem_info {
u8 owner_id;
u8 owner_type;
u16 total_size;
};
/**
* @struct isr_info
* @brief isr_info
*
* @var isr_info::ISRCnt
* Please Place Description here.
* @var isr_info::ISRExecTimeMax_hi
* Please Place Description here.
* @var isr_info::ISRExecTimeMax_lo
* Please Place Description here.
*/
struct isr_info {
u32 ISRCnt[ISRStatistic_MAX];
u32 ISRExecTimeMax_hi[ISRStatistic_MAX];
u32 ISRExecTimeMax_lo[ISRStatistic_MAX];
};
/**
* @struct fw_status_proc_class
* @brief fw_status_proc_class
*
* @var flash_info::b1initdone
* Please Place Description here.
* @var flash_info::b7rsvd
* Please Place Description here.
* @var flash_info::pid
* Please Place Description here.
*/
struct halcmd_proc_class {
u16 id;
u32 (*handler)(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV]);
};
/**
* @brief mac_fw_status_parser
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
void mac_fw_status_parser(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV],
u32 input_num);
/**
* @brief mac_halmac_cmd
*
* @param *adapter
* @param *input
* @param *output
* @param *out_len
* @return Please Place Description here.
* @retval s32
*/
s32 mac_halmac_cmd(struct mac_ax_adapter *adapter, char *input, char *output, u32 out_len);
/**
* @brief mac_halmac_cmd_parser
*
* @param *adapter
* @param *input
* @param *input_num
* @param *output
* @param *out_len
* @return Please Place Description here.
* @retval void
*/
void mac_halmac_cmd_parser(struct mac_ax_adapter *adapter,
char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len);
/**
* @brief c2h_fw_status
*
* @param *adapter
* @param *buf
* @param *len
* @param *info
* @return Please Place Description here.
* @retval void
*/
u32 c2h_fw_status(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
/**
* @brief fw_status_taskinfo_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_taskinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_flashinfo_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_flashinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_heapinfo_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_heapinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_meminfo_fast_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_meminfo_fast_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_meminfo_slow_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_meminfo_slow_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_psinfo_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_psinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_h2c_c2hinfo_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_h2c_c2hinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief fw_status_isrinfo_handler
*
* @param *adapter
* @param *buf
* @param *len
* @return Please Place Description here.
* @retval void
*/
u32 fw_status_isrinfo_handler(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
/**
* @brief cmd_mac_help
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_help(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used);
/**
* @brief cmd_mac_dbg_dump
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_dbg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used);
/**
* @brief cmd_mac_reg_dump
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_reg_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used);
/**
* @brief cmd_mac_fw_dump
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_fw_dump(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used);
/**
* @brief cmd_mac_fw_log_cfg
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_fw_log_cfg(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV], u32 input_num,
char *output, u32 out_len, u32 *used);
/**
* @brief cmd_mac_fw_curtcb
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_fw_curtcb(struct mac_ax_adapter *adapter,
char input[][MAC_MAX_ARGV],
u32 input_num,
char *output, u32 out_len, u32 *used);
/**
* @brief cmd_mac_fw_status_parser
*
* @param *adapter
* @param *input
* @param *input_num
* @return Please Place Description here.
* @retval void
*/
u32 cmd_mac_fw_status_parser(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV],
u32 input_num, char *output, u32 out_len, u32 *used);
u32 cmd_mac_dl_sym(struct mac_ax_adapter *adapter, char input[][MAC_MAX_ARGV],
u32 input_num, char *output, u32 out_len, u32 *used);
/**
* @brief fw_log_int_dump
*
* @param *adapter
* @param *buf
* @param *msgno
* @param *para_num
* @return Please Place Description here.
* @retval void
*/
static void fw_log_int_dump(struct mac_ax_adapter *adapter, u32 *buf, u32 msgno, u8 para_num,
char *str_buf);
/**
* @brief fw_log_scan_array
*
* @param *adapter
* @param *msgno
* @return Please Place Description here.
* @retval u32
*/
u32 fw_log_scan_array(struct mac_ax_adapter *adapter, u32 msgno);
/**
* @brief fw_log_set_array
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
void fw_log_set_array(struct mac_ax_adapter *adapter);
/**
* @brief fw_log_dump
*
* @param *adapter
* @param *buf
* @param *len
* @param *info
* @return Please Place Description here.
* @retval void
*/
void fw_log_dump(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
/**
* @brief fw_log_skip_trailing_zero
*
* @param *s_ptr
* @param *end_ptr
* @return Please Place Description here.
* @retval u8*
*/
u8 *fw_log_skip_trailing_zero(u8 *s_ptr, u8 *end_ptr);
/**
* @brief fw_log_check_integrity
*
* @param *symbol_tab
* @param *end_ptr
* @return Please Place Description here.
* @retval u32
*/
u32 fw_log_check_integrity(u8 *symbol_tab, u8 *end_ptr);
/**
* @brief fw_log_create_array
*
* @param *array_ptr
* @param *symbol_tab
* @param *end_ptr
* @param *enum_count
* @param *enum_list
* @return Please Place Description here.
* @retval u32
*/
u32 fw_log_create_array(struct mac_ax_adapter *adapter, struct mac_fw_msg *array_ptr,
u8 *symbol_tab, u8 *end_ptr, u32 enum_count, u8 *enum_list);
/**
* @brief mac_fw_log_set_array
*
* @param *adapter
* @param *symbol_ptr
* @param *file_size
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fw_log_set_array(struct mac_ax_adapter *adapter, void *symbol_ptr, u32 file_size);
/**
* @brief mac_fw_log_unset_array
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fw_log_unset_array(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dbg_cmd.h
|
C
|
agpl-3.0
| 17,130
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "dbgpkg.h"
#include "dbgport_hw.h"
#if MAC_AX_FEATURE_HV
#include "../hv_ax/phy_rpt_hv.h"
#endif
static u8 *fwcmd_lb_data;
/* For DLE DFI */
static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_freepg = {
0,
1,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_quota = {
0,
4,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_pagellt = {
0,
0xFFF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_bufmgn_pktinfo = {
0,
0xFFF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_prepkt = {
0,
0xFFF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_nxtpkt = {
0,
0xFFF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_qlnktbl = {
0,
0x453,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_wde_quemgn_qempty = {
0,
0x11,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_freepg = {
0,
1,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_quota = {
0,
0xA,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_pagellt = {
0,
0xDBF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_bufmgn_pktinfo = {
0,
0xDBF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_prepkt = {
0,
0xDBF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_nxtpkt = {
0,
0xDBF,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_qlnktbl = {
0,
0x41,
1
};
static struct mac_ax_dle_dfi_info dle_dfi_ple_quemgn_qempty = {
0,
1,
1
};
/* base address mapping table of enum mac_ax_mem_sel */
static u32 base_addr_map_tbl[MAC_AX_MEM_MAX] = {
CPU_LOCAL_BASE_ADDR,
AXIDMA_BASE_ADDR,
SHARED_BUF_BASE_ADDR,
DMAC_TBL_BASE_ADDR,
SHCUT_MACHDR_BASE_ADDR,
STA_SCHED_BASE_ADDR,
RXPLD_FLTR_CAM_BASE_ADDR,
SEC_CAM_BASE_ADDR,
WOW_CAM_BASE_ADDR,
CMAC_TBL_BASE_ADDR,
ADDR_CAM_BASE_ADDR,
BA_CAM_BASE_ADDR,
BCN_IE_CAM0_BASE_ADDR,
BCN_IE_CAM1_BASE_ADDR,
TXD_FIFO_0_BASE_ADDR,
TXD_FIFO_1_BASE_ADDR,
};
/* For dbg port */
static struct mac_ax_dbg_port_info dbg_port_ptcl_c0 = {
R_AX_PTCL_DBG,
MAC_AX_BYTE_SEL_1,
B_AX_PTCL_DBG_SEL_SH,
B_AX_PTCL_DBG_SEL_MSK,
0x00,
0x3F,
1,
R_AX_PTCL_DBG_INFO,
MAC_AX_BYTE_SEL_4,
B_AX_PTCL_DBG_INFO_SH,
B_AX_PTCL_DBG_INFO_MSK
};
static struct mac_ax_dbg_port_info dbg_port_ptcl_c1 = {
R_AX_PTCL_DBG_C1,
MAC_AX_BYTE_SEL_1,
B_AX_PTCL_DBG_SEL_SH,
B_AX_PTCL_DBG_SEL_MSK,
0x00,
0x3F,
1,
R_AX_PTCL_DBG_INFO_C1,
MAC_AX_BYTE_SEL_4,
B_AX_PTCL_DBG_INFO_SH,
B_AX_PTCL_DBG_INFO_MSK
};
static struct mac_ax_dbg_port_info dbg_port_sch_c0 = {
R_AX_SCH_DBG_SEL,
MAC_AX_BYTE_SEL_1,
B_AX_SCH_DBG_SEL_SH,
B_AX_SCH_DBG_SEL_MSK,
0x00,
0x2F,
1,
R_AX_SCH_DBG,
MAC_AX_BYTE_SEL_4,
B_AX_SCHEDULER_DBG_SH,
B_AX_SCHEDULER_DBG_MSK
};
static struct mac_ax_dbg_port_info dbg_port_sch_c1 = {
R_AX_SCH_DBG_SEL_C1,
MAC_AX_BYTE_SEL_1,
B_AX_SCH_DBG_SEL_SH,
B_AX_SCH_DBG_SEL_MSK,
0x00,
0x2F,
1,
R_AX_SCH_DBG_C1,
MAC_AX_BYTE_SEL_4,
B_AX_SCHEDULER_DBG_SH,
B_AX_SCHEDULER_DBG_MSK
};
static struct mac_ax_dbg_port_info dbg_port_tmac_c0 = {
R_AX_MACTX_DBG_SEL_CNT,
MAC_AX_BYTE_SEL_1,
B_AX_DBGSEL_MACTX_SH,
B_AX_DBGSEL_MACTX_MSK,
0x00,
0x19,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_tmac_c1 = {
R_AX_MACTX_DBG_SEL_CNT_C1,
MAC_AX_BYTE_SEL_1,
B_AX_DBGSEL_MACTX_SH,
B_AX_DBGSEL_MACTX_MSK,
0x00,
0x19,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_rmac_c0 = {
R_AX_RX_DEBUG_SELECT,
MAC_AX_BYTE_SEL_1,
B_AX_DEBUG_SEL_SH,
B_AX_DEBUG_SEL_MSK,
0x00,
0x58,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_rmac_c1 = {
R_AX_RX_DEBUG_SELECT_C1,
MAC_AX_BYTE_SEL_1,
B_AX_DEBUG_SEL_SH,
B_AX_DEBUG_SEL_MSK,
0x00,
0x58,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_rmacst_c0 = {
R_AX_RX_STATE_MONITOR,
MAC_AX_BYTE_SEL_1,
B_AX_STATE_SEL_SH,
B_AX_STATE_SEL_MSK,
0x00,
0x17,
1,
R_AX_RX_STATE_MONITOR,
MAC_AX_BYTE_SEL_4,
0,
0xffffffffL
};
static struct mac_ax_dbg_port_info dbg_port_rmacst_c1 = {
R_AX_RX_STATE_MONITOR_C1,
MAC_AX_BYTE_SEL_1,
B_AX_STATE_SEL_SH,
B_AX_STATE_SEL_MSK,
0x00,
0x17,
1,
R_AX_RX_STATE_MONITOR_C1,
MAC_AX_BYTE_SEL_4,
0,
0xffffffffL
};
static struct mac_ax_dbg_port_info dbg_port_rmac_plcp_c0 = {
R_AX_RMAC_PLCP_MON,
MAC_AX_BYTE_SEL_4,
B_AX_PCLP_MON_SEL_SH,
B_AX_PCLP_MON_SEL_MSK,
0x0,
0xF,
1,
R_AX_RMAC_PLCP_MON,
MAC_AX_BYTE_SEL_4,
0,
0xffffffffL
};
static struct mac_ax_dbg_port_info dbg_port_rmac_plcp_c1 = {
R_AX_RMAC_PLCP_MON_C1,
MAC_AX_BYTE_SEL_4,
B_AX_PCLP_MON_SEL_SH,
B_AX_PCLP_MON_SEL_MSK,
0x0,
0xF,
1,
R_AX_RMAC_PLCP_MON_C1,
MAC_AX_BYTE_SEL_4,
0,
0xffffffffL
};
static struct mac_ax_dbg_port_info dbg_port_trxptcl_c0 = {
R_AX_DBGSEL_TRXPTCL,
MAC_AX_BYTE_SEL_1,
B_AX_DBGSEL_TRXPTCL_SH,
B_AX_DBGSEL_TRXPTCL_MSK,
0x08,
0x10,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_trxptcl_c1 = {
R_AX_DBGSEL_TRXPTCL_C1,
MAC_AX_BYTE_SEL_1,
B_AX_DBGSEL_TRXPTCL_SH,
B_AX_DBGSEL_TRXPTCL_MSK,
0x08,
0x10,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_tx_infol_c0 = {
R_AX_WMAC_TX_CTRL_DEBUG,
MAC_AX_BYTE_SEL_1,
B_AX_TX_CTRL_DEBUG_SEL_SH,
B_AX_TX_CTRL_DEBUG_SEL_MSK,
0x00,
0x07,
1,
R_AX_WMAC_TX_INFO0_DEBUG,
MAC_AX_BYTE_SEL_4,
B_AX_TX_CTRL_INFO_P0_SH,
B_AX_TX_CTRL_INFO_P0_MSK
};
static struct mac_ax_dbg_port_info dbg_port_tx_infoh_c0 = {
R_AX_WMAC_TX_CTRL_DEBUG,
MAC_AX_BYTE_SEL_1,
B_AX_TX_CTRL_DEBUG_SEL_SH,
B_AX_TX_CTRL_DEBUG_SEL_MSK,
0x00,
0x07,
1,
R_AX_WMAC_TX_INFO1_DEBUG,
MAC_AX_BYTE_SEL_4,
B_AX_TX_CTRL_INFO_P1_SH,
B_AX_TX_CTRL_INFO_P1_MSK
};
static struct mac_ax_dbg_port_info dbg_port_tx_infol_c1 = {
R_AX_WMAC_TX_CTRL_DEBUG_C1,
MAC_AX_BYTE_SEL_1,
B_AX_TX_CTRL_DEBUG_SEL_SH,
B_AX_TX_CTRL_DEBUG_SEL_MSK,
0x00,
0x07,
1,
R_AX_WMAC_TX_INFO0_DEBUG_C1,
MAC_AX_BYTE_SEL_4,
B_AX_TX_CTRL_INFO_P0_SH,
B_AX_TX_CTRL_INFO_P0_MSK
};
static struct mac_ax_dbg_port_info dbg_port_tx_infoh_c1 = {
R_AX_WMAC_TX_CTRL_DEBUG_C1,
MAC_AX_BYTE_SEL_1,
B_AX_TX_CTRL_DEBUG_SEL_SH,
B_AX_TX_CTRL_DEBUG_SEL_MSK,
0x00,
0x07,
1,
R_AX_WMAC_TX_INFO1_DEBUG_C1,
MAC_AX_BYTE_SEL_4,
B_AX_TX_CTRL_INFO_P1_SH,
B_AX_TX_CTRL_INFO_P1_MSK
};
static struct mac_ax_dbg_port_info dbg_port_txtf_infol_c0 = {
R_AX_WMAC_TX_TF_INFO_0,
MAC_AX_BYTE_SEL_1,
B_AX_WMAC_TX_TF_INFO_SEL_SH,
B_AX_WMAC_TX_TF_INFO_SEL_MSK,
0x00,
0x04,
1,
R_AX_WMAC_TX_TF_INFO_1,
MAC_AX_BYTE_SEL_4,
B_AX_WMAC_TX_TF_INFO_P0_SH,
B_AX_WMAC_TX_TF_INFO_P0_MSK
};
static struct mac_ax_dbg_port_info dbg_port_txtf_infoh_c0 = {
R_AX_WMAC_TX_TF_INFO_0,
MAC_AX_BYTE_SEL_1,
B_AX_WMAC_TX_TF_INFO_SEL_SH,
B_AX_WMAC_TX_TF_INFO_SEL_MSK,
0x00,
0x04,
1,
R_AX_WMAC_TX_TF_INFO_2,
MAC_AX_BYTE_SEL_4,
B_AX_WMAC_TX_TF_INFO_P1_SH,
B_AX_WMAC_TX_TF_INFO_P1_MSK
};
static struct mac_ax_dbg_port_info dbg_port_txtf_infol_c1 = {
R_AX_WMAC_TX_TF_INFO_0_C1,
MAC_AX_BYTE_SEL_1,
B_AX_WMAC_TX_TF_INFO_SEL_SH,
B_AX_WMAC_TX_TF_INFO_SEL_MSK,
0x00,
0x04,
1,
R_AX_WMAC_TX_TF_INFO_1_C1,
MAC_AX_BYTE_SEL_4,
B_AX_WMAC_TX_TF_INFO_P0_SH,
B_AX_WMAC_TX_TF_INFO_P0_MSK
};
static struct mac_ax_dbg_port_info dbg_port_txtf_infoh_c1 = {
R_AX_WMAC_TX_TF_INFO_0_C1,
MAC_AX_BYTE_SEL_1,
B_AX_WMAC_TX_TF_INFO_SEL_SH,
B_AX_WMAC_TX_TF_INFO_SEL_MSK,
0x00,
0x04,
1,
R_AX_WMAC_TX_TF_INFO_2_C1,
MAC_AX_BYTE_SEL_4,
B_AX_WMAC_TX_TF_INFO_P1_SH,
B_AX_WMAC_TX_TF_INFO_P1_MSK
};
static struct mac_ax_dbg_port_info dbg_port_cmac_dma0_c0 = {
R_AX_RXDMA_CTRL_0,
MAC_AX_BYTE_SEL_4,
B_AX_RXDMA_FIFO_DBG_SEL_SH,
0x3F,
0x00,
0x3F,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_cmac_dma1_c0 = {
R_AX_TXDMA_DBG,
MAC_AX_BYTE_SEL_4,
B_AX_TXDMA_DBG_SEL_SH,
B_AX_TXDMA_DBG_SEL_MSK,
0x00,
0x03,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_cmac_dma0_c1 = {
R_AX_RXDMA_CTRL_0_C1,
MAC_AX_BYTE_SEL_4,
B_AX_RXDMA_FIFO_DBG_SEL_SH,
0x3F,
0x00,
0x3F,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_cmac_dma1_c1 = {
R_AX_TXDMA_DBG_C1,
MAC_AX_BYTE_SEL_4,
B_AX_TXDMA_DBG_SEL_SH,
B_AX_TXDMA_DBG_SEL_MSK,
0x00,
0x03,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pktinfo = {
R_AX_DBG_FUN_INTF_CTL,
MAC_AX_BYTE_SEL_4,
B_AX_DFI_DATA_SH,
B_AX_DFI_DATA_MSK,
0x80000000,
0x8000017f,
1,
R_AX_DBG_FUN_INTF_DATA,
MAC_AX_BYTE_SEL_4,
B_AX_DFI_DATA_SH,
B_AX_DFI_DATA_MSK
};
static struct mac_ax_dbg_port_info dbg_port_wdrls = {
R_AX_DBG_CTL_WDRLS,
MAC_AX_BYTE_SEL_2,
0,
0xffff,
0x0000,
0x0D0D,
0x0101,
R_AX_DBG_OUT_WDRLS,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
};
static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl0 = {
R_AX_DBG_CTL_TXPKT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
0x00000000,
0x00030003,
0x00010001,
R_AX_TPC_DBG_OUT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
};
static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl1 = {
R_AX_DBG_CTL_TXPKT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
0x00800080,
0x008F008F,
0x00010001,
R_AX_TPC_DBG_OUT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
};
static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl2 = {
R_AX_DBG_CTL_TXPKT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
0x01000100,
0x01FF01FF,
0x00010001,
R_AX_TPC_DBG_OUT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
};
static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl3 = {
R_AX_DBG_CTL_TXPKT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
0x02800280,
0x028F028F,
0x00010001,
R_AX_TPC_DBG_OUT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
};
static struct mac_ax_dbg_port_info dbg_port_txpkt_ctrl4 = {
R_AX_DBG_CTL_TXPKT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
0x03000300,
0x030F030F,
0x00010001,
R_AX_TPC_DBG_OUT,
MAC_AX_BYTE_SEL_4,
0,
0xffffffff,
};
static struct mac_ax_dbg_port_info dbg_port_pcie_txdma = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x03,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_rxdma = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x04,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_cvt = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x01,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac04 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x05,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac5 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac6 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac7 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_pnp_io = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x05,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac814 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x06,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac15 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac16 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac17 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_pcie_emac18 = {
R_AX_PCIE_DBG_CTRL,
MAC_AX_BYTE_SEL_2,
B_AX_DBG_SEL_SH,
B_AX_DBG_SEL_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_phy = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_sie = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x04,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_utmi = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x01,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_sie_mmu = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x03,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_sie_pce = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x03,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_utmi_if = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x00,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_wltx = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x04,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_wlrx = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x0D,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb3 = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x0E,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_setup = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x01,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_wltx_dma = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x09,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_wlrx_dma = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x0F,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_ainst = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x02,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_misc = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x01,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb_bttx = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x07,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_usb2_bt = {
R_AX_STC_INT_CS,
MAC_AX_BYTE_SEL_1,
B_AX_STC_INT_REALTIME_CS_SH,
B_AX_STC_INT_REALTIME_CS_MSK,
0x00,
0x01,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx0_5 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0xD,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx6 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x5,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx7 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x9,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx8 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x3,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_tx9_C = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x1,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_txD = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x0,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx0 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0xB,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx1 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x4,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx3 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x8,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx4 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x7,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx5_8 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x1,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_tx9 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x3,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_rx0 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x8,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_rx1_2 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x0,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_hdt_rx3 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_2,
B_AX_DISPATCHER_DBG_SEL_SH,
B_AX_DISPATCHER_DBG_SEL_MSK,
0x0,
0x6,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_rx_p0 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x0,
0x3,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_cdt_rx_p1 = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x8,
0xE,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_stf_ctrl = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x0,
0x5,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_addr_ctrl = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x0,
0x6,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_wde_intf = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x0,
0xF,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_ple_intf = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x0,
0x9,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_dspt_flow_ctrl = {
R_AX_DISPATCHER_DBG_PORT,
MAC_AX_BYTE_SEL_1,
B_AX_DISPATCHER_CH_SEL_SH,
B_AX_DISPATCHER_CH_SEL_MSK,
0x0,
0x3,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_axi_txdma_ctrl = {
R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL,
MAC_AX_BYTE_SEL_4,
B_PL_AXIDMA_DBG_SEL_SH,
0x3F,
0x0,
0x1B,
9,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_axi_rxdma_ctrl = {
R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL,
MAC_AX_BYTE_SEL_4,
B_PL_AXIDMA_DBG_SEL_SH,
0x3F,
0x0,
0x36,
9,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_axi_mst_wlan = {
R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL,
MAC_AX_BYTE_SEL_4,
B_PL_AXIDMA_DBG_SEL_SH,
0x3F,
0x0,
0,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_axi_int_wlan = {
R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL,
MAC_AX_BYTE_SEL_4,
B_PL_AXIDMA_DBG_SEL_SH,
0x3F,
0x0,
0,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
static struct mac_ax_dbg_port_info dbg_port_axi_page_fc = {
R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL,
MAC_AX_BYTE_SEL_4,
B_PL_AXIDMA_DBG_SEL_SH,
0x3F,
0x0,
0,
1,
R_AX_DBG_PORT_SEL,
MAC_AX_BYTE_SEL_4,
B_AX_DEBUG_ST_SH,
B_AX_DEBUG_ST_MSK
};
u32 mac_fwcmd_lb(struct mac_ax_adapter *adapter, u32 len, u8 burst)
{
u32 i;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
enum h2c_buf_class buf_class;
u8 *buf;
if (!burst) {
if (fwcmd_lb_data) {
PLTFM_MSG_ERR("C2H loopbakc is not received\n");
return MACWQBUSY;
}
}
if (len <= H2C_CMD_LEN)
buf_class = H2CB_CLASS_CMD;
else if (len <= H2C_DATA_LEN)
buf_class = H2CB_CLASS_DATA;
else
buf_class = H2CB_CLASS_LONG_DATA;
h2cb = h2cb_alloc(adapter, buf_class);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, len - FWCMD_HDR_LEN);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
for (i = 0; i < len - FWCMD_HDR_LEN; i++)
buf[i] = (u8)(i & 0xFF);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_TEST,
FWCMD_H2C_CL_CMD_PATH,
FWCMD_H2C_FUNC_H2C_LB,
0,
0);
if (ret != MACSUCCESS)
goto fail;
if (!burst) {
fwcmd_lb_data = (u8 *)PLTFM_MALLOC(len);
#if MAC_AX_PHL_H2C
PLTFM_MEMCPY(fwcmd_lb_data, h2cb->vir_data, len);
#else
PLTFM_MEMCPY(fwcmd_lb_data, h2cb->data, len);
#endif
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
goto fail;
}
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
PLTFM_FREE(fwcmd_lb_data, len);
h2cb_free(adapter, h2cb);
return ret;
}
static u32 c2h_sys_cmd_lb(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u32 hdr1;
u32 c2h_len;
u32 h2c_len;
u32 ret = MACSUCCESS;
PLTFM_MSG_TRACE("receive c2h cmd_lb\n");
if (!fwcmd_lb_data)
return MACSUCCESS;
hdr1 = ((struct fwcmd_hdr *)buf)->hdr1;
hdr1 = le32_to_cpu(hdr1);
c2h_len = GET_FIELD(hdr1, C2H_HDR_TOTAL_LEN);
hdr1 = ((struct fwcmd_hdr *)fwcmd_lb_data)->hdr1;
hdr1 = le32_to_cpu(hdr1);
h2c_len = GET_FIELD(hdr1, H2C_HDR_TOTAL_LEN);
if (c2h_len != h2c_len) {
PLTFM_MSG_ERR("[ERR]fwcmd lb wrong len\n");
ret = MACCMP;
goto END;
}
if (PLTFM_MEMCMP(buf + FWCMD_HDR_LEN, fwcmd_lb_data + FWCMD_HDR_LEN,
c2h_len - FWCMD_HDR_LEN)) {
PLTFM_MSG_ERR("[ERR]fwcmd lb contents compare fail\n");
ret = MACCMP;
goto END;
}
END:
PLTFM_FREE(fwcmd_lb_data, len);
fwcmd_lb_data = NULL;
return ret;
}
static struct c2h_proc_func c2h_proc_sys_cmd_path[] = {
{FWCMD_C2H_FUNC_C2H_LB, c2h_sys_cmd_lb},
#if MAC_AX_FEATURE_HV
{FWCMD_C2H_FUNC_TEST_PHY_RPT, c2h_test_phy_rpt},
#endif
{FWCMD_C2H_FUNC_NULL, NULL},
};
u32 c2h_sys_cmd_path(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_sys_cmd_path;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null func handler id: 0x%X\n", proc->id);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_sys_plat_autotest(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
//struct c2h_proc_func *proc = c2h_proc_sys_palt_autotest;
//u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
// struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
//PLTFM_MSG_TRACE("c2h_sys_plat_autotest\n");
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
//set info
info->c2h_cat = GET_FIELD(hdr0, C2H_HDR_CAT);
info->c2h_class = GET_FIELD(hdr0, C2H_HDR_CLASS);
info->c2h_func = GET_FIELD(hdr0, C2H_HDR_FUNC);
//info->done_ack = 0;
//info->rec_ack = 0;
info->content = buf + FWCMD_HDR_LEN;
//info->h2c_return = info->c2h_data[1];
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
return MACSUCCESS;
}
u32 iecam_aces_cfg(struct mac_ax_adapter *adapter, u8 band, u8 en,
struct iecam_cfg_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 camctrl_reg, rbp_reg, ioctrl_reg;
u16 ioctrl_bit;
u32 cnt;
camctrl_reg = band == MAC_AX_BAND_0 ?
R_AX_BCN_IECAM_CTRL : R_AX_BCN_IECAM_CTRL_C1;
rbp_reg = band == MAC_AX_BAND_0 ?
R_AX_BCN_PSR_CTRL : R_AX_BCN_PSR_CTRL_C1;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
ioctrl_reg = band == MAC_AX_BAND_0 ?
R_AX_RXGCK_CTRL : R_AX_RXGCK_CTRL_C1;
ioctrl_bit = B_AX_DISGCLK;
} else {
ioctrl_reg = camctrl_reg;
ioctrl_bit = B_AX_BCN_IECAM_IORST;
}
if (en == MAC_AX_FUNC_DIS) {
/* Restore original setting */
MAC_REG_W16(camctrl_reg, info->camctrl_bkp);
MAC_REG_W32(rbp_reg, info->rbp_bkp);
MAC_REG_W16(ioctrl_reg, info->ioctrl_bkp);
return MACSUCCESS;
}
info->camctrl_bkp = MAC_REG_R16(camctrl_reg);
if (info->camctrl_bkp & B_AX_BCN_IECAM_EN)
MAC_REG_W16(camctrl_reg, info->camctrl_bkp & ~B_AX_BCN_IECAM_EN);
info->rbp_bkp = MAC_REG_R32(rbp_reg);
if (info->rbp_bkp & B_AX_TIM_PARSER_EN)
MAC_REG_W32(rbp_reg, info->rbp_bkp & ~B_AX_TIM_PARSER_EN);
info->ioctrl_bkp = MAC_REG_R16(ioctrl_reg);
if (!(info->ioctrl_bkp & ioctrl_bit))
MAC_REG_W16(ioctrl_reg, info->ioctrl_bkp | ioctrl_bit);
cnt = BCN_PSR_WAIT_CNT;
while (cnt-- && MAC_REG_R16(camctrl_reg) & B_AX_BCN_PSR_BUSY)
PLTFM_DELAY_US(BCN_PSR_WAIT_US);
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]BCN PSR polling timeout\n");
return MACPOLLTO;
}
return MACSUCCESS;
}
static u32 __dump_mac_mem(struct mac_ax_adapter *adapter,
enum mac_ax_mem_sel sel, u32 offset, u8 *buf, u32 len,
u32 dbg_path)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct iecam_cfg_info iec_info;
u32 base_addr, strt_pg, residue, i, cnt, val32;
u32 ret = MACSUCCESS, ret2;
u8 iecam_cfg_flag, band;
if (sel >= MAC_AX_MEM_LAST)
return MACNOITEM;
if (sel == MAC_AX_MEM_BCN_IE_CAM0 || sel == MAC_AX_MEM_BCN_IE_CAM1) {
iecam_cfg_flag = 1;
band = sel == MAC_AX_MEM_BCN_IE_CAM0 ?
MAC_AX_BAND_0 : MAC_AX_BAND_1;
} else {
iecam_cfg_flag = 0;
band = 0;
}
if (iecam_cfg_flag) {
ret = iecam_aces_cfg(adapter, band, MAC_AX_FUNC_EN, &iec_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]iecam access en fail %d\n", ret);
ret2 = iecam_aces_cfg(adapter, band, MAC_AX_FUNC_DIS,
&iec_info);
if (ret2 != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]iecam access dis fail %d\n",
ret2);
return ret;
}
}
strt_pg = offset / MAC_MEM_DUMP_PAGE_SIZE;
residue = offset % MAC_MEM_DUMP_PAGE_SIZE;
base_addr = base_addr_map_tbl[sel] + strt_pg * MAC_MEM_DUMP_PAGE_SIZE;
cnt = 0;
while (cnt < len) {
//PLTFM_MSG_ERR("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, base_addr);
for (i = R_AX_INDIR_ACCESS_ENTRY + residue;
i < R_AX_INDIR_ACCESS_ENTRY + MAC_MEM_DUMP_PAGE_SIZE;
i += 4) {
val32 = le32_to_cpu(MAC_REG_R32(i));
if (dbg_path)
*(u32 *)(buf + cnt) = val32;
else
PLTFM_MSG_ALWAYS("0x%X: 0x%X\n",
(base_addr + i -
R_AX_INDIR_ACCESS_ENTRY),
val32);
cnt += 4;
if (cnt >= len)
break;
}
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
//PLTFM_MSG_ERR("%s ind access sel %d end\n", __func__, sel);
residue = 0;
base_addr += MAC_MEM_DUMP_PAGE_SIZE;
}
if (iecam_cfg_flag) {
ret = iecam_aces_cfg(adapter, band, MAC_AX_FUNC_DIS, &iec_info);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]iecam access dis fail %d\n", ret);
}
return ret;
}
u32 mac_mem_dump(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel,
u32 strt_addr, u8 *buf, u32 len, u32 dbg_path)
{
u32 ret, size;
if (len & (4 - 1)) {
PLTFM_MSG_ERR("[ERR]not 4byte alignment\n");
return MACBUFSZ;
}
size = mac_get_mem_size(adapter, sel);
if (len > size) {
PLTFM_MSG_ERR("[ERR]len %d over max mem size %d\n", len, size);
return MACBUFSZ;
}
/* dbg_path: 1: memory ; 0: console */
if (dbg_path) {
if (!buf) {
PLTFM_MSG_ERR("[ERR]null buf for mem dump\n");
return MACNPTR;
}
}
ret = __dump_mac_mem(adapter, sel, strt_addr, buf, len, dbg_path);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dump mac memory\n");
return ret;
}
return MACSUCCESS;
}
u32 mac_get_mem_size(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel)
{
u32 size;
u16 macid_num = adapter->hw_info->macid_num;
switch (sel) {
case MAC_AX_MEM_AXIDMA:
size = AXIDMA_REG_SIZE;
break;
case MAC_AX_MEM_SHARED_BUF:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
size = SHARE_BUFFER_SIZE_8852A;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
size = SHARE_BUFFER_SIZE_8852B;
else
size = 0;
break;
case MAC_AX_MEM_DMAC_TBL:
size = DCTL_INFO_SIZE * macid_num;
break;
case MAC_AX_MEM_SHCUT_MACHDR:
size = MACHDR_SIZE * macid_num;
break;
case MAC_AX_MEM_STA_SCHED:
size = STA_SCHED_MEM_SIZE;
break;
case MAC_AX_MEM_RXPLD_FLTR_CAM:
size = RXPLD_FLTR_CAM_MEM_SIZE;
break;
case MAC_AX_MEM_SECURITY_CAM:
size = SECURITY_CAM_MEM_SIZE;
break;
case MAC_AX_MEM_WOW_CAM:
size = WOW_CAM_MEM_SIZE;
break;
case MAC_AX_MEM_CMAC_TBL:
size = CCTL_INFO_SIZE * macid_num;
break;
case MAC_AX_MEM_ADDR_CAM:
size = ADDR_CAM_MEM_SIZE;
break;
case MAC_AX_MEM_BA_CAM:
size = BA_CAM_SIZE << BA_CAM_NUM_SH;
break;
case MAC_AX_MEM_BCN_IE_CAM0:
size = BCN_IE_CAM_SIZE * BCN_IE_CAM_NUM;
break;
case MAC_AX_MEM_BCN_IE_CAM1:
size = BCN_IE_CAM_SIZE * BCN_IE_CAM_NUM;
break;
case MAC_AX_MEM_TXD_FIFO_0:
case MAC_AX_MEM_TXD_FIFO_1:
size = TXD_FIFO_SIZE;
break;
default:
size = 0;
break;
}
return size;
}
static u32 __dump_reg_range(struct mac_ax_adapter *adapter,
u32 srt, u32 end)
{
#define REG_PAGE_SIZE 0x100
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 i, j, k, page, val32;
for (i = srt; i <= end; i++) {
page = i << 8;
for (j = page; j < page + REG_PAGE_SIZE; j += 16) {
PLTFM_MSG_ALWAYS("%08xh : ", 0x18600000 + j);
for (k = 0; k < 4; k++) {
val32 = MAC_REG_R32(j + 4 * k);
PLTFM_MSG_ALWAYS("%08x ", val32);
}
PLTFM_MSG_ALWAYS("\n");
}
}
return MACSUCCESS;
#undef REG_PAGE_SIZE
}
static u32 __dump_mac_reg(struct mac_ax_adapter *adapter,
enum mac_ax_reg_sel sel)
{
u32 srt, end;
switch (sel) {
case MAC_AX_REG_MAC:
srt = MAC_PAGE_SRT;
if (adapter->sm.pwr != MAC_AX_PWR_ON) {
PLTFM_MSG_WARN("[WARN]MAC is not power on %d\n",
adapter->sm.pwr);
end = MAC_PAGE_AON_END;
} else {
end = MAC_PAGE_TOP_END;
}
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
srt = MAC_PAGE_HCI_SRT;
end = MAC_PAGE_HCI_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
if (check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_DMAC_SEL)
== MACSUCCESS) {
srt = MAC_PAGE_DMAC_SRT;
end = MAC_PAGE_DMAC_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
}
if (check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL)
== MACSUCCESS) {
srt = MAC_PAGE_CMAC0_SRT;
end = MAC_PAGE_CMAC0_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
}
if (check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL)
== MACSUCCESS) {
srt = MAC_PAGE_CMAC1_SRT;
end = MAC_PAGE_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
}
PLTFM_MSG_ALWAYS("dump MAC REG all\n");
break;
case MAC_AX_REG_BB:
srt = BB_PAGE_SRT;
end = BB_PAGE_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
PLTFM_MSG_ALWAYS("dump BB REG all\n");
break;
case MAC_AX_REG_IQK:
srt = IQK_PAGE_SRT;
end = IQK_PAGE_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
PLTFM_MSG_ALWAYS("dump IQK REG all\n");
break;
case MAC_AX_REG_RFC:
srt = RFC_PAGE_SRT;
end = RFC_PAGE_END;
PLTFM_MSG_ALWAYS("dump MAC REG pg 0x%X-0x%X\n", srt, end);
__dump_reg_range(adapter, srt, end);
PLTFM_MSG_ALWAYS("dump RFC REG all\n");
break;
default:
PLTFM_MSG_ERR("Page sel error (%d)\n", sel);
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_reg_dump(struct mac_ax_adapter *adapter, enum mac_ax_reg_sel sel)
{
u32 ret;
adapter->sm.l2_st = MAC_AX_L2_DIS;
ret = __dump_mac_reg(adapter, sel);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dump mac memory\n");
return ret;
}
adapter->sm.l2_st = MAC_AX_L2_EN;
return MACSUCCESS;
}
u32 dbg_port_sel(struct mac_ax_adapter *adapter,
struct mac_ax_dbg_port_info **info, u32 sel)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u16 val16;
u8 val8, index;
u32 ret = MACSUCCESS;
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock);
adapter->hw_info->dbg_port_cnt++;
if (adapter->hw_info->dbg_port_cnt != 1) {
PLTFM_MSG_ERR("[ERR]dbg port sel %d lock cnt %d\n", sel,
adapter->hw_info->dbg_port_cnt);
ret = MACCMP;
goto err;
}
switch (sel) {
case MAC_AX_DBG_PORT_SEL_PTCL_C0:
*info = &dbg_port_ptcl_c0;
val16 = MAC_REG_R16(R_AX_PTCL_DBG);
val16 |= B_AX_PTCL_DBG_EN;
MAC_REG_W16(R_AX_PTCL_DBG, val16);
PLTFM_MSG_ALWAYS("Enable PTCL C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_PTCL_C1:
*info = &dbg_port_ptcl_c1;
val16 = MAC_REG_R16(R_AX_PTCL_DBG_C1);
val16 |= B_AX_PTCL_DBG_EN;
MAC_REG_W16(R_AX_PTCL_DBG_C1, val16);
PLTFM_MSG_ALWAYS("Enable PTCL C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_SCH_C0:
*info = &dbg_port_sch_c0;
val32 = MAC_REG_R32(R_AX_SCH_DBG_SEL);
val32 |= B_AX_SCH_DBG_EN;
MAC_REG_W32(R_AX_SCH_DBG_SEL, val32);
PLTFM_MSG_ALWAYS("Enable SCH C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_SCH_C1:
*info = &dbg_port_sch_c1;
val32 = MAC_REG_R32(R_AX_SCH_DBG_SEL_C1);
val32 |= B_AX_SCH_DBG_EN;
MAC_REG_W32(R_AX_SCH_DBG_SEL_C1, val32);
PLTFM_MSG_ALWAYS("Enable SCH C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_TMAC_C0:
*info = &dbg_port_tmac_c0;
val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL);
val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC,
B_AX_DBGSEL_TRXPTCL);
MAC_REG_W32(R_AX_DBGSEL_TRXPTCL, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
PLTFM_MSG_ALWAYS("Enable TMAC C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_TMAC_C1:
*info = &dbg_port_tmac_c1;
val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL_C1);
val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC,
B_AX_DBGSEL_TRXPTCL);
MAC_REG_W32(R_AX_DBGSEL_TRXPTCL_C1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
PLTFM_MSG_ALWAYS("Enable TMAC C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_RMAC_C0:
*info = &dbg_port_rmac_c0;
val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL);
val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_RMAC,
B_AX_DBGSEL_TRXPTCL);
MAC_REG_W32(R_AX_DBGSEL_TRXPTCL, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val8 = MAC_REG_R8(R_AX_DBGSEL_TRXPTCL);
val8 = SET_CLR_WORD(val8, RMAC_CMAC_DBG_SEL,
B_AX_DBGSEL_TRXPTCL);
MAC_REG_W8(R_AX_DBGSEL_TRXPTCL, val8);
PLTFM_MSG_ALWAYS("Enable RMAC C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_RMAC_C1:
*info = &dbg_port_rmac_c1;
val32 = MAC_REG_R32(R_AX_DBGSEL_TRXPTCL_C1);
val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_RMAC,
B_AX_DBGSEL_TRXPTCL);
MAC_REG_W32(R_AX_DBGSEL_TRXPTCL_C1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val8 = MAC_REG_R8(R_AX_DBGSEL_TRXPTCL_C1);
val8 = SET_CLR_WORD(val8, RMAC_CMAC_DBG_SEL,
B_AX_DBGSEL_TRXPTCL);
MAC_REG_W8(R_AX_DBGSEL_TRXPTCL_C1, val8);
PLTFM_MSG_ALWAYS("Enable RMAC C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_RMACST_C0:
*info = &dbg_port_rmacst_c0;
PLTFM_MSG_ALWAYS("Enable RMAC state C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_RMACST_C1:
*info = &dbg_port_rmacst_c1;
PLTFM_MSG_ALWAYS("Enable RMAC state C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C0:
*info = &dbg_port_rmac_plcp_c0;
PLTFM_MSG_ALWAYS("Enable RMAC PLCP C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C1:
*info = &dbg_port_rmac_plcp_c1;
PLTFM_MSG_ALWAYS("Enable RMAC PLCP C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_TRXPTCL_C0:
*info = &dbg_port_trxptcl_c0;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
PLTFM_MSG_ALWAYS("Enable TRXPTCL C0 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_TRXPTCL_C1:
*info = &dbg_port_trxptcl_c1;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
PLTFM_MSG_ALWAYS("Enable TRXPTCL C1 dbgport.\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOL_C0:
*info = &dbg_port_tx_infol_c0;
val32 = MAC_REG_R32(R_AX_TCR1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1, val32);
PLTFM_MSG_ALWAYS("Enable tx infol dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOH_C0:
*info = &dbg_port_tx_infoh_c0;
val32 = MAC_REG_R32(R_AX_TCR1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1, val32);
PLTFM_MSG_ALWAYS("Enable tx infoh dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOL_C1:
*info = &dbg_port_tx_infol_c1;
val32 = MAC_REG_R32(R_AX_TCR1_C1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1_C1, val32);
PLTFM_MSG_ALWAYS("Enable tx infol dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOH_C1:
*info = &dbg_port_tx_infoh_c1;
val32 = MAC_REG_R32(R_AX_TCR1_C1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1_C1, val32);
PLTFM_MSG_ALWAYS("Enable tx infoh dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0:
*info = &dbg_port_txtf_infol_c0;
val32 = MAC_REG_R32(R_AX_TCR1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1, val32);
PLTFM_MSG_ALWAYS("Enable tx tf infol dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0:
*info = &dbg_port_txtf_infoh_c0;
val32 = MAC_REG_R32(R_AX_TCR1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1, val32);
PLTFM_MSG_ALWAYS("Enable tx tf infoh dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1:
*info = &dbg_port_txtf_infol_c1;
val32 = MAC_REG_R32(R_AX_TCR1_C1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1_C1, val32);
PLTFM_MSG_ALWAYS("Enable tx tf infol dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1:
*info = &dbg_port_txtf_infoh_c1;
val32 = MAC_REG_R32(R_AX_TCR1_C1);
val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
MAC_REG_W32(R_AX_TCR1_C1, val32);
PLTFM_MSG_ALWAYS("Enable tx tf infoh dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0:
*info = &dbg_port_cmac_dma0_c0;
val32 = MAC_REG_R32(R_AX_TXDMA_DBG) | B_AX_TXDMA_DBG_EN;
MAC_REG_W32(R_AX_TXDMA_DBG, val32);
val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0) | B_AX_RXDMA_DBGOUT_EN;
MAC_REG_W32(R_AX_RXDMA_CTRL_0, val32);
val32 = MAC_REG_R32(R_AX_DLE_CTRL) | B_AX_DMA_DBG_SEL;
MAC_REG_W32(R_AX_DLE_CTRL, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable cmac0 dma0 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0:
*info = &dbg_port_cmac_dma1_c0;
val32 = MAC_REG_R32(R_AX_TXDMA_DBG) | B_AX_TXDMA_DBG_EN;
MAC_REG_W32(R_AX_TXDMA_DBG, val32);
val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0) | B_AX_RXDMA_DBGOUT_EN;
MAC_REG_W32(R_AX_RXDMA_CTRL_0, val32);
val32 = MAC_REG_R32(R_AX_DLE_CTRL) & ~B_AX_DMA_DBG_SEL;
MAC_REG_W32(R_AX_DLE_CTRL, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C0, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable cmac0 dma1 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1:
*info = &dbg_port_cmac_dma0_c1;
val32 = MAC_REG_R32(R_AX_TXDMA_DBG_C1) | B_AX_TXDMA_DBG_EN;
MAC_REG_W32(R_AX_TXDMA_DBG_C1, val32);
val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0_C1) |
B_AX_RXDMA_DBGOUT_EN;
MAC_REG_W32(R_AX_RXDMA_CTRL_0_C1, val32);
val32 = MAC_REG_R32(R_AX_DLE_CTRL_C1) | B_AX_DMA_DBG_SEL;
MAC_REG_W32(R_AX_DLE_CTRL_C1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable cmac1 dma0 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1:
*info = &dbg_port_cmac_dma1_c1;
val32 = MAC_REG_R32(R_AX_TXDMA_DBG_C1) | B_AX_TXDMA_DBG_EN;
MAC_REG_W32(R_AX_TXDMA_DBG_C1, val32);
val32 = MAC_REG_R32(R_AX_RXDMA_CTRL_0_C1) |
B_AX_RXDMA_DBGOUT_EN;
MAC_REG_W32(R_AX_RXDMA_CTRL_0_C1, val32);
val32 = MAC_REG_R32(R_AX_DLE_CTRL_C1) & ~B_AX_DMA_DBG_SEL;
MAC_REG_W32(R_AX_DLE_CTRL_C1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, CMAC_DMA_DBG_SEL_C1, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable cmac1 dma1 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PKTINFO:
*info = &dbg_port_pktinfo;
PLTFM_MSG_ALWAYS("Enable pktinfo dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_WDRLS:
*info = &dbg_port_wdrls;
PLTFM_MSG_ALWAYS("Enable wdrls dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0:
*info = &dbg_port_txpkt_ctrl0;
PLTFM_MSG_ALWAYS("Enable tx pkt control0 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1:
*info = &dbg_port_txpkt_ctrl1;
PLTFM_MSG_ALWAYS("Enable tx pkt control1 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2:
*info = &dbg_port_txpkt_ctrl2;
PLTFM_MSG_ALWAYS("Enable tx pkt control2 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3:
*info = &dbg_port_txpkt_ctrl3;
PLTFM_MSG_ALWAYS("Enable tx pkt control3 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4:
*info = &dbg_port_txpkt_ctrl4;
PLTFM_MSG_ALWAYS("Enable tx pkt control4 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_TXDMA:
*info = &dbg_port_pcie_txdma;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie txdma dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_RXDMA:
*info = &dbg_port_pcie_rxdma;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie rxdma dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_CVT:
*info = &dbg_port_pcie_cvt;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie cvt dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC04:
*info = &dbg_port_pcie_emac04;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC04_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC04_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 0-4 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC5:
*info = &dbg_port_pcie_emac5;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC5_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC5_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 5 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC6:
*info = &dbg_port_pcie_emac6;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC6_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC6_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 6 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC7:
*info = &dbg_port_pcie_emac7;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC7_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC7_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 7 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO:
*info = &dbg_port_pcie_pnp_io;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_PNP_IO_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_PNP_IO_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie p np io dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC814:
*info = &dbg_port_pcie_emac814;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC814_DBG_SEL,
B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC814_DBG_SEL,
B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 8-14 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC15:
*info = &dbg_port_pcie_emac15;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC15_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC15_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 15 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC16:
*info = &dbg_port_pcie_emac16;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC16_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC16_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 16 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC17:
*info = &dbg_port_pcie_emac17;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC17_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC17_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 17 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC18:
*info = &dbg_port_pcie_emac18;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, PCIE_EMAC18_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, PCIE_EMAC18_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable pcie emac 18 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_PHY:
*info = &dbg_port_usb2_phy;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_PHY_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_PHY_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_PHY dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_SIE:
*info = &dbg_port_usb2_sie;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_SIE_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_SIE_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_SIE dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_UTMI:
*info = &dbg_port_usb2_utmi;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_UTMI_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_UTMI_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_UTMI dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU:
*info = &dbg_port_usb2_sie_mmu;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_SIE_MMU_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_SIE_MMU_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_SIE_MMU dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE:
*info = &dbg_port_usb2_sie_pce;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_SIE_PCE_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_SIE_PCE_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_SIE_PCE dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF:
*info = &dbg_port_usb2_utmi_if;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_UTMI_IF_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_UTMI_IF_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_UTMI_IF dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLTX:
*info = &dbg_port_usb_wltx;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_WLTX_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_WLTX_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_WLTX dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLRX:
*info = &dbg_port_usb_wlrx;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_WLRX_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_WLRX_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_WLRX dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB3:
*info = &dbg_port_usb3;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB3_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB3_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB3 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_SETUP:
*info = &dbg_port_usb_setup;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_SETUP_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_SETUP_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_SETUP dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA:
*info = &dbg_port_usb_wltx_dma;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_WLTXDMA_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_WLTXDMA_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_WLTX_DMA dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA:
*info = &dbg_port_usb_wlrx_dma;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_WLRXDMA_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_WLRXDMA_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_WLRX_DMA dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_AINST:
*info = &dbg_port_usb_ainst;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_AINST_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_AINST_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_AINST_DMA dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_MISC:
*info = &dbg_port_usb_misc;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_MISC_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_MISC_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_MISC dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_BTTX:
*info = &dbg_port_usb_bttx;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB_BTTX_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB_BTTX_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB_BTTX dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_BT:
*info = &dbg_port_usb2_bt;
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, USB2_BT_DBG_SEL, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, USB2_BT_DBG_SEL, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_ALWAYS("Enable USB2_BT dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5:
if (sel == MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0) {
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, DISPATCHER_DBG_SEL,
B_AX_DBG_SEL0);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
}
*info = &dbg_port_dspt_hdt_tx0_5;
index = sel - MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx%x dump.\n", index);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6:
*info = &dbg_port_dspt_hdt_tx6;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 6, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx6 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7:
*info = &dbg_port_dspt_hdt_tx7;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 7, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx7 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8:
*info = &dbg_port_dspt_hdt_tx8;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 8, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx8 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC:
*info = &dbg_port_dspt_hdt_tx9_C;
index = sel + 9 - MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt tx%x dump.\n", index);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD:
*info = &dbg_port_dspt_hdt_txD;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 0xD, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt txD dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0:
*info = &dbg_port_dspt_cdt_tx0;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx0 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX1:
*info = &dbg_port_dspt_cdt_tx1;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx1 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3:
*info = &dbg_port_dspt_cdt_tx3;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 3, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx3 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4:
*info = &dbg_port_dspt_cdt_tx4;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 4, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx4 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8:
*info = &dbg_port_dspt_cdt_tx5_8;
index = sel + 5 - MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx%x dump.\n", index);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9:
*info = &dbg_port_dspt_cdt_tx9;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 1, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 9, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt tx9 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0:
*info = &dbg_port_dspt_hdt_rx0;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 2, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 0, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt rx0 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2:
*info = &dbg_port_dspt_hdt_rx1_2;
index = sel + 1 - MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 2, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, index, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt rx%x dump.\n", index);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3:
*info = &dbg_port_dspt_hdt_rx3;
val16 = MAC_REG_R16((*info)->sel_addr);
val16 = SET_CLR_WORD(val16, 2, B_AX_DISPATCHER_INTN_SEL);
val16 = SET_CLR_WORD(val16, 3, B_AX_DISPATCHER_CH_SEL);
MAC_REG_W16((*info)->sel_addr, val16);
PLTFM_MSG_ALWAYS("Enable Dispatcher hdt rx3 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0:
*info = &dbg_port_dspt_cdt_rx_p0;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 3, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt rx part0 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1:
*info = &dbg_port_dspt_cdt_rx_p1;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 3, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher cdt rx part1 dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL:
*info = &dbg_port_dspt_stf_ctrl;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 4, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher stf control dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL:
*info = &dbg_port_dspt_addr_ctrl;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 5, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher addr control dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF:
*info = &dbg_port_dspt_wde_intf;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 6, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher wde interface dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF:
*info = &dbg_port_dspt_ple_intf;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 7, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher ple interface dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL:
*info = &dbg_port_dspt_flow_ctrl;
val8 = MAC_REG_R8((*info)->sel_addr);
val8 = SET_CLR_WORD(val8, 8, B_AX_DISPATCHER_INTN_SEL);
MAC_REG_W8((*info)->sel_addr, val8);
PLTFM_MSG_ALWAYS("Enable Dispatcher flow control dump.\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL:
*info = &dbg_port_axi_txdma_ctrl;
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR);
val32 = MAC_REG_R32((*info)->sel_addr);
val32 = SET_CLR_WORD(val32, 0, B_AX_AXIDMA_INT_SEL);
MAC_REG_W32((*info)->sel_addr, val32);
PLTFM_MSG_ALWAYS("Enable AXIDMA TXDMA CTRL dump\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL:
*info = &dbg_port_axi_rxdma_ctrl;
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR);
val32 = MAC_REG_R32((*info)->sel_addr);
val32 = SET_CLR_WORD(val32, 1, B_AX_AXIDMA_INT_SEL);
MAC_REG_W32((*info)->sel_addr, val32);
PLTFM_MSG_ALWAYS("Enable AXIDMA RXDMA CTRL dump\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN:
*info = &dbg_port_axi_mst_wlan;
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR);
val32 = MAC_REG_R32((*info)->sel_addr);
val32 = SET_CLR_WORD(val32, 2, B_AX_AXIDMA_INT_SEL);
MAC_REG_W32((*info)->sel_addr, val32);
PLTFM_MSG_ALWAYS("Enable AXIDMA MST WLAN dump\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN:
*info = &dbg_port_axi_int_wlan;
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR);
val32 = MAC_REG_R32((*info)->sel_addr);
val32 = SET_CLR_WORD(val32, 3, B_AX_AXIDMA_INT_SEL);
MAC_REG_W32((*info)->sel_addr, val32);
PLTFM_MSG_ALWAYS("Enable AXIDMA INT WLAN dump\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL:
*info = &dbg_port_axi_page_fc;
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL0);
val32 = SET_CLR_WORD(val32, 0x71, B_AX_DBG_SEL1);
MAC_REG_W32(R_AX_DBG_CTRL, val32);
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR);
val32 = MAC_REG_R32((*info)->sel_addr);
val32 = SET_CLR_WORD(val32, 4, B_AX_AXIDMA_INT_SEL);
MAC_REG_W32((*info)->sel_addr, val32);
PLTFM_MSG_ALWAYS("Enable AXIDMA PAGE FLOW CTRL dump\n");
break;
default:
PLTFM_MSG_ALWAYS("Dbg port select err\n");
*info = NULL;
ret = MACDBGPORTSEL;
goto err;
}
return MACSUCCESS;
err:
if (ret == MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dbg port sel has no err code\n");
ret = MACPROCERR;
}
adapter->hw_info->dbg_port_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock);
return ret;
}
static void print_dbg_port_sel(struct mac_ax_adapter *adapter, u32 sel)
{
u32 i;
switch (sel) {
case MAC_AX_DBG_PORT_SEL_PTCL_C0:
PLTFM_MSG_ALWAYS("Dump debug port PTCL C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_PTCL_C1:
PLTFM_MSG_ALWAYS("Dump debug port PTCL C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_SCH_C0:
PLTFM_MSG_ALWAYS("Dump debug port SCH C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_SCH_C1:
PLTFM_MSG_ALWAYS("Dump debug port SCH C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TMAC_C0:
PLTFM_MSG_ALWAYS("Dump debug port TMAC C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TMAC_C1:
PLTFM_MSG_ALWAYS("Dump debug port TMAC C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_RMAC_C0:
PLTFM_MSG_ALWAYS("Dump debug port RMAC C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_RMAC_C1:
PLTFM_MSG_ALWAYS("Dump debug port RMAC C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_RMACST_C0:
PLTFM_MSG_ALWAYS("Dump debug port RMACST C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_RMACST_C1:
PLTFM_MSG_ALWAYS("Dump debug port RMACST C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TRXPTCL_C0:
PLTFM_MSG_ALWAYS("Dump debug port TRXPTCL C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TRXPTCL_C1:
PLTFM_MSG_ALWAYS("Dump debug port TRXPTCL C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOL_C0:
PLTFM_MSG_ALWAYS("Dump debug port TXINFOL C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOH_C0:
PLTFM_MSG_ALWAYS("Dump debug port TXINFOH C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOL_C1:
PLTFM_MSG_ALWAYS("Dump debug port TXINFOL C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TX_INFOH_C1:
PLTFM_MSG_ALWAYS("Dump debug port TXINFOH C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0:
PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOL C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0:
PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOH C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1:
PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOL C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1:
PLTFM_MSG_ALWAYS("Dump debug port TXTFINFOH C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0:
PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA0 C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0:
PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA1 C0:\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1:
PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA0 C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1:
PLTFM_MSG_ALWAYS("Dump debug port CMAC DMA1 C1:\n");
break;
case MAC_AX_DBG_PORT_SEL_PKTINFO:
PLTFM_MSG_ALWAYS("Dump debug port PKTINFO:\n");
break;
case MAC_AX_DBG_PORT_SEL_WDRLS:
PLTFM_MSG_ALWAYS("Dump debug port WDRLS:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0:
PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL0:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1:
PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL1:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2:
PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL2:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3:
PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL3:\n");
break;
case MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4:
PLTFM_MSG_ALWAYS("Dump debug port TXPKT_CTRL4:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_TXDMA:
PLTFM_MSG_ALWAYS("Dump debug port PCIE TXDMA:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_RXDMA:
PLTFM_MSG_ALWAYS("Dump debug port PCIE RXDMA:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_CVT:
PLTFM_MSG_ALWAYS("Dump debug port PCIE CVT:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC04:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 0-4:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC5:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 5:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC6:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 6:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC7:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 7:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC P-NP-IO:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC814:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 8-14:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC15:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 15:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC16:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 16:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC17:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 17:\n");
break;
case MAC_AX_DBG_PORT_SEL_PCIE_EMAC18:
PLTFM_MSG_ALWAYS("Dump debug port PCIE EMAC 18:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_PHY:
PLTFM_MSG_ALWAYS("Dump debug port USB2 PHY:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_SIE:
PLTFM_MSG_ALWAYS("Dump debug port USB2 SIE:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_UTMI:
PLTFM_MSG_ALWAYS("Dump debug port USB2 UTMI:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU:
PLTFM_MSG_ALWAYS("Dump debug port USB2 SIE MMU:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE:
PLTFM_MSG_ALWAYS("Dump debug port USB2 SIE PCE:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF:
PLTFM_MSG_ALWAYS("Dump debug port USB2 UTMI IF:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLTX:
PLTFM_MSG_ALWAYS("Dump debug port USB WLTX:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLRX:
PLTFM_MSG_ALWAYS("Dump debug port USB WLRX:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB3:
PLTFM_MSG_ALWAYS("Dump debug port USB3:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_SETUP:
PLTFM_MSG_ALWAYS("Dump debug port USB SETUP:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA:
PLTFM_MSG_ALWAYS("Dump debug port USB WLTXDMA:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA:
PLTFM_MSG_ALWAYS("Dump debug port USB WLRXDMA:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_AINST:
PLTFM_MSG_ALWAYS("Dump debug port USB AINST:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_MISC:
PLTFM_MSG_ALWAYS("Dump debug port USB2 MISC:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB_BTTX:
PLTFM_MSG_ALWAYS("Dump debug port USB2 BTTX:\n");
break;
case MAC_AX_DBG_PORT_SEL_USB2_BT:
PLTFM_MSG_ALWAYS("Dump debug port USB2 BT:\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD:
i = sel - MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0;
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER HDT TX%x:\n", i);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9:
if (sel == MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0)
i = 0;
else
i = sel + 3 - MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3;
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER CDT TX%x:\n", i);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2:
case MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3:
i = sel - MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0;
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER HDT RX%x:\n", i);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0:
case MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1:
i = sel - MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0;
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER CDT RX part%x:\n",
i);
break;
case MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL:
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER STF Control:\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL:
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER ADDR Control:\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF:
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER WDE Interface:\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF:
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER PLE Interface:\n");
break;
case MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL:
PLTFM_MSG_ALWAYS("Dump debug port DISPATCHER FLOW Control:\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL:
PLTFM_MSG_ALWAYS("Dump debug port AXI_TXDMA_CTRL:\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL:
PLTFM_MSG_ALWAYS("Dump debug port AXI_RXDMA_CTRL:\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN:
PLTFM_MSG_ALWAYS("Dump debug port AXI_MST_WLAN:\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN:
PLTFM_MSG_ALWAYS("Dump debug port AXI_INT_WLAN::\n");
break;
case MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL:
PLTFM_MSG_ALWAYS("Dump debug port AXI_PAGE_FLOW_CTRL:\n");
break;
default:
PLTFM_MSG_WARN("Dump unknown debug port sel %d:\n", sel);
break;
}
}
static void print_dbg_port(struct mac_ax_adapter *adapter, struct mac_ax_dbg_port_info *info)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 i;
u8 val8;
u16 val16;
u32 val32;
for (i = info->srt; i <= info->end; i += info->inc_num) {
switch (info->sel_byte) {
case MAC_AX_BYTE_SEL_1:
default:
val8 = SET_CLR_WOR2(MAC_REG_R8(info->sel_addr), i,
info->sel_sh,
info->sel_msk);
MAC_REG_W8(info->sel_addr, val8);
PLTFM_MSG_ALWAYS("0x%02X: ", val8);
break;
case MAC_AX_BYTE_SEL_2:
val16 = SET_CLR_WOR2(MAC_REG_R16(info->sel_addr), i,
info->sel_sh,
info->sel_msk);
MAC_REG_W16(info->sel_addr, val16);
PLTFM_MSG_ALWAYS("0x%04X: ", val16);
break;
case MAC_AX_BYTE_SEL_4:
val32 = SET_CLR_WOR2(MAC_REG_R32(info->sel_addr), i,
info->sel_sh,
info->sel_msk);
MAC_REG_W32(info->sel_addr, val32);
PLTFM_MSG_ALWAYS("0x%08X: ", val32);
break;
}
PLTFM_DELAY_US(DBG_PORT_DUMP_DLY_US);
switch (info->rd_byte) {
case MAC_AX_BYTE_SEL_1:
default:
val8 = GET_FIEL2(MAC_REG_R8(info->rd_addr),
info->rd_sh, info->rd_msk);
PLTFM_MSG_ALWAYS("0x%02X\n", val8);
break;
case MAC_AX_BYTE_SEL_2:
val16 = GET_FIEL2(MAC_REG_R16(info->rd_addr),
info->rd_sh, info->rd_msk);
PLTFM_MSG_ALWAYS("0x%04X\n", val16);
break;
case MAC_AX_BYTE_SEL_4:
val32 = GET_FIEL2(MAC_REG_R32(info->rd_addr),
info->rd_sh, info->rd_msk);
PLTFM_MSG_ALWAYS("0x%08X\n", val32);
break;
}
}
}
static u32 dbg_port_dump(struct mac_ax_adapter *adapter, u32 sel)
{
struct mac_ax_dbg_port_info *info;
u32 ret;
ret = dbg_port_sel(adapter, &info, sel);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] dbg port sel %d %d\n", sel, ret);
return ret;
}
print_dbg_port_sel(adapter, sel);
PLTFM_MSG_ALWAYS("Sel addr = 0x%X\n", info->sel_addr);
PLTFM_MSG_ALWAYS("Read addr = 0x%X\n", info->rd_addr);
print_dbg_port(adapter, info);
if (sel >= MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL &&
sel <= MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL) {
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access sel %d end\n", __func__, sel);
}
adapter->hw_info->dbg_port_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock);
return MACSUCCESS;
}
static u32 ss_poll_own(struct mac_ax_adapter *adapter, u32 addr)
{
u32 cnt = 100;
u32 val32 = SS_POLL_UNEXPECTED;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
while (--cnt) {
val32 = MAC_REG_R32(addr);
if ((val32 & B_AX_SS_OWN) == 0)
break;
PLTFM_DELAY_US(1);
}
return val32;
}
static u32 ss_tx_len_chk(struct mac_ax_adapter *adapter, u16 macid)
{
u32 sel;
u32 val32 = 0;
u32 dw[4];
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
for (sel = 0; sel < 4; sel++) {
MAC_REG_W32(R_AX_SS_SRAM_CTRL_1,
B_AX_SS_OWN |
SET_WORD(SS_CTRL1_R_TX_LEN, B_AX_SS_CMD_SEL) |
SET_WORD(sel, B_AX_SS_AC) | macid);
dw[sel] = ss_poll_own(adapter, R_AX_SS_SRAM_CTRL_1);
if (dw[sel] & (BIT(29) | BIT(30))) {
val32 |= SS_POLL_STAT_TX_LEN;
PLTFM_MSG_ERR("[ERR]SS_POLL_STAT_TX_LEN, macid %d, ",
macid);
PLTFM_MSG_ERR("ac %d\n", sel);
}
if (dw[sel] & B_AX_SS_OWN) {
val32 |= SS_POLL_OWN_TX_LEN;
PLTFM_MSG_ERR("[ERR]SS_POLL_OWN_TX_LEN, macid %d, ",
macid);
PLTFM_MSG_ERR("ac %d\n", sel);
}
}
if (((dw[0] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) {
val32 |= SS_TX_LEN_BE;
PLTFM_MSG_ERR("[ERR]SS_TX_LEN_BE, macid %d, ",
macid);
PLTFM_MSG_ERR("len 0x%X\n",
(dw[0] >> SS_MACID_SH) & SS_TX_LEN_MSK);
}
if (((dw[1] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) {
val32 |= SS_TX_LEN_BK;
PLTFM_MSG_ERR("[ERR]SS_TX_LEN_BK, macid %d, ",
macid);
PLTFM_MSG_ERR("len 0x%X\n",
(dw[1] >> SS_MACID_SH) & SS_TX_LEN_MSK);
}
if (((dw[2] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) {
val32 |= SS_TX_LEN_VI;
PLTFM_MSG_ERR("[ERR]SS_TX_LEN_VI, macid %d, ",
macid);
PLTFM_MSG_ERR("len 0x%X\n",
(dw[2] >> SS_MACID_SH) & SS_TX_LEN_MSK);
}
if (((dw[3] >> SS_MACID_SH) & SS_TX_LEN_MSK) != 0) {
val32 |= SS_TX_LEN_VO;
PLTFM_MSG_ERR("[ERR]SS_TX_LEN_VO, macid %d, ",
macid);
PLTFM_MSG_ERR("len 0x%X\n",
(dw[3] >> SS_MACID_SH) & SS_TX_LEN_MSK);
}
return val32;
}
static u32 ss_link_chk(struct mac_ax_adapter *adapter,
struct ss_link_info *link)
{
u32 val32 = 0;
u32 poll;
u8 wmm, ac;
u8 link_head;
u8 link_tail;
u8 link_len;
u32 i;
u32 cmd;
u8 macid;
u16 macid_num = adapter->hw_info->macid_num;
u16 id_empty = (macid_num << 1) - 1;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (link->ul) {
wmm = 0;
ac = 0;
} else {
wmm = link->wmm;
ac = link->ac;
}
MAC_REG_W32(R_AX_SS_LINK_INFO, B_AX_SS_OWN |
(link->ul ? B_AX_SS_UL : 0) |
SET_WORD(wmm, B_AX_SS_WMM) |
SET_WORD(ac, B_AX_SS_AC));
poll = ss_poll_own(adapter, R_AX_SS_LINK_INFO);
link_head = GET_FIELD(poll, B_AX_SS_LINK_HEAD);
link_tail = GET_FIELD(poll, B_AX_SS_LINK_TAIL);
link_len = GET_FIELD(poll, B_AX_SS_LINK_LEN);
if (poll & (BIT(29) | BIT(30))) {
val32 |= SS_POLL_STAT_LINK;
PLTFM_MSG_ERR("[ERR]SS_POLL_STAT_LINK, ul/wmm/ac %d/%d/%d\n",
link->ul, wmm, ac);
}
if (poll & B_AX_SS_OWN) {
val32 |= SS_POLL_OWN_LINK;
PLTFM_MSG_ERR("[ERR]SS_POLL_OWN_LINK, ul/wmm/ac %d/%d/%d\n",
link->ul, wmm, ac);
}
if (link_head != id_empty || link_tail != id_empty || link_len != 0) {
if (link->ul)
val32 |= SS_LINK_UL << ((wmm << 2) + ac);
else
val32 |= SS_LINK_WMM0_BE << ((wmm << 2) + ac);
PLTFM_MSG_ERR("[ERR]SS_LINK_DUMP, ul/wmm/ac %d/%d/%d, ",
link->ul, wmm, ac);
PLTFM_MSG_ERR("head/tail/len 0x%X/0x%X/%d\n",
link_head, link_tail, link_len);
macid = link_head;
i = 0;
do {
PLTFM_MSG_ERR("0x%X, ", macid);
cmd = B_AX_SS_OWN |
SET_WORD(SS_CTRL1_R_NEXT_LINK, B_AX_SS_CMD_SEL) |
SET_WORD(ac, B_AX_SS_AC) |
(link->ul ? BIT(23) : 0) | macid;
MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, cmd);
poll = ss_poll_own(adapter, R_AX_SS_SRAM_CTRL_1);
if (poll & (BIT(29) | BIT(30))) {
PLTFM_MSG_ERR("[ERR]SS_LINK_DUMP_POLL_STAT\n");
break;
}
if (poll & B_AX_SS_OWN) {
PLTFM_MSG_ERR("[ERR]SS_LINK_DUMP_POLL_OWN\n");
break;
}
if (GET_FIELD(poll, B_AX_SS_VALUE) == id_empty) {
if (macid != link_tail) {
PLTFM_MSG_ERR("[ERR]tail error!!\n");
break;
}
if (i >= link_len) {
PLTFM_MSG_ERR("[ERR]len error!!\n");
break;
}
break;
}
macid = GET_FIELD(poll, B_AX_SS_VALUE);
i++;
} while (i < SS_LINK_SIZE);
PLTFM_MSG_ERR("\n[ERR]SS_LINK_DUMP, end");
}
return val32;
}
static u32 ss_stat_chk(struct mac_ax_adapter *adapter)
{
u32 val32 = 0;
u32 r_val32;
u8 fw_vld;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (adapter->hw_info->chip_id) {
case MAC_AX_CHIP_ID_8852A:
fw_vld = SS_FW_SUPPORT_8852A;
break;
case MAC_AX_CHIP_ID_8852B:
fw_vld = SS_FW_SUPPORT_8852B;
break;
default:
fw_vld = 0;
break;
}
r_val32 = MAC_REG_R32(R_AX_SS_DBG_3);
if (r_val32 & B_AX_SS_HW_DECR_LEN_UDN)
val32 |= SS_TX_HW_LEN_UDN;
if (r_val32 & B_AX_SS_SW_DECR_LEN_UDN)
val32 |= SS_TX_SW_LEN_UDN;
if (r_val32 & B_AX_SS_HW_ADD_LEN_OVF)
val32 |= SS_TX_HW_LEN_OVF;
r_val32 = MAC_REG_R32(R_AX_SS_DBG_2);
if (fw_vld) {
if (GET_FIELD(r_val32, B_AX_SS_FWTX_STAT) != 1)
val32 |= SS_STAT_FWTX;
}
if (GET_FIELD(r_val32, B_AX_SS_RPTA_STAT) != 1)
val32 |= SS_STAT_RPTA;
if (GET_FIELD(r_val32, B_AX_SS_WDEA_STAT) != 1)
val32 |= SS_STAT_WDEA;
if (GET_FIELD(r_val32, B_AX_SS_PLEA_STAT) != 1)
val32 |= SS_STAT_PLEA;
r_val32 = MAC_REG_R32(R_AX_SS_DBG_1);
if (GET_FIELD(r_val32, B_AX_SS_ULRU_STAT) > 1)
val32 |= SS_STAT_ULRU;
if (GET_FIELD(r_val32, B_AX_SS_DLTX_STAT) > 1)
val32 |= SS_STAT_DLTX;
return val32;
}
static void ss_dbgpkg_val_parser(struct mac_ax_adapter *adapter,
struct mac_ax_dbgpkg *val)
{
/* STA Scheduler 0, indirect */
PLTFM_MSG_ALWAYS("[ERR][STA_SCH] ss_dbg_0 = 0x%X\n", val->ss_dbg_0);
if (val->ss_dbg_0 & SS_TX_LEN_BE)
PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's BE length != 0\n");
if (val->ss_dbg_0 & SS_TX_LEN_BK)
PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's BK length != 0\n");
if (val->ss_dbg_0 & SS_TX_LEN_VI)
PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's VI length != 0\n");
if (val->ss_dbg_0 & SS_TX_LEN_VO)
PLTFM_MSG_ERR("[ERR][STA_SCH] some MACID's VO length != 0\n");
if (val->ss_dbg_0 & SS_LINK_WMM0_BE)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 BE not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM0_BK)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 BK not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM0_VI)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 VI not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM0_VO)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_0 VO not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM1_BE)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 BE not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM1_BK)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 BK not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM1_VI)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 VI not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM1_VO)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_1 VO not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM2_BE)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 BE not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM2_BK)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 BK not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM2_VI)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 VI not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM2_VO)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_2 VO not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM3_BE)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 BE not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM3_BK)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 BK not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM3_VI)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 VI not empty\n");
if (val->ss_dbg_0 & SS_LINK_WMM3_VO)
PLTFM_MSG_ERR("[ERR][STA_SCH] WMM_3 VO not empty\n");
if (val->ss_dbg_0 & SS_LINK_UL)
PLTFM_MSG_ERR("[ERR][STA_SCH] UL not empty\n");
if (val->ss_dbg_0 & SS_POLL_OWN_TX_LEN)
PLTFM_MSG_ERR("[ERR][STA_SCH] (length) own bit polling fail\n");
if (val->ss_dbg_0 & SS_POLL_OWN_LINK)
PLTFM_MSG_ERR("[ERR][STA_SCH] (link) own bit polling fail\n");
if (val->ss_dbg_0 & SS_POLL_STAT_TX_LEN)
PLTFM_MSG_ERR("[ERR][STA_SCH] (length) state machine fail\n");
if (val->ss_dbg_0 & SS_POLL_STAT_LINK)
PLTFM_MSG_ERR("[ERR][STA_SCH] (link) state machine fail\n");
/* STA Scheduler 1, direct */
PLTFM_MSG_ALWAYS("[ERR][STA_SCH] ss_dbg_1 = 0x%X\n", val->ss_dbg_1);
if (val->ss_dbg_1 & SS_TX_HW_LEN_UDN)
PLTFM_MSG_ERR("[ERR][STA_SCH] HW cause length underflow\n");
if (val->ss_dbg_1 & SS_TX_SW_LEN_UDN)
PLTFM_MSG_ERR("[ERR][STA_SCH] SW cause length underflow\n");
if (val->ss_dbg_1 & SS_TX_HW_LEN_OVF)
PLTFM_MSG_ERR("[ERR][STA_SCH] HW cause length overflow\n");
if (val->ss_dbg_1 & SS_STAT_FWTX)
PLTFM_MSG_ERR("[ERR][STA_SCH] SW Tx state machine not idle\n");
if (val->ss_dbg_1 & SS_STAT_RPTA)
PLTFM_MSG_ERR("[ERR][STA_SCH] Report state machine not idle\n");
if (val->ss_dbg_1 & SS_STAT_WDEA)
PLTFM_MSG_ERR("[ERR][STA_SCH] WDE state machine not idle\n");
if (val->ss_dbg_1 & SS_STAT_PLEA)
PLTFM_MSG_ERR("[ERR][STA_SCH] PLE state machine not idle\n");
if (val->ss_dbg_1 & SS_STAT_ULRU)
PLTFM_MSG_ERR("[ERR][STA_SCH] UL RU state machine not idle\n");
if (val->ss_dbg_1 & SS_STAT_DLTX)
PLTFM_MSG_ERR("[ERR][STA_SCH] HW Tx state machine not idle\n");
}
static void ps_dbg_dump(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
enum mac_ax_intf intf = adapter->hw_info->intf;
PLTFM_MSG_ALWAYS("R_AX_PLATFORM_ENABLE=0x%x\n",
MAC_REG_R32(R_AX_PLATFORM_ENABLE));
PLTFM_MSG_ALWAYS("R_AX_WLLPS_CTRL=0x%x\n",
MAC_REG_R32(R_AX_WLLPS_CTRL));
PLTFM_MSG_ALWAYS("R_AX_WLRESUME_CTRL=0x%x\n",
MAC_REG_R32(R_AX_WLRESUME_CTRL));
PLTFM_MSG_ALWAYS("R_AX_SYS_CFG5=0x%x\n",
MAC_REG_R32(R_AX_SYS_CFG5));
PLTFM_MSG_ALWAYS("R_AX_IC_PWR_STATE=0x%x\n",
MAC_REG_R32(R_AX_IC_PWR_STATE));
switch (intf) {
case MAC_AX_INTF_USB:
PLTFM_MSG_ALWAYS("USB HRPWM=0x%x\n",
MAC_REG_R16(R_AX_USB_D2F_F2D_INFO + 2));
break;
case MAC_AX_INTF_SDIO:
PLTFM_MSG_ALWAYS("SDIO HRPWM=0x%x\n",
MAC_REG_R16(R_AX_SDIO_HRPWM1 + 2));
break;
case MAC_AX_INTF_PCIE:
PLTFM_MSG_ALWAYS("PCIE HRPWM=0x%x\n",
MAC_REG_R16(R_AX_PCIE_HRPWM));
break;
default:
PLTFM_MSG_ALWAYS("RPWM error interface=%d\n",
intf);
break;
}
PLTFM_MSG_ALWAYS("R_AX_RPWM=0x%x\n",
MAC_REG_R16(R_AX_RPWM));
PLTFM_MSG_ALWAYS("R_AX_LDM=0x%x\n",
MAC_REG_R32(R_AX_LDM));
if (mac_io_chk_access(adapter, R_AX_CPWM) == MACSUCCESS) {
PLTFM_MSG_ALWAYS("R_AX_CPWM=0x%x\n",
MAC_REG_R16(R_AX_CPWM));
}
}
u32 fw_backtrace_dump(struct mac_ax_adapter *adapter)
{
u32 addr = 0;
u32 str_addr = 0;
u32 size = 0;
u32 key = 0;
u32 i;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct fw_backtrace_info info;
if (adapter->mac_pwr_info.pwr_seq_proc ||
adapter->sm.pwr != MAC_AX_PWR_ON ||
adapter->mac_pwr_info.pwr_in_lps ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) {
PLTFM_MSG_ERR("[ERR]pwr seq proc %d/sm pwr %d/pwr in lps %d\n",
adapter->mac_pwr_info.pwr_seq_proc,
adapter->sm.pwr,
adapter->mac_pwr_info.pwr_in_lps);
PLTFM_MSG_ERR("[ERR]sm fw rst %d\n", adapter->sm.fw_rst);
return MACPROCERR;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
addr = RSVD_PLE_OFST_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
addr = RSVD_PLE_OFST_8852B;
} else {
PLTFM_MSG_ERR("[ERR]unknown chip id\n");
return MACCHIPID;
}
// Get FW Backtrace start address and size
addr = base_addr_map_tbl[MAC_AX_MEM_SHARED_BUF] + addr;
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, addr);
str_addr = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY) & ~0xA0000000;
size = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + FW_BACKTRACE_SIZE_OFST);
key = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + FW_BACKTRACE_KEY_OFST);
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_ERR("FW Backtrace addr(0x%x), size(0x%x), key(0x%x)\n", str_addr, size, key);
if (str_addr == 0)
return MACBADDR;
if (size == 0 || size > FW_BACKTRACE_MAX_SIZE
|| (size % sizeof(struct fw_backtrace_info) != 0))
return MACBUFSZ;
if (key != FW_BACKTRACE_KEY)
return MACNOITEM;
// Dump FW backtrace
PLTFM_MSG_WARN("%s ind access FW backtrace start\n", __func__);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, str_addr);
for (i = 0; i < size; i += sizeof(struct fw_backtrace_info)) {
info.ra = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + i);
info.sp = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + i + 4);
PLTFM_MSG_ERR("Next SP:0x%x, Next RA:0x%x\n", info.sp, info.ra);
}
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access FW backtrace end\n", __func__);
return MACSUCCESS;
}
void pltfm_dbg_dump(struct mac_ax_adapter *adapter)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
PLTFM_MSG_ERR("R_AX_SER_DBG_INFO =0x%08x\n",
MAC_REG_R32(R_AX_SER_DBG_INFO));
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_INIT_CFG1, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_INIT_CFG1 = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_DMA_STOP, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_DMA_STOP = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_INIT_CFG2, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_INIT_CFG2 = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_INFO, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_INFO = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_BUSY, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_BUSY = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH0_RXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH0_RXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH1_RXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH1_RXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH2_RXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH2_RXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH3_RXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH3_RXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH4_RXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH4_RXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH5_RXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH5_RXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH0_TXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH0_TXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH1_TXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH1_TXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH2_TXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH2_TXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_CH3_TXBD_IDX, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_CH3_TXBD_IDX = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_DBG_ERR_FLAG, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_DBG_ERR_FLAG = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWIMR0, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWIMR0 = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWIMR1, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWIMR1 = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWISR0, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWISR0 = 0x%x\n", val32);
val32 = mac_sram_dbg_read(adapter, R_PL_AXIDMA_FWISR1, AXIDMA_SEL);
PLTFM_MSG_ALWAYS("R_PL_AXIDMA_FWISR1 = 0x%x\n", val32);
}
u32 fw_st_dbg_dump(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, i;
if (adapter->mac_pwr_info.pwr_seq_proc ||
adapter->sm.pwr != MAC_AX_PWR_ON) {
PLTFM_MSG_ERR("[ERR]pwr seq proc %d/sm pwr %d\n",
adapter->mac_pwr_info.pwr_seq_proc,
adapter->sm.pwr);
return MACPROCERR;
}
PLTFM_MSG_ALWAYS("FW status = 0x%x\n", MAC_REG_R32(R_AX_UDM0));
PLTFM_MSG_ALWAYS("FW BADADDR = 0x%x\n", MAC_REG_R32(R_AX_UDM1));
PLTFM_MSG_ALWAYS("FW EPC/RA = 0x%x\n", MAC_REG_R32(R_AX_UDM2));
PLTFM_MSG_ALWAYS("FW MISC = 0x%x\n", MAC_REG_R32(R_AX_UDM3));
PLTFM_MSG_ALWAYS("R_AX_HALT_C2H = 0x%x\n", MAC_REG_R32(R_AX_HALT_C2H));
if (mac_io_chk_access(adapter, R_AX_SER_DBG_INFO) == MACSUCCESS)
PLTFM_MSG_ALWAYS("R_AX_SER_DBG_INFO = 0x%x\n", MAC_REG_R32(R_AX_SER_DBG_INFO));
/* Dump FW program counter */
MAC_REG_W32(R_AX_DBG_CTRL, DBG_SEL_FW_PROG_CNTR);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
for (i = 0; i < FW_PROG_CNTR_DMP_CNT; i++) {
PLTFM_MSG_ALWAYS("FW PC = 0x%x\n",
MAC_REG_R32(R_AX_DBG_PORT_SEL));
PLTFM_DELAY_US(FW_PROG_CNTR_DMP_DLY_US);
}
return MACSUCCESS;
}
u32 rsvd_ple_dump(struct mac_ax_adapter *adapter)
{
u32 ret;
u32 addr;
if (adapter->mac_pwr_info.pwr_seq_proc ||
adapter->sm.pwr != MAC_AX_PWR_ON ||
adapter->mac_pwr_info.pwr_in_lps ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) {
PLTFM_MSG_ERR("[ERR]pwr seq proc %d/sm pwr %d/pwr in lps %d\n",
adapter->mac_pwr_info.pwr_seq_proc,
adapter->sm.pwr,
adapter->mac_pwr_info.pwr_in_lps);
PLTFM_MSG_ERR("[ERR]sm fw rst %d\n", adapter->sm.fw_rst);
return MACPROCERR;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
addr = RSVD_PLE_OFST_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
addr = RSVD_PLE_OFST_8852B;
} else {
PLTFM_MSG_ERR("[ERR]unknown chip id\n");
return MACCHIPID;
}
ret = mac_mem_dump(adapter, MAC_AX_MEM_SHARED_BUF, addr, 0,
FW_RSVD_PLE_SIZE, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("Dump fw rsvd ple\n");
return ret;
}
ret = fw_backtrace_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("fw backtrace dump %d\n", ret);
return MACSUCCESS;
}
static u32 crit_dbg_dump(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
PLTFM_MSG_ALWAYS("R_AX_SYS_ISO_CTRL=0x%x\n",
MAC_REG_R16(R_AX_SYS_ISO_CTRL));
PLTFM_MSG_ALWAYS("R_AX_SYS_FUNC_EN=0x%x\n",
MAC_REG_R16(R_AX_SYS_FUNC_EN));
PLTFM_MSG_ALWAYS("R_AX_SYS_PW_CTRL=0x%x\n",
MAC_REG_R32(R_AX_SYS_PW_CTRL));
PLTFM_MSG_ALWAYS("R_AX_SYS_CLK_CTRL=0x%x\n",
MAC_REG_R16(R_AX_SYS_CLK_CTRL));
PLTFM_MSG_ALWAYS("R_AX_SYS_EEPROM_CTRL=0x%x\n",
MAC_REG_R16(R_AX_SYS_EEPROM_CTRL));
PLTFM_MSG_ALWAYS("R_AX_DBG_CTRL=0x%x\n",
MAC_REG_R32(R_AX_DBG_CTRL));
PLTFM_MSG_ALWAYS("R_AX_PLATFORM_ENABLE=0x%x\n",
MAC_REG_R32(R_AX_PLATFORM_ENABLE));
PLTFM_MSG_ALWAYS("R_AX_WLLPS_CTRL=0x%x\n",
MAC_REG_R32(R_AX_WLLPS_CTRL));
PLTFM_MSG_ALWAYS("R_AX_WLRESUME_CTRL=0x%x\n",
MAC_REG_R32(R_AX_WLRESUME_CTRL));
PLTFM_MSG_ALWAYS("R_AX_DBG_PORT_SEL=0x%x\n",
MAC_REG_R32(R_AX_DBG_PORT_SEL));
PLTFM_MSG_ALWAYS("R_AX_HALT_H2C_CTRL=0x%x\n",
MAC_REG_R32(R_AX_HALT_H2C_CTRL));
PLTFM_MSG_ALWAYS("R_AX_HALT_H2C=0x%x\n",
MAC_REG_R32(R_AX_HALT_H2C));
PLTFM_MSG_ALWAYS("R_AX_HALT_C2H_CTRL=0x%x\n",
MAC_REG_R32(R_AX_HALT_C2H_CTRL));
PLTFM_MSG_ALWAYS("R_AX_HALT_C2H=0x%x\n",
MAC_REG_R32(R_AX_HALT_C2H));
PLTFM_MSG_ALWAYS("R_AX_SYS_CFG5=0x%x\n",
MAC_REG_R32(R_AX_SYS_CFG5));
PLTFM_MSG_ALWAYS("R_AX_WCPU_FW_CTRL=0x%x\n",
MAC_REG_R32(R_AX_WCPU_FW_CTRL));
PLTFM_MSG_ALWAYS("R_AX_RPWM=0x%x\n",
MAC_REG_R16(R_AX_RPWM));
PLTFM_MSG_ALWAYS("R_AX_BOOT_REASON=0x%x\n",
MAC_REG_R16(R_AX_BOOT_REASON));
PLTFM_MSG_ALWAYS("R_AX_LDM=0x%x\n",
MAC_REG_R32(R_AX_LDM));
PLTFM_MSG_ALWAYS("R_AX_UDM0=0x%x\n",
MAC_REG_R32(R_AX_UDM0));
PLTFM_MSG_ALWAYS("R_AX_UDM1=0x%x\n",
MAC_REG_R32(R_AX_UDM1));
PLTFM_MSG_ALWAYS("R_AX_UDM2=0x%x\n",
MAC_REG_R32(R_AX_UDM2));
PLTFM_MSG_ALWAYS("R_AX_UDM3=0x%x\n",
MAC_REG_R32(R_AX_UDM3));
PLTFM_MSG_ALWAYS("R_AX_IC_PWR_STATE=0x%x\n",
MAC_REG_R32(R_AX_IC_PWR_STATE));
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTF=0x%x\n",
MAC_REG_R32(R_AX_PCIE_MIO_INTF));
PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTD=0x%x\n",
MAC_REG_R32(R_AX_PCIE_MIO_INTD));
PLTFM_MSG_ALWAYS("R_AX_PCIE_INIT_CFG1=0x%x\n",
MAC_REG_R32(R_AX_PCIE_INIT_CFG1));
PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_STOP1=0x%x\n",
MAC_REG_R32(R_AX_PCIE_DMA_STOP1));
PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_BUSY1=0x%x\n",
MAC_REG_R32(R_AX_PCIE_DMA_BUSY1));
PLTFM_MSG_ALWAYS("R_AX_PCIE_DBG_CTRL=0x%x\n",
MAC_REG_R32(R_AX_PCIE_DBG_CTRL));
PLTFM_MSG_ALWAYS("R_AX_DBG_ERR_FLAG=0x%x\n",
MAC_REG_R32(R_AX_DBG_ERR_FLAG));
PLTFM_MSG_ALWAYS("R_AX_LBC_WATCHDOG=0x%x\n",
MAC_REG_R32(R_AX_LBC_WATCHDOG));
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
PLTFM_MSG_ALWAYS("R_AX_ACH0_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH0_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH1_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH1_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH2_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH2_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH3_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH3_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH4_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH4_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH5_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH5_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH6_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH6_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH7_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH7_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_CH8_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_CH8_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_CH9_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_CH9_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_CH12_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_CH12_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_RXQ_RXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_RXQ_RXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_RPQ_RXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_RPQ_RXBD_IDX));
}
}
return MACSUCCESS;
}
static u32 ss_dbgpkg(struct mac_ax_adapter *adapter, struct mac_ax_dbgpkg *val)
{
u8 wmm, ac;
u16 macid;
struct ss_link_info link;
u16 macid_num = adapter->hw_info->macid_num;
u8 wmm_num;
u8 ul_vld;
u32 ret;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] check dmac en %d\n", ret);
return ret;
}
switch (adapter->hw_info->chip_id) {
case MAC_AX_CHIP_ID_8852A:
wmm_num = SS_WMM_NUM_8852A;
ul_vld = SS_UL_SUPPORT_8852A;
break;
case MAC_AX_CHIP_ID_8852B:
wmm_num = SS_WMM_NUM_8852B;
ul_vld = SS_UL_SUPPORT_8852B;
break;
default:
wmm_num = 0;
ul_vld = 0;
break;
}
for (macid = 0; macid < macid_num; macid++)
val->ss_dbg_0 |= ss_tx_len_chk(adapter, macid);
link.ul = 0;
for (wmm = 0; wmm < wmm_num; wmm++) {
link.wmm = wmm;
for (ac = 0; ac < 4; ac++) {
link.ac = ac;
val->ss_dbg_0 |= ss_link_chk(adapter, &link);
}
}
if (ul_vld) {
link.ul = 1;
link.wmm = 0;
link.ac = 0;
val->ss_dbg_0 |= ss_link_chk(adapter, &link);
}
val->ss_dbg_1 |= ss_stat_chk(adapter);
ss_dbgpkg_val_parser(adapter, val);
return MACSUCCESS;
}
static u32 dle_dbg_dump(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct dle_dfi_freepg_t freepg;
struct dle_dfi_quota_t quota;
struct dle_dfi_qempty_t qempty;
u32 qtaid, grpsel;
u32 qnum, qtanum, ret, val32;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] check dmac en %d\n", ret);
return ret;
}
PLTFM_MSG_ALWAYS("R_AX_WDE_PKTBUF_CFG=0x%x\n",
MAC_REG_R32(R_AX_WDE_PKTBUF_CFG));
PLTFM_MSG_ALWAYS("R_AX_PLE_PKTBUF_CFG=0x%x\n",
MAC_REG_R32(R_AX_PLE_PKTBUF_CFG));
val32 = MAC_REG_R32(R_AX_WDE_QTA0_CFG);
PLTFM_MSG_ALWAYS("[WDE][HIF]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q0_MIN_SIZE));
PLTFM_MSG_ALWAYS("[WDE][HIF]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q0_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_WDE_QTA1_CFG);
PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q1_MIN_SIZE));
PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q1_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_WDE_QTA2_CFG);
PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q2_MIN_SIZE));
PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q2_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_WDE_QTA3_CFG);
PLTFM_MSG_ALWAYS("[WDE][PKTIN]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q3_MIN_SIZE));
PLTFM_MSG_ALWAYS("[WDE][PKTIN]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q3_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_WDE_QTA4_CFG);
PLTFM_MSG_ALWAYS("[WDE][CPUIO]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q4_MIN_SIZE));
PLTFM_MSG_ALWAYS("[WDE][CPUIO]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_WDE_Q4_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA0_CFG);
PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q0_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q0_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA1_CFG);
PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q1_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q1_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA2_CFG);
PLTFM_MSG_ALWAYS("[PLE][C2H]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q2_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][C2H]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q2_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA3_CFG);
PLTFM_MSG_ALWAYS("[PLE][H2C]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q3_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][H2C]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q3_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA4_CFG);
PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q4_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q4_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA5_CFG);
PLTFM_MSG_ALWAYS("[PLE][MPDU]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q5_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][MPDU]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q5_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA6_CFG);
PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q6_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q6_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA7_CFG);
PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q7_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q7_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA8_CFG);
PLTFM_MSG_ALWAYS("[PLE][BBRPT]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q8_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][BBRPT]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q8_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA9_CFG);
PLTFM_MSG_ALWAYS("[PLE][WDRLS]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q9_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][WDRLS]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q9_MAX_SIZE));
val32 = MAC_REG_R32(R_AX_PLE_QTA10_CFG);
PLTFM_MSG_ALWAYS("[PLE][CPUIO]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q10_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][CPUIO]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q10_MAX_SIZE));
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = MAC_REG_R32(R_AX_PLE_QTA11_CFG);
PLTFM_MSG_ALWAYS("[PLE][TXRPT]min_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q11_MIN_SIZE));
PLTFM_MSG_ALWAYS("[PLE][TXRPT]max_pgnum=0x%x\n",
GET_FIELD(val32, B_AX_PLE_Q11_MAX_SIZE));
}
freepg.dle_type = DLE_CTRL_TYPE_WDE;
ret = dle_dfi_freepg(adapter, &freepg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] wde dfi freepg %d\n", ret);
return ret;
}
PLTFM_MSG_ALWAYS("[WDE]free_headpg = 0x%x\n", freepg.free_headpg);
PLTFM_MSG_ALWAYS("[WDE]free_tailpg = 0x%x\n", freepg.free_tailpg);
PLTFM_MSG_ALWAYS("[WDE]pub_pgnum = 0x%x\n", freepg.pub_pgnum);
freepg.dle_type = DLE_CTRL_TYPE_PLE;
ret = dle_dfi_freepg(adapter, &freepg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] ple dfi freepg %d\n", ret);
return ret;
}
PLTFM_MSG_ALWAYS("[PLE]free_headpg = 0x%x\n", freepg.free_headpg);
PLTFM_MSG_ALWAYS("[PLE]free_tailpg = 0x%x\n", freepg.free_tailpg);
PLTFM_MSG_ALWAYS("[PLE]pub_pgunm = 0x%x\n", freepg.pub_pgnum);
quota.dle_type = DLE_CTRL_TYPE_WDE;
for (qtaid = 0; qtaid < WDE_QTA_NUM; qtaid++) {
quota.qtaid = qtaid;
ret = dle_dfi_quota(adapter, "a);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] wde dfi quota %d\n", ret);
return ret;
}
switch (qtaid) {
case WDE_QTAID_HOST_IF:
PLTFM_MSG_ALWAYS("[WDE][HIF]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[WDE][HIF]use_pgnum = %d\n",
quota.use_pgnum);
break;
case WDE_QTAID_WLAN_CPU:
PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[WDE][WLAN_CPU]use_pgnum = %d\n",
quota.use_pgnum);
break;
case WDE_QTAID_DATA_CPU:
PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[WDE][DATA_CPU]use_pgnum = %d\n",
quota.use_pgnum);
break;
case WDE_QTAID_PKTIN:
PLTFM_MSG_ALWAYS("[WDE][PKTIN]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[WDE][PKTIN]use_pgnum = %d\n",
quota.use_pgnum);
break;
case WDE_QTAID_CPUIO:
PLTFM_MSG_ALWAYS("[WDE][CPUIO]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[WDE][CPUIO]use_pgnum = %d\n",
quota.use_pgnum);
break;
}
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
qtanum = PLE_QTA_NUM_8852AB;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
qtanum = PLE_QTA_NUM_8852C;
} else {
PLTFM_MSG_ERR("[ERR] ple qta num not define\n");
return MACCHIPID;
}
quota.dle_type = DLE_CTRL_TYPE_PLE;
for (qtaid = 0; qtaid < qtanum; qtaid++) {
quota.qtaid = qtaid;
ret = dle_dfi_quota(adapter, "a);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] dle dfi quota %d\n", ret);
return ret;
}
switch (qtaid) {
case PLE_QTAID_B0_TXPL:
PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][B0_TXPL]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_B1_TXPL:
PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][B1_TXPL]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_C2H:
PLTFM_MSG_ALWAYS("[PLE][C2H]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][C2H]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_H2C:
PLTFM_MSG_ALWAYS("[PLE][H2C]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][H2C]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_WLAN_CPU:
PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][WLAN_CPU]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_MPDU:
PLTFM_MSG_ALWAYS("[PLE][MPDU]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][MPDU]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_CMAC0_RX:
PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_CMAC1_RX:
PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_BBRPT:
PLTFM_MSG_ALWAYS("[PLE][BBRPT]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][BBRPT]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_WDRLS:
PLTFM_MSG_ALWAYS("[PLE][WDRLS]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][WDRLS]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_CPUIO:
PLTFM_MSG_ALWAYS("[PLE][CPUIO]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][CPUIO]use_pgnum = %d\n",
quota.use_pgnum);
break;
case PLE_QTAID_TXRPT:
PLTFM_MSG_ALWAYS("[PLE][TXRPT]rsv_pgnum = %d\n",
quota.rsv_pgnum);
PLTFM_MSG_ALWAYS("[PLE][TXRPT]use_pgnum = %d\n",
quota.use_pgnum);
break;
default:
PLTFM_MSG_ERR("[ERR] ple invalid qtaid %d\n", qtaid);
break;
}
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
qnum = WDE_QEMPTY_NUM_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
qnum = WDE_QEMPTY_NUM_8852B;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
qnum = WDE_QEMPTY_NUM_8852C;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
qnum = WDE_QEMPTY_NUM_8192XB;
} else {
PLTFM_MSG_ERR("[ERR] wde qempty num not define\n");
return MACCHIPID;
}
qempty.dle_type = DLE_CTRL_TYPE_WDE;
for (grpsel = 0; grpsel < qnum; grpsel++) {
qempty.grpsel = grpsel;
ret = dle_dfi_qempty(adapter, &qempty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] wde dfi qempty %d\n", ret);
return ret;
}
PLTFM_MSG_ALWAYS("[WDE][Group_%d]qempty = 0x%x\n",
grpsel, qempty.qempty);
}
qempty.dle_type = DLE_CTRL_TYPE_PLE;
for (grpsel = 0; grpsel < PLE_QEMPTY_NUM; grpsel++) {
qempty.grpsel = grpsel;
ret = dle_dfi_qempty(adapter, &qempty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] ple dfi qempty %d\n", ret);
return ret;
}
PLTFM_MSG_ALWAYS("[PLE][Group_%d]qempty = 0x%x\n",
grpsel, qempty.qempty);
}
return MACSUCCESS;
}
static u8 chk_dle_dfi_valid(struct mac_ax_adapter *adapter, u32 dbg_sel)
{
if ((check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) == MACSUCCESS) &&
dbg_sel <= MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY)
return 1;
return 0;
}
u32 dle_dfi_sel(struct mac_ax_adapter *adapter,
struct mac_ax_dle_dfi_info **info,
u32 *target, u32 sel)
{
switch (sel) {
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG:
*info = &dle_dfi_wde_bufmgn_freepg;
*target = DLE_DFI_TYPE_FREEPG;
PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN FREEPG:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA:
*info = &dle_dfi_wde_bufmgn_quota;
*target = DLE_DFI_TYPE_QUOTA;
PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN QUOTA:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT:
*info = &dle_dfi_wde_bufmgn_pagellt;
*target = DLE_DFI_TYPE_PAGELLT;
PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN PAGELLT:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO:
*info = &dle_dfi_wde_bufmgn_pktinfo;
*target = DLE_DFI_TYPE_PKTINFO;
PLTFM_MSG_ALWAYS("Dump debug port WDE BUFMGN PKTINFO:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT:
*info = &dle_dfi_wde_quemgn_prepkt;
*target = DLE_DFI_TYPE_PREPKTLLT;
PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN PREPKT:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT:
*info = &dle_dfi_wde_quemgn_nxtpkt;
*target = DLE_DFI_TYPE_NXTPKTLLT;
PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN NXTPKT:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL:
*info = &dle_dfi_wde_quemgn_qlnktbl;
*target = DLE_DFI_TYPE_QLNKTBL;
PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN QLNKTBL:\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY:
*info = &dle_dfi_wde_quemgn_qempty;
*target = DLE_DFI_TYPE_QEMPTY;
PLTFM_MSG_ALWAYS("Dump debug port WDE QUEMGN QEMPTY:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG:
*info = &dle_dfi_ple_bufmgn_freepg;
*target = DLE_DFI_TYPE_FREEPG;
PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN FREEPG:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA:
*info = &dle_dfi_ple_bufmgn_quota;
*target = DLE_DFI_TYPE_QUOTA;
PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN QUOTA:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT:
*info = &dle_dfi_ple_bufmgn_pagellt;
*target = DLE_DFI_TYPE_PAGELLT;
PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN PAGELLT:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO:
*info = &dle_dfi_ple_bufmgn_pktinfo;
*target = DLE_DFI_TYPE_PKTINFO;
PLTFM_MSG_ALWAYS("Dump debug port PLE BUFMGN PKTINFO:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT:
*info = &dle_dfi_ple_quemgn_prepkt;
*target = DLE_DFI_TYPE_PREPKTLLT;
PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN PREPKT:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT:
*info = &dle_dfi_ple_quemgn_nxtpkt;
*target = DLE_DFI_TYPE_NXTPKTLLT;
PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN NXTPKT:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL:
*info = &dle_dfi_ple_quemgn_qlnktbl;
*target = DLE_DFI_TYPE_QLNKTBL;
PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN QLNKTBL:\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY:
*info = &dle_dfi_ple_quemgn_qempty;
*target = DLE_DFI_TYPE_QEMPTY;
PLTFM_MSG_ALWAYS("Dump debug port PLE QUEMGN QEMPTY:\n");
break;
default:
PLTFM_MSG_ALWAYS("dle dfi select err\n");
*info = NULL;
return MACDBGPORTSEL;
}
return MACSUCCESS;
}
static u32 dle_dfi_dump(struct mac_ax_adapter *adapter, u32 sel)
{
struct mac_ax_dle_dfi_info *info;
struct dle_dfi_ctrl_t ctrl;
u32 ret, i;
ret = dle_dfi_sel(adapter, &info, &ctrl.target, sel);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] dle dfi sel %d %d\n", sel, ret);
return ret;
}
if (sel <= MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY) {
ctrl.type = DLE_CTRL_TYPE_WDE;
} else if (sel >= MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG &&
sel <= MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY) {
ctrl.type = DLE_CTRL_TYPE_PLE;
} else {
PLTFM_MSG_ERR("[ERR]unknown dle dfi sel-2 %d\n", sel);
return MACFUNCINPUT;
}
switch (sel) {
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG:
PLTFM_MSG_ALWAYS("WDE_BUFMGN_FREEPG\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA:
PLTFM_MSG_ALWAYS("WDE_BUFMGN_QUOTA\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT:
PLTFM_MSG_ALWAYS("WDE_BUFMGN_PAGELLT\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO:
PLTFM_MSG_ALWAYS("WDE_BUFMGN_PKTINFO\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT:
PLTFM_MSG_ALWAYS("WDE_QUEMGN_PREPKT\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT:
PLTFM_MSG_ALWAYS("WDE_QUEMGN_NXTPKT\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL:
PLTFM_MSG_ALWAYS("WDE_QUEMGN_QLNKTBL\n");
break;
case MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY:
PLTFM_MSG_ALWAYS("WDE_QUEMGN_QEMPTY\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG:
PLTFM_MSG_ALWAYS("PLE_BUFMGN_FREEPG\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA:
PLTFM_MSG_ALWAYS("PLE_BUFMGN_QUOTA\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT:
PLTFM_MSG_ALWAYS("PLE_BUFMGN_PAGELLT\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO:
PLTFM_MSG_ALWAYS("PLE_BUFMGN_PKTINFO\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT:
PLTFM_MSG_ALWAYS("PLE_QUEMGN_PREPKT\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT:
PLTFM_MSG_ALWAYS("PLE_QUEMGN_NXTPKT\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL:
PLTFM_MSG_ALWAYS("PLE_QUEMGN_QLNKTBL\n");
break;
case MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY:
PLTFM_MSG_ALWAYS("PLE_QUEMGN_QEMPTY\n");
break;
default:
break;
}
for (i = info->srt; i <= info->end; i += info->inc_num) {
ctrl.addr = i;
ret = dle_dfi_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle dfi ctrl %d\n", ret);
return ret;
}
PLTFM_MSG_ALWAYS("trg %d addr 0x%X: 0x%X\n",
ctrl.target, ctrl.addr, ctrl.out_data);
}
return MACSUCCESS;
}
static u32 tx_cnt_dump(struct mac_ax_adapter *adapter, u8 band, u32 loop_num)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret, reg, val32, i;
u8 idx;
u32 prev_cnt[TMAC_TX_CNT_NUM];
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret);
return ret;
}
PLTFM_MEMSET(prev_cnt, 0, sizeof(prev_cnt));
reg = band == MAC_AX_BAND_1 ? R_AX_TX_PPDU_CNT_C1 : R_AX_TX_PPDU_CNT;
for (i = 0; i < loop_num; i++) {
for (idx = 0; idx < TMAC_TX_CNT_NUM; idx++) {
MAC_REG_W8(reg, idx);
PLTFM_DELAY_US(TRX_CNT_READ_DLY_US);
val32 = GET_FIELD(MAC_REG_R32(reg), B_AX_TX_PPDU_CNT);
if (i == 0 || val32 != prev_cnt[idx])
PLTFM_MSG_ALWAYS("B%d TX_PPDU_CNT[%d]-%d=0x%x\n",
band, idx, i, val32);
prev_cnt[idx] = val32;
}
PLTFM_DELAY_US(TRX_CNT_REPT_DLY_US);
}
return MACSUCCESS;
}
static u32 rx_cnt_dump(struct mac_ax_adapter *adapter, u8 band, u32 loop_num)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret, reg, val32, i;
u8 idx;
u32 prev_cnt[RMAC_RX_CNT_NUM];
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret);
return ret;
}
PLTFM_MEMSET(prev_cnt, 0, sizeof(prev_cnt));
reg = band == MAC_AX_BAND_1 ?
R_AX_RX_DBG_CNT_SEL_C1 : R_AX_RX_DBG_CNT_SEL;
for (i = 0; i < loop_num; i++) {
for (idx = 0; idx < RMAC_RX_CNT_NUM; idx++) {
MAC_REG_W8(reg, idx);
PLTFM_DELAY_US(TRX_CNT_READ_DLY_US);
val32 = GET_FIELD(MAC_REG_R32(reg), B_AX_RX_DBG_CNT);
if (i == 0 || val32 != prev_cnt[idx])
PLTFM_MSG_ALWAYS("B%d RX_CNT[%d]-%d=0x%x\n",
band, idx, i, val32);
prev_cnt[idx] = val32;
}
PLTFM_DELAY_US(TRX_CNT_REPT_DLY_US);
}
return MACSUCCESS;
}
static u32 dmac_dbg_dump(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
/* Func/Clk */
PLTFM_MSG_ALWAYS("R_AX_DMAC_FUNC_EN=0x%x\n",
MAC_REG_R32(R_AX_DMAC_FUNC_EN));
PLTFM_MSG_ALWAYS("R_AX_DMAC_CLK_EN=0x%x\n",
MAC_REG_R32(R_AX_DMAC_CLK_EN));
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ALWAYS("[ERR] check dmac en %d\n", ret);
return ret;
}
/* Common */
PLTFM_MSG_ALWAYS("R_AX_SER_DBG_INFO=0x%x\n",
MAC_REG_R32(R_AX_SER_DBG_INFO));
PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY0=0x%x\n",
MAC_REG_R32(R_AX_DLE_EMPTY0));
PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY1=0x%x\n",
MAC_REG_R32(R_AX_DLE_EMPTY1));
/* Error IMR/ISR & Flag */
PLTFM_MSG_ALWAYS("R_AX_DMAC_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_DMAC_ERR_IMR));
PLTFM_MSG_ALWAYS("R_AX_DMAC_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_DMAC_ERR_ISR));
PLTFM_MSG_ALWAYS("[0]R_AX_WDRLS_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_WDRLS_ERR_IMR));
PLTFM_MSG_ALWAYS("[0]R_AX_WDRLS_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_WDRLS_ERR_ISR));
PLTFM_MSG_ALWAYS("[1]R_AX_SEC_ERR_IMR_ISR=0x%x\n",
MAC_REG_R32(R_AX_SEC_DEBUG));
PLTFM_MSG_ALWAYS("[2.1]R_AX_MPDU_TX_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR));
PLTFM_MSG_ALWAYS("[2.1]R_AX_MPDU_TX_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR));
PLTFM_MSG_ALWAYS("[2.2]R_AX_MPDU_RX_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR));
PLTFM_MSG_ALWAYS("[2.2]R_AX_MPDU_RX_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_MPDU_RX_ERR_ISR));
PLTFM_MSG_ALWAYS("[3]R_AX_STA_SCHEDULER_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR));
PLTFM_MSG_ALWAYS("[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_ISR));
PLTFM_MSG_ALWAYS("[4]R_AX_WDE_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_WDE_ERR_IMR));
PLTFM_MSG_ALWAYS("[4]R_AX_WDE_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_WDE_ERR_ISR));
PLTFM_MSG_ALWAYS("[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%x\n",
MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR));
PLTFM_MSG_ALWAYS("[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%x\n",
MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
PLTFM_MSG_ALWAYS("[6]R_AX_PLE_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_PLE_ERR_IMR));
PLTFM_MSG_ALWAYS("[6]R_AX_PLE_ERR_FLAG_ISR=0x%x\n",
MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR));
PLTFM_MSG_ALWAYS("[7]R_AX_PKTIN_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_PKTIN_ERR_IMR));
PLTFM_MSG_ALWAYS("[7]R_AX_PKTIN_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_PKTIN_ERR_ISR));
PLTFM_MSG_ALWAYS("[8.1]R_AX_OTHER_DISPATCHER_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR));
PLTFM_MSG_ALWAYS("[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_ISR));
PLTFM_MSG_ALWAYS("[8.2]R_AX_HOST_DISPATCHER_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR));
PLTFM_MSG_ALWAYS("[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_ISR));
PLTFM_MSG_ALWAYS("[8.3]R_AX_CPU_DISPATCHER_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR));
PLTFM_MSG_ALWAYS("[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_ISR));
PLTFM_MSG_ALWAYS("[10]R_AX_CPUIO_ERR_IMR=0x%x\n",
MAC_REG_R32(R_AX_CPUIO_ERR_IMR));
PLTFM_MSG_ALWAYS("[10]R_AX_CPUIO_ERR_ISR=0x%x\n",
MAC_REG_R32(R_AX_CPUIO_ERR_ISR));
PLTFM_MSG_ALWAYS("[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%x\n",
MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR));
PLTFM_MSG_ALWAYS("[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%x\n",
MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_IMR_ISR));
PLTFM_MSG_ALWAYS("[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%x\n",
MAC_REG_R32(R_AX_BBRPT_DFS_ERR_IMR_ISR));
PLTFM_MSG_ALWAYS("[11.4]R_AX_LA_ERRFLAG=0x%x\n",
MAC_REG_R32(R_AX_LA_ERRFLAG));
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
PLTFM_MSG_ALWAYS("R_AX_HCI_FC_ERR_FLAG=0x%x\n",
MAC_REG_R32(R_AX_HCI_FC_ERR_FLAG_V1));
} else {
PLTFM_MSG_ALWAYS("R_AX_HCI_FC_ERR_FLAG=0x%x\n",
MAC_REG_R32(R_AX_HCI_FC_ERR_FLAG));
}
/* Dispatcher */
PLTFM_MSG_ALWAYS("R_AX_DISPATCHER_GLOBAL_SETTING_0=0x%x\n",
MAC_REG_R32(R_AX_DISPATCHER_GLOBAL_SETTING_0));
PLTFM_MSG_ALWAYS("R_AX_TX_ADDRESS_INFO_MODE_SETTING=0x%x\n",
MAC_REG_R32(R_AX_TX_ADDRESS_INFO_MODE_SETTING));
PLTFM_MSG_ALWAYS("R_AX_CPU_PORT_DEBUG_SETTING=0x%x\n",
MAC_REG_R32(R_AX_CPU_PORT_DEBUG_SETTING));
PLTFM_MSG_ALWAYS("R_AX_HDP_DBG_INFO_4=0x%x\n",
MAC_REG_R32(R_AX_HDP_DBG_INFO_4));
/* PKTIN */
PLTFM_MSG_ALWAYS("R_AX_PKTIN_SETTING=0x%x\n",
MAC_REG_R32(R_AX_PKTIN_SETTING));
/* MPDU Proc */
PLTFM_MSG_ALWAYS("R_AX_TX_PTK_CNT=0x%x\n",
MAC_REG_R32(R_AX_TX_PTK_CNT));
PLTFM_MSG_ALWAYS("R_AX_MPDU_TX_ERRFLAG=0x%x\n",
MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR));
PLTFM_MSG_ALWAYS("R_AX_MPDU_TX_ERRFLAG_MSK=0x%x\n",
MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR));
PLTFM_MSG_ALWAYS("R_AX_MPDU_RX_PKTCNT=0x%x\n",
MAC_REG_R32(R_AX_MPDU_RX_PKTCNT));
PLTFM_MSG_ALWAYS("R_AX_MPDU_DROP_PKTCNT=0x%x\n",
MAC_REG_R32(R_AX_MPDU_DROP_PKTCNT));
/* STA SCH */
PLTFM_MSG_ALWAYS("R_AX_SS_CTRL=0x%x\n", MAC_REG_R32(R_AX_SS_CTRL));
return MACSUCCESS;
}
static u32 cmac_dbg_dump(struct mac_ax_adapter *adapter, enum mac_ax_band band)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret, reg;
if (band == MAC_AX_BAND_1 && is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
return MACSUCCESS;
adapter->sm.l2_st = MAC_AX_L2_DIS;
/* Func/Clk band 0 */
if (band == MAC_AX_BAND_0) {
reg = R_AX_CMAC_FUNC_EN;
PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_FUNC_EN=0x%x\n", band,
MAC_REG_R32(reg));
reg = R_AX_CK_EN;
PLTFM_MSG_ALWAYS("B%d R_AX_CK_EN=0x%x\n", band,
MAC_REG_R32(reg));
}
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] check cmac en %d\n", ret);
return ret;
}
/* Func/Clk band 1 */
if (band == MAC_AX_BAND_1) {
reg = R_AX_CMAC_FUNC_EN_C1;
PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_FUNC_EN=0x%x\n", band,
MAC_REG_R32(reg));
reg = R_AX_CK_EN_C1;
PLTFM_MSG_ALWAYS("B%d R_AX_CK_EN=0x%x\n", band,
MAC_REG_R32(reg));
}
/* Error IMR/ISR & Flag */
reg = band == MAC_AX_BAND_1 ? R_AX_CMAC_ERR_IMR_C1 : R_AX_CMAC_ERR_IMR;
PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_ERR_IMR=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_CMAC_ERR_ISR_C1 : R_AX_CMAC_ERR_ISR;
PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_ERR_ISR=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_SCHEDULE_ERR_IMR_C1 : R_AX_SCHEDULE_ERR_IMR;
PLTFM_MSG_ALWAYS("[0]B%d R_AX_SCHEDULE_ERR_IMR=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_SCHEDULE_ERR_ISR_C1 : R_AX_SCHEDULE_ERR_ISR;
PLTFM_MSG_ALWAYS("[0]B%d R_AX_SCHEDULE_ERR_ISR=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_PTCL_IMR0_C1 : R_AX_PTCL_IMR0;
PLTFM_MSG_ALWAYS("[1]B%d R_AX_PTCL_IMR0=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_PTCL_ISR0_C1 : R_AX_PTCL_ISR0;
PLTFM_MSG_ALWAYS("[1]B%d R_AX_PTCL_ISR0=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_DLE_CTRL_C1 : R_AX_DLE_CTRL;
PLTFM_MSG_ALWAYS("[3]B%d R_AX_DLE_CTRL=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_PHYINFO_ERR_ISR_C1 : R_AX_PHYINFO_ERR_ISR;
PLTFM_MSG_ALWAYS("[4]B%d R_AX_PHYINFO_ERR_ISR=0x%x\n", band,
MAC_REG_R8(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_TXPWR_IMR_C1 : R_AX_TXPWR_IMR;
PLTFM_MSG_ALWAYS("[5]B%d R_AX_TXPWR_IMR=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_TXPWR_ISR_C1 : R_AX_TXPWR_ISR;
PLTFM_MSG_ALWAYS("[5]B%d R_AX_TXPWR_ISR=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_RMAC_ERR_ISR_C1 : R_AX_RMAC_ERR_ISR;
PLTFM_MSG_ALWAYS("[6]B%d R_AX_RMAC_ERR_ISR=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TMAC_ERR_IMR_ISR_C1 : R_AX_TMAC_ERR_IMR_ISR;
PLTFM_MSG_ALWAYS("[7]B%d R_AX_TMAC_ERR_IMR_ISR=0x%x\n", band,
MAC_REG_R32(reg));
/* CMAC DMA */
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_ERR_FLG_0_C1 : R_AX_RXDMA_ERR_FLG_0;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_ERR_FLG_0=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_ERR_FLG_1_C1 : R_AX_RXDMA_ERR_FLG_1;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_ERR_FLG_1=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_PKT_INFO_0_C1 : R_AX_RXDMA_PKT_INFO_0;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_0=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_PKT_INFO_1_C1 : R_AX_RXDMA_PKT_INFO_1;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_1=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_PKT_INFO_2_C1 : R_AX_RXDMA_PKT_INFO_2;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_2=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_PKT_INFO_3_C1 : R_AX_RXDMA_PKT_INFO_3;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_3=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_RXDMA_PKT_INFO_4_C1 : R_AX_RXDMA_PKT_INFO_4;
PLTFM_MSG_ALWAYS("B%d R_AX_RXDMA_PKT_INFO_4=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_FIFO_INFO_0_C1 : R_AX_TXDMA_FIFO_INFO_0;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_FIFO_INFO_0=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_FIFO_INFO_1_C1 : R_AX_TXDMA_FIFO_INFO_1;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_FIFO_INFO_1=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_FIFO_INFO_2_C1 : R_AX_TXDMA_FIFO_INFO_2;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_FIFO_INFO_2=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_TXDMA_DBG_C1 : R_AX_TXDMA_DBG;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_DBG=0x%x\n", band, MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_RU_INFO_0_C1 : R_AX_TXDMA_RU_INFO_0;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_0=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_RU_INFO_1_C1 : R_AX_TXDMA_RU_INFO_1;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_1=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_RU_INFO_2_C1 : R_AX_TXDMA_RU_INFO_2;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_2=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_TXDMA_RU_INFO_3_C1 : R_AX_TXDMA_RU_INFO_3;
PLTFM_MSG_ALWAYS("B%d R_AX_TXDMA_RU_INFO_3=0x%x\n", band,
MAC_REG_R32(reg));
/* TMAC */
reg = band == MAC_AX_BAND_1 ?
R_AX_MACTX_DBG_SEL_CNT_C1 : R_AX_MACTX_DBG_SEL_CNT;
PLTFM_MSG_ALWAYS("B%d R_AX_MACTX_DBG_SEL_CNT=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_WMAC_TX_CTRL_DEBUG_C1 : R_AX_WMAC_TX_CTRL_DEBUG;
PLTFM_MSG_ALWAYS("B%d R_AX_WMAC_TX_CTRL_DEBUG=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_WMAC_TX_INFO0_DEBUG_C1 : R_AX_WMAC_TX_INFO0_DEBUG;
PLTFM_MSG_ALWAYS("B%d R_AX_WMAC_TX_INFO0_DEBUG=0x%x\n", band,
MAC_REG_R32(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_WMAC_TX_INFO1_DEBUG_C1 : R_AX_WMAC_TX_INFO1_DEBUG;
PLTFM_MSG_ALWAYS("B%d R_AX_WMAC_TX_INFO1_DEBUG=0x%x\n", band,
MAC_REG_R32(reg));
/* TMAC TX COUNTER */
ret = tx_cnt_dump(adapter, band, TRX_CNT_REPT_CNT);
if (ret != MACSUCCESS)
PLTFM_MSG_ALWAYS("[ERR]tx cnt dump err %d\n", ret);
/* TRX PTCL */
reg = band == MAC_AX_BAND_1 ?
R_AX_MAC_LOOPBACK_COUNT_C1 : R_AX_MAC_LOOPBACK_COUNT;
PLTFM_MSG_ALWAYS("B%d R_AX_MAC_LOOPBACK_COUNT=0x%x\n", band,
MAC_REG_R32(reg));
/* RMAC */
reg = band == MAC_AX_BAND_1 ? R_AX_RCR_C1 : R_AX_RCR;
PLTFM_MSG_ALWAYS("B%d R_AX_RCR=0x%x\n", band, MAC_REG_R16(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_DLK_PROTECT_CTL_C1 : R_AX_DLK_PROTECT_CTL;
PLTFM_MSG_ALWAYS("B%d R_AX_DLK_PROTECT_CTL=0x%x\n", band, MAC_REG_R16(reg));
reg = band == MAC_AX_BAND_1 ? R_AX_PPDU_STAT_C1 : R_AX_PPDU_STAT;
PLTFM_MSG_ALWAYS("B%d R_AX_PPDU_STAT=0x%x\n", band, MAC_REG_R16(reg));
reg = band == MAC_AX_BAND_1 ?
R_AX_PPDU_STAT_ERR_C1 : R_AX_PPDU_STAT_ERR;
PLTFM_MSG_ALWAYS("B%d R_AX_PPDU_STAT_ERR=0x%x\n", band, MAC_REG_R16(reg));
/* RMAC RX COUNTER */
ret = rx_cnt_dump(adapter, band, TRX_CNT_REPT_CNT);
if (ret != MACSUCCESS)
PLTFM_MSG_ALWAYS("[ERR]rx cnt dump err %d\n", ret);
adapter->sm.l2_st = MAC_AX_L2_EN;
return MACSUCCESS;
}
static u32 tx_dbg_dump(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
u32 i;
PLTFM_MSG_ALWAYS("R_AX_CMAC_MACID_DROP_0=0x%x\n",
MAC_REG_R32(R_AX_CMAC_MACID_DROP_0));
PLTFM_MSG_ALWAYS("R_AX_MBSSID_DROP_0=0x%x\n",
MAC_REG_R32(R_AX_MBSSID_DROP_0));
PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_0=0x%x\n",
MAC_REG_R32(R_AX_MACID_SLEEP_0));
PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_1=0x%x\n",
MAC_REG_R32(R_AX_MACID_SLEEP_1));
PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_2=0x%x\n",
MAC_REG_R32(R_AX_MACID_SLEEP_2));
PLTFM_MSG_ALWAYS("R_AX_MACID_SLEEP_3=0x%x\n",
MAC_REG_R32(R_AX_MACID_SLEEP_3));
PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_0=0x%x\n",
MAC_REG_R32(R_AX_SS_MACID_PAUSE_0));
PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_1=0x%x\n",
MAC_REG_R32(R_AX_SS_MACID_PAUSE_1));
PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_2=0x%x\n",
MAC_REG_R32(R_AX_SS_MACID_PAUSE_2));
PLTFM_MSG_ALWAYS("R_AX_SS_MACID_PAUSE_3=0x%x\n",
MAC_REG_R32(R_AX_SS_MACID_PAUSE_3));
PLTFM_MSG_ALWAYS("R_AX_CTN_TXEN=0x%x\n",
MAC_REG_R32(R_AX_CTN_TXEN));
PLTFM_MSG_ALWAYS("R_AX_PTCL_COMMON_SETTING_0=0x%x\n",
MAC_REG_R32(R_AX_PTCL_COMMON_SETTING_0));
PLTFM_MSG_ALWAYS("R_AX_MAC_LOOPBACK=0x%x\n",
MAC_REG_R32(R_AX_MAC_LOOPBACK));
ret = dbg_port_dump(adapter, MAC_AX_DBG_PORT_SEL_PTCL_C0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("PTCL_C0 dbg port dump %d\n", ret);
ret = dbg_port_dump(adapter, MAC_AX_DBG_PORT_SEL_SCH_C0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("SCH_C0 dbg port dump %d\n", ret);
PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY0=0x%x\n",
MAC_REG_R32(R_AX_DLE_EMPTY0));
PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY1=0x%x\n",
MAC_REG_R32(R_AX_DLE_EMPTY1));
for (i = 0; i < TRX_CNT_REPT_CNT; i++) {
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTF=0x%x\n",
MAC_REG_R32(R_AX_PCIE_MIO_INTF));
PLTFM_MSG_ALWAYS("R_AX_PCIE_MIO_INTD=0x%x\n",
MAC_REG_R32(R_AX_PCIE_MIO_INTD));
PLTFM_MSG_ALWAYS("R_AX_PCIE_INIT_CFG1=0x%x\n",
MAC_REG_R32(R_AX_PCIE_INIT_CFG1));
PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_STOP1=0x%x\n",
MAC_REG_R32(R_AX_PCIE_DMA_STOP1));
PLTFM_MSG_ALWAYS("R_AX_PCIE_DMA_BUSY1=0x%x\n",
MAC_REG_R32(R_AX_PCIE_DMA_BUSY1));
PLTFM_MSG_ALWAYS("R_AX_PCIE_DBG_CTRL=0x%x\n",
MAC_REG_R32(R_AX_PCIE_DBG_CTRL));
PLTFM_MSG_ALWAYS("R_AX_DBG_ERR_FLAG=0x%x\n",
MAC_REG_R32(R_AX_DBG_ERR_FLAG));
PLTFM_MSG_ALWAYS("R_AX_LBC_WATCHDOG=0x%x\n",
MAC_REG_R32(R_AX_LBC_WATCHDOG));
PLTFM_MSG_ALWAYS("R_AX_ACH0_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH0_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH1_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH1_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH2_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH2_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH3_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH3_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH4_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH4_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH5_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH5_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH6_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH6_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_ACH7_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_ACH7_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_CH8_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_CH8_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_CH9_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_CH9_TXBD_IDX));
PLTFM_MSG_ALWAYS("R_AX_CH12_TXBD_IDX=0x%x\n",
MAC_REG_R32(R_AX_CH12_TXBD_IDX));
}
/* TMAC TX COUNTER */
ret = tx_cnt_dump(adapter, MAC_AX_BAND_0, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ALWAYS("[ERR]tx cnt dump err %d\n", ret);
pltfm_dbg_dump(adapter);
PLTFM_DELAY_US(TRX_CNT_REPT_DLY_US);
}
return MACSUCCESS;
}
u8 is_dbg_port_not_valid(struct mac_ax_adapter *adapter, u32 dbg_sel)
{
if (adapter->hw_info->intf != MAC_AX_INTF_PCIE &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_PCIE_TXDMA &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_PCIE_EMAC18)
return 1;
if (adapter->hw_info->intf != MAC_AX_INTF_USB &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_USB2_PHY &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_USB2_BT)
return 1;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_PTCL_C1 &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1)
return 1;
if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_PKTINFO &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_PKTINFO)
return 1;
if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_WDRLS &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_WDRLS)
return 1;
if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0 &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4)
return 1;
if (check_mac_en(adapter, 0, MAC_AX_DMAC_SEL) != MACSUCCESS &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0 &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL)
return 1;
if (check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL) != MACSUCCESS &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0)
return 1;
if (check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL) != MACSUCCESS &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_PTCL_C1 &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1)
return 1;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY &&
dbg_sel >= MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL &&
dbg_sel <= MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL) {
return 1;
}
return 0;
}
static u32 tx_flow_ptcl_dbg_port(struct mac_ax_adapter *adapter, u8 band)
{
u16 i, val16;
u32 ret = MACSUCCESS;
struct mac_ax_dbg_port_info info;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ALWAYS("[ERR] check cmac en %d\n", ret);
return ret;
}
info = band == MAC_AX_BAND_1 ? dbg_port_ptcl_c1 : dbg_port_ptcl_c0;
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock);
adapter->hw_info->dbg_port_cnt++;
if (adapter->hw_info->dbg_port_cnt != 1) {
PLTFM_MSG_ERR("[ERR]dbg port sel %x lock cnt %d\n",
info.sel_addr, adapter->hw_info->dbg_port_cnt);
ret = MACCMP;
goto err;
}
val16 = MAC_REG_R16(info.sel_addr);
val16 |= B_AX_PTCL_DBG_EN;
MAC_REG_W16(info.sel_addr, val16);
PLTFM_MSG_ALWAYS("Sel addr = 0x%X\n", info.sel_addr);
PLTFM_MSG_ALWAYS("Read addr = 0x%X\n", info.rd_addr);
info.srt = PTCL_SEL_PHY_DBG;
info.end = PTCL_SEL_PHY_DBG;
for (i = 0; i < PTCL_DBG_DMP_CNT; i++)
print_dbg_port(adapter, &info);
err:
adapter->hw_info->dbg_port_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock);
return ret;
}
static u32 tx_flow_sch_dbg_port(struct mac_ax_adapter *adapter, u8 band)
{
u8 i;
u32 val32, ret = MACSUCCESS;
struct mac_ax_dbg_port_info info;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ALWAYS("[ERR] check cmac en %d\n", ret);
return ret;
}
info = band == MAC_AX_BAND_1 ? dbg_port_sch_c1 : dbg_port_sch_c0;
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock);
adapter->hw_info->dbg_port_cnt++;
if (adapter->hw_info->dbg_port_cnt != 1) {
PLTFM_MSG_ERR("[ERR]dbg port sel %x lock cnt %d\n",
info.sel_addr, adapter->hw_info->dbg_port_cnt);
ret = MACCMP;
goto err;
}
val32 = MAC_REG_R32(info.sel_addr);
val32 |= B_AX_SCH_DBG_EN;
MAC_REG_W32(info.sel_addr, val32);
info.srt = SCH_SEL_EDCA_DBG;
info.end = SCH_SEL_EDCA_DBG;
PLTFM_MSG_ALWAYS("Sel addr = 0x%X\n", info.sel_addr);
PLTFM_MSG_ALWAYS("Read addr = 0x%X\n", info.rd_addr);
for (i = 0; i <= SCH_DBG_DMP_CNT; i++)
print_dbg_port(adapter, &info);
err:
adapter->hw_info->dbg_port_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock);
return ret;
}
static u32 mac_tx_flow_dbg(struct mac_ax_adapter *adapter)
{
u32 ret;
ret = tx_flow_ptcl_dbg_port(adapter, MAC_AX_BAND_0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B0 ptcl dbg dump err %d\n", ret);
ret = tx_flow_ptcl_dbg_port(adapter, MAC_AX_BAND_1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B1 ptcl dbg dump err %d\n", ret);
ret = tx_flow_sch_dbg_port(adapter, MAC_AX_BAND_0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B0 sch dbg err %d\n", ret);
ret = tx_flow_sch_dbg_port(adapter, MAC_AX_BAND_1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B1 sch dbg dump err %d\n", ret);
return MACSUCCESS;
}
void mac_dbg_status_dump(struct mac_ax_adapter *adapter,
struct mac_ax_dbgpkg *val, struct mac_ax_dbgpkg_en *en)
{
u32 ret, i;
u32 ret_dmac = MACSUCCESS;
u8 cmac_allow;
adapter->sm.l2_st = MAC_AX_L2_DIS;
ret = crit_dbg_dump(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("crit dbg dump %d\n", ret);
return;
}
ret = fw_st_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("fw st dump %d\n", ret);
if (en->dmac_dbg) {
ret_dmac = dmac_dbg_dump(adapter);
if (ret_dmac != MACSUCCESS)
PLTFM_MSG_ERR("dmac dbg dump %d\n", ret_dmac);
}
cmac_allow = en->cmac_dbg && ret_dmac == MACSUCCESS ? 1 : 0;
if (cmac_allow) {
ret = cmac_dbg_dump(adapter, MAC_AX_BAND_0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("cmac%d dbg dump %d\n",
MAC_AX_BAND_0, ret);
ret = cmac_dbg_dump(adapter, MAC_AX_BAND_1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("cmac%d dbg dump %d\n",
MAC_AX_BAND_1, ret);
}
if (en->mac_dbg_port) {
for (i = MAC_AX_DBG_PORT_SEL_PTCL_C0;
i < MAC_AX_DBG_PORT_SEL_LAST; i++) {
if (is_dbg_port_not_valid(adapter, i))
continue;
ret = dbg_port_dump(adapter, i);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("dbg port %d dump %d\n", i, ret);
break;
}
}
}
if (cmac_allow) {
/* 2nd dump trx counter after dbg port dump */
ret = tx_cnt_dump(adapter, MAC_AX_BAND_0, TRX_CNT_REPT_CNT);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B0 tx cnt dump err %d\n", ret);
ret = rx_cnt_dump(adapter, MAC_AX_BAND_0, TRX_CNT_REPT_CNT);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B0 rx cnt dump err %d\n", ret);
ret = tx_cnt_dump(adapter, MAC_AX_BAND_1, TRX_CNT_REPT_CNT);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B1 tx cnt dump err %d\n", ret);
ret = rx_cnt_dump(adapter, MAC_AX_BAND_1, TRX_CNT_REPT_CNT);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("[ERR]B1 rx cnt dump err %d\n", ret);
}
if (en->dle_dbg && ret_dmac == MACSUCCESS) {
ret = dle_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("dle dbg dump %d\n", ret);
for (i = MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG;
i < MAC_AX_DLE_DFI_SEL_LAST; i++) {
if (!chk_dle_dfi_valid(adapter, i))
continue;
ret = dle_dfi_dump(adapter, i);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("dle dfi %d dump %d\n", i, ret);
break;
}
}
}
if (en->plersvd_dbg) {
ret = rsvd_ple_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("rsvd dle dump %d\n", ret);
}
if (en->ss_dbg && ret_dmac == MACSUCCESS) {
ret = ss_dbgpkg(adapter, val);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("ss dbgpkg %d\n", ret);
}
ret = dbgport_hw_dump(adapter, &en->dp_hw_en);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("dbgport hw dump %d\n", ret);
PLTFM_MSG_ALWAYS("access H2CREG before MAC init: %d\n",
adapter->stats.h2c_reg_uninit);
PLTFM_MSG_ALWAYS("access C2HREG before MAC init: %d\n",
adapter->stats.c2h_reg_uninit);
PLTFM_MSG_ALWAYS("access H2CPKT before MAC init: %d\n",
adapter->stats.h2c_pkt_uninit);
adapter->sm.l2_st = MAC_AX_L2_EN;
if (en->tx_flow_dbg) {
ret = mac_tx_flow_dbg(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("tx flow dbg %d\n", ret);
}
}
u32 mac_sram_dbg_write(struct mac_ax_adapter *adapter, u32 offset,
u32 val, enum mac_ax_sram_dbg_sel sel)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg_base;
switch (sel) {
case CPU_LOCAL_SEL:
reg_base = CPU_LOCAL_BASE_ADDR + offset;
break;
case AXIDMA_SEL:
reg_base = AXIDMA_BASE_ADDR + offset;
break;
case STA_SCHED_SEL:
reg_base = STA_SCHED_BASE_ADDR + offset;
break;
case RXPLD_FLTR_CAM_SEL:
reg_base = RXPLD_FLTR_CAM_BASE_ADDR + offset;
break;
case SEC_CAM_SEL:
reg_base = SEC_CAM_BASE_ADDR + offset;
break;
case WOW_CAM_SEL:
reg_base = WOW_CAM_BASE_ADDR + offset;
break;
case CMAC_TBL_SEL:
reg_base = CMAC_TBL_BASE_ADDR + offset;
break;
case ADDR_CAM_SEL:
reg_base = ADDR_CAM_BASE_ADDR + offset;
break;
case BSSID_CAM_SEL:
reg_base = BSSID_CAM_BASE_ADDR + offset;
break;
case BA_CAM_SEL:
reg_base = BA_CAM_BASE_ADDR + offset;
break;
case BCN_IE_CAM0_SEL:
reg_base = BCN_IE_CAM0_BASE_ADDR + offset;
break;
case SHARED_BUF_SEL:
reg_base = SHARED_BUF_BASE_ADDR + offset;
break;
case DMAC_TBL_SEL:
reg_base = DMAC_TBL_BASE_ADDR + offset;
break;
case SHCUT_MACHDR_SEL:
reg_base = SHCUT_MACHDR_BASE_ADDR + offset;
break;
case BCN_IE_CAM1_SEL:
reg_base = BCN_IE_CAM1_BASE_ADDR + offset;
break;
default:
PLTFM_MSG_ERR("[ERR] sel %d", sel);
return MACNOITEM;
}
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, reg_base);
MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY, val);
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access sel %d end\n", __func__, sel);
return MACSUCCESS;
}
u32 mac_sram_dbg_read(struct mac_ax_adapter *adapter, u32 offset,
enum mac_ax_sram_dbg_sel sel)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg_base, ret;
switch (sel) {
case CPU_LOCAL_SEL:
reg_base = CPU_LOCAL_BASE_ADDR + offset;
break;
case AXIDMA_SEL:
reg_base = AXIDMA_BASE_ADDR + offset;
break;
case STA_SCHED_SEL:
reg_base = STA_SCHED_BASE_ADDR + offset;
break;
case RXPLD_FLTR_CAM_SEL:
reg_base = RXPLD_FLTR_CAM_BASE_ADDR + offset;
break;
case SEC_CAM_SEL:
reg_base = SEC_CAM_BASE_ADDR + offset;
break;
case WOW_CAM_SEL:
reg_base = WOW_CAM_BASE_ADDR + offset;
break;
case CMAC_TBL_SEL:
reg_base = CMAC_TBL_BASE_ADDR + offset;
break;
case ADDR_CAM_SEL:
reg_base = ADDR_CAM_BASE_ADDR + offset;
break;
case BSSID_CAM_SEL:
reg_base = BSSID_CAM_BASE_ADDR + offset;
break;
case BA_CAM_SEL:
reg_base = BA_CAM_BASE_ADDR + offset;
break;
case BCN_IE_CAM0_SEL:
reg_base = BCN_IE_CAM0_BASE_ADDR + offset;
break;
case SHARED_BUF_SEL:
reg_base = SHARED_BUF_BASE_ADDR + offset;
break;
case DMAC_TBL_SEL:
reg_base = DMAC_TBL_BASE_ADDR + offset;
break;
case SHCUT_MACHDR_SEL:
reg_base = SHCUT_MACHDR_BASE_ADDR + offset;
break;
case BCN_IE_CAM1_SEL:
reg_base = BCN_IE_CAM1_BASE_ADDR + offset;
break;
default:
PLTFM_MSG_ERR("[ERR] sel %d", sel);
return MACNOITEM;
}
PLTFM_MSG_WARN("%s ind access sel %d start\n", __func__, sel);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, reg_base);
ret = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY);
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access sel %d end\n", __func__, sel);
return ret;
}
static u32 get_rx_idx(struct mac_ax_adapter *adapter,
struct mac_ax_rx_cnt *rxcnt, u8 *idx)
{
u8 rx_type[MAC_AX_RX_CNT_TYPE_NUM][MAC_AX_RX_PPDU_MAX] = {
MAC_AX_RXCRC_OK_IDX, MAC_AX_RXCRC_FAIL_IDX,
MAC_AX_RXFA_IDX, MAC_AX_RXPPDU_IDX};
u8 type = rxcnt->type;
switch (type) {
case MAC_AX_RX_CRC_OK:
case MAC_AX_RX_CRC_FAIL:
case MAC_AX_RX_FA:
case MAC_AX_RX_PPDU:
PLTFM_MEMCPY(idx, rx_type[type], MAC_AX_RX_PPDU_MAX);
break;
case MAC_AX_RX_IDX:
PLTFM_MEMSET(idx, MAC_AX_RX_CNT_IDX_MAX, MAC_AX_RX_PPDU_MAX);
idx[0] = rxcnt->idx;
break;
default:
PLTFM_MSG_ERR("Wrong RX cnt type\n");
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_rx_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_rx_cnt *rxcnt)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS;
u32 reg = rxcnt->band ? R_AX_RX_DBG_CNT_SEL_C1 : R_AX_RX_DBG_CNT_SEL;
u32 clk = rxcnt->band ? R_AX_RXGCK_CTRL_C1 : R_AX_RXGCK_CTRL;
u8 i;
u8 idx[MAC_AX_RX_PPDU_MAX] = {MAC_AX_RX_CNT_IDX_MAX};
u16 *buf = rxcnt->buf;
u8 val;
switch (rxcnt->op) {
case MAC_AX_RXCNT_R:
if (!buf) {
PLTFM_MSG_ERR("The rx cnt buffer is NULL\n");
return MACNPTR;
}
ret = get_rx_idx(adapter, rxcnt, idx);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("Get RX index fail\n");
return ret;
}
for (i = 0; i < MAC_AX_RX_PPDU_MAX; i++) {
if (idx[i] == MAC_AX_RX_CNT_IDX_MAX) {
buf[i] = 0;
continue;
}
MAC_REG_W8(reg, idx[i]);
buf[i] = MAC_REG_R16(reg + 2);
}
break;
case MAC_AX_RXCNT_RST_ALL:
val = MAC_REG_R8(clk);
MAC_REG_W8(clk, val | BIT(0));
MAC_REG_W8(reg + 1, BIT(0));
MAC_REG_W8(clk, val);
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_dump_fw_rsvd_ple(struct mac_ax_adapter *adapter, u8 **buf)
{
u32 ret = MACSUCCESS;
u32 addr;
*buf = NULL;
if (adapter->mac_pwr_info.pwr_seq_proc ||
adapter->sm.pwr != MAC_AX_PWR_ON ||
adapter->mac_pwr_info.pwr_in_lps ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS)
return MACPWRSTAT;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
addr = RSVD_PLE_OFST_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
addr = RSVD_PLE_OFST_8852B;
} else {
PLTFM_MSG_ERR("[ERR]unknown chip id\n");
return MACCHIPID;
}
*buf = (u8 *)PLTFM_MALLOC(FW_RSVD_PLE_SIZE);
if (!*buf)
return MACBUFALLOC;
ret = __dump_mac_mem(adapter, MAC_AX_MEM_SHARED_BUF, addr,
*buf, FW_RSVD_PLE_SIZE, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("Dump fw rsvd ple %d\n", ret);
PLTFM_FREE(buf, FW_RSVD_PLE_SIZE);
}
ret = fw_backtrace_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("fw backtrace dump %d\n", ret);
return ret;
}
void mac_dump_ple_dbg_page(struct mac_ax_adapter *adapter, u8 page_num)
{
u32 ret = MACSUCCESS;
u32 addr = 0;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
addr = RSVD_PLE_OFST_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
addr = RSVD_PLE_OFST_8852B;
} else {
PLTFM_MSG_ERR("unknown chip id\n");
return;
}
addr = addr + RSVD_PLE_OFST_DBG_START + (page_num * FW_RSVD_PLE_DBG_SIZE);
PLTFM_MSG_ERR("Dump fw ple dbg page %d:\n", page_num);
ret = __dump_mac_mem(adapter, MAC_AX_MEM_SHARED_BUF, addr,
NULL, FW_RSVD_PLE_DBG_SIZE, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("Dump fw ple dbg page fail: %d\n", ret);
return;
}
}
u32 mac_fw_dbg_dump(struct mac_ax_adapter *adapter, u8 **buf, struct mac_ax_fwdbg_en *en)
{
u32 ret = MACSUCCESS;
if (en->status_dbg)
fw_st_dbg_dump(adapter);
if (en->rsv_ple_dbg)
mac_dump_fw_rsvd_ple(adapter, buf);
if (en->ps_dbg)
ps_dbg_dump(adapter);
return ret;
}
u32 mac_event_notify(struct mac_ax_adapter *adapter, enum phl_msg_evt_id id,
u8 band)
{
u32 ret = MACSUCCESS, io_ret = MACSUCCESS;
struct mac_ax_dbgpkg dbg_val;
struct mac_ax_dbgpkg_en dbg_en;
struct mac_ax_io_stat pcie_io_stat;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
struct mac_ax_drv_stats *status = &adapter->drv_stats;
#endif
switch (id) {
case MSG_EVT_DBG_SIP_REG_DUMP:
ret = crit_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("crit dbg dump %d\n", ret);
ret = fw_st_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("fw st dump %d\n", ret);
ret = dmac_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("dmac dbg dump %d\n", ret);
ret = cmac_dbg_dump(adapter, MAC_AX_BAND_0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("cmac%d dbg dump %d\n",
MAC_AX_BAND_0, ret);
break;
case MSG_EVT_DBG_FULL_REG_DUMP:
ret = mac_reg_dump(adapter, MAC_AX_REG_MAC);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("fw st dump %d\n", ret);
break;
case MSG_EVT_DBG_L2_DIAGNOSE:
ret = mac_lps_pwr_state(adapter, MAC_AX_PWR_STATE_ACT_REQ,
MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("PWR_STATE_ACT_REQ fail\n");
PLTFM_MEMSET(&dbg_en, 0, sizeof(struct mac_ax_dbgpkg_en));
if (ret == MACSUCCESS) {
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
io_ret = ops->get_io_stat(adapter,
&pcie_io_stat);
if (io_ret == MACSUCCESS &&
pcie_io_stat.to_flag == 0) {
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.plersvd_dbg = 1;
}
} else {
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.plersvd_dbg = 1;
}
}
mac_dbg_status_dump(adapter, &dbg_val, &dbg_en);
break;
case MSG_EVT_DBG_RX_DUMP:
ret = crit_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("crit dbg dump %d\n", ret);
ret = dmac_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("dmac dbg dump %d\n", ret);
ret = cmac_dbg_dump(adapter, MAC_AX_BAND_0);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("cmac%d dbg dump %d\n",
MAC_AX_BAND_0, ret);
ret = dle_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("dle dbg dump %d\n", ret);
break;
case MSG_EVT_DBG_TX_DUMP:
ret = tx_dbg_dump(adapter);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("tx dbg dump %d\n", ret);
break;
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
case MSG_EVT_DATA_PATH_START:
status->rx_ok = 1;
break;
case MSG_EVT_DATA_PATH_STOP:
status->rx_ok = 0;
break;
case MSG_EVT_SURPRISE_REMOVE:
status->drv_rm = 1;
break;
#endif
default:
return MACNOITEM;
}
return ret;
}
u32 mac_fw_dbg_dle_cfg(struct mac_ax_adapter *adapter, bool lock)
{
u8 *buf;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_general_pkt *write_ptr;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_general_pkt_ids));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_general_pkt *)buf;
write_ptr->dword0 =
cpu_to_le32((lock ? FWCMD_H2C_FW_DBGREG_CFG_FW_DBG_LOCK : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_INFO,
FWCMD_H2C_FUNC_FW_DBGREG_CFG,
0, 0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_get_fw_status(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val8 = FWDL_INITIAL_STATE;
u32 i = 0, fw_pc = 0;
u32 val32, dbg_ctrl_bk, sys_status_bk;
val8 = GET_FIELD(MAC_REG_R8(R_AX_WCPU_FW_CTRL), B_AX_WCPU_FWDL_STS);
if (val8 == FWDL_WCPU_FW_INIT_RDY) {
/* Dump FW status */
val32 = Read_DBG_FS_REG();
if (val32 == FS_L2ERR_IN ||
val32 == FS_L2ERR_CPU_IN ||
val32 == FS_L2ERR_HCI_IN ||
val32 == FS_L2ERR_ELSE_IN) {
return MACFWRXI300;
} else if (val32 == FS_ASSERT_IN) {
return MACFWASSERT;
} else if (val32 == FS_EXCEP_IN) {
return MACFWEXCEP;
}
/* Dump FW program counter */
dbg_ctrl_bk = MAC_REG_R32(R_AX_DBG_CTRL);
sys_status_bk = MAC_REG_R32(R_AX_SYS_STATUS1);
MAC_REG_W32(R_AX_DBG_CTRL, DBG_SEL_FW_PROG_CNTR);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
for (i = 0; i < FW_PROG_CNTR_DMP_CNT; i++) {
val32 = MAC_REG_R32(R_AX_DBG_PORT_SEL);
PLTFM_MSG_ALWAYS("FW PC = 0x%x\n", val32);
if (fw_pc == val32)
return MACFWPCHANG;
fw_pc = val32;
PLTFM_DELAY_US(FW_PROG_CNTR_DMP_DLY_US);
}
MAC_REG_W32(R_AX_DBG_CTRL, dbg_ctrl_bk);
MAC_REG_W32(R_AX_SYS_STATUS1, sys_status_bk);
} else {
return MACNOFW;
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dbgpkg.c
|
C
|
agpl-3.0
| 161,483
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_DBGPKG_H_
#define _MAC_AX_DBGPKG_H_
#include "../mac_def.h"
#include "../mac_ax.h"
#include "fwcmd.h"
#include "trx_desc.h"
#include "trxcfg.h"
#include "dle.h"
#define FW_RSVD_PLE_SIZE 0x800
#define RSVD_PLE_OFST_8852A 0x6f800
#define RSVD_PLE_OFST_8852B 0x2f800
#define FW_RSVD_PLE_DBG_SIZE 0x100
#define RSVD_PLE_OFST_DBG_START 0x400
#define SHARE_BUFFER_SIZE_8852A 0x70000
#define SHARE_BUFFER_SIZE_8852B 0x30000
#define STA_SCHED_MEM_SIZE 0x1200
#define RXPLD_FLTR_CAM_MEM_SIZE 0x200
#define SECURITY_CAM_MEM_SIZE 0x800
#define WOW_CAM_MEM_SIZE 0x240
#define ADDR_CAM_MEM_SIZE 0x4000
#define TXD_FIFO_SIZE 0x200
#define DBG_PORT_DUMP_DLY_US 10
#define FW_BACKTRACE_MAX_SIZE 512 // 8 * 64(entry)
#define FW_BACKTRACE_KEY 0xBACEBACE
#define FW_BACKTRACE_SIZE_OFST 4
#define FW_BACKTRACE_KEY_OFST 8
#define B_AX_AXIDMA_INT_SEL_SH 22
#define B_AX_AXIDMA_INT_SEL_MSK 0x7
#define TMAC_TX_CNT_NUM 11
#define RMAC_RX_CNT_NUM 37
#define TRX_CNT_REPT_CNT 5
#define TRX_CNT_REPT_DLY_US 10
#define TRX_CNT_READ_DLY_US 1
#define PTCL_SEL_PHY_DBG 0x10
#define SCH_SEL_EDCA_DBG 0x04
#define PTCL_DBG_DMP_CNT 15
#define SCH_DBG_DMP_CNT 15
#define DBG_SEL_FW_PROG_CNTR 0xF200F2
#define FW_PROG_CNTR_DMP_CNT 15
#define FW_PROG_CNTR_DMP_DLY_US 10
/* Wait for BCN parser idle shall consider RX beacon max time */
#define BCN_PSR_WAIT_CNT 900
#define BCN_PSR_WAIT_US 10
/* REG dump*/
#define MAC_PAGE_SRT 0
#define MAC_PAGE_AON_END 0x4
#define MAC_PAGE_TOP_END 0xF
#define MAC_PAGE_HCI_SRT 0x10
#define MAC_PAGE_HCI_END 0x1F
#define MAC_PAGE_DMAC_SRT 0x80
#define MAC_PAGE_DMAC_END 0x9F
#define MAC_PAGE_CMAC0_SRT 0xC0
#define MAC_PAGE_CMAC0_END 0xDF
#define MAC_PAGE_CMAC1_SRT 0xE0
#define MAC_PAGE_END 0xFF
#define BB_PAGE_SRT 0x100
#define BB_PAGE_END 0x17F
#define IQK_PAGE_SRT 0x180
#define IQK_PAGE_END 0x1BF
#define RFC_PAGE_SRT 0x1C0
#define RFC_PAGE_END 0x1FF
/* STA scheduler */
#define SS_MACID_SH 8
#define SS_TX_LEN_MSK 0x1FFFFF
#define SS_CTRL1_R_TX_LEN 5
#define SS_CTRL1_R_NEXT_LINK 20
#define SS_LINK_SIZE 256
#define SS_WMM_NUM_8852A 4
#define SS_WMM_NUM_8852B 2
#define SS_UL_SUPPORT_8852A 1
#define SS_UL_SUPPORT_8852B 0
#define SS_FW_SUPPORT_8852A 1
#define SS_FW_SUPPORT_8852B 0
#define SS_POLL_UNEXPECTED 0xFFFFFFFF
/* MAC debug port */
#define CMAC_DMA_DBG_SEL_C0 0xA0
#define TMAC_DBG_SEL_C0 0xA5
#define RMAC_DBG_SEL_C0 0xA6
#define TRXPTCL_DBG_SEL_C0 0xA7
#define CMAC_DMA_DBG_SEL_C1 0xB0
#define TMAC_DBG_SEL_C1 0xB5
#define RMAC_DBG_SEL_C1 0xB6
#define TRXPTCL_DBG_SEL_C1 0xB7
#define PCIE_TXDMA_DBG_SEL 0x30
#define PCIE_RXDMA_DBG_SEL 0x31
#define PCIE_CVT_DBG_SEL 0x32
#define PCIE_EMAC04_DBG_SEL 0x33
#define PCIE_EMAC5_DBG_SEL 0x34
#define PCIE_EMAC6_DBG_SEL 0x35
#define PCIE_EMAC7_DBG_SEL 0x36
#define PCIE_PNP_IO_DBG_SEL 0x37
#define PCIE_EMAC814_DBG_SEL 0x38
#define PCIE_EMAC15_DBG_SEL 0x39
#define PCIE_EMAC16_DBG_SEL 0x3A
#define PCIE_EMAC17_DBG_SEL 0x3B
#define PCIE_EMAC18_DBG_SEL 0x3C
#define PCIE_IO_DBG_SEL 0x37
#define PCIE_MISC_DBG_SEL 0x38
#define PCIE_MISC2_DBG_SEL 0x00
#define USB2_PHY_DBG_SEL 0x50
#define USB2_SIE_DBG_SEL 0x51
#define USB2_UTMI_DBG_SEL 0x52
#define USB2_SIE_MMU_DBG_SEL 0x53
#define USB2_SIE_PCE_DBG_SEL 0x54
#define USB2_UTMI_IF_DBG_SEL 0x55
#define USB_WLTX_DBG_SEL 0x56
#define USB_WLRX_DBG_SEL 0x57
#define USB3_DBG_SEL 0x58
#define USB_SETUP_DBG_SEL 0x59
#define USB_WLTXDMA_DBG_SEL 0x5A
#define USB_WLRXDMA_DBG_SEL 0x5B
#define USB_AINST_DBG_SEL 0x5C
#define USB_MISC_DBG_SEL 0x5D
#define USB_BTTX_DBG_SEL 0x5E
#define USB2_BT_DBG_SEL 0x5F
#define DISPATCHER_DBG_SEL 0x80
#define MAC_DBG_SEL 1
#define RMAC_CMAC_DBG_SEL 1
/* TRXPTCL dbg port sel */
#define TRXPTRL_DBG_SEL_TMAC 0
#define TRXPTRL_DBG_SEL_RMAC 1
#define MAC_AX_RX_CNT_NUM 48
#define MAC_AX_RX_CNT_IDX_MAX MAC_AX_RX_CNT_NUM
#define MAC_AX_RX_CNT_TYPE_NUM 5
/* the order is CCK, OFDM, HT, VHTSU, VHTMU, HESU, HEMU, HETB */
#define MAC_AX_RXCRC_OK_IDX \
{3, 0, 6, 10, 14, 18, 22, 26}
#define MAC_AX_RXCRC_FAIL_IDX \
{4, 1, 7, 11, 15, 19, 23, 27}
#define MAC_AX_RXPPDU_IDX \
{MAC_AX_RX_CNT_IDX_MAX, MAC_AX_RX_CNT_IDX_MAX, 8, 16, 20, 24, 28}
#define MAC_AX_RXFA_IDX \
{5, 2, 9, 17, 21, 25, 29}
#define Read_DBG_FS_REG() GET_FIELD(MAC_REG_R32(R_AX_UDM0), B_AX_UDM0_FS_CODE)
/**
* @enum mac_ax_sram_dbg_sel
*
* @brief mac_ax_sram_dbg_sel
*
* @var mac_ax_sram_dbg_sel::CPU_LOCAL_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::AXIDMA_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::STA_SCHED_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::RXPLD_FLTR_CAM_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::SEC_CAM_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::WOW_CAM_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::CMAC_TBL_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::ADDR_CAM_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::BSSID_CAM_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::BA_CAM_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::BCN_IE_CAM0_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::SHARED_BUF_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::DMAC_TBL_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::SHCUT_MACHDR_SEL
* Please Place Description here.
* @var mac_ax_sram_dbg_sel::BCN_IE_CAM1_SEL
* Please Place Description here.
*/
enum mac_ax_sram_dbg_sel {
CPU_LOCAL_SEL,
AXIDMA_SEL,
STA_SCHED_SEL,
RXPLD_FLTR_CAM_SEL,
SEC_CAM_SEL,
WOW_CAM_SEL,
CMAC_TBL_SEL,
ADDR_CAM_SEL,
BSSID_CAM_SEL,
BA_CAM_SEL,
BCN_IE_CAM0_SEL,
SHARED_BUF_SEL,
DMAC_TBL_SEL,
SHCUT_MACHDR_SEL,
BCN_IE_CAM1_SEL,
};
/**
* @enum mac_ax_dle_dfi_sel
*
* @brief mac_ax_dle_dfi_sel
*
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY
* Please Place Description here.
*/
enum mac_ax_dle_dfi_sel {
MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_FREEPG = 0,
MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_QUOTA,
MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PAGELLT,
MAC_AX_DLE_DFI_SEL_WDE_BUFMGN_PKTINFO,
MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_PREPKT,
MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_NXTPKT,
MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QLNKTBL,
MAC_AX_DLE_DFI_SEL_WDE_QUEMGN_QEMPTY,
MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_FREEPG,
MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_QUOTA,
MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PAGELLT,
MAC_AX_DLE_DFI_SEL_PLE_BUFMGN_PKTINFO,
MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_PREPKT,
MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_NXTPKT,
MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QLNKTBL,
MAC_AX_DLE_DFI_SEL_PLE_QUEMGN_QEMPTY,
/* keep last */
MAC_AX_DLE_DFI_SEL_LAST,
MAC_AX_DLE_DFI_SEL_MAX = MAC_AX_DLE_DFI_SEL_LAST,
MAC_AX_DLE_DFI_SEL_INVALID = MAC_AX_DLE_DFI_SEL_LAST,
};
/**
* @struct mac_ax_dle_dfi_info
* @brief mac_ax_dle_dfi_info
*
* @var mac_ax_dle_dfi_info::srt
* Please Place Description here.
* @var mac_ax_dle_dfi_info::end
* Please Place Description here.
* @var mac_ax_dle_dfi_info::inc_num
* Please Place Description here.
*/
struct mac_ax_dle_dfi_info {
u32 srt;
u32 end;
u32 inc_num;
};
/**
* @enum mac_ax_dbg_port_sel
*
* @brief mac_ax_dbg_port_sel
*
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PTCL_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_SCH_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TMAC_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMACST_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TRXPTCL_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOL_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOH_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PTCL_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_SCH_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TMAC_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMACST_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TRXPTCL_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOL_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TX_INFOH_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PKTINFO
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_TXDMA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_RXDMA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_CVT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC04
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC5
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC6
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC7
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC814
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC15
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC16
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC17
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_PCIE_EMAC18
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_PHY
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_SIE
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_UTMI
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLTX
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLRX
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB3
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_SETUP
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_AINST
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_MISC
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB_BTTX
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_USB2_BT
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_LAST
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_MAX
* Please Place Description here.
* @var mac_ax_dbg_port_sel::MAC_AX_DBG_PORT_SEL_INVALID
* Please Place Description here.
*/
enum mac_ax_dbg_port_sel {
/* CMAC 0 related */
MAC_AX_DBG_PORT_SEL_PTCL_C0 = 0,
MAC_AX_DBG_PORT_SEL_SCH_C0,
MAC_AX_DBG_PORT_SEL_TMAC_C0,
MAC_AX_DBG_PORT_SEL_RMAC_C0,
MAC_AX_DBG_PORT_SEL_RMACST_C0,
MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C0,
MAC_AX_DBG_PORT_SEL_TRXPTCL_C0,
MAC_AX_DBG_PORT_SEL_TX_INFOL_C0,
MAC_AX_DBG_PORT_SEL_TX_INFOH_C0,
MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C0,
MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C0,
MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C0,
MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C0,
/* CMAC 1 related */
MAC_AX_DBG_PORT_SEL_PTCL_C1,
MAC_AX_DBG_PORT_SEL_SCH_C1,
MAC_AX_DBG_PORT_SEL_TMAC_C1,
MAC_AX_DBG_PORT_SEL_RMAC_C1,
MAC_AX_DBG_PORT_SEL_RMACST_C1,
MAC_AX_DBG_PORT_SEL_RMAC_PLCP_C1,
MAC_AX_DBG_PORT_SEL_TRXPTCL_C1,
MAC_AX_DBG_PORT_SEL_TX_INFOL_C1,
MAC_AX_DBG_PORT_SEL_TX_INFOH_C1,
MAC_AX_DBG_PORT_SEL_TXTF_INFOL_C1,
MAC_AX_DBG_PORT_SEL_TXTF_INFOH_C1,
MAC_AX_DBG_PORT_SEL_CMAC_DMA0_C1,
MAC_AX_DBG_PORT_SEL_CMAC_DMA1_C1,
/* DLE related */
MAC_AX_DBG_PORT_SEL_PKTINFO,
MAC_AX_DBG_PORT_SEL_WDRLS,
/* TXPKT_CTRL related */
MAC_AX_DBG_PORT_SEL_TXPKT_CTRL0,
MAC_AX_DBG_PORT_SEL_TXPKT_CTRL1,
MAC_AX_DBG_PORT_SEL_TXPKT_CTRL2,
MAC_AX_DBG_PORT_SEL_TXPKT_CTRL3,
MAC_AX_DBG_PORT_SEL_TXPKT_CTRL4,
/* PCIE related */
MAC_AX_DBG_PORT_SEL_PCIE_TXDMA,
MAC_AX_DBG_PORT_SEL_PCIE_RXDMA,
MAC_AX_DBG_PORT_SEL_PCIE_CVT,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC04,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC5,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC6,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC7,
MAC_AX_DBG_PORT_SEL_PCIE_PNP_IO,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC814,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC15,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC16,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC17,
MAC_AX_DBG_PORT_SEL_PCIE_EMAC18,
/* USB related */
MAC_AX_DBG_PORT_SEL_USB2_PHY,
MAC_AX_DBG_PORT_SEL_USB2_SIE,
MAC_AX_DBG_PORT_SEL_USB2_UTMI,
MAC_AX_DBG_PORT_SEL_USB2_SIE_MMU,
MAC_AX_DBG_PORT_SEL_USB2_SIE_PCE,
MAC_AX_DBG_PORT_SEL_USB2_UTMI_IF,
MAC_AX_DBG_PORT_SEL_USB_WLTX,
MAC_AX_DBG_PORT_SEL_USB_WLRX,
MAC_AX_DBG_PORT_SEL_USB3,
MAC_AX_DBG_PORT_SEL_USB_SETUP,
MAC_AX_DBG_PORT_SEL_USB_WLTX_DMA,
MAC_AX_DBG_PORT_SEL_USB_WLRX_DMA,
MAC_AX_DBG_PORT_SEL_USB_AINST,
MAC_AX_DBG_PORT_SEL_USB_MISC,
MAC_AX_DBG_PORT_SEL_USB_BTTX,
MAC_AX_DBG_PORT_SEL_USB2_BT,
/* DISPATCHER related */
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX0,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX1,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX2,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX3,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX4,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX5,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX6,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX7,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX8,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TX9,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXA,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXB,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXC,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_TXD,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX0,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX1,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX3,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX4,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX5,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX6,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX7,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX8,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_TX9,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX0,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX1,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX2,
MAC_AX_DBG_PORT_SEL_DSPT_HDT_RX3,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P0,
MAC_AX_DBG_PORT_SEL_DSPT_CDT_RX_P1,
MAC_AX_DBG_PORT_SEL_DSPT_STF_CTRL,
MAC_AX_DBG_PORT_SEL_DSPT_ADDR_CTRL,
MAC_AX_DBG_PORT_SEL_DSPT_WDE_INTF,
MAC_AX_DBG_PORT_SEL_DSPT_PLE_INTF,
MAC_AX_DBG_PORT_SEL_DSPT_FLOW_CTRL,
/*AXIDMAC related*/
MAC_AX_DBG_PORT_SEL_AXI_TXDMA_CTRL,
MAC_AX_DBG_PORT_SEL_AXI_RXDMA_CTRL,
MAC_AX_DBG_PORT_SEL_AXI_MST_WLAN,
MAC_AX_DBG_PORT_SEL_AXI_INT_WLAN,
MAC_AX_DBG_PORT_SEL_AXI_PAGE_FLOW_CTRL,
/* keep last */
MAC_AX_DBG_PORT_SEL_LAST,
MAC_AX_DBG_PORT_SEL_MAX = MAC_AX_DBG_PORT_SEL_LAST,
MAC_AX_DBG_PORT_SEL_INVALID = MAC_AX_DBG_PORT_SEL_LAST,
};
struct ss_link_info {
u8 wmm;
u8 ac;
u8 ul;
};
/**
* @struct mac_ax_dbg_port_info
* @brief mac_ax_dbg_port_info
*
* @var mac_ax_dbg_port_info::sel_addr
* Please Place Description here.
* @var mac_ax_dbg_port_info::sel_byte
* Please Place Description here.
* @var mac_ax_dbg_port_info::sel_sh
* Please Place Description here.
* @var mac_ax_dbg_port_info::sel_msk
* Please Place Description here.
* @var mac_ax_dbg_port_info::srt
* Please Place Description here.
* @var mac_ax_dbg_port_info::end
* Please Place Description here.
* @var mac_ax_dbg_port_info::inc_num
* Please Place Description here.
* @var mac_ax_dbg_port_info::rd_addr
* Please Place Description here.
* @var mac_ax_dbg_port_info::rd_byte
* Please Place Description here.
* @var mac_ax_dbg_port_info::rd_sh
* Please Place Description here.
* @var mac_ax_dbg_port_info::rd_msk
* Please Place Description here.
*/
struct mac_ax_dbg_port_info {
u32 sel_addr;
u8 sel_byte;
u32 sel_sh;
u32 sel_msk;
u32 srt;
u32 end;
u32 inc_num;
u32 rd_addr;
u8 rd_byte;
u32 rd_sh;
u32 rd_msk;
};
/**
* @struct iecam_cfg_info
* @brief iecam_cfg_info
*
* @var iecam_cfg_info::camctrl_bkp
* Please Place Description here.
* @var iecam_cfg_info::ioctrl_bkp
* Please Place Description here.
* @var iecam_cfg_info::rbp_bkp
* Please Place Description here.
*/
struct iecam_cfg_info {
u16 camctrl_bkp;
u16 ioctrl_bkp;
u32 rbp_bkp;
};
struct fw_backtrace_info {
u32 ra;
u32 sp;
};
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_fwcmd_lb
*
* @param *adapter
* @param len
* @param burst
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fwcmd_lb(struct mac_ax_adapter *adapter, u32 len, u8 burst);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief c2h_sys_cmd_path
*
* @param *adapter
* @param *buf
* @param len
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 c2h_sys_cmd_path(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief c2h_sys_plat_autotest
*
* @param *adapter
* @param *buf
* @param len
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 c2h_sys_plat_autotest(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief iecam_aces_cfg
*
* @param *adapter
* @param band
* @param en
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 iecam_aces_cfg(struct mac_ax_adapter *adapter, u8 band, u8 en,
struct iecam_cfg_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_mem_dump
*
* @param *adapter
* @param sel
* @param strt_addr
* @param *buf
* @param len
* @param dbg_path
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mem_dump(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel,
u32 strt_addr, u8 *buf, u32 len, u32 dbg_path);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_get_mem_size
*
* @param *adapter
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_mem_size(struct mac_ax_adapter *adapter, enum mac_ax_mem_sel sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_reg_dump
*
* @param *adapter
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 mac_reg_dump(struct mac_ax_adapter *adapter, enum mac_ax_reg_sel sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief dle_dfi_sel
*
* @param *adapter
* @param **info
* @param *ctrl
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 dle_dfi_sel(struct mac_ax_adapter *adapter,
struct mac_ax_dle_dfi_info **info,
u32 *target, u32 sel);
/**
* @}
* @}
*/
/**
* @brief is_dbg_port_not_valid
*
* @param *adapter
* @param dbg_sel
* @return Please Place Description here.
* @retval u8
*/
u8 is_dbg_port_not_valid(struct mac_ax_adapter *adapter, u32 dbg_sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_dbg_status_dump
*
* @param *adapter
* @param *val
* @param *en
* @return Please Place Description here.
* @retval void
*/
void mac_dbg_status_dump(struct mac_ax_adapter *adapter,
struct mac_ax_dbgpkg *val,
struct mac_ax_dbgpkg_en *en);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief dbg_port_sel
*
* @param *adapter
* @param **info
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 dbg_port_sel(struct mac_ax_adapter *adapter,
struct mac_ax_dbg_port_info **info, u32 sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_sram_dbg_write
*
* @param *adapter
* @param offset
* @param val
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sram_dbg_write(struct mac_ax_adapter *adapter, u32 offset,
u32 val, enum mac_ax_sram_dbg_sel sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_sram_dbg_read
*
* @param *adapter
* @param offset
* @param sel
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sram_dbg_read(struct mac_ax_adapter *adapter, u32 offset,
enum mac_ax_sram_dbg_sel sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_rx_cnt
*
* @param *adapter
* @param *rxcnt
* @return Please Place Description here.
* @retval u32
*/
u32 mac_rx_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_rx_cnt *rxcnt);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_dump_fw_rsvd_ple
*
* @param *adapter
* @param **buf
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_fw_rsvd_ple(struct mac_ax_adapter *adapter, u8 **buf);
/**
* @}
* @}
*/
/**
* @brief mac_dump_ple_dbg_page
*
* @param *adapter
* @return Please Place Description here.
* @retval void
*/
void mac_dump_ple_dbg_page(struct mac_ax_adapter *adapter, u8 page_num);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_fw_dbg_dump
*
* @param *adapter
* @param **buf
* @param *en
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fw_dbg_dump(struct mac_ax_adapter *adapter,
u8 **buf,
struct mac_ax_fwdbg_en *en);
/**
* @}
* @}
*/
u32 fw_st_dbg_dump(struct mac_ax_adapter *adapter);
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_event_notify
* for Sta mode debug usage
* @param *adapter
* @param **buf
* @param *en
* @return Please Place Description here.
* @retval u32
*/
u32 mac_event_notify(struct mac_ax_adapter *adapter, enum phl_msg_evt_id id,
u8 band);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DebugPackage
* @{
*/
/**
* @brief mac_fwdbg_lock
* lock or unlock fwdbgreg
* @param *adapter
* @param lock
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fw_dbg_dle_cfg(struct mac_ax_adapter *adapter, bool lock);
/**
* @}
* @}
*/
/**
* @brief pltfm_dbg_dump
* dump cpu platform for dbg
* @param *adapter
*/
void pltfm_dbg_dump(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @brief mac_get_fw_status
* get fw status
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_fw_status(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dbgpkg.h
|
C
|
agpl-3.0
| 30,878
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "dbgpkg.h"
#include "dbgport_hw.h"
static u32 dp_intn_idx_set(struct mac_ax_adapter *adapter,
struct mac_ax_dbgport_hw *dp_hw, u8 sel_idx)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, intn_val;
u16 val16;
u8 dbg_sel, intn_idx;
dbg_sel = dp_hw->dbg_sel[sel_idx];
intn_idx = dp_hw->intn_idx[sel_idx];
switch (dbg_sel) {
case MAC_AX_DP_SEL_SYS_0:
case MAC_AX_DP_SEL_SYS_1F:
/* To do... */
break;
case MAC_AX_DP_SEL_PINMUX_0:
case MAC_AX_DP_SEL_PINMUX_7:
/* To do... */
break;
case MAC_AX_DP_SEL_LOADER_0:
case MAC_AX_DP_SEL_LOADER_3:
/* To do... */
break;
case MAC_AX_DP_SEL_HMUX_0:
case MAC_AX_DP_SEL_HMUX_3:
/* To do... */
break;
case MAC_AX_DP_SEL_PCIE_0:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PCIE_0_0:
case MAC_AX_DP_INTN_IDX_PCIE_0_1:
case MAC_AX_DP_INTN_IDX_PCIE_0_2:
case MAC_AX_DP_INTN_IDX_PCIE_0_3:
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL);
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_PCIE_1:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PCIE_1_0:
case MAC_AX_DP_INTN_IDX_PCIE_1_1:
case MAC_AX_DP_INTN_IDX_PCIE_1_2:
case MAC_AX_DP_INTN_IDX_PCIE_1_3:
case MAC_AX_DP_INTN_IDX_PCIE_1_4:
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL);
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_PCIE_2:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PCIE_2_0:
case MAC_AX_DP_INTN_IDX_PCIE_2_1:
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL);
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_PCIE_3:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PCIE_3_0:
case MAC_AX_DP_INTN_IDX_PCIE_3_1:
case MAC_AX_DP_INTN_IDX_PCIE_3_2:
case MAC_AX_DP_INTN_IDX_PCIE_3_3:
case MAC_AX_DP_INTN_IDX_PCIE_3_4:
case MAC_AX_DP_INTN_IDX_PCIE_3_5:
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL);
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_PCIE_4:
case MAC_AX_DP_SEL_PCIE_5:
case MAC_AX_DP_SEL_PCIE_6:
// don't have internal setting
break;
case MAC_AX_DP_SEL_PCIE_7:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PCIE_7_0:
intn_val = 0x0;
break;
case MAC_AX_DP_INTN_IDX_PCIE_7_1:
intn_val = 0x4;
break;
case MAC_AX_DP_INTN_IDX_PCIE_7_2:
intn_val = 0x1;
break;
case MAC_AX_DP_INTN_IDX_PCIE_7_3:
intn_val = 0x5;
break;
case MAC_AX_DP_INTN_IDX_PCIE_7_4:
intn_val = 0x2;
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_val, B_AX_DBG_SEL);
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_PCIE_8:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PCIE_8_0:
case MAC_AX_DP_INTN_IDX_PCIE_8_1:
case MAC_AX_DP_INTN_IDX_PCIE_8_2:
case MAC_AX_DP_INTN_IDX_PCIE_8_3:
case MAC_AX_DP_INTN_IDX_PCIE_8_4:
case MAC_AX_DP_INTN_IDX_PCIE_8_5:
case MAC_AX_DP_INTN_IDX_PCIE_8_6:
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL);
MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_PCIE_9:
case MAC_AX_DP_SEL_PCIE_A:
case MAC_AX_DP_SEL_PCIE_B:
case MAC_AX_DP_SEL_PCIE_C:
// don't have internal setting
break;
case MAC_AX_DP_SEL_PCIE_D:
case MAC_AX_DP_SEL_PCIE_E:
case MAC_AX_DP_SEL_PCIE_F:
// don't have this item
return MACNOITEM;
case MAC_AX_DP_SEL_USB_0:
case MAC_AX_DP_SEL_USB_F:
/* To do... */
break;
case MAC_AX_DP_SEL_SDIO_0:
case MAC_AX_DP_SEL_SDIO_F:
/* To do... */
break;
case MAC_AX_DP_SEL_BT:
/* To do... */
break;
case MAC_AX_DP_SEL_AXIDMA:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_AXIDMA_0:
intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_1:
intn_val = (0x1 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_2:
intn_val = (0x2 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x2 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_3:
intn_val = (0x3 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x3 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_4:
intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_5:
intn_val = (0x1 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_6:
intn_val = (0x2 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x2 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_7:
intn_val = (0x3 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x3 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_8:
intn_val = (0x4 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x4 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_9:
intn_val = (0x5 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x5 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_A:
intn_val = (0x6 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x6 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x1 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_B:
intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x2 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_C:
intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x3 << AXIDMA_DBG_SEL_INTN2_SH);
break;
case MAC_AX_DP_INTN_IDX_AXIDMA_D:
intn_val = (0x0 << AXIDMA_DBG_SEL_INTN0_SH) |
(0x0 << AXIDMA_DBG_SEL_INTN1_SH) |
(0x4 << AXIDMA_DBG_SEL_INTN2_SH);
break;
default:
return MACNOITEM;
}
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, AXIDMA_BASE_ADDR);
val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL);
val32 = SET_CLR_WORD(val32, intn_val, B_PL_AXIDMA_DBG_SEL);
MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY + R_PL_AXIDMA_DBG_CTRL, val32);
break;
case MAC_AX_DP_SEL_WLPHYDBG_GPIO:
/* To do... */
break;
case MAC_AX_DP_SEL_BTCOEXIST:
/* To do... */
break;
case MAC_AX_DP_SEL_LTECOEX:
/* To do... */
break;
case MAC_AX_DP_SEL_WLPHYDBG:
/* To do... */
break;
case MAC_AX_DP_SEL_WLAN_MAC_REG:
/* To do... */
break;
case MAC_AX_DP_SEL_WLAN_MAC_PMC:
/* To do... */
break;
case MAC_AX_DP_SEL_CALIB_TOP:
/* To do... */
break;
case MAC_AX_DP_SEL_DISPATCHER_TOP:
/* To do... */
break;
case MAC_AX_DP_SEL_WDE_DLE:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_WDE_DLE_0:
intn_val = 0x0;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_1:
intn_val = 0x1;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_2:
intn_val = 0xE;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_3:
intn_val = 0x10;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_4:
intn_val = 0x11;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_5:
intn_val = 0x14;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_6:
intn_val = 0x1E;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_7:
intn_val = 0x80;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_8:
intn_val = 0x81;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_9:
intn_val = 0x82;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_A:
intn_val = 0x90;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_B:
intn_val = 0x91;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_C:
intn_val = 0x92;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_D:
intn_val = 0xB0;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_E:
intn_val = 0xB1;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_F:
intn_val = 0xB2;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_10:
intn_val = 0xC0;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_11:
intn_val = 0xC1;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_12:
intn_val = 0xC2;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_13:
intn_val = 0xE0;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_14:
intn_val = 0xE1;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_15:
intn_val = 0xE2;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_16:
intn_val = 0xF0;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_17:
intn_val = 0xF1;
break;
case MAC_AX_DP_INTN_IDX_WDE_DLE_18:
intn_val = 0xF2;
break;
default:
return MACNOITEM;
}
val16 = MAC_REG_R16(R_AX_WDE_DBG_CTL);
val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG0_SEL);
val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG1_SEL);
MAC_REG_W16(R_AX_WDE_DBG_CTL, val16);
break;
case MAC_AX_DP_SEL_PLE_DLE:
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_PLE_DLE_0:
intn_val = 0x0;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_1:
intn_val = 0x1;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_2:
intn_val = 0xE;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_3:
intn_val = 0x10;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_4:
intn_val = 0x11;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_5:
intn_val = 0x14;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_6:
intn_val = 0x1E;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_7:
intn_val = 0x80;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_8:
intn_val = 0x81;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_9:
intn_val = 0x82;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_A:
intn_val = 0x90;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_B:
intn_val = 0x91;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_C:
intn_val = 0x92;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_D:
intn_val = 0xA0;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_E:
intn_val = 0xA1;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_F:
intn_val = 0xA2;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_10:
intn_val = 0xB0;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_11:
intn_val = 0xB1;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_12:
intn_val = 0xB2;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_13:
intn_val = 0xC0;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_14:
intn_val = 0xC1;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_15:
intn_val = 0xC2;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_16:
intn_val = 0xD0;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_17:
intn_val = 0xD1;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_18:
intn_val = 0xD2;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_19:
intn_val = 0xE0;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_1A:
intn_val = 0xE1;
break;
case MAC_AX_DP_INTN_IDX_PLE_DLE_1B:
intn_val = 0xE2;
break;
default:
return MACNOITEM;
}
val16 = MAC_REG_R16(R_AX_PLE_DBG_CTL);
val16 = SET_CLR_WORD(val16, intn_val, B_AX_PLE_DBG0_SEL);
val16 = SET_CLR_WORD(val16, intn_val, B_AX_PLE_DBG1_SEL);
MAC_REG_W16(R_AX_PLE_DBG_CTL, val16);
break;
case MAC_AX_DP_SEL_WDRLS:
/* To do... */
break;
case MAC_AX_DP_SEL_DLE_CPUIO:
/* To do... */
break;
case MAC_AX_DP_SEL_BBRPT:
/* To do... */
break;
case MAC_AX_DP_SEL_TXPKTCTL:
/* To do... */
break;
case MAC_AX_DP_SEL_PKTBUFFER:
/* To do... */
break;
case MAC_AX_DP_SEL_DMAC_TABLE:
/* To do... */
break;
case MAC_AX_DP_SEL_STA_SCHEDULER:
val32 = MAC_REG_R32(R_AX_SS_DBG_0);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_LM_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_SA_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_PC_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_PARAM_STAT);
MAC_REG_W32(R_AX_SS_DBG_0, val32);
val32 = MAC_REG_R32(R_AX_SS_DBG_1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_LEN_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DLTX_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_ULRU_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_ADD_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DEL_STAT);
MAC_REG_W32(R_AX_SS_DBG_1, val32);
val32 = MAC_REG_R32(R_AX_SS_DBG_2);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_FWTX_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_RPTA_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_WDEA_STAT);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_PLEA_STAT);
MAC_REG_W32(R_AX_SS_DBG_2, val32);
val32 = MAC_REG_R32(R_AX_SS_MU_CTRL);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DLMU_STATE);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SS_DLRU_STATE);
MAC_REG_W32(R_AX_SS_MU_CTRL, val32);
switch (intn_idx) {
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_0:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_1:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_2:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_3:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_4:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_5:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_6:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_7:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_8:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_9:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_A:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_B:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_C:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_D:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_E:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_F:
case MAC_AX_DP_INTN_IDX_STA_SCHEDULER_10:
break;
default:
return MACNOITEM;
}
val32 = MAC_REG_R32(R_AX_SS_DBG_3);
val32 = SET_CLR_WORD(val32, intn_idx, B_AX_SS_TOP_DBG_SEL);
MAC_REG_W32(R_AX_SS_DBG_3, val32);
break;
case MAC_AX_DP_SEL_DMAC_PKTIN:
/* To do... */
break;
case MAC_AX_DP_SEL_WSEC_TOP:
/* To do... */
break;
case MAC_AX_DP_SEL_MPDU_PROCESSOR:
/* To do... */
break;
case MAC_AX_DP_SEL_DMAC_APB_BRIDGE:
/* To do... */
break;
case MAC_AX_DP_SEL_LTR_CTRL:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_CMAC_DMAC_TOP:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_PTCLTOP:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_SCHEDULERTOP:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_TXPWR_CTRL:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_CMAC_APB_BRIDGE:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_MACTX:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_MACRX:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC0_WMAC_TRXPTCL:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_CMAC_DMAC_TOP:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_PTCLTOP:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_SCHEDULERTOP:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_TXPWR_CTRL:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_CMAC_APB_BRIDGE:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_MACTX:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_MACRX:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC1_WMAC_TRXPTCL:
/* To do... */
break;
case MAC_AX_DP_SEL_CMAC_SHARE:
/* To do... */
break;
/* WLAN_MAC */
case MAC_AX_DP_SEL_WL_CPU_0:
case MAC_AX_DP_SEL_WL_CPU_F:
/* To do... */
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
static u32 dp_intn_dump(struct mac_ax_adapter *adapter,
u8 dbg_sel, u8 intn_idx_max)
{
struct mac_ax_dbgport_hw dp_hw;
u32 ret = MACSUCCESS;
u8 intn_idx;
PLTFM_MEMSET(&dp_hw, 0, sizeof(struct mac_ax_dbgport_hw));
for (intn_idx = 0; intn_idx < intn_idx_max; intn_idx++) {
dp_hw.dbg_sel[0] = dbg_sel;
dp_hw.intn_idx[0] = intn_idx;
dp_hw.dbg_sel_16b[0] = MAC_AX_DP_SEL0_16B_0_15;
dp_hw.dbg_sel_4b[0] = MAC_AX_DP_SEL_4B_0_7;
dp_hw.dbg_sel[1] = dbg_sel;
dp_hw.intn_idx[1] = intn_idx;
dp_hw.dbg_sel_16b[1] = MAC_AX_DP_SEL1_16B_16_31;
dp_hw.dbg_sel_4b[1] = MAC_AX_DP_SEL_4B_0_7;
dp_hw.mode = MAC_AX_DP_MODE_DUMP;
PLTFM_MSG_ERR("Internal index(%d):", intn_idx);
ret = mac_dbgport_hw_set(adapter, &dp_hw);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
}
return ret;
}
u32 dbgport_hw_dump(struct mac_ax_adapter *adapter,
struct mac_ax_dbgport_hw_en *dp_hw_en)
{
u32 ret;
u8 dbg_sel, intn_idx_max = MAC_AX_DP_INTN_IDX_NA_MAX;
/* PCIE */
if (dp_hw_en->pcie) {
for (dbg_sel = MAC_AX_DP_SEL_PCIE_0;
dbg_sel <= MAC_AX_DP_SEL_PCIE_C; dbg_sel++) {
switch (dbg_sel) {
case MAC_AX_DP_SEL_PCIE_0:
intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_0_MAX;
break;
case MAC_AX_DP_SEL_PCIE_1:
intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_1_MAX;
break;
case MAC_AX_DP_SEL_PCIE_2:
intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_2_MAX;
break;
case MAC_AX_DP_SEL_PCIE_3:
intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_3_MAX;
break;
case MAC_AX_DP_SEL_PCIE_4:
case MAC_AX_DP_SEL_PCIE_5:
case MAC_AX_DP_SEL_PCIE_6:
intn_idx_max = MAC_AX_DP_INTN_IDX_NA_MAX;
break;
case MAC_AX_DP_SEL_PCIE_7:
intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_7_MAX;
break;
case MAC_AX_DP_SEL_PCIE_8:
intn_idx_max = MAC_AX_DP_INTN_IDX_PCIE_8_MAX;
break;
case MAC_AX_DP_SEL_PCIE_9:
case MAC_AX_DP_SEL_PCIE_A:
case MAC_AX_DP_SEL_PCIE_B:
case MAC_AX_DP_SEL_PCIE_C:
intn_idx_max = MAC_AX_DP_INTN_IDX_NA_MAX;
break;
}
PLTFM_MSG_ERR("Dbgport PCIE(0x%x):\n", dbg_sel);
ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
}
}
/* WLAN_MAC */
if (dp_hw_en->axidma) {
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
ret = MACFWNONRDY;
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
dbg_sel = MAC_AX_DP_SEL_AXIDMA;
intn_idx_max = MAC_AX_DP_INTN_IDX_AXIDMA_MAX;
PLTFM_MSG_TRACE("Dbgport axidma(0x%x):\n", dbg_sel);
ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
}
/* DMAC */
if (dp_hw_en->wde_dle) {
dbg_sel = MAC_AX_DP_SEL_WDE_DLE;
intn_idx_max = MAC_AX_DP_INTN_IDX_WDE_DLE_MAX;
PLTFM_MSG_TRACE("Dbgport wde dle(0x%x):\n", dbg_sel);
ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
}
if (dp_hw_en->ple_dle) {
dbg_sel = MAC_AX_DP_SEL_PLE_DLE;
intn_idx_max = MAC_AX_DP_INTN_IDX_PLE_DLE_MAX;
PLTFM_MSG_TRACE("Dbgport ple dle(0x%x):\n", dbg_sel);
ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
}
if (dp_hw_en->sta_scheduler) {
dbg_sel = MAC_AX_DP_SEL_STA_SCHEDULER;
intn_idx_max = MAC_AX_DP_INTN_IDX_STA_SCHEDULER_MAX;
PLTFM_MSG_TRACE("Dbgport sta scheduler(0x%x):\n", dbg_sel);
ret = dp_intn_dump(adapter, dbg_sel, intn_idx_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
return ret;
}
}
return MACSUCCESS;
}
u32 mac_dbgport_hw_set(struct mac_ax_adapter *adapter,
struct mac_ax_dbgport_hw *dp_hw)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS, backup = 0, val32;
u8 dbg_sel, dbg_sel_16b, dbg_sel_4b, sel_idx;
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
if (dp_hw->mode == MAC_AX_DP_MODE_LA) {
/* For AL mode, set GPIO PINMUX */
val32 = 0xEEEEEEEE;
MAC_REG_W32(R_AX_GPIO0_7_FUNC_SEL, val32);
MAC_REG_W32(R_AX_GPIO8_15_FUNC_SEL, val32);
} else {
/* For dump mode, need backup R_AX_DBG_CTRL */
backup = MAC_REG_R32(R_AX_DBG_CTRL);
}
val32 = 0;
for (sel_idx = 0; sel_idx < MAC_AX_DP_SEL_NUM; sel_idx++) {
dbg_sel = dp_hw->dbg_sel[sel_idx];
dbg_sel_16b = dp_hw->dbg_sel_16b[sel_idx];
dbg_sel_4b = dp_hw->dbg_sel_4b[sel_idx];
/* dbg port select */
if (sel_idx == 0) {
val32 = SET_CLR_WORD(val32, dbg_sel, B_AX_DBG_SEL0);
val32 |= (dbg_sel_16b ? B_AX_DBG_SEL0_16BIT : 0);
val32 = SET_CLR_WORD(val32, dbg_sel_4b,
B_AX_DBG_SEL0_4BIT);
} else {
val32 = SET_CLR_WORD(val32, dbg_sel, B_AX_DBG_SEL1);
val32 |= (dbg_sel_16b ? B_AX_DBG_SEL1_16BIT : 0);
val32 = SET_CLR_WORD(val32, dbg_sel_4b,
B_AX_DBG_SEL1_4BIT);
}
/* internal index for each module */
ret = dp_intn_idx_set(adapter, dp_hw, sel_idx);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s, %d\n", __func__, ret);
goto DONE;
}
}
MAC_REG_W32(R_AX_DBG_CTRL, val32);
/* Enable */
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
/* dump info */
dp_hw->rsp_val = MAC_REG_R32(R_AX_DBG_PORT_SEL);
PLTFM_MSG_TRACE("0x%08X\n", dp_hw->rsp_val);
/* For dump mode, need restore R_AX_DBG_CTRL */
if (dp_hw->mode == MAC_AX_DP_MODE_DUMP)
MAC_REG_W32(R_AX_DBG_CTRL, backup);
DONE:
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dbgport_hw.c
|
C
|
agpl-3.0
| 21,802
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_DBGPORT_HW_H_
#define _MAC_AX_DBGPORT_HW_H_
#include "../mac_def.h"
#include "../mac_ax.h"
#define MAC_AX_DP_MODE_DUMP 0
#define MAC_AX_DP_MODE_LA 1
#define AXIDMA_DBG_SEL_INTN0_SH 0
#define AXIDMA_DBG_SEL_INTN1_SH 3
#define AXIDMA_DBG_SEL_INTN2_SH 6
/**
* @enum mac_ax_dbgport_sel
*
* @brief mac_ax_dbgport_sel
*
* @var mac_ax_dbgport_sel::MAC_AX_DP_SEL_SYS_0
* Please Place Description here.
* @var mac_ax_dbgport_sel::MAC_AX_DP_SEL_SYS_1F
* Please Place Description here.
* @var mac_ax_dbgport_sel::MAC_AX_DP_SEL_LAST
* Please Place Description here.
*/
enum mac_ax_dbgport_sel {
/* SYSTEM */
MAC_AX_DP_SEL_SYS_0 = 0x0, // 0x0 -0x1F
MAC_AX_DP_SEL_SYS_1F = 0x1F,
/* PINMUX */
MAC_AX_DP_SEL_PINMUX_0 = 0x20, // 0x20 - 0x27
MAC_AX_DP_SEL_PINMUX_7 = 0x27,
/* LOADER */
MAC_AX_DP_SEL_LOADER_0 = 0x28, //0x28-0x2B
MAC_AX_DP_SEL_LOADER_3 = 0x2B,
/* HMUX */
MAC_AX_DP_SEL_HMUX_0 = 0x2C, //0x2C-0x2F
MAC_AX_DP_SEL_HMUX_3 = 0x2F,
/* PCIE */
MAC_AX_DP_SEL_PCIE_0 = 0x30,
MAC_AX_DP_SEL_PCIE_1 = 0x31,
MAC_AX_DP_SEL_PCIE_2 = 0x32,
MAC_AX_DP_SEL_PCIE_3 = 0x33,
MAC_AX_DP_SEL_PCIE_4 = 0x34,
MAC_AX_DP_SEL_PCIE_5 = 0x35,
MAC_AX_DP_SEL_PCIE_6 = 0x36,
MAC_AX_DP_SEL_PCIE_7 = 0x37,
MAC_AX_DP_SEL_PCIE_8 = 0x38,
MAC_AX_DP_SEL_PCIE_9 = 0x39,
MAC_AX_DP_SEL_PCIE_A = 0x3A,
MAC_AX_DP_SEL_PCIE_B = 0x3B,
MAC_AX_DP_SEL_PCIE_C = 0x3C,
MAC_AX_DP_SEL_PCIE_D = 0x3D,
MAC_AX_DP_SEL_PCIE_E = 0x3E,
MAC_AX_DP_SEL_PCIE_F = 0x3F,
/* USB */
MAC_AX_DP_SEL_USB_0 = 0x40, //0x40-0x4F
MAC_AX_DP_SEL_USB_F = 0x4F,
/* SDIO */
MAC_AX_DP_SEL_SDIO_0 = 0x50, //0x50-0x5F
MAC_AX_DP_SEL_SDIO_F = 0x5F,
/* BT */
MAC_AX_DP_SEL_BT = 0x60,
/* WLAN_MAC */
MAC_AX_DP_SEL_AXIDMA = 0x71,
MAC_AX_DP_SEL_WLPHYDBG_GPIO = 0x72,
MAC_AX_DP_SEL_BTCOEXIST = 0x74,
MAC_AX_DP_SEL_LTECOEX = 0x75,
MAC_AX_DP_SEL_WLPHYDBG = 0x76,
MAC_AX_DP_SEL_WLAN_MAC_REG = 0x77,
MAC_AX_DP_SEL_WLAN_MAC_PMC = 0x78,
MAC_AX_DP_SEL_CALIB_TOP = 0x79,
/* MAC */
// DMAC
MAC_AX_DP_SEL_DISPATCHER_TOP = 0x80,
MAC_AX_DP_SEL_WDE_DLE = 0x81,
MAC_AX_DP_SEL_PLE_DLE = 0x82,
MAC_AX_DP_SEL_WDRLS = 0x83,
MAC_AX_DP_SEL_DLE_CPUIO = 0x84,
MAC_AX_DP_SEL_BBRPT = 0x85,
MAC_AX_DP_SEL_TXPKTCTL = 0x86,
MAC_AX_DP_SEL_PKTBUFFER = 0x87,
MAC_AX_DP_SEL_DMAC_TABLE = 0x88,
MAC_AX_DP_SEL_STA_SCHEDULER = 0x89,
MAC_AX_DP_SEL_DMAC_PKTIN = 0x8A,
MAC_AX_DP_SEL_WSEC_TOP = 0x8B,
MAC_AX_DP_SEL_MPDU_PROCESSOR = 0x8C,
MAC_AX_DP_SEL_DMAC_APB_BRIDGE = 0x8D,
MAC_AX_DP_SEL_LTR_CTRL = 0x8E,
// CMAC_0
MAC_AX_DP_SEL_CMAC0_CMAC_DMAC_TOP = 0xA0,
MAC_AX_DP_SEL_CMAC0_PTCLTOP = 0xA1,
MAC_AX_DP_SEL_CMAC0_SCHEDULERTOP = 0xA2,
MAC_AX_DP_SEL_CMAC0_TXPWR_CTRL = 0xA3,
MAC_AX_DP_SEL_CMAC0_CMAC_APB_BRIDGE = 0xA4,
MAC_AX_DP_SEL_CMAC0_MACTX = 0xA5,
MAC_AX_DP_SEL_CMAC0_MACRX = 0xA6,
MAC_AX_DP_SEL_CMAC0_WMAC_TRXPTCL = 0xA7,
// CMAC_1
MAC_AX_DP_SEL_CMAC1_CMAC_DMAC_TOP = 0xB0,
MAC_AX_DP_SEL_CMAC1_PTCLTOP = 0xB1,
MAC_AX_DP_SEL_CMAC1_SCHEDULERTOP = 0xB2,
MAC_AX_DP_SEL_CMAC1_TXPWR_CTRL = 0xB3,
MAC_AX_DP_SEL_CMAC1_CMAC_APB_BRIDGE = 0xB4,
MAC_AX_DP_SEL_CMAC1_MACTX = 0xB5,
MAC_AX_DP_SEL_CMAC1_MACRX = 0xB6,
MAC_AX_DP_SEL_CMAC1_WMAC_TRXPTCL = 0xB7,
MAC_AX_DP_SEL_CMAC_SHARE = 0xC0,
/* WLAN_MAC */
MAC_AX_DP_SEL_WL_CPU_0 = 0xF0, //0xF0-0xFF
MAC_AX_DP_SEL_WL_CPU_F = 0xFF,
/* keep last */
MAC_AX_DP_SEL_LAST
};
/**
* @enum mac_ax_dbgport_sel0_16b
*
* @brief mac_ax_dbgport_sel0_16b
*
* @var mac_ax_dbgport_sel0_16b::MAC_AX_DP_SEL0_16B_0_15
* Please Place Description here.
* @var mac_ax_dbgport_sel0_16b::MAC_AX_DP_SEL0_16B_16_31
* Please Place Description here.
* @var mac_ax_dbgport_sel0_16b::MAC_AX_DP_SEL0_16B_END
* Please Place Description here.
*/
enum mac_ax_dbgport_sel0_16b {
MAC_AX_DP_SEL0_16B_0_15 = 0,
MAC_AX_DP_SEL0_16B_16_31 = 1,
MAC_AX_DP_SEL0_16B_END
};
/**
* @enum mac_ax_dbgport_sel1_16b
*
* @brief mac_ax_dbgport_sel1_16b
*
* @var mac_ax_dbgport_sel1_16b::MAC_AX_DP_SEL1_16B_16_31
* Please Place Description here.
* @var mac_ax_dbgport_sel1_16b::MAC_AX_DP_SEL1_16B_0_15
* Please Place Description here.
* @var mac_ax_dbgport_sel1_16b::MAC_AX_DP_SEL1_16B_END
* Please Place Description here.
*/
enum mac_ax_dbgport_sel1_16b {
MAC_AX_DP_SEL1_16B_16_31 = 0,
MAC_AX_DP_SEL1_16B_0_15 = 1,
MAC_AX_DP_SEL1_16B_END
};
/**
* @enum mac_ax_dbgport_sel_4b
*
* @brief mac_ax_dbgport_sel_4b
*
* @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_0_7
* Please Place Description here.
* @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_4_11
* Please Place Description here.
* @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_8_15
* Please Place Description here.
* @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_0_3_12_15
* Please Place Description here.
* @var mac_ax_dbgport_sel_4b::MAC_AX_DP_SEL_4B_END
* Please Place Description here.
*/
enum mac_ax_dbgport_sel_4b {
MAC_AX_DP_SEL_4B_0_7 = 0,
MAC_AX_DP_SEL_4B_4_11 = 1,
MAC_AX_DP_SEL_4B_8_15 = 2,
MAC_AX_DP_SEL_4B_0_3_12_15 = 3,
MAC_AX_DP_SEL_4B_END
};
/* For internal index */
/* COMMON */
enum mac_ax_dbgport_intn_idx_na {
MAC_AX_DP_INTN_IDX_NA = 0x0,
MAC_AX_DP_INTN_IDX_NA_MAX = 0x1,
};
/* SYSTEM */
// MAC_AX_DP_SEL_SYS_0 = 0x0, // 0x0 -0x1F
// MAC_AX_DP_SEL_SYS_1F = 0x1F,
/* PINMUX */
// MAC_AX_DP_SEL_PINMUX_0 = 0x20, // 0x20 - 0x27
// MAC_AX_DP_SEL_PINMUX_7 = 0x27,
/* LOADER */
// MAC_AX_DP_SEL_LOADER_0 = 0x28, //0x28-0x2B
// MAC_AX_DP_SEL_LOADER_3 = 0x2B,
/* HMUX */
// MAC_AX_DP_SEL_HMUX_0 = 0x2C, //0x2C-0x2F
// MAC_AX_DP_SEL_HMUX_3 = 0x2F,
/* PCIE */
// MAC_AX_DP_SEL_PCIE_0 = 0x30,
enum mac_ax_dbgport_intn_idx_pcie_0 {
MAC_AX_DP_INTN_IDX_PCIE_0_0 = 0x0,
MAC_AX_DP_INTN_IDX_PCIE_0_1 = 0x1,
MAC_AX_DP_INTN_IDX_PCIE_0_2 = 0x2,
MAC_AX_DP_INTN_IDX_PCIE_0_3 = 0x3,
MAC_AX_DP_INTN_IDX_PCIE_0_MAX = 0x4
};
// MAC_AX_DP_SEL_PCIE_1 = 0x31,
enum mac_ax_dbgport_intn_idx_pcie_1 {
MAC_AX_DP_INTN_IDX_PCIE_1_0 = 0x0,
MAC_AX_DP_INTN_IDX_PCIE_1_1 = 0x1,
MAC_AX_DP_INTN_IDX_PCIE_1_2 = 0x2,
MAC_AX_DP_INTN_IDX_PCIE_1_3 = 0x3,
MAC_AX_DP_INTN_IDX_PCIE_1_4 = 0x4,
MAC_AX_DP_INTN_IDX_PCIE_1_MAX = 0x5
};
// MAC_AX_DP_SEL_PCIE_2 = 0x32,
enum mac_ax_dbgport_intn_idx_pcie_2 {
MAC_AX_DP_INTN_IDX_PCIE_2_0 = 0x0,
MAC_AX_DP_INTN_IDX_PCIE_2_1 = 0x1,
MAC_AX_DP_INTN_IDX_PCIE_2_MAX = 0x2
};
// MAC_AX_DP_SEL_PCIE_3 = 0x33,
enum mac_ax_dbgport_intn_idx_pcie_3 {
MAC_AX_DP_INTN_IDX_PCIE_3_0 = 0x0,
MAC_AX_DP_INTN_IDX_PCIE_3_1 = 0x1,
MAC_AX_DP_INTN_IDX_PCIE_3_2 = 0x2,
MAC_AX_DP_INTN_IDX_PCIE_3_3 = 0x3,
MAC_AX_DP_INTN_IDX_PCIE_3_4 = 0x4,
MAC_AX_DP_INTN_IDX_PCIE_3_5 = 0x5,
MAC_AX_DP_INTN_IDX_PCIE_3_MAX = 0x6
};
// MAC_AX_DP_SEL_PCIE_4 = 0x34,
// MAC_AX_DP_SEL_PCIE_5 = 0x35,
// MAC_AX_DP_SEL_PCIE_6 = 0x36,
// MAC_AX_DP_SEL_PCIE_7 = 0x37,
enum mac_ax_dbgport_intn_idx_pcie_7 {
MAC_AX_DP_INTN_IDX_PCIE_7_0 = 0x0,
MAC_AX_DP_INTN_IDX_PCIE_7_1 = 0x1,
MAC_AX_DP_INTN_IDX_PCIE_7_2 = 0x2,
MAC_AX_DP_INTN_IDX_PCIE_7_3 = 0x3,
MAC_AX_DP_INTN_IDX_PCIE_7_4 = 0x4,
MAC_AX_DP_INTN_IDX_PCIE_7_MAX = 0x5
};
// MAC_AX_DP_SEL_PCIE_8 = 0x38,
enum mac_ax_dbgport_intn_idx_pcie_8 {
MAC_AX_DP_INTN_IDX_PCIE_8_0 = 0x0,
MAC_AX_DP_INTN_IDX_PCIE_8_1 = 0x1,
MAC_AX_DP_INTN_IDX_PCIE_8_2 = 0x2,
MAC_AX_DP_INTN_IDX_PCIE_8_3 = 0x3,
MAC_AX_DP_INTN_IDX_PCIE_8_4 = 0x4,
MAC_AX_DP_INTN_IDX_PCIE_8_5 = 0x5,
MAC_AX_DP_INTN_IDX_PCIE_8_6 = 0x6,
MAC_AX_DP_INTN_IDX_PCIE_8_MAX = 0x7
};
// MAC_AX_DP_SEL_PCIE_9 = 0x39,
// MAC_AX_DP_SEL_PCIE_A = 0x3A,
// MAC_AX_DP_SEL_PCIE_B = 0x3B,
// MAC_AX_DP_SEL_PCIE_C = 0x3C,
// MAC_AX_DP_SEL_PCIE_D = 0x3D,
// MAC_AX_DP_SEL_PCIE_E = 0x3E,
// MAC_AX_DP_SEL_PCIE_F = 0x3F,
/* USB */
// MAC_AX_DP_SEL_USB_0 = 0x40, //0x40-0x4F
// MAC_AX_DP_SEL_USB_F = 0x4F,
/* SDIO */
// MAC_AX_DP_SEL_SDIO_0 = 0x50, //0x50-0x5F
// MAC_AX_DP_SEL_SDIO_F = 0x5F,
/* BT */
// MAC_AX_DP_SEL_BT = 0x60,
/* WLAN_MAC */
// MAC_AX_DP_SEL_AXIDMA = 0x71,
enum mac_ax_dbgport_intn_idx_axidma {
MAC_AX_DP_INTN_IDX_AXIDMA_0 = 0x0,
MAC_AX_DP_INTN_IDX_AXIDMA_1 = 0x1,
MAC_AX_DP_INTN_IDX_AXIDMA_2 = 0x2,
MAC_AX_DP_INTN_IDX_AXIDMA_3 = 0x3,
MAC_AX_DP_INTN_IDX_AXIDMA_4 = 0x4,
MAC_AX_DP_INTN_IDX_AXIDMA_5 = 0x5,
MAC_AX_DP_INTN_IDX_AXIDMA_6 = 0x6,
MAC_AX_DP_INTN_IDX_AXIDMA_7 = 0x7,
MAC_AX_DP_INTN_IDX_AXIDMA_8 = 0x8,
MAC_AX_DP_INTN_IDX_AXIDMA_9 = 0x9,
MAC_AX_DP_INTN_IDX_AXIDMA_A = 0xA,
MAC_AX_DP_INTN_IDX_AXIDMA_B = 0xB,
MAC_AX_DP_INTN_IDX_AXIDMA_C = 0xC,
MAC_AX_DP_INTN_IDX_AXIDMA_D = 0xD,
MAC_AX_DP_INTN_IDX_AXIDMA_MAX = 0xE
};
// MAC_AX_DP_SEL_WLPHYDBG_GPIO = 0x72,
// MAC_AX_DP_SEL_BTCOEXIST = 0x74,
// MAC_AX_DP_SEL_LTECOEX = 0x75,
// MAC_AX_DP_SEL_WLPHYDBG = 0x76,
// MAC_AX_DP_SEL_WLAN_MAC_REG = 0x77,
// MAC_AX_DP_SEL_WLAN_MAC_PMC = 0x78,
// MAC_AX_DP_SEL_CALIB_TOP = 0x79,
/* MAC */
// DMAC
// MAC_AX_DP_SEL_DISPATCHER_TOP = 0x80,
// MAC_AX_DP_SEL_WDE_DLE = 0x81,
enum mac_ax_dbgport_intn_idx_wde_dle {
MAC_AX_DP_INTN_IDX_WDE_DLE_0 = 0x0,
MAC_AX_DP_INTN_IDX_WDE_DLE_1 = 0x1,
MAC_AX_DP_INTN_IDX_WDE_DLE_2 = 0x2,
MAC_AX_DP_INTN_IDX_WDE_DLE_3 = 0x3,
MAC_AX_DP_INTN_IDX_WDE_DLE_4 = 0x4,
MAC_AX_DP_INTN_IDX_WDE_DLE_5 = 0x5,
MAC_AX_DP_INTN_IDX_WDE_DLE_6 = 0x6,
MAC_AX_DP_INTN_IDX_WDE_DLE_7 = 0x7,
MAC_AX_DP_INTN_IDX_WDE_DLE_8 = 0x8,
MAC_AX_DP_INTN_IDX_WDE_DLE_9 = 0x9,
MAC_AX_DP_INTN_IDX_WDE_DLE_A = 0xA,
MAC_AX_DP_INTN_IDX_WDE_DLE_B = 0xB,
MAC_AX_DP_INTN_IDX_WDE_DLE_C = 0xC,
MAC_AX_DP_INTN_IDX_WDE_DLE_D = 0xD,
MAC_AX_DP_INTN_IDX_WDE_DLE_E = 0xE,
MAC_AX_DP_INTN_IDX_WDE_DLE_F = 0xF,
MAC_AX_DP_INTN_IDX_WDE_DLE_10 = 0x10,
MAC_AX_DP_INTN_IDX_WDE_DLE_11 = 0x11,
MAC_AX_DP_INTN_IDX_WDE_DLE_12 = 0x12,
MAC_AX_DP_INTN_IDX_WDE_DLE_13 = 0x13,
MAC_AX_DP_INTN_IDX_WDE_DLE_14 = 0x14,
MAC_AX_DP_INTN_IDX_WDE_DLE_15 = 0x15,
MAC_AX_DP_INTN_IDX_WDE_DLE_16 = 0x16,
MAC_AX_DP_INTN_IDX_WDE_DLE_17 = 0x17,
MAC_AX_DP_INTN_IDX_WDE_DLE_18 = 0x18,
MAC_AX_DP_INTN_IDX_WDE_DLE_MAX = 0x19
};
// MAC_AX_DP_SEL_PLE_DLE = 0x82,
enum mac_ax_dbgport_intn_idx_ple_dle {
MAC_AX_DP_INTN_IDX_PLE_DLE_0 = 0x0,
MAC_AX_DP_INTN_IDX_PLE_DLE_1 = 0x1,
MAC_AX_DP_INTN_IDX_PLE_DLE_2 = 0x2,
MAC_AX_DP_INTN_IDX_PLE_DLE_3 = 0x3,
MAC_AX_DP_INTN_IDX_PLE_DLE_4 = 0x4,
MAC_AX_DP_INTN_IDX_PLE_DLE_5 = 0x5,
MAC_AX_DP_INTN_IDX_PLE_DLE_6 = 0x6,
MAC_AX_DP_INTN_IDX_PLE_DLE_7 = 0x7,
MAC_AX_DP_INTN_IDX_PLE_DLE_8 = 0x8,
MAC_AX_DP_INTN_IDX_PLE_DLE_9 = 0x9,
MAC_AX_DP_INTN_IDX_PLE_DLE_A = 0xA,
MAC_AX_DP_INTN_IDX_PLE_DLE_B = 0xB,
MAC_AX_DP_INTN_IDX_PLE_DLE_C = 0xC,
MAC_AX_DP_INTN_IDX_PLE_DLE_D = 0xD,
MAC_AX_DP_INTN_IDX_PLE_DLE_E = 0xE,
MAC_AX_DP_INTN_IDX_PLE_DLE_F = 0xF,
MAC_AX_DP_INTN_IDX_PLE_DLE_10 = 0x10,
MAC_AX_DP_INTN_IDX_PLE_DLE_11 = 0x11,
MAC_AX_DP_INTN_IDX_PLE_DLE_12 = 0x12,
MAC_AX_DP_INTN_IDX_PLE_DLE_13 = 0x13,
MAC_AX_DP_INTN_IDX_PLE_DLE_14 = 0x14,
MAC_AX_DP_INTN_IDX_PLE_DLE_15 = 0x15,
MAC_AX_DP_INTN_IDX_PLE_DLE_16 = 0x16,
MAC_AX_DP_INTN_IDX_PLE_DLE_17 = 0x17,
MAC_AX_DP_INTN_IDX_PLE_DLE_18 = 0x18,
MAC_AX_DP_INTN_IDX_PLE_DLE_19 = 0x19,
MAC_AX_DP_INTN_IDX_PLE_DLE_1A = 0x1A,
MAC_AX_DP_INTN_IDX_PLE_DLE_1B = 0x1B,
MAC_AX_DP_INTN_IDX_PLE_DLE_MAX = 0x1C
};
// MAC_AX_DP_SEL_WDRLS = 0x83,
// MAC_AX_DP_SEL_DLE_CPUIO = 0x84,
// MAC_AX_DP_SEL_BBRPT = 0x85,
// MAC_AX_DP_SEL_TXPKTCTL = 0x86,
// MAC_AX_DP_SEL_PKTBUFFER = 0x87,
// MAC_AX_DP_SEL_DMAC_TABLE = 0x88,
// MAC_AX_DP_SEL_STA_SCHEDULER = 0x89,
enum mac_ax_dbgport_intn_idx_sta_scheduler {
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_0 = 0x0,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_1 = 0x1,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_2 = 0x2,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_3 = 0x3,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_4 = 0x4,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_5 = 0x5,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_6 = 0x6,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_7 = 0x7,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_8 = 0x8,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_9 = 0x9,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_A = 0xA,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_B = 0xB,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_C = 0xC,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_D = 0xD,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_E = 0xE,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_F = 0xF,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_10 = 0x10,
MAC_AX_DP_INTN_IDX_STA_SCHEDULER_MAX = 0x11
};
// MAC_AX_DP_SEL_DMAC_PKTIN = 0x8A,
// MAC_AX_DP_SEL_WSEC_TOP = 0x8B,
// MAC_AX_DP_SEL_MPDU_PROCESSOR = 0x8C,
// MAC_AX_DP_SEL_DMAC_APB_BRIDGE = 0x8D,
// MAC_AX_DP_SEL_LTR_CTRL = 0x8E,
// CMAC_0
// MAC_AX_DP_SEL_CMAC0_CMAC_DMAC_TOP = 0xA0,
// MAC_AX_DP_SEL_CMAC0_PTCLTOP = 0xA1,
// MAC_AX_DP_SEL_CMAC0_SCHEDULERTOP = 0xA2,
// MAC_AX_DP_SEL_CMAC0_TXPWR_CTRL = 0xA3,
// MAC_AX_DP_SEL_CMAC0_CMAC_APB_BRIDGE = 0xA4,
// MAC_AX_DP_SEL_CMAC0_MACTX = 0xA5,
// MAC_AX_DP_SEL_CMAC0_MACRX = 0xA6,
// MAC_AX_DP_SEL_CMAC0_WMAC_TRXPTCL = 0xA7,
// CMAC_1
// MAC_AX_DP_SEL_CMAC1_CMAC_DMAC_TOP = 0xB0,
// MAC_AX_DP_SEL_CMAC1_PTCLTOP = 0xB1,
// MAC_AX_DP_SEL_CMAC1_SCHEDULERTOP = 0xB2,
// MAC_AX_DP_SEL_CMAC1_TXPWR_CTRL = 0xB3,
// MAC_AX_DP_SEL_CMAC1_CMAC_APB_BRIDGE = 0xB4,
// MAC_AX_DP_SEL_CMAC1_MACTX = 0xB5,
// MAC_AX_DP_SEL_CMAC1_MACRX = 0xB6,
// MAC_AX_DP_SEL_CMAC1_WMAC_TRXPTCL = 0xB7,
// MAC_AX_DP_SEL_CMAC_SHARE = 0xC0,
/* WLAN_MAC */
// MAC_AX_DP_SEL_WL_CPU_0 = 0xF0, //0xF0-0xFF
// MAC_AX_DP_SEL_WL_CPU_F = 0xFF,
/**
* @brief mac_dbgport_hw_dump
*
* @param *adapter
* @param *dp_hw_en
* @return Please Place Description here.
* @retval u32
*/
u32 dbgport_hw_dump(struct mac_ax_adapter *adapter,
struct mac_ax_dbgport_hw_en *dp_hw_en);
/**
* @brief mac_dbgport_hw_set
*
* @param *adapter
* @param *dbgport_hw
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dbgport_hw_set(struct mac_ax_adapter *adapter,
struct mac_ax_dbgport_hw *dp_hw);
#endif
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2301_81045437/rtl8852be
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phl/hal_g6/mac/mac_ax/dbgport_hw.h
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C
|
agpl-3.0
| 14,103
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "dle.h"
/* PCIE 64 */
static struct dle_size_t wde_size0 = {
MAC_AX_WDE_PG_64, /* pge_size */
4095, /* lnk_pge_num */
1, /* unlnk_pge_num */
};
/* SDIO, PCIE STF, USB */
static struct dle_size_t wde_size1 = {
MAC_AX_WDE_PG_64, /* pge_size */
768, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* PCIE 128 */
static struct dle_size_t wde_size2 = {
MAC_AX_WDE_PG_128, /* pge_size */
2016, /* lnk_pge_num */
32, /* unlnk_pge_num */
};
/* PCIE SU TP */
static struct dle_size_t wde_size3 = {
MAC_AX_WDE_PG_64, /* pge_size */
496, /* lnk_pge_num */
3600, /* unlnk_pge_num */
};
/* DLFW */
static struct dle_size_t wde_size4 = {
MAC_AX_WDE_PG_64, /* pge_size */
0, /* lnk_pge_num */
4096, /* unlnk_pge_num */
};
/* PCIE BCN TEST */
static struct dle_size_t wde_size5 = {
MAC_AX_WDE_PG_64, /* pge_size */
3904, /* lnk_pge_num */
64, /* unlnk_pge_num */
};
/* PCIE 64 */
static struct dle_size_t wde_size6 = {
MAC_AX_WDE_PG_64, /* pge_size */
1024, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* PCIE 128 */
static struct dle_size_t wde_size7 = {
MAC_AX_WDE_PG_128, /* pge_size */
960, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* PCIE STF, USB */
static struct dle_size_t wde_size8 = {
MAC_AX_WDE_PG_64, /* pge_size */
256, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* DLFW */
static struct dle_size_t wde_size9 = {
MAC_AX_WDE_PG_64, /* pge_size */
0, /* lnk_pge_num */
1024, /* unlnk_pge_num */
};
/* LA-PCIE */
static struct dle_size_t wde_size10 = {
MAC_AX_WDE_PG_64, /* pge_size */
1408, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* LA-PCIE */
static struct dle_size_t wde_size11 = {
MAC_AX_WDE_PG_64, /* pge_size */
256, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* LA-SDIO */
static struct dle_size_t wde_size12 = {
MAC_AX_WDE_PG_64, /* pge_size */
328, /* lnk_pge_num */
56, /* unlnk_pge_num */
};
/* SDIO SCC */
static struct dle_size_t wde_size13 = {
MAC_AX_WDE_PG_64, /* pge_size */
128, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* SDIO LA */
static struct dle_size_t wde_size14 = {
MAC_AX_WDE_PG_64, /* pge_size */
124, /* lnk_pge_num */
4, /* unlnk_pge_num */
};
/* LA-USB 8852A*/
static struct dle_size_t wde_size15 = {
MAC_AX_WDE_PG_64, /* pge_size */
384, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* LA-USB 8852B*/
static struct dle_size_t wde_size16 = {
MAC_AX_WDE_PG_64, /* pge_size */
124, /* lnk_pge_num */
4, /* unlnk_pge_num */
};
/* 8852C USB */
static struct dle_size_t wde_size17 = {
MAC_AX_WDE_PG_64, /* pge_size */
332, /* lnk_pge_num */
52, /* unlnk_pge_num */
};
/* 8852C DLFW */
static struct dle_size_t wde_size18 = {
MAC_AX_WDE_PG_64, /* pge_size */
0, /* lnk_pge_num */
2048, /* unlnk_pge_num */
};
/* 8852C PCIE SCC */
static struct dle_size_t wde_size19 = {
MAC_AX_WDE_PG_64, /* pge_size */
3328, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* 8852C PCIE DBCC */
static struct dle_size_t wde_size20 = {
MAC_AX_WDE_PG_64, /* pge_size */
3328, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* 8852C PCIE SCC/DBCC STF */
static struct dle_size_t wde_size21 = {
MAC_AX_WDE_PG_64, /* pge_size */
256, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* 8852C PCIE LA */
static struct dle_size_t wde_size22 = {
MAC_AX_WDE_PG_64, /* pge_size */
3224, /* lnk_pge_num */
104, /* unlnk_pge_num */
};
/* 8852B PCIE STF AB */
static struct dle_size_t wde_size23 = {
MAC_AX_WDE_PG_64, /* pge_size */
216, /* lnk_pge_num */
40, /* unlnk_pge_num */
};
/* 8852B USB CABV*/
static struct dle_size_t wde_size24 = {
MAC_AX_WDE_PG_64, /* pge_size */
216, /* lnk_pge_num */
40, /* unlnk_pge_num */
};
/* 8852B USB2.0 */
static struct dle_size_t wde_size25 = {
MAC_AX_WDE_PG_64, /* pge_size */
242, /* lnk_pge_num */
14, /* unlnk_pge_num */
};
/* 8852AU ccv*/
static struct dle_size_t wde_size26 = {
MAC_AX_WDE_PG_64, /* pge_size */
760, /* lnk_pge_num */
8, /* unlnk_pge_num */
};
/* PCIE */
static struct dle_size_t ple_size0 = {
MAC_AX_PLE_PG_128, /* pge_size */
1520, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* SDIO, USB */
static struct dle_size_t ple_size1 = {
MAC_AX_PLE_PG_128, /* pge_size */
3184, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* PCIE STF */
static struct dle_size_t ple_size2 = {
MAC_AX_PLE_PG_128, /* pge_size */
3184, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* PCIE SU TP */
static struct dle_size_t ple_size3 = {
MAC_AX_PLE_PG_128, /* pge_size */
330, /* lnk_pge_num */
1206, /* unlnk_pge_num */
};
/* DLFW */
static struct dle_size_t ple_size4 = {
MAC_AX_PLE_PG_128, /* pge_size */
64, /* lnk_pge_num */
1472, /* unlnk_pge_num */
};
/* PCIE BCN TEST */
static struct dle_size_t ple_size5 = {
MAC_AX_PLE_PG_128, /* pge_size */
1520, /* lnk_pge_num */
80, /* unlnk_pge_num */
};
/* PCIE 64 */
static struct dle_size_t ple_size6 = {
MAC_AX_PLE_PG_128, /* pge_size */
1008, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* PCIE STF, USB */
static struct dle_size_t ple_size7 = {
MAC_AX_PLE_PG_128, /* pge_size */
1392, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* DLFW */
static struct dle_size_t ple_size8 = {
MAC_AX_PLE_PG_128, /* pge_size */
64, /* lnk_pge_num */
960, /* unlnk_pge_num */
};
/* PCIE 128 */
static struct dle_size_t ple_size9 = {
MAC_AX_PLE_PG_128, /* pge_size */
576, /* lnk_pge_num */
0, /* unlnk_pge_num */
};
/* LA-PCIE 8852A*/
static struct dle_size_t ple_size10 = {
MAC_AX_PLE_PG_128, /* pge_size */
816, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* LA-PCIE */
static struct dle_size_t ple_size11 = {
MAC_AX_PLE_PG_128, /* pge_size */
368, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* LA-SDIO 8852A*/
static struct dle_size_t ple_size12 = {
MAC_AX_PLE_PG_128, /* pge_size */
1328, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* SDIO SCC */
static struct dle_size_t ple_size13 = {
MAC_AX_PLE_PG_128, /* pge_size */
1456, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* SDIO LA */
static struct dle_size_t ple_size14 = {
MAC_AX_PLE_PG_128, /* pge_size */
432, /* lnk_pge_num */
528, /* unlnk_pge_num */
};
/* LA-USB 8852A */
static struct dle_size_t ple_size15 = {
MAC_AX_PLE_PG_128, /* pge_size */
1328, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* LA-USB 8852B */
static struct dle_size_t ple_size16 = {
MAC_AX_PLE_PG_128, /* pge_size */
432, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852C USB */
static struct dle_size_t ple_size17 = {
MAC_AX_PLE_PG_128, /* pge_size */
3336, /* lnk_pge_num */
56, /* unlnk_pge_num */
};
/* 8852C DLFW*/
static struct dle_size_t ple_size18 = {
MAC_AX_PLE_PG_128, /* pge_size */
2544, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852C PCIE SCC */
static struct dle_size_t ple_size19 = {
MAC_AX_PLE_PG_128, /* pge_size */
1904, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852C PCIE DBCC */
static struct dle_size_t ple_size20 = {
MAC_AX_PLE_PG_128, /* pge_size */
1904, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852C PCIE SCC/DBCC STF */
static struct dle_size_t ple_size21 = {
MAC_AX_PLE_PG_128, /* pge_size */
3440, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852C PCIE LA */
static struct dle_size_t ple_size22 = {
MAC_AX_PLE_PG_128, /* pge_size */
1904, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852B PCIE AB */
static struct dle_size_t ple_size23 = {
MAC_AX_PLE_PG_128, /* pge_size */
496, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852B PCIE STF AB */
static struct dle_size_t ple_size24 = {
MAC_AX_PLE_PG_128, /* pge_size */
880, /* lnk_pge_num */
16, /* unlnk_pge_num */
};
/* 8852B DLFW AB */
static struct dle_size_t ple_size25 = {
MAC_AX_PLE_PG_128, /* pge_size */
64, /* lnk_pge_num */
448, /* unlnk_pge_num */
};
/* 8852B USB CABV*/
static struct dle_size_t ple_size26 = {
MAC_AX_PLE_PG_128, /* pge_size */
872, /* lnk_pge_num */
24, /* unlnk_pge_num */
};
/* 8852B USB2.0 */
static struct dle_size_t ple_size27 = {
MAC_AX_PLE_PG_128, /* pge_size */
1402, /* lnk_pge_num */
6, /* unlnk_pge_num */
};
/* PCIE 64 */
static struct wde_quota_t wde_qt0 = {
3792, /* hif */
196, /* wcpu */
0, /* pkt_in */
107, /* cpu_io */
};
/* SDIO, PCIE STF, USB */
static struct wde_quota_t wde_qt1 = {
512, /* hif */
196, /* wcpu */
0, /* pkt_in */
60, /* cpu_io */
};
/* PCIE 128 */
static struct wde_quota_t wde_qt2 = {
1896, /* hif */
98, /* wcpu */
0, /* pkt_in */
22, /* cpu_io */
};
/* PCIE SU TP */
static struct wde_quota_t wde_qt3 = {
256, /* hif */
196, /* wcpu */
0, /* pkt_in */
44, /* cpu_io */
};
/* DLFW */
static struct wde_quota_t wde_qt4 = {
0, /* hif */
0, /* wcpu */
0, /* pkt_in */
0, /* cpu_io */
};
/* PCIE BCN TEST */
static struct wde_quota_t wde_qt5 = {
3666, /* hif */
196, /* wcpu */
0, /* pkt_in */
44, /* cpu_io */
};
/* PCIE 64 */
static struct wde_quota_t wde_qt6 = {
960, /* hif */
48, /* wcpu */
0, /* pkt_in */
16, /* cpu_io */
};
/* PCIE 128 */
static struct wde_quota_t wde_qt7 = {
896, /* hif */
56, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* PCIE STF, USB */
static struct wde_quota_t wde_qt8 = {
204, /* hif */
44, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* LA-PCIE 8852A*/
static struct wde_quota_t wde_qt9 = {
1172, /* hif */
196, /* wcpu */
0, /* pkt_in */
40, /* cpu_io */
};
/* LA-PCIE */
static struct wde_quota_t wde_qt10 = {
200, /* hif */
48, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* LA-SDIO 8852A*/
static struct wde_quota_t wde_qt11 = {
128, /* hif */
196, /* wcpu */
0, /* pkt_in */
4, /* cpu_io */
};
/* SDIO SCC */
static struct wde_quota_t wde_qt12 = {
112, /* hif */
8, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* SDIO LA */
static struct wde_quota_t wde_qt13 = {
112, /* hif */
4, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* LA USB 8852A */
static struct wde_quota_t wde_qt14 = {
256, /* hif */
118, /* wcpu */
0, /* pkt_in */
10, /* cpu_io */
};
/* LA USB 8852B */
static struct wde_quota_t wde_qt15 = {
112, /* hif */
4, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/*8852C USB */
static struct wde_quota_t wde_qt16 = {
292, /* hif */
20, /* wcpu */
0, /* pkt_in */
20, /* cpu_io */
};
/*8852C DLFW */
static struct wde_quota_t wde_qt17 = {
0, /* hif */
0, /* wcpu */
0, /* pkt_in */
0, /* cpu_io */
};
/* 8852C PCIE SCC */
static struct wde_quota_t wde_qt18 = {
3228, /* hif */
60, /* wcpu */
0, /* pkt_in */
40, /* cpu_io */
};
/* 8852C PCIE DBCC */
static struct wde_quota_t wde_qt19 = {
3218, /* hif */
60, /* wcpu */
0, /* pkt_in */
50, /* cpu_io */
};
/* 8852C PCIE SCC STF */
static struct wde_quota_t wde_qt20 = {
216, /* hif */
20, /* wcpu */
0, /* pkt_in */
20, /* cpu_io */
};
/* 8852C PCIE DBCC STF */
static struct wde_quota_t wde_qt21 = {
152, /* hif */
64, /* wcpu */
0, /* pkt_in */
40, /* cpu_io */
};
/* 8852C PCIE LA */
static struct wde_quota_t wde_qt22 = {
3120, /* hif */
64, /* wcpu */
0, /* pkt_in */
40, /* cpu_io */
};
/* 8852B PCIE STF AB */
static struct wde_quota_t wde_qt23 = {
164, /* hif */
44, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* 8852B USB CABV */
static struct wde_quota_t wde_qt24 = {
164, /* hif */
44, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* 8852B USB2.0 */
static struct wde_quota_t wde_qt25 = {
190, /* hif */
44, /* wcpu */
0, /* pkt_in */
8, /* cpu_io */
};
/* PCIE DBCC */
static struct ple_quota_t ple_qt0 = {
264, /* cmac0_tx */
66, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
356, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* 8852AU ccv */
static struct wde_quota_t wde_qt26 = {
504, /* hif */
196, /* wcpu */
0, /* pkt_in */
60, /* cpu_io */
};
/* PCIE DBCC */
static struct ple_quota_t ple_qt1 = {
264, /* cmac0_tx */
66, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
941, /* cmac0_dma */
679, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
240, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO */
static struct ple_quota_t ple_qt2 = {
1536, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
26, /* mpdu_proc */
360, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO */
static struct ple_quota_t ple_qt3 = {
1536, /* cmac0_tx */
0, /* cmac1_tx */
1149, /* c2h */
20, /* h2c */
64, /* wcpu */
1159, /* mpdu_proc */
1493, /* cmac0_dma */
0, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
120, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE SCC */
static struct ple_quota_t ple_qt4 = {
264, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
356, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE SCC */
static struct ple_quota_t ple_qt5 = {
264, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
1101, /* cmac0_dma */
0, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
120, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO */
static struct ple_quota_t ple_qt6 = {
2048, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
26, /* mpdu_proc */
360, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO */
static struct ple_quota_t ple_qt7 = {
2048, /* cmac0_tx */
0, /* cmac1_tx */
530, /* c2h */
20, /* h2c */
64, /* wcpu */
540, /* mpdu_proc */
874, /* cmac0_dma */
608, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
240, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE STF SCC */
static struct ple_quota_t ple_qt8 = {
1536, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
356, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE STF SCC */
static struct ple_quota_t ple_qt9 = {
2686, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
1506, /* cmac0_dma */
0, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
120, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE STF DBCC */
static struct ple_quota_t ple_qt10 = {
2272, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
356, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE STF DBCC */
static struct ple_quota_t ple_qt11 = {
2579, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
663, /* cmac0_dma */
401, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
240, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE SU TP */
static struct ple_quota_t ple_qt12 = {
66, /* cmac0_tx */
66, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
25, /* cmac0_dma */
25, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* DLFW */
static struct ple_quota_t ple_qt13 = {
0, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
0, /* wcpu */
0, /* mpdu_proc */
0, /* cmac0_dma */
0, /* cma1_dma */
0, /* bb_rpt */
0, /* wd_rel */
0, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE BCN TEST */
static struct ple_quota_t ple_qt14 = {
588, /* cmac0_tx */
147, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
26, /* mpdu_proc */
356, /* cmac0_dma */
89, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
80, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE BCN TEST */
static struct ple_quota_t ple_qt15 = {
688, /* cmac0_tx */
247, /* cmac1_tx */
116, /* c2h */
20, /* h2c */
64, /* wcpu */
126, /* mpdu_proc */
456, /* cmac0_dma */
189, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
80, /* cpu_io */
0, /* tx_rpt */
};
/* USB DBCC */
static struct ple_quota_t ple_qt16 = {
2048, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
360, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* USB DBCC */
static struct ple_quota_t ple_qt17 = {
2048, /* cmac0_tx */
0, /* cmac1_tx */
515, /* c2h */
48, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
859, /* cmac0_dma */
593, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
240, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE 64 */
static struct ple_quota_t ple_qt18 = {
147, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE 64 */
static struct ple_quota_t ple_qt19 = {
147, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
580, /* wcpu */
13, /* mpdu_proc */
745, /* cmac0_dma */
0, /* cma1_dma */
599, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE STF */
static struct ple_quota_t ple_qt20 = {
962, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
88, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE STF */
static struct ple_quota_t ple_qt21 = {
1023, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
149, /* wcpu */
13, /* mpdu_proc */
239, /* cmac0_dma */
0, /* cma1_dma */
93, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE 128 */
static struct ple_quota_t ple_qt22 = {
269, /* cmac0_tx */
0, /* cmac1_tx */
18, /* c2h */
20, /* h2c */
15, /* wcpu */
28, /* mpdu_proc */
180, /* cmac0_dma */
0, /* cma1_dma */
34, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* LA PCIE 8852A*/
static struct ple_quota_t ple_qt23 = {
104, /* cmac0_tx */
26, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
356, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* LA PCIE 8852A*/
static struct ple_quota_t ple_qt24 = {
104, /* cmac0_tx */
26, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
437, /* cmac0_dma */
175, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
89, /* cpu_io */
0, /* tx_rpt */
};
/* USB SCC */
static struct ple_quota_t ple_qt25 = {
1536, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
360, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* USB SCC */
static struct ple_quota_t ple_qt26 = {
2654, /* cmac0_tx */
0, /* cmac1_tx */
1134, /* c2h */
48, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
1478, /* cmac0_dma */
0, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
120, /* cpu_io */
0, /* tx_rpt */
};
/* USB3.0 52B */
static struct ple_quota_t ple_qt27 = {
962, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
88, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* USB3.0 52B */
static struct ple_quota_t ple_qt28 = {
962, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
48, /* h2c */
121, /* wcpu */
13, /* mpdu_proc */
211, /* cmac0_dma */
0, /* cma1_dma */
65, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE SU TP */
static struct ple_quota_t ple_qt29 = {
66, /* cmac0_tx */
66, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
1224, /* cmac0_dma */
1224, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
240, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE LA */
static struct ple_quota_t ple_qt30 = {
51, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* PCIE LA */
static struct ple_quota_t ple_qt31 = {
74, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
36, /* wcpu */
13, /* mpdu_proc */
201, /* cmac0_dma */
0, /* cma1_dma */
55, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* LA SDIO 8852A*/
static struct ple_quota_t ple_qt32 = {
500, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
26, /* wcpu */
26, /* mpdu_proc */
360, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* LA SDIO 8852A*/
static struct ple_quota_t ple_qt33 = {
500, /* cmac0_tx */
0, /* cmac1_tx */
222, /* c2h */
20, /* h2c */
64, /* wcpu */
232, /* mpdu_proc */
566, /* cmac0_dma */
300, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
214, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO SCC */
static struct ple_quota_t ple_qt34 = {
836, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
16, /* h2c */
26, /* wcpu */
0, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
16, /* bb_rpt */
1, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO SCC */
static struct ple_quota_t ple_qt35 = {
836, /* cmac0_tx */
0, /* cmac1_tx */
375, /* c2h */
16, /* h2c */
385, /* wcpu */
0, /* mpdu_proc */
537, /* cmac0_dma */
0, /* cma1_dma */
375, /* bb_rpt */
1, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO LA */
static struct ple_quota_t ple_qt36 = {
86, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
52, /* wcpu */
26, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* SDIO LA */
static struct ple_quota_t ple_qt37 = {
86, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
52, /* wcpu */
26, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* LA USB 8852A*/
static struct ple_quota_t ple_qt38 = {
512, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
60, /* h2c */
26, /* wcpu */
13, /* mpdu_proc */
360, /* cmac0_dma */
94, /* cma1_dma */
32, /* bb_rpt */
40, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* LA USB 8852A*/
static struct ple_quota_t ple_qt39 = {
512, /* cmac0_tx */
0, /* cmac1_tx */
184, /* c2h */
60, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
527, /* cmac0_dma */
261, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
175, /* cpu_io */
0, /* tx_rpt */
};
/* LA USB 8852B*/
static struct ple_quota_t ple_qt40 = {
26, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
52, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* LA USB 8852B*/
static struct ple_quota_t ple_qt41 = {
26, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
48, /* h2c */
97, /* wcpu */
13, /* mpdu_proc */
223, /* cmac0_dma */
0, /* cma1_dma */
77, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* USB 52C */
static struct ple_quota_t ple_qt42 = {
1196, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
130, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
20, /* wd_rel */
8, /* cpu_io */
16, /* tx_rpt */
};
/* USB 52C */
static struct ple_quota_t ple_qt43 = {
2938, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
1755, /* wcpu */
13, /* mpdu_proc */
1872, /* cmac0_dma */
0, /* cma1_dma */
1774, /* bb_rpt */
20, /* wd_rel */
120, /* cpu_io */
1758, /* tx_rpt */
};
/* DLFW 52C */
static struct ple_quota_t ple_qt44 = {
0, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
256, /* h2c */
0, /* wcpu */
0, /* mpdu_proc */
0, /* cmac0_dma */
0, /* cma1_dma */
0, /* bb_rpt */
0, /* wd_rel */
0, /* cpu_io */
0, /* tx_rpt */
};
/* DLFW 52C */
static struct ple_quota_t ple_qt45 = {
0, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
256, /* h2c */
0, /* wcpu */
0, /* mpdu_proc */
0, /* cmac0_dma */
0, /* cma1_dma */
0, /* bb_rpt */
0, /* wd_rel */
0, /* cpu_io */
0, /* tx_rpt */
};
/* 8852C PCIE SCC */
static struct ple_quota_t ple_qt46 = {
525, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
62, /* wd_rel */
8, /* cpu_io */
16, /* tx_rpt */
};
/* 8852C PCIE SCC */
static struct ple_quota_t ple_qt47 = {
525, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
1034, /* wcpu */
13, /* mpdu_proc */
1199, /* cmac0_dma */
0, /* cma1_dma */
1053, /* bb_rpt */
62, /* wd_rel */
160, /* cpu_io */
1037, /* tx_rpt */
};
/* 8852C PCIE DBCC */
static struct ple_quota_t ple_qt48 = {
525, /* cmac0_tx */
200, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
178, /* cma1_dma */
32, /* bb_rpt */
62, /* wd_rel */
8, /* cpu_io */
16, /* tx_rpt */
};
/* 8852C PCIE DBCC */
static struct ple_quota_t ple_qt49 = {
525, /* cmac0_tx */
200, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
656, /* wcpu */
13, /* mpdu_proc */
821, /* cmac0_dma */
821, /* cma1_dma */
675, /* bb_rpt */
62, /* wd_rel */
160, /* cpu_io */
659, /* tx_rpt */
};
/* 8852C PCIE SCC STF */
static struct ple_quota_t ple_qt50 = {
1248, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
130, /* cmac0_dma */
130, /* cma1_dma */
32, /* bb_rpt */
38, /* wd_rel */
8, /* cpu_io */
16, /* tx_rpt */
};
/* 8852C PCIE SCC STF */
static struct ple_quota_t ple_qt51 = {
3024, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
1789, /* wcpu */
13, /* mpdu_proc */
1906, /* cmac0_dma */
1906, /* cma1_dma */
1808, /* bb_rpt */
38, /* wd_rel */
40, /* cpu_io */
1792, /* tx_rpt */
};
/* 8852C PCIE DBCC STF */
static struct ple_quota_t ple_qt52 = {
1664, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
130, /* cmac0_dma */
130, /* cma1_dma */
32, /* bb_rpt */
38, /* wd_rel */
8, /* cpu_io */
16, /* tx_rpt */
};
/* 8852C PCIE DBCC STF */
static struct ple_quota_t ple_qt53 = {
3024, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
1373, /* wcpu */
13, /* mpdu_proc */
1490, /* cmac0_dma */
1490, /* cma1_dma */
1392, /* bb_rpt */
38, /* wd_rel */
160, /* cpu_io */
1376, /* tx_rpt */
};
/* 8852C PCIE LA */
static struct ple_quota_t ple_qt54 = {
300, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
13, /* wcpu */
13, /* mpdu_proc */
356, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
62, /* wd_rel */
8, /* cpu_io */
16, /* tx_rpt */
};
/* 8852C PCIE LA */
static struct ple_quota_t ple_qt55 = {
300, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
1081, /* wcpu */
13, /* mpdu_proc */
1424, /* cmac0_dma */
0, /* cma1_dma */
1100, /* bb_rpt */
62, /* wd_rel */
160, /* cpu_io */
1084, /* tx_rpt */
};
/* 8852B PCIE AB */
static struct ple_quota_t ple_qt56 = {
147, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
68, /* wcpu */
13, /* mpdu_proc */
233, /* cmac0_dma */
0, /* cma1_dma */
87, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* 8852B PCIE STF AB */
static struct ple_quota_t ple_qt57 = {
442, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
20, /* h2c */
88, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* 8852B PCIE STF AB*/
static struct ple_quota_t ple_qt58 = {
511, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
20, /* h2c */
157, /* wcpu */
13, /* mpdu_proc */
247, /* cmac0_dma */
0, /* cma1_dma */
101, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* USB 52B CABV*/
static struct ple_quota_t ple_qt59 = {
442, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
88, /* wcpu */
13, /* mpdu_proc */
178, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* USB 52B CABV*/
static struct ple_quota_t ple_qt60 = {
442, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
48, /* h2c */
121, /* wcpu */
13, /* mpdu_proc */
211, /* cmac0_dma */
0, /* cma1_dma */
65, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* USB2.0 52B */
static struct ple_quota_t ple_qt61 = {
780, /* cmac0_tx */
0, /* cmac1_tx */
16, /* c2h */
48, /* h2c */
88, /* wcpu */
13, /* mpdu_proc */
370, /* cmac0_dma */
0, /* cma1_dma */
32, /* bb_rpt */
14, /* wd_rel */
8, /* cpu_io */
0, /* tx_rpt */
};
/* USB2.0 52B */
static struct ple_quota_t ple_qt62 = {
780, /* cmac0_tx */
0, /* cmac1_tx */
32, /* c2h */
48, /* h2c */
121, /* wcpu */
13, /* mpdu_proc */
403, /* cmac0_dma */
0, /* cma1_dma */
65, /* bb_rpt */
14, /* wd_rel */
24, /* cpu_io */
0, /* tx_rpt */
};
/* 8852AU ccv */
static struct ple_quota_t ple_qt63 = {
2654, /* cmac0_tx */
0, /* cmac1_tx */
1134, /* c2h */
48, /* h2c */
64, /* wcpu */
13, /* mpdu_proc */
1478, /* cmac0_dma */
0, /* cma1_dma */
64, /* bb_rpt */
128, /* wd_rel */
120, /* cpu_io */
0, /* tx_rpt */
};
#if MAC_AX_PCIE_SUPPORT
static struct dle_mem_t dle_mem_pcie_8852a[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size0, &ple_size0, /* wde_size, ple_size */
&wde_qt0, &wde_qt0, /* wde_min_qt, wde_max_qt */
&ple_qt4, &ple_qt5}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC, /* qta_mode */
&wde_size0, &ple_size0, /* wde_size, ple_size */
&wde_qt0, &wde_qt0, /* wde_min_qt, wde_max_qt */
&ple_qt0, &ple_qt1}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SCC_STF, /* qta_mode */
&wde_size1, &ple_size2, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt8, &ple_qt9}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC_STF, /* qta_mode */
&wde_size1, &ple_size2, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt10, &ple_qt11}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SU_TP, /* qta_mode */
&wde_size3, &ple_size3, /* wde_size, ple_size */
&wde_qt3, &wde_qt3, /* wde_min_qt, wde_max_qt */
&ple_qt12, &ple_qt29}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size4, &ple_size4, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size10, &ple_size10, /* wde_size, ple_size */
&wde_qt9, &wde_qt9, /* wde_min_qt, wde_max_qt */
&ple_qt23, &ple_qt24}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_pcie_8852b[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size6, &ple_size6, /* wde_size, ple_size */
&wde_qt6, &wde_qt6, /* wde_min_qt, wde_max_qt */
&ple_qt18, &ple_qt19}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SCC_STF, /* qta_mode */
&wde_size8, &ple_size7, /* wde_size, ple_size */
&wde_qt8, &wde_qt8, /* wde_min_qt, wde_max_qt */
&ple_qt20, &ple_qt21}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size9, &ple_size8, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size11, &ple_size11, /* wde_size, ple_size */
&wde_qt10, &wde_qt10, /* wde_min_qt, wde_max_qt */
&ple_qt30, &ple_qt31}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_pcie_8852b_cabv[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size6, &ple_size23, /* wde_size, ple_size */
&wde_qt6, &wde_qt6, /* wde_min_qt, wde_max_qt */
&ple_qt18, &ple_qt56}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SCC_STF, /* qta_mode */
&wde_size23, &ple_size24, /* wde_size, ple_size */
&wde_qt23, &wde_qt23, /* wde_min_qt, wde_max_qt */
&ple_qt57, &ple_qt58}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size9, &ple_size25, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size11, &ple_size11, /* wde_size, ple_size */
&wde_qt10, &wde_qt10, /* wde_min_qt, wde_max_qt */
&ple_qt30, &ple_qt31}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_pcie_8852c[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size19, &ple_size19, /* wde_size, ple_size */
&wde_qt18, &wde_qt18, /* wde_min_qt, wde_max_qt */
&ple_qt46, &ple_qt47}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC, /* qta_mode */
&wde_size20, &ple_size20, /* wde_size, ple_size */
&wde_qt19, &wde_qt19, /* wde_min_qt, wde_max_qt */
&ple_qt48, &ple_qt49}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SCC_STF, /* qta_mode */
&wde_size21, &ple_size21, /* wde_size, ple_size */
&wde_qt20, &wde_qt20, /* wde_min_qt, wde_max_qt */
&ple_qt50, &ple_qt51}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC_STF, /* qta_mode */
&wde_size21, &ple_size21, /* wde_size, ple_size */
&wde_qt21, &wde_qt21, /* wde_min_qt, wde_max_qt */
&ple_qt52, &ple_qt53}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size18, &ple_size18, /* wde_size, ple_size */
&wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */
&ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size22, &ple_size22, /* wde_size, ple_size */
&wde_qt22, &wde_qt22, /* wde_min_qt, wde_max_qt */
&ple_qt54, &ple_qt55}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_pcie_8192xb[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size19, &ple_size19, /* wde_size, ple_size */
&wde_qt18, &wde_qt18, /* wde_min_qt, wde_max_qt */
&ple_qt46, &ple_qt47}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC, /* qta_mode */
&wde_size20, &ple_size20, /* wde_size, ple_size */
&wde_qt19, &wde_qt19, /* wde_min_qt, wde_max_qt */
&ple_qt48, &ple_qt49}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SCC_STF, /* qta_mode */
&wde_size21, &ple_size21, /* wde_size, ple_size */
&wde_qt20, &wde_qt20, /* wde_min_qt, wde_max_qt */
&ple_qt50, &ple_qt51}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC_STF, /* qta_mode */
&wde_size21, &ple_size21, /* wde_size, ple_size */
&wde_qt21, &wde_qt21, /* wde_min_qt, wde_max_qt */
&ple_qt52, &ple_qt53}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size18, &ple_size18, /* wde_size, ple_size */
&wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */
&ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size22, &ple_size22, /* wde_size, ple_size */
&wde_qt22, &wde_qt22, /* wde_min_qt, wde_max_qt */
&ple_qt54, &ple_qt55}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
#endif
#if MAC_AX_USB_SUPPORT
static struct dle_mem_t dle_mem_usb_8852a[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size1, &ple_size1, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt25, &ple_qt26}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC, /* qta_mode */
&wde_size1, &ple_size1, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt16, &ple_qt17}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size4, &ple_size4, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size15, &ple_size15, /* wde_size, ple_size */
&wde_qt14, &wde_qt14, /* wde_min_qt, wde_max_qt */
&ple_qt38, &ple_qt39}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_usb_8852a_ccv[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size26, &ple_size1, /* wde_size, ple_size */
&wde_qt26, &wde_qt26, /* wde_min_qt, wde_max_qt */
&ple_qt25, &ple_qt63}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC, /* qta_mode */
&wde_size1, &ple_size1, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt16, &ple_qt17}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size4, &ple_size4, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size15, &ple_size15, /* wde_size, ple_size */
&wde_qt14, &wde_qt14, /* wde_min_qt, wde_max_qt */
&ple_qt38, &ple_qt39}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_usb2_8852b[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size25, &ple_size27, /* wde_size, ple_size */
&wde_qt25, &wde_qt25, /* wde_min_qt, wde_max_qt */
&ple_qt61, &ple_qt62}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size9, &ple_size8, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size16, &ple_size16, /* wde_size, ple_size */
&wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */
&ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_usb3_8852b[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size8, &ple_size7, /* wde_size, ple_size */
&wde_qt8, &wde_qt8, /* wde_min_qt, wde_max_qt */
&ple_qt27, &ple_qt28}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size9, &ple_size8, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size16, &ple_size16, /* wde_size, ple_size */
&wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */
&ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_usb_8852b_cabv[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size24, &ple_size26, /* wde_size, ple_size */
&wde_qt24, &wde_qt24, /* wde_min_qt, wde_max_qt */
&ple_qt59, &ple_qt60}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size9, &ple_size25, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size16, &ple_size16, /* wde_size, ple_size */
&wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */
&ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_usb_8852c[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size17, &ple_size17, /* wde_size, ple_size */
&wde_qt16, &wde_qt16, /* wde_min_qt, wde_max_qt */
&ple_qt42, &ple_qt43}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size18, &ple_size18, /* wde_size, ple_size */
&wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */
&ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size16, &ple_size16, /* wde_size, ple_size */
&wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */
&ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_usb_8192xb[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size17, &ple_size17, /* wde_size, ple_size */
&wde_qt16, &wde_qt16, /* wde_min_qt, wde_max_qt */
&ple_qt42, &ple_qt43}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size18, &ple_size18, /* wde_size, ple_size */
&wde_qt17, &wde_qt17, /* wde_min_qt, wde_max_qt */
&ple_qt44, &ple_qt45}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size16, &ple_size16, /* wde_size, ple_size */
&wde_qt15, &wde_qt15, /* wde_min_qt, wde_max_qt */
&ple_qt40, &ple_qt41}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
#endif
#if MAC_AX_SDIO_SUPPORT
static struct dle_mem_t dle_mem_sdio_8852a[] = {
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size1, &ple_size1, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt2, &ple_qt3}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DBCC, /* qta_mode */
&wde_size1, &ple_size1, /* wde_size, ple_size */
&wde_qt1, &wde_qt1, /* wde_min_qt, wde_max_qt */
&ple_qt6, &ple_qt7}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size4, &ple_size4, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size12, &ple_size12, /* wde_size, ple_size */
&wde_qt11, &wde_qt11, /* wde_min_qt, wde_max_qt */
&ple_qt32, &ple_qt33}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
static struct dle_mem_t dle_mem_sdio_8852b[] = {
{MAC_AX_QTA_DLFW, /* qta_mode */
&wde_size9, &ple_size8, /* wde_size, ple_size */
&wde_qt4, &wde_qt4, /* wde_min_qt, wde_max_qt */
&ple_qt13, &ple_qt13}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_SCC, /* qta_mode */
&wde_size13, &ple_size13, /* wde_size, ple_size */
&wde_qt12, &wde_qt12, /* wde_min_qt, wde_max_qt */
&ple_qt34, &ple_qt35}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_LAMODE, /* qta_mode */
&wde_size14, &ple_size14, /* wde_size, ple_size */
&wde_qt13, &wde_qt13, /* wde_min_qt, wde_max_qt */
&ple_qt36, &ple_qt37}, /* ple_min_qt, ple_max_qt */
{MAC_AX_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, NULL},
};
#endif
u32 dle_is_txq_empty(struct mac_ax_adapter *adapter, u8 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, rval32;
val32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH |
B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 |
B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS |
B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN |
B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU |
B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO |
B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL |
B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX |
B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU;
rval32 = MAC_REG_R32(R_AX_DLE_EMPTY0);
if (val32 != (rval32 & val32)) {
*val = DLE_QUEUE_NONEMPTY;
PLTFM_MSG_TRACE("[TRACE]TXQ non empty 0x%X\n", rval32);
} else {
*val = DLE_QUEUE_EMPTY;
PLTFM_MSG_TRACE("[TRACE]TXQ empty 0x%X\n", rval32);
}
return MACSUCCESS;
}
u32 dle_is_rxq_empty(struct mac_ax_adapter *adapter, u8 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, rval32;
val32 = B_AX_WDE_EMPTY_QUE_DMAC_WDRLS | B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX |
B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX | B_AX_PLE_EMPTY_QUE_DMAC_HDP |
B_AX_PLE_EMPTY_QUE_DMAC_PLRLS | B_AX_PLE_EMPTY_QUE_DMAC_CPUIO |
B_AX_PLE_EMPTY_QTA_DMAC_C2H | B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX |
B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX |
B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT |
B_AX_PLE_EMPTY_QTA_DMAC_WDRLS;
rval32 = MAC_REG_R32(R_AX_DLE_EMPTY1);
if (val32 != (rval32 & val32)) {
*val = DLE_QUEUE_NONEMPTY;
PLTFM_MSG_TRACE("[TRACE] RXQ non empty 0x%X\n", rval32);
} else {
*val = DLE_QUEUE_EMPTY;
PLTFM_MSG_TRACE("[TRACE] RXQ empty 0x%X\n", rval32);
}
return MACSUCCESS;
}
u32 dle_dfi_ctrl(struct mac_ax_adapter *adapter, struct dle_dfi_ctrl_t *ctrl_p)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cnt, ctrl_reg, data_reg, ctrl_data;
switch (ctrl_p->type) {
case DLE_CTRL_TYPE_WDE:
ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL;
data_reg = R_AX_WDE_DBG_FUN_INTF_DATA;
ctrl_data = SET_WORD(ctrl_p->target,
B_AX_WDE_DFI_TRGSEL) |
SET_WORD(ctrl_p->addr, B_AX_WDE_DFI_ADDR) |
B_AX_WDE_DFI_ACTIVE;
break;
case DLE_CTRL_TYPE_PLE:
ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL;
data_reg = R_AX_PLE_DBG_FUN_INTF_DATA;
ctrl_data = SET_WORD(ctrl_p->target,
B_AX_PLE_DFI_TRGSEL) |
SET_WORD(ctrl_p->addr, B_AX_PLE_DFI_ADDR) |
B_AX_PLE_DFI_ACTIVE;
break;
default:
PLTFM_MSG_ERR("[ERR] dfi ctrl type %d\n", ctrl_p->type);
return MACFUNCINPUT;
}
MAC_REG_W32(ctrl_reg, ctrl_data);
cnt = DLE_DFI_WAIT_CNT;
while (cnt && MAC_REG_R32(ctrl_reg) & B_AX_WDE_DFI_ACTIVE) {
PLTFM_DELAY_US(DLE_DFI_WAIT_US);
cnt--;
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
ctrl_reg, ctrl_data);
return MACPOLLTO;
}
ctrl_p->out_data = MAC_REG_R32(data_reg);
return MACSUCCESS;
}
u32 dle_dfi_freepg(struct mac_ax_adapter *adapter,
struct dle_dfi_freepg_t *freepg)
{
struct dle_dfi_ctrl_t ctrl;
u32 ret;
ctrl.type = freepg->dle_type;
ctrl.target = DLE_DFI_TYPE_FREEPG;
ctrl.addr = DFI_TYPE_FREEPG_IDX;
ret = dle_dfi_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret);
return ret;
}
freepg->free_headpg = GET_FIELD(ctrl.out_data, B_AX_DLE_FREE_HEADPG);
freepg->free_tailpg = GET_FIELD(ctrl.out_data, B_AX_DLE_FREE_TAILPG);
ctrl.addr = DFI_TYPE_FREEPG_PUBNUM;
ret = dle_dfi_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret);
return ret;
}
freepg->pub_pgnum = GET_FIELD(ctrl.out_data, B_AX_DLE_PUB_PGNUM);
return MACSUCCESS;
}
u32 dle_dfi_quota(struct mac_ax_adapter *adapter,
struct dle_dfi_quota_t *quota)
{
struct dle_dfi_ctrl_t ctrl;
u32 ret;
ctrl.type = quota->dle_type;
ctrl.target = DLE_DFI_TYPE_QUOTA;
ctrl.addr = quota->qtaid;
ret = dle_dfi_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret);
return ret;
}
quota->rsv_pgnum = GET_FIELD(ctrl.out_data, B_AX_DLE_RSV_PGNUM);
quota->use_pgnum = GET_FIELD(ctrl.out_data, B_AX_DLE_USE_PGNUM);
return MACSUCCESS;
}
u32 dle_dfi_qempty(struct mac_ax_adapter *adapter,
struct dle_dfi_qempty_t *qempty)
{
struct dle_dfi_ctrl_t ctrl;
u32 ret;
ctrl.type = qempty->dle_type;
ctrl.target = DLE_DFI_TYPE_QEMPTY;
ctrl.addr = qempty->grpsel;
ret = dle_dfi_ctrl(adapter, &ctrl);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle_dfi_ctrl %d\n", ret);
return ret;
}
qempty->qempty = GET_FIELD(ctrl.out_data, B_AX_DLE_QEMPTY_GRP);
return MACSUCCESS;
}
u32 mac_is_txq_empty(struct mac_ax_adapter *adapter,
struct mac_ax_tx_queue_empty *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct dle_dfi_qempty_t qempty;
u32 val32, val32_emp0, ret;
u32 i, j, qnum;
PLTFM_MEMSET(val, 0xFF, sizeof(struct mac_ax_tx_queue_empty));
qempty.dle_type = DLE_CTRL_TYPE_WDE;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
qnum = WDE_QEMPTY_ACQ_NUM_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
qnum = WDE_QEMPTY_ACQ_NUM_8852B;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
qnum = WDE_QEMPTY_ACQ_NUM_8852C;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
qnum = WDE_QEMPTY_ACQ_NUM_8192XB;
} else {
PLTFM_MSG_ERR("[ERR]wde qempty acq num not define\n");
return MACCHIPID;
}
for (i = 0; i < qnum; i++) {
qempty.grpsel = i;
ret = dle_dfi_qempty(adapter, &qempty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle dfi acq empty %d\n", ret);
return ret;
}
for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) {
val32 = GET_FIEL2(qempty.qempty,
j * QEMP_ACQ_GRP_QSEL_SH,
QEMP_ACQ_GRP_QSEL_MASK);
if (val32 != QEMP_ACQ_GRP_QSEL_MASK)
val->macid_txq_empty[i] &= ~BIT(j);
}
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8852A;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8852B;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8852C;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
qempty.grpsel = WDE_QEMPTY_MGQ_SEL_8192XB;
} else {
PLTFM_MSG_ERR("[ERR]wde qempty mgq sel not define\n");
return MACCHIPID;
}
ret = dle_dfi_qempty(adapter, &qempty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]dle dfi mgq empty %d\n", ret);
return ret;
}
if (!(qempty.qempty & B_CMAC0_MGQ_NORMAL))
val->band0_mgnt_empty = 0;
if (is_curr_dbcc(adapter) && !(qempty.qempty & B_CMAC1_MGQ_NORMAL))
val->band1_mgnt_empty = 0;
val32 = B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ;
if (is_curr_dbcc(adapter))
val32 |= B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ;
if ((qempty.qempty & val32) != val32)
val->fw_txq_empty = 0;
val32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU |
B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU;
val32_emp0 = MAC_REG_R32(R_AX_DLE_EMPTY0);
if (val32 != (val32_emp0 & val32))
val->fw_txq_empty = 0;
if (!(val32_emp0 & B_AX_PLE_EMPTY_QTA_DMAC_H2C))
val->h2c_empty = 0;
val32 = B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX |
B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF |
B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN |
B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL |
B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX;
if (val32 != (val32_emp0 & val32))
val->others_empty = 0;
return MACSUCCESS;
}
u32 mac_is_rxq_empty(struct mac_ax_adapter *adapter,
struct mac_ax_rx_queue_empty *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, val32_emp1;
PLTFM_MEMSET(val, 0xFF, sizeof(struct mac_ax_rx_queue_empty));
val32_emp1 = MAC_REG_R32(R_AX_DLE_EMPTY1);
if (!(val32_emp1 & B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX))
val->band0_rxq_empty = 0;
if (!(val32_emp1 & B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX))
val->band1_rxq_empty = 0;
if (!(val32_emp1 & B_AX_PLE_EMPTY_QTA_DMAC_C2H))
val->c2h_empty = 0;
val32 = B_AX_WDE_EMPTY_QUE_DMAC_WDRLS | B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX |
B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX | B_AX_PLE_EMPTY_QUE_DMAC_HDP |
B_AX_PLE_EMPTY_QUE_DMAC_PLRLS | B_AX_PLE_EMPTY_QUE_DMAC_CPUIO |
B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT |
B_AX_PLE_EMPTY_QTA_DMAC_WDRLS;
if (val32 != (val32_emp1 & val32))
val->others_empty = 0;
return MACSUCCESS;
}
u32 mac_chk_allq_empty(struct mac_ax_adapter *adapter, u8 *empty)
{
u8 chk_cnt, txq_empty, rxq_empty;
u32 ret;
*empty = 1;
for (chk_cnt = 0; chk_cnt < QUEUE_EMPTY_CHK_CNT; chk_cnt++) {
ret = dle_is_txq_empty(adapter, &txq_empty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] TXQ chk fail %d\n", ret);
return ret;
}
ret = dle_is_rxq_empty(adapter, &rxq_empty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] TXQ chk fail %d\n", ret);
return ret;
}
if (!(txq_empty & rxq_empty)) {
PLTFM_MSG_TRACE("[TRACE] CHK TXQ %d RXQ %d\n",
txq_empty, rxq_empty);
*empty = 0;
break;
}
}
return MACSUCCESS;
}
u32 dle_used_size(struct dle_size_t *wde, struct dle_size_t *ple)
{
return (u32)(wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num)) +
(u32)(ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num));
}
u32 dle_rsvd_size(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode)
{
if (mode != MAC_AX_QTA_LAMODE)
return 0;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
return DLE_LAMODE_SIZE_8852A;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
return DLE_LAMODE_SIZE_8852B;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
return DLE_LAMODE_SIZE_8852C;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
return DLE_LAMODE_SIZE_8192XB;
else
return 0;
}
void dle_func_en(struct mac_ax_adapter *adapter, u8 en)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN);
if (en == MAC_AX_FUNC_EN)
val32 |= (B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
else if (en == MAC_AX_FUNC_DIS)
val32 &= ~(B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
else
return;
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32);
}
void dle_clk_en(struct mac_ax_adapter *adapter, u8 en)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN);
if (en == MAC_AX_FUNC_EN)
val32 |= (B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN);
else if (en == MAC_AX_FUNC_DIS)
val32 &= ~(B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN);
else
return;
MAC_REG_W32(R_AX_DMAC_CLK_EN, val32);
}
struct dle_mem_t *get_dle_mem_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_qta_mode mode)
{
struct dle_mem_t *cfg;
enum mac_ax_intf intf = adapter->hw_info->intf;
switch (intf) {
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_INTF_SDIO:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
cfg = dle_mem_sdio_8852a;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
cfg = dle_mem_sdio_8852b;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
cfg = dle_mem_sdio_8852b;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
cfg = dle_mem_sdio_8852b;
else
cfg = NULL;
break;
#endif
#if MAC_AX_USB_SUPPORT
case MAC_AX_INTF_USB:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) &&
(is_cv(adapter, CCV)))
cfg = dle_mem_usb_8852a_ccv;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
cfg = dle_mem_usb_8852a;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
(is_cv(adapter, CAV) || is_cv(adapter, CBV)))
cfg = dle_mem_usb_8852b_cabv;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
(get_usb_mode(adapter) == MAC_AX_USB2))
cfg = dle_mem_usb2_8852b;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
cfg = dle_mem_usb3_8852b;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
cfg = dle_mem_usb_8852a;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
cfg = dle_mem_usb_8192xb;
else
cfg = NULL;
break;
#endif
#if MAC_AX_PCIE_SUPPORT
case MAC_AX_INTF_PCIE:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
cfg = dle_mem_pcie_8852a;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
(is_cv(adapter, CAV) || is_cv(adapter, CBV)))
cfg = dle_mem_pcie_8852b_cabv;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
cfg = dle_mem_pcie_8852b;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
cfg = dle_mem_pcie_8852c;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
cfg = dle_mem_pcie_8192xb;
else
cfg = NULL;
break;
#endif
default:
cfg = NULL;
break;
}
if (!cfg)
return NULL;
for (; cfg->mode != MAC_AX_QTA_INVALID; cfg++) {
if (cfg->mode == mode) {
adapter->dle_info.wde_pg_size = cfg->wde_size->pge_size;
adapter->dle_info.ple_pg_size = cfg->ple_size->pge_size;
adapter->dle_info.qta_mode = mode;
adapter->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
adapter->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma;
adapter->dle_info.c0_tx_min = cfg->ple_min_qt->cma0_tx;
adapter->dle_info.c1_tx_min = cfg->ple_min_qt->cma1_tx;
return cfg;
}
}
return NULL;
}
u32 dle_mix_cfg(struct mac_ax_adapter *adapter, struct dle_mem_t *cfg)
{
u8 bound;
u32 val32;
struct dle_size_t *size_cfg;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_WDE_PKTBUF_CFG);
bound = 0;
size_cfg = cfg->wde_size;
switch (size_cfg->pge_size) {
default:
case MAC_AX_WDE_PG_64:
val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_64,
B_AX_WDE_PAGE_SEL);
break;
case MAC_AX_WDE_PG_128:
val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_128,
B_AX_WDE_PAGE_SEL);
break;
case MAC_AX_WDE_PG_256:
PLTFM_MSG_ERR("[ERR]WDE DLE doesn't support 256 byte!\n");
return MACHWNOSUP;
}
val32 = SET_CLR_WORD(val32, bound, B_AX_WDE_START_BOUND);
val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num,
B_AX_WDE_FREE_PAGE_NUM);
MAC_REG_W32(R_AX_WDE_PKTBUF_CFG, val32);
val32 = MAC_REG_R32(R_AX_PLE_PKTBUF_CFG);
bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num)
* size_cfg->pge_size / DLE_BOUND_UNIT;
size_cfg = cfg->ple_size;
switch (size_cfg->pge_size) {
default:
case MAC_AX_PLE_PG_64:
PLTFM_MSG_ERR("[ERR]PLE DLE doesn't support 64 byte!\n");
return MACHWNOSUP;
case MAC_AX_PLE_PG_128:
val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_128,
B_AX_PLE_PAGE_SEL);
break;
case MAC_AX_PLE_PG_256:
val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_256,
B_AX_PLE_PAGE_SEL);
break;
}
val32 = SET_CLR_WORD(val32, bound, B_AX_PLE_START_BOUND);
val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num,
B_AX_PLE_FREE_PAGE_NUM);
MAC_REG_W32(R_AX_PLE_PKTBUF_CFG, val32);
return MACSUCCESS;
}
void wde_quota_cfg(struct mac_ax_adapter *adapter,
struct wde_quota_t *min_cfg,
struct wde_quota_t *max_cfg)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = SET_WORD(min_cfg->hif, B_AX_WDE_Q0_MIN_SIZE) |
SET_WORD(max_cfg->hif, B_AX_WDE_Q0_MAX_SIZE);
MAC_REG_W32(R_AX_WDE_QTA0_CFG, val32);
val32 = SET_WORD(min_cfg->wcpu, B_AX_WDE_Q1_MIN_SIZE) |
SET_WORD(max_cfg->wcpu, B_AX_WDE_Q1_MAX_SIZE);
MAC_REG_W32(R_AX_WDE_QTA1_CFG, val32);
val32 = SET_WORD(min_cfg->pkt_in, B_AX_WDE_Q3_MIN_SIZE) |
SET_WORD(max_cfg->pkt_in, B_AX_WDE_Q3_MAX_SIZE);
MAC_REG_W32(R_AX_WDE_QTA3_CFG, val32);
val32 = SET_WORD(min_cfg->cpu_io, B_AX_WDE_Q4_MIN_SIZE) |
SET_WORD(max_cfg->cpu_io, B_AX_WDE_Q4_MAX_SIZE);
MAC_REG_W32(R_AX_WDE_QTA4_CFG, val32);
}
void ple_quota_cfg(struct mac_ax_adapter *adapter,
struct ple_quota_t *min_cfg,
struct ple_quota_t *max_cfg)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = SET_WORD(min_cfg->cma0_tx, B_AX_PLE_Q0_MIN_SIZE) |
SET_WORD(max_cfg->cma0_tx, B_AX_PLE_Q0_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA0_CFG, val32);
val32 = SET_WORD(min_cfg->cma1_tx, B_AX_PLE_Q1_MIN_SIZE) |
SET_WORD(max_cfg->cma1_tx, B_AX_PLE_Q1_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA1_CFG, val32);
val32 = SET_WORD(min_cfg->c2h, B_AX_PLE_Q2_MIN_SIZE) |
SET_WORD(max_cfg->c2h, B_AX_PLE_Q2_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA2_CFG, val32);
val32 = SET_WORD(min_cfg->h2c, B_AX_PLE_Q3_MIN_SIZE) |
SET_WORD(max_cfg->h2c, B_AX_PLE_Q3_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA3_CFG, val32);
val32 = SET_WORD(min_cfg->wcpu, B_AX_PLE_Q4_MIN_SIZE) |
SET_WORD(max_cfg->wcpu, B_AX_PLE_Q4_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA4_CFG, val32);
val32 = SET_WORD(min_cfg->mpdu_proc, B_AX_PLE_Q5_MIN_SIZE) |
SET_WORD(max_cfg->mpdu_proc, B_AX_PLE_Q5_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA5_CFG, val32);
val32 = SET_WORD(min_cfg->cma0_dma, B_AX_PLE_Q6_MIN_SIZE) |
SET_WORD(max_cfg->cma0_dma, B_AX_PLE_Q6_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA6_CFG, val32);
val32 = SET_WORD(min_cfg->cma1_dma, B_AX_PLE_Q7_MIN_SIZE) |
SET_WORD(max_cfg->cma1_dma, B_AX_PLE_Q7_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA7_CFG, val32);
val32 = SET_WORD(min_cfg->bb_rpt, B_AX_PLE_Q8_MIN_SIZE) |
SET_WORD(max_cfg->bb_rpt, B_AX_PLE_Q8_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA8_CFG, val32);
val32 = SET_WORD(min_cfg->wd_rel, B_AX_PLE_Q9_MIN_SIZE) |
SET_WORD(max_cfg->wd_rel, B_AX_PLE_Q9_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA9_CFG, val32);
val32 = SET_WORD(min_cfg->cpu_io, B_AX_PLE_Q10_MIN_SIZE) |
SET_WORD(max_cfg->cpu_io, B_AX_PLE_Q10_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA10_CFG, val32);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = SET_WORD(min_cfg->tx_rpt, B_AX_PLE_Q11_MIN_SIZE) |
SET_WORD(max_cfg->tx_rpt, B_AX_PLE_Q11_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA11_CFG, val32);
}
}
void dle_quota_cfg(struct mac_ax_adapter *adapter, struct dle_mem_t *cfg)
{
wde_quota_cfg(adapter, cfg->wde_min_qt, cfg->wde_max_qt);
ple_quota_cfg(adapter, cfg->ple_min_qt, cfg->ple_max_qt);
}
u32 dle_quota_change(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode)
{
u32 ret = MACSUCCESS;
struct dle_mem_t *cfg;
struct cpuio_buf_req_t buf_req;
struct cpuio_ctrl_t ctrl_para;
u32 val32_1, val32_2;
cfg = get_dle_mem_cfg(adapter, mode);
if (!cfg) {
PLTFM_MSG_ERR("[ERR]wd/dle mem cfg\n");
return MACNOITEM;
}
val32_1 = dle_used_size(cfg->wde_size, cfg->ple_size);
val32_2 = adapter->hw_info->fifo_size - dle_rsvd_size(adapter, mode);
if (val32_1 != val32_2) {
PLTFM_MSG_ERR("[ERR]dle used size %d not match %d\n",
val32_1, val32_2);
return MACFFCFG;
}
dle_quota_cfg(adapter, cfg);
//Trigger change by enqueue packet
// Use CPUIO temporarily.
//WD
buf_req.len = 0x20; // chris comment
ret = mac_dle_buf_req_wd(adapter, &buf_req);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]WDE DLE buf req %d\n", ret);
return ret;
}
PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para));
ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
ctrl_para.start_pktid = buf_req.pktid;
ctrl_para.end_pktid = buf_req.pktid;
ctrl_para.pkt_num = 0;
ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
ret = mac_set_cpuio_wd(adapter, &ctrl_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]WDE DLE enqueue to head %d\n", ret);
return ret;
}
//PL
buf_req.len = 0x20;
ret = mac_dle_buf_req_pl(adapter, &buf_req);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]PLE DLE buf req %d\n", ret);
return ret;
}
PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para));
ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
ctrl_para.start_pktid = buf_req.pktid;
ctrl_para.end_pktid = buf_req.pktid;
ctrl_para.pkt_num = 0;
ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS;
ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT;
ret = mac_set_cpuio_pl(adapter, &ctrl_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]PLE DLE enqueue to head %d\n", ret);
return ret;
}
return ret;
}
u32 dle_init(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode,
enum mac_ax_qta_mode ext_mode)
{
u32 ret = MACSUCCESS;
u32 cnt, val32_1, val32_2;
struct dle_mem_t *cfg, *ext_cfg;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct dle_mem_t cfg_tmp;
struct dle_size_t wde_size_tmp, ple_size_tmp;
struct wde_quota_t wde_min_qt_tmp, wde_max_qt_tmp;
struct ple_quota_t ple_min_qt_tmp, ple_max_qt_tmp;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]chk dmac en %d\n", ret);
return ret;
}
cfg = get_dle_mem_cfg(adapter, mode);
if (!cfg) {
ret = MACNOITEM;
PLTFM_MSG_ERR("[ERR]get_dle_mem_cfg %d\n", mode);
goto error;
}
PLTFM_MEMCPY(&wde_size_tmp, cfg->wde_size, sizeof(struct dle_size_t));
PLTFM_MEMCPY(&ple_size_tmp, cfg->ple_size, sizeof(struct dle_size_t));
PLTFM_MEMCPY(&wde_min_qt_tmp, cfg->wde_min_qt, sizeof(struct wde_quota_t));
PLTFM_MEMCPY(&wde_max_qt_tmp, cfg->wde_max_qt, sizeof(struct wde_quota_t));
PLTFM_MEMCPY(&ple_min_qt_tmp, cfg->ple_min_qt, sizeof(struct ple_quota_t));
PLTFM_MEMCPY(&ple_max_qt_tmp, cfg->ple_max_qt, sizeof(struct ple_quota_t));
cfg_tmp.mode = cfg->mode;
cfg_tmp.wde_size = &wde_size_tmp;
cfg_tmp.ple_size = &ple_size_tmp;
cfg_tmp.wde_min_qt = &wde_min_qt_tmp;
cfg_tmp.wde_max_qt = &wde_max_qt_tmp;
cfg_tmp.ple_min_qt = &ple_min_qt_tmp;
cfg_tmp.ple_max_qt = &ple_max_qt_tmp;
cfg = &cfg_tmp;
if (mode == MAC_AX_QTA_DLFW) {
ext_cfg = get_dle_mem_cfg(adapter, ext_mode);
if (!ext_cfg) {
ret = MACNOITEM;
PLTFM_MSG_ERR("[ERR]get_dle_ext_mem_cfg %d\n",
ext_mode);
goto error;
}
cfg->wde_min_qt->wcpu = ext_cfg->wde_min_qt->wcpu;
}
val32_1 = dle_used_size(cfg->wde_size, cfg->ple_size);
val32_2 = adapter->hw_info->fifo_size - dle_rsvd_size(adapter, mode);
if (val32_1 != val32_2) {
PLTFM_MSG_ERR("[ERR]dle init used size %d not match %d\n",
val32_1, val32_2);
ret = MACFFCFG;
goto error;
}
dle_func_en(adapter, MAC_AX_FUNC_DIS);
dle_clk_en(adapter, MAC_AX_FUNC_EN);
ret = dle_mix_cfg(adapter, cfg);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] dle mix cfg %d\n", ret);
goto error;
}
dle_quota_cfg(adapter, cfg);
dle_func_en(adapter, MAC_AX_FUNC_EN);
cnt = DLE_WAIT_CNT;
while (cnt--) {
if ((MAC_REG_R32(R_AX_WDE_INI_STATUS) & WDE_MGN_INI_RDY)
== WDE_MGN_INI_RDY)
break;
PLTFM_DELAY_US(DLE_WAIT_US);
}
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]WDE cfg ready timeout\n");
return MACPOLLTO;
}
cnt = DLE_WAIT_CNT;
while (cnt--) {
if ((MAC_REG_R32(R_AX_PLE_INI_STATUS) & PLE_MGN_INI_RDY)
== PLE_MGN_INI_RDY)
break;
PLTFM_DELAY_US(DLE_WAIT_US);
}
if (!++cnt) {
PLTFM_MSG_ERR("[ERR]PLE cfg ready timeout\n");
return MACPOLLTO;
}
return ret;
error:
dle_func_en(adapter, MAC_AX_FUNC_DIS);
PLTFM_MSG_ERR("[ERR]trxcfg wde 0x8900 = %x\n",
MAC_REG_R32(R_AX_WDE_INI_STATUS));
PLTFM_MSG_ERR("[ERR]trxcfg ple 0x8D00 = %x\n",
MAC_REG_R32(R_AX_PLE_INI_STATUS));
return ret;
}
u32 is_qta_dbcc(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode,
u8 *is_dbcc)
{
struct dle_mem_t *cfg;
cfg = get_dle_mem_cfg(adapter, mode);
if (!cfg) {
PLTFM_MSG_ERR("[ERR]get_dle_mem_cfg\n");
return MACNOITEM;
}
*is_dbcc = (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma) ?
1 : 0;
return MACSUCCESS;
}
u8 is_curr_dbcc(struct mac_ax_adapter *adapter)
{
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
return 0;
return adapter->dle_info.c1_rx_qta ? 1 : 0;
}
u32 is_qta_poh(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode,
u8 *is_poh)
{
*is_poh = (mode == MAC_AX_QTA_SCC_STF || mode == MAC_AX_QTA_DBCC_STF) ?
0 : 1;
return MACSUCCESS;
}
u32 _patch_redu_rx_qta(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u16 new_qta, qta_min, qta_max, rdu_pg_num;
if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)))
return MACSUCCESS;
val32 = GET_FIELD(MAC_REG_R32(R_AX_PLE_PKTBUF_CFG), B_AX_PLE_PAGE_SEL);
if (val32 == S_AX_PLE_PAGE_SEL_128) {
rdu_pg_num = PLE_QTA_PG128B_12KB;
} else if (val32 == S_AX_PLE_PAGE_SEL_256) {
rdu_pg_num = PLE_QTA_PG128B_12KB / 2;
} else {
PLTFM_MSG_ERR("[ERR]PLE page sel %d unsupport\n", val32);
return MACHWERR;
}
val32 = MAC_REG_R32(R_AX_PLE_QTA6_CFG);
if (!val32) {
PLTFM_MSG_ERR("[ERR]no rx 0 qta\n");
return MACHWERR;
}
qta_min = GET_FIELD(val32, B_AX_PLE_Q6_MIN_SIZE);
qta_max = GET_FIELD(val32, B_AX_PLE_Q6_MAX_SIZE);
adapter->dle_info.c0_ori_max = qta_max;
new_qta = (qta_max - qta_min) < rdu_pg_num ?
qta_min : (qta_max - rdu_pg_num);
val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q6_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA6_CFG, val32);
val32 = MAC_REG_R32(R_AX_PLE_QTA7_CFG);
if (!val32)
return MACSUCCESS;
qta_min = GET_FIELD(val32, B_AX_PLE_Q7_MIN_SIZE);
qta_max = GET_FIELD(val32, B_AX_PLE_Q7_MAX_SIZE);
adapter->dle_info.c1_ori_max = qta_max;
new_qta = (qta_max - qta_min) < rdu_pg_num ?
qta_min : (qta_max - rdu_pg_num);
val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q7_MAX_SIZE);
MAC_REG_W32(R_AX_PLE_QTA7_CFG, val32);
return MACSUCCESS;
}
u32 _patch_restr_rx_qta(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, w_val32;
if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)))
return MACSUCCESS;
val32 = MAC_REG_R32(R_AX_PLE_QTA6_CFG);
if (!val32) {
PLTFM_MSG_ERR("[ERR]no rx 0 qta\n");
return MACHWERR;
}
w_val32 = SET_CLR_WORD(val32, adapter->dle_info.c0_ori_max,
B_AX_PLE_Q6_MAX_SIZE);
if (w_val32 != val32)
MAC_REG_W32(R_AX_PLE_QTA6_CFG, w_val32);
val32 = MAC_REG_R32(R_AX_PLE_QTA7_CFG);
if (!val32)
return MACSUCCESS;
w_val32 = SET_CLR_WORD(val32, adapter->dle_info.c1_ori_max,
B_AX_PLE_Q7_MAX_SIZE);
if (w_val32 != val32)
MAC_REG_W32(R_AX_PLE_QTA7_CFG, w_val32);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dle.c
|
C
|
agpl-3.0
| 68,912
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_DLE_H_
#define _MAC_AX_DLE_H_
#include "../type.h"
#include "../mac_ax.h"
#include "cpuio.h"
/*--------------------Define ----------------------------------------*/
#define DLE_DFI_WAIT_CNT 1000
#define DLE_DFI_WAIT_US 1
#define DLE_WAIT_CNT 2000
#define DLE_WAIT_US 1
// DLE_DFI_TYPE_FREEPG
#define B_AX_DLE_FREE_TAILPG_SH 16
#define B_AX_DLE_FREE_TAILPG_MSK 0xfff
#define B_AX_DLE_FREE_HEADPG_SH 0
#define B_AX_DLE_FREE_HEADPG_MSK 0xfff
#define B_AX_DLE_PUB_PGNUM_SH 0
#define B_AX_DLE_PUB_PGNUM_MSK 0x1fff
// DLE_DFI_TYPE_QUOTA
#define B_AX_DLE_USE_PGNUM_SH 16
#define B_AX_DLE_USE_PGNUM_MSK 0xfff
#define B_AX_DLE_RSV_PGNUM_SH 0
#define B_AX_DLE_RSV_PGNUM_MSK 0xfff
// DLE_DFI_TYPE_QEMPTY
#define B_AX_DLE_QEMPTY_GRP_SH 0
#define B_AX_DLE_QEMPTY_GRP_MSK 0xffffffff
#define QUEUE_EMPTY_CHK_CNT 2
#define WDE_QEMPTY_NUM_8852A 18
#define WDE_QEMPTY_NUM_8852B 5
#define WDE_QEMPTY_NUM_8852C 19
#define WDE_QEMPTY_NUM_8192XB 18
#define PLE_QEMPTY_NUM 2
#define WDE_QEMPTY_ACQ_NUM_8852A 16 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */
#define WDE_QEMPTY_ACQ_NUM_8852B 4 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */
#define WDE_QEMPTY_ACQ_NUM_8852C 16 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */
#define WDE_QEMPTY_ACQ_NUM_8192XB 16 /* cannot over WDE_QEMPTY_ACQ_NUM_MAX */
#define WDE_QEMPTY_MGQ_SEL_8852A 16
#define WDE_QEMPTY_MGQ_SEL_8852B 4
#define WDE_QEMPTY_MGQ_SEL_8852C 16
#define WDE_QEMPTY_MGQ_SEL_8192XB 16
#define QEMP_ACQ_GRP_MACID_NUM 8
#define QEMP_ACQ_GRP_QSEL_SH 4
#define QEMP_ACQ_GRP_QSEL_MASK 0xF
#define S_AX_WDE_PAGE_SEL_64 0
#define S_AX_WDE_PAGE_SEL_128 1
/* #define S_AX_WDE_PAGE_SEL_256 2 // HDP not support */
/* #define S_AX_PLE_PAGE_SEL_64 0 // HDP not support */
#define S_AX_PLE_PAGE_SEL_128 1
#define S_AX_PLE_PAGE_SEL_256 2
#define DLE_BOUND_UNIT (8 * 1024)
#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY)
#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY)
#define DLE_QUEUE_NONEMPTY 0
#define DLE_QUEUE_EMPTY 1
#define B_CMAC0_MGQ_NORMAL BIT2
#define B_CMAC0_MGQ_NO_PWRSAV BIT3
#define B_CMAC0_CPUMGQ BIT4
#define B_CMAC1_MGQ_NORMAL BIT10
#define B_CMAC1_MGQ_NO_PWRSAV BIT11
#define B_CMAC1_CPUMGQ BIT12
#define DLE_LAMODE_SIZE_8852A (256 * 1024)
#define DLE_LAMODE_SIZE_8852B (64 * 1024)
#define DLE_LAMODE_SIZE_8852C (192 * 1024)
#define DLE_LAMODE_SIZE_8192XB (192 * 1024)
#define WDE_QTA_NUM 5
#define PLE_QTA_NUM_8852AB 11
#define PLE_QTA_NUM_8852C 12
#define PLE_QTA_NUM_8192XB 12
#define PLE_QTA_PG128B_12KB 96
/*--------------------Define Enum------------------------------------*/
/**
* @enum WDE_QTAID
*
* @brief WDE_QTAID
*
* @var WDE_QTAID::WDE_QTAID_HOST_IF
* Please Place Description here.
* @var WDE_QTAID::WDE_QTAID_WLAN_CPU
* Please Place Description here.
* @var WDE_QTAID::WDE_QTAID_DATA_CPU
* Please Place Description here.
* @var WDE_QTAID::WDE_QTAID_PKTIN
* Please Place Description here.
* @var WDE_QTAID::WDE_QTAID_CPUIO
* Please Place Description here.
*/
enum WDE_QTAID {
WDE_QTAID_HOST_IF = 0,
WDE_QTAID_WLAN_CPU = 1,
WDE_QTAID_DATA_CPU = 2,
WDE_QTAID_PKTIN = 3,
WDE_QTAID_CPUIO = 4
};
/**
* @enum PLE_QTAID
*
* @brief PLE_QTAID
*
* @var PLE_QTAID::PLE_QTAID_B0_TXPL
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_B1_TXPL
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_C2H
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_H2C
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_WLAN_CPU
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_MPDU
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_CMAC0_RX
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_CMAC1_RX
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_CMAC1_BBRPT
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_WDRLS
* Please Place Description here.
* @var PLE_QTAID::PLE_QTAID_CPUIO
* Please Place Description here.
*/
enum PLE_QTAID {
PLE_QTAID_B0_TXPL = 0,
PLE_QTAID_B1_TXPL = 1,
PLE_QTAID_C2H = 2,
PLE_QTAID_H2C = 3,
PLE_QTAID_WLAN_CPU = 4,
PLE_QTAID_MPDU = 5,
PLE_QTAID_CMAC0_RX = 6,
PLE_QTAID_CMAC1_RX = 7,
PLE_QTAID_BBRPT = 8,
PLE_QTAID_WDRLS = 9,
PLE_QTAID_CPUIO = 10,
PLE_QTAID_TXRPT = 11
};
/**
* @enum DLE_CTRL_TYPE
*
* @brief DLE_CTRL_TYPE
*
* @var DLE_CTRL_TYPE::DLE_CTRL_TYPE_WDE
* Please Place Description here.
* @var DLE_CTRL_TYPE::DLE_CTRL_TYPE_PLE
* Please Place Description here.
* @var DLE_CTRL_TYPE::DLE_CTRL_TYPE_NUM
* Please Place Description here.
*/
enum DLE_CTRL_TYPE {
DLE_CTRL_TYPE_WDE = 0,
DLE_CTRL_TYPE_PLE = 1,
DLE_CTRL_TYPE_NUM = 2
};
/**
* @enum DLE_DFI_TYPE
*
* @brief DLE_DFI_TYPE
*
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_FREEPG
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_QUOTA
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_PAGELLT
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_PKTINFO
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_PREPKTLLT
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_NXTPKTLLT
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_QLNKTBL
* Please Place Description here.
* @var DLE_DFI_TYPE::DLE_DFI_TYPE_QEMPTY
* Please Place Description here.
*/
enum DLE_DFI_TYPE {
DLE_DFI_TYPE_FREEPG = 0,
DLE_DFI_TYPE_QUOTA = 1,
DLE_DFI_TYPE_PAGELLT = 2,
DLE_DFI_TYPE_PKTINFO = 3,
DLE_DFI_TYPE_PREPKTLLT = 4,
DLE_DFI_TYPE_NXTPKTLLT = 5,
DLE_DFI_TYPE_QLNKTBL = 6,
DLE_DFI_TYPE_QEMPTY = 7
};
enum DFI_TYPE_FREEPG_SEL {
DFI_TYPE_FREEPG_IDX = 0,
DFI_TYPE_FREEPG_PUBNUM
};
/*--------------------Define MACRO----------------------------------*/
/*--------------------Define Struct-----------------------------------*/
/**
* @struct dle_dfi_ctrl_t
* @brief dle_dfi_ctrl_t
*
* @var dle_dfi_ctrl_t::ctrl_type
* Please Place Description here.
* @var dle_dfi_ctrl_t::dfi_ctrl
* Please Place Description here.
* @var dle_dfi_ctrl_t::dfi_data
* Please Place Description here.
*/
struct dle_dfi_ctrl_t {
enum DLE_CTRL_TYPE type;
u32 target;
u32 addr;
u32 out_data;
};
/**
* @struct dle_dfi_freepg_t
* @brief dle_dfi_freepg_t
*
* @var dle_dfi_freepg_t::dle_type
* Please Place Description here.
* @var dle_dfi_freepg_t::free_headpg
* Please Place Description here.
* @var dle_dfi_freepg_t::free_tailpg
* Please Place Description here.
* @var dle_dfi_freepg_t::pub_pgnum
* Please Place Description here.
*/
struct dle_dfi_freepg_t {
// input parameter
enum DLE_CTRL_TYPE dle_type;
// output parameter
u16 free_headpg;
u16 free_tailpg;
u16 pub_pgnum;
};
/**
* @struct dle_dfi_quota_t
* @brief dle_dfi_quota_t
*
* @var dle_dfi_quota_t::dle_type
* Please Place Description here.
* @var dle_dfi_quota_t::qtaid
* Please Place Description here.
* @var dle_dfi_quota_t::rsv_pgnum
* Please Place Description here.
* @var dle_dfi_quota_t::use_pgnum
* Please Place Description here.
*/
struct dle_dfi_quota_t {
// input parameter
enum DLE_CTRL_TYPE dle_type;
u32 qtaid;
// output parameter
u16 rsv_pgnum;
u16 use_pgnum;
};
/**
* @struct dle_dfi_qempty_t
* @brief dle_dfi_qempty_t
*
* @var dle_dfi_qempty_t::dle_type
* Please Place Description here.
* @var dle_dfi_qempty_t::grpsel
* Please Place Description here.
* @var dle_dfi_qempty_t::qempty
* Please Place Description here.
*/
struct dle_dfi_qempty_t {
// input parameter
enum DLE_CTRL_TYPE dle_type;
u32 grpsel;
// output parameter
u32 qempty;
};
/**
* @struct dle_size_t
* @brief dle_size_t
*
* @var dle_size_t::pge_size
* Please Place Description here.
* @var dle_size_t::lnk_pge_num
* Please Place Description here.
* @var dle_size_t::unlnk_pge_num
* Please Place Description here.
*/
struct dle_size_t {
u16 pge_size;
u16 lnk_pge_num;
u16 unlnk_pge_num;
};
/**
* @struct wde_quota_t
* @brief wde_quota_t
*
* @var wde_quota_t::hif
* Please Place Description here.
* @var wde_quota_t::wcpu
* Please Place Description here.
* @var wde_quota_t::pkt_in
* Please Place Description here.
* @var wde_quota_t::cpu_io
* Please Place Description here.
*/
struct wde_quota_t {
u16 hif;
u16 wcpu;
u16 pkt_in;
u16 cpu_io;
};
/**
* @struct ple_quota_t
* @brief ple_quota_t
*
* @var ple_quota_t::cma0_tx
* Please Place Description here.
* @var ple_quota_t::cma1_tx
* Please Place Description here.
* @var ple_quota_t::c2h
* Please Place Description here.
* @var ple_quota_t::h2c
* Please Place Description here.
* @var ple_quota_t::wcpu
* Please Place Description here.
* @var ple_quota_t::mpdu_proc
* Please Place Description here.
* @var ple_quota_t::cma0_dma
* Please Place Description here.
* @var ple_quota_t::cma1_dma
* Please Place Description here.
* @var ple_quota_t::bb_rpt
* Please Place Description here.
* @var ple_quota_t::wd_rel
* Please Place Description here.
* @var ple_quota_t::cpu_io
* Please Place Description here.
* @var ple_quota_t::tx_rpt
* Please Place Description here.
*/
struct ple_quota_t {
u16 cma0_tx;
u16 cma1_tx;
u16 c2h;
u16 h2c;
u16 wcpu;
u16 mpdu_proc;
u16 cma0_dma;
u16 cma1_dma;
u16 bb_rpt;
u16 wd_rel;
u16 cpu_io;
u16 tx_rpt;
};
/**
* @struct dle_mem_t
* @brief dle_mem_t
*
* @var dle_mem_t::mode
* Please Place Description here.
* @var dle_mem_t::wde_size
* Please Place Description here.
* @var dle_mem_t::ple_size
* Please Place Description here.
* @var dle_mem_t::wde_min_qt
* Please Place Description here.
* @var dle_mem_t::wde_max_qt
* Please Place Description here.
* @var dle_mem_t::ple_min_qt
* Please Place Description here.
* @var dle_mem_t::ple_max_qt
* Please Place Description here.
*/
struct dle_mem_t {
enum mac_ax_qta_mode mode;
struct dle_size_t *wde_size;
struct dle_size_t *ple_size;
struct wde_quota_t *wde_min_qt;
struct wde_quota_t *wde_max_qt;
struct ple_quota_t *ple_min_qt;
struct ple_quota_t *ple_max_qt;
};
/*--------------------Export global variable----------------------------*/
/*--------------------Function declaration-----------------------------*/
u32 dle_dfi_ctrl(struct mac_ax_adapter *adapter, struct dle_dfi_ctrl_t *ctrl_p);
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_dfi_freepg
*
* @param *adapter
* @param *freepg
* @return Please Place Description here.
* @retval u32
*/
u32 dle_dfi_freepg(struct mac_ax_adapter *adapter,
struct dle_dfi_freepg_t *freepg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_dfi_quota
*
* @param *adapter
* @param *quota
* @return Please Place Description here.
* @retval u32
*/
u32 dle_dfi_quota(struct mac_ax_adapter *adapter,
struct dle_dfi_quota_t *quota);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_dfi_qempty
*
* @param *adapter
* @param *qempty
* @return Please Place Description here.
* @retval u32
*/
u32 dle_dfi_qempty(struct mac_ax_adapter *adapter,
struct dle_dfi_qempty_t *qempty);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief mac_chk_allq_empty
*
* @param *adapter
* @param *empty
* @return Please Place Description here.
* @retval u32
*/
u32 mac_chk_allq_empty(struct mac_ax_adapter *adapter, u8 *empty);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_quota_change
*
* @param *adapter
* @param mode
* @return Please Place Description here.
* @retval u32
*/
u32 dle_quota_change(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_init
*
* @param *adapter
* @param mode
* @param ext_mode
* @return Please Place Description here.
* @retval u32
*/
u32 dle_init(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode,
enum mac_ax_qta_mode ext_mode);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_is_txq_empty
*
* @param *adapter
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 dle_is_txq_empty(struct mac_ax_adapter *adapter, u8 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief dle_is_rxq_empty
*
* @param *adapter
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 dle_is_rxq_empty(struct mac_ax_adapter *adapter, u8 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief mac_is_txq_empty
*
* @param *adapter
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_is_txq_empty(struct mac_ax_adapter *adapter,
struct mac_ax_tx_queue_empty *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief mac_is_rxq_empty
*
* @param *adapter
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_is_rxq_empty(struct mac_ax_adapter *adapter,
struct mac_ax_rx_queue_empty *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief is_qta_dbcc
*
* @param *adapter
* @param mode
* @param *is_dbcc
* @return Please Place Description here.
* @retval u32
*/
u32 is_qta_dbcc(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode,
u8 *is_dbcc);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup DLE
* @{
*/
/**
* @brief is_qta_poh
*
* @param *adapter
* @param mode
* @param *is_poh
* @return Please Place Description here.
* @retval u32
*/
u8 is_curr_dbcc(struct mac_ax_adapter *adapter);
u32 is_qta_poh(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode,
u8 *is_poh);
/**
* @}
* @}
*/
u32 _patch_redu_rx_qta(struct mac_ax_adapter *adapter);
u32 _patch_restr_rx_qta(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/dle.h
|
C
|
agpl-3.0
| 14,647
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "efuse.h"
static struct mac_efuse_tbl efuse_tbl;
static struct mac_bank_efuse_info bank_efuse_info;
u16 efuse_ctrl = R_AX_EFUSE_CTRL;
u16 read_efuse_cnt = EFUSE_WAIT_CNT;
bool OTP_test;
enum rtw_dv_sel dv_sel = DDV;
static u32 efuse_map_init(struct mac_ax_adapter *adapter,
enum efuse_map_sel map_sel);
static u32 efuse_fwcmd_ck(struct mac_ax_adapter *adapter);
static u32 efuse_proc_ck(struct mac_ax_adapter *adapter);
static u32 cnv_efuse_state(struct mac_ax_adapter *adapter, u8 dest_state);
static u32 switch_efuse_bank(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_bank bank);
static u32 proc_dump_efuse(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg);
static u32 read_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size,
u8 *map);
static u32 write_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u8 value);
static u32 cmp_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u16 val);
static u32 eeprom_parser(struct mac_ax_adapter *adapter, u8 *phy_map,
u8 *log_map, enum mac_ax_efuse_parser_cfg cfg);
static u32 read_log_efuse_map(struct mac_ax_adapter *adapter, u8 *map,
u32 log_efuse_size);
static u32 proc_pg_efuse_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg);
static u32 dump_efuse_drv(struct mac_ax_adapter *adapter);
static u32 dump_efuse_fw(struct mac_ax_adapter *adapter);
static u32 proc_write_log_efuse(struct mac_ax_adapter *adapter, u32 offset,
u8 value);
static u32 read_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size,
u8 *map);
static u32 update_eeprom_mask(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
u8 *updated_mask, bool pg_sim);
static u32 check_efuse_enough(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
u8 *updated_mask);
static u32 proc_pg_efuse(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 word_en,
u8 pre_word_en, u32 eeprom_offset, bool pg_sim);
static u32 program_efuse(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *updated_mask,
bool pg_sim);
static void mask_eeprom(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
static u32 query_status_map(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_feature_id feature_id,
u8 *map, bool is_limit);
static u32 adjust_mask(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
static u32 compare_info_length(enum mac_ax_intf intf,
enum rtw_efuse_info id, u32 length);
static u32 set_check_sum_val(struct mac_ax_adapter *adapter,
u8 *map, u16 value);
static void cal_check_sum(struct mac_ax_adapter *adapter,
u16 *chksum);
static u32 compare_version(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u32 ver_len);
static void add_dummy_read(struct mac_ax_adapter *adapter);
static void enable_OTP_burst_mode(struct mac_ax_adapter *adapter,
bool enable);
static void enable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter,
bool is_write);
static void disable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter,
bool is_write);
static u32 enable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter,
bool is_write);
static u32 disable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter,
bool is_write);
static u32 read_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset, u32 size,
u8 *map);
static u32 write_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset,
u8 value);
static void switch_dv(struct mac_ax_adapter *adapter, enum rtw_dv_sel);
u32 mac_dump_efuse_map_wl_plus(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map)
{
u32 ret = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = hw_info->chip_id;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_dump_efuse_map_wl(adapter, cfg, efuse_map);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
ret = mac_dump_efuse_map_wl(adapter, cfg, efuse_map);
if (ret)
return ret;
switch_dv(adapter, DAV);
ret = mac_dump_efuse_map_wl(adapter, MAC_AX_EFUSE_R_DRV,
efuse_map + hw_info->efuse_size);
switch_dv(adapter, DDV);
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_dump_efuse_map_wl(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map)
{
u32 ret, stat;
#if 0
if (cfg == MAC_AX_EFUSE_R_FW ||
(cfg == MAC_AX_EFUSE_R_AUTO &&
adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY))
return MACNOITEM;
#else
if (cfg == MAC_AX_EFUSE_R_FW &&
adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) // no fw file
return MACNOFW;
#endif
PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
if (dv_sel == DAV)
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV);
else
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
if (ret != 0)
return ret;
ret = proc_dump_efuse(adapter, cfg);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]dump efuse!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
query_status_map(adapter, MAC_AX_DUMP_PHYSICAL_EFUSE, efuse_map, 0);
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_dump_efuse_map_bt(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map)
{
u32 ret, stat;
#if 0
if (cfg == MAC_AX_EFUSE_R_FW ||
(cfg == MAC_AX_EFUSE_R_AUTO &&
adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY))
return MACNOITEM;
#else
if (cfg == MAC_AX_EFUSE_R_FW &&
adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) // no fw file
return MACNOFW;
#endif
PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT);
if (ret != 0)
return ret;
ret = proc_dump_efuse(adapter, cfg);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]dump efuse!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
query_status_map(adapter, MAC_AX_DUMP_PHYSICAL_EFUSE, efuse_map, 0);
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_write_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val,
enum mac_ax_efuse_bank bank)
{
u32 ret = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = hw_info->chip_id;
u32 efuse_size = hw_info->wl_efuse_size;
switch (bank) {
case MAC_AX_EFUSE_BANK_WIFI:
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_write_efuse(adapter, addr, val, bank);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
if (addr < efuse_size) {
ret = mac_write_efuse(adapter, addr, val, bank);
} else {
switch_dv(adapter, DAV);
ret = mac_write_efuse(adapter, addr -
efuse_size, val, bank);
switch_dv(adapter, DDV);
}
break;
default:
break;
}
break;
case MAC_AX_EFUSE_BANK_BT:
ret = mac_write_efuse(adapter, addr, val, bank);
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_write_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val,
enum mac_ax_efuse_bank bank)
{
u32 ret, stat, efuse_size = 0;
if (bank == MAC_AX_EFUSE_BANK_WIFI) {
if (OTP_test)
efuse_size = OTP_PHY_SIZE;
else
efuse_size = adapter->hw_info->wl_efuse_size;
} else if (bank == MAC_AX_EFUSE_BANK_BT) {
efuse_size = adapter->hw_info->bt_efuse_size;
} else {
return MACEFUSEBANK;
}
if (addr >= efuse_size) {
PLTFM_MSG_ERR("[ERR]Offset is too large\n");
return MACEFUSESIZE;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, bank);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
enable_efuse_sw_pwr_cut(adapter, 1);
ret = write_hw_efuse(adapter, addr, val);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write physical efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
disable_efuse_sw_pwr_cut(adapter, 1);
if (bank == MAC_AX_EFUSE_BANK_BT) {
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return ret;
}
u32 mac_read_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val, enum mac_ax_efuse_bank bank)
{
u32 ret = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = hw_info->chip_id;
u32 efuse_size = hw_info->wl_efuse_size;
u32 size1, size2;
switch (bank) {
case MAC_AX_EFUSE_BANK_WIFI:
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_read_efuse(adapter, addr, size, val, bank);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
if (addr < efuse_size && addr + size <= efuse_size) {
ret = mac_read_efuse(adapter, addr, size,
val, bank);
} else if (addr >= efuse_size) {
switch_dv(adapter, DAV);
ret = mac_read_efuse(adapter, addr - efuse_size,
size, val, bank);
switch_dv(adapter, DDV);
} else if (addr < efuse_size &&
addr + size > efuse_size) {
size1 = efuse_size - addr;
size2 = addr + size - efuse_size;
ret = mac_read_efuse(adapter, addr, size1,
val, bank);
if (ret)
return ret;
switch_dv(adapter, DAV);
ret = mac_read_efuse(adapter, 0, size2,
val + size1, bank);
switch_dv(adapter, DDV);
}
if (ret)
return ret;
break;
default:
break;
}
break;
case MAC_AX_EFUSE_BANK_BT:
ret = mac_read_efuse(adapter, addr, size, val, bank);
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_read_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size, u8 *val,
enum mac_ax_efuse_bank bank)
{
u32 ret, stat, efuse_size = 0;
if (bank == MAC_AX_EFUSE_BANK_WIFI) {
if (OTP_test)
efuse_size = OTP_PHY_SIZE;
else
efuse_size = adapter->hw_info->wl_efuse_size;
} else if (bank == MAC_AX_EFUSE_BANK_BT) {
efuse_size = adapter->hw_info->bt_efuse_size;
} else {
return MACEFUSEBANK;
}
if (addr >= efuse_size || addr + size > efuse_size) {
PLTFM_MSG_ERR("[ERR] Wrong efuse index\n");
return MACEFUSESIZE;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, bank);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = read_hw_efuse(adapter, addr, size, val);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]read hw efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
if (bank == MAC_AX_EFUSE_BANK_BT) {
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_get_efuse_avl_size(struct mac_ax_adapter *adapter, u32 *size)
{
u32 ret;
u8 *map;
u32 efuse_size = adapter->hw_info->log_efuse_size;
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
ret = mac_dump_log_efuse(adapter, MAC_AX_EFUSE_PARSER_MAP,
MAC_AX_EFUSE_R_AUTO, map, 0);
PLTFM_FREE(map, efuse_size);
if (ret != 0)
return ret;
*size = adapter->hw_info->efuse_size - efuse_param->efuse_end;
return MACSUCCESS;
}
u32 mac_get_efuse_avl_size_bt(struct mac_ax_adapter *adapter, u32 *size)
{
u32 ret;
u8 *map;
u32 efuse_size = adapter->hw_info->bt_log_efuse_size;
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
ret = mac_dump_log_efuse_bt(adapter, MAC_AX_EFUSE_PARSER_MAP,
MAC_AX_EFUSE_R_DRV, map);
PLTFM_FREE(map, efuse_size);
if (ret != 0)
return ret;
*size = adapter->hw_info->bt_efuse_size - efuse_param->bt_efuse_end;
return MACSUCCESS;
}
u32 mac_dump_log_efuse_plus(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map, bool is_limit)
{
u32 ret = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = hw_info->chip_id;
enum mac_ax_intf intf = adapter->hw_info->intf;
u32 map_size = hw_info->log_efuse_size;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_dump_log_efuse(adapter, parser_cfg, cfg,
efuse_map, is_limit);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
ret = mac_dump_log_efuse(adapter, parser_cfg, cfg,
efuse_map, is_limit);
if (ret)
return ret;
switch_dv(adapter, DAV);
if (is_limit) {
switch (intf) {
case MAC_AX_INTF_PCIE:
map_size = hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
map_size = hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
map_size = hw_info->limit_efuse_size_sdio;
break;
default:
break;
}
}
ret = mac_dump_log_efuse(adapter, parser_cfg,
MAC_AX_EFUSE_R_DRV, efuse_map +
map_size, 0);
switch_dv(adapter, DDV);
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_dump_log_efuse(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map, bool is_limit)
{
u8 *map = NULL;
u32 ret, stat;
u32 efuse_size;
#if 0
if (cfg == MAC_AX_EFUSE_R_FW ||
(cfg == MAC_AX_EFUSE_R_AUTO &&
adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY))
return MACNOITEM;
#else
if (cfg == MAC_AX_EFUSE_R_FW &&
adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
#endif
PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
efuse_size = *bank_efuse_info.log_map_size;
if (dv_sel == DAV) {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV);
if (ret != 0)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV);
} else {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG);
if (ret != 0)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
}
if (ret)
return ret;
if (*bank_efuse_info.log_map_valid == 0) {
ret = proc_dump_efuse(adapter, cfg);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]dump efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
if (*bank_efuse_info.phy_map_valid == 1) {
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
stat = cnv_efuse_state(adapter,
MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return MACBUFALLOC;
}
ret = eeprom_parser(adapter, *bank_efuse_info.phy_map,
map, parser_cfg);
if (ret != 0) {
PLTFM_FREE(map, efuse_size);
stat = cnv_efuse_state(adapter,
MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(*bank_efuse_info.log_map, map,
efuse_size);
*bank_efuse_info.log_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(map, efuse_size);
}
}
query_status_map(adapter, MAC_AX_DUMP_LOGICAL_EFUSE,
efuse_map, is_limit);
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_read_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val)
{
u32 ret = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = hw_info->chip_id;
u32 efuse_size = hw_info->log_efuse_size;
u32 size1, size2;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_read_log_efuse(adapter, addr, size, val);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
if (addr < efuse_size && addr + size <= efuse_size) {
ret = mac_read_log_efuse(adapter, addr, size, val);
} else if (addr >= efuse_size) {
switch_dv(adapter, DAV);
ret = mac_read_log_efuse(adapter, addr - efuse_size,
size, val);
switch_dv(adapter, DDV);
} else if (addr < efuse_size && addr + size > efuse_size) {
size1 = efuse_size - addr;
size2 = addr + size - efuse_size;
ret = mac_read_log_efuse(adapter, addr, size1, val);
if (ret)
return ret;
switch_dv(adapter, DAV);
ret = mac_read_log_efuse(adapter, 0, size2,
val + size1);
switch_dv(adapter, DDV);
}
if (ret)
return ret;
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_read_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val)
{
u8 *map = NULL;
u32 ret = 0, stat;
u32 efuse_size;
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
efuse_size = *bank_efuse_info.log_map_size;
if (addr >= efuse_size || addr + size > efuse_size) {
PLTFM_MSG_ERR("[ERR] Wrong efuse index\n");
return MACEFUSESIZE;
}
if (dv_sel == DAV) {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV);
} else {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG);
}
if (ret)
return ret;
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return MACBUFALLOC;
}
ret = read_log_efuse_map(adapter, map, efuse_size);
if (ret != 0) {
PLTFM_FREE(map, efuse_size);
PLTFM_MSG_ERR("[ERR]read logical efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(val, map + addr, size);
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(map, efuse_size);
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return MACSUCCESS;
}
u32 mac_write_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val)
{
u32 ret = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = hw_info->chip_id;
u32 efuse_size = hw_info->log_efuse_size;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_write_log_efuse(adapter, addr, val);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
if (addr < efuse_size) {
ret = mac_write_log_efuse(adapter, addr, val);
} else {
switch_dv(adapter, DAV);
ret = mac_write_log_efuse(adapter,
addr - efuse_size, val);
switch_dv(adapter, DDV);
}
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_write_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val)
{
u32 ret, stat;
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
if (addr >= *bank_efuse_info.log_map_size) {
PLTFM_MSG_ERR("[ERR]addr is too large\n");
return MACEFUSESIZE;
}
if (dv_sel == DAV) {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV);
} else {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG);
}
if (ret)
return ret;
ret = proc_write_log_efuse(adapter, addr, val);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write logical efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_dump_log_efuse_bt(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map)
{
u8 *map = NULL;
u32 ret, stat;
u32 efuse_size = adapter->hw_info->bt_log_efuse_size;
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
#if 0
if (cfg == MAC_AX_EFUSE_R_FW ||
(cfg == MAC_AX_EFUSE_R_AUTO &&
adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY))
return MACNOITEM;
#else
if (cfg == MAC_AX_EFUSE_R_FW &&
adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
#endif
PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_BT);
if (ret != 0)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT);
if (ret != 0)
return ret;
if (efuse_param->bt_log_efuse_map_valid == 0) {
ret = proc_dump_efuse(adapter, cfg);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]dump efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
if (efuse_param->bt_efuse_map_valid == 1) {
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
stat = cnv_efuse_state(adapter,
MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return MACBUFALLOC;
}
ret = eeprom_parser(adapter, efuse_param->bt_efuse_map,
map, parser_cfg);
if (ret != 0) {
PLTFM_FREE(map, efuse_size);
stat = cnv_efuse_state(adapter,
MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(efuse_param->bt_log_efuse_map, map,
efuse_size);
efuse_param->bt_log_efuse_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(map, efuse_size);
}
}
query_status_map(adapter, MAC_AX_DUMP_LOGICAL_EFUSE, efuse_map, 0);
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_read_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val)
{
u8 *map = NULL;
u32 ret, stat;
u32 efuse_size = adapter->hw_info->bt_log_efuse_size;
if (addr >= efuse_size || addr + size > efuse_size) {
PLTFM_MSG_ERR("[ERR] Wrong efuse index\n");
return MACEFUSESIZE;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_BT);
if (ret)
return ret;
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return MACBUFALLOC;
}
PLTFM_MEMSET(map, 0xFF, efuse_size);
ret = read_log_efuse_map(adapter, map, efuse_size);
if (ret != 0) {
PLTFM_FREE(map, efuse_size);
PLTFM_MSG_ERR("[ERR]read logical efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(val, map + addr, size);
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(map, efuse_size);
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return MACSUCCESS;
}
u32 mac_write_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u8 val)
{
u32 ret, stat;
if (addr >= adapter->hw_info->log_efuse_size) {
PLTFM_MSG_ERR("[ERR]addr is too large\n");
return MACEFUSESIZE;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_LOG_MAP);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_BT);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_BT);
if (ret)
return ret;
ret = proc_write_log_efuse(adapter, addr, val);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write logical efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_pg_efuse_by_map_plus(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg,
bool part, bool is_limit)
{
u8 chip_id = adapter->hw_info->chip_id;
u32 ret;
struct mac_ax_pg_efuse_info info_DAV;
u32 ver_len = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
enum mac_ax_intf intf = adapter->hw_info->intf;
u32 map_size = adapter->hw_info->log_efuse_size;
//u8 *phy_map = NULL;
ret = mac_get_hw_value(adapter,
MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len);
if (ret)
return ret;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_pg_efuse_by_map(adapter, info, cfg, part, is_limit);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
/* cut map */
if (is_limit) {
switch (intf) {
case MAC_AX_INTF_PCIE:
map_size = hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
map_size = hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
map_size = hw_info->limit_efuse_size_sdio;
break;
default:
break;
}
}
info_DAV.efuse_map_size = hw_info->dav_log_efuse_size;
info_DAV.efuse_mask_size = hw_info->dav_log_efuse_size >> 4;
info_DAV.efuse_map = (u8 *)PLTFM_MALLOC(info_DAV.efuse_map_size + ver_len);
if (!info_DAV.efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
info_DAV.efuse_mask = (u8 *)PLTFM_MALLOC(info_DAV.efuse_mask_size + ver_len);
if (!info_DAV.efuse_mask) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
PLTFM_MEMCPY(info_DAV.efuse_map, info->efuse_map + map_size,
info_DAV.efuse_map_size + ver_len);
PLTFM_MEMCPY(info_DAV.efuse_mask,
info->efuse_mask + (map_size >> 4),
info_DAV.efuse_mask_size + ver_len);
info->efuse_map_size -= info_DAV.efuse_map_size;
info->efuse_mask_size -= info_DAV.efuse_mask_size;
PLTFM_MEMCPY(info->efuse_map + map_size, info->efuse_map +
map_size + info_DAV.efuse_map_size, ver_len);
PLTFM_MEMCPY(info->efuse_mask + (map_size >> 4),
info->efuse_mask + (map_size >> 4) +
info_DAV.efuse_mask_size, ver_len);
ret = mac_pg_efuse_by_map(adapter, info, cfg, part, is_limit);
if (ret)
return ret;
switch_dv(adapter, DAV);
ret = mac_pg_efuse_by_map(adapter,
&info_DAV, cfg, part, 0);
//phy_map = (u8 *)PLTFM_MALLOC(hw_info->wl_efuse_size_DAV);
//if (!phy_map) {
// PLTFM_MSG_ERR("[ERR]malloc map\n");
// return MACBUFALLOC;
//}
//PLTFM_MEMSET(phy_map, 0xFF, hw_info->wl_efuse_size_DAV);
//ret = mac_pg_simulator(adapter, &info_DAV, phy_map);
switch_dv(adapter, DDV);
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_pg_efuse_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg,
bool part, bool is_limit)
{
u32 ret, stat;
enum mac_ax_intf intf = adapter->hw_info->intf;
u32 map_size = adapter->hw_info->log_efuse_size;
u32 ver_len = 0;
if (is_limit) {
switch (intf) {
case MAC_AX_INTF_PCIE:
map_size = adapter->hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
map_size = adapter->hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
map_size = adapter->hw_info->limit_efuse_size_sdio;
break;
default:
break;
}
}
if (dv_sel == DAV)
map_size = adapter->hw_info->dav_log_efuse_size;
if (info->efuse_map_size != map_size) {
PLTFM_MSG_ERR("[ERR]map size error\n");
return MACEFUSESIZE;
}
if ((info->efuse_map_size & 0xF) > 0) {
PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
return MACEFUSESIZE;
}
if (info->efuse_mask_size != info->efuse_map_size >> 4) {
PLTFM_MSG_ERR("[ERR]mask size error\n");
return MACEFUSESIZE;
}
if (!info->efuse_map) {
PLTFM_MSG_ERR("[ERR]map is NULL\n");
return MACNPTR;
}
if (!info->efuse_mask) {
PLTFM_MSG_ERR("[ERR]mask is NULL\n");
return MACNPTR;
}
ret = mac_get_hw_value(adapter,
MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len);
if (ret)
return ret;
ret = compare_version(adapter, info, ver_len);
if (ret != 0)
return ret;
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
if (dv_sel == DAV) {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV);
} else {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG);
}
if (ret)
return ret;
if (part)
ret = adjust_mask(adapter, info);
if (ret != 0) {
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = proc_pg_efuse_by_map(adapter, info, cfg);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]pg efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_pg_efuse_by_map_bt(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg)
{
u32 ret, stat;
if (info->efuse_map_size != adapter->hw_info->bt_log_efuse_size) {
PLTFM_MSG_ERR("[ERR]map size error\n");
return MACEFUSESIZE;
}
if ((info->efuse_map_size & 0xF) > 0) {
PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
return MACEFUSESIZE;
}
if (info->efuse_mask_size != info->efuse_map_size >> 4) {
PLTFM_MSG_ERR("[ERR]mask size error\n");
return MACEFUSESIZE;
}
if (!info->efuse_map) {
PLTFM_MSG_ERR("[ERR]map is NULL\n");
return MACNPTR;
}
if (!info->efuse_mask) {
PLTFM_MSG_ERR("[ERR]mask is NULL\n");
return MACNPTR;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_BT);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = proc_pg_efuse_by_map(adapter, info, cfg);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]pg efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_mask_log_efuse(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info)
{
if (info->efuse_map_size != adapter->hw_info->log_efuse_size) {
PLTFM_MSG_ERR("[ERR]map size error\n");
return MACEFUSESIZE;
}
if ((info->efuse_map_size & 0xF) > 0) {
PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
return MACEFUSESIZE;
}
if (info->efuse_mask_size != info->efuse_map_size >> 4) {
PLTFM_MSG_ERR("[ERR]mask size error\n");
return MACEFUSESIZE;
}
if (!info->efuse_map) {
PLTFM_MSG_ERR("[ERR]map is NULL\n");
return MACNPTR;
}
if (!info->efuse_mask) {
PLTFM_MSG_ERR("[ERR]mask is NULL\n");
return MACNPTR;
}
mask_eeprom(adapter, info);
return MACSUCCESS;
}
u32 mac_pg_sec_data_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info)
{
u32 ret, stat;
u32 addr, efuse_size, sec_data_size;
u8 *map_pg;
u32 mac_addr_size = 6;
/*Soar TBD add MAC address PG*/
map_pg = info->efuse_map;
efuse_size = adapter->hw_info->efuse_size;
sec_data_size = adapter->hw_info->sec_data_efuse_size;
if (info->efuse_map_size != adapter->hw_info->sec_data_efuse_size) {
PLTFM_MSG_ERR("[ERR]map size error\n");
return MACEFUSESIZE;
}
if (!info->efuse_map) {
PLTFM_MSG_ERR("[ERR]map is NULL\n");
return MACNPTR;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
enable_efuse_sw_pwr_cut(adapter, 1);
for (addr = mac_addr_size; addr < sec_data_size; addr++) {
ret = write_hw_efuse(adapter, addr + efuse_size,
*(map_pg + addr));
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write physical efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
}
disable_efuse_sw_pwr_cut(adapter, 1);
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_cmp_sec_data_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info)
{
u32 ret, stat;
u32 addr, start_addr, sec_data_size;
u16 val16;
u8 *map_pg;
map_pg = info->efuse_map;
start_addr = adapter->hw_info->efuse_size;
sec_data_size = adapter->hw_info->sec_data_efuse_size;
if (info->efuse_map_size != adapter->hw_info->sec_data_efuse_size) {
PLTFM_MSG_ERR("[ERR]map size error\n");
return MACEFUSESIZE;
}
if (!info->efuse_map) {
PLTFM_MSG_ERR("[ERR]map is NULL\n");
return MACNPTR;
}
ret = efuse_proc_ck(adapter);
if (ret != 0)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
return ret;
}
for (addr = 0;
addr < sec_data_size; addr += 2) {
val16 = *(map_pg + addr) | (*(map_pg + addr + 1) << 8);
ret = cmp_hw_efuse(adapter, addr + start_addr, val16);
if (ret == MACEFUSECMP) {
*(map_pg + addr) = 0xFF;
*(map_pg + addr + 1) = 0xFF;
} else if (ret == MACEFUSEREAD) {
PLTFM_MSG_ERR("[ERR]compare hw efuse\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != 0)
return stat;
} else if (ret == 0) {
*(map_pg + addr) = 0x00;
*(map_pg + addr + 1) = 0x00;
}
}
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != 0)
return ret;
return MACSUCCESS;
}
u32 mac_get_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length,
u8 *autoload_status)
{
u32 offset = 0;
u32 ret;
enum mac_ax_intf intf = adapter->hw_info->intf;
u8 default_value = 0;
ret = compare_info_length(intf, id, length);
if (ret != 0)
return ret;
if (intf == MAC_AX_INTF_USB) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
offset = OFS_ADDR_AU;
default_value = VAL_ADDR_AU;
break;
case EFUSE_INFO_MAC_PID:
offset = OFS_PID_AU;
default_value = VAL_PID_AU;
break;
case EFUSE_INFO_MAC_VID:
offset = OFS_VID_AU;
default_value = VAL_VID_AU;
break;
default:
return MACNOITEM;
}
} else if (intf == MAC_AX_INTF_PCIE) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
offset = OFS_ADDR_AE;
default_value = VAL_ADDR_AE;
break;
case EFUSE_INFO_MAC_DID:
offset = OFS_DID_AE;
default_value = VAL_DID_AE;
break;
case EFUSE_INFO_MAC_VID:
offset = OFS_VID_AE;
default_value = VAL_VID_AE;
break;
case EFUSE_INFO_MAC_SVID:
offset = OFS_SVID_AE;
default_value = VAL_SVID_AE;
break;
case EFUSE_INFO_MAC_SMID:
offset = OFS_SMID_AE;
default_value = VAL_SMID_AE;
break;
default:
return MACNOITEM;
}
} else if (intf == MAC_AX_INTF_SDIO) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
offset = OFS_ADDR_AS;
default_value = VAL_ADDR_AS;
break;
default:
return MACNOITEM;
}
}
if (*autoload_status == 0)
PLTFM_MEMCPY(value, &default_value, 1);
else
PLTFM_MEMCPY(value, efuse_map + offset, length);
return MACSUCCESS;
}
u32 mac_set_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length)
{
u32 offset = 0;
u32 ret;
enum mac_ax_intf intf = adapter->hw_info->intf;
ret = compare_info_length(intf, id, length);
if (ret != 0)
return ret;
if (intf == MAC_AX_INTF_USB) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
offset = OFS_ADDR_AU;
break;
case EFUSE_INFO_MAC_PID:
offset = OFS_PID_AU;
break;
case EFUSE_INFO_MAC_VID:
offset = OFS_VID_AU;
break;
default:
return MACNOITEM;
}
} else if (intf == MAC_AX_INTF_PCIE) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
offset = OFS_ADDR_AE;
break;
case EFUSE_INFO_MAC_DID:
offset = OFS_DID_AE;
break;
case EFUSE_INFO_MAC_VID:
offset = OFS_VID_AE;
break;
case EFUSE_INFO_MAC_SVID:
offset = OFS_SVID_AE;
break;
case EFUSE_INFO_MAC_SMID:
offset = OFS_SMID_AE;
break;
default:
return MACNOITEM;
}
} else if (intf == MAC_AX_INTF_SDIO) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
offset = OFS_ADDR_AS;
break;
default:
return MACNOITEM;
}
}
PLTFM_MEMCPY(efuse_map + offset, value, length);
return MACSUCCESS;
}
u32 mac_read_hidden_rpt(struct mac_ax_adapter *adapter,
struct mac_defeature_value *rpt)
{
#if 0
return MACNOITEM;
#else
u32 ret, stat;
struct mac_ax_h2creg_info h2c;
struct mac_ax_c2hreg_poll c2h;
struct fwcmd_c2hreg *c2h_content;
ret = efuse_proc_ck(adapter);
if (ret != MACSUCCESS)
return ret;
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_PHY);
if (ret != MACSUCCESS)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat != MACSUCCESS)
return stat;
return ret;
}
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
if (ret != MACSUCCESS)
return ret;
h2c.id = FWCMD_H2CREG_FUNC_HIDDEN_GET;
h2c.content_len = sizeof(struct mac_efuse_hidden_h2creg);
c2h.polling_id = FWCMD_C2HREG_FUNC_EFUSE_HIDDEN;
c2h.retry_cnt = EFUSE_C2HREG_WAIT_CNT;
c2h.retry_wait_us = EFUSE_C2HREG_RETRY_WAIT_US;
ret = proc_msg_reg(adapter, &h2c, &c2h);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]read hidden rpt proc msg reg %d\n", ret);
stat = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (stat)
return stat;
return ret;
}
c2h_content = &c2h.c2hreg_cont.c2h_content;
rpt->rx_spatial_stream =
GET_FIELD(c2h_content->dword0, FWCMD_C2HREG_EFUSE_HIDDEN_RX_NSS);
rpt->bandwidth =
GET_FIELD(c2h_content->dword0, FWCMD_C2HREG_EFUSE_HIDDEN_BW);
rpt->tx_spatial_stream =
GET_FIELD(c2h_content->dword1, FWCMD_C2HREG_EFUSE_HIDDEN_TX_NSS);
rpt->protocol_80211 =
GET_FIELD(c2h_content->dword1, FWCMD_C2HREG_EFUSE_HIDDEN_PROT80211);
rpt->NIC_router =
GET_FIELD(c2h_content->dword1, FWCMD_C2HREG_EFUSE_HIDDEN_NIC_ROUTER);
rpt->wl_func_support =
GET_FIELD(c2h_content->dword1,
FWCMD_C2HREG_EFUSE_HIDDEN_WL_FUNC_SUPPORT);
rpt->hw_special_type =
GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_EFUSE_HIDDEN_HW_SPECIAL_TYPE);
rpt->uuid =
GET_FIELD(c2h_content->dword3,
FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_3) << 24 |
GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_2) << 16 |
GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_1) << 8 |
GET_FIELD(c2h_content->dword2,
FWCMD_C2HREG_EFUSE_HIDDEN_UUID_BYTE_0);
ret = cnv_efuse_state(adapter, MAC_AX_EFUSE_IDLE);
if (ret != MACSUCCESS)
return ret;
return MACSUCCESS;
#endif
}
u32 mac_check_efuse_autoload(struct mac_ax_adapter *adapter,
u8 *autoload_status)
{
#define AUTOLOAD_SUS 1
#define AUTOLOAD_FAIL 0
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (MAC_REG_R16(R_AX_SYS_EEPROM_CTRL) & B_AX_AUTOLOAD_SUS)
*autoload_status = AUTOLOAD_SUS;
else
*autoload_status = AUTOLOAD_FAIL;
return MACSUCCESS;
#undef AUTOLOAD_SUS
#undef AUTOLOAD_FAIL
}
u32 mac_pg_simulator_plus(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *phy_map)
{
u8 chip_id = adapter->hw_info->chip_id;
u32 ret;
struct mac_ax_pg_efuse_info info_dav;
u32 ver_len = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u32 map_size = hw_info->log_efuse_size;
ret = mac_get_hw_value(adapter,
MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len);
if (ret)
return ret;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
ret = mac_pg_simulator(adapter, info, phy_map);
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
/* cut log map */
info_dav.efuse_map_size = hw_info->dav_log_efuse_size;
info_dav.efuse_mask_size = hw_info->dav_log_efuse_size >> 4;
info_dav.efuse_map =
(u8 *)PLTFM_MALLOC(info_dav.efuse_map_size + ver_len);
if (!info_dav.efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
info_dav.efuse_mask =
(u8 *)PLTFM_MALLOC(info_dav.efuse_mask_size +
ver_len);
if (!info_dav.efuse_mask) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
PLTFM_MEMCPY(info_dav.efuse_map, info->efuse_map + map_size,
info_dav.efuse_map_size + ver_len);
PLTFM_MEMCPY(info_dav.efuse_mask,
info->efuse_mask + (map_size >> 4),
info_dav.efuse_mask_size + ver_len);
info->efuse_map_size -= info_dav.efuse_map_size;
info->efuse_mask_size -= info_dav.efuse_mask_size;
PLTFM_MEMCPY(info->efuse_map + map_size, info->efuse_map +
map_size + info_dav.efuse_map_size, ver_len);
PLTFM_MEMCPY(info->efuse_mask + (map_size >> 4),
info->efuse_mask + (map_size >> 4) +
info_dav.efuse_mask_size, ver_len);
ret = mac_pg_simulator(adapter, info, phy_map);
if (ret)
return ret;
switch_dv(adapter, DAV);
ret = mac_pg_simulator(adapter, &info_dav,
phy_map + hw_info->wl_efuse_size);
switch_dv(adapter, DDV);
PLTFM_MEMCPY(info->efuse_map + map_size, info_dav.efuse_map,
info_dav.efuse_map_size + ver_len);
break;
default:
break;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_pg_simulator(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *phy_map)
{
u8 *updated_mask;
u32 ret;
u32 mask_size;
u8 *log_efuse_map = NULL;
enum mac_ax_intf intf = adapter->hw_info->intf;
u32 map_size = adapter->hw_info->log_efuse_size;
u32 ver_len = 0;
if (info->efuse_map_size != adapter->hw_info->log_efuse_size) {
switch (intf) {
case MAC_AX_INTF_PCIE:
map_size = adapter->hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
map_size = adapter->hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
map_size = adapter->hw_info->limit_efuse_size_sdio;
break;
default:
break;
}
}
if (dv_sel == DAV)
map_size = adapter->hw_info->dav_log_efuse_size;
if (info->efuse_map_size != map_size) {
PLTFM_MSG_ERR("[ERR]map size error\n");
return MACEFUSESIZE;
}
mask_size = map_size >> 4;
ret = mac_get_hw_value(adapter,
MAC_AX_HW_GET_EFUSE_VERSION_SIZE, &ver_len);
if (ret)
return ret;
ret = compare_version(adapter, info, ver_len);
if (ret != 0)
return ret;
ret = switch_efuse_bank(adapter, MAC_AX_EFUSE_BANK_WIFI);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
return ret;
}
if (dv_sel == DAV) {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_DAV);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG_DAV);
} else {
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_PHY_WL);
if (ret)
return ret;
ret = efuse_map_init(adapter, EFUSE_MAP_SEL_LOG);
}
if (ret)
return ret;
ret = eeprom_parser(adapter, phy_map, *bank_efuse_info.log_map,
MAC_AX_EFUSE_PARSER_MAP);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]logical map parser\n");
return ret;
}
PLTFM_MEMCPY(*bank_efuse_info.phy_map, phy_map,
*bank_efuse_info.phy_map_size);
updated_mask = (u8 *)PLTFM_MALLOC(mask_size);
if (!updated_mask) {
PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
return MACBUFALLOC;
}
PLTFM_MEMSET(updated_mask, 0x00, mask_size);
ret = update_eeprom_mask(adapter, info, updated_mask, 1);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]update eeprom mask\n");
goto error;
}
ret = check_efuse_enough(adapter, info, updated_mask);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]chk efuse enough\n");
goto error;
}
ret = program_efuse(adapter, info, updated_mask, 1);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]pg efuse\n");
goto error;
}
PLTFM_FREE(updated_mask, mask_size);
PLTFM_MEMCPY(phy_map, *bank_efuse_info.phy_map,
*bank_efuse_info.phy_map_size);
ret = eeprom_parser(adapter, phy_map, info->efuse_map,
MAC_AX_EFUSE_PARSER_MAP);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]parser error\n");
PLTFM_FREE(log_efuse_map, map_size);
return ret;
}
/* For subsequent dump */
*bank_efuse_info.log_map_valid = 0;
*bank_efuse_info.phy_map_valid = 0;
return MACSUCCESS;
error:
PLTFM_FREE(updated_mask, mask_size);
return ret;
}
u32 mac_checksum_update(struct mac_ax_adapter *adapter)
{
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u32 log_efuse_size = hw_info->log_efuse_size;
u8 *map;
u16 chksum;
u32 ret;
map = (u8 *)PLTFM_MALLOC(log_efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
PLTFM_MEMSET(map, 0xFF, log_efuse_size);
ret = mac_dump_log_efuse(adapter, MAC_AX_EFUSE_PARSER_MAP,
MAC_AX_EFUSE_R_AUTO, map, 0);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]Dump log map\n");
goto error;
}
cal_check_sum(adapter, &chksum);
ret = set_check_sum_val(adapter, map, chksum);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write check sum\n");
goto error;
}
PLTFM_FREE(map, log_efuse_size);
return MACSUCCESS;
error:
PLTFM_FREE(map, log_efuse_size);
return ret;
}
u32 mac_checksum_rpt(struct mac_ax_adapter *adapter, u16 *chksum)
{
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u32 log_efuse_size = hw_info->log_efuse_size;
u8 *tmp;
u32 ret;
u16 real_chksum = 0;
/* Read chksum val */
tmp = (u8 *)PLTFM_MALLOC(sizeof(real_chksum));
if (!tmp) {
PLTFM_MSG_ERR("[ERR]malloc tmp\n");
return MACBUFALLOC;
}
ret = mac_read_log_efuse(adapter, chksum_offset_1, sizeof(real_chksum),
tmp);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]read log efuse\n");
PLTFM_FREE(tmp, sizeof(real_chksum));
return ret;
}
real_chksum = *(u16 *)tmp;
PLTFM_FREE(tmp, sizeof(real_chksum));
if (real_chksum == 0xFFFF)
return MACCHKSUMEMPTY;
/* Read log map*/
tmp = (u8 *)PLTFM_MALLOC(log_efuse_size);
if (!tmp) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
PLTFM_MEMSET(tmp, 0xFF, log_efuse_size);
ret = mac_read_log_efuse(adapter, 0, log_efuse_size, tmp);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]read log efuse\n");
PLTFM_FREE(tmp, log_efuse_size);
return ret;
}
PLTFM_FREE(tmp, log_efuse_size);
cal_check_sum(adapter, chksum);
if (*chksum != real_chksum)
return MACCHKSUMFAIL;
return MACSUCCESS;
}
u32 mac_disable_rf(struct mac_ax_adapter *adapter,
enum mac_ax_disable_rf_func func, enum mac_ax_net_type type)
{
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
struct fwcmd_disable_rf *write_ptr;
/* H2C */
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr));
if (!buf) {
h2cb_free(adapter, h2cb);
return MACNOBUF;
}
write_ptr = (struct fwcmd_disable_rf *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(func, FWCMD_H2C_DISABLE_RF_FUNC) |
SET_WORD(type, FWCMD_H2C_DISABLE_RF_NET_TYPE)
);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_DISABLE_RF,
0, 0);
if (ret) {
h2cb_free(adapter, h2cb);
return ret;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
h2cb_free(adapter, h2cb);
return ret;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
h2cb_free(adapter, h2cb);
return ret;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
}
u32 mac_check_OTP(struct mac_ax_adapter *adapter, u8 is_start)
{
#define is_read 0
#define secure 1
u32 ret;
u8 val8;
if (is_start == 1) {
enable_efuse_sw_pwr_cut(adapter, is_read);
mac_set_efuse_ctrl(adapter, secure);
read_efuse_cnt = CHK_OTP_WAIT_CNT;
ret = mac_read_efuse_plus(adapter, CHK_OTP_ADDR, 1, &val8,
MAC_AX_EFUSE_BANK_WIFI);
disable_efuse_sw_pwr_cut(adapter, is_read);
mac_set_efuse_ctrl(adapter, !secure);
read_efuse_cnt = EFUSE_WAIT_CNT;
}
return MACSUCCESS;
}
void mac_set_efuse_ctrl(struct mac_ax_adapter *adapter, u8 is_secure)
{
efuse_ctrl = is_secure ? R_AX_EFUSE_CTRL_S : R_AX_EFUSE_CTRL;
}
u32 mac_otp_test(struct mac_ax_adapter *adapter, bool is_OTP_test)
{
if (is_OTP_test)
OTP_test = 1;
else
OTP_test = 0;
return MACSUCCESS;
}
void cfg_efuse_auto_ck(struct mac_ax_adapter *adapter, u8 enable)
{
/*Soar TBD* move to set hw value */
#ifdef NEVER
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
adapter->efuse_param.auto_ck_en = enable;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
#endif /* NEVER */
}
u32 efuse_tbl_init(struct mac_ax_adapter *adapter)
{
PLTFM_MUTEX_INIT(&efuse_tbl.lock);
return MACSUCCESS;
}
u32 efuse_tbl_exit(struct mac_ax_adapter *adapter)
{
PLTFM_MUTEX_DEINIT(&efuse_tbl.lock);
return MACSUCCESS;
}
static u32 efuse_map_init(struct mac_ax_adapter *adapter,
enum efuse_map_sel map_sel)
{
u32 size;
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
switch (map_sel) {
case EFUSE_MAP_SEL_PHY_WL:
size = adapter->hw_info->efuse_size;
if (!efuse_param->efuse_map) {
efuse_param->efuse_map = (u8 *)PLTFM_MALLOC(size);
if (!efuse_param->efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
}
break;
case EFUSE_MAP_SEL_PHY_BT:
size = adapter->hw_info->bt_efuse_size;
if (!efuse_param->bt_efuse_map) {
efuse_param->bt_efuse_map = (u8 *)PLTFM_MALLOC(size);
if (!efuse_param->bt_efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
}
break;
case EFUSE_MAP_SEL_LOG:
size = adapter->hw_info->log_efuse_size;
if (!efuse_param->log_efuse_map) {
efuse_param->log_efuse_map = (u8 *)PLTFM_MALLOC(size);
if (!efuse_param->log_efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
}
break;
case EFUSE_MAP_SEL_LOG_BT:
size = adapter->hw_info->bt_log_efuse_size;
if (!efuse_param->bt_log_efuse_map) {
efuse_param->bt_log_efuse_map =
(u8 *)PLTFM_MALLOC(size);
if (!efuse_param->bt_log_efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
}
break;
case EFUSE_MAP_SEL_PHY_DAV:
size = adapter->hw_info->dav_efuse_size;
if (!efuse_param->dav_efuse_map) {
efuse_param->dav_efuse_map = (u8 *)PLTFM_MALLOC(size);
if (!efuse_param->dav_efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
}
break;
case EFUSE_MAP_SEL_LOG_DAV:
size = adapter->hw_info->dav_log_efuse_size;
if (!efuse_param->dav_log_efuse_map) {
efuse_param->dav_log_efuse_map =
(u8 *)PLTFM_MALLOC(size);
if (!efuse_param->dav_log_efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
}
break;
default:
break;
}
return MACSUCCESS;
}
static u32 efuse_fwcmd_ck(struct mac_ax_adapter *adapter)
{
/*Soar TBD*/
#ifdef NEVER
u32 ret;
ret = fwcmd_wq_idle(adapter,
SET_FWCMD_ID(FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
TBD,
TBD));
if (ret != 0) {
PLTFM_MSG_WARN("[WARN]H2C not idle(efuse)\n");
return ret;
}
#endif /* NEVER */
return MACSUCCESS;
}
static u32 efuse_proc_ck(struct mac_ax_adapter *adapter)
{
/*Soar TBD*/
#ifdef NEVER
u32 ret;
ret = efuse_fwcmd_ck(adapter);
if (ret != 0)
return ret;
#endif /* NEVER */
if (adapter->sm.efuse != MAC_AX_EFUSE_IDLE) {
PLTFM_MSG_WARN("[WARN]Proc not idle(efuse)\n");
return MACPROCBUSY;
}
if (adapter->sm.pwr != MAC_AX_PWR_ON)
PLTFM_MSG_ERR("[ERR]Access efuse in suspend\n");
return MACSUCCESS;
}
static u32 cnv_efuse_state(struct mac_ax_adapter *adapter, u8 dest_state)
{
if (adapter->sm.efuse >= MAC_AX_EFUSE_MAX)
return MACPROCERR;
if (adapter->sm.efuse == dest_state)
return MACPROCERR;
if (dest_state != MAC_AX_EFUSE_IDLE) {
if (adapter->sm.efuse != MAC_AX_EFUSE_IDLE)
return MACPROCERR;
}
adapter->sm.efuse = dest_state;
return MACSUCCESS;
}
static u32 switch_efuse_bank(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_bank bank)
{
u8 reg_value;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u8 chip_id = adapter->hw_info->chip_id;
switch (chip_id) {
case MAC_AX_CHIP_ID_8852A:
if (bank == MAC_AX_EFUSE_BANK_BT) {
/* check bt state */
MAC_REG_W8(R_AX_SYSON_FSM_MON + 3, 0x05);
reg_value = MAC_REG_R8(R_AX_SYSON_FSM_MON);
if (reg_value != 0x04)
return MACEFUSEBANK;
}
reg_value = MAC_REG_R8(R_AX_EFUSE_CTRL_1 + 1);
if (bank == (reg_value & B_AX_EF_CELL_SEL_MSK))
goto set_val;
reg_value &= ~B_AX_EF_CELL_SEL_MSK;
reg_value |= bank;
MAC_REG_W8(R_AX_EFUSE_CTRL_1 + 1, reg_value);
reg_value = MAC_REG_R8(R_AX_EFUSE_CTRL_1 + 1);
if ((reg_value & B_AX_EF_CELL_SEL_MSK) == bank)
goto set_val;
else
return MACEFUSEBANK;
break;
case MAC_AX_CHIP_ID_8852B:
case MAC_AX_CHIP_ID_8852C:
case MAC_AX_CHIP_ID_8192XB:
goto set_val;
default:
break;
}
set_val:
switch (bank) {
case MAC_AX_EFUSE_BANK_WIFI:
if (dv_sel == DAV) {
bank_efuse_info.phy_map = &efuse_param->dav_efuse_map;
bank_efuse_info.log_map =
&efuse_param->dav_log_efuse_map;
bank_efuse_info.phy_map_valid =
&efuse_param->dav_efuse_map_valid;
bank_efuse_info.log_map_valid =
&efuse_param->dav_log_efuse_map_valid;
bank_efuse_info.efuse_end =
&efuse_param->dav_efuse_end;
bank_efuse_info.phy_map_size =
&hw_info->dav_efuse_size;
bank_efuse_info.log_map_size =
&hw_info->dav_log_efuse_size;
bank_efuse_info.efuse_start =
&hw_info->dav_efuse_start_addr;
break;
}
bank_efuse_info.phy_map = &efuse_param->efuse_map;
bank_efuse_info.log_map = &efuse_param->log_efuse_map;
bank_efuse_info.phy_map_valid = &efuse_param->efuse_map_valid;
bank_efuse_info.log_map_valid =
&efuse_param->log_efuse_map_valid;
bank_efuse_info.efuse_end = &efuse_param->efuse_end;
bank_efuse_info.phy_map_size = &hw_info->efuse_size;
bank_efuse_info.log_map_size = &hw_info->log_efuse_size;
bank_efuse_info.efuse_start = &hw_info->wl_efuse_start_addr;
break;
case MAC_AX_EFUSE_BANK_BT:
bank_efuse_info.phy_map = &efuse_param->bt_efuse_map;
bank_efuse_info.log_map = &efuse_param->bt_log_efuse_map;
bank_efuse_info.phy_map_valid =
&efuse_param->bt_efuse_map_valid;
bank_efuse_info.log_map_valid =
&efuse_param->bt_log_efuse_map_valid;
bank_efuse_info.efuse_end = &efuse_param->bt_efuse_end;
bank_efuse_info.phy_map_size = &hw_info->bt_efuse_size;
bank_efuse_info.log_map_size = &hw_info->bt_log_efuse_size;
bank_efuse_info.efuse_start = &hw_info->bt_efuse_start_addr;
break;
default:
return MACEFUSEBANK;
}
return MACSUCCESS;
}
static u32 proc_dump_efuse(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg)
{
u32 ret;
if (cfg == MAC_AX_EFUSE_R_AUTO) {
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
ret = dump_efuse_drv(adapter);
else
ret = dump_efuse_fw(adapter);
} else if (cfg == MAC_AX_EFUSE_R_FW) {
ret = dump_efuse_fw(adapter);
} else {
ret = dump_efuse_drv(adapter);
}
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]dump efsue drv/fw\n");
return ret;
}
return MACSUCCESS;
}
static u32 read_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size,
u8 *map)
{
u32 addr;
u32 tmp32 = 0;
u32 cnt;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 efuse_start = *bank_efuse_info.efuse_start;
offset += efuse_start;
if (dv_sel == DDV) {
enable_efuse_sw_pwr_cut(adapter, 0);
for (addr = offset; addr < offset + size; addr++) {
MAC_REG_W32(efuse_ctrl,
((addr & B_AX_EF_ADDR_MSK) << B_AX_EF_ADDR_SH)
& ~B_AX_EF_RDY);
cnt = read_efuse_cnt;
while (--cnt) {
tmp32 = MAC_REG_R32(efuse_ctrl);
if (tmp32 & B_AX_EF_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]read efuse\n");
return MACEFUSEREAD;
}
*(map + addr - offset) = (u8)(tmp32 & 0xFF);
}
disable_efuse_sw_pwr_cut(adapter, 0);
} else {
read_hw_efuse_dav(adapter, offset, size, map);
}
return MACSUCCESS;
}
static u32 write_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u8 value)
{
//const u8 unlock_code = 0x69;
u8 value_read = 0;
u32 value32;
u32 cnt;
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
u32 efuse_start = *bank_efuse_info.efuse_start;
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
*bank_efuse_info.phy_map_valid = 0;
*bank_efuse_info.log_map_valid = 0;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
offset += efuse_start;
if (dv_sel == DDV) {
//MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, unlock_code);
value32 = value |
((offset & B_AX_EF_ADDR_MSK) << B_AX_EF_ADDR_SH);
value32 &= ~B_AX_EF_RDY;
MAC_REG_W32(efuse_ctrl,
value32 | (MODE_WRITE << B_AX_EF_MODE_SEL_SH));
cnt = EFUSE_WAIT_CNT;
while (--cnt) {
if (MAC_REG_R32(efuse_ctrl) & B_AX_EF_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]write efuse\n");
return MACEFUSEWRITE;
}
//MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, 0x00);
} else {
write_hw_efuse_dav(adapter, offset, value);
}
if (efuse_param->auto_ck_en == 1) {
ret = read_hw_efuse(adapter, offset, 1, &value_read);
if (ret != 0)
return ret;
if (value_read != value) {
PLTFM_MSG_ERR("[ERR]efuse compare\n");
return MACEFUSEWRITE;
}
}
return MACSUCCESS;
}
static u32 cmp_hw_efuse(struct mac_ax_adapter *adapter, u32 offset, u16 val)
{
u32 val32;
u32 tmp32 = 0;
u32 cnt;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = val | ((offset & B_AX_EF_ADDR_MSK) << B_AX_EF_ADDR_SH);
MAC_REG_W32(efuse_ctrl, val32 | (MODE_CMP << B_AX_EF_MODE_SEL_SH));
cnt = EFUSE_WAIT_CNT;
while (--cnt) {
tmp32 = MAC_REG_R32(efuse_ctrl);
if (tmp32 & B_AX_EF_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]compare efuse\n");
return MACEFUSEREAD;
}
if (0 == (tmp32 & B_AX_EF_COMP_RESULT))
return MACEFUSECMP;
return MACSUCCESS;
}
static u32 eeprom_parser(struct mac_ax_adapter *adapter, u8 *phy_map,
u8 *log_map, enum mac_ax_efuse_parser_cfg cfg)
{
u8 i;
u8 value8;
u8 blk_idx;
u8 word_en;
u8 valid;
u8 hdr = 0;
u8 hdr2 = 0;
u32 eeprom_idx;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
u32 sec_ctrl_size = hw_info->sec_ctrl_efuse_size;
u32 efuse_idx;
u32 efuse_size = *bank_efuse_info.phy_map_size;
bool is_bt = 0;
u32 log_efuse_size = *bank_efuse_info.log_map_size;
PLTFM_MEMSET(log_map, 0xFF, log_efuse_size);
if (log_efuse_size == hw_info->bt_log_efuse_size) {
sec_ctrl_size = 0;
is_bt = 1;
}
efuse_idx = sec_ctrl_size;
do {
if (efuse_idx >= efuse_size) // secure zone
break;
value8 = *(phy_map + efuse_idx);
hdr = value8;
if (hdr == 0xff)
break;
efuse_idx++;
if (is_bt) {
if ((hdr & 0xF) != 0xF) {// 1byte entry
blk_idx = (hdr & 0xF0) >> 4;
word_en = hdr & 0x0F;
} else {// 2byte entry
value8 = *(phy_map + efuse_idx);
hdr2 = value8;
if (hdr2 == 0xff)
break;
blk_idx = (((hdr2 & 0xF0) >> 4) << 3) +
(((hdr & 0xF0) >> 4) >> 1); // offset
word_en = hdr2 & 0x0F;
efuse_idx++;
}
} else { // WLAN
value8 = *(phy_map + efuse_idx);
hdr2 = value8;
if (hdr2 == 0xff)
break;
blk_idx = ((hdr2 & 0xF0) >> 4) | ((hdr & 0x0F) << 4);
word_en = hdr2 & 0x0F;
efuse_idx++;
}
if (efuse_idx >= efuse_size - 1)
return MACEFUSEPARSE;
for (i = 0; i < 4; i++) {
valid = (u8)((~(word_en >> i)) & BIT(0));
if (valid == 1) {
eeprom_idx = (blk_idx << 3) + (i << 1);
if ((eeprom_idx + 1) >
*bank_efuse_info.log_map_size) {
PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n",
efuse_idx - 1);
PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n",
hdr);
PLTFM_MSG_ERR("[ERR]read hdr2:0x%X\n",
hdr2);
return MACEFUSEPARSE;
}
if (cfg == MAC_AX_EFUSE_PARSER_MAP) {
value8 = *(phy_map + efuse_idx);
*(log_map + eeprom_idx) = value8;
} else if (cfg == MAC_AX_EFUSE_PARSER_MASK) {
*(log_map + eeprom_idx) = 0x00;
}
eeprom_idx++;// 1 byte
efuse_idx++;
if (efuse_idx > efuse_size - 1)
return MACEFUSEPARSE;
if (cfg == MAC_AX_EFUSE_PARSER_MAP) {
value8 = *(phy_map + efuse_idx);
*(log_map + eeprom_idx) = value8;
} else if (cfg == MAC_AX_EFUSE_PARSER_MASK) {
*(log_map + eeprom_idx) = 0x00;
}
efuse_idx++;
if (efuse_idx > efuse_size)
return MACEFUSEPARSE;
}
}
} while (1);
*bank_efuse_info.efuse_end = efuse_idx;
return MACSUCCESS;
}
static u32 read_log_efuse_map(struct mac_ax_adapter *adapter, u8 *map,
u32 log_efuse_size)
{
u8 *local_map = NULL;
u32 efuse_size = *bank_efuse_info.phy_map_size;
u32 ret;
if (*bank_efuse_info.log_map_valid == 0) {
if (*bank_efuse_info.phy_map_valid == 0) {
local_map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!local_map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
ret = read_efuse(adapter, 0, efuse_size, local_map);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]read efuse\n");
goto error;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(*bank_efuse_info.phy_map, local_map,
efuse_size);
*bank_efuse_info.phy_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(local_map, efuse_size);
}
ret = eeprom_parser(adapter, *bank_efuse_info.phy_map, map,
MAC_AX_EFUSE_PARSER_MAP);
if (ret != 0)
return ret;
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(*bank_efuse_info.log_map, map, log_efuse_size);
*bank_efuse_info.log_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
} else {
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(map, *bank_efuse_info.log_map, log_efuse_size);
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
}
return MACSUCCESS;
error:
PLTFM_FREE(local_map, efuse_size);
return ret;
}
static u32 proc_pg_efuse_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg)
{
u8 *updated_mask = NULL;
u32 ret;
u32 log_efuse_size = *bank_efuse_info.log_map_size;
u32 mask_size = log_efuse_size >> 4;
updated_mask = (u8 *)PLTFM_MALLOC(mask_size);
if (!updated_mask) {
PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
return MACBUFALLOC;
}
PLTFM_MEMSET(updated_mask, 0x00, mask_size);
ret = update_eeprom_mask(adapter, info, updated_mask, 0);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]update eeprom mask\n");
goto error;
}
ret = check_efuse_enough(adapter, info, updated_mask);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]chk efuse enough\n");
goto error;
}
ret = program_efuse(adapter, info, updated_mask, 0);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]pg efuse\n");
goto error;
}
PLTFM_FREE(updated_mask, mask_size);
return MACSUCCESS;
error:
PLTFM_FREE(updated_mask, mask_size);
return ret;
}
static u32 dump_efuse_drv(struct mac_ax_adapter *adapter)
{
u8 *map = NULL;
u32 efuse_size = *bank_efuse_info.phy_map_size;
u32 ret;
if (*bank_efuse_info.phy_map_valid == 0) {
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
ret = read_hw_efuse(adapter, 0, efuse_size, map);
if (ret != 0) {
PLTFM_FREE(map, efuse_size);
return ret;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(*bank_efuse_info.phy_map, map, efuse_size);
*bank_efuse_info.phy_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(map, efuse_size);
}
return MACSUCCESS;
}
static u32 dump_efuse_fw(struct mac_ax_adapter *adapter)
{
u32 ret, cnt;
struct mac_ax_ops *ops = adapter->ops;
u8 *map = NULL;
u32 efuse_size = *bank_efuse_info.phy_map_size;
if (*bank_efuse_info.phy_map_valid == 0) {
/* H2C */
ret = ops->dump_efuse_ofld(adapter, efuse_size, 0);
if (ret)
return ret;
/* Wait for C2H */
cnt = EFUSE_FW_DUMP_WAIT_CNT;
while (--cnt) {
if (adapter->sm.efuse_ofld == MAC_AX_OFLD_H2C_DONE)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]efuse C2H\n");
adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_IDLE;
return MACPROCERR;
}
/* cpy map */
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
PLTFM_MEMSET(map, 0xFF, efuse_size);
ret = ops->efuse_ofld_map(adapter, map, efuse_size);
if (ret) {
PLTFM_FREE(map, efuse_size);
return ret;
}
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(*bank_efuse_info.phy_map, map, efuse_size);
*bank_efuse_info.phy_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
PLTFM_FREE(map, efuse_size);
}
return MACSUCCESS;
}
static u32 proc_write_log_efuse(struct mac_ax_adapter *adapter, u32 offset,
u8 value)
{
u8 byte1;
u8 byte2;
u8 blk;
u8 blk_idx;
u8 hdr;
u8 hdr2 = 0;
u8 *map = NULL;
u32 log_efuse_size = *bank_efuse_info.log_map_size;
u32 end, ret;
bool is_bt = 0;
map = (u8 *)PLTFM_MALLOC(log_efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
if (*bank_efuse_info.log_map_valid == 0) {
ret = read_log_efuse_map(adapter, map, log_efuse_size);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]read logical efuse\n");
PLTFM_FREE(map, log_efuse_size);
return ret;
}
} else {
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
PLTFM_MEMCPY(map, *bank_efuse_info.log_map, log_efuse_size);
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
}
if (log_efuse_size == adapter->hw_info->bt_log_efuse_size)
is_bt = 1;
if (*(map + offset) != value) {
end = *bank_efuse_info.efuse_end;
if (is_bt) {
if (offset < BT_1B_ENTRY_SIZE) { // 1 byte entry
blk = (u8)(offset >> 3);
blk_idx = (u8)((offset & (8 - 1)) >> 1);//mod8
hdr = (u8)((blk << 4) +
((0x1 << blk_idx) ^ 0x0F));
} else { // 2 byte entry
blk = (u8)(offset >> 3 >> 3); // large section
blk_idx = (u8)(((offset >> 3) & (8 - 1)) << 1);
hdr = (u8)((blk_idx << 4) + 0xF);
blk_idx = (u8)((offset & (8 - 1)) >> 1);
hdr2 = (u8)((blk << 4) +
((0x1 << blk_idx) ^ 0x0F));
}
} else {
blk = (u8)(offset >> 3);// offset
blk_idx = (u8)((offset & (8 - 1)) >> 1); // mod8 0 1 2 3
hdr = ((blk & 0xF0) >> 4) | 0x30;
hdr2 = (u8)(((blk & 0x0F) << 4) +
((0x1 << blk_idx) ^ 0x0F));
}
if ((offset & 1) == 0) {
byte1 = value;
byte2 = *(map + offset + 1);
} else {
byte1 = *(map + offset - 1);
byte2 = value;
}
if (*bank_efuse_info.phy_map_size <= 4 + end) { // write 4 bytes
PLTFM_FREE(map, log_efuse_size);
return MACEFUSESIZE;
}
enable_efuse_sw_pwr_cut(adapter, 1);
ret = write_hw_efuse(adapter, end, hdr);
if (ret != 0)
goto error;
if (!is_bt || offset >= BT_1B_ENTRY_SIZE) {
ret = write_hw_efuse(adapter, end + 1, hdr2);
if (ret != 0)
goto error;
end++;
}
ret = write_hw_efuse(adapter, end + 1, byte1);
if (ret != 0)
goto error;
ret = write_hw_efuse(adapter, end + 2, byte2);
if (ret != 0)
goto error;
disable_efuse_sw_pwr_cut(adapter, 1);
}
PLTFM_FREE(map, log_efuse_size);
return MACSUCCESS;
error:
PLTFM_FREE(map, log_efuse_size);
return ret;
}
static u32 read_efuse(struct mac_ax_adapter *adapter, u32 offset, u32 size,
u8 *map)
{
u32 ret;
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
if (*bank_efuse_info.phy_map_valid == 1) {
PLTFM_MEMCPY(map, *bank_efuse_info.phy_map + offset, size);
} else {
ret = read_hw_efuse(adapter, offset, size, map);
if (ret != 0)
return ret;
}
return MACSUCCESS;
}
static u32 update_eeprom_mask(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
u8 *updated_mask, bool pg_sim)
{
u8 *map = NULL;
u8 *mask_map = NULL;
u8 clr_bit = 0;
u8 *map_pg;
u8 *efuse_mask;
u32 i;
u16 j;
u16 map_offset;
u16 mask_offset;
u32 ret;
u32 log_efuse_size = *bank_efuse_info.log_map_size;
map = (u8 *)PLTFM_MALLOC(log_efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return MACBUFALLOC;
}
PLTFM_MEMSET(map, 0xFF, log_efuse_size); // default: 0xFF
if (pg_sim) { //WL
PLTFM_MEMCPY(map, *bank_efuse_info.log_map, log_efuse_size);
} else {
ret = read_log_efuse_map(adapter, map, log_efuse_size);
if (ret != 0)
goto error;
}
/*log mask*/
mask_map = (u8 *)PLTFM_MALLOC(log_efuse_size);
if (!mask_map) {
PLTFM_MSG_ERR("[ERR]malloc mask map\n");
PLTFM_FREE(map, log_efuse_size);
return MACBUFALLOC;
}
PLTFM_MEMSET(mask_map, 0xFF, log_efuse_size);// default: 0xFF
ret = eeprom_parser(adapter, *bank_efuse_info.phy_map,
mask_map, MAC_AX_EFUSE_PARSER_MASK);
if (ret != 0) {
PLTFM_FREE(mask_map, log_efuse_size);
goto error;
}
map_pg = info->efuse_map;
efuse_mask = info->efuse_mask;
PLTFM_MEMCPY(updated_mask, efuse_mask, info->efuse_mask_size);
for (i = 0; i < info->efuse_map_size; i += 16) {
for (j = 0; j < 16; j += 2) {
map_offset = i + j;
mask_offset = i >> 4;
if (*(u16 *)(map_pg + map_offset) ==
*(u16 *)(map + map_offset) &&
*(mask_map + map_offset) == 0x00) {
switch (j) {
case 0:
clr_bit = BIT(4);
break;
case 2:
clr_bit = BIT(5);
break;
case 4:
clr_bit = BIT(6);
break;
case 6:
clr_bit = BIT(7);
break;
case 8:
clr_bit = BIT(0);
break;
case 10:
clr_bit = BIT(1);
break;
case 12:
clr_bit = BIT(2);
break;
case 14:
clr_bit = BIT(3);
break;
default:
break;
}
*(updated_mask + mask_offset) &= ~clr_bit;
}
}
}
PLTFM_FREE(map, log_efuse_size);
PLTFM_FREE(mask_map, log_efuse_size);
return MACSUCCESS;
error:
PLTFM_FREE(map, log_efuse_size);
return ret;
}
static u32 check_efuse_enough(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
u8 *updated_mask)
{
u8 pre_word_en;
u32 i;
u16 j;
u32 eeprom_offset;
u32 pg_num = 0;
for (i = 0; i < info->efuse_map_size; i += 8) {
eeprom_offset = i;
if ((eeprom_offset & 0xF) > 0)
pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
else
pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
if (pre_word_en > 0) { // msk ==1 -> write
pg_num += 2;
for (j = 0; j < 4; j++) {
if (((pre_word_en >> j) & 0x1) > 0)
pg_num += 2;
}
}
}
if (*bank_efuse_info.phy_map_size
< (pg_num + *bank_efuse_info.efuse_end))
return MACEFUSESIZE;
return MACSUCCESS;
}
static u32 proc_pg_efuse(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 word_en,
u8 pre_word_en, u32 eeprom_offset, bool pg_sim)
{
u8 blk, blk_idx;
u8 hdr;
u8 hdr2 = 0xFF;
u8 i;
u32 efuse_end, ret;
u8 *efuse_map = *bank_efuse_info.phy_map;
bool is_bt = 0;
if (info->efuse_map_size == adapter->hw_info->bt_log_efuse_size)
is_bt = 1;
efuse_end = *bank_efuse_info.efuse_end;
if (is_bt) {
if (eeprom_offset < BT_1B_ENTRY_SIZE) {
blk = (u8)(eeprom_offset >> 3);
hdr = (u8)((blk << 4) + word_en);
} else {
blk = (u8)(eeprom_offset >> 3 >> 3);
blk_idx = (u8)(((eeprom_offset >> 3) & (8 - 1)) << 1);
hdr = (u8)((blk_idx << 4) | 0xF);
hdr2 = (u8)((blk << 4) + word_en);
}
} else {
blk = (u8)(eeprom_offset >> 3);
hdr = ((blk & 0xF0) >> 4) | 0x30;
hdr2 = (u8)(((blk & 0x0F) << 4) + word_en);
}
if (pg_sim) { //WL
*(efuse_map + efuse_end) = hdr;
*(efuse_map + efuse_end + 1) = hdr2;
efuse_end += 2;
for (i = 0; i < 4; i++) {
if (((pre_word_en >> i) & 0x1) > 0) {
*(efuse_map + efuse_end) = *(info->efuse_map +
eeprom_offset + (i << 1));
efuse_end++;
*(efuse_map + efuse_end) = *(info->efuse_map +
eeprom_offset + (i << 1) + 1);
efuse_end++;
}
}
} else {
ret = write_hw_efuse(adapter, efuse_end, hdr);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write efuse\n");
return ret;
}
if (is_bt == 0 || eeprom_offset >= BT_1B_ENTRY_SIZE) {
ret = write_hw_efuse(adapter, efuse_end + 1, hdr2);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write efuse(+1)\n");
return ret;
}
efuse_end++;
}
efuse_end++;
for (i = 0; i < 4; i++) {
if (((pre_word_en >> i) & 0x1) > 0) {
ret = write_hw_efuse(adapter, efuse_end,
*(info->efuse_map +
eeprom_offset + (i << 1)));
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write efuse\n");
return ret;
}
ret = write_hw_efuse(adapter, efuse_end + 1,
*(info->efuse_map +
eeprom_offset +
(i << 1) + 1));
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]write efuse+1\n");
return ret;
}
efuse_end = efuse_end + 2;
}
}
}
*bank_efuse_info.efuse_end = efuse_end;
return MACSUCCESS;
}
static u32 program_efuse(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *updated_mask,
bool pg_sim)
{
u8 pre_word_en;
u8 word_en;
u32 i;
u32 eeprom_offset, ret;
enable_efuse_sw_pwr_cut(adapter, 1);
for (i = 0; i < info->efuse_map_size; i += 8) {
eeprom_offset = i;
if (((eeprom_offset >> 3) & 1) > 0) {
pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
word_en = pre_word_en ^ 0x0F;
} else {
pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
word_en = pre_word_en ^ 0x0F;
}
if (pre_word_en > 0) {
ret = proc_pg_efuse(adapter, info, word_en, pre_word_en,
eeprom_offset, pg_sim);
if (ret != 0) {
PLTFM_MSG_ERR("[ERR]pg efuse");
return ret;
}
}
}
disable_efuse_sw_pwr_cut(adapter, 1);
return MACSUCCESS;
}
static void mask_eeprom(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info)
{
u8 pre_word_en;
u8 *updated_mask;
u8 *efuse_map;
u32 i;
u16 j;
u32 offset;
updated_mask = info->efuse_mask;
efuse_map = info->efuse_map;
for (i = 0; i < info->efuse_map_size; i += 8) {
offset = i;
if (((offset >> 3) & 1) > 0)
pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
else
pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
for (j = 0; j < 4; j++) {
if (((pre_word_en >> j) & 0x1) == 0) {
*(efuse_map + offset + (j << 1)) = 0xFF;
*(efuse_map + offset + (j << 1) + 1) = 0xFF;
}
}
}
}
static u32 query_status_map(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_feature_id feature_id,
u8 *map, bool is_limit)
{
struct mac_ax_hw_info *hw_info = adapter->hw_info;
enum mac_ax_intf intf = adapter->hw_info->intf;
u32 map_size = 0;
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
switch (feature_id) {
case MAC_AX_DUMP_PHYSICAL_EFUSE:
map_size = *bank_efuse_info.phy_map_size;
PLTFM_MEMCPY(map, *bank_efuse_info.phy_map, map_size);
break;
case MAC_AX_DUMP_LOGICAL_EFUSE:
if (!is_limit) {
map_size = *bank_efuse_info.log_map_size;
} else {// WL
switch (intf) {
case MAC_AX_INTF_PCIE:
map_size = hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
map_size = hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
map_size = hw_info->limit_efuse_size_sdio;
break;
default:
break;
}
}
PLTFM_MEMCPY(map, *bank_efuse_info.log_map, map_size);
break;
default:
return MACFUNCINPUT;
}
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
return MACSUCCESS;
}
static u32 adjust_mask(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info)
{
u8 *efuse_mask = info->efuse_mask;
u8 *efuse_map = info->efuse_map;
u32 i = 0;
u16 j = 0;
u16 map_offset;
u16 mask_offset;
u8 adj_bit = 0;
PLTFM_MEMSET(efuse_mask, 0xFF, info->efuse_mask_size);
for (i = 0; i < info->efuse_map_size; i += 16) {
for (j = 0; j < 16; j += 2) {
map_offset = i + j;
mask_offset = i >> 4;
if (*(u16 *)(efuse_map + map_offset) == 0xFFFF) {
switch (j) {
case 0:
adj_bit = BIT(4);
break;
case 2:
adj_bit = BIT(5);
break;
case 4:
adj_bit = BIT(6);
break;
case 6:
adj_bit = BIT(7);
break;
case 8:
adj_bit = BIT(0);
break;
case 10:
adj_bit = BIT(1);
break;
case 12:
adj_bit = BIT(2);
break;
case 14:
adj_bit = BIT(3);
break;
}
*(efuse_mask + mask_offset) &= ~adj_bit;
}
}
}
return MACSUCCESS;
}
static u32 compare_info_length(enum mac_ax_intf intf,
enum rtw_efuse_info id, u32 length)
{
u32 idle_len = 0;
if (intf == MAC_AX_INTF_USB) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
idle_len = LEN_ADDR_AU;
break;
case EFUSE_INFO_MAC_PID:
idle_len = LEN_PID_AU;
break;
case EFUSE_INFO_MAC_VID:
idle_len = LEN_VID_AU;
break;
default:
return MACNOITEM;
}
} else if (intf == MAC_AX_INTF_PCIE) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
idle_len = LEN_ADDR_AE;
break;
case EFUSE_INFO_MAC_DID:
idle_len = LEN_DID_AE;
break;
case EFUSE_INFO_MAC_VID:
idle_len = LEN_VID_AE;
break;
case EFUSE_INFO_MAC_SVID:
idle_len = LEN_SVID_AE;
break;
case EFUSE_INFO_MAC_SMID:
idle_len = LEN_SMID_AE;
break;
default:
return MACNOITEM;
}
} else if (intf == MAC_AX_INTF_SDIO) {
switch (id) {
case EFUSE_INFO_MAC_ADDR:
idle_len = LEN_ADDR_AS;
break;
default:
return MACNOITEM;
}
}
if (length != idle_len || idle_len == 0)
return MACLENCMP;
else
return MACSUCCESS;
}
static u32 set_check_sum_val(struct mac_ax_adapter *adapter,
u8 *map, u16 value)
{
u8 byte1;
u8 byte2;
u8 blk;
u8 blk_idx;
u8 hdr;
u8 hdr2;
u32 end = *bank_efuse_info.efuse_end, ret;
u32 offset = chksum_offset_1;
u8 i = 0;
u8 value8 = (u8)(value & 0xFF);
enable_efuse_sw_pwr_cut(adapter, 1);
for (i = 0; i < 2; i++) {
blk = (u8)(offset >> 3);
blk_idx = (u8)((offset & (8 - 1)) >> 1);
hdr = ((blk & 0xF0) >> 4) | 0x30;
hdr2 = (u8)(((blk & 0x0F) << 4) + ((0x1 << blk_idx) ^ 0x0F));
if ((offset & 1) == 0) {
byte1 = value8;
byte2 = *(map + offset + 1);
} else {
byte1 = (u8)(value & 0xFF);
byte2 = value8;
}
if (*bank_efuse_info.phy_map_size <= 4 + end)
return MACEFUSESIZE;
ret = write_hw_efuse(adapter, end, hdr);
if (ret != 0)
return ret;
ret = write_hw_efuse(adapter, end + 1, hdr2);
if (ret != 0)
return ret;
ret = write_hw_efuse(adapter, end + 2, byte1);
if (ret != 0)
return ret;
ret = write_hw_efuse(adapter, end + 3, byte2);
if (ret != 0)
return ret;
offset = chksum_offset_2;
value8 = (u8)((value & 0xFF00) >> 8);
end += 4;
}
disable_efuse_sw_pwr_cut(adapter, 1);
return MACSUCCESS;
}
static void cal_check_sum(struct mac_ax_adapter *adapter, u16 *chksum)
{
u32 i = 0;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
struct mac_ax_efuse_param *efuse_param = &adapter->efuse_param;
u8 *map = efuse_param->log_efuse_map;
u16 *data;
data = (u16 *)map;
*chksum = 0x0000;
for (i = 0; i < hw_info->log_efuse_size >> 2; i++) {
if (i == chksum_offset_1 >> 2)
*chksum ^= 0x0000 ^ *(data + (2 * i + 1));
else
*chksum ^= *(data + 2 * i) ^ *(data + (2 * i + 1));
}
}
static u32 compare_version(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u32 ver_len)
{
u8 *map = info->efuse_map;
u8 *mask = info->efuse_mask;
u32 map_size = info->efuse_map_size;
u32 i = 0;
for (i = 0; i < ver_len; i++) {
if (*(map + map_size + i) != *(mask + (map_size >> 4) + i))
return MACVERERR;
}
return MACSUCCESS;
}
static void add_dummy_read(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
MAC_REG_W32(R_AX_EFUSE_CTRL_S,
SET_WORD(CHK_OTP_ADDR, B_AX_EF_ADDR) & ~B_AX_EF_RDY);
PLTFM_DELAY_US(DUMMY_READ_DELAY);
MAC_REG_W32(R_AX_EFUSE_CTRL,
SET_WORD(CHK_OTP_ADDR, B_AX_EF_ADDR) & ~B_AX_EF_RDY);
PLTFM_DELAY_US(DUMMY_READ_DELAY);
}
static void enable_OTP_burst_mode(struct mac_ax_adapter *adapter,
bool enable)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_EFUSE_CTRL_1_V1);
if (enable)
MAC_REG_W32(R_AX_EFUSE_CTRL_1_V1, val32 | B_AX_EF_BURST);
else
MAC_REG_W32(R_AX_EFUSE_CTRL_1_V1, val32 & ~B_AX_EF_BURST);
}
static void enable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter,
bool is_write)
{
u16 val16;
u8 val8;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 chip_id = adapter->hw_info->chip_id;
if (dv_sel == DDV) {
if (chip_id == MAC_AX_CHIP_ID_8852A && !(is_write))
return;
if (is_write)
MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, UNLOCK_CODE);
val8 = MAC_REG_R8(R_AX_PMC_DBG_CTRL2);
MAC_REG_W8(R_AX_PMC_DBG_CTRL2, val8 | B_AX_SYSON_DIS_PMCR_AX_WRMSK);
val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL, val16 | BIT(B_AX_PWC_EV2EF_SH));
PLTFM_DELAY_US(1000);
val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
val16 | BIT(B_AX_PWC_EV2EF_SH + 1));
if (chip_id == MAC_AX_CHIP_ID_8852A) {
return;
} else if (chip_id == MAC_AX_CHIP_ID_8852B) {
val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
val16 & ~(B_AX_ISO_EB2CORE));
if (is_cv(adapter, CAV))
enable_OTP_burst_mode(adapter, 1);
} else {
val16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
val16 & ~(B_AX_ISO_EB2CORE));
}
} else {
enable_efuse_pwr_cut_dav(adapter, is_write);
}
}
static void disable_efuse_sw_pwr_cut(struct mac_ax_adapter *adapter,
bool is_write)
{
u16 value16;
u8 value8;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 chip_id = adapter->hw_info->chip_id;
if (dv_sel == DDV) {
if (chip_id == MAC_AX_CHIP_ID_8852A) {
if (!(is_write))
return;
} else if (chip_id == MAC_AX_CHIP_ID_8852B) {
if (is_cv(adapter, CAV))
enable_OTP_burst_mode(adapter, 0);
value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
value16 | B_AX_ISO_EB2CORE);
} else {
value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
value16 | B_AX_ISO_EB2CORE);
}
value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
value16 & ~(BIT(B_AX_PWC_EV2EF_SH + 1)));// [15]=0
PLTFM_DELAY_US(1000);
value16 = MAC_REG_R16(R_AX_SYS_ISO_CTRL);
MAC_REG_W16(R_AX_SYS_ISO_CTRL,
value16 & ~(BIT(B_AX_PWC_EV2EF_SH)));// [14]=0,
if (is_write)
MAC_REG_W8(R_AX_PMC_DBG_CTRL2 + 3, 0x00);
value8 = MAC_REG_R8(R_AX_PMC_DBG_CTRL2);
MAC_REG_W8(R_AX_PMC_DBG_CTRL2, value8 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK);
} else {
disable_efuse_pwr_cut_dav(adapter, is_write);
}
}
static u32 enable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter,
bool is_write)
{
u32 ret;
u8 chip_id = adapter->hw_info->chip_id;
if (!(is_write))
return MACSUCCESS;
if (chip_id == MAC_AX_CHIP_ID_8852A) {
return MACSUCCESS;
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT,
XTAL_SI_SMALL_PWR_CUT,
XTAL_SI_SMALL_PWR_CUT);
if (ret)
return ret;
ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT,
XTAL_SI_BIG_PWR_CUT,
XTAL_SI_BIG_PWR_CUT);
if (ret)
return ret;
}
return MACSUCCESS;
}
static u32 disable_efuse_pwr_cut_dav(struct mac_ax_adapter *adapter,
bool is_write)
{
u32 ret;
u8 chip_id = adapter->hw_info->chip_id;
if (!(is_write))
return MACSUCCESS;
if (chip_id == MAC_AX_CHIP_ID_8852A) {
return MACSUCCESS;
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT, 0,
XTAL_SI_BIG_PWR_CUT);
if (ret)
return ret;
ret = mac_write_xtal_si(adapter, XTAL_SI_PWR_CUT, 0,
XTAL_SI_SMALL_PWR_CUT);
if (ret)
return ret;
}
return MACSUCCESS;
}
static u32 read_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset, u32 size,
u8 *map)
{
u32 addr;
u8 tmp8;
u32 cnt;
u32 ret;
ret = enable_efuse_pwr_cut_dav(adapter, 0);
if (ret)
return ret;
for (addr = offset; addr < offset + size; addr++) {
/* clear ready bit*/
ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0x40, FULL_BIT_MASK);
if (ret)
return ret;
/* set addr */
ret = mac_write_xtal_si(adapter, XTAL_SI_LOW_ADDR,
(addr & 0xff) << XTAL_SI_LOW_ADDR_SH,
XTAL_SI_LOW_ADDR_MSK);
if (ret)
return ret;
ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, (addr >> 8)
<< XTAL_SI_HIGH_ADDR_SH,
XTAL_SI_HIGH_ADDR_MSK
<< XTAL_SI_HIGH_ADDR_SH);
if (ret)
return ret;
/* set ctrl mode sel */
ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0,
XTAL_SI_MODE_SEL_MSK
<< XTAL_SI_MODE_SEL_SH);
if (ret)
return ret;
/* polling */
cnt = EFUSE_WAIT_CNT;
while (--cnt) {
ret = mac_read_xtal_si(adapter, XTAL_SI_CTRL, &tmp8);
if (ret)
return ret;
if (tmp8 & XTAL_SI_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]read efuse\n");
return MACEFUSEREAD;
}
ret = mac_read_xtal_si(adapter, XTAL_SI_READ_VAL, &tmp8);
if (ret)
return ret;
*(map + addr - offset) = tmp8;
}
ret = disable_efuse_pwr_cut_dav(adapter, 0);
if (ret)
return ret;
return MACSUCCESS;
}
static u32 write_hw_efuse_dav(struct mac_ax_adapter *adapter, u32 offset,
u8 value)
{
u32 cnt;
u32 ret;
u8 tmp8;
PLTFM_MUTEX_LOCK(&efuse_tbl.lock);
*bank_efuse_info.phy_map_valid = 0;
*bank_efuse_info.log_map_valid = 0;
PLTFM_MUTEX_UNLOCK(&efuse_tbl.lock);
/* clear ready bit*/
ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0x40, FULL_BIT_MASK);
if (ret)
return ret;
/* set val */
ret = mac_write_xtal_si(adapter, XTAL_SI_WRITE_VAL, value <<
XTAL_SI_WRITE_DATA_SH, XTAL_SI_WRITE_DATA_MSK <<
XTAL_SI_WRITE_DATA_SH);
if (ret)
return ret;
/* set addr */
ret = mac_write_xtal_si(adapter, XTAL_SI_LOW_ADDR, (offset & 0xff)
<< XTAL_SI_LOW_ADDR_SH,
XTAL_SI_LOW_ADDR_MSK << XTAL_SI_LOW_ADDR_SH);
if (ret)
return ret;
ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, (offset >> 8)
<< XTAL_SI_HIGH_ADDR_SH,
XTAL_SI_HIGH_ADDR_MSK << XTAL_SI_HIGH_ADDR_SH);
if (ret)
return ret;
/* set ctrl mode sel */
ret = mac_write_xtal_si(adapter, XTAL_SI_CTRL, 0x2
<< XTAL_SI_MODE_SEL_SH,
XTAL_SI_MODE_SEL_MSK << XTAL_SI_MODE_SEL_SH);
if (ret)
return ret;
/* polling */
cnt = EFUSE_WAIT_CNT;
while (--cnt) {
ret = mac_read_xtal_si(adapter, XTAL_SI_CTRL, &tmp8);
if (ret)
return ret;
if (tmp8 & XTAL_SI_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]write efuse\n");
return MACEFUSEREAD;
}
return MACSUCCESS;
}
static void switch_dv(struct mac_ax_adapter *adapter, enum rtw_dv_sel sel)
{
dv_sel = sel;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/efuse.c
|
C
|
agpl-3.0
| 92,227
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_EFUSE_H_
#define _MAC_AX_EFUSE_H_
#include "../type.h"
#include "fwcmd.h"
#define RSVD_EFUSE_SIZE 16
#define RSVD_CS_EFUSE_SIZE 24
#define EFUSE_WAIT_CNT 10000
#define EFUSE_C2HREG_WAIT_CNT 10000
#define EFUSE_C2HREG_RETRY_WAIT_US 1
#define EFUSE_FW_DUMP_WAIT_CNT 100000
#define OTP_PHY_SIZE 0x800
#define CHK_OTP_ADDR 0x4
#define CHK_OTP_WAIT_CNT 50000
#define DUMMY_READ_DELAY 200
#define BT_1B_ENTRY_SIZE 0x80
#define UNLOCK_CODE 0x69
#define XTAL_SI_PWR_CUT 0x10
#define XTAL_SI_SMALL_PWR_CUT BIT(0)
#define XTAL_SI_BIG_PWR_CUT BIT(1)
#define XTAL_SI_LOW_ADDR 0x62
#define XTAL_SI_LOW_ADDR_SH 0
#define XTAL_SI_LOW_ADDR_MSK 0xFF
#define XTAL_SI_CTRL 0x63
#define XTAL_SI_MODE_SEL_SH 6
#define XTAL_SI_MODE_SEL_MSK 0x3
#define XTAL_SI_RDY BIT(5)
#define XTAL_SI_HIGH_ADDR_SH 0
#define XTAL_SI_HIGH_ADDR_MSK 0x7
#define XTAL_SI_READ_VAL 0x7A
#define XTAL_SI_WRITE_VAL 0x60
#define XTAL_SI_WRITE_DATA_SH 0
#define XTAL_SI_WRITE_DATA_MSK 0xFF
/**
* @struct mac_efuse_tbl
* @brief mac_efuse_tbl
*
* @var mac_efuse_tbl::lock
* Please Place Description here.
*/
struct mac_efuse_tbl {
mac_ax_mutex lock;
};
/**
* @struct mac_efuse_hidden_h2creg
* @brief mac_efuse_hidden_h2creg
*
* @var mac_efuse_hidden_h2creg::rsvd0
* Please Place Description here.
*/
struct mac_efuse_hidden_h2creg {
/* dword0 */
u32 rsvd0:16;
};
/**
* @enum efuse_map_sel
*
* @brief efuse_map_sel
*
* @var efuse_map_sel::EFUSE_MAP_SEL_PHY_WL
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_PHY_BT
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_LOG
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_LOG_BT
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_PHY_OTP
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_LAST
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_MAX
* Please Place Description here.
* @var efuse_map_sel::EFUSE_MAP_SEL_INVALID
* Please Place Description here.
*/
enum efuse_map_sel {
EFUSE_MAP_SEL_PHY_WL,
EFUSE_MAP_SEL_PHY_BT,
EFUSE_MAP_SEL_LOG,
EFUSE_MAP_SEL_LOG_BT,
EFUSE_MAP_SEL_PHY_OTP,
EFUSE_MAP_SEL_PHY_DAV,
EFUSE_MAP_SEL_LOG_DAV,
/* keep last */
EFUSE_MAP_SEL_LAST,
EFUSE_MAP_SEL_MAX = EFUSE_MAP_SEL_LAST,
EFUSE_MAP_SEL_INVALID = EFUSE_MAP_SEL_LAST,
};
/**
* @enum mac_info_offset
*
* @brief mac_info_offset
*
* @var mac_info_offset::OFS_ADDR_AU
* Please Place Description here.
* @var mac_info_offset::OFS_PID_AU
* Please Place Description here.
* @var mac_info_offset::OFS_VID_AU
* Please Place Description here.
* @var mac_info_offset::OFS_ADDR_AE
* Please Place Description here.
* @var mac_info_offset::OFS_DID_AE
* Please Place Description here.
* @var mac_info_offset::OFS_VID_AE
* Please Place Description here.
* @var mac_info_offset::OFS_SVID_AE
* Please Place Description here.
* @var mac_info_offset::OFS_SMID_AE
* Please Place Description here.
* @var mac_info_offset::OFS_ADDR_AS
* Please Place Description here.
*/
enum mac_info_offset {
/*USB*/
OFS_ADDR_AU = 0x438,
OFS_PID_AU = 0x432,
OFS_VID_AU = 0x430,
/*PCIE*/
OFS_ADDR_AE = 0x400,
OFS_DID_AE = 0x408,
OFS_VID_AE = 0x406,
OFS_SVID_AE = 0x40A,
OFS_SMID_AE = 0x40C,
/*SDIO*/
OFS_ADDR_AS = 0x41A,
};
/**
* @enum mac_info_length
*
* @brief mac_info_length
*
* @var mac_info_length::LEN_ADDR_AU
* Please Place Description here.
* @var mac_info_length::LEN_PID_AU
* Please Place Description here.
* @var mac_info_length::LEN_VID_AU
* Please Place Description here.
* @var mac_info_length::LEN_ADDR_AE
* Please Place Description here.
* @var mac_info_length::LEN_DID_AE
* Please Place Description here.
* @var mac_info_length::LEN_VID_AE
* Please Place Description here.
* @var mac_info_length::LEN_SVID_AE
* Please Place Description here.
* @var mac_info_length::LEN_SMID_AE
* Please Place Description here.
* @var mac_info_length::LEN_ADDR_AS
* Please Place Description here.
*/
enum mac_info_length {
/*USB*/
LEN_ADDR_AU = 6,
LEN_PID_AU = 2,
LEN_VID_AU = 2,
/*PCIE*/
LEN_ADDR_AE = 6,
LEN_DID_AE = 2,
LEN_VID_AE = 2,
LEN_SVID_AE = 2,
LEN_SMID_AE = 2,
/*SDIO*/
LEN_ADDR_AS = 6,
};
/**
* @enum mac_info_default_value
*
* @brief mac_info_default_value
*
* @var mac_info_default_value::VAL_ADDR_AU
* Please Place Description here.
* @var mac_info_default_value::VAL_PID_AU
* Please Place Description here.
* @var mac_info_default_value::VAL_VID_AU
* Please Place Description here.
* @var mac_info_default_value::VAL_ADDR_AE
* Please Place Description here.
* @var mac_info_default_value::VAL_DID_AE
* Please Place Description here.
* @var mac_info_default_value::VAL_VID_AE
* Please Place Description here.
* @var mac_info_default_value::VAL_SVID_AE
* Please Place Description here.
* @var mac_info_default_value::VAL_SMID_AE
* Please Place Description here.
* @var mac_info_default_value::VAL_ADDR_AS
* Please Place Description here.
*/
enum mac_info_default_value {
/*USB*/
VAL_ADDR_AU = 0x0,
VAL_PID_AU = 0x5A,
VAL_VID_AU = 0xDA,
/*PCIE*/
VAL_ADDR_AE = 0x0,
VAL_DID_AE = 0x52,
VAL_VID_AE = 0xEC,
VAL_SVID_AE = 0xEC,
VAL_SMID_AE = 0x52,
/*SDIO*/
VAL_ADDR_AS = 0x0,
};
/**
* @enum mac_checksum_offset
*
* @brief mac_checksum_offset
*
* @var mac_checksum_offset::chksum_offset_1
* Please Place Description here.
* @var mac_checksum_offset::chksum_offset_2
* Please Place Description here.
*/
enum mac_checksum_offset {
chksum_offset_1 = 0x1AC,
chksum_offset_2 = 0x1AD,
};
/**
* @struct mac_bank_efuse_info
* @brief mac_bank_efuse_info
*
* @var mac_bank_efuse_info::phy_map
* Please Place Description here.
* @var mac_bank_efuse_info::log_map
* Please Place Description here.
* @var mac_bank_efuse_info::phy_map_valid
* Please Place Description here.
* @var mac_bank_efuse_info::log_map_valid
* Please Place Description here.
* @var mac_bank_efuse_info::efuse_end
* Please Place Description here.
* @var mac_bank_efuse_info::phy_map_size
* Please Place Description here.
* @var mac_bank_efuse_info::log_map_size
* Please Place Description here.
*/
struct mac_bank_efuse_info {
/* efuse_param */
u8 **phy_map;
u8 **log_map;
u8 *phy_map_valid;
u8 *log_map_valid;
u32 *efuse_end;
/* hw_info */
u32 *phy_map_size;
u32 *log_map_size;
u32 *efuse_start;
};
/**
* @enum mac_defeature_offset
*
* @brief mac_defeature_offset
*
* @var mac_defeature_offset::rx_spatial_stream
* Please Place Description here.
* @var mac_defeature_offset::rx_spatial_stream_sh
* Please Place Description here.
* @var mac_defeature_offset::rx_spatial_stream_msk
* Please Place Description here.
* @var mac_defeature_offset::bandwidth
* Please Place Description here.
* @var mac_defeature_offset::bandwidth_sh
* Please Place Description here.
* @var mac_defeature_offset::bandwidth_msk
* Please Place Description here.
* @var mac_defeature_offset::tx_spatial_stream
* Please Place Description here.
* @var mac_defeature_offset::tx_spatial_stream_sh
* Please Place Description here.
* @var mac_defeature_offset::tx_spatial_stream_msk
* Please Place Description here.
* @var mac_defeature_offset::protocol_80211
* Please Place Description here.
* @var mac_defeature_offset::protocol_80211_sh
* Please Place Description here.
* @var mac_defeature_offset::protocol_80211_msk
* Please Place Description here.
* @var mac_defeature_offset::NIC_router
* Please Place Description here.
* @var mac_defeature_offset::NIC_router_sh
* Please Place Description here.
* @var mac_defeature_offset::NIC_router_msk
* Please Place Description here.
*/
enum mac_defeature_offset {
rx_spatial_stream = 0xB,
rx_spatial_stream_sh = 0x4,
rx_spatial_stream_msk = 0x7,
bandwidth = 0xD,
bandwidth_sh = 0x0,
bandwidth_msk = 0x7,
tx_spatial_stream = 0xD,
tx_spatial_stream_sh = 0x4,
tx_spatial_stream_msk = 0x7,
protocol_80211 = 0x11,
protocol_80211_sh = 0x2,
protocol_80211_msk = 0x3,
NIC_router = 0x11,
NIC_router_sh = 0x6,
NIC_router_msk = 0x3,
};
/**
* @enum mac_cntlr_mode_sel
*
* @brief mac_cntlr_mode_sel
*
* @var mac_cntlr_mode_sel::MODE_READ
* Please Place Description here.
* @var mac_cntlr_mode_sel::MODE_AUTOLOAD_EN
* Please Place Description here.
* @var mac_cntlr_mode_sel::MODE_WRITE
* Please Place Description here.
* @var mac_cntlr_mode_sel::MODE_CMP
* Please Place Description here.
*/
enum mac_cntlr_mode_sel {
MODE_READ,
MODE_AUTOLOAD_EN,
MODE_WRITE,
MODE_CMP,
};
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_dump_efuse_map_wl
*
* @param *adapter
* @param cfg
* @param *efuse_map
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_efuse_map_wl_plus(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_dump_efuse_map_wl
*
* @param *adapter
* @param cfg
* @param *efuse_map
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_efuse_map_wl(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_dump_efuse_map_bt
*
* @param *adapter
* @param cfg
* @param *efuse_map
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_efuse_map_bt(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_read_cfg cfg, u8 *efuse_map);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_write_efuse
*
* @param *adapter
* @param addr
* @param val
* @param bank
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val,
enum mac_ax_efuse_bank bank);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_write_efuse
*
* @param *adapter
* @param addr
* @param val
* @param bank
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val,
enum mac_ax_efuse_bank bank);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_read_efuse_plus
*
* @param *adapter
* @param addr
* @param size
* @param *val
* @param bank
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val, enum mac_ax_efuse_bank bank);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_read_efuse
*
* @param *adapter
* @param addr
* @param size
* @param *val
* @param bank
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size, u8 *val,
enum mac_ax_efuse_bank bank);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_get_efuse_avl_size
*
* @param *adapter
* @param *size
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_efuse_avl_size(struct mac_ax_adapter *adapter, u32 *size);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_get_efuse_avl_size_bt
*
* @param *adapter
* @param *size
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_efuse_avl_size_bt(struct mac_ax_adapter *adapter, u32 *size);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_dump_log_efuse
*
* @param *adapter
* @param parser_cfg
* @param cfg
* @param *efuse_map
* @param is_limit
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_log_efuse_plus(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map, bool is_limit);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_dump_log_efuse
*
* @param *adapter
* @param parser_cfg
* @param cfg
* @param *efuse_map
* @param is_limit
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_log_efuse(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map, bool is_limit);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_read_log_efuse_plus
*
* @param *adapter
* @param addr
* @param size
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_read_log_efuse
*
* @param *adapter
* @param addr
* @param size
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_write_log_efuse_plus
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_log_efuse_plus(struct mac_ax_adapter *adapter, u32 addr, u8 val);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_write_log_efuse
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_log_efuse(struct mac_ax_adapter *adapter, u32 addr, u8 val);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_dump_log_efuse_bt
*
* @param *adapter
* @param parser_cfg
* @param cfg
* @param *efuse_map
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_log_efuse_bt(struct mac_ax_adapter *adapter,
enum mac_ax_efuse_parser_cfg parser_cfg,
enum mac_ax_efuse_read_cfg cfg,
u8 *efuse_map);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_read_log_efuse_bt
*
* @param *adapter
* @param addr
* @param size
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u32 size,
u8 *val);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_write_log_efuse_bt
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_log_efuse_bt(struct mac_ax_adapter *adapter, u32 addr, u8 val);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_pg_efuse_by_map_plus
*
* @param *adapter
* @param *info
* @param cfg
* @param part
* @param is_limit
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pg_efuse_by_map_plus(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg,
bool part, bool is_limit);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_pg_efuse_by_map
*
* @param *adapter
* @param *info
* @param cfg
* @param part
* @param is_limit
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pg_efuse_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg, bool part,
bool is_limit);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_pg_efuse_by_map_bt
*
* @param *adapter
* @param *info
* @param cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pg_efuse_by_map_bt(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info,
enum mac_ax_efuse_read_cfg cfg);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_mask_log_efuse
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mask_log_efuse(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_pg_sec_data_by_map
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pg_sec_data_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_cmp_sec_data_by_map
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cmp_sec_data_by_map(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_get_efuse_info
*
* @param *adapter
* @param *efuse_map
* @param id
* @param *value
* @param length
* @param *autoload_status
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length,
u8 *autoload_status);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_set_efuse_info
*
* @param *adapter
* @param *efuse_map
* @param id
* @param *value
* @param length
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_efuse_info(struct mac_ax_adapter *adapter, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_read_hidden_rpt
*
* @param *adapter
* @param *rpt
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_hidden_rpt(struct mac_ax_adapter *adapter,
struct mac_defeature_value *rpt);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_check_efuse_autoload
*
* @param *adapter
* @param *autoload_status
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_efuse_autoload(struct mac_ax_adapter *adapter,
u8 *autoload_status);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_pg_simulator_plus
*
* @param *adapter
* @param *info
* @param *phy_map
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pg_simulator_plus(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *phy_map);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_pg_simulator
*
* @param *adapter
* @param *info
* @param *phy_map
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pg_simulator(struct mac_ax_adapter *adapter,
struct mac_ax_pg_efuse_info *info, u8 *phy_map);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_checksum_update
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_checksum_update(struct mac_ax_adapter *adapter);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_checksum_rpt
*
* @param *adapter
* @param *chksum
* @return Please Place Description here.
* @retval u32
*/
u32 mac_checksum_rpt(struct mac_ax_adapter *adapter, u16 *chksum);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_check_OTP
*
* @param *adapter
* @param *is_start
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_OTP(struct mac_ax_adapter *adapter, u8 is_start);
/**
* @brief mac_disable_rf
*
* @param *adapter
* @param *func
* @param *type
* @return Please Place Description here.
* @retval u32
*/
u32 mac_disable_rf(struct mac_ax_adapter *adapter,
enum mac_ax_disable_rf_func func, enum mac_ax_net_type type);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_set_efuse_ctrl
*
* @param *adapter
* @param is_secure
* @return Please Place Description here.
* @retval void
*/
void mac_set_efuse_ctrl(struct mac_ax_adapter *adapter, u8 is_secure);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief mac_otp_test
*
* @param *adapter
* @param is_OTP_test
* @return Please Place Description here.
* @retval u32
*/
u32 mac_otp_test(struct mac_ax_adapter *adapter, bool is_OTP_test);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief cfg_efuse_auto_ck
*
* @param *adapter
* @param enable
* @return Please Place Description here.
* @retval void
*/
void cfg_efuse_auto_ck(struct mac_ax_adapter *adapter, u8 enable);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief efuse_tbl_init
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 efuse_tbl_init(struct mac_ax_adapter *adapter);
/**
* @}
*/
/**
* @addtogroup Efuse
* @{
*/
/**
* @brief efuse_tbl_exit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 efuse_tbl_exit(struct mac_ax_adapter *adapter);
/**
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/efuse.h
|
C
|
agpl-3.0
| 21,155
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "flash.h"
#include "../mac_ax/fwcmd.h"
#if MAC_AX_FW_REG_OFLD
u32 mac_flash_erase(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u32 timeout)
{
u8 *buf;
u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0;
u32 data[2];
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
if (timeout == 0)
no_timeout = 1;
else
local_timeout = timeout;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erase_done = 0;
adapter->flash_info.erasing = 1;
adapter->flash_info.erase_addr = addr;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACNPTR; // Maybe set a timeout counter
}
pkt_len = LEN_FLASH_H2C_HDR;
buf = h2cb_put(h2cb, pkt_len);
if (!buf) {
ret = MACNOBUF;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
data[0] = cpu_to_le32(addr);
data[1] = cpu_to_le32(length);
PLTFM_MEMCPY(buf, (u8 *)data, pkt_len);
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FLASH,
FWCMD_H2C_FUNC_PLAT_FLASH_ERASE,/*platform auto test*/
0,
0);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
h2cb_free(adapter, h2cb);
h2cb = NULL;
while (1) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (adapter->flash_info.erase_done == 1) {
adapter->flash_info.erase_done = 0;
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
break;
}
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//Sleep(50);
PLTFM_DELAY_MS(1);
if (no_timeout == 0) {
local_timeout--;
if (local_timeout == 0) {
ret = MACFLASHFAIL;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
}
}
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACSUCCESS;
fail:
if (h2cb)
h2cb_free(adapter, h2cb);
adapter->fw_info.h2c_seq--;
return ret;
}
u32 mac_flash_read(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout)
{
u8 *buf;
u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0;
u32 data[2];
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
//PLTFM_MSG_TRACE("testdata = 0x%llx\n", (u64)buffer);
if (length > FLASH_H2C_SIZE)
return MACFLASHFAIL;
if (timeout == 0)
no_timeout = 1;
else
local_timeout = timeout;
if ((addr % 4) || (length % 4)) {
PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n"
, addr, length);
return MACFLASHFAIL;
}
// mutex
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.read_done = 0;
adapter->flash_info.reading = 1;
adapter->flash_info.buf_addr = buffer;
adapter->flash_info.read_addr = addr;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR; // Maybe set a timeout counter
pkt_len = LEN_FLASH_H2C_HDR;
buf = h2cb_put(h2cb, pkt_len);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
data[0] = cpu_to_le32(addr);
data[1] = cpu_to_le32(length);
PLTFM_MEMCPY(buf, (u8 *)data, pkt_len);
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FLASH,
FWCMD_H2C_FUNC_PLAT_FLASH_READ,/*platform auto test*/
0,
0);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
adapter->flash_info.read_done = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
h2cb_free(adapter, h2cb);
h2cb = NULL;
while (1) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
//PLTFM_MSG_TRACE("polling enter critical\n");
if (adapter->flash_info.read_done == 1) {
//PLTFM_MSG_TRACE("read DONE\n");
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
adapter->flash_info.read_done = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
break;
}
//PLTFM_MSG_TRACE("polling exit critical\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//Sleep(1);
PLTFM_DELAY_MS(1);
if (no_timeout == 0) {
local_timeout--;
if (local_timeout == 0) {
ret = MACFLASHFAIL;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
adapter->flash_info.read_done = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
}
}
// end mutex
//adapter->flash_info.read_done == 0;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACSUCCESS;
fail:
if (h2cb)
h2cb_free(adapter, h2cb);
adapter->fw_info.h2c_seq--;
return ret;
}
u32 mac_flash_write(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout)
{
u8 *buf;
u32 ret = 0, residue_len, pkt_len, local_timeout = 5000, no_timeout = 0, i;
u32 data[2];
u32 waddr, wlength;
u32 *pbuf;
u32 *psource_data;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
if (timeout == 0)
no_timeout = 1;
else
local_timeout = timeout;
residue_len = length;
waddr = addr;
wlength = length;
if ((addr % 4) || (length % 4)) {
PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n"
, addr, length);
return MACFLASHFAIL;
}
while (residue_len) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.write_done = 0;
adapter->flash_info.writing = 1;
adapter->flash_info.write_addr = waddr;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
if (residue_len >= FLASH_H2C_SIZE)
pkt_len = FLASH_H2C_SIZE;
else
pkt_len = residue_len;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACNPTR; // Maybe set a timeout counter
}
buf = h2cb_put(h2cb, pkt_len + LEN_FLASH_H2C_HDR);
if (!buf) {
ret = MACNOBUF;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
data[0] = cpu_to_le32(waddr);
data[1] = cpu_to_le32(pkt_len);
PLTFM_MEMCPY(buf, (u8 *)data, LEN_FLASH_H2C_HDR);
buf += LEN_FLASH_H2C_HDR;
//copy data
pbuf = (u32 *)buf;
psource_data = (u32 *)buffer;
for (i = 0; i < (pkt_len / sizeof(u32)); i++) {
*pbuf = cpu_to_le32(*psource_data);
pbuf++;
psource_data++;
}
//PLTFM_MEMCPY(buf, buffer, pkt_len);
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FLASH,
FWCMD_H2C_FUNC_PLAT_FLASH_WRITE,/*platform auto test*/
0,
0);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
h2cb_free(adapter, h2cb);
h2cb = NULL;
PLTFM_MSG_ERR("Write H2C, addr = 0x%x, length = %d\n", waddr, pkt_len);
// delay for flash write
//Sleep(1000);
while (1) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (adapter->flash_info.write_done == 1) {
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
adapter->flash_info.write_done = 0;
PLTFM_MSG_TRACE("write DONE\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
break;
}
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//Sleep(1);
PLTFM_DELAY_MS(1);
if (no_timeout == 0) {
local_timeout--;
if (local_timeout == 0) {
ret = MACFLASHFAIL;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MSG_TRACE("write timeout\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
}
}
residue_len -= pkt_len;
buffer += pkt_len;
waddr += pkt_len;
}
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACSUCCESS;
fail:
if (h2cb)
h2cb_free(adapter, h2cb);
adapter->fw_info.h2c_seq--;
return ret;
}
#else
u32 mac_flash_erase(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u32 timeout)
{
u8 *buf;
u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0;
u32 data[2];
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
if (timeout == 0)
no_timeout = 1;
else
local_timeout = timeout;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erase_done = 0;
adapter->flash_info.erasing = 1;
adapter->flash_info.erase_addr = addr;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACNPTR; // Maybe set a timeout counter
}
pkt_len = LEN_FLASH_H2C_HDR;
buf = h2cb_put(h2cb, pkt_len);
if (!buf) {
ret = MACNOBUF;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
data[0] = cpu_to_le32(addr);
data[1] = cpu_to_le32(length);
PLTFM_MEMCPY(buf, (u8 *)data, pkt_len);
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FLASH,
FWCMD_H2C_FUNC_PLAT_FLASH_ERASE,/*platform auto test*/
0,
0);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
h2cb_free(adapter, h2cb);
h2cb = NULL;
while (1) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (adapter->flash_info.erase_done == 1) {
adapter->flash_info.erase_done = 0;
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
break;
}
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//Sleep(50);
PLTFM_DELAY_MS(1);
if (no_timeout == 0) {
local_timeout--;
if (local_timeout == 0) {
ret = MACFLASHFAIL;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
}
}
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACSUCCESS;
fail:
if (h2cb)
h2cb_free(adapter, h2cb);
adapter->fw_info.h2c_seq--;
return ret;
}
u32 mac_flash_read(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout)
{
u8 *buf;
u32 ret = 0, pkt_len, local_timeout = 10000, no_timeout = 0;
u32 data[2];
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
//PLTFM_MSG_TRACE("testdata = 0x%llx\n", (u64)buffer);
if (length > FLASH_H2C_SIZE)
return MACFLASHFAIL;
if (timeout == 0)
no_timeout = 1;
else
local_timeout = timeout;
if ((addr % 4) || (length % 4)) {
PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n"
, addr, length);
return MACFLASHFAIL;
}
// mutex
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.read_done = 0;
adapter->flash_info.reading = 1;
adapter->flash_info.buf_addr = buffer;
adapter->flash_info.read_addr = addr;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR; // Maybe set a timeout counter
pkt_len = LEN_FLASH_H2C_HDR;
buf = h2cb_put(h2cb, pkt_len);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
data[0] = cpu_to_le32(addr);
data[1] = cpu_to_le32(length);
PLTFM_MEMCPY(buf, (u8 *)data, pkt_len);
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FLASH,
FWCMD_H2C_FUNC_PLAT_FLASH_READ,/*platform auto test*/
0,
0);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
adapter->flash_info.read_done = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
h2cb_free(adapter, h2cb);
h2cb = NULL;
while (1) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
//PLTFM_MSG_TRACE("polling enter critical\n");
if (adapter->flash_info.read_done == 1) {
//PLTFM_MSG_TRACE("read DONE\n");
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
adapter->flash_info.read_done = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
break;
}
//PLTFM_MSG_TRACE("polling exit critical\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//Sleep(1);
PLTFM_DELAY_MS(1);
if (no_timeout == 0) {
local_timeout--;
if (local_timeout == 0) {
ret = MACFLASHFAIL;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
adapter->flash_info.read_done = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
}
}
// end mutex
//adapter->flash_info.read_done == 0;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.reading = 0;
adapter->flash_info.buf_addr = NULL;
adapter->flash_info.read_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACSUCCESS;
fail:
if (h2cb)
h2cb_free(adapter, h2cb);
adapter->fw_info.h2c_seq--;
return ret;
}
u32 mac_flash_write(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout)
{
u8 *buf;
u32 ret = 0, residue_len, pkt_len, local_timeout = 5000, no_timeout = 0, i;
u32 data[2];
u32 waddr, wlength;
u32 *pbuf;
u32 *psource_data;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
if (timeout == 0)
no_timeout = 1;
else
local_timeout = timeout;
residue_len = length;
waddr = addr;
wlength = length;
if ((addr % 4) || (length % 4)) {
PLTFM_MSG_ERR("Address/length not 4 byte aligned, addr : 0x%x, length : 0x%x\n"
, addr, length);
return MACFLASHFAIL;
}
while (residue_len) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.write_done = 0;
adapter->flash_info.writing = 1;
adapter->flash_info.write_addr = waddr;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
if (residue_len >= FLASH_H2C_SIZE)
pkt_len = FLASH_H2C_SIZE;
else
pkt_len = residue_len;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACNPTR; // Maybe set a timeout counter
}
buf = h2cb_put(h2cb, pkt_len + LEN_FLASH_H2C_HDR);
if (!buf) {
ret = MACNOBUF;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
data[0] = cpu_to_le32(waddr);
data[1] = cpu_to_le32(pkt_len);
PLTFM_MEMCPY(buf, (u8 *)data, LEN_FLASH_H2C_HDR);
buf += LEN_FLASH_H2C_HDR;
//copy data
pbuf = (u32 *)buf;
psource_data = (u32 *)buffer;
for (i = 0; i < (pkt_len / sizeof(u32)); i++) {
*pbuf = cpu_to_le32(*psource_data);
pbuf++;
psource_data++;
}
//PLTFM_MEMCPY(buf, buffer, pkt_len);
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FLASH,
FWCMD_H2C_FUNC_PLAT_FLASH_WRITE,/*platform auto test*/
0,
0);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %x\n", ret);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
h2cb_free(adapter, h2cb);
h2cb = NULL;
PLTFM_MSG_ERR("Write H2C, addr = 0x%x, length = %d\n", waddr, pkt_len);
// delay for flash write
//Sleep(1000);
while (1) {
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (adapter->flash_info.write_done == 1) {
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
adapter->flash_info.write_done = 0;
PLTFM_MSG_TRACE("write DONE\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
break;
}
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//Sleep(1);
PLTFM_DELAY_MS(1);
if (no_timeout == 0) {
local_timeout--;
if (local_timeout == 0) {
ret = MACFLASHFAIL;
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MSG_TRACE("write timeout\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
goto fail;
}
}
}
residue_len -= pkt_len;
buffer += pkt_len;
waddr += pkt_len;
}
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
adapter->flash_info.writing = 0;
adapter->flash_info.write_addr = 0;
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
return MACSUCCESS;
fail:
if (h2cb)
h2cb_free(adapter, h2cb);
adapter->fw_info.h2c_seq--;
return ret;
}
#endif
u32 c2h_sys_flash_pkt(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u32 hdr0, i;
u32 func, length, addr;
u32 *pbuf;
u32 *psource_data;
PLTFM_MSG_TRACE("%s\n", __func__);
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
//set info
info->c2h_cat = GET_FIELD(hdr0, C2H_HDR_CAT);
info->c2h_class = GET_FIELD(hdr0, C2H_HDR_CLASS);
info->c2h_func = GET_FIELD(hdr0, C2H_HDR_FUNC);
//info->done_ack = 0;
//info->rec_ack = 0;
info->content = buf + FWCMD_HDR_LEN;
//info->h2c_return = info->c2h_data[1];
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
if (func == FWCMD_H2C_FUNC_PLAT_FLASH_READ) {
addr = *((u32 *)info->content);
addr = le32_to_cpu(addr);
length = *((u32 *)(info->content + LEN_FLASH_C2H_HDR_ADDR));
length = le32_to_cpu(length);
PLTFM_MSG_TRACE("addr = 0x%x, length = 0x%x\n", addr, length);
PLTFM_MSG_TRACE("adapter->flash_info.read_addr = 0x%x\n",
adapter->flash_info.read_addr);
//PLTFM_MSG_TRACE("adapter->flash_info.buf_addr = 0x%llx\n",
//(u64)adapter->flash_info.buf_addr);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (addr == adapter->flash_info.read_addr && adapter->flash_info.reading == 1) {
// lost data if timeout happened
//PLTFM_MSG_TRACE("ready to read\n");
if (adapter->flash_info.buf_addr && length <= MAX_READ_SIZE) {
PLTFM_MSG_TRACE("memcpy to buf\n");
//PLTFM_MEMCPY(adapter->flash_info.buf_addr,
// info->content + LEN_FLASH_C2H_HDR, length);
pbuf = (u32 *)adapter->flash_info.buf_addr;
psource_data = (u32 *)(info->content + LEN_FLASH_C2H_HDR);
for (i = 0; i < length / sizeof(u32); i++) {
*pbuf = le32_to_cpu(*psource_data);
pbuf++;
psource_data++;
}
//PLTFM_MSG_TRACE("memcpy to buf end\n");
}
}
//PLTFM_MSG_TRACE("set reading = 0\n");
adapter->flash_info.reading = 0;
adapter->flash_info.read_done = 1;
//PLTFM_MSG_TRACE("set reading = 0 end\n");
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
//PLTFM_MSG_TRACE("exit critical\n");
} else if (func == FWCMD_H2C_FUNC_PLAT_FLASH_WRITE) {
addr = *((u32 *)info->content);
addr = le32_to_cpu(addr);
length = *((u32 *)(info->content + LEN_FLASH_C2H_HDR_ADDR));
length = le32_to_cpu(length);
PLTFM_MSG_TRACE("write addr = 0x%x\n", *((u32 *)info->content));
PLTFM_MSG_TRACE("adapter->flash_info.write_addr = 0x%x\n",
adapter->flash_info.write_addr);
PLTFM_MSG_TRACE("write length = 0x%x\n", length);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (addr == adapter->flash_info.write_addr && adapter->flash_info.writing == 1) {
adapter->flash_info.writing = 0;
adapter->flash_info.write_done = 1;
}
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
} else if (func == FWCMD_H2C_FUNC_PLAT_FLASH_ERASE) {
addr = *((u32 *)info->content);
addr = le32_to_cpu(addr);
length = *((u32 *)(info->content + LEN_FLASH_C2H_HDR_ADDR));
length = le32_to_cpu(length);
PLTFM_MSG_TRACE("erase addr = 0x%x\n", *((u32 *)info->content));
PLTFM_MSG_TRACE("adapter->flash_info.erase_addr = 0x%x\n",
adapter->flash_info.erase_addr);
PLTFM_MSG_TRACE("erase length = 0x%x\n", length);
PLTFM_MUTEX_LOCK(&adapter->flash_info.lock);
if (addr == adapter->flash_info.erase_addr && adapter->flash_info.erasing == 1) {
adapter->flash_info.erasing = 0;
adapter->flash_info.erase_done = 1;
}
PLTFM_MUTEX_UNLOCK(&adapter->flash_info.lock);
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/flash.c
|
C
|
agpl-3.0
| 26,351
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FLASH_H_
#define _MAC_AX_FLASH_H_
#include "../type.h"
#include "../mac_def.h"
#include "../mac_ax.h"
#include "fwcmd.h"
#include "trx_desc.h"
#include "trxcfg.h"
#include "dle.h"
#define MAX_LENGTH_ENUM 7
#define FLASH_H2C_SIZE 1984
#define LEN_FLASH_C2H_HDR_ADDR 4
#define LEN_FLASH_C2H_HDR_LENGTH 4
#define LEN_FLASH_H2C_HDR 8
#define LEN_FLASH_C2H_HDR 8
#define MAX_READ_SIZE 1984
u32 mac_flash_erase(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u32 timeout);
u32 mac_flash_read(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout);
u32 mac_flash_write(struct mac_ax_adapter *adapter,
u32 addr,
u32 length,
u8 *buffer,
u32 timeout);
u32 c2h_sys_flash_pkt(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/flash.h
|
C
|
agpl-3.0
| 1,541
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "fwcmd.h"
#include "mcc.h"
#if MAC_AX_FEATURE_HV
#include "../hv_ax/dbgpkg_hv.h"
#endif
/* 8852A/8852B: the format of H2C/DLFW descriptor: WD Body
* 8852C: the format of H2C/DLFW descriptor: RX Descriptor
* WD body max len: 24 bytes
* RX descriptor max len: 32 bytes
* We use the max RX descriptor size as the header size
* WD_BODY_LEN_V1 = RX descriptor max len = 32 bytes
*/
#define H2CB_CMD_HDR_SIZE (FWCMD_HDR_LEN + WD_BODY_LEN_V1)
#define H2CB_CMD_SIZE (H2C_CMD_LEN - FWCMD_HDR_LEN)
#define H2CB_CMD_QLEN 8
#define H2CB_DATA_HDR_SIZE (FWCMD_HDR_LEN + WD_BODY_LEN_V1)
#define H2CB_DATA_SIZE (H2C_DATA_LEN - FWCMD_HDR_LEN)
#define H2CB_DATA_QLEN 4
#define H2CB_LONG_DATA_HDR_SIZE (FWCMD_HDR_LEN + WD_BODY_LEN)
#define H2CB_LONG_DATA_SIZE (H2C_LONG_DATA_LEN - FWCMD_HDR_LEN)
#define H2CB_LONG_DATA_QLEN 1
#define FWCMD_WQ_MAX_JOB_NUM 5
#define FWCMD_LMT 12
#define MAC_AX_H2C_LMT_EN 0
#define FWCMD_H2CREG_BYTE0_SH 0
#define FWCMD_H2CREG_BYTE0_MSK 0xFF
#define FWCMD_H2CREG_BYTE1_SH 8
#define FWCMD_H2CREG_BYTE1_MSK 0xFF
#define FWCMD_H2CREG_BYTE2_SH 16
#define FWCMD_H2CREG_BYTE2_MSK 0xFF
#define FWCMD_H2CREG_BYTE3_SH 24
#define FWCMD_H2CREG_BYTE3_MSK 0xFF
#define BCN_GRPIE_OFST_EN BIT(7)
static struct h2c_buf_head h2cb_head[H2CB_CLASS_MAX];
static struct fwcmd_wkb_head fwcmd_wq_head;
struct fwcmd_outsrc_info {
#define MAX_OUTSRC_LEN 60 //need to extend if needed
u32 dword0[MAX_OUTSRC_LEN];
};
struct c2h_event_id_proc {
u8 cat;
u8 cls;
u8 func;
u32 (*hdl)(struct mac_ax_adapter *adapter, struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id, u8 *c2h_info);
};
static inline u32 h2cb_queue_len(struct h2c_buf_head *list)
{
return list->qlen;
}
static inline void __h2cb_queue_head_init(struct h2c_buf_head *list)
{
list->prev = (struct h2c_buf *)list;
list->next = (struct h2c_buf *)list;
list->qlen = 0;
list->suspend = 0;
}
static inline void h2cb_queue_head_init(struct mac_ax_adapter *adapter,
struct h2c_buf_head *list)
{
PLTFM_MUTEX_INIT(&list->lock);
__h2cb_queue_head_init(list);
}
static inline void __h2cb_insert(struct h2c_buf *new_h2cb, struct h2c_buf *prev,
struct h2c_buf *next,
struct h2c_buf_head *list)
{
new_h2cb->next = next;
new_h2cb->prev = prev;
next->prev = new_h2cb;
prev->next = new_h2cb;
list->qlen++;
}
static inline void __h2cb_queue_before(struct h2c_buf_head *list,
struct h2c_buf *next,
struct h2c_buf *new_h2cb)
{
__h2cb_insert(new_h2cb, next->prev, next, list);
}
static inline void __h2cb_queue_tail(struct h2c_buf_head *list,
struct h2c_buf *new_h2cb)
{
__h2cb_queue_before(list, (struct h2c_buf *)list, new_h2cb);
}
static inline void __h2cb_unlink(struct h2c_buf *h2cb,
struct h2c_buf_head *list)
{
struct h2c_buf *next, *prev;
list->qlen--;
next = h2cb->next;
prev = h2cb->prev;
h2cb->prev = NULL;
h2cb->next = NULL;
next->prev = prev;
prev->next = next;
}
static inline struct h2c_buf *h2cb_peek(struct h2c_buf_head *list)
{
struct h2c_buf *h2cb = list->next;
if (h2cb == (struct h2c_buf *)list)
h2cb = NULL;
return h2cb;
}
#if MAC_AX_PHL_H2C
u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb)
#else
u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb)
#endif
{
struct mac_ax_h2c_agg_node *h2c_agg_node = NULL;
u32 ret = MACSUCCESS;
PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock);
if (!adapter->h2c_agg_info.h2c_agg_en) {
/* return fall and send the H2C pkt by the orginal function*/
ret = MACNOITEM;
goto fail;
}
h2c_agg_node = (struct mac_ax_h2c_agg_node *)
PLTFM_MALLOC(sizeof(struct mac_ax_h2c_agg_node));
if (!h2c_agg_node) {
/* return fall and send the H2C pkt by the orginal function*/
ret = MACBUFALLOC;
goto fail;
}
PLTFM_MEMSET(h2c_agg_node, 0, sizeof(struct mac_ax_h2c_agg_node));
h2c_agg_node->h2c_pkt = (u8 *)h2cb;
h2c_agg_node->next = NULL;
adapter->h2c_agg_info.h2c_agg_pkt_num++;
if (!adapter->h2c_agg_info.h2c_agg_queue_head) {
adapter->h2c_agg_info.h2c_agg_queue_head = h2c_agg_node;
adapter->h2c_agg_info.h2c_agg_queue_last = h2c_agg_node;
} else {
adapter->h2c_agg_info.h2c_agg_queue_last->next = h2c_agg_node;
adapter->h2c_agg_info.h2c_agg_queue_last = h2c_agg_node;
}
fail:
PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock);
return ret;
}
#if MAC_AX_PHL_H2C
static inline u8 *h2cb_tail_pointer(const struct rtw_h2c_pkt *h2cb)
{
return h2cb->vir_tail;
}
#else
static inline u8 *h2cb_tail_pointer(const struct h2c_buf *h2cb)
{
return h2cb->tail;
}
#endif
static inline struct h2c_buf *h2cb_dequeue(struct h2c_buf_head *list)
{
struct h2c_buf *h2cb = h2cb_peek(list);
if (h2cb)
__h2cb_unlink(h2cb, list);
return h2cb;
}
static u8 *__h2cb_alloc_buf_pool(struct mac_ax_adapter *adapter,
struct h2c_buf_head *list, u32 size, int num)
{
u32 block_size = (size * num);
u8 *ptr;
ptr = (u8 *)PLTFM_MALLOC(block_size);
list->pool = ptr;
list->size = block_size;
return ptr;
}
static struct h2c_buf *__h2cb_alloc(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class,
u32 hdr_size, u8 *buf_ptr, int buf_size)
{
struct h2c_buf *h2cb;
//_ASSERT_(!buf_ptr);
h2cb = (struct h2c_buf *)PLTFM_MALLOC(sizeof(struct h2c_buf));
if (!h2cb)
return NULL;
PLTFM_MEMSET(h2cb, 0, sizeof(struct h2c_buf));
h2cb->_class_ = buf_class;
h2cb->id = 0;
h2cb->master = 0;
h2cb->len = 0;
h2cb->head = buf_ptr;
h2cb->end = h2cb->head + buf_size;
h2cb->data = h2cb->head + hdr_size;
h2cb->tail = h2cb->data;
h2cb->hdr_len = hdr_size;
h2cb->flags |= H2CB_FLAGS_FREED;
return h2cb;
}
static u32 __h2cb_free(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class)
{
struct h2c_buf_head *list_head = &h2cb_head[buf_class];
struct h2c_buf *h2cb;
if (buf_class >= H2CB_CLASS_LAST)
return MACNOITEM;
if (!list_head->pool)
return MACNPTR;
if (!h2cb_queue_len(list_head))
return MACSUCCESS;
while ((h2cb = h2cb_dequeue(list_head)))
PLTFM_FREE(h2cb, sizeof(struct h2c_buf));
PLTFM_FREE(list_head->pool, list_head->size);
list_head->pool = NULL;
list_head->size = 0;
PLTFM_MUTEX_DEINIT(&list_head->lock);
return MACSUCCESS;
}
static u32 __h2cb_init(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class, u32 num, u32 buf_size,
u32 hdr_size, u32 tailer_size)
{
u32 i;
u8 *ptr;
struct h2c_buf_head *list_head = &h2cb_head[buf_class];
u32 real_size = buf_size + hdr_size + tailer_size;
struct h2c_buf *h2cb;
if (buf_class >= H2CB_CLASS_LAST)
return MACNOITEM;
if (h2cb_queue_len(list_head))
return MACBUFSZ;
h2cb_queue_head_init(adapter, list_head);
ptr = __h2cb_alloc_buf_pool(adapter, list_head, real_size, num);
if (!ptr)
return MACNPTR;
for (i = 0; i < num; i++) {
h2cb = __h2cb_alloc(adapter,
buf_class, hdr_size, ptr, real_size);
if (!h2cb)
goto h2cb_fail;
__h2cb_queue_tail(list_head, h2cb);
ptr += real_size;
}
return MACSUCCESS;
h2cb_fail:
__h2cb_free(adapter, buf_class);
return MACBUFALLOC;
}
static inline u32 fwcmd_wkb_queue_len(struct fwcmd_wkb_head *list)
{
return list->qlen;
};
static inline void __fwcmd_wkb_queue_head_init(struct fwcmd_wkb_head *list)
{
list->prev = (struct h2c_buf *)list;
list->next = (struct h2c_buf *)list;
list->qlen = 0;
};
static inline void fwcmd_wkb_queue_head_init(struct mac_ax_adapter *adapter,
struct fwcmd_wkb_head *list)
{
PLTFM_MUTEX_INIT(&list->lock);
__fwcmd_wkb_queue_head_init(list);
}
static u32 __fwcmd_wkb_init(struct mac_ax_adapter *adapter)
{
struct fwcmd_wkb_head *list_head = &fwcmd_wq_head;
if (fwcmd_wkb_queue_len(list_head))
return MACBUFSZ;
fwcmd_wkb_queue_head_init(adapter, list_head);
return MACSUCCESS;
}
u32 h2cb_init(struct mac_ax_adapter *adapter)
{
u32 ret;
ret = __h2cb_init(adapter, H2CB_CLASS_CMD, H2CB_CMD_QLEN,
H2CB_CMD_SIZE, H2CB_CMD_HDR_SIZE, 0);
if (ret)
return ret;
ret = __h2cb_init(adapter, H2CB_CLASS_DATA, H2CB_DATA_QLEN,
H2CB_DATA_SIZE, H2CB_DATA_HDR_SIZE, 0);
if (ret)
return ret;
ret = __h2cb_init(adapter, H2CB_CLASS_LONG_DATA, H2CB_LONG_DATA_QLEN,
H2CB_LONG_DATA_SIZE, H2CB_LONG_DATA_HDR_SIZE, 0);
if (ret)
return ret;
ret = __fwcmd_wkb_init(adapter);
if (ret)
return ret;
return MACSUCCESS;
}
u32 h2cb_exit(struct mac_ax_adapter *adapter)
{
struct fwcmd_wkb_head *list_head = &fwcmd_wq_head;
if (fwcmd_wkb_queue_len(list_head))
return MACBUFSZ;
__h2cb_free(adapter, H2CB_CLASS_CMD);
__h2cb_free(adapter, H2CB_CLASS_DATA);
__h2cb_free(adapter, H2CB_CLASS_LONG_DATA);
return MACSUCCESS;
}
u32 h2c_end_flow(struct mac_ax_adapter *adapter)
{
struct mac_ax_fw_info *fwinfo = &adapter->fw_info;
PLTFM_MUTEX_LOCK(&fwinfo->seq_lock);
fwinfo->h2c_seq++;
PLTFM_MUTEX_UNLOCK(&fwinfo->seq_lock);
return MACSUCCESS;
}
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb_alloc(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class)
{
struct rtw_h2c_pkt *h2cb;
#if MAC_AX_H2C_LMT_EN
struct mac_ax_fw_info *fwinfo = &adapter->fw_info;
u8 diff;
u8 cnt = 100;
#endif
if (buf_class >= H2CB_CLASS_LAST) {
PLTFM_MSG_ERR("[ERR]unknown class\n");
return NULL;
}
#if MAC_AX_H2C_LMT_EN
while (--cnt) {
if (fwinfo->h2c_seq >= fwinfo->rec_seq)
diff = fwinfo->h2c_seq - fwinfo->rec_seq;
else
diff = (255 - fwinfo->rec_seq) + fwinfo->h2c_seq;
if (diff < FWCMD_LMT)
break;
PLTFM_DELAY_US(100);
}
if (diff >= FWCMD_LMT) {
PLTFM_MSG_ERR("The number of H2C has reached the limitation\n");
PLTFM_MSG_ERR("curr: %d, rec: %d\n",
fwinfo->h2c_seq, fwinfo->rec_seq);
return NULL;
}
#endif
h2cb = PLTFM_QUERY_H2C(buf_class);
return h2cb;
}
void h2cb_free(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb)
{
}
u8 *h2cb_push(struct rtw_h2c_pkt *h2cb, u32 len)
{
h2cb->vir_data -= len;
h2cb->data_len += len;
if (h2cb->vir_data < h2cb->vir_head)
return NULL;
return h2cb->vir_data;
}
u8 *h2cb_pull(struct rtw_h2c_pkt *h2cb, u32 len)
{
h2cb->vir_data += len;
if (h2cb->vir_data > h2cb->vir_end)
return NULL;
if (h2cb->data_len < len)
return NULL;
h2cb->data_len -= len;
return h2cb->vir_data;
}
u8 *h2cb_put(struct rtw_h2c_pkt *h2cb, u32 len)
{
u8 *tmp = h2cb_tail_pointer(h2cb);
h2cb->vir_tail += len;
h2cb->data_len += len;
if (h2cb->vir_tail > h2cb->vir_end)
return NULL;
return tmp;
}
u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb,
u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack)
{
struct fwcmd_hdr *hdr;
struct mac_ax_fw_info *fwinfo = &adapter->fw_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACFWNONRDY;
if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) {
PLTFM_MSG_TRACE("%s: MAC is not ready\n", __func__);
adapter->stats.h2c_pkt_uninit++;
}
hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN);
if (!hdr)
return MACNPTR;
hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) |
SET_WORD(cat, H2C_HDR_CAT) |
SET_WORD(_class_, H2C_HDR_CLASS) |
SET_WORD(func, H2C_HDR_FUNC) |
SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ));
hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->data_len, H2C_HDR_TOTAL_LEN) |
(rack || !(fwinfo->h2c_seq & 3) ?
H2C_HDR_REC_ACK : 0) |
(dack ? H2C_HDR_DONE_ACK : 0));
h2cb->id = SET_FWCMD_ID(type, cat, _class_, func);
h2cb->h2c_seq = fwinfo->h2c_seq;
return MACSUCCESS;
}
u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter,
struct rtw_h2c_pkt *h2cb, u8 type, u8 cat,
u8 _class_, u8 func, u16 rack, u16 dack)
{
struct fwcmd_hdr *hdr;
struct mac_ax_fw_info *fwinfo = &adapter->fw_info;
hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN);
if (!hdr)
return MACNPTR;
hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) |
SET_WORD(cat, H2C_HDR_CAT) |
SET_WORD(_class_, H2C_HDR_CLASS) |
SET_WORD(func, H2C_HDR_FUNC) |
SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ));
hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->data_len, H2C_HDR_TOTAL_LEN) |
(rack ? H2C_HDR_REC_ACK : 0) |
(dack ? H2C_HDR_DONE_ACK : 0));
h2cb->id = SET_FWCMD_ID(type, cat, _class_, func);
h2cb->h2c_seq = fwinfo->h2c_seq;
return MACSUCCESS;
}
u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb,
u8 *cmd, u32 len)
{
u8 *buf;
buf = h2cb_put(h2cb, len);
if (!buf)
return MACNPTR;
PLTFM_MEMCPY(buf, cmd, len);
return MACSUCCESS;
}
u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb)
{
u8 *buf;
u32 ret;
u32 txd_len;
struct rtw_t_meta_data info = {0};
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
info.type = RTW_PHL_PKT_TYPE_H2C;
info.pktlen = (u16)h2cb->data_len;
txd_len = ops->txdesc_len(adapter, &info);
if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
if (((info.pktlen + txd_len) & (512 - 1)) == 0) {
buf = h2cb_put(h2cb, 4);
if (!buf) {
PLTFM_MSG_ERR("Avoid USB 512-byte FAIL\n");
return MACNPTR;
}
info.pktlen = (u16)h2cb->data_len;
txd_len = ops->txdesc_len(adapter, &info);
}
}
buf = h2cb_push(h2cb, txd_len);
if (!buf)
return MACNPTR;
ret = ops->build_txdesc(adapter, &info, buf, txd_len);
if (ret)
return ret;
return MACSUCCESS;
}
u32 fwcmd_wq_idle(struct mac_ax_adapter *adapter, u32 id)
{
return MACSUCCESS;
}
#else
struct h2c_buf *h2cb_alloc(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class)
{
struct h2c_buf_head *list_head = &h2cb_head[buf_class];
struct h2c_buf *h2cb;
if (buf_class >= H2CB_CLASS_LAST) {
PLTFM_MSG_ERR("[ERR]unknown class\n");
return NULL;
}
PLTFM_MUTEX_LOCK(&list_head->lock);
h2cb = h2cb_dequeue(list_head);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]allocate h2cb, class : %d\n", buf_class);
goto h2cb_fail;
}
if (!(h2cb->flags & H2CB_FLAGS_FREED)) {
PLTFM_MSG_ERR("[ERR]not freed flag\n");
PLTFM_FREE(h2cb, sizeof(struct h2c_buf));
goto h2cb_fail;
}
h2cb->flags &= ~H2CB_FLAGS_FREED;
PLTFM_MUTEX_UNLOCK(&list_head->lock);
return h2cb;
h2cb_fail:
PLTFM_MUTEX_UNLOCK(&list_head->lock);
return NULL;
}
void h2cb_free(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb)
{
struct h2c_buf_head *list_head;
if (h2cb->flags & H2CB_FLAGS_FREED) {
PLTFM_MSG_ERR("[ERR]freed flag\n");
return;
}
if (h2cb->_class_ >= H2CB_CLASS_LAST) {
PLTFM_MSG_ERR("[ERR]unknown class\n");
return;
}
list_head = &h2cb_head[h2cb->_class_];
h2cb->len = 0;
h2cb->data = h2cb->head + h2cb->hdr_len;
h2cb->tail = h2cb->data;
h2cb->flags |= H2CB_FLAGS_FREED;
PLTFM_MUTEX_LOCK(&list_head->lock);
__h2cb_queue_tail(list_head, h2cb);
PLTFM_MUTEX_UNLOCK(&list_head->lock);
}
u8 *h2cb_push(struct h2c_buf *h2cb, u32 len)
{
h2cb->data -= len;
h2cb->len += len;
if (h2cb->data < h2cb->head)
return NULL;
return h2cb->data;
}
u8 *h2cb_pull(struct h2c_buf *h2cb, u32 len)
{
h2cb->data += len;
if (h2cb->data > h2cb->end)
return NULL;
if (h2cb->len < len)
return NULL;
h2cb->len -= len;
return h2cb->data;
}
u8 *h2cb_put(struct h2c_buf *h2cb, u32 len)
{
u8 *tmp = h2cb_tail_pointer(h2cb);
h2cb->tail += len;
h2cb->len += len;
if (h2cb->tail > h2cb->end)
return NULL;
return tmp;
}
u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb,
u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack)
{
struct fwcmd_hdr *hdr;
struct mac_ax_fw_info *fwinfo = &adapter->fw_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACFWNONRDY;
if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) {
PLTFM_MSG_TRACE("MAC is not ready\n");
adapter->stats.h2c_pkt_uninit++;
}
hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN);
if (!hdr)
return MACNPTR;
hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) |
SET_WORD(cat, H2C_HDR_CAT) |
SET_WORD(_class_, H2C_HDR_CLASS) |
SET_WORD(func, H2C_HDR_FUNC) |
SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ));
hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->len, H2C_HDR_TOTAL_LEN) |
(rack || !(fwinfo->h2c_seq & 3) ?
H2C_HDR_REC_ACK : 0) |
(dack ? H2C_HDR_DONE_ACK : 0));
h2cb->id = SET_FWCMD_ID(type, cat, _class_, func);
h2cb->h2c_seq = fwinfo->h2c_seq;
return 0;
}
u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter,
struct h2c_buf *h2cb, u8 type, u8 cat,
u8 _class_, u8 func, u16 rack, u16 dack)
{
struct fwcmd_hdr *hdr;
struct mac_ax_fw_info *fwinfo = &adapter->fw_info;
hdr = (struct fwcmd_hdr *)h2cb_push(h2cb, FWCMD_HDR_LEN);
if (!hdr)
return MACNPTR;
hdr->hdr0 = cpu_to_le32(SET_WORD(type, H2C_HDR_DEL_TYPE) |
SET_WORD(cat, H2C_HDR_CAT) |
SET_WORD(_class_, H2C_HDR_CLASS) |
SET_WORD(func, H2C_HDR_FUNC) |
SET_WORD(fwinfo->h2c_seq, H2C_HDR_H2C_SEQ));
hdr->hdr1 = cpu_to_le32(SET_WORD(h2cb->len, H2C_HDR_TOTAL_LEN) |
(rack ? H2C_HDR_REC_ACK : 0) |
(dack ? H2C_HDR_DONE_ACK : 0));
h2cb->id = SET_FWCMD_ID(type, cat, _class_, func);
h2cb->h2c_seq = fwinfo->h2c_seq;
return 0;
}
u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb,
u8 *cmd, u32 len)
{
u8 *buf;
buf = h2cb_put(h2cb, len);
if (!buf)
return MACNPTR;
PLTFM_MEMCPY(buf, cmd, len);
return MACSUCCESS;
}
u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb)
{
u8 *buf;
u32 ret;
u32 txd_len;
struct rtw_t_meta_data info = {0};
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
info.type = RTW_PHL_PKT_TYPE_H2C;
info.pktlen = (u16)h2cb->len;
txd_len = ops->txdesc_len(adapter, &info);
if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
if (((info.pktlen + txd_len) & (512 - 1)) == 0) {
buf = h2cb_put(h2cb, 4);
if (!buf) {
PLTFM_MSG_ERR("Avoid USB 512-byte FAIL\n");
return MACNPTR;
}
info.pktlen = (u16)h2cb->len;
txd_len = ops->txdesc_len(adapter, &info);
}
}
buf = h2cb_push(h2cb, txd_len);
if (!buf)
return MACNPTR;
ret = ops->build_txdesc(adapter, &info, buf, txd_len);
if (ret)
return ret;
return MACSUCCESS;
}
static inline void __fwcmd_wq_insert(struct h2c_buf *new_h2cb,
struct h2c_buf *prev, struct h2c_buf *next,
struct fwcmd_wkb_head *list)
{
new_h2cb->next = next;
new_h2cb->prev = prev;
next->prev = new_h2cb;
prev->next = new_h2cb;
list->qlen++;
}
static inline void __fwcmd_wq_before(struct fwcmd_wkb_head *list,
struct h2c_buf *next,
struct h2c_buf *new_h2cb)
{
__fwcmd_wq_insert(new_h2cb, next->prev, next, list);
}
static inline void __fwcmd_wq_tail(struct fwcmd_wkb_head *list,
struct h2c_buf *new_h2cb)
{
__fwcmd_wq_before(list, (struct h2c_buf *)list, new_h2cb);
}
u32 fwcmd_wq_enqueue(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb)
{
struct fwcmd_wkb_head *list_head = &fwcmd_wq_head;
if (list_head->qlen > FWCMD_WQ_MAX_JOB_NUM) {
PLTFM_MSG_WARN("[WARN]fwcmd work queue full\n");
return MACBUFALLOC;
}
/* worq queue doesn't need wd body */
h2cb_pull(h2cb, WD_BODY_LEN);
PLTFM_MUTEX_LOCK(&list_head->lock);
__fwcmd_wq_tail(list_head, h2cb);
PLTFM_MUTEX_UNLOCK(&list_head->lock);
return MACSUCCESS;
}
static inline void __fwcmd_wq_unlink(struct h2c_buf *h2cb,
struct fwcmd_wkb_head *list)
{
struct h2c_buf *next, *prev;
list->qlen--;
next = h2cb->next;
prev = h2cb->prev;
h2cb->prev = NULL;
h2cb->next = NULL;
next->prev = prev;
prev->next = next;
}
struct h2c_buf *fwcmd_wq_dequeue(struct mac_ax_adapter *adapter, u32 id)
{
struct fwcmd_wkb_head *list_head = &fwcmd_wq_head;
struct h2c_buf *h2cb;
u32 hdr0;
u16 type = GET_FWCMD_TYPE(id);
u16 cat = GET_FWCMD_CAT(id);
u16 _class_ = GET_FWCMD_CLASS(id);
u16 func = GET_FWCMD_FUNC(id);
PLTFM_MUTEX_LOCK(&list_head->lock);
for (h2cb = list_head->next; h2cb->next != list_head->next;
h2cb = h2cb->next) {
hdr0 = ((struct fwcmd_hdr *)h2cb->data)->hdr0;
hdr0 = le32_to_cpu(hdr0);
if (type == GET_FIELD(hdr0, H2C_HDR_DEL_TYPE) &&
cat == GET_FIELD(hdr0, H2C_HDR_CAT) &&
_class_ == GET_FIELD(hdr0, H2C_HDR_CLASS) &&
func == GET_FIELD(hdr0, H2C_HDR_FUNC)) {
__fwcmd_wq_unlink(h2cb, list_head);
PLTFM_MUTEX_UNLOCK(&list_head->lock);
return h2cb;
}
}
PLTFM_MUTEX_UNLOCK(&list_head->lock);
PLTFM_MSG_ERR("[ERR]cannot find wq item: %X\n", id);
return NULL;
}
u32 fwcmd_wq_idle(struct mac_ax_adapter *adapter, u32 id)
{
struct fwcmd_wkb_head *list_head = &fwcmd_wq_head;
struct h2c_buf *h2cb;
PLTFM_MUTEX_LOCK(&list_head->lock);
for (h2cb = list_head->next; h2cb->next != list_head->next;
h2cb = h2cb->next) {
if (h2cb->id == id) {
PLTFM_MUTEX_UNLOCK(&list_head->lock);
return MACWQBUSY;
}
}
PLTFM_MUTEX_UNLOCK(&list_head->lock);
return MACSUCCESS;
}
#endif
static u32 c2h_fwi_cmd_log(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
#if MAC_AX_FEATURE_DBGDEC
u8 syntax_1 = 0, syntax_2 = 0;
if ((len - FWCMD_HDR_LEN) >= 11) {
syntax_1 = *(buf + FWCMD_HDR_LEN);
syntax_2 = *(buf + FWCMD_HDR_LEN + 1);
}
//PLTFM_MSG_WARN("C2H encoded log syntax_1 %x, syntax_2 %x", syntax_1, syntax_2);
if (syntax_1 == 0xa5 && syntax_2 == 0xa5) {
//PLTFM_MSG_WARN("C2H encoded log");
fw_log_dump(adapter, buf, len, info);
} else {
if (buf[len - 1] != '\0')
buf[len - 1] = '\0';
PLTFM_MSG_WARN("C2H log: %s", (char *)(buf + FWCMD_HDR_LEN));
}
#else
if (buf[len - 1] != '\0')
buf[len - 1] = '\0';
PLTFM_MSG_WARN("C2H log: %s", (char *)(buf + FWCMD_HDR_LEN));
#endif
return MACSUCCESS;
}
static u32 c2h_wow_rcv_ack_hdl(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *info)
{
u8 *state;
switch (info->c2h_func) {
case FWCMD_H2C_FUNC_AOAC_REPORT_REQ:
state = &adapter->sm.aoac_rpt;
break;
default:
return MACSUCCESS;
}
if (*state == MAC_AX_AOAC_RPT_H2C_SENDING)
*state = MAC_AX_AOAC_RPT_H2C_RCVD;
return MACSUCCESS;
}
static u32 c2h_fwofld_rcv_ack_hdl(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *info)
{
u8 *state;
switch (info->c2h_func) {
case FWCMD_H2C_FUNC_WRITE_OFLD:
state = &adapter->sm.write_h2c;
break;
case FWCMD_H2C_FUNC_CONF_OFLD:
state = &adapter->sm.conf_h2c;
break;
case FWCMD_H2C_FUNC_PACKET_OFLD:
state = &adapter->sm.pkt_ofld;
break;
case FWCMD_H2C_FUNC_READ_OFLD:
state = &adapter->sm.read_h2c;
break;
case FWCMD_H2C_FUNC_DUMP_EFUSE:
state = &adapter->sm.efuse_ofld;
break;
default:
return MACSUCCESS;
}
if (*state == MAC_AX_OFLD_H2C_SENDING)
*state = MAC_AX_OFLD_H2C_RCVD;
return MACSUCCESS;
}
static u32 c2h_fwi_rev_ack(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u32 data = *(u32 *)(buf + FWCMD_HDR_LEN);
u32 ret;
u32 cat;
data = le32_to_cpu(data);
cat = GET_FIELD(data, FWCMD_C2H_REC_ACK_CAT);
if (cat == FWCMD_H2C_CAT_OUTSRC)
return MACSUCCESS;
info->c2h_cat = GET_FIELD(data, FWCMD_C2H_REC_ACK_CAT);
info->c2h_class = GET_FIELD(data, FWCMD_C2H_REC_ACK_CLASS);
info->c2h_func = GET_FIELD(data, FWCMD_C2H_REC_ACK_FUNC);
info->h2c_seq = GET_FIELD(data, FWCMD_C2H_REC_ACK_H2C_SEQ);
adapter->fw_info.rec_seq = info->h2c_seq;
info->type_rec_ack = 1;
if (info->c2h_cat == FWCMD_H2C_CAT_MAC) {
switch (info->c2h_class) {
case FWCMD_H2C_CL_WOW:
ret = c2h_wow_rcv_ack_hdl(adapter, info);
if (ret)
return ret;
break;
case FWCMD_H2C_CL_FW_OFLD:
ret = c2h_fwofld_rcv_ack_hdl(adapter, info);
if (ret)
return ret;
break;
default:
return MACSUCCESS;
}
}
return MACSUCCESS;
}
static u32 c2h_fwofld_done_ack_hdl(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *info)
{
struct mac_ax_state_mach *sm = &adapter->sm;
struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info;
switch (info->c2h_func) {
case FWCMD_H2C_FUNC_WRITE_OFLD:
if (sm->write_h2c == MAC_AX_OFLD_H2C_RCVD) {
if (info->h2c_return == MACSUCCESS)
sm->write_h2c = MAC_AX_OFLD_H2C_IDLE;
else
sm->write_h2c = MAC_AX_OFLD_H2C_ERROR;
}
break;
case FWCMD_H2C_FUNC_CONF_OFLD:
if (sm->conf_h2c == MAC_AX_OFLD_H2C_RCVD) {
if (info->h2c_return == MACSUCCESS)
sm->conf_h2c = MAC_AX_OFLD_H2C_IDLE;
else
sm->conf_h2c = MAC_AX_OFLD_H2C_ERROR;
}
break;
case FWCMD_H2C_FUNC_PACKET_OFLD:
if (sm->pkt_ofld == MAC_AX_OFLD_H2C_RCVD) {
if (info->h2c_return == MACSUCCESS) {
if (ofld_info->last_op == PKT_OFLD_OP_READ)
sm->pkt_ofld = MAC_AX_OFLD_H2C_DONE;
else
sm->pkt_ofld = MAC_AX_OFLD_H2C_IDLE;
} else {
sm->pkt_ofld = MAC_AX_OFLD_H2C_ERROR;
}
} else {
PLTFM_MSG_ERR("cant set pkt ofld state since no recv ack is received.");
}
break;
case FWCMD_H2C_FUNC_READ_OFLD:
if (sm->read_h2c == MAC_AX_OFLD_H2C_RCVD) {
if (info->h2c_return == MACSUCCESS)
sm->read_h2c = MAC_AX_OFLD_H2C_DONE;
else
sm->read_h2c = MAC_AX_OFLD_H2C_ERROR;
}
break;
case FWCMD_H2C_FUNC_DUMP_EFUSE:
if (sm->efuse_ofld == MAC_AX_OFLD_H2C_RCVD) {
if (info->h2c_return == MACSUCCESS)
sm->efuse_ofld = MAC_AX_OFLD_H2C_DONE;
else
sm->efuse_ofld = MAC_AX_OFLD_H2C_ERROR;
}
break;
default:
break;
}
return MACSUCCESS;
}
static u32 c2h_role_done_ack_hdl(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *info)
{
struct mac_ax_state_mach *sm = &adapter->sm;
if (info->c2h_class == FWCMD_H2C_CL_MEDIA_RPT &&
info->c2h_func == FWCMD_H2C_FUNC_FWROLE_MAINTAIN) {
if (info->h2c_return == MACSUCCESS) {
sm->role_stat = MAC_AX_ROLE_ALOC_SUCC;
} else {
PLTFM_MSG_ERR("[ERR]role_maintain: alloc failed\n");
sm->role_stat = MAC_AX_ROLE_ALOC_FAIL;
return MACROLEALOCFL;
}
} else if (info->c2h_class == FWCMD_H2C_CL_MEDIA_RPT &&
info->c2h_func == FWCMD_H2C_FUNC_JOININFO) {
if (info->h2c_return == MACSUCCESS) {
sm->role_stat = MAC_AX_ROLE_INIT_SUCC;
} else {
PLTFM_MSG_ERR("[ERR]role_join: init failed\n");
sm->role_stat = MAC_AX_ROLE_INIT_FAIL;
return MACROLEINITFL;
}
} else if (info->c2h_class == FWCMD_H2C_CL_ADDR_CAM_UPDATE &&
info->c2h_func == FWCMD_H2C_FUNC_ADDRCAM_INFO) {
if (info->h2c_return == MACSUCCESS) {
sm->role_stat = MAC_AX_ROLE_HW_UPD_SUCC;
} else {
PLTFM_MSG_ERR("[ERR]ADDR_CAM: upd failed\n");
sm->role_stat = MAC_AX_ROLE_HW_UPD_FAIL;
return MACROLEHWUPDFL;
}
}
return MACSUCCESS;
}
static u32 c2h_ps_done_ack_hdl(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *info)
{
struct mac_ax_state_mach *sm = &adapter->sm;
u8 p2pid;
u32 ret;
switch (info->c2h_func) {
case FWCMD_H2C_FUNC_P2P_ACT:
if (sm->p2p_stat != MAC_AX_P2P_ACT_BUSY) {
PLTFM_MSG_ERR("[ERR]p2p act dack stat err %d\n",
sm->p2p_stat);
return MACPROCERR;
}
if (info->h2c_return != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]p2p act dack ret %d\n",
info->h2c_return);
sm->p2p_stat = MAC_AX_P2P_ACT_FAIL;
break;
}
p2pid = P2PID_INVALID;
ret = get_wait_dack_p2pid(adapter, &p2pid);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]p2p act dack get wait id %d\n", ret);
return ret;
}
if (p2pid != P2PID_INVALID) {
if (adapter->p2p_info[p2pid].run) {
PLTFM_MEMSET(&adapter->p2p_info[p2pid], 0,
sizeof(struct mac_ax_p2p_info));
} else {
adapter->p2p_info[p2pid].run = 1;
adapter->p2p_info[p2pid].wait_dack = 0;
}
} else {
PLTFM_MSG_ERR("[ERR]p2p act dack no wait id\n");
}
sm->p2p_stat = MAC_AX_P2P_ACT_IDLE;
break;
case FWCMD_H2C_FUNC_P2P_MACID_CTRL:
if (sm->p2p_stat != MAC_AX_P2P_ACT_BUSY) {
PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack stat err %d\n",
sm->p2p_stat);
return MACPROCERR;
}
if (info->h2c_return != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack ret %d\n",
info->h2c_return);
sm->p2p_stat = MAC_AX_P2P_ACT_FAIL;
break;
}
p2pid = P2PID_INVALID;
ret = get_wait_dack_p2pid(adapter, &p2pid);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack get wait id %d\n",
ret);
return ret;
}
if (p2pid != P2PID_INVALID) {
if (adapter->p2p_info[p2pid].run) {
adapter->p2p_info[p2pid].wait_dack = 0;
} else {
PLTFM_MSG_ERR("[ERR]p2p%d macid ctrl dack not run\n",
p2pid);
}
} else {
PLTFM_MSG_ERR("[ERR]p2p macid ctrl dack no wait id\n");
}
sm->p2p_stat = MAC_AX_P2P_ACT_IDLE;
break;
default:
break;
}
return MACSUCCESS;
}
static u32 c2h_fwi_done_ack(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u32 data = *(u32 *)(buf + FWCMD_HDR_LEN);
u32 ret;
u32 cat;
data = le32_to_cpu(data);
cat = GET_FIELD(data, FWCMD_C2H_REC_ACK_CAT);
if (cat == FWCMD_H2C_CAT_OUTSRC)
return MACSUCCESS;
info->c2h_cat = GET_FIELD(data, FWCMD_C2H_DONE_ACK_CAT);
info->c2h_class = GET_FIELD(data, FWCMD_C2H_DONE_ACK_CLASS);
info->c2h_func = GET_FIELD(data, FWCMD_C2H_DONE_ACK_FUNC);
info->h2c_return = GET_FIELD(data, FWCMD_C2H_DONE_ACK_H2C_RETURN);
info->h2c_seq = GET_FIELD(data, FWCMD_C2H_DONE_ACK_H2C_SEQ);
info->type_done_ack = 1;
if (info->c2h_cat == FWCMD_H2C_CAT_MAC) {
if (info->c2h_class == FWCMD_H2C_CL_FW_OFLD) {
ret = c2h_fwofld_done_ack_hdl(adapter, info);
if (ret != MACSUCCESS)
return ret;
} else if (info->c2h_class == FWCMD_H2C_CL_PS) {
ret = c2h_ps_done_ack_hdl(adapter, info);
if (ret != MACSUCCESS)
return ret;
} else if (info->c2h_class == FWCMD_H2C_CL_MEDIA_RPT ||
info->c2h_class == FWCMD_H2C_CL_ADDR_CAM_UPDATE) {
ret = c2h_role_done_ack_hdl(adapter, info);
if (ret != MACSUCCESS)
return ret;
}
}
return MACSUCCESS;
}
static u32 c2h_fwi_bcn_stats(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
return MACSUCCESS;
}
static u32 c2h_fwi_bcn_csazero(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_fw_info_cmd[] = {
{FWCMD_C2H_FUNC_REC_ACK, c2h_fwi_rev_ack},
{FWCMD_C2H_FUNC_DONE_ACK, c2h_fwi_done_ack},
{FWCMD_C2H_FUNC_C2H_LOG, c2h_fwi_cmd_log},
{FWCMD_C2H_FUNC_BCN_CNT, c2h_fwi_bcn_stats},
{FWCMD_C2H_FUNC_BCN_CSAZERO, c2h_fwi_bcn_csazero},
{FWCMD_C2H_FUNC_NULL, NULL},
};
u32 c2h_fw_info(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_fw_info_cmd;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null func handler id: %X", func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
static u32 c2h_dump_efuse_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
struct mac_ax_efuse_ofld_info *ofld_info = &adapter->efuse_ofld_info;
u32 size;
if (adapter->sm.efuse_ofld != MAC_AX_OFLD_H2C_RCVD) {
PLTFM_MSG_ERR("[ERR]not cmd sending\n");
return MACPROCERR;
}
size = adapter->hw_info->efuse_size;
if (!ofld_info->buf) {
ofld_info->buf = (u8 *)PLTFM_MALLOC(size);
if (!ofld_info->buf) {
adapter->sm.efuse = MAC_AX_EFUSE_IDLE;
return MACBUFALLOC;
}
}
PLTFM_MEMCPY(ofld_info->buf, buf + FWCMD_HDR_LEN, size);
adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_DONE;
return MACSUCCESS;
}
static u32 c2h_read_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
struct mac_ax_read_ofld_value *value_info = &adapter->read_ofld_value;
u32 hdr1;
u16 read_len;
u8 *read_buff;
if (value_info->buf)
PLTFM_FREE(value_info->buf, value_info->len);
hdr1 = ((struct fwcmd_hdr *)buf)->hdr1;
hdr1 = le32_to_cpu(hdr1);
read_len = GET_FIELD(hdr1, C2H_HDR_TOTAL_LEN) - FWCMD_HDR_LEN;
read_buff = (u8 *)PLTFM_MALLOC(read_len);
if (!read_buff)
return MACBUFALLOC;
PLTFM_MEMCPY(read_buff, buf + FWCMD_HDR_LEN, read_len);
value_info->len = read_len;
value_info->buf = read_buff;
return MACSUCCESS;
}
static u32 c2h_pkt_ofld_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info;
struct mac_ax_pkt_ofld_pkt *ofld_pkt = &adapter->pkt_ofld_pkt;
u32 c2h_content = *(u32 *)(buf + FWCMD_HDR_LEN);
u16 pkt_len;
u8 id, pkt_op;
u8 *pkt_buff;
u8 *pkt_content;
c2h_content = le32_to_cpu(c2h_content);
pkt_op = GET_FIELD(c2h_content, FWCMD_C2H_PKT_OFLD_RSP_PKT_OP);
pkt_len = GET_FIELD(c2h_content, FWCMD_C2H_PKT_OFLD_RSP_PKT_LENGTH);
id = GET_FIELD(c2h_content, FWCMD_C2H_PKT_OFLD_RSP_PKT_ID);
PLTFM_MSG_TRACE("get pkt ofld rsp. pkt_op: %d, pkt_len: %d, id: %d\n", pkt_op, pkt_len, id);
switch (pkt_op) {
case PKT_OFLD_OP_ADD:
if (pkt_len != 0) {
ofld_info->id_bitmap[id >> 3] |= (1 << (id & 7));
ofld_info->free_id_count--;
ofld_info->used_id_count++;
}
break;
case PKT_OFLD_OP_DEL:
if (pkt_len != 0) {
ofld_info->id_bitmap[id >> 3] &= ~(1 << (id & 7));
ofld_info->free_id_count++;
ofld_info->used_id_count--;
}
break;
case PKT_OFLD_OP_READ:
if (pkt_len != 0) {
if (ofld_pkt->pkt)
PLTFM_FREE(ofld_pkt->pkt, ofld_pkt->pkt_len);
pkt_buff = (u8 *)PLTFM_MALLOC(pkt_len);
if (!pkt_buff)
return MACBUFALLOC;
pkt_content = buf + FWCMD_HDR_LEN;
pkt_content += sizeof(struct mac_ax_pkt_ofld_hdr);
PLTFM_MEMCPY(pkt_buff, pkt_content, pkt_len);
ofld_pkt->pkt_id = id;
ofld_pkt->pkt_len = pkt_len;
ofld_pkt->pkt = pkt_buff;
}
break;
default:
PLTFM_MSG_ERR("[ERR]invalid packet offload op: %d", pkt_op);
break;
}
return MACSUCCESS;
}
static u32 c2h_beacon_resend_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
return MACSUCCESS;
}
static u32 c2h_macid_pause_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
return MACSUCCESS;
}
static u32 c2h_tx_duty_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
u32 content = *(u32 *)(buf + FWCMD_HDR_LEN);
struct mac_ax_tx_duty_ofld_info ofld_info;
content = le32_to_cpu(content);
ofld_info.timer_err =
GET_FIELD(content, FWCMD_C2H_TX_DUTY_RPT_TIMER_ERR);
if (ofld_info.timer_err)
PLTFM_MSG_ERR("[ERR]Tx duty FW timer error\n");
return MACSUCCESS;
}
static u32 c2h_tsf32_togl_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
struct fwcmd_tsf32_togl_rpt rpt;
struct mac_ax_t32_togl_rpt *out_rpt;
u8 band, port;
if (!buf) {
PLTFM_MSG_ERR("[ERR]tsf32 togl rpt no buf\n");
return MACNPTR;
}
rpt.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN));
rpt.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4));
rpt.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8));
band = rpt.dword0 & FWCMD_C2H_TSF32_TOGL_RPT_BAND;
if (band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("[ERR]invalid band %d in tsf32 togl rpt\n", band);
return MACNOITEM;
}
port = GET_FIELD(rpt.dword0, FWCMD_C2H_TSF32_TOGL_RPT_PORT);
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port %d in tsf32 togl rpt\n", port);
return MACNOITEM;
}
out_rpt = &adapter->t32_togl_rpt[get_bp_idx(band, port)];
out_rpt->band = band;
out_rpt->port = port;
out_rpt->status = GET_FIELD(rpt.dword0, FWCMD_C2H_TSF32_TOGL_RPT_STATUS);
out_rpt->early = GET_FIELD(rpt.dword0, FWCMD_C2H_TSF32_TOGL_RPT_EARLY);
out_rpt->tsf_l = GET_FIELD(rpt.dword1, FWCMD_C2H_TSF32_TOGL_RPT_TSF_L);
out_rpt->tsf_h = GET_FIELD(rpt.dword2, FWCMD_C2H_TSF32_TOGL_RPT_TSF_H);
out_rpt->valid = 1;
return MACSUCCESS;
}
static u32 c2h_cmd_ofld_rsp_hdl(struct mac_ax_adapter *adapter, u8 *buf,
u32 len, struct rtw_c2h_info *info)
{
struct fwcmd_cmd_ofld_rsp rsp;
struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info;
struct mac_ax_state_mach *sm = &adapter->sm;
if (!buf) {
PLTFM_MSG_ERR("[ERR]tsf32 togl rpt no buf\n");
return MACNPTR;
}
rsp.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN));
ofld_info->result = rsp.dword0 & FWCMD_C2H_CMD_OFLD_RSP_RESULT;
if (ofld_info->result) {
PLTFM_MSG_ERR("%s: IO offload fail!!!\n", __func__);
rsp.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4));
rsp.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8));
rsp.dword3 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 12));
PLTFM_MSG_ERR("offset = %x\n", rsp.dword1);
PLTFM_MSG_ERR("expected val = %x\n", rsp.dword2);
PLTFM_MSG_ERR("read val = %x\n", rsp.dword3);
}
if (sm->cmd_state != MAC_AX_CMD_OFLD_SENDING)
PLTFM_MSG_ERR("%s: IO offload stat err\n", __func__);
else
sm->cmd_state = MAC_AX_CMD_OFLD_RCVD;
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_fw_ofld_cmd[] = {
{FWCMD_C2H_FUNC_EFUSE_DUMP, c2h_dump_efuse_hdl},
{FWCMD_C2H_FUNC_READ_RSP, c2h_read_rsp_hdl},
{FWCMD_C2H_FUNC_PKT_OFLD_RSP, c2h_pkt_ofld_rsp_hdl},
{FWCMD_C2H_FUNC_BEACON_RESEND, c2h_beacon_resend_hdl},
{FWCMD_C2H_FUNC_MACID_PAUSE, c2h_macid_pause_hdl},
{FWCMD_C2H_FUNC_TSF32_TOGL_RPT, c2h_tsf32_togl_rpt_hdl},
{FWCMD_C2H_FUNC_CMD_OFLD_RSP, c2h_cmd_ofld_rsp_hdl},
{FWCMD_C2H_FUNC_TX_DUTY_RPT, c2h_tx_duty_hdl},
{FWCMD_C2H_FUNC_NULL, NULL}
};
u32 c2h_fw_ofld(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_fw_ofld_cmd;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null func handler id: %X", func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_twt(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
return MACSUCCESS;
}
u32 c2h_wow_aoac_report_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct mac_ax_wowlan_info *wowlan_info = &adapter->wowlan_info;
u8 *c2h_content = buf + FWCMD_HDR_LEN;
if (adapter->sm.aoac_rpt != MAC_AX_AOAC_RPT_H2C_RCVD)
return MACPROCERR;
if (!wowlan_info->aoac_report)
return MACBUFALLOC;
PLTFM_MEMCPY(wowlan_info->aoac_report, c2h_content, sizeof(struct mac_ax_aoac_report));
adapter->sm.aoac_rpt = MAC_AX_AOAC_RPT_H2C_DONE;
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_wow_cmd[] = {
{FWCMD_C2H_FUNC_AOAC_REPORT, c2h_wow_aoac_report_hdl},
{FWCMD_C2H_FUNC_NULL, NULL},
};
u32 c2h_wow(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_wow_cmd;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null func handler id: %X", func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_mcc_rcv_ack_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct mac_ax_state_mach *sm = &adapter->sm;
u32 c2h_content = *(u32 *)(buf + FWCMD_HDR_LEN);
u8 group, h2c_func;
c2h_content = le32_to_cpu(c2h_content);
group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_RCV_ACK_GROUP);
h2c_func = GET_FIELD(c2h_content, FWCMD_C2H_MCC_RCV_ACK_H2C_FUNC);
if (h2c_func <= FWCMD_H2C_FUNC_RESET_MCC_GROUP) {
PLTFM_MSG_TRACE("[TRACE]%s: MCC group H2C rcv ack\n",
__func__);
if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_SENT) {
sm->mcc_group[group] = MAC_AX_MCC_STATE_H2C_RCVD;
PLTFM_MSG_TRACE("[TRACE]%s: MCC group %d state: %d\n",
__func__, group,
MAC_AX_MCC_STATE_H2C_RCVD);
}
} else if (h2c_func <= FWCMD_H2C_FUNC_MCC_SET_DURATION) {
PLTFM_MSG_TRACE("[TRACE]%s: MCC request H2C rcv ack\n",
__func__);
if (sm->mcc_request[group] == MAC_AX_MCC_REQ_H2C_SENT) {
sm->mcc_request[group] = MAC_AX_MCC_REQ_H2C_RCVD;
PLTFM_MSG_TRACE("[TRACE]%s: MCC group %d state: %d\n",
__func__, group,
MAC_AX_MCC_REQ_H2C_RCVD);
}
} else {
PLTFM_MSG_ERR("[ERR]%s: invalid MCC H2C func %d\n",
__func__, h2c_func);
return MACNOITEM;
}
return MACSUCCESS;
}
u32 c2h_mcc_req_ack_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct mac_ax_state_mach *sm = &adapter->sm;
u32 c2h_content = *(u32 *)(buf + FWCMD_HDR_LEN);
u8 group, h2c_func, h2c_return;
c2h_content = le32_to_cpu(c2h_content);
group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_REQ_ACK_GROUP);
h2c_func = GET_FIELD(c2h_content, FWCMD_C2H_MCC_REQ_ACK_H2C_FUNC);
h2c_return = GET_FIELD(c2h_content, FWCMD_C2H_MCC_REQ_ACK_H2C_RETURN);
PLTFM_MSG_TRACE("[TRACE]%s: group: %d, h2c_func: %d, h2c_return: %d\n",
__func__, group, h2c_func, h2c_return);
if (h2c_func < FWCMD_H2C_FUNC_MCC_REQ_TSF) {
PLTFM_MSG_ERR("[ERR]%s: invalid MCC H2C func: %d\n",
__func__, h2c_func);
return MACNOITEM;
}
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr req state: %d\n",
__func__, group, sm->mcc_request[group]);
if (sm->mcc_request[group] == MAC_AX_MCC_REQ_H2C_RCVD) {
if (h2c_return == 0) {
if (h2c_func == FWCMD_H2C_FUNC_MCC_REQ_TSF)
sm->mcc_request[group] = MAC_AX_MCC_REQ_DONE;
else
sm->mcc_request[group] = MAC_AX_MCC_REQ_IDLE;
} else {
sm->mcc_request[group] = MAC_AX_MCC_REQ_FAIL;
PLTFM_MSG_ERR("[ERR]%s: MCC H2C func %d fail: %d\n",
__func__, h2c_func, h2c_return);
}
}
return MACSUCCESS;
}
u32 c2h_mcc_tsf_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info;
struct fwcmd_mcc_tsf_rpt *tsf_rpt;
u32 c2h_content;
u32 tsf;
u8 macid_x, macid_y, group;
PLTFM_MSG_TRACE("[TRACE]%s: mcc tsf report received\n", __func__);
tsf_rpt = (struct fwcmd_mcc_tsf_rpt *)(buf + FWCMD_HDR_LEN);
c2h_content = tsf_rpt->dword0;
c2h_content = le32_to_cpu(c2h_content);
group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_TSF_RPT_GROUP);
macid_x = GET_FIELD(c2h_content, FWCMD_C2H_MCC_TSF_RPT_MACID_X);
macid_y = GET_FIELD(c2h_content, FWCMD_C2H_MCC_TSF_RPT_MACID_Y);
PLTFM_MSG_TRACE("[TRACE]%s: group: %d, macid_x: %d, macid_y: %d\n",
__func__, group, macid_x, macid_y);
mcc_info->groups[group].macid_x = macid_x;
mcc_info->groups[group].macid_y = macid_y;
tsf = tsf_rpt->dword1;
tsf = le32_to_cpu(tsf);
mcc_info->groups[group].tsf_x_low = tsf;
tsf = tsf_rpt->dword2;
tsf = le32_to_cpu(tsf);
mcc_info->groups[group].tsf_x_high = tsf;
tsf = tsf_rpt->dword3;
tsf = le32_to_cpu(tsf);
mcc_info->groups[group].tsf_y_low = tsf;
tsf = tsf_rpt->dword4;
tsf = le32_to_cpu(tsf);
mcc_info->groups[group].tsf_y_high = tsf;
PLTFM_MSG_TRACE("[TRACE]%s: tsf_x_high: 0x%x, tsf_x_low: 0x%x\n",
__func__, mcc_info->groups[group].tsf_x_high,
mcc_info->groups[group].tsf_x_low);
PLTFM_MSG_TRACE("[TRACE]%s: tsf_y_high: 0x%x, tsf_y_low: 0x%x\n",
__func__, mcc_info->groups[group].tsf_y_high,
mcc_info->groups[group].tsf_y_low);
return MACSUCCESS;
}
u32 c2h_mcc_status_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info;
struct mac_ax_state_mach *sm = &adapter->sm;
struct fwcmd_mcc_status_rpt *mcc_rpt;
u32 c2h_content;
u32 tsf_low;
u32 tsf_high;
u8 group, status, macid;
PLTFM_MSG_TRACE("[TRACE]%s: mcc status report received\n", __func__);
mcc_rpt = (struct fwcmd_mcc_status_rpt *)(buf + FWCMD_HDR_LEN);
c2h_content = mcc_rpt->dword0;
tsf_low = mcc_rpt->dword1;
tsf_high = mcc_rpt->dword2;
c2h_content = le32_to_cpu(c2h_content);
group = GET_FIELD(c2h_content, FWCMD_C2H_MCC_STATUS_RPT_GROUP);
macid = GET_FIELD(c2h_content, FWCMD_C2H_MCC_STATUS_RPT_MACID);
status = GET_FIELD(c2h_content, FWCMD_C2H_MCC_STATUS_RPT_STATUS);
PLTFM_MSG_TRACE("[TRACE]%s: mcc group: %d, macid: %d, status: %d\n",
__func__, group, macid, status);
switch (status) {
case MAC_AX_MCC_ADD_ROLE_OK:
if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) {
sm->mcc_group[group] = MAC_AX_MCC_ADD_DONE;
PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d add done\n",
__func__, group);
}
break;
case MAC_AX_MCC_START_GROUP_OK:
if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) {
sm->mcc_group[group] = MAC_AX_MCC_START_DONE;
PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d start done\n",
__func__, group);
}
break;
case MAC_AX_MCC_STOP_GROUP_OK:
sm->mcc_group[group] = MAC_AX_MCC_STOP_DONE;
PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d stop done\n",
__func__, group);
break;
case MAC_AX_MCC_DEL_GROUP_OK:
sm->mcc_group[group] = MAC_AX_MCC_EMPTY;
PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d empty\n",
__func__, group);
break;
case MAC_AX_MCC_RESET_GROUP_OK:
if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) {
sm->mcc_group[group] = MAC_AX_MCC_EMPTY;
PLTFM_MSG_TRACE("[TRACE]%s: mcc group %d empty\n",
__func__, group);
}
break;
case MAC_AX_MCC_ADD_ROLE_FAIL:
case MAC_AX_MCC_START_GROUP_FAIL:
case MAC_AX_MCC_STOP_GROUP_FAIL:
case MAC_AX_MCC_DEL_GROUP_FAIL:
case MAC_AX_MCC_RESET_GROUP_FAIL:
if (sm->mcc_group[group] == MAC_AX_MCC_STATE_H2C_RCVD) {
PLTFM_MSG_ERR("[ERR]%s: mcc group %d fail status: %d\n",
__func__, group, status);
sm->mcc_group[group] = MAC_AX_MCC_STATE_ERROR;
}
break;
default:
break;
}
tsf_low = le32_to_cpu(tsf_low);
tsf_high = le32_to_cpu(tsf_high);
mcc_info->groups[group].rpt_status = status;
mcc_info->groups[group].rpt_macid = macid;
mcc_info->groups[group].rpt_tsf_low = tsf_low;
mcc_info->groups[group].rpt_tsf_high = tsf_high;
PLTFM_MSG_TRACE("[TRACE]%s: tsf_high: 0x%x, tsf_low: 0x%x\n",
__func__, tsf_high, tsf_low);
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_mcc_cmd[] = {
{FWCMD_C2H_FUNC_MCC_RCV_ACK, c2h_mcc_rcv_ack_hdl},
{FWCMD_C2H_FUNC_MCC_REQ_ACK, c2h_mcc_req_ack_hdl},
{FWCMD_C2H_FUNC_MCC_TSF_RPT, c2h_mcc_tsf_rpt_hdl},
{FWCMD_C2H_FUNC_MCC_STATUS_RPT, c2h_mcc_status_rpt_hdl},
{FWCMD_C2H_FUNC_NULL, NULL},
};
u32 c2h_mcc(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_mcc_cmd;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
PLTFM_MSG_TRACE("[TRACE]%s: func: %d\n", __func__, func);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]%s: null func handler id: %X",
__func__, func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_rx_dbg_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
PLTFM_MSG_ERR("[ERR]%s: FW encounter Rx problem!\n", __func__);
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_fw_dbg_cmd[] = {
{FWCMD_C2H_FUNC_RX_DBG, c2h_rx_dbg_hdl},
{FWCMD_C2H_FUNC_NULL, NULL},
};
u32 c2h_fw_dbg(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_fw_dbg_cmd;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
PLTFM_MSG_TRACE("[TRACE]%s: func: %d\n", __func__, func);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]%s: null func handler id: %X",
__func__, func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_wps_rpt(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
PLTFM_MSG_TRACE("recevied wps report\n");
return MACSUCCESS;
}
static u32 c2h_misc_ccxrpt(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_misc[] = {
{FWCMD_C2H_FUNC_WPS_RPT, c2h_wps_rpt},
{FWCMD_C2H_FUNC_CCXRPT, c2h_misc_ccxrpt},
{FWCMD_C2H_FUNC_NULL, NULL},
};
static u32 c2h_cl_misc(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_misc;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null func handler id: %X", func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_fast_ch_sw_rpt_hdl(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u32 *c2h_content;
u32 *rpt_status;
PLTFM_MSG_TRACE("[HM][C2H][FCS] get rpt func\n");
adapter->fast_ch_sw_info.busy = 0;
c2h_content = (u32 *)(buf + FWCMD_HDR_LEN);
rpt_status = &adapter->fast_ch_sw_info.status;
PLTFM_MEMCPY(rpt_status, c2h_content, sizeof(u32));
PLTFM_MSG_TRACE("[HM][C2H][FCS] Report Status: 0x%x\n", adapter->fast_ch_sw_info.status);
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_fast_ch_sw_cmd[] = {
{FWCMD_C2H_FUNC_FCS_RPT, c2h_fast_ch_sw_rpt_hdl},
{FWCMD_C2H_FUNC_NULL, NULL},
};
u32 c2h_fast_ch_sw(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
u32 hdr0;
u32 func;
u32 (*handler)(struct mac_ax_adapter *adpater, u8 *buf,
u32 len, struct rtw_c2h_info *info);
struct c2h_proc_func *proc;
proc = c2h_proc_fast_ch_sw_cmd;
handler = NULL;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR][%s]: sent id = %x", __func__, func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 c2h_port_init_stat(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct fwcmd_port_init_stat stat;
struct mac_ax_port_info *pinfo;
u8 band, port;
u32 ret, tmp32;
stat.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN));
stat.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4));
stat.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8));
band = stat.dword0 & FWCMD_C2H_PORT_INIT_STAT_BAND;
if (band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("[ERR]invalid band %d in port init stat\n", band);
return MACNOITEM;
}
port = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_PORT);
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port %d in port init stat\n", port);
return MACNOITEM;
}
pinfo = &adapter->port_info[get_bp_idx(band, port)];
ret = GET_FIELD(stat.dword2, FWCMD_C2H_PORT_INIT_STAT_RET);
if (ret != C2H_MPORT_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d init fail: ret %d\n",
band, port, ret);
tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_STEP);
PLTFM_MSG_ERR("[ERR]B%dP%d init fail: step %d\n",
band, port, tmp32);
tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_CFG_MBID_IDX);
PLTFM_MSG_ERR("[ERR]B%dP%d init fail: cfg mbid %d\n",
band, port, tmp32);
tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_INIT_STAT_CFG_TYPE);
PLTFM_MSG_ERR("[ERR]B%dP%d init fail: cfg type %d\n",
band, port, tmp32);
tmp32 = GET_FIELD(stat.dword1, FWCMD_C2H_PORT_INIT_STAT_CFG_VAL);
PLTFM_MSG_ERR("[ERR]B%dP%d init fail: cfg val %d\n",
band, port, tmp32);
pinfo->h2c_sm = MAC_AX_PORT_H2C_FAIL;
} else {
pinfo->h2c_sm = MAC_AX_PORT_H2C_IDLE;
}
return MACSUCCESS;
}
u32 c2h_port_cfg_stat(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct fwcmd_port_cfg_stat stat;
struct mac_ax_port_info *pinfo;
u8 band, port, mbssid;
u32 ret, tmp32;
stat.dword0 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN));
stat.dword1 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 4));
stat.dword2 = le32_to_cpu(*(u32 *)(buf + FWCMD_HDR_LEN + 8));
band = stat.dword0 & FWCMD_C2H_PORT_CFG_STAT_BAND;
if (band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("[ERR]invalid band %d in port cfg stat\n", band);
return MACNOITEM;
}
port = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_CFG_STAT_PORT);
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port %d in port cfg stat\n", port);
return MACNOITEM;
}
pinfo = &adapter->port_info[get_bp_idx(band, port)];
mbssid = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_CFG_STAT_MBSSID_IDX);
ret = GET_FIELD(stat.dword2, FWCMD_C2H_PORT_CFG_STAT_RET);
if (ret != C2H_MPORT_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%dMB%d cfg fail: ret %d\n",
band, port, mbssid, ret);
tmp32 = GET_FIELD(stat.dword0, FWCMD_C2H_PORT_CFG_STAT_TYPE);
PLTFM_MSG_ERR("[ERR]B%dP%dMB%d cfg fail: type %d\n",
band, port, mbssid, tmp32);
tmp32 = GET_FIELD(stat.dword1, FWCMD_C2H_PORT_CFG_STAT_VAL);
PLTFM_MSG_ERR("[ERR]B%dP%dMB%d cfg fail: val %d\n",
band, port, mbssid, tmp32);
pinfo->h2c_sm = MAC_AX_PORT_H2C_FAIL;
} else {
pinfo->h2c_sm = MAC_AX_PORT_H2C_IDLE;
}
return MACSUCCESS;
}
static struct c2h_proc_func c2h_proc_mport[] = {
{FWCMD_C2H_FUNC_PORT_INIT_STAT, c2h_port_init_stat},
{FWCMD_C2H_FUNC_PORT_CFG_STAT, c2h_port_cfg_stat},
{FWCMD_C2H_FUNC_NULL, NULL},
};
static u32 c2h_cl_mport(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info)
{
struct c2h_proc_func *proc = c2h_proc_mport;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u32 hdr0;
u32 func;
hdr0 = ((struct fwcmd_hdr *)buf)->hdr0;
hdr0 = le32_to_cpu(hdr0);
func = GET_FIELD(hdr0, C2H_HDR_FUNC);
while (proc->id != FWCMD_C2H_FUNC_NULL) {
if (func == proc->id) {
handler = proc->handler;
break;
}
proc++;
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null func handler id: %X", func);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
static struct c2h_proc_class c2h_proc_sys[] = {
#if MAC_AX_FEATURE_DBGPKG
{FWCMD_C2H_CL_CMD_PATH, c2h_sys_cmd_path},
{FWCMD_H2C_CL_PLAT_AUTO_TEST, c2h_sys_plat_autotest},
#if MAC_AX_FEATURE_HV
{FWCMD_C2H_CL_FW_AUTO, c2h_sys_fw_autotest},
#endif
#endif
{FWCMD_C2H_CL_FW_STATUS, c2h_fw_status},
{FWCMD_C2H_CL_NULL, NULL},
};
static struct c2h_proc_class c2h_proc_mac[] = {
{FWCMD_C2H_CL_FW_INFO, c2h_fw_info},
{FWCMD_C2H_CL_FW_OFLD, c2h_fw_ofld},
{FWCMD_C2H_CL_TWT, c2h_twt},
{FWCMD_C2H_CL_WOW, c2h_wow},
{FWCMD_C2H_CL_MCC, c2h_mcc},
{FWCMD_C2H_CL_FW_DBG, c2h_fw_dbg},
{FWCMD_C2H_CL_FLASH, c2h_sys_flash_pkt},
{FWCMD_C2H_CL_MISC, c2h_cl_misc},
{FWCMD_C2H_CL_FCS, c2h_fast_ch_sw},
{FWCMD_C2H_CL_MPORT, c2h_cl_mport},
{FWCMD_C2H_CL_NULL, NULL},
};
static inline struct c2h_proc_class *c2h_proc_sel(u8 cat)
{
struct c2h_proc_class *proc;
switch (cat) {
case FWCMD_C2H_CAT_TEST:
proc = c2h_proc_sys;
break;
case FWCMD_C2H_CAT_MAC:
proc = c2h_proc_mac;
break;
default:
proc = NULL;
break;
}
return proc;
}
u8 c2h_field_parsing(struct fwcmd_hdr *hdr, struct rtw_c2h_info *info)
{
u32 val;
val = le32_to_cpu(hdr->hdr0);
info->c2h_cat = GET_FIELD(val, C2H_HDR_CAT);
info->c2h_class = GET_FIELD(val, C2H_HDR_CLASS);
info->c2h_func = GET_FIELD(val, C2H_HDR_FUNC);
val = le32_to_cpu(hdr->hdr1);
info->content_len = GET_FIELD(val, C2H_HDR_TOTAL_LEN) -
FWCMD_HDR_LEN;
info->content = (u8 *)(hdr + 1);
return MACSUCCESS;
}
u32 mac_process_c2h(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
u8 *ret)
{
u8 _class_, result;
struct c2h_proc_class *proc;
struct fwcmd_hdr *hdr;
struct rtw_c2h_info *info;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info) = NULL;
u8 cat;
u32 val;
hdr = (struct fwcmd_hdr *)buf;
info = (struct rtw_c2h_info *)ret;
val = le32_to_cpu(hdr->hdr0);
result = c2h_field_parsing(hdr, info);
if (result) {
PLTFM_MSG_ERR("[ERR]parsing c2h hdr error: %X\n", val);
return MACNOITEM;
}
if (GET_FIELD(val, C2H_HDR_DEL_TYPE) != FWCMD_TYPE_C2H) {
PLTFM_MSG_ERR("[ERR]wrong fwcmd type: %X\n", val);
return MACNOITEM;
}
cat = (u8)GET_FIELD(val, C2H_HDR_CAT);
if (cat == FWCMD_C2H_CAT_OUTSRC)
return MACSUCCESS;
proc = c2h_proc_sel(cat);
if (!proc) {
PLTFM_MSG_ERR("[ERR]wrong fwcmd cat: %X\n", val);
return MACNOITEM;
}
_class_ = GET_FIELD(val, C2H_HDR_CLASS);
for (; proc->id != FWCMD_C2H_CL_NULL; proc++) {
if (_class_ == proc->id) {
handler = proc->handler;
break;
}
}
if (!handler) {
PLTFM_MSG_ERR("[ERR]null class handler id: %X", proc->id);
return MACNOITEM;
}
return handler(adapter, buf, len, info);
}
u32 mac_outsrc_h2c_common(struct mac_ax_adapter *adapter,
struct rtw_g6_h2c_hdr *hdr, u32 *pvalue)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_outsrc_info *info;
/*temp workaround for h2cb no functionality and outsrc has its timer*/
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_ERR("FW is not ready\n");
return MACFWNONRDY;
}
h2cb = h2cb_alloc(adapter, (enum h2c_buf_class)hdr->type);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, hdr->content_len);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
info = (struct fwcmd_outsrc_info *)buf;
PLTFM_MEMCPY(info->dword0, pvalue, hdr->content_len);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_OUTSRC,
hdr->h2c_class,
hdr->h2c_func,
hdr->rec_ack,
hdr->done_ack);
if (ret)
goto fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_fw_log_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_fw_log *log_cfg)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_log_cfg *log;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_log_cfg));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMSET(buf, 0, sizeof(struct fwcmd_log_cfg));
log = (struct fwcmd_log_cfg *)buf;
log->dword0 = cpu_to_le32(SET_WORD(log_cfg->level,
FWCMD_H2C_LOG_CFG_DBG_LV) |
SET_WORD(log_cfg->output,
FWCMD_H2C_LOG_CFG_PATH));
log->dword1 = cpu_to_le32(log_cfg->comp);
log->dword2 = cpu_to_le32(log_cfg->comp_ext);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_INFO,
FWCMD_H2C_FUNC_LOG_CFG,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_send_bcn_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_bcn_info *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
struct fwcmd_bcn_upd *hdr;
u32 ret = MACSUCCESS;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_bcn_upd *)
h2cb_put(h2cb, sizeof(struct fwcmd_bcn_upd));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
info->grp_ie_ofst |= info->grp_ie_ofst ? BCN_GRPIE_OFST_EN : 0;
hdr->dword0 =
cpu_to_le32(SET_WORD(info->port,
FWCMD_H2C_BCN_UPD_PORT) |
SET_WORD(info->mbssid,
FWCMD_H2C_BCN_UPD_MBSSID) |
SET_WORD(info->band,
FWCMD_H2C_BCN_UPD_BAND) |
SET_WORD(info->grp_ie_ofst,
FWCMD_H2C_BCN_UPD_GRP_IE_OFST));
hdr->dword1 =
cpu_to_le32(SET_WORD(info->macid,
FWCMD_H2C_BCN_UPD_MACID) |
SET_WORD(info->ssn_sel,
FWCMD_H2C_BCN_UPD_SSN_SEL) |
SET_WORD(info->ssn_mode,
FWCMD_H2C_BCN_UPD_SSN_MODE) |
SET_WORD(info->rate_sel,
FWCMD_H2C_BCN_UPD_RATE) |
SET_WORD(info->txpwr,
FWCMD_H2C_BCN_UPD_TXPWR));
hdr->dword2 =
cpu_to_le32((info->txinfo_ctrl_en ?
FWCMD_H2C_BCN_UPD_TXINFO_CTRL_EN : 0) |
SET_WORD(info->ntx_path_en,
FWCMD_H2C_BCN_UPD_NTX_PATH_EN) |
SET_WORD(info->path_map_a,
FWCMD_H2C_BCN_UPD_PATH_MAP_A) |
SET_WORD(info->path_map_b,
FWCMD_H2C_BCN_UPD_PATH_MAP_B) |
SET_WORD(info->path_map_c,
FWCMD_H2C_BCN_UPD_PATH_MAP_C) |
SET_WORD(info->path_map_d,
FWCMD_H2C_BCN_UPD_PATH_MAP_D) |
(info->antsel_a ?
FWCMD_H2C_BCN_UPD_ANTSEL_A : 0) |
(info->antsel_b ?
FWCMD_H2C_BCN_UPD_ANTSEL_B : 0) |
(info->antsel_c ?
FWCMD_H2C_BCN_UPD_ANTSEL_C : 0) |
(info->antsel_d ?
FWCMD_H2C_BCN_UPD_ANTSEL_D : 0) |
SET_WORD(info->csa_ofst,
FWCMD_H2C_BCN_UPD_CSA_OFST));
buf = h2cb_put(h2cb, info->pld_len);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, info->pld_buf, info->pld_len);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FR_EXCHG,
FWCMD_H2C_FUNC_BCN_UPD,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_host_getpkt_h2c(struct mac_ax_adapter *adapter, u8 macid, u8 pkttype)
{
//temp patch, wait for h2creg api
u32 content = 0;
u32 ret;
content |= FWCMD_H2CREG_FUNC_GETPKT_INFORM;
content |= (1 << 8);
content |= (macid << 16);
content |= (pkttype << 24);
ret = mac_send_h2creg(adapter, &content, 1);
return ret;
}
#if MAC_AX_PHL_H2C
u32 __ie_cam_set_cmd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb,
struct mac_ax_ie_cam_cmd_info *info)
{
struct fwcmd_ie_cam *cmd;
u8 *buf;
u32 ret = MACSUCCESS;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ie_cam));
if (!buf) {
ret = MACNOBUF;
return ret;
}
cmd = (struct fwcmd_ie_cam *)buf;
cmd->dword0 =
cpu_to_le32((info->en ? FWCMD_H2C_IE_CAM_CAM_EN : 0) |
(info->band ? FWCMD_H2C_IE_CAM_BAND : 0) |
(info->hit_en ? FWCMD_H2C_IE_CAM_HIT_FRWD_EN : 0) |
(info->miss_en ?
FWCMD_H2C_IE_CAM_MISS_FRWD_EN : 0) |
(info->rst ? FWCMD_H2C_IE_CAM_RST : 0) |
SET_WORD(info->port, FWCMD_H2C_IE_CAM_PORT) |
SET_WORD(info->hit_sel, FWCMD_H2C_IE_CAM_HIT_FRWD) |
SET_WORD(info->miss_sel,
FWCMD_H2C_IE_CAM_MISS_FRWD) |
SET_WORD(info->num, FWCMD_H2C_IE_CAM_UPD_NUM));
buf = h2cb_put(h2cb, info->buf_len);
if (!buf) {
ret = MACNOBUF;
return ret;
}
PLTFM_MEMCPY(buf, info->buf, info->buf_len);
return ret;
}
#else
u32 __ie_cam_set_cmd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb,
struct mac_ax_ie_cam_cmd_info *info)
{
struct fwcmd_ie_cam *cmd;
u8 *buf;
u32 ret = MACSUCCESS;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_ie_cam));
if (!buf) {
ret = MACNOBUF;
return ret;
}
cmd = (struct fwcmd_ie_cam *)buf;
cmd->dword0 =
cpu_to_le32((info->en ? FWCMD_H2C_IE_CAM_CAM_EN : 0) |
(info->band ? FWCMD_H2C_IE_CAM_BAND : 0) |
(info->hit_en ? FWCMD_H2C_IE_CAM_HIT_FRWD_EN : 0) |
(info->miss_en ?
FWCMD_H2C_IE_CAM_MISS_FRWD_EN : 0) |
(info->rst ? FWCMD_H2C_IE_CAM_RST : 0) |
SET_WORD(info->port, FWCMD_H2C_IE_CAM_PORT) |
SET_WORD(info->hit_sel, FWCMD_H2C_IE_CAM_HIT_FRWD) |
SET_WORD(info->miss_sel,
FWCMD_H2C_IE_CAM_MISS_FRWD) |
SET_WORD(info->num, FWCMD_H2C_IE_CAM_UPD_NUM));
buf = h2cb_put(h2cb, info->buf_len);
if (!buf) {
ret = MACNOBUF;
return ret;
}
PLTFM_MEMCPY(buf, info->buf, info->buf_len);
return ret;
}
#endif
u32 mac_ie_cam_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ie_cam_cmd_info *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u32 ret;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
ret = __ie_cam_set_cmd(adapter, h2cb, info);
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM set cmd fail %d\n", ret);
goto fail;
}
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_IE_CAM,
FWCMD_H2C_FUNC_IE_CAM, 0, 1);
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM set hdr fail %d\n", ret);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM build txd fail %d\n", ret);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM tx fail %d\n", ret);
goto fail;
}
fail:
h2cb_free(adapter, h2cb);
if (!ret)
h2c_end_flow(adapter);
return ret;
}
u32 _mac_send_h2creg(struct mac_ax_adapter *adapter,
struct mac_ax_h2creg_info *h2c)
{
#define MAC_AX_H2CREG_CNT 100
#define MAC_AX_H2CREG_US 200
u32 cnt = MAC_AX_H2CREG_CNT;
u8 len, byte0, byte1, val;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct fwcmd_h2creg h2creg;
if (!h2c)
return MACSUCCESS;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_ERR("FW is not ready\n");
return MACFWNONRDY;
}
if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) {
PLTFM_MSG_TRACE("MAC is not ready\n");
adapter->stats.h2c_reg_uninit++;
}
do {
if (!(MAC_REG_R8(R_AX_H2CREG_CTRL) & B_AX_H2CREG_TRIGGER))
break;
PLTFM_DELAY_US(MAC_AX_H2CREG_US);
cnt--;
} while (cnt);
if (!cnt) {
PLTFM_MSG_ERR("FW does not process H2CREG\n");
return MACPOLLTO;
}
if (h2c->content_len > H2CREG_CONTENT_LEN) {
PLTFM_MSG_ERR("%s: h2creg len is TOO large\n", __func__);
return MACFUNCINPUT;
}
len = h2c->content_len + H2CREG_HDR_LEN;
if ((h2c->content_len + H2CREG_HDR_LEN) & 3)
len = ((h2c->content_len + H2CREG_HDR_LEN) >> 2) + 1;
else
len = (h2c->content_len + H2CREG_HDR_LEN) >> 2;
byte0 = (u8)GET_FIELD(h2c->h2c_content.dword0, FWCMD_H2CREG_BYTE2);
byte1 = (u8)GET_FIELD(h2c->h2c_content.dword0, FWCMD_H2CREG_BYTE3);
h2creg.dword0 = SET_WORD(h2c->id, FWCMD_H2CREG_H2CREG_HDR_FUNC) |
SET_WORD(len, FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN) |
SET_WORD(byte0, FWCMD_H2CREG_BYTE2) |
SET_WORD(byte1, FWCMD_H2CREG_BYTE3);
h2creg.dword1 = h2c->h2c_content.dword1;
h2creg.dword2 = h2c->h2c_content.dword2;
h2creg.dword3 = h2c->h2c_content.dword3;
MAC_REG_W32(R_AX_H2CREG_DATA0, h2creg.dword0);
MAC_REG_W32(R_AX_H2CREG_DATA1, h2creg.dword1);
MAC_REG_W32(R_AX_H2CREG_DATA2, h2creg.dword2);
MAC_REG_W32(R_AX_H2CREG_DATA3, h2creg.dword3);
val = MAC_REG_R8(R_AX_H2CREG_CTRL);
MAC_REG_W8(R_AX_H2CREG_CTRL, val | B_AX_H2CREG_TRIGGER);
return MACSUCCESS;
}
u32 mac_send_h2creg(struct mac_ax_adapter *adapter, u32 *content, u8 len)
{
#define MAC_AX_H2CREG_PCNT 5
u32 cnt = MAC_AX_H2CREG_PCNT;
u8 i;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_ERR("FW is not ready\n");
return MACFWNONRDY;
}
if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) {
PLTFM_MSG_TRACE("MAC is not ready\n");
adapter->stats.h2c_reg_uninit++;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
do {
if (!MAC_REG_R8(R_AX_H2CREG_CTRL_V1))
break;
PLTFM_DELAY_US(1000);
cnt--;
} while (cnt);
} else {
do {
if (!MAC_REG_R8(R_AX_H2CREG_CTRL))
break;
PLTFM_DELAY_US(1000);
cnt--;
} while (cnt);
}
if (!cnt) {
PLTFM_MSG_ERR("FW does not process H2CREG\n");
return MACPOLLTO;
}
for (i = 0; i < len; i++)
MAC_REG_W32(R_AX_H2CREG_DATA0 + i * 4, content[i]);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W8(R_AX_H2CREG_CTRL_V1, 1);
else
MAC_REG_W8(R_AX_H2CREG_CTRL, 1);
return MACSUCCESS;
}
u32 __recv_c2hreg(struct mac_ax_adapter *adapter, struct fwcmd_c2hreg *c2h)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
if (!(MAC_REG_R8(R_AX_C2HREG_CTRL_V1) & B_AX_C2HREG_TRIGGER))
return MACC2HREGEMP;
c2h->dword0 = MAC_REG_R32(R_AX_C2HREG_DATA0_V1);
c2h->dword1 = MAC_REG_R32(R_AX_C2HREG_DATA1_V1);
c2h->dword2 = MAC_REG_R32(R_AX_C2HREG_DATA2_V1);
c2h->dword3 = MAC_REG_R32(R_AX_C2HREG_DATA3_V1);
val = MAC_REG_R8(R_AX_C2HREG_CTRL_V1);
MAC_REG_W8(R_AX_C2HREG_CTRL_V1, val & ~B_AX_C2HREG_TRIGGER);
} else {
if (!(MAC_REG_R8(R_AX_C2HREG_CTRL) & B_AX_C2HREG_TRIGGER))
return MACC2HREGEMP;
c2h->dword0 = MAC_REG_R32(R_AX_C2HREG_DATA0);
c2h->dword1 = MAC_REG_R32(R_AX_C2HREG_DATA1);
c2h->dword2 = MAC_REG_R32(R_AX_C2HREG_DATA2);
c2h->dword3 = MAC_REG_R32(R_AX_C2HREG_DATA3);
val = MAC_REG_R8(R_AX_C2HREG_CTRL);
MAC_REG_W8(R_AX_C2HREG_CTRL, val & ~B_AX_C2HREG_TRIGGER);
}
return MACSUCCESS;
}
u32 _recv_c2hreg(struct mac_ax_adapter *adapter, u8 *buf)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 i;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
if (!(MAC_REG_R8(R_AX_C2HREG_CTRL_V1) & B_AX_C2HREG_TRIGGER))
return MACC2HREGEMP;
} else {
if (!(MAC_REG_R8(R_AX_C2HREG_CTRL) & B_AX_C2HREG_TRIGGER))
return MACC2HREGEMP;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
for (i = 0; i < C2HREG_LEN; i = i + 4)
*(u32 *)(buf + i) = MAC_REG_R32(R_AX_C2HREG_DATA0_V1 + i);
} else {
for (i = 0; i < C2HREG_LEN; i = i + 4)
*(u32 *)(buf + i) = MAC_REG_R32(R_AX_C2HREG_DATA0 + i);
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W8(R_AX_C2HREG_CTRL_V1, 0);
else
MAC_REG_W8(R_AX_C2HREG_CTRL, 0);
return MACSUCCESS;
}
u32 mac_process_c2hreg(struct mac_ax_adapter *adapter,
struct mac_ax_c2hreg_info *info)
{
u32 ret;
struct fwcmd_c2hreg_hdr *hdr;
info->id = FWCMD_C2H_FUNC_NULL;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_ERR("FW is not ready\n");
return MACFWNONRDY;
}
if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) {
PLTFM_MSG_TRACE("MAC is not ready\n");
adapter->stats.c2h_reg_uninit++;
}
ret = _recv_c2hreg(adapter, info->c2hreg);
if (ret == MACC2HREGEMP) {
return ret;
} else if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]Get C2H REG fail %d\n", ret);
return ret;
}
hdr = (struct fwcmd_c2hreg_hdr *)info->c2hreg;
info->id = GET_FIELD(hdr->dword0, FWCMD_C2HREG_C2HREG_HDR_FUNC);
info->content = info->c2hreg + C2HREG_HDR_LEN;
info->content_len = GET_FIELD(hdr->dword0,
FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN);
info->content_len = (info->content_len << 2) - C2HREG_HDR_LEN;
return MACSUCCESS;
}
u32 mac_recv_c2hreg(struct mac_ax_adapter *adapter,
struct mac_ax_c2hreg_cont *cont)
{
u32 ret;
cont->id = FWCMD_C2H_FUNC_NULL;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_ERR("FW is not ready\n");
return MACFWNONRDY;
}
if (adapter->sm.mac_rdy != MAC_AX_MAC_RDY) {
PLTFM_MSG_TRACE("MAC is not ready\n");
adapter->stats.c2h_reg_uninit++;
}
ret = __recv_c2hreg(adapter, &cont->c2h_content);
if (ret == MACC2HREGEMP) {
return ret;
} else if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]Get C2H REG fail %d\n", ret);
return ret;
}
cont->id = GET_FIELD(cont->c2h_content.dword0,
FWCMD_C2HREG_C2HREG_HDR_FUNC);
cont->content_len = GET_FIELD(cont->c2h_content.dword0,
FWCMD_C2HREG_C2HREG_HDR_TOTAL_LEN);
cont->content_len = (cont->content_len << 2) - C2HREG_HDR_LEN;
return MACSUCCESS;
}
u32 mac_notify_fw_dbcc(struct mac_ax_adapter *adapter, u8 en)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u32 ret;
struct fwcmd_notify_dbcc *dbcc;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
dbcc = (struct fwcmd_notify_dbcc *)
h2cb_put(h2cb, sizeof(struct fwcmd_notify_dbcc));
if (!dbcc) {
ret = MACNPTR;
PLTFM_MSG_ERR("%s: h2c put fail\n", __func__);
goto fail;
}
dbcc->dword0 = en ? FWCMD_H2C_NOTIFY_DBCC_EN : 0;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MEDIA_RPT,
FWCMD_H2C_FUNC_NOTIFY_DBCC, 0, 0);
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM set hdr fail %d\n", ret);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM build txd fail %d\n", ret);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("H2C IE CAM tx fail %d\n", ret);
goto fail;
}
fail:
h2cb_free(adapter, h2cb);
if (!ret)
h2c_end_flow(adapter);
return ret;
}
u32 poll_c2hreg(struct mac_ax_adapter *adapter,
struct mac_ax_c2hreg_poll *c2h)
{
u32 cnt, poll_us, ret;
struct mac_ax_c2hreg_cont *c2hreg_cont;
struct mac_ax_drv_stats *drv_stats = &adapter->drv_stats;
if (!c2h)
return MACSUCCESS;
cnt = c2h->retry_cnt;
poll_us = c2h->retry_wait_us;
c2hreg_cont = &c2h->c2hreg_cont;
do {
ret = mac_recv_c2hreg(adapter, c2hreg_cont);
if (cnt == 0 || ret == MACSUCCESS)
break;
if (drv_stats->drv_rm) {
PLTFM_MSG_ERR("%s: driver removed\n", __func__);
return MACDRVRM;
}
if (ret != MACSUCCESS) {
if (ret == MACC2HREGEMP) {
PLTFM_DELAY_US(poll_us);
cnt--;
} else {
PLTFM_MSG_ERR("%s: c2hreg fail\n", __func__);
return ret;
}
}
} while (cnt);
PLTFM_MSG_TRACE("%s: cnt = %d, us = %d\n",
__func__, cnt, poll_us);
if (ret == MACSUCCESS) {
if (c2h->polling_id != FWCMD_C2H_FUNC_NULL &&
c2h->polling_id != c2hreg_cont->id) {
PLTFM_MSG_ERR("%s: surprised c2h\n", __func__);
PLTFM_MSG_ERR("rev: %x\n", c2h->polling_id);
PLTFM_MSG_ERR("exp: %x\n", c2hreg_cont->id);
ret = MACBADC2HREG;
}
} else {
PLTFM_MSG_ERR("%s: polling c2hreg timeout\n", __func__);
}
return ret;
}
u32 proc_msg_reg(struct mac_ax_adapter *adapter,
struct mac_ax_h2creg_info *h2c,
struct mac_ax_c2hreg_poll *c2h)
{
struct mac_ax_dbgpkg_en en = {0};
u32 ret = MACSUCCESS;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
PLTFM_MSG_ERR("FW is not ready\n");
return MACFWNONRDY;
}
PLTFM_MUTEX_LOCK(&adapter->fw_info.msg_reg);
ret = _mac_send_h2creg(adapter, h2c);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: send h2c reg fail: %d\n", __func__, ret);
goto END;
}
ret = poll_c2hreg(adapter, c2h);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: poll c2h reg fail: %d\n", __func__, ret);
END:
PLTFM_MUTEX_UNLOCK(&adapter->fw_info.msg_reg);
if (ret != MACSUCCESS) {
en.plersvd_dbg = 1;
mac_dbg_status_dump(adapter, NULL, &en);
}
return ret;
}
static u32 get_wps_rpt_event_id(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info)
{
struct fwcmd_wps_rpt *rpt = (struct fwcmd_wps_rpt *)c2h->content;
u32 state, val;
val = le32_to_cpu(rpt->dword0);
state = GET_FIELD(val, FWCMD_C2H_WPS_RPT_STATE);
if (!state)
*id = MSG_EVT_WPS_RELEASED;
else
*id = MSG_EVT_WPS_PRESSED;
return MACSUCCESS;
}
static u32 get_bcn_resend_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info)
{
*id = MSG_EVT_BCN_RESEND;
return MACSUCCESS;
}
static u32 get_tsf32_togl_rpt_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info)
{
*id = MSG_EVT_TSF32_TOG;
return MACSUCCESS;
}
static u32 get_fw_rx_dbg_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info)
{
*id = MSG_EVT_DBG_RX_DUMP;
return MACSUCCESS;
}
static struct c2h_event_id_proc event_proc[] = {
/* cat, class, func, hdl */
{FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_MISC,
FWCMD_C2H_FUNC_WPS_RPT, get_wps_rpt_event_id},
{FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_FW_OFLD,
FWCMD_C2H_FUNC_BEACON_RESEND, get_bcn_resend_event},
{FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_FW_OFLD,
FWCMD_C2H_FUNC_TSF32_TOGL_RPT, get_tsf32_togl_rpt_event},
{FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_MISC,
FWCMD_C2H_FUNC_CCXRPT, get_ccxrpt_event},
{FWCMD_C2H_CAT_MAC, FWCMD_C2H_CL_FW_DBG,
FWCMD_C2H_FUNC_RX_DBG, get_fw_rx_dbg_event},
{FWCMD_C2H_CAT_NULL, FWCMD_C2H_CL_NULL,
FWCMD_C2H_FUNC_NULL, NULL},
};
u32 mac_get_c2h_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info)
{
struct c2h_event_id_proc *proc;
u32 (*hdl)(struct mac_ax_adapter *adapter, struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id, u8 *c2h_info) = NULL;
/*for C2H ack bit no need to process*/
if (c2h->type_done_ack == 1 || c2h->type_rec_ack == 1)
return MACSUCCESS;
proc = event_proc;
while (proc->cat != FWCMD_C2H_CAT_NULL) {
if (proc->cat == c2h->c2h_cat &&
proc->cls == c2h->c2h_class &&
proc->func == c2h->c2h_func) {
hdl = proc->hdl;
return hdl(adapter, c2h, id, c2h_info);
}
proc++;
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwcmd.c
|
C
|
agpl-3.0
| 79,088
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FW_CMD_H_
#define _MAC_AX_FW_CMD_H_
#include "../type.h"
#include "../fw_ax/inc_hdr/fwcmd_intf.h"
#include "fwcmd_intf_f2p.h"
#include "trx_desc.h"
#include "fwofld.h"
#include "p2p.h"
#include "flash.h"
#include "dbg_cmd.h"
#define FWCMD_HDR_LEN 8
#define C2HREG_HDR_LEN 2
#define H2CREG_HDR_LEN 2
#define C2HREG_CONTENT_LEN 14
#define H2CREG_CONTENT_LEN 14
#define C2HREG_LEN (C2HREG_HDR_LEN + C2HREG_CONTENT_LEN)
#define H2CREG_LEN (H2CREG_HDR_LEN + H2CREG_CONTENT_LEN)
#define H2C_CMD_LEN 64
#define H2C_DATA_LEN 256
#define H2C_LONG_DATA_LEN 2048
#define SET_FWCMD_ID(_t, _ca, _cl, _f) \
(SET_WORD(_t, H2C_HDR_DEL_TYPE) | SET_WORD(_ca, H2C_HDR_CAT) | \
SET_WORD(_cl, H2C_HDR_CLASS) | SET_WORD(_f, H2C_HDR_FUNC))
#define GET_FWCMD_TYPE(id) (GET_FIELD(id, C2H_HDR_DEL_TYPE))
#define GET_FWCMD_CAT(id) (GET_FIELD(id, C2H_HDR_CAT))
#define GET_FWCMD_CLASS(id) (GET_FIELD(id, C2H_HDR_CLASS))
#define GET_FWCMD_FUNC(id) (GET_FIELD(id, C2H_HDR_FUNC))
#define FWCMD_TYPE_H2C 0
#define FWCMD_TYPE_C2H 1
#define FWCMD_C2H_CL_NULL 0xFF
#define FWCMD_C2H_FUNC_NULL 0xFF
#define FWCMD_C2H_CAT_NULL 0xFF
/**
* @struct h2c_buf_head
* @brief h2c_buf_head
*
* @var h2c_buf_head::next
* Please Place Description here.
* @var h2c_buf_head::prev
* Please Place Description here.
* @var h2c_buf_head::pool
* Please Place Description here.
* @var h2c_buf_head::size
* Please Place Description here.
* @var h2c_buf_head::qlen
* Please Place Description here.
* @var h2c_buf_head::suspend
* Please Place Description here.
* @var h2c_buf_head::lock
* Please Place Description here.
*/
struct h2c_buf_head {
/* keep first */
struct h2c_buf *next;
struct h2c_buf *prev;
u8 *pool;
u32 size;
u32 qlen;
u8 suspend;
mac_ax_mutex lock;
};
/**
* @struct fwcmd_wkb_head
* @brief fwcmd_wkb_head
*
* @var fwcmd_wkb_head::next
* Please Place Description here.
* @var fwcmd_wkb_head::prev
* Please Place Description here.
* @var fwcmd_wkb_head::qlen
* Please Place Description here.
* @var fwcmd_wkb_head::lock
* Please Place Description here.
*/
struct fwcmd_wkb_head {
/* keep first */
struct h2c_buf *next;
struct h2c_buf *prev;
u32 qlen;
mac_ax_mutex lock;
};
/**
* @struct h2c_buf
* @brief h2c_buf
*
* @var h2c_buf::next
* Please Place Description here.
* @var h2c_buf::prev
* Please Place Description here.
* @var h2c_buf::_class_
* Please Place Description here.
* @var h2c_buf::id
* Please Place Description here.
* @var h2c_buf::master
* Please Place Description here.
* @var h2c_buf::len
* Please Place Description here.
* @var h2c_buf::head
* Please Place Description here.
* @var h2c_buf::end
* Please Place Description here.
* @var h2c_buf::data
* Please Place Description here.
* @var h2c_buf::tail
* Please Place Description here.
* @var h2c_buf::hdr_len
* Please Place Description here.
* @var h2c_buf::flags
* Please Place Description here.
* @var h2c_buf::h2c_seq
* Please Place Description here.
*/
struct h2c_buf {
/* keep first */
struct h2c_buf *next;
struct h2c_buf *prev;
enum h2c_buf_class _class_;
u32 id;
u8 master;
u32 len;
u8 *head;
u8 *end;
u8 *data;
u8 *tail;
u32 hdr_len;
#define H2CB_FLAGS_FREED BIT(0)
u32 flags;
u8 h2c_seq;
};
/**
* @struct c2h_proc_class
* @brief c2h_proc_class
*
* @var c2h_proc_class::id
* Please Place Description here.
* @var c2h_proc_class::handler
* Please Place Description here.
*/
struct c2h_proc_class {
u16 id;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
};
struct fw_status_proc_class {
u16 id;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len);
};
/**
* @struct c2h_proc_func
* @brief c2h_proc_func
*
* @var c2h_proc_func::id
* Please Place Description here.
* @var c2h_proc_func::handler
* Please Place Description here.
*/
struct c2h_proc_func {
u16 id;
u32 (*handler)(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
struct rtw_c2h_info *info);
};
/**
* @struct mac_ax_c2hreg_info
* @brief mac_ax_c2hreg_info
*
* @var mac_ax_c2hreg_info::id
* Please Place Description here.
* @var mac_ax_c2hreg_info::total_len
* Please Place Description here.
* @var mac_ax_c2hreg_info::content
* Please Place Description here.
* @var mac_ax_c2hreg_info::c2hreg
* Please Place Description here.
*/
struct mac_ax_c2hreg_info {
u8 id;
u8 content_len;
u8 *content;
u8 c2hreg[C2HREG_LEN];
};
struct mac_ax_c2hreg_cont {
u8 id;
u8 content_len;
struct fwcmd_c2hreg c2h_content;
};
struct mac_ax_c2hreg_poll {
u8 polling_id;
u32 retry_cnt;
u32 retry_wait_us;
struct mac_ax_c2hreg_cont c2hreg_cont;
};
struct mac_ax_h2creg_info {
u8 id;
u8 content_len;
struct fwcmd_h2creg h2c_content;
};
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_init
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 h2cb_init(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_exit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 h2cb_exit(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_alloc
*
* @param *adapter
* @param buf_class
* @return Please Place Description here.
* @retval rtw_h2c_pkt
*/
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb_alloc(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_free
*
* @param *adapter
* @param *h2cb
* @return Please Place Description here.
* @retval void
*/
void h2cb_free(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_push
*
* @param *h2cb
* @param len
* @return Please Place Description here.
* @retval u8
*/
u8 *h2cb_push(struct rtw_h2c_pkt *h2cb, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_pull
*
* @param *h2cb
* @param len
* @return Please Place Description here.
* @retval u8
*/
u8 *h2cb_pull(struct rtw_h2c_pkt *h2cb, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_put
*
* @param *h2cb
* @param len
* @return Please Place Description here.
* @retval u8
*/
u8 *h2cb_put(struct rtw_h2c_pkt *h2cb, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2c_pkt_set_hdr
*
* @param *adapter
* @param *h2cb
* @param type
* @param cat
* @param _class_
* @param func
* @param rack
* @param dack
* @return Please Place Description here.
* @retval u32
*/
u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb,
u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2c_pkt_set_hdr_fwdl
*
* @param *adapter
* @param *h2cb
* @param type
* @param cat
* @param _class_
* @param func
* @param rack
* @param dack
* @return Please Place Description here.
* @retval u32
*/
u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter,
struct rtw_h2c_pkt *h2cb, u8 type, u8 cat, u8 _class_,
u8 func, u16 rack, u16 dack);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2c_pkt_set_cmd
*
* @param *adapter
* @param *h2cb
* @param *cmd
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb,
u8 *cmd, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2c_agg_enqueue
*
* @param *adapter
* @param *h2cb
* @return Please Place Description here.
* @retval u32
*/
u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb);
/**
* @}
* @}
*/
/**
* @brief h2c_pkt_build_txd
*
* @param *adapter
* @param *h2cb
* @return Please Place Description here.
* @retval u32
*/
u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct rtw_h2c_pkt *h2cb);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2cb_alloc
*
* @param *adapter
* @param buf_class
* @return Please Place Description here.
* @retval h2c_buf
*/
#else
struct h2c_buf *h2cb_alloc(struct mac_ax_adapter *adapter,
enum h2c_buf_class buf_class);
/**
* @}
* @}
*/
void h2cb_free(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb);
u8 *h2cb_push(struct h2c_buf *h2cb, u32 len);
u8 *h2cb_pull(struct h2c_buf *h2cb, u32 len);
u8 *h2cb_put(struct h2c_buf *h2cb, u32 len);
u32 h2c_pkt_set_hdr(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb,
u8 type, u8 cat, u8 _class_, u8 func, u16 rack, u16 dack);
u32 h2c_pkt_set_hdr_fwdl(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb,
u8 type, u8 cat, u8 _class_, u8 func, u16 rack,
u16 dack);
u32 h2c_pkt_set_cmd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb,
u8 *cmd, u32 len);
u32 h2c_pkt_build_txd(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb);
u32 h2c_agg_enqueue(struct mac_ax_adapter *adapter, h2c_buf *h2cb);
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief fwcmd_wq_enqueue
*
* @param *adapter
* @param *h2cb
* @return Please Place Description here.
* @retval u32
*/
#endif
u32 fwcmd_wq_enqueue(struct mac_ax_adapter *adapter, struct h2c_buf *h2cb);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief fwcmd_wq_dequeue
*
* @param *adapter
* @param id
* @return Please Place Description here.
* @retval h2c_buf
*/
struct h2c_buf *fwcmd_wq_dequeue(struct mac_ax_adapter *adapter, u32 id);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief fwcmd_wq_idle
*
* @param *adapter
* @param id
* @return Please Place Description here.
* @retval u32
*/
u32 fwcmd_wq_idle(struct mac_ax_adapter *adapter, u32 id);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup C2H
* @{
*/
/**
* @brief mac_process_c2h
*
* @param *adapter
* @param *buf
* @param len
* @param *ret
* @return Please Place Description here.
* @retval u32
*/
u32 mac_process_c2h(struct mac_ax_adapter *adapter, u8 *buf, u32 len,
u8 *ret);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup C2H
* @{
*/
/**
* @brief c2h_field_parsing
*
* @param *hdr
* @param *info
* @return Please Place Description here.
* @retval u8
*/
u8 c2h_field_parsing(struct fwcmd_hdr *hdr, struct rtw_c2h_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup C2H
* @{
*/
/**
* @brief mac_fw_log_cfg
*
* @param *adapter
* @param *log_cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fw_log_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_fw_log *log_cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup Beacon
* @{
*/
/**
* @brief mac_send_bcn_h2c
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_send_bcn_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_bcn_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief mac_host_getpkt_h2c
*
* @param *adapter
* @param macid
* @param pkttype
* @return Please Place Description here.
* @retval u32
*/
u32 mac_host_getpkt_h2c(struct mac_ax_adapter *adapter, u8 macid, u8 pkttype);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief mac_outsrc_h2c_common
*
* @param *adapter
* @param *hdr
* @param *pvalue
* @return Please Place Description here.
* @retval u32
*/
u32 mac_outsrc_h2c_common(struct mac_ax_adapter *adapter,
struct rtw_g6_h2c_hdr *hdr, u32 *pvalue);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup Beacon
* @{
*/
/**
* @brief mac_ie_cam_upd
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ie_cam_upd(struct mac_ax_adapter *adapter,
struct mac_ax_ie_cam_cmd_info *info);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief h2c_end_flow
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 h2c_end_flow(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup H2C
* @{
*/
/**
* @brief mac_send_h2creg
*
* @param *adapter
* @param *content
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_send_h2creg(struct mac_ax_adapter *adapter, u32 *content, u8 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup C2H
* @{
*/
/**
* @brief mac_process_c2hreg
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_process_c2hreg(struct mac_ax_adapter *adapter,
struct mac_ax_c2hreg_info *info);
/**
* @}
* @}
*/
u32 proc_msg_reg(struct mac_ax_adapter *adapter,
struct mac_ax_h2creg_info *h2c,
struct mac_ax_c2hreg_poll *c2h);
/**
* @addtogroup Firmware
* @{
* @addtogroup C2H
* @{
*/
/**
* @brief mac_get_c2h_event
*
* Get the phl_msg_evt_id from C2H packet
*
* @param *adapter
* @param *c2h
* @param *id
* @return Return 0 when getting event ID successfully.
* @retval u32
*/
u32 mac_get_c2h_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id,
u8 *c2h_info);
/**
* @}
* @}
*/
u32 mac_notify_fw_dbcc(struct mac_ax_adapter *adapter, u8 en);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwcmd.h
|
C
|
agpl-3.0
| 14,727
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FWCMD_INTF_F2P_H_
#define _MAC_AX_FWCMD_INTF_F2P_H_
/* f2p test cmd para*/
#define FWCMD_F2PTEST_ULBW_SH 0
#define FWCMD_F2PTEST_ULBW_MSK 0x3
#define FWCMD_F2PTEST_GILTF_SH 2
#define FWCMD_F2PTEST_GILTF_MSK 0x3
#define FWCMD_F2PTEST_NUMLTF_SH 4
#define FWCMD_F2PTEST_NUMLTF_MSK 0x7
#define FWCMD_F2PTEST_ULSTBC_SH 7
#define FWCMD_F2PTEST_ULSTBC_MSK 0x1
#define FWCMD_F2PTEST_DPLR_SH 8
#define FWCMD_F2PTEST_DPLR_MSK 0x1
#define FWCMD_F2PTEST_TXPWR_SH 9
#define FWCMD_F2PTEST_TXPWR_MSK 0x3F
#define FWCMD_F2PTEST_USERNUM_SH 16
#define FWCMD_F2PTEST_USERNUM_MSK 0x7
#define FWCMD_F2PTEST_PKTNUM_SH 19
#define FWCMD_F2PTEST_PKTNUM_MSK 0x7
#define FWCMD_F2PTEST_BITMAP_SH 24
#define FWCMD_F2PTEST_BITMAP_MSK 0xFF
#define FWCMD_F2PTEST_AID12_SH 0
#define FWCMD_F2PTEST_AID12_MSK 0xFFF
#define FWCMD_F2PTEST_ULMCS_SH 12
#define FWCMD_F2PTEST_ULMCS_MSK 0xF
#define FWCMD_F2PTEST_MACID_SH 16
#define FWCMD_F2PTEST_MACID_MSK 0xFF
#define FWCMD_F2PTEST_RUPOS_SH 24
#define FWCMD_F2PTEST_RUPOS_MSK 0xFF
#define FWCMD_F2PTEST_ULFEC_SH 0
#define FWCMD_F2PTEST_ULFEC_MSK 0x1
#define FWCMD_F2PTEST_ULDCM_SH 1
#define FWCMD_F2PTEST_ULDCM_MSK 0x1
#define FWCMD_F2PTEST_SS_ALLOC_SH 2
#define FWCMD_F2PTEST_SS_ALLOC_MSK 0x3F
#define FWCMD_F2PTEST_UL_TGTRSSI_SH 8
#define FWCMD_F2PTEST_UL_TGTRSSI_MSK 0x7F
#define FWCMD_F2PTEST_PREF_AC_SH 0
#define FWCMD_F2PTEST_PREF_AC_MSK 0x3
#define FWCMD_F2PTEST_DATARATE_SH 0
#define FWCMD_F2PTEST_DATARATE_MSK 0x1FF
#define FWCMD_F2PTEST_MULPORT_SH 9
#define FWCMD_F2PTEST_MULPORT_MSK 0x7
#define FWCMD_F2PTEST_PWR_OFSET_SH 12
#define FWCMD_F2PTEST_PWR_OFSET_MSK 0x7
#define FWCMD_F2PTEST_MODE_SH 16
#define FWCMD_F2PTEST_MODE_MSK 0x3
#define FWCMD_F2PTEST_TYPE_SH 18
#define FWCMD_F2PTEST_TYPE_MSK 0x3F
#define FWCMD_F2PTEST_SIGB_LEN_SH 24
#define FWCMD_F2PTEST_SIGB_LEN_MSK 0xFF
#define FWCMD_F2PTEST_TXCMD_ADDR_SH 0
#define FWCMD_F2PTEST_TXCMD_ADDR_MSK 0xFF
#define FWCMD_F2PTEST_SIGB_ADDR_SH 8
#define FWCMD_F2PTEST_SIGB_ADDR_MSK 0xFF
/* f2p_wd*/
/* dword0 */
#define F2P_WD_CMD_QSEL_SH 0
#define F2P_WD_CMD_QSEL_MSK 0x3f
#define F2P_WD_LS BIT(10)
#define F2P_WD_FS BIT(11)
#define F2P_WD_TOTAL_NUMBER_SH 12
#define F2P_WD_TOTAL_NUMBER_MSK 0xf
#define F2P_WD_SEQ_SH 16
#define F2P_WD_SEQ_MSK 0xff
#define F2P_WD_LENGTH_SH 24
#define F2P_WD_LENGTH_MSK 0xff
/* f2p_tx_cmd*/
/* dword0 */
#define F2P_CMD_TYPE_SH 0
#define F2P_CMD_TYPE_MSK 0xff
#define F2P_CMD_SUB_TYPE_SH 8
#define F2P_CMD_SUB_TYPE_MSK 0xff
#define F2P_DL_USER_NUM_SH 16
#define F2P_DL_USER_NUM_MSK 0x1f
#define F2P_BW_SH 21
#define F2P_BW_MSK 0x3
#define F2P_TX_POWER_SH 23
#define F2P_TX_POWER_MSK 0x1ff
/* dword1 */
#define F2P_FW_DEFINE_SH 0
#define F2P_FW_DEFINE_MSK 0xffff
#define F2P_SS_SEL_MODE_SH 16
#define F2P_SS_SEL_MODE_MSK 0x3
#define F2P_NEXT_QSEL_SH 18
#define F2P_NEXT_QSEL_MSK 0x3f
#define F2P_TWT_GROUP_SH 24
#define F2P_TWT_GROUP_MSK 0xf
#define F2P_DIS_CHK_SLP BIT(28)
#define F2P_RU_MU_2_SU BIT(29)
#define F2P_DL_T_PE_SH 30
#define F2P_DL_T_PE_MSK 0x3
/* dword2 */
#define F2P_SIGB_CH1_LEN_SH 0
#define F2P_SIGB_CH1_LEN_MSK 0xff
#define F2P_SIGB_CH2_LEN_SH 8
#define F2P_SIGB_CH2_LEN_MSK 0xff
#define F2P_SIGB_SYM_NUM_SH 16
#define F2P_SIGB_SYM_NUM_MSK 0x3f
#define F2P_SIGB_CH2_OFS_SH 22
#define F2P_SIGB_CH2_OFS_MSK 0x1f
#define F2P_DIS_HTP_ACK BIT(27)
#define F2P_TX_TIME_REF_SH 28
#define F2P_TX_TIME_REF_MSK 0x3
#define F2P_PRI_USER_IDX_SH 30
#define F2P_PRI_USER_IDX_MSK 0x3
/* dword3 */
#define F2P_AMPDU_MAX_TXTIME_SH 0
#define F2P_AMPDU_MAX_TXTIME_MSK 0x3fff
#define F2P_GROUP_ID_SH 16
#define F2P_GROUP_ID_MSK 0x3f
#define F2P_TWT_CHK_EN BIT(28)
#define F2P_TWT_PORT_ID_SH 29
#define F2P_TWT_PORT_ID_MSK 0x7
/* dword4 */
#define F2P_TWT_START_TIME_SH 0
#define F2P_TWT_START_TIME_MSK 0xffffffff
/* dword5 */
#define F2P_TWT_END_TIME_SH 0
#define F2P_TWT_END_TIME_MSK 0xffffffff
/* dword6 */
#define F2P_APEP_LEN_SH 0
#define F2P_APEP_LEN_MSK 0xfff
#define F2P_TRI_PAD_SH 12
#define F2P_TRI_PAD_MSK 0x3
#define F2P_UL_T_PE_SH 14
#define F2P_UL_T_PE_MSK 0x3
#define F2P_RF_GAIN_IDX_SH 16
#define F2P_RF_GAIN_IDX_MSK 0x3ff
#define F2P_FIXED_GAIN_EN BIT(26)
#define F2P_UL_GI_LTF_SH 27
#define F2P_UL_GI_LTF_MSK 0x7
#define F2P_UL_DOPPLER BIT(30)
#define F2P_UL_STBC BIT(31)
/* dword7 */
#define F2P_UL_MID_PER BIT(0)
#define F2P_UL_CQI_RRP_TRI BIT(1)
#define F2P_SIGB_DCM BIT(16)
#define F2P_SIGB_COMP BIT(17)
#define F2P_DOPPLER BIT(18)
#define F2P_STBC BIT(19)
#define F2P_MID_PER BIT(20)
#define F2P_GI_LTF_SIZE_SH 21
#define F2P_GI_LTF_SIZE_MSK 0x7
#define F2P_SIGB_MCS_SH 24
#define F2P_SIGB_MCS_MSK 0x7
/* dword8 */
#define F2P_MACID_U0_SH 0
#define F2P_MACID_U0_MSK 0xff
#define F2P_AC_TYPE_U0_SH 8
#define F2P_AC_TYPE_U0_MSK 0x3
#define F2P_MU_STA_POS_U0_SH 10
#define F2P_MU_STA_POS_U0_MSK 0x3
#define F2P_DL_RATE_IDX_U0_SH 12
#define F2P_DL_RATE_IDX_U0_MSK 0x1ff
#define F2P_TX_CMD_DL_DCM_EN_U0 BIT(21)
#define F2P_RU_ALO_IDX_U0_SH 24
#define F2P_RU_ALO_IDX_U0_MSK 0xff
/* dword9 */
#define F2P_PWR_BOOST_U0_SH 0
#define F2P_PWR_BOOST_U0_MSK 0x1f
#define F2P_AGG_BMP_ALO_U0_SH 5
#define F2P_AGG_BMP_ALO_U0_MSK 0x7
#define F2P_AMPDU_MAX_NUM_U0_SH 8
#define F2P_AMPDU_MAX_NUM_U0_MSK 0xff
#define F2P_USER_DEFINE_U0_SH 16
#define F2P_USER_DEFINE_U0_MSK 0xff
#define F2P_USER_DEFINE_EXT_U0_SH 24
#define F2P_USER_DEFINE_EXT_U0_MSK 0xff
/* dword10 */
#define F2P_UL_ADDR_IDX_U0_SH 0
#define F2P_UL_ADDR_IDX_U0_MSK 0xff
#define F2P_UL_DCM_U0 BIT(8)
#define F2P_UL_FEC_COD_U0 BIT(9)
#define F2P_UL_RU_RATE_U0_SH 10
#define F2P_UL_RU_RATE_U0_MSK 0x7f
#define F2P_UL_RU_ALO_IDX_U0_SH 24
#define F2P_UL_RU_ALO_IDX_U0_MSK 0xff
/* dword11 */
/* dword12 */
#define F2P_MACID_U1_SH 0
#define F2P_MACID_U1_MSK 0xff
#define F2P_AC_TYPE_U1_SH 8
#define F2P_AC_TYPE_U1_MSK 0x3
#define F2P_MU_STA_POS_U1_SH 10
#define F2P_MU_STA_POS_U1_MSK 0x3
#define F2P_DL_RATE_IDX_U1_SH 12
#define F2P_DL_RATE_IDX_U1_MSK 0x1ff
#define F2P_TX_CMD_DL_DCM_EN_U1 BIT(21)
#define F2P_RU_ALO_IDX_U1_SH 24
#define F2P_RU_ALO_IDX_U1_MSK 0xff
/* dword13 */
#define F2P_PWR_BOOST_U1_SH 0
#define F2P_PWR_BOOST_U1_MSK 0x1f
#define F2P_AGG_BMP_ALO_U1_SH 5
#define F2P_AGG_BMP_ALO_U1_MSK 0x7
#define F2P_AMPDU_MAX_NUM_U1_SH 8
#define F2P_AMPDU_MAX_NUM_U1_MSK 0xff
#define F2P_USER_DEFINE_U1_SH 16
#define F2P_USER_DEFINE_U1_MSK 0xff
#define F2P_USER_DEFINE_EXT_U1_SH 24
#define F2P_USER_DEFINE_EXT_U1_MSK 0xff
/* dword14 */
#define F2P_UL_ADDR_IDX_U1_SH 0
#define F2P_UL_ADDR_IDX_U1_MSK 0xff
#define F2P_UL_DCM_U1 BIT(8)
#define F2P_UL_FEC_COD_U1 BIT(9)
#define F2P_UL_RU_RATE_U1_SH 10
#define F2P_UL_RU_RATE_U1_MSK 0x7f
#define F2P_UL_RU_ALO_IDX_U1_SH 24
#define F2P_UL_RU_ALO_IDX_U1_MSK 0xff
/* dword15 */
/* dword16 */
#define F2P_MACID_U2_SH 0
#define F2P_MACID_U2_MSK 0xff
#define F2P_AC_TYPE_U2_SH 8
#define F2P_AC_TYPE_U2_MSK 0x3
#define F2P_MU_STA_POS_U2_SH 10
#define F2P_MU_STA_POS_U2_MSK 0x3
#define F2P_DL_RATE_IDX_U2_SH 12
#define F2P_DL_RATE_IDX_U2_MSK 0x1ff
#define F2P_TX_CMD_DL_DCM_EN_U2 BIT(21)
#define F2P_RU_ALO_IDX_U2_SH 24
#define F2P_RU_ALO_IDX_U2_MSK 0xff
/* dword17 */
#define F2P_PWR_BOOST_U2_SH 0
#define F2P_PWR_BOOST_U2_MSK 0x1f
#define F2P_AGG_BMP_ALO_U2_SH 5
#define F2P_AGG_BMP_ALO_U2_MSK 0x7
#define F2P_AMPDU_MAX_NUM_U2_SH 8
#define F2P_AMPDU_MAX_NUM_U2_MSK 0xff
#define F2P_USER_DEFINE_U2_SH 16
#define F2P_USER_DEFINE_U2_MSK 0xff
#define F2P_USER_DEFINE_EXT_U2_SH 24
#define F2P_USER_DEFINE_EXT_U2_MSK 0xff
/* dword18 */
#define F2P_UL_ADDR_IDX_U2_SH 0
#define F2P_UL_ADDR_IDX_U2_MSK 0xff
#define F2P_UL_DCM_U2 BIT(8)
#define F2P_UL_FEC_COD_U2 BIT(9)
#define F2P_UL_RU_RATE_U2_SH 10
#define F2P_UL_RU_RATE_U2_MSK 0x7f
#define F2P_UL_RU_ALO_IDX_U2_SH 24
#define F2P_UL_RU_ALO_IDX_U2_MSK 0xff
/* dword19 */
/* dword20 */
#define F2P_MACID_U3_SH 0
#define F2P_MACID_U3_MSK 0xff
#define F2P_AC_TYPE_U3_SH 8
#define F2P_AC_TYPE_U3_MSK 0x3
#define F2P_MU_STA_POS_U3_SH 10
#define F2P_MU_STA_POS_U3_MSK 0x3
#define F2P_DL_RATE_IDX_U3_SH 12
#define F2P_DL_RATE_IDX_U3_MSK 0x1ff
#define F2P_TX_CMD_DL_DCM_EN_U3 BIT(21)
#define F2P_RU_ALO_IDX_U3_SH 24
#define F2P_RU_ALO_IDX_U3_MSK 0xff
/* dword21 */
#define F2P_PWR_BOOST_U3_SH 0
#define F2P_PWR_BOOST_U3_MSK 0x1f
#define F2P_AGG_BMP_ALO_U3_SH 5
#define F2P_AGG_BMP_ALO_U3_MSK 0x7
#define F2P_AMPDU_MAX_NUM_U3_SH 8
#define F2P_AMPDU_MAX_NUM_U3_MSK 0xff
#define F2P_USER_DEFINE_U3_SH 16
#define F2P_USER_DEFINE_U3_MSK 0xff
#define F2P_USER_DEFINE_EXT_U3_SH 24
#define F2P_USER_DEFINE_EXT_U3_MSK 0xff
/* dword22 */
#define F2P_UL_ADDR_IDX_U3_SH 0
#define F2P_UL_ADDR_IDX_U3_MSK 0xff
#define F2P_UL_DCM_U3 BIT(8)
#define F2P_UL_FEC_COD_U3 BIT(9)
#define F2P_UL_RU_RATE_U3_SH 10
#define F2P_UL_RU_RATE_U3_MSK 0x7f
#define F2P_UL_RU_ALO_IDX_U3_SH 24
#define F2P_UL_RU_ALO_IDX_U3_MSK 0xff
/* dword23 */
/* dword24 */
#define F2P_PKT_ID_0_SH 0
#define F2P_PKT_ID_0_MSK 0xfff
#define F2P_VALID_0 BIT(15)
#define F2P_UL_USER_NUM_0_SH 16
#define F2P_UL_USER_NUM_0_MSK 0xf
/* dword25 */
#define F2P_PKT_ID_1_SH 0
#define F2P_PKT_ID_1_MSK 0xfff
#define F2P_VALID_1 BIT(15)
#define F2P_UL_USER_NUM_1_SH 16
#define F2P_UL_USER_NUM_1_MSK 0xf
/* dword26 */
#define F2P_PKT_ID_2_SH 0
#define F2P_PKT_ID_2_MSK 0xfff
#define F2P_VALID_2 BIT(15)
#define F2P_UL_USER_NUM_2_SH 16
#define F2P_UL_USER_NUM_2_MSK 0xf
/* dword27 */
#define F2P_PKT_ID_3_SH 0
#define F2P_PKT_ID_3_MSK 0xfff
#define F2P_VALID_3 BIT(15)
#define F2P_UL_USER_NUM_3_SH 16
#define F2P_UL_USER_NUM_3_MSK 0xf
/* dword28 */
#define F2P_PKT_ID_4_SH 0
#define F2P_PKT_ID_4_MSK 0xfff
#define F2P_VALID_4 BIT(15)
#define F2P_UL_USER_NUM_4_SH 16
#define F2P_UL_USER_NUM_4_MSK 0xf
/* dword29 */
#define F2P_PKT_ID_5_SH 0
#define F2P_PKT_ID_5_MSK 0xfff
#define F2P_VALID_5 BIT(15)
#define F2P_UL_USER_NUM_5_SH 16
#define F2P_UL_USER_NUM_5_MSK 0xf
/**
* @struct fwcmd_test_para
* @brief fwcmd_test_para
*
* @var fwcmd_test_para::dword0
* Please Place Description here.
* @var fwcmd_test_para::dword1
* Please Place Description here.
* @var fwcmd_test_para::dword2
* Please Place Description here.
* @var fwcmd_test_para::dword3
* Please Place Description here.
* @var fwcmd_test_para::dword4
* Please Place Description here.
* @var fwcmd_test_para::dword5
* Please Place Description here.
* @var fwcmd_test_para::dword6
* Please Place Description here.
* @var fwcmd_test_para::dword7
* Please Place Description here.
* @var fwcmd_test_para::dword8
* Please Place Description here.
* @var fwcmd_test_para::byte9
* Please Place Description here.
* @var fwcmd_test_para::byte10
* Please Place Description here.
* @var fwcmd_test_para::byte11
* Please Place Description here.
* @var fwcmd_test_para::byte12
* Please Place Description here.
* @var fwcmd_test_para::dword13
* Please Place Description here.
* @var fwcmd_test_para::dword14
* Please Place Description here.
* @var fwcmd_test_para::dword15
* Please Place Description here.
* @var fwcmd_test_para::dword16
* Please Place Description here.
* @var fwcmd_test_para::dword17
* Please Place Description here.
* @var fwcmd_test_para::dword18
* Please Place Description here.
* @var fwcmd_test_para::dword19
* Please Place Description here.
* @var fwcmd_test_para::dword20
* Please Place Description here.
* @var fwcmd_test_para::dword21
* Please Place Description here.
* @var fwcmd_test_para::dword22
* Please Place Description here.
* @var fwcmd_test_para::dword23
* Please Place Description here.
* @var fwcmd_test_para::dword24
* Please Place Description here.
* @var fwcmd_test_para::dword25
* Please Place Description here.
* @var fwcmd_test_para::dword26
* Please Place Description here.
* @var fwcmd_test_para::dword27
* Please Place Description here.
* @var fwcmd_test_para::dword28
* Please Place Description here.
* @var fwcmd_test_para::dword29
* Please Place Description here.
* @var fwcmd_test_para::dword30
* Please Place Description here.
* @var fwcmd_test_para::dword31
* Please Place Description here.
* @var fwcmd_test_para::dword32
* Please Place Description here.
* @var fwcmd_test_para::dword33
* Please Place Description here.
* @var fwcmd_test_para::dword34
* Please Place Description here.
* @var fwcmd_test_para::dword35
* Please Place Description here.
* @var fwcmd_test_para::dword36
* Please Place Description here.
* @var fwcmd_test_para::dword37
* Please Place Description here.
* @var fwcmd_test_para::dword38
* Please Place Description here.
* @var fwcmd_test_para::dword39
* Please Place Description here.
* @var fwcmd_test_para::dword40
* Please Place Description here.
* @var fwcmd_test_para::dword41
* Please Place Description here.
* @var fwcmd_test_para::dword42
* Please Place Description here.
* @var fwcmd_test_para::dword43
* Please Place Description here.
* @var fwcmd_test_para::dword44
* Please Place Description here.
* @var fwcmd_test_para::dword45
* Please Place Description here.
* @var fwcmd_test_para::byte46
* Please Place Description here.
*/
struct fwcmd_test_para {
#define MAX_SIGB_LEN 64
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u8 byte9;
u8 byte10;
u8 byte11;
u8 byte12;
u32 dword13;
u32 dword14;
u32 dword15;
u32 dword16;
u32 dword17;
u32 dword18;
u32 dword19;
u32 dword20;
u32 dword21;
u32 dword22;
u32 dword23;
u32 dword24;
u32 dword25;
u32 dword26;
u32 dword27;
u32 dword28;
u32 dword29;
u32 dword30;
u32 dword31;
u32 dword32;
u32 dword33;
u32 dword34;
u32 dword35;
u32 dword36;
u32 dword37;
u32 dword38;
u32 dword39;
u32 dword40;
u32 dword41;
u32 dword42;
u32 dword43;
u32 dword44;
u32 dword45;
u8 byte46[MAX_SIGB_LEN];
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwcmd_intf_f2p.h
|
C
|
agpl-3.0
| 14,585
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "fwdl.h"
#define FWDL_WAIT_CNT 400000
#define FWDL_SECTION_MAX_NUM 10
#define FWDL_SECTION_CHKSUM_LEN 8
#define FWDL_SECTION_PER_PKT_LEN 2020
#define FWDL_TRY_CNT 3
#define FWDL_DIGEST_SIZE 0x20
struct fwhdr_section_info {
u8 redl;
u8 *addr;
u32 len;
u32 dladdr;
};
struct fw_bin_info {
u8 section_num;
u32 hdr_len;
u32 git_idx;
struct fwhdr_section_info section_info[FWDL_SECTION_MAX_NUM];
};
struct hw_info {
u8 chip;
u8 cut;
u8 category;
};
struct fwld_info {
u32 len;
u8 *fw;
};
static inline void fwhdr_section_parser(struct fwhdr_section_t *section,
struct fwhdr_section_info *info)
{
u32 hdr_val;
u32 section_len;
hdr_val = le32_to_cpu(section->dword1);
section_len = GET_FIELD(hdr_val, SECTION_INFO_SEC_SIZE);
if (hdr_val & SECTION_INFO_CHECKSUM)
section_len += FWDL_SECTION_CHKSUM_LEN;
info->len = section_len;
info->redl = (hdr_val & SECTION_INFO_REDL) ? 1 : 0;
info->dladdr = (GET_FIELD(le32_to_cpu(section->dword0),
SECTION_INFO_SEC_DL_ADDR)) & 0x1FFFFFFF;
}
static inline void fwhdr_hdr_parser(struct fwhdr_hdr_t *hdr,
struct fw_bin_info *info)
{
u32 hdr_val;
hdr_val = le32_to_cpu(hdr->dword6);
info->section_num = GET_FIELD(hdr_val, FWHDR_SEC_NUM);
info->hdr_len = FWHDR_HDR_LEN + info->section_num * FWHDR_SECTION_LEN;
/* fill HALMAC information */
hdr_val = le32_to_cpu(hdr->dword7);
hdr_val = SET_CLR_WORD(hdr_val, FWDL_SECTION_PER_PKT_LEN,
FWHDR_FW_PART_SZ);
hdr->dword7 = cpu_to_le32(hdr_val);
hdr_val = le32_to_cpu(hdr->dword2);
info->git_idx = GET_FIELD(hdr_val, FWHDR_COMMITID);
}
static u32 fwhdr_parser(struct mac_ax_adapter *adapter, u8 *fw, u32 len,
struct fw_bin_info *info)
{
u32 i;
u8 *fw_end = fw + len;
u8 *bin_ptr;
struct fwhdr_section_info *cur_section_info;
if (!info) {
PLTFM_MSG_ERR("[ERR]%s: *info = NULL\n", __func__);
return MACNPTR;
} else if (!fw) {
PLTFM_MSG_ERR("[ERR]%s: *fw = NULL\n", __func__);
return MACNOITEM;
} else if (!len) {
PLTFM_MSG_ERR("[ERR]%s: len = 0\n", __func__);
return MACBUFSZ;
}
fwhdr_hdr_parser((struct fwhdr_hdr_t *)fw, info);
bin_ptr = fw + info->hdr_len;
/* jump to section header */
fw += FWHDR_HDR_LEN;
cur_section_info = info->section_info;
for (i = 0; i < info->section_num; i++) {
fwhdr_section_parser((struct fwhdr_section_t *)fw,
cur_section_info);
cur_section_info->addr = bin_ptr;
bin_ptr += cur_section_info->len;
fw += FWHDR_SECTION_LEN;
cur_section_info++;
}
if (fw_end != bin_ptr) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("fw bin size != fw size in fwhdr\n");
return MACFWBIN;
}
return MACSUCCESS;
}
static inline u32 update_fw_ver(struct mac_ax_adapter *adapter,
struct fwhdr_hdr_t *hdr)
{
u32 hdr_val;
struct mac_ax_fw_info *info = &adapter->fw_info;
hdr_val = le32_to_cpu(hdr->dword1);
info->major_ver = GET_FIELD(hdr_val, FWHDR_MAJORVER);
info->minor_ver = GET_FIELD(hdr_val, FWHDR_MINORVER);
info->sub_ver = GET_FIELD(hdr_val, FWHDR_SUBVERSION);
info->sub_idx = GET_FIELD(hdr_val, FWHDR_SUBINDEX);
hdr_val = le32_to_cpu(hdr->dword5);
info->build_year = GET_FIELD(hdr_val, FWHDR_YEAR);
hdr_val = le32_to_cpu(hdr->dword4);
info->build_mon = GET_FIELD(hdr_val, FWHDR_MONTH);
info->build_date = GET_FIELD(hdr_val, FWHDR_DATE);
info->build_hour = GET_FIELD(hdr_val, FWHDR_HOUR);
info->build_min = GET_FIELD(hdr_val, FWHDR_MIN);
info->h2c_seq = 0;
info->rec_seq = 0;
return MACSUCCESS;
}
static u32 __fwhdr_download(struct mac_ax_adapter *adapter,
u8 *fw, u32 hdr_len, u8 redl)
{
u8 *buf;
u32 ret = 0;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: h2cb_alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, hdr_len);
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: h2cb_put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, fw, hdr_len);
if (redl) {
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FWDL,
FWCMD_H2C_FUNC_FWHDR_REDL, 0, 0);
} else {
ret = h2c_pkt_set_hdr_fwdl(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FWDL,
FWCMD_H2C_FUNC_FWHDR_DL, 0, 0);
}
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: set h2c hdr fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: build h2c txd fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: PLTFM_TX fail\n", __func__);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
PLTFM_MSG_ERR("[ERR]%s ret: %d\n", __func__, ret);
return ret;
}
#if MAC_AX_PHL_H2C
static u32 __sections_build_txd(struct mac_ax_adapter *adapter,
struct rtw_h2c_pkt *h2cb)
{
u8 *buf;
u32 ret;
u32 txd_len;
struct rtw_t_meta_data info = {0};
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
info.type = RTW_PHL_PKT_TYPE_FWDL;
info.pktlen = (u16)h2cb->data_len;
txd_len = ops->txdesc_len(adapter, &info);
buf = h2cb_push(h2cb, txd_len);
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: h2cb_push fail\n", __func__);
return MACNPTR;
}
ret = ops->build_txdesc(adapter, &info, buf, txd_len);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("build_txdesc fail\n");
return ret;
}
return MACSUCCESS;
}
static u32 __sections_push(struct rtw_h2c_pkt *h2cb)
{
#define section_push_len 8
h2cb->vir_data -= section_push_len;
h2cb->vir_tail -= section_push_len;
return MACSUCCESS;
}
#else
static u32 __sections_build_txd(struct mac_ax_adapter *adapter,
struct h2c_buf *h2cb)
{
u8 *buf;
u32 ret;
u32 txd_len;
struct rtw_t_meta_data info;
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
info.type = RTW_PHL_PKT_TYPE_FWDL;
info.pktlen = (u16)h2cb->len;
txd_len = ops->txdesc_len(adapter, &info);
buf = h2cb_push(h2cb, txd_len);
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: h2cb_push fail\n", __func__);
return MACNPTR;
}
ret = ops->build_txdesc(adapter, &info, buf, txd_len);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("mac_build_txdesc fail\n");
return ret;
}
return MACSUCCESS;
}
#endif
static u32 __sections_download(struct mac_ax_adapter *adapter,
struct fwhdr_section_info *info)
{
u8 *section = info->addr;
u32 residue_len = info->len;
u32 pkt_len;
u8 *buf;
u32 ret = 0;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
while (residue_len) {
if (residue_len >= FWDL_SECTION_PER_PKT_LEN)
pkt_len = FWDL_SECTION_PER_PKT_LEN;
else
pkt_len = residue_len;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("h2cb_alloc fail\n");
return MACNPTR;
}
#if MAC_AX_PHL_H2C
__sections_push(h2cb);
#endif
buf = h2cb_put(h2cb, pkt_len);
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("h2cb_put fail\n");
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, section, pkt_len);
ret = __sections_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("__sections_build_txd fail\n");
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: PLTFM_TX fail\n", __func__);
goto fail;
}
h2cb_free(adapter, h2cb);
section += pkt_len;
residue_len -= pkt_len;
}
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
PLTFM_MSG_ERR("[ERR]%s ret: %d\n", __func__, ret);
return ret;
}
static u32 __write_memory(struct mac_ax_adapter *adapter,
u8 *buffer, u32 addr, u32 len)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 *content = NULL;
u32 dl_size;
u32 target_addr, write_addr;
u32 seg_size, seg_bytes;
u32 val32;
u32 index = 0;
u32 ret = MACSUCCESS;
PLTFM_MSG_WARN("%s ind access start\n", __func__);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, addr);
MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY, 0xAAAAAAAA);
MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY + 4, 0xBBBBBBBB);
val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY);
if (val32 != 0xAAAAAAAA) {
ret = MACMEMRO;
goto ind_aces_end;
}
val32 = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + 4);
if (val32 != 0xBBBBBBBB) {
ret = MACMEMRO;
goto ind_aces_end;
}
ind_aces_end:
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access end\n", __func__);
if (ret != MACSUCCESS)
return ret;
content = (u8 *)PLTFM_MALLOC(len);
if (!content) {
PLTFM_MSG_ERR("[ERR]%s: malloc fail\n", __func__);
return MACNOBUF;
}
PLTFM_MEMCPY(content, buffer, len);
dl_size = len;
target_addr = addr;
PLTFM_MSG_WARN("%s ind access trg 0x%X start\n", __func__, target_addr);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
while (dl_size != 0) {
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, target_addr);
write_addr = R_AX_INDIR_ACCESS_ENTRY;
if (dl_size >= ROMDL_SEG_LEN)
seg_size = ROMDL_SEG_LEN;
else
seg_size = dl_size;
seg_bytes = seg_size;
while (seg_bytes != 0) {
val32 = *((u32 *)(content + index));
MAC_REG_W32(write_addr,
cpu_to_le32(val32));
seg_bytes -= 4;
write_addr += 4;
index += 4;
}
target_addr += seg_size;
dl_size -= seg_size;
}
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access trg 0x%X end\n", __func__, target_addr);
PLTFM_FREE(content, len);
return MACSUCCESS;
}
static u32 fwdl_phase0(struct mac_ax_adapter *adapter)
{
u32 cnt = FWDL_WAIT_CNT;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (adapter->sm.fwdl != MAC_AX_FWDL_CPU_ON) {
PLTFM_MSG_ERR("[ERR]%s: state != CPU_ON\n", __func__);
return MACPROCERR;
}
while (--cnt) {
if (MAC_REG_R8(R_AX_WCPU_FW_CTRL) & B_AX_H2C_PATH_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]%s: poll 0x1E0[1] = 1 fail\n", __func__);
return MACPOLLTO;
}
adapter->sm.fwdl = MAC_AX_FWDL_H2C_PATH_RDY;
return MACSUCCESS;
}
static u32 fwdl_phase1(struct mac_ax_adapter *adapter,
u8 *fw, u32 hdr_len, u8 redl)
{
u32 ret;
u32 cnt = FWDL_WAIT_CNT;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (adapter->sm.fwdl != MAC_AX_FWDL_H2C_PATH_RDY) {
PLTFM_MSG_ERR("[ERR]%s: state != H2C_PATH_RDY\n", __func__);
return MACPROCERR;
}
ret = __fwhdr_download(adapter, fw, hdr_len, redl);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: __fwhdr_download fail\n", __func__);
return ret;
}
while (--cnt) {
if (MAC_REG_R8(R_AX_WCPU_FW_CTRL) & B_AX_FWDL_PATH_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]%s: poll 0x1E0[2] = 1 fail\n", __func__);
return MACPOLLTO;
}
MAC_REG_W32(R_AX_HALT_H2C_CTRL, 0);
MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0);
adapter->sm.fwdl = MAC_AX_FWDL_PATH_RDY;
return MACSUCCESS;
}
static u32 check_fw_rdy(struct mac_ax_adapter *adapter)
{
u32 val8 = FWDL_INITIAL_STATE;
u32 cnt = FWDL_WAIT_CNT;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
while (--cnt) {
val8 = GET_FIELD(MAC_REG_R8(R_AX_WCPU_FW_CTRL),
B_AX_WCPU_FWDL_STS);
if (val8 == FWDL_WCPU_FW_INIT_RDY)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]%s: poll 0x1E0[7:5] = 7 fail\n", __func__);
switch (val8) {
case FWDL_CHECKSUM_FAIL:
return MACFWCHKSUM;
case FWDL_SECURITY_FAIL:
return MACFWSECBOOT;
case FWDL_CUT_NOT_MATCH:
return MACFWCUT;
default:
return MACPOLLTO;
}
}
adapter->sm.fwdl = MAC_AX_FWDL_INIT_RDY;
return MACSUCCESS;
}
static u32 fwdl_phase2(struct mac_ax_adapter *adapter, u8 *fw,
struct fw_bin_info *info, u8 redl)
{
u32 ret;
u32 section_num = info->section_num;
struct fwhdr_section_info *section_info = info->section_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_PATH_RDY) {
PLTFM_MSG_ERR("[ERR]%s: state != FWDL_PATH_RDY\n", __func__);
return MACPROCERR;
}
while (section_num > 0) {
if (!redl) {
ret = __sections_download(adapter, section_info);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("__sections_download fail\n");
return ret;
}
} else {
if (section_info->redl) {
ret = __sections_download(adapter,
section_info);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("__sections_download ");
PLTFM_MSG_ERR("fail\n");
return ret;
}
}
}
section_info++;
section_num--;
}
PLTFM_DELAY_MS(5);
ret = check_fw_rdy(adapter);
if (ret) {
PLTFM_MSG_ERR("%s: check_fw_rdy fail\n", __func__);
return ret;
}
return MACSUCCESS;
}
static void fwdl_fail_dump(struct mac_ax_adapter *adapter,
struct fw_bin_info *info, u32 ret)
{
u32 val32, digest_addr, digest;
u16 val16, index;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FEATURE_DBGPKG
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
struct mac_ax_dbgpkg dbg_val = {0};
struct mac_ax_dbgpkg_en dbg_en = {0};
#endif
PLTFM_MSG_ERR("[ERR]fwdl ret = %d\n", ret);
val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL);
PLTFM_MSG_ERR("[ERR]fwdl 0x1E0 = 0x%x\n", val32);
val16 = MAC_REG_R16(R_AX_BOOT_DBG + 2);
PLTFM_MSG_ERR("[ERR]fwdl 0x83F2 = 0x%x\n", val16);
val32 = MAC_REG_R32(R_AX_UDM3);
PLTFM_MSG_ERR("[ERR]fwdl 0x1FC = 0x%x\n", val32);
val32 = info->git_idx;
PLTFM_MSG_ERR("[ERR]fw git idx = 0x%x\n", val32);
PLTFM_MUTEX_LOCK(&adapter->hw_info->dbg_port_lock);
adapter->hw_info->dbg_port_cnt++;
if (adapter->hw_info->dbg_port_cnt != 1) {
PLTFM_MSG_ERR("[ERR]fwdl fail dump lock cnt %d\n",
adapter->hw_info->dbg_port_cnt);
goto end;
}
MAC_REG_W32(R_AX_DBG_CTRL, 0xf200f2);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_SEL_0XC0);
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
for (index = 0; index < 15; index++) {
val32 = MAC_REG_R32(R_AX_DBG_PORT_SEL);
PLTFM_MSG_ERR("[ERR]fw PC = 0x%x\n", val32);
PLTFM_DELAY_US(10);
}
PLTFM_MSG_WARN("%s ind access FW digest start\n", __func__);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
digest_addr = (0xB8E17C00 + 64) & ~0xA0000000;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, digest_addr);
PLTFM_MSG_ERR("IRAM digest:");
for (index = 0; index < FWDL_DIGEST_SIZE; index += 4) {
digest = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY + index);
PLTFM_MSG_ERR("0x%x\t", digest);
}
PLTFM_MSG_ERR("DMEM digest:");
for (index = 0; index < FWDL_DIGEST_SIZE; index += 4) {
digest = MAC_REG_R32(R_AX_INDIR_ACCESS_ENTRY +
FWDL_DIGEST_SIZE + index);
PLTFM_MSG_ERR("0x%x\t", digest);
}
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access FW digest end\n", __func__);
pltfm_dbg_dump(adapter);
mac_ops->dump_ple_dbg_page(adapter, 0);
end:
#if MAC_AX_FEATURE_DBGPKG
dbg_en.ss_dbg = 0;
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.mac_dbg_port = 1;
dbg_en.plersvd_dbg = 1;
mac_ops->dbg_status_dump(adapter, &dbg_val, &dbg_en);
#endif
adapter->hw_info->dbg_port_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->dbg_port_lock);
}
u32 disable_fw_watchdog(struct mac_ax_adapter *adapter)
{
u32 val32, ret;
ret = mac_sram_dbg_write(adapter, R_AX_WDT_CTRL,
B_AX_WDT_CTRL_ALL_DIS, CPU_LOCAL_SEL);
if (ret)
return ret;
val32 = mac_sram_dbg_read(adapter, R_AX_WDT_STATUS, CPU_LOCAL_SEL);
val32 = val32 | B_AX_FS_WDT_INT;
val32 = val32 & (~B_AX_FS_WDT_INT_MSK);
ret = mac_sram_dbg_write(adapter, R_AX_WDT_STATUS, val32, CPU_LOCAL_SEL);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_fwredl(struct mac_ax_adapter *adapter, u8 *fw, u32 len)
{
u32 val32;
u32 ret;
struct fw_bin_info info;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL);
val32 &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
val32 = SET_CLR_WORD(val32, FWDL_INITIAL_STATE,
B_AX_WCPU_FWDL_STS);
MAC_REG_W32(R_AX_WCPU_FW_CTRL, val32);
ret = fwhdr_parser(adapter, fw, len, &info);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwhdr_parser fail\n", __func__);
goto fwdl_err;
}
ret = update_fw_ver(adapter, (struct fwhdr_hdr_t *)fw);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: update_fw_ver fail\n", __func__);
goto fwdl_err;
}
adapter->sm.fwdl = MAC_AX_FWDL_H2C_PATH_RDY;
ret = fwdl_phase1(adapter, fw, info.hdr_len, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwdl_phase1 fail\n", __func__);
goto fwdl_err;
}
ret = fwdl_phase2(adapter, fw, &info, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwdl_phase2 fail\n", __func__);
goto fwdl_err;
}
return MACSUCCESS;
fwdl_err:
fwdl_fail_dump(adapter, &info, ret);
return ret;
}
u32 mac_fwdl(struct mac_ax_adapter *adapter, u8 *fw, u32 len)
{
u8 retry_cnt;
u32 ret;
struct fw_bin_info info;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = 0;
retry_cnt = 0;
MAC_REG_W32(R_AX_UDM1, 0);
// FWDL retry, for 025 temp workaround
while (retry_cnt < FWDL_TRY_CNT) {
if (!fw) {
PLTFM_MSG_ERR("[ERR]%s: no fw\n", __func__);
ret = MACNOFW;
PLTFM_MEMSET(&info, 0, sizeof(struct fw_bin_info));
goto fwdl_err;
}
ret = fwhdr_parser(adapter, fw, len, &info);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwhdr_parser fail\n", __func__);
goto fwdl_err;
}
ret = update_fw_ver(adapter, (struct fwhdr_hdr_t *)fw);
if (ret)
goto fwdl_err;
ret = fwdl_phase0(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwdl_phase0 fail\n", __func__);
goto fwdl_err;
}
ret = fwdl_phase1(adapter, fw, info.hdr_len, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwdl_phase1 fail\n", __func__);
goto fwdl_err;
}
ret = fwdl_phase2(adapter, fw, &info, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwdl_phase2 fail\n", __func__);
goto fwdl_err;
}
return MACSUCCESS;
fwdl_err:
retry_cnt++;
PLTFM_MSG_ERR("[ERR]%s: Retry FWDL count %d\n", __func__, retry_cnt);
// At most retry 2 times
if (retry_cnt < FWDL_TRY_CNT) {
ret = mac_disable_cpu(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_disable_cpu fail\n", __func__);
fwdl_fail_dump(adapter, &info, ret);
return ret;
}
ret = mac_enable_cpu(adapter, AX_BOOT_REASON_PWR_ON, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__);
fwdl_fail_dump(adapter, &info, ret);
return ret;
}
MAC_REG_W32(R_AX_UDM1, retry_cnt);
} else {
break;
}
}
fwdl_fail_dump(adapter, &info, ret);
return ret;
}
u32 mac_enable_cpu(struct mac_ax_adapter *adapter, u8 boot_reason, u8 dlfw)
{
u32 val32, ret;
u16 val16;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (MAC_REG_R32(R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
return MACCPUSTATE;
if (adapter->sm.fwdl != MAC_AX_FWDL_IDLE) {
PLTFM_MSG_ERR("[ERR]%s: state != FWDL_IDLE\n", __func__);
return MACPROCERR;
}
//FW cannot support too much log. Reset R_AX_LDM for FW debug config
MAC_REG_W32(R_AX_LDM, 0);
MAC_REG_W32(R_AX_HALT_H2C_CTRL, 0);
MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0);
val32 = MAC_REG_R32(R_AX_UDM0);
val32 &= ~(B_AX_UDM0_DBG_MODE_CTRL | B_AX_UDM0_TRAP_LOOP_CTRL);
MAC_REG_W32(R_AX_UDM0, val32);
MAC_REG_W32(R_AX_SYS_CLK_CTRL,
MAC_REG_R32(R_AX_SYS_CLK_CTRL) | B_AX_CPU_CLK_EN);
val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL);
val32 &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
val32 = SET_CLR_WORD(val32, FWDL_INITIAL_STATE,
B_AX_WCPU_FWDL_STS);
if (dlfw)
val32 |= B_AX_WCPU_FWDL_EN;
MAC_REG_W32(R_AX_WCPU_FW_CTRL, val32);
val16 = MAC_REG_R16(R_AX_BOOT_REASON);
val16 = SET_CLR_WORD(val16, boot_reason, B_AX_BOOT_REASON);
MAC_REG_W16(R_AX_BOOT_REASON, val16);
val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE);
MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 | B_AX_WCPU_EN);
adapter->sm.fwdl = MAC_AX_FWDL_CPU_ON;
if (!dlfw) {
PLTFM_DELAY_MS(5);
ret = check_fw_rdy(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: ", __func__);
PLTFM_MSG_ERR("check_fw_rdy fail\n");
return ret;
}
}
// Prevent sequence number in HALMAC and FW mismatching
reset_lps_seq_num(adapter);
return MACSUCCESS;
}
u32 mac_disable_cpu(struct mac_ax_adapter *adapter)
{
u32 val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
adapter->sm.fwdl = MAC_AX_FWDL_IDLE;
//todo: need to check cpu in safe state before reset CPU
val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE);
MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 & ~B_AX_WCPU_EN);
val32 = MAC_REG_R32(R_AX_UDM0);
val32 &= ~(B_AX_UDM0_DBG_MODE_CTRL | B_AX_UDM0_TRAP_LOOP_CTRL);
MAC_REG_W32(R_AX_UDM0, val32);
val32 = MAC_REG_R32(R_AX_WCPU_FW_CTRL);
val32 &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
MAC_REG_W32(R_AX_WCPU_FW_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_CLK_CTRL);
MAC_REG_W32(R_AX_SYS_CLK_CTRL, val32 & ~B_AX_CPU_CLK_EN);
ret = disable_fw_watchdog(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: disable_fw_watchdog fail\n", __func__);
return ret;
}
adapter->sm.plat = MAC_AX_PLAT_OFF;
val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE);
MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 & ~B_AX_PLATFORM_EN);
val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE);
MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32 | B_AX_PLATFORM_EN);
adapter->sm.plat = MAC_AX_PLAT_ON;
return MACSUCCESS;
}
u32 mac_romdl(struct mac_ax_adapter *adapter, u8 *ROM, u32 ROM_addr, u32 len)
{
u8 *content = NULL;
u32 val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = mac_disable_cpu(adapter);
if (ret)
return ret;
if (!ROM)
return MACNOITEM;
val32 = MAC_REG_R32(R_AX_SEC_CTRL);
if (val32 & BIT(0)) {
ret = __write_memory(adapter, ROM, ROM_addr, len);
if (ret)
return ret;
} else {
PLTFM_MSG_ERR("[ERR]%s: __write_memory fail\n", __func__);
return MACSECUREON;
}
PLTFM_FREE(content, len);
return MACSUCCESS;
}
u32 mac_ram_boot(struct mac_ax_adapter *adapter, u8 *fw, u32 len)
{
u32 addr;
u32 ret, section_num;
struct fw_bin_info info;
struct fwhdr_section_info *section_info;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
ret = mac_disable_cpu(adapter);
if (ret)
goto fwdl_err;
ret = fwhdr_parser(adapter, fw, len, &info);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: fwhdr_parser fail\n", __func__);
goto fwdl_err;
}
ret = update_fw_ver(adapter, (struct fwhdr_hdr_t *)fw);
if (ret)
goto fwdl_err;
section_num = info.section_num;
section_info = info.section_info;
while (section_num > 0) {
ret = __write_memory(adapter, section_info->addr,
section_info->dladdr, section_info->len);
if (ret)
goto fwdl_err;
section_info++;
section_num--;
}
addr = (0xb8003000 + R_AX_CPU_BOOT_ADDR) & 0x1FFFFFFF;
PLTFM_MSG_WARN("%s ind access 0x%X start\n", __func__, addr);
PLTFM_MUTEX_LOCK(&adapter->hw_info->ind_access_lock);
adapter->hw_info->ind_aces_cnt++;
MAC_REG_W32(R_AX_FILTER_MODEL_ADDR, addr);
MAC_REG_W32(R_AX_INDIR_ACCESS_ENTRY, (info.section_info[0].dladdr) |
0xA0000000);
adapter->hw_info->ind_aces_cnt--;
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->ind_access_lock);
PLTFM_MSG_WARN("%s ind access 0x%X end\n", __func__, addr);
ret = mac_enable_cpu(adapter, AX_BOOT_REASON_PWR_ON, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__);
goto fwdl_err;
}
PLTFM_DELAY_MS(10);
ret = check_fw_rdy(adapter);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: check_fw_rdy fail\n", __func__);
goto fwdl_err;
}
return MACSUCCESS;
fwdl_err:
fwdl_fail_dump(adapter, &info, ret);
return ret;
}
u32 mac_enable_fw(struct mac_ax_adapter *adapter, enum rtw_fw_type cat)
{
u32 ret = MACSUCCESS;
#if defined(PHL_FEATURE_AP) || defined(PHL_FEATURE_NIC)
u32 chip_id, cv;
u32 fw_len = 0;
u8 *fw = NULL;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
chip_id = GET_FIELD(MAC_REG_R32(R_AX_SYS_CHIPINFO), B_AX_HW_ID);
cv = GET_FIELD(MAC_REG_R32(R_AX_SYS_CFG1), B_AX_CHIP_VER);
switch (chip_id) {
#ifdef CONFIG_RTL8852A
case RTL8852A_ID:
switch (cv) {
#ifdef MAC_FW_8852A_U2
case FWDL_CBV:
switch (cat) {
#ifdef PHL_FEATURE_AP
case RTW_FW_AP:
fw_len = array_length_8852a_u2_ap;
fw = array_8852a_u2_ap;
break;
#endif /*PHL_FEATURE_AP*/
#ifdef PHL_FEATURE_NIC
case RTW_FW_NIC:
fw_len = array_length_8852a_u2_nic;
fw = array_8852a_u2_nic;
break;
#ifdef CONFIG_WOWLAN
case RTW_FW_WOWLAN:
fw_len = array_length_8852a_u2_wowlan;
fw = array_8852a_u2_wowlan;
break;
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
default:
PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*MAC_FW_8852A_U2*/
#ifdef MAC_FW_8852A_U3
case FWDL_CCV:
switch (cat) {
#ifdef PHL_FEATURE_AP
case RTW_FW_AP:
fw_len = array_length_8852a_u3_ap;
fw = array_8852a_u3_ap;
break;
#endif /*PHL_FEATURE_AP*/
#ifdef PHL_FEATURE_NIC
case RTW_FW_NIC:
fw_len = array_length_8852a_u3_nic;
fw = array_8852a_u3_nic;
break;
#ifdef CONFIG_WOWLAN
case RTW_FW_WOWLAN:
fw_len = array_length_8852a_u3_wowlan;
fw = array_8852a_u3_wowlan;
break;
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
default:
PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*MAC_FW_8852A_U3*/
default:
PLTFM_MSG_ERR("[ERR]%s: invalid cut\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*CONFIG_RTL8852A*/
#ifdef CONFIG_RTL8852B
case RTL8852B_ID:
switch (cv) {
#ifdef MAC_FW_8852B_U1
case FWDL_CAV:
switch (cat) {
#ifdef PHL_FEATURE_AP
case RTW_FW_AP:
fw_len = array_length_8852b_u1_ap;
fw = array_8852b_u1_ap;
break;
#endif /*PHL_FEATURE_AP*/
#ifdef PHL_FEATURE_NIC
case RTW_FW_NIC:
fw_len = array_length_8852b_u1_nic;
fw = array_8852b_u1_nic;
break;
#ifdef CONFIG_WOWLAN
case RTW_FW_WOWLAN:
fw_len = array_length_8852b_u1_wowlan;
fw = array_8852b_u1_wowlan;
break;
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
default:
PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*MAC_FW_8852B_U1*/
#ifdef MAC_FW_8852B_U2
case FWDL_CBV:
switch (cat) {
#ifdef PHL_FEATURE_NIC
case RTW_FW_NIC:
fw_len = array_length_8852b_u2_nic;
fw = array_8852b_u2_nic;
break;
#ifdef CONFIG_WOWLAN
case RTW_FW_WOWLAN:
fw_len = array_length_8852b_u2_wowlan;
fw = array_8852b_u2_wowlan;
break;
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
default:
PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*MAC_FW_8852B_U2*/
default:
PLTFM_MSG_ERR("[ERR]%s: invalid cut\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*CONFIG_RTL8852B*/
#ifdef CONFIG_RTL8852C
case RTL8852C_ID:
switch (cv) {
#ifdef MAC_FW_8852C_U1
case FWDL_CAV:
switch (cat) {
#ifdef PHL_FEATURE_AP
case RTW_FW_AP:
fw_len = array_length_8852c_u1_ap;
fw = array_8852c_u1_ap;
break;
#endif /*PHL_FEATURE_AP*/
#ifdef PHL_FEATURE_NIC
case RTW_FW_NIC:
fw_len = array_length_8852c_u1_nic;
fw = array_8852c_u1_nic;
break;
#ifdef CONFIG_WOWLAN
case RTW_FW_WOWLAN:
fw_len = array_length_8852c_u1_wowlan;
fw = array_8852c_u1_wowlan;
break;
#endif /*CONFIG_WOWLAN*/
#endif /*PHL_FEATURE_NIC*/
default:
PLTFM_MSG_ERR("[ERR]%s: no cat\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*MAC_FW_8852C_U1*/
default:
PLTFM_MSG_ERR("[ERR]%s: invalid cut\n", __func__);
fw_len = 0;
fw = 0;
break;
}
break;
#endif /*CONFIG_RTL8852C*/
default:
PLTFM_MSG_ERR("[ERR]%s: invalid chip\n", __func__);
fw_len = 0;
fw = 0;
break;
}
ret = mac_disable_cpu(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_disable_cpu fail\n", __func__);
return ret;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
ret = mac_check_OTP(adapter, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_check_OTP fail\n",
__func__);
return ret;
}
}
ret = mac_enable_cpu(adapter, AX_BOOT_REASON_PWR_ON, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__);
return ret;
}
ret = mac_fwdl(adapter, fw, fw_len);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_enable_cpu fail\n", __func__);
return ret;
}
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
ret = mac_check_OTP(adapter, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]%s: mac_check_OTP fail\n",
__func__);
return ret;
}
}
#endif /* #if defined(PHL_FEATURE_AP) || defined(PHL_FEATURE_NIC) */
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwdl.c
|
C
|
agpl-3.0
| 29,870
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FWDL_H_
#define _MAC_AX_FWDL_H_
#include "../type.h"
#include "fwcmd.h"
#include "trx_desc.h"
#include "trxcfg.h"
#include "dle.h"
#include "hci_fc.h"
#include "power_saving.h"
#if MAC_AX_PCIE_SUPPORT
#include "_pcie.h"
#endif
#if MAC_AX_8852A_SUPPORT
#include "../fw_ax/rtl8852a/hal8852a_fw.h"
#endif
#if MAC_AX_8852B_SUPPORT
#include "../fw_ax/rtl8852b/hal8852b_fw_u1.h"
#include "../fw_ax/rtl8852b/hal8852b_fw.h"
#endif
#define FWHDR_HDR_LEN (sizeof(struct fwhdr_hdr_t))
#define FWHDR_SECTION_LEN (sizeof(struct fwhdr_section_t))
#define ROMDL_SEG_LEN 0x40000
#define AX_BOOT_REASON_PWR_ON 0
#define AX_BOOT_REASON_WDT 1
#define AX_BOOT_REASON_LPS 2
#define RTL8852A_ID 0x50
#define RTL8852B_ID 0x51
#define RTL8852C_ID 0x52
#define RTL8834A_ID 0x53
#define RTL8852A_ROM_ADDR 0x18900000
#define RTL8852B_ROM_ADDR 0x18900000
#define RTL8852C_ROM_ADDR 0x20000000
#define RTL8192XB_ROM_ADDR 0x20000000
/**
* @struct fwhdr_hdr_t
* @brief fwhdr_hdr_t
*
* @var fwhdr_hdr_t::dword0
* Please Place Description here.
* @var fwhdr_hdr_t::dword1
* Please Place Description here.
* @var fwhdr_hdr_t::dword2
* Please Place Description here.
* @var fwhdr_hdr_t::dword3
* Please Place Description here.
* @var fwhdr_hdr_t::dword4
* Please Place Description here.
* @var fwhdr_hdr_t::dword5
* Please Place Description here.
* @var fwhdr_hdr_t::dword6
* Please Place Description here.
* @var fwhdr_hdr_t::dword7
* Please Place Description here.
*/
struct fwhdr_hdr_t {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
};
/**
* @struct fwhdr_section_t
* @brief fwhdr_section_t
*
* @var fwhdr_section_t::dword0
* Please Place Description here.
* @var fwhdr_section_t::dword1
* Please Place Description here.
* @var fwhdr_section_t::dword2
* Please Place Description here.
* @var fwhdr_section_t::dword3
* Please Place Description here.
*/
struct fwhdr_section_t {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
};
/**
* @enum fw_dl_status
*
* @brief fw_dl_status
*
* @var fw_dl_status::FWDL_INITIAL_STATE
* Please Place Description here.
* @var fw_dl_status::FWDL_FWDL_ONGOING
* Please Place Description here.
* @var fw_dl_status::FWDL_CHECKSUM_FAIL
* Please Place Description here.
* @var fw_dl_status::FWDL_SECURITY_FAIL
* Please Place Description here.
* @var fw_dl_status::FWDL_CUT_NOT_MATCH
* Please Place Description here.
* @var fw_dl_status::FWDL_RSVD0
* Please Place Description here.
* @var fw_dl_status::FWDL_WCPU_FWDL_RDY
* Please Place Description here.
* @var fw_dl_status::FWDL_WCPU_FW_INIT_RDY
* Please Place Description here.
*/
enum fw_dl_status {
FWDL_INITIAL_STATE = 0,
FWDL_FWDL_ONGOING = 1,
FWDL_CHECKSUM_FAIL = 2,
FWDL_SECURITY_FAIL = 3,
FWDL_CUT_NOT_MATCH = 4,
FWDL_RSVD0 = 5,
FWDL_WCPU_FWDL_RDY = 6,
FWDL_WCPU_FW_INIT_RDY = 7
};
/**
* @enum fw_dl_cv
*
* @brief fw_dl_cv
*
* @var fw_dl_chip_cut::FWDL_CAV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CBV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CCV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CDV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CEV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CFV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CGV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CHV
* Please Place Description here.
* @var fw_dl_chip_cut::FWDL_CIV
* Please Place Description here.
*/
enum fw_dl_cv {
FWDL_CAV = 0,
FWDL_CBV = 1,
FWDL_CCV,
FWDL_CDV,
FWDL_CEV,
FWDL_CFV,
FWDL_CGV,
FWDL_CHV,
FWDL_CIV,
};
/* === FW header === */
/* dword0 */
#define FWHDR_CUTID_SH 0
#define FWHDR_CUTID_MSK 0xff
#define FWHDR_CHIPID_SH 8
#define FWHDR_CHIPID_MSK 0xffffff
/* dword1 */
#define FWHDR_MAJORVER_SH 0
#define FWHDR_MAJORVER_MSK 0xff
#define FWHDR_MINORVER_SH 8
#define FWHDR_MINORVER_MSK 0xff
#define FWHDR_SUBVERSION_SH 16
#define FWHDR_SUBVERSION_MSK 0xff
#define FWHDR_SUBINDEX_SH 24
#define FWHDR_SUBINDEX_MSK 0xff
/* dword2 */
#define FWHDR_COMMITID_SH 0
#define FWHDR_COMMITID_MSK 0xffffffff
/* dword3 */
#define FWHDR_SEC_HDR_OFFSET_SH 0
#define FWHDR_SEC_HDR_OFFSET_MSK 0xff
#define FWHDR_SEC_HDR_SZ_SH 8
#define FWHDR_SEC_HDR_SZ_MSK 0xff
#define FWHDR_FWHDR_SZ_SH 16
#define FWHDR_FWHDR_SZ_MSK 0xff
#define FWHDR_FWHDR_VER_SH 24
#define FWHDR_FWHDR_VER_MSK 0xff
/* dword4 */
#define FWHDR_MONTH_SH 0
#define FWHDR_MONTH_MSK 0xff
#define FWHDR_DATE_SH 8
#define FWHDR_DATE_MSK 0xff
#define FWHDR_HOUR_SH 16
#define FWHDR_HOUR_MSK 0xff
#define FWHDR_MIN_SH 24
#define FWHDR_MIN_MSK 0xff
/* dword5 */
#define FWHDR_YEAR_SH 0
#define FWHDR_YEAR_MSK 0xffff
/* dword6 */
#define FWHDR_IMAGEFROM_SH 0
#define FWHDR_IMAGEFROM_MSK 0x3
#define FWHDR_BOOTFROM_SH 4
#define FWHDR_BOOTFROM_MSK 0x3
#define FWHDR_ROM_ONLY BIT(6)
#define FWHDR_FW_TYPE BIT(7)
#define FWHDR_SEC_NUM_SH 8
#define FWHDR_SEC_NUM_MSK 0xff
#define FWHDR_HCI_TYPE_SH 16
#define FWHDR_HCI_TYPE_MSK 0xf
#define FWHDR_NET_TYPE_SH 20
#define FWHDR_NET_TYPE_MSK 0xf
/* dword7 */
#define FWHDR_FW_PART_SZ_SH 0
#define FWHDR_FW_PART_SZ_MSK 0xffff
#define FWHDR_CMD_VER_SH 24
#define FWHDR_CMD_VER_MSK 0xff
/* === Section header === */
/* dword0 */
#define SECTION_INFO_SEC_DL_ADDR_SH 0
#define SECTION_INFO_SEC_DL_ADDR_MSK 0xffffffff
/* dword1 */
#define SECTION_INFO_SEC_SIZE_SH 0
#define SECTION_INFO_SEC_SIZE_MSK 0xffffff
#define SECTION_INFO_SECTIONTYPE_SH 24
#define SECTION_INFO_SECTIONTYPE_MSK 0xf
#define SECTION_INFO_CHECKSUM BIT(28)
#define SECTION_INFO_REDL BIT(29)
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief disable_fw_watchdog
*
* @param *adapter
* @param *fw
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 disable_fw_watchdog(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_fwredl
*
* @param *adapter
* @param *fw
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fwredl(struct mac_ax_adapter *adapter, u8 *fw, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_fwdl
*
* @param *adapter
* @param *fw
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_fwdl(struct mac_ax_adapter *adapter, u8 *fw, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_enable_cpu
*
* @param *adapter
* @param boot_reason
* @param dlfw
* @return Please Place Description here.
* @retval u32
*/
u32 mac_enable_cpu(struct mac_ax_adapter *adapter, u8 boot_reason, u8 dlfw);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_disable_cpu
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_disable_cpu(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_romdl
*
* @param *adapter
* @param *rom
* @param romaddr
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_romdl(struct mac_ax_adapter *adapter, u8 *rom, u32 romaddr, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_ram_boot
*
* @param *adapter
* @param *fw
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ram_boot(struct mac_ax_adapter *adapter, u8 *fw, u32 len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Download
* @{
*/
/**
* @brief mac_enable_fw
*
* @param *adapter
* @param cat
* @return Please Place Description here.
* @retval u32
*/
u32 mac_enable_fw(struct mac_ax_adapter *adapter, enum rtw_fw_type cat);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwdl.h
|
C
|
agpl-3.0
| 8,669
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "fwdl.h"
static u32 get_io_ofld_cap(struct mac_ax_adapter *adapter, u32 *val)
{
#define MAC_AX_IO_OFLD_MAJ_VER 0
#define MAC_AX_IO_OFLD_MIN_VER 10
#define MAC_AX_IO_OFLD_SUB_VER 3
#define MAC_AX_IO_OFLD_SUB_IDX 0
struct mac_ax_fw_info *fw_info = &adapter->fw_info;
if (fw_info->minor_ver > MAC_AX_IO_OFLD_MIN_VER) {
*val |= FW_CAP_IO_OFLD;
return MACSUCCESS;
}
if (fw_info->minor_ver == MAC_AX_IO_OFLD_MIN_VER &&
fw_info->sub_ver >= MAC_AX_IO_OFLD_SUB_VER)
*val |= FW_CAP_IO_OFLD;
return MACSUCCESS;
}
u32 mac_get_fw_cap(struct mac_ax_adapter *adapter, u32 *val)
{
*val = 0;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACFWNONRDY;
get_io_ofld_cap(adapter, val);
return MACSUCCESS;
}
u32 mac_reset_fwofld_state(struct mac_ax_adapter *adapter, u8 op)
{
switch (op) {
case FW_OFLD_OP_DUMP_EFUSE:
adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_IDLE;
break;
case FW_OFLD_OP_PACKET_OFLD:
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE;
break;
case FW_OFLD_OP_READ_OFLD:
adapter->sm.read_request = MAC_AX_OFLD_REQ_IDLE;
adapter->sm.read_h2c = MAC_AX_OFLD_H2C_IDLE;
break;
case FW_OFLD_OP_WRITE_OFLD:
adapter->sm.write_request = MAC_AX_OFLD_REQ_IDLE;
adapter->sm.write_h2c = MAC_AX_OFLD_H2C_IDLE;
break;
case FW_OFLD_OP_CONF_OFLD:
adapter->sm.conf_request = MAC_AX_OFLD_REQ_IDLE;
adapter->sm.conf_h2c = MAC_AX_OFLD_H2C_IDLE;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_check_fwofld_done(struct mac_ax_adapter *adapter, u8 op)
{
struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info;
switch (op) {
case FW_OFLD_OP_DUMP_EFUSE:
if (adapter->sm.efuse_ofld == MAC_AX_OFLD_H2C_IDLE)
return MACSUCCESS;
break;
case FW_OFLD_OP_PACKET_OFLD:
if (ofld_info->last_op == PKT_OFLD_OP_READ) {
if (adapter->sm.pkt_ofld == MAC_AX_OFLD_H2C_DONE)
return MACSUCCESS;
} else {
if (adapter->sm.pkt_ofld == MAC_AX_OFLD_H2C_IDLE)
return MACSUCCESS;
}
break;
case FW_OFLD_OP_READ_OFLD:
if (adapter->sm.read_h2c == MAC_AX_OFLD_H2C_DONE)
return MACSUCCESS;
break;
case FW_OFLD_OP_WRITE_OFLD:
if (adapter->sm.write_h2c == MAC_AX_OFLD_H2C_IDLE)
return MACSUCCESS;
break;
case FW_OFLD_OP_CONF_OFLD:
if (adapter->sm.conf_h2c == MAC_AX_OFLD_H2C_IDLE)
return MACSUCCESS;
break;
default:
return MACNOITEM;
}
return MACPROCBUSY;
}
static u32 cnv_write_ofld_state(struct mac_ax_adapter *adapter, u8 dest)
{
u8 state;
state = adapter->sm.write_request;
if (state > MAC_AX_OFLD_REQ_CLEANED)
return MACPROCERR;
if (dest == MAC_AX_OFLD_REQ_IDLE) {
if (state != MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_CLEANED) {
if (state == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_CREATED) {
if (state == MAC_AX_OFLD_REQ_IDLE ||
state == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_H2C_SENT) {
if (state != MAC_AX_OFLD_REQ_CREATED)
return MACPROCERR;
}
adapter->sm.write_request = dest;
return MACSUCCESS;
}
u32 mac_clear_write_request(struct mac_ax_adapter *adapter)
{
if (adapter->sm.write_request == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
if (cnv_write_ofld_state(adapter, MAC_AX_OFLD_REQ_CLEANED)
!= MACSUCCESS)
return MACPROCERR;
PLTFM_FREE(adapter->write_ofld_info.buf,
adapter->write_ofld_info.buf_size);
adapter->write_ofld_info.buf = NULL;
adapter->write_ofld_info.buf_wptr = NULL;
adapter->write_ofld_info.last_req = NULL;
adapter->write_ofld_info.buf_size = 0;
adapter->write_ofld_info.avl_buf_size = 0;
adapter->write_ofld_info.used_size = 0;
adapter->write_ofld_info.req_num = 0;
return MACSUCCESS;
}
u32 mac_add_write_request(struct mac_ax_adapter *adapter,
struct mac_ax_write_req *req, u8 *value, u8 *mask)
{
struct mac_ax_write_ofld_info *ofld_info = &adapter->write_ofld_info;
struct fwcmd_write_ofld_req *write_ptr;
u32 data_len = 0;
u8 state;
state = adapter->sm.write_request;
if (!(state == MAC_AX_OFLD_REQ_CREATED ||
state == MAC_AX_OFLD_REQ_CLEANED)) {
return MACPROCERR;
}
if (!ofld_info->buf) {
ofld_info->buf = (u8 *)PLTFM_MALLOC(WRITE_OFLD_MAX_LEN);
if (!ofld_info->buf)
return MACNPTR;
ofld_info->buf_wptr = ofld_info->buf;
ofld_info->buf_size = WRITE_OFLD_MAX_LEN;
ofld_info->avl_buf_size = WRITE_OFLD_MAX_LEN;
ofld_info->used_size = 0;
ofld_info->req_num = 0;
}
data_len = sizeof(struct mac_ax_write_req);
data_len += req->value_len;
if (req->mask_en == 1)
data_len += req->value_len;
if (ofld_info->avl_buf_size < data_len)
return MACNOBUF;
if (!value)
return MACNPTR;
if (req->mask_en == 1 && !mask)
return MACNPTR;
if (cnv_write_ofld_state(adapter,
MAC_AX_OFLD_REQ_CREATED) != MACSUCCESS)
return MACPROCERR;
if (ofld_info->req_num != 0)
ofld_info->last_req->ls = 0;
ofld_info->last_req = (struct mac_ax_write_req *)ofld_info->buf_wptr;
req->ls = 1;
write_ptr = (struct fwcmd_write_ofld_req *)ofld_info->buf_wptr;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(req->value_len,
FWCMD_H2C_WRITE_OFLD_REQ_VALUE_LEN) |
SET_WORD(req->ofld_id,
FWCMD_H2C_WRITE_OFLD_REQ_OFLD_ID) |
SET_WORD(req->entry_num,
FWCMD_H2C_WRITE_OFLD_REQ_ENTRY_NUM) |
req->polling | req->mask_en | req->ls
);
write_ptr->dword1 =
cpu_to_le32(SET_WORD(req->offset,
FWCMD_H2C_WRITE_OFLD_REQ_OFFSET)
);
ofld_info->buf_wptr += sizeof(struct mac_ax_write_req);
ofld_info->avl_buf_size -= sizeof(struct mac_ax_write_req);
ofld_info->used_size += sizeof(struct mac_ax_write_req);
PLTFM_MEMCPY(ofld_info->buf_wptr, value, req->value_len);
ofld_info->buf_wptr += req->value_len;
ofld_info->avl_buf_size -= req->value_len;
ofld_info->used_size += req->value_len;
if (req->mask_en == 1) {
PLTFM_MEMCPY(ofld_info->buf_wptr, mask, req->value_len);
ofld_info->buf_wptr += req->value_len;
ofld_info->avl_buf_size -= req->value_len;
ofld_info->used_size += req->value_len;
}
ofld_info->req_num++;
return MACSUCCESS;
}
u32 mac_write_ofld(struct mac_ax_adapter *adapter)
{
u8 *buf;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_write_ofld_info *ofld_info = &adapter->write_ofld_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (ofld_info->used_size + FWCMD_HDR_LEN > READ_OFLD_MAX_LEN)
return MACBUFSZ;
if (adapter->sm.write_h2c != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
if (adapter->sm.write_request != MAC_AX_OFLD_REQ_CREATED)
return MACPROCERR;
if (cnv_write_ofld_state(adapter,
MAC_AX_OFLD_REQ_H2C_SENT) != MACSUCCESS)
return MACPROCERR;
adapter->sm.write_h2c = MAC_AX_OFLD_H2C_SENDING;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, ofld_info->used_size);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, ofld_info->buf, ofld_info->used_size);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_WRITE_OFLD,
1, 1);
if (ret)
goto fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.write_request = MAC_AX_OFLD_REQ_IDLE;
adapter->sm.write_h2c = MAC_AX_OFLD_H2C_IDLE;
goto fail;
}
h2cb_free(adapter, h2cb);
if (cnv_write_ofld_state(adapter, MAC_AX_OFLD_REQ_IDLE) != MACSUCCESS)
return MACPROCERR;
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 cnv_conf_ofld_state(struct mac_ax_adapter *adapter, u8 dest)
{
u8 state;
state = adapter->sm.conf_request;
if (state > MAC_AX_OFLD_REQ_CLEANED)
return MACPROCERR;
if (dest == MAC_AX_OFLD_REQ_IDLE) {
if (state != MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_CLEANED) {
if (state == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_CREATED) {
if (state == MAC_AX_OFLD_REQ_IDLE ||
state == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_H2C_SENT) {
if (state != MAC_AX_OFLD_REQ_CREATED)
return MACPROCERR;
}
adapter->sm.conf_request = dest;
return MACSUCCESS;
}
u32 mac_clear_conf_request(struct mac_ax_adapter *adapter)
{
if (adapter->sm.conf_request == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
if (cnv_conf_ofld_state(adapter, MAC_AX_OFLD_REQ_CLEANED) !=
MACSUCCESS)
return MACPROCERR;
PLTFM_FREE(adapter->conf_ofld_info.buf,
adapter->conf_ofld_info.buf_size);
adapter->conf_ofld_info.buf = NULL;
adapter->conf_ofld_info.buf_wptr = NULL;
adapter->conf_ofld_info.buf_size = 0;
adapter->conf_ofld_info.avl_buf_size = 0;
adapter->conf_ofld_info.used_size = 0;
adapter->conf_ofld_info.req_num = 0;
return MACSUCCESS;
}
u32 mac_add_conf_request(struct mac_ax_adapter *adapter,
struct mac_ax_conf_ofld_req *req)
{
struct mac_ax_conf_ofld_info *ofld_info = &adapter->conf_ofld_info;
struct fwcmd_conf_ofld_req_cmd *write_ptr;
u8 state;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
state = adapter->sm.conf_request;
if (!(state == MAC_AX_OFLD_REQ_CREATED ||
state == MAC_AX_OFLD_REQ_CLEANED)) {
return MACPROCERR;
}
if (!ofld_info->buf) {
ofld_info->buf = (u8 *)PLTFM_MALLOC(CONF_OFLD_MAX_LEN);
if (!ofld_info->buf)
return MACNPTR;
ofld_info->buf_wptr = ofld_info->buf;
ofld_info->buf_size = CONF_OFLD_MAX_LEN;
ofld_info->avl_buf_size = CONF_OFLD_MAX_LEN;
ofld_info->used_size = 0;
ofld_info->req_num = 0;
}
if (ofld_info->avl_buf_size < sizeof(struct mac_ax_conf_ofld_req))
return MACNOBUF;
if (cnv_conf_ofld_state(adapter, MAC_AX_OFLD_REQ_CREATED) != MACSUCCESS)
return MACPROCERR;
write_ptr = (struct fwcmd_conf_ofld_req_cmd *)ofld_info->buf_wptr;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(req->device,
FWCMD_H2C_CONF_OFLD_REQ_CMD_DEVICE)
);
write_ptr->dword1 =
cpu_to_le32(SET_WORD(req->req.hioe.hioe_op,
FWCMD_H2C_CONF_OFLD_REQ_CMD_HIOE_OP) |
SET_WORD(req->req.hioe.inst_type,
FWCMD_H2C_CONF_OFLD_REQ_CMD_INST_TYPE) |
SET_WORD(req->req.hioe.data_mode,
FWCMD_H2C_CONF_OFLD_REQ_CMD_DATA_MODE)
);
write_ptr->dword2 = cpu_to_le32(req->req.hioe.param0.register_addr);
write_ptr->dword3 =
cpu_to_le32(SET_WORD(req->req.hioe.param1.byte_data_h,
FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_H) |
SET_WORD(req->req.hioe.param2.byte_data_l,
FWCMD_H2C_CONF_OFLD_REQ_CMD_BYTE_DATA_L)
);
ofld_info->buf_wptr += sizeof(struct mac_ax_conf_ofld_req);
ofld_info->avl_buf_size -= sizeof(struct mac_ax_conf_ofld_req);
ofld_info->used_size += sizeof(struct mac_ax_conf_ofld_req);
ofld_info->req_num++;
return MACSUCCESS;
}
u32 mac_conf_ofld(struct mac_ax_adapter *adapter)
{
u8 *buf;
u32 ret;
struct fwcmd_conf_ofld *write_ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_conf_ofld_info *ofld_info = &adapter->conf_ofld_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (ofld_info->used_size + FWCMD_HDR_LEN > CONF_OFLD_MAX_LEN)
return MACBUFSZ;
if (adapter->sm.conf_h2c != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
if (adapter->sm.conf_request != MAC_AX_OFLD_REQ_CREATED)
return MACPROCERR;
if (cnv_conf_ofld_state(adapter,
MAC_AX_OFLD_REQ_H2C_SENT) != MACSUCCESS)
return MACPROCERR;
adapter->sm.conf_h2c = MAC_AX_OFLD_H2C_SENDING;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_conf_ofld_hdr));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_conf_ofld *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(ofld_info->req_num,
FWCMD_H2C_CONF_OFLD_PATTERN_COUNT));
buf = h2cb_put(h2cb, ofld_info->used_size);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, ofld_info->buf, ofld_info->used_size);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_CONF_OFLD,
1, 1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.conf_request = MAC_AX_OFLD_REQ_IDLE;
adapter->sm.conf_h2c = MAC_AX_OFLD_H2C_IDLE;
goto fail;
}
h2cb_free(adapter, h2cb);
if (cnv_conf_ofld_state(adapter, MAC_AX_OFLD_REQ_IDLE) != MACSUCCESS)
return MACPROCERR;
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static inline void mac_pkt_ofld_set_bitmap(u8 *bitmap, u16 index)
{
bitmap[index >> 3] |= (1 << (index & 7));
}
static inline void mac_pkt_ofld_unset_bitmap(u8 *bitmap, u16 index)
{
bitmap[index >> 3] &= ~(1 << (index & 7));
}
static inline u8 mac_pkt_ofld_get_bitmap(u8 *bitmap, u16 index)
{
return bitmap[index / 8] & (1 << (index & 7)) ? 1 : 0;
}
u32 mac_read_pkt_ofld(struct mac_ax_adapter *adapter, u8 id)
{
u8 *buf;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_packet_ofld *write_ptr;
struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (id == PKT_OFLD_MAX_COUNT - 1)
return MACNOITEM;
if (mac_pkt_ofld_get_bitmap(ofld_info->id_bitmap, id) == 0)
return MACNOITEM;
if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_SENDING;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_packet_ofld *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(id, FWCMD_H2C_PACKET_OFLD_PKT_IDX) |
SET_WORD(PKT_OFLD_OP_READ, FWCMD_H2C_PACKET_OFLD_PKT_OP)
);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_PACKET_OFLD,
1, 1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE;
goto fail;
}
h2cb_free(adapter, h2cb);
ofld_info->last_op = PKT_OFLD_OP_READ;
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_del_pkt_ofld(struct mac_ax_adapter *adapter, u8 id)
{
u8 *buf;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_packet_ofld *write_ptr;
struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (id == PKT_OFLD_MAX_COUNT - 1)
return MACNOITEM;
if (mac_pkt_ofld_get_bitmap(ofld_info->id_bitmap, id) == 0)
return MACNOITEM;
if (ofld_info->used_id_count == 0)
return MACNOITEM;
if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_SENDING;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_packet_ofld *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(id, FWCMD_H2C_PACKET_OFLD_PKT_IDX) |
SET_WORD(PKT_OFLD_OP_DEL, FWCMD_H2C_PACKET_OFLD_PKT_OP)
);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_PACKET_OFLD,
1, 1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE;
goto fail;
}
h2cb_free(adapter, h2cb);
ofld_info->last_op = PKT_OFLD_OP_DEL;
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_add_pkt_ofld(struct mac_ax_adapter *adapter, u8 *pkt, u16 len, u8 *id)
{
u8 *buf;
u16 alloc_id;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_packet_ofld *write_ptr;
struct mac_ax_pkt_ofld_info *ofld_info = &adapter->pkt_ofld_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (ofld_info->free_id_count == 0)
return MACNOBUF;
if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_SENDING;
for (alloc_id = 0; alloc_id < PKT_OFLD_MAX_COUNT - 1; alloc_id++) {
if (mac_pkt_ofld_get_bitmap(ofld_info->id_bitmap,
alloc_id) == 0)
break;
}
PLTFM_MSG_TRACE("pkt ofld add. alloc_id: %d, free cnt: %d, use cnt: %d\n",
alloc_id, ofld_info->free_id_count,
ofld_info->used_id_count);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_packet_ofld *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD((u8)alloc_id, FWCMD_H2C_PACKET_OFLD_PKT_IDX) |
SET_WORD(PKT_OFLD_OP_ADD, FWCMD_H2C_PACKET_OFLD_PKT_OP) |
SET_WORD(len, FWCMD_H2C_PACKET_OFLD_PKT_LENGTH)
);
*id = (u8)alloc_id;
buf = h2cb_put(h2cb, len);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, pkt, len);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_PACKET_OFLD,
1, 1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE;
goto fail;
}
h2cb_free(adapter, h2cb);
ofld_info->last_op = PKT_OFLD_OP_ADD;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_pkt_ofld_packet(struct mac_ax_adapter *adapter,
u8 **pkt_buf, u16 *pkt_len, u8 *pkt_id)
{
struct mac_ax_pkt_ofld_pkt *pkt_info = &adapter->pkt_ofld_pkt;
*pkt_buf = NULL;
if (adapter->sm.pkt_ofld != MAC_AX_OFLD_H2C_DONE)
return MACPROCERR;
*pkt_buf = (u8 *)PLTFM_MALLOC(pkt_info->pkt_len);
if (!*pkt_buf)
return MACBUFALLOC;
PLTFM_MEMCPY(*pkt_buf, pkt_info->pkt, pkt_info->pkt_len);
*pkt_len = pkt_info->pkt_len;
*pkt_id = pkt_info->pkt_id;
adapter->sm.pkt_ofld = MAC_AX_OFLD_H2C_IDLE;
return MACSUCCESS;
}
u32 mac_dump_efuse_ofld(struct mac_ax_adapter *adapter, u32 efuse_size,
bool is_hidden)
{
u32 ret, size;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_efuse_ofld_info *ofld_info = &adapter->efuse_ofld_info;
u8 *buf;
struct fwcmd_dump_efuse *write_ptr;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (adapter->sm.efuse_ofld != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_SENDING;
size = efuse_size;
if (!ofld_info->buf) {
ofld_info->buf = (u8 *)PLTFM_MALLOC(size);
if (!ofld_info->buf)
return MACBUFALLOC;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_pkt_ofld_hdr));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_dump_efuse *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(efuse_size, FWCMD_H2C_DUMP_EFUSE_DUMP_SIZE) |
(is_hidden ? FWCMD_H2C_DUMP_EFUSE_IS_HIDDEN : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_DUMP_EFUSE,
0, 0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_efuse_ofld_map(struct mac_ax_adapter *adapter, u8 *efuse_map,
u32 efuse_size)
{
u32 size = efuse_size;
struct mac_ax_efuse_ofld_info *ofld_info = &adapter->efuse_ofld_info;
if (adapter->sm.efuse_ofld != MAC_AX_OFLD_H2C_DONE)
return MACPROCERR;
PLTFM_MEMCPY(efuse_map, ofld_info->buf, size);
adapter->sm.efuse_ofld = MAC_AX_OFLD_H2C_IDLE;
return MACSUCCESS;
}
static u32 cnv_read_ofld_state(struct mac_ax_adapter *adapter, u8 dest)
{
u8 state;
state = adapter->sm.read_request;
if (state > MAC_AX_OFLD_REQ_CLEANED)
return MACPROCERR;
if (dest == MAC_AX_OFLD_REQ_IDLE) {
if (state != MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_CLEANED) {
if (state == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_CREATED) {
if (state == MAC_AX_OFLD_REQ_IDLE ||
state == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
} else if (dest == MAC_AX_OFLD_REQ_H2C_SENT) {
if (state != MAC_AX_OFLD_REQ_CREATED)
return MACPROCERR;
}
adapter->sm.read_request = dest;
return MACSUCCESS;
}
u32 mac_clear_read_request(struct mac_ax_adapter *adapter)
{
if (adapter->sm.read_request == MAC_AX_OFLD_REQ_H2C_SENT)
return MACPROCERR;
if (cnv_read_ofld_state(adapter, MAC_AX_OFLD_REQ_CLEANED)
!= MACSUCCESS)
return MACPROCERR;
PLTFM_FREE(adapter->read_ofld_info.buf,
adapter->read_ofld_info.buf_size);
adapter->read_ofld_info.buf = NULL;
adapter->read_ofld_info.buf_wptr = NULL;
adapter->read_ofld_info.last_req = NULL;
adapter->read_ofld_info.buf_size = 0;
adapter->read_ofld_info.avl_buf_size = 0;
adapter->read_ofld_info.used_size = 0;
adapter->read_ofld_info.req_num = 0;
return MACSUCCESS;
}
u32 mac_add_read_request(struct mac_ax_adapter *adapter,
struct mac_ax_read_req *req)
{
struct mac_ax_read_ofld_info *ofld_info = &adapter->read_ofld_info;
struct fwcmd_read_ofld_req *write_ptr;
u8 state;
state = adapter->sm.read_request;
if (!(state == MAC_AX_OFLD_REQ_CREATED ||
state == MAC_AX_OFLD_REQ_CLEANED)) {
return MACPROCERR;
}
if (!ofld_info->buf) {
ofld_info->buf = (u8 *)PLTFM_MALLOC(READ_OFLD_MAX_LEN);
if (!ofld_info->buf)
return MACNPTR;
ofld_info->buf_wptr = ofld_info->buf;
ofld_info->buf_size = READ_OFLD_MAX_LEN;
ofld_info->avl_buf_size = READ_OFLD_MAX_LEN;
ofld_info->used_size = 0;
ofld_info->req_num = 0;
}
if (ofld_info->avl_buf_size < sizeof(struct mac_ax_read_req))
return MACNOBUF;
if (cnv_read_ofld_state(adapter, MAC_AX_OFLD_REQ_CREATED) != MACSUCCESS)
return MACPROCERR;
if (ofld_info->req_num != 0)
ofld_info->last_req->ls = 0;
ofld_info->last_req = (struct mac_ax_read_req *)ofld_info->buf_wptr;
req->ls = 1;
write_ptr = (struct fwcmd_read_ofld_req *)ofld_info->buf_wptr;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(req->value_len,
FWCMD_H2C_READ_OFLD_REQ_VALUE_LEN) |
SET_WORD(req->ofld_id,
FWCMD_H2C_READ_OFLD_REQ_OFLD_ID) |
SET_WORD(req->entry_num,
FWCMD_H2C_READ_OFLD_REQ_ENTRY_NUM) | req->ls
);
write_ptr->dword1 =
cpu_to_le32(SET_WORD(req->offset,
FWCMD_H2C_READ_OFLD_REQ_OFFSET)
);
ofld_info->buf_wptr += sizeof(struct mac_ax_read_req);
ofld_info->avl_buf_size -= sizeof(struct mac_ax_read_req);
ofld_info->used_size += sizeof(struct mac_ax_read_req);
ofld_info->req_num++;
return MACSUCCESS;
}
u32 mac_read_ofld(struct mac_ax_adapter *adapter)
{
u8 *buf;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_read_ofld_info *ofld_info = &adapter->read_ofld_info;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
if (ofld_info->used_size + FWCMD_HDR_LEN > READ_OFLD_MAX_LEN)
return MACBUFSZ;
if (adapter->sm.read_h2c != MAC_AX_OFLD_H2C_IDLE)
return MACPROCERR;
if (adapter->sm.read_request != MAC_AX_OFLD_REQ_CREATED)
return MACPROCERR;
if (cnv_read_ofld_state(adapter,
MAC_AX_OFLD_REQ_H2C_SENT) != MACSUCCESS)
return MACPROCERR;
adapter->sm.read_h2c = MAC_AX_OFLD_H2C_SENDING;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, ofld_info->used_size);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, ofld_info->buf, ofld_info->used_size);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_READ_OFLD,
1, 1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
adapter->sm.read_request = MAC_AX_OFLD_REQ_IDLE;
adapter->sm.read_h2c = MAC_AX_OFLD_H2C_IDLE;
goto fail;
}
h2cb_free(adapter, h2cb);
if (cnv_read_ofld_state(adapter, MAC_AX_OFLD_REQ_IDLE) != MACSUCCESS)
return MACPROCERR;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_read_ofld_value(struct mac_ax_adapter *adapter,
u8 **val_buf, u16 *val_len)
{
struct mac_ax_read_ofld_value *value_info = &adapter->read_ofld_value;
*val_buf = NULL;
if (adapter->sm.read_h2c != MAC_AX_OFLD_H2C_DONE)
return MACPROCERR;
*val_buf = (u8 *)PLTFM_MALLOC(value_info->len);
if (!*val_buf)
return MACBUFALLOC;
PLTFM_MEMCPY(*val_buf, value_info->buf, value_info->len);
*val_len = value_info->len;
adapter->sm.read_h2c = MAC_AX_OFLD_H2C_IDLE;
return MACSUCCESS;
}
u32 mac_general_pkt_ids(struct mac_ax_adapter *adapter,
struct mac_ax_general_pkt_ids *ids)
{
u8 *buf;
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_general_pkt *write_ptr;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_general_pkt_ids));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
write_ptr = (struct fwcmd_general_pkt *)buf;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(ids->macid, FWCMD_H2C_GENERAL_PKT_MACID) |
SET_WORD(ids->probersp, FWCMD_H2C_GENERAL_PKT_PROBRSP_ID) |
SET_WORD(ids->pspoll, FWCMD_H2C_GENERAL_PKT_PSPOLL_ID) |
SET_WORD(ids->nulldata, FWCMD_H2C_GENERAL_PKT_NULL_ID)
);
write_ptr->dword1 =
cpu_to_le32(SET_WORD(ids->qosnull, FWCMD_H2C_GENERAL_PKT_QOS_NULL_ID) |
SET_WORD(ids->cts2self, FWCMD_H2C_GENERAL_PKT_CTS2SELF_ID) |
SET_WORD(ids->probereq, FWCMD_H2C_GENERAL_PKT_PROBREQ_ID) |
SET_WORD(ids->apcsa, FWCMD_H2C_GENERAL_PKT_APCSA_ID)
);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_INFO,
FWCMD_H2C_FUNC_GENERAL_PKT,
1, 1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx: %d\n", ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static u32 add_cmd(struct mac_ax_adapter *adapter, struct rtw_mac_cmd *cmd)
{
struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info;
u16 total_len = CMD_OFLD_SIZE;
struct fwcmd_cmd_ofld *write_ptr;
if (!ofld_info->buf) {
ofld_info->buf = (u8 *)PLTFM_MALLOC(CMD_OFLD_MAX_LEN);
if (!ofld_info->buf)
return MACBUFALLOC;
ofld_info->buf_wptr = ofld_info->buf;
ofld_info->last_wptr = NULL;
ofld_info->buf_size = CMD_OFLD_MAX_LEN;
ofld_info->avl_buf_size = CMD_OFLD_MAX_LEN;
ofld_info->used_size = 0;
ofld_info->cmd_num = 0;
ofld_info->accu_delay = 0;
}
write_ptr = (struct fwcmd_cmd_ofld *)ofld_info->buf_wptr;
write_ptr->dword0 =
cpu_to_le32(SET_WORD(cmd->src, FWCMD_H2C_CMD_OFLD_SRC) |
SET_WORD(cmd->type, FWCMD_H2C_CMD_OFLD_TYPE) |
(cmd->lc ? FWCMD_H2C_CMD_OFLD_LC : 0) |
SET_WORD(cmd->rf_path, FWCMD_H2C_CMD_OFLD_PATH) |
SET_WORD(cmd->offset, FWCMD_H2C_CMD_OFLD_OFFSET) |
SET_WORD(ofld_info->cmd_num, FWCMD_H2C_CMD_OFLD_CMD_NUM)
);
write_ptr->dword1 =
cpu_to_le32(SET_WORD(cmd->id, FWCMD_H2C_CMD_OFLD_ID));
write_ptr->dword2 =
cpu_to_le32(SET_WORD(cmd->value, FWCMD_H2C_CMD_OFLD_VALUE));
write_ptr->dword3 =
cpu_to_le32(SET_WORD(cmd->mask, FWCMD_H2C_CMD_OFLD_MASK));
ofld_info->last_wptr = ofld_info->buf_wptr;
ofld_info->buf_wptr += total_len;
ofld_info->avl_buf_size -= total_len;
ofld_info->used_size += total_len;
ofld_info->cmd_num++;
if (cmd->type == RTW_MAC_DELAY_OFLD)
ofld_info->accu_delay += cmd->value;
return MACSUCCESS;
}
static u32 chk_cmd_ofld_reg(struct mac_ax_adapter *adapter)
{
#define MAC_AX_CMD_OFLD_POLL_CNT 1000
#define MAC_AX_CMD_OFLD_POLL_US 50
struct mac_ax_c2hreg_poll c2h;
struct fwcmd_c2hreg *c2h_content;
u32 ret, result, i, cmd_num;
struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info;
u8 *cmd;
c2h.polling_id = FWCMD_C2HREG_FUNC_IO_OFLD_RESULT;
c2h.retry_cnt = MAC_AX_CMD_OFLD_POLL_CNT;
c2h.retry_wait_us = MAC_AX_CMD_OFLD_POLL_US;
ret = proc_msg_reg(adapter, NULL, &c2h);
if (ret) {
PLTFM_MSG_ERR("%s: fail to wait FW done(%d)\n", __func__, ret);
return ret;
}
c2h_content = &c2h.c2hreg_cont.c2h_content;
result = GET_FIELD(c2h_content->dword0,
FWCMD_C2HREG_IO_OFLD_RESULT_RET);
if (result) {
cmd_num = GET_FIELD(c2h_content->dword0,
FWCMD_C2HREG_IO_OFLD_RESULT_CMD_NUM);
cmd = ofld_info->buf + cmd_num * CMD_OFLD_SIZE;
PLTFM_MSG_ERR("%s: fail to finish IO offload\n", __func__);
PLTFM_MSG_ERR("fail offset = %x\n", c2h_content->dword1);
PLTFM_MSG_ERR("exp val = %x\n", c2h_content->dword2);
PLTFM_MSG_ERR("read val = %x\n", c2h_content->dword3);
PLTFM_MSG_ERR("fail cmd num = %d\n", cmd_num);
for (i = 0; i < CMD_OFLD_SIZE; i += 4)
PLTFM_MSG_ERR("%x\n", *((u32 *)(cmd + i)));
return MACFIOOFLD;
}
return MACSUCCESS;
}
static u32 chk_cmd_ofld_pkt(struct mac_ax_adapter *adapter)
{
u32 cnt = MAC_AX_CMD_OFLD_POLL_CNT;
struct mac_ax_state_mach *sm = &adapter->sm;
struct mac_ax_drv_stats *drv_stats = &adapter->drv_stats;
struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info;
while (--cnt) {
if (sm->cmd_state == MAC_AX_CMD_OFLD_RCVD)
break;
if (drv_stats->drv_rm)
return MACDRVRM;
PLTFM_DELAY_US(MAC_AX_CMD_OFLD_POLL_US);
}
PLTFM_MSG_TRACE("%s: cnt = %d, us = %d\n",
__func__, cnt, MAC_AX_CMD_OFLD_POLL_US);
if (!cnt) {
PLTFM_MSG_ERR("%s: polling timeout\n", __func__);
return MACPOLLTO;
}
if (ofld_info->result) {
PLTFM_MSG_ERR("%s: ofld FAIL!!!\n", __func__);
return MACFIOOFLD;
}
return MACSUCCESS;
}
static u32 chk_cmd_ofld(struct mac_ax_adapter *adapter, u8 rx_ok)
{
u32 ret;
if (rx_ok)
ret = chk_cmd_ofld_pkt(adapter);
else
ret = chk_cmd_ofld_reg(adapter);
return ret;
}
static u32 cmd_ofld(struct mac_ax_adapter *adapter)
{
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info;
u8 *buffer;
u8 func;
u8 rx_ok = adapter->drv_stats.rx_ok;
struct mac_ax_state_mach *sm = &adapter->sm;
PLTFM_MSG_TRACE("%s===>\n", __func__);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!h2cb)
return MACNPTR;
buffer = h2cb_put(h2cb, ofld_info->used_size);
if (!buffer) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buffer, ofld_info->buf, ofld_info->used_size);
func = rx_ok ? FWCMD_H2C_FUNC_CMD_OFLD_PKT :
FWCMD_H2C_FUNC_CMD_OFLD_REG;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, func,
0, 0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
goto fail;
}
if (ofld_info->accu_delay)
PLTFM_DELAY_US(ofld_info->accu_delay);
sm->cmd_state = MAC_AX_CMD_OFLD_SENDING;
ret = chk_cmd_ofld(adapter, rx_ok);
if (ret) {
PLTFM_MSG_ERR("%s: check IO offload fail\n", __func__);
goto fail;
}
h2cb_free(adapter, h2cb);
PLTFM_FREE(ofld_info->buf, CMD_OFLD_MAX_LEN);
ofld_info->buf = NULL;
PLTFM_MSG_TRACE("%s<===\n", __func__);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
PLTFM_FREE(ofld_info->buf, CMD_OFLD_MAX_LEN);
ofld_info->buf = NULL;
return ret;
}
u32 mac_add_cmd_ofld(struct mac_ax_adapter *adapter, struct rtw_mac_cmd *cmd)
{
struct mac_ax_cmd_ofld_info *ofld_info = &adapter->cmd_ofld_info;
struct mac_ax_state_mach *sm = &adapter->sm;
u32 ret = MACSUCCESS;
if (cmd->type != RTW_MAC_DELAY_OFLD &&
cmd->src != RTW_MAC_RF_CMD_OFLD && cmd->offset & (4 - 1))
return MACBADDR;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
PLTFM_MUTEX_LOCK(&ofld_info->cmd_ofld_lock);
if (sm->cmd_state != MAC_AX_CMD_OFLD_IDLE) {
PLTFM_MSG_ERR("%s: IO offload is busy\n", __func__);
PLTFM_MUTEX_UNLOCK(&ofld_info->cmd_ofld_lock);
return MACPROCERR;
}
sm->cmd_state = MAC_AX_CMD_OFLD_PROC;
PLTFM_MUTEX_UNLOCK(&ofld_info->cmd_ofld_lock);
if (ofld_info->buf &&
ofld_info->avl_buf_size < CMD_OFLD_SIZE) {
if (!ofld_info->last_wptr) {
ret = MACNPTR;
PLTFM_MSG_ERR("%s: wrong pointer\n", __func__);
goto END;
}
*ofld_info->last_wptr = *ofld_info->last_wptr |
FWCMD_H2C_CMD_OFLD_LC;
ret = cmd_ofld(adapter);
if (ret) {
PLTFM_MSG_ERR("%s: send IO offload fail\n", __func__);
goto END;
}
}
ret = add_cmd(adapter, cmd);
if (ret)
goto END;
if (!cmd->lc)
goto END;
ret = cmd_ofld(adapter);
END:
PLTFM_MUTEX_LOCK(&ofld_info->cmd_ofld_lock);
sm->cmd_state = MAC_AX_CMD_OFLD_IDLE;
PLTFM_MUTEX_UNLOCK(&ofld_info->cmd_ofld_lock);
return ret;
}
u32 write_mac_reg_ofld(struct mac_ax_adapter *adapter,
u16 offset, u32 mask, u32 val, u8 lc)
{
struct rtw_mac_cmd cmd = {RTW_MAC_MAC_CMD_OFLD, RTW_MAC_WRITE_OFLD,
0, RTW_MAC_RF_PATH_A, 0, 0, 0, 0};
cmd.offset = offset;
cmd.mask = mask;
cmd.value = val;
cmd.lc = lc;
return mac_add_cmd_ofld(adapter, &cmd);
}
u32 poll_mac_reg_ofld(struct mac_ax_adapter *adapter,
u16 offset, u32 mask, u32 val, u8 lc)
{
struct rtw_mac_cmd cmd = {RTW_MAC_MAC_CMD_OFLD, RTW_MAC_COMPARE_OFLD,
0, RTW_MAC_RF_PATH_A, 0, 0, 0, 0};
cmd.offset = offset;
cmd.mask = mask;
cmd.value = val;
cmd.lc = lc;
return mac_add_cmd_ofld(adapter, &cmd);
}
u32 delay_ofld(struct mac_ax_adapter *adapter,
u32 val)
{
struct rtw_mac_cmd cmd = {RTW_MAC_MAC_CMD_OFLD, RTW_MAC_DELAY_OFLD,
0, RTW_MAC_RF_PATH_A, 0, 0, 0, 0};
cmd.value = val;
return mac_add_cmd_ofld(adapter, &cmd);
}
u32 mac_ccxrpt_parsing(struct mac_ax_adapter *adapter, u8 *buf, struct mac_ax_ccxrpt *info)
{
u32 val_d0;
u32 val_d3;
u32 dword0 = *((u32 *)buf);
u32 dword3 = *((u32 *)(buf + 12));
val_d0 = le32_to_cpu(dword0);
val_d3 = le32_to_cpu(dword3);
info->tx_state = GET_FIELD(val_d0, TXCCXRPT_TX_STATE);
info->sw_define = GET_FIELD(val_d0, TXCCXRPT_SW_DEFINE);
info->macid = GET_FIELD(val_d0, TXCCXRPT_MACID);
info->pkt_ok_num = GET_FIELD(val_d3, TXCCXRPT_PKT_OK_NUM);
info->data_txcnt = GET_FIELD(val_d3, TXCCXRPT_DATA_TX_CNT);
return MACSUCCESS;
}
u32 get_ccxrpt_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id, u8 *c2h_info)
{
struct mac_ax_ccxrpt *info;
u32 val_d0, val_d3;
u32 dword0 = *((u32 *)c2h->content);
u32 dword3 = *((u32 *)(c2h->content + 12));
info = (struct mac_ax_ccxrpt *)c2h_info;
val_d0 = le32_to_cpu(dword0);
val_d3 = le32_to_cpu(dword3);
info->tx_state = GET_FIELD(val_d0, TXCCXRPT_TX_STATE);
info->sw_define = GET_FIELD(val_d0, TXCCXRPT_SW_DEFINE);
info->macid = GET_FIELD(val_d0, TXCCXRPT_MACID);
info->pkt_ok_num = GET_FIELD(val_d3, TXCCXRPT_PKT_OK_NUM);
info->data_txcnt = GET_FIELD(val_d3, TXCCXRPT_DATA_TX_CNT);
if (info->tx_state)
*id = MSG_EVT_CCX_REPORT_TX_FAIL;
else
*id = MSG_EVT_CCX_REPORT_TX_OK;
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwofld.c
|
C
|
agpl-3.0
| 37,594
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_FW_OFLD_H_
#define _MAC_AX_FW_OFLD_H_
#include "../type.h"
#include "fwcmd.h"
#include "fwofld.h"
#include "trx_desc.h"
#define READ_OFLD_MAX_LEN 2000
#define WRITE_OFLD_MAX_LEN 2000
#define CONF_OFLD_MAX_LEN 2000
#define CMD_OFLD_MAX_LEN 2000
#define CONF_OFLD_RESTORE 0
#define CONF_OFLD_BACKUP 1
#define CMD_OFLD_SIZE sizeof(struct fwcmd_cmd_ofld)
/* Generate 8-bit mask for a 4-byte alignment offset */
#define GET_W8_MSK(offset) \
(0xFF << ((offset) & 0x3 ? (8 * ((offset) & 0x3)) : 0))
/* Generate 16-bit mask for a 4-byte alignment offset */
#define GET_W16_MSK(offset) \
(0xFFFF << ((offset) & 0x2 ? 16 : 0))
#define MAC_REG_W8_OFLD(offset, val, lc) \
write_mac_reg_ofld(adapter, offset & 0xFFFC, GET_W8_MSK(offset), val, lc)
#define MAC_REG_W16_OFLD(offset, val, lc) \
write_mac_reg_ofld(adapter, offset & 0xFFFD, GET_W16_MSK(offset), val, lc)
#define MAC_REG_W32_OFLD(offset, val, lc) \
write_mac_reg_ofld(adapter, offset, 0xFFFFFFFF, val, lc)
#define MAC_REG_W_OFLD(offset, mask, val, lc) \
write_mac_reg_ofld(adapter, offset, mask, val, lc)
#define MAC_REG_P_OFLD(offset, mask, val, lc) \
poll_mac_reg_ofld(adapter, offset, mask, val, lc)
#define DELAY_OFLD(val, lc) \
poll_mac_reg_ofld(adapter, val, lc)
/**
* @enum PKT_OFLD_OP
*
* @brief PKT_OFLD_OP
*
* @var PKT_OFLD_OP::PKT_OFLD_OP_ADD
* Please Place Description here.
* @var PKT_OFLD_OP::PKT_OFLD_OP_DEL
* Please Place Description here.
* @var PKT_OFLD_OP::PKT_OFLD_OP_READ
* Please Place Description here.
* @var PKT_OFLD_OP::PKT_OFLD_OP_MAX
* Please Place Description here.
*/
enum PKT_OFLD_OP {
PKT_OFLD_OP_ADD = 0,
PKT_OFLD_OP_DEL = 1,
PKT_OFLD_OP_READ = 2,
PKT_OFLD_OP_MAX
};
/**
* @enum FW_OFLD_OP
*
* @brief FW_OFLD_OP
*
* @var FW_OFLD_OP::FW_OFLD_OP_DUMP_EFUSE
* Please Place Description here.
* @var FW_OFLD_OP::FW_OFLD_OP_PACKET_OFLD
* Please Place Description here.
* @var FW_OFLD_OP::FW_OFLD_OP_READ_OFLD
* Please Place Description here.
* @var FW_OFLD_OP::FW_OFLD_OP_WRITE_OFLD
* Please Place Description here.
* @var FW_OFLD_OP::FW_OFLD_OP_CONF_OFLD
* Please Place Description here.
* @var FW_OFLD_OP::FW_OFLD_OP_MAX
* Please Place Description here.
*/
enum FW_OFLD_OP {
FW_OFLD_OP_DUMP_EFUSE = 0,
FW_OFLD_OP_PACKET_OFLD = 1,
FW_OFLD_OP_READ_OFLD = 2,
FW_OFLD_OP_WRITE_OFLD = 3,
FW_OFLD_OP_CONF_OFLD = 4,
FW_OFLD_OP_MAX
};
/**
* @struct mac_ax_conf_ofld_hdr
* @brief mac_ax_conf_ofld_hdr
*
* @var mac_ax_conf_ofld_hdr::pattern_count
* Please Place Description here.
* @var mac_ax_conf_ofld_hdr::rsvd
* Please Place Description here.
*/
struct mac_ax_conf_ofld_hdr {
u16 pattern_count;
u16 rsvd;
};
/**
* @struct mac_ax_pkt_ofld_hdr
* @brief mac_ax_pkt_ofld_hdr
*
* @var mac_ax_pkt_ofld_hdr::pkt_idx
* Please Place Description here.
* @var mac_ax_pkt_ofld_hdr::pkt_op
* Please Place Description here.
* @var mac_ax_pkt_ofld_hdr::rsvd
* Please Place Description here.
* @var mac_ax_pkt_ofld_hdr::pkt_len
* Please Place Description here.
*/
struct mac_ax_pkt_ofld_hdr {
u8 pkt_idx;
u8 pkt_op:3;
u8 rsvd:5;
u16 pkt_len;
};
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_reset_fwofld_state
*
* @param *adapter
* @param op
* @return Please Place Description here.
* @retval u32
*/
u32 mac_reset_fwofld_state(struct mac_ax_adapter *adapter, u8 op);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_check_fwofld_done
*
* @param *adapter
* @param op
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_fwofld_done(struct mac_ax_adapter *adapter, u8 op);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_clear_write_request
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_clear_write_request(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_add_write_request
*
* @param *adapter
* @param *req
* @param *value
* @param *mask
* @return Please Place Description here.
* @retval u32
*/
u32 mac_add_write_request(struct mac_ax_adapter *adapter,
struct mac_ax_write_req *req,
u8 *value, u8 *mask);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_write_ofld
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_ofld(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_clear_conf_request
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_clear_conf_request(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_add_conf_request
*
* @param *adapter
* @param *req
* @return Please Place Description here.
* @retval u32
*/
u32 mac_add_conf_request(struct mac_ax_adapter *adapter,
struct mac_ax_conf_ofld_req *req);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_conf_ofld
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_conf_ofld(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_read_pkt_ofld
*
* @param *adapter
* @param id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_pkt_ofld(struct mac_ax_adapter *adapter, u8 id);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_del_pkt_ofld
*
* @param *adapter
* @param id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_del_pkt_ofld(struct mac_ax_adapter *adapter, u8 id);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_add_pkt_ofld
*
* @param *adapter
* @param *pkt
* @param len
* @param *id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_add_pkt_ofld(struct mac_ax_adapter *adapter, u8 *pkt, u16 len, u8 *id);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_pkt_ofld_packet
*
* @param *adapter
* @param **pkt_buf
* @param *pkt_len
* @param *pkt_id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pkt_ofld_packet(struct mac_ax_adapter *adapter,
u8 **pkt_buf, u16 *pkt_len, u8 *pkt_id);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_dump_efuse_ofld
*
* @param *adapter
* @param efuse_size
* @param is_hidden
* @return Please Place Description here.
* @retval u32
*/
u32 mac_dump_efuse_ofld(struct mac_ax_adapter *adapter, u32 efuse_size,
bool is_hidden);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_efuse_ofld_map
*
* @param *adapter
* @param *efuse_map
* @param efuse_size
* @return Please Place Description here.
* @retval u32
*/
u32 mac_efuse_ofld_map(struct mac_ax_adapter *adapter, u8 *efuse_map,
u32 efuse_size);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_clear_read_request
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_clear_read_request(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_add_read_request
*
* @param *adapter
* @param *req
* @return Please Place Description here.
* @retval u32
*/
u32 mac_add_read_request(struct mac_ax_adapter *adapter,
struct mac_ax_read_req *req);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_read_ofld
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_ofld(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_read_ofld_value
*
* @param *adapter
* @param **val_buf
* @param *val_len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_ofld_value(struct mac_ax_adapter *adapter,
u8 **val_buf, u16 *val_len);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_general_pkt_ids
*
* @param *adapter
* @param *ids
* @return Please Place Description here.
* @retval u32
*/
u32 mac_general_pkt_ids(struct mac_ax_adapter *adapter,
struct mac_ax_general_pkt_ids *ids);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_add_cmd_ofld
*
* This is the function for FW IO offload.
* Users could call the function to add write BB/RF/MAC REG command.
* When the aggregated commands are full or the command is last,
* FW would receive a H2C containing aggreated IO command.
*
* @param *adapter
* @param *cmd
* @return 0 for success. Others are fail.
* @retval u32
*/
u32 mac_add_cmd_ofld(struct mac_ax_adapter *adapter, struct rtw_mac_cmd *cmd);
/**
* @}
* @}
*/
/**
* @addtogroup Firmware
* @{
* @addtogroup FW_Offload
* @{
*/
/**
* @brief mac_get_fw_cap
*
* @param *adapter
* @param *val
* @return This function would set FW capability in *val.
* return fail while FW is NOT ready
* @retval u32
*/
u32 mac_get_fw_cap(struct mac_ax_adapter *adapter, u32 *val);
/**
* @}
* @}
*/
u32 write_mac_reg_ofld(struct mac_ax_adapter *adapter,
u16 offset, u32 mask, u32 val, u8 lc);
u32 poll_mac_reg_ofld(struct mac_ax_adapter *adapter,
u16 offset, u32 mask, u32 val, u8 lc);
u32 delay_ofld(struct mac_ax_adapter *adapter, u32 val);
/**
* @brief mac_ccxrpt_parsing
*
* @param *adapter
* @param *buf
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ccxrpt_parsing(struct mac_ax_adapter *adapter,
u8 *buf, struct mac_ax_ccxrpt *info);
u32 get_ccxrpt_event(struct mac_ax_adapter *adapter,
struct rtw_c2h_info *c2h,
enum phl_msg_evt_id *id, u8 *c2h_info);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/fwofld.h
|
C
|
agpl-3.0
| 11,100
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "gpio.h"
u32 mac_sel_uart_tx_pin(struct mac_ax_adapter *adapter,
enum mac_ax_uart_tx_pin uart_pin)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
struct mac_ax_gpio_info *info = &adapter->gpio_info;
u8 val = MAC_REG_R8(R_AX_CAL_TIMER + 3);
u32 ret = MACSUCCESS;
switch (uart_pin) {
case MAC_AX_UART_TX_GPIO5:
val |= BIT(6);
if (!info->uart_tx_gpio5)
PLTFM_MSG_WARN("Pinmux function is not switched\n");
break;
case MAC_AX_UART_TX_GPIO7:
val &= ~(BIT(7) | BIT(6));
if (!info->uart_tx_gpio7)
PLTFM_MSG_WARN("Pinmux function is not switched\n");
break;
case MAC_AX_UART_TX_GPIO8:
val |= BIT(7);
if (!info->uart_tx_gpio8)
PLTFM_MSG_WARN("Pinmux function is not switched\n");
break;
case MAC_AX_UART_TX_GPIO5_GPIO8:
val |= (BIT(6) | BIT(7));
if (!info->uart_tx_gpio8 || !info->uart_tx_gpio5)
PLTFM_MSG_WARN("Pinmux function is not switched\n");
break;
default:
PLTFM_MSG_ERR("Wrong UART GPIO\n");
ret = MACNOITEM;
break;
}
MAC_REG_W8(R_AX_CAL_TIMER + 3, val);
return ret;
}
u32 mac_sel_uart_rx_pin(struct mac_ax_adapter *adapter,
enum mac_ax_uart_rx_pin uart_pin)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
struct mac_ax_gpio_info *info = &adapter->gpio_info;
u8 val = MAC_REG_R8(R_AX_CAL_TIMER + 3);
u32 ret = MACSUCCESS;
switch (uart_pin) {
case MAC_AX_UART_RX_GPIO6:
val &= ~BIT(5);
if (!info->uart_rx_gpio6)
PLTFM_MSG_WARN("Pinmux function is not switched\n");
break;
case MAC_AX_UART_RX_GPIO14:
val |= BIT(5);
if (!info->uart_rx_gpio14)
PLTFM_MSG_WARN("Pinmux function is not switched\n");
break;
default:
PLTFM_MSG_ERR("Wrong UART GPIO\n");
ret = MACNOITEM;
break;
}
MAC_REG_W8(R_AX_CAL_TIMER + 3, val);
return ret;
}
u32 mac_pinmux_switch(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func gpio_func,
const struct mac_ax_pinmux_list *list,
u32 list_size, u32 gpio_id)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
enum pinmux_name pinmux;
struct mac_ax_pinmux_list const *cur_list;
u32 i;
u8 val;
switch (gpio_func) {
case MAC_AX_GPIO_SW_IO_0:
case MAC_AX_GPIO_SW_IO_1:
case MAC_AX_GPIO_SW_IO_2:
case MAC_AX_GPIO_SW_IO_3:
case MAC_AX_GPIO_SW_IO_4:
case MAC_AX_GPIO_SW_IO_5:
case MAC_AX_GPIO_SW_IO_6:
case MAC_AX_GPIO_SW_IO_7:
case MAC_AX_GPIO_SW_IO_8:
case MAC_AX_GPIO_SW_IO_9:
case MAC_AX_GPIO_SW_IO_10:
case MAC_AX_GPIO_SW_IO_11:
case MAC_AX_GPIO_SW_IO_12:
case MAC_AX_GPIO_SW_IO_13:
case MAC_AX_GPIO_SW_IO_14:
case MAC_AX_GPIO_SW_IO_15:
pinmux = MAC_AX_SW_IO;
break;
case MAC_AX_GPIO_UART_TX_GPIO5:
case MAC_AX_GPIO_UART_TX_GPIO7:
case MAC_AX_GPIO_UART_TX_GPIO8:
pinmux = MAC_AX_WL_UART_TX;
break;
case MAC_AX_GPIO_UART_RX_GPIO6:
case MAC_AX_GPIO_UART_RX_GPIO14:
pinmux = MAC_AX_WL_UART_RX;
break;
default:
PLTFM_MSG_ERR("Wrong GPIO function\n");
return MACNOITEM;
}
cur_list = list;
for (i = 0; i < list_size; i++) {
val = MAC_REG_R8(cur_list->offset);
val &= ~(cur_list->msk);
if (pinmux == cur_list->func) {
val |= (cur_list->value & cur_list->msk);
MAC_REG_W8(cur_list->offset, val);
break;
}
val |= (~cur_list->value & cur_list->msk);
MAC_REG_W8(cur_list->offset, val);
cur_list++;
}
if (i == list_size) {
PLTFM_MSG_ERR("Get pinmux function error\n");
return MACNOITEM;
}
switch (pinmux) {
case MAC_AX_WL_UART_TX:
case MAC_AX_WL_UART_RX:
val = MAC_REG_R8(R_AX_WCPU_FW_CTRL + 3);
MAC_REG_W8(R_AX_WCPU_FW_CTRL + 3, val | BIT(7));
break;
default:
break;
}
return MACSUCCESS;
}
u32 mac_pinmux_record(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func, u8 val)
{
struct mac_ax_gpio_info *info = &adapter->gpio_info;
switch (func) {
case MAC_AX_GPIO_SW_IO_0:
info->sw_io_0 = val;
break;
case MAC_AX_GPIO_SW_IO_1:
info->sw_io_1 = val;
break;
case MAC_AX_GPIO_SW_IO_2:
info->sw_io_2 = val;
break;
case MAC_AX_GPIO_SW_IO_3:
info->sw_io_3 = val;
break;
case MAC_AX_GPIO_SW_IO_4:
info->sw_io_4 = val;
break;
case MAC_AX_GPIO_SW_IO_5:
info->sw_io_5 = val;
break;
case MAC_AX_GPIO_SW_IO_6:
info->sw_io_6 = val;
break;
case MAC_AX_GPIO_SW_IO_7:
info->sw_io_7 = val;
break;
case MAC_AX_GPIO_SW_IO_8:
info->sw_io_8 = val;
break;
case MAC_AX_GPIO_SW_IO_9:
info->sw_io_9 = val;
break;
case MAC_AX_GPIO_SW_IO_10:
info->sw_io_10 = val;
break;
case MAC_AX_GPIO_SW_IO_11:
info->sw_io_11 = val;
break;
case MAC_AX_GPIO_SW_IO_12:
info->sw_io_12 = val;
break;
case MAC_AX_GPIO_SW_IO_13:
info->sw_io_13 = val;
break;
case MAC_AX_GPIO_SW_IO_14:
info->sw_io_14 = val;
break;
case MAC_AX_GPIO_SW_IO_15:
info->sw_io_15 = val;
break;
case MAC_AX_GPIO_UART_TX_GPIO5:
info->uart_tx_gpio5 = val;
break;
case MAC_AX_GPIO_UART_TX_GPIO7:
info->uart_tx_gpio7 = val;
break;
case MAC_AX_GPIO_UART_TX_GPIO8:
info->uart_tx_gpio8 = val;
break;
case MAC_AX_GPIO_UART_RX_GPIO6:
info->uart_rx_gpio6 = val;
break;
case MAC_AX_GPIO_UART_RX_GPIO14:
info->uart_rx_gpio14 = val;
break;
default:
PLTFM_MSG_ERR("Wrong GPIO function\n");
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_pinmux_status(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func)
{
struct mac_ax_gpio_info *info = &adapter->gpio_info;
u32 ret = MACSUCCESS;
switch (func) {
case MAC_AX_GPIO_SW_IO_0:
if (info->sw_io_0)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_1:
if (info->sw_io_1)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_2:
if (info->sw_io_2)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_3:
if (info->sw_io_3)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_4:
if (info->sw_io_4)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_5:
if (info->sw_io_5 || info->uart_tx_gpio5 ||
info->uart_tx_gpio7 || info->uart_tx_gpio8)
goto GPIO_USED;
break;
case MAC_AX_GPIO_UART_TX_GPIO5:
if (info->sw_io_5 || info->uart_tx_gpio5)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_6:
if (info->sw_io_6 || info->uart_rx_gpio6 ||
info->uart_rx_gpio14)
goto GPIO_USED;
break;
case MAC_AX_GPIO_UART_RX_GPIO6:
if (info->sw_io_6 || info->uart_rx_gpio6)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_7:
if (info->sw_io_7 || info->uart_tx_gpio5 ||
info->uart_tx_gpio7 || info->uart_tx_gpio8)
goto GPIO_USED;
break;
case MAC_AX_GPIO_UART_TX_GPIO7:
if (info->sw_io_7 || info->uart_tx_gpio7)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_8:
if (info->sw_io_8 || info->uart_tx_gpio5 ||
info->uart_tx_gpio7 || info->uart_tx_gpio8)
goto GPIO_USED;
break;
case MAC_AX_GPIO_UART_TX_GPIO8:
if (info->sw_io_8 || info->uart_tx_gpio8)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_9:
if (info->sw_io_9)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_10:
if (info->sw_io_10)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_11:
if (info->sw_io_11)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_12:
if (info->sw_io_12)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_13:
if (info->sw_io_13)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_14:
if (info->sw_io_14 || info->uart_rx_gpio6 ||
info->uart_rx_gpio14)
goto GPIO_USED;
break;
case MAC_AX_GPIO_UART_RX_GPIO14:
if (info->sw_io_14 || info->uart_rx_gpio14)
goto GPIO_USED;
break;
case MAC_AX_GPIO_SW_IO_15:
if (info->sw_io_15)
goto GPIO_USED;
break;
default:
ret = MACNOITEM;
PLTFM_MSG_ERR("Wrong GPIO function\n");
}
return ret;
GPIO_USED:
ret = MACGPIOUSED;
return ret;
}
u32 mac_pinmux_free_func(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func)
{
return mac_pinmux_record(adapter, func, 0);
}
u8 get_led_gpio(u8 led_id)
{
/* LED 0 -> GPIO8 */
switch (led_id) {
case 0:
return 8;
default:
return 0xFF;
}
}
u32 mac_set_led_mode(struct mac_ax_adapter *adapter,
enum mac_ax_led_mode mode, u8 led_id)
{
#define LED_MODE_SW_CTRL 0
#define LED_MODE_AON 1
#define LED_MODE_TRX_ON 2
#define LED_MODE_TRX_OFF 3
#define LED_MODE_TX_ON 4
#define LED_MODE_TX_OFF 5
#define LED_MODE_RX_ON 6
#define LED_MODE_RX_OFF 7
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
struct mac_ax_ops *mac_ops = adapter->ops;
u32 val, ret;
u8 tmp, gpio;
gpio = get_led_gpio(led_id);
if (gpio == 0xFF) {
PLTFM_MSG_ERR("%s: Wrong LED ID: %d", __func__, led_id);
ret = MACNOITEM;
goto END;
}
val = MAC_REG_R32(R_AX_LED_CFG);
switch (mode) {
case MAC_AX_LED_MODE_TRX_ON:
tmp = LED_MODE_TRX_ON;
break;
case MAC_AX_LED_MODE_TX_ON:
tmp = LED_MODE_TX_ON;
break;
case MAC_AX_LED_MODE_RX_ON:
tmp = LED_MODE_RX_ON;
break;
case MAC_AX_LED_MODE_SW_CTRL_OD:
/* use SW IO to control LED */
ret = mac_set_sw_gpio_mode(adapter,
MAC_AX_SW_IO_MODE_OUTPUT_OD, 8);
if (ret)
PLTFM_MSG_ERR("%s: config SW GPIO fail: %d",
__func__, ret);
goto END;
case MAC_AX_LED_MODE_SW_CTRL_PP:
/* use SW IO to control LED */
ret = mac_set_sw_gpio_mode(adapter,
MAC_AX_SW_IO_MODE_OUTPUT_PP, 8);
if (ret)
PLTFM_MSG_ERR("%s: config SW GPIO fail: %d",
__func__, ret);
goto END;
default:
PLTFM_MSG_ERR("%s: Wrong LED mode: %d", __func__, mode);
return MACNOITEM;
}
ret = mac_ops->set_gpio_func(adapter, RTW_MAC_GPIO_WL_LED, gpio);
if (ret) {
PLTFM_MSG_ERR("%s: Config LED pinmux fail", __func__);
goto END;
}
val = SET_CLR_WORD(val, tmp, B_AX_LED2CM);
val = val & ~(B_AX_GPIO13_14_WL_CTRL_EN);
MAC_REG_W32(R_AX_LED_CFG, val);
END:
return ret;
}
u32 mac_led_ctrl(struct mac_ax_adapter *adapter,
u8 high, u8 led_id)
{
u32 ret = MACSUCCESS;
u8 gpio;
gpio = get_led_gpio(led_id);
if (gpio == 0xFF) {
PLTFM_MSG_ERR("%s: Wrong LED ID: %d", __func__, led_id);
ret = MACNOITEM;
goto END;
}
/* use SW IO to control LED */
ret = mac_sw_gpio_ctrl(adapter, high, gpio);
END:
return ret;
}
u32 _mac_set_sw_gpio_mode(struct mac_ax_adapter *adapter,
u8 output, u8 gpio)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
u32 reg;
u16 val16;
u8 in_out;
if (gpio <= 7) {
reg = R_AX_GPIO_PIN_CTRL + 2;
} else if (gpio >= 8 && gpio <= 15) {
reg = R_AX_GPIO_EXT_CTRL + 2;
gpio = gpio - 8;
} else {
PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, gpio);
return MACNOITEM;
}
in_out = (output == 0) ? 0 : 1;
val16 = MAC_REG_R16(reg);
val16 = (val16 & ~((u16)BIT(gpio) | (u16)BIT(gpio + 8))) |
(u16)(in_out << gpio) | (u16)(in_out << gpio << 8);
MAC_REG_W16(reg, val16);
return MACSUCCESS;
}
u32 mac_set_sw_gpio_mode(struct mac_ax_adapter *adapter,
enum mac_ax_sw_io_mode mode, u8 gpio)
{
struct mac_ax_ops *mac_ops = adapter->ops;
struct mac_ax_gpio_info *gpio_info = &adapter->gpio_info;
u32 ret;
ret = mac_ops->set_gpio_func(adapter, RTW_MAC_GPIO_SW_IO, gpio);
if (ret) {
PLTFM_MSG_ERR("%s: Config SW IO pinmux fail", __func__);
return ret;
}
switch (mode) {
case MAC_AX_SW_IO_MODE_INPUT:
ret = _mac_set_sw_gpio_mode(adapter, 0, gpio);
break;
case MAC_AX_SW_IO_MODE_OUTPUT_OD:
ret = _mac_set_sw_gpio_mode(adapter, 0, gpio);
gpio_info->sw_io_output[gpio] = MAC_AX_SW_IO_OUT_OD;
break;
case MAC_AX_SW_IO_MODE_OUTPUT_PP:
ret = _mac_set_sw_gpio_mode(adapter, 1, gpio);
gpio_info->sw_io_output[gpio] = MAC_AX_SW_IO_OUT_PP;
break;
default:
PLTFM_MSG_ERR("%s: Wrong SW GPIO mode: %d", __func__, mode);
ret = MACNOITEM;
break;
}
return ret;
}
u32 mac_sw_gpio_ctrl(struct mac_ax_adapter *adapter,
u8 high, u8 gpio)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
struct mac_ax_gpio_info *gpio_info = &adapter->gpio_info;
u32 reg, ret;
u8 ctrl, val8;
if (gpio >= MAC_AX_GPIO_NUM) {
PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, gpio);
ret = MACNOITEM;
goto END;
}
if (high && gpio_info->sw_io_output[gpio] == MAC_AX_SW_IO_OUT_OD) {
ret = _mac_set_sw_gpio_mode(adapter, 0, gpio);
} else {
ret = _mac_set_sw_gpio_mode(adapter, 1, gpio);
if (ret) {
PLTFM_MSG_ERR("%s: Set GPIO mode fail\n", __func__);
goto END;
}
if (gpio <= 7) {
reg = R_AX_GPIO_PIN_CTRL + 1;
} else {
reg = R_AX_GPIO_EXT_CTRL + 1;
gpio = gpio - 8;
}
ctrl = (high == 0) ? 0 : 1;
val8 = MAC_REG_R8(reg);
val8 = (val8 & ~((u8)BIT(gpio))) | (u8)(ctrl << gpio);
MAC_REG_W8(reg, val8);
}
END:
return ret;
}
enum rtw_mac_gfunc mac_get_gpio_status(struct mac_ax_adapter *adapter,
const struct mac_ax_pin_list *list)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
u8 val;
enum rtw_mac_gfunc curr = RTW_MAC_GPIO_INVALID;
while (list->func != RTW_MAC_GPIO_LAST) {
/* first fit list*/
if (curr != list->func &&
list->offset >= R_AX_GPIO0_7_FUNC_SEL &&
list->offset <= R_AX_EECS_EESK_FUNC_SEL) {
curr = list->func;
val = MAC_REG_R8(list->offset);
if ((val & list->msk) == list->value)
return list->func;
}
list++;
}
return RTW_MAC_GPIO_INVALID;
}
u32 mac_cfg_wps(struct mac_ax_adapter *adapter,
struct mac_ax_cfg_wps *wps)
{
u32 ret;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_cfg_wps *ptr;
struct mac_ax_gpio_info *info = &adapter->gpio_info;
if (wps->gpio > RTW_MAC_GPIO_MAX) {
PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, wps->gpio);
return MACGPIONUM;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
ptr = (struct fwcmd_cfg_wps *)h2cb_put(h2cb, sizeof(*ptr));
if (!ptr) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMSET(ptr, 0, sizeof(*ptr));
ptr->dword0 = cpu_to_le32((wps->en ? FWCMD_H2C_CFG_WPS_EN : 0) |
SET_WORD(wps->gpio,
FWCMD_H2C_CFG_WPS_GPIO) |
SET_WORD(wps->interval,
FWCMD_H2C_CFG_WPS_INTL));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MISC,
FWCMD_H2C_FUNC_CFG_WPS,
0,
0);
if (ret != MACSUCCESS)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret != MACSUCCESS)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
goto fail;
}
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
if (info->status[wps->gpio] != RTW_MAC_GPIO_DFLT &&
info->status[wps->gpio] != RTW_MAC_GPIO_SW_IO)
PLTFM_MSG_WARN("The gpio%d is %d\n",
wps->gpio, info->status[wps->gpio]);
info->status[wps->gpio] = RTW_MAC_GPIO_SW_IO;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_get_gpio_val(struct mac_ax_adapter *adapter, u8 gpio, u8 *val)
{
struct mac_ax_intf_ops *ops = adapter->ops->intf_ops;
u32 reg;
if (gpio <= 7) {
reg = R_AX_GPIO_PIN_CTRL;
} else if (gpio >= 8 && gpio <= 15) {
reg = R_AX_GPIO_EXT_CTRL;
gpio = gpio - 8;
} else {
PLTFM_MSG_ERR("%s: Wrong GPIO num: %d", __func__, gpio);
return MACNOITEM;
}
*val = !!(MAC_REG_R8(reg) & BIT(gpio));
return MACSUCCESS;
}
u32 mac_get_wl_dis_gpio(struct mac_ax_adapter *adapter, u8 *gpio)
{
#define MAC_AX_HCI_SEL_SDIO_UART 0
#define MAC_AX_HCI_SEL_USB_MULT 1
#define MAC_AX_HCI_SEL_PCIE_UART 2
#define MAC_AX_HCI_SEL_PCIE_USB 3
#define MAC_AX_HCI_SEL_SDIO_MULT 4
#define MAC_AX_HCI_SEL_PCIE_G1_UART 6
#define MAC_AX_HCI_SEL_PCIE_G1_USB 7
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val;
val = MAC_REG_R32(R_AX_SYS_STATUS1);
val = GET_FIELD(val, B_AX_HCI_SEL_V4);
switch (val) {
case MAC_AX_HCI_SEL_SDIO_UART:
case MAC_AX_HCI_SEL_USB_MULT:
case MAC_AX_HCI_SEL_PCIE_UART:
case MAC_AX_HCI_SEL_PCIE_USB:
case MAC_AX_HCI_SEL_PCIE_G1_UART:
case MAC_AX_HCI_SEL_PCIE_G1_USB:
*gpio = 9;
break;
case MAC_AX_HCI_SEL_SDIO_MULT:
*gpio = 15;
break;
default:
PLTFM_MSG_ERR("%s: Wrong HCI\n", __func__);
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_get_wl_dis_val(struct mac_ax_adapter *adapter, u8 *val)
{
u8 gpio;
u32 ret;
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
ret = mac_get_wl_dis_gpio(adapter, &gpio);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: Get WL_DIS GPIO fail\n", __func__);
return ret;
}
ret = ops->set_sw_gpio_mode(adapter, MAC_AX_SW_IO_MODE_INPUT, gpio);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: Set SW output mode fail\n", __func__);
return ret;
}
return mac_get_gpio_val(adapter, gpio, val);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/gpio.c
|
C
|
agpl-3.0
| 16,982
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_GPIO_H_
#define _MAC_AX_GPIO_H_
#include "../type.h"
#include "gpio_cmd.h"
#define DFLT_GPIO_STATE \
{RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \
RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \
RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \
RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \
RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \
RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, RTW_MAC_GPIO_DFLT, \
RTW_MAC_GPIO_DFLT}
#define DFLT_SW_IO_MODE \
{0, 0, 0, 0, \
0, 0, 0, 0, \
0, 0, 0, 0, \
0, 0, 0, 0}
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_sel_uart_tx_pin
*
* @param *adapter
* @param uart_pin
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sel_uart_tx_pin(struct mac_ax_adapter *adapter,
enum mac_ax_uart_tx_pin uart_pin);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_pinmux_status
*
* @param *adapter
* @param func
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pinmux_status(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_pinmux_free_func
*
* @param *adapter
* @param func
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pinmux_free_func(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_pinmux_record
*
* @param *adapter
* @param func
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pinmux_record(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_pinmux_switch
*
* @param *adapter
* @param gpio_func
* @param *list
* @param list_size
* @param gpio_id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pinmux_switch(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func gpio_func,
const struct mac_ax_pinmux_list *list,
u32 list_size, u32 gpio_id);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_sel_uart_rx_pin
*
* @param *adapter
* @param uart_pin
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sel_uart_rx_pin(struct mac_ax_adapter *adapter,
enum mac_ax_uart_rx_pin uart_pin);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_set_led_mode
*
* @param *adapter
* @param mode
* @param led_id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_led_mode(struct mac_ax_adapter *adapter,
enum mac_ax_led_mode mode, u8 led_id);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_led_ctrl
*
* @param *adapter
* @param high
* @param led_id
* @return Please Place Description here.
* @retval u32
*/
u32 mac_led_ctrl(struct mac_ax_adapter *adapter,
u8 high, u8 led_id);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_sw_gpio_ctrl
*
* @param *adapter
* @param high
* @param gpio
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sw_gpio_ctrl(struct mac_ax_adapter *adapter,
u8 high, u8 gpio);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_set_sw_gpio_mode
*
* @param *adapter
* @param mode
* @param gpio
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_sw_gpio_mode(struct mac_ax_adapter *adapter,
enum mac_ax_sw_io_mode mode, u8 gpio);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_get_gpio_status
*
* @param *adapter
* @param *list
* @return Please Place Description here.
* @retval rtw_mac_gfunc
*/
enum rtw_mac_gfunc mac_get_gpio_status(struct mac_ax_adapter *adapter,
const struct mac_ax_pin_list *list);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup GPIO
* @{
*/
/**
* @brief mac_cfg_wps
*
* WPS is a driver feature to detect button pressed or released.
* In HW view, the feature is to check the GPIO input value is 0->1 or 1->0
* We use FW to detect GPIO val.
* In a specified interval, if FW detects value changed, it will send a C2H
*
* @param *adapter
* @param *wps
* @return 0 for succcess, others for fail
* @retval u32
*/
u32 mac_cfg_wps(struct mac_ax_adapter *adapter,
struct mac_ax_cfg_wps *wps);
/**
* @}
* @}
*/
u32 mac_get_gpio_val(struct mac_ax_adapter *adapter, u8 gpio, u8 *val);
u32 mac_get_wl_dis_val(struct mac_ax_adapter *adapter, u8 *val);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/gpio.h
|
C
|
agpl-3.0
| 5,598
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_GPIO_CMD_H_
#define _MAC_AX_GPIO_CMD_H_
#include "../type.h"
#define MAC_AX_GPIO_MIN 0
#define RTW_MAC_GPIO_MAX 17
/**
* @enum pinmux_name
*
* @brief pinmux_name
*
* @var pinmux_name::MAC_AX_WL_HWPDN
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_HWPDN
* Please Place Description here.
* @var pinmux_name::MAC_AX_SWGPIO
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_HW_EXTWOL
* Please Place Description here.
* @var pinmux_name::MAC_AX_SIC
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_SFALSH
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_SFALSH
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_LED
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_SDIO_INT
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_SDIO_INT
* Please Place Description here.
* @var pinmux_name::MAC_AX_UART
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_JTAG
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_JTAG
* Please Place Description here.
* @var pinmux_name::MAC_AX_LTE_UART
* Please Place Description here.
* @var pinmux_name::MAC_AX_LTE_3W
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_GPIO16
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_OSC
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_OSC
* Please Place Description here.
* @var pinmux_name::MAC_AX_GPIO13_14_WL_CTRL_EN
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_RF
* Please Place Description here.
* @var pinmux_name::MAC_AX_DBG_GNT
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_3DDLS_A
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_3DDLS_B
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_GPIO18
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_PTA
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_PTA
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_UART_TX
* Please Place Description here.
* @var pinmux_name::MAC_AX_WL_UART_RX
* Please Place Description here.
* @var pinmux_name::MAC_AX_WLMAC_DBG
* Please Place Description here.
* @var pinmux_name::MAC_AX_WLPHY_DBG
* Please Place Description here.
* @var pinmux_name::MAC_AX_BT_DBG
* Please Place Description here.
* @var pinmux_name::MAC_AX_MAILBOX_3W
* Please Place Description here.
* @var pinmux_name::MAC_AX_MAILBOX_1W
* Please Place Description here.
* @var pinmux_name::MAC_AX_PAON_LNAON_2G_S0
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_0
* Please Place Description here.
* @var pinmux_name::MAC_AX_PAON_LNAON_2G_S1
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_1
* Please Place Description here.
* @var pinmux_name::MAC_AX_PAON_LNAON_5G_S0
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_2
* Please Place Description here.
* @var pinmux_name::MAC_AX_PAON_LNAON_5G_S1
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_3
* Please Place Description here.
* @var pinmux_name::MAC_AX_BANDSEL_5_6G
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_4
* Please Place Description here.
* @var pinmux_name::MAC_AX_BANDSEL_5G
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_5
* Please Place Description here.
* @var pinmux_name::MAC_AX_PAON_LNAON_6G_S1
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_7
* Please Place Description here.
* @var pinmux_name::MAC_AX_BANDSEL_5G_G7G6
* Please Place Description here.
* @var pinmux_name::MAC_AX_RFE_WLBT_FUNC_8
* Please Place Description here.
* @var pinmux_name::MAC_AX_EXT_XTAL_CLK
* Please Place Description here.
* @var pinmux_name::MAC_AX_SW_IO
* Please Place Description here.
*/
enum pinmux_name {
MAC_AX_WL_HWPDN,
MAC_AX_BT_HWPDN,
MAC_AX_SWGPIO,
MAC_AX_WL_HW_EXTWOL,
MAC_AX_SIC,
MAC_AX_BT_SFALSH,
MAC_AX_WL_SFALSH,
MAC_AX_WL_LED,
MAC_AX_WL_SDIO_INT,
MAC_AX_BT_SDIO_INT,
MAC_AX_UART,
MAC_AX_BT_JTAG,
MAC_AX_WL_JTAG,
MAC_AX_LTE_UART,
MAC_AX_LTE_3W,
MAC_AX_BT_GPIO16,
MAC_AX_WL_OSC,
MAC_AX_BT_OSC,
MAC_AX_GPIO13_14_WL_CTRL_EN,
MAC_AX_BT_RF,
MAC_AX_DBG_GNT,
MAC_AX_BT_3DDLS_A,
MAC_AX_BT_3DDLS_B,
MAC_AX_BT_GPIO18,
MAC_AX_BT_PTA,
MAC_AX_WL_PTA,
MAC_AX_WL_UART_TX,
MAC_AX_WL_UART_RX,
MAC_AX_WLMAC_DBG,
MAC_AX_WLPHY_DBG,
MAC_AX_BT_DBG,
MAC_AX_MAILBOX_3W,
MAC_AX_MAILBOX_1W,
MAC_AX_PAON_LNAON_2G_S0,
MAC_AX_RFE_WLBT_FUNC_0,
MAC_AX_PAON_LNAON_2G_S1,
MAC_AX_RFE_WLBT_FUNC_1,
MAC_AX_PAON_LNAON_5G_S0,
MAC_AX_RFE_WLBT_FUNC_2,
MAC_AX_PAON_LNAON_5G_S1,
MAC_AX_RFE_WLBT_FUNC_3,
MAC_AX_BANDSEL_5_6G,
MAC_AX_RFE_WLBT_FUNC_4,
MAC_AX_BANDSEL_5G,
MAC_AX_RFE_WLBT_FUNC_5,
MAC_AX_PAON_LNAON_6G_S1,
MAC_AX_RFE_WLBT_FUNC_7,
MAC_AX_BANDSEL_5G_G7G6,
MAC_AX_RFE_WLBT_FUNC_8,
MAC_AX_EXT_XTAL_CLK,
MAC_AX_SW_IO,
};
/**
* @enum pinmux_gpio
*
* @brief pinmux_gpio
*
* @var pinmux_gpio::MAC_AX_GPIO0
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO1
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO2
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO3
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO4
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO5
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO6
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO7
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO8
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO9
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO10
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO11
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO12
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO13
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO14
* Please Place Description here.
* @var pinmux_gpio::MAC_AX_GPIO15
* Please Place Description here.
*/
enum pinmux_gpio {
MAC_AX_GPIO0,
MAC_AX_GPIO1,
MAC_AX_GPIO2,
MAC_AX_GPIO3,
MAC_AX_GPIO4,
MAC_AX_GPIO5,
MAC_AX_GPIO6,
MAC_AX_GPIO7,
MAC_AX_GPIO8,
MAC_AX_GPIO9,
MAC_AX_GPIO10,
MAC_AX_GPIO11,
MAC_AX_GPIO12,
MAC_AX_GPIO13,
MAC_AX_GPIO14,
MAC_AX_GPIO15,
};
/**
* @enum pinmux_gpio_type
*
* @brief pinmux_gpio_type
*
* @var pinmux_gpio_type::MAC_AX_GPIO_IN
* Please Place Description here.
* @var pinmux_gpio_type::MAC_AX_GPIO_OUT
* Please Place Description here.
* @var pinmux_gpio_type::MAC_AX_GPIO_IN_OUT
* Please Place Description here.
*/
enum pinmux_gpio_type {
MAC_AX_GPIO_IN,
MAC_AX_GPIO_OUT,
MAC_AX_GPIO_IN_OUT,
};
/**
* @struct mac_ax_pinmux_list
* @brief mac_ax_pinmux_list
*
* @var mac_ax_pinmux_list::func
* Please Place Description here.
* @var mac_ax_pinmux_list::id
* Please Place Description here.
* @var mac_ax_pinmux_list::type
* Please Place Description here.
* @var mac_ax_pinmux_list::offset
* Please Place Description here.
* @var mac_ax_pinmux_list::msk
* Please Place Description here.
* @var mac_ax_pinmux_list::value
* Please Place Description here.
*/
struct mac_ax_pinmux_list {
enum pinmux_name func;
enum pinmux_gpio id;
enum pinmux_gpio_type type;
u32 offset;
u8 msk;
u8 value;
};
/**
* @struct mac_ax_pin_list
* @brief mac_ax_pin_list
*
* @var mac_ax_pin_list::func
* Please Place Description here.
* @var mac_ax_pin_list::offset
* Please Place Description here.
* @var mac_ax_pin_list::msk
* Please Place Description here.
* @var mac_ax_pin_list::value
* Please Place Description here.
*/
struct mac_ax_pin_list {
enum rtw_mac_gfunc func;
u32 offset;
u8 msk;
u8 value;
};
/**
* @struct mac_ax_gpio_func_list
* @brief mac_ax_gpio_func_list
*
* @var mac_ax_gpio_func_list::func
* Please Place Description here.
* @var mac_ax_gpio_func_list::list
* Please Place Description here.
*/
struct mac_ax_gpio_func_list {
enum rtw_mac_gfunc func;
struct mac_ax_pin_list *list;
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/gpio_cmd.h
|
C
|
agpl-3.0
| 8,813
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "h2c_agg.h"
static u32 mac_h2c_agg_tx_single_normal_h2c(struct mac_ax_adapter *adapter, u8 *h2cb)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *tx_h2cb = (struct rtw_h2c_pkt *)h2cb;
#else
struct h2c_buf *tx_h2cb = (struct h2c_buf *)h2cb;
#endif
u32 ret = MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, tx_h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(tx_h2cb);
#else
ret = PLTFM_TX(tx_h2cb->data, tx_h2cb->len);
if (ret)
goto fail;
h2cb_free(adapter, tx_h2cb);
#endif
fail:
return ret;
}
static u32 mac_h2c_agg_tx_single_agg_h2c(struct mac_ax_adapter *adapter, u8 *agg_h2cb)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *tx_h2cb = (struct rtw_h2c_pkt *)agg_h2cb;
#else
struct h2c_buf *tx_h2cb = (struct h2c_buf *)agg_h2cb;
#endif
u32 ret = MACSUCCESS;
ret = h2c_pkt_set_hdr(adapter,
tx_h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_H2C_AGG,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, tx_h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(tx_h2cb);
#else
ret = PLTFM_TX(tx_h2cb->data, tx_h2cb->len);
if (ret)
goto fail;
h2cb_free(adapter, tx_h2cb);
#endif
fail:
return ret;
}
void mac_h2c_agg_enable(struct mac_ax_adapter *adapter, u8 enable)
{
PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock);
adapter->h2c_agg_info.h2c_agg_en = enable;
PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock);
}
u32 mac_h2c_agg_tx(struct mac_ax_adapter *adapter)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *agg_h2cb = NULL;
struct rtw_h2c_pkt *cur_h2cb = NULL;
#else
struct h2c_buf *agg_h2cb = NULL;
struct h2c_buf *cur_h2cb = NULL;
#endif
struct mac_ax_h2c_agg_node *cur_agg_node = NULL;
struct mac_ax_h2c_agg_node *tmp_agg_node = NULL;
u32 agg_len = 0;
u32 cur_h2cb_len = 0;
u32 cur_sub_h2c_len = 0;
u32 cur_sub_h2c_len_swap = 0;
u32 next_h2cb_len = 0;
u32 ret = MACSUCCESS;
u8 *cur_h2cb_data = NULL;
u8 *buf = NULL;
PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock);
if (!adapter->h2c_agg_info.h2c_agg_queue_head)
goto fail;
cur_agg_node = adapter->h2c_agg_info.h2c_agg_queue_head;
agg_h2cb = NULL;
agg_len = 0;
while (cur_agg_node) {
#if MAC_AX_PHL_H2C
cur_h2cb = (struct rtw_h2c_pkt *)cur_agg_node->h2c_pkt;
cur_h2cb_len = cur_h2cb->data_len;
cur_h2cb_data = cur_h2cb->vir_data;
next_h2cb_len = (!cur_agg_node->next ? 0 :
((struct rtw_h2c_pkt *)
(cur_agg_node->next->h2c_pkt))->data_len);
#else
cur_h2cb = (struct h2c_buf *)cur_agg_node->h2c_pkt;
cur_h2cb_len = cur_h2cb->len;
cur_h2cb_data = cur_h2cb->data;
next_h2cb_len = (!cur_agg_node->next ? 0 :
((struct h2c_buf *)
(cur_agg_node->next->h2c_pkt))->len);
#endif
if (!agg_h2cb) {
if (!H2C_PKT_AGGREGATABLE(cur_h2cb_len) ||
!cur_agg_node->next ||
(cur_agg_node->next &&
!H2C_PKT_AGGREGATABLE(next_h2cb_len))) {
ret = mac_h2c_agg_tx_single_normal_h2c(adapter, (u8 *)cur_h2cb);
if (ret) {
PLTFM_MSG_ERR("tx normal h2c pkt fail\n");
goto fail;
}
tmp_agg_node = cur_agg_node;
cur_agg_node = cur_agg_node->next;
adapter->h2c_agg_info.h2c_agg_queue_head = cur_agg_node;
PLTFM_FREE(tmp_agg_node, sizeof(struct mac_ax_h2c_agg_node));
continue;
}
agg_h2cb = h2cb_alloc(adapter, H2CB_CLASS_LONG_DATA);
if (!agg_h2cb) {
PLTFM_MSG_ERR("allocate agg_h2c fail\n");
ret = MACNOBUF;
goto fail;
}
agg_len = WD_BODY_LEN + FWCMD_HDR_LEN;
}
cur_sub_h2c_len = ALIGN_4_BYTE(cur_h2cb_len);
buf = h2cb_put(agg_h2cb, cur_sub_h2c_len + H2C_AGG_SUB_HDR_LEN);
if (!buf) {
PLTFM_MSG_ERR("creat sub_h2c_buf in agg_h2cb get fail\n");
ret = MACNOITEM;
goto fail;
}
cur_sub_h2c_len_swap = cpu_to_le32(cur_sub_h2c_len);
PLTFM_MEMCPY(buf, &cur_sub_h2c_len_swap, H2C_AGG_SUB_HDR_LEN);
PLTFM_MEMCPY(buf + H2C_AGG_SUB_HDR_LEN, cur_h2cb_data, cur_h2cb_len);
agg_len = agg_len + cur_sub_h2c_len + H2C_AGG_SUB_HDR_LEN;
tmp_agg_node = cur_agg_node;
cur_agg_node = cur_agg_node->next;
adapter->h2c_agg_info.h2c_agg_queue_head = cur_agg_node;
PLTFM_FREE(tmp_agg_node, sizeof(struct mac_ax_h2c_agg_node));
#if MAC_AX_PHL_H2C
PLTFM_RECYCLE_H2C(cur_h2cb);
#else
h2cb_free(adapter, cur_h2cb);
#endif
if (!cur_agg_node ||
((agg_len + ALIGN_4_BYTE(next_h2cb_len) +
H2C_AGG_SUB_HDR_LEN) >= H2C_LONG_DATA_LEN)) {
ret = mac_h2c_agg_tx_single_agg_h2c(adapter, (u8 *)agg_h2cb);
if (ret) {
PLTFM_MSG_ERR("tx normal agg_h2c pkt fail\n");
goto fail;
}
agg_h2cb = NULL;
agg_len = 0;
}
}
fail:
if (ret) {
PLTFM_MSG_ERR("h2c agg error handle\n");
mac_h2c_agg_flush(adapter);
if (agg_h2cb) {
#if MAC_AX_PHL_H2C
PLTFM_RECYCLE_H2C((struct rtw_h2c_pkt *)agg_h2cb);
#else
h2cb_free(adapter, agg_h2cb);
#endif
}
} else {
adapter->h2c_agg_info.h2c_agg_queue_head = NULL;
adapter->h2c_agg_info.h2c_agg_queue_last = NULL;
adapter->h2c_agg_info.h2c_agg_pkt_num = 0;
}
PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock);
return ret;
}
void mac_h2c_agg_flush(struct mac_ax_adapter *adapter)
{
struct mac_ax_h2c_agg_node *cur_agg_node = NULL;
struct mac_ax_h2c_agg_node *tmp_agg_node = NULL;
PLTFM_MUTEX_LOCK(&adapter->h2c_agg_info.h2c_agg_lock);
cur_agg_node = adapter->h2c_agg_info.h2c_agg_queue_head;
while (cur_agg_node) {
#if MAC_AX_PHL_H2C
PLTFM_RECYCLE_H2C((struct rtw_h2c_pkt *)cur_agg_node->h2c_pkt);
#else
h2cb_free(adapter, (struct h2c_buf *)cur_agg_node->h2c_pkt);
#endif
tmp_agg_node = cur_agg_node;
cur_agg_node = cur_agg_node->next;
PLTFM_FREE(tmp_agg_node, sizeof(struct mac_ax_h2c_agg_node));
}
adapter->h2c_agg_info.h2c_agg_queue_head = NULL;
adapter->h2c_agg_info.h2c_agg_queue_last = NULL;
adapter->h2c_agg_info.h2c_agg_pkt_num = 0;
PLTFM_MUTEX_UNLOCK(&adapter->h2c_agg_info.h2c_agg_lock);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/h2c_agg.c
|
C
|
agpl-3.0
| 6,521
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _H2C_AGG_H_
#define _H2C_AGG_H_
#include "../type.h"
#include "fwcmd.h"
#include "../fw_ax/inc_hdr/fwcmd_intf.h"
#define ALIGN_4_BYTE(len) ((len + 0x3) & ~(0x3))
#define H2C_AGG_SUB_HDR_LEN sizeof(u32)
#define H2C_PKT_AGGREGATABLE(len) ((ALIGN_4_BYTE(len) + \
WD_BODY_LEN + FWCMD_HDR_LEN + \
H2C_AGG_SUB_HDR_LEN) \
< H2C_LONG_DATA_LEN)
void mac_h2c_agg_flush(struct mac_ax_adapter *adapter);
u32 mac_h2c_agg_tx(struct mac_ax_adapter *adapter);
void mac_h2c_agg_enable(struct mac_ax_adapter *adapter, u8 enable);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/h2c_agg.h
|
C
|
agpl-3.0
| 1,218
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "hci_fc.h"
static u32 chcfg_size = sizeof(struct mac_ax_hfc_ch_cfg) * MAC_AX_DMA_CH_NUM;
static u32 chinfo_size = sizeof(struct mac_ax_hfc_ch_info) * MAC_AX_DMA_CH_NUM;
#if MAC_AX_PCIE_SUPPORT
#ifdef PHL_FEATURE_AP
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_8852a[] = {
{16, 3792, grp_0}, /* ACH 0 */
{16, 3792, grp_0}, /* ACH 1 */
{16, 3792, grp_0}, /* ACH 2 */
{16, 3792, grp_0}, /* ACH 3 */
{8, 3792, grp_0}, /* ACH 4 */
{8, 3792, grp_0}, /* ACH 5 */
{8, 3792, grp_0}, /* ACH 6 */
{8, 3792, grp_0}, /* ACH 7 */
{16, 3792, grp_0}, /* B0MGQ */
{16, 3792, grp_0}, /* B0HIQ */
{8, 3792, grp_0}, /* B1MGQ */
{8, 3792, grp_0}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
#else // for NiC mode use
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_8852a[] = {
{16, 3276, grp_0}, /* ACH 0 */
{16, 3276, grp_0}, /* ACH 1 */
{16, 3276, grp_0}, /* ACH 2 */
{16, 3276, grp_0}, /* ACH 3 */
{8, 3284, grp_0}, /* ACH 4 */
{8, 3284, grp_0}, /* ACH 5 */
{8, 3284, grp_0}, /* ACH 6 */
{8, 3284, grp_0}, /* ACH 7 */
{16, 3276, grp_0}, /* B0MGQ */
{16, 3276, grp_0}, /* B0HIQ */
{8, 3284, grp_0}, /* B1MGQ */
{8, 3284, grp_0}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
#endif
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_8852b[] = {
{16, 744, grp_0}, /* ACH 0 */
{16, 744, grp_0}, /* ACH 1 */
{16, 744, grp_0}, /* ACH 2 */
{16, 744, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{16, 744, grp_0}, /* B0MGQ */
{16, 744, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_scc_8852c[] = {
{13, 1614, grp_0}, /* ACH 0 */
{13, 1614, grp_0}, /* ACH 1 */
{13, 1614, grp_0}, /* ACH 2 */
{13, 1614, grp_0}, /* ACH 3 */
{13, 1614, grp_1}, /* ACH 4 */
{13, 1614, grp_1}, /* ACH 5 */
{13, 1614, grp_1}, /* ACH 6 */
{13, 1614, grp_1}, /* ACH 7 */
{13, 1614, grp_0}, /* B0MGQ */
{13, 1614, grp_0}, /* B0HIQ */
{13, 1614, grp_1}, /* B1MGQ */
{13, 1614, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_dbcc_8852c[] = {
{12, 1609, grp_0}, /* ACH 0 */
{12, 1609, grp_0}, /* ACH 1 */
{12, 1609, grp_0}, /* ACH 2 */
{12, 1609, grp_0}, /* ACH 3 */
{12, 1609, grp_1}, /* ACH 4 */
{12, 1609, grp_1}, /* ACH 5 */
{12, 1609, grp_1}, /* ACH 6 */
{12, 1609, grp_1}, /* ACH 7 */
{12, 1609, grp_0}, /* B0MGQ */
{12, 1609, grp_0}, /* B0HIQ */
{12, 1609, grp_1}, /* B1MGQ */
{12, 1609, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_wd128_8852b[] = {
{256, 1792, grp_0}, /* ACH 0 */
{256, 1792, grp_0}, /* ACH 1 */
{256, 1792, grp_0}, /* ACH 2 */
{256, 1792, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{256, 1792, grp_0}, /* B0MGQ */
{256, 1792, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_stf_8852a[] = {
{8, 256, grp_0}, /* ACH 0 */
{8, 256, grp_0}, /* ACH 1 */
{8, 256, grp_0}, /* ACH 2 */
{8, 256, grp_0}, /* ACH 3 */
{8, 256, grp_1}, /* ACH 4 */
{8, 256, grp_1}, /* ACH 5 */
{8, 256, grp_1}, /* ACH 6 */
{8, 256, grp_1}, /* ACH 7 */
{8, 256, grp_0}, /* B0MGQ */
{8, 256, grp_0}, /* B0HIQ */
{8, 256, grp_1}, /* B1MGQ */
{8, 256, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_stf_8852b[] = {
{27, 204, grp_0}, /* ACH 0 */
{27, 204, grp_0}, /* ACH 1 */
{27, 204, grp_0}, /* ACH 2 */
{27, 204, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{11, 204, grp_0}, /* B0MGQ */
{11, 204, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_scc_stf_8852c[] = {
{2, 108, grp_0}, /* ACH 0 */
{2, 108, grp_0}, /* ACH 1 */
{2, 108, grp_0}, /* ACH 2 */
{2, 108, grp_0}, /* ACH 3 */
{2, 108, grp_1}, /* ACH 4 */
{2, 108, grp_1}, /* ACH 5 */
{2, 108, grp_1}, /* ACH 6 */
{2, 108, grp_1}, /* ACH 7 */
{2, 108, grp_0}, /* B0MGQ */
{2, 108, grp_0}, /* B0HIQ */
{2, 108, grp_1}, /* B1MGQ */
{2, 108, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_dbcc_stf_8852c[] = {
{2, 76, grp_0}, /* ACH 0 */
{2, 76, grp_0}, /* ACH 1 */
{2, 76, grp_0}, /* ACH 2 */
{2, 76, grp_0}, /* ACH 3 */
{2, 76, grp_1}, /* ACH 4 */
{2, 76, grp_1}, /* ACH 5 */
{2, 76, grp_1}, /* ACH 6 */
{2, 76, grp_1}, /* ACH 7 */
{2, 76, grp_0}, /* B0MGQ */
{2, 76, grp_0}, /* B0HIQ */
{2, 76, grp_1}, /* B1MGQ */
{2, 76, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_sutp_8852a[] = {
{128, 256, grp_0}, /* ACH 0 */
{0, 0, grp_1}, /* ACH 1 */
{0, 0, grp_1}, /* ACH 2 */
{0, 0, grp_1}, /* ACH 3 */
{0, 0, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{0, 0, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{0, 0, grp_1}, /* B0MGQ */
{0, 0, grp_1}, /* B0HIQ */
{0, 0, grp_1}, /* B1MGQ */
{0, 0, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_bcn_test_8852a[] = {
{128, 1833, grp_0}, /* ACH 0 */
{128, 1833, grp_0}, /* ACH 1 */
{128, 1833, grp_0}, /* ACH 2 */
{128, 1833, grp_0}, /* ACH 3 */
{128, 1833, grp_1}, /* ACH 4 */
{128, 1833, grp_1}, /* ACH 5 */
{128, 1833, grp_1}, /* ACH 6 */
{128, 1833, grp_1}, /* ACH 7 */
{32, 1833, grp_0}, /* B0MGQ */
{128, 1833, grp_0}, /* B0HIQ */
{32, 1833, grp_1}, /* B1MGQ */
{128, 1833, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_la_8852a[] = {
{64, 586, grp_0}, /* ACH 0 */
{64, 586, grp_0}, /* ACH 1 */
{64, 586, grp_0}, /* ACH 2 */
{64, 586, grp_0}, /* ACH 3 */
{64, 586, grp_1}, /* ACH 4 */
{64, 586, grp_1}, /* ACH 5 */
{64, 586, grp_1}, /* ACH 6 */
{64, 586, grp_1}, /* ACH 7 */
{32, 586, grp_0}, /* B0MGQ */
{64, 586, grp_0}, /* B0HIQ */
{32, 586, grp_1}, /* B1MGQ */
{64, 586, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_la_8852b[] = {
{10, 200, grp_0}, /* ACH 0 */
{10, 200, grp_0}, /* ACH 1 */
{10, 200, grp_0}, /* ACH 2 */
{10, 200, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{4, 200, grp_0}, /* B0MGQ */
{4, 200, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_pcie_la_8852c[] = {
{4, 1560, grp_0}, /* ACH 0 */
{4, 1560, grp_0}, /* ACH 1 */
{4, 1560, grp_0}, /* ACH 2 */
{4, 1560, grp_0}, /* ACH 3 */
{4, 1560, grp_1}, /* ACH 4 */
{4, 1560, grp_1}, /* ACH 5 */
{4, 1560, grp_1}, /* ACH 6 */
{4, 1560, grp_1}, /* ACH 7 */
{4, 1560, grp_0}, /* B0MGQ */
{4, 1560, grp_0}, /* B0HIQ */
{4, 1560, grp_1}, /* B1MGQ */
{4, 1560, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
#ifdef PHL_FEATURE_AP
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_8852a = {
3792, /* Group 0 */
0, /* Group 1 */
3792, /* Public Max */
0 /* WP threshold */
};
#else //for nic mode use
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_8852a = {
3792, /* Group 0 */
0, /* Group 1 */
3792, /* Public Max */
0 /* WP threshold */
};
#endif
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_8852b = {
960, /* Group 0 */
0, /* Group 1 */
960, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_scc_8852c = {
1614, /* Group 0 */
1614, /* Group 1 */
3228, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_dbcc_8852c = {
1609, /* Group 0 */
1609, /* Group 1 */
3218, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_wd128_8852b = {
1792, /* Group 0 */
0, /* Group 1 */
1792, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_stf_8852a = {
256, /* Group 0 */
256, /* Group 1 */
512, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_stf_8852b = {
204, /* Group 0 */
0, /* Group 1 */
204, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_scc_stf_8852c = {
108, /* Group 0 */
108, /* Group 1 */
216, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_dbcc_stf_8852c = {
76, /* Group 0 */
76, /* Group 1 */
152, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_sutp_8852a = {
256, /* Group 0 */
0, /* Group 1 */
256, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_bcn_test_8852a = {
1833, /* Group 0 */
1833, /* Group 1 */
3666, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_la_8852a = {
586, /* Group 0 */
586, /* Group 1 */
1172, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_la_8852b = {
200, /* Group 0 */
0, /* Group 1 */
200, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_pcie_la_8852c = {
1560, /* Group 0 */
1560, /* Group 1 */
3120, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie = {
2, /*CH 0-11 pre-cost */
40, /*H2C pre-cost */
0, /* WP CH 0-7 pre-cost */
0, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_wd128 = {
2, /*CH 0-11 pre-cost */
40, /*H2C pre-cost */
0, /* WP CH 0-7 pre-cost */
0, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_stf = {
1, /*CH 0-11 pre-cost */
40, /*H2C pre-cost */
64, /* WP CH 0-7 pre-cost */
64, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X2, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X2 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_stf_8852c = {
1, /*CH 0-11 pre-cost */
40, /*H2C pre-cost */
48, /* WP CH 0-7 pre-cost */
48, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_dlfw_8852c = {
0, /*CH 0-11 pre-cost */
256, /*H2C pre-cost */
0, /* WP CH 0-7 pre-cost */
0, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_pcie_la_8852c = {
2, /*CH 0-11 pre-cost */
20, /*H2C pre-cost */
0, /* WP CH 0-7 pre-cost */
0, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */
};
#endif
#if MAC_AX_USB_SUPPORT
static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_dbcc[] = {
{22, 212, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{22, 212, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{22, 212, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{22, 212, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{22, 212, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{22, 212, grp_1}, /* B1MGQ */
{0, 0, grp_1}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_dbcc = {
256, /* Group 0 */
256, /* Group 1 */
512, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_scc_8852a[] = {
{22, 402, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{22, 402, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{22, 402, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{22, 402, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{22, 402, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{22, 402, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_scc_8852b[] = {
{18, 204, grp_0}, /* ACH 0 */
{18, 204, grp_0}, /* ACH 1 */
{18, 204, grp_0}, /* ACH 2 */
{18, 204, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{18, 204, grp_0}, /* B0MGQ */
{18, 204, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_scc_8852a = {
512, /* Group 0 */
0, /* Group 1 */
512, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_scc_8852b = {
204, /* Group 0 */
0, /* Group 1 */
204, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_usb_8852a = {
11, /*CH 0-11 pre-cost */
32, /*H2C pre-cost */
76, /* WP CH 0-7 pre-cost */
25, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X2, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X2 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_usb_8852b = {
9, /*CH 0-11 pre-cost */
32, /*H2C pre-cost */
76, /* WP CH 0-7 pre-cost */
24, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X2, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X2, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X2, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X2 /* WP CH 8-11 full condition */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_usb_la_8852a[] = {
{22, 84, grp_0}, /* ACH 0 */
{0, 0, grp_0}, /* ACH 1 */
{22, 84, grp_0}, /* ACH 2 */
{0, 0, grp_0}, /* ACH 3 */
{22, 84, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{22, 84, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{22, 84, grp_0}, /* B0MGQ */
{0, 0, grp_0}, /* B0HIQ */
{22, 84, grp_1}, /* B1MGQ */
{0, 0, grp_1}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_usb_la_8852a = {
128, /* Group 0 */
128, /* Group 1 */
256, /* Public Max */
104 /* WP threshold */
};
#endif
#if MAC_AX_SDIO_SUPPORT
static struct mac_ax_hfc_ch_cfg hfc_chcfg_sdio_8852a[] = {
{2, 490, grp_0}, /* ACH 0 */
{2, 490, grp_0}, /* ACH 1 */
{2, 490, grp_0}, /* ACH 2 */
{2, 490, grp_0}, /* ACH 3 */
{2, 490, grp_0}, /* ACH 4 */
{2, 490, grp_0}, /* ACH 5 */
{2, 490, grp_0}, /* ACH 6 */
{2, 490, grp_0}, /* ACH 7 */
{2, 490, grp_0}, /* B0MGQ */
{2, 490, grp_0}, /* B0HIQ */
{2, 490, grp_0}, /* B1MGQ */
{2, 490, grp_0}, /* B1HIQ */
{40, 0, 0} /* H2CQ */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_sdio_8852b[] = {
{2, 102, grp_0}, /* ACH 0 */
{2, 102, grp_0}, /* ACH 1 */
{2, 102, grp_0}, /* ACH 2 */
{2, 102, grp_0}, /* ACH 3 */
{0, 0, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{0, 0, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{2, 102, grp_0}, /* B0MGQ */
{2, 102, grp_0}, /* B0HIQ */
{0, 0, grp_1}, /* B1MGQ */
{0, 0, grp_1}, /* B1HIQ */
{40, 0, 0} /* H2CQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_sdio_8852a = {
512, /* Group 0 */
0, /* Group 1 */
512, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_sdio_8852b = {
112, /* Group 0 */
0, /* Group 1 */
112, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_dbcc_sdio_8852a[] = {
{2, 246, grp_0}, /* ACH 0 */
{2, 246, grp_0}, /* ACH 1 */
{2, 246, grp_0}, /* ACH 2 */
{2, 246, grp_0}, /* ACH 3 */
{2, 246, grp_1}, /* ACH 4 */
{2, 246, grp_1}, /* ACH 5 */
{2, 246, grp_1}, /* ACH 6 */
{2, 246, grp_1}, /* ACH 7 */
{2, 246, grp_0}, /* B0MGQ */
{2, 246, grp_0}, /* B0HIQ */
{2, 246, grp_1}, /* B1MGQ */
{2, 246, grp_1}, /* B1HIQ */
{40, 0, 0} /* H2CQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_dbcc_sdio_8852a = {
256, /* Group 0 */
256, /* Group 1 */
512, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_la_sdio_8852a[] = {
{2, 54, grp_0}, /* ACH 0 */
{2, 54, grp_0}, /* ACH 1 */
{2, 54, grp_0}, /* ACH 2 */
{2, 54, grp_0}, /* ACH 3 */
{2, 54, grp_1}, /* ACH 4 */
{2, 54, grp_1}, /* ACH 5 */
{2, 54, grp_1}, /* ACH 6 */
{2, 54, grp_1}, /* ACH 7 */
{2, 54, grp_0}, /* B0MGQ */
{2, 54, grp_0}, /* B0HIQ */
{2, 54, grp_1}, /* B1MGQ */
{2, 54, grp_1}, /* B1HIQ */
{40, 0, 0} /* H2CQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_la_sdio_8852a = {
64, /* Group 0 */
64, /* Group 1 */
128, /* Public Max */
104 /* WP threshold */
};
static struct mac_ax_hfc_ch_cfg hfc_chcfg_la_sdio_8852b[] = {
{2, 102, grp_0}, /* ACH 0 */
{2, 102, grp_0}, /* ACH 1 */
{2, 102, grp_0}, /* ACH 2 */
{2, 102, grp_0}, /* ACH 3 */
{0, 0, grp_1}, /* ACH 4 */
{0, 0, grp_1}, /* ACH 5 */
{0, 0, grp_1}, /* ACH 6 */
{0, 0, grp_1}, /* ACH 7 */
{2, 102, grp_0}, /* B0MGQ */
{2, 102, grp_0}, /* B0HIQ */
{0, 0, grp_1}, /* B1MGQ */
{0, 0, grp_1}, /* B1HIQ */
{40, 0, 0} /* H2CQ */
};
static struct mac_ax_hfc_pub_cfg hfc_pubcfg_la_sdio_8852b = {
112, /* Group 0 */
0, /* Group 1 */
112, /* Public Max */
0 /* WP threshold */
};
static struct mac_ax_hfc_prec_cfg hfc_preccfg_sdio = {
1, /*CH 0-11 pre-cost */
40, /*H2C pre-cost */
0, /* WP CH 0-7 pre-cost */
0, /* WP CH 8-11 pre-cost */
MAC_AX_HFC_FULL_COND_X1, /* CH 0-11 full condition */
MAC_AX_HFC_FULL_COND_X1, /* H2C full condition */
MAC_AX_HFC_FULL_COND_X1, /* WP CH 0-7 full condition */
MAC_AX_HFC_FULL_COND_X1 /* WP CH 8-11 full condition */
};
#endif
u32 hfc_reset_param(struct mac_ax_adapter *adapter)
{
struct mac_ax_hfc_param *param;
struct mac_ax_hfc_ch_cfg *ch_cfg, *ch_cfg_ini;
struct mac_ax_hfc_ch_info *ch_info;
struct mac_ax_hfc_pub_cfg *pub_cfg, *pub_cfg_ini;
struct mac_ax_hfc_pub_info *pub_info;
struct mac_ax_hfc_prec_cfg *prec_cfg, *prec_cfg_ini;
u8 ch;
param = adapter->hfc_param;
ch_cfg = param->ch_cfg;
ch_info = param->ch_info;
pub_cfg = param->pub_cfg;
pub_info = param->pub_info;
prec_cfg = param->prec_cfg;
switch (adapter->hw_info->intf) {
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_INTF_SDIO:
param->en = 0;
param->mode = MAC_AX_HCIFC_SDIO;
prec_cfg_ini = &hfc_preccfg_sdio;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
ch_cfg_ini = hfc_chcfg_sdio_8852a;
pub_cfg_ini = &hfc_pubcfg_sdio_8852a;
break;
case MAC_AX_QTA_DBCC:
ch_cfg_ini = hfc_chcfg_dbcc_sdio_8852a;
pub_cfg_ini = &hfc_pubcfg_dbcc_sdio_8852a;
break;
case MAC_AX_QTA_DLFW:
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
break;
case MAC_AX_QTA_LAMODE:
ch_cfg_ini = hfc_chcfg_la_sdio_8852a;
pub_cfg_ini = &hfc_pubcfg_la_sdio_8852a;
break;
default:
return MACHFCCH011QTA;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
ch_cfg_ini = hfc_chcfg_sdio_8852b;
pub_cfg_ini = &hfc_pubcfg_sdio_8852b;
break;
case MAC_AX_QTA_DLFW:
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
break;
case MAC_AX_QTA_LAMODE:
ch_cfg_ini = hfc_chcfg_la_sdio_8852b;
pub_cfg_ini = &hfc_pubcfg_la_sdio_8852b;
break;
default:
return MACHFCCH011QTA;
}
} else {
return MACCHIPID;
}
break;
#endif
#if MAC_AX_USB_SUPPORT
case MAC_AX_INTF_USB:
param->en = 0;
param->mode = MAC_AX_HCIFC_STF;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
ch_cfg_ini = hfc_chcfg_usb_scc_8852a;
pub_cfg_ini = &hfc_pubcfg_usb_scc_8852a;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_DBCC:
ch_cfg_ini = hfc_chcfg_usb_dbcc;
pub_cfg_ini = &hfc_pubcfg_usb_dbcc;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_DLFW:
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_LAMODE:
ch_cfg_ini = hfc_chcfg_usb_la_8852a;
pub_cfg_ini = &hfc_pubcfg_usb_la_8852a;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
default:
return MACHFCCH011QTA;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
ch_cfg_ini = hfc_chcfg_usb_scc_8852b;
pub_cfg_ini = &hfc_pubcfg_usb_scc_8852b;
prec_cfg_ini = &hfc_preccfg_usb_8852b;
break;
case MAC_AX_QTA_DLFW:
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_usb_8852b;
break;
default:
return MACHFCCH011QTA;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
ch_cfg_ini = hfc_chcfg_usb_scc_8852a;
pub_cfg_ini = &hfc_pubcfg_usb_scc_8852a;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_DBCC:
ch_cfg_ini = hfc_chcfg_usb_dbcc;
pub_cfg_ini = &hfc_pubcfg_usb_dbcc;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_DLFW:
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_LAMODE:
ch_cfg_ini = hfc_chcfg_usb_la_8852a;
pub_cfg_ini = &hfc_pubcfg_usb_la_8852a;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
default:
return MACHFCCH011QTA;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
ch_cfg_ini = hfc_chcfg_usb_scc_8852a;
pub_cfg_ini = &hfc_pubcfg_usb_scc_8852a;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_DBCC:
ch_cfg_ini = hfc_chcfg_usb_dbcc;
pub_cfg_ini = &hfc_pubcfg_usb_dbcc;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_DLFW:
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
case MAC_AX_QTA_LAMODE:
ch_cfg_ini = hfc_chcfg_usb_la_8852a;
pub_cfg_ini = &hfc_pubcfg_usb_la_8852a;
prec_cfg_ini = &hfc_preccfg_usb_8852a;
break;
default:
return MACHFCCH011QTA;
}
} else {
return MACCHIPID;
}
break;
#endif
#if MAC_AX_PCIE_SUPPORT
case MAC_AX_INTF_PCIE:
param->en = 0;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_DBCC:
case MAC_AX_QTA_SCC:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_8852a;
pub_cfg_ini = &hfc_pubcfg_pcie_8852a;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_DBCC_STF:
case MAC_AX_QTA_SCC_STF:
param->mode = MAC_AX_HCIFC_STF;
ch_cfg_ini = hfc_chcfg_pcie_stf_8852a;
pub_cfg_ini = &hfc_pubcfg_pcie_stf_8852a;
prec_cfg_ini = &hfc_preccfg_pcie_stf;
break;
case MAC_AX_QTA_SU_TP:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_sutp_8852a;
pub_cfg_ini = &hfc_pubcfg_pcie_sutp_8852a;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_DLFW:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_LAMODE:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_la_8852a;
pub_cfg_ini = &hfc_pubcfg_pcie_la_8852a;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
default:
return MACHFCCH011QTA;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_SCC:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_8852b;
pub_cfg_ini = &hfc_pubcfg_pcie_8852b;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_SCC_STF:
param->mode = MAC_AX_HCIFC_STF;
ch_cfg_ini = hfc_chcfg_pcie_stf_8852b;
pub_cfg_ini = &hfc_pubcfg_pcie_stf_8852b;
prec_cfg_ini = &hfc_preccfg_pcie_stf;
break;
case MAC_AX_QTA_DLFW:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_LAMODE:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_la_8852b;
pub_cfg_ini = &hfc_pubcfg_pcie_la_8852b;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
default:
return MACHFCCH011QTA;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
switch (adapter->dle_info.qta_mode) {
case MAC_AX_QTA_DBCC:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_dbcc_8852c;
pub_cfg_ini = &hfc_pubcfg_pcie_dbcc_8852c;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_SCC:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_scc_8852c;
pub_cfg_ini = &hfc_pubcfg_pcie_scc_8852c;
prec_cfg_ini = &hfc_preccfg_pcie;
break;
case MAC_AX_QTA_SCC_STF:
param->mode = MAC_AX_HCIFC_STF;
ch_cfg_ini = hfc_chcfg_pcie_scc_stf_8852c;
pub_cfg_ini = &hfc_pubcfg_pcie_scc_stf_8852c;
prec_cfg_ini = &hfc_preccfg_pcie_stf_8852c;
break;
case MAC_AX_QTA_DBCC_STF:
param->mode = MAC_AX_HCIFC_STF;
ch_cfg_ini = hfc_chcfg_pcie_dbcc_stf_8852c;
pub_cfg_ini = &hfc_pubcfg_pcie_dbcc_stf_8852c;
prec_cfg_ini = &hfc_preccfg_pcie_stf_8852c;
break;
case MAC_AX_QTA_DLFW:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = NULL;
pub_cfg_ini = NULL;
prec_cfg_ini = &hfc_preccfg_pcie_dlfw_8852c;
break;
case MAC_AX_QTA_LAMODE:
param->mode = MAC_AX_HCIFC_POH;
ch_cfg_ini = hfc_chcfg_pcie_la_8852c;
pub_cfg_ini = &hfc_pubcfg_pcie_la_8852c;
prec_cfg_ini = &hfc_preccfg_pcie_la_8852c;
break;
default:
return MACHFCCH011QTA;
}
} else {
return MACCHIPID;
}
break;
#endif
default:
return MACINTF;
}
if (pub_cfg_ini) {
pub_cfg->group0 = pub_cfg_ini->group0;
pub_cfg->group1 = pub_cfg_ini->group1;
pub_cfg->pub_max = pub_cfg_ini->pub_max;
pub_cfg->wp_thrd = pub_cfg_ini->wp_thrd;
}
pub_info->g0_used = 0;
pub_info->g1_used = 0;
pub_info->pub_aval = 0;
pub_info->wp_aval = 0;
if (pub_cfg_ini) {
prec_cfg->ch011_prec = prec_cfg_ini->ch011_prec;
prec_cfg->h2c_prec = prec_cfg_ini->h2c_prec;
prec_cfg->wp_ch07_prec = prec_cfg_ini->wp_ch07_prec;
prec_cfg->wp_ch811_prec = prec_cfg_ini->wp_ch811_prec;
prec_cfg->ch011_full_cond = prec_cfg_ini->ch011_full_cond;
prec_cfg->h2c_full_cond = prec_cfg_ini->h2c_full_cond;
prec_cfg->wp_ch07_full_cond = prec_cfg_ini->wp_ch07_full_cond;
prec_cfg->wp_ch811_full_cond = prec_cfg_ini->wp_ch811_full_cond;
adapter->hw_info->sw_amsdu_max_size = prec_cfg->wp_ch07_prec *
HFC_PAGE_UNIT;
}
if (ch_cfg_ini) {
for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_CH_NUM; ch++) {
ch_cfg[ch].min = ch_cfg_ini[ch].min;
ch_cfg[ch].max = ch_cfg_ini[ch].max;
ch_cfg[ch].grp = ch_cfg_ini[ch].grp;
ch_info[ch].aval = 0;
ch_info[ch].used = 0;
}
}
return MACSUCCESS;
}
static inline u32 hfc_ch_cfg_chk(struct mac_ax_adapter *adapter, u8 ch)
{
struct mac_ax_hfc_ch_cfg *ch_cfg = adapter->hfc_param->ch_cfg;
struct mac_ax_hfc_pub_cfg *pub_cfg = adapter->hfc_param->pub_cfg;
struct mac_ax_hfc_prec_cfg *prec_cfg = adapter->hfc_param->prec_cfg;
if (ch >= MAC_AX_DMA_CH_NUM)
return MACINTF;
if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
ch_cfg[ch].max > pub_cfg->pub_max)
return MACHFCCH011QTA;
if (ch_cfg[ch].grp >= grp_num)
return MACHFCCH011GRP;
return MACSUCCESS;
}
static inline u32 hfc_pub_info_chk(struct mac_ax_adapter *adapter)
{
struct mac_ax_hfc_pub_cfg *cfg = adapter->hfc_param->pub_cfg;
struct mac_ax_hfc_pub_info *info = adapter->hfc_param->pub_info;
if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A))
return MACSUCCESS;
else
return MACHFCPUBINFO;
}
return MACSUCCESS;
}
static inline u32 hfc_pub_cfg_chk(struct mac_ax_adapter *adapter)
{
struct mac_ax_hfc_param *param = adapter->hfc_param;
struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg;
if (pub_cfg->group0 + pub_cfg->group1 > pub_cfg->pub_max)
return MACHFCPUBQTA;
return MACSUCCESS;
}
u32 hfc_ch_ctrl(struct mac_ax_adapter *adapter, u8 ch)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_ch_cfg *cfg = adapter->hfc_param->ch_cfg;
u32 val32 = 0;
u32 ret = 0;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret)
return ret;
ret = hfc_ch_cfg_chk(adapter, ch);
if (ret)
return ret;
switch (ch) {
case MAC_AX_DMA_ACH0:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH0].min, B_AX_ACH0_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH0].max, B_AX_ACH0_MAX_PG) |
(cfg[MAC_AX_DMA_ACH0].grp ? B_AX_ACH0_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH0_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH0_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH1:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH1].min, B_AX_ACH1_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH1].max, B_AX_ACH1_MAX_PG) |
(cfg[MAC_AX_DMA_ACH1].grp ? B_AX_ACH1_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH1_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH1_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH2:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH2].min, B_AX_ACH2_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH2].max, B_AX_ACH2_MAX_PG) |
(cfg[MAC_AX_DMA_ACH2].grp ? B_AX_ACH2_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH2_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH2_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH3:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH3].min, B_AX_ACH3_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH3].max, B_AX_ACH3_MAX_PG) |
(cfg[MAC_AX_DMA_ACH3].grp ? B_AX_ACH3_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH3_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH3_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH4:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH4].min, B_AX_ACH4_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH4].max, B_AX_ACH4_MAX_PG) |
(cfg[MAC_AX_DMA_ACH4].grp ? B_AX_ACH4_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH4_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH4_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH5:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH5].min, B_AX_ACH5_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH5].max, B_AX_ACH5_MAX_PG) |
(cfg[MAC_AX_DMA_ACH5].grp ? B_AX_ACH5_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH5_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH5_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH6:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH6].min, B_AX_ACH6_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH6].max, B_AX_ACH6_MAX_PG) |
(cfg[MAC_AX_DMA_ACH6].grp ? B_AX_ACH6_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH6_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH6_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_ACH7:
val32 = SET_WORD(cfg[MAC_AX_DMA_ACH7].min, B_AX_ACH7_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_ACH7].max, B_AX_ACH7_MAX_PG) |
(cfg[MAC_AX_DMA_ACH7].grp ? B_AX_ACH7_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_ACH7_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_ACH7_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_B0MG:
val32 = SET_WORD(cfg[MAC_AX_DMA_B0MG].min, B_AX_CH8_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_B0MG].max, B_AX_CH8_MAX_PG) |
(cfg[MAC_AX_DMA_B0MG].grp ? B_AX_CH8_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_CH8_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_CH8_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_B0HI:
val32 = SET_WORD(cfg[MAC_AX_DMA_B0HI].min, B_AX_CH9_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_B0HI].max, B_AX_CH9_MAX_PG) |
(cfg[MAC_AX_DMA_B0HI].grp ? B_AX_CH9_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_CH9_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_CH9_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_B1MG:
val32 = SET_WORD(cfg[MAC_AX_DMA_B1MG].min, B_AX_CH10_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_B1MG].max, B_AX_CH10_MAX_PG) |
(cfg[MAC_AX_DMA_B1MG].grp ? B_AX_CH10_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_CH10_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_CH10_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_B1HI:
val32 = SET_WORD(cfg[MAC_AX_DMA_B1HI].min, B_AX_CH11_MIN_PG) |
SET_WORD(cfg[MAC_AX_DMA_B1HI].max, B_AX_CH11_MAX_PG) |
(cfg[MAC_AX_DMA_B1HI].grp ? B_AX_CH11_GRP : 0);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_CH11_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_CH11_PAGE_CTRL, val32);
break;
case MAC_AX_DMA_H2C:
break;
default:
return MACTXCHDMA;
}
return MACSUCCESS;
}
u32 hfc_upd_ch_info(struct mac_ax_adapter *adapter, u8 ch)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_ch_info *info = adapter->hfc_param->ch_info;
struct mac_ax_hfc_ch_cfg *cfg = adapter->hfc_param->ch_cfg;
u32 val32;
u32 ret;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret)
return ret;
switch (ch) {
case MAC_AX_DMA_ACH0:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH0_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH0_PAGE_INFO);
info[MAC_AX_DMA_ACH0].aval =
GET_FIELD(val32, B_AX_ACH0_AVAL_PG);
info[MAC_AX_DMA_ACH0].used =
GET_FIELD(val32, B_AX_ACH0_USE_PG);
break;
case MAC_AX_DMA_ACH1:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH1_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH1_PAGE_INFO);
info[MAC_AX_DMA_ACH1].aval =
GET_FIELD(val32, B_AX_ACH1_AVAL_PG);
info[MAC_AX_DMA_ACH1].used =
GET_FIELD(val32, B_AX_ACH1_USE_PG);
break;
case MAC_AX_DMA_ACH2:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH2_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH2_PAGE_INFO);
info[MAC_AX_DMA_ACH2].aval =
GET_FIELD(val32, B_AX_ACH2_AVAL_PG);
info[MAC_AX_DMA_ACH2].used =
GET_FIELD(val32, B_AX_ACH2_USE_PG);
break;
case MAC_AX_DMA_ACH3:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH3_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH3_PAGE_INFO);
info[MAC_AX_DMA_ACH3].aval =
GET_FIELD(val32, B_AX_ACH3_AVAL_PG);
info[MAC_AX_DMA_ACH3].used =
GET_FIELD(val32, B_AX_ACH3_USE_PG);
break;
case MAC_AX_DMA_ACH4:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH4_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH4_PAGE_INFO);
info[MAC_AX_DMA_ACH4].aval =
GET_FIELD(val32, B_AX_ACH4_AVAL_PG);
info[MAC_AX_DMA_ACH4].used =
GET_FIELD(val32, B_AX_ACH4_USE_PG);
break;
case MAC_AX_DMA_ACH5:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH5_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH5_PAGE_INFO);
info[MAC_AX_DMA_ACH5].aval =
GET_FIELD(val32, B_AX_ACH5_AVAL_PG);
info[MAC_AX_DMA_ACH5].used =
GET_FIELD(val32, B_AX_ACH5_USE_PG);
break;
case MAC_AX_DMA_ACH6:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH6_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH6_PAGE_INFO);
info[MAC_AX_DMA_ACH6].aval =
GET_FIELD(val32, B_AX_ACH6_AVAL_PG);
info[MAC_AX_DMA_ACH6].used =
GET_FIELD(val32, B_AX_ACH6_USE_PG);
break;
case MAC_AX_DMA_ACH7:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_ACH7_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_ACH7_PAGE_INFO);
info[MAC_AX_DMA_ACH7].aval =
GET_FIELD(val32, B_AX_ACH7_AVAL_PG);
info[MAC_AX_DMA_ACH7].used =
GET_FIELD(val32, B_AX_ACH7_USE_PG);
break;
case MAC_AX_DMA_B0MG:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_CH8_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_CH8_PAGE_INFO);
info[MAC_AX_DMA_B0MG].aval =
GET_FIELD(val32, B_AX_CH8_AVAL_PG);
info[MAC_AX_DMA_B0MG].used =
GET_FIELD(val32, B_AX_CH8_USE_PG);
break;
case MAC_AX_DMA_B0HI:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_CH9_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_CH9_PAGE_INFO);
info[MAC_AX_DMA_B0HI].aval =
GET_FIELD(val32, B_AX_CH9_AVAL_PG);
info[MAC_AX_DMA_B0HI].used =
GET_FIELD(val32, B_AX_CH9_USE_PG);
break;
case MAC_AX_DMA_B1MG:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_CH10_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_CH10_PAGE_INFO);
info[MAC_AX_DMA_B1MG].aval =
GET_FIELD(val32, B_AX_CH10_AVAL_PG);
info[MAC_AX_DMA_B1MG].used =
GET_FIELD(val32, B_AX_CH10_USE_PG);
break;
case MAC_AX_DMA_B1HI:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_CH11_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_CH11_PAGE_INFO);
info[MAC_AX_DMA_B1HI].aval =
GET_FIELD(val32, B_AX_CH11_AVAL_PG);
info[MAC_AX_DMA_B1HI].used =
GET_FIELD(val32, B_AX_CH11_USE_PG);
break;
case MAC_AX_DMA_H2C:
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
val32 = MAC_REG_R32(R_AX_CH12_PAGE_INFO_V1);
else
val32 = MAC_REG_R32(R_AX_CH12_PAGE_INFO);
info[MAC_AX_DMA_H2C].aval =
GET_FIELD(val32, B_AX_CH12_AVAL_PG);
info[MAC_AX_DMA_H2C].used =
cfg[MAC_AX_DMA_H2C].min - info[MAC_AX_DMA_H2C].aval;
break;
default:
return MACTXCHDMA;
}
return MACSUCCESS;
}
u32 hfc_pub_ctrl(struct mac_ax_adapter *adapter)
{
u32 val32, ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_pub_cfg *cfg = adapter->hfc_param->pub_cfg;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret)
return ret;
ret = hfc_pub_cfg_chk(adapter);
if (ret)
return ret;
val32 = SET_WORD(cfg->group0, B_AX_PUBPG_G0) |
SET_WORD(cfg->group1, B_AX_PUBPG_G1);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_PUB_PAGE_CTRL1_V1, val32);
else
MAC_REG_W32(R_AX_PUB_PAGE_CTRL1, val32);
val32 = SET_WORD(cfg->wp_thrd, B_AX_WP_THRD);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_WP_PAGE_CTRL2_V1, val32);
else
MAC_REG_W32(R_AX_WP_PAGE_CTRL2, val32);
return MACSUCCESS;
}
u32 hfc_upd_mix_info(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_param *param = adapter->hfc_param;
struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg;
struct mac_ax_hfc_prec_cfg *prec_cfg = param->prec_cfg;
struct mac_ax_hfc_pub_info *info = param->pub_info;
u32 val32, ret;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret)
return ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO1_V1);
info->g0_used = GET_FIELD(val32, B_AX_G0_USE_PG);
info->g1_used = GET_FIELD(val32, B_AX_G1_USE_PG);
val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO3_V1);
info->g0_aval = GET_FIELD(val32, B_AX_G0_AVAL_PG);
info->g1_aval = GET_FIELD(val32, B_AX_G1_AVAL_PG);
info->pub_aval =
GET_FIELD(MAC_REG_R32(R_AX_PUB_PAGE_INFO2_V1), B_AX_PUB_AVAL_PG);
info->wp_aval =
GET_FIELD(MAC_REG_R32(R_AX_WP_PAGE_INFO1_V1), B_AX_WP_AVAL_PG);
val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL_V1);
param->en = val32 & B_AX_HCI_FC_EN ? 1 : 0;
param->h2c_en = val32 & B_AX_HCI_FC_CH12_EN ? 1 : 0;
param->mode = GET_FIELD(val32, B_AX_HCI_FC_MODE);
prec_cfg->ch011_full_cond = GET_FIELD(val32, B_AX_HCI_FC_WD_FULL_COND);
prec_cfg->h2c_full_cond = GET_FIELD(val32, B_AX_HCI_FC_CH12_FULL_COND);
prec_cfg->wp_ch07_full_cond =
GET_FIELD(val32, B_AX_HCI_FC_WP_CH07_FULL_COND);
prec_cfg->wp_ch811_full_cond =
GET_FIELD(val32, B_AX_HCI_FC_WP_CH811_FULL_COND);
val32 = MAC_REG_R32(R_AX_CH_PAGE_CTRL_V1);
prec_cfg->ch011_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH011);
prec_cfg->h2c_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH12);
val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL2_V1);
pub_cfg->pub_max = GET_FIELD(val32, B_AX_PUBPG_ALL);
val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL1_V1);
prec_cfg->wp_ch07_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH07);
prec_cfg->wp_ch811_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH811);
val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL2_V1);
pub_cfg->wp_thrd = GET_FIELD(val32, B_AX_WP_THRD);
val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL1_V1);
pub_cfg->group0 = GET_FIELD(val32, B_AX_PUBPG_G0);
pub_cfg->group1 = GET_FIELD(val32, B_AX_PUBPG_G1);
ret = hfc_pub_info_chk(adapter);
if (param->en && ret)
return ret;
} else {
val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO1);
info->g0_used = GET_FIELD(val32, B_AX_G0_USE_PG);
info->g1_used = GET_FIELD(val32, B_AX_G1_USE_PG);
val32 = MAC_REG_R32(R_AX_PUB_PAGE_INFO3);
info->g0_aval = GET_FIELD(val32, B_AX_G0_AVAL_PG);
info->g1_aval = GET_FIELD(val32, B_AX_G1_AVAL_PG);
info->pub_aval =
GET_FIELD(MAC_REG_R32(R_AX_PUB_PAGE_INFO2), B_AX_PUB_AVAL_PG);
info->wp_aval =
GET_FIELD(MAC_REG_R32(R_AX_WP_PAGE_INFO1), B_AX_WP_AVAL_PG);
val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL);
param->en = val32 & B_AX_HCI_FC_EN ? 1 : 0;
param->h2c_en = val32 & B_AX_HCI_FC_CH12_EN ? 1 : 0;
param->mode = GET_FIELD(val32, B_AX_HCI_FC_MODE);
prec_cfg->ch011_full_cond = GET_FIELD(val32, B_AX_HCI_FC_WD_FULL_COND);
prec_cfg->h2c_full_cond = GET_FIELD(val32, B_AX_HCI_FC_CH12_FULL_COND);
prec_cfg->wp_ch07_full_cond =
GET_FIELD(val32, B_AX_HCI_FC_WP_CH07_FULL_COND);
prec_cfg->wp_ch811_full_cond =
GET_FIELD(val32, B_AX_HCI_FC_WP_CH811_FULL_COND);
val32 = MAC_REG_R32(R_AX_CH_PAGE_CTRL);
prec_cfg->ch011_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH011);
prec_cfg->h2c_prec = GET_FIELD(val32, B_AX_PREC_PAGE_CH12);
val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL2);
pub_cfg->pub_max = GET_FIELD(val32, B_AX_PUBPG_ALL);
val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL1);
prec_cfg->wp_ch07_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH07);
prec_cfg->wp_ch811_prec = GET_FIELD(val32, B_AX_PREC_PAGE_WP_CH811);
val32 = MAC_REG_R32(R_AX_WP_PAGE_CTRL2);
pub_cfg->wp_thrd = GET_FIELD(val32, B_AX_WP_THRD);
val32 = MAC_REG_R32(R_AX_PUB_PAGE_CTRL1);
pub_cfg->group0 = GET_FIELD(val32, B_AX_PUBPG_G0);
pub_cfg->group1 = GET_FIELD(val32, B_AX_PUBPG_G1);
ret = hfc_pub_info_chk(adapter);
if (param->en && ret)
return ret;
}
return MACSUCCESS;
}
static void hfc_h2c_cfg(struct mac_ax_adapter *adapter)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_param *param = adapter->hfc_param;
//struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg;
struct mac_ax_hfc_prec_cfg *prec_cfg = param->prec_cfg;
val32 = SET_WORD(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
MAC_REG_W32(R_AX_CH_PAGE_CTRL_V1, val32);
else
MAC_REG_W32(R_AX_CH_PAGE_CTRL, val32);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL_V1),
prec_cfg->h2c_full_cond,
B_AX_HCI_FC_CH12_FULL_COND);
MAC_REG_W32((R_AX_HCI_FC_CTRL_V1), val32);
} else {
val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL),
prec_cfg->h2c_full_cond,
B_AX_HCI_FC_CH12_FULL_COND);
MAC_REG_W32(R_AX_HCI_FC_CTRL, val32);
}
}
static void hfc_mix_cfg(struct mac_ax_adapter *adapter)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_param *param = adapter->hfc_param;
struct mac_ax_hfc_pub_cfg *pub_cfg = param->pub_cfg;
struct mac_ax_hfc_prec_cfg *prec_cfg = param->prec_cfg;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = SET_WORD(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011) |
SET_WORD(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12);
MAC_REG_W32(R_AX_CH_PAGE_CTRL_V1, val32);
val32 = SET_WORD(pub_cfg->pub_max, B_AX_PUBPG_ALL);
MAC_REG_W32(R_AX_PUB_PAGE_CTRL2_V1, val32);
val32 = SET_WORD(prec_cfg->wp_ch07_prec, B_AX_PREC_PAGE_WP_CH07) |
SET_WORD(prec_cfg->wp_ch811_prec, B_AX_PREC_PAGE_WP_CH811);
MAC_REG_W32(R_AX_WP_PAGE_CTRL1_V1, val32);
val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL_V1),
param->mode, B_AX_HCI_FC_MODE);
val32 = SET_CLR_WORD(val32, prec_cfg->ch011_full_cond,
B_AX_HCI_FC_WD_FULL_COND);
val32 = SET_CLR_WORD(val32, prec_cfg->h2c_full_cond,
B_AX_HCI_FC_CH12_FULL_COND);
val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch07_full_cond,
B_AX_HCI_FC_WP_CH07_FULL_COND);
val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch811_full_cond,
B_AX_HCI_FC_WP_CH811_FULL_COND);
MAC_REG_W32(R_AX_HCI_FC_CTRL_V1, val32);
} else {
val32 = SET_WORD(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011) |
SET_WORD(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12);
MAC_REG_W32(R_AX_CH_PAGE_CTRL, val32);
val32 = SET_WORD(pub_cfg->pub_max, B_AX_PUBPG_ALL);
MAC_REG_W32(R_AX_PUB_PAGE_CTRL2, val32);
val32 = SET_WORD(prec_cfg->wp_ch07_prec, B_AX_PREC_PAGE_WP_CH07) |
SET_WORD(prec_cfg->wp_ch811_prec, B_AX_PREC_PAGE_WP_CH811);
MAC_REG_W32(R_AX_WP_PAGE_CTRL1, val32);
val32 = SET_CLR_WORD(MAC_REG_R32(R_AX_HCI_FC_CTRL),
param->mode, B_AX_HCI_FC_MODE);
val32 = SET_CLR_WORD(val32, prec_cfg->ch011_full_cond,
B_AX_HCI_FC_WD_FULL_COND);
val32 = SET_CLR_WORD(val32, prec_cfg->h2c_full_cond,
B_AX_HCI_FC_CH12_FULL_COND);
val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch07_full_cond,
B_AX_HCI_FC_WP_CH07_FULL_COND);
val32 = SET_CLR_WORD(val32, prec_cfg->wp_ch811_full_cond,
B_AX_HCI_FC_WP_CH811_FULL_COND);
MAC_REG_W32(R_AX_HCI_FC_CTRL, val32);
}
}
static void hfc_func_en(struct mac_ax_adapter *adapter, u8 en, u8 h2c_en)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hfc_param *param = adapter->hfc_param;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL_V1);
param->en = en ? 1 : 0;
param->h2c_en = h2c_en ? 1 : 0;
val32 = en ? (val32 | B_AX_HCI_FC_EN) : (val32 & ~B_AX_HCI_FC_EN);
val32 = h2c_en ? (val32 | B_AX_HCI_FC_CH12_EN) :
(val32 & ~B_AX_HCI_FC_CH12_EN);
MAC_REG_W32(R_AX_HCI_FC_CTRL_V1, val32);
} else {
val32 = MAC_REG_R32(R_AX_HCI_FC_CTRL);
param->en = en ? 1 : 0;
param->h2c_en = h2c_en ? 1 : 0;
val32 = en ? (val32 | B_AX_HCI_FC_EN) : (val32 & ~B_AX_HCI_FC_EN);
val32 = h2c_en ? (val32 | B_AX_HCI_FC_CH12_EN) :
(val32 & ~B_AX_HCI_FC_CH12_EN);
MAC_REG_W32(R_AX_HCI_FC_CTRL, val32);
}
}
u32 hfc_init(struct mac_ax_adapter *adapter, u8 rst, u8 en, u8 h2c_en)
{
u8 ch;
u32 ret = 0;
if (rst)
ret = hfc_reset_param(adapter);
if (ret)
return ret;
ret = check_mac_en(adapter, 0, MAC_AX_DMAC_SEL);
if (ret)
return ret;
hfc_func_en(adapter, 0, 0);
if (!en && h2c_en) {
hfc_h2c_cfg(adapter);
hfc_func_en(adapter, en, h2c_en);
return ret;
}
for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_H2C; ch++) {
ret = hfc_ch_ctrl(adapter, ch);
if (ret)
return ret;
}
ret = hfc_pub_ctrl(adapter);
if (ret)
return ret;
hfc_mix_cfg(adapter);
if (en || h2c_en) {
hfc_func_en(adapter, en, h2c_en);
PLTFM_DELAY_US(10);
}
for (ch = MAC_AX_DMA_ACH0; ch < MAC_AX_DMA_H2C; ch++) {
ret = hfc_upd_ch_info(adapter, ch);
if (ret)
return ret;
}
ret = hfc_upd_mix_info(adapter);
return ret;
}
u32 hfc_info_init(struct mac_ax_adapter *adapter)
{
adapter->hfc_param =
(struct mac_ax_hfc_param *)
PLTFM_MALLOC(sizeof(struct mac_ax_hfc_param));
adapter->hfc_param->ch_cfg =
(struct mac_ax_hfc_ch_cfg *)PLTFM_MALLOC(chcfg_size);
adapter->hfc_param->ch_info =
(struct mac_ax_hfc_ch_info *)PLTFM_MALLOC(chinfo_size);
adapter->hfc_param->pub_cfg =
(struct mac_ax_hfc_pub_cfg *)
PLTFM_MALLOC(sizeof(struct mac_ax_hfc_pub_cfg));
adapter->hfc_param->pub_info =
(struct mac_ax_hfc_pub_info *)
PLTFM_MALLOC(sizeof(struct mac_ax_hfc_pub_info));
adapter->hfc_param->prec_cfg =
(struct mac_ax_hfc_prec_cfg *)
PLTFM_MALLOC(sizeof(struct mac_ax_hfc_prec_cfg));
adapter->hfc_param->en = 0;
adapter->hfc_param->h2c_en = 0;
adapter->hfc_param->mode = 0;
return MACSUCCESS;
}
u32 hfc_info_exit(struct mac_ax_adapter *adapter)
{
PLTFM_FREE(adapter->hfc_param->prec_cfg,
sizeof(struct mac_ax_hfc_prec_cfg));
PLTFM_FREE(adapter->hfc_param->pub_info,
sizeof(struct mac_ax_hfc_pub_info));
PLTFM_FREE(adapter->hfc_param->pub_cfg,
sizeof(struct mac_ax_hfc_pub_cfg));
PLTFM_FREE(adapter->hfc_param->ch_info, chinfo_size);
PLTFM_FREE(adapter->hfc_param->ch_cfg, chcfg_size);
PLTFM_FREE(adapter->hfc_param, sizeof(struct mac_ax_hfc_param));
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hci_fc.c
|
C
|
agpl-3.0
| 51,658
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_HCIFC_H_
#define _MAC_AX_HCIFC_H_
#include "../type.h"
#include "trxcfg.h"
#include "../mac_ax.h"
#define HFC_PAGE_UNIT 64
/**
* @enum mac_ax_hfc_full_cond
*
* @brief mac_ax_hfc_full_cond
*
* @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X1
* Please Place Description here.
* @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X2
* Please Place Description here.
* @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X3
* Please Place Description here.
* @var mac_ax_hfc_full_cond::MAC_AX_HFC_FULL_COND_X4
* Please Place Description here.
*/
enum mac_ax_hfc_full_cond {
MAC_AX_HFC_FULL_COND_X1 = 0,
MAC_AX_HFC_FULL_COND_X2,
MAC_AX_HFC_FULL_COND_X3,
MAC_AX_HFC_FULL_COND_X4
};
/**
* @addtogroup HCI
* @{
* @addtogroup HCI_FlowControl
* @{
*/
/**
* @brief hfc_ch_ctrl
*
* @param *adapter
* @param ch
* @return Please Place Description here.
* @retval u32
*/
u32 hfc_ch_ctrl(struct mac_ax_adapter *adapter, u8 ch);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup HCI_FlowControl
* @{
*/
/**
* @brief hfc_upd_ch_info
*
* @param *adapter
* @param ch
* @return Please Place Description here.
* @retval u32
*/
u32 hfc_upd_ch_info(struct mac_ax_adapter *adapter, u8 ch);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup HCI_FlowControl
* @{
*/
/**
* @brief hfc_pub_ctrl
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 hfc_pub_ctrl(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup HCI_FlowControl
* @{
*/
/**
* @brief hfc_upd_mix_info
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 hfc_upd_mix_info(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup HCI_FlowControl
* @{
*/
/**
* @brief hfc_init
*
* @param *adapter
* @param rst
* @param en
* @param h2c_en
* @return Please Place Description here.
* @retval u32
*/
u32 hfc_init(struct mac_ax_adapter *adapter, u8 rst, u8 en, u8 h2c_en);
/**
* @}
* @}
*/
u32 hfc_info_init(struct mac_ax_adapter *adapter);
u32 hfc_info_exit(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hci_fc.h
|
C
|
agpl-3.0
| 2,877
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "hdr_conv.h"
#if MAC_AX_FW_REG_OFLD
u32 mac_hdr_conv(struct mac_ax_adapter *adapter, u8 en_hdr_conv)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_en_hdr_conv *content;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_hdr_conv));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
content = (struct mac_ax_en_hdr_conv *)buf;
content->enable = en_hdr_conv;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_EN_MAC_HDR_CONV,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#else
u32 mac_hdr_conv(struct mac_ax_adapter *adapter, u8 en_hdr_conv)
{
u32 val;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (en_hdr_conv) {
val = MAC_REG_R32(R_AX_HDR_SHCUT_SETTING);
val |= (B_AX_MAC_MPDU_PROC_EN |
B_AX_SHCUT_LLC_WR_LOCK |
B_AX_SHCUT_PARSE_DASA);
MAC_REG_W32(R_AX_HDR_SHCUT_SETTING, val);
} else {
val = MAC_REG_R32(R_AX_HDR_SHCUT_SETTING);
val &= (~(B_AX_MAC_MPDU_PROC_EN |
B_AX_SHCUT_LLC_WR_LOCK |
B_AX_SHCUT_PARSE_DASA));
MAC_REG_W32(R_AX_HDR_SHCUT_SETTING, val);
}
return MACSUCCESS;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hdr_conv.c
|
C
|
agpl-3.0
| 2,244
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_HDR_CONV_H_
#define _MAC_AX_HDR_CONV_H_
#include "../type.h"
/**
* @struct mac_ax_en_hdr_conv
* @brief mac_ax_en_hdr_conv
*
* @var mac_ax_en_hdr_conv::enable
* Please Place Description here.
* @var mac_ax_en_hdr_conv::rsvd0
* Please Place Description here.
*/
struct mac_ax_en_hdr_conv {
u32 enable: 1;
u32 rsvd0: 31;
};
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_hdr_conv
*
* @param *adapter
* @param en_hdr_conv
* @return Please Place Description here.
* @retval u32
*/
u32 mac_hdr_conv(struct mac_ax_adapter *adapter, u8 en_hdr_conv);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hdr_conv.h
|
C
|
agpl-3.0
| 1,333
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "hw.h"
#include "coex.h"
#include "twt.h"
#include "fwofld.h"
#include "rrsr.h"
static struct mac_ax_host_rpr_cfg rpr_cfg_poh = {
121, /* agg */
255, /* tmr */
0, /* agg_def */
0, /* tmr_def */
0, /* rsvd */
MAC_AX_FUNC_EN, /* txok_en */
MAC_AX_FUNC_EN, /* rty_lmt_en */
MAC_AX_FUNC_EN, /* lft_drop_en */
MAC_AX_FUNC_EN /* macid_drop_en */
};
static struct mac_ax_host_rpr_cfg rpr_cfg_stf = {
121, /* agg */
255, /* tmr */
0, /* agg_def */
0, /* tmr_def */
0, /* rsvd */
MAC_AX_FUNC_DIS, /* txok_en */
MAC_AX_FUNC_DIS, /* rty_lmt_en */
MAC_AX_FUNC_DIS, /* lft_drop_en */
MAC_AX_FUNC_DIS /* macid_drop_en */
};
static void get_delay_tx_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_delay_tx_cfg *cfg);
static void set_delay_tx_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_delay_tx_cfg *cfg);
struct mac_ax_hw_info *mac_get_hw_info(struct mac_ax_adapter *adapter)
{
return adapter->hw_info->done ? adapter->hw_info : NULL;
}
u8 shift_mask(u32 mask)
{
u8 i;
for (i = 0; i < 32; i++) {
if ((mask >> i) & BIT0)
break;
}
return i;
}
u32 get_block_tx_sel_msk(enum mac_ax_block_tx_sel src, u32 *msk)
{
switch (src) {
case MAC_AX_CCA:
*msk = B_AX_CCA_EN;
break;
case MAC_AX_SEC20_CCA:
*msk = B_AX_SEC20_EN;
break;
case MAC_AX_SEC40_CCA:
*msk = B_AX_SEC40_EN;
break;
case MAC_AX_SEC80_CCA:
*msk = B_AX_SEC80_EN;
break;
case MAC_AX_EDCCA:
*msk = B_AX_EDCCA_EN;
break;
case MAC_AX_BTCCA:
*msk = B_AX_BTCCA_EN;
break;
case MAC_AX_TX_NAV:
*msk = B_AX_TX_NAV_EN;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 cfg_block_tx(struct mac_ax_adapter *adapter,
enum mac_ax_block_tx_sel src, u8 band, u8 en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val, msk, ret;
u32 reg = band == 0 ? R_AX_CCA_CFG_0 : R_AX_CCA_CFG_0_C1;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret) {
PLTFM_MSG_ERR("%s: CMAC%d is NOT enabled\n", __func__, band);
return ret;
}
ret = get_block_tx_sel_msk(src, &msk);
if (ret) {
PLTFM_MSG_ERR("%s: %d is NOT supported\n", __func__, src);
return ret;
}
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)reg, msk,
en ? 1 : 0, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
#endif
val = MAC_REG_R32(reg);
if (en)
val = val | msk;
else
val = val & ~msk;
MAC_REG_W32(reg, val);
return MACSUCCESS;
}
u32 get_block_tx(struct mac_ax_adapter *adapter,
enum mac_ax_block_tx_sel src, u8 band, u8 *en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val, msk, ret;
u32 reg = band == 0 ? R_AX_CCA_CFG_0 : R_AX_CCA_CFG_0_C1;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret) {
PLTFM_MSG_ERR("%s: CMAC%d is NOT enabled", __func__, band);
return ret;
}
val = MAC_REG_R32(reg);
ret = get_block_tx_sel_msk(src, &msk);
if (ret) {
PLTFM_MSG_ERR("%s: %d is NOT supported\n", __func__, src);
return ret;
}
*en = !!(val & msk);
return MACSUCCESS;
}
u32 set_enable_bb_rf(struct mac_ax_adapter *adapter, u8 enable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 value32;
u8 value8;
u32 ret;
u8 wl_rfc_s0, wl_rfc_s1;
if (enable == 1) {
value8 = MAC_REG_R8(R_AX_SYS_FUNC_EN);
value8 |= B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN;
MAC_REG_W8(R_AX_SYS_FUNC_EN, value8);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 |= B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1;
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
value8 = PHYREG_SET_ALL_CYCLE;
MAC_REG_W8(R_AX_PHYREG_SET, value8);
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
/* RDC KS/BB suggest : write 1 then write 0 then write 1 */
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 = (value32 | B_AX_AFC_AFEDIG);
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 = (value32 & ~B_AX_AFC_AFEDIG);
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 = (value32 | B_AX_AFC_AFEDIG);
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
wl_rfc_s0 = (wl_rfc_s0 | 0x07);
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
wl_rfc_s1 = (wl_rfc_s1 | 0x07);
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
value8 = PHYREG_SET_XYN_CYCLE;
MAC_REG_W8(R_AX_PHYREG_SET, value8);
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
/* RDC KS/BB suggest : write 1 then write 0 then write 1 */
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 = (value32 | B_AX_AFC_AFEDIG);
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 = (value32 & ~B_AX_AFC_AFEDIG);
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 = (value32 | B_AX_AFC_AFEDIG);
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
wl_rfc_s0 = (wl_rfc_s0 | 0x07);
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
wl_rfc_s1 = (wl_rfc_s1 | 0x07);
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
return MACCHIPID;
}
adapter->sm.bb0_func = MAC_AX_FUNC_ON;
} else {
adapter->sm.bb0_func = MAC_AX_FUNC_OFF;
value8 = MAC_REG_R8(R_AX_SYS_FUNC_EN);
value8 &= (~(B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN));
MAC_REG_W8(R_AX_SYS_FUNC_EN, value8);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
value32 = MAC_REG_R32(R_AX_WLRF_CTRL);
value32 &= (~(B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1));
MAC_REG_W32(R_AX_WLRF_CTRL, value32);
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
wl_rfc_s0 = (wl_rfc_s0 & 0xF8);
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_read_xtal_si(adapter, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
wl_rfc_s1 = (wl_rfc_s1 & 0xF8);
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
return MACSUCCESS;
} else {
return MACCHIPID;
}
}
return MACSUCCESS;
}
static u32 set_append_fcs(struct mac_ax_adapter *adapter, u8 enable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 value8;
value8 = MAC_REG_R8(R_AX_MPDU_PROC);
value8 = enable == 1 ? value8 | B_AX_APPEND_FCS :
value8 & ~B_AX_APPEND_FCS;
MAC_REG_W8(R_AX_MPDU_PROC, value8);
return MACSUCCESS;
}
static u32 set_accept_icverr(struct mac_ax_adapter *adapter, u8 enable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 value8;
value8 = MAC_REG_R8(R_AX_MPDU_PROC);
value8 = enable == 1 ? (value8 | B_AX_A_ICV_ERR) :
(value8 & ~B_AX_A_ICV_ERR);
MAC_REG_W8(R_AX_MPDU_PROC, value8);
return MACSUCCESS;
}
u32 set_gt3_timer(struct mac_ax_adapter *adapter,
struct mac_ax_gt3_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = (cfg->count_en ? B_AX_GT3_COUNT_EN : 0) |
(cfg->mode ? B_AX_GT3_MODE : 0) |
(cfg->gt3_en ? B_AX_GT3_EN : 0) |
(cfg->sort_en ? B_AX_GT3_SORT_EN : 0) |
SET_WORD(cfg->timeout, B_AX_GT3_DATA);
MAC_REG_W32(R_AX_GT3_CTRL, val32);
return MACSUCCESS;
}
u32 set_cctl_rty_limit(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_rty_lmt_cfg *cfg)
{
#define DFLT_DATA_RTY_LIMIT 32
#define DFLT_RTS_RTY_LIMIT 15
struct mac_ax_cctl_info info;
struct mac_ax_cctl_info mask;
u32 data_rty, rts_rty;
PLTFM_MEMSET(&mask, 0, sizeof(struct mac_ax_cctl_info));
PLTFM_MEMSET(&info, 0, sizeof(struct mac_ax_cctl_info));
data_rty = cfg->data_lmt_val == 0 ?
DFLT_DATA_RTY_LIMIT : cfg->data_lmt_val;
rts_rty = cfg->rts_lmt_val == 0 ?
DFLT_RTS_RTY_LIMIT : cfg->rts_lmt_val;
info.data_txcnt_lmt_sel = cfg->data_lmt_sel;
info.data_tx_cnt_lmt = data_rty;
info.rts_txcnt_lmt_sel = cfg->rts_lmt_sel;
info.rts_txcnt_lmt = rts_rty;
mask.data_txcnt_lmt_sel = TXCNT_LMT_MSK;
mask.data_tx_cnt_lmt = FWCMD_H2C_CCTRL_DATA_TX_CNT_LMT_MSK;
mask.rts_txcnt_lmt_sel = TXCNT_LMT_MSK;
mask.rts_txcnt_lmt = FWCMD_H2C_CCTRL_RTS_TXCNT_LMT_MSK;
mac_upd_cctl_info(adapter, &info, &mask, cfg->macid, TBL_WRITE_OP);
return MACSUCCESS;
}
u32 get_data_rty_limit(struct mac_ax_adapter *adapter,
struct mac_ax_rty_lmt *rty)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS;
struct mac_role_tbl *role;
u32 offset;
u8 band;
role = mac_role_srch(adapter, rty->macid);
if (!role) {
PLTFM_MSG_ERR("%s: The MACID%d does not exist\n",
__func__, rty->macid);
return MACNOITEM;
}
if (role->info.c_info.data_txcnt_lmt_sel) {
rty->tx_cnt = role->info.c_info.data_tx_cnt_lmt;
} else {
band = role->info.wmm < 2 ? 0 : 1;
offset = band == 0 ? R_AX_TXCNT + 2 : R_AX_TXCNT_C1 + 2;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret == MACSUCCESS)
rty->tx_cnt = MAC_REG_R8(offset);
}
return ret;
}
u32 set_bacam_mode(struct mac_ax_adapter *adapter, u8 mode_sel)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_RESPBA_CAM_CTRL) & (~B_AX_BACAM_ENT_CFG);
if (mode_sel)
MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32 | B_AX_BACAM_ENT_CFG);
else
MAC_REG_W32(R_AX_RESPBA_CAM_CTRL, val32);
return MACSUCCESS;
}
u32 set_xtal_aac(struct mac_ax_adapter *adapter, u8 aac_mode)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
val8 = MAC_REG_R8(R_AX_XTAL_ON_CTRL2);
val8 &= ~(0x30);
val8 |= ((aac_mode & B_AX_AAC_MODE_MSK) << B_AX_AAC_MODE_SH);
MAC_REG_W8(R_AX_XTAL_ON_CTRL2, val8);
return MACSUCCESS;
}
u32 set_partial_pld_mode(struct mac_ax_adapter *adapter, u8 enable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
if (enable) {
val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL);
val32 |= B_AX_TX_PARTIAL_MODE;
MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32);
} else {
val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL);
val32 &= ~B_AX_TX_PARTIAL_MODE;
MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32);
}
return MACSUCCESS;
}
u32 set_nav_padding(struct mac_ax_adapter *adapter,
struct mac_ax_nav_padding *nav)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg_txop = nav->band ? R_AX_PROT_0_C1 : R_AX_PROT_0;
u32 reg_cnt = nav->band ? R_AX_PROT_C1 : R_AX_PROT;
u32 ret;
u8 val8;
#if MAC_AX_FW_REG_OFLD
u16 tmp;
#endif
ret = check_mac_en(adapter, nav->band, MAC_AX_CMAC_SEL);
if (ret)
return ret;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
tmp = nav->nav_pad_en ? nav->nav_padding : 0;
ret = MAC_REG_W16_OFLD((u16)reg_txop,
tmp, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W16_OFLD((u16)reg_cnt,
tmp, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
ret = MAC_REG_W_OFLD((u16)reg_cnt, B_AX_NAV_OVER_TXOP_EN,
nav->over_txop_en ? 1 : 0, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
return MACSUCCESS;
}
#endif
if (nav->nav_pad_en) {
MAC_REG_W16(reg_txop, nav->nav_padding);
MAC_REG_W16(reg_cnt, nav->nav_padding);
val8 = MAC_REG_R8(reg_cnt + 2);
if (nav->over_txop_en)
val8 |= BIT(0);
else
val8 &= ~BIT(0);
MAC_REG_W8(reg_cnt + 2, val8);
} else {
MAC_REG_W16(reg_txop, 0);
MAC_REG_W16(reg_cnt, 0);
}
return MACSUCCESS;
}
static void set_delay_tx_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_delay_tx_cfg *cfg)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_SS_CTRL);
SET_CLR_WORD(val32, cfg->en, B_AX_SS_DELAY_TX_BAND_SEL);
MAC_REG_W32(R_AX_SS_CTRL, val32);
val32 = SET_WORD(cfg->vovi_to_b0, B_AX_SS_VOVI_TO_0) |
SET_WORD(cfg->bebk_to_b0, B_AX_SS_BEBK_TO_0) |
SET_WORD(cfg->vovi_to_b1, B_AX_SS_VOVI_TO_1) |
SET_WORD(cfg->bebk_to_b1, B_AX_SS_BEBK_TO_1);
MAC_REG_W32(R_AX_SS_DELAYTX_TO, val32);
val32 = SET_WORD(cfg->vovi_len_b0, B_AX_SS_VOVI_LEN_THR_0) |
SET_WORD(cfg->bebk_len_b0, B_AX_SS_BEBK_LEN_THR_0) |
SET_WORD(cfg->vovi_len_b1, B_AX_SS_VOVI_LEN_THR_1) |
SET_WORD(cfg->bebk_len_b1, B_AX_SS_BEBK_LEN_THR_1);
MAC_REG_W32(R_AX_SS_DELAYTX_LEN_THR, val32);
}
u32 set_core_swr_volt(struct mac_ax_adapter *adapter,
enum mac_ax_core_swr_volt volt_sel)
{
u8 i, j, adjust = 0;
s8 sign = 0, v, val8;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val8 = adapter->hw_info->core_swr_volt_sel - volt_sel;
if (val8 == 0) {
return MACSUCCESS;
} else if (val8 > 0) {
adjust = adapter->hw_info->core_swr_volt_sel - volt_sel;
sign = -1;
} else {
adjust = volt_sel - adapter->hw_info->core_swr_volt_sel;
sign = 1;
}
for (i = 0; i < adjust; i++) {
val8 = MAC_REG_R8(R_AX_SPSLDO_ON_CTRL0);
v = GET_FIELD(val8, B_AX_VOL_L1);
v += sign;
if (v < CORE_SWR_VOLT_MIN)
v = CORE_SWR_VOLT_MIN;
else if (v > CORE_SWR_VOLT_MAX)
v = CORE_SWR_VOLT_MAX;
val8 = SET_CLR_WORD(val8, v, B_AX_VOL_L1);
MAC_REG_W8(R_AX_SPSLDO_ON_CTRL0, val8);
for (j = 0; j < POLL_SWR_VOLT_CNT; j++)
PLTFM_DELAY_US(POLL_SWR_VOLT_US);
}
if (volt_sel == MAC_AX_SWR_NORM) {
val8 = MAC_REG_R8(R_AX_SPSLDO_ON_CTRL0);
val8 = SET_CLR_WORD(val8, adapter->hw_info->core_swr_volt,
B_AX_VOL_L1);
MAC_REG_W8(R_AX_SPSLDO_ON_CTRL0, val8);
}
adapter->hw_info->core_swr_volt_sel = volt_sel;
return MACSUCCESS;
}
u32 set_macid_pause(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_cfg *cfg)
{
u32 val32;
u8 macid_sh = cfg->macid & (32 - 1);
u8 macid_grp = cfg->macid >> 5;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
struct mac_ax_macid_pause_grp grp = {{0}};
ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
if (ret)
return ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
if (cfg->pause) {
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_0);
MAC_REG_W32(R_AX_MACID_SLEEP_0,
val32 | BIT(macid_sh));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_0,
val32 | BIT(macid_sh));
break;
case 1:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_1);
MAC_REG_W32(R_AX_MACID_SLEEP_1,
val32 | BIT(macid_sh));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_1,
val32 | BIT(macid_sh));
break;
case 2:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_2);
MAC_REG_W32(R_AX_MACID_SLEEP_2,
val32 | BIT(macid_sh));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_2,
val32 | BIT(macid_sh));
break;
case 3:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_3);
MAC_REG_W32(R_AX_MACID_SLEEP_3,
val32 | BIT(macid_sh));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_3,
val32 | BIT(macid_sh));
break;
default:
break;
}
} else {
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_0);
MAC_REG_W32(R_AX_MACID_SLEEP_0,
val32 & ~(BIT(macid_sh)));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_0,
val32 & ~(BIT(macid_sh)));
break;
case 1:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_1);
MAC_REG_W32(R_AX_MACID_SLEEP_1,
val32 & ~(BIT(macid_sh)));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_1,
val32 & ~(BIT(macid_sh)));
break;
case 2:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_2);
MAC_REG_W32(R_AX_MACID_SLEEP_2,
val32 & ~(BIT(macid_sh)));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_2,
val32 & ~(BIT(macid_sh)));
break;
case 3:
val32 = MAC_REG_R32(R_AX_MACID_SLEEP_3);
MAC_REG_W32(R_AX_MACID_SLEEP_3,
val32 & ~(BIT(macid_sh)));
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3);
MAC_REG_W32(R_AX_SS_MACID_PAUSE_3,
val32 & ~(BIT(macid_sh)));
break;
default:
break;
}
}
} else {
grp.mask_grp[macid_grp] = BIT(macid_sh);
grp.pause_grp[macid_grp] = cfg->pause << macid_sh;
ret = macid_pause(adapter, &grp);
if (ret)
return ret;
}
return MACSUCCESS;
}
u32 macid_pause(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_grp *grp)
{
u32 ret, size;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
if (ret)
return ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY)
return MACNOFW;
size = sizeof(struct mac_ax_macid_pause_grp);
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, size);
if (!buf) {
ret = MACNOBUF;
goto fail;
}
PLTFM_MEMCPY(buf, grp, size);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD, FWCMD_H2C_FUNC_MACID_PAUSE,
1, 0);
if (ret)
goto fail;
// return MACSUCCESS if h2c aggregation is enabled and enqueued successfully.
// H2C shall be sent by mac_h2c_agg_tx.
ret = h2c_agg_enqueue(adapter, h2cb);
if (ret == MACSUCCESS)
return MACSUCCESS;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]platform tx\n");
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 set_ss_quota_mode(struct mac_ax_adapter *adapter,
struct mac_ax_ss_quota_mode_ctrl *ctrl)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32_wmm, val32_ul, ret;
val32_wmm = MAC_REG_R32(R_AX_SS_DL_QUOTA_CTRL);
val32_ul = MAC_REG_R32(R_AX_SS_UL_QUOTA_CTRL);
switch (ctrl->wmm) {
case MAC_AX_SS_WMM0:
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT)
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm | B_AX_SS_QUOTA_MODE_0);
else
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm & ~B_AX_SS_QUOTA_MODE_0);
break;
case MAC_AX_SS_WMM1:
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT)
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm | B_AX_SS_QUOTA_MODE_1);
else
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm & ~B_AX_SS_QUOTA_MODE_1);
break;
case MAC_AX_SS_WMM2:
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT)
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm | B_AX_SS_QUOTA_MODE_2);
else
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm & ~B_AX_SS_QUOTA_MODE_2);
break;
case MAC_AX_SS_WMM3:
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT)
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm | B_AX_SS_QUOTA_MODE_3);
else
MAC_REG_W32(R_AX_SS_DL_QUOTA_CTRL,
val32_wmm & ~B_AX_SS_QUOTA_MODE_3);
break;
case MAC_AX_SS_UL:
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_CNT)
MAC_REG_W32(R_AX_SS_UL_QUOTA_CTRL,
val32_ul | B_AX_SS_QUOTA_MODE_UL);
else
MAC_REG_W32(R_AX_SS_UL_QUOTA_CTRL,
val32_ul & ~B_AX_SS_QUOTA_MODE_UL);
break;
}
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
switch (ctrl->wmm) {
case MAC_AX_SS_WMM0:
case MAC_AX_SS_WMM1:
case MAC_AX_SS_UL:
ret = check_mac_en(adapter, 0, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME) {
MAC_REG_W_OFLD(R_AX_PTCL_ATM,
B_AX_ATM_AIRTIME_EN, 1, 1);
}
break;
case MAC_AX_SS_WMM2:
case MAC_AX_SS_WMM3:
ret = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME) {
MAC_REG_W_OFLD(R_AX_PTCL_ATM_C1,
B_AX_ATM_AIRTIME_EN, 1, 1);
}
break;
}
return MACSUCCESS;
}
#endif
switch (ctrl->wmm) {
case MAC_AX_SS_WMM0:
case MAC_AX_SS_WMM1:
case MAC_AX_SS_UL:
ret = check_mac_en(adapter, 0, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32_wmm = MAC_REG_R32(R_AX_PTCL_ATM);
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME)
MAC_REG_W32(R_AX_PTCL_ATM,
val32_wmm | B_AX_ATM_AIRTIME_EN);
break;
case MAC_AX_SS_WMM2:
case MAC_AX_SS_WMM3:
ret = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS)
return ret;
val32_wmm = MAC_REG_R32(R_AX_PTCL_ATM_C1);
if (ctrl->mode == MAC_AX_SS_QUOTA_MODE_TIME)
MAC_REG_W32(R_AX_PTCL_ATM_C1,
val32_wmm | B_AX_ATM_AIRTIME_EN);
break;
}
return MACSUCCESS;
}
u32 ss_set_quotasetting(struct mac_ax_adapter *adapter,
struct mac_ax_ss_quota_setting *para)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 cnt = 1000;
if (para->ul_dl == mac_ax_issue_ul) {
val32 = (B_AX_SS_OWN |
SET_WORD(SS_W_QUOTA_SETTING, B_AX_SS_CMD_SEL) |
BIT(23) | SET_WORD(para->val, B_AX_SS_VALUE) |
para->macid);
MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, val32);
} else {
val32 = (B_AX_SS_OWN |
SET_WORD(SS_W_QUOTA_SETTING, B_AX_SS_CMD_SEL) |
SET_WORD(para->ac_type, B_AX_SS_AC) |
SET_WORD(para->val, B_AX_SS_VALUE) | para->macid);
MAC_REG_W32(R_AX_SS_SRAM_CTRL_1, val32);
}
while (--cnt) {
val32 = MAC_REG_R32(R_AX_SS_SRAM_CTRL_1);
if ((val32 & B_AX_SS_OWN) == 0)
break;
PLTFM_DELAY_US(1);
}
if (!cnt) {
PLTFM_MSG_ERR("SS Set quota setting fail!!\n");
return MACPOLLTO;
}
return MACSUCCESS;
}
u32 scheduler_set_prebkf(struct mac_ax_adapter *adapter,
struct mac_ax_prebkf_setting *para)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg, val32;
#if MAC_AX_FW_REG_OFLD
u32 ret;
#endif
reg = para->band == MAC_AX_BAND_1 ? R_AX_PREBKF_CFG_0_C1 :
R_AX_PREBKF_CFG_0;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)reg, B_AX_PREBKF_TIME_MSK, para->val,
1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
return MACSUCCESS;
}
#endif
val32 = MAC_REG_R32(reg);
val32 = SET_CLR_WORD(val32, para->val, B_AX_PREBKF_TIME);
MAC_REG_W32(reg, val32);
return MACSUCCESS;
}
u32 mac_get_tx_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_tx_cnt *cnt)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 txcnt_addr;
u32 val32;
u16 val16;
u8 sel;
if (cnt->band != 0 && cnt->band != 1)
return MACNOITEM;
if (check_mac_en(adapter, cnt->band, MAC_AX_CMAC_SEL))
return MACHWNOTEN;
txcnt_addr = (cnt->band == MAC_AX_BAND_0) ?
R_AX_TX_PPDU_CNT : R_AX_TX_PPDU_CNT_C1;
for (sel = 0; sel < MAC_AX_TX_ALLTYPE; sel++) {
val16 = MAC_REG_R16(txcnt_addr);
val16 = SET_CLR_WORD(val16, sel, B_AX_PPDU_CNT_IDX);
MAC_REG_W16(txcnt_addr, val16);
PLTFM_DELAY_US(1000);
val32 = MAC_REG_R32(txcnt_addr);
cnt->txcnt[sel] = GET_FIELD(val32, B_AX_TX_PPDU_CNT);
}
return MACSUCCESS;
}
u32 cfg_wdt_isr_rst(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
val = val & ~B_AX_APB_WRAP_EN;
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val);
val = val | B_AX_APB_WRAP_EN;
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val);
return MACSUCCESS;
}
u32 mac_clr_tx_cnt(struct mac_ax_adapter *adapter,
struct mac_ax_tx_cnt *cnt)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u16 txcnt_addr;
u16 val16;
u16 to;
u8 i;
if (cnt->band != 0 && cnt->band != 1)
return MACNOITEM;
if (check_mac_en(adapter, cnt->band, MAC_AX_CMAC_SEL))
return MACHWNOTEN;
if (cnt->sel > MAC_AX_TX_ALLTYPE)
return MACNOITEM;
txcnt_addr = (cnt->band == MAC_AX_BAND_0) ?
R_AX_TX_PPDU_CNT : R_AX_TX_PPDU_CNT_C1;
#if MAC_AX_FW_REG_OFLD
u32 ret;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
for (i = 0; i < MAC_AX_TX_ALLTYPE; i++) {
if (cnt->sel == MAC_AX_TX_ALLTYPE || i == cnt->sel) {
ret = MAC_REG_W_OFLD(txcnt_addr,
B_AX_PPDU_CNT_RIDX_MSK <<
B_AX_PPDU_CNT_RIDX_SH,
i, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, txcnt_addr, ret);
return ret;
}
ret = MAC_REG_W_OFLD(txcnt_addr, B_AX_RST_PPDU_CNT,
1, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, txcnt_addr, ret);
return ret;
}
ret = MAC_REG_P_OFLD(txcnt_addr, B_AX_RST_PPDU_CNT, 0,
(cnt->sel != MAC_AX_TX_ALLTYPE ||
i == MAC_AX_TX_ALLTYPE - 1) ?
1 : 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: poll offload fail;"
"offset: %u, ret: %u\n",
__func__, txcnt_addr, ret);
return ret;
}
}
}
return MACSUCCESS;
}
#endif
to = 1000;
for (i = 0; i < MAC_AX_TX_ALLTYPE; i++) {
if (cnt->sel == MAC_AX_TX_ALLTYPE || i == cnt->sel) {
val16 = MAC_REG_R16(txcnt_addr);
val16 = SET_CLR_WORD(val16, i, B_AX_PPDU_CNT_RIDX) |
B_AX_RST_PPDU_CNT;
MAC_REG_W16(txcnt_addr, val16);
while (to--) {
val16 = MAC_REG_R16(txcnt_addr);
if (!(val16 & B_AX_RST_PPDU_CNT))
break;
PLTFM_DELAY_US(5);
}
if (to == 0)
return MACPOLLTO;
}
}
return MACSUCCESS;
}
u32 mac_set_hw_value(struct mac_ax_adapter *adapter,
enum mac_ax_hw_id hw_id, void *val)
{
u32 ret = MACSUCCESS;
if (!val) {
PLTFM_MSG_ERR("[ERR]: the parameter is NULL in %s\n", __func__);
return MACNPTR;
}
switch (hw_id) {
case MAC_AX_HW_SETTING:
break;
case MAC_AX_HW_SET_ID_PAUSE:
ret = set_macid_pause(adapter,
(struct mac_ax_macid_pause_cfg *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_SET_MULTI_ID_PAUSE:
ret = macid_pause(adapter,
(struct mac_ax_macid_pause_grp *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_SET_SCH_TXEN_CFG:
ret = set_hw_sch_tx_en(adapter,
(struct mac_ax_sch_tx_en_cfg *)val);
break;
case MAC_AX_HW_SET_AMPDU_CFG:
ret = set_hw_ampdu_cfg(adapter, (struct mac_ax_ampdu_cfg *)val);
break;
case MAC_AX_HW_SET_USR_EDCA_PARAM:
ret =
set_hw_usr_edca_param(adapter,
(struct mac_ax_usr_edca_param *)val);
break;
case MAC_AX_HW_SET_USR_TX_RPT_CFG:
ret =
set_hw_usr_tx_rpt_cfg(adapter,
(struct mac_ax_usr_tx_rpt_cfg *)val);
break;
case MAC_AX_HW_SET_EDCA_PARAM:
ret = set_hw_edca_param(adapter,
(struct mac_ax_edca_param *)val);
break;
case MAC_AX_HW_SET_EDCCA_PARAM:
ret = set_hw_edcca_param(adapter,
(struct mac_ax_edcca_param *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_SET_MUEDCA_PARAM:
ret = set_hw_muedca_param(adapter,
(struct mac_ax_muedca_param *)val);
break;
case MAC_AX_HW_SET_MUEDCA_CTRL:
ret = set_hw_muedca_ctrl(adapter,
(struct mac_ax_muedca_cfg *)val);
break;
case MAC_AX_HW_SET_TBPPDU_CTRL:
ret = set_hw_tb_ppdu_ctrl(adapter,
(struct mac_ax_tb_ppdu_ctrl *)val);
break;
case MAC_AX_HW_SET_HOST_RPR:
set_host_rpr(adapter, (struct mac_ax_host_rpr_cfg *)val);
break;
case MAC_AX_HW_SET_DELAYTX_CFG:
set_delay_tx_cfg(adapter, (struct mac_ax_delay_tx_cfg *)val);
break;
case MAC_AX_HW_SET_BW_CFG:
ret = cfg_mac_bw(adapter, (struct mac_ax_cfg_bw *)val);
break;
case MAC_AX_HW_SET_CH_BUSY_STAT_CFG:
ret = set_hw_ch_busy_cnt(adapter,
(struct mac_ax_ch_busy_cnt_cfg *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_SET_LIFETIME_CFG:
ret = set_hw_lifetime_cfg(adapter,
(struct mac_ax_lifetime_cfg *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_EN_BB_RF:
ret = set_enable_bb_rf(adapter, *(u8 *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_SET_APP_FCS:
set_append_fcs(adapter, *(u8 *)val);
break;
case MAC_AX_HW_SET_RX_ICVERR:
set_accept_icverr(adapter, *(u8 *)val);
break;
case MAC_AX_HW_SET_CCTL_RTY_LMT:
set_cctl_rty_limit(adapter,
(struct mac_ax_cctl_rty_lmt_cfg *)val);
break;
case MAC_AX_HW_SET_COEX_GNT:
ret = mac_cfg_gnt(adapter, (struct mac_ax_coex_gnt *)val);
break;
case MAC_AX_HW_SET_SCOREBOARD:
mac_cfg_sb(adapter, *(u32 *)val);
break;
case MAC_AX_HW_SET_POLLUTED:
mac_cfg_plt(adapter, (struct mac_ax_plt *)val);
break;
case MAC_AX_HW_SET_COEX_CTRL:
mac_cfg_ctrl_path(adapter, *(u32 *)val);
break;
case MAC_AX_HW_SET_CLR_TX_CNT:
ret = mac_clr_tx_cnt(adapter, (struct mac_ax_tx_cnt *)val);
break;
case MAC_AX_HW_SET_SLOT_TIME:
mac_set_slot_time(adapter, *(enum mac_ax_slot_time *)val);
break;
case MAC_AX_HW_SET_XTAL_AAC_MODE:
set_xtal_aac(adapter, *(u8 *)val);
break;
case MAC_AX_HW_SET_NAV_PADDING:
ret = set_nav_padding(adapter, (struct mac_ax_nav_padding *)val);
break;
case MAC_AX_HW_SET_MAX_TX_TIME:
ret = mac_set_cctl_max_tx_time(adapter,
(struct mac_ax_max_tx_time *)
val);
break;
case MAC_AX_HW_SET_SS_QUOTA_MODE:
ret = set_ss_quota_mode(adapter,
(struct mac_ax_ss_quota_mode_ctrl *)val);
break;
case MAC_AX_HW_SET_SS_QUOTA_SETTING:
ret = ss_set_quotasetting(adapter,
(struct mac_ax_ss_quota_setting *)val);
break;
case MAC_AX_HW_SET_SCHE_PREBKF:
ret = scheduler_set_prebkf(adapter,
(struct mac_ax_prebkf_setting *)val);
break;
case MAC_AX_HW_SET_WDT_ISR_RST:
ret = cfg_wdt_isr_rst(adapter);
break;
case MAC_AX_HW_SET_RESP_ACK:
ret = set_mac_resp_ack(adapter, (u32 *)val);
break;
case MAC_AX_HW_SET_HW_RTS_TH:
ret = mac_set_hw_rts_th(adapter,
(struct mac_ax_hw_rts_th *)val);
break;
case MAC_AX_HW_SET_TX_RU26_TB:
ret = mac_set_tx_ru26_tb(adapter, *(u8 *)val);
break;
case MAC_AX_HW_SET_BACAM_MODE_SEL:
ret = set_bacam_mode(adapter, *(u8 *)val);
break;
case MAC_AX_HW_SET_CORE_SWR_VOLT:
ret = set_core_swr_volt(adapter,
*(enum mac_ax_core_swr_volt *)val);
break;
case MAC_AX_HW_SET_PARTIAL_PLD_MODE:
ret = set_partial_pld_mode(adapter, *(u8 *)val);
break;
case MAC_AX_HW_SET_RRSR_CFG:
ret = mac_set_rrsr_cfg(adapter,
(struct mac_ax_rrsr_cfg *)val);
break;
case MAC_AX_HW_SET_CTS_RRSR_CFG:
ret = mac_set_cts_rrsr_cfg(adapter,
(struct mac_ax_cts_rrsr_cfg *)val);
break;
case MAC_AX_HW_SET_GT3_TIMER:
ret = set_gt3_timer(adapter,
(struct mac_ax_gt3_cfg *)val);
break;
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_HW_SDIO_INFO:
set_info_sdio(adapter, (struct mac_ax_sdio_info *)val);
break;
case MAC_AX_HW_SDIO_TX_MODE:
ret = tx_mode_cfg_sdio(adapter,
*(enum mac_ax_sdio_tx_mode *)val);
break;
case MAC_AX_HW_SDIO_RX_AGG:
rx_agg_cfg_sdio(adapter, (struct mac_ax_rx_agg_cfg *)val);
break;
case MAC_AX_HW_SDIO_TX_AGG:
ret = tx_agg_cfg_sdio(adapter,
(struct mac_ax_sdio_txagg_cfg *)val);
break;
case MAC_AX_HW_SDIO_AVAL_PAGE:
aval_page_cfg_sdio(adapter, (struct mac_ax_aval_page_cfg *)val);
break;
case MAC_AX_HW_SDIO_MON_WT:
set_wt_cfg_sdio(adapter, *(u8 *)val);
break;
#endif
#if MAC_AX_PCIE_SUPPORT
case MAC_AX_HW_PCIE_CFGSPC_SET:
ret = cfgspc_set_pcie(adapter,
(struct mac_ax_pcie_cfgspc_param *)val);
break;
case MAC_AX_HW_PCIE_RST_BDRAM:
ret = rst_bdram_pcie(adapter, *(u8 *)val);
break;
case MAX_AX_HW_PCIE_LTR_SW_TRIGGER:
ret = ltr_sw_trigger(adapter,
*(enum mac_ax_pcie_ltr_sw_ctrl *)val);
break;
case MAX_AX_HW_PCIE_MIT:
ret = pcie_trx_mit(adapter,
(struct mac_ax_pcie_trx_mitigation *)val);
break;
case MAX_AX_HW_PCIE_L2_LEAVE:
ret = set_pcie_l2_leave(adapter, *(u8 *)val);
break;
#endif
default:
return MACNOITEM;
}
return ret;
}
u32 get_macid_pause(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_cfg *cfg)
{
u32 val32 = 0;
u8 macid_grp = cfg->macid >> 5;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
if (ret)
return ret;
switch (macid_grp) {
case 0:
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_0) |
MAC_REG_R32(R_AX_MACID_SLEEP_0);
break;
case 1:
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_1) |
MAC_REG_R32(R_AX_MACID_SLEEP_1);
break;
case 2:
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_2) |
MAC_REG_R32(R_AX_MACID_SLEEP_2);
break;
case 3:
val32 = MAC_REG_R32(R_AX_SS_MACID_PAUSE_3) |
MAC_REG_R32(R_AX_MACID_SLEEP_3);
break;
default:
break;
}
cfg->pause = (u8)((val32 & BIT(cfg->macid & (32 - 1))) ? 1 : 0);
return MACSUCCESS;
}
u32 get_ss_wmm_tbl(struct mac_ax_adapter *adapter,
struct mac_ax_ss_wmm_tbl_ctrl *ctrl)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_SS_CTRL);
switch (ctrl->wmm) {
case 0:
ctrl->wmm_mapping =
(enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_0);
break;
case 1:
ctrl->wmm_mapping =
(enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_1);
break;
case 2:
ctrl->wmm_mapping =
(enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_2);
break;
case 3:
ctrl->wmm_mapping =
(enum mac_ax_ss_wmm_tbl)GET_FIELD(val32, B_AX_SS_WMM_SEL_3);
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
static void get_delay_tx_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_delay_tx_cfg *cfg)
{
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
val32 = MAC_REG_R32(R_AX_SS_CTRL);
cfg->en =
(enum mac_ax_delay_tx_en)GET_FIELD(val32,
B_AX_SS_DELAY_TX_BAND_SEL);
val32 = MAC_REG_R32(R_AX_SS_DELAYTX_TO);
cfg->vovi_to_b0 = GET_FIELD(val32, B_AX_SS_VOVI_TO_0);
cfg->bebk_to_b0 = GET_FIELD(val32, B_AX_SS_BEBK_TO_0);
cfg->vovi_to_b1 = GET_FIELD(val32, B_AX_SS_VOVI_TO_1);
cfg->bebk_to_b1 = GET_FIELD(val32, B_AX_SS_BEBK_TO_1);
val32 = MAC_REG_R32(R_AX_SS_DELAYTX_LEN_THR);
cfg->vovi_len_b0 = GET_FIELD(val32, B_AX_SS_VOVI_LEN_THR_0);
cfg->bebk_len_b0 = GET_FIELD(val32, B_AX_SS_BEBK_LEN_THR_0);
cfg->vovi_len_b1 = GET_FIELD(val32, B_AX_SS_VOVI_LEN_THR_1);
cfg->bebk_len_b1 = GET_FIELD(val32, B_AX_SS_BEBK_LEN_THR_1);
}
static u32 get_append_fcs(struct mac_ax_adapter *adapter, u8 *enable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
*enable = MAC_REG_R8(R_AX_MPDU_PROC) & B_AX_APPEND_FCS ? 1 : 0;
return MACSUCCESS;
}
static u32 get_accept_icverr(struct mac_ax_adapter *adapter, u8 *enable)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
*enable = MAC_REG_R8(R_AX_MPDU_PROC) & B_AX_A_ICV_ERR ? 1 : 0;
return MACSUCCESS;
}
u32 get_bacam_mode(struct mac_ax_adapter *adapter, u8 *mode_sel)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
*mode_sel = MAC_REG_R8(R_AX_RESPBA_CAM_CTRL) & B_AX_BACAM_ENT_CFG ? 1 : 0;
return MACSUCCESS;
}
u32 get_pwr_state(struct mac_ax_adapter *adapter, enum mac_ax_mac_pwr_st *st)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val;
val = GET_FIELD(MAC_REG_R32(R_AX_IC_PWR_STATE), B_AX_WLMAC_PWR_STE);
if (val == MAC_AX_MAC_OFF) {
*st = MAC_AX_MAC_OFF;
adapter->mac_pwr_info.pwr_in_lps = 0;
adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE;
adapter->sm.pwr = MAC_AX_PWR_OFF;
adapter->sm.mac_rdy = MAC_AX_MAC_NOT_RDY;
PLTFM_MSG_WARN("WL MAC is in off state.\n");
} else if (val == MAC_AX_MAC_ON) {
*st = MAC_AX_MAC_ON;
} else if (val == MAC_AX_MAC_LPS) {
*st = MAC_AX_MAC_LPS;
} else {
PLTFM_MSG_ERR("Unexpected MAC state = 0x%X\n", val);
return MACPWRSTAT;
}
return MACSUCCESS;
}
void get_dflt_nav(struct mac_ax_adapter *adapter, u16 *nav)
{
/* data NAV is consist of SIFS and ACK/BA time */
/* currently, we use SIFS + 64-bitmap BA as default NAV */
/* we use OFDM-6M to estimate BA time */
/* BA time = PLCP header(20us) + 32 bytes/data_rate */
*nav = 63;
}
u32 mac_get_hw_value(struct mac_ax_adapter *adapter,
enum mac_ax_hw_id hw_id, void *val)
{
u32 ret = MACSUCCESS;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (!val) {
PLTFM_MSG_ERR("[ERR]: the parameter is NULL in %s\n", __func__);
return MACNPTR;
}
switch (hw_id) {
case MAC_AX_HW_MAPPING:
break;
case MAC_AX_HW_GET_EFUSE_SIZE:
*(u32 *)val = adapter->hw_info->efuse_size +
adapter->hw_info->dav_efuse_size;
break;
case MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE:
*(u32 *)val = adapter->hw_info->log_efuse_size +
adapter->hw_info->dav_log_efuse_size;
break;
case MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE:
switch (adapter->hw_info->intf) {
case MAC_AX_INTF_PCIE:
*(u32 *)val = adapter->hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
*(u32 *)val = adapter->hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
*(u32 *)val = adapter->hw_info->limit_efuse_size_sdio;
break;
default:
*(u32 *)val = adapter->hw_info->log_efuse_size;
break;
}
*(u32 *)val += adapter->hw_info->dav_log_efuse_size;
break;
case MAC_AX_HW_GET_BT_EFUSE_SIZE:
*(u32 *)val = adapter->hw_info->bt_efuse_size;
break;
case MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE:
*(u32 *)val = adapter->hw_info->bt_log_efuse_size;
break;
case MAC_AX_HW_GET_EFUSE_MASK_SIZE:
*(u32 *)val = (adapter->hw_info->log_efuse_size +
adapter->hw_info->dav_log_efuse_size) >> 4;
break;
case MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE:
switch (adapter->hw_info->intf) {
case MAC_AX_INTF_PCIE:
*(u32 *)val = adapter->hw_info->limit_efuse_size_pcie;
break;
case MAC_AX_INTF_USB:
*(u32 *)val = adapter->hw_info->limit_efuse_size_usb;
break;
case MAC_AX_INTF_SDIO:
*(u32 *)val = adapter->hw_info->limit_efuse_size_sdio;
break;
default:
*(u32 *)val = adapter->hw_info->log_efuse_size;
break;
}
*(u32 *)val += adapter->hw_info->dav_log_efuse_size;
*(u32 *)val = *(u32 *)val >> 4;
break;
case MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE:
*(u32 *)val = adapter->hw_info->bt_log_efuse_size >> 4;
break;
case MAC_AX_HW_GET_EFUSE_VERSION_SIZE:
*(u32 *)val = adapter->hw_info->efuse_version_size;
break;
case MAC_AX_HW_GET_ID_PAUSE:
ret = get_macid_pause(adapter,
(struct mac_ax_macid_pause_cfg *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_SCH_TXEN_STATUS:
ret = get_hw_sch_tx_en(adapter,
(struct mac_ax_sch_tx_en_cfg *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_EDCA_PARAM:
ret = get_hw_edca_param(adapter,
(struct mac_ax_edca_param *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_TBPPDU_CTRL:
ret = get_hw_tb_ppdu_ctrl(adapter,
(struct mac_ax_tb_ppdu_ctrl *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_DELAYTX_CFG:
get_delay_tx_cfg(adapter, (struct mac_ax_delay_tx_cfg *)val);
break;
case MAC_AX_HW_GET_SS_WMM_TBL:
ret = get_ss_wmm_tbl(adapter,
(struct mac_ax_ss_wmm_tbl_ctrl *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_CH_STAT_CNT:
ret = get_hw_ch_stat_cnt(adapter,
(struct mac_ax_ch_stat_cnt *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_LIFETIME_CFG:
ret = get_hw_lifetime_cfg(adapter,
(struct mac_ax_lifetime_cfg *)val);
if (ret != MACSUCCESS)
return ret;
break;
case MAC_AX_HW_GET_APP_FCS:
get_append_fcs(adapter, (u8 *)val);
break;
case MAC_AX_HW_GET_RX_ICVERR:
get_accept_icverr(adapter, (u8 *)val);
break;
case MAC_AX_HW_GET_PWR_STATE:
get_pwr_state(adapter, (enum mac_ax_mac_pwr_st *)val);
break;
case MAC_AX_HW_GET_SCOREBOARD:
*(u32 *)val = MAC_REG_R32(R_AX_SCOREBOARD);
break;
case MAC_AX_HW_GET_BACAM_MODE_SEL:
get_bacam_mode(adapter, (u8 *)val);
break;
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_HW_SDIO_TX_AGG_SIZE:
*(u16 *)val = adapter->sdio_info.tx_align_size;
break;
#endif
case MAC_AX_HW_GET_WAKE_REASON:
ret = get_wake_reason(adapter, (u8 *)val);
if (ret != 0)
return ret;
break;
case MAC_AX_HW_GET_COEX_GNT:
ret = mac_get_gnt(adapter, (struct mac_ax_coex_gnt *)val);
break;
case MAC_AX_HW_GET_COEX_CTRL:
mac_get_ctrl_path(adapter, (u32 *)val);
break;
case MAC_AX_HW_GET_TX_CNT:
ret = mac_get_tx_cnt(adapter, (struct mac_ax_tx_cnt *)val);
if (ret != 0)
return ret;
break;
case MAC_AX_HW_GET_TSF:
mac_get_tsf(adapter, (struct mac_ax_port_tsf *)val);
break;
case MAC_AX_HW_GET_MAX_TX_TIME:
ret = mac_get_max_tx_time(adapter,
(struct mac_ax_max_tx_time *)val);
break;
case MAC_AX_HW_GET_POLLUTED_CNT:
mac_get_bt_polt_cnt(adapter, (struct mac_ax_bt_polt_cnt *)val);
break;
case MAC_AX_HW_GET_DATA_RTY_LMT:
get_data_rty_limit(adapter, (struct mac_ax_rty_lmt *)val);
break;
case MAC_AX_HW_GET_DFLT_NAV:
get_dflt_nav(adapter, (u16 *)val);
break;
case MAC_AX_HW_GET_FW_CAP:
ret = mac_get_fw_cap(adapter, (u32 *)val);
break;
case MAC_AX_HW_GET_RRSR_CFG:
ret = mac_get_rrsr_cfg(adapter,
(struct mac_ax_rrsr_cfg *)val);
break;
case MAC_AX_HW_GET_CTS_RRSR_CFG:
ret = mac_get_cts_rrsr_cfg(adapter,
(struct mac_ax_cts_rrsr_cfg *)val);
break;
case MAC_AX_HW_GET_USB_STS:
ret = ops->get_rx_state(adapter, (u32 *)val);
break;
default:
return MACNOITEM;
}
return ret;
}
u32 cfg_mac_bw(struct mac_ax_adapter *adapter, struct mac_ax_cfg_bw *cfg)
{
u32 value32 = 0;
u8 value8 = 0;
u8 chk_val8 = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct rtw_hal_com_t *hal_com =
(struct rtw_hal_com_t *)adapter->drv_adapter;
u8 txsc20 = 0, txsc40 = 0, txsc80 = 0;
switch (cfg->cbw) {
case CHANNEL_WIDTH_160:
txsc80 = rtw_hal_bb_get_txsc(hal_com, cfg->pri_ch,
cfg->central_ch, cfg->cbw,
CHANNEL_WIDTH_80);
/* fall through */
case CHANNEL_WIDTH_80:
txsc40 = rtw_hal_bb_get_txsc(hal_com, cfg->pri_ch,
cfg->central_ch, cfg->cbw,
CHANNEL_WIDTH_40);
/* fall through */
case CHANNEL_WIDTH_40:
txsc20 = rtw_hal_bb_get_txsc(hal_com, cfg->pri_ch,
cfg->central_ch, cfg->cbw,
CHANNEL_WIDTH_20);
break;
default:
break;
}
#if MAC_AX_FW_REG_OFLD
u32 ret;
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
if (cfg->band) {//BAND1
value8 = MAC_REG_R8(R_AX_WMAC_RFMOD_C1);
chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK_C1);
} else {//BAND0
value8 = MAC_REG_R8(R_AX_WMAC_RFMOD);
chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK);
}
value8 = value8 & (~(BIT(0) | BIT(1)));
chk_val8 = chk_val8 & (~(BIT(0) | BIT(1)));
switch (cfg->cbw) {
case CHANNEL_WIDTH_160:
value8 = value8 | BIT(1) | BIT(0);
value32 = txsc20 | (txsc40 << 4) | (txsc80 << 8); //TXSC_160M;
break;
case CHANNEL_WIDTH_80:
value8 = value8 | BIT(1);
value32 = txsc20 | (txsc40 << 4); //TXSC_80M;
break;
case CHANNEL_WIDTH_40:
value8 = value8 | BIT(0);
value32 = txsc20; //TXSC_40M;
break;
case CHANNEL_WIDTH_20:
value32 = 0; //TXSC_20M;
break;
default:
break;
}
if (cfg->pri_ch >= CHANNEL_5G)
chk_val8 |= B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6;
if (cfg->band) {//BAND1
ret = MAC_REG_W_OFLD(R_AX_WMAC_RFMOD_C1, B_AX_WMAC_RFMOD_MSK,
value8, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_TXRATE_CHK_C1, 0x3, chk_val8,
0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
ret = MAC_REG_W32_OFLD(R_AX_TX_SUB_CARRIER_VALUE_C1,
value32, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
} else {
ret = MAC_REG_W_OFLD(R_AX_WMAC_RFMOD, B_AX_WMAC_RFMOD_MSK,
value8, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
ret = MAC_REG_W_OFLD(R_AX_TXRATE_CHK, 0x3, chk_val8, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
ret = MAC_REG_W32_OFLD(R_AX_TX_SUB_CARRIER_VALUE,
value32, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
}
return MACSUCCESS;
}
#endif
if (cfg->band) {//BAND1
value8 = MAC_REG_R8(R_AX_WMAC_RFMOD_C1);
chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK_C1);
} else {//BAND0
value8 = MAC_REG_R8(R_AX_WMAC_RFMOD);
chk_val8 = MAC_REG_R8(R_AX_TXRATE_CHK);
}
value8 = value8 & (~(BIT(0) | BIT(1)));
chk_val8 = chk_val8 & (~(BIT(0) | BIT(1)));
switch (cfg->cbw) {
case CHANNEL_WIDTH_160:
value8 = value8 | BIT(1) | BIT(0);
value32 = txsc20 | (txsc40 << 4) | (txsc80 << 8); //TXSC_160M;
break;
case CHANNEL_WIDTH_80:
value8 = value8 | BIT(1);
value32 = txsc20 | (txsc40 << 4); //TXSC_80M;
break;
case CHANNEL_WIDTH_40:
value8 = value8 | BIT(0);
value32 = txsc20; //TXSC_40M;
break;
case CHANNEL_WIDTH_20:
value32 = 0; //TXSC_20M;
break;
default:
break;
}
if (cfg->pri_ch >= CHANNEL_5G)
chk_val8 |= B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6;
if (cfg->band) {//BAND1
MAC_REG_W8(R_AX_WMAC_RFMOD_C1, value8);
MAC_REG_W8(R_AX_TXRATE_CHK_C1, chk_val8);
MAC_REG_W32(R_AX_TX_SUB_CARRIER_VALUE_C1, value32);
} else {
MAC_REG_W8(R_AX_WMAC_RFMOD, value8);
MAC_REG_W8(R_AX_TXRATE_CHK, chk_val8);
MAC_REG_W32(R_AX_TX_SUB_CARRIER_VALUE, value32);
}
return MACSUCCESS;
}
u32 mac_write_lte(struct mac_ax_adapter *adapter,
const u32 offset, u32 val)
{
u32 cnt;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FW_REG_OFLD
u32 ret;
if (adapter->sm.fwdl != MAC_AX_FWDL_INIT_RDY) {
cnt = 1000;
while ((MAC_REG_R8(R_AX_LTE_CTRL + 3) & BIT(5)) == 0) {
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]lte not ready(W)\n");
return MACPOLLTO;
}
cnt--;
PLTFM_DELAY_US(50);
}
PLTFM_MUTEX_LOCK(&adapter->hw_info->lte_rlock);
MAC_REG_W32(R_AX_LTE_WDATA, val);
MAC_REG_W32(R_AX_LTE_CTRL, 0xC00F0000 | offset);
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->lte_rlock);
} else {
ret = MAC_REG_P_OFLD(R_AX_LTE_CTRL, B_AX_LTE_RDY, 1, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_LTE_WDATA, val, 0);
if (ret != MACSUCCESS)
return ret;
ret = MAC_REG_W32_OFLD(R_AX_LTE_WDATA, 0xC00F0000 | offset, 1);
if (ret != MACSUCCESS)
return ret;
}
#else
cnt = 1000;
while ((MAC_REG_R8(R_AX_LTE_CTRL + 3) & BIT(5)) == 0) {
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]lte not ready(W)\n");
return MACPOLLTO;
}
cnt--;
PLTFM_DELAY_US(50);
}
PLTFM_MUTEX_LOCK(&adapter->hw_info->lte_rlock);
MAC_REG_W32(R_AX_LTE_WDATA, val);
MAC_REG_W32(R_AX_LTE_CTRL, 0xC00F0000 | offset);
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->lte_rlock);
#endif
return MACSUCCESS;
}
u32 mac_read_lte(struct mac_ax_adapter *adapter,
const u32 offset, u32 *val)
{
u32 cnt;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
cnt = 1000;
while ((MAC_REG_R8(R_AX_LTE_CTRL + 3) & BIT(5)) == 0) {
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]lte not ready(W)\n");
break;
}
cnt--;
PLTFM_DELAY_US(50);
}
PLTFM_MUTEX_LOCK(&adapter->hw_info->lte_rlock);
MAC_REG_W32(R_AX_LTE_CTRL, 0x800F0000 | offset);
*val = MAC_REG_R32(R_AX_LTE_RDATA);
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->lte_rlock);
return MACSUCCESS;
}
u32 mac_write_xtal_si(struct mac_ax_adapter *adapter,
u8 offset, u8 val, u8 bitmask)
{
u32 cnt = 0;
u32 write_val = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
cnt = XTAL_SI_POLLING_CNT;
write_val = SET_CLR_WORD(write_val, offset, B_AX_WL_XTAL_SI_ADDR);
write_val = SET_CLR_WORD(write_val, val, B_AX_WL_XTAL_SI_DATA);
write_val = SET_CLR_WORD(write_val, bitmask, B_AX_WL_XTAL_SI_BITMASK);
write_val = SET_CLR_WORD(write_val, XTAL_SI_NORMAL_WRITE,
B_AX_WL_XTAL_SI_MODE);
write_val = (write_val | B_AX_WL_XTAL_SI_CMD_POLL);
MAC_REG_W32(R_AX_WLAN_XTAL_SI_CTRL, write_val);
while ((MAC_REG_R32(R_AX_WLAN_XTAL_SI_CTRL) & B_AX_WL_XTAL_SI_CMD_POLL)
== B_AX_WL_XTAL_SI_CMD_POLL) {
if (!cnt) {
PLTFM_MSG_ERR("[ERR]xtal si not ready(W)\n");
return MACPOLLTO;
}
cnt--;
PLTFM_DELAY_US(XTAL_SI_POLLING_DLY_US);
}
return MACSUCCESS;
}
u32 mac_read_xtal_si(struct mac_ax_adapter *adapter,
u8 offset, u8 *val)
{
u32 cnt = 0;
u32 write_val = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
cnt = XTAL_SI_POLLING_CNT;
write_val = SET_CLR_WORD(write_val, offset, B_AX_WL_XTAL_SI_ADDR);
write_val = SET_CLR_WORD(write_val, 0x00, B_AX_WL_XTAL_SI_DATA);
write_val = SET_CLR_WORD(write_val, 0x00, B_AX_WL_XTAL_SI_BITMASK);
write_val = SET_CLR_WORD(write_val, XTAL_SI_NORMAL_READ,
B_AX_WL_XTAL_SI_MODE);
write_val = (write_val | B_AX_WL_XTAL_SI_CMD_POLL);
MAC_REG_W32(R_AX_WLAN_XTAL_SI_CTRL, write_val);
while ((MAC_REG_R32(R_AX_WLAN_XTAL_SI_CTRL) & B_AX_WL_XTAL_SI_CMD_POLL)
== B_AX_WL_XTAL_SI_CMD_POLL) {
if (!cnt) {
PLTFM_MSG_ERR("[ERR]xtal_si not ready(R)\n");
return MACPOLLTO;
}
cnt--;
PLTFM_DELAY_US(XTAL_SI_POLLING_DLY_US);
}
*val = MAC_REG_R8(R_AX_WLAN_XTAL_SI_CTRL + 1);
return MACSUCCESS;
}
u32 set_host_rpr(struct mac_ax_adapter *adapter,
struct mac_ax_host_rpr_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_host_rpr_cfg *def_cfg;
enum mac_ax_host_rpr_mode mode;
u8 is_poh;
u32 val32, nval32;
u32 ret = MACSUCCESS;
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
ret = is_qta_poh(adapter, adapter->dle_info.qta_mode, &is_poh);
if (ret) {
PLTFM_MSG_ERR("is qta poh check fail %d\n", ret);
return ret;
}
def_cfg = is_poh ? &rpr_cfg_poh : &rpr_cfg_stf;
mode = is_poh ? MAC_AX_RPR_MODE_POH : MAC_AX_RPR_MODE_STF;
} else {
def_cfg = &rpr_cfg_stf;
mode = MAC_AX_RPR_MODE_STF;
}
val32 = MAC_REG_R32(R_AX_WDRLS_CFG);
nval32 = SET_CLR_WORD(val32, mode, B_AX_WDRLS_MODE);
if (nval32 != val32)
MAC_REG_W32(R_AX_WDRLS_CFG, nval32);
val32 = MAC_REG_R32(R_AX_RLSRPT0_CFG0);
nval32 = val32;
if ((cfg->txok_en == MAC_AX_FUNC_DEF &&
def_cfg->txok_en == MAC_AX_FUNC_EN) ||
cfg->txok_en == MAC_AX_FUNC_EN)
nval32 |= B_WDRLS_FLTR_TXOK;
else
nval32 &= ~B_WDRLS_FLTR_TXOK;
if ((cfg->rty_lmt_en == MAC_AX_FUNC_DEF &&
def_cfg->rty_lmt_en == MAC_AX_FUNC_EN) ||
cfg->rty_lmt_en == MAC_AX_FUNC_EN)
nval32 |= B_WDRLS_FLTR_RTYLMT;
else
nval32 &= ~B_WDRLS_FLTR_RTYLMT;
if ((cfg->lft_drop_en == MAC_AX_FUNC_DEF &&
def_cfg->lft_drop_en == MAC_AX_FUNC_EN) ||
cfg->lft_drop_en == MAC_AX_FUNC_EN)
nval32 |= B_WDRLS_FLTR_LIFTIM;
else
nval32 &= ~B_WDRLS_FLTR_LIFTIM;
if ((cfg->macid_drop_en == MAC_AX_FUNC_DEF &&
def_cfg->macid_drop_en == MAC_AX_FUNC_EN) ||
cfg->macid_drop_en == MAC_AX_FUNC_EN)
nval32 |= B_WDRLS_FLTR_MACID;
else
nval32 &= ~B_WDRLS_FLTR_MACID;
if (nval32 != val32)
MAC_REG_W32(R_AX_RLSRPT0_CFG0, nval32);
val32 = MAC_REG_R32(R_AX_RLSRPT0_CFG1);
nval32 = SET_CLR_WORD(val32, (cfg->agg_def ? def_cfg->agg : cfg->agg),
B_AX_RLSRPT0_AGGNUM);
nval32 = SET_CLR_WORD(nval32, (cfg->tmr_def ? def_cfg->tmr : cfg->tmr),
B_AX_RLSRPT0_TO);
if (nval32 != val32)
MAC_REG_W32(R_AX_RLSRPT0_CFG1, nval32);
return ret;
}
u32 set_l2_status(struct mac_ax_adapter *adapter)
{
adapter->sm.l2_st = MAC_AX_L2_EN;
return MACSUCCESS;
}
u32 mac_write_pwr_ofst_mode(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu)
{
#if MAC_AX_FW_REG_OFLD
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_OFST_CTRL :
R_AX_PWR_RATE_OFST_CTRL_C1;
u32 val32 = 0;
u32 ret;
s8 *tmp = &tpu->pwr_ofst_mode[0];
val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]);
ret = MAC_REG_W_OFLD(cr, 0xFFFFF, val32, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
#else
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_OFST_CTRL :
R_AX_PWR_RATE_OFST_CTRL_C1;
u32 val32 = 0;
s8 *tmp = &tpu->pwr_ofst_mode[0];
val32 = MAC_REG_R32(cr) & ~0xFFFFF;
val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]);
MAC_REG_W32(cr, val32);
#endif
return MACSUCCESS;
}
u32 mac_write_pwr_ofst_bw(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu)
{
#if MAC_AX_FW_REG_OFLD
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL :
R_AX_PWR_LMT_CTRL_C1;
u32 val32 = 0;
u32 ret;
s8 *tmp = &tpu->pwr_ofst_bw[0];
val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]);
ret = MAC_REG_W_OFLD(cr, 0xFFFFF, val32, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
#else
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL :
R_AX_PWR_LMT_CTRL_C1;
u32 val32 = 0;
s8 *tmp = &tpu->pwr_ofst_bw[0];
val32 = MAC_REG_R32(cr) & ~0xFFFFF;
val32 |= NIB_2_DW(0, 0, 0, tmp[4], tmp[3], tmp[2], tmp[1], tmp[0]);
MAC_REG_W32(cr, val32);
#endif
return MACSUCCESS;
}
u32 mac_write_pwr_ref_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu)
{
#if MAC_AX_FW_REG_OFLD
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL :
R_AX_PWR_RATE_CTRL_C1;
u32 val32 = 0;
u32 ret;
val32 |= (((tpu->ref_pow_ofdm & 0x1ff) << 9) |
((tpu->ref_pow_cck & 0x1ff)));
ret = MAC_REG_W_OFLD(cr, 0xFFFFC00, val32, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
#else
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL :
R_AX_PWR_RATE_CTRL_C1;
u32 val32 = 0;
val32 = MAC_REG_R32(cr) & ~0xFFFFC00;
val32 |= (((tpu->ref_pow_ofdm & 0x1ff) << 19) |
((tpu->ref_pow_cck & 0x1ff) << 10));
MAC_REG_W32(cr, val32);
#endif
return MACSUCCESS;
}
u32 mac_write_pwr_limit_en(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu)
{
#if MAC_AX_FW_REG_OFLD
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL :
R_AX_PWR_LMT_CTRL_C1;
u32 val32 = 0;
u32 ret;
if (tpu->pwr_lmt_en)
val32 = 3;
ret = MAC_REG_W_OFLD(cr, 0x300000, val32, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
val32 = 0;
cr = (band == HW_BAND_0) ? R_AX_PWR_RU_LMT_CTRL : R_AX_PWR_RU_LMT_CTRL_C1;
if (tpu->pwr_lmt_en)
val32 = 1;
ret = MAC_REG_W_OFLD(cr, 0x40000, val32, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: config fail\n", __func__);
return ret;
}
#else
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 cr = (band == HW_BAND_0) ? R_AX_PWR_LMT_CTRL :
R_AX_PWR_LMT_CTRL_C1;
u32 val32 = 0;
val32 = MAC_REG_R32(cr) & ~0x300000;
if (tpu->pwr_lmt_en)
val32 |= 0x300000;
MAC_REG_W32(cr, val32);
cr = (band == HW_BAND_0) ? R_AX_PWR_RU_LMT_CTRL : R_AX_PWR_RU_LMT_CTRL_C1;
val32 = MAC_REG_R32(cr) & ~BIT18;
if (tpu->pwr_lmt_en)
val32 |= BIT18;
MAC_REG_W32(cr, val32);
#endif
return MACSUCCESS;
}
u32 mac_read_pwr_reg(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret;
u32 access_offset = offset;
if (offset < R_AX_PWR_RATE_CTRL || offset > 0xFFFF) {
PLTFM_MSG_ERR("[ERR]offset exceed pwr ctrl reg %x\n", offset);
return MACBADDR;
}
if (band == MAC_AX_BAND_1)
access_offset = offset | BIT13;
ret = mac_check_access(adapter, access_offset);
if (ret)
return ret;
*val = MAC_REG_R32(access_offset);
return MACSUCCESS;
}
u32 mac_write_msk_pwr_reg(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 mask, u32 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS;
u32 access_offset = offset;
u32 ori_val = 0;
u8 shift;
if (offset < R_AX_PWR_RATE_CTRL || offset > 0xFFFF) {
PLTFM_MSG_ERR("[ERR]offset exceed pwr ctrl reg %x\n", offset);
return MACBADDR;
}
if (band == MAC_AX_BAND_1)
access_offset = offset | BIT13;
ret = mac_check_access(adapter, access_offset);
if (ret) {
PLTFM_MSG_ERR("[ERR]check access in %x\n", access_offset);
return ret;
}
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)access_offset, mask, val, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__,
access_offset);
return ret;
}
return MACSUCCESS;
}
#endif
if (mask != 0xffffffff) {
shift = shift_mask(mask);
ori_val = MAC_REG_R32(offset);
val = ((ori_val) & (~mask)) | (((val << shift)) & mask);
}
MAC_REG_W32(offset, val);
return MACSUCCESS;
}
u32 mac_write_pwr_reg(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 ret = MACSUCCESS;
u32 access_offset = offset;
if (offset < R_AX_PWR_RATE_CTRL || offset > 0xFFFF) {
PLTFM_MSG_ERR("[ERR]offset exceed pwr ctrl reg %x\n", offset);
return MACBADDR;
}
if (band == MAC_AX_BAND_1)
access_offset = offset | BIT13;
ret = mac_check_access(adapter, access_offset);
if (ret)
return ret;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W32_OFLD((u16)access_offset, val, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n", __func__,
access_offset);
return ret;
}
return MACSUCCESS;
}
#endif
MAC_REG_W32(access_offset, val);
return MACSUCCESS;
}
u32 mac_write_pwr_limit_rua_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u16 cr = (band == HW_BAND_0) ? R_AX_PWR_RU_LMT_TABLE0 :
R_AX_PWR_RU_LMT_TABLE0_C1;
s8 *tmp;
u8 i, j;
#if MAC_AX_FW_REG_OFLD
u32 ret;
#endif
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
for (i = 0; i < HAL_MAX_PATH; i++) {
for (j = 0; j < TPU_SIZE_RUA; j++) {
tmp = &tpu->pwr_lmt_ru[i][j][0];
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[3], tmp[2],
tmp[1], tmp[0]),
0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
cr += 4;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[7], tmp[6],
tmp[5], tmp[4]),
1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
cr += 4;
}
}
return MACSUCCESS;
}
#endif
for (i = 0; i < HAL_MAX_PATH; i++) {
for (j = 0; j < TPU_SIZE_RUA; j++) {
tmp = &tpu->pwr_lmt_ru[i][j][0];
MAC_REG_W32(cr, BT_2_DW(tmp[3], tmp[2], tmp[1], tmp[0]));
cr += 4;
MAC_REG_W32(cr, BT_2_DW(tmp[7], tmp[6], tmp[5], tmp[4]));
cr += 4;
}
}
return MACSUCCESS;
}
u32 mac_write_pwr_limit_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_pwr_imt_info *tpu)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 base = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL :
R_AX_PWR_RATE_CTRL_C1;
u32 ss_ofst = 0;
u16 cr = 0;
s8 *tmp, *tmp_1;
u8 i, j;
#if MAC_AX_FW_REG_OFLD
u32 ret;
#endif
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
for (i = 0; i < HAL_MAX_PATH; i++) {
tmp = &tpu->pwr_lmt_cck_20m[i][0];
tmp_1 = &tpu->pwr_lmt_cck_40m[i][0];
cr = (base | PWR_LMT_CCK_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
tmp = &tpu->pwr_lmt_lgcy_20m[i][0];
tmp_1 = &tpu->pwr_lmt_20m[i][0][0];
cr = (base | PWR_LMT_LGCY_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
cr = (base | PWR_LMT_TBL2_OFFSET) + ss_ofst;
for (j = 1; j <= 5; j += 2) {
tmp = &tpu->pwr_lmt_20m[i][j][0];
tmp_1 = &tpu->pwr_lmt_20m[i][j + 1][0];
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
cr += 4;
}
tmp = &tpu->pwr_lmt_20m[i][7][0];
tmp_1 = &tpu->pwr_lmt_40m[i][0][0];
cr = (base | PWR_LMT_TBL5_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
tmp = &tpu->pwr_lmt_40m[i][1][0];
tmp_1 = &tpu->pwr_lmt_40m[i][2][0];
cr = (base | PWR_LMT_TBL6_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
tmp = &tpu->pwr_lmt_40m[i][3][0];
tmp_1 = &tpu->pwr_lmt_80m[i][0][0];
cr = (base | PWR_LMT_TBL7_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
tmp = &tpu->pwr_lmt_80m[i][1][0];
tmp_1 = &tpu->pwr_lmt_160m[i][0];
cr = (base | PWR_LMT_TBL8_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
tmp = &tpu->pwr_lmt_40m_0p5[i][0];
tmp_1 = &tpu->pwr_lmt_40m_2p5[i][0];
cr = (base | PWR_LMT_TBL9_OFFSET) + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp_1[1], tmp_1[0],
tmp[1], tmp[0]), 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
ss_ofst += PWR_LMT_TBL_UNIT;
}
return MACSUCCESS;
}
#endif
for (i = 0; i < HAL_MAX_PATH; i++) {
tmp = &tpu->pwr_lmt_cck_20m[i][0];
tmp_1 = &tpu->pwr_lmt_cck_40m[i][0];
cr = (base | PWR_LMT_CCK_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
tmp = &tpu->pwr_lmt_lgcy_20m[i][0];
tmp_1 = &tpu->pwr_lmt_20m[i][0][0];
cr = (base | PWR_LMT_LGCY_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
cr = (base | PWR_LMT_TBL2_OFFSET) + ss_ofst;
for (j = 1; j <= 5; j += 2) {
tmp = &tpu->pwr_lmt_20m[i][j][0];
tmp_1 = &tpu->pwr_lmt_20m[i][j + 1][0];
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1],
tmp[0]));
cr += 4;
}
tmp = &tpu->pwr_lmt_20m[i][7][0];
tmp_1 = &tpu->pwr_lmt_40m[i][0][0];
cr = (base | PWR_LMT_TBL5_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
tmp = &tpu->pwr_lmt_40m[i][1][0];
tmp_1 = &tpu->pwr_lmt_40m[i][2][0];
cr = (base | PWR_LMT_TBL6_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
tmp = &tpu->pwr_lmt_40m[i][3][0];
tmp_1 = &tpu->pwr_lmt_80m[i][0][0];
cr = (base | PWR_LMT_TBL7_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
tmp = &tpu->pwr_lmt_80m[i][1][0];
tmp_1 = &tpu->pwr_lmt_160m[i][0];
cr = (base | PWR_LMT_TBL8_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
tmp = &tpu->pwr_lmt_40m_0p5[i][0];
tmp_1 = &tpu->pwr_lmt_40m_2p5[i][0];
cr = (base | PWR_LMT_TBL9_OFFSET) + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp_1[1], tmp_1[0], tmp[1], tmp[0]));
ss_ofst += PWR_LMT_TBL_UNIT;
}
return MACSUCCESS;
}
u32 mac_write_pwr_by_rate_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_pwr_by_rate_info *tpu)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 base = (band == HW_BAND_0) ? R_AX_PWR_RATE_CTRL :
R_AX_PWR_RATE_CTRL_C1;
u32 ss_ofst = 0;
u16 cr = 0;
s8 *tmp;
u8 i, j;
#if MAC_AX_FW_REG_OFLD
u32 ret;
#endif
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
for (i = 0; i <= 8; i += 4) {
tmp = &tpu->pwr_by_rate_lgcy[i];
cr = (base | PWR_BY_RATE_LGCY_OFFSET) + i;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[3], tmp[2],
tmp[1], tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
}
for (i = 0; i < HAL_MAX_PATH; i++) {
for (j = 0; j <= 12; j += 4) {
tmp = &tpu->pwr_by_rate[i][j];
cr = (base | PWR_BY_RATE_OFFSET) + j + ss_ofst;
ret = MAC_REG_W32_OFLD(cr, BT_2_DW(tmp[3], tmp[2], tmp[1],
tmp[0]), 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s FW_OFLD in %x\n",
__func__, cr);
return ret;
}
}
ss_ofst += 0x10; /*16*/
}
return MACSUCCESS;
}
#endif
for (i = 0; i <= 8; i += 4) {
tmp = &tpu->pwr_by_rate_lgcy[i];
cr = (base | PWR_BY_RATE_LGCY_OFFSET) + i;
MAC_REG_W32(cr, BT_2_DW(tmp[3], tmp[2], tmp[1], tmp[0]));
}
for (i = 0; i < HAL_MAX_PATH; i++) {
for (j = 0; j <= 12; j += 4) {
tmp = &tpu->pwr_by_rate[i][j];
cr = (base | PWR_BY_RATE_OFFSET) + j + ss_ofst;
MAC_REG_W32(cr, BT_2_DW(tmp[3], tmp[2], tmp[1],
tmp[0]));
}
ss_ofst += 0x10; /*16*/
}
return MACSUCCESS;
}
u32 mac_read_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (sc_xo) {
*val = (MAC_REG_R32(R_AX_XTAL_ON_CTRL0) >> B_AX_XTAL_SC_XO_SH) &
B_AX_XTAL_SC_XO_MSK;
} else {
*val = (MAC_REG_R32(R_AX_XTAL_ON_CTRL0) >> B_AX_XTAL_SC_XI_SH) &
B_AX_XTAL_SC_XI_MSK;
}
return MACSUCCESS;
}
u32 mac_write_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
if (sc_xo) {
val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0);
val32 &= ~(0xFE0000);
val32 |= ((val & B_AX_XTAL_SC_XO_MSK) << B_AX_XTAL_SC_XO_SH);
MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32);
} else {
val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0);
val32 &= ~(0x1FC00);
val32 = val32 | ((val & B_AX_XTAL_SC_XI_MSK) <<
B_AX_XTAL_SC_XI_SH);
MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32);
}
return MACSUCCESS;
}
u32 mac_read_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val)
{
u8 xtal_si_value;
u32 ret;
if (sc_xo) {
ret = mac_read_xtal_si(adapter, XTAL_SI_XTAL_SC_XO, &xtal_si_value);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
*val = xtal_si_value;
} else {
ret = mac_read_xtal_si(adapter, XTAL_SI_XTAL_SC_XI, &xtal_si_value);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
*val = xtal_si_value;
}
return MACSUCCESS;
}
u32 mac_write_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val)
{
u8 xtal_si_value;
u32 ret;
xtal_si_value = (u8)val;
if (sc_xo) {
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_SC_XO, xtal_si_value,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_SC_XI, xtal_si_value,
FULL_BIT_MASK);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
return MACSUCCESS;
}
u32 mac_write_bbrst_reg(struct mac_ax_adapter *adapter, u8 val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val8;
val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN);
if (val)
MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 | B_AX_FEN_BBRSTB);
else
MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & (~B_AX_FEN_BBRSTB));
return MACSUCCESS;
}
static inline u32 _get_addr_range(struct mac_ax_adapter *adapter, u32 addr)
{
u32 addr_idx;
#define IOCHKRANG(chip) do { \
if (ADDR_IS_AON_##chip(addr)) \
addr_idx = ADDR_AON; \
else if (ADDR_IS_HCI_##chip(addr)) \
addr_idx = ADDR_HCI; \
else if (ADDR_IS_DMAC_##chip(addr)) \
addr_idx = ADDR_DMAC; \
else if (ADDR_IS_CMAC0_##chip(addr)) \
addr_idx = ADDR_CMAC0; \
else if (ADDR_IS_CMAC1_##chip(addr)) \
addr_idx = ADDR_CMAC1; \
else if (ADDR_IS_BB0_##chip(addr)) \
addr_idx = ADDR_BB0; \
else if (ADDR_IS_BB1_##chip(addr)) \
addr_idx = ADDR_BB1; \
else if (ADDR_IS_RF_##chip(addr)) \
addr_idx = ADDR_RF; \
else if (ADDR_IS_IND_ACES_##chip(addr)) \
addr_idx = ADDR_IND_ACES; \
else if (ADDR_IS_RSVD_##chip(addr)) \
addr_idx = ADDR_RSVD; \
else if (ADDR_IS_PON_##chip(addr)) \
addr_idx = ADDR_PON; \
else \
addr_idx = ADDR_INVALID; \
} while (0)
switch (adapter->hw_info->chip_id) {
case MAC_AX_CHIP_ID_8852A:
IOCHKRANG(8852A);
break;
case MAC_AX_CHIP_ID_8852B:
IOCHKRANG(8852B);
break;
case MAC_AX_CHIP_ID_8852C:
IOCHKRANG(8852C);
break;
case MAC_AX_CHIP_ID_8192XB:
IOCHKRANG(8192XB);
break;
default:
addr_idx = ADDR_INVALID;
break;
}
#undef IOCHKRANG
return addr_idx;
}
u32 mac_io_chk_access(struct mac_ax_adapter *adapter, u32 offset)
{
switch (_get_addr_range(adapter, offset)) {
case ADDR_AON:
case ADDR_HCI:
return MACSUCCESS;
case ADDR_PON:
break;
case ADDR_DMAC:
if (adapter->sm.dmac_func != MAC_AX_FUNC_ON)
return MACIOERRDMAC;
break;
case ADDR_CMAC0:
if (adapter->sm.cmac0_func != MAC_AX_FUNC_ON)
return MACIOERRCMAC0;
break;
case ADDR_CMAC1:
if (adapter->sm.cmac1_func != MAC_AX_FUNC_ON)
return MACIOERRCMAC1;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
return MACHWNOSUP;
break;
case ADDR_BB0:
#if CHK_BBRF_IO
if (adapter->sm.bb0_func != MAC_AX_FUNC_ON)
return MACIOERRBB0;
#endif
break;
case ADDR_BB1:
#if CHK_BBRF_IO
if (adapter->sm.bb1_func != MAC_AX_FUNC_ON)
return MACIOERRBB1;
#endif
break;
case ADDR_RF:
#if CHK_BBRF_IO
if (adapter->sm.bb0_func != MAC_AX_FUNC_ON &&
adapter->sm.bb1_func != MAC_AX_FUNC_ON)
return MACIOERRRF;
#endif
break;
case ADDR_IND_ACES:
if (adapter->hw_info->ind_aces_cnt > 1)
PLTFM_MSG_ERR("[ERR]ind aces cnt %d ovf\n",
adapter->hw_info->ind_aces_cnt);
if (adapter->hw_info->ind_aces_cnt != 1)
return MACIOERRIND;
break;
case ADDR_RSVD:
return MACIOERRRSVD;
case ADDR_INVALID:
return MACHWNOSUP;
}
if (adapter->sm.pwr != MAC_AX_PWR_ON)
return MACIOERRPWR;
if (adapter->sm.plat != MAC_AX_PLAT_ON)
return MACIOERRPLAT;
if (adapter->sm.io_st == MAC_AX_IO_ST_HANG)
return MACIOERRISH;
if ((adapter->sm.fw_rst == MAC_AX_FW_RESET_RECV_DONE ||
adapter->sm.fw_rst == MAC_AX_FW_RESET_PROCESS) &&
ADDR_NOT_ALLOW_SERL1(offset))
return MACIOERRSERL1;
if (adapter->sm.fw_rst == MAC_AX_FW_RESET_IDLE &&
adapter->mac_pwr_info.pwr_in_lps && ADDR_NOT_ALLOW_LPS(offset))
return MACIOERRLPS;
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hw.c
|
C
|
agpl-3.0
| 72,559
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_HW_H_
#define _MAC_AX_HW_H_
#define BT_2_DW(B3, B2, B1, B0) \
(((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
#define NIB_2_DW(B7, B6, B5, B4, B3, B2, B1, B0) \
((((B7) & 0xf) << 28) | (((B6) & 0xf) << 24) | \
(((B5) & 0xf) << 20) | (((B4) & 0xf) << 16) | \
(((B3) & 0xf) << 12) | (((B2) & 0xf) << 8) | \
(((B1) & 0xf) << 4) | ((B0) & 0xf))
#include "../type.h"
#include "status.h"
#include "wowlan.h"
#include "tblupd.h"
#include "ser.h"
#if MAC_AX_SDIO_SUPPORT
#include "_sdio.h"
#endif
#if MAC_AX_PCIE_SUPPORT
#include "_pcie.h"
#endif
#if MAC_AX_USB_SUPPORT
#if MAC_AX_8852A_SUPPORT
#include "mac_8852a/_usb_8852a.h"
#endif
#if MAC_AX_8852B_SUPPORT
#include "mac_8852b/_usb_8852b.h"
#endif
#if MAC_AX_8852C_SUPPORT
#include "mac_8852c/_usb_8852c.h"
#endif
#endif
/*--------------------Define -------------------------------------------*/
#define BITS_WLRF_CTRL 0x82
#define BITS_WLRF1_CTRL 0x8200
#define PHYREG_SET_ALL_CYCLE 0xC
#define PHYREG_SET_XYN_CYCLE 0xE
#define PHYREG_SET_X_CYCLE 0x4
#define PHYREG_SET_N_CYCLE 0x2
#define PHYREG_SET_Y_CYCLE 0x1
#define TXSC_80M 0x91
#define TXSC_40M 0x1
#define TXSC_20M 0x0
#define TBL_READ_OP 0x0
#define TBL_WRITE_OP 0x1
#define TXCNT_LMT_MSK 0x1
#define CHANNEL_5G 34
#define CR_TXCNT_MSK 0x7FFFFFFF
/*For XTAL_SI */
#define XTAL_SI_POLLING_CNT 1000
#define XTAL_SI_POLLING_DLY_US 50
#define XTAL_SI_NORMAL_WRITE 0x00
#define XTAL_SI_NORMAL_READ 0x01
#define XTAL_SI_XTAL_SC_XI 0x04
#define XTAL_SI_XTAL_SC_XO 0x05
#define XTAL_SI_XTAL_XMD_2 0x24
#define XTAL_SI_XTAL_XMD_4 0x26
#define XTAL_SI_CV 0x41
#define XTAL_SI_WL_RFC_S0 0x80
#define XTAL_SI_WL_RFC_S1 0x81
#define XTAL_SI_ANAPAR_WL 0x90
#define XTAL_SI_SRAM_CTRL 0xA1
#define FULL_BIT_MASK 0xFF
/* For TXPWR Usage*/
#define PWR_BY_RATE_LGCY_OFFSET 0XC0
#define PWR_BY_RATE_OFFSET 0XCC
#define PWR_LMT_CCK_OFFSET 0XEC
#define PWR_LMT_LGCY_OFFSET 0XF0
#define PWR_LMT_TBL2_OFFSET 0XF4
#define PWR_LMT_TBL5_OFFSET 0X100
#define PWR_LMT_TBL6_OFFSET 0X104
#define PWR_LMT_TBL7_OFFSET 0X108
#define PWR_LMT_TBL8_OFFSET 0X10C
#define PWR_LMT_TBL9_OFFSET 0X110
#define PWR_LMT_TBL_UNIT 0X28
#define PWR_BY_RATE_TBL_UNIT 0XF
#define POLL_SWR_VOLT_CNT 2
#define POLL_SWR_VOLT_US 50
#define CORE_SWR_VOLT_MAX 0xE
#define CORE_SWR_VOLT_MIN 0x8
/* For SS SRAM access*/
#define SS_R_QUOTA_SETTING 0
#define SS_W_QUOTA_SETTING 1
#define SS_R_QUOTA 2
#define SS_W_QUOTA 3
#define SS_R_TX_LEN 5
#define SS_R_DL_MURU_DIS 8
#define SS_W_DL_MURU_DIS 9
#define SS_R_UL_TBL 10
#define SS_W_UL_TBL 11
#define SS_R_BSR_LEN 12
#define SS_W_BSR_LEN 13
#define SS_QUOTA_SETTING_MSK 0xF
#define SS_MACID_SH 8
/* WDRLS filter map */
#define B_WDRLS_FLTR_TXOK BIT(24)
#define B_WDRLS_FLTR_RTYLMT BIT(25)
#define B_WDRLS_FLTR_LIFTIM BIT(26)
#define B_WDRLS_FLTR_MACID BIT(27)
#define CHK_BBRF_IO 0
/*--------------------Define Enum---------------------------------------*/
/**
* @enum tx_tf_info
*
* @brief tx_tf_info
*
* @var tx_tf_info::USER_INFO0_SEL
* Please Place Description here.
* @var tx_tf_info::USER_INFO1_SEL
* Please Place Description here.
* @var tx_tf_info::USER_INFO2_SEL
* Please Place Description here.
* @var tx_tf_info::USER_INFO3_SEL
* Please Place Description here.
* @var tx_tf_info::COMMON_INFO_SEL
* Please Place Description here.
*/
enum tx_tf_info {
USER_INFO0_SEL = 0,
USER_INFO1_SEL = 1,
USER_INFO2_SEL = 2,
USER_INFO3_SEL = 3,
COMMON_INFO_SEL = 4,
};
enum addr_rang_idx {
ADDR_AON = 0,
ADDR_HCI,
ADDR_PON,
ADDR_DMAC,
ADDR_CMAC0,
ADDR_CMAC1,
ADDR_BB0,
ADDR_BB1,
ADDR_RF,
ADDR_IND_ACES,
ADDR_RSVD,
/* keep last */
ADDR_LAST,
ADDR_MAX = ADDR_LAST,
ADDR_INVALID = ADDR_LAST
};
/*--------------------Define MACRO--------------------------------------*/
#define ADDR_IS_AON_8852A(addr) ((addr) <= 0x4FF ? 1 : 0)
#define ADDR_IS_AON_8852B(addr) ((addr) <= 0x4FF ? 1 : 0)
#define ADDR_IS_AON_8852C(addr) ((addr) <= 0x4FF ? 1 : 0)
#define ADDR_IS_AON_8192XB(addr) ((addr) <= 0x4FF ? 1 : 0)
#define ADDR_IS_HCI_8852A(addr) \
((addr) >= 0x1000 && (addr) <= 0x1FFF ? 1 : 0)
#define ADDR_IS_HCI_8852B(addr) \
((addr) >= 0x1000 && (addr) <= 0x1FFF ? 1 : 0)
#define ADDR_IS_HCI_8852C(addr) \
(((addr) >= 0x2000 && (addr) <= 0x63FF) || \
((addr) >= 0x7C00 && (addr) <= 0x7FFF) ? 1 : 0)
#define ADDR_IS_HCI_8192XB(addr) \
(((addr) >= 0x2000 && (addr) <= 0x63FF) || \
((addr) >= 0x7C00 && (addr) <= 0x7FFF) ? 1 : 0)
#define ADDR_IS_PON_8852A(addr) \
(((addr) >= 0x400 && (addr) <= 0xFFF) || \
((addr) >= 0x8000 && (addr) <= 0x8407) || \
((addr) >= 0xC000 && (addr) <= 0xC007) || \
((addr) >= 0xE000 && (addr) <= 0xE007) ? 1 : 0)
#define ADDR_IS_PON_8852B(addr) \
(((addr) >= 0x400 && (addr) <= 0xFFF) || \
((addr) >= 0x8000 && (addr) <= 0x8407) || \
((addr) >= 0xC000 && (addr) <= 0xC007) ? 1 : 0)
#define ADDR_IS_PON_8852C(addr) \
(((addr) >= 0x400 && (addr) <= 0xFFF) || \
((addr) >= 0x7000 && (addr) <= 0x7BFF) || \
((addr) >= 0x8000 && (addr) <= 0x8407) || \
((addr) >= 0xC000 && (addr) <= 0xC007) || \
((addr) >= 0xE000 && (addr) <= 0xE007) ? 1 : 0)
#define ADDR_IS_PON_8192XB(addr) \
(((addr) >= 0x400 && (addr) <= 0xFFF) || \
((addr) >= 0x7000 && (addr) <= 0x7BFF) || \
((addr) >= 0x8000 && (addr) <= 0x8407) || \
((addr) >= 0xC000 && (addr) <= 0xC007) || \
((addr) >= 0xE000 && (addr) <= 0xE007) ? 1 : 0)
#define ADDR_IS_DMAC_8852A(addr) \
((addr) >= 0x8408 && (addr) <= 0xBFFF ? 1 : 0)
#define ADDR_IS_DMAC_8852B(addr) \
((addr) >= 0x8408 && (addr) <= 0xBFFF ? 1 : 0)
#define ADDR_IS_DMAC_8852C(addr) \
(((addr) >= 0x1000 && (addr) <= 0x1FFF) || \
((addr) >= 0x8408 && (addr) <= 0xBFFF) ? 1 : 0)
#define ADDR_IS_DMAC_8192XB(addr) \
(((addr) >= 0x1000 && (addr) <= 0x1FFF) || \
((addr) >= 0x8408 && (addr) <= 0xBFFF) ? 1 : 0)
#define ADDR_IS_CMAC0_8852A(addr) \
((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0)
#define ADDR_IS_CMAC0_8852B(addr) \
((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0)
#define ADDR_IS_CMAC0_8852C(addr) \
((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0)
#define ADDR_IS_CMAC0_8192XB(addr) \
((addr) >= 0xC008 && (addr) <= 0xDFFF ? 1 : 0)
#define ADDR_IS_CMAC1_8852A(addr) \
((addr) >= 0xE008 && (addr) <= 0xFFFF ? 1 : 0)
#define ADDR_IS_CMAC1_8852B(addr) \
((addr) >= 0xE008 && (addr) <= 0xFFFF ? 0 : 0)
#define ADDR_IS_CMAC1_8852C(addr) \
((addr) >= 0xE008 && (addr) <= 0xFFFF ? 1 : 0)
#define ADDR_IS_CMAC1_8192XB(addr) \
((addr) >= 0xE008 && (addr) <= 0xFFFF ? 1 : 0)
#define ADDR_IS_BB0_8852A(addr) \
(((addr) >= 0x10000 && (addr) <= 0x125FF) || \
((addr) >= 0x12E00 && (addr) <= 0x138FF) || \
((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \
((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0)
#define ADDR_IS_BB0_8852B(addr) \
(((addr) >= 0x10000 && (addr) <= 0x125FF) || \
((addr) >= 0x12E00 && (addr) <= 0x138FF) || \
((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \
((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0)
#define ADDR_IS_BB0_8852C(addr) \
(((addr) >= 0x10000 && (addr) <= 0x125FF) || \
((addr) >= 0x12E00 && (addr) <= 0x138FF) || \
((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \
((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0)
#define ADDR_IS_BB0_8192XB(addr) \
(((addr) >= 0x10000 && (addr) <= 0x125FF) || \
((addr) >= 0x12E00 && (addr) <= 0x138FF) || \
((addr) >= 0x13C00 && (addr) <= 0x15FFF) || \
((addr) >= 0x17000 && (addr) <= 0x17FFF) ? 1 : 0)
#define ADDR_IS_BB1_8852A(addr) \
(((addr) >= 0x12600 && (addr) <= 0x12DFF) || \
((addr) >= 0x13900 && (addr) <= 0x13BFF) || \
((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0)
#define ADDR_IS_BB1_8852B(addr) \
(((addr) >= 0x12600 && (addr) <= 0x12DFF) || \
((addr) >= 0x13900 && (addr) <= 0x13BFF) || \
((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0)
#define ADDR_IS_BB1_8852C(addr) \
(((addr) >= 0x12600 && (addr) <= 0x12DFF) || \
((addr) >= 0x13900 && (addr) <= 0x13BFF) || \
((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0)
#define ADDR_IS_BB1_8192XB(addr) \
(((addr) >= 0x12600 && (addr) <= 0x12DFF) || \
((addr) >= 0x13900 && (addr) <= 0x13BFF) || \
((addr) >= 0x16000 && (addr) <= 0x16FFF) ? 1 : 0)
#define ADDR_IS_RF_8852A(addr) \
((addr) >= 0x18000 && (addr) <= 0x1DFFF ? 1 : 0)
#define ADDR_IS_RF_8852B(addr) \
((addr) >= 0x18000 && (addr) <= 0x1FFFF ? 1 : 0)
#define ADDR_IS_RF_8852C(addr) \
((addr) >= 0x18000 && (addr) <= 0x1FFFF ? 1 : 0)
#define ADDR_IS_RF_8192XB(addr) \
((addr) >= 0x18000 && (addr) <= 0x1FFFF ? 1 : 0)
#define ADDR_IS_IND_ACES_8852A(addr) \
((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0)
#define ADDR_IS_IND_ACES_8852B(addr) \
((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0)
#define ADDR_IS_IND_ACES_8852C(addr) \
((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0)
#define ADDR_IS_IND_ACES_8192XB(addr) \
((addr) >= 0x40000 && (addr) <= 0x7FFFF ? 1 : 0)
#define ADDR_IS_RSVD_8852A(addr) \
(((addr) >= 0x2000 && (addr) <= 0x7FFF) || \
((addr) >= 0x1E000 && (addr) <= 0x3FFFF) || \
(addr) >= 0x80000 ? 1 : 0)
#define ADDR_IS_RSVD_8852B(addr) \
(((addr) >= 0x2000 && (addr) <= 0x7FFF) || \
((addr) >= 0x20000 && (addr) <= 0x3FFFF) || \
(addr) >= 0x80000 ? 1 : 0)
#define ADDR_IS_RSVD_8852C(addr) \
(((addr) >= 0x6400 && (addr) <= 0x6FFF) || \
((addr) >= 0x20000 && (addr) <= 0x3FFFF) || \
(addr) >= 0x80000 ? 1 : 0)
#define ADDR_IS_RSVD_8192XB(addr) \
(((addr) >= 0x6400 && (addr) <= 0x6FFF) || \
((addr) >= 0x20000 && (addr) <= 0x3FFFF) || \
(addr) >= 0x80000 ? 1 : 0)
#define ADDR_NOT_ALLOW_SERL1(addr) \
((addr) != R_AX_SER_DBG_INFO && (addr) != R_AX_HCI_FUNC_EN && \
(addr) != R_AX_HD0IMR && (addr) != R_AX_HD0ISR ? 1 : 0)
#define ADDR_NOT_ALLOW_LPS(addr) ((addr) != R_AX_CPWM ? 1 : 0)
/*--------------------Define Struct-------------------------------------*/
/*--------------------Function declaration------------------------------*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_get_hw_info
*
* @param *adapter
* @return Please Place Description here.
* @retval mac_ax_hw_info
*/
struct mac_ax_hw_info *mac_get_hw_info(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_set_hw_value
*
* @param *adapter
* @param hw_id
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_hw_value(struct mac_ax_adapter *adapter,
enum mac_ax_hw_id hw_id, void *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_get_hw_value
*
* @param *adapter
* @param hw_id
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_hw_value(struct mac_ax_adapter *adapter,
enum mac_ax_hw_id hw_id, void *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup LTE_COEX
* @{
*/
/**
* @brief mac_write_lte
*
* @param *adapter
* @param offset
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_lte(struct mac_ax_adapter *adapter,
const u32 offset, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup LTE_COEX
* @{
*/
/**
* @brief mac_read_lte
*
* @param *adapter
* @param offset
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_lte(struct mac_ax_adapter *adapter,
const u32 offset, u32 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_xtal_si
*
* @param *adapter
* @param offset
* @param val
* @param bitmask
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_xtal_si(struct mac_ax_adapter *adapter,
u8 offset, u8 val, u8 bitmask);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_read_xtal_si
*
* @param *adapter
* @param offset
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_xtal_si(struct mac_ax_adapter *adapter,
u8 offset, u8 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief set_host_rpr
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_host_rpr(struct mac_ax_adapter *adapter,
struct mac_ax_host_rpr_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_read_pwr_reg
*
* @param *adapter
* @param band
* @param offset
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 set_l2_status(struct mac_ax_adapter *adapter);
u32 mac_read_pwr_reg(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_reg
*
* @param *adapter
* @param band
* @param offset
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_reg(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_msk_pwr_reg
*
* @param *adapter
* @param band
* @param offset
* @param mask
* @param val
* @return write tx power reg with mask value into fw
* @retval u32
*/
u32 mac_write_msk_pwr_reg(struct mac_ax_adapter *adapter, u8 band,
const u32 offset, u32 mask, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_ofst_mode
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_ofst_mode(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_ofst_bw
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_ofst_bw(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_ref_reg
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_ref_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_limit_en
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_limit_en(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_limit_rua_reg
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_limit_rua_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_limit_reg
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_limit_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_pwr_imt_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_pwr_by_rate_reg
*
* @param *adapter
* @param band
* @param *tpu
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_pwr_by_rate_reg(struct mac_ax_adapter *adapter,
u8 band, struct rtw_tpu_pwr_by_rate_info *tpu);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/** * @brief mac_read_xcap_reg
*
* @param *adapter
* @param sc_xo
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_xcap_reg
*
* @param *adapter
* @param sc_xo
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_xcap_reg(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_bbrst_reg
*
* @param *adapter
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_read_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 *val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_xcap_reg
*
* @param *adapter
* @param sc_xo
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_xcap_reg_dav(struct mac_ax_adapter *adapter, u8 sc_xo, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_write_bbrst_reg
*
* @param *adapter
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_write_bbrst_reg(struct mac_ax_adapter *adapter, u8 val);
/**
* @}
* @}
*/
/** * @brief set_macid_pause
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_macid_pause(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief macid_pause
*
* @param *adapter
* @param *grp
* @return Please Place Description here.
* @retval u32
*/
u32 macid_pause(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_grp *grp);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief get_macid_pause
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 get_macid_pause(struct mac_ax_adapter *adapter,
struct mac_ax_macid_pause_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief get_ss_wmm_tbl
*
* @param *adapter
* @param *ctrl
* @return Please Place Description here.
* @retval u32
*/
u32 get_ss_wmm_tbl(struct mac_ax_adapter *adapter,
struct mac_ax_ss_wmm_tbl_ctrl *ctrl);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief set_enable_bb_rf
*
* @param *adapter
* @param enable
* @return Please Place Description here.
* @retval u32
*/
u32 set_enable_bb_rf(struct mac_ax_adapter *adapter, u8 enable);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief set_cctl_rty_limit
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 set_cctl_rty_limit(struct mac_ax_adapter *adapter,
struct mac_ax_cctl_rty_lmt_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief cfg_mac_bw
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 cfg_mac_bw(struct mac_ax_adapter *adapter,
struct mac_ax_cfg_bw *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief get_ss_quota_mode
*
* @param *adapter
* @param *ctrl
* @return Please Place Description here.
* @retval u32
*/
u32 get_ss_quota_mode(struct mac_ax_adapter *adapter,
struct mac_ax_ss_quota_mode_ctrl *ctrl);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief set_ss_quota_mode
*
* @param *adapter
* @param *ctrl
* @return Please Place Description here.
* @retval u32
*/
u32 set_ss_quota_mode(struct mac_ax_adapter *adapter,
struct mac_ax_ss_quota_mode_ctrl *ctrl);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief ss_get_quotasetting
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 ss_get_quotasetting(struct mac_ax_adapter *adapter,
struct mac_ax_ss_quota_setting *para);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief ss_set_quotasetting
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 ss_set_quotasetting(struct mac_ax_adapter *adapter,
struct mac_ax_ss_quota_setting *para);
/**
* @}
* @}
*/
/**
* @brief scheduler_set_prebkf
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 scheduler_set_prebkf(struct mac_ax_adapter *adapter,
struct mac_ax_prebkf_setting *para);
/**
* @}
* @}
*/
/**
* @brief set_bacam_mode
*
* @param *adapter
* @param mode_sel
* @return Set the R_AX_RESPBA_CAM_CTRL bit 4 to be 0 or 1 which decide the
* option mode in BA CAM.
* @retval u32
*/
u32 set_bacam_mode(struct mac_ax_adapter *adapter, u8 mode_sel);
/**
* @}
* @}
*/
/**
* @brief scheduler_set_prebkf
*
* @param *adapter
* @param *mode_sel
* @return Get the option mode from R_AX_RESPBA_CAM_CTRL bit 4 in the BA CAM.
* @retval u32
*/
u32 get_bacam_mode(struct mac_ax_adapter *adapter, u8 *mode_sel);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup HW_Related
* @{
*/
/**
* @brief mac_io_chk_access
*
* @param *adapter
* @param offset
* @return Please Place Description here.
* @retval u32
*/
u32 mac_io_chk_access(struct mac_ax_adapter *adapter, u32 offset);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hw.h
|
C
|
agpl-3.0
| 22,654
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "hw_seq.h"
#if MAC_AX_FW_REG_OFLD
u32 mac_set_hwseq_reg(struct mac_ax_adapter *adapter,
u8 idx,
u16 val)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_set_hwseq_reg *content;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_set_hwseq_reg));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
content = (struct mac_ax_set_hwseq_reg *)buf;
content->reg_idx = idx;
content->seq_val = val;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_SET_HWSEQ_REG,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#else
u32 mac_set_hwseq_reg(struct mac_ax_adapter *adapter,
u8 idx,
u16 val)
{
u32 reg_val;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (idx) {
case R_AX_HW_SEQ_0:
reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1);
reg_val &= ~((u32)B_AX_HW_SEQ0_MSK << B_AX_HW_SEQ0_SH);
reg_val |= (val << B_AX_HW_SEQ0_SH);
MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val);
break;
case R_AX_HW_SEQ_1:
reg_val = MAC_REG_R32(R_AX_HW_SEQ_0_1);
reg_val &= ~((u32)B_AX_HW_SEQ1_MSK << B_AX_HW_SEQ1_SH);
reg_val |= (val << B_AX_HW_SEQ1_SH);
MAC_REG_W32(R_AX_HW_SEQ_0_1, reg_val);
break;
case R_AX_HW_SEQ_2:
reg_val = MAC_REG_R32(R_AX_HW_SEQ_2_3);
reg_val &= ~((u32)B_AX_HW_SEQ2_MSK << B_AX_HW_SEQ2_SH);
reg_val |= (val << B_AX_HW_SEQ2_SH);
MAC_REG_W32(R_AX_HW_SEQ_2_3, reg_val);
break;
case R_AX_HW_SEQ_3:
reg_val = MAC_REG_R32(R_AX_HW_SEQ_2_3);
reg_val &= ~((u32)B_AX_HW_SEQ3_MSK << B_AX_HW_SEQ3_SH);
reg_val |= (val << B_AX_HW_SEQ3_SH);
MAC_REG_W32(R_AX_HW_SEQ_2_3, reg_val);
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hw_seq.c
|
C
|
agpl-3.0
| 2,743
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_HW_SEQ_H_
#define _MAC_AX_HW_SEQ_H_
#include "../type.h"
#include "fwcmd.h"
enum {
R_AX_HW_SEQ_0 = 0,
R_AX_HW_SEQ_1 = 1,
R_AX_HW_SEQ_2 = 2,
R_AX_HW_SEQ_3 = 3,
};
/**
* @struct mac_ax_set_hwseq_reg
* @brief mac_ax_set_hwseq_reg
*
* @var mac_ax_set_hwseq_reg::reg_idx
* Please Place Description here.
* @var mac_ax_set_hwseq_reg::seq_val
* Please Place Description here.
* @var mac_ax_set_hwseq_reg::rsvd0
* Please Place Description here.
*/
struct mac_ax_set_hwseq_reg {
u32 reg_idx: 2;
u32 seq_val: 12;
u32 rsvd0: 18;
};
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_set_hwseq_reg
*
* @param *adapter
* @param idx
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_hwseq_reg(struct mac_ax_adapter *adapter,
u8 idx,
u16 val);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hw_seq.h
|
C
|
agpl-3.0
| 1,574
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "hwamsdu.h"
#if MAC_AX_FW_REG_OFLD
u32 mac_enable_cut_hwamsdu(struct mac_ax_adapter *adapter,
u8 enable,
u8 low_th,
u16 high_th,
enum mac_ax_ex_shift aligned)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_en_amsdu_cut *content;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV))
return MACNOTSUP;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV))
return MACNOTSUP;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_amsdu_cut));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
content = (struct mac_ax_en_amsdu_cut *)buf;
content->enable = enable;
content->low_th = low_th;
content->high_th = high_th;
content->aligned = aligned;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_AMSDU_CUT_REG,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_enable_hwmasdu(struct mac_ax_adapter *adapter,
u8 enable,
enum mac_ax_amsdu_pkt_num max_num,
u8 en_single_amsdu,
u8 en_last_amsdu_padding)
{
u32 ret = 0;
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct mac_ax_en_hwamsdu *content;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV))
return MACNOTSUP;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV))
return MACNOTSUP;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct mac_ax_en_hwamsdu));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
content = (struct mac_ax_en_hwamsdu *)buf;
content->enable = enable;
content->max_num = max_num;
content->en_single_amsdu = en_single_amsdu;
content->en_last_amsdu_padding = en_last_amsdu_padding;
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_HWAMSDU_REG,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#else
u32 mac_enable_cut_hwamsdu(struct mac_ax_adapter *adapter,
u8 enable,
u8 low_th,
u16 high_th,
enum mac_ax_ex_shift aligned)
{
//cut AMSDU
u32 val;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV))
return MACNOTSUP;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV))
return MACNOTSUP;
}
if (aligned > MAC_AX_BYTE_ALIGNED_8)
return MACNOITEM;
val = MAC_REG_R32(R_AX_CUT_AMSDU_CTRL);
val = SET_CLR_WORD(val, low_th, B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH);
val = (SET_CLR_WORD(val, high_th, B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH) |
B_AX_BIT_CUT_AMSDU_CHKLEN_EN |
B_AX_BIT_EN_CUT_AMSDU);
if (!enable)
val &= ~B_AX_BIT_EN_CUT_AMSDU;
MAC_REG_W32(R_AX_CUT_AMSDU_CTRL, val);
//extra shift
val = 0;
val = (SET_CLR_WORD(val, aligned, B_AX_EXTRA_SHIFT));
MAC_REG_W32(R_AX_CUT_AMSDU_CTRL_2, val);
return MACSUCCESS;
}
u32 mac_enable_hwmasdu(struct mac_ax_adapter *adapter,
u8 enable,
enum mac_ax_amsdu_pkt_num max_num,
u8 en_single_amsdu,
u8 en_last_amsdu_padding)
{
u32 val;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV))
return MACNOTSUP;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV))
return MACNOTSUP;
}
if (max_num >= MAC_AX_AMSDU_AGG_NUM_MAX)
return MACNOITEM;
//HW AMSDU register
val = MAC_REG_R32(R_AX_HWAMSDU_CTRL);
val = (SET_CLR_WORD(val, max_num, B_AX_MAX_AMSDU_NUM) |
B_AX_HWAMSDU_EN);
if (!enable)
val &= ~B_AX_HWAMSDU_EN;
MAC_REG_W32(R_AX_HWAMSDU_CTRL, val);
MAC_REG_W32(R_AX_HWAMSDU_CTRL, (MAC_REG_R32(R_AX_HWAMSDU_CTRL) &
(~B_AX_SINGLE_AMSDU)) |
(en_single_amsdu ? B_AX_SINGLE_AMSDU : 0));
MAC_REG_W32(R_AX_DMAC_TABLE_CTRL, (MAC_REG_R32(R_AX_DMAC_TABLE_CTRL) &
(~B_AX_HWAMSDU_PADDING_MODE)) |
(en_last_amsdu_padding ? B_AX_HWAMSDU_PADDING_MODE : 0));
return MACSUCCESS;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hwamsdu.c
|
C
|
agpl-3.0
| 5,409
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_HWAMSDU_H_
#define _MAC_AX_HWAMSDU_H_
#include "../type.h"
#include "../mac_ax.h"
#define MAX_LENGTH_ENUM 7
/**
* @struct mac_ax_en_amsdu_cut
* @brief mac_ax_en_amsdu_cut
*
* @var mac_ax_en_amsdu_cut::enable
* Please Place Description here.
* @var mac_ax_en_amsdu_cut::low_th
* Please Place Description here.
* @var mac_ax_en_amsdu_cut::high_th
* Please Place Description here.
* @var mac_ax_en_amsdu_cut::aligned
* Please Place Description here.
* @var mac_ax_en_amsdu_cut::rsvd0
* Please Place Description here.
*/
struct mac_ax_en_amsdu_cut {
/* dword0 */
u32 enable: 1;
u32 low_th: 8;
u32 high_th: 16;
u32 aligned: 2;
u32 rsvd0: 5;
};
/**
* @struct mac_ax_en_hwamsdu
* @brief mac_ax_en_hwamsdu
*
* @var mac_ax_en_hwamsdu::enable
* Please Place Description here.
* @var mac_ax_en_hwamsdu::max_num
* Please Place Description here.
* @var mac_ax_en_hwamsdu::en_single_amsdu
* Please Place Description here.
* @var mac_ax_en_hwamsdu::en_last_amsdu_padding
* Please Place Description here.
* @var mac_ax_en_hwamsdu::rsvd0
* Please Place Description here.
*/
struct mac_ax_en_hwamsdu {
/* dword0 */
u32 enable: 1;
u32 max_num: 2;
u32 en_single_amsdu:1;
u32 en_last_amsdu_padding:1;
u32 rsvd0: 27;
};
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_enable_cut_hwamsdu
*
* @param *adapter
* @param enable
* @param low_th
* @param high_th
* @param aligned
* @return Please Place Description here.
* @retval u32
*/
u32 mac_enable_cut_hwamsdu(struct mac_ax_adapter *adapter,
u8 enable,
u8 low_th,
u16 high_th,
enum mac_ax_ex_shift aligned);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup TX_ShortCut
* @{
*/
/**
* @brief mac_enable_hwmasdu
*
* @param *adapter
* @param enable
* @param max_num
* @param en_single_amsdu
* @param en_last_amsdu_padding
* @return Please Place Description here.
* @retval u32
*/
u32 mac_enable_hwmasdu(struct mac_ax_adapter *adapter,
u8 enable,
enum mac_ax_amsdu_pkt_num max_num,
u8 en_single_amsdu,
u8 en_last_amsdu_padding);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/hwamsdu.h
|
C
|
agpl-3.0
| 2,870
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "init.h"
#include "security_cam.h"
#include "hw.h"
#if MAC_AX_PCIE_SUPPORT
#include "_pcie.h"
#endif
static void _mp_core_swr_volt(struct mac_ax_adapter *adapter, u8 init)
{
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
enum mac_ax_core_swr_volt v;
u8 val8;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB))
return;
if (init) {
val8 = MAC_REG_R8(R_AX_SPSLDO_ON_CTRL0);
adapter->hw_info->core_swr_volt = GET_FIELD(val8, B_AX_VOL_L1);
} else {
v = MAC_AX_SWR_NORM;
mac_ops->set_hw_value(adapter, MAC_AX_HW_SET_CORE_SWR_VOLT, &v);
}
}
#if MAC_AX_PCIE_SUPPORT
static u32 _patch_pcie_pldr_polling_fail(struct mac_ax_adapter *adapter)
{
u32 ret = MACSUCCESS;
if (!(is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)))
return MACSUCCESS;
ctrl_dma_all_pcie(adapter, MAC_AX_FUNC_DIS);
ret = clr_idx_all_pcie(adapter);
if (ret)
return ret;
ret = poll_dma_all_idle_pcie(adapter);
if (ret)
return ret;
return ret;
}
#endif
#ifdef CONFIG_NEW_HALMAC_INTERFACE
struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf,
u8 chip_id, u8 cv,
void *phl_adapter, void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb)
{
struct mac_ax_adapter *adapter = NULL;
switch (chip_id) {
#if MAC_AX_8852A_SUPPORT
case MAC_AX_CHIP_ID_8852A:
adapter = get_mac_8852a_adapter(intf, cv, phl_adapter,
drv_adapter, pltfm_cb);
break;
#endif
default:
return NULL;
}
return adapter;
}
#else
struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf,
u8 chip_id, u8 cv,
void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb)
{
struct mac_ax_adapter *adapter = NULL;
switch (chip_id) {
#if MAC_AX_8852A_SUPPORT
case MAC_AX_CHIP_ID_8852A:
adapter = get_mac_8852a_adapter(intf, cv, drv_adapter,
pltfm_cb);
break;
#endif
#if MAC_AX_8852B_SUPPORT
case MAC_AX_CHIP_ID_8852B:
adapter = get_mac_8852b_adapter(intf, cv, drv_adapter,
pltfm_cb);
break;
#endif
#if MAC_AX_8852C_SUPPORT
case MAC_AX_CHIP_ID_8852C:
adapter = get_mac_8852c_adapter(intf, cv, drv_adapter,
pltfm_cb);
break;
#endif
#if MAC_AX_8192XB_SUPPORT
case MAC_AX_CHIP_ID_8192XB:
adapter = get_mac_8192xb_adapter(intf, cv, drv_adapter,
pltfm_cb);
break;
#endif
default:
return NULL;
}
return adapter;
}
#endif
u32 hci_func_en(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret = MACSUCCESS;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
val32 = MAC_REG_R32(R_AX_HCI_FUNC_EN) |
B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN;
MAC_REG_W32(R_AX_HCI_FUNC_EN, val32);
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
val32 = MAC_REG_R32(R_AX_HCI_FUNC_EN) |
B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN;
MAC_REG_W32(R_AX_HCI_FUNC_EN, val32);
} else {
val32 = MAC_REG_R32(R_AX_HCI_FUNC_EN_V1) |
B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN;
MAC_REG_W32(R_AX_HCI_FUNC_EN_V1, val32);
}
return ret;
}
u32 dmac_pre_init(struct mac_ax_adapter *adapter, enum mac_ax_qta_mode mode, u8 fwdl)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
B_AX_DISPATCHER_EN | B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN);
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32);
adapter->sm.dmac_func = MAC_AX_FUNC_ON;
val32 = MAC_REG_R32(R_AX_HAXI_INIT_CFG1);
switch (adapter->hw_info->intf) {
case MAC_AX_INTF_USB:
val32 = SET_CLR_WORD(val32, DMA_MOD_USB,
B_AX_DMA_MODE);
break;
case MAC_AX_INTF_PCIE:
val32 = SET_CLR_WORD(val32, DMA_MOD_PCIE_1B,
B_AX_DMA_MODE);
break;
case MAC_AX_INTF_SDIO:
val32 = SET_CLR_WORD(val32, DMA_MOD_SDIO,
B_AX_DMA_MODE);
break;
default:
PLTFM_MSG_ERR("[ERR]DMAC init with not support intf: %X\n",
adapter->hw_info->intf);
return MACINTF;
}
val32 = (val32 & ~B_AX_STOP_AXI_MST) | B_AX_TXHCI_EN_V1 |
B_AX_RXHCI_EN_V1;
MAC_REG_W32(R_AX_HAXI_INIT_CFG1, val32);
val32 = MAC_REG_R32(R_AX_HAXI_DMA_STOP1) &
~(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 |
B_AX_STOP_ACH3 | B_AX_STOP_ACH4 |
B_AX_STOP_ACH5 | B_AX_STOP_ACH6 |
B_AX_STOP_ACH7 | B_AX_STOP_CH8 |
B_AX_STOP_CH9 | B_AX_STOP_CH12);
MAC_REG_W32(R_AX_HAXI_DMA_STOP1, val32);
val32 = MAC_REG_R32(R_AX_HAXI_DMA_STOP2) &
~(B_AX_STOP_CH10 | B_AX_STOP_CH11);
MAC_REG_W32(R_AX_HAXI_DMA_STOP2, val32);
val32 = MAC_REG_R32(R_AX_PLATFORM_ENABLE) | B_AX_AXIDMA_EN;
MAC_REG_W32(R_AX_PLATFORM_ENABLE, val32);
} else {
val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
B_AX_DISPATCHER_EN | B_AX_PKT_BUF_EN);
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32);
adapter->sm.dmac_func = MAC_AX_FUNC_ON;
}
val32 = (B_AX_DISPATCHER_CLK_EN);
MAC_REG_W32(R_AX_DMAC_CLK_EN, val32);
if (!fwdl)
return MACSUCCESS;
ret = dle_init(adapter, MAC_AX_QTA_DLFW, mode);
if (ret) {
PLTFM_MSG_ERR("[ERR]DLE pre init %d\n", ret);
return ret;
}
ret = hfc_init(adapter, 1, 0, 1);
if (ret) {
PLTFM_MSG_ERR("[ERR]HCI FC pre init %d\n", ret);
return ret;
}
return ret;
}
u32 dmac_func_en(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret = 0;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB)) {
val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN |
B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN |
B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN);
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32);
} else {
val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN |
B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN |
B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
B_AX_DMAC_CRPRT);
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32);
}
val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN |
B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN |
B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN |
B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN);
MAC_REG_W32(R_AX_DMAC_CLK_EN, val32);
adapter->sm.dmac_func = MAC_AX_FUNC_ON;
return ret;
}
u32 cmac_func_en(struct mac_ax_adapter *adapter, u8 band, u8 en)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32_func_en = 0;
u32 val32_ck_en = 0;
u32 val32_c1pc_en = 0;
u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1};
u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1};
val32_func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN |
B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN |
B_AX_CMAC_CRPRT;
val32_ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN |
B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN |
B_AX_RMAC_CKEN;
val32_c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN |
B_AX_R_SYM_WLCMAC1_P1_PC_EN |
B_AX_R_SYM_WLCMAC1_P2_PC_EN |
B_AX_R_SYM_WLCMAC1_P3_PC_EN |
B_AX_R_SYM_WLCMAC1_P4_PC_EN;
if (band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("band %d invalid\n", band);
return MACFUNCINPUT;
}
if (en) {
if (band == MAC_AX_BAND_1) {
MAC_REG_W32(R_AX_AFE_CTRL1,
MAC_REG_R32(R_AX_AFE_CTRL1) |
val32_c1pc_en);
MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND,
MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) &
~B_AX_R_SYM_ISO_CMAC12PP);
MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND,
MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) |
B_AX_CMAC1_FEN);
}
MAC_REG_W32(addrl_ck_en[band],
MAC_REG_R32(addrl_ck_en[band]) | val32_ck_en);
MAC_REG_W32(addrl_func_en[band],
MAC_REG_R32(addrl_func_en[band]) | val32_func_en);
} else {
MAC_REG_W32(addrl_func_en[band],
MAC_REG_R32(addrl_func_en[band]) & ~val32_func_en);
MAC_REG_W32(addrl_ck_en[band],
MAC_REG_R32(addrl_ck_en[band]) & ~val32_ck_en);
if (band == MAC_AX_BAND_1) {
MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND,
MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) &
~B_AX_CMAC1_FEN);
MAC_REG_W32(R_AX_SYS_ISO_CTRL_EXTEND,
MAC_REG_R32(R_AX_SYS_ISO_CTRL_EXTEND) |
B_AX_R_SYM_ISO_CMAC12PP);
MAC_REG_W32(R_AX_AFE_CTRL1,
MAC_REG_R32(R_AX_AFE_CTRL1) &
~val32_c1pc_en);
}
}
if (band == MAC_AX_BAND_0)
adapter->sm.cmac0_func = en ? MAC_AX_FUNC_ON : MAC_AX_FUNC_OFF;
else
adapter->sm.cmac1_func = en ? MAC_AX_FUNC_ON : MAC_AX_FUNC_OFF;
return MACSUCCESS;
}
u32 chip_func_en(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret = MACSUCCESS;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
/* patch for OCP */
val32 = MAC_REG_R32(R_AX_SPSLDO_ON_CTRL0);
val32 |= SET_WOR2(B_AX_OCP_L1_MSK, B_AX_OCP_L1_SH,
B_AX_OCP_L1_MSK);
MAC_REG_W32(R_AX_SPSLDO_ON_CTRL0, val32);
}
return ret;
}
u32 mac_sys_init(struct mac_ax_adapter *adapter)
{
u32 ret;
ret = dmac_func_en(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]DMAC en %d\n", ret);
return ret;
}
ret = cmac_func_en(adapter, MAC_AX_BAND_0, MAC_AX_FUNC_EN);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]CMAC %d en %d %d\n",
MAC_AX_BAND_0, MAC_AX_FUNC_EN, ret);
return ret;
}
ret = chip_func_en(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]chip en %d\n", ret);
return ret;
}
return ret;
}
u32 mac_hal_init(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *trx_info,
struct mac_ax_fwdl_info *fwdl_info,
struct mac_ax_intf_info *intf_info)
{
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hw_info *hw_info = adapter->hw_info;
#if MAC_AX_FEATURE_DBGPKG
struct mac_ax_dbgpkg dbg_val = {0};
struct mac_ax_dbgpkg_en dbg_en = {0};
#endif
u32 ret;
u32 rom_addr;
u8 fwdl_en;
_mp_core_swr_volt(adapter, 1);
ret = mac_ops->pwr_switch(adapter, 1);
if (ret == MACALRDYON) {
ret = mac_ops->pwr_switch(adapter, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr_switch 0 fail %d\n", ret);
goto end;
}
ret = mac_ops->pwr_switch(adapter, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr_switch 0->1 fail %d\n", ret);
goto end;
}
}
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr_switch 1 fail %d\n", ret);
goto end;
}
#if MAC_AX_PCIE_SUPPORT
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
ret = _patch_pcie_pldr_polling_fail(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]_patch_pcie_pldr_polling_fail %d\n", ret);
goto end;
}
}
#endif
ret = hci_func_en(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]hci_func_en %d\n", ret);
goto end;
}
fwdl_en = fwdl_info->fw_en &&
(fwdl_info->dlrom_en || fwdl_info->dlram_en) ? 1 : 0;
ret = dmac_pre_init(adapter, trx_info->qta_mode, fwdl_en);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]fwdl_pre_init %d\n", ret);
goto end;
}
ret = ops->intf_pre_init(adapter, intf_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]intf_pre_init %d\n", ret);
goto end;
}
if (fwdl_info->fw_en) {
if (fwdl_info->dlrom_en) {
switch (hw_info->chip_id) {
case MAC_AX_CHIP_ID_8852A:
rom_addr = RTL8852A_ROM_ADDR;
break;
case MAC_AX_CHIP_ID_8852B:
rom_addr = RTL8852B_ROM_ADDR;
break;
case MAC_AX_CHIP_ID_8852C:
rom_addr = RTL8852C_ROM_ADDR;
break;
case MAC_AX_CHIP_ID_8192XB:
rom_addr = RTL8192XB_ROM_ADDR;
break;
default:
PLTFM_MSG_ERR("[ERR]chip id\n");
return MACNOITEM;
}
ret = mac_ops->romdl(adapter,
fwdl_info->rom_buff,
rom_addr,
fwdl_info->rom_size);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]romdl %d\n", ret);
goto end;
}
}
if (fwdl_info->dlram_en) {
if (fwdl_info->fw_from_hdr) {
ret = mac_ops->enable_fw(adapter,
fwdl_info->fw_cat);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]enable_fw %d\n",
ret);
goto end;
}
} else {
ret = mac_ops->enable_cpu(adapter, 0,
fwdl_info->dlram_en);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]enable_cpu %d\n",
ret);
goto end;
}
ret = mac_ops->fwdl(adapter,
fwdl_info->ram_buff,
fwdl_info->ram_size);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]fwdl %d\n", ret);
goto end;
}
}
}
}
ret = set_enable_bb_rf(adapter, MAC_AX_FUNC_EN);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]set_enable_bb_rf %d\n", ret);
goto end;
}
ret = mac_ops->sys_init(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sys_init %d\n", ret);
goto end;
}
ret = mac_ops->trx_init(adapter, trx_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]trx_init %d\n", ret);
goto end;
}
ret = ops->intf_init(adapter, intf_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]intf_init %d\n", ret);
goto end;
}
end:
if (ret != MACSUCCESS) {
adapter->sm.mac_rdy = MAC_AX_MAC_INIT_ERR;
PLTFM_MSG_ERR("[ERR]hal_init fail %d\n", ret);
#if MAC_AX_FEATURE_DBGPKG
dbg_en.ss_dbg = 1;
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.mac_dbg_port = 1;
dbg_en.plersvd_dbg = 1;
mac_ops->dbg_status_dump(adapter, &dbg_val, &dbg_en);
#endif
} else {
adapter->sm.mac_rdy = MAC_AX_MAC_RDY;
}
return ret;
}
u32 mac_hal_deinit(struct mac_ax_adapter *adapter)
{
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *intf_ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FEATURE_DBGPKG
struct mac_ax_dbgpkg dbg_val = {0};
struct mac_ax_dbgpkg_en dbg_en = {0};
#endif
u32 ret;
adapter->sm.mac_rdy = MAC_AX_MAC_NOT_RDY;
_mp_core_swr_volt(adapter, 1);
ret = rst_port_info(adapter, MAC_AX_BAND_0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]reset port info %d\n", ret);
return ret;
}
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
ret = rst_port_info(adapter, MAC_AX_BAND_1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]reset port info %d\n", ret);
return ret;
}
}
ret = rst_p2p_info(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]reset p2p info %d\n", ret);
return ret;
}
ret = free_sec_info_tbl(adapter, SEC_CAM_NORMAL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]remove security info tbl\n");
return ret;
}
ret = mac_remove_role_by_band(adapter, MAC_AX_BAND_0, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]remove band0 role fail\n");
return ret;
}
ret = mac_remove_role_by_band(adapter, MAC_AX_BAND_1, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]remove band0 role fail\n");
return ret;
}
ret = intf_ops->intf_deinit(adapter, NULL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]intf deinit\n");
goto end;
}
ret = ops->pwr_switch(adapter, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr switch off\n");
goto end;
}
end:
if (ret != MACSUCCESS) {
adapter->sm.mac_rdy = MAC_AX_MAC_DEINIT_ERR;
PLTFM_MSG_ERR("[ERR]hal_deinit fail %d\n", ret);
#if MAC_AX_FEATURE_DBGPKG
dbg_en.ss_dbg = 1;
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.mac_dbg_port = 1;
dbg_en.plersvd_dbg = 1;
ops->dbg_status_dump(adapter, &dbg_val, &dbg_en);
#endif
}
return ret;
}
u32 mac_hal_fast_init(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *trx_info,
struct mac_ax_fwdl_info *fwdl_info,
struct mac_ax_intf_info *intf_info)
{
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_hw_info *hw_info = adapter->hw_info;
#if MAC_AX_FEATURE_DBGPKG
struct mac_ax_dbgpkg dbg_val = {0};
struct mac_ax_dbgpkg_en dbg_en = {0};
#endif
u32 rom_addr;
u32 ret;
u8 fwdl_en;
ret = mac_ops->pwr_switch(adapter, 1);
if (ret == MACALRDYON) {
ret = mac_ops->pwr_switch(adapter, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr_switch 0 fail %d\n", ret);
goto end;
}
ret = mac_ops->pwr_switch(adapter, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr_switch 0->1 fail %d\n", ret);
goto end;
}
}
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr_switch 1 fail %d\n", ret);
goto end;
}
#if MAC_AX_PCIE_SUPPORT
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
ret = _patch_pcie_pldr_polling_fail(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]_patch_pcie_pldr_polling_fail %d\n", ret);
goto end;
}
}
#endif
ret = hci_func_en(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]hci_func_en %d\n", ret);
goto end;
}
fwdl_en = fwdl_info->fw_en &&
(fwdl_info->dlrom_en || fwdl_info->dlram_en) ? 1 : 0;
ret = dmac_pre_init(adapter, trx_info->qta_mode, fwdl_en);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]fwdl_pre_init %d\n", ret);
goto end;
}
ret = ops->intf_pre_init(adapter, intf_info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]intf_pre_init %d\n", ret);
goto end;
}
if (fwdl_info->fw_en) {
if (fwdl_info->dlrom_en) {
switch (hw_info->chip_id) {
case MAC_AX_CHIP_ID_8852A:
rom_addr = RTL8852A_ROM_ADDR;
break;
case MAC_AX_CHIP_ID_8852B:
rom_addr = RTL8852B_ROM_ADDR;
break;
case MAC_AX_CHIP_ID_8852C:
rom_addr = RTL8852C_ROM_ADDR;
break;
case MAC_AX_CHIP_ID_8192XB:
rom_addr = RTL8192XB_ROM_ADDR;
break;
default:
PLTFM_MSG_ERR("[ERR]chip id\n");
return MACNOITEM;
}
ret = mac_ops->romdl(adapter,
fwdl_info->rom_buff,
rom_addr,
fwdl_info->rom_size);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]romdl %d\n", ret);
goto end;
}
}
if (fwdl_info->dlram_en) {
if (fwdl_info->fw_from_hdr) {
ret = mac_ops->enable_fw(adapter,
fwdl_info->fw_cat);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]enable_fw %d\n",
ret);
goto end;
}
} else {
ret = mac_ops->enable_cpu(adapter, 0,
fwdl_info->dlram_en);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]enable_cpu %d\n",
ret);
goto end;
}
ret = mac_ops->fwdl(adapter,
fwdl_info->ram_buff,
fwdl_info->ram_size);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]fwdl %d\n", ret);
goto end;
}
}
}
}
end:
if (ret != MACSUCCESS) {
adapter->sm.mac_rdy = MAC_AX_MAC_FINIT_ERR;
PLTFM_MSG_ERR("[ERR]hal_fast_init fail %d\n", ret);
#if MAC_AX_FEATURE_DBGPKG
dbg_en.ss_dbg = 1;
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.mac_dbg_port = 1;
dbg_en.plersvd_dbg = 1;
mac_ops->dbg_status_dump(adapter, &dbg_val, &dbg_en);
#endif
} else {
adapter->sm.mac_rdy = MAC_AX_MAC_RDY;
}
return ret;
}
u32 mac_hal_fast_deinit(struct mac_ax_adapter *adapter)
{
struct mac_ax_ops *ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *intf_ops = adapter_to_intf_ops(adapter);
#if MAC_AX_FEATURE_DBGPKG
struct mac_ax_dbgpkg dbg_val = {0};
struct mac_ax_dbgpkg_en dbg_en = {0};
#endif
u32 ret;
adapter->sm.mac_rdy = MAC_AX_MAC_NOT_RDY;
ret = intf_ops->intf_deinit(adapter, NULL);
if (ret) {
PLTFM_MSG_ERR("[ERR]intf deinit\n");
goto end;
}
ret = ops->pwr_switch(adapter, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]pwr switch off\n");
goto end;
}
end:
if (ret != MACSUCCESS) {
adapter->sm.mac_rdy = MAC_AX_MAC_FDEINIT_ERR;
PLTFM_MSG_ERR("[ERR]hal_fast_deinit fail %d\n", ret);
#if MAC_AX_FEATURE_DBGPKG
dbg_en.ss_dbg = 1;
dbg_en.dle_dbg = 1;
dbg_en.dmac_dbg = 1;
dbg_en.cmac_dbg = 1;
dbg_en.mac_dbg_port = 1;
dbg_en.plersvd_dbg = 1;
ops->dbg_status_dump(adapter, &dbg_val, &dbg_en);
#endif
}
return ret;
}
u32 mac_ax_init_state(struct mac_ax_adapter *adapter)
{
struct mac_ax_state_mach sm = MAC_AX_DFLT_SM;
adapter->sm = sm;
adapter->fw_info.h2c_seq = 0;
adapter->fw_info.rec_seq = 0;
return MACSUCCESS;
}
u32 mix_info_init(struct mac_ax_adapter *adapter)
{
PLTFM_MUTEX_INIT(&adapter->fw_info.seq_lock);
PLTFM_MUTEX_INIT(&adapter->fw_info.msg_reg);
PLTFM_MUTEX_INIT(&adapter->flash_info.lock);
PLTFM_MUTEX_INIT(&adapter->hw_info->ind_access_lock);
PLTFM_MUTEX_INIT(&adapter->hw_info->lte_rlock);
PLTFM_MUTEX_INIT(&adapter->hw_info->lte_wlock);
PLTFM_MUTEX_INIT(&adapter->hw_info->dbg_port_lock);
PLTFM_MUTEX_INIT(&adapter->cmd_ofld_info.cmd_ofld_lock);
PLTFM_MUTEX_INIT(&adapter->hw_info->err_set_lock);
PLTFM_MUTEX_INIT(&adapter->hw_info->err_get_lock);
#if MAC_AX_PCIE_SUPPORT
PLTFM_MUTEX_INIT(&adapter->hw_info->dbi_lock);
PLTFM_MUTEX_INIT(&adapter->hw_info->mdio_lock);
#endif
PLTFM_MUTEX_INIT(&adapter->h2c_agg_info.h2c_agg_lock);
adapter->hw_info->ind_aces_cnt = 0;
adapter->hw_info->dbg_port_cnt = 0;
return MACSUCCESS;
}
u32 mix_info_exit(struct mac_ax_adapter *adapter)
{
PLTFM_MUTEX_DEINIT(&adapter->fw_info.seq_lock);
PLTFM_MUTEX_DEINIT(&adapter->fw_info.msg_reg);
PLTFM_MUTEX_DEINIT(&adapter->flash_info.lock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->ind_access_lock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->lte_rlock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->lte_wlock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->dbg_port_lock);
PLTFM_MUTEX_DEINIT(&adapter->cmd_ofld_info.cmd_ofld_lock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->err_set_lock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->err_get_lock);
#if MAC_AX_PCIE_SUPPORT
PLTFM_MUTEX_DEINIT(&adapter->hw_info->dbi_lock);
PLTFM_MUTEX_DEINIT(&adapter->hw_info->mdio_lock);
#endif
PLTFM_MUTEX_DEINIT(&adapter->h2c_agg_info.h2c_agg_lock);
adapter->hw_info->ind_aces_cnt = 0;
adapter->hw_info->dbg_port_cnt = 0;
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/init.c
|
C
|
agpl-3.0
| 22,580
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_INIT_H_
#define _MAC_AX_INIT_H_
#include "../type.h"
#if MAC_AX_8852A_SUPPORT
#include "mac_8852a/init_8852a.h"
#endif
#if MAC_AX_8852B_SUPPORT
#include "mac_8852b/init_8852b.h"
#endif
#if MAC_AX_8852C_SUPPORT
#include "mac_8852c/init_8852c.h"
#endif
#if MAC_AX_8192XB_SUPPORT
#include "mac_8192xb/init_8192xb.h"
#endif
#include "role.h"
#include "fwdl.h"
#include "mport.h"
#if MAC_AX_PCIE_SUPPORT
#include "_pcie.h"
#endif
/*--------------------Define -------------------------------------------*/
/*--------------------Define Enum---------------------------------------*/
/*--------------------Define Struct-------------------------------------*/
#ifdef CONFIG_NEW_HALMAC_INTERFACE
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief get_mac_ax_adapter
*
* @param intf
* @param chip_id
* @param cv
* @param *phl_adapter
* @param *drv_adapter
* @param *pltfm_cb
* @return Please Place Description here.
* @retval mac_ax_adapter
*/
struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf,
u8 chip_id, u8 cv,
void *phl_adapter, void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief get_mac_ax_adapter
*
* @param intf
* @param chip_id
* @param cv
* @param *drv_adapter
* @param *pltfm_cb
* @return Please Place Description here.
* @retval mac_ax_adapter
*/
#else
struct mac_ax_adapter *get_mac_ax_adapter(enum mac_ax_intf intf,
u8 chip_id, u8 cv,
void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief cmac_func_en
*
* @param *adapter
* @param band
* @param en
* @return Please Place Description here.
* @retval u32
*/
#endif
u32 cmac_func_en(struct mac_ax_adapter *adapter, u8 band, u8 en);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief mac_sys_init
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_sys_init(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief mac_hal_init
*
* @param *adapter
* @param *trx_info
* @param *fwdl_info
* @param *intf_info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_hal_init(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *trx_info,
struct mac_ax_fwdl_info *fwdl_info,
struct mac_ax_intf_info *intf_info);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief mac_hal_fast_init
*
* @param *adapter
* @param *trx_info
* @param *fwdl_info
* @param *intf_info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_hal_fast_init(struct mac_ax_adapter *adapter,
struct mac_ax_trx_info *trx_info,
struct mac_ax_fwdl_info *fwdl_info,
struct mac_ax_intf_info *intf_info);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief mac_hal_fast_deinit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_hal_fast_deinit(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief mac_hal_deinit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_hal_deinit(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup System
* @{
*/
/**
* @brief mac_ax_init_state
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_ax_init_state(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
u32 mix_info_init(struct mac_ax_adapter *adapter);
u32 mix_info_exit(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/init.h
|
C
|
agpl-3.0
| 4,614
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "la_mode.h"
u32 mac_lamode_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_la_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN);
val32 |= B_AX_BBRPT_EN;
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32);
val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN);
val32 |= B_AX_BBRPT_CLK_EN;
MAC_REG_W32(R_AX_DMAC_CLK_EN, val32);
val32 = MAC_REG_R32(R_AX_LA_CFG);
val32 &= ~BITS_AX_LA_CFG;
val32 |= ((cfg->la_func_en ? B_AX_LA_FEN : 0) |
(cfg->la_restart_en ? B_AX_LA_RESTART_EN : 0) |
(cfg->la_timeout_en ? B_AX_LA_TO_EN : 0) |
SET_WORD(cfg->la_timeout_val, B_AX_LA_TO_VAL) |
SET_WORD(cfg->la_tgr_tu_sel, B_AX_LA_TRIG_TU_SEL) |
SET_WORD(cfg->la_tgr_time_val, B_AX_LA_TRIG_TIME_VAL));
MAC_REG_W32(R_AX_LA_CFG, val32);
if (cfg->la_data_loss_imr)
MAC_REG_W8(R_AX_LA_ERRFLAG, BIT0);
return MACSUCCESS;
}
u32 mac_lamode_buf_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_la_buf_param *param)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_LA_CFG);
val32 &= ~BITS_AX_LA_BUF_CFG;
val32 |= SET_WORD(param->la_buf_sel, B_AX_LA_BUF_SEL);
if (param->la_buf_sel == LA_BUF_SEL_256K) { /* la buf 256K */
val32 |= SET_WORD(LA_SIZE_256K_BUF_BNDY, B_AX_LA_BUF_BNDY);
param->start_addr = LA_SIZE_256K_BUF_BNDY * DLE_BLOCK_SIZE;
param->end_addr = DLE_BUF_BNDY_8852A;
} else if (param->la_buf_sel == LA_BUF_SEL_192K) { /* la buf 192K */
val32 |= SET_WORD(LA_SIZE_192K_BUF_BNDY, B_AX_LA_BUF_BNDY);
param->start_addr = LA_SIZE_192K_BUF_BNDY * DLE_BLOCK_SIZE;
param->end_addr = DLE_BUF_BNDY_8852A;
} else if (param->la_buf_sel == LA_BUF_SEL_128K) { /* la buf 128K */
val32 |= SET_WORD(LA_SIZE_128K_BUF_BNDY_8852B,
B_AX_LA_BUF_BNDY);
param->start_addr = LA_SIZE_128K_BUF_BNDY_8852B *
DLE_BLOCK_SIZE;
param->end_addr = DLE_BUF_BNDY_8852B;
} else if (param->la_buf_sel == LA_BUF_SEL_64K) { /* la buf 64K */
val32 |= SET_WORD(LA_SIZE_128K_BUF_BNDY_8852B,
B_AX_LA_BUF_BNDY);
param->start_addr = LA_SIZE_128K_BUF_BNDY_8852B *
DLE_BLOCK_SIZE;
param->end_addr = DLE_BUF_BNDY_8852B;
} else {
PLTFM_MSG_ERR("[ERR]Non support buf sel %d\n",
param->la_buf_sel);
}
MAC_REG_W32(R_AX_LA_CFG, val32);
return MACSUCCESS;
}
u32 mac_lamode_trigger(struct mac_ax_adapter *adapter, u8 tgr)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 count = 3000;
u8 val8;
if (tgr) {
val8 = MAC_REG_R8(R_AX_LA_CFG);
MAC_REG_W8(R_AX_LA_CFG, val8 | B_AX_LA_TRIG_START);
}
val8 = MAC_REG_R8(R_AX_LA_CFG);
while (--count) {
if (!(val8 & B_AX_LA_TRIG_START))
break;
PLTFM_DELAY_MS(1);
}
if (!count)
return MACPOLLTO;
return MACSUCCESS;
}
struct mac_ax_la_status mac_get_lamode_st(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
struct mac_ax_la_status info;
info.la_buf_wptr = 0;
info.la_buf_rndup_ind = 0;
info.la_sw_fsmst = 0;
info.la_data_loss = 0;
val32 = MAC_REG_R32(R_AX_LA_STATUS);
info.la_sw_fsmst = (val32 >> B_AX_LA_SW_FSMST_SH) &
B_AX_LA_SW_FSMST_MSK;
info.la_buf_wptr = (val32 >> B_AX_LA_BUF_WPTR_SH) &
B_AX_LA_BUF_WPTR_MSK;
info.la_buf_rndup_ind = (val32 & B_AX_LA_BUF_RNDUP) ? 1 : 0;
val32 = MAC_REG_R32(R_AX_LA_ERRFLAG);
info.la_data_loss = (val32 & B_AX_LA_ISR_DATA_LOSS_ERR) ? 1 : 0;
return info;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/la_mode.c
|
C
|
agpl-3.0
| 4,103
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_LA_MODE_H_
#define _MAC_AX_LA_MODE_H_
#include "../type.h"
#include "../mac_ax.h"
/*--------------------Define ----------------------------------------*/
#define BITS_AX_LA_BUF_CFG 0xFFF00
#define BITS_AX_LA_CFG 0xFFF000FF
#define LA_SIZE_192K_BUF_BNDY 0x20
#define LA_SIZE_256K_BUF_BNDY 0x18
#define DLE_BLOCK_SIZE 0x2000
#define DLE_BUF_BNDY_8852A 0x70000
#define DLE_BUF_BNDY_8852B 0x20000
#define LA_BUF_SEL_256K 3
#define LA_BUF_SEL_192K 2
#define LA_BUF_SEL_128K 1
#define LA_BUF_SEL_64K 0
#define LA_SIZE_128K_BUF_BNDY_8852B 0x8
/*--------------------Define Enum------------------------------------*/
/*--------------------Define MACRO----------------------------------*/
/*--------------------Define Struct-----------------------------------*/
/*--------------------Export global variable----------------------------*/
/*--------------------Function declaration-----------------------------*/
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_lamode_cfg
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_lamode_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_la_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_lamode_trigger
*
* @param *adapter
* @param tgr
* @return Please Place Description here.
* @retval u32
*/
u32 mac_lamode_trigger(struct mac_ax_adapter *adapter, u8 tgr);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_lamode_buf_cfg
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 mac_lamode_buf_cfg(struct mac_ax_adapter *adapter,
struct mac_ax_la_buf_param *param);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_get_lamode_st
*
* @param *adapter
* @return Please Place Description here.
* @retval mac_ax_la_status
*/
struct mac_ax_la_status mac_get_lamode_st
(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/la_mode.h
|
C
|
agpl-3.0
| 2,820
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "_usb_8852b.h"
#include "../../mac_ax.h"
#if MAC_AX_USB_SUPPORT
u8 reg_read8_usb_8852b(struct mac_ax_adapter *adapter, u32 addr)
{
u8 offset, count = 0;
u32 val;
offset = addr % MAC_REG_OFFSET;
val = PLTFM_REG_R32(addr - offset);
if (addr >= R_AX_CMAC_FUNC_EN && addr < R_AX_CMAC_REG_END) {
while (count < MAC_REG_POOL_COUNT) {
if (val != MAC_AX_R32_DEAD)
break;
PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr + offset);
PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
val = PLTFM_REG_R32(addr);
count++;
}
}
return (u8)(val >> (offset * MAC_REG_OFFSET_SH));
}
void reg_write8_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u8 val)
{
PLTFM_REG_W8(addr, val);
}
u16 reg_read16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr)
{
u8 offset, count = 0;
u32 val;
offset = addr % MAC_REG_OFFSET;
val = PLTFM_REG_R32(addr - offset);
if (addr >= R_AX_CMAC_FUNC_EN && addr < R_AX_CMAC_REG_END) {
while (count < MAC_REG_POOL_COUNT) {
if (val != MAC_AX_R32_DEAD)
break;
PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr + offset);
PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
val = PLTFM_REG_R32(addr);
count++;
}
}
return (u16)(val >> (offset * MAC_REG_OFFSET_SH));
}
void reg_write16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u16 val)
{
PLTFM_REG_W16(addr, val);
}
u32 reg_read32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr)
{
u8 count = 0;
u32 val = PLTFM_REG_R32(addr);
if (addr >= R_AX_CMAC_FUNC_EN && addr < R_AX_CMAC_REG_END) {
while (count < MAC_REG_POOL_COUNT) {
if (val != MAC_AX_R32_DEAD)
break;
PLTFM_MSG_ERR("[ERR]addr 0x%x = 0xdeadbeef\n", addr);
PLTFM_REG_W32(R_AX_CK_EN, CMAC_CLK_ALLEN);
val = PLTFM_REG_R32(addr);
count++;
}
}
return val;
}
void reg_write32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u32 val)
{
PLTFM_REG_W32(addr, val);
}
u8 get_bulkout_id_8852b(struct mac_ax_adapter *adapter, u8 ch_dma, u8 mode)
{
u8 bulkout_id = 0;
if (mode == 0 && adapter->usb_info.ep5 && adapter->usb_info.ep6 &&
adapter->usb_info.ep12) {
switch (ch_dma) {
case MAC_AX_DMA_ACH0:
bulkout_id = BULKOUTID3;
break;
case MAC_AX_DMA_ACH1:
bulkout_id = BULKOUTID4;
break;
case MAC_AX_DMA_ACH2:
bulkout_id = BULKOUTID5;
break;
case MAC_AX_DMA_ACH3:
bulkout_id = BULKOUTID6;
break;
case MAC_AX_DMA_B0MG:
case MAC_AX_DMA_B0HI:
bulkout_id = BULKOUTID0;
break;
case MAC_AX_DMA_H2C:
bulkout_id = BULKOUTID2;
break;
default:
return USBEPMAPERR;
}
} else if ((mode == 1) && adapter->usb_info.ep5 &&
adapter->usb_info.ep6 && adapter->usb_info.ep12) {
switch (ch_dma) {
case MAC_AX_DMA_ACH0:
bulkout_id = BULKOUTID2;
break;
case MAC_AX_DMA_ACH1:
bulkout_id = BULKOUTID3;
break;
case MAC_AX_DMA_ACH2:
bulkout_id = BULKOUTID4;
break;
case MAC_AX_DMA_ACH3:
bulkout_id = BULKOUTID5;
break;
case MAC_AX_DMA_B0MG:
case MAC_AX_DMA_B0HI:
bulkout_id = BULKOUTID0;
break;
case MAC_AX_DMA_H2C:
bulkout_id = BULKOUTID2;
break;
default:
bulkout_id = USBEPMAPERR;
}
} else {
bulkout_id = USBEPMAPERR;
}
return bulkout_id;
}
u32 usb_pre_init_8852b(struct mac_ax_adapter *adapter, void *param)
{
u32 val32 = 0;
val32 = PLTFM_REG_R32(R_AX_USB_HOST_REQUEST_2) | B_AX_R_USBIO_MODE;
PLTFM_REG_W32(R_AX_USB_HOST_REQUEST_2, val32);
// fix USB IO hang suggest by chihhanli@realtek.com
val32 = PLTFM_REG_R32(R_AX_USB_WLAN0_1) & ~(B_AX_USBRX_RST | B_AX_USBTX_RST);
PLTFM_REG_W32(R_AX_USB_WLAN0_1, val32);
val32 = PLTFM_REG_R32(R_AX_HCI_FUNC_EN);
val32 &= ~B_AX_HCI_RXDMA_EN;
val32 &= ~B_AX_HCI_TXDMA_EN;
PLTFM_REG_W32(R_AX_HCI_FUNC_EN, val32);
val32 |= B_AX_HCI_RXDMA_EN;
val32 |= B_AX_HCI_TXDMA_EN;
PLTFM_REG_W32(R_AX_HCI_FUNC_EN, val32);
// fix USB TRX hang suggest by chihhanli@realtek.com
val32 = PLTFM_REG_R32(R_AX_USB_ENDPOINT_3);
if ((val32 & B_AX_BULKOUT0) == B_AX_BULKOUT0)
adapter->usb_info.ep5 = ENABLE;
if ((val32 & B_AX_BULKOUT1) == B_AX_BULKOUT1)
adapter->usb_info.ep6 = ENABLE;
if (((PLTFM_REG_R32(R_AX_USB_ENDPOINT_3) >> B_AX_AC_BULKOUT_SH) &
B_AX_AC_BULKOUT_MSK) == 1)
adapter->usb_info.ep10 = ENABLE;
if (((PLTFM_REG_R32(R_AX_USB_ENDPOINT_3) >> B_AX_AC_BULKOUT_SH) &
B_AX_AC_BULKOUT_MSK) == 2) {
adapter->usb_info.ep10 = ENABLE;
adapter->usb_info.ep11 = ENABLE;
}
if (((PLTFM_REG_R32(R_AX_USB_ENDPOINT_3) >> B_AX_AC_BULKOUT_SH) &
B_AX_AC_BULKOUT_MSK) == 3) {
adapter->usb_info.ep10 = ENABLE;
adapter->usb_info.ep11 = ENABLE;
adapter->usb_info.ep12 = ENABLE;
}
return MACSUCCESS;
}
u32 usb_init_8852b(struct mac_ax_adapter *adapter, void *param)
{
u32 val32;
u8 val8;
adapter->usb_info.max_bulkout_wd_num = GET_FIELD
(PLTFM_REG_R32(R_AX_CH_PAGE_CTRL), B_AX_PREC_PAGE_CH011);
val32 = PLTFM_REG_R32(R_AX_USB3_MAC_NPI_CONFIG_INTF_0);
val32 &= ~B_AX_SSPHY_LFPS_FILTER;
PLTFM_REG_W32(R_AX_USB3_MAC_NPI_CONFIG_INTF_0, val32);
/* else if (is_cv(adapter, CBV) &&
* is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
* val32 = PLTFM_REG_R32(R_AX_USB3_MAC_LINK_0);
* val32 &= ~B_AX_R_DIS_USB3_U1_EN;
* val32 &= ~B_AX_R_DIS_USB3_U2_EN;
* PLTFM_REG_W32(R_AX_USB3_MAC_LINK_0, val32);
*} else {
* val32 = PLTFM_REG_R32(R_AX_USB3_MAC_LINK_0);
* val32 |= B_AX_R_DIS_USB3_U1_EN;
* val32 |= B_AX_R_DIS_USB3_U2_EN;
* PLTFM_REG_W32(R_AX_USB3_MAC_LINK_0, val32);
*}
*/
val32 = get_usb_mode(adapter);
if (val32 == MAC_AX_USB3)
PLTFM_REG_W8(R_AX_RXDMA_SETTING, USB3_BULKSIZE);
else if (val32 == MAC_AX_USB2)
PLTFM_REG_W8(R_AX_RXDMA_SETTING, USB2_BULKSIZE);
else if (val32 == MAC_AX_USB11)
PLTFM_REG_W8(R_AX_RXDMA_SETTING, USB11_BULKSIZE);
else
return MACHWNOSUP;
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP5, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP6, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP7, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP9, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP10, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP11, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
val8 = PLTFM_REG_R8(R_AX_USB_ENDPOINT_0);
val8 = SET_CLR_WORD(val8, EP12, B_AX_EP_IDX);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_0, val8);
PLTFM_REG_W8(R_AX_USB_ENDPOINT_2 + 1, NUMP);
return MACSUCCESS;
}
u32 usb_deinit_8852b(struct mac_ax_adapter *adapter, void *param)
{
return MACSUCCESS;
}
u32 read_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset)
{
u32 value32 = 0;
u8 rdata = 0;
value32 = SET_CLR_WORD(value32, offset - phyoffset,
B_AX_USB_SIE_INTF_ADDR);
value32 |= B_AX_USB_REG_SEL;
value32 |= B_AX_USB_REG_EN;
value32 |= B_AX_USB_REG_STATUS;
PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32);
while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN)
;
rdata = GET_FIELD(PLTFM_REG_R32(R_AX_USB_SIE_INTF),
B_AX_USB_SIE_INTF_RD);
//DD-Yingli suggest that shall clear it if read operation is done.
PLTFM_REG_W32(R_AX_USB_SIE_INTF, 0);
return rdata;
}
u32 write_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, u8 val)
{
u32 value32 = 0;
value32 = SET_CLR_WORD(value32, val, B_AX_USB_SIE_INTF_WD);
value32 = SET_CLR_WORD(value32, offset, B_AX_USB_SIE_INTF_ADDR);
value32 |= B_AX_USB_REG_SEL;
value32 |= B_AX_USB_WRITE_EN;
value32 |= B_AX_USB_REG_EN;
value32 |= B_AX_USB_REG_STATUS;
PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32);
while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN)
;
//DD-Yingli suggest that shall clear it if write operation is done.
PLTFM_REG_W32(R_AX_USB_SIE_INTF, 0);
return MACSUCCESS;
}
u32 read_usb3phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, u8 b_sel)
{
u32 value32 = 0;
u16 rdata = 0;
if (is_cv(adapter, CAV)) {
value32 = (u32)offset;
value32 |= B_AX_USB3_PHY_REG_RDFLAG;
PLTFM_REG_W32(R_AX_USB3_PHY, value32);
while (PLTFM_REG_R32(R_AX_USB3_PHY) & B_AX_USB3_PHY_REG_RDFLAG)
;
rdata = GET_FIELD(PLTFM_REG_R32(R_AX_USB3_PHY),
B_AX_USB3_PHY_RWDATA);
} else {
value32 = SET_CLR_WORD(value32, offset + USBPHYOFFSET,
B_AX_USB_SIE_INTF_ADDR);
value32 |= B_AX_USB_REG_SEL;
value32 |= B_AX_USB_REG_SEL;
value32 |= B_AX_USB_REG_EN;
if (b_sel)
value32 |= B_AX_USB_PHY_BYTE_SEL;
PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32);
while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN)
;
rdata = GET_FIELD(PLTFM_REG_R32(R_AX_USB_SIE_INTF),
B_AX_USB_SIE_INTF_RD);
}
return rdata;
}
u32 write_usb3phy_para_8852b(struct mac_ax_adapter *adapter,
u16 offset, u8 b_sel, u8 val)
{
u32 value32 = 0;
if (is_cv(adapter, CAV)) {
value32 = SET_CLR_WORD(value32, val, B_AX_USB3_PHY_RWDATA);
value32 |= (u32)offset;
value32 |= B_AX_USB3_PHY_REG_WRFLAG;
PLTFM_REG_W32(R_AX_USB3_PHY, value32);
while (PLTFM_REG_R32(R_AX_USB3_PHY) & B_AX_USB3_PHY_REG_WRFLAG)
;
} else {
value32 = SET_CLR_WORD(value32, val, B_AX_USB_SIE_INTF_WD);
value32 = SET_CLR_WORD(value32, offset + USBPHYOFFSET,
B_AX_USB_SIE_INTF_ADDR);
value32 |= B_AX_USB_REG_SEL;
value32 |= B_AX_USB_REG_SEL;
value32 |= B_AX_USB_WRITE_EN;
value32 |= B_AX_USB_REG_EN;
if (b_sel)
value32 |= B_AX_USB_PHY_BYTE_SEL;
PLTFM_REG_W32(R_AX_USB_SIE_INTF, value32);
while (PLTFM_REG_R32(R_AX_USB_SIE_INTF) & B_AX_USB_REG_EN)
;
}
return MACSUCCESS;
}
u32 u2u3_switch_8852b(struct mac_ax_adapter *adapter)
{
u32 ret = 0;
PLTFM_REG_W8(R_AX_PAD_CTRL2 + 1, USB_SWITCH_DELAY);
ret = get_usb_mode(adapter);
if (ret == MAC_AX_USB2)
PLTFM_REG_W8(R_AX_PAD_CTRL2 + 2, U2SWITCHU3);
else if (ret == MAC_AX_USB3)
PLTFM_REG_W8(R_AX_PAD_CTRL2 + 2, U3SWITCHU2);
else
PLTFM_REG_W8(R_AX_PAD_CTRL2 + 2, U2SWITCHU3);
return MACSUCCESS;
}
u32 get_usb_support_ability_8852b(struct mac_ax_adapter *adapter)
{
u32 u2force = 0;
u32 u3force = 0;
u2force = PLTFM_REG_R32(R_AX_USB_HOST_REQUEST_2) &
B_AX_R_FORCE_U3MAC_HS_MODE;
u3force = PLTFM_REG_R32(R_AX_PAD_CTRL2) &
B_AX_USB3_USB2_TRANSITION;
if (u2force == B_AX_R_FORCE_U3MAC_HS_MODE)
return FORCEUSB2MODE;
else if (u3force == B_AX_USB3_USB2_TRANSITION)
return SWITCHMODE;
else
return FORCEUSB3MODE;
}
u32 usb_tx_agg_cfg_8852b(struct mac_ax_adapter *adapter,
struct mac_ax_usb_tx_agg_cfg *agg)
{
u32 dw1 = ((struct wd_body_usb_8852b *)agg->pkt)->dword1;
((struct wd_body_usb_8852b *)agg->pkt)->dword1 =
SET_CLR_WORD(dw1, agg->agg_num, AX_TXD_DMA_TXAGG_NUM);
return MACSUCCESS;
}
u32 usb_rx_agg_cfg_8852b(struct mac_ax_adapter *adapter,
struct mac_ax_rx_agg_cfg *cfg)
{
u8 size;
u8 timeout;
u8 agg_en;
u8 agg_mode;
u8 pkt_num;
u32 val32;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (cfg->mode == MAC_AX_RX_AGG_MODE_DMA) {
agg_en = ENABLE;
agg_mode = ENABLE;
} else if (cfg->mode == MAC_AX_RX_AGG_MODE_USB) {
agg_en = ENABLE;
agg_mode = DISABLE;
} else {
agg_en = DISABLE;
agg_mode = DISABLE;
}
if (cfg->thold.drv_define == 0) {
size = RXAGGSIZE;
timeout = RXAGGTO;
pkt_num = 0;
} else {
size = cfg->thold.size;
timeout = cfg->thold.timeout;
pkt_num = cfg->thold.pkt_num;
}
val32 = MAC_REG_R32(R_AX_RXAGG_0);
MAC_REG_W32(R_AX_RXAGG_0, (agg_en ? B_AX_RXAGG_EN : 0) |
(agg_mode ? B_AX_RXAGG_DMA_STORE : 0) |
(val32 & B_AX_RXAGG_SW_EN) |
SET_WORD(pkt_num, B_AX_RXAGG_PKTNUM_TH) |
SET_WORD(timeout, B_AX_RXAGG_TIMEOUT_TH) |
SET_WORD(size, B_AX_RXAGG_LEN_TH));
return MACSUCCESS;
}
u32 usb_pwr_switch_8852b(void *vadapter, u8 pre_switch, u8 on)
{
return MACSUCCESS;
}
u32 set_usb_wowlan_8852b(struct mac_ax_adapter *adapter,
enum mac_ax_wow_ctrl w_c)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (w_c == MAC_AX_WOW_ENTER) {
PLTFM_REG_W32(R_AX_USB2_LPM_0, PLTFM_REG_R32(R_AX_USB2_LPM_0) |
B_AX_USB_SUS_WAKEUP_EN);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
B_AX_WLOCK_1C_B6);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
B_AX_R_DIS_PRST);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
~B_AX_WLOCK_1C_B6);
} else if (w_c == MAC_AX_WOW_LEAVE) {
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) |
B_AX_WLOCK_1C_B6);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
~B_AX_R_DIS_PRST);
MAC_REG_W32(R_AX_RSV_CTRL, MAC_REG_R32(R_AX_RSV_CTRL) &
~B_AX_WLOCK_1C_B6);
} else {
PLTFM_MSG_ERR("[ERR] Invalid WoWLAN input.\n");
return MACFUNCINPUT;
}
return MACSUCCESS;
}
u32 usb_get_txagg_num_8852b(struct mac_ax_adapter *adapter, u8 band)
{
u32 quotanum = band ? adapter->dle_info.c1_tx_min : adapter->dle_info.c0_tx_min;
return quotanum * PLE_PAGE_SIZE / (PINGPONG * (SINGLE_MSDU_SIZE + SEC_FCS_SIZE));
}
u32 usb_get_rx_state_8852b(struct mac_ax_adapter *adapter, u32 *val)
{
u8 rxdma_cnt, ep_cnt, curr_rxdma_cnt, curr_ep_cnt;
*val = 0;
rxdma_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_DMA_COUNTER);
ep_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_ENDPOINT_COUNTER);
PLTFM_DELAY_MS(RX_POLLING_PERIOD);
curr_rxdma_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_DMA_COUNTER);
curr_ep_cnt = GET_FIELD(PLTFM_REG_R32(R_AX_USB_DEBUG_1), B_AX_RXDMA_ENDPOINT_COUNTER);
if (curr_rxdma_cnt == rxdma_cnt)
return MACRXDMAHANG;
else if (curr_ep_cnt == ep_cnt)
return MACUSBRXHANG;
else
return MACSUCCESS;
}
#endif /* #if MAC_AX_USB_SUPPORT */
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.c
|
C
|
agpl-3.0
| 14,698
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_USB_8852B_H_
#define _MAC_AX_USB_8852B_H_
#include "../../type.h"
#include "../_usb.h"
/**
* @struct wd_body_usb
* @brief wd_body_usb
*
* @var wd_body_usb::dword0
* Please Place Description here.
* @var wd_body_usb::dword1
* Please Place Description here.
* @var wd_body_usb::dword2
* Please Place Description here.
* @var wd_body_usb::dword3
* Please Place Description here.
* @var wd_body_usb::dword4
* Please Place Description here.
* @var wd_body_usb::dword5
* Please Place Description here.
*/
struct wd_body_usb_8852b {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_read8_usb_8852b
*
* @param *adapter
* @param addr
* @return Please Place Description here.
* @retval u8
*/
u8 reg_read8_usb_8852b(struct mac_ax_adapter *adapter, u32 addr);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_write8_usb_8852b
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval void
*/
void reg_write8_usb_8852b(struct mac_ax_adapter *adapter,
u32 addr, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_read16_usb_8852b
*
* @param *adapter
* @param addr
* @return Please Place Description here.
* @retval u16
*/
u16 reg_read16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_write16_usb_8852b
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval void
*/
void reg_write16_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u16 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_read32_usb_8852b
*
* @param *adapter
* @param addr
* @return Please Place Description here.
* @retval u32
*/
u32 reg_read32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup BasicIO
* @{
*/
/**
* @brief reg_write32_usb_8852b
*
* @param *adapter
* @param addr
* @param val
* @return Please Place Description here.
* @retval void
*/
void reg_write32_usb_8852b(struct mac_ax_adapter *adapter, u32 addr, u32 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief get_bulkout_id_8852b
*
* @param *adapter
* @param ch_dma
* @param mode
* @return Please Place Description here.
* @retval u8
*/
u8 get_bulkout_id_8852b(struct mac_ax_adapter *adapter, u8 ch_dma, u8 mode);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief usb_pre_init_8852b
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 usb_pre_init_8852b(struct mac_ax_adapter *adapter, void *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief usb_init_8852b
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 usb_init_8852b(struct mac_ax_adapter *adapter, void *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief usb_deinit_8852b
*
* @param *adapter
* @param *param
* @return Please Place Description here.
* @retval u32
*/
u32 usb_deinit_8852b(struct mac_ax_adapter *adapter, void *param);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief read_usb2phy_para_8852b
*
* @param *adapter
* @param offset
* @return Please Place Description here.
* @retval u32
*/
u32 read_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief write_usb2phy_para_8852b
*
* @param *adapter
* @param offset
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 write_usb2phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief read_usb3phy_para_8852b
*
* @param *adapter
* @param offset
* @param b_sel
* @return Please Place Description here.
* @retval u32
*/
u32 read_usb3phy_para_8852b(struct mac_ax_adapter *adapter,
u16 offset, u8 b_sel);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief write_usb3phy_para_8852b
*
* @param *adapter
* @param offset
* @param b_sel
* @param val
* @return Please Place Description here.
* @retval u32
*/
u32 write_usb3phy_para_8852b(struct mac_ax_adapter *adapter, u16 offset,
u8 b_sel, u8 val);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief u2u3_switch_8852b
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 u2u3_switch_8852b(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief get_usb_support_ability_8852b
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 get_usb_support_ability_8852b(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief usb_tx_agg_cfg_8852b
*
* @param *adapter
* @param *agg
* @return Please Place Description here.
* @retval u32
*/
u32 usb_tx_agg_cfg_8852b(struct mac_ax_adapter *adapter,
struct mac_ax_usb_tx_agg_cfg *agg);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief usb_rx_agg_cfg_8852b
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 usb_rx_agg_cfg_8852b(struct mac_ax_adapter *adapter,
struct mac_ax_rx_agg_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief usb_pwr_switch_8852b
*
* @param *vadapter
* @param pre_switch
* @param on
* @return Please Place Description here.
* @retval u32
*/
u32 usb_pwr_switch_8852b(void *vadapter,
u8 pre_switch, u8 on);
/**
* @}
* @}
*/
/**
* @addtogroup HCI
* @{
* @addtogroup USB
* @{
*/
/**
* @brief set_usb_wowlan_8852b
*
* @param *adapter
* @param w_c
* @return Please Place Description here.
* @retval u32
*/
u32 set_usb_wowlan_8852b(struct mac_ax_adapter *adapter,
enum mac_ax_wow_ctrl w_c);
/**
* @}
* @}
*/
/**
* @brief usb_get_txagg_num_88852b
*
* @param *adapter
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 usb_get_txagg_num_8852b(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
* @}
*/
/**
* @brief usb_get_rx_state_8852b
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 usb_get_rx_state_8852b(struct mac_ax_adapter *adapter, u32 *val);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/_usb_8852b.h
|
C
|
agpl-3.0
| 7,727
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "../gpio_cmd.h"
#include "../gpio.h"
#include "../../mac_reg.h"
#include "gpio_8852b.h"
/* GPIO0 definition */
#define GPIO0_BT_GPIO0_8852B \
{MAC_AX_SWGPIO, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \
0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define GPIO0_BT_SDIO_INT_8852B \
{MAC_AX_BT_SDIO_INT, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \
0x4F, BIT(5), BIT(5)}
#define GPIO0_USIN_8852B \
{MAC_AX_SWGPIO, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \
0x66, BIT(6), BIT(6)}
#define GPIO0_BT_ANT_SW0_8852B \
{MAC_AX_BT_RF, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \
0x4F, BIT(6), BIT(6)}
#define GPIO0_BT_ACT_8852B \
{MAC_AX_BT_PTA, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \
0x41, BIT(1), BIT(1)}
#define GPIO0_WL_ACT_8852B \
{MAC_AX_WL_PTA, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \
0x41, BIT(2), BIT(2)}
#define GPIO0_WLMAC_DBG_GPIO0_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO0_WLPHY_DBG_GPIO0_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO0_BT_DBG_GPIO0_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO0, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO0_PAON_2G_S0_8852B \
{MAC_AX_PAON_LNAON_2G_S0, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \
0x142, BIT(0), BIT(0)}
#define GPIO0_WL_RFE_CTRL0_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_0, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \
0x142, BIT(1), BIT(1)}
#define GPIO0_PAON_5G_S0_8852B \
{MAC_AX_PAON_LNAON_5G_S0, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \
0x142, BIT(4), BIT(4)}
#define GPIO0_WL_RFE_CTRL0_1_8852B \
{MAC_AX_RFE_WLBT_FUNC_2, MAC_AX_GPIO0, MAC_AX_GPIO_IN, \
0x142, BIT(5), BIT(5)}
#define GPIO0_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO0, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO1 definition */
#define GPIO1_BT_GPIO1_8852B \
{MAC_AX_SWGPIO, MAC_AX_GPIO1, MAC_AX_GPIO_IN_OUT, \
0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define GPIO1_USOUT_8852B \
{MAC_AX_UART, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \
0x66, BIT(6), BIT(6)}
#define GPIO1_BT_ANT_SW1_8852B \
{MAC_AX_BT_RF, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \
0x4F, BIT(6), BIT(6)}
#define GPIO1_BT_3DD_SYNC_8852B \
{MAC_AX_BT_3DDLS_A, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \
0x22, BIT(2), BIT(2)}
#define GPIO1_WL_CK_8852B \
{MAC_AX_BT_PTA, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \
0x41, BIT(1), BIT(1)}
#define GPIO1_BT_CK_8852B \
{MAC_AX_WL_PTA, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \
0x41, BIT(2), BIT(2)}
#define GPIO1_WLMAC_DBG_GPIO1_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO1_WLPHY_DBG_GPIO1_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO1, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO1_BT_DBG_GPIO1_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO1, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO1_LNAON_2G_S0_8852B \
{MAC_AX_PAON_LNAON_2G_S0, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \
0x142, BIT(0), BIT(0)}
#define GPIO1_WL_RFE_CTRL1_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_0, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \
0x142, BIT(1), BIT(1)}
#define GPIO1_LNAON_5G_S0_8852B \
{MAC_AX_PAON_LNAON_5G_S0, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \
0x142, BIT(4), BIT(4)}
#define GPIO1_WL_RFE_CTRL1_1_8852B \
{MAC_AX_RFE_WLBT_FUNC_2, MAC_AX_GPIO1, MAC_AX_GPIO_IN, \
0x142, BIT(5), BIT(5)}
#define GPIO1_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO1, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO2 definition */
#define GPIO2_BT_GPIO2_8852B \
{MAC_AX_SWGPIO, MAC_AX_GPIO2, MAC_AX_GPIO_IN_OUT, \
0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define GPIO2_BT_WAKE_8852B \
{MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \
0x4E, BIT(6), BIT(6)}
#define GPIO2_BT_ANT_SW2_8852B \
{MAC_AX_BT_RF, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \
0x4F, BIT(6), BIT(6)}
#define GPIO2_WL_STATE_8852B \
{MAC_AX_BT_PTA, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \
0x41, BIT(1), BIT(1)}
#define GPIO2_BT_STATE_8852B \
{MAC_AX_WL_PTA, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \
0x41, BIT(2), BIT(2)}
#define GPIO2_WLMAC_DBG_GPIO2_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO2_WLPHY_DBG_GPIO2_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO2, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO2_BT_DBG_GPIO2_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO2, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO2_PAON_2G_S1_8852B \
{MAC_AX_PAON_LNAON_2G_S1, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \
0x142, BIT(2), BIT(2)}
#define GPIO2_WL_RFE_CTRL2_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_1, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \
0x142, BIT(3), BIT(3)}
#define GPIO2_PAON_5G_S1_8852B \
{MAC_AX_PAON_LNAON_5G_S1, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \
0x142, BIT(6), BIT(6)}
#define GPIO2_WL_RFE_CTRL2_1_8852B \
{MAC_AX_RFE_WLBT_FUNC_3, MAC_AX_GPIO2, MAC_AX_GPIO_IN, \
0x142, BIT(7), BIT(7)}
#define GPIO2_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO2, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO3 definition */
#define GPIO3_BT_GPIO3_8852B \
{MAC_AX_SWGPIO, MAC_AX_GPIO3, MAC_AX_GPIO_IN_OUT, \
0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define GPIO3_UART_WAKE_8852B \
{MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \
0x4E, BIT(6), BIT(6)}
#define GPIO3_BT_ANT_SW3_8852B \
{MAC_AX_BT_RF, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \
0x4F, BIT(6), BIT(6)}
#define GPIO3_WL_PRI_8852B \
{MAC_AX_BT_PTA, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \
0x41, BIT(1), BIT(1)}
#define GPIO3_BT_PRI_8852B \
{MAC_AX_WL_PTA, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \
0x41, BIT(2), BIT(2)}
#define GPIO3_WLMAC_DBG_GPIO3_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO3_WLPHY_DBG_GPIO3_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO3, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO3_BT_DBG_GPIO3_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO3, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO3_LNAON_2G_S1_8852B \
{MAC_AX_PAON_LNAON_2G_S1, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \
0x142, BIT(2), BIT(2)}
#define GPIO3_WL_RFE_CTRL3_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_1, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \
0x142, BIT(3), BIT(3)}
#define GPIO3_LNAON_5G_S1_8852B \
{MAC_AX_PAON_LNAON_5G_S1, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \
0x142, BIT(6), BIT(6)}
#define GPIO3_WL_RFE_CTRL3_1_8852B \
{MAC_AX_RFE_WLBT_FUNC_3, MAC_AX_GPIO3, MAC_AX_GPIO_IN, \
0x142, BIT(7), BIT(7)}
#define GPIO3_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO3, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO4 definition */
#define GPIO4_BT_SPI0_8852B \
{MAC_AX_BT_SFALSH, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \
0x66, BIT(4), BIT(4)}
#define GPIO4_WL_SPI0_8852B \
{MAC_AX_WL_SFALSH, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \
0x42, BIT(3), BIT(3)}
#define GPIO4_BT_JTAG_TRST_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \
0x67, BIT(0), BIT(0)}
#define GPIO4_WL_JTAG_TRST_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \
0x65, BIT(7), BIT(7)}
#define GPIO4_DBG_GNT_WL_8852B \
{MAC_AX_DBG_GNT, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \
0x73, BIT(3), BIT(3)}
#define GPIO4_WLMAC_DBG_GPIO4_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO4_WLPHY_DBG_GPIO4_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO4_BT_DBG_GPIO4_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO4, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO4_BANDSEL_5_6G_8852B \
{MAC_AX_BANDSEL_5_6G, MAC_AX_GPIO4, MAC_AX_GPIO_IN, \
0x143, BIT(4), BIT(4)}
#define GPIO4_WL_RFE_CTRL4_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_4, MAC_AX_GPIO4, MAC_AX_GPIO_IN, \
0x144, BIT(4), BIT(4)}
#define GPIO4_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO4, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO5 definition */
#define GPIO5_BT_SPI1_8852B \
{MAC_AX_BT_SFALSH, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \
0x66, BIT(4), BIT(4)}
#define GPIO5_WL_SPI1_8852B \
{MAC_AX_WL_SFALSH, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \
0x42, BIT(3), BIT(3)}
#define GPIO5_BT_JTAG_TDI_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \
0x67, BIT(0), BIT(0)}
#define GPIO5_WL_JTAG_TDI_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \
0x65, BIT(7), BIT(7)}
#define GPIO5_DBG_GNT_BT_8852B \
{MAC_AX_DBG_GNT, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \
0x73, BIT(3), BIT(3)}
#define GPIO5_BT_GPIO18_8852B \
{MAC_AX_BT_GPIO18, MAC_AX_GPIO5, MAC_AX_GPIO_IN_OUT, \
0x67, BIT(1), BIT(1)}
#define GPIO5_SOUT_8852B \
{MAC_AX_WL_UART_TX, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \
0x41, BIT(0), BIT(0)}
#define GPIO5_WLMAC_DBG_GPIO5_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO5_WLPHY_DBG_GPIO5_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO5, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO5_BT_DBG_GPIO5_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO5, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO5_I2C_INT_3W_8852B \
{MAC_AX_MAILBOX_3W, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \
0x4F, BIT(4), BIT(4)}
#define GPIO5_I2C_INT_1W_8852B \
{MAC_AX_MAILBOX_1W, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \
0x4F, BIT(7), BIT(7)}
#define GPIO5_BANDSEL_5_6G_8852B \
{MAC_AX_BANDSEL_5_6G, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \
0x143, BIT(4), BIT(4)}
#define GPIO5_WL_RFE_CTRL5_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_4, MAC_AX_GPIO5, MAC_AX_GPIO_IN, \
0x144, BIT(4), BIT(4)}
#define GPIO5_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO5, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO6 definition */
#define GPIO6_BT_SPI2_8852B \
{MAC_AX_BT_SFALSH, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \
0x66, BIT(4), BIT(4)}
#define GPIO6_WL_SPI2_8852B \
{MAC_AX_WL_SFALSH, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \
0x42, BIT(3), BIT(3)}
#define GPIO6_BT_JTAG_TDO_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \
0x67, BIT(0), BIT(0)}
#define GPIO6_WL_JTAG_TDO_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \
0x65, BIT(7), BIT(7)}
#define GPIO6_LTE_UART_IN_8852B \
{MAC_AX_LTE_UART, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x73, BIT(2), BIT(2)}
#define GPIO6_LTE_3W_RX_IN_8852B \
{MAC_AX_LTE_3W, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x73, BIT(2), BIT(2)}
#define GPIO6_BT_3DD_SYNC_8852B \
{MAC_AX_BT_3DDLS_B, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x67, BIT(1), BIT(1)}
#define GPIO6_SIN_8852B \
{MAC_AX_WL_UART_RX, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x40, BIT(2), BIT(2)}
#define GPIO6_WLMAC_DBG_GPIO6_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO6_WLPHY_DBG_GPIO6_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO6, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO6_BT_DBG_GPIO6_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO6, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO6_PAON_6G_S1_8852B \
{MAC_AX_PAON_LNAON_6G_S1, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x143, BIT(2), BIT(2)}
#define GPIO6_WL_RFE_CTRL6_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_7, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x144, BIT(4), BIT(4)}
#define GPIO6_BANDSEL_5G_8852B \
{MAC_AX_BANDSEL_5G, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x143, BIT(2), BIT(2)}
#define GPIO6_WL_RFE_CTRL6_1_8852B \
{MAC_AX_RFE_WLBT_FUNC_8, MAC_AX_GPIO6, MAC_AX_GPIO_IN, \
0x145, BIT(0), BIT(0)}
#define GPIO6_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO6, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO7 definition */
#define GPIO7_BT_SPI3_8852B \
{MAC_AX_BT_SFALSH, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \
0x66, BIT(4), BIT(4)}
#define GPIO7_WL_SPI3_8852B \
{MAC_AX_WL_SFALSH, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \
0x42, BIT(3), BIT(3)}
#define GPIO7_BT_JTAG_TMS_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x67, BIT(0), BIT(0)}
#define GPIO7_WL_JTAG_TMS_8852B \
{MAC_AX_BT_JTAG, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x65, BIT(7), BIT(7)}
#define GPIO7_LTE_UART_OUT_8852B \
{MAC_AX_LTE_UART, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x73, BIT(2), BIT(2)}
#define GPIO7_LTE_3W_TX_IN_8852B \
{MAC_AX_LTE_3W, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x73, BIT(2), BIT(2)}
#define GPIO7_BT_GPIO16_8852B \
{MAC_AX_BT_GPIO16, MAC_AX_GPIO7, MAC_AX_GPIO_IN_OUT, \
0x67, BIT(2), BIT(2)}
#define GPIO7_SOUT_8852B \
{MAC_AX_WL_UART_TX, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \
0x41, BIT(0), BIT(0)}
#define GPIO7_WLMAC_DBG_GPIO7_8852B \
{MAC_AX_WLMAC_DBG, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(0)}
#define GPIO7_WLPHY_DBG_GPIO7_8852B \
{MAC_AX_WLPHY_DBG, MAC_AX_GPIO7, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), BIT(1)}
#define GPIO7_BT_DBG_GPIO7_8852B \
{MAC_AX_BT_DBG, MAC_AX_GPIO7, MAC_AX_GPIO_OUT, \
0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define GPIO7_LNAON_6G_S1_8852B \
{MAC_AX_PAON_LNAON_6G_S1, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x143, BIT(2), BIT(2)}
#define GPIO7_WL_RFE_CTRL7_0_8852B \
{MAC_AX_RFE_WLBT_FUNC_7, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x144, BIT(4), BIT(4)}
#define GPIO7_BANDSEL_5G_8852B \
{MAC_AX_BANDSEL_5G, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x143, BIT(2), BIT(2)}
#define GPIO7_WL_RFE_CTRL7_1_8852B \
{MAC_AX_RFE_WLBT_FUNC_8, MAC_AX_GPIO7, MAC_AX_GPIO_IN, \
0x145, BIT(0), BIT(0)}
#define GPIO7_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO7, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO8 definition */
#define GPIO8_EXT_WOL_8852B \
{MAC_AX_WL_HW_EXTWOL, MAC_AX_GPIO8, MAC_AX_GPIO_IN, \
0x4A, BIT(0), BIT(0)}
#define GPIO8_SICK_8852B \
{MAC_AX_SIC, MAC_AX_GPIO8, MAC_AX_GPIO_IN, \
0x41, BIT(4), BIT(4)}
#define GPIO8_WL_LED_8852B \
{MAC_AX_WL_LED, MAC_AX_GPIO8, MAC_AX_GPIO_IN, \
0x4E, BIT(5), BIT(5)}
#define GPIO8_SOUT_8852B \
{MAC_AX_WL_UART_TX, MAC_AX_GPIO8, MAC_AX_GPIO_OUT, \
0x41, BIT(0), BIT(0)}
#define GPIO8_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO8, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO9 definition */
#define GPIO9_DIS_WL_N_8852B \
{MAC_AX_WL_HWPDN, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \
0x68, BIT(3), BIT(3)}
#define GPIO9_EXT_WOL_8852B \
{MAC_AX_WL_HW_EXTWOL, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \
0x4A, BIT(0), BIT(0)}
#define GPIO9_USIN_8852B \
{MAC_AX_UART, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \
0x66, BIT(6), BIT(6)}
#define GPIO9_I2C_SD_8852B \
{MAC_AX_MAILBOX_3W, MAC_AX_GPIO9, MAC_AX_GPIO_IN, \
0x4F, BIT(4), BIT(4)}
#define GPIO9_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO9, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO10 definition */
#define GPIO10_WL_SDIO_INT_8852B \
{MAC_AX_WL_SDIO_INT, MAC_AX_GPIO10, MAC_AX_GPIO_OUT, \
0x72, BIT(2), BIT(2)}
#define GPIO10_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO10, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO11 definition */
#define GPIO11_DIS_BT_N_8852B \
{MAC_AX_BT_HWPDN, MAC_AX_GPIO11, MAC_AX_GPIO_IN, \
0x6A, BIT(3), BIT(3)}
#define GPIO11_USOUT_8852B \
{MAC_AX_UART, MAC_AX_GPIO11, MAC_AX_GPIO_OUT, \
0x66, BIT(6), BIT(6)}
#define GPIO11_BANDSEL_5G_G7G6_8852B \
{MAC_AX_BANDSEL_5G_G7G6, MAC_AX_GPIO11, MAC_AX_GPIO_IN, \
0x143, BIT(6), BIT(6)}
#define GPIO11_WL_RFE_CTRL11_8852B \
{MAC_AX_RFE_WLBT_FUNC_5, MAC_AX_GPIO11, MAC_AX_GPIO_IN, \
0x144, BIT(5), BIT(5)}
#define GPIO11_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO11, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO12 definition */
#define GPIO12_USCTS_8852B \
{MAC_AX_UART, MAC_AX_GPIO12, MAC_AX_GPIO_IN, \
0x66, BIT(6), BIT(6)}
#define GPIO12_LTE_PRI_OUT_8852B \
{MAC_AX_LTE_3W, MAC_AX_GPIO12, MAC_AX_GPIO_OUT, \
0x73, BIT(2), BIT(2)}
#define GPIO12_I2C_CLK_8852B \
{MAC_AX_MAILBOX_3W, MAC_AX_GPIO12, MAC_AX_GPIO_IN, \
0x4F, BIT(4), BIT(4)}
#define GPIO12_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO12, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO13 definition */
#define GPIO13_BT_WAKE_8852B \
{MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO13, MAC_AX_GPIO_IN, \
0x4E, BIT(6), BIT(6)}
#define GPIO13_BT_ANT_SW0_8852B \
{MAC_AX_BT_RF, MAC_AX_GPIO13, MAC_AX_GPIO_OUT, \
0x4F, BIT(6), BIT(6)}
#define GPIO13_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO13, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO14 definition */
#define GPIO14_UART_WAKE_8852B \
{MAC_AX_GPIO13_14_WL_CTRL_EN, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \
0x4E, BIT(6), BIT(6)}
#define GPIO14_BT_ANT_SW1_8852B \
{MAC_AX_BT_RF, MAC_AX_GPIO14, MAC_AX_GPIO_OUT, \
0x4F, BIT(6), BIT(6)}
#define GPIO14_SIN_8852B \
{MAC_AX_WL_UART_RX, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \
0x40, BIT(2), BIT(2)}
#define GPIO14_BANDSEL_5G_G7G6_8852B \
{MAC_AX_BANDSEL_5G_G7G6, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \
0x143, BIT(6), BIT(6)}
#define GPIO14_WL_RFE_CTRL11_8852B \
{MAC_AX_RFE_WLBT_FUNC_5, MAC_AX_GPIO14, MAC_AX_GPIO_IN, \
0x144, BIT(5), BIT(5)}
#define GPIO14_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO14, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
/* GPIO15 definition */
#define GPIO15_EXT_XTAL_EN_8852B \
{MAC_AX_EXT_XTAL_CLK, MAC_AX_GPIO15, MAC_AX_GPIO_IN, \
0x66, BIT(7), BIT(7)}
#define GPIO15_SW_IO_8852B \
{MAC_AX_SW_IO, MAC_AX_GPIO15, MAC_AX_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO0_8852B[] = {
GPIO0_BT_GPIO0_8852B,
GPIO0_BT_SDIO_INT_8852B,
GPIO0_USIN_8852B,
GPIO0_BT_ANT_SW0_8852B,
GPIO0_BT_ACT_8852B,
GPIO0_WL_ACT_8852B,
GPIO0_WLMAC_DBG_GPIO0_8852B,
GPIO0_WLPHY_DBG_GPIO0_8852B,
GPIO0_BT_DBG_GPIO0_8852B,
GPIO0_PAON_2G_S0_8852B,
GPIO0_WL_RFE_CTRL0_0_8852B,
GPIO0_PAON_5G_S0_8852B,
GPIO0_WL_RFE_CTRL0_1_8852B,
GPIO0_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO1_8852B[] = {
GPIO1_BT_GPIO1_8852B,
GPIO1_USOUT_8852B,
GPIO1_BT_ANT_SW1_8852B,
GPIO1_BT_3DD_SYNC_8852B,
GPIO1_WL_CK_8852B,
GPIO1_BT_CK_8852B,
GPIO1_WLMAC_DBG_GPIO1_8852B,
GPIO1_WLPHY_DBG_GPIO1_8852B,
GPIO1_BT_DBG_GPIO1_8852B,
GPIO1_LNAON_2G_S0_8852B,
GPIO1_WL_RFE_CTRL1_0_8852B,
GPIO1_LNAON_5G_S0_8852B,
GPIO1_WL_RFE_CTRL1_1_8852B,
GPIO1_SW_IO_8852B,
GPIO1_BT_3DD_SYNC_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO2_8852B[] = {
GPIO2_BT_GPIO2_8852B,
GPIO2_BT_WAKE_8852B,
GPIO2_BT_ANT_SW2_8852B,
GPIO2_WL_STATE_8852B,
GPIO2_BT_STATE_8852B,
GPIO2_WLMAC_DBG_GPIO2_8852B,
GPIO2_WLPHY_DBG_GPIO2_8852B,
GPIO2_BT_DBG_GPIO2_8852B,
GPIO2_PAON_2G_S1_8852B,
GPIO2_WL_RFE_CTRL2_0_8852B,
GPIO2_PAON_5G_S1_8852B,
GPIO2_WL_RFE_CTRL2_1_8852B,
GPIO2_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO3_8852B[] = {
GPIO3_BT_GPIO3_8852B,
GPIO3_UART_WAKE_8852B,
GPIO3_BT_ANT_SW3_8852B,
GPIO3_WL_PRI_8852B,
GPIO3_BT_PRI_8852B,
GPIO3_WLMAC_DBG_GPIO3_8852B,
GPIO3_WLPHY_DBG_GPIO3_8852B,
GPIO3_BT_DBG_GPIO3_8852B,
GPIO3_LNAON_2G_S1_8852B,
GPIO3_WL_RFE_CTRL3_0_8852B,
GPIO3_LNAON_5G_S1_8852B,
GPIO3_WL_RFE_CTRL3_1_8852B,
GPIO3_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO4_8852B[] = {
GPIO4_BT_SPI0_8852B,
GPIO4_WL_SPI0_8852B,
GPIO4_BT_JTAG_TRST_8852B,
GPIO4_WL_JTAG_TRST_8852B,
GPIO4_DBG_GNT_WL_8852B,
GPIO4_WLMAC_DBG_GPIO4_8852B,
GPIO4_WLPHY_DBG_GPIO4_8852B,
GPIO4_BT_DBG_GPIO4_8852B,
GPIO4_BANDSEL_5_6G_8852B,
GPIO4_WL_RFE_CTRL4_0_8852B,
GPIO4_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO5_8852B[] = {
GPIO5_BT_SPI1_8852B,
GPIO5_WL_SPI1_8852B,
GPIO5_BT_JTAG_TDI_8852B,
GPIO5_WL_JTAG_TDI_8852B,
GPIO5_DBG_GNT_BT_8852B,
GPIO5_BT_GPIO18_8852B,
GPIO5_SOUT_8852B,
GPIO5_WLMAC_DBG_GPIO5_8852B,
GPIO5_WLPHY_DBG_GPIO5_8852B,
GPIO5_BT_DBG_GPIO5_8852B,
GPIO5_I2C_INT_3W_8852B,
GPIO5_I2C_INT_1W_8852B,
GPIO5_BANDSEL_5_6G_8852B,
GPIO5_WL_RFE_CTRL5_0_8852B,
GPIO5_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO6_8852B[] = {
GPIO6_BT_SPI2_8852B,
GPIO6_WL_SPI2_8852B,
GPIO6_BT_JTAG_TDO_8852B,
GPIO6_WL_JTAG_TDO_8852B,
GPIO6_LTE_UART_IN_8852B,
GPIO6_LTE_3W_RX_IN_8852B,
GPIO6_SIN_8852B,
GPIO6_WLMAC_DBG_GPIO6_8852B,
GPIO6_WLPHY_DBG_GPIO6_8852B,
GPIO6_BT_DBG_GPIO6_8852B,
GPIO6_PAON_6G_S1_8852B,
GPIO6_WL_RFE_CTRL6_0_8852B,
GPIO6_BANDSEL_5G_8852B,
GPIO6_WL_RFE_CTRL6_1_8852B,
GPIO6_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO7_8852B[] = {
GPIO7_BT_SPI3_8852B,
GPIO7_WL_SPI3_8852B,
GPIO7_BT_JTAG_TMS_8852B,
GPIO7_WL_JTAG_TMS_8852B,
GPIO7_LTE_UART_OUT_8852B,
GPIO7_LTE_3W_TX_IN_8852B,
GPIO7_BT_GPIO16_8852B,
GPIO7_SOUT_8852B,
GPIO7_WLMAC_DBG_GPIO7_8852B,
GPIO7_WLPHY_DBG_GPIO7_8852B,
GPIO7_BT_DBG_GPIO7_8852B,
GPIO7_LNAON_6G_S1_8852B,
GPIO7_WL_RFE_CTRL7_0_8852B,
GPIO7_BANDSEL_5G_8852B,
GPIO7_WL_RFE_CTRL7_1_8852B,
GPIO7_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO8_8852B[] = {
GPIO8_EXT_WOL_8852B,
GPIO8_SICK_8852B,
GPIO8_WL_LED_8852B,
GPIO8_SOUT_8852B,
GPIO8_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO9_8852B[] = {
GPIO9_DIS_WL_N_8852B,
GPIO9_EXT_WOL_8852B,
GPIO9_USIN_8852B,
GPIO9_I2C_SD_8852B,
GPIO9_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO10_8852B[] = {
GPIO10_WL_SDIO_INT_8852B,
GPIO10_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO11_8852B[] = {
GPIO11_DIS_BT_N_8852B,
GPIO11_USOUT_8852B,
GPIO11_BANDSEL_5G_G7G6_8852B,
GPIO11_WL_RFE_CTRL11_8852B,
GPIO11_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO12_8852B[] = {
GPIO12_USCTS_8852B,
GPIO12_LTE_PRI_OUT_8852B,
GPIO12_I2C_CLK_8852B,
GPIO12_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO13_8852B[] = {
GPIO13_BT_WAKE_8852B,
GPIO13_BT_ANT_SW0_8852B,
GPIO13_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO14_8852B[] = {
GPIO14_UART_WAKE_8852B,
GPIO14_BT_ANT_SW1_8852B,
GPIO14_SIN_8852B,
GPIO14_BANDSEL_5G_G7G6_8852B,
GPIO14_WL_RFE_CTRL11_8852B,
GPIO14_SW_IO_8852B,
};
static const struct mac_ax_pinmux_list PINMUX_LIST_GPIO15_8852B[] = {
GPIO15_EXT_XTAL_EN_8852B,
GPIO15_SW_IO_8852B,
};
#define PINMUX_GPIO0_BT_GPIO0_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO0_LTE_UART_IN_PINEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define PINMUX_GPIO0_LTE_UART_IN_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO0_LTE_UART_IN_DIS_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO0_LTE_3W_RX_IN_PINEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define PINMUX_GPIO0_LTE_3W_RX_IN_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO0_LTE_3W_RX_IN_DIS_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO0_WL_ACT_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO0_WL_ACT_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO0_BT_ACT_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO0_BT_ACT_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO0_DBG_GNT_WL_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)}
#define PINMUX_GPIO0_WL_JTAG_TRST_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO0_WL_JTAG_TRST_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO0_WL_JTAG_TRST_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO0_WL_JTAG_TRST_DIS_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO0_WL_RFE_CTRL0_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO0_DBG0_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO0_SW_IO0_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO1_BT_GPIO1_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO1_LTE_UART_OUT_PINEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5) | BIT(4)}
#define PINMUX_GPIO1_LTE_UART_OUT_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO1_LTE_3W_TX_IN_PINEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6)}
#define PINMUX_GPIO1_LTE_3W_TX_IN_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO1_LTE_3W_TX_IN_DIS_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO1_BT_CLK_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO1_BT_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO1_WL_CLK_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO1_WL_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO1_DBG_GNT_BT_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)}
#define PINMUX_GPIO1_WL_JTAG_TDI_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO1_WL_JTAG_TDI_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO1_WL_JTAG_TDI_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO1_WL_JTAG_TDI_DIS_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO1_WL_RFE_CTRL1_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO1_DBG1_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO1_SW_IO1_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D0, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO2_WL_PD_PINEN_8852B \
{RTW_MAC_GPIO_WL_PD, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}
#define PINMUX_GPIO2_WL_PD_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PD, 0x68, \
BIT(0), BIT(0)}
#define PINMUX_GPIO2_WL_PD_DIS_8852B \
{RTW_MAC_GPIO_WL_PD, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO2_WL_PD_DIS_2_8852B \
{RTW_MAC_GPIO_WL_PD, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO2_BT_GPIO2_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO2_LTE_3W_PRI_OUT_PINEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define PINMUX_GPIO2_LTE_3W_PRI_OUT_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO2_BT_STA_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO2_BT_STA_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO2_WL_STA_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO2_WL_STA_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO2_DBG_GNT_WL_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)}
#define PINMUX_GPIO2_WL_JTAG_TDO_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO2_WL_JTAG_TDO_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO2_WL_JTAG_TDO_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO2_WL_JTAG_TDO_DIS_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO2_WL_RFE_CTRL2_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO2_DBG2_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO2_SW_IO02_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D1, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO3_BT_PD_PINEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), 0}
#define PINMUX_GPIO3_BT_PD_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x6A, \
BIT(0), BIT(0)}
#define PINMUX_GPIO3_BT_GPIO3_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO3_BT_PRI_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO3_BT_PRI_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO3_WL_PRI_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO3_WL_PRI_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO3_DBG_GNT_BT_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)}
#define PINMUX_GPIO3_WL_JTAG_TMS_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO3_WL_JTAG_TMS_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO3_WL_JTAG_TMS_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO3_WL_JTAG_TMS_DIS_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO3_WL_RFE_CTRL3_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO3_DBG3_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO3_SW_IO3_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D1, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO4_BT_GPIO4_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO4_WL_FLASH0_PINEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO4_WL_FLASH0_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x42, \
BIT(3), BIT(3)}
#define PINMUX_GPIO4_BT_FLASH0_PINEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO4_BT_FLASH0_SECEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO4_BT_FLASH0_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x66, \
BIT(4), BIT(4)}
#define PINMUX_GPIO4_WL_JTAG_TRST_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO4_WL_JTAG_TRST_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO4_WL_JTAG_TRST_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO4_WL_RFE_CTRL4_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO4_DBG4_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO4_SW_IO04_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D2, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO5_BT_GPIO5_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO5_WL_FLASH1_PINEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)}
#define PINMUX_GPIO5_WL_FLASH1_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x42, \
BIT(3), BIT(3)}
#define PINMUX_GPIO5_BT_FLASH1_PINEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)}
#define PINMUX_GPIO5_BT_FLASH1_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x66, \
BIT(4), BIT(4)}
#define PINMUX_GPIO5_BT_FLASH1_SECEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO5_MAILBOX_I2C_INT_PINEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO5_MAILBOX_I2C_INT_FUNCEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x4F, \
BIT(4), BIT(4)}
#define PINMUX_GPIO5_XTAL_CLK_PINEN_8852B \
{RTW_MAC_GPIO_XTAL_CLK, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)}
#define PINMUX_GPIO5_XTAL_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_XTAL_CLK, 0x4F, \
BIT(5), BIT(5)}
#define PINMUX_GPIO5_WL_JTAG_TDI_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO5_WL_JTAG_TDI_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO5_WL_JTAG_TDI_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO5_WL_RFE_CTRL5_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO5_DBG5_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO5_SW_IO5_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D2, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO6_BT_PD_PINEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}
#define PINMUX_GPIO6_BT_PD_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x6A, \
BIT(0), BIT(0)}
#define PINMUX_GPIO6_BT_GPIO6_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO6_WL_FLASH2_PINEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO6_WL_FLASH2_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x42, \
BIT(3), BIT(3)}
#define PINMUX_GPIO6_BT_FLASH2_PINEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO6_BT_FLASH2_SECEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO6_BT_FLASH2_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x66, \
BIT(4), BIT(4)}
#define PINMUX_GPIO6_LTE_UART_IN_PINEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1) | BIT(0)}
#define PINMUX_GPIO6_LTE_UART_IN_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO6_LTE_3W_RX_IN_PINEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2)}
#define PINMUX_GPIO6_LTE_3W_RX_IN_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO6_MAILBOX_I2C_SD_PINEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO6_MAILBOX_I2C_SD_FUNCEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x4F, \
BIT(4), BIT(4)}
#define PINMUX_GPIO6_DBG_GNT_WL_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)}
#define PINMUX_GPIO6_WL_JTAG_TDO_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO6_WL_JTAG_TDO_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO6_WL_JTAG_TDO_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO6_WL_RFE6_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO6_DBG_GPIO6_8852B \
{RTW_MAC_GPIO_DBG, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO6_SW_IO6_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D3, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO7_BT_PD_PINEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), 0}
#define PINMUX_GPIO7_BT_PD_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x6A, \
BIT(0), BIT(0)}
#define PINMUX_GPIO7_BT_GPIO7_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO7_WL_FLASH3_PINEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)}
#define PINMUX_GPIO7_WL_FLASH3_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_FLASH, 0x42, \
BIT(3), BIT(3)}
#define PINMUX_GPIO7_BT_FLASH3_PINEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5)}
#define PINMUX_GPIO7_BT_FLASH3_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0x66, \
BIT(4), BIT(4)}
#define PINMUX_GPIO7_BT_FLASH3_SECEN_8852B \
{RTW_MAC_GPIO_BT_FLASH, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO7_LTE_UART_OUT_PINEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(5) | BIT(4)}
#define PINMUX_GPIO7_LTE_UART_OUT_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_UART, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO7_LTE_3W_TX_IN_PINEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6)}
#define PINMUX_GPIO7_LTE_3W_TX_IN_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO7_MAILBOX_I2C_CLK_PINEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO7_MAILBOX_I2C_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x4F, \
BIT(4), BIT(4)}
#define PINMUX_GPIO7_DBG_GNT_BT_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)}
#define PINMUX_GPIO7_WL_JTAG_TMS_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO7_WL_JTAG_TMS_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO7_WL_JTAG_TMS_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO7_WL_RFE_CTRL7_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO7_DBG7_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO7_SW_IO7_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D3, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO8_EXT_WOL_PINEN_8852B \
{RTW_MAC_GPIO_WL_EXTWOL, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}
#define PINMUX_GPIO8_EXT_WOL_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_EXTWOL, 0x4A, \
BIT(0), BIT(0)}
#define PINMUX_GPIO8_BT_GPIO8_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO8_SIC_CLK_PINEN_8852B \
{RTW_MAC_GPIO_SIC, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO8_SIC_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_SIC, 0x41, \
BIT(4) | BIT(3), BIT(4) | BIT(3)}
#define PINMUX_GPIO8_SIC_CLK_SECEN_8852B \
{RTW_MAC_GPIO_SIC, 0xC00, \
BIT(1), BIT(1)}
#define PINMUX_GPIO8_MAILBOX_I2C_INT_PINEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO8_MAILBOX_I2C_INT_FUNCEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x4F, \
BIT(4), BIT(4)}
#define PINMUX_GPIO8_WL_LED_PINEN_8852B \
{RTW_MAC_GPIO_WL_LED, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)}
#define PINMUX_GPIO8_WL_LED_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_LED, 0x4E, \
BIT(5), BIT(5)}
#define PINMUX_GPIO8_WL_UART_TX_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO8_WL_UART_TX_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x41, \
BIT(0), BIT(0)}
#define PINMUX_GPIO8_WL_UART_TX_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0xC00, \
BIT(3), BIT(3)}
#define PINMUX_GPIO8_WL_RFE8_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO8_DBG_GPIO8_8852B \
{RTW_MAC_GPIO_DBG, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO8_SW_IO8_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D4, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO9_WL_PD_PINEN_8852B \
{RTW_MAC_GPIO_WL_PD, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), 0}
#define PINMUX_GPIO9_BT_GPIO9_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO9_MAILBOX_I2C_SD_PINEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO9_MAILBOX_I2C_SD_FUNCEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x4F, \
BIT(4), BIT(4)}
#define PINMUX_GPIO9_DBG_GNT_WL_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)}
#define PINMUX_GPIO9_WL_UART_TX_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO9_WL_UART_TX_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x41, \
BIT(0), BIT(0)}
#define PINMUX_GPIO9_WL_UART_TX_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0xC00, \
BIT(3), BIT(3)}
#define PINMUX_GPIO9_WL_RFE_CTRL9_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO9_DBG9_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO9_SW_IO9_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D4, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO10_BT_GPIO10_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO10_WL_SDIO_INT_PINEN_8852B \
{RTW_MAC_GPIO_WL_SDIO_INT, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO10_WL_UART_RX_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO10_WL_UART_RX_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x40, \
BIT(2), BIT(2)}
#define PINMUX_GPIO10_WL_UART_RX_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0xC00, \
BIT(4), BIT(4)}
#define PINMUX_GPIO10_WL_UART_RX_DIS_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO10_WL_UART_RX_DIS_2_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO10_WL_RFE10_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO10_DBG_GPIO10_8852B \
{RTW_MAC_GPIO_DBG, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO10_SW_IO10_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO11_BT_PD_PINEN_8852B \
{RTW_MAC_GPIO_BT_PD, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), 0}
#define PINMUX_GPIO11_BT_GPIO11_PINEN_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO11_MAILBOX_I2C_CLK_PINEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO11_MAILBOX_I2C_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_MAILBOX, 0x4F, \
BIT(4), BIT(4)}
#define PINMUX_GPIO11_DBG_GNT_BT_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5)}
#define PINMUX_GPIO11_WL_UART_RX_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO11_WL_UART_RX_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0xC00, \
BIT(4), BIT(4)}
#define PINMUX_GPIO11_WL_UART_RX_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x40, \
BIT(2), BIT(2)}
#define PINMUX_GPIO11_WL_UART_RX_DIS_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x2D5, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO11_WL_UART_RX_DIS_2_8852B \
{RTW_MAC_GPIO_WL_UART_RX, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO11_WL_RFE_CTRL11_PINEN_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO11_DBG11_PINEN_8852B \
{RTW_MAC_GPIO_DBG, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO11_SW_IO11_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D5, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO12_BT_GPIO12_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO12_LTE_3W_PRI_OUT_PINEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(1)}
#define PINMUX_GPIO12_LTE_3W_PRI_OUT_FUNCEN_8852B \
{RTW_MAC_GPIO_LTE_3W, 0x73, \
BIT(2), BIT(2)}
#define PINMUX_GPIO12_WL_ACT_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO12_WL_ACT_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO12_BT_ACT_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO12_BT_ACT_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO12_BT_ACT_DIS_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D0, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO12_DBG_GNT_WL_PINEN_8852B \
{RTW_MAC_GPIO_DBG_GNT, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1)}
#define PINMUX_GPIO12_SOUT_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO12_SOUT_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0xC00, \
BIT(3), BIT(3)}
#define PINMUX_GPIO12_SOUT_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x41, \
BIT(0), BIT(0)}
#define PINMUX_GPIO12_WL_RFE12_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO12_DBG_GPIO12_8852B \
{RTW_MAC_GPIO_DBG, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO12_SW_IO12_PINEN_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D6, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO13_BT_GPIO13_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO13_WL_PTA_BT_CLK_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO13_WL_PTA_BT_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO13_BT_PTA_WL_CLK_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO13_BT_PTA_WL_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO13_WL_UART_TX_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO13_WL_UART_TX_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0xC00, \
BIT(3), BIT(3)}
#define PINMUX_GPIO13_WL_UART_TX_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x41, \
BIT(0), BIT(0)}
#define PINMUX_GPIO13_WL_RFE_CTRL13_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO13_DBG13_8852B \
{RTW_MAC_GPIO_DBG, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO13_SW_IO13_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D6, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO14_BT_GPIO14_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(0)}
#define PINMUX_GPIO14_WL_PTA_BT_STA_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO14_WL_PTA_BT_STA_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO14_BT_PTA_WL_STA_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(0)}
#define PINMUX_GPIO14_BT_PTA_WL_STA_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO14_WL_JTAG_CLK_PINEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO14_WL_JTAG_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0x65, \
BIT(7), BIT(7)}
#define PINMUX_GPIO14_WL_JTAG_CLK_SECEN_8852B \
{RTW_MAC_GPIO_WL_JTAG, 0xC00, \
BIT(2), BIT(2)}
#define PINMUX_GPIO14_WL_RFE_CTRL13_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO14_DBG14_8852B \
{RTW_MAC_GPIO_DBG, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1)}
#define PINMUX_GPIO14_SW_IO14_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D7, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3) | BIT(2) | BIT(1) | BIT(0)}
#define PINMUX_GPIO15_WL_PD_PINEN_8852B \
{RTW_MAC_GPIO_WL_PD, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), 0}
#define PINMUX_GPIO15_BT_GPIO15_8852B \
{RTW_MAC_GPIO_BT_GPIO, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(4)}
#define PINMUX_GPIO15_WL_PTA_BT_CLK_PINEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO15_WL_PTA_BT_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2)}
#define PINMUX_GPIO15_BT_PTA_WL_CLK_PINEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(4)}
#define PINMUX_GPIO15_BT_PTA_WL_CLK_FUNCEN_8852B \
{RTW_MAC_GPIO_BT_PTA, 0x41, \
BIT(2) | BIT(1), BIT(2) | BIT(1)}
#define PINMUX_GPIO15_WL_UART_TX_PINEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO15_WL_UART_TX_SECEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0xC00, \
BIT(3), BIT(3)}
#define PINMUX_GPIO15_WL_UART_TX_FUNCEN_8852B \
{RTW_MAC_GPIO_WL_UART_TX, 0x41, \
BIT(0), BIT(0)}
#define PINMUX_GPIO15_WL_RFE_CTRL15_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO15_DBG15_8852B \
{RTW_MAC_GPIO_DBG, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5)}
#define PINMUX_GPIO15_SW_IO15_8852B \
{RTW_MAC_GPIO_SW_IO, 0x2D7, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7) | BIT(6) | BIT(5) | BIT(4)}
#define PINMUX_GPIO16_WL_RFE_CTRL16_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D8, \
BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT(3)}
#define PINMUX_GPIO17_WL_RFE_CTRL17_8852B \
{RTW_MAC_GPIO_WL_RFE_CTRL, 0x2D8, \
BIT(7) | BIT(6) | BIT(5) | BIT(4), BIT(7)}
#define PINMUX_GPIO_END_8852B \
{RTW_MAC_GPIO_INVALID, 0, 0, 0}
static const struct mac_ax_pin_list PIN_LIST_GPIO0_8852B[] = {
PINMUX_GPIO0_BT_GPIO0_PINEN_8852B,
PINMUX_GPIO0_LTE_UART_IN_PINEN_8852B,
PINMUX_GPIO0_LTE_UART_IN_FUNCEN_8852B,
PINMUX_GPIO0_LTE_UART_IN_DIS_8852B,
PINMUX_GPIO0_LTE_3W_RX_IN_PINEN_8852B,
PINMUX_GPIO0_LTE_3W_RX_IN_FUNCEN_8852B,
PINMUX_GPIO0_LTE_3W_RX_IN_DIS_8852B,
PINMUX_GPIO0_WL_ACT_PINEN_8852B,
PINMUX_GPIO0_WL_ACT_FUNCEN_8852B,
PINMUX_GPIO0_BT_ACT_PINEN_8852B,
PINMUX_GPIO0_BT_ACT_FUNCEN_8852B,
PINMUX_GPIO0_DBG_GNT_WL_PINEN_8852B,
PINMUX_GPIO0_WL_JTAG_TRST_PINEN_8852B,
PINMUX_GPIO0_WL_JTAG_TRST_FUNCEN_8852B,
PINMUX_GPIO0_WL_JTAG_TRST_SECEN_8852B,
PINMUX_GPIO0_WL_JTAG_TRST_DIS_8852B,
PINMUX_GPIO0_WL_RFE_CTRL0_PINEN_8852B,
PINMUX_GPIO0_DBG0_PINEN_8852B,
PINMUX_GPIO0_SW_IO0_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO1_8852B[] = {
PINMUX_GPIO1_BT_GPIO1_PINEN_8852B,
PINMUX_GPIO1_LTE_UART_OUT_PINEN_8852B,
PINMUX_GPIO1_LTE_UART_OUT_FUNCEN_8852B,
PINMUX_GPIO1_LTE_3W_TX_IN_PINEN_8852B,
PINMUX_GPIO1_LTE_3W_TX_IN_FUNCEN_8852B,
PINMUX_GPIO1_LTE_3W_TX_IN_DIS_8852B,
PINMUX_GPIO1_BT_CLK_PINEN_8852B,
PINMUX_GPIO1_BT_CLK_FUNCEN_8852B,
PINMUX_GPIO1_WL_CLK_PINEN_8852B,
PINMUX_GPIO1_WL_CLK_FUNCEN_8852B,
PINMUX_GPIO1_DBG_GNT_BT_PINEN_8852B,
PINMUX_GPIO1_WL_JTAG_TDI_PINEN_8852B,
PINMUX_GPIO1_WL_JTAG_TDI_FUNCEN_8852B,
PINMUX_GPIO1_WL_JTAG_TDI_SECEN_8852B,
PINMUX_GPIO1_WL_JTAG_TDI_DIS_8852B,
PINMUX_GPIO1_WL_RFE_CTRL1_PINEN_8852B,
PINMUX_GPIO1_DBG1_PINEN_8852B,
PINMUX_GPIO1_SW_IO1_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO2_8852B[] = {
PINMUX_GPIO2_WL_PD_PINEN_8852B,
PINMUX_GPIO2_WL_PD_FUNCEN_8852B,
PINMUX_GPIO2_WL_PD_DIS_8852B,
PINMUX_GPIO2_WL_PD_DIS_2_8852B,
PINMUX_GPIO2_BT_GPIO2_PINEN_8852B,
PINMUX_GPIO2_LTE_3W_PRI_OUT_PINEN_8852B,
PINMUX_GPIO2_LTE_3W_PRI_OUT_FUNCEN_8852B,
PINMUX_GPIO2_BT_STA_PINEN_8852B,
PINMUX_GPIO2_BT_STA_FUNCEN_8852B,
PINMUX_GPIO2_WL_STA_PINEN_8852B,
PINMUX_GPIO2_WL_STA_FUNCEN_8852B,
PINMUX_GPIO2_DBG_GNT_WL_PINEN_8852B,
PINMUX_GPIO2_WL_JTAG_TDO_PINEN_8852B,
PINMUX_GPIO2_WL_JTAG_TDO_FUNCEN_8852B,
PINMUX_GPIO2_WL_JTAG_TDO_SECEN_8852B,
PINMUX_GPIO2_WL_JTAG_TDO_DIS_8852B,
PINMUX_GPIO2_WL_RFE_CTRL2_PINEN_8852B,
PINMUX_GPIO2_DBG2_PINEN_8852B,
PINMUX_GPIO2_SW_IO02_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO3_8852B[] = {
PINMUX_GPIO3_BT_PD_PINEN_8852B,
PINMUX_GPIO3_BT_PD_FUNCEN_8852B,
PINMUX_GPIO3_BT_GPIO3_PINEN_8852B,
PINMUX_GPIO3_BT_PRI_PINEN_8852B,
PINMUX_GPIO3_BT_PRI_FUNCEN_8852B,
PINMUX_GPIO3_WL_PRI_PINEN_8852B,
PINMUX_GPIO3_WL_PRI_FUNCEN_8852B,
PINMUX_GPIO3_DBG_GNT_BT_PINEN_8852B,
PINMUX_GPIO3_WL_JTAG_TMS_PINEN_8852B,
PINMUX_GPIO3_WL_JTAG_TMS_FUNCEN_8852B,
PINMUX_GPIO3_WL_JTAG_TMS_SECEN_8852B,
PINMUX_GPIO3_WL_JTAG_TMS_DIS_8852B,
PINMUX_GPIO3_WL_RFE_CTRL3_PINEN_8852B,
PINMUX_GPIO3_DBG3_PINEN_8852B,
PINMUX_GPIO3_SW_IO3_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO4_8852B[] = {
PINMUX_GPIO4_BT_GPIO4_PINEN_8852B,
PINMUX_GPIO4_WL_FLASH0_PINEN_8852B,
PINMUX_GPIO4_WL_FLASH0_FUNCEN_8852B,
PINMUX_GPIO4_BT_FLASH0_PINEN_8852B,
PINMUX_GPIO4_BT_FLASH0_SECEN_8852B,
PINMUX_GPIO4_BT_FLASH0_FUNCEN_8852B,
PINMUX_GPIO4_WL_JTAG_TRST_PINEN_8852B,
PINMUX_GPIO4_WL_JTAG_TRST_FUNCEN_8852B,
PINMUX_GPIO4_WL_JTAG_TRST_SECEN_8852B,
PINMUX_GPIO4_WL_RFE_CTRL4_PINEN_8852B,
PINMUX_GPIO4_DBG4_PINEN_8852B,
PINMUX_GPIO4_SW_IO04_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO5_8852B[] = {
PINMUX_GPIO5_BT_GPIO5_PINEN_8852B,
PINMUX_GPIO5_WL_FLASH1_PINEN_8852B,
PINMUX_GPIO5_WL_FLASH1_FUNCEN_8852B,
PINMUX_GPIO5_BT_FLASH1_PINEN_8852B,
PINMUX_GPIO5_BT_FLASH1_FUNCEN_8852B,
PINMUX_GPIO5_BT_FLASH1_SECEN_8852B,
PINMUX_GPIO5_MAILBOX_I2C_INT_PINEN_8852B,
PINMUX_GPIO5_MAILBOX_I2C_INT_FUNCEN_8852B,
PINMUX_GPIO5_XTAL_CLK_PINEN_8852B,
PINMUX_GPIO5_XTAL_CLK_FUNCEN_8852B,
PINMUX_GPIO5_WL_JTAG_TDI_PINEN_8852B,
PINMUX_GPIO5_WL_JTAG_TDI_FUNCEN_8852B,
PINMUX_GPIO5_WL_JTAG_TDI_SECEN_8852B,
PINMUX_GPIO5_WL_RFE_CTRL5_PINEN_8852B,
PINMUX_GPIO5_DBG5_PINEN_8852B,
PINMUX_GPIO5_SW_IO5_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO6_8852B[] = {
PINMUX_GPIO6_BT_PD_PINEN_8852B,
PINMUX_GPIO6_BT_PD_FUNCEN_8852B,
PINMUX_GPIO6_BT_GPIO6_8852B,
PINMUX_GPIO6_WL_FLASH2_PINEN_8852B,
PINMUX_GPIO6_WL_FLASH2_FUNCEN_8852B,
PINMUX_GPIO6_BT_FLASH2_PINEN_8852B,
PINMUX_GPIO6_BT_FLASH2_SECEN_8852B,
PINMUX_GPIO6_BT_FLASH2_FUNCEN_8852B,
PINMUX_GPIO6_LTE_UART_IN_PINEN_8852B,
PINMUX_GPIO6_LTE_UART_IN_FUNCEN_8852B,
PINMUX_GPIO6_LTE_3W_RX_IN_PINEN_8852B,
PINMUX_GPIO6_LTE_3W_RX_IN_FUNCEN_8852B,
PINMUX_GPIO6_MAILBOX_I2C_SD_PINEN_8852B,
PINMUX_GPIO6_MAILBOX_I2C_SD_FUNCEN_8852B,
PINMUX_GPIO6_DBG_GNT_WL_PINEN_8852B,
PINMUX_GPIO6_WL_JTAG_TDO_PINEN_8852B,
PINMUX_GPIO6_WL_JTAG_TDO_FUNCEN_8852B,
PINMUX_GPIO6_WL_JTAG_TDO_SECEN_8852B,
PINMUX_GPIO6_WL_RFE6_8852B,
PINMUX_GPIO6_DBG_GPIO6_8852B,
PINMUX_GPIO6_SW_IO6_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO7_8852B[] = {
PINMUX_GPIO7_BT_PD_PINEN_8852B,
PINMUX_GPIO7_BT_PD_FUNCEN_8852B,
PINMUX_GPIO7_BT_GPIO7_PINEN_8852B,
PINMUX_GPIO7_WL_FLASH3_PINEN_8852B,
PINMUX_GPIO7_WL_FLASH3_FUNCEN_8852B,
PINMUX_GPIO7_BT_FLASH3_PINEN_8852B,
PINMUX_GPIO7_BT_FLASH3_FUNCEN_8852B,
PINMUX_GPIO7_BT_FLASH3_SECEN_8852B,
PINMUX_GPIO7_LTE_UART_OUT_PINEN_8852B,
PINMUX_GPIO7_LTE_UART_OUT_FUNCEN_8852B,
PINMUX_GPIO7_LTE_3W_TX_IN_PINEN_8852B,
PINMUX_GPIO7_LTE_3W_TX_IN_FUNCEN_8852B,
PINMUX_GPIO7_MAILBOX_I2C_CLK_PINEN_8852B,
PINMUX_GPIO7_MAILBOX_I2C_CLK_FUNCEN_8852B,
PINMUX_GPIO7_DBG_GNT_BT_PINEN_8852B,
PINMUX_GPIO7_WL_JTAG_TMS_PINEN_8852B,
PINMUX_GPIO7_WL_JTAG_TMS_FUNCEN_8852B,
PINMUX_GPIO7_WL_JTAG_TMS_SECEN_8852B,
PINMUX_GPIO7_WL_RFE_CTRL7_PINEN_8852B,
PINMUX_GPIO7_DBG7_PINEN_8852B,
PINMUX_GPIO7_SW_IO7_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO8_8852B[] = {
PINMUX_GPIO8_EXT_WOL_PINEN_8852B,
PINMUX_GPIO8_EXT_WOL_FUNCEN_8852B,
PINMUX_GPIO8_BT_GPIO8_8852B,
PINMUX_GPIO8_SIC_CLK_PINEN_8852B,
PINMUX_GPIO8_SIC_CLK_FUNCEN_8852B,
PINMUX_GPIO8_SIC_CLK_SECEN_8852B,
PINMUX_GPIO8_MAILBOX_I2C_INT_PINEN_8852B,
PINMUX_GPIO8_MAILBOX_I2C_INT_FUNCEN_8852B,
PINMUX_GPIO8_WL_LED_PINEN_8852B,
PINMUX_GPIO8_WL_LED_FUNCEN_8852B,
PINMUX_GPIO8_WL_UART_TX_PINEN_8852B,
PINMUX_GPIO8_WL_UART_TX_FUNCEN_8852B,
PINMUX_GPIO8_WL_UART_TX_SECEN_8852B,
PINMUX_GPIO8_WL_RFE8_8852B,
PINMUX_GPIO8_DBG_GPIO8_8852B,
PINMUX_GPIO8_SW_IO8_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO9_8852B[] = {
PINMUX_GPIO9_WL_PD_PINEN_8852B,
PINMUX_GPIO9_BT_GPIO9_PINEN_8852B,
PINMUX_GPIO9_MAILBOX_I2C_SD_PINEN_8852B,
PINMUX_GPIO9_MAILBOX_I2C_SD_FUNCEN_8852B,
PINMUX_GPIO9_DBG_GNT_WL_PINEN_8852B,
PINMUX_GPIO9_WL_UART_TX_PINEN_8852B,
PINMUX_GPIO9_WL_UART_TX_FUNCEN_8852B,
PINMUX_GPIO9_WL_UART_TX_SECEN_8852B,
PINMUX_GPIO9_WL_RFE_CTRL9_PINEN_8852B,
PINMUX_GPIO9_DBG9_PINEN_8852B,
PINMUX_GPIO9_SW_IO9_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO10_8852B[] = {
PINMUX_GPIO10_BT_GPIO10_8852B,
PINMUX_GPIO10_WL_SDIO_INT_PINEN_8852B,
PINMUX_GPIO10_WL_UART_RX_PINEN_8852B,
PINMUX_GPIO10_WL_UART_RX_FUNCEN_8852B,
PINMUX_GPIO10_WL_UART_RX_SECEN_8852B,
PINMUX_GPIO10_WL_UART_RX_DIS_8852B,
PINMUX_GPIO10_WL_UART_RX_DIS_2_8852B,
PINMUX_GPIO10_WL_RFE10_8852B,
PINMUX_GPIO10_DBG_GPIO10_8852B,
PINMUX_GPIO10_SW_IO10_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO11_8852B[] = {
PINMUX_GPIO11_BT_PD_PINEN_8852B,
PINMUX_GPIO11_BT_GPIO11_PINEN_8852B,
PINMUX_GPIO11_MAILBOX_I2C_CLK_PINEN_8852B,
PINMUX_GPIO11_MAILBOX_I2C_CLK_FUNCEN_8852B,
PINMUX_GPIO11_DBG_GNT_BT_PINEN_8852B,
PINMUX_GPIO11_WL_UART_RX_PINEN_8852B,
PINMUX_GPIO11_WL_UART_RX_SECEN_8852B,
PINMUX_GPIO11_WL_UART_RX_FUNCEN_8852B,
PINMUX_GPIO11_WL_UART_RX_DIS_8852B,
PINMUX_GPIO11_WL_UART_RX_DIS_2_8852B,
PINMUX_GPIO11_WL_RFE_CTRL11_PINEN_8852B,
PINMUX_GPIO11_DBG11_PINEN_8852B,
PINMUX_GPIO11_SW_IO11_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO12_8852B[] = {
PINMUX_GPIO12_BT_GPIO12_8852B,
PINMUX_GPIO12_LTE_3W_PRI_OUT_PINEN_8852B,
PINMUX_GPIO12_LTE_3W_PRI_OUT_FUNCEN_8852B,
PINMUX_GPIO12_WL_ACT_PINEN_8852B,
PINMUX_GPIO12_WL_ACT_FUNCEN_8852B,
PINMUX_GPIO12_BT_ACT_PINEN_8852B,
PINMUX_GPIO12_BT_ACT_FUNCEN_8852B,
PINMUX_GPIO12_BT_ACT_DIS_8852B,
PINMUX_GPIO12_DBG_GNT_WL_PINEN_8852B,
PINMUX_GPIO12_SOUT_PINEN_8852B,
PINMUX_GPIO12_SOUT_SECEN_8852B,
PINMUX_GPIO12_SOUT_FUNCEN_8852B,
PINMUX_GPIO12_WL_RFE12_8852B,
PINMUX_GPIO12_DBG_GPIO12_8852B,
PINMUX_GPIO12_SW_IO12_PINEN_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO13_8852B[] = {
PINMUX_GPIO13_BT_GPIO13_8852B,
PINMUX_GPIO13_WL_PTA_BT_CLK_PINEN_8852B,
PINMUX_GPIO13_WL_PTA_BT_CLK_FUNCEN_8852B,
PINMUX_GPIO13_BT_PTA_WL_CLK_PINEN_8852B,
PINMUX_GPIO13_BT_PTA_WL_CLK_FUNCEN_8852B,
PINMUX_GPIO13_WL_UART_TX_PINEN_8852B,
PINMUX_GPIO13_WL_UART_TX_SECEN_8852B,
PINMUX_GPIO13_WL_UART_TX_FUNCEN_8852B,
PINMUX_GPIO13_WL_RFE_CTRL13_8852B,
PINMUX_GPIO13_DBG13_8852B,
PINMUX_GPIO13_SW_IO13_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO14_8852B[] = {
PINMUX_GPIO14_BT_GPIO14_8852B,
PINMUX_GPIO14_WL_PTA_BT_STA_PINEN_8852B,
PINMUX_GPIO14_WL_PTA_BT_STA_FUNCEN_8852B,
PINMUX_GPIO14_BT_PTA_WL_STA_PINEN_8852B,
PINMUX_GPIO14_BT_PTA_WL_STA_FUNCEN_8852B,
PINMUX_GPIO14_WL_JTAG_CLK_PINEN_8852B,
PINMUX_GPIO14_WL_JTAG_CLK_FUNCEN_8852B,
PINMUX_GPIO14_WL_JTAG_CLK_SECEN_8852B,
PINMUX_GPIO14_WL_RFE_CTRL13_8852B,
PINMUX_GPIO14_DBG14_8852B,
PINMUX_GPIO14_SW_IO14_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO15_8852B[] = {
PINMUX_GPIO15_WL_PD_PINEN_8852B,
PINMUX_GPIO15_BT_GPIO15_8852B,
PINMUX_GPIO15_WL_PTA_BT_CLK_PINEN_8852B,
PINMUX_GPIO15_WL_PTA_BT_CLK_FUNCEN_8852B,
PINMUX_GPIO15_BT_PTA_WL_CLK_PINEN_8852B,
PINMUX_GPIO15_BT_PTA_WL_CLK_FUNCEN_8852B,
PINMUX_GPIO15_WL_UART_TX_PINEN_8852B,
PINMUX_GPIO15_WL_UART_TX_SECEN_8852B,
PINMUX_GPIO15_WL_UART_TX_FUNCEN_8852B,
PINMUX_GPIO15_WL_RFE_CTRL15_8852B,
PINMUX_GPIO15_DBG15_8852B,
PINMUX_GPIO15_SW_IO15_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO16_8852B[] = {
PINMUX_GPIO16_WL_RFE_CTRL16_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list PIN_LIST_GPIO17_8852B[] = {
PINMUX_GPIO17_WL_RFE_CTRL17_8852B,
PINMUX_GPIO_END_8852B,
};
static const struct mac_ax_pin_list *PIN_LIST_8852B[] = {
PIN_LIST_GPIO0_8852B, /* gpio0 */
PIN_LIST_GPIO1_8852B, /* gpio1 */
PIN_LIST_GPIO2_8852B, /* gpio2 */
PIN_LIST_GPIO3_8852B, /* gpio3 */
PIN_LIST_GPIO4_8852B, /* gpio4 */
PIN_LIST_GPIO5_8852B, /* gpio5 */
PIN_LIST_GPIO6_8852B, /* gpio6 */
PIN_LIST_GPIO7_8852B, /* gpio7 */
PIN_LIST_GPIO8_8852B, /* gpio8 */
PIN_LIST_GPIO9_8852B, /* gpio9 */
PIN_LIST_GPIO10_8852B, /* gpio10 */
PIN_LIST_GPIO11_8852B, /* gpio11 */
PIN_LIST_GPIO12_8852B, /* gpio12 */
PIN_LIST_GPIO13_8852B, /* gpio13 */
PIN_LIST_GPIO14_8852B, /* gpio14 */
PIN_LIST_GPIO15_8852B, /* gpio15 */
PIN_LIST_GPIO16_8852B, /* gpio16 */
PIN_LIST_GPIO17_8852B, /* gpio17 */
};
static u32 mac_get_pinmux_list_8852b(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func,
const struct mac_ax_pinmux_list **list,
u32 *list_size, u32 *gpio_id)
{
switch (func) {
case MAC_AX_GPIO_SW_IO_0:
*list = PINMUX_LIST_GPIO0_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8852B);
*gpio_id = MAC_AX_GPIO0;
break;
case MAC_AX_GPIO_SW_IO_1:
*list = PINMUX_LIST_GPIO1_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8852B);
*gpio_id = MAC_AX_GPIO1;
break;
case MAC_AX_GPIO_SW_IO_2:
*list = PINMUX_LIST_GPIO2_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8852B);
*gpio_id = MAC_AX_GPIO2;
break;
case MAC_AX_GPIO_SW_IO_3:
*list = PINMUX_LIST_GPIO3_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8852B);
*gpio_id = MAC_AX_GPIO3;
break;
case MAC_AX_GPIO_SW_IO_4:
*list = PINMUX_LIST_GPIO4_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8852B);
*gpio_id = MAC_AX_GPIO4;
break;
case MAC_AX_GPIO_SW_IO_5:
case MAC_AX_GPIO_UART_TX_GPIO5:
*list = PINMUX_LIST_GPIO5_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8852B);
*gpio_id = MAC_AX_GPIO5;
break;
case MAC_AX_GPIO_SW_IO_6:
case MAC_AX_GPIO_UART_RX_GPIO6:
*list = PINMUX_LIST_GPIO6_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8852B);
*gpio_id = MAC_AX_GPIO6;
break;
case MAC_AX_GPIO_SW_IO_7:
case MAC_AX_GPIO_UART_TX_GPIO7:
*list = PINMUX_LIST_GPIO7_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8852B);
*gpio_id = MAC_AX_GPIO7;
break;
case MAC_AX_GPIO_SW_IO_8:
case MAC_AX_GPIO_UART_TX_GPIO8:
*list = PINMUX_LIST_GPIO8_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8852B);
*gpio_id = MAC_AX_GPIO8;
break;
case MAC_AX_GPIO_SW_IO_9:
*list = PINMUX_LIST_GPIO9_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8852B);
*gpio_id = MAC_AX_GPIO9;
break;
case MAC_AX_GPIO_SW_IO_10:
*list = PINMUX_LIST_GPIO10_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8852B);
*gpio_id = MAC_AX_GPIO10;
break;
case MAC_AX_GPIO_SW_IO_11:
*list = PINMUX_LIST_GPIO11_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8852B);
*gpio_id = MAC_AX_GPIO11;
break;
case MAC_AX_GPIO_SW_IO_12:
*list = PINMUX_LIST_GPIO12_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8852B);
*gpio_id = MAC_AX_GPIO12;
break;
case MAC_AX_GPIO_SW_IO_13:
*list = PINMUX_LIST_GPIO13_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8852B);
*gpio_id = MAC_AX_GPIO13;
break;
case MAC_AX_GPIO_SW_IO_14:
case MAC_AX_GPIO_UART_RX_GPIO14:
*list = PINMUX_LIST_GPIO14_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8852B);
*gpio_id = MAC_AX_GPIO14;
break;
case MAC_AX_GPIO_SW_IO_15:
*list = PINMUX_LIST_GPIO15_8852B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8852B);
*gpio_id = MAC_AX_GPIO15;
break;
default:
return MACNOITEM;
}
return MACSUCCESS;
}
u32 mac_pinmux_set_func_8852b(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func)
{
const struct mac_ax_pinmux_list *list = NULL;
u32 ret;
u32 gpio_id, list_size;
ret = mac_pinmux_status(adapter, func);
if (ret)
goto END;
ret = mac_get_pinmux_list_8852b(adapter, func, &list,
&list_size, &gpio_id);
if (ret)
goto END;
ret = mac_pinmux_switch(adapter, func, list, list_size, gpio_id);
if (ret)
goto END;
ret = mac_pinmux_record(adapter, func, 1);
END:
return ret;
}
u32 mac_set_gpio_func_8852b(struct mac_ax_adapter *adapter,
enum rtw_mac_gfunc func, s8 gpio_cfg)
{
const struct mac_ax_pin_list *list;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val, is_set = 0;
u8 gpio;
if (gpio_cfg < MAC_AX_GPIO_MIN || gpio_cfg > RTW_MAC_GPIO_MAX) {
PLTFM_MSG_ERR("The GPIO number is wrong: %d", gpio_cfg);
return MACGPIONUM;
}
gpio = gpio_cfg;
list = PIN_LIST_8852B[gpio];
while (list && list->func != RTW_MAC_GPIO_INVALID) {
if (list->func == func) {
val = MAC_REG_R8(list->offset);
val = (val & ~(list->msk)) | list->value;
MAC_REG_W8(list->offset, val);
is_set++;
}
list++;
}
if (!is_set) {
PLTFM_MSG_ERR("The GPIO function is NOT available in %d", gpio);
return MACNOITEM;
}
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.c
|
C
|
agpl-3.0
| 67,257
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_GPIO_8852B_H_
#define _MAC_AX_GPIO_8852B_H_
#include "../../type.h"
/**
* @brief mac_pinmux_set_func_8852b
*
* @param *adapter
* @param func
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pinmux_set_func_8852b(struct mac_ax_adapter *adapter,
enum mac_ax_gpio_func func);
/**
* @brief mac_set_gpio_func_8852b
*
* @param *adapter
* @param func
* @param gpio
* @return Please Place Description here.
* @retval u32
*/
u32 mac_set_gpio_func_8852b(struct mac_ax_adapter *adapter,
enum rtw_mac_gfunc func, s8 gpio);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/gpio_8852b.h
|
C
|
agpl-3.0
| 1,272
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "init_8852b.h"
#include "../pwr.h"
#include "../efuse.h"
#include "../init.h"
#include "../trxcfg.h"
#include "pwr_seq_8852b.h"
#include "pwr_seq_func_8852b.h"
#include "../hw.h"
#include "../security_cam.h"
#include "../trx_desc.h"
#include "../../feature_cfg.h"
#include "../fwcmd.h"
#include "../fwdl.h"
#include "../fwofld.h"
#include "../role.h"
#include "../tblupd.h"
#include "../rx_forwarding.h"
#include "../rx_filter.h"
#include "../phy_rpt.h"
#include "../hwamsdu.h"
#include "../status.h"
#include "../hdr_conv.h"
#include "../hw_seq.h"
#include "gpio_8852b.h"
#include "../gpio.h"
#include "../cpuio.h"
#include "../sounding.h"
#include "../power_saving.h"
#include "../wowlan.h"
#include "../tcpip_checksum_offload.h"
#include "../la_mode.h"
#include "../dle.h"
#include "../coex.h"
#include "../mcc.h"
#include "../twt.h"
#include "../mport.h"
#include "../p2p.h"
#include "../flash.h"
#include "../dbg_cmd.h"
#include "../phy_misc.h"
#include "../h2c_agg.h"
#if MAC_AX_SDIO_SUPPORT
#include "../_sdio.h"
#endif
#if MAC_AX_USB_SUPPORT
#include "_usb_8852b.h"
#endif
#if MAC_AX_PCIE_SUPPORT
#include "../_pcie.h"
#endif
#if MAC_AX_FEATURE_DBGPKG
#include "../dbgpkg.h"
#include "../dbgport_hw.h"
#endif
#if MAC_AX_SDIO_SUPPORT
static struct mac_ax_intf_ops mac8852b_sdio_ops = {
reg_read8_sdio, /* reg_read8 */
reg_write8_sdio, /* reg_write8 */
reg_read16_sdio, /* reg_read16 */
reg_write16_sdio, /* reg_write16 */
reg_read32_sdio, /* reg_read32 */
reg_write32_sdio, /* reg_write32 */
tx_allow_sdio, /* tx_allow_sdio */
tx_cmd_addr_sdio, /* tx_cmd_addr_sdio */
sdio_pre_init, /* intf_pre_init */
sdio_init, /* intf_init */
sdio_deinit, /* intf_init */
reg_read_n_sdio, /* reg_read_n_sdio */
NULL, /*get_bulkout_id*/
NULL, /* ltr_set_pcie */
NULL, /*u2u3_switch*/
NULL, /*get_usb_mode*/
NULL, /*get_usb_support_ability*/
NULL, /*usb_tx_agg_cfg*/
NULL, /*usb_rx_agg_cfg*/
set_sdio_wowlan, /*set_wowlan*/
NULL, /*ctrl_txdma_ch*/
NULL, /*clr_idx_all*/
NULL, /*poll_txdma_ch_idle*/
NULL, /*poll_rxdma_ch_idle*/
NULL, /*ctrl_txhci*/
NULL, /*ctrl_rxhci*/
NULL, /*ctrl_dma_io*/
NULL, /* get_io_stat */
sdio_get_txagg_num, /*get_txagg_num*/
NULL, /*get_usb_rx_state*/
};
#endif
#if MAC_AX_USB_SUPPORT
static struct mac_ax_intf_ops mac8852b_usb_ops = {
reg_read8_usb_8852b, /* reg_read8 */
reg_write8_usb_8852b, /* reg_write8 */
reg_read16_usb_8852b, /* reg_read16 */
reg_write16_usb_8852b, /* reg_write16 */
reg_read32_usb_8852b, /* reg_read32 */
reg_write32_usb_8852b, /* reg_write32 */
NULL, /* tx_allow_sdio */
NULL, /* tx_cmd_addr_sdio */
usb_pre_init_8852b, /* intf_pre_init */
usb_init_8852b, /* intf_init */
usb_deinit_8852b, /* intf_init */
NULL, /* reg_read_n_sdio */
get_bulkout_id_8852b, /*get_bulkout_id*/
NULL, /* ltr_set_pcie */
u2u3_switch_8852b, /*u2u3_switch*/
get_usb_mode, /*get_usb_mode*/
get_usb_support_ability_8852b,/*get_usb_support_ability*/
usb_tx_agg_cfg_8852b, /*usb_tx_agg_cfg*/
usb_rx_agg_cfg_8852b, /*usb_rx_agg_cfg*/
set_usb_wowlan_8852b, /*set_wowlan*/
NULL, /*ctrl_txdma_ch*/
NULL, /*clr_idx_all*/
NULL, /*poll_txdma_ch_idle*/
NULL, /*poll_rxdma_ch_idle*/
NULL, /*ctrl_txhci*/
NULL, /*ctrl_rxhci*/
NULL, /*ctrl_dma_io*/
NULL, /* get_io_stat */
usb_get_txagg_num_8852b, /*get_txagg_num*/
usb_get_rx_state_8852b, /*get_usb_rx_state*/
};
#endif
#if MAC_AX_PCIE_SUPPORT
static struct mac_ax_intf_ops mac8852b_pcie_ops = {
reg_read8_pcie, /* reg_read8 */
reg_write8_pcie, /* reg_write8 */
reg_read16_pcie, /* reg_read16 */
reg_write16_pcie, /* reg_write16 */
reg_read32_pcie, /* reg_read32 */
reg_write32_pcie, /* reg_write32 */
NULL, /* tx_allow_sdio */
NULL, /* tx_cmd_addr_sdio */
pcie_pre_init, /* intf_pre_init */
pcie_init, /* intf_init */
pcie_deinit, /* intf_init */
NULL, /* reg_read_n_sdio */
NULL, /*get_bulkout_id*/
ltr_set_pcie, /* ltr_set_pcie */
NULL, /*u2u3_switch*/
NULL, /*get_usb_mode*/
NULL, /*get_usb_support_ability*/
NULL, /*usb_tx_agg_cfg*/
NULL, /*usb_rx_agg_cfg*/
set_pcie_wowlan, /*set_wowlan*/
ctrl_txdma_ch_pcie, /*ctrl_txdma_ch*/
clr_idx_all_pcie, /*clr_idx_all*/
poll_txdma_ch_idle_pcie, /*poll_txdma_ch_idle*/
poll_rxdma_ch_idle_pcie, /*poll_rxdma_ch_idle*/
ctrl_txhci_pcie, /*ctrl_txhci*/
ctrl_rxhci_pcie, /*ctrl_rxhci*/
ctrl_dma_io_pcie, /*ctrl_dma_io*/
get_io_stat_pcie, /* get_io_stat */
pcie_get_txagg_num, /*get_txagg_num*/
NULL, /*get_usb_rx_state*/
};
#endif
static struct mac_ax_ops mac8852b_ops = {
NULL, /* intf_ops */
/*System level*/
mac_hal_init, /* hal_init */
mac_hal_fast_init, /* hal_fast_init */
mac_hal_deinit, /* hal_deinit */
mac_hal_fast_deinit, /*hal_fast_deinit*/
mac_add_role, /* add_role */
mac_remove_role, /* remove_role */
mac_change_role, /* change_role */
mac_pwr_switch, /* pwr_switch */
mac_sys_init, /* sys_init */
mac_trx_init, /* init */
mac_romdl, /* romdl */
mac_enable_cpu, /* enable_cpu */
mac_disable_cpu, /* disable_cpu */
mac_fwredl, /* fwredl */
mac_fwdl, /* fwdl */
mac_enable_fw, /* enable_fw */
mac_lv1_rcvy, /* lv1_rcvy */
mac_get_macaddr,
mac_build_txdesc, /* build_txdesc */
mac_refill_txdesc, /*refill txdesc*/
mac_parse_rxdesc, /* parse_rxdesc */
/*FW offload related*/
mac_reset_fwofld_state,
mac_check_fwofld_done,
mac_read_pkt_ofld,
mac_del_pkt_ofld,
mac_add_pkt_ofld,
mac_pkt_ofld_packet,
mac_dump_efuse_ofld,
mac_efuse_ofld_map,
mac_upd_dctl_info, /*update dmac ctrl info*/
mac_upd_cctl_info, /*update cmac ctrl info*/
mac_ie_cam_upd, /* ie_cam_upd */
mac_twt_info_upd_h2c, /* twt info update h2c */
mac_twt_act_h2c, /* twt act h2c */
mac_twt_staanno_h2c, /* twt anno h2c */
mac_twt_wait_anno,
mac_host_getpkt_h2c,
mac_p2p_act_h2c, /* p2p_act_h2c */
mac_p2p_macid_ctrl_h2c, /* p2p_macid_ctrl_h2c */
mac_get_p2p_stat, /* get_p2p_stat */
mac_tsf32_togl_h2c, /* tsf32_togl_h2c */
mac_get_t32_togl_rpt, /* get_t32_togl_rpt */
mac_ccxrpt_parsing,
/*Association, de-association related*/
mac_sta_add_key, /* add station key */
mac_sta_del_key, /* del station key */
mac_sta_search_key_idx, /* search station key index */
mac_sta_hw_security_support, /* control hw security support */
mac_sta_keycam_backup, /* sta keycam backup restore control */
mac_set_mu_table, /*set mu score table*/
mac_ss_dl_grp_upd, /* update SS dl group info*/
mac_ss_ul_grp_upd, /* update SS ul group info*/
mac_ss_ul_sta_upd, /* add sta into SS ul link*/
mac_bacam_info, /*update BA CAM info*/
/*TRX related*/
mac_txdesc_len, /* txdesc_len */
mac_upd_shcut_mhdr,/*update short cut mac header*/
mac_enable_hwmasdu, /* enable_hwmasdu */
mac_enable_cut_hwamsdu, /* enable_cut_hwamsdu */
mac_hdr_conv, /* hdr_conv */
mac_set_hwseq_reg, /* set hw seq by reg */
mac_process_c2h, /* process_c2h */
mac_parse_dfs, /* parse_dfs */
mac_parse_ppdu, /* parse_ppdu */
mac_cfg_phy_rpt, /* cfg_phy_rpt */
mac_set_rx_forwarding, /*rx_forwarding */
mac_get_rx_fltr_opt, /* set rx fltr mac, pclp header opt */
mac_set_rx_fltr_opt, /* get rx fltr mac, pclp header opt */
mac_set_typ_fltr_opt, /* set machdr type fltr opt */
mac_set_typsbtyp_fltr_opt, /* set machdr typ subtyp fltr opt */
mac_set_typsbtyp_fltr_detail, /* set detail type subtype filter config*/
mac_get_cfg_addr_cam, /* get addrcam setting */
mac_get_cfg_addr_cam_dis, /* get addrcam disable default setting */
mac_cfg_addr_cam, /* config addrcam setting */
mac_cfg_addr_cam_dis, /* config addrcam disable default setting */
mac_sr_update, /* set sr parameter */
mac_two_nav_cfg, /* config 2NAV hw setting */
mac_wde_pkt_drop, /* pkt_drop */
mac_send_bcn_h2c, /* send beacon h2c */
mac_tx_mode_sel, /*tx mode sel*/
mac_tcpip_chksum_ofd, /* tcpip_chksum_ofd */
mac_chk_rx_tcpip_chksum_ofd, /* chk_rx_tcpip_chksum_ofd */
mac_chk_allq_empty, /*chk_allq_empty*/
mac_is_txq_empty, /*is_txq_empty*/
mac_is_rxq_empty, /*is_rxq_empty*/
mac_parse_bcn_stats_c2h, /*parse tx bcn statistics*/
mac_tx_idle_poll, /*tx_idle_poll*/
mac_sifs_chk_cca_en, /*mac_sifs_chk_cca_en*/
mac_patch_rx_rate, /*for patch rx rate error*/
/*frame exchange related*/
mac_upd_mudecision_para, /* upd_ba_infotbl */
mac_mu_sta_upd, /* upd_mu_sta */
mac_upd_ul_fixinfo, /* upd_ul_fixinfo */
mac_f2p_test_cmd, /*f2p test cmd para*/
mac_snd_test_cmd, /* f2p test cmd para */
mac_set_fixmode_mib, /* set_fw_testmode */
mac_dumpwlanc,
mac_dumpwlans,
mac_dumpwland,
/*outsrcing related */
mac_outsrc_h2c_common, /* outsrc common h2c */
mac_read_pwr_reg, /* for read tx power reg*/
mac_write_pwr_reg, /* for write tx power reg*/
mac_write_msk_pwr_reg, /* for write tx power reg*/
mac_write_pwr_ofst_mode, /* for write tx power mode offset reg*/
mac_write_pwr_ofst_bw, /* for write tx power BW offset reg*/
mac_write_pwr_ref_reg, /* for write tx power ref reg*/
mac_write_pwr_limit_en, /* for write tx power limit enable reg*/
mac_write_pwr_limit_rua_reg, /* for write tx power limit rua reg*/
mac_write_pwr_limit_reg, /* for write tx power limit reg*/
mac_write_pwr_by_rate_reg, /* for write tx power by rate reg*/
mac_lamode_cfg, /*cfg la mode para*/
mac_lamode_trigger, /*trigger la mode start*/
mac_lamode_buf_cfg, /*la mode buf size cfg */
mac_get_lamode_st, /*get la mode status*/
mac_read_xcap_reg_dav, /*read xcap xo/xi reg*/
mac_write_xcap_reg_dav, /*write xcap xo/xi reg*/
mac_write_bbrst_reg, /*write bb rst reg*/
/*sounding related*/
mac_get_csi_buffer_index, /* get CSI buffer index */
mac_set_csi_buffer_index, /* set CSI buffer index */
mac_get_snd_sts_index, /* get MACID SND status */
mac_set_snd_sts_index, /* set SND status MACID */
mac_init_snd_mer,/* init SND MER */
mac_init_snd_mee,/* init SND MEE */
mac_csi_force_rate, /*CSI fix rate reg*/
mac_csi_rrsc, /*CSI RRSC*/
mac_set_snd_para, /*set sound parameter*/
mac_set_csi_para_reg, /*set reg csi para*/
mac_set_csi_para_cctl, /*set csi para in cmac ctrl info*/
mac_hw_snd_pause_release, /*HW SND pause release*/
mac_bypass_snd_sts, /*bypass SND status*/
mac_deinit_mee, /*deinit mee*/
mac_snd_sup, /*bf entry num and SU MU buffer num*/
mac_gidpos, /*VHT MU GID position setting*/
/*lps related*/
mac_cfg_lps, /*config LPS*/
mac_lps_pwr_state, /*set or check lps power state*/
mac_chk_leave_lps, /*check already leave protocol ps*/
/* Wowlan related*/
mac_cfg_wow_wake, /*config wowlan wake*/
mac_cfg_disconnect_det, /*config disconnect det*/
mac_cfg_keep_alive, /*config keep alive*/
mac_cfg_gtk_ofld, /*config gtk ofld*/
mac_cfg_arp_ofld, /*config arp ofld*/
mac_cfg_ndp_ofld, /*config ndp ofld*/
mac_cfg_realwow, /*config realwow*/
mac_cfg_nlo, /*config nlo*/
mac_cfg_dev2hst_gpio, /*config dev2hst gpio*/
mac_cfg_uphy_ctrl, /*config uphy ctrl*/
mac_cfg_wowcam_upd, /*config wowcam update*/
mac_get_wow_wake_rsn, /* Get wowlan wakeup reason with reset option */
mac_cfg_wow_sleep, /*config wowlan before sleep/after wake*/
mac_get_wow_fw_status, /*get wowlan fw status*/
mac_request_aoac_report, /* request_aoac_report */
mac_read_aoac_report, /* read_aoac_report */
mac_check_aoac_report_done, /* check_aoac_report_done */
mac_wow_stop_trx, /* wow_stop_trx */
/*system related*/
mac_dbcc_enable, /*enable / disable dbcc */
mac_port_cfg, /* cofig port para */
mac_port_init, /* init port para */
mac_enable_imr, /* enable CMAC/DMAC IMR */
mac_dump_efuse_map_wl_plus, /* dump_wl_efuse*/
mac_dump_efuse_map_bt, /* dump_bt_efuse */
mac_write_efuse_plus, /* write_wl_bt_efuse */
mac_read_efuse_plus, /* read_wl_bt_efuse */
mac_get_efuse_avl_size, /* get_available_efuse_size */
mac_get_efuse_avl_size_bt, /* get_available_efuse_size_bt */
mac_dump_log_efuse_plus, /* dump_logical_efuse */
mac_read_log_efuse_plus, /* read_logical_efuse */
mac_write_log_efuse_plus, /* write_logical_efuse */
mac_dump_log_efuse_bt, /* dump_logical_efuse_bt */
mac_read_log_efuse_bt, /* read_logical_efuse_bt */
mac_write_log_efuse_bt, /* write_logical_efuse_bt */
mac_pg_efuse_by_map_plus, /* program_efuse_map */
mac_pg_efuse_by_map_bt, /* program_efuse_map_bt */
mac_mask_log_efuse, /* mask_logical_efuse_map */
mac_pg_sec_data_by_map, /* program_secure_data_map */
mac_cmp_sec_data_by_map, /* compare_secure_data_map */
mac_get_efuse_info, /* get_efuse_info */
mac_set_efuse_info, /* set_efuse_info */
mac_read_hidden_rpt, /* read_efuse_hidden_report */
mac_check_efuse_autoload, /* check_efuse_autoload */
mac_pg_simulator_plus, /* efuse pg simulator */
mac_checksum_update, /* checksum update */
mac_checksum_rpt, /*report checksum comparison result*/
mac_disable_rf, /* Disable RF Offload */
mac_set_efuse_ctrl, /*set efuse ctrl 0x30 or 0xC30*/
mac_otp_test, /*efuse OTP test R/W to 0x7ff*/
mac_get_ft_status, /* get_mac_ft_status */
mac_fw_log_cfg, /* fw_log_cfg */
mac_pinmux_set_func_8852b, /* pinmux_set_func */
mac_pinmux_free_func, /* pinmux_free_func */
mac_sel_uart_tx_pin, /* sel_uart_tx_pin */
mac_sel_uart_rx_pin, /* sel_uart_rx_pin */
mac_set_gpio_func_8852b, /* set_gpio_func */
mac_get_hw_info, /* get_hw_info */
mac_set_hw_value, /* set_hw_value */
mac_get_hw_value, /* get_hw_value */
mac_get_err_status, /* get_err_status */
mac_set_err_status, /* set_err_status */
mac_general_pkt_ids, /*general_pkt_ids */
mac_coex_init, /* coex_init */
mac_read_coex_reg, /* coex_read */
mac_write_coex_reg, /* coex_write */
mac_trigger_cmac_err, /*trigger_cmac_err*/
mac_trigger_cmac1_err, /*trigger_cmac1_err*/
mac_trigger_dmac_err, /*trigger_dmac_err*/
mac_tsf_sync, /*tsf_sync*/
mac_read_xtal_si, /*read_xtal_si*/
mac_write_xtal_si, /*write_xtal_si*/
mac_io_chk_access, /* io_chk_access */
mac_ser_ctrl, /* ser_ctrl */
/* mcc */
mac_reset_mcc_group,
mac_reset_mcc_request,
mac_add_mcc, /* add_mcc */
mac_start_mcc, /* start_mcc */
mac_stop_mcc, /* stop_mcc */
mac_del_mcc_group, /* del_mcc_group */
mac_mcc_request_tsf, /* mcc_request_tsf */
mac_mcc_macid_bitmap, /* mcc_macid_bitmap */
mac_mcc_sync_enable, /* mcc_sync_enable */
mac_mcc_set_duration, /* mcc_set_duration */
mac_get_mcc_tsf_rpt,
mac_get_mcc_status_rpt,
mac_get_mcc_group,
mac_check_add_mcc_done,
mac_check_start_mcc_done,
mac_check_stop_mcc_done,
mac_check_del_mcc_group_done,
mac_check_mcc_request_tsf_done,
mac_check_mcc_macid_bitmap_done,
mac_check_mcc_sync_enable_done,
mac_check_mcc_set_duration_done,
/* not mcc */
mac_check_access,
mac_set_led_mode, /* set_led_mode */
mac_led_ctrl, /* led_ctrl */
mac_set_sw_gpio_mode, /* set_sw_gpio_mode */
mac_sw_gpio_ctrl, /* sw_gpio_ctrl */
mac_get_c2h_event, /* get_c2h_event */
mac_cfg_wps, /* cfg_wps */
mac_get_wl_dis_val, /* get_wl_dis_val */
#if MAC_AX_FEATURE_DBGPKG
mac_fwcmd_lb, /* fwcmd_lb */
mac_mem_dump, /* sram mem dump */
mac_get_mem_size, /* get mem size */
mac_dbg_status_dump, /* mac dbg status dump */
mac_reg_dump, /* debug reg dump for MAC/BB/RF*/
mac_rx_cnt,
mac_dump_fw_rsvd_ple,
mac_dump_ple_dbg_page, /* dump_ple_dbg_page */
mac_fw_dbg_dump,
mac_event_notify,
mac_dbgport_hw_set, /* Set debug port for LA */
#endif
#if MAC_AX_FEATURE_HV
mac_ram_boot, /* ram_boot */
/*fw offload related*/
mac_clear_write_request, /* clear_write_request */
mac_add_write_request, /* add_write_request */
mac_write_ofld, /* write_ofld */
mac_clear_conf_request, /* clear_conf_request */
mac_add_conf_request, /* add_conf_request */
mac_conf_ofld, /* conf_ofld */
mac_clear_read_request, /* clear_read_request */
mac_add_read_request, /* add_read_request */
mac_read_ofld, /* read_ofld */
mac_read_ofld_value, /* read_ofld_value */
#endif
mac_add_cmd_ofld, /* add_cmd_ofld */
mac_flash_erase,
mac_flash_read,
mac_flash_write,
mac_fw_status_cmd, /* fw_status_cmd */
mac_fwc2h_ofdma_sts_parse, /* parse c2h fw sts */
mac_fw_ofdma_sts_en, /* send fw sts en to fw */
mac_tx_duty, /* tx_duty */
mac_tx_duty_stop, /* tx_duty _stop */
#if MAC_AX_FEATURE_DBGCMD
mac_halmac_cmd, /* halmac_cmd */
mac_halmac_cmd_parser, /* halmac_cmd_parser */
#endif
mac_fast_ch_sw,
mac_fast_ch_sw_done,
mac_get_fast_ch_sw_rpt,
mac_write_coex_mask,
mac_fw_dbg_dle_cfg,
mac_h2c_agg_enable,
mac_h2c_agg_flush,
mac_h2c_agg_tx,
#if MAC_AX_FEATURE_DBGDEC
mac_fw_log_set_array,
mac_fw_log_unset_array,
#endif
mac_get_fw_status
};
static struct mac_ax_hw_info mac8852b_hw_info = {
0, /* done */
MAC_AX_CHIP_ID_8852B, /* chip_id */
0xFF, /* cv */
MAC_AX_INTF_INVALID, /* intf */
19, /* tx_ch_num */
10, /* tx_data_ch_num */
WD_BODY_LEN, /* wd_body_len */
WD_INFO_LEN, /* wd_info_len */
pwr_on_seq_8852b, /* pwr_on_seq */
pwr_off_seq_8852b, /* pwr_off_seq */
PWR_SEQ_VER_8852B, /* pwr_seq_ver */
196608, /* fifo_size */
32, /* macid_num */
5, /* port_num */
4, /* mbssid_num */
20, /* bssid_num */
1536, /* wl_efuse_size */
1216, /* wl_zone2_efuse_size */
2048, /* log_efuse_size */
1280, /* limit_efuse_size_PCIE */
1280, /* limit_efuse_size_USB */
1280, /* limit_efuse_size_SDIO */
512, /* bt_efuse_size */
1024, /* bt_log_efuse_size */
32, /*hidden_efuse_size*/
4, /* sec_ctrl_efuse_size */
192, /* sec_data_efuse_size */
NULL, /* sec_cam_table_t pointer */
NULL, /* sec_cam_table_bk pointer */
32, /* ple_rsvd_space */
24, /* payload_desc_size */
8, /* efuse_version_size */
128, /* wl_efuse_size_DAV */
96, /* wl_zone2_efuse_size_DAV */
32, /* hidden_efuse_size_DAV */
16, /* log_efuse_size_DAV */
0, /* wl_efuse_start_addr */
0, /* wl_efuse_start_addr_DAV */
0x600, /* bt_efuse_start_addr */
0, /* wd_checksum_en */
0, /* sw_amsdu_max_size */
NULL, /* pwr_on */
NULL, /* pwr_off */
0, /* ind_aces_cnt */
0, /* dbg_port_cnt */
0, /* core_swr_volt */
MAC_AX_SWR_NORM, /* core_swr_volt_sel */
};
static struct mac_ax_hw_info mac8852b_hw_info_cabv = {
0, /* done */
MAC_AX_CHIP_ID_8852B, /* chip_id */
0xFF, /* cv */
MAC_AX_INTF_INVALID, /* intf */
19, /* tx_ch_num */
10, /* tx_data_ch_num */
WD_BODY_LEN, /* wd_body_len */
WD_INFO_LEN, /* wd_info_len */
pwr_on_seq_8852b, /* pwr_on_seq */
pwr_off_seq_8852b, /* pwr_off_seq */
PWR_SEQ_VER_8852B, /* pwr_seq_ver */
131072, /* fifo_size */
32, /* macid_num */
5, /* port_num */
4, /* mbssid_num */
20, /* bssid_num */
1536, /* wl_efuse_size */
1216, /* wl_zone2_efuse_size */
2048, /* log_efuse_size */
1280, /* limit_efuse_size_PCIE */
1280, /* limit_efuse_size_USB */
1280, /* limit_efuse_size_SDIO */
512, /* bt_efuse_size */
1024, /* bt_log_efuse_size */
32, /*hidden_efuse_size*/
4, /* sec_ctrl_efuse_size */
192, /* sec_data_efuse_size */
NULL, /* sec_cam_table_t pointer */
NULL, /* sec_cam_table_bk pointer */
32, /* ple_rsvd_space */
24, /* payload_desc_size */
8, /* efuse_version_size */
128, /* wl_efuse_size_DAV */
96, /* wl_zone2_efuse_size_DAV */
32, /* hidden_efuse_size_DAV */
16, /* log_efuse_size_DAV */
0, /* wl_efuse_start_addr */
0, /* wl_efuse_start_addr_DAV */
0x600, /* bt_efuse_start_addr */
0, /* wd_checksum_en */
0, /* sw_amsdu_max_size */
NULL, /* pwr_on */
NULL, /* pwr_off */
0, /* ind_aces_cnt */
0, /* dbg_port_cnt */
0, /* core_swr_volt */
MAC_AX_SWR_NORM, /* core_swr_volt_sel */
};
struct mac_ax_ft_status mac_8852b_ft_status[] = {
{MAC_AX_FT_DUMP_EFUSE, MAC_AX_STATUS_IDLE, NULL, 0},
{MAC_AX_FT_MAX, MAC_AX_STATUS_ERR, NULL, 0},
};
static struct mac_ax_adapter mac_8852b_adapter = {
&mac8852b_ops, /* ops */
NULL, /* drv_adapter */
NULL, /* phl_adapter */
NULL, /* pltfm_cb */
MAC_AX_DFLT_SM, /* sm */
NULL, /* hw_info */
{0}, /* fw_info */
{0}, /* efuse_param */
{0}, /* mac_pwr_info */
mac_8852b_ft_status, /* ft_stat */
NULL, /* hfc_param */
{MAC_AX_QTA_SCC, 64, 128, 0, 0, 0, 0, 0, 0}, /* dle_info */
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, DFLT_GPIO_STATE}, /* gpio_info */
NULL, /* role table */
{NULL, NULL, NULL, 0, 0, 0, 0}, /* read_ofld_info */
{0, 0, NULL}, /* read_ofld_value */
{NULL, NULL, NULL, 0, 0, 0, 0}, /* write_ofld_info */
{NULL}, /* efuse_ofld_info */
{NULL, NULL, 0, 0, 0, 0}, /* conf_ofld_info */
{PKT_OFLD_OP_MAX, PKT_OFLD_MAX_COUNT, 0, {0}}, /* pkt_ofld_info */
{0, 0, 0, NULL}, /* pkt_ofld_pkt */
{NULL, NULL, NULL, 0, 0, 0, 0, 0}, /* cmd_ofld_info */
{{{0}, {0}, {0}, {0}}}, /* mcc_group_info */
{NULL}, /* wowlan_info */
NULL, /* p2p_info */
NULL, /* t32_togl_rpt */
NULL, /* port_info */
{0}, /* struct mac_ax_int_stats stats */
{0, 0}, /* struct mac_ax_drv_stats drv_stats */
{0}, /*h2c_agg_info*/
#if MAC_AX_SDIO_SUPPORT
{MAC_AX_SDIO_4BYTE_MODE_DISABLE, MAC_AX_SDIO_TX_MODE_AGG,
MAC_AX_SDIO_SPEC_VER_2_00, MAC_AX_SDIO_OPN_MODE_BLOCK,
512, 1, 8, 0}, /* sdio_info */
#endif
#if MAC_AX_USB_SUPPORT
{0}, /* usb_info */
#endif
{0, 0, 0, 0, 0, 0, 0, 0, 0, NULL}, /*flash_info */
{0, 0}, /* fast_ch_sw_info */
#if MAC_AX_FEATURE_HV
NULL, /*hv_ax_ops*/
HV_AX_ASIC, /* env */
#endif
#if MAC_AX_FEATURE_DBGCMD
{NULL}, /*fw_dbgcmd*/
#endif
#if MAC_AX_FEATURE_DBGDEC
NULL, /*fw_log_array*/
NULL,
0,
#endif
{0}, /*log_cfg*/
};
#ifdef CONFIG_NEW_HALMAC_INTERFACE
struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf,
u8 cv, void *phl_adapter,
void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb)
{
struct mac_ax_adapter *adapter = NULL;
struct mac_ax_mac_pwr_info *pwr_info;
adapter =
(struct mac_ax_adapter *)hal_mem_alloc(drv_adapter,
sizeof(struct mac_ax_adapter));
if (!adapter)
return NULL;
hal_mem_cpy(drv_adapter, adapter, &mac_8852b_adapter,
sizeof(struct mac_ax_adapter));
pwr_info = &adapter->mac_pwr_info;
adapter->phl_adapter = phl_adapter;
adapter->drv_adapter = drv_adapter;
adapter->pltfm_cb = pltfm_cb;
adapter->hw_info->cv = cv;
adapter->hw_info->intf = intf;
adapter->hw_info->done = 1;
switch (intf) {
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_INTF_SDIO:
adapter->ops->intf_ops = &mac8852b_sdio_ops;
pwr_info->intf_pwr_switch = sdio_pwr_switch;
break;
#endif
#if MAC_AX_USB_SUPPORT
case MAC_AX_INTF_USB:
adapter->ops->intf_ops = &mac8852b_usb_ops;
pwr_info->intf_pwr_switch = usb_pwr_switch;
break;
#endif
#if MAC_AX_PCIE_SUPPORT
case MAC_AX_INTF_PCIE:
adapter->ops->intf_ops = &mac8852b_pcie_ops;
pwr_info->intf_pwr_switch = pcie_pwr_switch;
break;
#endif
default:
return NULL;
}
return adapter;
}
#else
struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf,
u8 cv, void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb)
{
struct mac_ax_adapter *adapter = NULL;
struct mac_ax_hw_info *hw_info = NULL;
struct mac_ax_mac_pwr_info *pwr_info;
if (!pltfm_cb)
return NULL;
adapter = (struct mac_ax_adapter *)pltfm_cb->rtl_malloc(drv_adapter,
sizeof(struct mac_ax_adapter));
if (!adapter) {
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "Malloc adapter fail\n");
return NULL;
}
pltfm_cb->rtl_memcpy(drv_adapter, adapter, &mac_8852b_adapter,
sizeof(struct mac_ax_adapter));
/*Alloc HW INFO */
hw_info = (struct mac_ax_hw_info *)pltfm_cb->rtl_malloc(drv_adapter,
sizeof(struct mac_ax_hw_info));
if (!hw_info) {
pltfm_cb->msg_print(drv_adapter, _PHL_ERR_, "Malloc hw info fail\n");
return NULL;
}
if ((intf == MAC_AX_INTF_USB || intf == MAC_AX_INTF_PCIE) &&
(cv == CAV || cv == CBV))
pltfm_cb->rtl_memcpy(drv_adapter, hw_info,
&mac8852b_hw_info_cabv,
sizeof(struct mac_ax_hw_info));
else
pltfm_cb->rtl_memcpy(drv_adapter, hw_info,
&mac8852b_hw_info,
sizeof(struct mac_ax_hw_info));
pwr_info = &adapter->mac_pwr_info;
adapter->drv_adapter = drv_adapter;
adapter->pltfm_cb = pltfm_cb;
adapter->hw_info = hw_info;
adapter->hw_info->cv = cv;
adapter->hw_info->intf = intf;
adapter->hw_info->done = 1;
switch (intf) {
#if MAC_AX_SDIO_SUPPORT
case MAC_AX_INTF_SDIO:
adapter->ops->intf_ops = &mac8852b_sdio_ops;
pwr_info->intf_pwr_switch = sdio_pwr_switch;
adapter->hw_info->pwr_on = mac_pwr_on_sdio_8852b;
adapter->hw_info->pwr_off = mac_pwr_off_sdio_8852b;
break;
#endif
#if MAC_AX_USB_SUPPORT
case MAC_AX_INTF_USB:
adapter->ops->intf_ops = &mac8852b_usb_ops;
pwr_info->intf_pwr_switch = usb_pwr_switch_8852b;
adapter->hw_info->pwr_on = mac_pwr_on_usb_8852b;
adapter->hw_info->pwr_off = mac_pwr_off_usb_8852b;
break;
#endif
#if MAC_AX_PCIE_SUPPORT
case MAC_AX_INTF_PCIE:
adapter->ops->intf_ops = &mac8852b_pcie_ops;
pwr_info->intf_pwr_switch = pcie_pwr_switch;
adapter->hw_info->pwr_on = mac_pwr_on_pcie_8852b;
adapter->hw_info->pwr_off = mac_pwr_off_pcie_8852b;
break;
#endif
default:
return NULL;
}
return adapter;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.c
|
C
|
agpl-3.0
| 25,098
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_INIT_8852B_H_
#define _MAC_AX_INIT_8852B_H_
#include "../../type.h"
#ifdef CONFIG_NEW_HALMAC_INTERFACE
struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf,
u8 cv, void *phl_adapter,
void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb)
#else
struct mac_ax_adapter *get_mac_8852b_adapter(enum mac_ax_intf intf,
u8 cv, void *drv_adapter,
struct mac_ax_pltfm_cb *pltfm_cb);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/init_8852b.h
|
C
|
agpl-3.0
| 1,152
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "../pwr.h"
static struct mac_pwr_cfg mac_pwron_8852b[] = {
{0x1086,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x1086,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), BIT(1)},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), 0},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(2), 0},
{0x0006,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), BIT(1)},
{0x0006,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(0), 0},
{0x0088,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0071,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), BIT(6)},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(5), BIT(5)},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x20},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x20},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x08},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x08},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x10},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0001,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0001,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), 0},
{0x0001,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), 0},
{0xFFFF,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
static struct mac_pwr_cfg mac_pwroff_8852b[] = {
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x10},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x10},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x08},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x81},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0006,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0002,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(5), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x20},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), 0},
{0x0091,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(2), BIT(2)},
{0x0007,
PWR_CVALL_MSK,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4), 0},
{0x0007,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
{0x0005,
PWR_CVALL_MSK,
PWR_INTF_MSK_USB | PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
{0x1086,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x1086,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), 0},
{0xFFFF,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
/* Power on sequence */
struct mac_pwr_cfg *pwr_on_seq_8852b[] = {
mac_pwron_8852b,
NULL
};
/* Power off sequence */
struct mac_pwr_cfg *pwr_off_seq_8852b[] = {
mac_pwroff_8852b,
NULL
};
#if MAC_AX_FEATURE_HV
static struct mac_pwr_cfg mac_carddisable_seq_8852b[] = {
{0xFFFF,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
static struct mac_pwr_cfg mac_enterlps_seq_8852b[] = {
{0x0068,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), 0},
{0x8394,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(2), BIT(2)},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xC4},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xB4},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x41},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x42},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x43},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x7D},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x44},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x45},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x48},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(2), BIT(2)},
{0x8398,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x8399,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x839A,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x48},
{0x839B,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x8300,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x8322,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x8322,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), BIT(1)},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xA1},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x10},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x10},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x08},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x81},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(5), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x20},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0090,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xB0},
{0x0091,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xA1},
{0x0092,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0093,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0090,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xB0},
{0x0091,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xA1},
{0x0092,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x81},
{0x0093,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE | PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0090,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0090,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(0), 0},
{0xFFFF,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
static struct mac_pwr_cfg mac_leavelps_seq_8852b[] = {
{0x1083,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), BIT(7)},
{0x10C1,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), BIT(7)},
{0x1203,
PWR_CVALL_MSK,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), BIT(7)},
{0x1E5,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), BIT(7)},
{0x10,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_DELAY, PWR_DELAY_MS, PWR_DELAY_MS},
{0x8322,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x8322,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), 0},
{0x1083,
PWR_CVALL_MSK,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), 0},
{0x10C1,
PWR_CVALL_MSK,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), 0},
{0x1203,
PWR_CVALL_MSK,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), 0},
{0x8304,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), BIT(6)},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x40},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0018,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(5), BIT(5)},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x20},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x20},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x04},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x08},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x08},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x10},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x81},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0xA1},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x02},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0x0270,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x90},
{0x0271,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x00},
{0x0272,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x01},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0x80},
{0x0273,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(7), 0},
{0xFFFF,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
static struct mac_pwr_cfg mac_ips_seq_8852b[] = {
{0xFFFF,
PWR_CVALL_MSK,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
struct mac_pwr_cfg *card_disable_seq_8852b[] = {
mac_carddisable_seq_8852b,
NULL
};
struct mac_pwr_cfg *enter_lps_seq_8852b[] = {
mac_enterlps_seq_8852b,
NULL
};
struct mac_pwr_cfg *leave_lps_seq_8852b[] = {
mac_leavelps_seq_8852b,
NULL
};
struct mac_pwr_cfg *ips_seq_8852b[] = {
mac_ips_seq_8852b,
NULL
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.c
|
C
|
agpl-3.0
| 27,935
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PWR_SEQ_8852B_H_
#define _MAC_AX_PWR_SEQ_8852B_H_
//#define PWR_SEQ_VER_8852B 000
extern struct mac_pwr_cfg *pwr_on_seq_8852b[];
extern struct mac_pwr_cfg *pwr_off_seq_8852b[];
#if MAC_AX_FEATURE_HV
extern struct mac_pwr_cfg *card_disable_seq_8852b[];
extern struct mac_pwr_cfg *enter_lps_seq_8852b[];
extern struct mac_pwr_cfg *leave_lps_seq_8852b[];
extern struct mac_pwr_cfg *ips_seq_8852b[];
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_8852b.h
|
C
|
agpl-3.0
| 1,114
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "../pwr.h"
#include "../pwr_seq_func.h"
u32 mac_pwr_on_sdio_8852b(void *vadapter)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
u8 val8;
/* 0x1086[0] = 0 == 0x1084[16] = 0 */
val32 = MAC_REG_R32(R_AX_SDIO_BUS_CTRL);
MAC_REG_W32(R_AX_SDIO_BUS_CTRL, val32 & ~B_AX_HCI_SUS_REQ);
/* polling 0x1086[1] = 1 */
ret = pwr_poll_u32(adapter, R_AX_SDIO_BUS_CTRL, B_AX_HCI_RESUME_RDY,
B_AX_HCI_RESUME_RDY);
if (ret)
return ret;
/* 0x04[12:11] = 2'b00 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN |
B_AX_AFSM_PCIE_SUS_EN));
/* 0x04[18] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC);
/* 0x90[1] = 1 */
val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC);
/* 0x04[15] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APDM_HPDN);
/* 0x04[10] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APFM_SWLPS);
/* polling 0x04[17] = 1*/
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_RDY_SYSPWR,
B_AX_RDY_SYSPWR);
if (ret)
return ret;
/* 0x20[23] = 1*/
val32 = MAC_REG_R32(R_AX_AFE_LDO_CTRL);
MAC_REG_W32(R_AX_AFE_LDO_CTRL, val32 | B_AX_AON_OFF_PC_EN);
/* polling 0x20[23] = 1*/
ret = pwr_poll_u32(adapter, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN,
B_AX_AON_OFF_PC_EN);
if (ret)
return ret;
/* 0x400[1:0] = 2'b01 and 0x400[5:4] = 2'b11*/
val32 = MAC_REG_R32(R_AX_SPS_DIG_OFF_CTRL0);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1);
val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1);
MAC_REG_W32(R_AX_SPS_DIG_OFF_CTRL0, val32);
/* 0x04[16] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON);
/* 0x04[8] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFN_ONMAC);
/* polling 0x04[8] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC, 0);
if (ret)
return ret;
/* reset platform twice : 0x88[0] = 1->0->1->0 */
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN);
/* 0x88[0] = 1 */
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
/* 0x18[6] = 1 */
/* XTAL_SI 0x90[6] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 1 */
/* XTAL_SI 0x90[5] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[4] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[7] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x24[6:4] = 3'b000 */
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_2, 0, 0x70);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x26[3:0] = 4'b0000 */
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_4, 0, 0x0F);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0xCC[2] = 1 */
val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2);
MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | B_AX_SYSON_DIS_PMCR_AX_WRMSK);
/* 0x00[8] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 | B_AX_ISO_EB2CORE);
/* 0x00[15] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(15)));
PLTFM_DELAY_MS(1);
/* 0x00[14] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(14)));
/* 0xCC[2] = 0 */
val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2);
MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK);
/* 0x200[3:0]=0x9, 0x200 [25:22]=0xA */
val32 = MAC_REG_R32(R_AX_SPS_DIG_ON_CTRL0);
val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1);
val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L);
MAC_REG_W32(R_AX_SPS_DIG_ON_CTRL0, val32);
return MACSUCCESS;
}
u32 mac_pwr_on_usb_8852b(void *vadapter)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
u8 val8;
/* 0x04[12:11] = 2'b00 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN |
B_AX_AFSM_PCIE_SUS_EN));
/* 0x04[18] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC);
/* 0x90[1] = 1 */
val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC);
/* 0x04[15] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APDM_HPDN);
/* 0x04[10] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APFM_SWLPS);
/* polling 0x04[17] = 1*/
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_RDY_SYSPWR,
B_AX_RDY_SYSPWR);
if (ret)
return ret;
/* 0x20[23] = 1*/
val32 = MAC_REG_R32(R_AX_AFE_LDO_CTRL);
MAC_REG_W32(R_AX_AFE_LDO_CTRL, val32 | B_AX_AON_OFF_PC_EN);
/* polling 0x20[23] = 1*/
ret = pwr_poll_u32(adapter, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN,
B_AX_AON_OFF_PC_EN);
if (ret)
return ret;
/* 0x400[1:0] = 2'b01 and 0x400[5:4] = 2'b11*/
val32 = MAC_REG_R32(R_AX_SPS_DIG_OFF_CTRL0);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1);
val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1);
MAC_REG_W32(R_AX_SPS_DIG_OFF_CTRL0, val32);
/* 0x04[16] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON);
/* 0x04[8] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFN_ONMAC);
/* polling 0x04[8] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC, 0);
if (ret)
return ret;
/* reset platform twice : 0x88[0] = 1->0->1->0 */
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN);
/* 0x88[0] = 1 */
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
/* 0x18[6] = 1 */
/* XTAL_SI 0x90[6] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 1 */
/* XTAL_SI 0x90[5] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[4] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[7] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x24[6:4] = 3'b000 */
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_2, 0, 0x70);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x26[3:0] = 4'b0000 */
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_4, 0, 0x0F);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0xCC[2] = 1 */
val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2);
MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | B_AX_SYSON_DIS_PMCR_AX_WRMSK);
/* 0x00[8] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 | B_AX_ISO_EB2CORE);
/* 0x00[15] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(15)));
PLTFM_DELAY_MS(1);
/* 0x00[14] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(14)));
/* 0xCC[2] = 0 */
val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2);
MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK);
/* 0x200[3:0]=0x9, 0x200 [25:22]=0xA */
val32 = MAC_REG_R32(R_AX_SPS_DIG_ON_CTRL0);
val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1);
val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L);
MAC_REG_W32(R_AX_SPS_DIG_ON_CTRL0, val32);
return MACSUCCESS;
}
u32 mac_pwr_on_pcie_8852b(void *vadapter)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
u8 val8;
/* 0x04[12:11] = 2'b00 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN |
B_AX_AFSM_PCIE_SUS_EN));
/* 0x04[18] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC);
/* 0x90[1] = 1 */
val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC);
/* 0x04[15] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APDM_HPDN);
/* 0x04[10] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_APFM_SWLPS);
/* polling 0x04[17] = 1*/
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_RDY_SYSPWR,
B_AX_RDY_SYSPWR);
if (ret)
return ret;
/* 0x20[23] = 1*/
val32 = MAC_REG_R32(R_AX_AFE_LDO_CTRL);
MAC_REG_W32(R_AX_AFE_LDO_CTRL, val32 | B_AX_AON_OFF_PC_EN);
/* polling 0x20[23] = 1*/
ret = pwr_poll_u32(adapter, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN,
B_AX_AON_OFF_PC_EN);
if (ret)
return ret;
/* 0x400[1:0] = 2'b01 and 0x400[5:4] = 2'b11*/
val32 = MAC_REG_R32(R_AX_SPS_DIG_OFF_CTRL0);
val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1);
val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1);
MAC_REG_W32(R_AX_SPS_DIG_OFF_CTRL0, val32);
/* 0x04[16] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON);
/* 0x04[8] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFN_ONMAC);
/* polling 0x04[8] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC, 0);
if (ret)
return ret;
/* reset platform twice : 0x88[0] = 1->0->1->0 */
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 & ~B_AX_PLATFORM_EN);
/* 0x88[0] = 1 */
val8 = MAC_REG_R8(R_AX_PLATFORM_ENABLE);
MAC_REG_W8(R_AX_PLATFORM_ENABLE, val8 | B_AX_PLATFORM_EN);
/* 0x70[12] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_SDIO_CTRL);
MAC_REG_W32(R_AX_SYS_SDIO_CTRL, val32 & ~B_AX_PCIE_CALIB_EN_V1);
/* 0x18[6] = 1 */
/* XTAL_SI 0x90[6] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 1 */
/* XTAL_SI 0x90[5] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[4] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[7] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x24[6:4] = 3'b000 */
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_2, 0, 0x70);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x26[3:0] = 4'b0000 */
ret = mac_write_xtal_si(adapter, XTAL_SI_XTAL_XMD_4, 0, 0x0F);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0xCC[2] = 1 */
val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2);
MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 | B_AX_SYSON_DIS_PMCR_AX_WRMSK);
/* 0x00[8] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 | B_AX_ISO_EB2CORE);
/* 0x00[15] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(15)));
PLTFM_DELAY_MS(1);
/* 0x00[14] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ISO_CTRL);
MAC_REG_W32(R_AX_SYS_ISO_CTRL, val32 & ~(BIT(14)));
/* 0xCC[2] = 0 */
val32 = MAC_REG_R32(R_AX_PMC_DBG_CTRL2);
MAC_REG_W32(R_AX_PMC_DBG_CTRL2, val32 & ~B_AX_SYSON_DIS_PMCR_AX_WRMSK);
/* 0x200[3:0]=0x9, 0x200 [25:22]=0xA */
val32 = MAC_REG_R32(R_AX_SPS_DIG_ON_CTRL0);
val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1);
val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L);
MAC_REG_W32(R_AX_SPS_DIG_ON_CTRL0, val32);
return MACSUCCESS;
}
u32 mac_pwr_off_sdio_8852b(void *vadapter)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u8 val8;
u32 ret;
u8 xtal_si_val;
/* XTAL_SI 0x90[4] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x80[0] = 0 and 0x81[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[7] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* 0x04[16] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON);
/* 0x02[1:0] = 0 */
val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN);
MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & ~B_AX_FEN_BB_GLB_RSTN & ~B_AX_FEN_BBRSTB);
/* 0x18[5] = 0 */
/* XTAL_SI 0x90[5] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[6] = 0 */
/* XTAL_SI 0x90[6] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x04[9] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_OFFMAC);
/* polling 0x04[9] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC, 0);
if (ret)
return ret;
/* 0x04[28][30] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_SOP_EDSWR &
~B_AX_SOP_EASWR);
/* 0x04[12:11] = 2'b01 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, (val32 | B_AX_AFSM_WLSUS_EN) &
~B_AX_AFSM_PCIE_SUS_EN);
/* 0x1086[0] = 1 */
val32 = MAC_REG_R32(R_AX_SDIO_BUS_CTRL);
MAC_REG_W32(R_AX_SDIO_BUS_CTRL, val32 | B_AX_HCI_SUS_REQ);
#if 0
/* polling 0x1086[1] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SDIO_BUS_CTRL, B_AX_HCI_RESUME_RDY, 0);
if (ret)
return ret;
#endif
return MACSUCCESS;
}
u32 mac_pwr_off_usb_8852b(void *vadapter)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u8 val8;
u32 ret;
u8 xtal_si_val;
/* XTAL_SI 0x90[4] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x80[0] = 0 and 0x81[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[7] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* 0x04[16] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON);
/* 0x02[1:0] = 0 */
val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN);
MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & ~B_AX_FEN_BB_GLB_RSTN & ~B_AX_FEN_BBRSTB);
/* 0x18[5] = 0 */
/* XTAL_SI 0x90[5] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[6] = 0 */
/* XTAL_SI 0x90[6] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x04[9] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_OFFMAC);
/* polling 0x04[9] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC, 0);
if (ret)
return ret;
/* 0x04[28] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~B_AX_SOP_EDSWR);
/* 0x04[12:11] = 2'b01 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, (val32 | B_AX_AFSM_WLSUS_EN) &
~B_AX_AFSM_PCIE_SUS_EN);
return MACSUCCESS;
}
u32 mac_pwr_off_pcie_8852b(void *vadapter)
{
struct mac_ax_adapter *adapter = (struct mac_ax_adapter *)vadapter;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u8 val8;
u32 ret;
u8 xtal_si_val;
/* XTAL_SI 0x90[4] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x80[0] = 0 and 0x81[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[7] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* 0x04[16] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_EN_WLON);
/* 0x02[1:0] = 0 */
val8 = MAC_REG_R8(R_AX_SYS_FUNC_EN);
MAC_REG_W8(R_AX_SYS_FUNC_EN, val8 & ~B_AX_FEN_BB_GLB_RSTN & ~B_AX_FEN_BBRSTB);
/* 0x18[5] = 0 */
/* XTAL_SI 0x90[5] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[6] = 0 */
/* XTAL_SI 0x90[6] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x04[9] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_OFFMAC);
/* polling 0x04[9] = 0 */
ret = pwr_poll_u32(adapter, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC, 0);
if (ret)
return ret;
/* 0x91[0] = 0 == 0x90[8]=0 */
//val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
//MAC_REG_W32(R_AX_WLLPS_CTRL, val32 & ~B_AX_LPSOP_DSWR);
/* 0x90[31:0] = 0x00_01_A0_B0 */
MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0001A0B2);
/* 0x04[10] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL);
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_APFM_SWLPS);
return MACSUCCESS;
}
#if MAC_AX_FEATURE_HV
u32 mac_enter_lps_sdio_8852b(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
/* 0x280[6] = 1 */
val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0);
MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32 | B_AX_EN_XBUF_DRV_LPS);
/* 0x68[6] = 0 */
val32 = MAC_REG_R32(R_AX_WL_BT_PWR_CTRL);
MAC_REG_W32(R_AX_WL_BT_PWR_CTRL, val32 & ~B_AX_WLAN_32K_SEL);
/* 0x8394[2] = 1 */
val32 = MAC_REG_R32(R_AX_OSC_32K_CTRL);
MAC_REG_W32(R_AX_OSC_32K_CTRL, val32 | B_AX_CAL32K_XTAL_EN);
/* 0x8398[31:0] = 0x00_40_04_C4 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x004004C4);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x804004C4);
/* 0x8398[31:0] = 0x00_41_B4_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x0041B400);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x8041B400);
/* 0x8398[31:0] = 0x00_42_00_04 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00420004);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80420004);
/* 0x8398[31:0] = 0x00_43_00_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00430000);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80430000);
/* 0x8398[31:0] = 0x00_44_7D_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00447D00);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80447D00);
/* 0x8398[31:0] = 0x00_45_00_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00450000);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80450000);
/* 0x8398[31:0] = 0x00_48_00_01 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00480001);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80480001);
/* polling 0x8398[2] = 1 */
ret = pwr_poll_u32(adapter, R_AX_32K_CAL_REG0, BIT(2), BIT(2));
if (ret)
return ret;
/* 0x8398[1] = 1 */
val32 = MAC_REG_R32(R_AX_32K_CAL_REG0);
MAC_REG_W32(R_AX_32K_CAL_REG0, val32 | BIT(1));
/* 0x8399[7:0] = 0x00 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 1, 0x00);
/* 0x839A[7:0] = 0x48 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 2, 0x48);
/* 0x839B[7:0] = 0x80 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 3, 0x80);
/* 0x8300[0] = 1 */
val32 = MAC_REG_R32(R_AX_FWD1IMR);
MAC_REG_W32(R_AX_FWD1IMR, val32 | B_AX_FS_RPWM_INT_EN);
/* 0x8322[0] = 1 == 0x8320[16] =1 */
val32 = MAC_REG_R32(R_AX_TSF_32K_SEL);
MAC_REG_W32(R_AX_TSF_32K_SEL, val32 | B_AX_CKSL_WLTSF);
/* polling 0x8322[1] = 1 */
ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE,
B_AX_TSF_CLK_STABLE);
if (ret)
return ret;
/* DAV CAV */
/* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[7] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0xA1[1] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[4] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x80[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x81[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 0 */
/* XTAL_SI 0x90[5] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[6] = 0 */
/* XTAL_SI 0x90[6] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x90[31:0] = 0x04_80_A1_B0 */
MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0480A1B0);
/* 0x90[0] = 1 */
val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_WL_LPS_EN);
/* polling 0x90[0] = 0 */
ret = pwr_poll_u32(adapter, R_AX_WLLPS_CTRL, B_AX_WL_LPS_EN, 0);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_enter_lps_usb_8852b(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
/* 0x280[6] = 1 */
val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0);
MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32 | B_AX_EN_XBUF_DRV_LPS);
/* 0x68[6] = 0 */
val32 = MAC_REG_R32(R_AX_WL_BT_PWR_CTRL);
MAC_REG_W32(R_AX_WL_BT_PWR_CTRL, val32 & ~B_AX_WLAN_32K_SEL);
/* 0x8394[2] = 1 */
val32 = MAC_REG_R32(R_AX_OSC_32K_CTRL);
MAC_REG_W32(R_AX_OSC_32K_CTRL, val32 | B_AX_CAL32K_XTAL_EN);
/* 0x8398[31:0] = 0x00_40_04_C4 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x004004C4);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x804004C4);
/* 0x8398[31:0] = 0x00_41_B4_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x0041B400);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x8041B400);
/* 0x8398[31:0] = 0x00_42_00_04 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00420004);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80420004);
/* 0x8398[31:0] = 0x00_43_00_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00430000);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80430000);
/* 0x8398[31:0] = 0x00_44_7D_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00447D00);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80447D00);
/* 0x8398[31:0] = 0x00_45_00_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00450000);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80450000);
/* 0x8398[31:0] = 0x00_48_00_01 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00480001);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80480001);
/* polling 0x8398[2] = 1 */
ret = pwr_poll_u32(adapter, R_AX_32K_CAL_REG0, BIT(2), BIT(2));
if (ret)
return ret;
/* 0x8398[1] = 1 */
val32 = MAC_REG_R32(R_AX_32K_CAL_REG0);
MAC_REG_W32(R_AX_32K_CAL_REG0, val32 | BIT(1));
/* 0x8399[7:0] = 0x00 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 1, 0x00);
/* 0x839A[7:0] = 0x48 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 2, 0x48);
/* 0x839B[7:0] = 0x80 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 3, 0x80);
/* 0x8300[0] = 1 */
val32 = MAC_REG_R32(R_AX_FWD1IMR);
MAC_REG_W32(R_AX_FWD1IMR, val32 | B_AX_FS_RPWM_INT_EN);
/* 0x8322[0] = 1 == 0x8320[16] =1 */
val32 = MAC_REG_R32(R_AX_TSF_32K_SEL);
MAC_REG_W32(R_AX_TSF_32K_SEL, val32 | B_AX_CKSL_WLTSF);
/* polling 0x8322[1] = 1 */
ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE,
B_AX_TSF_CLK_STABLE);
if (ret)
return ret;
/* DAV CAV */
/* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[7] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0xA1[1] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[4] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x80[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x81[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 0 */
/* XTAL_SI 0x90[5] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[6] = 0 */
/* XTAL_SI 0x90[6] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x90[31:0] = 0x04_81_A1_B0 */
MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0481A1B0);
/* 0x90[0] = 1 */
val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_WL_LPS_EN);
/* polling 0x90[0] = 0 */
ret = pwr_poll_u32(adapter, R_AX_WLLPS_CTRL, B_AX_WL_LPS_EN, 0);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_enter_lps_pcie_8852b(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
/* 0x280[6] = 1 */
val32 = MAC_REG_R32(R_AX_XTAL_ON_CTRL0);
MAC_REG_W32(R_AX_XTAL_ON_CTRL0, val32 | B_AX_EN_XBUF_DRV_LPS);
/* 0x68[6] = 0 */
val32 = MAC_REG_R32(R_AX_WL_BT_PWR_CTRL);
MAC_REG_W32(R_AX_WL_BT_PWR_CTRL, val32 & ~B_AX_WLAN_32K_SEL);
/* 0x8394[2] = 1 */
val32 = MAC_REG_R32(R_AX_OSC_32K_CTRL);
MAC_REG_W32(R_AX_OSC_32K_CTRL, val32 | B_AX_CAL32K_XTAL_EN);
/* 0x8398[31:0] = 0x00_40_04_C4 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x004004C4);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x804004C4);
/* 0x8398[31:0] = 0x00_41_B4_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x0041B400);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x8041B400);
/* 0x8398[31:0] = 0x00_42_00_04 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00420004);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80420004);
/* 0x8398[31:0] = 0x00_43_00_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00430000);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80430000);
/* 0x8398[31:0] = 0x00_44_7D_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00447D00);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80447D00);
/* 0x8398[31:0] = 0x00_45_00_00 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00450000);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80450000);
/* 0x8398[31:0] = 0x00_48_00_01 then 0x8398[31] = 1 */
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x00480001);
MAC_REG_W32(R_AX_32K_CAL_REG0, 0x80480001);
/* polling 0x8398[2] = 1 */
ret = pwr_poll_u32(adapter, R_AX_32K_CAL_REG0, BIT(2), BIT(2));
if (ret)
return ret;
/* 0x8398[1] = 1 */
val32 = MAC_REG_R32(R_AX_32K_CAL_REG0);
MAC_REG_W32(R_AX_32K_CAL_REG0, val32 | BIT(1));
/* 0x8399[7:0] = 0x00 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 1, 0x00);
/* 0x839A[7:0] = 0x48 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 2, 0x48);
/* 0x839B[7:0] = 0x80 */
MAC_REG_W8(R_AX_32K_CAL_REG0 + 3, 0x80);
/* 0x8300[0] = 1 */
val32 = MAC_REG_R32(R_AX_FWD1IMR);
MAC_REG_W32(R_AX_FWD1IMR, val32 | B_AX_FS_RPWM_INT_EN);
/* 0x8322[0] = 1 == 0x8320[16] =1 */
val32 = MAC_REG_R32(R_AX_TSF_32K_SEL);
MAC_REG_W32(R_AX_TSF_32K_SEL, val32 | B_AX_CKSL_WLTSF);
/* polling 0x8322[1] = 1 */
ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE,
B_AX_TSF_CLK_STABLE);
if (ret)
return ret;
/* DAV CAV */
/* XTAL_SI 0x90[0] = 0 then 0x90[1] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[0] = 1 then 0x90[1] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[7] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0xA1[1] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[4] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[3] = 1 then 0x90[2] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[3] = 0 then 0x90[2] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x80[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x81[0] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 0 */
/* XTAL_SI 0x90[5] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[6] = 0 */
/* XTAL_SI 0x90[6] = 0 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 & ~B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x90[31:0] = 0x04_81_A1_B0 */
MAC_REG_W32(R_AX_WLLPS_CTRL, 0x0481A1B0);
/* 0x90[0] = 1 */
val32 = MAC_REG_R32(R_AX_WLLPS_CTRL);
MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_WL_LPS_EN);
/* polling 0x90[0] = 0 */
ret = pwr_poll_u32(adapter, R_AX_WLLPS_CTRL, B_AX_WL_LPS_EN, 0);
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_leave_lps_sdio_8852b(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
u32 cnt = 320;
/* 0x1083[7] = 1 == 0x1080[31] = 1 */
val32 = MAC_REG_R32(R_AX_SDIO_HRPWM1);
MAC_REG_W32(R_AX_SDIO_HRPWM1, val32 | BIT(31));
/* polling 0x1E5[7] = 1 == 0x1E4[15] = 1 */
ret = pwr_poll_u32(adapter, R_AX_RPWM,
B_AX_RPWM_TOGGLE, B_AX_RPWM_TOGGLE);
if (ret)
return ret;
/* delay 0x10 ms */
while (--cnt)
PLTFM_DELAY_US(50);
/* 0x8322[0] = 0 == 0x8320[16] = 0 */
val32 = MAC_REG_R32(R_AX_TSF_32K_SEL);
MAC_REG_W32(R_AX_TSF_32K_SEL, val32 & ~B_AX_CKSL_WLTSF);
/* polling 0x8322[1] = 0 */
ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, 0);
if (ret)
return ret;
/* 0x1083[7] = 0 == 0x1080[31] = 0 */
val32 = MAC_REG_R32(R_AX_SDIO_HRPWM1);
MAC_REG_W32(R_AX_SDIO_HRPWM1, val32 & ~(BIT(31)));
/* 0x8304[0] = 1 */
val32 = MAC_REG_R32(R_AX_FWD1ISR);
MAC_REG_W32(R_AX_FWD1ISR, val32 | B_AX_FS_RPWM_INT);
/* 0x18[6] = 1 */
/* XTAL_SI 0x90[6] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 1 */
/* XTAL_SI 0x90[5] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[4] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x80[0] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x81[0] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0xA1[1] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[7] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
return MACSUCCESS;
}
u32 mac_leave_lps_usb_8852b(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
u32 cnt = 320;
/* 0x1203[7] = 1 == 0x1200[31] = 1 */
val32 = MAC_REG_R32(R_AX_USB_D2F_F2D_INFO);
MAC_REG_W32(R_AX_USB_D2F_F2D_INFO, val32 | BIT(31));
/* polling 0x1E5[7] = 1 == 0x1E4[15] = 1 */
ret = pwr_poll_u32(adapter, R_AX_RPWM,
B_AX_RPWM_TOGGLE, B_AX_RPWM_TOGGLE);
if (ret)
return ret;
/* delay 0x10 ms */
while (--cnt)
PLTFM_DELAY_US(50);
/* 0x8322[0] = 0 == 0x8320[16] = 0 */
val32 = MAC_REG_R32(R_AX_TSF_32K_SEL);
MAC_REG_W32(R_AX_TSF_32K_SEL, val32 & ~B_AX_CKSL_WLTSF);
/* polling 0x8322[1] = 0 */
ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, 0);
if (ret)
return ret;
/* 0x1203[7] = 0 == 0x1200[31] = 0 */
val32 = MAC_REG_R32(R_AX_USB_D2F_F2D_INFO);
MAC_REG_W32(R_AX_USB_D2F_F2D_INFO, val32 & ~(BIT(31)));
/* 0x8304[0] = 1 */
val32 = MAC_REG_R32(R_AX_FWD1ISR);
MAC_REG_W32(R_AX_FWD1ISR, val32 | B_AX_FS_RPWM_INT);
/* 0x18[6] = 1 */
/* XTAL_SI 0x90[6] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 1 */
/* XTAL_SI 0x90[5] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[4] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x80[0] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x81[0] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0xA1[1] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[7] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
return MACSUCCESS;
}
u32 mac_leave_lps_pcie_8852b(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 ret;
u8 xtal_si_val;
u32 cnt = 320;
/* 0x10C1[7] = 1 == 0x10C0[15] = 1 */
val32 = MAC_REG_R32(R_AX_PCIE_HRPWM);
MAC_REG_W32(R_AX_PCIE_HRPWM, val32 | BIT(15));
/* polling 0x1E5[7] = 1 == 0x1E4[15] = 1 */
ret = pwr_poll_u32(adapter, R_AX_RPWM,
B_AX_RPWM_TOGGLE, B_AX_RPWM_TOGGLE);
if (ret)
return ret;
/* delay 0x10 ms */
while (--cnt)
PLTFM_DELAY_US(50);
/* 0x8322[0] = 0 == 0x8320[16] = 0 */
val32 = MAC_REG_R32(R_AX_TSF_32K_SEL);
MAC_REG_W32(R_AX_TSF_32K_SEL, val32 & ~B_AX_CKSL_WLTSF);
/* polling 0x8322[1] = 0 */
ret = pwr_poll_u32(adapter, R_AX_TSF_32K_SEL, B_AX_TSF_CLK_STABLE, 0);
if (ret)
return ret;
/* 0x10C1[7] = 0 */
val32 = MAC_REG_R32(R_AX_PCIE_HRPWM);
MAC_REG_W32(R_AX_PCIE_HRPWM, val32 & ~(BIT(15)));
/* 0x8304[0] = 1 */
val32 = MAC_REG_R32(R_AX_FWD1ISR);
MAC_REG_W32(R_AX_FWD1ISR, val32 | B_AX_FS_RPWM_INT);
/* 0x18[6] = 1 */
/* XTAL_SI 0x90[6] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_PTA_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* 0x18[5] = 1 */
/* XTAL_SI 0x90[5] = 1 */
val32 = MAC_REG_R32(R_AX_SYS_ADIE_PAD_PWR_CTRL);
MAC_REG_W32(R_AX_SYS_ADIE_PAD_PWR_CTRL, val32 | B_AX_SYM_PADPDN_WL_RFC_1P3);
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[2] = 0 then 0x90[3] = 0 */
/* DAV after CBV */
/* XTAL_SI 0x90[2] = 1 then 0x90[3] = 1 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
/* XTAL_SI 0x90[4] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x10);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x80[0] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S0, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x81[0] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_WL_RFC_S1, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0xA1[1] = 0 */
ret = mac_write_xtal_si(adapter, XTAL_SI_SRAM_CTRL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* XTAL_SI 0x90[7] = 1 */
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
/* DAV CAV */
/* XTAL_SI 0x90[1] = 1 then 0x90[0] = 1 */
/* DAV after CBV */
/* XTAL_SI 0x90[1] = 0 then 0x90[0] = 0 */
ret = mac_read_xtal_si(adapter, XTAL_SI_CV, &xtal_si_val);
if (ret) {
PLTFM_MSG_ERR("Read XTAL_SI fail!\n");
return ret;
}
xtal_si_val = (xtal_si_val & 0x0F);
if (xtal_si_val == CAV) {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
} else {
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x02);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
ret = mac_write_xtal_si(adapter, XTAL_SI_ANAPAR_WL, 0, 0x01);
if (ret) {
PLTFM_MSG_ERR("Write XTAL_SI fail!\n");
return ret;
}
}
return MACSUCCESS;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.c
|
C
|
agpl-3.0
| 63,820
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PWR_SEQ_FUNC_8852B_H_
#define _MAC_AX_PWR_SEQ_FUNC_8852B_H_
#define PWR_SEQ_VER_8852B 9
u32 mac_pwr_on_sdio_8852b(void *vadapter);
u32 mac_pwr_on_usb_8852b(void *vadapter);
u32 mac_pwr_on_pcie_8852b(void *vadapter);
u32 mac_pwr_off_sdio_8852b(void *vadapter);
u32 mac_pwr_off_usb_8852b(void *vadapter);
u32 mac_pwr_off_pcie_8852b(void *vadapter);
#if MAC_AX_FEATURE_HV
u32 mac_enter_lps_sdio_8852b(struct mac_ax_adapter *adapter);
u32 mac_enter_lps_usb_8852b(struct mac_ax_adapter *adapter);
u32 mac_enter_lps_pcie_8852b(struct mac_ax_adapter *adapter);
u32 mac_leave_lps_sdio_8852b(struct mac_ax_adapter *adapter);
u32 mac_leave_lps_usb_8852b(struct mac_ax_adapter *adapter);
u32 mac_leave_lps_pcie_8852b(struct mac_ax_adapter *adapter);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_8852b/pwr_seq_func_8852b.h
|
C
|
agpl-3.0
| 1,460
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_DFS_H_
#define _MAC_AX_DFS_H_
/* dword0 */
#define AX_DFS_DROP_NUM_SH 0
#define AX_DFS_DROP_NUM_MSK 0xffff
#define AX_DFS_MAX_CONT_DROP_SH 16
#define AX_DFS_MAX_CONT_DROP_MSK 0xff
#define AX_DFS_TOTAL_DROP_SH 24
#define AX_DFS_TOTAL_DROP_MSK 0xff
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_ax_dfs.h
|
C
|
agpl-3.0
| 963
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_MAC_INFO_H_
#define _MAC_AX_MAC_INFO_H_
/* dword0 */
#define AX_MAC_INFO_USR_NUM_SH 0
#define AX_MAC_INFO_USR_NUM_MSK 0xf
#define AX_MAC_INFO_FW_DEFINE_SH 8
#define AX_MAC_INFO_FW_DEFINE_MSK 0xff
#define AX_MAC_INFO_LSIG_LEN_SH 16
#define AX_MAC_INFO_LSIG_LEN_MSK 0xfff
#define AX_MAC_INFO_IS_TO_SELF BIT(28)
#define AX_MAC_INFO_RX_CNT_VLD BIT(29)
#define AX_MAC_INFO_LONG_RXD_SH 30
#define AX_MAC_INFO_LONG_RXD_MSK 0x3
/* dword1 */
#define AX_MAC_INFO_SERVICE_SH 0
#define AX_MAC_INFO_SERVICE_MSK 0xffff
#define AX_MAC_INFO_PLCP_LEN_SH 16
#define AX_MAC_INFO_PLCP_LEN_MSK 0xff
/* dword2 */
#define AX_MAC_INFO_MAC_ID_VALID BIT(0)
#define AX_MAC_INFO_HAS_DATA BIT(1)
#define AX_MAC_INFO_HAS_CTRL BIT(2)
#define AX_MAC_INFO_HAS_MGNT BIT(3)
#define AX_MAC_INFO_HAS_BCN BIT(4)
#define AX_MAC_INFO_MACID_SH 8
#define AX_MAC_INFO_MACID_MSK 0xff
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_ax_mac_info.h
|
C
|
agpl-3.0
| 1,573
|
#ifndef _MAC_TXCCXRPT_H_
#define _MAC_TXCCXRPT_H_
/* dword0 */
#define TXCCXRPT_RPT_SEL_SH 0
#define TXCCXRPT_RPT_SEL_MSK 0x1f
#define TXCCXRPT_POLLUTED BIT(5)
#define TXCCXRPT_TX_STATE_SH 6
#define TXCCXRPT_TX_STATE_MSK 0x3
#define TXCCXRPT_SW_DEFINE_SH 8
#define TXCCXRPT_SW_DEFINE_MSK 0xf
#define TXCCXRPT_TRY_RATE BIT(14)
#define TXCCXRPT_FIXRATE BIT(15)
#define TXCCXRPT_MACID_SH 16
#define TXCCXRPT_MACID_MSK 0x7f
#define TXCCXRPT_QSEL_SH 24
#define TXCCXRPT_QSEL_MSK 0x3f
#define TXCCXRPT_TXOP_START BIT(31)
/* dword1 */
#define TXCCXRPT_QUEUE_TIME_SH 0
#define TXCCXRPT_QUEUE_TIME_MSK 0xffff
#define TXCCXRPT_ACCTXTIME_SH 16
#define TXCCXRPT_ACCTXTIME_MSK 0xff
#define TXCCXRPT_BMC BIT(29)
#define TXCCXRPT_BITMAP_SHORT_SH 30
#define TXCCXRPT_BITMAP_SHORT_MSK 0x3
/* dword2 */
#define TXCCXRPT_FINAL_RATE_SH 0
#define TXCCXRPT_FINAL_RATE_MSK 0x1ff
#define TXCCXRPT_FINAL_GI_LTF_SH 9
#define TXCCXRPT_FINAL_GI_LTF_MSK 0x7
#define TXCCXRPT_DATA_BW_SH 12
#define TXCCXRPT_DATA_BW_MSK 0x3
#define TXCCXRPT_MU2SU BIT(14)
#define TXCCXRPT_MU_LMT BIT(15)
#define TXCCXRPT_FINAL_RTS_RATE_SH 16
#define TXCCXRPT_FINAL_RTS_RATE_MSK 0x1ff
#define TXCCXRPT_FINAL_RTS_GI_LTF_SH 25
#define TXCCXRPT_FINAL_RTS_GI_LTF_MSK 0x7
#define TXCCXRPT_RTS_TX_STATE_SH 28
#define TXCCXRPT_RTS_TX_STATE_MSK 0x3
#define TXCCXRPT_COLLISION_HEAD BIT(30)
#define TXCCXRPT_COLLISION_TAIL BIT(31)
/* dword3 */
#define TXCCXRPT_TOTAL_PKT_NUM_SH 0
#define TXCCXRPT_TOTAL_PKT_NUM_MSK 0xff
#define TXCCXRPT_DATA_TX_CNT_SH 8
#define TXCCXRPT_DATA_TX_CNT_MSK 0x3f
#define TXCCXRPT_BPRI BIT(14)
#define TXCCXRPT_BBAR BIT(15)
#define TXCCXRPT_PKT_OK_NUM_SH 16
#define TXCCXRPT_PKT_OK_NUM_MSK 0xff
#define TXCCXRPT_RTS_TX_COUNT_SH 24
#define TXCCXRPT_RTS_TX_COUNT_MSK 0x3f
/* dword4 */
#define TXCCXRPT_INIT_RATE_SH 0
#define TXCCXRPT_INIT_RATE_MSK 0x1ff
#define TXCCXRPT_INIT_GI_LTF_SH 9
#define TXCCXRPT_INIT_GI_LTF_MSK 0x7
#define TXCCXRPT_PPDU_TYPE_SH 12
#define TXCCXRPT_PPDU_TYPE_MSK 0x3
#define TXCCXRPT_HE_TB_PPDU_FLAG BIT(14)
#define TXCCXRPT_PPDU_FST_RPT BIT(15)
#define TXCCXRPT_SU_TXPWR_SH 16
#define TXCCXRPT_SU_TXPWR_MSK 0x3f
#define TXCCXRPT_DIFF_PKT_NUM_SH 24
#define TXCCXRPT_DIFF_PKT_NUM_MSK 0xf
#define TXCCXRPT_USER_DEFINE_EXT_L_SH 28
#define TXCCXRPT_USER_DEFINE_EXT_L_MSK 0xf
/* dword5 */
#define TXCCXRPT_USER_DEFINE_SH 0
#define TXCCXRPT_USER_DEFINE_MSK 0xff
#define TXCCXRPT_FW_DEFINE_SH 8
#define TXCCXRPT_FW_DEFINE_MSK 0xff
#define TXCCXRPT_TXPWR_PD_SH 16
#define TXCCXRPT_TXPWR_PD_MSK 0x1f
#define TXCCXRPT_BSR BIT(21)
#define TXCCXRPT_SR_RX_COUNT_SH 24
#define TXCCXRPT_SR_RX_COUNT_MSK 0xf
#define TXCCXRPT_USER_DEFINE_EXT_H_SH 28
#define TXCCXRPT_USER_DEFINE_EXT_H_MSK 0xf
struct mac_ccxrpt {
/* dword 0 */
u32 rpt_sel:5;
u32 polluted:1;
u32 tx_state:2;
u32 sw_define:4;
u32 rsvd0:2;
u32 try_rate:1;
u32 fixrate:1;
u32 macid:7;
u32 rsvd1:1;
u32 qsel:6;
u32 rsvd2:1;
u32 txop_start:1;
/* dword 1 */
u32 queue_time:16;
u32 acctxtime:8;
u32 rsvd3:5;
u32 bmc:1;
u32 bitmap_short:2;
/* dword 2 */
u32 final_rate:9;
u32 final_gi_ltf:3;
u32 data_bw:2;
u32 mu2su:1;
u32 mu_lmt:1;
u32 final_rts_rate:9;
u32 final_rts_gi_ltf:3;
u32 rts_tx_state:2;
u32 collision_head:1;
u32 collision_tail:1;
/* dword 3 */
u32 total_pkt_num:8;
u32 data_tx_cnt:6;
u32 bpri:1;
u32 bbar:1;
u32 pkt_ok_num:8;
u32 rts_tx_count:6;
u32 rsvd4:2;
/* dword 4 */
u32 init_rate:9;
u32 init_gi_ltf:3;
u32 ppdu_type:2;
u32 he_tb_ppdu_flag:1;
u32 ppdu_fst_rpt:1;
u32 su_txpwr:6;
u32 rsvd5:2;
u32 diff_pkt_num:4;
u32 user_define_ext_l:4;
/* dword 5 */
u32 user_define:8;
u32 fw_define:8;
u32 txpwr_pd:5;
u32 bsr:1;
u32 rsvd6:2;
u32 sr_rx_count:4;
u32 user_define_ext_h:4;
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mac_txccxrpt.h
|
C
|
agpl-3.0
| 3,770
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "mcc.h"
u32 mac_reset_mcc_group(struct mac_ax_adapter *adapter, u8 group)
{
struct fwcmd_reset_mcc_group *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (adapter->sm.mcc_group[group] != MAC_AX_MCC_STATE_ERROR) {
PLTFM_MSG_ERR("[ERR]%s: state != error\n", __func__);
return MACPROCERR;
}
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
adapter->sm.mcc_group[group] = MAC_AX_MCC_STATE_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_reset_mcc_group));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_reset_mcc_group *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(group, FWCMD_H2C_RESET_MCC_GROUP_GROUP));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_RESET_MCC_GROUP, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_reset_mcc_request(struct mac_ax_adapter *adapter, u8 group)
{
if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_FAIL) {
PLTFM_MSG_ERR("[ERR]%s: state != req fail\n", __func__);
return MACPROCERR;
}
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_IDLE;
return MACSUCCESS;
}
u32 mac_add_mcc(struct mac_ax_adapter *adapter, struct mac_ax_mcc_role *info)
{
struct fwcmd_add_mcc *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (!(adapter->sm.mcc_group[info->group] == MAC_AX_MCC_EMPTY ||
adapter->sm.mcc_group[info->group] == MAC_AX_MCC_ADD_DONE)) {
PLTFM_MSG_ERR("[ERR]%s: state != empty or add done\n",
__func__);
return MACPROCERR;
}
adapter->sm.mcc_group[info->group] = MAC_AX_MCC_STATE_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_add_mcc));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_add_mcc *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_ADD_MCC_MACID) |
SET_WORD(info->central_ch_seg0,
FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG0) |
SET_WORD(info->central_ch_seg1,
FWCMD_H2C_ADD_MCC_CENTRAL_CH_SEG1) |
SET_WORD(info->primary_ch, FWCMD_H2C_ADD_MCC_PRIMARY_CH));
ptr->dword1 =
cpu_to_le32((info->dis_tx_null ? FWCMD_H2C_ADD_MCC_DIS_TX_NULL : 0) |
(info->dis_sw_retry ? FWCMD_H2C_ADD_MCC_DIS_SW_RETRY : 0) |
(info->in_curr_ch ? FWCMD_H2C_ADD_MCC_IN_CURR_CH : 0) |
SET_WORD(info->bandwidth, FWCMD_H2C_ADD_MCC_BANDWIDTH) |
SET_WORD(info->group, FWCMD_H2C_ADD_MCC_GROUP) |
SET_WORD(info->c2h_rpt, FWCMD_H2C_ADD_MCC_C2H_RPT) |
SET_WORD(info->sw_retry_count,
FWCMD_H2C_ADD_MCC_SW_RETRY_COUNT) |
SET_WORD(info->tx_null_early,
FWCMD_H2C_ADD_MCC_TX_NULL_EARLY) |
(info->btc_in_2g ? FWCMD_H2C_ADD_MCC_BTC_IN_2G : 0) |
(info->pta_en ? FWCMD_H2C_ADD_MCC_PTA_EN : 0) |
(info->rfk_by_pass ? FWCMD_H2C_ADD_MCC_RFK_BY_PASS : 0));
ptr->dword2 =
cpu_to_le32(SET_WORD(info->duration, FWCMD_H2C_ADD_MCC_DURATION));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_ADD_MCC, 0, 0);
ptr->dword3 =
cpu_to_le32((info->courtesy_en ? FWCMD_H2C_ADD_MCC_COURTESY_EN : 0) |
SET_WORD(info->courtesy_num,
FWCMD_H2C_ADD_MCC_COURTESY_NUM) |
SET_WORD(info->courtesy_target,
FWCMD_H2C_ADD_MCC_COURTESY_TARGET));
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_start_mcc(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_start *info)
{
struct fwcmd_start_mcc *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
u32 group = info->group;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, info->group);
return MACNOITEM;
}
if (adapter->sm.mcc_group[info->group] != MAC_AX_MCC_ADD_DONE) {
PLTFM_MSG_ERR("[ERR]%s: state != add done\n", __func__);
return MACPROCERR;
}
adapter->sm.mcc_group[info->group] = MAC_AX_MCC_STATE_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_start_mcc));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_start_mcc *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(info->group, FWCMD_H2C_START_MCC_GROUP) |
(info->btc_in_group ? FWCMD_H2C_START_MCC_BTC_IN_GROUP : 0) |
SET_WORD(info->old_group_action,
FWCMD_H2C_START_MCC_OLD_GROUP_ACTION) |
SET_WORD(info->old_group, FWCMD_H2C_START_MCC_OLD_GROUP) |
SET_WORD(info->macid, FWCMD_H2C_START_MCC_MACID));
ptr->dword1 =
cpu_to_le32(SET_WORD(info->tsf_low, FWCMD_H2C_START_MCC_TSF_LOW));
ptr->dword2 =
cpu_to_le32(SET_WORD(info->tsf_high, FWCMD_H2C_START_MCC_TSF_HIGH));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_START_MCC, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_stop_mcc(struct mac_ax_adapter *adapter, u8 group, u8 macid,
u8 prev_groups)
{
struct fwcmd_stop_mcc *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
if (adapter->sm.mcc_group[group] != MAC_AX_MCC_START_DONE) {
PLTFM_MSG_ERR("[ERR]%s: state != start done\n", __func__);
return MACPROCERR;
}
adapter->sm.mcc_group[group] = MAC_AX_MCC_STATE_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_stop_mcc));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_stop_mcc *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(group, FWCMD_H2C_STOP_MCC_GROUP) |
SET_WORD(macid, FWCMD_H2C_STOP_MCC_MACID) |
(prev_groups ? FWCMD_H2C_STOP_MCC_PREV_GROUPS : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_STOP_MCC, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_del_mcc_group(struct mac_ax_adapter *adapter, u8 group,
u8 prev_groups)
{
struct fwcmd_del_mcc_group *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
if (!(adapter->sm.mcc_group[group] == MAC_AX_MCC_ADD_DONE ||
adapter->sm.mcc_group[group] == MAC_AX_MCC_STOP_DONE)) {
PLTFM_MSG_ERR("[ERR]%s: state != add or stop done\n",
__func__);
return MACPROCERR;
}
adapter->sm.mcc_group[group] = MAC_AX_MCC_STATE_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_del_mcc_group));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_del_mcc_group *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(group, FWCMD_H2C_DEL_MCC_GROUP_GROUP) |
(prev_groups ? FWCMD_H2C_DEL_MCC_GROUP_PREV_GROUPS : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_DEL_MCC_GROUP, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_mcc_request_tsf(struct mac_ax_adapter *adapter, u8 group,
u8 macid_x, u8 macid_y)
{
struct fwcmd_mcc_req_tsf *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_IDLE) {
PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__);
return MACPROCERR;
}
adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_mcc_req_tsf));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_mcc_req_tsf *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(group, FWCMD_H2C_MCC_REQ_TSF_GROUP) |
SET_WORD(macid_x, FWCMD_H2C_MCC_REQ_TSF_MACID_X) |
SET_WORD(macid_y, FWCMD_H2C_MCC_REQ_TSF_MACID_Y));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_MCC_REQ_TSF, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err: %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_mcc_macid_bitmap(struct mac_ax_adapter *adapter, u8 group,
u8 macid, u8 *bitmap, u8 len)
{
struct fwcmd_mcc_macid_bitmap *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_IDLE) {
PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__);
return MACPROCERR;
}
adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, len + 4);
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_mcc_macid_bitmap *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(group, FWCMD_H2C_MCC_MACID_BITMAP_GROUP) |
SET_WORD(macid, FWCMD_H2C_MCC_MACID_BITMAP_MACID) |
SET_WORD(len, FWCMD_H2C_MCC_MACID_BITMAP_BITMAP_LENGTH));
PLTFM_MEMCPY((u8 *)ptr + sizeof(u32), bitmap, len);
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_MCC_MACID_BITMAP, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx error %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_mcc_sync_enable(struct mac_ax_adapter *adapter, u8 group,
u8 source, u8 target, u8 offset)
{
struct fwcmd_mcc_sync *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
if (adapter->sm.mcc_request[group] != MAC_AX_MCC_REQ_IDLE) {
PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__);
return MACPROCERR;
}
adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_mcc_sync));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_mcc_sync *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(group, FWCMD_H2C_MCC_SYNC_GROUP) |
SET_WORD(source, FWCMD_H2C_MCC_SYNC_MACID_SOURCE) |
SET_WORD(target, FWCMD_H2C_MCC_SYNC_MACID_TARGET) |
SET_WORD(offset, FWCMD_H2C_MCC_SYNC_SYNC_OFFSET));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_MCC_SYNC, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx error %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_mcc_set_duration(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_duration_info *info)
{
struct fwcmd_mcc_set_duration *ptr;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
u8 *buf;
u32 ret = 0;
if (adapter->sm.mcc_request[info->group] != MAC_AX_MCC_REQ_IDLE) {
PLTFM_MSG_ERR("[ERR]%s: state != req idle\n", __func__);
return MACPROCERR;
}
adapter->sm.mcc_request[info->group] = MAC_AX_MCC_REQ_H2C_SENT;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cb) {
PLTFM_MSG_ERR("[ERR]%s: H2C alloc fail\n", __func__);
return MACNPTR;
}
buf = h2cb_put(h2cb, sizeof(struct fwcmd_mcc_set_duration));
if (!buf) {
PLTFM_MSG_ERR("[ERR]%s: H2C put fail\n", __func__);
ret = MACNOBUF;
goto fail;
}
ptr = (struct fwcmd_mcc_set_duration *)buf;
ptr->dword0 =
cpu_to_le32(SET_WORD(info->group, FWCMD_H2C_MCC_SET_DURATION_GROUP) |
(info->btc_in_group ?
FWCMD_H2C_MCC_SET_DURATION_BTC_IN_GROUP : 0) |
SET_WORD(info->start_macid,
FWCMD_H2C_MCC_SET_DURATION_START_MACID) |
SET_WORD(info->macid_x,
FWCMD_H2C_MCC_SET_DURATION_MACID_X) |
SET_WORD(info->macid_y,
FWCMD_H2C_MCC_SET_DURATION_MACID_Y));
ptr->dword1 =
cpu_to_le32(SET_WORD(info->start_tsf_low,
FWCMD_H2C_MCC_SET_DURATION_START_TSF_LOW));
ptr->dword2 =
cpu_to_le32(SET_WORD(info->start_tsf_high,
FWCMD_H2C_MCC_SET_DURATION_START_TSF_HIGH));
ptr->dword3 =
cpu_to_le32(SET_WORD(info->duration_x,
FWCMD_H2C_MCC_SET_DURATION_DURATION_X));
ptr->dword4 =
cpu_to_le32(SET_WORD(info->duration_y,
FWCMD_H2C_MCC_SET_DURATION_DURATION_Y));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MCC,
FWCMD_H2C_FUNC_MCC_SET_DURATION, 0, 0);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Set H2C HDR fail\n", __func__);
goto fail;
}
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: Build H2C TXD fail\n", __func__);
goto fail;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret) {
PLTFM_MSG_ERR("[ERR]%s: platform tx err %d\n", __func__, ret);
goto fail;
}
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_get_mcc_status_rpt(struct mac_ax_adapter *adapter,
u8 group, u8 *status, u32 *tsf_high, u32 *tsf_low)
{
struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info;
if (adapter->sm.mcc_group[group] == MAC_AX_MCC_EMPTY) {
PLTFM_MSG_ERR("[ERR]%s: state = empty\n", __func__);
return MACPROCERR;
}
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
*status = mcc_info->groups[group].rpt_status;
PLTFM_MSG_TRACE("[TRACE]%s: mcc status: %d\n", __func__, *status);
*tsf_high = mcc_info->groups[group].rpt_tsf_high;
*tsf_low = mcc_info->groups[group].rpt_tsf_low;
PLTFM_MSG_TRACE("[TRACE]%s: report tsf_high: 0x%x\n",
__func__, *tsf_high);
PLTFM_MSG_TRACE("[TRACE]%s: report tsf_low: 0x%x\n",
__func__, *tsf_low);
return MACSUCCESS;
}
u32 mac_get_mcc_tsf_rpt(struct mac_ax_adapter *adapter, u8 group,
u32 *tsf_x_high, u32 *tsf_x_low,
u32 *tsf_y_high, u32 *tsf_y_low)
{
struct mac_ax_mcc_group_info *mcc_info = &adapter->mcc_group_info;
if (group > MCC_GROUP_ID_MAX) {
PLTFM_MSG_ERR("[ERR]%s: invalid group: %d\n", __func__, group);
return MACNOITEM;
}
*tsf_x_high = mcc_info->groups[group].tsf_x_high;
*tsf_x_low = mcc_info->groups[group].tsf_x_low;
PLTFM_MSG_TRACE("[TRACE]%s: tsf_x_high: 0x%x\n", __func__, *tsf_x_high);
PLTFM_MSG_TRACE("[TRACE]%s: tsf_x_low: 0x%x\n", __func__, *tsf_x_low);
*tsf_y_high = mcc_info->groups[group].tsf_y_high;
*tsf_y_low += mcc_info->groups[group].tsf_y_low;
PLTFM_MSG_TRACE("[TRACE]%s: tsf_y_high: 0x%x\n", __func__, *tsf_y_high);
PLTFM_MSG_TRACE("[TRACE]%s: tsf_y_low: 0x%x\n", __func__, *tsf_y_low);
adapter->sm.mcc_request[group] = MAC_AX_MCC_REQ_IDLE;
return MACSUCCESS;
}
u32 mac_get_mcc_group(struct mac_ax_adapter *adapter, u8 *pget_group)
{
struct mac_ax_state_mach *sm = &adapter->sm;
u8 group_idx;
for (group_idx = 0; group_idx <= MCC_GROUP_ID_MAX; group_idx++) {
if (sm->mcc_group[group_idx] == MAC_AX_MCC_EMPTY) {
*pget_group = group_idx;
PLTFM_MSG_TRACE("[TRACE]%s: get mcc empty group %u\n",
__func__, *pget_group);
return MACSUCCESS;
}
}
return MACMCCGPFL;
}
u32 mac_check_add_mcc_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_group[group] == MAC_AX_MCC_ADD_DONE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_start_mcc_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_group[group] == MAC_AX_MCC_START_DONE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_stop_mcc_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_group[group] == MAC_AX_MCC_STOP_DONE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_del_mcc_group_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_group[group] == MAC_AX_MCC_EMPTY)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_mcc_request_tsf_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_DONE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_mcc_macid_bitmap_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_IDLE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_mcc_sync_enable_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_IDLE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
u32 mac_check_mcc_set_duration_done(struct mac_ax_adapter *adapter, u8 group)
{
PLTFM_MSG_TRACE("[TRACE]%s: group %d curr state: %d\n", __func__,
group, adapter->sm.mcc_group[group]);
if (adapter->sm.mcc_request[group] == MAC_AX_MCC_REQ_IDLE)
return MACSUCCESS;
else
return MACPROCBUSY;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mcc.c
|
C
|
agpl-3.0
| 23,505
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_MCC_H_
#define _MAC_AX_MCC_H_
#include "../type.h"
#include "fwcmd.h"
#define MCC_GROUP_ID_MAX 3
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_reset_mcc_group
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_reset_mcc_group(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_reset_mcc_request
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_reset_mcc_request(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_add_mcc
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_add_mcc(struct mac_ax_adapter *adapter, struct mac_ax_mcc_role *info);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_start_mcc
*
* @param *adapter
* @param group
* @param macid
* @param tsf_high
* @param tsf_low
* @return Please Place Description here.
* @retval u32
*/
u32 mac_start_mcc(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_start *info);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_stop_mcc
*
* @param *adapter
* @param group
* @param macid
* @return Please Place Description here.
* @retval u32
*/
u32 mac_stop_mcc(struct mac_ax_adapter *adapter, u8 group, u8 macid,
u8 prev_groups);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_del_mcc_group
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_del_mcc_group(struct mac_ax_adapter *adapter, u8 group,
u8 prev_groups);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_mcc_request_tsf
*
* @param *adapter
* @param group
* @param macid_x
* @param macid_y
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mcc_request_tsf(struct mac_ax_adapter *adapter, u8 group,
u8 macid_x, u8 macid_y);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_mcc_macid_bitmap
*
* @param *adapter
* @param group
* @param macid
* @param *bitmap
* @param len
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mcc_macid_bitmap(struct mac_ax_adapter *adapter, u8 group,
u8 macid, u8 *bitmap, u8 len);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_mcc_sync_enable
*
* @param *adapter
* @param group
* @param source
* @param target
* @param offset
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mcc_sync_enable(struct mac_ax_adapter *adapter, u8 group,
u8 source, u8 target, u8 offset);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_mcc_set_duration
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_mcc_set_duration(struct mac_ax_adapter *adapter,
struct mac_ax_mcc_duration_info *info);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_get_mcc_status_rpt
*
* @param *adapter
* @param group
* @param *status
* @param *tsf_high
* @param *tsf_low
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_mcc_status_rpt(struct mac_ax_adapter *adapter,
u8 group, u8 *status, u32 *tsf_high, u32 *tsf_low);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_get_mcc_tsf_rpt
*
* @param *adapter
* @param group
* @param *tsf_x_high
* @param *tsf_x_low
* @param *tsf_y_high
* @param *tsf_y_low
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_mcc_tsf_rpt(struct mac_ax_adapter *adapter, u8 group,
u32 *tsf_x_high, u32 *tsf_x_low,
u32 *tsf_y_high, u32 *tsf_y_low);
/**
* @}
*/
u32 mac_get_mcc_group(struct mac_ax_adapter *adapter, u8 *pget_group);
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_add_mcc_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_add_mcc_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_start_mcc_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_start_mcc_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_stop_mcc_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_stop_mcc_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_del_mcc_group_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_del_mcc_group_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_mcc_request_tsf_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_mcc_request_tsf_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_mcc_macid_bitmap_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_mcc_macid_bitmap_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_mcc_sync_enable_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_mcc_sync_enable_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
/**
* @addtogroup MCC
* @{
*/
/**
* @brief mac_check_mcc_set_duration_done
*
* @param *adapter
* @param group
* @return Please Place Description here.
* @retval u32
*/
u32 mac_check_mcc_set_duration_done(struct mac_ax_adapter *adapter, u8 group);
/**
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mcc.h
|
C
|
agpl-3.0
| 6,653
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "mport.h"
#include "../mac_ax.h"
#define MAX_TSF_SOURCE_PORT 7
#define MAX_TSF_TARGET_PORT 4
#define MAX_TSF_SYNC_OFFSET 0x3FFFF
static u32 cfg_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_PORT_CFG_P0, R_AX_PORT_CFG_P1, R_AX_PORT_CFG_P2,
R_AX_PORT_CFG_P3, R_AX_PORT_CFG_P4},
{R_AX_PORT_CFG_P0_C1, R_AX_PORT_CFG_P1_C1, R_AX_PORT_CFG_P2_C1,
R_AX_PORT_CFG_P3_C1, R_AX_PORT_CFG_P4_C1}
};
static u32 phb_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_TBTT_PROHIB_P0, R_AX_TBTT_PROHIB_P1, R_AX_TBTT_PROHIB_P1,
R_AX_TBTT_PROHIB_P1, R_AX_TBTT_PROHIB_P1},
{R_AX_TBTT_PROHIB_P0_C1, R_AX_TBTT_PROHIB_P1_C1, R_AX_TBTT_PROHIB_P1_C1,
R_AX_TBTT_PROHIB_P1_C1, R_AX_TBTT_PROHIB_P1_C1}
};
static u32 ctnarea_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_BCN_AREA_P0, R_AX_BCN_AREA_P1, R_AX_BCN_AREA_P1,
R_AX_BCN_AREA_P1, R_AX_BCN_AREA_P1},
{R_AX_BCN_AREA_P0_C1, R_AX_BCN_AREA_P1_C1, R_AX_BCN_AREA_P1_C1,
R_AX_BCN_AREA_P1_C1, R_AX_BCN_AREA_P1_C1}
};
static u32 mskarea_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_BCN_AREA_P0, R_AX_BCN_AREA_P1, R_AX_BCN_AREA_P2,
R_AX_BCN_AREA_P3, R_AX_BCN_AREA_P4},
{R_AX_BCN_AREA_P0_C1, R_AX_BCN_AREA_P1_C1, R_AX_BCN_AREA_P2_C1,
R_AX_BCN_AREA_P3_C1, R_AX_BCN_AREA_P4_C1}
};
static u32 tbttagg_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_TBTT_AGG_P0, R_AX_TBTT_AGG_P1, R_AX_TBTT_AGG_P2,
R_AX_TBTT_AGG_P3, R_AX_TBTT_AGG_P4},
{R_AX_TBTT_AGG_P0_C1, R_AX_TBTT_AGG_P1_C1, R_AX_TBTT_AGG_P2_C1,
R_AX_TBTT_AGG_P3_C1, R_AX_TBTT_AGG_P4_C1}
};
static u32 tbttery_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_TBTTERLYINT_CFG_P0, R_AX_TBTTERLYINT_CFG_P1,
R_AX_TBTTERLYINT_CFG_P2, R_AX_TBTTERLYINT_CFG_P3,
R_AX_TBTTERLYINT_CFG_P4},
{R_AX_TBTTERLYINT_CFG_P0_C1, R_AX_TBTTERLYINT_CFG_P1_C1,
R_AX_TBTTERLYINT_CFG_P2_C1, R_AX_TBTTERLYINT_CFG_P3_C1,
R_AX_TBTTERLYINT_CFG_P4_C1}
};
static u32 bcnspc_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_BCN_SPACE_CFG_P0, R_AX_BCN_SPACE_CFG_P1, R_AX_BCN_SPACE_CFG_P2,
R_AX_BCN_SPACE_CFG_P3, R_AX_BCN_SPACE_CFG_P4},
{R_AX_BCN_SPACE_CFG_P0_C1, R_AX_BCN_SPACE_CFG_P1_C1,
R_AX_BCN_SPACE_CFG_P2_C1, R_AX_BCN_SPACE_CFG_P3_C1,
R_AX_BCN_SPACE_CFG_P4_C1}
};
static u32 tbttsht_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_TBTT_SHIFT_P0, R_AX_TBTT_SHIFT_P1, R_AX_TBTT_SHIFT_P2,
R_AX_TBTT_SHIFT_P3, R_AX_TBTT_SHIFT_P4},
{R_AX_TBTT_SHIFT_P0_C1, R_AX_TBTT_SHIFT_P1_C1, R_AX_TBTT_SHIFT_P2_C1,
R_AX_TBTT_SHIFT_P3_C1, R_AX_TBTT_SHIFT_P4_C1}
};
static u32 bcndrp_regl[MAC_AX_BAND_NUM] = {
R_AX_BCN_DROP_ALL0, R_AX_BCN_DROP_ALL0_C1
};
static u32 mbssid_drp_regl[MAC_AX_BAND_NUM] = {
R_AX_BCN_DROP_ALL0_P0MB, R_AX_BCN_DROP_ALL0_P0MB_C1
};
static u32 bcnpsr_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_BCN_PSR_RPT_P0, R_AX_BCN_PSR_RPT_P1, R_AX_BCN_PSR_RPT_P2,
R_AX_BCN_PSR_RPT_P3, R_AX_BCN_PSR_RPT_P4},
{R_AX_BCN_PSR_RPT_P0_C1, R_AX_BCN_PSR_RPT_P1_C1, R_AX_BCN_PSR_RPT_P2_C1,
R_AX_BCN_PSR_RPT_P3_C1, R_AX_BCN_PSR_RPT_P4_C1}
};
static u32 cnt_tmr_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_BCN_CNT_TMR_P0, R_AX_BCN_CNT_TMR_P1, R_AX_BCN_CNT_TMR_P2,
R_AX_BCN_CNT_TMR_P3, R_AX_BCN_CNT_TMR_P4},
{R_AX_BCN_CNT_TMR_P0_C1, R_AX_BCN_CNT_TMR_P1_C1, R_AX_BCN_CNT_TMR_P2_C1,
R_AX_BCN_CNT_TMR_P3_C1, R_AX_BCN_CNT_TMR_P4_C1}
};
static u32 hiq_win_port_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG,
R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2,
R_AX_PORT_HGQ_WINDOW_CFG + 3},
{R_AX_P0MB_HGQ_WINDOW_CFG_0_C1, R_AX_PORT_HGQ_WINDOW_CFG_C1,
R_AX_PORT_HGQ_WINDOW_CFG_C1 + 1, R_AX_PORT_HGQ_WINDOW_CFG_C1 + 2,
R_AX_PORT_HGQ_WINDOW_CFG_C1 + 3}
};
static u32 hiq_win_mbid_regl[MAC_AX_BAND_NUM][MAC_AX_P0_MBID_MAX] = {
{R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_P0MB_HGQ_WINDOW_CFG_0 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_0 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_0 + 3,
R_AX_P0MB_HGQ_WINDOW_CFG_1, R_AX_P0MB_HGQ_WINDOW_CFG_1 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_1 + 3,
R_AX_P0MB_HGQ_WINDOW_CFG_2, R_AX_P0MB_HGQ_WINDOW_CFG_2 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_2 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_2 + 3,
R_AX_P0MB_HGQ_WINDOW_CFG_3, R_AX_P0MB_HGQ_WINDOW_CFG_3 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_3 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_3 + 3},
{R_AX_P0MB_HGQ_WINDOW_CFG_0_C1, R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 + 3,
R_AX_P0MB_HGQ_WINDOW_CFG_1_C1, R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_1_C1 + 3,
R_AX_P0MB_HGQ_WINDOW_CFG_2_C1, R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_2_C1 + 3,
R_AX_P0MB_HGQ_WINDOW_CFG_3_C1, R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 + 1,
R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 + 2, R_AX_P0MB_HGQ_WINDOW_CFG_3_C1 + 3}
};
static u32 dtim_prd_port_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_DTIM_CTRL_P0 + 1, R_AX_DTIM_CTRL_P1 + 1,
R_AX_DTIM_CTRL_P2 + 1, R_AX_DTIM_CTRL_P3 + 1,
R_AX_DTIM_CTRL_P4 + 1},
{R_AX_DTIM_CTRL_P0_C1 + 1, R_AX_DTIM_CTRL_P1_C1 + 1,
R_AX_DTIM_CTRL_P2_C1 + 1, R_AX_DTIM_CTRL_P3_C1 + 1,
R_AX_DTIM_CTRL_P4_C1 + 1}
};
static u32 dtim_prd_mbid_regl[MAC_AX_BAND_NUM][MAC_AX_P0_MBID_MAX] = {
{R_AX_DTIM_CTRL_P0 + 1, R_AX_DTIM_NUM0 + 1, R_AX_DTIM_NUM0 + 2,
R_AX_DTIM_NUM0 + 3, R_AX_DTIM_NUM1, R_AX_DTIM_NUM1 + 1,
R_AX_DTIM_NUM1 + 2, R_AX_DTIM_NUM1 + 3, R_AX_DTIM_NUM2,
R_AX_DTIM_NUM2 + 1, R_AX_DTIM_NUM2 + 2, R_AX_DTIM_NUM2 + 3,
R_AX_DTIM_NUM3, R_AX_DTIM_NUM3 + 1, R_AX_DTIM_NUM3 + 2,
R_AX_DTIM_NUM3 + 3},
{R_AX_DTIM_CTRL_P0_C1 + 1, R_AX_DTIM_NUM0_C1 + 1, R_AX_DTIM_NUM0_C1 + 2,
R_AX_DTIM_NUM0_C1 + 3, R_AX_DTIM_NUM1_C1, R_AX_DTIM_NUM1_C1 + 1,
R_AX_DTIM_NUM1_C1 + 2, R_AX_DTIM_NUM1_C1 + 3, R_AX_DTIM_NUM2_C1,
R_AX_DTIM_NUM2_C1 + 1, R_AX_DTIM_NUM2_C1 + 2, R_AX_DTIM_NUM2_C1 + 3,
R_AX_DTIM_NUM3_C1, R_AX_DTIM_NUM3_C1 + 1, R_AX_DTIM_NUM3_C1 + 2,
R_AX_DTIM_NUM3_C1 + 3}
};
static u32 dtim_switch[MAC_AX_BAND_NUM] = {
R_AX_MD_TSFT_STMP_CTL, R_AX_MD_TSFT_STMP_CTL_C1
};
static u32 hiq_nolmt_regl[MAC_AX_BAND_NUM] = {
R_AX_EN_HGQ_NOLIMIT, R_AX_EN_HGQ_NOLIMIT_C1
};
static u32 mbid_ctrl_regl[MAC_AX_BAND_NUM] = {
R_AX_MBSSID_CTRL, R_AX_MBSSID_CTRL_C1
};
static u32 bcn_early_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_BCNERLYINT_CFG_P0, R_AX_BCNERLYINT_CFG_P1,
R_AX_BCNERLYINT_CFG_P2, R_AX_BCNERLYINT_CFG_P3,
R_AX_BCNERLYINT_CFG_P4},
{R_AX_BCNERLYINT_CFG_P0_C1, R_AX_BCNERLYINT_CFG_P1_C1,
R_AX_BCNERLYINT_CFG_P2_C1, R_AX_BCNERLYINT_CFG_P3_C1,
R_AX_BCNERLYINT_CFG_P4_C1}
};
static u32 tsfl_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_TSFTR_LOW_P0, R_AX_TSFTR_LOW_P1, R_AX_TSFTR_LOW_P2,
R_AX_TSFTR_LOW_P3, R_AX_TSFTR_LOW_P4},
{R_AX_TSFTR_LOW_P0_C1, R_AX_TSFTR_LOW_P1_C1, R_AX_TSFTR_LOW_P2_C1,
R_AX_TSFTR_LOW_P3_C1, R_AX_TSFTR_LOW_P4_C1}
};
static u32 ptcl_dbg_regl[MAC_AX_BAND_NUM] = {
R_AX_PTCL_DBG, R_AX_PTCL_DBG_C1
};
static u32 bss_color_regl[MAC_AX_BAND_NUM][MAC_AX_PORT_NUM] = {
{R_AX_PTCL_BSS_COLOR_0,
R_AX_PTCL_BSS_COLOR_0,
R_AX_PTCL_BSS_COLOR_0,
R_AX_PTCL_BSS_COLOR_0,
R_AX_PTCL_BSS_COLOR_1},
{R_AX_PTCL_BSS_COLOR_0_C1,
R_AX_PTCL_BSS_COLOR_0_C1,
R_AX_PTCL_BSS_COLOR_0_C1,
R_AX_PTCL_BSS_COLOR_0_C1,
R_AX_PTCL_BSS_COLOR_1_C1}
};
static u32 ptcl_dbg_info_regl[MAC_AX_BAND_NUM] = {
R_AX_PTCL_DBG_INFO, R_AX_PTCL_DBG_INFO_C1
};
static u32 b_en_l[MAC_AX_PORT_NUM] = {
B_AX_PORT_FUNC_EN_P0, B_AX_PORT_FUNC_EN_P1, B_AX_PORT_FUNC_EN_P2,
B_AX_PORT_FUNC_EN_P3, B_AX_PORT_FUNC_EN_P4
};
static u32 b_txbcnrpt_l[MAC_AX_PORT_NUM] = {
B_AX_TXBCN_RPT_EN_P0, B_AX_TXBCN_RPT_EN_P1, B_AX_TXBCN_RPT_EN_P2,
B_AX_TXBCN_RPT_EN_P3, B_AX_TXBCN_RPT_EN_P4
};
static u32 b_rxbcnrpt_l[MAC_AX_PORT_NUM] = {
B_AX_RXBCN_RPT_EN_P0, B_AX_RXBCN_RPT_EN_P1, B_AX_RXBCN_RPT_EN_P2,
B_AX_RXBCN_RPT_EN_P3, B_AX_RXBCN_RPT_EN_P4
};
static u32 b_rxupd_l[MAC_AX_PORT_NUM] = {
B_AX_RX_BSSID_FIT_EN_P0, B_AX_RX_BSSID_FIT_EN_P1,
B_AX_RX_BSSID_FIT_EN_P2, B_AX_RX_BSSID_FIT_EN_P3,
B_AX_RX_BSSID_FIT_EN_P4
};
static u32 b_rxtsfupd_l[MAC_AX_PORT_NUM] = {
B_AX_TSF_UDT_EN_P0, B_AX_TSF_UDT_EN_P1, B_AX_TSF_UDT_EN_P2,
B_AX_TSF_UDT_EN_P3, B_AX_TSF_UDT_EN_P4
};
static u32 b_bcntxen_l[MAC_AX_PORT_NUM] = {
B_AX_BCNTX_EN_P0, B_AX_BCNTX_EN_P1, B_AX_BCNTX_EN_P2,
B_AX_BCNTX_EN_P3, B_AX_BCNTX_EN_P4
};
static u32 b_phben_l[MAC_AX_PORT_NUM] = {
B_AX_TBTT_PROHIB_EN_P0, B_AX_TBTT_PROHIB_EN_P1, B_AX_TBTT_PROHIB_EN_P2,
B_AX_TBTT_PROHIB_EN_P3, B_AX_TBTT_PROHIB_EN_P4
};
static u32 b_shten_l[MAC_AX_PORT_NUM] = {
B_AX_TBTT_UPD_SHIFT_SEL_P0, B_AX_TBTT_UPD_SHIFT_SEL_P1,
B_AX_TBTT_UPD_SHIFT_SEL_P2, B_AX_TBTT_UPD_SHIFT_SEL_P3,
B_AX_TBTT_UPD_SHIFT_SEL_P4
};
static u32 b_brken_l[MAC_AX_PORT_NUM] = {
B_AX_BRK_SETUP_P0, B_AX_BRK_SETUP_P1, B_AX_BRK_SETUP_P2,
B_AX_BRK_SETUP_P3, B_AX_BRK_SETUP_P4
};
static u32 b_rsttsf_l[MAC_AX_PORT_NUM] = {
B_AX_TSFTR_RST_P0, B_AX_TSFTR_RST_P1, B_AX_TSFTR_RST_P2,
B_AX_TSFTR_RST_P3, B_AX_TSFTR_RST_P4
};
static u32 b_drpall_l[MAC_AX_PORT_NUM] = {
B_AX_BCN_DROP_ALL_P0, B_AX_BCN_DROP_ALL_P1, B_AX_BCN_DROP_ALL_P2,
B_AX_BCN_DROP_ALL_P3, B_AX_BCN_DROP_ALL_P4
};
static u32 b_rptvld_l[MAC_AX_PORT_NUM] = {
B_AX_RPT_VALID_P0, B_AX_RPT_VALID_P1, B_AX_RPT_VALID_P2,
B_AX_RPT_VALID_P3, B_AX_RPT_VALID_P4
};
static u32 b_timerr_l[MAC_AX_PORT_NUM] = {
B_AX_TIM_ILEGAL_P0, B_AX_TIM_ILEGAL_P1, B_AX_TIM_ILEGAL_P2,
B_AX_TIM_ILEGAL_P3, B_AX_TIM_ILEGAL_P4
};
static u32 b_mbid_en_l[MAC_AX_P0_MBID_MAX - 1] = {
B_AX_P0MB1_EN, B_AX_P0MB2_EN, B_AX_P0MB3_EN, B_AX_P0MB4_EN,
B_AX_P0MB5_EN, B_AX_P0MB6_EN, B_AX_P0MB7_EN, B_AX_P0MB8_EN,
B_AX_P0MB9_EN, B_AX_P0MB10_EN, B_AX_P0MB11_EN, B_AX_P0MB12_EN,
B_AX_P0MB13_EN, B_AX_P0MB14_EN, B_AX_P0MB15_EN
};
static u32 b_mbid_drp_l[MAC_AX_P0_MBID_MAX - 1] = {
B_AX_BCN_DROP_ALL_P0MB1, B_AX_BCN_DROP_ALL_P0MB2,
B_AX_BCN_DROP_ALL_P0MB3, B_AX_BCN_DROP_ALL_P0MB4,
B_AX_BCN_DROP_ALL_P0MB5, B_AX_BCN_DROP_ALL_P0MB6,
B_AX_BCN_DROP_ALL_P0MB7, B_AX_BCN_DROP_ALL_P0MB8,
B_AX_BCN_DROP_ALL_P0MB9, B_AX_BCN_DROP_ALL_P0MB10,
B_AX_BCN_DROP_ALL_P0MB11, B_AX_BCN_DROP_ALL_P0MB12,
B_AX_BCN_DROP_ALL_P0MB13, B_AX_BCN_DROP_ALL_P0MB14,
B_AX_BCN_DROP_ALL_P0MB15
};
static u32 b_hiq_nolmt_mbid_l[MAC_AX_P0_MBID_MAX - 1] = {
B_AX_HIQ_NO_LMT_EN_P0_VAP1, B_AX_HIQ_NO_LMT_EN_P0_VAP2,
B_AX_HIQ_NO_LMT_EN_P0_VAP3, B_AX_HIQ_NO_LMT_EN_P0_VAP4,
B_AX_HIQ_NO_LMT_EN_P0_VAP5, B_AX_HIQ_NO_LMT_EN_P0_VAP6,
B_AX_HIQ_NO_LMT_EN_P0_VAP7, B_AX_HIQ_NO_LMT_EN_P0_VAP8,
B_AX_HIQ_NO_LMT_EN_P0_VAP9, B_AX_HIQ_NO_LMT_EN_P0_VAP10,
B_AX_HIQ_NO_LMT_EN_P0_VAP11, B_AX_HIQ_NO_LMT_EN_P0_VAP12,
B_AX_HIQ_NO_LMT_EN_P0_VAP13, B_AX_HIQ_NO_LMT_EN_P0_VAP14,
B_AX_HIQ_NO_LMT_EN_P0_VAP15
};
static u32 b_hiq_nolmt_port_l[MAC_AX_PORT_NUM] = {
B_AX_HIQ_NO_LMT_EN_P0_ROOT, B_AX_HIQ_NO_LMT_EN_P1,
B_AX_HIQ_NO_LMT_EN_P2, B_AX_HIQ_NO_LMT_EN_P3, B_AX_HIQ_NO_LMT_EN_P4
};
static u32 mbid_idx_l[MAC_AX_P0_MBID_MAX] = {
MAC_AX_P0_ROOT, MAC_AX_P0_MBID1, MAC_AX_P0_MBID2, MAC_AX_P0_MBID3,
MAC_AX_P0_MBID4, MAC_AX_P0_MBID5, MAC_AX_P0_MBID6, MAC_AX_P0_MBID7,
MAC_AX_P0_MBID8, MAC_AX_P0_MBID9, MAC_AX_P0_MBID10, MAC_AX_P0_MBID11,
MAC_AX_P0_MBID12, MAC_AX_P0_MBID13, MAC_AX_P0_MBID14, MAC_AX_P0_MBID15
};
static u32 t32_togl_rpt_size =
sizeof(struct mac_ax_t32_togl_rpt) * MAC_AX_BAND_NUM * MAC_AX_PORT_NUM;
static u32 port_info_size =
sizeof(struct mac_ax_port_info) * MAC_AX_BAND_NUM * MAC_AX_PORT_NUM;
static u32 _get_max_mbid(struct mac_ax_adapter *adapter, u8 *mbid_max)
{
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
*mbid_max = MAC_AX_P0_MBID15;
else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
*mbid_max = MAC_AX_P0_MBID3;
else
return MACCHIPID;
return MACSUCCESS;
}
u32 get_bp_idx(u8 band, u8 port)
{
return (band * MAC_AX_BAND_NUM + port);
}
u32 _get_port_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_port_cfg_type type,
struct mac_ax_port_cfg_para *para)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 mbssid_idx = para->mbssid_idx;
u8 port = para->port;
u8 band = para->band;
u32 val32;
u16 val16;
u8 mbid_max;
u32 ret;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
band != MAC_AX_BAND_0) {
PLTFM_MSG_ERR("[ERR] invalid band idx %d\n", band);
return MACFUNCINPUT;
}
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR] invalid port idx %d\n", port);
return MACPORTCFGPORT;
}
if (mbssid_idx) {
ret = _get_max_mbid(adapter, &mbid_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret);
return MACPORTCFGPORT;
}
if (mbssid_idx > (u32)mbid_max) {
PLTFM_MSG_ERR("[ERR] invalid mbssid %d\n", mbssid_idx);
return MACFUNCINPUT;
}
}
switch (type) {
case MAC_AX_PCFG_NET_TYPE:
val32 = MAC_REG_R32(cfg_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = GET_FIELD(val32, B_AX_NET_TYPE_P0);
break;
case MAC_AX_PORT_1:
para->val = GET_FIELD(val32, B_AX_NET_TYPE_P1);
break;
case MAC_AX_PORT_2:
para->val = GET_FIELD(val32, B_AX_NET_TYPE_P2);
break;
case MAC_AX_PORT_3:
para->val = GET_FIELD(val32, B_AX_NET_TYPE_P3);
break;
case MAC_AX_PORT_4:
para->val = GET_FIELD(val32, B_AX_NET_TYPE_P4);
break;
}
break;
case MAC_AX_PCFG_FUNC_SW:
val32 = MAC_REG_R32(cfg_regl[band][port]);
if (val32 & b_en_l[port])
para->val = 1;
else
para->val = 0;
break;
case MAC_AX_PCFG_BCN_INTV:
val32 = MAC_REG_R32(bcnspc_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = mbssid_idx ?
GET_FIELD(val32, B_AX_SUB_BCN_SPACE_P0) :
GET_FIELD(val32, B_AX_BCN_SPACE_P0);
break;
case MAC_AX_PORT_1:
para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P1);
break;
case MAC_AX_PORT_2:
para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P2);
break;
case MAC_AX_PORT_3:
para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P3);
break;
case MAC_AX_PORT_4:
para->val = GET_FIELD(val32, B_AX_BCN_SPACE_P4);
break;
}
break;
case MAC_AX_PCFG_BCN_HOLD_TIME:
val32 = MAC_REG_R32(phb_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = GET_FIELD(val32, B_AX_TBTT_HOLD_P0);
break;
case MAC_AX_PORT_1:
case MAC_AX_PORT_2:
case MAC_AX_PORT_3:
case MAC_AX_PORT_4:
para->val = GET_FIELD(val32, B_AX_TBTT_HOLD_P1);
break;
}
break;
case MAC_AX_PCFG_BCN_ERLY:
val32 = MAC_REG_R32(bcn_early_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = GET_FIELD(val32, B_AX_BCNERLY_P0);
break;
case MAC_AX_PORT_1:
para->val = GET_FIELD(val32, B_AX_BCNERLY_P1);
break;
case MAC_AX_PORT_2:
para->val = GET_FIELD(val32, B_AX_BCNERLY_P2);
break;
case MAC_AX_PORT_3:
para->val = GET_FIELD(val32, B_AX_BCNERLY_P3);
break;
case MAC_AX_PORT_4:
para->val = GET_FIELD(val32, B_AX_BCNERLY_P4);
break;
}
break;
case MAC_AX_PCFG_BCN_SETUP_TIME:
val32 = MAC_REG_R32(phb_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = GET_FIELD(val32, B_AX_TBTT_SETUP_P0);
break;
case MAC_AX_PORT_1:
case MAC_AX_PORT_2:
case MAC_AX_PORT_3:
case MAC_AX_PORT_4:
para->val = GET_FIELD(val32, B_AX_TBTT_SETUP_P1);
break;
}
break;
case MAC_AX_PCFG_TBTT_ERLY:
val16 = MAC_REG_R16(tbttery_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = GET_FIELD(val16, B_AX_TBTTERLY_P0);
break;
case MAC_AX_PORT_1:
para->val = GET_FIELD(val16, B_AX_TBTTERLY_P1);
break;
case MAC_AX_PORT_2:
para->val = GET_FIELD(val16, B_AX_TBTTERLY_P2);
break;
case MAC_AX_PORT_3:
para->val = GET_FIELD(val16, B_AX_TBTTERLY_P3);
break;
case MAC_AX_PORT_4:
para->val = GET_FIELD(val16, B_AX_TBTTERLY_P4);
break;
}
break;
case MAC_AX_PCFG_BCN_MASK_AREA:
val32 = MAC_REG_R32(mskarea_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P0);
break;
case MAC_AX_PORT_1:
para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P1);
break;
case MAC_AX_PORT_2:
para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P2);
break;
case MAC_AX_PORT_3:
para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P3);
break;
case MAC_AX_PORT_4:
para->val = GET_FIELD(val32, B_AX_BCN_MSK_AREA_P4);
break;
}
break;
default:
PLTFM_MSG_ERR("[ERR] invalid get cfg type %d\n", type);
return MACPORTCFGTYPE;
}
return MACSUCCESS;
}
static u32 _port_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_port_cfg_type type,
struct mac_ax_port_cfg_para *para)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 set_val = para->val;
u8 port = para->port;
u8 band = para->band;
u32 val32;
u32 w_val32 = MAC_AX_R32_DEAD;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
band != MAC_AX_BAND_0) {
PLTFM_MSG_ERR("[ERR] invalid band idx %d\n", band);
return MACFUNCINPUT;
}
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR] invalid port idx %d\n", port);
return MACPORTCFGPORT;
}
switch (type) {
case MAC_AX_PCFG_NET_TYPE:
val32 = MAC_REG_R32(cfg_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_NET_TYPE_P0);
break;
case MAC_AX_PORT_1:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_NET_TYPE_P1);
break;
case MAC_AX_PORT_2:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_NET_TYPE_P2);
break;
case MAC_AX_PORT_3:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_NET_TYPE_P3);
break;
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_NET_TYPE_P4);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
default:
PLTFM_MSG_ERR("[ERR] invalid cfg type %d\n", type);
return MACPORTCFGTYPE;
}
return MACSUCCESS;
}
static u32 _bcn_setup_chk(struct mac_ax_adapter *adapter, u8 band, u8 port,
u32 *set_val)
{
struct mac_ax_port_cfg_para cfg_para;
struct mac_ax_port_info *pinfo_self, *pinfo_tmp;
u32 ret;
u32 up_lmt = 0xFFFFFFFF;
u8 port_idx;
pinfo_self = &adapter->port_info[get_bp_idx(band, port)];
if (port == MAC_AX_PORT_0 && pinfo_self->stat == PORT_ST_DIS)
return MACSUCCESS;
if (*set_val > B_AX_TBTT_SETUP_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal bcn setup time %d\n", *set_val);
return MACFUNCINPUT;
}
for (port_idx = MAC_AX_PORT_0; port_idx < MAC_AX_PORT_NUM; port_idx++) {
pinfo_tmp = &adapter->port_info[get_bp_idx(band, port_idx)];
if (pinfo_tmp->stat == PORT_ST_DIS)
continue;
if (port != MAC_AX_PORT_0 && port_idx == MAC_AX_PORT_0)
continue;
cfg_para.band = band;
cfg_para.port = port_idx;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn erly fail %d\n",
ret);
return ret;
}
if (cfg_para.val < up_lmt)
up_lmt = cfg_para.val;
if (port == MAC_AX_PORT_0)
break;
}
if (*set_val >= up_lmt) {
PLTFM_MSG_WARN("[WARN]setup time %d over hw limit\n", *set_val);
*set_val = up_lmt - 1;
return MACSETVALERR;
}
return MACSUCCESS;
}
static u32 _bcn_mask_chk(struct mac_ax_adapter *adapter, u8 band, u8 port,
u32 *set_val)
{
struct mac_ax_port_cfg_para cfg_para;
struct mac_ax_port_info *pinfo;
u32 ret;
pinfo = &adapter->port_info[get_bp_idx(band, port)];
if (pinfo->stat == PORT_ST_DIS)
return MACSUCCESS;
if (*set_val > B_AX_BCN_MSK_AREA_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal mask area %d\n", *set_val);
return MACFUNCINPUT;
}
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn hold fail %d\n", ret);
return ret;
}
if (*set_val > cfg_para.val) {
PLTFM_MSG_WARN("[WARN]mask area %d over hw limit\n", *set_val);
*set_val = cfg_para.val;
return MACSETVALERR;
}
return MACSUCCESS;
}
static u32 _bcn_hold_chk(struct mac_ax_adapter *adapter, u8 band, u8 port,
u32 *set_val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_port_cfg_para cfg_para;
struct mac_ax_port_info *pinfo_self, *pinfo_tmp;
u32 ret, bcn_erly, bcn_spc, val32;
u8 port_idx;
u32 low_lmt = 0, up_lmt = 0xFFFFFFFF;
pinfo_self = &adapter->port_info[get_bp_idx(band, port)];
if (port == MAC_AX_PORT_0 && pinfo_self->stat == PORT_ST_DIS)
return MACSUCCESS;
if (*set_val > B_AX_TBTT_HOLD_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal hold time %d\n", *set_val);
return MACFUNCINPUT;
}
for (port_idx = MAC_AX_PORT_0; port_idx < MAC_AX_PORT_NUM; port_idx++) {
pinfo_tmp = &adapter->port_info[get_bp_idx(band, port_idx)];
if (pinfo_tmp->stat == PORT_ST_DIS)
continue;
if (port != MAC_AX_PORT_0 && port_idx == MAC_AX_PORT_0)
continue;
cfg_para.band = band;
cfg_para.port = port_idx;
cfg_para.mbssid_idx = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA,
&cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg mask area fail %d\n",
ret);
return ret;
}
if (cfg_para.val > low_lmt)
low_lmt = cfg_para.val;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn erly fail %d\n",
ret);
return ret;
}
bcn_erly = cfg_para.val;
if (port == MAC_AX_PORT_0 &&
GET_FIELD(MAC_REG_R32(mbid_ctrl_regl[band]), B_AX_P0MB_NUM))
cfg_para.mbssid_idx = 1;
else
cfg_para.mbssid_idx = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn intv fail %d\n",
ret);
return ret;
}
bcn_spc = cfg_para.val;
val32 = bcn_spc * TU_TO_BCN_SET - bcn_erly;
if (val32 < up_lmt)
up_lmt = val32;
if (port == MAC_AX_PORT_0)
break;
}
if (*set_val < low_lmt) {
PLTFM_MSG_WARN("[WARN]hold time %d below hw limit\n", *set_val);
*set_val = low_lmt;
return MACSETVALERR;
}
if (*set_val >= up_lmt) {
PLTFM_MSG_WARN("[WARN]hold time %d over hw limit\n", *set_val);
*set_val = up_lmt - 1;
return MACSETVALERR;
}
return MACSUCCESS;
}
static u32 _bcn_erly_chk(struct mac_ax_adapter *adapter, u8 band, u8 port,
u32 *set_val)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_port_cfg_para cfg_para;
struct mac_ax_port_info *pinfo;
u32 ret, bcn_hold, bcn_spc, val32;
pinfo = &adapter->port_info[get_bp_idx(band, port)];
if (pinfo->stat == PORT_ST_DIS)
return MACSUCCESS;
if (*set_val > B_AX_BCNERLY_P0_MSK || !*set_val) {
PLTFM_MSG_ERR("[ERR] illegal bcn erly %d\n", *set_val);
return MACFUNCINPUT;
}
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn setup fail %d\n", ret);
return ret;
}
if (*set_val <= cfg_para.val) {
PLTFM_MSG_WARN("[WARN]bcn erly %d below hw limit\n", *set_val);
*set_val = cfg_para.val + 1;
return MACSETVALERR;
}
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg tbtt erly fail %d\n", ret);
return ret;
}
val32 = cfg_para.val / BCN_SET_TO_US;
if (*set_val <= val32) {
PLTFM_MSG_WARN("[WARN]bcn erly %d below hw limit\n", *set_val);
*set_val = val32 + 1;
return MACSETVALERR;
}
cfg_para.band = band;
cfg_para.port = port;
if (port == MAC_AX_PORT_0 &&
GET_FIELD(MAC_REG_R32(mbid_ctrl_regl[band]), B_AX_P0MB_NUM))
cfg_para.mbssid_idx = 1;
else
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn intv fail %d\n", ret);
return ret;
}
bcn_spc = cfg_para.val;
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] get port cfg bcn hold fail %d\n", ret);
return ret;
}
bcn_hold = cfg_para.val;
val32 = bcn_spc * TU_TO_BCN_SET - bcn_hold;
if (*set_val >= val32) {
PLTFM_MSG_WARN("[WARN]bcn erly %d over hw limit\n", *set_val);
*set_val = val32 - 1;
return MACSETVALERR;
}
return MACSUCCESS;
}
static u32 _tbtt_erly_chk(struct mac_ax_adapter *adapter, u8 band, u8 port,
u32 *set_val)
{
struct mac_ax_port_cfg_para cfg_para;
struct mac_ax_port_info *pinfo;
u32 ret, val32;
pinfo = &adapter->port_info[get_bp_idx(band, port)];
if (pinfo->stat == PORT_ST_DIS)
return MACSUCCESS;
if (*set_val > B_AX_TBTTERLY_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal tbtt erly %d\n", *set_val);
return MACFUNCINPUT;
}
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get port cfg bcn erly fail %d\n", ret);
return ret;
}
val32 = cfg_para.val * BCN_SET_TO_US;
if (*set_val >= val32) {
PLTFM_MSG_WARN("[WARN] tbtt erly %d over hw limit\n", *set_val);
*set_val = val32 - 1;
return MACSETVALERR;
}
return MACSUCCESS;
}
static u32 _set_max_mbid_num(struct mac_ax_adapter *adapter,
struct mac_ax_port_cfg_para *para)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_port_cfg_para cfg_para;
u8 port = para->port;
u8 band = para->band;
u32 mbid_num = para->mbssid_idx;
u32 ret;
u32 bcn_erly;
u32 hold_time;
u32 subspc;
u32 val32, w_val32;
if (mbid_num && !(mbid_num % 2))
mbid_num++;
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d get cfg bcn_erly fail %d\n",
band, port, ret);
return ret;
}
bcn_erly = cfg_para.val;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d get cfg hold_time fail %d\n",
band, port, ret);
return ret;
}
hold_time = cfg_para.val;
subspc = para->val / (mbid_num + 1);
if (bcn_erly + hold_time > subspc * TU_TO_BCN_SET) {
PLTFM_MSG_ERR("[ERR] BcnSubspc not enough for erly and hold time\n");
para->val = (bcn_erly + hold_time) / TU_TO_BCN_SET * (mbid_num + 1);
return MACSUBSPCERR;
}
//set interval
cfg_para.val = para->val;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn intv fail %d\n",
band, port, ret);
return ret;
}
//set mbssid num
val32 = MAC_REG_R32(mbid_ctrl_regl[band]);
w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM);
if (val32 != w_val32)
MAC_REG_W32(mbid_ctrl_regl[band], w_val32);
//set subspace
val32 = MAC_REG_R32(bcnspc_regl[band][MAC_AX_PORT_0]);
if (mbid_num)
w_val32 = SET_CLR_WORD(val32, subspc, B_AX_SUB_BCN_SPACE_P0);
else
w_val32 = SET_CLR_WORD(val32, 0, B_AX_SUB_BCN_SPACE_P0);
if (w_val32 != val32)
MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], w_val32);
return MACSUCCESS;
}
static u32 port0_mbid_set(struct mac_ax_adapter *adapter, u8 band, u8 mbid_num,
u8 mbid_max)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, w_val32, i;
val32 = MAC_REG_R32(mbid_ctrl_regl[band]);
w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM);
for (i = 0; i < mbid_max; i++) {
if (i >= (MAC_AX_P0_MBID_MAX - 1)) {
PLTFM_MSG_ERR("mbid en idx %d over array %d\n", i,
MAC_AX_P0_MBID_MAX - 1);
return MACCMP;
}
w_val32 &= ~b_mbid_en_l[i];
}
if (w_val32 != val32)
MAC_REG_W32(mbid_ctrl_regl[band], w_val32);
return MACSUCCESS;
}
static u32 port0_subspc_set(struct mac_ax_adapter *adapter, u8 band,
u8 mbid_num, u32 *bcn_erly, u32 *hold_time)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 subspc_u32;
u32 val32, w_val32;
u32 ret = MACSUCCESS;
val32 = MAC_REG_R32(bcnspc_regl[band][MAC_AX_PORT_0]);
subspc_u32 = mbid_num ?
(GET_FIELD(val32, B_AX_BCN_SPACE_P0) / (mbid_num + 1)) : 0;
if (subspc_u32 > B_AX_SUB_BCN_SPACE_P0_MSK) {
PLTFM_MSG_ERR("[ERR] sub space %d overflow\n", subspc_u32);
return MACSUBSPCERR;
}
w_val32 = SET_CLR_WORD(val32, subspc_u32, B_AX_SUB_BCN_SPACE_P0);
if (w_val32 != val32)
MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], w_val32);
subspc_u32 *= TU_TO_BCN_SET;
if (mbid_num && (BCN_HOLD_DEF + BCN_ERLY_DEF) > subspc_u32) {
*bcn_erly = subspc_u32 * BCN_ERLY_RATIO / BCN_ITVL_RATIO;
*hold_time = subspc_u32 * BCN_HOLD_RATIO / BCN_ITVL_RATIO;
}
return ret;
}
u32 dly_port_tu(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_tu)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 cnt;
u32 ori_tsf;
u32 dly_us = dly_tu * TU_UNIT;
cnt = dly_tu * PORT_DLY_TU_CNT_LMT;
ori_tsf = MAC_REG_R32(tsfl_regl[band][port]);
PLTFM_DELAY_US(TU_UNIT);
do {
val32 = MAC_REG_R32(tsfl_regl[band][port]);
if ((val32 >= ori_tsf &&
(val32 - ori_tsf) >= dly_us) ||
(val32 < ori_tsf &&
(ori_tsf - val32 + 1) >= dly_us))
break;
if (val32 == ori_tsf) {
PLTFM_MSG_ERR("B%dP%d tsf not running 0x%X\n",
band, port, val32);
return MACHWERR;
}
PLTFM_DELAY_US(TU_UNIT);
cnt--;
} while (cnt);
if (!cnt)
return MACPOLLTO;
return MACSUCCESS;
}
u32 dly_port_us(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_us)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 cnt;
u32 ori_tsf;
cnt = dly_us * PORT_DLY_US_CNT_LMT;
ori_tsf = MAC_REG_R32(tsfl_regl[band][port]);
PLTFM_DELAY_US(10);
do {
val32 = MAC_REG_R32(tsfl_regl[band][port]);
if ((val32 >= ori_tsf &&
(val32 - ori_tsf) >= dly_us) ||
(val32 < ori_tsf &&
(ori_tsf - val32 + 1) >= dly_us))
break;
if (val32 == ori_tsf) {
PLTFM_MSG_ERR("B%dP%d tsf not running 0x%X\n",
band, port, val32);
return MACHWERR;
}
PLTFM_DELAY_US(10);
cnt--;
} while (cnt);
if (!cnt)
return MACPOLLTO;
return MACSUCCESS;
}
u32 rst_port_info(struct mac_ax_adapter *adapter, u8 band)
{
u8 p_idx;
for (p_idx = MAC_AX_PORT_0; p_idx < MAC_AX_PORT_NUM; p_idx++)
PLTFM_MEMSET(&adapter->port_info[get_bp_idx(band, p_idx)], 0,
sizeof(struct mac_ax_port_info));
return MACSUCCESS;
}
static u32 chk_bcnq_empty(struct mac_ax_adapter *adapter, u8 band, u8 port,
u32 bcn_spc, u8 *empty)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
u32 bcnq_num_sh, bcnq_num_msk;
u32 cnt, emp_cont_cnt;
u32 ret;
*empty = 1;
val32 = MAC_REG_R32(ptcl_dbg_regl[band]);
val32 = SET_CLR_WORD(val32, PTCL_DBG_BCNQ_NUM0, B_AX_PTCL_DBG_SEL);
MAC_REG_W32(ptcl_dbg_regl[band], val32);
PLTFM_DELAY_US(PTCL_DBG_DLY_US);
cnt = CHK_BCNQ_CNT;
emp_cont_cnt = 0;
do {
val32 = MAC_REG_R32(ptcl_dbg_info_regl[band]);
bcnq_num_sh = port * 2;
bcnq_num_msk = 3;
val32 = GET_FIEL2(val32, bcnq_num_sh, bcnq_num_msk);
if (val32)
emp_cont_cnt = 0;
else
emp_cont_cnt++;
if (emp_cont_cnt >= BCNQ_EMP_CONT_CNT) {
if (port == MAC_AX_PORT_0)
break;
return MACSUCCESS;
}
ret = dly_port_tu(adapter, band, port, bcn_spc);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] dly B%dP%d %d tu fail %d\n",
band, port, bcn_spc, val32);
return ret;
}
cnt--;
} while (cnt);
if (!cnt) {
PLTFM_MSG_ERR("[ERR] chk bcnq empty0 %d timeout\n", val32);
*empty = 0;
return MACPOLLTO;
}
val32 = MAC_REG_R32(ptcl_dbg_regl[band]);
val32 = SET_CLR_WORD(val32, PTCL_DBG_BCNQ_NUM1, B_AX_PTCL_DBG_SEL);
MAC_REG_W32(ptcl_dbg_regl[band], val32);
PLTFM_DELAY_US(PTCL_DBG_DLY_US);
cnt = CHK_BCNQ_CNT;
emp_cont_cnt = 0;
do {
val32 = MAC_REG_R32(ptcl_dbg_info_regl[band]);
if (val32)
emp_cont_cnt = 0;
else
emp_cont_cnt++;
if (emp_cont_cnt >= BCNQ_EMP_CONT_CNT)
return MACSUCCESS;
ret = dly_port_tu(adapter, band, port, bcn_spc);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] dly B%dP%d %d tu fail %d\n",
band, port, bcn_spc, val32);
return ret;
}
cnt--;
} while (cnt);
PLTFM_MSG_ERR("[ERR] chk bcnq empty1 %d timeout\n", val32);
*empty = 0;
return MACPOLLTO;
}
static u32 fast_bcn_drop(struct mac_ax_adapter *adapter, u8 band, u8 port)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_port_cfg_para cfg_para;
u32 ret = MACSUCCESS;
u32 port_drp_sel;
u32 mbid_drp_sel = 0;
u32 val32;
u32 bcn_spc;
u8 mbid_num;
u8 is_empty;
u32 i;
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
port_drp_sel = (port == MAC_AX_PORT_0 ? B_AX_BCN_DROP_ALL_P0 : 0) |
(port == MAC_AX_PORT_1 ? B_AX_BCN_DROP_ALL_P1 : 0) |
(port == MAC_AX_PORT_2 ? B_AX_BCN_DROP_ALL_P2 : 0) |
(port == MAC_AX_PORT_3 ? B_AX_BCN_DROP_ALL_P3 : 0) |
(port == MAC_AX_PORT_4 ? B_AX_BCN_DROP_ALL_P4 : 0);
val32 = MAC_REG_R32(bcndrp_regl[band]) | port_drp_sel;
MAC_REG_W32(bcndrp_regl[band], val32);
if (port == MAC_AX_PORT_0) {
mbid_drp_sel = B_AX_BCN_DROP_ALL_P0MB1 |
B_AX_BCN_DROP_ALL_P0MB2 |
B_AX_BCN_DROP_ALL_P0MB3;
if (!is_chip_id(adapter, MAC_AX_CHIP_ID_8852B))
mbid_drp_sel |= B_AX_BCN_DROP_ALL_P0MB4 |
B_AX_BCN_DROP_ALL_P0MB5 |
B_AX_BCN_DROP_ALL_P0MB6 |
B_AX_BCN_DROP_ALL_P0MB7 |
B_AX_BCN_DROP_ALL_P0MB8 |
B_AX_BCN_DROP_ALL_P0MB9 |
B_AX_BCN_DROP_ALL_P0MB10 |
B_AX_BCN_DROP_ALL_P0MB11 |
B_AX_BCN_DROP_ALL_P0MB12 |
B_AX_BCN_DROP_ALL_P0MB13 |
B_AX_BCN_DROP_ALL_P0MB14 |
B_AX_BCN_DROP_ALL_P0MB15;
val32 = MAC_REG_R32(mbssid_drp_regl[band]) | mbid_drp_sel;
MAC_REG_W32(mbssid_drp_regl[band], val32);
}
cfg_para.val = 1;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] port cfg func setup time fail %d\n", ret);
return ret;
}
cfg_para.val = 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] port cfg func mask area fail %d\n", ret);
return ret;
}
cfg_para.val = 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] port cfg func hold time fail %d\n", ret);
return ret;
}
cfg_para.val = 2;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] port cfg func bcn early fail %d\n", ret);
return ret;
}
cfg_para.val = 1;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] port cfg tbtt early fail %d\n", ret);
return ret;
}
if (port == MAC_AX_PORT_0) {
ret = _get_max_mbid(adapter, &mbid_num);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret);
return MACPORTCFGPORT;
}
bcn_spc = (u32)(mbid_num + 1) * BCN_FAST_DRP_TBTT;
val32 = MAC_REG_R32(bcnspc_regl[band][MAC_AX_PORT_0]);
val32 = SET_CLR_WORD(val32, BCN_FAST_DRP_TBTT,
B_AX_SUB_BCN_SPACE_P0);
MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], val32);
val32 = SET_CLR_WORD(val32, bcn_spc, B_AX_BCN_SPACE_P0);
MAC_REG_W32(bcnspc_regl[band][MAC_AX_PORT_0], val32);
val32 = MAC_REG_R32(mbid_ctrl_regl[band]);
val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM);
for (i = 0; i < mbid_num; i++)
val32 |= b_mbid_en_l[i];
MAC_REG_W32(mbid_ctrl_regl[band], val32);
} else {
bcn_spc = BCN_FAST_DRP_TBTT;
cfg_para.val = bcn_spc;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] port cfg func bcn intv fail %d\n",
ret);
return ret;
}
}
ret = chk_bcnq_empty(adapter, band, port, bcn_spc, &is_empty);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] chk bcnq empty fail %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(bcndrp_regl[band]) & ~port_drp_sel;
MAC_REG_W32(bcndrp_regl[band], val32);
if (port == MAC_AX_PORT_0) {
val32 = MAC_REG_R32(mbssid_drp_regl[band]) & ~mbid_drp_sel;
MAC_REG_W32(mbssid_drp_regl[band], val32);
}
val32 = MAC_REG_R32(cfg_regl[band][port]) & ~b_phben_l[port];
MAC_REG_W32(cfg_regl[band][port], val32);
ret = dly_port_tu(adapter, band, port, bcn_spc + 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d dly %d tu fail %d\n",
band, port, bcn_spc + 1, ret);
return ret;
}
return MACSUCCESS;
}
u32 _patch_port_dis_flow(struct mac_ax_adapter *adapter, u8 band, u8 port,
struct mac_ax_port_info *pinfo)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_port_cfg_para cfg_para;
u32 bcn_set_bk = MAC_AX_R32_DEAD;
u32 bcn_spc;
u32 val32;
u32 ret = MACSUCCESS;
u16 val16;
u8 patch_flag, phb_bkp_flag;
u8 mbid_max;
patch_flag = is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ? 1 : 0;
phb_bkp_flag = patch_flag && port != MAC_AX_PORT_0 ? 1 : 0;
if (phb_bkp_flag)
bcn_set_bk = MAC_REG_R32(phb_regl[band][port]);
if (pinfo->stat == PORT_ST_AP || pinfo->stat == PORT_ST_ADHOC) {
ret = fast_bcn_drop(adapter, band, port);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] fast bcn drop fail %d\n",
ret);
goto end;
}
}
if (patch_flag) {
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
cfg_para.val = 0;
ret = _get_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] get port cfg bcn intv fail %d\n",
ret);
goto end;
}
bcn_spc = cfg_para.val;
val32 = MAC_REG_R32(phb_regl[band][port]);
val32 = SET_CLR_WORD(val32, 0, B_AX_TBTT_SETUP_P0);
val32 = SET_CLR_WORD(val32, 1, B_AX_TBTT_HOLD_P0);
MAC_REG_W32(phb_regl[band][port], val32);
val16 = MAC_REG_R16(tbttery_regl[band][port]);
val16 = SET_CLR_WORD(val16, 0, B_AX_TBTTERLY_P0);
MAC_REG_W16(tbttery_regl[band][port], val16);
val16 = MAC_REG_R16(bcn_early_regl[band][port]);
val16 = SET_CLR_WORD(val16, 0, B_AX_BCNERLY_P0);
MAC_REG_W16(bcn_early_regl[band][port], val16);
ret = dly_port_tu(adapter, band, port, bcn_spc + 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d dly %d tu fail %d\n",
band, port, bcn_spc, ret);
goto end;
}
}
if (port == MAC_AX_PORT_0) {
ret = _get_max_mbid(adapter, &mbid_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret);
return MACPORTCFGPORT;
}
ret = port0_mbid_set(adapter, band, 0, mbid_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d mbid set fail %d\n",
band, port, ret);
return ret;
}
}
val32 = MAC_REG_R32(cfg_regl[band][port]) &
~(b_en_l[port] | b_brken_l[port]);
MAC_REG_W32(cfg_regl[band][port], val32);
val32 |= b_rsttsf_l[port];
MAC_REG_W32(cfg_regl[band][port], val32);
MAC_REG_W32(cnt_tmr_regl[band][port], 0);
pinfo->stat = PORT_ST_DIS;
end:
if (phb_bkp_flag) {
if (bcn_set_bk != MAC_AX_R32_DEAD) {
MAC_REG_W32(phb_regl[band][port], bcn_set_bk);
} else {
PLTFM_MSG_ERR("[ERR]prev ret %d\n", ret);
PLTFM_MSG_ERR("[ERR]B%dP%d phb reg dead\n", band, port);
ret = MACCMP;
}
}
return ret;
}
u32 mac_port_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_port_cfg_type type,
struct mac_ax_port_cfg_para *para)
{
struct mac_ax_port_info *pinfo;
u8 band = para->band;
u8 port = para->port;
#if 0 // MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_port_cfg *hdr;
u32 ret = MACSUCCESS;
u32 cnt;
if (para->band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("[ERR]invalid band %d\n", para->band);
return MACFUNCINPUT;
}
if (para->port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port %d\n", para->port);
return MACFUNCINPUT;
}
pinfo = &adapter->port_info[get_bp_idx(band, port)];
cnt = PORT_H2C_DLY_CNT;
while (pinfo->h2c_sm == MAC_AX_PORT_H2C_BUSY) {
cnt--;
if (!cnt) {
PLTFM_MSG_ERR("[ERR]B%dP%d port H2C busy\n",
band, port);
return MACPROCBUSY;
}
PLTFM_DELAY_US(PORT_H2C_DLY_US);
}
if (pinfo->h2c_sm == MAC_AX_PORT_H2C_FAIL) {
PLTFM_MSG_ERR("[ERR]prev B%dP%d port H2C fail\n",
band, port);
return MACPROCERR;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_port_cfg *)
h2cb_put(h2cb, sizeof(struct fwcmd_port_cfg));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(type, FWCMD_H2C_PORT_CFG_TYPE) |
SET_WORD(para->mbssid_idx,
FWCMD_H2C_PORT_CFG_MBSSID_IDX) |
SET_WORD(port, FWCMD_H2C_PORT_CFG_PORT) |
(band ? FWCMD_H2C_PORT_CFG_BAND : 0));
hdr->dword1 =
cpu_to_le32(SET_WORD(para->val, FWCMD_H2C_PORT_CFG_VAL));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MPORT,
FWCMD_H2C_FUNC_PORT_CFG,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
pinfo->h2c_sm = MAC_AX_PORT_H2C_BUSY;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#endif
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 mbssid_idx = para->mbssid_idx;
u32 set_val = para->val;
u8 val8, w_val8;
u16 val16;
u16 w_val16 = MAC_AX_R16_DEAD;
u32 val32;
u32 w_val32 = MAC_AX_R32_DEAD;
struct mac_ax_pkt_drop_info info;
u8 mbid_max;
u32 ret = MACSUCCESS;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
band != MAC_AX_BAND_0) {
PLTFM_MSG_ERR("[ERR] invalid band idx %d\n", band);
return MACFUNCINPUT;
}
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR] invalid port idx %d\n", port);
return MACPORTCFGPORT;
}
if (mbssid_idx) {
ret = _get_max_mbid(adapter, &mbid_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] get_max_mbid %d\n", ret);
return MACPORTCFGPORT;
}
if (mbssid_idx > (u32)mbid_max) {
PLTFM_MSG_ERR("[ERR] invalid MBSSID number %d\n",
mbssid_idx);
return MACFUNCINPUT;
}
}
pinfo = &adapter->port_info[get_bp_idx(band, port)];
switch (type) {
case MAC_AX_PCFG_FUNC_SW:
if (set_val) {
PLTFM_MSG_ERR("[ERR] use port init to enable port\n");
return MACFUNCINPUT;
}
if (pinfo->stat == PORT_ST_DIS) {
PLTFM_MSG_WARN("[WARN]B%dP%d stat already disable\n",
band, port);
break;
}
ret = _patch_port_dis_flow(adapter, band, port, pinfo);
break;
case MAC_AX_PCFG_TX_SW:
val32 = MAC_REG_R32(cfg_regl[band][port]);
w_val32 = set_val ? val32 | b_bcntxen_l[port] :
val32 & ~b_bcntxen_l[port];
if (w_val32 != val32)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_TX_RPT:
val32 = MAC_REG_R32(cfg_regl[band][port]);
w_val32 = set_val ? val32 | b_txbcnrpt_l[port] :
val32 & ~b_txbcnrpt_l[port];
if (w_val32 != val32)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_RX_SW:
val32 = MAC_REG_R32(cfg_regl[band][port]);
w_val32 = set_val ? val32 | b_rxupd_l[port] :
val32 & ~b_rxupd_l[port];
if (w_val32 != val32)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_RX_RPT:
val32 = MAC_REG_R32(cfg_regl[band][port]);
w_val32 = set_val ? val32 | b_rxbcnrpt_l[port] :
val32 & ~b_rxbcnrpt_l[port];
if (w_val32 != val32)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_RX_SYNC:
val32 = MAC_REG_R32(cfg_regl[band][port]);
w_val32 = set_val ? val32 | b_rxtsfupd_l[port] :
val32 & ~b_rxtsfupd_l[port];
if (w_val32 != val32)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_BCN_PRCT:
val32 = MAC_REG_R32(cfg_regl[band][port]);
w_val32 = set_val ? val32 | b_phben_l[port] | b_brken_l[port] :
val32 & ~(b_phben_l[port] |
b_brken_l[port]);
if (w_val32 != val32)
MAC_REG_W32(cfg_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_TBTT_AGG:
if (set_val > B_AX_TBTT_AGG_NUM_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal tbtt agg %d\n", set_val);
return MACFUNCINPUT;
}
val16 = MAC_REG_R16(tbttagg_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTT_AGG_NUM_P0);
break;
case MAC_AX_PORT_1:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTT_AGG_NUM_P1);
break;
case MAC_AX_PORT_2:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTT_AGG_NUM_P2);
break;
case MAC_AX_PORT_3:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTT_AGG_NUM_P3);
break;
case MAC_AX_PORT_4:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTT_AGG_NUM_P4);
break;
}
if (w_val16 != val16 && w_val16 != MAC_AX_R16_DEAD)
MAC_REG_W16(tbttagg_regl[band][port], w_val16);
break;
case MAC_AX_PCFG_TBTT_SHIFT:
if (set_val > B_AX_TBTT_SHIFT_OFST_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal tbtt shift %d\n", set_val);
return MACFUNCINPUT;
}
val32 = MAC_REG_R32(tbttsht_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SHIFT_OFST_P0);
break;
case MAC_AX_PORT_1:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SHIFT_OFST_P1);
break;
case MAC_AX_PORT_2:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SHIFT_OFST_P2);
break;
case MAC_AX_PORT_3:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SHIFT_OFST_P3);
break;
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SHIFT_OFST_P4);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(tbttsht_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_RST_TSF:
val32 = MAC_REG_R32(cfg_regl[band][port]);
val32 = val32 | b_rsttsf_l[port];
MAC_REG_W32(cfg_regl[band][port], val32);
break;
case MAC_AX_PCFG_RST_TPR:
val32 = MAC_REG_R32(bcnpsr_regl[band][port]);
val32 |= b_rptvld_l[port];
MAC_REG_W32(bcnpsr_regl[band][port], val32);
break;
case MAC_AX_PCFG_HIQ_WIN:
if (set_val > B_AX_HGQWND_0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal hiq win %d\n", set_val);
return MACFUNCINPUT;
}
if (port == MAC_AX_PORT_0)
MAC_REG_W8(hiq_win_mbid_regl[band][mbssid_idx],
(u8)set_val);
else
MAC_REG_W8(hiq_win_port_regl[band][port],
(u8)set_val);
break;
case MAC_AX_PCFG_HIQ_DTIM:
if (set_val > B_AX_DTIM_NUM_P0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal dtim prd %d\n", set_val);
return MACFUNCINPUT;
}
val8 = MAC_REG_R8(dtim_switch[band]);
w_val8 = val8 | B_AX_UPD_TIMIE | B_AX_UPD_HGQMD;
if (w_val8 != val8)
MAC_REG_W8(dtim_switch[band], w_val8);
if (port == MAC_AX_PORT_0)
MAC_REG_W8(dtim_prd_mbid_regl[band][mbssid_idx],
(u8)set_val);
else
MAC_REG_W8(dtim_prd_port_regl[band][port],
(u8)set_val);
break;
case MAC_AX_PCFG_HIQ_NOLIMIT:
val32 = MAC_REG_R32(hiq_nolmt_regl[band]);
if (port == MAC_AX_PORT_0 && mbssid_idx)
w_val32 = set_val ?
val32 | b_hiq_nolmt_mbid_l[mbssid_idx - 1] :
val32 & ~b_hiq_nolmt_mbid_l[mbssid_idx - 1];
else
w_val32 = set_val ?
val32 | b_hiq_nolmt_port_l[port] :
val32 & ~b_hiq_nolmt_port_l[port];
if (w_val32 != val32)
MAC_REG_W32(hiq_nolmt_regl[band], w_val32);
break;
case MAC_AX_PCFG_BCN_SETUP_TIME:
ret = _bcn_setup_chk(adapter, band, port, ¶->val);
if (ret != MACSUCCESS) {
PLTFM_MSG_WARN("[WARN]bcn setup chk %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(phb_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SETUP_P0);
break;
case MAC_AX_PORT_1:
case MAC_AX_PORT_2:
case MAC_AX_PORT_3:
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_SETUP_P1);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(phb_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_BCN_HOLD_TIME:
ret = _bcn_hold_chk(adapter, band, port, ¶->val);
if (ret != MACSUCCESS) {
PLTFM_MSG_WARN("[WARN]bcn hold chk %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(phb_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_HOLD_P0);
break;
case MAC_AX_PORT_1:
case MAC_AX_PORT_2:
case MAC_AX_PORT_3:
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_TBTT_HOLD_P1);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(phb_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_MBSSID_EN:
if (port != MAC_AX_PORT_0 || !mbssid_idx) {
PLTFM_MSG_ERR("[ERR] mbssid en invalid for P%d MB%d\n",
port, mbssid_idx);
return MACFUNCINPUT;
}
val32 = MAC_REG_R32(mbid_ctrl_regl[band]);
if (mbssid_idx > GET_FIELD(val32, B_AX_P0MB_NUM)) {
PLTFM_MSG_ERR("[ERR] mbssid %d over %d\n", set_val,
GET_FIELD(val32, B_AX_P0MB_NUM));
return MACFUNCINPUT;
}
w_val32 = set_val ? val32 | b_mbid_en_l[mbssid_idx - 1] :
val32 & ~b_mbid_en_l[mbssid_idx - 1];
if (w_val32 != val32)
MAC_REG_W32(mbid_ctrl_regl[band], w_val32);
info.band = band;
info.port = port;
info.mbssid = (u8)mbssid_idx;
info.sel = MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID;
ret = adapter->ops->pkt_drop(adapter, &info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR] B%d P%d MB%d hiq drop %d\n",
band, port, mbssid_idx, ret);
return ret;
}
break;
case MAC_AX_PCFG_BCN_ERLY:
ret = _bcn_erly_chk(adapter, band, port, ¶->val);
if (ret != MACSUCCESS) {
PLTFM_MSG_WARN("[WARN]bcn erly chk %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(bcn_early_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P0);
break;
case MAC_AX_PORT_1:
w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P1);
break;
case MAC_AX_PORT_2:
w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P2);
break;
case MAC_AX_PORT_3:
w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P3);
break;
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val, B_AX_BCNERLY_P4);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(bcn_early_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_BCN_MASK_AREA:
ret = _bcn_mask_chk(adapter, band, port, ¶->val);
if (ret != MACSUCCESS) {
PLTFM_MSG_WARN("[WARN]bcn mask chk %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(mskarea_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_MSK_AREA_P0);
break;
case MAC_AX_PORT_1:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_MSK_AREA_P1);
break;
case MAC_AX_PORT_2:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_MSK_AREA_P2);
break;
case MAC_AX_PORT_3:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_MSK_AREA_P3);
break;
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_MSK_AREA_P4);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(mskarea_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_TBTT_ERLY:
ret = _tbtt_erly_chk(adapter, band, port, ¶->val);
if (ret != MACSUCCESS) {
PLTFM_MSG_WARN("[WARN]tbtt erly chk %d\n", ret);
return ret;
}
val16 = MAC_REG_R16(tbttery_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTTERLY_P0);
break;
case MAC_AX_PORT_1:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTTERLY_P1);
break;
case MAC_AX_PORT_2:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTTERLY_P2);
break;
case MAC_AX_PORT_3:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTTERLY_P3);
break;
case MAC_AX_PORT_4:
w_val16 = SET_CLR_WORD(val16, set_val,
B_AX_TBTTERLY_P4);
break;
}
if (w_val16 != val16 && w_val16 != MAC_AX_R16_DEAD)
MAC_REG_W16(tbttery_regl[band][port], w_val16);
break;
case MAC_AX_PCFG_BSS_CLR:
if (set_val > B_AX_BSS_COLOB_AX_PORT_0_MSK) {
PLTFM_MSG_ERR("[ERR] illegal bss color %d\n", set_val);
return MACFUNCINPUT;
}
val32 = MAC_REG_R32(bss_color_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BSS_COLOB_AX_PORT_0);
break;
case MAC_AX_PORT_1:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BSS_COLOB_AX_PORT_1);
break;
case MAC_AX_PORT_2:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BSS_COLOB_AX_PORT_2);
break;
case MAC_AX_PORT_3:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BSS_COLOB_AX_PORT_3);
break;
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BSS_COLOB_AX_PORT_4);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(bss_color_regl[band][port], w_val32);
break;
case MAC_AX_PCFG_BCN_DRP_ALL:
if (port == MAC_AX_PORT_0 && mbssid_idx) {
val32 = MAC_REG_R32(mbssid_drp_regl[band]);
w_val32 = set_val ?
val32 | b_mbid_drp_l[mbssid_idx - 1] :
val32 & ~b_mbid_drp_l[mbssid_idx - 1];
if (w_val32 != val32)
MAC_REG_W32(mbssid_drp_regl[band], w_val32);
} else {
val32 = MAC_REG_R32(bcndrp_regl[band]);
w_val32 = set_val ? val32 | b_drpall_l[port] :
val32 & ~b_drpall_l[port];
if (w_val32 != val32)
MAC_REG_W32(bcndrp_regl[band], w_val32);
}
break;
case MAC_AX_PCFG_MBSSID_NUM:
if (port != MAC_AX_PORT_0 || pinfo->stat != PORT_ST_AP) {
PLTFM_MSG_ERR("[ERR]port is not 0 or is not AP\n");
return MACPORTCFGPORT;
}
_set_max_mbid_num(adapter, para);
break;
case MAC_AX_PCFG_BCN_INTV:
if (set_val > B_AX_BCN_SPACE_P0_MSK || !set_val) {
PLTFM_MSG_ERR("[ERR] illegal bcn itvl %d\n", set_val);
return MACFUNCINPUT;
}
val32 = MAC_REG_R32(bcnspc_regl[band][port]);
switch (port) {
case MAC_AX_PORT_0:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_SPACE_P0);
break;
case MAC_AX_PORT_1:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_SPACE_P1);
break;
case MAC_AX_PORT_2:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_SPACE_P2);
break;
case MAC_AX_PORT_3:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_SPACE_P3);
break;
case MAC_AX_PORT_4:
w_val32 = SET_CLR_WORD(val32, set_val,
B_AX_BCN_SPACE_P4);
break;
}
if (w_val32 != val32 && val32 != MAC_AX_R32_DEAD)
MAC_REG_W32(bcnspc_regl[band][port], w_val32);
break;
default:
PLTFM_MSG_ERR("[ERR] invalid cfg type %d\n", type);
return MACPORTCFGTYPE;
}
return ret;
}
u32 mac_port_init(struct mac_ax_adapter *adapter,
struct mac_ax_port_init_para *para)
{
struct mac_ax_port_info *pinfo;
u8 band = para->band_idx;
u8 port = para->port_idx;
u8 net_type = para->net_type;
#if 0 // MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_port_init *hdr;
u32 ret = MACSUCCESS;
u32 cnt;
if (band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("[ERR]invalid band %d\n", band);
return MACFUNCINPUT;
}
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port %d\n", port);
return MACFUNCINPUT;
}
pinfo = &adapter->port_info[get_bp_idx(band, port)];
if (pinfo->h2c_sm == MAC_AX_PORT_H2C_FAIL) {
PLTFM_MSG_ERR("[ERR]prev B%dP%d port H2C fail\n",
band, port);
return MACPROCERR;
}
cnt = PORT_H2C_DLY_CNT;
while (pinfo->h2c_sm == MAC_AX_PORT_H2C_BUSY) {
cnt--;
if (!cnt) {
PLTFM_MSG_ERR("[ERR]B%dP%d port H2C busy\n",
band, port);
return MACPROCBUSY;
}
PLTFM_DELAY_US(PORT_H2C_DLY_US);
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_port_init *)
h2cb_put(h2cb, sizeof(struct fwcmd_port_init));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(para->bss_color,
FWCMD_H2C_PORT_INIT_BSS_COLOR) |
SET_WORD(para->mbid_num,
FWCMD_H2C_PORT_INIT_MBSSID_NUM) |
SET_WORD(para->dtim_period,
FWCMD_H2C_PORT_INIT_DTIM_PRD) |
SET_WORD(net_type,
FWCMD_H2C_PORT_INIT_NET_TYPE) |
SET_WORD(port, FWCMD_H2C_PORT_INIT_PORT) |
(band ? FWCMD_H2C_PORT_INIT_BAND : 0));
hdr->dword1 =
cpu_to_le32(SET_WORD(para->hiq_win,
FWCMD_H2C_PORT_INIT_HIQ_WND) |
SET_WORD(para->bcn_interval,
FWCMD_H2C_PORT_INIT_BCN_ITVL));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_MPORT,
FWCMD_H2C_FUNC_PORT_INIT,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
pinfo->h2c_sm = MAC_AX_PORT_H2C_BUSY;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
#endif
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_port_cfg_para cfg_para;
struct mac_ax_pkt_drop_info info;
u8 mbid_num;
u8 mbid_max;
u8 i = 0;
u32 ret = MACSUCCESS;
u32 val32;
u32 bcn_erly = BCN_ERLY_DEF;
u32 hold_time = BCN_HOLD_DEF;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
band != MAC_AX_BAND_0) {
PLTFM_MSG_ERR("[ERR]invalid band idx %d\n", band);
return MACFUNCINPUT;
}
if (port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port idx %d\n", port);
return MACPORTCFGPORT;
}
mbid_num = net_type == MAC_AX_NET_TYPE_AP && port == MAC_AX_BAND_0 ?
para->mbid_num : 0;
ret = _get_max_mbid(adapter, &mbid_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get_max_mbid %d\n", ret);
return MACPORTCFGPORT;
}
if (mbid_num > mbid_max) {
PLTFM_MSG_ERR("[ERR]invalid MBSSID number %d\n", mbid_num);
return MACFUNCINPUT;
}
if (mbid_num && !(mbid_num % 2))
mbid_num++;
pinfo = &adapter->port_info[get_bp_idx(band, port)];
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]chk mac en %d\n", ret);
return ret;
}
cfg_para.band = band;
cfg_para.port = port;
cfg_para.mbssid_idx = 0;
if (pinfo->stat != PORT_ST_DIS) {
cfg_para.val = 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_FUNC_SW, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg func sw 0 fail %d\n",
band, port, ret);
return ret;
}
}
cfg_para.val = 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_TX_RPT, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg tx rpt fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_RX_RPT, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg rx rpt fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = net_type;
ret = _port_cfg(adapter, MAC_AX_PCFG_NET_TYPE, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg net type fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = net_type == MAC_AX_NET_TYPE_NO_LINK ? 0 : 1;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_PRCT, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn prct fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = (net_type == MAC_AX_NET_TYPE_INFRA ||
net_type == MAC_AX_NET_TYPE_ADHOC) ? 1 : 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_RX_SW, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg rx sw fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = (net_type == MAC_AX_NET_TYPE_INFRA ||
net_type == MAC_AX_NET_TYPE_ADHOC) ? 1 : 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_RX_SYNC, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg rx sync fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = (net_type == MAC_AX_NET_TYPE_AP ||
net_type == MAC_AX_NET_TYPE_ADHOC) ? 1 : 0;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_TX_SW, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg tx sw fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = (u32)para->bcn_interval;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_INTV, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn intv fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = (u32)para->bss_color;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BSS_CLR, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg bss_color fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = TBTT_AGG_DEF;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_AGG, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg tbtt agg fail %d\n",
band, port, ret);
return ret;
}
for (i = 0; i <= mbid_num; i++) {
cfg_para.mbssid_idx = mbid_idx_l[i];
cfg_para.val = para->hiq_win;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_HIQ_WIN, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d mbid%d cfg hiq win %d\n",
band, port, cfg_para.mbssid_idx, ret);
return ret;
}
cfg_para.val = (u32)para->dtim_period;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_HIQ_DTIM, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d mbid%d cfg hiq dtim %d\n",
band, port, cfg_para.mbssid_idx, ret);
return ret;
}
info.band = band;
info.port = port;
info.mbssid = (u8)mbid_idx_l[i];
info.sel = info.mbssid ?
MAC_AX_PKT_DROP_SEL_REL_HIQ_MBSSID :
MAC_AX_PKT_DROP_SEL_REL_HIQ_PORT;
ret = adapter->ops->pkt_drop(adapter, &info);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d mbid%d hiq drop %d\n",
band, port, info.mbssid, ret);
return ret;
}
}
cfg_para.val = hold_time;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME, &cfg_para);
if (ret == MACSETVALERR)
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_HOLD_TIME,
&cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg hold time fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = BCN_MASK_DEF;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA, &cfg_para);
if (ret == MACSETVALERR)
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_MASK_AREA,
&cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg mask area fail %d\n",
band, port, ret);
return ret;
}
val32 = MAC_REG_R32(cfg_regl[band][port]) | b_en_l[port];
MAC_REG_W32(cfg_regl[band][port], val32);
switch (net_type) {
case MAC_AX_NET_TYPE_NO_LINK:
pinfo->stat = PORT_ST_NOLINK;
break;
case MAC_AX_NET_TYPE_ADHOC:
pinfo->stat = PORT_ST_ADHOC;
break;
case MAC_AX_NET_TYPE_INFRA:
pinfo->stat = PORT_ST_INFRA;
break;
case MAC_AX_NET_TYPE_AP:
pinfo->stat = PORT_ST_AP;
break;
}
ret = dly_port_us(adapter, band, port, BCN_ERLY_SET_DLY);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d dly %d us fail %d\n",
band, port, BCN_ERLY_SET_DLY, ret);
return ret;
}
cfg_para.val = bcn_erly;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret == MACSETVALERR)
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg bcn early fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = BCN_SETUP_DEF;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME, &cfg_para);
if (ret == MACSETVALERR)
ret = mac_port_cfg(adapter, MAC_AX_PCFG_BCN_SETUP_TIME,
&cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg setup time fail %d\n",
band, port, ret);
return ret;
}
cfg_para.val = TBTT_ERLY_DEF;
ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para);
if (ret == MACSETVALERR)
ret = mac_port_cfg(adapter, MAC_AX_PCFG_TBTT_ERLY, &cfg_para);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d cfg tbtt early fail %d\n",
band, port, ret);
return ret;
}
if (port == MAC_AX_PORT_0) {
ret = port0_mbid_set(adapter, band, mbid_num, mbid_max);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d mbid set fail %d\n",
band, port, ret);
return ret;
}
ret = port0_subspc_set(adapter, band, mbid_num,
&bcn_erly, &hold_time);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]B%dP%d subspc set fail %d\n",
band, port, ret);
return ret;
}
}
return ret;
}
u32 mac_tsf_sync(struct mac_ax_adapter *adapter, u8 from_port, u8 to_port,
s32 sync_offset, enum mac_ax_tsf_sync_act action)
{
u32 abs_sync_offset, val32, ret = MACSUCCESS;
u16 to_port_reg;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (from_port > MAX_TSF_SOURCE_PORT || to_port > MAX_TSF_TARGET_PORT ||
from_port == to_port) {
PLTFM_MSG_ERR("[ERR] Invalid tsf_sync port.\n");
return MACFUNCINPUT;
}
abs_sync_offset = sync_offset > 0 ? sync_offset : -sync_offset;
if (abs_sync_offset > MAX_TSF_SYNC_OFFSET) {
PLTFM_MSG_ERR("[ERR] Invalid tsf_sync offset.\n");
return MACFUNCINPUT;
}
if (sync_offset < 0)
abs_sync_offset |= BIT18;
switch (to_port) {
case MAC_AX_PORT_0:
to_port_reg = R_AX_PORT_0_TSF_SYNC;
break;
case MAC_AX_PORT_1:
to_port_reg = R_AX_PORT_1_TSF_SYNC;
break;
case MAC_AX_PORT_2:
to_port_reg = R_AX_PORT_2_TSF_SYNC;
break;
case MAC_AX_PORT_3:
to_port_reg = R_AX_PORT_3_TSF_SYNC;
break;
case MAC_AX_PORT_4:
to_port_reg = R_AX_PORT_4_TSF_SYNC;
break;
default:
PLTFM_MSG_ERR("[ERR] Invalid tsf_sync input.\n");
return MACFUNCINPUT;
}
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD(to_port_reg,
B_AX_P0_TSFTR_SYNC_OFFSET_MSK <<
B_AX_P0_TSFTR_SYNC_OFFSET_SH,
abs_sync_offset, 0);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, to_port_reg, ret);
return ret;
}
ret = MAC_REG_W_OFLD(to_port_reg,
B_AX_P0_SYNC_PORT_SRC_SEL_MSK <<
B_AX_P0_SYNC_PORT_SRC_SEL_SH,
from_port, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, to_port_reg, ret);
return ret;
}
switch (action) {
case MAC_AX_TSF_SYNC_NOW_ONCE:
ret = MAC_REG_W_OFLD(to_port_reg, B_AX_P0_SYNC_NOW_P,
1, 1);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, to_port_reg, ret);
return ret;
}
ret = MAC_REG_P_OFLD(to_port_reg, B_AX_P0_SYNC_NOW_P,
0, 1);
break;
case MAC_AX_TSF_EN_SYNC_AUTO:
ret = MAC_REG_W_OFLD(to_port_reg, B_AX_P0_AUTO_SYNC,
1, 1);
break;
case MAC_AX_TSF_DIS_SYNC_AUTO:
ret = MAC_REG_W_OFLD(to_port_reg, B_AX_P0_AUTO_SYNC,
0, 1);
break;
default:
PLTFM_MSG_ERR("[ERR] Invalid tsf_sync input.\n");
return MACFUNCINPUT;
}
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("%s: write offload fail;"
"offset: %u, ret: %u\n",
__func__, to_port_reg, ret);
return ret;
}
return ret;
}
#endif
val32 = MAC_REG_R32(to_port_reg);
val32 = SET_CLR_WORD(val32, abs_sync_offset, B_AX_P0_TSFTR_SYNC_OFFSET);
val32 = SET_CLR_WORD(val32, from_port, B_AX_P0_SYNC_PORT_SRC_SEL);
MAC_REG_W32(to_port_reg, val32);
switch (action) {
case MAC_AX_TSF_SYNC_NOW_ONCE:
MAC_REG_W32(to_port_reg, val32 | B_AX_P0_SYNC_NOW_P);
break;
case MAC_AX_TSF_EN_SYNC_AUTO:
MAC_REG_W32(to_port_reg, val32 | B_AX_P0_AUTO_SYNC);
break;
case MAC_AX_TSF_DIS_SYNC_AUTO:
MAC_REG_W32(to_port_reg, val32 & ~B_AX_P0_AUTO_SYNC);
break;
default:
PLTFM_MSG_ERR("[ERR] Invalid tsf_sync input.\n");
return MACFUNCINPUT;
}
return ret;
}
u32 mac_parse_bcn_stats_c2h(struct mac_ax_adapter *adapter,
u8 *content, struct mac_ax_bcn_cnt *val)
{
u32 *pdata, data0, data1;
u8 port_mbssid;
pdata = (u32 *)content;
data0 = le32_to_cpu(*pdata);
data1 = le32_to_cpu(*(pdata + 1));
port_mbssid = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_PORT_MBSSID_IDX);
if (port_mbssid < MAC_AX_P0_MBID_LAST) {
val->port = 0;
val->mbssid = port_mbssid;
} else {
val->port = port_mbssid - MAC_AX_P0_MBID_LAST + 1;
val->mbssid = 0;
}
val->band = data0 & FWCMD_C2H_BCN_CNT_BAND_IDX ? 1 : 0;
val->cca_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_CCA_FAIL_CNT);
val->edcca_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_EDCCA_FAIL_CNT);
val->nav_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_NAV_FAIL_CNT);
val->txon_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_TXON_FAIL_CNT);
val->mac_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_MAC_FAIL_CNT);
val->others_cnt = GET_FIELD(data0, FWCMD_C2H_BCN_CNT_OTHERS_FAIL_CNT);
val->lock_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_LOCK_FAIL_CNT);
val->cmp_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_CMP_FAIL_CNT);
val->invalid_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_INVALID_FAIL_CNT);
val->srchend_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_SRCHEND_FAIL_CNT);
val->ok_cnt = GET_FIELD(data1, FWCMD_C2H_BCN_CNT_OK_CNT);
return MACSUCCESS;
}
u32 mac_tsf32_togl_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_t32_togl_info *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_tsf32_togl *hdr;
u32 ret = MACSUCCESS;
if (info->band >= MAC_AX_BAND_NUM) {
PLTFM_MSG_ERR("[ERR]invalid band %d\n", info->band);
return MACFUNCINPUT;
}
if (info->port >= MAC_AX_PORT_NUM) {
PLTFM_MSG_ERR("[ERR]invalid port %d\n", info->port);
return MACFUNCINPUT;
}
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_tsf32_togl *)
h2cb_put(h2cb, sizeof(struct fwcmd_tsf32_togl));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(info->port, FWCMD_H2C_TSF32_TOGL_PORT) |
SET_WORD(info->early, FWCMD_H2C_TSF32_TOGL_EARLY) |
(info->band ? FWCMD_H2C_TSF32_TOGL_BAND : 0) |
(info->en ? FWCMD_H2C_TSF32_TOGL_EN : 0));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FW_OFLD,
FWCMD_H2C_FUNC_TSF32_TOGL,
0,
0);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_get_t32_togl_rpt(struct mac_ax_adapter *adapter,
struct mac_ax_t32_togl_rpt *ret_rpt)
{
struct mac_ax_t32_togl_rpt *rpt;
u8 b_idx, p_idx;
for (b_idx = MAC_AX_BAND_0; b_idx < MAC_AX_BAND_NUM; b_idx++) {
for (p_idx = MAC_AX_PORT_0; p_idx < MAC_AX_PORT_NUM; p_idx++) {
rpt = &adapter->t32_togl_rpt[get_bp_idx(b_idx, p_idx)];
if (!rpt->valid)
continue;
PLTFM_MEMCPY(ret_rpt, rpt,
sizeof(struct mac_ax_t32_togl_rpt));
rpt->valid = 0;
return MACSUCCESS;
}
}
PLTFM_MSG_WARN("[WARN]no tsf32 togl rpt find\n");
return MACNOITEM;
}
u32 mport_info_init(struct mac_ax_adapter *adapter)
{
u8 b_idx, p_idx;
u32 idx;
adapter->t32_togl_rpt =
(struct mac_ax_t32_togl_rpt *)PLTFM_MALLOC(t32_togl_rpt_size);
adapter->port_info =
(struct mac_ax_port_info *)PLTFM_MALLOC(port_info_size);
for (b_idx = MAC_AX_BAND_0; b_idx < MAC_AX_BAND_NUM; b_idx++) {
for (p_idx = MAC_AX_PORT_0; p_idx < MAC_AX_PORT_NUM; p_idx++) {
idx = get_bp_idx(b_idx, p_idx);
PLTFM_MEMSET(&adapter->t32_togl_rpt[idx], 0,
sizeof(struct mac_ax_t32_togl_rpt));
PLTFM_MEMSET(&adapter->port_info[idx], 0,
sizeof(struct mac_ax_port_info));
}
}
return MACSUCCESS;
}
u32 mport_info_exit(struct mac_ax_adapter *adapter)
{
PLTFM_FREE(adapter->t32_togl_rpt, t32_togl_rpt_size);
PLTFM_FREE(adapter->port_info, port_info_size);
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mport.c
|
C
|
agpl-3.0
| 73,312
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_MPORT_H_
#define _MAC_AX_MPORT_H_
#include "../type.h"
/*--------------------Define -------------------------------------------*/
#define BCN_ERLY_DEF 160
#define BCN_SETUP_DEF 4
#define BCN_HOLD_DEF 400
#define BCN_MASK_DEF 0
#define TBTT_ERLY_DEF 5
#define TBTT_AGG_DEF 1
#define BCN_SET_TO_US 32
#define TU_TO_BCN_SET (1024 / BCN_SET_TO_US)
#define BCN_ERLY_SET_DLY 10
#define PTCL_DBG_BCNQ_NUM0 8
#define PTCL_DBG_BCNQ_NUM1 9
#define PTCL_DBG_DLY_US 100
#define TU_UNIT 1024
#define MS_UNIT 1000
#define PORT_DLY_TU_CNT_LMT 2
#define PORT_DLY_US_CNT_LMT 2
#define MAX_BCN_ITVL 0x639C
#define CHK_BCNQ_CNT 200
#define BCNQ_EMP_CONT_CNT 2
#define LBK_PLCP_DLY_DEF 0x28
#define LBK_PLCP_DLY_FPGA 0x46
#define BCN_FAST_DRP_TBTT 1
/* 50% hold time , 30% beacon early */
#define BCN_ERLY_RATIO 3
#define BCN_HOLD_RATIO 5
#define BCN_ITVL_RATIO 10
#define PORT_H2C_DLY_US 10
#define PORT_H2C_DLY_CNT 20000
/*--------------------Define MACRO--------------------------------------*/
/*--------------------Define Enum---------------------------------------*/
enum port_stat {
PORT_ST_DIS = 0,
PORT_ST_NOLINK,
PORT_ST_ADHOC,
PORT_ST_INFRA,
PORT_ST_AP,
};
enum C2H_MPORT_RET_CODE {
C2H_MPORT_RET_SUCCESS = 0,
C2H_MPORT_RET_PENDING,
C2H_MPORT_RET_BAND_ERR,
C2H_MPORT_RET_PORT_ERR,
C2H_MPORT_RET_MBID_ERR,
C2H_MPORT_RET_NO_CONTENT,
C2H_MPORT_RET_TSF32TOG_C2H_FAIL,
C2H_MPORT_RET_CFG_TYPE_ERR,
C2H_MPORT_RET_SET_CFG_ILEGAL_EN,
C2H_MPORT_RET_SET_CFG_ARDY_DIS,
C2H_MPORT_RET_INPUT_ILEGAL,
C2H_MPORT_RET_CHK_BELW_LMT,
C2H_MPORT_RET_CHK_OVER_LMT,
C2H_MPORT_RET_SUB_SPC_ERR,
C2H_MPORT_RET_POLL_TO,
C2H_MPORT_RET_TSF_NOT_RUN,
C2H_MPORT_RET_MALLOC_FAIL,
C2H_MPORT_RET_DEINIT_FAIL,
C2H_MPORT_RET_PKT_DROP,
C2H_MPORT_RET_ADD_PSTIMER,
C2H_MPORT_RET_CHK_BCNQ_TO,
C2H_MPORT_RET_CHK_BCNQ_FAIL,
C2H_MPORT_RET_SEND_C2H_INIT,
C2H_MPORT_RET_SEND_C2H_CFG,
};
/*--------------------Define Struct-------------------------------------*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief dly_port_tu
*
* @param *adapter
* @param band
* @param port
* @param dly_tu
* @return Please Place Description here.
* @retval u32
*/
u32 dly_port_tu(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_tu);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief dly_port_us
*
* @param *adapter
* @param band
* @param port
* @param dly_us
* @return Please Place Description here.
* @retval u32
*/
u32 dly_port_us(struct mac_ax_adapter *adapter, u8 band, u8 port, u32 dly_us);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief rst_port_info
*
* @param *adapter
* @param band
* @return Please Place Description here.
* @retval u32
*/
u32 rst_port_info(struct mac_ax_adapter *adapter, u8 band);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief mac_port_cfg
*
* @param *adapter
* @param type
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_port_cfg(struct mac_ax_adapter *adapter,
enum mac_ax_port_cfg_type type,
struct mac_ax_port_cfg_para *para);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief mac_port_init
*
* @param *adapter
* @param *para
* @return Please Place Description here.
* @retval u32
*/
u32 mac_port_init(struct mac_ax_adapter *adapter,
struct mac_ax_port_init_para *para);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief mac_tsf_sync
*
* @param *adapter
* @param from_port
* @param to_port
* @param sync_offset
* @param action
* @return Please Place Description here.
* @retval u32
*/
u32 mac_tsf_sync(struct mac_ax_adapter *adapter, u8 from_port, u8 to_port,
s32 sync_offset, enum mac_ax_tsf_sync_act action);
/**
* @}
* @}
*/
/**
* @addtogroup Basic_TRX
* @{
* @addtogroup MultiPort
* @{
*/
/**
* @brief mac_parse_bcn_stats_c2h
*
* @param *adapter
* @param *content
* @param *val
* @return Please Place Description here.
* @retval u32
*/
u32 mac_parse_bcn_stats_c2h(struct mac_ax_adapter *adapter,
u8 *content, struct mac_ax_bcn_cnt *val);
/**
* @}
* @}
*/
u32 mac_tsf32_togl_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_t32_togl_info *info);
u32 mac_get_t32_togl_rpt(struct mac_ax_adapter *adapter,
struct mac_ax_t32_togl_rpt *ret_rpt);
u32 get_bp_idx(u8 band, u8 port);
u32 mport_info_init(struct mac_ax_adapter *adapter);
u32 mport_info_exit(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/mport.h
|
C
|
agpl-3.0
| 5,361
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "p2p.h"
static u32 p2p_info_size = sizeof(struct mac_ax_p2p_info) * P2P_MAX_NUM;
static u32 _get_valid_p2pid(struct mac_ax_adapter *adapter, u8 macid, u8 *p2pid)
{
struct mac_ax_p2p_info *info = adapter->p2p_info;
u8 idx;
for (idx = 0; idx < P2P_MAX_NUM; idx++) {
if (info[idx].run && info[idx].macid == macid) {
PLTFM_MSG_ERR("[ERR]macid %d has running p2pid %d\n",
macid, idx);
*p2pid = P2PID_INVALID;
return MACSUCCESS;
}
}
for (idx = 0; idx < P2P_MAX_NUM; idx++) {
if (!info[idx].run && !info[idx].wait_dack) {
*p2pid = idx;
return MACSUCCESS;
}
}
PLTFM_MSG_ERR("[ERR]no valid p2p\n");
*p2pid = P2PID_INVALID;
return MACHWNOSUP;
}
static u32 _get_macid_p2pid(struct mac_ax_adapter *adapter, u8 macid, u8 *p2pid)
{
struct mac_ax_p2p_info *info = adapter->p2p_info;
u8 idx;
for (idx = 0; idx < P2P_MAX_NUM; idx++) {
if (info[idx].run && info[idx].macid == macid) {
*p2pid = idx;
return MACSUCCESS;
}
}
PLTFM_MSG_ERR("[ERR]no valid p2pid for macid %d\n", macid);
*p2pid = P2PID_INVALID;
return MACFUNCINPUT;
}
u32 get_wait_dack_p2pid(struct mac_ax_adapter *adapter, u8 *p2pid)
{
struct mac_ax_p2p_info *info = adapter->p2p_info;
u8 idx;
u8 hit = 0;
for (idx = 0; idx < P2P_MAX_NUM; idx++) {
if (info[idx].wait_dack && !hit) {
*p2pid = idx;
hit = 1;
} else if (info[idx].wait_dack) {
PLTFM_MSG_ERR("[ERR]multiple wait dack p2p\n");
return MACPROCERR;
}
}
if (!hit)
*p2pid = P2PID_INVALID;
return MACSUCCESS;
}
u32 p2p_info_init(struct mac_ax_adapter *adapter)
{
u32 i;
adapter->p2p_info =
(struct mac_ax_p2p_info *)PLTFM_MALLOC(p2p_info_size);
for (i = 0; i < P2P_MAX_NUM; i++)
PLTFM_MEMSET(&adapter->p2p_info[i], 0,
sizeof(struct mac_ax_p2p_info));
return MACSUCCESS;
}
u32 p2p_info_exit(struct mac_ax_adapter *adapter)
{
PLTFM_FREE(adapter->p2p_info, p2p_info_size);
return MACSUCCESS;
}
u32 rst_p2p_info(struct mac_ax_adapter *adapter)
{
PLTFM_MEMSET(adapter->p2p_info, 0, p2p_info_size);
return MACSUCCESS;
}
u32 mac_p2p_act_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_p2p_act_info *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_p2p_act *hdr;
u32 ret = MACSUCCESS;
u8 p2pid;
if (info->noaid >= NOA_MAX_NUM) {
PLTFM_MSG_ERR("[ERR]invalid noaid %d\n", info->noaid);
return MACFUNCINPUT;
}
if (info->act == P2P_ACT_INIT) {
ret = _get_valid_p2pid(adapter, info->macid, &p2pid);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get valid p2pid %d\n", ret);
return MACHWNOSUP;
}
if (p2pid == P2PID_INVALID) {
PLTFM_MSG_ERR("[ERR]get invalid p2pid\n");
return MACNOITEM;
}
} else {
ret = _get_macid_p2pid(adapter, info->macid, &p2pid);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get macid %d p2pid %d\n",
info->macid, ret);
return MACFUNCINPUT;
}
if (p2pid == P2PID_INVALID) {
PLTFM_MSG_ERR("[ERR]get macid p2pid shall ret err\n");
return MACCMP;
}
}
if (adapter->sm.p2p_stat == MAC_AX_P2P_ACT_BUSY) {
PLTFM_MSG_ERR("[ERR] p2p act h2c stat busy\n");
return MACPROCERR;
}
adapter->sm.p2p_stat = MAC_AX_P2P_ACT_BUSY;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
hdr = (struct fwcmd_p2p_act *)
h2cb_put(h2cb, sizeof(struct fwcmd_p2p_act));
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(info->macid, FWCMD_H2C_P2P_ACT_MACID) |
SET_WORD(p2pid, FWCMD_H2C_P2P_ACT_P2PID) |
SET_WORD(info->noaid, FWCMD_H2C_P2P_ACT_NOAID) |
SET_WORD(info->act, FWCMD_H2C_P2P_ACT_ACT) |
(info->type ? FWCMD_H2C_P2P_ACT_TYPE : 0) |
(info->all_slep ? FWCMD_H2C_P2P_ACT_ALL_SLEP : 0));
hdr->dword1 =
cpu_to_le32(SET_WORD(info->srt, FWCMD_H2C_P2P_ACT_SRT));
hdr->dword2 =
cpu_to_le32(SET_WORD(info->itvl, FWCMD_H2C_P2P_ACT_ITVL));
hdr->dword3 =
cpu_to_le32(SET_WORD(info->dur, FWCMD_H2C_P2P_ACT_DUR));
hdr->dword4 =
cpu_to_le32(SET_WORD(info->cnt, FWCMD_H2C_P2P_ACT_CNT) |
SET_WORD(info->ctw, FWCMD_H2C_P2P_ACT_CTW));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_PS,
FWCMD_H2C_FUNC_P2P_ACT,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
if (info->act == P2P_ACT_INIT)
adapter->p2p_info[p2pid].macid = info->macid;
if (info->act == P2P_ACT_INIT || info->act == P2P_ACT_TERM)
adapter->p2p_info[p2pid].wait_dack = 1;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_p2p_macid_ctrl_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_p2p_macid_info *info)
{
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_p2p_macid_ctrl *hdr;
u32 ret = MACSUCCESS;
u32 idx, bmap_ext_size, pldsize, bmap_srt_sh, bmap_last;
u32 bmap_idx_srt, bmap_idx_end, bmap_idx_diff;
u8 *curr_buf;
u8 p2pid;
if (info->ctrl_type >= P2P_MACID_CTRL_MAX) {
PLTFM_MSG_ERR("[ERR]p2p macid ctrl invalid ctrl type %d\n",
info->ctrl_type);
return MACFUNCINPUT;
}
ret = _get_macid_p2pid(adapter, info->main_macid, &p2pid);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]get macid %d p2pid %d\n",
info->main_macid, ret);
return MACFUNCINPUT;
}
if (p2pid == P2PID_INVALID) {
PLTFM_MSG_ERR("[ERR]get macid p2pid shall ret err\n");
return MACNOITEM;
}
bmap_idx_srt = 0;
for (idx = 0; idx < info->bmap_len; idx++) {
if (*(info->bitmap + idx))
break;
if (idx && !(idx & MACID_BMAP_BYTE_MSK))
bmap_idx_srt++;
}
bmap_idx_end = info->bmap_len >> MACID_BMAP_BYTE_SH;
bmap_last = info->bmap_len ? (info->bmap_len - 1) : 0;
for (idx = bmap_last; idx > 0; idx--) {
if (*(info->bitmap + idx))
break;
if (!(idx & MACID_BMAP_BYTE_MSK))
bmap_idx_end--;
}
if (bmap_idx_srt > bmap_idx_end) {
PLTFM_MSG_ERR("[ERR] p2p macid ctrl bitmap comp err\n");
return MACCMP;
}
bmap_idx_diff = bmap_idx_end - bmap_idx_srt;
bmap_ext_size = bmap_idx_diff << MACID_BMAP_BYTE_SH;
if (adapter->sm.p2p_stat == MAC_AX_P2P_ACT_BUSY) {
PLTFM_MSG_ERR("[ERR] p2p macid ctrl h2c stat busy\n");
return MACPROCERR;
}
adapter->sm.p2p_stat = MAC_AX_P2P_ACT_BUSY;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
pldsize = sizeof(struct fwcmd_p2p_macid_ctrl) + bmap_ext_size;
hdr = (struct fwcmd_p2p_macid_ctrl *)h2cb_put(h2cb, pldsize);
if (!hdr) {
ret = MACNOBUF;
goto fail;
}
hdr->dword0 =
cpu_to_le32(SET_WORD(p2pid, FWCMD_H2C_P2P_MACID_CTRL_P2PID) |
SET_WORD(info->ctrl_type,
FWCMD_H2C_P2P_MACID_CTRL_CTRL_TYPE) |
SET_WORD((bmap_idx_srt << MACID_BMAP_BIT_SH),
FWCMD_H2C_P2P_MACID_CTRL_MACID_SRT) |
SET_WORD((bmap_idx_diff + 1),
FWCMD_H2C_P2P_MACID_CTRL_BMAP_LEN));
for (idx = 0; idx <= ((bmap_idx_diff + 1) << MACID_BMAP_BYTE_SH); idx++) {
bmap_srt_sh = (bmap_idx_srt << MACID_BMAP_BYTE_SH) + idx;
curr_buf = (u8 *)(&hdr->dword1) + idx;
if (bmap_srt_sh < info->bmap_len)
*curr_buf = *(info->bitmap + bmap_srt_sh);
else
*curr_buf = 0;
}
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_PS,
FWCMD_H2C_FUNC_P2P_MACID_CTRL,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
h2c_end_flow(adapter);
adapter->p2p_info[p2pid].wait_dack = 1;
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
u32 mac_get_p2p_stat(struct mac_ax_adapter *adapter)
{
switch (adapter->sm.p2p_stat) {
case MAC_AX_P2P_ACT_IDLE:
return MACSUCCESS;
case MAC_AX_P2P_ACT_BUSY:
return MACPROCBUSY;
case MAC_AX_P2P_ACT_FAIL:
default:
return MACP2PSTFAIL;
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/p2p.c
|
C
|
agpl-3.0
| 8,821
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_P2P_H_
#define _MAC_AX_P2P_H_
#include "../type.h"
#include "fwcmd.h"
/*--------------------Define -------------------------------------------*/
#define P2P_MAX_NUM 2
#define NOA_MAX_NUM 2
#define P2PID_INVALID 0xFF
#define MACID_BMAP_BYTE_SH 2 /* DWORD to Byte */
#define MACID_BMAP_BYTE_MSK 0x3
#define MACID_BMAP_BIT_SH 5 /* DWORD to bit */
/*--------------------Define MACRO--------------------------------------*/
/*--------------------Define Enum---------------------------------------*/
enum P2P_ACT {
P2P_ACT_INIT = 0,
P2P_ACT_UPD,
P2P_ACT_RM,
P2P_ACT_TERM
};
enum P2P_MACID_CTRL_TYPE {
P2P_MACID_CTRL_JOIN = 0,
P2P_MACID_CTRL_CLR,
P2P_MACID_CTRL_CLR_ALL,
P2P_MACID_CTRL_MAX
};
/*--------------------Define Struct-------------------------------------*/
/**
* @brief get_wait_dack_p2pid
*
* @param *adapter
* @param *p2pid
* @return Please Place Description here.
* @retval u32
*/
u32 get_wait_dack_p2pid(struct mac_ax_adapter *adapter, u8 *p2pid);
/**
* @brief p2p_info_init
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 p2p_info_init(struct mac_ax_adapter *adapter);
/**
* @brief p2p_info_exit
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 p2p_info_exit(struct mac_ax_adapter *adapter);
/**
* @brief rst_p2p_info
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 rst_p2p_info(struct mac_ax_adapter *adapter);
/**
* @brief mac_p2p_act_h2c
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_p2p_act_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_p2p_act_info *info);
/**
* @brief mac_p2p_macid_ctrl_h2c
*
* @param *adapter
* @param *info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_p2p_macid_ctrl_h2c(struct mac_ax_adapter *adapter,
struct mac_ax_p2p_macid_info *info);
/**
* @brief mac_get_p2p_stat
*
* @param *adapter
* @return Please Place Description here.
* @retval u32
*/
u32 mac_get_p2p_stat(struct mac_ax_adapter *adapter);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/p2p.h
|
C
|
agpl-3.0
| 2,805
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "phy_misc.h"
u32 mac_fast_ch_sw(struct mac_ax_adapter *adapter, struct mac_ax_fast_ch_sw_param *fast_ch_sw_param)
{
u8 *buf;
u32 ret = MACSUCCESS;
struct fwcmd_fcs *pkt;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cbuf;
#else
struct h2c_buf *h2cbuf;
#endif
h2cbuf = h2cb_alloc(adapter, H2CB_CLASS_DATA);
if (!h2cbuf)
return MACNPTR;
buf = h2cb_put(h2cbuf, sizeof(struct fwcmd_fcs));
if (!buf) {
PLTFM_MSG_ERR("[HM][H2C][FCS] ret = %d\n", MACNOBUF);
return MACNOBUF;
}
pkt = (struct fwcmd_fcs *)buf;
pkt->dword0 = cpu_to_le32(SET_WORD(fast_ch_sw_param->ap_port_id,
FWCMD_H2C_FCS_AP_PORT_ID) |
SET_WORD(fast_ch_sw_param->ch_idx,
FWCMD_H2C_FCS_CH_IDX) |
SET_WORD(fast_ch_sw_param->thermal_idx,
FWCMD_H2C_FCS_THERMAL_IDX) |
SET_WORD(fast_ch_sw_param->pause_rel_mode,
FWCMD_H2C_FCS_PAUSE_REL_MODE) |
SET_WORD(fast_ch_sw_param->con_sta_num,
FWCMD_H2C_FCS_CON_STA_NUM) |
(fast_ch_sw_param->band ? FWCMD_H2C_FCS_BAND : 0) |
SET_WORD(fast_ch_sw_param->bandwidth,
FWCMD_H2C_FCS_BANDWIDTH));
pkt->dword1 = cpu_to_le32(SET_WORD(fast_ch_sw_param->pri_ch,
FWCMD_H2C_FCS_PRI_CH) |
SET_WORD(fast_ch_sw_param->central_ch,
FWCMD_H2C_FCS_CENTRAL_CH));
pkt->dword2 = cpu_to_le32(fast_ch_sw_param->rel_pause_tsfl);
pkt->dword3 = cpu_to_le32(fast_ch_sw_param->rel_pause_tsfh);
pkt->dword4 = cpu_to_le32(fast_ch_sw_param->rel_pause_delay_time);
pkt->dword5 = cpu_to_le32(SET_WORD(fast_ch_sw_param->csa_pkt_id[0],
FWCMD_H2C_FCS_CSA_PKT_ID0) |
SET_WORD(fast_ch_sw_param->csa_pkt_id[1],
FWCMD_H2C_FCS_CSA_PKT_ID1) |
SET_WORD(fast_ch_sw_param->csa_pkt_id[2],
FWCMD_H2C_FCS_CSA_PKT_ID2) |
SET_WORD(fast_ch_sw_param->csa_pkt_id[3],
FWCMD_H2C_FCS_CSA_PKT_ID3));
ret = h2c_pkt_set_hdr(adapter, h2cbuf,
FWCMD_TYPE_H2C, FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_FCS, FWCMD_H2C_FUNC_FCS, 1, 1);
if (ret) {
PLTFM_MSG_ERR("[HM][H2C][FCS] error when set hdr\n");
return ret;
}
ret = h2c_pkt_build_txd(adapter, h2cbuf);
if (ret) {
PLTFM_MSG_ERR("[HM][H2C][FCS] error when build txd\n");
return ret;
}
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cbuf);
#else
ret = PLTFM_TX(h2cbuf->data, h2cbuf->len);
#endif
h2cb_free(adapter, h2cbuf);
if (ret) {
PLTFM_MSG_ERR("[HM][H2C][FCS] error when h2cb free\n");
return ret;
}
h2c_end_flow(adapter);
adapter->fast_ch_sw_info.busy = 1;
if (ret) {
PLTFM_MSG_ERR("[HM][H2C][FCS] error when h2c_end_flow\n");
return ret;
}
PLTFM_MSG_TRACE("[HM][H2C][FCS] ret = %d\n", ret);
return ret;
}
u32 mac_fast_ch_sw_done(struct mac_ax_adapter *adapter)
{
if (adapter->fast_ch_sw_info.busy)
return MACPROCBUSY;
else
return MACSUCCESS;
}
u32 mac_get_fast_ch_sw_rpt(struct mac_ax_adapter *adapter, u32 *fast_ch_sw_status_code)
{
*fast_ch_sw_status_code = adapter->fast_ch_sw_info.status;
return MACSUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/phy_misc.c
|
C
|
agpl-3.0
| 3,608
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PHY_MISC_H_
#define _MAC_AX_PHY_MISC_H_
#include "../type.h"
#include "fwcmd.h"
u32 mac_fast_ch_sw(struct mac_ax_adapter *adapter,
struct mac_ax_fast_ch_sw_param *fast_ch_sw_param);
u32 mac_fast_ch_sw_done(struct mac_ax_adapter *adapter);
u32 mac_get_fast_ch_sw_rpt(struct mac_ax_adapter *adapter, u32 *fast_ch_sw_status_code);
#endif // __MAC_AX_PHY_MISC_H_
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/phy_misc.h
|
C
|
agpl-3.0
| 1,053
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "phy_rpt.h"
#define MAC_AX_RX_CNT_SIZE 96
#define MAC_AX_DISP_QID_HOST 0x2
#define MAC_AX_DISP_QID_WLCPU 0xB
#define MAC_AX_DFS_HDR_SIZE 8
#define MAC_AX_DFS_RPT_SIZE 8
#define MAC_AX_DFS_RPT_SIZE_SH 3
#define MAC_AX_CH_INFO_BUF 0
#define B_AX_CH_INFO_BUF_128 0
#define B_AX_GET_CH_INFO_TO_DIS 0
#define B_AX_GET_CH_INFO_TO_8 2
#define B_AX_CH_INFO_INTVL_DIS 0
#define B_AX_CH_INFO_INTVL_1 1
#define B_AX_CH_INFO_INTVL_2 2
#define B_AX_CH_INFO_INTVL_4 4
#define B_AX_CH_INFO_INTVL_7 7
#define B_AX_CH_INFO_REQ_2 1
#define B_AX_DFS_BUF_64 1
#define MAC_AX_MAC_INFO_USE_SIZE 4
struct mac_ax_mac_info_t {
u32 dword0;
u32 dword1;
};
struct mac_ax_dfs_hdr_t {
u32 dword0;
u32 dword1;
};
static u32 is_cfg_avl(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *cfg,
struct mac_ax_ppdu_stat *ppdu)
{
if (cfg->dest == MAC_AX_PRPT_DEST_HOST && ppdu->dup2fw_en &&
ppdu->dup2fw_len != 0) {
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A)) {
if (is_cv(adapter, CBV))
return MACFUNCINPUT;
} else if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B)) {
if (is_cv(adapter, CAV))
return MACFUNCINPUT;
}
}
return MACSUCCESS;
}
static u32 cfg_ppdu_status(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_ppdu_stat *ppdu = &cfg->u.ppdu;
u32 reg = (ppdu->band) ? R_AX_PPDU_STAT_C1 : R_AX_PPDU_STAT;
u32 val;
u32 ret = 0;
ret = check_mac_en(adapter, ppdu->band, MAC_AX_CMAC_SEL);
if (ret) {
PLTFM_MSG_ERR("MAC%d is not ready\n", ppdu->band);
goto END;
}
ret = is_cfg_avl(adapter, cfg, ppdu);
if (ret) {
PLTFM_MSG_ERR("The PPDU status config is INVALID\n");
goto END;
}
if (!cfg->en) {
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)reg,
B_AX_PPDU_STAT_RPT_EN,
0, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
goto END;
}
#endif
val = MAC_REG_R32(reg);
val = val & ~B_AX_PPDU_STAT_RPT_EN;
MAC_REG_W32(reg, val);
goto END;
}
val = MAC_REG_R32(R_AX_HW_RPT_FWD);
switch (cfg->dest) {
case MAC_AX_PRPT_DEST_HOST:
if (ppdu->dup2fw_en) {
MAC_REG_W32(R_AX_RX_PPDU_STATUS_FW_MODE,
B_AX_HDR_PPDU_ENQ_WLCPU_EN |
SET_WORD(ppdu->dup2fw_len,
B_AX_CDR_PPDU_2_WLCPU_LEN));
}
val = SET_CLR_WORD(val, MAC_AX_FWD_TO_HOST, B_AX_FWD_PPDU_STAT);
break;
case MAC_AX_PRPT_DEST_WLCPU:
val = SET_CLR_WORD(val, MAC_AX_FWD_TO_WLAN_CPU,
B_AX_FWD_PPDU_STAT);
break;
default:
PLTFM_MSG_ERR("Wrong PPDU status destination\n");
ret = MACFUNCINPUT;
}
MAC_REG_W32(R_AX_HW_RPT_FWD, val);
ppdu->bmp_append_info = ppdu->bmp_append_info &
(MAC_AX_PPDU_MAC_INFO |
MAC_AX_PPDU_PLCP |
MAC_AX_PPDU_RX_CNT);
ppdu->bmp_filter = ppdu->bmp_filter &
(MAC_AX_PPDU_HAS_A1M |
MAC_AX_PPDU_HAS_CRC_OK);
val = B_AX_PPDU_STAT_RPT_EN |
ppdu->bmp_filter |
ppdu->bmp_append_info;
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W32_OFLD((u16)reg, val, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
goto END;
}
#endif
MAC_REG_W32(reg, val);
END:
return ret;
}
static u32 en_bbrpt(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val;
val = MAC_REG_R32(R_AX_DMAC_CLK_EN);
if (!(val & B_AX_BBRPT_CLK_EN)) {
val = val | B_AX_BBRPT_CLK_EN;
MAC_REG_W32(R_AX_DMAC_CLK_EN, val);
}
val = MAC_REG_R32(R_AX_DMAC_FUNC_EN);
if (!(val & B_AX_BBRPT_EN)) {
val = val | B_AX_BBRPT_EN;
MAC_REG_W32(R_AX_DMAC_FUNC_EN, val);
}
return MACSUCCESS;
}
static u32 stop_ch_info(struct mac_ax_adapter *adapter, u32 ch_info_reg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val;
u32 count = 3000;
#if MAC_AX_FW_REG_OFLD
u32 ret;
#endif
val = MAC_REG_R8(R_AX_CH_INFO);
MAC_REG_W8(R_AX_CH_INFO, val | B_AX_CH_INFO_STOP_REQ);
while (!(MAC_REG_R8(R_AX_CH_INFO) & B_AX_CH_INFO_STOP)) {
count--;
if (count == 0) {
PLTFM_MSG_ERR("Polling ch info idle timeout\n");
return MACPOLLTO;
}
}
val = MAC_REG_R8(R_AX_CH_INFO);
MAC_REG_W8(R_AX_CH_INFO, val | B_AX_CH_INFO_EN);
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W_OFLD((u16)ch_info_reg, B_AX_GET_CH_INFO_EN, 0, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
#endif
val = MAC_REG_R8(ch_info_reg);
MAC_REG_W8(ch_info_reg, val & ~B_AX_GET_CH_INFO_EN);
return MACSUCCESS;
}
static u32 cfg_ch_info(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg;
u32 val;
u32 ret = 0;
struct mac_role_tbl *role;
struct mac_ax_ch_info *chif = &cfg->u.chif;
u8 band;
u8 intvl;
role = mac_role_srch(adapter, chif->macid);
if (!role) {
PLTFM_MSG_ERR("[ERR]cannot find macid: %d\n", chif->macid);
ret = MACNOITEM;
goto END;
}
band = role->info.band;
en_bbrpt(adapter);
reg = (band == MAC_AX_BAND_0) ?
R_AX_CH_INFO_QRY : R_AX_CH_INFO_QRY_C1;
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
if (ret) {
PLTFM_MSG_ERR("MAC%d is not ready\n", band);
goto END;
}
if (!cfg->en) {
ret = stop_ch_info(adapter, reg);
goto END;
}
switch (chif->seg_size) {
case MAC_AX_CH_IFNO_SEG_128:
intvl = B_AX_CH_INFO_INTVL_1;
break;
case MAC_AX_CH_IFNO_SEG_256:
intvl = B_AX_CH_INFO_INTVL_2;
break;
case MAC_AX_CH_IFNO_SEG_512:
intvl = B_AX_CH_INFO_INTVL_4;
break;
case MAC_AX_CH_IFNO_SEG_1024:
intvl = B_AX_CH_INFO_INTVL_7;
break;
default:
PLTFM_MSG_ERR("Wrong ch info segment\n");
ret = MACFUNCINPUT;
goto END;
}
MAC_REG_W8(R_AX_BB_COEX_CFG, B_AX_BBRPT_COEX_EN);
MAC_REG_W32(R_AX_CH_INFO,
SET_WORD(cfg->dest == MAC_AX_PRPT_DEST_WLCPU ?
MAC_AX_DISP_QID_WLCPU : MAC_AX_DISP_QID_HOST,
B_AX_CH_INFO_QID) |
SET_WORD(B_AX_CH_INFO_REQ_2, B_AX_CH_INFO_REQ) |
SET_WORD(chif->seg_size, B_AX_CH_INFO_SEG) |
SET_WORD(intvl, B_AX_CH_INFO_INTVL) |
(chif->dis_to ?
0 : SET_WORD(B_AX_GET_CH_INFO_TO_8, B_AX_GET_CH_INFO_TO)) |
(band ? B_AX_CH_INFO_PHY : 0) |
SET_WORD(B_AX_CH_INFO_BUF_128, B_AX_CH_INFO_BUF) |
B_AX_CH_INFO_EN);
switch (chif->trigger) {
case MAC_AX_CH_INFO_MACID:
case MAC_AX_CH_INFO_ACK:
val = B_AX_GET_CH_INFO_EN |
SET_WORD(MAC_AX_CH_INFO_MACID, B_AX_CH_INFO_MODE) |
SET_WORD(chif->macid, B_AX_CH_INFO_MACID) |
((chif->bmp_filter << 16) & (B_AX_CH_INFO_CRC_FAIL |
B_AX_CH_INFO_DATA_FRM |
B_AX_CH_INFO_CTRL_FRM |
B_AX_CH_INFO_MGNT_FRM));
break;
case MAC_AX_CH_INFO_NDP:
val = B_AX_GET_CH_INFO_EN |
SET_WORD(chif->trigger, B_AX_CH_INFO_MODE) |
SET_WORD(chif->macid, B_AX_CH_INFO_MACID);
break;
case MAC_AX_CH_INFO_SND:
val = B_AX_GET_CH_INFO_EN |
SET_WORD(chif->trigger, B_AX_CH_INFO_MODE) |
SET_WORD(chif->macid, B_AX_CH_INFO_MACID) |
((chif->bmp_filter << 16) & (B_AX_CH_INFO_CRC_FAIL |
B_AX_CH_INFO_DATA_FRM |
B_AX_CH_INFO_CTRL_FRM |
B_AX_CH_INFO_MGNT_FRM));
break;
default:
PLTFM_MSG_ERR("Wrong channel info mode\n");
ret = MACFUNCINPUT;
goto END;
}
#if MAC_AX_FW_REG_OFLD
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
ret = MAC_REG_W32_OFLD((u16)reg, val, 1);
if (ret != MACSUCCESS)
PLTFM_MSG_ERR("%s: write offload fail %d",
__func__, ret);
return ret;
}
#endif
MAC_REG_W32(reg, val);
END:
return ret;
}
static u32 stop_dfs(struct mac_ax_adapter *adapter)
{
#define MAC_AX_PHY_RPT_CNT 3000
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u8 val;
u32 count = MAC_AX_PHY_RPT_CNT;
val = MAC_REG_R8(R_AX_DFS_CFG0);
MAC_REG_W8(R_AX_DFS_CFG0, val | B_AX_STOP_DFS);
while (!(MAC_REG_R8(R_AX_DFS_CFG0) & B_AX_DFS_IN_STOP)) {
count--;
if (count == 0) {
PLTFM_MSG_ERR("Polling ch info idle timeout\n");
return MACPOLLTO;
}
}
MAC_REG_W8(R_AX_DFS_CFG0, val & ~B_AX_DFS_RPT_EN);
return MACSUCCESS;
}
static u32 cfg_dfs(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *cfg)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
struct mac_ax_dfs *dfs = &cfg->u.dfs;
u32 ret = 0, val;
en_bbrpt(adapter);
if (!cfg->en) {
ret = stop_dfs(adapter);
goto END;
}
switch (dfs->num_th) {
case MAC_AX_DFS_TH_29:
case MAC_AX_DFS_TH_61:
case MAC_AX_DFS_TH_93:
case MAC_AX_DFS_TH_125:
val = B_AX_DFS_RPT_EN |
SET_WORD(B_AX_DFS_BUF_64, B_AX_DFS_BUF) |
SET_WORD(dfs->num_th, B_AX_DFS_NUM_TH) |
SET_WORD(dfs->en_timeout ? 1 : 0, B_AX_DFS_TIME_TH) |
SET_WORD(cfg->dest == MAC_AX_PRPT_DEST_WLCPU ?
MAC_AX_DISP_QID_WLCPU : MAC_AX_DISP_QID_HOST,
B_AX_DFS_QID);
break;
default:
PLTFM_MSG_ERR("Wrong DFS report num threshold\n");
ret = MACFUNCINPUT;
goto END;
}
MAC_REG_W32(R_AX_DFS_CFG0, val);
END:
return ret;
}
u32 mac_cfg_phy_rpt(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *rpt)
{
u32 (*handle)(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *rpt);
switch (rpt->type) {
case MAC_AX_PPDU_STATUS:
handle = cfg_ppdu_status;
break;
case MAC_AX_CH_INFO:
handle = cfg_ch_info;
break;
case MAC_AX_DFS:
handle = cfg_dfs;
break;
default:
PLTFM_MSG_ERR("Wrong PHY report type\n");
return MACFUNCINPUT;
}
return handle(adapter, rpt);
}
static u32 parse_mac_info(struct mac_ax_adapter *adapter,
u8 *buf, u32 len,
struct mac_ax_ppdu_rpt *rpt)
{
struct mac_ax_ppdu_usr *usr;
struct mac_ax_mac_info_t *macinfo;
u8 i;
u32 ret = MACSUCCESS;
u32 accu_size = sizeof(struct mac_ax_mac_info_t);
u32 val;
u8 *ptr;
macinfo = (struct mac_ax_mac_info_t *)buf;
/* dword0 */
val = le32_to_cpu(macinfo->dword0);
rpt->usr_num = (u8)GET_FIELD(val, AX_MAC_INFO_USR_NUM);
if (rpt->usr_num > MAC_AX_PPDU_MAX_USR) {
PLTFM_MSG_ERR("The user num in mac info is invalid\n");
ret = MACPARSEERR;
goto END;
}
rpt->fw_def = (u8)GET_FIELD(val, AX_MAC_INFO_FW_DEFINE);
rpt->lsig_len = (u16)GET_FIELD(val, AX_MAC_INFO_LSIG_LEN);
rpt->is_to_self = !!(val & AX_MAC_INFO_IS_TO_SELF);
rpt->rx_cnt_size = val & AX_MAC_INFO_RX_CNT_VLD ?
MAC_AX_RX_CNT_SIZE : 0;
/* dowrd1 */
val = le32_to_cpu(macinfo->dword1);
rpt->service = (u16)GET_FIELD(val, AX_MAC_INFO_SERVICE);
rpt->plcp_size = (u8)GET_FIELD(val, AX_MAC_INFO_PLCP_LEN) * 8;
/* dword2 */
usr = rpt->usr;
ptr = (u8 *)(macinfo + 1);
for (i = 0; i < rpt->usr_num; i++, usr++) {
val = le32_to_cpu(*((u32 *)ptr));
usr->vld = !!(val & AX_MAC_INFO_MAC_ID_VALID);
usr->has_data = !!(val & AX_MAC_INFO_HAS_DATA);
usr->has_ctrl = !!(val & AX_MAC_INFO_HAS_CTRL);
usr->has_mgnt = !!(val & AX_MAC_INFO_HAS_MGNT);
usr->has_bcn = !!(val & AX_MAC_INFO_HAS_BCN);
usr->macid = (u8)GET_FIELD(val, AX_MAC_INFO_MACID);
accu_size += MAC_AX_MAC_INFO_USE_SIZE;
ptr += MAC_AX_MAC_INFO_USE_SIZE;
}
/* 8-byte alignment */
accu_size += rpt->usr_num & BIT(0) ? MAC_AX_MAC_INFO_USE_SIZE : 0;
ptr += rpt->usr_num & BIT(0) ? MAC_AX_MAC_INFO_USE_SIZE : 0;
if (rpt->rx_cnt_size) {
rpt->rx_cnt_ptr = ptr;
accu_size += rpt->rx_cnt_size;
ptr += rpt->rx_cnt_size;
}
if (rpt->plcp_size) {
rpt->plcp_ptr = ptr;
accu_size += rpt->plcp_size;
ptr += rpt->plcp_size;
}
if (len > accu_size) {
rpt->phy_st_ptr = ptr;
rpt->phy_st_size = len - accu_size;
}
END:
return ret;
}
u32 mac_parse_ppdu(struct mac_ax_adapter *adapter,
u8 *buf, u32 ppdu_len, u8 mac_info,
struct mac_ax_ppdu_rpt *rpt)
{
u32 ret = MACSUCCESS;
PLTFM_MEMSET(rpt, 0, sizeof(struct mac_ax_ppdu_rpt));
if (mac_info) {
ret = parse_mac_info(adapter, buf, ppdu_len, rpt);
} else {
rpt->phy_st_ptr = buf;
rpt->phy_st_size = ppdu_len;
}
return ret;
}
u32 mac_parse_dfs(struct mac_ax_adapter *adapter,
u8 *buf, u32 dfs_len, struct mac_ax_dfs_rpt *rpt)
{
struct mac_ax_dfs_hdr_t *dfs;
u32 len;
u32 msk = BIT(MAC_AX_DFS_RPT_SIZE_SH) - 1;
u32 ret = 0;
u32 val;
dfs = (struct mac_ax_dfs_hdr_t *)buf;
/* dword0 */
val = le32_to_cpu(dfs->dword0);
rpt->drop_num = (u16)GET_FIELD(val, AX_DFS_DROP_NUM);
rpt->max_cont_drop = (u16)GET_FIELD(val, AX_DFS_MAX_CONT_DROP);
/* dword1 */
val = le32_to_cpu(dfs->dword1);
rpt->total_drop = (u16)GET_FIELD(val, AX_DFS_TOTAL_DROP);
len = dfs_len - MAC_AX_DFS_HDR_SIZE;
rpt->dfs_num = (u16)(len >> MAC_AX_DFS_RPT_SIZE_SH);
if (len & msk) {
PLTFM_MSG_ERR("The DFS report size is wrong\n");
ret = MACPARSEERR;
}
rpt->dfs_ptr = buf + MAC_AX_DFS_HDR_SIZE;
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/phy_rpt.c
|
C
|
agpl-3.0
| 13,398
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PHY_RPT_H_
#define _MAC_AX_PHY_RPT_H_
#include "../type.h"
#include "role.h"
#include "trxcfg.h"
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_cfg_phy_rpt
*
* @param *adapter
* @param *cfg
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_phy_rpt(struct mac_ax_adapter *adapter,
struct mac_ax_phy_rpt_cfg *cfg);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_parse_ppdu
*
* @param *adapter
* @param *buf
* @param ppdu_len
* @param mac_info
* @param *rpt
* @return Please Place Description here.
* @retval u32
*/
u32 mac_parse_ppdu(struct mac_ax_adapter *adapter,
u8 *buf, u32 ppdu_len, u8 mac_info,
struct mac_ax_ppdu_rpt *rpt);
/**
* @}
* @}
*/
/**
* @addtogroup Common
* @{
* @addtogroup BB_Related
* @{
*/
/**
* @brief mac_parse_dfs
*
* @param *adapter
* @param *buf
* @param dfs_len
* @param *rpt
* @return Please Place Description here.
* @retval u32
*/
u32 mac_parse_dfs(struct mac_ax_adapter *adapter,
u8 *buf, u32 dfs_len, struct mac_ax_dfs_rpt *rpt);
/**
* @}
* @}
*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/phy_rpt.h
|
C
|
agpl-3.0
| 1,869
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "power_saving.h"
#include "coex.h"
#define RPWM_SEQ_NUM_MAX 3
#define CPWM_SEQ_NUM_MAX 3
//RPWM bit definition
#define PS_RPWM_TOGGLE BIT(15)
#define PS_RPWM_ACK BIT(14)
#define PS_RPWM_SEQ_NUM_SH 12
#define PS_RPWM_SEQ_NUM_MSK 0x3
#define PS_RPWM_STATE_SH 0
#define PS_RPWM_STATE_MSK 0x7
//CPWM bit definition
#define PS_CPWM_TOGGLE BIT(15)
#define PS_CPWM_ACK BIT(14)
#define PS_CPWM_SEQ_NUM_SH 12
#define PS_CPWM_SEQ_NUM_MSK 0x3
#define PS_CPWM_RSP_SEQ_NUM_SH 8
#define PS_CPWM_RSP_SEQ_NUM_MSK 0x3
#define PS_CPWM_STATE_SH 0
#define PS_CPWM_STATE_MSK 0x7
//(workaround) CPWM register is in OFF area
//LPS debug message bit definition
#define B_PS_LDM_32K_EN BIT(31)
#define B_PS_LDM_32K_EN_SH 31
static u32 lps_status[4] = {0};
static u8 rpwm_seq_num = RPWM_SEQ_NUM_MAX;
static u8 cpwm_seq_num = CPWM_SEQ_NUM_MAX;
static u32 send_h2c_lps_parm(struct mac_ax_adapter *adapter,
struct lps_parm *parm)
{
u8 *buf;
#if MAC_AX_PHL_H2C
struct rtw_h2c_pkt *h2cb;
#else
struct h2c_buf *h2cb;
#endif
struct fwcmd_lps_parm *fwcmd_lps;
u32 ret = 0;
h2cb = h2cb_alloc(adapter, H2CB_CLASS_CMD);
if (!h2cb)
return MACNPTR;
buf = h2cb_put(h2cb, sizeof(struct fwcmd_lps_parm));
if (!buf) {
ret = MACNOBUF;
goto fail;
}
fwcmd_lps = (struct fwcmd_lps_parm *)buf;
fwcmd_lps->dword0 =
cpu_to_le32(SET_WORD(parm->macid, FWCMD_H2C_LPS_PARM_MACID) |
SET_WORD(parm->psmode, FWCMD_H2C_LPS_PARM_PSMODE) |
SET_WORD(parm->rlbm, FWCMD_H2C_LPS_PARM_RLBM) |
SET_WORD(parm->smartps, FWCMD_H2C_LPS_PARM_SMARTPS) |
SET_WORD(parm->awakeinterval,
FWCMD_H2C_LPS_PARM_AWAKEINTERVAL));
fwcmd_lps->dword1 =
cpu_to_le32((parm->vouapsd ? FWCMD_H2C_LPS_PARM_VOUAPSD : 0) |
(parm->viuapsd ? FWCMD_H2C_LPS_PARM_VIUAPSD : 0) |
(parm->beuapsd ? FWCMD_H2C_LPS_PARM_BEUAPSD : 0) |
(parm->bkuapsd ? FWCMD_H2C_LPS_PARM_BKUAPSD : 0) |
SET_WORD(parm->lastrpwm, FWCMD_H2C_LPS_PARM_LASTRPWM));
ret = h2c_pkt_set_hdr(adapter, h2cb,
FWCMD_TYPE_H2C,
FWCMD_H2C_CAT_MAC,
FWCMD_H2C_CL_PS,
FWCMD_H2C_FUNC_LPS_PARM,
0,
1);
if (ret)
goto fail;
ret = h2c_pkt_build_txd(adapter, h2cb);
if (ret)
goto fail;
#if MAC_AX_PHL_H2C
ret = PLTFM_TX(h2cb);
#else
ret = PLTFM_TX(h2cb->data, h2cb->len);
#endif
if (ret)
goto fail;
h2cb_free(adapter, h2cb);
return MACSUCCESS;
fail:
h2cb_free(adapter, h2cb);
return ret;
}
static void send_rpwm(struct mac_ax_adapter *adapter,
enum mac_ax_rpwm_req_pwr_state req_pwr_state)
{
u16 next_rpwm_value = 0;
u16 current_rpwm_value = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (rpwm_seq_num == RPWM_SEQ_NUM_MAX)
rpwm_seq_num = 0;
else
rpwm_seq_num += 1;
next_rpwm_value = (SET_WORD(req_pwr_state, PS_RPWM_STATE) |
SET_WORD(rpwm_seq_num, PS_RPWM_SEQ_NUM));
if (req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_ACTIVE ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFON ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFON ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND0_RFOFF ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_BAND1_RFOFF)
next_rpwm_value |= PS_RPWM_ACK;
current_rpwm_value = MAC_REG_R16(R_AX_RPWM);
if (0 == (current_rpwm_value & PS_RPWM_TOGGLE))
next_rpwm_value |= PS_RPWM_TOGGLE;
if (req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED) {
adapter->mac_pwr_info.pwr_in_lps = 1;
}
switch (adapter->hw_info->intf) {
case MAC_AX_INTF_USB:
#if (MAC_AX_USB_SUPPORT)
MAC_REG_W16(R_AX_USB_D2F_F2D_INFO + 2, next_rpwm_value);
#endif
break;
case MAC_AX_INTF_SDIO:
#if (MAC_AX_SDIO_SUPPORT)
MAC_REG_W16(R_AX_SDIO_HRPWM1 + 2, next_rpwm_value);
if (req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_PWR_GATED ||
req_pwr_state == MAC_AX_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED)
adapter->sdio_info.tx_seq = 1;
#endif
break;
case MAC_AX_INTF_PCIE:
#if (MAC_AX_PCIE_SUPPORT)
MAC_REG_W16(R_AX_PCIE_HRPWM, next_rpwm_value);
#endif
break;
default:
PLTFM_MSG_ERR("%s: invalid interface = %d!!\n",
__func__, adapter->hw_info->intf);
break;
}
PLTFM_MSG_TRACE("Send RPWM. rpwm_val=0x%x, HRPWM=0x%x, RPWM=0x%x\n",
next_rpwm_value, MAC_REG_R16(R_AX_PCIE_HRPWM), MAC_REG_R16(R_AX_RPWM));
}
static u32 leave_lps(struct mac_ax_adapter *adapter, u8 macid)
{
struct lps_parm h2c_lps_parm;
u32 ret;
PLTFM_MEMSET(&h2c_lps_parm, 0, sizeof(struct lps_parm));
h2c_lps_parm.macid = macid;
h2c_lps_parm.psmode = MAC_AX_PS_MODE_ACTIVE;
h2c_lps_parm.lastrpwm = LAST_RPWM_ACTIVE;
ret = send_h2c_lps_parm(adapter, &h2c_lps_parm);
if (ret)
return ret;
lps_status[(macid >> 5)] &= ~BIT(macid & 0x1F);
return MACSUCCESS;
}
static u32 enter_lps(struct mac_ax_adapter *adapter,
u8 macid,
struct mac_ax_lps_info *lps_info)
{
struct lps_parm h2c_lps_parm;
u32 ret = 0;
if (!lps_info) {
PLTFM_MSG_ERR("[ERR]:LPS info is null\n");
return MACNOITEM;
}
if (lps_status[(macid >> 5)] & BIT(macid & 0x1F))
ret = leave_lps(adapter, macid);
if (ret)
return ret;
PLTFM_MEMSET(&h2c_lps_parm, 0, sizeof(struct lps_parm));
h2c_lps_parm.macid = macid;
h2c_lps_parm.psmode = MAC_AX_PS_MODE_LEGACY;
if (lps_info->listen_bcn_mode > MAC_AX_RLBM_USERDEFINE)
lps_info->listen_bcn_mode = MAC_AX_RLBM_MIN;
if (lps_info->listen_bcn_mode == MAC_AX_RLBM_USERDEFINE) {
h2c_lps_parm.rlbm = MAC_AX_RLBM_USERDEFINE;
h2c_lps_parm.awakeinterval = lps_info->awake_interval;
if (h2c_lps_parm.awakeinterval == 0)
h2c_lps_parm.awakeinterval = 1;
} else if (lps_info->listen_bcn_mode == MAC_AX_RLBM_MAX) {
h2c_lps_parm.rlbm = MAC_AX_RLBM_MAX;
h2c_lps_parm.awakeinterval = 1;
} else {
h2c_lps_parm.rlbm = MAC_AX_RLBM_MIN;
h2c_lps_parm.awakeinterval = 1;
}
h2c_lps_parm.smartps = lps_info->smart_ps_mode;
h2c_lps_parm.lastrpwm = LAST_RPWM_PS;
ret = send_h2c_lps_parm(adapter, &h2c_lps_parm);
if (ret)
return ret;
lps_status[(macid >> 5)] |= BIT(macid & 0x1F);
return MACSUCCESS;
}
static u32 set_req_pwr_state(struct mac_ax_adapter *adapter,
enum mac_ax_rpwm_req_pwr_state req_pwr_state)
{
if (req_pwr_state >= MAC_AX_RPWM_REQ_PWR_STATE_MAX) {
PLTFM_MSG_ERR("%s: invalid pwr state:%d\n",
__func__, req_pwr_state);
return MACNOITEM;
}
send_rpwm(adapter, req_pwr_state);
return MACSUCCESS;
}
static u32 _chk_cpwm_seq_num(u8 seq_num)
{
u32 ret;
if (cpwm_seq_num == CPWM_SEQ_NUM_MAX) {
if (seq_num == 0) {
cpwm_seq_num = seq_num;
ret = MACSUCCESS;
} else {
ret = MACCPWMSEQERR;
}
} else {
if (seq_num == (cpwm_seq_num + 1)) {
cpwm_seq_num = seq_num;
ret = MACSUCCESS;
} else {
ret = MACCPWMSEQERR;
}
}
return ret;
}
static u32 chk_cur_pwr_state(struct mac_ax_adapter *adapter,
enum mac_ax_rpwm_req_pwr_state req_pwr_state)
{
u16 cpwm;
u32 rpwm_32k;
u32 req_32k;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
if (req_pwr_state >= MAC_AX_RPWM_REQ_PWR_STATE_CLK_GATED)
req_32k = 1;
else
req_32k = 0;
//(workaround) CPWM register is in OFF area
//Use LDM to check if FW receives RPWM
rpwm_32k = (MAC_REG_R32(R_AX_LDM) & B_PS_LDM_32K_EN) >> B_PS_LDM_32K_EN_SH;
if (req_32k != rpwm_32k)
return MACCPWMPWRSTATERR;
//There is no CPWM if 32K state
if (req_32k)
return MACSUCCESS;
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C))
cpwm = MAC_REG_R16(R_AX_CPWM_V1);
else
cpwm = MAC_REG_R16(R_AX_CPWM);
PLTFM_MSG_TRACE("Read CPWM=0x%x\n", cpwm);
if (rpwm_seq_num != GET_FIELD(cpwm, PS_CPWM_RSP_SEQ_NUM)) {
PLTFM_MSG_TRACE("RPWM seq mismatch!!: expect val:%d, Rx val:%d\n",
rpwm_seq_num, GET_FIELD(cpwm, PS_CPWM_RSP_SEQ_NUM));
return MACCPWMSEQERR;
}
if (_chk_cpwm_seq_num(GET_FIELD(cpwm, PS_CPWM_SEQ_NUM)) == MACCPWMSEQERR) {
PLTFM_MSG_TRACE("CPWM seq mismatch!!: expect val:%d, Rx val:%d\n",
cpwm_seq_num, GET_FIELD(cpwm, PS_CPWM_SEQ_NUM));
return MACCPWMSEQERR;
}
if (req_pwr_state != GET_FIELD(cpwm, PS_CPWM_STATE))
return MACCPWMSTATERR;
adapter->mac_pwr_info.pwr_in_lps = 0;
return MACSUCCESS;
}
u32 mac_cfg_lps(struct mac_ax_adapter *adapter, u8 macid,
enum mac_ax_ps_mode ps_mode, void *lps_info)
{
u32 ret = 0;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
switch (ps_mode) {
case MAC_AX_PS_MODE_ACTIVE:
ret = leave_lps(adapter, macid);
/* patch form BT BG/LDO issue, ONLY FOR 52B CAV */
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
is_cv(adapter, CAV))
MAC_REG_W8(R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
break;
case MAC_AX_PS_MODE_LEGACY:
ret = enter_lps(adapter, macid,
(struct mac_ax_lps_info *)lps_info);
/* patch form BT BG/LDO issue, ONLY FOR 52B CAV */
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
is_cv(adapter, CAV))
MAC_REG_W8(R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
break;
case MAC_AX_PS_MODE_WMMPS:
// TODO:
break;
default:
return MACNOITEM;
}
if (ret)
return ret;
return MACSUCCESS;
}
u32 mac_lps_pwr_state(struct mac_ax_adapter *adapter,
enum mac_ax_pwr_state_action action,
enum mac_ax_rpwm_req_pwr_state req_pwr_state)
{
u32 ret = MACSUCCESS;
switch (action) {
case MAC_AX_PWR_STATE_ACT_REQ:
ret = set_req_pwr_state(adapter, req_pwr_state);
break;
case MAC_AX_PWR_STATE_ACT_CHK:
ret = chk_cur_pwr_state(adapter, req_pwr_state);
break;
default:
ret = MACNOITEM;
}
return ret;
}
u32 mac_chk_leave_lps(struct mac_ax_adapter *adapter, u8 macid)
{
u8 band = 0;
u8 port = 0;
u32 chk_msk = 0;
struct mac_role_tbl *role;
u16 pwrbit_set_reg[2] = {R_AX_PPWRBIT_SETTING, R_AX_PPWRBIT_SETTING_C1};
u32 pwr_mgt_en_bit = 0xE;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 reg_pause = 0;
u32 reg_sleep = 0;
u8 macid_grp = macid >> MACID_GRP_SH;
u8 macid_sh = macid & MACID_GRP_MASK;
role = mac_role_srch(adapter, macid);
if (!role) {
PLTFM_MSG_ERR("[ERR]cannot find macid: %d\n", macid);
return MACNOITEM;
}
band = role->info.a_info.bb_sel;
port = role->info.a_info.port_int;
chk_msk = pwr_mgt_en_bit << (PORT_SH * port);
switch (macid_grp) {
case MACID_GRP_0:
reg_sleep = R_AX_MACID_SLEEP_0;
reg_pause = R_AX_SS_MACID_PAUSE_0;
break;
case MACID_GRP_1:
reg_sleep = R_AX_MACID_SLEEP_1;
reg_pause = R_AX_SS_MACID_PAUSE_1;
break;
case MACID_GRP_2:
reg_sleep = R_AX_MACID_SLEEP_2;
reg_pause = R_AX_SS_MACID_PAUSE_2;
break;
case MACID_GRP_3:
reg_sleep = R_AX_MACID_SLEEP_3;
reg_pause = R_AX_SS_MACID_PAUSE_3;
break;
default:
return MACPSSTATFAIL;
}
// Bypass Tx pause check during STOP SER period
if (adapter->sm.ser_ctrl_st != MAC_AX_SER_CTRL_STOP)
if (MAC_REG_R32(reg_pause) & BIT(macid_sh))
return MACPSSTATFAIL;
if ((MAC_REG_R32(pwrbit_set_reg[band]) & chk_msk) ||
(MAC_REG_R32(reg_sleep) & BIT(macid_sh)))
return MACPSSTATFAIL;
return MACSUCCESS;
}
u8 _is_in_lps(struct mac_ax_adapter *adapter)
{
u8 i;
for (i = 0; i < 4; i++) {
if (lps_status[i] != 0)
return 1;
}
return 0;
}
void reset_lps_seq_num(struct mac_ax_adapter *adapter)
{
rpwm_seq_num = RPWM_SEQ_NUM_MAX;
cpwm_seq_num = CPWM_SEQ_NUM_MAX;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/power_saving.c
|
C
|
agpl-3.0
| 12,022
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_POWER_SAVING_H_
#define _MAC_AX_POWER_SAVING_H_
#include "../type.h"
#include "fwcmd.h"
#include "role.h"
#define MACID_GRP_SH 5
#define MACID_GRP_MASK 0x1F
#define PORT_SH 4
/**
* @enum last_rpwm_mode
*
* @brief last_rpwm_mode
*
* @var last_rpwm_mode::LAST_RPWM_PS
* Please Place Description here.
* @var last_rpwm_mode::LAST_RPWM_ACTIVE
* Please Place Description here.
*/
enum last_rpwm_mode {
LAST_RPWM_PS = 0x0,
LAST_RPWM_ACTIVE = 0x6,
};
/**
* @struct lps_parm
* @brief lps_parm
*
* @var lps_parm::macid
* Please Place Description here.
* @var lps_parm::psmode
* Please Place Description here.
* @var lps_parm::rlbm
* Please Place Description here.
* @var lps_parm::smartps
* Please Place Description here.
* @var lps_parm::awakeinterval
* Please Place Description here.
* @var lps_parm::vouapsd
* Please Place Description here.
* @var lps_parm::viuapsd
* Please Place Description here.
* @var lps_parm::beuapsd
* Please Place Description here.
* @var lps_parm::bkuapsd
* Please Place Description here.
* @var lps_parm::rsvd
* Please Place Description here.
* @var lps_parm::lastrpwm
* Please Place Description here.
* @var lps_parm::rsvd1
* Please Place Description here.
*/
struct lps_parm {
u32 macid:8;
u32 psmode:8;
u32 rlbm:4;
u32 smartps:4;
u32 awakeinterval:8;
u32 vouapsd:1;
u32 viuapsd:1;
u32 beuapsd:1;
u32 bkuapsd:1;
u32 rsvd:4;
u32 lastrpwm:8;
u32 rsvd1:16;
};
/**
* @macid_grp_list
*
* @brief macid_grp_list
*
* @var macid_grp_list::MACID_GRP_0
* Please Place Description here.
* @var macid_grp_list::MACID_GRP_1
* Please Place Description here.
* @var macid_grp_list::MACID_GRP_2
* Please Place Description here.
* @var macid_grp_list::MACID_GRP_3
* Please Place Description here.
*/
enum macid_grp_list {
MACID_GRP_0 = 0,
MACID_GRP_1 = 1,
MACID_GRP_2 = 2,
MACID_GRP_3 = 3,
};
/**
* @addtogroup PowerSaving
* @{
* @addtogroup LPS
* @{
*/
/**
* @brief mac_cfg_lps
*
* @param *adapter
* @param macid
* @param ps_mode
* @param *lps_info
* @return Please Place Description here.
* @retval u32
*/
u32 mac_cfg_lps(struct mac_ax_adapter *adapter, u8 macid,
enum mac_ax_ps_mode ps_mode, void *lps_info);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup LPS
* @{
*/
/**
* @brief mac_lps_pwr_state
*
* @param *adapter
* @param action
* @param req_pwr_state
* @return Please Place Description here.
* @retval u32
*/
u32 mac_lps_pwr_state(struct mac_ax_adapter *adapter,
enum mac_ax_pwr_state_action action,
enum mac_ax_rpwm_req_pwr_state req_pwr_state);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup LPS
* @{
*/
/**
* @brief mac_chk_leave_lps
*
* @param *adapter
* @param macid
* @return Please Place Description here.
* @retval u32
*/
u32 mac_chk_leave_lps(struct mac_ax_adapter *adapter, u8 macid);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup LPS
* @{
*/
/**
* @brief _is_in_lps
*
* @param *adapter
* @return Please Place Description here.
* @retval u8
*/
u8 _is_in_lps(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
/**
* @addtogroup PowerSaving
* @{
* @addtogroup LPS
* @{
*/
/**
* @brief reset_lps_seq_num
*
* @param *adapter
* @return Please Place Description here.
* @retval void
*/
void reset_lps_seq_num(struct mac_ax_adapter *adapter);
/**
* @}
* @}
*/
#endif // #define _MAC_AX_POWER_SAVING_H_
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/power_saving.h
|
C
|
agpl-3.0
| 4,171
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "pwr.h"
#include "coex.h"
static void restore_flr_lps(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
MAC_REG_W32(R_AX_WCPU_FW_CTRL, 0);
MAC_REG_W32(R_AX_AFE_CTRL1, MAC_REG_R32(R_AX_AFE_CTRL1) &
~B_AX_CMAC_CLK_SEL);
MAC_REG_W32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
MAC_REG_R32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN) &
~(B_AX_GPIO8_PULL_LOW_EN | B_AX_LED1_PULL_LOW_EN));
}
static void clr_aon_int(struct mac_ax_adapter *adapter)
{
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32;
if (adapter->hw_info->intf != MAC_AX_INTF_PCIE)
return;
val32 = MAC_REG_R32(R_AX_FWS0IMR);
val32 &= ~B_AX_FS_GPIOA_INT_EN;
MAC_REG_W32(R_AX_FWS0IMR, val32);
val32 = MAC_REG_R32(R_AX_FWS0ISR);
val32 |= B_AX_FS_GPIOA_INT;
MAC_REG_W32(R_AX_FWS0ISR, val32);
}
static u32 _patch_aon_int_leave_lps(struct mac_ax_adapter *adapter)
{
struct mac_ax_ops *mac_ops = adapter_to_mac_ops(adapter);
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 val32, cnt, ret = MACSUCCESS;
if (adapter->hw_info->intf != MAC_AX_INTF_PCIE)
return MACSUCCESS;
restore_flr_lps(adapter);
val32 = MAC_REG_R32(R_AX_FWS0IMR);
val32 |= B_AX_FS_GPIOA_INT_EN;
MAC_REG_W32(R_AX_FWS0IMR, val32);
ret = mac_ops->set_gpio_func(adapter, RTW_MAC_GPIO_SW_IO,
LPS_LEAVE_GPIO);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]set gpio fail %d\n", ret);
return ret;
}
val32 = MAC_REG_R32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_HIGH_EN);
val32 |= B_AX_GPIO10_PULL_HIGH_EN;
MAC_REG_W32(R_AX_GPIO0_15_EECS_EESK_LED1_PULL_HIGH_EN, val32);
val32 = MAC_REG_R32(R_AX_GPIO_EXT_CTRL);
val32 |= (BIT10 | BIT18 | BIT26);
MAC_REG_W32(R_AX_GPIO_EXT_CTRL, val32);
val32 &= ~BIT10;
MAC_REG_W32(R_AX_GPIO_EXT_CTRL, val32);
val32 |= BIT10;
MAC_REG_W32(R_AX_GPIO_EXT_CTRL, val32);
cnt = LPS_POLL_CNT;
while (cnt && (GET_FIELD(MAC_REG_R32(R_AX_IC_PWR_STATE), B_AX_WLMAC_PWR_STE) ==
MAC_AX_MAC_LPS)) {
cnt--;
PLTFM_DELAY_US(LPS_POLL_DLY_US);
}
if (!cnt) {
PLTFM_MSG_ERR("[ERR]Polling MAC state timeout! 0x3F0 = %X\n",
MAC_REG_R32(R_AX_IC_PWR_STATE));
return MACPOLLTO;
}
return MACSUCCESS;
}
static u32 pwr_cmd_poll(struct mac_ax_adapter *adapter, struct mac_pwr_cfg *seq)
{
u8 val = 0;
u32 addr;
u32 cnt;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
cnt = PWR_POLL_CNT;
addr = seq->addr;
while (cnt--) {
val = MAC_REG_R8(addr);
val &= seq->msk;
if (val == (seq->val & seq->msk))
return MACSUCCESS;
PLTFM_DELAY_US(PWR_POLL_DLY_US);
}
PLTFM_MSG_ERR("[ERR] Polling timeout\n");
PLTFM_MSG_ERR("[ERR] addr: %X, %X\n", addr, seq->addr);
PLTFM_MSG_ERR("[ERR] val: %X, %X\n", val, seq->val);
return MACPOLLTO;
}
static u32 sub_pwr_seq_start(struct mac_ax_adapter *adapter,
u8 cv_msk, u8 intf_msk, struct mac_pwr_cfg *seq)
{
u8 val;
u32 addr;
u32 ret;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
while (seq->cmd != PWR_CMD_END) {
if (!(seq->intf_msk & intf_msk) || !(seq->cut_msk & cv_msk))
goto next_seq;
switch (seq->cmd) {
case PWR_CMD_WRITE:
addr = seq->addr;
val = MAC_REG_R8(addr);
val &= ~(seq->msk);
val |= (seq->val & seq->msk);
MAC_REG_W8(addr, val);
break;
case PWR_CMD_POLL:
ret = pwr_cmd_poll(adapter, seq);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr cmd poll %d\n", ret);
return ret;
}
break;
case PWR_CMD_DELAY:
if (seq->val == PWR_DELAY_US)
PLTFM_DELAY_US(seq->addr);
else
PLTFM_DELAY_US(seq->addr * 1000);
break;
default:
PLTFM_MSG_ERR("[ERR]unknown pwr seq cmd %d\n",
seq->cmd);
return MACNOITEM;
}
next_seq:
seq++;
}
return MACSUCCESS;
}
u32 pwr_seq_start(struct mac_ax_adapter *adapter,
struct mac_pwr_cfg **seq)
{
u8 cv;
u8 intf;
u32 ret;
struct mac_ax_hw_info *hw_info = adapter->hw_info;
struct mac_pwr_cfg *sub_seq = *seq;
#if MAC_AX_USB_SUPPORT
u32 val = 0;
#endif
switch (hw_info->cv) {
case CAV:
cv = PWR_CAV_MSK;
break;
case CBV:
cv = PWR_CBV_MSK;
break;
case CCV:
cv = PWR_CCV_MSK;
break;
case CDV:
cv = PWR_CDV_MSK;
break;
case CEV:
cv = PWR_CEV_MSK;
break;
default:
PLTFM_MSG_ERR("[ERR]cut version\n");
return MACNOITEM;
}
switch (hw_info->intf) {
case MAC_AX_INTF_SDIO:
intf = PWR_INTF_MSK_SDIO;
break;
case MAC_AX_INTF_USB:
#if MAC_AX_USB_SUPPORT
val = get_usb_mode(adapter);
if (val == MAC_AX_USB3)
intf = PWR_INTF_MSK_USB3;
else
intf = PWR_INTF_MSK_USB2;
break;
#endif
case MAC_AX_INTF_PCIE:
intf = PWR_INTF_MSK_PCIE;
break;
default:
PLTFM_MSG_ERR("[ERR]interface\n");
return MACNOITEM;
}
while (sub_seq) {
ret = sub_pwr_seq_start(adapter, cv, intf, sub_seq);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]sub pwr seq %d\n", ret);
return ret;
}
seq++;
sub_seq = *seq;
}
return MACSUCCESS;
}
u32 mac_pwr_switch(struct mac_ax_adapter *adapter, u8 on)
{
u32 ret = MACSUCCESS;
u32 ret_end;
struct mac_pwr_cfg **pwr_seq;
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
u32 (*intf_pwr_switch)(void *vadapter, u8 pre_switch, u8 on);
u32 (*pwr_func)(void *vadapter);
u32 val32;
val32 = MAC_REG_R32(R_AX_GPIO_MUXCFG) & B_AX_BOOT_MODE;
if (val32 == B_AX_BOOT_MODE) {
val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL) & ~B_AX_APFN_ONMAC;
MAC_REG_W32(R_AX_SYS_PW_CTRL, val32);
val32 = MAC_REG_R32(R_AX_SYS_STATUS1) & ~B_AX_AUTO_WLPON;
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
val32 = MAC_REG_R32(R_AX_GPIO_MUXCFG) & ~B_AX_BOOT_MODE;
MAC_REG_W32(R_AX_GPIO_MUXCFG, val32);
val32 = MAC_REG_R32(R_AX_RSV_CTRL) & ~B_AX_R_DIS_PRST;
MAC_REG_W32(R_AX_RSV_CTRL, val32);
}
val32 = MAC_REG_R32(R_AX_IC_PWR_STATE);
val32 = GET_FIELD(val32, B_AX_WLMAC_PWR_STE);
if (val32 == MAC_AX_MAC_OFF && on == MAC_AX_MAC_OFF) {
PLTFM_MSG_WARN("MAC has already powered off\n");
return MACSUCCESS;
}
intf_pwr_switch = adapter->mac_pwr_info.intf_pwr_switch;
if (!intf_pwr_switch) {
PLTFM_MSG_ERR("interface power switch func is NULL\n");
ret = MACNPTR;
return ret;
}
if (on) {
pwr_seq = adapter->hw_info->pwr_on_seq;
pwr_func = adapter->hw_info->pwr_on;
} else {
pwr_seq = adapter->hw_info->pwr_off_seq;
pwr_func = adapter->hw_info->pwr_off;
adapter->sm.pwr = MAC_AX_PWR_PRE_OFF;
adapter->sm.dmac_func = MAC_AX_FUNC_OFF;
adapter->sm.cmac0_func = MAC_AX_FUNC_OFF;
adapter->sm.cmac1_func = MAC_AX_FUNC_OFF;
adapter->sm.bb0_func = MAC_AX_FUNC_OFF;
adapter->sm.bb1_func = MAC_AX_FUNC_OFF;
adapter->sm.plat = MAC_AX_PLAT_OFF;
}
ret = intf_pwr_switch(adapter, PWR_PRE_SWITCH, on);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("interface pre pwr switch fails %d\n", ret);
goto END;
}
if (on) {
ret = _patch_aon_int_leave_lps(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("AON interrupt leave LPS fail %X\n", ret);
goto END;
}
val32 = MAC_REG_R32(R_AX_IC_PWR_STATE);
val32 = GET_FIELD(val32, B_AX_WLMAC_PWR_STE);
if (val32 == MAC_AX_MAC_ON) {
PLTFM_MSG_WARN("MAC has already powered on %d\n", val32);
ret = MACALRDYON;
goto END;
} else if (val32 == MAC_AX_MAC_LPS) {
PLTFM_MSG_ERR("MAC leave LPS fail %d\n", val32);
ret = MACPWRSTAT;
goto END;
}
}
if (!pwr_func) {
ret = pwr_seq_start(adapter, pwr_seq);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr seq start %d\n", ret);
adapter->sm.pwr = MAC_AX_PWR_ERR;
goto END;
}
} else {
ret = pwr_func(adapter);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("[ERR]pwr func %d\n", ret);
adapter->sm.pwr = MAC_AX_PWR_ERR;
goto END;
}
}
ret = intf_pwr_switch(adapter, PWR_POST_SWITCH, on);
if (ret != MACSUCCESS) {
PLTFM_MSG_ERR("interface post pwr switch fails %d\n", ret);
adapter->sm.pwr = MAC_AX_PWR_ERR;
goto END;
}
mac_ax_init_state(adapter);
if (on) {
adapter->sm.pwr = MAC_AX_PWR_ON;
adapter->sm.plat = MAC_AX_PLAT_ON;
adapter->sm.io_st = MAC_AX_IO_ST_NORM;
adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE;
adapter->sm.l2_st = MAC_AX_L2_DIS;
adapter->mac_pwr_info.pwr_in_lps = 0;
/* patch form BT BG/LDO issue, ONLY FOR 52B CAV */
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
is_cv(adapter, CAV))
MAC_REG_W32(R_AX_SCOREBOARD,
(u32)(MAC_AX_NOTIFY_TP_MAJOR <<
MAC_AX_NOTIFY_SH));
} else {
adapter->sm.pwr = MAC_AX_PWR_OFF;
adapter->sm.l2_st = MAC_AX_L2_DIS;
/* patch form BT BG/LDO issue, ONLY FOR 52B CAV */
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) &&
is_cv(adapter, CAV))
MAC_REG_W32(R_AX_SCOREBOARD,
(u32)(MAC_AX_NOTIFY_PWR_MAJOR <<
MAC_AX_NOTIFY_SH));
}
END:
if (on)
clr_aon_int(adapter);
ret_end = intf_pwr_switch(adapter, PWR_END_SWITCH, on);
if (ret_end != MACSUCCESS) {
PLTFM_MSG_ERR("interface end pwr switch fails %d\n", ret_end);
adapter->sm.pwr = MAC_AX_PWR_ERR;
return ret_end;
}
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/pwr.c
|
C
|
agpl-3.0
| 9,550
|
/** @file */
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _MAC_AX_PWR_H_
#define _MAC_AX_PWR_H_
#include "../type.h"
#include "init.h"
/**
* Power switch command description
* @PWR_CMD_WRITE:
* @PWR_CMD_POLL:
* @PWR_CMD_DELAY:
* @PWR_CMD_END:
*/
#define PWR_CMD_WRITE 0
#define PWR_CMD_POLL 1
#define PWR_CMD_DELAY 2
#define PWR_CMD_END 3
#define PWR_CAV_MSK BIT(0)
#define PWR_CBV_MSK BIT(1)
#define PWR_CCV_MSK BIT(2)
#define PWR_CDV_MSK BIT(3)
#define PWR_CEV_MSK BIT(4)
#define PWR_CFV_MSK BIT(5)
#define PWR_CGV_MSK BIT(6)
#define PWR_CTV_MSK BIT(7)
#define PWR_CVALL_MSK 0xFF
#define PWR_INTF_MSK_SDIO BIT(0)
#define PWR_INTF_MSK_USB2 BIT(1)
#define PWR_INTF_MSK_USB3 BIT(2)
#define PWR_INTF_MSK_USB (PWR_INTF_MSK_USB3 | PWR_INTF_MSK_USB2)
#define PWR_INTF_MSK_PCIE BIT(3)
#define PWR_INTF_MSK_ALL 0xF
#define PWR_BASE_MAC 0
#define PWR_BASE_USB 1
#define PWR_BASE_PCIE 2
#define PWR_DELAY_US 0
#define PWR_DELAY_MS 1
#define PWR_POLL_CNT 2000
#define PWR_POLL_DLY_US 1000
#define LPS_LEAVE_GPIO 10
#define LPS_POLL_CNT 10000
#define LPS_POLL_DLY_US 50
#define PWR_POST_SWITCH 0
#define PWR_PRE_SWITCH 1
#define PWR_END_SWITCH 2
/**
* @struct mac_pwr_cfg
* @brief mac_pwr_cfg
*
* @var mac_pwr_cfg::addr
* Please Place Description here.
* @var mac_pwr_cfg::cut_msk
* Please Place Description here.
* @var mac_pwr_cfg::intf_msk
* Please Place Description here.
* @var mac_pwr_cfg::base
* Please Place Description here.
* @var mac_pwr_cfg::cmd
* Please Place Description here.
* @var mac_pwr_cfg::msk
* Please Place Description here.
* @var mac_pwr_cfg::val
* Please Place Description here.
*/
struct mac_pwr_cfg {
u16 addr;
u8 cut_msk;
u8 intf_msk;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 val;
};
/**
* @brief pwr_seq_start
*
* @param *adapter
* @param **seq
* @return Please Place Description here.
* @retval u32
*/
u32 pwr_seq_start(struct mac_ax_adapter *adapter, struct mac_pwr_cfg **seq);
/**
* @brief mac_pwr_switch
*
* @param *adapter
* @param on
* @return Please Place Description here.
* @retval u32
*/
u32 mac_pwr_switch(struct mac_ax_adapter *adapter, u8 on);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/mac/mac_ax/pwr.h
|
C
|
agpl-3.0
| 2,794
|