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/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EX_H__
#define __HALBB_EX_H__
#include "halbb_ic_hw_info.h"
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum halbb_pause_type {
HALBB_PAUSE = 1, /*Pause & Set new value*/
HALBB_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/
HALBB_RESUME = 3,
HALBB_RESUME_NO_RECOVERY = 4,
};
enum halbb_pause_lv_type {
HALBB_PAUSE_RELEASE = -1,
HALBB_PAUSE_LV_0 = 0, /* @Low Priority function */
HALBB_PAUSE_LV_1 = 1, /* @Middle Priority function */
HALBB_PAUSE_LV_2 = 2, /* @High priority function (ex: Check hang function) */
HALBB_PAUSE_LV_3 = 3, /* @Debug function (the highest priority) */
HALBB_PAUSE_MAX_NUM = 4
};
enum halbb_pause_rpt {
PAUSE_FAIL = 0,
PAUSE_SUCCESS = 1
};
/*---[BB Components]---*/
enum habb_fun_t {
F_RA = 0,
F_FA_CNT = 1,
HALBB_FUN_RSVD_2 = 2,
F_DFS = 3,
F_EDCCA = 4,
F_ENV_MNTR = 5,
F_CFO_TRK = 6,
F_PWR_CTRL = 7,
F_RUA_TBL = 8,
F_AUTO_DBG = 9,
F_ANT_DIV = 10,
F_DIG = 11,
F_DCR = 31,
F_DEFAULT = 0xff
};
enum bb_watchdog_mode_t {
BB_WATCHDOG_NORMAL = 0,
BB_WATCHDOG_LOW_IO = 1,
BB_WATCHDOG_NON_IO = 2,
};
struct halbb_func_info {
char name[16];
u8 id;
};
static const struct halbb_func_info halbb_func_i[] = {
{"ra", F_RA}, /*@do not move this element to other position*/
{"fa_cnt", F_FA_CNT}, /*@do not move this element to other position*/
{"rsvd2", HALBB_FUN_RSVD_2},
{"dfs", F_DFS},
{"edcca", F_EDCCA},
{"env_mntr", F_ENV_MNTR},
{"cfo_trk", F_CFO_TRK},
{"pwr_ctrl", F_PWR_CTRL},
{"rua_tbl", F_RUA_TBL},
{"auto_dbg", F_AUTO_DBG},
{"ant_div", F_ANT_DIV},
{"dig", F_DIG},
};
/*@=[HALBB supportability]=======================================*/
enum habb_supportability_t {
BB_RA = BIT(F_RA),
BB_FA_CNT = BIT(F_FA_CNT),
BB_FUN_RSVD_2 = BIT(HALBB_FUN_RSVD_2),
BB_DFS = BIT(F_DFS),
BB_EDCCA = BIT(F_EDCCA),
BB_ENVMNTR = BIT(F_ENV_MNTR),
BB_CFO_TRK = BIT(F_CFO_TRK),
BB_PWR_CTRL = BIT(F_PWR_CTRL),
BB_RUA_TBL = BIT(F_RUA_TBL),
BB_AUTO_DBG = BIT(F_AUTO_DBG),
BB_ANT_DIV = BIT(F_ANT_DIV),
BB_DIG = BIT(F_DIG),
BB_DCR = BIT(F_DCR)
};
/*@=[HALBB Debug Component]=====================================*/
enum halbb_dbg_comp_t {
/*=== [DM Part] ==========================*/
DBG_RA = BIT(F_RA),
DBG_FA_CNT = BIT(F_FA_CNT),
DBG_HALBB_FUN_RSVD_2 = BIT(HALBB_FUN_RSVD_2),
DBG_DFS = BIT(F_DFS),
DBG_EDCCA = BIT(F_EDCCA),
DBG_ENV_MNTR = BIT(F_ENV_MNTR),
DBG_CFO_TRK = BIT(F_CFO_TRK),
DBG_PWR_CTRL = BIT(F_PWR_CTRL),
DBG_RUA_TBL = BIT(F_RUA_TBL),
DBG_AUTO_DBG = BIT(F_AUTO_DBG),
DBG_ANT_DIV = BIT(F_ANT_DIV),
DBG_DIG = BIT(F_DIG),
/*=== [Non-DM Part] ======================*/
DBG_BIT12 = BIT(12),
DBG_BIT13 = BIT(13),
DBG_BIT14 = BIT(14),
DBG_BIT15 = BIT(15),
DBG_BIT16 = BIT(16),
DBG_BIT17 = BIT(17),
DBG_BIT18 = BIT(18),
DBG_BIT19 = BIT(19),
DBG_PHY_STS = BIT(20),
DBG_BIT21 = BIT(21),
DBG_FW_INFO = BIT(22),
DBG_COMMON_FLOW = BIT(23),
DBG_IC_API = BIT(24),
DBG_DBG_API = BIT(25),
DBG_DBCC = BIT(26),
DBG_DM_SUMMARY = BIT(27),
DBG_PHY_CONFIG = BIT(28),
DBG_INIT = BIT(29),
DBG_CMN = BIT(30),
DBG_DCR = BIT(F_DCR)
};
/*@--------------------------[Structure]-------------------------------------*/
#if 0
/*For development use only, and will move to "struct rtw_rssi_info" in near furture*/
struct bb_rssi_info{
u8 rssi; /*avg RSSI among all RF path, dbm = RSSI - 110*/
u16 rssi_acc; /*U(16,4) version of rssi*/
u8 rssi_cck; /*instance value of CCK RSSI*/
u8 rssi_ofdm; /*instance value of OFDM RSSI*/
};
#endif
struct bb_sta_info {
u8 sta_status_tmp;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
bool halbb_sta_info_init(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info);
bool halbb_sta_info_deinit(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info);
bool halbb_sta_info_add_entry(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_info);
bool halbb_sta_info_delete_entry(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info);
void halbb_media_status_update(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info,
bool is_connected);
void halbb_watchdog_reset(struct bb_info *bb);
void halbb_watchdog(struct bb_info *bb, enum bb_watchdog_mode_t mode,
enum phl_phy_idx phy_idx);
void halbb_bb_cmd_notify(struct bb_info *bb, void *bb_cmd, enum phl_phy_idx phy_idx);
u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func,
enum halbb_pause_type pause_type,
enum halbb_pause_lv_type lv,
u8 val_lehgth,
u32 *val_buf);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ex.h
|
C
|
agpl-3.0
| 5,670
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EXPORT_FUN_H__
#define __HALBB_EXPORT_FUN_H__
#include "halbb_cfg_ic.h"
#include "halbb_hw_cfg_ex.h"
#include "halbb_init_ex.h"
#include "halbb_ex.h"
#include "halbb_dbg_cmd_ex.h"
#include "halbb_physts_ex.h"
#include "halbb_api_ex.h"
#include "halbb_interface_ex.h"
#include "halbb_dfs_ex.h"
#include "halbb_dig_ex.h"
#include "halbb_mp_ex.h"
#include "halbb_plcp_tx_ex.h"
#include "halbb_pmac_setting_ex.h"
#include "halbb_la_mode_ex.h"
#include "halbb_ra_ex.h"
#include "halbb_cmn_rpt_ex.h"
#include "halbb_ch_info_ex.h"
#include "halbb_math_lib_ex.h"
#include "halbb_edcca_ex.h"
#include "halbb_dbcc_ex.h"
#include "halbb_rua_tbl_ex.h"
#include "halbb_env_mntr_ex.h"
#include "halbb_pwr_ctrl_ex.h"
#include "halbb_dyn_csi_rsp_ex.h"
#ifdef BB_8852A_CAV_SUPPORT
#include "halbb_8852a/halbb_8852a_api_ex.h"
#endif
#ifdef BB_8852A_2_SUPPORT
#include "halbb_8852a_2/halbb_8852a_2_api_ex.h"
#endif
#ifdef BB_8852B_SUPPORT
#include "halbb_8852b/halbb_8852b_api_ex.h"
#endif
#ifdef BB_8852C_SUPPORT
#include "halbb_8852c/halbb_8852c_api_ex.h"
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_export_fun.h
|
C
|
agpl-3.0
| 2,042
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_FEATURES_H__
#define __HALBB_FEATURES_H__
#include "../../hal_headers_le.h"
#include "halbb_cfg_ic.h"
#include "halbb_ic_hw_info.h"
/*[Control by Outer Driver]--------------------------------------------------*/
#ifndef DRV_BB_TIMER_SUPPORT_DISABLE
#define HALBB_TIMER_SUPPORT
#endif
#ifndef DRV_BB_DBG_TRACE_DISABLE
#define HALBB_DBG_TRACE_SUPPORT
#endif
#ifndef DRV_BB_PHYSTS_PARSING_DISABLE
#define HALBB_PHYSTS_PARSING_SUPPORT
#endif
#ifndef DRV_BB_ENV_MNTR_DISABLE
#define HALBB_ENV_MNTR_SUPPORT
#define CLM_SUPPORT
#define NHM_SUPPORT
#define IFS_CLM_SUPPORT
#define FAHM_SUPPORT
#define EDCCA_CLM_SUPPORT
#endif
#ifndef DRV_BB_STATISTICS_DISABLE
#define HALBB_STATISTICS_SUPPORT
#endif
#ifndef DRV_BB_RA_DISABLE
#define HALBB_RA_SUPPORT
#endif
#ifndef DRV_BB_ADPTVTY_DISABLE
#define HALBB_EDCCA_SUPPORT
#endif
#ifndef DRV_BB_DFS_DISABLE
#define HALBB_DFS_SUPPORT
#endif
#ifndef DRV_BB_CFO_TRK_DISABLE
#define HALBB_CFO_TRK_SUPPORT
//#define BB_DYN_CFO_TRK_LOP
#endif
#ifndef DRV_BB_DIG_DISABLE
#define HALBB_DIG_SUPPORT
#ifndef DRV_BB_TDMADIG_DISABLE
#define HALBB_DIG_TDMA_SUPPORT
#endif
#ifndef DRV_BB_DIG_MCC_DISABLE
#define HALBB_DIG_MCC_SUPPORT
#define HALBB_DIG_MCC_SUPPORT_IC (BB_RTL8852A | BB_RTL8852B)
#endif
#define HALBB_DIG_DAMPING_CHK
#endif
#ifndef DRV_BB_LA_MODE_DISABLE
#define HALBB_LA_MODE_SUPPORT
#endif
#ifndef DRV_BB_PSD_DISABLE
#define HALBB_PSD_SUPPORT
#endif
#ifndef DRV_BB_PWR_CTRL_DISABLE
#define HALBB_PWR_CTRL_SUPPORT
#endif
#ifndef DRV_BB_RUA_DISABLE
#define HALBB_RUA_SUPPORT
#endif
#ifndef DRV_BB_PMAC_TX_DISABLE
#define HALBB_PMAC_TX_SUPPORT
#endif
#ifndef DRV_BB_CH_INFO_DISABLE
#define HALBB_CH_INFO_SUPPORT
#ifndef DRV_BB_DYN_CSI_RSP_DISABLE
#define HALBB_DYN_CSI_RSP_SUPPORT
#endif
#endif
#ifndef DRV_BB_AUTO_DBG_DISABLE
#define HALBB_AUTO_DBG_SUPPORT
#endif
#if 0
#define HALBB_ANT_DIV_SUPPORT
#endif
#ifndef DRV_BB_DYN_L2H_DISABLE
#define HALBB_DYN_L2H_SUPPORT
#endif
/*[DBCC]*/
#if (defined(CONFIG_DBCC_SUPPORT) && defined(HALBB_COMPILE_IC_DBCC))
#define HALBB_DBCC_SUPPORT
#define HALBB_DBCC_DVLP_FLAG
#endif
/*[FW OFFLOAD]*/
#if (defined(CONFIG_FW_IO_OFLD_SUPPORT) && defined(HALBB_COMPILE_IC_FWOFLD))
#define HALBB_FW_OFLD_SUPPORT
#endif
#define HALBB_TDMA_CR_SUPPORT
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_features.h
|
C
|
agpl-3.0
| 3,254
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_FW_OFLD_SUPPORT
bool halbb_check_fw_ofld(struct bb_info *bb)
{
bool ret = bb->phl_com->dev_cap.fw_cap.offload_cap & BIT0;
BB_DBG(bb, DBG_FW_INFO, "FW ofld ret = %d\n", (u8)ret);
return ret;
}
bool halbb_fw_delay(struct bb_info *bb, u32 val)
{
/* halbb_set_reg */
struct rtw_mac_cmd cmd;
u32 ret;
cmd.type = RTW_MAC_DELAY_OFLD;
cmd.lc = 0;
cmd.value = val; /*delay us*/
ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd);
BB_DBG(bb, DBG_FW_INFO, "FW ofld delay:%x\n", val);
if (ret) {
BB_WARNING("IO offload fail: %d\n", ret);
return false;
}
else {
return true;
}
}
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc)
{
/* halbb_set_reg */
struct rtw_mac_cmd cmd;
u32 ret;
cmd.src = RTW_MAC_BB_CMD_OFLD;
cmd.type = RTW_MAC_WRITE_OFLD;
cmd.lc = lc;
cmd.offset = (u16)addr;
cmd.value = val;
cmd.mask = mask;
ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd);
BB_DBG(bb, DBG_FW_INFO, "FW ofld addr:%x, val:%x, msk:%x\n", addr, val, mask);
if (ret) {
BB_WARNING("IO offload fail: %d\n", ret);
return false;
}
else {
return true;
}
}
bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr,
u32 mask, u32 val, enum phl_phy_idx phy_idx, u8 lc)
{
bool ret = true;
u32 val_mod = val;
#ifdef HALBB_DBCC_SUPPORT
if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1)
addr += halbb_phy0_to_phy1_ofst(bb, addr);
#endif
ret = halbb_fw_set_reg(bb, addr, mask, val_mod, lc);
return ret;
}
bool halbb_fwcfg_bb_phy_8852a_2(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DBCC_SUPPORT
u32 ofst = 0;
#endif
bool ret = true;
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else {
#ifdef HALBB_DBCC_SUPPORT
if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) &&
phy_idx == HW_PHY_1) {
ofst = halbb_phy0_to_phy1_ofst(bb, addr);
if (ofst == 0)
return true;
addr += ofst;
} else {
phy_idx = HW_PHY_0;
}
#endif
/*FWOFLD in init BB reg flow */
if (halbb_check_fw_ofld(bb)) {
ret &= halbb_fw_set_reg(bb, addr, MASKDWORD, data, 0);
BB_DBG(bb, DBG_INIT, "[REG FWOFLD]0x%04X = 0x%08X, ret = %d\n", addr, data, (u8)ret);
}
else {
halbb_set_reg(bb, addr, MASKDWORD, data);
#ifdef HALBB_DBCC_SUPPORT
BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data);
#else
BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data);
#endif
}
}
return ret;
}
bool halbb_fwofld_cck_en_8852a_2(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx)
{
bool ret = true;
if (cck_en) {
ret &= halbb_fw_set_reg(bb, 0x2344, BIT(31), 0, 0);
} else {
ret &= halbb_fw_set_reg(bb, 0x2344, BIT(31), 1, 0);
}
BB_DBG(bb, DBG_PHY_CONFIG, "[CCK Enable for PHY%d]\n", phy_idx);
return ret;
}
bool halbb_fwofld_btg_8852a_2(struct bb_info *bb, bool btg)
{
struct rtw_phl_com_t *phl = bb->phl_com;
struct dev_cap_t *dev = &phl->dev_cap;
bool ret = true;
if (dev->rfe_type >= 50)
return true;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (btg) {
// Path A
ret &= halbb_fw_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x1, 0);
// Path B
ret &= halbb_fw_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x3, 0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply BTG Setting\n");
// Apply Grant BT by TMAC Setting
ret &= halbb_fw_set_reg(bb, 0x980, 0x1e0000, 0x0, 0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Apply Grant BT by TMAC Setting\n");
// Add BT share
ret &= halbb_fw_set_reg(bb, 0x4978, BIT(14), 0x1, 0);
ret &= halbb_fw_set_reg(bb, 0x4974, 0x3c00000, 0x2, 0);
ret &= halbb_fw_set_reg(bb, 0x441c, BIT(31), 0x1, 0);
} else {
// Path A
ret &= halbb_fw_set_reg(bb, 0x466c, BIT(18) | BIT(17), 0x0, 0);
// Path B
ret &= halbb_fw_set_reg(bb, 0x4740, BIT(18) | BIT(17), 0x0, 0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Disable BTG Setting\n");
// Ignore Grant BT by PMAC Setting
ret &= halbb_fw_set_reg(bb, 0x980, 0x1e0000, 0xf, 0);
ret &= halbb_fw_set_reg(bb, 0x980, 0x3c000000, 0x4, 0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] Ignore Grant BT by PMAC Setting\n");
// Reset BT share
ret &= halbb_fw_set_reg(bb, 0x4978, BIT(14), 0x0, 0);
ret &= halbb_fw_set_reg(bb, 0x4974, 0x3c00000, 0x0, 0);
ret &= halbb_fw_set_reg(bb, 0x441c, BIT(31), 0x0, 0);
}
return ret;
}
bool halbb_fw_5m_mask_8852a_2(struct bb_info *bb, u8 pri_ch, enum channel_width bw)
{
bool mask_5m_low = false;
bool mask_5m_en = false;
bool ret = true;
switch (bw) {
case CHANNEL_WIDTH_40:
/* Prich=1 : Mask 5M High
Prich=2 : Mask 5M Low */
mask_5m_en = true;
mask_5m_low = pri_ch == 2 ? true : false;
break;
case CHANNEL_WIDTH_80:
/* Prich=3 : Mask 5M High
Prich=4 : Mask 5M Low
Else : Mask 5M Disable */
mask_5m_en = ((pri_ch == 3) || (pri_ch == 4)) ? true : false;
mask_5m_low = pri_ch == 4 ? true : false;
break;
default:
mask_5m_en = false;
break;
}
BB_DBG(bb, DBG_PHY_CONFIG, "[5M Mask] pri_ch = %d, bw = %d", pri_ch, bw);
if (!mask_5m_en) {
ret &= halbb_fw_set_reg(bb, 0x46b0, BIT(12), 0x0, 0);
ret &= halbb_fw_set_reg(bb, 0x4784, BIT(12), 0x0, 0);
} else {
if (mask_5m_low) {
ret &= halbb_fw_set_reg(bb, 0x46b0, 0x3f, 0x4, 0);
ret &= halbb_fw_set_reg(bb, 0x46b0, BIT(12) | BIT(8) | BIT(6), 0x5, 0);
ret &= halbb_fw_set_reg(bb, 0x4784, 0x3f, 0x4, 0);
ret &= halbb_fw_set_reg(bb, 0x4784, BIT(12) | BIT(8) | BIT(6), 0x5, 0);
} else {
ret &= halbb_fw_set_reg(bb, 0x46b0, 0x3f, 0x4, 0);
ret &= halbb_fw_set_reg(bb, 0x46b0, BIT(12) | BIT(8) | BIT(6), 0x6, 0);
ret &= halbb_fw_set_reg(bb, 0x4784, 0x3f, 0x4, 0);
ret &= halbb_fw_set_reg(bb, 0x4784, BIT(12) | BIT(8) | BIT(6), 0x6, 0);
}
}
return ret;
}
bool halbb_fw_set_rf_reg_8852a_2(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data, u8 lc)
{
/* halbb_write_rf_reg_8852a_2 */
bool ret = true;
u32 direct_addr = 0;
u32 offset_write_rf[2] = {0xc000, 0xd000};
/*==== Error handling ====*/
if (path > RF_PATH_B) {
BB_WARNING("[%s] Unsupported path (%d)\n", __func__, path);
return false;
}
/*==== Calculate offset ====*/
reg_addr &= 0xff;
direct_addr = offset_write_rf[path] + (reg_addr << 2);
/*==== RF register only has 20bits ====*/
bit_mask &= RFREGOFFSETMASK;
halbb_fw_delay(bb, 1);
/*==== Write RF register directly ====*/
ret = halbb_fw_set_reg(bb, direct_addr, bit_mask, data, lc);
/*halbb_delay_us(bb, 1);*/
halbb_fw_delay(bb, 1);
BB_DBG(bb, DBG_FW_INFO, "FW OFLD RF-%d 0x%x = 0x%x , bit mask = 0x%x, ret = %d\n",
path, reg_addr, data, bit_mask, (u8)ret);
return ret;
}
bool halbb_fw_set_efuse_8852a_2(struct bb_info *bb, u8 central_ch, enum rf_path path, enum phl_phy_idx phy_idx)
{
u8 band;
bool ret = true;
u8 upper_bound = 60; // S(7,4): 3.75
u8 lower_bound = 64; // S(7,4): -4
s32 hidden_efuse = 0, normal_efuse = 0, normal_efuse_cck = 0;
s32 tmp = 0;
u32 efuse_5g[BB_PATH_MAX_8852A] = {0x4624, 0x46f8};
u32 efuse_5g_mask = 0x07e00000;
u32 efuse_2g[BB_PATH_MAX_8852A] = {0x4628, 0x46fc};
u32 efuse_2g_mask = 0x0000003f;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// 2G Band: (0)
// 5G Band: (1):Low, (2): Mid, (3):High
if (central_ch >= 0 && central_ch <= 14)
band = 0;
else if (central_ch >= 36 && central_ch <= 64)
band = 1;
else if (central_ch >= 100 && central_ch <= 144)
band = 2;
else if (central_ch >= 149 && central_ch <= 177)
band = 3;
else
band = 0;
// === [Set hidden efuse] === //
if (bb->bb_efuse_i.hidden_efuse_check) {
for (path = RF_PATH_A; path < BB_PATH_MAX_8852A; path++) {
if (central_ch >= 0 && central_ch <= 14) {
hidden_efuse = (bb->bb_efuse_i.gain_cg[path][band] << 2);
ret &= halbb_fw_set_reg(bb, efuse_2g[path], efuse_2g_mask, (hidden_efuse & 0x3f), 0);
} else {
hidden_efuse = (bb->bb_efuse_i.gain_cg[path][band] << 2);
ret &= halbb_fw_set_reg(bb, efuse_5g[path], efuse_5g_mask, (hidden_efuse & 0x3f), 0);
}
}
BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Hidden efuse dynamic setting!!\n");
} else {
BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Values of hidden efuse are all 0xff, bypass dynamic setting!!\n");
}
// === [Set normal efuse] === //
if (bb->bb_efuse_i.normal_efuse_check) {
if ((bb->rx_path == RF_PATH_A) || (bb->rx_path == RF_PATH_AB)) {
normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_A][band + 1];
normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_A][0];
} else if (bb->rx_path == RF_PATH_B) {
normal_efuse = bb->bb_efuse_i.gain_offset[RF_PATH_B][band + 1];
normal_efuse_cck = bb->bb_efuse_i.gain_offset[RF_PATH_B][0];
}
normal_efuse *= (-1);
normal_efuse_cck *= (-1);
// OFDM normal efuse
if (normal_efuse > 3) {
tmp = (normal_efuse << 4) + (bb->bb_efuse_i.efuse_ofst << 2) - upper_bound;
ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, ((tmp >> 2) & 0x1f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0xfe00000, (tmp & 0x7f), phy_idx, 0);
// Set efuse
ret &= halbb_fw_set_reg_cmn(bb, 0x4960, 0xfe00000, (upper_bound & 0x7f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x7f, (upper_bound & 0x7f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x3f80, (upper_bound & 0x7f), phy_idx, 0);
} else if (normal_efuse < -4) {
tmp = (normal_efuse << 4) + (bb->bb_efuse_i.efuse_ofst << 2) + lower_bound;
// r_1_rpl_bias_comp
ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, ((tmp >> 2) & 0x1f), phy_idx, 0);
// r_tb_rssi_bias_comp
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0xfe00000, (tmp & 0x7f), phy_idx, 0);
// Set efuse
ret &= halbb_fw_set_reg_cmn(bb, 0x4960, 0xfe00000, (lower_bound & 0x7f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x7f, (lower_bound & 0x7f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x3f80, (lower_bound & 0x7f), phy_idx, 0);
} else {
ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, (bb->bb_efuse_i.efuse_ofst & 0x1f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0xfe00000, (bb->bb_efuse_i.efuse_ofst_tb & 0x7f), phy_idx, 0);
// Set efuse
ret &= halbb_fw_set_reg_cmn(bb, 0x4960, 0xfe00000, ((normal_efuse << 4) & 0x7f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x7f, ((normal_efuse << 4) & 0x7f), phy_idx, 0);
ret &= halbb_fw_set_reg_cmn(bb, 0x4964, 0x3f80, ((normal_efuse << 4) & 0x7f), phy_idx, 0);
}
// CCK normal efuse
if (band == 0) {
tmp = normal_efuse_cck << 3;
ret &= halbb_fw_set_reg(bb, 0x23ac, 0x7f, (tmp & 0x7f), 0);
}
BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Normal efuse dynamic setting!!\n");
} else {
BB_DBG(bb, DBG_INIT, "[Efuse][FWOFLD] Values of normal efuse are all 0xff, bypass dynamic setting!!\n");
}
return ret;
}
bool halbb_fw_set_gain_error_8852a_2(struct bb_info *bb, u8 central_ch)
{
bool ret = true;
u8 band;
u8 path = 0, lna_idx = 0, tia_idx = 0;
s32 tmp = 0;
u32 lna_err_a_5g[BB_PATH_MAX_8852A][7] = {{0x462c, 0x462c, 0x4630,
0x4634, 0x4634, 0x4638,
0x4638}, {0x4700, 0x4700,
0x4704, 0x4708, 0x4708,
0x470c, 0x470c}};
u32 lna_err_a_5g_mask[7] = {0x00000fc0, 0x3f000000, 0x0003f000,
0x0000003f, 0x00fc0000, 0x00000fc0,
0x3f000000};
u32 lna_err_a_2g[BB_PATH_MAX_8852A][7] = {{0x462c, 0x4630, 0x4630,
0x4634, 0x4634, 0x4638,
0x463c}, {0x4700, 0x4704,
0x4704, 0x4708, 0x4708,
0x470c, 0x4710}};
u32 lna_err_a_2g_mask[7] = {0x0003f000, 0x0000003f, 0x00fc0000,
0x00000fc0, 0x3f000000, 0x0003f000,
0x0000003f};
u32 tia_err_a_5g[BB_PATH_MAX_8852A][2] = {{0x4640, 0x4644}, {0x4714,
0x4718}};
u32 tia_err_a_5g_mask[2] = {0x0003f000, 0x0000003f};
u32 tia_err_a_2g[BB_PATH_MAX_8852A][2] = {{0x4640, 0x4644}, {0x4714,
0x4718}};
u32 tia_err_a_2g_mask[2] = {0x00fc0000, 0x00000fc0};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// 2G Band: (0)
// 5G Band: (1):Low, (2): Mid, (3):High
if (central_ch >= 0 && central_ch <= 14)
band = 0;
else if (central_ch >= 36 && central_ch <= 64)
band = 1;
else if (central_ch >= 100 && central_ch <= 144)
band = 2;
else if (central_ch >= 149 && central_ch <= 177)
band = 3;
else
band = 0;
if (central_ch >= 0 && central_ch <= 14) {
for (path = RF_PATH_A; path < BB_PATH_MAX_8852A; path++) {
// Set 2G LNA Gain Err
for (lna_idx = 0; lna_idx < 7; lna_idx++) {
tmp = bb->bb_gain_i.lna_gain[band][path][lna_idx];
ret &= halbb_fw_set_reg(bb, lna_err_a_2g[path][lna_idx],
lna_err_a_2g_mask[lna_idx], (tmp & 0x3f), 0);
}
// Set 2G TIA Gain Err
for (tia_idx = 0; tia_idx < 2; tia_idx++) {
tmp = bb->bb_gain_i.tia_gain[band][path][tia_idx];
ret &= halbb_fw_set_reg(bb, tia_err_a_2g[path][tia_idx],
tia_err_a_2g_mask[tia_idx], (tmp & 0x3f), 0);
}
}
} else {
for (path = RF_PATH_A; path < BB_PATH_MAX_8852A; path++) {
// Set 5G LNA Gain Err
for (lna_idx = 0; lna_idx < 7; lna_idx++) {
tmp = bb->bb_gain_i.lna_gain[band][path][lna_idx];
ret &= halbb_fw_set_reg(bb, lna_err_a_5g[path][lna_idx],
lna_err_a_5g_mask[lna_idx], (tmp & 0x3f), 0);
}
// Set 5G TIA Gain Err
for (tia_idx = 0; tia_idx < 2; tia_idx++) {
tmp = bb->bb_gain_i.tia_gain[band][path][tia_idx];
ret &= halbb_fw_set_reg(bb, tia_err_a_5g[path][tia_idx],
tia_err_a_5g_mask[tia_idx], (tmp & 0x3f), 0);
}
}
}
return ret;
}
bool halbb_fwofld_sco_cck_8852a_2(struct bb_info *bb, u8 pri_ch)
{
u32 sco_barker_threshold[14] = {0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd,
0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
0x1d79c, 0x1d892, 0x1d988, 0x1da7f,
0x1db75, 0x1ddc4};
u32 sco_cck_threshold[14] = {0x27de3, 0x27f35, 0x28088, 0x281da,
0x2832d, 0x2847f, 0x285d2, 0x28724,
0x28877, 0x289c9, 0x28b1c, 0x28c6e,
0x28dc1, 0x290ed};
bool rpt = true;
if (pri_ch > 14) {
BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Fail]");
/*Return true because its not FW offload fail*/
return true;
}
rpt &= halbb_fw_set_reg(bb, 0x23b0, 0x7ffff, sco_barker_threshold[pri_ch - 1], 0);
rpt &= halbb_fw_set_reg(bb, 0x23b4, 0x7ffff, sco_cck_threshold[pri_ch - 1], 0);
BB_DBG(bb, DBG_PHY_CONFIG, "[CCK SCO Success]");
return rpt;
}
bool halbb_fwofld_rf_ch_8852a_2(struct bb_info *bb, u8 central_ch, enum rf_path path,
bool *is_2g_ch, u32 *rf_reg18)
{
//u32 rf_reg18 = 0;
bool ret = true;
/*rf_reg18 = halbb_read_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK);*/
/*==== [Error handling] ====*/
if (*rf_reg18 == INVALID_RF_DATA) {
BB_WARNING("Invalid RF_0x18 for Path-%d\n", path);
return false;
}
*is_2g_ch = (central_ch <= 14) ? true : false;
/*==== [Set RF Reg 0x18] ====*/
*rf_reg18 &= ~0x303ff; /*[17:16],[9:8],[7:0]*/
*rf_reg18 |= central_ch; /* Channel*/
/*==== [5G Setting] ====*/
if (!*is_2g_ch)
*rf_reg18 |= (BIT(16) | BIT(8));
/*ret &= halbb_fw_set_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK, *rf_reg18);*/
BB_DBG(bb, DBG_PHY_CONFIG, "[Success][ch_setting] CH: %d for Path-%d\n",
central_ch, path);
return ret;
}
bool halbb_fwofld_ch_8852a_2(struct bb_info *bb, u8 central_ch,
enum phl_phy_idx phy_idx, u32 *path0_rf18, u32 *path1_rf18)
{
u8 sco_comp;
bool is_2g_ch = false;
bool ret = true;
if (bb->is_disable_phy_api) {
BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__);
return true;
}
/*==== Error handling ====*/
if ((central_ch > 14 && central_ch < 36) ||
(central_ch > 64 && central_ch < 100) ||
(central_ch > 144 && central_ch < 149) ||
central_ch > 177 ) {
BB_WARNING("Invalid CH:%d for PHY%d\n", central_ch,
phy_idx);
return false;
}
if (phy_idx == HW_PHY_0) {
/*============== [Path A] ==============*/
ret &= halbb_fwofld_rf_ch_8852a_2(bb, central_ch, RF_PATH_A, &is_2g_ch, path0_rf18);
//------------- [Mode Sel - Path A] ------------//
if (is_2g_ch)
ret &= halbb_fw_set_reg_cmn(bb, 0x4644, BIT(31) | BIT(30), 1,
phy_idx, 0);
else
ret &= halbb_fw_set_reg_cmn(bb, 0x4644, BIT(31) | BIT(30), 0,
phy_idx, 0);
/*============== [Path B] ==============*/
if (!bb->hal_com->dbcc_en) {
ret &= halbb_fwofld_rf_ch_8852a_2(bb, central_ch, RF_PATH_B,
&is_2g_ch, path1_rf18);
//------------- [Mode Sel - Path B] ------------//
if (is_2g_ch)
ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30),
1, phy_idx, 0);
else
ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30),
0, phy_idx, 0);
} else { /*==== [Phy0 config at 2/5G] ====*/
if (is_2g_ch)
ret &= halbb_fw_set_reg(bb, 0x4970, BIT(1), 0, 0);
else
ret &= halbb_fw_set_reg(bb, 0x4970, BIT(1), 1, 0);
}
/*==== [SCO compensate fc setting] ====*/
sco_comp = halbb_sco_mapping_8852a_2(bb, central_ch);
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0x7f, sco_comp, phy_idx, 0);
} else {
/*============== [Path B] ==============*/
ret &= halbb_fwofld_rf_ch_8852a_2(bb, central_ch, RF_PATH_B, &is_2g_ch, path0_rf18);
//------------- [Mode Sel - Path B] ------------//
if (is_2g_ch)
ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30), 1,
phy_idx, 0);
else
ret &= halbb_fw_set_reg_cmn(bb, 0x4718, BIT(31) | BIT(30), 0,
phy_idx, 0);
/*==== [SCO compensate fc setting] ====*/
sco_comp = halbb_sco_mapping_8852a_2(bb, central_ch);
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0x7f, sco_comp, phy_idx, 0);
}
/* === Bandedge ===*/
if (is_2g_ch)
ret &= halbb_fw_set_reg_cmn(bb, 0x4498, BIT(30), 1, phy_idx, 0);
else
ret &= halbb_fw_set_reg_cmn(bb, 0x4498, BIT(30), 0, phy_idx, 0);
/* === CCK Parameters === */
if (central_ch == 14) {
ret &= halbb_fw_set_reg(bb, 0x2300, 0xffffff, 0x3b13ff, 0);
ret &= halbb_fw_set_reg(bb, 0x2304, 0xffffff, 0x1c42de, 0);
ret &= halbb_fw_set_reg(bb, 0x2308, 0xffffff, 0xfdb0ad, 0);
ret &= halbb_fw_set_reg(bb, 0x230c, 0xffffff, 0xf60f6e, 0);
ret &= halbb_fw_set_reg(bb, 0x2310, 0xffffff, 0xfd8f92, 0);
ret &= halbb_fw_set_reg(bb, 0x2314, 0xffffff, 0x2d011, 0);
ret &= halbb_fw_set_reg(bb, 0x2318, 0xffffff, 0x1c02c, 0);
ret &= halbb_fw_set_reg(bb, 0x231c, 0xffffff, 0xfff00a, 0);
} else {
ret &= halbb_fw_set_reg(bb, 0x2300, 0xffffff, 0x3d23ff, 0);
ret &= halbb_fw_set_reg(bb, 0x2304, 0xffffff, 0x29b354, 0);
ret &= halbb_fw_set_reg(bb, 0x2308, 0xffffff, 0xfc1c8, 0);
ret &= halbb_fw_set_reg(bb, 0x230c, 0xffffff, 0xfdb053, 0);
ret &= halbb_fw_set_reg(bb, 0x2310, 0xffffff, 0xf86f9a, 0);
ret &= halbb_fw_set_reg(bb, 0x2314, 0xffffff, 0xfaef92, 0);
ret &= halbb_fw_set_reg(bb, 0x2318, 0xffffff, 0xfe5fcc, 0);
ret &= halbb_fw_set_reg(bb, 0x231c, 0xffffff, 0xffdff5, 0);
}
/* === Set Gain Error === */
ret &= halbb_fw_set_gain_error_8852a_2(bb, central_ch);
/* === Set Efuse === */
ret &= halbb_fw_set_efuse_8852a_2(bb, central_ch, bb->rx_path, phy_idx);
/* === Set Ch idx report in phy-sts === */
/* write for last cmd*/
ret &= halbb_fw_set_reg_cmn(bb, 0x0734, 0x0ff0000, central_ch, phy_idx, 0);
BB_DBG(bb, DBG_PHY_CONFIG, "[Switch CH] CH: %d for PHY%d, ret = %d\n",
central_ch, phy_idx, (u8)ret);
return ret;
}
bool halbb_fw_bw_setting_8852a_2(struct bb_info *bb, enum channel_width bw,
enum rf_path path, u32 *rf_reg18)
{
bool ret = true;
/*u32 rf_reg18 = 0;*/
u32 adc_sel[2] = {0x12d0, 0x32d0};
u32 wbadc_sel[2] = {0x12ec, 0x32ec};
/*rf_reg18 = halbb_read_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK);*/
/*==== [Error handling] ====*/
if (*rf_reg18 == INVALID_RF_DATA) {
BB_WARNING("Invalid RF_0x18 for Path-%d\n", path);
return false;
}
*rf_reg18 &= ~(BIT(11) | BIT(10));
/*==== [Switch bandwidth] ====*/
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
if (bw == CHANNEL_WIDTH_5) {
/*ADC clock = 20M & WB ADC clock = 40M for BW5 */
ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x1, 0);
ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x0, 0);
} else if (bw == CHANNEL_WIDTH_10) {
/*ADC clock = 40M & WB ADC clock = 80M for BW10 */
ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x2, 0);
ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x1, 0);
} else if (bw == CHANNEL_WIDTH_20) {
/*ADC clock = 80M & WB ADC clock = 160M for BW20 */
ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x0, 0);
ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x2, 0);
}
/*RF bandwidth */
*rf_reg18 |= (BIT(11) | BIT(10));
break;
case CHANNEL_WIDTH_40:
/*ADC clock = 80M & WB ADC clock = 160M for BW40 */
ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x0, 0);
ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x2, 0);
/*RF bandwidth */
*rf_reg18 |= BIT(11);
break;
case CHANNEL_WIDTH_80:
/*ADC clock = 160M & WB ADC clock = 160M for BW40 */
ret &= halbb_fw_set_reg(bb, adc_sel[path], 0x6000, 0x0, 0);
ret &= halbb_fw_set_reg(bb, wbadc_sel[path], 0x30, 0x2, 0);
/*RF bandwidth */
*rf_reg18 |= BIT(10);
break;
default:
BB_WARNING("Fail to set ADC\n");
}
/*==== [Write RF register] ====*/
/*ret &= halbb_fw_set_rf_reg_8852a_2(bb, path, 0x18, RFREGOFFSETMASK, rf_reg18);*/
BB_DBG(bb, DBG_PHY_CONFIG,
"[bw_setting] ADC setting for Path-%d\n, ret = %d", path, (u8)ret);
return ret;
}
bool halbb_fwofld_bw_8852a_2(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx, u32 *path0_rf18, u32 *path1_rf18)
{
bool ret = true;
if (bb->is_disable_phy_api) {
BB_DBG(bb, DBG_PHY_CONFIG, "[%s] Disable PHY API\n", __func__);
return true;
}
/*==== Error handling ====*/
if (bw >= CHANNEL_WIDTH_MAX || (bw == CHANNEL_WIDTH_40 && pri_ch > 2) ||
(bw == CHANNEL_WIDTH_80 && pri_ch > 4)) {
BB_WARNING("Fail to switch bw(bw:%d, pri ch:%d)\n", bw,
pri_ch);
return true;
}
/*==== Switch bandwidth ====*/
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
if (bw == CHANNEL_WIDTH_5) {
/*RF_BW:[31:30]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x0,
phy_idx, 0);
/*small BW:[13:12]=0x1 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x1, phy_idx, 0);
/*Pri ch:[11:8]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, 0x0, phy_idx, 0);
} else if (bw == CHANNEL_WIDTH_10) {
/*RF_BW:[31:30]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x0,
phy_idx, 0);
/*small BW:[13:12]=0x2 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x2, phy_idx, 0);
/*Pri ch:[11:8]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, 0x0, phy_idx, 0);
} else if (bw == CHANNEL_WIDTH_20) {
/*RF_BW:[31:30]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x0,
phy_idx, 0);
/*small BW:[13:12]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x0, phy_idx, 0);
/*Pri ch:[11:8]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, 0x0, phy_idx, 0);
}
break;
case CHANNEL_WIDTH_40:
/*RF_BW:[31:30]=0x1 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x1, phy_idx, 0);
/*small BW:[13:12]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x0, phy_idx, 0);
/*Pri ch:[11:8] */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, pri_ch, phy_idx, 0);
/*CCK primary channel */
if (pri_ch == 1)
ret &= halbb_fw_set_reg(bb, 0x237c, BIT(0), 1, 0);
else
ret &= halbb_fw_set_reg(bb, 0x237c, BIT(0), 0, 0);
break;
case CHANNEL_WIDTH_80:
/*RF_BW:[31:30]=0x2 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4974, 0xC0000000, 0x2, phy_idx, 0);
/*small BW:[13:12]=0x0 */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0x3000, 0x0, phy_idx, 0);
/*Pri ch:[11:8] */
ret &= halbb_fw_set_reg_cmn(bb, 0x4978, 0xf00, pri_ch, phy_idx, 0);
break;
default:
BB_WARNING("Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
pri_ch);
}
if (phy_idx == HW_PHY_0) {
/*============== [Path A] ==============*/
ret &= halbb_fw_bw_setting_8852a_2(bb, bw, RF_PATH_A, path0_rf18);
/*============== [Path B] ==============*/
if (!bb->hal_com->dbcc_en)
ret &= halbb_fw_bw_setting_8852a_2(bb, bw, RF_PATH_B, path1_rf18);
} else {
/*============== [Path B] ==============*/
ret &= halbb_fw_bw_setting_8852a_2(bb, bw, RF_PATH_B, path1_rf18);
}
BB_DBG(bb, DBG_PHY_CONFIG,
"[Switch BW] BW: %d for PHY%d\n, ret = %d", bw, phy_idx, (u8)ret);
return ret;
}
bool halbb_fwofld_bw_ch_8852a_2(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum phl_phy_idx phy_idx)
{
bool rpt = true;
bool cck_en = false;
bool is_2g_ch = false;
u8 pri_ch_idx = 0;
u32 path0_rf18 = 0;
u32 path1_rf18 = 0;
/*==== [Set pri_ch idx] ====*/
if (central_ch <= 14) {
// === 2G === //
switch (bw) {
case CHANNEL_WIDTH_20:
break;
case CHANNEL_WIDTH_40:
pri_ch_idx = pri_ch > central_ch ? 1 : 2;
break;
default:
break;
}
/*==== [CCK SCO Compesate] ====*/
rpt &= halbb_fwofld_sco_cck_8852a_2(bb, pri_ch);
cck_en = true;
is_2g_ch = true;
} else {
// === 5G === //
switch (bw) {
case CHANNEL_WIDTH_20:
break;
case CHANNEL_WIDTH_40:
case CHANNEL_WIDTH_80:
if (pri_ch > central_ch)
pri_ch_idx = (pri_ch - central_ch) >> 1;
else
pri_ch_idx = ((central_ch - pri_ch) >> 1) + 1;
break;
default:
break;
}
cck_en = false;
is_2g_ch = false;
}
if (!bb->hal_com->dbcc_en) {
/*============== [Path A] ==============*/
path0_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK);
/*============== [Path B] ==============*/
path1_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK);
} else {
if (phy_idx == HW_PHY_0) {
/*============== [Path A] ==============*/
path0_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK);
}
else {
/*============== [Path B] ==============*/
path1_rf18 = halbb_read_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK);
}
}
/*BB_WARNING("RF a/b = %x , %x", path0_rf18, path1_rf18);*/
/*==== [Switch BW] ====*/
rpt &= halbb_fwofld_bw_8852a_2(bb, pri_ch_idx, bw, phy_idx, &path0_rf18, &path1_rf18);
/*BB_WARNING("SwBW : RF a/b = %x , %x", path0_rf18, path1_rf18);*/
/*==== [Switch CH] ====*/
rpt &= halbb_fwofld_ch_8852a_2(bb, central_ch, phy_idx, &path0_rf18, &path1_rf18);
/*BB_WARNING("SwCH : RF a/b = %x , %x", path0_rf18, path1_rf18);*/
if (!bb->hal_com->dbcc_en) {
/*============== [Path A] ==============*/
rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK, path0_rf18, 0);
/*============== [Path B] ==============*/
rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK, path1_rf18, 0);
} else {
if (phy_idx == HW_PHY_0) {
/*============== [Path A] ==============*/
rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK, path0_rf18, 0);
} else {
/*============== [Path B] ==============*/
rpt &= halbb_fw_set_rf_reg_8852a_2(bb, RF_PATH_B, 0x18, RFREGOFFSETMASK, path1_rf18, 0);
}
}
/*==== [CCK Enable / Disable] ====*/
rpt &= halbb_fwofld_cck_en_8852a_2(bb, cck_en, phy_idx);
/*==== [Spur elimination] ====*/
if (central_ch == 153) {
rpt &= halbb_fw_set_reg(bb, 0x469c, 0xfff, 0x210, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, 0xfff, 0x210, 0);
rpt &= halbb_fw_set_reg(bb, 0x42ac, 0xfff, 0x7c0, 0);
rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x1, 0);
} else if (central_ch == 151) {
rpt &= halbb_fw_set_reg(bb, 0x469c, 0xfff, 0x210, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, 0xfff, 0x210, 0);
rpt &= halbb_fw_set_reg(bb, 0x42ac, 0xfff, 0x40, 0);
rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x1, 0);
} else if (central_ch == 155) {
rpt &= halbb_fw_set_reg(bb, 0x469c, 0xfff, 0x2d0, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, 0xfff, 0x2d0, 0);
rpt &= halbb_fw_set_reg(bb, 0x42ac, 0xfff, 0x740, 0);
rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x1, 0);
} else {
rpt &= halbb_fw_set_reg(bb, 0x469c, BIT(12), 0x0, 0);
rpt &= halbb_fw_set_reg(bb, 0x4770, BIT(12), 0x0, 0);
rpt &= halbb_fw_set_reg(bb, 0x42c4, BIT(23), 0x0, 0);
}
if (is_2g_ch && ((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB)))
rpt &=halbb_fwofld_btg_8852a_2(bb, true);
else
rpt &=halbb_fwofld_btg_8852a_2(bb, false);
/* Dynamic 5M Mask Setting */
rpt &=halbb_fw_5m_mask_8852a_2(bb, pri_ch, bw);
/*==== [TSSI reset] ====*/
if (!bb->hal_com->dbcc_en) {
// Path A
rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x3, 0);
// Path B
rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x3, 1);
} else {
if (phy_idx == HW_PHY_0) {
// Path A
rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x58dc, BIT(31) | BIT(30), 0x3, 1);
} else {
// Path B
rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x1, 0);
rpt &= halbb_fw_set_reg(bb, 0x78dc, BIT(31) | BIT(30), 0x3, 1);
}
}
return rpt;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_fwofld.c
|
C
|
agpl-3.0
| 30,805
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_FWOFLD_H__
#define __HALBB_FWOFLD_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_FW_OFLD_SUPPORT
bool halbb_fwcfg_bb_phy_8852a_2(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
bool halbb_fwofld_bw_ch_8852a_2(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum phl_phy_idx phy_idx);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_fwofld.h
|
C
|
agpl-3.0
| 1,646
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
void halbb_cfg_bb_rpl_ofst(struct bb_info *bb, enum bb_band_t band, u8 path, u32 addr, u32 data)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u8 i = 0;
u8 bw = (u8)(addr & 0xf0) >> 4;
u8 rxsc_start = (u8)(addr & 0xf);
u8 rxsc = 0;
s8 ofst = 0;
if (bw == (u8)CHANNEL_WIDTH_20) {
gain->rpl_ofst_20[band][path] = (s8)data;
BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n",
band, path, (20 << bw), rxsc, gain->rpl_ofst_20[band][path]);
} else if (bw == (u8)CHANNEL_WIDTH_40){
if (rxsc_start == BB_RXSC_START_IDX_FULL) {
gain->rpl_ofst_40[band][path][0] = (s8)data;
BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n",
band, path, (20 << bw), rxsc,
gain->rpl_ofst_40[band][path][0]);
} else if (rxsc_start == BB_RXSC_START_IDX_20) {
for (i = 0; i < 2; i++) {
rxsc = BB_RXSC_START_IDX_20 + i;
ofst = (s8)((data >> (8 * i)) & 0xff);
gain->rpl_ofst_40[band][path][rxsc] = ofst;
BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n",
band, path, (20 << bw), rxsc,
gain->rpl_ofst_40[band][path][rxsc]);
}
}
} else if (bw == (u8)CHANNEL_WIDTH_80){
if (rxsc_start == BB_RXSC_START_IDX_FULL) {
gain->rpl_ofst_80[band][path][0] = (s8)data;
BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n",
band, path, (20 << bw), rxsc,
gain->rpl_ofst_80[band][path][0]);
} else if (rxsc_start == BB_RXSC_START_IDX_20) {
for (i = 0; i < 4; i++) {
rxsc = BB_RXSC_START_IDX_20 + i;
ofst = (s8)((data >> (8 * i)) & 0xff);
gain->rpl_ofst_80[band][path][rxsc] = ofst;
BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n",
band, path, (20 << bw), rxsc,
gain->rpl_ofst_80[band][path][rxsc]);
}
} else if (rxsc_start == BB_RXSC_START_IDX_40) {
for (i = 0; i < 2; i++) {
rxsc = BB_RXSC_START_IDX_40 + i;
ofst = (s8)((data >> (8 * i)) & 0xff);
gain->rpl_ofst_80[band][path][rxsc] = ofst;
BB_DBG(bb, DBG_INIT, "RPL[Band:%d][path=%d][%dM][rxsc=%d]=%d\n",
band, path, (20 << bw), rxsc,
gain->rpl_ofst_80[band][path][rxsc]);
}
}
}
}
bool halbb_init_cr_default(struct bb_info *bb, bool is_form_folder, u32 folder_len,
u32 *folder_array, enum phl_phy_idx phy_idx)
{
bool result = true;
if (!bb->bb_cmn_info_init_ready) {
BB_WARNING("bb_cmn_info_init_ready = false");
return false;
}
if (is_form_folder) {
if (!folder_array) {
BB_WARNING("[%s] folder_array=NULL\n", __func__);
return false;
}
if (folder_len == 0) {
BB_WARNING("[%s] folder_len=0\n", __func__);
return false;
}
}
#ifdef HALBB_DBCC_SUPPORT
if (phy_idx == HW_PHY_1 && !bb->hal_com->dbcc_en) {
BB_WARNING("[%s]\n",__func__);
if (!bb->bb_dbg_i.cr_dbg_mode_en)
return false;
}
#endif
BB_DBG(bb, DBG_INIT, "[%s] ic=%d\n", __func__, bb->hal_com->chip_id);
switch (bb->ic_type) {
case BB_RTL8852AA:
#ifdef BB_8852A_CAV_SUPPORT
result = halbb_cfg_bbcr_ax_8852a(bb, is_form_folder, folder_len,
folder_array, phy_idx);
#else
BB_WARNING("[%s] NOT Support 8852AA\n", __func__);
result = false;
#endif
break;
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
result = halbb_cfg_bbcr_ax_8852a_2(bb, is_form_folder, folder_len,
folder_array, phy_idx);
halbb_tpu_mac_cr_init(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
result = halbb_cfg_bbcr_ax_8852b(bb, is_form_folder, folder_len,
folder_array, phy_idx);
halbb_tpu_mac_cr_init(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
result = halbb_cfg_bbcr_ax_8852c(bb, is_form_folder, folder_len,
folder_array, phy_idx);
halbb_tpu_mac_cr_init(bb, phy_idx);
break;
#endif
default:
BB_WARNING("[%s] ic=%d\n", __func__, bb->hal_com->chip_id);
break;
}
BB_DBG(bb, DBG_INIT, "BB_CR_init_success = %d\n", result);
return result;
}
bool halbb_init_gain_table(struct bb_info *bb, bool is_form_folder, u32 folder_len,
u32 *folder_array, enum phl_phy_idx phy_idx)
{
bool result = true;
if (!bb->bb_cmn_info_init_ready) {
BB_WARNING("bb_cmn_info_init_ready = false");
return false;
}
if (is_form_folder) {
if (!folder_array) {
BB_WARNING("[%s] folder_array=NULL\n", __func__);
return false;
}
if (folder_len == 0) {
BB_WARNING("[%s] folder_len=0\n", __func__);
return false;
}
}
#ifdef HALBB_DBCC_SUPPORT
if (phy_idx == HW_PHY_1 && !bb->hal_com->dbcc_en) {
BB_WARNING("[%s]\n",__func__);
if (!bb->bb_dbg_i.cr_dbg_mode_en)
return false;
}
#endif
BB_DBG(bb, DBG_INIT, "[%s] ic=%d\n", __func__, bb->hal_com->chip_id);
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
result &= halbb_cfg_bb_gain_ax_8852a_2(bb, is_form_folder,
folder_len, folder_array);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
result &= halbb_cfg_bb_gain_ax_8852b(bb, is_form_folder,
folder_len, folder_array);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
result &= halbb_cfg_bb_gain_ax_8852c(bb, is_form_folder,
folder_len, folder_array);
break;
#endif
default:
BB_WARNING("[%s] ic=%d\n", __func__, bb->hal_com->chip_id);
break;
}
BB_DBG(bb, DBG_INIT, "BB_Gain_table_init_success = %d\n", result);
return result;
}
bool halbb_init_reg(struct bb_info *bb)
{
struct rtw_para_info_t *reg = NULL;
bool rpt_0 = true, rpt_1 = true, rpt_gain = true;
reg = &bb->phl_com->phy_sw_cap[HW_PHY_0].bb_phy_reg_info;
rpt_0 = halbb_init_cr_default(bb, reg->para_src, reg->para_data_len, reg->para_data, HW_PHY_0);
if (bb->hal_com->dbcc_en) {
reg = &bb->phl_com->phy_sw_cap[HW_PHY_1].bb_phy_reg_info;
rpt_1 = halbb_init_cr_default(bb, reg->para_src, reg->para_data_len, reg->para_data, HW_PHY_1);
}
reg = &bb->phl_com->phy_sw_cap[HW_PHY_0].bb_phy_reg_gain_info;
rpt_gain = halbb_init_gain_table(bb, reg->para_src, reg->para_data_len, reg->para_data, HW_PHY_0);
if (rpt_0 && rpt_1 && rpt_gain)
return true;
else
return false;
}
void halbb_rx_gain_table_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u32 val[10] = {0};
u8 i = 0, j = 0;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{show}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set {lna, tia} band path idx val\n");
return;
}
if (_os_strcmp(input[1], "show") == 0) {
for (i = 0; i < BB_GAIN_BAND_NUM; i++) {
if (i == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"===[2G]===\n");
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"===[5G-%s]===\n", (i == 1) ? ("Low") : ((i == 2) ? "Mid" : "High"));
}
for (j = 0; j < HALBB_MAX_PATH; j++) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"LNA_gain[Path=%d] = {%d, %d, %d, %d, %d, %d, %d}\n",
j,
gain->lna_gain[i][j][0],
gain->lna_gain[i][j][1],
gain->lna_gain[i][j][2],
gain->lna_gain[i][j][3],
gain->lna_gain[i][j][4],
gain->lna_gain[i][j][5],
gain->lna_gain[i][j][6]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"TIA_gain[Path=%d] = {%d, %d}\n",
j,
gain->tia_gain[i][j][0],
gain->tia_gain[i][j][1]);
}
}
} else if (_os_strcmp(input[1], "set") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[6], DCMD_DECIMAL, &val[3]);
if (_os_strcmp(input[2], "lna") == 0) {
if (val[0] >= BB_GAIN_BAND_NUM ||
val[1] >= HALBB_MAX_PATH ||
val[2] >= IC_LNA_NUM) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
gain->lna_gain[val[0]][val[1]][val[2]] = (s8)val[3];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set lna_gain[%d][%d][%d] = %d\n",
val[0], val[1], val[2], val[3]);
} else if (_os_strcmp(input[2], "tia") == 0) {
if (val[0] >= BB_GAIN_BAND_NUM ||
val[1] >= HALBB_MAX_PATH ||
val[2] >= IC_TIA_NUM) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
gain->tia_gain[val[0]][val[1]][val[2]] = (s8)val[3];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set tia_gain[%d][%d][%d] = %d\n",
val[0], val[1], val[2], val[3]);
}
halbb_set_gain_error(bb, bb->hal_com->band[bb->bb_phy_idx].cur_chandef.center_ch);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_hw_cfg.c
|
C
|
agpl-3.0
| 9,839
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_HW_CFG_H__
#define __HALBB_HW_CFG_H__
/*@--------------------------[Define] ---------------------------------------*/
#define BB_RXSC_NUM_40 9 /*SC:0,1~8*/
#define BB_RXSC_NUM_80 13 /*SC:0,1~8,9~12*/
#define BB_RXSC_NUM_160 15 /*SC:0,1~8,9~12,13~14*/
#define BB_RXSC_START_IDX_FULL 0
#define BB_RXSC_START_IDX_20 1
#define BB_RXSC_START_IDX_40 9
#define BB_RXSC_START_IDX_80 13
//#define BB_GAIN_BAND_NUM 4
/*@--------------------------[Enum]------------------------------------------*/
enum bb_band_t {
BB_BAND_2G = 0,
BB_BAND_5G_L = 1,
BB_BAND_5G_M = 2,
BB_BAND_5G_H = 3,
BB_GAIN_BAND_NUM = 4
};
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_cfg_bb_rpl_ofst(struct bb_info *bb, enum bb_band_t band, u8 path, u32 addr, u32 data);
bool halbb_init_cr_default(struct bb_info *bb, bool is_form_folder, u32 folder_len,
u32 *folder_array, enum phl_phy_idx phy_idx);
bool halbb_init_gain_table(struct bb_info *bb, bool is_form_folder, u32 folder_len,
u32 *folder_array, enum phl_phy_idx phy_idx);
void halbb_rx_gain_table_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_hw_cfg.h
|
C
|
agpl-3.0
| 2,263
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_HW_CFG_EX_H_
#define _HALBB_HW_CFG_EX_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_para_init_t {
BB_DEFAULT_CR = 0,
BB_GAIN_TABLE = 1,
};
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
bool halbb_init_reg(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_hw_cfg_ex.h
|
C
|
agpl-3.0
| 1,477
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_IC_HW_INFO_H__
#define __HALBB_IC_HW_INFO_H__
enum bb_ic_t {
BB_RTL8852AA = BIT(0), /*8852A Acut*/
BB_RTL8852A = BIT(1), /*8852A > Bcut*/
BB_RTL8852B = BIT(2),
BB_RTL8852C = BIT(3),
BB_RTL8834A = BIT(4),
BB_RTL8192XB = BIT(5)
};
enum bb_cr_t {
BB_52AA = 0,
BB_AP = 1,
BB_AP2 = 2,
BB_CLIENT = 3
};
#define BB_IC_N_1SS 0
#define BB_IC_N_2SS 0
#define BB_IC_N_3SS 0
#define BB_IC_N_4SS 0
#define BB_IC_AC_1SS 0
#define BB_IC_AC_2SS 0
#define BB_IC_AC_3SS 0
#define BB_IC_AC_4SS 0
#define BB_IC_AX_1SS 0
#define BB_IC_AX_2SS (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852B | BB_RTL8852C)
#define BB_IC_AX_3SS 0
#define BB_IC_AX_4SS (BB_RTL8834A)
/*@====the following macro DO NOT need to update when adding a new IC======= */
#define BB_IC_1SS (BB_IC_N_1SS | BB_IC_AC_1SS | BB_IC_AX_1SS)
#define BB_IC_2SS (BB_IC_N_2SS | BB_IC_AC_2SS | BB_IC_AX_2SS)
#define BB_IC_3SS (BB_IC_N_3SS | BB_IC_AC_3SS | BB_IC_AX_3SS)
#define BB_IC_4SS (BB_IC_N_4SS | BB_IC_AC_4SS | BB_IC_AX_4SS)
#define BB_IC_ABOVE_1SS (BB_IC_1SS | BB_IC_2SS | BB_IC_3SS |\
BB_IC_4SS)
#define BB_IC_ABOVE_2SS (BB_IC_2SS | BB_IC_3SS | BB_IC_4SS)
#define BB_IC_ABOVE_3SS (BB_IC_3SS | BB_IC_4SS)
#define BB_IC_ABOVE_4SS BB_IC_4SS
#define BB_IC_N_SERIES (BB_IC_N_1SS | BB_IC_N_2SS | BB_IC_N_3SS |\
BB_IC_N_4SS)
#define BB_IC_AC_SERIES (BB_IC_AC_1SS | BB_IC_AC_2SS |\
BB_IC_AC_3SS | BB_IC_AC_4SS)
#define BB_IC_AX_SERIES (BB_IC_AX_1SS | BB_IC_AX_2SS |\
BB_IC_AX_3SS | BB_IC_AX_4SS)
/*@==========================================================================*/
#define BB_IC_AX_AP (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852C | BB_RTL8834A)
#define BB_IC_AX_AP2 (BB_RTL8852C | BB_RTL8192XB)
#define BB_IC_AX_CLIENT (BB_RTL8852B)
/*@==========================================================================*/
#define BB_IC_MAX_BW_80 (BB_RTL8852AA | BB_RTL8852A | BB_RTL8852B)
#define BB_IC_MAX_BW_160 (BB_RTL8852C | BB_RTL8834A)
/*@==========================================================================*/
#if defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT)
#define HALBB_COMPILE_IC_DBCC
#endif
#if defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT)
/* FW OFFLOAD will be used in non-AP-only ICs*/
#define HALBB_COMPILE_IC_FWOFLD
#endif
#if defined(RTL8851A_SUPPORT)
#define HALBB_COMPILE_IC_1SS
#endif
#if (defined(BB_8852A_CAV_SUPPORT) || defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) || defined(BB_8852C_SUPPORT))
#define HALBB_COMPILE_IC_2SS
#endif
#if defined(RTL8853A_SUPPORT)
#define HALBB_COMPILE_IC_3SS
#endif
#if defined(RTL8834A_SUPPORT)
#define HALBB_COMPILE_IC_4SS
#endif
/*@==========================================================================*/
#if (defined(HALBB_COMPILE_IC_4SS))
#define HALBB_COMPILE_ABOVE_4SS
#endif
#if (defined(HALBB_COMPILE_IC_3SS) || defined(HALBB_COMPILE_ABOVE_4SS))
#define HALBB_COMPILE_ABOVE_3SS
#endif
#if (defined(HALBB_COMPILE_IC_2SS) || defined(HALBB_COMPILE_ABOVE_3SS))
#define HALBB_COMPILE_ABOVE_2SS
#endif
#if (defined(HALBB_COMPILE_IC_1SS) || defined(HALBB_COMPILE_ABOVE_2SS))
#define HALBB_COMPILE_ABOVE_1SS
#endif
#if (defined(HALBB_COMPILE_ABOVE_4SS))
#define HALBB_MAX_PATH 4
#elif (defined(HALBB_COMPILE_ABOVE_3SS))
#define HALBB_MAX_PATH 3
#elif (defined(HALBB_COMPILE_ABOVE_2SS))
#define HALBB_MAX_PATH 2
#else
#define HALBB_MAX_PATH 1
#endif
/*@==========================================================================*/
#if (defined(BB_8852A_CAV_SUPPORT))
#define HALBB_52AA_SERIES
#endif
#if (defined(BB_8852A_2_SUPPORT) || defined(BB_8852C_SUPPORT) || defined(BB_8834A_SUPPORT))
#define HALBB_COMPILE_AP_SERIES
#endif
#if (defined(BB_8852C_SUPPORT) || defined(BB_8192XB_SUPPORT))
#define HALBB_COMPILE_AP2_SERIES
#endif
#if (defined(BB_8852B_SUPPORT))
#define HALBB_COMPILE_CLIENT_SERIES
#endif
/*@==========================================================================*/
enum halbb_rate_type {
BB_1SS = 1, /*HE/VHT/HT 1SS*/
BB_2SS = 2, /*HE/VHT/HT 2SS*/
BB_3SS = 3, /*HE/VHT/HT 3SS*/
BB_4SS = 4, /*HE/VHT/HT 4SS*/
BB_CCK = 11, /*B mode*/
BB_OFDM = 12 /*G mode*/
};
enum halbb_rate_table {
BB_01M = 0,
BB_02M = 1,
BB_05M = 2,
BB_11M = 3,
BB_06M = 4,
BB_09M = 5,
BB_12M = 6,
BB_18M = 7,
BB_24M = 8,
BB_36M = 9,
BB_48M = 10,
BB_54M = 11,
BB_HT_MCS0 = 128, /*0x1000000*/
BB_VHT_1SS_MCS0 = 256, /*0x2000000*/
BB_VHT_2SS_MCS0 = 272,
BB_VHT_3SS_MCS0 = 288,
BB_VHT_4SS_MCS0 = 304,
BB_VHT_5SS_MCS0 = 320,
BB_VHT_6SS_MCS0 = 336,
BB_VHT_7SS_MCS0 = 352,
BB_VHT_8SS_MCS0 = 368,
BB_HE_1SS_MCS0 = 384, /*0x3000000*/
BB_HE_2SS_MCS0 = 400,
BB_HE_3SS_MCS0 = 416,
BB_HE_4SS_MCS0 = 432,
BB_HE_5SS_MCS0 = 448,
BB_HE_6SS_MCS0 = 464,
BB_HE_7SS_MCS0 = 480,
BB_HE_8SS_MCS0 = 496
};
enum halbb_legacy_spec_rate {
BB_SPEC_RATE_6M = 0xb,
BB_SPEC_RATE_9M = 0xf,
BB_SPEC_RATE_12M = 0xa,
BB_SPEC_RATE_18M = 0xe,
BB_SPEC_RATE_24M = 0x9,
BB_SPEC_RATE_36M = 0xd,
BB_SPEC_RATE_48M = 0x8,
BB_SPEC_RATE_54M = 0xc
};
#define GEN_HT_RATE_IDX(MCS) (0x80 | ((MCS) & 0x1f))
#define GEN_VHT_RATE_IDX(SS, MCS) (0x100 | (((SS) & 0x3) << 4) | ((MCS) & 0xf))
#define GEN_HE_RATE_IDX(SS, MCS) (0x180 | (((SS) & 0x3) << 4) | ((MCS) & 0xf))
#define BB_HT_MCS(x) (BB_HT_MCS0 + x)
#define BB_VHT_1SS_MCS(x) (BB_VHT_1SS_MCS0 + x)
#define BB_VHT_2SS_MCS(x) (BB_VHT_2SS_MCS0 + x)
#define BB_VHT_3SS_MCS(x) (BB_VHT_3SS_MCS0 + x)
#define BB_VHT_4SS_MCS(x) (BB_VHT_4SS_MCS0 + x)
#define BB_VHT_5SS_MCS(x) (BB_VHT_5SS_MCS0 + x)
#define BB_VHT_6SS_MCS(x) (BB_VHT_6SS_MCS0 + x)
#define BB_VHT_7SS_MCS(x) (BB_VHT_7SS_MCS0 + x)
#define BB_VHT_8SS_MCS(x) (BB_VHT_8SS_MCS0 + x)
#define BB_HE_1SS_MCS(x) (BB_HE_1SS_MCS0 + x)
#define BB_HE_2SS_MCS(x) (BB_HE_2SS_MCS0 + x)
#define BB_HE_3SS_MCS(x) (BB_HE_3SS_MCS0 + x)
#define BB_HE_4SS_MCS(x) (BB_HE_4SS_MCS0 + x)
#define BB_HE_5SS_MCS(x) (BB_HE_5SS_MCS0 + x)
#define BB_HE_6SS_MCS(x) (BB_HE_6SS_MCS0 + x)
#define BB_HE_7SS_MCS(x) (BB_HE_7SS_MCS0 + x)
#define BB_HE_8SS_MCS(x) (BB_HE_8SS_MCS0 + x)
#define BB_VHT_MCS(SS, x) (BB_VHT_1SS_MCS0 + ((SS - 1) * 16 ) + x)
#define BB_HE_MCS(SS, x) (BB_HE_1SS_MCS0 + ((SS - 1) * 16 ) + x)
/*[Rate Number]*/
#define HT_NUM_MCS 8
#define HE_VHT_NUM_MCS 12
#define LEGACY_RATE_NUM 12
#define HT_RATE_NUM_4SS (HT_NUM_MCS * 4)
#define VHT_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4)
#define HE_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4)
#define HT_RATE_NUM_3SS (HT_NUM_MCS * 3)
#define VHT_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3)
#define HE_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3)
#define HT_RATE_NUM_2SS (HT_NUM_MCS * 2)
#define VHT_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2)
#define HE_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2)
#define HT_RATE_NUM_1SS HT_NUM_MCS
#define VHT_RATE_NUM_1SS HE_VHT_NUM_MCS
#define HE_RATE_NUM_1SS HE_VHT_NUM_MCS
#if (defined(HALBB_COMPILE_ABOVE_4SS))
#define HT_RATE_NUM HT_RATE_NUM_4SS
#define VHT_RATE_NUM VHT_RATE_NUM_4SS
#define HE_RATE_NUM HE_RATE_NUM_4SS
#elif (defined(HALBB_COMPILE_ABOVE_3SS))
#define HT_RATE_NUM HT_RATE_NUM_3SS
#define VHT_RATE_NUM VHT_RATE_NUM_3SS
#define HE_RATE_NUM HE_RATE_NUM_3SS
#elif (defined(HALBB_COMPILE_ABOVE_2SS))
#define HT_RATE_NUM HT_RATE_NUM_2SS
#define VHT_RATE_NUM VHT_RATE_NUM_2SS
#define HE_RATE_NUM HE_RATE_NUM_2SS
#else
#define HT_RATE_NUM HT_RATE_NUM_1SS
#define VHT_RATE_NUM VHT_RATE_NUM_1SS
#define HE_RATE_NUM HE_RATE_NUM_1SS
#endif
#define LOW_BW_RATE_NUM HE_RATE_NUM
/*@==========================================================================*/
/****************************************************************
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
***************************************************************/
enum bb_qam_type {
BB_QAM_CCK = 0,
BB_QAM_BPSK = 1,
BB_QAM_QPSK = 2,
BB_QAM_16QAM = 3,
BB_QAM_64QAM = 4,
BB_QAM_256QAM = 5,
BB_QAM_1024QAM = 6
};
enum bb_mode_type { /*@Fast antenna training*/
BB_LEGACY_MODE = 0,
BB_HT_MODE = 1,
BB_VHT_MODE = 2,
BB_HE_MODE = 3
};
/* BB_CMNINFO_CART_VER */
enum halbb_cart_ver {
BB_CART_A = 0,
BB_CART_B = 1,
BB_CART_C = 2,
BB_CART_D = 3,
BB_CART_E = 4,
BB_CART_F = 5,
BB_CART_G = 6,
BB_CART_H = 7,
BB_CART_I = 8,
BB_CART_J = 9,
BB_CART_K = 10,
BB_CART_L = 11,
BB_CART_M = 12,
BB_CART_N = 13,
BB_CART_O = 14,
BB_CART_TEST = 15,
};
enum bb_path {
BB_PATH_NON = 0,
BB_PATH_A = 0x00000001,
BB_PATH_B = 0x00000002,
BB_PATH_C = 0x00000004,
BB_PATH_D = 0x00000008,
BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
BB_PATH_AUTO = 0xff /*for auto path selection*/
};
enum rf_syn {
RF_SYN0 = 0,
RF_SYN1 = 1,
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ic_hw_info.h
|
C
|
agpl-3.0
| 10,155
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_IC_SW_INFO_H__
#define __HALBB_IC_SW_INFO_H__
#define HLABB_CODE_BASE "HALBB_025"
#define HALBB_RELEASE_DATE "20210817"
/*HALBB API status*/
#define HALBB_SET_FAIL 0
#define HALBB_SET_SUCCESS 1
#define HALBB_SET_NO_NEED 3
/*HALBB Set/Revert*/
#define HALBB_SET 1
#define HALBB_REVERT 2
/****************************************************************
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
***************************************************************/
enum halbb_api_host {
RUN_IN_FW = 0,
RUN_IN_DRIVER = 1
};
enum halbb_backup_type {
HALBB_BACKUP = 1,
HALBB_RESTORE = 2
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ic_sw_info.h
|
C
|
agpl-3.0
| 1,705
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halbb_precomp.h"
bool halbb_chk_bb_rf_pkg_set_valid(struct bb_info *bb)
{
struct rtw_hal_com_t *hal_i = bb->hal_com;
u8 bb_ver = 0; /*hal_i->bb_para_pkg_ver;*/ /*TBD*/
u8 rf_ver = 0; /*hal_i->rf_para_pkg_ver;*/ /*TBD*/
bool valid = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
valid = halbb_chk_pkg_valid_8852a(bb, bb_ver, rf_ver);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
valid = halbb_chk_pkg_valid_8852a_2(bb, bb_ver, rf_ver);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
valid = halbb_chk_pkg_valid_8852b(bb, bb_ver, rf_ver);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
valid = halbb_chk_pkg_valid_8852c(bb, bb_ver, rf_ver);
break;
#endif
#ifdef BB_8834A_SUPPORT
case BB_RTL8834A:
valid = halbb_chk_pkg_valid_8834a(bb, bb_ver, rf_ver);
break;
#endif
default:
break;
}
return valid;
}
void halbb_ic_hw_setting_init(struct bb_info *bb)
{
#ifdef HALBB_TDMA_CR_SUPPORT
halbb_tdma_cr_sel_init(bb);
#endif
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_ic_hw_setting_init_8852a(bb);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_ic_hw_setting_init_8852a_2(bb);
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
halbb_dcr_init(bb);
#endif
#ifdef BB_DYN_CFO_TRK_LOP
halbb_dyn_cfo_trk_loop_init(bb);
#endif
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_ic_hw_setting_init_8852b(bb);
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
halbb_dcr_init(bb);
#endif
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_ic_hw_setting_init_8852c(bb);
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
halbb_dcr_init(bb);
#endif
break;
#endif
default:
break;
}
}
void halbb_get_efuse_init(struct bb_info *bb)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_get_normal_efuse_init_8852a_2(bb);
halbb_get_hidden_efuse_init_8852a_2(bb);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_get_normal_efuse_init_8852b(bb);
halbb_get_hide_efuse_init_8852b(bb);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_get_normal_efuse_init_8852c(bb);
halbb_get_hidden_efuse_init_8852c(bb);
break;
#endif
default:
break;
}
}
void halbb_cmn_info_self_init(struct bb_info *bb)
{
struct rtw_hal_com_t *hal_i = bb->hal_com;
/*[IC type]*/
if (hal_i->chip_id == CHIP_WIFI6_8852A) {
if (hal_i->cv == CAV)
bb->ic_type = BB_RTL8852AA;
else
bb->ic_type = BB_RTL8852A;
} else if (hal_i->chip_id == CHIP_WIFI6_8852B) {
bb->ic_type = BB_RTL8852B;
#ifdef BB_8852C_SUPPORT
} else if (hal_i->chip_id == CHIP_WIFI6_8852C) {
bb->ic_type = BB_RTL8852C;
#endif
} else if (hal_i->chip_id == CHIP_WIFI6_8834A) {
bb->ic_type = BB_RTL8834A;
#ifdef BB_8192XB_SUPPORT
} else if (hal_i->chip_id == CHIP_WIFI6_8192XB) {
bb->ic_type = BB_RTL8192XB;
#endif
}
/*[CR type]*/
if (bb->ic_type == BB_RTL8852AA)
bb->cr_type = BB_52AA;
else if (bb->ic_type & BB_IC_AX_AP)
bb->cr_type = BB_AP;
else if (bb->ic_type & BB_IC_AX_AP2)
bb->cr_type = BB_AP2;
else if (bb->ic_type & BB_IC_AX_CLIENT)
bb->cr_type = BB_CLIENT;
/*[RF path number]*/
if (bb->ic_type & BB_IC_1SS)
bb->num_rf_path = 1;
else if (bb->ic_type & BB_IC_2SS)
bb->num_rf_path = 2;
else if (bb->ic_type & BB_IC_3SS)
bb->num_rf_path = 3;
else if (bb->ic_type & BB_IC_4SS)
bb->num_rf_path = 4;
else
bb->num_rf_path = 1;
BB_DBG(bb, DBG_INIT, "cr_type=%d, num_rf_path=%d\n",
bb->cr_type, bb->num_rf_path);
BB_DBG(bb, DBG_INIT,
"num_rf_path=%d, rate_num{Legcy, HT, VHT, HE}={%d,%d,%d,%d}\n",
bb->num_rf_path,
LEGACY_RATE_NUM, HT_RATE_NUM, VHT_RATE_NUM, HE_RATE_NUM);
bb->manual_support_ability = 0xffffffff;
bb->bb_dm_init_ready = false;
bb->bb_sys_up_time = 0;
bb->bb_watchdog_en = true;
bb->bb_ic_api_en = true;
/*[Drv Dbg Info]*/
bb->cmn_dbg_msg_period = 2;
bb->cmn_dbg_msg_cnt = 0;
/*[Dummy]*/
bb->bool_dummy = false;
bb->u8_dummy = 0xff;
bb->u16_dummy = 0xffff;
bb->u32_dummy = 0xffffffff;
/*@=== [HALBB Structure] ============================================*/
bb->bb_link_i.is_linked = false;
bb->bb_link_i.is_linked_pre = false;
bb->bb_link_i.tp_active_th = 5;
bb->bb_path_i.rx_path_en = bb->num_rf_path;
bb->bb_path_i.tx_path_en = bb->num_rf_path;
bb->adv_bb_dm_en = true;
bb->bb_cmn_info_init_ready = true;
bb->bb_watchdog_period = 2; /*sec*/
bb->bb_cmn_hooker->bb_dm_number = sizeof(halbb_func_i) / sizeof(struct halbb_func_info);
halbb_edcca_dev_hw_cap(bb);
halbb_cmn_info_self_reset(bb);
}
u64 halbb_supportability_default(struct bb_info *bb)
{
u64 support_ability = 0;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
support_ability |=
/*BB_RA |*/
BB_FA_CNT |
/*BB_DFS |*/
BB_EDCCA |
/*BB_ENVMNTR |*/
BB_CFO_TRK |
/*BB_DIG |*/
0;
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
support_ability |=
/*BB_RA |*/
BB_FA_CNT |
BB_DFS |
BB_EDCCA |
BB_ENVMNTR |
BB_CFO_TRK |
BB_DIG |
/*BB_ANT_DIV |*/
0;
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
support_ability |=
BB_RA |
BB_FA_CNT |
BB_DFS |
BB_EDCCA |
BB_CFO_TRK |
BB_ENVMNTR |
BB_DIG |
0;
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
support_ability |=
/*BB_RA |*/
BB_FA_CNT |
BB_DFS |
BB_EDCCA |
BB_ENVMNTR |
BB_CFO_TRK |
BB_DIG |
/*BB_ANT_DIV |*/
0;
break;
#endif
default:
BB_WARNING("[%s]\n", __func__);
break;
}
return support_ability;
}
void halbb_supportability_init(struct bb_info *bb)
{
u64 support_ability;
#if 0
if (bb->phl_com->bb_ability_manual != 0xffffffff) {
support_ability = bb->phl_com->bb_ability_manual;
} else
#endif
if(phl_is_mp_mode(bb->phl_com)) {
support_ability = 0;
} else {
support_ability = halbb_supportability_default(bb);
}
bb->support_ability = support_ability;
BB_DBG(bb, DBG_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
bb->ic_type, bb->phl_com->drv_mode, bb->support_ability);
}
void halbb_hw_init(struct bb_info *bb)
{
BB_DBG(bb, DBG_INIT, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
halbb_cmn_info_self_init(bb);
if (!halbb_chk_bb_rf_pkg_set_valid(bb)) {
BB_WARNING("[%s] Init fail\n", __func__);
return;
}
}
void halbb_dm_deinit(struct rtw_phl_com_t *phl_com, void *bb_phy_0)
{
struct bb_info *bb = (struct bb_info *)bb_phy_0;
if (!bb->bb_dm_init_ready)
return;
halbb_timer_ctrl(bb, BB_CANCEL_TIMER);
#ifdef HALBB_LA_MODE_SUPPORT
halbb_la_deinit(bb);
#endif
#ifdef HALBB_PSD_SUPPORT
halbb_psd_deinit(bb);
#endif
#ifdef HALBB_CH_INFO_SUPPORT
halbb_ch_info_deinit(bb);
#endif
#ifdef HALBB_DIG_SUPPORT
halbb_dig_deinit(bb);
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_antdiv_deinit(bb);
#endif
#ifdef BB_8852A_2_SUPPORT
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfo_deinit(bb);
#endif
bb->bb_dm_init_ready = false;
}
enum rtw_hal_status halbb_dm_init(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
if (!bb) {
BB_WARNING("[%s] *bb = NULL", __func__);
return RTW_HAL_STATUS_FAILURE;
}
if (!bb->bb_cmn_info_init_ready) {
BB_WARNING("bb_cmn_info_init_ready = false");
return RTW_HAL_STATUS_FAILURE;
}
#ifdef HALBB_DBCC_SUPPORT
#ifdef HALBB_DBCC_DVLP_FLAG
if (phy_idx == HW_PHY_1)
return hal_status;
#endif
bb = halbb_get_curr_bb_pointer(bb, phy_idx);
BB_DBG(bb, DBG_INIT, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
#endif
halbb_ic_hw_setting_init(bb);
halbb_gpio_setting_init(bb);
halbb_get_efuse_init(bb);
halbb_supportability_init(bb);
halbb_physts_parsing_init(bb);
halbb_cmn_rpt_init(bb);
halbb_dbg_setting_init(bb);
#ifdef HALBB_PWR_CTRL_SUPPORT
halbb_macid_ctrl_init(bb);
#endif
#ifdef HALBB_STATISTICS_SUPPORT
halbb_statistics_init(bb);
#endif
#ifdef HALBB_LA_MODE_SUPPORT
halbb_la_init(bb);
#endif
#ifdef HALBB_PSD_SUPPORT
halbb_psd_init(bb);
#endif
#ifdef HALBB_EDCCA_SUPPORT
halbb_edcca_init(bb);
#endif
#ifdef HALBB_DFS_SUPPORT
halbb_dfs_init(bb);
#endif
#ifdef HALBB_DIG_SUPPORT
halbb_dig_init(bb);
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfo_trk_init(bb);
#endif
#ifdef HALBB_RA_SUPPORT
halbb_ra_init(bb);
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
halbb_env_mntr_init(bb);
#endif
#ifdef HALBB_PWR_CTRL_SUPPORT
halbb_pwr_ctrl_init(bb);
#endif
#ifdef HALBB_RUA_SUPPORT
halbb_rua_tbl_init(bb);
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_antdiv_init(bb);
#endif
#ifdef HALBB_CH_INFO_SUPPORT
halbb_ch_info_init(bb);
#endif
halbb_reset_adc(bb);
#ifdef HALBB_DIG_MCC_SUPPORT
Halbb_init_mccdm(bb);
#endif
bb->bb_dm_init_ready = true;
BB_DBG(bb, DBG_INIT, "bb_init_ready = %d\n", bb->bb_dm_init_ready);
return hal_status;
}
void halbb_timer_ctrl(struct bb_info *bb, enum bb_timer_cfg_t timer_state)
{
BB_DBG(bb, DBG_INIT, "[%s] timer_state = %d\n", __func__, timer_state);
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_cfg_timers(bb, timer_state, &bb->bb_ant_div_i.antdiv_timer_i);
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfg_timers(bb, timer_state, &bb->bb_cfo_trk_i.cfo_timer_i);
#endif
#ifdef HALBB_TDMA_CR_SUPPORT
halbb_cfg_timers(bb, timer_state, &bb->bb_dbg_i.tdma_cr_timer_i);
#endif
#ifdef HALBB_DIG_TDMA_SUPPORT
halbb_cfg_timers(bb, timer_state, &bb->bb_dig_i.dig_timer_i);
#endif
}
void halbb_timer_init(struct bb_info *bb)
{
BB_DBG(bb, DBG_INIT, "[%s]\n", __func__);
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_antdiv_timer_init(bb);
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cfo_acc_timer_init(bb);
#endif
#ifdef HALBB_TDMA_CR_SUPPORT
halbb_tdma_cr_timer_init(bb);
#endif
#ifdef HALBB_DIG_TDMA_SUPPORT
halbb_dig_timer_init(bb);
#endif
}
void halbb_cr_cfg_init(struct bb_info *bb)
{
halbb_cr_cfg_dbg_init(bb);
halbb_cr_cfg_physts_init(bb);
#ifdef HALBB_STATISTICS_SUPPORT
halbb_cr_cfg_stat_init(bb);
#endif
#ifdef HALBB_PSD_SUPPORT
halbb_cr_cfg_psd_init(bb);
#endif
#ifdef HALBB_DIG_SUPPORT
halbb_cr_cfg_dig_init(bb);
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
halbb_cr_cfg_env_mntr_init(bb);
#endif
#ifdef HALBB_EDCCA_SUPPORT
halbb_cr_cfg_edcca_init(bb);
#endif
#ifdef HALBB_DFS_SUPPORT
halbb_cr_cfg_dfs_init(bb);
#endif
#ifdef HALBB_LA_MODE_SUPPORT
halbb_cr_cfg_la_init(bb);
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_cr_cfg_antdiv_init(bb);
#endif
#ifdef HALBB_PMAC_TX_SUPPORT
halbb_cr_cfg_plcp_init(bb);
#endif
halbb_cr_cfg_mp_init(bb);
#ifdef HALBB_CH_INFO_SUPPORT
halbb_cr_cfg_ch_info_init(bb);
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_cr_cfg_cfo_trk_init(bb);
#endif
}
void halbb_buffer_deinit(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void *bb_phy_0)
{
struct bb_info *bb = (struct bb_info *)bb_phy_0;
/*Deinit phy-cmn*/
if (bb->bb_cmn_hooker) {
BB_DBG(bb, DBG_INIT, "deinit bb_cmn_hooker");
hal_mem_free(hal_com, bb->bb_cmn_hooker, sizeof(struct bb_cmn_info));
}
#ifdef HALBB_DBCC_SUPPORT
/*Deinit phy-1*/
if (bb->bb_phy_hooker) {
BB_DBG(bb, DBG_INIT, "deinit phy-%d", bb->bb_phy_hooker->bb_phy_idx);
//halbb_timer_ctrl(bb->bb_phy_hooker, BB_CANCEL_TIMER);
//halbb_timer_ctrl(bb->bb_phy_hooker, BB_RELEASE_TIMER);
hal_mem_free(hal_com, bb->bb_phy_hooker, sizeof(struct bb_info));
}
#endif
/*Deinit phy-0*/
if (bb) {
BB_DBG(bb, DBG_INIT, "deinit phy-%d", bb->bb_phy_idx);
halbb_timer_ctrl(bb, BB_CANCEL_TIMER);
halbb_timer_ctrl(bb, BB_RELEASE_TIMER);
hal_mem_free(hal_com, bb, sizeof(struct bb_info));
}
}
u32
halbb_buffer_init(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void **bb_out_addr)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct bb_info *bb_0 = NULL;
struct bb_cmn_info *bb_cmn = NULL;
bb_0 = hal_mem_alloc(hal_com, sizeof(struct bb_info));
if (!bb_0) {
BB_WARNING("*bb = NULL\n");
return RTW_HAL_STATUS_BB_INIT_FAILURE;
}
*bb_out_addr = bb_0;
bb_0->phl_com = phl_com;/*shared memory for all components*/
bb_0->hal_com = hal_com;/*shared memory for phl and hal*/
bb_0->bb_phy_idx = HW_PHY_0;
bb_cmn = hal_mem_alloc(hal_com, sizeof(struct bb_cmn_info));
if (!bb_cmn) {
BB_WARNING("*bb_cmn = NULL\n");
return RTW_HAL_STATUS_BB_INIT_FAILURE;
}
bb_0->bb_cmn_hooker = bb_cmn;
halbb_dbg_comp_init(bb_0);
halbb_hw_init(bb_0);
halbb_timer_init(bb_0);
halbb_cr_cfg_init(bb_0);
#ifdef HALBB_DBCC_SUPPORT
BB_DBG(bb_0, DBG_INIT, "dbcc_support = %d\n", phl_com->dev_cap.dbcc_sup);
hal_status = halbb_buffer_init_phy1(bb_0);
#else
BB_DBG(bb_0, DBG_INIT, "DBCC macro not enabled\n");
#endif
BB_DBG(bb_0, DBG_INIT, "[%s]\n", __func__);
BB_DBG(bb_0, DBG_INIT, " %-35s: %s\n", "Code Base:", HLABB_CODE_BASE);
BB_DBG(bb_0, DBG_INIT, " %-35s: %s\n", "Code Release Date", HALBB_RELEASE_DATE);
#ifdef BB_8852A_CAV_SUPPORT
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[CAV]52A BB_REG Ver", BB_REG_RELEASE_VERSION_8852A);
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[CAV]52A BB_REG Release Date", BB_REG_RELEASE_DATE_8852A);
#endif
#ifdef BB_8852A_2_SUPPORT
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[>CBV]52A BB_REG Ver", BB_REG_RELEASE_VERSION_8852A_2);
BB_DBG(bb_0, DBG_INIT, " %-35s: %d\n", "[>CBV]52A BB_REG Release Date", BB_REG_RELEASE_DATE_8852A_2);
#endif
return (u32)hal_status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_init.c
|
C
|
agpl-3.0
| 14,014
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_INIT_H_
#define _HALBB_INIT_H_
#include "../../hal_headers_le.h"
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_cmn_info_self_init(struct bb_info *bb);
void halbb_timer_ctrl(struct bb_info *bb, enum bb_timer_cfg_t timer_state);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_init.h
|
C
|
agpl-3.0
| 1,193
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_INIT_EX_H_
#define _HALBB_INIT_EX_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_dm_deinit(struct rtw_phl_com_t *phl_com, void *bb_phy_0);
enum rtw_hal_status halbb_dm_init(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_buffer_deinit(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void *bb_phy_0);
u32 halbb_buffer_init(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void **bb_out_addr);
void halbb_get_efuse_init(struct bb_info *bb);
void halbb_ic_hw_setting_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_init_ex.h
|
C
|
agpl-3.0
| 1,511
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
void halbb_cfg_timers(struct bb_info *bb, enum bb_timer_cfg_t cfg,
struct halbb_timer_info *timer)
{
BB_DBG(bb, DBG_DBG_API, "[%s] %s timer\n", __func__,
((cfg == BB_SET_TIMER) ? "SET" : ((cfg == BB_CANCEL_TIMER) ? "CANCEL" : ("RLS"))));
if (cfg == BB_INIT_TIMER) {
BB_WARNING("[%s]\n", __func__);
return;
}
if (cfg == BB_SET_TIMER) {
if (timer->timer_state != BB_TIMER_IDLE) {
BB_WARNING("[%s] state=%d\n", __func__, timer->timer_state);
return;
}
timer->timer_state = BB_TIMER_RUN;
halbb_set_timer(bb, &timer->timer_list, timer->cb_time);
} else if (cfg == BB_CANCEL_TIMER) {
halbb_cancel_timer(bb, &timer->timer_list);
timer->timer_state = BB_TIMER_IDLE;
} else if (cfg == BB_RELEASE_TIMER) {
halbb_release_timer(bb, &timer->timer_list);
timer->timer_state = BB_TIMER_RELEASE;
}
}
u32 halbb_get_sys_time(struct bb_info *bb)
{
return 0;
}
u32 halbb_phy0_to_phy1_ofst(struct bb_info *bb, u32 addr)
{
u32 ofst = 0;
#ifdef HALBB_DBCC_SUPPORT
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
ofst = halbb_phy0_to_phy1_ofst_8852a(bb, addr);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
ofst = halbb_phy0_to_phy1_ofst_8852a_2(bb, addr);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
ofst = halbb_phy0_to_phy1_ofst_8852c(bb, addr);
break;
#endif
default:
break;
}
#endif
return ofst;
}
#ifdef BB_FW_OFLD_SUPPORT
bool halbb_check_fw_ofld(struct bb_info *bb)
{
bool ret = bb->phl_com->dev_cap.fw_cap.offload_cap & BIT0;
BB_DBG(bb, DBG_FW_INFO, "FW ofld ret = %d\n", (u8)ret);
return ret;
}
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc)
{
/* halbb_set_reg */
struct rtw_mac_cmd cmd;
u32 ret;
cmd.src = RTW_MAC_BB_CMD_OFLD;
cmd.type = RTW_MAC_WRITE_OFLD;
cmd.lc = lc;
cmd.offset = (u16)addr;
cmd.value = val;
cmd.mask = mask;
ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd);
BB_DBG(bb, DBG_FW_INFO, "FW ofld addr:%x, val:%x, msk:%x\n", addr, val, mask);
if (ret) {
BB_WARNING("IO offload fail: %d\n", ret);
return false;
}
else {
return true;
}
}
bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr,
u32 mask, u32 val, enum phl_phy_idx phy_idx, u8 lc)
{
bool ret = true;
u32 val_mod = val;
#ifdef HALBB_DBCC_SUPPORT
if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1)
addr += halbb_phy0_to_phy1_ofst(bb, addr);
#endif
ret = halbb_fw_set_reg(bb, addr, mask, val_mod, lc);
return ret;
}
#endif
void halbb_set_cr(struct bb_info *bb, u32 addr, u32 val)
{
if (bb->bb_dbg_i.cr_recorder_en)
BB_TRACE("[W] 0x%04x = 0x%08x\n", addr, val);
halbb_set_32(bb, addr, val);
}
u32 halbb_get_cr(struct bb_info *bb, u32 addr)
{
u32 val = halbb_get_32(bb, addr);
if (bb->bb_dbg_i.cr_recorder_en)
BB_TRACE("[R] 0x%04x = 0x%08x\n", addr, val);
return val;
}
void halbb_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val)
{
u32 ori_val = 0;
u32 shift;
if (mask != MASKDWORD) {
ori_val = halbb_get_32(bb, addr);
shift = halbb_cal_bit_shift(mask);
val = ((ori_val) & (~mask)) | (((val << shift)) & mask);
}
halbb_set_cr(bb, addr, val);
}
void halbb_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val, enum phl_phy_idx phy_idx)
{
u32 ori_val, shift;
u32 val_mod = val;
#ifdef HALBB_DBCC_SUPPORT
if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1)
addr += halbb_phy0_to_phy1_ofst(bb, addr);
#endif
if (mask != MASKDWORD) {
shift = halbb_cal_bit_shift(mask);
ori_val = halbb_get_32(bb, addr);
val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
}
halbb_set_cr(bb, addr, val_mod);
}
void halbb_set_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 val)
{
u32 ori_val = 0, shift = 0;
u32 val_mod = val;
if (mask != MASKDWORD) {
shift = halbb_cal_bit_shift(mask);
ori_val = halbb_get_32(bb, addr);
val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
}
halbb_set_cr(bb, addr, val_mod);
#ifdef HALBB_DBCC_SUPPORT
if (!bb->hal_com->dbcc_en)
return;
addr += halbb_phy0_to_phy1_ofst(bb, addr);
if (mask != MASKDWORD) {
ori_val = halbb_get_32(bb, addr);
val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
}
halbb_set_cr(bb, addr, val_mod);
#endif
}
u32 halbb_get_reg(struct bb_info *bb, u32 addr, u32 mask)
{
u32 val_0 = 0;
val_0 = (halbb_get_cr(bb, addr) & mask) >> halbb_cal_bit_shift(mask);
return val_0;
}
u32 halbb_get_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, enum phl_phy_idx phy_idx)
{
u32 val_0 = 0;
#ifdef HALBB_DBCC_SUPPORT
if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1)
addr += halbb_phy0_to_phy1_ofst(bb, addr);
#endif
val_0 = (halbb_get_cr(bb, addr) & mask) >> halbb_cal_bit_shift(mask);
return val_0;
}
u32 halbb_get_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 *val_1)
{
u32 val_0 = 0;
u32 shift = halbb_cal_bit_shift(mask);
val_0 = (halbb_get_cr(bb, addr) & mask) >> shift;
#ifdef HALBB_DBCC_SUPPORT
if (!bb->hal_com->dbcc_en)
return val_0;
addr += halbb_phy0_to_phy1_ofst(bb, addr);
*val_1 = (halbb_get_cr(bb, addr) & mask) >> shift;
#endif
return val_0;
}
bool halbb_fill_h2c_cmd(struct bb_info *bb, u16 cmdlen, u8 cmdid,
u8 classid, u32 *pval)
{
u32 rt_val = 0;
struct rtw_g6_h2c_hdr hdr = {0};
struct rtw_hal_com_t *hal_com = NULL;
hdr.h2c_class = classid;
hdr.h2c_func = cmdid;
hdr.content_len = cmdlen;
hdr.type = H2CB_TYPE_LONG_DATA;
hdr.rec_ack = 0;
hdr.done_ack = 0;
hal_com = bb->hal_com;
BB_DBG(bb, DBG_FW_INFO, "H2C: %x %x %x\n", classid, cmdid, cmdlen);
rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval);
if (rt_val != 0) {
BB_WARNING("Error H2C CLASS=%d, ID=%d, Rt_v = %d\n", classid, cmdid, rt_val);
return false;
} else {
return true;
}
}
bool halbb_test_h2c_c2h_flow(struct bb_info *bb)
{
u32 rt_val = 0;
u32 *bb_h2c;
u8 h2ctest[4] = {1, 0, 0, 0};
bb_h2c = (u32 *) &h2ctest;
rt_val = halbb_fill_h2c_cmd(bb, 1, DM_H2C_FW_H2C_TEST, HALBB_H2C_DM, bb_h2c);
if (rt_val != 0) {
BB_WARNING("Error H2C TEST\n");
return false;
} else {
return true;
}
}
u32 halbb_c2h_rua_parsing(struct bb_info *bb, u8 cmdid, u8 len, u8 *c2h)
{
u32 val = 0;
return val;
}
u32 halbb_c2h_mu_gptbl_rpt(struct bb_info *bb, u16 len, u8 *c2h)
{
/* Set MU grouping table and return value */
u32 val = 0;
u8 i = 0;
u8 j = 0;
u8 k = 0;
u8 mask = 0x03;
struct hal_mu_score_tbl *mu_sc_tbl = &bb->hal_com->bb_mu_score_tbl;
/*
Need to do MU protect to prevent error c2h sending
this function will be return to prevent error c2h
*/
return val;
for (i = 0; i < HAL_MAX_MU_STA_NUM; i++)
for (j = 0; j < HAL_MAX_MU_SCORE_SIZE; j++) {
if (mask == 0x03) {
mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask);
mask = mask <<2;
} else if (mask == 0x0c) {
mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>2;
mask = mask <<2;
} else if (mask == 0x30) {
mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>4;
mask = mask <<2;
} else { /*(mask == 0xc0) */
mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>6;
mask = 0x03;
k++;
}
}
return val;
}
#ifdef HALBB_DYN_L2H_SUPPORT
u32 halbb_c2h_lowrt_rty(struct bb_info *bb, u16 len, u8 *c2h)
{
u32 c2h_rty_cnt = 0;
struct bb_dyn_l2h_info *dyn_l2h_i = &bb->bb_dyn_l2h_i;
c2h_rty_cnt = (*c2h) + ((*(c2h+1))<<8);
dyn_l2h_i->low_rate_rty_cnt += c2h_rty_cnt;
return 0;
}
void halbb_fw_ctrl_rtyrpt(struct bb_info *bb, u8 rpt_rtycnt, u8 en_fw_rpt)
{
struct bb_fw_dbg_cmn_info *fwmn_i = &bb->bb_fwdbg_i;
u32 *bb_h2c = (u32 *) fwmn_i;
u8 cmdlen = sizeof(struct bb_fw_dbg_cmn_info);
bool ret_val = false;
fwmn_i->fw_cmn_info |= (en_fw_rpt & 0x01);
fwmn_i->fw_rty_rpt_ctrl = rpt_rtycnt;
BB_DBG(bb, DBG_FW_INFO, "FW CTRL RTYRPT: %d %d\n", fwmn_i->fw_cmn_info, fwmn_i->fw_rty_rpt_ctrl);
BB_DBG(bb, DBG_FW_INFO, "FW CMN CTRL: %x %x\n", bb_h2c[0], bb_h2c[1]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FWTRACE, HALBB_H2C_DM, bb_h2c);
}
#endif
/* Remove after 8852A B cut */
/*
u32 halbb_c2h_fw_trig_tx_rpt(struct bb_info *bb, u16 len, u8 *c2h)
{
struct bb_c2h_fw_tx_rpt *fw_tx_i = &bb->bb_fwtx_c2h_i;
bool tx_stat = c2h[0] & BIT(0);
u32 val = (u32)false;
if (tx_stat) {
BB_DBG(bb, DBG_FW_INFO, "[FW][C2H] Tx done\n");
} else {
BB_DBG(bb, DBG_FW_INFO, "[FW][C2H] Tx fail\n");
}
// PD hit enable
halbb_set_reg(bb, 0xa3c, BIT(9), 0);
halbb_set_reg(bb, 0xabc, BIT(9), 0);
fw_tx_i->tx_done = tx_stat;
val = (u32)true;
return val;
}*/
u32 halbb_c2h_fw_h2c_test(struct bb_info *bb, u16 len, u8 *c2h)
{
u16 i;
u32 val = (u32)false;
for (i = 0; i < len; i++) {
BB_DBG(bb, DBG_FW_INFO, "FW H2C and C2H test: %d\n", c2h[i]);
}
return val;
}
u32 halbb_c2h_ra_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h)
{
u32 val = 0;
u16 i;
BB_DBG(bb, DBG_FW_INFO, "FW C2H RA parsing: cmdid:%d len:%d\n", cmdid, len);
BB_DBG(bb, DBG_FW_INFO, "FW C2H RA parsing: content ==>");
for (i = 0; i < len; i++)
BB_DBG(bb, DBG_FW_INFO, "%x", *(c2h+i));
BB_DBG(bb, DBG_FW_INFO, "<== \n ");
switch(cmdid) {
case HALBB_C2HRA_STS_RPT:
val = halbb_get_fw_ra_rpt(bb, len, c2h);
break;
case HALBB_C2HRA_MU_GPTBL_RPT:
val = halbb_c2h_mu_gptbl_rpt(bb, len, c2h);
break;
case HALBB_C2HRA_TXSTS:
val = halbb_get_txsts_rpt(bb, len, c2h);
break;
default:
break;
}
return val;
}
u32 halbb_c2h_dm_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h)
{
u32 val = 0;
u16 i;
BB_DBG(bb, DBG_FW_INFO, "FW C2H DM parsing: cmdid:%d len:%d\n", cmdid, len);
BB_DBG(bb, DBG_FW_INFO, "FW C2H DM parsing: content ==>");
for (i = 0; i < len; i++)
BB_DBG(bb, DBG_FW_INFO, "%x", *(c2h+i));
BB_DBG(bb, DBG_FW_INFO, "<== \n ");
switch(cmdid) {
case DM_C2H_FW_TEST:
val = halbb_c2h_fw_h2c_test(bb, len, c2h);
break;
case DM_C2H_FW_TRIG_TX_RPT: /* Remove after 8852A B cut */
break;
#ifdef HALBB_DYN_L2H_SUPPORT
case DM_C2H_LOWRT_RTY:
val = halbb_c2h_lowrt_rty(bb, len, c2h);
break;
#endif
#ifdef HALBB_DIG_MCC_SUPPORT
case DM_C2H_MCC_DIG:
val = halbb_c2h_mccdm_check(bb, len, c2h);
break;
#endif
default:
break;
}
return val;
}
u32 rtw_halbb_c2h_parsing(struct bb_info *bb, u8 classid, u8 cmdid, u16 len, u8 *c2h)
{
u32 val = 0;
switch(classid) {
case HALBB_C2H_RUA:
break;
case HALBB_C2H_RA:
val = halbb_c2h_ra_parsing(bb, cmdid, len, c2h);
break;
case HALBB_C2H_DM:
val = halbb_c2h_dm_parsing(bb, cmdid, len, c2h);
break;
default:
break;
}
return val;
}
u8 halbb_set_cmac_txpwr_mode(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
/* power by macid */
return 0;
}
u8 halbb_set_cmac_ntx_en(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 1;
}
u8 halbb_set_cmac_path_map_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 0;
}
u8 halbb_set_cmac_path_map_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 1;
}
u8 halbb_set_cmac_path_map_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 2;
}
u8 halbb_set_cmac_path_map_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 3;
}
u8 halbb_set_cmac_antsel_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
/* antenna selection*/
return 0;
}
u8 halbb_set_cmac_antsel_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 0;
}
u8 halbb_set_cmac_antsel_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 0;
}
u8 halbb_set_cmac_antsel_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 0;
}
u8 halbb_set_cmac_pwr_tol(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
return 0;
}
u8 halbb_set_cmac_databw_er(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
/* 0: RU242, 1:RU106*/
return 0;
}
bool halbb_set_pwr_by_rate_tbl(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
struct halbb_pwr_by_rate_tbl pwr_t = {{0}};
u8 i = 0;
enum rtw_data_rate ru_pwr_rate[PWR_TBL_NUM] = {RTW_DATA_RATE_HE_NSS1_MCS0,
RTW_DATA_RATE_HE_NSS1_MCS1, RTW_DATA_RATE_HE_NSS1_MCS2,
RTW_DATA_RATE_HE_NSS1_MCS3, RTW_DATA_RATE_HE_NSS1_MCS4,
RTW_DATA_RATE_HE_NSS1_MCS5, RTW_DATA_RATE_HE_NSS1_MCS6,
RTW_DATA_RATE_HE_NSS1_MCS7, RTW_DATA_RATE_HE_NSS1_MCS8,
RTW_DATA_RATE_HE_NSS1_MCS9, RTW_DATA_RATE_HE_NSS1_MCS10,
RTW_DATA_RATE_HE_NSS1_MCS11, RTW_DATA_RATE_HE_NSS2_MCS0,
RTW_DATA_RATE_HE_NSS2_MCS1, RTW_DATA_RATE_HE_NSS2_MCS2,
RTW_DATA_RATE_HE_NSS2_MCS3, RTW_DATA_RATE_HE_NSS2_MCS4,
RTW_DATA_RATE_HE_NSS2_MCS5, RTW_DATA_RATE_HE_NSS2_MCS6,
RTW_DATA_RATE_HE_NSS2_MCS7, RTW_DATA_RATE_HE_NSS2_MCS8,
RTW_DATA_RATE_HE_NSS2_MCS9, RTW_DATA_RATE_HE_NSS2_MCS10,
RTW_DATA_RATE_HE_NSS2_MCS11, RTW_DATA_RATE_HE_NSS1_MCS0,
RTW_DATA_RATE_HE_NSS1_MCS1, RTW_DATA_RATE_HE_NSS1_MCS3,
RTW_DATA_RATE_HE_NSS1_MCS4, RTW_DATA_RATE_HE_NSS2_MCS0,
RTW_DATA_RATE_HE_NSS2_MCS1, RTW_DATA_RATE_HE_NSS2_MCS3,
RTW_DATA_RATE_HE_NSS2_MCS4};
u32 *pval = (u32 *)&pwr_t;
u8 cmdlen = sizeof(pwr_t);
u8 dcm = 0;
enum rtw_data_rate rate;
enum channel_width bw = phl_sta_i->chandef.bw;
u8 channel = phl_sta_i->chandef.center_ch;
s16 pwr_db = 0;
for (i = 0; i < PWR_TBL_NUM; i++) {
rate = ru_pwr_rate[i];
if (i >=24)
dcm = 1;
/*rtw_hal_rf_read_pwr_table(bb->hal_com, 0, rate, bw, channel, 0, dcm, 0, &pwr_db);*/
pwr_t.pwr_by_rate[i*2] = (u8)(pwr_db&0xff);
pwr_t.pwr_by_rate[i*2+1] = (u8)((pwr_db>>8)&0xff);
}
/* Get pwr by rate tbl from halrf */
halbb_fill_h2c_cmd(bb, cmdlen, RUA_H2C_PWR_TBL, HALBB_H2C_RUA, pval);
return false;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_interface.c
|
C
|
agpl-3.0
| 14,467
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_INTERFACE_H__
#define __HALBB_INTERFACE_H__
/*@--------------------------[Define] ---------------------------------------*/
/*[IO Reg]*/
#define BB_OFST 0x10000
#define HALBB_SET_CR_CMN(bb, cr, val, phy_idx) halbb_set_reg_cmn(bb, cr, cr##_M, val, phy_idx);
#define HALBB_SET_CR(bb, cr, val) halbb_set_reg(bb, cr, cr##_M, val);
#define HALBB_GET_CR_CMN(bb, cr, val, phy_idx) halbb_get_reg_cmn(bb, cr, cr##_M, phy_idx);
#define HALBB_GET_CR(bb, cr) halbb_get_reg(bb, cr, cr##_M);
#define halbb_get_32(bb, addr) hal_read32((bb)->hal_com, (addr | BB_OFST))
#define halbb_get_16(bb, addr) hal_read16((bb)->hal_com, (addr | BB_OFST))
#define halbb_get_8(bb, addr) hal_read8((bb)->hal_com, (addr | BB_OFST))
#define halbb_set_32(bb, addr, val) hal_write32((bb)->hal_com, (addr | BB_OFST), val)
#define halbb_set_16(bb, addr, val) hal_write16((bb)->hal_com, (addr | BB_OFST), val)
#define halbb_set_8(bb, addr, val) hal_write8((bb)->hal_com, (addr | BB_OFST), val)
#define halbb_read_mem(bb, addr, cnt, pmem) hal_read_mem((bb)->hal_com, addr, cnt, pmem)
/*[Delay]*/
#define halbb_delay_ms(bb, ms) _os_delay_ms(bb->hal_com->drv_priv, ms)
#define halbb_delay_us(bb, us) _os_delay_us(bb->hal_com->drv_priv, us)
/*[Memory Access]*/
#define halbb_mem_alloc(bb, buf_sz) _os_mem_alloc(bb->hal_com->drv_priv, buf_sz)
#define halbb_mem_free(bb, buf, buf_sz) _os_mem_free(bb->hal_com->drv_priv, (void *)buf, buf_sz)
#define halbb_mem_set(bb, buf, value, size) _os_mem_set(bb->hal_com->drv_priv, (void *)buf, value, size)
#define halbb_mem_cpy(bb, dest, src, size) _os_mem_cpy(bb->hal_com->drv_priv, (void *)dest, (void *)src, size)
#define halbb_mem_cmp(bb, dest, src, size) _os_mem_cmp(bb->hal_com->drv_priv, (void *)dest, (void *)src, size)
/*[Timer]*/
#ifdef HALBB_TIMER_SUPPORT
#define halbb_timer_list _os_timer
#define halbb_init_timer(bb, timer, call_back_func, context, sz_id) _os_init_timer(bb->hal_com->drv_priv, timer, call_back_func, context, sz_id)
#define halbb_set_timer(bb, timer, ms_delay) _os_set_timer(bb->hal_com->drv_priv, timer, ms_delay)
#define halbb_cancel_timer(bb, timer) _os_cancel_timer(bb->hal_com->drv_priv, timer)
#define halbb_release_timer(bb, timer) _os_release_timer(bb->hal_com->drv_priv, timer)
#else
#define halbb_timer_list u8
#define halbb_init_timer(bb, timer, call_back_func, context, sz_id)
#define halbb_set_timer(bb, timer, ms_delay)
#define halbb_cancel_timer(bb, timer)
#define halbb_release_timer(bb, timer)
#endif
/*[Efuse]*/
#ifndef RTW_FLASH_98D
#define halbb_efuse_get_info(bb, info_type, value, size) rtw_hal_efuse_get_info(bb->hal_com, info_type, (void *)value, size)
#else
#define halbb_efuse_get_info(bb, info_type, value, size) rtw_hal_flash_get_info(bb->hal_com, info_type, (void *)value, size)
#endif
#define halbb_phy_efuse_get_info(bb, addr, size, value) rtw_hal_mac_read_phy_efuse(bb->hal_com, addr, size, value)
/*[String]*/
#define halbb_snprintf _os_snprintf
/*[PwrTable]*/
#define PWR_TBL_NUM 32
#define NUM_HE_MCS 12
#define NUM_DCM_MCS 4
/*@--------------------------[Enum]------------------------------------------*/
enum bb_timer_cfg_t {
BB_INIT_TIMER = 0,
BB_CANCEL_TIMER = 1,
BB_RELEASE_TIMER = 2,
BB_SET_TIMER = 3
};
enum halbb_h2c_ra_cmdid {
RA_H2C_MACIDCFG = 0x0,
RA_H2C_RSSISETTING = 0x1,
RA_H2C_GET_TXSTS = 0x2,
RA_H2C_RA_ADJUST = 0x3,
RA_H2C_MUCFG = 0x10,
RA_MAX_H2CCMD
};
enum halbb_h2c_rua_cmdid {
RUA_H2C_TABLE = 0x0,
RUA_H2C_SWGRP = 0x1,
RUA_H2C_DL_MACID = 0x2,
RUA_H2C_UL_MACID = 0x3,
RUA_H2C_CSIINFO = 0x4,
RUA_H2C_CQI = 0x5,
RUA_H2C_BBINFO = 0x6,
RUA_H2C_SEN_TBL = 0x7,
RUA_H2C_PWR_TBL = 0x8,
RUA_MAX_H2CCMD
};
enum halbb_h2c_classid {
HALBB_H2C_RUA = 0x0,
HALBB_H2C_RA = 0x1,
HALBB_H2C_DM = 0x2,
HALBB_MAX_H2CCMD
};
enum halbb_h2c_dm_cmdid {
DM_H2C_FWTRACE = 0x0,
DM_H2C_FW_TRIG_TX = 0x1,
DM_H2C_FW_HE_SIGB = 0x2,
DM_H2C_FW_H2C_TEST = 0x3,
DM_H2C_FW_EDCCA = 0x4,
DM_H2C_FW_CMW = 0x5,
DM_H2C_FW_MCC = 0x6,
DM_MAX_H2CCMD
};
enum halbb_c2h_classid {
HALBB_C2H_RUA = 0x0,
HALBB_C2H_RA = 0x1,
HALBB_C2H_DM = 0x2,
HALBB_MAX_C2HCMD
};
enum halbb_c2h_ra_cmdid {
HALBB_C2HRA_STS_RPT = 0x0,
HALBB_C2HRA_MU_GPTBL_RPT = 0x1,
HALBB_C2HRA_TXSTS = 0x2,
HALBB_MAX_C2HRACMD
};
enum halbb_c2h_dm_cmdid {
DM_C2H_FW_TEST = 0x0,
DM_C2H_FW_TRIG_TX_RPT = 0x1,
DM_C2H_SIGB = 0x2,
DM_C2H_LOWRT_RTY = 0x3,
DM_C2H_MCC_DIG = 0x4,
HALBB_MAX_C2HDMCMD
};
enum halbb_event_idx_t {
/*timer*/
BB_EVENT_TIMER_DIG = 0,
BB_EVENT_TIMER_CFO = 1,
BB_EVENT_TIMER_ANTDIV = 2,
BB_EVENT_TIMER_TDMA_CR = 3
};
enum halbb_timer_state_t {
/*timer*/
BB_TIMER_IDLE = 0,
BB_TIMER_RUN = 1,
BB_TIMER_RELEASE = 0xff,
};
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_timer_info {
halbb_timer_list timer_list;
u32 cb_time; /*callback time (ms)*/
enum halbb_event_idx_t event_idx;
enum halbb_timer_state_t timer_state;
};
struct halbb_pwr_by_rate_tbl {
u8 pwr_by_rate[PWR_TBL_NUM*2];
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_cfg_timers(struct bb_info *bb, enum bb_timer_cfg_t cfg,
struct halbb_timer_info *timer);
u32 halbb_get_sys_time(struct bb_info *bb);
u32 halbb_phy0_to_phy1_ofst(struct bb_info *bb, u32 addr);
void halbb_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val,
enum phl_phy_idx phy_idx);
void halbb_set_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 val);
u32 halbb_get_reg_cmn(struct bb_info *bb, u32 addr, u32 mask,
enum phl_phy_idx phy_idx);
u32 halbb_get_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 *val_1);
bool halbb_fill_h2c_cmd(struct bb_info *bb, u16 cmdlen, u8 cmdid,
u8 classid, u32 *pval);
bool halbb_test_h2c_c2h_flow(struct bb_info *bb);
bool halbb_check_fw_ofld(struct bb_info *bb);
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lst_cmd);
bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val,
enum phl_phy_idx phy_idx, u8 lst_cmd);
bool halbb_fw_set_rf_reg(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_interface.h
|
C
|
agpl-3.0
| 7,150
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_INTERFACE_EX_H__
#define __HALBB_INTERFACE_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val);
u32 halbb_get_reg(struct bb_info *bb, u32 addr, u32 bit_mask);
u32 rtw_halbb_c2h_parsing(struct bb_info *bb, u8 classid, u8 cmdid, u16 len, u8 *c2h);
u8 halbb_set_cmac_txpwr_mode(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_ntx_en(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_path_map_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_path_map_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_path_map_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_path_map_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_antsel_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_antsel_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_antsel_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_antsel_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_pwr_tol(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_set_cmac_databw_er(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_interface_ex.h
|
C
|
agpl-3.0
| 2,631
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_LA_MODE_SUPPORT
#define LAMODE_ECHO_CMD 1
#define LAMODE_MAIN 1
#define SET_BB_TRIG_RULE 1
#define SET_BB_DMA_FMT 1
#define SET_MAC_CFG 1
#define SET_MAC_TRIG 1
#define SET_MAC_GET_BUF_RPT 1
#if (SET_MAC_GET_BUF_RPT)
u8 halbb_la_ptrn_chk(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
u32 i = 0, idx = 0;
u8 ptrn_match = 1;
u8 ptrn_match_num = 0;
u32 shift = 0;
u32 point_tmp = 0;
u32 mask_tmp = 0;
u32 val_tmp = 0;
u32 data_msb_tmp = 0;
for (i = 0; i < LA_CHK_PTRN_NUM; i++) {
BB_TRACE("[%d] point=%05d, chk_mask=0x%08x, chk_val=0x%x\n",
i, la->la_ptrn_chk_i[i].smp_point,
la->la_ptrn_chk_i[i].la_ptrn_chk_mask,
la->la_ptrn_chk_i[i].la_ptrn_chk_val);
}
BB_TRACE("==========================>\n");
for (i = 0; i < LA_CHK_PTRN_NUM; i++) {
if (la->la_ptrn_chk_i[i].la_ptrn_chk_mask == 0)
continue;
point_tmp = la->la_ptrn_chk_i[i].smp_point;
mask_tmp = la->la_ptrn_chk_i[i].la_ptrn_chk_mask;
val_tmp = la->la_ptrn_chk_i[i].la_ptrn_chk_val;
idx = point_tmp << 1;
data_msb_tmp = buf->octet[idx + 1];
BB_TRACE("[%d] [Point:%d] %08x | %08x\n",
i, point_tmp, buf->octet[idx + 1], buf->octet[idx]);
if (mask_tmp != MASKDWORD)
shift = halbb_cal_bit_shift(mask_tmp);
if ((data_msb_tmp & mask_tmp) == (val_tmp << shift)) {
ptrn_match_num++;
BB_TRACE("pattern[%d] match\n", i);
} else {
ptrn_match &= 0;
BB_TRACE("pattern[%d] NOT match\n", i);
}
}
if (ptrn_match_num == 0)
ptrn_match = 0;
BB_TRACE("pattern_match=%d, ptrn_match_num=%d\n", ptrn_match, ptrn_match_num);
return ptrn_match;
}
void halbb_la_rpt_buf_get(struct bb_info *bb, u16 finish_ofst, bool is_round_up)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
bool la_ptrn_match;
u32 i = 0;
u32 addr = 0, start_addr = 0, finish_addr = 0; /* @(unit: Byte)*/
u32 round_up_size = 0;
u32 finish_ofst_byte = 0;
u8 *la_data;
if (la->la_mode_state != LA_STATE_GET_DLE_BUF) {
BB_WARNING("[%s]\n", __func__);
return;
}
BB_TRACE("[%s]\n", __func__);
/*@==== [Get LA Report] ==============================================*/
finish_ofst_byte = ((u32)finish_ofst) << 3;
finish_addr = buf->start_pos + finish_ofst_byte;
BB_TRACE("start_addr = ((0x%x)), end_addr = ((0x%x)), buf_size = ((0x%x))\n",
buf->start_pos, buf->end_pos, buf->buffer_size);
if (is_round_up) {
start_addr = finish_addr;
round_up_size = buf->end_pos - start_addr;
BB_TRACE("[Round_up:1] round_up_point=(%d)\n", finish_ofst); /*@Byte to 8Byte*/
BB_TRACE("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n",
buf->start_pos, finish_addr, buf->end_pos);
la->smp_number = buf->smp_number_max;
} else {
start_addr = buf->start_pos;
BB_TRACE("[Round_up:0]\n");
BB_TRACE("buf_start(0x%x)|------->|finish_addr(0x%x) |buf_end(0x%x)\n",
buf->start_pos, finish_addr, buf->end_pos);
la->smp_number = DIFF_2(start_addr, finish_addr) >> 3;
}
BB_TRACE("smp_num=(%d)\n", la->smp_number);
/*@==== [Get LA Patterns in TXFF] ====================================*/
BB_TRACE("Dump_Start\n");
if (!buf->octet)
return;
la_data = (u8 *)buf->octet;
if (is_round_up) {
/*BB_TRACE("0x%x + 0x%x = 0x%x, 0x%x\n", round_up_size, finish_ofst_byte + 8, (round_up_size + finish_ofst_byte + 8), buf->buffer_size);*/
rtw_hal_mac_get_buffer_data(bb->hal_com, start_addr, la_data, round_up_size, 1);
la_data += round_up_size;
}
rtw_hal_mac_get_buffer_data(bb->hal_com, buf->start_pos, la_data, finish_ofst_byte, 1);
la_ptrn_match = halbb_la_ptrn_chk(bb);
BB_TRACE("[Dump_End], la_ptrn_match=%d\n", la_ptrn_match);
}
#endif
#if (SET_MAC_CFG)
void halbb_la_set_mac_trig_time(struct bb_info *bb, u32 trig_time, u8 *unit, u8 *unit_num)
{
u32 ref_time = 128;
u8 time_unit_num = 0;
u8 i;
/*mac_la_tgr_tu_sel: 0 ~ 2^[0~15] */
/*mac_la_tgr_time_val: 0 ~ 2^7 */
if (trig_time > 0x400000)
trig_time = 0x400000;
for (i = 0; i < 16; i++) {
if (trig_time <= (ref_time << i)) {
*unit = i;
break;
}
}
*unit_num = (u8)(trig_time >> *unit);
BB_DBG(bb, DBG_DBG_API, "2. [Set Trig-Time] Time=%d * unit=2^%d us\n",
*unit_num, *unit);
}
bool halbb_la_mac_cfg_buf(struct bb_info *bb, enum la_buff_mode_t mode)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i;
struct la_string_info *buf = &la->la_string_i;
u32 addr_start = 0;
u32 addr_end = 0;
u32 buf_size_tmp = 0;
switch (bb->ic_type) {
case BB_RTL8852AA:
case BB_RTL8852A:
if (mode == LA_BUFF_256K)
buf->buffer_size = 0x40000; /*2^18=(2^8)*(2^10)=256K Byte*/
else if(mode == LA_BUFF_192K)
buf->buffer_size = 0x30000;
else
buf->buffer_size = 0;
break;
case BB_RTL8852B:
if (mode == LA_BUFF_128K && bb->hal_com->cv == CAV)
buf->buffer_size = 0x20000; /*2^17=(2^7)*(2^10)=128K Byte*/
else if (mode == LA_BUFF_64K && bb->hal_com->cv >= CBV)
buf->buffer_size = 0x10000; /*2^16=(2^6)*(2^10)=64K Byte*/
else
buf->buffer_size = 0;
break;
default:
BB_WARNING("[%s] IC\n", __func__);
buf->buffer_size = 0;
break;
}
if (buf->buffer_size == 0) {
BB_WARNING("[%s] Buf=0\n", __func__);
return false;
}
rtw_hal_mac_lamode_cfg_buf(bb->hal_com, cfg->mac_la_buf_sel, &addr_start, &addr_end);
buf->start_pos = addr_start;
buf->end_pos = addr_end;
buf_size_tmp = buf->end_pos - buf->start_pos;
if (buf_size_tmp != buf->buffer_size) {
BB_WARNING("buf_size_tmp=0x%x, buffer_size=0x%x\n",
buf_size_tmp, buf->buffer_size);
return false;
}
buf->smp_number_max = buf->buffer_size >> 3;
BB_TRACE("addr=[0x%x ~ 0x%x], buf_size=(%d K), smp_num_max=(%d)\n",
buf->start_pos, buf->end_pos, (buf->buffer_size >> 10),
buf->smp_number_max);
return true;
}
bool halbb_la_mac_cfg_buf_default(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
enum la_buff_mode_t mode;
switch (bb->ic_type) {
case BB_RTL8852A:
mode = LA_BUFF_256K;
break;
case BB_RTL8852B:
if (bb->hal_com->cv == CAV)
mode = LA_BUFF_128K;
else
mode = LA_BUFF_64K;
break;
case BB_RTL8852C:
mode = LA_BUFF_256K; /*TBD*/
break;
default:
return false;
}
la->la_mac_cfg_i.mac_la_buf_sel = mode;
BB_TRACE("Auto Init MAC BUF CR, mode=(%d)K\n", 64 * (mode + 1));
return halbb_la_mac_cfg_buf(bb, mode);
}
void halbb_la_mac_cfg_cmn(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i;
u8 t_unit = 0, t_unit_num = 0;
cfg->mac_la_en = (cfg->mac_la_buf_sel == LA_BUF_DISABLE) ? 0 : 1;
halbb_la_set_mac_trig_time(bb, cfg->la_trigger_time, &t_unit, &t_unit_num);
rtw_hal_mac_lamode_cfg(bb->hal_com, cfg->mac_la_en, cfg->mac_la_restart_en,
cfg->mac_la_timeout_en, cfg->mac_la_timeout_val,
cfg->mac_la_data_loss_imr, t_unit, t_unit_num);
}
void halbb_la_mac_init(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i;
/*[MAC Buf]*/
//cfg->mac_la_buf_sel = LA_BUFF_256K;
//halbb_la_mac_cfg_buf(bb, cfg->mac_la_buf_sel);
/*[MAC Common]*/
halbb_la_mac_cfg_cmn(bb);
}
#endif
#if SET_MAC_TRIG
void halbb_la_mac_set_adv_reset(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i;
halbb_mem_set(bb, trig_mac, 0, sizeof(struct la_trig_mac_info));
}
void halbb_la_mac_set_trig(struct bb_info *bb, bool mac_trig_en)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i;
struct bb_la_cr_info *cr = &la->bb_la_cr_i;
BB_TRACE(" *[%s]\n", __func__);
if (!mac_trig_en) {
/*MAC_AND0*/
halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m, 0);
/*MAC_AND1*/
halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m, 0);
/*MAC_AND2*/
halbb_set_reg(bb, cr->la_mac_and2_en, cr->la_mac_and2_en_m, 0);
return;
}
halbb_set_reg(bb, cr->la_mac_and0_en, cr->la_mac_and0_en_m,
trig_mac->la_mac_and0_en);
halbb_set_reg(bb, cr->la_mac_and0_sel, cr->la_mac_and0_sel_m,
trig_mac->la_mac_and0_sel);
halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(16), 0);
if (trig_mac->la_mac_and0_sel == 1)
halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(22),
trig_mac->la_mac_and0_mac_sel);
else if (trig_mac->la_mac_and0_sel == 2)
halbb_set_reg(bb, cr->la_mac_and0_mac_sel, BIT(23),
trig_mac->la_mac_and0_mac_sel);
halbb_set_reg(bb, cr->la_mac_and1_en, cr->la_mac_and1_en_m,
trig_mac->la_mac_and1_en);
halbb_set_reg(bb, cr->la_mac_and2_en, cr->la_mac_and2_en_m,
trig_mac->la_mac_and2_en);
halbb_set_reg(bb, 0xd04, 0xf, trig_mac->la_mac_and2_frame_sel); /*HW error*/
}
#endif
#if (SET_BB_DMA_FMT)
void halbb_la_bb_set_dma_type(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
struct bb_la_cr_info *cr = &la->bb_la_cr_i;
u32 la_en = 1;
u32 r_dma_rdrdy = 0;
if (la->la_smp_rate == LA_SMP_CLK_160) {
dma->dma_a_ck160_dly_en = 1;
dma->dma_b_ck160_dly_en = 1;
dma->dma_c_ck160_dly_en = 1;
dma->dma_d_ck160_dly_en = 1;
} else {
dma->dma_a_ck160_dly_en = 0;
dma->dma_b_ck160_dly_en = 0;
dma->dma_c_ck160_dly_en = 0;
dma->dma_d_ck160_dly_en = 0;
}
halbb_set_reg(bb, cr->la_en, cr->la_en_m, la_en);
halbb_set_reg(bb, cr->dma_dbgport_base_n, cr->dma_dbgport_base_n_m,
dma->dma_dbgport_base_n);
halbb_set_reg(bb, cr->dma_a_path_sel, cr->dma_a_path_sel_m,
dma->dma_a_path_sel);
halbb_set_reg(bb, cr->dma_b_path_sel, cr->dma_b_path_sel_m,
dma->dma_b_path_sel);
halbb_set_reg(bb, cr->dma_c_path_sel, cr->dma_c_path_sel_m,
dma->dma_c_path_sel);
halbb_set_reg(bb, cr->dma_d_path_sel, cr->dma_d_path_sel_m,
dma->dma_d_path_sel);
halbb_set_reg(bb, cr->dma_a_src_sel, cr->dma_a_src_sel_m,
dma->dma_a_src_sel);
halbb_set_reg(bb, cr->dma_b_src_sel, cr->dma_b_src_sel_m,
dma->dma_b_src_sel);
halbb_set_reg(bb, cr->dma_c_src_sel, cr->dma_c_src_sel_m,
dma->dma_c_src_sel);
halbb_set_reg(bb, cr->dma_d_src_sel, cr->dma_d_src_sel_m,
dma->dma_d_src_sel);
halbb_set_reg(bb, cr->dma_hdr_sel_63, cr->dma_hdr_sel_63_m,
dma->dma_hdr_sel_63);
halbb_set_reg(bb, cr->dma_hdr_sel_62, cr->dma_hdr_sel_62_m,
dma->dma_hdr_sel_62);
halbb_set_reg(bb, cr->dma_hdr_sel_61, cr->dma_hdr_sel_61_m,
dma->dma_hdr_sel_61);
halbb_set_reg(bb, cr->dma_hdr_sel_60, cr->dma_hdr_sel_60_m,
dma->dma_hdr_sel_60);
halbb_set_reg(bb, cr->dma_a_ck160_dly_en, cr->dma_a_ck160_dly_en_m,
dma->dma_a_ck160_dly_en);
halbb_set_reg(bb, cr->dma_b_ck160_dly_en, cr->dma_b_ck160_dly_en_m,
dma->dma_b_ck160_dly_en);
halbb_set_reg(bb, cr->dma_dbgport_phy_sel, cr->dma_dbgport_phy_sel_m,
dma->dma_dbgport_phy_sel);
halbb_set_reg(bb, cr->dma_data_type, cr->dma_data_type_m,
dma->dma_data_type);
halbb_set_reg(bb, cr->r_dma_rdrdy, cr->r_dma_rdrdy_m, r_dma_rdrdy);
}
void halbb_la_bb_set_dma_type_reset(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
dma->dma_dbgport_base_n = 0;
dma->dma_a_path_sel = 0;
dma->dma_b_path_sel = 1;
dma->dma_c_path_sel = 2;
dma->dma_d_path_sel = 3;
dma->dma_a_src_sel = 3;
dma->dma_b_src_sel = 3;
dma->dma_c_src_sel = 3;
dma->dma_d_src_sel = 3;
dma->dma_dbgport_phy_sel = 0;
dma->dma_hdr_sel_63 = 1;
dma->dma_hdr_sel_62 = 4;
dma->dma_hdr_sel_61 = 8;
dma->dma_hdr_sel_60 = 13;
dma->dma_data_type = 1;
}
#endif
#if SET_BB_TRIG_RULE
void halbb_la_bb_set_adv_reset(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_adv_trig_info *adv = &la->adv_trig_i;
halbb_mem_set(bb, adv, 0, sizeof(struct la_adv_trig_info));
}
void halbb_la_bb_set_cmn_reset(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
la->la_trigger_cnt = 0;
la->la_dbg_port = 0x10205;
la->la_trigger_edge = 0;
la->la_smp_rate = LA_SMP_CLK_80;
la->la_mac_cfg_i.la_trigger_time = 404;
la->la_polling_cnt = 20;
la->la_and0_disable = true;
}
void halbb_la_bb_set_re_trig_reset(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_re_trig_info *re_trig = &la->la_re_trig_i;
halbb_mem_set(bb, re_trig, 0, sizeof(struct la_re_trig_info));
if (bb->ic_type == BB_RTL8852AA)
re_trig->la_re_and0_sel = 2;
}
void halbb_la_bb_set_re_trig(struct bb_info *bb, bool re_trig_en)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_re_trig_info *re_trig = &la->la_re_trig_i;
struct rtw_hal_com_t *hal_i = bb->hal_com;
struct bb_la_cr_info *cr = &la->bb_la_cr_i;
/*Since HW bug, 52A CAV use re-trigger to set LA mode stop condition*/
if (bb->ic_type != BB_RTL8852AA) {
if (!re_trig_en) {
halbb_set_reg(bb, cr->la_re_and1_sel,
cr->la_re_and1_sel_m, 0);/*1b'1*/
halbb_set_reg(bb, cr->la_re_and1_inv,
cr->la_re_and1_inv_m, 1);
return;
}
}
halbb_set_reg(bb, cr->la_re_trig_edge, cr->la_re_trig_edge_m,
re_trig->la_re_trig_edge);
halbb_set_reg(bb, cr->la_re_and1_sel, cr->la_re_and1_sel_m,
re_trig->la_re_and0_sel);
if (re_trig->la_re_and0_sel == 0xf)
halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m,
re_trig->la_re_and0_val);
else
halbb_set_reg(bb, cr->la_re_and1_val, cr->la_re_and1_val_m,
re_trig->la_re_and0_val);
halbb_set_reg(bb, cr->la_re_and1_inv, cr->la_re_and1_inv_m,
re_trig->la_re_and0_inv);
}
void halbb_la_bb_set_trig(struct bb_info *bb, bool and0_trig_disable, bool adv_trig_en, bool not_stop_trig_en)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_adv_trig_info *adv = &la->adv_trig_i;
struct bb_la_cr_info *cr = &la->bb_la_cr_i;
u32 trig_sel = 0;
BB_TRACE(" {and0_trig_disable, adv_trig, not_stop_trig} = {%d, %d, %d}\n",
and0_trig_disable, adv_trig_en, not_stop_trig_en);
/*===== [And-0 Trigger] ==============================================*/
if (and0_trig_disable) {
halbb_set_reg(bb, cr->and0_trig_disable,
cr->and0_trig_disable_m, 1);/*disable=1*/
} else {
if (not_stop_trig_en)
trig_sel = 0; /*set to unchanged BB debug port bit*/
else
trig_sel = la->la_and0_bit_sel;
halbb_set_reg(bb, cr->and0_trig_disable,
cr->and0_trig_disable_m, 0); /*disable=0*/
halbb_set_reg(bb, cr->la_and0_bit_sel, cr->la_and0_bit_sel_m,
trig_sel); /*debug port bit*/
}
BB_TRACE(" *Set dbg_port[BIT] = %d\n", trig_sel);
/*===== [And-1~7 Trigger] ============================================*/
if (!adv_trig_en) { /*normal LA mode & back to default*/
/*AND1*/
halbb_set_reg(bb, cr->la_and1_mask, cr->la_and1_mask_m, 0);
/*AND2*/
halbb_set_reg(bb, cr->la_and2_en, cr->la_and2_en_m, 0);
/*AND3*/
halbb_set_reg(bb, cr->la_and3_en, cr->la_and3_en_m, 0);
/*AND4*/
halbb_set_reg(bb, cr->la_and4_en, cr->la_and4_en_m, 0);
/*AND5*/
halbb_set_reg(bb, cr->la_and5_sel, cr->la_and5_sel_m, 0);
/*AND6*/
halbb_set_reg(bb, cr->la_and6_sel, cr->la_and6_sel_m, 0);
/*AND7*/
halbb_set_reg(bb, cr->la_and7_sel, cr->la_and7_sel_m, 0);
return;
}
/*AND1*/
halbb_set_reg(bb, cr->la_and1_mask, cr->la_and1_mask_m,
adv->la_and1_mask);
halbb_set_reg(bb, cr->la_and1_inv, cr->la_and1_inv_m, adv->la_and1_inv);
halbb_set_reg(bb, cr->la_and1_val, cr->la_and1_val_m, adv->la_and1_val);
/*AND2*/
halbb_set_reg(bb, cr->la_and2_en, cr->la_and2_en_m, adv->la_and2_en);
halbb_set_reg(bb, cr->la_and2_inv, cr->la_and2_inv_m, adv->la_and2_inv);
halbb_set_reg(bb, cr->la_and2_val, cr->la_and2_val_m, adv->la_and2_val);
halbb_set_reg(bb, cr->la_and2_mask, cr->la_and2_mask_m,
adv->la_and2_mask);
halbb_set_reg(bb, cr->la_and2_sign, cr->la_and2_sign_m,
adv->la_and2_sign);
/*AND3*/
halbb_set_reg(bb, cr->la_and3_en, cr->la_and3_en_m, adv->la_and3_en);
halbb_set_reg(bb, cr->la_and3_inv, cr->la_and3_inv_m, adv->la_and3_inv);
halbb_set_reg(bb, cr->la_and3_val, cr->la_and3_val_m, adv->la_and3_val);
halbb_set_reg(bb, cr->la_and3_mask, cr->la_and3_mask_m,
adv->la_and3_mask);
halbb_set_reg(bb, cr->la_and3_sign, cr->la_and3_sign_m,
adv->la_and3_sign);
/*AND4*/
halbb_set_reg(bb, cr->la_and4_en, cr->la_and4_en_m, adv->la_and4_en);
halbb_set_reg(bb, cr->la_and4_inv, cr->la_and4_inv_m, adv->la_and4_inv);
halbb_set_reg(bb, cr->la_and4_rate, cr->la_and4_rate_m,
adv->la_and4_rate);
/*AND5*/
halbb_set_reg(bb, cr->la_and5_sel, cr->la_and5_sel_m, adv->la_and5_sel);
halbb_set_reg(bb, cr->la_and5_inv, cr->la_and5_inv_m, adv->la_and5_inv);
if (adv->la_and5_sel == 0xf)
halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m,
adv->la_and5_val);
else
halbb_set_reg(bb, cr->la_and5_val, cr->la_and5_val_m,
adv->la_and5_val);
/*AND6*/
halbb_set_reg(bb, cr->la_and6_sel, cr->la_and6_sel_m, adv->la_and6_sel);
halbb_set_reg(bb, cr->la_and6_inv, cr->la_and6_inv_m, adv->la_and6_inv);
if (adv->la_and6_sel == 0xf)
halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m,
adv->la_and6_val);
else
halbb_set_reg(bb, cr->la_and6_val, cr->la_and6_val_m,
adv->la_and6_val);
/*AND7*/
halbb_set_reg(bb, cr->la_and7_sel, cr->la_and7_sel_m, adv->la_and7_sel);
halbb_set_reg(bb, cr->la_and7_inv, cr->la_and7_inv_m, adv->la_and7_inv);
if (adv->la_and7_sel == 0xf)
halbb_set_reg(bb, cr->la_brk_sel, cr->la_brk_sel_m,
adv->la_and7_val);
else
halbb_set_reg(bb, cr->la_and7_val, cr->la_and7_val_m,
adv->la_and7_val);
}
void halbb_la_bb_set_dbg_port(struct bb_info *bb, bool not_stop_trig_en)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
u32 trig_sel = la->la_and0_bit_sel;
u32 dbg_port = la->la_dbg_port;
/*===== [And-0 Trigger] ====================*/
/*set to unchanged BB debug port*/
if (not_stop_trig_en) {
dbg_port = 0xf;
trig_sel = 0;
BB_TRACE("[BB Setting] not stop trigger!\n");
}
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
halbb_set_bb_dbg_port_ip(bb, (dbg_port & 0xff0000) >> 16);
halbb_set_bb_dbg_port(bb, dbg_port & 0xffff);
BB_TRACE(" *Set dbg_port=(0x%x)\n", dbg_port);
} else {
dbg_port = halbb_get_bb_dbg_port_idx(bb);
BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
}
}
void halbb_la_bb_set_general(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
struct bb_la_cr_info *cr = &la->bb_la_cr_i;
u32 rdrdy_3_phase_en = 0;
u32 la_top_trig = 1;
BB_TRACE("3. [BB Setting] Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n",
(la->la_trigger_edge == 0) ? "P" : "N",
80 >> la->la_smp_rate, dma->dma_data_type);
rdrdy_3_phase_en = (dma->dma_data_type == DMA13_MPHS_1s_3p_10b) ? 1 : 0;
halbb_set_reg(bb, cr->la_trigger_edge, cr->la_trigger_edge_m,
la->la_trigger_edge);
halbb_set_reg(bb, cr->rdrdy_3_phase_en, cr->rdrdy_3_phase_en_m,
rdrdy_3_phase_en);
halbb_set_reg(bb, cr->la_smp_rate, cr->la_smp_rate_m, la->la_smp_rate);
halbb_set_reg(bb, cr->la_trigger_cnt, cr->la_trigger_cnt_m,
la->la_trigger_cnt);
halbb_set_reg(bb, cr->la_clk_en, cr->la_clk_en_m, la_top_trig);
}
#endif
#if (LAMODE_MAIN)
void
halbb_la_drv_buf_release(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
if (buf->length != 0 && buf->octet) {
halbb_mem_free(bb, buf->octet, buf->buffer_size);
buf->length = 0;
}
}
bool
halbb_la_drv_buf_allocate(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
bool ret = true;
BB_TRACE("[LA mode BufferAllocate]\n");
if (buf->length == 0) {
buf->octet = (u32 *)halbb_mem_alloc(bb, buf->buffer_size);
if (!buf->octet)
ret = false;
if (ret)
buf->length = buf->buffer_size;
}
return ret;
}
void halbb_la_stop(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
la->la_mode_state = LA_STATE_IDLE;
}
void halbb_la_main(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i;
u8 mac_rpt_state = LA_HW_IDLE;
u32 mac_trig_fail;
u8 tmp_u1b = 0;
u8 i = 0;
u16 finish_ofst = 0;
bool round_up = 0;
bool loss_data;
if (la->la_mode_state != LA_STATE_MAIN) {
halbb_la_stop(bb);
BB_WARNING("[%s]\n", __func__);
}
BB_TRACE("1. [BB Setting] dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Bit_Sel = ((0x%x)), Dma_type = ((%d))\n",
la->la_dbg_port, la->la_trigger_edge,
la->la_smp_rate, la->la_and0_bit_sel, dma->dma_data_type);
halbb_la_bb_set_general(bb);
halbb_la_bb_set_dma_type(bb);
halbb_la_bb_set_dbg_port(bb, la->not_stop_trig);
halbb_la_bb_set_trig(bb, la->la_and0_disable,
la->adv_trig_i.adv_trig_en, la->not_stop_trig);
halbb_la_bb_set_re_trig(bb, la->la_re_trig_i.re_trig_en);
halbb_la_mac_set_trig(bb, la->la_trig_mac_i.la_mac_trig_en);
halbb_la_mac_cfg_cmn(bb);
if (la->not_stop_trig) {
halbb_delay_ms(bb, 100);
halbb_la_bb_set_dbg_port(bb, false);
}
mac_trig_fail = rtw_hal_mac_lamode_trig(bb->hal_com, 1);
if (!mac_trig_fail) {
do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
rtw_hal_mac_get_lamode_st(bb->hal_com, (u8 *)&mac_rpt_state,
&finish_ofst, &round_up,
&loss_data);
BB_TRACE("[%d] rpt=((0x%x)), finish_ofst =((%d)), round_up =((%d)) \n", i, mac_rpt_state, finish_ofst, round_up);
if (mac_rpt_state == LA_HW_RE_START) {
BB_TRACE("[Restart]\n");
break;
} else if (mac_rpt_state == LA_HW_FINISH_STOP) {
BB_TRACE("[LA Query OK]\n");
break;
} else if (mac_rpt_state == LA_HW_START) {
halbb_delay_ms(bb, 100);
i++;
continue;
} else if (mac_rpt_state == LA_HW_FINISH_TIMEOUT) {
BB_TRACE("[LA HW timeout]\n");
break;
} else { /*LA_HW_IDLE)*/
break;
}
} while (i < la->la_polling_cnt);
if (mac_rpt_state == LA_HW_FINISH_STOP) {
la->la_mode_state = LA_STATE_GET_DLE_BUF;
halbb_la_rpt_buf_get(bb, finish_ofst, round_up);
} else if (mac_rpt_state == LA_HW_RE_START) {
la->la_mode_state = LA_STATE_WAIT_RESTART;
la->la_count = 0;
return;
} else {
BB_TRACE("[Polling Fail]\n");
}
}
halbb_la_stop(bb);
BB_TRACE("[LA mode] la_count = ((%d))\n", la->la_count);
if (la->la_count == 0) {
BB_TRACE("LA Dump finished ---------->\n\n\n");
halbb_release_bb_dbg_port(bb);
} else {
la->la_count--;
BB_TRACE("LA Dump more ---------->\n\n\n");
halbb_la_run(bb);
}
}
void halbb_la_re_trig_watchdog(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
if (la->la_mode_state != LA_STATE_WAIT_RESTART) {
return;
}
la->la_re_trig_i.re_trig_wait_cnt++;
BB_TRACE("re_trig_wait_cnt=(%d)\n", la->la_re_trig_i.re_trig_wait_cnt);
la->la_mode_state = LA_STATE_MAIN;
halbb_la_main(bb);
}
void halbb_la_run(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
bool is_set_success = true;
BB_TRACE("[%s] LA_State=(%d)\n", __func__, la->la_mode_state);
if (!la->la_mac_cfg_i.mac_alloc_success) {
la->la_mac_cfg_i.mac_alloc_success = halbb_la_mac_cfg_buf_default(bb);
if (!la->la_mac_cfg_i.mac_alloc_success) {
BB_WARNING("MAC BUF CR set fail)\n");
return;
}
}
if (la->la_mode_state != LA_STATE_IDLE) {
halbb_la_stop(bb);
return;
}
if (buf->length == 0)
is_set_success = halbb_la_drv_buf_allocate(bb);
if (!is_set_success) {
BB_WARNING("LA_BUf_alloc fail)\n");
return;
}
halbb_mem_set(bb, buf->octet, 0, buf->buffer_size);
la->la_re_trig_i.re_trig_wait_cnt = 0;
la->la_mode_state = LA_STATE_MAIN;
halbb_la_main(bb);
}
void halbb_la_deinit(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
halbb_la_stop(bb);
halbb_la_drv_buf_release(bb);
}
void halbb_la_reset(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *la_string = &la->la_string_i;
la->la_mode_state = LA_STATE_IDLE;
la->la_print_i.is_la_print = false;
la->not_stop_trig = false;
halbb_la_bb_set_cmn_reset(bb);
halbb_la_bb_set_dma_type_reset(bb);
halbb_la_bb_set_adv_reset(bb);
halbb_la_mac_set_adv_reset(bb);
halbb_la_bb_set_re_trig_reset(bb);
halbb_la_mac_init(bb);
}
void halbb_la_init(struct bb_info *bb)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_string_info *buf = &la->la_string_i;
la->la_mac_cfg_i.mac_alloc_success = false;
buf->length = 0;
halbb_la_reset(bb);
halbb_mem_set(bb, la->la_ptrn_chk_i, 0, sizeof(struct la_ptrn_chk_info) * LA_CHK_PTRN_NUM);
}
void halbb_cr_cfg_la_init(struct bb_info *bb)
{
struct bb_la_cr_info *cr = &bb->bb_cmn_hooker->bb_la_mode_i.bb_la_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_52AA_SERIES
case BB_52AA:
cr->la_clk_en = LA_CKEN_52AA;
cr->la_clk_en_m = LA_CKEN_52AA_M;
cr->la_en = LA_EN_52AA;
cr->la_en_m = LA_EN_52AA_M;
cr->dma_dbgport_base_n = LA_DBGPORT_BASE_N_52AA;
cr->dma_dbgport_base_n_m = LA_DBGPORT_BASE_N_52AA_M;
cr->dma_a_path_sel = LA_TYPEA_PATH_SEL_52AA;
cr->dma_a_path_sel_m = LA_TYPEA_PATH_SEL_52AA_M;
cr->dma_b_path_sel = LA_TYPEB_PATH_SEL_52AA;
cr->dma_b_path_sel_m = LA_TYPEB_PATH_SEL_52AA_M;
cr->dma_c_path_sel = LA_TYPEC_PATH_SEL_52AA;
cr->dma_c_path_sel_m = LA_TYPEC_PATH_SEL_52AA_M;
cr->dma_d_path_sel = LA_TYPED_PATH_SEL_52AA;
cr->dma_d_path_sel_m = LA_TYPED_PATH_SEL_52AA_M;
cr->dma_a_src_sel = LA_TYPEA_SRC_SEL_52AA;
cr->dma_a_src_sel_m = LA_TYPEA_SRC_SEL_52AA_M;
cr->dma_b_src_sel = LA_TYPEB_SRC_SEL_52AA;
cr->dma_b_src_sel_m = LA_TYPEB_SRC_SEL_52AA_M;
cr->dma_c_src_sel = LA_TYPEC_SRC_SEL_52AA;
cr->dma_c_src_sel_m = LA_TYPEC_SRC_SEL_52AA_M;
cr->dma_d_src_sel = LA_TYPED_SRC_SEL_52AA;
cr->dma_d_src_sel_m = LA_TYPED_SRC_SEL_52AA_M;
cr->la_smp_rate = LA_SMP_RT_SEL_52AA;
cr->la_smp_rate_m = LA_SMP_RT_SEL_52AA_M;
cr->rdrdy_3_phase_en = LA_RDRDY_3PHASE_EN_52AA;
cr->rdrdy_3_phase_en_m = LA_RDRDY_3PHASE_EN_52AA_M;
cr->la_trigger_edge = LA_EDGE_SEL_52AA;
cr->la_trigger_edge_m = LA_EDGE_SEL_52AA_M;
cr->dma_hdr_sel_63 = LA_HDR_SEL_63_52AA;
cr->dma_hdr_sel_63_m = LA_HDR_SEL_63_52AA_M;
cr->dma_hdr_sel_62 = LA_HDR_SEL_62_52AA;
cr->dma_hdr_sel_62_m = LA_HDR_SEL_62_52AA_M;
cr->dma_hdr_sel_61 = LA_HDR_SEL_61_52AA;
cr->dma_hdr_sel_61_m = LA_HDR_SEL_61_52AA_M;
cr->dma_hdr_sel_60 = LA_HDR_SEL_60_52AA;
cr->dma_hdr_sel_60_m = LA_HDR_SEL_60_52AA_M;
cr->dma_a_ck160_dly_en = LA_TYPEA_CK160_DLY_EN_52AA;
cr->dma_a_ck160_dly_en_m = LA_TYPEA_CK160_DLY_EN_52AA_M;
cr->dma_b_ck160_dly_en = LA_TYPEB_CK160_DLY_EN_52AA;
cr->dma_b_ck160_dly_en_m = LA_TYPEB_CK160_DLY_EN_52AA_M;
cr->dma_dbgport_phy_sel = LA_DBGPORT_SRC_SEL_52AA;
cr->dma_dbgport_phy_sel_m = LA_DBGPORT_SRC_SEL_52AA_M;
cr->dma_data_type = LA_DATA_52AA;
cr->dma_data_type_m = LA_DATA_52AA_M;
cr->r_dma_rdrdy = LA_RDRDY_52AA;
cr->r_dma_rdrdy_m = LA_RDRDY_52AA_M;
cr->la_and0_bit_sel = LA_TRIG_52AA;
cr->la_and0_bit_sel_m = LA_TRIG_52AA_M;
cr->la_trigger_cnt = LA_TRIG_CNT_52AA;
cr->la_trigger_cnt_m = LA_TRIG_CNT_52AA_M;
cr->and0_trig_disable = LA_TRIG_NEW_ONLY_52AA;
cr->and0_trig_disable_m = LA_TRIG_NEW_ONLY_52AA_M;
cr->la_and1_inv = LA_TRIG_AND1_INV_52AA;
cr->la_and1_inv_m = LA_TRIG_AND1_INV_52AA_M;
cr->la_and2_en = LA_TRIG_AND2_EN_52AA;
cr->la_and2_en_m = LA_TRIG_AND2_EN_52AA_M;
cr->la_and2_inv = LA_TRIG_AND2_INV_52AA;
cr->la_and2_inv_m = LA_TRIG_AND2_INV_52AA_M;
cr->la_and3_en = LA_TRIG_AND3_EN_52AA;
cr->la_and3_en_m = LA_TRIG_AND3_EN_52AA_M;
cr->la_and3_inv = LA_TRIG_AND3_INV_52AA;
cr->la_and3_inv_m = LA_TRIG_AND3_INV_52AA_M;
cr->la_and4_en = LA_TRIG_AND4_EN_52AA;
cr->la_and4_en_m = LA_TRIG_AND4_EN_52AA_M;
cr->la_and4_rate = LA_TRIG_AND4_VAL_52AA;
cr->la_and4_rate_m = LA_TRIG_AND4_VAL_52AA_M;
cr->la_and4_inv = LA_TRIG_AND4_INV_52AA;
cr->la_and4_inv_m = LA_TRIG_AND4_INV_52AA_M;
cr->la_and1_mask = LA_TRIG_AND1_BIT_EN_52AA;
cr->la_and1_mask_m = LA_TRIG_AND1_BIT_EN_52AA_M;
cr->la_and1_val = LA_TRIG_AND1_VAL_52AA;
cr->la_and1_val_m = LA_TRIG_AND1_VAL_52AA_M;
cr->la_and2_mask = LA_TRIG_AND2_MASK_52AA;
cr->la_and2_mask_m = LA_TRIG_AND2_MASK_52AA_M;
cr->la_and2_val = LA_TRIG_AND2_VAL_52AA;
cr->la_and2_val_m = LA_TRIG_AND2_VAL_52AA_M;
cr->la_and3_mask = LA_TRIG_AND3_MASK_52AA;
cr->la_and3_mask_m = LA_TRIG_AND3_MASK_52AA_M;
cr->la_and3_val = LA_TRIG_AND3_VAL_52AA;
cr->la_and3_val_m = LA_TRIG_AND3_VAL_52AA_M;
cr->la_and5_sel = LA_TRIG_AND5_52AA;
cr->la_and5_sel_m = LA_TRIG_AND5_52AA_M;
cr->la_and5_val = LA_TRIG_AND5_VAL_52AA;
cr->la_and5_val_m = LA_TRIG_AND5_VAL_52AA_M;
cr->la_and5_inv = LA_TRIG_AND5_INV_52AA;
cr->la_and5_inv_m = LA_TRIG_AND5_INV_52AA_M;
cr->la_and6_sel = LA_TRIG_AND6_52AA;
cr->la_and6_sel_m = LA_TRIG_AND6_52AA_M;
cr->la_and6_val = LA_TRIG_AND6_VAL_52AA;
cr->la_and6_val_m = LA_TRIG_AND6_VAL_52AA_M;
cr->la_and6_inv = LA_TRIG_AND6_INV_52AA;
cr->la_and6_inv_m = LA_TRIG_AND6_INV_52AA_M;
cr->la_and7_sel = LA_TRIG_AND7_52AA;
cr->la_and7_sel_m = LA_TRIG_AND7_52AA_M;
cr->la_and7_val = LA_TRIG_AND7_VAL_52AA;
cr->la_and7_val_m = LA_TRIG_AND7_VAL_52AA_M;
cr->la_and7_inv = LA_TRIG_AND7_INV_52AA;
cr->la_and7_inv_m = LA_TRIG_AND7_INV_52AA_M;
cr->la_mac_and1_en = LA_M_AND1_EN_52AA;
cr->la_mac_and1_en_m = LA_M_AND1_EN_52AA_M;
cr->la_mac_and2_en = LA_M_AND2_EN_52AA;
cr->la_mac_and2_en_m = LA_M_AND2_EN_52AA_M;
cr->la_mac_and0_sel = LA_M_AND0_SEL_52AA;
cr->la_mac_and0_sel_m = LA_M_AND0_SEL_52AA_M;
cr->la_mac_and0_en = LA_M_AND0_EN_52AA;
cr->la_mac_and0_en_m = LA_M_AND0_EN_52AA_M;
cr->la_and2_sign = LA_SIGN2_52AA;
cr->la_and2_sign_m = LA_SIGN2_52AA_M;
cr->la_and3_sign = LA_SIGN3_52AA;
cr->la_and3_sign_m = LA_SIGN3_52AA_M;
cr->la_re_trig_edge = LA_RE_INIT_POLARITY_52AA;
cr->la_re_trig_edge_m = LA_RE_INIT_POLARITY_52AA_M;
cr->la_re_and1_sel = LA_RE_INIT_AND1_52AA;
cr->la_re_and1_sel_m = LA_RE_INIT_AND1_52AA_M;
cr->la_re_and1_val = LA_RE_INIT_AND1_VAL_52AA;
cr->la_re_and1_val_m = LA_RE_INIT_AND1_VAL_52AA_M;
cr->la_re_and1_inv = LA_RE_INIT_AND1_INV_52AA;
cr->la_re_and1_inv_m = LA_RE_INIT_AND1_INV_52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->la_clk_en = LA_CKEN_A;
cr->la_clk_en_m = LA_CKEN_A_M;
cr->la_en = LA_EN_A;
cr->la_en_m = LA_EN_A_M;
cr->dma_dbgport_base_n = LA_DBGPORT_BASE_N_A;
cr->dma_dbgport_base_n_m = LA_DBGPORT_BASE_N_A_M;
cr->dma_a_path_sel = LA_TYPEA_PATH_SEL_A;
cr->dma_a_path_sel_m = LA_TYPEA_PATH_SEL_A_M;
cr->dma_b_path_sel = LA_TYPEB_PATH_SEL_A;
cr->dma_b_path_sel_m = LA_TYPEB_PATH_SEL_A_M;
cr->dma_c_path_sel = LA_TYPEC_PATH_SEL_A;
cr->dma_c_path_sel_m = LA_TYPEC_PATH_SEL_A_M;
cr->dma_d_path_sel = LA_TYPED_PATH_SEL_A;
cr->dma_d_path_sel_m = LA_TYPED_PATH_SEL_A_M;
cr->dma_a_src_sel = LA_TYPEA_SRC_SEL_A;
cr->dma_a_src_sel_m = LA_TYPEA_SRC_SEL_A_M;
cr->dma_b_src_sel = LA_TYPEB_SRC_SEL_A;
cr->dma_b_src_sel_m = LA_TYPEB_SRC_SEL_A_M;
cr->dma_c_src_sel = LA_TYPEC_SRC_SEL_A;
cr->dma_c_src_sel_m = LA_TYPEC_SRC_SEL_A_M;
cr->dma_d_src_sel = LA_TYPED_SRC_SEL_A;
cr->dma_d_src_sel_m = LA_TYPED_SRC_SEL_A_M;
cr->la_smp_rate = LA_SMP_RT_SEL_A;
cr->la_smp_rate_m = LA_SMP_RT_SEL_A_M;
cr->rdrdy_3_phase_en = LA_RDRDY_3PHASE_EN_A;
cr->rdrdy_3_phase_en_m = LA_RDRDY_3PHASE_EN_A_M;
cr->la_trigger_edge = LA_EDGE_SEL_A;
cr->la_trigger_edge_m = LA_EDGE_SEL_A_M;
cr->dma_hdr_sel_63 = LA_HDR_SEL_63_A;
cr->dma_hdr_sel_63_m = LA_HDR_SEL_63_A_M;
cr->dma_hdr_sel_62 = LA_HDR_SEL_62_A;
cr->dma_hdr_sel_62_m = LA_HDR_SEL_62_A_M;
cr->dma_hdr_sel_61 = LA_HDR_SEL_61_A;
cr->dma_hdr_sel_61_m = LA_HDR_SEL_61_A_M;
cr->dma_hdr_sel_60 = LA_HDR_SEL_60_A;
cr->dma_hdr_sel_60_m = LA_HDR_SEL_60_A_M;
cr->dma_a_ck160_dly_en = LA_TYPEA_CK160_DLY_EN_A;
cr->dma_a_ck160_dly_en_m = LA_TYPEA_CK160_DLY_EN_A_M;
cr->dma_b_ck160_dly_en = LA_TYPEB_CK160_DLY_EN_A;
cr->dma_b_ck160_dly_en_m = LA_TYPEB_CK160_DLY_EN_A_M;
cr->dma_dbgport_phy_sel = LA_DBGPORT_SRC_SEL_A;
cr->dma_dbgport_phy_sel_m = LA_DBGPORT_SRC_SEL_A_M;
cr->dma_data_type = LA_DATA_A;
cr->dma_data_type_m = LA_DATA_A_M;
cr->r_dma_rdrdy = LA_RDRDY_A;
cr->r_dma_rdrdy_m= LA_RDRDY_A_M;
cr->la_and0_bit_sel = LA_TRIG_A;
cr->la_and0_bit_sel_m = LA_TRIG_A_M;
cr->la_trigger_cnt = LA_TRIG_CNT_A;
cr->la_trigger_cnt_m = LA_TRIG_CNT_A_M;
cr->and0_trig_disable = LA_TRIG_NEW_ONLY_A;
cr->and0_trig_disable_m = LA_TRIG_NEW_ONLY_A_M;
cr->la_and1_inv = LA_TRIG_AND1_INV_A;
cr->la_and1_inv_m = LA_TRIG_AND1_INV_A_M;
cr->la_and2_en = LA_TRIG_AND2_EN_A;
cr->la_and2_en_m = LA_TRIG_AND2_EN_A_M;
cr->la_and2_inv = LA_TRIG_AND2_INV_A;
cr->la_and2_inv_m = LA_TRIG_AND2_INV_A_M;
cr->la_and3_en = LA_TRIG_AND3_EN_A;
cr->la_and3_en_m = LA_TRIG_AND3_EN_A_M;
cr->la_and3_inv = LA_TRIG_AND3_INV_A;
cr->la_and3_inv_m = LA_TRIG_AND3_INV_A_M;
cr->la_and4_en = LA_TRIG_AND4_EN_A;
cr->la_and4_en_m = LA_TRIG_AND4_EN_A_M;
cr->la_and4_rate = LA_TRIG_AND4_VAL_A;
cr->la_and4_rate_m = LA_TRIG_AND4_VAL_A_M;
cr->la_and4_inv = LA_TRIG_AND4_INV_A;
cr->la_and4_inv_m = LA_TRIG_AND4_INV_A_M;
cr->la_and1_mask = LA_TRIG_AND1_BIT_EN_A;
cr->la_and1_mask_m = LA_TRIG_AND1_BIT_EN_A_M;
cr->la_and1_val = LA_TRIG_AND1_VAL_A;
cr->la_and1_val_m = LA_TRIG_AND1_VAL_A_M;
cr->la_and2_mask = LA_TRIG_AND2_MASK_A;
cr->la_and2_mask_m = LA_TRIG_AND2_MASK_A_M;
cr->la_and2_val = LA_TRIG_AND2_VAL_A;
cr->la_and2_val_m = LA_TRIG_AND2_VAL_A_M;
cr->la_and3_mask = LA_TRIG_AND3_MASK_A;
cr->la_and3_mask_m = LA_TRIG_AND3_MASK_A_M;
cr->la_and3_val = LA_TRIG_AND3_VAL_A;
cr->la_and3_val_m = LA_TRIG_AND3_VAL_A_M;
cr->la_and5_sel = LA_TRIG_AND5_A;
cr->la_and5_sel_m = LA_TRIG_AND5_A_M;
cr->la_and5_val = LA_TRIG_AND5_VAL_A;
cr->la_and5_val_m = LA_TRIG_AND5_VAL_A_M;
cr->la_and5_inv = LA_TRIG_AND5_INV_A;
cr->la_and5_inv_m = LA_TRIG_AND5_INV_A_M;
cr->la_and6_sel = LA_TRIG_AND6_A;
cr->la_and6_sel_m = LA_TRIG_AND6_A_M;
cr->la_and6_val = LA_TRIG_AND6_VAL_A;
cr->la_and6_val_m = LA_TRIG_AND6_VAL_A_M;
cr->la_and6_inv = LA_TRIG_AND6_INV_A;
cr->la_and6_inv_m = LA_TRIG_AND6_INV_A_M;
cr->la_and7_sel = LA_TRIG_AND7_A;
cr->la_and7_sel_m = LA_TRIG_AND7_A_M;
cr->la_and7_val = LA_TRIG_AND7_VAL_A;
cr->la_and7_val_m = LA_TRIG_AND7_VAL_A_M;
cr->la_and7_inv = LA_TRIG_AND7_INV_A;
cr->la_and7_inv_m = LA_TRIG_AND7_INV_A_M;
cr->la_brk_sel = BRK_R_BRK_SEL_FOR_CNT_A;
cr->la_brk_sel_m =BRK_R_BRK_SEL_FOR_CNT_A_M;
cr->la_mac_and1_en = LA_M_AND1_EN_A;
cr->la_mac_and1_en_m = LA_M_AND1_EN_A_M;
cr->la_mac_and2_en = LA_M_AND2_EN_A;
cr->la_mac_and2_en_m = LA_M_AND2_EN_A_M;
cr->la_mac_and0_sel = LA_M_AND0_SEL_A;
cr->la_mac_and0_sel_m = LA_M_AND0_SEL_A_M;
cr->la_mac_and0_en = LA_M_AND0_EN_A;
cr->la_mac_and0_en_m = LA_M_AND0_EN_A_M;
cr->la_mac_and0_mac_sel = INTF_R_MAC_SEL_A;
cr->la_mac_and0_mac_sel_m = INTF_R_MAC_SEL_A_M;
cr->la_and2_sign = LA_SIGN2_A;
cr->la_and2_sign_m = LA_SIGN2_A_M;
cr->la_and3_sign = LA_SIGN3_A;
cr->la_and3_sign_m = LA_SIGN3_A_M;
cr->la_re_trig_edge = LA_RE_INIT_POLARITY_A;
cr->la_re_trig_edge_m = LA_RE_INIT_POLARITY_A_M;
cr->la_re_and1_sel = LA_RE_INIT_AND1_A;
cr->la_re_and1_sel_m = LA_RE_INIT_AND1_A_M;
cr->la_re_and1_val = LA_RE_INIT_AND1_VAL_A;
cr->la_re_and1_val_m = LA_RE_INIT_AND1_VAL_A_M;
cr->la_re_and1_inv = LA_RE_INIT_AND1_INV_A;
cr->la_re_and1_inv_m = LA_RE_INIT_AND1_INV_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->la_clk_en = LA_CKEN_C;
cr->la_clk_en_m = LA_CKEN_C_M;
cr->la_en = LA_EN_C;
cr->la_en_m = LA_EN_C_M;
cr->dma_dbgport_base_n = LA_DBGPORT_BASE_N_C;
cr->dma_dbgport_base_n_m = LA_DBGPORT_BASE_N_C_M;
cr->dma_a_path_sel = LA_TYPEA_PATH_SEL_C;
cr->dma_a_path_sel_m = LA_TYPEA_PATH_SEL_C_M;
cr->dma_b_path_sel = LA_TYPEB_PATH_SEL_C;
cr->dma_b_path_sel_m = LA_TYPEB_PATH_SEL_C_M;
cr->dma_c_path_sel = LA_TYPEC_PATH_SEL_C;
cr->dma_c_path_sel_m = LA_TYPEC_PATH_SEL_C_M;
cr->dma_d_path_sel = LA_TYPED_PATH_SEL_C;
cr->dma_d_path_sel_m = LA_TYPED_PATH_SEL_C_M;
cr->dma_a_src_sel = LA_TYPEA_SRC_SEL_C;
cr->dma_a_src_sel_m = LA_TYPEA_SRC_SEL_C_M;
cr->dma_b_src_sel = LA_TYPEB_SRC_SEL_C;
cr->dma_b_src_sel_m = LA_TYPEB_SRC_SEL_C_M;
cr->dma_c_src_sel = LA_TYPEC_SRC_SEL_C;
cr->dma_c_src_sel_m = LA_TYPEC_SRC_SEL_C_M;
cr->dma_d_src_sel = LA_TYPED_SRC_SEL_C;
cr->dma_d_src_sel_m = LA_TYPED_SRC_SEL_C_M;
cr->la_smp_rate = LA_SMP_RT_SEL_C;
cr->la_smp_rate_m = LA_SMP_RT_SEL_C_M;
cr->rdrdy_3_phase_en = LA_RDRDY_3PHASE_EN_C;
cr->rdrdy_3_phase_en_m = LA_RDRDY_3PHASE_EN_C_M;
cr->la_trigger_edge = LA_EDGE_SEL_C;
cr->la_trigger_edge_m = LA_EDGE_SEL_C_M;
cr->dma_hdr_sel_63 = LA_HDR_SEL_63_C;
cr->dma_hdr_sel_63_m = LA_HDR_SEL_63_C_M;
cr->dma_hdr_sel_62 = LA_HDR_SEL_62_C;
cr->dma_hdr_sel_62_m = LA_HDR_SEL_62_C_M;
cr->dma_hdr_sel_61 = LA_HDR_SEL_61_C;
cr->dma_hdr_sel_61_m = LA_HDR_SEL_61_C_M;
cr->dma_hdr_sel_60 = LA_HDR_SEL_60_C;
cr->dma_hdr_sel_60_m = LA_HDR_SEL_60_C_M;
cr->dma_a_ck160_dly_en = LA_TYPEA_CK160_DLY_EN_C;
cr->dma_a_ck160_dly_en_m = LA_TYPEA_CK160_DLY_EN_C_M;
cr->dma_b_ck160_dly_en = LA_TYPEB_CK160_DLY_EN_C;
cr->dma_b_ck160_dly_en_m = LA_TYPEB_CK160_DLY_EN_C_M;
cr->dma_dbgport_phy_sel = LA_DBGPORT_SRC_SEL_C;
cr->dma_dbgport_phy_sel_m = LA_DBGPORT_SRC_SEL_C_M;
cr->dma_data_type = LA_DATA_C;
cr->dma_data_type_m = LA_DATA_C_M;
cr->r_dma_rdrdy = LA_RDRDY_C;
cr->r_dma_rdrdy_m= LA_RDRDY_C_M;
cr->la_and0_bit_sel = LA_TRIG_C;
cr->la_and0_bit_sel_m = LA_TRIG_C_M;
cr->la_trigger_cnt = LA_TRIG_CNT_C;
cr->la_trigger_cnt_m = LA_TRIG_CNT_C_M;
cr->and0_trig_disable = LA_TRIG_NEW_ONLY_C;
cr->and0_trig_disable_m = LA_TRIG_NEW_ONLY_C_M;
cr->la_and1_inv = LA_TRIG_AND1_INV_C;
cr->la_and1_inv_m = LA_TRIG_AND1_INV_C_M;
cr->la_and2_en = LA_TRIG_AND2_EN_C;
cr->la_and2_en_m = LA_TRIG_AND2_EN_C_M;
cr->la_and2_inv = LA_TRIG_AND2_INV_C;
cr->la_and2_inv_m = LA_TRIG_AND2_INV_C_M;
cr->la_and3_en = LA_TRIG_AND3_EN_C;
cr->la_and3_en_m = LA_TRIG_AND3_EN_C_M;
cr->la_and3_inv = LA_TRIG_AND3_INV_C;
cr->la_and3_inv_m = LA_TRIG_AND3_INV_C_M;
cr->la_and4_en = LA_TRIG_AND4_EN_C;
cr->la_and4_en_m = LA_TRIG_AND4_EN_C_M;
cr->la_and4_rate = LA_TRIG_AND4_VAL_C;
cr->la_and4_rate_m = LA_TRIG_AND4_VAL_C_M;
cr->la_and4_inv = LA_TRIG_AND4_INV_C;
cr->la_and4_inv_m = LA_TRIG_AND4_INV_C_M;
cr->la_and1_mask = LA_TRIG_AND1_BIT_EN_C;
cr->la_and1_mask_m = LA_TRIG_AND1_BIT_EN_C_M;
cr->la_and1_val = LA_TRIG_AND1_VAL_C;
cr->la_and1_val_m = LA_TRIG_AND1_VAL_C_M;
cr->la_and2_mask = LA_TRIG_AND2_MASK_C;
cr->la_and2_mask_m = LA_TRIG_AND2_MASK_C_M;
cr->la_and2_val = LA_TRIG_AND2_VAL_C;
cr->la_and2_val_m = LA_TRIG_AND2_VAL_C_M;
cr->la_and3_mask = LA_TRIG_AND3_MASK_C;
cr->la_and3_mask_m = LA_TRIG_AND3_MASK_C_M;
cr->la_and3_val = LA_TRIG_AND3_VAL_C;
cr->la_and3_val_m = LA_TRIG_AND3_VAL_C_M;
cr->la_and5_sel = LA_TRIG_AND5_C;
cr->la_and5_sel_m = LA_TRIG_AND5_C_M;
cr->la_and5_val = LA_TRIG_AND5_VAL_C;
cr->la_and5_val_m = LA_TRIG_AND5_VAL_C_M;
cr->la_and5_inv = LA_TRIG_AND5_INV_C;
cr->la_and5_inv_m = LA_TRIG_AND5_INV_C_M;
cr->la_and6_sel = LA_TRIG_AND6_C;
cr->la_and6_sel_m = LA_TRIG_AND6_C_M;
cr->la_and6_val = LA_TRIG_AND6_VAL_C;
cr->la_and6_val_m = LA_TRIG_AND6_VAL_C_M;
cr->la_and6_inv = LA_TRIG_AND6_INV_C;
cr->la_and6_inv_m = LA_TRIG_AND6_INV_C_M;
cr->la_and7_sel = LA_TRIG_AND7_C;
cr->la_and7_sel_m = LA_TRIG_AND7_C_M;
cr->la_and7_val = LA_TRIG_AND7_VAL_C;
cr->la_and7_val_m = LA_TRIG_AND7_VAL_C_M;
cr->la_and7_inv = LA_TRIG_AND7_INV_C;
cr->la_and7_inv_m = LA_TRIG_AND7_INV_C_M;
cr->la_brk_sel = BRK_R_BRK_SEL_FOR_CNT_C;
cr->la_brk_sel_m =BRK_R_BRK_SEL_FOR_CNT_C_M;
cr->la_mac_and1_en = LA_M_AND1_EN_C;
cr->la_mac_and1_en_m = LA_M_AND1_EN_C_M;
cr->la_mac_and2_en = LA_M_AND2_EN_C;
cr->la_mac_and2_en_m = LA_M_AND2_EN_C_M;
cr->la_mac_and0_sel = LA_M_AND0_SEL_C;
cr->la_mac_and0_sel_m = LA_M_AND0_SEL_C_M;
cr->la_mac_and0_en = LA_M_AND0_EN_C;
cr->la_mac_and0_en_m = LA_M_AND0_EN_C_M;
cr->la_mac_and0_mac_sel = INTF_R_MAC_SEL_C;
cr->la_mac_and0_mac_sel_m = INTF_R_MAC_SEL_C_M;
cr->la_and2_sign = LA_SIGN2_C;
cr->la_and2_sign_m = LA_SIGN2_C_M;
cr->la_and3_sign = LA_SIGN3_C;
cr->la_and3_sign_m = LA_SIGN3_C_M;
cr->la_re_trig_edge = LA_RE_INIT_POLARITY_C;
cr->la_re_trig_edge_m = LA_RE_INIT_POLARITY_C_M;
cr->la_re_and1_sel = LA_RE_INIT_AND1_C;
cr->la_re_and1_sel_m = LA_RE_INIT_AND1_C_M;
cr->la_re_and1_val = LA_RE_INIT_AND1_VAL_C;
cr->la_re_and1_val_m = LA_RE_INIT_AND1_VAL_C_M;
cr->la_re_and1_inv = LA_RE_INIT_AND1_INV_C;
cr->la_re_and1_inv_m = LA_RE_INIT_AND1_INV_C_M;
break;
#endif
default:
break;
}
}
#endif
#if LAMODE_ECHO_CMD
void
halbb_la_buffer_print(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
struct la_string_info *buf = &la->la_string_i;
struct la_print_info *print = &la->la_print_i;
u64 la_pattern_msb, la_pattern_lsb;
u64 la_pattern, la_pattern_part;
s64 tmp_s64;
u64 mask = 0xffffffff;
u8 mask_length = 0;
u32 i;
u32 idx;
u32 var[10] = {0};
if (!buf->octet || buf->length == 0 || buf->length < la->smp_number)
return;
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[2]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &var[3]);
BB_TRACE("echo lamode 1 %d %d %d 0 %x %d %d %d\n\n",
la->la_and0_bit_sel, dma->dma_data_type,
la->la_mac_cfg_i.la_trigger_time,
la->la_dbg_port, la->la_trigger_edge, la->la_smp_rate,
la->la_count);
BB_TRACE("[LA Data Dump] smp_number = %d\n", la->smp_number);
BB_TRACE("Dump_Start\n");
print->print_len = (u8)var[0];
if (var[0] == 0) {
for (i = 0; i < la->smp_number; i++) {
idx = i << 1;
BB_TRACE("%08x%08x\n", buf->octet[idx + 1],
buf->octet[idx]);
}
} else if (var[0] == 1) {
print->print_mode = (u8)var[1];
print->print_lsb = (u8)var[2];
print->print_msb = (u8)var[3];
/*------------------------*/
if (var[1] == 0)
BB_TRACE("[Hex]\n");
else if (var[1] == 1)
BB_TRACE("[Dec unsigned]\n");
else if (var[1] == 2)
BB_TRACE("[Dec signed]\n");
BB_TRACE("BIT[%d:%d]\n", var[3], var[2]);
if (var[2] > var[3]) {
BB_TRACE("[Warning] BIT_L > BIT_H\n");
return;
}
mask_length = (u8)(var[3] - var[2] + 1);
mask = halbb_gen_mask_from_0(mask_length) << var[2];
/*------------------------*/
for (i = 0; i < la->smp_number; i++) {
idx = i << 1;
la_pattern_msb = (u64)buf->octet[idx + 1];
la_pattern_lsb = (u64)buf->octet[idx];
la_pattern = (la_pattern_msb << 32) | la_pattern_lsb;
la_pattern_part = (la_pattern & mask) >> var[2];
if (var[1] == 0) {
BB_TRACE("0x%llx\n", la_pattern_part);
} else if (var[1] == 1) {
BB_TRACE("%llu\n", la_pattern_part);
} else if (var[1] == 2) {
tmp_s64 = halbb_cnvrt_2_sign_64(la_pattern_part,
mask_length);
BB_TRACE("%lld\n", tmp_s64);
}
}
}
BB_TRACE("Dump_End\n\n");
}
void halbb_la_cmd_bb_show_cfg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_adv_trig_info *adv = &la->adv_trig_i;
struct la_dma_info *dma = &la->la_dma_i;
struct la_re_trig_info *re = &la->la_re_trig_i;
struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i;
struct la_print_info *print = &la->la_print_i;
struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cmn {TrigTime:%d} {TrigCnt:%d} {DbgPort:%x} {Edge:P/N:%d} {f_smp:%d}\n",
cfg->la_trigger_time, la->la_trigger_cnt,
la->la_dbg_port, la->la_trigger_edge, la->la_smp_rate);
#if 1
/*BB DMA*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dma {0:dbgPort_base_N} {N:%d}\n",
dma->dma_dbgport_base_n);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dma {1:path_sel} {A:%d} {B:%d} {C:%d} {D:%d}\n",
dma->dma_a_path_sel, dma->dma_b_path_sel,
dma->dma_c_path_sel, dma->dma_d_path_sel);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dma {2:src_sel} {A:%d} {B:%d} {C:%d} {D:%d}\n",
dma->dma_a_src_sel, dma->dma_b_src_sel,
dma->dma_c_src_sel, dma->dma_d_src_sel);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dma {3:hdr_sel} {B63:%d} {B62:%d} {B61:%d} {B60:%d}\n",
dma->dma_hdr_sel_63, dma->dma_hdr_sel_62,
dma->dma_hdr_sel_61, dma->dma_hdr_sel_60);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dma {4:phy_sel} {phy:%d}\n", dma->dma_dbgport_phy_sel);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dma {5:dma_sel} {type:%d}\n", dma->dma_data_type);
/*BB -Trig*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {0:And0} {disable:%d} {bit_num:%d}\n",
la->la_and0_disable, la->la_and0_bit_sel);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {1:And1} {en_bitmap:%d} {inv:%d} {bitmap:%d}\n",
adv->la_and1_mask, adv->la_and1_inv, adv->la_and1_val);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {2:And2} {en:%d} {inv:%d} {val:%d} {mask(0x%x)} {sign:%d}\n",
adv->la_and2_en, adv->la_and2_inv, adv->la_and2_val,
adv->la_and2_mask, adv->la_and2_sign);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {3:And3} {en:%d} {inv:%d} {val:%d} {mask(0x%x)} {sign:%d}\n",
adv->la_and3_en, adv->la_and3_inv, adv->la_and3_val,
adv->la_and3_mask, adv->la_and3_sign);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {4:And4} {en:%d} {inv:%d} {rate_idx:%d}\n",
adv->la_and4_en, adv->la_and4_inv, adv->la_and4_rate);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {5:And5} {en/sel:%d} {inv:%d} {val:%d}\n",
adv->la_and5_sel, adv->la_and5_inv, adv->la_and5_val);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {6:And6} {en/sel:%d} {inv:%d} {val:%d}\n",
adv->la_and6_sel, adv->la_and6_inv, adv->la_and6_val);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bb {7:And7} {en/sel:%d} {inv:%d} {val:%d}\n",
adv->la_and7_sel, adv->la_and7_inv, adv->la_and7_val);
/*MAC Adv-Trig*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"mac {0:And0} {en:%d} {0:cca,1:er,2:ok:%d} {0:tmac,1:pmac:%d}\n",
trig_mac->la_mac_and0_en, trig_mac->la_mac_and0_sel,
trig_mac->la_mac_and0_mac_sel);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"mac {1:And1} {en:%d}\n", trig_mac->la_mac_and1_en);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"mac {2:And2} {en:%d} {frame_type(%x)}\n",
trig_mac->la_mac_and2_en, trig_mac->la_mac_and2_frame_sel);
/*BB Re-Trig*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"re {mac_en:%d} {en/sel:%d} {inv:%d} {val:%d} {edge:%d}\n",
cfg->mac_la_restart_en, re->la_re_and0_sel,
re->la_re_and0_inv, re->la_re_and0_val,
re->la_re_trig_edge);
/*Buffer*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"buf {0:64K, 1:128K, 2:192K, 3:256K, 4:320K:%d}\n",
cfg->mac_la_buf_sel);
/*control*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"poll {la_polling_cnt:%d} (polling time = %d * 100ms)\n",
la->la_polling_cnt, la->la_polling_cnt);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tmac {timeout_en:%d} {timeout_val:%d} (timeout= 1s << %d )\n",
cfg->mac_la_timeout_en, cfg->mac_la_timeout_val,
cfg->mac_la_timeout_val);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"get {finish_ofst} {is_round_up} (get buffer data for timeout)\n");
/*Print*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"print {0:all(Hex):%d}\n", print->print_len);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"print {1:partial:%d} {0:hex,1:dec,2:s-dec:%d} {bit_L:%d} {bit_H:%d}\n",
print->print_len, print->print_mode, print->print_lsb,
print->print_msb);
/*Setting*/
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set {1:Fake Trig} {en:%d}\n", la->not_stop_trig);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set {2:Auto Print} {en:%d}\n",
print->is_la_print);
#endif
}
void halbb_la_cmd_bb_cmn(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
u32 val[10] = {0};
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_HEX, &val[2]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]);
HALBB_SCAN(input[6], DCMD_DECIMAL, &val[4]);
la->la_mac_cfg_i.la_trigger_time = val[0];
la->la_trigger_cnt = (u8)val[1];
la->la_dbg_port = val[2];
la->la_trigger_edge = (u8)val[3];
la->la_smp_rate = (enum la_bb_smp_clk)val[4];
}
void halbb_la_cmd_bb_dma(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
u32 val[10] = {0};
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]);
HALBB_SCAN(input[6], DCMD_DECIMAL, &val[4]);
if (val[0] == 0) {
dma->dma_dbgport_base_n = (u8)val[1];
} else if (val[0] == 1) {
dma->dma_a_path_sel = (u8)val[1];
dma->dma_b_path_sel = (u8)val[2];
dma->dma_c_path_sel = (u8)val[3];
dma->dma_d_path_sel = (u8)val[4];
} else if (val[0] == 2) {
dma->dma_a_src_sel = (u8)val[1];
dma->dma_b_src_sel = (u8)val[2];
dma->dma_c_src_sel = (u8)val[3];
dma->dma_d_src_sel = (u8)val[4];
} else if (val[0] == 3) {
dma->dma_hdr_sel_63 = (u8)val[1];
dma->dma_hdr_sel_62 = (u8)val[2];
dma->dma_hdr_sel_61 = (u8)val[3];
dma->dma_hdr_sel_60 = (u8)val[4];
} else if (val[0] == 4) {
dma->dma_dbgport_phy_sel = (bool)val[1];
} else if (val[0] == 5) {
dma->dma_data_type = (enum la_dma_data_type_t)val[1];
}
}
void halbb_la_cmd_bb_trig(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_adv_trig_info *adv = &la->adv_trig_i;
u32 val[10] = {0};
HALBB_SCAN(input[2], DCMD_HEX, &val[0]);
HALBB_SCAN(input[3], DCMD_HEX, &val[1]);
HALBB_SCAN(input[4], DCMD_HEX, &val[2]);
HALBB_SCAN(input[5], DCMD_HEX, &val[3]);
HALBB_SCAN(input[6], DCMD_HEX, &val[4]);
HALBB_SCAN(input[7], DCMD_HEX, &val[5]);
HALBB_SCAN(input[8], DCMD_HEX, &val[6]);
if (val[0] == 0) {
la->la_and0_disable = (bool)val[1];
la->la_and0_bit_sel = val[2];
} else if (val[0] == 1) {
adv->la_and1_mask = val[1];
adv->la_and1_inv = (bool)val[2];
adv->la_and1_val = val[3];
} else if (val[0] == 2) {
adv->la_and2_en = (bool)val[1];
adv->la_and2_inv = (bool)val[2];
adv->la_and2_val = val[3];
adv->la_and2_mask = val[4];
adv->la_and2_sign = (u8)val[5];
} else if (val[0] == 3) {
adv->la_and3_en = (bool)val[1];
adv->la_and3_inv = (bool)val[2];
adv->la_and3_val = val[3];
adv->la_and3_mask = val[4];
adv->la_and3_sign = (u8)val[5];
} else if (val[0] == 4) {
adv->la_and4_en = (bool)val[1];
adv->la_and4_inv = (bool)val[2];
adv->la_and4_rate = (u16)val[3];
} else if (val[0] == 5) {
adv->la_and5_sel = (u8)val[1];
adv->la_and5_inv = (bool)val[2];
adv->la_and5_val = (u8)val[3];
} else if (val[0] == 6) {
adv->la_and6_sel = (u8)val[1];
adv->la_and6_inv = (bool)val[2];
adv->la_and6_val = (u8)val[3];
} else if (val[0] == 7) {
adv->la_and7_sel = (u8)val[1];
adv->la_and7_inv = (bool)val[2];
adv->la_and7_val = (u8)val[3];
}
if (adv->la_and1_mask == 0 &&
!adv->la_and2_en && !adv->la_and3_en && !adv->la_and4_en &&
adv->la_and5_sel == 0 &&
adv->la_and6_sel == 0 &&
adv->la_and7_sel == 0) {
adv->adv_trig_en = false;
} else {
adv->adv_trig_en = true;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Adv_trig_en=%d]\n\n", adv->adv_trig_en);
}
void halbb_la_cmd_bb_re_trig(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_re_trig_info *re = &la->la_re_trig_i;
u32 val[10] = {0};
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[3]);
la->la_mac_cfg_i.mac_la_restart_en = (u8)val[0];
re->re_trig_en = (bool)val[0];
re->la_re_and0_sel = (u8)val[1];
re->la_re_and0_inv = (bool)val[2];
re->la_re_and0_val = (u8)val[3];
re->la_re_trig_edge = (bool)val[4];
}
void halbb_la_cmd_mac_trig(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i;
u32 val[10] = {0};
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_HEX, &val[2]);
HALBB_SCAN(input[5], DCMD_HEX, &val[3]);
if (val[0] == 0) {
trig_mac->la_mac_and0_en = (bool)val[1];
trig_mac->la_mac_and0_sel = (u8)val[2];
trig_mac->la_mac_and0_mac_sel = (u8)val[3];
} else if (val[0] == 1) {
trig_mac->la_mac_and1_en = (bool)val[1];
} else if (val[0] == 2) {
trig_mac->la_mac_and2_en = (bool)val[1];
trig_mac->la_mac_and2_frame_sel = (u8)val[2];
}
if (!trig_mac->la_mac_and0_en &&
!trig_mac->la_mac_and1_en &&
!trig_mac->la_mac_and2_en)
trig_mac->la_mac_trig_en = false;
else
trig_mac->la_mac_trig_en = true;
}
void halbb_la_cmd_fast(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_adv_trig_info *adv = &la->adv_trig_i;
struct la_re_trig_info *re_trig = &la->la_re_trig_i;
u32 trig_time_cca = 0;
s32 val_sign32_tmp = 0;
u32 var[10] = {0};
enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw;
if (bw > 2) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Not Support for BW > %dM\n", 20 << bw);
return;
}
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
trig_time_cca = ((la->la_string_i.smp_number_max >> (bw + 1)) / 10)
- (2 << (2 - bw)) - (2 - bw);
if (var[0] < 10) {
/*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
/*--- Basic Trigger Setting --------------------------------*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca;
la->la_trigger_edge = 0;
la->la_smp_rate = 2 - bw;
la->la_count = 0;
la->la_trigger_cnt = 0;
if (var[0] == 0) { /*CCA*/
if (bb->ic_type == BB_RTL8852AA) {
la->la_and0_disable = true;
la->la_dbg_port = 0x10205;
halbb_la_bb_set_dma_type_reset(bb);
halbb_la_bb_set_adv_reset(bb);
halbb_la_mac_set_adv_reset(bb);
halbb_la_bb_set_re_trig_reset(bb);
adv->adv_trig_en = false;
BB_TRACE("[Fast trigger 0: CCA]\n");
} else if (bb->ic_type == BB_RTL8852A) {
la->la_and0_disable = true;
la->la_dbg_port = 0x10205;
halbb_la_bb_set_dma_type_reset(bb);
halbb_la_bb_set_adv_reset(bb);
halbb_la_mac_set_adv_reset(bb);
halbb_la_bb_set_re_trig_reset(bb);
adv->adv_trig_en = false;
adv->la_and5_sel = 2;
adv->la_and5_inv = false;
adv->la_and5_val = 0;
BB_TRACE("[Fast trigger 0: OFDM CCA]\n");
}
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Not Support\n");
return;
}
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Not Support\n");
return;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Basic-Trigger]\n");
#if 0
struct bb_la_mode_info *la = &bb->bb_la_mode_i;
struct la_adv_trig_info *adv = &la->adv_trig_i;
enum bb_mode_type bb_mode;
const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc};
u32 codeword;
u8 rate_idx;
u32 trig_time_cca = 0;
s32 val_sign32_tmp = 0;
u32 var[10] = {0};
enum channel_width bw = bb->hal_com->band[0].cur_chandef.bw;
if (bw > 2) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Not Support for BW > %dM\n", 20 << bw);
return;
}
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var[2]);
trig_time_cca = ((la->la_string_i.smp_number_max >> (bw + 1)) / 10)
- (2 << (2 - bw)) - (2 - bw);
if (var[0] < 10) {
/*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
/*--- Basic Trigger Setting --------------------------------*/
la->la_and0_bit_sel = 2;
la->la_mac_cfg_i.la_trigger_time = trig_time_cca;
la->la_trigger_edge = 0;
la->la_smp_rate = 2 - bw;
la->la_count = 0;
if (var[0] == 0) { /*AGC*/
dma->dma_data_type = 5;
la->la_dbg_port = 0x870;
} else if (var[0] == 1) { /*EVM*/
dma->dma_data_type = 4;
la->la_dbg_port = 0x392;
} else if (var[0] == 2) { /*SNR*/
dma->dma_data_type = 4;
if (var[1] == 0)
la->la_dbg_port = 0x89e;
else
la->la_dbg_port = 0xa9e;
} else if (var[0] == 3) { /*CFO*/
dma->dma_data_type = 4;
if (var[1] == 0)
la->la_dbg_port = 0x88c;
else
la->la_dbg_port = 0xa8c;
} else if (var[0] == 4) { /*ADC*/
if (var[1] == 0) {
dma->dma_data_type = 0;
la->la_dbg_port = 0x880;
} else {
dma->dma_data_type = 1;
la->la_dbg_port = 0xa80;
}
}
/*--- Adv-Trigger Setting------------------------------------*/
adv->adv_trig_en = false;
} else if (var[0] < 20) {
/*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/
/*--- Basic Trigger Setting ---------------------------------*/
la->la_and0_bit_sel = 0;
la->la_trigger_edge = 0;
la->la_smp_rate = 2 - bw;
la->la_count = 0;
dma->dma_data_type = 4;
la->la_dbg_port = 0x392;
/*--- Adv-Trigger Setting -----------------------------------*/
halbb_la_bb_set_adv_reset(bb);
adv->adv_trig_en = true;
/*And[0]*/
la->la_and0_disable = true;
/*And[1]*/
adv->la_and1_inv = 0;
adv->la_and1_sel = 4; /*RX-state*/
if (var[2] == 0) {
/*L-preamble 8+8+4 = 20*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca - 20;
/*Legacy Data*/
adv->la_and1_val = 5;
} else if (var[2] == 1) {
/*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca - 32 -
(bb->num_rf_path * 4);
/*HT Data*/
adv->la_and1_val = 18;
} else {
/*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca - 36 -
(bb->num_rf_path * 4);
/*VHT Data*/
adv->la_and1_val = 18;
}
/*And[2]*/
adv->la_and2_inv = 0;
adv->la_and2_sel = 0; /*Disable*/
/*And[3]*/
adv->la_and2_inv = 0;
adv->la_and3_sel = 0; /*Disable*/
/*And[4]*/
adv->la_and4_inv = 0;
if (var[0] == 11) {
/*[>= -X dB]*/
if (var[1] == 2) {
adv->la_and4_bitmap = 0;
adv->la_and4_mask = 0x1;
} else if (var[1] == 4) {
adv->la_and4_bitmap = 0;
adv->la_and4_mask = 0x3;
} else if (var[1] == 8) {
adv->la_and4_bitmap = 0;
adv->la_and4_mask = 0x7;
} else if (var[1] == 16) {
adv->la_and4_bitmap = 0;
adv->la_and4_mask = 0xf;
} else if (var[1] == 32) {
adv->la_and4_bitmap = 0;
adv->la_and4_mask = 0x1f;
} else if (var[1] == 64) {
adv->la_and4_bitmap = 0;
adv->la_and4_mask = 0x3f;
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"Not Support >= -%d dB\n", var[1]);
return;
}
} else if (var[0] == 10) {
/*[<= -X dB]*/
if (var[1] == 2) {
adv->la_and4_bitmap = 0x7e;
adv->la_and4_mask = 0x7e;
} else if (var[1] == 4) {
adv->la_and4_bitmap = 0x7c;
adv->la_and4_mask = 0x7c;
} else if (var[1] == 8) {
adv->la_and4_bitmap = 0x78;
adv->la_and4_mask = 0x78;
} else if (var[1] == 16) {
adv->la_and4_bitmap = 0x70;
adv->la_and4_mask = 0x70;
} else if (var[1] == 32) {
adv->la_and4_bitmap = 0x60;
adv->la_and4_mask = 0x60;
} else if (var[1] == 64) {
adv->la_and4_bitmap = 0x40;
adv->la_and4_mask = 0x40;
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"Not Support <= -%d dB\n", var[1]);
return;
}
} else if (var[0] == 12) {
/*[= -X dB]*/
val_sign32_tmp = 0 - (s32)var[1];
adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f);
adv->la_and4_mask = 0x7f;
}
} else if (var[0] < 30) {
/*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/
/*--- Basic Trigger Setting ---------------------------------*/
la->la_and0_bit_sel = 0;
la->la_trigger_edge = 0;
la->la_smp_rate = 2 - bw;
la->la_count = 0;
dma->dma_data_type = 4;
rate_idx = (u8)var[1];
/*--- Adv-Trigger Setting -----------------------------------*/
halbb_la_bb_set_adv_reset(bb);
adv->adv_trig_en = true;
/*And[0]*/
la->la_and0_disable = true;
/*And[1]*/
adv->la_and1_inv = 0;
adv->la_and1_sel = 4; /*RX-state*/
if (rate_idx <= BB_54M && rate_idx >= BB_06M) {
bb_mode = BB_LEGACY_MODE;
codeword = (u32)ofdm_codeword[rate_idx - BB_06M];
la->la_dbg_port = 0x3a9;
/*L-preamble 8+8 = 16*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca - 20;
/*Legacy Data*/
adv->la_and1_val = 5;
} else if (rate_idx <= BB_HT_MCS(31)) {
bb_mode = BB_HT_MODE;
codeword = (u32)(rate_idx - BB_HT_MCS(0));
la->la_dbg_port = 0x3aa;
/*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca - 32 -
(bb->num_rf_path * 4);
/*HT,VHT Data*/
adv->la_and1_val = 18;
} else if (rate_idx <= BB_VHT_4SS_MCS(9)) {
bb_mode = BB_VHT_MODE;
codeword = (u32)halbb_rate_order_compute(bb, rate_idx);
codeword--;
la->la_dbg_port = 0x3ab;
/*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/
la->la_mac_cfg_i.la_trigger_time = trig_time_cca - 36 -
(bb->num_rf_path * 4);
/*HT,VHT Data*/
adv->la_and1_val = 18;
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"Not Support\n");
return;
}
/*And[2]*/
adv->la_and2_inv = 0;
adv->la_and2_sel = 0; /*Disable*/
/*And[3]*/
adv->la_and2_inv = 0;
adv->la_and3_sel = 0; /*Disable*/
/*And[4]*/
adv->la_and4_inv = 0;
if (var[0] == 20) {
if (bb_mode == BB_LEGACY_MODE) {
adv->la_and4_bitmap = codeword;
adv->la_and4_mask = 0x3000000f;
} else if (bb_mode == BB_HT_MODE) {
adv->la_and4_bitmap = (2 << 28) | codeword;
adv->la_and4_mask = 0x3000003f;
} else { /* BB_VHT_MODE*/
adv->la_and4_bitmap = (1 << 28) |
(codeword << 4);
adv->la_and4_mask = 0x300000f0;
}
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"Not Support\n");
return;
}
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Not Support\n");
return;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Basic-Trigger]\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
" *echo lamode 1 %d %d %d 0 %x %d %d %d\n\n",
la->la_and0_bit_sel, dma->dma_data_type,
la->la_mac_cfg_i.la_trigger_time,
la->la_dbg_port, la->la_trigger_edge, la->la_smp_rate,
la->la_count);
BB_TRACE("echo lamode 1 %d %d %d 0 %x %d %d %d\n\n",
la->la_and0_bit_sel, dma->dma_data_type,
la->la_mac_cfg_i.la_trigger_time,
la->la_dbg_port, la->la_trigger_edge, la->la_smp_rate,
la->la_count);
if (adv->adv_trig_en) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Adv-Trigger]\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
" *And0 Disable=%d\n", la->la_and0_disable);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
" *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
" *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
adv->la_and4_mask, adv->la_and4_bitmap,
adv->la_and4_inv);
}
#endif
halbb_la_run(bb);
}
void halbb_la_cmd_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output,
u32 *_out_len)
{
struct bb_la_mode_info *la = &bb->bb_cmn_hooker->bb_la_mode_i;
struct la_dma_info *dma = &la->la_dma_i;
struct la_trig_mac_info *trig_mac = &la->la_trig_mac_i;
struct la_mac_cfg_info *cfg = &la->la_mac_cfg_i;
struct la_string_info *buf = &la->la_string_i;
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]);
/*@dbg_print("echo cmd input_num = %d\n", input_num);*/
if ((_os_strcmp(input[1], "-h") == 0)) {
/*BB Basic Trigger*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"BB_trig: 1 0 {DbgPort Bit} {DMA#} {TrigTime} {TrigCnt}\n\t {DbgPort} {Edge:P/N} {f_smp} {Cap_num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"MAC_trig: 1 1 {0:cca,1:ok_pmac,2:er_pmac,3:ok,4:er} {DMA#} {TrigTime} {trig_cnt}\n\t {DbgPort} {Edge:0(P),1(N)} {f_smp} {Cpture num}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"buf {0~4: 64K/128K/192K/256K/320K}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"disable\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"show\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"reset\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"trig\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ptrn_chk {show(END), rst(END), {ptrn_idx:0~3} {smp_point} {msb32_mask(hex)} {val(hex)}\n");
#if 0
/*Fast Trigger*/
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {0: CCA trig & AGC Dbg Port}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {1: CCA trig & EVM Dbg Port}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {2: CCA trig & SNR Dbg Port}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {3: CCA trig & CFO Dbg Port}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {4: CCA trig & ADC output Dbg Port}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"fast {20: RX-rate-idx=X} {X}\n");
#endif
goto LA_END;
}
if (_os_strcmp(input[1], "ptrn_chk") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[2], "show") == 0) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[LA CHK Pattern] ===>\n");
} else if (_os_strcmp(input[2], "rst") == 0) {
halbb_mem_set(bb, la->la_ptrn_chk_i, 0, sizeof(struct la_ptrn_chk_info) * LA_CHK_PTRN_NUM);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"ptrn_chk reset(Disable)\n");
} else if (val[0] < LA_CHK_PTRN_NUM) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_HEX, &val[2]);
HALBB_SCAN(input[5], DCMD_HEX, &val[3]);
if (val[1] < la->la_string_i.smp_number_max) {
la->la_ptrn_chk_i[val[0]].smp_point = val[1];
la->la_ptrn_chk_i[val[0]].la_ptrn_chk_mask = val[2];
la->la_ptrn_chk_i[val[0]].la_ptrn_chk_val = val[3];
} else {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[Err] smp_number_max=%d\n", la->la_string_i.smp_number_max);
goto LA_END;
}
} else {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Err, idx=%d\n", val[0]);
goto LA_END;
}
for (i = 0; i < LA_CHK_PTRN_NUM; i++) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[%d] point=%05d, chk_mask=0x%08x, chk_val=0x%x\n",
i, la->la_ptrn_chk_i[i].smp_point,
la->la_ptrn_chk_i[i].la_ptrn_chk_mask,
la->la_ptrn_chk_i[i].la_ptrn_chk_val);
}
} else if ((_os_strcmp(input[1], "fast") == 0)) {
halbb_la_cmd_fast(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "show") == 0)) {
halbb_la_cmd_bb_show_cfg(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "reset") == 0)) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Reset\n");
halbb_la_reset(bb);
} else if ((_os_strcmp(input[1], "trig") == 0)) {
halbb_la_run(bb);
} else if ((_os_strcmp(input[1], "cmn") == 0)) {
halbb_la_cmd_bb_cmn(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "dma") == 0)) {
halbb_la_cmd_bb_dma(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "bb") == 0)) {
halbb_la_cmd_bb_trig(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "mac") == 0)) {
halbb_la_cmd_mac_trig(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "tmac") == 0)) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]);
cfg->mac_la_timeout_en = (u8)val[1];
cfg->mac_la_timeout_val = (u8)val[2];
} else if ((_os_strcmp(input[1], "poll") == 0)) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
la->la_polling_cnt = (u8)val[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"la_polling_cnt = %d, polling time = %d * 100ms\n",
la->la_polling_cnt, la->la_polling_cnt);
} else if ((_os_strcmp(input[1], "get") == 0)) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]);
la->la_mode_state = LA_STATE_GET_DLE_BUF;
halbb_mem_set(bb, buf->octet, 0, buf->length);
halbb_la_rpt_buf_get(bb, (u16)val[1], (bool)val[2]);
halbb_la_stop(bb);
} else if ((_os_strcmp(input[1], "re") == 0)) {
halbb_la_cmd_bb_re_trig(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "buf") == 0)) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
la->la_mac_cfg_i.mac_la_buf_sel = (enum la_buff_mode_t)val[1];
la->la_mac_cfg_i.mac_alloc_success = halbb_la_mac_cfg_buf(bb, la->la_mac_cfg_i.mac_la_buf_sel);
if (!la->la_mac_cfg_i.mac_alloc_success)
halbb_la_stop(bb);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"MAC_BUF_alloc_success=%d, Buff_mode=(%d)K\n",
la->la_mac_cfg_i.mac_alloc_success,
64 * (la->la_mac_cfg_i.mac_la_buf_sel + 1));
} else if ((_os_strcmp(input[1], "set") == 0)) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
if (val[1] == 1) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]);
la->not_stop_trig = (bool)val[2];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"not_stop_trig=(%d)\n", la->not_stop_trig);
} else if (val[1] == 2) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]);
la->la_print_i.is_la_print = (bool)val[2];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Auto print=(%d)\n", la->la_print_i.is_la_print);
}
} else if ((_os_strcmp(input[1], "print") == 0)) {
halbb_la_buffer_print(bb, input, &used, output, &out_len);
} else if ((_os_strcmp(input[1], "disable") == 0)) {
halbb_la_stop(bb);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Disable LA mode\n");
} else if (val[0] == 1) {
if (!la->la_mac_cfg_i.mac_alloc_success) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Need to set MAC CR(buf) first: echo bb lamode buf {val}\n");
}
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[3]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[4]);
HALBB_SCAN(input[6], DCMD_HEX, &val[5]);
HALBB_SCAN(input[7], DCMD_HEX, &val[6]);
HALBB_SCAN(input[8], DCMD_DECIMAL, &val[7]);
HALBB_SCAN(input[9], DCMD_DECIMAL, &val[8]);
HALBB_SCAN(input[10], DCMD_DECIMAL, &val[9]);
halbb_la_bb_set_adv_reset(bb);
halbb_la_mac_set_adv_reset(bb);
halbb_la_bb_set_re_trig_reset(bb);
la->la_basic_mode_sel = (u8)val[1];
la->la_and0_bit_sel = val[2];
la->la_mac_cfg_i.la_trigger_time = val[4]; /*unit: us*/
la->la_trigger_cnt= (u8)val[5];
la->la_dbg_port = val[6];
la->la_trigger_edge = (u8)val[7];
la->la_smp_rate = (enum la_bb_smp_clk)(val[8]);
la->la_count = val[9];
if (la->la_basic_mode_sel == 0) {
dma->dma_data_type = (u8)val[3];
la->la_and0_disable = false;
la->adv_trig_i.adv_trig_en = false;
la->la_re_trig_i.re_trig_en = false;
trig_mac->la_mac_trig_en = false;
} else {
la->la_and0_disable = true;
la->adv_trig_i.adv_trig_en = false;
la->la_re_trig_i.re_trig_en = false;
trig_mac->la_mac_trig_en = true;
trig_mac->la_mac_and0_en = true;
trig_mac->la_mac_and0_sel = (u8)val[3];
}
BB_TRACE("echo bb lamode %d %d %d %d %d %d %x %d %d %d\n\n",
val[0], val[1], val[2], val[3], val[4],
val[5], val[6], val[7], val[8], val[9]);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"a.En= ((1)), b.Mode = ((%d)), c.Trig_sel = ((0x%x)), d.Dma_type = ((%d))\n",
la->la_and0_bit_sel, la->la_basic_mode_sel,
dma->dma_data_type);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"e.Trig_time = ((%dus)), f.Trig_cnt = ((%d)), g.Dbg_port = ((0x%x))\n",
la->la_mac_cfg_i.la_trigger_time, la->la_trigger_cnt,
la->la_dbg_port);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"h.Trig_edge = ((%d)), i.La rate = ((%d MHz)), j.Cap_num = ((%d))\n\n",
la->la_trigger_edge, (80 >> la->la_smp_rate),
la->la_count);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{And0_disable, adv_trig, re_trig, mac_trig}= {%d, %d, %d, %d}\n",
la->la_and0_disable, la->adv_trig_i.adv_trig_en,
la->la_re_trig_i.re_trig_en,
trig_mac->la_mac_trig_en);
halbb_la_run(bb);
}
LA_END:
*_used = used;
*_out_len = out_len;
}
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_la_mode.c
|
C
|
agpl-3.0
| 76,429
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_LA_MODE_H__
#define __HALBB_LA_MODE_H__
/*@--------------------------[Define] ---------------------------------------*/
#define LA_CHK_PTRN_NUM 4
/*@--------------------------[Enum]------------------------------------------*/
enum la_mac_polling_state {
LA_HW_IDLE = 0,
LA_HW_START = 1,
LA_HW_FINISH_STOP = 2,
LA_HW_FINISH_TIMEOUT = 3,
LA_HW_RE_START = 4
};
enum la_mode_state_t {
LA_STATE_IDLE = 0,
LA_STATE_MAIN = 1,
LA_STATE_GET_DLE_BUF = 2,
LA_STATE_WAIT_RESTART = 3
};
enum la_buff_mode_t {
LA_BUFF_64K = 0,
LA_BUFF_128K = 1,
LA_BUFF_192K = 2,
LA_BUFF_256K = 3,
LA_BUFF_320K = 4,
LA_BUF_DISABLE = 0xff
};
enum la_bb_smp_clk {
LA_SMP_CLK_80 = 0,
LA_SMP_CLK_40 = 1,
LA_SMP_CLK_20 = 2,
LA_SMP_CLK_10 = 3,
LA_SMP_CLK_5 = 4,
LA_SMP_CLK_2_5 = 5,
LA_SMP_CLK_1_25 = 6,
LA_SMP_CLK_160 = 7
};
enum la_dma_data_type_t {
DMA00_NRML_1s_14b = 0,
DMA01_NRML_2s_12b = 1,
DMA02_NRML_2s_13b = 2,
DMA03_NRML_2s_14b = 3,
DMA04_NRML_3s_08b = 4,
DMA05_NRML_3s_09b = 5,
DMA06_NRML_3s_10b = 6,
DMA07_NRML_4s_07b = 7,
DMA08_NRML_4s_08b = 8,
DMA09_DUAL_4s_12b = 9,
DMA10_DUAL_4s_13b = 10,
DMA11_DUAL_4s_14b = 11,
DMA12_MPHS_1s_2p_12b = 12,
DMA13_MPHS_1s_3p_10b = 13,
DMA14_MPHS_1s_4p_08b = 14,
DMA15_MPHS_2s_2p_08b = 15,
DMA16_DBG = 16,
DMA17_DUAL_WB_1s_14b = 17,
DMA18_DUAL_WB_2s_14b = 18,
DMA19_DUAL_WB_3s_14b = 19,
DMA20_DUAL_WB_4s_14b = 20
};
/*@--------------------------[Structure]-------------------------------------*/
struct la_ptrn_chk_info {
u32 smp_point;
u32 la_ptrn_chk_mask; /*if mask=0: disable pattern chk, for MSB 32bit only*/
u32 la_ptrn_chk_val;
};
struct la_print_info {
bool is_la_print;
u8 print_len; /*0: all, 1:partial*/
u8 print_mode; /*0: hex, 1:unsign, 2:sign*/
u8 print_lsb;
u8 print_msb;
};
struct la_dma_info {
u8 dma_dbgport_base_n;
u8 dma_a_path_sel;
u8 dma_b_path_sel;
u8 dma_c_path_sel;
u8 dma_d_path_sel;
u8 dma_a_src_sel;
u8 dma_b_src_sel;
u8 dma_c_src_sel;
u8 dma_d_src_sel;
u8 dma_hdr_sel_63;
u8 dma_hdr_sel_62;
u8 dma_hdr_sel_61;
u8 dma_hdr_sel_60;
bool dma_a_ck160_dly_en;
bool dma_b_ck160_dly_en;
bool dma_c_ck160_dly_en;
bool dma_d_ck160_dly_en;
bool dma_dbgport_phy_sel;
enum la_dma_data_type_t dma_data_type;
};
struct la_string_info {
u32 *octet;
u32 length;
u32 buffer_size; /*Byte*/
u32 start_pos;
u32 end_pos; /*buf addr*/
u32 smp_number_max; /*number of LA sample*/
};
struct la_re_trig_info {
bool re_trig_en;
u16 re_trig_wait_cnt;
/*Re-trig*/
bool la_re_trig_edge;
u8 la_re_and0_sel;
u8 la_re_and0_val;
bool la_re_and0_inv;
};
struct la_adv_trig_info {
bool adv_trig_en;
/*AND1*/
u32 la_and1_mask; /*sel all 0 = disable*/
u32 la_and1_val;
bool la_and1_inv;
/*AND2*/
bool la_and2_en;
bool la_and2_inv;
u32 la_and2_val;
u32 la_and2_mask;
u8 la_and2_sign; /*0: unsigned, 1:signed, 2:norm*/
/*AND3*/
bool la_and3_en;
bool la_and3_inv;
u32 la_and3_val;
u32 la_and3_mask;
u8 la_and3_sign; /*0: unsigned, 1:signed, 2:norm*/
/*AND4*/
bool la_and4_en;
u16 la_and4_rate; /*rate_idx*/
bool la_and4_inv;
/*AND5*/
u8 la_and5_sel;
bool la_and5_inv;
u8 la_and5_val;
/*AND6*/
u8 la_and6_sel;
bool la_and6_inv;
u8 la_and6_val;
/*AND7*/
u8 la_and7_sel;
bool la_and7_inv;
u8 la_and7_val;
};
struct la_trig_mac_info {
bool la_mac_trig_en; /*sw tag*/
bool la_mac_and0_en;
u8 la_mac_and0_sel; /*0~2: cca, crc_er, crc_ok*/
u8 la_mac_and0_mac_sel; /*0: true mac, 1: pmac*/
bool la_mac_and1_en;
bool la_mac_and2_en;
u8 la_mac_and2_frame_sel; /*6-bit mac hdr*/
};
struct la_mac_cfg_info {
enum la_buff_mode_t mac_la_buf_sel;
bool mac_alloc_success;
u32 la_trigger_time; /*mu sec*/
u8 mac_la_en;
u8 mac_la_restart_en;
u8 mac_la_timeout_en;
u8 mac_la_data_loss_imr;/*Error flag mask bit for LA data loss due to pktbuffer busy */
u8 mac_la_timeout_val; /*0:1s, 1:2s, 2:4s, 3:8s*/
};
struct bb_la_cr_info {
u32 la_clk_en;
u32 la_clk_en_m;
u32 la_en;
u32 la_en_m;
u32 dma_dbgport_base_n;
u32 dma_dbgport_base_n_m;
u32 dma_a_path_sel;
u32 dma_a_path_sel_m;
u32 dma_b_path_sel;
u32 dma_b_path_sel_m;
u32 dma_c_path_sel;
u32 dma_c_path_sel_m;
u32 dma_d_path_sel;
u32 dma_d_path_sel_m;
u32 dma_a_src_sel;
u32 dma_a_src_sel_m;
u32 dma_b_src_sel;
u32 dma_b_src_sel_m;
u32 dma_c_src_sel;
u32 dma_c_src_sel_m;
u32 dma_d_src_sel;
u32 dma_d_src_sel_m;
u32 la_smp_rate;
u32 la_smp_rate_m;
u32 rdrdy_3_phase_en;
u32 rdrdy_3_phase_en_m;
u32 la_trigger_edge;
u32 la_trigger_edge_m;
u32 dma_hdr_sel_63;
u32 dma_hdr_sel_63_m;
u32 dma_hdr_sel_62;
u32 dma_hdr_sel_62_m;
u32 dma_hdr_sel_61;
u32 dma_hdr_sel_61_m;
u32 dma_hdr_sel_60;
u32 dma_hdr_sel_60_m;
u32 dma_a_ck160_dly_en;
u32 dma_a_ck160_dly_en_m;
u32 dma_b_ck160_dly_en;
u32 dma_b_ck160_dly_en_m;
u32 dma_dbgport_phy_sel;
u32 dma_dbgport_phy_sel_m;
u32 dma_data_type;
u32 dma_data_type_m;
u32 r_dma_rdrdy;
u32 r_dma_rdrdy_m;
u32 la_and0_bit_sel;
u32 la_and0_bit_sel_m;
u32 la_trigger_cnt;
u32 la_trigger_cnt_m;
u32 and0_trig_disable;
u32 and0_trig_disable_m;
u32 la_and1_inv;
u32 la_and1_inv_m;
u32 la_and2_en;
u32 la_and2_en_m;
u32 la_and2_inv;
u32 la_and2_inv_m;
u32 la_and3_en;
u32 la_and3_en_m;
u32 la_and3_inv;
u32 la_and3_inv_m;
u32 la_and4_en;
u32 la_and4_en_m;
u32 la_and4_rate;
u32 la_and4_rate_m;
u32 la_and4_inv;
u32 la_and4_inv_m;
u32 la_and1_mask;
u32 la_and1_mask_m;
u32 la_and1_val;
u32 la_and1_val_m;
u32 la_and2_mask;
u32 la_and2_mask_m;
u32 la_and2_val;
u32 la_and2_val_m;
u32 la_and3_mask;
u32 la_and3_mask_m;
u32 la_and3_val;
u32 la_and3_val_m;
u32 la_and5_sel;
u32 la_and5_sel_m;
u32 la_and5_val;
u32 la_and5_val_m;
u32 la_and5_inv;
u32 la_and5_inv_m;
u32 la_and6_sel;
u32 la_and6_sel_m;
u32 la_and6_val;
u32 la_and6_val_m;
u32 la_and6_inv;
u32 la_and6_inv_m;
u32 la_and7_sel;
u32 la_and7_sel_m;
u32 la_and7_val;
u32 la_and7_val_m;
u32 la_and7_inv;
u32 la_and7_inv_m;
u32 la_brk_sel;
u32 la_brk_sel_m;
u32 la_mac_and1_en;
u32 la_mac_and1_en_m;
u32 la_mac_and2_en;
u32 la_mac_and2_en_m;
u32 la_mac_and0_sel;
u32 la_mac_and0_sel_m;
u32 la_mac_and0_en;
u32 la_mac_and0_en_m;
u32 la_mac_and0_mac_sel;
u32 la_mac_and0_mac_sel_m;
u32 la_and2_sign;
u32 la_and2_sign_m;
u32 la_and3_sign;
u32 la_and3_sign_m;
u32 la_re_trig_edge;
u32 la_re_trig_edge_m;
u32 la_re_and1_sel;
u32 la_re_and1_sel_m;
u32 la_re_and1_val;
u32 la_re_and1_val_m;
u32 la_re_and1_inv;
u32 la_re_and1_inv_m;
};
struct bb_la_mode_info {
struct bb_la_cr_info bb_la_cr_i;
struct la_string_info la_string_i;
enum la_mode_state_t la_mode_state;
u32 la_dbg_port;
u32 la_count;
u32 smp_number;
u32 txff_page;
bool not_stop_trig; /*set impossible trigger condition*/
u8 la_basic_mode_sel; /*0:bb_mode, mac mode*/
/*[General setting]*/
u8 la_polling_cnt;
u8 la_trigger_cnt;
u8 la_trigger_edge; /*0: p-edge, 1: n-edge*/
enum la_bb_smp_clk la_smp_rate;
/*[AND-0 sel]*/
bool la_and0_disable;
u32 la_and0_bit_sel; /*And0 trigger bit sel*/
struct la_dma_info la_dma_i;
struct la_re_trig_info la_re_trig_i;
struct la_adv_trig_info adv_trig_i;
struct la_trig_mac_info la_trig_mac_i;
struct la_mac_cfg_info la_mac_cfg_i; /*MAC CR Control*/
struct la_print_info la_print_i;
struct la_ptrn_chk_info la_ptrn_chk_i[LA_CHK_PTRN_NUM];
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_la_re_trig_watchdog(struct bb_info *bb);
void halbb_la_run(struct bb_info *bb);
void halbb_la_deinit(struct bb_info *bb);
void halbb_la_init(struct bb_info *bb);
void halbb_cr_cfg_la_init(struct bb_info *bb);
void halbb_la_cmd_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_la_mode.h
|
C
|
agpl-3.0
| 8,752
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_LA_MODE_EX_H__
#define __HALBB_LA_MODE_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_la_mode_ex.h
|
C
|
agpl-3.0
| 1,363
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
const u32 db_invert_table[12][8] = {
{10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */
{64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */
{401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */
{316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */
{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */
{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */
{79433, 100000, 125893, 158489, 199526, 251189, 316228,
398107}, /* @U(32,0) */
{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262,
2511886}, /* @U(32,0) */
{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,
15848932}, /* @U(32,0) */
{19952623, 25118864, 31622777, 39810717, 50118723, 63095734,
79432823, 100000000}, /* @U(32,0) */
{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,
501187234, 630957345}, /* @U(32,0) */
{794328235, 1000000000, 1258925412, 1584893192, 1995262315,
2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */
/*Y = 10*log(X)*/
s32 halbb_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
{
s32 Y, integer = 0, decimal = 0;
u32 i;
if (X == 0)
X = 1; /* @log2(x), x can't be 0 */
for (i = (total_bit - 1); i > 0; i--) {
if (X & BIT(i)) {
integer = i;
if (i > 0) {
/*decimal is 0.5dB*3=1.5dB~=2dB */
decimal = (X & BIT(i - 1)) ? 2 : 0;
}
break;
}
}
Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */
return Y;
}
s32 halbb_sign_conversion(s32 val, u32 total_bit)
{
if (val & BIT(total_bit - 1))
val -= BIT(total_bit);
return val;
}
/*threshold must form low to high*/
u8 halbb_find_intrvl(struct bb_info *bb, u16 val, u8 *threshold, u8 len)
{
u8 i = 0;
u8 ret_val = 0;
u8 max_th = threshold[len - 1];
for (i = 0; i < len; i++) {
if (val < threshold[i]) {
ret_val = i;
break;
} else if (val >= max_th) {
ret_val = len;
break;
}
}
return ret_val;
}
void halbb_seq_sorting(struct bb_info *bb, u32 *val, u32 *idx, u32 *idx_out,
u8 seq_length)
{
u8 i = 0, j = 0, tmp = 0;
u32 tmp_a, tmp_b;
u32 tmp_idx_a, tmp_idx_b;
for (i = 0; i < seq_length; i++)
idx[i] = i;
for (i = 0; i < (seq_length - 1); i++) {
tmp = seq_length - 1 - i; /*to prevent WIN WHQL warning*/
for (j = 0; j < tmp; j++) {
tmp_a = val[j];
tmp_b = val[j + 1];
tmp_idx_a = idx[j];
tmp_idx_b = idx[j + 1];
if (tmp_a < tmp_b) {
val[j] = tmp_b;
val[j + 1] = tmp_a;
idx[j] = tmp_idx_b;
idx[j + 1] = tmp_idx_a;
}
}
}
for (i = 0; i < seq_length; i++)
idx_out[idx[i]] = i + 1;
}
u32 halbb_convert_to_db(u64 val)
{
u8 i;
u8 j;
u32 dB;
if (val >= db_invert_table[11][7])
return 96; /* @maximum 96 dB */
for (i = 0; i < 12; i++) {
if (i <= 2 && (val << FRAC_BITS) <= db_invert_table[i][7])
break;
else if (i > 2 && val <= db_invert_table[i][7])
break;
}
for (j = 0; j < 8; j++) {
if (i <= 2 && (val << FRAC_BITS) <= db_invert_table[i][j])
break;
else if (i > 2 && i < 12 && val <= db_invert_table[i][j])
break;
}
/*special cases*/
if (j == 0 && i == 0)
goto end;
if (i == 3 && j == 0) {
if (db_invert_table[3][0] - val >
val - (db_invert_table[2][7] >> FRAC_BITS)) {
i = 2;
j = 7;
}
goto end;
}
if (i < 3)
val = val << FRAC_BITS; /*@elements of row 0~2 shift left*/
/*compare difference to get precise dB*/
if (j == 0) {
if (db_invert_table[i][j] - val >
val - db_invert_table[i - 1][7]) {
i = i - 1;
j = 7;
}
} else {
if (db_invert_table[i][j] - val >
val - db_invert_table[i][j - 1]) {
j = j - 1;
}
}
end:
dB = (i << 3) + j + 1;
return dB;
}
u64 halbb_db_2_linear(u32 val)
{
u8 i = 0;
u8 j = 0;
u64 linear = 0;
val = val & 0xFF;
/* @1dB~96dB */
if (val > 96) {
val = 96;
} else if (val < 1) {
linear = 1;
return linear;
}
i = (u8)((val - 1) >> 3);
j = (u8)(val - 1) - (i << 3);
linear = db_invert_table[i][j];
if (i > 2)
linear = linear << FRAC_BITS;
return linear;
}
u16 halbb_show_fraction_num(u32 frac_val, u8 bit_num)
{
u8 i = 0;
u16 val = 0;
u16 base = 500; /* Fix to 3 digit after the decimal point*/
for (i = bit_num; i > 0; i--) {
if (frac_val & BIT(i - 1))
val += (base >> (bit_num - i));
}
return val;
}
u32 halbb_show_fraction_num_opt(u32 frac_val, u8 bit_num, u8 decimal_place)
{
u8 i = 0;
u32 val = 0;
u32 base = 5;
if (decimal_place == 0)
return 0;
if (decimal_place > 9)
decimal_place = 9;
for (i = 1; i < decimal_place; i++)
base *= 10;
for (i = bit_num; i > 0; i--) {
if (frac_val & BIT(i - 1))
val += (base >> (bit_num - i));
}
return val;
}
u16 halbb_ones_num_in_bitmap(u64 val, u8 size)
{
u8 i = 0;
u8 ones_num = 0;
for (i = 0; i < size; i++) {
if (val & BIT(0))
ones_num++;
val = val >> 1;
}
return ones_num;
}
u64 halbb_gen_mask_from_0(u8 mask_num)
{
u8 i = 0;
u64 bitmask = 0;
if (mask_num > 64 || mask_num == 0)
return 0;
for (i = 0; i < mask_num; i++)
bitmask = (bitmask << 1) | BIT(0);
return bitmask;
}
u64 halbb_gen_mask(u8 up_num, u8 low_num)
{
if (up_num < low_num)
return 0;
return (halbb_gen_mask_from_0(up_num - low_num + 1) << low_num);
}
u32 halbb_cal_bit_shift(u32 bit_mask)
{
u32 i;
for (i = 0; i <= 31; i++) {
if ((bit_mask >> i) & BIT0)
break;
}
return i;
}
s32 halbb_cnvrt_2_sign(u32 val, u8 bit_num)
{
if (bit_num > 32)
return (s32)val;
if (val & BIT(bit_num - 1)) /*Sign BIT*/
val -= (1 << bit_num); /*@2's*/
return val;
}
s64 halbb_cnvrt_2_sign_64(u64 val, u8 bit_num)
{
u64 one = 1;
s64 val_sign = (s64)val;
if (bit_num >= 64)
return (s64)val;
if (val & (one << (bit_num - 1))) /*Sign BIT*/
val_sign = val - (one << bit_num); /*@2's*/
return val_sign;
}
void halbb_print_sign_frac_digit(struct bb_info *bb, u32 val, u8 total_bit_num,
u8 frac_bit_num, char *buf, u16 buf_size)
{
s32 val_s32 = (s32)val;
u32 val_abs = 0;
u32 mask_frac = 0;
u32 frac_digit = 0;
val_abs = ABS_32(val_s32);
mask_frac = (u32)halbb_gen_mask_from_0(frac_bit_num);
frac_digit = halbb_show_fraction_num(val_abs & mask_frac, frac_bit_num);
if (frac_bit_num == 1) {
frac_digit = (val & 0x1) * 5;
_os_snprintf(buf, buf_size, "%s%d.%d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else if (frac_bit_num == 2) {
frac_digit = (val & 0x3) * 25;
_os_snprintf(buf, buf_size, "%s%d.%02d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else if (frac_bit_num == 3) {
frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 3);
_os_snprintf(buf, buf_size, "%s%d.%03d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else if (frac_bit_num == 4) {
frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 4);
_os_snprintf(buf, buf_size, "%s%d.%04d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else if (frac_bit_num == 5) {
frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 5);
_os_snprintf(buf, buf_size, "%s%d.%05d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else {
frac_digit = halbb_show_fraction_num_opt(val_abs & mask_frac, frac_bit_num, 8);
_os_snprintf(buf, buf_size, "%s%d.%08d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
}
}
char *halbb_print_sign_frac_digit2(struct bb_info *bb, u32 val, u8 total_bit_num,
u8 frac_bit_num)
{
char *buf = bb->dbg_buf;
u16 buf_size = HALBB_SNPRINT_SIZE;
s32 val_s32 = (s32)val;
u32 val_abs = 0;
u32 mask_frac = 0;
u16 frac_digit = 0;
val_abs = ABS_32(val_s32);
mask_frac = (u32)halbb_gen_mask_from_0(frac_bit_num);
if (frac_bit_num == 1) {
frac_digit = (val & 0x1) * 5;
_os_snprintf(buf, buf_size, "%s%d.%d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else if (frac_bit_num == 2) {
frac_digit = (val & 0x3) * 25;
_os_snprintf(buf, buf_size, "%s%d.%02d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
} else {
frac_digit = halbb_show_fraction_num(val_abs & mask_frac, frac_bit_num);
_os_snprintf(buf, buf_size, "%s%d.%03d", (val_s32 >= 0) ? "" : "-",
val_abs >> frac_bit_num, frac_digit);
}
return buf;
}
void halbb_print_buff_64(struct bb_info *bb, u8 *addr, u16 length) /*unit: Byte*/
{
u64 *buff_tmp = NULL;
u8 print_len = length >> 3;
u8 i;
if (length % 8)
print_len++;
buff_tmp = (u64 *)addr;
for (i = 0; i < print_len; i++) {
BB_TRACE("[%02d]0x%016llx\n", i, buff_tmp[i]);
}
}
void halbb_print_buff_32(struct bb_info *bb, u8 *addr, u16 length) /*unit: Byte*/
{
u32 *buff_tmp = NULL;
u8 print_len = length >> 2;
u8 i;
if (length % 4)
print_len++;
buff_tmp = (u32 *)addr;
for (i = 0; i < print_len; i++) {
BB_TRACE("0x%08x\n", buff_tmp[i]);
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_math_lib.c
|
C
|
agpl-3.0
| 9,851
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_MATH_LIB_H__
#define __HALBB_MATH_LIB_H__
/*@--------------------------[Define] ---------------------------------------*/
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define RFREGOFFSETMASK 0xfffff
#define KB_2_MB(val) ((val) >> 10)
#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_))
#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_))
#define DIFF_2(_x_, _y_) (((_x_) >= (_y_)) ? ((_x_) - (_y_)) : ((_y_) - (_x_)))
#define SUBTRACT_TO_0(_x_, _y_) (((_x_) >= (_y_)) ? ((_x_) - (_y_)) : 0)
#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false)
#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false)
#define NOT_GREATER(_x_, _y_) (((_x_) > (_y_)) ? (_y_) : (_x_))
#define BYTE_DUPLICATE_2_DWORD(B0) \
(((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))
#define BYTE_2_DWORD(B3, B2, B1, B0) \
(((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
#define BYTE_2_WORD(B1, B0) \
(((B1) << 8) | (B0))
#define BIT_2_BYTE(B3, B2, B1, B0) \
(((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))
#define NIBBLE_2_WORD(B3, B2, B1, B0) \
((((B3) & 0xf) << 12) | (((B2) & 0xf) << 8) |\
(((B1) & 0xf) << 4) | ((B0) & 0xf))
#define NIBBLE_2_DWORD(B7, B6, B5, B4, B3, B2, B1, B0) \
((((B7) & 0xf) << 28) | (((B6) & 0xf) << 24) | \
(((B5) & 0xf) << 20) | (((B4) & 0xf) << 16) | \
(((B3) & 0xf) << 12) | (((B2) & 0xf) << 8) | \
(((B1) & 0xf) << 4) | ((B0) & 0xf))
#define HALBB_DIV(a, b) ((b) ? ((a) / (b)) : 0)
#define ABS_32(X) (((X) & BIT(31)) ? (0 - (X)) : (X))
#define ABS_16(X) (((X) & BIT(15)) ? (0 - (X)) : (X))
#define ABS_8(X) (((X) & BIT(7)) ? (0 - (X)) : (X))
#define DIVIDED_2(X) ((X) >> 1)
#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)
#define DIVIDED_4(X) ((X) >> 2)
#define WEIGHTING_AVG_2(v1, w1, v2, w2) \
(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))
#define MA_ACC(old, new_val, ma, ma_max) ((old) - ((old << (ma_max - ma)) >> (ma_max)) + (new_val << (ma_max - ma)))
#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))
#define FRAC_BITS 3
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
s32 halbb_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
s32 halbb_sign_conversion(s32 val, u32 total_bit);
u8 halbb_find_intrvl(struct bb_info *bb, u16 val, u8 *threshold, u8 len);
void halbb_seq_sorting(struct bb_info *bb, u32 *val, u32 *idx, u32 *idx_out,
u8 seq_length);
u16 halbb_show_fraction_num(u32 frac_val, u8 bit_num);
u16 halbb_ones_num_in_bitmap(u64 val, u8 size);
u64 halbb_gen_mask_from_0(u8 mask_num);
u64 halbb_gen_mask(u8 up_num, u8 low_num);
u32 halbb_cal_bit_shift(u32 bit_mask);
s32 halbb_cnvrt_2_sign(u32 val, u8 bit_num);
s64 halbb_cnvrt_2_sign_64(u64 val, u8 bit_num);
void halbb_print_sign_frac_digit(struct bb_info *bb, u32 val, u8 total_bit_num,
u8 frac_bit_num, char *buf, u16 buf_size);
char *halbb_print_sign_frac_digit2(struct bb_info *bb, u32 val, u8 total_bit_num,
u8 frac_bit_num);
void halbb_print_buff_64(struct bb_info *bb, u8 *addr, u16 length);
void halbb_print_buff_32(struct bb_info *bb, u8 *addr, u16 length);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_math_lib.h
|
C
|
agpl-3.0
| 4,398
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_MATH_LIB_EX_H__
#define __HALBB_MATH_LIB_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u32 halbb_convert_to_db(u64 val);
u64 halbb_db_2_linear(u32 val);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_math_lib_ex.h
|
C
|
agpl-3.0
| 1,447
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
u16 halbb_mp_get_tx_ok(struct bb_info *bb, u32 rate_index,
enum phl_phy_idx phy_idx)
{
u32 tx_ok;
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
if (halbb_is_cck_rate(bb, (u16)rate_index))
tx_ok = halbb_get_reg(bb, cr->cnt_ccktxon, cr->cnt_ccktxon_m);
else
tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx);
return (u16)tx_ok;
}
u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0, he_ok = 0;
u32 crc_ok;
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
if (phy_idx == HW_PHY_0)
cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p0, cr->cnt_cck_crc32ok_p0_m);
else
cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p1, cr->cnt_cck_crc32ok_p1_m);
ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx);
ht_ok = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_ok, cr->cnt_ht_crc_ok_m, phy_idx);
vht_ok = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_ok, cr->cnt_vht_crc_ok_m, phy_idx);
he_ok = halbb_get_reg_cmn(bb, cr->cnt_he_crc_ok, cr->cnt_he_crc_ok_m, phy_idx);
crc_ok = cck_ok + ofdm_ok + ht_ok + vht_ok + he_ok;
// === [Reset cnt] === //
if (crc_ok == 65535) {
halbb_mp_reset_cnt(bb);
crc_ok = 0;
}
return crc_ok;
}
u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0, he_err = 0;
u32 crc_err;
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
if (phy_idx == HW_PHY_0)
cck_err = halbb_get_reg(bb, cr->cnt_cck_crc32fail_p0, cr->cnt_cck_crc32fail_p0_m);
else
cck_err = halbb_get_reg(bb, cr->cnt_cck_crc32fail_p1, cr->cnt_cck_crc32fail_p1_m);
ofdm_err = halbb_get_reg_cmn(bb, cr->cnt_l_crc_err, cr->cnt_l_crc_err_m, phy_idx);
ht_err = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_err, cr->cnt_ht_crc_err_m, phy_idx);
vht_err = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_err, cr->cnt_vht_crc_err_m, phy_idx);
he_err = halbb_get_reg_cmn(bb, cr->cnt_he_crc_err, cr->cnt_he_crc_err_m, phy_idx);
crc_err = cck_err + ofdm_err + ht_err + vht_err + he_err;
// === [Reset cnt] === //
if (crc_err == 65535) {
halbb_mp_reset_cnt(bb);
crc_err = 0;
}
return crc_err;
}
void halbb_mp_reset_cnt(struct bb_info *bb)
{
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
// PHY0 cnt reset
halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 1, HW_PHY_0);
halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 0, HW_PHY_0);
// PHY1 cnt reset
halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 1, HW_PHY_1);
halbb_set_reg_cmn(bb, cr->rst_all_cnt, cr->rst_all_cnt_m, 0, HW_PHY_1);
}
void halbb_mp_psts_setting(struct bb_info *bb, u32 ie_bitmap_setting)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (ie_bitmap_setting & BIT(IE00_CMN_CCK)) {
halbb_set_reg(bb, cr->phy_sts_bitmap_he_mu, cr->phy_sts_bitmap_he_mu_m, BIT(IE00_CMN_CCK));
halbb_set_reg(bb, cr->phy_sts_bitmap_vht_mu, cr->phy_sts_bitmap_vht_mu_m, BIT(IE00_CMN_CCK));
halbb_set_reg(bb, cr->phy_sts_bitmap_cck, cr->phy_sts_bitmap_cck_m, BIT(IE00_CMN_CCK));
halbb_set_reg(bb, cr->phy_sts_bitmap_legacy, cr->phy_sts_bitmap_legacy_m, BIT(IE00_CMN_CCK));
halbb_set_reg(bb, cr->phy_sts_bitmap_ht, cr->phy_sts_bitmap_ht_m, BIT(IE00_CMN_CCK));
halbb_set_reg(bb, cr->phy_sts_bitmap_vht, cr->phy_sts_bitmap_vht_m, BIT(IE00_CMN_CCK));
halbb_set_reg(bb, cr->phy_sts_bitmap_he, cr->phy_sts_bitmap_he_m, BIT(IE00_CMN_CCK));
}
if (ie_bitmap_setting & BIT(IE01_CMN_OFDM)) {
halbb_set_reg(bb, cr->phy_sts_bitmap_he_mu, cr->phy_sts_bitmap_he_mu_m, BIT(IE01_CMN_OFDM));
halbb_set_reg(bb, cr->phy_sts_bitmap_vht_mu, cr->phy_sts_bitmap_vht_mu_m, BIT(IE01_CMN_OFDM));
halbb_set_reg(bb, cr->phy_sts_bitmap_cck, cr->phy_sts_bitmap_cck_m, BIT(IE01_CMN_OFDM));
halbb_set_reg(bb, cr->phy_sts_bitmap_legacy, cr->phy_sts_bitmap_legacy_m, BIT(IE01_CMN_OFDM));
halbb_set_reg(bb, cr->phy_sts_bitmap_ht, cr->phy_sts_bitmap_ht_m, BIT(IE01_CMN_OFDM));
halbb_set_reg(bb, cr->phy_sts_bitmap_vht, cr->phy_sts_bitmap_vht_m, BIT(IE01_CMN_OFDM));
halbb_set_reg(bb, cr->phy_sts_bitmap_he, cr->phy_sts_bitmap_he_m, BIT(IE01_CMN_OFDM));
}
BB_DBG(bb, DBG_PHY_CONFIG, "[MP] physts ie bitmap setting : 0x%08x\n", ie_bitmap_setting);
}
void
halbb_mp_get_psts_ie_bitmap(struct bb_info *bb, struct bb_mp_psts *bb_mp_physts)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
u32 *bitmap_ptr = &physts->physts_bitmap_recv;
u32 *mp_bitmap_ptr = &bb_mp_physts->ie_bitmap;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
mp_bitmap_ptr = bitmap_ptr;
}
void
halbb_mp_get_psts_ie_00(struct bb_info *bb, struct bb_mp_psts *bb_mp_physts)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i;
struct mp_physts_rslt_0 *mp_psts_0 = &bb_mp_physts->mp_physts_rslt_0_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
mp_psts_0 = (struct mp_physts_rslt_0 *)psts_0;
}
void
halbb_mp_get_psts_ie_01(struct bb_info *bb, struct bb_mp_psts *bb_mp_physts)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i;
//struct bb_mp_psts *mp_physts = &bb->bb_mp_psts_i;
struct mp_physts_rslt_1 *mp_psts_1 = &bb_mp_physts->mp_physts_rslt_1_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
mp_psts_1 = (struct mp_physts_rslt_1 *)psts_1;
}
void
halbb_mp_get_psts(struct bb_info *bb , struct bb_mp_psts *bb_mp_physts)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// IE bitmap info //
halbb_mp_get_psts_ie_bitmap(bb , bb_mp_physts);
// detail info of per IE //
if (bb_mp_physts->ie_bitmap & BIT(IE00_CMN_CCK)) {
halbb_mp_get_psts_ie_00(bb , bb_mp_physts);
}
if (bb_mp_physts->ie_bitmap & BIT(IE01_CMN_OFDM)) {
halbb_mp_get_psts_ie_01(bb , bb_mp_physts);
}
}
void halbb_keeper_cond(struct bb_info *bb, bool keeper_en, u8 keeper_trig_cond,
u8 dbg_sel, enum phl_phy_idx phy_idx)
{
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
halbb_set_reg_cmn(bb, cr->sts_keeper_en, cr->sts_keeper_en_m, keeper_en,
phy_idx); //0x0738[4]
halbb_set_reg_cmn(bb, cr->sts_keeper_trig_cond,
cr->sts_keeper_trig_cond_m, keeper_trig_cond, phy_idx); //0x0738[7:6]
halbb_set_reg_cmn(bb, cr->sts_dbg_sel, cr->sts_dbg_sel_m, dbg_sel,
phy_idx); //0x0738[30:28]
}
void halbb_dbg_port_sel(struct bb_info *bb, u16 dbg_port_sel, u8 dbg_port_ip_sel,
bool dbg_port_ref_clk_en, bool dbg_port_en)
{
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
halbb_set_reg(bb, cr->dbg_port_sel, 0xfff, dbg_port_sel); // 0x20f0[11:0]
halbb_set_reg(bb, cr->dbg_port_ip_sel, cr->dbg_port_ip_sel_m,
dbg_port_ip_sel); // 0x20f0[23:16]
halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m,
dbg_port_ref_clk_en); // 0x20f4[24]
halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, dbg_port_en); // 0x20f8[31]
}
u8 halbb_mp_get_rxevm(struct bb_info *bb, u8 user, u8 strm, bool rxevm_table)
{
u8 rx_evm;
u8 mode;
u32 user_mask[4] = {0xff000000, 0xff0000, 0xff00, 0xff};
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
if ((user >= 4) || (strm >= 4)) {
BB_WARNING("Invalid User or Stream\n");
return false;
}
/*=== [All tone] ===*/
halbb_set_reg(bb, cr->rpt_tone_evm_idx, 0x3ff, 0); // Only use [9:0], Total [10:0]
halbb_set_reg_cmn(bb, cr->rpt_tone_evm_idx, 0x3ff, 0, HW_PHY_1);
/*=== [Switch MUX] ===*/
halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, 0);
halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, 1);
halbb_set_reg(bb, cr->dbg_port_ip_sel, 0x1f, 2); // Only use [4:0], Total [7:0]
halbb_set_reg(bb, cr->dbg_port_sel, 0xf0, 1); // Only use [7:4], Total [15:0]
mode = user + 1 + rxevm_table * 8;
halbb_set_reg(bb, cr->dbg_port_sel, 0xf, mode); // Only use [3:0], Total [15:0]
rx_evm = (u8)halbb_get_reg(bb, cr->dbg32_d, user_mask[strm]);
return rx_evm;
}
struct rxevm_physts halbb_mp_get_rxevm_physts(struct bb_info *bb,
enum phl_phy_idx phy_idx)
{
// Note: Only supports 2SS ! //
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
bool is_cck;
u8 i = 0;
u32 rxevm_tmp = 0;
u8 addr_ofst[2] = {0, 20};
u32 dbg_port = 0;
u16 tmp = 0;
u32 bitmap[7] = {cr->phy_sts_bitmap_he_mu, cr->phy_sts_bitmap_vht_mu,
cr->phy_sts_bitmap_trigbase, cr->phy_sts_bitmap_legacy,
cr->phy_sts_bitmap_ht, cr->phy_sts_bitmap_vht,
cr->phy_sts_bitmap_he};
u32 bitmap_m[7] = {cr->phy_sts_bitmap_he_mu_m,
cr->phy_sts_bitmap_vht_mu_m,
cr->phy_sts_bitmap_trigbase_m,
cr->phy_sts_bitmap_legacy_m, cr->phy_sts_bitmap_ht_m,
cr->phy_sts_bitmap_vht_m, cr->phy_sts_bitmap_he_m};
u32 bitmap_restore[7] = {0};
BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] halbb_mp_get_rxevm_physts==========================>\n");
//=== Backup Bitmap value ===//
for (i = 0; i < 7; i++)
bitmap_restore[i] = halbb_get_reg_cmn(bb, bitmap[i], bitmap_m[i], phy_idx);
//=== Set Bitmap ===//
for (i = 0; i < 7; i++)
halbb_set_reg_cmn(bb, bitmap[i], bitmap_m[i], 0x300002, phy_idx);
// Set keeper condition //
halbb_keeper_cond(bb, true, 0x1, 0x2, phy_idx);
// DBG port polling //
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
tmp = (phy_idx == HW_PHY_0 ? 0x700 : 0x701);
halbb_dbg_port_sel(bb, tmp, 0x1, 0x0, 0x1);
} else {
dbg_port = halbb_get_bb_dbg_port_idx(bb);
BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
return bb->rxevm;
}
// Config user0
halbb_set_reg_cmn(bb, cr->sts_user_sel, cr->sts_user_sel_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 1, phy_idx);
halbb_delay_us(bb, 2);
if (halbb_get_reg(bb, cr->dbg32_d, BIT(5)) == 1) {
// Determine CCK pkt
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 1, phy_idx);
is_cck = (halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xf, phy_idx) == 11) ? true : false;
// CCK
if (is_cck) {
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 5, phy_idx);
rxevm_tmp = halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff00, phy_idx); // Only use [15:8], Total [31:0]
bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0 = (u8)rxevm_tmp;
bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1 = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm][CCK][Phy-%d] rxevm_ss_0=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0);
BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm][CCK][Phy-%d] rxevm_ss_1=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1);
} else {
if ((bb->ic_type == BB_RTL8852A) || (bb->ic_type == BB_RTL8852B)) {
for (i = 0; i < 2; i++) {
// Usr0
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 15 + addr_ofst[i], phy_idx);
rxevm_tmp = halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xffff00, phy_idx); // Only use [23:8], Total [31:0]
bb->rxevm.rxevm_seg[i].rxevm_user[0].rxevm_ss_0 = (rxevm_tmp & 0xff);
bb->rxevm.rxevm_seg[i].rxevm_user[0].rxevm_ss_1 = ((rxevm_tmp & 0xff00) >> 8);
// Usr1
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 19 + addr_ofst[i], phy_idx);
bb->rxevm.rxevm_seg[i].rxevm_user[1].rxevm_ss_0 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx); // Only use [31:24], Total [31:0]
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 18 + addr_ofst[i], phy_idx);
bb->rxevm.rxevm_seg[i].rxevm_user[1].rxevm_ss_1 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff, phy_idx); // Only use [7:0], Total [31:0]
// Usr2
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 22 + addr_ofst[i], phy_idx);
rxevm_tmp = halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xffff00, phy_idx); // Only use [23:8], Total [31:0]
bb->rxevm.rxevm_seg[i].rxevm_user[2].rxevm_ss_0 = (rxevm_tmp & 0xff);
bb->rxevm.rxevm_seg[i].rxevm_user[2].rxevm_ss_1 = ((rxevm_tmp & 0xff00) >> 8);
// Usr3
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 26 + addr_ofst[i], phy_idx);
bb->rxevm.rxevm_seg[i].rxevm_user[3].rxevm_ss_0 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx); // Only use [31:24], Total [31:0]
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 29 + addr_ofst[i], phy_idx);
bb->rxevm.rxevm_seg[i].rxevm_user[3].rxevm_ss_1 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff, phy_idx); // Only use [7:0], Total [31:0]
}
} else {
// Usr0
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 15, phy_idx);
bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx);
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 19, phy_idx);
bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1 = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff000000, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] [Phy-%d] rxevm_ss_0=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0);
BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] [Phy-%d] rxevm_ss_1=0x%x\n", phy_idx, bb->rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1);
}
}
bb->bb_cmn_backup_i.last_rxevm_rpt = bb->rxevm;
} else {
BB_DBG(bb, DBG_PHY_CONFIG, "[Rxevm] No crc_ok\n");
bb->rxevm = bb->bb_cmn_backup_i.last_rxevm_rpt;
}
halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 0, phy_idx);
halbb_release_bb_dbg_port(bb);
//=== Restore Bitmap value ===//
//for (i = 0; i < 7; i++)
// halbb_set_reg_cmn(bb, bitmap[i], bitmap_m[i], bitmap_restore[i], phy_idx);
return bb->rxevm;
}
/*
u16 halbb_mp_get_pwdb_diff(struct bb_info *bb, enum rf_path path)
{
u16 pwdb_diff;
u32 rpt_addr[4] = {0x4048, 0x4060, 0x4078, 0x4090};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (path > RF_PATH_D) {
BB_WARNING("Invalid Path\n");
return false;
}
pwdb_diff = (u16)halbb_get_reg(bb, rpt_addr[path], 0xff800);
return pwdb_diff;
}
*/
u8 halbb_mp_get_rssi(struct bb_info *bb, enum rf_path path)
{
u8 rssi;
u32 dbg_port = 0;
#if 0
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
/*==== Error handling ====*/
if (path > RF_PATH_D) {
BB_WARNING("Invalid Path\n");
return false;
}
rssi = psts_h->rssi[path];
BB_DBG(bb, DBG_PHY_CONFIG, "[MP] rssi for Path-%d : %d\n", path, rssi);
#else
// RSSI_FD
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
// Phy0 / 1
halbb_set_reg_cmn(bb, cr->sts_keeper_en, cr->sts_keeper_en_m, 1, HW_PHY_0);
halbb_set_reg_cmn(bb, cr->sts_keeper_trig_cond, cr->sts_keeper_trig_cond_m, 1, HW_PHY_0);
halbb_set_reg_cmn(bb, cr->sts_dbg_sel, cr->sts_dbg_sel_m, 2, HW_PHY_0);
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, 0);
halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, 1);
halbb_set_reg(bb, cr->dbg_port_ip_sel, cr->dbg_port_ip_sel_m, 1);
halbb_set_reg(bb, cr->dbg_port_sel, 0xf00, 7); // Only use [11:8], Total [15:0]
halbb_set_reg(bb, cr->dbg_port_sel, 0xff, 0); // Only use [7:0], Total [15:0]
} else {
dbg_port = halbb_get_bb_dbg_port_idx(bb);
BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
return bb->bb_cmn_backup_i.last_rssi;
}
halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 1, HW_PHY_0);
halbb_delay_us(bb, 2);
if (halbb_get_reg(bb, cr->dbg32_d, BIT(5)) == 1) {
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 3, HW_PHY_0);
rssi = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff00, HW_PHY_0); // Only use [23:8], Total [31:0]
bb->bb_cmn_backup_i.last_rssi = rssi;
} else {
rssi = bb->bb_cmn_backup_i.last_rssi;
}
halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 0, HW_PHY_0);
halbb_release_bb_dbg_port(bb);
#endif
return rssi;
}
s32 halbb_rssi_cal(struct bb_info *bb, u8 rssi_0, u8 rssi_1, bool is_higher_rssi_path, enum phl_phy_idx phy_idx)
{
u8 rssi_diff = rssi_0 - rssi_1;
s32 rssi_cal;
u64 alpha_tmp;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (rssi_diff == 0)
return 0;
rssi_diff = rssi_diff % 2 ? (rssi_diff + 1) >> 1 : rssi_diff >> 1;
alpha_tmp = halbb_db_2_linear((u32) rssi_diff);
alpha_tmp = (alpha_tmp >> 2) % 2 ? (alpha_tmp >> FRAC_BITS) + 1 : alpha_tmp >> FRAC_BITS;
if (is_higher_rssi_path)
rssi_cal = halbb_convert_to_db(alpha_tmp) -
halbb_convert_to_db(alpha_tmp + 1) + 3;
else
rssi_cal = 3 - halbb_convert_to_db(alpha_tmp + 1);
return rssi_cal;
}
struct rssi_physts halbb_get_mp_rssi_physts(struct bb_info *bb, enum rf_path path, enum phl_phy_idx phy_idx)
{
// RSSI_FD
struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i;
struct bb_physts_info physts = bb->bb_physts_i;
struct bb_physts_rslt_hdr_info psts_h = physts.bb_physts_rslt_hdr_i;
struct bb_efuse_info efuse = bb->bb_efuse_i;
struct rssi_physts rssi_rpt;
bool rssi_0_high = psts_h.rssi[0] > psts_h.rssi[1] ? true : false;
s32 efuse_tmp = 0;
u8 band = 0;
u8 central_ch = bb->hal_com->band[phy_idx].cur_chandef.center_ch;
u8 RPL = 0;
u32 dbg_port = 0;
s32 cal_tmp[2] = {0};
halbb_mem_set(bb, &rssi_rpt,0,sizeof(rssi_rpt));
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// 2G Band: (0)
// 5G Band: (1):Low, (2): Mid, (3):High
if (central_ch >= 0 && central_ch <= 14)
band = 0;
else if (central_ch >= 36 && central_ch <= 64)
band = 1;
else if (central_ch >= 100 && central_ch <= 144)
band = 2;
else if (central_ch >= 149 && central_ch <= 177)
band = 3;
else
band = 0;
efuse_tmp = efuse.gain_offset[RF_PATH_A][band] - efuse.gain_offset[RF_PATH_B][band];
// Phy0 / 1
halbb_set_reg_cmn(bb, cr->sts_keeper_en, cr->sts_keeper_en_m, 1, HW_PHY_0);
halbb_set_reg_cmn(bb, cr->sts_keeper_trig_cond, cr->sts_keeper_trig_cond_m, 1, HW_PHY_0);
halbb_set_reg_cmn(bb, cr->sts_dbg_sel, cr->sts_dbg_sel_m, 2, HW_PHY_0);
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
halbb_set_reg(bb, cr->dbg_port_ref_clk_en, cr->dbg_port_ref_clk_en_m, 0);
halbb_set_reg(bb, cr->dbg_port_en, cr->dbg_port_en_m, 1);
halbb_set_reg(bb, cr->dbg_port_ip_sel, cr->dbg_port_ip_sel_m, 1);
halbb_set_reg(bb, cr->dbg_port_sel, 0xf00, 7); // Only use [11:8], Total [15:0]
halbb_set_reg(bb, cr->dbg_port_sel, 0xff, 0); // Only use [7:0], Total [15:0]
} else {
dbg_port = halbb_get_bb_dbg_port_idx(bb);
BB_TRACE("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
return bb->bb_cmn_backup_i.last_rssi_rpt;
}
halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 1, HW_PHY_0);
halbb_delay_us(bb, 2);
if (halbb_get_reg(bb, cr->dbg32_d, BIT(5)) == 1) {
halbb_set_reg_cmn(bb, cr->sts_keeper_addr, cr->sts_keeper_addr_m, 3, HW_PHY_0);
RPL = (u8)halbb_get_reg_cmn(bb, cr->sts_keeper_data, 0xff00, HW_PHY_0); // Only use [23:8], Total [31:0]
bb->bb_cmn_backup_i.last_rssi = RPL;
} else {
RPL = bb->bb_cmn_backup_i.last_rssi;
}
halbb_set_reg_cmn(bb, cr->sts_keeper_read, cr->sts_keeper_read_m, 0, HW_PHY_0);
halbb_release_bb_dbg_port(bb);
if (path == RF_PATH_A) {
rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)(RPL - 220);
rssi_rpt.rssi_seg[phy_idx].rssi[1] = 0;
} else if (path == RF_PATH_B) {
rssi_rpt.rssi_seg[phy_idx].rssi[0] = 0;
rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)(RPL - 220);
} else {
if (rssi_0_high) {
if (psts_h.rssi[0] - psts_h.rssi[1] > 12) {
rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)(RPL - 220 + 6);
rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)(psts_h.rssi[1] - 220);
} else {
cal_tmp[0] = halbb_rssi_cal(bb, psts_h.rssi[0], psts_h.rssi[1], true, phy_idx);
cal_tmp[1] = halbb_rssi_cal(bb, psts_h.rssi[0], psts_h.rssi[1], false, phy_idx);
rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)((RPL - 220) + (cal_tmp[0] << 1));
rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)((RPL - 220) + (efuse_tmp << 1) + (cal_tmp[1] << 1));
}
} else {
if (psts_h.rssi[1] - psts_h.rssi[0] > 12) {
rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)(psts_h.rssi[0] - 220);
rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)(RPL - 220 + 6);
} else {
cal_tmp[0] = halbb_rssi_cal(bb, psts_h.rssi[1], psts_h.rssi[0], false, phy_idx);
cal_tmp[1] = halbb_rssi_cal(bb, psts_h.rssi[1], psts_h.rssi[0], true, phy_idx);
rssi_rpt.rssi_seg[phy_idx].rssi[0] = (s32)((RPL - 220) + (cal_tmp[0] << 1));
rssi_rpt.rssi_seg[phy_idx].rssi[1] = (s32)((RPL - 220) + (efuse_tmp << 1) + (cal_tmp[1] << 1));
}
}
}
return rssi_rpt;
}
void halbb_mp_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
struct rxevm_physts rxevm;
halbb_mem_set(bb, &rxevm,0,sizeof(rxevm));
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"EVM({phy_idx (0~1)})\n");
} else if (_os_strcmp(input[1], "evm") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
rxevm = halbb_mp_get_rxevm_physts(bb, (enum phl_phy_idx)val[0]);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[MP] [User 0] [SS0] RXEVM = -%d\n",
rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0 >> 2);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[MP] [User 0] [SS1] RXEVM = -%d\n",
rxevm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1 >> 2);
}
*_used = used;
*_out_len = out_len;
}
void halbb_cr_cfg_mp_init(struct bb_info *bb)
{
struct bb_rpt_info *rpt_info = &bb->bb_rpt_i;
struct bb_rpt_cr_info *cr = &rpt_info->bb_rpt_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_52AA:
cr->cnt_ccktxon = CNT_CCKTXON_52AA;
cr->cnt_ccktxon_m = CNT_CCKTXON_52AA_M;
cr->cnt_ofdmtxon = CNT_OFDMTXON_52AA;
cr->cnt_ofdmtxon_m = CNT_OFDMTXON_52AA_M;
cr->cnt_cck_crc32ok_p0 = CNT_CCK_CRC32OK_P0_52AA;
cr->cnt_cck_crc32ok_p0_m = CNT_CCK_CRC32OK_P0_52AA_M;
cr->cnt_cck_crc32ok_p1 = CNT_CCK_CRC32OK_P1_52AA;
cr->cnt_cck_crc32ok_p1_m = CNT_CCK_CRC32OK_P1_52AA_M;
cr->cnt_l_crc_ok = CNT_L_CRC_OK_52AA;
cr->cnt_l_crc_ok_m = CNT_L_CRC_OK_52AA_M;
cr->cnt_ht_crc_ok = CNT_HT_CRC_OK_52AA;
cr->cnt_ht_crc_ok_m = CNT_HT_CRC_OK_52AA_M;
cr->cnt_vht_crc_ok = CNT_VHT_CRC_OK_52AA;
cr->cnt_vht_crc_ok_m = CNT_VHT_CRC_OK_52AA_M;
cr->cnt_he_crc_ok = CNT_HE_CRC_OK_52AA;
cr->cnt_he_crc_ok_m = CNT_HE_CRC_OK_52AA_M;
cr->cnt_cck_crc32fail_p0 = CNT_CCK_CRC32FAIL_P0_52AA;
cr->cnt_cck_crc32fail_p0_m = CNT_CCK_CRC32FAIL_P0_52AA_M;
cr->cnt_cck_crc32fail_p1 = CNT_CCK_CRC32FAIL_P1_52AA;
cr->cnt_cck_crc32fail_p1_m = CNT_CCK_CRC32FAIL_P1_52AA_M;
cr->cnt_l_crc_err = CNT_L_CRC_ERR_52AA;
cr->cnt_l_crc_err_m = CNT_L_CRC_ERR_52AA_M;
cr->cnt_ht_crc_err = CNT_HT_CRC_ERR_52AA;
cr->cnt_ht_crc_err_m = CNT_HT_CRC_ERR_52AA_M;
cr->cnt_vht_crc_err = CNT_VHT_CRC_ERR_52AA;
cr->cnt_vht_crc_err_m = CNT_VHT_CRC_ERR_52AA_M;
cr->cnt_he_crc_err = CNT_HE_CRC_ERR_52AA;
cr->cnt_he_crc_err_m = CNT_HE_CRC_ERR_52AA_M;
cr->rst_all_cnt = RST_ALL_CNT_52AA;
cr->rst_all_cnt_m = RST_ALL_CNT_52AA_M;
cr->phy_sts_bitmap_he_mu = PHY_STS_BITMAP_HE_MU_52AA;
cr->phy_sts_bitmap_he_mu_m = PHY_STS_BITMAP_HE_MU_52AA_M;
cr->phy_sts_bitmap_vht_mu = PHY_STS_BITMAP_VHT_MU_52AA;
cr->phy_sts_bitmap_vht_mu_m = PHY_STS_BITMAP_VHT_MU_52AA_M;
cr->phy_sts_bitmap_cck = PHY_STS_BITMAP_CCK_52AA;
cr->phy_sts_bitmap_cck_m = PHY_STS_BITMAP_CCK_52AA_M;
cr->phy_sts_bitmap_legacy = PHY_STS_BITMAP_LEGACY_52AA;
cr->phy_sts_bitmap_legacy_m = PHY_STS_BITMAP_LEGACY_52AA_M;
cr->phy_sts_bitmap_ht = PHY_STS_BITMAP_HT_52AA;
cr->phy_sts_bitmap_ht_m = PHY_STS_BITMAP_HT_52AA_M;
cr->phy_sts_bitmap_vht = PHY_STS_BITMAP_VHT_52AA;
cr->phy_sts_bitmap_vht_m = PHY_STS_BITMAP_VHT_52AA_M;
cr->phy_sts_bitmap_he = PHY_STS_BITMAP_HE_52AA;
cr->phy_sts_bitmap_he_m = PHY_STS_BITMAP_HE_52AA_M;
cr->rpt_tone_evm_idx = RPT_TONE_EVM_IDX_52AA;
cr->rpt_tone_evm_idx_m = RPT_TONE_EVM_IDX_52AA_M;
cr->dbg_port_ref_clk_en = DBG_PORT_REF_CLK_EN_52AA;
cr->dbg_port_ref_clk_en_m = DBG_PORT_REF_CLK_EN_52AA_M;
cr->dbg_port_en = DBG_PORT_EN_52AA;
cr->dbg_port_en_m = DBG_PORT_EN_52AA_M;
cr->dbg_port_ip_sel = DBG_PORT_IP_SEL_52AA;
cr->dbg_port_ip_sel_m = DBG_PORT_IP_SEL_52AA_M;
cr->dbg_port_sel = DBG_PORT_SEL_52AA;
cr->dbg_port_sel_m = DBG_PORT_SEL_52AA_M;
cr->dbg32_d = DBG32_D_52AA;
cr->dbg32_d_m = DBG32_D_52AA_M;
cr->phy_sts_bitmap_trigbase = PHY_STS_BITMAP_TRIGBASE_52AA;
cr->phy_sts_bitmap_trigbase_m = PHY_STS_BITMAP_TRIGBASE_52AA_M;
cr->sts_keeper_en = STS_KEEPER_EN_52AA;
cr->sts_keeper_en_m = STS_KEEPER_EN_52AA_M;
cr->sts_keeper_trig_cond = STS_KEEPER_TRIG_COND_52AA;
cr->sts_keeper_trig_cond_m = STS_KEEPER_TRIG_COND_52AA_M;
cr->sts_dbg_sel = STS_DBG_SEL_52AA;
cr->sts_dbg_sel_m = STS_DBG_SEL_52AA_M;
cr->sts_keeper_read = STS_KEEPER_READ_52AA;
cr->sts_keeper_read_m = STS_KEEPER_READ_52AA_M;
cr->sts_keeper_addr = STS_KEEPER_ADDR_52AA;
cr->sts_keeper_addr_m = STS_KEEPER_ADDR_52AA_M;
cr->sts_keeper_data = STS_KEEPER_DATA_52AA;
cr->sts_keeper_data_m = STS_KEEPER_DATA_52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->cnt_ccktxon = CNT_CCKTXON_A;
cr->cnt_ccktxon_m = CNT_CCKTXON_A_M;
cr->cnt_ofdmtxon = CNT_OFDMTXON_A;
cr->cnt_ofdmtxon_m = CNT_OFDMTXON_A_M;
cr->cnt_cck_crc32ok_p0 = CNT_CCK_CRC32OK_P0_A;
cr->cnt_cck_crc32ok_p0_m = CNT_CCK_CRC32OK_P0_A_M;
cr->cnt_cck_crc32ok_p1 = CNT_CCK_CRC32OK_P1_A;
cr->cnt_cck_crc32ok_p1_m = CNT_CCK_CRC32OK_P1_A_M;
cr->cnt_l_crc_ok = CNT_L_CRC_OK_A;
cr->cnt_l_crc_ok_m = CNT_L_CRC_OK_A_M;
cr->cnt_ht_crc_ok = CNT_HT_CRC_OK_A;
cr->cnt_ht_crc_ok_m = CNT_HT_CRC_OK_A_M;
cr->cnt_vht_crc_ok = CNT_VHT_CRC_OK_A;
cr->cnt_vht_crc_ok_m = CNT_VHT_CRC_OK_A_M;
cr->cnt_he_crc_ok = CNT_HE_CRC_OK_A;
cr->cnt_he_crc_ok_m = CNT_HE_CRC_OK_A_M;
cr->cnt_cck_crc32fail_p0 = CNT_CCK_CRC32FAIL_P0_A;
cr->cnt_cck_crc32fail_p0_m = CNT_CCK_CRC32FAIL_P0_A_M;
cr->cnt_cck_crc32fail_p1 = CNT_CCK_CRC32FAIL_P1_A;
cr->cnt_cck_crc32fail_p1_m = CNT_CCK_CRC32FAIL_P1_A_M;
cr->cnt_l_crc_err = CNT_L_CRC_ERR_A;
cr->cnt_l_crc_err_m = CNT_L_CRC_ERR_A_M;
cr->cnt_ht_crc_err = CNT_HT_CRC_ERR_A;
cr->cnt_ht_crc_err_m = CNT_HT_CRC_ERR_A_M;
cr->cnt_vht_crc_err = CNT_VHT_CRC_ERR_A;
cr->cnt_vht_crc_err_m = CNT_VHT_CRC_ERR_A_M;
cr->cnt_he_crc_err = CNT_HE_CRC_ERR_A;
cr->cnt_he_crc_err_m = CNT_HE_CRC_ERR_A_M;
cr->rst_all_cnt = RST_ALL_CNT_A;
cr->rst_all_cnt_m = RST_ALL_CNT_A_M;
cr->phy_sts_bitmap_he_mu = PHY_STS_BITMAP_HE_MU_A;
cr->phy_sts_bitmap_he_mu_m = PHY_STS_BITMAP_HE_MU_A_M;
cr->phy_sts_bitmap_vht_mu = PHY_STS_BITMAP_VHT_MU_A;
cr->phy_sts_bitmap_vht_mu_m = PHY_STS_BITMAP_VHT_MU_A_M;
cr->phy_sts_bitmap_cck = PHY_STS_BITMAP_CCK_A;
cr->phy_sts_bitmap_cck_m = PHY_STS_BITMAP_CCK_A_M;
cr->phy_sts_bitmap_legacy = PHY_STS_BITMAP_LEGACY_A;
cr->phy_sts_bitmap_legacy_m = PHY_STS_BITMAP_LEGACY_A_M;
cr->phy_sts_bitmap_ht = PHY_STS_BITMAP_HT_A;
cr->phy_sts_bitmap_ht_m = PHY_STS_BITMAP_HT_A_M;
cr->phy_sts_bitmap_vht = PHY_STS_BITMAP_VHT_A;
cr->phy_sts_bitmap_vht_m = PHY_STS_BITMAP_VHT_A_M;
cr->phy_sts_bitmap_he = PHY_STS_BITMAP_HE_A;
cr->phy_sts_bitmap_he_m = PHY_STS_BITMAP_HE_A_M;
cr->rpt_tone_evm_idx = RPT_TONE_EVM_IDX_A;
cr->rpt_tone_evm_idx_m = RPT_TONE_EVM_IDX_A_M;
cr->dbg_port_ref_clk_en = DBG_PORT_REF_CLK_EN_A;
cr->dbg_port_ref_clk_en_m = DBG_PORT_REF_CLK_EN_A_M;
cr->dbg_port_en = DBG_PORT_EN_A;
cr->dbg_port_en_m = DBG_PORT_EN_A_M;
cr->dbg_port_ip_sel = DBG_PORT_IP_SEL_A;
cr->dbg_port_ip_sel_m = DBG_PORT_IP_SEL_A_M;
cr->dbg_port_sel = DBG_PORT_SEL_A;
cr->dbg_port_sel_m = DBG_PORT_SEL_A_M;
cr->dbg32_d = DBG32_D_A;
cr->dbg32_d_m = DBG32_D_A_M;
cr->phy_sts_bitmap_trigbase = PHY_STS_BITMAP_TRIGBASE_A;
cr->phy_sts_bitmap_trigbase_m = PHY_STS_BITMAP_TRIGBASE_A_M;
cr->sts_keeper_en = STS_KEEPER_EN_A;
cr->sts_keeper_en_m = STS_KEEPER_EN_A_M;
cr->sts_keeper_trig_cond = STS_KEEPER_TRIG_COND_A;
cr->sts_keeper_trig_cond_m = STS_KEEPER_TRIG_COND_A_M;
cr->sts_dbg_sel = STS_DBG_SEL_A;
cr->sts_dbg_sel_m = STS_DBG_SEL_A_M;
cr->sts_keeper_read = STS_KEEPER_READ_A;
cr->sts_keeper_read_m = STS_KEEPER_READ_A_M;
cr->sts_keeper_addr = STS_KEEPER_ADDR_A;
cr->sts_keeper_addr_m = STS_KEEPER_ADDR_A_M;
cr->sts_keeper_data = STS_KEEPER_DATA_A;
cr->sts_keeper_data_m = STS_KEEPER_DATA_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->cnt_ccktxon = CNT_CCKTXON_C;
cr->cnt_ccktxon_m = CNT_CCKTXON_C_M;
cr->cnt_ofdmtxon = CNT_OFDMTXON_C;
cr->cnt_ofdmtxon_m = CNT_OFDMTXON_C_M;
cr->cnt_cck_crc32ok_p0 = CNT_CCK_CRC32OK_P0_C;
cr->cnt_cck_crc32ok_p0_m = CNT_CCK_CRC32OK_P0_C_M;
cr->cnt_cck_crc32ok_p1 = CNT_CCK_CRC32OK_P1_C;
cr->cnt_cck_crc32ok_p1_m = CNT_CCK_CRC32OK_P1_C_M;
cr->cnt_l_crc_ok = CNT_L_CRC_OK_C;
cr->cnt_l_crc_ok_m = CNT_L_CRC_OK_C_M;
cr->cnt_ht_crc_ok = CNT_HT_CRC_OK_C;
cr->cnt_ht_crc_ok_m = CNT_HT_CRC_OK_C_M;
cr->cnt_vht_crc_ok = CNT_VHT_CRC_OK_C;
cr->cnt_vht_crc_ok_m = CNT_VHT_CRC_OK_C_M;
cr->cnt_he_crc_ok = CNT_HE_CRC_OK_C;
cr->cnt_he_crc_ok_m = CNT_HE_CRC_OK_C_M;
cr->cnt_cck_crc32fail_p0 = CNT_CCK_CRC32FAIL_P0_C;
cr->cnt_cck_crc32fail_p0_m = CNT_CCK_CRC32FAIL_P0_C_M;
cr->cnt_cck_crc32fail_p1 = CNT_CCK_CRC32FAIL_P1_C;
cr->cnt_cck_crc32fail_p1_m = CNT_CCK_CRC32FAIL_P1_C_M;
cr->cnt_l_crc_err = CNT_L_CRC_ERR_C;
cr->cnt_l_crc_err_m = CNT_L_CRC_ERR_C_M;
cr->cnt_ht_crc_err = CNT_HT_CRC_ERR_C;
cr->cnt_ht_crc_err_m = CNT_HT_CRC_ERR_C_M;
cr->cnt_vht_crc_err = CNT_VHT_CRC_ERR_C;
cr->cnt_vht_crc_err_m = CNT_VHT_CRC_ERR_C_M;
cr->cnt_he_crc_err = CNT_HE_CRC_ERR_C;
cr->cnt_he_crc_err_m = CNT_HE_CRC_ERR_C_M;
cr->rst_all_cnt = RST_ALL_CNT_C;
cr->rst_all_cnt_m = RST_ALL_CNT_C_M;
cr->phy_sts_bitmap_he_mu = PHY_STS_BITMAP_HE_MU_C;
cr->phy_sts_bitmap_he_mu_m = PHY_STS_BITMAP_HE_MU_C_M;
cr->phy_sts_bitmap_vht_mu = PHY_STS_BITMAP_VHT_MU_C;
cr->phy_sts_bitmap_vht_mu_m = PHY_STS_BITMAP_VHT_MU_C_M;
cr->phy_sts_bitmap_cck = PHY_STS_BITMAP_CCK_C;
cr->phy_sts_bitmap_cck_m = PHY_STS_BITMAP_CCK_C_M;
cr->phy_sts_bitmap_legacy = PHY_STS_BITMAP_LEGACY_C;
cr->phy_sts_bitmap_legacy_m = PHY_STS_BITMAP_LEGACY_C_M;
cr->phy_sts_bitmap_ht = PHY_STS_BITMAP_HT_C;
cr->phy_sts_bitmap_ht_m = PHY_STS_BITMAP_HT_C_M;
cr->phy_sts_bitmap_vht = PHY_STS_BITMAP_VHT_C;
cr->phy_sts_bitmap_vht_m = PHY_STS_BITMAP_VHT_C_M;
cr->phy_sts_bitmap_he = PHY_STS_BITMAP_HE_C;
cr->phy_sts_bitmap_he_m = PHY_STS_BITMAP_HE_C_M;
cr->rpt_tone_evm_idx = RPT_TONE_EVM_IDX_C;
cr->rpt_tone_evm_idx_m = RPT_TONE_EVM_IDX_C_M;
cr->dbg_port_ref_clk_en = DBG_PORT_REF_CLK_EN_C;
cr->dbg_port_ref_clk_en_m = DBG_PORT_REF_CLK_EN_C_M;
cr->dbg_port_en = DBG_PORT_EN_C;
cr->dbg_port_en_m = DBG_PORT_EN_C_M;
cr->dbg_port_ip_sel = DBG_PORT_IP_SEL_C;
cr->dbg_port_ip_sel_m = DBG_PORT_IP_SEL_C_M;
cr->dbg_port_sel = DBG_PORT_SEL_C;
cr->dbg_port_sel_m = DBG_PORT_SEL_C_M;
cr->dbg32_d = DBG32_D_C;
cr->dbg32_d_m = DBG32_D_C_M;
cr->phy_sts_bitmap_trigbase = PHY_STS_BITMAP_TRIGBASE_C;
cr->phy_sts_bitmap_trigbase_m = PHY_STS_BITMAP_TRIGBASE_C_M;
cr->sts_keeper_en = STS_KEEPER_EN_C;
cr->sts_keeper_en_m = STS_KEEPER_EN_C_M;
cr->sts_keeper_trig_cond = STS_KEEPER_TRIG_COND_C;
cr->sts_keeper_trig_cond_m = STS_KEEPER_TRIG_COND_C_M;
cr->sts_dbg_sel = STS_DBG_SEL_C;
cr->sts_dbg_sel_m = STS_DBG_SEL_C_M;
cr->sts_keeper_read = STS_KEEPER_READ_C;
cr->sts_keeper_read_m = STS_KEEPER_READ_C_M;
cr->sts_keeper_addr = STS_KEEPER_ADDR_C;
cr->sts_keeper_addr_m = STS_KEEPER_ADDR_C_M;
cr->sts_keeper_data = STS_KEEPER_DATA_C;
cr->sts_keeper_data_m = STS_KEEPER_DATA_C_M;
cr->pw_dbm_rx0 = P0_L_TOT_PW_DBM_RX0_C;
cr->pw_dbm_rx0_m = P0_L_TOT_PW_DBM_RX0_C_M;
cr->sts_user_sel = STS_USER_SEL_C;
cr->sts_user_sel_m = STS_USER_SEL_C_M;
break;
#endif
default:
break;
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_mp.c
|
C
|
agpl-3.0
| 33,280
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_MP_EX_H__
#define __HALBB_MP_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
#define MAX_USER_NUM 4
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_rpt_cr_info {
u32 cnt_ccktxon;
u32 cnt_ccktxon_m;
u32 cnt_ofdmtxon;
u32 cnt_ofdmtxon_m;
u32 cnt_cck_crc32ok_p0;
u32 cnt_cck_crc32ok_p0_m;
u32 cnt_cck_crc32ok_p1;
u32 cnt_cck_crc32ok_p1_m;
u32 cnt_l_crc_ok;
u32 cnt_l_crc_ok_m;
u32 cnt_ht_crc_ok;
u32 cnt_ht_crc_ok_m;
u32 cnt_vht_crc_ok;
u32 cnt_vht_crc_ok_m;
u32 cnt_he_crc_ok;
u32 cnt_he_crc_ok_m;
u32 cnt_cck_crc32fail_p0;
u32 cnt_cck_crc32fail_p0_m;
u32 cnt_cck_crc32fail_p1;
u32 cnt_cck_crc32fail_p1_m;
u32 cnt_l_crc_err;
u32 cnt_l_crc_err_m;
u32 cnt_ht_crc_err;
u32 cnt_ht_crc_err_m;
u32 cnt_vht_crc_err;
u32 cnt_vht_crc_err_m;
u32 cnt_he_crc_err;
u32 cnt_he_crc_err_m;
u32 rst_all_cnt;
u32 rst_all_cnt_m;
u32 phy_sts_bitmap_he_mu;
u32 phy_sts_bitmap_he_mu_m;
u32 phy_sts_bitmap_vht_mu;
u32 phy_sts_bitmap_vht_mu_m;
u32 phy_sts_bitmap_cck;
u32 phy_sts_bitmap_cck_m;
u32 phy_sts_bitmap_legacy;
u32 phy_sts_bitmap_legacy_m;
u32 phy_sts_bitmap_ht;
u32 phy_sts_bitmap_ht_m;
u32 phy_sts_bitmap_vht;
u32 phy_sts_bitmap_vht_m;
u32 phy_sts_bitmap_he;
u32 phy_sts_bitmap_he_m;
u32 rpt_tone_evm_idx;
u32 rpt_tone_evm_idx_m;
u32 dbg_port_ref_clk_en;
u32 dbg_port_ref_clk_en_m;
u32 dbg_port_en;
u32 dbg_port_en_m;
u32 dbg_port_ip_sel;
u32 dbg_port_ip_sel_m;
u32 dbg_port_sel;
u32 dbg_port_sel_m;
u32 dbg32_d;
u32 dbg32_d_m;
u32 phy_sts_bitmap_trigbase;
u32 phy_sts_bitmap_trigbase_m;
u32 sts_keeper_en;
u32 sts_keeper_en_m;
u32 sts_keeper_trig_cond;
u32 sts_keeper_trig_cond_m;
u32 sts_dbg_sel;
u32 sts_dbg_sel_m;
u32 sts_keeper_read;
u32 sts_keeper_read_m;
u32 sts_keeper_addr;
u32 sts_keeper_addr_m;
u32 sts_keeper_data;
u32 sts_keeper_data_m;
u32 pw_dbm_rx0;
u32 pw_dbm_rx0_m;
u32 path0_rssi_at_agc_rdy;
u32 path0_rssi_at_agc_rdy_m;
u32 path1_rssi_at_agc_rdy;
u32 path1_rssi_at_agc_rdy_m;
u32 sts_user_sel;
u32 sts_user_sel_m;
};
struct bb_rpt_info {
struct bb_rpt_cr_info bb_rpt_cr_i;
};
struct rxevm_usr {
u8 rxevm_ss_0;
u8 rxevm_ss_1;
u8 rxevm_ss_2;
u8 rxevm_ss_3;
};
struct rxevm_info {
struct rxevm_usr rxevm_user[MAX_USER_NUM];
bool rxevm_valid;
};
struct rxevm_physts {
// Seg0/1
struct rxevm_info rxevm_seg[2];
};
struct rssi_i {
s32 rssi[4];
};
struct rssi_physts {
// Seg0/1
struct rssi_i rssi_seg[2];
};
struct mp_physts_rslt_0 {
u8 rx_path_en_cck;
u8 cfo_avg_cck;
u8 evm_avg_cck;
u8 avg_idle_noise_pwr_cck;
u8 pop_idx_cck;
};
struct mp_physts_rslt_1 {
u8 rx_path_en;
s16 cfo_avg; /*S(12,2), -512~+511.75 kHz*/
u8 evm_max;
u8 evm_min;
u8 snr_avg;
u8 cn_avg;
u8 avg_idle_noise_pwr;
u8 pop_idx;
u8 rxsc;
u8 ch_idx;
enum channel_width bw_idx;
bool is_su; /*if (not MU && not OFDMA), is_su = 1*/
bool is_ldpc;
bool is_ndp;
bool is_stbc;
bool grant_bt;
bool is_awgn;
bool is_bf;
};
struct mp_physts_rslt_basic {
struct mp_physts_rslt_0 mp_physts_rslt_basic_0_i;
struct mp_physts_rslt_1 mp_physts_rslt_basic_1_i;
};
struct bb_mp_psts {
u32 ie_bitmap;
struct mp_physts_rslt_basic mp_physts_rslt_basic_i;
struct mp_physts_rslt_0 mp_physts_rslt_0_i;
struct mp_physts_rslt_1 mp_physts_rslt_1_i;
};
struct halbb_mp {
/*Tx ok count, statistics used in Mass Production Test.*/
u64 tx_phy_ok_cnt;
/*Rx CRC32 ok/error count, statistics used in Mass Production Test.*/
u64 rx_phy_crc_ok_cnt;
u64 rx_phy_crc_err_cnt;
/*The Value of IO operation is depend of MptActType.*/
u32 io_ok_value;
u32 io_err_value;
};
/*@--------------------------[Prptotype]-------------------------------------*/
u16 halbb_mp_get_tx_ok(struct bb_info *bb, u32 rate_index,
enum phl_phy_idx phy_idx);
u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx);
u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_mp_reset_cnt(struct bb_info *bb);
u8 halbb_mp_get_rxevm(struct bb_info *bb, u8 user, u8 strm, bool rxevm_table);
struct rxevm_physts halbb_mp_get_rxevm_physts(struct bb_info *bb,
enum phl_phy_idx phy_idx);
//u16 halbb_mp_get_pwdb_diff(struct bb_info *bb, enum rf_path path);
u8 halbb_mp_get_rssi(struct bb_info *bb, enum rf_path path);
struct rssi_physts halbb_get_mp_rssi_physts(struct bb_info *bb, enum rf_path path, enum phl_phy_idx phy_idx);
void halbb_mp_get_psts(struct bb_info *bb , struct bb_mp_psts *bb_mp_physts);
void halbb_mp_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_mp_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_mp_ex.h
|
C
|
agpl-3.0
| 5,804
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_PHYSTS_PARSING_SUPPORT
static const u32 phy_sts_dbg[] = {
0x34006A8A,//HDR
0x00003632,
0x03020101,//IE-1
#if 0 //to save memory
0x8DF0CA04,
0x0b797f1e,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03020102,//IE-2
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x00000000,
0x00000000,
0x03020103,//IE-3
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x78787878,
0x78787878,
0x03020104,//IE-4
0x0706050f,
0x30201005,//IE-5
0x70605040,
0x03020106,//IE-6
0x07060504,
0x30201007,//IE-7
0x70605040,
0x02000088,//IE-8
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03002089,//IE-9
0x07060504,
0x0302008A,//IE-10
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x0302010B,//IE-11
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03020100,
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03020100,
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03020100,
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03020100,
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x13121110,
0x17161514,
0x1b1a1918,
0x1f1e1d1c,
0x03020100,
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x0002004c, //IE-12
0x87654321,
0x654321a9,
0x0000a987,
0x0002008D, //IE-13
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x654321a9,
0x0000a987,
0x030200ae, //IE-14
0x00000000,
0x71c50701,
0x1c71c71c,
0x010e0105,
0x05040302,
0x09080706,
0x0d0c0b0a,
0x0000000e,
0x00000000,
0x0002008F, //IE-15
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x654321a9,
0x0000a987,
0x00002071, //IE-17
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x03020112, //IE-18
0x07060504,
0x0b0a0908,
0x0f0e0d0c,
0x03002013, //IE-19
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x03012074, //IE-20
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x03012075, //IE-21
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x03010076, //IE-22
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x03020118, //IE-24
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x03020119, //IE-25
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x0302011a, //IE-26
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x0302011b, //IE-27
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x0302011c, //IE-28
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x87654321,
0x87654321,
0x0302011d, //IE-29
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x87654321,
0x87654321,
0x0302011e, //IE-30
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x87654321,
0x87654321,
0x0302011f, //IE-31
0x87654321,
0x654321a9,
0x0000a987,
0x0002004c,
0x87654321,
0x87654321,
0x87654321,
#endif
};
void halbb_physts_detail_dump_ie_11(struct bb_info *bb)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_11_info *psts_11 = &physts->bb_physts_rslt_11_i;
struct physts_ie_11_info *ie_11 = NULL;
struct physts_ie_11_pkt_info *pkt_info;
char *mode = NULL;
char *state = NULL;
u64 type = 0;
u32 type1 = 0, type2 = 0;
u8 i = 0, j = 0;
ie_11 = (struct physts_ie_11_info *)psts_11->ie_11_addr;
BB_TRACE("[11][PLCP_Hist][T=%04d] LSIG=0x%05X, SIGA1=0x%07X, SIGA2=0x%04X\n",
(ie_11->time_stamp_m << 8) | ie_11->time_stamp_l,
(ie_11->l_sig_m << 11) | (ie_11->l_sig_lm << 3) | ie_11->l_sig_l,
(ie_11->sig_a1_m1 << 18) | (ie_11->sig_a1_m2 << 10) | (ie_11->sig_a1_m3 << 2) | ie_11->sig_a1_l,
(ie_11->sig_a2_m << 8) | ie_11->sig_a2_l);
#if 0
BB_TRACE("*stamp=%d, r/tx_pkt_idx={%d, %d}\n",
(ie_11->time_stamp_m << 8) | (ie_11->time_stamp_l),
ie_11->rx_pkt_info_idx,
(ie_11->tx_pkt_info_idx_m << 1) | ie_11->tx_pkt_info_idx_l);
#endif
for (i = 0; i < IE11_PKT_INFO_LEN; i++) {
j = (ie_11->rx_pkt_info_idx + i) % IE11_PKT_INFO_LEN;
pkt_info = &ie_11->pkt_info_rx_i[j];
type = (pkt_info->info_type_4 << 31) | (pkt_info->info_type_3 << 23) |
(pkt_info->info_type_2 << 15) |(pkt_info->info_type_1 << 7) |
pkt_info->info_type_0;
if (pkt_info->pkt_format == 1) {
type1 = (u32)(type & 0xFFFFFF);
type2 = (u32)(type >> 23);
mode = " HT ";
} else if (pkt_info->pkt_format == 2) {
type1 = (u32)(type & 0xFFFFFF);
type2 = (u32)(type >> 23);
mode = "VHT ";
} else if (pkt_info->pkt_format == 3) {
type1 = (u32)(type & 0x3FFFFFF);
type2 = (u32)(type >> 25);
mode = " HE ";
} else {
type1 = (u32)type;
type2 = 0;
mode = "Lgcy";
}
if (pkt_info->state == 1) {
state = "CRC-ER";
} else if (pkt_info->state == 2) {
state = "Break ";
} else if (pkt_info->state == 3) {
state = "SS FAL";
} else {
state = "CRC-OK";
}
BB_TRACE(" *[R][%d][%s][%s][T=%04d] l_rate=%d, SIG1/2={0x%08x, 0x%08x}\n",
i, mode, state,
(pkt_info->time_stamp_m << 5) | pkt_info->time_stamp_l,
pkt_info->l_rate,
type1, type2);
}
BB_TRACE(" *\n");
for (i = 0; i < IE11_PKT_INFO_LEN; i++) {
j = (ie_11->rx_pkt_info_idx + i) % IE11_PKT_INFO_LEN;
pkt_info = &ie_11->pkt_info_tx_i[i];
type = (pkt_info->info_type_4 << 31) | (pkt_info->info_type_3 << 23) |
(pkt_info->info_type_2 << 15) |(pkt_info->info_type_1 << 7) |
pkt_info->info_type_0;
if (pkt_info->pkt_format == 1) {
type1 = (u32)(type & 0xFFFFFF);
type2 = (u32)(type >> 23);
mode = " HT ";
} else if (pkt_info->pkt_format == 2) {
type1 = (u32)(type & 0xFFFFFF);
type2 = (u32)(type >> 23);
mode = "VHT ";
} else if (pkt_info->pkt_format == 3) {
type1 = (u32)(type & 0x3FFFFFF);
type2 = (u32)(type >> 25);
mode = " HE ";
} else {
type1 = (u32)type;
type2 = 0;
mode = "Lgcy";
}
if (pkt_info->state == 1) {
state = "CRC-ER";
} else if (pkt_info->state == 2) {
state = "Break ";
} else if (pkt_info->state == 3) {
state = "SS FAL";
} else {
state = "CRC-OK";
}
BB_TRACE(" *[T][%d][%s][%s][T=%04d] l_rate=%d, SIG1/2={0x%08x, 0x%08x}\n",
i, mode, state,
(pkt_info->time_stamp_m << 5) | pkt_info->time_stamp_l,
pkt_info->l_rate,
type1, type2);
}
}
void halbb_physts_detail_dump_ie_4_7(struct bb_info *bb, enum bb_physts_ie_t ie)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_4_to_7_info *psts_r = NULL;
struct physts_ie_4_to_7_info *ie_4_7 = NULL;
char dbg_buf_1[HALBB_SNPRINT_SIZE_S], dbg_buf_2[HALBB_SNPRINT_SIZE_S], dbg_buf_3[HALBB_SNPRINT_SIZE_S];
if (ie < IE04_CMN_EXT_PATH_A)
return;
BB_TRACE("[%02d][Extend path-%c]\n", ie, ('A' + (u8)(ie - IE04_CMN_EXT_PATH_A)));
if (ie == IE04_CMN_EXT_PATH_A)
psts_r = &physts->bb_physts_rslt_4_i;
else if (ie == IE05_CMN_EXT_PATH_B)
psts_r = &physts->bb_physts_rslt_5_i;
else if (ie == IE06_CMN_EXT_PATH_C)
psts_r = &physts->bb_physts_rslt_6_i;
else if (ie == IE07_CMN_EXT_PATH_D)
psts_r = &physts->bb_physts_rslt_7_i;
else
return;
ie_4_7 = (struct physts_ie_4_to_7_info *)psts_r->ie_04_07_addr;
BB_TRACE(" *ie_hdr=%d\n", ie_4_7->ie_hdr);
halbb_print_sign_frac_digit(bb, (s8)ie_4_7->sig_val_y, 8, 2, dbg_buf_1, HALBB_SNPRINT_SIZE_S);
halbb_print_sign_frac_digit(bb, (s8)ie_4_7->td_ant_weight, 8, 6, dbg_buf_3, HALBB_SNPRINT_SIZE_S);
BB_TRACE(" *ant=%d, sig_val=%s, rf_gain_idx=%d, snr_lgy=%d, evm_ss_y=%d.%02d, ant_weight=%s\n",
ie_4_7->ant_idx, dbg_buf_1, ie_4_7->rf_gain_idx,
ie_4_7->snr_lgy, ie_4_7->evm_ss_y >> 2,
halbb_show_fraction_num(ie_4_7->evm_ss_y & 0x3, 2), dbg_buf_3);
halbb_print_sign_frac_digit(bb, (s8)ie_4_7->dc_est_re, 8, 7, dbg_buf_1, HALBB_SNPRINT_SIZE_S);
halbb_print_sign_frac_digit(bb, (s8)ie_4_7->dc_est_im, 8, 7, dbg_buf_2, HALBB_SNPRINT_SIZE_S);
BB_TRACE(" *dc_est_re/im={%s, %s}, tia_gain=%d, tia_shrink=%d\n",
dbg_buf_1, dbg_buf_2,
ie_4_7->rf_tia_gain_idx, ie_4_7->tia_shrink_indicator);
}
void halbb_physts_detail_dump(struct bb_info *bb, u32 bitmap, u32 bitmap_mask)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i;
struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i;
struct physts_ie_1_info *ie_1 = NULL;
struct bb_physts_rslt_2_info *psts_2 = &physts->bb_physts_rslt_2_i;
struct bb_physts_rslt_8_info *psts_8 = &physts->bb_physts_rslt_8_i;
struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i;
struct bb_physts_rslt_12_info *psts_12 = &physts->bb_physts_rslt_12_i;
struct bb_physts_rslt_13_info *psts_13 = &physts->bb_physts_rslt_13_i;
struct bb_physts_rslt_14_info *psts_14 = &physts->bb_physts_rslt_14_i;
struct bb_physts_rslt_15_info *psts_15 = &physts->bb_physts_rslt_15_i;
struct bb_physts_rslt_17_info *psts_17 = &physts->bb_physts_rslt_17_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
char *tmp_char = NULL;
u8 i;
if (!physts->is_valid) {
BB_TRACE("physts invalid\n");
return;
}
if (psts_h->ie_map_type > 16)
return;
if (bitmap_mask != 0xffffffff) {
BB_TRACE("user_def_mask=0x%08x\n", bitmap_mask);
}
BB_TRACE("[Hdr] rssi={%d}{%d,%d,%d,%d}\n",
TRANS_2_RSSI(psts_h->rssi_avg),
TRANS_2_RSSI(psts_h->rssi[0]),
TRANS_2_RSSI(psts_h->rssi[1]),
TRANS_2_RSSI(psts_h->rssi[2]),
TRANS_2_RSSI(psts_h->rssi[3]));
if (bitmap == 0) {
BB_TRACE("Hdr only, empty IE\n");
return;
}
if (bitmap & BIT(IE00_CMN_CCK)) {
BB_TRACE("[00][CCK] path_en=0x%x, rpl=%d.%01d, cfo=%s%d.%02d kHz, evm=%d.%02d\n",
psts_0->rx_path_en_cck,
psts_0->rpl >> 2,
halbb_show_fraction_num(psts_0->rpl & 0x3, 2),
((psts_0->cfo_avg_cck & BIT15)!= 0) ? "-": " ",
ABS_16(psts_0->cfo_avg_cck) >> 2,
halbb_show_fraction_num((u16)ABS_16(psts_0->cfo_avg_cck) & 0x3, 2),
psts_0->evm_avg_cck >> 2,
halbb_show_fraction_num(psts_0->evm_avg_cck & 0x3, 2));
BB_TRACE("[00][CCK] idle_noise=%d.%01d, pop idx=%d\n",
psts_0->avg_idle_noise_pwr_cck >> 1,
halbb_show_fraction_num(psts_0->avg_idle_noise_pwr_cck & 0x1, 1),
psts_0->pop_idx_cck);
}
if (bitmap & BIT(IE01_CMN_OFDM)) {
ie_1 = (struct physts_ie_1_info *)physts->bb_physts_rslt_1_i.ie_01_addr;
BB_TRACE("[01][OFDM] path_en=0x%x, rpl=%d.%01d, cfo_fd=%s%d.%02d kHz, cfo_pab=%s%d.%02d kHz, Max&Min evm={%d.%02d,%d.%02d}, avg SNR=%d , CN=%d.%01d\n",
psts_1->rx_path_en,
psts_1->rpl_fd >> 1,
halbb_show_fraction_num(psts_1->rpl_fd & 0x1, 1),
((psts_1->cfo_avg & BIT15) != 0) ? "-": " ",
ABS_16(psts_1->cfo_avg) >> 2,
halbb_show_fraction_num((u16)ABS_16(psts_1->cfo_avg) & 0x3, 2),
((psts_1->cfo_pab_avg & BIT15) != 0) ? "-": " ",
ABS_16(psts_1->cfo_pab_avg) >> 2,
halbb_show_fraction_num((u16)ABS_16(psts_1->cfo_pab_avg) & 0x3, 2),
psts_1->evm_max >> 2,
halbb_show_fraction_num(psts_1->evm_max & 0x3, 2),
psts_1->evm_min >> 2,
halbb_show_fraction_num(psts_1->evm_min & 0x3, 2),
psts_1->snr_avg,
psts_1->cn_avg >> 1,
halbb_show_fraction_num(psts_1->cn_avg & 0x1, 1));
BB_TRACE("[01][OFDM] idle_noise=%d, pop idx=%d, ch=%d, bw=%d, rxsc=%d, su=%d, ldpc=%d, stbc=%d, gnt_bt=%d, awgn=%d, bf=%d\n",
psts_1->avg_idle_noise_pwr >> 1, psts_1->pop_idx,
psts_1->ch_idx, psts_1->bw_idx, psts_1->rxsc,
psts_1->is_su, psts_1->is_ldpc, psts_1->is_stbc,
psts_1->grant_bt, psts_1->is_awgn, psts_1->is_bf);
BB_TRACE("[01][OFDM] pwr_to_cca=%d ns, cca_to_agc=%d ns, cca_to_sbd=%dns",
(BYTE_2_WORD((u32)ie_1->pwr_to_cca_m, (u32)ie_1->pwr_to_cca_l) * 25),
ie_1->cca_to_agc * 25, ie_1->cca_to_sbd * 25);
}
if (bitmap & BIT(IE02_CMN_EXT_AX)) {
BB_TRACE("[02][HE] max_nsts=%d, ltf_type=%d, gi=%d, c_cfo_i/q={%s%d.%07d, %s%d.%07d}, f_cfo_i/q={%s%d.%07d, %s%d.%07d}\n",
psts_2->max_nsts, psts_2->ltf_type, psts_2->gi,
((psts_2->c_cfo_i & BIT31)!= 0) ? "-": " ",
((u32)ABS_32(psts_2->c_cfo_i) >> 7),
halbb_show_fraction_num((u32)ABS_32(psts_2->c_cfo_i) & 0x7f, 7),
((psts_2->c_cfo_q & BIT31)!= 0) ? "-": " ",
((u32)ABS_32(psts_2->c_cfo_q) >> 7),
halbb_show_fraction_num((u32)ABS_32(psts_2->c_cfo_q) & 0x7f, 7),
((psts_2->f_cfo_i & BIT31)!= 0) ? "-": " ",
((u32)ABS_32(psts_2->f_cfo_i) >> 7),
halbb_show_fraction_num((u32)ABS_32(psts_2->f_cfo_i) & 0x7f, 7),
((psts_2->f_cfo_q & BIT31)!= 0) ? "-": " ",
((u32)ABS_32(psts_2->f_cfo_q) >> 7),
halbb_show_fraction_num((u32)ABS_32(psts_2->f_cfo_q) & 0x7f, 7));
BB_TRACE("[02][HE] rx_info_1=%d, rx_state_feq=%d, est_cmped_phase=0.%08d, pkt_ext=%d, n_ltf=%d, n_sym=%d\n",
psts_2->rx_info_1, psts_2->rx_state_feq,
halbb_show_fraction_num(psts_2->est_cmped_phase & 0xff, 8),
psts_2->pkt_extension, psts_2->n_ltf, psts_2->n_sym);
}
if (bitmap & BIT(IE03_CMN_EXT_SEG_1)) {
/* suspended due to low priority */
}
if (bitmap & BIT(IE04_CMN_EXT_PATH_A))
halbb_physts_detail_dump_ie_4_7(bb, IE04_CMN_EXT_PATH_A);
if (bitmap & BIT(IE05_CMN_EXT_PATH_B))
halbb_physts_detail_dump_ie_4_7(bb, IE05_CMN_EXT_PATH_B);
if (bitmap & BIT(IE06_CMN_EXT_PATH_C))
halbb_physts_detail_dump_ie_4_7(bb, IE06_CMN_EXT_PATH_C);
if (bitmap & BIT(IE07_CMN_EXT_PATH_D))
halbb_physts_detail_dump_ie_4_7(bb, IE07_CMN_EXT_PATH_D);
if (bitmap & BIT(IE08_FTR_CH)) {
BB_TRACE("[08][ch_info] rxsc=%d, n_rx=%d, sts=%d, EVM{1,2}={%d.%02d, %d.%02d}, avg_noise_pw=%d.%01d\n",
psts_8->rxsc, psts_8->n_rx, psts_8->n_sts,
psts_8->evm_1_sts >> 2,
halbb_show_fraction_num(psts_8->evm_1_sts & 0x3, 2),
psts_8->evm_2_sts >> 2,
halbb_show_fraction_num(psts_8->evm_2_sts & 0x3, 2),
(psts_8->avg_idle_noise_pwr >> 1),
halbb_show_fraction_num(psts_8->avg_idle_noise_pwr & 0x1, 1));
}
if (bitmap & BIT(IE09_FTR_PLCP_0)) {
if (cmn_rpt->bb_rate_i.mode == BB_HE_MODE)
tmp_char = "HE";
else if (cmn_rpt->bb_rate_i.mode == BB_VHT_MODE)
tmp_char = "VHT";
else if (cmn_rpt->bb_rate_i.mode == BB_HT_MODE)
tmp_char = "HT";
else
tmp_char = "Lgcy";
BB_TRACE("[09][PLCP] mode=%s LSIG=0x%06x, SIGA1=0x%08x, SIGA2=0x%08x\n",
tmp_char, psts_9->l_sig, psts_9->sig_a1, psts_9->sig_a2);
}
if (bitmap & BIT(IE11_FTR_PLCP_HISTOGRAM))
halbb_physts_detail_dump_ie_11(bb);
if (bitmap & BIT(IE12_MU_EIGEN_INFO)) {
for (i = 0; i < psts_12->n_user; i++) {
if (i >= MU_USER_MAX)
break;
BB_TRACE("[12][MU_eigen][U:%d] sig_val_ss[3:0]={%d,%d,%d,%d}, cn bad tone=%d, sig bad tone=%d\n",
i,
psts_12->bb_physts_uer_info[i].sig_val_ss3_seg_cr_user_i,
psts_12->bb_physts_uer_info[i].sig_val_ss2_seg_cr_user_i,
psts_12->bb_physts_uer_info[i].sig_val_ss1_seg_cr_user_i,
psts_12->bb_physts_uer_info[i].sig_val_ss0_seg_cr_user_i,
psts_12->bb_physts_uer_info[i].cn_bad_tone_cnt_seg_cr_user_i,
psts_12->bb_physts_uer_info[i].sig_bad_tone_cnt_seg_cr_user_i);
}
}
if (bitmap & BIT(IE13_DL_MU_DEF)) {
for (i = 0; i < psts_13->n_user; i++) {
if (i >= MU_USER_MAX)
break;
BB_TRACE("[13][HEMU][U:%d] avg_cn=%d.%01d, fec_type=%d, awgn=%d, bf=%d, dcm=%d, mu=%d\n",
i,
(psts_13->bb_physts_uer_info[i].avg_cn_seg_cr >> 1),
halbb_show_fraction_num(psts_13->bb_physts_uer_info[i].avg_cn_seg_cr & 0x1, 1),
psts_13->bb_physts_uer_info[i].fec_type,
psts_13->bb_physts_uer_info[i].is_awgn,
psts_13->bb_physts_uer_info[i].is_bf,
psts_13->bb_physts_uer_info[i].is_dcm,
psts_13->bb_physts_uer_info[i].is_mu_mimo);
BB_TRACE("[13][HEMU][U:%d] mcs=%d, sts=%d, sts_ru_total=%d, gi_ltf=%d, pilot_exist=%d, mu=%d\n",
i,
psts_13->bb_physts_uer_info[i].mcs,
psts_13->bb_physts_uer_info[i].n_sts,
psts_13->bb_physts_uer_info[i].n_sts_ru_total,
psts_13->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type,
psts_13->bb_physts_uer_info[i].pilot_exist,
psts_13->bb_physts_uer_info[i].is_mu_mimo);
BB_TRACE("[13][HEMU][U:%d] ru_aloc=%d, evm_segN_max/min={%d.%02d, %d.%02d}, snr=%s%d.%01d, start_sts=%d\n",
i,
psts_13->bb_physts_uer_info[i].ru_alloc,
psts_13->bb_physts_uer_info[i].rx_evm_max_seg_cr >> 2,
halbb_show_fraction_num(psts_13->bb_physts_uer_info[i].rx_evm_max_seg_cr & 0x3, 2),
psts_13->bb_physts_uer_info[i].rx_evm_min_seg_cr >> 2,
halbb_show_fraction_num(psts_13->bb_physts_uer_info[i].rx_evm_min_seg_cr & 0x3, 2),
((psts_13->bb_physts_uer_info[i].snr & BIT7)!= 0) ? "-": " ",
ABS_8(psts_13->bb_physts_uer_info[i].snr ) >> 1,
halbb_show_fraction_num((u8)ABS_8(psts_13->bb_physts_uer_info[i].snr ) & 0x1, 1),
psts_13->bb_physts_uer_info[i].start_sts);
}
BB_TRACE("[13][HEMU] n_not_sup_sta=%d\n", psts_13->n_not_sup_sta);
}
if (bitmap & BIT(IE14_TB_UL_CQI)) {
BB_TRACE("[14][TB_CQI] ndp_en=%d, n_user=%d\n",
psts_14->rxinfo_ndp_en, psts_14->n_user);
for (i = 0; i < psts_14->n_user; i++) {
if (i >= TB_USER_MAX)
break;
BB_TRACE("[14][TB_CQI][U:%d] cqi_bitmap_ul_tb=%d\n",
i,
psts_14->bb_physts_uer_info[i].cqi_bitmap_ul_tb);
}
}
if (bitmap & BIT(IE15_TB_UL_DEF)) {
BB_TRACE("[15][TB_AC_MU] n_user=%d\n", psts_15->n_user);
for (i = 0; i < psts_15->n_user; i++) {
if (i >= TB_USER_MAX)
break;
BB_TRACE("[15][TB_AC_MU][U:%d] avg_cn=%d.%01d, fec_type=%d, awgn=%d, bf=%d, dcm=%d, mu=%d\n",
i,
(psts_15->bb_physts_uer_info[i].avg_cn_seg_cr >> 1),
halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].avg_cn_seg_cr & 0x1, 1),
psts_15->bb_physts_uer_info[i].fec_type,
psts_15->bb_physts_uer_info[i].is_awgn,
psts_15->bb_physts_uer_info[i].is_bf,
psts_15->bb_physts_uer_info[i].is_dcm,
psts_15->bb_physts_uer_info[i].is_mu_mimo);
BB_TRACE("[15][TB_AC_MU][U:%d] mcs=%d, sts=%d, sts_ru_total=%d, gi_ltf=%d, pilot_exist=%d, mu=%d\n",
i,
psts_15->bb_physts_uer_info[i].mcs,
psts_15->bb_physts_uer_info[i].n_sts,
psts_15->bb_physts_uer_info[i].n_sts_ru_total,
psts_15->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type,
psts_15->bb_physts_uer_info[i].pilot_exist,
psts_15->bb_physts_uer_info[i].is_mu_mimo);
BB_TRACE("[15][TB_AC_MU][U:%d] ru_aloc=%d, evm_segN_max/min={%d.%02d, %d.%02d}, snr=%s%d.%02d, start_sts=%d\n",
i,
psts_15->bb_physts_uer_info[i].ru_alloc,
psts_15->bb_physts_uer_info[i].rx_evm_max_seg_cr >> 2,
halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].rx_evm_max_seg_cr & 0x3, 2),
(psts_15->bb_physts_uer_info[i].rx_evm_min_seg_cr >> 2),
halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].rx_evm_min_seg_cr & 0x3, 2),
((psts_15->bb_physts_uer_info[i].snr & BIT7)!= 0) ? "-": " ",
((u8)ABS_8(psts_15->bb_physts_uer_info[i].snr ) >> 1),
halbb_show_fraction_num((u8)ABS_8(psts_15->bb_physts_uer_info[i].snr ) & 0x1, 1),
(psts_15->bb_physts_uer_info[i].start_sts ));
BB_TRACE("[15][TB_AC_MU][U:%d] uid=%d, avg_cfo_seg0=%s%d.%02d, rssi_m_ul_tb=%d.%02d\n",
i, psts_15->bb_physts_uer_info[i].uid,
((psts_15->bb_physts_uer_info[i].avg_cfo_seg0 & BIT15)!= 0) ? "-": " ",
((u16)ABS_16(psts_15->bb_physts_uer_info[i].avg_cfo_seg0) >> 2),
halbb_show_fraction_num((u16)ABS_16(psts_15->bb_physts_uer_info[i].avg_cfo_seg0) & 0x3, 2),
(psts_15->bb_physts_uer_info[i].rssi_m_ul_tb >> 2),
halbb_show_fraction_num(psts_15->bb_physts_uer_info[i].rssi_m_ul_tb & 0x3, 2));
}
}
if (bitmap & BIT(IE17_TB_UL_CTRL)) {
BB_TRACE("[17][TB_UL_CTRL] n_user=%d\n", psts_17->n_user);
BB_TRACE("[17][TB_UL_CTRL][CMN] stbc_en=%d, ldpc_extra=%d, doppler_en=%d, midamle_mode=%d, gi_type=%d, ltf_type=%d\n",
psts_17->bb_physts_cmn_info.stbc_en ,
psts_17->bb_physts_cmn_info.ldpc_extra,
psts_17->bb_physts_cmn_info.doppler_en,
psts_17->bb_physts_cmn_info.midamle_mode,
psts_17->bb_physts_cmn_info.gi_type,
psts_17->bb_physts_cmn_info.ltf_type);
BB_TRACE("[17][TB_UL_CTRL][CMN] n_ltf=%d, n_sym=%d, pe_idx=%d, pre_fec_factor=%d, n_usr=%d, mumimo_ltf_mode_en=%d\n",
psts_17->bb_physts_cmn_info.n_ltf,
psts_17->bb_physts_cmn_info.n_sym,
psts_17->bb_physts_cmn_info.pe_idx,
psts_17->bb_physts_cmn_info.pre_fec_factor,
psts_17->bb_physts_cmn_info.n_usr,
psts_17->bb_physts_cmn_info.mumimo_ltf_mode_en);
BB_TRACE("[17][TB_UL_CTRL][CMN] ndp=%d, pri_exp_rssi_dbm=%d, dbw_idx=%d, rxtime=%d\n",
psts_17->bb_physts_cmn_info.ndp,
psts_17->bb_physts_cmn_info.pri_exp_rssi_dbm,
psts_17->bb_physts_cmn_info.dbw_idx,
psts_17->bb_physts_cmn_info.rxtime);
for (i = 0; i < psts_15->n_user; i++) {
if (i >= TB_USER_MAX)
break;
BB_TRACE("[17][TB_UL_CTRL][U:%d] u_id=%d, ru_alloc=%d, n_sts_ru_tot=%d, strt_sts=%d, n_sts=%d, fec_type=%d, mcs=%d, dcm_en=%d\n",
i,
psts_17->bb_physts_uer_info[i].u_id,
psts_17->bb_physts_uer_info[i].ru_alloc,
psts_17->bb_physts_uer_info[i].n_sts_ru_tot,
psts_17->bb_physts_uer_info[i].strt_sts,
psts_17->bb_physts_uer_info[i].n_sts,
psts_17->bb_physts_uer_info[i].fec_type,
psts_17->bb_physts_uer_info[i].mcs,
psts_17->bb_physts_uer_info[i].dcm_en);
}
}
}
void halbb_physts_ie_bitmap_set(struct bb_info *bb, u32 ie_page, u32 bitmap)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_cr_info *cr = &bb->bb_physts_i.bb_physts_cr_i;
if (ie_page >= PHYSTS_BITMAP_NUM)
return;
if (ie_page == 9) /* Bitmap 9 is rsvd */
return;
physts->bitmap_type[ie_page] = bitmap;
BB_DBG(bb, DBG_PHY_CONFIG, "Bitmap[%d] = 0x%x\n",
ie_page, physts->bitmap_type[ie_page]);
if (ie_page >= 10)
ie_page--;
if (bb->ic_type == BB_RTL8852A)
bitmap &= 0x337cff3f;
//halbb_set_reg(bb, cr->plcp_hist, cr->plcp_hist_m, (bitmap & BIT(11)) ? 1 : 0);
halbb_set_reg(bb, cr->bitmap_search_fail + (ie_page << 2), MASKDWORD, bitmap);
}
u32 halbb_physts_ie_bitmap_get(struct bb_info *bb, u32 ie_page)
{
struct bb_physts_cr_info *cr = &bb->bb_physts_i.bb_physts_cr_i;
if (ie_page >= PHYSTS_BITMAP_NUM)
return 0;
if (ie_page == 9) /* Bitmap 9 is rsvd */
return 0;
else if (ie_page >= 10)
ie_page--;
return halbb_get_reg(bb, cr->bitmap_search_fail + (ie_page << 2), MASKDWORD);
}
void halbb_physts_ie_bitmap_en(struct bb_info *bb, enum bb_physts_bitmap_t type,
enum bb_physts_ie_t ie, bool en)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
u32 bitmap_ori = physts->bitmap_type[type];
u32 bitmap = bitmap_ori & ~((u32)BIT(ie));
#if 0
BB_DBG(bb, DBG_IC_API, "Bitmap_ori[%d] = 0x%x\n",
type, bitmap_ori);
BB_DBG(bb, DBG_IC_API, "Bitmap_en[%d][Bit:%d]=%d\n",
type, ie, en);
#endif
if (en) {
if (bitmap_ori & (u32)BIT(ie))
return;
bitmap |= (u32)BIT(ie);
} else {
if (!(bitmap_ori & (u32)BIT(ie)))
return;
}
halbb_physts_ie_bitmap_set(bb, type, bitmap);
}
void halbb_physts_brk_fail_rpt_en(struct bb_info *bb, bool enable,
enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_physts_brk_fail_pkt_rpt_8852a_2(bb, enable, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_physts_td_time_rpt_en(struct bb_info *bb, bool en,
enum phl_phy_idx phy_idx)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i;
halbb_set_reg_cmn(bb, cr->period_cnt_en, BIT0, en, phy_idx); /*enable pwr_2_cca time report*/
}
void halbb_mod_rssi_by_path_en(struct bb_info *bb, u8 rx_path_en)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
u8 num_path_en = 0;
u8 valid_rssi_max = 0;
u8 i = 0;
for (i = 0; i < bb->num_rf_path; i++) {
if (!(rx_path_en & BIT(i))) {
psts_h->rssi[i] = 0;
continue;
}
num_path_en++;
if (psts_h->rssi[i] > valid_rssi_max)
valid_rssi_max = psts_h->rssi[i];
}
if (num_path_en < bb->num_rf_path)
psts_h->rssi_avg = valid_rssi_max;
}
u8 halbb_physts_ie_hdr(struct bb_info *bb,
u8 *addr,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
struct physts_hdr_info *physts_hdr = NULL;
/*---[Physts header parsing]------------------------------------------*/
physts_hdr = (struct physts_hdr_info *)addr;
#if 0
if (desc->is_to_self) {
BB_DBG(bb, DBG_PHY_STS, "ie_map=%02d, null_tb_ppdu=%d, valid=%d, length=%d, rssi= {%d}{%d, %d, %d, %d}\n\n",
physts_hdr->ie_bitmap_select,
physts_hdr->null_tb_ppdu,
physts_hdr->is_valid,
physts_hdr->physts_total_length,
TRANS_2_RSSI(physts_hdr->rssi_avg_td),
TRANS_2_RSSI(physts_hdr->rssi_td[0]),
TRANS_2_RSSI(physts_hdr->rssi_td[1]),
TRANS_2_RSSI(physts_hdr->rssi_td[2]),
TRANS_2_RSSI(physts_hdr->rssi_td[3]));
}
#endif
psts_h->rssi_avg = physts_hdr->rssi_avg_td;
psts_h->rssi[0] = physts_hdr->rssi_td[0];
psts_h->rssi[1] = physts_hdr->rssi_td[1];
psts_h->rssi[2] = physts_hdr->rssi_td[2];
psts_h->rssi[3] = physts_hdr->rssi_td[3];
psts_h->ie_map_type = (enum bb_physts_bitmap_t)physts_hdr->ie_bitmap_select;
return physts_hdr->physts_total_length;
}
bool halbb_physts_ie_00(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i;
struct physts_ie_0_info *physts_ie_0 = NULL;
u32 cfo_tmp;
physts_ie_0 = (struct physts_ie_0_info *)addr;
psts_0->ie_00_addr = addr;
psts_0->rx_path_en_cck = physts_ie_0->rx_path_en_bitmap;
cfo_tmp = (physts_ie_0->avg_cfo_m << 8) | physts_ie_0->avg_cfo_l;
psts_0->cfo_avg_cck = (s16) halbb_cnvrt_2_sign(cfo_tmp, 12);
psts_0->evm_avg_cck = physts_ie_0->rxevm_pld;
psts_0->avg_idle_noise_pwr_cck = physts_ie_0->avg_idle_noise_pwr;
psts_0->rpl = (physts_ie_0->rpl_m << 1) | physts_ie_0->rpl_l;
psts_0->pop_idx_cck = physts_ie_0->pop_idx;
halbb_mod_rssi_by_path_en(bb, psts_0->rx_path_en_cck);
return true;
}
bool halbb_physts_ie_01(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i;
struct physts_ie_1_info *ie_1 = NULL;
u32 cfo_tmp;
ie_1 = (struct physts_ie_1_info *)addr;
psts_1->ie_01_addr = addr;
/*0~6: 5, 10, 20, 40, 80, 160, 80_80*/
if (ie_1->bw_idx == 0)
psts_1->bw_idx = CHANNEL_WIDTH_5;
else if (ie_1->bw_idx == 1)
psts_1->bw_idx = CHANNEL_WIDTH_10;
else if (ie_1->bw_idx == 2)
psts_1->bw_idx = CHANNEL_WIDTH_20;
else if (ie_1->bw_idx == 3)
psts_1->bw_idx = CHANNEL_WIDTH_40;
else if (ie_1->bw_idx == 4)
psts_1->bw_idx = CHANNEL_WIDTH_80;
else if (ie_1->bw_idx == 5)
psts_1->bw_idx = CHANNEL_WIDTH_160;
else if (ie_1->bw_idx == 6)
psts_1->bw_idx = CHANNEL_WIDTH_80_80;
else
psts_1->bw_idx = CHANNEL_WIDTH_20;
psts_1->rx_path_en = ie_1->rx_path_en_bitmap;
#if 0
cfo_tmp = (ie_1->avg_cfo_premb_seg0_m << 4) | ie_1->avg_cfo_premb_seg0_l;
psts_1->cfo_pab_avg = (s16) halbb_cnvrt_2_sign(cfo_tmp, 12);
#else
cfo_tmp = (((u32)ie_1->avg_cfo_seg0_m) << 8) | (u32)ie_1->avg_cfo_seg0_l;
psts_1->cfo_avg = (s16)halbb_cnvrt_2_sign(cfo_tmp, 12);
cfo_tmp = (((u32)ie_1->avg_cfo_premb_seg0_m) << 4) | (u32)ie_1->avg_cfo_premb_seg0_l;
psts_1->cfo_pab_avg = (s16)halbb_cnvrt_2_sign(cfo_tmp, 12);
#endif
psts_1->evm_max = ie_1->evm_max;
psts_1->evm_min = ie_1->evm_min;
psts_1->snr_avg = ie_1->avg_snr;
psts_1->cn_avg = ie_1->avg_cn_seg0;
psts_1->avg_idle_noise_pwr = ie_1->avg_idle_noise_pwr;
psts_1->pop_idx = ie_1->pop_idx;
psts_1->ch_idx = ie_1->ch_idx_seg0;
psts_1->rpl_fd = ie_1->rssi_avg_fd;
//psts_1->bw_idx = ie_1->bw_idx;
psts_1->rxsc = ie_1->rxsc;
psts_1->is_su = ie_1->is_su;
psts_1->is_ldpc = ie_1->is_ldpc;
psts_1->is_ndp = ie_1->is_ndp;
psts_1->is_stbc = ie_1->is_stbc;
psts_1->grant_bt = ie_1->grant_bt;
psts_1->is_awgn = ie_1->is_awgn;
psts_1->is_bf = ie_1->is_bf;
//BB_DBG(bb, DBG_CMN, "[1]cfo_avg=%d, evm_max=%d, evm_min=%d, cn_avg=%d\n",
// psts_1->cfo_avg, psts_1->evm_max, psts_1->evm_min, psts_1->cn_avg);
halbb_mod_rssi_by_path_en(bb, psts_1->rx_path_en);
return true;
}
bool halbb_physts_ie_02(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_2_info *psts_2 = &physts->bb_physts_rslt_2_i;
struct physts_ie_2_info *ie_2 = NULL;
u32 cfo_tmp;
u32 lt_cfo_buffer_th = (1<<24);
u32 lt_cfo_abs_tmp_i,lt_cfo_abs_tmp_q;
ie_2 = (struct physts_ie_2_info *)addr;
psts_2->ie_02_addr = addr;
psts_2->max_nsts = ie_2->max_nsts;
psts_2->ltf_type = ie_2->ltf_type;
psts_2->gi = ie_2->gi;
cfo_tmp = (ie_2->c_cfo_i_m1<<10) | (ie_2->c_cfo_i_m2<<2) | ie_2->c_cfo_i_l;
psts_2->c_cfo_i = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18);
psts_2->rx_info_1 = ie_2->rx_info_1;
psts_2->rx_state_feq = ie_2->rx_state_feq;
cfo_tmp = (ie_2->c_cfo_q_m1<<10) | (ie_2->c_cfo_q_m2<<2) | ie_2->c_cfo_q_l;
psts_2->c_cfo_q = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18);
psts_2->est_cmped_phase = ie_2->est_cmped_phase;
psts_2->pkt_extension = ie_2->pkt_extension;
cfo_tmp = (ie_2->f_cfo_i_m1<<10) | (ie_2->f_cfo_i_m2<<2) | ie_2->f_cfo_i_l;
psts_2->f_cfo_i = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18);
psts_2->n_ltf = ie_2->n_ltf;
psts_2->n_sym = (ie_2->n_sym_m<<5) | ie_2->n_sym_l;
cfo_tmp = (ie_2->f_cfo_q_m1<<10) | (ie_2->f_cfo_q_m2<<2) | ie_2->f_cfo_q_l;
psts_2->f_cfo_q = (s32) halbb_cnvrt_2_sign(cfo_tmp, 18);
psts_2->midamble = ie_2->midamble;
psts_2->is_mu_mimo = ie_2->is_mu_mimo;
psts_2->is_dl_ofdma = ie_2->is_dl_ofdma;
psts_2->is_dcm = ie_2->is_dcm;
psts_2->is_doppler = ie_2->is_doppler;
physts->l_ltf_cfo_i += psts_2->f_cfo_i;
physts->l_ltf_cfo_q += psts_2->f_cfo_q;
lt_cfo_abs_tmp_i = ABS_32(physts->l_ltf_cfo_i);
lt_cfo_abs_tmp_q = ABS_32(physts->l_ltf_cfo_q);
if ( lt_cfo_abs_tmp_i > lt_cfo_buffer_th || lt_cfo_abs_tmp_q > lt_cfo_buffer_th ){
physts->l_ltf_cfo_i = physts->l_ltf_cfo_i >> 16;
physts->l_ltf_cfo_q = physts->l_ltf_cfo_q >> 16;
}
return true;
}
bool halbb_physts_ie_03(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_3_info *psts_3 = &physts->bb_physts_rslt_3_i;
struct physts_ie_3_info *ie_3 = NULL;
ie_3 = (struct physts_ie_3_info *)addr;
psts_3->ie_03_addr = addr;
psts_3->avg_cn_seg1 = ie_3->avg_cn_seg1;
psts_3->sigval_below_th_tone_cnt_seg1 = ie_3->sigval_below_th_tone_cnt_seg1;
psts_3->cn_excess_th_tone_cnt_seg1 = ie_3->cn_excess_th_tone_cnt_seg1;
psts_3->avg_cfo_seg1 = (ie_3->avg_cfo_seg1_m<<8) | ie_3->avg_cfo_seg1_l;
psts_3->avg_cfo_premb_seg1 = (ie_3->avg_cfo_premb_seg1_m<<8) | ie_3->avg_cfo_premb_seg1_l;
psts_3->est_cmped_phase_seg1 = ie_3->est_cmped_phase_seg1;
psts_3->avg_snr_seg1 = ie_3->avg_snr_seg1;
psts_3->c_cfo_i_seg1 = (ie_3->c_cfo_i_seg1_m1<<10) | (ie_3->c_cfo_i_seg1_m2<<2) | ie_3->c_cfo_i_seg1_l;
psts_3->c_cfo_q_seg1 = (ie_3->c_cfo_q_seg1_m<<16) | (ie_3->c_cfo_q_seg1_l1<<8) | ie_3->c_cfo_q_seg1_l2;
psts_3->f_cfo_i_seg1 = (ie_3->f_cfo_i_seg1_m<<14) | (ie_3->f_cfo_i_seg1_lm<<6) | ie_3->f_cfo_i_seg1_l;
psts_3->f_cfo_q_seg1 = (ie_3->f_cfo_q_seg1_m<<12) | (ie_3->f_cfo_q_seg1_lm<<4) | ie_3->f_cfo_q_seg1_l;
psts_3->ch_idx_seg1 = ie_3->ch_idx_seg1;
psts_3->evm_max_seg1 = ie_3->evm_max_seg1;
psts_3->evm_min_seg1 = ie_3->evm_min_seg1;
return true;
}
bool halbb_physts_ie_04_07(struct bb_info *bb,
enum bb_physts_ie_t ie,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_4_to_7_info *psts_r = NULL;
struct physts_ie_4_to_7_info *ie_4_7 = NULL;
u8 ant_idx_tmp;
if (ie == IE04_CMN_EXT_PATH_A)
psts_r = &physts->bb_physts_rslt_4_i;
else if (ie == IE05_CMN_EXT_PATH_B)
psts_r = &physts->bb_physts_rslt_5_i;
else if (ie == IE06_CMN_EXT_PATH_C)
psts_r = &physts->bb_physts_rslt_6_i;
else if (ie == IE07_CMN_EXT_PATH_D)
psts_r = &physts->bb_physts_rslt_7_i;
else
return false;
ie_4_7 = (struct physts_ie_4_to_7_info *)addr;
psts_r->ie_04_07_addr = addr;
ant_idx_tmp = (ie_4_7->ant_idx_msb << 3) | ie_4_7->ant_idx;
psts_r->ant_idx = ant_idx_tmp;
psts_r->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_4_7->sig_val_y, 8);
psts_r->rf_gain_idx = ie_4_7->rf_gain_idx;
psts_r->snr_lgy = ie_4_7->snr_lgy;
psts_r->evm_ss_y = ie_4_7->evm_ss_y;
psts_r->td_ant_weight = ie_4_7->td_ant_weight;
psts_r->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_4_7->dc_est_re, 8);
psts_r->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_4_7->dc_est_im, 8);
psts_r->rf_tia_gain_idx = ie_4_7->rf_tia_gain_idx;
psts_r->tia_shrink_indicator = ie_4_7->tia_shrink_indicator;
return true;
}
#if 1
bool halbb_physts_ie_05(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_4_to_7_info *psts_5 = &physts->bb_physts_rslt_5_i;
struct physts_ie_4_to_7_info *ie_5 = NULL;
u8 ant_idx_tmp;
ie_5 = (struct physts_ie_4_to_7_info *)addr;
ant_idx_tmp = (ie_5->ant_idx_msb << 3) | ie_5->ant_idx;
psts_5->ant_idx = ant_idx_tmp;
psts_5->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_5->sig_val_y,8);
psts_5->rf_gain_idx = ie_5->rf_gain_idx;
psts_5->snr_lgy = ie_5->snr_lgy;
psts_5->evm_ss_y = ie_5->evm_ss_y;
psts_5->td_ant_weight = ie_5->td_ant_weight;
psts_5->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_5->dc_est_re,8);
psts_5->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_5->dc_est_im,8);
psts_5->rf_tia_gain_idx = ie_5->rf_tia_gain_idx;
psts_5->tia_shrink_indicator = ie_5->tia_shrink_indicator;
return true;
}
bool halbb_physts_ie_06(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_4_to_7_info *psts_6 = &physts->bb_physts_rslt_6_i;
struct physts_ie_4_to_7_info *ie_6 = NULL;
u8 ant_idx_tmp;
ie_6 = (struct physts_ie_4_to_7_info *)addr;
ant_idx_tmp = (ie_6->ant_idx_msb << 3) | ie_6->ant_idx;
psts_6->ant_idx = ant_idx_tmp;
psts_6->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_6->sig_val_y,8);
psts_6->rf_gain_idx = ie_6->rf_gain_idx;
psts_6->snr_lgy = ie_6->snr_lgy;
psts_6->evm_ss_y = ie_6->evm_ss_y;
psts_6->td_ant_weight = ie_6->td_ant_weight;
psts_6->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_6->dc_est_re,8);
psts_6->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_6->dc_est_im,8);
psts_6->rf_tia_gain_idx = ie_6->rf_tia_gain_idx;
psts_6->tia_shrink_indicator = ie_6->tia_shrink_indicator;
return true;
}
bool halbb_physts_ie_07(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_4_to_7_info *psts_7 = &physts->bb_physts_rslt_7_i;
struct physts_ie_4_to_7_info *ie_7 = NULL;
u8 ant_idx_tmp;
ie_7 = (struct physts_ie_4_to_7_info *)addr;
ant_idx_tmp = (ie_7->ant_idx_msb << 3) | ie_7->ant_idx;
psts_7->ant_idx = ant_idx_tmp;
psts_7->sig_val_y = (s8)halbb_cnvrt_2_sign(ie_7->sig_val_y,8);
psts_7->rf_gain_idx = ie_7->rf_gain_idx;
psts_7->snr_lgy = ie_7->snr_lgy;
psts_7->evm_ss_y = ie_7->evm_ss_y;
psts_7->td_ant_weight = ie_7->td_ant_weight;
psts_7->dc_est_re = (s8)halbb_cnvrt_2_sign(ie_7->dc_est_re,8);
psts_7->dc_est_im = (s8)halbb_cnvrt_2_sign(ie_7->dc_est_im,8);
psts_7->rf_tia_gain_idx = ie_7->rf_tia_gain_idx;
psts_7->tia_shrink_indicator = ie_7->tia_shrink_indicator;
return true;
}
#endif
bool halbb_physts_ie_08(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_8_info *psts_8 = &physts->bb_physts_rslt_8_i;
struct physts_ie_8_ch_info *ie_8 = NULL;
#ifdef HALBB_CH_INFO_SUPPORT
struct bb_ch_info_raw_info *buf = &bb->bb_ch_rpt_i.bb_ch_info_raw_i;
struct bb_ch_info_physts_info *ch_physts = &bb->bb_ch_rpt_i.bb_ch_info_physts_i;
#endif
u64 *phy_sts_tmp = NULL;
ie_8 = (struct physts_ie_8_ch_info *)addr;
psts_8->ie_08_addr = addr;
addr += sizeof(struct physts_ie_8_ch_info);
psts_8->rxsc = ie_8->rxsc;
psts_8->n_rx = ie_8->n_rx;
psts_8->n_sts = ie_8->n_sts;
psts_8->ch_info_len = (ie_8->ch_info_len_m << 2) | ie_8->ch_info_len_l;
psts_8->evm_1_sts= ie_8->evm_1_sts;
psts_8->evm_2_sts = ie_8->evm_2_sts;
psts_8->avg_idle_noise_pwr= ie_8->avg_idle_noise_pwr;
psts_8->is_ch_info_len_valid= ie_8->is_ch_info_len_valid;
#ifdef HALBB_CH_INFO_SUPPORT
if (ch_physts->ch_info_state == CH_RPT_START_TO_WAIT) {
halbb_mem_cpy(bb, buf->octet, (s16*)addr, buf->ch_info_buf_len);
ch_physts->ch_info_state = CH_RPT_GETTED;
ch_physts->ch_info_len = psts_8->ch_info_len;
ch_physts->bitmap_type_rpt = physts->bb_physts_rslt_hdr_i.ie_map_type;
}
#endif
if (bb->bb_physts_i.print_more_info) {
BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-8] ch-raw info. len=%d\n", psts_8->ch_info_len);
halbb_print_buff_64(bb, addr, psts_8->ch_info_len);
}
return true;
}
void halbb_physts_ie_09_lgcy(struct bb_info *bb,
u8 *addr,
u8 rate_mode,
struct physts_rxd *desc)
{
struct physts_ie_9_lgcy_info *ie_9 = NULL;
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i;
ie_9 = (struct physts_ie_9_lgcy_info *)addr;
psts_9->ie_09_addr = addr;
psts_9->l_sig = (ie_9->l_sig_m << 11) | (ie_9->l_sig_lm << 3) | (ie_9->l_sig_l);
}
void halbb_physts_ie_09_vht(struct bb_info *bb,
u8 *addr,
u8 rate_mode,
struct physts_rxd *desc)
{
struct physts_ie_9_vht_info *ie_9 = NULL;
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i;
ie_9 = (struct physts_ie_9_vht_info *)addr;
psts_9->ie_09_addr = addr;
psts_9->l_sig = (ie_9->l_sig_m << 11) | (ie_9->l_sig_lm << 3) | (ie_9->l_sig_l);
psts_9->sig_a1 = (ie_9->sig_a1_m << 18)| (ie_9->sig_a1_lm1 << 10) | (ie_9->sig_a1_lm2 << 2) | (ie_9->sig_a1_l);
psts_9->sig_a2 = (ie_9->sig_a2_m << 2) | (ie_9->sig_a2_l);
}
void halbb_physts_ie_09_he(struct bb_info *bb,
u8 *addr,
u8 rate_mode,
struct physts_rxd *desc)
{
struct physts_ie_9_he_info *ie_9 = NULL;
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_9_info *psts_9 = &physts->bb_physts_rslt_9_i;
ie_9 = (struct physts_ie_9_he_info *)addr;
psts_9->ie_09_addr = addr;
psts_9->l_sig = (ie_9->l_sig_m<<11) | (ie_9->l_sig_lm<<3) | (ie_9->l_sig_l);
psts_9->sig_a1 = (ie_9->sig_a1_m1<<18) | (ie_9->sig_a1_m2<<10) | (ie_9->sig_a1_m3<<2) | (ie_9->sig_a1_l);
psts_9->sig_a2 = (ie_9->sig_a2_m << 8) | (ie_9->sig_a2_l);
#ifdef BB_8852A_2_SUPPORT
if (bb->ic_type == BB_RTL8852A &&
bb->hal_com->cv <= CBV) {
if (psts_9->sig_a1 & BIT7 && /*DCM == 1*/
((psts_9->sig_a1 & 0x3800000) >> 23) == 1 && /*NSTS == 2*/
psts_9->sig_a2 & BIT9) { /*STBC == 1*/
desc->data_rate &= ~0x70;
desc->data_rate |= 0x10; /*HW issue*/
}
}
#endif
}
bool halbb_physts_ie_09(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
u8 mode = physts->bb_rate_i.mode;
/* To get rate mode for plcp ie parsing */
/* allocate different plcp type structure */
if (mode == BB_LEGACY_MODE) {
halbb_physts_ie_09_lgcy(bb, addr, mode, desc);
} else if ((mode == BB_HT_MODE) || (mode == BB_VHT_MODE)) {
halbb_physts_ie_09_vht(bb, addr, mode, desc);
} else if (mode == BB_HE_MODE) {
halbb_physts_ie_09_he(bb, addr, mode, desc);
}
return true;
}
bool halbb_physts_ie_10(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct physts_ie_10_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_10_sigb_info physts_sigb;
u16 sigb_len; /* bytes */
physts_c = (struct physts_ie_10_cmn_info *)addr;
addr += sizeof(struct physts_ie_10_cmn_info);
physts_sigb.sigb_raw_data_bits_addr = addr;
/* SIG-B len(with zero padding)= IE length - remaining cotent len (64bits)*/
sigb_len = ie_length - 8;
if (bb->bb_physts_i.print_more_info) {
BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-10] SIG-B len(with zero-pad)=%d\n", sigb_len);
halbb_print_buff_64(bb, physts_sigb.sigb_raw_data_bits_addr, sigb_len);
}
return true;
}
bool halbb_physts_ie_11(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_11_info *psts_11 = &physts->bb_physts_rslt_11_i;
struct physts_ie_11_info *ie_11 = NULL;
ie_11 = (struct physts_ie_11_info *)addr;
psts_11->ie_11_addr = addr;
psts_11->l_sig = (ie_11->l_sig_m << 11) | (ie_11->l_sig_lm << 3) | (ie_11->l_sig_l);
psts_11->sig_a1 = (ie_11->sig_a1_m1 << 18) | (ie_11->sig_a1_m2 << 10) | (ie_11->sig_a1_m3 << 2) | (ie_11->sig_a1_l);
psts_11->sig_a2 = (ie_11->sig_a2_m<<8) | ie_11->sig_a2_l;
psts_11->time_stamp = (ie_11->time_stamp_m << 8) | (ie_11->time_stamp_l);
psts_11->rx_pkt_info_idx = ie_11->rx_pkt_info_idx;
psts_11->tx_pkt_info_idx = (ie_11->tx_pkt_info_idx_m << 1) | (ie_11->tx_pkt_info_idx_l);
return true;
}
bool halbb_physts_ie_12(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_12_info *psts_12 = &physts->bb_physts_rslt_12_i;
struct physts_ie_12_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_12_user_info *physts_u[MU_USER_MAX] = {NULL}; /*per user*/
u8 i;
physts_c = (struct physts_ie_12_cmn_info *)addr;
psts_12->ie_12_addr = addr;
addr += sizeof(struct physts_ie_12_cmn_info);
//BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-12]n_user=%d\n",physts_c->n_user);
psts_12->n_user = physts_c->n_user;
for (i = 0; i < physts_c->n_user; i++) {
if (i >= MU_USER_MAX)
break;
physts_u[i] = (struct physts_ie_12_user_info *)addr;
/*
physts_u[i].sig_val_ss0_seg_cr_user_i = *addr;
physts_u[i].sig_val_ss1_seg_cr_user_i = *(++addr);
physts_u[i].sig_val_ss2_seg_cr_user_i = *(++addr);
physts_u[i].sig_val_ss3_seg_cr_user_i = *(++addr);
physts_u[i].sig_bad_tone_cnt_seg_cr_user_i = *(++addr);
physts_u[i].cn_bad_tone_cnt_seg_cr_user_i = *(++addr);
*/
psts_12->bb_physts_uer_info[i].cn_bad_tone_cnt_seg_cr_user_i =
physts_u[i]->cn_bad_tone_cnt_seg_cr_user_i;
psts_12->bb_physts_uer_info[i].sig_bad_tone_cnt_seg_cr_user_i =
physts_u[i]->sig_bad_tone_cnt_seg_cr_user_i;
psts_12->bb_physts_uer_info[i].sig_val_ss0_seg_cr_user_i =
physts_u[i]->sig_val_ss0_seg_cr_user_i;
psts_12->bb_physts_uer_info[i].sig_val_ss1_seg_cr_user_i =
physts_u[i]->sig_val_ss1_seg_cr_user_i;
psts_12->bb_physts_uer_info[i].sig_val_ss2_seg_cr_user_i =
physts_u[i]->sig_val_ss2_seg_cr_user_i;
psts_12->bb_physts_uer_info[i].sig_val_ss3_seg_cr_user_i =
physts_u[i]->sig_val_ss3_seg_cr_user_i;
addr += sizeof(struct physts_ie_12_user_info);
}
return true;
}
bool halbb_physts_ie_13(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_13_info *psts_13 = &physts->bb_physts_rslt_13_i;
struct physts_ie_13_cmn_info_p1 *physts_c = NULL; /*common*/
struct physts_ie_13_cmn_info_p2 *physts_c2 = NULL; /*common*/
struct physts_ie_13_user_info *physts_u[MU_USER_MAX] = {NULL}; /*per user*/
u8 i;
u16 sta_id_tmp;
physts_c = (struct physts_ie_13_cmn_info_p1 *)addr;
psts_13->ie_13_addr = addr;
addr += sizeof(struct physts_ie_13_cmn_info_p1);
//BB_DBG(bb, DBG_PHY_STS, "n_user=%d\n", physts_c->n_user);
psts_13->n_user = physts_c->n_user;
for (i = 0; i < physts_c->n_user; i++) {
if (i >= MU_USER_MAX)
break;
physts_u[i] = (struct physts_ie_13_user_info *)addr;
psts_13->bb_physts_uer_info[i].avg_cn_seg_cr = physts_u[i]->avg_cn_seg_cr;
psts_13->bb_physts_uer_info[i].fec_type = physts_u[i]->fec_type;
psts_13->bb_physts_uer_info[i].is_awgn = physts_u[i]->is_awgn;
psts_13->bb_physts_uer_info[i].is_bf= physts_u[i]->is_bf;
psts_13->bb_physts_uer_info[i].is_dcm = physts_u[i]->is_dcm;
psts_13->bb_physts_uer_info[i].is_mu_mimo = physts_u[i]->is_mu_mimo;
psts_13->bb_physts_uer_info[i].mcs = physts_u[i]->mcs;
psts_13->bb_physts_uer_info[i].n_sts = physts_u[i]->n_sts;
psts_13->bb_physts_uer_info[i].n_sts_ru_total = physts_u[i]->n_sts_ru_total;
psts_13->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type = physts_u[i]->pdp_he_ltf_and_gi_type;
psts_13->bb_physts_uer_info[i].pilot_exist = physts_u[i]->pilot_exist;
psts_13->bb_physts_uer_info[i].ru_alloc = physts_u[i]->ru_alloc;
psts_13->bb_physts_uer_info[i].rx_evm_max_seg_cr = physts_u[i]->rx_evm_max_seg_cr;
psts_13->bb_physts_uer_info[i].rx_evm_min_seg_cr = physts_u[i]->rx_evm_min_seg_cr;
psts_13->bb_physts_uer_info[i].snr = (s8)halbb_cnvrt_2_sign(physts_u[i]->snr,8);
psts_13->bb_physts_uer_info[i].start_sts = physts_u[i]->start_sts;
sta_id_tmp = (physts_u[i]->sta_id_m << 8) | physts_u[i]->sta_id_l;
psts_13->bb_physts_uer_info[i].sta_id = sta_id_tmp;
addr += sizeof(struct physts_ie_13_user_info);
}
physts_c2 = (struct physts_ie_13_cmn_info_p2 *)addr;
psts_13->n_not_sup_sta = physts_c2->n_not_sup_sta;
return true;
}
bool halbb_physts_ie_14(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_14_info *psts_14 = &physts->bb_physts_rslt_14_i;
struct physts_ie_14_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_14_user_info physts_u[TB_USER_MAX]; /*per user*/
u8 cqi_user_len = 0;
u8 *cqi_user_addr;
u8 i;
physts_c = (struct physts_ie_14_cmn_info *)addr;
psts_14->ie_14_addr = addr;
addr += sizeof(struct physts_ie_14_cmn_info);
psts_14->n_user = physts_c->n_user;
psts_14->rxinfo_ndp_en= physts_c->rxinfo_ndp_en;
for (i = 0; i < physts_c->n_user; i++) {
if (i >= TB_USER_MAX)
break;
physts_u[i].cqi_bitmap_ul_tb = *addr;
physts_u[i].cqi_raw_len_ul_tb = *(++addr);
physts_u[i].cqi_raw_ul_tb_addr = (++addr);
psts_14->bb_physts_uer_info[i].cqi_bitmap_ul_tb = physts_u[i].cqi_bitmap_ul_tb;
psts_14->bb_physts_uer_info[i].cqi_raw_len_ul_tb = physts_u[i].cqi_raw_len_ul_tb;
psts_14->bb_physts_uer_info[i].cqi_raw_ul_tb_addr= physts_u[i].cqi_raw_ul_tb_addr;
addr += physts_u[i].cqi_raw_len_ul_tb;
}
for (i = 0; i < physts_c->n_user; i++) {
if (i >= TB_USER_MAX)
break;
cqi_user_len = physts_u[i].cqi_raw_len_ul_tb;
cqi_user_addr = physts_u[i].cqi_raw_ul_tb_addr;
if (bb->bb_physts_i.print_more_info) {
BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-14][User:%d] len=%d\n", i, cqi_user_len);
halbb_print_buff_64(bb, cqi_user_addr, cqi_user_len);
}
}
return true;
}
bool halbb_physts_ie_15(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_15_info *psts_15 = &physts->bb_physts_rslt_15_i;
struct physts_ie_15_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_15_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/
u8 i;
u16 rssi_tmp;
s16 cfo_tmp;
physts_c = (struct physts_ie_15_cmn_info *)addr;
psts_15->ie_15_addr = addr;
addr += sizeof(struct physts_ie_15_cmn_info);
psts_15->n_user = physts_c->n_user;
for (i = 0; i < physts_c->n_user; i++) {
if (i >= TB_USER_MAX)
break;
physts_u[i] = (struct physts_ie_15_user_info *)addr;
cfo_tmp = (s16) halbb_cnvrt_2_sign(((physts_u[i]->avg_cfo_seg0_m << 8) | physts_u[i]->avg_cfo_seg0_l), 12);
rssi_tmp = (physts_u[i]->rssi_m_ul_tb_m << 8) | physts_u[i]->rssi_m_ul_tb_l;
psts_15->bb_physts_uer_info[i].avg_cn_seg_cr = physts_u[i]->avg_cn_seg_cr;
psts_15->bb_physts_uer_info[i].fec_type = physts_u[i]->fec_type;
psts_15->bb_physts_uer_info[i].is_awgn = physts_u[i]->is_awgn;
psts_15->bb_physts_uer_info[i].is_bf= physts_u[i]->is_bf;
psts_15->bb_physts_uer_info[i].is_dcm = physts_u[i]->is_dcm;
psts_15->bb_physts_uer_info[i].is_mu_mimo = physts_u[i]->is_mu_mimo;
psts_15->bb_physts_uer_info[i].mcs = physts_u[i]->mcs;
psts_15->bb_physts_uer_info[i].n_sts = physts_u[i]->n_sts;
psts_15->bb_physts_uer_info[i].n_sts_ru_total = physts_u[i]->n_sts_ru_total;
psts_15->bb_physts_uer_info[i].pdp_he_ltf_and_gi_type = physts_u[i]->pdp_he_ltf_and_gi_type;
psts_15->bb_physts_uer_info[i].pilot_exist = physts_u[i]->pilot_exist;
psts_15->bb_physts_uer_info[i].ru_alloc = physts_u[i]->ru_alloc;
psts_15->bb_physts_uer_info[i].rx_evm_max_seg_cr = physts_u[i]->rx_evm_max_seg_cr;
psts_15->bb_physts_uer_info[i].rx_evm_min_seg_cr = physts_u[i]->rx_evm_min_seg_cr;
psts_15->bb_physts_uer_info[i].snr = physts_u[i]->snr;
psts_15->bb_physts_uer_info[i].start_sts = physts_u[i]->start_sts;
psts_15->bb_physts_uer_info[i].uid = physts_u[i]->uid;
psts_15->bb_physts_uer_info[i].avg_cfo_seg0 = cfo_tmp;
psts_15->bb_physts_uer_info[i].rssi_m_ul_tb = rssi_tmp;
addr += sizeof(struct physts_ie_15_user_info);
}
return true;
}
bool halbb_physts_ie_17(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct physts_ie_17_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_17_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_17_info *psts_17 = &physts->bb_physts_rslt_17_i;
u8 i;
u8 n_user;
physts_c = (struct physts_ie_17_cmn_info *)addr;
psts_17->ie_17_addr = addr;
addr += sizeof(struct physts_ie_17_cmn_info);
psts_17->bb_physts_cmn_info.stbc_en = physts_c->stbc_en;
psts_17->bb_physts_cmn_info.ldpc_extra = physts_c->ldpc_extra;
psts_17->bb_physts_cmn_info.doppler_en = physts_c->doppler_en;
psts_17->bb_physts_cmn_info.midamle_mode = physts_c->midamle_mode;
psts_17->bb_physts_cmn_info.gi_type = physts_c->gi_type;
psts_17->bb_physts_cmn_info.ltf_type = physts_c->ltf_type;
psts_17->bb_physts_cmn_info.n_ltf = physts_c->n_ltf;
psts_17->bb_physts_cmn_info.n_sym = (physts_c->n_sym_m<<5)|physts_c->n_sym_l;
psts_17->bb_physts_cmn_info.pe_idx = ((physts_c->pe_idx_m<<2)|physts_c->pe_idx_l);
psts_17->bb_physts_cmn_info.pre_fec_factor = physts_c->pre_fec_factor;
psts_17->bb_physts_cmn_info.n_usr = ((physts_c->n_user_m<<5)|physts_c->n_user_l);
psts_17->bb_physts_cmn_info.mumimo_ltf_mode_en = physts_c->mumimo_ltf_mode_en;
psts_17->bb_physts_cmn_info.ndp = physts_c->ndp;
psts_17->bb_physts_cmn_info.pri_exp_rssi_dbm = ((physts_c->pri_exp_rssi_dbm_m<<3)|physts_c->pri_exp_rssi_dbm_l);
psts_17->bb_physts_cmn_info.dbw_idx = physts_c->dbw_idx;
psts_17->bb_physts_cmn_info.rxtime = (physts_c->rxtime_m<<8)|physts_c->rxtime_l;
n_user = (physts_c->n_user_m<<4) | physts_c->n_user_l;
psts_17->n_user = n_user;
//BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-17]n_user=%d\n", n_user);
for (i = 0; i < n_user; i++) {
if (i >= TB_USER_MAX)
break;
physts_u[i] = (struct physts_ie_17_user_info *)addr;
psts_17->bb_physts_uer_info[i].u_id= physts_u[i]->u_id;
psts_17->bb_physts_uer_info[i].ru_alloc= physts_u[i]->ru_alloc;
psts_17->bb_physts_uer_info[i].n_sts_ru_tot= physts_u[i]->n_sts_ru_tot;
psts_17->bb_physts_uer_info[i].strt_sts= physts_u[i]->strt_sts;
psts_17->bb_physts_uer_info[i].n_sts= physts_u[i]->n_sts;
psts_17->bb_physts_uer_info[i].fec_type= physts_u[i]->fec_type;
psts_17->bb_physts_uer_info[i].mcs= physts_u[i]->mcs;
psts_17->bb_physts_uer_info[i].dcm_en= (bool)physts_u[i]->dcm_en;
addr += sizeof(struct physts_ie_17_user_info);
}
return true;
}
bool halbb_physts_ie_18(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_18_info *psts_18 = &physts->bb_physts_rslt_18_i;
struct physts_ie_18_info *ie_18 = NULL;
ie_18 = (struct physts_ie_18_info *)addr;
psts_18->ie_18_addr = addr;
psts_18->rx_time = (ie_18->rx_time_m<<8) | ie_18->rx_time_l;
psts_18->ch_len_lgcy_seg0 = ie_18->ch_len_lgcy_seg0;
psts_18->bw_det_seg0 = ie_18->bw_det_seg0;
psts_18->snr_idx_lgcy_seg0 = ie_18->snr_idx_lgcy_seg0;
psts_18->pdp_idx_lgcy_seg0 = ie_18->pdp_idx_lgcy_seg0;
psts_18->pfd_flow = (ie_18->pfd_flow_m<<8) | ie_18->pfd_flow_l;
psts_18->ch_len_lgcy_seg1 = ie_18->ch_len_lgcy_seg1;
psts_18->bw_det_seg1 = ie_18->bw_det_seg1;
psts_18->snr_idx_lgcy_seg1 = ie_18->snr_idx_lgcy_seg1;
psts_18->pdp_idx_lgcy_seg1 = ie_18->pdp_idx_lgcy_seg1;
psts_18->is_seg1_exist = ie_18->is_seg1_exist;
return true;
}
bool halbb_physts_ie_19(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_19_info *psts_19 = &physts->bb_physts_rslt_19_i;
struct physts_ie_19_info *ie_19 = NULL;
ie_19 = (struct physts_ie_19_info *)addr;
psts_19->ie_19_addr = addr;
psts_19->ppdu_inpwrdbm_p20 = ie_19->ppdu_inpwrdbm_p20;
psts_19->ppdu_inpwrdbm_s20 = ie_19->ppdu_inpwrdbm_s20;
psts_19->ppdu_inpwrdbm_s40 = ie_19->ppdu_inpwrdbm_s40;
psts_19->ppdu_inpwrdbm_s80 = ie_19->ppdu_inpwrdbm_s80;
psts_19->ppdu_inpwrdbm_per20_1 = ie_19->ppdu_inpwrdbm_per20_1;
psts_19->ppdu_inpwrdbm_per20_2 = ie_19->ppdu_inpwrdbm_per20_2;
psts_19->ppdu_inpwrdbm_per20_3 = ie_19->ppdu_inpwrdbm_per20_3;
psts_19->ppdu_inpwrdbm_per20_4 = ie_19->ppdu_inpwrdbm_per20_4;
psts_19->edcca_rpt_cnt_p20 = ie_19->edcca_rpt_cnt_p20;
psts_19->edcca_rpt_p20_max = ie_19->edcca_rpt_p20_max;
psts_19->edcca_rpt_p20_min = ie_19->edcca_rpt_p20_min;
psts_19->edcca_total_smp_cnt = ie_19->edcca_total_smp_cnt;
psts_19->edcca_rpt_cnt_s80 = ie_19->edcca_rpt_cnt_s80;
psts_19->edcca_rpt_cnt_s80_max = ie_19->edcca_rpt_cnt_s80_max;
psts_19->edcca_rpt_cnt_s80_min = ie_19->edcca_rpt_cnt_s80_min;
psts_19->pop_reg_pwr = ie_19->pop_reg_pwr;
psts_19->pop_trig_pwr = ie_19->pop_trig_pwr;
psts_19->early_drop_pwr = ie_19->early_drop_pwr;
psts_19->tx_over_flow = ie_19->tx_over_flow;
return true;
}
bool halbb_physts_ie_20(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_20_info *psts_20 = &physts->bb_physts_rslt_20_i;
struct physts_ie_20_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_20_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/
u8 i;
physts_c = (struct physts_ie_20_cmn_info *)addr;
psts_20->ie_20_addr = addr;
addr += sizeof(struct physts_ie_20_cmn_info);
//BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-20]n_user=%d\n", physts_c->n_user);
for (i = 0; i < physts_c->n_user; i++) {
if (i >= TB_USER_MAX)
break;
physts_u[i] = (struct physts_ie_20_user_info *)addr;
addr += sizeof(struct physts_ie_20_user_info);
/* mapping to the bb struct */
psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_0_seg_0 =
physts_u[i]->ch_smo_n_block_lgcy_sub_0_seg_0;
psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_1_seg_0 =
physts_u[i]->ch_smo_n_block_lgcy_sub_1_seg_0;
psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_2_seg_0 =
physts_u[i]->ch_smo_n_block_lgcy_sub_2_seg_0;
psts_20->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_3_seg_0 =
physts_u[i]->ch_smo_n_block_lgcy_sub_3_seg_0;
psts_20->bb_physts_usr_info[i].ch_smo_en_lgcy_seg_0 =
physts_u[i]->ch_smo_en_lgcy_seg_0;
psts_20->bb_physts_usr_info[i].ch_smo_en_non_lgcy_seg_0 =
physts_u[i]->ch_smo_en_non_lgcy_seg_0;
psts_20->bb_physts_usr_info[i].ch_smo_n_block_non_lgcy_seg_0 =
physts_u[i]->ch_smo_n_block_non_lgcy_seg_0;
psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_0_seg_0 =
physts_u[i]->ch_len_non_lgcy_sts_0_seg_0;
psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_1_seg_0 =
physts_u[i]->ch_len_non_lgcy_sts_1_seg_0;
psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_2_seg_0 =
physts_u[i]->ch_len_non_lgcy_sts_2_seg_0;
psts_20->bb_physts_usr_info[i].ch_len_non_lgcy_sts_3_seg_0 =
physts_u[i]->ch_len_non_lgcy_sts_3_seg_0;
psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_0_seg_0 =
physts_u[i]->snr_idx_non_lgy_sts_0_seg_0;
psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_1_seg_0 =
physts_u[i]->snr_idx_non_lgy_sts_1_seg_0;
psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_2_seg_0 =
(physts_u[i]->snr_idx_non_lgy_sts_2_seg_0_m<<2) |
physts_u[i]->snr_idx_non_lgy_sts_2_seg_0_l;
psts_20->bb_physts_usr_info[i].snr_idx_non_lgy_sts_3_seg_0 =
physts_u[i]->snr_idx_non_lgy_sts_3_seg_0;
psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_0_seg_0 =
physts_u[i]->pdp_idx_non_lgcy_sts_0_seg_0;
psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_1_seg_0 =
(physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_0_m<<1) |
physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_0_l;
psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_2_seg_0 =
physts_u[i]->pdp_idx_non_lgcy_sts_2_seg_0;
psts_20->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_3_seg_0 =
physts_u[i]->pdp_idx_non_lgcy_sts_3_seg_0;
psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_0_seg_0 =
physts_u[i]->snr_non_lgy_sts_0_seg_0;
psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_1_seg_0 =
physts_u[i]->snr_non_lgy_sts_1_seg_0;
psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_2_seg_0 =
physts_u[i]->snr_non_lgy_sts_2_seg_0;
psts_20->bb_physts_usr_info[i].snr_non_lgy_sts_3_seg_0 =
physts_u[i]->snr_non_lgy_sts_3_seg_0;
psts_20->bb_physts_usr_info[i].evm_ss_0_seg_0 =
physts_u[i]->evm_ss_0_seg_0;
psts_20->bb_physts_usr_info[i].evm_ss_1_seg_0 =
physts_u[i]->evm_ss_1_seg_0;
psts_20->bb_physts_usr_info[i].evm_ss_2_seg_0 =
physts_u[i]->evm_ss_2_seg_0;
psts_20->bb_physts_usr_info[i].evm_ss_3_seg_0 =
physts_u[i]->evm_ss_3_seg_0;
}
return true;
}
bool halbb_physts_ie_21(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_21_info *psts_21 = &physts->bb_physts_rslt_21_i;
struct physts_ie_21_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_21_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/
u8 i;
physts_c = (struct physts_ie_21_cmn_info *)addr;
psts_21->ie_21_addr = addr;
addr += sizeof(struct physts_ie_21_cmn_info);
//BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-21]n_user=%d\n", physts_c->n_user);
for (i = 0; i < physts_c->n_user; i++) {
if (i >= TB_USER_MAX)
break;
physts_u[i] = (struct physts_ie_21_user_info *)addr;
addr += sizeof(struct physts_ie_21_user_info);
/* mapping to the bb struct */
psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_0_seg_1 =
physts_u[i]->ch_smo_n_block_lgcy_sub_0_seg_1;
psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_1_seg_1 =
physts_u[i]->ch_smo_n_block_lgcy_sub_1_seg_1;
psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_2_seg_1 =
physts_u[i]->ch_smo_n_block_lgcy_sub_2_seg_1;
psts_21->bb_physts_usr_info[i].ch_smo_n_block_lgcy_sub_3_seg_1 =
physts_u[i]->ch_smo_n_block_lgcy_sub_3_seg_1;
psts_21->bb_physts_usr_info[i].ch_smo_en_lgcy_seg_1 =
physts_u[i]->ch_smo_en_lgcy_seg_1;
psts_21->bb_physts_usr_info[i].ch_smo_en_non_lgcy_seg_1 =
physts_u[i]->ch_smo_en_non_lgcy_seg_1;
psts_21->bb_physts_usr_info[i].ch_smo_n_block_non_lgcy_seg_1 =
physts_u[i]->ch_smo_n_block_non_lgcy_seg_1;
psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_0_seg_1 =
physts_u[i]->ch_len_non_lgcy_sts_0_seg_1;
psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_1_seg_1 =
physts_u[i]->ch_len_non_lgcy_sts_1_seg_1;
psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_2_seg_1 =
physts_u[i]->ch_len_non_lgcy_sts_2_seg_1;
psts_21->bb_physts_usr_info[i].ch_len_non_lgcy_sts_3_seg_1 =
physts_u[i]->ch_len_non_lgcy_sts_3_seg_1;
psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_0_seg_1 =
physts_u[i]->snr_idx_non_lgy_sts_0_seg_1;
psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_1_seg_1 =
physts_u[i]->snr_idx_non_lgy_sts_1_seg_1;
psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_2_seg_1 =
(physts_u[i]->snr_idx_non_lgy_sts_2_seg_1_m<<2) |
physts_u[i]->snr_idx_non_lgy_sts_2_seg_1_l;
psts_21->bb_physts_usr_info[i].snr_idx_non_lgy_sts_3_seg_1 =
physts_u[i]->snr_idx_non_lgy_sts_3_seg_1;
psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_0_seg_1 =
physts_u[i]->pdp_idx_non_lgcy_sts_0_seg_1;
psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_1_seg_1 =
(physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_1_m<<1) |
physts_u[i]->pdp_idx_non_lgcy_sts_1_seg_1_l;
psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_2_seg_1 =
physts_u[i]->pdp_idx_non_lgcy_sts_2_seg_1;
psts_21->bb_physts_usr_info[i].pdp_idx_non_lgcy_sts_3_seg_1 =
physts_u[i]->pdp_idx_non_lgcy_sts_3_seg_1;
psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_0_seg_1 =
physts_u[i]->snr_non_lgy_sts_0_seg_1;
psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_1_seg_1 =
physts_u[i]->snr_non_lgy_sts_1_seg_1;
psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_2_seg_1 =
physts_u[i]->snr_non_lgy_sts_2_seg_1;
psts_21->bb_physts_usr_info[i].snr_non_lgy_sts_3_seg_1 =
physts_u[i]->snr_non_lgy_sts_3_seg_1;
psts_21->bb_physts_usr_info[i].evm_ss_0_seg_1 =
physts_u[i]->evm_ss_0_seg_1;
psts_21->bb_physts_usr_info[i].evm_ss_1_seg_1 =
physts_u[i]->evm_ss_1_seg_1;
psts_21->bb_physts_usr_info[i].evm_ss_2_seg_1 =
physts_u[i]->evm_ss_2_seg_1;
psts_21->bb_physts_usr_info[i].evm_ss_3_seg_1 =
physts_u[i]->evm_ss_3_seg_1;
}
return true;
}
bool halbb_physts_ie_22(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct physts_ie_22_cmn_info *physts_c = NULL; /*common*/
struct physts_ie_22_user_info *physts_u[TB_USER_MAX] = {NULL}; /*per user*/
u8 i;
physts_c = (struct physts_ie_22_cmn_info *)addr;
addr += sizeof(struct physts_ie_22_cmn_info);
//BB_DBG(bb, DBG_PHY_STS, "[Physts][IE-22] n_user=%d\n", physts_c->n_user);
for (i = 0; i < physts_c->n_user; i++) {
if (i >= TB_USER_MAX)
break;
physts_u[i] = (struct physts_ie_22_user_info *)addr;
addr += sizeof(struct physts_ie_22_user_info);
}
return true;
}
bool halbb_physts_ie_24(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_24_info *psts_24 = &physts->bb_physts_rslt_24_i;
struct physts_ie_24_info *ie_24 = NULL;
ie_24 = (struct physts_ie_24_info *)addr;
psts_24->ie_24_addr = addr;
psts_24->pre_agc_step_a = ie_24->pre_agc_step_a;
psts_24->l_fine_agc_step_a = ie_24->l_fine_agc_step_a;
psts_24->ht_fine_agc_step_a = ie_24->ht_fine_agc_step_a;
psts_24->pre_gain_code_a = ie_24->pre_gain_code_a;
psts_24->l_fine_gain_code_a = ie_24->l_fine_gain_code_a;
psts_24->ht_fine_gain_code_a = ie_24->ht_fine_gain_code_a;
psts_24->l_dagc_a = ie_24->l_dagc_a;
psts_24->ht_dagc_a = ie_24->ht_dagc_a;
psts_24->pre_ibpwrdbm_a = ie_24->pre_ibpwrdbm_a;
psts_24->pre_wbpwrdbm_a = ie_24->pre_wbpwrdbm_a;
psts_24->l_ibpwrdbm_a = ie_24->l_ibpwrdbm_a;
psts_24->l_wbpwrdbm_a = ie_24->l_wbpwrdbm_a;
psts_24->ht_ibpwrdbm_a = ie_24->ht_ibpwrdbm_a;
psts_24->ht_wbpwrdbm_a = ie_24->ht_wbpwrdbm_a;
psts_24->l_dig_ibpwrdbm_a = ie_24->l_dig_ibpwrdbm_a;
psts_24->ht_dig_ibpwrdbm_a = ie_24->ht_dig_ibpwrdbm_a;
psts_24->lna_inpwrdbm_a = ie_24->lna_inpwrdbm_a;
psts_24->aci2sig_db = ie_24->aci2sig_db;
psts_24->sb5m_ratio_0 = ie_24->sb5m_ratio_0;
psts_24->sb5m_ratio_1 = ie_24->sb5m_ratio_1;
psts_24->sb5m_ratio_2 = ie_24->sb5m_ratio_2;
psts_24->sb5m_ratio_3 = ie_24->sb5m_ratio_3;
psts_24->aci_indicator_a = ie_24->aci_indicator_a;
psts_24->tia_shrink_indicator_a = ie_24->tia_shrink_indicator_a;
psts_24->pre_gain_code_tia_a = ie_24->pre_gain_code_tia_a;
psts_24->l_fine_gain_code_tia_a = ie_24->l_fine_gain_code_tia_a;
psts_24->ht_fine_gain_code_tia_a = ie_24->ht_fine_gain_code_tia_a;
psts_24->aci_det = ie_24->aci_det;
return true;
}
bool halbb_physts_ie_25(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_25_info *psts_25 = &physts->bb_physts_rslt_25_i;
struct physts_ie_25_info *ie_25 = NULL;
ie_25 = (struct physts_ie_25_info *)addr;
psts_25->ie_25_addr = addr;
psts_25->pre_agc_step_b = ie_25->pre_agc_step_b;
psts_25->l_fine_agc_step_b = ie_25->l_fine_agc_step_b;
psts_25->ht_fine_agc_step_b = ie_25->ht_fine_agc_step_b;
psts_25->pre_gain_code_b = ie_25->pre_gain_code_b;
psts_25->l_fine_gain_code_b = ie_25->l_fine_gain_code_b;
psts_25->ht_fine_gain_code_b = ie_25->ht_fine_gain_code_b;
psts_25->l_dagc_b = ie_25->l_dagc_b;
psts_25->ht_dagc_b = ie_25->ht_dagc_b;
psts_25->pre_ibpwrdbm_b = ie_25->pre_ibpwrdbm_b;
psts_25->pre_wbpwrdbm_b = ie_25->pre_wbpwrdbm_b;
psts_25->l_ibpwrdbm_b = ie_25->l_ibpwrdbm_b;
psts_25->l_wbpwrdbm_b = ie_25->l_wbpwrdbm_b;
psts_25->ht_ibpwrdbm_b = ie_25->ht_ibpwrdbm_b;
psts_25->ht_wbpwrdbm_b = ie_25->ht_wbpwrdbm_b;
psts_25->l_dig_ibpwrdbm_b = ie_25->l_dig_ibpwrdbm_b;
psts_25->ht_dig_ibpwrdbm_b = ie_25->ht_dig_ibpwrdbm_b;
psts_25->lna_inpwrdbm_b = ie_25->lna_inpwrdbm_b;
psts_25->aci2sig_db = ie_25->aci2sig_db;
psts_25->sb5m_ratio_0 = ie_25->sb5m_ratio_0;
psts_25->sb5m_ratio_1 = ie_25->sb5m_ratio_1;
psts_25->sb5m_ratio_2 = ie_25->sb5m_ratio_2;
psts_25->sb5m_ratio_3 = ie_25->sb5m_ratio_3;
psts_25->aci_indicator_b = ie_25->aci_indicator_b;
psts_25->tia_shrink_indicator_b = ie_25->tia_shrink_indicator_b;
psts_25->pre_gain_code_tia_b = ie_25->pre_gain_code_tia_b;
psts_25->l_fine_gain_code_tia_b = ie_25->l_fine_gain_code_tia_b;
psts_25->ht_fine_gain_code_tia_b = ie_25->ht_fine_gain_code_tia_b;
psts_25->aci_det = ie_25->aci_det;
return true;
}
bool halbb_physts_ie_26(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct physts_ie_26_info *ie_26 = NULL;
ie_26 = (struct physts_ie_26_info *)addr;
return true;
}
bool halbb_physts_ie_27(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct physts_ie_27_info *ie_27 = NULL;
ie_27 = (struct physts_ie_27_info *)addr;
return true;
}
bool halbb_physts_ie_28(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_28_info *psts_28 = &physts->bb_physts_rslt_28_i;
struct physts_ie_28_info *ie_28 = NULL;
ie_28 = (struct physts_ie_28_info *)addr;
psts_28->ie_28_addr = addr;
psts_28->ant_weight_a = (ie_28->ant_weight_a_m<<1) | ie_28->ant_weight_a_l;
psts_28->h3_real_a = ie_28->h3_real_a;
psts_28->h3_imag_a = ie_28->h3_imag_a;
psts_28->h4_real_a = ie_28->h4_real_a;
psts_28->h4_imag_a = ie_28->h4_imag_a;
psts_28->h5_real_a = ie_28->h5_real_a;
psts_28->h5_imag_a = ie_28->h5_imag_a;
psts_28->h6_real_a = ie_28->h6_real_a;
psts_28->h6_imag_a = ie_28->h6_imag_a;
psts_28->h7_real_a = ie_28->h7_real_a;
psts_28->h7_imag_a = ie_28->h7_imag_a;
psts_28->h8_real_a = ie_28->h8_real_a;
psts_28->h8_imag_a = ie_28->h8_imag_a;
psts_28->h9_real_a = ie_28->h9_real_a;
psts_28->h9_imag_a = ie_28->h9_imag_a;
psts_28->h10_real_a = ie_28->h10_real_a;
psts_28->h10_imag_a = ie_28->h10_imag_a;
psts_28->h11_real_a = ie_28->h11_real_a;
psts_28->h11_imag_a = ie_28->h11_imag_a;
psts_28->h12_real_a = ie_28->h12_real_a;
psts_28->h12_imag_a = ie_28->h12_imag_a;
psts_28->h13_real_a = ie_28->h13_real_a;
psts_28->h13_imag_a = ie_28->h13_imag_a;
psts_28->h14_real_a = ie_28->h14_real_a;
psts_28->h14_imag_a = ie_28->h14_imag_a;
psts_28->h15_real_a = ie_28->h15_real_a;
psts_28->h15_imag_a = ie_28->h15_imag_a;
psts_28->h16_real_a = ie_28->h16_real_a;
psts_28->h16_imag_a = ie_28->h16_imag_a;
psts_28->h17_real_a = ie_28->h17_real_a;
psts_28->h17_imag_a = ie_28->h17_imag_a;
return true;
}
bool halbb_physts_ie_29(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_29_info *psts_29 = &physts->bb_physts_rslt_29_i;
struct physts_ie_29_info *ie_29 = NULL;
ie_29 = (struct physts_ie_29_info *)addr;
psts_29->ie_29_addr = addr;
psts_29->ant_weight_b = (ie_29->ant_weight_b_m<<1) | ie_29->ant_weight_b_l;
psts_29->h3_real_b = ie_29->h3_real_b;
psts_29->h3_imag_b = ie_29->h3_imag_b;
psts_29->h4_real_b = ie_29->h4_real_b;
psts_29->h4_imag_b = ie_29->h4_imag_b;
psts_29->h5_real_b = ie_29->h5_real_b;
psts_29->h5_imag_b = ie_29->h5_imag_b;
psts_29->h6_real_b = ie_29->h6_real_b;
psts_29->h6_imag_b = ie_29->h6_imag_b;
psts_29->h7_real_b = ie_29->h7_real_b;
psts_29->h7_imag_b = ie_29->h7_imag_b;
psts_29->h8_real_b = ie_29->h8_real_b;
psts_29->h8_imag_b = ie_29->h8_imag_b;
psts_29->h9_real_b = ie_29->h9_real_b;
psts_29->h9_imag_b = ie_29->h9_imag_b;
psts_29->h10_real_b = ie_29->h10_real_b;
psts_29->h10_imag_b = ie_29->h10_imag_b;
psts_29->h11_real_b = ie_29->h11_real_b;
psts_29->h11_imag_b = ie_29->h11_imag_b;
psts_29->h12_real_b = ie_29->h12_real_b;
psts_29->h12_imag_b = ie_29->h12_imag_b;
psts_29->h13_real_b = ie_29->h13_real_b;
psts_29->h13_imag_b = ie_29->h13_imag_b;
psts_29->h14_real_b = ie_29->h14_real_b;
psts_29->h14_imag_b = ie_29->h14_imag_b;
psts_29->h15_real_b = ie_29->h15_real_b;
psts_29->h15_imag_b = ie_29->h15_imag_b;
psts_29->h16_real_b = ie_29->h16_real_b;
psts_29->h16_imag_b = ie_29->h16_imag_b;
psts_29->h17_real_b = ie_29->h17_real_b;
psts_29->h17_imag_b = ie_29->h17_imag_b;
return true;
}
bool halbb_physts_ie_30(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct physts_ie_30_info *ie_30 = NULL;
ie_30 = (struct physts_ie_30_info *)addr;
return true;
}
bool halbb_physts_ie_31(struct bb_info *bb,
u8 *addr,
u16 ie_length,
struct physts_rxd *desc)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct physts_ie_31_info *ie_31 = NULL;
ie_31 = (struct physts_ie_31_info *)addr;
return true;
}
void halbb_physts_rpt_gen(struct bb_info *bb, struct physts_result *rpt,
bool physts_rpt_valid, struct physts_rxd *desc,
bool is_cck_rate)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
struct bb_physts_rslt_0_info *psts_0 = &physts->bb_physts_rslt_0_i;
struct bb_physts_rslt_1_info *psts_1 = &physts->bb_physts_rslt_1_i;
u16 tmp_val16 = 0;
u8 i = 0;
rpt->physts_rpt_valid = physts_rpt_valid;
rpt->rssi_avg = psts_h->rssi_avg;
rpt->rssi[0] = psts_h->rssi[0];
rpt->rssi[1] = psts_h->rssi[1];
rpt->rssi[2] = psts_h->rssi[2];
rpt->rssi[3] = psts_h->rssi[3];
rpt->ie_map_type = psts_h->ie_map_type;
for (i = 0; i < 4; i++) {
if (psts_h->rssi[i] == 0)
continue;
tmp_val16 = SUBTRACT_TO_0((((u16)psts_h->rssi[i]) << 2), bb->bb_env_mntr_i.idle_pwr_physts);
rpt->snr_td[i] = GET_MA_VAL(tmp_val16, 3);
}
rpt->is_mu_pkt = (desc->is_su) ? 0 : 1; /*TBD*/
if (!physts_rpt_valid)
return;
if (!desc->is_to_self)
return;
if (is_cck_rate) {
rpt->ch_idx = bb->bb_ch_i.rf_central_ch_cfg;
rpt->rx_bw = CHANNEL_WIDTH_20;
rpt->rxsc = 0;
rpt->is_bf = 0;
rpt->snr_td_avg = SUBTRACT_TO_0((u16)psts_h->rssi_avg, psts_0->avg_idle_noise_pwr_cck);
rpt->snr_fd_avg = 0; /*HW not support*/
rpt->is_su = 1;
rpt->is_ldpc = 0;
rpt->is_stbc = 0;
} else {
rpt->ch_idx = psts_1->ch_idx;
rpt->rx_bw = psts_1->bw_idx;
rpt->rxsc = psts_1->rxsc;
rpt->is_bf = psts_1->is_bf;
rpt->snr_fd_avg = psts_1->snr_avg;
rpt->snr_td_avg = SUBTRACT_TO_0((u16)psts_h->rssi_avg, psts_1->avg_idle_noise_pwr);
rpt->is_su = psts_1->is_su;
rpt->is_ldpc = psts_1->is_ldpc;
rpt->is_stbc = psts_1->is_stbc;
for (i = 0; i < 4; i++) {
if (psts_h->rssi[i] == 0)
continue;
rpt->snr_fd[i] = (((rpt->snr_fd_avg << 1) + rpt->rssi_avg - rpt->rssi[i]) >> 1);
}
}
BB_DBG(bb, DBG_PHY_STS, "[RPT] rssi_u81=(%d){%d,%d,%d,%d} idle_pwr_physts_u83=%d\n",
rpt->rssi_avg, rpt->rssi[0], rpt->rssi[1], rpt->rssi[2], rpt->rssi[3],
bb->bb_env_mntr_i.idle_pwr_physts);
BB_DBG(bb, DBG_PHY_STS, "[RPT] snr_td=(%d){%d,%d,%d,%d}\n",
rpt->snr_td_avg, rpt->snr_td[0], rpt->snr_td[1], rpt->snr_td[2], rpt->snr_td[3]);
BB_DBG(bb, DBG_PHY_STS, "[RPT] snr_fd =(%d){%d,%d,%d,%d}\n",
rpt->snr_fd_avg, rpt->snr_fd[0], rpt->snr_fd[1], rpt->snr_fd[2], rpt->snr_fd[3]);
}
void halbb_physts_print(struct bb_info *bb, struct physts_rxd *desc,
u16 total_len, u8 *addr, u32 physts_bitmap)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_rslt_hdr_info *psts_h = &physts->bb_physts_rslt_hdr_i;
u8 i = 0, curr_ie = 0;
if (physts->physts_dump_mode == 0)
return;
if (!physts->show_phy_sts_all_pkt) {
if (!desc->is_to_self)
return;
}
if (physts->show_phy_sts_cnt >= physts->show_phy_sts_max_cnt)
return;
physts->show_phy_sts_cnt++;
BB_TRACE("[Dump_idx:%04d][%d: %s] len=%04d bitmap=0x%08x\n",
bb->bb_physts_i.physts_dump_idx,
psts_h->ie_map_type,
bb_physts_bitmap_type_t[psts_h->ie_map_type],
total_len, physts_bitmap);
bb->bb_physts_i.physts_dump_idx++;
if (bb->bb_physts_i.physts_dump_mode & BIT(0)) {
BB_TRACE("[HDR]\n");
halbb_print_buff_64(bb, addr, PHYSTS_HDR_LEN);
addr += PHYSTS_HDR_LEN;
total_len -= PHYSTS_HDR_LEN;
for (i = 0; i < IE_PHYSTS_LEN_ALL; i++) {
if (total_len < 8)
break;
curr_ie = *addr & 0x1f;
BB_TRACE("===[IE_%02d]===\n", curr_ie);
halbb_print_buff_64(bb, addr, physts->ie_len_curr[i]);
addr += physts->ie_len_curr[i];
if (total_len >= physts->ie_len_curr[i])
total_len -= physts->ie_len_curr[i];
}
BB_TRACE("----------------------------\n");
}
if (bb->bb_physts_i.physts_dump_mode & BIT(1)) {
halbb_print_rate_2_buff(bb, desc->data_rate, desc->gi_ltf, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_TRACE("is_to_self=%d, su=%d, user_num=%d, phy_idx=%d, total_len=%d\n",
desc->is_to_self, desc->is_su, desc->user_num, desc->phy_idx, total_len);
BB_TRACE("Rate= %s (0x%x-%x), macid_su=%d\n",
bb->dbg_buf, desc->data_rate, desc->gi_ltf, desc->macid_su);
if (desc->user_num >= 4)
return;
for (i = 0; i < desc->user_num; i++) {
BB_TRACE("[%d]bcn=%d, ctrl=%d, data=%d, mgnt=%d\n", i,
desc->user_i[i].is_bcn, desc->user_i[i].is_ctrl,
desc->user_i[i].is_data, desc->user_i[i].is_mgnt);
}
BB_TRACE("----------------------------\n");
halbb_physts_detail_dump(bb, physts_bitmap, 0xffffffff);
}
BB_TRACE("==============================================\n");
}
bool halbb_physts_parsing(struct bb_info *bb,
u8 *addr,
u16 physts_total_length,
struct physts_rxd *desc,
struct physts_result *bb_rpt)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
u8 physts_ie_len_tab[IE_PHYSTS_LEN_ALL] = {2, 4, 3, 3, 1, 1, 1, 1,
VAR_LENGTH, 1, VAR_LENGTH, 22, VAR_LENGTH, VAR_LENGTH, VAR_LENGTH, VAR_LENGTH,
VAR_LENGTH, VAR_LENGTH, 2, 3, VAR_LENGTH, VAR_LENGTH, VAR_LENGTH, 0,
3, 3, 3, 3, 4, 4, 4, 4}; /*Unit: 8Byte*/
enum bb_physts_hdr_t physts_hdr_t;
u32 physts_bitmap = 0;
u16 ie_len;
u16 acc_ie_len = 0;
u16 total_ie_len = physts_total_length - PHYSTS_HDR_LEN; /*Unit: Byte*/
u16 ie_length_hdr = 0;
u8 i = 0;
u8 curr_ie = 0xff;
u8 *addr_in_bkp = addr;
bool is_cck_rate = false;
bool is_valid = true;
#ifdef HALBB_DBCC_SUPPORT
#ifdef HALBB_DBCC_DVLP_FLAG
if (desc->phy_idx == HW_PHY_1)
return false;
#endif
bb = halbb_get_curr_bb_pointer(bb, desc->phy_idx);
//BB_DBG(bb, DBG_PHY_STS, "[%s] phy_idx=%d\n", __func__, bb->bb_phy_idx);
#endif
if (desc->is_su)
desc->macid_su = desc->user_i[0].macid;
physts->bb_physts_cnt_i.all_cnt++;
if (desc->is_to_self) {
physts->bb_physts_cnt_i.is_2_self_cnt++;
}
/*---[Physts header parsing]------------------------------------------*/
ie_length_hdr = halbb_physts_ie_hdr(bb, addr, desc);
addr += PHYSTS_HDR_LEN;
if ((ie_length_hdr << 3) != physts_total_length) {
physts->bb_physts_cnt_i.err_len_cnt++;
//BB_DBG(bb, DBG_PHY_STS, "len_hdr error\n");
is_valid = false;
//return false;
goto PARSING_END;
}
if (!desc->is_to_self && !physts->show_phy_sts_all_pkt) {
/*Only parsing Hdr if the packet is not "to_self"*/
is_valid = true;
goto PARSING_END;
}
if (total_ie_len == 0) {
is_valid = true;
goto PARSING_END;
}
halbb_rate_idx_parsor(bb, desc->data_rate, (enum rtw_gi_ltf)desc->gi_ltf, &physts->bb_rate_i);
is_cck_rate = halbb_is_cck_rate(bb, desc->data_rate);
/*---[Physts per IE parsing]------------------------------------------*/
for (i = 0; i < IE_PHYSTS_LEN_ALL; i++) {
curr_ie = *addr & 0x1f;
if (physts_bitmap & BIT(curr_ie)) {
is_valid = false;
break;
}
if (physts_ie_len_tab[curr_ie] != VAR_LENGTH) {
physts_hdr_t = HDR_TYPE1;
ie_len = (u16)(physts_ie_len_tab[curr_ie] << 3); /*8-byte to byte*/
} else {
physts_hdr_t = HDR_TYPE2;
ie_len = (u16)((((*(addr + 1) & 0xf) << 3) | ((*addr & 0xe0) >> 5)) << 3);
}
if (curr_ie == IE00_CMN_CCK) {
halbb_physts_ie_00(bb, addr, ie_len, desc);
} else if (curr_ie == IE01_CMN_OFDM) {
halbb_physts_ie_01(bb, addr, ie_len, desc);
} else if (curr_ie == IE02_CMN_EXT_AX) {
halbb_physts_ie_02(bb, addr, ie_len, desc);
} else if (curr_ie == IE03_CMN_EXT_SEG_1) {
halbb_physts_ie_03(bb, addr, ie_len, desc);
} else if (curr_ie >= IE04_CMN_EXT_PATH_A &&
curr_ie <= IE07_CMN_EXT_PATH_D) {
halbb_physts_ie_04_07(bb, curr_ie, addr, ie_len, desc);
} else if (curr_ie == IE08_FTR_CH) {
halbb_physts_ie_08(bb, addr, ie_len, desc);
} else if (curr_ie == IE09_FTR_PLCP_0) {
halbb_physts_ie_09(bb, addr, ie_len, desc);
} else if (curr_ie == IE10_FTR_PLCP_EXT) {
halbb_physts_ie_10(bb, addr, ie_len, desc);
} else if (curr_ie == IE11_FTR_PLCP_HISTOGRAM) {
halbb_physts_ie_11(bb, addr, ie_len, desc);
} else if (curr_ie == IE12_MU_EIGEN_INFO) {
halbb_physts_ie_12(bb, addr, ie_len, desc);
} else if (curr_ie == IE13_DL_MU_DEF) {
halbb_physts_ie_13(bb, addr, ie_len, desc);
} else if (curr_ie == IE14_TB_UL_CQI) {
halbb_physts_ie_14(bb, addr, ie_len, desc);
} else if (curr_ie == IE15_TB_UL_DEF) {
halbb_physts_ie_15(bb, addr, ie_len, desc);
} else if (curr_ie == IE17_TB_UL_CTRL) {
halbb_physts_ie_17(bb, addr, ie_len, desc);
} else if (curr_ie == IE18_DBG_OFDM_FD_CMN) {
halbb_physts_ie_18(bb, addr, ie_len, desc);
} else if (curr_ie == IE19_DBG_OFDM_TD_CMN) {
halbb_physts_ie_19(bb, addr, ie_len, desc);
} else if (curr_ie == IE20_DBG_OFDM_FD_USER_SEG_0) {
halbb_physts_ie_20(bb, addr, ie_len, desc);
} else if (curr_ie == IE21_DBG_OFDM_FD_USER_SEG_1) {
halbb_physts_ie_21(bb, addr, ie_len, desc);
} else if (curr_ie == IE22_DBG_OFDM_FD_USER_AGC) {
halbb_physts_ie_22(bb, addr, ie_len, desc);
} else if (curr_ie == IE24_DBG_OFDM_TD_PATH_A) {
halbb_physts_ie_24(bb, addr, ie_len, desc);
} else if (curr_ie == IE25_DBG_OFDM_TD_PATH_B) {
halbb_physts_ie_25(bb, addr, ie_len, desc);
} else if (curr_ie == IE26_DBG_OFDM_TD_PATH_C) {
halbb_physts_ie_26(bb, addr, ie_len, desc);
} else if (curr_ie == IE27_DBG_OFDM_TD_PATH_D) {
halbb_physts_ie_27(bb, addr, ie_len, desc);
} else if (curr_ie == IE28_DBG_CCK_PATH_A) {
halbb_physts_ie_28(bb, addr, ie_len, desc);
} else if (curr_ie == IE29_DBG_CCK_PATH_B) {
halbb_physts_ie_29(bb, addr, ie_len, desc);
} else if (curr_ie == IE30_DBG_CCK_PATH_C) {
halbb_physts_ie_30(bb, addr, ie_len, desc);
} else if (curr_ie == IE31_DBG_CCK_PATH_D) {
halbb_physts_ie_31(bb, addr, ie_len, desc);
} else {
break;
}
physts->ie_len_curr[i] = ie_len;
addr += ie_len;
acc_ie_len += ie_len;
physts_bitmap |= BIT(curr_ie);
BB_DBG(bb, DBG_PHY_STS, "IE=%d, Hdr_type=%d, len=%d, acc_ie_len=%d\n",
curr_ie, physts_hdr_t, ie_len, acc_ie_len);
if (acc_ie_len == total_ie_len) {
is_valid = true;
physts->bb_physts_cnt_i.ok_ie_cnt++;
break;
} else if (acc_ie_len > total_ie_len) {
is_valid = false;
physts->bb_physts_cnt_i.err_ie_cnt++;
break;
}
}
BB_DBG(bb, DBG_PHY_STS, "[%d]Parsing_OK = %d, bitmap=0x%x\n",
physts->bb_physts_cnt_i.all_cnt, is_valid, physts_bitmap);
/*===================================================================*/
PARSING_END:
halbb_physts_rpt_gen(bb, bb_rpt, is_valid, desc, is_cck_rate);
physts->is_valid = is_valid;
if (!is_valid)
return false;
if (desc->is_to_self) {
physts->physts_bitmap_recv = physts_bitmap;
halbb_cmn_rpt(bb, desc);
#ifdef HALBB_CFO_TRK_SUPPORT
halbb_parsing_cfo(bb, physts_bitmap, desc);
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
halbb_antdiv_phy_sts(bb);
#endif
}
halbb_physts_print(bb, desc, physts_total_length, addr_in_bkp, physts_bitmap);
return true;
}
void
halbb_phy_sts_manual_trig(struct bb_info *bb, enum bb_mode_type mode, u8 ss)
{
struct physts_rxd rxdesc = {0};
struct physts_result bb_rpt = {0};
u8 i = 0;
u8 rate_tmp = 0;
bb->u8_dummy++;
BB_DBG(bb, DBG_PHY_STS, "[%s]\n", __func__);
if (ss == 0)
ss = 1;
else if (ss >= 2)
ss= 2;
if (mode == BB_LEGACY_MODE) {
rate_tmp = bb->u8_dummy % HE_VHT_NUM_MCS;
rxdesc.data_rate = rate_tmp;
} else if (mode == BB_HT_MODE) {
rate_tmp = bb->u8_dummy % HT_NUM_MCS;
rate_tmp += (ss - 1) * 8;
rxdesc.data_rate = BB_HT_MCS(rate_tmp);
} else if (mode == BB_VHT_MODE) {
rate_tmp = bb->u8_dummy % HE_VHT_NUM_MCS;
rxdesc.data_rate = BB_VHT_MCS(ss, rate_tmp);
} else if (mode == BB_HE_MODE) {
rate_tmp = bb->u8_dummy % HE_VHT_NUM_MCS;
rxdesc.data_rate = BB_HE_MCS(ss, rate_tmp);
}
BB_DBG(bb, DBG_PHY_STS, "rate = %d\n", rxdesc.data_rate);
rxdesc.gi_ltf = 0;
rxdesc.is_su = 1;
rxdesc.macid_su = 0;
rxdesc.user_num = 0;
rxdesc.is_to_self = 1;
for (i = 0; i < rxdesc.user_num; i++) {
rxdesc.user_i[i].macid = 0;
rxdesc.user_i[i].is_data = 1;
rxdesc.user_i[i].is_ctrl = 0;
rxdesc.user_i[i].is_mgnt = 0;
rxdesc.user_i[i].is_bcn = 0;
}
halbb_physts_parsing(bb, (u8 *)phy_sts_dbg, sizeof(phy_sts_dbg), &rxdesc, &bb_rpt);
}
void halbb_physts_watchdog(struct bb_info *bb)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
if (cmn_rpt->bb_pkt_cnt_mu_i.pkt_cnt_all != 0)
cmn_rpt->consec_idle_prd_mu = 0;
else
cmn_rpt->consec_idle_prd_mu++;
BB_DBG(bb, DBG_COMMON_FLOW, "su_cnt=%d, mu_cnt=%d\n",
cmn_rpt->bb_pkt_cnt_su_i.pkt_cnt_all,
cmn_rpt->bb_pkt_cnt_mu_i.pkt_cnt_all);
/*[Phy-sts control]*/
physts->show_phy_sts_cnt = 0;
physts->bb_physts_cnt_i.all_cnt = 0;
physts->bb_physts_cnt_i.is_2_self_cnt = 0;
physts->bb_physts_cnt_i.ok_ie_cnt = 0;
physts->bb_physts_cnt_i.err_ie_cnt = 0;
physts->bb_physts_cnt_i.err_len_cnt = 0;
}
void halbb_physts_parsing_init(struct bb_info *bb)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i;
u32 u32_tmp = 0;
u32 mask_tmp = 0;
u8 i = 0;
if(phl_is_mp_mode(bb->phl_com))
halbb_physts_brk_fail_rpt_en(bb, true, bb->bb_phy_idx);
else
halbb_physts_brk_fail_rpt_en(bb, false, bb->bb_phy_idx);
/*Enable IE Pages 9*/
for (i = 0; i < PHYSTS_BITMAP_NUM; i++) {
u32_tmp = halbb_physts_ie_bitmap_get(bb, i);
if (i >= CCK_PKT) {
u32_tmp |= BIT(IE09_FTR_PLCP_0);
halbb_physts_ie_bitmap_set(bb, i, u32_tmp);
u32_tmp = halbb_physts_ie_bitmap_get(bb, i);
}
physts->bitmap_type[i] = u32_tmp;
}
/*[MP Mode] Enable extend path info A~D*/
if(phl_is_mp_mode(bb->phl_com)) {
mask_tmp = (u32)halbb_gen_mask(IE04_CMN_EXT_PATH_A + bb->num_rf_path - 1, IE04_CMN_EXT_PATH_A);
//BB_DBG(bb, DBG_DBG_API, "mask_tmp = 0x%x\n", mask_tmp);
for (i = 0; i < PHYSTS_BITMAP_NUM; i++) {
u32_tmp = halbb_physts_ie_bitmap_get(bb, i);
if (i >= LEGACY_OFDM_PKT) {
u32_tmp |= mask_tmp;
bb->num_rf_path;
halbb_physts_ie_bitmap_set(bb, i, u32_tmp);
u32_tmp = halbb_physts_ie_bitmap_get(bb, i);
}
physts->bitmap_type[i] = u32_tmp;
}
}
halbb_physts_ie_bitmap_en(bb, HE_MU, IE13_DL_MU_DEF, true);
halbb_physts_ie_bitmap_en(bb, VHT_MU, IE13_DL_MU_DEF, true);
physts->show_phy_sts_all_pkt = false;
physts->show_phy_sts_max_cnt = 5;
physts->show_phy_sts_cnt = 0;
}
void halbb_physts_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i;
u32 val[10] = {0};
u32 u32_tmp = 0;
u8 ie11_ever_used = 0;
u8 i;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dump {0:dis, 1: raw data, 2: msg, 3: raw + msg}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"filter {max_num_per_2s} {not_2_self_pkt_en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"brk_rpt_en {en} :[enable physts of brk&fail pkt]\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bitmap show\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"bitmap set {idx, all, or} {hex_val}\n");
return;
}
if (_os_strcmp(input[1], "bitmap") == 0) {
if (_os_strcmp(input[2], "show") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Show all IE BITMAP\n");
} else if (_os_strcmp(input[2], "set") == 0) {
HALBB_SCAN(input[4], DCMD_HEX, &val[1]);
if (_os_strcmp(input[3], "all") == 0) {
for (i = 0; i < PHYSTS_BITMAP_NUM; i++)
halbb_physts_ie_bitmap_set(bb, i, val[1]);
} else if (_os_strcmp(input[3], "or") == 0) {
for (i = 0; i < PHYSTS_BITMAP_NUM; i++) {
u32_tmp = val[1] | halbb_physts_ie_bitmap_get(bb, i);
halbb_physts_ie_bitmap_set(bb, i, u32_tmp);
}
} else {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
halbb_physts_ie_bitmap_set(bb, val[0], val[1]);
}
}
for (i = 0; i < PHYSTS_BITMAP_NUM; i++) {
u32_tmp = halbb_physts_ie_bitmap_get(bb, i);
if (physts->bitmap_type[i] != u32_tmp) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Warning] Mismatch drv_para=0x%08x\n",
physts->bitmap_type[i]);
}
if (ie11_ever_used == 0)
ie11_ever_used = (u32_tmp & BIT(11)) ? 1 : 0;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"IE_BITMAP[%02d]=0x%08x : %s\n",
i, u32_tmp, bb_physts_bitmap_type_t[i]);
}
/*IE-11 HW enable*/
halbb_set_reg(bb, cr->plcp_hist, cr->plcp_hist_m, ie11_ever_used);
} else if (_os_strcmp(input[1], "filter") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
bb->bb_physts_i.show_phy_sts_max_cnt = (u16)val[0];
bb->bb_physts_i.show_phy_sts_all_pkt = (bool)val[1];
physts->show_phy_sts_cnt = 0;
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"show_max_num=%d, show_not2self_pkt_en=%d\n\n",
bb->bb_physts_i.show_phy_sts_max_cnt,
bb->bb_physts_i.show_phy_sts_all_pkt);
} else if (_os_strcmp(input[1], "dump") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
bb->bb_physts_i.physts_dump_idx = 0;
bb->bb_physts_i.physts_dump_mode = (u8)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"physts_dump_mode=%d\n", bb->bb_physts_i.physts_dump_mode);
if (bb->bb_physts_i.physts_dump_mode != 0)
halbb_physts_td_time_rpt_en(bb, true, bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "trig") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
halbb_phy_sts_manual_trig(bb, (enum bb_mode_type)val[0], (u8)val[1]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Physts manual trigger\n");
} else if (_os_strcmp(input[1], "brk_rpt_en") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
halbb_physts_brk_fail_rpt_en(bb, (bool)val[0], bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"brk_rpt_en = %d\n",val[0]);
}
}
void halbb_cr_cfg_physts_init(struct bb_info *bb)
{
struct bb_physts_info *physts = &bb->bb_physts_i;
struct bb_physts_cr_info *cr = &physts->bb_physts_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->plcp_hist = PLCP_HISTOGRAM_EN_A;
cr->plcp_hist_m = PLCP_HISTOGRAM_EN_A_M;
cr->bitmap_search_fail = PHY_STS_BITMAP_SEARCH_FAIL_A;
cr->period_cnt_en = PERIOD_CNT_EN_A;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->plcp_hist = PLCP_HISTOGRAM_EN_C;
cr->plcp_hist_m = PLCP_HISTOGRAM_EN_C_M;
cr->bitmap_search_fail = PHY_STS_BITMAP_SEARCH_FAIL_C;
cr->period_cnt_en = PERIOD_CNT_EN_C;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_physts.c
|
C
|
agpl-3.0
| 89,857
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_PHYSTS_H__
#define __HALBB_PHYSTS_H__
#define VAR_LENGTH 0xff
#define TRANS_2_RSSI(X) (X >> 1)
#define PHYSTS_HDR_LEN 8
#define TB_USER_MAX 4
#define MU_USER_MAX 4
#define PSTS_USR(x,y) psts_##x_usr_##y
#define IE11_PKT_INFO_LEN 10
enum bb_physts_bw_info{
PSTS_BW5 = 0,
PSTS_BW10 = 1,
PSTS_BW20 = 2,
PSTS_BW40 = 3,
PSTS_BW80 = 4,
PSTS_BW160 = 5,
PSTS_BW80_80 = 6,
PSTS_BW_MAX
};
enum bb_physts_ie_t {
IE00_CMN_CCK = 0,
IE01_CMN_OFDM = 1,
IE02_CMN_EXT_AX = 2,
IE03_CMN_EXT_SEG_1 = 3,
IE04_CMN_EXT_PATH_A = 4,
IE05_CMN_EXT_PATH_B = 5,
IE06_CMN_EXT_PATH_C = 6,
IE07_CMN_EXT_PATH_D = 7,
IE08_FTR_CH = 8,
IE09_FTR_PLCP_0 = 9,
IE10_FTR_PLCP_EXT = 10,
IE11_FTR_PLCP_HISTOGRAM = 11,
IE12_MU_EIGEN_INFO = 12,
IE13_DL_MU_DEF = 13,
IE14_TB_UL_CQI = 14,
IE15_TB_UL_DEF = 15,
IE16_RSVD16 = 16,
IE17_TB_UL_CTRL = 17,
IE18_DBG_OFDM_FD_CMN = 18,
IE19_DBG_OFDM_TD_CMN = 19,
IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
IE22_DBG_OFDM_FD_USER_AGC = 22,
IE23_RSVD23 = 23,
IE24_DBG_OFDM_TD_PATH_A = 24,
IE25_DBG_OFDM_TD_PATH_B = 25,
IE26_DBG_OFDM_TD_PATH_C = 26,
IE27_DBG_OFDM_TD_PATH_D = 27,
IE28_DBG_CCK_PATH_A = 28,
IE29_DBG_CCK_PATH_B = 29,
IE30_DBG_CCK_PATH_C = 30,
IE31_DBG_CCK_PATH_D = 31,
IE_PHYSTS_LEN_ALL = 32
};
struct bb_info;
static const char bb_physts_bitmap_type_t[][9] = {
"SRH_FAIL",
"BRK_BY_TX",
"CCA_SPF",
"OFDM_BRK",
"CCK_BRK",
"DLMU_SPF",
"HE_MU",
"VHT_MU",
"TB_SPF",
"N/A",
"TB",
"CCK",
"LEGACY",
"HT",
"VHT",
"HE",
};
struct bb_physts_rslt_hdr_info {
u8 rssi[4];
u8 rssi_avg;
enum bb_physts_bitmap_t ie_map_type;
};
struct bb_physts_rslt_0_info {
u8 *ie_00_addr;
u8 rx_path_en_cck;
s16 cfo_avg_cck; /*S(12,2), -512~+511.75 kHz*/
u8 evm_avg_cck;
u8 avg_idle_noise_pwr_cck; /*u(8,1)*/
u8 pop_idx_cck;
u16 rpl; /*U(9,2)*/
};
struct bb_physts_rslt_1_info {
u8 *ie_01_addr;
u8 rx_path_en;
s16 cfo_avg; /*S(12,2), -512~+511.75 kHz, FD tracking CFO*/
s16 cfo_pab_avg; /*S(12,2), -512~+511.75 kHz, preamble CFO*/
u8 evm_max;
u8 evm_min;
u8 snr_avg;
u8 cn_avg;
u8 avg_idle_noise_pwr; /*u(8,1)*/
u8 pop_idx;
u8 rxsc;
u8 ch_idx;
u8 rpl_fd;
enum channel_width bw_idx;
bool is_su; /*if (not MU && not OFDMA), is_su = 1*/
bool is_ldpc;
bool is_ndp;
bool is_stbc;
bool grant_bt;
bool is_awgn;
bool is_bf;
};
struct bb_physts_rslt_2_info {
u8 *ie_02_addr;
u8 max_nsts;
u8 ltf_type;
u8 gi;
s32 c_cfo_i;
u8 rx_info_1;
u8 rx_state_feq;
s32 c_cfo_q;
u8 est_cmped_phase;
u8 pkt_extension;
s32 f_cfo_i;
u8 n_ltf;
u16 n_sym;
s32 f_cfo_q;
bool midamble;
bool is_mu_mimo;
bool is_dl_ofdma;
bool is_dcm;
bool is_doppler;
};
struct bb_physts_rslt_3_info {
u8 *ie_03_addr;
u8 avg_cn_seg1;
u8 sigval_below_th_tone_cnt_seg1;
u8 cn_excess_th_tone_cnt_seg1;
u16 avg_cfo_seg1;
u16 avg_cfo_premb_seg1;
u8 est_cmped_phase_seg1;
u8 avg_snr_seg1;
u32 c_cfo_i_seg1;
u32 c_cfo_q_seg1;
u32 f_cfo_i_seg1;
u32 f_cfo_q_seg1;
u8 ch_idx_seg1;
u8 evm_max_seg1;
u8 evm_min_seg1;
};
struct bb_physts_rslt_4_to_7_info {
u8 *ie_04_07_addr;
u8 ant_idx;
s8 sig_val_y;
u8 rf_gain_idx;
u8 snr_lgy;
u8 evm_ss_y;
u8 td_ant_weight;
s8 dc_est_re;
s8 dc_est_im;
bool rf_tia_gain_idx;
bool tia_shrink_indicator;
//bool ant_idx_0_msb;
};
struct bb_physts_rslt_8_info {
u8 *ie_08_addr;
u8 rxsc;
u8 n_rx;
u8 n_sts;
u16 ch_info_len;
u8 evm_1_sts;
u8 evm_2_sts;
u8 avg_idle_noise_pwr;
bool is_ch_info_len_valid;
};
struct bb_physts_rslt_9_info {
u8 *ie_09_addr;
u32 l_sig;
u32 sig_a1;
u16 sig_a2;
};
struct bb_physts_rslt_10_info {
u8 *ie_10_addr;
u8 tmp;
};
struct bb_physts_rslt_11_info {
u8 *ie_11_addr;
u32 l_sig;
u32 sig_a1;
u16 sig_a2;
u16 time_stamp;
u8 rx_pkt_info_idx;
u8 tx_pkt_info_idx;
};
struct bb_physts_user_info_ie_12{
u8 sig_val_ss0_seg_cr_user_i;
u8 sig_val_ss1_seg_cr_user_i;
u8 sig_val_ss2_seg_cr_user_i;
u8 sig_val_ss3_seg_cr_user_i;
u8 sig_bad_tone_cnt_seg_cr_user_i;
u8 cn_bad_tone_cnt_seg_cr_user_i;
};
struct bb_physts_rslt_12_info {
u8 *ie_12_addr;
u8 n_user;
struct bb_physts_user_info_ie_12 bb_physts_uer_info[MU_USER_MAX];
};
struct bb_physts_user_info_ie_13{
u8 is_bf;
u8 fec_type;
u8 mcs;
u8 pilot_exist;
u8 n_sts;
u8 n_sts_ru_total;
u8 is_awgn;
u8 is_mu_mimo;
u8 pdp_he_ltf_and_gi_type;
u8 start_sts;
u8 rx_evm_max_seg_cr;
u8 rx_evm_min_seg_cr;
s8 snr;
u8 ru_alloc;
u8 is_dcm;
u8 avg_cn_seg_cr;
u16 sta_id;
};
struct bb_physts_rslt_13_info {
u8 *ie_13_addr;
u8 n_user;
struct bb_physts_user_info_ie_13 bb_physts_uer_info[MU_USER_MAX];
u8 n_not_sup_sta;
};
struct bb_physts_user_info_ie_14{
u8 cqi_bitmap_ul_tb;
u8 cqi_raw_len_ul_tb;
u8 *cqi_raw_ul_tb_addr;
};
struct bb_physts_rslt_14_info {
u8 *ie_14_addr;
u8 rxinfo_ndp_en;
u8 n_user;
struct bb_physts_user_info_ie_14 bb_physts_uer_info[MU_USER_MAX];
};
struct bb_physts_user_info_ie_15{
/* 64bit cmn_info */
u8 mcs;
u8 fec_type;
u8 is_bf;
u8 n_sts_ru_total;
u8 n_sts;
u8 pilot_exist;
u8 start_sts;
u8 pdp_he_ltf_and_gi_type;
u8 is_mu_mimo;
u8 is_awgn;
u8 rx_evm_max_seg_cr;
u8 rx_evm_min_seg_cr;
s8 snr;
u8 ru_alloc;
u8 avg_cn_seg_cr;
u8 is_dcm;
/* others */
u8 uid;
s16 avg_cfo_seg0;
u16 rssi_m_ul_tb;
};
struct bb_physts_rslt_15_info {
u8 *ie_15_addr;
u8 n_user;
struct bb_physts_user_info_ie_15 bb_physts_uer_info[MU_USER_MAX];
};
struct bb_physts_rslt_16_info {
u8 *ie_16_addr;
u8 tmp;
};
struct bb_physts_cmn_info_ie_17 {
bool stbc_en;
bool ldpc_extra;
bool doppler_en;
bool midamle_mode;
u8 gi_type;
u8 ltf_type;
u8 n_ltf;
u8 n_sym;
u8 pe_idx;
u8 pre_fec_factor;
u8 n_usr;
bool mumimo_ltf_mode_en;
bool ndp;
u8 pri_exp_rssi_dbm;
u8 dbw_idx;
u8 rsvd;
u16 rxtime;
};
struct bb_physts_user_info_ie_17 {
u8 u_id;
u8 ru_alloc;
u8 n_sts_ru_tot;
u8 rsvd1;
u8 strt_sts;
u8 n_sts;
bool fec_type;
u8 mcs;
u8 rsvd2;
bool dcm_en;
u8 rsvd3;
};
struct bb_physts_rslt_17_info {
u8 *ie_17_addr;
u8 n_user;
struct bb_physts_cmn_info_ie_17 bb_physts_cmn_info;
struct bb_physts_user_info_ie_17 bb_physts_uer_info[MU_USER_MAX];
};
struct bb_physts_rslt_18_info {
u8 *ie_18_addr;
u16 rx_time;
u8 ch_len_lgcy_seg0;
u8 bw_det_seg0;
u8 snr_idx_lgcy_seg0;
u8 pdp_idx_lgcy_seg0;
u16 pfd_flow;
u8 ch_len_lgcy_seg1;
u8 bw_det_seg1;
u8 snr_idx_lgcy_seg1;
u8 pdp_idx_lgcy_seg1;
bool is_seg1_exist;
};
struct bb_physts_rslt_19_info {
u8 *ie_19_addr;
u8 ppdu_inpwrdbm_p20;
u8 ppdu_inpwrdbm_s20;
u8 ppdu_inpwrdbm_s40;
u8 ppdu_inpwrdbm_s80;
u8 ppdu_inpwrdbm_per20_1;
u8 ppdu_inpwrdbm_per20_2;
u8 ppdu_inpwrdbm_per20_3;
u8 ppdu_inpwrdbm_per20_4;
u8 edcca_rpt_cnt_p20;
u8 edcca_rpt_p20_max;
u8 edcca_rpt_p20_min;
u8 edcca_total_smp_cnt;
u8 edcca_rpt_cnt_s80;
u8 edcca_rpt_cnt_s80_max;
u8 edcca_rpt_cnt_s80_min;
u8 pop_reg_pwr;
u8 pop_trig_pwr;
u8 early_drop_pwr;
bool tx_over_flow;
};
struct bb_physts_user_info_20 {
u8 ch_smo_n_block_lgcy_sub_0_seg_0;
u8 ch_smo_n_block_lgcy_sub_1_seg_0;
u8 ch_smo_n_block_lgcy_sub_2_seg_0;
u8 ch_smo_n_block_lgcy_sub_3_seg_0;
u8 ch_smo_en_lgcy_seg_0;
u8 ch_smo_en_non_lgcy_seg_0;
u8 ch_smo_n_block_non_lgcy_seg_0;
u8 ch_len_non_lgcy_sts_0_seg_0;
u8 ch_len_non_lgcy_sts_1_seg_0;
u8 ch_len_non_lgcy_sts_2_seg_0;
u8 ch_len_non_lgcy_sts_3_seg_0;
u8 snr_idx_non_lgy_sts_0_seg_0;
u8 snr_idx_non_lgy_sts_1_seg_0;
u8 snr_idx_non_lgy_sts_2_seg_0;
u8 snr_idx_non_lgy_sts_3_seg_0;
u8 pdp_idx_non_lgcy_sts_0_seg_0;
u8 pdp_idx_non_lgcy_sts_1_seg_0;
u8 pdp_idx_non_lgcy_sts_2_seg_0;
u8 pdp_idx_non_lgcy_sts_3_seg_0;
u8 snr_non_lgy_sts_0_seg_0;
u8 snr_non_lgy_sts_1_seg_0;
u8 snr_non_lgy_sts_2_seg_0;
u8 snr_non_lgy_sts_3_seg_0;
u8 evm_ss_0_seg_0;
u8 evm_ss_1_seg_0;
u8 evm_ss_2_seg_0;
u8 evm_ss_3_seg_0;
};
struct bb_physts_rslt_20_info {
u8 *ie_20_addr;
u8 n_user;
struct bb_physts_user_info_20 bb_physts_usr_info[MU_USER_MAX];
};
struct bb_physts_user_info_21 {
u8 ch_smo_n_block_lgcy_sub_0_seg_1;
u8 ch_smo_n_block_lgcy_sub_1_seg_1;
u8 ch_smo_n_block_lgcy_sub_2_seg_1;
u8 ch_smo_n_block_lgcy_sub_3_seg_1;
u8 ch_smo_en_lgcy_seg_1;
u8 ch_smo_en_non_lgcy_seg_1;
u8 ch_smo_n_block_non_lgcy_seg_1;
u8 ch_len_non_lgcy_sts_0_seg_1;
u8 ch_len_non_lgcy_sts_1_seg_1;
u8 ch_len_non_lgcy_sts_2_seg_1;
u8 ch_len_non_lgcy_sts_3_seg_1;
u8 snr_idx_non_lgy_sts_0_seg_1;
u8 snr_idx_non_lgy_sts_1_seg_1;
u8 snr_idx_non_lgy_sts_2_seg_1;
u8 snr_idx_non_lgy_sts_3_seg_1;
u8 pdp_idx_non_lgcy_sts_0_seg_1;
u8 pdp_idx_non_lgcy_sts_1_seg_1;
u8 pdp_idx_non_lgcy_sts_2_seg_1;
u8 pdp_idx_non_lgcy_sts_3_seg_1;
u8 snr_non_lgy_sts_0_seg_1;
u8 snr_non_lgy_sts_1_seg_1;
u8 snr_non_lgy_sts_2_seg_1;
u8 snr_non_lgy_sts_3_seg_1;
u8 evm_ss_0_seg_1;
u8 evm_ss_1_seg_1;
u8 evm_ss_2_seg_1;
u8 evm_ss_3_seg_1;
};
struct bb_physts_rslt_21_info {
u8 *ie_21_addr;
u8 n_user;
struct bb_physts_user_info_21 bb_physts_usr_info[MU_USER_MAX];
};
struct bb_physts_rslt_22_info {
u8 *ie_22_addr;
u8 tmp;
};
struct bb_physts_rslt_23_info {
u8 *ie_23_addr;
u8 tmp;
};
struct bb_physts_rslt_24_info {
u8 *ie_24_addr;
u8 pre_agc_step_a;
u8 l_fine_agc_step_a;
u8 ht_fine_agc_step_a;
u8 pre_gain_code_a;
u8 l_fine_gain_code_a;
u8 ht_fine_gain_code_a;
u8 l_dagc_a;
u8 ht_dagc_a;
u8 pre_ibpwrdbm_a;
u8 pre_wbpwrdbm_a;
u8 l_ibpwrdbm_a;
u8 l_wbpwrdbm_a;
u8 ht_ibpwrdbm_a;
u8 ht_wbpwrdbm_a;
u8 l_dig_ibpwrdbm_a;
u8 ht_dig_ibpwrdbm_a;
u8 lna_inpwrdbm_a;
u8 aci2sig_db;
u8 sb5m_ratio_0;
u8 sb5m_ratio_1;
u8 sb5m_ratio_2;
u8 sb5m_ratio_3;
bool aci_indicator_a;
bool tia_shrink_indicator_a;
bool pre_gain_code_tia_a;
bool l_fine_gain_code_tia_a;
bool ht_fine_gain_code_tia_a;
bool aci_det;
};
struct bb_physts_rslt_25_info {
u8 *ie_25_addr;
u8 pre_agc_step_b;
u8 l_fine_agc_step_b;
u8 ht_fine_agc_step_b;
u8 pre_gain_code_b;
u8 l_fine_gain_code_b;
u8 ht_fine_gain_code_b;
u8 l_dagc_b;
u8 ht_dagc_b;
u8 pre_ibpwrdbm_b;
u8 pre_wbpwrdbm_b;
u8 l_ibpwrdbm_b;
u8 l_wbpwrdbm_b;
u8 ht_ibpwrdbm_b;
u8 ht_wbpwrdbm_b;
u8 l_dig_ibpwrdbm_b;
u8 ht_dig_ibpwrdbm_b;
u8 lna_inpwrdbm_b;
u8 aci2sig_db;
u8 sb5m_ratio_0;
u8 sb5m_ratio_1;
u8 sb5m_ratio_2;
u8 sb5m_ratio_3;
bool aci_indicator_b;
bool tia_shrink_indicator_b;
bool pre_gain_code_tia_b;
bool l_fine_gain_code_tia_b;
bool ht_fine_gain_code_tia_b;
bool aci_det;
};
struct bb_physts_rslt_26_info {
u8 *ie_26_addr;
u8 tmp;
};
struct bb_physts_rslt_27_info {
u8 *ie_27_addr;
u8 tmp;
};
struct bb_physts_rslt_28_info {
u8 *ie_28_addr;
u16 ant_weight_a;
u8 h3_real_a;
u8 h3_imag_a;
u8 h4_real_a;
u8 h4_imag_a;
u8 h5_real_a;
u8 h5_imag_a;
u8 h6_real_a;
u8 h6_imag_a;
u8 h7_real_a;
u8 h7_imag_a;
u8 h8_real_a;
u8 h8_imag_a;
u8 h9_real_a;
u8 h9_imag_a;
u8 h10_real_a;
u8 h10_imag_a;
u8 h11_real_a;
u8 h11_imag_a;
u8 h12_real_a;
u8 h12_imag_a;
u8 h13_real_a;
u8 h13_imag_a;
u8 h14_real_a;
u8 h14_imag_a;
u8 h15_real_a;
u8 h15_imag_a;
u8 h16_real_a;
u8 h16_imag_a;
u8 h17_real_a;
u8 h17_imag_a;
};
struct bb_physts_rslt_29_info {
u8 *ie_29_addr;
u16 ant_weight_b;
u8 h3_real_b;
u8 h3_imag_b;
u8 h4_real_b;
u8 h4_imag_b;
u8 h5_real_b;
u8 h5_imag_b;
u8 h6_real_b;
u8 h6_imag_b;
u8 h7_real_b;
u8 h7_imag_b;
u8 h8_real_b;
u8 h8_imag_b;
u8 h9_real_b;
u8 h9_imag_b;
u8 h10_real_b;
u8 h10_imag_b;
u8 h11_real_b;
u8 h11_imag_b;
u8 h12_real_b;
u8 h12_imag_b;
u8 h13_real_b;
u8 h13_imag_b;
u8 h14_real_b;
u8 h14_imag_b;
u8 h15_real_b;
u8 h15_imag_b;
u8 h16_real_b;
u8 h16_imag_b;
u8 h17_real_b;
u8 h17_imag_b;
};
struct bb_physts_rslt_30_info {
u8 *ie_30_addr;
u8 tmp;
};
struct bb_physts_rslt_31_info {
u8 *ie_31_addr;
u8 tmp;
};
struct bb_physts_cnt_info {
u16 all_cnt;
u16 is_2_self_cnt;
u16 err_ie_cnt;
u16 ok_ie_cnt;
u16 err_len_cnt;
};
struct bb_physts_cr_info {
u32 bitmap_search_fail;
//u32 bitmap_search_fail_m;
u32 plcp_hist;
u32 plcp_hist_m;
u32 period_cnt_en;
};
struct bb_physts_info {
u32 physts_bitmap_recv;
u32 bitmap_type[PHYSTS_BITMAP_NUM];
u8 rx_path_en;
bool print_more_info;
u8 physts_dump_mode; /*0: disable, 1:raw data, 2: msg mode, 3:raw data + msg mode*/
u16 physts_dump_idx;
bool is_valid; // used for UI parsing
bool show_phy_sts_all_pkt;
u16 show_phy_sts_cnt;
u16 show_phy_sts_max_cnt;
// long term cfo rslt
s32 l_ltf_cfo_i;
s32 l_ltf_cfo_q;
u16 ie_len_curr[IE_PHYSTS_LEN_ALL];
struct bb_rate_info bb_rate_i;
struct bb_rate_info bb_rate_mu_i;
struct bb_physts_cr_info bb_physts_cr_i;
struct bb_physts_cnt_info bb_physts_cnt_i;
struct bb_physts_rslt_hdr_info bb_physts_rslt_hdr_i;
struct bb_physts_rslt_0_info bb_physts_rslt_0_i;
struct bb_physts_rslt_1_info bb_physts_rslt_1_i;
struct bb_physts_rslt_2_info bb_physts_rslt_2_i;
struct bb_physts_rslt_3_info bb_physts_rslt_3_i;
struct bb_physts_rslt_4_to_7_info bb_physts_rslt_4_i;
struct bb_physts_rslt_4_to_7_info bb_physts_rslt_5_i;
struct bb_physts_rslt_4_to_7_info bb_physts_rslt_6_i;
struct bb_physts_rslt_4_to_7_info bb_physts_rslt_7_i;
struct bb_physts_rslt_8_info bb_physts_rslt_8_i;
struct bb_physts_rslt_9_info bb_physts_rslt_9_i;
struct bb_physts_rslt_10_info bb_physts_rslt_10_i;
struct bb_physts_rslt_11_info bb_physts_rslt_11_i;
struct bb_physts_rslt_12_info bb_physts_rslt_12_i;
struct bb_physts_rslt_13_info bb_physts_rslt_13_i;
struct bb_physts_rslt_14_info bb_physts_rslt_14_i;
struct bb_physts_rslt_15_info bb_physts_rslt_15_i;
struct bb_physts_rslt_16_info bb_physts_rslt_16_i;
struct bb_physts_rslt_17_info bb_physts_rslt_17_i;
struct bb_physts_rslt_18_info bb_physts_rslt_18_i;
struct bb_physts_rslt_19_info bb_physts_rslt_19_i;
struct bb_physts_rslt_20_info bb_physts_rslt_20_i;
struct bb_physts_rslt_21_info bb_physts_rslt_21_i;
struct bb_physts_rslt_22_info bb_physts_rslt_22_i;
struct bb_physts_rslt_23_info bb_physts_rslt_23_i;
struct bb_physts_rslt_24_info bb_physts_rslt_24_i;
struct bb_physts_rslt_25_info bb_physts_rslt_25_i;
struct bb_physts_rslt_26_info bb_physts_rslt_26_i;
struct bb_physts_rslt_27_info bb_physts_rslt_27_i;
struct bb_physts_rslt_28_info bb_physts_rslt_28_i;
struct bb_physts_rslt_29_info bb_physts_rslt_29_i;
struct bb_physts_rslt_30_info bb_physts_rslt_30_i;
struct bb_physts_rslt_31_info bb_physts_rslt_31_i;
};
void halbb_physts_ie_bitmap_set(struct bb_info *bb, u32 ie_page, u32 bitmap);
u32 halbb_physts_ie_bitmap_get(struct bb_info *bb, u32 ie_page);
void halbb_physts_ie_bitmap_en(struct bb_info *bb, enum bb_physts_bitmap_t type,
enum bb_physts_ie_t ie, bool en);
void halbb_phy_sts_manual_trig(struct bb_info *bb, enum bb_mode_type mode, u8 ss);
void halbb_physts_watchdog(struct bb_info *bb);
void halbb_physts_parsing_init(struct bb_info *bb);
void halbb_physts_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_physts_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_physts.h
|
C
|
agpl-3.0
| 15,806
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_PHYSTS_EX_H__
#define __HALBB_PHYSTS_EX_H__
enum bb_physts_bitmap_t {
TD_SEARCH_FAIL = 0,
BRK_BY_TX_PKT = 1,
CCA_SPOOF = 2,
OFDM_BRK = 3,
CCK_BRK = 4,
DL_MU_SPOOFING = 5,
HE_MU = 6,
VHT_MU = 7,
UL_TB_SPOOFING = 8,
RSVD_9 = 9,
TRIG_BASE_PPDU = 10,
CCK_PKT = 11,
LEGACY_OFDM_PKT = 12,
HT_PKT = 13,
VHT_PKT = 14,
HE_PKT = 15,
PHYSTS_BITMAP_NUM
};
struct physts_rxd_user {
u8 macid;
u8 is_data: 1;
u8 is_ctrl:1;
u8 is_mgnt:1;
u8 is_bcn:1;
u8 rsvd_0:4;
};
struct physts_rxd {
u8 is_su:1;
u8 user_num:2;
u8 is_to_self:1;
u8 gi_ltf:4;
u16 data_rate;
u8 macid_su;
//u8 ppdu_cnt;
enum phl_phy_idx phy_idx;
struct physts_rxd_user user_i[4];
};
struct physts_result {
bool physts_rpt_valid; /* @if physts_rpt_valid is false, please ignore the parsing result in this structure*/
u8 rssi_avg;
u8 rssi[4]; /* u(8,1) RSSI in 0~100 index */
enum bb_physts_bitmap_t ie_map_type;
u8 ch_idx; /* channel number---*/
enum channel_width rx_bw;
u8 rxsc; /* sub-channel---*/
u8 is_mu_pkt; /* is MU packet or not---bool*/
u8 is_bf; /* BF packet---bool*/
u8 snr_fd_avg; /* fd, u(8,0), OFDM, fd_snr_avg(phy-sts), limited by FD DFIR output wordlength*/
u8 snr_fd[4]; /* fd, u(8,0), OFDM, fd_snr_avg(phy-sts) + td_rssi_diff[i]*/
u8 snr_td_avg; /* td, u(8,0), OFDM + CCK, td_rssi_avg(phy-sts) - MA(rx_idle_pwer)*/
u8 snr_td[4]; /* td, u(8,0), OFDM + CCK, td_rssi[i](phy-sts) - MA(rx_idle_pwer), limited by DIG in 52A B-cut*/
u8 is_su ;
u8 is_ldpc;
u8 is_stbc;
};
struct bb_info;
bool halbb_physts_parsing(struct bb_info *bb,
u8 *addr,
u16 physts_total_length,
struct physts_rxd *desc,
struct physts_result *bb_rpt);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_physts_ex.h
|
C
|
agpl-3.0
| 2,738
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#include "halbb_plcp_gen.h"
//search tb_ru_tot_sts_max
void halbb_set_bit(u8 strt, u8 len, u32 in, u32 *out)
{
u32 bit_mask = 0;
u8 i = 0;
for (i = 0; i < len; i++)
bit_mask += 1 << i;
in &= bit_mask;
*out |= (in << strt);
}
void halbb_write_cr(struct bb_info *bb, struct cr_address_t cr_address, u32 val, enum phl_phy_idx phy_idx)
{
halbb_set_reg_cmn(bb, cr_address.address, cr_address.bitmask, val, phy_idx);
}
u32 halbb_ceil(u32 numerator, u32 denominator)
{
u32 out = 0;
/*========[ return BSOD ]========*/
// if (denominator == 0)
// return 0;
out = (numerator / denominator) + (numerator > (numerator / denominator)*denominator);
return out;
}
u32 halbb_mod(u32 numerator, u32 denominator)
{
u32 out;
/*========[ return BSOD ]========*/
// if (denominator == 0)
// return 0;
out = numerator - (numerator / denominator) * denominator;
return out;
}
u32 halbb_min(u32 val_1, u32 val_2)
{
u32 out = val_1 > val_2 ? val_2 : val_1;
return out;
}
u32 halbb_max(u32 val_1, u32 val_2)
{
u32 out = val_1 < val_2 ? val_2 : val_1;
return out;
}
enum spec_list halbb_format2spec(enum packet_format_t in, bool *valid)
{
enum spec_list spec = SPEC_B_MODE;
*valid = true;
switch (in){
case B_MODE_FMT:
spec = SPEC_B_MODE;
break;
case LEGACY_FMT:
spec = SPEC_LEGACY;
break;
case HT_MF_FMT:
case HT_GF_FMT:
spec = SPEC_HT;
break;
case VHT_FMT:
spec = SPEC_VHT;
break;
case HE_SU_FMT:
case HE_ER_SU_FMT:
case HE_MU_FMT:
case HE_TB_FMT:
spec = SPEC_HE;
break;
default:
(*valid) = false;
break;
}
return spec;
}
void halbb_find_apep(u32 *apep, bool *can_find, u32 *n_mpdu, u32 *mpdu_length, u8 spec_idx)
{
u32 apep_tmp;
bool is_match;
if (spec_idx == SPEC_HT)
*n_mpdu = halbb_max(halbb_ceil(*apep, (1 << 12) - 1 + 4), 2);
else
*n_mpdu = halbb_ceil(*apep, (1 << 14) - 1 + 4);
/*========[ return BSOD ]========*/
// if (*n_mpdu == 0)
// return;
*mpdu_length = *apep / *n_mpdu - 4; //?????????????
*mpdu_length = *apep - (4 + 4 * halbb_ceil(*mpdu_length, 4)) * (*n_mpdu - 1) - 4;
apep_tmp = (*n_mpdu - 1)*(4 + 4 * halbb_ceil(*mpdu_length, 4)) + (4 + *mpdu_length);
is_match = (apep_tmp == *apep);
*can_find = true;
while (!is_match)
{
*n_mpdu = *n_mpdu + 1;
/*========[ return BSOD ]========*/
// if (*n_mpdu == 0)
// return;
*mpdu_length = *apep / *n_mpdu - 4;
*mpdu_length = *apep - (4 + 4 * halbb_ceil(*mpdu_length , 4)) * (*n_mpdu - 1) - 4;
apep_tmp = (*n_mpdu - 1)*(4 + 4 * halbb_ceil(*mpdu_length , 4)) + (4 + *mpdu_length);
is_match = apep_tmp == *apep;
if (*n_mpdu > (1 << 8)){
*can_find = false;
break;
}
}
}
void halbb_com_par_cal(struct bb_info *bb, u16 n_sd, enum coding_rate_t code_rate, u8 n_bpscs, u8 nss, bool dcm, struct plcp_mcs_table_out_t *out)
{
if (dcm)
out->n_cbps = (n_sd * nss * n_bpscs) >> 1;
else
out->n_cbps = n_sd * nss * n_bpscs;
switch (code_rate) {
case R12:
out->n_dbps = out->n_cbps >> 1;
break;
case R23:
out->n_dbps = (out->n_cbps * 2) / 3;
break;
case R34:
out->n_dbps = (out->n_cbps * 3) / 4;
break;
case R56:
out->n_dbps = (out->n_cbps * 5) / 6;
break;
default:
break;
}
}
bool ldpc_extra_check(u32 n_avbits, u32 n_pld, u8 code_rate)
{
bool cnd0, cnd1, cnd2;
u32 n_cw = 0, l_ldpc = 0, l_ldpc_idx = 0;
u32 n_shrt = 0, n_punc = 0;
u32 table0[4][4] = {{456, 304, 228, 152}, {732, 488, 366, 244},
{1458, 972, 729, 486}, {972, 1296, 1458, 1620}};//912 * (1-R), 1464 * (1-R), 2916 * (1-R), 1944 * R
u32 table1[3][4] = {{324, 432, 486, 540}, {648, 864, 972, 1080},
{972, 1296, 1458, 1620}};//648 * R, 1296 * R, 1944 * R
u32 table2[4] = {1, 2, 3, 5} ;
if (n_avbits <= 648) {
n_cw = 1;
if (n_avbits >= n_pld + table0[0][code_rate])
l_ldpc = 1296;
else
l_ldpc = 648;
} else if (n_avbits <= 1296) {
n_cw = 1;
if (n_avbits >= n_pld + table0[1][code_rate])
l_ldpc = 1944;
else
l_ldpc = 1296;
} else if (n_avbits <= 1944) {
n_cw = 1;
l_ldpc = 1944;
} else if (n_avbits <= 2592) {
n_cw = 2;
if (n_avbits >= n_pld + table0[2][code_rate])
l_ldpc = 1944;
else
l_ldpc = 1296;
} else {
l_ldpc = 1944;
n_cw = halbb_ceil(n_pld, table0[3][code_rate]);
}
if (l_ldpc == 648)
l_ldpc_idx = 0;
else if (l_ldpc == 1296)
l_ldpc_idx = 1;
else if (l_ldpc == 1944)
l_ldpc_idx = 2;
n_shrt = n_cw * table1[l_ldpc_idx][code_rate] > n_pld ? n_cw * table1[l_ldpc_idx][code_rate] - n_pld : 0;
n_punc = n_cw * l_ldpc > n_avbits + n_shrt ? n_cw * l_ldpc - n_avbits - n_shrt : 0;
cnd0 = 10 * n_punc > n_cw * (l_ldpc - table1[l_ldpc_idx][code_rate]);
cnd1 = 10 * n_shrt < 12 * n_punc * table2[code_rate];
cnd2 = n_punc * 10 > 3 * n_cw * (l_ldpc - table1[l_ldpc_idx][code_rate]); //n_punc * 10 > 3 * n_cw * (l_ldpc - table1[l_ldpc_idx][code_rate]); ?
return (cnd0 && cnd1) || cnd2;
}
bool halbb_legacy_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out)
{
u16 n_dbps_table[8] = {24, 36, 48, 72, 96, 144, 192, 216}; // int size
u16 n_cbps_table[8] = {48, 48, 96, 96, 192, 192, 288, 288};
enum coding_rate_t code_rate_table[8] = {R12, R34, R12, R34, R12, R34,
R23,R34};
/*if (in->mcs < 8)
out->valid = true;
else
out->valid = false;
*/
if (in->mcs >= 8) {
//rtw_error("invalid mcs input");
out->valid = false;
return false;
} else {
out->valid = true;
}
out->code_rate = code_rate_table[in->mcs];
out->n_cbps = n_cbps_table[in->mcs];
out->n_dbps = n_dbps_table[in->mcs];
out->n_es = 1;
out->fec = 0;
out->dcm = 0;
out->nss = 1;
return true;
}
bool halbb_ht_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out)
{
u8 nss, mcs;
u16 n_sd_table[2] = {52, 108};
u8 n_bpscs_table[8] = {1, 2, 2, 4, 4, 6, 6, 6};
enum coding_rate_t code_rate_table[8] = {R12, R12, R34, R12, R34, R23,
R34, R56};
out->valid = ((in->bw < 2) && (in->mcs <= 32));
if ((in->mcs == 32) && (in->bw == 1)) {//?????????????????????????????????????????????????????????????
out->code_rate = R12;
out->n_cbps = 48;
out->n_dbps = 24;
out->n_es = 1;
out->valid = in->fec == BCC;
out->fec = 0;
out->nss = 1;
out->dcm = 0;
} else if (out->valid) {
nss = (in->mcs >> 3) + 1;
mcs = in->mcs - ((nss - 1) << 3);
out->code_rate = code_rate_table[mcs];
halbb_com_par_cal(bb, n_sd_table[in->bw], code_rate_table[mcs],
n_bpscs_table[mcs], nss, false, out);
out->n_es = in->fec == BCC ? ((in->mcs == 21 || in->mcs == 22 ||
in->mcs == 23 || in->mcs == 28 ||
in->mcs == 29 || in->mcs == 30 ||
in->mcs == 31) && in->bw == 1) + 1
: 0;
out->fec = in->fec;
out->nss = nss;
out->dcm = 0;
} else {
return false;
//rtw_error("invalid mcs input");
}
return true;
}
bool halbb_vht_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out){
u16 n_sd_table[4] = {52, 108, 234, 468};
enum coding_rate_t code_rate_table[12] = {R12, R12, R34, R12, R34, R23,
R34, R56, R34, R56, R34, R56};
u8 n_bpscs_table[12] = { 1, 2, 2, 4, 4, 6, 6, 6, 8, 8, 10, 10};
s8 n_es_table[4][8][12] = {
{
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 2, -1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 2, -1, 0, 0 }
},
{
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0 },
{ 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0}
},
{
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0 },
{ 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 0, 0 }
},
{
{ 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 0, 0 },
{ 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 0, 0 },
{ 1, 1, 1, 2, 2, 3, 3, 4, 4, -1, 0, 0 },
{ 1, 1, 2, 2, 3, 4, 4, 6, 6, 6, 0, 0 },
{ 1, 2, 2, 3, 4, 5, 5, 6, 8, 8, 0, 0 },
{ 1, 2, 2, 3, 4, 6, 6, 8, 8, 9, 0, 0 },
{ 1, 2, 3, 4, 6, 7, 7, 9, 12, 12, 0, 0 },
{ 1, 2, 3, 4, 6, 8, 8, 9, 12, 12, 0, 0 }
}
};
u16 n_sd = n_sd_table[in->bw];
u8 n_bpscs = n_bpscs_table[in->mcs];
//enum coding_rate_t code_rate = code_rate_table[in->mcs];
u8 nss = in->nss;
out->valid = ((((in->fec == LDPC) && (in->mcs <= 11)) ||
((in->fec == BCC) && (in->mcs <= 9))) &&
((in->nss > 0) && (in->nss <= 8)));
out->code_rate = code_rate_table[in->mcs];
halbb_com_par_cal(bb, n_sd, code_rate_table[in->mcs], n_bpscs, nss, false, out);
if ((in->fec == BCC) && (out->valid)) {
s8 n_es = n_es_table[in->bw][in->nss - 1][in->mcs];
out->n_es = n_es;
out->valid = (n_es != -1);
out->fec = in->fec;
out->dcm = 0;
out->nss = in->nss;
} else if (out->valid) {
out->n_es = 0;
out->fec = in->fec;
out->dcm = 0;
out->nss = in->nss;
} else {
//rtw_error("invalid mcs input");
return false;
}
return true;
}
bool halbb_he_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out)
{
struct plcp_mcs_table_out_t out_temp;
u16 n_sd_table[8] = {24, 48, 102, 234, 468, 980, 1960, 52};
enum coding_rate_t code_rate_table[12] = {R12, R12, R34, R12, R34, R23,
R34, R56, R34, R56, R34, R56};
u8 n_bpscs_table[12] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8, 10, 10};
u16 n_sd_short_table[2][8] = {{6,12,24,60,120,240,492,0},
{2,6,12,30,60,120,246,0} };
out->valid = ((in->nss > 0 && in->nss <= 8) && (!in->dcm || in->mcs == 0 || in->mcs == 1 || in->mcs == 3 || in->mcs == 4) && (!in->dcm || in->nss == 1 || in->nss == 2) && (in->fec == LDPC || ( in->mcs <= 9 && in->ru_size <= RU242)));
if (!out->valid) {
//rtw_error("invalid mcs input");
return false;
}
out->code_rate = code_rate_table[in->mcs];
halbb_com_par_cal(bb, n_sd_table[in->ru_size], code_rate_table[in->mcs],
n_bpscs_table[in->mcs], in->ru_size==HESIGB ? 1 : in->nss,
in->dcm, out);
out->n_es = in->fec == BCC || in->ru_size == HESIGB;
halbb_com_par_cal(bb, n_sd_short_table[in->dcm][in->ru_size], code_rate_table[in->mcs], n_bpscs_table[in->mcs],in->nss,false,&out_temp);
out->he_n_cbps_short = out_temp.n_cbps;
out->he_n_dbps_short = out_temp.n_dbps;
out->fec = in->fec || in->ru_size == HESIGB;
out->dcm = in->dcm;
out->nss = in->ru_size == HESIGB ? 1 : in->nss;
return true;
}
enum plcp_sts halbb_mcs_table(struct bb_info *bb, const struct plcp_mcs_table_in_t *in, struct plcp_mcs_table_out_t *out)
{
switch ((enum spec_list)(in->spec_idx)) {
case SPEC_LEGACY:
if (!halbb_legacy_mcs_table(bb, in, out))
return OFDM_INVALID;
break;
case SPEC_HT:
if (!halbb_ht_mcs_table(bb, in, out))
return HT_INVALID;
break;
case SPEC_VHT:
if (!halbb_vht_mcs_table(bb, in, out))
return VHT_INVALID;
break;
case SPEC_HE:
if (!halbb_he_mcs_table(bb, in, out))
return HE_INVALID;
break;
default:
out->valid = false;
return SPEC_INVALID;
//break;
}
//rtw_assert(out->valid, "invalid spec");
return PLCP_SUCCESS;
}
void halbb_get_mcs_out(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par, struct plcp_tx_pre_fec_padding_setting_out_t *out, bool *valid){
bool mu_usr_en[9] = { false,false,false,false,false,false,false,true,true };
struct plcp_mcs_table_in_t mcs_in;
enum spec_list spec;
u32 u = 0;
if (mu_usr_en[in->format_idx])
par->com.n_usr_refine = in->n_user;
else
par->com.n_usr_refine = 1;
spec = halbb_format2spec((enum packet_format_t)(in->format_idx), valid);
if (!(*valid)){
//rtw_error("invalid spec");
return;
}
par->com.spec_idx = spec;
mcs_in.spec_idx = (u8)spec;//?????????????????????????????????????????????????????????????????????????????????
for (u = 0; u < par->com.n_usr_refine; u++){
mcs_in.bw = in->dbw;
mcs_in.dcm = in->usr[u].dcm;
mcs_in.fec = in->usr[u].fec;
mcs_in.mcs = in->usr[u].mcs;
mcs_in.nss = in->usr[u].nss;
if (par->com.spec_idx == SPEC_HE) {
if (in->format_idx == HE_TB_FMT || in->format_idx == HE_MU_FMT)
mcs_in.ru_size = in->usr[u].ru_size_idx;
else if (in->format_idx == HE_ER_SU_FMT)
mcs_in.ru_size = (u8)(3 - in->he_er_u106ru_en);//?????????????????????????????????????????????????????????????????????????????????
else
mcs_in.ru_size = in->dbw + 3;
} else {
mcs_in.ru_size = 0;
}
par->usr[u].ru_size_refine = mcs_in.ru_size;
out->plcp_valid = halbb_mcs_table(bb, &mcs_in, &par->usr_mcs_out[u]);
out->usr[u].mcs_valid = par->usr_mcs_out[u].valid;
if (!par->usr_mcs_out[u].valid){
*valid = false;
return;
}
out->usr[u].ru_size = mcs_in.ru_size;
out->usr[u].dcm = par->usr_mcs_out[u].dcm;
out->usr[u].fec = par->usr_mcs_out[u].fec;
out->usr[u].nss = par->usr_mcs_out[u].nss;
}
}
void halbb_get_nsym_init(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par)
{
u8 n_tail = 6;
u8 n_service = 16;
u32 u_max = 0;
u32 val_max = 0;
u32 comp_val;
u32 u = 0;
for (u = 0; u < par->com.n_usr_refine; u++){
par->usr[u].n_excess = halbb_mod((par->usr[u].apep_refine << 3) + par->usr_mcs_out[u].n_es * n_tail + n_service, par->usr_mcs_out[u].n_dbps << par->com.stbc);
if (par->usr[u].n_excess == 0 || par->com.spec_idx != SPEC_HE)
par->usr[u].pre_fec_padding_factor_init = 4;
else
par->usr[u].pre_fec_padding_factor_init = halbb_min(halbb_ceil(par->usr[u].n_excess, par->usr_mcs_out[u].he_n_dbps_short << par->com.stbc), 4);
par->usr[u].n_sym_init = halbb_ceil((par->usr[u].apep_refine << 3) + n_service + n_tail * par->usr_mcs_out[u].n_es, par->usr_mcs_out[u].n_dbps << par->com.stbc) << par->com.stbc;
comp_val = ((par->usr[u].n_sym_init - par->com.m_stbc) << 2) + (par->usr[u].pre_fec_padding_factor_init << par->com.stbc);
if (comp_val >= val_max) {
val_max = comp_val;
u_max = u;
}
}
par->com.n_sym_init = (u16)par->usr[u_max].n_sym_init;//?????????????????????????????????????????????????????????????????????????????????
par->com.pre_fec_padding_factor_init = (u16)par->usr[u_max].pre_fec_padding_factor_init;//?????????????????????????????????????????????????????????????????????????????????
if (par->com.pre_fec_padding_factor_init < 4) {
for (u = 0; u < par->com.n_usr_refine; u++){
par->usr[u].n_dbps_last_init = par->com.pre_fec_padding_factor_init * par->usr_mcs_out[u].he_n_dbps_short;
par->usr[u].n_cbps_last_init = par->com.pre_fec_padding_factor_init * par->usr_mcs_out[u].he_n_cbps_short;
}
} else {
for (u = 0; u < in->n_user; u++) {
par->usr[u].n_dbps_last_init = par->usr_mcs_out[u].n_dbps;
par->usr[u].n_cbps_last_init = par->usr_mcs_out[u].n_cbps;
}
}
}
void halbb_get_nsym(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, const struct plcp_tx_pre_fec_padding_setting_par_t *par, struct plcp_tx_pre_fec_padding_setting_out_t *out)
{
u8 n_service, n_tail;
u8 t_pe_table[4][3] = {{0, 2, 4}, {0, 0, 1}, {0, 0, 2}, {0, 1, 3}};
u32 n_pld, n_avbits, n_dpbs_last;
u32 psdu = 0;
u32 u = 0;
if (!par->com.ndp_en) {
n_service = 16;
n_tail = 6;
out->ldpc_extra = false;
out->stbc = par->com.stbc;
for (u = 0; u < par->com.n_usr_refine; u++) {
out->usr[u].nsts = out->usr[u].nss << par->com.stbc;
if (par->usr_mcs_out[u].fec == LDPC) {
if (par->com.spec_idx == SPEC_HT)
n_pld = (par->usr[u].apep_refine << 3) + n_service;
else
n_pld = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (par->usr[u].n_dbps_last_init << par->com.stbc);
n_avbits = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_cbps + (par->usr[u].n_cbps_last_init << par->com.stbc);
out->ldpc_extra = ldpc_extra_check(n_avbits, n_pld, (u8)par->usr_mcs_out[u].code_rate);//?????????????????????????????????????????????????????????????????????????????????
if (out->ldpc_extra > 0)
break;
}
}
out->doppler_en = par->com.doppler_mode > 0;
out->midamble = out->doppler_en ? par->com.doppler_mode - 1 : 0;
if (out->ldpc_extra > 0 || (par->com.tb_trig && par->com.tb_ldpc_extra)) {
if (par->com.pre_fec_padding_factor_init == 4) {
out->n_sym = par->com.n_sym_init + par->com.m_stbc;
out->pre_fec_padding_factor = par->com.spec_idx == SPEC_HE ? 1 : 0;
} else {
out->n_sym = par->com.n_sym_init;
out->pre_fec_padding_factor = par->com.spec_idx == SPEC_HE ? halbb_mod(par->com.pre_fec_padding_factor_init + 1, 4) : 0;
}
} else {
out->n_sym = par->com.n_sym_init;
out->pre_fec_padding_factor = par->com.spec_idx == SPEC_HE ? halbb_mod(par->com.pre_fec_padding_factor_init, 4) : 0;
}
for (u = 0; u < par->com.n_usr_refine; u++) {
//u32 n_pld(0), psdu(0);
if (par->com.spec_idx == SPEC_HT && par->usr_mcs_out[u].fec == LDPC) {
n_pld = (in->usr[u].apep << 3) + n_service;
} else if (par->usr_mcs_out[u].fec == LDPC) {
n_pld = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (par->usr[u].n_dbps_last_init << par->com.stbc);
} else {
n_dpbs_last = out->pre_fec_padding_factor == 0 ? par->usr_mcs_out[u].n_dbps : par->usr_mcs_out[u].he_n_dbps_short * out->pre_fec_padding_factor;
n_pld = (out->n_sym - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (n_dpbs_last << par->com.stbc);
}
psdu = (n_pld - n_service - n_tail * par->usr_mcs_out[u].n_es) >> 3;
//out->usr[u]->eof_padding_length = max(0,psdu - ceil(par->usr[u]->apep_refine, 4) << 2);
if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && par->usr[u].n_mpdu_refine == 1)) {
out->usr[u].eof_padding_length = 0;
} else {
out->usr[u].eof_padding_length = (psdu > (halbb_ceil(par->usr[u].apep_refine, 4) << 2)) ? (psdu - (halbb_ceil(par->usr[u].apep_refine, 4) << 2)) : 0;
}
out->usr[u].nsts = par->usr_mcs_out[u].nss << par->com.stbc;
out->usr[u].apep_len = par->usr[u].apep_refine;
out->usr[u].mpdu_length_byte = par->usr[u].mpdu_length_byte_refine;
out->usr[u].n_mpdu = par->usr[u].n_mpdu_refine;
}
if (par->com.tb_trig)
out->t_pe = par->com.tb_trig_t_pe;
else
out->t_pe = par->com.spec_idx == SPEC_HE ? t_pe_table[out->pre_fec_padding_factor][in->nominal_t_pe] : 0;
} else {
out->ldpc_extra = false;
out->t_pe = par->com.spec_idx == SPEC_HE ? 2 : 0;
out->stbc = par->com.stbc;
for (u = 0; u < par->com.n_usr_refine; u++) {
out->usr[u].eof_padding_length = 0;
out->usr[u].nsts = par->usr_mcs_out[u].nss << par->com.stbc;
out->usr[u].apep_len = par->usr[u].apep_refine;
out->usr[u].mpdu_length_byte = par->usr[u].mpdu_length_byte_refine;
out->usr[u].n_mpdu = par->usr[u].n_mpdu_refine;
}
out->n_sym = 0;
out->pre_fec_padding_factor = 0;
}
out->n_sym_hesigb = par->com.n_hesigb_sym;
}
void halbb_get_txtime(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par, struct plcp_tx_pre_fec_padding_setting_out_t *out)
{
struct bb_h2c_fw_tx_setting *fw_tx_i = &bb->bb_fwtx_h2c_i;
//n_ma, m_ma
u8 m_table[9] = {0,0,0,0,0,2,1,1,2};
u32 l_len_temp;
if (par->com.doppler_mode > 0)
par->com.n_ma = halbb_ceil(out->n_sym - 1, par->com.m_ma) > 1 ? halbb_ceil(out->n_sym - 1, par->com.m_ma) - 1 : 0;
else
par->com.n_ma = 0;
out->tx_time_0p4us = par->com.preamble_0p4us + par->com.n_ma * par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us + out->n_sym * par->com.t_sym_0p4us + out->t_pe * 10;
if (par->com.spec_idx == SPEC_LEGACY) {
out->l_len = (u16)par->usr[0].apep_refine; //?????????????????????????????????????????????????????????????????????????????????
} else {
l_len_temp = halbb_ceil(out->tx_time_0p4us - 50, 10) * 3 - 3 - m_table[in->format_idx];
if (par->com.spec_idx == SPEC_HT)
out->l_len = (u16)halbb_max(l_len_temp,in->ht_l_len);//?????????????????????????????????????????????????????????????????????????????????
else
out->l_len = (u16)l_len_temp;//?????????????????????????????????????????????????????????????????????????????????
}
if (par->com.spec_idx == SPEC_VHT)
out->disamb = par->com.gi == 0 ? halbb_mod(out->n_sym, 10) == 9 : 0;
else if (par->com.spec_idx == SPEC_HE)
out->disamb = (out->t_pe * 10 + halbb_mod(10 - halbb_mod(out->tx_time_0p4us, 10), 10)) >= par->com.t_sym_0p4us;
else
out->disamb = 0;
out->ndp = par->com.ndp_en;
out->n_ltf = par->com.n_ltf_sym > 0 ? (u16)(par->com.n_ltf_sym - 1) : 0;//?????????????????????????????????????????????????????????????????????????????????
out->valid = out->tx_time_0p4us <= 13710 || in->format_idx == HT_GF_FMT;
fw_tx_i->tx_time[0]= (u8) (out->tx_time_0p4us & 0x000000ff); // for FW trigger specific duty cycle used
fw_tx_i->tx_time[1]= (u8) ((out->tx_time_0p4us & 0x0000ff00) >> 8);
fw_tx_i->tx_time[2]= (u8) ((out->tx_time_0p4us & 0x00ff0000) >> 16);
fw_tx_i->tx_time[3]= (u8) ((out->tx_time_0p4us & 0xff000000) >> 24);
//rtw_assert(out->valid,"txtime exceeds");
if (!out->valid)
out->plcp_valid = LENGTH_EXCEED;
out->n_usr = par->com.n_usr_refine;
out->gi = par->com.gi;
}
void halbb_refine_input(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_par_t *par)
{
bool can_find = false , disam;
u8 n_tail = 6;
u8 n_service = 24;
u8 remain_time_0p4us;
u32 n_mpdu = 0, mpdu_length = 0, apep, tmp, max_tx_time_0p4us, n_dbps_last, n_pld, n_psdu;
bool ndp_en_table[9] = {false,false,true,true,true,true,false,false,false};
u8 n_ltf_table[9] = { 0, 1, 2, 4, 4, 6, 6, 8, 8 };
u8 t_fft_0p4us[2] = { 8, 32 };
u8 must_preamble_0p4us_table[9] = { 0, 50, 80, 50, 90, 90, 110, 90, 100 };
u8 m_ma_table[3] = { 0, 10, 20 };
u32 u = 0;
u8 spec_idx = 0;
spec_idx = (u8)par->com.spec_idx;
if (par->com.spec_idx > SPEC_LEGACY)
par->com.stbc = in->stbc;
else
par->com.stbc = false;
par->com.m_stbc = par->com.stbc + 1;
if (par->com.spec_idx == SPEC_HE)
par->com.doppler_mode = in->doppler_mode;
else
par->com.doppler_mode = 0;
par->com.n_sts_max = 0;
for (u = 0; u < par->com.n_usr_refine; u++)
par->com.n_sts_max = halbb_max(par->com.n_sts_max, par->usr_mcs_out[u].nss << par->com.stbc);
if (in->format_idx == HE_TB_FMT && in->mode_idx == 3)
par->com.n_ltf_sym = n_ltf_table[in->tb_ru_tot_sts_max+1];
else
par->com.n_ltf_sym = (par->com.spec_idx == SPEC_LEGACY ? 0 : n_ltf_table[par->com.n_sts_max]) + n_ltf_table[par->com.spec_idx == SPEC_HT ? in->ness : 0];
if (in->format_idx == HE_MU_FMT)
par->com.n_hesigb_sym = in->n_hesigb_sym;
else
par->com.n_hesigb_sym = 0;
//t_sym
if (par->com.spec_idx == SPEC_LEGACY)
par->com.gi = 1;
else if (par->com.spec_idx == SPEC_HT || par->com.spec_idx == SPEC_VHT)
par->com.gi = in->gi > 0;
else
par->com.gi = (u8)halbb_max(1,in->gi); //???????????????????????????????????
par->com.t_sym_0p4us = t_fft_0p4us[par->com.spec_idx == SPEC_HE] + (1 << par->com.gi);
if (par->com.spec_idx == SPEC_HE)
par->com.t_ltf_sym_0p4us = (8 << halbb_min(in->ltf_type, 2)) + (1 << par->com.gi);
else
par->com.t_ltf_sym_0p4us = 10;
par->com.preamble_0p4us = must_preamble_0p4us_table[in->format_idx] + (u16)par->com.n_ltf_sym * (u16)par->com.t_ltf_sym_0p4us + (u16)par->com.n_hesigb_sym * 10;//?????????????????????????
par->com.m_ma = m_ma_table[par->com.doppler_mode];
par->com.ndp_en = ndp_en_table[in->format_idx] && in->ndp;
par->com.tb_trig = (in->mode_idx == 3 && in->format_idx == HE_TB_FMT);
if (par->com.ndp_en) {
apep = 0;
for (u = 0; u < par->com.n_usr_refine; u++) {
par->usr[u].n_mpdu_refine = 1;
par->usr[u].mpdu_length_byte_refine = apep;
par->usr[u].apep_refine = apep;
}
} else if (in->mode_idx == 0){//apep
for (u = 0; u < par->com.n_usr_refine; u++) {
apep = in->usr[u].apep;
if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && apep < (1 << 14))) {
par->usr[u].n_mpdu_refine = 1;
par->usr[u].mpdu_length_byte_refine = apep;
par->usr[u].apep_refine = apep;
} else{
halbb_find_apep(&apep,&can_find,&n_mpdu,&mpdu_length,spec_idx);
while (!can_find){
apep = apep - 1;
halbb_find_apep(&apep, &can_find, &n_mpdu, &mpdu_length,spec_idx);
}
par->usr[u].n_mpdu_refine = n_mpdu;
par->usr[u].mpdu_length_byte_refine = mpdu_length;
par->usr[u].apep_refine = apep;
}
}
} else if(in->mode_idx == 1 || par->com.tb_trig) { // max_tx_time
disam = par->com.spec_idx == SPEC_HE ? in->nominal_t_pe == 2 : false;
disam = par->com.tb_trig ? (bool)in->tb_disam : disam; //??????????????????????????????????????????????
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/*========[ return BSOD ]========*/
// if ((par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us + par->com.m_ma * par->com.t_sym_0p4us) == 0)
// return;
max_tx_time_0p4us = par->com.tb_trig ? halbb_ceil(in->tb_l_len + 3 + 2,3)*10 : in->max_tx_time_0p4us;
tmp = (max_tx_time_0p4us > par->com.preamble_0p4us + (disam + 2) * par->com.t_sym_0p4us ) && par->com.doppler_mode > 0 ? (in->max_tx_time_0p4us - par->com.preamble_0p4us - (disam + 2) * par->com.t_sym_0p4us) / (par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us + par->com.m_ma * par->com.t_sym_0p4us) : 0;
par->com.n_ma = par->com.doppler_mode > 0 ? tmp : 0;
par->com.n_sym_init = ((u16)max_tx_time_0p4us - par->com.preamble_0p4us - ((u16)par->com.n_ma * (u16)par->com.n_ltf_sym * (u16)par->com.t_ltf_sym_0p4us)) / (u16)par->com.t_sym_0p4us - disam; // Look
if (par->com.stbc)
par->com.n_sym_init = (u16)halbb_ceil(par->com.n_sym_init, 2) << 1; //???????????????????????????????
remain_time_0p4us = (u8)(max_tx_time_0p4us - par->com.preamble_0p4us - par->com.n_sym_init * par->com.t_sym_0p4us - par->com.n_ma * par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us);//????????????????????????????????? false?
if (par->com.spec_idx == SPEC_HE && !par->com.tb_trig) {
if (remain_time_0p4us >= 40) {
par->com.pre_fec_padding_factor_init = 4;
} else if (remain_time_0p4us >= 30) {
if (in->nominal_t_pe == 2)
par->com.pre_fec_padding_factor_init = 3;
else
par->com.pre_fec_padding_factor_init = 4;
} else if (remain_time_0p4us >= 20) {
if (in->nominal_t_pe == 2)
par->com.pre_fec_padding_factor_init = 2;
else
par->com.pre_fec_padding_factor_init = 4;
} else if (remain_time_0p4us >= 10) {
if (in->nominal_t_pe == 2)
par->com.pre_fec_padding_factor_init = 1;
else if (in->nominal_t_pe == 1)
par->com.pre_fec_padding_factor_init = 3;
else
par->com.pre_fec_padding_factor_init = 4;
} else if (remain_time_0p4us >= 0) {
if (in->nominal_t_pe == 2)
par->com.pre_fec_padding_factor_init = 1;
else if (in->nominal_t_pe == 1)
par->com.pre_fec_padding_factor_init = 1;
else
par->com.pre_fec_padding_factor_init = 1;
}
} else if(!par->com.tb_trig) {
par->com.pre_fec_padding_factor_init = 4;
} else {
//tb_tri_en
par->com.tb_trig_t_pe = (max_tx_time_0p4us - par->com.preamble_0p4us - par->com.n_sym_init * par->com.t_sym_0p4us - par->com.n_ma * par->com.n_ltf_sym * par->com.t_ltf_sym_0p4us)/10;
par->com.tb_ldpc_extra = in->tb_ldpc_extra;
if (par->com.tb_ldpc_extra) {
if (in->tb_pre_fec_padding_factor == 1) {
par->com.n_sym_init = par->com.n_sym_init - 1;
par->com.pre_fec_padding_factor_init = 4;
} else {
par->com.n_sym_init = par->com.n_sym_init;
par->com.pre_fec_padding_factor_init = (u16)in->tb_pre_fec_padding_factor - 1; //??????????????????????????????
}
} else {
par->com.n_sym_init = par->com.n_sym_init;
par->com.pre_fec_padding_factor_init = in->tb_pre_fec_padding_factor == 0 ? 4 : (u16)in->tb_pre_fec_padding_factor;
}
}
for (u = 0; u < par->com.n_usr_refine; u++) {
n_dbps_last = par->com.pre_fec_padding_factor_init == 4 ? par->usr_mcs_out[u].n_dbps : par->usr_mcs_out[u].he_n_dbps_short * par->com.pre_fec_padding_factor_init;
n_pld = (par->com.n_sym_init - par->com.m_stbc) * par->usr_mcs_out[u].n_dbps + (n_dbps_last << par->com.stbc);
n_psdu = (n_pld - n_tail * par->usr_mcs_out[u].n_es - n_service) >> 3;
apep = n_psdu;
if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && apep < (1 << 14))) {
par->usr[u].n_mpdu_refine = 1;
par->usr[u].mpdu_length_byte_refine = apep;
par->usr[u].apep_refine = apep;
} else {
//can_find;
//u32 n_mpdu, mpdu_length;
halbb_find_apep(&apep, &can_find, &n_mpdu, &mpdu_length,spec_idx);
while (!can_find) {
apep = apep - 1;
halbb_find_apep(&apep, &can_find, &n_mpdu, &mpdu_length,spec_idx);
}
par->usr[u].n_mpdu_refine = n_mpdu;
par->usr[u].mpdu_length_byte_refine = mpdu_length;
par->usr[u].apep_refine = apep;
}
}
} else { //n_mpdu,mpdu_len
for (u = 0; u < par->com.n_usr_refine; u++) {
par->usr[u].n_mpdu_refine = par->com.spec_idx > SPEC_LEGACY ? in->usr[u].n_mpdu : 1;
par->usr[u].mpdu_length_byte_refine = in->usr[u].mpdu_length_byte;
if (par->com.spec_idx == SPEC_LEGACY || (par->com.spec_idx == SPEC_HT && par->usr[u].n_mpdu_refine == 1))
par->usr[u].apep_refine = par->usr[u].mpdu_length_byte_refine;
else
par->usr[u].apep_refine = (par->usr[u].n_mpdu_refine - 1)*(4 + 4 * halbb_ceil(par->usr[u].mpdu_length_byte_refine, 4)) + (4 + par->usr[u].mpdu_length_byte_refine);
}
}
}
enum plcp_sts halbb_tx_plcp_cal(struct bb_info *bb, const struct plcp_tx_pre_fec_padding_setting_in_t *in, struct plcp_tx_pre_fec_padding_setting_out_t *out)
{
bool mcs_out_valid = false;
struct plcp_tx_pre_fec_padding_setting_par_t par;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
halbb_get_mcs_out(bb, in, &par, out, &mcs_out_valid);
if (!mcs_out_valid) {
out->valid = false;
return out->plcp_valid;
}
halbb_refine_input(bb, in, &par);
halbb_get_nsym_init(bb, in, &par);
halbb_get_nsym(bb, in, &par, out);
halbb_get_txtime(bb, in, &par, out);
return out->plcp_valid;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_plcp_gen.c
|
C
|
agpl-3.0
| 31,477
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_PLCP_GEN_H_
#define _HALBB_PLCP_GEN_H_
/* ============================================================
define
============================================================
*/
#define N_USER 4
/* ============================================================
structure
============================================================
*/
struct plcp_mcs_table_in_t {
u8 spec_idx : 3;
u8 mcs : 5;
u8 nss : 4;
u8 bw : 2;//0:BW20, 1:BW40, 2:BW80, 3:BW160 /*enum channel_width*/
u8 rsvd0 : 2;
u8 ru_size : 3; //0:RU26, 1:RU52, 2:RU106, 3:RU242, 4:RU484, 5:RU996, 6:RU996x2, 7:hesigb
u8 rsvd1 : 5;
bool dcm;
bool fec;
};
struct plcp_mcs_table_out_t {
u32 n_dbps : 17;
u32 he_n_dbps_short : 15;
u32 n_cbps : 18;
u32 n_es : 4;
u32 valid : 1;
u32 code_rate : 2;
u32 nss : 3;
u32 rsvd0 : 4;
u32 he_n_cbps_short : 15;
u32 rsvd1 : 17;
bool dcm;
bool fec;
};
//========== [Par] ==========//
struct com_pre_fec_par {
u16 n_sym_init : 11;
u16 spec_idx : 3;
u16 pre_fec_padding_factor_init : 3;
u16 ndp_en : 1;
u16 preamble_0p4us : 16;
u8 m_stbc : 2;
u8 stbc : 1;
u8 doppler_mode : 2;
u8 gi : 2;
u32 t_sym_0p4us : 6;
u32 t_ltf_sym_0p4us : 6;
u32 n_ltf_sym : 4;
u32 n_sts_max : 4;
u32 n_ma : 6;
u32 m_ma : 5;
u32 tb_trig : 1;
u32 n_hesigb_sym : 8;
u32 n_usr_refine : 8;
u32 tb_trig_t_pe : 3;
u32 tb_ldpc_extra : 1;
u32 rsvd1 : 12;
};
struct usr_pre_fec_par {
u32 n_excess : 15;
u32 pre_fec_padding_factor_init : 3;
u32 n_sym_init : 11;
u32 rsvd0 : 3;
u32 n_dbps_last_init : 17;
u32 n_mpdu_refine : 9;
u32 rsvd1 : 6;
u32 n_cbps_last_init : 18;
u32 mpdu_length_byte_refine : 14;
u32 apep_refine : 22;
u32 ru_size_refine : 3;
u32 rsvd3 : 7;
};
struct plcp_tx_pre_fec_padding_setting_par_t {
struct com_pre_fec_par com;
struct plcp_mcs_table_out_t usr_mcs_out[4];
struct usr_pre_fec_par usr[N_USER];
};
//========== [Input] ==========//
struct usr_pre_fec_in {
u8 ru_size_idx : 3;
u8 nss : 4;
u8 rsvd0 : 1;
u8 mcs : 6;
u8 rsvd1 : 2;
u32 apep : 22;
u32 n_mpdu : 9;
u32 rsvd2 : 1;
u16 mpdu_length_byte : 14;
u16 rsvd3 : 2;
bool dcm;
bool fec;
};
struct plcp_tx_pre_fec_padding_setting_in_t {
u8 format_idx : 4;
u8 stbc : 1;
u8 he_dcm_sigb : 1;
u8 doppler_mode : 2; //0: diable ,1:MA10, 2:MA20
u16 n_hesigb_sym : 11; //per ch
u16 he_mcs_sigb : 3;
u16 nominal_t_pe : 2;
u8 dbw : 2;
u8 gi : 2; //0.4,0.8,1.6,3.2
u8 ltf_type : 2; //1x, 2x, 4x
u8 ness : 2;
u32 mode_idx : 2; //0:apep, 1:max_tx_time, 2:n_mpdu,mpdu_len, 3:tb_trigger_mode
u32 max_tx_time_0p4us : 14;
u32 n_user : 8;
u32 ndp : 1;
u32 he_er_u106ru_en : 1; //done
u32 rsvd1 : 6;
u32 tb_l_len : 12;
u32 tb_ru_tot_sts_max : 3;
u32 tb_disam : 1;
u32 tb_ldpc_extra : 1;
u32 tb_pre_fec_padding_factor : 2;
u32 ht_l_len : 12;
u32 rsvd2 : 10;
struct usr_pre_fec_in usr[N_USER];
};
//========== [Output] ==========//
struct usr_pre_fec_out {
u32 nss : 4;
u32 nsts : 4;
u32 mpdu_length_byte : 14;
u32 n_mpdu : 9;
u32 rsvd0 : 1;
u32 eof_padding_length : 32;
u32 apep_len : 22;
u32 ru_size : 3;
u32 mcs_valid : 1;
u32 rsvd1 : 6;
bool fec;
bool dcm;
};
struct plcp_tx_pre_fec_padding_setting_out_t {
u32 pre_fec_padding_factor : 2; // 0:4, 1:1, 2:2, 3:3
u32 n_sym : 11;
u32 ldpc_extra : 1;
u32 rsvd : 14;
u32 t_pe : 3; //0: 0us, 1:4us, 2:8us, 3:12us, 4:16us
u32 valid : 1;
u16 l_len : 12;
u16 disamb : 1;
u16 n_ltf : 3;
u32 tx_time_0p4us;
u32 stbc : 1;
u32 doppler_en : 1;
u32 midamble : 2;
u32 n_usr : 8;
u32 ndp : 1;
u32 gi : 2;
u32 n_sym_hesigb : 6;
u32 plcp_valid : 8;
u32 rvsd0 : 3;
struct usr_pre_fec_out usr[N_USER];
};
/* ============================================================
Enumeration
============================================================
*/
enum spec_list {
SPEC_B_MODE = 0,
SPEC_LEGACY = 1,
SPEC_HT = 2,
SPEC_VHT = 3,
SPEC_HE = 4
};
enum fec_t {
BCC = 0,
LDPC
};
enum ru_sizes_list{
RU26 = 0,
RU52,
RU106,
RU242,
RU484,
RU996,
RU996X2,
HESIGB
};
enum packet_format_t{
B_MODE_FMT = 0,
LEGACY_FMT,
HT_MF_FMT,
HT_GF_FMT,
VHT_FMT,
HE_SU_FMT,
HE_ER_SU_FMT,
HE_MU_FMT,
HE_TB_FMT
};
enum coding_rate_t{
R12 = 0,
R23,
R34,
R56
};
/* ============================================================
Function Prototype
============================================================
*/
struct bb_info;
u32 halbb_ceil(u32 numerator, u32 denominator);
u32 halbb_mod(u32 numerator, u32 denominator);
u32 halbb_min(u32 val_1, u32 val_2);
u32 halbb_max(u32 val_1, u32 val_2);
void halbb_set_bit(u8 strt, u8 len, u32 in, u32* out);
void halbb_write_cr(struct bb_info *bb, struct cr_address_t cr_address, u32 val,
enum phl_phy_idx phy_idx);
enum plcp_sts halbb_tx_plcp_cal(struct bb_info *bb,
const struct plcp_tx_pre_fec_padding_setting_in_t *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_plcp_gen.h
|
C
|
agpl-3.0
| 5,854
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#include "halbb_plcp_gen.h"
//#include "halbb_plcp_tx.h"
//#include "halbb_he_sigb_gen.h"
#ifdef HALBB_PMAC_TX_SUPPORT
u8 halbb_set_crc8(struct bb_info *bb, unsigned char in[], u8 len)
{
u16 i = 0;
u8 reg0 = 1;
u8 reg1 = 1;
u8 reg2 = 1;
u8 reg3 = 1;
u8 reg4 = 1;
u8 reg5 = 1;
u8 reg6 = 1;
u8 reg7 = 1;
u8 bit_in = 0;
u8 out = 0;
for (i = 0; i < len; i++) {
bit_in = in[i] ^ reg7;
reg7 = reg6;
reg6 = reg5;
reg5 = reg4;
reg4 = reg3;
reg3 = reg2;
reg2 = bit_in ^ reg1;
reg1 = bit_in ^ reg0;
reg0 = bit_in;
}
out = (reg0 << 7) | (reg1 << 6) | (reg2 << 5) | (reg3 << 4) |
(reg4 << 3) | (reg5 << 2) | (reg6 << 1) | reg7;
return ~out;
}
void rtw_halbb_plcp_gen_init(struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_in_t *in_plcp)
{
u32 i = 0;
//Outer Input
in->source_gen_mode = 2;
in->locked_clk = 1;
in->dyn_bw = 0;
in->ndp_en = 0;
in->doppler = 0;
in->ht_l_len = 0;
in->preamble_puncture = 0;
in->he_sigb_compress_en = 1;
in->ul_flag = 0;
in->bss_color= 10;
in->sr = 0;
in->beamchange_en = 1;
in->ul_srp1 = 0;
in->ul_srp2 = 0;
in->ul_srp3 = 0;
in->ul_srp4 = 0;
in->group_id = 0;
in->txop = 127;
in->nominal_t_pe = 2;
in->ness = 0;
in->tb_rsvd = 0;
in->vht_txop_not_allowed = 0;
for (i = 0; i < in->n_user; i++) {
in->usr[i].mpdu_len = 0;
in->usr[i].n_mpdu = 0;
in->usr[i].txbf = 0;
in->usr[i].scrambler_seed = 0x81;
in->usr[i].random_init_seed = 0x4b;
}
//PLCP Input
in_plcp->format_idx = (u8)in->ppdu_type;
in_plcp->stbc = (u8)in->stbc;
in_plcp->he_dcm_sigb = (u8)in->he_dcm_sigb;
in_plcp->doppler_mode = (u8)in->doppler;
in_plcp->he_mcs_sigb = (u16)in->he_mcs_sigb;
in_plcp->nominal_t_pe = in->nominal_t_pe;
in_plcp->dbw = (u8)in->dbw;
in_plcp->gi = (u8)in->gi;
in_plcp->ltf_type = (u8)in->he_ltf_type;
in_plcp->ness = in->ness;
in_plcp->mode_idx = (u8)in->mode;
in_plcp->max_tx_time_0p4us = in->max_tx_time_0p4us;
in_plcp->n_user = in->n_user;
in_plcp->ndp = in->ndp_en;
in_plcp->he_er_u106ru_en = in->he_er_u106ru_en;
in_plcp->tb_l_len = in->tb_l_len;
in_plcp->tb_ru_tot_sts_max = in->tb_ru_tot_sts_max;
in_plcp->tb_disam = in->tb_disam;
in_plcp->tb_ldpc_extra = in->tb_ldpc_extra;
in_plcp->tb_pre_fec_padding_factor = in->tb_pre_fec_padding_factor;
in_plcp->ht_l_len = in->ht_l_len;
for (i = 0; i < in_plcp->n_user; i++) {
in_plcp->usr[i].nss = (u8)in->usr[i].nss;
in_plcp->usr[i].fec = (u8)in->usr[i].fec;
in_plcp->usr[i].apep = in->usr[i].apep;
in_plcp->usr[i].dcm = (bool)in->usr[i].dcm;
in_plcp->usr[i].mcs = (u8)in->usr[i].mcs;
in_plcp->usr[i].mpdu_length_byte = (u16)in->usr[i].mpdu_len;
in_plcp->usr[i].n_mpdu = in->usr[i].n_mpdu;
}
if (in->ppdu_type == HE_SU_FMT) { //HE_SU
if (in->dbw == 0)
in->usr[0].ru_alloc = 122;
else if (in->dbw == 1)
in->usr[0].ru_alloc = 130;
else if (in->dbw == 2)
in->usr[0].ru_alloc = 134;
else
in->usr[0].ru_alloc = 137;
} else if (in->ppdu_type == HE_ER_SU_FMT) { //HE_ER_SU
if (in->he_er_u106ru_en)
in->usr[0].ru_alloc = 108;
else
in->usr[0].ru_alloc = 122;
}
}
void halbb_plcp_lsig(struct bb_info *bb, struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp,
enum phl_phy_idx phy_idx)
{
bool parity = 0;
u8 lsig_rate = 0;
u32 lsig_bits = 0;
u32 lsig = 0;
u8 i = 0;
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (in->ppdu_type == LEGACY_FMT) {
switch (in->usr[0].mcs) {
case 0:
lsig_rate = 11;
break;
case 1:
lsig_rate = 15;
break;
case 2:
lsig_rate = 10;
break;
case 3:
lsig_rate = 14;
break;
case 4:
lsig_rate = 9;
break;
case 5:
lsig_rate = 13;
break;
case 6:
lsig_rate = 8;
break;
case 7:
lsig_rate = 12;
break;
default:
break;
}
} else {
lsig_rate = 11;
}
lsig_bits = ((out_plcp->l_len) << 5) + lsig_rate;
for (i = 0; i < 17; i++)
parity ^= (lsig_bits >> i) % 2;
halbb_set_bit(0, 4, lsig_rate, &lsig);
halbb_set_bit(4, 1, 0, &lsig);// rsvd //
halbb_set_bit(5, 12, out_plcp->l_len, &lsig);
halbb_set_bit(17, 1, parity, &lsig);
halbb_set_bit(18, 6, 0, &lsig);
/*=== Write CR ===*/
halbb_set_reg_cmn(bb, cr->lsig, cr->lsig_m, lsig, phy_idx);
}
void halbb_plcp_siga(struct bb_info *bb, struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp,
enum phl_phy_idx phy_idx)
{
u32 siga1 = 0;
u32 siga2 = 0;
unsigned char siga_bits[64] = {0};
u8 crc8_out;
u8 crc4_out = 0;
u8 i = 0;
u8 n_he_ltf[8] = { 0, 1, 1, 2, 2, 3, 3, 4 };
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if ((in->ppdu_type == HE_SU_FMT) || (in->ppdu_type == HE_ER_SU_FMT)) { // HE_SU SIG-A //
/*=== SIG-A1 ===*/
halbb_set_bit(0, 1, 1, &siga1);
halbb_set_bit(1, 1, in->beamchange_en, &siga1);
halbb_set_bit(2, 1, in->ul_flag, &siga1);
halbb_set_bit(3, 4, in->usr[0].mcs, &siga1);
if ((in->gi == 1) && (in->he_ltf_type == 2))
halbb_set_bit(7, 1, 1, &siga1);
else
halbb_set_bit(7, 1, out_plcp->usr[0].dcm, &siga1);
halbb_set_bit(8, 6, in->bss_color, &siga1);
halbb_set_bit(14, 1, 1, &siga1); // rsvd //
halbb_set_bit(15, 4, in->sr, &siga1);
if (in->ppdu_type == HE_ER_SU_FMT) {
if (in->he_er_u106ru_en)
halbb_set_bit(19, 2, 1, &siga1);
else
halbb_set_bit(19, 2, 0, &siga1);
} else {
halbb_set_bit(19, 2, in->dbw, &siga1);
}
if (out_plcp->gi == 1 && in->he_ltf_type == 0)
halbb_set_bit(21, 2, 0, &siga1);// he_ltf_type & GI
else if (out_plcp->gi == 1 && in->he_ltf_type == 1)
halbb_set_bit(21, 2, 1, &siga1);
else if (out_plcp->gi == 2 && in->he_ltf_type == 1)
halbb_set_bit(21, 2, 2, &siga1);
else if ((out_plcp->gi == 1 && in->he_ltf_type == 2) || (out_plcp->gi == 3 && in->he_ltf_type == 2))
halbb_set_bit(21, 2, 3, &siga1);
halbb_set_bit(23, 3, out_plcp->usr[0].nsts-1, &siga1);//NSTS & Midamble// doppler //???????????????
/*=== SIG-A2 ===*/
halbb_set_bit(0, 7, in->txop, &siga2);
halbb_set_bit(7, 1, out_plcp->usr[0].fec, &siga2);
if (out_plcp->usr[0].fec == 0)
halbb_set_bit(8, 1, 1, &siga2);
else
halbb_set_bit(8, 1, out_plcp->ldpc_extra, &siga2);
if ((in->gi == 1) && (in->he_ltf_type == 2))
halbb_set_bit(9, 1, 1, &siga2);
else
halbb_set_bit(9, 1, out_plcp->stbc, &siga2);
halbb_set_bit(10, 1, 0, &siga2);//Beamformed? //
halbb_set_bit(11, 2, out_plcp->pre_fec_padding_factor, &siga2);
halbb_set_bit(13, 1, out_plcp->disamb, &siga2);
halbb_set_bit(14, 1, 1, &siga2); // rsvd //
halbb_set_bit(15, 1, out_plcp->doppler_en, &siga2);
//CRC4//
//--- Set HESIG1 ---
for(i = 0; i < 26; i++)
siga_bits[i] = ( siga1 >> i ) & 0x1 ;
//--- Set HESIG2 ---
for(i = 0; i < 16; i++)
siga_bits[i + 26] = ( siga2 >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, siga_bits, 42);
crc4_out = crc8_out & 0xf;
halbb_set_bit(16, 4, crc4_out, &siga2);
halbb_set_bit(20, 6, 0, &siga2);
}
else if (in->ppdu_type == HE_MU_FMT) { // HE MU SIG-A //
/*=== SIG-A1 ===*/
halbb_set_bit(0, 1, in->ul_flag, &siga1);
halbb_set_bit(1, 3, in->he_mcs_sigb, &siga1);
halbb_set_bit(4, 1, in->he_dcm_sigb, &siga1);
halbb_set_bit(5, 6, in->bss_color, &siga1);
halbb_set_bit(11, 4, in->sr, &siga1);
halbb_set_bit(15, 3, in->dbw, &siga1); // Bandwidth = DBW
halbb_set_bit(18, 4, out_plcp->n_sym_hesigb, &siga1);
halbb_set_bit(22, 1, 0, &siga1);
if (in->he_ltf_type == 2 && out_plcp->gi == 1)
halbb_set_bit(23, 2, 0, &siga1);// he_ltf_type & GI
else if (in->he_ltf_type == 1 && out_plcp->gi == 1)
halbb_set_bit(23, 2, 1, &siga1);
else if (in->he_ltf_type == 1 && out_plcp->gi == 2)
halbb_set_bit(23, 2, 2, &siga1);
else if (in->he_ltf_type == 2 && out_plcp->gi == 3)
halbb_set_bit(23, 2, 3, &siga1);
halbb_set_bit(25, 1, out_plcp->doppler_en, &siga1);
/*=== SIG-A2 ===*/
halbb_set_bit(0, 7, in->txop, &siga2);
halbb_set_bit(7, 1, 1, &siga2); //rsvd
halbb_set_bit(8, 3, n_he_ltf[out_plcp->n_ltf], &siga2);//N_LTF & Midamble// doppler
halbb_set_bit(11, 1, out_plcp->ldpc_extra, &siga2);// LDPC extra symbpl seg ldpc_extra
halbb_set_bit(12, 1, out_plcp->stbc, &siga2);
halbb_set_bit(13, 2, out_plcp->pre_fec_padding_factor, &siga2);
halbb_set_bit(15, 1, out_plcp->disamb, &siga2);
//CRC4//
//--- Set HESIG1 ---
for(i = 0; i < 26; i++)
siga_bits[i] = ( siga1 >> i ) & 0x1 ;
//--- Set HESIG2 ---
for(i = 0; i < 16; i++)
siga_bits[i + 26] = ( siga2 >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, siga_bits, 42);
crc4_out = crc8_out & 0xf;
halbb_set_bit(16, 4, crc4_out, &siga2);
halbb_set_bit(20, 6, 0, &siga2);
halbb_set_bit(20, 6, 0, &siga2);
}
else if (in->ppdu_type == HE_TB_FMT) { // HE_TB SIG-A //
/*=== SIG-A1 ===*/
halbb_set_bit(0, 1, 0, &siga1);
halbb_set_bit(1, 6, in->bss_color, &siga1);
halbb_set_bit(7, 4, in->ul_srp1, &siga1);
halbb_set_bit(11, 4, in->ul_srp2, &siga1);
halbb_set_bit(15, 4, in->ul_srp3, &siga1);
halbb_set_bit(19, 4, in->ul_srp4, &siga1);
halbb_set_bit(23, 1, 1, &siga1); // rsvd //
halbb_set_bit(24, 2, in->dbw, &siga1);
/*=== SIG-A2 ===*/
halbb_set_bit(0, 7, in->txop, &siga2);
halbb_set_bit(7, 9, in->tb_rsvd, &siga2);
//CRC4//
//--- Set HESIG1 ---
for(i = 0; i < 26; i++)
siga_bits[i] = ( siga1 >> i ) & 0x1 ;
//--- Set HESIG2 ---
for(i = 0; i < 16; i++)
siga_bits[i + 26] = ( siga2 >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, siga_bits, 42);
crc4_out = crc8_out & 0xf;
halbb_set_bit(16, 4, crc4_out, &siga2);
halbb_set_bit(20, 6, 0, &siga2);
}
else if (in->ppdu_type == VHT_FMT) {// VHT SIG-A //
/*=== SIG-A1 ===*/
halbb_set_bit(0, 2, in->dbw, &siga1);
halbb_set_bit(2, 1, 1, &siga1); // rsvd //
halbb_set_bit(3, 1, out_plcp->stbc, &siga1);
halbb_set_bit(4, 6, in->group_id, &siga1);
halbb_set_bit(10, 3, out_plcp->usr[0].nsts-1, &siga1); // NSS //
halbb_set_bit(13, 9, in->usr[0].aid, &siga1); // AID //
halbb_set_bit(22, 1, in->vht_txop_not_allowed, &siga1);
halbb_set_bit(23, 1, 1, &siga1);
/*=== SIG-A2 ===*/
if (out_plcp->gi == 0)
halbb_set_bit(0, 1, 1, &siga2); // Short GI //
else
halbb_set_bit(0, 1, 0, &siga2);
halbb_set_bit(1, 1, out_plcp->disamb, &siga2);
halbb_set_bit(2, 1, out_plcp->usr[0].fec, &siga2);
halbb_set_bit(3, 1, out_plcp->ldpc_extra, &siga2);
halbb_set_bit(4, 4, in->usr[0].mcs, &siga2);
halbb_set_bit(8, 1, 0, &siga2);//Beamformed? //
halbb_set_bit(9, 1, 1, &siga2);// rsvd //
//CRC8//
//--- Set HTSIG1 ---
for(i = 0; i < 24; i++)
siga_bits[i] = ( siga1 >> i ) & 0x1 ;
for(i = 0; i < 10; i++)
siga_bits[i+24] = ( siga2 >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, siga_bits, 34);
halbb_set_bit(10, 8, crc8_out, &siga2);
halbb_set_bit(18, 6, 0, &siga2);
}
else if (in->ppdu_type == HT_MF_FMT) {// HT_MF SIG-A //
/*=== SIG-A1 ===*/
halbb_set_bit(0, 7, in->usr[0].mcs, &siga1);
halbb_set_bit(7, 1, in->dbw, &siga1);
halbb_set_bit(8, 16, out_plcp->usr[0].apep_len, &siga1);
/*=== SIG-A2 ===*/
halbb_set_bit(0, 1, 1, &siga2);
halbb_set_bit(1, 1, ~in->ndp_en, &siga2);
halbb_set_bit(2, 1, 1, &siga2);
halbb_set_bit(3, 1, out_plcp->usr[0].n_mpdu > 1 ? 1 : 0, &siga2);
halbb_set_bit(4, 2, out_plcp->usr[0].nsts - out_plcp->usr[0].nss, &siga2);
halbb_set_bit(6, 1, out_plcp->usr[0].fec, &siga2);
if (out_plcp->gi == 0)
halbb_set_bit(7, 1, 1, &siga2);
else
halbb_set_bit(7, 1, 0, &siga2);
halbb_set_bit(8, 2, in->ness, &siga2);
//CRC8//
//--- Set HTSIG1 ---
for(i = 0; i < 24; i++)
siga_bits[i] = ( siga1 >> i ) & 0x1 ;
//--- Set HTSIG2 ---
for(i = 0; i < 10; i++)
siga_bits[i+24] = ( siga2 >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, siga_bits, 34);
halbb_set_bit(10, 8, crc8_out, &siga2);
halbb_set_bit(18, 6, 0, &siga2);
}
/*=== Write CR ===*/
halbb_set_reg_cmn(bb, cr->siga1, cr->siga1_m, siga1, phy_idx);
halbb_set_reg_cmn(bb, cr->siga2, cr->siga2_m, siga2, phy_idx);
}
void halbb_cfg_txinfo(struct bb_info *bb, struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp,
enum phl_phy_idx phy_idx)
{
u8 txinfo_ppdu = 0;
u8 ch20_with_data = 0;
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
halbb_set_reg_cmn(bb, cr->cfo_comp, cr->cfo_comp_m, 7, phy_idx);
halbb_set_reg_cmn(bb, cr->obw_cts2self_dup_type, cr->obw_cts2self_dup_type_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->txcmd_txtp, cr->txcmd_txtp_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->ul_cqi_rpt_tri, cr->ul_cqi_rpt_tri_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->rf_fixed_gain_en, cr->rf_fixed_gain_en_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->rf_gain_idx, cr->rf_gain_idx_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->cca_pw_th_en, cr->cca_pw_th_en_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->cca_pw_th, cr->cca_pw_th_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->ant_sel_a, cr->ant_sel_a_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->ant_sel_b, cr->ant_sel_b_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->ant_sel_c, cr->ant_sel_c_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->ant_sel_d, cr->ant_sel_d_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->dbw_idx, cr->dbw_idx_m, in->dbw, phy_idx);
halbb_set_reg_cmn(bb, cr->txsc, cr->txsc_m, in->txsc, phy_idx);
halbb_set_reg_cmn(bb, cr->source_gen_mode_idx, cr->source_gen_mode_idx_m, in->source_gen_mode, phy_idx);
// 'b"[7:0] means whether the corresponding channel20 contains legacy portion data in DBW
if (in->ppdu_type == HE_TB_FMT) {
switch (in->dbw) {
case 0:
if (((in->usr[0].ru_alloc >> 1) <= 8) || ((in->usr[0].ru_alloc >> 1) >= 37 && (in->usr[0].ru_alloc >> 1) <= 40)
|| (in->usr[0].ru_alloc >> 1) == 53 || (in->usr[0].ru_alloc >> 1) == 54 || (in->usr[0].ru_alloc >> 1) == 61)
ch20_with_data = 0x80;
break;
case 1:
if (((in->usr[0].ru_alloc >> 1) <= 8) || ((in->usr[0].ru_alloc >> 1) >= 37 && (in->usr[0].ru_alloc >> 1) <= 40)
|| (in->usr[0].ru_alloc >> 1) == 53 || (in->usr[0].ru_alloc >> 1) == 54 || (in->usr[0].ru_alloc >> 1) == 61)
ch20_with_data = 0x80;
else if (((in->usr[0].ru_alloc >> 1) >= 9 && (in->usr[0].ru_alloc >> 1) <= 17) || ((in->usr[0].ru_alloc >> 1) >= 41 && (in->usr[0].ru_alloc >> 1) <= 44)
|| (in->usr[0].ru_alloc >> 1) == 55 || (in->usr[0].ru_alloc >> 1) == 56 || (in->usr[0].ru_alloc >> 1) == 62)
ch20_with_data = 0x40;
else if ((in->usr[0].ru_alloc >> 1) == 65)
ch20_with_data = 0xc0;
break;
case 2:
if (((in->usr[0].ru_alloc >> 1) <= 8) || ((in->usr[0].ru_alloc >> 1) >= 37 && (in->usr[0].ru_alloc >> 1) <= 40)
|| (in->usr[0].ru_alloc >> 1) == 53 || (in->usr[0].ru_alloc >> 1) == 54 || (in->usr[0].ru_alloc >> 1) == 61)
ch20_with_data = 0x80;
else if (((in->usr[0].ru_alloc >> 1) >= 10 && (in->usr[0].ru_alloc >> 1) <= 17) || ((in->usr[0].ru_alloc >> 1) >= 42 && (in->usr[0].ru_alloc >> 1) <= 44)
|| (in->usr[0].ru_alloc >> 1) == 56)
ch20_with_data = 0x40;
else if ((in->usr[0].ru_alloc >> 1) == 9 || (in->usr[0].ru_alloc >> 1) == 41 || (in->usr[0].ru_alloc >> 1) == 55 || (in->usr[0].ru_alloc >> 1) == 62 || (in->usr[0].ru_alloc >> 1) == 65)
ch20_with_data = 0xc0;
else if (((in->usr[0].ru_alloc >> 1) >= 19 && (in->usr[0].ru_alloc >> 1) <= 26) || ((in->usr[0].ru_alloc >> 1) >= 45 && (in->usr[0].ru_alloc >> 1) <= 47)
|| (in->usr[0].ru_alloc >> 1) == 57)
ch20_with_data = 0x20;
else if (((in->usr[0].ru_alloc >> 1) >= 28 && (in->usr[0].ru_alloc >> 1) <= 36) || ((in->usr[0].ru_alloc >> 1) >= 49 && (in->usr[0].ru_alloc >> 1) <= 52)
|| (in->usr[0].ru_alloc >> 1) == 59 || (in->usr[0].ru_alloc >> 1) == 60 || (in->usr[0].ru_alloc >> 1) == 64)
ch20_with_data = 0x10;
else if ((in->usr[0].ru_alloc >> 1) == 27 || (in->usr[0].ru_alloc >> 1) == 48 || (in->usr[0].ru_alloc >> 1) == 58 || (in->usr[0].ru_alloc >> 1) == 63 || (in->usr[0].ru_alloc >> 1) == 66)
ch20_with_data = 0x30;
else if ((in->usr[0].ru_alloc >> 1) == 18)
ch20_with_data = 0x60;
else if ((in->usr[0].ru_alloc >> 1) == 67)
ch20_with_data = 0xf0;
break;
default:
break;
}
} else {
switch (in->dbw) {
case 0:
ch20_with_data = 0x80;
break;
case 1:
ch20_with_data = 0xc0;
break;
case 2:
ch20_with_data = 0xf0;
break;
case 3:
ch20_with_data = 0xff;
break;
default:
break;
}
}
halbb_set_reg_cmn(bb, cr->ch20_with_data, cr->ch20_with_data_m, ch20_with_data, phy_idx);
switch(in->ppdu_type) {
case B_MODE_FMT: //CCK
if (in->long_preamble_en)
txinfo_ppdu = 0;
else
txinfo_ppdu = 1;
break;
case LEGACY_FMT: //Legacy
txinfo_ppdu = 2;
break;
case HT_MF_FMT: //HT_MF
txinfo_ppdu = 3;
break;
case HT_GF_FMT: //HT_GF
txinfo_ppdu = 4;
break;
case VHT_FMT: //VHT
txinfo_ppdu = 5;
break;
case HE_SU_FMT: //HE_SU
txinfo_ppdu = 7;
break;
case HE_ER_SU_FMT: //HE_ER_SU
txinfo_ppdu = 8;
break;
case HE_MU_FMT: //HE_MU
txinfo_ppdu = 9;
break;
case HE_TB_FMT: //HE_TB
txinfo_ppdu = 10;
break;
default:
break;
}
halbb_set_reg_cmn(bb, cr->ppdu_type, cr->ppdu_type_m, txinfo_ppdu, phy_idx);
if (in->ppdu_type == B_MODE_FMT)
halbb_set_reg_cmn(bb, cr->n_usr, cr->n_usr_m, in->n_user, phy_idx);
else
halbb_set_reg_cmn(bb, cr->n_usr, cr->n_usr_m, out_plcp->n_usr, phy_idx);
}
void halbb_cfg_txctrl(struct bb_info *bb, struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp,
enum phl_phy_idx phy_idx)//Add random value
{
u8 i = 0;
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
u32 pw_boost_fac[4] = {cr->usr0_pw_boost_fctr_db, cr->usr1_pw_boost_fctr_db,
cr->usr2_pw_boost_fctr_db, cr->usr3_pw_boost_fctr_db};
u32 pw_boost_fac_m[4] = {cr->usr0_pw_boost_fctr_db_m ,cr->usr1_pw_boost_fctr_db_m,
cr->usr2_pw_boost_fctr_db_m, cr->usr3_pw_boost_fctr_db_m};
u32 dcm_en[4] = {cr->usr0_dcm_en, cr->usr1_dcm_en, cr->usr2_dcm_en,
cr->usr3_dcm_en};
u32 dcm_en_m[4] = {cr->usr0_dcm_en_m, cr->usr1_dcm_en_m, cr->usr2_dcm_en_m,
cr->usr3_dcm_en_m};
u32 mcs[4] = {cr->usr0_mcs, cr->usr1_mcs, cr->usr2_mcs, cr->usr3_mcs};
u32 mcs_m[4] = {cr->usr0_mcs_m, cr->usr1_mcs_m, cr->usr2_mcs_m, cr->usr3_mcs_m};
u32 fec[4] = {cr->usr0_fec_type, cr->usr1_fec_type, cr->usr2_fec_type, cr->usr3_fec_type};
u32 fec_m[4] = {cr->usr0_fec_type_m, cr->usr1_fec_type_m, cr->usr2_fec_type_m, cr->usr3_fec_type_m};
u32 n_sts[4] = {cr->usr0_n_sts, cr->usr1_n_sts, cr->usr2_n_sts, cr->usr3_n_sts};
u32 n_sts_m[4] = {cr->usr0_n_sts_m, cr->usr1_n_sts_m, cr->usr2_n_sts_m, cr->usr3_n_sts_m};
u32 n_sts_ru_tot[4] = {cr->usr0_n_sts_ru_tot, cr->usr1_n_sts_ru_tot,
cr->usr2_n_sts_ru_tot, cr->usr3_n_sts_ru_tot};
u32 n_sts_ru_tot_m[4] = {cr->usr0_n_sts_ru_tot_m, cr->usr1_n_sts_ru_tot_m,
cr->usr2_n_sts_ru_tot_m, cr->usr3_n_sts_ru_tot_m};
u32 ru_alloc[4] = {cr->usr0_ru_alloc, cr->usr1_ru_alloc, cr->usr2_ru_alloc,
cr->usr3_ru_alloc};
u32 ru_alloc_m[4] = {cr->usr0_ru_alloc_m, cr->usr1_ru_alloc_m, cr->usr2_ru_alloc_m,
cr->usr3_ru_alloc_m};
u32 txbf_en[4] = {cr->usr0_txbf_en, cr->usr1_txbf_en, cr->usr2_txbf_en,
cr->usr3_txbf_en};
u32 txbf_en_m[4] = {cr->usr0_txbf_en_m, cr->usr1_txbf_en_m, cr->usr2_txbf_en_m,
cr->usr3_txbf_en_m};
u32 precoding_mode_idx[4] = {cr->usr0_precoding_mode_idx, cr->usr1_precoding_mode_idx,
cr->usr2_precoding_mode_idx, cr->usr3_precoding_mode_idx};
u32 precoding_mode_idx_m[4] = {cr->usr0_precoding_mode_idx_m, cr->usr1_precoding_mode_idx_m,
cr->usr2_precoding_mode_idx_m, cr->usr3_precoding_mode_idx_m};
u32 csi_buf_id[4] = {cr->usr0_csi_buf_id, cr->usr1_csi_buf_id, cr->usr2_csi_buf_id,
cr->usr3_csi_buf_id};
u32 csi_buf_id_m[4] = {cr->usr0_csi_buf_id_m, cr->usr1_csi_buf_id_m,
cr->usr2_csi_buf_id_m, cr->usr3_csi_buf_id_m};
u32 strt_sts[4] = {cr->usr0_strt_sts, cr->usr1_strt_sts, cr->usr2_strt_sts,
cr->usr3_strt_sts};
u32 strt_sts_m[4] = {cr->usr0_strt_sts_m, cr->usr1_strt_sts_m, cr->usr2_strt_sts_m,
cr->usr3_strt_sts_m};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// Default value //
// When HE_TB NDP, it's valid; o.w., it's RSVD and set to 1'b0
halbb_set_reg_cmn(bb, cr->feedback_status, cr->feedback_status_m, 0, phy_idx);
// Whether this PPDU contains data field or not. 0: with data field, 1:without data field
halbb_set_reg_cmn(bb, cr->ndp, cr->ndp_m, 0, phy_idx);
// it's RSVD except HE PPDU and set to 1'b0 when it's RSVD 0: disable MU-MIMO-LTF-Mode, 1: enable MU-MIMO-LTF-Mode
halbb_set_reg_cmn(bb, cr->mumimo_ltf_mode_en, cr->mumimo_ltf_mode_en_m, 0, phy_idx);
// it's RSVD except VHT_MU and HE_MU. When it's RSVD, it shall be set to 1'b0 0: non-full-bandwidth-MU-MIMO, 1: full-bandwidth-MU-MIMO
halbb_set_reg_cmn(bb, cr->fb_mumimo_en, cr->fb_mumimo_en_m, 0, phy_idx);
// usr value //
// U_ID
halbb_set_reg_cmn(bb, cr->usr0_u_id, cr->usr0_u_id_m, 0, phy_idx);
halbb_set_reg_cmn(bb, cr->usr1_u_id, cr->usr1_u_id_m, 1, phy_idx);
halbb_set_reg_cmn(bb, cr->usr2_u_id, cr->usr2_u_id_m, 2, phy_idx);
halbb_set_reg_cmn(bb, cr->usr3_u_id, cr->usr3_u_id_m, 3, phy_idx);
// Input Interface //
// When HE_MU, whether to apply DCM is HE-SIGB or not; o.w., it's RSVD and set to 1'b0
if (in->ppdu_type != HE_MU_FMT)
halbb_set_reg_cmn(bb, cr->he_sigb_dcm_en, cr->he_sigb_dcm_en_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->he_sigb_dcm_en, cr->he_sigb_dcm_en_m, in->he_dcm_sigb, phy_idx);//0: disable, 1:enable
// When HE_MU, the MCS for HE-SIGB or not; o.w., it's RSVD and set to 3'b0
if (in->ppdu_type != HE_MU_FMT)
halbb_set_reg_cmn(bb, cr->he_sigb_mcs, cr->he_sigb_mcs_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->he_sigb_mcs, cr->he_sigb_mcs_m, in->he_mcs_sigb, phy_idx);
// When HE_SU or HE_ER_SU, it means whether to apply beam_change or not; o.w. it's RSVD and set to 1'b1 for OFDM and set to 1'b0 for b_mode.
if (in->ppdu_type == B_MODE_FMT)
halbb_set_reg_cmn(bb, cr->beam_change_en, cr->beam_change_en_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->beam_change_en, cr->beam_change_en_m, in->beamchange_en, phy_idx);
// The number of LTF. The definition is on the right-hand side. it's RSVD when b_mode and Legacy. When it's RSVD, it shall be set to 3'b0.
if (in->ppdu_type == B_MODE_FMT || in->ppdu_type == LEGACY_FMT)
halbb_set_reg_cmn(bb, cr->n_ltf, cr->n_ltf_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->n_ltf, cr->n_ltf_m, out_plcp->n_ltf, phy_idx);
// 0: LTF_type1x, 1: LTF_type2x, 2: LTF_type4x, 3:RSVD
if (in->ppdu_type < HE_SU_FMT)
halbb_set_reg_cmn(bb, cr->ltf_type, cr->ltf_type_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->ltf_type, cr->ltf_type_m, in->he_ltf_type, phy_idx);
// 0: GI_0p4us, 1: GI_0p8us, 2:GI_1p6us, 3:GI_3p2us
if (in->ppdu_type == B_MODE_FMT)
halbb_set_reg_cmn(bb, cr->gi_type, cr->gi_type_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->gi_type, cr->gi_type_m, out_plcp->gi, phy_idx);
// it's RSVD except HE PPDU when Doppler=enable. When it's RSVD, it shall be set to 1'b0
if (!((in->ppdu_type > VHT_FMT) && out_plcp->doppler_en))
halbb_set_reg_cmn(bb, cr->midamble_mode, cr->midamble_mode_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->midamble_mode, cr->midamble_mode_m, out_plcp->midamble, phy_idx);
// it's RSVD expect HE PPDU. It shall be set to 1'b0
if (in->ppdu_type < HE_SU_FMT)
halbb_set_reg_cmn(bb, cr->doppler_en, cr->doppler_en_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->doppler_en, cr->doppler_en_m, out_plcp->doppler_en, phy_idx);
// It's RSVD when b_mode and Legacy, and shall be set to 1'b0. For 8852A, STBC only support NSS * 2 = NSTS
if (in->ppdu_type == B_MODE_FMT || in->ppdu_type == LEGACY_FMT)
halbb_set_reg_cmn(bb, cr->stbc_en, cr->stbc_en_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->stbc_en, cr->stbc_en_m, out_plcp->stbc, phy_idx);
// usr0 value //
// The power boost factor applied in corresponding RU in pwr. S(5,2)
// Initialize
for (i = 0; i < 4; i++) {
halbb_set_reg_cmn(bb, pw_boost_fac[i], pw_boost_fac_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, dcm_en[i], dcm_en_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, mcs[i], mcs_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, fec[i], fec_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, n_sts[i], n_sts_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, n_sts_ru_tot[i], n_sts_ru_tot_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, ru_alloc[i], ru_alloc_m[i], 0, phy_idx);
// Txbf
if (bb->ic_type == BB_RTL8852A || bb->ic_type == BB_RTL8852B)
halbb_set_reg_cmn(bb, txbf_en[i], txbf_en_m[i], 0, phy_idx);
else
halbb_set_reg_cmn(bb, precoding_mode_idx[i], precoding_mode_idx_m[i], 0, phy_idx);
// CSI buf_id
halbb_set_reg_cmn(bb, csi_buf_id[i], csi_buf_id_m[i], 0, phy_idx);
// Strt sts
halbb_set_reg_cmn(bb, strt_sts[i], strt_sts_m[i], 0, phy_idx);
}
for (i = 0; i < in->n_user; i++) {
halbb_set_reg_cmn(bb, pw_boost_fac[i], pw_boost_fac_m[i], in->usr[i].pwr_boost_db, phy_idx);
// Whether the user applies DCM; it's RSVD when STBC or MU-MIMO
if (!out_plcp->stbc) // if (!STBC)
halbb_set_reg_cmn(bb, dcm_en[i], dcm_en_m[i], out_plcp->usr[i].dcm, phy_idx);
// The modulation and coding scheme applied to the user.For 8852A, HT(0~31), VHT/HE(0~11), OFDM(0~8), bmode(0~3); otherwise, it's RSVD
halbb_set_reg_cmn(bb, mcs[i], mcs_m[i], in->usr[i].mcs, phy_idx);
// 0: BCC, 1:LDPC
if (in->ppdu_type == B_MODE_FMT)
halbb_set_reg_cmn(bb, fec[i], fec_m[i], 0, phy_idx);
else
halbb_set_reg_cmn(bb, fec[i], fec_m[i], out_plcp->usr[i].fec, phy_idx);
// The number of space-time-stream
halbb_set_reg_cmn(bb, n_sts[i], n_sts_m[i], out_plcp->usr[i].nsts - 1, phy_idx);
// N_STS_RU_total - 1
halbb_set_reg_cmn(bb, n_sts_ru_tot[i], n_sts_ru_tot_m[i], out_plcp->usr[i].nsts - 1, phy_idx);
// For all PPDU excepts HE_SU, HE_ER_SU, HE_MU, HE_TB, are RSVD and shall be set to 8'b0
if (in->ppdu_type < HE_SU_FMT)
halbb_set_reg_cmn(bb, ru_alloc[i], ru_alloc_m[i], 0, phy_idx);
else
halbb_set_reg_cmn(bb, ru_alloc[i], ru_alloc_m[i], in->usr[i].ru_alloc, phy_idx);
}
// it's RSVD except HE PPDU and shall be set to 2'b0
if (in->ppdu_type < HE_SU_FMT)
halbb_set_reg_cmn(bb, cr->pre_fec_fctr, cr->pre_fec_fctr_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->pre_fec_fctr, cr->pre_fec_fctr_m, out_plcp->pre_fec_padding_factor, phy_idx);
// it's RSVD except HE-PPDU and shall be set to 2'b0. it means the duration for packet extension field
if (in->ppdu_type < HE_SU_FMT)
halbb_set_reg_cmn(bb, cr->pkt_ext_idx, cr->pkt_ext_idx_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->pkt_ext_idx, cr->pkt_ext_idx_m, out_plcp->t_pe, phy_idx);
// 0: without LDPC extra, 1: with LDPC extra
halbb_set_reg_cmn(bb, cr->ldpc_extr, cr->ldpc_extr_m, out_plcp->ldpc_extra, phy_idx);
// The number of data symbols in HE-SIGB. It is RSVD except HE_MU and shall be set to 6'b0
if (in->ppdu_type != HE_MU_FMT)
halbb_set_reg_cmn(bb, cr->n_sym_hesigb, cr->n_sym_hesigb_m, 0, phy_idx);
else
halbb_set_reg_cmn(bb, cr->n_sym_hesigb, cr->n_sym_hesigb_m, out_plcp->n_sym_hesigb, phy_idx);
// It means the number of data symbols in data_field, which the number of midamble symbols are excluded
halbb_set_reg_cmn(bb, cr->n_sym, cr->n_sym_m, out_plcp->n_sym, phy_idx);
}
void halbb_plcp_delimiter(struct bb_info *bb, struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp,
enum phl_phy_idx phy_idx) //Add random value
{
u8 crc8_out = 0;
u16 tmp = 0;
u32 delimiter = 0;
unsigned char delimiter_crc[32] = {0};
u8 i = 0;
u8 j = 0;
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
u32 delmter[4] = {cr->usr0_delmter, cr->usr1_delmter, cr->usr2_delmter,
cr->usr3_delmter};
u32 delmter_m[4] = {cr->usr0_delmter_m, cr->usr1_delmter_m,
cr->usr2_delmter_m, cr->usr3_delmter_m};
u32 mpdu_len[4] = {cr->usr0_mdpu_len_byte, cr->usr1_mdpu_len_byte,
cr->usr2_mdpu_len_byte, cr->usr3_mdpu_len_byte};
u32 mpdu_len_m[4] = {cr->usr0_mdpu_len_byte_m, cr->usr1_mdpu_len_byte_m,
cr->usr2_mdpu_len_byte_m, cr->usr3_mdpu_len_byte_m};
u32 n_mpdu[4] = {cr->usr0_n_mpdu, cr->usr1_n_mpdu, cr->usr2_n_mpdu,
cr->usr3_n_mpdu};
u32 n_mpdu_m[4] = {cr->usr0_n_mpdu_m, cr->usr1_n_mpdu_m, cr->usr2_n_mpdu_m,
cr->usr3_n_mpdu_m};
u32 eof_padding_len[4] = {cr->usr0_eof_padding_len, cr->usr1_eof_padding_len,
cr->usr2_eof_padding_len, cr->usr3_eof_padding_len};
u32 eof_padding_len_m[4] = {cr->usr0_eof_padding_len_m, cr->usr1_eof_padding_len_m,
cr->usr2_eof_padding_len_m, cr->usr3_eof_padding_len_m};
u32 init_seed[4] = {cr->usr0_init_seed, cr->usr1_init_seed,
cr->usr2_init_seed, cr->usr3_init_seed};
u32 init_seed_m[4] = {cr->usr0_init_seed_m, cr->usr1_init_seed_m,
cr->usr2_init_seed_m, cr->usr3_init_seed_m};
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
// Initialize
for (i = 0; i < 4; i++) {
halbb_set_reg_cmn(bb, delmter[i], delmter_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, mpdu_len[i], mpdu_len_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, n_mpdu[i], n_mpdu_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, eof_padding_len[i], eof_padding_len_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, init_seed[i], init_seed_m[i], 0, phy_idx);
}
for (i = 0; i < in->n_user; i++) {
//=== [Delimiter] ===//
if (out_plcp->usr[i].n_mpdu == 1)
halbb_set_bit(0, 1, 1, &delimiter);
else
halbb_set_bit(0, 1, 0, &delimiter);
halbb_set_bit(1, 1, 0, &delimiter); //rsvd
halbb_set_bit(2, 2, out_plcp->usr[i].mpdu_length_byte >> 12, &delimiter);
tmp = out_plcp->usr[i].mpdu_length_byte & 0xfff;
halbb_set_bit(4, 12, tmp, &delimiter);
//CRC8//
//--- Set Delimiter ---
for(j = 0; j < 16; j++)
delimiter_crc[j] = ( delimiter >> j ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, delimiter_crc, 16);
halbb_set_bit(16, 8, crc8_out, &delimiter);
halbb_set_bit(24, 8, 0x4e, &delimiter); // MSB [01001110] LSB
/*=== Write CR ===*/
halbb_set_reg_cmn(bb, delmter[i], delmter_m[i], delimiter, phy_idx);
//=== [MPDU Length] ===//
halbb_set_reg_cmn(bb, mpdu_len[i], mpdu_len_m[i], out_plcp->usr[i].mpdu_length_byte, phy_idx);
//=== [N_MPDU] ===//
halbb_set_reg_cmn(bb, n_mpdu[i], n_mpdu_m[i], out_plcp->usr[i].n_mpdu, phy_idx);
//=== [EOF Padding Length] ===//
halbb_set_reg_cmn(bb, eof_padding_len[i], eof_padding_len_m[i], out_plcp->usr[i].eof_padding_length * 8, phy_idx);
//=== [Init seed] ===//
halbb_set_reg_cmn(bb, init_seed[i], init_seed_m[i], in->usr[i].random_init_seed, phy_idx);
}
}
void halbb_cfg_cck(struct bb_info *bb, struct halbb_plcp_info *in, enum phl_phy_idx phy_idx)
{
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
if (bb->ic_type == BB_RTL8852A || bb->ic_type == BB_RTL8852B) {
// === 11b_tx_pmac_psdu_byte === //
halbb_set_reg(bb, cr->b_psdu_byte, cr->b_psdu_byte_m, in->usr[0].apep);
// === 11b_tx_pmac_psdu_type === //
halbb_set_reg(bb, cr->b_ppdu_type, cr->b_ppdu_type_m, ~in->long_preamble_en);
// === 11b_tx_pmac_psdu_rate === //
halbb_set_reg(bb, cr->b_psdu_rate, cr->b_psdu_rate_m, in->usr[0].mcs);
// === 11b_tx_pmac_service_bit2 === //
halbb_set_reg(bb, cr->b_service_bit2, cr->b_service_bit2_m, 1);
} else {
// === 11b_tx_pmac_psdu_byte === //
halbb_set_reg_cmn(bb, cr->usr0_mdpu_len_byte, cr->usr0_mdpu_len_byte_m, in->usr[0].apep, phy_idx);
// === 11b_tx_pmac_psdu_type === //
halbb_set_reg_cmn(bb, cr->ppdu_type, cr->ppdu_type_m, ~in->long_preamble_en, phy_idx);
// === 11b_tx_pmac_psdu_rate === //
halbb_set_reg(bb, cr->b_rate_idx, cr->b_rate_idx_m, in->usr[0].mcs);
// === 11b_tx_pmac_service_bit2 === //
halbb_set_reg(bb, cr->b_locked_clk_en, cr->b_locked_clk_en_m, 1);
}
// === 11b_tx_pmac_carrier_suppress_tx === //
halbb_set_reg(bb, cr->b_carrier_suppress_tx, cr->b_carrier_suppress_tx_m, 0);
// === 11b_tx_pmac_psdu_header === //
halbb_set_reg(bb, cr->b_header_0, cr->b_header_0_m, 0x3020100);
halbb_set_reg(bb, cr->b_header_1, cr->b_header_1_m, 0x7060504);
halbb_set_reg(bb, cr->b_header_2, cr->b_header_2_m, 0xb0a0908);
halbb_set_reg(bb, cr->b_header_3, cr->b_header_3_m, 0xf0e0d0c);
halbb_set_reg(bb, cr->b_header_4, cr->b_header_4_m, 0x13121110);
halbb_set_reg(bb, cr->b_header_5, cr->b_header_5_m, 0x17161514);
}
void halbb_vht_sigb(struct bb_info *bb, struct halbb_plcp_info *in,
struct plcp_tx_pre_fec_padding_setting_out_t *out_plcp,
enum phl_phy_idx phy_idx)
{
// VHT SU
u8 crc8_out = 0;
u8 scrambler_seed = 0;
u32 vht_sigb = 0;
unsigned char sigb[32] = {0};
u8 i = 0;
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
u32 vht_sigb_cr[4] = {cr->vht_sigb0, cr->vht_sigb1, cr->vht_sigb2,
cr->vht_sigb3};
u32 vht_sigb_cr_m[4] = {cr->vht_sigb0_m, cr->vht_sigb1_m, cr->vht_sigb2_m,
cr->vht_sigb3_m};
u32 service[4] = {cr->usr0_service, cr->usr1_service, cr->usr2_service,
cr->usr3_service};
u32 service_m[4] = {cr->usr0_service_m, cr->usr1_service_m,
cr->usr2_service_m, cr->usr3_service_m};
// Initialize
for (i = 0; i < 4; i++) {
halbb_set_reg_cmn(bb, vht_sigb_cr[i], vht_sigb_cr_m[i], 0, phy_idx);
halbb_set_reg_cmn(bb, service[i], service_m[i], 0, phy_idx);
}
switch (in->dbw) {//0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80
case 0:
halbb_set_bit(0, 17, halbb_ceil(out_plcp->usr[0].apep_len, 4), &vht_sigb);
halbb_set_bit(17, 3, 0x7, &vht_sigb);
//--- Set VHT SigB ---
for(i = 0; i < 20; i++)
sigb[i] = ( vht_sigb >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, sigb, 20);
halbb_set_bit(20, 6, 0x0, &vht_sigb);
break;
case 1:
halbb_set_bit(0, 19, halbb_ceil(out_plcp->usr[0].apep_len, 4), &vht_sigb);
halbb_set_bit(19, 2, 0x3, &vht_sigb);
//--- Set VHT SigB ---
for(i = 0; i < 21; i++)
sigb[i] = ( vht_sigb >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, sigb, 21);
halbb_set_bit(21, 6, 0x0, &vht_sigb);
break;
case 2:
case 3:
halbb_set_bit(0, 21, halbb_ceil(out_plcp->usr[0].apep_len, 4), &vht_sigb);
halbb_set_bit(21, 2, 0x3, &vht_sigb);
//--- Set VHT SigB ---
for(i = 0; i < 23; i++)
sigb[i] = ( vht_sigb >> i ) & 0x1 ;
crc8_out = halbb_set_crc8(bb, sigb, 23);
halbb_set_bit(23, 6, 0x0, &vht_sigb);
break;
default:
break;
}
//=== [Service] ===//
scrambler_seed = in->usr[0].scrambler_seed & 0x7f;
halbb_set_reg_cmn(bb, service[0], service_m[0], (crc8_out << 8) + scrambler_seed, phy_idx);
halbb_set_reg_cmn(bb, vht_sigb_cr[0], vht_sigb_cr_m[0], vht_sigb, phy_idx);
}
void halbb_service(struct bb_info *bb, struct halbb_plcp_info *in,
enum phl_phy_idx phy_idx)
{
u8 i = 0;
u32 scrambler_seed[4] = {0};
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
u32 service[4] = {cr->usr0_service, cr->usr1_service, cr->usr2_service,
cr->usr3_service};
u32 service_m[4] = {cr->usr0_service_m, cr->usr1_service_m,
cr->usr2_service_m, cr->usr3_service_m};
for (i = 0; i < 4; i++)
halbb_set_reg_cmn(bb, service[i], service_m[i], 0, phy_idx);
for(i = 0; i < in->n_user; i++) {
//=== [Service] ===//
scrambler_seed[i] = in->usr[i].scrambler_seed & 0x7f;
halbb_set_reg_cmn(bb, service[i], service_m[i], scrambler_seed[i], phy_idx);
}
}
void halbb_he_sigb(struct bb_info *bb, struct halbb_plcp_info *in,
enum phl_phy_idx phy_idx)
{
struct bb_h2c_he_sigb *he_sigb = &bb->bb_h2c_he_sigb_i;
u8 i = 0;
u16 cmdlen;
bool ret_val = false;
u32 *bb_h2c = (u32 *)he_sigb;
struct bb_plcp_cr_info *cr = &bb->bb_plcp_i.bb_plcp_cr_i;
u32 n_sym_sigb_ch1_phy0[16] = {cr->he_sigb_ch1_0, cr->he_sigb_ch1_1,
cr->he_sigb_ch1_2, cr->he_sigb_ch1_3,
cr->he_sigb_ch1_4, cr->he_sigb_ch1_5,
cr->he_sigb_ch1_6, cr->he_sigb_ch1_7,
cr->he_sigb_ch1_8, cr->he_sigb_ch1_9,
cr->he_sigb_ch1_10, cr->he_sigb_ch1_11,
cr->he_sigb_ch1_12, cr->he_sigb_ch1_13,
cr->he_sigb_ch1_14, cr->he_sigb_ch1_15};
u32 n_sym_sigb_ch2_phy0[16] = {cr->he_sigb_ch2_0, cr->he_sigb_ch2_1,
cr->he_sigb_ch2_2, cr->he_sigb_ch2_3,
cr->he_sigb_ch2_4, cr->he_sigb_ch2_5,
cr->he_sigb_ch2_6, cr->he_sigb_ch2_7,
cr->he_sigb_ch2_8, cr->he_sigb_ch2_9,
cr->he_sigb_ch2_10, cr->he_sigb_ch2_11,
cr->he_sigb_ch2_12, cr->he_sigb_ch2_13,
cr->he_sigb_ch2_14, cr->he_sigb_ch2_15};
for (i = 0; i < 16; i++) {
halbb_set_reg(bb, n_sym_sigb_ch1_phy0[i], MASKDWORD, 0);
halbb_set_reg(bb, n_sym_sigb_ch2_phy0[i], MASKDWORD, 0);
}
if (phy_idx == HW_PHY_0) {
for (i = 0; i < 16; i++) {
he_sigb->n_sym_sigb_ch1[i].address= n_sym_sigb_ch1_phy0[i];
he_sigb->n_sym_sigb_ch2[i].address = n_sym_sigb_ch2_phy0[i];
}
} /*else {
for (i = 0; i < 16; i++) {
he_sigb->n_sym_sigb_ch1[i] = n_sym_sigb_ch1_phy1[i];
he_sigb->n_sym_sigb_ch2[i] = n_sym_sigb_ch2_phy1[i];
}
}*/
cmdlen = sizeof(struct bb_h2c_he_sigb);
he_sigb->dl_rua_out.ppdu_bw = (u16)in->dbw;
he_sigb->dl_rua_out.sta_list_num = (u8)in->n_user;
he_sigb->dl_rua_out.fixed_mode = 1;
he_sigb->force_sigb_rate = 1; // Force SIGB MCS & DCM setting
he_sigb->force_sigb_mcs = (u8)in->he_mcs_sigb;
he_sigb->force_sigb_dcm = (u8)in->he_dcm_sigb;
for (i = 0; i < in->n_user; i++) {
he_sigb->dl_rua_out.dl_output_sta_list[i].dropping_flag = 0;
he_sigb->dl_rua_out.dl_output_sta_list[i].txbf = (u8)in->usr[i].txbf;
he_sigb->dl_rua_out.dl_output_sta_list[i].coding = (u8)in->usr[i].fec;
he_sigb->dl_rua_out.dl_output_sta_list[i].nsts = (u8)(in->usr[i].nss << in->stbc) - 1;
he_sigb->dl_rua_out.dl_output_sta_list[i].mac_id = i;
he_sigb->dl_rua_out.dl_output_sta_list[i].ru_position = (u8)in->usr[i].ru_alloc << 1;
//he_sigb->dl_rua_out.dl_output_sta_list[i].aid = (u16)in->usr[i].aid;
he_sigb->aid12[i] = (u16)in->usr[i].aid;
he_sigb->dl_rua_out.dl_output_sta_list[i].ru_rate.dcm = (u8)in->usr[i].dcm;
he_sigb->dl_rua_out.dl_output_sta_list[i].ru_rate.mcs = (u8)in->usr[i].mcs;
he_sigb->dl_rua_out.dl_output_sta_list[i].ru_rate.ss = (u8)in->usr[i].nss;
}
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FW_HE_SIGB,
HALBB_H2C_DM, bb_h2c);
/*
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 NSS = %d\n", in->usr[0].nss);
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 MCS = %d\n", in->usr[0].mcs);
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 AID = %d\n", in->usr[0].aid);
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 ru position = %d\n", he_sigb->dl_rua_out.dl_output_sta_list[0].ru_position);
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User0 dropping flag = %d\n", he_sigb->dl_rua_out.dl_output_sta_list[0].dropping_flag);
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] SIGB Addr = 0x%x, Mask = 0x%x\n",
he_sigb->n_sym_sigb_ch1[0].address, he_sigb->n_sym_sigb_ch1[0].bitmask);
*/
}
enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in,
struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx)
{
u16 i = 0;
u8 he_sigb_c2h[2] = {0};
bool he_sigb_valid = false;
bool he_sigb_pol = false;
u16 he_n_sigb_sym = 0;
u32 he_sigb_tmp = 0;
enum plcp_sts tmp = PLCP_SUCCESS;
struct plcp_tx_pre_fec_padding_setting_in_t in_plcp;
struct plcp_tx_pre_fec_padding_setting_out_t out;
//struct _bb_result he_result;
halbb_mem_cpy(bb, in->usr, user, 4*sizeof(struct usr_plcp_gen_in));
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
rtw_halbb_plcp_gen_init(in, &in_plcp);
// HE SIG-B
if (in->ppdu_type == HE_MU_FMT) {
halbb_he_sigb(bb, in, phy_idx);
for (i = 0; i < 500; i++) {
halbb_delay_us(bb, 10);
he_sigb_pol = (bool)halbb_get_reg(bb, 0xfc, BIT(16));
if (he_sigb_pol) {
he_sigb_valid = (bool)halbb_get_reg(bb, 0xfc, BIT(8));
he_n_sigb_sym = (u16)halbb_get_reg(bb, 0xfc, 0x3f);
in_plcp.n_hesigb_sym = he_n_sigb_sym;
break;
}
}
for (i = 0; i < in->n_user; i++) {
// === Set ru_size_idx === //
if(in->usr[i].ru_alloc < 37)
in_plcp.usr[i].ru_size_idx = 0;
else if(in->usr[i].ru_alloc < 53)
in_plcp.usr[i].ru_size_idx = 1;
else if(in->usr[i].ru_alloc < 61)
in_plcp.usr[i].ru_size_idx = 2;
else if(in->usr[i].ru_alloc < 65)
in_plcp.usr[i].ru_size_idx = 3;
else if(in->usr[i].ru_alloc < 67)
in_plcp.usr[i].ru_size_idx = 4;
else
in_plcp.usr[i].ru_size_idx = 5;
in->usr[i].ru_alloc = (in->usr[i].ru_alloc << 1);
BB_DBG(bb, DBG_PHY_CONFIG, "[SIGB] User%d RU_alloc = %d\n", i, in->usr[i].ru_alloc);
}
}
if (in->ppdu_type == HE_TB_FMT) {
in->n_user = 1;
// === Set ru_size_idx === //
if(in->usr[0].ru_alloc < 37)
in_plcp.usr[0].ru_size_idx = 0;
else if(in->usr[0].ru_alloc < 53)
in_plcp.usr[0].ru_size_idx = 1;
else if(in->usr[0].ru_alloc < 61)
in_plcp.usr[0].ru_size_idx = 2;
else if(in->usr[0].ru_alloc < 65)
in_plcp.usr[0].ru_size_idx = 3;
else if(in->usr[0].ru_alloc < 67)
in_plcp.usr[0].ru_size_idx = 4;
else
in_plcp.usr[0].ru_size_idx = 5;
in->usr[0].ru_alloc = (in->usr[0].ru_alloc << 1);
}
// CCK
if (in->ppdu_type == B_MODE_FMT) {
halbb_cfg_cck(bb, in, phy_idx);
if ((in->usr[0].mcs == 0) && (in->long_preamble_en == 0))
tmp = CCK_INVALID;
} else {
tmp = halbb_tx_plcp_cal(bb, &in_plcp, &out);
// VHT SIG-B
if (in->ppdu_type == VHT_FMT)
halbb_vht_sigb(bb, in, &out, phy_idx);
else
halbb_service(bb, in, phy_idx);
// L-SIG
halbb_plcp_lsig(bb, in, &out, phy_idx);
// SIG-A
if (in->ppdu_type > LEGACY_FMT)
halbb_plcp_siga(bb, in, &out, phy_idx);
// Tx Ctrl Info
halbb_cfg_txctrl(bb, in, &out, phy_idx);
// Delimiter
halbb_plcp_delimiter(bb, in, &out, phy_idx);
}
// Tx Info
halbb_cfg_txinfo(bb, in, &out, phy_idx);
// === [Global Verification Setting] === //
#ifdef BB_8852A_CAV_SUPPORT
if (bb->ic_type == BB_RTL8852AA)
halbb_plcp_gen_homologation_8852a (bb, in);
#endif
// ===================================== //
return tmp;
}
void halbb_cr_cfg_plcp_init(struct bb_info *bb)
{
struct bb_plcp_info *plcp_info = &bb->bb_plcp_i;
struct bb_plcp_cr_info *cr = &plcp_info->bb_plcp_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_52AA:
cr->b_header_0 = R1B_TX_PMAC_HEADER_0_52AA;
cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_52AA_M;
cr->b_header_1 = R1B_TX_PMAC_HEADER_1_52AA;
cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_52AA_M;
cr->b_header_2 = R1B_TX_PMAC_HEADER_2_52AA;
cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_52AA_M;
cr->b_header_3 = R1B_TX_PMAC_HEADER_3_52AA;
cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_52AA_M;
cr->b_header_4 = R1B_TX_PMAC_HEADER_4_52AA;
cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_52AA_M;
cr->b_header_5 = R1B_TX_PMAC_HEADER_5_52AA;
cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_52AA_M;
cr->b_psdu_byte = R1B_TX_PMAC_PSDU_BYTE_52AA;
cr->b_psdu_byte_m = R1B_TX_PMAC_PSDU_BYTE_52AA_M;
cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_52AA;
cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_52AA_M;
cr->b_ppdu_type = R1B_TX_PMAC_PPDU_TYPE_52AA;
cr->b_ppdu_type_m = R1B_TX_PMAC_PPDU_TYPE_52AA_M;
cr->b_psdu_rate = R1B_TX_PMAC_PSDU_RATE_52AA;
cr->b_psdu_rate_m = R1B_TX_PMAC_PSDU_RATE_52AA_M;
cr->b_service_bit2 = R1B_TX_PMAC_SERVICE_BIT2_52AA;
cr->b_service_bit2_m = R1B_TX_PMAC_SERVICE_BIT2_52AA_M;
cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_52AA;
cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_52AA_M;
cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_52AA;
cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_52AA_M;
cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_52AA;
cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_52AA_M;
cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_52AA;
cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_52AA_M;
cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_52AA;
cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_52AA_M;
cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_52AA;
cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_52AA_M;
cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_52AA;
cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_52AA_M;
cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_52AA;
cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_52AA_M;
cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_52AA;
cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_52AA_M;
cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_52AA;
cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_52AA_M;
cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_52AA;
cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_52AA_M;
cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_52AA;
cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_52AA_M;
cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_52AA;
cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_52AA_M;
cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_52AA;
cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_52AA_M;
cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_52AA;
cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_52AA_M;
cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_52AA;
cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_52AA_M;
cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_52AA;
cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_52AA_M;
cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_52AA;
cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_52AA_M;
cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_52AA;
cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_52AA_M;
cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_52AA;
cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_52AA_M;
cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_52AA;
cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_52AA_M;
cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_52AA;
cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_52AA_M;
cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_52AA;
cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_52AA_M;
cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_52AA;
cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_52AA_M;
cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_52AA;
cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_52AA_M;
cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_52AA;
cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_52AA_M;
cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_52AA;
cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_52AA_M;
cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_52AA;
cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_52AA_M;
cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_52AA;
cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_52AA_M;
cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_52AA;
cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_52AA_M;
cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_52AA;
cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_52AA_M;
cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_52AA;
cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_52AA_M;
cr->usr0_delmter = USER0_DELMTER_52AA;
cr->usr0_delmter_m = USER0_DELMTER_52AA_M;
cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_52AA;
cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_52AA_M;
cr->usr0_init_seed = USER0_INIT_SEED_52AA;
cr->usr0_init_seed_m = USER0_INIT_SEED_52AA_M;
cr->usr1_delmter = USER1_DELMTER_52AA;
cr->usr1_delmter_m = USER1_DELMTER_52AA_M;
cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_52AA;
cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_52AA_M;
cr->usr1_init_seed = USER1_INIT_SEED_52AA;
cr->usr1_init_seed_m = USER1_INIT_SEED_52AA_M;
cr->usr2_delmter = USER2_DELMTER_52AA;
cr->usr2_delmter_m = USER2_DELMTER_52AA_M;
cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_52AA;
cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_52AA_M;
cr->usr2_init_seed = USER2_INIT_SEED_52AA;
cr->usr2_init_seed_m = USER2_INIT_SEED_52AA_M;
cr->usr3_delmter = USER3_DELMTER_52AA;
cr->usr3_delmter_m = USER3_DELMTER_52AA_M;
cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_52AA;
cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_52AA_M;
cr->usr3_init_seed = USER3_INIT_SEED_52AA;
cr->usr3_init_seed_m = USER3_INIT_SEED_52AA_M;
cr->vht_sigb0 = TXD_VHT_SIGB0_52AA;
cr->vht_sigb0_m = TXD_VHT_SIGB0_52AA_M;
cr->vht_sigb1 = TXD_VHT_SIGB1_52AA;
cr->vht_sigb1_m = TXD_VHT_SIGB1_52AA_M;
cr->vht_sigb2 = TXD_VHT_SIGB2_52AA;
cr->vht_sigb2_m = TXD_VHT_SIGB2_52AA_M;
cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_52AA;
cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_52AA_M;
cr->vht_sigb3 = TXD_VHT_SIGB3_52AA;
cr->vht_sigb3_m = TXD_VHT_SIGB3_52AA_M;
cr->n_ltf = TXCOMCT_N_LTF_52AA;
cr->n_ltf_m = TXCOMCT_N_LTF_52AA_M;
cr->siga1 = TXD_SIGA1_52AA;
cr->siga1_m = TXD_SIGA1_52AA_M;
cr->siga2 = TXD_SIGA2_52AA;
cr->siga2_m = TXD_SIGA2_52AA_M;
cr->lsig = TXD_LSIG_52AA;
cr->lsig_m = TXD_LSIG_52AA_M;
cr->cca_pw_th = TXINFO_CCA_PW_TH_52AA;
cr->cca_pw_th_m = TXINFO_CCA_PW_TH_52AA_M;
cr->n_sym = TXTIMCT_N_SYM_52AA;
cr->n_sym_m = TXTIMCT_N_SYM_52AA_M;
cr->usr0_service = USER0_SERVICE_52AA;
cr->usr0_service_m = USER0_SERVICE_52AA_M;
cr->usr1_service = USER1_SERVICE_52AA;
cr->usr1_service_m = USER1_SERVICE_52AA_M;
cr->usr2_service = USER2_SERVICE_52AA;
cr->usr2_service_m = USER2_SERVICE_52AA_M;
cr->usr3_service = USER3_SERVICE_52AA;
cr->usr3_service_m = USER3_SERVICE_52AA_M;
cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_52AA;
cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_52AA_M;
cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_52AA;
cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_52AA_M;
cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_52AA;
cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_52AA_M;
cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_52AA;
cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_52AA_M;
cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_52AA;
cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_52AA_M;
cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_52AA;
cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_52AA_M;
cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_52AA;
cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_52AA_M;
cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_52AA;
cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_52AA_M;
cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_52AA;
cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_52AA_M;
cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_52AA;
cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_52AA_M;
cr->usr0_n_mpdu = USER0_N_MPDU_52AA;
cr->usr0_n_mpdu_m = USER0_N_MPDU_52AA_M;
cr->usr1_n_mpdu = USER1_N_MPDU_52AA;
cr->usr1_n_mpdu_m = USER1_N_MPDU_52AA_M;
cr->usr2_n_mpdu = USER2_N_MPDU_52AA;
cr->usr2_n_mpdu_m = USER2_N_MPDU_52AA_M;
cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_52AA;
cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_52AA_M;
cr->usr3_n_mpdu = USER3_N_MPDU_52AA;
cr->usr3_n_mpdu_m = USER3_N_MPDU_52AA_M;
cr->ch20_with_data = TXINFO_CH20_WITH_DATA_52AA;
cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_52AA_M;
cr->n_usr = TXINFO_N_USR_52AA;
cr->n_usr_m = TXINFO_N_USR_52AA_M;
cr->txcmd_txtp = TXINFO_TXCMD_TXTP_52AA;
cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_52AA_M;
cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_52AA;
cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_52AA_M;
cr->usr0_u_id = TXUSRCT0_U_ID_52AA;
cr->usr0_u_id_m = TXUSRCT0_U_ID_52AA_M;
cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_52AA;
cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_52AA_M;
cr->usr1_u_id = TXUSRCT1_U_ID_52AA;
cr->usr1_u_id_m = TXUSRCT1_U_ID_52AA_M;
cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_52AA;
cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_52AA_M;
cr->usr2_u_id = TXUSRCT2_U_ID_52AA;
cr->usr2_u_id_m = TXUSRCT2_U_ID_52AA_M;
cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_52AA;
cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_52AA_M;
cr->usr3_u_id = TXUSRCT3_U_ID_52AA;
cr->usr3_u_id_m = TXUSRCT3_U_ID_52AA_M;
cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_52AA;
cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_52AA_M;
cr->usr0_mcs = TXUSRCT0_MCS_52AA;
cr->usr0_mcs_m = TXUSRCT0_MCS_52AA_M;
cr->usr1_mcs = TXUSRCT1_MCS_52AA;
cr->usr1_mcs_m = TXUSRCT1_MCS_52AA_M;
cr->usr2_mcs = TXUSRCT2_MCS_52AA;
cr->usr2_mcs_m = TXUSRCT2_MCS_52AA_M;
cr->usr3_mcs = TXUSRCT3_MCS_52AA;
cr->usr3_mcs_m = TXUSRCT3_MCS_52AA_M;
cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_52AA;
cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_52AA_M;
cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_52AA;
cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_52AA_M;
cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_52AA;
cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_52AA_M;
cr->ppdu_type = TXINFO_PPDU_TYPE_52AA;
cr->ppdu_type_m = TXINFO_PPDU_TYPE_52AA_M;
cr->txsc = TXINFO_TXSC_52AA;
cr->txsc_m = TXINFO_TXSC_52AA_M;
cr->cfo_comp = TXINFO_CFO_COMP_52AA;
cr->cfo_comp_m = TXINFO_CFO_COMP_52AA_M;
cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_52AA;
cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_52AA_M;
cr->usr0_n_sts = TXUSRCT0_N_STS_52AA;
cr->usr0_n_sts_m = TXUSRCT0_N_STS_52AA_M;
cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_52AA;
cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_52AA_M;
cr->usr0_strt_sts = TXUSRCT0_STRT_STS_52AA;
cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_52AA_M;
cr->usr1_n_sts = TXUSRCT1_N_STS_52AA;
cr->usr1_n_sts_m = TXUSRCT1_N_STS_52AA_M;
cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_52AA;
cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_52AA_M;
cr->usr1_strt_sts = TXUSRCT1_STRT_STS_52AA;
cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_52AA_M;
cr->usr2_n_sts = TXUSRCT2_N_STS_52AA;
cr->usr2_n_sts_m = TXUSRCT2_N_STS_52AA_M;
cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_52AA;
cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_52AA_M;
cr->usr2_strt_sts = TXUSRCT2_STRT_STS_52AA;
cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_52AA_M;
cr->usr3_n_sts = TXUSRCT3_N_STS_52AA;
cr->usr3_n_sts_m = TXUSRCT3_N_STS_52AA_M;
cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_52AA;
cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_52AA_M;
cr->usr3_strt_sts = TXUSRCT3_STRT_STS_52AA;
cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_52AA_M;
cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_52AA;
cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_52AA_M;
cr->gi_type = TXCOMCT_GI_TYPE_52AA;
cr->gi_type_m = TXCOMCT_GI_TYPE_52AA_M;
cr->ltf_type = TXCOMCT_LTF_TYPE_52AA;
cr->ltf_type_m = TXCOMCT_LTF_TYPE_52AA_M;
cr->dbw_idx = TXINFO_DBW_IDX_52AA;
cr->dbw_idx_m = TXINFO_DBW_IDX_52AA_M;
cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_52AA;
cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_52AA_M;
cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_52AA;
cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_52AA_M;
cr->doppler_en = TXCOMCT_DOPPLER_EN_52AA;
cr->doppler_en_m = TXCOMCT_DOPPLER_EN_52AA_M;
cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_52AA;
cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_52AA_M;
cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_52AA;
cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_52AA_M;
cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_52AA;
cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_52AA_M;
cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_52AA;
cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_52AA_M;
cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_52AA;
cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_52AA_M;
cr->ndp = TXCOMCT_NDP_52AA;
cr->ndp_m = TXCOMCT_NDP_52AA_M;
cr->stbc_en = TXCOMCT_STBC_EN_52AA;
cr->stbc_en_m = TXCOMCT_STBC_EN_52AA_M;
cr->ant_sel_a = TXINFO_ANT_SEL_A_52AA;
cr->ant_sel_a_m = TXINFO_ANT_SEL_A_52AA_M;
cr->ant_sel_b = TXINFO_ANT_SEL_B_52AA;
cr->ant_sel_b_m = TXINFO_ANT_SEL_B_52AA_M;
cr->ant_sel_c = TXINFO_ANT_SEL_C_52AA;
cr->ant_sel_c_m = TXINFO_ANT_SEL_C_52AA_M;
cr->ant_sel_d = TXINFO_ANT_SEL_D_52AA;
cr->ant_sel_d_m = TXINFO_ANT_SEL_D_52AA_M;
cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_52AA;
cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_52AA_M;
cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_52AA;
cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_52AA_M;
cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_52AA;
cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_52AA_M;
cr->ldpc_extr = TXTIMCT_LDPC_EXTR_52AA;
cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_52AA_M;
cr->usr0_dcm_en = TXUSRCT0_DCM_EN_52AA;
cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_52AA_M;
cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_52AA;
cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_52AA_M;
cr->usr0_txbf_en = TXUSRCT0_TXBF_EN_52AA;
cr->usr0_txbf_en_m = TXUSRCT0_TXBF_EN_52AA_M;
cr->usr1_dcm_en = TXUSRCT1_DCM_EN_52AA;
cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_52AA_M;
cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_52AA;
cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_52AA_M;
cr->usr1_txbf_en = TXUSRCT1_TXBF_EN_52AA;
cr->usr1_txbf_en_m = TXUSRCT1_TXBF_EN_52AA_M;
cr->usr2_dcm_en = TXUSRCT2_DCM_EN_52AA;
cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_52AA_M;
cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_52AA;
cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_52AA_M;
cr->usr2_txbf_en = TXUSRCT2_TXBF_EN_52AA;
cr->usr2_txbf_en_m = TXUSRCT2_TXBF_EN_52AA_M;
cr->usr3_dcm_en = TXUSRCT3_DCM_EN_52AA;
cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_52AA_M;
cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_52AA;
cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_52AA_M;
cr->usr3_txbf_en = TXUSRCT3_TXBF_EN_52AA;
cr->usr3_txbf_en_m = TXUSRCT3_TXBF_EN_52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->b_header_0 = R1B_TX_PMAC_HEADER_0_A;
cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_A_M;
cr->b_header_1 = R1B_TX_PMAC_HEADER_1_A;
cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_A_M;
cr->b_header_2 = R1B_TX_PMAC_HEADER_2_A;
cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_A_M;
cr->b_header_3 = R1B_TX_PMAC_HEADER_3_A;
cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_A_M;
cr->b_header_4 = R1B_TX_PMAC_HEADER_4_A;
cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_A_M;
cr->b_header_5 = R1B_TX_PMAC_HEADER_5_A;
cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_A_M;
cr->b_psdu_byte = R1B_TX_PMAC_PSDU_BYTE_A;
cr->b_psdu_byte_m = R1B_TX_PMAC_PSDU_BYTE_A_M;
cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A;
cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A_M;
cr->b_ppdu_type = R1B_TX_PMAC_PPDU_TYPE_A;
cr->b_ppdu_type_m = R1B_TX_PMAC_PPDU_TYPE_A_M;
cr->b_psdu_rate = R1B_TX_PMAC_PSDU_RATE_A;
cr->b_psdu_rate_m = R1B_TX_PMAC_PSDU_RATE_A_M;
cr->b_service_bit2 = R1B_TX_PMAC_SERVICE_BIT2_A;
cr->b_service_bit2_m = R1B_TX_PMAC_SERVICE_BIT2_A_M;
cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_A;
cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_A_M;
cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_A;
cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_A_M;
cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_A;
cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_A_M;
cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_A;
cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_A_M;
cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_A;
cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_A_M;
cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_A;
cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_A_M;
cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_A;
cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_A_M;
cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_A;
cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_A_M;
cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_A;
cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_A_M;
cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_A;
cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_A_M;
cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_A;
cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_A_M;
cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_A;
cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_A_M;
cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_A;
cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_A_M;
cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_A;
cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_A_M;
cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_A;
cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_A_M;
cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_A;
cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_A_M;
cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_A;
cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_A_M;
cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_A;
cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_A_M;
cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_A;
cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_A_M;
cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_A;
cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_A_M;
cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_A;
cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_A_M;
cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_A;
cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_A_M;
cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_A;
cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_A_M;
cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_A;
cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_A_M;
cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_A;
cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_A_M;
cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_A;
cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_A_M;
cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_A;
cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_A_M;
cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_A;
cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_A_M;
cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_A;
cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_A_M;
cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_A;
cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_A_M;
cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_A;
cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_A_M;
cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_A;
cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_A_M;
cr->usr0_delmter = USER0_DELMTER_A;
cr->usr0_delmter_m = USER0_DELMTER_A_M;
cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_A;
cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_A_M;
cr->usr0_init_seed = USER0_INIT_SEED_A;
cr->usr0_init_seed_m = USER0_INIT_SEED_A_M;
cr->usr1_delmter = USER1_DELMTER_A;
cr->usr1_delmter_m = USER1_DELMTER_A_M;
cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_A;
cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_A_M;
cr->usr1_init_seed = USER1_INIT_SEED_A;
cr->usr1_init_seed_m = USER1_INIT_SEED_A_M;
cr->usr2_delmter = USER2_DELMTER_A;
cr->usr2_delmter_m = USER2_DELMTER_A_M;
cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_A;
cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_A_M;
cr->usr2_init_seed = USER2_INIT_SEED_A;
cr->usr2_init_seed_m = USER2_INIT_SEED_A_M;
cr->usr3_delmter = USER3_DELMTER_A;
cr->usr3_delmter_m = USER3_DELMTER_A_M;
cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_A;
cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_A_M;
cr->usr3_init_seed = USER3_INIT_SEED_A;
cr->usr3_init_seed_m = USER3_INIT_SEED_A_M;
cr->vht_sigb0 = TXD_VHT_SIGB0_A;
cr->vht_sigb0_m = TXD_VHT_SIGB0_A_M;
cr->vht_sigb1 = TXD_VHT_SIGB1_A;
cr->vht_sigb1_m = TXD_VHT_SIGB1_A_M;
cr->vht_sigb2 = TXD_VHT_SIGB2_A;
cr->vht_sigb2_m = TXD_VHT_SIGB2_A_M;
cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_A;
cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_A_M;
cr->vht_sigb3 = TXD_VHT_SIGB3_A;
cr->vht_sigb3_m = TXD_VHT_SIGB3_A_M;
cr->n_ltf = TXCOMCT_N_LTF_A;
cr->n_ltf_m = TXCOMCT_N_LTF_A_M;
cr->siga1 = TXD_SIGA1_A;
cr->siga1_m = TXD_SIGA1_A_M;
cr->siga2 = TXD_SIGA2_A;
cr->siga2_m = TXD_SIGA2_A_M;
cr->lsig = TXD_LSIG_A;
cr->lsig_m = TXD_LSIG_A_M;
cr->cca_pw_th = TXINFO_CCA_PW_TH_A;
cr->cca_pw_th_m = TXINFO_CCA_PW_TH_A_M;
cr->n_sym = TXTIMCT_N_SYM_A;
cr->n_sym_m = TXTIMCT_N_SYM_A_M;
cr->usr0_service = USER0_SERVICE_A;
cr->usr0_service_m = USER0_SERVICE_A_M;
cr->usr1_service = USER1_SERVICE_A;
cr->usr1_service_m = USER1_SERVICE_A_M;
cr->usr2_service = USER2_SERVICE_A;
cr->usr2_service_m = USER2_SERVICE_A_M;
cr->usr3_service = USER3_SERVICE_A;
cr->usr3_service_m = USER3_SERVICE_A_M;
cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_A;
cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_A_M;
cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_A;
cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_A_M;
cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_A;
cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_A_M;
cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_A;
cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_A_M;
cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_A;
cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_A_M;
cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_A;
cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_A_M;
cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_A;
cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_A_M;
cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_A;
cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_A_M;
cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_A;
cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_A_M;
cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_A;
cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_A_M;
cr->usr0_n_mpdu = USER0_N_MPDU_A;
cr->usr0_n_mpdu_m = USER0_N_MPDU_A_M;
cr->usr1_n_mpdu = USER1_N_MPDU_A;
cr->usr1_n_mpdu_m = USER1_N_MPDU_A_M;
cr->usr2_n_mpdu = USER2_N_MPDU_A;
cr->usr2_n_mpdu_m = USER2_N_MPDU_A_M;
cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_A;
cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_A_M;
cr->usr3_n_mpdu = USER3_N_MPDU_A;
cr->usr3_n_mpdu_m = USER3_N_MPDU_A_M;
cr->ch20_with_data = TXINFO_CH20_WITH_DATA_A;
cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_A_M;
cr->n_usr = TXINFO_N_USR_A;
cr->n_usr_m = TXINFO_N_USR_A_M;
cr->txcmd_txtp = TXINFO_TXCMD_TXTP_A;
cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_A_M;
cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_A;
cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_A_M;
cr->usr0_u_id = TXUSRCT0_U_ID_A;
cr->usr0_u_id_m = TXUSRCT0_U_ID_A_M;
cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_A;
cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_A_M;
cr->usr1_u_id = TXUSRCT1_U_ID_A;
cr->usr1_u_id_m = TXUSRCT1_U_ID_A_M;
cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_A;
cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_A_M;
cr->usr2_u_id = TXUSRCT2_U_ID_A;
cr->usr2_u_id_m = TXUSRCT2_U_ID_A_M;
cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_A;
cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_A_M;
cr->usr3_u_id = TXUSRCT3_U_ID_A;
cr->usr3_u_id_m = TXUSRCT3_U_ID_A_M;
cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_A;
cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_A_M;
cr->usr0_mcs = TXUSRCT0_MCS_A;
cr->usr0_mcs_m = TXUSRCT0_MCS_A_M;
cr->usr1_mcs = TXUSRCT1_MCS_A;
cr->usr1_mcs_m = TXUSRCT1_MCS_A_M;
cr->usr2_mcs = TXUSRCT2_MCS_A;
cr->usr2_mcs_m = TXUSRCT2_MCS_A_M;
cr->usr3_mcs = TXUSRCT3_MCS_A;
cr->usr3_mcs_m = TXUSRCT3_MCS_A_M;
cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_A;
cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_A_M;
cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_A;
cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_A_M;
cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_A;
cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_A_M;
cr->ppdu_type = TXINFO_PPDU_TYPE_A;
cr->ppdu_type_m = TXINFO_PPDU_TYPE_A_M;
cr->txsc = TXINFO_TXSC_A;
cr->txsc_m = TXINFO_TXSC_A_M;
cr->cfo_comp = TXINFO_CFO_COMP_A;
cr->cfo_comp_m = TXINFO_CFO_COMP_A_M;
cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_A;
cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_A_M;
cr->usr0_n_sts = TXUSRCT0_N_STS_A;
cr->usr0_n_sts_m = TXUSRCT0_N_STS_A_M;
cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_A;
cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_A_M;
cr->usr0_strt_sts = TXUSRCT0_STRT_STS_A;
cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_A_M;
cr->usr1_n_sts = TXUSRCT1_N_STS_A;
cr->usr1_n_sts_m = TXUSRCT1_N_STS_A_M;
cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_A;
cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_A_M;
cr->usr1_strt_sts = TXUSRCT1_STRT_STS_A;
cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_A_M;
cr->usr2_n_sts = TXUSRCT2_N_STS_A;
cr->usr2_n_sts_m = TXUSRCT2_N_STS_A_M;
cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_A;
cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_A_M;
cr->usr2_strt_sts = TXUSRCT2_STRT_STS_A;
cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_A_M;
cr->usr3_n_sts = TXUSRCT3_N_STS_A;
cr->usr3_n_sts_m = TXUSRCT3_N_STS_A_M;
cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_A;
cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_A_M;
cr->usr3_strt_sts = TXUSRCT3_STRT_STS_A;
cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_A_M;
cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_A;
cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_A_M;
cr->gi_type = TXCOMCT_GI_TYPE_A;
cr->gi_type_m = TXCOMCT_GI_TYPE_A_M;
cr->ltf_type = TXCOMCT_LTF_TYPE_A;
cr->ltf_type_m = TXCOMCT_LTF_TYPE_A_M;
cr->dbw_idx = TXINFO_DBW_IDX_A;
cr->dbw_idx_m = TXINFO_DBW_IDX_A_M;
cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_A;
cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_A_M;
cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_A;
cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_A_M;
cr->doppler_en = TXCOMCT_DOPPLER_EN_A;
cr->doppler_en_m = TXCOMCT_DOPPLER_EN_A_M;
cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_A;
cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_A_M;
cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_A;
cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_A_M;
cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_A;
cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_A_M;
cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_A;
cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_A_M;
cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_A;
cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_A_M;
cr->ndp = TXCOMCT_NDP_A;
cr->ndp_m = TXCOMCT_NDP_A_M;
cr->stbc_en = TXCOMCT_STBC_EN_A;
cr->stbc_en_m = TXCOMCT_STBC_EN_A_M;
cr->ant_sel_a = TXINFO_ANT_SEL_A_A;
cr->ant_sel_a_m = TXINFO_ANT_SEL_A_A_M;
cr->ant_sel_b = TXINFO_ANT_SEL_B_A;
cr->ant_sel_b_m = TXINFO_ANT_SEL_B_A_M;
cr->ant_sel_c = TXINFO_ANT_SEL_C_A;
cr->ant_sel_c_m = TXINFO_ANT_SEL_C_A_M;
cr->ant_sel_d = TXINFO_ANT_SEL_D_A;
cr->ant_sel_d_m = TXINFO_ANT_SEL_D_A_M;
cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_A;
cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_A_M;
cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_A;
cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_A_M;
cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_A;
cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_A_M;
cr->ldpc_extr = TXTIMCT_LDPC_EXTR_A;
cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_A_M;
cr->usr0_dcm_en = TXUSRCT0_DCM_EN_A;
cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_A_M;
cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_A;
cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_A_M;
cr->usr0_txbf_en = TXUSRCT0_TXBF_EN_A;
cr->usr0_txbf_en_m = TXUSRCT0_TXBF_EN_A_M;
cr->usr1_dcm_en = TXUSRCT1_DCM_EN_A;
cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_A_M;
cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_A;
cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_A_M;
cr->usr1_txbf_en = TXUSRCT1_TXBF_EN_A;
cr->usr1_txbf_en_m = TXUSRCT1_TXBF_EN_A_M;
cr->usr2_dcm_en = TXUSRCT2_DCM_EN_A;
cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_A_M;
cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_A;
cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_A_M;
cr->usr2_txbf_en = TXUSRCT2_TXBF_EN_A;
cr->usr2_txbf_en_m = TXUSRCT2_TXBF_EN_A_M;
cr->usr3_dcm_en = TXUSRCT3_DCM_EN_A;
cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_A_M;
cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_A;
cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_A_M;
cr->usr3_txbf_en = TXUSRCT3_TXBF_EN_A;
cr->usr3_txbf_en_m = TXUSRCT3_TXBF_EN_A_M;
break;
#endif
#ifdef HALBB_COMPILE_AP2_SERIES
case BB_AP2:
cr->b_header_0 = R1B_TX_PMAC_HEADER_0_A2;
cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_A2_M;
cr->b_header_1 = R1B_TX_PMAC_HEADER_1_A2;
cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_A2_M;
cr->b_header_2 = R1B_TX_PMAC_HEADER_2_A2;
cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_A2_M;
cr->b_header_3 = R1B_TX_PMAC_HEADER_3_A2;
cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_A2_M;
cr->b_header_4 = R1B_TX_PMAC_HEADER_4_A2;
cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_A2_M;
cr->b_header_5 = R1B_TX_PMAC_HEADER_5_A2;
cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_A2_M;
cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A2;
cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_A2_M;
cr->b_rate_idx = BMODE_RATE_IDX_A2;
cr->b_rate_idx_m = BMODE_RATE_IDX_A2_M;
cr->b_locked_clk_en = BMODE_LOCKED_CLK_EN_A2;
cr->b_locked_clk_en_m = BMODE_LOCKED_CLK_EN_A2_M;
cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_A2;
cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_A2_M;
cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_A2;
cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_A2_M;
cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_A2;
cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_A2_M;
cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_A2;
cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_A2_M;
cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_A2;
cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_A2_M;
cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_A2;
cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_A2_M;
cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_A2;
cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_A2_M;
cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_A2;
cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_A2_M;
cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_A2;
cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_A2_M;
cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_A2;
cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_A2_M;
cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_A2;
cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_A2_M;
cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_A2;
cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_A2_M;
cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_A2;
cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_A2_M;
cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_A2;
cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_A2_M;
cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_A2;
cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_A2_M;
cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_A2;
cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_A2_M;
cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_A2;
cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_A2_M;
cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_A2;
cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_A2_M;
cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_A2;
cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_A2_M;
cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_A2;
cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_A2_M;
cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_A2;
cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_A2_M;
cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_A2;
cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_A2_M;
cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_A2;
cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_A2_M;
cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_A2;
cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_A2_M;
cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_A2;
cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_A2_M;
cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_A2;
cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_A2_M;
cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_A2;
cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_A2_M;
cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_A2;
cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_A2_M;
cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_A2;
cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_A2_M;
cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_A2;
cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_A2_M;
cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_A2;
cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_A2_M;
cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_A2;
cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_A2_M;
cr->usr0_delmter = USER0_DELMTER_A2;
cr->usr0_delmter_m = USER0_DELMTER_A2_M;
cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_A2;
cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_A2_M;
cr->usr0_init_seed = USER0_INIT_SEED_A2;
cr->usr0_init_seed_m = USER0_INIT_SEED_A2_M;
cr->usr1_delmter = USER1_DELMTER_A2;
cr->usr1_delmter_m = USER1_DELMTER_A2_M;
cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_A2;
cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_A2_M;
cr->usr1_init_seed = USER1_INIT_SEED_A2;
cr->usr1_init_seed_m = USER1_INIT_SEED_A2_M;
cr->usr2_delmter = USER2_DELMTER_A2;
cr->usr2_delmter_m = USER2_DELMTER_A2_M;
cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_A2;
cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_A2_M;
cr->usr2_init_seed = USER2_INIT_SEED_A2;
cr->usr2_init_seed_m = USER2_INIT_SEED_A2_M;
cr->usr3_delmter = USER3_DELMTER_A2;
cr->usr3_delmter_m = USER3_DELMTER_A2_M;
cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_A2;
cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_A2_M;
cr->usr3_init_seed = USER3_INIT_SEED_A2;
cr->usr3_init_seed_m = USER3_INIT_SEED_A2_M;
cr->vht_sigb0 = TXD_VHT_SIGB0_A2;
cr->vht_sigb0_m = TXD_VHT_SIGB0_A2_M;
cr->vht_sigb1 = TXD_VHT_SIGB1_A2;
cr->vht_sigb1_m = TXD_VHT_SIGB1_A2_M;
cr->vht_sigb2 = TXD_VHT_SIGB2_A2;
cr->vht_sigb2_m = TXD_VHT_SIGB2_A2_M;
cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_A2;
cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_A2_M;
cr->vht_sigb3 = TXD_VHT_SIGB3_A2;
cr->vht_sigb3_m = TXD_VHT_SIGB3_A2_M;
cr->n_ltf = TXCOMCT_N_LTF_A2;
cr->n_ltf_m = TXCOMCT_N_LTF_A2_M;
cr->siga1 = TXD_SIGA1_A2;
cr->siga1_m = TXD_SIGA1_A2_M;
cr->siga2 = TXD_SIGA2_A2;
cr->siga2_m = TXD_SIGA2_A2_M;
cr->lsig = TXD_LSIG_A2;
cr->lsig_m = TXD_LSIG_A2_M;
cr->cca_pw_th = TXINFO_CCA_PW_TH_A2;
cr->cca_pw_th_m = TXINFO_CCA_PW_TH_A2_M;
cr->n_sym = TXTIMCT_N_SYM_A2;
cr->n_sym_m = TXTIMCT_N_SYM_A2_M;
cr->usr0_service = USER0_SERVICE_A2;
cr->usr0_service_m = USER0_SERVICE_A2_M;
cr->usr1_service = USER1_SERVICE_A2;
cr->usr1_service_m = USER1_SERVICE_A2_M;
cr->usr2_service = USER2_SERVICE_A2;
cr->usr2_service_m = USER2_SERVICE_A2_M;
cr->usr3_service = USER3_SERVICE_A2;
cr->usr3_service_m = USER3_SERVICE_A2_M;
cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_A2;
cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_A2_M;
cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_A2;
cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_A2_M;
cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_A2;
cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_A2_M;
cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_A2;
cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_A2_M;
cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_A2;
cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_A2_M;
cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_A2;
cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_A2_M;
cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_A2;
cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_A2_M;
cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_A2;
cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_A2_M;
cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_A2;
cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_A2_M;
cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_A2;
cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_A2_M;
cr->usr0_n_mpdu = USER0_N_MPDU_A2;
cr->usr0_n_mpdu_m = USER0_N_MPDU_A2_M;
cr->usr1_n_mpdu = USER1_N_MPDU_A2;
cr->usr1_n_mpdu_m = USER1_N_MPDU_A2_M;
cr->usr2_n_mpdu = USER2_N_MPDU_A2;
cr->usr2_n_mpdu_m = USER2_N_MPDU_A2_M;
cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_A2;
cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_A2_M;
cr->usr3_n_mpdu = USER3_N_MPDU_A2;
cr->usr3_n_mpdu_m = USER3_N_MPDU_A2_M;
cr->ch20_with_data = TXINFO_CH20_WITH_DATA_A2;
cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_A2_M;
cr->n_usr = TXINFO_N_USR_A2;
cr->n_usr_m = TXINFO_N_USR_A2_M;
cr->txcmd_txtp = TXINFO_TXCMD_TXTP_A2;
cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_A2_M;
cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_A2;
cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_A2_M;
cr->usr0_u_id = TXUSRCT0_U_ID_A2;
cr->usr0_u_id_m = TXUSRCT0_U_ID_A2_M;
cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_A2;
cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_A2_M;
cr->usr1_u_id = TXUSRCT1_U_ID_A2;
cr->usr1_u_id_m = TXUSRCT1_U_ID_A2_M;
cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_A2;
cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_A2_M;
cr->usr2_u_id = TXUSRCT2_U_ID_A2;
cr->usr2_u_id_m = TXUSRCT2_U_ID_A2_M;
cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_A2;
cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_A2_M;
cr->usr3_u_id = TXUSRCT3_U_ID_A2;
cr->usr3_u_id_m = TXUSRCT3_U_ID_A2_M;
cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_A2;
cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_A2_M;
cr->usr0_mcs = TXUSRCT0_MCS_A2;
cr->usr0_mcs_m = TXUSRCT0_MCS_A2_M;
cr->usr1_mcs = TXUSRCT1_MCS_A2;
cr->usr1_mcs_m = TXUSRCT1_MCS_A2_M;
cr->usr2_mcs = TXUSRCT2_MCS_A2;
cr->usr2_mcs_m = TXUSRCT2_MCS_A2_M;
cr->usr3_mcs = TXUSRCT3_MCS_A2;
cr->usr3_mcs_m = TXUSRCT3_MCS_A2_M;
cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_A2;
cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_A2_M;
cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_A2;
cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_A2_M;
cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_A2;
cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_A2_M;
cr->ppdu_type = TXINFO_PPDU_TYPE_A2;
cr->ppdu_type_m = TXINFO_PPDU_TYPE_A2_M;
cr->txsc = TXINFO_TXSC_A2;
cr->txsc_m = TXINFO_TXSC_A2_M;
cr->cfo_comp = TXINFO_CFO_COMP_A2;
cr->cfo_comp_m = TXINFO_CFO_COMP_A2_M;
cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_A2;
cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_A2_M;
cr->usr0_n_sts = TXUSRCT0_N_STS_A2;
cr->usr0_n_sts_m = TXUSRCT0_N_STS_A2_M;
cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_A2;
cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_A2_M;
cr->usr0_strt_sts = TXUSRCT0_STRT_STS_A2;
cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_A2_M;
cr->usr1_n_sts = TXUSRCT1_N_STS_A2;
cr->usr1_n_sts_m = TXUSRCT1_N_STS_A2_M;
cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_A2;
cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_A2_M;
cr->usr1_strt_sts = TXUSRCT1_STRT_STS_A2;
cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_A2_M;
cr->usr2_n_sts = TXUSRCT2_N_STS_A2;
cr->usr2_n_sts_m = TXUSRCT2_N_STS_A2_M;
cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_A2;
cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_A2_M;
cr->usr2_strt_sts = TXUSRCT2_STRT_STS_A2;
cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_A2_M;
cr->usr3_n_sts = TXUSRCT3_N_STS_A2;
cr->usr3_n_sts_m = TXUSRCT3_N_STS_A2_M;
cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_A2;
cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_A2_M;
cr->usr3_strt_sts = TXUSRCT3_STRT_STS_A2;
cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_A2_M;
cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_A2;
cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_A2_M;
cr->gi_type = TXCOMCT_GI_TYPE_A2;
cr->gi_type_m = TXCOMCT_GI_TYPE_A2_M;
cr->ltf_type = TXCOMCT_LTF_TYPE_A2;
cr->ltf_type_m = TXCOMCT_LTF_TYPE_A2_M;
cr->dbw_idx = TXINFO_DBW_IDX_A2;
cr->dbw_idx_m = TXINFO_DBW_IDX_A2_M;
cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_A2;
cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_A2_M;
cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_A2;
cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_A2_M;
cr->doppler_en = TXCOMCT_DOPPLER_EN_A2;
cr->doppler_en_m = TXCOMCT_DOPPLER_EN_A2_M;
cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_A2;
cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_A2_M;
cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_A2;
cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_A2_M;
cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_A2;
cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_A2_M;
cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_A2;
cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_A2_M;
cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_A2;
cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_A2_M;
cr->ndp = TXCOMCT_NDP_A2;
cr->ndp_m = TXCOMCT_NDP_A2_M;
cr->stbc_en = TXCOMCT_STBC_EN_A2;
cr->stbc_en_m = TXCOMCT_STBC_EN_A2_M;
cr->ant_sel_a = TXINFO_ANT_SEL_A_A2;
cr->ant_sel_a_m = TXINFO_ANT_SEL_A_A2_M;
cr->ant_sel_b = TXINFO_ANT_SEL_B_A2;
cr->ant_sel_b_m = TXINFO_ANT_SEL_B_A2_M;
cr->ant_sel_c = TXINFO_ANT_SEL_C_A2;
cr->ant_sel_c_m = TXINFO_ANT_SEL_C_A2_M;
cr->ant_sel_d = TXINFO_ANT_SEL_D_A2;
cr->ant_sel_d_m = TXINFO_ANT_SEL_D_A2_M;
cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_A2;
cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_A2_M;
cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_A2;
cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_A2_M;
cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_A2;
cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_A2_M;
cr->ldpc_extr = TXTIMCT_LDPC_EXTR_A2;
cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_A2_M;
cr->usr0_dcm_en = TXUSRCT0_DCM_EN_A2;
cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_A2_M;
cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_A2;
cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_A2_M;
cr->usr0_precoding_mode_idx = TXUSRCT0_PRECODING_MODE_IDX_A2;
cr->usr0_precoding_mode_idx_m = TXUSRCT0_PRECODING_MODE_IDX_A2;
cr->usr1_dcm_en = TXUSRCT1_DCM_EN_A2;
cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_A2_M;
cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_A2;
cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_A2_M;
cr->usr1_precoding_mode_idx = TXUSRCT1_PRECODING_MODE_IDX_A2;
cr->usr1_precoding_mode_idx_m = TXUSRCT1_PRECODING_MODE_IDX_A2;
cr->usr2_dcm_en = TXUSRCT2_DCM_EN_A2;
cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_A2_M;
cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_A2;
cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_A2_M;
cr->usr2_precoding_mode_idx = TXUSRCT2_PRECODING_MODE_IDX_A2;
cr->usr2_precoding_mode_idx_m = TXUSRCT2_PRECODING_MODE_IDX_A2;
cr->usr3_dcm_en = TXUSRCT3_DCM_EN_A2;
cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_A2_M;
cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_A2;
cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_A2_M;
cr->usr3_precoding_mode_idx = TXUSRCT3_PRECODING_MODE_IDX_A2;
cr->usr3_precoding_mode_idx_m = TXUSRCT3_PRECODING_MODE_IDX_A2;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->b_header_0 = R1B_TX_PMAC_HEADER_0_C;
cr->b_header_0_m = R1B_TX_PMAC_HEADER_0_C_M;
cr->b_header_1 = R1B_TX_PMAC_HEADER_1_C;
cr->b_header_1_m = R1B_TX_PMAC_HEADER_1_C_M;
cr->b_header_2 = R1B_TX_PMAC_HEADER_2_C;
cr->b_header_2_m = R1B_TX_PMAC_HEADER_2_C_M;
cr->b_header_3 = R1B_TX_PMAC_HEADER_3_C;
cr->b_header_3_m = R1B_TX_PMAC_HEADER_3_C_M;
cr->b_header_4 = R1B_TX_PMAC_HEADER_4_C;
cr->b_header_4_m = R1B_TX_PMAC_HEADER_4_C_M;
cr->b_header_5 = R1B_TX_PMAC_HEADER_5_C;
cr->b_header_5_m = R1B_TX_PMAC_HEADER_5_C_M;
cr->b_psdu_byte = R1B_TX_PMAC_PSDU_BYTE_C;
cr->b_psdu_byte_m = R1B_TX_PMAC_PSDU_BYTE_C_M;
cr->b_carrier_suppress_tx = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C;
cr->b_carrier_suppress_tx_m = R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C_M;
cr->b_ppdu_type = R1B_TX_PMAC_PPDU_TYPE_C;
cr->b_ppdu_type_m = R1B_TX_PMAC_PPDU_TYPE_C_M;
cr->b_psdu_rate = R1B_TX_PMAC_PSDU_RATE_C;
cr->b_psdu_rate_m = R1B_TX_PMAC_PSDU_RATE_C_M;
cr->b_service_bit2 = R1B_TX_PMAC_SERVICE_BIT2_C;
cr->b_service_bit2_m = R1B_TX_PMAC_SERVICE_BIT2_C_M;
cr->he_sigb_ch1_0 = TXD_HE_SIGB_CH1_0_C;
cr->he_sigb_ch1_0_m = TXD_HE_SIGB_CH1_0_C_M;
cr->he_sigb_ch1_1 = TXD_HE_SIGB_CH1_1_C;
cr->he_sigb_ch1_1_m = TXD_HE_SIGB_CH1_1_C_M;
cr->he_sigb_ch1_10 = TXD_HE_SIGB_CH1_10_C;
cr->he_sigb_ch1_10_m = TXD_HE_SIGB_CH1_10_C_M;
cr->he_sigb_ch1_11 = TXD_HE_SIGB_CH1_11_C;
cr->he_sigb_ch1_11_m = TXD_HE_SIGB_CH1_11_C_M;
cr->he_sigb_ch1_12 = TXD_HE_SIGB_CH1_12_C;
cr->he_sigb_ch1_12_m = TXD_HE_SIGB_CH1_12_C_M;
cr->he_sigb_ch1_13 = TXD_HE_SIGB_CH1_13_C;
cr->he_sigb_ch1_13_m = TXD_HE_SIGB_CH1_13_C_M;
cr->he_sigb_ch1_14 = TXD_HE_SIGB_CH1_14_C;
cr->he_sigb_ch1_14_m = TXD_HE_SIGB_CH1_14_C_M;
cr->he_sigb_ch1_15 = TXD_HE_SIGB_CH1_15_C;
cr->he_sigb_ch1_15_m = TXD_HE_SIGB_CH1_15_C_M;
cr->he_sigb_ch1_2 = TXD_HE_SIGB_CH1_2_C;
cr->he_sigb_ch1_2_m = TXD_HE_SIGB_CH1_2_C_M;
cr->he_sigb_ch1_3 = TXD_HE_SIGB_CH1_3_C;
cr->he_sigb_ch1_3_m = TXD_HE_SIGB_CH1_3_C_M;
cr->he_sigb_ch1_4 = TXD_HE_SIGB_CH1_4_C;
cr->he_sigb_ch1_4_m = TXD_HE_SIGB_CH1_4_C_M;
cr->he_sigb_ch1_5 = TXD_HE_SIGB_CH1_5_C;
cr->he_sigb_ch1_5_m = TXD_HE_SIGB_CH1_5_C_M;
cr->he_sigb_ch1_6 = TXD_HE_SIGB_CH1_6_C;
cr->he_sigb_ch1_6_m = TXD_HE_SIGB_CH1_6_C_M;
cr->he_sigb_ch1_7 = TXD_HE_SIGB_CH1_7_C;
cr->he_sigb_ch1_7_m = TXD_HE_SIGB_CH1_7_C_M;
cr->he_sigb_ch1_8 = TXD_HE_SIGB_CH1_8_C;
cr->he_sigb_ch1_8_m = TXD_HE_SIGB_CH1_8_C_M;
cr->he_sigb_ch1_9 = TXD_HE_SIGB_CH1_9_C;
cr->he_sigb_ch1_9_m = TXD_HE_SIGB_CH1_9_C_M;
cr->he_sigb_ch2_0 = TXD_HE_SIGB_CH2_0_C;
cr->he_sigb_ch2_0_m = TXD_HE_SIGB_CH2_0_C_M;
cr->he_sigb_ch2_1 = TXD_HE_SIGB_CH2_1_C;
cr->he_sigb_ch2_1_m = TXD_HE_SIGB_CH2_1_C_M;
cr->he_sigb_ch2_10 = TXD_HE_SIGB_CH2_10_C;
cr->he_sigb_ch2_10_m = TXD_HE_SIGB_CH2_10_C_M;
cr->he_sigb_ch2_11 = TXD_HE_SIGB_CH2_11_C;
cr->he_sigb_ch2_11_m = TXD_HE_SIGB_CH2_11_C_M;
cr->he_sigb_ch2_12 = TXD_HE_SIGB_CH2_12_C;
cr->he_sigb_ch2_12_m = TXD_HE_SIGB_CH2_12_C_M;
cr->he_sigb_ch2_13 = TXD_HE_SIGB_CH2_13_C;
cr->he_sigb_ch2_13_m = TXD_HE_SIGB_CH2_13_C_M;
cr->he_sigb_ch2_14 = TXD_HE_SIGB_CH2_14_C;
cr->he_sigb_ch2_14_m = TXD_HE_SIGB_CH2_14_C_M;
cr->he_sigb_ch2_15 = TXD_HE_SIGB_CH2_15_C;
cr->he_sigb_ch2_15_m = TXD_HE_SIGB_CH2_15_C_M;
cr->he_sigb_ch2_2 = TXD_HE_SIGB_CH2_2_C;
cr->he_sigb_ch2_2_m = TXD_HE_SIGB_CH2_2_C_M;
cr->he_sigb_ch2_3 = TXD_HE_SIGB_CH2_3_C;
cr->he_sigb_ch2_3_m = TXD_HE_SIGB_CH2_3_C_M;
cr->he_sigb_ch2_4 = TXD_HE_SIGB_CH2_4_C;
cr->he_sigb_ch2_4_m = TXD_HE_SIGB_CH2_4_C_M;
cr->he_sigb_ch2_5 = TXD_HE_SIGB_CH2_5_C;
cr->he_sigb_ch2_5_m = TXD_HE_SIGB_CH2_5_C_M;
cr->he_sigb_ch2_6 = TXD_HE_SIGB_CH2_6_C;
cr->he_sigb_ch2_6_m = TXD_HE_SIGB_CH2_6_C_M;
cr->he_sigb_ch2_7 = TXD_HE_SIGB_CH2_7_C;
cr->he_sigb_ch2_7_m = TXD_HE_SIGB_CH2_7_C_M;
cr->he_sigb_ch2_8 = TXD_HE_SIGB_CH2_8_C;
cr->he_sigb_ch2_8_m = TXD_HE_SIGB_CH2_8_C_M;
cr->he_sigb_ch2_9 = TXD_HE_SIGB_CH2_9_C;
cr->he_sigb_ch2_9_m = TXD_HE_SIGB_CH2_9_C_M;
cr->usr0_delmter = USER0_DELMTER_C;
cr->usr0_delmter_m = USER0_DELMTER_C_M;
cr->usr0_eof_padding_len = USER0_EOF_PADDING_LEN_C;
cr->usr0_eof_padding_len_m = USER0_EOF_PADDING_LEN_C_M;
cr->usr0_init_seed = USER0_INIT_SEED_C;
cr->usr0_init_seed_m = USER0_INIT_SEED_C_M;
cr->usr1_delmter = USER1_DELMTER_C;
cr->usr1_delmter_m = USER1_DELMTER_C_M;
cr->usr1_eof_padding_len = USER1_EOF_PADDING_LEN_C;
cr->usr1_eof_padding_len_m = USER1_EOF_PADDING_LEN_C_M;
cr->usr1_init_seed = USER1_INIT_SEED_C;
cr->usr1_init_seed_m = USER1_INIT_SEED_C_M;
cr->usr2_delmter = USER2_DELMTER_C;
cr->usr2_delmter_m = USER2_DELMTER_C_M;
cr->usr2_eof_padding_len = USER2_EOF_PADDING_LEN_C;
cr->usr2_eof_padding_len_m = USER2_EOF_PADDING_LEN_C_M;
cr->usr2_init_seed = USER2_INIT_SEED_C;
cr->usr2_init_seed_m = USER2_INIT_SEED_C_M;
cr->usr3_delmter = USER3_DELMTER_C;
cr->usr3_delmter_m = USER3_DELMTER_C_M;
cr->usr3_eof_padding_len = USER3_EOF_PADDING_LEN_C;
cr->usr3_eof_padding_len_m = USER3_EOF_PADDING_LEN_C_M;
cr->usr3_init_seed = USER3_INIT_SEED_C;
cr->usr3_init_seed_m = USER3_INIT_SEED_C_M;
cr->vht_sigb0 = TXD_VHT_SIGB0_C;
cr->vht_sigb0_m = TXD_VHT_SIGB0_C_M;
cr->vht_sigb1 = TXD_VHT_SIGB1_C;
cr->vht_sigb1_m = TXD_VHT_SIGB1_C_M;
cr->vht_sigb2 = TXD_VHT_SIGB2_C;
cr->vht_sigb2_m = TXD_VHT_SIGB2_C_M;
cr->he_sigb_mcs = TXCOMCT_HE_SIGB_MCS_C;
cr->he_sigb_mcs_m = TXCOMCT_HE_SIGB_MCS_C_M;
cr->vht_sigb3 = TXD_VHT_SIGB3_C;
cr->vht_sigb3_m = TXD_VHT_SIGB3_C_M;
cr->n_ltf = TXCOMCT_N_LTF_C;
cr->n_ltf_m = TXCOMCT_N_LTF_C_M;
cr->siga1 = TXD_SIGA1_C;
cr->siga1_m = TXD_SIGA1_C_M;
cr->siga2 = TXD_SIGA2_C;
cr->siga2_m = TXD_SIGA2_C_M;
cr->lsig = TXD_LSIG_C;
cr->lsig_m = TXD_LSIG_C_M;
cr->cca_pw_th = TXINFO_CCA_PW_TH_C;
cr->cca_pw_th_m = TXINFO_CCA_PW_TH_C_M;
cr->n_sym = TXTIMCT_N_SYM_C;
cr->n_sym_m = TXTIMCT_N_SYM_C_M;
cr->usr0_service = USER0_SERVICE_C;
cr->usr0_service_m = USER0_SERVICE_C_M;
cr->usr1_service = USER1_SERVICE_C;
cr->usr1_service_m = USER1_SERVICE_C_M;
cr->usr2_service = USER2_SERVICE_C;
cr->usr2_service_m = USER2_SERVICE_C_M;
cr->usr3_service = USER3_SERVICE_C;
cr->usr3_service_m = USER3_SERVICE_C_M;
cr->usr0_mdpu_len_byte = USER0_MDPU_LEN_BYTE_C;
cr->usr0_mdpu_len_byte_m = USER0_MDPU_LEN_BYTE_C_M;
cr->usr1_mdpu_len_byte = USER1_MDPU_LEN_BYTE_C;
cr->usr1_mdpu_len_byte_m = USER1_MDPU_LEN_BYTE_C_M;
cr->obw_cts2self_dup_type = TXINFO_OBW_CTS2SELF_DUP_TYPE_C;
cr->obw_cts2self_dup_type_m = TXINFO_OBW_CTS2SELF_DUP_TYPE_C_M;
cr->usr2_mdpu_len_byte = USER2_MDPU_LEN_BYTE_C;
cr->usr2_mdpu_len_byte_m = USER2_MDPU_LEN_BYTE_C_M;
cr->usr3_mdpu_len_byte = USER3_MDPU_LEN_BYTE_C;
cr->usr3_mdpu_len_byte_m = USER3_MDPU_LEN_BYTE_C_M;
cr->usr0_csi_buf_id = TXUSRCT0_CSI_BUF_ID_C;
cr->usr0_csi_buf_id_m = TXUSRCT0_CSI_BUF_ID_C_M;
cr->usr1_csi_buf_id = TXUSRCT1_CSI_BUF_ID_C;
cr->usr1_csi_buf_id_m = TXUSRCT1_CSI_BUF_ID_C_M;
cr->rf_gain_idx = TXINFO_RF_GAIN_IDX_C;
cr->rf_gain_idx_m = TXINFO_RF_GAIN_IDX_C_M;
cr->usr2_csi_buf_id = TXUSRCT2_CSI_BUF_ID_C;
cr->usr2_csi_buf_id_m = TXUSRCT2_CSI_BUF_ID_C_M;
cr->usr3_csi_buf_id = TXUSRCT3_CSI_BUF_ID_C;
cr->usr3_csi_buf_id_m = TXUSRCT3_CSI_BUF_ID_C_M;
cr->usr0_n_mpdu = USER0_N_MPDU_C;
cr->usr0_n_mpdu_m = USER0_N_MPDU_C_M;
cr->usr1_n_mpdu = USER1_N_MPDU_C;
cr->usr1_n_mpdu_m = USER1_N_MPDU_C_M;
cr->usr2_n_mpdu = USER2_N_MPDU_C;
cr->usr2_n_mpdu_m = USER2_N_MPDU_C_M;
cr->usr0_pw_boost_fctr_db = TXUSRCT0_PW_BOOST_FCTR_DB_C;
cr->usr0_pw_boost_fctr_db_m = TXUSRCT0_PW_BOOST_FCTR_DB_C_M;
cr->usr3_n_mpdu = USER3_N_MPDU_C;
cr->usr3_n_mpdu_m = USER3_N_MPDU_C_M;
cr->ch20_with_data = TXINFO_CH20_WITH_DATA_C;
cr->ch20_with_data_m = TXINFO_CH20_WITH_DATA_C_M;
cr->n_usr = TXINFO_N_USR_C;
cr->n_usr_m = TXINFO_N_USR_C_M;
cr->txcmd_txtp = TXINFO_TXCMD_TXTP_C;
cr->txcmd_txtp_m = TXINFO_TXCMD_TXTP_C_M;
cr->usr0_ru_alloc = TXUSRCT0_RU_ALLOC_C;
cr->usr0_ru_alloc_m = TXUSRCT0_RU_ALLOC_C_M;
cr->usr0_u_id = TXUSRCT0_U_ID_C;
cr->usr0_u_id_m = TXUSRCT0_U_ID_C_M;
cr->usr1_ru_alloc = TXUSRCT1_RU_ALLOC_C;
cr->usr1_ru_alloc_m = TXUSRCT1_RU_ALLOC_C_M;
cr->usr1_u_id = TXUSRCT1_U_ID_C;
cr->usr1_u_id_m = TXUSRCT1_U_ID_C_M;
cr->usr2_ru_alloc = TXUSRCT2_RU_ALLOC_C;
cr->usr2_ru_alloc_m = TXUSRCT2_RU_ALLOC_C_M;
cr->usr2_u_id = TXUSRCT2_U_ID_C;
cr->usr2_u_id_m = TXUSRCT2_U_ID_C_M;
cr->usr3_ru_alloc = TXUSRCT3_RU_ALLOC_C;
cr->usr3_ru_alloc_m = TXUSRCT3_RU_ALLOC_C_M;
cr->usr3_u_id = TXUSRCT3_U_ID_C;
cr->usr3_u_id_m = TXUSRCT3_U_ID_C_M;
cr->n_sym_hesigb = TXTIMCT_N_SYM_HESIGB_C;
cr->n_sym_hesigb_m = TXTIMCT_N_SYM_HESIGB_C_M;
cr->usr0_mcs = TXUSRCT0_MCS_C;
cr->usr0_mcs_m = TXUSRCT0_MCS_C_M;
cr->usr1_mcs = TXUSRCT1_MCS_C;
cr->usr1_mcs_m = TXUSRCT1_MCS_C_M;
cr->usr2_mcs = TXUSRCT2_MCS_C;
cr->usr2_mcs_m = TXUSRCT2_MCS_C_M;
cr->usr3_mcs = TXUSRCT3_MCS_C;
cr->usr3_mcs_m = TXUSRCT3_MCS_C_M;
cr->usr1_pw_boost_fctr_db = TXUSRCT1_PW_BOOST_FCTR_DB_C;
cr->usr1_pw_boost_fctr_db_m = TXUSRCT1_PW_BOOST_FCTR_DB_C_M;
cr->usr2_pw_boost_fctr_db = TXUSRCT2_PW_BOOST_FCTR_DB_C;
cr->usr2_pw_boost_fctr_db_m = TXUSRCT2_PW_BOOST_FCTR_DB_C_M;
cr->usr3_pw_boost_fctr_db = TXUSRCT3_PW_BOOST_FCTR_DB_C;
cr->usr3_pw_boost_fctr_db_m = TXUSRCT3_PW_BOOST_FCTR_DB_C_M;
cr->ppdu_type = TXINFO_PPDU_TYPE_C;
cr->ppdu_type_m = TXINFO_PPDU_TYPE_C_M;
cr->txsc = TXINFO_TXSC_C;
cr->txsc_m = TXINFO_TXSC_C_M;
cr->cfo_comp = TXINFO_CFO_COMP_C;
cr->cfo_comp_m = TXINFO_CFO_COMP_C_M;
cr->pkt_ext_idx = TXTIMCT_PKT_EXT_IDX_C;
cr->pkt_ext_idx_m = TXTIMCT_PKT_EXT_IDX_C_M;
cr->usr0_n_sts = TXUSRCT0_N_STS_C;
cr->usr0_n_sts_m = TXUSRCT0_N_STS_C_M;
cr->usr0_n_sts_ru_tot = TXUSRCT0_N_STS_RU_TOT_C;
cr->usr0_n_sts_ru_tot_m = TXUSRCT0_N_STS_RU_TOT_C_M;
cr->usr0_strt_sts = TXUSRCT0_STRT_STS_C;
cr->usr0_strt_sts_m = TXUSRCT0_STRT_STS_C_M;
cr->usr1_n_sts = TXUSRCT1_N_STS_C;
cr->usr1_n_sts_m = TXUSRCT1_N_STS_C_M;
cr->usr1_n_sts_ru_tot = TXUSRCT1_N_STS_RU_TOT_C;
cr->usr1_n_sts_ru_tot_m = TXUSRCT1_N_STS_RU_TOT_C_M;
cr->usr1_strt_sts = TXUSRCT1_STRT_STS_C;
cr->usr1_strt_sts_m = TXUSRCT1_STRT_STS_C_M;
cr->usr2_n_sts = TXUSRCT2_N_STS_C;
cr->usr2_n_sts_m = TXUSRCT2_N_STS_C_M;
cr->usr2_n_sts_ru_tot = TXUSRCT2_N_STS_RU_TOT_C;
cr->usr2_n_sts_ru_tot_m = TXUSRCT2_N_STS_RU_TOT_C_M;
cr->usr2_strt_sts = TXUSRCT2_STRT_STS_C;
cr->usr2_strt_sts_m = TXUSRCT2_STRT_STS_C_M;
cr->usr3_n_sts = TXUSRCT3_N_STS_C;
cr->usr3_n_sts_m = TXUSRCT3_N_STS_C_M;
cr->usr3_n_sts_ru_tot = TXUSRCT3_N_STS_RU_TOT_C;
cr->usr3_n_sts_ru_tot_m = TXUSRCT3_N_STS_RU_TOT_C_M;
cr->usr3_strt_sts = TXUSRCT3_STRT_STS_C;
cr->usr3_strt_sts_m = TXUSRCT3_STRT_STS_C_M;
cr->source_gen_mode_idx = SOURCE_GEN_MODE_IDX_C;
cr->source_gen_mode_idx_m = SOURCE_GEN_MODE_IDX_C_M;
cr->gi_type = TXCOMCT_GI_TYPE_C;
cr->gi_type_m = TXCOMCT_GI_TYPE_C_M;
cr->ltf_type = TXCOMCT_LTF_TYPE_C;
cr->ltf_type_m = TXCOMCT_LTF_TYPE_C_M;
cr->dbw_idx = TXINFO_DBW_IDX_C;
cr->dbw_idx_m = TXINFO_DBW_IDX_C_M;
cr->pre_fec_fctr = TXTIMCT_PRE_FEC_FCTR_C;
cr->pre_fec_fctr_m = TXTIMCT_PRE_FEC_FCTR_C_M;
cr->beam_change_en = TXCOMCT_BEAM_CHANGE_EN_C;
cr->beam_change_en_m = TXCOMCT_BEAM_CHANGE_EN_C_M;
cr->doppler_en = TXCOMCT_DOPPLER_EN_C;
cr->doppler_en_m = TXCOMCT_DOPPLER_EN_C_M;
cr->fb_mumimo_en = TXCOMCT_FB_MUMIMO_EN_C;
cr->fb_mumimo_en_m = TXCOMCT_FB_MUMIMO_EN_C_M;
cr->feedback_status = TXCOMCT_FEEDBACK_STATUS_C;
cr->feedback_status_m = TXCOMCT_FEEDBACK_STATUS_C_M;
cr->he_sigb_dcm_en = TXCOMCT_HE_SIGB_DCM_EN_C;
cr->he_sigb_dcm_en_m = TXCOMCT_HE_SIGB_DCM_EN_C_M;
cr->midamble_mode = TXCOMCT_MIDAMBLE_MODE_C;
cr->midamble_mode_m = TXCOMCT_MIDAMBLE_MODE_C_M;
cr->mumimo_ltf_mode_en = TXCOMCT_MUMIMO_LTF_MODE_EN_C;
cr->mumimo_ltf_mode_en_m = TXCOMCT_MUMIMO_LTF_MODE_EN_C_M;
cr->ndp = TXCOMCT_NDP_C;
cr->ndp_m = TXCOMCT_NDP_C_M;
cr->stbc_en = TXCOMCT_STBC_EN_C;
cr->stbc_en_m = TXCOMCT_STBC_EN_C_M;
cr->ant_sel_a = TXINFO_ANT_SEL_A_C;
cr->ant_sel_a_m = TXINFO_ANT_SEL_A_C_M;
cr->ant_sel_b = TXINFO_ANT_SEL_B_C;
cr->ant_sel_b_m = TXINFO_ANT_SEL_B_C_M;
cr->ant_sel_c = TXINFO_ANT_SEL_C_C;
cr->ant_sel_c_m = TXINFO_ANT_SEL_C_C_M;
cr->ant_sel_d = TXINFO_ANT_SEL_D_C;
cr->ant_sel_d_m = TXINFO_ANT_SEL_D_C_M;
cr->cca_pw_th_en = TXINFO_CCA_PW_TH_EN_C;
cr->cca_pw_th_en_m = TXINFO_CCA_PW_TH_EN_C_M;
cr->rf_fixed_gain_en = TXINFO_RF_FIXED_GAIN_EN_C;
cr->rf_fixed_gain_en_m = TXINFO_RF_FIXED_GAIN_EN_C_M;
cr->ul_cqi_rpt_tri = TXINFO_UL_CQI_RPT_TRI_C;
cr->ul_cqi_rpt_tri_m = TXINFO_UL_CQI_RPT_TRI_C_M;
cr->ldpc_extr = TXTIMCT_LDPC_EXTR_C;
cr->ldpc_extr_m = TXTIMCT_LDPC_EXTR_C_M;
cr->usr0_dcm_en = TXUSRCT0_DCM_EN_C;
cr->usr0_dcm_en_m = TXUSRCT0_DCM_EN_C_M;
cr->usr0_fec_type = TXUSRCT0_FEC_TYPE_C;
cr->usr0_fec_type_m = TXUSRCT0_FEC_TYPE_C_M;
cr->usr0_txbf_en = TXUSRCT0_TXBF_EN_C;
cr->usr0_txbf_en_m = TXUSRCT0_TXBF_EN_C_M;
cr->usr1_dcm_en = TXUSRCT1_DCM_EN_C;
cr->usr1_dcm_en_m = TXUSRCT1_DCM_EN_C_M;
cr->usr1_fec_type = TXUSRCT1_FEC_TYPE_C;
cr->usr1_fec_type_m = TXUSRCT1_FEC_TYPE_C_M;
cr->usr1_txbf_en = TXUSRCT1_TXBF_EN_C;
cr->usr1_txbf_en_m = TXUSRCT1_TXBF_EN_C_M;
cr->usr2_dcm_en = TXUSRCT2_DCM_EN_C;
cr->usr2_dcm_en_m = TXUSRCT2_DCM_EN_C_M;
cr->usr2_fec_type = TXUSRCT2_FEC_TYPE_C;
cr->usr2_fec_type_m = TXUSRCT2_FEC_TYPE_C_M;
cr->usr2_txbf_en = TXUSRCT2_TXBF_EN_C;
cr->usr2_txbf_en_m = TXUSRCT2_TXBF_EN_C_M;
cr->usr3_dcm_en = TXUSRCT3_DCM_EN_C;
cr->usr3_dcm_en_m = TXUSRCT3_DCM_EN_C_M;
cr->usr3_fec_type = TXUSRCT3_FEC_TYPE_C;
cr->usr3_fec_type_m = TXUSRCT3_FEC_TYPE_C_M;
cr->usr3_txbf_en = TXUSRCT3_TXBF_EN_C;
cr->usr3_txbf_en_m = TXUSRCT3_TXBF_EN_C_M;
break;
#endif
default:
break;
}
}
#else
enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in,
struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx)
{
return SPEC_INVALID;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_plcp_tx.c
|
C
|
agpl-3.0
| 100,035
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_PLCP_TX_H_
#define _HALBB_PLCP_TX_H_
/* ============================================================
structure
============================================================
*/
struct bb_plcp_cr_info {
u32 b_header_0;
u32 b_header_0_m;
u32 b_header_1;
u32 b_header_1_m;
u32 b_header_2;
u32 b_header_2_m;
u32 b_header_3;
u32 b_header_3_m;
u32 b_header_4;
u32 b_header_4_m;
u32 b_header_5;
u32 b_header_5_m;
u32 b_psdu_byte;
u32 b_psdu_byte_m;
u32 b_carrier_suppress_tx;
u32 b_carrier_suppress_tx_m;
u32 b_ppdu_type;
u32 b_ppdu_type_m;
u32 b_psdu_rate;
u32 b_psdu_rate_m;
u32 b_service_bit2;
u32 b_service_bit2_m;
u32 he_sigb_ch1_0;
u32 he_sigb_ch1_0_m;
u32 he_sigb_ch1_1;
u32 he_sigb_ch1_1_m;
u32 he_sigb_ch1_10;
u32 he_sigb_ch1_10_m;
u32 he_sigb_ch1_11;
u32 he_sigb_ch1_11_m;
u32 he_sigb_ch1_12;
u32 he_sigb_ch1_12_m;
u32 he_sigb_ch1_13;
u32 he_sigb_ch1_13_m;
u32 he_sigb_ch1_14;
u32 he_sigb_ch1_14_m;
u32 he_sigb_ch1_15;
u32 he_sigb_ch1_15_m;
u32 he_sigb_ch1_2;
u32 he_sigb_ch1_2_m;
u32 he_sigb_ch1_3;
u32 he_sigb_ch1_3_m;
u32 he_sigb_ch1_4;
u32 he_sigb_ch1_4_m;
u32 he_sigb_ch1_5;
u32 he_sigb_ch1_5_m;
u32 he_sigb_ch1_6;
u32 he_sigb_ch1_6_m;
u32 he_sigb_ch1_7;
u32 he_sigb_ch1_7_m;
u32 he_sigb_ch1_8;
u32 he_sigb_ch1_8_m;
u32 he_sigb_ch1_9;
u32 he_sigb_ch1_9_m;
u32 he_sigb_ch2_0;
u32 he_sigb_ch2_0_m;
u32 he_sigb_ch2_1;
u32 he_sigb_ch2_1_m;
u32 he_sigb_ch2_10;
u32 he_sigb_ch2_10_m;
u32 he_sigb_ch2_11;
u32 he_sigb_ch2_11_m;
u32 he_sigb_ch2_12;
u32 he_sigb_ch2_12_m;
u32 he_sigb_ch2_13;
u32 he_sigb_ch2_13_m;
u32 he_sigb_ch2_14;
u32 he_sigb_ch2_14_m;
u32 he_sigb_ch2_15;
u32 he_sigb_ch2_15_m;
u32 he_sigb_ch2_2;
u32 he_sigb_ch2_2_m;
u32 he_sigb_ch2_3;
u32 he_sigb_ch2_3_m;
u32 he_sigb_ch2_4;
u32 he_sigb_ch2_4_m;
u32 he_sigb_ch2_5;
u32 he_sigb_ch2_5_m;
u32 he_sigb_ch2_6;
u32 he_sigb_ch2_6_m;
u32 he_sigb_ch2_7;
u32 he_sigb_ch2_7_m;
u32 he_sigb_ch2_8;
u32 he_sigb_ch2_8_m;
u32 he_sigb_ch2_9;
u32 he_sigb_ch2_9_m;
u32 usr0_delmter;
u32 usr0_delmter_m;
u32 usr0_eof_padding_len;
u32 usr0_eof_padding_len_m;
u32 usr0_init_seed;
u32 usr0_init_seed_m;
u32 usr1_delmter;
u32 usr1_delmter_m;
u32 usr1_eof_padding_len;
u32 usr1_eof_padding_len_m;
u32 usr1_init_seed;
u32 usr1_init_seed_m;
u32 usr2_delmter;
u32 usr2_delmter_m;
u32 usr2_eof_padding_len;
u32 usr2_eof_padding_len_m;
u32 usr2_init_seed;
u32 usr2_init_seed_m;
u32 usr3_delmter;
u32 usr3_delmter_m;
u32 usr3_eof_padding_len;
u32 usr3_eof_padding_len_m;
u32 usr3_init_seed;
u32 usr3_init_seed_m;
u32 vht_sigb0;
u32 vht_sigb0_m;
u32 vht_sigb1;
u32 vht_sigb1_m;
u32 vht_sigb2;
u32 vht_sigb2_m;
u32 he_sigb_mcs;
u32 he_sigb_mcs_m;
u32 vht_sigb3;
u32 vht_sigb3_m;
u32 n_ltf;
u32 n_ltf_m;
u32 siga1;
u32 siga1_m;
u32 siga2;
u32 siga2_m;
u32 lsig;
u32 lsig_m;
u32 cca_pw_th;
u32 cca_pw_th_m;
u32 n_sym;
u32 n_sym_m;
u32 usr0_service;
u32 usr0_service_m;
u32 usr1_service;
u32 usr1_service_m;
u32 usr2_service;
u32 usr2_service_m;
u32 usr3_service;
u32 usr3_service_m;
u32 usr0_mdpu_len_byte;
u32 usr0_mdpu_len_byte_m;
u32 usr1_mdpu_len_byte;
u32 usr1_mdpu_len_byte_m;
u32 obw_cts2self_dup_type;
u32 obw_cts2self_dup_type_m;
u32 usr2_mdpu_len_byte;
u32 usr2_mdpu_len_byte_m;
u32 usr3_mdpu_len_byte;
u32 usr3_mdpu_len_byte_m;
u32 usr0_csi_buf_id;
u32 usr0_csi_buf_id_m;
u32 usr1_csi_buf_id;
u32 usr1_csi_buf_id_m;
u32 rf_gain_idx;
u32 rf_gain_idx_m;
u32 usr2_csi_buf_id;
u32 usr2_csi_buf_id_m;
u32 usr3_csi_buf_id;
u32 usr3_csi_buf_id_m;
u32 usr0_n_mpdu;
u32 usr0_n_mpdu_m;
u32 usr1_n_mpdu;
u32 usr1_n_mpdu_m;
u32 usr2_n_mpdu;
u32 usr2_n_mpdu_m;
u32 usr0_pw_boost_fctr_db;
u32 usr0_pw_boost_fctr_db_m;
u32 usr3_n_mpdu;
u32 usr3_n_mpdu_m;
u32 ch20_with_data;
u32 ch20_with_data_m;
u32 n_usr;
u32 n_usr_m;
u32 txcmd_txtp;
u32 txcmd_txtp_m;
u32 usr0_ru_alloc;
u32 usr0_ru_alloc_m;
u32 usr0_u_id;
u32 usr0_u_id_m;
u32 usr1_ru_alloc;
u32 usr1_ru_alloc_m;
u32 usr1_u_id;
u32 usr1_u_id_m;
u32 usr2_ru_alloc;
u32 usr2_ru_alloc_m;
u32 usr2_u_id;
u32 usr2_u_id_m;
u32 usr3_ru_alloc;
u32 usr3_ru_alloc_m;
u32 usr3_u_id;
u32 usr3_u_id_m;
u32 n_sym_hesigb;
u32 n_sym_hesigb_m;
u32 usr0_mcs;
u32 usr0_mcs_m;
u32 usr1_mcs;
u32 usr1_mcs_m;
u32 usr2_mcs;
u32 usr2_mcs_m;
u32 usr3_mcs;
u32 usr3_mcs_m;
u32 usr1_pw_boost_fctr_db;
u32 usr1_pw_boost_fctr_db_m;
u32 usr2_pw_boost_fctr_db;
u32 usr2_pw_boost_fctr_db_m;
u32 usr3_pw_boost_fctr_db;
u32 usr3_pw_boost_fctr_db_m;
u32 ppdu_type;
u32 ppdu_type_m;
u32 txsc;
u32 txsc_m;
u32 cfo_comp;
u32 cfo_comp_m;
u32 pkt_ext_idx;
u32 pkt_ext_idx_m;
u32 usr0_n_sts;
u32 usr0_n_sts_m;
u32 usr0_n_sts_ru_tot;
u32 usr0_n_sts_ru_tot_m;
u32 usr0_strt_sts;
u32 usr0_strt_sts_m;
u32 usr1_n_sts;
u32 usr1_n_sts_m;
u32 usr1_n_sts_ru_tot;
u32 usr1_n_sts_ru_tot_m;
u32 usr1_strt_sts;
u32 usr1_strt_sts_m;
u32 usr2_n_sts;
u32 usr2_n_sts_m;
u32 usr2_n_sts_ru_tot;
u32 usr2_n_sts_ru_tot_m;
u32 usr2_strt_sts;
u32 usr2_strt_sts_m;
u32 usr3_n_sts;
u32 usr3_n_sts_m;
u32 usr3_n_sts_ru_tot;
u32 usr3_n_sts_ru_tot_m;
u32 usr3_strt_sts;
u32 usr3_strt_sts_m;
u32 source_gen_mode_idx;
u32 source_gen_mode_idx_m;
u32 gi_type;
u32 gi_type_m;
u32 ltf_type;
u32 ltf_type_m;
u32 dbw_idx;
u32 dbw_idx_m;
u32 pre_fec_fctr;
u32 pre_fec_fctr_m;
u32 beam_change_en;
u32 beam_change_en_m;
u32 doppler_en;
u32 doppler_en_m;
u32 fb_mumimo_en;
u32 fb_mumimo_en_m;
u32 feedback_status;
u32 feedback_status_m;
u32 he_sigb_dcm_en;
u32 he_sigb_dcm_en_m;
u32 midamble_mode;
u32 midamble_mode_m;
u32 mumimo_ltf_mode_en;
u32 mumimo_ltf_mode_en_m;
u32 ndp;
u32 ndp_m;
u32 stbc_en;
u32 stbc_en_m;
u32 ant_sel_a;
u32 ant_sel_a_m;
u32 ant_sel_b;
u32 ant_sel_b_m;
u32 ant_sel_c;
u32 ant_sel_c_m;
u32 ant_sel_d;
u32 ant_sel_d_m;
u32 cca_pw_th_en;
u32 cca_pw_th_en_m;
u32 rf_fixed_gain_en;
u32 rf_fixed_gain_en_m;
u32 ul_cqi_rpt_tri;
u32 ul_cqi_rpt_tri_m;
u32 ldpc_extr;
u32 ldpc_extr_m;
u32 usr0_dcm_en;
u32 usr0_dcm_en_m;
u32 usr0_fec_type;
u32 usr0_fec_type_m;
u32 usr0_txbf_en;
u32 usr0_txbf_en_m;
u32 usr1_dcm_en;
u32 usr1_dcm_en_m;
u32 usr1_fec_type;
u32 usr1_fec_type_m;
u32 usr1_txbf_en;
u32 usr1_txbf_en_m;
u32 usr2_dcm_en;
u32 usr2_dcm_en_m;
u32 usr2_fec_type;
u32 usr2_fec_type_m;
u32 usr2_txbf_en;
u32 usr2_txbf_en_m;
u32 usr3_dcm_en;
u32 usr3_dcm_en_m;
u32 usr3_fec_type;
u32 usr3_fec_type_m;
u32 usr3_txbf_en;
u32 usr3_txbf_en_m;
u32 usr0_precoding_mode_idx;
u32 usr0_precoding_mode_idx_m;
u32 usr1_precoding_mode_idx;
u32 usr1_precoding_mode_idx_m;
u32 usr2_precoding_mode_idx;
u32 usr2_precoding_mode_idx_m;
u32 usr3_precoding_mode_idx;
u32 usr3_precoding_mode_idx_m;
u32 b_rate_idx;
u32 b_rate_idx_m;
u32 b_locked_clk_en;
u32 b_locked_clk_en_m;
};
struct bb_plcp_info {
struct bb_plcp_cr_info bb_plcp_cr_i;
};
/* ============================================================
Function Prototype
============================================================
*/
struct bb_info;
void halbb_cr_cfg_plcp_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_plcp_tx.h
|
C
|
agpl-3.0
| 8,489
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_PLCP_TX_EX_H_
#define _HALBB_PLCP_TX_EX_H_
/* ============================================================
define
============================================================
*/
#define N_USER 4
#define DL_STA_LIST_MAX_NUM 8
/* ============================================================
Enumeration
============================================================
*/
enum plcp_sts {
PLCP_SUCCESS = 0,
LENGTH_EXCEED,
CCK_INVALID,
OFDM_INVALID,
HT_INVALID,
VHT_INVALID,
HE_INVALID,
SPEC_INVALID
};
/* ============================================================
structure
============================================================
*/
struct cr_address_t {
u32 address;
u32 bitmask;
};
struct ru_rate_entry {
u8 dcm: 1;
u8 ss: 3;
u8 mcs: 4;
};
struct rura_report {
u8 rate_table_col_idx: 6;
u8 partial_allocation_flag: 1;
u8 rate_change_flag: 1;
};
struct dl_ru_output_sta_entry {
u8 dropping_flag: 1; //0
u8 txbf: 1;
u8 coding: 1;
u8 nsts: 3;
u8 rsvd0: 2;
u8 mac_id: 8;
u8 ru_position: 8;
u8 vip_flag: 1; //dont care
u8 pwr_boost_factor: 5; //dont care
u8 rsvd1: 2;
u32 tx_length;
struct ru_rate_entry ru_rate;
//for dl rura
struct rura_report ru_ra_report;
};
struct dl_rua_output {
u16 ru2su_flag: 1;
u16 ppdu_bw: 2; //set
u16 group_tx_pwr: 9;
u16 stbc: 1;
u16 gi_ltf: 3;
u8 doppler: 1;
u8 n_ltf_and_ma: 3;
u8 sta_list_num: 4; //set
u8 grp_mode: 1;
u8 group_id: 6;
u8 fixed_mode: 1; //set 1
struct dl_ru_output_sta_entry dl_output_sta_list[DL_STA_LIST_MAX_NUM];
};
//sig-b output
struct sigb_compute_output {
u8 sta_0_idx: 2;
u8 sta_1_idx: 2;
u8 sta_2_idx: 2;
u8 sta_3_idx: 2;
u32 hw_sigb_content_channelone_len: 8;
u32 hw_sigb_content_channeltwo_len: 8;
u32 hw_sigb_symbolnum: 6;
u32 hw_sigb_content_channeltwo_offset: 5; //have to +1
u32 ru2su_flag: 1;
u32 sigb_dcm: 1;
u32 sigb_mcs: 3;
};
struct bb_h2c_he_sigb {
u16 aid12[4];
u8 force_sigb_rate;
u8 force_sigb_mcs;
u8 force_sigb_dcm;
u8 rsvd;
struct dl_rua_output dl_rua_out;
struct sigb_compute_output sigb_output;
struct cr_address_t n_sym_sigb_ch1[16];
struct cr_address_t n_sym_sigb_ch2[16];
};
//========== [Outer-Input] ==========//
struct usr_plcp_gen_in {
u32 mcs : 6;
u32 mpdu_len : 14;
u32 n_mpdu : 9;
u32 fec : 1;
u32 dcm : 1;
u32 rsvd0 : 1;
u32 aid : 12;
u32 scrambler_seed : 8; // rand (1~255)
u32 random_init_seed : 8; // rand (1~255)
u32 rsvd1 : 4;
u32 apep : 22;
u32 ru_alloc : 8;
u32 rsvd2 : 2;
u32 nss : 4;
u32 txbf : 1;
u32 pwr_boost_db : 5;
u32 rsvd3 : 22;
};
struct halbb_plcp_info {
u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80
u32 source_gen_mode : 2;
u32 locked_clk : 1;
u32 dyn_bw : 1;
u32 ndp_en : 1;
u32 long_preamble_en : 1; //bmode
u32 stbc : 1;
u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2
u32 tb_l_len : 12;
u32 tb_ru_tot_sts_max : 3;
u32 vht_txop_not_allowed : 1;
u32 tb_disam : 1;
u32 doppler : 2;
u32 he_ltf_type : 2;//0:1x,1:2x,2:4x
u32 ht_l_len : 12;
u32 preamble_puncture : 1;
u32 he_mcs_sigb : 3;//0~5
u32 he_dcm_sigb : 1;
u32 he_sigb_compress_en : 1;
u32 max_tx_time_0p4us : 14;
u32 ul_flag : 1;
u32 tb_ldpc_extra : 1;
u32 bss_color : 6;
u32 sr : 4;
u32 beamchange_en : 1;
u32 he_er_u106ru_en : 1;
u32 ul_srp1 : 4;
u32 ul_srp2 : 4;
u32 ul_srp3 : 4;
u32 ul_srp4 : 4;
u32 mode : 2;
u32 group_id : 6;
u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB
u32 txop : 7;
u32 tb_strt_sts : 3;
u32 tb_pre_fec_padding_factor : 2;
u32 cbw : 2;
u32 txsc : 4;
u32 tb_mumimo_mode_en : 1;
u32 rsvd1 : 3;
u8 nominal_t_pe : 2; // def = 2
u8 ness : 2; // def = 0
u8 rsvd2 : 4;
u8 n_user;
u16 tb_rsvd : 9;//def = 0
u16 rsvd3 : 7;
struct usr_plcp_gen_in usr[N_USER];
};
/* ============================================================
Function Prototype
============================================================
*/
struct bb_info;
enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in,
struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_plcp_tx_ex.h
|
C
|
agpl-3.0
| 5,226
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
/*============================ [Tx Settings] =============================*/
void halbb_set_pmac_tx(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_set_pmac_tx_8852a(bb, tx_info, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_set_pmac_tx_8852a_2(bb, tx_info, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_set_pmac_tx_8852b(bb, tx_info, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_set_pmac_tx_8852c(bb, tx_info, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
halbb_set_tmac_tx_8852a(bb, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_set_tmac_tx_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_set_tmac_tx_8852b(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_set_tmac_tx_8852c(bb, phy_idx);
break;
#endif
default:
break;
}
}
/*============================ [Power Module] =============================*/
bool halbb_cfg_lbk(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
enum rf_path tx_path, enum rf_path rx_path,
enum channel_width bw, enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_A_CUT_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_cfg_lbk_8852c(bb, lbk_en, is_dgt_lbk, tx_path,
rx_path, bw, phy_idx);
break;
#endif
default:
break;
}
return rpt;
}
/*============================ [Power Module] =============================*/
bool halbb_set_txpwr_dbm(struct bb_info *bb, s16 pwr_dbm,
enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_set_txpwr_dbm_8852a(bb, pwr_dbm, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_txpwr_dbm_8852a_2(bb, pwr_dbm, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_txpwr_dbm_8852b(bb, pwr_dbm, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_txpwr_dbm_8852c(bb, pwr_dbm, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
s16 halbb_get_txpwr_dbm(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
s16 rpt;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_get_txpwr_dbm_8852a(bb, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_txpwr_dbm_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_get_txpwr_dbm_8852b(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_txpwr_dbm_8852c(bb, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
s16 halbb_get_txinfo_txpwr_dbm(struct bb_info *bb)
{
s16 rpt;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_get_txinfo_txpwr_dbm_8852a(bb);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_txinfo_txpwr_dbm_8852a_2(bb);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_get_txinfo_txpwr_dbm_8852b(bb);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_txinfo_txpwr_dbm_8852c(bb);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_set_cck_txpwr_idx(struct bb_info *bb, u16 pwr_idx,
enum rf_path tx_path)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_set_cck_txpwr_idx_8852a(bb, pwr_idx, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_cck_txpwr_idx_8852a_2(bb, pwr_idx, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_cck_txpwr_idx_8852b(bb, pwr_idx, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_cck_txpwr_idx_8852c(bb, pwr_idx, tx_path);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
u16 halbb_get_cck_txpwr_idx(struct bb_info *bb, enum rf_path tx_path)
{
u16 rpt;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_get_cck_txpwr_idx_8852a(bb, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_cck_txpwr_idx_8852a_2(bb, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_get_cck_txpwr_idx_8852b(bb, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_cck_txpwr_idx_8852c(bb, tx_path);
break;
#endif
default:
rpt= false;
break;
}
return rpt;
}
s16 halbb_get_cck_ref_dbm(struct bb_info *bb, enum rf_path tx_path)
{
s16 rpt;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_get_cck_ref_dbm_8852a(bb, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_cck_ref_dbm_8852a_2(bb, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_get_cck_ref_dbm_8852b(bb, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_cck_ref_dbm_8852c(bb, tx_path);
break;
#endif
default:
rpt= false;
break;
}
return rpt;
}
bool halbb_set_ofdm_txpwr_idx(struct bb_info *bb, u16 pwr_idx,
enum rf_path tx_path)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_set_ofdm_txpwr_idx_8852a(bb, pwr_idx, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_ofdm_txpwr_idx_8852a_2(bb, pwr_idx, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_ofdm_txpwr_idx_8852b(bb, pwr_idx, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_ofdm_txpwr_idx_8852c(bb, pwr_idx, tx_path);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
u16 halbb_get_ofdm_txpwr_idx(struct bb_info *bb, enum rf_path tx_path)
{
u16 rpt;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_get_ofdm_txpwr_idx_8852a(bb, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_ofdm_txpwr_idx_8852a_2(bb, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_get_ofdm_txpwr_idx_8852b(bb, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_ofdm_txpwr_idx_8852c(bb, tx_path);
break;
#endif
default:
rpt= false;
break;
}
return rpt;
}
s16 halbb_get_ofdm_ref_dbm(struct bb_info *bb, enum rf_path tx_path)
{
s16 rpt;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_get_ofdm_ref_dbm_8852a(bb, tx_path);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_get_ofdm_ref_dbm_8852a_2(bb, tx_path);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_get_ofdm_ref_dbm_8852b(bb, tx_path);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_get_ofdm_ref_dbm_8852c(bb, tx_path);
break;
#endif
default:
rpt= false;
break;
}
return rpt;
}
/*============================ [Others] =============================*/
bool halbb_chk_tx_idle(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_chk_tx_idle_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_chk_tx_idle_8852c(bb, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
void halbb_dpd_bypass(struct bb_info *bb, bool pdp_bypass,
enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_dpd_bypass_8852a_2(bb, pdp_bypass, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
//halbb_dpd_bypass_8852b(bb, pdp_bypass, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_dpd_bypass_8852c(bb, pdp_bypass, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_backup_info(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_backup_info_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_backup_info_8852b(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_backup_info_8852c(bb, phy_idx);
break;
#endif
default:
break;
}
}
void halbb_restore_info(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_restore_info_8852a_2(bb, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_restore_info_8852b(bb, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_restore_info_8852c(bb, phy_idx);
break;
#endif
default:
break;
}
}
bool halbb_set_txsc(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_set_txsc_8852a(bb, txsc, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_txsc_8852a_2(bb, txsc, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_txsc_8852b(bb, txsc, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_txsc_8852c(bb, txsc, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_set_bss_color(struct bb_info *bb, u8 bss_color,
enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_set_bss_color_8852a(bb, bss_color, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_bss_color_8852a_2(bb, bss_color, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_bss_color_8852b(bb, bss_color, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_bss_color_8852c(bb, bss_color, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
bool halbb_set_sta_id(struct bb_info *bb, u16 sta_id, enum phl_phy_idx phy_idx)
{
bool rpt = true;
switch (bb->ic_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_RTL8852AA:
rpt = halbb_set_sta_id_8852a(bb, sta_id, phy_idx);
break;
#endif
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
rpt = halbb_set_sta_id_8852a_2(bb, sta_id, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
rpt = halbb_set_sta_id_8852b(bb, sta_id, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
rpt = halbb_set_sta_id_8852c(bb, sta_id, phy_idx);
break;
#endif
default:
rpt = false;
break;
}
return rpt;
}
void halbb_pmac_tx_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{bw} {pri_ch bw} {phy_idx}\n");
} else if (_os_strcmp(input[1], "tx_path") == 0) {
HALBB_SCAN(input[1], DCMD_DECIMAL, &val[0]);
//halbb_set_pmac_tx_path(bb, (enum bb_path)val[0]);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Cfg Tx Path API \n");
}
*_used = used;
*_out_len = out_len;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_pmac_setting.c
|
C
|
agpl-3.0
| 13,474
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_PMAC_SETTING_H_
#define _HALBB_PMAC_SETTING_H_
/* ============================================================
Enumeration
============================================================
*/
enum halbb_pmac_mode {
NONE_TEST,
PKTS_TX,
PKTS_RX,
CONT_TX,
FW_TRIG_TX,
OFDM_SINGLE_TONE_TX,
CCK_CARRIER_SIPPRESSION_TX
};
/* ============================================================
Function Prototype
============================================================
*/
struct bb_info;
void halbb_pmac_tx_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_pmac_setting.h
|
C
|
agpl-3.0
| 1,612
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_PMAC_SETTING_EX_H_
#define _HALBB_PMAC_SETTING_EX_H_
#include "halbb_ic_hw_info.h"
#include "halbb_pmac_setting.h"
/* ============================================================
structure
============================================================
*/
struct halbb_pmac_info {
u8 en_pmac_tx:1; /*0: PMAC Tx Off 1: PMAC Tx On */
u8 is_cck:1;
u8 mode:3; /*1: Packet TX 3:Continuous TX */
u8 rsvd:3;
u16 tx_cnt;
u16 period; // us
u16 tx_time; // us
u8 duty_cycle; // for fw trig. tx used
};
struct bb_h2c_fw_tx_setting {
u8 pkt_cnt[2];
bool tx_en;
u8 tx_type;
u8 tx_period[4];
u8 tx_time[4];
u8 duty_cycle[4];
};
struct bb_c2h_fw_tx_rpt {
bool tx_done;
};
/* ============================================================
Function Prototype
============================================================
*/
struct bb_info;
void halbb_set_pmac_tx(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx);
void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_cfg_lbk(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
enum rf_path tx_path, enum rf_path rx_path,
enum channel_width bw, enum phl_phy_idx phy_idx);
bool halbb_set_txpwr_dbm(struct bb_info *bb, s16 pwr_dbm,
enum phl_phy_idx phy_idx);
s16 halbb_get_txpwr_dbm(struct bb_info *bb, enum phl_phy_idx phy_idx);
s16 halbb_get_txinfo_txpwr_dbm(struct bb_info *bb);
bool halbb_set_cck_txpwr_idx(struct bb_info *bb, u16 pwr_idx,
enum rf_path tx_path);
u16 halbb_get_cck_txpwr_idx(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_cck_ref_dbm(struct bb_info *bb, enum rf_path tx_path);
bool halbb_set_ofdm_txpwr_idx(struct bb_info *bb, u16 pwr_idx,
enum rf_path tx_path);
u16 halbb_get_ofdm_txpwr_idx(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_ofdm_ref_dbm(struct bb_info *bb, enum rf_path tx_path);
bool halbb_chk_tx_idle(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_dpd_bypass(struct bb_info *bb, bool pdp_bypass,
enum phl_phy_idx phy_idx);
void halbb_backup_info(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_restore_info(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_set_txsc(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx);
bool halbb_set_bss_color(struct bb_info *bb, u8 bss_color,
enum phl_phy_idx phy_idx);
bool halbb_set_sta_id(struct bb_info *bb, u16 sta_id, enum phl_phy_idx phy_idx);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_pmac_setting_ex.h
|
C
|
agpl-3.0
| 3,464
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_PRECOMP_H__
#define __HALBB_PRECOMP_H__
#include "halbb_cfg_ic.h"
/*---[Define Only] ----------------------------------------------------------*/
#include "../../hal_headers_le.h"
#include "halbb_types.h"
#include "halbb_features.h"
#include "halbb_ic_hw_info.h"
#include "halbb_ic_sw_info.h"
#include "halbb_interface.h"
#include "halbb_rua_tbl_ex.h"
#if (PLATFOM_IS_LITTLE_ENDIAN)
#include "halbb_physts_ie_l_endian.h"
#include "halbb_ra_l_endian.h"
#include "halbb_rua_tbl_l_endian.h"
#else
#include "halbb_physts_ie_b_endian.h"
#include "halbb_ra_b_endian.h"
#include "halbb_rua_tbl_b_endian.h"
#endif
/*---[Include structure & prototype] ----------------------------------------*/
#ifdef BB_8852A_CAV_SUPPORT
#include "halbb_8852a/halbb_cr_info_8852a_a_cut.h"
#include "halbb_8852a/halbb_8852a.h"
#include "halbb_8852a/halbb_8852a_api.h"
#include "halbb_8852a/halbb_8852a_api_ex.h"
#include "halbb_8852a/halbb_hwimg_8852a.h"
#include "halbb_8852a/halbb_reg_cfg_8852a.h"
#include "halbb_8852a/halbb_version_rtl8852a.h"
#endif
#ifdef BB_8852A_2_SUPPORT
#include "halbb_8852a_2/halbb_cr_info_8852a_2.h"
#include "halbb_8852a_2/halbb_8852a_2.h"
#include "halbb_8852a_2/halbb_8852a_2_api.h"
#include "halbb_8852a_2/halbb_8852a_2_api_ex.h"
#include "halbb_8852a_2/halbb_hwimg_8852a_2.h"
#include "halbb_8852a_2/halbb_reg_cfg_8852a_2.h"
#include "halbb_8852a_2/halbb_version_rtl8852a_2.h"
#endif
#ifdef BB_8852B_SUPPORT
#include "halbb_8852b/halbb_cr_info_8852b.h"
#include "halbb_8852b/halbb_8852b.h"
#include "halbb_8852b/halbb_8852b_api.h"
#include "halbb_8852b/halbb_8852b_api_ex.h"
#include "halbb_8852b/halbb_hwimg_8852b.h"
#include "halbb_8852b/halbb_reg_cfg_8852b.h"
#include "halbb_8852b/halbb_version_rtl8852b.h"
#endif
#ifdef BB_8852C_SUPPORT
#include "halbb_8852c/halbb_cr_info_8852c.h"
#include "halbb_8852c/halbb_8852c.h"
#include "halbb_8852c/halbb_8852c_api.h"
#include "halbb_8852c/halbb_8852c_api_ex.h"
#include "halbb_8852c/halbb_hwimg_8852c.h"
#include "halbb_8852c/halbb_reg_cfg_8852c.h"
#include "halbb_8852c/halbb_version_rtl8852c.h"
#endif
#include "halbb_ra.h"
#include "halbb_ra_ex.h"
#include "halbb_hw_cfg.h"
#include "halbb_hw_cfg_ex.h"
#include "halbb_api.h"
#include "halbb_api_ex.h"
#include "halbb_interface_ex.h"
#include "halbb_math_lib_ex.h"
#include "halbb_math_lib.h"
#include "halbb_dbg.h"
#include "halbb_dbg_cmd.h"
#include "halbb_dbg_cmd_ex.h"
#include "halbb_physts_ex.h"
#include "halbb_physts.h"
#include "halbb_cmn_rpt_ex.h"
#include "halbb_cmn_rpt.h"
#include "halbb_init.h"
#include "halbb_init_ex.h"
#include "halbb_pmac_setting.h"
#include "halbb_pmac_setting_ex.h"
#include "halbb_plcp_tx_ex.h"
#include "halbb_plcp_tx.h"
#include "halbb_plcp_gen.h"
#include "halbb_la_mode_ex.h"
#include "halbb_la_mode.h"
#include "halbb_psd.h"
#include "halbb_pwr_ctrl_ex.h"
#include "halbb_pwr_ctrl.h"
#include "halbb_mp_ex.h"
#include "halbb_dfs.h"
#include "halbb_dfs_ex.h"
#include "halbb_cfo_trk.h"
#include "halbb_edcca.h"
#include "halbb_edcca_ex.h"
#include "halbb_env_mntr_ex.h"
#include "halbb_env_mntr.h"
#include "halbb_dig_ex.h"
#include "halbb_dig.h"
#include "halbb_dyn_csi_rsp.h"
#include "halbb_dyn_csi_rsp_ex.h"
#include "halbb_ant_div.h"
#include "halbb_statistics.h"
#include "halbb_ch_info_ex.h"
#include "halbb_ch_info.h"
#include "halbb_auto_dbg.h"
#include "halbb_dbcc_ex.h"
#include "halbb_dbcc.h"
#include "halbb_rua_tbl.h"
#include "halbb_fwofld.h"
#include "halbb_ex.h"
#include "halbb.h"
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_precomp.h
|
C
|
agpl-3.0
| 4,488
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_PSD_SUPPORT
static const u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
static const u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
void halbb_psd_igi_lv(struct bb_info *bb, enum igi_lv_sel igi_lv)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
if (igi_lv == IGI_DEFAULT) {
psd->igi_pin = 28;
halbb_set_reg(bb, 0x1590, 0x7000, psd->lna_bkp);
halbb_set_reg(bb, 0x1650, 0x7000, psd->lna_bkp_b);
halbb_set_reg(bb, 0x1598, BIT(20), psd->tia_bkp);
halbb_set_reg(bb, 0x1658, BIT(20), psd->tia_bkp_b);
halbb_set_reg(bb, 0x1580, 0x3e0, psd->rxbb_bkp);
halbb_set_reg(bb, 0x1640, 0x3e0, psd->rxbb_bkp_b);
} else if (igi_lv == IGI_LEVEL1) {/*@ target Pin=-72dBm*/
psd->igi_pin = 28;
halbb_set_reg(bb, 0x1590, 0x7000, 0x6);
halbb_set_reg(bb, 0x1650, 0x7000, 0x6);
halbb_set_reg(bb, 0x1598, BIT(20), 0x1);
halbb_set_reg(bb, 0x1658, BIT(20), 0x1);
halbb_set_reg(bb, 0x1580, 0x3e0, 0x1f);
halbb_set_reg(bb, 0x1640, 0x3e0, 0x1f);
} else if (igi_lv == IGI_LEVEL2) {/*@ target Pin=-50dBm*/
psd->igi_pin = 50;
halbb_set_reg(bb, 0x1590, 0x7000, 0x6);
halbb_set_reg(bb, 0x1650, 0x7000, 0x6);
halbb_set_reg(bb, 0x1598, BIT(20), 0x1);
halbb_set_reg(bb, 0x1658, BIT(20), 0x1);
halbb_set_reg(bb, 0x1580, 0x3e0, 0x9);
halbb_set_reg(bb, 0x1640, 0x3e0, 0x9);
} else if (igi_lv == IGI_LEVEL3) {/*@ target Pin=-35dBm*/
psd->igi_pin = 65;
halbb_set_reg(bb, 0x1590, 0x7000, 0x6);
halbb_set_reg(bb, 0x1650, 0x7000, 0x6);
halbb_set_reg(bb, 0x1598, BIT(20), 0x0);
halbb_set_reg(bb, 0x1658, BIT(20), 0x0);
halbb_set_reg(bb, 0x1580, 0x3e0, 0x0);
halbb_set_reg(bb, 0x1640, 0x3e0, 0x0);
} else if (igi_lv == IGI_LEVEL4) {/*@ target Pin=0dBm*/
psd->igi_pin = 100;
halbb_set_reg(bb, 0x1590, 0x7000, 0x0);
halbb_set_reg(bb, 0x1650, 0x7000, 0x0);
halbb_set_reg(bb, 0x1598, BIT(20), 0x0);
halbb_set_reg(bb, 0x1658, BIT(20), 0x0);
halbb_set_reg(bb, 0x1580, 0x3e0, 0x8);
halbb_set_reg(bb, 0x1640, 0x3e0, 0x8);
}
}
u32 halbb_get_psd_data(struct bb_info *bb, u32 psd_tone_idx, u32 igi_pin)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
struct bb_psd_cr_info *cr = &psd->bb_psd_cr_i;
u8 i = 0;
u8 j = 0;
u32 psd_report = 0;
bool psd_rdy = false;
halbb_set_reg(bb, cr->fft_idx, cr->fft_idx_m, psd_tone_idx & 0x3ff);
/*PSD trigger start*/
halbb_set_reg(bb, cr->psd_en, cr->psd_en_m, 1);
halbb_delay_us(bb, 10 << (psd->fft_point >> 7));
/*Get PSD Report*/
do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
psd_rdy = (u8)halbb_get_reg(bb, psd->psd_report_reg, BIT(25));
if (!psd_rdy) {
halbb_delay_us(bb, 100);
i++;
continue;
} else {
/*BB_DBG(bb, DBG_DBG_API, "psd_rdy = %d\n", psd_rdy);*/
psd_report = halbb_get_reg(bb, psd->psd_report_reg,
0x1ffffff);
/*psd_report = psd_report >> 22;*/
psd_report = halbb_convert_to_db((u64)psd_report) +
igi_pin;
break;
}
psd_report = 0;
} while (i < 20);
/*PSD trigger stop*/
halbb_set_reg(bb, psd->psd_reg, BIT(22), 0);
do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
psd_rdy = (u8)halbb_get_reg(bb, psd->psd_report_reg, BIT(25));
if (psd_rdy) {
/*BB_TRACE("psd_rdy2 = %d, wait %d * 100us for release \n", psd_rdy, (j + 1));*/
halbb_delay_us(bb, 100);
j++;
continue;
} else {
break;
}
} while (j < 20);
return psd_report;
}
void halbb_psd_para_setting(struct bb_info *bb, u8 sw_avg_time, u8 hw_avg_time,
u8 i_q_setting, u16 fft_point, u8 path,
u8 psd_input, u8 channel, u8 bw)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
u8 fft_idx = 0;
psd->fft_point_pre = psd->fft_point;
psd->fft_point = fft_point;
if (sw_avg_time == 0)
sw_avg_time = 1;
psd->sw_avg_time = sw_avg_time;
psd->hw_avg_time = hw_avg_time;
psd->i_q_setting = i_q_setting;
psd->path = path;
psd->input = psd_input;
psd->psd_fc_ch = channel;
psd->bw = bw;
if (fft_point == 128)
fft_idx = 3;
else if (fft_point == 256)
fft_idx = 2;
else if (fft_point == 512)
fft_idx = 1;
else if (fft_point == 1024)
fft_idx = 0;
halbb_set_reg(bb, psd->psd_reg, BIT(16) | BIT(15), fft_idx);
halbb_set_reg(bb, psd->psd_reg, BIT(12) | BIT(11), i_q_setting);
halbb_set_reg(bb, psd->psd_reg, BIT(14) | BIT(13), hw_avg_time);
halbb_set_reg(bb, psd->psd_reg, BIT(18) | BIT(17), path);
halbb_set_reg(bb, psd->psd_reg, BIT(20) | BIT(19), psd_input);
}
bool halbb_psd_alloc_buff(struct bb_info *bb)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
if (!psd->rpt) {
psd->rpt = (u8 *)halbb_mem_alloc(bb, psd->fft_point);
} else if (psd->rpt && psd->fft_point != psd->fft_point_pre) {
halbb_mem_free(bb, psd->rpt, sizeof(psd->rpt));
psd->rpt = (u8 *)halbb_mem_alloc(bb, psd->fft_point);
}
if (!psd->rpt)
return false;
else
return true;
}
void halbb_get_gain_index(struct bb_info *bb)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
psd->lna_bkp = (u8)halbb_get_reg(bb, 0x1590, 0x7000);
psd->lna_bkp_b = (u8)halbb_get_reg(bb, 0x1650, 0x7000);
psd->tia_bkp = (u8)halbb_get_reg(bb, 0x1598, BIT(20));
psd->tia_bkp_b = (u8)halbb_get_reg(bb, 0x1658, BIT(20));
psd->rxbb_bkp = (u8)halbb_get_reg(bb, 0x1580, 0x3e0);
psd->rxbb_bkp_b = (u8)halbb_get_reg(bb, 0x1640, 0x3e0);
}
u8 halbb_psd(struct bb_info *bb, enum igi_lv_sel igi_lv, u16 start_point,
u16 stop_point)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
struct bb_api_info *api = &bb->bb_api_i;
u32 i = 0, mod_tone_idx = 0;
u32 t = 0;
u16 fft_max_half_bw = 0;
u16 fail_cnt = 0;
u16 valid_cnt = 0;
u8 psd_fc_ch = psd->psd_fc_ch;
enum band_type psd_band = psd->psd_band;
u8 bw = psd->bw;
u32 psd_result_tmp = 0;
u32 psd_result_total = 0;
u8 psd_result = 0;
u8 psd_result_cali_tone[7] = {0};
u8 psd_result_cali_val[7] = {0};
u8 noise_idx = 0;
u8 set_result = 0;
u8 psd_pri_ch = 1;
if (bb->hal_com->chip_id == CHIP_WIFI6_8852A) {
halbb_mem_cpy(bb, psd_result_cali_tone,
psd_result_cali_tone_8821, 7);
halbb_mem_cpy(bb, psd_result_cali_val,
psd_result_cali_val_8821, 7);
}
psd->psd_in_progress = 1;
halbb_set_reg(bb, 0x014, BIT(1), 1);
BB_TRACE(" PSD_Start =>\n");
/* @[Get default gain value]*/
halbb_get_gain_index(bb);
/* @[Stop pre-AGC]*/
/* @[Set High IGI level & make it can't CCA]*/
halbb_pre_agc_en(bb, false);
halbb_psd_igi_lv(bb, IGI_LEVEL4);
halbb_delay_us(bb, 10);
BB_TRACE(" sw_avg_time = %d , hw_avg_time = %d , IQ = %d , fft_point = %d , path = %d , input = %d , ch = %d , BW = %d\n",
psd->sw_avg_time, psd->hw_avg_time, psd->i_q_setting,
psd->fft_point, psd->path, psd->input, psd_fc_ch, bw);
if (halbb_stop_ic_trx(bb, HALBB_SET) == HALBB_SET_FAIL) {
/*@[resume pre-AGC and resume IGI level]*/
halbb_pre_agc_en(bb, true);
halbb_psd_igi_lv(bb, IGI_DEFAULT);
return HALBB_SET_FAIL;
}
/* @[Set IGI level]*/
halbb_psd_igi_lv(bb, igi_lv);
/* @[Backup RF Reg]*/
psd->rf_0x18_bkp = halbb_read_rf_reg(bb, RF_PATH_A, 0x18,
RFREGOFFSETMASK);
psd->rf_0x18_bkp_b = halbb_read_rf_reg(bb, RF_PATH_B, 0x18,
RFREGOFFSETMASK);
if ((psd->input == 0) || (psd->input == 1)) {
if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)
psd->psd_bw = 80;
else
psd->psd_bw = 160;
} else if ((psd->input == 2) || (psd->input == 3)) {
if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)
psd->psd_bw = 40;
else
psd->psd_bw = 80;
}
if (psd->psd_bw == 80)
halbb_set_reg(bb, 0x9c8, BIT(23), 1);
else
halbb_set_reg(bb, 0x9c8, BIT(23), 0);
BB_DBG(bb, DBG_DBG_API, " PSD_BW = %d\n", psd->psd_bw);
/* Set RF fc*/
if(halbb_ctrl_ch(bb, psd_fc_ch, psd_band, HW_PHY_0) == false)
return HALBB_SET_FAIL;
if(halbb_ctrl_ch(bb, psd_fc_ch, psd_band, HW_PHY_1) == false)
return HALBB_SET_FAIL;
if(halbb_ctrl_bw(bb, psd_pri_ch, bw, HW_PHY_0) == false)
return HALBB_SET_FAIL;
if(halbb_ctrl_bw(bb, psd_pri_ch, bw, HW_PHY_1) == false)
return HALBB_SET_FAIL;
BB_DBG(bb, DBG_DBG_API, "RF0x18=((0x%x))\n",
halbb_read_rf_reg(bb, RF_PATH_A, 0x18, RFREGOFFSETMASK));
halbb_delay_us(bb, 10);
if (stop_point > (psd->fft_point - 1))
stop_point = (psd->fft_point - 1);
if (start_point > (psd->fft_point - 1))
start_point = (psd->fft_point - 1);
if (start_point > stop_point)
stop_point = start_point;
for (i = start_point; i <= stop_point; i++) {
fft_max_half_bw = (psd->fft_point) >> 1;
if (i < fft_max_half_bw)
mod_tone_idx = i + fft_max_half_bw;
else
mod_tone_idx = i - fft_max_half_bw;
psd_result_tmp = 0;
psd_result_total = 0;
fail_cnt = 0;
for (t = 0; t < psd->sw_avg_time; t++) {
psd_result_tmp = halbb_get_psd_data(bb, mod_tone_idx,
psd->igi_pin);
if (psd_result_tmp == 0)
fail_cnt ++;
psd_result_total += psd_result_tmp;
}
if (psd->sw_avg_time > fail_cnt)
valid_cnt = psd->sw_avg_time - fail_cnt;
else
valid_cnt = psd->sw_avg_time;
psd_result = (u8)((psd_result_total / valid_cnt)) -
psd->psd_pwr_common_offset;
psd->rpt[i] = psd_result;
if (psd->fft_point == 128 && psd->noise_k_en) {
if (i > psd_result_cali_tone[noise_idx])
noise_idx++;
if (noise_idx > 6)
noise_idx = 6;
if (psd_result >= psd_result_cali_val[noise_idx])
psd_result = psd_result -
psd_result_cali_val[noise_idx];
else
psd_result = 0;
psd->psd_result[i] = psd_result;
}
BB_DBG(bb, DBG_DBG_API, "[%-4d] N_cali = %d, PSD = %d\n",
mod_tone_idx, psd_result_cali_val[noise_idx],
psd_result);
}
/*@[Revert Reg]*/
set_result = halbb_stop_ic_trx(bb, HALBB_REVERT);
halbb_ctrl_ch(bb, api->central_ch, api->band, HW_PHY_0);
halbb_ctrl_ch(bb, api->central_ch, api->band, HW_PHY_1);
halbb_ctrl_bw(bb, api->pri_ch_idx, (enum channel_width)api->bw,
HW_PHY_0);
halbb_ctrl_bw(bb, api->pri_ch_idx, (enum channel_width)api->bw,
HW_PHY_1);
BB_DBG(bb, DBG_DBG_API, " PSD_finish\n\n");
/*@[Resume pre-AGC and IGI level]*/
halbb_pre_agc_en(bb, true);
halbb_psd_igi_lv(bb, IGI_DEFAULT);
psd->psd_in_progress = 0;
return HALBB_SET_SUCCESS;
}
void halbb_psd_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
HALBB_SCAN(input[1], DCMD_DECIMAL, &var1[0]);
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{0} {sw_avg} {hw_avg 0:3} {0:I,1:Q,2:IQ} {fft_point: 128/256/512/1024}\n{path_sel 0~3} {00: dout_sub20_0_40M, 01: ccx_in, 10: dout_cfir, 11: rxdib_in} {CH} {BW 20/40/80: 0/1/2}\n\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{1} {IGI_lv(0:4)} {start_point} {stop_point}\n");
} else if (var1[0] == 0) {
for (i = 1; i < 10; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL,
&var1[i]);
}
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), bw=((%d))\n",
var1[1], var1[2], var1[3], var1[4], var1[5],
var1[6], (u8)var1[7], (u8)var1[8]);
halbb_psd_para_setting(bb, (u8)var1[1], (u8)var1[2],
(u8)var1[3], (u16)var1[4], (u8)var1[5],
(u8)var1[6], (u8)var1[7], (u8)var1[8]);
} else if (var1[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var1[1]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &var1[2]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &var1[3]);
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"IGI_lv=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
var1[1], var1[2], var1[3]);
bb->dbg_component |= DBG_DBG_API;
if (!halbb_psd_alloc_buff(bb)) {
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "memory alloc FAIL\n");
return;
}
if (halbb_psd(bb, (enum igi_lv_sel)var1[1], (u16)var1[2],
(u16)var1[3]) == HALBB_SET_FAIL)
BB_DBG_CNSL(out_len, used, output + used,
out_len - used, "PSD_SET_FAIL\n");
bb->dbg_component &= ~(DBG_DBG_API);
}
*_used = used;
*_out_len = out_len;
}
void halbb_psd_init(struct bb_info *bb)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
BB_DBG(bb, DBG_DBG_API, "[%s]\n", __func__);
psd->psd_in_progress = false;
psd->psd_reg = 0x1150;
psd->psd_report_reg = 0x40b4;
psd->psd_pwr_common_offset = 0;
psd->fft_point_pre = 0;
halbb_psd_para_setting(bb, 1, 3, 2, 512, 0, 0, 36, 0);
}
void halbb_psd_deinit(struct bb_info *bb)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
if (psd->rpt)
halbb_mem_free(bb, psd->rpt, sizeof(psd->rpt));
}
bool halbb_get_psd_result(struct bb_info *bb, u8 *psd_data, u16 *psd_len)
{
struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i;
if (!psd->rpt)
return false;
psd_data = psd->rpt;
*psd_len = psd->fft_point;
return true;
}
void halbb_cr_cfg_psd_init(struct bb_info *bb)
{
struct bb_psd_cr_info *cr = &bb->bb_cmn_hooker->bb_psd_i.bb_psd_cr_i;
switch (bb->cr_type) {
#ifdef HALBB_52AA_SERIES
case BB_52AA:
cr->fft_idx = PSD_FFT_IDX_52AA;
cr->fft_idx_m = PSD_FFT_IDX_52AA_M;
cr->psd_en = PSD_ENABLE_52AA;
cr->psd_en_m = PSD_ENABLE_52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->fft_idx = PSD_FFT_IDX_A;
cr->fft_idx_m = PSD_FFT_IDX_A_M;
cr->psd_en = PSD_ENABLE_A;
cr->psd_en_m = PSD_ENABLE_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->fft_idx = PSD_FFT_IDX_C;
cr->fft_idx_m = PSD_FFT_IDX_C_M;
cr->psd_en = PSD_ENABLE_C;
cr->psd_en_m = PSD_ENABLE_C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_psd.c
|
C
|
agpl-3.0
| 14,696
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_PSD_H__
#define __HALBB_PSD_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum igi_lv_sel {
IGI_DEFAULT = 0,/*@default value*/
IGI_LEVEL1 = 1,
IGI_LEVEL2 = 2,
IGI_LEVEL3 = 3,
IGI_LEVEL4 = 4
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_psd_cr_info {
u32 psd_en;
u32 psd_en_m;
u32 fft_idx;
u32 fft_idx_m;
};
struct bb_psd_info {
struct bb_psd_cr_info bb_psd_cr_i;
u8 psd_in_progress;
u32 psd_reg;
u32 psd_report_reg;
u8 psd_pwr_common_offset;
u8 hw_avg_time;
u16 sw_avg_time;
u16 fft_point;
u16 fft_point_pre;
u32 rf_0x18_bkp;
u32 rf_0x18_bkp_b;
u8 psd_fc_ch;
u32 psd_bw;
u8 psd_result[128];
u8 i_q_setting;
u8 path;
u8 bw;
u8 input;
u8 noise_k_en;
u8 lna_bkp;
u8 lna_bkp_b;
u8 tia_bkp;
u8 tia_bkp_b;
u8 rxbb_bkp;
u8 rxbb_bkp_b;
u32 igi_pin;
u8 *rpt;
enum band_type psd_band;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_psd_igi_lv(struct bb_info *bb, enum igi_lv_sel igi_lv);
u32 halbb_get_psd_data(struct bb_info *bb, u32 psd_tone_idx, u32 igi_pin);
void halbb_psd_para_setting(struct bb_info *bb, u8 sw_avg_time, u8 hw_avg_time,
u8 i_q_setting, u16 fft_point, u8 path,
u8 psd_input, u8 channel, u8 bw);
bool halbb_psd_alloc_buff(struct bb_info *bb);
void halbb_get_gain_index(struct bb_info *bb);
u8 halbb_psd(struct bb_info *bb, enum igi_lv_sel igi, u16 start_point,
u16 stop_point);
void halbb_psd_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_psd_init(struct bb_info *bb);
void halbb_psd_deinit(struct bb_info *bb);
bool halbb_get_psd_result(struct bb_info *bb, u8 *psd_data, u16 *psd_len);
void halbb_cr_cfg_psd_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_psd.h
|
C
|
agpl-3.0
| 2,887
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_PWR_CTRL_SUPPORT
/* @ Dynamic CCA TH part */
void halbb_set_ccath_macid(struct bb_info *bb, u16 macid, s8 cca_th, bool cca_th_en)
{
u32 ret_v = 0;
u32 mask_ccath = 0xff0000;
u32 mask_en = BIT(26);
struct rtw_phl_stainfo_t *phl_sta_i = NULL;
enum phl_band_idx hw_band;
u32 reg_ofst = REG_PWRMACID_OFST + (macid << 2) + 0xd200;
if (!bb->sta_exist[macid]) {
BB_WARNING("Error Set Pwr Macid for STA not exist!!\n");
return;
}
phl_sta_i = bb->phl_sta_info[macid];
if (!phl_sta_i)
return;
//phl_sta_i = bb->phl_sta_info[macid];
hw_band = phl_sta_i->wrole->hw_band;
/* pwr : S(8,1)*/
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_ccath, cca_th);
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_en, cca_th_en);
BB_DBG(bb, DBG_PWR_CTRL, "halbb_set_ccath_macid = %x %x\n", cca_th, cca_th_en);
if (ret_v != 0)
BB_WARNING("Error Set Pwr Macid for API return fail!!\n");
}
void halbb_ccath_init(struct bb_info *bb)
{
u8 i;
struct bb_dyncca_info *dyncca_i = &bb->bb_dyncca_i;
BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__);
dyncca_i->dyncca_offset = 10; /* clean */
dyncca_i->dyncca_offset_n = 6; /* noisy */
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
dyncca_i->macidcca_i[i].cca_th = 0;
dyncca_i->macidcca_i[i].cca_th_en= 0;
}
}
void halbb_cca_th_per_sta(struct bb_info *bb, u16 macid)
{
bool noisy_state = bb->is_noisy;
struct bb_dyncca_info *dyncca_i = &bb->bb_dyncca_i;
s8 dyn_ccath = 0;
s8 offset = dyncca_i->dyncca_offset;
struct rtw_phl_stainfo_t *sta;
u8 rssi = 0;
#if 0
if (!dyncca_i) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n");
return;
}
#endif
sta = bb->phl_sta_info[macid];
if (!sta) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL PHL STA info\n");
return;
}
if (!is_sta_active(sta))
return;
rssi = sta->hal_sta->rssi_stat.rssi;
if (noisy_state)
offset = dyncca_i->dyncca_offset_n;
dyn_ccath = (s8)rssi - 110 - offset;
}
void halbb_dyncca_th(struct bb_info *bb)
{
struct bb_dyncca_info *dyncca_i = &bb->bb_dyncca_i;
u8 i;
if (!dyncca_i) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n");
return;
}
if (!dyncca_i->dyncca_en)
return;
/* Need to add support ability here */
/*if (!(bb->support_ability & BB_PWR_CTRL))
return;
*/
BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__);
for (i = 0; i < PHL_MAX_STA_NUM; i++)
halbb_cca_th_per_sta( bb, i);
}
/* @ Power Ctrl part */
s8 halbb_get_pwr_macid_idx(struct bb_info *bb, u16 macid, u8 idx)
{
s8 tx_pwr = 0;
struct bb_dtp_info *dtp = &bb->bb_pwr_ctrl_i.dtp_i[macid];
if (!dtp) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer macid = %d\n", macid);
return 0;
}
tx_pwr = dtp->pwr_val[idx];
return tx_pwr; /* S(8,1)*/
}
bool halbb_get_pwr_macid_en_idx(struct bb_info *bb, u16 macid, u8 idx)
{
bool pwr_en = false;
struct bb_dtp_info *dtp = &bb->bb_pwr_ctrl_i.dtp_i[macid];
if (!dtp) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer macid = %d\n", macid);
return 0;
}
pwr_en = dtp->en_pwr[idx];
return pwr_en; /* bool*/
}
void halbb_set_pwr_macid_idx(struct bb_info *bb, u16 macid, s8 pwr, bool pwr_en, u8 idx)
{
u32 ret_v = 0;
u32 mask_pwr = 0xff;
u32 mask_en = BIT(24);
struct rtw_phl_stainfo_t *phl_sta_i = NULL;
enum phl_band_idx hw_band;
u32 reg_ofst = REG_PWRMACID_OFST + (macid << 2) + 0xd200;
if (!bb->sta_exist[macid]) {
BB_WARNING("Error Set Pwr Macid for STA not exist!!\n");
return;
}
phl_sta_i = bb->phl_sta_info[macid];
if (!phl_sta_i)
return;
//phl_sta_i = bb->phl_sta_info[macid];
if (idx == 1) {
mask_pwr = 0x0000ff00;
mask_en = BIT(25);
}
hw_band = phl_sta_i->wrole->hw_band;
/* pwr : S(8,1)*/
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_pwr, pwr);
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, hw_band, reg_ofst, mask_en, pwr_en);
BB_DBG(bb, DBG_PWR_CTRL, "halbb_set_pwr_macid(%d) = %x %x\n", idx, pwr, pwr_en);
if (ret_v != 0)
BB_WARNING("Error Set Pwr Macid for API return fail!!\n");
}
void halbb_pwr_ctrl_en(struct bb_info *bb, bool pwr_ctrl_en)
{
u32 ret_v = 0;
u32 mask_en = BIT(29);
u32 reg_ofst = 0xd20c;
BB_DBG(bb, DBG_PWR_CTRL, "halbb_pwr_ctrl_en() = %x\n", (u32)pwr_ctrl_en);
if(pwr_ctrl_en) {
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 0, reg_ofst, mask_en, 0x1);
if (bb->hal_com->dbcc_en)
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 1, reg_ofst, mask_en, 0x1);
} else {
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 0, reg_ofst, mask_en, 0x0);
if (bb->hal_com->dbcc_en)
ret_v |= rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, 1, reg_ofst, mask_en, 0x0);
}
if (ret_v != 0)
BB_WARNING("Error Enable Power Control for API return fail!!\n");
}
void halbb_pwr_ctrl_th(struct bb_info *bb)
{
bool noisy_state = bb->is_noisy;
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
if (!pwr_ctrl_i) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n");
return;
}
if (noisy_state == 0) {
pwr_ctrl_i->enhance_pwr_th[0] = pwr_ctrl_i->set_pwr_th[0];
pwr_ctrl_i->enhance_pwr_th[1] = pwr_ctrl_i->set_pwr_th[1];
pwr_ctrl_i->enhance_pwr_th[2] = pwr_ctrl_i->set_pwr_th[2];
} else {
pwr_ctrl_i->enhance_pwr_th[0] = pwr_ctrl_i->set_pwr_th[0] + 8;
pwr_ctrl_i->enhance_pwr_th[1] = pwr_ctrl_i->set_pwr_th[1] + 5;
pwr_ctrl_i->enhance_pwr_th[2] = pwr_ctrl_i->set_pwr_th[2];
}
BB_DBG(bb, DBG_PWR_CTRL,
"halbb pwr ctrl pwr_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
pwr_ctrl_i->enhance_pwr_th[0], pwr_ctrl_i->enhance_pwr_th[1],
pwr_ctrl_i->enhance_pwr_th[2]);
}
u8 halbb_pwr_lvl_check(struct bb_info *bb, u8 rssi_in, u8 last_pwr_lvl)
{
u8 i;
u8 th[HALBB_PWR_STATE_NUM];
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
if (!pwr_ctrl_i) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n");
return 0;
}
for (i = 0; i < HALBB_PWR_STATE_NUM; i++)
th[i] = pwr_ctrl_i->set_pwr_th[i];
BB_DBG(bb, DBG_PWR_CTRL,
"Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
th[0], th[1], th[2]);
for (i = 0; i < HALBB_PWR_STATE_NUM; i++) {
if (i >= last_pwr_lvl)
th[i] += DTP_FLOOR_UP_GAP;
}
BB_DBG(bb, DBG_PWR_CTRL,
"Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
th[0], th[1], th[2]);
if (rssi_in >= th[2])
return TX_HP_LV_3;
else if (rssi_in < (th[2] - 3) && rssi_in >= th[1])
return TX_HP_LV_2;
else if (rssi_in < (th[1] - 3) && rssi_in >= th[0])
return TX_HP_LV_1;
else if (rssi_in < (th[0] - 3))
return TX_HP_LV_0;
else
return TX_HP_LV_UNCHANGE;
}
void halbb_set_pwr_ctrl(struct bb_info *bb, u16 macid, u8 pwr_lv)
{
struct rtw_phl_stainfo_t *sta;
s8 pwr = 0;
bool pwr_ctrl_en = false;
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
if (!(bb->support_ability & BB_PWR_CTRL))
return;
sta = bb->phl_sta_info[macid];
if (!sta) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL PHL STA info\n");
return;
}
if (pwr_lv == TX_HP_LV_3) {
pwr_ctrl_en = true;
pwr = pwr_ctrl_i->pwr_lv_dbm[3];
} else if (pwr_lv == TX_HP_LV_2) {
pwr_ctrl_en = true;
pwr = pwr_ctrl_i->pwr_lv_dbm[2];
} else if (pwr_lv == TX_HP_LV_1) {
pwr_ctrl_en = true;
pwr = pwr_ctrl_i->pwr_lv_dbm[1];
} else {
pwr_ctrl_en = false;
pwr = 0;
}
halbb_set_pwr_macid_idx(bb, macid, pwr, pwr_ctrl_en, 0);
/* only use pwr_tbl_0 */
}
void halbb_pwr_ctrl_per_sta(struct bb_info *bb, u16 macid)
{
struct rtw_phl_stainfo_t *sta;
struct bb_dtp_info *dtp = &bb->bb_pwr_ctrl_i.dtp_i[macid];
u8 lst_pwr_lv = 0;
u8 rssi = 0;
sta = bb->phl_sta_info[macid];
if (!sta) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL PHL STA info\n");
return;
}
if (is_sta_active(sta)) {
rssi = (sta->hal_sta->rssi_stat.rssi) >> 1;
lst_pwr_lv = dtp->last_pwr_lvl;
dtp->dyn_tx_pwr_lvl = halbb_pwr_lvl_check(bb, rssi, lst_pwr_lv);
BB_DBG(bb, DBG_PWR_CTRL,
"STA=%d , RSSI: %d , GetPwrLv: %d\n", macid,
rssi, dtp->dyn_tx_pwr_lvl);
if (dtp->dyn_tx_pwr_lvl == TX_HP_LV_UNCHANGE ||
dtp->dyn_tx_pwr_lvl == lst_pwr_lv) {
dtp->dyn_tx_pwr_lvl = lst_pwr_lv;
BB_DBG(bb, DBG_PWR_CTRL,
"DTP_lv not change: ((%d))\n",
dtp->dyn_tx_pwr_lvl);
return;
}
BB_DBG(bb, DBG_PWR_CTRL,
"DTP_lv update: ((%d)) -> ((%d))\n", lst_pwr_lv,
dtp->dyn_tx_pwr_lvl);
dtp->last_pwr_lvl = dtp->dyn_tx_pwr_lvl;
halbb_set_pwr_ctrl(bb, macid, dtp->dyn_tx_pwr_lvl);
}
}
void halbb_pwr_ctrl(struct bb_info *bb)
{
struct bb_pwr_ctrl_info *pwr_ctrl = &bb->bb_pwr_ctrl_i;
u16 i;
if (!(bb->support_ability & BB_PWR_CTRL)) {
/* Disable*/
halbb_pwr_ctrl_en(bb, false);
return;
}
BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__);
/*Enable*/
halbb_pwr_ctrl_en(bb, true);
for (i = 0; i < PHL_MAX_STA_NUM; i++)
halbb_pwr_ctrl_per_sta( bb, i);
BB_DBG(bb, DBG_PWR_CTRL, "pwr = %d\n", pwr_ctrl->pwr);
}
void halbb_pwr_ctrl_para_init(struct bb_info *bb)
{
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
pwr_ctrl_i->set_pwr_th[0] = TX_PWR_TH_LVL1;
pwr_ctrl_i->set_pwr_th[1] = TX_PWR_TH_LVL2;
pwr_ctrl_i->set_pwr_th[2] = TX_PWR_TH_LVL3;
pwr_ctrl_i->pwr_lv_dbm[0] = TX_PWR_LVL1;
pwr_ctrl_i->pwr_lv_dbm[1] = TX_PWR_LVL2;
pwr_ctrl_i->pwr_lv_dbm[2] = TX_PWR_LVL3;
}
void halbb_pwr_ctrl_txpwr_cfg(struct bb_info *bb, u8 pwr_lv1, u8 pwr_lv2, u8 pwr_lv3)
{
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
pwr_ctrl_i->pwr_lv_dbm[0] = pwr_lv1;
pwr_ctrl_i->pwr_lv_dbm[1] = pwr_lv2;
pwr_ctrl_i->pwr_lv_dbm[2] = pwr_lv3;
}
void halbb_pwr_ctrl_th_cfg(struct bb_info *bb, u8 th_lv1, u8 th_lv2, u8 th_lv3)
{
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
pwr_ctrl_i->set_pwr_th[0] = th_lv1;
pwr_ctrl_i->set_pwr_th[1] = th_lv2;
pwr_ctrl_i->set_pwr_th[2] = th_lv3;
}
void halbb_pwr_ctrl_init(struct bb_info *bb)
{
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
u8 i = 0;
if (!pwr_ctrl_i) {
BB_DBG(bb, DBG_PWR_CTRL, "NULL pointer!\n");
return;
}
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
pwr_ctrl_i->dtp_i[i].last_pwr_lvl= TX_HP_LV_0;
pwr_ctrl_i->dtp_i[i].dyn_tx_pwr_lvl= TX_HP_LV_0;
}
halbb_pwr_ctrl_para_init(bb);
for (i = 0; i < HALBB_PWR_STATE_NUM; i++)
pwr_ctrl_i->enhance_pwr_th[i] = 0xff;
BB_DBG(bb, DBG_PWR_CTRL, "pwr = %d\n", pwr_ctrl_i->pwr);
}
void halbb_pwr_ctrl_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char help[] = "-h";
u32 val[10] = {0};
u8 i = 0;
struct bb_pwr_ctrl_info *pwr_ctrl_i = &bb->bb_pwr_ctrl_i;
if (_os_strcmp(input[1], help) == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{Use Org TH and PWR} [pwr_ctrl] [0]\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{Modify LV1(H)~LV3(L) Power} [pwr_ctrl] [1] [LV1] [LV2] [LV3]\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{Modify LV1(H)~LV3(L) TH} [pwr_ctrl] [2] [LV1] [LV2] [LV3]\n");
return;
}
for (i = 0; i < 8; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
switch (val[0]) {
case 0:
halbb_pwr_ctrl_para_init(bb);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Reset Parameters\n");
break;
case 1:
halbb_pwr_ctrl_txpwr_cfg(bb, (u8)val[1], (u8)val[2], (u8)val[3]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"PWRCTRL TxPWR for each LV = {%d, %d, %d}\n",
pwr_ctrl_i->pwr_lv_dbm[0], pwr_ctrl_i->pwr_lv_dbm[1],
pwr_ctrl_i->pwr_lv_dbm[2]);
break;
case 2:
halbb_pwr_ctrl_th_cfg(bb, (u8)val[1], (u8)val[2], (u8)val[3]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"PWRCTRL TH for each LV = {%d, %d, %d}\n",
pwr_ctrl_i->set_pwr_th[0], pwr_ctrl_i->set_pwr_th[1],
pwr_ctrl_i->set_pwr_th[2]);
break;
default:
break;
}
}
#endif
bool halbb_set_pwr_ul_tb_ofst(struct bb_info *bb, s16 pw_ofst,
enum phl_phy_idx phy_idx)
{
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
halbb_set_pwr_ul_tb_ofst_8852a_2(bb, pw_ofst, phy_idx);
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
halbb_set_pwr_ul_tb_ofst_8852b(bb, pw_ofst, phy_idx);
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
halbb_set_pwr_ul_tb_ofst_8852c(bb, (s8)pw_ofst, phy_idx);
break;
#endif
default:
break;
}
return true;
}
void halbb_macid_ctrl_init(struct bb_info *bb)
{
u8 i = 0;
u32 reg_ofst = 0;
u32 ret_v = 0;
BB_DBG(bb, DBG_PWR_CTRL, "[%s]\n", __func__);
if (bb->hal_com == NULL) {
BB_WARNING("hal_com is not allocated in halbb_macid_ctrl_init!!\n");
return;
}
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
reg_ofst = REG_PWRMACID_OFST + (i<<2) + 0xd200;
ret_v = rtw_hal_mac_set_pwr_reg( bb->hal_com, 0, reg_ofst, 0);
if (bb->hal_com->dbcc_en)
ret_v = rtw_hal_mac_set_pwr_reg( bb->hal_com, 1, reg_ofst, 0);
}
}
void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u32 tpu_array_type1[] = {0xD248, 0x07763333,
0xD220, 0x01ebf004,
0xD240, 0x0002f8ff};
u32 *tpu_array = NULL;
u8 cr_size = 0;
u8 i = 0;
enum phl_band_idx band;
band = (phy_idx == HW_PHY_0) ? HW_BAND_0 : HW_BAND_1;
switch (bb->ic_type) {
#if defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT)
case BB_RTL8852A:
case BB_RTL8852B:
tpu_array = (u32 *)tpu_array_type1;
cr_size = sizeof(tpu_array_type1)/sizeof(u32);
break;
#endif
default:
break;
}
BB_DBG(bb, DBG_INIT, "[%s] size=%d\n", __func__, cr_size >> 1);
if (!tpu_array) {
BB_WARNING("[%s]\n", __func__);
return;
}
for (i = 0; i < cr_size; i+=2) {
BB_DBG(bb, DBG_INIT, "0x%x = 0x%x\n", tpu_array[i], tpu_array[i+1]);
rtw_hal_mac_set_pwr_reg(bb->hal_com, band, tpu_array[i], tpu_array[i+1]);
}
}
void halbb_pwr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_tpu_info *tpu = &bb->hal_com->band[bb->bb_phy_idx].rtw_tpu_i;
struct rtw_tpu_pwr_by_rate_info *by_rate = &tpu->rtw_tpu_pwr_by_rate_i;
struct rtw_tpu_pwr_imt_info *lmt = &tpu->rtw_tpu_pwr_imt_i;
bool rpt_tmp;
u16 size_tmp = 0;
u32 val[10] = {0};
u16 i = 0, j = 0;
u8 rate_idx = 0, path = 0;
s8 *tmp_s8, val_s8;
if (_os_strcmp(input[1], "-h") == 0) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dbg_en {en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"show\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set all {s(7,1) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set lgcy {idx} {s(7,1) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"set mcs {path:0~3} {idx} {s(7,1) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"ofst bw {all:255, 0~4: 80_80/160/80/40/20} {0:+, 1:-} {u(3,1) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"ofst mode {all:255 0~4: HE/VHT/HT/Legacy/CCK} {0:+, 1:-} {u(3,1) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"ref {cck, ofdm} {s(9,2) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"ref ofst {s(8,3) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"cw {0:rf_0db_cw(39), 1:tssi_16dBm_cw(300)} {val}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"lmt en {en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"lmt {all, ru_all} {s(7,1) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tb_ofst {s(5,0) dB}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tx_shap {ch} {shap_idx} {is_ofdm}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tpu 0\n");
return;
}
if (_os_strcmp(input[1], "tpu") == 0) {
halbb_set_tx_pow_ref(bb, bb->bb_phy_idx);
rtw_hal_mac_write_pwr_by_rate_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
rtw_hal_mac_write_pwr_limit_rua_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
rtw_hal_mac_write_pwr_limit_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
rtw_hal_mac_write_pwr_ofst_mode(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
rtw_hal_mac_write_pwr_ofst_bw(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set all TPU component\n");
} else if (_os_strcmp(input[1], "dbg_en") == 0) {
HALBB_SCAN(input[2], DCMD_HEX, &val[0]);
rtw_hal_mac_set_tpu_mode(bb->hal_com, (enum rtw_tpu_op_mode)val[0], bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"dbg_en=%d, Locking driver set TPU = %d\n", val[0], tpu->normal_mode_lock_en);
} else if (_os_strcmp(input[1], "show") == 0) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"================\n\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[PW Ref]\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s {%d}\n", "[base_cw_0db]", tpu->base_cw_0db);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s {%s dB}\n", "[ref_ofst]",
halbb_print_sign_frac_digit2(bb, tpu->ofst_int, 8, 3));
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s {%s dBm} pw_cw=0x%03x\n", "[CCK]",
halbb_print_sign_frac_digit2(bb, tpu->ref_pow_cck, 16, 2),
tpu->ref_pow_cck_cw);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s {%s dBm} pw_cw=0x%03x\n", "[OFDM]",
halbb_print_sign_frac_digit2(bb, tpu->ref_pow_ofdm, 16, 2),
tpu->ref_pow_ofdm_cw);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"================\n\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[PW Offset] (s41)\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-20s {%02d, %02d, %02d, %02d, %02d}\n", "[AX/AC/N/G/B]",
tpu->pwr_ofst_mode[0], tpu->pwr_ofst_mode[1],
tpu->pwr_ofst_mode[2], tpu->pwr_ofst_mode[3],
tpu->pwr_ofst_mode[4]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-20s {%02d, %02d, %02d, %02d, %02d}\n", "[80_80/160/80/40/20]",
tpu->pwr_ofst_bw[0], tpu->pwr_ofst_bw[1],
tpu->pwr_ofst_bw[2], tpu->pwr_ofst_bw[3],
tpu->pwr_ofst_bw[4]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"================\n\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Pwr By Rate] (s71)\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s {%02d, %02d, %02d, %02d}\n", "[CCK]",
by_rate->pwr_by_rate_lgcy[0], by_rate->pwr_by_rate_lgcy[1],
by_rate->pwr_by_rate_lgcy[2], by_rate->pwr_by_rate_lgcy[3]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s {%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n","[Lgcy]",
by_rate->pwr_by_rate_lgcy[4], by_rate->pwr_by_rate_lgcy[5],
by_rate->pwr_by_rate_lgcy[6], by_rate->pwr_by_rate_lgcy[7],
by_rate->pwr_by_rate_lgcy[8], by_rate->pwr_by_rate_lgcy[9],
by_rate->pwr_by_rate_lgcy[10], by_rate->pwr_by_rate_lgcy[11]);
for (i = 0; i < HAL_MAX_PATH; i++) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%d]%-7s {%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n",
i, "[OFDM]",
by_rate->pwr_by_rate[i][0], by_rate->pwr_by_rate[i][1],
by_rate->pwr_by_rate[i][2], by_rate->pwr_by_rate[i][3],
by_rate->pwr_by_rate[i][4], by_rate->pwr_by_rate[i][5],
by_rate->pwr_by_rate[i][6], by_rate->pwr_by_rate[i][7],
by_rate->pwr_by_rate[i][8], by_rate->pwr_by_rate[i][9],
by_rate->pwr_by_rate[i][10], by_rate->pwr_by_rate[i][11]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%d]%-7s {%02d, %02d, %02d, %02d}\n",
i,"[DCM]",
by_rate->pwr_by_rate[i][12], by_rate->pwr_by_rate[i][13],
by_rate->pwr_by_rate[i][14], by_rate->pwr_by_rate[i][15]);
}
for (j = 0; j < TPU_SIZE_BF; j++) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"================\n\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Pwr Lmt][%sBF]\n", (j == 0) ? "non-" : "");
for (i = 0; i < HAL_MAX_PATH; i++) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d}\n", "[CCK-20M]",
i, lmt->pwr_lmt_cck_20m[i][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d}\n", "[CCK-40M]",
i, lmt->pwr_lmt_cck_40m[i][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d}\n", "[Lgcy-20M]",
i, lmt->pwr_lmt_lgcy_20m[i][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n", "[OFDM-20M]",
i, lmt->pwr_lmt_20m[i][0][j], lmt->pwr_lmt_20m[i][1][j],
lmt->pwr_lmt_20m[i][2][j], lmt->pwr_lmt_20m[i][3][j],
lmt->pwr_lmt_20m[i][4][j], lmt->pwr_lmt_20m[i][5][j],
lmt->pwr_lmt_20m[i][6][j], lmt->pwr_lmt_20m[i][7][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d, %02d, %02d, %02d}\n", "[OFDM-40M]",
i, lmt->pwr_lmt_40m[i][0][j], lmt->pwr_lmt_40m[i][1][j],
lmt->pwr_lmt_40m[i][2][j], lmt->pwr_lmt_40m[i][3][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d, %02d}\n", "[OFDM-80M]",
i, lmt->pwr_lmt_80m[i][0][j], lmt->pwr_lmt_80m[i][1][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s[%d]{%02d}\n", "[OFDM-160M]",
i, lmt->pwr_lmt_160m[i][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d}\n", "[40m_0p5]",
i, lmt->pwr_lmt_40m_0p5[i][j]);
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d}\n", "[40m_2p5]",
i, lmt->pwr_lmt_40m_2p5[i][j]);
}
}
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"================\n\n");
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Pwr Lmt RUA]\n");
for (j = 0; j < TPU_SIZE_RUA; j++) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[RU-%3d]\n", (j == 0) ? 26 : ((j == 1) ? 52 : 106));
for (i = 0; i < HAL_MAX_PATH; i++) {
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s [%d]{%02d, %02d, %02d, %02d, %02d, %02d, %02d, %02d}\n", "[OFDM-20M]",
i, tpu->pwr_lmt_ru[i][j][0], tpu->pwr_lmt_ru[i][j][1],
tpu->pwr_lmt_ru[i][j][2], tpu->pwr_lmt_ru[i][j][3],
tpu->pwr_lmt_ru[i][j][4], tpu->pwr_lmt_ru[i][j][5],
tpu->pwr_lmt_ru[i][j][6], tpu->pwr_lmt_ru[i][j][7]);
}
}
BB_DBG_VAST(*_out_len, *_used, output + *_used, *_out_len - *_used,
"================\n\n");
} else if (_os_strcmp(input[1], "cw") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
if (val[0] == 0) {
tpu->base_cw_0db = (u8)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"rf_cw_0dbm=%d\n", tpu->base_cw_0db);
} else if (val[0] == 1) {
tpu->tssi_16dBm_cw = (u16)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"tssi_16dBm_cw=%d\n", tpu->tssi_16dBm_cw);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
halbb_set_tx_pow_ref(bb, bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "ofst") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]);
if (val[1] == 0) {
if (val[2] > 7) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Set Err] max = +3.5 dB\n");
return;
}
val_s8 = (s8)val[2];
} else {
if (val[2] > 8) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Set Err] max = -4 dB\n");
return;
}
val_s8 = (s8)val[2] * -1;
}
if (_os_strcmp(input[2], "bw") == 0) {
if (val[0] == 255) {
for (i = 0; i < TPU_SIZE_BW; i++)
tpu->pwr_ofst_bw[i] = val_s8;
} else if (val[0] >= TPU_SIZE_BW) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
} else {
tpu->pwr_ofst_bw[val[0]] = val_s8;
}
rtw_hal_mac_write_pwr_ofst_bw(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
} else if (_os_strcmp(input[2], "mode") == 0) {
if (val[0] == 255) {
for (i = 0; i < TPU_SIZE_MODE; i++)
tpu->pwr_ofst_mode[i] = val_s8;
} else if (val[0] >= TPU_SIZE_MODE) {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
} else {
tpu->pwr_ofst_mode[val[0]] = val_s8;
}
rtw_hal_mac_write_pwr_ofst_mode(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[%s]pw ofst[%d]=(%s%d.%d)dB\n",
(_os_strcmp(input[2], "bw") == 0) ? "BW" : "MODE",
val[0], (val[1] == 0) ? "+" : "-",
val[2] >> 1, (val[2] & 0x1) * 5);
} else if (_os_strcmp(input[1], "ref") == 0) {
if (_os_strcmp(input[2], "ofst") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"ref_ofst=(%s)dB\n",
halbb_print_sign_frac_digit2(bb, tpu->ofst_int, 8, 3));
} else {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
if (_os_strcmp(input[2], "ofdm") == 0) {
tpu->ref_pow_ofdm = (s16)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s ref_pw={%s dBm} cw=0x%09x\n", "[OFDM]",
halbb_print_sign_frac_digit2(bb, tpu->ref_pow_ofdm, 16, 2),
tpu->ref_pow_ofdm_cw);
} else if (_os_strcmp(input[2], "cck") == 0) {
tpu->ref_pow_cck = (s16)val[0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"%-10s ref_pw={%s dBm} cw=0x%09x\n", "[CCK]",
halbb_print_sign_frac_digit2(bb, tpu->ref_pow_cck, 16, 2),
tpu->ref_pow_cck_cw);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
//halbb_print_sign_frac_digit2(bb, val[0], 32, 2);
//BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, "ref_pw = (%s)dBm\n", bb->dbg_buf);
}
halbb_set_tx_pow_ref(bb, bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "set") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[5], DCMD_DECIMAL, &val[2]);
if (_os_strcmp(input[2], "lgcy") == 0) {
rate_idx = (u8)val[0];
if (rate_idx > TPU_SIZE_PWR_TAB_lGCY)
return;
tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate_lgcy[rate_idx] = (s8)val[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[TX Pw] lgcy[%d] = (%d.%d)dBm\n", rate_idx, val[1]>>1, (val[1] & 1)*5);
} else if (_os_strcmp(input[2], "mcs") == 0) {
path = (u8)val[0];
if (path > HAL_MAX_PATH)
return;
rate_idx = (u8)val[1];
if (rate_idx > TPU_SIZE_PWR_TAB)
return;
tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate[path][rate_idx] = (s8)val[2];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[TX Pw] Path[%d] MCS[%d] = (%d.%d)dBm\n", path, rate_idx, val[2]>>1, (val[2] & 1)*5);
} else if (_os_strcmp(input[2], "all") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
for (i = 0; i < TPU_SIZE_PWR_TAB_lGCY; i++)
tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate_lgcy[i] = (s8)val[0];
for (i = 0; i < HAL_MAX_PATH; i++) {
for (j = 0; j < TPU_SIZE_PWR_TAB; j++)
tpu->rtw_tpu_pwr_by_rate_i.pwr_by_rate[i][j] = (s8)val[0];
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[TX Pw] All rate = (%d.%d)dBm\n", val[0]>>1, (val[0] & 1)*5);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
rtw_hal_mac_write_pwr_by_rate_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
} else if (_os_strcmp(input[1], "lmt") == 0) {
if (_os_strcmp(input[2], "en") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
tpu->pwr_lmt_en = (bool)val[0];
rtw_hal_mac_write_pwr_limit_en(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"pwr_lmt_en = %d\n", tpu->pwr_lmt_en);
} else if (_os_strcmp(input[2], "all") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
size_tmp = sizeof(struct rtw_tpu_pwr_imt_info) / sizeof(s8);
tmp_s8 = &lmt->pwr_lmt_cck_20m[0][0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"pwr_lmt_size = %d\n", size_tmp);
for (i = 0; i < size_tmp; i++) {
*tmp_s8 = (u8)val[0];
tmp_s8++;
}
rtw_hal_mac_write_pwr_limit_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set all Pwr Lmt = (%d.%d)dBm\n", val[0]>>1, (val[0] & 1)*5);
} else if (_os_strcmp(input[2], "ru_all") == 0) {
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[0]);
size_tmp = HAL_MAX_PATH * TPU_SIZE_RUA * TPU_SIZE_BW20_SC;
tmp_s8 = &tpu->pwr_lmt_ru[0][0][0];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"pwr_lmt_size_ru = %d\n", size_tmp);
for (i = 0; i < size_tmp; i++) {
*tmp_s8 = (s8)val[0];
tmp_s8++;
}
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set all RUA Pwr Lmt = (%d.%d)dBm\n", val[0]>>1, (val[0] & 1)*5);
rtw_hal_mac_write_pwr_limit_rua_reg(bb->hal_com, (enum phl_band_idx)bb->bb_phy_idx);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
return;
}
} else if (_os_strcmp(input[1], "tb_ofst") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
rpt_tmp = halbb_set_pwr_ul_tb_ofst(bb, (s16)val[0], bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[ULTB Ofst]Set succcess=%d, en = %d, pw_ofst=%d\n",
rpt_tmp, val[0], (s16)val[1]);
} else if (_os_strcmp(input[1], "tx_shap") == 0) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &val[0]);
HALBB_SCAN(input[3], DCMD_DECIMAL, &val[1]);
HALBB_SCAN(input[4], DCMD_DECIMAL, &val[2]);
tpu->tx_ptrn_shap_idx = (u8)val[1];
halbb_set_tx_pow_pattern_shap(bb, (u8)val[0], (bool)val[2], bb->bb_phy_idx);
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[Tx Shap] ch=%d, shap_idx=%d\n", val[0], tpu->tx_ptrn_shap_idx);
} else {
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Set Err\n");
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_pwr_ctrl.c
|
C
|
agpl-3.0
| 33,295
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_PWR_CTRL_H__
#define __HALBB_PWR_CTRL_H__
/*@--------------------------[Define] ---------------------------------------*/
#define REG_PWRMACID_OFST 0x0016c
#define HALBB_PWR_STATE_NUM 3
#define DTP_FLOOR_UP_GAP 3
#define TX_HP_LV_0 0
#define TX_HP_LV_1 1
#define TX_HP_LV_2 2
#define TX_HP_LV_3 3
#define TX_HP_LV_UNCHANGE 4
/*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
#define TX_PWR_TH_LVL3 80
#define TX_PWR_TH_LVL2 63
#define TX_PWR_TH_LVL1 55
/*#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define TX_PWR_TH_LVL3 90
#define TX_PWR_TH_LVL2 85
#define TX_PWR_TH_LVL1 80
#endif*/
#define TX_PWR_LVL3 6 /*3dBm*/
#define TX_PWR_LVL2 12 /*6dBm*/
#define TX_PWR_LVL1 20 /*10dBm*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/* @ Dynamic CCA TH part */
struct bb_macidcca_info {
bool cca_th_en;
s8 cca_th;
};
struct bb_dyncca_info {
/* [] */
bool dyncca_en;
u8 dyncca_offset;
u8 dyncca_offset_n;
/**/
struct bb_macidcca_info macidcca_i[PHL_MAX_STA_NUM];
};
/* @ Power Ctrl part */
struct bb_dtp_info {
/*u8 dyn_tx_power;
u8 last_tx_power;*/
u8 dyn_tx_pwr_lvl:4;
u8 last_pwr_lvl:4;
s8 pwr_val[2]; /* S(8,1) */
bool en_pwr[2];
};
struct bb_pwr_ctrl_info {
u8 pwr;
/* [] */
u8 enhance_pwr_th[HALBB_PWR_STATE_NUM];
u8 set_pwr_th[HALBB_PWR_STATE_NUM];
u8 pwr_lv_dbm[HALBB_PWR_STATE_NUM];
/**/
struct bb_dtp_info dtp_i[PHL_MAX_STA_NUM];
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_PWR_CTRL_SUPPORT
void halbb_pwr_ctrl(struct bb_info *bb);
void halbb_pwr_ctrl_init(struct bb_info *bb);
void halbb_set_pwr_macid_idx(struct bb_info *bb, u16 macid, s8 pwr, bool pwr_en, u8 idx);
#endif
void halbb_macid_ctrl_init(struct bb_info *bb);
void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_pwr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_pwr_ctrl.h
|
C
|
agpl-3.0
| 2,992
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_PWR_CTRL_EX_H__
#define __HALBB_PWR_CTRL_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
bool halbb_set_pwr_ul_tb_ofst(struct bb_info *bb, s16 pw_ofst,
enum phl_phy_idx phy_idx);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_pwr_ctrl_ex.h
|
C
|
agpl-3.0
| 1,219
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_RA_SUPPORT
const u16 bb_phy_rate_table[] = {
/*CCK*/
1, 2, 5, 11,
/*OFDM*/
6, 9, 12, 18, 24, 36, 48, 54,
/*HT/VHT-1ss LGI*/
6, 13, 19, 26, 39, 52, 58, 65, 78, 87, 98, 108,
/*HT/VHT-2ss LGI*/
13, 26, 39, 52, 78, 104, 117, 130, 156, 173, 195, 217,
/*HT/VHT-3ss LGI*/
19, 39, 58, 78, 117, 156, 175, 195, 234, 260, 293, 325,
/*HT/VHT-4ss LGI*/
26, 52, 78, 104, 156, 208, 234, 260, 312, 347, 390, 433,
}; /*HE[3.2] = VHT[LGI] * 1.125*/
bool halbb_is_he_rate(struct bb_info *bb, u16 rate)
{
return ((((rate & 0x1ff) >= BB_HE_1SS_MCS0) &&
((rate & 0x1ff) <= BB_HE_1SS_MCS(11))) ||
(((rate & 0x1ff) >= BB_HE_2SS_MCS0) &&
((rate & 0x1ff) <= BB_HE_2SS_MCS(11))) ||
(((rate & 0x1ff) >= BB_HE_3SS_MCS0) &&
((rate & 0x1ff) <= BB_HE_3SS_MCS(11))) ||
(((rate & 0x1ff) >= BB_HE_4SS_MCS0) &&
((rate & 0x1ff) <= BB_HE_4SS_MCS(11)))) ? true : false;
}
bool halbb_is_vht_rate(struct bb_info *bb, u16 rate)
{
return ((((rate & 0x1ff) >= BB_VHT_1SS_MCS0) &&
((rate & 0x1ff) <= BB_VHT_1SS_MCS(9))) ||
(((rate & 0x1ff) >= BB_VHT_2SS_MCS0) &&
((rate & 0x1ff) <= BB_VHT_2SS_MCS(9))) ||
(((rate & 0x1ff) >= BB_VHT_3SS_MCS0) &&
((rate & 0x1ff) <= BB_VHT_3SS_MCS(9))) ||
(((rate & 0x1ff) >= BB_VHT_4SS_MCS0) &&
((rate & 0x1ff) <= BB_VHT_4SS_MCS(9)))) ? true : false;
}
bool halbb_is_ht_rate(struct bb_info *bb, u16 rate)
{
return (((rate & 0x1ff) >= BB_HT_MCS0) &&
((rate & 0x1ff) <= BB_HT_MCS(31))) ? true : false;
}
bool halbb_is_ofdm_rate(struct bb_info *bb, u16 rate)
{
return (((rate & 0x1ff) >= BB_06M) &&
((rate & 0x1ff) <= BB_54M)) ? true : false;
}
bool halbb_is_cck_rate(struct bb_info *bb, u16 rate)
{
return ((rate & 0x1ff) <= BB_11M) ? true : false;
}
u8 halbb_legacy_rate_2_spec_rate(struct bb_info *bb, u16 rate)
{
u8 rate_idx = 0x0;
u8 legacy_spec_rate_t[8] = {BB_SPEC_RATE_6M, BB_SPEC_RATE_9M,
BB_SPEC_RATE_12M, BB_SPEC_RATE_18M,
BB_SPEC_RATE_24M, BB_SPEC_RATE_36M,
BB_SPEC_RATE_48M, BB_SPEC_RATE_54M};
rate_idx = rate - BB_06M;
return legacy_spec_rate_t[rate_idx];
}
u8 halbb_mgnt_2_hw_rate(u8 rate)
{
u8 ret = 0;
/*exclude BSS basic bit*/
rate &= 0x7f;
/*a/b/g mode only, there is no requirement for n/ac/ax mode*/
if (rate > 108)
return ret;
/*unit:0.5Mbps*/
switch (rate) {
case 2:
ret = BB_01M;
break;
case 4:
ret = BB_02M;
break;
case 11:
ret = BB_05M;
break;
case 22:
ret = BB_11M;
break;
case 12:
ret = BB_06M;
break;
case 18:
ret = BB_09M;
break;
case 24:
ret = BB_12M;
break;
case 36:
ret = BB_18M;
break;
case 48:
ret = BB_24M;
break;
case 72:
ret = BB_36M;
break;
case 96:
ret = BB_48M;
break;
case 108:
ret = BB_54M;
break;
default:
break;
}
return ret;
}
u8 halbb_mcs_ss_to_fw_rate_idx(u8 mode, u8 mcs, u8 ss)
{
u8 fw_rate_idx = 0;
if (mode == 3) {
fw_rate_idx = RATE_HE1SS_MCS0 + (ss - 1) * 12; // MAX HE MCS is MCS11 (Totally, 12 MCS index)
} else if (mode == 2) {
fw_rate_idx = RATE_VHT1SS_MCS0 + (ss - 1) * 10; // MAX VHT MCS is MCS9 (Totally, 10 MCS index)
} else if (mode == 1) { // HT
fw_rate_idx = RATE_HT_MCS0 + (ss - 1) * 8;
} else {
fw_rate_idx = 0;
}
return fw_rate_idx;
}
void halbb_rate_idx_parsor(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, struct bb_rate_info *ra_i)
{
ra_i->rate_idx_all = rate_idx | (((u16)gi_ltf & 0xf) << 12);
ra_i->rate_idx = rate_idx;
ra_i->gi_ltf = gi_ltf;
ra_i->mode = (enum bb_mode_type)((rate_idx & 0x180) >> 7);
if (ra_i->mode == BB_LEGACY_MODE) {
ra_i->ss = 1;
ra_i->idx = rate_idx & 0x1f;
} else if (ra_i->mode == BB_HT_MODE) {
ra_i->ss = (ra_i->idx >> 3) + 1;
ra_i->idx = rate_idx & 0x1f;
} else {
ra_i->ss = ((rate_idx & 0x70) >> 4) + 1;
ra_i->idx = rate_idx & 0xf;
}
/* Transfer to fw used rate_idx*/
if (ra_i->mode == BB_LEGACY_MODE) {
ra_i->fw_rate_idx = ra_i->idx;
return;
}
ra_i->fw_rate_idx = halbb_mcs_ss_to_fw_rate_idx(ra_i->mode, ra_i->idx, ra_i->ss);
return;
}
u8 halbb_rate_2_rate_digit(struct bb_info *bb, u16 rate)
{
u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
u8 rate_digit = 0;
if (rate >= BB_HE_8SS_MCS0)
rate_digit = (rate - BB_HE_8SS_MCS0);
else if (rate >= BB_HE_7SS_MCS0)
rate_digit = (rate - BB_HE_7SS_MCS0);
else if (rate >= BB_HE_6SS_MCS0)
rate_digit = (rate - BB_HE_6SS_MCS0);
else if (rate >= BB_HE_5SS_MCS0)
rate_digit = (rate - BB_HE_5SS_MCS0);
else if (rate >= BB_HE_4SS_MCS0)
rate_digit = (rate - BB_HE_4SS_MCS0);
else if (rate >= BB_HE_3SS_MCS0)
rate_digit = (rate - BB_HE_3SS_MCS0);
else if (rate >= BB_HE_2SS_MCS0)
rate_digit = (rate - BB_HE_2SS_MCS0);
else if (rate >= BB_HE_1SS_MCS0)
rate_digit = (rate - BB_HE_1SS_MCS0);
else if (rate >= BB_VHT_8SS_MCS0)
rate_digit = (rate - BB_VHT_8SS_MCS0);
else if (rate >= BB_VHT_7SS_MCS0)
rate_digit = (rate - BB_VHT_7SS_MCS0);
else if (rate >= BB_VHT_6SS_MCS0)
rate_digit = (rate - BB_VHT_6SS_MCS0);
else if (rate >= BB_VHT_5SS_MCS0)
rate_digit = (rate - BB_VHT_5SS_MCS0);
else if (rate >= BB_VHT_4SS_MCS0)
rate_digit = (rate - BB_VHT_4SS_MCS0);
else if (rate >= BB_VHT_3SS_MCS0)
rate_digit = (rate - BB_VHT_3SS_MCS0);
else if (rate >= BB_VHT_2SS_MCS0)
rate_digit = (rate - BB_VHT_2SS_MCS0);
else if (rate >= BB_VHT_1SS_MCS0)
rate_digit = (rate - BB_VHT_1SS_MCS0);
else if (rate >= BB_HT_MCS0)
rate_digit = (rate - BB_HT_MCS0);
else if (rate <= BB_54M)
rate_digit = legacy_table[rate];
return rate_digit;
}
/*u8 halbb_get_rx_stream_num(struct bb_info *bb, enum rf_type type)
{
u8 rx_num = 1;
if (type == RF_1T1R)
rx_num = 1;
else if (type == RF_2T2R || type == RF_1T2R)
rx_num = 2;
else if (type == RF_3T3R || type == RF_2T3R)
rx_num = 3;
else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)
rx_num = 4;
else
BB_WARNING("%s\n", __func__);
return rx_num;
}*/
u8 halbb_rate_type_2_num_ss(struct bb_info *bb, enum halbb_rate_type type)
{
u8 num_ss = 1;
switch (type) {
case BB_CCK:
case BB_OFDM:
case BB_1SS:
num_ss = 1;
break;
case BB_2SS:
num_ss = 2;
break;
case BB_3SS:
num_ss = 3;
break;
case BB_4SS:
num_ss = 4;
break;
default:
break;
}
return num_ss;
}
u8 halbb_rate_to_num_ss(struct bb_info *bb, u16 rate)
{
u8 num_ss = 1;
if (rate <= BB_54M)
num_ss = 1;
else if (rate <= BB_HT_MCS(31))
num_ss = ((rate - BB_HT_MCS0) >> 3) + 1;
else if (rate <= BB_VHT_1SS_MCS(9))
num_ss = 1;
else if (rate <= BB_VHT_2SS_MCS(9))
num_ss = 2;
else if (rate <= BB_VHT_3SS_MCS(9))
num_ss = 3;
else if (rate <= BB_VHT_4SS_MCS(9))
num_ss = 4;
else if (rate <= BB_VHT_5SS_MCS(9))
num_ss = 5;
else if (rate <= BB_VHT_6SS_MCS(9))
num_ss = 6;
else if (rate <= BB_VHT_7SS_MCS(9))
num_ss = 7;
else if (rate <= BB_VHT_8SS_MCS(9))
num_ss = 8;
else if (rate <= BB_HE_1SS_MCS(11))
num_ss = 1;
else if (rate <= BB_HE_2SS_MCS(11))
num_ss = 2;
else if (rate <= BB_HE_3SS_MCS(11))
num_ss = 3;
else if (rate <= BB_HE_4SS_MCS(11))
num_ss = 4;
else if (rate <= BB_HE_5SS_MCS(11))
num_ss = 5;
else if (rate <= BB_HE_6SS_MCS(11))
num_ss = 6;
else if (rate <= BB_HE_7SS_MCS(11))
num_ss = 7;
else if (rate <= BB_HE_8SS_MCS(11))
num_ss = 8;
return num_ss;
}
void halbb_print_rate_2_buff(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, char *buf, u16 buf_size)
{
struct bb_rate_info rate;
char *ss = NULL;
char *mode = NULL;
char *gi = NULL;
halbb_rate_idx_parsor(bb, rate_idx, gi_ltf, &rate);
if (rate.mode == BB_HE_MODE)
mode = "HE ";
else if (rate.mode == BB_VHT_MODE)
mode = "VHT ";
else if (rate.mode == BB_HT_MODE)
mode = "HT";
else
mode = "";
if (rate.ss == 4)
ss = "4";
else if (rate.ss == 3)
ss = "3";
else if (rate.ss == 2)
ss = "2";
else
ss = "1";
if (rate.mode == BB_HE_MODE) {
if (rate.gi_ltf == RTW_GILTF_LGI_4XHE32)
gi = "[4X32]";
else if (rate.gi_ltf == RTW_GILTF_SGI_4XHE08)
gi = "[4X08]";
else if (rate.gi_ltf == RTW_GILTF_2XHE16)
gi = "[2X16]";
else if (rate.gi_ltf == RTW_GILTF_2XHE08)
gi = "[2X08]";
else if (rate.gi_ltf == RTW_GILTF_1XHE16)
gi = "[1X16]";
else
gi = "[1X08]";
} else if (rate.mode >= BB_HT_MODE) {
if (rate.gi_ltf == RTW_GILTF_SGI_4XHE08)
gi = "[sgi]";
else
gi = "";
} else {
gi = "";
}
/* BB_SNPRINTF wait driver porting */
_os_snprintf(buf, buf_size, "(%s%s%s%s%d%s%s)",
mode,
(rate.mode >= BB_VHT_MODE) ? ss : "",
(rate.mode >= BB_VHT_MODE) ? "-ss " : "",
(rate.rate_idx >= BB_HT_MCS0) ? "MCS" : "",
(rate.rate_idx >= BB_HT_MCS0) ? rate.idx : bb_phy_rate_table[rate.idx],
gi,
(rate.rate_idx < BB_HT_MCS0) ? "M" : "");
}
enum bb_qam_type halbb_get_qam_order(struct bb_info *bb, u16 rate_idx)
{
u16 tmp_idx = rate_idx;
enum bb_qam_type qam_order = BB_QAM_BPSK;
enum bb_qam_type qam[10] = {BB_QAM_BPSK, BB_QAM_QPSK,
BB_QAM_QPSK, BB_QAM_16QAM,
BB_QAM_16QAM, BB_QAM_64QAM,
BB_QAM_64QAM, BB_QAM_64QAM,
BB_QAM_256QAM, BB_QAM_256QAM};
if (rate_idx <= BB_11M)
return BB_QAM_CCK;
if ((rate_idx >= BB_VHT_MCS(1, 0)) && (rate_idx <= BB_VHT_MCS(4, 9))) {
if (rate_idx >= BB_VHT_MCS(4, 0))
tmp_idx -= BB_VHT_MCS(4, 0);
else if (rate_idx >= BB_VHT_MCS(3, 0))
tmp_idx -= BB_VHT_MCS(3, 0);
else if (rate_idx >= BB_VHT_MCS(2, 0))
tmp_idx -= BB_VHT_MCS(2, 0);
else
tmp_idx -= BB_VHT_MCS(1, 0);
qam_order = qam[tmp_idx];
} else if ((rate_idx >= BB_HT_MCS(0)) && (rate_idx <= BB_HT_MCS(31))) {
if (rate_idx >= BB_HT_MCS(24))
tmp_idx -= BB_HT_MCS(24);
else if (rate_idx >= BB_HT_MCS(16))
tmp_idx -= BB_HT_MCS(16);
else if (rate_idx >= BB_HT_MCS(8))
tmp_idx -= BB_HT_MCS(8);
else
tmp_idx -= BB_HT_MCS(0);
qam_order = qam[tmp_idx];
} else {
if ((rate_idx > BB_06M) && (rate_idx <= BB_54M)) {
tmp_idx -= BB_06M;
qam_order = qam[tmp_idx - 1];
} else { /* OFDM 6M & all other undefine rate*/
qam_order = BB_QAM_BPSK;
}
}
return qam_order;
}
u8 halbb_rate_order_compute(struct bb_info *bb, u16 rate_idx)
{
u16 rate_order = rate_idx & 0x7f;
rate_idx &= 0x7f;
if (rate_idx >= BB_VHT_MCS(4, 0))
rate_order -= BB_VHT_MCS(4, 0);
else if (rate_idx >= BB_VHT_MCS(3, 0))
rate_order -= BB_VHT_MCS(3, 0);
else if (rate_idx >= BB_VHT_MCS(2, 0))
rate_order -= BB_VHT_MCS(2, 0);
else if (rate_idx >= BB_VHT_MCS(1, 0))
rate_order -= BB_VHT_MCS(1, 0);
else if (rate_idx >= BB_HT_MCS(24))
rate_order -= BB_HT_MCS(24);
else if (rate_idx >= BB_HT_MCS(16))
rate_order -= BB_HT_MCS(16);
else if (rate_idx >= BB_HT_MCS(8))
rate_order -= BB_HT_MCS(8);
else if (rate_idx >= BB_HT_MCS(0))
rate_order -= BB_HT_MCS(0);
else if (rate_idx >= BB_06M)
rate_order -= BB_06M;
else
rate_order -= BB_01M;
if (rate_idx >= BB_HT_MCS(0))
rate_order++;
return (u8)rate_order;
}
u8 halbb_init_ra_by_rssi(struct bb_info *bb, u8 rssi_assoc)
{
u8 init_ra_lv = 0;
BB_DBG(bb, DBG_RA, "====>%s\n", __func__);
if (rssi_assoc > 50)
init_ra_lv = 1;
else if (rssi_assoc > 30)
init_ra_lv = 2;
else if (rssi_assoc > 1)
init_ra_lv = 3;
else
init_ra_lv = 0;
return init_ra_lv;
}
bool halbb_set_csi_rate(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
u8 macid;
struct bb_h2c_ra_cfg_info *ra_cfg;
struct rtw_hal_stainfo_t *hal_sta_i;
struct rtw_ra_sta_info * ra_sta_i;
if (!phl_sta_i || !bb)
return false;
macid = (u8)(phl_sta_i->macid);
hal_sta_i = phl_sta_i->hal_sta;
if (!hal_sta_i)
return false;
ra_cfg = &bb->bb_ra_i[macid].ra_cfg;
ra_sta_i = &(hal_sta_i->ra_info);
if (!ra_sta_i)
return false;
/*if ((!ra_sta_i->ra_csi_rate_en) && (!ra_sta_i->fixed_csi_rate_en))
return false;*/
/* Set csi rate ctrl enable */
ra_cfg->ramask[7] |= BIT(7);
ra_cfg->ra_csi_rate_en = ra_sta_i->ra_csi_rate_en;
ra_cfg->fixed_csi_rate_en = ra_sta_i->fixed_csi_rate_en;
ra_cfg->cr_tbl_sel = bb->hal_com->csi_para_ctrl_sel;
ra_cfg->band_num = ra_sta_i->band_num;
ra_cfg->fixed_csi_rate_l = ra_sta_i->csi_rate.mcs_ss_idx;
ra_cfg->fixed_csi_rate_m = ra_sta_i->csi_rate.mode |
ra_sta_i->csi_rate.gi_ltf << 2 |
ra_sta_i->csi_rate.bw << 5;
return true;
}
u8 halbb_rssi_lv_dec(struct bb_info *bb, u8 rssi, u8 ratr_state)
{
/*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
/*u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};*/
u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
/*@ RSSI definition changed in AX*/
u8 new_rssi_lv = 0;
u8 i;
BB_DBG(bb, DBG_RA,
"curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
if (i >= (ratr_state))
rssi_lv_t[i] += RA_FLOOR_UP_GAP;
}
BB_DBG(bb, DBG_RA,
"RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
rssi_lv_t[4], rssi_lv_t[5]);
for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
if (rssi < rssi_lv_t[i]) {
new_rssi_lv = i;
break;
}
}
return new_rssi_lv;
}
u64 halbb_ramask_by_rssi(struct bb_info *bb, u8 rssi_lv, u64 ramask)
{
u64 ra_mask_bitmap = ramask;
if (rssi_lv == 0)
ra_mask_bitmap &= 0xffffffffffffffff;
else if (rssi_lv == 1)
ra_mask_bitmap &= 0xfffffffffffffff0;
else if (rssi_lv == 2)
ra_mask_bitmap &= 0xffffffffffffefe0;
else if (rssi_lv == 3)
ra_mask_bitmap &= 0xffffffffffffcfc0;
else if (rssi_lv == 4)
ra_mask_bitmap &= 0xffffffffffff8f80;
else if (rssi_lv >= 5)
ra_mask_bitmap &= 0xffffffffffff0f00;
/*Avoid empty HT/VHT/HE ramask when HT/VHT/HE mode is enabled*/
if ((ra_mask_bitmap >> 12) == 0x0) {
ra_mask_bitmap |= (ramask & 0xfffffffffffff000);
BB_DBG(bb, DBG_RA,
"Empty HT/VHT/HE ramask! Bypass HT/VHT/HE ramask_by_rssi\n");
}
/*Avoid empty legacy ramask after foolproof of HT/VHT/HE mode*/
if (ra_mask_bitmap == 0x0) {
ra_mask_bitmap |= (ramask & 0xfff);
BB_DBG(bb, DBG_RA,
"Empty ramask! Bypass a/b/g ramask_by_rssi\n");
}
return ra_mask_bitmap;
}
u64 halbb_ramask_mod(struct bb_info *bb, u8 macid, u64 ramask, u8 rssi, u8 mode,
u8 nss)
{
struct bb_ra_info *bb_ra = &bb->bb_ra_i[macid];
u64 mod_mask = ramask;
u64 mod_mask_rssi = ramask;
u8 new_rssi_lv = 0;
u8 wifi_mode = RA_non_ht;
if (mode == CCK_SUPPORT) { /* B mode */
mod_mask &= RAMASK_B;
wifi_mode = RA_CCK;
BB_DBG(bb, DBG_RA, "RA mask B mode\n");
} else if (mode == OFDM_SUPPORT) { /* AG mode */
mod_mask &= RAMASK_AG;
wifi_mode = RA_non_ht;
BB_DBG(bb, DBG_RA, "RA mask A mode\n");
} else if (mode == (CCK_SUPPORT|OFDM_SUPPORT)) {
/* BG mode */
mod_mask &= RAMASK_BG;
wifi_mode = RA_non_ht;
BB_DBG(bb, DBG_RA, "RA mask 2.4G BG mode\n");
} else if (mode == (CCK_SUPPORT|OFDM_SUPPORT|HT_SUPPORT)) {
/* 2G N mode */
mod_mask &= RAMASK_HT_2G;
wifi_mode = RA_HT;
BB_DBG(bb, DBG_RA, "RA mask 2.4G HT mode\n");
} else if (mode == (OFDM_SUPPORT|HT_SUPPORT)) {
/* 5G N mode */
mod_mask &= RAMASK_HT_5G;
wifi_mode = RA_HT;
BB_DBG(bb, DBG_RA, "RA mask 5G HT mode\n");
} else if (mode == (CCK_SUPPORT|OFDM_SUPPORT|VHT_SUPPORT_TX)) {
/* 2G AC mode */
mod_mask &= RAMASK_VHT_2G;
wifi_mode = RA_VHT;
BB_DBG(bb, DBG_RA, "RA mask 2.4G VHT mode\n");
} else if (mode == (OFDM_SUPPORT|VHT_SUPPORT_TX)) {
/* 5G AC mode */
mod_mask &= RAMASK_VHT_5G;
wifi_mode = RA_VHT;
BB_DBG(bb, DBG_RA, "RA mask 5G VHT mode\n");
} else if (mode == (CCK_SUPPORT|OFDM_SUPPORT|HE_SUPPORT)) {
/* 2G AX mode */
mod_mask &= RAMASK_HE_2G;
wifi_mode = RA_HE;
BB_DBG(bb, DBG_RA, "RA mask 2.4G HE mode\n");
} else if (mode == (OFDM_SUPPORT|HE_SUPPORT)) {
/* 5G AX mode */
mod_mask &= RAMASK_HE_5G;
wifi_mode = RA_HE;
BB_DBG(bb, DBG_RA, "RA mask 5G HE mode\n");
} else {
BB_WARNING("MD id %x, RA mask not found\n", mode);
}
BB_DBG(bb, DBG_RA, "RA mask SS NUM : %d\n", nss);
if (wifi_mode == RA_HT) {
switch (nss) {
case RA_1SS_MODE:
mod_mask &= RAMASK_1SS_HT;
break;
case RA_2SS_MODE:
mod_mask &= RAMASK_2SS_HT;
break;
case RA_3SS_MODE:
mod_mask &= RAMASK_3SS_HT;
break;
case RA_4SS_MODE:
mod_mask &= RAMASK_4SS_HT;
break;
default:
mod_mask &= RAMASK_1SS_HT;
break;
}
} else if (wifi_mode == RA_VHT) {
switch (nss) {
case RA_1SS_MODE:
mod_mask &= RAMASK_1SS_VHT;
break;
case RA_2SS_MODE:
mod_mask &= RAMASK_2SS_VHT;
break;
case RA_3SS_MODE:
mod_mask &= RAMASK_3SS_VHT;
break;
case RA_4SS_MODE:
mod_mask &= RAMASK_4SS_VHT;
break;
default:
mod_mask &= RAMASK_1SS_VHT;
break;
}
} else if (wifi_mode == RA_HE) {
switch (nss) {
case RA_1SS_MODE:
mod_mask &= RAMASK_1SS_HE;
break;
case RA_2SS_MODE:
mod_mask &= RAMASK_2SS_HE;
break;
case RA_3SS_MODE:
mod_mask &= RAMASK_3SS_HE;
break;
case RA_4SS_MODE:
mod_mask &= RAMASK_4SS_HE;
break;
default:
mod_mask &= RAMASK_1SS_HE;
break;
}
} else {
BB_DBG(bb, DBG_RA, "RA mask non-ht mode\n");
}
BB_DBG(bb, DBG_RA, "RA mask modify : %llx\n", mod_mask);
new_rssi_lv = halbb_rssi_lv_dec(bb, rssi, bb_ra->rssi_lv);
if (wifi_mode != RA_CCK) {
mod_mask_rssi = halbb_ramask_by_rssi(bb, new_rssi_lv, mod_mask);
//BB_DBG(bb, DBG_RA, "RA mask modify by rssi : 0x%016llx\n", mod_mask_rssi);
} else {
mod_mask_rssi = mod_mask;
}
return mod_mask_rssi;
}
void rtw_halbb_mudbg(struct bb_info *bb, u8 type, u8 mu_entry, u8 macid,
bool en_256q, bool en_1024q)
{
struct bb_h2c_mu_cfg mucfg = {0};
u32 *bb_h2c = (u32 *)&mucfg;
u8 cmdlen = sizeof(mucfg);
mucfg.cmd_type = type;
mucfg.entry = mu_entry;
mucfg.macid = macid;
halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MUCFG, HALBB_H2C_RA, bb_h2c);
}
u64 halbb_gen_abg_mask(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
u64 tmp_mask = 0;
u64 abg_mask = 0;
u8 i;
struct protocol_cap_t *asoc_cap_i;
if (!phl_sta_i)
return 0;
asoc_cap_i = &phl_sta_i->asoc_cap;
BB_DBG(bb, DBG_RA,
"supported rates(L->H) = [%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x]\n",
asoc_cap_i->supported_rates[0], asoc_cap_i->supported_rates[1],
asoc_cap_i->supported_rates[2], asoc_cap_i->supported_rates[3],
asoc_cap_i->supported_rates[4], asoc_cap_i->supported_rates[5],
asoc_cap_i->supported_rates[6], asoc_cap_i->supported_rates[7],
asoc_cap_i->supported_rates[8], asoc_cap_i->supported_rates[9],
asoc_cap_i->supported_rates[10], asoc_cap_i->supported_rates[11]);
for (i = 0; i < MAX_ABG_RATE_NUM; i++) {
if (asoc_cap_i->supported_rates[i] == 0x0)
continue;
tmp_mask = (u64)halbb_mgnt_2_hw_rate(asoc_cap_i->supported_rates[i]);
abg_mask |= (u64)BIT(tmp_mask);
}
BB_DBG(bb, DBG_RA, "gen_abgmask: 0x%llx\n", abg_mask);
return abg_mask;
}
u64 halbb_gen_vht_mask(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i)
{
u8 vht_cap[2] = {0};
u8 tmp_cap = 0;
u8 cap_ss;
u64 tmp_mask_nss = 0;
u8 i;
struct protocol_cap_t *asoc_cap_i;
/*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/
if (!phl_sta_i)
return 0;
asoc_cap_i = &phl_sta_i->asoc_cap;
vht_cap[0] = asoc_cap_i->vht_rx_mcs[0];
vht_cap[1] = asoc_cap_i->vht_rx_mcs[1];
BB_DBG(bb, DBG_RA, "%s : vhtcap:%x %x\n", __func__, vht_cap[0], vht_cap[1]);
for (i = 0; i < MAX_NSS_VHT; i++) {
if (i == 0)
tmp_cap = vht_cap[0];
else if (i == 4)
tmp_cap = vht_cap[1];
cap_ss = tmp_cap & 0x03;
tmp_cap = tmp_cap >> 2;
if (cap_ss == 0)
tmp_mask_nss |= ((u64)0xff << (i * 12));
else if (cap_ss == 1)
tmp_mask_nss |= ((u64)0x1ff << (i * 12));
else if (cap_ss == 2)
tmp_mask_nss |= ((u64)0x3ff << (i * 12));
BB_DBG(bb, DBG_RA, "gen_vhtmask:cap%x, ss%x, hemask: 0x%llx\n",
cap_ss, i, tmp_mask_nss);
}
return tmp_mask_nss;
}
u64 halbb_gen_ht_mask(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i)
{
u8 ht_cap[4] = {0};
u64 cap_ss;
u64 tmp_mask_nss = 0;
u8 i;
struct protocol_cap_t *asoc_cap_i;
/*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/
if (!phl_sta_i)
return 0;
asoc_cap_i = &phl_sta_i->asoc_cap;
for (i = 0; i < MAX_NSS_HT; i++)/* can use pointer after merge code*/
ht_cap[i] = asoc_cap_i->ht_rx_mcs[i];
BB_DBG(bb, DBG_RA, "%s : htcap: %x %x\n", __func__, ht_cap[0], ht_cap[1]);
for (i = 0; i < MAX_NSS_HT; i++) {
cap_ss = (u64)ht_cap[i];
tmp_mask_nss = tmp_mask_nss | (cap_ss << (i * 12));
BB_DBG(bb, DBG_RA, "gen_htmask:cap%llx, ss%x, htmask: 0x%llx\n", cap_ss, i, tmp_mask_nss);
}
return tmp_mask_nss;
}
u64 halbb_gen_he_mask(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i, enum channel_width bw)
{
u8 he_cap[2] = {0};
u8 tmp_cap = 0;
u8 cap_ss;
u64 tmp_mask_nss = 0;
u8 i;
struct protocol_cap_t *asoc_cap_i;
/*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/
/*@In HE cap, mcs is correspond to channel bw"*/
if (!phl_sta_i)
return 0;
asoc_cap_i = &phl_sta_i->asoc_cap;
if (bw == CHANNEL_WIDTH_80_80) {
he_cap[0] = asoc_cap_i->he_rx_mcs[4];
he_cap[1] = asoc_cap_i->he_rx_mcs[5];
} else if (bw == CHANNEL_WIDTH_160) {
he_cap[0] = asoc_cap_i->he_rx_mcs[2];
he_cap[1] = asoc_cap_i->he_rx_mcs[3];
} else {
he_cap[0] = asoc_cap_i->he_rx_mcs[0];
he_cap[1] = asoc_cap_i->he_rx_mcs[1];
}
BB_DBG(bb, DBG_RA, "%s: hecap:%x %x\n", __func__, he_cap[0], he_cap[1]);
for (i = 0; i < MAX_NSS_HE; i++) {
if (i == 0)
tmp_cap = he_cap[0];
else if (i == 4)
tmp_cap = he_cap[1];
cap_ss = tmp_cap & 0x03;
tmp_cap = tmp_cap >> 2;
if (cap_ss == 0)
tmp_mask_nss |= ((u64)0xff << (i * 12));
else if (cap_ss == 1)
tmp_mask_nss |= ((u64)0x3ff << (i * 12));
else if (cap_ss == 2)
tmp_mask_nss |= ((u64)0xfff << (i * 12));
BB_DBG(bb, DBG_RA, "gen_hemask:cap%x, ss%x, hemask: 0x%llx\n",
cap_ss, i, tmp_mask_nss);
}
return tmp_mask_nss;
}
bool halbb_chk_bw_under_20(struct bb_info *bb, u8 bw)
{
bool ret_val = true;
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
ret_val = true;
break;
case CHANNEL_WIDTH_40:
case CHANNEL_WIDTH_80:
case CHANNEL_WIDTH_80_80:
case CHANNEL_WIDTH_160:
ret_val = false;
break;
default:
ret_val = false;
break;
}
return ret_val;
}
bool halbb_chk_bw_under_40(struct bb_info *bb, u8 bw)
{
bool ret_val = true;
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
case CHANNEL_WIDTH_40:
ret_val = true;
break;
case CHANNEL_WIDTH_80:
case CHANNEL_WIDTH_80_80:
case CHANNEL_WIDTH_160:
ret_val = false;
break;
default:
ret_val = false;
break;
}
return ret_val;
}
bool halbb_hw_bw_mode_chk(struct bb_info *bb, u8 bw, u8 hw_mode)
{
bool ret_val = true;
switch (hw_mode) {
case CCK_SUPPORT:
case OFDM_SUPPORT:
case (CCK_SUPPORT | OFDM_SUPPORT):
ret_val = halbb_chk_bw_under_20(bb, bw);
break;
case HT_SUPPORT:
case (HT_SUPPORT | CCK_SUPPORT):
case (HT_SUPPORT | OFDM_SUPPORT):
case (HT_SUPPORT | OFDM_SUPPORT | CCK_SUPPORT):
ret_val = halbb_chk_bw_under_40(bb, bw);
break;
case VHT_SUPPORT_TX:
case (VHT_SUPPORT_TX | CCK_SUPPORT):
case (VHT_SUPPORT_TX | OFDM_SUPPORT):
case (VHT_SUPPORT_TX | OFDM_SUPPORT | CCK_SUPPORT):
case HE_SUPPORT:
case (HE_SUPPORT | CCK_SUPPORT):
case (HE_SUPPORT | OFDM_SUPPORT):
case (HE_SUPPORT | OFDM_SUPPORT | CCK_SUPPORT):
ret_val = true;
break;
default:
ret_val = true;
break;
}
if (!ret_val)
BB_WARNING("WRONG BW setting !!!!\n");
return ret_val;
}
u8 halbb_hw_bw_mapping(struct bb_info *bb, u8 bw, u8 hw_mode)
{
u8 hw_bw_map = CHANNEL_WIDTH_20;
bool ret_val;
if (bw <= CHANNEL_WIDTH_80)
hw_bw_map = bw;
else if (bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80)
hw_bw_map = CHANNEL_WIDTH_160;
else
hw_bw_map = CHANNEL_WIDTH_20;
ret_val = halbb_hw_bw_mode_chk(bb, bw, hw_mode);
return hw_bw_map;
}
u8 halbb_hw_mode_mapping(struct bb_info *bb, u8 wifi_mode)
{
u8 hw_mode_map = 0;
/* Driver wifi mode mapping */
if (wifi_mode & WLAN_MD_11B) /*11B*/
hw_mode_map |= CCK_SUPPORT;
if ((wifi_mode & WLAN_MD_11A) || (wifi_mode & WLAN_MD_11G)) /*11G, 11A*/
hw_mode_map |= OFDM_SUPPORT;
/* To prevent unnecessary mode from driver, causing confusing ra mask selection after then*/
if (wifi_mode & WLAN_MD_11AX) /*11AX*/
hw_mode_map |= HE_SUPPORT;
else if (wifi_mode & WLAN_MD_11AC) /*11AC*/
hw_mode_map |= VHT_SUPPORT_TX;
else if (wifi_mode & WLAN_MD_11N) /* 11_N*/
hw_mode_map |= HT_SUPPORT;
if (hw_mode_map == 0)
BB_WARNING("WRONG Wireless mode !!!!\n");
return hw_mode_map;
}
bool halbb_ac_n_sgi_chk(struct bb_info *bb, u8 hw_mode, bool en_sgi)
{
bool sgi_chk = en_sgi;
/* Driver wifi mode mapping */
if (hw_mode & HE_SUPPORT) {
sgi_chk = false;
BB_DBG(bb, DBG_RA, "HE mode sgi is not used!\n");
}
return sgi_chk;
}
u8 halbb_ax_giltf_chk(struct bb_info *bb, u8 hw_mode, u8 giltf_cap)
{
u8 giltf_chk = giltf_cap;
/* Driver wifi mode mapping */
if (!(hw_mode & HE_SUPPORT)) {
giltf_chk = 0;
BB_DBG(bb, DBG_RA, "In non-HE mode gi_ltf is not used!\n");
}
return giltf_chk;
}
bool halbb_ldpc_chk(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, u8 hw_mode)
{
struct protocol_cap_t *asoc_cap_i;
bool ldpc_en = false;
/* Driver wifi mode mapping */
if (!phl_sta_i)
return false;
asoc_cap_i = &phl_sta_i->asoc_cap;
if (hw_mode & HE_SUPPORT) {
ldpc_en |= asoc_cap_i->he_ldpc;
BB_DBG(bb, DBG_RA, "Enable HE LDPC\n");
} else if (hw_mode&VHT_SUPPORT_TX) {
ldpc_en |= asoc_cap_i->vht_ldpc;
BB_DBG(bb, DBG_RA, "Enable VHT LDPC\n");
} else if (hw_mode&HT_SUPPORT) {
ldpc_en |= asoc_cap_i->ht_ldpc;
BB_DBG(bb, DBG_RA, "Enable HT LDPC\n");
}
return ldpc_en;
}
u8 halbb_nss_mapping(struct bb_info *bb, u8 nss)
{
u8 mapping_nss = 0;
if (nss != 0)
mapping_nss = nss - 1;
/* Driver tx_nss mapping */
if (mapping_nss > (bb->hal_com->rfpath_tx_num - 1))
mapping_nss = bb->hal_com->rfpath_tx_num - 1;
return mapping_nss;
}
bool halbb_stbc_mapping(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, u8 hw_mode)
{
struct protocol_cap_t *asoc_cap_i;
bool stbc_en = false;
/* Driver wifi mode mapping */
if (!phl_sta_i)
return false;
asoc_cap_i = &phl_sta_i->asoc_cap;
if (hw_mode & HE_SUPPORT) {
if (asoc_cap_i->stbc_he_rx != 0)
stbc_en = true;
BB_DBG(bb, DBG_RA, "HE STBC %d\n", stbc_en);
} else if (hw_mode & VHT_SUPPORT_TX) {
if (asoc_cap_i->stbc_vht_rx != 0)
stbc_en = true;
BB_DBG(bb, DBG_RA, "VHT STBC %d\n", stbc_en);
} else if (hw_mode & HT_SUPPORT) {
if (asoc_cap_i->stbc_ht_rx != 0)
stbc_en = true;
BB_DBG(bb, DBG_RA, "HT STBC %d\n", stbc_en);
}
return stbc_en;
}
bool halbb_sgi_chk(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, u8 hw_bw)
{
struct protocol_cap_t *asoc_cap_i;
bool sgi_en = false;
/* Driver wifi mode mapping */
if (!phl_sta_i)
return false;
asoc_cap_i = &phl_sta_i->asoc_cap;
if (hw_bw == CHANNEL_WIDTH_20) {
sgi_en = asoc_cap_i->sgi_20;
BB_DBG(bb, DBG_RA, "Enable 20M SGI\n");
} else if (hw_bw == CHANNEL_WIDTH_40) {
sgi_en = asoc_cap_i->sgi_40;
BB_DBG(bb, DBG_RA, "Enable 40M SGI\n");
} else if (hw_bw == CHANNEL_WIDTH_80) {
sgi_en = asoc_cap_i->sgi_80;
BB_DBG(bb, DBG_RA, "Enable 80M SGI\n");
} else if (hw_bw == CHANNEL_WIDTH_160) {
sgi_en = asoc_cap_i->sgi_160;
BB_DBG(bb, DBG_RA, "Enable 160M SGI\n");
}
return sgi_en;
}
void halbb_ramask_trans(struct bb_info *bb, u8 macid, u64 mask)
{
struct bb_h2c_ra_cfg_info *ra_cfg = &bb->bb_ra_i[macid].ra_cfg;
ra_cfg->ramask[0] = (u8)(mask & 0x00000000000000ff);
ra_cfg->ramask[1] = (u8)((mask & 0x000000000000ff00)>>8);
ra_cfg->ramask[2] = (u8)((mask & 0x0000000000ff0000)>>16);
ra_cfg->ramask[3] = (u8)((mask & 0x00000000ff000000)>>24);
ra_cfg->ramask[4] = (u8)((mask & 0x000000ff00000000)>>32);
ra_cfg->ramask[5] = (u8)((mask & 0x0000ff0000000000)>>40);
ra_cfg->ramask[6] = (u8)((mask & 0x00ff000000000000)>>48);
ra_cfg->ramask[7] = (u8)((mask & 0xff00000000000000)>>56);
}
u8 halbb_get_opt_giltf(struct bb_info *bb, u8 assoc_giltf)
{
u8 i =0;
u8 opt_gi_ltf = 0;
if (assoc_giltf & BIT(1)) /* cap. for 4x0.8*/
opt_gi_ltf |= BIT(BB_OPT_GILTF_4XHE08);
else if (assoc_giltf & BIT(5)) /* cap. for 1x0.8*/
opt_gi_ltf |= BIT(BB_OPT_GILTF_1XHE08);
BB_DBG(bb, DBG_RA, "Ass GILTF=%x,opt GILTF=%x\n", assoc_giltf, opt_gi_ltf);
return opt_gi_ltf;
}
u8 halbb_giltf_trans(struct bb_info *bb, u8 assoc_giltf, u8 cal_giltf)
{
u8 i =0;
BB_DBG(bb, DBG_RA, "Ass GILTF=%x,Cal GILTF=%x\n", assoc_giltf, cal_giltf);
if (cal_giltf == RTW_GILTF_LGI_4XHE32 && (assoc_giltf & BIT(0)))
return cal_giltf;
else if (cal_giltf == RTW_GILTF_SGI_4XHE08 && (assoc_giltf & BIT(1)))
return cal_giltf;
else if (cal_giltf == RTW_GILTF_2XHE16 && (assoc_giltf & BIT(2)))
return cal_giltf;
else if (cal_giltf == RTW_GILTF_2XHE08 && (assoc_giltf & BIT(3)))
return cal_giltf;
else if (cal_giltf == RTW_GILTF_1XHE16 && (assoc_giltf & BIT(4)))
return cal_giltf;
else if (cal_giltf == RTW_GILTF_1XHE08 && (assoc_giltf & BIT(5)))
return cal_giltf;
if (assoc_giltf & BIT(3))
return RTW_GILTF_2XHE08;
else if (assoc_giltf & BIT(2))
return RTW_GILTF_2XHE16;
else if (assoc_giltf & BIT(1))
return RTW_GILTF_SGI_4XHE08;
else if (assoc_giltf & BIT(5))
return RTW_GILTF_1XHE08;
else if (assoc_giltf & BIT(4))
return RTW_GILTF_1XHE16;
else
return RTW_GILTF_LGI_4XHE32;
}
bool rtw_halbb_dft_mask(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i)
{
u8 mode = 0; /* connect to phl->assoc*/
u8 hw_md;
u64 init_mask = 0;
u64 get_mask = 0;
u32 mask0, mask1;
enum channel_width bw;
struct rtw_hal_stainfo_t *hal_sta_i;
struct protocol_cap_t *asoc_cap_i;
if (!phl_sta_i || !bb) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
return false;
}
hal_sta_i = phl_sta_i->hal_sta;
if (!hal_sta_i) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
return false;
}
asoc_cap_i = &phl_sta_i->asoc_cap;
mode = phl_sta_i->wmode;
bw = phl_sta_i->chandef.bw;
hw_md = halbb_hw_mode_mapping(bb, mode);
BB_DBG(bb, DBG_RA, "Gen Dftmask: mode = %x, hw_md = %x\n", mode, hw_md);
if (hw_md & (CCK_SUPPORT | OFDM_SUPPORT))
init_mask = halbb_gen_abg_mask(bb, phl_sta_i);
if (init_mask == 0) {
if (hw_md & CCK_SUPPORT) {
init_mask |= 0x0000000f;
BB_DBG(bb, DBG_RA,
"[%s]abg mask is null!, set b mask=0xf\n", __func__);
}
if (hw_md & OFDM_SUPPORT) {
init_mask |= 0x00000ff0;
BB_DBG(bb, DBG_RA,
"[%s]abg mask is null!, set ag mask=0xff\n", __func__);
}
}
if (hw_md & HE_SUPPORT)
get_mask = halbb_gen_he_mask(bb, phl_sta_i, bw);
else if (hw_md & VHT_SUPPORT_TX)
get_mask = halbb_gen_vht_mask(bb, phl_sta_i);
else if (hw_md & HT_SUPPORT)
get_mask = halbb_gen_ht_mask(bb, phl_sta_i);
else
get_mask = 0;
init_mask |= (get_mask << 12);
mask0 = (u32)(init_mask & 0xffffffff);
mask1 = (u32)((init_mask >> 32) & 0xffffffff);
if (init_mask != 0) {
hal_sta_i->ra_info.cur_ra_mask = init_mask;
BB_DBG(bb, DBG_RA, "Default mask = %x %x\n", mask0, mask1);
return true;
} else {
BB_WARNING("Error default mask, it should not zero\n");
return false;
}
}
u8 rtw_halbb_arfr_trans(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i)
{
struct rtw_hal_stainfo_t *hal_sta_i;
u8 mode;
u8 arfr_ret = 0x0;
if (!phl_sta_i)
return false;
hal_sta_i = phl_sta_i->hal_sta;
if (!hal_sta_i)
return false;
mode = phl_sta_i->wmode;
if (mode & WLAN_MD_11B) /*11B*/
arfr_ret |= CCK_SUPPORT;
if ((mode & WLAN_MD_11A)||(mode & WLAN_MD_11G)) /*11G, 11A*/
arfr_ret |= OFDM_SUPPORT;
if (mode & WLAN_MD_11N) /* 11_N*/
arfr_ret |= HT_SUPPORT;
if (mode & WLAN_MD_11AC) /*11AC*/
arfr_ret |= VHT_SUPPORT_TX;
return arfr_ret;
/*if (mode|WLAN_MD_11AX ) // 11AX usually can use arfr
hw_mode_map |= HE_SUPPORT;*/
}
bool rtw_halbb_raregistered(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
/*struct rtw_phl_stainfo_t *phl_sta_i = bb->phl_sta_info[macid];*/
u8 macid;
struct bb_h2c_ra_cfg_info *ra_cfg;
struct rtw_hal_stainfo_t *hal_sta_i;
bool tx_ldpc;
bool tx_stbc;
bool ret_val = false;
u8 tx_nss;
u8 rssi;
struct protocol_cap_t *asoc_cap_i;
u8 rssi_assoc ;
u8 mode;
bool en_sgi = false;
u8 giltf_cap = 0;
u8 init_lv;
/* Need to mapping with driver wifi mode*/
u32 *bb_h2c;
u8 cmdlen = sizeof(struct bb_h2c_ra_cfg_info);
u64 mod_mask;
BB_DBG(bb, DBG_RA, "====>%s\n", __func__);
if (!phl_sta_i || !bb) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
return ret_val;
}
macid = (u8)(phl_sta_i->macid);
ra_cfg = &bb->bb_ra_i[macid].ra_cfg;
bb_h2c = (u32 *) ra_cfg;
hal_sta_i = phl_sta_i->hal_sta;
if (!hal_sta_i) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
return ret_val;
}
asoc_cap_i = &phl_sta_i->asoc_cap;
/*@ use assoc rssi to init ra, only use in ra register, it is an integer using U(8,0)*/
rssi_assoc = (u8)(hal_sta_i->rssi_stat.assoc_rssi);
BB_DBG(bb, DBG_RA, "Assoc rssi = %d\n", rssi_assoc);
rssi = (u8)(hal_sta_i->rssi_stat.rssi) >> 1;
mode = phl_sta_i->wmode;
init_lv = halbb_init_ra_by_rssi(bb, rssi_assoc);
/*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/
tx_nss = halbb_nss_mapping(bb, asoc_cap_i->nss_rx);
if (asoc_cap_i->dcm_max_const_rx)
ra_cfg->dcm_cap = 1;
else
ra_cfg->dcm_cap = 0;
mode = halbb_hw_mode_mapping(bb, mode);
/* ONLY need to get the optional gi-ltf combination for H2C FW*/
/* bit(0)=4x0.8, bit(1)=1x0.8 -> different definition from the drver giltf*/
giltf_cap = halbb_get_opt_giltf(bb, asoc_cap_i->ltf_gi);
ra_cfg->giltf_cap = halbb_ax_giltf_chk(bb, mode, giltf_cap);
/* giltf assigned by driver or trained by FW*/
hal_sta_i->ra_info.cal_giltf = (u8)RTW_GILTF_2XHE08; /*value from driver, temporarily set here, no work until bool fixed_giltf_en assign at hal layer;*/
if (bb->ic_type == BB_RTL8852B)
ra_cfg->fix_giltf_en = true; /* Need to move to hal layer*/
else
ra_cfg->fix_giltf_en = false; /* Need to move to hal layer*/
ra_cfg->fix_giltf = halbb_giltf_trans(bb, asoc_cap_i->ltf_gi, hal_sta_i->ra_info.cal_giltf);
BB_DBG(bb, DBG_RA, "fix_giltf_en=%d, fix_giltf=%d\n", ra_cfg->fix_giltf_en,
ra_cfg->fix_giltf);
ra_cfg->is_dis_ra = hal_sta_i->ra_info.dis_ra;
mod_mask = hal_sta_i->ra_info.cur_ra_mask;
ra_cfg->er_cap = asoc_cap_i->er_su;
tx_stbc = halbb_stbc_mapping(bb, phl_sta_i, mode);
ra_cfg->upd_all= true;
ra_cfg->upd_bw_nss_mask= false;
ra_cfg->upd_mask= false;
if (mode == 0)
return ret_val;
tx_ldpc = halbb_ldpc_chk(bb, phl_sta_i, mode);
ra_cfg->mode_ctrl = mode;
ra_cfg->bw_cap = halbb_hw_bw_mapping(bb, phl_sta_i->chandef.bw, mode);
en_sgi = halbb_sgi_chk(bb, phl_sta_i, ra_cfg->bw_cap);
ra_cfg->macid = macid;
ra_cfg->init_rate_lv = init_lv;
ra_cfg->en_sgi = halbb_ac_n_sgi_chk(bb, mode, en_sgi);
ra_cfg->ldpc_cap = tx_ldpc;
ra_cfg->stbc_cap = tx_stbc;
ra_cfg->ss_num = tx_nss;
/*@ modify ra mask by assoc rssi*/
mod_mask = halbb_ramask_mod(bb, macid, mod_mask, rssi_assoc, mode, tx_nss);
halbb_ramask_trans(bb, macid, mod_mask);
ret_val = halbb_set_csi_rate(bb, phl_sta_i);
if (!ret_val)
return ret_val;
BB_DBG(bb, DBG_RA, "RA Register=>In: Dis_ra=%x, MD=%x, BW=%x, macid=%x\n",
hal_sta_i->ra_info.dis_ra, mode, phl_sta_i->chandef.bw, macid);
BB_DBG(bb, DBG_RA, "RA Register=>In: DCM =%x, ER=%x, in_rt=%x, upd_a=%x, sgi=%x, ldpc=%x, stbc=%x\n",
ra_cfg->dcm_cap, ra_cfg->er_cap, init_lv, ra_cfg->upd_all,
en_sgi, tx_ldpc, tx_stbc);
BB_DBG(bb, DBG_RA, "RA Register=>In: SS=%x, GILTF_cap=%x, upd_bnm=%x, upd_m=%x, mask=%llx\n",
tx_nss, giltf_cap, ra_cfg->upd_bw_nss_mask, ra_cfg->upd_mask, mod_mask);
BB_DBG(bb, DBG_RA, "RA Register=>Out racfg: dis%x bw%x md%x mid%x\n", ra_cfg->is_dis_ra,
ra_cfg->bw_cap, ra_cfg->mode_ctrl, ra_cfg->macid);
BB_DBG(bb, DBG_RA, "RA Register=>Out h2cp: %x %x %x %x\n", bb_h2c[0], bb_h2c[1],
bb_h2c[2], bb_h2c[3]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c);
return ret_val;
}
bool rtw_halbb_ra_deregistered(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i)
{
return true;
}
bool rtw_halbb_raupdate(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_i)
{
/* Update only change bw, nss, ramask */
u8 macid;
struct bb_h2c_ra_cfg_info *ra_cfg;
struct rtw_hal_stainfo_t *hal_sta_i;
struct protocol_cap_t *asoc_cap_i;
u8 tx_nss;
u8 rssi;
u8 init_lv = 0;
u8 mode = 0;
u8 giltf_cap = 0;
bool ret_val = false;
/* Need to mapping with driver wifi mode*/
u32 *bb_h2c;
u8 cmdlen = sizeof(struct bb_h2c_ra_cfg_info);
u64 mod_mask;
BB_DBG(bb, DBG_RA, "====>%s\n", __func__);
if (!phl_sta_i || !bb) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
return ret_val;
}
macid = (u8) (phl_sta_i->macid);
hal_sta_i = phl_sta_i->hal_sta;
if (!hal_sta_i) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
return ret_val;
}
ra_cfg = &bb->bb_ra_i[macid].ra_cfg;
mode = ra_cfg->mode_ctrl;
bb_h2c = (u32 *) ra_cfg;
asoc_cap_i = &phl_sta_i->asoc_cap;
rssi = hal_sta_i->rssi_stat.rssi >> 1;
/*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/
tx_nss = halbb_nss_mapping(bb, asoc_cap_i->nss_rx);
ra_cfg->is_dis_ra = hal_sta_i->ra_info.dis_ra;
mod_mask = hal_sta_i->ra_info.cur_ra_mask;
ra_cfg->upd_all= false;
ra_cfg->upd_bw_nss_mask= true;
ra_cfg->upd_mask= false;
mode = ra_cfg->mode_ctrl;
if (mode == 0)
return ret_val;
ra_cfg->mode_ctrl = mode;
/* ONLY need to get the optional gi-ltf combination for H2C FW*/
/* bit(0)=4x0.8, bit(1)=1x0.8 -> different definition from the drver giltf*/
giltf_cap = halbb_get_opt_giltf(bb, asoc_cap_i->ltf_gi);
ra_cfg->giltf_cap = halbb_ax_giltf_chk(bb, mode, giltf_cap);
/* giltf assigned by driver or trained by FW*/
hal_sta_i->ra_info.cal_giltf = (u8)RTW_GILTF_2XHE08; /*value from driver, temporarily set here, no work until bool fixed_giltf_en assign at hal layer;*/
if (bb->ic_type == BB_RTL8852B)
ra_cfg->fix_giltf_en = true; /* Need to move to hal layer*/
else
ra_cfg->fix_giltf_en = false; /* Need to move to hal layer*/
ra_cfg->fix_giltf = halbb_giltf_trans(bb, asoc_cap_i->ltf_gi, hal_sta_i->ra_info.cal_giltf);
BB_DBG(bb, DBG_RA, "fix_giltf_en=%d, fix_giltf=%d\n", ra_cfg->fix_giltf_en,
ra_cfg->fix_giltf);
ra_cfg->bw_cap = halbb_hw_bw_mapping(bb, phl_sta_i->chandef.bw, mode);
ra_cfg->init_rate_lv = 0;
ra_cfg->ss_num = tx_nss;
mod_mask = halbb_ramask_mod(bb, macid, mod_mask, rssi, mode, tx_nss);
halbb_ramask_trans(bb, macid, mod_mask);
BB_DBG(bb, DBG_RA, "RA update: %x %x %x\n", bb_h2c[0], bb_h2c[1],
bb_h2c[2]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c);
return ret_val;
}
bool halbb_raupdate_mask(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
{
u8 macid;
struct bb_h2c_ra_cfg_info *ra_cfg;
struct rtw_hal_stainfo_t *hal_sta_i;
struct protocol_cap_t *asoc_cap_i;
u8 tx_nss;
u8 rssi;
u8 init_lv = 0;
u8 mode = 0;
u8 giltf_cap = 0;
bool ret_val = false;
/* Need to mapping with driver wifi mode*/
u32 *bb_h2c;
u8 cmdlen = sizeof(struct bb_h2c_ra_cfg_info);
u64 mod_mask;
macid = (u8)(phl_sta_i->macid);
hal_sta_i = phl_sta_i->hal_sta;
ra_cfg = &bb->bb_ra_i[macid].ra_cfg;
mode = ra_cfg->mode_ctrl;
bb_h2c = (u32 *) ra_cfg;
asoc_cap_i = &phl_sta_i->asoc_cap;
rssi = hal_sta_i->rssi_stat.rssi >> 1;
/*@Becareful RA use our "Tx" capability which means the capability of their "Rx"*/
tx_nss = halbb_nss_mapping(bb, asoc_cap_i->nss_rx);
ra_cfg->is_dis_ra = hal_sta_i->ra_info.dis_ra;
mod_mask = hal_sta_i->ra_info.cur_ra_mask;
ra_cfg->upd_all= false;
ra_cfg->upd_bw_nss_mask= false;
ra_cfg->upd_mask= true;
/* while ra mask is updated, gi_ltf can also be update */
mode = ra_cfg->mode_ctrl;
if (mode == 0)
return ret_val;
ra_cfg->mode_ctrl = mode;
ra_cfg->init_rate_lv = 0;
/* ONLY need to get the optional gi-ltf combination for H2C FW*/
/* bit(0)=4x0.8, bit(1)=1x0.8 -> different definition from the drver giltf*/
giltf_cap = halbb_get_opt_giltf(bb, asoc_cap_i->ltf_gi);
ra_cfg->giltf_cap = halbb_ax_giltf_chk(bb, mode, giltf_cap);
/* giltf assigned by driver or trained by FW*/
hal_sta_i->ra_info.cal_giltf = (u8)RTW_GILTF_2XHE08; /*value from driver, temporarily set here, no work until bool fixed_giltf_en assign at hal layer;*/
if (bb->ic_type == BB_RTL8852B)
ra_cfg->fix_giltf_en = true; /* Need to move to hal layer*/
else
ra_cfg->fix_giltf_en = false; /* Need to move to hal layer*/
ra_cfg->fix_giltf = halbb_giltf_trans(bb, asoc_cap_i->ltf_gi, hal_sta_i->ra_info.cal_giltf);
/* Need to verfy GI LTF flow
ra_cfg->fix_giltf = halbb_ra_giltf_ctrl(bb, macid, delay_sp, asoc_cap_i->ltf_gi);
*/
BB_DBG(bb, DBG_RA, "fix_giltf_en=%d, fix_giltf=%d\n", ra_cfg->fix_giltf_en,
ra_cfg->fix_giltf);
mod_mask = halbb_ramask_mod(bb, macid, mod_mask, rssi, mode, tx_nss);
halbb_ramask_trans(bb, macid, mod_mask);
BB_DBG(bb, DBG_RA, "RA update mask: %x %x %x\n", bb_h2c[0], bb_h2c[1],
bb_h2c[2]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c);
return ret_val;
}
u32 halbb_get_fw_ra_rpt(struct bb_info *bb, u16 len, u8 *c2h)
{
u16 macid_rpt;
struct rtw_hal_stainfo_t *hal_sta_i;
struct rtw_phl_stainfo_t *phl_sta_i;
struct rtw_rate_info *rt_i;
struct halbb_ra_rpt_info *ra_rpt_i;
if (!c2h)
return 0;
ra_rpt_i = (struct halbb_ra_rpt_info *)c2h;
macid_rpt = ra_rpt_i->rpt_macid_l + (ra_rpt_i->rpt_macid_m << 8);
if (macid_rpt >= PHL_MAX_STA_NUM) {
BB_WARNING("[%s]Error macid = %d!!\n", __func__, macid_rpt);
return 0;
}
if (!bb->sta_exist[macid_rpt]) {
BB_WARNING("[%s]Error macid = %d!!\n", __func__, macid_rpt);
return 0;
}
phl_sta_i = bb->phl_sta_info[(u8)macid_rpt];
if (!phl_sta_i) {
BB_WARNING("[%s]phl_sta==NULL, Wrong C2H RA macid !!\n", __func__);
return 0;
}
hal_sta_i = phl_sta_i->hal_sta;
if (!hal_sta_i) {
BB_WARNING("[%s]hal_sta==NULL, Wrong C2H RA macid !!\n", __func__);
return 0;
}
hal_sta_i->ra_info.curr_retry_ratio = ra_rpt_i->retry_ratio;
rt_i = &hal_sta_i->ra_info.rpt_rt_i;
rt_i->mcs_ss_idx = ra_rpt_i->rpt_mcs_nss;
rt_i->gi_ltf = ra_rpt_i->rpt_gi_ltf;
rt_i->bw = ra_rpt_i->rpt_bw;
rt_i->mode = ra_rpt_i->rpt_md_sel;
BB_DBG(bb, DBG_RA, "RA RPT: macid = %d, mode = %d, giltf = %x, mcs_nss = %x\n",
macid_rpt, rt_i->mode, rt_i->gi_ltf, rt_i->mcs_ss_idx);
return 0;
}
bool rtw_halbb_query_txsts(struct bb_info *bb, u16 macid0, u16 macid1)
{
u8 content[4];
u32 *bb_h2c = (u32 *)content;
bool ret_val;
u16 cmdlen = 4;
BB_DBG(bb, DBG_RA, "====> QuerryTxSts : macid = %d %d\n", macid0, macid1);
content[0] = (u8)(macid0& 0xff);
content[1] = (u8)((macid0>>8)& 0xff);
content[2] = (u8)(macid1& 0xff);
content[3] = (u8)((macid1>>8)& 0xff);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_GET_TXSTS, HALBB_H2C_RA, bb_h2c);
if (!ret_val)
BB_WARNING("Error H2C cmd in querry txsts !!\n");
return ret_val;
}
void halbb_drv_cmac_rpt_parsing(struct bb_info *bb, u8 *rpt)
{
struct bb_fw_cmac_rpt_info *c_rpt;
u16 rpt_len, i;
u8 *rpt_tmp = rpt;
if (!rpt)
return;
c_rpt = (struct bb_fw_cmac_rpt_info *)rpt;
rpt_len = sizeof(struct bb_fw_cmac_rpt_info);
if (rpt_len % 4) {
return;
}
BB_DBG(bb, DBG_RA,
"[%d] try_rate=%d, fix_rate=0x%x, final{rate, giltf}={0x%x,0x%x}, data_bw = 0x%x\n",
c_rpt->macid, c_rpt->try_rate, c_rpt->fix_rate,
c_rpt->final_rate, c_rpt->final_gi_ltf, c_rpt->data_bw);
for (i = 0; i < rpt_len; i++) {
BB_DBG(bb, DBG_RA, "[%d] 0x%x\n", i, *(u32*)rpt);
rpt_tmp += 4;
}
}
u32 halbb_get_txsts_rpt(struct bb_info *bb, u16 len, u8 *c2h)
{
u16 macid_rpt;
u8 i = 0;
struct rtw_hal_stainfo_t *hal_sta_i;
struct rtw_phl_stainfo_t *phl_sta_i;
struct rtw_ra_sta_info *ra_sta_i;
struct halbb_txsts_info *txsts_i;
u16 tx_total;
u16 tx_ok[4];
u16 tx_retry[4];
if (!c2h)
return 0;
txsts_i = (struct halbb_txsts_info *)c2h;
macid_rpt = txsts_i->rpt_macid_l + (txsts_i->rpt_macid_m << 8);
if (macid_rpt >= PHL_MAX_STA_NUM) {
BB_WARNING("report macid = %d, Error macid !!\n", macid_rpt);
return 0;
}
if (!bb->sta_exist[macid_rpt]) {
BB_WARNING("report macid = %d, Error macid !!\n", macid_rpt);
return 0;
}
phl_sta_i = bb->phl_sta_info[(u8)macid_rpt];
if (phl_sta_i == NULL) {
BB_WARNING("phl_sta == NULL, Wrong C2H RA macid !!\n");
return 0;
}
hal_sta_i = phl_sta_i->hal_sta;
if (hal_sta_i == NULL) {
BB_WARNING("hal_sta == NULL, Wrong C2H RA macid !!\n");
return 0;
}
ra_sta_i = &hal_sta_i->ra_info;
tx_ok[0] = txsts_i->tx_ok_be_l + (txsts_i->tx_ok_be_m << 8);
tx_ok[1] = txsts_i->tx_ok_bk_l + (txsts_i->tx_ok_bk_m << 8);
tx_ok[2] = txsts_i->tx_ok_vi_l + (txsts_i->tx_ok_vi_m << 8);
tx_ok[3] = txsts_i->tx_ok_vo_l + (txsts_i->tx_ok_vo_m << 8);
tx_retry[0] = txsts_i->tx_retry_be_l + (txsts_i->tx_retry_be_m << 8);
tx_retry[1] = txsts_i->tx_retry_bk_l + (txsts_i->tx_retry_bk_m << 8);
tx_retry[2] = txsts_i->tx_retry_vi_l + (txsts_i->tx_retry_vi_m << 8);
tx_retry[3] = txsts_i->tx_retry_vo_l + (txsts_i->tx_retry_vo_m << 8);
for ( i = 0; i <= 3; i++) {
if ((0xffffffff - ra_sta_i->tx_ok_cnt[i]) > (tx_ok[i]))
ra_sta_i->tx_ok_cnt[i] += tx_ok[i];
if ((0xffffffff - ra_sta_i->tx_retry_cnt[i]) > (tx_retry[i]))
ra_sta_i->tx_retry_cnt[i] += tx_retry[i];
BB_DBG(bb, DBG_RA, "TxOk[%d] = %d, TxRty[%d] = %d\n", i, tx_ok[i], i, tx_retry[i]);
}
tx_total = txsts_i->tx_total_l + (txsts_i->tx_total_m << 8);
if ((0xffffffff - ra_sta_i->tx_total_cnt) > tx_total)
ra_sta_i->tx_total_cnt += tx_total;
BB_DBG(bb, DBG_RA, "====> GetTxSts : TxTotal = %d\n", tx_total);
return 0;
}
void halbb_ra_rssisetting(struct bb_info *bb)
{
u8 macid = 0;
u8 i = 0, sta_cnt = 0;
u16 cmdlen;
bool ret_val = true;
struct rtw_ra_sta_info *bb_ra;
struct rtw_hal_stainfo_t *hal_sta_i;
struct bb_h2c_rssi_setting *rssi_i;
struct bb_link_info *bb_link = &bb->bb_link_i;
u16 rssi_len = 0;
u32 *bb_h2c;
u8 rssi_a = 0;
u8 rssi_b = 0;
rssi_len = sizeof(struct bb_h2c_rssi_setting) * PHL_MAX_STA_NUM;
rssi_i = hal_mem_alloc(bb->hal_com, rssi_len);
if (!rssi_i) {
BB_WARNING(" Error RSSI allocat failed!!\n");
return;
}
bb_h2c = (u32 *)rssi_i;
cmdlen = rssi_len;
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!bb->sta_exist[i] || !bb->phl_sta_info[i])
continue;
hal_sta_i = bb->phl_sta_info[i]->hal_sta;
if (!hal_sta_i)
continue;
bb_ra = &hal_sta_i->ra_info;
if (!(bb_ra->ra_registered))
continue;
macid = (u8)(bb->phl_sta_info[i]->macid);
BB_DBG(bb, DBG_RA, "Add BB rssi info[%d], macid=%d\n", i, macid);
/* Need modify for Nss > 2 */
rssi_a = (hal_sta_i->rssi_stat.rssi_ma_path[0] >> 5) & 0x7f;
if (!bb->hal_com->dbcc_en)
rssi_b = (hal_sta_i->rssi_stat.rssi_ma_path[1] >> 5) & 0x7f;
rssi_i[sta_cnt].macid = macid;
rssi_i[sta_cnt].rssi = rssi_a | BIT(7);
rssi_i[sta_cnt].rainfo1 = 0;
rssi_i[sta_cnt].rainfo2 = 0; /* RSVD */
rssi_i[sta_cnt].drv_ractrl = 0; /* RSVD */
rssi_i[sta_cnt].is_fixed_rate = bb_ra->fixed_rt_en;
rssi_i[sta_cnt].fixed_rate = bb_ra->fixed_rt_i.mcs_ss_idx;
rssi_i[sta_cnt].fixed_rate_md = bb_ra->fixed_rt_i.mode;
rssi_i[sta_cnt].fixed_giltf = bb_ra->fixed_rt_i.gi_ltf;
rssi_i[sta_cnt].fixed_bw = bb_ra->fixed_rt_i.bw;
rssi_i[sta_cnt].rsvd2_rssi_b = rssi_b;
sta_cnt++;
if (sta_cnt == bb_link->num_linked_client)
break;
}
if (sta_cnt == STA_NUM_RSSI_CMD) {
/* Fill endcmd = 1 for last sta */
rssi_i[sta_cnt - 1].endcmd = 1;
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING,
HALBB_H2C_RA, bb_h2c);
BB_DBG(bb, DBG_RA, "sta_cnt=%d, RSSI cmd end 1\n", sta_cnt);
} else if ((sta_cnt > 0) && (sta_cnt < STA_NUM_RSSI_CMD)) {
/* Fill endcmd = 1 for last sta */
rssi_i[sta_cnt - 1].endcmd = 1;
rssi_i[sta_cnt].macid = 0xff;
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING,
HALBB_H2C_RA, bb_h2c);
BB_DBG(bb, DBG_RA, "sta_cnt=%d, RSSI cmd end 2\n", sta_cnt);
}
BB_DBG(bb, DBG_RA, "RSSI=>h2c[0~3]: %x %x %x %x\n", bb_h2c[0], bb_h2c[1],
bb_h2c[2], bb_h2c[3]);
if (ret_val == false)
BB_WARNING(" H2C cmd error!!\n");
if (rssi_i)
hal_mem_free(bb->hal_com, rssi_i, rssi_len);
}
void halbb_ra_giltf_ctrl(struct bb_info *bb, u8 macid, u8 delay_sp, u8 assoc_giltf)
{
struct bb_ra_info *bb_ra = &bb->bb_ra_i[macid];
struct bb_h2c_ra_cfg_info *ra_cfg = &bb->bb_ra_i[macid].ra_cfg;
enum rtw_gi_ltf giltf = RTW_GILTF_LGI_4XHE32;
if (!bb)
return;
/*This dhould be decision before ra mask h2c*/
/* GI LTF decision algorithm is needed*/
/*if (delay_sp)
giltf = RTW_GILTF_LGI_4XHE32;
else
giltf = RTW_GILTF_LGI_4XHE32;
ra_cfg->giltf = giltf;*/
}
void halbb_ra_watchdog(struct bb_info *bb)
{
struct bb_link_info *bb_link = &bb->bb_link_i;
u8 i = 0, sta_cnt = 0, macid = 0;
#if 0
if (!(bb->support_ability & BB_RA))
return;
#endif
halbb_ra_rssisetting(bb);
for (i = 0; i < PHL_MAX_STA_NUM; i++) {
if (!(bb->sta_exist[i]))
continue;
if (!(bb->phl_sta_info[i]) || !bb) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
continue;
}
if (!(bb->phl_sta_info[i]->hal_sta)) {
BB_WARNING("Error RA registered !!! Pointer is NULL!!!\n");
continue;
}
if (!(bb->phl_sta_info[i]->hal_sta->ra_info.ra_registered))
continue;
macid = (u8)(bb->phl_sta_info[i]->macid);
BB_DBG(bb, DBG_RA, "====>ra update mask[%d], macid=%d\n", i, macid);
halbb_raupdate_mask(bb, bb->phl_sta_info[i]);
sta_cnt++;
if (sta_cnt == bb_link->num_linked_client)
break;
}
}
void halbb_ra_init(struct bb_info *bb)
{
struct bb_ra_info *bb_ra = NULL;
u8 macid = 0;
for (macid = 0; macid < PHL_MAX_STA_NUM; macid ++) {
bb_ra = &bb->bb_ra_i[macid];
if (!bb_ra)
halbb_mem_set(bb, bb_ra, 0, sizeof (struct bb_ra_info));
}
}
u8 rtw_halbb_rts_rate(struct bb_info *bb, u16 tx_rate, bool is_erp_prot)
{
u8 rts_ini_rate = RTW_DATA_RATE_OFDM6;
if (is_erp_prot) { /* use CCK rate as RTS */
rts_ini_rate = RTW_DATA_RATE_CCK1;
} else {
switch (tx_rate) {
case RTW_DATA_RATE_VHT_NSS4_MCS9:
case RTW_DATA_RATE_VHT_NSS4_MCS8:
case RTW_DATA_RATE_VHT_NSS4_MCS7:
case RTW_DATA_RATE_VHT_NSS4_MCS6:
case RTW_DATA_RATE_VHT_NSS4_MCS5:
case RTW_DATA_RATE_VHT_NSS4_MCS4:
case RTW_DATA_RATE_VHT_NSS4_MCS3:
case RTW_DATA_RATE_VHT_NSS3_MCS9:
case RTW_DATA_RATE_VHT_NSS3_MCS8:
case RTW_DATA_RATE_VHT_NSS3_MCS7:
case RTW_DATA_RATE_VHT_NSS3_MCS6:
case RTW_DATA_RATE_VHT_NSS3_MCS5:
case RTW_DATA_RATE_VHT_NSS3_MCS4:
case RTW_DATA_RATE_VHT_NSS3_MCS3:
case RTW_DATA_RATE_VHT_NSS2_MCS9:
case RTW_DATA_RATE_VHT_NSS2_MCS8:
case RTW_DATA_RATE_VHT_NSS2_MCS7:
case RTW_DATA_RATE_VHT_NSS2_MCS6:
case RTW_DATA_RATE_VHT_NSS2_MCS5:
case RTW_DATA_RATE_VHT_NSS2_MCS4:
case RTW_DATA_RATE_VHT_NSS2_MCS3:
case RTW_DATA_RATE_VHT_NSS1_MCS9:
case RTW_DATA_RATE_VHT_NSS1_MCS8:
case RTW_DATA_RATE_VHT_NSS1_MCS7:
case RTW_DATA_RATE_VHT_NSS1_MCS6:
case RTW_DATA_RATE_VHT_NSS1_MCS5:
case RTW_DATA_RATE_VHT_NSS1_MCS4:
case RTW_DATA_RATE_VHT_NSS1_MCS3:
case RTW_DATA_RATE_MCS31:
case RTW_DATA_RATE_MCS30:
case RTW_DATA_RATE_MCS29:
case RTW_DATA_RATE_MCS28:
case RTW_DATA_RATE_MCS27:
case RTW_DATA_RATE_MCS23:
case RTW_DATA_RATE_MCS22:
case RTW_DATA_RATE_MCS21:
case RTW_DATA_RATE_MCS20:
case RTW_DATA_RATE_MCS19:
case RTW_DATA_RATE_MCS15:
case RTW_DATA_RATE_MCS14:
case RTW_DATA_RATE_MCS13:
case RTW_DATA_RATE_MCS12:
case RTW_DATA_RATE_MCS11:
case RTW_DATA_RATE_MCS7:
case RTW_DATA_RATE_MCS6:
case RTW_DATA_RATE_MCS5:
case RTW_DATA_RATE_MCS4:
case RTW_DATA_RATE_MCS3:
case RTW_DATA_RATE_OFDM54:
case RTW_DATA_RATE_OFDM48:
case RTW_DATA_RATE_OFDM36:
case RTW_DATA_RATE_OFDM24:
rts_ini_rate = RTW_DATA_RATE_OFDM24;
break;
case RTW_DATA_RATE_VHT_NSS4_MCS2:
case RTW_DATA_RATE_VHT_NSS4_MCS1:
case RTW_DATA_RATE_VHT_NSS3_MCS2:
case RTW_DATA_RATE_VHT_NSS3_MCS1:
case RTW_DATA_RATE_VHT_NSS2_MCS2:
case RTW_DATA_RATE_VHT_NSS2_MCS1:
case RTW_DATA_RATE_VHT_NSS1_MCS2:
case RTW_DATA_RATE_VHT_NSS1_MCS1:
case RTW_DATA_RATE_MCS26:
case RTW_DATA_RATE_MCS25:
case RTW_DATA_RATE_MCS18:
case RTW_DATA_RATE_MCS17:
case RTW_DATA_RATE_MCS10:
case RTW_DATA_RATE_MCS9:
case RTW_DATA_RATE_MCS2:
case RTW_DATA_RATE_MCS1:
case RTW_DATA_RATE_OFDM18:
case RTW_DATA_RATE_OFDM12:
rts_ini_rate = RTW_DATA_RATE_OFDM12;
break;
case RTW_DATA_RATE_VHT_NSS4_MCS0:
case RTW_DATA_RATE_VHT_NSS3_MCS0:
case RTW_DATA_RATE_VHT_NSS2_MCS0:
case RTW_DATA_RATE_VHT_NSS1_MCS0:
case RTW_DATA_RATE_MCS24:
case RTW_DATA_RATE_MCS16:
case RTW_DATA_RATE_MCS8:
case RTW_DATA_RATE_MCS0:
case RTW_DATA_RATE_OFDM9:
case RTW_DATA_RATE_OFDM6:
rts_ini_rate = RTW_DATA_RATE_OFDM6;
break;
case RTW_DATA_RATE_CCK11:
case RTW_DATA_RATE_CCK5_5:
case RTW_DATA_RATE_CCK2:
case RTW_DATA_RATE_CCK1:
rts_ini_rate = RTW_DATA_RATE_CCK1;
break;
default:
rts_ini_rate = RTW_DATA_RATE_OFDM6;
break;
}
}
if (bb->hal_com->band[0].cur_chandef.band == BAND_ON_5G) {
if (rts_ini_rate < RTW_DATA_RATE_OFDM6)
rts_ini_rate = RTW_DATA_RATE_OFDM6;
}
return rts_ini_rate;
}
void halbb_ra_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char help[] = "-h";
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i;
u8 rssi_assoc = 60;
bool ret_val = false;
struct rtw_ra_sta_info *bb_ra;
struct rtw_hal_stainfo_t *hal_sta_i;
//struct bb_h2c_rssi_setting *rssi_i;
u16 rssi_len = 0;
u8 rssi_a = 0;
u8 rssi_b = 0;
if (_os_strcmp(input[1], help) == 0) {
//BB_DBG_CNSL(out_len, used, output + used, out_len - used,
// "{Test ra mode}: [ra] [100] [macid] [mode 0: fixed rate, 1:fixed macidcfg]\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{Fix rate} [ra] [1] [macid] [mode] [giltf] [ss_mcs] [bw])\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{Auto rate}: [ra] [2] [macid] [mode] [giltf] [ss_mcs] [bw]\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"=============Notes=============>\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[mode]: 0:(legacy), 1:(HT), 2:(VHT), 3:(HE)\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[giltf]: 0: (4xHE-LTF 3.2usGI), 1: (4xHE-LTF 0.8usGI), 2: (2xHE-LTF 1.6usGI)\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[giltf]: 3: (2xHE-LTF 0.8usGI), 4: (1xHE-LTF 1.6usGI), 5: (1xHE-LTF 0.8usGI)\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"[ss_mcs]: (Bitmap format) [6:4]: Nsts [3:0]: MCS\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"==============================>\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{Drvier shift rate up/down threshold}: [ra] [3] [macid] [0: Increase th. (Tend to RU) 1: Decrease th (Tend to RD)] [percent]\n");
//BB_DBG_CNSL(out_len, used, output + used, out_len - used,
// "{Fix rate & ra mask}: ra (3 [macid] [mode] [giltf] [ss_mcs] [mask1] [mask0])}\n");
goto out;
}
for (i = 0; i < 8; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
//rssi_len = sizeof(struct bb_h2c_rssi_setting);
//rssi_i = hal_mem_alloc(bb->hal_com, rssi_len);
if (0) { /* Test RA mode */
/*
bb_h2c = (u32 *) &ra_cfg;
ra_cfg.bw_cap = 0;
ra_cfg.mode_ctrl = (u8)val[2];
ra_cfg.is_dis_ra= false;
ra_cfg.macid = (u8)val[1];
ra_cfg.stbc_cap = false;
ra_cfg.ldpc_cap = false;
ra_cfg.en_sgi = false;
ra_cfg.upd_all = true;
ra_cfg.init_rate_lv = 1;
ra_cfg.er_cap = false;
ra_cfg.dcm_cap = false;
ra_cfg.upd_mask = false;
ra_cfg.upd_bw_nss_mask = false;
ra_cfg.giltf = 0;
ra_cfg.ss_num = 1;
for (i = 0; i < 8; i++)
ra_cfg.ramask[i] = 0xff;
BB_DBG(bb, DBG_RA, "RA Register: %x %x %x\n", bb_h2c[0], bb_h2c[1],
bb_h2c[2]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_MACIDCFG, HALBB_H2C_RA, bb_h2c);
*/
} else if (val[0] == 1) {
struct bb_h2c_rssi_setting rssi_i;
u32 *bb_h2c = (u32 *) &rssi_i;
u8 cmdlen = sizeof(struct bb_h2c_rssi_setting);
hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta;
bb_ra = &hal_sta_i->ra_info;
if (bb_ra->ra_registered) {
BB_DBG(bb, DBG_RA, "RA fix rate macid=[%d]\n", (u8)val[1]);
/* Need modify for Nss > 2 */
rssi_a = (hal_sta_i->rssi_stat.rssi_ma_path[0] >> 5) & 0x7f;
if (!bb->hal_com->dbcc_en)
rssi_b = (hal_sta_i->rssi_stat.rssi_ma_path[1] >> 5) & 0x7f;
rssi_i.macid = (u8)val[1];
rssi_i.rssi = rssi_a | BIT(7);
rssi_i.is_fixed_rate = true;
rssi_i.fixed_rate = (u8)val[4];
rssi_i.fixed_giltf = (u8)val[3];
rssi_i.fixed_bw = (u8)val[5];
rssi_i.fixed_rate_md = (u8)val[2];
rssi_i.rsvd2_rssi_b = rssi_b;
rssi_i.endcmd = 1;
bb_ra->fixed_rt_en = rssi_i.is_fixed_rate;
bb_ra->fixed_rt_i.mcs_ss_idx = rssi_i.fixed_rate;
bb_ra->fixed_rt_i.mode = rssi_i.fixed_rate_md;
bb_ra->fixed_rt_i.gi_ltf = rssi_i.fixed_giltf;
bb_ra->fixed_rt_i.bw = rssi_i.fixed_bw;
BB_DBG(bb, DBG_RA, "RA fix rate H2C: %x %x\n", bb_h2c[0], bb_h2c[1]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING, HALBB_H2C_RA, bb_h2c);
} else {
BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n");
}
} else if (val[0] == 2) {
struct bb_h2c_rssi_setting rssi_i;
u32 *bb_h2c = (u32 *) &rssi_i;
u8 cmdlen = sizeof(struct bb_h2c_rssi_setting);
hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta;
bb_ra = &hal_sta_i->ra_info;
if (bb_ra->ra_registered) {
BB_DBG(bb, DBG_RA, "RA auto rate macid=[%d]\n", (u8)val[1]);
/* Need modify for Nss > 2 */
rssi_a = (hal_sta_i->rssi_stat.rssi_ma_path[0] >> 5) & 0x7f;
if (!bb->hal_com->dbcc_en)
rssi_b = (hal_sta_i->rssi_stat.rssi_ma_path[1] >> 5) & 0x7f;
rssi_i.macid = (u8)val[1];
rssi_i.rssi = rssi_a | BIT(7);
rssi_i.is_fixed_rate = false;
rssi_i.rsvd2_rssi_b = rssi_b;
rssi_i.endcmd = 1;
bb_ra->fixed_rt_en = rssi_i.is_fixed_rate;
BB_DBG(bb, DBG_RA, "RA auto rate H2C: %x %x\n", bb_h2c[0], bb_h2c[1]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RSSISETTING, HALBB_H2C_RA, bb_h2c);
} else {
BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n");
}
} else if (val[0] == 3) {
struct bb_h2c_ra_adjust ra_th_i;
u32 *bb_h2c = (u32 *) &ra_th_i;
u8 cmdlen = sizeof(struct bb_h2c_ra_adjust);
hal_sta_i = bb->phl_sta_info[(u8)val[1]]->hal_sta;
bb_ra = &hal_sta_i->ra_info;
if (bb_ra->ra_registered) {
BB_DBG(bb, DBG_RA, "RA adjust th. macid=[%d]\n", (u8)val[1]);
ra_th_i.macid = (u8)val[1];
ra_th_i.drv_shift_en = (u8)val[2] & 0x01;
ra_th_i.drv_shift_value= (u8)val[3] & 0x7f;
BB_DBG(bb, DBG_RA, "RA adjust %s th =[%d]\n",
ra_th_i.drv_shift_en == 0x1 ? "RD": "RU", ra_th_i.drv_shift_value);
BB_DBG(bb, DBG_RA, "RA adjust th H2C: %x %x\n", bb_h2c[0], bb_h2c[1]);
ret_val = halbb_fill_h2c_cmd(bb, cmdlen, RA_H2C_RA_ADJUST, HALBB_H2C_RA, bb_h2c);
} else {
BB_DBG(bb, DBG_RA, "No Link ! RA rssi cmd fail!\n");
}
}
//if (rssi_i)
// hal_mem_free(bb->hal_com, rssi_i, rssi_len);
out:
*_used = used;
*_out_len = out_len;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ra.c
|
C
|
agpl-3.0
| 59,677
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_RA_H_
#define _HALBB_RA_H_
/*@--------------------------[extern] ---------------------------------------*/
extern const u16 bb_phy_rate_table[LEGACY_RATE_NUM + HE_RATE_NUM_4SS];
/*@--------------------------[Define] ---------------------------------------*/
#define VHT_2_HE32_RATE(X) ((((X) << 3) + (X) + 4) >> 3) /*= Round(X * 1.125)*/
#define HE32_2_HE16_RATE(X) ((((X) << 3) + (X) + 4) >> 3) /*= Round(X * 1.125)*/
#define HE32_2_HE08_RATE(X) ((((X) << 4) + ((X) << 1) + (X) + 8) >> 4) /*= Round(X * 1.1875)*/
#define RAMASK_B 0x000000000000000f
#define RAMASK_AG 0x0000000000000ff0
#define RAMASK_BG 0x0000000000000ff5
#define RAMASK_HT_2G 0x00000ffffffff015
#define RAMASK_HT_5G 0x00000ffffffff010
#define RAMASK_VHT_2G 0x000ffffffffff015
#define RAMASK_VHT_5G 0x000ffffffffff010
#define RAMASK_HE_2G 0x0ffffffffffff015
#define RAMASK_HE_5G 0x0ffffffffffff010
#define RAMASK_1SS_HT 0x00000000000fffff
#define RAMASK_2SS_HT 0x00000000ff0fffff
#define RAMASK_3SS_HT 0x00000ff0ff0fffff
#define RAMASK_4SS_HT 0x00ff0ff0ff0fffff
#define RAMASK_1SS_VHT 0x00000000003fffff
#define RAMASK_2SS_VHT 0x00000003ff3fffff
#define RAMASK_3SS_VHT 0x00003ff3ff3fffff
#define RAMASK_4SS_VHT 0x03ff3ff3ff3fffff
#define RAMASK_1SS_HE 0x0000000000ffffff
#define RAMASK_2SS_HE 0x0000000fffffffff
#define RAMASK_3SS_HE 0x0000ffffffffffff
#define RAMASK_4SS_HE 0x0fffffffffffffff
#define MAX_ABG_RATE_NUM 12
#define MAX_NSS_VHT 4
#define MAX_NSS_HT 4
#define MAX_NSS_HE 4
#define STA_NUM_RSSI_CMD PHL_MAX_STA_NUM
#define MASKRATE_AX 0x01ff
#define MASKGILTF_AX 0x0e00
/* WiFi Support Mode */
#define CCK_SUPPORT BIT(0)
#define OFDM_SUPPORT BIT(1)
#define HT_SUPPORT BIT(2)
#define VHT_SUPPORT_TX BIT(3)
#define HE_SUPPORT BIT(4)
#define RA_FLOOR_TABLE_SIZE 7
#define RA_FLOOR_UP_GAP 3
#define MAX_RATE_HE 24
#define MAX_RATE_VHT 40 // 8198F is 4SS
#define MAX_RATE_HT 32
/*@--------------------------[Enum]------------------------------------------*/
/* rate_idx table used in FW*/
enum rate_table {
RATE_CCK_1M = 0x00,
RATE_CCK_2M = 0x01,
RATE_CCK_5M = 0x02,
RATE_CCK_11M = 0x03,
RATE_OFDM_6M = 0x04,
RATE_OFDM_9M = 0x05,
RATE_OFDM_12M = 0x06,
RATE_OFDM_18M = 0x07,
RATE_OFDM_24M = 0x08,
RATE_OFDM_36M = 0x09,
RATE_OFDM_48M = 0x0A,
RATE_OFDM_54M = 0x0B,
RATE_HT_MCS0 = 0x0C,
RATE_HT_MCS1 = 0x0D,
RATE_HT_MCS2 = 0x0E,
RATE_HT_MCS3 = 0x0F,
RATE_HT_MCS4 = 0x10,
RATE_HT_MCS5 = 0x11,
RATE_HT_MCS6 = 0x12,
RATE_HT_MCS7 = 0x13,
RATE_HT_MCS8 = 0x14,
RATE_HT_MCS9 = 0x15,
RATE_HT_MCS10 = 0x16,
RATE_HT_MCS11 = 0x17,
RATE_HT_MCS12 = 0x18,
RATE_HT_MCS13 = 0x19,
RATE_HT_MCS14 = 0x1A,
RATE_HT_MCS15 = 0x1B,
RATE_HT_MCS16 = 0x1C,
RATE_HT_MCS17 = 0x1D,
RATE_HT_MCS18 = 0x1E,
RATE_HT_MCS19 = 0x1F,
RATE_HT_MCS20 = 0x20,
RATE_HT_MCS21 = 0x21,
RATE_HT_MCS22 = 0x22,
RATE_HT_MCS23 = 0x23,
RATE_HT_MCS24 = 0x24,
RATE_HT_MCS25 = 0x25,
RATE_HT_MCS26 = 0x26,
RATE_HT_MCS27 = 0x27,
RATE_HT_MCS28 = 0x28,
RATE_HT_MCS29 = 0x29,
RATE_HT_MCS30 = 0x2A,
RATE_HT_MCS31 = 0x2B,
RATE_VHT1SS_MCS0 = 0x2C,
RATE_VHT1SS_MCS1 = 0x2D,
RATE_VHT1SS_MCS2 = 0x2E,
RATE_VHT1SS_MCS3 = 0x2F,
RATE_VHT1SS_MCS4 = 0x30,
RATE_VHT1SS_MCS5 = 0x31,
RATE_VHT1SS_MCS6 = 0x32,
RATE_VHT1SS_MCS7 = 0x33,
RATE_VHT1SS_MCS8 = 0x34,
RATE_VHT1SS_MCS9 = 0x35,
RATE_VHT2SS_MCS0 = 0x36,
RATE_VHT2SS_MCS1 = 0x37,
RATE_VHT2SS_MCS2 = 0x38,
RATE_VHT2SS_MCS3 = 0x39,
RATE_VHT2SS_MCS4 = 0x3A,
RATE_VHT2SS_MCS5 = 0x3B,
RATE_VHT2SS_MCS6 = 0x3C,
RATE_VHT2SS_MCS7 = 0x3D,
RATE_VHT2SS_MCS8 = 0x3E,
RATE_VHT2SS_MCS9 = 0x3F,
RATE_VHT3SS_MCS0 = 0x40,
RATE_VHT3SS_MCS1 = 0x41,
RATE_VHT3SS_MCS2 = 0x42,
RATE_VHT3SS_MCS3 = 0x43,
RATE_VHT3SS_MCS4 = 0x44,
RATE_VHT3SS_MCS5 = 0x45,
RATE_VHT3SS_MCS6 = 0x46,
RATE_VHT3SS_MCS7 = 0x47,
RATE_VHT3SS_MCS8 = 0x48,
RATE_VHT3SS_MCS9 = 0x49,
RATE_VHT4SS_MCS0 = 0x4A,
RATE_VHT4SS_MCS1 = 0x4B,
RATE_VHT4SS_MCS2 = 0x4C,
RATE_VHT4SS_MCS3 = 0x4D,
RATE_VHT4SS_MCS4 = 0x4E,
RATE_VHT4SS_MCS5 = 0x4F,
RATE_VHT4SS_MCS6 = 0x50,
RATE_VHT4SS_MCS7 = 0x51,
RATE_VHT4SS_MCS8 = 0x52,
RATE_VHT4SS_MCS9 = 0x53,
// HE
RATE_HE1SS_MCS0 = 0x54,
RATE_HE1SS_MCS1 = 0x55,
RATE_HE1SS_MCS2 = 0x56,
RATE_HE1SS_MCS3 = 0x57,
RATE_HE1SS_MCS4 = 0x58,
RATE_HE1SS_MCS5 = 0x59,
RATE_HE1SS_MCS6 = 0x5A,
RATE_HE1SS_MCS7 = 0x5B,
RATE_HE1SS_MCS8 = 0x5C,
RATE_HE1SS_MCS9 = 0x5D,
RATE_HE1SS_MCS10 = 0x5E,
RATE_HE1SS_MCS11 = 0x5F,
RATE_HE2SS_MCS0 = 0x60,
RATE_HE2SS_MCS1 = 0x61,
RATE_HE2SS_MCS2 = 0x62,
RATE_HE2SS_MCS3 = 0x63,
RATE_HE2SS_MCS4 = 0x64,
RATE_HE2SS_MCS5 = 0x65,
RATE_HE2SS_MCS6 = 0x66,
RATE_HE2SS_MCS7 = 0x67,
RATE_HE2SS_MCS8 = 0x68,
RATE_HE2SS_MCS9 = 0x69,
RATE_HE2SS_MCS10 = 0x6A,
RATE_HE2SS_MCS11 = 0x6B,
};
enum spatial_stream_num {
RA_1SS_MODE = 0,
RA_2SS_MODE = 1,
RA_3SS_MODE = 2,
RA_4SS_MODE = 3
};
enum wifi_mode {
RA_CCK = 0,
RA_non_ht = 1,
RA_HT = 2,
RA_VHT = 3,
RA_HE = 4
};
enum mu_cmd_type {
MU_ADD_ENTRY = 0,
MU_DEL_ENTRY = 1,
MU_DBG_CTRL =2,
};
enum bb_opt_gi_ltf {
BB_OPT_GILTF_4XHE08 = 0,
BB_OPT_GILTF_1XHE08 = 1
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_rate_info {
u16 rate_idx_all;
u16 rate_idx;
enum rtw_gi_ltf gi_ltf;
enum bb_mode_type mode; /*0:legacy, 1:HT, 2*/
enum channel_width bw;
u8 ss;
u8 idx;
u8 fw_rate_idx;
};
struct bb_ra_info {
/* Config move to phl_sta_info*/
struct bb_h2c_ra_cfg_info ra_cfg;
u8 cal_giltf;
/* Ctrl */
u8 drv_ractrl;
bool fixed_rate_en;
u8 fixed_rate; /* 7bit rate */
u8 fixed_rat_md; /* 2bit rate_mode */
u8 fixed_giltf; /* 3bit giltf */
u8 fixed_bw; /* 2bit bw */
u8 rssi; /* should not put here */
u8 rainfo_cfg1; /* prepare for other control*/
u8 rainfo_cfg2; /* prepare for other control*/
u8 rssi_lv;
/* Report */
u8 rpt_rate; /* 7bit rate + 2bit rat_md + 3bit giltf + 2bit bw */
u8 rpt_rat_md;
u8 rpt_giltf;
u8 rpt_bw;
u8 rpt_ratio;
u8 tmp;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
bool halbb_is_cck_rate(struct bb_info *bb, u16 rate);
bool halbb_is_ofdm_rate(struct bb_info *bb, u16 rate);
bool halbb_is_ht_rate(struct bb_info *bb, u16 rate);
bool halbb_is_vht_rate(struct bb_info *bb, u16 rate);
bool halbb_is_he_rate(struct bb_info *bb, u16 rate);
u8 halbb_legacy_rate_2_spec_rate(struct bb_info *bb, u16 rate);
u8 halbb_rate_2_rate_digit(struct bb_info *bb, u16 rate);
u8 halbb_get_rx_stream_num(struct bb_info *bb, enum rf_type type);
u8 halbb_rate_type_2_num_ss(struct bb_info *bb, enum halbb_rate_type type);
u8 halbb_rate_to_num_ss(struct bb_info *bb, u16 rate);
void halbb_print_rate_2_buff(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, char *buf, u16 buf_size);
enum bb_qam_type halbb_get_qam_order(struct bb_info *bb, u16 rate_idx);
u8 halbb_rate_order_compute(struct bb_info *bb, u16 rate_idx);
void halbb_ra_watchdog(struct bb_info *bb);
void halbb_ra_init(struct bb_info *bb);
void halbb_ra_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_rate_idx_parsor(struct bb_info *bb, u16 rate_idx, enum rtw_gi_ltf gi_ltf, struct bb_rate_info *ra_i);
u32 halbb_get_fw_ra_rpt(struct bb_info *bb, u16 len, u8 *c2h);
u32 halbb_get_txsts_rpt(struct bb_info *bb, u16 len, u8 *c2h);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ra.h
|
C
|
agpl-3.0
| 8,601
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_RA_B_ENDIAN_H_
#define _HALBB_RA_B_ENDIAN_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_fw_cmac_rpt_info { /*need to translate to big endian*/
/* dword 0 */
u32 rpt_sel: 5;
u32 polluted: 1;
u32 tx_state: 2;
u32 sw_define: 4;
u32 rsvd0: 2;
u32 try_rate: 1;
u32 fix_rate: 1;
u32 macid: 7;
u32 rsvd1: 1;
u32 qsel: 6;
u32 rsvd2: 1;
u32 txop_start: 1;
/* dword 1 */
u32 queue_time: 16;
u32 acc_tx_time: 8;
u32 rsvd3: 5;
u32 bmc: 1;
u32 bitmap_short: 2;
/* dword 2 */
u32 final_rate: 9;
u32 final_gi_ltf: 3;
u32 data_bw: 2;
u32 mu2su: 1;
u32 mu_lmt: 1;
u32 final_rts_rate: 9;
u32 final_rts_gi_ltf: 3;
u32 rts_tx_state: 2;
u32 collision_head: 1;
u32 collision_tail: 1;
/* dword 3 */
u32 total_pkt_num: 8;
u32 data_tx_cnt: 6;
u32 bpri: 1;
u32 bbar: 1;
u32 pkt_ok_num: 8;
u32 rts_tx_count: 6;
u32 rsvd4: 2;
/* dword 4 */
u32 init_rate: 9;
u32 init_gi_ltf: 3;
u32 ppdu_type: 2;
u32 he_tb_ppdu_flag: 1;
u32 ppdu_fst_rpt: 1;
u32 su_txpwr: 6;
u32 rsvd5: 2;
u32 diff_pkt_num: 4;
u32 user_define_ext_l: 4;
/* dword 5 */
u32 user_define: 8;
u32 fw_define: 8;
u32 txpwr_pd: 5;
u32 bsr: 1;
u32 rsvd6: 2;
u32 sr_rx_count: 4;
u32 user_define_ext_h: 4;
};
struct bb_h2c_ra_cfg_info {
u8 bw_cap:2;
u8 mode_ctrl:5;
/*
@ Bit0 : CCK
@ Bit1 : OFDM
@ Bit2 : HT
@ Bit3 : VHT
@ Bit4 : HE
*/
u8 is_dis_ra:1;
u8 macid;
u8 stbc_cap:1;
u8 ldpc_cap:1;
u8 en_sgi:1;
u8 upd_all:1;
u8 init_rate_lv:2;
u8 er_cap:1;
u8 dcm_cap:1;
u8 upd_mask:1;
u8 upd_bw_nss_mask:1;
u8 giltf_cap:3;
u8 ss_num:3;
u8 ramask[8]; /* ramask[7] bit 7 is for indicate bfee csi rate ctrl */
/* BFee CSI rate ctrl */
u8 band_num;
u8 rsvd2:1;
u8 fix_giltf:3;
u8 fix_giltf_en:1;
u8 cr_tbl_sel:1;
u8 fixed_csi_rate_en:1;
u8 ra_csi_rate_en:1;
u8 fixed_csi_rate_l;
u8 fixed_csi_rate_m;
};
struct bb_h2c_rssi_setting {
u8 macid;
u8 rssi;
u8 rainfo1;
u8 rainfo2;
u8 drv_ractrl;
/* RSVD */
u8 fixed_rate:7;
u8 is_fixed_rate:1;
u8 rsvd2_M:1;
u8 fixed_bw:2;
u8 fixed_giltf:3;
u8 fixed_rate_md:2;
u8 endcmd:1;
u8 rsvd2_rssi_b:7;
};
struct bb_h2c_ra_adjust {
u8 macid;
u8 drv_shift_en:1;
u8 drv_shift_value:7;
};
struct bb_h2c_mu_cfg {
u8 cmd_type;
u8 entry;
u8 macid;
u8 rsvd3:6;
u8 en_1024q:1;
u8 en_256q:1;
};
struct halbb_ra_rpt_info {
u8 rpt_macid_l;
u8 rpt_macid_m;
u8 retry_ratio;
u8 rsvd0;
u8 rsvd1: 1;
u8 rpt_mcs_nss: 7;
u8 rsvd2: 1;
u8 rpt_bw: 2;
u8 rpt_gi_ltf: 3;
u8 rpt_md_sel: 2;
u8 rsvd3;
u8 rsvd4;
};
struct halbb_txsts_info {
u8 rpt_macid_l;
u8 rpt_macid_m;
u8 avg_agg;
u8 rsvd0;
u8 tx_ok_be_l;
u8 tx_ok_be_m;
u8 tx_ok_bk_l;
u8 tx_ok_bk_m;
u8 tx_ok_vi_l;
u8 tx_ok_vi_m;
u8 tx_ok_vo_l;
u8 tx_ok_vo_m;
u8 tx_retry_be_l;
u8 tx_retry_be_m;
u8 tx_retry_bk_l;
u8 tx_retry_bk_m;
u8 tx_retry_vi_l;
u8 tx_retry_vi_m;
u8 tx_retry_vo_l;
u8 tx_retry_vo_m;
u8 tx_rate_l;
u8 tx_rate_m;
u8 retry_ratio;
u8 rsvd1;
u8 tx_total_l;
u8 tx_total_m;
u8 rsvd2;
u8 rsvd3;
u8 rsvd4;
u8 rsvd5;
u8 rsvd6;
u8 rsvd7;
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ra_b_endian.h
|
C
|
agpl-3.0
| 3,999
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_RA_EX_H_
#define _HALBB_RA_EX_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
extern bool rtw_halbb_raregistered(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
extern bool rtw_halbb_raupdate(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
extern bool rtw_halbb_dft_mask(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
extern bool rtw_halbb_ra_deregistered(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
extern bool rtw_halbb_query_txsts(struct bb_info *bb, u16 macid0, u16 macid1);
void halbb_drv_cmac_rpt_parsing(struct bb_info *bb, u8 *rpt);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ra_ex.h
|
C
|
agpl-3.0
| 1,543
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_RA_L_ENDIAN_H_
#define _HALBB_RA_L_ENDIAN_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_fw_cmac_rpt_info {
/* dword 0 */
u32 rpt_sel: 5;
u32 polluted: 1;
u32 tx_state: 2;
u32 sw_define: 4;
u32 rsvd0: 2;
u32 try_rate: 1;
u32 fix_rate: 1;
u32 macid: 7;
u32 rsvd1: 1;
u32 qsel: 6;
u32 rsvd2: 1;
u32 txop_start: 1;
/* dword 1 */
u32 queue_time: 16;
u32 acc_tx_time: 8;
u32 rsvd3: 5;
u32 bmc: 1;
u32 bitmap_short: 2;
/* dword 2 */
u32 final_rate: 9;
u32 final_gi_ltf: 3;
u32 data_bw: 2;
u32 mu2su: 1;
u32 mu_lmt: 1;
u32 final_rts_rate: 9;
u32 final_rts_gi_ltf: 3;
u32 rts_tx_state: 2;
u32 collision_head: 1;
u32 collision_tail: 1;
/* dword 3 */
u32 total_pkt_num: 8;
u32 data_tx_cnt: 6;
u32 bpri: 1;
u32 bbar: 1;
u32 pkt_ok_num: 8;
u32 rts_tx_count: 6;
u32 rsvd4: 2;
/* dword 4 */
u32 init_rate: 9;
u32 init_gi_ltf: 3;
u32 ppdu_type: 2;
u32 he_tb_ppdu_flag: 1;
u32 ppdu_fst_rpt: 1;
u32 su_txpwr: 6;
u32 rsvd5: 2;
u32 diff_pkt_num: 4;
u32 user_define_ext_l: 4;
/* dword 5 */
u32 user_define: 8;
u32 fw_define: 8;
u32 txpwr_pd: 5;
u32 bsr: 1;
u32 rsvd6: 2;
u32 sr_rx_count: 4;
u32 user_define_ext_h: 4;
};
struct bb_h2c_ra_cfg_info {
u8 is_dis_ra:1;
u8 mode_ctrl:5;
/*
@ Bit0 : CCK
@ Bit1 : OFDM
@ Bit2 : HT
@ Bit3 : VHT
@ Bit4 : HE
*/
u8 bw_cap:2;
u8 macid;
u8 dcm_cap:1;
u8 er_cap:1;
u8 init_rate_lv:2;
u8 upd_all:1;
u8 en_sgi:1;
u8 ldpc_cap:1;
u8 stbc_cap:1;
u8 ss_num:3;
u8 giltf_cap:3;
u8 upd_bw_nss_mask:1;
u8 upd_mask:1;
u8 ramask[8]; /* ramask[7] bit 7 is for indicate bfee csi rate ctrl */
/* BFee CSI rate ctrl */
u8 band_num;
u8 ra_csi_rate_en:1;
u8 fixed_csi_rate_en:1;
u8 cr_tbl_sel:1;
u8 fix_giltf_en:1;
u8 fix_giltf:3;
u8 rsvd2:1;
u8 fixed_csi_rate_l;
u8 fixed_csi_rate_m;
};
struct bb_h2c_rssi_setting {
u8 macid;
u8 rssi;
u8 rainfo1;
u8 rainfo2;
u8 drv_ractrl;
/* RSVD */
u8 is_fixed_rate:1;
u8 fixed_rate:7;
u8 fixed_rate_md:2;
u8 fixed_giltf:3;
u8 fixed_bw:2;
u8 rsvd2_M:1;
u8 rsvd2_rssi_b:7;
u8 endcmd:1;
};
struct bb_h2c_ra_adjust {
u8 macid;
u8 drv_shift_value:7;
u8 drv_shift_en:1;
};
struct bb_h2c_mu_cfg {
u8 cmd_type;
u8 entry;
u8 macid;
u8 en_256q:1;
u8 en_1024q:1;
u8 rsvd3:6;
};
struct halbb_ra_rpt_info {
u8 rpt_macid_l;
u8 rpt_macid_m;
u8 retry_ratio;
u8 rsvd0;
u8 rpt_mcs_nss: 7;
u8 rsvd1: 1;
u8 rpt_md_sel: 2;
u8 rpt_gi_ltf: 3;
u8 rpt_bw: 2;
u8 rsvd2: 1;
u8 rsvd3;
u8 rsvd4;
};
struct halbb_txsts_info {
u8 rpt_macid_l;
u8 rpt_macid_m;
u8 avg_agg;
u8 rsvd0;
u8 tx_ok_be_l;
u8 tx_ok_be_m;
u8 tx_ok_bk_l;
u8 tx_ok_bk_m;
u8 tx_ok_vi_l;
u8 tx_ok_vi_m;
u8 tx_ok_vo_l;
u8 tx_ok_vo_m;
u8 tx_retry_be_l;
u8 tx_retry_be_m;
u8 tx_retry_bk_l;
u8 tx_retry_bk_m;
u8 tx_retry_vi_l;
u8 tx_retry_vi_m;
u8 tx_retry_vo_l;
u8 tx_retry_vo_m;
u8 tx_rate_l;
u8 tx_rate_m;
u8 retry_ratio;
u8 rsvd1;
u8 tx_total_l;
u8 tx_total_m;
u8 rsvd2;
u8 rsvd3;
u8 rsvd4;
u8 rsvd5;
u8 rsvd6;
u8 rsvd7;
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_ra_l_endian.h
|
C
|
agpl-3.0
| 3,957
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_RUA_SUPPORT
u32 halbb_rua_tbl_hdr_cfg(struct bb_info *bb,
struct rtw_rua_tbl_hdr *rtw_tbl_hdr,
struct halbb_rua_tbl_hdr_info *rua_tbl_hdr)
{
u32 ret = RTW_HAL_STATUS_SUCCESS;
/*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/
BB_DBG(bb, DBG_RUA_TBL, "halbb_rau_tbl_hdr_cfg\n");
rua_tbl_hdr->idx = rtw_tbl_hdr->idx;
rua_tbl_hdr->rw = rtw_tbl_hdr->rw;
rua_tbl_hdr->len_l= (u8)(rtw_tbl_hdr->len&0x0007);
rua_tbl_hdr->len_m= (u8)((rtw_tbl_hdr->len&0x03f8)>>3);
rua_tbl_hdr->offset= (u8)rtw_tbl_hdr->offset;
rua_tbl_hdr->type = (u8)rtw_tbl_hdr->type;
rua_tbl_hdr->tbl_class = rtw_tbl_hdr->tbl_class;
return ret;
}
void halbb_ru_rate_cfg(struct bb_info *bb,
struct rtw_ru_rate_ent *rate_ent,
struct halbb_ru_rate_info *rate_i)
{
BB_DBG(bb, DBG_RUA_TBL, "halbb_ru_rate_cfg\n");
rate_i->dcm = rate_ent->dcm;
rate_i->mcs = rate_ent->mcs;
rate_i->ss = rate_ent->ss;
}
u32 halbb_dlfix_sta_i_ax4ru_cfg(struct bb_info *bb,
struct rtw_dlfix_sta_i_ax4ru *sta_ent,
struct halbb_dl_fix_sta_info *fix_sta_i)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 i;
/*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/
BB_DBG(bb, DBG_RUA_TBL, "halbb_rua_sta_info_cfg\n");
if ((!fix_sta_i) || (!sta_ent)) {
BB_WARNING("halbb_rua_sta_info_cfg: NULL pointer!!\n");
return ret;
}
fix_sta_i->mac_id = sta_ent->mac_id;
for (i = 0; i < 3; i++)
fix_sta_i->ru_pos[i] = sta_ent->ru_pos[i];
fix_sta_i->fix_rate = sta_ent->fix_rate;
fix_sta_i->fix_coding = sta_ent->fix_coding;
fix_sta_i->fix_txbf = sta_ent->fix_txbf;
fix_sta_i->fix_pwr_fac = sta_ent->fix_pwr_fac;
halbb_ru_rate_cfg(bb, &(sta_ent->rate), &(fix_sta_i->rate_i));
fix_sta_i->txbf = sta_ent->txbf;
fix_sta_i->coding = sta_ent->coding;
fix_sta_i->pwr_boost_fac = sta_ent->pwr_boost_fac;
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_ulfix_sta_i_ax4ru_cfg(struct bb_info *bb,
struct rtw_ulfix_sta_i_ax4ru *sta_ent,
struct halbb_ul_fix_sta_info *fix_sta_i)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 i;
/*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/
BB_DBG(bb, DBG_RUA_TBL, "halbb_rua_sta_info_cfg\n");
if ((!fix_sta_i) || (!sta_ent)) {
BB_WARNING("halbb_rua_sta_info_cfg: NULL pointer!!\n");
return ret;
}
fix_sta_i->mac_id = sta_ent->mac_id;
for (i = 0; i < 3; i++) {
fix_sta_i->ru_pos[i] = sta_ent->ru_pos[i];
fix_sta_i->tgt_rssi[i] = sta_ent->tgt_rssi[i];
}
fix_sta_i->fix_tgt_rssi = sta_ent->fix_tgt_rssi;
fix_sta_i->fix_rate = sta_ent->fix_rate;
fix_sta_i->fix_coding = sta_ent->fix_coding;
fix_sta_i->coding = sta_ent->coding;
halbb_ru_rate_cfg(bb, &(sta_ent->rate), &(fix_sta_i->rate_i));
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_tf_ba_tbl_info_cfg(struct bb_info *bb,
struct rtw_tf_ba_tbl *tf_tbl,
struct halbb_tf_ba_tbl_info *tf_i)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
/*struct rtw_rua_tbl *rtw_rua = &bb->rtw_rua_t;*/
BB_DBG(bb, DBG_RUA_TBL, "halbb_rua_sta_info_cfg\n");
if ((!tf_i) || (!tf_tbl)) {
BB_WARNING("halbb_tf_ba_tbl_info_cfg: NULL pointer!!\n");
return ret;
}
tf_i->fix_ba = (u8)tf_tbl->fix_ba;
tf_i->ru_psd_l = (u8)(tf_tbl->ru_psd&0x007f);
tf_i->ru_psd_m = (u8)((tf_tbl->ru_psd&0x0180)>>7);
tf_i->tf_rate_l = (u8)(tf_tbl->tf_rate&0x003f);
tf_i->tf_rate_m = (u8)((tf_tbl->tf_rate&0x01c0)>>6);
tf_i->rf_gain_fix = (u8)tf_tbl->rf_gain_fix;
tf_i->rf_gain_idx_l = (u8)(tf_tbl->rf_gain_idx&0x0000000f);
tf_i->rf_gain_idx_m = (u8)((tf_tbl->rf_gain_idx&0x000003f0)>>4);
tf_i->tb_ppdu_bw = (u8)tf_tbl->tb_ppdu_bw;
halbb_ru_rate_cfg(bb, &(tf_tbl->rate), &(tf_i->rate_i));
tf_i->gi_ltf = tf_tbl->gi_ltf;
tf_i->doppler = tf_tbl->doppler;
tf_i->stbc = tf_tbl->stbc;
tf_i->sta_coding = tf_tbl->sta_coding;
tf_i->tb_t_pe_nom = tf_tbl->tb_t_pe_nom;
tf_i->pr20_bw_en = tf_tbl->pr20_bw_en;
tf_i->ma_type = tf_tbl->ma_type;
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
void halbb_rua_tbl_init(struct bb_info *bb)
{
BB_DBG(bb, DBG_RUA_TBL, "RUA TBL Init\n");
}
u32 halbb_upd_dlru_fixtbl_ax4ru(struct bb_info *bb,
struct rtw_dlru_fixtbl_ax4ru *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 i;
bool ret_v= false;
u8 len = sizeof(struct rtw_dlru_fixtbl_ax4ru);
struct halbb_dl_ru_fix_tbl_info *fix_tbl_i;
u8 pkt_len = sizeof(struct halbb_dl_ru_fix_tbl_info);
u32 *bb_h2c = NULL;
/*u8 *buf;*/
BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_dlru_fixtbl: in_len = %d, out_len = %d\n", len, pkt_len);
//if (len != pkt_len)
// BB_WARNING("halbb_upd_dlru_fixtbl: tble length mismatch!!\n");
fix_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) fix_tbl_i;
info->tbl_hdr.len= sizeof(struct halbb_dl_ru_fix_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = DL_RU_FIX_TBL;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(fix_tbl_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
fix_tbl_i->max_sta_num = info->max_sta_num;
fix_tbl_i->min_sta_num = info->min_sta_num;
fix_tbl_i->doppler = info->doppler;
fix_tbl_i->stbc = info->stbc;
fix_tbl_i->gi_ltf = info->gi_ltf;
fix_tbl_i->ma_type = info->ma_type;
fix_tbl_i->fixru_flag = info->fixru_flag;
fix_tbl_i->rupos_csht_flag = info->rupos_csht_flag;
fix_tbl_i->ru_swp_flg = info->ru_swp_flg;
for (i = 0; i < HALBB_AX4RU_STA_NUM; i++)
halbb_dlfix_sta_i_ax4ru_cfg(bb, &(info->sta[i]), &(fix_tbl_i->sta_i[i]));
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c);
out:
if (fix_tbl_i)
hal_mem_free(bb->hal_com, fix_tbl_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
union rtw_dlru_fixtbl *union_info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
ret = halbb_upd_dlru_fixtbl_ax4ru(bb, &(union_info->ax4ru));
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
ret = halbb_upd_dlru_fixtbl_ax4ru(bb, &(union_info->ax4ru));
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
ret = halbb_upd_dlru_fixtbl_ax4ru(bb, &(union_info->ax4ru));
break;
#endif
default:
ret = RTW_HAL_STATUS_FAILURE;
break;
}
return ret;
}
u32 halbb_upd_ulru_fixtbl_ax4ru(struct bb_info *bb,
struct rtw_ulru_fixtbl_ax4ru *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 i;
bool ret_v= false;
u8 len = sizeof(struct rtw_ulru_fixtbl_ax4ru);
struct halbb_ul_ru_fix_tbl_info *fix_tbl_i;
u8 pkt_len = sizeof(struct halbb_ul_ru_fix_tbl_info);
u32 *bb_h2c = NULL;
/*u8 *buf;*/
BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_ulru_fixtbl: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_upd_ulru_fixtbl: tble length mismatch!!\n");
fix_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) fix_tbl_i;
info->tbl_hdr.len= sizeof(struct halbb_ul_ru_fix_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = UL_RU_FIX_TBL;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(fix_tbl_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
fix_tbl_i->max_sta_num = info->max_sta_num;
fix_tbl_i->min_sta_num = info->min_sta_num;
fix_tbl_i->doppler = info->doppler;
fix_tbl_i->ma_type = info->ma_type;
fix_tbl_i->gi_ltf = info->gi_ltf;
fix_tbl_i->stbc = info->stbc;
fix_tbl_i->fix_tb_t_pe_nom = info->fix_tb_t_pe_nom;
fix_tbl_i->tb_t_pe_nom = info->tb_t_pe_nom;
fix_tbl_i->fixru_flag = info->fixru_flag;
for (i = 0; i < HALBB_AX4RU_STA_NUM; i++)
halbb_ulfix_sta_i_ax4ru_cfg(bb, &(info->sta[i]), &(fix_tbl_i->sta_i[i]));
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c);
out:
if (fix_tbl_i)
hal_mem_free(bb->hal_com, fix_tbl_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
union rtw_ulru_fixtbl *union_info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
switch (bb->ic_type) {
#ifdef BB_8852A_2_SUPPORT
case BB_RTL8852A:
ret = halbb_upd_ulru_fixtbl_ax4ru(bb, &(union_info->ax4ru));
break;
#endif
#ifdef BB_8852B_SUPPORT
case BB_RTL8852B:
ret = halbb_upd_ulru_fixtbl_ax4ru(bb, &(union_info->ax4ru));
break;
#endif
#ifdef BB_8852C_SUPPORT
case BB_RTL8852C:
ret = halbb_upd_ulru_fixtbl_ax4ru(bb, &(union_info->ax4ru));
break;
#endif
default:
ret = RTW_HAL_STATUS_FAILURE;
break;
}
return ret;
}
u32 halbb_upd_dlru_grptbl(struct bb_info *bb,
struct rtw_dl_ru_gp_tbl *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
bool ret_v= false;
u8 len = sizeof(struct rtw_dl_ru_gp_tbl);
struct halbb_dl_ru_gp_tbl_info *gp_tbl_i;
u8 pkt_len = sizeof(struct halbb_dl_ru_gp_tbl_info);
u32 *bb_h2c = NULL;
BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_dlru_grptbl: in_len = %d, out_len = %d\n", len, pkt_len);
//if (len != pkt_len)
// BB_WARNING("halbb_upd_dlru_grptbl: tble length mismatch!!\n");
gp_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c=(u32 *) gp_tbl_i;
info->tbl_hdr.len= sizeof(struct halbb_dl_ru_gp_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = DL_RU_GP_TBL;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(gp_tbl_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
gp_tbl_i->ppdu_bw = (u8)info->ppdu_bw;
gp_tbl_i->tx_pwr_l = (u8)(info->tx_pwr&0x003f);
gp_tbl_i->tx_pwr_m = (u8)((info->tx_pwr&0x01c0)>>6);
gp_tbl_i->pwr_boost_fac = (u8)info->pwr_boost_fac;
gp_tbl_i->fix_mode_flag = info->fix_mode_flag;
ret = halbb_tf_ba_tbl_info_cfg(bb, &(info->tf), &(gp_tbl_i->tf));
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c);
out:
if (gp_tbl_i)
hal_mem_free(bb->hal_com, gp_tbl_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_upd_ulru_grptbl(struct bb_info *bb,
struct rtw_ul_ru_gp_tbl *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
bool ret_v= false;
u8 len = sizeof(struct rtw_ul_ru_gp_tbl);
struct halbb_ul_ru_gp_tbl_info *gp_tbl_i;
u8 pkt_len = sizeof(struct halbb_ul_ru_gp_tbl_info);
u32 *bb_h2c = NULL;
BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_ulru_grptbl: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_upd_ulru_grptbl: tble length mismatch!!\n");
gp_tbl_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) gp_tbl_i;
info->tbl_hdr.len= sizeof(struct halbb_ul_ru_gp_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = UL_RU_GP_TBL;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(gp_tbl_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
gp_tbl_i->grp_psd_max_l = (u8)(info->grp_psd_max&0x00ff);
gp_tbl_i->grp_psd_max_m = (u8)((info->grp_psd_max>>8)&0x0001);
gp_tbl_i->grp_psd_min_l = (u8)(info->grp_psd_min&0x007f);
gp_tbl_i->grp_psd_min_m = (u8)((info->grp_psd_min>>7)&0x0003);
gp_tbl_i->tf_rate_l = (u8)(info->tf_rate&0x003f);
gp_tbl_i->tf_rate_m = (u8)((info->tf_rate>>6)&0x0007);
gp_tbl_i->fix_tf_rate = (u8)info->fix_tf_rate;
gp_tbl_i->ppdu_bw = (u8)info->ppdu_bw;
gp_tbl_i->rf_gain_fix = (u8)info->rf_gain_fix;
gp_tbl_i->rf_gain_idx_l = (u8)(info->rf_gain_idx&0x001f);
gp_tbl_i->rf_gain_idx_m = (u8)((info->rf_gain_idx>>5)&0x001f);
gp_tbl_i->fix_mode_flag = (u8)info->fix_mode_flag;
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c);
out:
if (gp_tbl_i)
hal_mem_free(bb->hal_com, gp_tbl_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_upd_rusta_info(struct bb_info *bb,
struct rtw_ru_sta_info *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_ru_sta_info);
struct halbb_ru_sta_info *ru_sta_i;
u8 pkt_len = sizeof(struct halbb_ru_sta_info);
u32 *bb_h2c = NULL;
u8 i = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_rusta_info: in_len = %d, out_len = %d\n", len, pkt_len);
//if (len != pkt_len)
// BB_WARNING("halbb_upd_rusta_info: tble length mismatch!!\n");
ru_sta_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c=(u32 *) ru_sta_i;
info->tbl_hdr.len = sizeof(struct halbb_ru_sta_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = RU_STA_INFO;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(ru_sta_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
ru_sta_i->gi_ltf_48spt = info->gi_ltf_48spt;
ru_sta_i->gi_ltf_18spt = info->gi_ltf_18spt;
ru_sta_i->dlsu_info_en = info->dlsu_info_en;
ru_sta_i->dlsu_bw = info->dlsu_bw;
ru_sta_i->dlsu_gi_ltf = info->dlsu_gi_ltf;
ru_sta_i->dlsu_doppler_ctrl = info->dlsu_doppler_ctrl;
ru_sta_i->dlsu_coding = info->dlsu_coding;
ru_sta_i->dlsu_txbf = info->dlsu_txbf;
ru_sta_i->dlsu_stbc = info->dlsu_stbc;
ru_sta_i->dl_fwcqi_flag = info->dl_fwcqi_flag;
ru_sta_i->dlru_ratetbl_ridx = info->dlru_ratetbl_ridx;
ru_sta_i->csi_info_bitmap = info->csi_info_bitmap;
for (i = 0; i < 4; i++)
ru_sta_i->dl_swgrp_bitmap[i] = (u8)((info->dl_swgrp_bitmap) >> (i<<3))&0xff;
ru_sta_i->dlsu_dcm = (u8)info->dlsu_dcm;
ru_sta_i->dlsu_rate_l = (u8)(info->dlsu_rate&0x0001);
ru_sta_i->dlsu_rate_m = (u8)((info->dlsu_rate>>1)&0x00ff);
ru_sta_i->dlsu_pwr = info->dlsu_pwr;
ru_sta_i->ulsu_info_en = info->ulsu_info_en;
ru_sta_i->ulsu_bw = info->ulsu_bw;
ru_sta_i->ulsu_gi_ltf = info->ulsu_gi_ltf;
ru_sta_i->ulsu_doppler_ctrl = info->ulsu_doppler_ctrl;
ru_sta_i->ulsu_dcm = info->ulsu_dcm;
ru_sta_i->ulsu_ss = info->ulsu_ss;
ru_sta_i->ulsu_mcs = info->ulsu_mcs;
ru_sta_i->ul_fwcqi_flag = (u8)info->ul_fwcqi_flag;
ru_sta_i->ulru_ratetbl_ridx = (u8)info->ulru_ratetbl_ridx;
ru_sta_i->ulsu_stbc = (u8)info->ulsu_stbc;
ru_sta_i->ulsu_coding = (u8)info->ulsu_coding;
ru_sta_i->ulsu_rssi_m_l = (u8)(info->ulsu_rssi_m&0x0001);
ru_sta_i->ulsu_rssi_m_m = (u8)((info->ulsu_rssi_m>>1)&0x00ff);
for (i = 0; i < 4; i++)
ru_sta_i->ul_swgrp_bitmap[i] = (u8)((info->ul_swgrp_bitmap) >> (i<<3))&0xff;
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c);
out:
if (ru_sta_i)
hal_mem_free(bb->hal_com, ru_sta_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_upd_ba_infotbl(struct bb_info *bb,
struct rtw_ba_tbl_info *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_ba_tbl_info);
struct halbb_ba_tbl_info *ba_i;
u8 pkt_len = sizeof(struct halbb_ba_tbl_info);
u32 *bb_h2c = NULL;
u8 i = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_upd_ba_infotbl: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_upd_ba_infotbl: tble length mismatch!!\n");
ba_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) ba_i;
info->tbl_hdr.len = sizeof(struct halbb_ba_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = BA_INFO_TBL;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(ba_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
ret = halbb_tf_ba_tbl_info_cfg( bb, &(info->tf_ba_t), &(ba_i->tf_i));
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_TABLE, HALBB_H2C_RUA, bb_h2c);
out:
if (ba_i)
hal_mem_free(bb->hal_com, ba_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_swgrp_hdl(struct bb_info *bb, struct rtw_sw_grp_set *info)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_sw_grp_set);
struct halbb_sw_grp_set *swgrp_i;
u8 pkt_len = sizeof(struct halbb_sw_grp_set);
u32 *bb_h2c = NULL;
u8 i,j = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_swgrp_hdl: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_swgrp_hdl: tble length mismatch!!\n");
swgrp_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) swgrp_i;
/*
info->tbl_hdr.len = sizeof(struct halbb_tf_ba_tbl_info)-sizeof(struct halbb_rua_tbl_hdr_info);
info->tbl_hdr.tbl_class = BA_INFO_TBL;
ret = halbb_rua_tbl_hdr_cfg(bb, &(info->tbl_hdr), &(ba_i->tbl_hdr_i));
if (ret == RTW_HAL_STATUS_FAILURE)
goto out;
*/
for (i = 0; i < 8; i++) {
swgrp_i->swgrp_bitmap[i].macid= info->swgrp_bitmap[i].macid;
swgrp_i->swgrp_bitmap[i].en_upd_dl_swgrp = info->swgrp_bitmap[i].en_upd_dl_swgrp;
swgrp_i->swgrp_bitmap[i].en_upd_ul_swgrp = info->swgrp_bitmap[i].en_upd_ul_swgrp;
for (j = 0; j < 4; j++) {
swgrp_i->swgrp_bitmap[i].dl_sw_grp_bitmap[j] = (u8)((info->swgrp_bitmap[i].dl_sw_grp_bitmap) >> (j<<3))&0xff;
swgrp_i->swgrp_bitmap[i].ul_sw_grp_bitmap[j] = (u8)((info->swgrp_bitmap[i].ul_sw_grp_bitmap) >> (j<<3))&0xff;
}
swgrp_i->swgrp_bitmap[i].cmdend= info->swgrp_bitmap[i].cmdend;
if (swgrp_i->swgrp_bitmap[i].cmdend)
break;
}
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_SWGRP, HALBB_H2C_RUA, bb_h2c);
//out:
if (swgrp_i)
hal_mem_free(bb->hal_com, swgrp_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_dl_macid_cfg);
struct dl_macid_cfg *dlmac_i;
u8 pkt_len = sizeof(struct dl_macid_cfg);
u32 *bb_h2c = NULL;
//u8 i,j = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_dlmacid_cfg: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_dlmacid_cfg: tble length mismatch!!\n");
dlmac_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) dlmac_i;
dlmac_i->macid = (u8)cfg->macid;
dlmac_i->dl_su_rate_cfg = (u8)cfg->dl_su_rate_cfg;
dlmac_i->dl_su_rate_l = (u8)(cfg->dl_su_rate & 0x7f);
dlmac_i->dl_su_rate_m= (u8)(cfg->dl_su_rate & 0x180)>>7;
dlmac_i->dl_su_bw = (u8)cfg->dl_su_bw;
dlmac_i->dl_su_pwr_cfg = (u8)cfg->dl_su_pwr_cfg;
dlmac_i->dl_su_pwr_l= (u8)(cfg->dl_su_pwr & 0x7);
dlmac_i->dl_su_pwr_m= (u8)(cfg->dl_su_pwr & 0x38)>>3;
dlmac_i->gi_ltf_4x8_support = (u8)cfg->gi_ltf_4x8_support;
dlmac_i->gi_ltf_1x8_support = (u8)cfg->gi_ltf_1x8_support;
dlmac_i->dl_su_info_en = (u8)cfg->dl_su_info_en;
dlmac_i->dl_su_gi_ltf = (u8)cfg->dl_su_gi_ltf;
dlmac_i->dl_su_doppler_ctrl = (u8)cfg->dl_su_doppler_ctrl;
dlmac_i->dl_su_coding = (u8)cfg->dl_su_coding;
dlmac_i->dl_su_txbf = (u8)cfg->dl_su_txbf;
dlmac_i->dl_su_stbc = (u8)cfg->dl_su_stbc;
dlmac_i->dl_su_dcm = (u8)cfg->dl_su_dcm;
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_DL_MACID, HALBB_H2C_RUA, bb_h2c);
//out:
if (dlmac_i)
hal_mem_free(bb->hal_com, dlmac_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_ul_macid_set);
struct halbb_ul_macid_set *ulmac_i;
u8 pkt_len = sizeof(struct halbb_ul_macid_set);
u32 *bb_h2c = NULL;
u8 i = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_ulmacid_cfg: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_ulmacid_cfg: tble length mismatch!!\n");
ulmac_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) ulmac_i;
for (i = 0; i < 8; i++) {
ulmac_i->ul_macid_cfg[i].macid= (u8)cfg->ul_macid_cfg[i].macid;
ulmac_i->ul_macid_cfg[i].endcmd = (u8)cfg->ul_macid_cfg[i].endcmd;
ulmac_i->ul_macid_cfg[i].ul_su_info_en = (u8)cfg->ul_macid_cfg[i].ul_su_info_en;
ulmac_i->ul_macid_cfg[i].ul_su_bw = (u8)cfg->ul_macid_cfg[i].ul_su_bw;
ulmac_i->ul_macid_cfg[i].ul_su_gi_ltf= (u8)cfg->ul_macid_cfg[i].ul_su_gi_ltf;
ulmac_i->ul_macid_cfg[i].ul_su_doppler_ctrl = (u8)cfg->ul_macid_cfg[i].ul_su_doppler_ctrl;
ulmac_i->ul_macid_cfg[i].ul_su_dcm= (u8)cfg->ul_macid_cfg[i].ul_su_dcm;
ulmac_i->ul_macid_cfg[i].ul_su_ss = (u8)cfg->ul_macid_cfg[i].ul_su_ss;
ulmac_i->ul_macid_cfg[i].ul_su_mcs= (u8)cfg->ul_macid_cfg[i].ul_su_mcs;
ulmac_i->ul_macid_cfg[i].ul_su_coding = (u8)cfg->ul_macid_cfg[i].ul_su_coding;
ulmac_i->ul_macid_cfg[i].ul_su_rssi_m_l= (u8)(cfg->ul_macid_cfg[i].ul_su_rssi_m & 0x1);
ulmac_i->ul_macid_cfg[i].ul_su_rssi_m_m= (u8)(cfg->ul_macid_cfg[i].ul_su_rssi_m & 0x1fe)>>1;
if (ulmac_i->ul_macid_cfg[i].endcmd)
break;
}
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_UL_MACID, HALBB_H2C_RUA, bb_h2c);
//out:
if (ulmac_i)
hal_mem_free(bb->hal_com, ulmac_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_csiinfo_cfg);
struct csiinfo_cfg *csiinfo_i;
u8 pkt_len = sizeof(struct csiinfo_cfg);
u32 *bb_h2c = NULL;
//u8 i,j = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_csiinfo_cfg: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_csiinfo_cfg: tble length mismatch!!\n");
csiinfo_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) csiinfo_i;
csiinfo_i->macid = (u8)cfg->macid;
csiinfo_i->csi_info_bitmap = (u8)cfg->csi_info_bitmap;
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_CSIINFO, HALBB_H2C_RUA, bb_h2c);
//out:
if (csiinfo_i)
hal_mem_free(bb->hal_com, csiinfo_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_cqi_set);
struct halbb_cqi_set *cqi_i;
u8 pkt_len = sizeof(struct halbb_cqi_set);
u32 *bb_h2c = NULL;
u8 i,j = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_ulmacid_cfg: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_ulmacid_cfg: tble length mismatch!!\n");
cqi_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) cqi_i;
for (i = 0; i < 8; i++) {
cqi_i->cqi_info[i].macid= (u8)cfg->cqi_info[i].macid;
cqi_i->cqi_info[i].fw_cqi_flag= (u8)cfg->cqi_info[i].fw_cqi_flag;
cqi_i->cqi_info[i].ru_rate_table_row_idx= (u8)cfg->cqi_info[i].ru_rate_table_row_idx;
cqi_i->cqi_info[i].ul_dl= (u8)cfg->cqi_info[i].ul_dl;
cqi_i->cqi_info[i].endcmd = (u8)cfg->cqi_info[i].endcmd;
for (j=0;j<19;j++)
cqi_i->cqi_info[i].cqi_diff_table[j]= (u8)cfg->cqi_info[i].cqi_diff_table[j];
if (cqi_i->cqi_info[i].endcmd)
break;
}
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_CQI, HALBB_H2C_RUA, bb_h2c);
//out:
if (cqi_i)
hal_mem_free(bb->hal_com, cqi_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_bbinfo_cfg);
struct halbb_bb_info_cfg *bbinfo_i;
u8 pkt_len = sizeof(struct halbb_bb_info_cfg);
u32 *bb_h2c = NULL;
//u8 i,j = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_bbinfo_cfg: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_bbinfo_cfg: tble length mismatch!!\n");
bbinfo_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) bbinfo_i;
bbinfo_i->p20_ch_bitmap = (u8)cfg->p20_ch_bitmap;
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_BBINFO, HALBB_H2C_RUA, bb_h2c);
//out:
if (bbinfo_i)
hal_mem_free(bb->hal_com, bbinfo_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
u32 halbb_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg)
{
u32 ret = RTW_HAL_STATUS_FAILURE;
u8 len = sizeof(struct rtw_pwr_by_rt_tbl);
struct halbb_pwr_by_rt_tbl *pbr_i;
u8 pkt_len = sizeof(struct halbb_pwr_by_rt_tbl);
u32 *bb_h2c = NULL;
u8 i = 0;
bool ret_v = false;
BB_DBG(bb, DBG_RUA_TBL, "halbb_bbinfo_cfg: in_len = %d, out_len = %d\n", len, pkt_len);
// if (len != pkt_len)
// BB_WARNING("halbb_bbinfo_cfg: tble length mismatch!!\n");
pbr_i = hal_mem_alloc(bb->hal_com, pkt_len);
bb_h2c = (u32 *) pbr_i;
for (i=0;i<32;i++){
pbr_i->pwr_by_rt[2*i] = (u8)(cfg->pwr_by_rt[i] & 0xff);
pbr_i->pwr_by_rt[2*i+1] = (u8)((cfg->pwr_by_rt[i] & 0xff00)>>8);
}
BB_DBG(bb, DBG_RUA_TBL, "content %x %x %x \n", *bb_h2c, *(bb_h2c+1), *(bb_h2c+2));
ret_v = halbb_fill_h2c_cmd(bb, pkt_len, RUA_H2C_PWR_TBL, HALBB_H2C_RUA, bb_h2c);
//out:
if (pbr_i)
hal_mem_free(bb->hal_com, pbr_i, pkt_len);
if (ret_v)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
/* For Test mode */
void halbb_test_dlru_gp_tbl(struct bb_info *bb, struct rtw_dl_ru_gp_tbl *tbl)
{
tbl->tbl_hdr.rw = 1; /* write */
tbl->tbl_hdr.idx = 0;
tbl->tbl_hdr.offset = 0;
tbl->tbl_hdr.len = sizeof(struct rtw_dl_ru_gp_tbl);
tbl->tbl_hdr.type = 0;
tbl->ppdu_bw = 2;
tbl->tx_pwr = 0x3c;
tbl->pwr_boost_fac = 0;
tbl->fix_mode_flag = 1;
tbl->tf.fix_ba = 1;
tbl->tf.ru_psd = 20;
tbl->tf.tf_rate = 388;
tbl->tf.rf_gain_fix = 0;
tbl->tf.rf_gain_idx = 0;
tbl->tf.tb_ppdu_bw = 2;
tbl->tf.rate.dcm = 0;
tbl->tf.rate.mcs = 7;
tbl->tf.rate.ss = 0;
tbl->tf.gi_ltf = 2;
tbl->tf.doppler = 0;
tbl->tf.stbc = 0;
tbl->tf.sta_coding = 1;
tbl->tf.tb_t_pe_nom = 2;
tbl->tf.pr20_bw_en = 0;
tbl->tf.ma_type = 0;
}
void halbb_test_dl_sta_ent0(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 0;
sta_ent->ru_pos[0] = 122;
sta_ent->ru_pos[1] = 122;
sta_ent->ru_pos[2] = 122;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->fix_txbf = 1;
sta_ent->fix_pwr_fac = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 11;
sta_ent->rate.ss = 1;
sta_ent->txbf = 0;
sta_ent->coding = 1;
sta_ent->pwr_boost_fac = 0;
}
void halbb_test_dl_sta_ent1(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 1;
sta_ent->ru_pos[0] = 124;
sta_ent->ru_pos[1] = 124;
sta_ent->ru_pos[2] = 124;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->fix_txbf = 1;
sta_ent->fix_pwr_fac = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 10;
sta_ent->rate.ss = 1;
sta_ent->txbf = 0;
sta_ent->coding = 1;
sta_ent->pwr_boost_fac = 0;
}
void halbb_test_dl_sta_ent2(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 2;
sta_ent->ru_pos[0] = 0;
sta_ent->ru_pos[1] = 126;
sta_ent->ru_pos[2] = 126;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->fix_txbf = 1;
sta_ent->fix_pwr_fac = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 9;
sta_ent->rate.ss = 1;
sta_ent->txbf = 0;
sta_ent->coding = 1;
sta_ent->pwr_boost_fac = 0;
}
void halbb_test_dl_sta_ent3(struct bb_info *bb, struct rtw_dlfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 255;
sta_ent->ru_pos[0] = 0;
sta_ent->ru_pos[1] = 0;
sta_ent->ru_pos[2] = 128;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->fix_txbf = 1;
sta_ent->fix_pwr_fac = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 11;
sta_ent->rate.ss = 0;
sta_ent->txbf = 0;
sta_ent->coding = 1;
sta_ent->pwr_boost_fac = 0;
}
void halbb_test_dl_fix_tbl(struct bb_info *bb, struct rtw_dlru_fixtbl_ax4ru *tbl)
{
tbl->tbl_hdr.rw = 1; /* write */
tbl->tbl_hdr.idx = 0;
tbl->tbl_hdr.offset = 0;
tbl->tbl_hdr.len = sizeof(struct rtw_dlru_fixtbl_ax4ru);
tbl->tbl_hdr.type = 0;
/* Need finish */
tbl->max_sta_num = 4;
tbl->min_sta_num = 2;
tbl->doppler = 0;
tbl->stbc = 0;
tbl->gi_ltf = 3;
tbl->ma_type = 0;
tbl->fixru_flag = 1;
halbb_test_dl_sta_ent0(bb, &(tbl->sta[0]));
halbb_test_dl_sta_ent1(bb, &(tbl->sta[1]));
halbb_test_dl_sta_ent2(bb, &(tbl->sta[2]));
halbb_test_dl_sta_ent3(bb, &(tbl->sta[3]));
}
void halbb_test_ru_sta_info(struct bb_info *bb, struct rtw_ru_sta_info *tbl)
{
tbl->tbl_hdr.rw = 1; /* write */
tbl->tbl_hdr.idx = 0;
tbl->tbl_hdr.offset = 0;
tbl->tbl_hdr.len = sizeof(struct rtw_ru_sta_info);
tbl->tbl_hdr.type = 0;
tbl->gi_ltf_18spt = 0;
tbl->gi_ltf_48spt = 0;
tbl->dlsu_info_en = 1;
tbl->dlsu_bw = 2;
tbl->dlsu_gi_ltf = 2;
tbl->dlsu_doppler_ctrl = 0;
tbl->dlsu_coding = 1;
tbl->dlsu_txbf = 0;
tbl->dlsu_stbc = 0;
tbl->dl_fwcqi_flag = 0;
tbl->dlru_ratetbl_ridx = 12;
tbl->csi_info_bitmap = 0;
tbl->dl_swgrp_bitmap = 1;
tbl->dlsu_dcm = 0;
tbl->dlsu_rate = 390;
tbl->dlsu_pwr = 25;
tbl->ulsu_info_en = 1;
tbl->ulsu_bw = 2;
tbl->ulsu_gi_ltf = 3;
tbl->ulsu_doppler_ctrl = 0;
tbl->ulsu_dcm = 0;
tbl->ulsu_ss = 0;
tbl->ulsu_mcs = 7;
tbl->ul_fwcqi_flag = 1;
tbl->ulru_ratetbl_ridx = 13;
tbl->ulsu_stbc = 0;
tbl->ulsu_coding = 1;
tbl->ulsu_rssi_m = 200;
tbl->ul_swgrp_bitmap = 2;
}
void halbb_test_ul_sta_ent0(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 0;
sta_ent->ru_pos[0] = 122;
sta_ent->ru_pos[1] = 122;
sta_ent->ru_pos[2] = 122;
sta_ent->fix_tgt_rssi=1;
sta_ent->tgt_rssi[0] = 115;
sta_ent->tgt_rssi[1] = 110;
sta_ent->tgt_rssi[2] = 105;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 11;
sta_ent->rate.ss = 1;
sta_ent->coding = 1;
}
void halbb_test_ul_sta_ent1(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 1;
sta_ent->ru_pos[0] = 124;
sta_ent->ru_pos[1] = 124;
sta_ent->ru_pos[2] = 124;
sta_ent->fix_tgt_rssi=1;
sta_ent->tgt_rssi[0] = 115;
sta_ent->tgt_rssi[1] = 110;
sta_ent->tgt_rssi[2] = 105;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 11;
sta_ent->rate.ss = 1;
sta_ent->coding = 1;
}
void halbb_test_ul_sta_ent2(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 255;
sta_ent->ru_pos[0] = 0;
sta_ent->ru_pos[1] = 126;
sta_ent->ru_pos[2] = 126;
sta_ent->fix_tgt_rssi=1;
sta_ent->tgt_rssi[0] = 0;
sta_ent->tgt_rssi[1] = 110;
sta_ent->tgt_rssi[2] = 105;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 11;
sta_ent->rate.ss = 1;
sta_ent->coding = 1;
}
void halbb_test_ul_sta_ent3(struct bb_info *bb, struct rtw_ulfix_sta_i_ax4ru *sta_ent)
{
sta_ent->mac_id = 255;
sta_ent->ru_pos[0] = 0;
sta_ent->ru_pos[1] = 0;
sta_ent->ru_pos[2] = 128;
sta_ent->fix_tgt_rssi=1;
sta_ent->tgt_rssi[0] = 0;
sta_ent->tgt_rssi[1] = 0;
sta_ent->tgt_rssi[2] = 105;
sta_ent->fix_rate = 1;
sta_ent->fix_coding = 1;
sta_ent->rate.dcm = 0;
sta_ent->rate.mcs = 11;
sta_ent->rate.ss = 1;
sta_ent->coding = 1;
}
void halbb_test_ul_fix_tbl(struct bb_info *bb, struct rtw_ulru_fixtbl_ax4ru *tbl)
{
tbl->tbl_hdr.rw = 1; /* write */
tbl->tbl_hdr.idx = 0;
tbl->tbl_hdr.offset = 0;
tbl->tbl_hdr.type = 0;
/* Need finish */
tbl->max_sta_num = 4;
tbl->min_sta_num = 2;
tbl->doppler = 0;
tbl->stbc = 0;
tbl->gi_ltf = 2;
tbl->ma_type = 0;
tbl->fix_tb_t_pe_nom=1;
tbl->tb_t_pe_nom=2;
tbl->fixru_flag = 1;
halbb_test_ul_sta_ent0(bb, &(tbl->sta[0]));
halbb_test_ul_sta_ent1(bb, &(tbl->sta[1]));
halbb_test_ul_sta_ent2(bb, &(tbl->sta[2]));
halbb_test_ul_sta_ent3(bb, &(tbl->sta[3]));
}
void halbb_test_ulru_gp_tbl(struct bb_info *bb, struct rtw_ul_ru_gp_tbl *tbl)
{
tbl->tbl_hdr.rw = 1; /* write */
tbl->tbl_hdr.idx = 0;
tbl->tbl_hdr.offset = 0;
tbl->tbl_hdr.type = 0;
tbl->grp_psd_max = 100;
tbl->grp_psd_min = 80;
tbl->ppdu_bw = 2;
tbl->tf_rate = 390;
tbl->fix_tf_rate = 1;
tbl->rf_gain_fix = 0;
tbl->rf_gain_idx = 0;
tbl->fix_mode_flag= 1;
}
void halbb_test_ba_tbl(struct bb_info *bb, struct rtw_ba_tbl_info *tbl)
{
tbl->tbl_hdr.rw = 1;
tbl->tbl_hdr.idx = 0;
tbl->tbl_hdr.offset = 0;
tbl->tbl_hdr.len = sizeof(struct rtw_ba_tbl_info);
tbl->tbl_hdr.type = 0;
tbl->tf_ba_t.fix_ba = 1;
tbl->tf_ba_t.ru_psd = 20;
tbl->tf_ba_t.tf_rate = 388;
tbl->tf_ba_t.rf_gain_fix = 0;
tbl->tf_ba_t.rf_gain_idx = 0;
tbl->tf_ba_t.tb_ppdu_bw = 2;
tbl->tf_ba_t.rate.dcm = 0;
tbl->tf_ba_t.rate.mcs = 7;
tbl->tf_ba_t.rate.ss = 0;
tbl->tf_ba_t.gi_ltf = 2;
tbl->tf_ba_t.doppler = 0;
tbl->tf_ba_t.stbc = 0;
tbl->tf_ba_t.sta_coding = 1;
tbl->tf_ba_t.tb_t_pe_nom = 2;
tbl->tf_ba_t.pr20_bw_en = 0;
tbl->tf_ba_t.ma_type = 0;
}
void halbb_test_swgrp_hdl(struct bb_info *bb, struct rtw_sw_grp_set *hdl)
{
hdl->swgrp_bitmap[0].macid = 3;
hdl->swgrp_bitmap[0].en_upd_dl_swgrp = 1;
hdl->swgrp_bitmap[0].en_upd_ul_swgrp = 0;
hdl->swgrp_bitmap[0].dl_sw_grp_bitmap = 92;
hdl->swgrp_bitmap[0].ul_sw_grp_bitmap = 5;
hdl->swgrp_bitmap[0].cmdend = 0;
hdl->swgrp_bitmap[1].macid = 7;
hdl->swgrp_bitmap[1].en_upd_dl_swgrp = 0;
hdl->swgrp_bitmap[1].en_upd_ul_swgrp = 1;
hdl->swgrp_bitmap[1].dl_sw_grp_bitmap = 99;
hdl->swgrp_bitmap[1].ul_sw_grp_bitmap = 58;
hdl->swgrp_bitmap[1].cmdend = 1;
}
void halbb_test_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg)
{
cfg->macid = 5;
cfg->dl_su_rate_cfg = 1;
cfg->dl_su_rate = 3;
cfg->dl_su_bw = 2;
cfg->dl_su_pwr_cfg = 1;
cfg->dl_su_pwr = 15;
cfg->gi_ltf_4x8_support = 1;
cfg->gi_ltf_1x8_support = 0;
cfg->dl_su_info_en = 1;
cfg->dl_su_gi_ltf = 3;
cfg->dl_su_doppler_ctrl = 2;
cfg->dl_su_coding = 1;
cfg->dl_su_txbf = 0;
cfg->dl_su_stbc = 0;
cfg->dl_su_dcm = 0;
}
void halbb_test_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg)
{
cfg->ul_macid_cfg[0].macid = 5;
cfg->ul_macid_cfg[0].endcmd = 0;
cfg->ul_macid_cfg[0].ul_su_info_en = 1;
cfg->ul_macid_cfg[0].ul_su_bw = 0;
cfg->ul_macid_cfg[0].ul_su_gi_ltf = 1;
cfg->ul_macid_cfg[0].ul_su_doppler_ctrl = 0;
cfg->ul_macid_cfg[0].ul_su_dcm = 1;
cfg->ul_macid_cfg[0].ul_su_ss = 2;
cfg->ul_macid_cfg[0].ul_su_mcs = 7;
cfg->ul_macid_cfg[0].ul_su_stbc = 0;
cfg->ul_macid_cfg[0].ul_su_coding = 1;
cfg->ul_macid_cfg[0].ul_su_rssi_m = 100;
cfg->ul_macid_cfg[1].macid = 3;
cfg->ul_macid_cfg[1].endcmd = 0;
cfg->ul_macid_cfg[1].ul_su_info_en = 1;
cfg->ul_macid_cfg[1].ul_su_bw = 0;
cfg->ul_macid_cfg[1].ul_su_gi_ltf = 2;
cfg->ul_macid_cfg[1].ul_su_doppler_ctrl = 0;
cfg->ul_macid_cfg[1].ul_su_dcm = 1;
cfg->ul_macid_cfg[1].ul_su_ss = 2;
cfg->ul_macid_cfg[1].ul_su_mcs = 8;
cfg->ul_macid_cfg[1].ul_su_stbc = 0;
cfg->ul_macid_cfg[1].ul_su_coding = 1;
cfg->ul_macid_cfg[1].ul_su_rssi_m = 101;
cfg->ul_macid_cfg[2].macid = 6;
cfg->ul_macid_cfg[2].endcmd = 1;
cfg->ul_macid_cfg[2].ul_su_info_en = 1;
cfg->ul_macid_cfg[2].ul_su_bw = 0;
cfg->ul_macid_cfg[2].ul_su_gi_ltf = 3;
cfg->ul_macid_cfg[2].ul_su_doppler_ctrl = 0;
cfg->ul_macid_cfg[2].ul_su_dcm = 1;
cfg->ul_macid_cfg[2].ul_su_ss = 2;
cfg->ul_macid_cfg[2].ul_su_mcs = 9;
cfg->ul_macid_cfg[2].ul_su_stbc = 0;
cfg->ul_macid_cfg[2].ul_su_coding = 1;
cfg->ul_macid_cfg[2].ul_su_rssi_m = 102;
}
void halbb_test_sta_modify(struct bb_info *bb, struct rtw_dlru_fixtbl_ax4ru *fix_tbl, u8 mcs, u8 ss)
{
fix_tbl->max_sta_num = 2;
fix_tbl->min_sta_num = 2;
fix_tbl->doppler=0;
fix_tbl->stbc=0;
fix_tbl->gi_ltf=0;
fix_tbl->ma_type=0;
fix_tbl->fixru_flag = true;
fix_tbl->sta[0].mac_id=2;
fix_tbl->sta[0].ru_pos[0]=130;
fix_tbl->sta[0].ru_pos[1]=122;
fix_tbl->sta[0].ru_pos[2]=122;
fix_tbl->sta[0].fix_rate=1;
fix_tbl->sta[0].rate.mcs=mcs;
fix_tbl->sta[0].rate.ss=ss;
fix_tbl->sta[0].rate.dcm=0;
fix_tbl->sta[0].fix_coding=1;
fix_tbl->sta[0].coding=1;
fix_tbl->sta[0].fix_txbf=1;
fix_tbl->sta[0].txbf=0;
fix_tbl->sta[0].fix_pwr_fac=1;
fix_tbl->sta[0].pwr_boost_fac=0;
fix_tbl->sta[1].mac_id=3;
fix_tbl->sta[1].ru_pos[0]=132;
fix_tbl->sta[1].ru_pos[1]=124;
fix_tbl->sta[1].ru_pos[2]=124;
fix_tbl->sta[1].fix_rate=1;
fix_tbl->sta[1].rate.mcs=mcs;
fix_tbl->sta[1].rate.ss=ss;
fix_tbl->sta[1].rate.dcm=0;
fix_tbl->sta[1].fix_coding=1;
fix_tbl->sta[1].coding=1;
fix_tbl->sta[1].fix_txbf=1;
fix_tbl->sta[1].txbf=0;
fix_tbl->sta[1].fix_pwr_fac=1;
fix_tbl->sta[1].pwr_boost_fac=0;
fix_tbl->sta[2].mac_id=4;
fix_tbl->sta[2].ru_pos[0]=0;
fix_tbl->sta[2].ru_pos[1]=126;
fix_tbl->sta[2].ru_pos[2]=126;
fix_tbl->sta[2].fix_rate=1;
fix_tbl->sta[2].rate.mcs=mcs;
fix_tbl->sta[2].rate.ss=ss;
fix_tbl->sta[2].rate.dcm=0;
fix_tbl->sta[2].fix_coding=1;
fix_tbl->sta[2].coding=1;
fix_tbl->sta[2].fix_txbf=1;
fix_tbl->sta[2].txbf=0;
fix_tbl->sta[2].fix_pwr_fac=1;
fix_tbl->sta[2].pwr_boost_fac=0;
fix_tbl->sta[3].mac_id=5;
fix_tbl->sta[3].ru_pos[0]=0;
fix_tbl->sta[3].ru_pos[1]=0;
fix_tbl->sta[3].ru_pos[2]=128;
fix_tbl->sta[3].fix_rate=1;
fix_tbl->sta[3].rate.mcs=mcs;
fix_tbl->sta[3].rate.ss=ss;
fix_tbl->sta[3].rate.dcm=0;
fix_tbl->sta[3].fix_coding=1;
fix_tbl->sta[3].coding=1;
fix_tbl->sta[3].fix_txbf=1;
fix_tbl->sta[3].txbf=0;
fix_tbl->sta[3].fix_pwr_fac=1;
fix_tbl->sta[3].pwr_boost_fac=0;
}
void halbb_test_grppwr_modify(struct bb_info *bb, struct rtw_dl_ru_gp_tbl *tbl, u8 grp_pwr)
{
tbl->ppdu_bw = CHANNEL_WIDTH_80;
tbl->tx_pwr = grp_pwr; /*TODO:get from bb api*/
tbl->pwr_boost_fac = 0;/*TODO:get from bb api*/
tbl->fix_mode_flag = 1;
/* Trigger BA settings */
tbl->tf.tf_rate = RTW_DATA_RATE_OFDM24;
tbl->tf.tb_ppdu_bw = CHANNEL_WIDTH_80;
tbl->tf.rate.dcm = 0;
tbl->tf.rate.mcs = 3;
tbl->tf.rate.ss = 0;
tbl->tf.fix_ba = 0;
tbl->tf.ru_psd = 20;/*TODO:get from bb api*/
tbl->tf.rf_gain_fix = 0;/*TODO:get from bb api*/
tbl->tf.rf_gain_idx = 0;/*TODO:get from bb api*/
tbl->tf.gi_ltf = RTW_GILTF_2XHE16;
tbl->tf.doppler = 0;
tbl->tf.stbc = 0;
tbl->tf.sta_coding = 0;
tbl->tf.tb_t_pe_nom = 2;
tbl->tf.pr20_bw_en = 0;
tbl->tf.ma_type = 0;
}
void halbb_test_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg)
{
cfg->macid = 5;
cfg->csi_info_bitmap= 99;
}
void halbb_test_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg)
{
u8 i;
cfg->cqi_info[0].macid = 5;
cfg->cqi_info[0].fw_cqi_flag= 1;
cfg->cqi_info[0].ru_rate_table_row_idx= 4;
cfg->cqi_info[0].ul_dl= 0;
cfg->cqi_info[0].endcmd= 0;
for (i=10;i<29;i++)
cfg->cqi_info[0].cqi_diff_table[i-10]= i;
cfg->cqi_info[1].macid = 3;
cfg->cqi_info[1].fw_cqi_flag= 1;
cfg->cqi_info[1].ru_rate_table_row_idx= 2;
cfg->cqi_info[1].ul_dl= 1;
cfg->cqi_info[1].endcmd= 0;
for (i=20;i<39;i++)
cfg->cqi_info[1].cqi_diff_table[i-20]= i;
cfg->cqi_info[2].macid = 1;
cfg->cqi_info[2].fw_cqi_flag= 1;
cfg->cqi_info[2].ru_rate_table_row_idx= 0;
cfg->cqi_info[2].ul_dl= 0;
cfg->cqi_info[2].endcmd= 0;
for (i=30;i<49;i++)
cfg->cqi_info[2].cqi_diff_table[i-30]= i-40;
cfg->cqi_info[3].macid = 7;
cfg->cqi_info[3].fw_cqi_flag= 1;
cfg->cqi_info[3].ru_rate_table_row_idx= 6;
cfg->cqi_info[3].ul_dl= 0;
cfg->cqi_info[3].endcmd= 1;
for (i=40;i<59;i++)
cfg->cqi_info[3].cqi_diff_table[i-40]= i-60;
}
void halbb_test_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg)
{
cfg->p20_ch_bitmap= 168;
}
void halbb_test_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg)
{ u8 i;
for (i=0;i<32;i++)
cfg->pwr_by_rt[i]= -200 + i*10;
}
u32 halbb_set_rua_tbl(struct bb_info *bb, u8 rua_tbl_idx)
{
u32 ret = 0;
struct rtw_dl_ru_gp_tbl dl_ru_gp_t = {{0}};
struct rtw_ul_ru_gp_tbl ul_ru_gp_t = {{0}};
struct rtw_ru_sta_info ru_sta_i = {{0}};
struct rtw_dlru_fixtbl_ax4ru dl_ru_fix_t = {{0}};
struct rtw_ulru_fixtbl_ax4ru ul_ru_fix_t = {{0}};
struct rtw_ba_tbl_info ba_tbl_i = {{0}};
BB_DBG(bb, DBG_RUA_TBL, "SET RUA TBL (%d)\n", rua_tbl_idx);
switch(rua_tbl_idx) {
case DL_RU_GP_TBL:
halbb_test_dlru_gp_tbl(bb, &dl_ru_gp_t);
halbb_upd_dlru_grptbl(bb, &dl_ru_gp_t);
break;
case UL_RU_GP_TBL:
halbb_test_ulru_gp_tbl(bb, &ul_ru_gp_t);
halbb_upd_ulru_grptbl(bb, &ul_ru_gp_t);
break;
case RU_STA_INFO:
halbb_test_ru_sta_info(bb, &ru_sta_i);
halbb_upd_rusta_info(bb, &ru_sta_i);
break;
case DL_RU_FIX_TBL:
halbb_test_dl_fix_tbl(bb, &dl_ru_fix_t);
halbb_upd_dlru_fixtbl_ax4ru(bb, &dl_ru_fix_t);//shall be revised
break;
case UL_RU_FIX_TBL:
halbb_test_ul_fix_tbl(bb, &ul_ru_fix_t);
halbb_upd_ulru_fixtbl_ax4ru(bb, &ul_ru_fix_t);//shall be revised
break;
case BA_INFO_TBL:
halbb_test_ba_tbl(bb, &ba_tbl_i);
halbb_upd_ba_infotbl(bb, &ba_tbl_i);
break;
default:
break;
}
return ret;
}
u32 halbb_set_rua_cfg(struct bb_info *bb, u8 rua_cfg_idx)
{
u32 ret = 0;
struct rtw_sw_grp_set swgrp_hdl;
struct rtw_dl_macid_cfg dlmacid_cfg;
struct rtw_ul_macid_set ulmacid_cfg;
struct rtw_csiinfo_cfg csiinfo_cfg;
struct rtw_cqi_set cqi_info;
struct rtw_bbinfo_cfg bbinfo_cfg;
struct rtw_pwr_by_rt_tbl pbr_tbl;
halbb_mem_set(bb, &swgrp_hdl, 0, sizeof(swgrp_hdl));
halbb_mem_set(bb, &dlmacid_cfg, 0, sizeof(dlmacid_cfg));
halbb_mem_set(bb, &ulmacid_cfg, 0, sizeof(ulmacid_cfg));
halbb_mem_set(bb, &csiinfo_cfg, 0, sizeof(csiinfo_cfg));
halbb_mem_set(bb, &cqi_info, 0, sizeof(cqi_info));
halbb_mem_set(bb, &bbinfo_cfg, 0, sizeof(bbinfo_cfg));
halbb_mem_set(bb, &pbr_tbl, 0, sizeof(pbr_tbl));
BB_DBG(bb, DBG_RUA_TBL, "SET RUA TBL (%d)\n", rua_cfg_idx);
switch(rua_cfg_idx) {
case SW_GRP_HDL:
halbb_test_swgrp_hdl(bb, &swgrp_hdl);
halbb_swgrp_hdl(bb, &swgrp_hdl);
break;
case DL_MACID_CFG:
halbb_test_dlmacid_cfg(bb, &dlmacid_cfg);
halbb_dlmacid_cfg(bb, &dlmacid_cfg);
break;
case UL_MACID_CFG:
halbb_test_ulmacid_cfg(bb, &ulmacid_cfg);
halbb_ulmacid_cfg(bb, &ulmacid_cfg);
break;
case CSI_INFO_CFG:
halbb_test_csiinfo_cfg(bb, &csiinfo_cfg);
halbb_csiinfo_cfg(bb, &csiinfo_cfg);
break;
case CQI_CFG:
halbb_test_cqi_cfg(bb, &cqi_info);
halbb_cqi_cfg(bb, &cqi_info);
break;
case BB_INFO_CFG:
halbb_test_bbinfo_cfg(bb, &bbinfo_cfg);
halbb_bbinfo_cfg(bb, &bbinfo_cfg);
break;
case PWR_TBL_init:
halbb_test_pbr_tbl_cfg(bb, &pbr_tbl);
halbb_pbr_tbl_cfg(bb, &pbr_tbl);
break;
default:
break;
}
return ret;
}
u32 halbb_set_rua_sta_rate_ss(struct bb_info *bb, u8 hdr_type, u8 ent, u8 mcs, u8 ss)
{
u32 ret = 0;
//struct rtw_dlru_fixtbl_ax4ru dl_ru_fix_t;
union rtw_dlru_fixtbl dl_ru_fix_t;
halbb_mem_set(bb, &dl_ru_fix_t,0,sizeof(dl_ru_fix_t));
BB_DBG(bb, DBG_RUA_TBL, "SET DL FIX RUA TBL with sta_info change\n");
BB_DBG(bb, DBG_RUA_TBL, "hdr_type: %d, ent: %d, mcs: %d ,ss: %d\n", hdr_type, ent, mcs, ss);
dl_ru_fix_t.ax4ru.tbl_hdr.rw = 1; /* write */
dl_ru_fix_t.ax4ru.tbl_hdr.idx = ent;
dl_ru_fix_t.ax4ru.tbl_hdr.offset = 0;
dl_ru_fix_t.ax4ru.tbl_hdr.len = sizeof(struct rtw_dlru_fixtbl_ax4ru);
dl_ru_fix_t.ax4ru.tbl_hdr.type = hdr_type;
halbb_test_sta_modify(bb, &dl_ru_fix_t.ax4ru, mcs, ss);
ret = halbb_upd_dlru_fixtbl(bb, &dl_ru_fix_t);
return ret;
}
u32 halbb_set_rua_grp_pwr(struct bb_info *bb, u8 hdr_type, u8 ent, u8 grp_pwr)
{
u32 ret = 0;
struct rtw_dl_ru_gp_tbl dl_ru_gp_t = {0};
BB_DBG(bb, DBG_RUA_TBL, "SET DL GRP RUA TBL with grp_pwr change\n");
BB_DBG(bb, DBG_RUA_TBL, "hdr_type: %d, ent: %d, grp_pwr: %d\n", hdr_type, ent, grp_pwr);
dl_ru_gp_t.tbl_hdr.rw = 1; /* write */
dl_ru_gp_t.tbl_hdr.idx = ent;
dl_ru_gp_t.tbl_hdr.offset = 0;
dl_ru_gp_t.tbl_hdr.len = sizeof(struct rtw_dl_ru_gp_tbl);
dl_ru_gp_t.tbl_hdr.type = hdr_type;
halbb_test_grppwr_modify(bb, &dl_ru_gp_t, grp_pwr);
ret = halbb_upd_dlru_grptbl(bb, &dl_ru_gp_t);
return ret;
}
void halbb_rua_tbl_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char help[] = "-h";
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i;
if (_os_strcmp(input[1], help) == 0) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (0 [dlru_grptbl])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (1 [ulru_grptbl])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (2 [rusta_info])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (3 [dlru_fixtbl])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (4 [ulru_fixtbl])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (5 [ba_infotbl])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 0 [SW_GRP_HDL])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 1 [DL_MACID_CFG])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 2 [UL_MACID_CFG])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 3 [CSI_INFO_CFG])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 4 [CQI_CFG])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 5 [BB_INFO_CFG])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (6 6 [PWR_TBL_init])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (7 1:hw,0:sw ent mcs ss [dlru_fixtbl with sta_info change])}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rua (8 1:hw,0:sw ent grp_pwr [dlru_fixtbl with grp_pwr change])}\n");
goto out;
}
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALBB_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
if (val[0] < 6)
halbb_set_rua_tbl(bb, (u8)val[0]);
else if(val[0] == 6 )
halbb_set_rua_cfg(bb, (u8)val[1]);
else if(val[0] == 7 )
halbb_set_rua_sta_rate_ss(bb, (u8)val[1],(u8)val[2],(u8)val[3],(u8)val[4]);
else
halbb_set_rua_grp_pwr(bb, (u8)val[1],(u8)val[2],(u8)val[3]);
out:
*_used = used;
*_out_len = out_len;
}
#endif /* HALBB_RUA_SUPPORT */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_rua_tbl.c
|
C
|
agpl-3.0
| 46,469
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_RUA_TBL_H__
#define __HALBB_RUA_TBL_H__
#ifdef HALBB_RUA_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*[IO Reg]*/
/*@--------------------------[Enum]------------------------------------------*/
enum rua_tbl_sel {
DL_RU_GP_TBL = 0x0,
UL_RU_GP_TBL = 0x1,
RU_STA_INFO = 0x2,
DL_RU_FIX_TBL = 0x3,
UL_RU_FIX_TBL = 0x4,
BA_INFO_TBL = 0x5
};
enum rua_cfg_sel {
SW_GRP_HDL = 0x0,
DL_MACID_CFG = 0x1,
UL_MACID_CFG = 0x2,
CSI_INFO_CFG = 0x3,
CQI_CFG = 0x4,
BB_INFO_CFG = 0x5,
PWR_TBL_init = 0x6
};
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_rua_tbl_init(struct bb_info *bb);
void halbb_rua_tbl_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif /* HALBB_RUA_SUPPORT */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_rua_tbl.h
|
C
|
agpl-3.0
| 1,919
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_RUA_TBL_B_ENDIAN_H__
#define __HALBB_RUA_TBL_B_ENDIAN_H__
#ifdef HALBB_RUA_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*[IO Reg]*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_rua_tbl_hdr_info {
u8 idx:7;
u8 rw:1;
u8 len_l:3;
u8 offset:5;
u8 type:1;
u8 len_m:7;
u8 tbl_class;
};
struct halbb_ru_rate_info {
u8 mcs:4;
u8 ss:3;
u8 dcm:1;
};
struct halbb_tf_ba_tbl_info {
u8 ru_psd_l:7;
u8 fix_ba:1;
u8 tf_rate_l:6;
u8 ru_psd_m:2;
u8 rf_gain_idx_l:4;
u8 rf_gain_fix:1;
u8 tf_rate_m:3;
u8 tb_ppdu_bw:2;
u8 rf_gain_idx_m:6;
struct halbb_ru_rate_info rate_i;
u8 tb_t_pe_nom:2;
u8 sta_coding:1;
u8 stbc:1;
u8 doppler:1;
u8 gi_ltf:3;
u8 rsvd1: 6;
u8 ma_type: 1;
u8 pr20_bw_en:1;
};
struct halbb_dl_ru_gp_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 tx_pwr_l:6;
u8 ppdu_bw:2;
u8 pwr_boost_fac:5;
u8 tx_pwr_m:3;
u8 rsvd1:7;
u8 fix_mode_flag:1;
u8 rsvd2;
struct halbb_tf_ba_tbl_info tf;
};
struct halbb_ul_ru_gp_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 grp_psd_max_l;
u8 grp_psd_min_l:7;
u8 grp_psd_max_m:1;
u8 tf_rate_l:6;
u8 grp_psd_min_m:2;
u8 rsvd2:4;
u8 fix_tf_rate:1;
u8 tf_rate_m:3;
u8 rf_gain_idx_l:5;
u8 rf_gain_fix:1;
u8 ppdu_bw:2;
u8 rsvd1: 2;
u8 fix_mode_flag: 1;
u8 rf_gain_idx_m:5;
};
struct halbb_ru_sta_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
/* sta capability */
u8 rsvd0:6;
u8 gi_ltf_18spt:1;
u8 gi_ltf_48spt:1;
/* dl su */
u8 dlsu_doppler_ctrl:2;
u8 dlsu_gi_ltf:3;
u8 dlsu_bw:2;
u8 dlsu_info_en:1;
u8 dlru_ratetbl_ridx:4;
u8 dl_fwcqi_flag:1;
u8 dlsu_stbc:1;
u8 dlsu_txbf:1;
u8 dlsu_coding:1;
u8 csi_info_bitmap;
u8 dl_swgrp_bitmap[4];
u8 dlsu_rate_l:1;
u8 rsvd1:6;
u8 dlsu_dcm:1;
u8 dlsu_rate_m;
u8 rsvd2:2;
u8 dlsu_pwr:6;
u8 rsvd4;
/* ul su */
u8 ulsu_doppler_ctrl:2;
u8 ulsu_gi_ltf:3;
u8 ulsu_bw:2;
u8 ulsu_info_en:1;
u8 ulsu_mcs:4;
u8 ulsu_ss:3;
u8 ulsu_dcm:1;
u8 ulsu_rssi_m_l:1;
u8 ulsu_coding:1;
u8 ulsu_stbc:1;
u8 ulru_ratetbl_ridx:4;
u8 ul_fwcqi_flag:1;
u8 ulsu_rssi_m_m;
u8 ul_swgrp_bitmap[4];
/* tb info */
};
struct halbb_dl_fix_sta_info {
u8 mac_id;
u8 ru_pos[3];
u8 rsvd0: 4;
u8 fix_pwr_fac:1;
u8 fix_txbf:1;
u8 fix_coding:1;
u8 fix_rate:1;
struct halbb_ru_rate_info rate_i;
u8 rsvd1: 1;
u8 pwr_boost_fac:5;
u8 coding:1;
u8 txbf:1;
u8 rsvd2;
};
struct halbb_dl_ru_fix_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 rsvd0:1;
u8 ru_swp_flg:1;
u8 min_sta_num:3;
u8 max_sta_num:3;
u8 rupos_csht_flag:1;
u8 fixru_flag:1;
u8 ma_type:1;
u8 gi_ltf:3;
u8 stbc:1;
u8 doppler:1;
u8 rsvd2;
u8 rsvd3;
struct halbb_dl_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM];
};
struct halbb_ul_fix_sta_info {
u8 mac_id;
u8 ru_pos[3];
u8 tgt_rssi[3];
u8 rsvd1: 4;
u8 coding: 1;
u8 fix_coding: 1;
u8 fix_rate: 1;
u8 fix_tgt_rssi: 1;
struct halbb_ru_rate_info rate_i;
};
struct halbb_ul_ru_fix_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 ma_type:1;
u8 doppler:1;
u8 min_sta_num:3;
u8 max_sta_num:3;
u8 fixru_flag: 1;
u8 tb_t_pe_nom: 2;
u8 fix_tb_t_pe_nom: 1;
u8 stbc:1;
u8 gi_ltf:3;
struct halbb_ul_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM];
};
struct halbb_rua_tbl {
struct halbb_dl_ru_gp_tbl_info dl_ru_gp_tbl_i;
struct halbb_ul_ru_gp_tbl_info ul_ru_gp_tbl_i;
struct halbb_ru_sta_info ru_sta_i;
struct halbb_dl_ru_fix_tbl_info dl_ru_fix_tbl_i;
struct halbb_ul_ru_fix_tbl_info ul_ru_fix_tbl_i;
struct halbb_tf_ba_tbl_info tf_ba_tbl_i;
};
struct halbb_sw_grp_bitmap {
u8 macid;
u8 rsvd1:5;
u8 cmdend:1; // add for determine whether last user or not
u8 en_upd_ul_swgrp:1;
u8 en_upd_dl_swgrp:1;
u8 rsvd2;
u8 rsvd3;
u8 dl_sw_grp_bitmap[4];
u8 ul_sw_grp_bitmap[4];
};
struct halbb_sw_grp_set {
struct halbb_sw_grp_bitmap swgrp_bitmap[8];
};
struct dl_macid_cfg {
u8 macid;
u8 dl_su_rate_l:7;
u8 dl_su_rate_cfg:1;
u8 dl_su_pwr_l:3;
u8 dl_su_pwr_cfg:1;
u8 dl_su_bw:2;
u8 dl_su_rate_m:2;
u8 rsvd0:5;
u8 dl_su_pwr_m:3;
u8 rsvd1:6;
u8 gi_ltf_1x8_support:1;
u8 gi_ltf_4x8_support:1;
u8 dl_su_doppler_ctrl:2;
u8 dl_su_gi_ltf:3;
u8 rsvd2:2;
u8 dl_su_info_en:1;
u8 rsvd3:4;
u8 dl_su_dcm:1;
u8 dl_su_stbc:1;
u8 dl_su_txbf:1;
u8 dl_su_coding:1;
u8 rsvd4;
};
struct halbb_ul_macid_cfg {
u8 macid;
u8 rsvd0: 7;
u8 endcmd: 1;
u8 rsvd1;
u8 rsvd2;
u8 ul_su_doppler_ctrl: 2;
u8 ul_su_gi_ltf: 3;
u8 ul_su_bw: 2;
u8 ul_su_info_en: 1;
u8 ul_su_mcs: 4;
u8 ul_su_ss: 3;
u8 ul_su_dcm: 1;
u8 ul_su_rssi_m_l: 1;
u8 ul_su_coding: 1;
u8 ul_su_stbc: 1;
u8 rsvd3: 5;
u8 ul_su_rssi_m_m;
};
struct halbb_ul_macid_set {
struct halbb_ul_macid_cfg ul_macid_cfg[8];
};
struct halbb_ba_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
struct halbb_tf_ba_tbl_info tf_i;
};
struct csiinfo_cfg{
u8 macid;
u8 csi_info_bitmap;
u8 rsvd0;
u8 rsvd1;
};
struct halbb_cqi_info {
u8 macid;
u8 rsvd0: 1;
u8 endcmd: 1;
u8 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */
u8 ru_rate_table_row_idx: 4; /* UL or DL*/
u8 fw_cqi_flag: 1; /* UL or DL*/
u8 rsvd1;
u8 rsvd2;
s8 cqi_diff_table[19]; /* UL or DL*/
u8 rsvd3;
};
struct halbb_cqi_set{
struct halbb_cqi_info cqi_info[8];
};
struct halbb_bb_info_cfg {
u8 p20_ch_bitmap;
u8 rsvd0;
u8 rsvd1;
u8 rsvd2;
};
struct halbb_pwr_by_rt_tbl{
u8 pwr_by_rt[64];
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif /* HALBB_RUA_SUPPORT */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_rua_tbl_b_endian.h
|
C
|
agpl-3.0
| 6,626
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_RUA_TBL_EX_H__
#define __HALBB_RUA_TBL_EX_H__
#ifdef HALBB_RUA_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
#define HALBB_AX4RU_STA_NUM 4
#define HALBB_AX8RU_STA_NUM 8
/*@--------------------------[Enum]------------------------------------------*/
enum rtw_rua_tbl_hdr_rw {
RUA_TBL_RW_READ = 0,
RUA_TBL_RW_WRITE = 1
};
enum rtw_rua_tbl_hdr_type {
RUA_TBL_TYPE_SW = 0,
RUA_TBL_TYPE_HW = 1
};
enum rtw_rua_tbl_hdr_class {
RUA_TBL_CL_DLRU_SW = 0x0,
RUA_TBL_CL_ULRU_SW = 0x1,
RUA_TBL_CL_RU_STA = 0x2,
RUA_TBL_CL_DLRU_SW_FIX = 0x3,
RUA_TBL_CL_ULRU_SW_FIX = 0x4,
RUA_TBL_CL_BA_INFO = 0x5
};
/*@--------------------------[Structure]-------------------------------------*/
struct rtw_rua_tbl_hdr {
u8 rw:1;
u8 idx:7;
u16 offset:5;
u16 len:10;
u16 type:1;
u8 tbl_class;
};
struct rtw_ru_rate_ent {
u8 dcm:1;
u8 ss:3;
u8 mcs:4;
};
struct rtw_tf_ba_tbl {
u32 fix_ba:1;
u32 ru_psd:9;
u32 tf_rate:9;
u32 rf_gain_fix:1;
u32 rf_gain_idx:10;
u32 tb_ppdu_bw:2;
struct rtw_ru_rate_ent rate;
u8 gi_ltf:3;
u8 doppler:1;
u8 stbc:1;
u8 sta_coding:1;
u8 tb_t_pe_nom:2;
u8 pr20_bw_en:1;
u8 ma_type:1;
u8 rsvd1:6;
u8 rsvd2;
};
struct rtw_dl_ru_gp_tbl {
struct rtw_rua_tbl_hdr tbl_hdr;
u16 ppdu_bw:2;
u16 tx_pwr:9;
u16 pwr_boost_fac:5;
u8 fix_mode_flag:1;
u8 rsvd1:7;
u8 rsvd2;
struct rtw_tf_ba_tbl tf;
};
struct rtw_ul_ru_gp_tbl {
struct rtw_rua_tbl_hdr tbl_hdr;
u32 grp_psd_max:9;
u32 grp_psd_min:9;
u32 tf_rate:9;
u32 fix_tf_rate:1;
u32 rsvd2:4;
u16 ppdu_bw:2;
u16 rf_gain_fix:1;
u16 rf_gain_idx:10;
u16 fix_mode_flag:1;
u16 rsvd1:2;
};
struct rtw_ru_sta_info {
struct rtw_rua_tbl_hdr tbl_hdr;
/* sta capability */
u8 gi_ltf_48spt:1;
u8 gi_ltf_18spt:1;
u8 rsvd0:6;
/* dl su */
u8 dlsu_info_en:1;
u8 dlsu_bw:2;
u8 dlsu_gi_ltf:3;
u8 dlsu_doppler_ctrl:2;
u8 dlsu_coding:1;
u8 dlsu_txbf:1;
u8 dlsu_stbc:1;
u8 dl_fwcqi_flag:1;
u8 dlru_ratetbl_ridx:4;
u8 csi_info_bitmap;
u32 dl_swgrp_bitmap;
u16 dlsu_dcm:1;
u16 rsvd1:6;
u16 dlsu_rate:9;
u8 dlsu_pwr:6;
u8 rsvd2:2;
u8 rsvd4;
/* ul su */
u8 ulsu_info_en:1;
u8 ulsu_bw:2;
u8 ulsu_gi_ltf:3;
u8 ulsu_doppler_ctrl:2;
u8 ulsu_dcm:1;
u8 ulsu_ss:3;
u8 ulsu_mcs:4;
u16 ul_fwcqi_flag:1;
u16 ulru_ratetbl_ridx:4;
u16 ulsu_stbc:1;
u16 ulsu_coding:1;
u16 ulsu_rssi_m:9;
u32 ul_swgrp_bitmap;
/* tb info */
};
/*
struct rtw_dl_fix_sta_ent {
u8 mac_id;
u8 ru_pos[3];
u8 fix_rate:1;
u8 fix_coding:1;
u8 fix_txbf:1;
u8 fix_pwr_fac:1;
u8 rsvd0:4;
struct rtw_ru_rate_ent rate;
u8 txbf:1;
u8 coding:1;
u8 pwr_boost_fac:5;
u8 rsvd1: 1;
u8 rsvd2;
};
struct rtw_dl_ru_fix_tbl {
struct rtw_rua_tbl_hdr tbl_hdr;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 ru_swp_flg:1;
u8 rsvd0:1;
u8 doppler:1;
u8 stbc:1;
u8 gi_ltf:3;
u8 ma_type:1;
u8 fixru_flag:1;
u8 rupos_csht_flag:1;
u8 rsvd2;
struct rtw_dl_fix_sta_ent sta[HALBB_AX4RU_STA_NUM];
};
*/
struct rtw_dlfix_sta_i_ax4ru {
u8 mac_id;
u8 ru_pos[3];
u8 fix_rate:1;
u8 fix_coding:1;
u8 fix_txbf:1;
u8 fix_pwr_fac:1;
u8 rsvd0:4;
struct rtw_ru_rate_ent rate;
u8 txbf:1;
u8 coding:1;
u8 pwr_boost_fac:5;
u8 rsvd1: 1;
u8 rsvd2;
};
struct rtw_dlru_fixtbl_ax4ru {
struct rtw_rua_tbl_hdr tbl_hdr;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 ru_swp_flg:1;
u8 rsvd0:1;
u8 doppler:1;
u8 stbc:1;
u8 gi_ltf:3;
u8 ma_type:1;
u8 fixru_flag:1;
u8 rupos_csht_flag:1;
u8 rsvd2;
struct rtw_dlfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM];
};
union rtw_dlru_fixtbl{
struct rtw_dlru_fixtbl_ax4ru ax4ru;
};
/*
struct rtw_ul_fix_sta_ent {
u8 mac_id;
u8 ru_pos[3];
u8 tgt_rssi[3];
u8 fix_tgt_rssi:1;
u8 fix_rate:1;
u8 fix_coding:1;
u8 coding:1;
u8 rsvd1:4;
struct rtw_ru_rate_ent rate;
};
struct rtw_ul_ru_fix_tbl {
struct rtw_rua_tbl_hdr tbl_hdr;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 doppler:1;
u8 ma_type:1;
u8 gi_ltf:3;
u8 stbc:1;
u8 fix_tb_t_pe_nom: 1;
u8 tb_t_pe_nom: 2;
u8 fixru_flag: 1;
struct rtw_ul_fix_sta_ent sta[HALBB_AX4RU_STA_NUM];
};
*/
struct rtw_ulfix_sta_i_ax4ru {
u8 mac_id;
u8 ru_pos[3];
u8 tgt_rssi[3];
u8 fix_tgt_rssi:1;
u8 fix_rate:1;
u8 fix_coding:1;
u8 coding:1;
u8 rsvd1:4;
struct rtw_ru_rate_ent rate;
};
struct rtw_ulru_fixtbl_ax4ru {
struct rtw_rua_tbl_hdr tbl_hdr;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 doppler:1;
u8 ma_type:1;
u8 gi_ltf:3;
u8 stbc:1;
u8 fix_tb_t_pe_nom: 1;
u8 tb_t_pe_nom: 2;
u8 fixru_flag: 1;
struct rtw_ulfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM];
};
union rtw_ulru_fixtbl{
struct rtw_ulru_fixtbl_ax4ru ax4ru;
};
struct rtw_ba_tbl_info {
struct rtw_rua_tbl_hdr tbl_hdr;
struct rtw_tf_ba_tbl tf_ba_t;
};
struct rtw_sw_grp_bitmap {
u8 macid;
u8 en_upd_dl_swgrp:1;
u8 en_upd_ul_swgrp:1;
u8 cmdend:1; // add for determine whether last user or not
u8 rsvd1:5;
u32 dl_sw_grp_bitmap;
u32 ul_sw_grp_bitmap;
};
struct rtw_sw_grp_set {
struct rtw_sw_grp_bitmap swgrp_bitmap[8];
};
struct rtw_dl_macid_cfg {
u32 macid: 8;
u32 dl_su_rate_cfg: 1;
u32 dl_su_rate: 9;
u32 dl_su_bw: 2;
u32 dl_su_pwr_cfg: 1;
u32 dl_su_pwr: 6;
u32 rsvd0: 5;
u32 gi_ltf_4x8_support: 1;
u32 gi_ltf_1x8_support: 1;
u32 rsvd1: 6;
u32 dl_su_info_en: 1;
u32 rsvd2: 2;
u32 dl_su_gi_ltf: 3;
u32 dl_su_doppler_ctrl: 2;
u32 dl_su_coding: 1;
u32 dl_su_txbf: 1;
u32 dl_su_stbc: 1;
u32 dl_su_dcm: 1;
u32 rsvd3: 12;
};
struct rtw_ul_macid_cfg {
u32 macid: 8;
u32 endcmd: 1;
u32 rsvd0: 23;
u32 ul_su_info_en: 1;
u32 ul_su_bw: 2;
u32 ul_su_gi_ltf: 3;
u32 ul_su_doppler_ctrl: 2;
u32 ul_su_dcm: 1;
u32 ul_su_ss: 3;
u32 ul_su_mcs: 4;
u32 rsvd2: 5;
u32 ul_su_stbc: 1;
u32 ul_su_coding: 1;
u32 ul_su_rssi_m: 9;
};
struct rtw_ul_macid_set {
struct rtw_ul_macid_cfg ul_macid_cfg[8];
};
struct rtw_csiinfo_cfg {
u32 macid: 8;
u32 csi_info_bitmap: 8;
u32 rsvd0: 16;
};
struct rtw_cqi_info {
u32 macid: 8;
u32 fw_cqi_flag: 1; /* UL or DL*/
u32 ru_rate_table_row_idx: 4; /* UL or DL*/
u32 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */
u32 endcmd: 1;
u32 rsvd0: 1;
u32 rsvd1: 16;
s8 cqi_diff_table[19]; /* UL or DL*/
u8 rsvd2;
};
struct rtw_cqi_set{
struct rtw_cqi_info cqi_info[8];
};
struct rtw_bbinfo_cfg {
u32 p20_ch_bitmap: 8;
u32 rsvd0: 24;
};
struct rtw_pwr_by_rt_tbl{
s16 pwr_by_rt[32];
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
// u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
// struct rtw_dl_ru_fix_tbl *info);
u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
union rtw_dlru_fixtbl *union_info);
u32 halbb_upd_dlru_grptbl(struct bb_info *bb,
struct rtw_dl_ru_gp_tbl *info);
// u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
// struct rtw_ul_ru_fix_tbl *info);
u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
union rtw_ulru_fixtbl *union_info);
u32 halbb_upd_ulru_grptbl(struct bb_info *bb,
struct rtw_ul_ru_gp_tbl *info);
u32 halbb_upd_rusta_info(struct bb_info *bb,
struct rtw_ru_sta_info *info);
u32 halbb_upd_ba_infotbl(struct bb_info *bb,
struct rtw_ba_tbl_info *info);
u32 halbb_swgrp_hdl(struct bb_info *bb,
struct rtw_sw_grp_set *info);
u32 halbb_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg);
u32 halbb_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg);
u32 halbb_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg);
u32 halbb_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg);
u32 halbb_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg);
u32 halbb_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg);
/*u32 halbb_rua_tbl_init(struct bb_info *bb);*/
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_rua_tbl_ex.h
|
C
|
agpl-3.0
| 8,836
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_RUA_TBL_L_ENDIAN_H__
#define __HALBB_RUA_TBL_L_ENDIAN_H__
#ifdef HALBB_RUA_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*[IO Reg]*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_rua_tbl_hdr_info {
u8 rw:1;
u8 idx:7;
u8 offset:5;
u8 len_l:3;
u8 len_m:7;
u8 type:1;
u8 tbl_class;
};
struct halbb_ru_rate_info {
u8 dcm:1;
u8 ss:3;
u8 mcs:4;
};
struct halbb_tf_ba_tbl_info {
u8 fix_ba:1;
u8 ru_psd_l:7;
u8 ru_psd_m:2;
u8 tf_rate_l:6;
u8 tf_rate_m:3;
u8 rf_gain_fix:1;
u8 rf_gain_idx_l:4;
u8 rf_gain_idx_m:6;
u8 tb_ppdu_bw:2;
struct halbb_ru_rate_info rate_i;
u8 gi_ltf:3;
u8 doppler:1;
u8 stbc:1;
u8 sta_coding:1;
u8 tb_t_pe_nom:2;
u8 pr20_bw_en:1;
u8 ma_type: 1;
u8 rsvd1: 6;
};
struct halbb_dl_ru_gp_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 ppdu_bw:2;
u8 tx_pwr_l:6;
u8 tx_pwr_m:3;
u8 pwr_boost_fac:5;
u8 fix_mode_flag:1;
u8 rsvd1:7;
u8 rsvd2;
struct halbb_tf_ba_tbl_info tf;
};
struct halbb_ul_ru_gp_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 grp_psd_max_l;
u8 grp_psd_max_m:1;
u8 grp_psd_min_l:7;
u8 grp_psd_min_m:2;
u8 tf_rate_l:6;
u8 tf_rate_m:3;
u8 fix_tf_rate:1;
u8 rsvd2:4;
u8 ppdu_bw:2;
u8 rf_gain_fix:1;
u8 rf_gain_idx_l:5;
u8 rf_gain_idx_m:5;
u8 fix_mode_flag: 1;
u8 rsvd1: 2;
};
struct halbb_ru_sta_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
/* sta capability */
u8 gi_ltf_48spt:1;
u8 gi_ltf_18spt:1;
u8 rsvd0:6;
/* dl su */
u8 dlsu_info_en:1;
u8 dlsu_bw:2;
u8 dlsu_gi_ltf:3;
u8 dlsu_doppler_ctrl:2;
u8 dlsu_coding:1;
u8 dlsu_txbf:1;
u8 dlsu_stbc:1;
u8 dl_fwcqi_flag:1;
u8 dlru_ratetbl_ridx:4;
u8 csi_info_bitmap;
u8 dl_swgrp_bitmap[4];
u8 dlsu_dcm:1;
u8 rsvd1:6;
u8 dlsu_rate_l:1;
u8 dlsu_rate_m;
u8 dlsu_pwr:6;
u8 rsvd2:2;
u8 rsvd4;
/* ul su */
u8 ulsu_info_en:1;
u8 ulsu_bw:2;
u8 ulsu_gi_ltf:3;
u8 ulsu_doppler_ctrl:2;
u8 ulsu_dcm:1;
u8 ulsu_ss:3;
u8 ulsu_mcs:4;
u8 ul_fwcqi_flag:1;
u8 ulru_ratetbl_ridx:4;
u8 ulsu_stbc:1;
u8 ulsu_coding:1;
u8 ulsu_rssi_m_l:1;
u8 ulsu_rssi_m_m;
u8 ul_swgrp_bitmap[4];
/* tb info */
};
struct halbb_dl_fix_sta_info {
u8 mac_id;
u8 ru_pos[3];
u8 fix_rate:1;
u8 fix_coding:1;
u8 fix_txbf:1;
u8 fix_pwr_fac:1;
u8 rsvd0: 4;
struct halbb_ru_rate_info rate_i;
u8 txbf:1;
u8 coding:1;
u8 pwr_boost_fac:5;
u8 rsvd1: 1;
u8 rsvd2;
};
struct halbb_dl_ru_fix_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 ru_swp_flg:1;
u8 rsvd0:1;
u8 doppler:1;
u8 stbc:1;
u8 gi_ltf:3;
u8 ma_type:1;
u8 fixru_flag:1;
u8 rupos_csht_flag:1;
u8 rsvd2;
u8 rsvd3;
struct halbb_dl_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM];
};
struct halbb_ul_fix_sta_info {
u8 mac_id;
u8 ru_pos[3];
u8 tgt_rssi[3];
u8 fix_tgt_rssi: 1;
u8 fix_rate: 1;
u8 fix_coding: 1;
u8 coding: 1;
u8 rsvd1: 4;
struct halbb_ru_rate_info rate_i;
};
struct halbb_ul_ru_fix_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
u8 max_sta_num:3;
u8 min_sta_num:3;
u8 doppler:1;
u8 ma_type:1;
u8 gi_ltf:3;
u8 stbc:1;
u8 fix_tb_t_pe_nom: 1;
u8 tb_t_pe_nom: 2;
u8 fixru_flag: 1;
struct halbb_ul_fix_sta_info sta_i[HALBB_AX4RU_STA_NUM];
};
struct halbb_rua_tbl {
struct halbb_dl_ru_gp_tbl_info dl_ru_gp_tbl_i;
struct halbb_ul_ru_gp_tbl_info ul_ru_gp_tbl_i;
struct halbb_ru_sta_info ru_sta_i;
struct halbb_dl_ru_fix_tbl_info dl_ru_fix_tbl_i;
struct halbb_ul_ru_fix_tbl_info ul_ru_fix_tbl_i;
struct halbb_tf_ba_tbl_info tf_ba_tbl_i;
};
struct halbb_sw_grp_bitmap {
u8 macid;
u8 en_upd_dl_swgrp:1;
u8 en_upd_ul_swgrp:1;
u8 cmdend:1; // add for determine whether last user or not
u8 rsvd1:5;
u8 rsvd2;
u8 rsvd3;
u8 dl_sw_grp_bitmap[4];
u8 ul_sw_grp_bitmap[4];
};
struct halbb_sw_grp_set {
struct halbb_sw_grp_bitmap swgrp_bitmap[8];
};
struct dl_macid_cfg {
u8 macid;
u8 dl_su_rate_cfg:1;
u8 dl_su_rate_l:7;
u8 dl_su_rate_m:2;
u8 dl_su_bw:2;
u8 dl_su_pwr_cfg:1;
u8 dl_su_pwr_l:3;
u8 dl_su_pwr_m:3;
u8 rsvd0:5;
u8 gi_ltf_4x8_support:1;
u8 gi_ltf_1x8_support:1;
u8 rsvd1:6;
u8 dl_su_info_en:1;
u8 rsvd2:2;
u8 dl_su_gi_ltf:3;
u8 dl_su_doppler_ctrl:2;
u8 dl_su_coding:1;
u8 dl_su_txbf:1;
u8 dl_su_stbc:1;
u8 dl_su_dcm:1;
u8 rsvd3:4;
u8 rsvd4;
};
struct halbb_ul_macid_cfg {
u8 macid;
u8 endcmd: 1;
u8 rsvd0: 7;
u8 rsvd1;
u8 rsvd2;
u8 ul_su_info_en: 1;
u8 ul_su_bw: 2;
u8 ul_su_gi_ltf: 3;
u8 ul_su_doppler_ctrl: 2;
u8 ul_su_dcm: 1;
u8 ul_su_ss: 3;
u8 ul_su_mcs: 4;
u8 rsvd3: 5;
u8 ul_su_stbc: 1;
u8 ul_su_coding: 1;
u8 ul_su_rssi_m_l: 1;
u8 ul_su_rssi_m_m;
};
struct halbb_ul_macid_set {
struct halbb_ul_macid_cfg ul_macid_cfg[8];
};
struct halbb_ba_tbl_info {
struct halbb_rua_tbl_hdr_info tbl_hdr_i;
struct halbb_tf_ba_tbl_info tf_i;
};
struct csiinfo_cfg{
u8 macid;
u8 csi_info_bitmap;
u8 rsvd0;
u8 rsvd1;
};
struct halbb_cqi_info {
u8 macid;
u8 fw_cqi_flag: 1; /* UL or DL*/
u8 ru_rate_table_row_idx: 4; /* UL or DL*/
u8 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */
u8 endcmd: 1;
u8 rsvd0: 1;
u8 rsvd1;
u8 rsvd2;
s8 cqi_diff_table[19]; /* UL or DL*/
u8 rsvd3;
};
struct halbb_cqi_set{
struct halbb_cqi_info cqi_info[8];
};
struct halbb_bb_info_cfg {
u8 p20_ch_bitmap;
u8 rsvd0;
u8 rsvd1;
u8 rsvd2;
};
struct halbb_pwr_by_rt_tbl{
u8 pwr_by_rt[64];
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif /* HALBB_RUA_SUPPORT */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_rua_tbl_l_endian.h
|
C
|
agpl-3.0
| 6,626
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbb_precomp.h"
#ifdef HALBB_STATISTICS_SUPPORT
void halbb_set_crc32_cnt2_rate(struct bb_info *bb, u16 rate_idx)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
bool is_ofdm_rate = halbb_is_ofdm_rate(bb, rate_idx);
bool is_ht_rate = halbb_is_ht_rate(bb, rate_idx);
bool is_vht_rate = halbb_is_vht_rate(bb, rate_idx);
bool is_he_rate = halbb_is_he_rate(bb, rate_idx);
u32 reg_addr = cr->intf_r_rate;
u32 ofdm_rate_bitmask = cr->intf_r_rate_m;
u32 ht_mcs_bitmask = cr->intf_r_mcs_m;
u32 vht_mcs_bitmask = cr->intf_r_vht_mcs_m;
u32 vht_ss_bitmask = cr->intf_r_vht_nss_m;
u32 he_mcs_bitmask =cr->intf_r_he_mcs_m;
u32 he_ss_bitmask = cr->intf_r_he_nss_m;
u8 rate_digi = 0x0;
u8 ss = 0x0;
if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate && !is_he_rate)
BB_DBG(bb, DBG_FA_CNT,
"[STAT] rate_idx = (0x%x) Not support !!\n",
rate_idx);
if (is_ofdm_rate) {
rate_digi = halbb_legacy_rate_2_spec_rate(bb, rate_idx);
halbb_set_reg(bb, reg_addr, ofdm_rate_bitmask, rate_digi);
usr_set->ofdm2_rate_idx = rate_idx;
usr_set->ht2_rate_idx = 0;
usr_set->vht2_rate_idx = 0;
usr_set->he2_rate_idx = 0;
} else if (is_ht_rate) {
rate_digi = halbb_rate_2_rate_digit(bb, rate_idx);
halbb_set_reg(bb, reg_addr, ht_mcs_bitmask, rate_digi);
usr_set->ht2_rate_idx = rate_idx;
usr_set->ofdm2_rate_idx = 0;
usr_set->vht2_rate_idx = 0;
usr_set->he2_rate_idx = 0;
} else if (is_vht_rate) {
rate_digi = halbb_rate_2_rate_digit(bb, rate_idx);
ss = halbb_rate_to_num_ss(bb, rate_idx);
halbb_set_reg(bb, reg_addr, vht_mcs_bitmask, rate_digi);
halbb_set_reg(bb, reg_addr, vht_ss_bitmask, ss - 1);
usr_set->vht2_rate_idx = rate_idx;
usr_set->ofdm2_rate_idx = 0;
usr_set->ht2_rate_idx = 0;
usr_set->he2_rate_idx = 0;
} else if (is_he_rate) {
rate_digi = halbb_rate_2_rate_digit(bb, rate_idx);
ss = halbb_rate_to_num_ss(bb, rate_idx);
halbb_set_reg(bb, reg_addr, he_mcs_bitmask, rate_digi);
halbb_set_reg(bb, reg_addr, he_ss_bitmask, ss - 1);
usr_set->he2_rate_idx = rate_idx;
usr_set->ofdm2_rate_idx = 0;
usr_set->ht2_rate_idx = 0;
usr_set->vht2_rate_idx = 0;
}
}
void halbb_set_crc32_cnt3_format(struct bb_info *bb, u8 usr_type_sel)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat_t->bb_fa_i;
struct bb_cca_info *cca = &stat_t->bb_cca_i;
struct bb_crc_info *crc = &stat_t->bb_crc_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
u32 reg_addr = cr->intf_r_mac_hdr_type;
u32 type_bitmask = cr->intf_r_mac_hdr_type_m;
usr_set->stat_type_sel_i = usr_type_sel;
usr_set->stat_mac_type_i = TYPE_DATA;
switch(usr_set->stat_type_sel_i) {
case STATE_PROBE_RESP:
usr_set->stat_mac_type_i = TYPE_PROBE_RESP;
break;
case STATE_BEACON:
usr_set->stat_mac_type_i = TYPE_BEACON;
break;
case STATE_ACTION:
usr_set->stat_mac_type_i = TYPE_ACTION;
break;
case STATE_BFRP:
usr_set->stat_mac_type_i = TYPE_BFRP;
break;
case STATE_NDPA:
usr_set->stat_mac_type_i = TYPE_NDPA;
break;
case STATE_BA:
usr_set->stat_mac_type_i = TYPE_BA;
break;
case STATE_RTS:
usr_set->stat_mac_type_i = TYPE_RTS;
break;
case STATE_CTS:
usr_set->stat_mac_type_i = TYPE_CTS;
break;
case STATE_ACK:
usr_set->stat_mac_type_i = TYPE_ACK;
break;
case STATE_DATA:
usr_set->stat_mac_type_i = TYPE_DATA;
break;
case STATE_NULL:
usr_set->stat_mac_type_i = TYPE_NULL;
break;
case STATE_QOS:
usr_set->stat_mac_type_i = TYPE_QOS;
break;
default:
BB_DBG(bb, DBG_FA_CNT,
"[STAT] MAC frame type cnt: Not support !!!\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] Please choose one of the following options\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {1: Probe Request}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {2: Beacon}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {3: Action}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {4: Beamforming Report Poll}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {5: NDPA}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {6: BA}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {7: RTS}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {8: CTS}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {9: ACK}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {10: Data}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {11: Null}\n");
BB_DBG(bb, DBG_FA_CNT,
"[STAT] {12: QoS Data}\n");
break;
}
halbb_set_reg(bb, reg_addr, type_bitmask, usr_set->stat_mac_type_i);
}
void halbb_crc32_cnt_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
char help[] = "-h";
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
u16 rate = 0x0;
u8 usr_type_sel = 0;
if ((_os_strcmp(input[1], help) == 0)) {
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"Get CRC_OK/error for specific rate_idx or mac hdr type\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"============== Specific rate cnt ==============\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {1} {rate_idx in decimal}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"---------- Specific MAC header type ----------\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {1: Probe Request}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {2: Beacon}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {3: Action}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {4: Beamforming Report Poll}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {5: NDPA}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {6: BA}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {7: RTS}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {8: CTS}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {9: ACK}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {10: Data}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {11: Null}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"stat {2} {12: QoS Data}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Chk hang Auto recovery enable: {3} {en}\n");
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Chk hang limit: {4} {#limit}\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"============== Notes ==============\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"------------ Rate_idx ------------\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"CCK_idx: 0~3\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"OFDM_idx: 4~11\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"HT_idx: 128~\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"VHT_1ss_idx: 256~265\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"VHT_2ss_idx: 272~281\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"HE_1ss_idx: 384~395\n");
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"HE_2ss_idx: 400~411\n");
} else {
HALBB_SCAN(input[1], DCMD_DECIMAL, &var[0]);
if (var[0] == 1) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
rate = (u16)var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{rate}={0x%x}", rate);
halbb_set_crc32_cnt2_rate(bb, rate);
} else if (var[0] == 2) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
usr_type_sel = (u8)var[1];
BB_DBG_CNSL(out_len, used, output + used, out_len - used,
"{MAC header type}={%d}", usr_type_sel);
halbb_set_crc32_cnt3_format(bb, usr_type_sel);
} else if (var[0] == 3) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
stat_t->hang_recovery_en = (u8)var[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Chk hang Auto recovery enable=%d\n", stat_t->hang_recovery_en);
} else if (var[0] == 4) {
HALBB_SCAN(input[2], DCMD_DECIMAL, &var[1]);
stat_t->chk_hang_limit = (u8)var[1];
BB_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
"Chk hang limit=%d\n", stat_t->chk_hang_limit);
}
}
*_used = used;
*_out_len = out_len;
}
void halbb_print_cnt3(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat_t->bb_fa_i;
struct bb_cca_info *cca = &stat_t->bb_cca_i;
struct bb_crc_info *crc = &stat_t->bb_crc_i;
struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
//char dbg_buf[HALBB_SNPRINT_SIZE] = {0};
u32 tmp = 0;
u8 pcr = 0;
tmp = crc2->cnt_ofdm3_crc32_ok + crc2->cnt_ofdm3_crc32_error;
if (bb->hal_com->dbcc_en) {
BB_DBG(bb, DBG_FA_CNT, "[DBCC!!!!]===>\n");
BB_DBG(bb, DBG_FA_CNT, "[The following statistics is at %s]===>\n", phy_idx == HW_PHY_0 ? "PHY-0" : "PHY-1");
}
switch(usr_set->stat_type_sel_i) {
case STATE_PROBE_RESP:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[Probe Response Data CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_BEACON:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[Beacon CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_ACTION:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[Action CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_BFRP:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[BFRP CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_NDPA:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[NDPA CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_BA:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[BA CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_RTS:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[RTS CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_CTS:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[CTS CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_ACK:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[ACK CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_DATA:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[DATA CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_NULL:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[Null CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
case STATE_QOS:
pcr = (u8)HALBB_DIV(crc2->cnt_ofdm3_crc32_ok * 100, tmp);
BB_DBG(bb, DBG_FA_CNT,
"[QoS CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
crc2->cnt_ofdm3_crc32_error,
crc2->cnt_ofdm3_crc32_ok, pcr);
break;
default:
break;
}
}
void halbb_print_cnt2(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
struct bb_usr_set_info *usr_set = &stat_t->bb_usr_set_i;
u32 tmp = 0;
//char dbg_buf[HALBB_SNPRINT_SIZE] = {0};
if (bb->hal_com->dbcc_en) {
BB_DBG(bb, DBG_FA_CNT, "[DBCC!!!!]===>\n");
BB_DBG(bb, DBG_FA_CNT, "[The following statistics is at %s]===>\n", phy_idx == HW_PHY_0 ? "PHY-0" : "PHY-1");
}
if (usr_set->ofdm2_rate_idx) {
tmp = crc2->cnt_ofdm2_crc32_error + crc2->cnt_ofdm2_crc32_ok;
crc2->ofdm2_pcr = (u8)HALBB_DIV(crc2->cnt_ofdm2_crc32_ok * 100,
tmp);
halbb_print_rate_2_buff(bb, usr_set->ofdm2_rate_idx, RTW_GILTF_LGI_4XHE32, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_FA_CNT,
"[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
bb->dbg_buf, crc2->cnt_ofdm2_crc32_error,
crc2->cnt_ofdm2_crc32_ok, crc2->ofdm2_pcr);
} else if (usr_set->ht2_rate_idx) {
tmp = crc2->cnt_ht2_crc32_error + crc2->cnt_ht2_crc32_ok;
crc2->ht2_pcr = (u8)HALBB_DIV(crc2->cnt_ht2_crc32_ok * 100,
tmp);
halbb_print_rate_2_buff(bb, usr_set->ht2_rate_idx, RTW_GILTF_LGI_4XHE32, bb->dbg_buf,
HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_FA_CNT,
"[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
bb->dbg_buf, crc2->cnt_ht2_crc32_error,
crc2->cnt_ht2_crc32_ok, crc2->ht2_pcr);
} else if(usr_set->vht2_rate_idx) {
tmp = crc2->cnt_vht2_crc32_error +
crc2->cnt_vht2_crc32_ok;
crc2->vht2_pcr = (u8)HALBB_DIV(crc2->cnt_vht2_crc32_ok *
100, tmp);
halbb_print_rate_2_buff(bb, usr_set->vht2_rate_idx,
RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_FA_CNT,
"[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
bb->dbg_buf, crc2->cnt_vht2_crc32_error,
crc2->cnt_vht2_crc32_ok, crc2->vht2_pcr);
} else if (usr_set->he2_rate_idx) {
tmp = crc2->cnt_he2_crc32_error +
crc2->cnt_he2_crc32_ok;
crc2->he2_pcr = (u8)HALBB_DIV(crc2->cnt_he2_crc32_ok *
100, tmp);
halbb_print_rate_2_buff(bb, usr_set->he2_rate_idx,
RTW_GILTF_LGI_4XHE32, bb->dbg_buf, HALBB_SNPRINT_SIZE);
BB_DBG(bb, DBG_FA_CNT,
"[HE:%s CRC32 Cnt] {error, ok}= {%d, %d} (PCR=%d percent)\n",
bb->dbg_buf, crc2->cnt_he2_crc32_error,
crc2->cnt_he2_crc32_ok, crc2->he2_pcr);
}
}
void halbb_chk_hang(struct bb_info *bb)
{
struct bb_stat_info *stat = &bb->bb_stat_i;
struct bb_cca_info *cca = &stat->bb_cca_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
bool chk_hang_en = false;
/* According to sd4 info., when rx hang --> all cca brk, half of brk is l-sig brk */
chk_hang_en = (cca->cnt_cca_all == 0);
if (chk_hang_en) {
BB_DBG(bb, DBG_FA_CNT, "[CHK-HANG] ReasonCode:RHAX-2 (POP HANG)\n\n");
stat->chk_hang_cnt = stat->chk_hang_cnt + 1;
BB_DBG(bb, DBG_FA_CNT, "[CHK-HANG] hang_cnt=%d, hang_limit=%d, recovery_en=%d\n",
stat->chk_hang_cnt, stat->chk_hang_limit, stat->hang_recovery_en);
if (stat->hang_recovery_en && (stat->chk_hang_cnt >= stat->chk_hang_limit)) {
BB_DBG(bb, DBG_FA_CNT, "[CHK-HANG] Change PoP counter limit\n");
halbb_set_reg(bb, cr->max_cnt_pop, cr->max_cnt_pop_m, 0x0);
halbb_delay_us(bb, 1);
halbb_set_reg(bb, cr->max_cnt_pop, cr->max_cnt_pop_m, 0x50);
stat->chk_hang_cnt = 0;
}
}
}
void halbb_print_cnt(struct bb_info *bb, bool cck_en, enum phl_phy_idx phy_idx, enum phl_phy_idx phy_idx_2)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat_t->bb_fa_i;
struct bb_cck_fa_info *cck_fa = &fa->bb_cck_fa_i;
struct bb_legacy_fa_info *legacy_fa = &fa->bb_legacy_fa_i;
struct bb_ht_fa_info *ht_fa = &fa->bb_ht_fa_i;
struct bb_vht_fa_info *vht_fa = &fa->bb_vht_fa_i;
struct bb_he_fa_info *he_fa = &fa->bb_he_fa_i;
struct bb_cca_info *cca = &stat_t->bb_cca_i;
struct bb_crc_info *crc = &stat_t->bb_crc_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i;
struct rtw_hal_com_t *hal = bb->hal_com;
struct rtw_hal_stat_info *stat_info = &hal->band[bb->bb_phy_idx].stat_info;
if (bb->hal_com->dbcc_en) {
if (!cck_en) {
fa->cnt_fail_all = fa->cnt_ofdm_fail;
cca->cnt_cca_all = cca->cnt_ofdm_cca;
} else {
fa->cnt_fail_all = fa->cnt_ofdm_fail +
fa->cnt_cck_fail;
cca->cnt_cca_all = cca->cnt_cck_cca +
cca->cnt_ofdm_cca;
}
} else {
if (!cck_en) {
fa->cnt_fail_all = fa->cnt_ofdm_fail;
cca->cnt_cca_all = cca->cnt_ofdm_cca;
} else {
fa->cnt_fail_all = fa->cnt_ofdm_fail +
fa->cnt_cck_fail;
cca->cnt_cca_all = cca->cnt_cck_cca +
cca->cnt_ofdm_cca;
}
}
crc->cnt_crc32_error_all = crc->cnt_he_crc32_error +
crc->cnt_vht_crc32_error +
crc->cnt_ht_crc32_error +
crc->cnt_ofdm_crc32_error +
crc->cnt_cck_crc32_error;
crc->cnt_crc32_ok_all = crc->cnt_he_crc32_ok +
crc->cnt_vht_crc32_ok +
crc->cnt_ht_crc32_ok +
crc->cnt_ofdm_crc32_ok +
crc->cnt_cck_crc32_ok;
stat_info->cnt_fail_all = fa->cnt_fail_all;
stat_info->cnt_cck_fail = fa->cnt_cck_fail;
stat_info->cnt_ofdm_fail = fa->cnt_ofdm_fail;
stat_info->cnt_cca_all = cca->cnt_cca_all;
stat_info->cnt_ofdm_cca = cca->cnt_ofdm_cca;
stat_info->cnt_cck_cca = cca->cnt_cck_cca;
stat_info->cnt_crc32_error_all = crc->cnt_crc32_error_all;
stat_info->cnt_he_crc32_error = crc->cnt_he_crc32_error;
stat_info->cnt_vht_crc32_error = crc->cnt_vht_crc32_error;
stat_info->cnt_ht_crc32_error = crc->cnt_ht_crc32_error;
stat_info->cnt_ofdm_crc32_error = crc->cnt_ofdm_crc32_error;
stat_info->cnt_cck_crc32_error = crc->cnt_cck_crc32_error;
stat_info->cnt_crc32_ok_all = crc->cnt_crc32_ok_all;
stat_info->cnt_he_crc32_ok = crc->cnt_he_crc32_ok;
stat_info->cnt_vht_crc32_ok = crc->cnt_vht_crc32_ok;
stat_info->cnt_ht_crc32_ok = crc->cnt_ht_crc32_ok;
stat_info->cnt_ofdm_crc32_ok = crc->cnt_ofdm_crc32_ok;
stat_info->cnt_cck_crc32_ok = crc->cnt_cck_crc32_ok;
stat_info->igi_fa_rssi = bb->bb_dig_i.p_cur_dig_unit->igi_fa_rssi;
if (bb->hal_com->dbcc_en) {
BB_DBG(bb, DBG_FA_CNT, "[DBCC!!!!]===>\n");
BB_DBG(bb, DBG_FA_CNT, "[The following statistics is at %s]===>\n", phy_idx == HW_PHY_0 ? "PHY-0" : "PHY-1");
#if 1
if (cck_en) {
if (phy_idx_2 != HW_PHY_MAX)
BB_DBG(bb, DBG_FA_CNT, "[The following CCK statistics is at %s]===>\n",
phy_idx_2 == HW_PHY_0 ? "PHY-0" : "PHY-1");
}
#endif
}
BB_DBG(bb, DBG_FA_CNT, "[Tx counter]===>\n");
BB_DBG(bb, DBG_FA_CNT,
"[Tx Cnt]{CCK_TXEN, CCK_TXON, OFDM_TXEN, OFDM_TXON}: {%d, %d, %d, %d}\n",
tx->cck_mac_txen, tx->cck_phy_txon, tx->ofdm_mac_txen,
tx->ofdm_phy_txon);
BB_DBG(bb, DBG_FA_CNT, "[Rx counter]===>\n");
BB_DBG(bb, DBG_FA_CNT,
"[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
cca->cnt_cck_cca, cca->cnt_ofdm_cca, cca->cnt_cca_all);
BB_DBG(bb, DBG_FA_CNT,
"[CCA Spoofing Cnt] {CCK, OFDM} = {%d, %d}\n",
cca->cnt_cck_spoofing, cca->cnt_ofdm_spoofing);
BB_DBG(bb, DBG_FA_CNT,
"[AMPDU miss] = {%d}\n", crc->cnt_ampdu_miss);
BB_DBG(bb, DBG_FA_CNT,
"[Total HW Break counter] = {%d}\n", fa->cnt_total_brk);
BB_DBG(bb, DBG_FA_CNT,
"[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
fa->cnt_cck_fail, fa->cnt_ofdm_fail, fa->cnt_fail_all);
BB_DBG(bb, DBG_FA_CNT,
"[CCK FA] SFD_err=%d, SIG_err=%d CRC16=%d\n",
cck_fa->sfd_gg_cnt, cck_fa->sig_gg_cnt, cck_fa->cnt_cck_crc_16);
BB_DBG(bb, DBG_FA_CNT,
"[OFDM FA] Parity_err=%d, Rate=%d, LSIG_brk_s=%d, LSIG_brk_l=%d, SBD=%d\n",
legacy_fa->cnt_parity_fail, legacy_fa->cnt_rate_illegal,
legacy_fa->cnt_lsig_brk_s_th, legacy_fa->cnt_lsig_brk_l_th,
legacy_fa->cnt_sb_search_fail);
BB_DBG(bb, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
ht_fa->cnt_crc8_fail, ht_fa->cnt_mcs_fail);
BB_DBG(bb, DBG_FA_CNT,
"[VHT FA] SIGA_CRC8=%d, MCS=%d\n",
vht_fa->cnt_crc8_fail_vhta, vht_fa->cnt_mcs_fail_vht);
#if 0
BB_DBG(bb, DBG_FA_CNT,
"[HE FA] SIGA_CRC4_SU=%d, SIGA_CRC4_ERSU=%d, SIGA_CRC4_MU=%d, SIGB_CRC4_ch1=%d, SIGB_CRC4_ch2=%d, MCS=%d, MCS_bcc=%d, MCS_DCM=%d\n",
he_fa->cnt_crc4_fail_hea_su, he_fa->cnt_crc4_fail_hea_ersu,
he_fa->cnt_crc4_fail_hea_mu, he_fa->cnt_crc4_fail_heb_ch1_mu,
he_fa->cnt_crc4_fail_heb_ch2_mu, he_fa->cnt_mcs_fail_he,
he_fa->cnt_mcs_fail_he_bcc, he_fa->cnt_mcs_fail_he_dcm);
#endif
BB_DBG(bb, DBG_FA_CNT,
"[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, HE, Total} = {%d, %d, %d, %d, %d, %d}\n",
crc->cnt_cck_crc32_ok, crc->cnt_ofdm_crc32_ok,
crc->cnt_ht_crc32_ok, crc->cnt_vht_crc32_ok,
crc->cnt_he_crc32_ok, crc->cnt_crc32_ok_all);
BB_DBG(bb, DBG_FA_CNT,
"[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, HE, Total} = {%d, %d, %d, %d, %d, %d}\n",
crc->cnt_cck_crc32_error, crc->cnt_ofdm_crc32_error,
crc->cnt_ht_crc32_error, crc->cnt_vht_crc32_error,
crc->cnt_he_crc32_error, crc->cnt_crc32_error_all);
BB_DBG(bb, DBG_FA_CNT, "[Halbb DM status]===>\n");
BB_DBG(bb, DBG_FA_CNT, "[DIG] IGI=%d\n", stat_info->igi_fa_rssi);
}
void halbb_cnt_reg_reset(struct bb_info *bb)
{
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
/* @reset CCK FA counter */
halbb_set_reg(bb, cr->r1b_rx_rpt_rst, cr->r1b_rx_rpt_rst_m, 0);
halbb_set_reg(bb, cr->r1b_rx_rpt_rst, cr->r1b_rx_rpt_rst_m, 1);
/* @make sure cnt is enable */
halbb_set_reg_phy0_1(bb, cr->enable_all_cnt, cr->enable_all_cnt_m, 1);
/* @reset all bb hw cnt */
halbb_mp_reset_cnt(bb);
}
void halbb_cck_cnt_statistics(struct bb_info *bb)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat_t->bb_fa_i;
struct bb_cck_fa_info *cck_fa = &fa->bb_cck_fa_i;
struct bb_cca_info *cca = &stat_t->bb_cca_i;
struct bb_crc_info *crc = &stat_t->bb_crc_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
u32 ret_value = 0;
#if (defined(HALBB_COMPILE_AP_SERIES) || defined(HALBB_COMPILE_CLIENT_SERIES))
/* select cck dbg port */
halbb_set_reg(bb, cr->r1b_rr_sel, cr->r1b_rr_sel_m, 2);
/* read CCK CCA counter */
ret_value = halbb_get_reg(bb, cr->cck_cca, cr->cck_cca_m);
cca->cnt_cck_cca = ret_value;
/* select cck dbg port */
halbb_set_reg(bb, cr->r1b_rr_sel, cr->r1b_rr_sel_m, 1);
/* read CCK CRC32 counter */
ret_value = halbb_get_reg(bb, cr->cck_crc32ok, MASKDWORD);
crc->cnt_cck_crc32_ok = ret_value & cr->cck_crc32ok_m;
crc->cnt_cck_crc32_error = (ret_value & cr->cck_crc32fail_m) >> 16;
/* Read CCK FA counter */
ret_value = halbb_get_reg(bb, 0x23e0, MASKLWORD); // Reg. doc. doesn't have CCK report reg. 0x78(0x23), need change these addr. one by one
cck_fa->sfd_gg_cnt = ret_value;
ret_value = halbb_get_reg(bb, 0x23e0, MASKHWORD);
cck_fa->cnt_cck_crc_16 = ret_value;
ret_value = halbb_get_reg(bb, 0x23e8, MASKLWORD);
cck_fa->sig_gg_cnt = ret_value;
/* Number of spoofing*/
ret_value = halbb_get_reg(bb, 0x23ec, MASKBYTE0);
cca->cnt_cck_spoofing = ret_value;
//fa->cnt_cck_fail = cck_fa->sfd_gg_cnt + cck_fa->sig_gg_cnt;
/* Adjust FA computation due to repeated caculatation of brk_cnt when pop starting*/
fa->cnt_cck_fail = cca->cnt_cck_cca - crc->cnt_cck_crc32_ok -
crc->cnt_cck_crc32_error - cca->cnt_cck_spoofing;
#elif (defined(HALBB_COMPILE_AP2_SERIES))
/*Wait for b mode report CR docs. preparation*/
#endif
}
void halbb_ofdm_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat_t->bb_fa_i;
struct bb_legacy_fa_info *legacy_fa = &fa->bb_legacy_fa_i;
struct bb_ht_fa_info *ht_fa = &fa->bb_ht_fa_i;
struct bb_vht_fa_info *vht_fa = &fa->bb_vht_fa_i;
struct bb_he_fa_info *he_fa = &fa->bb_he_fa_i;
struct bb_cca_info *cca = &stat_t->bb_cca_i;
struct bb_crc_info *crc = &stat_t->bb_crc_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
u32 ret_value = 0;
/* read OFDM CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->l_crc_ok, MASKDWORD, phy_idx);
crc->cnt_ofdm_crc32_ok = ret_value & cr->l_crc_ok_m;
crc->cnt_ofdm_crc32_error = (ret_value & cr->l_crc_err_m) >> 16;
/* read OFDM2 CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->l_crc_ok2, MASKDWORD, phy_idx);
crc2->cnt_ofdm2_crc32_ok = ret_value & cr->l_crc_ok2_m;
crc2->cnt_ofdm2_crc32_error = (ret_value & cr->l_crc_err2_m) >> 16;
/* read OFDM3 CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->l_crc_ok3, MASKDWORD, phy_idx);
crc2->cnt_ofdm3_crc32_ok = ret_value & cr->l_crc_ok3_m;
crc2->cnt_ofdm3_crc32_error = (ret_value & cr->l_crc_err3_m) >> 16;
/* read HT CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->ht_crc_ok, MASKDWORD, phy_idx);
crc->cnt_ht_crc32_ok = ret_value & cr->ht_crc_ok_m;
crc->cnt_ht_crc32_error = (ret_value & cr->ht_crc_err_m) >> 16;
/* read HT2 CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->ht_crc_ok2, MASKDWORD, phy_idx);
crc2->cnt_ht2_crc32_ok = ret_value & cr->ht_crc_ok2_m;
crc2->cnt_ht2_crc32_error = (ret_value & cr->ht_crc_err2_m) >> 16;
/*read VHT CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->vht_crc_ok, MASKDWORD, phy_idx);
crc->cnt_vht_crc32_ok = ret_value & cr->vht_crc_ok_m;
crc->cnt_vht_crc32_error = (ret_value & cr->vht_crc_err_m) >> 16;
/*read VHT2 CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->vht_crc_ok2, MASKDWORD, phy_idx);
crc2->cnt_vht2_crc32_ok = ret_value & cr->vht_crc_ok2_m;
crc2->cnt_vht2_crc32_error = (ret_value & cr->vht_crc_err2_m) >> 16;
/*read HE CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->he_crc_ok, MASKDWORD, phy_idx);
crc->cnt_he_crc32_ok = ret_value & cr->he_crc_ok_m;
crc->cnt_he_crc32_error = (ret_value & cr->he_crc_err_m) >> 16;
/*read HE2 CRC32 counter */
ret_value = halbb_get_reg_cmn(bb, cr->he_crc_ok2, MASKDWORD, phy_idx);
crc2->cnt_he2_crc32_ok = ret_value & cr->he_crc_ok2_m;
crc2->cnt_he2_crc32_error = (ret_value & cr->he_crc_err2_m) >> 16;
ret_value = halbb_get_reg_cmn(bb, cr->brk, cr->brk_m, phy_idx);
fa->cnt_total_brk = ret_value;
/* Acut workaround because of no HE cnt */
fa->cnt_ofdm_fail= ret_value;
/* @calculate OFDM FA counter instead of reading brk_cnt*/
ret_value = halbb_get_reg_cmn(bb, cr->search_fail, cr->search_fail_m, phy_idx);
legacy_fa->cnt_sb_search_fail = ret_value;
/* Legacy portion */
ret_value = halbb_get_reg_cmn(bb, cr->lsig_brk_s_th, cr->lsig_brk_s_th_m, phy_idx);
legacy_fa->cnt_lsig_brk_s_th = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->lsig_brk_l_th, cr->lsig_brk_l_th_m, phy_idx);
legacy_fa->cnt_lsig_brk_l_th = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->rxl_err_parity, cr->rxl_err_parity_m, phy_idx);
legacy_fa->cnt_parity_fail = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->rxl_err_rate, cr->rxl_err_rate_m, phy_idx);
legacy_fa->cnt_rate_illegal = ret_value;
/* HT portion */
ret_value = halbb_get_reg_cmn(bb, cr->ht_not_support_mcs, cr->ht_not_support_mcs_m, phy_idx);
ht_fa->cnt_mcs_fail = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->htsig_crc8_err_s_th, cr->htsig_crc8_err_s_th_m, phy_idx);
ht_fa->cnt_crc8_fail_s_th = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->htsig_crc8_err_l_th, cr->htsig_crc8_err_l_th_m, phy_idx);
ht_fa->cnt_crc8_fail_l_th = ret_value;
ht_fa->cnt_crc8_fail = ht_fa->cnt_crc8_fail_s_th + ht_fa->cnt_crc8_fail_l_th;
/* VHT portion */
ret_value = halbb_get_reg_cmn(bb, cr->vht_not_support_mcs, cr->vht_not_support_mcs_m, phy_idx);
vht_fa->cnt_mcs_fail_vht = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->vht_err_siga_crc8, cr->vht_err_siga_crc8_m, phy_idx);
vht_fa->cnt_crc8_fail_vhta = ret_value;
#if 0
/* HE portion need to ECO for CBV */
ret_value = halbb_get_reg_cmn(bb, cr->hesu_err_sig_a_crc4, MASKDWORD, phy_idx);
he_fa->cnt_crc4_fail_hea_su = ret_value & cr->hesu_err_sig_a_crc4_m;
he_fa->cnt_crc4_fail_hea_ersu = ret_value & cr->heersu_err_sig_a_crc4_m;
ret_value = halbb_get_reg_cmn(bb, cr->hemu_err_sig_a_crc4, MASKDWORD, phy_idx);
he_fa->cnt_crc4_fail_hea_mu = ret_value & cr->hemu_err_sig_a_crc4_m;
he_fa->cnt_crc4_fail_heb_ch1_mu = (ret_value & cr->hemu_err_sigb_ch1_comm_crc4_m) >> 16;
ret_value = halbb_get_reg_cmn(bb, 0x4a08, cr->hemu_err_sigb_ch1_comm_crc4, phy_idx);
he_fa->cnt_crc4_fail_heb_ch2_mu = ret_value & cr->hemu_err_sigb_ch1_comm_crc4_m;
he_fa->cnt_mcs_fail_he_bcc = ret_value & cr->he_u0_err_bcc_mcs_m;
ret_value = halbb_get_reg_cmn(bb, 0x4a0c, cr->he_u0_err_mcs, phy_idx);
he_fa->cnt_mcs_fail_he = ret_value & cr->he_u0_err_m;
he_fa->cnt_mcs_fail_he_dcm = ret_value & cr->he_u0_err_mcs_m;
fa->cnt_ofdm_fail = legacy_fa->cnt_lsig_brk_s_th +
legacy_fa->cnt_sb_search_fail +
legacy_fa->cnt_lsig_brk_l_th +
legacy_fa->cnt_rate_illegal +
legacy_fa->cnt_parity_fail +
ht_fa->cnt_mcs_fail + ht_fa->cnt_crc8_fail +
vht_fa->cnt_mcs_fail_vht +
vht_fa->cnt_crc8_fail_vhta +
he_fa->cnt_crc4_fail_hea_su +
he_fa->cnt_crc4_fail_hea_ersu +
he_fa->cnt_crc4_fail_hea_mu +
he_fa->cnt_crc4_fail_heb_ch1_mu +
he_fa->cnt_crc4_fail_heb_ch2_mu +
he_fa->cnt_mcs_fail_he_bcc +
he_fa->cnt_mcs_fail_he +
he_fa->cnt_mcs_fail_he_dcm
#endif
/* read OFDM CCA counter */
ret_value = halbb_get_reg_cmn(bb, cr->ofdm_cca, cr->ofdm_cca_m, phy_idx);
cca->cnt_ofdm_cca = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->cca_spoofing, cr->cca_spoofing_m, phy_idx);
cca->cnt_ofdm_spoofing = ret_value;
ret_value = halbb_get_reg_cmn(bb, cr->ampdu_miss, cr->ampdu_miss_m, phy_idx);
crc->cnt_ampdu_miss = ret_value;
/* POP counter */
ret_value = halbb_get_reg_cmn(bb, cr->cnt_pop_trig, cr->cnt_pop_trig_m, phy_idx);
cca->pop_cnt = ret_value;
}
void halbb_cck_tx_cnt_statistics(struct bb_info *bb)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
u32 ret_value = 0;
/* read Tx counter */
ret_value = halbb_get_reg(bb, cr->ccktxon, cr->ccktxon_m);
tx->cck_phy_txon = ret_value;
ret_value = halbb_get_reg(bb, cr->ccktxen, cr->ccktxen_m);
tx->cck_mac_txen = ret_value;
}
void halbb_ofdm_tx_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
u32 ret_value = 0;
/* read Tx counter */
ret_value = halbb_get_reg_cmn(bb, cr->ofdmtxon, MASKDWORD, phy_idx);
tx->ofdm_phy_txon = ret_value & cr->ofdmtxon_m;
tx->ofdm_mac_txen = (ret_value & cr->ofdmtxen_m) >> 16;
}
void halbb_statistics_reset(struct bb_info *bb)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_fa_info *fa = &stat_t->bb_fa_i;
struct bb_cca_info *cca = &stat_t->bb_cca_i;
struct bb_crc_info *crc = &stat_t->bb_crc_i;
struct bb_crc2_info *crc2 = &stat_t->bb_crc2_i;
struct bb_tx_cnt_info *tx = &stat_t->bb_tx_cnt_i;
/* @reset sw mem */
halbb_mem_set(bb, tx, 0, sizeof(struct bb_tx_cnt_info));
halbb_mem_set(bb, fa, 0, sizeof(struct bb_fa_info));
halbb_mem_set(bb, cca, 0, sizeof(struct bb_cca_info));
halbb_mem_set(bb, crc, 0, sizeof(struct bb_crc_info));
halbb_mem_set(bb, crc2, 0, sizeof(struct bb_crc2_info));
}
void halbb_statistics(struct bb_info *bb)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
//char dbg_buf[HALBB_SNPRINT_SIZE] = {0};
u32 tmp = 0;
u8 path_a_ch = 0;
u8 path_b_ch = 0;
bool cck_en = 0;
u8 cck_band_sel = 0;
/* Always turn on*/
if (!(bb->support_ability & BB_FA_CNT))
return;
BB_DBG(bb, DBG_FA_CNT, "[%s]===>\n", __func__);
/*Need to provide API by HALRF . Dino 2020.02.21*/
path_a_ch = (u8)halbb_read_rf_reg(bb, RF_PATH_A, 0x18, 0x3ff);
path_b_ch = (u8)halbb_read_rf_reg(bb, RF_PATH_B, 0x18, 0x3ff);
cck_en = (path_a_ch <= 14) || (path_b_ch <= 14);
cck_band_sel = (u8)halbb_get_reg(bb, cr->dbcc, cr->dbcc_m);
if (bb->hal_com->dbcc_en) {
if (!cck_en) {
halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0);
halbb_ofdm_cnt_statistics(bb, HW_PHY_0);
halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_MAX);
halbb_print_cnt2(bb, HW_PHY_0);
halbb_print_cnt3(bb, HW_PHY_0);
halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_1);
halbb_ofdm_cnt_statistics(bb, HW_PHY_1);
halbb_print_cnt(bb, cck_en, HW_PHY_1, HW_PHY_MAX);
halbb_print_cnt2(bb, HW_PHY_1);
halbb_print_cnt3(bb, HW_PHY_1);
} else {
halbb_cck_tx_cnt_statistics(bb);
halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0);
halbb_cck_cnt_statistics(bb);
halbb_ofdm_cnt_statistics(bb, HW_PHY_0);
halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_0);
halbb_print_cnt2(bb, HW_PHY_0);
halbb_print_cnt3(bb, HW_PHY_0);
halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_1);
halbb_ofdm_cnt_statistics(bb, HW_PHY_1);
halbb_print_cnt(bb, cck_en, HW_PHY_1, HW_PHY_MAX);
halbb_print_cnt2(bb, HW_PHY_1);
halbb_print_cnt3(bb, HW_PHY_1);
}/*else if (cck_en && (cck_band_sel == 1)) {
halbb_cck_cnt_statistics(bb, HW_PHY_1);
halbb_ofdm_cnt_statistics(bb, HW_PHY_0);
halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_1);
halbb_print_cnt2(bb, HW_PHY_0);
halbb_print_cnt3(bb, HW_PHY_0);
}*/
} else {
if (!cck_en) {
halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0);
halbb_ofdm_cnt_statistics(bb, HW_PHY_0);
halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_MAX);
halbb_print_cnt2(bb, HW_PHY_0);
halbb_print_cnt3(bb, HW_PHY_0);
} else {
halbb_cck_tx_cnt_statistics(bb);
halbb_ofdm_tx_cnt_statistics(bb, HW_PHY_0);
halbb_cck_cnt_statistics(bb);
halbb_ofdm_cnt_statistics(bb, HW_PHY_0);
halbb_print_cnt(bb, cck_en, HW_PHY_0, HW_PHY_0);
halbb_print_cnt2(bb, HW_PHY_0);
halbb_print_cnt3(bb, HW_PHY_0);
}
}
/*==52A CBV CCV/52B/52C Rx hang workaround==*/
halbb_chk_hang(bb);
/*================================*/
halbb_cnt_reg_reset(bb);
}
void halbb_statistics_init(struct bb_info *bb)
{
struct bb_stat_info *stat_t = &bb->bb_stat_i;
stat_t->chk_hang_cnt = 0;
stat_t->hang_recovery_en = HANG_RECOVERY;
stat_t->chk_hang_limit = HANG_LIMIT;
halbb_statistics_reset(bb);
halbb_set_crc32_cnt2_rate(bb, BB_06M);
halbb_set_crc32_cnt3_format(bb, STATE_BEACON);
}
void halbb_cr_cfg_stat_init(struct bb_info *bb)
{
struct bb_stat_cr_info *cr = &bb->bb_stat_i.bb_stat_cr_i;
switch (bb->cr_type) {
#ifdef BB_8852A_CAV_SUPPORT
case BB_52AA:
cr->cck_cca = CNT_CCK_CCA_P0_52AA;
cr->cck_cca_m = CNT_CCK_CCA_P0_52AA_M;
cr->cck_crc16fail = CNT_CCK_CRC16FAIL_P0_52AA;
cr->cck_crc16fail_m = CNT_CCK_CRC16FAIL_P0_52AA_M;
cr->cck_crc32ok = CNT_CCK_CRC32OK_P0_52AA;
cr->cck_crc32ok_m = CNT_CCK_CRC32OK_P0_52AA_M;
cr->cck_crc32fail = CNT_CCK_CRC32FAIL_P0_52AA;
cr->cck_crc32fail_m = CNT_CCK_CRC32FAIL_P0_52AA_M;
cr->cca_spoofing = CNT_CCA_SPOOFING_52AA;
cr->cca_spoofing_m = CNT_CCA_SPOOFING_52AA_M;
cr->lsig_brk_s_th = CNT_LSIG_BRK_S_TH_52AA;
cr->lsig_brk_s_th_m = CNT_LSIG_BRK_S_TH_52AA_M;
cr->lsig_brk_l_th = CNT_LSIG_BRK_L_TH_52AA;
cr->lsig_brk_l_th_m = CNT_LSIG_BRK_L_TH_52AA_M;
cr->htsig_crc8_err_s_th = CNT_HTSIG_CRC8_ERR_S_TH_52AA;
cr->htsig_crc8_err_s_th_m = CNT_HTSIG_CRC8_ERR_S_TH_52AA_M;
cr->htsig_crc8_err_l_th = CNT_HTSIG_CRC8_ERR_L_TH_52AA;
cr->htsig_crc8_err_l_th_m = CNT_HTSIG_CRC8_ERR_L_TH_52AA_M;
cr->brk = CNT_BRK_52AA;
cr->brk_m = CNT_BRK_52AA_M;
cr->brk_sel = CNT_BRK_SEL_52AA;
cr->brk_sel_m = CNT_BRK_SEL_52AA_M;
cr->rxl_err_parity = CNT_RXL_ERR_PARITY_52AA;
cr->rxl_err_parity_m = CNT_RXL_ERR_PARITY_52AA_M;
cr->rxl_err_rate = CNT_RXL_ERR_RATE_52AA;
cr->rxl_err_rate_m = CNT_RXL_ERR_RATE_52AA_M;
cr->ht_err_crc8 = CNT_HT_ERR_CRC8_52AA;
cr->ht_err_crc8_m = CNT_HT_ERR_CRC8_52AA_M;
cr->vht_err_siga_crc8 = CNT_VHT_ERR_SIGA_CRC8_52AA;
cr->vht_err_siga_crc8_m = CNT_VHT_ERR_SIGA_CRC8_52AA_M;
cr->ht_not_support_mcs = CNT_HT_NOT_SUPPORT_MCS_52AA;
cr->ht_not_support_mcs_m = CNT_HT_NOT_SUPPORT_MCS_52AA_M;
cr->vht_not_support_mcs = CNT_VHT_NOT_SUPPORT_MCS_52AA;
cr->vht_not_support_mcs_m = CNT_VHT_NOT_SUPPORT_MCS_52AA_M;
cr->err_during_bt_tx = CNT_ERR_DURING_BT_TX_52AA;
cr->err_during_bt_tx_m = CNT_ERR_DURING_BT_TX_52AA_M;
cr->err_during_bt_rx = CNT_ERR_DURING_BT_RX_52AA;
cr->err_during_bt_rx_m = CNT_ERR_DURING_BT_RX_52AA_M;
cr->edge_murx_nsts0 = CNT_EDGE_MURX_NSTS0_52AA;
cr->edge_murx_nsts0_m = CNT_EDGE_MURX_NSTS0_52AA_M;
cr->search_fail = CNT_SEARCH_FAIL_52AA;
cr->search_fail_m = CNT_SEARCH_FAIL_52AA_M;
cr->ofdm_cca = CNT_OFDM_CCA_52AA;
cr->ofdm_cca_m = CNT_OFDM_CCA_52AA_M;
cr->ofdm_cca_s20 = CNT_OFDM_CCA_S20_52AA;
cr->ofdm_cca_s20_m = CNT_OFDM_CCA_S20_52AA_M;
cr->ofdm_cca_s40 = CNT_OFDM_CCA_S40_52AA;
cr->ofdm_cca_s40_m = CNT_OFDM_CCA_S40_52AA_M;
cr->ofdm_cca_s80 = CNT_OFDM_CCA_S80_52AA;
cr->ofdm_cca_s80_m = CNT_OFDM_CCA_S80_52AA_M;
cr->ofdmtxon = CNT_OFDMTXON_52AA;
cr->ofdmtxon_m = CNT_OFDMTXON_52AA_M;
cr->ofdmtxen = CNT_OFDMTXEN_52AA;
cr->ofdmtxen_m = CNT_OFDMTXEN_52AA_M;
cr->drop_trig = CNT_DROP_TRIG_52AA;
cr->drop_trig_m = CNT_DROP_TRIG_52AA_M;
cr->pop_trig = CNT_POP_TRIG_52AA;
cr->pop_trig_m = CNT_POP_TRIG_52AA_M;
cr->tx_conflict = CNT_TX_CONFLICT_52AA;
cr->tx_conflict_m = CNT_TX_CONFLICT_52AA_M;
cr->wmac_rstb = CNT_WMAC_RSTB_52AA;
cr->wmac_rstb_m = CNT_WMAC_RSTB_52AA_M;
cr->en_tb_ppdu_fix_gain = CNT_EN_TB_PPDU_FIX_GAIN_52AA;
cr->en_tb_ppdu_fix_gain_m = CNT_EN_TB_PPDU_FIX_GAIN_52AA_M;
cr->en_tb_cca_pw_th = CNT_EN_TB_CCA_PW_TH_52AA;
cr->en_tb_cca_pw_th_m = CNT_EN_TB_CCA_PW_TH_52AA_M;
cr->he_crc_ok = CNT_HE_CRC_OK_52AA;
cr->he_crc_ok_m = CNT_HE_CRC_OK_52AA_M;
cr->he_crc_err = CNT_HE_CRC_ERR_52AA;
cr->he_crc_err_m = CNT_HE_CRC_ERR_52AA_M;
cr->vht_crc_ok = CNT_VHT_CRC_OK_52AA;
cr->vht_crc_ok_m = CNT_VHT_CRC_OK_52AA_M;
cr->vht_crc_err = CNT_VHT_CRC_ERR_52AA;
cr->vht_crc_err_m = CNT_VHT_CRC_ERR_52AA_M;
cr->ht_crc_ok = CNT_HT_CRC_OK_52AA;
cr->ht_crc_ok_m = CNT_HT_CRC_OK_52AA_M;
cr->ht_crc_err = CNT_HT_CRC_ERR_52AA;
cr->ht_crc_err_m = CNT_HT_CRC_ERR_52AA_M;
cr->l_crc_ok = CNT_L_CRC_OK_52AA;
cr->l_crc_ok_m = CNT_L_CRC_OK_52AA_M;
cr->l_crc_err = CNT_L_CRC_ERR_52AA;
cr->l_crc_err_m = CNT_L_CRC_ERR_52AA_M;
cr->he_crc_ok2 = CNT_HE_CRC_OK2_52AA;
cr->he_crc_ok2_m = CNT_HE_CRC_OK2_52AA_M;
cr->he_crc_err2 = CNT_HE_CRC_ERR2_52AA;
cr->he_crc_err2_m = CNT_HE_CRC_ERR2_52AA_M;
cr->vht_crc_ok2 = CNT_VHT_CRC_OK2_52AA;
cr->vht_crc_ok2_m = CNT_VHT_CRC_OK2_52AA_M;
cr->vht_crc_err2 = CNT_VHT_CRC_ERR2_52AA;
cr->vht_crc_err2_m = CNT_VHT_CRC_ERR2_52AA_M;
cr->ht_crc_ok2 = CNT_HT_CRC_OK2_52AA;
cr->ht_crc_ok2_m = CNT_HT_CRC_OK2_52AA_M;
cr->ht_crc_err2 = CNT_HT_CRC_ERR2_52AA;
cr->ht_crc_err2_m = CNT_HT_CRC_ERR2_52AA_M;
cr->l_crc_ok2 = CNT_L_CRC_OK2_52AA;
cr->l_crc_ok2_m = CNT_L_CRC_OK2_52AA_M;
cr->l_crc_err2 = CNT_L_CRC_ERR2_52AA;
cr->l_crc_err2_m = CNT_L_CRC_ERR2_52AA_M;
cr->l_crc_ok3 = CNT_L_CRC_OK3_52AA;
cr->l_crc_ok3_m = CNT_L_CRC_OK3_52AA_M;
cr->l_crc_err3 = CNT_L_CRC_ERR3_52AA;
cr->l_crc_err3_m = CNT_L_CRC_ERR3_52AA_M;
cr->ampdu_rxon = CNT_AMPDU_RXON_52AA;
cr->ampdu_rxon_m = CNT_AMPDU_RXON_52AA_M;
cr->ampdu_miss = CNT_AMPDU_MISS_52AA;
cr->ampdu_miss_m = CNT_AMPDU_MISS_52AA_M;
cr->hesu_err_sig_a_crc4 = CNT_HESU_ERR_SIG_A_CRC4_52AA;
cr->hesu_err_sig_a_crc4_m = CNT_HESU_ERR_SIG_A_CRC4_52AA_M;
cr->heersu_err_sig_a_crc4 = CNT_HEERSU_ERR_SIG_A_CRC4_52AA;
cr->heersu_err_sig_a_crc4_m = CNT_HEERSU_ERR_SIG_A_CRC4_52AA_M;
cr->hemu_err_sig_a_crc4 = CNT_HEMU_ERR_SIG_A_CRC4_52AA;
cr->hemu_err_sig_a_crc4_m = CNT_HEMU_ERR_SIG_A_CRC4_52AA_M;
cr->hemu_err_sigb_ch1_comm_crc4 = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_52AA;
cr->hemu_err_sigb_ch1_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_52AA_M;
cr->hemu_err_sigb_ch2_comm_crc4 = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_52AA;
cr->hemu_err_sigb_ch2_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_52AA_M;
cr->he_u0_err_bcc_mcs = CNT_HE_U0_ERR_BCC_MCS_52AA;
cr->he_u0_err_bcc_mcs_m = CNT_HE_U0_ERR_BCC_MCS_52AA_M;
cr->he_u0_err_mcs = CNT_HE_U0_ERR_MCS_52AA;
cr->he_u0_err_mcs_m = CNT_HE_U0_ERR_MCS_52AA_M;
cr->he_u0_err_dcm_mcs = CNT_HE_U0_ERR_DCM_MCS_52AA;
cr->he_u0_err_dcm_mcs_m = CNT_HE_U0_ERR_DCM_MCS_52AA_M;
cr->r1b_rx_rpt_rst = R1B_RX_RPT_RST_52AA;
cr->r1b_rx_rpt_rst_m = R1B_RX_RPT_RST_52AA_M;
cr->r1b_rr_sel = R1B_RR_SEL_52AA;
cr->r1b_rr_sel_m = R1B_RR_SEL_52AA_M;
cr->rst_all_cnt = RST_ALL_CNT_52AA;
cr->rst_all_cnt_m = RST_ALL_CNT_52AA_M;
cr->enable_all_cnt = ENABLE_ALL_CNT_52AA;
cr->enable_all_cnt_m = ENABLE_ALL_CNT_52AA_M;
cr->enable_ofdm = ENABLE_OFDM_52AA;
cr->enable_ofdm_m = ENABLE_OFDM_52AA_M;
cr->enable_cck = ENABLE_CCK_52AA;
cr->enable_cck_m = ENABLE_CCK_52AA_M;
cr->r1b_rx_dis_cca = R1B_RX_DIS_CCA_52AA;
cr->r1b_rx_dis_cca_m = R1B_RX_DIS_CCA_52AA_M;
cr->intf_r_rate = INTF_R_CNT_RATE_52AA;
cr->intf_r_rate_m = INTF_R_CNT_RATE_52AA_M;
cr->intf_r_mcs = INTF_R_CNT_MCS_52AA;
cr->intf_r_mcs_m = INTF_R_CNT_MCS_52AA_M;
cr->intf_r_vht_mcs = INTF_R_CNT_VHT_MCS_52AA;
cr->intf_r_vht_mcs_m = INTF_R_CNT_VHT_MCS_52AA_M;
cr->intf_r_he_mcs = INTF_R_CNT_HE_MCS_52AA;
cr->intf_r_he_mcs_m = INTF_R_CNT_HE_MCS_52AA_M;
cr->intf_r_vht_nss = INTF_R_CNT_VHT_NSS_52AA;
cr->intf_r_vht_nss_m = INTF_R_CNT_VHT_NSS_52AA_M;
cr->intf_r_he_nss = INTF_R_CNT_HE_NSS_52AA;
cr->intf_r_he_nss_m = INTF_R_CNT_HE_NSS_52AA_M;
cr->intf_r_mac_hdr_type = INTF_R_MAC_HDR_TYPE_52AA;
cr->intf_r_mac_hdr_type_m = INTF_R_MAC_HDR_TYPE_52AA_M;
cr->intf_r_pkt_type = INTF_R_PKT_TYPE_52AA;
cr->intf_r_pkt_type_m = INTF_R_PKT_TYPE_52AA_M;
cr->dbcc = DBCC_52AA;
cr->dbcc_m = DBCC_52AA_M;
cr->dbcc_2p4g_band_sel = DBCC_2P4G_BAND_SEL_52AA;
cr->dbcc_2p4g_band_sel_m = DBCC_2P4G_BAND_SEL_52AA_M;
cr->max_cnt_pop = MAX_CNT_POP_52AA;
cr->max_cnt_pop_m = MAX_CNT_POP_52AA_M;
break;
#endif
#ifdef HALBB_COMPILE_AP_SERIES
case BB_AP:
cr->cck_cca = CNT_CCK_CCA_P0_A;
cr->cck_cca_m = CNT_CCK_CCA_P0_A_M;
cr->cck_crc16fail = CNT_CCK_CRC16FAIL_P0_A;
cr->cck_crc16fail_m = CNT_CCK_CRC16FAIL_P0_A_M;
cr->cck_crc32ok = CNT_CCK_CRC32OK_P0_A;
cr->cck_crc32ok_m = CNT_CCK_CRC32OK_P0_A_M;
cr->cck_crc32fail = CNT_CCK_CRC32FAIL_P0_A;
cr->cck_crc32fail_m = CNT_CCK_CRC32FAIL_P0_A_M;
cr->cca_spoofing = CNT_CCA_SPOOFING_A;
cr->cca_spoofing_m = CNT_CCA_SPOOFING_A_M;
cr->lsig_brk_s_th = CNT_LSIG_BRK_S_TH_A;
cr->lsig_brk_s_th_m = CNT_LSIG_BRK_S_TH_A_M;
cr->lsig_brk_l_th = CNT_LSIG_BRK_L_TH_A;
cr->lsig_brk_l_th_m = CNT_LSIG_BRK_L_TH_A_M;
cr->htsig_crc8_err_s_th = CNT_HTSIG_CRC8_ERR_S_TH_A;
cr->htsig_crc8_err_s_th_m = CNT_HTSIG_CRC8_ERR_S_TH_A_M;
cr->htsig_crc8_err_l_th = CNT_HTSIG_CRC8_ERR_L_TH_A;
cr->htsig_crc8_err_l_th_m = CNT_HTSIG_CRC8_ERR_L_TH_A_M;
cr->brk = CNT_BRK_A;
cr->brk_m = CNT_BRK_A_M;
cr->brk_sel = CNT_BRK_SEL_A;
cr->brk_sel_m = CNT_BRK_SEL_A_M;
cr->rxl_err_parity = CNT_RXL_ERR_PARITY_A;
cr->rxl_err_parity_m = CNT_RXL_ERR_PARITY_A_M;
cr->rxl_err_rate = CNT_RXL_ERR_RATE_A;
cr->rxl_err_rate_m = CNT_RXL_ERR_RATE_A_M;
cr->ht_err_crc8 = CNT_HT_ERR_CRC8_A;
cr->ht_err_crc8_m = CNT_HT_ERR_CRC8_A_M;
cr->vht_err_siga_crc8 = CNT_VHT_ERR_SIGA_CRC8_A;
cr->vht_err_siga_crc8_m = CNT_VHT_ERR_SIGA_CRC8_A_M;
cr->ht_not_support_mcs = CNT_HT_NOT_SUPPORT_MCS_A;
cr->ht_not_support_mcs_m = CNT_HT_NOT_SUPPORT_MCS_A_M;
cr->vht_not_support_mcs = CNT_VHT_NOT_SUPPORT_MCS_A;
cr->vht_not_support_mcs_m = CNT_VHT_NOT_SUPPORT_MCS_A_M;
cr->err_during_bt_tx = CNT_ERR_DURING_BT_TX_A;
cr->err_during_bt_tx_m = CNT_ERR_DURING_BT_TX_A_M;
cr->err_during_bt_rx = CNT_ERR_DURING_BT_RX_A;
cr->err_during_bt_rx_m = CNT_ERR_DURING_BT_RX_A_M;
cr->edge_murx_nsts0 = CNT_EDGE_MURX_NSTS0_A;
cr->edge_murx_nsts0_m = CNT_EDGE_MURX_NSTS0_A_M;
cr->search_fail = CNT_SEARCH_FAIL_A;
cr->search_fail_m = CNT_SEARCH_FAIL_A_M;
cr->ofdm_cca = CNT_OFDM_CCA_A;
cr->ofdm_cca_m = CNT_OFDM_CCA_A_M;
cr->ofdm_cca_s20 = CNT_OFDM_CCA_S20_A;
cr->ofdm_cca_s20_m = CNT_OFDM_CCA_S20_A_M;
cr->ofdm_cca_s40 = CNT_OFDM_CCA_S40_A;
cr->ofdm_cca_s40_m = CNT_OFDM_CCA_S40_A_M;
cr->ofdm_cca_s80 = CNT_OFDM_CCA_S80_A;
cr->ofdm_cca_s80_m = CNT_OFDM_CCA_S80_A_M;
cr->ccktxon = CNT_CCKTXON_A;
cr->ccktxon_m = CNT_CCKTXON_A_M;
cr->ccktxen = CNT_CCKTXEN_A;
cr->ccktxen_m = CNT_CCKTXEN_A_M;
cr->ofdmtxon = CNT_OFDMTXON_A;
cr->ofdmtxon_m = CNT_OFDMTXON_A_M;
cr->ofdmtxen = CNT_OFDMTXEN_A;
cr->ofdmtxen_m = CNT_OFDMTXEN_A_M;
cr->drop_trig = CNT_DROP_TRIG_A;
cr->drop_trig_m = CNT_DROP_TRIG_A_M;
cr->pop_trig = CNT_POP_TRIG_A;
cr->pop_trig_m = CNT_POP_TRIG_A_M;
cr->tx_conflict = CNT_TX_CONFLICT_A;
cr->tx_conflict_m = CNT_TX_CONFLICT_A_M;
cr->wmac_rstb = CNT_WMAC_RSTB_A;
cr->wmac_rstb_m = CNT_WMAC_RSTB_A_M;
cr->en_tb_ppdu_fix_gain = CNT_EN_TB_PPDU_FIX_GAIN_A;
cr->en_tb_ppdu_fix_gain_m = CNT_EN_TB_PPDU_FIX_GAIN_A_M;
cr->en_tb_cca_pw_th = CNT_EN_TB_CCA_PW_TH_A;
cr->en_tb_cca_pw_th_m = CNT_EN_TB_CCA_PW_TH_A_M;
cr->he_crc_ok = CNT_HE_CRC_OK_A;
cr->he_crc_ok_m = CNT_HE_CRC_OK_A_M;
cr->he_crc_err = CNT_HE_CRC_ERR_A;
cr->he_crc_err_m = CNT_HE_CRC_ERR_A_M;
cr->vht_crc_ok = CNT_VHT_CRC_OK_A;
cr->vht_crc_ok_m = CNT_VHT_CRC_OK_A_M;
cr->vht_crc_err = CNT_VHT_CRC_ERR_A;
cr->vht_crc_err_m = CNT_VHT_CRC_ERR_A_M;
cr->ht_crc_ok = CNT_HT_CRC_OK_A;
cr->ht_crc_ok_m = CNT_HT_CRC_OK_A_M;
cr->ht_crc_err = CNT_HT_CRC_ERR_A;
cr->ht_crc_err_m = CNT_HT_CRC_ERR_A_M;
cr->l_crc_ok = CNT_L_CRC_OK_A;
cr->l_crc_ok_m = CNT_L_CRC_OK_A_M;
cr->l_crc_err = CNT_L_CRC_ERR_A;
cr->l_crc_err_m = CNT_L_CRC_ERR_A_M;
cr->he_crc_ok2 = CNT_HE_CRC_OK2_A;
cr->he_crc_ok2_m = CNT_HE_CRC_OK2_A_M;
cr->he_crc_err2 = CNT_HE_CRC_ERR2_A;
cr->he_crc_err2_m = CNT_HE_CRC_ERR2_A_M;
cr->vht_crc_ok2 = CNT_VHT_CRC_OK2_A;
cr->vht_crc_ok2_m = CNT_VHT_CRC_OK2_A_M;
cr->vht_crc_err2 = CNT_VHT_CRC_ERR2_A;
cr->vht_crc_err2_m = CNT_VHT_CRC_ERR2_A_M;
cr->ht_crc_ok2 = CNT_HT_CRC_OK2_A;
cr->ht_crc_ok2_m = CNT_HT_CRC_OK2_A_M;
cr->ht_crc_err2 = CNT_HT_CRC_ERR2_A;
cr->ht_crc_err2_m = CNT_HT_CRC_ERR2_A_M;
cr->l_crc_ok2 = CNT_L_CRC_OK2_A;
cr->l_crc_ok2_m = CNT_L_CRC_OK2_A_M;
cr->l_crc_err2 = CNT_L_CRC_ERR2_A;
cr->l_crc_err2_m = CNT_L_CRC_ERR2_A_M;
cr->l_crc_ok3 = CNT_L_CRC_OK3_A;
cr->l_crc_ok3_m = CNT_L_CRC_OK3_A_M;
cr->l_crc_err3 = CNT_L_CRC_ERR3_A;
cr->l_crc_err3_m = CNT_L_CRC_ERR3_A_M;
cr->ampdu_rxon = CNT_AMPDU_RXON_A;
cr->ampdu_rxon_m = CNT_AMPDU_RXON_A_M;
cr->ampdu_miss = CNT_AMPDU_MISS_A;
cr->ampdu_miss_m = CNT_AMPDU_MISS_A_M;
cr->hesu_err_sig_a_crc4 = CNT_HESU_ERR_SIG_A_CRC4_A;
cr->hesu_err_sig_a_crc4_m = CNT_HESU_ERR_SIG_A_CRC4_A_M;
cr->heersu_err_sig_a_crc4 = CNT_HEERSU_ERR_SIG_A_CRC4_A;
cr->heersu_err_sig_a_crc4_m = CNT_HEERSU_ERR_SIG_A_CRC4_A_M;
cr->hemu_err_sig_a_crc4 = CNT_HEMU_ERR_SIG_A_CRC4_A;
cr->hemu_err_sig_a_crc4_m = CNT_HEMU_ERR_SIG_A_CRC4_A_M;
cr->hemu_err_sigb_ch1_comm_crc4 = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_A;
cr->hemu_err_sigb_ch1_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_A_M;
cr->hemu_err_sigb_ch2_comm_crc4 = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_A;
cr->hemu_err_sigb_ch2_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_A_M;
cr->he_u0_err_bcc_mcs = CNT_HE_U0_ERR_BCC_MCS_A;
cr->he_u0_err_bcc_mcs_m = CNT_HE_U0_ERR_BCC_MCS_A_M;
cr->he_u0_err_mcs = CNT_HE_U0_ERR_MCS_A;
cr->he_u0_err_mcs_m = CNT_HE_U0_ERR_MCS_A_M;
cr->he_u0_err_dcm_mcs = CNT_HE_U0_ERR_DCM_MCS_A;
cr->he_u0_err_dcm_mcs_m = CNT_HE_U0_ERR_DCM_MCS_A_M;
cr->r1b_rx_rpt_rst = R1B_RX_RPT_RST_A;
cr->r1b_rx_rpt_rst_m = R1B_RX_RPT_RST_A_M;
cr->r1b_rr_sel = R1B_RR_SEL_A;
cr->r1b_rr_sel_m = R1B_RR_SEL_A_M;
cr->rst_all_cnt = RST_ALL_CNT_A;
cr->rst_all_cnt_m = RST_ALL_CNT_A_M;
cr->enable_all_cnt = ENABLE_ALL_CNT_A;
cr->enable_all_cnt_m = ENABLE_ALL_CNT_A_M;
cr->enable_ofdm = ENABLE_OFDM_A;
cr->enable_ofdm_m = ENABLE_OFDM_A_M;
cr->enable_cck = ENABLE_CCK_A;
cr->enable_cck_m = ENABLE_CCK_A_M;
cr->r1b_rx_dis_cca = R1B_RX_DIS_CCA_A;
cr->r1b_rx_dis_cca_m = R1B_RX_DIS_CCA_A_M;
cr->intf_r_rate = INTF_R_CNT_RATE_A;
cr->intf_r_rate_m = INTF_R_CNT_RATE_A_M;
cr->intf_r_mcs = INTF_R_CNT_MCS_A;
cr->intf_r_mcs_m = INTF_R_CNT_MCS_A_M;
cr->intf_r_vht_mcs = INTF_R_CNT_VHT_MCS_A;
cr->intf_r_vht_mcs_m = INTF_R_CNT_VHT_MCS_A_M;
cr->intf_r_he_mcs = INTF_R_CNT_HE_MCS_A;
cr->intf_r_he_mcs_m = INTF_R_CNT_HE_MCS_A_M;
cr->intf_r_vht_nss = INTF_R_CNT_VHT_NSS_A;
cr->intf_r_vht_nss_m = INTF_R_CNT_VHT_NSS_A_M;
cr->intf_r_he_nss = INTF_R_CNT_HE_NSS_A;
cr->intf_r_he_nss_m = INTF_R_CNT_HE_NSS_A_M;
cr->intf_r_mac_hdr_type = INTF_R_MAC_HDR_TYPE_A;
cr->intf_r_mac_hdr_type_m = INTF_R_MAC_HDR_TYPE_A_M;
cr->intf_r_pkt_type = INTF_R_PKT_TYPE_A;
cr->intf_r_pkt_type_m = INTF_R_PKT_TYPE_A_M;
cr->dbcc = DBCC_A;
cr->dbcc_m = DBCC_A_M;
cr->dbcc_2p4g_band_sel = DBCC_2P4G_BAND_SEL_A;
cr->dbcc_2p4g_band_sel_m = DBCC_2P4G_BAND_SEL_A_M;
cr->cnt_pop_trig = CNT_POP_TRIG_A;
cr->cnt_pop_trig_m = CNT_POP_TRIG_A_M;
cr->max_cnt_pop = MAX_CNT_POP_A;
cr->max_cnt_pop_m = MAX_CNT_POP_A_M;
break;
#endif
#ifdef HALBB_COMPILE_CLIENT_SERIES
case BB_CLIENT:
cr->cck_cca = CNT_CCK_CCA_P0_C;
cr->cck_cca_m = CNT_CCK_CCA_P0_C_M;
cr->cck_crc16fail = CNT_CCK_CRC16FAIL_P0_C;
cr->cck_crc16fail_m = CNT_CCK_CRC16FAIL_P0_C_M;
cr->cck_crc32ok = CNT_CCK_CRC32OK_P0_C;
cr->cck_crc32ok_m = CNT_CCK_CRC32OK_P0_C_M;
cr->cck_crc32fail = CNT_CCK_CRC32FAIL_P0_C;
cr->cck_crc32fail_m = CNT_CCK_CRC32FAIL_P0_C_M;
cr->cca_spoofing = CNT_CCA_SPOOFING_C;
cr->cca_spoofing_m = CNT_CCA_SPOOFING_C_M;
cr->lsig_brk_s_th = CNT_LSIG_BRK_S_TH_C;
cr->lsig_brk_s_th_m = CNT_LSIG_BRK_S_TH_C_M;
cr->lsig_brk_l_th = CNT_LSIG_BRK_L_TH_C;
cr->lsig_brk_l_th_m = CNT_LSIG_BRK_L_TH_C_M;
cr->htsig_crc8_err_s_th = CNT_HTSIG_CRC8_ERR_S_TH_C;
cr->htsig_crc8_err_s_th_m = CNT_HTSIG_CRC8_ERR_S_TH_C_M;
cr->htsig_crc8_err_l_th = CNT_HTSIG_CRC8_ERR_L_TH_C;
cr->htsig_crc8_err_l_th_m = CNT_HTSIG_CRC8_ERR_L_TH_C_M;
cr->brk = CNT_BRK_C;
cr->brk_m = CNT_BRK_C_M;
cr->brk_sel = CNT_BRK_SEL_C;
cr->brk_sel_m = CNT_BRK_SEL_C_M;
cr->rxl_err_parity = CNT_RXL_ERR_PARITY_C;
cr->rxl_err_parity_m = CNT_RXL_ERR_PARITY_C_M;
cr->rxl_err_rate = CNT_RXL_ERR_RATE_C;
cr->rxl_err_rate_m = CNT_RXL_ERR_RATE_C_M;
cr->ht_err_crc8 = CNT_HT_ERR_CRC8_C;
cr->ht_err_crc8_m = CNT_HT_ERR_CRC8_C_M;
cr->vht_err_siga_crc8 = CNT_VHT_ERR_SIGA_CRC8_C;
cr->vht_err_siga_crc8_m = CNT_VHT_ERR_SIGA_CRC8_C_M;
cr->ht_not_support_mcs = CNT_HT_NOT_SUPPORT_MCS_C;
cr->ht_not_support_mcs_m = CNT_HT_NOT_SUPPORT_MCS_C_M;
cr->vht_not_support_mcs = CNT_VHT_NOT_SUPPORT_MCS_C;
cr->vht_not_support_mcs_m = CNT_VHT_NOT_SUPPORT_MCS_C_M;
cr->err_during_bt_tx = CNT_ERR_DURING_BT_TX_C;
cr->err_during_bt_tx_m = CNT_ERR_DURING_BT_TX_C_M;
cr->err_during_bt_rx = CNT_ERR_DURING_BT_RX_C;
cr->err_during_bt_rx_m = CNT_ERR_DURING_BT_RX_C_M;
cr->edge_murx_nsts0 = CNT_EDGE_MURX_NSTS0_C;
cr->edge_murx_nsts0_m = CNT_EDGE_MURX_NSTS0_C_M;
cr->search_fail = CNT_SEARCH_FAIL_C;
cr->search_fail_m = CNT_SEARCH_FAIL_C_M;
cr->ofdm_cca = CNT_OFDM_CCA_C;
cr->ofdm_cca_m = CNT_OFDM_CCA_C_M;
cr->ofdm_cca_s20 = CNT_OFDM_CCA_S20_C;
cr->ofdm_cca_s20_m = CNT_OFDM_CCA_S20_C_M;
cr->ofdm_cca_s40 = CNT_OFDM_CCA_S40_C;
cr->ofdm_cca_s40_m = CNT_OFDM_CCA_S40_C_M;
cr->ofdm_cca_s80 = CNT_OFDM_CCA_S80_C;
cr->ofdm_cca_s80_m = CNT_OFDM_CCA_S80_C_M;
cr->ccktxon = CNT_CCKTXON_C;
cr->ccktxon_m = CNT_CCKTXON_C_M;
cr->ccktxen = CNT_CCKTXEN_C;
cr->ccktxen_m = CNT_CCKTXEN_C_M;
cr->ofdmtxon = CNT_OFDMTXON_C;
cr->ofdmtxon_m = CNT_OFDMTXON_C_M;
cr->ofdmtxen = CNT_OFDMTXEN_C;
cr->ofdmtxen_m = CNT_OFDMTXEN_C_M;
cr->drop_trig = CNT_DROP_TRIG_C;
cr->drop_trig_m = CNT_DROP_TRIG_C_M;
cr->pop_trig = CNT_POP_TRIG_C;
cr->pop_trig_m = CNT_POP_TRIG_C_M;
cr->tx_conflict = CNT_TX_CONFLICT_C;
cr->tx_conflict_m = CNT_TX_CONFLICT_C_M;
cr->wmac_rstb = CNT_WMAC_RSTB_C;
cr->wmac_rstb_m = CNT_WMAC_RSTB_C_M;
cr->en_tb_ppdu_fix_gain = CNT_EN_TB_PPDU_FIX_GAIN_C;
cr->en_tb_ppdu_fix_gain_m = CNT_EN_TB_PPDU_FIX_GAIN_C_M;
cr->en_tb_cca_pw_th = CNT_EN_TB_CCA_PW_TH_C;
cr->en_tb_cca_pw_th_m = CNT_EN_TB_CCA_PW_TH_C_M;
cr->he_crc_ok = CNT_HE_CRC_OK_C;
cr->he_crc_ok_m = CNT_HE_CRC_OK_C_M;
cr->he_crc_err = CNT_HE_CRC_ERR_C;
cr->he_crc_err_m = CNT_HE_CRC_ERR_C_M;
cr->vht_crc_ok = CNT_VHT_CRC_OK_C;
cr->vht_crc_ok_m = CNT_VHT_CRC_OK_C_M;
cr->vht_crc_err = CNT_VHT_CRC_ERR_C;
cr->vht_crc_err_m = CNT_VHT_CRC_ERR_C_M;
cr->ht_crc_ok = CNT_HT_CRC_OK_C;
cr->ht_crc_ok_m = CNT_HT_CRC_OK_C_M;
cr->ht_crc_err = CNT_HT_CRC_ERR_C;
cr->ht_crc_err_m = CNT_HT_CRC_ERR_C_M;
cr->l_crc_ok = CNT_L_CRC_OK_C;
cr->l_crc_ok_m = CNT_L_CRC_OK_C_M;
cr->l_crc_err = CNT_L_CRC_ERR_C;
cr->l_crc_err_m = CNT_L_CRC_ERR_C_M;
cr->he_crc_ok2 = CNT_HE_CRC_OK2_C;
cr->he_crc_ok2_m = CNT_HE_CRC_OK2_C_M;
cr->he_crc_err2 = CNT_HE_CRC_ERR2_C;
cr->he_crc_err2_m = CNT_HE_CRC_ERR2_C_M;
cr->vht_crc_ok2 = CNT_VHT_CRC_OK2_C;
cr->vht_crc_ok2_m = CNT_VHT_CRC_OK2_C_M;
cr->vht_crc_err2 = CNT_VHT_CRC_ERR2_C;
cr->vht_crc_err2_m = CNT_VHT_CRC_ERR2_C_M;
cr->ht_crc_ok2 = CNT_HT_CRC_OK2_C;
cr->ht_crc_ok2_m = CNT_HT_CRC_OK2_C_M;
cr->ht_crc_err2 = CNT_HT_CRC_ERR2_C;
cr->ht_crc_err2_m = CNT_HT_CRC_ERR2_C_M;
cr->l_crc_ok2 = CNT_L_CRC_OK2_C;
cr->l_crc_ok2_m = CNT_L_CRC_OK2_C_M;
cr->l_crc_err2 = CNT_L_CRC_ERR2_C;
cr->l_crc_err2_m = CNT_L_CRC_ERR2_C_M;
cr->l_crc_ok3 = CNT_L_CRC_OK3_C;
cr->l_crc_ok3_m = CNT_L_CRC_OK3_C_M;
cr->l_crc_err3 = CNT_L_CRC_ERR3_C;
cr->l_crc_err3_m = CNT_L_CRC_ERR3_C_M;
cr->ampdu_rxon = CNT_AMPDU_RXON_C;
cr->ampdu_rxon_m = CNT_AMPDU_RXON_C_M;
cr->ampdu_miss = CNT_AMPDU_MISS_C;
cr->ampdu_miss_m = CNT_AMPDU_MISS_C_M;
cr->hesu_err_sig_a_crc4 = CNT_HESU_ERR_SIG_A_CRC4_C;
cr->hesu_err_sig_a_crc4_m = CNT_HESU_ERR_SIG_A_CRC4_C_M;
cr->heersu_err_sig_a_crc4 = CNT_HEERSU_ERR_SIG_A_CRC4_C;
cr->heersu_err_sig_a_crc4_m = CNT_HEERSU_ERR_SIG_A_CRC4_C_M;
cr->hemu_err_sig_a_crc4 = CNT_HEMU_ERR_SIG_A_CRC4_C;
cr->hemu_err_sig_a_crc4_m = CNT_HEMU_ERR_SIG_A_CRC4_C_M;
cr->hemu_err_sigb_ch1_comm_crc4 = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C;
cr->hemu_err_sigb_ch1_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C_M;
cr->hemu_err_sigb_ch2_comm_crc4 = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C;
cr->hemu_err_sigb_ch2_comm_crc4_m = CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C_M;
cr->he_u0_err_bcc_mcs = CNT_HE_U0_ERR_BCC_MCS_C;
cr->he_u0_err_bcc_mcs_m = CNT_HE_U0_ERR_BCC_MCS_C_M;
cr->he_u0_err_mcs = CNT_HE_U0_ERR_MCS_C;
cr->he_u0_err_mcs_m = CNT_HE_U0_ERR_MCS_C_M;
cr->he_u0_err_dcm_mcs = CNT_HE_U0_ERR_DCM_MCS_C;
cr->he_u0_err_dcm_mcs_m = CNT_HE_U0_ERR_DCM_MCS_C_M;
cr->r1b_rx_rpt_rst = R1B_RX_RPT_RST_C;
cr->r1b_rx_rpt_rst_m = R1B_RX_RPT_RST_C_M;
cr->r1b_rr_sel = R1B_RR_SEL_C;
cr->r1b_rr_sel_m = R1B_RR_SEL_C_M;
cr->rst_all_cnt = RST_ALL_CNT_C;
cr->rst_all_cnt_m = RST_ALL_CNT_C_M;
cr->enable_all_cnt = ENABLE_ALL_CNT_C;
cr->enable_all_cnt_m = ENABLE_ALL_CNT_C_M;
cr->enable_ofdm = ENABLE_OFDM_C;
cr->enable_ofdm_m = ENABLE_OFDM_C_M;
cr->enable_cck = ENABLE_CCK_C;
cr->enable_cck_m = ENABLE_CCK_C_M;
cr->r1b_rx_dis_cca = R1B_RX_DIS_CCA_C;
cr->r1b_rx_dis_cca_m = R1B_RX_DIS_CCA_C_M;
cr->intf_r_rate = INTF_R_CNT_RATE_C;
cr->intf_r_rate_m = INTF_R_CNT_RATE_C_M;
cr->intf_r_mcs = INTF_R_CNT_MCS_C;
cr->intf_r_mcs_m = INTF_R_CNT_MCS_C_M;
cr->intf_r_vht_mcs = INTF_R_CNT_VHT_MCS_C;
cr->intf_r_vht_mcs_m = INTF_R_CNT_VHT_MCS_C_M;
cr->intf_r_he_mcs = INTF_R_CNT_HE_MCS_C;
cr->intf_r_he_mcs_m = INTF_R_CNT_HE_MCS_C_M;
cr->intf_r_vht_nss = INTF_R_CNT_VHT_NSS_C;
cr->intf_r_vht_nss_m = INTF_R_CNT_VHT_NSS_C_M;
cr->intf_r_he_nss = INTF_R_CNT_HE_NSS_C;
cr->intf_r_he_nss_m = INTF_R_CNT_HE_NSS_C_M;
cr->intf_r_mac_hdr_type = INTF_R_MAC_HDR_TYPE_C;
cr->intf_r_mac_hdr_type_m = INTF_R_MAC_HDR_TYPE_C_M;
cr->intf_r_pkt_type = INTF_R_PKT_TYPE_C;
cr->intf_r_pkt_type_m = INTF_R_PKT_TYPE_C_M;
cr->dbcc = DBCC_C;
cr->dbcc_m = DBCC_C_M;
cr->dbcc_2p4g_band_sel = DBCC_2P4G_BAND_SEL_C;
cr->dbcc_2p4g_band_sel_m = DBCC_2P4G_BAND_SEL_C_M;
cr->cnt_pop_trig = CNT_POP_TRIG_C;
cr->cnt_pop_trig_m = CNT_POP_TRIG_C_M;
cr->max_cnt_pop = MAX_CNT_POP_C;
cr->max_cnt_pop_m = MAX_CNT_POP_C_M;
break;
#endif
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_statistics.c
|
C
|
agpl-3.0
| 57,630
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_STATISTICS_H__
#define __HALBB_STATISTICS_H__
/*@--------------------------[Define] ---------------------------------------*/
#define CHK_HANG_L_SIG_TH 3
#define HANG_RECOVERY true // Disable auto-recovery mechanism for 52A CBV
#define HANG_LIMIT 1
/*@--------------------------[Enum]------------------------------------------*/
enum stat_type_sel {
STATE_PROBE_RESP = 1,
STATE_BEACON = 2,
STATE_ACTION = 3,
STATE_BFRP = 4,
STATE_NDPA = 5,
STATE_BA = 6,
STATE_RTS = 7,
STATE_CTS = 8,
STATE_ACK = 9,
STATE_DATA = 10,
STATE_NULL = 11,
STATE_QOS = 12,
};
enum stat_mac_type {
TYPE_PROBE_RESP = 0x05,
TYPE_BEACON = 0x08,
TYPE_ACTION = 0x0d,
TYPE_BFRP = 0x14,
TYPE_NDPA = 0x15,
TYPE_BA = 0x19,
TYPE_RTS = 0x1b,
TYPE_CTS = 0x1c,
TYPE_ACK = 0x1d,
TYPE_DATA = 0x20,
TYPE_NULL = 0x24,
TYPE_QOS = 0x28,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_usr_set_info {
u16 ofdm2_rate_idx;
u16 ht2_rate_idx;
u16 vht2_rate_idx;
u16 he2_rate_idx;
enum stat_mac_type stat_mac_type_i;
enum stat_type_sel stat_type_sel_i;
};
struct bb_cca_info {
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_cca_all;
u32 cnt_cck_spoofing;
u32 cnt_ofdm_spoofing;
u32 cnt_cca_spoofing_all;
u32 pop_cnt;
};
struct bb_crc_info {
u32 cnt_ampdu_miss;
u32 cnt_cck_crc32_error;
u32 cnt_cck_crc32_ok;
u32 cnt_ofdm_crc32_error;
u32 cnt_ofdm_crc32_ok;
u32 cnt_ht_crc32_error;
u32 cnt_ht_crc32_ok;
u32 cnt_vht_crc32_error;
u32 cnt_vht_crc32_ok;
u32 cnt_he_crc32_ok;
u32 cnt_he_crc32_error;
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
};
struct bb_crc2_info {
u32 cnt_ofdm2_crc32_error;
u32 cnt_ofdm2_crc32_ok;
u8 ofdm2_pcr;
u32 cnt_ht2_crc32_error;
u32 cnt_ht2_crc32_ok;
u8 ht2_pcr;
u32 cnt_vht2_crc32_error;
u32 cnt_vht2_crc32_ok;
u8 vht2_pcr;
u32 cnt_he2_crc32_error;
u32 cnt_he2_crc32_ok;
u8 he2_pcr;
u32 cnt_ofdm3_crc32_error;
u32 cnt_ofdm3_crc32_ok;
};
struct bb_cck_fa_info {
u32 sfd_gg_cnt;
u32 sig_gg_cnt;
u32 cnt_cck_crc_16;
};
struct bb_legacy_fa_info {
u32 cnt_lsig_brk_s_th;
u32 cnt_lsig_brk_l_th;
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_sb_search_fail;
};
struct bb_ht_fa_info {
u32 cnt_crc8_fail;
u32 cnt_crc8_fail_s_th;
u32 cnt_crc8_fail_l_th;
u32 cnt_mcs_fail;
};
struct bb_vht_fa_info {
u32 cnt_crc8_fail_vhta;
/*u32 cnt_crc8_fail_vhtb; removed at RXD*/
u32 cnt_mcs_fail_vht;
};
struct bb_he_fa_info {
u32 cnt_crc4_fail_hea_su;
u32 cnt_crc4_fail_hea_ersu;
u32 cnt_crc4_fail_hea_mu;
u32 cnt_crc4_fail_heb_ch1_mu;
u32 cnt_crc4_fail_heb_ch2_mu;
u32 cnt_mcs_fail_he_bcc;
u32 cnt_mcs_fail_he;
u32 cnt_mcs_fail_he_dcm;
};
struct bb_fa_info {
u32 cnt_total_brk;
u32 cnt_cck_fail;
u32 cnt_ofdm_fail;
u32 cnt_fail_all;
struct bb_cck_fa_info bb_cck_fa_i;
struct bb_legacy_fa_info bb_legacy_fa_i;
struct bb_ht_fa_info bb_ht_fa_i;
struct bb_vht_fa_info bb_vht_fa_i;
struct bb_he_fa_info bb_he_fa_i;
};
struct bb_tx_cnt_info {
u32 cck_mac_txen;
u32 cck_phy_txon;
u32 ofdm_mac_txen;
u32 ofdm_phy_txon;
};
struct bb_stat_cr_info {
u32 cck_cca;
u32 cck_cca_m;
u32 cck_crc16fail;
u32 cck_crc16fail_m;
u32 cck_crc32ok;
u32 cck_crc32ok_m;
u32 cck_crc32fail;
u32 cck_crc32fail_m;
u32 cca_spoofing;
u32 cca_spoofing_m;
u32 lsig_brk_s_th;
u32 lsig_brk_s_th_m;
u32 lsig_brk_l_th;
u32 lsig_brk_l_th_m;
u32 htsig_crc8_err_s_th;
u32 htsig_crc8_err_s_th_m;
u32 htsig_crc8_err_l_th;
u32 htsig_crc8_err_l_th_m;
u32 brk;
u32 brk_m;
u32 brk_sel;
u32 brk_sel_m;
u32 rxl_err_parity;
u32 rxl_err_parity_m;
u32 rxl_err_rate;
u32 rxl_err_rate_m;
u32 ht_err_crc8;
u32 ht_err_crc8_m;
u32 vht_err_siga_crc8;
u32 vht_err_siga_crc8_m;
u32 ht_not_support_mcs;
u32 ht_not_support_mcs_m;
u32 vht_not_support_mcs;
u32 vht_not_support_mcs_m;
u32 err_during_bt_tx;
u32 err_during_bt_tx_m;
u32 err_during_bt_rx;
u32 err_during_bt_rx_m;
u32 edge_murx_nsts0;
u32 edge_murx_nsts0_m;
u32 search_fail;
u32 search_fail_m;
u32 ofdm_cca;
u32 ofdm_cca_m;
u32 ofdm_cca_s20;
u32 ofdm_cca_s20_m;
u32 ofdm_cca_s40;
u32 ofdm_cca_s40_m;
u32 ofdm_cca_s80;
u32 ofdm_cca_s80_m;
u32 ccktxen;
u32 ccktxen_m;
u32 ccktxon;
u32 ccktxon_m;
u32 ofdmtxon;
u32 ofdmtxon_m;
u32 ofdmtxen;
u32 ofdmtxen_m;
u32 drop_trig;
u32 drop_trig_m;
u32 pop_trig;
u32 pop_trig_m;
u32 tx_conflict;
u32 tx_conflict_m;
u32 wmac_rstb;
u32 wmac_rstb_m;
u32 en_tb_ppdu_fix_gain;
u32 en_tb_ppdu_fix_gain_m;
u32 en_tb_cca_pw_th;
u32 en_tb_cca_pw_th_m;
u32 he_crc_ok;
u32 he_crc_ok_m;
u32 he_crc_err;
u32 he_crc_err_m;
u32 vht_crc_ok;
u32 vht_crc_ok_m;
u32 vht_crc_err;
u32 vht_crc_err_m;
u32 ht_crc_ok;
u32 ht_crc_ok_m;
u32 ht_crc_err;
u32 ht_crc_err_m;
u32 l_crc_ok;
u32 l_crc_ok_m;
u32 l_crc_err;
u32 l_crc_err_m;
u32 he_crc_ok2;
u32 he_crc_ok2_m;
u32 he_crc_err2;
u32 he_crc_err2_m;
u32 vht_crc_ok2;
u32 vht_crc_ok2_m;
u32 vht_crc_err2;
u32 vht_crc_err2_m;
u32 ht_crc_ok2;
u32 ht_crc_ok2_m;
u32 ht_crc_err2;
u32 ht_crc_err2_m;
u32 l_crc_ok2;
u32 l_crc_ok2_m;
u32 l_crc_err2;
u32 l_crc_err2_m;
u32 l_crc_ok3;
u32 l_crc_ok3_m;
u32 l_crc_err3;
u32 l_crc_err3_m;
u32 ampdu_rxon;
u32 ampdu_rxon_m;
u32 ampdu_miss;
u32 ampdu_miss_m;
u32 hesu_err_sig_a_crc4;
u32 hesu_err_sig_a_crc4_m;
u32 heersu_err_sig_a_crc4;
u32 heersu_err_sig_a_crc4_m;
u32 hemu_err_sig_a_crc4;
u32 hemu_err_sig_a_crc4_m;
u32 hemu_err_sigb_ch1_comm_crc4;
u32 hemu_err_sigb_ch1_comm_crc4_m;
u32 hemu_err_sigb_ch2_comm_crc4;
u32 hemu_err_sigb_ch2_comm_crc4_m;
u32 he_u0_err_bcc_mcs;
u32 he_u0_err_bcc_mcs_m;
u32 he_u0_err_mcs;
u32 he_u0_err_mcs_m;
u32 he_u0_err_dcm_mcs;
u32 he_u0_err_dcm_mcs_m;
u32 r1b_rx_rpt_rst;
u32 r1b_rx_rpt_rst_m;
u32 r1b_rr_sel;
u32 r1b_rr_sel_m;
u32 rst_all_cnt;
u32 rst_all_cnt_m;
u32 enable_all_cnt;
u32 enable_all_cnt_m;
u32 enable_ofdm;
u32 enable_ofdm_m;
u32 enable_cck;
u32 enable_cck_m;
u32 r1b_rx_dis_cca;
u32 r1b_rx_dis_cca_m;
u32 intf_r_rate;
u32 intf_r_rate_m;
u32 intf_r_mcs;
u32 intf_r_mcs_m;
u32 intf_r_vht_mcs;
u32 intf_r_vht_mcs_m;
u32 intf_r_he_mcs;
u32 intf_r_he_mcs_m;
u32 intf_r_vht_nss;
u32 intf_r_vht_nss_m;
u32 intf_r_he_nss;
u32 intf_r_he_nss_m;
u32 intf_r_mac_hdr_type;
u32 intf_r_mac_hdr_type_m;
u32 intf_r_pkt_type;
u32 intf_r_pkt_type_m;
u32 dbcc;
u32 dbcc_m;
u32 dbcc_2p4g_band_sel;
u32 dbcc_2p4g_band_sel_m;
u32 cnt_pop_trig;
u32 cnt_pop_trig_m;
u32 max_cnt_pop;
u32 max_cnt_pop_m;
};
struct bb_stat_info {
struct bb_stat_cr_info bb_stat_cr_i;
u32 cnt_bw_usc;
u32 cnt_bw_lsc;
u32 time_fa_all;
u32 dbg_port0;
u32 chk_hang_cnt;
u8 chk_hang_limit;
bool hang_recovery_en;
bool cck_block_enable;
bool ofdm_block_enable;
struct bb_tx_cnt_info bb_tx_cnt_i;
struct bb_cca_info bb_cca_i;
struct bb_crc_info bb_crc_i;
struct bb_crc2_info bb_crc2_i;
struct bb_fa_info bb_fa_i;
struct bb_usr_set_info bb_usr_set_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_chk_hang(struct bb_info *bb);
void halbb_print_cnt3(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_print_cnt2(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_print_cnt(struct bb_info *bb, bool cck_enable, enum phl_phy_idx phy_idx, enum phl_phy_idx phy_idx_2);
void halbb_cnt_reg_reset(struct bb_info *bb);
void halbb_set_crc32_cnt2_rate(struct bb_info *bb, u16 rate_idx);
void halbb_set_crc32_cnt3_format(struct bb_info *bb, u8 usr_type_sel);
void halbb_crc32_cnt_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cck_cnt_statistics(struct bb_info *bb);
void halbb_ofdm_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_statistics_reset(struct bb_info *bb);
void halbb_statistics(struct bb_info *bb);
void halbb_statistics_init(struct bb_info *bb);
void halbb_cr_cfg_stat_init(struct bb_info *bb);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_statistics.h
|
C
|
agpl-3.0
| 9,069
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_TYPES_H__
#define __HALBB_TYPES_H__
/*@--------------------------[Define] ---------------------------------------*/
#define HALBB_CONFIG_RUN_IN_DRV
/*For FW API*/
#define __iram_func__
#endif /* __HALBB_TYPES_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_types.h
|
C
|
agpl-3.0
| 1,203
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_WPP_H__
#define __HALBB_WPP_H__
#define HALBB_WPP_CONTROL_GUIDS \
WPP_DEFINE_CONTROL_GUID( \
HalbbGuid, (111AA0F8,4BB9,4C05,BE3E,03383B8CD916), \
WPP_DEFINE_BIT(DBG_RA) \
WPP_DEFINE_BIT(DBG_FA_CNT) \
WPP_DEFINE_BIT(HALBB_FUN_RSVD_2) \
WPP_DEFINE_BIT(DBG_DFS) \
WPP_DEFINE_BIT(DBG_EDCCA)\
WPP_DEFINE_BIT(DBG_ENV_MNTR)\
WPP_DEFINE_BIT(DBG_CFO_TRK)\
WPP_DEFINE_BIT(DBG_PWR_CTRL)\
WPP_DEFINE_BIT(DBG_RUA_TBL)\
WPP_DEFINE_BIT(DBG_AUTO_DBG)\
WPP_DEFINE_BIT(DBG_ANT_DIV)\
WPP_DEFINE_BIT(DBG_DIG)\
WPP_DEFINE_BIT(DBG_BIT12)\
WPP_DEFINE_BIT(DBG_BIT13)\
WPP_DEFINE_BIT(DBG_BIT14)\
WPP_DEFINE_BIT(DBG_BIT15)\
WPP_DEFINE_BIT(DBG_BIT16)\
WPP_DEFINE_BIT(DBG_BIT17)\
WPP_DEFINE_BIT(DBG_BIT18)\
WPP_DEFINE_BIT(DBG_BIT19)\
WPP_DEFINE_BIT(DBG_PHY_STS)\
WPP_DEFINE_BIT(DBG_BIT21)\
WPP_DEFINE_BIT(DBG_FW_INFO)\
WPP_DEFINE_BIT(DBG_COMMON_FLOW)\
WPP_DEFINE_BIT(DBG_IC_API)\
WPP_DEFINE_BIT(DBG_DBG_API)\
WPP_DEFINE_BIT(DBG_DBCC)\
WPP_DEFINE_BIT(DBG_DM_SUMMARY)\
WPP_DEFINE_BIT(DBG_PHY_CONFIG)\
WPP_DEFINE_BIT(DBG_INIT)\
WPP_DEFINE_BIT(DBG_CMN)\
WPP_DEFINE_BIT(DBG_DCR)\
)
#endif /* __HALBB_TYPES_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/bb/halbb_wpp.h
|
C
|
agpl-3.0
| 2,133
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halrf_precomp.h"
#if 1
enum rtw_hal_status halrf_chl_rfk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force)
{
struct rf_info *rf = (struct rf_info *)rf_void;
u32 start_time, finish_time;
#if 0
struct rtw_hal_com_t *hal_i = rf->hal_com;
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
start_time = _os_get_cur_time_us();
/*[RX Gain K]*/
halrf_do_rx_gain_k(rf, phy_idx);
/*[TX GAP K]*/
halrf_gapk_trigger(rf, phy_idx, true);
/*[RX dck]*/
halrf_rx_dck_trigger(rf, phy_idx, true);
/*[LOK, IQK]*/
halrf_iqk_trigger(rf, phy_idx, force);
/*[TSSI Trk]*/
halrf_tssi_trigger(rf, phy_idx);
/*[DPK]*/
halrf_dpk_trigger(rf, phy_idx, force);
halrf_fw_ntfy(rf, phy_idx);
finish_time = _os_get_cur_time_us();
RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] halrf_chl_rfk_trigger processing time = %d.%dms\n",
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
void halrf_dack_recover(void *rf_void,
u8 offset,
enum rf_path path,
u32 val,
bool reload)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
#if 0
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
if (hal_i->cv == CAV)
halrf_dack_recover_8852a(rf, offset, path, val, reload);
break;
#endif
default:
break;
}
}
enum rtw_hal_status halrf_dack_trigger(void *rf_void, bool force)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_dack_info *dack = &rf->dack;
u32 start_time, finish_time;
#if 0
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_DACK))
return RTW_HAL_STATUS_SUCCESS;
halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_DACK, RFK_START);
start_time = _os_get_cur_time_us();
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
if (hal_i->cv == CAV)
halrf_dac_cal_8852a(rf, force);
else
halrf_dac_cal_8852a_b(rf, force);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_dac_cal_8852b(rf, force);
break;
#endif
default:
break;
}
finish_time = _os_get_cur_time_us();
halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_DACK, RFK_STOP);
dack->dack_time = HALRF_ABS(finish_time, start_time) / 1000;
RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] DACK processing time = %d.%dms\n",
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_rx_dck_trigger(void *rf_void,
enum phl_phy_idx phy_idx, bool is_afe)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 start_time, finish_time;
#if 0
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_RXDCK))
return RTW_HAL_STATUS_SUCCESS;
halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_RXDCK, RFK_START);
halrf_tmac_tx_pause(rf, phy_idx, true);
#if 0
for (i = 0; i < 2000; i++)
halrf_delay_us(rf, 10); /*delay 20ms*/
#endif
start_time = _os_get_cur_time_us();
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_rx_dck_8852a(rf, phy_idx, is_afe);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_rx_dck_8852b(rf, phy_idx, false);
break;
#endif
default:
break;
}
halrf_tmac_tx_pause(rf, phy_idx, false);
finish_time = _os_get_cur_time_us();
halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_RXDCK, RFK_STOP);
RF_DBG(rf, DBG_RF_RXDCK, "[RX_DCK] RX_DCK processing time = %d.%dms\n",
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_iqk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 start_time, finish_time;
#if 0
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_IQK))
return RTW_HAL_STATUS_SUCCESS;
rf->rfk_is_processing = true;
start_time = _os_get_cur_time_us();
halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_IQK, RFK_START);
halrf_tmac_tx_pause(rf, phy_idx, true);
halrf_iqk_init(rf);
halrf_iqk(rf, phy_idx, force);
halrf_tmac_tx_pause(rf, phy_idx, false);
rf->rfk_is_processing = false;
finish_time = _os_get_cur_time_us();
halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_IQK, RFK_STOP);
RF_DBG(rf, DBG_RF_IQK, "[IQK] IQK processing time = %d.%dms\n",
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
void halrf_lck_trigger(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
#if 0
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_LCK))
return;
#if 0
while (*dm->is_scan_in_process) {
RF_DBG(dm, DBG_RF_IQK, "[LCK]scan is in process, bypass LCK\n");
return;
}
#endif
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
break;
#endif
default:
break;
}
}
enum rtw_hal_status halrf_dpk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 start_time, finish_time;
#if 0
if ((rf->phl_com->drv_mode == RTW_DRV_MODE_MP) &
(hal_i->is_con_tx ||
hal_i->is_single_tone ||
hal_i->is_carrier_suppresion))
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_DPK) || rf->phl_com->id.id == 0x1010a) /*USB buffalo*/
return RTW_HAL_STATUS_SUCCESS;
halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_DPK, RFK_START);
halrf_tmac_tx_pause(rf, phy_idx, true);
rf->rfk_is_processing = true;
start_time = _os_get_cur_time_us();
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_dpk_8852a(rf, phy_idx, force);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_dpk_8852b(rf, phy_idx, force);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
finish_time = _os_get_cur_time_us();
halrf_tmac_tx_pause(rf, phy_idx, false);
halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_DPK, RFK_STOP);
RF_DBG(rf, DBG_RF_DPK, "[DPK] DPK processing time = %d.%dms\n",
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_dpk_tracking(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_dpk_info *dpk = &rf->dpk;
if (!(rf->support_ability & HAL_RF_DPK_TRACK) || rf->rfk_is_processing ||
rf->is_watchdog_stop || rf->psd.psd_progress)
return RTW_HAL_STATUS_SUCCESS;
rf->is_watchdog_stop = true; /*avoid race condition*/
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_dpk_track_8852a(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_dpk_track_8852b(rf);
break;
#endif
default:
break;
}
rf->is_watchdog_stop = false;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_tssi_tracking(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if ((!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) || (!(rf->support_ability & HAL_RF_TSSI_TRK))
|| rf->rfk_is_processing || rf->is_watchdog_stop || rf->psd.psd_progress)
return RTW_HAL_STATUS_SUCCESS;
rf->is_watchdog_stop = true; /*avoid race condition*/
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_tracking_8852a(rf);
break;
#endif
default:
break;
}
rf->is_watchdog_stop = false;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_tssi_tracking_clean(void *rf_void, s16 power_dbm)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if ((!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) || (!(rf->support_ability & HAL_RF_TSSI_TRK))
|| rf->rfk_is_processing || rf->is_watchdog_stop || rf->psd.psd_progress)
return RTW_HAL_STATUS_SUCCESS;
rf->is_watchdog_stop = true; /*avoid race condition*/
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_tracking_clean_8852ab(rf, power_dbm);
break;
#endif
default:
break;
}
rf->is_watchdog_stop = false;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_tssi_ant_open(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if ((!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) || (!(rf->support_ability & HAL_RF_TSSI_TRK))
|| rf->rfk_is_processing || rf->is_watchdog_stop || rf->psd.psd_progress)
return RTW_HAL_STATUS_SUCCESS;
rf->is_watchdog_stop = true; /*avoid race condition*/
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_ant_open_8852a(rf);
break;
#endif
default:
break;
}
rf->is_watchdog_stop = false;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 start_time, finish_time;
start_time = _os_get_cur_time_us();
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) {
if (tssi_info->tssi_type == TSSI_OFF ) {
rf->support_ability = rf->support_ability & ~HAL_RF_TX_PWR_TRACK;
}
}
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) {
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_disable_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_disable_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
return RTW_HAL_STATUS_SUCCESS;
}
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_do_tssi_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_do_tssi_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
finish_time = _os_get_cur_time_us();
RF_DBG(rf, DBG_RF_RFK, "[TSSI] %s processing time = %d.%dms\n",
__func__,
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 start_time, finish_time;
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK))
return;
start_time = _os_get_cur_time_us();
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_do_tssi_scan_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_do_tssi_scan_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
finish_time = _os_get_cur_time_us();
RF_DBG(rf, DBG_RF_RFK, "[TSSI] %s processing time = %d.%dms\n",
__func__,
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
}
void halrf_tssi_set_avg(void *rf_void,
enum phl_phy_idx phy_idx, bool enable)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK))
return;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_set_avg_8852ab(rf, phy_idx, enable);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
}
void halrf_tssi_default_txagc(void *rf_void,
enum phl_phy_idx phy_idx, bool enable)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK))
return;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_default_txagc_8852ab(rf, phy_idx, enable);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_default_txagc_8852b(rf, phy_idx, enable);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
}
void halrf_tssi_set_efuse_to_de(void *rf_void,
enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK))
return;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_set_efuse_to_de_8852ab(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_set_efuse_to_de_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
}
void halrf_tssi_scan_ch(void *rf_void, enum rf_path path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK))
return;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_scan_ch_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_scan_ch_8852b(rf, path);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
}
void halrf_hw_tx(void *rf_void, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw,
bool enable)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_hw_tx_8852a(rf, HW_PHY_0, path, cnt, dbm, T_HT_MF, 0, enable);
break;
#endif
default:
break;
}
}
void halrf_txgapk_init(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
//halrf_txgapk_init_8852a(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_txgapk_init_8852b(rf);
break;
#endif
default:
break;
}
}
enum rtw_hal_status halrf_gapk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 start_time, finish_time;
if (!(rf->support_ability & HAL_RF_TXGAPK))
return RTW_HAL_STATUS_SUCCESS;
rf->rfk_is_processing = true;
start_time = _os_get_cur_time_us();
halrf_txgapk_init(rf);
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_do_txgapk_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_do_txgapk_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
finish_time = _os_get_cur_time_us();
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] %s processing time = %d.%dms\n",
__func__,
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_gapk_enable(void *rf_void,
enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_txgapk_enable_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_txgapk_enable_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status halrf_gapk_disable(void *rf_void,
enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_txgapk_write_table_default_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_txgapk_write_table_default_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
return RTW_HAL_STATUS_SUCCESS;
}
void halrf_rck_trigger(void *rf_void,
enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 path = 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
for (path = 0; path < 2; path++)
halrf_rck_8852a(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
for (path = 0; path < 2; path++)
halrf_rck_8852b(rf, path);
break;
#endif
default:
break;
}
}
void halrf_gapk_save_tx_gain(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
//halrf_gapk_save_tx_gain_8852a(rf);
break;
#endif
default:
break;
}
}
void halrf_gapk_reload_tx_gain(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
//halrf_gapk_reload_tx_gain_8852a(rf);
break;
#endif
default:
break;
}
}
void halrf_lo_test(void *rf_void, bool is_on, enum rf_path path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
#if 0
if (hal_i->is_mp_mode &&
hal_i->is_con_tx &&
hal_i->is_single_tone &&
hal_i->is_carrier_suppresion)
return;
if (hal_i->rfk_forbidden)
return;
#endif
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_lo_test_8852a(rf, is_on, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_lo_test_8852b(rf, is_on, path);
break;
#endif
default:
break;
}
}
void halrf_iqk_onoff(void *rf_void, bool is_enable)
{
/*signal go throughput iqk or not*/
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 path = 0x0;
if (!(rf->support_ability & HAL_RF_DPK))
return;
rf->rfk_is_processing = true;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_onoff_8852ab(rf, is_enable);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
}
void halrf_dpk_onoff(void *rf_void, bool is_enable)
{
/*signal go throughput dpk or not*/
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_dpk_info *dpk = &rf->dpk;
u8 path = 0;
#if 0
if (hal_i->is_mp_mode &&
hal_i->is_con_tx &&
hal_i->is_single_tone &&
hal_i->is_carrier_suppresion)
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_DPK))
return;
rf->rfk_is_processing = true;
dpk->is_dpk_enable = is_enable;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
for (path = 0; path < 2; path++)
halrf_dpk_onoff_8852a(rf, path, false);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
for (path = 0; path < 2; path++)
halrf_dpk_onoff_8852b(rf, path, false);
break;
#endif
default:
break;
}
rf->rfk_is_processing = false;
}
void halrf_dpk_track_onoff(void *rf_void, bool is_enable)
{
struct rf_info *rf = (struct rf_info *)rf_void;
if (is_enable)
rf->support_ability = rf->support_ability | HAL_RF_DPK_TRACK;
else
rf->support_ability = rf->support_ability & ~HAL_RF_DPK_TRACK;
}
void halrf_dpk_switch(void *rf_void, bool is_enable)
{
struct rf_info *rf = (struct rf_info *)rf_void;
if (is_enable) {
halrf_dpk_onoff(rf, true);
halrf_dpk_trigger(rf, HW_PHY_0, true);
halrf_dpk_track_onoff(rf, true);
halrf_wl_tx_power_control(rf, 0xffffeeee);
} else {
halrf_wl_tx_power_control(rf, 0xffff8034);
halrf_dpk_track_onoff(rf, false);
halrf_dpk_onoff(rf, false);
}
}
void halrf_dpk_init(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_dpk_info *dpk = &rf->dpk;
u8 path, idx;
for (path = 0; path < KPATH; path++) {
dpk->cur_idx[path] = 0;
for (idx = 0; idx < DPK_BKUP_NUM; idx++) {
dpk->bp[path][idx].band = 0;
dpk->bp[path][idx].bw = 0;
dpk->bp[path][idx].ch = 0;
dpk->bp[path][idx].path_ok = 0;
dpk->bp[path][idx].txagc_dpk = 0;
dpk->bp[path][idx].ther_dpk = 0;
dpk->bp[path][idx].gs = 0;
dpk->bp[path][idx].pwsf = 0;
}
}
dpk->is_dpk_enable = true;
dpk->is_dpk_reload_en = false;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_dpk_init_8852a(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_dpk_init_8852b(rf);
break;
#endif
default:
break;
}
}
void halrf_rx_dck_onoff(void *rf_void, bool is_enable)
{
/*signal go throughput dpk or not*/
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
#if 0
if (hal_i->is_mp_mode &&
hal_i->is_con_tx &&
hal_i->is_single_tone &&
hal_i->is_carrier_suppresion)
return;
if (hal_i->rfk_forbidden)
return;
#endif
if (!(rf->support_ability & HAL_RF_RXDCK))
return;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_rx_dck_onoff_8852a(rf, is_enable);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_rx_dck_onoff_8852b(rf, is_enable);
break;
#endif
default:
break;
}
}
void halrf_gapk_onoff(void *rf_void, bool is_enable)
{
/*parameter to default or not*/
}
void halrf_dack_onoff(void *rf_void, bool is_enable)
{
/*parameter to default or not*/
}
void halrf_tssi_onoff(void *rf_void, bool is_enable)
{
/*parameter to default or not*/
}
bool halrf_get_iqk_onoff(void *rf_void)
{
return 1;
}
bool halrf_get_dpk_onoff(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct halrf_dpk_info *dpk = &rf->dpk;
return dpk->is_dpk_enable;
}
bool halrf_get_dpk_track_onoff(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
if (rf->support_ability & HAL_RF_DPK_TRACK)
return 1;
else
return 0;
}
bool halrf_get_gapk_onoff(void *rf_void)
{
return 1;
}
bool halrf_get_dack_onoff(void *rf_void)
{
return 1;
}
bool halrf_get_tssi_onoff(void *rf_void)
{
return 1;
}
u8 halrf_get_thermal(void *rf_void, u8 rf_path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_get_thermal_8852a(rf, rf_path);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_get_thermal_8852b(rf, rf_path);
#endif
return 0;
}
u32 halrf_get_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path)
{
return 0;
}
s32 halrf_get_online_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path, s32 dbm, s32 puot)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
s32 tmp = 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
tmp = halrf_get_online_tssi_de_8852a(rf, phy_idx, path, dbm, puot);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
tmp = halrf_get_online_tssi_de_8852b(rf, phy_idx, path, dbm, puot);
break;
#endif
default:
break;
}
return tmp;
}
void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_enable_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_enable_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
}
void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_disable_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_disable_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
}
s8 halrf_get_ther_protected_threshold(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
return halrf_get_ther_protected_threshold_8852a(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
return halrf_get_ther_protected_threshold_8852b(rf);
break;
#endif
default:
break;
}
return 0;
}
void halrf_set_tssi_de_for_tx_verify(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_set_tssi_de_for_tx_verify_8852a(rf, phy_idx, tssi_de, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_set_tssi_de_for_tx_verify_8852b(rf, phy_idx, tssi_de, path);
break;
#endif
default:
break;
}
}
u32 halrf_tssi_get_final(void *rf_void, enum phl_phy_idx phy_idx, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
return halrf_tssi_get_final_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
return halrf_tssi_get_final_8852b(rf, path);
break;
#endif
default:
break;
}
return 0;
}
void halrf_set_tssi_de_offset(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de_offset, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_set_tssi_de_offset_8852a(rf, phy_idx, tssi_de_offset, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_set_tssi_de_offset_8852b(rf, phy_idx, tssi_de_offset, path);
break;
#endif
default:
break;
}
}
void halrf_set_tssi_avg_mp(void *rf_void,
enum phl_phy_idx phy_idx, s32 xdbm)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_set_tssi_avg_mp_8852a(rf, phy_idx, xdbm);
break;
#endif
default:
break;
}
}
void halrf_set_rx_gain_offset_for_rx_verify(void *rf_void,
enum phl_phy_idx phy,
s8 rx_gain_offset, u8 path)
{
#if 0
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_set_rx_gain_offset_for_rx_verify_8852a(rf, phy, rx_gain_offset, path);
break;
#endif
default:
break;
}
#endif
}
void halrf_set_power_track(void *rf_void, enum phl_phy_idx phy_idx, u8 value)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct halrf_tssi_info *tssi_info = &rf->tssi;
tssi_info->tssi_type = value;
if (value == TSSI_OFF) {
halrf_tssi_trigger(rf, phy_idx);
rf->support_ability = rf->support_ability & ~HAL_RF_TX_PWR_TRACK;
} else if (value == TSSI_ON) {
rf->support_ability = rf->support_ability | HAL_RF_TX_PWR_TRACK;
halrf_tssi_trigger(rf, phy_idx);
} else if (value == TSSI_CAL) {
rf->support_ability = rf->support_ability | HAL_RF_TX_PWR_TRACK;
halrf_tssi_trigger(rf, phy_idx);
} else
rf->support_ability = rf->support_ability & ~HAL_RF_TX_PWR_TRACK;
}
u8 halrf_get_power_track(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct halrf_tssi_info *tssi_info = &rf->tssi;
return tssi_info->tssi_type;
}
void halrf_tssi_get_efuse_ex(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_tssi_get_efuse_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_get_efuse_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
halrf_get_efuse_power_table_switch(rf, phy_idx);
}
bool halrf_tssi_check_efuse_data(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
return halrf_tssi_check_efuse_data_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
return halrf_tssi_check_efuse_data_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
return false;
}
void halrf_set_ref_power_to_struct(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_set_ref_power_to_struct_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_set_ref_power_to_struct_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
}
void halrf_set_regulation_init(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_pwr_info *pwr = &rf->pwr_info;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
pwr->regulation_idx = 0xff;
break;
#endif
default:
break;
}
}
void halrf_bf_config_rf(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_bf_config_rf_8852a(rf);
break;
#endif
default:
break;
}
}
bool halrf_get_efuse_info(void *rf_void, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length,
u8 autoload_status)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_get_efuse_info_8852a(rf, efuse_map, id, value, length,
autoload_status);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_get_efuse_info_8852b(rf, efuse_map, id, value, length,
autoload_status);
#endif
return 0;
}
void halrf_get_efuse_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx)
{
#if 0
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_get_efuse_rx_gain_k_8852a(rf, phy_idx);
#endif
#endif
}
void halrf_get_efuse_trim(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_get_efuse_trim_8852a(rf, phy_idx);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_get_efuse_trim_8852b(rf, phy_idx);
#endif
}
void halrf_do_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx)
{
#if 0
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
if (!(rf->support_ability & HAL_RF_RXGAINK))
return;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_do_rx_gain_k_8852a(rf, phy_idx);
#endif
#endif
}
bool halrf_set_dbcc(void *rf_void, bool dbcc_en)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_set_dbcc_8852a(rf, dbcc_en);
#endif
return 0;
}
bool halrf_wl_tx_power_control(void *rf_void, u32 tx_power_val)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool rtn = false;
switch (hal_com->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
rtn = halrf_wl_tx_power_control_8852a(rf, tx_power_val);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
rtn = halrf_wl_tx_power_control_8852b(rf, tx_power_val);
break;
#endif
default:
break;
}
return rtn;
}
void halrf_watchdog(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
/*halrf_thermal_period(rf);*/
halrf_tssi_ant_open(rf);
halrf_tssi_tracking(rf);
halrf_dpk_tracking(rf);
halrf_iqk_tracking(rf);
}
u8 halrf_get_default_rfe_type(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_get_default_rfe_type_8852a(rf);
#endif
return 1;
}
u8 halrf_get_default_xtal(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_get_default_xtal_8852a(rf);
#endif
return 0x3f;
}
bool halrf_iqk_get_ther_rek(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_iqk_get_ther_rek_8852ab(rf);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_iqk_get_ther_rek_8852b(rf);
#endif
return false;
}
enum rtw_hal_status halrf_iqk_tracking(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_iqk_info *iqk = &rf->iqk;
if (!(rf->support_ability & HAL_RF_IQK) || rf->rfk_is_processing ||
rf->is_watchdog_stop)
return RTW_HAL_STATUS_SUCCESS;
rf->is_watchdog_stop = true; /*avoid race condition*/
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_track_8852ab(rf);
#if 0
if (halrf_iqk_get_ther_rek(rf))
halrf_iqk(rf, 0x0, false);
#endif
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_track_8852b(rf);
break;
#endif
default:
break;
}
rf->is_watchdog_stop = false;
return RTW_HAL_STATUS_SUCCESS;
}
void halrf_psd_init(void *rf_void, enum phl_phy_idx phy,
u8 path, u8 iq_path, u32 avg, u32 fft)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_psd_init_8852a(rf, phy, path, iq_path, avg, fft);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_psd_init_8852b(rf, phy, path, iq_path, avg, fft);
#endif
}
void halrf_psd_restore(void *rf_void, enum phl_phy_idx phy)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_psd_restore_8852a(rf, phy);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_psd_restore_8852b(rf, phy);
#endif
}
u32 halrf_psd_get_point_data(void *rf_void, enum phl_phy_idx phy, s32 point)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_psd_get_point_data_8852a(rf, phy, point);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_psd_get_point_data_8852b(rf, phy, point);
#endif
return 0;
}
void halrf_psd_query(void *rf_void, enum phl_phy_idx phy,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_psd_query_8852a(rf, phy, point, start_point, stop_point, outbuf);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_psd_query_8852b(rf, phy, point, start_point, stop_point, outbuf);
#endif
}
void halrf_set_fix_power_to_struct(void *rf_void,
enum phl_phy_idx phy, s8 dbm)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_hal_com_t *hal_i = rf->hal_com;
pwr->fix_power[RF_PATH_A] = true;
pwr->fix_power_dbm[RF_PATH_A] = dbm * 2;
pwr->fix_power[RF_PATH_B] = true;
pwr->fix_power_dbm[RF_PATH_B] = dbm * 2;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_set_fix_power_to_struct_8852ab(rf, phy, dbm);
break;
#endif
default:
break;
}
}
void halrf_pwr_by_rate_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 used = *_used;
u32 out_len = *_out_len;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_pwr_by_rate_info_8852a(rf, input, &used,
output, &out_len);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_pwr_by_rate_info_8852b(rf, input, &used,
output, &out_len);
break;
#endif
default:
break;
}
}
void halrf_pwr_limit_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 used = *_used;
u32 out_len = *_out_len;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_pwr_limit_info_8852a(rf, input, &used,
output, &out_len);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_pwr_limit_info_8852b(rf, input, &used,
output, &out_len);
break;
#endif
default:
break;
}
}
void halrf_pwr_limit_ru_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 used = *_used;
u32 out_len = *_out_len;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_pwr_limit_ru_info_8852a(rf, input, &used,
output, &out_len);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_pwr_limit_ru_info_8852b(rf, input, &used,
output, &out_len);
break;
#endif
default:
break;
}
}
void halrf_get_tssi_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 used = *_used;
u32 out_len = *_out_len;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_get_tssi_info_8852a(rf, input, &used,
output, &out_len);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_get_tssi_info_8852b(rf, input, &used,
output, &out_len);
break;
#endif
default:
break;
}
}
void halrf_get_tssi_trk_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 used = *_used;
u32 out_len = *_out_len;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_get_tssi_trk_info_8852a(rf, input, &used,
output, &out_len);
break;
#endif
default:
break;
}
}
void halrf_tssi_backup_txagc(struct rf_info *rf, enum phl_phy_idx phy, bool enable)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_tssi_backup_txagc_8852b(rf, phy, enable);
break;
#endif
default:
break;
}
}
void halrf_set_tx_shape(struct rf_info *rf, u8 tx_shape_idx)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_set_tx_shape_8852b(rf, tx_shape_idx);
break;
#endif
default:
break;
}
}
void halrf_ctl_bw(void *rf_void, enum channel_width bw)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_ctrl_bw_8852b(rf, bw);
break;
#endif
default:
break;
}
return;
}
void halrf_ctl_ch(void *rf_void, u8 central_ch)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_ctrl_ch_8852b(rf, central_ch);
break;
#endif
default:
break;
}
return;
}
void halrf_rxbb_bw(void *rf_void, enum phl_phy_idx phy, enum channel_width bw)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_rxbb_bw_8852a(rf, phy, bw);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_rxbb_bw_8852b(rf, phy, bw);
break;
#endif
default:
break;
}
return;
}
void halrf_config_radio_to_fw(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_config_8852a_radio_to_fw(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_config_8852b_radio_to_fw(rf);
break;
#endif
default:
break;
}
}
void halrf_rfc_reg_backup(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_rfc_reg_backup_8852a(rf);
break;
#endif
default:
break;
}
}
bool halrf_rfc_reg_check_fail(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
bool fail = false;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
fail = halrf_rfc_reg_check_fail_8852a(rf);
break;
#endif
default:
break;
}
return fail;
}
void halrf_rfk_reg_backup(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_rfk_reg_backup_8852a(rf);
break;
#endif
default:
break;
}
}
bool halrf_rfk_reg_check_fail(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
bool fail = false;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
fail = halrf_rfk_reg_check_fail_8852a(rf);
break;
#endif
default:
break;
}
return fail;
}
bool halrf_dack_reg_check_fail(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
bool fail = false;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
fail = halrf_dack_reg_check_fail_8852a(rf);
break;
#endif
default:
break;
}
return fail;
}
bool halrf_rfk_chl_thermal(void *rf_void,
u8 chl_idx, u8 ther_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool fail = false;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
fail = halrf_rfk_chl_thermal_8852a(rf, chl_idx, ther_idx);
#endif
return fail;
}
void halrf_rfk_recovery_chl_thermal(void *rf_void, u8 chl_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_rfk_recovery_chl_thermal_8852a(rf, chl_idx);
#endif
}
u8 halrf_fcs_get_thermal_index(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
u8 idx = 0;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
idx = halrf_thermal_index_cal_8852a(rf);
#endif
return idx;
}
void halrf_disconnect_notify(void *rf_void, struct rtw_chan_def *chandef )
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool fail = false;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_disconnect_notify_8852a(rf, chandef);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_disconnect_notify_8852b(rf, chandef);
#endif
return;
}
bool halrf_check_mcc_ch(void *rf_void, struct rtw_chan_def *chandef )
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool fail = false;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
fail = halrf_check_mcc_ch_8852a(rf, chandef);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
fail = halrf_check_mcc_ch_8852b(rf, chandef);
#endif
return fail;
}
void halrf_fw_ntfy(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_fw_ntfy_8852a(rf, phy_idx);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_fw_ntfy_8852b(rf, phy_idx);
#endif
return;
}
void halrf_set_regulation_from_driver(void *rf_void,
u8 regulation_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_set_regulation_from_driver_8852a(rf, regulation_idx);
#endif
return;
}
u32 halrf_get_nctl_reg_ver(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_get_8852a_nctl_reg_ver();
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_get_8852b_nctl_reg_ver();
#endif
return 0;
}
u32 halrf_get_radio_reg_ver(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_get_8852a_radio_reg_ver();
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_get_8852b_radio_reg_ver();
#endif
return 0;
}
void halrf_config_nctl_reg(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_config_8852a_nctl_reg(rf);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_config_8852b_nctl_reg(rf);
#endif
return;
}
void halrf_set_gpio(void *rf_void, enum phl_phy_idx phy, u8 band)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_set_gpio_8852a(rf, phy, band);
#endif
}
bool halrf_mac_set_pwr_reg(void *rf_void, enum phl_phy_idx phy,
u32 addr, u32 mask, u32 val)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
u32 result = 0;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
result = halrf_mac_set_pwr_reg_8852a(rf, phy, addr, mask, val);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
result = halrf_mac_set_pwr_reg_8852b(rf, phy, addr, mask, val);
#endif
if (result == 0) /*MAC: MACSUCCESS == 0*/
return true;
else
return false;
}
u32 halrf_mac_get_pwr_reg(void *rf_void, enum phl_phy_idx phy,
u32 addr, u32 mask)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_mac_get_pwr_reg_8852a(rf, phy, addr, mask);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
return halrf_mac_get_pwr_reg_8852b(rf, phy, addr, mask);
#endif
return 0;
}
bool halrf_check_efem(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
return halrf_check_efem_8852a(rf, phy_idx);
#endif
return false;
}
void halrf_2g_rxant(void *rf_void, enum halrf_ant ant)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_2g_rxant_8852a(rf, ant);
#endif
}
s8 halrf_xtal_tracking_offset(void *rf_void, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
if (!(rf->support_ability & HAL_RF_XTAL_TRACK))
return 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
return halrf_xtal_tracking_offset_8852a(rf, phy_idx);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
return halrf_xtal_tracking_offset_8852b(rf, phy_idx);
break;
#endif
default:
break;
}
return 0;
}
void halrf_set_mp_regulation(void *rf_void, enum phl_phy_idx phy, u8 regulation)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct halrf_pwr_info *pwr = &rf->pwr_info;
pwr->mp_regulation = regulation;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf.c
|
C
|
agpl-3.0
| 51,183
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_H__
#define __HALRF_H__
/*@--------------------------[Define] ---------------------------------------*/
/*H2C cmd ID*/
/*Class 8*/
/*Class 9*/
/*Class a*/
#define FWCMD_H2C_BACKUP_RFK 0
#define FWCMD_H2C_RELOAD_RFK 1
#define FWCMD_H2C_GET_MCCCH 2
#define FWCMD_H2C_DPK_OFFLOAD 3
#define FWCMD_H2C_IQK_OFFLOAD 4
/*@--------------------------[Enum]------------------------------------------*/
enum halrf_func_idx {
RF00_PWR_TRK = 0,
RF01_IQK = 1,
RF02_LCK = 2,
RF03_DPK = 3,
RF04_TXGAPK = 4,
RF05_DACK = 5,
RF06_DPK_TRK = 6,
RF07_2GBAND_SHIFT = 7,
RF08_RXDCK = 8,
RF09_RFK = 9,
RF10_RF_INIT = 10,
RF11_RF_POWER = 11,
RF12_RXGAINK = 12,
RF13_THER_TRIM = 13,
RF14_PABIAS_TRIM = 14,
RF15_TSSI_TRIM = 15,
RF16_PSD = 16,
RF17_TSSI_TRK = 17,
RF18_XTAL_TRK = 18,
RF19_TX_SHAPE = 19
};
enum halrf_rf_mode {
RF_SHUT_DOWN = 0x0,
RF_STANDBY = 0x1,
RF_TX = 0x2,
RF_RX = 0x3,
RF_TXIQK = 0x4,
RF_DPK = 0x5,
RF_RXK1 = 0x6,
RF_RXK2 = 0x7
};
enum halrf_rfe_src_sel {
HALRF_PAPE_RFM = 0,
HALRF_GNT_BT_INV = 1,
HALRF_LNA0N = 2,
HALRF_LNAON_RFM = 3,
HALRF_TRSW_RFM = 4,
HALRF_TRSW_RFM_B = 5,
HALRF_GNT_BT = 6,
HALRF_ZERO = 7,
HALRF_ANTSEL_0 = 8,
HALRF_ANTSEL_1 = 9,
HALRF_ANTSEL_2 = 0xa,
HALRF_ANTSEL_3 = 0xb,
HALRF_ANTSEL_4 = 0xc,
HALRF_ANTSEL_5 = 0xd,
HALRF_ANTSEL_6 = 0xe,
HALRF_ANTSEL_7 = 0xf
};
/*@=[HALRF supportability]=======================================*/
enum halrf_ability {
HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
HAL_RF_IQK = BIT(RF01_IQK),
HAL_RF_LCK = BIT(RF02_LCK),
HAL_RF_DPK = BIT(RF03_DPK),
HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
HAL_RF_DACK = BIT(RF05_DACK),
HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
HAL_RF_RXDCK = BIT(RF08_RXDCK),
HAL_RF_RXGAINK = BIT(RF12_RXGAINK),
HAL_RF_THER_TRIM = BIT(RF13_THER_TRIM),
HAL_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
HAL_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
HAL_RF_TSSI_TRK = BIT(RF17_TSSI_TRK),
HAL_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
HAL_RF_TX_SHAPE = BIT(RF19_TX_SHAPE)
};
/*@=[HALRF Debug Component]=====================================*/
enum halrf_dbg_comp {
DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
DBG_RF_IQK = BIT(RF01_IQK),
DBG_RF_LCK = BIT(RF02_LCK),
DBG_RF_DPK = BIT(RF03_DPK),
DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
DBG_RF_DACK = BIT(RF05_DACK),
DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
DBG_RF_RXDCK = BIT(RF08_RXDCK),
DBG_RF_RFK = BIT(RF09_RFK),
DBG_RF_INIT = BIT(RF10_RF_INIT),
DBG_RF_POWER = BIT(RF11_RF_POWER),
DBG_RF_RXGAINK = BIT(RF12_RXGAINK),
DBG_RF_THER_TRIM = BIT(RF13_THER_TRIM),
DBG_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
DBG_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
DBG_RF_PSD = BIT(RF16_PSD),
DBG_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
DBG_RF_FW = BIT(28),
DBG_RF_MP = BIT(29),
DBG_RF_TMP = BIT(30),
DBG_RF_CHK = BIT(31)
};
/*@--------------------------[Structure]-------------------------------------*/
struct rfk_location {
enum band_type cur_band;
enum channel_width cur_bw;
u8 cur_ch;
};
struct halrf_fem_info {
u8 elna_2g; /*@with 2G eLNA NO/Yes = 0/1*/
u8 elna_5g; /*@with 5G eLNA NO/Yes = 0/1*/
u8 elna_6g; /*@with 6G eLNA NO/Yes = 0/1*/
u8 epa_2g; /*@with 2G ePA NO/Yes = 0/1*/
u8 epa_5g; /*@with 5G ePA NO/Yes = 0/1*/
u8 epa_6g; /*@with 6G ePA NO/Yes = 0/1*/
};
#if 1 /* all rf operation usage (header) */
/* clang-format on */
#define RF_PATH_MAX_NUM (8)
#define RF_TASK_RECORD_MAX_TIMES (16)
#define RF_BACKUP_MAC_REG_MAX_NUM (16)
#define RF_BACKUP_BB_REG_MAX_NUM (16)
#define RF_BACKUP_RF_REG_MAX_NUM (16)
struct halrf_iqk_ops {
u8 (*iqk_kpath)(struct rf_info *rf, enum phl_phy_idx phy_idx);
bool (*iqk_mcc_page_sel)(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
void (*iqk_get_ch_info)(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
void (*iqk_preset)(struct rf_info *rf, u8 path);
void (*iqk_macbb_setting)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
void (*iqk_start_iqk)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
void (*iqk_restore)(struct rf_info *rf, u8 path);
void (*iqk_afebb_restore)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
};
struct rfk_iqk_info {
struct halrf_iqk_ops *rf_iqk_ops;
u8 rf_max_path_num;
u32 rf_iqk_version;
u8 rf_iqk_ch_num;
u8 rf_iqk_path_num;
const u32 *backup_mac_reg;
u32 backup_mac_reg_num;
const u32 *backup_bb_reg;
u32 backup_bb_reg_num;
const u32 *backup_rf_reg;
u32 backup_rf_reg_num;
};
/* clang-format off */
#endif /* all rf operation usage (header) */
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
struct halrf_fw_offload {
enum rtw_mac_src_cmd_ofld src;
enum rtw_mac_cmd_type_ofld type;
u8 lc;
enum rtw_mac_rf_path rf_path;
u16 offset;
u16 id;
u32 value;
u32 mask;
};
#endif
struct halrf_rx_dck_info {
bool is_afe;
struct rfk_location loc[KPATH]; /*max RF path*/
};
struct rf_info {
struct rtw_phl_com_t *phl_com;
struct rtw_hal_com_t *hal_com;
/*[Common Info]*/
u32 ic_type;
u8 num_rf_path;
/*[System Info]*/
bool rf_init_ready;
u32 rf_sys_up_time;
bool rf_watchdog_en;
bool rf_ic_api_en;
/*[DM Info]*/
u32 support_ability;
u32 manual_support_ability;
/*[FW Info]*/
u32 fw_dbg_component;
/*[Drv Dbg Info]*/
u32 dbg_component;
u8 cmn_dbg_msg_period;
u8 cmn_dbg_msg_cnt;
/*[BTC / RFK Info ]*/
bool rfk_is_processing;
bool is_bt_iqk_timeout;
/*[initial]*/
u8 pre_rxbb_bw[KPATH];
/*[TSSI Info]*/
bool is_tssi_mode[4]; /*S0/S1*/
/*[Thermal Trigger]*/
bool is_thermal_trigger;
/*[Do Coex]*/
bool is_coex;
/*[watchdog]*/
bool is_watchdog_stop;
/*[thermal rek indictor]*/
bool rfk_do_thr_rek;
/*reg check*/
u32 rfk_reg[2048];
u32 rfc_reg[2][10];
u32 rfk_check_fail_count;
/*fast channel switch*/
u8 ther_init;
u32 fcs_rfk_ok_map;
u8 pre_chl_idx;
u8 pre_ther_idx;
/* [Check NCTL Done status Read Times] */
u32 nctl_ck_times[2]; /* 0xbff8 0x80fc*/
/*@=== [HALRF Structure] ============================================*/
struct halrf_pwr_track_info pwr_track;
struct halrf_tssi_info tssi;
struct halrf_xtal_info xtal_track;
struct halrf_iqk_info iqk;
struct halrf_dpk_info dpk;
struct halrf_rx_dck_info rx_dck;
struct halrf_dack_info dack;
struct halrf_gapk_info gapk;
struct halrf_pwr_info pwr_info;
struct halrf_radio_info radio_info;
struct halrf_fem_info fem;
struct rf_dbg_cmd_info rf_dbg_cmd_i;
struct halrf_rx_gain_k_info rx_gain_k;
struct halrf_psd_data psd;
struct rfk_location iqk_loc[2]; /*S0/S1*/
struct rfk_location dpk_loc[2]; /*S0/S1*/
struct rfk_location gapk_loc[2]; /*S0/S1*/
struct rfk_iqk_info *rfk_iqk_info;
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
struct halrf_fw_offload fwofld;
#endif
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf.h
|
C
|
agpl-3.0
| 7,743
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
bool halrf_bw_setting_8852b(struct rf_info *rf, enum rf_path path, enum channel_width bw, bool is_dav)
{
u32 rf_reg18 = 0;
u32 reg_reg18_addr = 0x0;
RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__);
if(is_dav)
reg_reg18_addr =0x18;
else
reg_reg18_addr =0x10018;
rf_reg18 = halrf_rrf(rf, path, reg_reg18_addr, MASKRF);
/*==== [Error handling] ====*/
if (rf_reg18 == INVALID_RF_DATA) {
RF_DBG(rf, DBG_RF_RFK, "[RFK]Invalid RF_0x18 for Path-%d\n", path);
return false;
}
rf_reg18 &= ~(BIT(11) | BIT(10));
/*==== [Switch bandwidth] ====*/
switch (bw) {
case CHANNEL_WIDTH_5:
case CHANNEL_WIDTH_10:
case CHANNEL_WIDTH_20:
/*RF bandwidth */
rf_reg18 |= (BIT(11) | BIT(10));
break;
case CHANNEL_WIDTH_40:
/*RF bandwidth */
rf_reg18 |= BIT(11);
break;
case CHANNEL_WIDTH_80:
/*RF bandwidth */
rf_reg18 |= BIT(10);
break;
default:
RF_DBG(rf, DBG_RF_RFK, "[RFK]Fail to set CH\n");
}
/*==== [Write RF register] ====*/
halrf_wrf(rf, path, reg_reg18_addr, MASKRF, rf_reg18);
RF_DBG(rf, DBG_RF_RFK, "[RFK] set %x at path%d, %x =0x%x\n",bw, path, reg_reg18_addr, halrf_rrf(rf, path, reg_reg18_addr, MASKRF));
return true;
}
bool halrf_ctrl_bw_8852b(struct rf_info *rf, enum channel_width bw)
{
bool is_dav;
//RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__);
/*==== Error handling ====*/
if (bw >= CHANNEL_WIDTH_MAX ) {
RF_DBG(rf, DBG_RF_RFK,"[RFK]Fail to switch bw(bw:%d)\n", bw);
return false;
}
//DAV
is_dav = true;
halrf_bw_setting_8852b(rf, RF_PATH_A, bw, is_dav);
halrf_bw_setting_8852b(rf, RF_PATH_B, bw, is_dav);
//DDV
is_dav = false;
halrf_bw_setting_8852b(rf, RF_PATH_A, bw, is_dav);
halrf_bw_setting_8852b(rf, RF_PATH_B, bw, is_dav);
//RF_DBG(rf, DBG_RF_RFK, "[RFK] BW: %d\n", bw);
//RF_DBG(rf, DBG_RF_RFK, "[RFK] 0x18 = 0x%x\n",halrf_rrf(rf, RF_PATH_A, 0x18, MASKRF));
return true;
}
bool halrf_ch_setting_8852b(struct rf_info *rf, enum rf_path path, u8 central_ch,
bool *is_2g_ch, bool is_dav)
{
u32 rf_reg18 = 0;
u32 reg_reg18_addr = 0x0;
RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__);
if(is_dav)
reg_reg18_addr = 0x18;
else
reg_reg18_addr =0x10018;
rf_reg18 = halrf_rrf(rf, path, reg_reg18_addr, MASKRF);
/*==== [Error handling] ====*/
if (rf_reg18 == INVALID_RF_DATA) {
RF_DBG(rf, DBG_RF_RFK, "[RFK]Invalid RF_0x18 for Path-%d\n", path);
return false;
}
*is_2g_ch = (central_ch <= 14) ? true : false;
/*==== [Set RF Reg 0x18] ====*/
rf_reg18 &= ~0x303ff; /*[17:16],[9:8],[7:0]*/
rf_reg18 |= central_ch; /* Channel*/
/*==== [5G Setting] ====*/
if (!*is_2g_ch)
rf_reg18 |= (BIT(16) | BIT(8));
halrf_wrf(rf, path, reg_reg18_addr, MASKRF, rf_reg18);
halrf_delay_us(rf, 100);
halrf_wrf(rf, path, 0xcf, BIT(0), 0);
halrf_wrf(rf, path, 0xcf, BIT(0), 1);
RF_DBG(rf, DBG_RF_RFK, "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n", central_ch, path, reg_reg18_addr, halrf_rrf(rf, path, reg_reg18_addr, MASKRF));
return true;
}
bool halrf_ctrl_ch_8852b(struct rf_info *rf, u8 central_ch)
{
bool is_2g_ch;
bool is_dav;
//RF_DBG(rf, DBG_RF_RFK, "[RFK]===> %s\n", __func__);
/*==== Error handling ====*/
if ((central_ch > 14 && central_ch < 36) ||
(central_ch > 64 && central_ch < 100) ||
(central_ch > 144 && central_ch < 149) ||
central_ch > 177 ) {
RF_DBG(rf, DBG_RF_RFK, "[RFK]Invalid CH:%d \n", central_ch);
return false;
}
//DAV
is_dav = true;
halrf_ch_setting_8852b(rf, RF_PATH_A, central_ch, &is_2g_ch, is_dav);
halrf_ch_setting_8852b(rf, RF_PATH_B, central_ch, &is_2g_ch, is_dav);
//DDV
is_dav = false;
halrf_ch_setting_8852b(rf, RF_PATH_A, central_ch, &is_2g_ch, is_dav);
halrf_ch_setting_8852b(rf, RF_PATH_B, central_ch, &is_2g_ch, is_dav);
//RF_DBG(rf, DBG_RF_RFK, "[RFK] CH: %d\n", central_ch);
return true;
}
void halrf_set_lo_8852b(struct rf_info *rf, bool is_on, enum rf_path path)
{
if (is_on) {
halrf_rf_direct_cntrl_8852b(rf, path, false);
halrf_wrf(rf, path, 0x0, MASKRFMODE, 0x2);
halrf_wrf(rf, path, 0x58, BIT(1), 0x1);
halrf_wrf(rf, path, 0xde, 0x1800, 0x3);
halrf_wrf(rf, path, 0x56, 0x1c00, 0x1);
halrf_wrf(rf, path, 0x56, 0x1e0, 0x1);
} else {
halrf_wrf(rf, path, 0x58, BIT(1), 0x0);
halrf_rf_direct_cntrl_8852b(rf, path, true);
halrf_wrf(rf, path, 0xde, 0x1800, 0x0);
}
}
void halrf_rf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb)
{
if (is_bybb)
halrf_wrf(rf, path, 0x5, BIT(0), 0x1);
else
halrf_wrf(rf, path, 0x5, BIT(0), 0x0);
}
void halrf_drf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb)
{
if (is_bybb)
halrf_wrf(rf, path, 0x10005, BIT(0), 0x1);
else
halrf_wrf(rf, path, 0x10005, BIT(0), 0x0);
}
void halrf_lo_test_8852b(struct rf_info *rf, bool is_on, enum rf_path path)
{
switch (path) {
case RF_PATH_A:
halrf_set_lo_8852b(rf, is_on, RF_PATH_A);
halrf_set_lo_8852b(rf, false, RF_PATH_B);
break;
case RF_PATH_B:
halrf_set_lo_8852b(rf, false, RF_PATH_A);
halrf_set_lo_8852b(rf, is_on, RF_PATH_B);
break;
case RF_PATH_AB:
halrf_set_lo_8852b(rf, is_on, RF_PATH_A);
halrf_set_lo_8852b(rf, is_on, RF_PATH_B);
break;
default:
break;
}
}
u8 halrf_kpath_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx) {
RF_DBG(rf, DBG_RF_RFK, "[RFK]dbcc_en: %x, PHY%d\n", rf->hal_com->dbcc_en, phy_idx);
if (!rf->hal_com->dbcc_en) {
return RF_AB;
} else {
if (phy_idx == HW_PHY_0)
return RF_A;
else
return RF_B;
}
}
void _rx_dck_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe)
{
struct halrf_rx_dck_info *rx_dck = &rf->rx_dck;
rx_dck->is_afe = is_afe;
rx_dck->loc[path].cur_band = rf->hal_com->band[phy].cur_chandef.band;
rx_dck->loc[path].cur_bw = rf->hal_com->band[phy].cur_chandef.bw;
rx_dck->loc[path].cur_ch = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_RXDCK, "[RX_DCK] ==== S%d RX DCK (%s / CH%d / %s / by %s)====\n", path,
rx_dck->loc[path].cur_band == 0 ? "2G" :
(rx_dck->loc[path].cur_band == 1 ? "5G" : "6G"),
rx_dck->loc[path].cur_ch,
rx_dck->loc[path].cur_bw == 0 ? "20M" :
(rx_dck->loc[path].cur_bw == 1 ? "40M" : "80M"),
rx_dck->is_afe ? "AFE" : "RFC");
}
void halrf_set_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe)
{
u8 phy_map;
u32 ori_val, i = 0;
phy_map = (BIT(phy) << 4) | BIT(path);
_rx_dck_info_8852b(rf, phy, path, is_afe);
if (is_afe) {
ori_val = halrf_rreg(rf, 0x12a0 + (path << 13), MASKDWORD);
halrf_wreg(rf, 0x12b8 + (path << 13), BIT(30), 0x1); /*debug en*/
//halrf_wreg(rf, 0x12a0 + (path << 13), BIT(19), 0x1);
//halrf_wreg(rf, 0x12a0 + (path << 13), 0x00070000, 0x3); /*ADC 320M*/
halrf_wreg(rf, 0x12a0 + (path << 13), 0x000F0000, 0xb);
//halrf_wreg(rf, 0x12d8 + (path << 13), BIT(5) | BIT(4), 0x3); /*offset manual en*/
//halrf_wreg(rf, 0x12d8 + (path << 13), BIT(7) | BIT(6), 0x3); /*avg 0:16; 1:32; 2:64; 3:128*/
halrf_wreg(rf, 0xc0f4 + (path << 8), 0x000000F0, 0xf); /*offset manual en*/
halrf_wreg(rf, 0x030c, 0x0f000000, 0x3); /*adc en*/
halrf_wreg(rf, 0x032c, BIT(30), 0x0); /*adc clk*/
halrf_wreg(rf, 0x032c, BIT(22), 0x0); /*filter reset*/
halrf_wreg(rf, 0x032c, BIT(22), 0x1); /*filter reset release*/
halrf_wreg(rf, 0x032c, BIT(18) | BIT(17) | BIT(16), 0x1); /*connect with RXBB*/
halrf_wreg(rf, 0x5864, BIT(29), 0x1); /*iqk_control_sw_si*/
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080);
halrf_wreg(rf, 0x8034, MASKDWORD, 0x00000020);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00000100);
halrf_wreg(rf, 0x81e0, MASKDWORD, 0x02000000);
halrf_wreg(rf, 0x82e0, MASKDWORD, 0x02100000);
halrf_wreg(rf, 0x8000, BIT(2) | BIT(1), path); /*subpage_id*/
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_START);
halrf_wreg(rf, 0x80ac, MASKDWORD, 0xfc030000);
halrf_wreg(rf, 0x80ac, MASKDWORD, 0x7c030000);
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x34);
while ((halrf_rreg(rf, 0x80fc, BIT(16)) == 0x0) && (i < 500)) {
halrf_delay_us(rf, 2);
i++;
}
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_STOP);
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x12b8 + (path << 13), BIT(30), 0x0); /*debug en*/
halrf_wreg(rf, 0x12a0 + (path << 13), MASKDWORD, ori_val);
halrf_wreg(rf, 0x5864, BIT(29), 0x0); /*iqk_control_sw_si*/
} else {
halrf_wrf(rf, path, 0x93, 0x0000f, 0x0); /*0: from RFC; 1: from AFE*/
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_START);
halrf_wrf(rf, path, 0x92, BIT(0), 0x0);
halrf_wrf(rf, path, 0x92, BIT(0), 0x1);
for (i = 0; i < 30; i++) /*delay 600us*/
halrf_delay_us(rf, 20);
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_RXDCK, RFK_ONESHOT_STOP);
}
#if 0
RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] 0x92 = 0x%x, 0x93 = 0x%x\n",
halrf_rrf(rf, path, 0x92, MASKRF),
halrf_rrf(rf, path, 0x93, MASKRF));
#endif
}
bool halrf_rx_dck_check_8852b(struct rf_info *rf, enum rf_path path)
{
u8 addr;
bool is_fail = false;
if (halrf_rreg(rf, 0xc400 + path * 0x1000, 0xF0000) == 0x0)
return is_fail = true;
else if (halrf_rreg(rf, 0xc400 + path * 0x1000, 0x0F000) == 0x0)
return is_fail = true;
else if (halrf_rreg(rf, 0xc440 + path * 0x1000, 0xF0000) == 0x0)
return is_fail = true;
else if (halrf_rreg(rf, 0xc440 + path * 0x1000, 0x0F000) == 0x0)
return is_fail = true;
else {
for (addr = 0x0; addr < 0x20; addr++) {
if (halrf_rreg(rf, 0xc400 + path * 0x1000 + addr * 4, 0x00FC0) == 0x0)
return is_fail = true;
}
for (addr = 0x0; addr < 0x20; addr++) {
if (halrf_rreg(rf, 0xc400 + path * 0x1000 + addr * 4, 0x0003F) == 0x0)
return is_fail = true;
}
}
return is_fail;
}
void halrf_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe)
{
u8 path, dck_tune;
u32 rf_reg5;
RF_DBG(rf, DBG_RF_RXDCK, "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n",
RXDCK_VER_8852B, rf->hal_com->cv);
for (path = 0; path < 2; path++) {
rf_reg5 = halrf_rrf(rf, path, 0x5, MASKRF);
dck_tune = (u8)halrf_rrf(rf, path, 0x92, BIT(1));
if (rf->is_tssi_mode[path])
halrf_wreg(rf, 0x5818 + (path << 13), BIT(30), 0x1); /*TSSI pause*/
halrf_wrf(rf, path, 0x5, BIT(0), 0x0);
halrf_wrf(rf, path, 0x92, BIT(1), 0x0);
//halrf_wrf(rf, path, 0x8f, BIT(11) | BIT(10), 0x1); /*EN_TIA_IDAC_LSB[1:0]*/
halrf_wrf(rf, path, 0x00, MASKRFMODE, RF_RX);
halrf_set_rx_dck_8852b(rf, phy, path, is_afe);
#if 0
if (halrf_rx_dck_check_8852b(rf, path)) {
RF_DBG(rf, DBG_RF_RFK, "[RX_DCK] S%d RX_DCK value = 0 happen!!!\n", path);
halrf_wrf(rf, path, 0x8f, BIT(11) | BIT(10), 0x2); /*EN_TIA_IDAC_LSB[1:0]*/
halrf_set_rx_dck_8852b(rf, phy, path, is_afe);
}
#endif
halrf_wrf(rf, path, 0x92, BIT(1), dck_tune);
halrf_wrf(rf, path, 0x5, MASKRF, rf_reg5);
if (rf->is_tssi_mode[path])
halrf_wreg(rf, 0x5818 + (path << 13), BIT(30), 0x0); /*TSSI resume*/
}
}
void halrf_rx_dck_onoff_8852b(struct rf_info *rf, bool is_enable)
{
u8 path;
for (path = 0; path < 2; path++) {
halrf_wrf(rf, path, 0x93, BIT(0), !is_enable);
if (!is_enable) {
halrf_wrf(rf, path, 0x92, 0xFFC00, 0x220); /*[19:10]*/
halrf_wrf(rf, path, 0x93, 0xFFC00, 0x220); /*[19:10]*/
}
}
}
void halrf_rck_8852b(struct rf_info *rf, enum rf_path path)
{
u8 cnt = 0;
u32 rf_reg5;
u32 rck_val = 0;
RF_DBG(rf, DBG_RF_RFK, "[RCK] ====== S%d RCK ======\n", path);
rf_reg5 = halrf_rrf(rf, path, 0x5, MASKRF);
halrf_wrf(rf, path, 0x5, BIT(0), 0x0);
halrf_wrf(rf, path, 0x0, MASKRFMODE, RF_RX);
RF_DBG(rf, DBG_RF_RFK, "[RCK] RF0x00 = 0x%05x\n", halrf_rrf(rf, path, 0x00, MASKRF));
/*RCK trigger*/
halrf_wrf(rf, path, 0x1b, MASKRF, 0x00240);
while ((halrf_rrf(rf, path, 0x1c, BIT(3)) == 0x00) && (cnt < 10)) {
halrf_delay_us(rf, 2);
cnt++;
}
rck_val = halrf_rrf(rf, path, 0x1b, 0x07C00); /*[14:10]*/
RF_DBG(rf, DBG_RF_RFK, "[RCK] rck_val = 0x%x, count = %d\n", rck_val, cnt);
halrf_wrf(rf, path, 0x1b, MASKRF, rck_val);
halrf_wrf(rf, path, 0x5, MASKRF, rf_reg5);
RF_DBG(rf, DBG_RF_RFK, "[RCK] RF 0x1b = 0x%x\n",
halrf_rrf(rf, path, 0x1b, MASKRF));
}
void iqk_backup_8852b(struct rf_info *rf, enum rf_path path)
{
return;
}
void halrf_bf_config_rf_8852b(struct rf_info *rf)
{
u8 i;
for (i = 0; i < 2; i++) {
halrf_wrf(rf, (enum rf_path)i, 0xef, BIT(19), 0x1);
halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0x1);
halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001);
halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0xb2120);
halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0x2);
halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001);
halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0xfe124);
halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0x3);
halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001);
halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0x30d7c);
halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0xa);
halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001);
halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0x30d7e);
halrf_wrf(rf, (enum rf_path)i, 0x33, 0xf, 0xb);
halrf_wrf(rf, (enum rf_path)i, 0x3e, MASKRF, 0x00001);
halrf_wrf(rf, (enum rf_path)i, 0x3f, MASKRF, 0x30d7d);
halrf_wrf(rf, (enum rf_path)i, 0xef, BIT(19), 0x0);
}
}
void halrf_set_dpd_backoff_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u8 tx_scale, ofdm_bkof, path, kpath;
kpath = halrf_kpath_8852b(rf, phy);
ofdm_bkof = (u8)halrf_rreg(rf, 0x44a0 + (phy << 13), 0x0001F000); /*[16:12]*/
tx_scale = (u8)halrf_rreg(rf, 0x44a0 + (phy << 13), 0x0000007F); /*[6:0]*/
if ((ofdm_bkof + tx_scale) >= 44) { /*move dpd backoff to bb, and set dpd backoff to 0*/
dpk->dpk_gs[phy] = 0x7f;
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
if (kpath & BIT(path)) {
halrf_wreg(rf, 0x81bc + (path << 8), 0x007FFFFF, 0x7f7f7f); /*[22:0]*/
RF_DBG(rf, DBG_RF_RFK, "[RFK] Set S%d DPD backoff to 0dB\n", path);
}
}
} else
dpk->dpk_gs[phy] = 0x5b;
}
void halrf_dpk_init_8852b(struct rf_info *rf)
{
halrf_set_dpd_backoff_8852b(rf, HW_PHY_0);
}
void halrf_set_rxbb_bw_8852b(struct rf_info *rf, enum channel_width bw, enum rf_path path)
{
halrf_wrf(rf, path, 0xee, BIT(2), 0x1);
halrf_wrf(rf, path, 0x33, 0x0001F, 0x12); /*[4:0]*/
if (bw == CHANNEL_WIDTH_20)
halrf_wrf(rf, path, 0x3f, 0x0003F, 0x1b); /*[5:0]*/
else if (bw == CHANNEL_WIDTH_40)
halrf_wrf(rf, path, 0x3f, 0x0003F, 0x13); /*[5:0]*/
else if (bw == CHANNEL_WIDTH_80)
halrf_wrf(rf, path, 0x3f, 0x0003F, 0xb); /*[5:0]*/
else
halrf_wrf(rf, path, 0x3f, 0x0003F, 0x3); /*[5:0]*/
RF_DBG(rf, DBG_RF_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
halrf_rrf(rf, path, 0x3f, 0x0003F));
halrf_wrf(rf, path, 0xee, BIT(2), 0x0);
}
void halrf_rxbb_bw_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum channel_width bw)
{
u8 kpath, path;
kpath = halrf_kpath_8852b(rf, phy);
for (path = 0; path < 2; path++) {
if ((kpath & BIT(path)) && (rf->pre_rxbb_bw[path] != bw)) {
halrf_set_rxbb_bw_8852b(rf, bw, path);
rf->pre_rxbb_bw[path] = bw;
} else
RF_DBG(rf, DBG_RF_RFK,
"[RFK] S%d RXBB BW unchanged (pre_bw = 0x%x)\n",
path, rf->pre_rxbb_bw[path]);
}
}
void halrf_disconnect_notify_8852b(struct rf_info *rf, struct rtw_chan_def *chandef ) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 path, ch;
RF_DBG(rf, DBG_RF_RFK, "[IQK]===>%s\n", __func__);
/*[IQK disconnect]*/
for (ch = 0; ch < 2; ch++) {
for (path = 0; path < KPATH; path++) {
if (iqk_info->iqk_mcc_ch[ch][path] == chandef->center_ch)
iqk_info->iqk_mcc_ch[ch][path] = 0x0;
}
}
/*TXGAPK*/
for (ch = 0; ch < 2; ch++) {
if (txgapk_info->txgapk_mcc_ch[ch] == chandef->center_ch)
txgapk_info->txgapk_mcc_ch[ch] = 0x0;
}
}
bool halrf_check_mcc_ch_8852b(struct rf_info *rf, struct rtw_chan_def *chandef) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 path, ch;
bool check = false;
RF_DBG(rf, DBG_RF_RFK, "[IQK]===>%s, center_ch(%d)\n", __func__, chandef->center_ch);
/*[IQK check_mcc_ch]*/
for (ch = 0; ch < 2; ch++) {
for (path = 0; path < KPATH; path++) {
if (iqk_info->iqk_mcc_ch[ch][path] == chandef->center_ch) {
check = true;
return check;
}
}
}
return check;
}
void halrf_fw_ntfy_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 i = 0x0;
u32 data_to_fw[5] = {0};
u16 len = (u16) (sizeof(data_to_fw) / sizeof(u32))*4;
data_to_fw[0] = (u32) iqk_info->iqk_mcc_ch[0][0];
data_to_fw[1] = (u32) iqk_info->iqk_mcc_ch[0][1];
data_to_fw[2] = (u32) iqk_info->iqk_mcc_ch[1][0];
data_to_fw[3] = (u32) iqk_info->iqk_mcc_ch[1][1];
data_to_fw[4] = rf->hal_com->band[phy_idx].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_RFK, "[IQK] len = 0x%x\n", len);
for (i =0; i < 5; i++)
RF_DBG(rf, DBG_RF_RFK, "[IQK] data_to_fw[%x] = 0x%x\n", i, data_to_fw[i]);
halrf_fill_h2c_cmd(rf, len, FWCMD_H2C_GET_MCCCH, 0xa, H2CB_TYPE_DATA, (u32 *) data_to_fw);
return;
}
void halrf_before_one_shot_enable_8852b(struct rf_info *rf) {
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
/* set 0x80d4[21:16]=0x03 (before oneshot NCTL) to get report later */
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x03);
RF_DBG(rf, DBG_RF_RFK, "======> before set one-shot bit, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD));
}
bool halrf_one_shot_nctl_done_check_8852b(struct rf_info *rf, enum rf_path path) {
/* for check status */
u32 r_bff8 = 0;
u32 r_80fc = 0;
bool is_ready = false;
u16 count = 1;
rf->nctl_ck_times[0] = 0;
rf->nctl_ck_times[1] = 0;
/* for 0xbff8 check NCTL DONE */
while (count < 2000) {
r_bff8 = halrf_rreg(rf, 0xbff8, MASKBYTE0);
if (r_bff8 == 0x55) {
is_ready = true;
break;
}
halrf_delay_us(rf, 10);
count++;
}
halrf_delay_us(rf, 1);
/* txgapk_info->txgapk_chk_cnt[path][id][0] = count; */
rf->nctl_ck_times[0] = count;
RF_DBG(rf, DBG_RF_RFK, "======> check 0xBFF8[7:0] = 0x%x, IsReady = %d, ReadTimes = %d,delay 1 us\n", r_bff8, is_ready, count);
/* for 0x80fc check NCTL DONE */
count = 1;
is_ready = false;
while (count < 2000) {
r_80fc = halrf_rreg(rf, 0x80fc, MASKLWORD);
if (r_80fc == 0x8000) {
is_ready = true;
break;
}
halrf_delay_us(rf, 1);
count++;
}
halrf_delay_us(rf, 1);
/* txgapk_info->txgapk_chk_cnt[path][id][1] = count; */
rf->nctl_ck_times[1] = count;
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
RF_DBG(rf, DBG_RF_RFK, "======> check 0x80fc[15:0] = 0x%x, IsReady = %d, ReadTimes = %d, 0x%x= 0x%x \n", r_80fc, is_ready, count, 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD) );
return is_ready;
}
static u32 check_rfc_reg[] = {0x9f, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x10000, 0x1, 0x10001,
0x5, 0x10005, 0x8, 0x18, 0x10018,
0x2, 0x10002, 0x11, 0x10011, 0x53,
0x10055, 0x58, 0x63, 0x6e, 0x6f,
0x7e, 0x7f, 0x80, 0x81, 0x8d,
0x8f, 0x90, 0x92, 0x93, 0xa0,
0xb2, 0xc5};
static u32 check_dack_reg[] = {0x12a0, 0x32a0, 0x12b8, 0x32b8, 0x030c,
0x032c, 0xc000, 0xc004, 0xc020, 0xc024,
0xc100, 0xc104, 0xc120, 0xc124, 0xc0d4,
0xc1d4, 0xc0f0, 0xc0f4, 0xc1f0, 0xc1f4,
0xc05c, 0xc080, 0xc048, 0xc06c, 0xc060,
0xc084, 0xc05c, 0xc080, 0xc048, 0xc06c,
0xc060, 0xc084};
static u32 check_iqk_reg[] = {0x8000, 0x8004, 0x8008, 0x8080, 0x808c,
0x8120, 0x8124, 0x8138, 0x813c, 0x81dc,
0x8220, 0x8224, 0x8238, 0x823c, 0x82dc,
0x9fe0, 0x9fe4, 0x9fe8, 0x9fec, 0x9f30,
0x9f40, 0x9f50, 0x9f60, 0x9f70, 0x9f80,
0x9f90, 0x9fa0};
static u32 check_dpk_reg[] = {0x80b0, 0x81bc, 0x82bc, 0x81b4, 0x82b4,
0x81c4, 0x82c4, 0x81c8, 0x82c8, 0x58d4,
0x78d4};
static u32 check_tssi_reg[] = {0x0304, 0x5818, 0x581c, 0x5820, 0x1c60,
0x1c44, 0x5838, 0x5630, 0x5634, 0x58f8,
0x12c0, 0x120c, 0x1c04, 0x1c0c, 0x1c18,
0x7630, 0x7634, 0x7818, 0x781c, 0x7820,
0x3c60, 0x3c44, 0x7838, 0x78f8, 0x32c0,
0x320c, 0x3c04, 0x3c0c, 0x3c18};
void halrf_quick_checkrf_8852b(struct rf_info *rf)
{
u32 path, temp, i;
u32 len = sizeof(check_rfc_reg) / sizeof(u32);
u32 *add = (u32 *)check_rfc_reg;
/*check RFC*/
RF_DBG(rf, DBG_RF_CHK, "======RFC======\n");
for (path = 0; path < 2; path++) {
for (i = 0; i < len; i++ ) {
temp = halrf_rrf(rf, path, add[i], MASKRF);
RF_DBG(rf, DBG_RF_CHK, "RF%d 0x%x = 0x%x\n",
path,
add[i],
temp);
}
}
/*check DACK*/
RF_DBG(rf, DBG_RF_CHK, "======DACK======\n");
len = sizeof(check_dack_reg) / sizeof(u32);
add = check_dack_reg;
for (i = 0; i < len; i++ ) {
temp = halrf_rreg(rf, add[i], MASKDWORD);
RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n",
add[i],
temp);
}
/*check IQK*/
RF_DBG(rf, DBG_RF_CHK, "======IQK======\n");
len = sizeof(check_iqk_reg) / sizeof(u32);
add = check_iqk_reg;
for (i = 0; i < len; i++ ) {
temp = halrf_rreg(rf, add[i], MASKDWORD);
RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n",
add[i],
temp);
}
/*check DPK*/
RF_DBG(rf, DBG_RF_CHK, "======DPK======\n");
len = sizeof(check_dpk_reg) / sizeof(u32);
add = check_dpk_reg;
for (i = 0; i < len; i++ ) {
temp = halrf_rreg(rf, add[i], MASKDWORD);
RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n",
add[i],
temp);
}
/*check TSSI*/
RF_DBG(rf, DBG_RF_CHK, "======TSSI======\n");
len = sizeof(check_tssi_reg) / sizeof(u32);
add = check_tssi_reg;
for (i = 0; i < len; i++ ) {
temp = halrf_rreg(rf, add[i], MASKDWORD);
RF_DBG(rf, DBG_RF_CHK, "0x%x = 0x%x\n",
add[i],
temp);
}
}
static u32 backup_mac_reg_8852b[] = {0x0};
static u32 backup_bb_reg_8852b[] = {0x2344};
static u32 backup_rf_reg_8852b[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
#if 1
static struct halrf_iqk_ops iqk_ops= {
.iqk_kpath = halrf_kpath_8852b,
.iqk_mcc_page_sel = iqk_mcc_page_sel_8852b,
.iqk_get_ch_info = iqk_get_ch_info_8852b,
.iqk_preset = iqk_preset_8852b,
.iqk_macbb_setting = iqk_macbb_setting_8852b,
.iqk_start_iqk = iqk_start_iqk_8852b,
.iqk_restore = iqk_restore_8852b,
.iqk_afebb_restore = iqk_afebb_restore_8852b,
};
struct rfk_iqk_info rf_iqk_hwspec_8852b = {
.rf_iqk_ops = &iqk_ops,
.rf_max_path_num = 2,
.rf_iqk_version = iqk_version_8852b,
.rf_iqk_ch_num = 2,
.rf_iqk_path_num = 2,
#if 0
.backup_mac_reg = backup_mac_reg_8852b,
.backup_mac_reg_num = ARRAY_SIZE(backup_mac_reg_8852b),
#else
.backup_mac_reg = backup_mac_reg_8852b,
.backup_mac_reg_num = 0,
#endif
.backup_bb_reg = backup_bb_reg_8852b,
.backup_bb_reg_num = ARRAY_SIZE(backup_bb_reg_8852b),
.backup_rf_reg = backup_rf_reg_8852b,
.backup_rf_reg_num = ARRAY_SIZE(backup_rf_reg_8852b),
};
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.c
|
C
|
agpl-3.0
| 23,505
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_8852B_H__
#define __HALRF_8852B_H__
#ifdef RF_8852B_SUPPORT
#define RXDCK_VER_8852B 0x1
#define RCK_VER_8852B 0x1
void halrf_lo_test_8852b(struct rf_info *rf, bool is_on, enum rf_path path);
u8 halrf_kpath_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx);
void halrf_set_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe);
void halrf_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
void halrf_rx_dck_onoff_8852b(struct rf_info *rf, bool is_enable);
void halrf_rck_8852b(struct rf_info *rf, enum rf_path path);
void halrf_rf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb);
void halrf_drf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb);
void halrf_bf_config_rf_8852b(struct rf_info *rf);
extern struct rfk_iqk_info rf_iqk_hwspec_8852b;
void halrf_dpk_init_8852b(struct rf_info *rf);
bool halrf_ctrl_ch_8852b(struct rf_info *rf, u8 central_ch);
bool halrf_ctrl_bw_8852b(struct rf_info *rf, enum channel_width bw);
void halrf_rxbb_bw_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum channel_width bw);
void halrf_fw_ntfy_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx);
void halrf_disconnect_notify_8852b(struct rf_info *rf, struct rtw_chan_def *chandef ) ;
bool halrf_check_mcc_ch_8852b(struct rf_info *rf, struct rtw_chan_def *chandef) ;
void halrf_quick_checkrf_8852b(struct rf_info *rf);
void halrf_before_one_shot_enable_8852b(struct rf_info *rf);
bool halrf_one_shot_nctl_done_check_8852b(struct rf_info *rf, enum rf_path path);
#endif
#endif /* __HALRF_8852b_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b.h
|
C
|
agpl-3.0
| 2,579
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path)
{
halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x0);
halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
halrf_delay_10us(rf, 20);
return (u8)halrf_rrf(rf, rf_path, 0x42, 0x0007e);
}
u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u32 addr, u32 mask)
{
struct rtw_hal_com_t *hal = rf->hal_com;
u32 result, ori_val, bit_shift, reg_val;
result = rtw_hal_mac_get_pwr_reg(hal, phy, addr, &ori_val);
if (result)
RF_WARNING("=======>%s Get MAC(0x%x) fail, error code=%d\n",
__func__, addr, result);
else
RF_DBG(rf, DBG_RF_POWER, "Get MAC(0x%x) ok!!! 0x%08x\n",
addr, ori_val);
bit_shift = halrf_cal_bit_shift(mask);
reg_val = (ori_val & mask) >> bit_shift;
return reg_val;
}
u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u32 addr, u32 mask, u32 val)
{
struct rtw_hal_com_t *hal = rf->hal_com;
u32 result;
result = rtw_hal_mac_write_msk_pwr_reg(hal, phy, addr, mask, val);
if (result) {
RF_WARNING("=======>%s Set MAC(0x%x[0x%08x]) fail, error code=%d\n",
__func__, addr, mask, result);
return false;
} else
RF_DBG(rf, DBG_RF_POWER, "Set MAC(0x%x[0x%08x])=0x%08x ok!!! \n",
addr, mask, val);
return result;
}
bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u32 result;
s32 tmp_pwr;
u8 phy = 0;
u32 all_time_control = 0;
u32 gnt_bt_control = 0;
RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__);
all_time_control = tx_power_val & 0xffff;
gnt_bt_control = (tx_power_val & 0xffff0000) >> 16;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl]tx_power_val=0x%x all_time_control=0x%x gnt_bt_control=0x%x\n",
tx_power_val, all_time_control, gnt_bt_control);
if (all_time_control == 0xffff) {
/*Coex Disable*/
pwr->coex_pwr_ctl_enable = false;
pwr->coex_pwr = 0;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Disable all_time_control=0xffff!!!\n");
} else if (all_time_control == 0xeeee) {
/*DPK Disable*/
pwr->dpk_pwr_ctl_enable = false;
pwr->dpk_pwr = 0;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Disable all_time_control=0xeeee\n");
} else {
if (all_time_control & BIT(15)) {
/*DPK*/
pwr->dpk_pwr_ctl_enable = true;
pwr->dpk_pwr = all_time_control & 0x1ff;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Enable Set pwr->dpk_pwr = %d\n",
pwr->dpk_pwr);
} else {
/*Coex*/
pwr->coex_pwr_ctl_enable = true;
pwr->coex_pwr = all_time_control & 0x1ff;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Enable Set pwr->coex_pwr = %d\n",
pwr->coex_pwr);
}
}
if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == false) {
tmp_pwr = pwr->coex_pwr;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=false tmp_pwr=%d\n",
tmp_pwr);
} else if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == true) {
tmp_pwr = pwr->dpk_pwr;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=false dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
tmp_pwr);
} else if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == true) {
if (pwr->coex_pwr > pwr->dpk_pwr)
tmp_pwr = pwr->dpk_pwr;
else
tmp_pwr = pwr->coex_pwr;
RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
tmp_pwr);
} else
tmp_pwr = 0;
if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == false) {
/*all-time control Disable*/
result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0xfffffc00, 0x0);
if (result) {
RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
__func__, result);
return false;
} else {
RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
rf->is_coex = false;
}
} else {
/*all-time control*/
result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0xfffffc00, ((tmp_pwr & 0x1ff) | BIT(9)));
if (result) {
RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
__func__, result);
return false;
} else {
RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
rf->is_coex = true;
}
}
if (gnt_bt_control == 0xffff) {
/*GNT_BT control*/
RF_DBG(rf, DBG_RF_POWER, "=======>%s gnt_bt_control = 0x%x\n",
__func__, gnt_bt_control);
result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x0);
result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xfffff007, 0x0);
if (result) {
RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
__func__, result);
return false;
} else {
RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
rf->is_coex = false;
}
} else {
/*GNT_BT control*/
RF_DBG(rf, DBG_RF_POWER, "=======>%s gnt_bt_control = 0x%x\n",
__func__, gnt_bt_control);
result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x1);
result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xfffff007, ((gnt_bt_control & 0x1ff) << 3));
if (result) {
RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
__func__, result);
return false;
} else {
RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
rf->is_coex = true;
}
}
return true;
}
s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf)
{
u8 tmp_a, tmp_b, tmp;
tmp_a = halrf_get_thermal(rf, RF_PATH_A);
tmp_b = halrf_get_thermal(rf, RF_PATH_B);
if (tmp_a > tmp_b)
tmp = tmp_a;
else
tmp = tmp_b;
if (tmp > 0x32)
return -1; /*Tx duty reduce*/
else if (tmp < 0x31)
return 1; /*Tx duty up*/
else
return 0; /*Tx duty the same*/
}
s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_xtal_info *xtal_trk = &rf->xtal_track;
u8 thermal_a = 0xff, thermal_b = 0xff;
u8 tmp_a, tmp_b, tmp;
s8 xtal_ofst = 0;
RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s phy=%d\n",
__func__, phy);
tmp_a = halrf_get_thermal(rf, RF_PATH_A);
tmp_b = halrf_get_thermal(rf, RF_PATH_B);
halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal_a, 1);
halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal_b, 1);
if (thermal_a == 0xff || thermal_b == 0xff ||
thermal_a == 0x0 || thermal_b == 0x0) {
RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s PG ThermalA=%d ThermalB=%d\n",
__func__, thermal_a, thermal_b);
return 0;
}
if (tmp_a > tmp_b) {
if (tmp_a > thermal_a) {
tmp = tmp_a - thermal_a;
if (tmp > DELTA_SWINGIDX_SIZE)
tmp = DELTA_SWINGIDX_SIZE - 1;
xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
} else {
tmp = thermal_a - tmp_a;
if (tmp > DELTA_SWINGIDX_SIZE)
tmp = DELTA_SWINGIDX_SIZE - 1;
xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
}
} else {
if (tmp_b > thermal_b) {
tmp = tmp_b - thermal_b;
if (tmp > DELTA_SWINGIDX_SIZE)
tmp = DELTA_SWINGIDX_SIZE - 1;
xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
} else {
tmp = thermal_b - tmp_b;
if (tmp > DELTA_SWINGIDX_SIZE)
tmp = DELTA_SWINGIDX_SIZE - 1;
xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
}
}
RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalA=%d ThermalA=%d\n",
thermal_a, tmp_a);
RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalB=%d ThermalB=%d\n",
thermal_b, tmp_b);
RF_DBG(rf, DBG_RF_XTAL_TRACK, "xtal_ofst[%d]=%d\n",
tmp, xtal_ofst);
return xtal_ofst;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.c
|
C
|
agpl-3.0
| 8,397
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_8852B_API_H__
#define __HALRF_8852B_API_H__
#ifdef RF_8852B_SUPPORT
u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path);
u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u32 addr, u32 mask);
u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u32 addr, u32 mask, u32 val);
bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val);
s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf);
s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf, enum phl_phy_idx phy);
#endif
#endif /* __INC_PHYDM_API_H_8852B__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api.h
|
C
|
agpl-3.0
| 1,597
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_8852B_API_EX_H__
#define __HALRF_8852B_API_EX_H__
#ifdef RF_8852B_SUPPORT
#endif
#endif /* __INC_PHYDM_API_H_8852B__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_8852b_api_ex.h
|
C
|
agpl-3.0
| 1,106
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
#define t_avg 100
void halrf_afe_init_8852b(struct rf_info *rf)
{
halrf_wmac32(rf, 0x8040, 0xf);
halrf_wreg(rf, 0xc0d4, MASKDWORD, 0x4486888c);
halrf_wreg(rf, 0xc0d8, MASKDWORD, 0xc6ba10e0);
halrf_wreg(rf, 0xc0dc, MASKDWORD, 0x30c52868);
halrf_wreg(rf, 0xc0e0, MASKDWORD, 0x05008128);
halrf_wreg(rf, 0xc0e4, MASKDWORD, 0x0000272b);
halrf_wreg(rf, 0xc1d4, MASKDWORD, 0x4486888c);
halrf_wreg(rf, 0xc1d8, MASKDWORD, 0xc6ba10e0);
halrf_wreg(rf, 0xc1dc, MASKDWORD, 0x30c52868);
halrf_wreg(rf, 0xc1e0, MASKDWORD, 0x05008128);
halrf_wreg(rf, 0xc1e4, MASKDWORD, 0x0000272b);
}
void halrf_dack_init_8852b(struct rf_info *rf)
{
}
void halrf_drck_8852b(struct rf_info *rf)
{
u32 c;
u32 rck_d;
RF_DBG(rf, DBG_RF_DACK, "[DACK]Ddie RCK start!!!\n");
halrf_wreg(rf, 0xc0cc, BIT(6), 0x1);
c = 0;
while (halrf_rreg(rf, 0xc0d0, BIT(3)) == 0) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]DRCK timeout\n");
break;
}
}
halrf_wreg(rf, 0xc0cc, BIT(6), 0x0);
halrf_wreg(rf, 0xc094, BIT(9), 0x1);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0xc094, BIT(9), 0x0);
/*manual write for LPS*/
rck_d = halrf_rreg(rf, 0xc0d0, 0xf8000);
/*RCK_SEL=0*/
halrf_wreg(rf, 0xc0cc, BIT(9), 0x0);
halrf_wreg(rf, 0xc0cc, 0x1f, rck_d);
RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc0cc = 0x%x\n", halrf_rreg(rf, 0xc0cc, MASKDWORD));
}
void halrf_addck_backup_8852b(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
halrf_wreg(rf, 0xc0f4, 0x300, 0x0);
dack->addck_d[0][0] = (u16)halrf_rreg(rf, 0xc0fc,0xffc00) ;
dack->addck_d[0][1] = (u16)halrf_rreg(rf, 0xc0fc,0x003ff) ;
halrf_wreg(rf, 0xc1f4, 0x300, 0x0);
dack->addck_d[1][0] = (u16)halrf_rreg(rf, 0xc1fc,0xffc00) ;
dack->addck_d[1][1] = (u16)halrf_rreg(rf, 0xc1fc,0x003ff) ;
}
void halrf_addck_reload_8852b(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
/*S0*/
halrf_wreg(rf, 0xc0f0, 0x3ff0000, dack->addck_d[0][0]);
halrf_wreg(rf, 0xc0f4, 0xf, (dack->addck_d[0][1] >> 6));
halrf_wreg(rf, 0xc0f0, 0xfc000000, (dack->addck_d[0][1] & 0x3f));
/*manual*/
halrf_wreg(rf, 0xc0f4, 0x30, 0x3);
/*S1*/
halrf_wreg(rf, 0xc1f0, 0x3ff0000, dack->addck_d[1][0]);
halrf_wreg(rf, 0xc1f4, 0xf, (dack->addck_d[1][1] >> 6));
halrf_wreg(rf, 0xc1f0, 0xfc000000, (dack->addck_d[1][1] & 0x3f));
/*manual*/
halrf_wreg(rf, 0xc1f4, 0x30, 0x3);
}
void halrf_dack_backup_s0_8852b(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
u8 i;
// u32 temp;
// halrf_wreg(rf, 0x5e00, BIT(3), 0x1);
// halrf_wreg(rf, 0x5e50, BIT(3), 0x1);
halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
/*MSBK*/
#if 0
for (i = 0; i < 0x10; i++) {
/*S0*/
halrf_wreg(rf, 0xc000, 0x1e, i);
temp = (u8)halrf_rreg(rf, 0xc04c, 0x7fc0);
RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc04c %d = 0x%x\n",
i, temp);
}
for (i = 0; i < 0x10; i++) {
/*S0*/
halrf_wreg(rf, 0xc020, 0x1e, i);
temp = (u8)halrf_rreg(rf, 0xc070, 0x7fc0);
RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc070 %d = 0x%x\n",
i, temp);
}
#endif
for (i = 0; i < 0x10; i++) {
/*S0*/
halrf_wreg(rf, 0xc000, 0x1e, i);
dack->msbk_d[0][0][i] = (u8)halrf_rreg(rf, 0xc05c, 0xff000000);
halrf_wreg(rf, 0xc020, 0x1e, i);
dack->msbk_d[0][1][i] = (u8)halrf_rreg(rf, 0xc080, 0xff000000);
}
/*biasK*/
dack->biask_d[0][0] = (u16)halrf_rreg(rf, 0xc048, 0xffc);
dack->biask_d[0][1] = (u16)halrf_rreg(rf, 0xc06c, 0xffc);
/*DADCK*/
dack->dadck_d[0][0] = (u8)halrf_rreg(rf, 0xc060, 0xff000000);
dack->dadck_d[0][1] = (u8)halrf_rreg(rf, 0xc084, 0xff000000);
}
void halrf_dack_backup_s1_8852b(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
u8 i;
// u32 temp;
// halrf_wreg(rf, 0x7e00, BIT(3), 0x1);
// halrf_wreg(rf, 0x7e50, BIT(3), 0x1);
halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
/*MSBK*/
#if 0
for (i = 0; i < 0x10; i++) {
/*S0*/
halrf_wreg(rf, 0xc100, 0x1e, i);
temp = (u8)halrf_rreg(rf, 0xc14c, 0x7fc0);
RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc14c %d = 0x%x\n",
i, temp);
}
for (i = 0; i < 0x10; i++) {
/*S0*/
halrf_wreg(rf, 0xc120, 0x1e, i);
temp = (u8)halrf_rreg(rf, 0xc170, 0x7fc0);
RF_DBG(rf, DBG_RF_DACK, "[DACK]0xc170 %d = 0x%x\n",
i, temp);
}
#endif
for (i = 0; i < 0x10; i++) {
/*S1*/
halrf_wreg(rf, 0xc100, 0x1e, i);
dack->msbk_d[1][0][i] = (u8)halrf_rreg(rf, 0xc15c, 0xff000000);
halrf_wreg(rf, 0xc120, 0x1e, i);
dack->msbk_d[1][1][i] = (u8)halrf_rreg(rf, 0xc180, 0xff000000);
}
/*biasK*/
dack->biask_d[1][0] = (u16)halrf_rreg(rf, 0xc148, 0xffc);
dack->biask_d[1][1] = (u16)halrf_rreg(rf, 0xc16c, 0xffc);
/*DADCK*/
dack->dadck_d[1][0] = (u8)halrf_rreg(rf, 0xc160, 0xff000000);
dack->dadck_d[1][1] = (u8)halrf_rreg(rf, 0xc184, 0xff000000);
}
void halrf_dack_reload_by_path_8852b(struct rf_info *rf, enum rf_path path)
{
struct halrf_dack_info *dack = &rf->dack;
u8 i;
u32 oft;
if (path == RF_PATH_A)
oft = 0;
else
oft = 0x100;
/*MSBK*/
for (i = 0; i < 16; i++) {
halrf_wreg(rf, 0xc000+ oft, 0x1e, i);
halrf_wreg(rf, 0xc004+ oft, 0x3fc0, dack->msbk_d[path][0][i]);
}
for (i = 0; i < 16; i++) {
halrf_wreg(rf, 0xc020+ oft, 0x1e, i);
halrf_wreg(rf, 0xc024+ oft, 0x3fc0, dack->msbk_d[path][1][i]);
}
/*biask*/
halrf_wreg(rf, 0xc004+ oft, 0x3ff00000, dack->biask_d[path][0]);
halrf_wreg(rf, 0xc024+ oft, 0x3ff00000, dack->biask_d[path][1]);
/*DADCK*/
}
void halrf_dack_reload_8852b(struct rf_info *rf, enum rf_path path)
{
u32 oft;
if (path == RF_PATH_A)
oft = 0;
else
oft = 0x100;
halrf_wreg(rf, 0xc004 + oft, 0x3, 0x2);
halrf_wreg(rf, 0xc024 + oft, 0x3, 0x2);
halrf_wreg(rf, 0xc004 + oft, BIT(5), 0x1);
halrf_wreg(rf, 0xc024 + oft, BIT(5), 0x1);
halrf_dack_reload_by_path_8852b(rf, path);
halrf_wreg(rf, 0xc004 + oft, 0x3, 0x0);
halrf_wreg(rf, 0xc024 + oft, 0x3, 0x0);
}
void halrf_check_addc_8852b(struct rf_info *rf, enum rf_path path)
{
u32 temp, dc_re, dc_im;
u32 i, m, p, t;
u32 re[t_avg], im[t_avg];
#if 1
halrf_wreg(rf, 0x20f4, BIT(24), 0x0);
halrf_wreg(rf, 0x20f8, 0x80000000, 0x1);
halrf_wreg(rf, 0x20f0, 0xff0000, 0x1);
halrf_wreg(rf, 0x20f0, 0xf00, 0x2);
halrf_wreg(rf, 0x20f0, 0xf, 0x0);
if (path == RF_PATH_A)
halrf_wreg(rf, 0x20f0, 0xc0, 0x2);
else
halrf_wreg(rf, 0x20f0, 0xc0, 0x3);
for (i = 0; i < t_avg; i++) {
temp = halrf_rreg(rf, 0x1730, 0xffffffff);
re[i] = (temp & 0xfff000) >> 12;
im[i] = temp & 0xfff;
// RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,re[i]= 0x%x,im[i] =0x%x\n",
// path, re[i], im[i]);
}
#else
for (i = 0; i < t_avg; i++) {
if (path == RF_PATH_A)
temp = halrf_rreg(rf, 0x1c8c, MASKDWORD);
else
temp = halrf_rreg(rf, 0x3c8c, MASKDWORD);
re[i] = (temp & 0xfff000) >> 12;
im[i] = temp & 0xfff;
// RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,re[i]= 0x%x,im[i] =0x%x\n",
// path, re[i], im[i]);
}
#endif
m = 0;
p = 0;
for (i = 0; i < t_avg; i++) {
if (re[i] > 0x800)
m = (0x1000 - re[i]) + m;
else
p = re[i] + p;
}
if (p > m) {
t = p - m;
t = t / t_avg;
} else {
t = m - p;
t = t / t_avg;
if (t != 0x0)
t = 0x1000 - t;
}
dc_re = t;
m = 0;
p = 0;
for (i = 0; i < t_avg; i++) {
if (im[i] > 0x800)
m = (0x1000 - im[i]) + m;
else
p = im[i] + p;
}
if (p > m) {
t = p - m;
t = t / t_avg;
} else {
t = m - p;
t = t / t_avg;
if (t != 0x0)
t = 0x1000 - t;
}
dc_im = t;
RF_DBG(rf, DBG_RF_DACK, "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n",
path, dc_re, dc_im);
}
void halrf_addck_8852b(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
u32 c;
/*S0*/
#if 1
/*manual off*/
halrf_wreg(rf, 0xc0f4, 0x30, 0x0);
halrf_wreg(rf, 0xc1d4, 0x30, 0x0);
/*1.ADC & clk enable */
halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
halrf_wreg(rf, 0x032c, BIT(30), 0x0);
/*4.Reset calibration*/
halrf_wreg(rf, 0x032c, BIT(22), 0x0);
halrf_wreg(rf, 0x032c, BIT(22), 0x1);
halrf_wreg(rf, 0x030c, 0x0f000000, 0xf);
/*2.ADC input not from RXBB & ADC input short*/
halrf_wreg(rf, 0x032c, BIT(16), 0x0);
halrf_wreg(rf, 0xc0d4, BIT(1), 0x1);
/*3.release ADC reset*/
halrf_wreg(rf, 0x030c, 0x0f000000, 0x3);
RF_DBG(rf, DBG_RF_DACK, "[DACK]before S0 ADDCK\n");
halrf_check_addc_8852b(rf, RF_PATH_A);
/*average 128 times*/
// halrf_wreg(rf, 0xc0f4, BIT(7) | BIT(6), 0x3);
/*5.trigger dc offset calibration*/
halrf_wreg(rf, 0xc0f4, BIT(11), 0x1);
halrf_wreg(rf, 0xc0f4, BIT(11), 0x0);
halrf_delay_us(rf, 1);
/*check if cal done*/
halrf_wreg(rf, 0xc0f4, 0x300, 0x1);
c = 0;
while (halrf_rreg(rf, 0xc0fc, BIT(0)) == 0) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 ADDCK timeout\n");
dack->addck_timeout[0] = true;
break;
}
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]ADDCK c = %d\n", c);
RF_DBG(rf, DBG_RF_DACK, "[DACK]after S0 ADDCK\n");
halrf_check_addc_8852b(rf, RF_PATH_A);
/*restore*/
halrf_wreg(rf, 0xc0d4, BIT(1), 0x0);
halrf_wreg(rf, 0x032c, BIT(16), 0x1);
halrf_wreg(rf, 0x030c, 0x0f000000, 0xc);
halrf_wreg(rf, 0x032c, BIT(30), 0x1);
halrf_wreg(rf, 0x12b8, BIT(30), 0x0);
#endif
/*S1*/
#if 1
/*1.ADC & clk enable */
halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
halrf_wreg(rf, 0x032c, BIT(30), 0x0);
/*4.Reset calibration*/
halrf_wreg(rf, 0x032c, BIT(22), 0x0);
halrf_wreg(rf, 0x032c, BIT(22), 0x1);
halrf_wreg(rf, 0x030c, 0x0f000000, 0xf);
/*2.ADC input not from RXBB & ADC input short*/
halrf_wreg(rf, 0x032c, BIT(16), 0x0);
halrf_wreg(rf, 0xc1d4, BIT(1), 0x1);
/*3.release ADC reset*/
halrf_wreg(rf, 0x030c, 0x0f000000, 0x3);
RF_DBG(rf, DBG_RF_DACK, "[DACK]before S1 ADDCK\n");
halrf_check_addc_8852b(rf, RF_PATH_B);
/*average 128 times*/
// halrf_wreg(rf, 0xc1f4, BIT(7) | BIT(6), 0x3);
/*5.trigger dc offset calibration*/
halrf_wreg(rf, 0xc1f4, BIT(11), 0x1);
halrf_wreg(rf, 0xc1f4, BIT(11), 0x0);
halrf_delay_us(rf, 1);
/*check if cal done*/
halrf_wreg(rf, 0xc1f4, 0x300, 0x1);
c = 0;
while (halrf_rreg(rf, 0xc1fc, BIT(0)) == 0) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 ADDCK timeout\n");
dack->addck_timeout[1] = true;
break;
}
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]ADDCK c = %d\n", c);
RF_DBG(rf, DBG_RF_DACK, "[DACK]after S1 ADDCK\n");
halrf_check_addc_8852b(rf, RF_PATH_B);
/*restore*/
halrf_wreg(rf, 0xc1d4, BIT(1), 0x0);
halrf_wreg(rf, 0x032c, BIT(16), 0x1);
halrf_wreg(rf, 0x030c, 0x0f000000, 0xc);
halrf_wreg(rf, 0x032c, BIT(30), 0x1);
halrf_wreg(rf, 0x32b8, BIT(30), 0x0);
#endif
}
void halrf_check_dadc_8852b(struct rf_info *rf, enum rf_path path)
{
halrf_wreg(rf, 0x032c, BIT(30), 0x0);
halrf_wreg(rf, 0x030c, 0x0f000000, 0xf);
halrf_wreg(rf, 0x030c, 0x0f000000, 0x3);
halrf_wreg(rf, 0x032c, BIT(16), 0x0);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x12dc, BIT(0), 0x1);
halrf_wreg(rf, 0x12e8, BIT(2), 0x1);
halrf_wrf(rf, RF_PATH_A, 0x8f, BIT(13), 0x1);
} else {
halrf_wreg(rf, 0x32dc, BIT(0), 0x1);
halrf_wreg(rf, 0x32e8, BIT(2), 0x1);
halrf_wrf(rf, RF_PATH_B, 0x8f, BIT(13), 0x1);
}
halrf_check_addc_8852b(rf, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x12dc, BIT(0), 0x0);
halrf_wreg(rf, 0x12e8, BIT(2), 0x0);
halrf_wrf(rf, RF_PATH_A, 0x8f, BIT(13), 0x0);
} else {
halrf_wreg(rf, 0x32dc, BIT(0), 0x0);
halrf_wreg(rf, 0x32e8, BIT(2), 0x0);
halrf_wrf(rf, RF_PATH_B, 0x8f, BIT(13), 0x0);
}
halrf_wreg(rf, 0x032c, BIT(16), 0x1);
}
void halrf_dack_8852b_s0(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
u32 c = 0;
/*step 1*/
halrf_wreg(rf, 0x12a0, BIT(15), 0x1);
halrf_wreg(rf, 0x12a0, 0x7000, 0x3);
/*step 2*/
halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
halrf_wreg(rf, 0x030c, BIT(28), 0x1);
halrf_wreg(rf, 0x032c, 0x80000000, 0x0);
/*step 3*/
halrf_wreg(rf, 0xc0d8, BIT(16), 0x1);
/*step 4*/
halrf_wreg(rf, 0xc0dc, BIT(27) | BIT(26), 0x3);
/*step 5*/
halrf_wreg(rf, 0xc004, BIT(30), 0x0);
halrf_wreg(rf, 0xc024, BIT(30), 0x0);
/*step 6*/
halrf_wreg(rf, 0xc004, 0x3ff00000, 0x30);
// halrf_wreg(rf, 0xc024, 0x3ff00000, 0x30);
/*step 7*/
halrf_wreg(rf, 0xc004, BIT(31) | BIT(30), 0x0);
// halrf_wreg(rf, 0xc024, BIT(31) | BIT(30), 0x0);
/*step 8*/
halrf_wreg(rf, 0xc004, BIT(17), 0x1);
halrf_wreg(rf, 0xc024, BIT(17), 0x1);
halrf_wreg(rf, 0xc00c, BIT(2), 0x0);
halrf_wreg(rf, 0xc02c, BIT(2), 0x0);
/*step 9*/ /*auto mode*/
halrf_wreg(rf, 0xc004, BIT(0), 0x1);
halrf_wreg(rf, 0xc024, BIT(0), 0x1);
halrf_delay_us(rf, 1);
/*step 10*/
c = 0x0;
while ((halrf_rreg(rf, 0xc040, BIT(31)) == 0) || (halrf_rreg(rf, 0xc064, BIT(31)) == 0)) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK timeout\n");
dack->msbk_timeout[0] = true;
break;
}
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
/*step 11*/
halrf_wreg(rf, 0xc0dc, BIT(27) | BIT(26), 0x0);
/*step 12*/
halrf_wreg(rf, 0xc00c, BIT(2), 0x1);
halrf_wreg(rf, 0xc02c, BIT(2), 0x1);
/*step 13*/
c = 0x0;
while ((halrf_rreg(rf, 0xc05c, BIT(2)) == 0) || (halrf_rreg(rf, 0xc080, BIT(2)) == 0)) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 DADCK timeout\n");
dack->dadck_timeout[0] = true;
break;
}
}
/*step 14*/ /*auto mode off*/
halrf_wreg(rf, 0xc004, BIT(0), 0x0);
halrf_wreg(rf, 0xc024, BIT(0), 0x0);
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
/*step 15*/
halrf_wreg(rf, 0xc0d8, BIT(16), 0x0);
/*step 16*/
halrf_wreg(rf, 0x12a0, BIT(15), 0x0);
halrf_wreg(rf, 0x12a0, 0x7000, 0x7);
RF_DBG(rf, DBG_RF_DACK, "[DACK]after S0 DADCK\n");
// halrf_check_dadc_8852b(rf, RF_PATH_A);
/*backup here*/
halrf_dack_backup_s0_8852b(rf);
// halrf_dack_reload_8852b(rf, RF_PATH_A);
/*step 17*/
halrf_wreg(rf, 0x12b8, BIT(30), 0x0);
}
void halrf_dack_8852b_s1(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
u32 c = 0;
/*step 1*/
halrf_wreg(rf, 0x32a0, BIT(15), 0x1);
halrf_wreg(rf, 0x32a0, 0x7000, 0x3);
/*step 2*/
halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
halrf_wreg(rf, 0x030c, BIT(28), 0x1);
halrf_wreg(rf, 0x032c, 0x80000000, 0x0);
/*step 3*/
halrf_wreg(rf, 0xc1d8, BIT(16), 0x1);
/*step 4*/
halrf_wreg(rf, 0xc1dc, BIT(27) | BIT(26), 0x3);
/*step 5*/
halrf_wreg(rf, 0xc104, BIT(30), 0x0);
halrf_wreg(rf, 0xc124, BIT(30), 0x0);
/*step 6*/
halrf_wreg(rf, 0xc104, 0x3ff00000, 0x30);
// halrf_wreg(rf, 0xc024, 0x3ff00000, 0x30);
/*step 7*/
halrf_wreg(rf, 0xc104, BIT(31) | BIT(30), 0x0);
// halrf_wreg(rf, 0xc124, BIT(31) | BIT(30), 0x0);
/*step 8*/
halrf_wreg(rf, 0xc104, BIT(17), 0x1);
halrf_wreg(rf, 0xc124, BIT(17), 0x1);
halrf_wreg(rf, 0xc10c, BIT(2), 0x0);
halrf_wreg(rf, 0xc12c, BIT(2), 0x0);
/*step 9*/ /*auto mode*/
halrf_wreg(rf, 0xc104, BIT(0), 0x1);
halrf_wreg(rf, 0xc124, BIT(0), 0x1);
halrf_delay_us(rf, 1);
/*step 10*/
c = 0x0;
while((halrf_rreg(rf, 0xc140, BIT(31)) == 0) && (halrf_rreg(rf, 0xc164, BIT(31)) == 0)) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK timeout\n");
dack->msbk_timeout[1] = true;
break;
}
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
/*step 11*/
halrf_wreg(rf, 0xc1dc, BIT(27) | BIT(26), 0x0);
/*step 12*/
halrf_wreg(rf, 0xc10c, BIT(2), 0x1);
halrf_wreg(rf, 0xc12c, BIT(2), 0x1);
halrf_delay_us(rf, 1);
/*step 13*/
c = 0x0;
while(halrf_rreg(rf, 0xc15c, BIT(2)) == 0 && halrf_rreg(rf, 0xc180, BIT(2)) == 0) {
c++;
halrf_delay_us(rf, 1);
if (c > 10000) {
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 DADCK timeout\n");
dack->dadck_timeout[1] = true;
break;
}
}
/*step 14*/ /*auto mode off*/
halrf_wreg(rf, 0xc104, BIT(0), 0x0);
halrf_wreg(rf, 0xc124, BIT(0), 0x0);
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK c = %d\n", c);
/*step 15*/
halrf_wreg(rf, 0xc1d8, BIT(16), 0x0);
/*step 16*/
halrf_wreg(rf, 0x32a0, BIT(15), 0x0);
halrf_wreg(rf, 0x32a0, 0x7000, 0x7);
RF_DBG(rf, DBG_RF_DACK, "[DACK]after S1 DADCK\n");
halrf_check_dadc_8852b(rf, RF_PATH_B);
/*backup here*/
halrf_dack_backup_s1_8852b(rf);
// halrf_dack_reload_8852b(rf, RF_PATH_B);
/*step 17*/
halrf_wreg(rf, 0x32b8, BIT(30), 0x0);
}
void halrf_dack_8852b(struct rf_info *rf)
{
halrf_dack_8852b_s0(rf);
halrf_dack_8852b_s1(rf);
}
void halrf_dack_dump_8852b(struct rf_info *rf)
{
struct halrf_dack_info *dack = &rf->dack;
u8 i;
u8 t;
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
dack->addck_d[0][0], dack->addck_d[0][1] );
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
dack->addck_d[1][0], dack->addck_d[1][1] );
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
dack->dadck_d[0][0], dack->dadck_d[0][1] );
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
dack->dadck_d[1][0], dack->dadck_d[1][1] );
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
dack->biask_d[0][0], dack->biask_d[0][1] );
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
dack->biask_d[1][0], dack->biask_d[1][1] );
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK ic:\n");
for (i = 0; i < 0x10; i++) {
t = dack->msbk_d[0][0][i];
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]S0 MSBK qc:\n");
for (i = 0; i < 0x10; i++) {
t = dack->msbk_d[0][1][i];
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK ic:\n");
for (i = 0; i < 0x10; i++) {
t = dack->msbk_d[1][0][i];
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
}
RF_DBG(rf, DBG_RF_DACK, "[DACK]S1 MSBK qc:\n");
for (i = 0; i < 0x10; i++) {
t = dack->msbk_d[1][1][i];
RF_DBG(rf, DBG_RF_DACK, "[DACK]0x%x\n", t);
}
}
void halrf_dac_cal_8852b(struct rf_info *rf, bool force)
{
struct halrf_dack_info *dack = &rf->dack;
u32 rf0_0, rf1_0;
u8 phy_map;
phy_map = (BIT(HW_PHY_0) << 4) | RF_AB;
#if 0
if (dack->dack_en) {
if (!force) {
halrf_dack_reload_8852a(rf);
RF_DBG(rf, DBG_RF_DACK, "[DACK]reload dack value\n");
return;
}
} else {
dack->dack_en = true;
}
#endif
dack->dack_done = false;
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK 0x1\n");
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK start!!!\n");
rf0_0 = halrf_rrf(rf,RF_PATH_A, 0x0, MASKRF);
rf1_0 = halrf_rrf(rf,RF_PATH_B, 0x0, MASKRF);
#if 1
halrf_afe_init_8852b(rf);
halrf_drck_8852b(rf);
halrf_wrf(rf, RF_PATH_A, 0x5, BIT(0), 0x0);
halrf_wrf(rf, RF_PATH_B, 0x5, BIT(0), 0x0);
halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, 0x337e1);
halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, 0x337e1);
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_START);
halrf_addck_8852b(rf);
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_STOP);
halrf_addck_backup_8852b(rf);
halrf_addck_reload_8852b(rf);
// halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, 0x40001);
// halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, 0x40001);
halrf_wrf(rf, RF_PATH_A, 0x1, MASKRF, 0x0);
halrf_wrf(rf, RF_PATH_B, 0x1, MASKRF, 0x0);
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_START);
halrf_dack_8852b(rf);
// halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DACK, RFK_ONESHOT_STOP);
halrf_dack_dump_8852b(rf);
dack->dack_done = true;
halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF, rf0_0);
halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF, rf1_0);
halrf_wrf(rf, RF_PATH_A, 0x5, BIT(0), 0x1);
halrf_wrf(rf, RF_PATH_B, 0x5, BIT(0), 0x1);
#endif
dack->dack_cnt++;
RF_DBG(rf, DBG_RF_DACK, "[DACK]DACK finish!!!\n");
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.c
|
C
|
agpl-3.0
| 19,870
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DACK_8852B_H__
#define __HALRF_DACK_8852B_H__
#ifdef RF_8852B_SUPPORT
#define DACK_VER_8852B 0x5
void halrf_dack_recover_8852b(struct rf_info *rf,
u8 offset,
enum rf_path path,
u32 val,
bool reload);
void halrf_dac_cal_8852b(struct rf_info *rf, bool force);
#endif
#endif /* __INC_PHYDM_API_H_8852A__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_dack_8852b.h
|
C
|
agpl-3.0
| 1,327
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
/*8852B DPK ver:0x9 20210713*/
void _dpk_bkup_kip_8852b(
struct rf_info *rf,
u32 *reg,
u32 reg_bkup[][DPK_KIP_REG_NUM_8852B],
u8 path)
{
u8 i;
for (i = 0; i < DPK_KIP_REG_NUM_8852B; i++) {
reg_bkup[path][i] = halrf_rreg(rf, reg[i] + (path << 8), MASKDWORD);
if (DPK_REG_DBG)
RF_DBG(rf, DBG_RF_DPK, "[DPK] Backup 0x%x = %x\n", reg[i]+ (path << 8), reg_bkup[path][i]);
}
}
void _dpk_bkup_bb_8852b(
struct rf_info *rf,
u32 *reg,
u32 reg_bkup[DPK_BB_REG_NUM_8852B])
{
u8 i;
for (i = 0; i < DPK_BB_REG_NUM_8852B; i++) {
reg_bkup[i] = halrf_rreg(rf, reg[i], MASKDWORD);
if (DPK_REG_DBG)
RF_DBG(rf, DBG_RF_DPK, "[DPK] Backup 0x%x = %x\n", reg[i], reg_bkup[i]);
}
}
void _dpk_bkup_rf_8852b(
struct rf_info *rf,
u32 *rf_reg,
u32 rf_bkup[][DPK_RF_REG_NUM_8852B],
u8 path)
{
u8 i;
for (i = 0; i < DPK_RF_REG_NUM_8852B; i++) {
rf_bkup[path][i] = halrf_rrf(rf, path, rf_reg[i], MASKRF);
if (DPK_REG_DBG)
RF_DBG(rf, DBG_RF_DPK, "[DPK] Backup RF S%d 0x%x = %x\n",
path, rf_reg[i], rf_bkup[path][i]);
}
}
void _dpk_reload_kip_8852b(
struct rf_info *rf,
u32 *reg,
u32 reg_bkup[][DPK_KIP_REG_NUM_8852B],
u8 path)
{
u8 i;
for (i = 0; i < DPK_KIP_REG_NUM_8852B; i++) {
halrf_wreg(rf, reg[i] + (path << 8), MASKDWORD, reg_bkup[path][i]);
if (DPK_REG_DBG)
RF_DBG(rf, DBG_RF_DPK, "[DPK] Reload 0x%x = %x\n", reg[i] + (path << 8),
reg_bkup[path][i]);
}
}
void _dpk_reload_bb_8852b(
struct rf_info *rf,
u32 *reg,
u32 reg_bkup[DPK_BB_REG_NUM_8852B])
{
u8 i;
for (i = 0; i < DPK_BB_REG_NUM_8852B; i++) {
halrf_wreg(rf, reg[i], MASKDWORD, reg_bkup[i]);
if (DPK_REG_DBG)
RF_DBG(rf, DBG_RF_DPK, "[DPK] Reload 0x%x = %x\n", reg[i],
reg_bkup[i]);
}
}
void _dpk_reload_rf_8852b(
struct rf_info *rf,
u32 *rf_reg,
u32 rf_bkup[][DPK_RF_REG_NUM_8852B],
u8 path)
{
u8 i;
for (i = 0; i < DPK_RF_REG_NUM_8852B; i++) {
halrf_wrf(rf, path, rf_reg[i], MASKRF, rf_bkup[path][i]);
if (DPK_REG_DBG)
RF_DBG(rf, DBG_RF_DPK, "[DPK] Reload RF S%d 0x%x = %x\n",
path, rf_reg[i], rf_bkup[path][i]);
}
}
u8 _dpk_one_shot_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
enum dpk_id id)
{
u8 r_bff8 = 0x0, phy_map;
u16 dpk_cmd = 0x0, count = 0;
phy_map = (BIT(phy) << 4) | BIT(path);
dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4)));
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DPK, RFK_ONESHOT_START);
halrf_wreg(rf, 0x8000, MASKDWORD, dpk_cmd);
r_bff8 = (u8)halrf_rreg(rf, 0xbff8, MASKBYTE0);
while (r_bff8 != 0x55 && count < 2000) {
halrf_delay_us(rf, 10);
r_bff8 = (u8)halrf_rreg(rf, 0xbff8, MASKBYTE0);
count++;
}
halrf_wreg(rf, 0x8010, MASKBYTE0, 0x0);
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_DPK, RFK_ONESHOT_STOP);
RF_DBG(rf, DBG_RF_DPK, "[DPK] one-shot for %s = 0x%04x (count=%d)\n",
id == 0x06 ? "LBK_RXIQK" : (id == 0x10 ? "SYNC" :
(id == 0x11 ? "MDPK_IDL" : (id == 0x12 ? "MDPK_MPA" :
(id == 0x13 ? "GAIN_LOSS" : (id == 0x14 ? "PWR_CAL" :
(id == 0x15 ? "DPK_RXAGC" : (id == 0x16 ? "KIP_PRESET" :
(id == 0x17 ? "KIP_RESOTRE" : "DPK_TXAGC")))))))),
dpk_cmd, count);
if (count == 2000) {
RF_DBG(rf, DBG_RF_DPK, "[DPK] one-shot over 20ms!!!!\n");
return 1;
} else
return 0;
}
void _dpk_information_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u8 kidx = dpk->cur_idx[path];
dpk->bp[path][kidx].band = rf->hal_com->band[phy].cur_chandef.band;
dpk->bp[path][kidx].ch = rf->hal_com->band[phy].cur_chandef.center_ch;
dpk->bp[path][kidx].bw = rf->hal_com->band[phy].cur_chandef.bw;
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
path, dpk->cur_idx[path], phy, rf->is_tssi_mode[path] ? "on" : "off",
rf->hal_com->dbcc_en ? "on" : "off",
dpk->bp[path][kidx].band == 0 ? "2G" : (dpk->bp[path][kidx].band == 1 ? "5G" : "6G"),
dpk->bp[path][kidx].ch,
dpk->bp[path][kidx].bw == 0 ? "20M" : (dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"));
}
void _dpk_bb_afe_setting_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kpath)
{
halrf_wreg(rf, 0x20fc, MASKHWORD, 0x0303);
halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
halrf_wreg(rf, 0x030c, MASKBYTE3, 0x13);
halrf_wreg(rf, 0x032c, MASKHWORD, 0x0041);
halrf_wreg(rf, 0x12b8, BIT(28), 0x1);
halrf_wreg(rf, 0x58c8, BIT(24), 0x1);
halrf_wreg(rf, 0x78c8, BIT(24), 0x1);
halrf_wreg(rf, 0x5864, BIT(31) | BIT(30), 0x3);
halrf_wreg(rf, 0x7864, BIT(31) | BIT(30), 0x3);
halrf_wreg(rf, 0x2008, 0x01FFFFFF, 0x1ffffff);
halrf_wreg(rf, 0x0c1c, BIT(2), 0x1);
halrf_wreg(rf, 0x0700, BIT(27), 0x1);
halrf_wreg(rf, 0x0c70, 0x000003FF, 0x3ff);
halrf_wreg(rf, 0x0c60, BIT(1) | BIT(0), 0x3);
halrf_wreg(rf, 0x0c6c, BIT(0), 0x1);
halrf_wreg(rf, 0x58ac, BIT(27), 0x1);
halrf_wreg(rf, 0x78ac, BIT(27), 0x1);
halrf_wreg(rf, 0x0c3c, BIT(9), 0x1); /*block OFDM CCA*/
halrf_wreg(rf, 0x2344, BIT(31), 0x1); /*block CCK CCA*/
halrf_wreg(rf, 0x4490, BIT(31), 0x1);
//halrf_wreg(rf, 0x12a0, BIT(14) | BIT(13) | BIT(12), 0x7);
//halrf_wreg(rf, 0x12a0, BIT(15), 0x1);
//halrf_wreg(rf, 0x12a0, BIT(18) | BIT(17) | BIT(16), 0x3);
//halrf_wreg(rf, 0x12a0, BIT(19), 0x1);
halrf_wreg(rf, 0x12a0, 0x000FF000, 0xbf); /*[19:12]*/
//halrf_wreg(rf, 0x32a0, BIT(18) | BIT(17) | BIT(16), 0x3);
//halrf_wreg(rf, 0x32a0, BIT(19), 0x1);
halrf_wreg(rf, 0x32a0, BIT(19) | BIT(18) | BIT(17) | BIT(16), 0xb);
//halrf_wreg(rf, 0x0700, BIT(24), 0x1);
//halrf_wreg(rf, 0x0700, BIT(26) | BIT(25), 0x2);
halrf_wreg(rf, 0x0700, BIT(26) | BIT(25) | BIT(24), 0x5);
halrf_wreg(rf, 0x20fc, MASKHWORD, 0x3333);
halrf_wreg(rf, 0x580c, BIT(15), 0x1); /*txbb_force_rdy*/
halrf_wreg(rf, 0x5800, MASKLWORD, 0x0000);/*txbb_max_min*/
halrf_wreg(rf, 0x780c, BIT(15), 0x1); /*txbb_force_rdy*/
halrf_wreg(rf, 0x7800, MASKLWORD, 0x0000); /*txbb_max_min*/
if (rf->hal_com->band[phy].cur_chandef.bw == 2) {/*extend ADC LPF BW*/
halrf_wreg(rf, 0xc0d8, BIT(13), 0x1);
halrf_wreg(rf, 0xc1d8, BIT(13), 0x1);
}
}
void _dpk_bb_afe_restore_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kpath)
{
halrf_wreg(rf, 0x20fc, MASKHWORD, 0x0303);
halrf_wreg(rf, 0x12b8, BIT(30), 0x0);
halrf_wreg(rf, 0x32b8, BIT(30), 0x0);
halrf_wreg(rf, 0x5864, BIT(31) | BIT(30), 0x0);
halrf_wreg(rf, 0x7864, BIT(31) | BIT(30), 0x0);
halrf_wreg(rf, 0x2008, 0x01FFFFFF, 0x0);
halrf_wreg(rf, 0x0c1c, BIT(2), 0x0);
halrf_wreg(rf, 0x0700, BIT(27), 0x0);
halrf_wreg(rf, 0x0c70, 0x000003FF, 0x63);
halrf_wreg(rf, 0x12a0, 0x000FF000, 0x00);
halrf_wreg(rf, 0x32a0, 0x000FF000, 0x00);
halrf_wreg(rf, 0x0700, BIT(26) | BIT(25) | BIT(24), 0x0);
halrf_wreg(rf, 0x5864, BIT(29), 0x0);
halrf_wreg(rf, 0x7864, BIT(29), 0x0);
//halrf_wreg(rf, 0x0c3c, BIT(9), 0x0); /*block OFDM CCA*/
//halrf_wreg(rf, 0x2344, BIT(31), 0x0); /*block CCK CCA*/
halrf_wreg(rf, 0x20fc, MASKHWORD, 0x0000);
halrf_wreg(rf, 0x58c8, BIT(24), 0x0);
halrf_wreg(rf, 0x78c8, BIT(24), 0x0);
halrf_wreg(rf, 0x0c3c, BIT(9), 0x0); /*block OFDM CCA*/
halrf_wreg(rf, 0x580c, BIT(15), 0x0); /*txbb_force_rdy*/
halrf_wreg(rf, 0x58e4, BIT(28) | BIT(27), 0x1); /*force rst*/
halrf_wreg(rf, 0x58e4, BIT(28) | BIT(27), 0x2); /*force rst release*/
halrf_wreg(rf, 0x780c, BIT(15), 0x0); /*txbb_force_rdy*/
halrf_wreg(rf, 0x78e4, BIT(28) | BIT(27), 0x1); /*force rst*/
halrf_wreg(rf, 0x78e4, BIT(28) | BIT(27), 0x2); /*force rst release*/
if (rf->hal_com->band[phy].cur_chandef.bw == 2) {/*extend ADC LPF BW*/
halrf_wreg(rf, 0xc0d8, BIT(13), 0x0);
halrf_wreg(rf, 0xc1d8, BIT(13), 0x0);
}
}
void _dpk_tssi_pause_8852b(
struct rf_info *rf,
enum rf_path path,
bool is_pause)
{
halrf_wreg(rf, 0x5818 + (path << 13), BIT(30), is_pause);
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d TSSI %s\n", path,
is_pause ? "pause" : "resume");
}
void _dpk_tpg_sel_8852b(
struct rf_info *rf,
enum rf_path path,
u8 kidx)
{
struct halrf_dpk_info *dpk = &rf->dpk;
if (dpk->bp[path][kidx].bw == CHANNEL_WIDTH_80)
halrf_wreg(rf, 0x806c, BIT(2) | BIT (1), 0x0);
else if (dpk->bp[path][kidx].bw == CHANNEL_WIDTH_40)
halrf_wreg(rf, 0x806c, BIT(2) | BIT (1), 0x2);
else
halrf_wreg(rf, 0x806c, BIT(2) | BIT (1), 0x1);
RF_DBG(rf, DBG_RF_DPK, "[DPK] TPG Select for %s\n",
dpk->bp[path][kidx].bw == CHANNEL_WIDTH_80 ? "80M" :
(dpk->bp[path][kidx].bw == CHANNEL_WIDTH_40 ? "40M" : "20M"));
}
void _dpk_kip_pwr_clk_on_8852b(
struct rf_info *rf,
enum rf_path path)
{
/*cip power on*/
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080);
/*320M*/
halrf_wreg(rf, 0x8088, MASKDWORD, 0x807f030a);
halrf_wreg(rf, 0x8120 + (path << 8), MASKDWORD, 0xce000a08);
//RF_DBG(rf, DBG_RF_DPK, "[DPK] KIP Power/CLK on\n");
}
void _dpk_kip_preset_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx)
{
_dpk_tpg_sel_8852b(rf, path, kidx);
_dpk_one_shot_8852b(rf, phy, path, KIP_PRESET);
}
void _dpk_kip_restore_8852b(
struct rf_info *rf,
enum rf_path path)
{
/*cip power on*/
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000);
/*CFIR CLK restore*/
halrf_wreg(rf, 0x8088, MASKDWORD, 0x80000000);
/*clk/en/misc*/
//halrf_wreg(rf, 0x808c, MASKDWORD, 0x00000000);
//halrf_wreg(rf, 0x8120 + (path << 8), MASKDWORD, 0x10010000);
if (rf->hal_com->cv > 0x0) /*hw txagc_offset*/
halrf_wreg(rf, 0x81c8 + (path << 8), BIT(15), 0x1);
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d restore KIP\n", path);
}
void _dpk_kip_set_txagc_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 txagc)
{
halrf_wrf(rf, path, 0x10001, MASKRF, txagc);
halrf_wreg(rf, 0x5864, BIT(29), 0x1);
_dpk_one_shot_8852b(rf, phy, path, DPK_TXAGC);
halrf_wreg(rf, 0x5864, BIT(29), 0x0);
RF_DBG(rf, DBG_RF_DPK, "[DPK] set TXAGC = 0x%x\n", txagc);
}
void _dpk_kip_set_rxagc_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path)
{
halrf_wreg(rf, 0x8078, 0x000FFFFF, halrf_rrf(rf, path, 0x00, MASKRF)); /*copy ARFC 0x00*/
halrf_wreg(rf, 0x5864, BIT(29), 0x1); /*enable kip control RFC*/
_dpk_one_shot_8852b(rf, phy, path, DPK_RXAGC);
halrf_wreg(rf, 0x5864, BIT(29), 0x0); /*disable kip control RFC*/
#if 1
halrf_wreg(rf, 0x80d4, 0x000F0000, 0x8);
RF_DBG(rf, DBG_RF_DPK, "[DPK] set RXBB = 0x%x (RF0x0[9:5] = 0x%x)\n",
halrf_rreg(rf, 0x80fc, 0x0000001F),
halrf_rrf(rf, path, 0x00, MASKRFRXBB));
#endif
}
void _dpk_read_rxsram_8852b(
struct rf_info *rf)
{
u32 addr;
halrf_wreg(rf, 0x80e8, BIT(7), 0x1); /*web_iqrx*/
halrf_wreg(rf, 0x8074, BIT(31), 0x1); /*rxsram_ctrl_sel*/
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00020000); /*rpt_sel*/
for (addr = 0; addr < 0x200; addr++) {
halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000 | addr);
RF_DBG(rf, DBG_RF_DPK, "[DPK] RXSRAM[%03d] = 0x%x\n", addr,
halrf_rreg(rf, 0x80fc, MASKDWORD));
}
halrf_wreg(rf, 0x80e8, BIT(7), 0x0); /*web_iqrx*/
halrf_wreg(rf, 0x8074, BIT(31), 0x0); /*rxsram_ctrl_sel*/
}
void _dpk_lbk_rxiqk_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path)
{
u8 i, cur_rxbb;
cur_rxbb = (u8)halrf_rrf(rf, path, 0x00, MASKRFRXBB);
halrf_wreg(rf, 0x8074, BIT(31), 0x1); /*RxSRAM_ctrl_sel 0:MDPK; 1:IQK*/
halrf_wreg(rf, 0x8124 + (path << 8), 0x0000000F, 0x0); /*[3:0] disable all rx_cfir_en*/
/*RF setting*/
halrf_wrf(rf, path, 0x1f, MASKRF, halrf_rrf(rf, path, 0x18, MASKRF));
halrf_wrf(rf, path, 0x00, MASKRFMODE, 0xd);
halrf_wrf(rf, path, 0x20, BIT(5), 0x1); /*IQKPLL_EN_BCN_A*/
if (cur_rxbb >= 0x11)
halrf_wrf(rf, path, 0x98, 0x0000007F, 0x13); /*[6:0] DPK_RXIQK Att*/
else if (cur_rxbb <= 0xa)
halrf_wrf(rf, path, 0x98, 0x0000007F, 0x00); /*[6:0] DPK_RXIQK Att*/
else
halrf_wrf(rf, path, 0x98, 0x0000007F, 0x05); /*[6:0] DPK_RXIQK Att*/
halrf_wrf(rf, path, 0x85, BIT(1) | BIT(0), 0x0); /*lower LNA LDO out*/
halrf_wrf(rf, path, 0x1e, BIT(19), 0x0);
halrf_wrf(rf, path, 0x1e, MASKRF, 0x80014); /*POW IQKPLL, 9.25MHz offset for IQKPLL*/
for (i = 0; i < 7; i++)
halrf_delay_us(rf, 10); /*IQKPLL's settling time*/
halrf_wreg(rf, 0x5864, BIT(29), 0x1);
halrf_wreg(rf, 0x802c, 0x0FFF0000, 0x025); /*[27:16] Rx_tone_idx=0x025 (9.25MHz)*/
_dpk_one_shot_8852b(rf, phy, path, LBK_RXIQK);
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, halrf_rreg(rf, 0x813c, MASKDWORD));
halrf_wreg(rf, 0x5864, BIT(29), 0x0);
halrf_wrf(rf, path, 0x20, BIT(5), 0x0); /*disable RXIQK PLL*/
//halrf_wrf(rf, path, 0x1e, BIT(19), 0x0); /*POW IQKPLL*/
halrf_wreg(rf, 0x8074, BIT(31), 0x0); /*RxSRAM_ctrl_sel 0:MDPK; 1:IQK*/
halrf_wreg(rf, 0x80d0, BIT(21) | BIT(20), 0x0);
halrf_wreg(rf, 0x81dc + (path << 8), BIT(1), 0x1); /*auto*/
halrf_wrf(rf, path, 0x00, MASKRFMODE, 0x5);
}
void _dpk_get_thermal_8852b(struct rf_info *rf, u8 kidx, enum rf_path path)
{
struct halrf_dpk_info *dpk = &rf->dpk;
//halrf_wreg(rf, 0x80d4, 0x003F0000, 0x32);
//RF_DBG(rf, DBG_RF_DPK, "[DPK] thermal@DPK (by KIP)= 0x%x\n", halrf_rreg(rf, 0x80fc, 0x0000003F));
dpk->bp[path][kidx].ther_dpk = halrf_get_thermal_8852b(rf, path);
RF_DBG(rf, DBG_RF_DPK, "[DPK] thermal@DPK (by RFC)= 0x%x\n", dpk->bp[path][kidx].ther_dpk);
}
void _dpk_tx_mapping_8852b(
struct rf_info *rf,
enum rf_path path,
u8 kidx,
u8 txagc)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u16 table_g[18] = {0xa043, 0xb043, 0xc043, 0xd043, 0xe043,
0xf043, 0xa053, 0xb053, 0xc053, 0xd053,
0xe053, 0xf053, 0x9063, 0xa063, 0xb063,
0xc063, 0xd063, 0xe063};
u16 table_a[18] = {0xd033, 0xe033, 0xf033, 0x3043, 0x4043,
0x5043, 0x4053, 0x5053, 0x6053, 0x3063,
0x4063, 0x5063, 0x6063, 0x7063, 0x8063,
0x9063, 0xa063, 0xb063};
u16 tx_gain = 0;
if (dpk->bp[path][kidx].band == BAND_ON_24G)
tx_gain = table_g[txagc - 0x2e];
if (dpk->bp[path][kidx].band == BAND_ON_5G)
tx_gain = table_a[txagc - 0x2e];
halrf_wrf(rf, path, 0x11, MASKRF, tx_gain);
}
void _dpk_rf_setting_8852b(
struct rf_info *rf,
u8 gain,
enum rf_path path,
u8 kidx)
{
struct halrf_dpk_info *dpk = &rf->dpk;
if (dpk->bp[path][kidx].band == BAND_ON_24G) { /*2G*/
halrf_wrf(rf, path, 0x00, MASKRF, 0x50220);
/*att*/
halrf_wrf(rf, path, 0x83, 0x000FF, 0xf2);
/*TIA*/
halrf_wrf(rf, path, 0xdf, BIT(12), 0x1);
halrf_wrf(rf, path, 0x9e, BIT(8), 0x1);
} else { /*5G*/
halrf_wrf(rf, path, 0x00, MASKRF, 0x50220);
/*switch + att*/
halrf_wrf(rf, path, 0x8c, 0x0FE00, 0x5); /*[15:9]*/
/*TIA*/
halrf_wrf(rf, path, 0xdf, BIT(12), 0x1);
halrf_wrf(rf, path, 0x9e, BIT(8), 0x1);
/*RXCIM3*/
halrf_wrf(rf, path, 0x8b, MASKRF, 0x920FC);
halrf_wrf(rf, path, 0x90, MASKRF, 0x002C0);
halrf_wrf(rf, path, 0x97, MASKRF, 0x38800);
}
/*debug rtxbw*/
halrf_wrf(rf, path, 0xde, BIT(2), 0x1);
/*txbb filter*/
halrf_wrf(rf, path, 0x1a, BIT(14) | BIT(13) | BIT(12), dpk->bp[path][kidx].bw + 1);
/*rxbb filter*/
halrf_wrf(rf, path, 0x1a, BIT(11) | BIT(10), 0x0);
RF_DBG(rf, DBG_RF_DPK, "[DPK] ARF 0x0/0x11/0x1a = 0x%x/ 0x%x/ 0x%x\n",
halrf_rrf(rf, path, 0x00, MASKRF),
halrf_rrf(rf, path, 0x11, MASKRF),
halrf_rrf(rf, path, 0x1a, MASKRF));
}
void _dpk_manual_txcfir_8852b(
struct rf_info *rf,
enum rf_path path,
bool is_manual)
{
u8 tmp_pad, tmp_txbb;
if (is_manual) {
halrf_wreg(rf, 0x8140 + (path << 8), BIT(8), 0x1);
/*set pad to pad_man*/
tmp_pad = (u8)halrf_rrf(rf, path, 0x56, 0x003e0); /*[9:5]*/
halrf_wreg(rf, 0x8144 + (path << 8), 0x0001f, tmp_pad); /*[4:0]*/
/*set txbb to txbb_man*/
tmp_txbb = (u8)halrf_rrf(rf, path, 0x56, 0x0001f); /*[4:0]*/
halrf_wreg(rf, 0x8144 + (path << 8), 0x01f00, tmp_txbb); /*[12:8]*/
/*cfir load shot*/
halrf_wreg(rf, 0x81dc + (path << 8), BIT(1) | BIT(0), 0x1);
halrf_wreg(rf, 0x81dc + (path << 8), BIT(1) | BIT(0), 0x0);
halrf_wreg(rf, 0x81dc + (path << 8), BIT(1), 0x1); /*auto*/
RF_DBG(rf, DBG_RF_DPK, "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n",
tmp_pad, tmp_txbb);
} else {
halrf_wreg(rf, 0x8140 + (path << 8), BIT(8), 0x0);
RF_DBG(rf, DBG_RF_DPK, "[DPK] disable manual switch TXCFIR\n");
}
}
void _dpk_bypass_rxcfir_8852b(
struct rf_info *rf,
enum rf_path path,
bool is_bypass)
{
if (is_bypass) {
halrf_wreg(rf, 0x813c + (path << 8), BIT(2), 0x1);
halrf_wreg(rf, 0x813c + (path << 8), BIT(0), 0x1);
//halrf_wreg(rf, 0x813c + (path << 8), MASKDWORD, 0x00004002);
RF_DBG(rf, DBG_RF_DPK, "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n",
1 + path, halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD));
} else {
halrf_wreg(rf, 0x813c + (path << 8), BIT(2), 0x0);
halrf_wreg(rf, 0x813c + (path << 8), BIT(0), 0x0);
RF_DBG(rf, DBG_RF_DPK, "[DPK] restore 0x8%d3c = 0x%x\n",
1 + path, halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD));
}
}
void _dpk_table_select_8852b(
struct rf_info *rf,
enum rf_path path,
u8 kidx,
u8 gain)
{
u8 val;
val = 0x80 + kidx * 0x20 + gain * 0x10;
halrf_wreg(rf, 0x81ac + (path << 8), MASKBYTE3, val);
RF_DBG(rf, DBG_RF_DPK, "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n",
kidx, gain, val);
}
bool _dpk_sync_check_8852b(
struct rf_info *rf,
enum rf_path path,
u8 kidx)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u16 dc_i, dc_q;
u8 corr_val, corr_idx;
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x0); /*rpt_sel*/
corr_idx = (u8)halrf_rreg(rf, 0x80fc, 0x000000ff);
corr_val = (u8)halrf_rreg(rf, 0x80fc, 0x0000ff00);
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d Corr_idx / Corr_val = %d / %d\n",
path, corr_idx, corr_val);
dpk->corr_idx[path][kidx] = corr_idx;
dpk->corr_val[path][kidx] = corr_val;
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x9); /*rpt_sel*/
dc_i = (u16)halrf_rreg(rf, 0x80fc, 0x0fff0000); /*[27:16]*/
dc_q = (u16)halrf_rreg(rf, 0x80fc, 0x00000fff); /*[11:0]*/
if (dc_i >> 11 == 1)
dc_i = 0x1000 - dc_i;
if (dc_q >> 11 == 1)
dc_q = 0x1000 - dc_q;
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d DC I/Q, = %d / %d\n", path, dc_i, dc_q);
dpk->dc_i[path][kidx] = dc_i;
dpk->dc_q[path][kidx] = dc_q;
if ((dc_i > 200) || (dc_q > 200) || (corr_val < 170))
return true;
else
return false;
}
bool _dpk_sync_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx)
{
_dpk_one_shot_8852b(rf, phy, path, SYNC);
return _dpk_sync_check_8852b(rf, path, kidx); /*1= fail*/
}
u16 _dpk_dgain_read_8852b(
struct rf_info *rf)
{
u16 dgain = 0x0;
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x0); /*rpt_sel*/
dgain = (u16)halrf_rreg(rf, 0x80fc, 0x0FFF0000); /*[27:16]*/
RF_DBG(rf, DBG_RF_DPK, "[DPK] DGain = 0x%x\n", dgain);
return dgain;
}
s8 _dpk_dgain_mapping_8852b(
struct rf_info *rf,
u16 dgain)
{
u16 bnd[15] = {0xbf1, 0xaa5, 0x97d, 0x875, 0x789,
0x6b7, 0x5fc, 0x556, 0x4c1, 0x43d,
0x3c7, 0x35e, 0x2ac, 0x262, 0x220};
s8 offset = 0;
if (dgain >= bnd[0])
offset = 0x6;
else if ((bnd[0] > dgain) && (dgain >= bnd[1]))
offset = 0x6;
else if ((bnd[1] > dgain) && (dgain >= bnd[2]))
offset = 0x5;
else if ((bnd[2] > dgain) && (dgain >= bnd[3]))
offset = 0x4;
else if ((bnd[3] > dgain) && (dgain >= bnd[4]))
offset = 0x3;
else if ((bnd[4] > dgain) && (dgain >= bnd[5]))
offset = 0x2;
else if ((bnd[5] > dgain) && (dgain >= bnd[6]))
offset = 0x1;
else if ((bnd[6] > dgain) && (dgain >= bnd[7]))
offset = 0x0;
else if ((bnd[7] > dgain) && (dgain >= bnd[8]))
offset = 0xff;
else if ((bnd[8] > dgain) && (dgain >= bnd[9]))
offset = 0xfe;
else if ((bnd[9] > dgain) && (dgain >= bnd[10]))
offset = 0xfd;
else if ((bnd[10] > dgain) && (dgain >= bnd[11]))
offset = 0xfc;
else if ((bnd[11] > dgain) && (dgain >= bnd[12]))
offset = 0xfb;
else if ((bnd[12] > dgain) && (dgain >= bnd[13]))
offset = 0xfa;
else if ((bnd[13] > dgain) && (dgain >= bnd[14]))
offset = 0xf9;
else if (bnd[14] > dgain)
offset = 0xf8;
else
offset = 0x0;
//RF_DBG(rf, DBG_RF_DPK, "[DPK] DGain offset = %d\n", offset);
return offset;
}
u8 _dpk_pas_check_8852b(
struct rf_info *rf)
{
u8 fail = 0;
halrf_wreg(rf, 0x80d4, MASKBYTE2, 0x06); /*0x80d6, ctrl_out_Kpack*/
halrf_wreg(rf, 0x80bc, BIT(14), 0x0); /*query status*/
halrf_wreg(rf, 0x80c0, MASKBYTE2, 0x08);
halrf_wreg(rf, 0x80c0, MASKBYTE3, 0x00); /*0x80C3*/
if (halrf_rreg(rf, 0x80fc, MASKHWORD) == 0x0800) {
fail = 1;
RF_DBG(rf, DBG_RF_DPK, "[DPK] PAS check Fail!!\n");
}
return fail;
}
u8 _dpk_gainloss_read_8852b(
struct rf_info *rf)
{
u8 result;
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x6); /*rpt_sel*/
halrf_wreg(rf, 0x80bc, BIT(14), 0x1); /*query status*/
result = (u8)halrf_rreg(rf, 0x80fc, 0x000000F0); /*[7:4]*/
RF_DBG(rf, DBG_RF_DPK, "[DPK] tmp GL = %d\n", result);
return result;
}
void _dpk_gainloss_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx)
{
//_dpk_table_select_8852b(rf, path, kidx, 1);
_dpk_one_shot_8852b(rf, phy, path, GAIN_LOSS);
}
u8 _dpk_set_offset_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
s8 gain_offset)
{
u8 txagc;
txagc = (u8)halrf_rrf(rf, path, 0x10001, MASKRF);
if (txagc - gain_offset < 0x2e)
txagc = 0x2e;
else if (txagc - gain_offset > 0x3f)
txagc = 0x3f;
else
txagc = txagc - gain_offset;
_dpk_kip_set_txagc_8852b(rf, phy, path, txagc);
RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust TxAGC (offset %d) = 0x%x\n", gain_offset, txagc);
return txagc;
}
u8 _dpk_pas_read_8852b(
struct rf_info *rf,
u8 is_check)
{
u8 i;
u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
halrf_wreg(rf, 0x80d4, MASKBYTE2, 0x06); /*0x80d6, ctrl_out_Kpack*/
halrf_wreg(rf, 0x80bc, BIT(14), 0x0); /*query status*/
halrf_wreg(rf, 0x80c0, MASKBYTE2, 0x08);
if (is_check) {
halrf_wreg(rf, 0x80c0, MASKBYTE3, 0x00);
val1_i = halrf_rreg(rf, 0x80fc, MASKHWORD);
if (val1_i >= 0x800)
val1_i = 0x1000 - val1_i;
val1_q = halrf_rreg(rf, 0x80fc, MASKLWORD);
if (val1_q >= 0x800)
val1_q = 0x1000 - val1_q;
halrf_wreg(rf, 0x80c0, MASKBYTE3, 0x1f);
val2_i = halrf_rreg(rf, 0x80fc, MASKHWORD);
if (val2_i >= 0x800)
val2_i = 0x1000 - val2_i;
val2_q = halrf_rreg(rf, 0x80fc, MASKLWORD);
if (val2_q >= 0x800)
val2_q = 0x1000 - val2_q;
RF_DBG(rf, DBG_RF_DPK, "[DPK] PAS_delta = 0x%x\n",
(val1_i * val1_i + val1_q * val1_q) /
(val2_i * val2_i + val2_q * val2_q));
} else {
for (i = 0; i < 32; i++) {
halrf_wreg(rf, 0x80c0, MASKBYTE3, i); /*0x80C3*/
RF_DBG(rf, DBG_RF_DPK, "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
halrf_rreg(rf, 0x80fc, MASKDWORD));
}
}
if ((val1_i * val1_i + val1_q * val1_q) >= ((val2_i * val2_i + val2_q * val2_q) * 8 / 5))
return 1;
else
return 0;
}
u8 _dpk_agc_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx,
u8 init_txagc,
u8 loss_only)
{
u8 tmp_txagc, tmp_rxbb = 0, i = 0, tmp_gl_idx = 0;
u8 goout = 0, agc_cnt = 0, limited_rxbb = 0;
s8 offset = 0;
u16 dgain = 0;
tmp_txagc = init_txagc;
do {
switch (i) {
case 0: /*SYNC and Dgain*/
if (_dpk_sync_8852b(rf, phy, path, kidx) == true) {
tmp_txagc = 0xff;
goout = 1;
break;
}
dgain = _dpk_dgain_read_8852b(rf);
if (loss_only == 1 || limited_rxbb == 1)
i = 2;
else
i = 1;
break;
case 1: /*Gain adjustment*/
tmp_rxbb = (u8)halrf_rrf(rf, path, 0x00, MASKRFRXBB);
offset = _dpk_dgain_mapping_8852b(rf, dgain);
if (tmp_rxbb + offset > 0x1f) {
tmp_rxbb = 0x1f;
limited_rxbb = 1;
} else if (tmp_rxbb + offset < 0) {
tmp_rxbb = 0;
limited_rxbb = 1;
} else
tmp_rxbb = tmp_rxbb + offset;
halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb);
RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, tmp_rxbb);
#if 1
if (offset != 0 || agc_cnt == 0) {
if (rf->hal_com->band[phy].cur_chandef.bw < 2)
_dpk_bypass_rxcfir_8852b(rf, path, true);
else
_dpk_lbk_rxiqk_8852b(rf, phy, path);
}
#endif
if ((dgain > 1922) || (dgain < 342))
i = 0;
else
i = 2;
agc_cnt++;
break;
case 2: /*GAIN_LOSS and idx*/
_dpk_gainloss_8852b(rf, phy, path, kidx);
tmp_gl_idx = _dpk_gainloss_read_8852b(rf);
/*_dpk_pas_read_8852a(rf, false);*/
if ((tmp_gl_idx == 0 && _dpk_pas_read_8852b(rf, true) == 1) || tmp_gl_idx >= 7)
i = 3; /*GL > criterion*/
else if (tmp_gl_idx == 0)
i = 4; /*GL < criterion*/
else
i = 5;
break;
case 3: /*GL > criterion*/
if (tmp_txagc == 0x2e) {
goout = 1;
RF_DBG(rf, DBG_RF_DPK, "[DPK] Txagc@lower bound!!\n");
} else {
tmp_txagc = _dpk_set_offset_8852b(rf, phy, path, 0x3); /*tx gain -3*/
#if 0
if (0x1f - tmp_rxbb > 2)
tmp_rxbb = tmp_rxbb + 2;
else
tmp_rxbb = 0x1f;
halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb);
RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust RXBB = 0x%x\n", tmp_rxbb);
#endif
}
i = 2;
agc_cnt++;
break;
case 4: /*GL < criterion*/
if (tmp_txagc == 0x3f) {
goout = 1;
RF_DBG(rf, DBG_RF_DPK, "[DPK] Txagc@upper bound!!\n");
} else {
tmp_txagc = _dpk_set_offset_8852b(rf, phy, path, 0xfe); /*tx gain +2*/
#if 0
if (tmp_rxbb - 2 > 0)
tmp_rxbb = tmp_rxbb - 2;
else
tmp_rxbb = 0x0;
halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb);
RF_DBG(rf, DBG_RF_DPK, "[DPK] Adjust RXBB = 0x%x\n", tmp_rxbb);
#endif
}
i = 2;
agc_cnt++;
break;
case 5: /*set tx gain for DPK*/
tmp_txagc =_dpk_set_offset_8852b(rf, phy, path, tmp_gl_idx);
#if 0
if (tmp_rxbb + tmp_gl_idx >= 0x1f)
tmp_rxbb = 0x1f;
else
tmp_rxbb = tmp_rxbb + tmp_gl_idx;
halrf_wrf(rf, path, 0x00, MASKRFRXBB, tmp_rxbb);
#endif
goout = 1;
agc_cnt++;
break;
default:
goout = 1;
break;
}
} while (!goout && (agc_cnt < 6));
RF_DBG(rf, DBG_RF_DPK, "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n",
tmp_txagc, tmp_rxbb);
return tmp_txagc;
}
void _dpk_set_mdpd_para_8852b(
struct rf_info *rf,
u8 order)
{
switch (order) {
case 0: /*(5,3,1)*/
halrf_wreg(rf, 0x80a0, BIT(1) | BIT(0), order);
halrf_wreg(rf, 0x80a0, 0x00001F00, 0x3); /*[12:8] phase normalize tap*/
halrf_wreg(rf, 0x8070, 0xF0000000, 0x1); /*[31:28] tx_delay_man*/
break;
case 1: /*(5,3,0)*/
halrf_wreg(rf, 0x80a0, BIT(1) | BIT(0), order);
halrf_wreg(rf, 0x80a0, 0x00001F00, 0x0); /*[12:8] phase normalize tap*/
halrf_wreg(rf, 0x8070, 0xF0000000, 0x0); /*[31:28] tx_delay_man*/
break;
case 2: /*(5,0,0)*/
halrf_wreg(rf, 0x80a0, BIT(1) | BIT(0), order);
halrf_wreg(rf, 0x80a0, 0x00001F00, 0x0); /*[12:8] phase normalize tap*/
halrf_wreg(rf, 0x8070, 0xF0000000, 0x0); /*[31:28] tx_delay_man*/
break;
default:
RF_DBG(rf, DBG_RF_DPK, "[DPK] Wrong MDPD order!!(0x%x)\n", order);
break;
}
RF_DBG(rf, DBG_RF_DPK, "[DPK] Set %s for IDL\n", order == 0x0 ? "(5,3,1)" :
(order == 0x1 ? "(5,3,0)" : "(5,0,0)"));
}
void _dpk_idl_mpa_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx,
u8 gain)
{
struct halrf_dpk_info *dpk = &rf->dpk;
/*IDL*/
if (dpk->bp[path][kidx].bw < CHANNEL_WIDTH_80 &&
dpk->bp[path][kidx].band == BAND_ON_5G)
_dpk_set_mdpd_para_8852b(rf, 0x2); /*5,0,0*/
else
_dpk_set_mdpd_para_8852b(rf, 0x0); /*5,3,1*/
//_dpk_table_select_8852b(rf, path, kidx, 1);
_dpk_one_shot_8852b(rf, phy, path, MDPK_IDL);
}
u8 _dpk_order_convert_8852b(
struct rf_info *rf)
{
u8 val;
val = 0x3 >> (u8)halrf_rreg(rf, 0x80a0, 0x00000003);
/*0x80a0 [1:0] = 0x0 => 0x81bc[26:25] = 0x3 //(5,3,1)*/
/*0x80a0 [1:0] = 0x1 => 0x81bc[26:25] = 0x1 //(5,3,0)*/
/*0x80a0 [1:0] = 0x2 => 0x81bc[26:25] = 0x0 //(5,0,0)*/
/*0x80a0->val : 0->3; 1->1; 2->0*/
RF_DBG(rf, DBG_RF_DPK, "[DPK] convert MDPD order to 0x%x\n", val);
return val;
}
u8 _dpk_pwsf_addr_cal_8852b(
struct rf_info *rf,
u8 t1,
u8 t2)
{
u8 addr;
s8 offset;
/*w/o TSSI : t2 = cur_thermal*/
offset = t2 - t1;
addr = 0x78 + (offset << 3); /*due to TPG -3dB, start from 0x78*/
return addr;
}
void _dpk_gs_normalize_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx,
u8 txagc,
u8 gs_ori,
u16 pwsf)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u8 gs;
u16 sqrt_out;
if (dpk->bp[path][kidx].bw == 2) /*80M*/
halrf_wreg(rf, 0x819c + (path << 8), MASKDWORD, 0x000300c0);
else
halrf_wreg(rf, 0x819c + (path << 8), MASKDWORD, 0x00030200);
halrf_wreg(rf, 0x81c8 + (path << 8), 0x0000003F, txagc); /*man_txagc_vall*/
halrf_wreg(rf, 0x81c8 + (path << 8), BIT(6), 0x1); /*man_txagc_en*/
halrf_wreg(rf, 0x81c8 + (path << 8), MASKBYTE2, 0x08); /*man_pwsf_en*/
halrf_wreg(rf, 0x81c8 + (path << 8), MASKBYTE1, pwsf - 24); /*man_pwsf_val*/
_dpk_one_shot_8852b(rf, phy, path, GAIN_CAL);
halrf_wreg(rf, 0x81d4, 0x003F0000, 0x13); /*rpt_sel = pow_diff */
sqrt_out = (u16)halrf_rreg(rf, 0x81fc, 0x000001FF); /*[8:0]*/
gs = (u8)(gs_ori * sqrt_out >> 8);
/*ch0/gain0 [6:0]*/
halrf_wreg(rf, 0x81bc + (path << 8), 0x0000007F, gs);
/*ch0/gain1 [14:8]*/
halrf_wreg(rf, 0x81bc + (path << 8), 0x00007F00, gs);
/*ch1/gain0 [6:0]*/
//halrf_wreg(rf, 0x81c0 + (path << 8), 0x0000007F, gs);
/*ch1/gain1 [14:8]*/
//halrf_wreg(rf, 0x81c0 + (path << 8), 0x00007F00, gs);
RF_DBG(rf, DBG_RF_DPK, "[DPK] gs_ori/ sqrt_out/ gs_new = 0x%x/ %d/ 0x%x\n",
gs_ori, sqrt_out, gs);
}
void _dpk_fill_result_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 kidx,
u8 gain,
u8 txagc)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u16 pwsf = 0x78;
u8 gs = dpk->dpk_gs[phy];
halrf_wreg(rf, 0x8104 + (path << 8), BIT(8), kidx);
/*read agc*/
//txagc = (u8)(halrf_rrf(rf, path, 0x01, MASKTXPWR) + gain_offset); /*U(6.0)*/
/*cal pwsf*/
//pwsf = _dpk_pwsf_addr_cal_8852b(rf, 0, 0);
#if 0
/*read gs and normalize*/
gs = (u8)halrf_rreg(rf, 0x81bc + path * PATH_OFST_8852B + ch * CH_OFST_8852B,
0x7F << (gain * 8));
gs = _dpk_gs_normalize_8852b(rf, gs, path);
#endif
RF_DBG(rf, DBG_RF_DPK, "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n",
txagc, pwsf, gs);
/*========== txagc_rf ==========*/
dpk->bp[path][kidx].txagc_dpk = txagc;
halrf_wreg(rf, 0x81c4 + (path << 8), 0x3F << ((gain << 3) + (kidx << 4)), txagc);
/*ch0/gain0 [5:0]*/
//halrf_wreg(rf, 0x81c4 + (path << 8), 0x0000003F, txagc); /*txagc_rf*/
//halrf_wreg(rf, 0x8190 + (path << 8), 0x000001F8, txagc); /*txagc_orig*/
/*ch0/gain1 [13:8]*/
//halrf_wreg(rf, 0x81c4 + (path << 8), 0x00003F00, txagc); /*txagc_rf*/
//halrf_wreg(rf, 0x8190 + (path << 8), 0x01F80000, txagc); /*txagc_orig*/
/*ch1/gain0 [21:16]*/
//halrf_wreg(rf, 0x81c4 + (path << 8), 0x003F0000, txagc);
/*ch1/gain1 [29:24]*/
//halrf_wreg(rf, 0x81c4 + (path << 8), 0x3F000000, txagc);
/*========== txagc_bb ==========*/
/*ch0/gain0 [9:0]*/
//halrf_wreg(rf, 0x81a4 + (path << 8), 0x000003FF, txagc_bb);
/*ch0/gain1 [25:16]*/
//halrf_wreg(rf, 0x81a4 + (path << 8), 0x03FF0000, bb_gain);
/*ch1/gain0 [9:0]*/
//halrf_wreg(rf, 0x81a8 + (path << 8), 0x000003FF, txagc_bb);
/*ch1/gain1 [25:16]*/
//halrf_wreg(rf, 0x81a8 + (path << 8), 0x03FF0000, txagc_bb);
/*========== pwsf ==========*/
dpk->bp[path][kidx].pwsf = pwsf;
halrf_wreg(rf, 0x81b4 + (path << 8) + (kidx << 2), 0x1FF << (gain << 4), pwsf);
/*ch0/gain0 [8:0]*/
//halrf_wreg(rf, 0x81b4 + (path << 8), 0x000001FF, pwsf);
/*ch0/gain1 [24:16]*/
//halrf_wreg(rf, 0x81b4 + (path << 8), 0x01FF0000, pwsf);
/*ch1/gain0 [8:0]*/
//halrf_wreg(rf, 0x81b8 + (path << 8), 0x000001FF, pwsf);
/*ch1/gain1 [24:16]*/
//halrf_wreg(rf, 0x81b8 + (path << 8), 0x01FF0000, pwsf);
/*========== road shot MDPD==========*/
halrf_wreg(rf, 0x81dc + (path << 8), BIT(16), 0x1);
halrf_wreg(rf, 0x81dc + (path << 8), BIT(16), 0x0);
//halrf_wreg(rf, 0x81bc + (path << 8), MASKDWORD, 0x075b5b5b);
/*========== gs & MDPD order ==========*/
dpk->bp[path][kidx].gs = gs;
if (dpk->dpk_gs[phy] == 0x7f)
halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), MASKDWORD, 0x007f7f7f);
else
halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), MASKDWORD, 0x005b5b5b);
halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), BIT(26) | BIT(25), _dpk_order_convert_8852b(rf));
/*order [26:25]*/
/*ch0*/
//halrf_wreg(rf, 0x81bc + (path << 8), 0x06000000, _dpk_order_convert_8852b(rf));
/*ch1*/
//halrf_wreg(rf, 0x81c0 + (path << 8), 0x06000000, _dpk_order_convert_8852b(rf));
//halrf_wreg(rf, 0x81bc + (path << 8), 0x007F0000, 0x5b); /*gs2 set to -3dB*/
/*ch0/gain0 [6:0]*/
//halrf_wreg(rf, 0x81bc + (path << 8), 0x0000007F, gs);
/*ch0/gain1 [14:8]*/
//halrf_wreg(rf, 0x81bc + (path << 8), 0x00007F00, gs);
/*ch1/gain0 [6:0]*/
//halrf_wreg(rf, 0x81c0 + (path << 8), 0x0000007F, gs);
/*ch1/gain1 [14:8]*/
//halrf_wreg(rf, 0x81c0 + (path << 8), 0x00007F00, gs);
/*========== mdpd_en ==========*/
/*ch0*/
//halrf_wreg(rf, 0x81bc + (path << 8), BIT(24), 0x1);
/*ch1*/
//halrf_wreg(rf, 0x81c0 + (path << 8), BIT(24), 0x1);
/*========== release all setting for K==========*/
//halrf_wreg(rf, 0x81c8, MASKDWORD, 0x0);
halrf_wreg(rf, 0x81a0 + (path << 8), MASKDWORD, 0x0);
halrf_wreg(rf, 0x8070, 0x80000000, 0x0); /*BIT(31)*/
//_dpk_gs_normalize_8852b(rf, path, txagc, gs, pwsf);
}
void _dpk_coef_read_8852b(
struct rf_info *rf,
enum rf_path path,
u8 kidx,
u8 gain)
{
u32 reg, reg_start, reg_stop;
halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00010000);
reg_start = 0x9500 + kidx * 0xa0 + path * 0x200 + gain * 0x50;
reg_stop = reg_start + 0x50;
RF_DBG(rf, DBG_RF_DPK, "[DPK] ===== [Coef of S%d[%d], gain%d] =====\n",
path, kidx, gain);
for (reg = reg_start; reg < reg_stop ; reg += 4) {
RF_DBG(rf, DBG_RF_DPK, "[DPK][coef_r] 0x%x = 0x%08x\n", reg,
halrf_rreg(rf, reg, MASKDWORD));
}
halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00000000);
}
bool _dpk_reload_check_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path)
{
struct halrf_dpk_info *dpk = &rf->dpk;
bool is_reload = false;
u8 idx, cur_band, cur_ch;
cur_band = rf->hal_com->band[phy].cur_chandef.band;
cur_ch = rf->hal_com->band[phy].cur_chandef.center_ch;
for (idx = 0; idx < DPK_BKUP_NUM; idx++) {
if ((cur_band == dpk->bp[path][idx].band) && (cur_ch == dpk->bp[path][idx].ch)) {
halrf_wreg(rf, 0x8104 + (path << 8), BIT(8), idx);
dpk->cur_idx[path] = idx;
is_reload = true;
RF_DBG(rf, DBG_RF_DPK, "[DPK] reload S%d[%d] success\n", path, idx);
}
}
return is_reload;
}
bool _dpk_main_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
enum rf_path path,
u8 gain)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u8 txagc = 0x38, kidx = dpk->cur_idx[path];
bool is_fail = false;
RF_DBG(rf, DBG_RF_DPK, "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
halrf_rf_direct_cntrl_8852b(rf, path, false); /*switch control to direct write*/
halrf_drf_direct_cntrl_8852b(rf, path, false); /*switch control to direct write*/
_dpk_kip_pwr_clk_on_8852b(rf, path);
_dpk_kip_set_txagc_8852b(rf, phy, path, txagc);
_dpk_rf_setting_8852b(rf, gain, path, kidx);
halrf_set_rx_dck_8852b(rf, phy, path, false);
_dpk_kip_preset_8852b(rf, phy, path, kidx);
_dpk_kip_set_rxagc_8852b(rf, phy, path);
_dpk_table_select_8852b(rf, path, kidx, gain);
#if 0
is_fail = _dpk_sync_8852b(rf, phy, path, kidx);
if (is_fail)
goto _error;
_dpk_dgain_read_8852b(rf);
_dpk_gainloss_8852b(rf, phy, path, kidx);
//tmp_gl_idx = _dpk_gainloss_read_8852b(rf);
txagc = _dpk_set_offset_8852b(rf, phy, path, _dpk_gainloss_read_8852b(rf));
#else
txagc = _dpk_agc_8852b(rf, phy, path, kidx, txagc, false);
if (txagc == 0xff) {
is_fail = true;
goto _error;
}
#endif
/*_dpk_pas_read_8852b(rf, false);*/
_dpk_get_thermal_8852b(rf, kidx, path);
_dpk_idl_mpa_8852b(rf, phy, path, kidx, gain);
halrf_wrf(rf, path, 0x00, MASKRFMODE, RF_RX);
#if 0
_dpk_coef_read_8852b(rf, path, kidx, gain);
#endif
_dpk_fill_result_8852b(rf, phy, path, kidx, gain, txagc);
_error:
if (is_fail == false)
dpk->bp[path][kidx].path_ok = 1;
else
dpk->bp[path][kidx].path_ok = 0;
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d[%d] DPK %s\n", path, kidx, is_fail ? "Check" : "Success");
return is_fail;
}
void _dpk_cal_select_8852b(
struct rf_info *rf,
bool force,
enum phl_phy_idx phy,
u8 kpath)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u32 kip_bkup[DPK_RF_PATH_MAX_8852B][DPK_KIP_REG_NUM_8852B] = {{0}};
u32 bb_bkup[DPK_BB_REG_NUM_8852B] = {0};
u32 rf_bkup[DPK_RF_PATH_MAX_8852B][DPK_RF_REG_NUM_8852B] = {{0}};
u32 kip_reg[] = {0x813c, 0x8124, 0x8120};
u32 bb_reg[] = {0x2344, 0x5800, 0x7800};
u32 rf_reg[DPK_RF_REG_NUM_8852B] = {0xde, 0xdf, 0x8b, 0x90, 0x97,
0x85, 0x5, 0x10005};
u8 path;
bool is_fail = true, reloaded[DPK_RF_PATH_MAX_8852B] = {false};
if (rf->phl_com->drv_mode != RTW_DRV_MODE_MP && DPK_RELOAD_EN_8852B) {
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
reloaded[path] = _dpk_reload_check_8852b(rf, phy, path);
if ((reloaded[path] == false) && (dpk->bp[path][0].ch != 0))
dpk->cur_idx[path] = !dpk->cur_idx[path];
else
halrf_dpk_onoff_8852b(rf, path, false);
}
} else {
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++)
dpk->cur_idx[path] = 0;
}
_dpk_bkup_bb_8852b(rf, bb_reg, bb_bkup);
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
_dpk_bkup_kip_8852b(rf, kip_reg, kip_bkup, path);
_dpk_bkup_rf_8852b(rf, rf_reg, rf_bkup, path);
_dpk_information_8852b(rf, phy, path);
if (rf->is_tssi_mode[path])
_dpk_tssi_pause_8852b(rf, path, true);
}
_dpk_bb_afe_setting_8852b(rf, phy, path, kpath);
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
is_fail = _dpk_main_8852b(rf, phy, path, 1);
halrf_dpk_onoff_8852b(rf, path, is_fail);
}
_dpk_bb_afe_restore_8852b(rf, phy, path, kpath);
_dpk_reload_bb_8852b(rf, bb_reg, bb_bkup);
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
_dpk_kip_restore_8852b(rf, path);
_dpk_reload_kip_8852b(rf, kip_reg, kip_bkup, path);
_dpk_reload_rf_8852b(rf, rf_reg, rf_bkup, path);
if (rf->is_tssi_mode[path])
_dpk_tssi_pause_8852b(rf, path, false);
}
}
u8 _dpk_bypass_check_8852b(
struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_fem_info *fem = &rf->fem;
u8 result;
if (fem->epa_2g && (rf->hal_com->band[phy].cur_chandef.band == BAND_ON_24G)) {
RF_DBG(rf, DBG_RF_DPK, "[DPK] Skip DPK due to 2G_ext_PA exist!!\n");
result = 1;
} else if (fem->epa_5g && (rf->hal_com->band[phy].cur_chandef.band == BAND_ON_5G)) {
RF_DBG(rf, DBG_RF_DPK, "[DPK] Skip DPK due to 5G_ext_PA exist!!\n");
result = 1;
} else if (fem->epa_6g && (rf->hal_com->band[phy].cur_chandef.band == BAND_ON_6G)) {
RF_DBG(rf, DBG_RF_DPK, "[DPK] Skip DPK due to 6G_ext_PA exist!!\n");
result = 1;
} else
result = 0;
return result;
}
void _dpk_force_bypass_8852b(
struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 path, kpath;
kpath = halrf_kpath_8852b(rf, phy);
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
if (kpath & BIT(path))
halrf_dpk_onoff_8852b(rf, path, true);
}
}
void halrf_dpk_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
bool force)
{
RF_DBG(rf, DBG_RF_DPK, "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n",
DPK_VER_8852B, rf->hal_com->cv, RF_RELEASE_VERSION_8852B);
RF_DBG(rf, DBG_RF_DPK, "[DPK] Driver mode = %d\n", rf->phl_com->drv_mode);
#if 1
if (_dpk_bypass_check_8852b(rf, phy))
_dpk_force_bypass_8852b(rf, phy);
else
_dpk_cal_select_8852b(rf, force, phy, RF_AB);
#else
_dpk_information_8852b(rf, 0, RF_PATH_A);
_dpk_bb_afe_setting_8852b(rf, 0, RF_PATH_A);
//_dpk_main_8852b(rf, 0, 0, 1, RF_PATH_A);
_dpk_set_tx_pwr_8852b(rf, 1, RF_PATH_A);
_dpk_rf_setting_8852b(rf, 1, RF_PATH_A);
halrf_set_rx_dck_8852b(rf, RF_PATH_A, false);
_dpk_cip_setting_8852b(rf, RF_PATH_A);
_dpk_manual_txcfir_8852b(rf, RF_PATH_A, true);
_dpk_bypass_rxcfir_8852b(rf, RF_PATH_A, true);
//_dpk_sync_8852b(rf, RF_PATH_A);
//_dpk_dgain_read_8852b(rf);
//_dpk_gainloss_8852b(rf, RF_PATH_A);
_dpk_idl_mpa_8852b(rf, 0, 1, RF_PATH_A);
_dpk_fill_result_8852b(rf, 0, 1, RF_PATH_A, 0x36);
//halrf_dpk_onoff_8852b(rf, RF_PATH_A, 0);
//_dpk_reload_rf_8852b(rf, rf_reg, rf_bkup, kpath);
//halrf_rf_direct_cntrl_8852b(rf, RF_PATH_A, true);
//_dpk_bb_afe_restore_8852b(rf, phy, RF_PATH_A);
#endif
}
void halrf_dpk_onoff_8852b(
struct rf_info *rf,
enum rf_path path,
bool off)
{
struct halrf_dpk_info *dpk = &rf->dpk;
bool off_reverse;
u8 val, kidx = dpk->cur_idx[path];
if (off)
off_reverse = false;
else
off_reverse = true;
val = dpk->is_dpk_enable & off_reverse & dpk->bp[path][kidx].path_ok;
halrf_wreg(rf, 0x81bc + (path << 8) + (kidx << 2), MASKBYTE3,
_dpk_order_convert_8852b(rf) << 1 | val);
//halrf_wreg(rf, 0x81bc + (path << 8), BIT(24), dpk->is_dpk_enable & (!off)); /*ch0*/
//halrf_wreg(rf, 0x81c0 + (path << 8), BIT(24), dpk->is_dpk_enable & (!off)); /*ch1*/
RF_DBG(rf, DBG_RF_DPK, "[DPK] S%d[%d] DPK %s !!!\n", path, kidx,
(dpk->is_dpk_enable & off_reverse) ? "enable" : "disable");
}
void halrf_dpk_track_8852b(
struct rf_info *rf)
{
struct halrf_dpk_info *dpk = &rf->dpk;
u8 path, i, kidx;
u8 trk_idx = 0, txagc_rf = 0;
s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0;
u16 pwsf[2];
u8 cur_ther, ther_avg_cnt = 0;
u32 ther_avg[2] = {0};
s8 delta_ther[2] = {0};
for (path = 0; path < DPK_RF_PATH_MAX_8852B; path++) {
kidx = dpk->cur_idx[path];
RF_DBG(rf, DBG_RF_DPK_TRACK,
"[DPK_TRK] ================[S%d[%d] (CH %d)]================\n",
path, kidx, dpk->bp[path][kidx].ch);
//cur_ther = halrf_get_thermal_8852b(rf, path);
cur_ther = (u8)halrf_rreg(rf, 0x1c10 + (path << 13), 0x3F000000); /*[29:24]*/
RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] thermal now = %d\n", cur_ther);
dpk->ther_avg[path][dpk->ther_avg_idx] = cur_ther;
/*Average times */
ther_avg_cnt = 0;
for (i = 0; i < THERMAL_DPK_AVG_NUM; i++) {
if (dpk->ther_avg[path][i]) {
ther_avg[path] += dpk->ther_avg[path][i];
ther_avg_cnt++;
#if 0
RF_DBG(rf, DBG_RF_DPK_TRACK,
"[DPK_TRK] thermal avg[%d] = %d\n", i,
dpk->thermal_dpk_avg[path][i]);
#endif
}
}
/*Calculate Average ThermalValue after average enough times*/
if (ther_avg_cnt) {
cur_ther = (u8)(ther_avg[path] / ther_avg_cnt);
#if 0
RF_DBG(rf, DBG_RF_DPK_TRACK,
"[DPK_TRK] thermal avg total = %d, avg_cnt = %d\n",
ther_avg[path], ther_avg_cnt);
#endif
RF_DBG(rf, DBG_RF_DPK_TRACK,
"[DPK_TRK] thermal avg = %d (DPK @ %d)\n",
cur_ther, dpk->bp[path][kidx].ther_dpk);
}
if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
if (dpk->bp[path][kidx].band == 0) /*2G*/
delta_ther[path] = delta_ther[path] * 3 / 2;
else
delta_ther[path] = delta_ther[path] * 5 / 2;
txagc_rf = (u8)halrf_rreg(rf, 0x1c60 + (path << 13), 0x0000003f); /*[5:0]*/
if (rf->is_tssi_mode[path]) { /*TSSI mode*/
trk_idx = (u8)halrf_rrf(rf, path, 0x5D, 0xFC000); /*[19:14] for integer*/
RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n",
txagc_rf, trk_idx);
txagc_bb = (s8)halrf_rreg(rf, 0x1c60 + (path << 13), MASKBYTE2); /*[23:16]*/
txagc_bb_tp = (u8)halrf_rreg(rf, 0x1c04 + (path << 13), 0x00000007); /*[2:0]*/
RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
txagc_bb_tp, txagc_bb);
txagc_ofst = (s8)halrf_rreg(rf, 0x1c60 + (path << 13), MASKBYTE3); /*[31:24]*/
RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n", txagc_ofst, delta_ther[path]);
if (halrf_rreg(rf, 0x81c8 + (path << 8), BIT(15)) == 0x1) {
txagc_ofst = 0; /*hw txagc_offset*/
RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] HW txagc offset mode\n");
}
if (txagc_rf != 0 && cur_ther != 0)
ini_diff = txagc_ofst + (delta_ther[path]);
if (halrf_rreg(rf, 0x58d4 + (path << 13), 0xf0000000) == 0x0) {
pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - txagc_bb + ini_diff; /*gain0*/
pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - txagc_bb + ini_diff; /*gain1*/
} else {
pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; /*gain0*/
pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff; /*gain1*/
}
} else { /*without any tx power tracking mechanism*/
pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; /*gain0*/
pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; /*gain1*/
}
if (rf->rfk_is_processing != true && halrf_rreg(rf, 0x80f0, BIT(31)) == 0x0 && txagc_rf != 0) {
RF_DBG(rf, DBG_RF_DPK_TRACK, "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n",
pwsf[0], pwsf[1]);
halrf_wreg(rf, 0x81b4 + (path << 8) + (kidx << 2), 0x000001FF, pwsf[0]);
halrf_wreg(rf, 0x81b4 + (path << 8) + (kidx << 2), 0x01FF0000, pwsf[1]);
}
}
dpk->ther_avg_idx++;
if (dpk->ther_avg_idx == THERMAL_DPK_AVG_NUM)
dpk->ther_avg_idx = 0;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.c
|
C
|
agpl-3.0
| 45,554
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DPK_8852BH__
#define __HALRF_DPK_8852BH__
#ifdef RF_8852B_SUPPORT
/*--------------------------Define Parameters-------------------------------*/
#define DPK_VER_8852B 0x9
#define DPK_RF_PATH_MAX_8852B 2
#define DPK_KIP_REG_NUM_8852B 3
#define DPK_BB_REG_NUM_8852B 3
#define DPK_RF_REG_NUM_8852B 8
#define DPK_PATH_A_8852B 1
#define DPK_PATH_B_8852B 1
#define PATH_OFST_8852B 0x100
#define CH_OFST_8852B 0x4
#define PHY_OFST_8852B 0x80
#define DPK_BY_NCTL_8852B 1
#define DPK_RELOAD_EN_8852B 0
#define DPK_REG_DBG 0
/*---------------------------End Define Parameters----------------------------*/
void halrf_dpk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
void halrf_dpk_onoff_8852b(struct rf_info *rf, enum rf_path path, bool off);
void halrf_dpk_track_8852b(struct rf_info *rf);
#endif
#endif /* __HALRF_DPK_8852BH__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_dpk_8852b.h
|
C
|
agpl-3.0
| 1,832
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
bool halrf_get_efuse_info_8852b(struct rf_info *rf, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length,
u8 autoload_status)
{
struct rtw_hal_com_t *hal = rf->hal_com;
u32 offset = 0;
u8 default_value = 0;
if (length != 1)
return false;
switch (id) {
case EFUSE_INFO_RF_PKG_TYPE:
offset = 0;
default_value = 0;
break;
case EFUSE_INFO_RF_PA:
offset = 0;
default_value = 0;
break;
case EFUSE_INFO_RF_VALID_PATH:
offset = 0;
default_value = 0;
break;
case EFUSE_INFO_RF_RFE:
offset = EFUSE_INFO_RF_RFE_8852B_ADDR;
default_value = EFUSE_INFO_RF_RFE_8852B_VALUE;
break;
case EFUSE_INFO_RF_TXPWR:
offset = 0;
default_value = 0;
break;
case EFUSE_INFO_RF_BOARD_OPTION:
offset = EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR;
default_value = EFUSE_INFO_RF_BOARD_OPTION_8852B_VALUE;
break;
case EFUSE_INFO_RF_CHAN_PLAN:
offset = EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR;
default_value = EFUSE_INFO_RF_CHAN_PLAN_8852B_VALUE;
break;
case EFUSE_INFO_RF_COUNTRY:
offset = 0;
default_value = 0;
break;
/*TSSI DE PathA CCK*/
case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1:
offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2:
offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3:
offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4:
offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5:
offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6:
offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
/*TSSI DE PathA 2G MCS7 BW40M*/
case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1:
offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2:
offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3:
offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4:
offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5:
offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
/*TSSI DE PathA 5G MCS7 BW40M*/
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14:
offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
/*TSSI DE PathB CCK*/
case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1:
offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2:
offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3:
offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4:
offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5:
offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6:
offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
/*TSSI DE PathB 2G MCS7 BW40M*/
case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1:
offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2:
offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3:
offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4:
offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5:
offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
/*TSSI DE PathB 5G MCS7 BW40M*/
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14:
offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852B_ADDR;
default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
break;
case EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK:
offset = EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852B_ADDR;
default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
break;
case EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD:
offset = EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852B_ADDR;
default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
break;
case EFUSE_INFO_RF_RX_GAIN_K_A_5GL:
offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852B_ADDR;
default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
break;
case EFUSE_INFO_RF_RX_GAIN_K_A_5GM:
offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852B_ADDR;
default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
break;
case EFUSE_INFO_RF_RX_GAIN_K_A_5GH:
offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852B_ADDR;
default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
break;
/*Thermal*/
case EFUSE_INFO_RF_THERMAL_A:
offset = EFUSE_INFO_RF_THERMAL_A_8852B_ADDR;
default_value = EFUSE_INFO_RF_THERMAL_A_8852B_VALUE;
break;
case EFUSE_INFO_RF_THERMAL_B:
offset = EFUSE_INFO_RF_THERMAL_B_8852B_ADDR;
default_value = EFUSE_INFO_RF_THERMAL_B_8852B_VALUE;
break;
case EFUSE_INFO_RF_XTAL:
offset = EFUSE_INFO_RF_XTAL_8852B_ADDR;
default_value = EFUSE_INFO_RF_XTAL_8852B_VALUE;
break;
default:
return false;
}
if (autoload_status == 0)
hal_mem_cpy(hal, value, &default_value, 1);
else {
hal_mem_cpy(hal, value, efuse_map + offset, length);
if (id == EFUSE_INFO_RF_XTAL) {
if (*((u8 *)value) == 0xff)
hal_mem_set(hal, value, 0x3f, 1);
}
}
return true;
}
#endif /*#ifdef RF_8852B_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.c
|
C
|
agpl-3.0
| 12,160
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_EFUSE_8852B_H_
#define _HALRF_EFUSE_8852B_H_
#ifdef RF_8852B_SUPPORT
enum halrf_efsue_info_8852b_offset {
EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR = 0x2c1,
EFUSE_INFO_RF_RFE_8852B_ADDR = 0x2ca,
EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR = 0x2b8,
EFUSE_INFO_RF_XTAL_8852B_ADDR = 0x2b9,
EFUSE_INFO_RF_THERMAL_A_8852B_ADDR = 0x2d0,
EFUSE_INFO_RF_THERMAL_B_8852B_ADDR = 0x2d1,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR = 0x210,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR = 0x211,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR = 0x212,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR = 0x213,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852B_ADDR = 0x214,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852B_ADDR = 0x215,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852B_ADDR = 0x216,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852B_ADDR = 0x217,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852B_ADDR = 0x218,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852B_ADDR = 0x219,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852B_ADDR = 0x21a,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852B_ADDR = 0x222,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852B_ADDR = 0x223,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852B_ADDR = 0x224,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852B_ADDR = 0x225,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852B_ADDR = 0x226,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852B_ADDR = 0x227,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852B_ADDR = 0x228,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852B_ADDR = 0x229,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852B_ADDR = 0x22a,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852B_ADDR = 0x22b,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852B_ADDR = 0x22c,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852B_ADDR = 0x22d,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852B_ADDR = 0x22e,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852B_ADDR = 0x22f,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852B_ADDR = 0x23a,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852B_ADDR = 0x23b,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852B_ADDR = 0x23c,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852B_ADDR = 0x23d,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852B_ADDR = 0x23e,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852B_ADDR = 0x23f,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852B_ADDR = 0x240,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852B_ADDR = 0x241,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852B_ADDR = 0x242,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852B_ADDR = 0x243,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852B_ADDR = 0x244,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852B_ADDR = 0x24c,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852B_ADDR = 0x24d,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852B_ADDR = 0x24e,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852B_ADDR = 0x24f,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852B_ADDR = 0x250,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852B_ADDR = 0x251,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852B_ADDR = 0x252,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852B_ADDR = 0x253,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852B_ADDR = 0x254,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852B_ADDR = 0x255,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852B_ADDR = 0x256,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852B_ADDR = 0x257,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852B_ADDR = 0x258,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852B_ADDR = 0x259,
EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852B_ADDR = 0x2d6,
EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852B_ADDR = 0x2d4,
EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852B_ADDR = 0x2d8,
EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852B_ADDR = 0x2da,
EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852B_ADDR = 0x2dc
};
enum halrf_efsue_default_value_8852b {
EFUSE_INFO_RF_RFE_8852B_VALUE = 0x1,
EFUSE_INFO_RF_CHAN_PLAN_8852B_VALUE = 0x7f,
EFUSE_INFO_RF_XTAL_8852B_VALUE = 0x3f,
EFUSE_INFO_RF_THERMAL_A_8852B_VALUE = 0x22,
EFUSE_INFO_RF_THERMAL_B_8852B_VALUE = 0x22,
EFUSE_INFO_RF_TSSI_DE_8852B_VALUE = 0x0,
EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE = 0xf,
EFUSE_INFO_RF_BOARD_OPTION_8852B_VALUE = 0x1
};
bool halrf_get_efuse_info_8852b(struct rf_info *rf, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length,
u8 autoload_status);
#endif /*RF_8852B_SUPPORT*/
#endif /*_HALRF_EFUSE_8852B_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_efuse_8852b.h
|
C
|
agpl-3.0
| 5,013
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#include "halrf_hwimg_raw_data_8852b.h"
#include "halrf_hwimg_nctl_raw_data_8852b.h"
bool halrf_check_cond_8852b(struct rf_info *rf, u32 para_opt)
{
struct rtw_hal_com_t *hal = rf->hal_com;
u32 cv_ver = (hal->cv == CAV) ? 15 : hal->cv;
/*[20200204][Dino]Request from SD7 Sinda, and need Sinda to tell us what is the correct pkg_type/rfe_type parameters in PHL layer for halbb reference*/
u8 pkg_type = 0; /*(hal->efuse->pkg_type == 0) ? 15 : hal->efuse->pkg_type;*/
u8 rfe_type = 0; /*hal->efuse->rfe_type;*/
u32 drv_cfg = cv_ver << 16 | pkg_type << 8 | rfe_type;
u32 para_opt_tmp = 0;
/*============== value Defined Check ===============*/
/*Cart ver BIT[23:16]*/
para_opt_tmp = para_opt & 0xff0000;
if (para_opt_tmp && (para_opt_tmp != (drv_cfg & 0xff0000)))
return false;
/*PKG type, BIT[15:8]*/
para_opt_tmp = para_opt & 0xff00;
if (para_opt_tmp && (para_opt_tmp != (drv_cfg & 0xff00)))
return false;
/*RFE, BIT[7:0]*/
para_opt_tmp = para_opt & 0xff;
if (para_opt_tmp && (para_opt_tmp != (drv_cfg & 0xff)))
return false;
return true;
}
u32
halrf_get_8852b_nctl_reg_ver(void)
{
return 0xa;
}
u32
halrf_get_8852b_radio_reg_ver(void)
{
return RF_RELEASE_VERSION_8852B;
}
void halrf_config_8852b_store_radio_a_reg(struct rf_info *rf,
u32 addr, u32 data)
{
struct halrf_radio_info *radio = &rf->radio_info;
u32 page = radio->write_times_a / RADIO_TO_FW_DATA_SIZE;
u32 idx = radio->write_times_a % RADIO_TO_FW_DATA_SIZE;
u32 reg_tmp = 0;
RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__);
if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
addr == 0xfa || addr == 0xf9) {
RF_DBG(rf, DBG_RF_INIT, "Radio parameter is delay return!!!\n");
return;
}
if (data > 0xfffff)
RF_DBG(rf, DBG_RF_INIT, "Radio parameter format error !!!\n");
/*DRFC only*/
if (addr < 0x100)
return;
addr &= 0xff;
reg_tmp = cpu_to_le32((addr << 20) | data);
radio->radio_a_parameter[page][idx] = reg_tmp;
RF_DBG(rf, DBG_RF_INIT, "radioA->radio_parameter[%d][%03d]=0x%08x\n",
page, idx, radio->radio_a_parameter[page][idx]);
radio->write_times_a++;
}
void halrf_config_8852b_store_radio_b_reg(struct rf_info *rf,
u32 addr, u32 data)
{
struct halrf_radio_info *radio = &rf->radio_info;
u32 page = radio->write_times_b / RADIO_TO_FW_DATA_SIZE;
u32 idx = radio->write_times_b % RADIO_TO_FW_DATA_SIZE;
u32 reg_tmp = 0;
RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__);
if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
addr == 0xfa || addr == 0xf9) {
RF_DBG(rf, DBG_RF_INIT, "Radio parameter is delay return!!!\n");
return;
}
if (data > 0xfffff)
RF_DBG(rf, DBG_RF_INIT, "Radio parameter format error !!!\n");
/*DRFC only*/
if (addr < 0x100)
return;
addr &= 0xff;
reg_tmp = cpu_to_le32((addr << 20) | data);
radio->radio_b_parameter[page][idx] = reg_tmp;
RF_DBG(rf, DBG_RF_INIT, "radioB->radio_parameter[%d][%03d]=0x%08x\n",
page, idx, radio->radio_b_parameter[page][idx]);
radio->write_times_b++;
}
void halrf_config_8852b_write_radio_a_reg_to_fw(struct rf_info *rf)
{
struct halrf_radio_info *radio = &rf->radio_info;
u8 page = (u8)(radio->write_times_a / RADIO_TO_FW_DATA_SIZE);
u16 len = (radio->write_times_a % RADIO_TO_FW_DATA_SIZE) * 4;
u8 i;
RF_DBG(rf, DBG_RF_INIT, "======> %s write_times_a=%d page=%d len=%d\n",
__func__, radio->write_times_a, page, len / 4);
for (i = 0; i < page; i++) {
halrf_fill_h2c_cmd(rf, RADIO_TO_FW_DATA_SIZE * 4, i, 8,
H2CB_TYPE_LONG_DATA, radio->radio_a_parameter[i]);
RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4);
}
halrf_fill_h2c_cmd(rf, len, i, 8,
H2CB_TYPE_LONG_DATA, radio->radio_a_parameter[i]);
RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4);
}
void halrf_config_8852b_write_radio_b_reg_to_fw(struct rf_info *rf)
{
struct halrf_radio_info *radio = &rf->radio_info;
u8 page = (u8)(radio->write_times_b / RADIO_TO_FW_DATA_SIZE);
u16 len = (radio->write_times_b % RADIO_TO_FW_DATA_SIZE) * 4;
u8 i;
RF_DBG(rf, DBG_RF_INIT, "======> %s write_times_b=%d page=%d len=%d\n",
__func__, radio->write_times_b, page, len / 4);
for (i = 0; i < page; i++) {
halrf_fill_h2c_cmd(rf, RADIO_TO_FW_DATA_SIZE * 4, i, 9,
H2CB_TYPE_LONG_DATA, radio->radio_b_parameter[i]);
RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4);
}
halrf_fill_h2c_cmd(rf, len, i, 9,
H2CB_TYPE_LONG_DATA, radio->radio_b_parameter[i]);
RF_DBG(rf, DBG_RF_INIT, "page=%d len=%d\n", i, len / 4);
}
void halrf_config_8852b_radio_to_fw(struct rf_info *rf)
{
halrf_config_8852b_write_radio_a_reg_to_fw(rf);
halrf_config_8852b_write_radio_b_reg_to_fw(rf);
}
void halrf_config_8852b_nctl_reg(struct rf_info *rf)
{
u32 i = 0;
u32 array_len = 0x0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u32 cnt = 0x0;
RF_DBG(rf, DBG_RF_INIT, "[RFK]===> %s\n", __func__);
//5. iqkdpk clk&rst
halrf_wreg(rf, 0x0c60, 0x00000003, 0x3);
halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1);
halrf_wreg(rf, 0x58ac, 0x08000000, 0x1);
halrf_wreg(rf, 0x78ac, 0x08000000, 0x1);
halrf_wreg(rf, 0x0c60, 0x00000002, 0x1);
array_len = sizeof(array_mp_8852b_nctl_reg) / sizeof(u32);
array = (u32 *) &array_mp_8852b_nctl_reg;
// check 0x8080
halrf_wreg(rf, 0x8000, MASKDWORD, 0x8);
while(cnt < 1000) {
cnt++;
halrf_wreg(rf, 0x8080, MASKDWORD, 0x4);
halrf_delay_us(rf, 1);
if(halrf_rreg(rf, 0x8080, MASKDWORD) == 0x4)
break;
}
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
halrf_cfg_rf_nctl_8852b(rf, v1, MASKDWORD, v2);
i += 2;
}
}
bool halrf_sel_headline_8852b(struct rf_info *rf, u32 *array, u32 array_len,
u8 *headline_size, u8 *headline_idx)
{
bool case_match = false;
u8 cv_drv_org = rf->hal_com->cv;
u8 rfe_drv_org = rf->phl_com->dev_cap.rfe_type;
u32 cv_para = 0, rfe_para = 0;
u32 compare_target = 0;
u32 cv_max = 0;
u32 i = 0;
u32 cv_drv = (u32)cv_drv_org;
u32 rfe_drv = (u32)rfe_drv_org;
*headline_idx = 0;
*headline_size = 0;
#if 0
if (rf->rf_dbg_i.cr_dbg_mode_en) {
rfe_drv = rf->rf_dbg_i.rfe_type_curr_dbg;
cv_drv = rf->rf_dbg_i.cv_curr_dbg;
}
RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n",
rfe_drv, cv_drv, rf->rf_dbg_i.cr_dbg_mode_en);
#endif
RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart}={%d, %d}\n",
rfe_drv, cv_drv);
while ((i + 1) < array_len) {
if ((array[i] >> 28) != 0xf) {
*headline_size = (u8)i;
break;
}
RF_DBG(rf, DBG_RF_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n",
i, array[i], i+1, array[i+1]);
i += 2;
}
RF_DBG(rf, DBG_RF_INIT, "headline_size=%d\n", i);
if (i == 0)
return true;
/*case_idx:1 {RFE:Match, cv:Match}*/
compare_target = ((rfe_drv & 0xff) << 16) | (cv_drv & 0xff);
RF_DBG(rf, DBG_RF_INIT, "[1] CHK {RFE:Match, cv:Match}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
RF_DBG(rf, DBG_RF_INIT, "\t fail\n");
/*case_idx:2 {RFE:Match, cv:Dont care}*/
compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852B & 0xff);
RF_DBG(rf, DBG_RF_INIT, "[2] CHK {RFE:Match, cv:Dont_Care}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
RF_DBG(rf, DBG_RF_INIT, "\t fail\n");
/*case_idx:3 {RFE:Match, cv:Max_in_table}*/
RF_DBG(rf, DBG_RF_INIT, "[3] CHK {RFE:Match, cv:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cv_para = array[i] & 0x0ff;
if (rfe_para == rfe_drv) {
if (cv_para > cv_max) {
cv_max = cv_para;
*headline_idx = (u8)(i >> 1);
RF_DBG(rf, DBG_RF_INIT, "cv_max:%d\n", cv_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
RF_DBG(rf, DBG_RF_INIT, "\t fail\n");
/*case_idx:4 {RFE:Dont Care, cv:Max_in_table}*/
RF_DBG(rf, DBG_RF_INIT, "[4] CHK {RFE:Dont_Care, cv:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cv_para = array[i] & 0x0ff;
if (rfe_para == DONT_CARE_8852B) {
if (cv_para >= cv_max) {
cv_max = cv_para;
*headline_idx = (u8)(i >> 1);
RF_DBG(rf, DBG_RF_INIT, "cv_max:%d\n", cv_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
RF_DBG(rf, DBG_RF_INIT, "\t fail\n");
/*case_idx:5 {RFE:Not_Match, cv:Not_Match}*/
RF_DBG(rf, DBG_RF_INIT, "[5] CHK {RFE:Not_Match, cv:Not_Match}\n");
RF_DBG(rf, DBG_RF_INIT, "\t all fail\n");
return false;
}
void halrf_flag_2_default_8852b(bool *is_matched, bool *find_target)
{
*is_matched = true;
*find_target = false;
}
void
halrf_config_8852b_radio_a_reg(struct rf_info *rf, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
#if 0
struct rtw_hal_com_t *hal = rf->hal_com;
struct halrf_radio_info *radio = &rf->radio_info;
u32 i = 0, j = 0;
u32 c_cond;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u32 tmp_val = 0;
u32 cv = 0; /*cv ver of para*/
u8 rfe_type_org = 0; /*rfe ver of para*/
u32 cv_curr = (u32)rf->hal_com->cv;
u8 rfe_type_curr_org = (u32)rf->phl_com->dev_cap.rfe_type;
u32 cv_max = 0;
u32 latest_rfe_match_entry = 0;
bool is_matched = true;
bool is_skipped = false;
bool is_rfe_match = false;
bool is_cart_match = false;
bool is_else_case = false;
bool is_rfe_ever_match = false;
u32 rfe_type = (u32)rfe_type_org;
u32 rfe_type_curr = (u32)rfe_type_curr_org;
radio->write_times_a = 0;
hal_mem_set(hal, radio->radio_a_parameter, 0, sizeof(radio->radio_a_parameter));
RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_radioa) / sizeof(u32);
array = (u32 *)array_mp_8852b_radioa;
}
RF_DBG(rf, DBG_RF_INIT, "RF CR form_folder=%d, len=%d\n",
is_form_folder, array_len);
RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart} = (%d, %d)\n",
rfe_type_curr, cv_curr);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & BIT(31)) {
/*Get para-setting from para-array*/
c_cond = v1 >> 28;
if (c_cond == 0xb) {/*b:end*/
is_matched = true;
is_skipped = false;
RF_DBG(rf, DBG_RF_INIT, "END\n");
} else {/*8:if , 9:else if*/
tmp_val = (v1 & 0xff0000) >> 16;
if (tmp_val == DONT_CARE_8852b) {
is_rfe_match = true; /*dont care condition*/
} else {
rfe_type = tmp_val;
is_rfe_match = (rfe_type == rfe_type_curr);
}
tmp_val = v1 & 0xff;
if (tmp_val == DONT_CARE_8852b) {
is_cart_match = true; /*dont care condition*/
} else {
cv = tmp_val;
is_cart_match = (cv == cv_curr);
}
if (c_cond == 0xa) { /*a:else*/
is_else_case = is_skipped ? false : true;
RF_DBG(rf, DBG_RF_INIT, "ELSE\n");
if (!is_rfe_ever_match) {
/*RF_WARNING("Set Default CR\n");*/
is_matched = is_skipped ? false : true;
}
} else if (c_cond == 0x9) {
RF_DBG(rf, DBG_RF_INIT, "ELSE IF (rfe=%d, cart=%d)\n",
rfe_type, cv);
} else {
RF_DBG(rf, DBG_RF_INIT, "IF (rfe=%d, cart=%d)\n",
rfe_type, cv);
}
RF_DBG(rf, DBG_RF_INIT, "is_rfe_match=%d, is_cart_match=%d)\n",
is_rfe_match, is_cart_match);
}
} else if (v1 & BIT(30)) {
/*Check this para-setting meets driver's requirement or not*/
if (is_skipped) {
is_matched = false;
} else {
//rpt = halbb_check_cond_8852b(bb, rfe_type, cv);
if (is_rfe_match && is_cart_match) {
is_matched = true;
is_skipped = true;
RF_DBG(rf, DBG_RF_INIT, " ==>match\n");
} else {
is_matched = false;
is_skipped = false;
}
}
} else {
if (is_matched) {
halrf_cfg_rf_radio_a_8852b(rf, v1, v2);
halrf_config_8852b_store_radio_a_reg(rf, v1, v2);
is_rfe_match = false;
is_else_case = false;
is_rfe_ever_match = false;
} else if (is_rfe_match) {
RF_DBG(rf, DBG_RF_INIT, "rfe_ever_match\n");
if (cv >= cv_max) {
cv_max = cv;
is_rfe_ever_match = true;
latest_rfe_match_entry = i;
RF_DBG(rf, DBG_RF_INIT, "Update entry=%d\n", latest_rfe_match_entry);
}
is_rfe_match = false;
} else if (is_else_case) {
is_else_case = false;
is_rfe_ever_match = false;
is_rfe_match = false;
j = latest_rfe_match_entry;
RF_DBG(rf, DBG_RF_INIT, "Set RFE match value, entry=%d\n", latest_rfe_match_entry);
do {
v1 = array[j];
v2 = array[j + 1];
halrf_cfg_rf_radio_a_8852b(rf, v1, v2);
halrf_config_8852b_store_radio_a_reg(rf, v1, v2);
j = j + 2;
} while (!(array[j] & 0xC0000000));
}
}
i += 2;
}
#else
struct rtw_hal_com_t *hal = rf->hal_com;
struct halrf_radio_info *radio = &rf->radio_info;
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__, is_form_folder, folder_len);
radio->write_times_a = 0;
hal_mem_set(hal, radio->radio_a_parameter, 0, sizeof(radio->radio_a_parameter));
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_radioa) / sizeof(u32);
array = (u32 *)array_mp_8852b_radioa;
}
RF_DBG(rf, DBG_RF_INIT, "RFCR_form_folder=%d, len=%d\n",
is_form_folder, array_len);
if (!halrf_sel_headline_8852b(rf, array, array_len, &h_size, &h_idx)) {
RF_WARNING("[%s]Invalid RF CR Pkg\n", __func__);
return;
}
RF_DBG(rf, DBG_RF_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
RF_DBG(rf, DBG_RF_INIT, "cfg_target = 0x%x\n", cfg_target);
RF_DBG(rf, DBG_RF_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halrf_flag_2_default_8852b(&is_matched, &find_target);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852B:
case ELSE_IF_8852B:
cfg_para = v1 & 0x0fffffff;
RF_DBG(rf, DBG_RF_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852B:
RF_DBG(rf, DBG_RF_INIT, "*else\n");
is_matched = false;
if (!find_target) {
RF_WARNING("Init RFCR Fail in Reg 0x%x\n", array[i]);
return;
}
break;
case END_8852B:
RF_DBG(rf, DBG_RF_INIT, "*endif\n");
halrf_flag_2_default_8852b(&is_matched, &find_target);
break;
case CHK_8852B:
/*Check this para meets driver's requirement or not*/
if (find_target) {
RF_DBG(rf, DBG_RF_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
RF_DBG(rf, DBG_RF_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched) {
halrf_cfg_rf_radio_a_8852b(rf, v1, v2);
halrf_config_8852b_store_radio_a_reg(rf, v1, v2);
}
break;
}
}
RF_DBG(rf, DBG_RF_INIT, "RFCR Init Success\n");
halrf_config_8852b_write_radio_a_reg_to_fw(rf);
#endif
}
void
halrf_config_8852b_radio_b_reg(struct rf_info *rf, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
#if 0
struct rtw_hal_com_t *hal = rf->hal_com;
struct halrf_radio_info *radio = &rf->radio_info;
u32 i = 0, j = 0;
u32 c_cond;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u32 tmp_val = 0;
u32 cv = 0; /*cv ver of para*/
u8 rfe_type_org = 0; /*rfe ver of para*/
u32 cv_curr = (u32)rf->hal_com->cv;
u8 rfe_type_curr_org = (u32)rf->phl_com->dev_cap.rfe_type;
u32 cv_max = 0;
u32 latest_rfe_match_entry = 0;
bool is_matched = true;
bool is_skipped = false;
bool is_rfe_match = false;
bool is_cart_match = false;
bool is_else_case = false;
bool is_rfe_ever_match = false;
u32 rfe_type = (u32)rfe_type_org;
u32 rfe_type_curr = (u32)rfe_type_curr_org;
radio->write_times_b = 0;
hal_mem_set(hal, radio->radio_b_parameter, 0, sizeof(radio->radio_b_parameter));
RF_DBG(rf, DBG_RF_INIT, "======> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_radiob) / sizeof(u32);
array = (u32 *)array_mp_8852b_radiob;
}
RF_DBG(rf, DBG_RF_INIT, "BBCR_form_folder=%d, len=%d\n",
is_form_folder, array_len);
RF_DBG(rf, DBG_RF_INIT, "{RFE, Cart} = (%d, %d)\n",
rfe_type_curr, cv_curr);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & BIT(31)) {
/*Get para-setting from para-array*/
c_cond = v1 >> 28;
if (c_cond == 0xb) {/*b:end*/
is_matched = true;
is_skipped = false;
RF_DBG(rf, DBG_RF_INIT, "END\n");
} else {/*8:if , 9:else if*/
tmp_val = (v1 & 0xff0000) >> 16;
if (tmp_val == DONT_CARE_8852b) {
is_rfe_match = true; /*dont care condition*/
} else {
rfe_type = tmp_val;
is_rfe_match = (rfe_type == rfe_type_curr);
}
tmp_val = v1 & 0xff;
if (tmp_val == DONT_CARE_8852b) {
is_cart_match = true; /*dont care condition*/
} else {
cv = tmp_val;
is_cart_match = (cv == cv_curr);
}
if (c_cond == 0xa) { /*a:else*/
is_else_case = is_skipped ? false : true;
RF_DBG(rf, DBG_RF_INIT, "ELSE\n");
if (!is_rfe_ever_match) {
/*RF_WARNING("Set Default CR\n");*/
is_matched = is_skipped ? false : true;
}
} else if (c_cond == 0x9) {
RF_DBG(rf, DBG_RF_INIT, "ELSE IF (rfe=%d, cart=%d)\n",
rfe_type, cv);
} else {
RF_DBG(rf, DBG_RF_INIT, "IF (rfe=%d, cart=%d)\n",
rfe_type, cv);
}
RF_DBG(rf, DBG_RF_INIT, "is_rfe_match=%d, is_cart_match=%d)\n",
is_rfe_match, is_cart_match);
}
} else if (v1 & BIT(30)) {
/*Check this para-setting meets driver's requirement or not*/
if (is_skipped) {
is_matched = false;
} else {
//rpt = halbb_check_cond_8852b(bb, rfe_type, cv);
if (is_rfe_match && is_cart_match) {
is_matched = true;
is_skipped = true;
RF_DBG(rf, DBG_RF_INIT, " ==>match\n");
} else {
is_matched = false;
is_skipped = false;
}
}
} else {
if (is_matched) {
halrf_cfg_rf_radio_b_8852b(rf, v1, v2);
halrf_config_8852b_store_radio_b_reg(rf, v1, v2);
is_rfe_match = false;
is_else_case = false;
is_rfe_ever_match = false;
} else if (is_rfe_match) {
RF_DBG(rf, DBG_RF_INIT, "rfe_ever_match\n");
if (cv >= cv_max) {
cv_max = cv;
is_rfe_ever_match = true;
latest_rfe_match_entry = i;
RF_DBG(rf, DBG_RF_INIT, "Update entry=%d\n", latest_rfe_match_entry);
}
is_rfe_match = false;
} else if (is_else_case) {
is_else_case = false;
is_rfe_ever_match = false;
is_rfe_match = false;
j = latest_rfe_match_entry;
RF_DBG(rf, DBG_RF_INIT, "Set RFE match value, entry=%d\n", latest_rfe_match_entry);
do {
v1 = array[j];
v2 = array[j + 1];
halrf_cfg_rf_radio_b_8852b(rf, v1, v2);
halrf_config_8852b_store_radio_b_reg(rf, v1, v2);
j = j + 2;
} while (!(array[j] & 0xC0000000));
}
}
i += 2;
}
#else
struct rtw_hal_com_t *hal = rf->hal_com;
struct halrf_radio_info *radio = &rf->radio_info;
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__, is_form_folder, folder_len);
radio->write_times_b = 0;
hal_mem_set(hal, radio->radio_b_parameter, 0, sizeof(radio->radio_b_parameter));
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_radiob) / sizeof(u32);
array = (u32 *)array_mp_8852b_radiob;
}
RF_DBG(rf, DBG_RF_INIT, "RFCR_form_folder=%d, len=%d\n",
is_form_folder, array_len);
if (!halrf_sel_headline_8852b(rf, array, array_len, &h_size, &h_idx)) {
RF_WARNING("[%s]Invalid RF CR Pkg\n", __func__);
return;
}
RF_DBG(rf, DBG_RF_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
RF_DBG(rf, DBG_RF_INIT, "cfg_target = 0x%x\n", cfg_target);
RF_DBG(rf, DBG_RF_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halrf_flag_2_default_8852b(&is_matched, &find_target);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852B:
case ELSE_IF_8852B:
cfg_para = v1 & 0x0fffffff;
RF_DBG(rf, DBG_RF_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852B:
RF_DBG(rf, DBG_RF_INIT, "*else\n");
is_matched = false;
if (!find_target) {
RF_WARNING("Init RFCR Fail in Reg 0x%x\n", array[i]);
return;
}
break;
case END_8852B:
RF_DBG(rf, DBG_RF_INIT, "*endif\n");
halrf_flag_2_default_8852b(&is_matched, &find_target);
break;
case CHK_8852B:
/*Check this para meets driver's requirement or not*/
if (find_target) {
RF_DBG(rf, DBG_RF_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
RF_DBG(rf, DBG_RF_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched) {
halrf_cfg_rf_radio_b_8852b(rf, v1, v2);
halrf_config_8852b_store_radio_b_reg(rf, v1, v2);
}
break;
}
}
RF_DBG(rf, DBG_RF_INIT, "RFCR Init Success\n");
halrf_config_8852b_write_radio_b_reg_to_fw(rf);
#endif
}
void
halrf_config_8852b_store_power_by_rate(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u32 i, j;
u32 array_len = 0;
u32 *array = NULL;
RF_DBG(rf, DBG_RF_INIT, "======> %s folder_len=%d\n", __func__, folder_len);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852b_txpwr_byrate) / sizeof(u32);
array = (u32 *)array_mp_8852b_txpwr_byrate;
}
for (i = 0; i < array_len; i += 4) {
u32 band = array[i];
u32 tx_num = array[i + 1];
u32 rate_id = array[i + 2];
u32 data = array[i + 3];
halrf_power_by_rate_store_to_array(rf, band, tx_num, rate_id, data);
}
for (i = 0; i < PW_LMT_MAX_BAND; i++)
for (j = 0; j < HALRF_DATA_RATE_MAX; j++)
RF_DBG(rf, DBG_RF_INIT, "pwr_by_rate[%d][%03d]=%d\n",
i, j, pwr->tx_pwr_by_rate[i][j]);
/*compiler error*/
pwr->tx_pwr_by_rate[0][0]++;
pwr->tx_pwr_by_rate[0][0]--;
}
void
halrf_config_8852b_store_power_limit(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
const struct halrf_tx_pw_lmt *array = NULL;
struct halrf_tx_pw_lmt *parray = NULL;
struct halrf_pwr_info *pwr = &rf->pwr_info;
u32 i;
u32 array_len = 0;
u8 band, bandwidth, tx_num, rate, beamforming, regulation, chnl, val;
RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__,
is_form_folder, folder_len);
if (is_form_folder) {
array_len = folder_len;
parray = (struct halrf_tx_pw_lmt *) folder_array;
for (i = 0; i < array_len; i++) {
array = (struct halrf_tx_pw_lmt *)&parray[i];
band = array->band;
bandwidth = array->bw;
tx_num = array->ntx;
rate = array->rs;
beamforming = array->bf;
regulation = array->reg;
chnl = array->ch;
val = array->val;
pwr->regulation[band][regulation] = true;
if (rate == PW_LMT_RS_CCK) {
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array->tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]);
} else {
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array->tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]);
}
halrf_power_limit_store_to_array(rf, regulation, band, bandwidth,
rate, tx_num, beamforming, chnl, val);
}
} else {
array_len = sizeof(array_mp_8852b_txpwr_lmt) / sizeof(struct halrf_tx_pw_lmt);
array = array_mp_8852b_txpwr_lmt;
for (i = 0; i < array_len; i++) {
band = array[i].band;
bandwidth = array[i].bw;
tx_num = array[i].ntx;
rate = array[i].rs;
beamforming = array[i].bf;
regulation = array[i].reg;
chnl = array[i].ch;
val = array[i].val;
pwr->regulation[band][regulation] = true;
if (rate == PW_LMT_RS_CCK) {
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array[i].tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]);
} else {
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array[i].tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]);
}
halrf_power_limit_store_to_array(rf, regulation, band, bandwidth,
rate, tx_num, beamforming, chnl, val);
}
}
halrf_power_limit_set_worldwide(rf);
halrf_power_limit_set_ext_pwr_limit_table(rf, 0);
}
void
halrf_config_8852b_store_power_limit_ru(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
const struct halrf_tx_pw_lmt_ru *array = NULL;
struct halrf_tx_pw_lmt_ru *parray = NULL;
struct halrf_pwr_info *pwr = &rf->pwr_info;
u32 i;
u32 array_len = 0;
u8 band, bandwidth, tx_num, rate, regulation, chnl, val;
RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n", __func__,
is_form_folder, folder_len);
if (is_form_folder) {
array_len = folder_len;
parray = (struct halrf_tx_pw_lmt_ru *) folder_array;
for (i = 0; i < array_len; i++) {
array = (struct halrf_tx_pw_lmt_ru *)&parray[i];
band = array->band;
bandwidth = array->bw;
tx_num = array->ntx;
rate = array->rs;
regulation = array->reg;
chnl = array->ch;
val = array->val;
if (rate == PW_LMT_RS_CCK) {
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array->tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]);
} else {
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array->tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]);
}
halrf_power_limit_ru_store_to_array(rf, band, bandwidth, tx_num,
rate, regulation, chnl, val);
}
} else {
array_len = sizeof(array_mp_8852b_txpwr_lmt_ru) / sizeof(struct halrf_tx_pw_lmt_ru);
array = array_mp_8852b_txpwr_lmt_ru;
for (i = 0; i < array_len; i++) {
band = array[i].band;
bandwidth = array[i].bw;
tx_num = array[i].ntx;
rate = array[i].rs;
regulation = array[i].reg;
chnl = array[i].ch;
val = array[i].val;
if (rate == PW_LMT_RS_CCK) {
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation] = array[i].tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][CCK][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_CCK][regulation]);
} else {
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation] = array[i].tx_shap_idx;
RF_DBG(rf, DBG_RF_INIT, "======>%s pwr->tx_shap_idx[%d][OFDM][%d]=%d\n",
__func__, band, regulation,
pwr->tx_shap_idx[band][TX_SHAPE_OFDM][regulation]);
}
halrf_power_limit_ru_store_to_array(rf, band, bandwidth, tx_num,
rate, regulation, chnl, val);
}
}
halrf_power_limit_ru_set_worldwide(rf);
halrf_power_limit_set_ext_pwr_limit_ru_table(rf, 0);
}
void
halrf_config_8852b_store_pwr_track(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct halrf_pwr_track_info *tmp_info = NULL;
struct halrf_pwr_track_info *pwr_trk = &rf->pwr_track;
struct rtw_hal_com_t *hal = rf->hal_com;
RF_DBG(rf, DBG_RF_INIT, "======> %s is_form_folder=%d folder_len=%d\n",
__func__, is_form_folder, folder_len);
if (is_form_folder) {
tmp_info = (struct halrf_pwr_track_info *) folder_array;
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_p,
tmp_info->delta_swing_table_idx_2ga_p,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_n,
tmp_info->delta_swing_table_idx_2ga_n,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_p,
tmp_info->delta_swing_table_idx_2gb_p,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_n,
tmp_info->delta_swing_table_idx_2gb_n,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_p,
tmp_info->delta_swing_table_idx_2g_cck_a_p,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_n,
tmp_info->delta_swing_table_idx_2g_cck_a_n,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_p,
tmp_info->delta_swing_table_idx_2g_cck_b_p,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_n,
tmp_info->delta_swing_table_idx_2g_cck_b_n,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_p,
tmp_info->delta_swing_table_idx_5ga_p,
DELTA_SWINGIDX_SIZE * 3);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_n,
tmp_info->delta_swing_table_idx_5ga_n,
DELTA_SWINGIDX_SIZE * 3);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_p,
tmp_info->delta_swing_table_idx_5gb_p,
DELTA_SWINGIDX_SIZE * 3);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_n,
tmp_info->delta_swing_table_idx_5gb_n,
DELTA_SWINGIDX_SIZE * 3);
} else {
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_p,
(void *)delta_swingidx_mp_2ga_p_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2ga_n,
(void *)delta_swingidx_mp_2ga_n_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_p,
(void *)delta_swingidx_mp_2gb_p_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2gb_n,
(void *)delta_swingidx_mp_2gb_n_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_p,
(void *)delta_swingidx_mp_2g_cck_a_p_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_a_n,
(void *)delta_swingidx_mp_2g_cck_a_n_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_p,
(void *)delta_swingidx_mp_2g_cck_b_p_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_2g_cck_b_n,
(void *)delta_swingidx_mp_2g_cck_b_n_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_p,
(void *)delta_swingidx_mp_5ga_p_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE * 3);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5ga_n,
(void *)delta_swingidx_mp_5ga_n_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE * 3);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_p,
(void *)delta_swingidx_mp_5gb_p_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE * 3);
hal_mem_cpy(hal, pwr_trk->delta_swing_table_idx_5gb_n,
(void *)delta_swingidx_mp_5gb_n_txpwrtrkssi_8852b,
DELTA_SWINGIDX_SIZE * 3);
}
}
void
_halrf_config_rfe_xtal_track_table_8852b(struct rf_info *rf)
{
#if 0
struct halrf_xtal_info *xtal_trk = &rf->xtal_track;
struct rtw_hal_com_t *hal = rf->hal_com;
hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_p,
(void *)delta_swing_xtal_mp_p_txxtaltrack_8852b,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_n,
(void *)delta_swing_xtal_mp_n_txxtaltrack_8852b,
DELTA_SWINGIDX_SIZE);
#endif
}
void
halrf_config_8852b_store_xtal_track(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct halrf_xtal_info *tmp_info = NULL;
struct halrf_xtal_info *xtal_trk = &rf->xtal_track;
struct rtw_hal_com_t *hal = rf->hal_com;
if (is_form_folder) {
tmp_info = (struct halrf_xtal_info *) folder_array;
hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_p,
tmp_info->delta_swing_xtal_table_idx_p,
DELTA_SWINGIDX_SIZE);
hal_mem_cpy(hal, xtal_trk->delta_swing_xtal_table_idx_n,
tmp_info->delta_swing_xtal_table_idx_n,
DELTA_SWINGIDX_SIZE);
} else {
_halrf_config_rfe_xtal_track_table_8852b(rf);
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.c
|
C
|
agpl-3.0
| 33,869
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_HW_IMG_8852B_H_
#define _HALRF_HW_IMG_8852B_H_
#ifdef RF_8852B_SUPPORT
#define DONT_CARE_8852B 0xff
#define IF_8852B 0x8
#define ELSE_IF_8852B 0x9
#define ELSE_8852B 0xa
#define END_8852B 0xb
#define CHK_8852B 0x4
#if 0
#define RADIO_TO_FW_PAGE_SIZE 6
#define RADIO_TO_FW_DATA_SIZE 500
#define FWCMD_H2C_RADIO_A_INIT_0 0x0
#define FWCMD_H2C_RADIO_A_INIT_1 0x1
#define FWCMD_H2C_RADIO_A_INIT_2 0x2
#define FWCMD_H2C_RADIO_A_INIT_3 0x3
#define FWCMD_H2C_RADIO_A_INIT_4 0x4
#define FWCMD_H2C_RADIO_A_INIT_5 0x5
#define FWCMD_H2C_RADIO_A_INIT_6 0x6
#define FWCMD_H2C_RADIO_A_INIT_7 0x7
#define FWCMD_H2C_RADIO_A_INIT_8 0x8
#define FWCMD_H2C_RADIO_A_INIT_9 0x9
#define FWCMD_H2C_RADIO_B_INIT_0 0x0
#define FWCMD_H2C_RADIO_B_INIT_1 0x1
#define FWCMD_H2C_RADIO_B_INIT_2 0x2
#define FWCMD_H2C_RADIO_B_INIT_3 0x3
#define FWCMD_H2C_RADIO_B_INIT_4 0x4
#define FWCMD_H2C_RADIO_B_INIT_5 0x5
#define FWCMD_H2C_RADIO_B_INIT_6 0x6
#define FWCMD_H2C_RADIO_B_INIT_7 0x7
#define FWCMD_H2C_RADIO_B_INIT_8 0x8
#define FWCMD_H2C_RADIO_B_INIT_9 0x9
struct halrf_radio_info {
u32 write_times_a;
u32 write_times_b;
u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
};
#endif
void halrf_config_8852b_nctl_reg(struct rf_info *rf);
void halrf_config_8852b_radio_a_reg(struct rf_info *rf, bool is_form_folder,
u32 folder_len, u32 *folder_array);
void halrf_config_8852b_radio_b_reg(struct rf_info *rf, bool is_form_folder,
u32 folder_len, u32 *folder_array);
void halrf_config_8852b_store_power_by_rate(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array);
void halrf_config_8852b_store_power_limit(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array);
void halrf_config_8852b_store_power_limit_ru(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array);
void halrf_config_8852b_store_pwr_track(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array);
void halrf_config_8852b_store_xtal_track(struct rf_info *rf,
bool is_form_folder, u32 folder_len, u32 *folder_array);
u32 halrf_get_8852b_nctl_reg_ver(void);
u32 halrf_get_8852b_radio_reg_ver(void);
void halrf_config_8852b_radio_to_fw(struct rf_info *rf);
#endif
#endif /* _HALRF_HW_IMG_8852b_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_8852b.h
|
C
|
agpl-3.0
| 3,316
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_HW_IMG_NCTL_INIT_REG_8852B_H_
#define _HALRF_HW_IMG_NCTL_INIT_REG_8852B_H_
const u32 array_mp_8852b_nctl_reg[] = {
//_Init0_IQKDPK_Init_Reg_52B_20210621
0x8000, 0x00000008,
0x8008, 0x00000000,
0x8004, 0xf0862966,
0x800c, 0x78000000,
0x8010, 0x88015000,
0x8014, 0x80010100,
0x8018, 0x10010100,
0x801c, 0xa210bc00,
0x8020, 0x000403e0,
0x8024, 0x00072160,
0x8028, 0x00180e00,
0x8030, 0x400000c0,
0x8034, 0x11000830,
0x8038, 0x00000009,
0x803c, 0x00000008,
0x8040, 0x00000046,
0x8044, 0x0010001f,
0x8048, 0xf0000003,
0x804c, 0x62ac6162,
0x8050, 0xf2acf162,
0x8054, 0x62ac6162,
0x8058, 0xf2acf162,
0x805c, 0x150c0b02,
0x8060, 0x150c0b02,
0x8064, 0x2aa00047,
0x8074, 0x80000000,
0x807c, 0x000000ee,
0x8088, 0x80000000,
0x8098, 0x0000ff00,
0x809c, 0x0000001f,
0x80a0, 0x00010300,
0x80b8, 0x00001000,
0x80b0, 0x00000000,
0x80d0, 0x00000000,
0x80ec, 0x00000002,
0x810c, 0x33112200,
0x8110, 0x33112200,
0x8114, 0x00000000,
0x8120, 0x10010000,
0x8124, 0x00000000,
0x812c, 0x0000c000,
0x8138, 0x40000000,
0x813c, 0x40000000,
0x8140, 0x00000000,
0x8144, 0x0b040b03,
0x8148, 0x0a050b04,
0x814c, 0x0a050b04,
0x8150, 0xe4e40000,
0x8158, 0xffffffff,
0x815c, 0xffffffff,
0x8160, 0xffffffff,
0x8164, 0xffffffff,
0x8168, 0xffffffff,
0x816c, 0x1fffffff,
0x81a0, 0x00000000,
0x81ac, 0x003f2e2e,
0x81b0, 0x003f2e2e,
0x81bc, 0x005b5b5b,
0x81c0, 0x005b5b5b,
0x81b4, 0x00600060,
0x81b8, 0x00600060,
0x81cc, 0x00000000,
0x81dc, 0x00000002,
0x81e0, 0x00000000,
0x81e4, 0x00000001,
0x820c, 0x33112200,
0x8210, 0x33112200,
0x8214, 0x00000000,
0x8220, 0x10010000,
0x8224, 0x00000000,
0x822c, 0x0000d000,
0x8238, 0x40000000,
0x823c, 0x40000000,
0x8240, 0x00000000,
0x8244, 0x0b040b03,
0x8248, 0x0a050b04,
0x824c, 0x0a050b04,
0x8250, 0xe4e40000,
0x8258, 0xffffffff,
0x825c, 0xffffffff,
0x8260, 0xffffffff,
0x8264, 0xffffffff,
0x8268, 0xffffffff,
0x826c, 0x1fffffff,
0x82a0, 0x00000000,
0x82ac, 0x003f2e2e,
0x82b0, 0x003f2e2e,
0x82bc, 0x005b5b5b,
0x82c0, 0x005b5b5b,
0x82b4, 0x00600060,
0x82b8, 0x00600060,
0x82cc, 0x00000000,
0x82dc, 0x00000002,
0x82e0, 0x00100000,
0x82e4, 0x00000001,
0x81d8, 0x00000001,
0x82d8, 0x00000001,
0x8d00, 0x00000000,
0x8d04, 0x00000000,
0x8d08, 0x00000000,
0x8d0c, 0x00000000,
0x8d10, 0x00000000,
0x8d14, 0x00000000,
0x8d18, 0x00000000,
0x8d1c, 0x00000000,
0x8d20, 0x00000000,
0x8d24, 0x00000000,
0x8d28, 0x00000000,
0x8d2c, 0x00000000,
0x8d30, 0x00000000,
0x8d34, 0x00000000,
0x8d38, 0x00000000,
0x8d3c, 0x00000000,
0x8d40, 0x00000000,
0x8d44, 0x00000000,
0x8d48, 0x00000000,
0x8d4c, 0x00000000,
0x8d50, 0x00000000,
0x8d54, 0x00000000,
0x8d58, 0x00000000,
0x8d5c, 0x00000000,
0x8d60, 0x00000000,
0x8d64, 0x00000000,
0x8d68, 0x00000000,
0x8d6c, 0x00000000,
0x8d70, 0x00000000,
0x8d74, 0x00000000,
0x8d78, 0x00000000,
0x8d7c, 0x00000000,
0x8d80, 0x00000000,
0x8d84, 0x00000000,
0x8d88, 0x00000000,
0x8d8c, 0x00000000,
0x8d90, 0x00000000,
0x8d94, 0x00000000,
0x8d98, 0x00000000,
0x8d9c, 0x00000000,
0x8da0, 0x00000000,
0x8da4, 0x00000000,
0x8da8, 0x00000000,
0x8dac, 0x00000000,
0x8db0, 0x00000000,
0x8db4, 0x00000000,
0x8db8, 0x00000000,
0x8dbc, 0x00000000,
0x8dc0, 0x00000000,
0x8dc4, 0x00000000,
0x8dc8, 0x00000000,
0x8dcc, 0x00000000,
0x8dd0, 0x00000000,
0x8dd4, 0x00000000,
0x8dd8, 0x00000000,
0x8ddc, 0x00000000,
0x8de0, 0x00000000,
0x8de4, 0x00000000,
0x8de8, 0x00000000,
0x8dec, 0x00000000,
0x8df0, 0x00000000,
0x8df4, 0x00000000,
0x8df8, 0x00000000,
0x8dfc, 0x00000000,
0x8e00, 0x00000000,
0x8e04, 0x00000000,
0x8e08, 0x00000000,
0x8e0c, 0x00000000,
0x8e10, 0x00000000,
0x8e14, 0x00000000,
0x8e18, 0x00000000,
0x8e1c, 0x00000000,
0x8e20, 0x00000000,
0x8e24, 0x00000000,
0x8e28, 0x00000000,
0x8e2c, 0x00000000,
0x8e30, 0x00000000,
0x8e34, 0x00000000,
0x8e38, 0x00000000,
0x8e3c, 0x00000000,
0x8e40, 0x00000000,
0x8e44, 0x00000000,
0x8e48, 0x00000000,
0x8e4c, 0x00000000,
0x8e50, 0x00000000,
0x8e54, 0x00000000,
0x8e58, 0x00000000,
0x8e5c, 0x00000000,
0x8e60, 0x00000000,
0x8e64, 0x00000000,
0x8e68, 0x00000000,
0x8e6c, 0x00000000,
0x8e70, 0x00000000,
0x8e74, 0x00000000,
0x8e78, 0x00000000,
0x8e7c, 0x00000000,
0x8e80, 0x00000000,
0x8e84, 0x00000000,
0x8e88, 0x00000000,
0x8e8c, 0x00000000,
0x8e90, 0x00000000,
0x8e94, 0x00000000,
0x8e98, 0x00000000,
0x8e9c, 0x00000000,
0x8ea0, 0x00000000,
0x8ea4, 0x00000000,
0x8ea8, 0x00000000,
0x8eac, 0x00000000,
0x8eb0, 0x00000000,
0x8eb4, 0x00000000,
0x8eb8, 0x00000000,
0x8ebc, 0x00000000,
0x8ec0, 0x00000000,
0x8ec4, 0x00000000,
0x8ec8, 0x00000000,
0x8ecc, 0x00000000,
0x8ed0, 0x00000000,
0x8ed4, 0x00000000,
0x8ed8, 0x00000000,
0x8edc, 0x00000000,
0x8ee0, 0x00000000,
0x8ee4, 0x00000000,
0x8ee8, 0x00000000,
0x8eec, 0x00000000,
0x8ef0, 0x00000000,
0x8ef4, 0x00000000,
0x8ef8, 0x00000000,
0x8efc, 0x00000000,
0x8f00, 0x00000000,
0x8f04, 0x00000000,
0x8f08, 0x00000000,
0x8f0c, 0x00000000,
0x8f10, 0x00000000,
0x8f14, 0x00000000,
0x8f18, 0x00000000,
0x8f1c, 0x00000000,
0x8f20, 0x00000000,
0x8f24, 0x00000000,
0x8f28, 0x00000000,
0x8f2c, 0x00000000,
0x8f30, 0x00000000,
0x8f34, 0x00000000,
0x8f38, 0x00000000,
0x8f3c, 0x00000000,
0x8f40, 0x00000000,
0x8f44, 0x00000000,
0x8f48, 0x00000000,
0x8f4c, 0x00000000,
0x8f50, 0x00000000,
0x8f54, 0x00000000,
0x8f58, 0x00000000,
0x8f5c, 0x00000000,
0x8f60, 0x00000000,
0x8f64, 0x00000000,
0x8f68, 0x00000000,
0x8f6c, 0x00000000,
0x8f70, 0x00000000,
0x8f74, 0x00000000,
0x8f78, 0x00000000,
0x8f7c, 0x00000000,
0x8f80, 0x00000000,
0x8f84, 0x00000000,
0x8f88, 0x00000000,
0x8f8c, 0x00000000,
0x8f90, 0x00000000,
0x8f94, 0x00000000,
0x8f98, 0x00000000,
0x8f9c, 0x00000000,
0x8fa0, 0x00000000,
0x8fa4, 0x00000000,
0x8fa8, 0x00000000,
0x8fac, 0x00000000,
0x8fb0, 0x00000000,
0x8fb4, 0x00000000,
0x8fb8, 0x00000000,
0x8fbc, 0x00000000,
0x8fc0, 0x00000000,
0x8fc4, 0x00000000,
0x8fc8, 0x00000000,
0x8fcc, 0x00000000,
0x8fd0, 0x00000000,
0x8fd4, 0x00000000,
0x8fd8, 0x00000000,
0x8fdc, 0x00000000,
0x8fe0, 0x00000000,
0x8fe4, 0x00000000,
0x8fe8, 0x00000000,
0x8fec, 0x00000000,
0x8ff0, 0x00000000,
0x8ff4, 0x00000000,
0x8ff8, 0x00000000,
0x8ffc, 0x00000000,
0x9000, 0x00000000,
0x9004, 0x00000000,
0x9008, 0x00000000,
0x900c, 0x00000000,
0x9010, 0x00000000,
0x9014, 0x00000000,
0x9018, 0x00000000,
0x901c, 0x00000000,
0x9020, 0x00000000,
0x9024, 0x00000000,
0x9028, 0x00000000,
0x902c, 0x00000000,
0x9030, 0x00000000,
0x9034, 0x00000000,
0x9038, 0x00000000,
0x903c, 0x00000000,
0x9040, 0x00000000,
0x9044, 0x00000000,
0x9048, 0x00000000,
0x904c, 0x00000000,
0x9050, 0x00000000,
0x9054, 0x00000000,
0x9058, 0x00000000,
0x905c, 0x00000000,
0x9060, 0x00000000,
0x9064, 0x00000000,
0x9068, 0x00000000,
0x906c, 0x00000000,
0x9070, 0x00000000,
0x9074, 0x00000000,
0x9078, 0x00000000,
0x907c, 0x00000000,
0x9080, 0x00000000,
0x9084, 0x00000000,
0x9088, 0x00000000,
0x908c, 0x00000000,
0x9090, 0x00000000,
0x9094, 0x00000000,
0x9098, 0x00000000,
0x909c, 0x00000000,
0x90a0, 0x00000000,
0x90a4, 0x00000000,
0x90a8, 0x00000000,
0x90ac, 0x00000000,
0x90b0, 0x00000000,
0x90b4, 0x00000000,
0x90b8, 0x00000000,
0x90bc, 0x00000000,
0x9100, 0x00000000,
0x9104, 0x00000000,
0x9108, 0x00000000,
0x910c, 0x00000000,
0x9110, 0x00000000,
0x9114, 0x00000000,
0x9118, 0x00000000,
0x911c, 0x00000000,
0x9120, 0x00000000,
0x9124, 0x00000000,
0x9128, 0x00000000,
0x912c, 0x00000000,
0x9130, 0x00000000,
0x9134, 0x00000000,
0x9138, 0x00000000,
0x913c, 0x00000000,
0x9140, 0x00000000,
0x9144, 0x00000000,
0x9148, 0x00000000,
0x914c, 0x00000000,
0x9150, 0x00000000,
0x9154, 0x00000000,
0x9158, 0x00000000,
0x915c, 0x00000000,
0x9160, 0x00000000,
0x9164, 0x00000000,
0x9168, 0x00000000,
0x916c, 0x00000000,
0x9170, 0x00000000,
0x9174, 0x00000000,
0x9178, 0x00000000,
0x917c, 0x00000000,
0x9180, 0x00000000,
0x9184, 0x00000000,
0x9188, 0x00000000,
0x918c, 0x00000000,
0x9190, 0x00000000,
0x9194, 0x00000000,
0x9198, 0x00000000,
0x919c, 0x00000000,
0x91a0, 0x00000000,
0x91a4, 0x00000000,
0x91a8, 0x00000000,
0x91ac, 0x00000000,
0x91b0, 0x00000000,
0x91b4, 0x00000000,
0x91b8, 0x00000000,
0x91bc, 0x00000000,
0x91c0, 0x00000000,
0x91c4, 0x00000000,
0x91c8, 0x00000000,
0x91cc, 0x00000000,
0x91d0, 0x00000000,
0x91d4, 0x00000000,
0x91d8, 0x00000000,
0x91dc, 0x00000000,
0x91e0, 0x00000000,
0x91e4, 0x00000000,
0x91e8, 0x00000000,
0x91ec, 0x00000000,
0x91f0, 0x00000000,
0x91f4, 0x00000000,
0x91f8, 0x00000000,
0x91fc, 0x00000000,
0x9200, 0x00000000,
0x9204, 0x00000000,
0x9208, 0x00000000,
0x920c, 0x00000000,
0x9210, 0x00000000,
0x9214, 0x00000000,
0x9218, 0x00000000,
0x921c, 0x00000000,
0x9220, 0x00000000,
0x9224, 0x00000000,
0x9228, 0x00000000,
0x922c, 0x00000000,
0x9230, 0x00000000,
0x9234, 0x00000000,
0x9238, 0x00000000,
0x923c, 0x00000000,
0x9240, 0x00000000,
0x9244, 0x00000000,
0x9248, 0x00000000,
0x924c, 0x00000000,
0x9250, 0x00000000,
0x9254, 0x00000000,
0x9258, 0x00000000,
0x925c, 0x00000000,
0x9260, 0x00000000,
0x9264, 0x00000000,
0x9268, 0x00000000,
0x926c, 0x00000000,
0x9270, 0x00000000,
0x9274, 0x00000000,
0x9278, 0x00000000,
0x927c, 0x00000000,
0x9280, 0x00000000,
0x9284, 0x00000000,
0x9288, 0x00000000,
0x928c, 0x00000000,
0x9290, 0x00000000,
0x9294, 0x00000000,
0x9298, 0x00000000,
0x929c, 0x00000000,
0x92a0, 0x00000000,
0x92a4, 0x00000000,
0x92a8, 0x00000000,
0x92ac, 0x00000000,
0x92b0, 0x00000000,
0x92b4, 0x00000000,
0x92b8, 0x00000000,
0x92bc, 0x00000000,
0x92c0, 0x00000000,
0x92c4, 0x00000000,
0x92c8, 0x00000000,
0x92cc, 0x00000000,
0x92d0, 0x00000000,
0x92d4, 0x00000000,
0x92d8, 0x00000000,
0x92dc, 0x00000000,
0x92e0, 0x00000000,
0x92e4, 0x00000000,
0x92e8, 0x00000000,
0x92ec, 0x00000000,
0x92f0, 0x00000000,
0x92f4, 0x00000000,
0x92f8, 0x00000000,
0x92fc, 0x00000000,
0x9300, 0x00000000,
0x9304, 0x00000000,
0x9308, 0x00000000,
0x930c, 0x00000000,
0x9310, 0x00000000,
0x9314, 0x00000000,
0x9318, 0x00000000,
0x931c, 0x00000000,
0x9320, 0x00000000,
0x9324, 0x00000000,
0x9328, 0x00000000,
0x932c, 0x00000000,
0x9330, 0x00000000,
0x9334, 0x00000000,
0x9338, 0x00000000,
0x933c, 0x00000000,
0x9340, 0x00000000,
0x9344, 0x00000000,
0x9348, 0x00000000,
0x934c, 0x00000000,
0x9350, 0x00000000,
0x9354, 0x00000000,
0x9358, 0x00000000,
0x935c, 0x00000000,
0x9360, 0x00000000,
0x9364, 0x00000000,
0x9368, 0x00000000,
0x936c, 0x00000000,
0x9370, 0x00000000,
0x9374, 0x00000000,
0x9378, 0x00000000,
0x937c, 0x00000000,
0x9380, 0x00000000,
0x9384, 0x00000000,
0x9388, 0x00000000,
0x938c, 0x00000000,
0x9390, 0x00000000,
0x9394, 0x00000000,
0x9398, 0x00000000,
0x939c, 0x00000000,
0x93a0, 0x00000000,
0x93a4, 0x00000000,
0x93a8, 0x00000000,
0x93ac, 0x00000000,
0x93b0, 0x00000000,
0x93b4, 0x00000000,
0x93b8, 0x00000000,
0x93bc, 0x00000000,
0x93c0, 0x00000000,
0x93c4, 0x00000000,
0x93c8, 0x00000000,
0x93cc, 0x00000000,
0x93d0, 0x00000000,
0x93d4, 0x00000000,
0x93d8, 0x00000000,
0x93dc, 0x00000000,
0x93e0, 0x00000000,
0x93e4, 0x00000000,
0x93e8, 0x00000000,
0x93ec, 0x00000000,
0x93f0, 0x00000000,
0x93f4, 0x00000000,
0x93f8, 0x00000000,
0x93fc, 0x00000000,
0x9400, 0x00000000,
0x9404, 0x00000000,
0x9408, 0x00000000,
0x940c, 0x00000000,
0x9410, 0x00000000,
0x9414, 0x00000000,
0x9418, 0x00000000,
0x941c, 0x00000000,
0x9420, 0x00000000,
0x9424, 0x00000000,
0x9428, 0x00000000,
0x942c, 0x00000000,
0x9430, 0x00000000,
0x9434, 0x00000000,
0x9438, 0x00000000,
0x943c, 0x00000000,
0x9440, 0x00000000,
0x9444, 0x00000000,
0x9448, 0x00000000,
0x944c, 0x00000000,
0x9450, 0x00000000,
0x9454, 0x00000000,
0x9458, 0x00000000,
0x945c, 0x00000000,
0x9460, 0x00000000,
0x9464, 0x00000000,
0x9468, 0x00000000,
0x946c, 0x00000000,
0x9470, 0x00000000,
0x9474, 0x00000000,
0x9478, 0x00000000,
0x947c, 0x00000000,
0x9480, 0x00000000,
0x9484, 0x00000000,
0x9488, 0x00000000,
0x948c, 0x00000000,
0x9490, 0x00000000,
0x9494, 0x00000000,
0x9498, 0x00000000,
0x949c, 0x00000000,
0x94a0, 0x00000000,
0x94a4, 0x00000000,
0x94a8, 0x00000000,
0x94ac, 0x00000000,
0x94b0, 0x00000000,
0x94b4, 0x00000000,
0x94b8, 0x00000000,
0x94bc, 0x00000000,
0xa220, 0x00000000,
0xa224, 0x00000000,
0xa228, 0x00000000,
0xa22c, 0x00000000,
0xa230, 0x00000000,
0xa234, 0x00000000,
0xa238, 0x00000000,
0xa23c, 0x00000000,
0xa240, 0x00000000,
0xa244, 0x00000000,
0xa248, 0x00000000,
0xa24c, 0x00000000,
0xa250, 0x00000000,
0xa254, 0x00000000,
0xa258, 0x00000000,
0xa25c, 0x00000000,
0xa260, 0x00000000,
0xa264, 0x00000000,
0xa268, 0x00000000,
0xa26c, 0x00000000,
0xa270, 0x00000000,
0xa274, 0x00000000,
0xa278, 0x00000000,
0xa27c, 0x00000000,
0xa280, 0x00000000,
0xa284, 0x00000000,
0xa288, 0x00000000,
0xa28c, 0x00000000,
0xa290, 0x00000000,
0xa294, 0x00000000,
0xa298, 0x00000000,
0xa29c, 0x00000000,
0xa2a0, 0x00000000,
0xa2a4, 0x00000000,
0xa2a8, 0x00000000,
0xa2ac, 0x00000000,
0xa2b0, 0x00000000,
0xa2b4, 0x00000000,
0xa2b8, 0x00000000,
0xa2bc, 0x00000000,
0xa2c0, 0x00000000,
0xa2c4, 0x00000000,
0xa2c8, 0x00000000,
0xa2cc, 0x00000000,
0xa2d0, 0x00000000,
0xa2d4, 0x00000000,
0xa2d8, 0x00000000,
0xa2dc, 0x00000000,
0xa2e0, 0x00000000,
0xa2e4, 0x00000000,
0xa2e8, 0x00000000,
0xa2ec, 0x00000000,
0xa2f0, 0x00000000,
0xa2f4, 0x00000000,
0xa2f8, 0x00000000,
0xa2fc, 0x00000000,
0xa300, 0x00000000,
0xa304, 0x00000000,
0xa308, 0x00000000,
0xa30c, 0x00000000,
0xa310, 0x00000000,
0xa314, 0x00000000,
0xa318, 0x00000000,
0xa31c, 0x00000000,
0xa320, 0x00000000,
0xa324, 0x00000000,
0xa328, 0x00000000,
0xa32c, 0x00000000,
0xa330, 0x00000000,
0xa334, 0x00000000,
0xa338, 0x00000000,
0xa33c, 0x00000000,
0xa340, 0x00000000,
0xa344, 0x00000000,
0xa348, 0x00000000,
0xa34c, 0x00000000,
0xa350, 0x00000000,
0xa354, 0x00000000,
0xa358, 0x00000000,
0xa35c, 0x00000000,
0xa360, 0x00000000,
0xa364, 0x00000000,
0xa368, 0x00000000,
0xa36c, 0x00000000,
0xa370, 0x00000000,
0xa374, 0x00000000,
0xa378, 0x00000000,
0xa37c, 0x00000000,
0xa380, 0x00000000,
0xa384, 0x00000000,
0xa388, 0x00000000,
0xa38c, 0x00000000,
0xa390, 0x00000000,
0xa394, 0x00000000,
0xa398, 0x00000000,
0xa39c, 0x00000000,
0xa3a0, 0x00000000,
0xa3a4, 0x00000000,
0xa3a8, 0x00000000,
0xa3ac, 0x00000000,
0xa3b0, 0x00000000,
0xa3b4, 0x00000000,
0xa3b8, 0x00000000,
0xa3bc, 0x00000000,
0xa620, 0x00000000,
0xa624, 0x00000000,
0xa628, 0x00000000,
0xa62c, 0x00000000,
0xa630, 0x00000000,
0xa634, 0x00000000,
0xa638, 0x00000000,
0xa63c, 0x00000000,
0xa640, 0x00000000,
0xa644, 0x00000000,
0xa648, 0x00000000,
0xa64c, 0x00000000,
0xa650, 0x00000000,
0xa654, 0x00000000,
0xa658, 0x00000000,
0xa65c, 0x00000000,
0xa660, 0x00000000,
0xa664, 0x00000000,
0xa668, 0x00000000,
0xa66c, 0x00000000,
0xa670, 0x00000000,
0xa674, 0x00000000,
0xa678, 0x00000000,
0xa67c, 0x00000000,
0xa680, 0x00000000,
0xa684, 0x00000000,
0xa688, 0x00000000,
0xa68c, 0x00000000,
0xa690, 0x00000000,
0xa694, 0x00000000,
0xa698, 0x00000000,
0xa69c, 0x00000000,
0xa6a0, 0x00000000,
0xa6a4, 0x00000000,
0xa6a8, 0x00000000,
0xa6ac, 0x00000000,
0xa6b0, 0x00000000,
0xa6b4, 0x00000000,
0xa6b8, 0x00000000,
0xa6bc, 0x00000000,
0xa6c0, 0x00000000,
0xa6c4, 0x00000000,
0xa6c8, 0x00000000,
0xa6cc, 0x00000000,
0xa6d0, 0x00000000,
0xa6d4, 0x00000000,
0xa6d8, 0x00000000,
0xa6dc, 0x00000000,
0xa6e0, 0x00000000,
0xa6e4, 0x00000000,
0xa6e8, 0x00000000,
0xa6ec, 0x00000000,
0xa6f0, 0x00000000,
0xa6f4, 0x00000000,
0xa6f8, 0x00000000,
0xa6fc, 0x00000000,
0xa700, 0x00000000,
0xa704, 0x00000000,
0xa708, 0x00000000,
0xa70c, 0x00000000,
0xa710, 0x00000000,
0xa714, 0x00000000,
0xa718, 0x00000000,
0xa71c, 0x00000000,
0xa720, 0x00000000,
0xa724, 0x00000000,
0xa728, 0x00000000,
0xa72c, 0x00000000,
0xa730, 0x00000000,
0xa734, 0x00000000,
0xa738, 0x00000000,
0xa73c, 0x00000000,
0xa740, 0x00000000,
0xa744, 0x00000000,
0xa748, 0x00000000,
0xa74c, 0x00000000,
0xa750, 0x00000000,
0xa754, 0x00000000,
0xa758, 0x00000000,
0xa75c, 0x00000000,
0xa760, 0x00000000,
0xa764, 0x00000000,
0xa768, 0x00000000,
0xa76c, 0x00000000,
0xa770, 0x00000000,
0xa774, 0x00000000,
0xa778, 0x00000000,
0xa77c, 0x00000000,
0xa780, 0x00000000,
0xa784, 0x00000000,
0xa788, 0x00000000,
0xa78c, 0x00000000,
0xa790, 0x00000000,
0xa794, 0x00000000,
0xa798, 0x00000000,
0xa79c, 0x00000000,
0xa7a0, 0x00000000,
0xa7a4, 0x00000000,
0xa7a8, 0x00000000,
0xa7ac, 0x00000000,
0xa7b0, 0x00000000,
0xa7b4, 0x00000000,
0xa7b8, 0x00000000,
0xa7bc, 0x00000000,
0x81d8, 0x00000000,
0x82d8, 0x00000000,
0x9f04, 0x2b251f19,
0x9f08, 0x433d3731,
0x9f0c, 0x5b554f49,
0x9f10, 0x736d6761,
0x9f14, 0x7f7f7f79,
0x9f18, 0x120f7f7f,
0x9f1c, 0x1e1b1815,
0x9f20, 0x2a272421,
0x9f24, 0x3633302d,
0x9f28, 0x3f3f3c39,
0x9f2c, 0x3f3f3f3f,
0x8008, 0x00000080,
0x8088, 0x807f030a,
0x80c8, 0x708f0bf1,
0x80c8, 0x708e0aa5,
0x80c8, 0x708d097d,
0x80c8, 0x708c0875,
0x80c8, 0x708b0789,
0x80c8, 0x708a06b7,
0x80c8, 0x708905fc,
0x80c8, 0x70880556,
0x80c8, 0x708704c1,
0x80c8, 0x7086043d,
0x80c8, 0x708503c7,
0x80c8, 0x7084035e,
0x80c8, 0x708302ac,
0x80c8, 0x70820262,
0x80c8, 0x70810220,
0x80c8, 0x70800000,
0x80c8, 0x7090011f,
0x80c8, 0x7010011f,
0x8088, 0x80000000,
0x8008, 0x00000000,
//_Init1_nctl_52B_rm_DPKPreset_0x808c_20210511_wlab
0x8088, 0x00000110,
0x8000, 0x00000008,
0x8080, 0x00000005,
0x8500, 0x80000008,
0x8504, 0x43000004,
0x8508, 0x4b044a00,
0x850c, 0x40098604,
0x8510, 0x0004e020,
0x8514, 0x87044b05,
0x8518, 0xe020400b,
0x851c, 0x4b000004,
0x8520, 0x21e07410,
0x8524, 0x74300000,
0x8528, 0x43800004,
0x852c, 0x4c000007,
0x8530, 0x43000004,
0x8534, 0x42fe5700,
0x8538, 0x42004000,
0x853c, 0x30005055,
0x8540, 0xa50fb41a,
0x8544, 0xf11ce3c7,
0x8548, 0xf31cf21c,
0x854c, 0xf61cf41c,
0x8550, 0xf91cf81c,
0x8554, 0xfb1cfa1c,
0x8558, 0xfd1cfc1c,
0x855c, 0xff1cfe1c,
0x8560, 0xf11cf01c,
0x8564, 0xf31cf21c,
0x8568, 0xf51cf41c,
0x856c, 0xf71cf61c,
0x8570, 0xf91cf81c,
0x8574, 0xe3c7a504,
0x8578, 0xf11af01a,
0x857c, 0x30580001,
0x8580, 0x30b030c9,
0x8584, 0x30ff30fc,
0x8588, 0x310f3102,
0x858c, 0x3148311c,
0x8590, 0x31603158,
0x8594, 0x30c7320e,
0x8598, 0x32293225,
0x859c, 0x32433242,
0x85a0, 0x3286327a,
0x85a4, 0x329d328a,
0x85a8, 0x32aa32a8,
0x85ac, 0x320331c5,
0x85b0, 0x7410e2c1,
0x85b4, 0x020020a8,
0x85b8, 0x2098140f,
0x85bc, 0x140f0200,
0x85c0, 0x02002088,
0x85c4, 0x7430140f,
0x85c8, 0x5b10e31c,
0x85cc, 0x20a87410,
0x85d0, 0x140f0201,
0x85d4, 0x00002080,
0x85d8, 0x5507140f,
0x85dc, 0x5c065661,
0x85e0, 0x7410e308,
0x85e4, 0x02002088,
0x85e8, 0x5517140f,
0x85ec, 0x7410e308,
0x85f0, 0x020020a8,
0x85f4, 0x5517140f,
0x85f8, 0x5c025641,
0x85fc, 0x7410e308,
0x8600, 0x00002080,
0x8604, 0x1407140f,
0x8608, 0xe3085507,
0x860c, 0x7508e2b4,
0x8610, 0xe312468e,
0x8614, 0x5b10e0f4,
0x8618, 0x20a87410,
0x861c, 0x140f0201,
0x8620, 0x00002090,
0x8624, 0x5507140f,
0x8628, 0x5c065661,
0x862c, 0x7410e308,
0x8630, 0x02002098,
0x8634, 0x5517140f,
0x8638, 0x7410e308,
0x863c, 0x020020a8,
0x8640, 0x5517140f,
0x8644, 0x5c025641,
0x8648, 0x7410e308,
0x864c, 0x00002090,
0x8650, 0x5507140f,
0x8654, 0x7509e308,
0x8658, 0xe3124696,
0x865c, 0x0001e0f4,
0x8660, 0x74105b10,
0x8664, 0x000020a0,
0x8668, 0x5507140f,
0x866c, 0xe3085601,
0x8670, 0x20a87410,
0x8674, 0x140f0200,
0x8678, 0xe3085517,
0x867c, 0x750ae2b4,
0x8680, 0xe3124686,
0x8684, 0x5500e0f4,
0x8688, 0x5501e304,
0x868c, 0xe2c10001,
0x8690, 0x5b10e31c,
0x8694, 0x20807410,
0x8698, 0x140f0000,
0x869c, 0x02002098,
0x86a0, 0xf204140f,
0x86a4, 0x020020a8,
0x86a8, 0x5507140f,
0x86ac, 0xe3085601,
0x86b0, 0x20887410,
0x86b4, 0x140f0200,
0x86b8, 0xe3085517,
0x86bc, 0x7508e2b4,
0x86c0, 0xe312468e,
0x86c4, 0x7410e0f4,
0x86c8, 0x00002090,
0x86cc, 0x5507140f,
0x86d0, 0x7410e308,
0x86d4, 0x02002098,
0x86d8, 0x5517140f,
0x86dc, 0x7509e308,
0x86e0, 0xe3124696,
0x86e4, 0x0001e0f4,
0x86e8, 0x74207900,
0x86ec, 0x57005710,
0x86f0, 0x9700140f,
0x86f4, 0x00017430,
0x86f8, 0xe31ce2c1,
0x86fc, 0xe2ca0001,
0x8700, 0x0001e34b,
0x8704, 0x312ae2c1,
0x8708, 0xe3ba0023,
0x870c, 0x54ed0002,
0x8710, 0x00230baa,
0x8714, 0x0002e3ba,
0x8718, 0xe2b9e367,
0x871c, 0xe2c10001,
0x8720, 0x00223125,
0x8724, 0x0002e3ba,
0x8728, 0x0baa54ec,
0x872c, 0xe3ba0022,
0x8730, 0xe3670002,
0x8734, 0x0001e2b9,
0x8738, 0x0baae2c1,
0x873c, 0x6d0f6c67,
0x8740, 0xe3bae31c,
0x8744, 0xe31c6c8b,
0x8748, 0x0bace3ba,
0x874c, 0x6d0f6cb3,
0x8750, 0xe3bae31c,
0x8754, 0x6cdb0bad,
0x8758, 0xe31c6d0f,
0x875c, 0x6cf7e3ba,
0x8760, 0xe31c6d0f,
0x8764, 0x6c09e3ba,
0x8768, 0xe31c6d00,
0x876c, 0x6c25e3ba,
0x8770, 0xe3bae31c,
0x8774, 0x6c4df8ca,
0x8778, 0xe3bae31c,
0x877c, 0x6c75f9d3,
0x8780, 0xe3bae31c,
0x8784, 0xe31c6c99,
0x8788, 0xe367e3ba,
0x878c, 0x0001e2b9,
0x8790, 0x4380e2ca,
0x8794, 0x43006344,
0x8798, 0x00223188,
0x879c, 0x0002e3bf,
0x87a0, 0x0baa54ec,
0x87a4, 0xe3bf0022,
0x87a8, 0xe3670002,
0x87ac, 0x0001e2c5,
0x87b0, 0x4380e2ca,
0x87b4, 0x43006344,
0x87b8, 0xe367317b,
0x87bc, 0x0001e2c5,
0x87c0, 0x4380e2ca,
0x87c4, 0x4300634d,
0x87c8, 0x74100ba6,
0x87cc, 0x000921e8,
0x87d0, 0x6f0f6e67,
0x87d4, 0xe3bfe34b,
0x87d8, 0x000a21e8,
0x87dc, 0xe34b6e77,
0x87e0, 0x21e8e3bf,
0x87e4, 0x6e8b000b,
0x87e8, 0xe3bfe34b,
0x87ec, 0x000c21e8,
0x87f0, 0xe34b6e9f,
0x87f4, 0x0baae3bf,
0x87f8, 0x21e87410,
0x87fc, 0x6eb3000d,
0x8800, 0xe34b6f0f,
0x8804, 0x21e8e3bf,
0x8808, 0x6ec7000e,
0x880c, 0xe3bfe34b,
0x8810, 0x74100bac,
0x8814, 0x000f21e8,
0x8818, 0x6f0f6edb,
0x881c, 0xe3bfe34b,
0x8820, 0x001021e8,
0x8824, 0xe34b6eef,
0x8828, 0xe3bfe3bf,
0x882c, 0x001321e8,
0x8830, 0x6f006e11,
0x8834, 0xe3bfe34b,
0x8838, 0x21e8e3bf,
0x883c, 0x6e250014,
0x8840, 0xe3bfe34b,
0x8844, 0x21e8fbab,
0x8848, 0x6e390015,
0x884c, 0xe3bfe34b,
0x8850, 0x001621e8,
0x8854, 0xe34b6e4d,
0x8858, 0xfcb0e3bf,
0x885c, 0x001721e8,
0x8860, 0xe34b6e61,
0x8864, 0x21e8e3bf,
0x8868, 0x6e750018,
0x886c, 0xe3bfe34b,
0x8870, 0x001921e8,
0x8874, 0xe34b6e89,
0x8878, 0x21e8e3bf,
0x887c, 0x6e99001a,
0x8880, 0xe3bfe34b,
0x8884, 0xe2c5e367,
0x8888, 0x00040001,
0x888c, 0x42fc0004,
0x8890, 0x60010007,
0x8894, 0x42000004,
0x8898, 0x62200007,
0x889c, 0x00046200,
0x88a0, 0x5b005501,
0x88a4, 0x5b40e304,
0x88a8, 0x00076605,
0x88ac, 0x63006200,
0x88b0, 0x0004e388,
0x88b4, 0x0a010900,
0x88b8, 0x0d000b40,
0x88bc, 0x00320e01,
0x88c0, 0x95090004,
0x88c4, 0x790442fb,
0x88c8, 0x43804200,
0x88cc, 0x4d010007,
0x88d0, 0x43000004,
0x88d4, 0x05620007,
0x88d8, 0x961d05a3,
0x88dc, 0x0004e388,
0x88e0, 0x0007e304,
0x88e4, 0x07a306a2,
0x88e8, 0x0004e388,
0x88ec, 0xe378e304,
0x88f0, 0xe3800002,
0x88f4, 0x00074380,
0x88f8, 0x00044d00,
0x88fc, 0x42fe4300,
0x8900, 0x42007900,
0x8904, 0x00040001,
0x8908, 0x000742fc,
0x890c, 0x00046003,
0x8910, 0x31cc4200,
0x8914, 0x06a20007,
0x8918, 0x31f807a3,
0x891c, 0x77000005,
0x8920, 0x52000007,
0x8924, 0x42fe0004,
0x8928, 0x60000007,
0x892c, 0x42000004,
0x8930, 0x60004380,
0x8934, 0x62016100,
0x8938, 0x00056310,
0x893c, 0x55004100,
0x8940, 0x5c020007,
0x8944, 0x43000004,
0x8948, 0xe2d70001,
0x894c, 0x73000005,
0x8950, 0xe2d70001,
0x8954, 0x5d000006,
0x8958, 0x42f70004,
0x895c, 0x6c000005,
0x8960, 0x42000004,
0x8964, 0x0004e2de,
0x8968, 0x00074380,
0x896c, 0x4a004e00,
0x8970, 0x00064c00,
0x8974, 0x60007f00,
0x8978, 0x00046f00,
0x897c, 0x00054300,
0x8980, 0x00017300,
0x8984, 0xe2d70001,
0x8988, 0x5d010006,
0x898c, 0x61006002,
0x8990, 0x00055601,
0x8994, 0xe2e27710,
0x8998, 0x73000005,
0x899c, 0x43800004,
0x89a0, 0x5e010007,
0x89a4, 0x4d205e00,
0x89a8, 0x4a084e20,
0x89ac, 0x4c3f4960,
0x89b0, 0x00064301,
0x89b4, 0x63807f01,
0x89b8, 0x00046010,
0x89bc, 0x00064300,
0x89c0, 0x00077402,
0x89c4, 0x40004001,
0x89c8, 0x0006ab00,
0x89cc, 0x00077404,
0x89d0, 0x40004001,
0x89d4, 0x0004ab00,
0x89d8, 0x00074380,
0x89dc, 0x4e004d00,
0x89e0, 0x4c004a00,
0x89e4, 0x00064300,
0x89e8, 0x63007f00,
0x89ec, 0x00046000,
0x89f0, 0x00014300,
0x89f4, 0x73800005,
0x89f8, 0x42fe0004,
0x89fc, 0x6c010005,
0x8a00, 0x000514c8,
0x8a04, 0x00046c00,
0x8a08, 0x00014200,
0x8a0c, 0x0005e2ce,
0x8a10, 0x00017300,
0x8a14, 0x00040006,
0x8a18, 0x42fa4380,
0x8a1c, 0x42007c05,
0x8a20, 0x7c5b0006,
0x8a24, 0x7e5b7d5b,
0x8a28, 0x00077f00,
0x8a2c, 0x415b405b,
0x8a30, 0x4300425b,
0x8a34, 0x43000004,
0x8a38, 0x00040001,
0x8a3c, 0x60004380,
0x8a40, 0x62016100,
0x8a44, 0x42fa6310,
0x8a48, 0x42007c00,
0x8a4c, 0x00014300,
0x8a50, 0x0001e2e5,
0x8a54, 0x55000007,
0x8a58, 0x74200004,
0x8a5c, 0x79017711,
0x8a60, 0x57005710,
0x8a64, 0x00019700,
0x8a68, 0x4e004f02,
0x8a6c, 0x52015302,
0x8a70, 0x43800001,
0x8a74, 0x78006505,
0x8a78, 0x7a007900,
0x8a7c, 0x43007b00,
0x8a80, 0x43800001,
0x8a84, 0x43006500,
0x8a88, 0x43800001,
0x8a8c, 0x7c006405,
0x8a90, 0x00014300,
0x8a94, 0x64004380,
0x8a98, 0x00014300,
0x8a9c, 0x74200004,
0x8aa0, 0x0005e392,
0x8aa4, 0x73807388,
0x8aa8, 0xe3a08f00,
0x8aac, 0xe3920001,
0x8ab0, 0x73810005,
0x8ab4, 0x93007380,
0x8ab8, 0x0001e3a0,
0x8abc, 0xe2e5e3a7,
0x8ac0, 0x0001e3ae,
0x8ac4, 0xe3aee3a7,
0x8ac8, 0x00040001,
0x8acc, 0x24207410,
0x8ad0, 0x14c80000,
0x8ad4, 0x00002428,
0x8ad8, 0x1a4215f4,
0x8adc, 0x74300008,
0x8ae0, 0x43800001,
0x8ae4, 0x7a907b48,
0x8ae8, 0x78027900,
0x8aec, 0x55034300,
0x8af0, 0x43803308,
0x8af4, 0x7a807b38,
0x8af8, 0x55134300,
0x8afc, 0x43803308,
0x8b00, 0x7a007b40,
0x8b04, 0x55234300,
0x8b08, 0x74007401,
0x8b0c, 0x00018e00,
0x8b10, 0x52300007,
0x8b14, 0x74310004,
0x8b18, 0x8e007430,
0x8b1c, 0x52200007,
0x8b20, 0x00010004,
0x8b24, 0x57005702,
0x8b28, 0x00018e00,
0x8b2c, 0x561042ef,
0x8b30, 0x42005600,
0x8b34, 0x00018c00,
0x8b38, 0x4e004f78,
0x8b3c, 0x52015388,
0x8b40, 0xe32b5b20,
0x8b44, 0x54005480,
0x8b48, 0x54005481,
0x8b4c, 0x54005482,
0x8b50, 0xbf1de336,
0x8b54, 0xe2f13010,
0x8b58, 0xe2ffe2f9,
0x8b5c, 0xe3b3e312,
0x8b60, 0xe3085523,
0x8b64, 0xe3125525,
0x8b68, 0x0001e3b3,
0x8b6c, 0x54c054bf,
0x8b70, 0x54c154a3,
0x8b74, 0x4c1854a4,
0x8b78, 0x54c2bf07,
0x8b7c, 0xbf0454a4,
0x8b80, 0x54a354c1,
0x8b84, 0xe3c4bf01,
0x8b88, 0x000154df,
0x8b8c, 0x54e554bf,
0x8b90, 0x54df050a,
0x8b94, 0x16570001,
0x8b98, 0x74307b80,
0x8b9c, 0x7f404380,
0x8ba0, 0x7d007e00,
0x8ba4, 0x43007c02,
0x8ba8, 0x55015b40,
0x8bac, 0xe3165c01,
0x8bb0, 0x54005480,
0x8bb4, 0x54005481,
0x8bb8, 0x54005482,
0x8bbc, 0x74107b00,
0x8bc0, 0xbfe5e336,
0x8bc4, 0x56103010,
0x8bc8, 0x8c005600,
0x8bcc, 0x57040001,
0x8bd0, 0x8e005700,
0x8bd4, 0x57005708,
0x8bd8, 0x57818e00,
0x8bdc, 0x8e005780,
0x8be0, 0x00074380,
0x8be4, 0x5c005c01,
0x8be8, 0x00041403,
0x8bec, 0x00014300,
0x8bf0, 0x0007427f,
0x8bf4, 0x62006280,
0x8bf8, 0x00049200,
0x8bfc, 0x00014200,
0x8c00, 0x0007427f,
0x8c04, 0x63146394,
0x8c08, 0x00049200,
0x8c0c, 0x00014200,
0x8c10, 0x42fe0004,
0x8c14, 0x42007901,
0x8c18, 0x14037420,
0x8c1c, 0x57005710,
0x8c20, 0x0001140f,
0x8c24, 0x56010006,
0x8c28, 0x54005502,
0x8c2c, 0x7f000005,
0x8c30, 0x77107e12,
0x8c34, 0x75007600,
0x8c38, 0x00047400,
0x8c3c, 0x00014270,
0x8c40, 0x42000004,
0x8c44, 0x77000005,
0x8c48, 0x56000006,
0x8c4c, 0x00060001,
0x8c50, 0x5f005f80,
0x8c54, 0x00059900,
0x8c58, 0x00017300,
0x8c5c, 0x63800006,
0x8c60, 0x98006300,
0x8c64, 0x549f0001,
0x8c68, 0x5c015400,
0x8c6c, 0x540054df,
0x8c70, 0x00015c02,
0x8c74, 0x07145c01,
0x8c78, 0x5c025400,
0x8c7c, 0x5c020001,
0x8c80, 0x54000714,
0x8c84, 0x00015c01,
0x8c88, 0x4c184c98,
0x8c8c, 0x00040001,
0x8c90, 0x74305c02,
0x8c94, 0x0c010901,
0x8c98, 0x00050ba6,
0x8c9c, 0x00077780,
0x8ca0, 0x00045220,
0x8ca4, 0x60084380,
0x8ca8, 0x6200610a,
0x8cac, 0x000763ce,
0x8cb0, 0x00045c00,
0x8cb4, 0x00014300,
0x8080, 0x00000004,
0x8080, 0x00000000,
0x8088, 0x00000000,
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_nctl_raw_data_8852b.h
|
C
|
agpl-3.0
| 28,923
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 2.0.1.6*/
#ifndef _HALRF_HWIMG_RAW_DATA_8852B_H
#define _HALRF_HWIMG_RAW_DATA_8852B_H
#define D_S_SIZE DELTA_SWINGIDX_SIZE
#define D_ST_SIZE DELTA_SWINTSSI_SIZE
#if 0
/* Please put following enum definitions in appropriate header file. */
enum odm_pw_byrate_para_type {
PW_BYRATE_PARA_NSS1,
PW_BYRATE_PARA_NSS2,
PW_BYRATE_PARA_OFFS = 0xF
};
enum odm_pw_byrate_rate_type {
PW_BYRATE_RATE_11M_1M,
PW_BYRATE_RATE_18M_6M,
PW_BYRATE_RATE_54M_24M,
PW_BYRATE_RATE_MCS3_0,
PW_BYRATE_RATE_MCS7_4,
PW_BYRATE_RATE_MCS11_8,
PW_BYRATE_RATE_DCM4_0,
PW_BYRATE_RATE_AllRate2_1, /* CCK, OFDM, HT, VHT */
PW_BYRATE_RATE_AllRate2_2, /* HE_HEDCM */
PW_BYRATE_RATE_AllRate5_1, /* OFDM, HT, VHT, HE_HEDCM */
PW_BYRATE_RATE_NULL = 0xF
};
enum odm_pw_lmt_regulation_type {
PW_LMT_REGU_FCC,
PW_LMT_REGU_ETSI,
PW_LMT_REGU_MKK,
PW_LMT_REGU_IC,
PW_LMT_REGU_KCC,
PW_LMT_REGU_ACMA,
PW_LMT_REGU_CHILE,
PW_LMT_REGU_UKRAINE,
PW_LMT_REGU_MEXICO,
PW_LMT_REGU_CN,
PW_LMT_REGU_WW13,
PW_LMT_REGU_NULL
};
enum odm_pw_lmt_band_type {
PW_LMT_BAND_2_4G,
PW_LMT_BAND_5G,
PW_LMT_BAND_NULL
};
enum odm_pw_lmt_bandwidth_type {
PW_LMT_BW_20M,
PW_LMT_BW_40M,
PW_LMT_BW_80M,
PW_LMT_BW_NULL
};
enum odm_pw_lmt_ru_bandwidth_type {
PW_LMT_RU_BW_RU26,
PW_LMT_RU_BW_RU52,
PW_LMT_RU_BW_RU106,
PW_LMT_RU_BW_NULL
};
enum odm_pw_lmt_ratesection_type {
PW_LMT_RS_CCK,
PW_LMT_RS_OFDM,
PW_LMT_RS_HT,
PW_LMT_RS_VHT,
PW_LMT_RS_HE,
PW_LMT_RS_NULL
};
enum odm_pw_lmt_beamform_type {
PW_LMT_BF,
PW_LMT_NONBF,
PW_LMT_NULL
};
enum odm_pw_lmt_rfpath_type {
PW_LMT_PH_1T,
PW_LMT_PH_2T,
PW_LMT_PH_3T,
PW_LMT_PH_4T,
PW_LMT_PH_NULL
};
struct halrf_tx_pw_lmt {
u8 band:1;
u8 bw:3;
u8 rs:2;
u8 ntx:2;
u8 bf:3;
u8 reg:5;
u8 ch;
s8 val;
};
struct halrf_tx_pw_lmt_ru {
u8 band:1;
u8 bw:2;
u8 ntx:2;
u8 rs:3;
u8 reg;
u8 ch;
s8 val;
};
#endif
/******************************************************************************
* radioa.TXT
******************************************************************************/
const u32 array_mp_8852b_radioa[] = {
0xF0010000, 0x00000000,
0xF0020000, 0x00000001,
0xF0010001, 0x00000002,
0xF0020001, 0x00000003,
0xF0030001, 0x00000004,
0xF0040001, 0x00000005,
0x005, 0x00000000,
0x000, 0x00030000,
0x10000, 0x00030000,
0x018, 0x00011124,
0x10018, 0x00011124,
0x000, 0x00033C00,
0x10000, 0x00033C00,
0x01A, 0x00040004,
0x0FE, 0x00000000,
0x011, 0x00014073,
0x067, 0x00000070,
0x059, 0x000A0000,
0x066, 0x00000100,
0x057, 0x0000D589,
0x05A, 0x0007FFFF,
0x0A4, 0x0006FF12,
0x043, 0x00005000,
0x0E1, 0x00000001,
0x0DD, 0x000001A0,
0x0CA, 0x00002000,
0x0D3, 0x00000103,
0x0B3, 0x0004EFE0,
0x0B4, 0x0007C07E,
0x0B5, 0x0003A701,
0x0B6, 0x000581E0,
0x0B7, 0x00001A0A,
0x0BB, 0x000C7000,
0x0ED, 0x00000400,
0x033, 0x00000000,
0x03F, 0x00000543,
0x033, 0x00000001,
0x03F, 0x00000542,
0x033, 0x00000002,
0x03F, 0x00000541,
0x033, 0x00000003,
0x03F, 0x00000521,
0x033, 0x00000004,
0x03F, 0x00000343,
0x033, 0x00000005,
0x03F, 0x00000342,
0x033, 0x00000006,
0x03F, 0x00000341,
0x033, 0x00000007,
0x03F, 0x00000321,
0x033, 0x00000008,
0x03F, 0x000005C3,
0x033, 0x00000009,
0x03F, 0x000005C2,
0x033, 0x0000000A,
0x03F, 0x000005C1,
0x033, 0x0000000B,
0x03F, 0x000005A1,
0x033, 0x0000000C,
0x03F, 0x000002C3,
0x033, 0x0000000D,
0x03F, 0x000002C2,
0x033, 0x0000000E,
0x03F, 0x000002C1,
0x033, 0x0000000F,
0x03F, 0x000002A1,
0x0ED, 0x00000000,
0x0ED, 0x00002000,
0x033, 0x00000002,
0x03D, 0x0004A883,
0x03E, 0x00000000,
0x03F, 0x00000001,
0x033, 0x00000006,
0x03D, 0x0004A883,
0x03E, 0x00000000,
0x03F, 0x00000001,
0x0ED, 0x00000000,
0x018, 0x00001001,
0x10018, 0x00001001,
0x002, 0x0000000D,
0x10002, 0x0000000D,
0x0EE, 0x00000004,
0x033, 0x0000000B,
0x03F, 0x0000000B,
0x033, 0x0000000C,
0x03F, 0x00000012,
0x033, 0x0000000D,
0x03F, 0x00000019,
0x0EE, 0x00000000,
0x08F, 0x000D0F7A,
0x0EF, 0x00080000,
0x033, 0x00000008,
0x03E, 0x000000C4,
0x03F, 0x000034C0,
0x033, 0x0000000A,
0x03E, 0x000000C4,
0x03F, 0x000035D0,
0x033, 0x0000000B,
0x03E, 0x000000C4,
0x03F, 0x000035C8,
0x0EF, 0x00000000,
0x0EF, 0x00004000,
0x033, 0x00000006,
0x03F, 0x00000700,
0x033, 0x00000005,
0x03F, 0x00090600,
0x033, 0x00000004,
0x03F, 0x000A3500,
0x033, 0x00000003,
0x03F, 0x000A3400,
0x033, 0x00000002,
0x03F, 0x00008B00,
0x033, 0x00000001,
0x03F, 0x00001B00,
0x033, 0x00000000,
0x03F, 0x00003A00,
0x0EF, 0x00000000,
0x0EE, 0x00000010,
0x033, 0x00000006,
0x03F, 0x00000003,
0x033, 0x00000007,
0x03F, 0x00000003,
0x033, 0x00000008,
0x03F, 0x00000001,
0x0EE, 0x00000000,
0x0EF, 0x00001000,
0x033, 0x00000000,
0x03F, 0x00000015,
0x033, 0x00000001,
0x03F, 0x00000017,
0x0EF, 0x00000000,
0x0EF, 0x00008000,
0x033, 0x00000000,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000001,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000002,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000003,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000004,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000005,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000006,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000008,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000009,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x0000000A,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x0000000B,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x0000000C,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x0000000D,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x0000000E,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000010,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000011,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000012,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000013,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000014,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000015,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000016,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000020,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000021,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000022,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000023,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000024,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000025,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000026,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000028,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000029,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x0000002A,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x0000002B,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x0000002C,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x0000002D,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x0000002E,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000030,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000031,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000032,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000033,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000034,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000035,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000036,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x0EF, 0x00000000,
0x0EF, 0x00000100,
0x033, 0x00000000,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000001,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000002,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000003,
0x03F, 0x00004376,
0x033, 0x00000004,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000005,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000006,
0x03F, 0x00004376,
0x033, 0x00000007,
0x03F, 0x00004376,
0x033, 0x00000008,
0x03F, 0x00004376,
0x033, 0x00000009,
0x03F, 0x00004376,
0x033, 0x0000000A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x0000000D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x0000000E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x0000000F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000010,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000011,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000012,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000013,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000014,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000015,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000016,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000017,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000020,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000021,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000022,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004376,
0xB0000000, 0x00000000,
0x033, 0x00000023,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0xA0000000, 0x00000000,
0x03F, 0x00004396,
0xB0000000, 0x00000000,
0x033, 0x00000024,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0xA0000000, 0x00000000,
0x03F, 0x00004396,
0xB0000000, 0x00000000,
0x033, 0x00000025,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0xA0000000, 0x00000000,
0x03F, 0x00004396,
0xB0000000, 0x00000000,
0x033, 0x00000026,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0xA0000000, 0x00000000,
0x03F, 0x00004396,
0xB0000000, 0x00000000,
0x033, 0x00000027,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004396,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004386,
0xA0000000, 0x00000000,
0x03F, 0x00004396,
0xB0000000, 0x00000000,
0x0EF, 0x00000000,
0x067, 0x00008072,
0x0EF, 0x00000010,
0x033, 0x00000001,
0x03F, 0x00000ED5,
0x033, 0x00000002,
0x03F, 0x00000FC7,
0x033, 0x00000003,
0x03F, 0x00000783,
0x033, 0x00000004,
0x03F, 0x00000973,
0x033, 0x00000005,
0x03F, 0x00000762,
0x033, 0x00000006,
0x03F, 0x00000762,
0x0EF, 0x00000000,
0x0EF, 0x00000080,
0x033, 0x00000000,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000001,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000002,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000003,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000004,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000005,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000006,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000007,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000008,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000009,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000000A,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000000B,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000000C,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000000D,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000000E,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000000F,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000010,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000011,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000012,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000013,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023958,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000014,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000015,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000016,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000017,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000018,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000019,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000001A,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000001B,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000001C,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000001D,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000001E,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000001F,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000020,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000021,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000022,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000023,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000024,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000025,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000026,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000027,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000028,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000029,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000002A,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000002B,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000002C,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000002D,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000002E,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000002F,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000030,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000031,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000032,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000033,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000034,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000035,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000036,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000037,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x00000038,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x00000039,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026858,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x00026858,
0xB0000000, 0x00000000,
0x033, 0x0000003A,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x033, 0x0000003B,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x0002C758,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00023A58,
0xA0000000, 0x00000000,
0x03F, 0x0002C758,
0xB0000000, 0x00000000,
0x0EF, 0x00000000,
0x0EE, 0x00000800,
0x033, 0x00000000,
0x03F, 0x00000001,
0x033, 0x00000001,
0x03F, 0x00000003,
0x033, 0x00000002,
0x03F, 0x00000005,
0x033, 0x00000003,
0x03F, 0x00000007,
0x033, 0x00000004,
0x03F, 0x00000001,
0x033, 0x00000005,
0x03F, 0x00000003,
0x033, 0x00000006,
0x03F, 0x00000006,
0x033, 0x00000007,
0x03F, 0x00000007,
0x0EE, 0x00000000,
0x0EE, 0x00001000,
0x033, 0x00000000,
0x03F, 0x00003000,
0x033, 0x00000001,
0x03F, 0x00003001,
0x033, 0x00000002,
0x03F, 0x00003003,
0x033, 0x00000003,
0x03F, 0x00003007,
0x033, 0x00000004,
0x03F, 0x0000300F,
0x033, 0x00000005,
0x03F, 0x0000310F,
0x033, 0x00000006,
0x03F, 0x0000330F,
0x033, 0x00000007,
0x03F, 0x0000330F,
0x033, 0x00000008,
0x03F, 0x00003000,
0x033, 0x00000009,
0x03F, 0x00003001,
0x033, 0x0000000A,
0x03F, 0x00003003,
0x033, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0xA0000000, 0x00000000,
0x03F, 0x00003103,
0xB0000000, 0x00000000,
0x033, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0xA0000000, 0x00000000,
0x03F, 0x00003307,
0xB0000000, 0x00000000,
0x033, 0x0000000D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0xA0000000, 0x00000000,
0x03F, 0x00002307,
0xB0000000, 0x00000000,
0x033, 0x0000000E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0xA0000000, 0x00000000,
0x03F, 0x00000307,
0xB0000000, 0x00000000,
0x033, 0x0000000F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0xA0000000, 0x00000000,
0x03F, 0x00000307,
0xB0000000, 0x00000000,
0x0EE, 0x00000000,
0x0EE, 0x00000200,
0x033, 0x00000000,
0x03F, 0x00000001,
0x033, 0x00000001,
0x03F, 0x00000003,
0x033, 0x00000002,
0x03F, 0x00000005,
0x033, 0x00000003,
0x03F, 0x00000007,
0x0EE, 0x00000000,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000100,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000100,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0xA0000000, 0x00000000,
0x0EC, 0x00000100,
0xB0000000, 0x00000000,
0x033, 0x00000004,
0x03D, 0x00000078,
0x03E, 0x00080000,
0x03F, 0x00000000,
0x033, 0x00000005,
0x03D, 0x0000007B,
0x03E, 0x00020000,
0x03F, 0x00000000,
0x0EC, 0x00000000,
0x0DE, 0x00000000,
0x0EF, 0x00000000,
0x033, 0x00000000,
0x008, 0x00060280,
0x009, 0x00030400,
0x0EF, 0x00000000,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x000001F7,
0x033, 0x00000003,
0x03F, 0x000000FF,
0x033, 0x00000004,
0x03F, 0x000000FF,
0x033, 0x00000005,
0x03F, 0x000000FF,
0x033, 0x00000006,
0x03F, 0x000000FF,
0x033, 0x00000007,
0x03F, 0x000000FF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x000001F7,
0x033, 0x00000003,
0x03F, 0x000000FF,
0x033, 0x00000004,
0x03F, 0x000000FF,
0x033, 0x00000005,
0x03F, 0x000000FF,
0x033, 0x00000006,
0x03F, 0x000000FF,
0x033, 0x00000007,
0x03F, 0x000000FF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0xA0000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x000001F7,
0x033, 0x00000003,
0x03F, 0x000000FF,
0x033, 0x00000004,
0x03F, 0x000000FF,
0x033, 0x00000005,
0x03F, 0x000000FF,
0x033, 0x00000006,
0x03F, 0x000000FF,
0x033, 0x00000007,
0x03F, 0x000000FF,
0xB0000000, 0x00000000,
0x0EF, 0x00000200,
0x033, 0x00000000,
0x03F, 0x0000017F,
0x033, 0x00000001,
0x03F, 0x0000017F,
0x033, 0x00000002,
0x03F, 0x0000017F,
0x033, 0x00000003,
0x03F, 0x0000007F,
0x033, 0x00000004,
0x03F, 0x0000007F,
0x033, 0x00000005,
0x03F, 0x0000007F,
0x033, 0x00000006,
0x03F, 0x0000007F,
0x033, 0x00000007,
0x03F, 0x0000007F,
0x0EF, 0x00000000,
0x06E, 0x00077A18,
0x06F, 0x00077A18,
0x06D, 0x00000C31,
0x0EF, 0x00020000,
0x033, 0x00000000,
0x03F, 0x000005FF,
0x0EF, 0x00000000,
0x005, 0x00000001,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0xA0000000, 0x00000000,
0x094, 0x000001FC,
0xB0000000, 0x00000000,
0x100EE, 0x00002000,
0x10033, 0x00000080,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0xA0000000, 0x00000000,
0x1003F, 0x000000F6,
0xB0000000, 0x00000000,
0x10033, 0x00000081,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0xA0000000, 0x00000000,
0x1003F, 0x000000F3,
0xB0000000, 0x00000000,
0x10033, 0x00000082,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0xA0000000, 0x00000000,
0x1003F, 0x000000F0,
0xB0000000, 0x00000000,
0x10033, 0x00000083,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0xA0000000, 0x00000000,
0x1003F, 0x000000ED,
0xB0000000, 0x00000000,
0x10033, 0x00000084,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0xA0000000, 0x00000000,
0x1003F, 0x000000EA,
0xB0000000, 0x00000000,
0x10033, 0x00000085,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0xA0000000, 0x00000000,
0x1003F, 0x000000E7,
0xB0000000, 0x00000000,
0x10033, 0x00000086,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0xA0000000, 0x00000000,
0x1003F, 0x000000A6,
0xB0000000, 0x00000000,
0x10033, 0x00000087,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0xA0000000, 0x00000000,
0x1003F, 0x000000A3,
0xB0000000, 0x00000000,
0x10033, 0x00000088,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0xA0000000, 0x00000000,
0x1003F, 0x00000063,
0xB0000000, 0x00000000,
0x10033, 0x00000089,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0xA0000000, 0x00000000,
0x1003F, 0x00000060,
0xB0000000, 0x00000000,
0x10033, 0x0000008A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0xA0000000, 0x00000000,
0x1003F, 0x00000026,
0xB0000000, 0x00000000,
0x10033, 0x0000008B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0xA0000000, 0x00000000,
0x1003F, 0x00000023,
0xB0000000, 0x00000000,
0x10033, 0x0000008C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0xA0000000, 0x00000000,
0x1003F, 0x00000020,
0xB0000000, 0x00000000,
0x10033, 0x0000008D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0xA0000000, 0x00000000,
0x1003F, 0x0000001D,
0xB0000000, 0x00000000,
0x10033, 0x0000008E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x0000001A,
0xB0000000, 0x00000000,
0x10033, 0x0000008F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0xA0000000, 0x00000000,
0x1003F, 0x00000017,
0xB0000000, 0x00000000,
0x10033, 0x00000090,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000014,
0xB0000000, 0x00000000,
0x10033, 0x000000A0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0xA0000000, 0x00000000,
0x1003F, 0x000000F6,
0xB0000000, 0x00000000,
0x10033, 0x000000A1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0xA0000000, 0x00000000,
0x1003F, 0x000000F3,
0xB0000000, 0x00000000,
0x10033, 0x000000A2,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0xA0000000, 0x00000000,
0x1003F, 0x000000F0,
0xB0000000, 0x00000000,
0x10033, 0x000000A3,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0xA0000000, 0x00000000,
0x1003F, 0x000000ED,
0xB0000000, 0x00000000,
0x10033, 0x000000A4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0xA0000000, 0x00000000,
0x1003F, 0x000000EA,
0xB0000000, 0x00000000,
0x10033, 0x000000A5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0xA0000000, 0x00000000,
0x1003F, 0x000000E7,
0xB0000000, 0x00000000,
0x10033, 0x000000A6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0xA0000000, 0x00000000,
0x1003F, 0x000000A6,
0xB0000000, 0x00000000,
0x10033, 0x000000A7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0xA0000000, 0x00000000,
0x1003F, 0x000000A3,
0xB0000000, 0x00000000,
0x10033, 0x000000A8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0xA0000000, 0x00000000,
0x1003F, 0x00000063,
0xB0000000, 0x00000000,
0x10033, 0x000000A9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0xA0000000, 0x00000000,
0x1003F, 0x00000060,
0xB0000000, 0x00000000,
0x10033, 0x000000AA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0xA0000000, 0x00000000,
0x1003F, 0x00000026,
0xB0000000, 0x00000000,
0x10033, 0x000000AB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0xA0000000, 0x00000000,
0x1003F, 0x00000023,
0xB0000000, 0x00000000,
0x10033, 0x000000AC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0xA0000000, 0x00000000,
0x1003F, 0x00000020,
0xB0000000, 0x00000000,
0x10033, 0x000000AD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0xA0000000, 0x00000000,
0x1003F, 0x0000001D,
0xB0000000, 0x00000000,
0x10033, 0x000000AE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x0000001A,
0xB0000000, 0x00000000,
0x10033, 0x000000AF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0xA0000000, 0x00000000,
0x1003F, 0x00000017,
0xB0000000, 0x00000000,
0x10033, 0x000000B0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000014,
0xB0000000, 0x00000000,
0x10033, 0x000000C0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0xA0000000, 0x00000000,
0x1003F, 0x000000F6,
0xB0000000, 0x00000000,
0x10033, 0x000000C1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0xA0000000, 0x00000000,
0x1003F, 0x000000F3,
0xB0000000, 0x00000000,
0x10033, 0x000000C2,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0xA0000000, 0x00000000,
0x1003F, 0x000000F0,
0xB0000000, 0x00000000,
0x10033, 0x000000C3,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0xA0000000, 0x00000000,
0x1003F, 0x000000ED,
0xB0000000, 0x00000000,
0x10033, 0x000000C4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0xA0000000, 0x00000000,
0x1003F, 0x000000EA,
0xB0000000, 0x00000000,
0x10033, 0x000000C5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0xA0000000, 0x00000000,
0x1003F, 0x000000E7,
0xB0000000, 0x00000000,
0x10033, 0x000000C6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0xA0000000, 0x00000000,
0x1003F, 0x000000A6,
0xB0000000, 0x00000000,
0x10033, 0x000000C7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0xA0000000, 0x00000000,
0x1003F, 0x000000A3,
0xB0000000, 0x00000000,
0x10033, 0x000000C8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0xA0000000, 0x00000000,
0x1003F, 0x00000063,
0xB0000000, 0x00000000,
0x10033, 0x000000C9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0xA0000000, 0x00000000,
0x1003F, 0x00000060,
0xB0000000, 0x00000000,
0x10033, 0x000000CA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0xA0000000, 0x00000000,
0x1003F, 0x00000026,
0xB0000000, 0x00000000,
0x10033, 0x000000CB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0xA0000000, 0x00000000,
0x1003F, 0x00000023,
0xB0000000, 0x00000000,
0x10033, 0x000000CC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0xA0000000, 0x00000000,
0x1003F, 0x00000020,
0xB0000000, 0x00000000,
0x10033, 0x000000CD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0xA0000000, 0x00000000,
0x1003F, 0x0000001D,
0xB0000000, 0x00000000,
0x10033, 0x000000CE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x0000001A,
0xB0000000, 0x00000000,
0x10033, 0x000000CF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0xA0000000, 0x00000000,
0x1003F, 0x00000017,
0xB0000000, 0x00000000,
0x10033, 0x000000D0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000014,
0xB0000000, 0x00000000,
0x100EE, 0x00000000,
0x100EE, 0x00004000,
0x10033, 0x00000080,
0x1003F, 0x000001A9,
0x10033, 0x00000081,
0x1003F, 0x000001A3,
0x10033, 0x00000082,
0x1003F, 0x0000019D,
0x10033, 0x00000083,
0x1003F, 0x00000197,
0x10033, 0x00000084,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0xA0000000, 0x00000000,
0x1003F, 0x00000191,
0xB0000000, 0x00000000,
0x10033, 0x00000085,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0xA0000000, 0x00000000,
0x1003F, 0x0000018B,
0xB0000000, 0x00000000,
0x10033, 0x00000086,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0xA0000000, 0x00000000,
0x1003F, 0x0000014D,
0xB0000000, 0x00000000,
0x10033, 0x00000087,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0xA0000000, 0x00000000,
0x1003F, 0x0000010B,
0xB0000000, 0x00000000,
0x10033, 0x00000088,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0xA0000000, 0x00000000,
0x1003F, 0x000000DF,
0xB0000000, 0x00000000,
0x10033, 0x00000089,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0xA0000000, 0x00000000,
0x1003F, 0x000000D9,
0xB0000000, 0x00000000,
0x10033, 0x0000008A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0xA0000000, 0x00000000,
0x1003F, 0x000000D3,
0xB0000000, 0x00000000,
0x10033, 0x0000008B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0xA0000000, 0x00000000,
0x1003F, 0x00000099,
0xB0000000, 0x00000000,
0x10033, 0x0000008C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0xA0000000, 0x00000000,
0x1003F, 0x00000093,
0xB0000000, 0x00000000,
0x10033, 0x0000008D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x00000059,
0xB0000000, 0x00000000,
0x10033, 0x0000008E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000053,
0xB0000000, 0x00000000,
0x10033, 0x0000008F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0xA0000000, 0x00000000,
0x1003F, 0x00000019,
0xB0000000, 0x00000000,
0x10033, 0x00000090,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0xA0000000, 0x00000000,
0x1003F, 0x00000013,
0xB0000000, 0x00000000,
0x10033, 0x00000091,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0xA0000000, 0x00000000,
0x1003F, 0x0000000D,
0xB0000000, 0x00000000,
0x10033, 0x000000A0,
0x1003F, 0x000001A9,
0x10033, 0x000000A1,
0x1003F, 0x000001A3,
0x10033, 0x000000A2,
0x1003F, 0x0000019D,
0x10033, 0x000000A3,
0x1003F, 0x00000197,
0x10033, 0x000000A4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0xA0000000, 0x00000000,
0x1003F, 0x00000191,
0xB0000000, 0x00000000,
0x10033, 0x000000A5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0xA0000000, 0x00000000,
0x1003F, 0x0000018B,
0xB0000000, 0x00000000,
0x10033, 0x000000A6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0xA0000000, 0x00000000,
0x1003F, 0x0000014D,
0xB0000000, 0x00000000,
0x10033, 0x000000A7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0xA0000000, 0x00000000,
0x1003F, 0x0000010B,
0xB0000000, 0x00000000,
0x10033, 0x000000A8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0xA0000000, 0x00000000,
0x1003F, 0x000000DF,
0xB0000000, 0x00000000,
0x10033, 0x000000A9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0xA0000000, 0x00000000,
0x1003F, 0x000000D9,
0xB0000000, 0x00000000,
0x10033, 0x000000AA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0xA0000000, 0x00000000,
0x1003F, 0x000000D3,
0xB0000000, 0x00000000,
0x10033, 0x000000AB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0xA0000000, 0x00000000,
0x1003F, 0x00000099,
0xB0000000, 0x00000000,
0x10033, 0x000000AC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0xA0000000, 0x00000000,
0x1003F, 0x00000093,
0xB0000000, 0x00000000,
0x10033, 0x000000AD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x00000059,
0xB0000000, 0x00000000,
0x10033, 0x000000AE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000053,
0xB0000000, 0x00000000,
0x10033, 0x000000AF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0xA0000000, 0x00000000,
0x1003F, 0x00000019,
0xB0000000, 0x00000000,
0x10033, 0x000000B0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0xA0000000, 0x00000000,
0x1003F, 0x00000013,
0xB0000000, 0x00000000,
0x10033, 0x000000B1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0xA0000000, 0x00000000,
0x1003F, 0x0000000D,
0xB0000000, 0x00000000,
0x10033, 0x000000C0,
0x1003F, 0x000001A9,
0x10033, 0x000000C1,
0x1003F, 0x000001A3,
0x10033, 0x000000C2,
0x1003F, 0x0000019D,
0x10033, 0x000000C3,
0x1003F, 0x00000197,
0x10033, 0x000000C4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0xA0000000, 0x00000000,
0x1003F, 0x00000191,
0xB0000000, 0x00000000,
0x10033, 0x000000C5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0xA0000000, 0x00000000,
0x1003F, 0x0000018B,
0xB0000000, 0x00000000,
0x10033, 0x000000C6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0xA0000000, 0x00000000,
0x1003F, 0x0000014D,
0xB0000000, 0x00000000,
0x10033, 0x000000C7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0xA0000000, 0x00000000,
0x1003F, 0x0000010B,
0xB0000000, 0x00000000,
0x10033, 0x000000C8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0xA0000000, 0x00000000,
0x1003F, 0x000000DF,
0xB0000000, 0x00000000,
0x10033, 0x000000C9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0xA0000000, 0x00000000,
0x1003F, 0x000000D9,
0xB0000000, 0x00000000,
0x10033, 0x000000CA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0xA0000000, 0x00000000,
0x1003F, 0x000000D3,
0xB0000000, 0x00000000,
0x10033, 0x000000CB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0xA0000000, 0x00000000,
0x1003F, 0x00000099,
0xB0000000, 0x00000000,
0x10033, 0x000000CC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0xA0000000, 0x00000000,
0x1003F, 0x00000093,
0xB0000000, 0x00000000,
0x10033, 0x000000CD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x00000059,
0xB0000000, 0x00000000,
0x10033, 0x000000CE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000053,
0xB0000000, 0x00000000,
0x10033, 0x000000CF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0xA0000000, 0x00000000,
0x1003F, 0x00000019,
0xB0000000, 0x00000000,
0x10033, 0x000000D0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0xA0000000, 0x00000000,
0x1003F, 0x00000013,
0xB0000000, 0x00000000,
0x10033, 0x000000D1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0xA0000000, 0x00000000,
0x1003F, 0x0000000D,
0xB0000000, 0x00000000,
0x100EE, 0x00000000,
0x100EE, 0x00002000,
0x10033, 0x00000000,
0x1003F, 0x000000F6,
0x10033, 0x00000001,
0x1003F, 0x000000F3,
0x10033, 0x00000002,
0x1003F, 0x000000F0,
0x10033, 0x00000003,
0x1003F, 0x000000ED,
0x10033, 0x00000004,
0x1003F, 0x000000EA,
0x10033, 0x00000005,
0x1003F, 0x000000E7,
0x10033, 0x00000006,
0x1003F, 0x000000A6,
0x10033, 0x00000007,
0x1003F, 0x000000A3,
0x10033, 0x00000008,
0x1003F, 0x00000063,
0x10033, 0x00000009,
0x1003F, 0x00000060,
0x10033, 0x0000000A,
0x1003F, 0x00000023,
0x10033, 0x0000000B,
0x1003F, 0x00000020,
0x10033, 0x0000000C,
0x1003F, 0x0000001D,
0x10033, 0x0000000D,
0x1003F, 0x0000001A,
0x10033, 0x0000000E,
0x1003F, 0x00000017,
0x10033, 0x0000000F,
0x1003F, 0x00000014,
0x10033, 0x00000010,
0x1003F, 0x00000011,
0x100EE, 0x00000000,
0x100EE, 0x00004000,
0x10033, 0x00000000,
0x1003F, 0x000001AF,
0x10033, 0x00000001,
0x1003F, 0x000001A9,
0x10033, 0x00000002,
0x1003F, 0x000001A3,
0x10033, 0x00000003,
0x1003F, 0x0000019D,
0x10033, 0x00000004,
0x1003F, 0x00000197,
0x10033, 0x00000005,
0x1003F, 0x0000015F,
0x10033, 0x00000006,
0x1003F, 0x00000159,
0x10033, 0x00000007,
0x1003F, 0x0000011F,
0x10033, 0x00000008,
0x1003F, 0x00000119,
0x10033, 0x00000009,
0x1003F, 0x000000DF,
0x10033, 0x0000000A,
0x1003F, 0x000000D9,
0x10033, 0x0000000B,
0x1003F, 0x0000009F,
0x10033, 0x0000000C,
0x1003F, 0x00000099,
0x10033, 0x0000000D,
0x1003F, 0x0000005F,
0x10033, 0x0000000E,
0x1003F, 0x00000059,
0x10033, 0x0000000F,
0x1003F, 0x0000001F,
0x10033, 0x00000010,
0x1003F, 0x00000019,
0x10033, 0x00000011,
0x1003F, 0x00000013,
0x100EE, 0x00000000,
0x10005, 0x00000001,
0x09F, 0x00000019,
};
/******************************************************************************
* radiob.TXT
******************************************************************************/
const u32 array_mp_8852b_radiob[] = {
0xF0010000, 0x00000000,
0xF0020000, 0x00000001,
0xF0010001, 0x00000002,
0xF0020001, 0x00000003,
0xF0030001, 0x00000004,
0xF0040001, 0x00000005,
0x005, 0x00000000,
0x000, 0x00030000,
0x10000, 0x00030000,
0x018, 0x00011124,
0x10018, 0x00011124,
0x000, 0x00033C00,
0x10000, 0x00033C00,
0x01A, 0x00040004,
0x0FE, 0x00000000,
0x011, 0x00014073,
0x067, 0x00000070,
0x059, 0x000A0000,
0x066, 0x00000100,
0x05A, 0x0007F000,
0x0A4, 0x0006FF12,
0x043, 0x00005000,
0x0E1, 0x00000001,
0x0DD, 0x000001A0,
0x0CA, 0x00002000,
0x0D3, 0x00000103,
0x0B3, 0x0004EFE0,
0x0B4, 0x0007C03E,
0x0B5, 0x0003A201,
0x0BB, 0x000C7000,
0x0ED, 0x00002000,
0x033, 0x00000002,
0x03D, 0x0004A883,
0x03E, 0x00000000,
0x03F, 0x00000001,
0x033, 0x00000006,
0x03D, 0x0004A883,
0x03E, 0x00000000,
0x03F, 0x00000001,
0x0ED, 0x00000000,
0x018, 0x00001001,
0x10018, 0x00001001,
0x002, 0x0000000D,
0x10002, 0x0000000D,
0x0EE, 0x00000004,
0x033, 0x0000000B,
0x03F, 0x0000000B,
0x033, 0x0000000C,
0x03F, 0x00000012,
0x033, 0x0000000D,
0x03F, 0x00000019,
0x0EE, 0x00000000,
0x08F, 0x000D0F7A,
0x0EF, 0x00080000,
0x033, 0x00000008,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D30,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D30,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D30,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D30,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D30,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D30,
0xA0000000, 0x00000000,
0x03E, 0x000000C4,
0x03F, 0x000034C0,
0xB0000000, 0x00000000,
0x033, 0x0000000A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D74,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D74,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D74,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D74,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D74,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D74,
0xA0000000, 0x00000000,
0x03E, 0x000000C4,
0x03F, 0x000035D0,
0xB0000000, 0x00000000,
0x033, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D72,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D72,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D72,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D72,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D72,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03E, 0x00000031,
0x03F, 0x00000D72,
0xA0000000, 0x00000000,
0x03E, 0x000000C4,
0x03F, 0x000035C8,
0xB0000000, 0x00000000,
0x0EF, 0x00000000,
0x0EF, 0x00004000,
0x033, 0x00000007,
0x03F, 0x00000707,
0x033, 0x00000006,
0x03F, 0x00000707,
0x033, 0x00000005,
0x03F, 0x00090607,
0x033, 0x00000004,
0x03F, 0x000A3507,
0x033, 0x00000003,
0x03F, 0x000A3407,
0x033, 0x00000002,
0x03F, 0x00008B07,
0x033, 0x00000001,
0x03F, 0x00001B07,
0x033, 0x00000000,
0x03F, 0x00003A07,
0x033, 0x00000017,
0x03F, 0x00000705,
0x033, 0x00000016,
0x03F, 0x00000705,
0x033, 0x00000015,
0x03F, 0x00090605,
0x033, 0x00000014,
0x03F, 0x000A3505,
0x033, 0x00000013,
0x03F, 0x000A3405,
0x033, 0x00000012,
0x03F, 0x00008B05,
0x033, 0x00000011,
0x03F, 0x00001B05,
0x033, 0x00000010,
0x03F, 0x00003A05,
0x0EF, 0x00000000,
0x0EE, 0x00000010,
0x033, 0x00000006,
0x03F, 0x00000003,
0x033, 0x00000007,
0x03F, 0x00000003,
0x033, 0x00000008,
0x03F, 0x00000001,
0x0EE, 0x00000000,
0x0EF, 0x00001000,
0x033, 0x00000000,
0x03F, 0x00000015,
0x033, 0x00000001,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000005,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000005,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000017,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000017,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000017,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000017,
0xA0000000, 0x00000000,
0x03F, 0x00000005,
0xB0000000, 0x00000000,
0x033, 0x00000002,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000017,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000017,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000015,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000015,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000015,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000015,
0xA0000000, 0x00000000,
0x03F, 0x00000017,
0xB0000000, 0x00000000,
0x033, 0x00000003,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000005,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000005,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000005,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000005,
0xA0000000, 0x00000000,
0x03F, 0x00000007,
0xB0000000, 0x00000000,
0x0EF, 0x00000000,
0x0EF, 0x00008000,
0x033, 0x00000000,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000001,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000002,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000003,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000004,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000005,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000006,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000008,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000009,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x0000000A,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x0000000B,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x0000000C,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x0000000D,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x0000000E,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000010,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000011,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000012,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000013,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000014,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000015,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000016,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000020,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000021,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000022,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000023,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000024,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000025,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000026,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000028,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000029,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x0000002A,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x0000002B,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x0000002C,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x0000002D,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x0000002E,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x033, 0x00000030,
0x03E, 0x00004FC0,
0x03F, 0x00000087,
0x033, 0x00000031,
0x03E, 0x000046C0,
0x03F, 0x00000087,
0x033, 0x00000032,
0x03E, 0x00004240,
0x03F, 0x00000087,
0x033, 0x00000033,
0x03E, 0x00008010,
0x03F, 0x00000147,
0x033, 0x00000034,
0x03E, 0x0000A048,
0x03F, 0x0000004F,
0x033, 0x00000035,
0x03E, 0x0000A030,
0x03F, 0x0000005F,
0x033, 0x00000036,
0x03E, 0x0000A000,
0x03F, 0x0000009F,
0x0EF, 0x00000000,
0x0EF, 0x00000100,
0x033, 0x00000000,
0x03F, 0x00004346,
0x033, 0x00000001,
0x03F, 0x00004346,
0x033, 0x00000002,
0x03F, 0x00004346,
0x033, 0x00000003,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x00000004,
0x03F, 0x00004346,
0x033, 0x00000005,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004317,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x00000006,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x00000007,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x00000008,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x00000009,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004376,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x0000000A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x0000000D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x000043A6,
0xA0000000, 0x00000000,
0x03F, 0x00004346,
0xB0000000, 0x00000000,
0x033, 0x0000000E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x0000000F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000010,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000011,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000012,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000013,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000014,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000015,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000016,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000017,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000020,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000021,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004347,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000022,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004366,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00004346,
0xA0000000, 0x00000000,
0x03F, 0x00004366,
0xB0000000, 0x00000000,
0x033, 0x00000023,
0x03F, 0x00004386,
0x033, 0x00000024,
0x03F, 0x00004386,
0x033, 0x00000025,
0x03F, 0x00004386,
0x033, 0x00000026,
0x03F, 0x00004386,
0x033, 0x00000027,
0x03F, 0x00004386,
0x0EF, 0x00000000,
0x067, 0x00008072,
0x0EF, 0x00000010,
0x033, 0x00000001,
0x03F, 0x00000ED5,
0x033, 0x00000002,
0x03F, 0x00000FC5,
0x033, 0x00000003,
0x03F, 0x00000A93,
0x033, 0x00000004,
0x03F, 0x00000973,
0x033, 0x00000005,
0x03F, 0x00000761,
0x033, 0x00000006,
0x03F, 0x00000761,
0x0EF, 0x00000000,
0x0EF, 0x00000080,
0x033, 0x00000000,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000001,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000002,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000003,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000004,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000005,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000006,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000007,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000008,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000009,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x0000000A,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000000B,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000000C,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x0000000D,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x0000000E,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000000F,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000010,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000011,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022758,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000012,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000013,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020758,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000014,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000015,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026558,
0xB0000000, 0x00000000,
0x033, 0x00000016,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000017,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000018,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000019,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000001A,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000001B,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000001C,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000001D,
0x03E, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000001E,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000001F,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000020,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000021,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000022,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000023,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000024,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000025,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000026,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000027,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000028,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000029,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000002A,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000002B,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000002C,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000002D,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000002E,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000002F,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000030,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000031,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000032,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000033,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000034,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000035,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000036,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000037,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x00000038,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x00000039,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00026458,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022658,
0xA0000000, 0x00000000,
0x03F, 0x00026458,
0xB0000000, 0x00000000,
0x033, 0x0000003A,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00022858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x033, 0x0000003B,
0x03E, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00027558,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00020858,
0xA0000000, 0x00000000,
0x03F, 0x00027558,
0xB0000000, 0x00000000,
0x0EF, 0x00000000,
0x0EE, 0x00000800,
0x033, 0x00000000,
0x03F, 0x00000001,
0x033, 0x00000001,
0x03F, 0x00000003,
0x033, 0x00000002,
0x03F, 0x00000005,
0x033, 0x00000003,
0x03F, 0x00000007,
0x033, 0x00000004,
0x03F, 0x00000001,
0x033, 0x00000005,
0x03F, 0x00000003,
0x033, 0x00000006,
0x03F, 0x00000006,
0x033, 0x00000007,
0x03F, 0x00000007,
0x0EE, 0x00000000,
0x0EE, 0x00001000,
0x033, 0x00000000,
0x03F, 0x00003000,
0x033, 0x00000001,
0x03F, 0x00003001,
0x033, 0x00000002,
0x03F, 0x00003003,
0x033, 0x00000003,
0x03F, 0x00003007,
0x033, 0x00000004,
0x03F, 0x0000300F,
0x033, 0x00000005,
0x03F, 0x0000310F,
0x033, 0x00000006,
0x03F, 0x0000330F,
0x033, 0x00000007,
0x03F, 0x0000330F,
0x033, 0x00000008,
0x03F, 0x00003000,
0x033, 0x00000009,
0x03F, 0x00003001,
0x033, 0x0000000A,
0x03F, 0x00003003,
0x033, 0x0000000B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003007,
0xA0000000, 0x00000000,
0x03F, 0x00003103,
0xB0000000, 0x00000000,
0x033, 0x0000000C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003107,
0xA0000000, 0x00000000,
0x03F, 0x00003307,
0xB0000000, 0x00000000,
0x033, 0x0000000D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00003307,
0xA0000000, 0x00000000,
0x03F, 0x00002307,
0xB0000000, 0x00000000,
0x033, 0x0000000E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00001307,
0xA0000000, 0x00000000,
0x03F, 0x00000307,
0xB0000000, 0x00000000,
0x033, 0x0000000F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x03F, 0x00000307,
0xA0000000, 0x00000000,
0x03F, 0x00000307,
0xB0000000, 0x00000000,
0x0EE, 0x00000000,
0x0EE, 0x00000200,
0x033, 0x00000000,
0x03F, 0x00000001,
0x033, 0x00000001,
0x03F, 0x00000003,
0x033, 0x00000002,
0x03F, 0x00000005,
0x033, 0x00000003,
0x03F, 0x00000007,
0x0EE, 0x00000000,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000100,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000100,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x0EC, 0x00000000,
0xA0000000, 0x00000000,
0x0EC, 0x00000100,
0xB0000000, 0x00000000,
0x033, 0x00000004,
0x03D, 0x00000078,
0x03E, 0x00080000,
0x03F, 0x00000000,
0x033, 0x00000005,
0x03D, 0x0000007B,
0x03E, 0x00020000,
0x03F, 0x00000000,
0x0EC, 0x00000000,
0x0DE, 0x00000000,
0x0EF, 0x00000000,
0x033, 0x00000000,
0x008, 0x00060280,
0x009, 0x00030400,
0x0EF, 0x00000000,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x000001F7,
0x033, 0x00000003,
0x03F, 0x000000FF,
0x033, 0x00000004,
0x03F, 0x000000FF,
0x033, 0x00000005,
0x03F, 0x000000FF,
0x033, 0x00000006,
0x03F, 0x000000FF,
0x033, 0x00000007,
0x03F, 0x000000FF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x000001F7,
0x033, 0x00000003,
0x03F, 0x000000FF,
0x033, 0x00000004,
0x03F, 0x000000FF,
0x033, 0x00000005,
0x03F, 0x000000FF,
0x033, 0x00000006,
0x03F, 0x000000FF,
0x033, 0x00000007,
0x03F, 0x000000FF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x0000013F,
0x033, 0x00000003,
0x03F, 0x000000FB,
0x033, 0x00000004,
0x03F, 0x000000FB,
0x033, 0x00000005,
0x03F, 0x000000FB,
0x033, 0x00000006,
0x03F, 0x000000FB,
0x033, 0x00000007,
0x03F, 0x000000FB,
0xA0000000, 0x00000000,
0x0EF, 0x00000400,
0x033, 0x00000000,
0x03F, 0x000001FF,
0x033, 0x00000001,
0x03F, 0x000001FF,
0x033, 0x00000002,
0x03F, 0x000001F7,
0x033, 0x00000003,
0x03F, 0x000000FF,
0x033, 0x00000004,
0x03F, 0x000000FF,
0x033, 0x00000005,
0x03F, 0x000000FF,
0x033, 0x00000006,
0x03F, 0x000000FF,
0x033, 0x00000007,
0x03F, 0x000000FF,
0xB0000000, 0x00000000,
0x0EF, 0x00000200,
0x033, 0x00000000,
0x03F, 0x0000017F,
0x033, 0x00000001,
0x03F, 0x0000017F,
0x033, 0x00000002,
0x03F, 0x0000017F,
0x033, 0x00000003,
0x03F, 0x0000007F,
0x033, 0x00000004,
0x03F, 0x0000007F,
0x033, 0x00000005,
0x03F, 0x0000007F,
0x033, 0x00000006,
0x03F, 0x0000007F,
0x033, 0x00000007,
0x03F, 0x0000007F,
0x0EF, 0x00000000,
0x06E, 0x00077A18,
0x06F, 0x00077A18,
0x06D, 0x00000C31,
0x0EF, 0x00020000,
0x033, 0x00000000,
0x03F, 0x000005FF,
0x0EF, 0x00000000,
0x005, 0x00000001,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x094, 0x000000FC,
0xA0000000, 0x00000000,
0x094, 0x000001FC,
0xB0000000, 0x00000000,
0x100EE, 0x00002000,
0x10033, 0x00000080,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0xA0000000, 0x00000000,
0x1003F, 0x000000F6,
0xB0000000, 0x00000000,
0x10033, 0x00000081,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0xA0000000, 0x00000000,
0x1003F, 0x000000F3,
0xB0000000, 0x00000000,
0x10033, 0x00000082,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0xA0000000, 0x00000000,
0x1003F, 0x000000F0,
0xB0000000, 0x00000000,
0x10033, 0x00000083,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0xA0000000, 0x00000000,
0x1003F, 0x000000ED,
0xB0000000, 0x00000000,
0x10033, 0x00000084,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0xA0000000, 0x00000000,
0x1003F, 0x000000EA,
0xB0000000, 0x00000000,
0x10033, 0x00000085,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0xA0000000, 0x00000000,
0x1003F, 0x000000E7,
0xB0000000, 0x00000000,
0x10033, 0x00000086,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0xA0000000, 0x00000000,
0x1003F, 0x000000A6,
0xB0000000, 0x00000000,
0x10033, 0x00000087,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0xA0000000, 0x00000000,
0x1003F, 0x000000A3,
0xB0000000, 0x00000000,
0x10033, 0x00000088,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0xA0000000, 0x00000000,
0x1003F, 0x00000063,
0xB0000000, 0x00000000,
0x10033, 0x00000089,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0xA0000000, 0x00000000,
0x1003F, 0x00000060,
0xB0000000, 0x00000000,
0x10033, 0x0000008A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0xA0000000, 0x00000000,
0x1003F, 0x00000026,
0xB0000000, 0x00000000,
0x10033, 0x0000008B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0xA0000000, 0x00000000,
0x1003F, 0x00000023,
0xB0000000, 0x00000000,
0x10033, 0x0000008C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0xA0000000, 0x00000000,
0x1003F, 0x00000020,
0xB0000000, 0x00000000,
0x10033, 0x0000008D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0xA0000000, 0x00000000,
0x1003F, 0x0000001D,
0xB0000000, 0x00000000,
0x10033, 0x0000008E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x0000001A,
0xB0000000, 0x00000000,
0x10033, 0x0000008F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0xA0000000, 0x00000000,
0x1003F, 0x00000017,
0xB0000000, 0x00000000,
0x10033, 0x00000090,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000014,
0xB0000000, 0x00000000,
0x10033, 0x000000A0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0xA0000000, 0x00000000,
0x1003F, 0x000000F6,
0xB0000000, 0x00000000,
0x10033, 0x000000A1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0xA0000000, 0x00000000,
0x1003F, 0x000000F3,
0xB0000000, 0x00000000,
0x10033, 0x000000A2,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0xA0000000, 0x00000000,
0x1003F, 0x000000F0,
0xB0000000, 0x00000000,
0x10033, 0x000000A3,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0xA0000000, 0x00000000,
0x1003F, 0x000000ED,
0xB0000000, 0x00000000,
0x10033, 0x000000A4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0xA0000000, 0x00000000,
0x1003F, 0x000000EA,
0xB0000000, 0x00000000,
0x10033, 0x000000A5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0xA0000000, 0x00000000,
0x1003F, 0x000000E7,
0xB0000000, 0x00000000,
0x10033, 0x000000A6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0xA0000000, 0x00000000,
0x1003F, 0x000000A6,
0xB0000000, 0x00000000,
0x10033, 0x000000A7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0xA0000000, 0x00000000,
0x1003F, 0x000000A3,
0xB0000000, 0x00000000,
0x10033, 0x000000A8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0xA0000000, 0x00000000,
0x1003F, 0x00000063,
0xB0000000, 0x00000000,
0x10033, 0x000000A9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0xA0000000, 0x00000000,
0x1003F, 0x00000060,
0xB0000000, 0x00000000,
0x10033, 0x000000AA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0xA0000000, 0x00000000,
0x1003F, 0x00000026,
0xB0000000, 0x00000000,
0x10033, 0x000000AB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0xA0000000, 0x00000000,
0x1003F, 0x00000023,
0xB0000000, 0x00000000,
0x10033, 0x000000AC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0xA0000000, 0x00000000,
0x1003F, 0x00000020,
0xB0000000, 0x00000000,
0x10033, 0x000000AD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0xA0000000, 0x00000000,
0x1003F, 0x0000001D,
0xB0000000, 0x00000000,
0x10033, 0x000000AE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x0000001A,
0xB0000000, 0x00000000,
0x10033, 0x000000AF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0xA0000000, 0x00000000,
0x1003F, 0x00000017,
0xB0000000, 0x00000000,
0x10033, 0x000000B0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000014,
0xB0000000, 0x00000000,
0x10033, 0x000000C0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000FB,
0xA0000000, 0x00000000,
0x1003F, 0x000000F6,
0xB0000000, 0x00000000,
0x10033, 0x000000C1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F8,
0xA0000000, 0x00000000,
0x1003F, 0x000000F3,
0xB0000000, 0x00000000,
0x10033, 0x000000C2,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F5,
0xA0000000, 0x00000000,
0x1003F, 0x000000F0,
0xB0000000, 0x00000000,
0x10033, 0x000000C3,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000F2,
0xA0000000, 0x00000000,
0x1003F, 0x000000ED,
0xB0000000, 0x00000000,
0x10033, 0x000000C4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EF,
0xA0000000, 0x00000000,
0x1003F, 0x000000EA,
0xB0000000, 0x00000000,
0x10033, 0x000000C5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000EC,
0xA0000000, 0x00000000,
0x1003F, 0x000000E7,
0xB0000000, 0x00000000,
0x10033, 0x000000C6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000AB,
0xA0000000, 0x00000000,
0x1003F, 0x000000A6,
0xB0000000, 0x00000000,
0x10033, 0x000000C7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000A8,
0xA0000000, 0x00000000,
0x1003F, 0x000000A3,
0xB0000000, 0x00000000,
0x10033, 0x000000C8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000068,
0xA0000000, 0x00000000,
0x1003F, 0x00000063,
0xB0000000, 0x00000000,
0x10033, 0x000000C9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000065,
0xA0000000, 0x00000000,
0x1003F, 0x00000060,
0xB0000000, 0x00000000,
0x10033, 0x000000CA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000002B,
0xA0000000, 0x00000000,
0x1003F, 0x00000026,
0xB0000000, 0x00000000,
0x10033, 0x000000CB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000028,
0xA0000000, 0x00000000,
0x1003F, 0x00000023,
0xB0000000, 0x00000000,
0x10033, 0x000000CC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000025,
0xA0000000, 0x00000000,
0x1003F, 0x00000020,
0xB0000000, 0x00000000,
0x10033, 0x000000CD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000022,
0xA0000000, 0x00000000,
0x1003F, 0x0000001D,
0xB0000000, 0x00000000,
0x10033, 0x000000CE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x0000001A,
0xB0000000, 0x00000000,
0x10033, 0x000000CF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001C,
0xA0000000, 0x00000000,
0x1003F, 0x00000017,
0xB0000000, 0x00000000,
0x10033, 0x000000D0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000014,
0xB0000000, 0x00000000,
0x100EE, 0x00000000,
0x100EE, 0x00004000,
0x10033, 0x00000080,
0x1003F, 0x000001A9,
0x10033, 0x00000081,
0x1003F, 0x000001A3,
0x10033, 0x00000082,
0x1003F, 0x0000019D,
0x10033, 0x00000083,
0x1003F, 0x00000197,
0x10033, 0x00000084,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0xA0000000, 0x00000000,
0x1003F, 0x00000191,
0xB0000000, 0x00000000,
0x10033, 0x00000085,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0xA0000000, 0x00000000,
0x1003F, 0x0000018B,
0xB0000000, 0x00000000,
0x10033, 0x00000086,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0xA0000000, 0x00000000,
0x1003F, 0x0000014D,
0xB0000000, 0x00000000,
0x10033, 0x00000087,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0xA0000000, 0x00000000,
0x1003F, 0x0000010B,
0xB0000000, 0x00000000,
0x10033, 0x00000088,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0xA0000000, 0x00000000,
0x1003F, 0x000000DF,
0xB0000000, 0x00000000,
0x10033, 0x00000089,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0xA0000000, 0x00000000,
0x1003F, 0x000000D9,
0xB0000000, 0x00000000,
0x10033, 0x0000008A,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0xA0000000, 0x00000000,
0x1003F, 0x000000D3,
0xB0000000, 0x00000000,
0x10033, 0x0000008B,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0xA0000000, 0x00000000,
0x1003F, 0x00000099,
0xB0000000, 0x00000000,
0x10033, 0x0000008C,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0xA0000000, 0x00000000,
0x1003F, 0x00000093,
0xB0000000, 0x00000000,
0x10033, 0x0000008D,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x00000059,
0xB0000000, 0x00000000,
0x10033, 0x0000008E,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000053,
0xB0000000, 0x00000000,
0x10033, 0x0000008F,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0xA0000000, 0x00000000,
0x1003F, 0x00000019,
0xB0000000, 0x00000000,
0x10033, 0x00000090,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0xA0000000, 0x00000000,
0x1003F, 0x00000013,
0xB0000000, 0x00000000,
0x10033, 0x00000091,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0xA0000000, 0x00000000,
0x1003F, 0x0000000D,
0xB0000000, 0x00000000,
0x10033, 0x000000A0,
0x1003F, 0x000001A9,
0x10033, 0x000000A1,
0x1003F, 0x000001A3,
0x10033, 0x000000A2,
0x1003F, 0x0000019D,
0x10033, 0x000000A3,
0x1003F, 0x00000197,
0x10033, 0x000000A4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0xA0000000, 0x00000000,
0x1003F, 0x00000191,
0xB0000000, 0x00000000,
0x10033, 0x000000A5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0xA0000000, 0x00000000,
0x1003F, 0x0000018B,
0xB0000000, 0x00000000,
0x10033, 0x000000A6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0xA0000000, 0x00000000,
0x1003F, 0x0000014D,
0xB0000000, 0x00000000,
0x10033, 0x000000A7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0xA0000000, 0x00000000,
0x1003F, 0x0000010B,
0xB0000000, 0x00000000,
0x10033, 0x000000A8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0xA0000000, 0x00000000,
0x1003F, 0x000000DF,
0xB0000000, 0x00000000,
0x10033, 0x000000A9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0xA0000000, 0x00000000,
0x1003F, 0x000000D9,
0xB0000000, 0x00000000,
0x10033, 0x000000AA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0xA0000000, 0x00000000,
0x1003F, 0x000000D3,
0xB0000000, 0x00000000,
0x10033, 0x000000AB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0xA0000000, 0x00000000,
0x1003F, 0x00000099,
0xB0000000, 0x00000000,
0x10033, 0x000000AC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0xA0000000, 0x00000000,
0x1003F, 0x00000093,
0xB0000000, 0x00000000,
0x10033, 0x000000AD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x00000059,
0xB0000000, 0x00000000,
0x10033, 0x000000AE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000053,
0xB0000000, 0x00000000,
0x10033, 0x000000AF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0xA0000000, 0x00000000,
0x1003F, 0x00000019,
0xB0000000, 0x00000000,
0x10033, 0x000000B0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0xA0000000, 0x00000000,
0x1003F, 0x00000013,
0xB0000000, 0x00000000,
0x10033, 0x000000B1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0xA0000000, 0x00000000,
0x1003F, 0x0000000D,
0xB0000000, 0x00000000,
0x10033, 0x000000C0,
0x1003F, 0x000001A9,
0x10033, 0x000000C1,
0x1003F, 0x000001A3,
0x10033, 0x000000C2,
0x1003F, 0x0000019D,
0x10033, 0x000000C3,
0x1003F, 0x00000197,
0x10033, 0x000000C4,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000158,
0xA0000000, 0x00000000,
0x1003F, 0x00000191,
0xB0000000, 0x00000000,
0x10033, 0x000000C5,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000011F,
0xA0000000, 0x00000000,
0x1003F, 0x0000018B,
0xB0000000, 0x00000000,
0x10033, 0x000000C6,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000119,
0xA0000000, 0x00000000,
0x1003F, 0x0000014D,
0xB0000000, 0x00000000,
0x10033, 0x000000C7,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000DF,
0xA0000000, 0x00000000,
0x1003F, 0x0000010B,
0xB0000000, 0x00000000,
0x10033, 0x000000C8,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x000000D9,
0xA0000000, 0x00000000,
0x1003F, 0x000000DF,
0xB0000000, 0x00000000,
0x10033, 0x000000C9,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000009F,
0xA0000000, 0x00000000,
0x1003F, 0x000000D9,
0xB0000000, 0x00000000,
0x10033, 0x000000CA,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000099,
0xA0000000, 0x00000000,
0x1003F, 0x000000D3,
0xB0000000, 0x00000000,
0x10033, 0x000000CB,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000005F,
0xA0000000, 0x00000000,
0x1003F, 0x00000099,
0xB0000000, 0x00000000,
0x10033, 0x000000CC,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000059,
0xA0000000, 0x00000000,
0x1003F, 0x00000093,
0xB0000000, 0x00000000,
0x10033, 0x000000CD,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000001F,
0xA0000000, 0x00000000,
0x1003F, 0x00000059,
0xB0000000, 0x00000000,
0x10033, 0x000000CE,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000019,
0xA0000000, 0x00000000,
0x1003F, 0x00000053,
0xB0000000, 0x00000000,
0x10033, 0x000000CF,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000013,
0xA0000000, 0x00000000,
0x1003F, 0x00000019,
0xB0000000, 0x00000000,
0x10033, 0x000000D0,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x0000000D,
0xA0000000, 0x00000000,
0x1003F, 0x00000013,
0xB0000000, 0x00000000,
0x10033, 0x000000D1,
0x80010000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020000, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90010001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90020001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90030001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0x90040001, 0x00000000, 0x40000000, 0x00000000,
0x1003F, 0x00000007,
0xA0000000, 0x00000000,
0x1003F, 0x0000000D,
0xB0000000, 0x00000000,
0x100EE, 0x00000000,
0x100EE, 0x00002000,
0x10033, 0x00000000,
0x1003F, 0x000000F6,
0x10033, 0x00000001,
0x1003F, 0x000000F3,
0x10033, 0x00000002,
0x1003F, 0x000000F0,
0x10033, 0x00000003,
0x1003F, 0x000000ED,
0x10033, 0x00000004,
0x1003F, 0x000000EA,
0x10033, 0x00000005,
0x1003F, 0x000000E7,
0x10033, 0x00000006,
0x1003F, 0x000000A6,
0x10033, 0x00000007,
0x1003F, 0x000000A3,
0x10033, 0x00000008,
0x1003F, 0x00000063,
0x10033, 0x00000009,
0x1003F, 0x00000060,
0x10033, 0x0000000A,
0x1003F, 0x00000023,
0x10033, 0x0000000B,
0x1003F, 0x00000020,
0x10033, 0x0000000C,
0x1003F, 0x0000001D,
0x10033, 0x0000000D,
0x1003F, 0x0000001A,
0x10033, 0x0000000E,
0x1003F, 0x00000017,
0x10033, 0x0000000F,
0x1003F, 0x00000014,
0x10033, 0x00000010,
0x1003F, 0x00000011,
0x100EE, 0x00000000,
0x100EE, 0x00004000,
0x10033, 0x00000000,
0x1003F, 0x000001AF,
0x10033, 0x00000001,
0x1003F, 0x000001A9,
0x10033, 0x00000002,
0x1003F, 0x000001A3,
0x10033, 0x00000003,
0x1003F, 0x0000019D,
0x10033, 0x00000004,
0x1003F, 0x00000197,
0x10033, 0x00000005,
0x1003F, 0x0000015F,
0x10033, 0x00000006,
0x1003F, 0x00000159,
0x10033, 0x00000007,
0x1003F, 0x0000011F,
0x10033, 0x00000008,
0x1003F, 0x00000119,
0x10033, 0x00000009,
0x1003F, 0x000000DF,
0x10033, 0x0000000A,
0x1003F, 0x000000D9,
0x10033, 0x0000000B,
0x1003F, 0x0000009F,
0x10033, 0x0000000C,
0x1003F, 0x00000099,
0x10033, 0x0000000D,
0x1003F, 0x0000005F,
0x10033, 0x0000000E,
0x1003F, 0x00000059,
0x10033, 0x0000000F,
0x1003F, 0x0000001F,
0x10033, 0x00000010,
0x1003F, 0x00000019,
0x10033, 0x00000011,
0x1003F, 0x00000013,
0x100EE, 0x00000000,
0x10005, 0x00000001,
0x09F, 0x00000019,
};
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
const struct halrf_tx_pw_lmt array_mp_8852b_txpwr_lmt[] = {
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 80, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 72, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 72, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 58, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 70, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 58, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 76, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 56, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 56, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 44, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 58, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 44, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 68, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 68, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 52, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 44, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 44, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 32, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 74, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 32, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 48, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 48, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 48, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 48, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 48, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 48, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 64, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 64, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 36, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 36, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 36, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 36, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 36, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 36, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 32, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 32, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 32, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 32, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 1},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_CCK, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 52, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 52, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 66, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 52, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 78, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 52, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 1, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 1, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 1, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 1, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 1, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 2, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 2, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 2, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 2, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 2, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 3, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 3, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 3, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 3, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 3, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 4, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 4, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 4, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 4, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 4, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 5, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 5, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 5, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 6, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 6, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 6, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 7, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 7, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 7, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 7, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 7, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 8, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 8, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 8, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 8, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 8, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 9, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 9, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 9, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 9, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 9, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 10, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 10, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 10, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 10, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 10, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 11, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 11, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 11, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 11, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 11, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 12, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 12, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 12, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 13, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 13, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 13, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 76, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 60, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 1, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 1, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 2, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 2, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 3, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 3, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 3, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 3, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 4, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 4, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 4, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 4, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 5, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 5, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 5, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 5, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 6, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 6, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 6, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 6, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 7, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 7, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 7, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 7, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 8, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 8, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 8, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 8, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 9, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 9, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 9, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 9, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 10, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 10, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 10, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 10, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 11, 40, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 11, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 11, 40, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 11, 48, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 12, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 12, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 13, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 13, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 1, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 1, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 1, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 2, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 2, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 2, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 3, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 3, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 3, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 3, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 3, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 4, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 4, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 4, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 4, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 4, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 5, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 5, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 5, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 5, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 5, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 6, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 6, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 6, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 6, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 6, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 7, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 7, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 7, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 7, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 7, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 8, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 8, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 8, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 8, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 8, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 9, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 9, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 9, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 9, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 9, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 10, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 10, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 10, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 10, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 10, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 11, 40, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 11, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 11, 68, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 11, 40, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 11, 36, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 12, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 12, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 12, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 13, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 13, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 13, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 74, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_OFDM, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 62, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 36, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 36, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 36, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 36, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 36, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 40, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 40, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 40, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 40, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 40, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 44, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 44, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 44, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 44, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 44, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 48, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 48, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 48, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 48, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 48, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 52, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 52, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 52, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 52, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 52, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 56, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 56, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 56, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 56, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 56, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 60, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 60, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 60, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 60, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 60, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 64, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 64, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 64, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 64, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 64, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 100, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 100, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 100, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 100, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 100, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 104, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 104, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 104, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 104, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 104, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 108, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 108, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 108, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 108, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 108, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 112, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 112, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 112, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 112, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 112, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 116, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 116, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 116, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 116, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 116, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 120, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 120, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 120, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 124, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 124, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 124, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 128, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 128, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 128, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 132, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 132, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 132, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 132, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 132, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 136, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 136, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 136, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 136, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 136, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 140, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 140, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 140, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 140, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 140, 50, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 144, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 144, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 144, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 144, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 149, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 149, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 153, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 153, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 157, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 157, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 161, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 161, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 165, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 165, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 169, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 173, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 177, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 36, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 36, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 36, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 36, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 36, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 40, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 40, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 40, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 40, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 40, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 44, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 44, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 44, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 44, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 44, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 48, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 48, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 48, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 48, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 48, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 52, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 52, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 52, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 52, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 52, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 56, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 56, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 56, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 56, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 56, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 60, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 60, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 60, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 60, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 60, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 64, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 64, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 64, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 64, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 64, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 100, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 100, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 100, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 100, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 100, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 104, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 104, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 104, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 104, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 104, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 108, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 108, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 108, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 108, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 108, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 112, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 112, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 112, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 112, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 112, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 116, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 116, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 116, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 116, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 116, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 120, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 120, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 120, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 124, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 124, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 124, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 128, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 128, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 128, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 132, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 132, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 132, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 132, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 132, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 136, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 136, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 136, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 136, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 136, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 140, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 140, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 140, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 140, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 140, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 144, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 144, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 144, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 144, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 149, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 149, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 149, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 153, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 153, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 153, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 157, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 157, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 157, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 161, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 161, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 161, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 165, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 165, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 165, 78, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 169, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 173, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 177, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_20M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 38, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 38, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 38, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 38, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 38, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 46, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 46, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 46, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 46, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 46, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 54, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 54, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 54, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 54, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 54, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 62, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 62, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 62, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 62, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 62, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 102, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 102, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 102, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 102, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 102, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 110, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 110, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 110, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 110, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 110, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 118, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 118, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 118, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 118, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 118, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 126, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 126, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 126, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 126, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 126, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 134, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 134, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 134, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 134, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 134, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 142, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 142, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 142, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 142, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 142, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 151, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 151, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 151, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 151, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 151, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 159, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 159, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 159, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 159, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 159, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 167, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 167, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 175, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 175, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 38, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 38, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 38, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 38, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 38, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 46, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 46, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 46, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 46, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 46, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 54, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 54, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 54, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 54, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 54, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 62, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 62, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 62, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 62, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 62, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 102, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 102, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 102, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 102, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 102, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 110, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 110, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 110, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 110, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 110, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 118, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 118, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 118, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 118, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 118, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 126, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 126, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 126, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 126, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 126, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 134, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 134, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 134, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 134, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 134, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 142, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 142, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 142, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 142, 78, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 142, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 151, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 151, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 151, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 151, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 151, 74, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 159, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 159, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 159, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 159, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 159, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 167, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 167, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 175, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 175, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 38, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 38, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 38, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 38, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 38, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 46, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 46, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 46, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 46, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 46, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 54, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 54, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 54, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 54, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 54, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 62, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 62, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 62, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 62, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 62, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 102, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 102, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 102, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 102, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 102, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 110, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 110, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 110, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 110, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 110, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 118, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 118, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 118, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 118, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 118, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 126, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 126, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 126, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 126, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 126, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 134, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 134, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 134, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 134, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 134, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 142, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 142, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 142, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 142, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 142, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 151, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 151, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 151, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 151, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 151, 74, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 159, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 159, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 159, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 159, 80, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 159, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 167, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 167, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 167, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 175, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 175, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_40M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 175, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 42, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 42, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 42, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 42, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 42, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 58, 68, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 58, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 58, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 58, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 58, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 106, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 106, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 106, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 106, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 106, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 122, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 122, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 122, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 122, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 122, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 138, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 138, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 138, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 138, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 138, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 155, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 155, 30, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 155, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 155, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 155, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 171, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 171, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 42, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 42, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 42, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 42, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 42, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 58, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 58, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 58, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 58, 54, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 58, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 106, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 106, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 106, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 106, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 106, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 122, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 122, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 122, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 122, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 122, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 138, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 138, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 138, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 138, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 138, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 155, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 155, 18, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 155, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 155, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 155, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_FCC, 171, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ETSI, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_MKK, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_IC, 171, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_NONBF, PW_LMT_REGU_ACMA, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 42, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 42, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 42, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 42, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 42, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 58, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 58, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 58, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 58, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 58, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 106, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 106, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 106, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 106, 58, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 106, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 122, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 122, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 122, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 122, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 122, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 138, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 138, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 138, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 138, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 138, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 155, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 155, 6, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 155, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 155, 76, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 155, 72, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_FCC, 171, 60, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ETSI, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_MKK, 171, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_IC, 171, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_BW_80M, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_BF, PW_LMT_REGU_ACMA, 171, 127, 0}
};
/******************************************************************************
* txpwr_lmt_ru.TXT
******************************************************************************/
const struct halrf_tx_pw_lmt_ru array_mp_8852b_txpwr_lmt_ru[] = {
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 32, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 32, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 62, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 20, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 62, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 20, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 62, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 62, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 30, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 68, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 64, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 52, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 52, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 22, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 30, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 20, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 30, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 30, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 20, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 82, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 82, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 72, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 38, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 38, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 48, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 32, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 40, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 32, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 32, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 84, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 76, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 66, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 64, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 56, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 56, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 1, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 1, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 1, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 1, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 1, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 2, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 2, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 2, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 2, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 2, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 3, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 3, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 3, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 3, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 3, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 4, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 4, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 4, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 4, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 4, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 5, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 5, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 5, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 5, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 6, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 6, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 6, 80, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 6, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 7, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 7, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 7, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 7, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 7, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 8, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 8, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 8, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 8, 78, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 8, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 9, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 9, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 9, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 9, 74, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 9, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 10, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 10, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 10, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 10, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 10, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 11, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 11, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 11, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 11, 70, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 11, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 12, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 12, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 12, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 12, 60, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 12, 44, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 13, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 13, 52, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 13, 44, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 13, 42, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 14, 127, 0},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 14, 127, 3},
{PW_LMT_BAND_2_4G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 14, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 26, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 24, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 26, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 24, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 26, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 24, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 26, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 24, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 26, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 26, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 46, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 24, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 32, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 32, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 32, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 0, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 4, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 14, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 0, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 14, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 0, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 14, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 14, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 32, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 34, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 12, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 38, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 82, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 20, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 20, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 20, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 36, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 36, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 36, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 36, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 58, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 62, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 52, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 64, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 64, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 10, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 14, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 20, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 10, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 20, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 10, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 20, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 20, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 46, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 46, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 40, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 42, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 40, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 40, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 44, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 38, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 22, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 48, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 42, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 48, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 82, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 82, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 32, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 32, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 32, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 46, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 46, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 46, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 46, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 46, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 46, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 66, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 68, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 70, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 72, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 48, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 66, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 70, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 76, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 28, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 56, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 56, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 56, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 36, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 36, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 36, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 36, 20, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 36, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 40, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 40, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 40, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 40, 18, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 40, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 44, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 44, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 44, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 44, 22, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 44, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 48, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 48, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 48, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 48, 22, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 48, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 52, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 52, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 52, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 52, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 52, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 56, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 56, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 56, 34, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 56, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 56, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 60, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 60, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 60, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 60, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 60, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 64, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 64, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 64, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 64, 52, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 64, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 100, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 100, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 100, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 100, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 100, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 104, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 104, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 104, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 104, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 104, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 108, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 108, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 108, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 108, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 108, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 112, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 112, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 112, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 112, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 112, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 116, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 116, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 116, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 116, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 116, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 120, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 120, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 120, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 120, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 120, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 124, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 124, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 124, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 124, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 124, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 128, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 128, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 128, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 128, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 128, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 132, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 132, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 132, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 132, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 132, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 136, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 136, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 136, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 136, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 136, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 140, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 140, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 140, 56, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 140, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 140, 36, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 144, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 144, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 144, 54, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 144, 50, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 144, 60, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 149, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 149, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 149, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 149, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 153, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 153, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 153, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 153, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 157, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 157, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 157, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 157, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 161, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 161, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 161, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 161, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 165, 16, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 165, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 165, 84, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 165, 84, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 169, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 169, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 169, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 173, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 173, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 173, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_FCC, 177, 44, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ETSI, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_MKK, 177, 127, 0},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_IC, 177, 127, 3},
{PW_LMT_BAND_5G, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, PW_LMT_RS_HE, PW_LMT_REGU_ACMA, 177, 127, 0}
};
/******************************************************************************
* txpwr_tracktssi.TXT
******************************************************************************/
const s8 delta_swingidx_mp_5gb_n_txpwrtrkssi_8852b[][D_S_SIZE] = {
{0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,
4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8},
{0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8},
{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7,
7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12},
};
const s8 delta_swingidx_mp_5gb_p_txpwrtrkssi_8852b[][D_S_SIZE] = {
{0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8},
{0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,
4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8},
{0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},
};
const s8 delta_swingidx_mp_5ga_n_txpwrtrkssi_8852b[][D_S_SIZE] = {
{0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2,
2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4},
{0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3},
{0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3},
};
const s8 delta_swingidx_mp_5ga_p_txpwrtrkssi_8852b[][D_S_SIZE] = {
{0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7},
{0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5,
5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},
{0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5,
5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9},
};
const s8 delta_swingidx_mp_2gb_n_txpwrtrkssi_8852b[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2, -2};
const s8 delta_swingidx_mp_2gb_p_txpwrtrkssi_8852b[] = {
0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3,
3, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 6, 6};
const s8 delta_swingidx_mp_2ga_n_txpwrtrkssi_8852b[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
const s8 delta_swingidx_mp_2ga_p_txpwrtrkssi_8852b[] = {
0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3,
3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5};
const s8 delta_swingidx_mp_2g_cck_b_n_txpwrtrkssi_8852b[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
const s8 delta_swingidx_mp_2g_cck_b_p_txpwrtrkssi_8852b[] = {
0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6};
const s8 delta_swingidx_mp_2g_cck_a_n_txpwrtrkssi_8852b[] = {
0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -2, -2,
-2, -2, -2, -2, -2, -2, -3, -3, -3, -3, -3, -3, -3};
const s8 delta_swingidx_mp_2g_cck_a_p_txpwrtrkssi_8852b[] = {
0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
/******************************************************************************
* txpwr_byrate.TXT
******************************************************************************/
const u32 array_mp_8852b_txpwr_byrate[] = {
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_11M_1M , 0x50505050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_18M_6M , 0x50505050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_54M_24M, 0x484c5050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS3_0 , 0x50505050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS7_4 , 0x44484c50,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS11_8, 0x34383c40,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_DCM4_0 , 0x50505050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS3_0 , 0x50505050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS7_4 , 0x44484c50,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS11_8, 0x34383c40,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_DCM4_0 , 0x50505050,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_OFFS, PW_BYRATE_RATE_AllRate2_1, 0x00000000,
PW_LMT_BAND_2_4G, PW_BYRATE_PARA_OFFS, PW_BYRATE_RATE_AllRate2_2, 0x00000000,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_18M_6M , 0x50505050,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_54M_24M, 0x484c5050,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS3_0 , 0x50505050,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS7_4 , 0x44484c50,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_MCS11_8, 0x34383c40,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS1, PW_BYRATE_RATE_DCM4_0 , 0x50505050,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS3_0 , 0x50505050,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS7_4 , 0x44484c50,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_MCS11_8, 0x34383c40,
PW_LMT_BAND_5G, PW_BYRATE_PARA_NSS2, PW_BYRATE_RATE_DCM4_0 , 0x50505050,
PW_LMT_BAND_5G, PW_BYRATE_PARA_OFFS, PW_BYRATE_RATE_AllRate5_1, 0x00000000
};
#endif /* _HALRF_HWIMG_RAW_DATA_8852B_H */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_hwimg_raw_data_8852b.h
|
C
|
agpl-3.0
| 549,317
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
#ifndef __iram_func__
#define __iram_func__
#endif
const u32 array_set_nondbcc_path01_8852b[] = {
//02_BB_AFE_Non_DBCC_PHY0_path01
0x20fc, 0xffff0000, 0x0303,
0x5864, 0x18000000, 0x3,
0x7864, 0x18000000, 0x3,
0x12b8, 0x40000000, 0x1,
0x32b8, 0x40000000, 0x1,
0x030c, 0xff000000, 0x13,
0x032c, 0xffff0000, 0x0041,
0x12b8, 0x10000000, 0x1,
0x58c8, 0x01000000, 0x1,
0x78c8, 0x01000000, 0x1,
0x5864, 0xc0000000, 0x3,
0x7864, 0xc0000000, 0x3,
0x2008, 0x01ffffff, 0x1ffffff,
0x0c1c, 0x00000004, 0x1,
0x0700, 0x08000000, 0x1,
0x0c70, 0x000003ff, 0x3ff,
0x0c60, 0x00000003, 0x3,
0x0c6c, 0x00000001, 0x1,
0x58ac, 0x08000000, 0x1,
0x78ac, 0x08000000, 0x1,
0x0c3c, 0x00000200, 0x1,
0x2344, 0x80000000, 0x1,
0x4490, 0x80000000, 0x1,
0x12a0, 0x00007000, 0x7,
0x12a0, 0x00008000, 0x1,
0x12a0, 0x00070000, 0x3,
0x12a0, 0x00080000, 0x1,
0x32a0, 0x00070000, 0x3,
0x32a0, 0x00080000, 0x1,
0x0700, 0x01000000, 0x1,
0x0700, 0x06000000, 0x2,
0x20fc, 0xffff0000, 0x3333,
};
const u32 array_restore_nondbcc_path01_8852b[] = {
//99_BB_AFE_Non_DBCC_PHY0_path01_restore
0x20fc, 0xffff0000, 0x0303,
0x12b8, 0x40000000, 0x0,
0x32b8, 0x40000000, 0x0,
0x5864, 0xc0000000, 0x0,
0x7864, 0xc0000000, 0x0,
0x2008, 0x01ffffff, 0x0000000,
0x0c1c, 0x00000004, 0x0,
0x0700, 0x08000000, 0x0,
0x0c70, 0x0000001f, 0x03,
0x0c70, 0x000003e0, 0x03,
0x12a0, 0x000ff000, 0x00,
0x32a0, 0x000ff000, 0x00,
0x0700, 0x07000000, 0x0,
0x20fc, 0xffff0000, 0x0000,
0x58c8, 0x01000000, 0x0,
0x78c8, 0x01000000, 0x0,
0x0c3c, 0x00000200, 0x0,
0x2344, 0x80000000, 0x0,
};
__iram_func__
void iqk_backup_rf0_8852b(
struct rf_info *rf, u8 path,
u32 backup_rf0[rf_reg_num_8852b],
u32 backup_rf_reg0[rf_reg_num_8852b])
{
u8 i;
if(path != RF_PATH_A)
return;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
for (i = 0; i < rf_reg_num_8852b; i++) {
backup_rf0[i] = halrf_rrf(rf, RF_PATH_A, backup_rf_reg0[i], MASKRF);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]bk rf0, %x = %x\n", backup_rf_reg0[i], backup_rf0[i]);
}
return;
}
__iram_func__
void iqk_backup_rf1_8852b(
struct rf_info *rf, u8 path,
u32 backup_rf1[rf_reg_num_8852b],
u32 backup_rf_reg1[rf_reg_num_8852b])
{
u8 i;
if(path != RF_PATH_B)
return;
//DBG_LOG_SERIOUS(DBGMSG_RF, DBG_WARNING, "[IQK] 06 \n");
for (i = 0; i < rf_reg_num_8852b; i++) {
backup_rf1[i] = halrf_rrf(rf, RF_PATH_B, backup_rf_reg1[i], MASKRF);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]bk rf1, %x = %x\n", backup_rf_reg1[i], backup_rf1[i]);
}
return;
}
__iram_func__
void iqk_restore_rf0_8852b(
struct rf_info *rf, u8 path,
u32 backup_rf0[rf_reg_num_8852b],
u32 backup_rf_reg0[rf_reg_num_8852b])
{
u32 i = 0;
if(path != RF_PATH_A)
return;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
//DBG_LOG_SERIOUS(DBGMSG_RF, DBG_WARNING, "[IQK] 13 \n");
for (i = 0; i < rf_reg_num_8852b; i++) {
halrf_wrf(rf, RF_PATH_A, backup_rf_reg0[i], MASKRF, backup_rf0[i]);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]restore rf0, 0x%x = 0x%x\n", backup_rf_reg0[i], halrf_rrf(rf, 0x0, backup_rf_reg0[i], MASKRF));
}
return;
}
__iram_func__
void iqk_restore_rf1_8852b(
struct rf_info *rf, u8 path,
u32 backup_rf1[rf_reg_num_8852b],
u32 backup_rf_reg1[rf_reg_num_8852b])
{
u32 i;
if(path != RF_PATH_B)
return;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
for (i = 0; i < rf_reg_num_8852b; i++) {
halrf_wrf(rf, RF_PATH_B, backup_rf_reg1[i], MASKRF, backup_rf1[i]);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]restore rf S%d = %x, value = %x\n", path, backup_rf_reg[path][i], halrf_rrf(rf, path, backup_rf_reg[path][i], MASKRF));
}
return;
}
#if 0
static void _iqk_config_8852b_reg(struct rf_info *rf, u32 *array_map)
{
u32 i = 0;
u32 array_len = 0x0;
u32 *array = NULL;
u32 addr = 0, mask = 0, val = 0;
RF_DBG(rf, DBG_RF_INIT, "===> %s\n", __func__);
array_len = sizeof(array_map) / sizeof(u32);
array = (u32 *) &array_map;
while ((i + 1) < array_len) {
addr = array[i];
mask = array[i + 1];
val = array[i + 2];
halrf_wreg(rf, addr, mask, val);
RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, val);
i += 3;
}
}
#endif
__iram_func__
static void _iqk_read_fft_dbcc0_8852b(struct rf_info *rf, u8 path)
{
u8 i = 0x0;
u32 fft[6] = {0x0};
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00160000);
fft[0] = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00170000);
fft[1] = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00180000);
fft[2] = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00190000);
fft[3] = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x001a0000);
fft[4] = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x001b0000);
fft[5] = halrf_rreg(rf, 0x80fc, MASKDWORD);
for(i =0; i< 6; i++)
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x,fft[%x]= %x\n", path, i, fft[i]);
return;
}
__iram_func__
static void _iqk_read_xym_dbcc0_8852b(struct rf_info *rf, u8 path)
{
u8 i = 0x0;
u32 tmp = 0x0;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
halrf_wreg(rf, 0x8000, 0x00000006, path);
halrf_wreg(rf, 0x801c, 0x00000003, 0x1);
for (i = 0x0; i < 0x18; i++) {
halrf_wreg(rf, 0x8014, MASKDWORD, 0x000000c0 + i);
halrf_wreg(rf, 0x8014, MASKDWORD, 0x00000000);
tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x38 = %x\n", path, 1 << path, tmp);
halrf_delay_us(rf, 1);
}
halrf_wreg(rf, 0x801c, 0x00000003, 0x0);
halrf_wreg(rf, 0x8138+ (path << 8), MASKDWORD, 0x40000000);
halrf_wreg(rf, 0x8014, MASKDWORD, 0x80010100);
halrf_delay_us(rf, 1);
return;
}
__iram_func__
static void _iqk_read_txcfir_dbcc0_8852b(struct rf_info *rf, u8 path, u8 group)
{
u8 idx = 0x0;
u32 tmp = 0x0;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
halrf_wreg(rf, 0x81d8+ (path << 8), MASKDWORD, 0x00000001);
if (path == 0x0) {
switch (group) {
case 0:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x8f20 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8f20 + (idx << 2), tmp);
}
break;
case 1:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x8f54 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8f54 + (idx << 2), tmp);
}
break;
case 2:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x8f88 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8f88 + (idx << 2), tmp);
}
break;
case 3:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x8fbc + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x8fbc + (idx << 2), tmp);
}
break;
default:
break;
}
RF_DBG(rf, DBG_RF_IQK, "[IQK]\n");
tmp = halrf_rreg(rf, 0x8f50, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8f50 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x8f84, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8f84 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x8fb8, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8fb8 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x8fec, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8fec = %x\n", tmp);
} else {
switch (group) {
case 0:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x9320 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x9320 + (idx << 2), tmp);
}
break;
case 1:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x9354 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x9354 + (idx << 2), tmp);
}
break;
case 2:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x9388 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x9388 + (idx << 2), tmp);
}
break;
case 3:
for (idx = 0; idx < 0x0d; idx++) {
tmp = halrf_rreg(rf, 0x93bc + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] %x = %x\n", 0x93bc + (idx << 2), tmp);
}
break;
default:
break;
}
RF_DBG(rf, DBG_RF_IQK, "[IQK]\n");
tmp = halrf_rreg(rf, 0x9350, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9350 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x9384, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9384 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x93b8, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x93b8 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x93ec, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x93ec = %x\n", tmp);
}
halrf_wreg(rf, 0x81d8+ (path << 8), MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x81d4 + (path << 8), 0x003f0000, 0xc);
halrf_delay_us(rf, 1);
tmp = halrf_rreg(rf, 0x81fc + (path << 8), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%xfc = %x\n", path, 1 << path, tmp);
return;
}
__iram_func__
static void _iqk_read_rxcfir_dbcc0_8852b(struct rf_info *rf, u8 path, u8 group)
{
u8 idx = 0x0;
u32 tmp = 0x0;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00000001);
if (path == 0x0) {
switch (group) {
case 0:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x8d00 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8d00 + (idx << 2), tmp);
}
break;
case 1:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x8d44 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8d44 + (idx << 2), tmp);
}
break;
case 2:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x8d88 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8d88 + (idx << 2), tmp);
}
break;
case 3:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x8dcc + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x8dcc + (idx << 2), tmp);
}
break;
default:
break;
}
RF_DBG(rf, DBG_RF_IQK, "[IQK]\n");
tmp = halrf_rreg(rf, 0x8d40, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8d40 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x8d84, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8d84 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x8dc8, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8dc8 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x8e0c, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x8e0c = %x\n", tmp);
} else {
switch (group) {
case 0:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x9100 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x9100 + (idx << 2), tmp);
}
break;
case 1:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x9144 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x9144 + (idx << 2), tmp);
}
break;
case 2:
for(idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x9188 + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x9188 + (idx << 2), tmp);
}
break;
case 3:
for (idx = 0; idx < 0x10; idx++) {
tmp = halrf_rreg(rf, 0x91cc + (idx << 2), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]%x = %x\n", 0x91cc + (idx << 2), tmp);
}
break;
default:
break;
}
RF_DBG(rf, DBG_RF_IQK, "[IQK]\n");
tmp = halrf_rreg(rf, 0x9140, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9140 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x9184, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x9184 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x91c8, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x91c8 = %x\n", tmp);
tmp = halrf_rreg(rf, 0x920c, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK] 0x920c = %x\n", tmp);
}
halrf_wreg(rf, 0x81d8 + (path << 8), MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x81d4 + (path << 8), 0x003f0000, 0xd);
tmp = halrf_rreg(rf, 0x81fc + (path << 8), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%xfc = %x\n", path, 1 << path, tmp);
return;
}
__iram_func__
static void _iqk_sram_8852b(struct rf_info *rf, u8 path)
{
u32 tmp = 0x0;
u32 i = 0x0;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00020000);
halrf_wreg(rf, 0x80e8, MASKDWORD, 0x00000080);
halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000);
halrf_wreg(rf, 0x802c, 0x00000fff, 0x009);
for (i = 0; i <= 0x9f; i++) {
halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000 + i);
tmp = halrf_rreg(rf, 0x80fc, 0x0fff0000);
RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x\n", tmp);
}
for (i = 0; i <= 0x9f; i++) {
halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00010000 + i);
tmp = halrf_rreg(rf, 0x80fc, 0x00000fff);
RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x\n", tmp);
}
halrf_wreg(rf, 0x80e8, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x80d8, MASKDWORD, 0x00000000);
return;
}
__iram_func__
static void _iqk_rxk_setting_8852b(struct rf_info *rf, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 tmp = 0x0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x0, 0xf0000, 0xc);
halrf_wrf(rf, path, 0x20, 0x00100, 0x1);
tmp = halrf_rrf(rf, path, 0x18, MASKRF);
halrf_wrf(rf, path, 0x1f, 0xfffff, tmp);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x0, 0xf0000, 0xc);
halrf_wrf(rf, path, 0x20, 0x00080, 0x1);
tmp = halrf_rrf(rf, path, 0x18, MASKRF);
halrf_wrf(rf, path, 0x1f, 0xfffff, tmp);
break;
default:
break;
}
return;
}
__iram_func__
static bool _iqk_check_cal_8852b(struct rf_info *rf, u8 path, u8 ktype)
{
//struct halrf_iqk_info *iqk_info = &rf->iqk;
bool notready = true, fail = true;
u32 delay_count = 0x0;
//u32 tmp = 0x0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
delay_count = 0x0;
while (notready) {
if (halrf_rreg(rf, 0xbff8, MASKBYTE0) == 0x55) {
halrf_delay_us(rf, 1);
if(halrf_rreg(rf, 0x8010, MASKBYTE0) == 0x55)
notready = false;
} else {
halrf_delay_us(rf, 1);
delay_count++;
}
if (delay_count > 8200) {
fail = true;
RF_DBG(rf, DBG_RF_IQK, "[IQK]IQK timeout!!!\n");
break;
}
}
if (!notready)
fail = (bool)halrf_rreg(rf, 0x8008, BIT(26));
halrf_wreg(rf, 0x8010, MASKBYTE0, 0x0);
//DBG_LOG_SERIOUS(DBGMSG_RF, DBG_WARNING, "[IQK]%x\n", delay_count);
/*
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, cnt= %d\n", path, delay_count);
tmp = halrf_rreg(rf, 0x8008, MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, type= %x, 0x8008 = 0x%x \n", path, ktype, tmp);
*/
return fail;
}
__iram_func__
static bool _iqk_one_shot_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path, u8 ktype)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool fail = false;
u32 iqk_cmd = 0x0;
u8 phy_map;
u32 addr_rfc_ctl = 0x0;
phy_map = (BIT(phy_idx) << 4) | BIT(path);
addr_rfc_ctl = 0x5864;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
//halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_IQK, RFK_ONESHOT_START);
switch (ktype) {
case ID_TXAGC:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d TXAGC ============\n", path);
iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
break;
case ID_FLoK_coarse:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_FLoK_coarse ============\n", path);
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1);
iqk_cmd = 0x108 | (1 << (4 + path));
break;
case ID_FLoK_fine:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_FLoK_fine ============\n", path);
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1);
iqk_cmd = 0x208 | (1 << (4 + path));
break;
case ID_FLOK_vbuffer:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_FLoK_fine ============\n", path);
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1);
iqk_cmd = 0x308 | (1 << (4 + path));
break;
case ID_TXK:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_TXK ============\n", path);
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x0);
iqk_cmd = 0x008 | (1 << (path + 4)) | (((0x8 + iqk_info->iqk_bw[path] ) & 0xf) << 8);
break;
case ID_RXAGC:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_RXAGC ============\n", path);
iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
break;
case ID_RXK:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]============ S%d ID_RXK ============\n", path);
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1);
iqk_cmd = 0x008 | (1 << (path + 4)) | (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
break;
case ID_NBTXK:
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x0);
halrf_wreg(rf, 0x802c, 0x00000fff, 0x011);
iqk_cmd = 0x308 | (1 << (4 + path));
break;
case ID_NBRXK:
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x1);
halrf_wreg(rf, 0x802c, 0x0fff0000, 0x011);
iqk_cmd = 0x608 | (1 << (4 + path));
break;
default:
return false;
break;
}
halrf_wreg(rf, 0x8000, MASKDWORD, iqk_cmd + 1);
//halrf_delay_us(rf, 1);
halrf_delay_us(rf, 1);
fail = _iqk_check_cal_8852b(rf, path, ktype);
if (iqk_info->iqk_xym_en == true)
_iqk_read_xym_dbcc0_8852b(rf, path);
if (iqk_info->iqk_fft_en == true)
_iqk_read_fft_dbcc0_8852b(rf, path);
if (iqk_info->iqk_sram_en == true)
_iqk_sram_8852b(rf, path);
if (iqk_info->iqk_cfir_en == true) {
if (ktype == ID_TXK) {
_iqk_read_txcfir_dbcc0_8852b(rf, path, 0x0);
_iqk_read_txcfir_dbcc0_8852b(rf, path, 0x1);
_iqk_read_txcfir_dbcc0_8852b(rf, path, 0x2);
_iqk_read_txcfir_dbcc0_8852b(rf, path, 0x3);
} else {
_iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x0);
_iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x1);
_iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x2);
_iqk_read_rxcfir_dbcc0_8852b(rf, path, 0x3);
}
}
//8. IQK cotrol RFC
halrf_wreg(rf, addr_rfc_ctl, 0x20000000, 0x0);
//halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_IQK, RFK_ONESHOT_STOP);
return fail;
}
__iram_func__
static bool _rxk_group_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 gp = 0x0;
u32 a_idxrxgain[4] = {0x190, 0x198, 0x350, 0x352};
u32 a_idxattc2[4] = {0x0f, 0x0f, 0x3f, 0x7f};
u32 a_idxattc1[4] = {0x3, 0x1, 0x0, 0x0};
u32 g_idxrxgain[4] = {0x212, 0x21c, 0x350, 0x360};
u32 g_idxattc2[4] = {0x00, 0x00, 0x28, 0x5f};
u32 g_idxattc1[4] = {0x3, 0x3, 0x2, 0x1};
bool fail = false;
bool kfail = false;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
for (gp = 0; gp < 0x4; gp++) {
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x00, 0x03ff0, g_idxrxgain[gp]);
halrf_wrf(rf, path, 0x83, 0x1fc00, g_idxattc2[gp]);
halrf_wrf(rf, path, 0x83, 0x00300, g_idxattc1[gp]);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x00, 0x03ff0, a_idxrxgain[gp]);
halrf_wrf(rf, path, 0x8c, 0x0007f, a_idxattc2[gp]);
halrf_wrf(rf, path, 0x8c, 0x00180, a_idxattc1[gp]);
break;
default:
break;
}
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x0);
//halrf_wreg(rf, 0x8154 + (path << 8), 0x00000008, 0x0);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000007, gp);
fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_RXK);
halrf_wreg(rf, 0x9fe0, BIT(16 + gp + path * 4), fail);
kfail = kfail | fail;
}
halrf_wrf(rf, path, 0x20, 0x00080, 0x0);
if (kfail) {
iqk_info->nb_rxcfir[path] = 0x40000002;
halrf_wreg(rf, 0x8124 + (path << 8), 0x0000000f, 0x0);
iqk_info->is_wb_rxiqk[path] = false;
} else {
iqk_info->nb_rxcfir[path] = 0x40000000;
halrf_wreg(rf, 0x8124 + (path << 8), 0x0000000f, 0x5);
iqk_info->is_wb_rxiqk[path] = true;
}
/*
tmp = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x3c = 0x%x\n", path, 1 << path, tmp);
*/
return kfail;
}
__iram_func__
static bool _iqk_nbrxk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 gp = 0x0;
u32 a_idxrxgain[4] = {0x190, 0x198, 0x350, 0x352};
u32 a_idxattc2[4] = {0x0f, 0x0f, 0x3f, 0x7f};
u32 a_idxattc1[4] = {0x3, 0x1, 0x0, 0x0};
u32 g_idxrxgain[4] = {0x212, 0x21c, 0x350, 0x360};
u32 g_idxattc2[4] = {0x00, 0x00, 0x28, 0x5f};
u32 g_idxattc1[4] = {0x3, 0x3, 0x2, 0x1};
bool fail = false;
bool kfail = false;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
gp =0x3;
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x00, 0x03ff0, g_idxrxgain[gp]);
halrf_wrf(rf, path, 0x83, 0x1fc00, g_idxattc2[gp]);
halrf_wrf(rf, path, 0x83, 0x00300, g_idxattc1[gp]);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x00, 0x03ff0, a_idxrxgain[gp]);
halrf_wrf(rf, path, 0x8c, 0x0007f, a_idxattc2[gp]);
halrf_wrf(rf, path, 0x8c, 0x00180, a_idxattc1[gp]);
break;
default:
break;
}
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x0);
//halrf_wreg(rf, 0x8154 + (path << 8), 0x00000008, 0x0);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000007, gp);
halrf_wrf(rf, path, 0x1e, MASKRF, 0x80013);
halrf_delay_us(rf, 1);
fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_NBRXK);
halrf_wreg(rf, 0x9fe0, BIT(16 + gp + path * 4), fail);
kfail = kfail | fail;
halrf_wrf(rf, path, 0x20, 0x00080, 0x0);
if (!kfail) {
iqk_info->nb_rxcfir[path] = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD) | 0x2;
} else {
iqk_info->nb_rxcfir[path] = 0x40000002;
}
//RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, result = %x, 0x8%x3c = 0x%x\n", path, fail, 1 << path, halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD));
return kfail;
}
__iram_func__
static void _iqk_rxclk_setting_8852b(struct rf_info *rf, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
if (iqk_info->iqk_bw[path] == CHANNEL_WIDTH_80) { //BW80
//07_CLK_Setting_RxIQK_BW80M_Non_DBCC_PHY0_path01
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x0f);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x03);
halrf_wreg(rf, 0x032c, 0xffff0000, 0xa001);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x032c, 0xffff0000, 0xa041);
halrf_wreg(rf, 0x12a0, 0x00070000, 0x2);
halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00070000, 0x2);
halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
halrf_wreg(rf, 0x0700, 0x06000000, 0x1);
} else {
//07_CLK_Setting_RxIQK_BW40M_Non_DBCC_PHY0_path01
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x0f);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x03);
halrf_wreg(rf, 0x032c, 0xffff0000, 0xa001);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x032c, 0xffff0000, 0xa041);
halrf_wreg(rf, 0x12a0, 0x00070000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00070000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
halrf_wreg(rf, 0x0700, 0x06000000, 0x0);
}
return;
}
__iram_func__
static bool _txk_group_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool fail = false;
bool kfail = false;
u8 gp = 0x0;
u32 a_power_range[4] = {0x0, 0x0, 0x0, 0x0};
u32 a_track_range[4] = {0x3, 0x3, 0x6, 0x6};
u32 a_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e};
u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b};
u32 g_power_range[4] = {0x0, 0x0, 0x0, 0x0};
u32 g_track_range[4] = {0x4, 0x4, 0x6, 0x6};
u32 g_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e};
u32 g_itqt[4] = { 0x09, 0x12, 0x1b, 0x24};
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
for (gp = 0x0; gp < 0x4; gp++) {
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x11, 0x00003, g_power_range[gp]);
halrf_wrf(rf, path, 0x11, 0x00070, g_track_range[gp]);
halrf_wrf(rf, path, 0x11, 0x1f000, g_gain_bb[gp]);
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, g_itqt[gp]);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x11, 0x00003, a_power_range[gp]);
halrf_wrf(rf, path, 0x11, 0x00070, a_track_range[gp]);
halrf_wrf(rf, path, 0x11, 0x1f000, a_gain_bb[gp]);
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, a_itqt[gp]);
break;
default:
break;
}
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1); //man_sel_cfir_lut
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x1); //TX=0x1 or RX=0x0
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x0); //force to zero
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000003, gp);//remapping as {idx_rfgain, idx_txbb}
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_TXK);
halrf_wreg(rf, 0x9fe0, BIT(8 + gp + path * 4), fail);
kfail = kfail | fail;
}
if (kfail) {
iqk_info->nb_txcfir[path] = 0x40000002;
halrf_wreg(rf, 0x8124 + (path << 8), 0x00000f00, 0x0);
iqk_info->is_wb_txiqk[path] = false;
} else {
iqk_info->nb_txcfir[path] = 0x40000000;
halrf_wreg(rf, 0x8124 + (path << 8), 0x00000f00, 0x5);
iqk_info->is_wb_txiqk[path] = true;
}
/*
tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x38 = 0x%x\n", path, 1 << path, tmp);
*/
return kfail;
}
__iram_func__
static bool _iqk_nbtxk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool fail = false;
bool kfail = false;
u8 gp = 0x0;
u32 a_power_range[4] = {0x0, 0x0, 0x0, 0x0};
u32 a_track_range[4] = {0x3, 0x3, 0x6, 0x6};
u32 a_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e};
u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b};
u32 g_power_range[4] = {0x0, 0x0, 0x0, 0x0};
u32 g_track_range[4] = {0x4, 0x4, 0x6, 0x6};
u32 g_gain_bb[4] = {0x08, 0x0e, 0x06, 0x0e};
u32 g_itqt[4] = { 0x09, 0x12, 0x1b, 0x24};
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
gp = 0x3;
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x11, 0x00003, g_power_range[gp]);
halrf_wrf(rf, path, 0x11, 0x00070, g_track_range[gp]);
halrf_wrf(rf, path, 0x11, 0x1f000, g_gain_bb[gp]);
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, g_itqt[gp]);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x11, 0x00003, a_power_range[gp]);
halrf_wrf(rf, path, 0x11, 0x00070, a_track_range[gp]);
halrf_wrf(rf, path, 0x11, 0x1f000, a_gain_bb[gp]);
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, a_itqt[gp]);
break;
default:
break;
}
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000100, 0x1); //man_sel_cfir_lut
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000010, 0x1); //TX=0x1 or RX=0x0
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x0); //force to zero
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000003, gp);//remapping as {idx_rfgain, idx_txbb}
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
fail = _iqk_one_shot_8852b(rf, phy_idx, path, ID_NBTXK);
kfail = kfail | fail;
if (!kfail) {
iqk_info->nb_txcfir[path] = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD) | 0x2;
} else {
iqk_info->nb_txcfir[path] = 0x40000002;
}
/*
tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x8%x38 = 0x%x\n", path, 1 << path,
tmp);
*/
return kfail;
}
__iram_func__
static void _lok_res_table_8852b(struct rf_info *rf, u8 path, u8 ibias)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, ibias = %x\n", path, ibias);
halrf_wrf(rf, path, 0xef, MASKRF, 0x2);
if (iqk_info->iqk_band[path] == BAND_ON_24G)
halrf_wrf(rf, path, 0x33, MASKRF, 0x0);
else
halrf_wrf(rf, path, 0x33, MASKRF, 0x1);
halrf_wrf(rf, path, 0x3f, MASKRF, ibias);
halrf_wrf(rf, path, 0xef, MASKRF, 0x0);
halrf_wrf(rf, path, 0x7c, BIT(5), 0x1);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x7c = %x\n", path, halrf_rrf(rf, path, 0x7c,MASKRF));
return;
}
__iram_func__
static bool _lok_finetune_check_8852b(struct rf_info *rf, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool is_fail = false, is_fail1 = false, is_fail2 = false;
u32 temp = 0x0;
u32 core_i = 0x0;
u32 core_q = 0x0;
u32 fine_i = 0x0;
u32 fine_q = 0x0;
u8 ch = 0x0;
u32 vbuff_i = 0x0;
u32 vbuff_q = 0x0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
temp = halrf_rrf(rf, path, 0x58, MASKRF);
core_i = (temp & 0xf8000) >> 15;
core_q = (temp & 0x07c00) >> 10;
fine_i = (temp & 0x003c0) >> 6;
fine_q = (temp & 0x0003c) >> 2;
ch = ((iqk_info->iqk_times /2) % 2) & 0x1;
if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) {
is_fail1 = true;
} else {
is_fail1 = false;
}
iqk_info->lok_idac[ch][path] = temp;
temp = halrf_rrf(rf, path, 0x0a, MASKRF);
vbuff_i = (temp & 0xfc000) >> 14;
vbuff_q = (temp & 0x003f0) >> 4;
if (vbuff_i < 0x2 || vbuff_i > 0x3d || vbuff_q < 0x2 || vbuff_q > 0x3d) {
is_fail2 = true;
} else {
is_fail2 = false;
}
iqk_info->lok_vbuf[ch][path] = temp;
is_fail = is_fail1 | is_fail2;
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path, iqk_info->lok_idac[ch][path]);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path, iqk_info->lok_vbuf[ch][path]);
return is_fail;
}
__iram_func__
static bool _iqk_lok_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool fail = false;
bool tmp = false;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
//Init RF gain & tone idx= 8.25Mhz
halrf_wreg(rf, 0x802c, 0x00000fff, 0x021);
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
halrf_wrf(rf, path, 0x11, 0x00070, 0x6);
//halrf_wrf(rf, path, 0x11, 0x1f000, 0x0);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
halrf_wrf(rf, path, 0x11, 0x00070, 0x4);
//halrf_wrf(rf, path, 0x11, 0x1f000, 0x0);
break;
default:
break;
}
//Step 1 small mod gain
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x6);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x0);
break;
case BAND_ON_5G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x4);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x0);
break;
default:
break;
}
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x9);
tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLoK_coarse);
iqk_info->lok_cor_fail[0][path] = tmp;
//Step 2 large mod gain
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x6);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x12);
break;
case BAND_ON_5G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x4);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x12);
break;
default:
break;
}
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x24);
tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLOK_vbuffer);
//Step 3 small rf gain
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x6);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x0);
break;
case BAND_ON_5G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x4);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x0);
break;
default:
break;
}
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x9);
halrf_wreg(rf, 0x802c, 0x00000fff, 0x021);
tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLoK_fine);
iqk_info->lok_fin_fail[0][path] = tmp;
//Step 4 large rf gain
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x5);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x12);
break;
case BAND_ON_5G:
//halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
//halrf_wrf(rf, path, 0x11, 0x00070, 0x4);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x12);
break;
default:
break;
}
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x24);
tmp = _iqk_one_shot_8852b(rf, phy_idx, path, ID_FLOK_vbuffer);
fail = _lok_finetune_check_8852b(rf, path);
return fail;
}
__iram_func__
static void _iqk_txk_setting_8852b(struct rf_info *rf, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
//u32 tmp = 0x0;
//TX init gain setting
/*0/1:G/A*/
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
//05a_G_S0_TxLOK_52B_reg
halrf_wrf(rf, path, 0x90, 0x00300, 0x00);
halrf_wrf(rf, path, 0x51, 0x80000, 0x0);
halrf_wrf(rf, path, 0x51, 0x00800, 0x0);
halrf_wrf(rf, path, 0x52, 0x00800, 0x1);
halrf_wrf(rf, path, 0x55, 0x0001f, 0x0);
halrf_wrf(rf, path, 0xef, 0x00004, 0x1);
halrf_wrf(rf, path, 0x33, 0x000ff, 0x00);
halrf_wrf(rf, path, 0x0, 0xffff0, 0x403e);
halrf_delay_us(rf, 1);
break;
case BAND_ON_5G:
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
//05a_A_S0_TxLOK_52B__reg
halrf_wrf(rf, path, 0x85, 0x00003, 0x00);
halrf_wrf(rf, path, 0x60, 0x00007, 0x1);
halrf_wrf(rf, path, 0x55, 0x0001f, 0x0);
halrf_wrf(rf, path, 0xef, 0x00004, 0x1);
halrf_wrf(rf, path, 0x33, 0x000ff, 0x80);
halrf_wrf(rf, path, 0x0, 0xffff0, 0x403e);
halrf_delay_us(rf, 1);
break;
default:
break;
}
/*
tmp = halrf_rrf(rf, path, 0x00, MASKRF);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, rf%x = 0x%x\n", path, path, tmp);
*/
return;
}
__iram_func__
static void _iqk_txclk_setting_8852b(struct rf_info *rf, u8 path)
{
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
//04_CLK_Setting_TxIQK_DAC960MHz_nonDBCC_PHY0_path01_reg
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x1f);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0001);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
return;
}
__iram_func__
static void _iqk_info_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 tmp = 0x0;
bool flag = 0x0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
iqk_info->thermal[path] = halrf_get_thermal_8852b(rf, path);
iqk_info->thermal_rek_en = false;
/*
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_thermal = %d\n", path,
iqk_info->thermal[path] );
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
iqk_info->lok_cor_fail[0][path]);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
iqk_info->lok_fin_fail[0][path]);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_TXIQK_fail = %d\n", path,
iqk_info->iqk_tx_fail[0][path]);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d_RXIQK_fail= %d,\n", path,
iqk_info->iqk_rx_fail[0][path]);
*/
flag = iqk_info->lok_cor_fail[0][path];
halrf_wreg(rf, 0x9fe0, BIT(0) << (path * 4), flag);
flag = iqk_info->lok_fin_fail[0][path];
halrf_wreg(rf, 0x9fe0, BIT(1) << (path * 4), flag);
flag = iqk_info->iqk_tx_fail[0][path];
halrf_wreg(rf, 0x9fe0, BIT(2) << (path * 4), flag);
flag = iqk_info->iqk_rx_fail[0][path];
halrf_wreg(rf, 0x9fe0, BIT(3) << (path * 4), flag);
tmp = halrf_rreg(rf, 0x8124 + (path << 8), MASKDWORD);
iqk_info->bp_iqkenable[path] = tmp;
tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD);
iqk_info->bp_txkresult[path] = tmp;
tmp = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD);
iqk_info->bp_rxkresult[path] = tmp;
halrf_wreg(rf, 0x9fe8, 0x0000ff00, (u8)iqk_info->iqk_times);
tmp = halrf_rreg(rf, 0x9fe0, 0x0000000f << (path * 4));
if (tmp != 0x0)
iqk_info->iqk_fail_cnt++;
halrf_wreg(rf, 0x9fe8, 0x00ff0000 << (path * 4), iqk_info->iqk_fail_cnt);
return;
}
__iram_func__
void iqk_set_info_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 tmp = 0x0;
bool flag = 0x0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
iqk_info->thermal[path] = halrf_get_thermal_8852b(rf, path);
iqk_info->thermal_rek_en = false;
flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(0) << (path * 4));
iqk_info->lok_cor_fail[0][path] = flag;
flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(1) << (path * 4));
iqk_info->lok_fin_fail[0][path] = flag;
flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(2) << (path * 4));
iqk_info->iqk_tx_fail[0][path] = flag;
flag = (bool) halrf_rreg(rf, 0x9fe0, BIT(3) << (path * 4));
iqk_info->iqk_rx_fail[0][path] = flag;
tmp = halrf_rreg(rf, 0x8124 + (path << 8), MASKDWORD);
iqk_info->bp_iqkenable[path] = tmp;
tmp = halrf_rreg(rf, 0x8138 + (path << 8), MASKDWORD);
iqk_info->bp_txkresult[path] = tmp;
tmp = halrf_rreg(rf, 0x813c + (path << 8), MASKDWORD);
iqk_info->bp_rxkresult[path] = tmp;
iqk_info->iqk_times = (u8) halrf_rreg(rf, 0x9fe8, 0x0000ff00);
iqk_info->iqk_fail_cnt = halrf_rreg(rf, 0x9fe8, 0x00ff0000 << (path * 4));
return;
}
__iram_func__
static void _iqk_by_path_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool lok_is_fail = false;
u8 ibias = 0x1;
u8 i = 0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
_iqk_txclk_setting_8852b(rf, path);
//LOK
for (i = 0; i < 3; i++) {
_lok_res_table_8852b(rf, path, ibias++);
_iqk_txk_setting_8852b(rf, path);
lok_is_fail = _iqk_lok_8852b(rf, phy_idx, path);
if (!lok_is_fail)
break;
}
//TXK
if (iqk_info->is_nbiqk) {
iqk_info->iqk_tx_fail[0][path] =
_iqk_nbtxk_8852b(rf, phy_idx, path);
} else {
iqk_info->iqk_tx_fail[0][path] =
_txk_group_sel_8852b(rf, phy_idx, path);
}
//RX
_iqk_rxclk_setting_8852b(rf, path);
_iqk_rxk_setting_8852b(rf, path);
if (iqk_info->is_nbiqk) {
iqk_info->iqk_rx_fail[0][path] =
_iqk_nbrxk_8852b(rf, phy_idx, path);
} else {
iqk_info->iqk_rx_fail[0][path] =
_rxk_group_sel_8852b(rf, phy_idx, path);
}
_iqk_info_iqk_8852b(rf, phy_idx, path);
return;
}
__iram_func__
bool iqk_mcc_page_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path)
{
#if 0
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool flag = false;
if (rf->hal_com->band[phy].cur_chandef.center_ch == iqk_info->iqk_mcc_ch[0][path]) {
halrf_wreg(rf, 0x8104 + (path << 8), 0x00000001, 0x0);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x0);
_iqk_mcc_load_lok_8852b(rf, phy, path, iqk_info->lok_idac[0][path]);
flag = true;
} else if (rf->hal_com->band[phy].cur_chandef.center_ch == iqk_info->iqk_mcc_ch[1][path]) {
halrf_wreg(rf, 0x8104 + (path << 8), 0x00000001, 0x1);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000004, 0x1);
_iqk_mcc_load_lok_8852b(rf, phy, path, iqk_info->lok_idac[1][path]);
flag = true;
} else
flag = false;
#endif
return false;
}
__iram_func__
void iqk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 reg_rf18 = 0x0;
u32 reg_35c = 0x0;
u8 ver;
u8 idx = 0;
u8 get_empty_table = false;
for (idx = 0; idx < 2; idx++) {
if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
get_empty_table = true;
break;
}
}
RF_DBG(rf, DBG_RF_IQK, "[IQK] (1) idx = %x\n", idx);
if (false == get_empty_table) {
idx = iqk_info->iqk_table_idx[path] + 1;
if (idx > 1) {
idx = 0;
}
//RF_DBG(rf, DBG_RF_IQK, "[IQK]we will replace iqk table index(%d), !!!!! \n", idx);
}
RF_DBG(rf, DBG_RF_IQK, "[IQK] (2) idx = %x\n", idx);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
reg_rf18 = halrf_rrf(rf, path, 0x18, MASKRF);
reg_35c = halrf_rreg(rf, 0x35c, 0x00000c00);
#if 1
iqk_info->iqk_band[path] = rf->hal_com->band[phy].cur_chandef.band;
iqk_info->iqk_bw[path] = rf->hal_com->band[phy].cur_chandef.bw;
iqk_info->iqk_ch[path] = rf->hal_com->band[phy].cur_chandef.center_ch;
iqk_info->iqk_mcc_ch[idx][path] = rf->hal_com->band[phy].cur_chandef.center_ch;
iqk_info->iqk_table_idx[path] = idx;
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n", path, reg_rf18, idx);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, iqk_info->iqk_band[path]);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n", path, iqk_info->iqk_bw[path]);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n", path, iqk_info->iqk_ch[path]);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]iqk_info->iqk_mcc_ch[%x][%x]= 0x%x\n", ch, path, iqk_info->iqk_mcc_ch[ch][path]);
#else
/*0/1:G/A*/
if (((reg_rf18 & BIT(16)) >> 16)== 0x0)
iqk_info->iqk_band[path] = BAND_ON_24G;
else
iqk_info->iqk_band[path] = BAND_ON_5G;
iqk_info->iqk_mcc_ch[ch][path] = (u8)reg_rf18 & 0xff;
iqk_info->iqk_ch[path] = (u8)reg_rf18 & 0xff;
/*3/2/1:20/40/80*/
if (((reg_rf18 & 0xc00) >> 10)== 0x3)
iqk_info->iqk_bw[path] = CHANNEL_WIDTH_20; //Bw20
else if (((reg_rf18 & 0xc00) >> 10)== 0x2)
iqk_info->iqk_bw[path] = CHANNEL_WIDTH_40; //Bw40
else
iqk_info->iqk_bw[path] = CHANNEL_WIDTH_80; //Bw80
#endif
#if 1
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, 0x18= 0x%x\n", path, reg_rf18);
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n",
path, phy, rf->hal_com->dbcc_en ? "on" : "off",
iqk_info->iqk_band[path] == 0 ? "2G" : (iqk_info->iqk_band[path] == 1 ? "5G" : "6G"),
iqk_info->iqk_ch[path] ,
iqk_info->iqk_bw[path] == 0 ? "20M" : (iqk_info->iqk_bw[path] == 1 ? "40M" : "80M"));
RF_DBG(rf, DBG_RF_IQK, "[IQK] times = 0x%x, ch =%x\n", iqk_info->iqk_times , idx);
RF_DBG(rf, DBG_RF_IQK, "[IQK] iqk_mcc_ch[%x][%x] = 0x%x\n", (u8)idx, (u8)path, iqk_info->iqk_mcc_ch[idx][path]);
#endif
#if 1
if (reg_35c == 0x01)
iqk_info->syn1to2 = 0x1;
else
iqk_info->syn1to2 = 0x0;
#else
iqk_info->syn1to2 = 0x1;
#endif
RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path, iqk_info->syn1to2);
halrf_wreg(rf, 0x9fe0, 0xff000000, iqk_version_8852b);
//2G5G6G = 0/1/2
halrf_wreg(rf, 0x9fe4, 0x000f << (path * 16), (u8)iqk_info->iqk_band[path]);
//20/40/80 = 0/1/2
halrf_wreg(rf, 0x9fe4, 0x00f0 << (path * 16), (u8)iqk_info->iqk_bw[path]);
halrf_wreg(rf, 0x9fe4, 0xff00 << (path * 16), (u8)iqk_info->iqk_ch[path]);
ver = (u8) halrf_get_8852b_nctl_reg_ver();
halrf_wreg(rf, 0x9fe8, 0x000000ff, ver);
#if 0
if (iqk_info->iqk_band[path] == BAND_ON_5G)
RF_DBG(rf, DBG_RF_IQK, "[IQK]band = BAND_ON_5G\n");
else
RF_DBG(rf, DBG_RF_IQK, "[IQK]band = BAND_ON_24G\n");
if (iqk_info->iqk_bw[path] == CHANNEL_WIDTH_20)
RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 20MHz\n");
else if(iqk_info->iqk_bw[path] == CHANNEL_WIDTH_40)
RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 40MHz\n");
else if(iqk_info->iqk_bw[path] == CHANNEL_WIDTH_80)
RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 80MHz\n");
else if(iqk_info->iqk_bw[path] == CHANNEL_WIDTH_160)
RF_DBG(rf, DBG_RF_IQK, "[IQK]band_width = 160MHz\n");
else
RF_DBG(rf, DBG_RF_IQK, "[IQK]!!!! Channle is not support !!!!\n");
#endif
return;
}
__iram_func__
void halrf_iqk_reload_8852b(struct rf_info *rf, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 tmp;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
iqk_info->reload_cnt++;
tmp = iqk_info->bp_iqkenable[path];
halrf_wreg(rf, 0x8124 + (path << 8), MASKDWORD, tmp);
tmp = iqk_info->bp_txkresult[path];
halrf_wreg(rf, 0x8138 + (path << 8), MASKDWORD, tmp);
tmp = iqk_info->bp_rxkresult[path];
halrf_wreg(rf, 0x813c + (path << 8), MASKDWORD, tmp);
return;
}
__iram_func__
void iqk_start_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
_iqk_by_path_8852b(rf, phy_idx, path);
return;
}
__iram_func__
void iqk_restore_8852b(struct rf_info *rf, u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool fail;
halrf_wreg(rf, 0x8138 + (path << 8), MASKDWORD, iqk_info->nb_txcfir[path]);
halrf_wreg(rf, 0x813c + (path << 8), MASKDWORD, iqk_info->nb_rxcfir[path]);
halrf_wreg(rf, 0x8000, MASKDWORD, 0x00000e19 + (path << 4));
halrf_delay_us(rf, 10);
fail = _iqk_check_cal_8852b(rf, path, 0x0);
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x8088, MASKDWORD, 0x80000000);
halrf_wreg(rf, 0x8120, 0x10000000, 0x0);
halrf_wreg(rf, 0x8220, 0x10000000, 0x0);
halrf_wreg(rf, 0x8220, 0x00010000, 0x0);
halrf_wrf(rf, path, 0xef, 0x00004, 0x0);
halrf_wrf(rf, path, 0xef, 0x00004, 0x0);
halrf_wrf(rf, path, 0x0, 0xf0000, 0x3);
halrf_wrf(rf, path, 0x5, 0x00001, 0x1);
halrf_wrf(rf, path, 0x10005, 0x00001, 0x1);
return;
}
__iram_func__
void iqk_afebb_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
u32 i = 0;
u32 array_len = 0x0;
u32 *array = NULL;
u32 addr = 0, mask = 0, val = 0;
RF_DBG(rf, DBG_RF_IQK, "===> %s\n", __func__);
switch(halrf_kpath_8852b(rf, phy_idx)) {
case RF_A:
break;
case RF_B:
break;
default:
array_len = sizeof(array_restore_nondbcc_path01_8852b) / sizeof(u32);
array = (u32 *) &array_restore_nondbcc_path01_8852b;
break;
}
while ((i + 1) < array_len) {
addr = array[i];
mask = array[i + 1];
val = array[i + 2];
halrf_wreg(rf, addr, mask, val);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, val);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, halrf_rreg(rf, addr, mask));
i += 3;
}
return;
}
__iram_func__
void iqk_preset_8852b(struct rf_info *rf, u8 path)
{
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
//03_IQK_Preset_Non_DBCC_PHY0_path01
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 idx = 0;
//ch = ((iqk_info->iqk_times /2) % 2) & 0x1;
idx = iqk_info->iqk_table_idx[path];
RF_DBG(rf, DBG_RF_IQK, "[IQK] (3) idx = %x\n", idx);
halrf_wreg(rf, 0x8104 + (path << 8), 0x00000001, idx);
halrf_wreg(rf, 0x8154 + (path << 8), 0x00000008, idx);
halrf_wrf(rf, path, 0x5, 0x00001, 0x0);
halrf_wrf(rf, path, 0x10005, 0x00001, 0x0);
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080);
halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff010a);
RF_DBG(rf, DBG_RF_IQK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path, halrf_rreg(rf, 0x8154 + (path << 8), MASKDWORD));
RF_DBG(rf, DBG_RF_IQK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path, halrf_rreg(rf, 0x8104 + (path << 8), MASKDWORD));
return;
}
__iram_func__
void iqk_macbb_setting_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
u32 i = 0;
u32 array_len = 0x0;
u32 *array = NULL;
u32 addr = 0, mask = 0, val = 0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===> %s\n", __func__);
switch(halrf_kpath_8852b(rf, phy_idx)) {
case RF_A:
break;
case RF_B:
break;
default:
array_len = sizeof(array_set_nondbcc_path01_8852b) / sizeof(u32);
array = (u32 *) &array_set_nondbcc_path01_8852b;
break;
}
while ((i + 1) < array_len) {
addr = array[i];
mask = array[i + 1];
val = array[i + 2];
halrf_wreg(rf, addr, mask, val);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, val);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]0x%x[%x] = 0x%x\n", addr, mask, halrf_rreg(rf, addr, mask));
i += 3;
}
return;
}
__iram_func__
void halrf_iqk_toneleakage_8852b(struct rf_info *rf, u8 path)
{
iqk_macbb_setting_8852b(rf, HW_PHY_0, path);
iqk_preset_8852b(rf, path);
_iqk_txclk_setting_8852b(rf, path);
// main iqk single tone process
halrf_wrf(rf, path, 0x0, 0xf0000, 0x2);
#if 0
switch (iqk_info->iqk_band[path]) {
case BAND_ON_24G:
halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
halrf_wrf(rf, path, 0x11, 0x00070, 0x6);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x0e);
break;
case BAND_ON_5G:
halrf_wrf(rf, path, 0x11, 0x00003, 0x0);
halrf_wrf(rf, path, 0x11, 0x00070, 0x6);
halrf_wrf(rf, path, 0x11, 0x1f000, 0x0e);
break;
default:
break;
}
#endif
halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff010a);
halrf_wreg(rf, 0x80d0, MASKDWORD, 0x00300000);
halrf_wreg(rf, 0x8120 + (path << 8), MASKDWORD, 0xce000a08);
halrf_wreg(rf, 0x8000, 0x00000006, path);
halrf_wrf(rf, path, 0x10001, 0x0003f, 0x3c);
halrf_wreg(rf, 0x8034, 0x00000030, 0x2);
halrf_wreg(rf, 0x8038, 0x00000100, 0x1);
halrf_wreg(rf, 0x8034, 0xff000000, 0x11);
halrf_wreg(rf, 0x5864, 0x20000000, 0x1);
halrf_wreg(rf, 0x8014, 0x10000000, 0x1);
halrf_wreg(rf, 0x8014, 0x10000000, 0x0);
halrf_delay_us(rf, 100);
halrf_wreg(rf, 0x5864, 0x20000000, 0x0);
halrf_wreg(rf, 0x8018, 0x70000000, 0x2);
halrf_wreg(rf, 0x81cc + (path << 8), MASKDWORD, 0x12);
halrf_wreg(rf, 0x802c, 0x00000fff, 0x009);
halrf_wreg(rf, 0x8034, 0x00000001, 0x1);
halrf_wreg(rf, 0x8034, 0x00000001, 0x0);
halrf_delay_us(rf, 1);
//halrf_wreg(rf, 0x8034, 0x00000030, 0x3);
//halrf_wreg(rf, 0x8038, 0x00000100, 0x0);
return;
}
__iram_func__
void halrf_iqk_dbcc_8852b(struct rf_info *rf, u8 path)
{
#if 0
bool bkdbcc = false;
u8 phy_idx = 0x0;
bkdbcc = rf->hal_com->dbcc_en;
rf->hal_com->dbcc_en = true;
if (path == 0x0)
phy_idx = HW_PHY_0;
else
phy_idx = HW_PHY_1;
//iqk_mcc_page_sel_8852b(rf,phy_idx, path);
iqk_get_ch_info_8852b(rf,phy_idx, path);
iqk_macbb_setting_8852b(rf, phy_idx, path);
iqk_preset_8852b(rf, path);
iqk_start_iqk_8852b(rf, phy_idx, path);
iqk_restore_8852b(rf, path);
iqk_afebb_restore_8852b(rf, phy_idx, path);
rf->hal_com->dbcc_en = bkdbcc;
#endif
return;
}
__iram_func__
void halrf_iqk_onoff_8852b(struct rf_info *rf, bool is_enable)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (is_enable) {
halrf_wreg(rf, 0x8124, MASKDWORD, 0x00000505); /*ch0*/
halrf_wreg(rf, 0x8224, MASKDWORD, 0x00000505); /*ch1*/
iqk_info->is_iqk_enable = true;
} else {
halrf_wreg(rf, 0x8124, MASKDWORD, 0x00000000); /*ch0*/
halrf_wreg(rf, 0x8224, MASKDWORD, 0x00000000); /*ch1*/
iqk_info->is_iqk_enable = false;
}
RF_DBG(rf, DBG_RF_IQK, "[IQK] IQK enable : %s !!!\n",
iqk_info->is_iqk_enable ? "enable" : "disable");
return;
}
__iram_func__
void halrf_iqk_tx_bypass_8852b(struct rf_info *rf, u8 path)
{
if (path == RF_PATH_A) { //path A
/*ch0*/
halrf_wreg(rf, 0x8124, 0x00000f00, 0x0);
halrf_wreg(rf, 0x8138, MASKDWORD, 0x40000002);
} else {
/*ch1*/
halrf_wreg(rf, 0x8224, 0x00000f00, 0x0);
halrf_wreg(rf, 0x8238, MASKDWORD, 0x40000002);
}
return;
}
__iram_func__
void halrf_iqk_rx_bypass_8852b(struct rf_info *rf, u8 path)
{
if (path == RF_PATH_A) { //path A
/*ch0*/
halrf_wreg(rf, 0x8124, 0x0000000f, 0x0);
halrf_wreg(rf, 0x813c, MASKDWORD, 0x40000002);
} else {
/*ch1*/
halrf_wreg(rf, 0x8224, 0x0000000f, 0x0);
halrf_wreg(rf, 0x823c, MASKDWORD, 0x40000002);
}
return;
}
__iram_func__
void halrf_iqk_lok_bypass_8852b(struct rf_info *rf, u8 path)
{
halrf_wrf(rf, path, 0xdf, 0x00004, 0x1);
halrf_wrf(rf, path, 0x58, MASKRF, 0x84220);
return;
}
__iram_func__
void halrf_nbiqk_enable_8852b(struct rf_info *rf, bool nbiqk_en)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (nbiqk_en) {
iqk_info->is_nbiqk = true;
} else {
iqk_info->is_nbiqk = false;
}
return;
}
__iram_func__
void halrf_iqk_xym_enable_8852b(struct rf_info *rf, bool iqk_xym_en)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (iqk_xym_en) {
iqk_info->iqk_xym_en = true;
} else {
iqk_info->iqk_xym_en = false;
}
return;
}
__iram_func__
void halrf_iqk_fft_enable_8852b(struct rf_info *rf, bool iqk_fft_en)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (iqk_fft_en) {
iqk_info->iqk_fft_en = true;
} else {
iqk_info->iqk_fft_en = false;
}
return;
}
__iram_func__
void halrf_iqk_sram_enable_8852b(struct rf_info *rf, bool iqk_sram_en)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (iqk_sram_en) {
iqk_info->iqk_sram_en = true;
} else {
iqk_info->iqk_sram_en = false;
}
return;
}
__iram_func__
void halrf_iqk_cfir_enable_8852b(struct rf_info *rf, bool iqk_cfir_en)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (iqk_cfir_en) {
iqk_info->iqk_cfir_en = true;
} else {
iqk_info->iqk_cfir_en = false;
}
return;
}
__iram_func__
void halrf_iqk_track_8852b(
struct rf_info *rf)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 path =0x0, i = 0x0;
u8 cur_ther = 0x0, ther_avg_cnt = 0;
u32 ther_avg[2] = {0};
/*only check path 0 */
for (path = 0; path < 1; path++) {
cur_ther = halrf_get_thermal_8852b(rf, path);
iqk_info->ther_avg[path][iqk_info->ther_avg_idx] = cur_ther;
/*Average times */
ther_avg_cnt = 0;
for (i = 0; i < 0x4; i++) {
if (iqk_info->ther_avg[path][i]) {
ther_avg[path] += iqk_info->ther_avg[path][i];
ther_avg_cnt++;
#if 0
RF_DBG(rf, DBG_RF_IQK,
"[IQK] thermal avg[%d] = %d\n", i,
iqk_info->ther_avg[path][i]);
#endif
}
}
/*Calculate Average ThermalValue after average enough times*/
if (ther_avg_cnt) {
cur_ther = (u8)(ther_avg[path] / ther_avg_cnt);
}
if (HALRF_ABS(cur_ther, iqk_info->thermal[path] ) > IQK_THR_ReK) {
iqk_info->thermal_rek_en = true;
}
else {
iqk_info->thermal_rek_en = false;
}
//RF_DBG(rf, DBG_RF_IQK, "[IQK]S%x, iqk_ther =%d, ther_now = %d\n", path, iqk->thermal[path], cur_ther);
}
iqk_info->ther_avg_idx++;
if (iqk_info->ther_avg_idx == 0x4)
iqk_info->ther_avg_idx = 0;
return;
}
__iram_func__
bool halrf_iqk_get_ther_rek_8852b(struct rf_info *rf ) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
return iqk_info->thermal_rek_en;
}
__iram_func__
u8 halrf_iqk_get_mcc_ch0_8852b(struct rf_info *rf ) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
return iqk_info->iqk_mcc_ch[0][0];
}
__iram_func__
u8 halrf_iqk_get_mcc_ch1_8852b(struct rf_info *rf ) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
return iqk_info->iqk_mcc_ch[1][0];
}
__iram_func__
bool halrf_check_fwiqk_done_8852b(struct rf_info *rf)
{
u32 counter = 0x0;
bool flag = false;
bool isfail = false;
#if 1
while (1) {
if (halrf_rreg(rf, 0xbff8, MASKBYTE0) == 0xaa || counter > 3000) {
if(halrf_rreg(rf, 0x8010, MASKBYTE0) == 0xaa) {
flag = true;
break;
}
}
counter++;
halrf_delay_us(rf, 10);
};
#else
for(counter = 0; counter < 6000; counter++)
halrf_delay_us(rf, 10);
#endif
if (counter < 10)
isfail = true;
else
isfail = false;
if(flag) {
RF_DBG(rf, DBG_RF_IQK, "[IQK] Load FW Done, counter = %d!!\n", counter);
} else {
RF_DBG(rf, DBG_RF_IQK, "[IQK] Load FW Fail, counter = %d!!\n", counter);
halrf_iqk_tx_bypass_8852b(rf, RF_PATH_A);
halrf_iqk_tx_bypass_8852b(rf, RF_PATH_B);
halrf_iqk_rx_bypass_8852b(rf, RF_PATH_A);
halrf_iqk_rx_bypass_8852b(rf, RF_PATH_B);
halrf_iqk_lok_bypass_8852b(rf, RF_PATH_A);
halrf_iqk_lok_bypass_8852b(rf, RF_PATH_B);
}
halrf_wreg(rf, 0x8010, 0x000000ff,0x0);
return isfail;
}
__iram_func__
void halrf_enable_fw_iqk_8852b(struct rf_info *rf, bool is_fw_iqk)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
if (is_fw_iqk) {
iqk_info->is_fw_iqk = true;
} else {
iqk_info->is_fw_iqk = false;
}
return;
}
__iram_func__
u8 halrf_get_iqk_times_8852b(struct rf_info *rf) {
u8 times = 0x0;
times = (u8) halrf_rreg(rf, 0x9fe8, 0x0000ff00);
return times;
}
__iram_func__
u32 halrf_get_iqk_ver_8852b(void)
{
return iqk_version_8852b;
}
__iram_func__
void iqk_init_8852b(struct rf_info *rf)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 idx, path;
halrf_wreg(rf, 0x9fe0, MASKDWORD, 0x0);
if (!iqk_info->is_iqk_init) {
RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
iqk_info->is_iqk_init = true;
iqk_info->is_nbiqk = false;
iqk_info->iqk_fft_en = false;
iqk_info->iqk_sram_en = false;
iqk_info->iqk_cfir_en = false;
iqk_info->iqk_xym_en = false;
iqk_info->thermal_rek_en = false;
iqk_info->ther_avg_idx = 0x0;
iqk_info->iqk_times = 0x0;
/*channel/path/TRX(TX:0, RX:1) */
iqk_info->iqk_times = 0x0;
iqk_info->is_fw_iqk = false;
for (idx = 0; idx < 2; idx++) { //channel
iqk_info->iqk_channel[idx] = 0x0;
for (path = 0; path < ss_8852b; path++) {//path
iqk_info->lok_cor_fail[idx][path] = false;
iqk_info->lok_fin_fail[idx][path] = false;
iqk_info->iqk_tx_fail[idx][path] = false;
iqk_info->iqk_rx_fail[idx][path] = false;
iqk_info->iqk_mcc_ch[idx][path] = 0x0;
iqk_info->iqk_table_idx[path] = 0x0;
}
}
}
return;
}
u8 halrf_iqk_get_rxevm_8852b(struct rf_info *rf)
{
u8 rxevm =0x0;
#if 1
halrf_wreg(rf, 0x738, 0x00000010, 0x1);
halrf_wreg(rf, 0x738, 0x000000c0, 0x1);
halrf_wreg(rf, 0x738, 0x70000000, 0x2);
halrf_wreg(rf, 0x738, 0x00000020, 0x0);
halrf_delay_us(rf, 100);
halrf_wreg(rf, 0x20f4, 0x01000000, 0x0);
halrf_wreg(rf, 0x20f8, 0x80000000, 0x1);
halrf_wreg(rf, 0x20f0, 0x00ff0000, 0x1);
halrf_wreg(rf, 0x20f0, 0x00000f00, 0x7);
halrf_wreg(rf, 0x20f0, 0x000000ff, 0x0);
halrf_wreg(rf, 0x738, 0x00000020, 0x1);
halrf_wreg(rf, 0x738, 0x0000ff00, 0x5);
rxevm = (u8) (halrf_rreg(rf, 0x1af0, 0x00ff0000) /4) ;
#else
rxevm = rtw_hal_bb_get_rxevm_single_user(rf->hal_com, HW_PHY_0, 0, 1);
#endif
return rxevm;
}
u32 halrf_iqk_get_rximr_8852b(struct rf_info *rf, u8 path, u32 idx)
{
u32 rximr =0x0;
u32 tone_idx = 0x0;
u32 main_idx = 0x0;
u32 rf0 = 0x0;
u32 pwr_sig = 0x0, pwr_img = 0x0;
u32 reg_0x800c = 0x0, reg_0x8018 = 0x0, reg_0x801c = 0x0, reg_0x81cc = 0x0, reg_0x82cc = 0x0;
reg_0x800c = halrf_rreg(rf, 0x800c, MASKDWORD);
reg_0x8018 = halrf_rreg(rf, 0x8018, MASKDWORD);
reg_0x801c = halrf_rreg(rf, 0x801c, MASKDWORD);
reg_0x81cc = halrf_rreg(rf, 0x81cc, MASKDWORD);
reg_0x82cc = halrf_rreg(rf, 0x82cc, MASKDWORD);
//tone_idx = idx * 320MHz/80MHz
if (idx <100) {
tone_idx = idx * 4 * 2;
main_idx = tone_idx & 0xfff;
} else {
tone_idx = (idx -100) *4 * 2;
main_idx = (0x1000-tone_idx) & 0xfff;
}
RF_DBG(rf, DBG_RF_IQK, "[IQK][IMR]S%x, idx = 0x%x, tone_idx = 0x%x, main_idx = 0x%x\n", path, idx, tone_idx, main_idx);
iqk_macbb_setting_8852b(rf, HW_PHY_0, path);
iqk_preset_8852b(rf, path);
_iqk_rxclk_setting_8852b(rf, path);
halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff0109);
halrf_wreg(rf, 0x8000, 0x00000006, path);
halrf_wreg(rf, 0x800c, MASKDWORD, 0x00000c00);
halrf_wreg(rf, 0x8018, 0x70000000, 0x4);
halrf_wreg(rf, 0x801c, 0x000e0000, 0x0);
halrf_wreg(rf, 0x80d0, MASKDWORD, 0x00300000);
halrf_wreg(rf, 0x81cc + (path << 8), 0x0000003f, 0x3f);
halrf_wreg(rf, 0x8140 + (path << 8), 0x00000100, 0x1);
rf0 = halrf_rrf(rf, path, 0x00, 0x03800);
halrf_wreg(rf, 0x8144 + (path << 8), 0x00070000, rf0);
rf0 = halrf_rrf(rf, path, 0x00, 0x003e0);
halrf_wreg(rf, 0x8144 + (path << 8), 0x1f000000, rf0);
halrf_wreg(rf, 0x81dc + (path << 8), MASKDWORD, 0x00000001);
halrf_wreg(rf, 0x81dc + (path << 8), MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x802c, 0x0fff0000, main_idx);
halrf_wreg(rf, 0x8034, 0x00000001, 0x1);
halrf_wreg(rf, 0x8034, 0x00000001, 0x0);
halrf_delay_us(rf, 100);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002d0000);
pwr_sig = halrf_rreg(rf, 0x80fc, 0x007f0000);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002e0000);
pwr_sig = (pwr_sig << 25) + (halrf_rreg(rf, 0x80fc, MASKDWORD) >> 7);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002d0000);
pwr_img = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x002f0000);
pwr_img = (pwr_img << 25) + (halrf_rreg(rf, 0x80fc, MASKDWORD) >> 7);
rximr = (u32) (pwr_sig / pwr_img);
RF_DBG(rf, DBG_RF_IQK, "[IQK][IMR]S%x, %x, %d,%d, %d\n", path, halrf_rrf(rf, path, 0x0, MASKRF),pwr_sig, pwr_img, rximr);
halrf_wreg(rf, 0x800c, MASKDWORD, reg_0x800c);
halrf_wreg(rf, 0x8018, MASKDWORD, reg_0x8018);
halrf_wreg(rf, 0x801c, MASKDWORD, reg_0x801c);
halrf_wreg(rf, 0x81cc, MASKDWORD, reg_0x81cc);
halrf_wreg(rf, 0x82cc, MASKDWORD, reg_0x82cc);
return rximr;
}
#if 0
__iram_func__
void halrf_doiqk_8852b(struct rf_info *rf, bool force, enum phl_phy_idx phy_idx, u8 path)
{
u32 backup_mac[2] = {0x0};
u32 backup_bb[2] = {0x0};
u32 backup_rf0[6] = {0x0};
u32 backup_rf1[6] = {0x0};
u32 backup_mac_reg[1] = {0x0};
u32 backup_bb_reg[1] = {0x2344};
u32 backup_rf_reg0[6] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x5};
u32 backup_rf_reg1[6] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x5};
struct halrf_iqk_info *iqk_info = &rf->iqk;
//halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_START);
RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK strat!!!!!==========\n");
iqk_info->version = iqk_version_8852b;
iqk_info->iqk_step = 0;
iqk_info->rxiqk_step = 0;
iqk_info->reload_cnt = 0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]Test Ver 0x%x\n", iqk_version);
//RF_DBG(rf, DBG_RF_IQK, "[IQK]Test Ver 0x%x\n", 0x2);
//u32 addr = 0x0;
//for (addr = 0x8000; addr < 0x8300; addr += 0x4)
// RF_DBG(rf, DBG_RF_IQK, "[IQK] %8x, %8x \n", addr, halrf_rreg(rf, addr + 0x4, MASKDWORD));
if (iqk_mcc_page_sel_8852b(rf,phy_idx, path))
return;
iqk_get_ch_info_8852b(rf,phy_idx, path);
iqk_backup_mac_bb_8852b(rf, path, backup_mac, backup_bb, backup_mac_reg, backup_bb_reg);
iqk_backup_rf0_8852b(rf, path, backup_rf0, backup_rf_reg0);
iqk_backup_rf1_8852b(rf, path, backup_rf1, backup_rf_reg1);
iqk_macbb_setting_8852b(rf, phy_idx, path);
iqk_preset_8852b(rf, path);
iqk_start_iqk_8852b(rf, phy_idx, path);
iqk_restore_8852b(rf, path);
iqk_afebb_restore_8852b(rf, phy_idx, path);
iqk_restore_mac_bb_8852b(rf, path, backup_mac, backup_bb, backup_mac_reg, backup_bb_reg);
iqk_restore_rf0_8852b(rf, path, backup_rf0, backup_rf_reg0);
iqk_restore_rf1_8852b(rf, path, backup_rf1, backup_rf_reg1);
iqk_info->iqk_times++;
//halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_STOP);
RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK End!!!!!==========\n");
return;
}
__iram_func__
void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force)
{
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
iqk_init_8852b(rf);
switch(halrf_kpath_8852b(rf, phy_idx)) {
case RF_A:
halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_A);
break;
case RF_B:
halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_B);
break;
case RF_AB:
halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_A);
halrf_doiqk_8852b(rf, force, phy_idx, RF_PATH_B);
break;
default:
break;
}
return;
}
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.c
|
C
|
agpl-3.0
| 62,532
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_IQK_8852BH__
#define __HALRF_IQK_8852BH__
#ifdef RF_8852B_SUPPORT
#define iqk_version_8852b 0xc
#define ss_8852b 2
#define mac_reg_num_8852b 2
#define bb_reg_num_8852b 1
#define rf_reg_num_8852b 6
#define iqk_delay_8852b 1
#define iqk_step_8852b 2
#define rxk_step_8852b 4
#define path_baseaddr 0x8
#define txagck 0
#define lok 1
#define txk 2
#define rxk 3
#define IQK_THR_ReK 8
void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
//cv b
void iqk_init_8852b(struct rf_info *rf);
void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
void halrf_doiqk_8852b(struct rf_info *rf, bool force,
enum phl_phy_idx phy_idx, u8 path);
void iqk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
bool iqk_mcc_page_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
void iqk_macbb_setting_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
void iqk_preset_8852b(struct rf_info *rf, u8 path);
void iqk_start_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path);
void iqk_restore_8852b(struct rf_info *rf, u8 path);
void iqk_afebb_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
void halrf_iqk_reload_8852b(struct rf_info *rf, u8 path);
void halrf_nbiqk_enable_8852b(struct rf_info *rf, bool nbiqk_en);
void halrf_iqk_toneleakage_8852b(struct rf_info *rf, u8 path);
void halrf_iqk_sram_enable_8852b(struct rf_info *rf, bool iqk_sram_en);
void halrf_iqk_xym_enable_8852b(struct rf_info *rf, bool iqk_xym_en);
void halrf_iqk_fft_enable_8852b(struct rf_info *rf, bool iqk_fft_en);
void halrf_iqk_cfir_enable_8852b(struct rf_info *rf, bool iqk_cfir_en);
void halrf_iqk_onoff_8852b(struct rf_info *rf, bool is_enable);
void halrf_iqk_lok_bypass_8852b(struct rf_info *rf, u8 path);
void halrf_iqk_rx_bypass_8852b(struct rf_info *rf, u8 path);
void halrf_iqk_tx_bypass_8852b(struct rf_info *rf, u8 path);
void iqk_backup_mac_bb_8852b(struct rf_info *rf, u8 path,
u32 backup_mac[mac_reg_num_8852b],
u32 backup_bb[bb_reg_num_8852b],
u32 backup_mac_reg[mac_reg_num_8852b],
u32 backup_bb_reg[bb_reg_num_8852b]);
void iqk_backup_rf_8852b(struct rf_info *rf, u8 path,
u32 backup_rf[][rf_reg_num_8852b],
u32 backup_rf_reg[][rf_reg_num_8852b]);
void iqk_restore_mac_bb_8852b(struct rf_info *rf, u8 path,
u32 backup_mac[mac_reg_num_8852b],
u32 backup_bb[bb_reg_num_8852b],
u32 backup_mac_reg[mac_reg_num_8852b],
u32 backup_bb_reg[bb_reg_num_8852b]);
void iqk_restore_rf_8852b(struct rf_info *rf, u8 path,
u32 backup_rf[][rf_reg_num_8852b],
u32 backup_rf_reg[][rf_reg_num_8852b]);
void halrf_iqk_track_8852b(struct rf_info *rf);
bool halrf_iqk_get_ther_rek_8852b(struct rf_info *rf );
void halrf_iqk_dbcc_8852b(struct rf_info *rf, u8 path);
u8 halrf_iqk_get_mcc_ch0_8852b(struct rf_info *rf );
u8 halrf_iqk_get_mcc_ch1_8852b(struct rf_info *rf );
bool halrf_check_fwiqk_done_8852b(struct rf_info *rf);
void iqk_set_info_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
void halrf_enable_fw_iqk_8852b(struct rf_info *rf, bool is_fw_iqk);
u8 halrf_get_iqk_times_8852b(struct rf_info *rf) ;
u32 halrf_get_iqk_ver_8852b(void);
u8 halrf_iqk_get_rxevm_8852b(struct rf_info *rf);
u32 halrf_iqk_get_rximr_8852b(struct rf_info *rf, u8 path, u32 idx);
#endif
#endif /* __HALRF_IQK_8852BH__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_iqk_8852b.h
|
C
|
agpl-3.0
| 4,383
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
s8 _halrf_efuse_exchange_8852b(struct rf_info *rf, u8 value, u8 mask)
{
s8 tmp = 0;
if (mask == LOW_MASK) {
tmp = value & 0xf;
if (tmp & BIT(3))
tmp = tmp | 0xf0;
} else {
tmp = (value & 0xf0) >> 4;
if (tmp & BIT(3))
tmp = tmp | 0xf0;
}
return tmp;
}
void _halrf_set_thermal_trim_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 thermal_a, thermal_b;
RF_DBG(rf, DBG_RF_THER_TRIM, "======> %s phy=%d\n", __func__, phy);
if (!(rf->support_ability & HAL_RF_THER_TRIM)) {
RF_DBG(rf, DBG_RF_THER_TRIM, "<== %s phy=%d support_ability=%d Ther Trim Off!!!\n",
__func__, phy, rf->support_ability);
return;
}
halrf_phy_efuse_get_info(rf, THERMAL_TRIM_HIDE_EFUSE_A_8852B, 1, &thermal_a);
halrf_phy_efuse_get_info(rf, THERMAL_TRIM_HIDE_EFUSE_B_8852B, 1, &thermal_b);
RF_DBG(rf, DBG_RF_THER_TRIM, "efuse Ther_A=0x%x Ther_B=0x%x\n",
thermal_a, thermal_b);
if (thermal_a == 0xff && thermal_b == 0xff) {
RF_DBG(rf, DBG_RF_THER_TRIM, "Ther_A, Ther_B=0xff no PG Return!!!\n");
return;
}
thermal_a = thermal_a & 0x1f;
thermal_a = ((thermal_a & 0x1) << 3) | (thermal_a >> 1);
thermal_b = thermal_b & 0x1f;
thermal_b = ((thermal_b & 0x1) << 3) | (thermal_b >> 1);
RF_DBG(rf, DBG_RF_THER_TRIM, "After Exchange Ther_A=0x%x Ther_B=0x%x\n",
thermal_a, thermal_b);
halrf_wrf(rf, RF_PATH_A, 0x43, 0x000f0000, thermal_a);
halrf_wrf(rf, RF_PATH_B, 0x43, 0x000f0000, thermal_b);
}
void _halrf_set_pa_bias_trim_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 pa_bias_a, pa_bias_b;
u8 pa_bias_a_2g, pa_bias_b_2g, pa_bias_a_5g, pa_bias_b_5g;
RF_DBG(rf, DBG_RF_PABIAS_TRIM, "======> %s phy=%d\n", __func__, phy);
if (!(rf->support_ability & HAL_RF_PABIAS_TRIM)) {
RF_DBG(rf, DBG_RF_PABIAS_TRIM, "<== %s phy=%d support_ability=%d PA Bias K Off!!!\n",
__func__, phy, rf->support_ability);
return;
}
halrf_phy_efuse_get_info(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852B, 1, &pa_bias_a);
halrf_phy_efuse_get_info(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852B, 1, &pa_bias_b);
RF_DBG(rf, DBG_RF_PABIAS_TRIM, "efuse PA_Bias_A=0x%x PA_Bias_B=0x%x\n",
pa_bias_a, pa_bias_b);
if (pa_bias_a == 0xff && pa_bias_b == 0xff) {
RF_DBG(rf, DBG_RF_PABIAS_TRIM, "PA_Bias_A, PA_Bias_B=0xff no PG Return!!!\n");
return;
}
pa_bias_a_2g = pa_bias_a & 0xf;
pa_bias_a_5g = (pa_bias_a & 0xf0) >> 4;
pa_bias_b_2g = pa_bias_b & 0xf;
pa_bias_b_5g = (pa_bias_b & 0xf0) >> 4;
RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_A_2G=0x%x PA_Bias_A_5G=0x%x\n",
pa_bias_a_2g, pa_bias_a_5g);
RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_B_2G=0x%x PA_Bias_B_5G=0x%x\n",
pa_bias_b_2g, pa_bias_b_5g);
halrf_wrf(rf, RF_PATH_A, 0x60, 0x0000f000, pa_bias_a_2g);
halrf_wrf(rf, RF_PATH_A, 0x60, 0x000f0000, pa_bias_a_5g);
halrf_wrf(rf, RF_PATH_B, 0x60, 0x0000f000, pa_bias_b_2g);
halrf_wrf(rf, RF_PATH_B, 0x60, 0x000f0000, pa_bias_b_5g);
}
void _halrf_get_tssi_trim_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_tssi_info *tssi = &rf->tssi;
u8 i, j , check_tmp = 0;
RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s phy=%d\n", __func__, phy);
if (!(rf->support_ability & HAL_RF_TSSI_TRIM)) {
RF_DBG(rf, DBG_RF_TSSI_TRIM, "<== %s phy=%d support_ability=%d TSSI Trim Off!!!\n",
__func__, phy, rf->support_ability);
return;
}
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_2GL_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][0]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_2GH_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][1]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][2]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][3]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][4]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][5]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][6]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_A][7]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_2GL_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][0]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_2GH_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][1]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][2]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][3]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][4]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][5]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][6]);
halrf_phy_efuse_get_info(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852B, 1,
(u8 *)&tssi->tssi_trim[RF_PATH_B][7]);
for (i = 0; i < 2; i++) {
for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++) {
RF_DBG(rf, DBG_RF_TSSI_TRIM, "tssi->tssi_trim[%d][%d]=0x%x\n", i, j, tssi->tssi_trim[i][j]);
if ((tssi->tssi_trim[i][j] & 0xff) == 0xff)
check_tmp++;
}
}
RF_DBG(rf, DBG_RF_TSSI_TRIM, "check_tmp=%d\n", check_tmp);
if (check_tmp == 2 * TSSI_HIDE_EFUSE_NUM) {
for (i = 0; i < 2; i++) {
for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++)
tssi->tssi_trim[i][j] = 0;
}
RF_DBG(rf, DBG_RF_TSSI_TRIM, "TSSI Trim no PG tssi->tssi_trim=0x0\n");
}
}
void halrf_get_efuse_trim_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
_halrf_set_thermal_trim_8852b(rf, phy);
_halrf_set_pa_bias_trim_8852b(rf, phy);
_halrf_get_tssi_trim_8852b(rf, phy);
}
#endif /*RF_8852B_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.c
|
C
|
agpl-3.0
| 6,530
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_KFREE_8852B_H_
#define _HALRF_KFREE_8852B_H_
#ifdef RF_8852B_SUPPORT
/*@--------------------------Define Parameters-------------------------------*/
#define THERMAL_TRIM_HIDE_EFUSE_A_8852B 0x5DF
#define THERMAL_TRIM_HIDE_EFUSE_B_8852B 0x5DC
#define PABIAS_TRIM_HIDE_EFUSE_A_8852B 0x5DE
#define PABIAS_TRIM_HIDE_EFUSE_B_8852B 0x5DB
#define TSSI_TRIM_HIDE_EFUSE_2GL_A_8852B 0x5D6
#define TSSI_TRIM_HIDE_EFUSE_2GH_A_8852B 0x5D5
#define TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852B 0x5D4
#define TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852B 0x5D3
#define TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852B 0x5D2
#define TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852B 0x5D1
#define TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852B 0x5D0
#define TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852B 0x5CF
#define TSSI_TRIM_HIDE_EFUSE_2GL_B_8852B 0x5AB
#define TSSI_TRIM_HIDE_EFUSE_2GH_B_8852B 0x5AA
#define TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852B 0x5A9
#define TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852B 0x5A8
#define TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852B 0x5A7
#define TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852B 0x5A6
#define TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852B 0x5A5
#define TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852B 0x5A4
/*@-----------------------End Define Parameters-----------------------*/
void halrf_get_efuse_trim_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
#endif
#endif /*_HALRF_SET_PWR_TABLE_8852B_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_kfree_8852b.h
|
C
|
agpl-3.0
| 1,968
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
void _halrf_psd_backup_bb_registers_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
u32 *reg,
u32 *reg_backup,
u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++) {
reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD);
RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n",
reg[i], reg_backup[i]);
}
}
void _halrf_psd_reload_bb_registers_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
u32 *reg,
u32 *reg_backup,
u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++) {
halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]);
RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n",
reg[i], reg_backup[i]);
}
}
void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u8 path, u8 iq_path, u32 avg, u32 fft)
{
struct halrf_psd_data *psd_info = &rf->psd;
u32 bb_reg[PSD_BACKUP_NUM_8852B] = {
0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8,
0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008,
0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c,
0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490,
0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088,
0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120,
0x8220, 0x8018, 0x8000, 0x800c, 0x81cc,
0x82cc, 0x802c, 0x8034, 0x80d4, 0x80fc,
0x801c};
RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d\n", __func__, phy);
psd_info->psd_progress = 1;
_halrf_psd_backup_bb_registers_8852b(rf, phy, bb_reg,
psd_info->psd_reg_backup, PSD_BACKUP_NUM_8852B);
psd_info->path = path;
psd_info->iq_path = iq_path;
psd_info->avg = avg;
psd_info->fft = fft;
/*02_BB_AFE_PHY0*/
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303);
halrf_wreg(rf, 0x5864, 0x18000000, 0x3);
halrf_wreg(rf, 0x7864, 0x18000000, 0x3);
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
halrf_wreg(rf, 0x12b8, 0x10000000, 0x1);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x1);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x1);
halrf_wreg(rf, 0x5864, 0xc0000000, 0x3);
halrf_wreg(rf, 0x7864, 0xc0000000, 0x3);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff);
halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1);
halrf_wreg(rf, 0x0700, 0x08000000, 0x1);
halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff);
halrf_wreg(rf, 0x0c60, 0x00000003, 0x3);
halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1);
halrf_wreg(rf, 0x58ac, 0x08000000, 0x1);
halrf_wreg(rf, 0x78ac, 0x08000000, 0x1);
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1);
halrf_wreg(rf, 0x2320, 0x00000001, 0x1);
halrf_wreg(rf, 0x4490, 0x80000000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00007000, 0x7);
halrf_wreg(rf, 0x12a0, 0x00008000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00070000, 0x3);
halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00070000, 0x3);
halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
halrf_wreg(rf, 0x0700, 0x06000000, 0x2);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x3333);
/*03_IQK_Preset_Non_DBCC_PHY0*/
halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0);
halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0);
halrf_wreg(rf, 0x8008, 0xffffffff, 0x00000080);
halrf_wreg(rf, 0x8080, 0xffffffff, 0x00000000);
halrf_wreg(rf, 0x8088, 0xffffffff, 0x81ff010a);
halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00200000);
halrf_wreg(rf, 0x8074, 0xffffffff, 0x80000000);
halrf_wreg(rf, 0x81dc, 0xffffffff, 0x00000000);
halrf_wreg(rf, 0x82dc, 0xffffffff, 0x00000000);
/*07_CLK_Setting_RxIQK_BW80M_Non_DBCC_PHY0*/
halrf_wreg(rf, 0x8120, 0xffffffff, 0x4d000a08);
halrf_wreg(rf, 0x8220, 0xffffffff, 0x4d000a08);
halrf_wreg(rf, 0x12a0, 0x00070000, 0x2);
halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00070000, 0x2);
halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
halrf_wreg(rf, 0x0700, 0x06000000, 0x1);
/*windowing*/
halrf_wreg(rf, 0x8018, 0xfffffffe, 0x20008080);
if (fft == 160)
halrf_wreg(rf, 0x801c, 0x00003000, 0x0);
else if (fft == 320)
halrf_wreg(rf, 0x801c, 0x00003000, 0x1);
else if (fft == 640)
halrf_wreg(rf, 0x801c, 0x00003000, 0x2);
else /*1280*/
halrf_wreg(rf, 0x801c, 0x00003000, 0x3);
if (avg == 1)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x0);
else if (avg == 2)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x1);
else if (avg == 4)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x2);
else if (avg == 8)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x3);
else if (avg == 16)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x4);
else if (avg == 64)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x6);
else if (avg == 128)
halrf_wreg(rf, 0x801c, 0x000e0000, 0x7);
else /*32*/
halrf_wreg(rf, 0x801c, 0x000e0000, 0x5);
}
void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct halrf_psd_data *psd_info = &rf->psd;
u32 bb_reg[PSD_BACKUP_NUM_8852B] = {
0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8,
0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008,
0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c,
0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490,
0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088,
0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120,
0x8220, 0x8018, 0x8000, 0x800c, 0x81cc,
0x82cc, 0x802c, 0x8034, 0x80d4, 0x80fc,
0x801c};
RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d\n", __func__, phy);
_halrf_psd_reload_bb_registers_8852b(rf, phy, bb_reg,
psd_info->psd_reg_backup, PSD_BACKUP_NUM_8852B);
halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x1);
halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x1);
psd_info->psd_progress = 0;
#if 0
/*98_IQK_Reg_Non_DBCC_PHY0_path01_Restore*/
halrf_wreg(rf, 0x8008, 0xffffffff, 0x00000000);
halrf_wreg(rf, 0x8074, 0xffffffff, 0x00000000);
halrf_wreg(rf, 0x8088, 0xffffffff, 0x80000000);
halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00000000);
halrf_wreg(rf, 0x80e0, 0x00000001, 0x0);
halrf_wreg(rf, 0x8120, 0xffffffff, 0x10010000);
halrf_wreg(rf, 0x8140, 0x00000100, 0x0);
halrf_wreg(rf, 0x8150, 0xffffffff, 0xe4e4e4e4);
halrf_wreg(rf, 0x8154, 0x00000100, 0x0);
halrf_wreg(rf, 0x81cc, 0x0000003f, 0x0);
halrf_wreg(rf, 0x81dc, 0xffffffff, 0x00000002);
halrf_wreg(rf, 0x8220, 0xffffffff, 0x10010000);
halrf_wreg(rf, 0x8240, 0x00000100, 0x0);
halrf_wreg(rf, 0x8250, 0xffffffff, 0xe4e4e4e4);
halrf_wreg(rf, 0x8254, 0x00000100, 0x0);
halrf_wreg(rf, 0x82cc, 0x0000003f, 0x0);
halrf_wreg(rf, 0x82dc, 0xffffffff, 0x00000002);
/*99_BB_AFE_Non_DBCC_PHY0_path01_restore*/
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303);
halrf_wreg(rf, 0x12b8, 0x40000000, 0x0);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x0);
halrf_wreg(rf, 0x5864, 0xc0000000, 0x0);
halrf_wreg(rf, 0x7864, 0xc0000000, 0x0);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000);
halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0);
halrf_wreg(rf, 0x0700, 0x08000000, 0x0);
halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03);
halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03);
halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00);
halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00);
halrf_wreg(rf, 0x0700, 0x07000000, 0x0);
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0);
halrf_wreg(rf, 0x2320, 0x00000001, 0x0);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x0);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x0);
#endif
}
u32 halrf_psd_get_point_data_8852b(struct rf_info *rf,
enum phl_phy_idx phy, s32 point)
{
struct halrf_psd_data *psd_info = &rf->psd;
u32 val_tmp, val, data;
halrf_wreg(rf, 0x8088, 0xffffffff, 0x81ff0109);
if (psd_info->path == RF_PATH_A)
halrf_wreg(rf, 0x8000, 0xffffffff, 0x00000008);
else
halrf_wreg(rf, 0x8000, 0xffffffff, 0x0000000a);
halrf_wreg(rf, 0x800c, 0xffffffff, 0x00000c00);
halrf_wreg(rf, 0x8018, 0xfffffffe, 0x20008080);
halrf_wreg(rf, 0x80d0, 0xffffffff, 0x00300000);
if (psd_info->path == RF_PATH_A)
halrf_wreg(rf, 0x81cc, 0x0000003f, 0x3f);
else
halrf_wreg(rf, 0x82cc, 0x0000003f, 0x3f);
halrf_wreg(rf, 0x802c, 0x0fff0000, (point & 0xfff));
halrf_wreg(rf, 0x8034, 0x00000001, 0x1);
halrf_wreg(rf, 0x8034, 0x00000001, 0x0);
halrf_delay_ms(rf, 1);
halrf_wreg(rf, 0x80d4, 0xffffffff, 0x002d0000);
val_tmp = halrf_rreg(rf, 0x80fc, 0x007f0000);
halrf_wreg(rf, 0x80d4, 0xffffffff, 0x002e0000);
val = halrf_rreg(rf, 0x80fc, 0xffffffff);
data = (val_tmp << 25) | (val >> 7);
RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d point=0x%x data=0x%08x\n",
__func__, phy, point, data);
return data;
}
void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf)
{
struct halrf_psd_data *psd_info = &rf->psd;
struct rtw_hal_com_t *hal = rf->hal_com;
u32 i = 0, j = 0;
s32 point_temp;
RF_DBG(rf, DBG_RF_PSD, "======> %s phy=%d point=%d start_point=%d stop_point=%d\n",
__func__, phy, point, start_point, stop_point);
if (psd_info->psd_result_running == true) {
RF_DBG(rf, DBG_RF_PSD, "======> %s PSD Running Return !!!\n", __func__);
return;
}
psd_info->psd_result_running = true;
hal_mem_set(hal, psd_info->psd_data, 0, sizeof(psd_info->psd_data));
i = start_point;
while (i < stop_point) {
if (i >= point)
point_temp = i - point;
else
{
point_temp = i - point;
point_temp = point_temp & 0xfff;
}
psd_info->psd_data[j] = halrf_psd_get_point_data_8852b(rf, phy, point_temp);
i++;
j++;
}
RF_DBG(rf, DBG_RF_PSD, "psd_info->psd_data\n");
for (i = 0; i < 320; i = i + 10) {
RF_DBG(rf, DBG_RF_PSD, "%d %d %d %d %d %d %d %d %d %d\n",
psd_info->psd_data[i], psd_info->psd_data[i + 1],
psd_info->psd_data[i + 2], psd_info->psd_data[i + 3],
psd_info->psd_data[i + 4], psd_info->psd_data[i + 5],
psd_info->psd_data[i + 6], psd_info->psd_data[i + 7],
psd_info->psd_data[i + 8], psd_info->psd_data[i + 9]);
}
hal_mem_cpy(hal, outbuf, psd_info->psd_data,
sizeof(psd_info->psd_data));
RF_DBG(rf, DBG_RF_PSD, "======> %s PSD End !!!\n", __func__);
psd_info->psd_result_running = false;
}
#endif /*RF_8852B_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.c
|
C
|
agpl-3.0
| 10,464
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_PSD_TSSI_8852B_H_
#define _HALRF_PSD_TSSI_8852B_H_
#ifdef RF_8852B_SUPPORT
#define PSD_VER_8852B 0x1
#define PSD_BACKUP_NUM_8852B 41
/*@--------------------------Define Parameters-------------------------------*/
/*@-----------------------End Define Parameters-----------------------*/
void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u8 path, u8 iq_path, u32 avg, u32 fft);
void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy);
u32 halrf_psd_get_point_data_8852b(struct rf_info *rf,
enum phl_phy_idx phy, s32 point);
void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf);
#endif /*RF_8852B_SUPPORT*/
#endif /*_HALRF_PSD_TSSI_8852B_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_psd_8852b.h
|
C
|
agpl-3.0
| 1,438
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
void halrf_cfg_rf_radio_a_8852b(struct rf_info *rf, u32 addr, u32 data)
{
/*laod radio a table*/
if (addr == 0xfe)
halrf_delay_ms(rf, 50);
else if (addr == 0xfd)
halrf_delay_ms(rf, 5);
else if (addr == 0xfc)
halrf_delay_ms(rf, 1);
else if (addr == 0xfb)
halrf_delay_us(rf, 50);
else if (addr == 0xfa)
halrf_delay_us(rf, 5);
else if (addr == 0xf9)
halrf_delay_us(rf, 1);
else
halrf_wrf(rf, RF_PATH_A, addr, MASKRF, data);
RF_DBG(rf, DBG_RF_INIT, "[RF_a] %08X %08X\n", addr, data);
}
void halrf_cfg_rf_radio_b_8852b(struct rf_info *rf, u32 addr, u32 data)
{
/*laod radio b table*/
if (addr == 0xfe)
halrf_delay_ms(rf, 50);
else if (addr == 0xfd)
halrf_delay_ms(rf, 5);
else if (addr == 0xfc)
halrf_delay_ms(rf, 1);
else if (addr == 0xfb)
halrf_delay_us(rf, 50);
else if (addr == 0xfa)
halrf_delay_us(rf, 5);
else if (addr == 0xf9)
halrf_delay_us(rf, 1);
else
halrf_wrf(rf, RF_PATH_B, addr, MASKRF, data);
RF_DBG(rf, DBG_RF_INIT, "[RF_b] %08X %08X\n", addr, data);
}
void halrf_cfg_rf_nctl_8852b(struct rf_info *rf, u32 addr, u32 mask, u32 data)
{
/*laod NCTL table*/
if (addr == 0xfe)
halrf_delay_ms(rf, 50);
else if (addr == 0xfd)
halrf_delay_ms(rf, 5);
else if (addr == 0xfc)
halrf_delay_ms(rf, 1);
else if (addr == 0xfb)
halrf_delay_us(rf, 50);
else if (addr == 0xfa)
halrf_delay_us(rf, 5);
else if (addr == 0xf9)
halrf_delay_us(rf, 1);
else
halrf_wreg(rf, addr, mask, data);
RF_DBG(rf, DBG_RF_INIT, "[RFK] %08X %08X\n", addr, data);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.c
|
C
|
agpl-3.0
| 2,578
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_REG_CFG_8852B_H_
#define _HALRF_REG_CFG_8852B_H_
#ifdef RF_8852B_SUPPORT
void halrf_cfg_rf_radio_a_8852b(struct rf_info *rf, u32 addr, u32 data);
void halrf_cfg_rf_radio_b_8852b(struct rf_info *rf, u32 addr, u32 data);
void halrf_cfg_rf_nctl_8852b(struct rf_info *rf, u32 addr, u32 mask, u32 data);
#endif
#endif /* RTL8822C_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_reg_cfg_8852b.h
|
C
|
agpl-3.0
| 1,321
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
s8 _halrf_avg_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *value, s8 n)
{
u8 i;
s16 total = 0;
RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__);
for (i = 0; i < n; i++) {
total = total + value[i];
RF_DBG(rf, DBG_RF_POWER, "value[%d]=%d total=%d n=%d\n", i, value[i], total, n);
}
total = total / n;
return (s8)total;
}
void _halrf_bub_sort_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *data, u32 n)
{
s32 i, j, sp;
s8 temp;
u32 k;
for (k = 0; k < n; k++)
RF_DBG(rf, DBG_RF_POWER, "===> %s Before data[%d]=%d\n", __func__, k, data[k]);
for (i = n - 1; i >= 0; i--) {
sp = 1;
for (j = 0; j < i; j++) {
if (data[j] < data[j + 1]) {
temp = data[j];
data[j] = data[j + 1];
data[j + 1] = temp;
sp = 0;
}
}
if (sp == 1)
break;
}
for (k = 0; k < n; k++)
RF_DBG(rf, DBG_RF_POWER, "<=== %s After data[%d]=%d\n", __func__, k, data[k]);
}
bool halrf_set_power_by_rate_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i;
u32 i, j;
RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__);
rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) / 2;
rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) / 2;
rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0) / 2;
rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2;
rate->pwr_by_rate_lgcy[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM6, 0, 0) / 2;
rate->pwr_by_rate_lgcy[5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM9, 0, 0) / 2;
rate->pwr_by_rate_lgcy[6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM12, 0, 0) / 2;
rate->pwr_by_rate_lgcy[7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM18, 0, 0) / 2;
rate->pwr_by_rate_lgcy[8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM24, 0, 0) / 2;
rate->pwr_by_rate_lgcy[9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM36, 0, 0) / 2;
rate->pwr_by_rate_lgcy[10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM48, 0, 0) / 2;
rate->pwr_by_rate_lgcy[11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS0, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS1, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS2, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS3, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS5, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS6, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS8, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS9, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS10, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS11, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS0, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS1, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS3, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS0, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS1, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS2, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS3, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS5, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS6, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS8, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS9, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS10, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS11, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS0, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS1, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS3, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS0, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS1, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS3, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2;
/*CCK, Legacy, HT, VHT, HE*/
tpu->pwr_ofst_mode[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS11, 0, 1) / 2;
tpu->pwr_ofst_mode[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_VHT_NSS1_MCS9, 0, 1) / 2;
tpu->pwr_ofst_mode[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_MCS7, 0, 1) / 2;
tpu->pwr_ofst_mode[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 1) / 2;
tpu->pwr_ofst_mode[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 1) / 2;
for (i = 0; i < 12; i = i + 4)
RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n",
rate->pwr_by_rate_lgcy[i + 3],
rate->pwr_by_rate_lgcy[i + 2],
rate->pwr_by_rate_lgcy[i + 1],
rate->pwr_by_rate_lgcy[i]);
for (j = 0; j < 2; j++)
for (i = 0; i < 16; i = i + 4)
RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n",
rate->pwr_by_rate[j][i + 3],
rate->pwr_by_rate[j][i + 2],
rate->pwr_by_rate[j][i + 1],
rate->pwr_by_rate[j][i]);
RF_DBG(rf, DBG_RF_POWER, "power_by_rate_offset ==> %d %d %d %d %d\n",
tpu->pwr_ofst_mode[4],
tpu->pwr_ofst_mode[3],
tpu->pwr_ofst_mode[2],
tpu->pwr_ofst_mode[1],
tpu->pwr_ofst_mode[0]);
return true;
}
bool halrf_set_power_by_rate_all_the_smae_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i;
u32 i, j;
RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__);
rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2;
rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2;
rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2;
rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0) / 2;
rate->pwr_by_rate_lgcy[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate_lgcy[11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_1T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][5] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][6] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][7] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][8] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][9] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][10] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][11] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS7, 0, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][12] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][13] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][14] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2;
rate->pwr_by_rate[PW_LMT_PH_2T][15] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS2_MCS4, 1, 0) / 2;
/*CCK, Legacy, HT, VHT, HE*/
tpu->pwr_ofst_mode[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS11, 0, 1) / 2;
tpu->pwr_ofst_mode[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_VHT_NSS1_MCS9, 0, 1) / 2;
tpu->pwr_ofst_mode[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_MCS7, 0, 1) / 2;
tpu->pwr_ofst_mode[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, 0, 1) / 2;
tpu->pwr_ofst_mode[4] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 1) / 2;
for (i = 0; i < 12; i = i + 4)
RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n",
rate->pwr_by_rate_lgcy[i + 3],
rate->pwr_by_rate_lgcy[i + 2],
rate->pwr_by_rate_lgcy[i + 1],
rate->pwr_by_rate_lgcy[i]);
for (j = 0; j < 2; j++)
for (i = 0; i < 16; i = i + 4)
RF_DBG(rf, DBG_RF_POWER, "power_by_rate ==> %d %d %d %d\n",
rate->pwr_by_rate[j][i + 3],
rate->pwr_by_rate[j][i + 2],
rate->pwr_by_rate[j][i + 1],
rate->pwr_by_rate[j][i]);
RF_DBG(rf, DBG_RF_POWER, "power_by_rate_offset ==> %d %d %d %d %d\n",
tpu->pwr_ofst_mode[0],
tpu->pwr_ofst_mode[1],
tpu->pwr_ofst_mode[2],
tpu->pwr_ofst_mode[3],
tpu->pwr_ofst_mode[4]);
return true;
}
void halrf_get_power_limit_to_struct_20m_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
hal_mem_set(hal, lmt, 0, sizeof(*lmt));
/*1Tx CCK 20m NOBF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx CCK 20m BF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*1Tx CCK 40m NOBF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx CCK 40m BF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*1Tx OFDM NOBF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx OFDM BF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*1Tx 20m NOBF*/
lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx 20m BF*/
lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*2Tx CCK 20m NOBF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx CCK 20m BF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
/*2Tx CCK 40m NOBF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx CCK 40m BF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
/*2Tx OFDM NOBF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx OFDM BF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
/*2Tx 20m NOBF*/
lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx 20m BF*/
lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
}
void halrf_get_power_limit_to_struct_40m_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
hal_mem_set(hal, lmt, 0, sizeof(*lmt));
/*1Tx CCK 20m NONBF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2;
/*1Tx CCK 20m BF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2;
/*1Tx CCK 40m NONBF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx CCK 40m BF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*1Tx OFDM NONBF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2;
/*1Tx OFDM BF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2;
/*1Tx 20m NOBF*/
lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 2) / 2;
/*1Tx 20m BF*/
lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch + 2) / 2;
/*1Tx 40m NOBF*/
lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx 40m BF*/
lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*2Tx CCK 20m NONBF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2;
/*2Tx CCK 20m BF*/
lmt->pwr_lmt_cck_20m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2;
/*2Tx CCK 40m NONBF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx CCK 40m BF*/
lmt->pwr_lmt_cck_40m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
/*2Tx OFDM NONBF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2;
/*2Tx OFDM BF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2;
/*2Tx 20m NOBF*/
lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 2) / 2;
/*2Tx 20m BF*/
lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch + 2) / 2;
/*2Tx 40m NOBF*/
lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx 40m BF*/
lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
}
void halrf_get_power_limit_to_struct_80m_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
s8 tmp, tmp1, tmp2;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
hal_mem_set(hal, lmt, 0, sizeof(*lmt));
/*1Tx OFDM NONBF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 6) / 2;
/*1Tx OFDM BF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_1T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 6) / 2;
/*1Tx 20m NOBF*/
lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 6) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][2][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][3][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 6) / 2;
/*1Tx 20m BF*/
lmt->pwr_lmt_20m[PW_LMT_PH_1T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 6) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][1][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][2][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch + 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_1T][3][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_1T, ch + 6) / 2;
/*1Tx 40m NOBF*/
lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 4) / 2;
lmt->pwr_lmt_40m[PW_LMT_PH_1T][1][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 4) / 2;
/*1Tx 40m BF*/
lmt->pwr_lmt_40m[PW_LMT_PH_1T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch - 4) / 2;
lmt->pwr_lmt_40m[PW_LMT_PH_1T][1][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch + 4) / 2;
/*1Tx 80m NOBF*/
lmt->pwr_lmt_80m[PW_LMT_PH_1T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_NONBF, PW_LMT_PH_1T, ch) / 2;
/*1Tx 80m BF*/
lmt->pwr_lmt_80m[PW_LMT_PH_1T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_BF, PW_LMT_PH_1T, ch) / 2;
/*1Tx 40m 0p5 NOBF*/
tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch - 4) / 2;
tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_1T, ch + 4) / 2;
if (tmp1 >= tmp2)
tmp = tmp2;
else
tmp = tmp1;
lmt->pwr_lmt_40m_0p5[PW_LMT_PH_1T][PW_LMT_NONBF] = tmp;
/*1Tx 40m 0p5 BF*/
tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch - 4) / 2;
tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_1T, ch + 4) / 2;
if (tmp1 >= tmp2)
tmp = tmp2;
else
tmp = tmp1;
lmt->pwr_lmt_40m_0p5[PW_LMT_PH_1T][PW_LMT_BF] = tmp;
/*2Tx OFDM NONBF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 6) / 2;
/*2Tx OFDM BF*/
lmt->pwr_lmt_lgcy_20m[PW_LMT_PH_2T][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_OFDM54, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 6) / 2;
/*2Tx 20m NOBF*/
lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 6) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][2][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][3][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 6) / 2;
/*2Tx 20m BF*/
lmt->pwr_lmt_20m[PW_LMT_PH_2T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 6) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][1][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch - 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][2][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch + 2) / 2;
lmt->pwr_lmt_20m[PW_LMT_PH_2T][3][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_20M, PW_LMT_BF, PW_LMT_PH_2T, ch + 6) / 2;
/*2Tx 40m NOBF*/
lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 4) / 2;
lmt->pwr_lmt_40m[PW_LMT_PH_2T][1][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 4) / 2;
/*2Tx 40m BF*/
lmt->pwr_lmt_40m[PW_LMT_PH_2T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch - 4) / 2;
lmt->pwr_lmt_40m[PW_LMT_PH_2T][1][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch + 4) / 2;
/*2Tx 80m NOBF*/
lmt->pwr_lmt_80m[PW_LMT_PH_2T][0][PW_LMT_NONBF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_NONBF, PW_LMT_PH_2T, ch) / 2;
/*2Tx 80m BF*/
lmt->pwr_lmt_80m[PW_LMT_PH_2T][0][PW_LMT_BF] =
halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_80M, PW_LMT_BF, PW_LMT_PH_2T, ch) / 2;
/*2Tx 40m 0p5 NOBF*/
tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch - 4) / 2;
tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_NONBF, PW_LMT_PH_2T, ch + 4) / 2;
if (tmp1 >= tmp2)
tmp = tmp2;
else
tmp = tmp1;
lmt->pwr_lmt_40m_0p5[PW_LMT_PH_2T][PW_LMT_NONBF] = tmp;
/*2Tx 40m 0p5 BF*/
tmp1 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch - 4) / 2;
tmp2 = halrf_get_power_limit(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_BW_40M, PW_LMT_BF, PW_LMT_PH_2T, ch + 4) / 2;
if (tmp1 >= tmp2)
tmp = tmp2;
else
tmp = tmp1;
lmt->pwr_lmt_40m_0p5[PW_LMT_PH_2T][PW_LMT_BF] = tmp;
}
bool halrf_set_power_limit_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_pwr_imt_info *lmt = &rf->hal_com->band[phy].rtw_tpu_i.rtw_tpu_pwr_imt_i;
u8 bw = rf->hal_com->band[phy].cur_chandef.bw;
u32 i;
s8 tmp;
RF_DBG(rf, DBG_RF_POWER, "======>%s bandwidth=%d\n",
__func__, bw);
if (bw == CHANNEL_WIDTH_20)
halrf_get_power_limit_to_struct_20m_8852b(rf, phy);
else if (bw == CHANNEL_WIDTH_40)
halrf_get_power_limit_to_struct_40m_8852b(rf, phy);
else
halrf_get_power_limit_to_struct_80m_8852b(rf, phy);
tmp = lmt->pwr_lmt_cck_40m[0][0];
for (i = 0; i < 2; i++) {
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_cck_40m[i][1], lmt->pwr_lmt_cck_40m[i][0],
lmt->pwr_lmt_cck_20m[i][1], lmt->pwr_lmt_cck_20m[i][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_20m[i][0][1], lmt->pwr_lmt_20m[i][0][0],
lmt->pwr_lmt_lgcy_20m[i][1], lmt->pwr_lmt_lgcy_20m[i][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_20m[i][2][1], lmt->pwr_lmt_20m[i][2][0],
lmt->pwr_lmt_20m[i][1][1], lmt->pwr_lmt_20m[i][1][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_20m[i][4][1], lmt->pwr_lmt_20m[i][4][0],
lmt->pwr_lmt_20m[i][3][1], lmt->pwr_lmt_20m[i][3][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_20m[i][6][1], lmt->pwr_lmt_20m[i][6][0],
lmt->pwr_lmt_20m[i][5][1], lmt->pwr_lmt_20m[i][5][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_40m[i][0][1], lmt->pwr_lmt_40m[i][0][0],
lmt->pwr_lmt_20m[i][7][1], lmt->pwr_lmt_20m[i][7][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_40m[i][2][1], lmt->pwr_lmt_40m[i][2][0],
lmt->pwr_lmt_40m[i][1][1], lmt->pwr_lmt_40m[i][1][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_80m[i][0][1], lmt->pwr_lmt_80m[i][0][0],
lmt->pwr_lmt_40m[i][3][1], lmt->pwr_lmt_40m[i][3][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_160m[i][1], lmt->pwr_lmt_160m[i][0],
lmt->pwr_lmt_80m[i][1][1], lmt->pwr_lmt_80m[i][1][0]);
RF_DBG(rf, DBG_RF_POWER, "power_limit ==> %d %d %d %d\n",
lmt->pwr_lmt_40m_2p5[i][1], lmt->pwr_lmt_40m_2p5[i][0],
lmt->pwr_lmt_40m_0p5[i][1], lmt->pwr_lmt_40m_0p5[i][0]);
}
return true;
}
void halrf_get_power_limit_ru_to_struct_20m_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
hal_mem_set(hal, tpu->pwr_lmt_ru, 0, sizeof(tpu->pwr_lmt_ru));
/*1Tx RU26*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch) / 2;
/*1Tx RU52*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch) / 2;
/*1Tx RU106*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch) / 2;
/*2Tx RU26*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch) / 2;
/*2Tx RU52*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch) / 2;
/*2Tx RU106*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch) / 2;
}
void halrf_get_power_limit_ru_to_struct_40m_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
hal_mem_set(hal, tpu->pwr_lmt_ru, 0, sizeof(tpu->pwr_lmt_ru));
/*1Tx RU26*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch + 2) / 2;
/*1Tx RU52*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch + 2) / 2;
/*1Tx RU106*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch + 2) / 2;
/*2TX RU26*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch + 2) / 2;
/*2TX RU52*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch + 2) / 2;
/*2TX RU106*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch + 2) / 2;
}
void halrf_get_power_limit_ru_to_struct_80m_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
hal_mem_set(hal, tpu->pwr_lmt_ru, 0, sizeof(tpu->pwr_lmt_ru));
/*1TX RU26*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch - 6) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][2] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch + 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU26][3] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_1T, ch + 6) / 2;
/*1TX RU52*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch - 6) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][2] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch + 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU52][3] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_1T, ch + 6) / 2;
/*1TX RU106*/
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch - 6) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][2] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch + 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_1T][PW_LMT_RU_BW_RU106][3] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_1T, ch + 6) / 2;
/*2TX RU26*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch - 6) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][2] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch + 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU26][3] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU26, PW_LMT_PH_2T, ch + 6) / 2;
/*2TX RU52*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch - 6) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][2] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch + 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU52][3] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU52, PW_LMT_PH_2T, ch + 6) / 2;
/*2TX RU106*/
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][0] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch - 6) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][1] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch - 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][2] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch + 2) / 2;
tpu->pwr_lmt_ru[PW_LMT_PH_2T][PW_LMT_RU_BW_RU106][3] =
halrf_get_power_limit_ru(rf, phy, RF_PATH_A, RTW_DATA_RATE_HE_NSS1_MCS7, PW_LMT_RU_BW_RU106, PW_LMT_PH_2T, ch + 6) / 2;
}
bool halrf_set_power_limit_ru_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
u8 bw = rf->hal_com->band[phy].cur_chandef.bw;
u8 i, j, k;
RF_DBG(rf, DBG_RF_POWER, "======>%s bandwidth=%d\n",
__func__, bw);
if (bw == CHANNEL_WIDTH_20)
halrf_get_power_limit_ru_to_struct_20m_8852b(rf, phy);
else if (bw == CHANNEL_WIDTH_40) {
halrf_get_power_limit_ru_to_struct_40m_8852b(rf, phy);
} else if (bw == CHANNEL_WIDTH_80) {
halrf_get_power_limit_ru_to_struct_80m_8852b(rf, phy);
}
tpu->pwr_lmt_ru_mem_size = tpu->pwr_lmt_ru_mem_size;
for (k = 0; k < 2; k++) {
for (j = 0; j < PW_LMT_RU_BW_NULL; j++) {
for (i = 0; i < 8; i = i + 4) {
RF_DBG(rf, DBG_RF_POWER,
"power_limit_ru %dTx ==> %d %d %d %d\n",
k + 1,
tpu->pwr_lmt_ru[k][j][i + 3],
tpu->pwr_lmt_ru[k][j][i + 2],
tpu->pwr_lmt_ru[k][j][i + 1],
tpu->pwr_lmt_ru[k][j][i]);
}
}
}
return true;
}
void _halrf_set_tx_shape_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
u8 ch = rf->hal_com->band[phy].cur_chandef.center_ch;
u8 reg;
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d\n", __func__, ch);
if (!(rf->support_ability & HAL_RF_TX_SHAPE)) {
RF_DBG(rf, DBG_RF_POWER, "======>%s rf->support_ability & HAL_RF_TX_SHAPE=%d Return!!!\n",
__func__, rf->support_ability & HAL_RF_TX_SHAPE);
return;
}
if (pwr->set_tx_ptrn_shap_en == true) {
RF_DBG(rf, DBG_RF_POWER, "======>%s pwr->set_tx_ptrn_shap_en == true Return!!!\n",
__func__);
return;
} else {
RF_DBG(rf, DBG_RF_POWER, "======>%s pwr->set_tx_ptrn_shap_en == false Set TX shape Default\n",
__func__);
}
if (ch >= 1 && ch <= 14) {
reg = halrf_get_regulation_info(rf, BAND_ON_24G);
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d regulation=%d\n", __func__, ch, reg);
RF_DBG(rf, DBG_RF_POWER, "tpu->tx_ptrn_shap_idx=%d pwr->tx_shap_idx[%d][CCK][%d]=%d pwr->tx_shap_idx[%d][OFDM][%d]=%d\n",
tpu->tx_ptrn_shap_idx, PW_LMT_BAND_2_4G, reg,
pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg],
PW_LMT_BAND_2_4G, reg,
pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg]);
tpu->tx_ptrn_shap_idx = pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg];
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK] =
pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg];
halrf_bb_set_pow_patten_sharp(rf, ch, true,
pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK][reg], phy); /*cck*/
RF_DBG(rf, DBG_RF_POWER, "[TX shape] tpu->tx_ptrn_shap_idx=%d channel=%d Set CCK Tx Shape!!!\n",
tpu->tx_ptrn_shap_idx, ch);
tpu->tx_ptrn_shap_idx = pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg];
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM] =
pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg];
halrf_bb_set_pow_patten_sharp(rf, ch, false,
pwr->tx_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM][reg], phy); /*ofdm*/
RF_DBG(rf, DBG_RF_POWER, "[TX shape] tpu->tx_ptrn_shap_idx=%d channel=%d Set OFDM Tx Shape!!!\n",
tpu->tx_ptrn_shap_idx, ch);
} else if (ch >= 36 && ch <= 177) {
reg = halrf_get_regulation_info(rf, BAND_ON_5G);
RF_DBG(rf, DBG_RF_POWER, "======>%s channel=%d regulation=%d\n", __func__, ch, reg);
RF_DBG(rf, DBG_RF_POWER, "tpu->tx_ptrn_shap_idx=%d pwr->tx_shap_idx[%d][OFDM][%d]=%d\n",
tpu->tx_ptrn_shap_idx, PW_LMT_BAND_5G, reg,
pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg]);
tpu->tx_ptrn_shap_idx = pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg];
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM] =
pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg];
halrf_bb_set_pow_patten_sharp(rf, ch, false,
pwr->tx_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM][reg], phy); /*ofdm*/
RF_DBG(rf, DBG_RF_POWER, "[TX shape] tpu->tx_ptrn_shap_idx=%d channel=%d Set Tx Shape!!!\n",
tpu->tx_ptrn_shap_idx, ch);
} else {
#if 0
reg = halrf_get_regulation_info(rf, BAND_ON_6G);
pwr->tx_shap_idx[PW_LMT_BAND_6G][reg];
#endif
}
}
bool _halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 i;
RF_DBG(rf, DBG_RF_POWER, "======>%s phl_pwr_table=%d\n", __func__, pwr_table);
RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_by_rate_switch=%d\n",
__func__, pwr->pwr_by_rate_switch);
RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_limit_switch=%d\n",
__func__, pwr->pwr_limit_switch);
RF_DBG(rf, DBG_RF_POWER, "======>%s From Efuse pwr->pwr_table_switch_efuse=%d\n",
__func__, pwr->pwr_table_switch_efuse);
if (pwr_table & PWR_BY_RATE) {
if (pwr->pwr_by_rate_switch == PW_BY_RATE_ALL_SAME) {
halrf_set_power_by_rate_all_the_smae_to_struct_8852b(rf, phy);
} else
halrf_set_power_by_rate_to_struct_8852b(rf, phy);
if (pwr->pwr_limit_switch == PWLMT_BY_EFUSE) {
if (pwr->pwr_table_switch_efuse == 0) {
halrf_set_power_by_rate_to_struct_8852b(rf, phy);
} else if (pwr->pwr_table_switch_efuse == 2) {
halrf_set_power_by_rate_all_the_smae_to_struct_8852b(rf, phy);
} else {
halrf_set_power_by_rate_to_struct_8852b(rf, phy);
}
}
halrf_mac_write_pwr_by_rate_reg(rf, phy);
halrf_mac_write_pwr_ofst_mode(rf, phy);
if (rf->dbg_component & DBG_RF_POWER) {
halrf_delay_ms(rf, 100);
for (i = 0; i < TX_PWR_BY_RATE_NUM_MAC; i = i + 4)
halrf_mac_get_pwr_reg_8852b(rf, phy, (0xd2c0 + i), 0xffffffff);
}
}
if (pwr_table & PWR_LIMIT) {
_halrf_set_tx_shape_8852b(rf, phy);
if (!halrf_set_power_limit_to_struct_8852b(rf, phy)) {
RF_DBG(rf, DBG_RF_POWER, "halrf_set_power_limit_to_struct_8852b return fail\n");
return false;
}
halrf_mac_write_pwr_limit_reg(rf, phy);
if (rf->dbg_component & DBG_RF_POWER) {
halrf_delay_ms(rf, 100);
for (i = 0; i < TX_PWR_LIMIT_NUM_MAC; i = i + 4)
halrf_mac_get_pwr_reg_8852b(rf, phy, (0xd2ec + i), 0xffffffff);
}
}
if (pwr_table & PWR_LIMIT_RU) {
_halrf_set_tx_shape_8852b(rf, phy);
if (!halrf_set_power_limit_ru_to_struct_8852b(rf, phy)) {
RF_DBG(rf, DBG_RF_POWER, "halrf_set_power_limit_ru_to_struct_8852b return fail\n");
return false;
}
halrf_mac_write_pwr_limit_rua_reg(rf, phy);
if (rf->dbg_component & DBG_RF_POWER) {
halrf_delay_ms(rf, 100);
for (i = 0; i < 48; i = i + 4)
halrf_mac_get_pwr_reg_8852b(rf, phy, (0xd33c + i), 0xffffffff);
}
}
return true;
}
void halrf_set_ref_power_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i;
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__);
tpu->ofst_int = 0;
tpu->ofst_fraction = 0;
/*Set ref power*/
if (rfe_type > 50)
tpu->base_cw_0db = 0x21;
else
tpu->base_cw_0db = 0x27;
tpu->tssi_16dBm_cw = 0x12c;
/*[Ref Pwr]*/
tpu->ref_pow_ofdm = 0; /*0dBm*/
tpu->ref_pow_cck = 0; /*0dBm*/
halrf_bb_set_tx_pow_ref(rf, phy);
}
bool halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table)
{
#if 0
if (rf->is_coex == true) {
RF_DBG(rf, DBG_RF_POWER, "===>%s rf->is_coex==true return!!!\n", __func__);
return true;
}
#endif
if (!_halrf_set_power_8852b(rf, phy, pwr_table)) {
RF_DBG(rf, DBG_RF_POWER, "_halrf_set_power_8852b return fail\n");
return false;
}
return true;
}
void halrf_pwr_by_rate_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u32 bw = rf->hal_com->band[0].cur_chandef.bw;
u32 band = rf->hal_com->band[0].cur_chandef.band;
u32 reg_tmp, cck_ref, ofdm_ref;
s32 s_cck_ref, s_ofdm_ref;
s32 int_tmp[2], float_tmp[2];
u32 used = *_used;
u32 out_len = *_out_len;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n",
"RF Para Ver", RF_RELEASE_VERSION_8852B);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n",
"RFE type", rf->phl_com->dev_cap.rfe_type);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %d / %s\n",
"Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"),
channel,
bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s\n",
"Driver Swith / Efuse Switch",
(pwr->pwr_limit_switch == PWLMT_DISABLE) ? "Disable Limit" :
(pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) ? "Enable Limit" : "From Efuse",
(pwr->pwr_limit_switch == PWLMT_BY_EFUSE) ?
((pwr->pwr_table_switch_efuse == 0) ? "Disable Limit" : (pwr->pwr_table_switch_efuse == 2) ? "The Same" : "Enable Limit")
: "From Driver");
cck_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0007fc00);
ofdm_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0ff80000);
(cck_ref & BIT(8)) ? (s_cck_ref = cck_ref | 0xfffffe00) : (s_cck_ref = cck_ref);
(ofdm_ref & BIT(8)) ? (s_ofdm_ref = ofdm_ref | 0xfffffe00) : (s_ofdm_ref = ofdm_ref);
int_tmp[0] = s_cck_ref / 4;
float_tmp[0] = s_cck_ref * 100 / 4 % 100;
float_tmp[0] < 0 ? float_tmp[0] = float_tmp[0] * -1 : 0;
int_tmp[1] = s_ofdm_ref / 4;
float_tmp[1] = s_ofdm_ref * 100 / 4 % 100;
float_tmp[1] < 0 ? float_tmp[1] = float_tmp[1] * -1 : 0;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s%d.%ddB / %s%d.%ddB\n",
"CCK REF / OFDM REF",
(int_tmp[0] == 0 && s_cck_ref < 0) ? "-" : "",
int_tmp[0], float_tmp[0],
(int_tmp[1] == 0 && s_ofdm_ref < 0) ? "-" : "",
int_tmp[1], float_tmp[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "1SS\n");
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2c0, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"CCK 11M / 5.5M / 2M / 1M",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2c4, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"OFDM 18M / 12M / 9M / 6M",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2c8, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"OFDM 54M / 48M / 36M / 24M",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s\n",
"HT / VHT / HE");
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2cc, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"MCS3 / MCS2 / MCS1 / MCS0",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2d0, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"MCS7 / MCS6 / MCS5 / MCS4",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2d4, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"MCS11 / MCS10 / MCS9 / MCS8",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2d8, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"DCM MCS4 / MCS3 / MCS1 / MCS0",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "2SS\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s\n",
"HT / VHT / HE");
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2dc, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"MCS3 / MCS2 / MCS1 / MCS0",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2e0, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"MCS7 / MCS6 / MCS5 / MCS4",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2e4, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"MCS11 / MCS10 / MCS9 / MCS8",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2e8, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-36s = %d.%d / %d.%d / %d.%d / %d.%d\n",
"DCM MCS4 / MCS3 / MCS1 / MCS0",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10,
((reg_tmp & 0x7f00) >> 8) / 2, ((reg_tmp & 0x7f00) >> 8) * 10 / 2 % 10,
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10
);
*_used = used;
*_out_len = out_len;
}
void halrf_pwr_limit_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u32 bw = rf->hal_com->band[0].cur_chandef.bw;
u32 band = rf->hal_com->band[0].cur_chandef.band;
u32 reg_tmp, cck_ref, ofdm_ref;
s32 s_cck_ref, s_ofdm_ref;
s32 int_tmp[2], float_tmp[2];
u32 used = *_used;
u32 out_len = *_out_len;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n",
"RF Para Ver", RF_RELEASE_VERSION_8852B);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n",
"RFE type", rf->phl_com->dev_cap.rfe_type);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %d / %s\n",
"Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"),
channel,
bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s / %s\n",
"Regulation 2G / 5G / 6G",
halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_24G),
halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_5G),
halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_6G));
cck_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0007fc00);
ofdm_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0ff80000);
(cck_ref & BIT(8)) ? (s_cck_ref = cck_ref | 0xfffffe00) : (s_cck_ref = cck_ref);
(ofdm_ref & BIT(8)) ? (s_ofdm_ref = ofdm_ref | 0xfffffe00) : (s_ofdm_ref = ofdm_ref);
int_tmp[0] = s_cck_ref / 4;
float_tmp[0] = s_cck_ref * 100 / 4 % 100;
float_tmp[0] < 0 ? float_tmp[0] = float_tmp[0] * -1 : 0;
int_tmp[1] = s_ofdm_ref / 4;
float_tmp[1] = s_ofdm_ref * 100 / 4 % 100;
float_tmp[1] < 0 ? float_tmp[1] = float_tmp[1] * -1 : 0;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s%d.%ddB / %s%d.%ddB\n",
"CCK REF / OFDM REF",
(int_tmp[0] == 0 && s_cck_ref < 0) ? "-" : "",
int_tmp[0], float_tmp[0],
(int_tmp[1] == 0 && s_ofdm_ref < 0) ? "-" : "",
int_tmp[1], float_tmp[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s\n",
"Power Limit (Reg)",
halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd208, BIT(21)) ? "Enable Limit" : "Disable Limit");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s\n",
"Driver Swith / Efuse Switch",
(pwr->pwr_limit_switch == PWLMT_DISABLE) ? "Disable Limit" :
(pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) ? "Enable Limit" : "From Efuse",
(pwr->pwr_limit_switch == PWLMT_BY_EFUSE) ?
((pwr->pwr_table_switch_efuse == 0) ? "Disable Limit" : (pwr->pwr_table_switch_efuse == 2) ? "The Same" : "Enable Limit")
: "From Driver");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d / %d / %d\n",
"TX Shape CCK / 2G / 5G",
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK],
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM],
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "1SS\n");
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2ec, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"CCK 20M NOBF", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"CCK 40M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2,
((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd2f0, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"OFDM NOBF", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"HT 20M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2,
((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd300, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"HT 40M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2,
((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd308, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"HT 80M NOBF", ((reg_tmp & 0x7f0000) >> 16) / 2,
((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "2SS\n");
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd314, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"CCK 20M NOBF",
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"CCK 40M NOBF",
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd318, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"OFDM NOBF",
(reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d / %d.%d\n",
"HT 20M BF / NOBF",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd328, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d / %d.%d\n",
"HT 40M BF / NOBF",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd330, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d / %d.%d\n",
"HT 80M BF / NOBF",
((reg_tmp & 0x7f000000) >> 24) / 2, ((reg_tmp & 0x7f000000) >> 24) * 10 / 2 % 10,
((reg_tmp & 0x7f0000) >> 16) / 2, ((reg_tmp & 0x7f0000) >> 16) * 10 / 2 % 10);
*_used = used;
*_out_len = out_len;
}
void halrf_pwr_limit_ru_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u32 bw = rf->hal_com->band[0].cur_chandef.bw;
u32 band = rf->hal_com->band[0].cur_chandef.band;
u32 reg_tmp, cck_ref, ofdm_ref;
s32 s_cck_ref, s_ofdm_ref;
s32 int_tmp[2], float_tmp[2];
u32 used = *_used;
u32 out_len = *_out_len;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n",
"RF Para Ver", RF_RELEASE_VERSION_8852B);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d\n",
"RFE type", rf->phl_com->dev_cap.rfe_type);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %d / %s\n",
"Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"),
channel,
bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s / %s\n",
"Regulation 2G / 5G / 6G",
halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_24G),
halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_5G),
halrf_get_pw_lmt_regu_type_str(rf, BAND_ON_6G));
cck_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0007fc00);
ofdm_ref = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd200, 0x0ff80000);
(cck_ref & BIT(8)) ? (s_cck_ref = cck_ref | 0xfffffe00) : (s_cck_ref = cck_ref);
(ofdm_ref & BIT(8)) ? (s_ofdm_ref = ofdm_ref | 0xfffffe00) : (s_ofdm_ref = ofdm_ref);
int_tmp[0] = s_cck_ref / 4;
float_tmp[0] = s_cck_ref * 100 / 4 % 100;
float_tmp[0] < 0 ? float_tmp[0] = float_tmp[0] * -1 : 0;
int_tmp[1] = s_ofdm_ref / 4;
float_tmp[1] = s_ofdm_ref * 100 / 4 % 100;
float_tmp[1] < 0 ? float_tmp[1] = float_tmp[1] * -1 : 0;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s%d.%ddB / %s%d.%ddB\n",
"CCK REF / OFDM REF",
(int_tmp[0] == 0 && s_cck_ref < 0) ? "-" : "",
int_tmp[0], float_tmp[0],
(int_tmp[1] == 0 && s_ofdm_ref < 0) ? "-" : "",
int_tmp[1], float_tmp[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s\n",
"Power Limit (Reg)",
halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd208, BIT(20)) ? "Enable Limit" : "Disable Limit");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %s / %s\n",
"Driver Swith / Efuse Switch",
(pwr->pwr_limit_switch == PWLMT_DISABLE) ? "Disable Limit" :
(pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT) ? "Enable Limit" : "From Efuse",
(pwr->pwr_limit_switch == PWLMT_BY_EFUSE) ?
((pwr->pwr_table_switch_efuse == 0) ? "Disable Limit" : (pwr->pwr_table_switch_efuse == 2) ? "The Same" : "Enable Limit")
: "From Driver");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d / %d / %d\n",
"TX Shape CCK / 2G / 5G",
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK],
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM],
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM]);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd33c, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"RU26", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd344, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"RU52", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
reg_tmp = halrf_mac_get_pwr_reg_8852b(rf, 0, 0xd34c, 0xffffffff);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-30s = %d.%d\n",
"RU106", (reg_tmp & 0x7f) / 2, (reg_tmp & 0x7f) * 10 / 2 % 10);
*_used = used;
*_out_len = out_len;
}
void halrf_set_tx_shape_8852b(struct rf_info *rf, u8 tx_shape_idx)
{
struct rtw_tpu_info *tpu = &rf->hal_com->band[0].rtw_tpu_i;
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 ch = rf->hal_com->band[0].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s ch=%d tx_shape_idx=%d\n",
__func__, ch, tx_shape_idx);
tpu->tx_ptrn_shap_idx = tx_shape_idx;
if (tx_shape_idx == 255) {
pwr->set_tx_ptrn_shap_en = false;
_halrf_set_tx_shape_8852b(rf, 0);
return;
} else
pwr->set_tx_ptrn_shap_en = true;
if (ch <= 14) {
halrf_bb_set_pow_patten_sharp(rf, ch, true, tx_shape_idx, 0); /*cck*/
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_CCK] = tx_shape_idx;
}
halrf_bb_set_pow_patten_sharp(rf, ch, false, tx_shape_idx, 0); /*ofdm*/
if (ch >= 1 && ch <= 14)
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_2_4G][TX_SHAPE_OFDM] = tx_shape_idx;
else
pwr->set_tx_ptrn_shap_idx[PW_LMT_BAND_5G][TX_SHAPE_OFDM] = tx_shape_idx;
}
#endif /*RF_8852B_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.c
|
C
|
agpl-3.0
| 69,541
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_SET_PWR_TABLE_8852B_H_
#define _HALRF_SET_PWR_TABLE_8852B_H_
#ifdef RF_8852B_SUPPORT
/*@--------------------------Define Parameters-------------------------------*/
#define MAX_TX_PATH 2
#define TPU_SIZE_RUA 3 /*{26, 52, 106}*/
#define TPU_SIZE_BW20_SC 8 /*8 * 20M = 160M*/
/*@-----------------------End Define Parameters-----------------------*/
bool halrf_set_power_by_rate_to_mac_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
bool halrf_set_power_limit_to_mac_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
void halrf_set_ref_power_to_struct_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
bool halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table);
void halrf_pwr_by_rate_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_pwr_limit_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_pwr_limit_ru_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_set_tx_shape_8852b(struct rf_info *rf, u8 tx_shape_idx);
#endif /*RF_8852B_SUPPORT*/
#endif /*_HALRF_SET_PWR_TABLE_8852B_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_set_pwr_table_8852b.h
|
C
|
agpl-3.0
| 1,873
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
void _tssi_backup_bb_registers_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
u32 *reg,
u32 *reg_backup,
u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++) {
reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n",
reg[i], reg_backup[i]);
}
}
void _tssi_reload_bb_registers_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
u32 *reg,
u32 *reg_backup,
u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++) {
halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n",
reg[i], reg_backup[i]);
}
}
u8 _halrf_ch_to_idx(struct rf_info *rf, u8 channel)
{
u8 channelIndex;
if (channel >= 1 && channel <= 14)
channelIndex = channel - 1;
else if (channel >= 36 && channel <= 64)
channelIndex = (channel - 36) / 2 + 14;
else if (channel >= 100 && channel <= 144)
channelIndex = ((channel - 100) / 2) + 15 + 14;
else if (channel >= 149 && channel <= 177)
channelIndex = ((channel - 149) / 2) + 38 + 14;
else
channelIndex = 0;
return channelIndex;
}
u8 _halrf_idx_to_ch(struct rf_info *rf, u8 idx)
{
u8 channelIndex;
if (idx >= 0 && idx <= 13)
channelIndex = idx + 1;
else if (idx >= (0 + 14) && idx <= (14 + 14))
channelIndex = (idx - 14) * 2 + 36;
else if (idx >= (15 + 14) && idx <= (37 + 14))
channelIndex = (idx - 15 - 14) * 2 + 100;
else if (idx >= (38 + 14) && idx <= (52 + 14))
channelIndex = (idx - 38 - 14) * 2 + 149;
else
channelIndex = 0;
return channelIndex;
}
void _halrf_tssi_hw_tx_8852b(struct rf_info *rf,
enum phl_phy_idx phy, u8 path, u16 cnt, u16 period, s16 dbm, u32 rate, u8 bw,
bool enable)
{
struct rf_pmac_tx_info tx_info = {0};
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
tx_info.ppdu = rate;
tx_info.mcs = 7;
tx_info.bw = bw;
tx_info.nss = 1;
tx_info.gi = 1;
tx_info.txagc_cw = 0;
tx_info.dbm = dbm;
tx_info.cnt = cnt;
tx_info.time = 20;
tx_info.period = period;
tx_info.length = 0;
halrf_set_pmac_tx(rf, phy, path, &tx_info, enable, false);
}
void _halrf_tssi_rf_setting_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
if (channel >= 1 && channel <= 14)
halrf_wrf(rf, path, 0x7f, 0x00002, 0x1);
else
halrf_wrf(rf, path, 0x7f, 0x00100, 0x1);
}
void _halrf_tssi_set_sys_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
halrf_wreg(rf, 0x12a8, 0x0000000f, 0x5);
halrf_wreg(rf, 0x32a8, 0x0000000f, 0x5);
halrf_wreg(rf, 0x12bc, 0x000ffff0, 0x5555);
halrf_wreg(rf, 0x32bc, 0x000ffff0, 0x5555);
halrf_wreg(rf, 0x0300, 0xff000000, 0x16);
halrf_wreg(rf, 0x0304, 0x000000ff, 0x19);
halrf_wreg(rf, 0x0314, 0xffff0000, 0x2041);
halrf_wreg(rf, 0x0318, 0xffffffff, 0x2041);
halrf_wreg(rf, 0x0318, 0xffffffff, 0x20012041);
halrf_wreg(rf, 0x0020, 0x00006000, 0x3);
halrf_wreg(rf, 0x0024, 0x00006000, 0x3);
halrf_wreg(rf, 0x0704, 0xffff0000, 0x601e);
halrf_wreg(rf, 0x2704, 0xffff0000, 0x601e);
halrf_wreg(rf, 0x0700, 0xf0000000, 0x4);
halrf_wreg(rf, 0x2700, 0xf0000000, 0x4);
halrf_wreg(rf, 0x0650, 0x3c000000, 0x0);
halrf_wreg(rf, 0x2650, 0x3c000000, 0x0);
if (path == RF_PATH_A) {
if (channel >= 1 && channel <= 14) {
halrf_wreg(rf, 0x120c, 0x000000ff, 0x33);
halrf_wreg(rf, 0x12c0, 0x0ff00000, 0x33);
halrf_wreg(rf, 0x58f8, 0x40000000, 0x1);
halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1e);
} else {
halrf_wreg(rf, 0x120c, 0x000000ff, 0x44);
halrf_wreg(rf, 0x12c0, 0x0ff00000, 0x44);
halrf_wreg(rf, 0x58f8, 0x40000000, 0x0);
halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1d);
}
} else {
if (channel >= 1 && channel <= 14) {
halrf_wreg(rf, 0x32c0, 0x0ff00000, 0x33);
halrf_wreg(rf, 0x320c, 0x000000ff, 0x33);
halrf_wreg(rf, 0x78f8, 0x40000000, 0x1);
halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1e);
} else {
halrf_wreg(rf, 0x32c0, 0x0ff00000, 0x44);
halrf_wreg(rf, 0x320c, 0x000000ff, 0x44);
halrf_wreg(rf, 0x78f8, 0x40000000, 0x0);
halrf_wreg(rf, 0x0304, 0x0000ff00, 0x1d);
}
}
}
void _halrf_tssi_ini_txpwr_ctrl_bb_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x566c, 0x00001000, 0x0);
halrf_wreg(rf, 0x5800, 0xffffffff, 0x003f807f);
#if 0
halrf_wreg(rf, 0x5804, 0x000001ff, 0x040);
halrf_wreg(rf, 0x5804, 0xfffc0000, 0x012c);
halrf_wreg(rf, 0x5808, 0x000001ff, 0x040);
halrf_wreg(rf, 0x5808, 0x07fc0000, 0x12c);
#endif
halrf_wreg(rf, 0x580c, 0x0000007f, 0x40);
halrf_wreg(rf, 0x580c, 0x0fffff00, 0x00040);
halrf_wreg(rf, 0x5810, 0xffffffff, 0x59010000);
halrf_wreg(rf, 0x5814, 0x01ffffff, 0x002d000);
halrf_wreg(rf, 0x5814, 0xf8000000, 0x00);
halrf_wreg(rf, 0x5818, 0xffffffff, 0x002c1800);
halrf_wreg(rf, 0x581c, 0x3fffffff, 0x1dc80280);
halrf_wreg(rf, 0x5820, 0xffffffff, 0x00002080);
halrf_wreg(rf, 0x580c, 0x10000000, 0x1);
halrf_wreg(rf, 0x580c, 0x40000000, 0x1);
halrf_wreg(rf, 0x5834, 0x3fffffff, 0x000115f2);
halrf_wreg(rf, 0x5838, 0x7fffffff, 0x0000121);
halrf_wreg(rf, 0x5854, 0x3fffffff, 0x000115f2);
halrf_wreg(rf, 0x5858, 0x7fffffff, 0x0000121);
halrf_wreg(rf, 0x5860, 0x80000000, 0x0);
halrf_wreg(rf, 0x5864, 0x07ffffff, 0x00801ff);
halrf_wreg(rf, 0x5898, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x589c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x58a4, 0x000000ff, 0x16);
halrf_wreg(rf, 0x58b0, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x58b4, 0x7fffffff, 0x0a002000);
halrf_wreg(rf, 0x58b8, 0x7fffffff, 0x00007628);
/*GNT_WL==0 & 0x58bc[18]==1, Bypass TSSI*/
/*GNT_BT==1 & 0x58bc[20]==1, Bypass TSSI*/
/*GNT_BT_TX==1 & 0x58bc[22]==1, Bypass TSSI*/
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP)
halrf_wreg(rf, 0x58bc, 0x07ffffff, 0x7f7807f);
else
halrf_wreg(rf, 0x58bc, 0x07ffffff, 0x7a7807f);
halrf_wreg(rf, 0x58c0, 0xfffe0000, 0x003f);
halrf_wreg(rf, 0x58c4, 0xffffffff, 0x0003ffff);
halrf_wreg(rf, 0x58c8, 0x00ffffff, 0x000000);
halrf_wreg(rf, 0x58c8, 0xf0000000, 0x0);
halrf_wreg(rf, 0x58cc, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x58d0, 0x07ffffff, 0x2008101);
halrf_wreg(rf, 0x58d4, 0x000000ff, 0x00);
halrf_wreg(rf, 0x58d4, 0x0003fe00, 0x0ff);
halrf_wreg(rf, 0x58d4, 0x07fc0000, 0x100);
halrf_wreg(rf, 0x58d8, 0xffffffff, 0x8008016c);
halrf_wreg(rf, 0x58dc, 0x0001ffff, 0x0807f);
halrf_wreg(rf, 0x58dc, 0xfff00000, 0x800);
halrf_wreg(rf, 0x58f0, 0x0003ffff, 0x001ff);
halrf_wreg(rf, 0x58f4, 0x000fffff, 0x000);
} else {
halrf_wreg(rf, 0x566c, 0x00001000, 0x0);
halrf_wreg(rf, 0x7800, 0xffffffff, 0x003f807f);
#if 0
halrf_wreg(rf, 0x7804, 0x000001ff, 0x040);
halrf_wreg(rf, 0x7804, 0xfffc0000, 0x012c);
halrf_wreg(rf, 0x7808, 0x000001ff, 0x040);
halrf_wreg(rf, 0x7808, 0x07fc0000, 0x12c);
#endif
halrf_wreg(rf, 0x780c, 0x0000007f, 0x40);
halrf_wreg(rf, 0x780c, 0x0fffff00, 0x00040);
halrf_wreg(rf, 0x7810, 0xffffffff, 0x59010000);
halrf_wreg(rf, 0x7814, 0x01ffffff, 0x002d000);
halrf_wreg(rf, 0x7814, 0xf8000000, 0x00);
halrf_wreg(rf, 0x7818, 0xffffffff, 0x002c1800);
halrf_wreg(rf, 0x781c, 0x3fffffff, 0x1dc80280);
halrf_wreg(rf, 0x7820, 0xffffffff, 0x00002080);
halrf_wreg(rf, 0x780c, 0x10000000, 0x1);
halrf_wreg(rf, 0x780c, 0x40000000, 0x1);
halrf_wreg(rf, 0x7834, 0x3fffffff, 0x000115f2);
halrf_wreg(rf, 0x7838, 0x7fffffff, 0x0000121);
halrf_wreg(rf, 0x7854, 0x3fffffff, 0x000115f2);
halrf_wreg(rf, 0x7858, 0x7fffffff, 0x0000121);
halrf_wreg(rf, 0x7860, 0x80000000, 0x0);
halrf_wreg(rf, 0x7864, 0x07ffffff, 0x00801ff);
halrf_wreg(rf, 0x7898, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x789c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x78a4, 0x000000ff, 0x16);
halrf_wreg(rf, 0x78b0, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x78b4, 0x7fffffff, 0x0a002000);
halrf_wreg(rf, 0x78b8, 0x7fffffff, 0x00007628);
/*GNT_WL==0 & 0x78bc[18]==1, Bypass TSSI*/
/*GNT_BT==1 & 0x78bc[20]==1, Bypass TSSI*/
/*GNT_BT_TX==1 & 0x78bc[22]==1, Bypass TSSI*/
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP)
halrf_wreg(rf, 0x78bc, 0x07ffffff, 0x7f7807f);
else
halrf_wreg(rf, 0x78bc, 0x07ffffff, 0x7a7807f);
halrf_wreg(rf, 0x78c0, 0xfffe0000, 0x003f);
halrf_wreg(rf, 0x78c4, 0xffffffff, 0x0003ffff);
halrf_wreg(rf, 0x78c8, 0x00ffffff, 0x000000);
halrf_wreg(rf, 0x78c8, 0xf0000000, 0x0);
halrf_wreg(rf, 0x78cc, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x78d0, 0x07ffffff, 0x2008101);
halrf_wreg(rf, 0x78d4, 0x000000ff, 0x00);
halrf_wreg(rf, 0x78d4, 0x0003fe00, 0x0ff);
halrf_wreg(rf, 0x78d4, 0x07fc0000, 0x100);
halrf_wreg(rf, 0x78d8, 0xffffffff, 0x8008016c);
halrf_wreg(rf, 0x78dc, 0x0001ffff, 0x0807f);
halrf_wreg(rf, 0x78dc, 0xfff00000, 0x800);
halrf_wreg(rf, 0x78f0, 0x0003ffff, 0x001ff);
halrf_wreg(rf, 0x78f4, 0x000fffff, 0x000);
}
}
void _halrf_tssi_ini_txpwr_ctrl_bb_he_tb_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x58a0, MASKDWORD, 0x000000fe);
halrf_wreg(rf, 0x58e4, 0x0000007f, 0x1f);
} else {
halrf_wreg(rf, 0x78a0, MASKDWORD, 0x000000fe);
halrf_wreg(rf, 0x78e4, 0x0000007f, 0x1f);
}
}
void _halrf_tssi_set_dck_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x580c, 0x0fff0000, 0x000);
halrf_wreg(rf, 0x5814, 0x003ff000, 0x0ef);
halrf_wreg(rf, 0x5814, 0x18000000, 0x0);
} else {
halrf_wreg(rf, 0x780c, 0x0fff0000, 0x000);
halrf_wreg(rf, 0x7814, 0x003ff000, 0x0ef);
halrf_wreg(rf, 0x7814, 0x18000000, 0x0);
}
}
void _halrf_tssi_set_bbgain_split_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5818, 0x08000000, 0x1);
halrf_wreg(rf, 0x58d4, 0xf0000000, 0x7);
halrf_wreg(rf, 0x58f0, 0x000c0000, 0x1);
halrf_wreg(rf, 0x58f0, 0xfff00000, 0x400);
} else {
halrf_wreg(rf, 0x7818, 0x08000000, 0x1);
halrf_wreg(rf, 0x78d4, 0xf0000000, 0x7);
halrf_wreg(rf, 0x78f0, 0x000c0000, 0x1);
halrf_wreg(rf, 0x78f0, 0xfff00000, 0x400);
}
}
void _halrf_tssi_set_tmeter_tbl_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_pwr_track_info *pwr_trk = &rf->pwr_track;
struct halrf_tssi_info *tssi_info = &rf->tssi;
struct rtw_hal_com_t *hal = rf->hal_com;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u8 i, thermal = 0xff, j;
//u8 rate = phydm_get_tx_rate(dm);
u32 thermal_offset_tmp = 0;
s8 thermal_offset[64] = {0};
s8 thermal_up_a[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_a[DELTA_SWINGIDX_SIZE] = {0};
s8 thermal_up_b[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_b[DELTA_SWINGIDX_SIZE] = {0};
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (tssi_info->tssi_type == TSSI_CAL) {
halrf_wreg(rf, 0x5810, 0x00010000, 0x0);
halrf_wreg(rf, 0x5810, 0x01000000, 0x1);
halrf_wreg(rf, 0x7810, 0x00010000, 0x0);
halrf_wreg(rf, 0x7810, 0x01000000, 0x1);
halrf_wreg(rf, 0x5810, 0x0000fc00, 32);
halrf_wreg(rf, 0x5864, 0x03f00000, 32);
halrf_wreg(rf, 0x7810, 0x0000fc00, 32);
halrf_wreg(rf, 0x7864, 0x03f00000, 32);
for (i = 0; i < 64; i = i + 4) {
thermal_offset_tmp = (thermal_offset[i] & 0xff) |
(thermal_offset[i + 1] & 0xff) << 8 |
(thermal_offset[i + 2] & 0xff) << 16 |
(thermal_offset[i + 3] & 0xff) << 24;
halrf_wreg(rf, (0x5c00 + i), MASKDWORD, thermal_offset_tmp);
halrf_wreg(rf, (0x7c00 + i), MASKDWORD, thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(0x5c00 + i), thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(0x7c00 + i), thermal_offset_tmp);
}
halrf_wreg(rf, 0x5864, BIT(26), 0x1);
halrf_wreg(rf, 0x5864, BIT(26), 0x0);
halrf_wreg(rf, 0x7864, BIT(26), 0x1);
halrf_wreg(rf, 0x7864, BIT(26), 0x0);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s TSSI Calibration Mode return !!!\n", __func__);
return;
}
if (channel >= 1 && channel <= 14) {
hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_2ga_p, sizeof(thermal_up_a));
hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_2ga_n, sizeof(thermal_down_a));
hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_2gb_p, sizeof(thermal_up_b));
hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_2gb_n, sizeof(thermal_down_b));
} else if (channel >= 36 && channel <= 64) {
hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_5ga_p[0], sizeof(thermal_up_a));
hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_5ga_n[0], sizeof(thermal_down_a));
hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_5gb_p[0], sizeof(thermal_up_b));
hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_5gb_n[0], sizeof(thermal_down_b));
} else if (channel >= 100 && channel <= 144) {
hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_5ga_p[1], sizeof(thermal_up_a));
hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_5ga_n[1], sizeof(thermal_down_a));
hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_5gb_p[1], sizeof(thermal_up_b));
hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_5gb_n[1], sizeof(thermal_down_b));
} else if (channel >= 149 && channel <= 177) {
hal_mem_cpy(hal, thermal_up_a, pwr_trk->delta_swing_table_idx_5ga_p[2], sizeof(thermal_up_a));
hal_mem_cpy(hal, thermal_down_a, pwr_trk->delta_swing_table_idx_5ga_n[2], sizeof(thermal_down_a));
hal_mem_cpy(hal, thermal_up_b, pwr_trk->delta_swing_table_idx_5gb_p[2], sizeof(thermal_up_b));
hal_mem_cpy(hal, thermal_down_b, pwr_trk->delta_swing_table_idx_5gb_n[2], sizeof(thermal_down_b));
}
/*path s0*/
if (path == RF_PATH_A) {
hal_mem_set(hal, thermal_offset, 0, sizeof(thermal_offset));
halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal, 1);
/*thermal = 32;*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] channel=%d thermal_pahtA=0x%x tssi_info->tssi_type=%d\n",
channel, thermal, tssi_info->tssi_type);
halrf_wreg(rf, 0x5810, 0x00010000, 0x0);
halrf_wreg(rf, 0x5810, 0x01000000, 0x1);
if (thermal == 0xff) {
halrf_wreg(rf, 0x5810, 0x0000fc00, 32);
halrf_wreg(rf, 0x5864, 0x03f00000, 32);
for (i = 0; i < 64; i = i + 4) {
thermal_offset_tmp = (thermal_offset[i] & 0xff) |
(thermal_offset[i + 1] & 0xff) << 8 |
(thermal_offset[i + 2] & 0xff) << 16 |
(thermal_offset[i + 3] & 0xff) << 24;
halrf_wreg(rf, (0x5c00 + i), MASKDWORD, thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(0x5c00 + i), thermal_offset_tmp);
}
}
tssi_info->thermal[RF_PATH_A] = thermal;
if (thermal != 0xff) {
halrf_wreg(rf, 0x5810, 0x0000fc00, (thermal & 0x3f));
halrf_wreg(rf, 0x5864, 0x03f00000, (thermal & 0x3f));
i = 0;
for (j = 0; j < 32; j++) {
if (i < DELTA_SWINGIDX_SIZE)
thermal_offset[j] = -1 * thermal_down_a[i++];
else
thermal_offset[j] = -1 * thermal_down_a[DELTA_SWINGIDX_SIZE - 1];
}
i = 1;
for (j = 63; j >= 32; j--) {
if (i < DELTA_SWINGIDX_SIZE)
thermal_offset[j] = thermal_up_a[i++];
else
thermal_offset[j] = thermal_up_a[DELTA_SWINGIDX_SIZE - 1];
}
for (i = 0; i < 64; i = i + 4) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\n",
i, thermal_offset[i + 3] & 0xff, thermal_offset[i + 2] & 0xff,
thermal_offset[i + 1] & 0xff, thermal_offset[i] & 0xff);
}
for (i = 0; i < 64; i = i + 4) {
thermal_offset_tmp = (thermal_offset[i] & 0xff) |
(thermal_offset[i + 1] & 0xff) << 8 |
(thermal_offset[i + 2] & 0xff) << 16 |
(thermal_offset[i + 3] & 0xff) << 24;
halrf_wreg(rf, (0x5c00 + i), MASKDWORD, thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(0x5c00 + i), thermal_offset_tmp);
}
}
halrf_wreg(rf, 0x5864, BIT(26), 0x1);
halrf_wreg(rf, 0x5864, BIT(26), 0x0);
} else {
/*path s1*/
hal_mem_set(hal, thermal_offset, 0, sizeof(thermal_offset));
halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal, 1);
/*thermal = 32;*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] channel=%d thermal_pahtB=0x%x tssi_info->tssi_type=%d\n",
channel, thermal, tssi_info->tssi_type);
halrf_wreg(rf, 0x7810, 0x00010000, 0x0);
halrf_wreg(rf, 0x7810, 0x01000000, 0x1);
if (thermal == 0xff) {
halrf_wreg(rf, 0x7810, 0x0000fc00, 32);
halrf_wreg(rf, 0x7864, 0x03f00000, 32);
for (i = 0; i < 64; i = i + 4) {
thermal_offset_tmp = (thermal_offset[i] & 0xff) |
(thermal_offset[i + 1] & 0xff) << 8 |
(thermal_offset[i + 2] & 0xff) << 16 |
(thermal_offset[i + 3] & 0xff) << 24;
halrf_wreg(rf, (0x7c00 + i), MASKDWORD, thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(0x7c00 + i), thermal_offset_tmp);
}
}
tssi_info->thermal[RF_PATH_B] = thermal;
if (thermal != 0xff) {
halrf_wreg(rf, 0x7810, 0x0000fc00, (thermal & 0x3f));
halrf_wreg(rf, 0x7864, 0x03f00000, (thermal & 0x3f));
i = 0;
for (j = 0; j < 32; j++) {
if (i < DELTA_SWINGIDX_SIZE)
thermal_offset[j] = -1 * thermal_down_b[i++];
else
thermal_offset[j] = -1 * thermal_down_b[DELTA_SWINGIDX_SIZE - 1];
}
i = 1;
for (j = 63; j >= 32; j--) {
if (i < DELTA_SWINGIDX_SIZE)
thermal_offset[j] = thermal_up_b[i++];
else
thermal_offset[j] = thermal_up_b[DELTA_SWINGIDX_SIZE - 1];
}
for (i = 0; i < 64; i = i + 4) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\n",
i, thermal_offset[i + 3] & 0xff, thermal_offset[i + 2] & 0xff,
thermal_offset[i + 1] & 0xff, thermal_offset[i] & 0xff);
}
for (i = 0; i < 64; i = i + 4) {
thermal_offset_tmp = (thermal_offset[i] & 0xff) |
(thermal_offset[i + 1] & 0xff) << 8 |
(thermal_offset[i + 2] & 0xff) << 16 |
(thermal_offset[i + 3] & 0xff) << 24;
halrf_wreg(rf, (0x7c00 + i), MASKDWORD, thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(0x7c00 + i), thermal_offset_tmp);
}
}
halrf_wreg(rf, 0x7864, BIT(26), 0x1);
halrf_wreg(rf, 0x7864, BIT(26), 0x0);
}
}
void _halrf_tssi_set_tmeter_tbl_zere_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
u8 i;
u32 thermal_offset_tmp = 0;
u32 ftable_reg[TSSI_PATH_MAX_8852B] = {0x5c00, 0x7c00};
u32 ftable_base_reg[TSSI_PATH_MAX_8852B] = {0x5810, 0x7810};
u32 ftable_trigger_reg[TSSI_PATH_MAX_8852B] = {0x5864, 0x7864};
s8 thermal_offset[64] = {0};
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
halrf_wreg(rf, ftable_base_reg[path], 0x00010000, 0x0);
halrf_wreg(rf, ftable_base_reg[path], 0x01000000, 0x1);
halrf_wreg(rf, ftable_base_reg[path], 0x0000fc00, 32);
halrf_wreg(rf, ftable_trigger_reg[path], 0x03f00000, 32);
for (i = 0; i < 64; i = i + 4) {
thermal_offset_tmp = (thermal_offset[i] & 0xff) |
(thermal_offset[i + 1] & 0xff) << 8 |
(thermal_offset[i + 2] & 0xff) << 16 |
(thermal_offset[i + 3] & 0xff) << 24;
halrf_wreg(rf, (ftable_reg[path] + i), MASKDWORD, thermal_offset_tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] write addr:0x%x value=0x%08x\n",
(ftable_reg[path] + i), thermal_offset_tmp);
}
halrf_wreg(rf, ftable_trigger_reg[path], BIT(26), 0x1);
halrf_wreg(rf, ftable_trigger_reg[path], BIT(26), 0x0);
}
void _halrf_tssi_set_dac_gain_tbl_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x58b0, 0x00000400, 0x1);
halrf_wreg(rf, 0x58b0, 0x00000fff, 0x000);
halrf_wreg(rf, 0x58b0, 0x00000800, 0x1);
halrf_wreg(rf, 0x5a00, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a04, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a08, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a0c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a10, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a14, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a18, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a1c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a20, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a24, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a28, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a2c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a30, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a34, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a38, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a3c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a40, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a44, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a48, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a4c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a50, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a54, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a58, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a5c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a60, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a64, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a68, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a6c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a70, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a74, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a78, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a7c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a80, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a84, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a88, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a8c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a90, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a94, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a98, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5a9c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5aa0, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5aa4, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5aa8, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5aac, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5ab0, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5ab4, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5ab8, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5abc, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x5ac0, MASKDWORD, 0x00000000);
} else {
halrf_wreg(rf, 0x78b0, 0x00000fff, 0x000);
halrf_wreg(rf, 0x78b0, 0x00000800, 0x1);
halrf_wreg(rf, 0x7a00, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a04, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a08, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a0c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a10, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a14, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a18, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a1c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a20, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a24, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a28, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a2c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a30, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a34, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a38, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a3c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a40, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a44, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a48, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a4c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a50, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a54, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a58, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a5c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a60, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a64, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a68, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a6c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a70, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a74, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a78, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a7c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a80, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a84, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a88, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a8c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a90, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a94, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a98, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7a9c, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7aa0, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7aa4, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7aa8, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7aac, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7ab0, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7ab4, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7ab8, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7abc, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x7ac0, MASKDWORD, 0x00000000);
}
}
void _halrf_tssi_slope_cal_org_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5608, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x560c, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x5610, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x5614, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x5618, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x561c, 0x000001ff, 0x008);
halrf_wreg(rf, 0x561c, 0xffff0000, 0x0808);
halrf_wreg(rf, 0x5620, 0xffffffff, 0x08080808);
halrf_wreg(rf, 0x5624, 0xffffffff, 0x08080808);
halrf_wreg(rf, 0x5628, 0xffffffff, 0x08080808);
halrf_wreg(rf, 0x562c, 0x0000ffff, 0x0808);
halrf_wreg(rf, 0x581c, 0x00100000, 0x0);
} else {
halrf_wreg(rf, 0x7608, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x760c, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x7610, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x7614, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x7618, 0x07ffffff, 0x0201008);
halrf_wreg(rf, 0x761c, 0x000001ff, 0x008);
halrf_wreg(rf, 0x761c, 0xffff0000, 0x0808);
halrf_wreg(rf, 0x7620, 0xffffffff, 0x08080808);
halrf_wreg(rf, 0x7624, 0xffffffff, 0x08080808);
halrf_wreg(rf, 0x7628, 0xffffffff, 0x08080808);
halrf_wreg(rf, 0x762c, 0x0000ffff, 0x0808);
halrf_wreg(rf, 0x781c, 0x00100000, 0x0);
}
}
void _halrf_tssi_slope_cal_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
s16 power_2g_high[4] = {80, 24, 0, -24};
s16 power_2g_low[4] = {56, 8, -16, -36};
s16 power_5g_high[4] = {80, 24, 0, -36};
s16 power_5g_low[4] = {56, 8, -16, -44};
s16 power_high[4] = {0}, power_low[4] = {0};
u32 tssi_cw_rpt_high = 0, tssi_cw_rpt_low = 0,
tssi_cw_rpt_offset[4] = {0};
u32 tssi_trigger[TSSI_PATH_MAX_8852B] = {0x5820, 0x7820};
u32 tssi_cw_rpt_addr[TSSI_PATH_MAX_8852B] = {0x1c18, 0x3c18};
u8 i, j, k;
u32 rate = T_HT_MF;
u8 bw = 0;
u8 phy_map;
phy_map = (BIT(phy) << 4) | BIT(path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n",
__func__, channel, path);
if (channel >= 1 && channel <= 14) {
for (i = 0; i < 4; i++) {
power_high[i] = power_2g_high[i];
power_low[i] = power_2g_low[i];
}
} else {
for (i = 0; i < 4; i++) {
power_high[i] = power_5g_high[i];
power_low[i] = power_5g_low[i];
}
}
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_TSSI, RFK_ONESHOT_START);
for (j = 0; j < 4; j++) {
/*high power*/
halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x0);
halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x1);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, true);
for (k = 0; halrf_rreg(rf, tssi_cw_rpt_addr[path], BIT(16)) == 0; k++) {
halrf_delay_us(rf, 1);
if (k > 100) {
//halrf_set_pseudo_cw(rf, i, power_high[j], false);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] TSSI finish bit k > 100us path=%d\n",
i);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false);
return;
}
}
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false);
tssi_cw_rpt_high = halrf_rreg(rf, tssi_cw_rpt_addr[path], 0x000001ff);
/*low power*/
halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x0);
halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x1);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_low[j], rate, bw, true);
for (k = 0; halrf_rreg(rf, tssi_cw_rpt_addr[path], BIT(16)) == 0; k++) {
halrf_delay_us(rf, 1);
if (k > 100) {
//halrf_set_pseudo_cw(rf, i, power_low[j], false);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] TSSI finish bit k > 100us path=%d\n",
i);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false);
return;
}
}
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power_high[j], rate, bw, false);
tssi_cw_rpt_low = halrf_rreg(rf, tssi_cw_rpt_addr[path], 0x000001ff);
tssi_cw_rpt_offset[j] = tssi_cw_rpt_high - tssi_cw_rpt_low;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] power_high[%d]=%d power_low[%d]=%d\n",
j, power_high[j], j, power_low[j]);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_cw_rpt_offset[%d](0x%x) = tssi_cw_rpt_high(0x%x) - tssi_cw_rpt_low(0x%x)\n",
j, tssi_cw_rpt_offset[j], tssi_cw_rpt_high, tssi_cw_rpt_low);
//halrf_set_pseudo_cw(rf, i, power_low[j], false);
}
halrf_wreg(rf, 0x581c, 0x00100000, 0x1);
halrf_wreg(rf, 0x58cc, 0x00001000, 0x1);
halrf_wreg(rf, 0x58cc, 0x00000007, 0x7);
halrf_wreg(rf, 0x58cc, 0x00000038, 0x6);
halrf_wreg(rf, 0x58cc, 0x000001c0, 0x3);
halrf_wreg(rf, 0x58cc, 0x00000e00, 0x1);
halrf_wreg(rf, 0x5828, 0x7fc00000, tssi_cw_rpt_offset[0]);
halrf_wreg(rf, 0x5898, 0x000000ff, power_high[0] - power_low[0]);
halrf_wreg(rf, 0x5830, 0x7fc00000, tssi_cw_rpt_offset[0]);
halrf_wreg(rf, 0x5898, 0x0000ff00, power_high[0] - power_low[0]);
halrf_wreg(rf, 0x5838, 0x7fc00000, tssi_cw_rpt_offset[1]);
halrf_wreg(rf, 0x5898, 0x00ff0000, power_high[1] - power_low[1]);
halrf_wreg(rf, 0x5840, 0x7fc00000, tssi_cw_rpt_offset[1]);
halrf_wreg(rf, 0x5898, 0xff000000, power_high[1] - power_low[1]);
halrf_wreg(rf, 0x5848, 0x7fc00000, tssi_cw_rpt_offset[2]);
halrf_wreg(rf, 0x589c, 0x000000ff, power_high[2] - power_low[2]);
halrf_wreg(rf, 0x5850, 0x7fc00000, tssi_cw_rpt_offset[2]);
halrf_wreg(rf, 0x589c, 0x0000ff00, power_high[2] - power_low[2]);
halrf_wreg(rf, 0x5858, 0x7fc00000, tssi_cw_rpt_offset[3]);
halrf_wreg(rf, 0x589c, 0x00ff0000, power_high[3] - power_low[3]);
halrf_wreg(rf, 0x5860, 0x7fc00000, tssi_cw_rpt_offset[3]);
halrf_wreg(rf, 0x589c, 0xff000000, power_high[3] - power_low[3]);
halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_TSSI, RFK_ONESHOT_STOP);
}
void _halrf_tssi_set_rf_gap_tbl_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
}
}
void _halrf_tssi_alignment_default_8852ba(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n",
__func__, channel, path);
if (path == RF_PATH_A) {
if (channel >= 1 && channel <= 14) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x01cfb3d6);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000074);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x01cfb3d6);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000074);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else if (channel >= 36 && channel <= 64) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x01e053ee);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x0000007b);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else if (channel >= 100 && channel <= 144) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x02807ff9);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000078);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else if (channel >= 149 && channel <= 177) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x025067f1);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
}
} else {
if (channel >= 1 && channel <= 14) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x018fa3d2);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000079);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x018fa3d2);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000079);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else if (channel >= 36 && channel <= 64) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x01a047eb);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000079);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else if (channel >= 100 && channel <= 144) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x02506ff7);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000076);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else if (channel >= 149 && channel <= 177) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x01a04bf0);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000076);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
}
}
}
void _halrf_tssi_alignment_default_8852bb(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path, bool all)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n",
__func__, channel, path);
if (path == RF_PATH_A) {
if (channel >= 1 && channel <= 14) {
if (all == true) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00ef77c3);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x0000007b);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x01cfb3d6);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000074);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00ef77c3);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x0000007b);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x01cfb3d6);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000074);
}
} else if (channel >= 36 && channel <= 64) {
if (all == true) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x009003da);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x009003da);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
}
} else if (channel >= 100 && channel <= 144) {
if (all == true) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
}
} else if (channel >= 149 && channel <= 177) {
if (all == true) {
halrf_wreg(rf, 0x5604, 0x80000000, 0x1);
halrf_wreg(rf, 0x5600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x5604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x5638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x5630, 0x3fffffff, 0x00f013e1);
halrf_wreg(rf, 0x5634, 0x3fffffff, 0x00000075);
halrf_wreg(rf, 0x563c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x5640, 0x3fffffff, 0x00000000);
}
}
} else {
if (channel >= 1 && channel <= 14) {
if (all == true) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009f4fbe);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000080);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x018fa3d2);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000079);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009f4fbe);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000080);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x018fa3d2);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000079);
}
} else if (channel >= 36 && channel <= 64) {
if (all == true) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
}
} else if (channel >= 100 && channel <= 144) {
if (all == true) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x013027e6);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x013027e6);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
}
} else if (channel >= 149 && channel <= 177) {
if (all == true) {
halrf_wreg(rf, 0x7604, 0x80000000, 0x1);
halrf_wreg(rf, 0x7600, 0x3fffffff, 0x3f2d2721);
halrf_wreg(rf, 0x7604, 0x003fffff, 0x010101);
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070);
halrf_wreg(rf, 0x7638, 0x000fffff, 0x00000);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7644, 0x000fffff, 0x00000);
} else {
halrf_wreg(rf, 0x7630, 0x3fffffff, 0x009003da);
halrf_wreg(rf, 0x7634, 0x3fffffff, 0x00000070);
halrf_wreg(rf, 0x763c, 0x3fffffff, 0x00000000);
halrf_wreg(rf, 0x7640, 0x3fffffff, 0x00000000);
}
}
}
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n",
__func__,
0x5600 + (path << 13), halrf_rreg(rf, 0x5600 + (path << 13), 0xffffffff),
0x5604 + (path << 13), halrf_rreg(rf, 0x5604 + (path << 13), 0xffffffff),
0x5630 + (path << 13), halrf_rreg(rf, 0x5630 + (path << 13), 0xffffffff),
0x5634 + (path << 13), halrf_rreg(rf, 0x5634 + (path << 13), 0xffffffff),
0x5638 + (path << 13), halrf_rreg(rf, 0x5638 + (path << 13), 0xffffffff),
0x563c + (path << 13), halrf_rreg(rf, 0x563c + (path << 13), 0xffffffff),
0x5640 + (path << 13), halrf_rreg(rf, 0x5640 + (path << 13), 0xffffffff),
0x5644 + (path << 13), halrf_rreg(rf, 0x5644 + (path << 13), 0xffffffff));
}
void _halrf_tssi_run_slope_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5820, 0x80000000, 0x0);
halrf_wreg(rf, 0x5820, 0x80000000, 0x1);
} else {
halrf_wreg(rf, 0x7820, 0x80000000, 0x0);
halrf_wreg(rf, 0x7820, 0x80000000, 0x1);
}
}
void _halrf_tssi_set_tssi_slope_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5814, 0x00000800, 0x1);
halrf_wreg(rf, 0x581c, 0x20000000, 0x1);
halrf_wreg(rf, 0x5814, 0x20000000, 0x1);
} else {
halrf_wreg(rf, 0x7814, 0x00000800, 0x1);
halrf_wreg(rf, 0x781c, 0x20000000, 0x1);
halrf_wreg(rf, 0x7814, 0x20000000, 0x1);
}
}
void _halrf_tssi_set_tssi_track_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5814, 0x00000800, 0x0);
} else {
halrf_wreg(rf, 0x7814, 0x00000800, 0x0);
}
}
void _halrf_tssi_set_txagc_offset_mv_avg_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n", __func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x58e4, 0x000ff800, 0x010);
} else {
halrf_wreg(rf, 0x78e4, 0x000ff800, 0x010);
}
}
u32 _halrf_tssi_get_cck_efuse_group_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u32 offset_index = 0;
if (channel >= 1 && channel <= 2)
offset_index = 0;
else if (channel >= 3 && channel <= 5)
offset_index = 1;
else if (channel >= 6 && channel <= 8)
offset_index = 2;
else if (channel >= 9 && channel <= 11)
offset_index = 3;
else if (channel >= 12 && channel <= 13)
offset_index = 4;
else if (channel == 14)
offset_index = 5;
return offset_index;
}
u32 _halrf_tssi_get_ofdm_efuse_group_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u32 offset_index = 0;
if (channel >= 1 && channel <= 2)
offset_index = 0;
else if (channel >= 3 && channel <= 5)
offset_index = 1;
else if (channel >= 6 && channel <= 8)
offset_index = 2;
else if (channel >= 9 && channel <= 11)
offset_index = 3;
else if (channel >= 12 && channel <= 14)
offset_index = 4;
else if (channel >= 36 && channel <= 40)
offset_index = 5;
else if (channel >= 44 && channel <= 48)
offset_index = 6;
else if (channel >= 52 && channel <= 56)
offset_index = 7;
else if (channel >= 60 && channel <= 64)
offset_index = 8;
else if (channel >= 100 && channel <= 104)
offset_index = 9;
else if (channel >= 108 && channel <= 112)
offset_index = 10;
else if (channel >= 116 && channel <= 120)
offset_index = 11;
else if (channel >= 124 && channel <= 128)
offset_index = 12;
else if (channel >= 132 && channel <= 136)
offset_index = 13;
else if (channel >= 140 && channel <= 144)
offset_index = 14;
else if (channel >= 149 && channel <= 153)
offset_index = 15;
else if (channel >= 157 && channel <= 161)
offset_index = 16;
else if (channel >= 165 && channel <= 169)
offset_index = 17;
else if (channel >= 173 && channel <= 177)
offset_index = 18;
else if (channel > 40 && channel < 44)
offset_index = 0x0506;
else if (channel > 48 && channel < 52)
offset_index = 0x0607;
else if (channel > 56 && channel < 60)
offset_index = 0x0708;
else if (channel > 104 && channel < 108)
offset_index = 0x090a;
else if (channel > 112 && channel < 116)
offset_index = 0x0a0b;
else if (channel > 120 && channel < 124)
offset_index = 0x0b0c;
else if (channel > 128 && channel < 132)
offset_index = 0x0c0d;
else if (channel > 136 && channel < 140)
offset_index = 0x0d0e;
else if (channel > 153 && channel < 157)
offset_index = 0x0f10;
else if (channel > 161 && channel < 165)
offset_index = 0x1011;
else if (channel > 169 && channel < 173)
offset_index = 0x1112;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI efuse] ======> %s offset_index=0x%x(%d) channel=%d\n",
__func__, offset_index, offset_index, channel);
return offset_index;
}
s8 _halrf_tssi_get_ofdm_efuse_tssi_de_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 group_idx;
s8 first_de = 0, second_de = 0, final_de;
group_idx = _halrf_tssi_get_ofdm_efuse_group_8852b(rf, phy);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s group_idx=0x%x(%d)\n",
__func__, group_idx, group_idx);
if (group_idx >= 0x0506) {
first_de = tssi_info->tssi_efuse[path][EFUSE_TSSI_MCS][group_idx >> 8];
second_de = tssi_info->tssi_efuse[path][EFUSE_TSSI_MCS][group_idx & 0xff];
final_de = (first_de + second_de) / 2;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI efuse] first_de=%d second_de=%d final_de=%d\n",
first_de, second_de, final_de);
} else {
final_de = tssi_info->tssi_efuse[path][EFUSE_TSSI_MCS][group_idx];
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI efuse] final_de=%d\n",
final_de);
}
return final_de;
}
u32 _halrf_tssi_get_tssi_trim_efuse_group_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u32 group_index = 0;
if (channel >= 1 && channel <= 8)
group_index = 0;
else if (channel >= 9 && channel <= 14)
group_index = 1;
else if (channel >= 36 && channel <= 48)
group_index = 2;
else if (channel >= 52 && channel <= 64)
group_index = 3;
else if (channel >= 100 && channel <= 112)
group_index = 4;
else if (channel >= 116 && channel <= 128)
group_index = 5;
else if (channel >= 132 && channel <= 144)
group_index = 6;
else if (channel >= 149 && channel <= 177)
group_index = 7;
#if 0
else if (channel > 48 && channel < 52)
group_index = 0x0203;
else if (channel > 120 && channel < 124)
group_index = 0x0405;
else if (channel > 161 && channel < 165)
group_index = 0x0607;
#endif
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] ======> %s offset_index=0x%x(%d) channel=%d\n",
__func__, group_index, group_index, channel);
return group_index;
}
s8 _halrf_tssi_get_ofdm_tssi_trim_de_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 group_idx;
s8 first_de = 0, second_de = 0, final_de;
group_idx = _halrf_tssi_get_tssi_trim_efuse_group_8852b(rf, phy);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] ======> %s group_idx=0x%x(%d)\n",
__func__, group_idx, group_idx);
if (group_idx >= 0x0203) {
first_de = tssi_info->tssi_trim[path][group_idx >> 8];
second_de = tssi_info->tssi_trim[path][group_idx & 0xff];
final_de = (first_de + second_de) / 2;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] Trim_first_de=%d Trim_second_de=%d Trim_final_de=%d\n",
first_de, second_de, final_de);
} else {
final_de = tssi_info->tssi_trim[path][group_idx];
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI Trim] Trim_final_de=%d\n",
final_de);
}
return final_de;
}
void _halrf_tssi_alimentk_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
s16 power_2g[4] = {48, 20, 4, 4};
s16 power_5g[4] = {48, 20, 4, 4};
s16 power[4] = {0};
s32 tssi_alim_offset[4] = {0};
s32 aliment_diff, tssi_cw_default;
u32 tssi_cw_rpt[4] = {0}, tx_couter, tx_couter_tmp, tmp, retry;
u32 tssi_trigger[TSSI_PATH_MAX_8852B] = {0x5820, 0x7820};
u32 tssi_cw_rpt_addr[TSSI_PATH_MAX_8852B] = {0x1c18, 0x3c18};
u32 tssi_cw_default_addr[TSSI_PATH_MAX_8852B][4] =
{{0x5634, 0x5630, 0x5630, 0x5630},
{0x7634, 0x7630, 0x7630, 0x7630}};
u32 tssi_cw_default_mask[4] =
{0x000003ff, 0x3ff00000, 0x000ffc00, 0x000003ff};
//u32 bb_reg[5] = {0x5820, 0x7820, 0x4978, 0x58e4, 0x78e4};
//u32 bb_reg_backup[5] = {0};
//u32 backup_num = 5;
u32 bb_reg[8] = {0x5820, 0x7820, 0x4978, 0x58e4, 0x78e4,
0x49c0, 0x0d18, 0x0d80};
u32 bb_reg_backup[8] = {0};
u32 backup_num = 8;
u8 i, j, k;
u32 rate = T_HT_MF;
u8 bw = 0, band;
u8 phy_map;
u32 start_time, finish_time;
phy_map = (BIT(phy) << 4) | BIT(path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s channel=%d path=%d\n",
__func__, channel, path);
start_time = _os_get_cur_time_us();
halrf_hal_bb_backup_info(rf, phy);
if (channel >= 1 && channel <= 14) {
for (i = 0; i < 4; i++) {
power[i] = power_2g[i];
}
} else {
for (i = 0; i < 4; i++) {
power[i] = power_5g[i];
}
}
if (channel >= 1 && channel <= 14)
band = TSSI_ALIMK_2G;
else if (channel >= 36 && channel <= 64)
band = TSSI_ALIMK_5GL;
else if (channel >= 100 && channel <= 144)
band = TSSI_ALIMK_5GM;
else if (channel >= 149 && channel <= 177)
band = TSSI_ALIMK_5GH;
else
band = TSSI_ALIMK_2G;
_tssi_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
halrf_wreg(rf, 0x5820, 0x0000f000, 0x8);
halrf_wreg(rf, 0x7820, 0x0000f000, 0x8);
halrf_wreg(rf, 0x58e4, 0x00003800, 0x2);
halrf_wreg(rf, 0x78e4, 0x00003800, 0x2);
//halrf_btc_rfk_ntfy(rf, phy_map, RF_BTC_TSSI, RFK_START);
for (j = 0; j < 2; j++) {
halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x0);
halrf_wreg(rf, tssi_trigger[path], 0x80000000, 0x1);
tx_couter = halrf_rreg(rf, 0x1a40, 0xffff);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] 0x%x = 0x%08x path=%d\n",
tssi_trigger[path],
halrf_rreg(rf, tssi_trigger[path], 0xffffffff), path);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power[j], rate, bw, true);
//halrf_delay_ms(rf, 10);
tx_couter_tmp = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] First HWTXcounter=%d path=%d\n",
tx_couter_tmp, path);
for (k = 0; halrf_rreg(rf, tssi_cw_rpt_addr[path], BIT(16)) == 0; k++) {
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) {
halrf_delay_ms(rf, 1);
retry = 30;
} else {
halrf_delay_us(rf, 30);
retry = 100;
}
tx_couter_tmp = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n",
k, tx_couter_tmp, path);
if (k > retry) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n",
k, path);
_tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power[j], rate, bw, false);
return;
}
}
tssi_cw_rpt[j] = halrf_rreg(rf, tssi_cw_rpt_addr[path], 0x000001ff);
_halrf_tssi_hw_tx_8852b(rf, phy, path, 100, 5000, power[j], rate, bw, false);
tx_couter = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] Fianl HWTXcounter = %d path=%d\n",
tx_couter, path);
}
for (j = 0; j < 2; j++) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] power[%d]=%d tssi_cw_rpt[%d]=%d\n",
j, power[j], j, tssi_cw_rpt[j]);
}
tmp = halrf_rreg(rf, tssi_cw_default_addr[path][1],
tssi_cw_default_mask[1]);
if (tmp & BIT(8))
tssi_cw_default = tmp | 0xfffffe00;
else
tssi_cw_default = tmp;
tssi_alim_offset[1] = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) -
tssi_cw_rpt[1] + tssi_cw_default;
aliment_diff = tssi_alim_offset[1] - tssi_cw_default;
/*tssi_alim_offset[2]*/
tmp = halrf_rreg(rf, tssi_cw_default_addr[path][2],
tssi_cw_default_mask[2]);
if (tmp & BIT(8))
tssi_cw_default = tmp | 0xfffffe00;
else
tssi_cw_default = tmp;
tssi_alim_offset[2] = tssi_cw_default + aliment_diff;
/*tssi_alim_offset[3]*/
tmp = halrf_rreg(rf, tssi_cw_default_addr[path][3],
tssi_cw_default_mask[3]);
if (tmp & BIT(8))
tssi_cw_default = tmp | 0xfffffe00;
else
tssi_cw_default = tmp;
tssi_alim_offset[3] = tssi_cw_default + aliment_diff;
if (path == RF_PATH_A) {
tmp = ((tssi_alim_offset[1] & 0x3ff) << 20) |
((tssi_alim_offset[2] & 0x3ff) << 10) |
(tssi_alim_offset[3] & 0x3ff);
halrf_wreg(rf, 0x5630, 0x3fffffff, tmp);
halrf_wreg(rf, 0x563c, 0x3fffffff, tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n",
halrf_rreg(rf, 0x5634, 0x000003ff),
halrf_rreg(rf, 0x5630, 0x3ff00000),
halrf_rreg(rf, 0x5630, 0x000ffc00),
halrf_rreg(rf, 0x5630, 0x000003ff)
);
} else {
tmp = ((tssi_alim_offset[1] & 0x3ff) << 20) |
((tssi_alim_offset[2] & 0x3ff) << 10) |
(tssi_alim_offset[3] & 0x3ff);
halrf_wreg(rf, 0x7630, 0x3fffffff, tmp);
halrf_wreg(rf, 0x763c, 0x3fffffff, tmp);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n",
halrf_rreg(rf, 0x7634, 0x000003ff),
halrf_rreg(rf, 0x7630, 0x3ff00000),
halrf_rreg(rf, 0x7630, 0x000ffc00),
halrf_rreg(rf, 0x7630, 0x000003ff)
);
}
tssi_info->alignment_done[path][band] = true;
tssi_info->alignment_value[path][band][0] = halrf_rreg(rf, 0x5630 + (path << 13), 0xffffffff);
tssi_info->alignment_value[path][band][1] = halrf_rreg(rf, 0x5634 + (path << 13), 0xffffffff);
tssi_info->alignment_value[path][band][2] = halrf_rreg(rf, 0x563c + (path << 13), 0xffffffff);
tssi_info->alignment_value[path][band][3] = halrf_rreg(rf, 0x5640 + (path << 13), 0xffffffff);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n",
path, band, 0x5630 + (path << 13), tssi_info->alignment_value[path][band][0]);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n",
path, band, 0x5634 + (path << 13), tssi_info->alignment_value[path][band][1]);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
path, band, 0x563c + (path << 13), tssi_info->alignment_value[path][band][2]);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
path, band, 0x5640 + (path << 13), tssi_info->alignment_value[path][band][3]);
_tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
halrf_hal_bb_restore_info(rf, phy);
if (rf->phl_com->drv_mode != RTW_DRV_MODE_MP)
halrf_tx_mode_switch(rf, phy, 0);
finish_time = _os_get_cur_time_us();
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI PA K] %s processing time = %d.%dms\n",
__func__,
HALRF_ABS(finish_time, start_time) / 1000,
HALRF_ABS(finish_time, start_time) % 1000);
}
void _halrf_tssi_alimentk_done_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u8 band;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d path=%d\n", __func__, phy, path);
if (channel >= 1 && channel <= 14)
band = TSSI_ALIMK_2G;
else if (channel >= 36 && channel <= 64)
band = TSSI_ALIMK_5GL;
else if (channel >= 100 && channel <= 144)
band = TSSI_ALIMK_5GM;
else if (channel >= 149 && channel <= 177)
band = TSSI_ALIMK_5GH;
else
band = TSSI_ALIMK_2G;
if (tssi_info->alignment_done[path][band] == true) {
halrf_wreg(rf, 0x5630 + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][0]);
halrf_wreg(rf, 0x5634 + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][1]);
halrf_wreg(rf, 0x563c + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][2]);
halrf_wreg(rf, 0x5640 + (path << 13), 0xffffffff, tssi_info->alignment_value[path][band][3]);
}
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n",
0x5600 + (path << 13), halrf_rreg(rf, 0x5600 + (path << 13), 0xffffffff),
0x5604 + (path << 13), halrf_rreg(rf, 0x5604 + (path << 13), 0xffffffff),
0x5630 + (path << 13), halrf_rreg(rf, 0x5630 + (path << 13), 0xffffffff),
0x5634 + (path << 13), halrf_rreg(rf, 0x5634 + (path << 13), 0xffffffff),
0x5638 + (path << 13), halrf_rreg(rf, 0x5638 + (path << 13), 0xffffffff),
0x563c + (path << 13), halrf_rreg(rf, 0x563c + (path << 13), 0xffffffff),
0x5640 + (path << 13), halrf_rreg(rf, 0x5640 + (path << 13), 0xffffffff),
0x5644 + (path << 13), halrf_rreg(rf, 0x5644 + (path << 13), 0xffffffff));
}
void halrf_tssi_backup_txagc_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool enable)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u8 bw = rf->hal_com->band[phy].cur_chandef.bw;
s8 power, power_tmp;
s16 xdbm;
u32 i, j, tx_couter = 0;
u8 ch_idx = _halrf_ch_to_idx(rf, channel);
u8 channel_tmp;
//u32 bb_reg[4] = {0x5820, 0x7820, 0x58e4, 0x78e4};
//u32 bb_reg_backup[4] = {0};
//u32 backup_num = 4;
u32 bb_reg[7] = {0x5820, 0x7820, 0x58e4, 0x78e4,
0x49c0, 0x0d18, 0x0d80};
u32 bb_reg_backup[7] = {0};
u32 backup_num = 7;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d enable=%d\n", __func__, phy, enable);
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s phy=%d rf->phl_com->drv_mode == RTW_DRV_MODE_MP return!!!\n",
__func__, phy);
return;
}
if (enable == false) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s phy=%d enable=%d return!!!\n",
__func__, phy, enable);
return;
}
if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s phy=%d rf->is_tssi_mode[A&B] != true return!!!\n",
__func__, phy);
return;
}
if (tssi_info->check_backup_txagc[ch_idx] == true) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s check_backup_txagc[%d]==true Backup 0x1c60=0x%x 0x3c60=0x%x channel=%d return!!!\n",
__func__, ch_idx,
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx],
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx],
channel);
halrf_wreg(rf, 0x5818, 0x000000ff,
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx]);
halrf_wreg(rf, 0x7818, 0x000000ff,
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]);
halrf_wreg(rf, 0x5818 , 0x10000000, 0x0);
halrf_wreg(rf, 0x5818 , 0x10000000, 0x1);
halrf_wreg(rf, 0x7818 , 0x10000000, 0x0);
halrf_wreg(rf, 0x7818 , 0x10000000, 0x1);
return;
}
halrf_hal_bb_backup_info(rf, phy);
_tssi_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
halrf_wreg(rf, 0x5820, 0x0000f000, 0x8);
halrf_wreg(rf, 0x7820, 0x0000f000, 0x8);
halrf_wreg(rf, 0x58e4, 0x00003800, 0x2);
halrf_wreg(rf, 0x78e4, 0x00003800, 0x2);
if (bw == CHANNEL_WIDTH_40)
channel_tmp = channel - 2;
else if (bw == CHANNEL_WIDTH_80)
channel_tmp = channel - 6;
else
channel_tmp = channel;
power = halrf_get_power_limit(rf, phy, RF_PATH_A,
RTW_DATA_RATE_MCS0, CHANNEL_WIDTH_20,
PW_LMT_NONBF, PW_LMT_PH_1T, channel_tmp);
if (power > 17 * 4)
power_tmp = 17 * 4;
else
power_tmp = power;
xdbm = power_tmp * 100 / 4;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s phy=%d limit_table=%d power_tmp=%d xdbm=%d\n",
__func__, phy, power, power_tmp, xdbm);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START);
halrf_tmac_tx_pause(rf, phy, true);
/*Path A*/
tx_couter= halrf_rreg(rf, 0x1a40, 0xffff);
_halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_AB, 1000, 100, power_tmp, T_HT_MF, 0, true);
#if 0
/*Path B*/
tx_couter[RF_PATH_B] = halrf_rreg(rf, 0x1a40, 0xffff);
_halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_B, 1000, 100, xdbm, T_HT_MF, 0, true);
halrf_delay_ms(rf, 15);
_halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_B, 1000, 100, xdbm, T_HT_MF, 0, false);
#endif
for (i = 0; i < 6; i++) {
for (j = 0; j < 300; j++)
halrf_delay_us(rf, 10);
if (halrf_rreg(rf, 0x1c60, 0xff000000) != 0x0 &&
halrf_rreg(rf, 0x3c60, 0xff000000) != 0x0) {
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx] =
halrf_rreg(rf, 0x1c60, 0xff000000);
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx] =
halrf_rreg(rf, 0x3c60, 0xff000000);
tssi_info->check_backup_txagc[ch_idx] = true;
break;
}
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"Get %d times 0x1c60=0x%x 0x3c60=0x%x\n",
i,
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx],
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]);
}
tssi_info->backup_txagc_oft_ther[RF_PATH_A][ch_idx] =
halrf_get_thermal_8852b(rf, RF_PATH_A);
tssi_info->backup_txagc_oft_ther[RF_PATH_B][ch_idx] =
halrf_get_thermal_8852b(rf, RF_PATH_B);
_halrf_tssi_hw_tx_8852b(rf, phy, RF_PATH_AB, 1000, 100, power_tmp, T_HT_MF, 0, false);
tx_couter = halrf_rreg(rf, 0x1a40, 0xffff) - tx_couter;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s tx couter=%d\n",
__func__, tx_couter);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"Backup TSSI TXAGC Offset ch_idx=%d 0x1c60=0x%x therA=0x%x channel=%d\n",
ch_idx,
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx],
tssi_info->backup_txagc_oft_ther[RF_PATH_A][ch_idx],
channel);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"Backup TSSI TXAGC Offset ch_idx=%d 0x3c60=0x%x therB=0x%x channel=%d\n",
ch_idx,
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx],
tssi_info->backup_txagc_oft_ther[RF_PATH_B][ch_idx],
channel);
halrf_wreg(rf, 0x5818, 0x000000ff,
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx]);
halrf_wreg(rf, 0x7818, 0x000000ff,
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]);
halrf_wreg(rf, 0x5818 , 0x10000000, 0x0);
halrf_wreg(rf, 0x5818 , 0x10000000, 0x1);
halrf_wreg(rf, 0x7818 , 0x10000000, 0x0);
halrf_wreg(rf, 0x7818 , 0x10000000, 0x1);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
__func__,
halrf_rreg(rf, 0x5818, 0x000000ff),
halrf_rreg(rf, 0x7818, 0x000000ff));
_tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
halrf_hal_bb_restore_info(rf, phy);
halrf_tx_mode_switch(rf, phy, 0);
halrf_tmac_tx_pause(rf, phy, false);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP);
//_tssi_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup, backup_num);
}
void halrf_do_tssi_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u8 ch_idx = _halrf_ch_to_idx(rf, channel);
u32 i;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s phy=%d ch=%d ch_idx=%d\n",
__func__, phy, channel, ch_idx);
tssi_info->check_backup_txagc[ch_idx] = false;
halrf_tssi_disable_8852b(rf, phy);
for (i = RF_PATH_A; i < TSSI_PATH_MAX_8852B; i++) {
_halrf_tssi_rf_setting_8852b(rf, phy, i);
_halrf_tssi_set_sys_8852b(rf, phy, i);
_halrf_tssi_ini_txpwr_ctrl_bb_8852b(rf, phy, i);
_halrf_tssi_ini_txpwr_ctrl_bb_he_tb_8852b(rf, phy, i);
_halrf_tssi_set_dck_8852b(rf, phy, i);
//_halrf_tssi_set_bbgain_split_8852b(rf, phy, i);
_halrf_tssi_set_tmeter_tbl_8852b(rf, phy, i);
_halrf_tssi_set_dac_gain_tbl_8852b(rf, phy, i);
_halrf_tssi_slope_cal_org_8852b(rf, phy, i);
_halrf_tssi_set_rf_gap_tbl_8852b(rf, phy, i);
if (rf->hal_com->cv == CAV)
_halrf_tssi_alignment_default_8852ba(rf, phy, i);
else
_halrf_tssi_alignment_default_8852bb(rf, phy, i, true);
_halrf_tssi_set_tssi_slope_8852b(rf, phy, i);
//halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START);
//halrf_tmac_tx_pause(rf, phy, true);
//if (rfe_type <= 50)
//_halrf_tssi_slope_cal_8852b(rf, phy, i);
//halrf_tmac_tx_pause(rf, phy, false);
//halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START);
halrf_tmac_tx_pause(rf, phy, true);
_halrf_tssi_alimentk_8852b(rf, phy, i);
halrf_tmac_tx_pause(rf, phy, false);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP);
}
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP) {
if (tssi_info->tssi_type == TSSI_ON || tssi_info->tssi_type == TSSI_CAL) {
halrf_tssi_enable_8852b(rf, phy);
halrf_tssi_set_efuse_to_de_8852b(rf, phy);
} else
halrf_tssi_disable_8852b(rf, phy);
} else {
if (rf->support_ability & HAL_RF_TX_PWR_TRACK) {
halrf_tssi_enable_8852b(rf, phy);
halrf_tssi_set_efuse_to_de_8852b(rf, phy);
halrf_tssi_backup_txagc_8852b(rf, phy, true);
}
}
tssi_info->do_tssi = true;
}
void halrf_do_tssi_scan_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 i;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
u8 band;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d channel=%d\n",
__func__, phy, channel);
if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s phy=%d rf->is_tssi_mode[A&B] != true return!!!\n",
__func__, phy);
return;
}
if (channel >= 1 && channel <= 14)
band = TSSI_ALIMK_2G;
else if (channel >= 36 && channel <= 64)
band = TSSI_ALIMK_5GL;
else if (channel >= 100 && channel <= 144)
band = TSSI_ALIMK_5GM;
else if (channel >= 149 && channel <= 177)
band = TSSI_ALIMK_5GH;
else
band = TSSI_ALIMK_2G;
halrf_tssi_disable_8852b(rf, phy);
for (i = RF_PATH_A; i < TSSI_PATH_MAX_8852B; i++) {
_halrf_tssi_rf_setting_8852b(rf, phy, i);
_halrf_tssi_set_sys_8852b(rf, phy, i);
//_halrf_tssi_ini_txpwr_ctrl_bb_8852b(rf, phy, i);
//_halrf_tssi_ini_txpwr_ctrl_bb_he_tb_8852b(rf, phy, i);
//_halrf_tssi_set_dck_8852b(rf, phy, i);
//_halrf_tssi_set_bbgain_split_8852b(rf, phy, i);
_halrf_tssi_set_tmeter_tbl_8852b(rf, phy, i);
//_halrf_tssi_set_dac_gain_tbl_8852b(rf, phy, i);
//_halrf_tssi_slope_cal_org_8852b(rf, phy, i);
//_halrf_tssi_set_rf_gap_tbl_8852b(rf, phy, i);
//_halrf_tssi_set_tssi_slope_8852b(rf, phy, i);
if (tssi_info->alignment_done[i][band] == true)
_halrf_tssi_alimentk_done_8852b(rf, phy, i);
else {
if (rf->hal_com->cv == CAV)
_halrf_tssi_alignment_default_8852ba(rf, phy, i);
else
_halrf_tssi_alignment_default_8852bb(rf, phy, i, false);
}
}
halrf_tssi_enable_8852b(rf, phy);
halrf_tssi_set_efuse_to_de_8852b(rf, phy);
}
void halrf_tssi_get_efuse_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
s8 de_offset = 0;
u32 i, j;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
/*path s0*/
for (i = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6; i++, j++) {
halrf_efuse_get_info(rf, i, &de_offset, 1);
tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_CCK][j] = de_offset;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n",
i, tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_CCK][j]);
}
for (i = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14; i++, j++) {
halrf_efuse_get_info(rf, i, &de_offset, 1);
tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_MCS][j] = de_offset;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n",
i, tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_MCS][j]);
}
/*path s1*/
for (i = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6; i++, j++) {
halrf_efuse_get_info(rf, i, &de_offset, 1);
tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_CCK][j] = de_offset;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n",
i, tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_CCK][j]);
}
for (i = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14; i++, j++) {
halrf_efuse_get_info(rf, i, &de_offset, 1);
tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_MCS][j] = de_offset;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse_addr=0x%x value=0x%x\n",
i, tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_MCS][j]);
}
}
bool halrf_tssi_check_efuse_data_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 i, j, countr = 0;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
halrf_tssi_get_efuse_8852b(rf, phy);
/*path s0*/
for (i = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6; i++, j++) {
if ((tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_CCK][j] & 0xff) == 0xff)
countr++;
}
for (i = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14; i++, j++) {
if ((tssi_info->tssi_efuse[RF_PATH_A][EFUSE_TSSI_MCS][j] & 0xff) == 0xff)
countr++;
}
/*path s1*/
for (i = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6; i++, j++) {
if ((tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_CCK][j] & 0xff) == 0xff)
countr++;
}
for (i = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1, j = 0; i <= EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14; i++, j++) {
if ((tssi_info->tssi_efuse[RF_PATH_B][EFUSE_TSSI_MCS][j] & 0xff) == 0xff)
countr++;
}
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] countr == %d\n", countr);
if (countr == 50) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI][Efuse] Efuse all are 0xff, return false!!!\n");
return false;
}
return true;
}
void halrf_set_tssi_de_for_tx_verify_8852b(struct rf_info *rf,
enum phl_phy_idx phy, u32 tssi_de, u8 path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 tssi_de_tmp;
s32 s_tssi_de, tmp;
s8 tssi_trim;
u32 addr_cck_long[2] = {0x5858, 0x7858};
u32 addr_cck_short[2] = {0x5860, 0x7860};
u32 addr_cck_bitmask[2] = {0x003ff000, 0x003ff000};
u32 addr_mcs_20m[2] = {0x5838, 0x7838};
u32 addr_mcs_40m[2] = {0x5840, 0x7840};
u32 addr_mcs_80m[2] = {0x5848, 0x7848};
u32 addr_mcs_80m_80m[2] = {0x5850, 0x7850};
u32 addr_mcs_5m[2] = {0x5828, 0x7828};
u32 addr_mcs_10m[2] = {0x5830, 0x7830};
u32 addr_mcs_bitmask[2] = {0x003ff000, 0x003ff000};
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d tssi_de=0x%x path=%d\n",
__func__, phy, tssi_de, path);
if (tssi_de & BIT(7))
s_tssi_de = tssi_de | 0xffffff00;
else
s_tssi_de = tssi_de;
tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, path);
tmp = s_tssi_de + tssi_trim;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] tmp(%d) = s_tssi_de(%d) + tssi_trim(%d)\n",
tmp, s_tssi_de, tssi_trim);
tssi_de_tmp = tmp & 0x3ff;
halrf_wreg(rf, addr_cck_long[path], addr_cck_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_cck_short[path], addr_cck_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_mcs_20m[path], addr_mcs_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_mcs_40m[path], addr_mcs_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_mcs_80m[path], addr_mcs_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_mcs_80m_80m[path], addr_mcs_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_mcs_5m[path], addr_mcs_bitmask[path], tssi_de_tmp);
halrf_wreg(rf, addr_mcs_10m[path], addr_mcs_bitmask[path], tssi_de_tmp);
tssi_info->tssi_de[path] = tmp;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x%x[21:12]=0x%x 0x%x[21:12]=0x%x path=%d\n",
addr_mcs_20m[path],
halrf_rreg(rf, addr_mcs_20m[path], 0x003ff000),
addr_cck_long[path],
halrf_rreg(rf, addr_cck_long[path], 0x003ff000),
path);
/*Save TSSI data for WINCLI*/
tssi_info->curr_tssi_cck_de[path] =
(s8)(halrf_rreg(rf, addr_cck_long[path], addr_cck_bitmask[path]) & 0xff);
tssi_info->curr_tssi_ofdm_de[path] =
(s8)(halrf_rreg(rf, addr_mcs_20m[path], addr_mcs_bitmask[path]) & 0xff);
tssi_info->curr_tssi_efuse_cck_de[path] = (s8)s_tssi_de;
tssi_info->curr_tssi_efuse_ofdm_de[path] = (s8)s_tssi_de;
tssi_info->curr_tssi_trim_de[path] = tssi_trim;
}
void halrf_set_tssi_de_offset_8852b(struct rf_info *rf,
enum phl_phy_idx phy, u32 tssi_de_offset, u8 path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
s32 tssi_tmp, s_tssi_de_offset;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s phy=%d tssi_de_offset=0x%x path=%d\n",
__func__, phy, tssi_de_offset, path);
if (tssi_de_offset & BIT(7))
s_tssi_de_offset = tssi_de_offset | 0xffffff00;
else
s_tssi_de_offset = tssi_de_offset;
s_tssi_de_offset = s_tssi_de_offset * -1;
if (path == RF_PATH_A) {
tssi_tmp = tssi_info->tssi_de[RF_PATH_A] + s_tssi_de_offset;
tssi_tmp = tssi_tmp & 0x3ff;
halrf_wreg(rf, 0x5838, 0x003ff000, tssi_tmp); /*20M*/
halrf_wreg(rf, 0x5858, 0x003ff000, tssi_tmp); /*CCK long*/
halrf_wreg(rf, 0x5828, 0x003ff000, tssi_tmp); /*5M*/
halrf_wreg(rf, 0x5830, 0x003ff000, tssi_tmp); /*10M*/
halrf_wreg(rf, 0x5840, 0x003ff000, tssi_tmp); /*40M*/
halrf_wreg(rf, 0x5848, 0x003ff000, tssi_tmp); /*80M*/
halrf_wreg(rf, 0x5850, 0x003ff000, tssi_tmp); /*80M+80M*/
halrf_wreg(rf, 0x5860, 0x003ff000, tssi_tmp); /*CCK short*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] tssi_tmp(%d) = tssi_info->tssi_de[RF_PATH_A](%d) + s_tssi_de_offset(%d) path=%d\n",
tssi_tmp, tssi_info->tssi_de[RF_PATH_A],
s_tssi_de_offset, path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x5838[21:12]=0x%x 0x5858[21:12]=0x%x path=%d\n",
halrf_rreg(rf, 0x5838, 0x003ff000),
halrf_rreg(rf, 0x5858, 0x003ff000),
path);
} else {
tssi_tmp = tssi_info->tssi_de[RF_PATH_B] + s_tssi_de_offset;
tssi_tmp = tssi_tmp & 0x3ff;
halrf_wreg(rf, 0x7838, 0x003ff000, tssi_tmp); /*20M*/
halrf_wreg(rf, 0x7858, 0x003ff000, tssi_tmp); /*CCK long*/
halrf_wreg(rf, 0x7828, 0x003ff000, tssi_tmp); /*5M*/
halrf_wreg(rf, 0x7830, 0x003ff000, tssi_tmp); /*10M*/
halrf_wreg(rf, 0x7840, 0x003ff000, tssi_tmp); /*40M*/
halrf_wreg(rf, 0x7848, 0x003ff000, tssi_tmp); /*80M*/
halrf_wreg(rf, 0x7850, 0x003ff000, tssi_tmp); /*80M+80M*/
halrf_wreg(rf, 0x7860, 0x003ff000, tssi_tmp); /*CCK short*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] tssi_tmp(%d) = tssi_info->tssi_de[RF_PATH_B](%d) + s_tssi_de_offset(%d) path=%d\n",
tssi_tmp, tssi_info->tssi_de[RF_PATH_B],
s_tssi_de_offset, path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x7838[21:12]=0x%x 0x7858[21:12]=0x%x path=%d\n",
halrf_rreg(rf, 0x7838, 0x003ff000),
halrf_rreg(rf, 0x7858, 0x003ff000),
path);
}
}
void halrf_set_tssi_de_offset_zero_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
halrf_wreg(rf, 0x5838, 0x003ff000, 0x0); /*20M*/
halrf_wreg(rf, 0x5858, 0x003ff000, 0x0); /*CCK long*/
halrf_wreg(rf, 0x5828, 0x003ff000, 0x0); /*5M*/
halrf_wreg(rf, 0x5830, 0x003ff000, 0x0); /*10M*/
halrf_wreg(rf, 0x5840, 0x003ff000, 0x0); /*40M*/
halrf_wreg(rf, 0x5848, 0x003ff000, 0x0); /*80M*/
halrf_wreg(rf, 0x5850, 0x003ff000, 0x0); /*80M+80M*/
halrf_wreg(rf, 0x5860, 0x003ff000, 0x0); /*CCK short*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE Zero 0x5838[21:12]=0x%x 0x5858[21:12]=0x%x\n",
halrf_rreg(rf, 0x5838, 0x003ff000),
halrf_rreg(rf, 0x5858, 0x003ff000));
halrf_wreg(rf, 0x7838, 0x003ff000, 0x0); /*20M*/
halrf_wreg(rf, 0x7858, 0x003ff000, 0x0); /*CCK long*/
halrf_wreg(rf, 0x7828, 0x003ff000, 0x0); /*5M*/
halrf_wreg(rf, 0x7830, 0x003ff000, 0x0); /*10M*/
halrf_wreg(rf, 0x7840, 0x003ff000, 0x0); /*40M*/
halrf_wreg(rf, 0x7848, 0x003ff000, 0x0); /*80M*/
halrf_wreg(rf, 0x7850, 0x003ff000, 0x0); /*80M+80M*/
halrf_wreg(rf, 0x7860, 0x003ff000, 0x0); /*CCK short*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE Zero 0x7838[21:12]=0x%x 0x7858[21:12]=0x%x\n",
halrf_rreg(rf, 0x7838, 0x003ff000),
halrf_rreg(rf, 0x7858, 0x003ff000));
}
void halrf_tssi_enable_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 i;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s\n", __func__);
for (i = 0; i < TSSI_PATH_MAX_8852B; i++) {
/*_halrf_tssi_set_tssi_slope_8852b(rf, phy, i);*/
_halrf_tssi_set_tssi_track_8852b(rf, phy, i);
_halrf_tssi_set_txagc_offset_mv_avg_8852b(rf, phy, i);
if (i == RF_PATH_A) {
halrf_wreg(rf, 0x58e4, 0x00004000, 0x0);
halrf_wreg(rf, 0x5820, 0x80000000, 0x0);
halrf_wreg(rf, 0x5820, 0x80000000, 0x1);
halrf_wrf(rf, i, 0x10055, 0x00080, 0x1);
halrf_wreg(rf, 0x5818, 0x18000000, 0x3);
rf->is_tssi_mode[RF_PATH_A] = true;
} else {
halrf_wreg(rf, 0x78e4, 0x00004000, 0x0);
halrf_wreg(rf, 0x7820, 0x80000000, 0x0);
halrf_wreg(rf, 0x7820, 0x80000000, 0x1);
halrf_wrf(rf, i, 0x10055, 0x00080, 0x1);
halrf_wreg(rf, 0x7818, 0x18000000, 0x3);
rf->is_tssi_mode[RF_PATH_B] = true;
}
}
}
void halrf_tssi_disable_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
#if 0
halrf_wreg(rf, 0x5820, 0x80000000, 0x0);
/*Request by Jerry for DPK*/
halrf_wreg(rf, 0x5818, 0x18000000, 0x1);
halrf_wreg(rf, 0x7820, 0x80000000, 0x0);
/*Request by Jerry for DPK*/
halrf_wreg(rf, 0x7818, 0x18000000, 0x1);
/*Path A*/
halrf_wreg(rf, 0x5818, 0x000000ff, 0x0); /*TXAGC_OFFSET init = 0*/
halrf_wreg(rf, 0x58dc, 0x80000000, 0x0); /*rst release*/
halrf_wreg(rf, 0x58dc, 0x80000000, 0x1); /*rst*/
/*Path B*/
halrf_wreg(rf, 0x7818, 0x000000ff, 0x0); /*TXAGC_OFFSET init = 0*/
halrf_wreg(rf, 0x78dc, 0x80000000, 0x0); /*rst release*/
halrf_wreg(rf, 0x78dc, 0x80000000, 0x1); /*rst*/
#endif
halrf_wreg(rf, 0x5820, 0x80000000, 0x0);
halrf_wreg(rf, 0x5818, 0x18000000, 0x1);
halrf_wreg(rf, 0x58e4, 0x00004000, 0x1);
halrf_wreg(rf, 0x7820, 0x80000000, 0x0);
halrf_wreg(rf, 0x7818, 0x18000000, 0x1);
halrf_wreg(rf, 0x78e4, 0x00004000, 0x1);
rf->is_tssi_mode[RF_PATH_A] = false;
rf->is_tssi_mode[RF_PATH_B] = false;
}
s32 halrf_get_online_tssi_de_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path, s32 dbm, s32 puot)
{
s32 de = ((puot - dbm) * 8) / 100;
s32 s_tssi_offset;
u32 tssi_offset;
s8 tssi_trim;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s phy=%d\n", __func__, phy_idx);
if (path == RF_PATH_A) {
tssi_offset = halrf_rreg(rf, 0x5838, 0x003ff000);
/*tssi_offset = halrf_rreg(rf, 0x5858, 0x003ff000);*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x5838[21:12]=0x%x 0x5858[21:12]=0x%x path=%d\n",
halrf_rreg(rf, 0x5838, 0x003ff000),
halrf_rreg(rf, 0x5858, 0x003ff000),
path);
} else {
tssi_offset = halrf_rreg(rf, 0x7838, 0x003ff000);
/*tssi_offset = halrf_rreg(rf, 0x7858, 0x003ff000);*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI DE 0x7838[21:12]=0x%x 0x7858[21:12]=0x%x path=%d\n",
halrf_rreg(rf, 0x7838, 0x003ff000),
halrf_rreg(rf, 0x7858, 0x003ff000),
path);
}
if (tssi_offset & BIT(9))
s_tssi_offset = tssi_offset | 0xfffffc00;
else
s_tssi_offset = tssi_offset;
tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy_idx, path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] de(%d) = de(%d) + s_tssi_offset(%d) - tssi_trim(%d) path=%d\n",
(de + s_tssi_offset - tssi_trim), de, s_tssi_offset, tssi_trim, path);
de = de + s_tssi_offset - tssi_trim;
de = de & 0xff;
return de;
}
void halrf_tssi_set_efuse_to_de_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 addr_cck_long[2] = {0x5858, 0x7858};
u32 addr_cck_short[2] = {0x5860, 0x7860};
u32 addr_cck_bitmask[2] = {0x003ff000, 0x003ff000};
u32 addr_mcs_20m[2] = {0x5838, 0x7838};
u32 addr_mcs_40m[2] = {0x5840, 0x7840};
u32 addr_mcs_80m[2] = {0x5848, 0x7848};
u32 addr_mcs_80m_80m[2] = {0x5850, 0x7850};
u32 addr_mcs_5m[2] = {0x5828, 0x7828};
u32 addr_mcs_10m[2] = {0x5830, 0x7830};
u32 addr_mcs_bitmask[2] = {0x003ff000, 0x003ff000};
u32 i, group_idx;
s32 tmp;
s8 ofmd_de, tssi_trim;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s\n", __func__);
if (tssi_info->tssi_type == TSSI_CAL) {
/*halrf_set_tssi_de_offset_zero_8852b(rf, phy);*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s TSSI_CAL mode set TSSI Trim !!!\n", __func__);
for (i = 0; i < TSSI_PATH_MAX_8852B; i++) {
tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, i);
tmp = (s32)tssi_trim;
halrf_wreg(rf, addr_cck_long[i], addr_cck_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_cck_short[i], addr_cck_bitmask[i],
(u32)(tmp & 0x3ff));
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] TSSI_CAL Set TSSI Trim CCK DE 0x%x[21:12]=0x%x\n",
addr_cck_long[i], halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i]));
halrf_wreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_40m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_80m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_80m_80m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_5m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_10m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] TSSI_CAL Set TSSI Trim MCS DE 0x%x[21:12]=0x%x\n",
addr_mcs_20m[i], halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i]));
/*Save TSSI data for WINCLI*/
tssi_info->curr_tssi_cck_de[i] =
(s8)(halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i]) & 0xff);
tssi_info->curr_tssi_ofdm_de[i] =
(s8)(halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i]) & 0xff);
tssi_info->curr_tssi_efuse_cck_de[i] = 0;
tssi_info->curr_tssi_efuse_ofdm_de[i] = 0;
tssi_info->curr_tssi_trim_de[i] = tssi_trim;
}
return;
}
for (i = 0; i < TSSI_PATH_MAX_8852B; i++) {
/*CCK*/
group_idx = _halrf_tssi_get_cck_efuse_group_8852b(rf, phy);
tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, i);
tmp = tssi_info->tssi_efuse[i][EFUSE_TSSI_CCK][group_idx] +
tssi_trim;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] tmp(0x%x) = tssi_efuse_cck[%d](0x%x) + tssi_trim(0x%x) path=%d\n",
tmp, group_idx, tssi_info->tssi_efuse[i][EFUSE_TSSI_CCK][group_idx],
tssi_trim, i);
halrf_wreg(rf, addr_cck_long[i], addr_cck_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_cck_short[i], addr_cck_bitmask[i],
(u32)(tmp & 0x3ff));
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
addr_cck_long[i], halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i]));
/*OFDM*/
ofmd_de = _halrf_tssi_get_ofdm_efuse_tssi_de_8852b(rf, phy, i);
tssi_trim = _halrf_tssi_get_ofdm_tssi_trim_de_8852b(rf, phy, i);
tmp = ofmd_de + tssi_trim;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"[TSSI] tmp(0x%x) = tssi_efuse_ofdm(0x%x) + tssi_trim(0x%x) path=%d\n",
tmp, ofmd_de, tssi_trim, i);
halrf_wreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_40m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_80m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_80m_80m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_5m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
halrf_wreg(rf, addr_mcs_10m[i], addr_mcs_bitmask[i],
(u32)(tmp & 0x3ff));
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
addr_mcs_20m[i], halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i]));
/*Save TSSI data for WINCLI*/
tssi_info->curr_tssi_cck_de[i] =
(s8)(halrf_rreg(rf, addr_cck_long[i], addr_cck_bitmask[i]) & 0xff);
tssi_info->curr_tssi_ofdm_de[i] =
(s8)(halrf_rreg(rf, addr_mcs_20m[i], addr_mcs_bitmask[i]) & 0xff);
tssi_info->curr_tssi_efuse_cck_de[i] = tssi_info->tssi_efuse[i][EFUSE_TSSI_CCK][group_idx];
tssi_info->curr_tssi_efuse_ofdm_de[i] = ofmd_de;
tssi_info->curr_tssi_trim_de[i] = tssi_trim;
}
}
void halrf_tssi_default_txagc_8852b(struct rf_info *rf,
enum phl_phy_idx phy, bool enable)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u8 ch_idx = _halrf_ch_to_idx(rf, channel);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s ch=%d\n", __func__, channel);
if (enable == true) {
/*SCAN_START*/
tssi_info->start_time = _os_get_cur_time_us();
if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s phy=%d rf->is_tssi_mode[A&B] != true return!!!\n",
__func__, phy);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s SCAN_START\n", __func__);
halrf_do_tssi_8852b(rf, phy);
return;
}
} else {
/*SCAN_END*/
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
__func__,
halrf_rreg(rf, 0x5818, 0x000000ff),
halrf_rreg(rf, 0x7818, 0x000000ff));
halrf_wreg(rf, 0x5818, 0x000000ff,
tssi_info->backup_txagc_offset[RF_PATH_A][ch_idx]);
halrf_wreg(rf, 0x7818, 0x000000ff,
tssi_info->backup_txagc_offset[RF_PATH_B][ch_idx]);
halrf_wreg(rf, 0x5818 , 0x10000000, 0x0);
halrf_wreg(rf, 0x5818 , 0x10000000, 0x1);
halrf_wreg(rf, 0x7818 , 0x10000000, 0x0);
halrf_wreg(rf, 0x7818 , 0x10000000, 0x1);
_halrf_tssi_alimentk_done_8852b(rf, phy, RF_PATH_A);
_halrf_tssi_alimentk_done_8852b(rf, phy, RF_PATH_B);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
__func__,
halrf_rreg(rf, 0x5818, 0x000000ff),
halrf_rreg(rf, 0x7818, 0x000000ff));
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======> %s SCAN_END\n", __func__);
tssi_info->finish_time = _os_get_cur_time_us();
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] %s processing time = %d.%dms\n",
__func__,
HALRF_ABS(tssi_info->finish_time, tssi_info->start_time) / 1000,
HALRF_ABS(tssi_info->finish_time, tssi_info->start_time) % 1000);
}
}
void halrf_tssi_scan_ch_8852b(struct rf_info *rf, enum rf_path path)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 tssi_trk_man[2] = {0x5818, 0x7818};
u32 tssi_en[2] = {0x5820, 0x7820};
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u8 ch_idx = _halrf_ch_to_idx(rf, channel);
u8 band;
if (rf->is_tssi_mode[RF_PATH_A] != true && rf->is_tssi_mode[RF_PATH_B] != true) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s rf->is_tssi_mode[A&B] != true return!!!\n",
__func__);
return;
}
if (channel >= 1 && channel <= 14)
band = TSSI_ALIMK_2G;
else if (channel >= 36 && channel <= 64)
band = TSSI_ALIMK_5GL;
else if (channel >= 100 && channel <= 144)
band = TSSI_ALIMK_5GM;
else if (channel >= 149 && channel <= 177)
band = TSSI_ALIMK_5GH;
else
band = TSSI_ALIMK_2G;
if (!(rf->phl_com->drv_mode == RTW_DRV_MODE_MP)) {
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s Restore_txagc_offset[%d][%d]=0x%x ther=0x%x channel=%d path=%d\n",
__func__, path, ch_idx, tssi_info->backup_txagc_offset[path][ch_idx],
tssi_info->backup_txagc_oft_ther[path][ch_idx], channel, path);
if (tssi_info->alignment_done[path][band] == true)
_halrf_tssi_alimentk_done_8852b(rf, 0, path);
else {
if (rf->hal_com->cv == CAV)
_halrf_tssi_alignment_default_8852ba(rf, 0, path);
else
_halrf_tssi_alignment_default_8852bb(rf, 0, path, false);
}
halrf_wreg(rf, tssi_en[path], BIT(31), 0x0);
halrf_wreg(rf, tssi_en[path], BIT(31), 0x1);
halrf_wreg(rf, tssi_trk_man[path], 0x000000ff,
tssi_info->backup_txagc_offset[path][ch_idx]);
halrf_wreg(rf, tssi_trk_man[path], BIT(28), 0x0);
halrf_wreg(rf, tssi_trk_man[path], BIT(28), 0x1);
}
}
u32 halrf_tssi_get_final_8852b(struct rf_info *rf, enum rf_path path)
{
u32 i;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "======>%s path=%d\n",
__func__, path);
if (path == RF_PATH_A) {
halrf_wreg(rf, 0x5818, 0x10000000, 0x0);
halrf_wreg(rf, 0x5820, 0x80000000, 0x0);
halrf_wreg(rf, 0x5820, 0x80000000, 0x1);
halrf_wreg(rf, 0x58b4, 0x0000001f, 0x7);
for (i = 0; i < 300; i ++)
halrf_delay_us(rf, 10);
return halrf_rreg(rf, 0x1c00, 0x0003fe00);
} else {
halrf_wreg(rf, 0x7818, 0x10000000, 0x0);
halrf_wreg(rf, 0x7820, 0x80000000, 0x0);
halrf_wreg(rf, 0x7820, 0x80000000, 0x1);
halrf_wreg(rf, 0x78b4, 0x0000001f, 0x7);
for (i = 0; i < 300; i ++)
halrf_delay_us(rf, 10);
return halrf_rreg(rf, 0x3c00, 0x0003fe00);
}
}
void halrf_get_tssi_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len)
{
struct halrf_tssi_info *tssi_info = &rf->tssi;
u32 tmp, tmp1, pg_ther, cur_ther;
s32 delta_tssi;
s32 diff_ther;
s32 int_tmp[TSSI_PATH_MAX_8852B], float_tmp[TSSI_PATH_MAX_8852B];
s8 txagc_offset[TSSI_PATH_MAX_8852B] = {0};
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %x\n",
"RF Para Ver", halrf_rrf(rf, RF_PATH_A, 0x9f, 0xfff));
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = 0x%x / 0x%x\n",
"TSSI DCK A / B", halrf_rreg(rf, 0x1c04, 0x00FFF000),
halrf_rreg(rf, 0x3c04, 0x00FFF000));
tmp = halrf_rreg(rf, 0x1c78, 0x1ff);
tmp1 = halrf_rreg(rf, 0x3c78, 0x1ff);
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d.%d / %d.%d\n",
"T-MAC xdbm A / B",
tmp / 4, tmp * 100 / 4 % 100,
tmp1 / 4, tmp1 * 100 / 4 % 100);
halrf_wreg(rf, 0x58b4, 0x0000001f, 0x7);
tmp = halrf_rreg(rf, 0x1c00, 0x0ffc0000);
if (tmp & BIT(9))
delta_tssi = tmp | 0xfffffc00;
else
delta_tssi = tmp;
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d\n",
"TSSI C / Final / Delta A", halrf_rreg(rf, 0x1c00, 0x000001ff),
halrf_rreg(rf, 0x1c00, 0x0003fe00), delta_tssi);
halrf_wreg(rf, 0x78b4, 0x0000001f, 0x7);
tmp = halrf_rreg(rf, 0x3c00, 0x0ffc0000);
if (tmp & BIT(9))
delta_tssi = tmp | 0xfffffc00;
else
delta_tssi = tmp;
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d\n",
"TSSI C / Final / Delta B", halrf_rreg(rf, 0x1c00, 0x000001ff),
halrf_rreg(rf, 0x1c00, 0x0003fe00), delta_tssi);
pg_ther = halrf_rreg(rf, 0x5810, 0x0000fc00);
cur_ther = halrf_rreg(rf, 0x1c10, 0xff000000);
diff_ther = pg_ther - cur_ther;
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d / %d\n",
"TherA PG / Cur / Diff / F", ((tssi_info->thermal[RF_PATH_A] == 0xff) ? 0xff : pg_ther),
cur_ther, diff_ther,
(s8)halrf_rreg(rf, 0x1c08, 0xff000000));
pg_ther = halrf_rreg(rf, 0x7810, 0x0000fc00);
cur_ther = halrf_rreg(rf, 0x3c10, 0xff000000);
diff_ther = pg_ther - cur_ther;
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %d / %d / %d / %d\n",
"TherB PG / Cur / Diff / F", ((tssi_info->thermal[RF_PATH_B] == 0xff) ? 0xff : pg_ther),
cur_ther, diff_ther,
(s8)halrf_rreg(rf, 0x3c08, 0xff000000));
txagc_offset[RF_PATH_A] = (s8)halrf_rreg(rf, 0x1c60, 0xff000000);
txagc_offset[RF_PATH_B] = (s8)halrf_rreg(rf, 0x3c60, 0xff000000);
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = 0x%x (%d) / 0x%x (%d)\n",
"TXAGC Offset A / B",
(txagc_offset[RF_PATH_A] & 0xff), txagc_offset[RF_PATH_A],
(txagc_offset[RF_PATH_B] & 0xff), txagc_offset[RF_PATH_B]);
int_tmp[RF_PATH_A] = txagc_offset[RF_PATH_A] * 125 / 1000;
float_tmp[RF_PATH_A] = txagc_offset[RF_PATH_A] * 125 % 1000;
float_tmp[RF_PATH_A] < 0 ? float_tmp[RF_PATH_A] = float_tmp[RF_PATH_A] * -1 : 0;
int_tmp[RF_PATH_B] = txagc_offset[RF_PATH_B] * 125 / 1000;
float_tmp[RF_PATH_B] = txagc_offset[RF_PATH_B] * 125 % 1000;
float_tmp[RF_PATH_B] < 0 ? float_tmp[RF_PATH_B] = float_tmp[RF_PATH_B] * -1 : 0;
RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used, " %-25s = %s%d.%ddB / %s%d.%ddB\n",
"TXAGC Offset dB A / B",
(int_tmp[RF_PATH_A] == 0 && txagc_offset[RF_PATH_A] < 0) ? "-" : "",
int_tmp[RF_PATH_A], float_tmp[RF_PATH_A],
(int_tmp[RF_PATH_B] == 0 && txagc_offset[RF_PATH_B] < 0) ? "-" : "",
int_tmp[RF_PATH_B], float_tmp[RF_PATH_B]);
}
#endif /*RF_8852B_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.c
|
C
|
agpl-3.0
| 95,917
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_TSSI_8852B_H_
#define _HALRF_TSSI_8852B_H_
#ifdef RF_8852B_SUPPORT
#define TSSI_VER_8852B 0x18
#define TSSI_PATH_MAX_8852B 2
/*@--------------------------Define Parameters-------------------------------*/
/*@-----------------------End Define Parameters-----------------------*/
void halrf_tssi_get_efuse_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
bool halrf_tssi_check_efuse_data_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
void halrf_set_tssi_de_for_tx_verify_8852b(struct rf_info *rf,
enum phl_phy_idx phy, u32 tssi_de, u8 path);
void halrf_set_tssi_de_offset_8852b(struct rf_info *rf,
enum phl_phy_idx phy, u32 tssi_de_offset, u8 path);
void halrf_set_tssi_de_offset_zero_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
void halrf_do_tssi_8852b(struct rf_info *rf, enum phl_phy_idx phy);
void halrf_do_tssi_scan_8852b(struct rf_info *rf, enum phl_phy_idx phy);
void halrf_tssi_enable_8852b(struct rf_info *rf, enum phl_phy_idx phy);
void halrf_tssi_disable_8852b(struct rf_info *rf, enum phl_phy_idx phy);
s32 halrf_get_online_tssi_de_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
u8 path, s32 dbm, s32 puot);
void halrf_tssi_cck_8852b(struct rf_info *rf, enum phl_phy_idx phy,
bool is_cck);
void halrf_set_tssi_avg_mp_8852b(struct rf_info *rf,
enum phl_phy_idx phy_idx, s32 xdbm);
void halrf_tssi_set_efuse_to_de_8852b(struct rf_info *rf,
enum phl_phy_idx phy);
void halrf_tssi_default_txagc_8852b(struct rf_info *rf,
enum phl_phy_idx phy, bool enable);
void halrf_tssi_scan_ch_8852b(struct rf_info *rf, enum rf_path path);
void halrf_tssi_backup_txagc_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool enable);
u32 halrf_tssi_get_final_8852b(struct rf_info *rf, enum rf_path path);
void halrf_get_tssi_info_8852b(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
#endif
#endif /*_HALRF_SET_PWR_TABLE_8852B_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_tssi_8852b.h
|
C
|
agpl-3.0
| 2,592
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halrf_precomp.h"
#ifdef RF_8852B_SUPPORT
void _txgapk_backup_bb_registers_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
u32 *reg,
u32 *reg_backup,
u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++) {
reg_backup[i] = halrf_rreg(rf, reg[i], MASKDWORD);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
reg[i], reg_backup[i]);
}
}
void _txgapk_reload_bb_registers_8852b(
struct rf_info *rf,
enum phl_phy_idx phy,
u32 *reg,
u32 *reg_backup,
u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++) {
halrf_wreg(rf, reg[i], MASKDWORD, reg_backup[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
reg[i], reg_backup[i]);
}
}
void _halrf_txgapk_bkup_rf_8852b(
struct rf_info *rf,
u32 *rf_reg,
u32 rf_bkup[][TXGAPK_RF_REG_NUM_8852B],
u8 path)
{
u8 i;
for (i = 0; i < TXGAPK_RF_REG_NUM_8852B; i++) {
rf_bkup[path][i] = halrf_rrf(rf, path, rf_reg[i], MASKRF);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Backup RF S%d 0x%x = %x\n",
path, rf_reg[i], rf_bkup[path][i]);
}
}
void _halrf_txgapk_reload_rf_8852b(
struct rf_info *rf,
u32 *rf_reg,
u32 rf_bkup[][TXGAPK_RF_REG_NUM_8852B],
u8 path)
{
u8 i;
for (i = 0; i < TXGAPK_RF_REG_NUM_8852B; i++) {
halrf_wrf(rf, path, rf_reg[i], MASKRF, rf_bkup[path][i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] Reload RF S%d 0x%x = %x\n",
path, rf_reg[i], rf_bkup[path][i]);
}
}
void _halrf_txgapk_bb_afe_by_mode_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path, bool is_dbcc)
{
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
if (!is_dbcc) {
/* nodbcc */
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303);
halrf_wreg(rf, 0x5864, 0x18000000, 0x3);
halrf_wreg(rf, 0x7864, 0x18000000, 0x3);
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
halrf_wreg(rf, 0x12b8, 0x10000000, 0x1);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x1);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x1);
halrf_wreg(rf, 0x5864, 0xc0000000, 0x3);
halrf_wreg(rf, 0x7864, 0xc0000000, 0x3);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff);
halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1);
halrf_wreg(rf, 0x0700, 0x08000000, 0x1);
halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff);
halrf_wreg(rf, 0x0c60, 0x00000003, 0x3);
halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1);
halrf_wreg(rf, 0x58ac, 0x08000000, 0x1);
halrf_wreg(rf, 0x78ac, 0x08000000, 0x1);
#ifdef CF_PHL_BB_CTRL_RX_CCA
halrf_bb_ctrl_rx_cca(rf, false, phy);
#else
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1);
halrf_wreg(rf, 0x2344, 0x80000000, 0x1);
halrf_wreg(rf, 0x0704, BIT(1), 0x0); /*bb rst*/
halrf_wreg(rf, 0x0704, BIT(1), 0x1);
halrf_delay_us(rf, 1);
#endif
halrf_wreg(rf, 0x4490, 0x80000000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00007000, 0x7);
halrf_wreg(rf, 0x12a0, 0x00008000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00070000, 0x3);
halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00070000, 0x3);
halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
halrf_wreg(rf, 0x0700, 0x06000000, 0x2);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x3333);
} else {
if (phy == HW_PHY_0) {
/* dbcc phy0 path 0 */
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0101);
halrf_wreg(rf, 0x5864, 0x18000000, 0x3);
halrf_wreg(rf, 0x7864, 0x18000000, 0x3);
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
halrf_wreg(rf, 0x12b8, 0x10000000, 0x1);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x1);
halrf_wreg(rf, 0x5864, 0xc0000000, 0x3);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff);
halrf_wreg(rf, 0x0c1c, 0x00000004, 0x1);
halrf_wreg(rf, 0x0700, 0x08000000, 0x1);
halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff);
halrf_wreg(rf, 0x0c60, 0x00000003, 0x3);
halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1);
halrf_wreg(rf, 0x58ac, 0x08000000, 0x1);
#ifdef CF_PHL_BB_CTRL_RX_CCA
halrf_bb_ctrl_rx_cca(rf, false, phy);
#else
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x1);
/* halrf_wreg(rf, 0x2344, 0x80000000, 0x1); */
if (halrf_rreg(rf, 0x4970, BIT(1)) == 0x0) /*CCK @PHY0*/
halrf_wreg(rf, 0x2344, BIT(31), 0x1); /*block CCK CCA*/
halrf_wreg(rf, 0x0704, BIT(1), 0x0); /*bb rst*/
halrf_wreg(rf, 0x0704, BIT(1), 0x1);
halrf_delay_us(rf, 1);
#endif
halrf_wreg(rf, 0x4490, 0x80000000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00007000, 0x7);
halrf_wreg(rf, 0x12a0, 0x00008000, 0x1);
halrf_wreg(rf, 0x12a0, 0x00070000, 0x3);
halrf_wreg(rf, 0x12a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x0700, 0x01000000, 0x1);
halrf_wreg(rf, 0x0700, 0x06000000, 0x2);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x1111);
} else if (phy == HW_PHY_1) {
/* dbcc phy1 path 1 */
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0202);
halrf_wreg(rf, 0x7864, 0x18000000, 0x3);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
halrf_wreg(rf, 0x32b8, 0x10000000, 0x1);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x1);
halrf_wreg(rf, 0x7864, 0xc0000000, 0x3);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x1ffffff);
halrf_wreg(rf, 0x2c1c, 0x00000004, 0x1);
halrf_wreg(rf, 0x2700, 0x08000000, 0x1);
halrf_wreg(rf, 0x0c70, 0x000003ff, 0x3ff);
halrf_wreg(rf, 0x0c60, 0x00000003, 0x3);
halrf_wreg(rf, 0x0c6c, 0x00000001, 0x1);
halrf_wreg(rf, 0x78ac, 0x08000000, 0x1);
#ifdef CF_PHL_BB_CTRL_RX_CCA
halrf_bb_ctrl_rx_cca(rf, false, phy);
#else
halrf_wreg(rf, 0x2c3c, 0x00000200, 0x1);
if (halrf_rreg(rf, 0x4970, BIT(1)) == 0x1) /*CCK @PHY1*/
halrf_wreg(rf, 0x2344, BIT(31), 0x1); /*block CCK CCA*/
halrf_wreg(rf, 0x2704, BIT(1), 0x0); /*bb rst*/
halrf_wreg(rf, 0x2704, BIT(1), 0x1);
halrf_delay_us(rf, 1);
#endif
halrf_wreg(rf, 0x6490, 0x80000000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00007000, 0x7);
halrf_wreg(rf, 0x32a0, 0x00008000, 0x1);
halrf_wreg(rf, 0x32a0, 0x00070000, 0x3);
halrf_wreg(rf, 0x32a0, 0x00080000, 0x1);
halrf_wreg(rf, 0x2700, 0x01000000, 0x1);
halrf_wreg(rf, 0x2700, 0x06000000, 0x2);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x2222);
}
}
}
void _halrf_txgapk_iqk_preset_by_mode_8852b(struct rf_info *rf,
enum phl_phy_idx phy, enum rf_path path, bool is_dbcc)
{
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
if (!is_dbcc) {
/* nodbcc */
halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0);
halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0);
/* D-Die BB_Direct_SEL */
halrf_wrf(rf, RF_PATH_A, 0x10005, 0x00001, 0x0);
halrf_wrf(rf, RF_PATH_B, 0x10005, 0x00001, 0x0);
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080);
halrf_wreg(rf, 0x8088, MASKDWORD, 0x81ff010a);
} else {
/* dbcc */
if (phy == HW_PHY_0)
halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x0);
else if (phy == HW_PHY_1)
halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x0);
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000080);
halrf_wreg(rf, 0x8080, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x8088, MASKDWORD, 0x83ff010a);
halrf_wreg(rf, 0x80d0, MASKDWORD, 0x00200000);
halrf_wreg(rf, 0x8074, MASKDWORD, 0x80000000);
if (phy == HW_PHY_0)
halrf_wreg(rf, 0x81dc, MASKDWORD, 0x00000000);
else if (phy == HW_PHY_1)
halrf_wreg(rf, 0x82dc, MASKDWORD, 0x00000000);
}
}
void _halrf_txgapk_clk_setting_dac960mhz_by_mode_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_dbcc)
{
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
if (!is_dbcc) {
/* nodbcc */
halrf_wreg(rf, 0x12b8, 0x40000000, 0x1);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x1);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x1f);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x030c, 0xff000000, 0x13);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0001);
halrf_delay_us(rf, 1);
halrf_wreg(rf, 0x032c, 0xffff0000, 0x0041);
} else {
/* dbcc */
if (phy == HW_PHY_0)
halrf_wreg(rf, 0x8120, MASKDWORD, 0xce000a08);
else if (phy == HW_PHY_1)
halrf_wreg(rf, 0x8220, MASKDWORD, 0xce000a08);
}
}
void _halrf_txgapk_before_one_shot_enable_8852b
(struct rf_info *rf)
{
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
/* set 0x80d4[21:16]=0x03 (before oneshot NCTL) to get report later */
halrf_wreg(rf, 0x80d4, 0x003F0000, 0x03);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> before set one-shot bit, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD));
}
void _halrf_txgapk_one_shot_nctl_done_check_8852b
(struct rf_info *rf, enum txgapk_id id, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
/* for check status */
u32 r_bff8 = 0;
u32 r_80fc = 0;
bool is_ready = false;
u16 count = 1;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
/* for 0xbff8 check NCTL DONE */
while (count < 2000) {
r_bff8 = halrf_rreg(rf, 0xbff8, MASKBYTE0);
if (r_bff8 == 0x55) {
is_ready = true;
break;
}
/* r_bff8 = 0; */
halrf_delay_us(rf, 10);
count++;
}
halrf_delay_us(rf, 1);
txgapk_info->txgapk_chk_cnt[path][id][0] = count;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> check 0xBFF8[7:0] = 0x%x, IsReady = %d, ReadTimes = %d,delay 1 us\n", r_bff8, is_ready, count);
/* for 0x80fc check NCTL DONE */
count = 1;
is_ready = false;
while (count < 2000) {
r_80fc = halrf_rreg(rf, 0x80fc, MASKLWORD);
if (r_80fc == 0x8000) {
is_ready = true;
break;
}
/* r_80fc = 0; */
halrf_delay_us(rf, 1);
count++;
}
halrf_delay_us(rf, 1);
txgapk_info->txgapk_chk_cnt[path][id][1] = count;
halrf_wreg(rf, 0x8010, 0x000000ff, 0x00);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> check 0x80fc[15:0] = 0x%x, IsReady = %d, ReadTimes = %d, 0x%x= 0x%x \n", r_80fc, is_ready, count, 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD) );
}
void _halrf_txgapk_track_table_nctl_2g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 i;
u32 d[17] = {0}, ta[17] = {0};
u32 itqt[2] = {0x81cc, 0x82cc};
u32 gapk_on_table0_setting[2] = {0x8158, 0x8258};
u32 cal_path[2] = {0x00002019, 0x00002029};
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, path = %d\n", __func__, path);
halrf_wrf(rf, path, 0x00, MASKRF, 0x503e0);
halrf_wrf(rf, path, 0xdf, 0x01000, 0x1);
halrf_wrf(rf, path, 0x9e, 0x00100, 0x1);
halrf_wrf(rf, path, 0x83, 0x00007, 0x2);
halrf_wrf(rf, path, 0x83, 0x000f0, 0xf);
halrf_wreg(rf, itqt[path], 0x0000003f, 0x3f);
#if 0
halrf_wrf(rf, path, 0x94, 0x003fc, 0x7f);
halrf_wrf(rf, path, 0x93, 0x00008, 0x0);
halrf_wrf(rf, path, 0x92, 0x00001, 0x0);
halrf_wrf(rf, path, 0x92, 0x00001, 0x1);
for (i = 0; i < 100; i++)
halrf_delay_us(rf, 1);
#else
halrf_set_rx_dck_8852b(rf, phy, path, false);
#endif
halrf_wrf(rf, path, 0x92, 0x00001, 0x0);
for (i = 0; i < 100; i++)
halrf_delay_us(rf, 1);
halrf_wrf(rf, path, 0x1005e, MASKRF, 0xc0000);
halrf_wreg(rf, 0x801c, 0x000e0000, 0x2);
halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f);
halrf_wreg(rf, 0x80e0, 0x0000f000, 0x0);
halrf_wreg(rf, 0x8038, 0x003f0000, 0x24);
halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x001554);
halrf_wreg(rf, 0x5864, 0x20000000, 0x1);
halrf_wreg(rf, itqt[path], 0x0000003f, 0x1b);
halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009);
_halrf_txgapk_before_one_shot_enable_8852b(rf);
halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]);
_halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_TRACK, path);
halrf_wreg(rf, 0x5864, 0x20000000, 0x0);
halrf_wrf(rf, path, 0x1005e, MASKRF, 0x0);
/* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3);
d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4);
d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5);
d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6);
d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7);
d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9);
ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa);
ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb);
ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc);
ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd);
ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff);
/* for debug */
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x007f0000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, itqt[path], MASKDWORD, 0x09);
halrf_wreg(rf, 0x80d0, 0x00100000, 0x1);
for (i = 0; i < 17; i++) {
if (d[i] & BIT(6))
txgapk_info->track_d[path][i] = (s32)(d[i] | 0xffffff80);
else
txgapk_info->track_d[path][i] = (s32)(d[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track d[%d][%d]=0x%x\n",
path, i, txgapk_info->track_d[path][i]);
}
for (i = 0; i < 17; i++) {
if (ta[i] & BIT(7))
txgapk_info->track_ta[path][i] = (s32)(ta[i] | 0xffffff00);
else
txgapk_info->track_ta[path][i] = (s32)(ta[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track ta[%d][%d]=0x%x\n",
path, i, txgapk_info->track_ta[path][i]);
}
}
void _halrf_txgapk_track_table_nctl_5g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 i;
u32 d[17] = {0}, ta[17] = {0};
u32 itqt[2] = {0x81cc, 0x82cc};
u32 gapk_on_table0_setting[2] = {0x8158, 0x8258};
u32 cal_path[2] = {0x00002019, 0x00002029};
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, path = %d\n", __func__, path);
halrf_wrf(rf, path, 0x00, MASKRF, 0x503e0);
halrf_wrf(rf, path, 0xdf, 0x01000, 0x1);
halrf_wrf(rf, path, 0x9e, 0x00100, 0x1);
halrf_wrf(rf, path, 0x8c, 0x0e000, 0x0);
halrf_wrf(rf, path, 0x8c, 0x01800, 0x3);
halrf_wrf(rf, path, 0x8c, 0x00600, 0x1);
halrf_wreg(rf, itqt[path], 0x0000003f, 0x3f);
#if 0
halrf_wrf(rf, path, 0x94, 0x003fc, 0x7f);
halrf_wrf(rf, path, 0x93, 0x00008, 0x0);
halrf_wrf(rf, path, 0x92, 0x00001, 0x0);
halrf_wrf(rf, path, 0x92, 0x00001, 0x1);
for (i = 0; i < 100; i++)
halrf_delay_us(rf, 1);
#else
halrf_set_rx_dck_8852b(rf, phy, path, false);
#endif
halrf_wrf(rf, path, 0x92, 0x00001, 0x0);
for (i = 0; i < 100; i++)
halrf_delay_us(rf, 1);
halrf_wrf(rf, path, 0x1005e, MASKRF, 0xc0000);
halrf_wreg(rf, 0x801c, 0x000e0000, 0x2);
halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f);
halrf_wreg(rf, 0x80e0, 0x0000f000, 0x0);
halrf_wreg(rf, 0x8038, 0x003f0000, 0x24);
halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x003550);
halrf_wreg(rf, 0x5864, 0x20000000, 0x1);
halrf_wreg(rf, itqt[path], 0x0000003f, 0x24);
halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009);
_halrf_txgapk_before_one_shot_enable_8852b(rf);
halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]);
_halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_TRACK, path);
halrf_wreg(rf, 0x5864, 0x20000000, 0x0);
halrf_wrf(rf, path, 0x1005e, MASKRF, 0x0);
/* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3);
d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4);
d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5);
d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6);
d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7);
d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9);
ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa);
ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb);
ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc);
ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd);
ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff);
/* debug */
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x007f0000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, itqt[path], MASKDWORD, 0x09);
halrf_wreg(rf, 0x80d0, 0x00100000, 0x1);
for (i = 0; i < 17; i++) {
if (d[i] & BIT(6))
txgapk_info->track_d[path][i] = (s32)(d[i] | 0xffffff80);
else
txgapk_info->track_d[path][i] = (s32)(d[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track d[%d][%d]=0x%x\n",
path, i, txgapk_info->track_d[path][i]);
}
for (i = 0; i < 17; i++) {
if (ta[i] & BIT(7))
txgapk_info->track_ta[path][i] = (s32)(ta[i] | 0xffffff00);
else
txgapk_info->track_ta[path][i] = (s32)(ta[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] track ta[%d][%d]=0x%x\n",
path, i, txgapk_info->track_ta[path][i]);
}
}
void _halrf_txgapk_track_table_nctl_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
if (channel >= 1 && channel <= 14)
_halrf_txgapk_track_table_nctl_2g_8852b(rf, phy, path);
else
_halrf_txgapk_track_table_nctl_5g_8852b(rf, phy, path);
}
void _halrf_txgapk_write_track_table_default_2g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_default_5gl_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_default_5gm_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_default_5gh_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x0|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x1|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x2|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x3|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x4|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, (0x5|bias));
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x3f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_default_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
if (channel >= 1 && channel <= 14)
_halrf_txgapk_write_track_table_default_2g_8852b(rf, phy, path);
else if (channel >= 36 && channel <= 64)
_halrf_txgapk_write_track_table_default_5gl_8852b(rf, phy, path);
else if (channel >= 100 && channel <= 144)
_halrf_txgapk_write_track_table_default_5gm_8852b(rf, phy, path);
else if (channel >= 149 && channel <= 177)
_halrf_txgapk_write_track_table_default_5gh_8852b(rf, phy, path);
}
void _halrf_txgapk_write_track_table_2g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
u8 pa_change[6] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
if (rfe_type <= 50) {
/* NIC */
/* AP iFEM */
pa_change[0] = 2;
pa_change[1] = 4;
pa_change[2] = 6;
pa_change[3] = 8;
pa_change[4] = 10;
pa_change[5] = 12;
}
else {
/* AP eFEM */
pa_change[0] = 1;
pa_change[1] = 3;
pa_change[2] = 5;
pa_change[3] = 7;
pa_change[4] = 9;
pa_change[5] = 11;
}
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_5gl_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 pa_change[6] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
pa_change[0] = 4;
pa_change[1] = 6;
pa_change[2] = 8;
pa_change[3] = 10;
pa_change[4] = 12;
pa_change[5] = 13;
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_5gm_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 pa_change[6] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
pa_change[0] = 4;
pa_change[1] = 6;
pa_change[2] = 8;
pa_change[3] = 10;
pa_change[4] = 12;
pa_change[5] = 13;
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_5gh_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 pa_change[6] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 8;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
pa_change[0] = 4;
pa_change[1] = 6;
pa_change[2] = 8;
pa_change[3] = 10;
pa_change[4] = 12;
pa_change[5] = 13;
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[2]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x3|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[3]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x4|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[4]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x0f, 0x5|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->track_ta[path][pa_change[5]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x08000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_track_table_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
if (channel >= 1 && channel <= 14)
_halrf_txgapk_write_track_table_2g_8852b(rf, phy, path);
else if (channel >= 36 && channel <= 64)
_halrf_txgapk_write_track_table_5gl_8852b(rf, phy, path);
else if (channel >= 100 && channel <= 144)
_halrf_txgapk_write_track_table_5gm_8852b(rf, phy, path);
else if (channel >= 149 && channel <= 177)
_halrf_txgapk_write_track_table_5gh_8852b(rf, phy, path);
}
void _halrf_txgapk_power_table_nctl_2g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
/* u8 rfe_type = rf->phl_com->dev_cap.rfe_type; */
u32 i;
u32 d[17] = {0}, ta[17] = {0};
u32 gapk_on_table0_setting[2] = {0x8170, 0x8270};
/* u32 path_setting[2] = {0x5864, 0x7864}; */
u32 itqt[2] = {0x81cc, 0x82cc};
u32 cal_path[2] = {0x00002119, 0x00002129};
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f);
halrf_wreg(rf, 0x8038, 0x003f0000, 0x24);
halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x000540);
halrf_wreg(rf, 0x5864, 0x20000000, 0x1);
halrf_wreg(rf, itqt[path], 0x0000003f, 0x24);
halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009);
_halrf_txgapk_before_one_shot_enable_8852b(rf);
halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]);
_halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_PWR, path);
halrf_wreg(rf, 0x5864, 0x20000000, 0x0);
/* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3);
d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4);
d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5);
d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6);
d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7);
d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9);
ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa);
ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb);
ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc);
ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd);
ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff);
/* debug */
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x007f0000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x801c, 0x000e0000, 0x0);
/* for debug */
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> afr restore 0x801c, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD));
halrf_wreg(rf, itqt[path], MASKDWORD, 0x1b);
halrf_wreg(rf, 0x80d0, 0x00100000, 0x1);
for (i = 0; i < 17; i++) {
if (d[i] & BIT(6))
txgapk_info->power_d[path][i] = (s32)(d[i] | 0xffffff80);
else
txgapk_info->power_d[path][i] = (s32)(d[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power d[%d][%d]=0x%x\n",
path, i, txgapk_info->power_d[path][i]);
}
for (i = 0; i < 17; i++) {
if (ta[i] & BIT(7))
txgapk_info->power_ta[path][i] = (s32)(ta[i] | 0xffffff00);
else
txgapk_info->power_ta[path][i] = (s32)(ta[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power ta[%d][%d]=0x%x\n",
path, i, txgapk_info->power_ta[path][i]);
}
}
void _halrf_txgapk_power_table_nctl_5g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
/* u8 rfe_type = rf->phl_com->dev_cap.rfe_type; */
u32 i;
u32 d[17] = {0}, ta[17] = {0};
u32 gapk_on_table0_setting[2] = {0x8170, 0x8270};
/* u32 path_setting[2] = {0x5864, 0x7864}; */
u32 itqt[2] = {0x81cc, 0x82cc};
u32 cal_path[2] = {0x00002119, 0x00002129};
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
halrf_wreg(rf, 0x80e0, 0x000001f0, 0x1f);
halrf_wreg(rf, 0x8038, 0x003f0000, 0x24);
halrf_wreg(rf, gapk_on_table0_setting[path], 0x001fffff, 0x000540);
halrf_wreg(rf, 0x5864, 0x20000000, 0x1);
halrf_wreg(rf, itqt[path], MASKDWORD, 0x24);
halrf_wreg(rf, 0x802c, 0x0fff0000, 0x009);
_halrf_txgapk_before_one_shot_enable_8852b(rf);
halrf_wreg(rf, 0x8000, MASKDWORD, cal_path[path]);
_halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_PWR, path);
halrf_wreg(rf, 0x5864, 0x20000000, 0x0);
/* ===== Read GapK Results, Bcut resolution = 0.0625 dB ===== */
halrf_wreg(rf, 0x80d4, MASKDWORD, 0x00130000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x3);
d[0] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[1] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[2] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[3] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x4);
d[4] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[5] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[6] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[7] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x5);
d[8] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[9] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[10] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[11] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x6);
d[12] = halrf_rreg(rf, 0x80fc, 0x0000007f);
d[13] = halrf_rreg(rf, 0x80fc, 0x00003f80);
d[14] = halrf_rreg(rf, 0x80fc, 0x001fc000);
d[15] = halrf_rreg(rf, 0x80fc, 0x0fe00000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x7);
d[16] = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x9);
ta[0] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[1] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[2] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[3] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xa);
ta[4] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[5] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[6] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[7] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xb);
ta[8] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[9] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[10] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[11] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xc);
ta[12] = halrf_rreg(rf, 0x80fc, 0x000000ff);
ta[13] = halrf_rreg(rf, 0x80fc, 0x0000ff00);
ta[14] = halrf_rreg(rf, 0x80fc, 0x00ff0000);
ta[15] = halrf_rreg(rf, 0x80fc, 0xff000000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xd);
ta[16] = halrf_rreg(rf, 0x80fc, 0x000000ff);
/* debug */
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x0000007f);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x0);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x2);
// = halrf_rreg(rf, 0x80fc, 0x007f0000);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0x1);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x80e4, 0x00000f00, 0xf);
// = halrf_rreg(rf, 0x80fc, MASKDWORD);
halrf_wreg(rf, 0x801c, 0x000e0000, 0x0);
/* for debug */
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> afr restore 0x801c, 0x%x= 0x%x\n", 0x8010, halrf_rreg(rf, 0x8010, MASKDWORD));
halrf_wreg(rf, itqt[path], MASKDWORD, 0x1b);
halrf_wreg(rf, 0x80d0, 0x00100000, 0x1);
for (i = 0; i < 17; i++) {
if (d[i] & BIT(6))
txgapk_info->power_d[path][i] = (s32)(d[i] | 0xffffff80);
else
txgapk_info->power_d[path][i] = (s32)(d[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power d[%d][%d]=0x%x\n",
path, i, txgapk_info->power_d[path][i]);
}
for (i = 0; i < 17; i++) {
if (ta[i] & BIT(7))
txgapk_info->power_ta[path][i] = (s32)(ta[i] | 0xffffff00);
else
txgapk_info->power_ta[path][i] = (s32)(ta[i]);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] power ta[%d][%d]=0x%x\n",
path, i, txgapk_info->power_ta[path][i]);
}
}
void _halrf_txgapk_power_table_nctl_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
if (channel >= 1 && channel <= 14)
_halrf_txgapk_power_table_nctl_2g_8852b(rf, phy, path);
else
_halrf_txgapk_power_table_nctl_5g_8852b(rf, phy, path);
}
void _halrf_txgapk_write_power_table_default_2g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_default_5gl_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_default_5gm_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_default_5gh_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
/* NIC */
/* AP iFEM */
/* AP eFEM */
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, 0x0);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_default_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
if (channel >= 1 && channel <= 14)
_halrf_txgapk_write_power_table_default_2g_8852b(rf, phy, path);
else if (channel >= 36 && channel <= 64)
_halrf_txgapk_write_power_table_default_5gl_8852b(rf, phy, path);
else if (channel >= 100 && channel <= 144)
_halrf_txgapk_write_power_table_default_5gm_8852b(rf, phy, path);
else if (channel >= 149 && channel <= 177)
_halrf_txgapk_write_power_table_default_5gh_8852b(rf, phy, path);
}
void _halrf_txgapk_write_power_table_2g_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
u8 pa_change[3] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
if (rfe_type <= 50) {
/* NIC */
/* AP iFEM */
pa_change[0] = 6;
pa_change[1] = 8;
pa_change[2] = 10;
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
}
else {
/* AP eFEM */
pa_change[0] = 14;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x1);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
}
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_5gl_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
u8 pa_change[3] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
if (rfe_type < 50) {
/* NIC */
pa_change[0] = 6;
pa_change[1] = 8;
pa_change[2] = 10;
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
} else if (rfe_type == 50) {
/* AP iFEM */
pa_change[0] = 6;
pa_change[1] = 9;
pa_change[2] = 10;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x21);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, 0x33, 0x01fff, 0x23);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, 0x33, 0x01fff, 0x26);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
} else {
/* AP eFEM */
pa_change[0] = 14;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x21);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
}
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_5gm_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
u8 pa_change[3] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
if (rfe_type < 50) {
/* NIC */
pa_change[0] = 6;
pa_change[1] = 8;
pa_change[2] = 10;
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
} else if (rfe_type == 50) {
/* AP iFEM */
pa_change[0] = 6;
pa_change[1] = 9;
pa_change[2] = 10;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x29);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, 0x33, 0x01fff, 0x2b);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, 0x33, 0x01fff, 0x2e);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
} else {
/* AP eFEM */
pa_change[0] = 14;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x29);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
}
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_5gh_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
u8 pa_change[3] = {0};
u32 bias = 0;
/* table1 */
if (txgapk_info->txgapk_table_idx == 1)
bias = 4;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s, table index = %d, addr_bias = %d\n", __func__, txgapk_info->txgapk_table_idx, bias);
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x1); /* enter debug mode before write */
if (rfe_type < 50) {
/* NIC */
pa_change[0] = 6;
pa_change[1] = 8;
pa_change[2] = 10;
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x0|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x1|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, TXGAP_TB_ADDR_8852B, 0x07, 0x2|bias);
halrf_wrf(rf, path, TXGAP_TB_VAL_8852B, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
} else if (rfe_type == 50) {
/* AP iFEM */
pa_change[0] = 6;
pa_change[1] = 9;
pa_change[2] = 10;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x31);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
halrf_wrf(rf, path, 0x33, 0x01fff, 0x33);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[1]] / 2) & 0x3f);
halrf_wrf(rf, path, 0x33, 0x01fff, 0x36);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[2]] / 2) & 0x3f);
} else {
/* AP eFEM */
pa_change[0] = 14;
halrf_wrf(rf, path, 0x33, 0x01fff, 0x31);
halrf_wrf(rf, path, 0x3f, 0x0003f, (txgapk_info->power_ta[path][pa_change[0]] / 2) & 0x3f);
}
halrf_wrf(rf, path, TXGAPK_DEBUGMASK_8852B, 0x40000, 0x0); /* exit debug mode after write */
}
void _halrf_txgapk_write_power_table_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path)
{
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
if (channel >= 1 && channel <= 14)
_halrf_txgapk_write_power_table_2g_8852b(rf, phy, path);
else if (channel >= 36 && channel <= 64)
_halrf_txgapk_write_power_table_5gl_8852b(rf, phy, path);
else if (channel >= 100 && channel <= 144)
_halrf_txgapk_write_power_table_5gm_8852b(rf, phy, path);
else if (channel >= 149 && channel <= 177)
_halrf_txgapk_write_power_table_5gh_8852b(rf, phy, path);
}
void _halrf_txgapk_iqk_bk_reg_by_mode_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_dbcc)
{
u32 path_setting[2] = {0x0e19, 0x0e29};
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
if (!is_dbcc) {
/* no dbcc */
_halrf_txgapk_before_one_shot_enable_8852b(rf);
halrf_wreg(rf, 0x8000, MASKDWORD, path_setting[path]);
_halrf_txgapk_one_shot_nctl_done_check_8852b(rf, TXGAPK_IQKBK, path);
halrf_wreg(rf, 0x8008, MASKDWORD, 0x00000000);
halrf_wreg(rf, 0x8088, MASKDWORD, 0x80000000);
} else {
/* dbcc */
if (phy == HW_PHY_0) {
halrf_wreg(rf, 0x8120, MASKDWORD, 0x10010000);
halrf_wreg(rf, 0x8140, 0x00000100, 0x0);
halrf_wreg(rf, 0x8150, MASKDWORD, 0xe4e4e4e4);
halrf_wreg(rf, 0x8154, 0x00000100, 0x0);
halrf_wreg(rf, 0x81cc, 0x0000003f, 0x0);
halrf_wreg(rf, 0x81dc, MASKDWORD, 0x00000002);
} else if (phy == HW_PHY_1) {
halrf_wreg(rf, 0x8220, MASKDWORD, 0x10010000);
halrf_wreg(rf, 0x8240, 0x00000100, 0x0);
halrf_wreg(rf, 0x8250, MASKDWORD, 0xe4e4e4e4);
halrf_wreg(rf, 0x8254, 0x00000100, 0x0);
halrf_wreg(rf, 0x82cc, 0x0000003f, 0x0);
halrf_wreg(rf, 0x82dc, MASKDWORD, 0x00000002);
}
}
halrf_wrf(rf, path, 0xef, 0x00004, 0x0);
halrf_wrf(rf, path, 0x0, 0xf0000, 0x3);
halrf_wrf(rf, RF_PATH_A, 0x5, 0x00001, 0x1);
halrf_wrf(rf, RF_PATH_B, 0x5, 0x00001, 0x1);
halrf_wrf(rf, RF_PATH_A, 0x10005, 0x00001, 0x1);
halrf_wrf(rf, RF_PATH_B, 0x10005, 0x00001, 0x1);
}
void _halrf_txgapk_afe_bk_reg_by_mode_8852b
(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_dbcc)
{
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s\n", __func__);
if (!is_dbcc) {
/* no dbcc */
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0303);
halrf_wreg(rf, 0x12b8, 0x40000000, 0x0);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x0);
halrf_wreg(rf, 0x5864, 0xc0000000, 0x0);
halrf_wreg(rf, 0x7864, 0xc0000000, 0x0);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000);
halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0);
halrf_wreg(rf, 0x0700, 0x08000000, 0x0);
halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03);
halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03);
halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00);
halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00);
halrf_wreg(rf, 0x0700, 0x07000000, 0x0);
#if 1 /* jerry recommand to fix */
/* halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); */
halrf_wreg(rf, 0x2344, 0x80000000, 0x0);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x0);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x0);
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0); /* block OFDM CCK */
#else /* default */
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0);
halrf_wreg(rf, 0x2344, 0x80000000, 0x0);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x0);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x0);
#endif
} else {
/* dbcc */
if (phy == HW_PHY_0) {
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0101);
halrf_wreg(rf, 0x12b8, 0x40000000, 0x0);
halrf_wreg(rf, 0x5864, 0xc0000000, 0x0);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000);
halrf_wreg(rf, 0x0c1c, 0x00000004, 0x0);
halrf_wreg(rf, 0x0700, 0x08000000, 0x0);
halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03);
halrf_wreg(rf, 0x0c70, 0x000003e0, 0x03);
halrf_wreg(rf, 0x12a0, 0x000ff000, 0x00);
halrf_wreg(rf, 0x0700, 0x07000000, 0x0);
halrf_wreg(rf, 0x0c3c, 0x00000200, 0x0);
halrf_wreg(rf, 0x2344, 0x80000000, 0x0);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000);
halrf_wreg(rf, 0x58c8, 0x01000000, 0x0);
} else if (phy == HW_PHY_1) {
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0202);
halrf_wreg(rf, 0x32b8, 0x40000000, 0x0);
halrf_wreg(rf, 0x7864, 0xc0000000, 0x0);
halrf_wreg(rf, 0x2008, 0x01ffffff, 0x0000000);
halrf_wreg(rf, 0x2c1c, 0x00000004, 0x0);
halrf_wreg(rf, 0x2700, 0x08000000, 0x0);
halrf_wreg(rf, 0x0cf0, 0x000001ff, 0x000);
halrf_wreg(rf, 0x32a0, 0x000ff000, 0x00);
halrf_wreg(rf, 0x2700, 0x07000000, 0x0);
halrf_wreg(rf, 0x2c3c, 0x00000200, 0x0);
halrf_wreg(rf, 0x20fc, 0xffff0000, 0x0000);
halrf_wreg(rf, 0x78c8, 0x01000000, 0x0);
halrf_wreg(rf, 0x0c70, 0x0000001f, 0x03);
}
}
}
void _halrf_do_non_dbcc_txgapk_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u8 i;
u32 bb_reg[1] = {0x2344};
u32 bb_reg_backup[1] = {0};
u32 backup_num = 1;
u32 rf_3wire_a_die[2] = {0};
u32 rf_3wire_d_die[2] = {0};
u32 rf_bkup[TXGAPK_RF_PATH_MAX_8852B][TXGAPK_RF_REG_NUM_8852B] = {{0}};
u32 rf_reg[TXGAPK_RF_REG_NUM_8852B] = {0xdf};
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy);
_txgapk_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
for (i = 0; i < TXGAPK_RF_PATH_MAX_8852B; i++) {
_halrf_txgapk_bkup_rf_8852b(rf, rf_reg, rf_bkup, i);
}
/*rf_0[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x0, 0xfffff);*/
/*rf_0[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x0, 0xfffff);*/
rf_3wire_a_die[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x5, 0xfffff);
rf_3wire_a_die[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x5, 0xfffff);
rf_3wire_d_die[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x10005, 0xfffff);
rf_3wire_d_die[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x10005, 0xfffff);
/*halrf_wrf(rf, RF_PATH_A, 0x0, 0x00001, 0x1);*/
/*halrf_wrf(rf, RF_PATH_B, 0x0, 0x00001, 0x1);*/
for (i = 0; i < 2; i++) {
/*_halrf_txgapk_iqk_dpk_init_reg_8852b(rf, phy, RF_PATH_A);*/
/*_halrf_txgapk_nctl_8852b(rf, phy, RF_PATH_A);*/
_halrf_txgapk_write_track_table_default_8852b(rf, phy, i);
_halrf_txgapk_write_power_table_default_8852b(rf, phy, i);
_halrf_txgapk_bb_afe_by_mode_8852b(rf, phy, i, false);
_halrf_txgapk_iqk_preset_by_mode_8852b(rf, phy, i, false);
_halrf_txgapk_clk_setting_dac960mhz_by_mode_8852b(rf, phy, i, false);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START);
halrf_tmac_tx_pause(rf, phy, true);
_halrf_txgapk_track_table_nctl_8852b(rf, phy, i);
_halrf_txgapk_write_track_table_8852b(rf, phy, i);
_halrf_txgapk_power_table_nctl_8852b(rf, phy, i);
_halrf_txgapk_write_power_table_8852b(rf, phy, i);
halrf_tmac_tx_pause(rf, phy, false);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP);
_halrf_txgapk_iqk_bk_reg_by_mode_8852b(rf, phy, i, false);
_halrf_txgapk_afe_bk_reg_by_mode_8852b(rf, phy, i, false);
}
/*halrf_wrf(rf, RF_PATH_A, 0x0, 0x00001, rf_0[RF_PATH_A]);*/
/*halrf_wrf(rf, RF_PATH_B, 0x0, 0x00001, rf_0[RF_PATH_B]);*/
for (i = 0; i < TXGAPK_RF_PATH_MAX_8852B; i++) {
_halrf_txgapk_reload_rf_8852b(rf, rf_reg, rf_bkup, i);
}
halrf_wrf(rf, RF_PATH_A, 0x5, 0xfffff, rf_3wire_a_die[RF_PATH_A]);
halrf_wrf(rf, RF_PATH_B, 0x5, 0xfffff, rf_3wire_a_die[RF_PATH_B]);
halrf_wrf(rf, RF_PATH_A, 0x10005, 0xfffff, rf_3wire_d_die[RF_PATH_A]);
halrf_wrf(rf, RF_PATH_B, 0x10005, 0xfffff, rf_3wire_d_die[RF_PATH_B]);
_txgapk_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
}
void _halrf_do_dbcc_txgapk_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
u32 bb_reg[1] = {0x2344};
u32 bb_reg_backup[1] = {0};
u32 backup_num = 1;
u32 rf_3wire[2] = {0};
enum rf_path path = 0;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy);
_txgapk_backup_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
rf_3wire[RF_PATH_A] = halrf_rrf(rf, RF_PATH_A, 0x5, 0xfffff);
rf_3wire[RF_PATH_B] = halrf_rrf(rf, RF_PATH_B, 0x5, 0xfffff);
/* halrf_wrf(rf, RF_PATH_A, 0x00, 0x00001, 0x1); */
/* halrf_wrf(rf, RF_PATH_B, 0x00, 0x00001, 0x1); */
/*_halrf_txgapk_iqk_dpk_init_reg_8852b(rf, phy, RF_PATH_A);*/
/*_halrf_txgapk_nctl_8852b(rf, phy, RF_PATH_A);*/
if (phy == HW_PHY_0)
path = RF_PATH_A;
else if (phy == HW_PHY_1)
path = RF_PATH_B;
_halrf_txgapk_write_track_table_default_8852b(rf, phy, path);
_halrf_txgapk_write_power_table_default_8852b(rf, phy, path);
_halrf_txgapk_bb_afe_by_mode_8852b(rf, phy, path, true);
_halrf_txgapk_iqk_preset_by_mode_8852b(rf, phy, path, true);
_halrf_txgapk_clk_setting_dac960mhz_by_mode_8852b(rf, phy, path, true);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_START);
halrf_tmac_tx_pause(rf, phy, true);
_halrf_txgapk_track_table_nctl_8852b(rf, phy, path);
_halrf_txgapk_write_track_table_8852b(rf, phy, path);
_halrf_txgapk_power_table_nctl_8852b(rf, phy, path);
_halrf_txgapk_write_power_table_8852b(rf, phy, path);
halrf_tmac_tx_pause(rf, phy, true);
halrf_btc_rfk_ntfy(rf, (BIT(phy) << 4), RF_BTC_TSSI, RFK_STOP);
_halrf_txgapk_iqk_bk_reg_by_mode_8852b(rf, phy, path, true);
_halrf_txgapk_afe_bk_reg_by_mode_8852b(rf, phy, path, true);
/* halrf_wrf(rf, RF_PATH_A, 0x00, 0x00001, 0x0); */
/* halrf_wrf(rf, RF_PATH_B, 0x00, 0x00001, 0x0); */
halrf_wrf(rf, RF_PATH_A, 0x5, 0xfffff, rf_3wire[RF_PATH_A]);
halrf_wrf(rf, RF_PATH_B, 0x5, 0xfffff, rf_3wire[RF_PATH_B]);
_txgapk_reload_bb_registers_8852b(rf, phy, bb_reg, bb_reg_backup,
backup_num);
}
void _halrf_txgapk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 idx = 0;
u8 get_empty_table = false;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s \n", __func__);
for (idx = 0; idx < 2; idx++) {
if (txgapk_info->txgapk_mcc_ch[idx] == 0) {
get_empty_table = true;
break;
}
}
//RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] (1) idx = %x\n", idx);
if (false == get_empty_table) {
idx = txgapk_info->txgapk_table_idx + 1;
if (idx > 1) {
idx = 0;
}
//RF_DBG(rf, DBG_RF_IQK, "[IQK]we will replace iqk table index(%d), !!!!! \n", idx);
}
//RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK] (2) idx = %x\n", idx);
txgapk_info->txgapk_table_idx = idx;
txgapk_info->txgapk_mcc_ch[idx] = rf->hal_com->band[phy].cur_chandef.center_ch;
txgapk_info->ch[0] = rf->hal_com->band[phy].cur_chandef.center_ch;
}
void halrf_do_txgapk_8852b(struct rf_info *rf,
enum phl_phy_idx phy)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
txgapk_info->is_txgapk_ok = true;
txgapk_info->r0x8010[0] = halrf_rreg(rf, 0x8010, MASKDWORD);
_halrf_txgapk_get_ch_info_8852b(rf, phy);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d, dbcc_en = %d, table = %d \n", __func__, phy, rf->hal_com->dbcc_en, txgapk_info->txgapk_table_idx);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> version = 0x%x\n", TXGAPK_VER_8852B);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> before GapK process, 0x%x= 0x%x\n", 0x8010, txgapk_info->r0x8010[0]);
/* 0:table_0, 1:table_1 */
halrf_wrf(rf, RF_PATH_A, 0x18, 0x80000, txgapk_info->txgapk_table_idx);
halrf_wrf(rf, RF_PATH_B, 0x18, 0x80000, txgapk_info->txgapk_table_idx);
halrf_wrf(rf, RF_PATH_A, 0x10018, 0x80000, txgapk_info->txgapk_table_idx);
halrf_wrf(rf, RF_PATH_B, 0x10018, 0x80000, txgapk_info->txgapk_table_idx);
if (rf->hal_com->dbcc_en)
_halrf_do_dbcc_txgapk_8852b(rf, phy);
else
_halrf_do_non_dbcc_txgapk_8852b(rf, phy);
txgapk_info->r0x8010[1] = halrf_rreg(rf, 0x8010, MASKDWORD);
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> After GapK process, 0x%x= 0x%x\n", 0x8010, txgapk_info->r0x8010[1]);
}
void halrf_txgapk_init_8852b(struct rf_info *rf)
{
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 idx;
if(!txgapk_info->is_gapk_init) {
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s \n", __func__);
txgapk_info->is_gapk_init = true;
for (idx = 0; idx < 2; idx++) { //channel
txgapk_info->txgapk_mcc_ch[idx] = 0;
}
txgapk_info->txgapk_table_idx = 0;
}
}
void halrf_txgapk_enable_8852b
(struct rf_info *rf, enum phl_phy_idx phy)
{
u8 i;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy);
for (i = RF_PATH_A; i < 2; i++) {
_halrf_txgapk_write_track_table_8852b(rf, phy, i);
_halrf_txgapk_write_power_table_8852b(rf, phy, i);
}
}
void halrf_txgapk_write_table_default_8852b
(struct rf_info *rf, enum phl_phy_idx phy)
{
u8 i;
RF_DBG(rf, DBG_RF_TXGAPK, "[TXGAPK]======> %s phy=%d\n", __func__, phy);
for (i = RF_PATH_A; i < 2; i++) {
_halrf_txgapk_write_track_table_default_8852b(rf, phy, i);
_halrf_txgapk_write_power_table_default_8852b(rf, phy, i);
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.c
|
C
|
agpl-3.0
| 68,660
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_TXGAPK_8852B_H__
#define __HALRF_TXGAPK_8852B_H__
#ifdef RF_8852B_SUPPORT
#define TXGAPK_VER_8852B 0x06
/*--------------------------Define Parameters-------------------------------*/
#define TXGAPK_RF_PATH_MAX_8852B 2
#define TXGAPK_RF_REG_NUM_8852B 1
#define TXGAPK_DEBUGMASK_8852B 0x100EE
#define TXGAP_TB_ADDR_8852B 0x10033
#define TXGAP_TB_VAL_8852B 0x1003F
/*---------------------------End Define Parameters----------------------------*/
void halrf_txgapk_enable_8852b
(struct rf_info *rf, enum phl_phy_idx phy);
void halrf_txgapk_write_table_default_8852b
(struct rf_info *rf, enum phl_phy_idx phy);
void halrf_do_txgapk_8852b(struct rf_info *rf, enum phl_phy_idx phy);
void halrf_txgapk_init_8852b(struct rf_info *rf);
#endif /* RF_8852B_SUPPORT */
#endif /*#ifndef __HALRF_TXGAPK_8852B_H__*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_txgapk_8852b.h
|
C
|
agpl-3.0
| 1,811
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852B RF Parameters*/
#define RF_RELEASE_VERSION_8852B 19
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_8852b/halrf_version_rtl8852b.h
|
C
|
agpl-3.0
| 1,031
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halrf_precomp.h"
u32 phlrf_psd_log2base(struct rf_info *rf, u32 val)
{
u32 j;
u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
u32 result, val_fractiond_b = 0;
u32 table_fraction[21] = {
0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
if (val == 0)
return 0;
tmp = val;
while (1) {
if (tmp == 1)
break;
tmp = (tmp >> 1);
shiftcount++;
}
val_integerd_b = shiftcount + 1;
tmp2 = 1;
for (j = 1; j <= val_integerd_b; j++)
tmp2 = tmp2 * 2;
tmp = (val * 100) / tmp2;
tindex = tmp / 5;
if (tindex > 20)
tindex = 20;
val_fractiond_b = table_fraction[tindex];
result = val_integerd_b * 100 - val_fractiond_b;
return result;
}
void phlrf_rf_lna_setting(struct rf_info *rf, enum phlrf_lna_set type)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
break;
#endif
default:
break;
}
}
void halrf_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++)
bp[i] = halrf_rreg(rf, bp_reg[i], MASKDWORD);
}
void halrf_bkprf(struct rf_info *rf, u32 *bp_reg, u32 bp[][4], u32 reg_num, u32 path_num)
{
u32 i, j;
for (i = 0; i < reg_num; i++) {
for (j = 0; j < path_num; j++)
bp[i][j] = halrf_rrf(rf, j, bp_reg[i], MASKRF);
}
}
void halrf_reload_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num)
{
u32 i;
for (i = 0; i < reg_num; i++)
halrf_wreg(rf, bp_reg[i], MASKDWORD, bp[i]);
}
void halrf_reload_bkprf(struct rf_info *rf,
u32 *bp_reg,
u32 bp[][4],
u32 reg_num,
u8 path_num)
{
u32 i, path;
for (i = 0; i < reg_num; i++) {
for (path = 0; path < path_num; path++)
halrf_wrf(rf, (enum rf_path)path, bp_reg[i],
MASKRF, bp[i][path]);
}
}
u8 halrf_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 path = 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
path = halrf_kpath_8852a(rf, phy_idx);
break;
#endif
default:
break;
}
return path;
}
void halrf_wait_rx_mode(struct rf_info *rf, u8 kpath)
{
u8 path, rf_mode = 0;
u16 count = 0;
for (path = 0; path < 4; path++) {
if (kpath & BIT(path)) {
rf_mode = (u8)halrf_rrf(rf, path, 0x00, MASKRFMODE);
while (rf_mode == 2 && count < 2500) {
rf_mode = (u8)halrf_rrf(rf, path, 0x00, MASKRFMODE);
halrf_delay_us(rf, 2);
count++;
}
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Wait S%d to Rx mode!! (count = %d)\n", path, count);
}
}
}
void halrf_tmac_tx_pause(struct rf_info *rf, enum phl_phy_idx band_idx, bool is_pause)
{
halrf_tx_pause(rf, band_idx, is_pause, PAUSE_RSON_RFK);
RF_DBG(rf, DBG_RF_RFK,"[RFK] Band%d Tx Pause %s!!\n",
band_idx, is_pause ? "on" : "off");
if (is_pause)
halrf_wait_rx_mode(rf, halrf_kpath(rf, band_idx));
}
void halrf_trigger_thermal(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_trigger_thermal_8852a(rf, RF_PATH_A);
halrf_trigger_thermal_8852a(rf, RF_PATH_B);
break;
#endif
default:
break;
}
}
u8 halrf_only_get_thermal(struct rf_info *rf, enum rf_path path)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
return halrf_only_get_thermal_8852a(rf, path);
break;
#endif
default:
break;
}
return 0;
}
void halrf_btc_rfk_ntfy(struct rf_info *rf, u8 phy_map, enum halrf_rfk_type type,
enum halrf_rfk_process process)
{
u32 cnt = 0;
u8 band;
/*idx : use BIT mask for RF path PATH A: 1, PATH B:2, PATH AB:3*/
band = rf->hal_com->band[(phy_map & 0x30) >> 5].cur_chandef.band;
phy_map = (band << 6) | phy_map;
RF_DBG(rf, DBG_RF_RFK, "[RFK] RFK notify (%s / PHY%d / K_type = %d / path_idx = %d / process = %s)\n",
band == 0 ? "2G" : (band == 1 ? "5G" : "6G"), (phy_map & 0x30) >> 5, type,
phy_map & 0xf, process == 0 ? "RFK_STOP" : (process == 1 ? "RFK_START" :
(process == 2 ? "ONE-SHOT_START" : "ONE-SHOT_STOP")));
#if 1
if (process == RFK_START && rf->is_bt_iqk_timeout == false) {
while (halrf_btc_ntfy(rf, phy_map, type, process) == 0 && cnt < 2500) {
halrf_delay_us(rf, 40);
cnt++;
}
if (cnt == 2500) {
RF_DBG(rf, DBG_RF_RFK, "[RFK] Wait BT IQK timeout!!!!\n");
rf->is_bt_iqk_timeout = true;
}
} else
halrf_btc_ntfy(rf, phy_map, type, process);
#endif
}
void halrf_fcs_init(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_fcs_init_8852a(rf);
#endif
}
void halrf_fast_chl_sw_backup(struct rf_info *rf, u8 chl_index, u8 t_index)
{
u32 t[2];
t[0] = chl_index;
t[1] = t_index;
halrf_fill_h2c_cmd(rf, 8, FWCMD_H2C_BACKUP_RFK, 0xa, H2CB_TYPE_DATA, t);
RF_DBG(rf, DBG_RF_RFK, "FWCMD_H2C_BACKUP_RFK chl=%d t=%d\n", chl_index, t_index);
}
void halrf_fast_chl_sw_reload(struct rf_info *rf, u8 chl_index, u8 t_index)
{
u32 t[2];
t[0] = chl_index;
t[1] = t_index;
halrf_fill_h2c_cmd(rf, 8, FWCMD_H2C_RELOAD_RFK, 0xa, H2CB_TYPE_DATA, t);
RF_DBG(rf, DBG_RF_RFK, "FWCMD_H2C_RELOAD_RFK chl=%d t=%d\n", chl_index, t_index);
}
void halrf_quick_check_rf(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A)
halrf_quick_check_rfrx_8852a(rf);
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B)
halrf_quick_checkrf_8852b(rf);
#endif
}
void halrf_wifi_event_notify(void *rf_void,
enum phl_msg_evt_id event, enum phl_phy_idx phy_idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
if (event == MSG_EVT_SCAN_START) {
halrf_tssi_default_txagc(rf, phy_idx, true);
halrf_tssi_set_avg(rf, phy_idx, true);
halrf_dpk_track_onoff(rf, false);
} else if (event == MSG_EVT_SCAN_END) {
halrf_tssi_default_txagc(rf, phy_idx, false);
halrf_tssi_set_avg(rf, phy_idx, false);
halrf_dpk_track_onoff(rf, true);
} else if (event == MSG_EVT_DBG_RX_DUMP) {
halrf_quick_check_rf(rf);
} else if (event == MSG_EVT_SWCH_START) {
halrf_tssi_backup_txagc(rf, phy_idx, true);
}
}
void halrf_wreg_fw(struct rf_info *rf, u32 addr, u32 mask, u32 val)
{
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
struct rtw_mac_cmd cmd = {0};
struct halrf_fw_offload *fwofld_info = &rf->fwofld;
bool fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
u32 rtn;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s addr=0x%x mask=0x%x val=0x%x fw_ofld=%d\n",
__func__, addr, mask, val, fw_ofld);
hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info));
if (fw_ofld) {
cmd.src = RTW_MAC_BB_CMD_OFLD;
cmd.type = RTW_MAC_WRITE_OFLD;
cmd.lc = 0;
cmd.offset = (u16)addr;
cmd.value = val;
cmd.mask = mask;
fwofld_info->src = RTW_MAC_BB_CMD_OFLD;
fwofld_info->type = RTW_MAC_WRITE_OFLD;
fwofld_info->lc = 1;
fwofld_info->offset = (u16)addr;
fwofld_info->value = val;
fwofld_info->mask = mask;
rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
if (rtn) {
RF_WARNING("======>%s return fail error code = %d !!!\n",
__func__, rtn);
}
} else
#endif
halrf_wreg(rf, addr, mask, val);
}
void halrf_wrf_fw(struct rf_info *rf,
enum rf_path path, u32 addr, u32 mask, u32 val)
{
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
struct rtw_mac_cmd cmd = {0};
struct halrf_fw_offload *fwofld_info = &rf->fwofld;
bool fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
u32 rtn;
RF_DBG(rf, DBG_RF_INIT,
"======>%s addr=0x%x mask=0x%x val=0x%x fw_ofld=%d path=%d\n",
__func__, addr, mask, val, fw_ofld, path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK,
"======>%s addr=0x%x mask=0x%x val=0x%x fw_ofld=%d path=%d\n",
__func__, addr, mask, val, fw_ofld, path);
hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info));
if (fw_ofld) {
cmd.src = RTW_MAC_RF_CMD_OFLD;
cmd.type = RTW_MAC_WRITE_OFLD;
cmd.lc = 0;
cmd.rf_path = path;
cmd.offset = (u16)addr;
cmd.value = val;
cmd.mask = mask;
fwofld_info->src = RTW_MAC_RF_CMD_OFLD;
fwofld_info->type = RTW_MAC_WRITE_OFLD;
fwofld_info->lc = 1;
fwofld_info->rf_path = path;
fwofld_info->offset = (u16)addr;
fwofld_info->value = val;
fwofld_info->mask = mask;
rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
if (rtn) {
RF_WARNING("======>%s return fail error code = %d !!!\n",
__func__, rtn);
}
} else
#endif
halrf_wrf(rf, path, addr, mask, val);
}
void halrf_wmac_fw(struct rf_info *rf, enum phl_phy_idx phy,
u32 addr, u32 mask, u32 val)
{
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
struct rtw_mac_cmd cmd = {0};
struct halrf_fw_offload *fwofld_info = &rf->fwofld;
bool fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
u32 rtn;
RF_DBG(rf, DBG_RF_POWER,
"======>%s addr=0x%x mask=0x%x val=0x%x fw_ofld=%d\n",
__func__, addr, mask, val, fw_ofld);
hal_mem_set(rf->hal_com, fwofld_info, 0, sizeof(*fwofld_info));
if (fw_ofld) {
cmd.src = RTW_MAC_MAC_CMD_OFLD;
cmd.type = RTW_MAC_WRITE_OFLD;
cmd.lc = 0;
cmd.offset = (u16)addr;
cmd.value = val;
cmd.mask = mask;
fwofld_info->src = RTW_MAC_MAC_CMD_OFLD;
fwofld_info->type = RTW_MAC_WRITE_OFLD;
fwofld_info->lc = 1;
fwofld_info->offset = (u16)addr;
fwofld_info->value = val;
fwofld_info->mask = mask;
rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
if (rtn) {
RF_WARNING("======>%s return fail error code = %d !!!\n",
__func__, rtn);
}
} else
#endif
halrf_mac_set_pwr_reg(rf, phy, addr, mask, val);
}
void halrf_write_fw_final(struct rf_info *rf)
{
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
struct rtw_mac_cmd cmd = {0};
struct halrf_fw_offload *fwofld_info = &rf->fwofld;
bool fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
u32 rtn;
RF_DBG(rf, DBG_RF_TX_PWR_TRACK | DBG_RF_POWER,
"======>%s src=%d type=%d lc=%d rf_path=%d\n",
__func__, fwofld_info->src, fwofld_info->type,
fwofld_info->lc, fwofld_info->rf_path);
RF_DBG(rf, DBG_RF_TX_PWR_TRACK | DBG_RF_POWER,
"======>%s offset=0x%x mask=0x%x value=0x%x fw_ofld=%d\n",
__func__, fwofld_info->offset, fwofld_info->mask,
fwofld_info->value, fw_ofld);
cmd.src = fwofld_info->src;
cmd.type = fwofld_info->type;
cmd.lc = 1;
cmd.rf_path = fwofld_info->rf_path;
cmd.offset = fwofld_info->offset;
cmd.value = fwofld_info->value;
cmd.mask = fwofld_info->mask;
if (fw_ofld) {
rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
if (rtn) {
RF_WARNING("======>%s return fail error code = %d !!!\n",
__func__, rtn);
}
}
#endif
}
void halrf_ctrl_bw_ch(void *rf_void, enum phl_phy_idx phy, u8 central_ch,
enum band_type band, enum channel_width bw)
{
struct rf_info *rf = (struct rf_info *)rf_void;
halrf_ctl_ch(rf, central_ch);
halrf_ctl_bw(rf, bw);
halrf_rxbb_bw(rf, phy, bw);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_api.c
|
C
|
agpl-3.0
| 11,542
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_API_H_
#define _HALRF_API_H_
/*@--------------------------[Define] ---------------------------------------*/
#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))
/*@--------------------------[Enum]------------------------------------------*/
enum phlrf_lna_set {
PHLRF_LNA_DISABLE = 0,
PHLRF_LNA_ENABLE = 1,
};
enum halrf_rfk_type {
RF_BTC_IQK = 0,
RF_BTC_LCK = 1,
RF_BTC_DPK = 2,
RF_BTC_TXGAPK = 3,
RF_BTC_DACK = 4,
RF_BTC_RXDCK = 5,
RF_BTC_TSSI = 6
};
enum halrf_rfk_process {
RFK_STOP = 0,
RFK_START = 1,
RFK_ONESHOT_START = 2,
RFK_ONESHOT_STOP = 3
};
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct rf_info;
u32 phlrf_psd_log2base(struct rf_info *rf, u32 val);
void phlrf_rf_lna_setting(struct rf_info *rf, enum phlrf_lna_set type);
void halrf_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num);
void halrf_bkprf(struct rf_info *rf, u32 *bp_reg, u32 bp[][4], u32 reg_num, u32 path_num);
void halrf_reload_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num);
void halrf_reload_bkprf(struct rf_info *rf,
u32 *bp_reg,
u32 bp[][4],
u32 reg_num,
u8 path_num);
u8 halrf_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx);
void halrf_tmac_tx_pause(struct rf_info *rf, enum phl_phy_idx band_idx, bool pause);
void halrf_trigger_thermal(struct rf_info *rf);
u8 halrf_only_get_thermal(struct rf_info *rf, enum rf_path path);
void halrf_thermal_period(struct rf_info *rf);
void halrf_btc_rfk_ntfy(struct rf_info *rf, u8 phy_map, enum halrf_rfk_type type,
enum halrf_rfk_process process);
void halrf_fcs_init(struct rf_info *rf);
void halrf_fast_chl_sw_backup(struct rf_info *rf, u8 chl_index, u8 t_index);
void halrf_fast_chl_sw_reload(struct rf_info *rf, u8 chl_index, u8 t_index);
/*FW Offload*/
void halrf_wreg_fw(struct rf_info *rf, u32 addr, u32 mask, u32 val);
void halrf_wrf_fw(struct rf_info *rf,
enum rf_path path, u32 addr, u32 mask, u32 val);
void halrf_wmac_fw(struct rf_info *rf, enum phl_phy_idx phy,
u32 addr, u32 mask, u32 val);
void halrf_write_fw_final(struct rf_info *rf);
void halrf_quick_check_rf(void *rf_void);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_api.h
|
C
|
agpl-3.0
| 2,916
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_DACK_H_
#define _HALRF_DACK_H_
/*@--------------------------Define Parameters-------------------------------*/
/*@-----------------------End Define Parameters-----------------------*/
struct halrf_dack_info {
bool dack_done;
u8 msbk_d[2][2][16];
u8 dadck_d[2][2]; /*path/IQ*/
u16 addck_d[2][2]; /*path/IQ*/
u16 biask_d[2][2]; /*path/IQ*/
u32 dack_cnt;
u32 dack_time;
bool addck_timeout[2];
bool dadck_timeout[2];
bool msbk_timeout[2];
bool dack_fail;
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dack.h
|
C
|
agpl-3.0
| 1,143
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halrf_precomp.h"
void halrf_dbg_setting_init(struct rf_info *rf)
{
rf->fw_dbg_component = 0;
rf->dbg_component =
/*DBG_RF_TX_PWR_TRACK | */
/*DBG_RF_IQK | */
/*DBG_RF_LCK | */
/*DBG_RF_DPK | */
/*DBG_RF_TXGAPK | */
/*DBG_RF_DACK | */
/*DBG_RF_DPK_TRACK | */
/*DBG_RF_RXDCK | */
/*DBG_RF_RFK | */
/*DBG_RF_MP | */
/*DBG_RF_TMP | */
/*DBG_RF_INIT | */
/*DBG_RF_POWER | */
/*DBG_RF_RXGAINK | */
/*DBG_RF_THER_TRIM | */
/*DBG_RF_PABIAS_TRIM | */
/*DBG_RF_TSSI_TRIM | */
/*DBG_RF_PSD | */
/*DBG_RF_CHK | */
/*DBG_RF_XTAL_TRACK | */
0;
rf->cmn_dbg_msg_cnt = HALRF_WATCHDOG_PERIOD;
rf->cmn_dbg_msg_period = HALRF_WATCHDOG_PERIOD;
}
void halrf_iqk_log(struct rf_info *rf)
{
#if 0
struct halrf_iqk_info *iqk_info = &rf->iqk;
/* IQK INFO */
RF_DBG(rf, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
RF_DBG(rf, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
iqk_info->iqk_cnt, iqk_info->iqk_fail_cnt);
RF_DBG(rf, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
(iqk_info->segment_iqk) ? "True" : "False");
#endif
}
void halrf_lck_log(struct rf_info *rf)
{
RF_DBG(rf, DBG_RF_LCK, "%-20s\n", "====== LCK Info ======");
}
void halrf_support_ability(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 value[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i;
for (i = 0; i < 5; i++)
if (input[i + 1])
_os_sscanf(input[i + 1], "%d", &value[i]);
if (value[0] == 100) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[RF Supportability]\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"00. (( %s ))Power Tracking\n",
((rf->support_ability & HAL_RF_TX_PWR_TRACK) ?
("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"01. (( %s ))IQK\n",
((rf->support_ability & HAL_RF_IQK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"02. (( %s ))LCK\n",
((rf->support_ability & HAL_RF_LCK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"03. (( %s ))DPK\n",
((rf->support_ability & HAL_RF_DPK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"04. (( %s ))HAL_RF_TXGAPK\n",
((rf->support_ability & HAL_RF_TXGAPK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"05. (( %s ))HAL_RF_DACK\n",
((rf->support_ability & HAL_RF_DACK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"06. (( %s ))DPK_TRACK\n",
((rf->support_ability & HAL_RF_DPK_TRACK) ? ("V") :
(".")));
#ifdef CONFIG_2G_BAND_SHIFT
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"07. (( %s ))HAL_2GBAND_SHIFT\n",
((rf->support_ability & HAL_2GBAND_SHIFT) ? ("V") :
(".")));
#endif
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"08. (( %s ))HAL_RF_RXDCK\n",
((rf->support_ability & HAL_RF_RXDCK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"13. (( %s ))HAL_RF_THER_TRIM\n",
((rf->support_ability & HAL_RF_THER_TRIM) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"14. (( %s ))HAL_RF_PABIAS_TRIM\n",
((rf->support_ability & HAL_RF_PABIAS_TRIM) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"15. (( %s ))HAL_RF_TSSI_TRIM\n",
((rf->support_ability & HAL_RF_TSSI_TRIM) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"17. (( %s ))HAL_RF_TSSI_TRK\n",
((rf->support_ability & HAL_RF_TSSI_TRK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"18. (( %s ))HAL_RF_XTAL_TRACK\n",
((rf->support_ability & HAL_RF_XTAL_TRACK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"19. (( %s ))HAL_RF_TX_SHAPE\n",
((rf->support_ability & HAL_RF_TX_SHAPE) ? ("V") :
(".")));
} else {
if (value[1] == 1) /* enable */
rf->support_ability |= BIT(value[0]);
else if (value[1] == 2) /* disable */
rf->support_ability &= ~(BIT(value[0]));
else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[Warning!!!] 1:enable, 2:disable\n");
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Curr-RF_supportability = 0x%x\n\n", rf->support_ability);
*_used = used;
*_out_len = out_len;
}
void halrf_dbg_trace(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 one = 1;
u32 used = *_used;
u32 out_len = *_out_len;
u32 value[10] = {0};
u8 i;
for (i = 0; i < 5; i++)
if (input[i + 1])
_os_sscanf(input[i + 1], "%d", &value[i]);
if (value[0] == 100) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[RF Debug Trace Selection]\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"00. (( %s ))TX_PWR_TRACK\n",
((rf->dbg_component & DBG_RF_TX_PWR_TRACK) ? ("V") :
(".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"01. (( %s ))IQK\n",
((rf->dbg_component & DBG_RF_IQK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"02. (( %s ))LCK\n",
((rf->dbg_component & DBG_RF_LCK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"03. (( %s ))DPK\n",
((rf->dbg_component & DBG_RF_DPK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"04. (( %s ))TXGAPK\n",
((rf->dbg_component & DBG_RF_TXGAPK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"05. (( %s ))DACK\n",
((rf->dbg_component & DBG_RF_DACK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"06. (( %s ))DPK_TRACK\n",
((rf->dbg_component & DBG_RF_DPK_TRACK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"08. (( %s ))RXDCK\n",
((rf->dbg_component & DBG_RF_RXDCK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"09. (( %s ))RFK\n",
((rf->dbg_component & DBG_RF_RFK) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"10. (( %s ))INIT\n",
((rf->dbg_component & DBG_RF_INIT) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"11. (( %s ))POWER\n",
((rf->dbg_component & DBG_RF_POWER) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"28. (( %s ))FW\n",
((rf->dbg_component & DBG_RF_FW) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"29. (( %s ))MP\n",
((rf->dbg_component & DBG_RF_MP) ? ("V") : (".")));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"30. (( %s ))TMP\n",
((rf->dbg_component & DBG_RF_TMP) ? ("V") : (".")));
} else if (value[0] == 101) {
rf->dbg_component = 0;
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Disable all DBG COMP\n");
} else {
if (value[1] == 1) /*enable*/
rf->dbg_component |= (one << value[0]);
else if (value[1] == 2) /*disable*/
rf->dbg_component &= ~(one << value[0]);
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Curr-RF_Dbg_Comp = 0x%x\n", rf->dbg_component);
*_used = used;
*_out_len = out_len;
}
void halrf_dump_rfk_reg(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u32 addr = 0;
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"===================[ RFK Reg start ]===================\n");
for (addr = 0x8000; addr < 0xa000; addr += 0x10)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
halrf_rreg(rf, addr, MASKDWORD),
halrf_rreg(rf, addr + 0x4, MASKDWORD),
halrf_rreg(rf, addr + 0x8, MASKDWORD),
halrf_rreg(rf, addr + 0xc, MASKDWORD));
*_used = used;
*_out_len = out_len;
}
void _halrf_dpk_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_dpk_info *dpk = &rf->dpk;
u32 used = *_used;
u32 out_len = *_out_len;
char *ic_name = NULL;
u32 dpk_ver = 0;
u32 rf_para = 0;
u32 rfk_init_ver = 0;
u8 path, kidx;
u32 rf_para_min = 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
ic_name = "8852A";
dpk_ver = DPK_VER_8852A;
rf_para_min = 16;
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
ic_name = "8852B";
dpk_ver = DPK_VER_8852B;
break;
#endif
default:
break;
}
rf_para = halrf_get_radio_reg_ver(rf);
rfk_init_ver = halrf_get_nctl_reg_ver(rf);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n===============[ DPK info %s ]===============\n", ic_name);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"DPK Ver", dpk_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d (%s)\n",
"RF Para Ver", rf_para, rf_para >= rf_para_min ? "match" : "mismatch");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"RFK init ver", rfk_init_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d (RFE type:%d)\n",
"Ext_PA 2G / 5G / 6G", rf->fem.epa_2g, rf->fem.epa_5g, rf->fem.epa_6g,
rf->phl_com->dev_cap.rfe_type);
if (dpk->bp[0][0].ch == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n %-25s\n",
"No DPK had been done before!!!");
return;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
"DPK Cal / OK / Reload", dpk->dpk_cal_cnt, dpk->dpk_ok_cnt,
dpk->dpk_reload_cnt);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"BT IQK timeout", rf->is_bt_iqk_timeout ? "Yes" : "No");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"DPD status", dpk->is_dpk_enable ? "Enable" : "Disable");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"DPD track status", (rf->support_ability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %s\n",
"DBCC / TSSI", rf->hal_com->dbcc_en ? "On" : "Off",
rf->is_tssi_mode[0] ? "On" : "Off");
for (path = 0; path < KPATH; path++) {
for (kidx = 0; kidx < DPK_BKUP_NUM; kidx++) {
if (dpk->bp[path][kidx].ch == 0)
break;
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"=============== S%d[%d] ===============\n", path, kidx);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n",
"Band / CH / BW", dpk->bp[path][kidx].band == 0 ? "2G" : (dpk->bp[path][kidx].band == 1 ? "5G" : "6G"),
dpk->bp[path][kidx].ch,
dpk->bp[path][kidx].bw == 0 ? "20M" : (dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s \n",
"DPK result", dpk->bp[path][kidx].path_ok ? "OK" : "Fail");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x\n",
"DPK TxAGC / Gain Scaling", dpk->bp[path][kidx].txagc_dpk, dpk->bp[path][kidx].gs);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Corr (idx/val)", dpk->corr_idx[path][kidx], dpk->corr_val[path][kidx]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"DC (I/Q)", dpk->dc_i[path][kidx], dpk->dc_q[path][kidx]);
}
}
*_used = used;
*_out_len = out_len;
}
void halrf_dpk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#if 1
char *cmd[5] = {"-h", "on", "off", "info", "trigger"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
if (!(rf->support_ability & HAL_RF_DPK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"DPK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 5; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"DPK is Enabled!!\n");
halrf_dpk_onoff(rf, true);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"DPK is Disabled!!\n");
halrf_dpk_onoff(rf, false);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
_halrf_dpk_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0){
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" DPK Trigger start!!\n");
_os_sscanf(input[1], "%d", &val);
halrf_dpk_trigger(rf, val, false);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" DPK Trigger finish!!\n");
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_rx_dck_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_rx_dck_info *rx_dck = &rf->rx_dck;
u32 used = *_used;
u32 out_len = *_out_len;
char *ic_name = NULL;
u32 rxdck_ver = 0;
u8 path;
u32 addr = 0;
u32 reg_05[KPATH];
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
ic_name = "8852A";
rxdck_ver = RXDCK_VER_8852A;
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
ic_name = "8852B";
rxdck_ver = RXDCK_VER_8852B;
break;
#endif
default:
break;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n===============[ RX_DCK info %s ]===============\n", ic_name);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"RX_DCK Ver", rxdck_ver);
if (rx_dck->loc[0].cur_ch == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n %-25s\n",
"No RX_DCK had been done before!!!");
return;
}
for (path = 0; path < KPATH; path++) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" S%d:", path);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s / %s\n",
"Band / CH / BW / Cal", rx_dck->loc[path].cur_band == 0 ? "2G" :
(rx_dck->loc[path].cur_band == 1 ? "5G" : "6G"),
rx_dck->loc[path].cur_ch,
rx_dck->loc[path].cur_bw == 0 ? "20M" :
(rx_dck->loc[path].cur_bw == 1 ? "40M" : "80M"),
rx_dck->is_afe ? "AFE" : "RFC");
}
for (path = 0; path < KPATH; path++) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n---------------[ S%d DCK Value ]---------------\n", path);
reg_05[path] = halrf_rrf(rf, path, 0x5, MASKRF);
halrf_wrf(rf, path, 0x5, BIT(0), 0x0);
halrf_wrf(rf, path, 0x00, MASKRFMODE, RF_RX);
for (addr = 0; addr < 0x20; addr++) {
halrf_wrf(rf, path, 0x00, 0x07c00, addr); /*[14:10]*/
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"0x%02x | 0x%02x/ 0x%02x 0x%02x/ 0x%02x\n", addr,
halrf_rrf(rf, path, 0x92, 0xF0000), /*[19:16]*/
halrf_rrf(rf, path, 0x92, 0x0FC00), /*[15:10]*/
halrf_rrf(rf, path, 0x93, 0xF0000), /*[19:16]*/
halrf_rrf(rf, path, 0x93, 0x0FC00)); /*[15:10]*/
}
halrf_wrf(rf, path, 0x5, BIT(0), reg_05[path]);
}
*_used = used;
*_out_len = out_len;
}
void halrf_get_rx_dck_value(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
u32 val_1 = 0, val_2 = 0;
u32 used = *_used;
u32 out_len = *_out_len;
u32 reg_05[KPATH];
_os_sscanf(input[2], "%d", &val_1); /*RF path*/
_os_sscanf(input[3], "%x", &val_2); /*RF 0x0*/
if (val_1 > 3) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" Wrong path number!!\n");
return;
}
reg_05[val_1] = halrf_rrf(rf, val_1, 0x5, MASKRF);
halrf_wrf(rf, val_1, 0x5, BIT(0), 0x0);
halrf_wrf(rf, val_1, 0x00, MASKRF, val_2);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" Input S%d RF0x00 = 0x%x\n", val_1, val_2);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" Get I : RXBB / TIA = 0x%x / 0x%x\n",
halrf_rrf(rf, val_1, 0x92, 0xF0000), /*[19:16]*/
halrf_rrf(rf, val_1, 0x92, 0x0FC00)); /*[15:10]*/
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" Get Q : RXBB / TIA = 0x%x / 0x%x\n",
halrf_rrf(rf, val_1, 0x93, 0xF0000), /*[19:16]*/
halrf_rrf(rf, val_1, 0x93, 0x0FC00)); /*[15:10]*/
halrf_wrf(rf, val_1, 0x5, BIT(0), reg_05[val_1]);
*_used = used;
*_out_len = out_len;
}
void halrf_rx_dck_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char *cmd[6] = {"-h", "on", "off", "info", "trigger", "get"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val_1 = 0, val_2 = 0;
u8 i;
if (!(rf->support_ability & HAL_RF_RXDCK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RX_DCK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 6; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RX_DCK is Enabled!!\n");
halrf_rx_dck_onoff(rf, true);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RX_DCK is Disabled!!\n");
halrf_rx_dck_onoff(rf, false);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
halrf_rx_dck_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RX DCK Trigger\n");
_os_sscanf(input[2], "%d", &val_1);
_os_sscanf(input[3], "%d", &val_2);
halrf_rx_dck_trigger(rf, val_1, (bool)val_2);
} else if (_os_strcmp(input[1], cmd[5]) == 0) {
halrf_get_rx_dck_value(rf, input, &used, output, &out_len);
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
}
void halrf_dack_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_dack_info *dack = &rf->dack;
u32 used = *_used;
u32 out_len = *_out_len;
char *ic_name = NULL;
u32 dack_ver = 0;
u32 rf_para = 0;
u32 rfk_init_ver = 0;
u8 i;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
ic_name = "8852A";
dack_ver = DACK_VER_8852AB;
rf_para = halrf_get_radio_reg_ver(rf);
break;
#endif
default:
break;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n===============[ DACK info %s ]===============\n", ic_name);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"DACK Ver", dack_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"RF Para Ver", rf_para);
if (dack->dack_cnt == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n %-25s\n",
"No DACK had been done before!!!");
return;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"DACK count", dack->dack_cnt);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d ms\n",
"DACK processing time", dack->dack_time);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-60s = %d / %d / %d / %d / %d / %d\n",
"DACK timeout(ADDCK_0/ADDCK_1/DADCK_0/DADCK_1/MSBK_0/MSBK_1):",
dack->addck_timeout[0], dack->addck_timeout[1],
dack->dadck_timeout[0], dack->dadck_timeout[1],
dack->msbk_timeout[0], dack->msbk_timeout[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"DACK Fail(last)", (dack->dack_fail) ? "TRUE" : "FALSE");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"===============[ ADDCK result ]===============\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n",
"S0_I/ S0_Q", dack->addck_d[0][0], dack->addck_d[0][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n",
"S1_I/ S1_Q", dack->addck_d[1][0], dack->addck_d[1][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"===============[ DADCK result ]===============\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n",
"S0_I/ S0_Q", dack->dadck_d[0][0], dack->dadck_d[0][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n",
"S1_I/ S1_Q", dack->dadck_d[1][0], dack->dadck_d[1][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"===============[ biask result ]===============\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n",
"S0_I/ S0_Q", dack->biask_d[0][0], dack->biask_d[0][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x \n",
"S1_I/ S1_Q", dack->biask_d[1][0], dack->biask_d[1][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"===============[ MSBK result ]===============\n");
for (i = 0; i < 16; i++) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s [%2d] = 0x%x/ 0x%x/ 0x%x/ 0x%x\n",
"S0_I/S0_Q/S1_I/S1_Q",
i,
dack->msbk_d[0][0][i], dack->msbk_d[0][1][i],
dack->msbk_d[1][0][i], dack->msbk_d[1][1][i]);
}
*_used = used;
*_out_len = out_len;
}
void halrf_dack_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#if 1
char *cmd[5] = {"-h", "on", "off", "info", "trigger"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
if (!(rf->support_ability & HAL_RF_DACK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"DACK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 5; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"DPK is Enabled!!\n");
halrf_dack_onoff(rf, true);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"DPK is Disabled!!\n");
halrf_dack_onoff(rf, false);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
halrf_dack_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0){
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" DACKTrigger start!!\n");
_os_sscanf(input[1], "%d", &val);
halrf_dack_trigger(rf, true);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" DACK Trigger finish!!\n");
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
#endif
}
void _halrf_tssi_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_tssi_info *tssi_info = &rf->tssi;
struct halrf_dpk_info *dpk = &rf->dpk;
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u32 bw = rf->hal_com->band[0].cur_chandef.bw;
u32 band = rf->hal_com->band[0].cur_chandef.band;
u8 txsc_ch = rf->hal_com->band[0].cur_chandef.chan;
u32 used = *_used;
u32 out_len = *_out_len;
char *ic_name = NULL;
u32 tssi_ver = 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
ic_name = "8852A";
tssi_ver = TSSI_VER_8852A;
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
ic_name = "8852B";
tssi_ver = TSSI_VER_8852B;
break;
#endif
default:
break;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n===============[ TSSI info %s ]===============\n", ic_name);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"TSSI Ver", tssi_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d (RFE type:%d)\n",
"Ext_PA 2G / 5G / 6G", rf->fem.epa_2g, rf->fem.epa_5g, rf->fem.epa_6g,
rf->phl_com->dev_cap.rfe_type);
//RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
// "BT IQK timeout", rf->is_bt_iqk_timeout ? "Yes" : "No");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s/%s\n",
"TSSI status A/B",
rf->is_tssi_mode[RF_PATH_A] ? "Enable" : "Disable",
rf->is_tssi_mode[RF_PATH_B] ? "Enable" : "Disable");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %s\n",
"DBCC / DPK", rf->hal_com->dbcc_en ? "On" : "Off",
dpk->is_dpk_enable ? "On" : "Off");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s / %d\n",
"Band / CH / BW / TXSC", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"),
channel,
bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M"),
txsc_ch);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n",
"TSSI DE CCK A",
tssi_info->curr_tssi_cck_de[RF_PATH_A],
tssi_info->curr_tssi_efuse_cck_de[RF_PATH_A],
tssi_info->curr_tssi_trim_de[RF_PATH_A]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n",
"TSSI DE CCK B",
tssi_info->curr_tssi_cck_de[RF_PATH_B],
tssi_info->curr_tssi_efuse_cck_de[RF_PATH_B],
tssi_info->curr_tssi_trim_de[RF_PATH_B]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n",
"TSSI DE OFDM A",
tssi_info->curr_tssi_ofdm_de[RF_PATH_A],
tssi_info->curr_tssi_efuse_ofdm_de[RF_PATH_A],
tssi_info->curr_tssi_trim_de[RF_PATH_A]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s : DE(%d) = EFUSE(%d) + Trim(%d)\n",
"TSSI DE OFDM B",
tssi_info->curr_tssi_ofdm_de[RF_PATH_B],
tssi_info->curr_tssi_efuse_ofdm_de[RF_PATH_B],
tssi_info->curr_tssi_trim_de[RF_PATH_B]);
halrf_get_tssi_info(rf, input, &used, output, &out_len);
*_used = used;
*_out_len = out_len;
}
void halrf_tssi_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char *cmd[7] = {"-h", "on", "off", "info", "trk", "trigger", "final"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0, val1 = 0;
u8 i;
#if 0
if (!(rf->support_ability & HAL_RF_TX_PWR_TRACK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI is Unsupported!!!\n");
return;
}
#endif
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 7; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI is Enabled!!\n");
halrf_tssi_enable(rf, val);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI is Disabled!!\n");
halrf_tssi_disable(rf, val);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
_halrf_tssi_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0) {
halrf_get_tssi_trk_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[5]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI Trigger start!!\n");
_os_sscanf(input[2], "%d", &val);
halrf_tssi_trigger(rf, val);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI Trigger finish, TSSI ON!!!\n");
} else if (_os_strcmp(input[1], cmd[6]) == 0){
_os_sscanf(input[1], "%d", &val);
_os_sscanf(input[2], "%d", &val1);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI Final Path%s\n", (val1 == RF_PATH_A) ? "A" : "B");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TSSI Final Path%s Result:%d\n",
(val1 == RF_PATH_A) ? "A" : "B",
halrf_tssi_get_final(rf, val, (u8)val1));
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
}
static void _halrf_iqk_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 used = *_used;
u32 out_len = *_out_len;
char *ic_name = NULL;
u32 ver = 0;
u32 rfk_init_ver = 0;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===>%s\n", __func__);
switch (hal_i->chip_id) {
case CHIP_WIFI6_8852A:
ic_name = "8852A";
ver = halrf_get_iqk_ver(rf);
rfk_init_ver = halrf_get_nctl_reg_ver(rf);
break;
default:
break;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n===============[ IQK info %s ]===============\n", ic_name);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"IQK Version", ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"RFK init ver", rfk_init_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
"IQK Cal / Fail / Reload", iqk_info->iqk_times, iqk_info->iqk_fail_cnt,
iqk_info->reload_cnt);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n",
"S0 Band / CH / BW", iqk_info->iqk_band[0]== 0 ? "2G" : (iqk_info->iqk_band[0] == 1 ? "5G" : "6G"),
iqk_info->iqk_ch[0],
iqk_info->iqk_bw[0] == 0 ? "20M" : (iqk_info->iqk_bw[0] == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S0 NB/WB TXIQK", iqk_info->is_wb_txiqk[0]? "WBTXK" : "NBTXK");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S0 NB/WB RXIQK", iqk_info->is_wb_rxiqk[0]? "WBRXK" : "NBRXK");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S0 LOK status", (iqk_info->lok_cor_fail[0][0] | iqk_info->lok_fin_fail[0][0]) ? "Fail" : "Pass");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S0 TXK status", iqk_info->iqk_tx_fail[0][0]? "Fail" : "Pass");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S0 RXK status", iqk_info->iqk_rx_fail[0][0]? "Fail" : "Pass");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n",
"S1 Band / CH / BW", iqk_info->iqk_band[1]== 0 ? "2G" : (iqk_info->iqk_band[1] == 1 ? "5G" : "6G"),
iqk_info->iqk_ch[1],
iqk_info->iqk_bw[1] == 0 ? "20M" : (iqk_info->iqk_bw[1] == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S1 NB/WB TXIQK", iqk_info->is_wb_txiqk[1]? "WBTXK" : "NBTXK");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S1 NB/WB RXIQK", iqk_info->is_wb_rxiqk[1]? "WBRXK" : "NBRXK");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S1 LOK status", (iqk_info->lok_cor_fail[0][1] | iqk_info->lok_fin_fail[0][1]) ? "Fail" : "Pass");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S1 TXK status", iqk_info->iqk_tx_fail[0][1]? "Fail" : "Pass");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"S1 RXK status", iqk_info->iqk_rx_fail[0][1]? "Fail" : "Pass");
*_used = used;
*_out_len = out_len;
return;
}
void halrf_iqk_bypass_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#if 1
char *cmd[4] = {"-h", "lok", "txk", "rxk"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
if (!(rf->support_ability & HAL_RF_IQK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"IQK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 4; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"LOK is Bypass!!\n");
halrf_iqk_lok_bypass(rf, 0x0);
halrf_iqk_lok_bypass(rf, 0x1);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TOK is Bypass!!\n");
halrf_iqk_tx_bypass(rf, 0x0);
halrf_iqk_tx_bypass(rf, 0x1);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RXK is Bypass!!\n");
halrf_iqk_rx_bypass(rf, 0x0);
halrf_iqk_rx_bypass(rf, 0x1);
} else {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
}
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_iqk_klog_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#if 1
char *cmd[6] = {"-h", "fft", "sram", "xym", "cfir", "off"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
if (!(rf->support_ability & HAL_RF_IQK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"IQK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 6; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"FFT message turn on!!\n");
halrf_iqk_fft_enable(rf, true);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Sram message turn on!!\n");
halrf_iqk_sram_enable(rf, true);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"XYM message turn on!!\n");
halrf_iqk_xym_enable(rf, true);
} else if (_os_strcmp(input[1], cmd[4]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"CFIR message turn on!!\n");
halrf_iqk_cfir_enable(rf, true);
} else if (_os_strcmp(input[1], cmd[4]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"all message turn off!!\n");
halrf_iqk_fft_enable(rf, false);
halrf_iqk_sram_enable(rf, false);
halrf_iqk_xym_enable(rf, false);
halrf_iqk_cfir_enable(rf, false);
} else {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
}
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_iqk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char *cmd[7] = {"-h", "on", "off", "info", "trigger", "nbiqk", "rxevm"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
u8 rxevm = 0x0;
if (!(rf->support_ability & HAL_RF_IQK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"IQK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 8; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"IQK is Enabled!!\n");
halrf_iqk_onoff(rf, true);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"IQK is Disabled!!\n");
halrf_iqk_onoff(rf, false);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
_halrf_iqk_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0){
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" WBIQK Trigger start!!\n");
halrf_nbiqk_enable(rf, false);
halrf_iqk_trigger(rf, HW_PHY_0, false);
} else if (_os_strcmp(input[1], cmd[5]) == 0){
halrf_nbiqk_enable(rf, true);
halrf_iqk_trigger(rf, val, false);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" NBIQK Trigger!!\n");
} else if (_os_strcmp(input[1], cmd[6]) == 0){
rxevm = halrf_iqk_get_rxevm( rf);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" RXEVM = -%d dB!!\n", rxevm);
} else {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
}
*_used = used;
*_out_len = out_len;
}
void halrf_pwr_table_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
char *cmd[7] = {"-h", "rate", "limit", "limit_ru", "set_all", "set", "txshape"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u32 tmp;
u8 i;
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 7; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Power by rate info\n");
halrf_pwr_by_rate_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Power limit info\n");
halrf_pwr_limit_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Power limit RU info\n");
halrf_pwr_limit_ru_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0) {
pwr->fix_power[RF_PATH_A] = false;
pwr->fix_power_dbm[RF_PATH_A] = 0;
pwr->fix_power[RF_PATH_B] = false;
pwr->fix_power_dbm[RF_PATH_B] = 0;
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Reset Power by Rate, Power limit and Power Limit RU to Default\n");
halrf_set_power(rf, HW_PHY_0, PWR_BY_RATE);
halrf_set_power(rf, HW_PHY_0, PWR_LIMIT);
halrf_set_power(rf, HW_PHY_0, PWR_LIMIT_RU);
#ifndef RTW_FLASH_98D
//halrf_set_power(rf, HW_PHY_1, PWR_BY_RATE);
//halrf_set_power(rf, HW_PHY_1, PWR_LIMIT);
//halrf_set_power(rf, HW_PHY_1, PWR_LIMIT_RU);
#endif
} else if (_os_strcmp(input[1], cmd[5]) == 0) {
_os_sscanf(input[2], "%d", &tmp);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set Power by Rate, Power limit and Power Limit RU %d.%ddBm\n",
tmp / 2, tmp * 10 / 2 % 10);
halrf_set_fix_power_to_struct(rf, HW_PHY_0, (s8)tmp);
} else if (_os_strcmp(input[1], cmd[6]) == 0) {
_os_sscanf(input[2], "%d", &tmp);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set TX Shape = 255, disable Set Tx shape function\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Set TX Shape = %d\n", tmp);
halrf_set_tx_shape(rf, (u8)tmp);
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
}
void halrf_rfk_check_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#if 1
char *cmd[3] = {"-h", "backup", "check"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 3; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RFK backup!!\n");
halrf_rfk_reg_backup(rf);
halrf_rfc_reg_backup(rf);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RFK check!!\n");
#if 1
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[RFK]DACK reg check : %s \n", (halrf_dack_reg_check_fail(rf)) ? "FAIL" : "OK");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[RFK]RFK reg check : %s \n", (halrf_rfk_reg_check_fail(rf))?"FAIL" : "OK");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[RFK]RFC reg check : %s \n", (halrf_rfc_reg_check_fail(rf))?"FAIL" : "OK");
#endif
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_test_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#if 0
u32 used = *_used;
u32 out_len = *_out_len;
u32 val[10] = {0};
u8 i;
for (i = 0; i < 5; i++) {
if (input[i + 1])
HALRF_SCAN(input[i + 1], DCMD_DECIMAL, &val[i]);
}
if (val[0] == 0) {
halrf_rfk_chl_thermal(rf, (u8)val[1], (u8)val[2]);
}else if (val[0] == 1) {
halrf_rfk_recovery_chl_thermal(rf, (u8)val[1], (u8)val[2]);
}
*_used = used;
*_out_len = out_len;
#endif
}
void _halrf_gapk_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
struct halrf_gapk_info *txgapk_info = &rf->gapk;
struct halrf_iqk_info *iqk_info = &rf->iqk;
u8 i;
u8 channel = rf->hal_com->band[0].cur_chandef.center_ch;
u32 bw = rf->hal_com->band[0].cur_chandef.bw;
u32 band = rf->hal_com->band[0].cur_chandef.band;
u32 used = *_used;
u32 out_len = *_out_len;
char *ic_name = NULL;
u32 txgapk_ver = 0;
u32 rf_para = 0;
u32 rfk_init_ver = 0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
ic_name = "8852A";
txgapk_ver = TXGAPK_VER_8852A;
rf_para = halrf_get_radio_reg_ver(rf);
rfk_init_ver = halrf_get_nctl_reg_ver(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
ic_name = "8852B";
txgapk_ver = TXGAPK_VER_8852B;
rf_para = halrf_get_radio_reg_ver(rf);
rfk_init_ver = halrf_get_nctl_reg_ver(rf);
break;
#endif
default:
break;
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"\n===============[ TxGapK info %s ]===============\n", ic_name);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"TxGapK Ver", txgapk_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"RF Para Ver", rf_para);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
"RFK init ver", rfk_init_ver);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d (RFE type:%d)\n",
"Ext_PA 2G / 5G / 6G", rf->fem.epa_2g, rf->fem.epa_5g, rf->fem.epa_6g,
rf->phl_com->dev_cap.rfe_type);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s / %d / %s\n",
"Band / CH / BW", band == BAND_ON_24G ? "2G" : (band == BAND_ON_5G ? "5G" : "6G"),
channel,
bw == 0 ? "20M" : (bw == 1 ? "40M" : "80M"));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"=======================\n");
/* table info */
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"iqk_info->iqk_mcc_ch[0][0]/[0][1]", iqk_info->iqk_mcc_ch[0][0], iqk_info->iqk_mcc_ch[0][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"iqk_info->iqk_mcc_ch[1][0]/[1][1]", iqk_info->iqk_mcc_ch[1][0], iqk_info->iqk_mcc_ch[1][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"iqk_info->iqk_table_idx[0]/[1]", iqk_info->iqk_table_idx[0], iqk_info->iqk_table_idx[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"txgapk_info->txgapk_mcc_ch[0]", txgapk_info->txgapk_mcc_ch[0]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"txgapk_info->txgapk_mcc_ch[1]", txgapk_info->txgapk_mcc_ch[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"txgapk_info->txgapk_table_idx", txgapk_info->txgapk_table_idx);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d\n",
"txgapk_info->ch", txgapk_info->ch[0]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"===============[ TxGapK result ]===============\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %s\n",
"TXGapK OK(last)", (txgapk_info->is_txgapk_ok) ? "TRUE" : "FALSE");
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = 0x%x / 0x%x\n",
"Read0x8010 Befr /Aftr GapK", txgapk_info->r0x8010[0], txgapk_info->r0x8010[1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[ NCTL Done Check Times R_0xbff / R_0x80fc ]\n");
/* txgapk_info->txgapk_chk_cnt[2][2][2]; */ /* path */ /* track pwr */ /* 0xbff8 0x80fc*/
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Path_0 Track", txgapk_info->txgapk_chk_cnt[0][TXGAPK_TRACK][0], txgapk_info->txgapk_chk_cnt[0][TXGAPK_TRACK][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Path_0 PWR",txgapk_info->txgapk_chk_cnt[0][TXGAPK_PWR][0], txgapk_info->txgapk_chk_cnt[0][TXGAPK_PWR][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Path_0 IQKBK", txgapk_info->txgapk_chk_cnt[0][TXGAPK_IQKBK][0], txgapk_info->txgapk_chk_cnt[0][TXGAPK_IQKBK][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Path_1 Track", txgapk_info->txgapk_chk_cnt[1][TXGAPK_TRACK][0], txgapk_info->txgapk_chk_cnt[1][TXGAPK_TRACK][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Path_1 PWR", txgapk_info->txgapk_chk_cnt[1][TXGAPK_PWR][0], txgapk_info->txgapk_chk_cnt[1][TXGAPK_PWR][1]);
RF_DBG_CNSL(out_len, used, output + used, out_len - used, " %-25s = %d / %d\n",
"Path_1 IQKBK", txgapk_info->txgapk_chk_cnt[1][TXGAPK_IQKBK][0], txgapk_info->txgapk_chk_cnt[1][TXGAPK_IQKBK][1]);
for (i = 0; i < 17; i++) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s [%2d] = 0x%02x/ 0x%02x/ 0x%02x/ 0x%02x\n",
"S0: Trk_d/Trk_ta/Pwr_d/Pwr_ta",
i,
txgapk_info->track_d[0][i]&0xff, txgapk_info->track_ta[0][i]&0xff,
txgapk_info->power_d[0][i]&0xff, txgapk_info->power_ta[0][i]&0xff);
}
for (i = 0; i < 17; i++) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s [%2d] = 0x%02x/ 0x%02x/ 0x%02x/ 0x%02x\n",
"S1: Trk_d/Trk_ta/Pwr_d/Pwr_ta",
i,
txgapk_info->track_d[1][i]&0xff, txgapk_info->track_ta[1][i]&0xff,
txgapk_info->power_d[1][i]&0xff, txgapk_info->power_ta[1][i]&0xff);
}
*_used = used;
*_out_len = out_len;
}
void halrf_txgapk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char *cmd[5] = {"-h", "on", "off", "info", "trigger"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u8 i;
if (!(rf->support_ability & HAL_RF_TXGAPK)) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TXGAPK is Unsupported!!!\n");
return;
}
if (_os_strcmp(input[1], cmd[0]) == 0) {
for (i = 1; i < 5; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %s\n", cmd[i]);
} else if (_os_strcmp(input[1], cmd[1]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TXGAPK is Enabled!!\n");
halrf_gapk_enable(rf, val);
} else if (_os_strcmp(input[1], cmd[2]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TXGAPK is Disabled!!\n");
halrf_gapk_disable(rf, val);
} else if (_os_strcmp(input[1], cmd[3]) == 0) {
_halrf_gapk_info(rf, input, &used, output, &out_len);
} else if (_os_strcmp(input[1], cmd[4]) == 0){
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TXGAPK Trigger start!!\n");
_os_sscanf(input[1], "%d", &val);
halrf_gapk_trigger(rf, val, true);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"TXGAPK Trigger finish, TXGAPK ON!!!\n");
} else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" No CMD find!!\n");
*_used = used;
*_out_len = out_len;
}
void halrf_dump_rf_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
char *cmd[1] = {"-h"};
u32 used = *_used;
u32 out_len = *_out_len;
u32 val = 0;
u32 i;
u32 start_addr = 0, end_addr = 0, range_value = 0, path = 0;
_os_sscanf(input[1], "%x", &path);
_os_sscanf(input[2], "%x", &start_addr);
_os_sscanf(input[3], "%x", &range_value);
end_addr = start_addr + range_value;
if (_os_strcmp(input[1], cmd[0]) == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" Command parameters :\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" <rf_path> : 0/1/2/3 = rf-A/B/C/D\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" <offset> : rf start offset (HEX)\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" <num> : number of offset to dump (HEX)\n");
} else if (path < RTW_PHL_MAX_RF_PATH) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" Dump RF Register Path:%d 0x%X ~ 0x%X\n", path, start_addr, end_addr - 1);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" See Result in DebugView or Debug Log\n");
for (i = start_addr; i < end_addr; i = i + 4) {
if (!(i % 4)) {
RF_DBG_VAST(out_len, used, output + used, out_len - used,
" RF-%d (0x%02X) = ", path, i);
}
RF_DBG_VAST(out_len, used, output + used, out_len - used,
"%05X %05X %05X %05X\n",
halrf_rrf(rf, path, i, 0xfffff),
halrf_rrf(rf, path, i + 1, 0xfffff),
halrf_rrf(rf, path, i + 2, 0xfffff),
halrf_rrf(rf, path, i + 3, 0xfffff));
}
RF_DBG_VAST(out_len, used, output + used, out_len - used, "\n\n\n");
for (i = start_addr; i < end_addr; i++) {
RF_DBG_VAST(out_len, used, output + used, out_len - used,
" RF-%d (0x%02X) = %05X\n", path, i,
halrf_rrf(rf, path, i, 0xfffff));
}
} else {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" echo rf dump -h\n");
}
*_used = used;
*_out_len = out_len;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dbg.c
|
C
|
agpl-3.0
| 50,580
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DBG_H__
#define __HALRF_DBG_H__
/*@--------------------------[Define] ---------------------------------------*/
#define HALRF_WATCHDOG_PERIOD 2 /*second*/
#define RFDBG_TRACE_EN
#ifdef RFDBG_TRACE_EN
#define RF_DBG(rf, comp, fmt, ...) \
do {\
if(rf->dbg_component & comp)\
_os_dbgdump("[RF]" fmt, ##__VA_ARGS__);\
} while (0)
#define RF_TRACE(fmt, ...) \
do {\
_os_dbgdump("[RF]" fmt, ##__VA_ARGS__);\
} while (0)
#define RF_WARNING(fmt, ...) \
do {\
_os_dbgdump("[WARNING][RF]" fmt, ##__VA_ARGS__);\
} while (0)
#define RF_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do {\
_os_dbgdump(fmt, ##__VA_ARGS__);\
} while (0)
#define RF_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
#else
#define RF_DBG
#define RF_TRACE
#define RF_WARNING
#define RF_DBG_CNSL /*Print on Consol,CLI */
#define RF_DBG_VAST /*Print to Comport, Debug View*/
#endif
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct rf_info;
void halrf_dbg_setting_init(struct rf_info *rf);
void halrf_iqk_log(struct rf_info *rf);
void halrf_lck_log(struct rf_info *rf);
void halrf_dump_rfk_reg(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_support_ability(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_dbg_trace(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_dpk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_rx_dck_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_dack_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_tssi_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_iqk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halrf_iqk_bypass_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halrf_iqk_klog_cmd(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halrf_pwr_table_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_rfk_check_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_test_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_scanf(char *in, enum rf_scanf_type type, u32 *out);
void halrf_txgapk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_dump_rf_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dbg.h
|
C
|
agpl-3.0
| 4,182
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halrf_precomp.h"
struct halrf_cmd_info {
char name[16];
u8 id;
};
enum HALRF_CMD_ID {
HALRF_HELP,
HALRF_SUPPORTABILITY,
HALRF_DBG_COMP,
HALRF_PROFILE,
HALRF_IQK,
HALRF_IQK_DEBUG,
HALRF_DPK,
HALRF_DACK,
HALRF_DACK_DEBUG,
HALRF_RX_DCK,
HALRF_DUMP_RFK_REG,
HALRF_LO_TEST,
#ifdef CONFIG_2G_BAND_SHIFT
HAL_BAND_SHIFT,
#endif
HALRF_RCK,
HALRF_WATCHDOG,
HALRF_SINGLETONE_EN,
HALRF_IQK_BYPASS,
HALRF_IQK_KLOG,
HALRF_TSSI,
HALRF_PWR_TABLE,
HALRF_IQK_DBCC,
HALRF_RFK_CHECK,
HALRF_RFK_TEST,
HALRF_TXGAPK,
HALRF_FW_IQK,
HALRF_DUMP,
HALRF_IQK_RXIMR,
HALRF_THER,
HALRF_XTAL_TRK,
HALRF_HWTX
};
struct halrf_cmd_info halrf_cmd_i[] = {
{"-h", HALRF_HELP},
{"ability", HALRF_SUPPORTABILITY},
{"dbg", HALRF_DBG_COMP},
{"profile", HALRF_PROFILE},
{"iqk", HALRF_IQK},
{"dpk", HALRF_DPK},
{"dack", HALRF_DACK},
{"dack_dbg", HALRF_DACK_DEBUG},
{"rx_dck", HALRF_RX_DCK},
{"dump_rfk_reg", HALRF_DUMP_RFK_REG},
{"lo_test", HALRF_LO_TEST},
{"rck", HALRF_RCK},
{"rfk_check", HALRF_RFK_CHECK},
#ifdef CONFIG_2G_BAND_SHIFT
{"band_shift", HAL_BAND_SHIFT},
#endif
{"watchdog_stop", HALRF_WATCHDOG},
{"iqk_tone", HALRF_SINGLETONE_EN},
{"iqk_bypass", HALRF_IQK_BYPASS},
{"iqk_klog", HALRF_IQK_KLOG},
{"iqk_dbcc", HALRF_IQK_DBCC},
{"iqk_rximr", HALRF_IQK_RXIMR},
{"tssi", HALRF_TSSI},
{"pwr_table", HALRF_PWR_TABLE},
{"test", HALRF_RFK_TEST},
{"txgapk", HALRF_TXGAPK},
{"iqk_fw", HALRF_FW_IQK},
{"dump", HALRF_DUMP},
{"ther", HALRF_THER},
{"xtal_trk", HALRF_XTAL_TRK},
{"hwtx", HALRF_HWTX},
};
void halrf_cmd_parser(struct rf_info *rf, char input[][RF_MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct rf_dbg_cmd_info *rf_dbg_cmd = &rf->rf_dbg_cmd_i;
u32 used = 0;
u8 id = 0;
u32 i, val_1 = 0, val_2 = 0;
u32 halrf_ary_size = rf_dbg_cmd->cmd_size;
RF_DBG_CNSL(out_len, used, output + used, out_len - used, "\n");
/* Parsing Cmd ID */
if (input_num) {
for (i = 0; i < halrf_ary_size; i++) {
if (_os_strcmp(halrf_cmd_i[i].name, input[0]) == 0) {
id = halrf_cmd_i[i].id;
break;
}
}
if (i == halrf_ary_size) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"HALRF command not found!\n");
return;
}
}
switch (id) {
case HALRF_HELP: {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"RF cmd ==>\n");
for (i = 0; i < halrf_ary_size - 1; i++)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" %-5d: %s\n", i, halrf_cmd_i[i + 1].name);
}
break;
case HALRF_SUPPORTABILITY:
halrf_support_ability(rf, input, &used, output, &out_len);
break;
case HALRF_DBG_COMP:
halrf_dbg_trace(rf, input, &used, output, &out_len);
break;
case HALRF_DUMP_RFK_REG:
halrf_dump_rfk_reg(rf, input, &used, output, &out_len);
break;
case HALRF_IQK:
halrf_iqk_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_DPK:
halrf_dpk_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_DACK:
halrf_dack_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_RX_DCK:
halrf_rx_dck_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_LO_TEST:
_os_sscanf(input[1], "%d", &val_1);
_os_sscanf(input[2], "%d", &val_2);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"S%d LO test %s!!\n", val_2, val_1 ? "on" : "off");
halrf_lo_test(rf, (bool)val_1, val_2);
break;
case HALRF_RCK:
halrf_rck_trigger(rf, HW_PHY_0);
break;
case HALRF_WATCHDOG:
_os_sscanf(input[1], "%d", &val_1);
rf->is_watchdog_stop = (bool)val_1;
if (val_1 == true)
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Halrf watchdog STOP!!\n");
else
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Halrf watchdog GO!!\n");
break;
case HALRF_SINGLETONE_EN:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[IQK]single tone enable => 0: path 0; 1: path 1\n");
_os_sscanf(input[1], "%d", &val_1);
halrf_iqk_toneleakage(rf, val_1 & 0x1);
break;
case HALRF_IQK_BYPASS:
halrf_iqk_bypass_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_IQK_KLOG:
halrf_iqk_klog_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_TSSI:
halrf_tssi_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_PWR_TABLE:
halrf_pwr_table_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_IQK_DBCC:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[IQK]dbcc enable => 0: PHY0; 1: PHY1\n");
_os_sscanf(input[1], "%d", &val_1);
halrf_iqk_dbcc(rf, val_1 & 0x1);
break;
case HALRF_RFK_CHECK:
halrf_rfk_check_reg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_RFK_TEST:
halrf_test_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_TXGAPK:
halrf_txgapk_dbg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_FW_IQK:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[IQK] IQK TYPE => 0: DRV, 1: FW\n");
_os_sscanf(input[1], "%d", &val_1);
halrf_enable_fw_iqk(rf, val_1 & 0x1);
break;
case HALRF_DUMP:
halrf_dump_rf_reg_cmd(rf, input, &used, output, &out_len);
break;
case HALRF_IQK_RXIMR:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"[IQK] -path -idx \n");
_os_sscanf(input[1], "%d", &val_1);
_os_sscanf(input[2], "%d", &val_2);
i= halrf_iqk_get_rximr(rf, (u8)val_1, val_2);
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
" dec, rximr = %d !!\n", i);
break;
case HALRF_THER:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Thermal A: %d\n", halrf_get_thermal(rf, RF_PATH_A));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Thermal B: %d\n", halrf_get_thermal(rf, RF_PATH_B));
break;
case HALRF_XTAL_TRK:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Xtal Tracking offset PHY0 : %d\n",
halrf_xtal_tracking_offset(rf, 0));
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Xtal Tracking offset PHY1 : %d\n",
halrf_xtal_tracking_offset(rf, 1));
break;
case HALRF_HWTX:
{
u32 value[10] = {0};
u8 i;
for (i = 0; i < 4; i++)
if (input[i + 1])
_os_sscanf(input[i + 1], "%d", &value[i]);
if (_os_strcmp(input[1], "-h") == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"echo rf hwtx enable path cnt dB\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Enable / Disable = 1 / 0\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"PathA / PathB = 0 / 1\n");
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"EX:echo rf hwtx 1 0 0 10\n");
}
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"==>Enable:%d Path:%d Count:%d Power:%ddB\n", value[0], value[1], value[2], value[3]);
//halrf_tssi_hw_tx_8852a(rf, 0, path, cnt, dbm, T_HT_MF, 0, enable);
if (value[0] == 1) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"HW TX Start\n");
halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_TSSI, RFK_START);
halrf_tmac_tx_pause(rf, HW_PHY_0, true);
halrf_hw_tx(rf, (u8)value[1], (u16)value[2],
(s16)(value[3] * 4), T_HT_MF, 0, 1);
}
if (value[0] == 0) {
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"HW TX Stop\n");
halrf_hw_tx(rf, (u8)value[1], (u16)value[2],
(s16)(value[3] * 4), T_HT_MF, 0, 0);
halrf_tx_mode_switch(rf, HW_PHY_0, 0);
halrf_tmac_tx_pause(rf, HW_PHY_0, false);
halrf_btc_rfk_ntfy(rf, (BIT(HW_PHY_0) << 4), RF_BTC_TSSI, RFK_STOP);
}
}
break;
default:
RF_DBG_CNSL(out_len, used, output + used, out_len - used,
"Do not support this command\n");
break;
}
}
void halrf_cmd_parser_init(struct rf_info *rf)
{
struct rf_dbg_cmd_info *rf_dbg_cmd = &rf->rf_dbg_cmd_i;
rf_dbg_cmd->cmd_size = sizeof(halrf_cmd_i) / sizeof(struct halrf_cmd_info);
}
#if 0
#ifndef strsep
char *strsep(char **s, const char *ct)
{
char *sbegin = *s;
char tmp = 0;
char *end = &tmp;
if (!sbegin)
return NULL;
//end = strpbrk(sbegin, ct);
if (end)
*end++ = '\0';
*s = end;
return sbegin;
}
#endif
#endif
s32 halrf_cmd(struct rf_info *rf, char *input, char *output, u32 out_len)
{
char *token;
u32 argc = 0;
char argv[RF_MAX_ARGC][RF_MAX_ARGV];
do {
token = _os_strsep(&input, ", "); //smae name in bb
if (token) {
if (_os_strlen(token) <= RF_MAX_ARGV)
_os_strcpy(argv[argc], token);
argc++;
} else {
break;
}
} while (argc < RF_MAX_ARGC);
if (argc == 1)
argv[0][_os_strlen(argv[0]) - 1] = '\0';
halrf_cmd_parser(rf, argv, argc, output, out_len);
return 0;
}
u32 halrf_get_multiple(u8 pow, u8 base)
{
u8 i;
u32 return_value = 1;
for (i = 0; i < pow; i++)
return_value *= base; /*base ^ pow*/
return return_value;
}
u32 halrf_str_2_dec(u8 val)
{
if (val >= 0x30 && val <= 0x39) /*0~9*/
return (val - 0x30);
else if (val >= 0x41 && val <= 0x46) /*A~F*/
return (val - 0x41 + 10);
else if (val >= 0x61 && val <= 0x66) /*a~f*/
return (val - 0x61 + 10);
else
return 1;
}
void halrf_scanf(char *in, enum rf_scanf_type type, u32 *out)
{
char buff[HALRF_DCMD_SCAN_LIMIT];
u32 multiple = 1;
u8 text_num = 0;
u8 base = 10;
u8 i = 0, j = 0;
*out = 0;
for (i = 0; i < HALRF_DCMD_SCAN_LIMIT; i++) {
if (in[i] != 0x0) { /* 0x0 = NULL. */
buff[i] = in[i];
continue;
}
if (type == DCMD_CHAR) {
*out = *in;
break;
}
base = (type == DCMD_DECIMAL) ? 10 : 16;
text_num = i;
for (j = 0; j < text_num; j++) {
multiple = halrf_get_multiple(text_num - 1 - j, base);
*out += halrf_str_2_dec(buff[j]) * multiple;
}
break;
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dbg_cmd.c
|
C
|
agpl-3.0
| 10,327
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_DBG_CMD_H_
#define _HALRF_DBG_CMD_H_
/*@--------------------------[Define] ---------------------------------------*/
#define RF_MAX_ARGC 20
#define RF_MAX_ARGV 16
#define HALRF_SCAN halrf_scanf
#define HALRF_DCMD_SCAN_LIMIT 10
/*@--------------------------[Enum]------------------------------------------*/
enum rf_scanf_type
{
DCMD_DECIMAL = 1,
DCMD_HEX = 2,
DCMD_CHAR = 3,
};
/*@--------------------------[Structure]-------------------------------------*/
struct rf_dbg_cmd_info {
u8 cmd_size;
};
/*@--------------------------[Prptotype]-------------------------------------*/
void halrf_cmd_parser_init(struct rf_info *rf);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dbg_cmd.h
|
C
|
agpl-3.0
| 1,309
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DBG_CMD_EX_H__
#define __HALRF_DBG_CMD_EX_H__
#define RF_MAX_ARGV 16
struct rf_info;
s32 halrf_cmd(struct rf_info *rf, char *input, char *output, u32 out_len);
void halrf_cmd_parser(struct rf_info *rf, char input[][RF_MAX_ARGV],
u32 input_num, char *output, u32 out_len);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dbg_cmd_ex.h
|
C
|
agpl-3.0
| 1,277
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_DPK_H__
#define __HALRF_DPK_H__
/*@--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_DPK 8
#define THERMAL_DPK_AVG_NUM 1
#if defined (RF_8852A_SUPPORT) || defined (RF_8852B_SUPPORT)
#define KPATH 2
#else
#define KPATH 1
#endif
#define DPK_BKUP_NUM 2
enum dpk_id {
LBK_RXIQK = 0x06,
SYNC = 0x10,
MDPK_IDL = 0x11,
MDPK_MPA = 0x12,
GAIN_LOSS = 0x13,
GAIN_CAL = 0x14,
DPK_RXAGC = 0x15,
KIP_PRESET = 0x16,
KIP_RESTORE = 0x17,
DPK_TXAGC = 0x19
};
struct dpk_bkup_para {
enum band_type band; /* 2.4G,5G,6G*/
enum channel_width bw;
u8 ch;
u8 path_ok;
u8 txagc_dpk; /*txagc@dpk with path*/
u8 ther_dpk; /*thermal@dpk with path*/
//u8 trk_idx_dpk; /*track_idx@dpk with path*/
//u8 ther_tssi; /*thermal@tssi with path*/
u8 gs;
u16 pwsf;
};
/*@---------------------------End Define Parameters---------------------------*/
struct halrf_dpk_info {
bool is_dpk_enable;
bool is_dpk_reload_en;
u8 dpk_gs[2]; /*PHY*/
u8 ther_avg[KPATH][AVG_THERMAL_NUM_DPK]; /*path*/
u8 pre_pwsf[KPATH];
u8 ther_avg_idx;
u32 dpk_cal_cnt;
u32 dpk_ok_cnt;
u32 dpk_reload_cnt;
u16 dc_i[KPATH][DPK_BKUP_NUM]; /*path*/
u16 dc_q[KPATH][DPK_BKUP_NUM]; /*path*/
u8 corr_val[KPATH][DPK_BKUP_NUM]; /*path*/
u8 corr_idx[KPATH][DPK_BKUP_NUM]; /*path*/
u8 cur_idx[KPATH]; /*path*/
struct dpk_bkup_para bp[KPATH][DPK_BKUP_NUM]; /*path/index*/
};
#endif /*__HALRF_DPK_H__*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_dpk.h
|
C
|
agpl-3.0
| 2,103
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_ex.c
|
C
|
agpl-3.0
| 651
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_EX_H__
#define __HALRF_EX_H__
struct rf_info;
/**************halrf.c**************/
void halrf_watchdog(void *rf_void);
enum rtw_hal_status halrf_chl_rfk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force);
enum rtw_hal_status halrf_dack_trigger(void *rf_void, bool force);
enum rtw_hal_status halrf_rx_dck_trigger(void *rf_void,
enum phl_phy_idx phy_idx, bool is_afe);
enum rtw_hal_status halrf_iqk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force);
void halrf_lck_trigger(void *rf_void);
enum rtw_hal_status halrf_dpk_trigger(void *rf_void,
enum phl_phy_idx phy_idx,
bool force);
enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx);
enum rtw_hal_status halrf_gapk_trigger(void *rf_void,
enum phl_phy_idx phy_idx, bool force);
enum rtw_hal_status halrf_gapk_enable(void *rf_void,
enum phl_phy_idx phy_idx);
enum rtw_hal_status halrf_gapk_disable(void *rf_void,
enum phl_phy_idx phy_idx);
void halrf_rck_trigger(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_iqk_onoff(void *rf_void, bool is_enable);
void halrf_dpk_onoff(void *rf_void, bool is_enable);
void halrf_dpk_track_onoff(void *rf_void, bool is_enable);
void halrf_dpk_switch(void *rf_void, bool is_enable);
void halrf_dpk_init(void *rf_void);
void halrf_rx_dck_onoff(void *rf_void, bool is_enable);
void halrf_gapk_onoff(void *rf_void, bool is_enable);
void halrf_dack_onoff(void *rf_void, bool is_enable);
void halrf_tssi_onoff(void *rf_void, bool is_enable);
bool halrf_get_iqk_onoff(void *rf_void);
bool halrf_get_dpk_onoff(void *rf_void);
bool halrf_get_dpk_track_onoff(void *rf_void);
bool halrf_get_gapk_onoff(void *rf_void);
bool halrf_get_dack_onoff(void *rf_void);
bool halrf_get_tssi_onoff(void *rf_void);
void halrf_lo_test(void *rf_void, bool is_on, enum rf_path path);
int halrf_get_predefined_pw_lmt_regu_type_from_str(const char *str);
const char * const *halrf_get_predefined_pw_lmt_regu_type_str_array(u8 *num);
const char *halrf_get_pw_lmt_regu_type_str(struct rf_info *rf, u8 band);
s8 halrf_get_power_by_rate(struct rf_info *rf,
enum phl_phy_idx phy,
u8 rf_path, u16 rate, u8 dcm, u8 offset);
s8 halrf_get_power_by_rate_band(struct rf_info *rf,
enum phl_phy_idx phy, u16 rate, u8 dcm, u8 offset, u32 band);
s8 halrf_get_power_limit(struct rf_info *rf,
enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
u8 beamforming, u8 tx_num, u8 channel);
s8 halrf_get_power_limit_ru(struct rf_info *rf,
enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
u8 tx_num, u8 channel);
s16 halrf_get_power(void *rf_void,
u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth,
u8 beamforming, u8 channel);
u8 halrf_get_thermal(void *rf_void, u8 rf_path);
u32 halrf_get_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path);
s32 halrf_get_online_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path, s32 dbm, s32 puot);
void halrf_set_tssi_de_for_tx_verify(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de, u8 path);
void halrf_set_tssi_de_offset(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de_offset, u8 path);
void halrf_set_tssi_avg_mp(void *rf_void, enum phl_phy_idx phy_idx, s32 xdbm);
void halrf_set_rx_gain_offset_for_rx_verify(void *rf_void, enum phl_phy_idx phy,
s8 rx_gain_offset, u8 path);
void halrf_set_power_track(void *rf_void, enum phl_phy_idx phy_idx, u8 value);
u8 halrf_get_power_track(void *rf_void);
void halrf_tssi_get_efuse_ex(void *rf_void, enum phl_phy_idx phy_idx);
bool halrf_tssi_check_efuse_data(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_set_ref_power_to_struct(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_bf_config_rf(void *rf_void);
void halrf_rfk_reg_backup(void *rf_void);
void halrf_rfc_reg_backup(void *rf_void);
bool halrf_rfc_reg_check_fail(void *rf_void);
bool halrf_rfk_reg_check_fail(void *rf_void);
bool halrf_dack_reg_check_fail(void *rf_void);
bool halrf_rfk_chl_thermal(void *rf_void, u8 chl_index, u8 ther_index);
void halrf_rfk_recovery_chl_thermal(void *rf_void, u8 chl_index);
u8 halrf_fcs_get_thermal_index(void *rf_void);
/**************halrf_init.c**************/
enum rtw_hal_status halrf_dm_init(void *rf_void);
enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void **rf_out);
void halrf_deinit(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void *rf);
/**************halrf_hw_cfg.c**************/
bool halrf_init_reg_by_hdr(void *rf_void);
bool halrf_nctl_init_reg_by_hdr(void *rf_void);
bool halrf_config_radio_a_reg(void *rf_void, bool is_form_folder,
u32 folder_len, u32 *folder_array);
bool halrf_config_radio_b_reg(void *rf_void, bool is_form_folder,
u32 folder_len, u32 *folder_array);
bool halrf_config_store_power_by_rate(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array);
bool halrf_config_store_power_limit(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array);
bool halrf_config_store_power_limit_ru(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array);
bool halrf_config_store_power_track(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array);
bool halrf_config_store_xtal_track(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array);
void halrf_gapk_save_tx_gain(struct rf_info *rf);
void halrf_gapk_reload_tx_gain(struct rf_info *rf);
/*******************************************/
void halrf_dack_recover(void *rf_void,
u8 offset,
enum rf_path path,
u32 val,
bool reload);
bool halrf_set_power(struct rf_info *rf, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table);
bool halrf_get_efuse_power_table_switch(struct rf_info *rf, enum phl_phy_idx phy_idx);
void halrf_set_power_table_switch(struct rf_info *rf,
enum phl_phy_idx phy, u8 pwr_by_rate, u8 pwr_limt);
bool halrf_get_efuse_info(void *rf_void, u8 *efuse_map,
enum rtw_efuse_info id, void *value, u32 length,
u8 autoload_status);
bool halrf_set_dbcc(void *rf_void, bool dbcc_en);
bool halrf_wl_tx_power_control(void *rf_void, u32 tx_power_val);
void halrf_get_efuse_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_get_efuse_trim(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_do_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx);
enum rtw_hal_status halrf_dpk_tracking(void *rf_void);
enum rtw_hal_status halrf_tssi_tracking(void *rf_void);
enum rtw_hal_status halrf_tssi_tracking_clean(void *rf_void, s16 power_dbm);
u8 halrf_get_default_rfe_type(void *rf_void);
u8 halrf_get_default_xtal(void *rf_void);
void halrf_power_limit_set_ext_pwr_limit_table(struct rf_info *rf,
enum phl_phy_idx phy);
void halrf_power_limit_set_ext_pwr_limit_ru_table(struct rf_info *rf,
enum phl_phy_idx phy);
enum rtw_hal_status halrf_iqk_tracking(void *rf_void);
bool halrf_iqk_get_ther_rek(void *rf_void);
void halrf_psd_init(void *rf_void, enum phl_phy_idx phy,
u8 path, u8 iq_path, u32 avg, u32 fft);
void halrf_psd_restore(void *rf_void, enum phl_phy_idx phy);
u32 halrf_psd_get_point_data(void *rf_void, enum phl_phy_idx phy, s32 point);
void halrf_psd_query(void *rf_void, enum phl_phy_idx phy,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf);
void halrf_config_radio_to_fw(void *rf_void);
void halrf_set_fix_power_to_struct(void *rf_void,
enum phl_phy_idx phy, s8 dbm);
void halrf_pwr_by_rate_info(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_pwr_limit_info(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_pwr_limit_ru_info(struct rf_info *rf,
char input[][16], u32 *_used, char *output, u32 *_out_len);
void halrf_get_tssi_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halrf_get_tssi_trk_info(struct rf_info *rf, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halrf_set_tx_shape(struct rf_info *rf, u8 tx_shape_idx);
void halrf_disconnect_notify(void *rf_void, struct rtw_chan_def *chandef);
bool halrf_check_mcc_ch(void *rf_void, struct rtw_chan_def *chandef );
void halrf_ctl_bw(void *rf_void, enum channel_width bw);
void halrf_ctl_ch(void *rf_void, u8 central_ch);
void halrf_rxbb_bw(void *rf_void, enum phl_phy_idx phy, enum channel_width bw);
void halrf_ctrl_bw_ch(void *rf_void, enum phl_phy_idx phy, u8 central_ch,
enum band_type band, enum channel_width bw);
void halrf_fw_ntfy(void *rf_void, enum phl_phy_idx phy_idx);
u32 halrf_get_nctl_reg_ver(struct rf_info *rf);
u32 halrf_get_radio_reg_ver(struct rf_info *rf);
void halrf_config_nctl_reg(struct rf_info *rf);
void halrf_set_gpio(void *rf_void, enum phl_phy_idx phy, u8 band);
bool halrf_check_efem(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_set_regulation_from_driver(void *rf_void, u8 regulation_idx);
void halrf_set_regulation_init(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_tssi_default_txagc(void *rf_void,
enum phl_phy_idx phy_idx, bool enable);
void halrf_tssi_set_avg(void *rf_void,
enum phl_phy_idx phy_idx, bool enable);
void halrf_wifi_event_notify(void *rf_void,
enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
void halrf_2g_rxant(void *rf_void, enum halrf_ant ant);
s8 halrf_get_ther_protected_threshold(void *rf_void);
void halrf_tssi_set_efuse_to_de(void *rf_void,
enum phl_phy_idx phy_idx);
void halrf_tssi_scan_ch(void *rf_void, enum rf_path path);
bool halrf_mac_set_pwr_reg(void *rf_void, enum phl_phy_idx phy,
u32 addr, u32 mask, u32 val);
u32 halrf_mac_get_pwr_reg(void *rf_void, enum phl_phy_idx phy,
u32 addr, u32 mask);
s8 halrf_get_ther_protected_threshold(void *rf_void);
s8 halrf_xtal_tracking_offset(void *rf_void, enum phl_phy_idx phy_idx);
void halrf_hw_tx(void *rf_void, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw,
bool enable);
void halrf_set_mp_regulation(void *rf_void, enum phl_phy_idx phy, u8 regulation);
u32 halrf_tssi_get_final(void *rf_void, enum phl_phy_idx phy_idx, u8 path);
void halrf_tssi_backup_txagc(struct rf_info *rf, enum phl_phy_idx phy, bool enable);
void halrf_reload_pwr_limit_tbl_and_set(struct rf_info *rf,
enum phl_phy_idx phy, enum phl_pwr_table pwr_table);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_ex.h
|
C
|
agpl-3.0
| 11,453
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_EXPORT_FUN_H__
#define __HALRF_EXPORT_FUN_H__
#if 1
#include "halrf_ic_hw_info.h"
#include "halrf_hw_cfg_ex.h"
#include "halrf_init_ex.h"
#include "halrf_ex.h"
#include "halrf_dbg_cmd_ex.h"
#ifdef RF_8852A_SUPPORT
#include "halrf_8852a/halrf_8852a_api_ex.h"
#endif
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_export_fun.h
|
C
|
agpl-3.0
| 1,264
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_HEADERS_H_
#define _HALRF_HEADERS_H_
#include "../../hal_headers_le.h"
#include "halrf_struct.h"
#endif /*_HALRF_HEADERS_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_headers.h
|
C
|
agpl-3.0
| 791
|