code
stringlengths 1
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stringlengths 6
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stringclasses 222
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/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halrf_precomp.h"
bool halrf_init_reg_by_hdr(void *rf_void)
{
bool result = true;
#if 0
struct rf_info *rf = (struct rf_info *)rf_void;
#ifdef RF_8852A_SUPPORT
if (rf->ic_type == RF_RTL8852A) {
halrf_config_8852a_radio_a_reg(rf, is_form_folder,
folder_len, folder_array);
halrf_config_8852a_radio_b_reg(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#endif
return result;
}
bool halrf_nctl_init_reg_by_hdr(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (rf->ic_type == RF_RTL8852A) {
halrf_config_8852a_nctl_reg(rf);
}
#endif
#ifdef RF_8852B_SUPPORT
if (rf->ic_type == RF_RTL8852B) {
halrf_config_8852b_nctl_reg(rf);
}
#endif
return result;
}
bool halrf_config_radio_a_reg(void *rf_void, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_radio_a_reg(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_radio_a_reg(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
bool halrf_config_radio_b_reg(void *rf_void, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_radio_b_reg(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_radio_b_reg(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
bool halrf_config_store_power_by_rate(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_store_power_by_rate(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_store_power_by_rate(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
bool halrf_config_store_power_limit(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_store_power_limit(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_store_power_limit(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
bool halrf_config_store_power_limit_ru(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_store_power_limit_ru(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_store_power_limit_ru(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
bool halrf_config_store_power_track(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_store_pwr_track(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_store_pwr_track(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
bool halrf_config_store_xtal_track(void *rf_void,
bool is_form_folder, u32 folder_len, u32 *folder_array)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_config_8852a_store_xtal_track(rf, is_form_folder,
folder_len, folder_array);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_config_8852b_store_xtal_track(rf, is_form_folder,
folder_len, folder_array);
}
#endif
return result;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_hw_cfg.c
|
C
|
agpl-3.0
| 5,882
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_HW_CFG_H__
#define __HALRF_HW_CFG_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_hw_cfg.h
|
C
|
agpl-3.0
| 1,354
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_HW_CFG_EX_H_
#define _HALRF_HW_CFG_EX_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct rf_info;
bool halrf_init_reg_by_hdr(void *rf_void);
bool halrf_nctl_init_reg_by_hdr(void *rf_void);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_hw_cfg_ex.h
|
C
|
agpl-3.0
| 1,462
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALRF_HWIMG_H_
#define _HALRF_HWIMG_H_
#define RADIO_TO_FW_PAGE_SIZE 6
#define RADIO_TO_FW_DATA_SIZE 500
struct halrf_radio_info {
u32 write_times_a;
u32 write_times_b;
u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
};
#endif /* _HALRF_HW_IMG_8852A_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_hwimg.h
|
C
|
agpl-3.0
| 1,331
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_IC_HW_INFO_H__
#define __HALRF_IC_HW_INFO_H__
enum halrf_ic {
RF_RTL8852A = BIT(0),
RF_RTL8852B = BIT(1),
RF_RTL8834A = BIT(2),
RF_RTL8852C = BIT(3),
};
#define RF_N_1SS 0
#define RF_N_2SS 0
#define RF_N_3SS 0
#define RF_N_4SS 0
#define RF_AC_1SS 0
#define RF_AC_2SS 0
#define RF_AC_3SS 0
#define RF_AC_4SS 0
#define RF_AX_1SS 0
#define RF_AX_2SS (RF_RTL8852A | RF_RTL8852B | RF_RTL8852C)
#define RF_AX_3SS 0
#define RF_AX_4SS (RTL8834A)
/*@====the following macro DO NOT need to update when adding a new IC======= */
#define RF_1SS (RF_N_1SS | RF_AC_1SS | RF_AX_1SS)
#define RF_2SS (RF_N_2SS | RF_AC_2SS | RF_AX_2SS)
#define RF_3SS (RF_N_3SS | RF_AC_3SS | RF_AX_3SS)
#define RF_4SS (RF_N_4SS | RF_AC_4SS | RF_AX_4SS)
#define RF_N_SERIES (RF_N_1SS | RF_N_2SS | RF_N_3SS |\
RF_N_4SS)
#define RF_AC_SERIES (RF_AC_1SS | RF_AC_2SS |\
RF_AC_3SS | RF_AC_4SS)
#define RF_AX_SERIES (RF_AX_1SS | RF_AX_2SS |\
RF_AX_3SS | RF_AX_4SS)
/*@==========================================================================*/
/*@==========================================================================*/
/*@==========================================================================*/
/*@==========================================================================*/
/****************************************************************
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
***************************************************************/
enum rf_path_bit {
RF_A = BIT(0),
RF_B = BIT(1),
RF_C = BIT(2),
RF_D = BIT(3),
RF_AB = (RF_A | RF_B),
RF_AC = (RF_A | RF_C),
RF_AD = (RF_A | RF_D),
RF_BC = (RF_B | RF_C),
RF_BD = (RF_B | RF_D),
RF_CD = (RF_C | RF_D),
RF_ABC = (RF_A | RF_B | RF_C),
RF_ABD = (RF_A | RF_B | RF_D),
RF_ACD = (RF_A | RF_C | RF_D),
RF_BCD = (RF_B | RF_C | RF_D),
RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
};
enum halrf_ant {
RF_MAIN_ANT = 1,
RF_AUX_ANT = 2,
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_ic_hw_info.h
|
C
|
agpl-3.0
| 3,024
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_IC_SW_INFO_H__
#define __HALRF_IC_SW_INFO_H__
#define HLARF_CODE_BASE "HALRF_TRUNK"
#define HALRF_RELEASE_DATE "20200106.0"
/****************************************************************
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
***************************************************************/
enum halrf_api_host {
RUN_IN_FW = 0,
RUN_IN_DRIVER = 1
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_ic_sw_info.h
|
C
|
agpl-3.0
| 1,466
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halrf_precomp.h"
void halrf_cmn_info_self_init(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
if (hal_i->chip_id == CHIP_WIFI6_8852A)
rf->ic_type = RF_RTL8852A;
else if (hal_i->chip_id == CHIP_WIFI6_8834A)
rf->ic_type = RF_RTL8834A;
else if (hal_i->chip_id == CHIP_WIFI6_8852B)
rf->ic_type = RF_RTL8852B;
else if (hal_i->chip_id == CHIP_WIFI6_8852C)
rf->ic_type = RF_RTL8852C;
if (rf->ic_type & RF_AX_1SS)
rf->num_rf_path = 1;
else if (rf->ic_type & RF_AX_2SS)
rf->num_rf_path = 2;
else if (rf->ic_type & RF_AX_3SS)
rf->num_rf_path = 3;
else if (rf->ic_type & RF_AX_4SS)
rf->num_rf_path = 4;
else
rf->num_rf_path = 1;
rf->manual_support_ability = 0xffffffff;
rf->rf_init_ready = false;
rf->rf_sys_up_time = 0;
rf->rf_watchdog_en = true;
rf->rf_ic_api_en = true;
/*[Drv Dbg Info]*/
rf->dbg_component = 0;
rf->cmn_dbg_msg_period = 2;
rf->cmn_dbg_msg_cnt = 0;
/*@=== [HALRF Structure] ============================================*/
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
rf->rfk_iqk_info = &rf_iqk_hwspec_8852a;
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
rf->rfk_iqk_info = &rf_iqk_hwspec_8852b;
break;
#endif
default:
break;
}
}
void halrf_rfk_self_init(struct rf_info *rf)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
struct halrf_gapk_info *txgapk_info = &rf->gapk;
u8 path;
RF_DBG(rf, DBG_RF_RFK, "===> %s\n", __func__);
/* [TXGAPK init] */
txgapk_info->is_gapk_init = false;
/*[IQK init]*/
iqk_info->is_iqk_init = false;
/*[DPK init]*/
halrf_dpk_init(rf);
/*[RXBB BW]*/
for (path = 0; path < KPATH; path++)
rf->pre_rxbb_bw[path] = 0xff;
}
void halrf_rfability_init_mp(struct rf_info *rf)
{
//u64 support_ability = 0;
switch (rf->ic_type) {
#ifdef RF_8852A_SUPPORT
case RF_RTL8852A:
rf->support_ability |=
/*HAL_RF_TX_PWR_TRACK |*/
HAL_RF_TSSI_TRK |
HAL_RF_IQK |
/*HAL_RF_LCK |*/
HAL_RF_DPK |
HAL_RF_DACK |
HAL_RF_TXGAPK |
HAL_RF_DPK_TRACK |
HAL_RF_RXDCK |
HAL_RF_RXGAINK |
HAL_RF_THER_TRIM |
HAL_RF_PABIAS_TRIM |
HAL_RF_TSSI_TRIM |
/*HAL_RF_XTAL_TRACK |*/
0;
break;
#endif
#ifdef RF_8852B_SUPPORT
case RF_RTL8852B:
rf->support_ability |=
/*HAL_RF_TX_PWR_TRACK |*/
HAL_RF_IQK |
/*HAL_RF_LCK |*/
HAL_RF_DPK |
HAL_RF_DACK |
HAL_RF_TXGAPK |
HAL_RF_DPK_TRACK |
HAL_RF_RXDCK |
/*HAL_RF_RXGAINK |*/
HAL_RF_THER_TRIM |
HAL_RF_PABIAS_TRIM |
HAL_RF_TSSI_TRIM |
/*HAL_RF_XTAL_TRACK |*/
HAL_RF_TX_SHAPE |
0;
break;
#endif
#ifdef RF_8852C_SUPPORT
case RF_RTL8852C:
rf->support_ability =
/*HAL_RF_TX_PWR_TRACK |*/
/*HAL_RF_IQK |*/
/*HAL_RF_LCK |*/
/*HAL_RF_DPK |*/
/*HAL_RF_DACK |*/
/*HAL_RF_TXGAPK |*/
/*HAL_RF_DPK_TRACK |*/
0;
break;
#endif
default:
rf->support_ability =
/*HAL_RF_TX_PWR_TRACK |*/
/*HAL_RF_IQK |*/
/*HAL_RF_LCK |*/
/*HAL_RF_DPK |*/
/*HAL_RF_DACK |*/
/*HAL_RF_TXGAPK |*/
/*HAL_RF_DPK_TRACK |*/
0;
break;
}
}
void halrf_rfability_init(struct rf_info *rf)
{
switch (rf->ic_type) {
#ifdef RF_8852A_SUPPORT
case RF_RTL8852A:
rf->support_ability =
HAL_RF_TX_PWR_TRACK |
HAL_RF_TSSI_TRK |
HAL_RF_IQK |
/*HAL_RF_LCK |*/
HAL_RF_DPK |
HAL_RF_DACK |
HAL_RF_TXGAPK |
HAL_RF_DPK_TRACK |
HAL_RF_RXDCK |
HAL_RF_RXGAINK |
HAL_RF_THER_TRIM |
HAL_RF_PABIAS_TRIM |
HAL_RF_TSSI_TRIM |
HAL_RF_XTAL_TRACK |
0;
break;
#endif
#ifdef RF_8852B_SUPPORT
case RF_RTL8852B:
rf->support_ability |=
HAL_RF_TX_PWR_TRACK |
HAL_RF_IQK |
/*HAL_RF_LCK |*/
HAL_RF_DPK |
HAL_RF_DACK |
HAL_RF_TXGAPK |
HAL_RF_DPK_TRACK |
HAL_RF_RXDCK |
/*HAL_RF_RXGAINK |*/
HAL_RF_THER_TRIM |
HAL_RF_PABIAS_TRIM |
HAL_RF_TSSI_TRIM |
/*HAL_RF_XTAL_TRACK |*/
HAL_RF_TX_SHAPE |
0;
break;
#endif
#ifdef RF_8852C_SUPPORT
case RF_RTL8852C:
rf->support_ability |=
/*HAL_RF_TX_PWR_TRACK |*/
/*HAL_RF_IQK |*/
/*HAL_RF_LCK |*/
/*HAL_RF_DPK |*/
/*HAL_RF_DACK |*/
/*HAL_RF_TXGAPK |*/
/*HAL_RF_DPK_TRACK |*/
0;
break;
#endif
default:
rf->support_ability =
/*HAL_RF_TX_PWR_TRACK |*/
/*HAL_RF_IQK |*/
/*HAL_RF_LCK |*/
/*HAL_RF_DPK |*/
/*HAL_RF_DACK |*/
/*HAL_RF_TXGAPK |*/
/*HAL_RF_DPK_TRACK |*/
0;
break;
}
}
void halrf_set_rfability(struct rf_info *rf)
{
if (rf->manual_support_ability &&
rf->manual_support_ability != 0xffffffff)
rf->support_ability = rf->manual_support_ability;
else if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP)
halrf_rfability_init_mp(rf);
else
halrf_rfability_init(rf);
PHL_INFO("[PHL]%x\n", rf->dbg_component);
RF_DBG(rf, DBG_RF_INIT,
"IC = ((0x%x)), mp=%d, RF_Supportability Init = ((0x%x))\n",
rf->ic_type, rf->phl_com->drv_mode, rf->support_ability);
}
void halrf_rfe_init(struct rf_info *rf)
{
u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
switch (rf->ic_type) {
#ifdef RF_8852A_SUPPORT
case RF_RTL8852A:
/*2G FEM check*/
if (rfe_type == 11 || rfe_type == 12 || rfe_type == 17 ||
rfe_type == 18 || rfe_type == 51 || rfe_type == 52 ||
rfe_type == 53 || rfe_type == 54) {
rf->fem.epa_2g = 1;
rf->fem.elna_2g = 1;
}
/*5G FEM check*/
if (rfe_type == 9 || rfe_type == 10 || rfe_type == 11 ||
rfe_type == 12 || rfe_type == 15 || rfe_type == 16 ||
rfe_type == 17 || rfe_type == 18 || rfe_type == 37 ||
rfe_type == 38 || rfe_type == 51 || rfe_type == 52 ||
rfe_type == 53 || rfe_type == 54) {
rf->fem.epa_5g = 1;
rf->fem.elna_5g = 1;
}
/*6G FEM check*/
if (rfe_type == 13 || rfe_type == 14 || rfe_type == 15 ||
rfe_type == 16 || rfe_type == 17 || rfe_type == 18 ||
rfe_type == 37 || rfe_type == 38 || rfe_type == 51 ||
rfe_type == 52 || rfe_type == 53 ||
rfe_type == 54) {
rf->fem.epa_6g = 1;
rf->fem.elna_6g = 1;
}
break;
#endif
default:
break;
}
}
void halrf_rfe_type_gpio_setting(struct rf_info *rf)
{
u32 band = rf->hal_com->band[HW_PHY_0].cur_chandef.band;
RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__);
halrf_set_gpio(rf, HW_PHY_0, (u8)band);
}
enum rtw_hal_status halrf_dm_init(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
if (!rf) {
RF_DBG(rf, DBG_RF_INIT, "[%s] *rf = NULL", __func__);
return RTW_HAL_STATUS_FAILURE;
}
halrf_cmn_info_self_init(rf);
halrf_dbg_setting_init(rf);
halrf_cmd_parser_init(rf);
halrf_set_rfability(rf);
halrf_rfe_init(rf);
halrf_rfe_type_gpio_setting(rf);
halrf_config_nctl_reg(rf);
halrf_rfk_self_init(rf);
/*Set Power table ref power*/
halrf_set_ref_power_to_struct(rf, HW_PHY_0);
halrf_rck_trigger(rf, HW_PHY_0);
//halrf_gapk_save_tx_gain_8852a(rf);
halrf_dack_trigger(rf, false);
halrf_rx_dck_trigger(rf, HW_PHY_0, true);
/*RX Gain K Get efuse*/
/*halrf_get_efuse_rx_gain_k(rf, HW_PHY_0);*/
/*Thermal Trim, PA Bias k, TSSI Trim get efuse and set reg*/
halrf_get_efuse_trim(rf, HW_PHY_0);
/*TSSI Init*/
halrf_tssi_get_efuse_ex(rf, HW_PHY_0);
/*halrf_tssi_get_efuse_ex(rf, HW_PHY_1);*/
/*Set MAC 0xd220[1]=0 r_txagc_BT_en=0 by Bryant*/
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP)
halrf_wl_tx_power_control(rf, 0xffffffff);
halrf_fcs_init(rf);
return hal_status;
}
enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void **rf_out)
{
//enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct rf_info *rf = NULL;
rf = hal_mem_alloc(hal_com, sizeof(struct rf_info));
if (!rf)
return RTW_HAL_STATUS_RF_INIT_FAILURE;
*rf_out = rf;
// PHL_INFO("[PHL] %s - halrf(%p), *rf(%p)\n", __func__, halrf, *rf);
// PHL_INFO("[PHL] %s\n", __func__);
rf->phl_com = phl_com;/*shared memory for all components*/
rf->hal_com = hal_com;/*shared memory for phl and hal*/
return RTW_HAL_STATUS_SUCCESS;
}
void halrf_deinit(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void *rf)
{
//enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct rf_info *halrf = (struct rf_info *)rf;
/*stop FSM of RF or free memory*/
PHL_INFO("[PHL] %s - halrf(%p)\n", __func__, halrf);
if(halrf) {
hal_mem_free(hal_com, halrf, sizeof(struct rf_info));
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_init.c
|
C
|
agpl-3.0
| 8,922
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_INIT_H_
#define _HALRF_INIT_H_
#include "../../hal_headers_le.h"
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct rf_info;
void halrf_cmn_info_self_init(struct rf_info *rf);
void halrf_rfability_init_mp(struct rf_info *rf);
void halrf_rfability_init(struct rf_info *rf);
void halrf_set_rfability(struct rf_info *rf);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_init.h
|
C
|
agpl-3.0
| 1,277
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_INIT_EX_H_
#define _HALRF_INIT_EX_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
#if 0
struct rf_info;
void halrf_cmn_info_self_init(struct rf_info *rf);
void halrf_rfability_init_mp(struct rf_info *rf);
void halrf_rfability_init(struct rf_info *rf);
void halrf_set_rfability(struct rf_info *rf);
enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void **rf_out);
void halrf_deinit(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void *rf);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_init_ex.h
|
C
|
agpl-3.0
| 1,472
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halrf_precomp.h"
u32 halrf_get_sys_time(struct rf_info *rf)
{
return 0;
}
u32 halrf_cal_bit_shift(u32 bit_mask)
{
u32 i;
for (i = 0; i <= 31; i++) {
if ((bit_mask >> i) & BIT0)
break;
}
return i;
}
void halrf_wreg(struct rf_info *rf, u32 addr, u32 mask, u32 val)
{
u32 ori_val, bit_shift;
// u32 page_temp;
// u32 offset_temp;
// u32 temp = 0;
// page_temp = addr & 0xff00;
// offset_temp = addr & 0xff;
// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
// if (offset_temp <= 0x9c)
// temp = halrf_r32(rf, offset_temp | 0x4c00);
// }
if (mask != MASKDWORD) {
ori_val = halrf_r32(rf, addr);
bit_shift = halrf_cal_bit_shift(mask);
val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask);
}
halrf_w32(rf, addr, val);
// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
// if (offset_temp <= 0x9c)
// halrf_w32(rf, offset_temp | 0x4c00, temp);
// }
}
u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 mask)
{
u32 reg_val = 0, ori_val, bit_shift;
ori_val = halrf_r32(rf, addr);
bit_shift = halrf_cal_bit_shift(mask);
reg_val = (ori_val & mask) >> bit_shift;
return reg_val;
}
void halrf_delay_10us(struct rf_info *rf, u32 count)
{
u32 i;
for (i = 0; i < count; i++)
halrf_delay_us(rf, 10);
}
void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
u8 classid, u32 cmdtype, u32 *pval)
{
u32 rt_val = 0;
struct rtw_g6_h2c_hdr hdr = {0};
struct rtw_hal_com_t *hal_com = NULL;
hdr.h2c_class = classid;
hdr.h2c_func = cmdid;
hdr.type = cmdtype;
hdr.content_len = cmdlen;
hal_com = rf->hal_com;
RF_DBG(rf, DBG_RF_IQK, "[IQK]======>%s H2C: %x %x %x\n",
__func__, classid, cmdid, cmdlen);
rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval);
if (rt_val != 0) {
RF_WARNING("Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
RF_DBG(rf, DBG_RF_IQK, "Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_interface.c
|
C
|
agpl-3.0
| 2,861
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_INTERFACE_H__
#define __HALRF_INTERFACE_H__
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
#define HALRF_CONFIG_FW_IO_OFLD_SUPPORT
#endif
#define CF_PHL_BB_CTRL_RX_CCA
/*@--------------------------[Define] ---------------------------------------*/
/*[IO Reg]*/
#define RF_OFST 0x10000
#define halrf_btc_ntfy(rf, idx, type, process) rtw_hal_btc_wl_rfk_ntfy((rf)->hal_com, idx, type, process)
#define halrf_r32(rf, addr) hal_read32((rf)->hal_com, (addr | RF_OFST))
#define halrf_r16(rf, addr) hal_read16((rf)->hal_com, (addr | RF_OFST))
#define halrf_r8(rf, addr) hal_read8((rf)->hal_com, (addr | RF_OFST))
#define halrf_w32(rf, addr, val) hal_write32((rf)->hal_com, (addr | RF_OFST), val)
#define halrf_w16(rf, addr, val) hal_write16((rf)->hal_com, (addr | RF_OFST), val)
#define halrf_w8(rf, addr, val) hal_write8((rf)->hal_com, (addr | RF_OFST), val)
#define halrf_rrf(rf, path, addr, mask) rtw_hal_read_rf_reg((rf)->hal_com, path, addr, mask)
#define halrf_wrf(rf, path, addr, mask, val) rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val)
#define halrf_wmac32(rf, addr, val) hal_write32((rf)->hal_com, addr, val)
#define halrf_rmac32(rf, addr) hal_read32((rf)->hal_com, addr)
#define halrf_read_mem(rf, addr, cnt, pmem) hal_read_mem((rf)->hal_com, addr, cnt, pmem)
/*[TX]*/
#define halrf_tx_pause(rf, band_idx, tx_pause, rson) rtw_hal_tx_pause((rf)->hal_com, band_idx, tx_pause, rson)
#define halrf_set_pmac_pattern(rf, ppdu_type, case_id, phy_idx) rtw_hal_bb_set_plcp_pattern((rf)->hal_com, ppdu_type, case_id, phy_idx)
#define halrf_set_pmac_plcp_tx(rf, plcp, usr, phy_idx, sts) rtw_hal_bb_set_plcp_tx((rf)->hal_com, plcp, usr, phy_idx, sts)
#define halrf_set_pmac_packet_tx(rf, enable, is_cck, cnt, period, time, phy_idx) rtw_hal_bb_set_pmac_packet_tx((rf)->hal_com, enable, is_cck, cnt, period, time, phy_idx)
#define halrf_set_pmac_power(rf, dbm, phy_idx) rtw_hal_bb_set_power((rf)->hal_com, dbm, phy_idx)
#define halrf_cfg_tx_path(rf, path) rtw_hal_bb_cfg_tx_path((rf)->hal_com, path)
#define halrf_cfg_rx_path(rf, path) rtw_hal_bb_cfg_rx_path((rf)->hal_com, path)
#define halrf_tx_mode_switch(rf, phy_idx, mode) rtw_hal_bb_tx_mode_switch((rf)->hal_com, phy_idx, mode)
#define halrf_query_regulation_info(rf, info) rtw_hal_query_regulation((rf)->phl_com->phl_priv, info)
#define halrf_hal_bb_backup_info(rf, phy_idx) rtw_hal_bb_backup_info((rf)->hal_com, phy_idx)
#define halrf_hal_bb_restore_info(rf, phy_idx) rtw_hal_bb_restore_info((rf)->hal_com, phy_idx)
/*[Delay]*/
#define halrf_delay_ms(rf, ms) _os_delay_ms(rf->hal_com->drv_priv, ms)
#define halrf_delay_us(rf, us) _os_delay_us(rf->hal_com->drv_priv, us)
/*[Memory Access]*/
#define halrf_mem_alloc(rf, buf_sz) _os_mem_alloc(rf->hal_com->drv_priv, buf_sz)
#define halrf_mem_free(rf, buf, buf_sz) _os_mem_free(rf->hal_com->drv_priv, (void *)buf, buf_sz)
#define halrf_mem_set(rf, buf, value, size) _os_mem_set(rf->hal_com->drv_priv, (void *)buf, value, size)
#define halrf_mem_cpy(rf, dest, src, size) _os_mem_cpy(rf->hal_com->drv_priv, (void *)dest, (void *)src, size)
#define halrf_mem_cmp(rf, dest, src, size) _os_mem_cmp(rf->hal_com->drv_priv, (void *)dest, (void *)src, size)
/*[Timer]*/
#define halrf_init_timer(rf, timer, call_back_func, context, sz_id) _os_init_timer(rf->hal_com->drv_priv, timer, call_back_func, context, sz_id)
#define halrf_set_timer(rf, timer, ms_delay) _os_set_timer(rf->hal_com->drv_priv, timer, ms_delay)
#define halrf_cancel_timer(rf, timer) _os_cancel_timer(rf->hal_com->drv_priv, timer)
#define halrf_release_timer(rf, timer) _os_release_timer(rf->hal_com->drv_priv, timer)
/*efuse*/
#ifndef RTW_FLASH_98D
#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_efuse_get_info((rf)->hal_com, info_type, (void *)value, size)
#else
#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_flash_get_info((rf)->hal_com, info_type, (void *)value, size)
#endif /*RTW_FLASH_98D*/
#define halrf_phy_efuse_get_info(rf, addr, size, value) rtw_hal_mac_read_phy_efuse((rf)->hal_com, addr, size, value)
/*GPIO*/
#ifndef RF_8852B_SUPPORT
#define halrf_gpio_setting_all(rf, rfe_idx) rtw_hal_bb_gpio_setting_all((rf)->hal_com, rfe_idx)
#define halrf_gpio_setting(rf, gpio_idx, path, inv, src) rtw_hal_bb_gpio_setting((rf)->hal_com, gpio_idx, path, inv, src)
#define halrf_set_gpio_func(rf, func, gpio_cfg) rtw_hal_mac_set_gpio_func((rf)->hal_com, func, gpio_cfg)
#endif
/*Set power by rate, power limit, power */
#define halrf_mac_write_pwr_limit_rua_reg(rf, band) rtw_hal_mac_write_pwr_limit_rua_reg((rf)->hal_com, band)
#define halrf_mac_write_pwr_limit_reg(rf, band) rtw_hal_mac_write_pwr_limit_reg((rf)->hal_com, band)
#define halrf_mac_write_pwr_by_rate_reg(rf, band) rtw_hal_mac_write_pwr_by_rate_reg((rf)->hal_com, band)
#define halrf_bb_set_tx_pow_ref(rf, phy_idx) rtw_hal_bb_set_tx_pow_ref((rf)->hal_com, phy_idx)
#define halrf_mac_write_pwr_ofst_mode(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_mode((rf)->hal_com, phy_idx)
#define halrf_mac_write_pwr_ofst_bw(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_bw((rf)->hal_com, phy_idx)
#define halrf_mac_write_pwr_limit_en(rf, phy_idx) rtw_hal_mac_write_pwr_limit_en((rf)->hal_com, phy_idx)
#define halrf_bb_set_pow_patten_sharp(rf, channel, is_cck, sharp_id, phy_idx) rtw_hal_bb_set_pow_patten_sharp((rf)->hal_com, channel, is_cck, sharp_id, phy_idx)
#ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT
/*FW offload*/
#define halrf_mac_add_cmd_ofld(rf, cmd) rtw_hal_mac_add_cmd_ofld((rf)->hal_com, cmd)
#endif
/*BB related*/
#define halrf_bb_ctrl_rx_cca(rf, cca_en, phy_idx) rtw_hal_bb_ctrl_rx_cca((rf)->hal_com, cca_en, phy_idx)
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u32 halrf_cal_bit_shift(u32 bit_mask);
u32 halrf_get_sys_time(struct rf_info *rf);
void halrf_wreg(struct rf_info *rf, u32 addr, u32 bit_mask, u32 val);
u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 bit_mask);
void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
u8 classid, u32 cmdtype, u32 *pval);
void halrf_delay_10us(struct rf_info *rf, u32 count);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_interface.h
|
C
|
agpl-3.0
| 7,205
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halrf_precomp.h"
#define OLD_BACKUP_RESTORE_ENABLE (0)
//#ifdef RF_8852A_SUPPORT
u8 iqk_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx)
{
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
return iqk_ops->iqk_kpath(rf, phy_idx);
}
void iqk_restore(struct rf_info *rf, u8 path)
{
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
iqk_ops->iqk_restore(rf, path);
return;
}
void iqk_backup_mac_reg(struct rf_info *rf, u32 *backup_mac_reg_val)
{
struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info;
u32 i;
for (i = 0; i < iqk_info->backup_mac_reg_num; i++) {
if (i >= RF_BACKUP_MAC_REG_MAX_NUM) {
RF_DBG(rf, DBG_RF_IQK,
"[IQK] %s backup size not enough\n", __func__);
break;
}
*(backup_mac_reg_val + i) =
halrf_rreg(rf, iqk_info->backup_mac_reg[i], MASKDWORD);
/*
RF_DBG(rf, DBG_RF_IQK, "[IQK]backup mac reg : %x, value =%x\n",
iqk_info->backup_mac_reg[i], *(backup_mac_reg_val + i));
*/
}
}
void iqk_backup_bb_reg(struct rf_info *rf, u32 *backup_bb_reg_val)
{
struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info;
u32 i;
for (i = 0; i < iqk_info->backup_bb_reg_num; i++) {
if (i >= RF_BACKUP_BB_REG_MAX_NUM) {
RF_DBG(rf, DBG_RF_IQK,
"[IQK] %s backup size not enough\n", __func__);
break;
}
*(backup_bb_reg_val + i) =
halrf_rreg(rf, iqk_info->backup_bb_reg[i], MASKDWORD);
/*
RF_DBG(rf, DBG_RF_IQK, "[IQK]backup bb reg : %x, value =%x\n",
iqk_info->backup_bb_reg[i], *(backup_bb_reg_val + i));
*/
}
}
void iqk_backup_rf_reg(struct rf_info *rf, u32 *backup_rf_reg_val, u8 rf_path)
{
struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info;
u32 i;
for (i = 0; i < iqk_info->backup_rf_reg_num; i++) {
if (i >= RF_BACKUP_RF_REG_MAX_NUM) {
RF_DBG(rf, DBG_RF_IQK,
"[IQK] %s backup size not enough\n", __func__);
break;
}
*(backup_rf_reg_val + i) = halrf_rrf(
rf, rf_path, iqk_info->backup_rf_reg[i], MASKRF);
/*
RF_DBG(rf, DBG_RF_IQK,
"[IQK]backup rf S%d reg : %x, value =%x\n", rf_path,
iqk_info->backup_rf_reg[i], *(backup_rf_reg_val + i));
*/
}
}
void iqk_restore_mac_reg(struct rf_info *rf, u32 *backup_mac_reg_val)
{
struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info;
u32 i;
for (i = 0; i < iqk_info->backup_mac_reg_num; i++) {
if (i >= RF_BACKUP_MAC_REG_MAX_NUM) {
RF_DBG(rf, DBG_RF_IQK,
"[IQK] %s restore size not enough\n", __func__);
break;
}
halrf_wreg(rf, iqk_info->backup_mac_reg[i], MASKDWORD,
*(backup_mac_reg_val + i));
/*
RF_DBG(rf, DBG_RF_IQK,
"[IQK]restore mac reg : %x, value =%x\n",
iqk_info->backup_mac_reg[i], *(backup_mac_reg_val + i));
*/
}
}
void iqk_restore_bb_reg(struct rf_info *rf, u32 *backup_bb_reg_val)
{
struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info;
u32 i;
for (i = 0; i < iqk_info->backup_bb_reg_num; i++) {
if (i >= RF_BACKUP_BB_REG_MAX_NUM) {
RF_DBG(rf, DBG_RF_IQK,
"[IQK] %s restore size not enough\n", __func__);
break;
}
halrf_wreg(rf, iqk_info->backup_bb_reg[i], MASKDWORD,
*(backup_bb_reg_val + i));
/*
RF_DBG(rf, DBG_RF_IQK, "[IQK]restore bb reg : %x, value =%x\n",
iqk_info->backup_bb_reg[i], *(backup_bb_reg_val + i));
*/
}
}
void iqk_restore_rf_reg(struct rf_info *rf, u32 *backup_rf_reg_val, u8 rf_path)
{
struct rfk_iqk_info *iqk_info = rf->rfk_iqk_info;
u32 i;
for (i = 0; i < iqk_info->backup_rf_reg_num; i++) {
if (i >= RF_BACKUP_RF_REG_MAX_NUM) {
RF_DBG(rf, DBG_RF_IQK,
"[IQK] %s restore size not enough\n", __func__);
break;
}
halrf_wrf(rf, rf_path, iqk_info->backup_rf_reg[i], MASKRF,
*(backup_rf_reg_val + i));
/*
RF_DBG(rf, DBG_RF_IQK,
"[IQK]restore rf S%d reg: %x, value =%x\n", rf_path,
iqk_info->backup_rf_reg[i], *(backup_rf_reg_val + i));
*/
}
}
void iqk_macbb_setting(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
#if 1
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===> %s\n", __func__);
iqk_ops->iqk_macbb_setting(rf, phy_idx, path);
#else
iqk_macbb_setting_8852a(rf, path, dbcc_en);
#endif
return;
}
void iqk_preset(struct rf_info *rf, u8 path)
{
#if 1
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
iqk_ops->iqk_preset(rf, path);
#endif
return;
}
void iqk_afebb_restore(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
#if 1
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
//RF_DBG(rf, DBG_RF_IQK, "[IQK]===> %s\n", __func__);
iqk_ops->iqk_afebb_restore(rf, phy_idx, path);
#else
iqk_afebb_restore_8852a(rf, path);
#endif
return;
}
void iqk_get_ch_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
#if 1
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
iqk_ops->iqk_get_ch_info(rf, phy_idx, path);
#else
iqk_get_ch_info_8852a(rf, phy_idx, path);
#endif
return;
}
bool iqk_mcc_page_sel(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
return iqk_ops->iqk_mcc_page_sel(rf, phy_idx, path);;
}
void iqk_start_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
#if 1
struct halrf_iqk_ops *iqk_ops = rf->rfk_iqk_info->rf_iqk_ops;
iqk_ops->iqk_start_iqk(rf, phy_idx, path);
#else
iqk_start_iqk_8852a(rf, phy_idx, path);
#endif
return;
}
void halrf_iqk_init(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
iqk_init_8852ab(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
iqk_init_8852b(rf);
break;
#endif
default:
break;
}
return;
}
void halrf_doiqk(struct rf_info *rf, bool force, enum phl_phy_idx phy_idx,
u8 path)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 backup_mac_val[RF_BACKUP_MAC_REG_MAX_NUM] = {0x0};
u32 backup_bb_val[RF_BACKUP_BB_REG_MAX_NUM] = {0x0};
u32 backup_rf_val[RF_PATH_MAX_NUM][RF_BACKUP_RF_REG_MAX_NUM] = {{0x0}};
u8 rf_path = 0x0;
#if 0
if(!force) {
if (!phl_is_mp_mode(rf->phl_com)) {
if(iqk_mcc_page_sel(rf, phy_idx, path)) {
RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK reload!!!!==========\n");
return;
}
}
}
#endif
//halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_START);
//iqk_info->version = iqk_version;
RF_DBG(rf, DBG_RF_IQK, "[IQK]==========IQK strat!!!!!==========\n");
//RF_DBG(rf, DBG_RF_IQK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
iqk_get_ch_info(rf, phy_idx, path);
iqk_backup_mac_reg(rf, &backup_mac_val[0]);
iqk_backup_bb_reg(rf, &backup_bb_val[0]);
iqk_backup_rf_reg(rf, &backup_rf_val[path][0], path);
iqk_macbb_setting(rf, phy_idx, path);
iqk_preset(rf, path);
iqk_start_iqk(rf, phy_idx, path);
iqk_restore(rf, path);
iqk_afebb_restore(rf, phy_idx, path);
iqk_restore_mac_reg(rf, &backup_mac_val[0]);
iqk_restore_bb_reg(rf, &backup_bb_val[0]);
iqk_restore_rf_reg(rf, &backup_rf_val[path][0], path);
iqk_info->iqk_times++;
//halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_STOP);
return;
}
void halrf_drv_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force) {
/*drv_iqk*/
RF_DBG(rf, DBG_RF_IQK, "[IQK]==== DRV IQK ==== \n");
switch (iqk_kpath(rf, phy_idx)) {
case RF_A:
halrf_doiqk(rf, force, phy_idx, RF_PATH_A);
break;
case RF_B:
halrf_doiqk(rf, force, phy_idx, RF_PATH_B);
break;
case RF_AB:
halrf_doiqk(rf, force, phy_idx, RF_PATH_A);
halrf_doiqk(rf, force, phy_idx, RF_PATH_B);
break;
default:
break;
}
}
bool halrf_check_fwiqk_done(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
bool isfail = false;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
isfail = halrf_check_fwiqk_done_8852ab(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
isfail = halrf_check_fwiqk_done_8852b(rf);
break;
#endif
default:
break;
}
return isfail;
}
void halrf_iqk_get_ch_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
iqk_get_ch_info_8852ab(rf, phy_idx, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
iqk_get_ch_info_8852b(rf, phy_idx, path);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_set_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
iqk_set_info_8852ab(rf, phy_idx, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
iqk_set_info_8852b(rf, phy_idx, path);
break;
#endif
default:
break;
}
return;
}
u8 halrf_get_iqk_times(struct rf_info *rf)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 times =0x0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
times = halrf_get_iqk_times_8852ab(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
times = halrf_get_iqk_times_8852b(rf);
break;
#endif
default:
break;
}
return times ;
}
bool halrf_fw_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force) {
struct halrf_iqk_info *iqk_info = &rf->iqk;
u32 data_to_fw[2] = {0};
u16 len = (u16) (sizeof(data_to_fw) / sizeof(u32))*4;
bool isfail = true;
RF_DBG(rf, DBG_RF_IQK, "[IQK]==== FW IQK START v3 ==== \n");
data_to_fw[0] = (u32) phy_idx;
data_to_fw[1] = (u32) rf->hal_com->dbcc_en;
halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_START);
RF_DBG(rf, DBG_RF_IQK, "[IQK] phy_idx = 0x%x\n", data_to_fw[0]);
RF_DBG(rf, DBG_RF_IQK, "[IQK] dbcc_en = 0x%x\n", data_to_fw[1]);
halrf_iqk_get_ch_info(rf, phy_idx, RF_PATH_A);
halrf_iqk_get_ch_info(rf, phy_idx, RF_PATH_B);
halrf_fill_h2c_cmd(rf, len, FWCMD_H2C_IQK_OFFLOAD, 0xa, H2CB_TYPE_DATA, (u32 *) data_to_fw);
halrf_check_fwiqk_done(rf);
iqk_info->iqk_times = halrf_get_iqk_times(rf);
halrf_iqk_set_info(rf, phy_idx, RF_PATH_A);
halrf_iqk_set_info(rf, phy_idx, RF_PATH_B);
halrf_btc_rfk_ntfy(rf, ((BIT(phy_idx) << 4) | RF_AB), RF_BTC_IQK, RFK_ONESHOT_STOP);
RF_DBG(rf, DBG_RF_IQK, "[IQK]==== FW IQK FINISH ==== \n");
return isfail;
}
void halrf_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force)
{
struct halrf_iqk_info *iqk_info = &rf->iqk;
bool isfail = true;
#if 0
if ((rf->phl_com->id.id & 0x7)== 0x2) //USB
iqk_info->is_fw_iqk = true;
else
iqk_info->is_fw_iqk = false;
#endif
if (iqk_info->is_fw_iqk) {
isfail = halrf_fw_iqk(rf, phy_idx, force);
if (isfail) {
iqk_info->is_iqk_init = false;
halrf_iqk_init(rf);
isfail = halrf_fw_iqk(rf, phy_idx, force);
}
} else {
halrf_drv_iqk(rf, phy_idx, force);
}
return;
}
////////////// debg command //////////////////////////
u32 halrf_get_iqk_ver(struct rf_info *rf)
{
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 tmp = 0x0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
tmp = halrf_get_iqk_ver_8852a();
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
tmp =halrf_get_iqk_ver_8852b();
break;
#endif
default:
break;
}
return tmp;
}
void halrf_iqk_toneleakage(void *rf_void, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_toneleakage_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_toneleakage_8852b(rf, path);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_tx_bypass(void *rf_void, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_tx_bypass_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_tx_bypass_8852b(rf, path);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_rx_bypass(void *rf_void, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_rx_bypass_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_rx_bypass_8852b(rf, path);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_lok_bypass(void *rf_void, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_lok_bypass_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_lok_bypass_8852b(rf, path);
break;
#endif
default:
break;
}
return;
}
void halrf_nbiqk_enable(void *rf_void, bool iqk_nbiqk_en)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_nbiqk_enable_8852ab(rf, iqk_nbiqk_en);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_nbiqk_enable_8852b(rf, iqk_nbiqk_en);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_xym_enable(void *rf_void, bool iqk_xym_en)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_xym_enable_8852ab(rf, iqk_xym_en);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_xym_enable_8852b(rf, iqk_xym_en);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_fft_enable(void *rf_void, bool iqk_fft_en)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_fft_enable_8852ab(rf, iqk_fft_en);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_fft_enable_8852b(rf, iqk_fft_en);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_cfir_enable(void *rf_void, bool iqk_cfir_en)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_cfir_enable_8852ab(rf, iqk_cfir_en);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_cfir_enable_8852b(rf, iqk_cfir_en);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_sram_enable(void *rf_void, bool iqk_sram_en)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_sram_enable_8852ab(rf, iqk_sram_en);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_sram_enable_8852b(rf, iqk_sram_en);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_reload(void *rf_void, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_reload_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_reload_8852b(rf, path);
break;
#endif
default:
break;
}
return;
}
void halrf_iqk_dbcc(void *rf_void, u8 path)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_iqk_dbcc_8852ab(rf, path);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_iqk_dbcc_8852b(rf, path);
break;
#endif
default:
break;
}
return;
}
u8 halrf_iqk_get_mcc_ch0(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 tmp = 0x0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
tmp = halrf_iqk_get_mcc_ch0_8852ab(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
tmp = halrf_iqk_get_mcc_ch0_8852b(rf);
break;
#endif
default:
break;
}
return tmp;
}
u8 halrf_iqk_get_mcc_ch1(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 tmp = 0x0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
tmp= halrf_iqk_get_mcc_ch0_8852ab(rf);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
tmp = halrf_iqk_get_mcc_ch0_8852b(rf);
break;
#endif
default:
break;
}
return tmp;
}
void halrf_enable_fw_iqk(void *rf_void, bool is_fw_iqk)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
halrf_enable_fw_iqk_8852ab(rf, is_fw_iqk);
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
halrf_enable_fw_iqk_8852b(rf, is_fw_iqk);
break;
#endif
default:
break;
}
return;
}
u8 halrf_iqk_get_rxevm(void *rf_void)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u8 rxevm =0x0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
rxevm = halrf_iqk_get_rxevm_8852b(rf);
break;
#endif
default:
break;
}
return rxevm;
}
u32 halrf_iqk_get_rximr(void *rf_void, u8 path, u32 idx)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct rtw_hal_com_t *hal_i = rf->hal_com;
u32 rximr =0x0;
switch (hal_i->chip_id) {
#ifdef RF_8852A_SUPPORT
case CHIP_WIFI6_8852A:
break;
#endif
#ifdef RF_8852B_SUPPORT
case CHIP_WIFI6_8852B:
rximr = halrf_iqk_get_rximr_8852b(rf, path, idx);
break;
#endif
default:
break;
}
return rximr;
}
//#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_iqk.c
|
C
|
agpl-3.0
| 18,866
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_IQK_H_
#define _HALRF_IQK_H_
/*@--------------------------Define Parameters-------------------------------*/
#define TXIQK 0
#define RXIQK 1
#define RXIQK1 2
#define RXIQK2 3
#define NBTXK 4
#define NBRXK 5
//#define NUM 2
#define ID_TXAGC 0x0
#define ID_FLoK_coarse 0x1
#define ID_FLoK_fine 0x2
#define ID_TXK 0x3
#define ID_RXAGC 0x4
#define ID_RXK 0x5
#define ID_NBTXK 0x6
#define ID_NBRXK 0x7
#define ID_FLOK_vbuffer 0x8
#define ID_TX_PAD_GainGapK 0xe
#define ID_TX_PA_GainGapK 0xf
/*@-----------------------End Define Parameters-----------------------*/
struct halrf_iqk_info {
bool lok_cor_fail[2][NUM]; /*channel/path */
bool lok_fin_fail[2][NUM]; /*channel/path */
bool iqk_tx_fail[2][NUM]; /*channel/path */
bool iqk_rx_fail[2][NUM]; /*channel/path */
u32 iqk_cnt;
u32 iqk_fail_cnt;
bool segment_iqk;
bool is_iqk_enable;
bool is_iqk_init;
bool is_reload;
u32 iqk_channel[2];
u8 iqk_band[NUM];
u8 iqk_ch[NUM];
u8 iqk_bw[NUM];
u8 kcount;
u8 iqk_times;
u8 rxiqk_step;
u8 iqk_step;
u8 version;
u32 lok_idac[2][NUM];
u32 lok_vbuf[2][NUM];
u32 iqc_gain;
u32 rftxgain[NUM];
u32 rfrxgain[NUM];
u32 nb_txcfir[NUM];
u32 nb_rxcfir[NUM];
u32 rximr[NUM];
u32 syn1to2;
u32 bp_txkresult[2];
u32 bp_rxkresult[2];
u32 bp_lokresult[2];
u32 bp_iqkenable[2];
u32 reload_cnt;
bool is_wb_txiqk[2];
bool is_wb_rxiqk[2];
bool is_nbiqk;
bool iqk_fft_en;
bool iqk_xym_en;
bool iqk_sram_en;
bool iqk_cfir_en;
u8 ther_avg[2][8]; /*path*/
u8 ther_avg_idx;
u8 thermal[2];
bool thermal_rek_en;
u8 iqk_mcc_ch[2][NUM];
u8 iqk_table_idx[NUM];
bool is_fw_iqk;
};
void halrf_iqk_init(struct rf_info *rf);
void halrf_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
u32 halrf_get_iqk_ver(struct rf_info *rf);
void halrf_iqk_toneleakage(void *rf_void, u8 path);
void halrf_nbiqk_enable(void *rf_void, bool iqk_nbiqk_en);
void halrf_iqk_tx_bypass(void *rf_void, u8 path);
void halrf_iqk_rx_bypass(void *rf_void, u8 path);
void halrf_iqk_lok_bypass(void *rf_void, u8 path);
void halrf_iqk_xym_enable(void *rf_void, bool iqk_xym_en);
void halrf_iqk_fft_enable(void *rf_void, bool iqk_fft_en);
void halrf_iqk_cfir_enable(void *rf_void, bool iqk_cfir_en);
void halrf_iqk_sram_enable(void *rf_void, bool iqk_sram_en);
void halrf_iqk_reload(void *rf_void, u8 path);
void halrf_iqk_dbcc(void *rf_void, u8 path);
u8 halrf_iqk_get_mcc_ch0(void *rf_void);
u8 halrf_iqk_get_mcc_ch1(void *rf_void);
void halrf_enable_fw_iqk(void *rf_void, bool is_fw_iqk);
u8 halrf_iqk_get_rxevm(void *rf_void);
u32 halrf_iqk_get_rximr(void *rf_void, u8 path, u32 idx);
bool halrf_check_fwiqk_done(struct rf_info *rf);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_iqk.h
|
C
|
agpl-3.0
| 3,302
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_KFREE_H_
#define _HALRF_KFREE_H_
#define RX_GAIN_K_PATH_MAX 2
#define RX_GAIN_K_OFFSET_MAX 5
#define RX_GAIN_K_HIDE_OFFSET_MAX 4
enum BITMASK {
LOW_MASK = 0,
HIGH_MASK = 1
};
struct halrf_rx_gain_k_info{
bool efuse_chenk;
bool hide_efuse_chenk;
s8 rx_gain_offset[RX_GAIN_K_PATH_MAX][RX_GAIN_K_OFFSET_MAX];
s8 rx_gain_cs[RX_GAIN_K_PATH_MAX][RX_GAIN_K_HIDE_OFFSET_MAX];
s8 rx_gain_cg[RX_GAIN_K_PATH_MAX][RX_GAIN_K_HIDE_OFFSET_MAX];
s8 rx_lna_err_2g[RX_GAIN_K_PATH_MAX][7];
s8 rx_lna_err_5g[RX_GAIN_K_PATH_MAX][7];
s8 rx_frontend_loss[RX_GAIN_K_PATH_MAX];
s8 rx_rpl_bias_comp[RX_GAIN_K_PATH_MAX];
s8 rx_rssi_bias_comp[RX_GAIN_K_PATH_MAX];
};
#endif /*_HALRF_SET_PWR_TABLE_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_kfree.h
|
C
|
agpl-3.0
| 1,356
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halrf_precomp.h"
void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path,
u16 txagc_cw, bool en)
{
u32 cw_addr[2] = {0x7c10, 0x7d10};
halrf_wreg(rf, cw_addr[path], 0x000001FF, txagc_cw & 0x1ff);
halrf_wreg(rf, cw_addr[path], BIT(9), en);
if (en)
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set S%d Pseudo_CW RF:0x%x, BB:%d(x0.125)\n",
path, (txagc_cw & 0x1f8) >> 3, txagc_cw & 0x7);
else
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set S%d Pseudo_CW off!!\n", path);
}
void halrf_set_plcp_usr_info(struct rf_info *rf, struct rf_plcp_param_t *plcp,
struct rf_pmac_tx_info *tx_info)
{
plcp->usr[0].mcs = tx_info->mcs;
plcp->usr[0].mpdu_len = 0; /*def*/
plcp->usr[0].n_mpdu = 0; /*def*/
plcp->usr[0].fec = 0;
plcp->usr[0].dcm = 0;
plcp->usr[0].aid = 0;
plcp->usr[0].scrambler_seed = 100; /*rand(1~255)*/
plcp->usr[0].random_init_seed = 100; /*rand(1~255)*/
plcp->usr[0].apep = tx_info->length;
plcp->usr[0].ru_alloc = 0;
plcp->usr[0].nss = tx_info->nss;
plcp->usr[0].txbf = 0; /*def*/
plcp->usr[0].pwr_boost_db = 0;
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set PLCP usr (mcs:%d, length:%d, nss:%d)\n",
tx_info->mcs, tx_info->length, tx_info->nss);
}
void halrf_set_plcp_para_info(struct rf_info *rf, struct rf_plcp_param_t *plcp,
struct rf_pmac_tx_info *tx_info)
{
plcp->dbw = tx_info->bw; /*0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80*/
plcp->source_gen_mode = 3; /*def*/
plcp->locked_clk = 1; /*def*/
plcp->dyn_bw = 0; /*def*/
plcp->ndp_en = 0; /*def*/
plcp->long_preamble_en = tx_info->long_preamble_en;
plcp->stbc = 0;
plcp->gi = tx_info->gi;
plcp->tb_l_len = 0;
plcp->tb_ru_tot_sts_max = 0;
plcp->vht_txop_not_allowed = 0;
plcp->tb_disam = 0;
plcp->doppler = 0; /*def*/
plcp->he_ltf_type = 0;
plcp->ht_l_len = 0; /*def*/
plcp->preamble_puncture = 0; /*def*/
plcp->he_mcs_sigb = 0;
plcp->he_dcm_sigb = 0;
plcp->he_sigb_compress_en = 1; /*def*/
plcp->max_tx_time_0p4us = 0;
plcp->ul_flag = 0; /*def*/
plcp->tb_ldpc_extra = 0;
plcp->bss_color = 0;
plcp->sr = 0; /*def*/
plcp->beamchange_en = 1; /*def*/
plcp->he_er_u106ru_en = 0;
plcp->ul_srp1 = 0; /*def*/
plcp->ul_srp2 = 0; /*def*/
plcp->ul_srp3 = 0; /*def*/
plcp->ul_srp4 = 0; /*def*/
plcp->mode = 0;
plcp->group_id = 0;
plcp->ppdu_type = tx_info->ppdu;
plcp->txop = 127; /*def*/
plcp->tb_strt_sts = 0;
plcp->tb_pre_fec_padding_factor = 0;
plcp->cbw = 0;
plcp->txsc = 0;
plcp->tb_mumimo_mode_en = 0;
plcp->nominal_t_pe = 2; /*def*/
plcp->ness = 0; /*def*/
plcp->n_user = 1;
plcp->tb_rsvd = 0; /*def*/
/*halrf_mem_cpy(rf, plcp->usr, rf->usr, 4*sizeof(struct rf_usr_plcp_gen_in));*/
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set PLCP para (BW:%d, long_preamble:%d, GI:%d, PPDU:%d)\n",
tx_info->bw, tx_info->long_preamble_en, tx_info->gi ,tx_info->ppdu);
}
void halrf_set_pmac_plcp_gen(struct rf_info *rf, enum phl_phy_idx phy_idx,
struct rf_pmac_tx_info *tx_info)
{
struct rf_plcp_param_t plcp = {0};
u8 sts = 0;
halrf_set_plcp_usr_info(rf, &plcp, tx_info);
halrf_set_plcp_para_info(rf, &plcp, tx_info);
halrf_set_pmac_plcp_tx(rf, (void*)&plcp, (void*)&plcp.usr, phy_idx, &sts);
}
void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
enum rf_path path, struct rf_pmac_tx_info *tx,
u8 enable, bool by_cw)
{
if (enable) {
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set S%d PMAC Tx (PHY%d)\n", path, phy_idx);
halrf_set_pmac_plcp_gen(rf, phy_idx, tx);
halrf_cfg_tx_path(rf, path);
halrf_cfg_rx_path(rf, path);
if (by_cw)
halrf_set_pseudo_cw(rf, path, tx->txagc_cw, true);
else
halrf_set_pmac_power(rf, tx->dbm, phy_idx);
} else
RF_DBG(rf, DBG_RF_RFK, "[RFK] Disable PMAC Tx!!\n");
halrf_set_pmac_packet_tx(rf, enable, tx->is_cck, tx->cnt,
tx->period, tx->time, phy_idx);
}
#if 0
void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
enum rf_path path, enum rf_ppdu_type ppdu_type, u8 case_id,
s16 dbm, u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period)
{
#if 1
if (enable) {
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set PMAC Tx (PHY%d, S%d, PPDU:%d, case:%d)\n",
phy_idx, path, ppdu_type, case_id);
RF_DBG(rf, DBG_RF_RFK,
"[RFK] Set PMAC Tx (%ddBm, Cnt:%d, time:%d, period:%d)\n",
dbm, cnt, time, period);
//halrf_set_pmac_pattern(rf, ppdu_type, case_id, phy_idx);
halrf_set_pmac_plcp_gen(rf, 7, 0, 1, 0, 0, 1, ppdu_type, phy_idx);
halrf_cfg_tx_path(rf, path);
//halrf_set_pmac_power(rf, dbm, phy_idx);
halrf_set_pseudo_cw(rf, path, 0x1d0, true);
} else
RF_DBG(rf, DBG_RF_RFK, "[RFK] Disable PMAC Tx!!\n");
halrf_set_pmac_packet_tx(rf, enable, is_cck, cnt, period, time, phy_idx);
#endif
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_pmac.c
|
C
|
agpl-3.0
| 5,341
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_PMAC_H_
#define _HALRF_PMAC_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum rf_ppdu_type {
T_CCK = 0,
T_LEGACY = 1,
T_HT_MF = 2,
T_VHT = 3,
T_HE_SU = 4,
T_HE_ER_SU = 5,
T_HE_MU_OFDMA = 6,
T_HE_TB = 7,
};
/*@--------------------------[Structure]-------------------------------------*/
struct rf_pmac_tx_info {
enum rf_ppdu_type ppdu;
u8 mcs;
u8 bw;
u8 nss;
u8 long_preamble_en;
u8 gi;
u16 case_id;
s16 dbm;
u16 txagc_cw;
u8 is_cck;
u16 cnt;
u16 time;
u16 period;
u16 length;
};
struct rf_usr_plcp_gen_in {
u32 mcs : 6;
u32 mpdu_len : 14;
u32 n_mpdu : 9;
u32 fec : 1;
u32 dcm : 1;
u32 rsvd0 : 1;
u32 aid : 12;
u32 scrambler_seed : 8; // rand (1~255)
u32 random_init_seed : 8; // rand (1~255)
u32 rsvd1 : 4;
u32 apep : 22;
u32 ru_alloc : 8;
u32 rsvd2 : 2;
u32 nss : 4;
u32 txbf : 1;
u32 pwr_boost_db : 5;
u32 rsvd3 : 22;
};
struct rf_plcp_param_t {
u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80
u32 source_gen_mode : 2;
u32 locked_clk : 1;
u32 dyn_bw : 1;
u32 ndp_en : 1;
u32 long_preamble_en : 1; //bmode
u32 stbc : 1;
u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2
u32 tb_l_len : 12;
u32 tb_ru_tot_sts_max : 3;
u32 vht_txop_not_allowed : 1;
u32 tb_disam : 1;
u32 doppler : 2;
u32 he_ltf_type : 2;//0:1x,1:2x,2:4x
u32 ht_l_len : 12;
u32 preamble_puncture : 1;
u32 he_mcs_sigb : 3;//0~5
u32 he_dcm_sigb : 1;
u32 he_sigb_compress_en : 1;
u32 max_tx_time_0p4us : 14;
u32 ul_flag : 1;
u32 tb_ldpc_extra : 1;
u32 bss_color : 6;
u32 sr : 4;
u32 beamchange_en : 1;
u32 he_er_u106ru_en : 1;
u32 ul_srp1 : 4;
u32 ul_srp2 : 4;
u32 ul_srp3 : 4;
u32 ul_srp4 : 4;
u32 mode : 2;
u32 group_id : 6;
u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB
u32 txop : 7;
u32 tb_strt_sts : 3;
u32 tb_pre_fec_padding_factor : 2;
u32 cbw : 2;
u32 txsc : 4;
u32 tb_mumimo_mode_en : 1;
u32 rsvd1 : 3;
u8 nominal_t_pe : 2; // def = 2
u8 ness : 2; // def = 0
u8 rsvd2 : 4;
u8 n_user;
u16 tb_rsvd : 9;//def = 0
u16 rsvd3 : 7;
struct rf_usr_plcp_gen_in usr[4];
};
/*@--------------------------[Prptotype]-------------------------------------*/
void halrf_set_pmac_cw(struct rf_info *rf, enum rf_path path, u16 txagc_cw, bool en);
void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
enum rf_path path, struct rf_pmac_tx_info *tx,
u8 enable, bool by_cw);
void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path,
u16 txagc_cw, bool en);
#if 0
void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
enum rf_path path, u8 ppdu_type, u8 case_id, s16 dbm,
u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period);
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_pmac.h
|
C
|
agpl-3.0
| 3,478
|
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_PRECOMP_H__
#define __HALRF_PRECOMP_H__
/*@--------------------------[Define] ---------------------------------------*/
#ifdef CONFIG_RTL8852A
#define RF_8852A_SUPPORT
#endif
#ifdef CONFIG_RTL8852B
#define RF_8852B_SUPPORT
#endif
#ifdef CONFIG_RTL8852C
#define RF_8852C_SUPPORT
#endif
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASKRF 0xfffff
#define MASKRFMODE 0xf0000
#define MASKRFRXBB 0x003e0
#define MASKTXPWR 0x0003f
#define INVALID_RF_DATA 0xffffffff
/*---[Define Only] ----------------------------------------------------------*/
#include "../../hal_headers_le.h"
#include "halrf_ic_hw_info.h"
#include "halrf_ic_sw_info.h"
/*---[Include structure & prototype] ----------------------------------------*/
#include "halrf_hw_cfg.h"
#include "halrf_hw_cfg_ex.h"
#include "halrf_interface.h"
#include "halrf_dbg_cmd.h"
#include "halrf_dbg.h"
#include "halrf_txgapk.h"
#include "halrf_pwr_track.h"
#include "halrf_iqk.h"
#include "halrf_dpk.h"
#include "halrf_dack.h"
#include "halrf_pmac.h"
//#include "halrf_dbg_cmd.h"
#include "halrf_dbg_cmd_ex.h"
#include "halrf_init.h"
#include "halrf_init_ex.h"
#include "halrf_pwr_table.h"
#include "halrf_api.h"
#include "halrf_psd.h"
#include "halrf_kfree.h"
#include "halrf_hwimg.h"
#ifdef RF_8852A_SUPPORT
#include "halrf_8852a/halrf_dack_8852a.h"
#include "halrf_8852a/halrf_hwimg_8852a.h"
#include "halrf_8852a/halrf_kfree_8852a.h"
#endif
#ifdef RF_8852B_SUPPORT
#include "halrf_8852b/halrf_dack_8852b.h"
#include "halrf_8852b/halrf_hwimg_8852b.h"
#include "halrf_8852b/halrf_kfree_8852b.h"
#endif
#ifdef RF_8852C_SUPPORT
//#include "halrf_8852c/halrf_dack_8852c.h"
//#include "halrf_8852c/halrf_hwimg_8852c.h"
//#include "halrf_8852c/halrf_kfree_8852c.h"
#endif
#include "halrf.h"
#include "halrf_ex.h"
#ifdef RF_8852A_SUPPORT
#include "halrf_8852a/halrf_efuse_8852a.h"
#include "halrf_8852a/halrf_reg_cfg_8852a.h"
#include "halrf_8852a/halrf_8852a.h"
#include "halrf_8852a/halrf_8852a_api.h"
#include "halrf_8852a/halrf_8852a_api_ex.h"
#include "halrf_8852a/halrf_iqk_8852a.h"
#include "halrf_8852a/halrf_dpk_8852a.h"
#include "halrf_8852a/halrf_txgapk_8852a.h"
#include "halrf_8852a/halrf_version_rtl8852a.h"
#include "halrf_8852a/halrf_set_pwr_table_8852a.h"
#include "halrf_8852a/halrf_tssi_8852a.h"
#include "halrf_8852a/halrf_psd_8852a.h"
#endif
#ifdef RF_8852B_SUPPORT
#include "halrf_8852b/halrf_efuse_8852b.h"
#include "halrf_8852b/halrf_reg_cfg_8852b.h"
#include "halrf_8852b/halrf_8852b.h"
#include "halrf_8852b/halrf_8852b_api.h"
#include "halrf_8852b/halrf_8852b_api_ex.h"
#include "halrf_8852b/halrf_iqk_8852b.h"
#include "halrf_8852b/halrf_dpk_8852b.h"
#include "halrf_8852b/halrf_txgapk_8852b.h"
#include "halrf_8852b/halrf_version_rtl8852b.h"
#include "halrf_8852b/halrf_set_pwr_table_8852b.h"
#include "halrf_8852b/halrf_tssi_8852b.h"
#include "halrf_8852b/halrf_psd_8852b.h"
#endif
#ifdef RF_8852C_SUPPORT
// #include "halrf_8852c/halrf_efuse_8852c.h"
// #include "halrf_8852c/halrf_reg_cfg_8852c.h"
#include "halrf_8852c/halrf_8852c.h"
// #include "halrf_8852c/halrf_8852c_api.h"
// #include "halrf_8852c/halrf_8852c_api_ex.h"
// #include "halrf_8852c/halrf_iqk_8852c.h"
// #include "halrf_8852c/halrf_dpk_8852c.h"
// #include "halrf_8852c/halrf_txgapk_8852c.h"
// #include "halrf_8852c/halrf_version_rtl8852c.h"
// #include "halrf_8852c/halrf_set_pwr_table_8852c.h"
// #include "halrf_8852c/halrf_tssi_8852c.h"
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_precomp.h
|
C
|
agpl-3.0
| 4,603
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_PSD_H_
#define _HALRF_PSD_H_
/*@--------------------------Define Parameters-------------------------------*/
/*@-----------------------End Define Parameters-----------------------*/
struct halrf_psd_data {
u8 path;
u8 iq_path;
u32 avg;
u32 fft;
u32 point;
u32 start_point;
u32 stop_point;
u32 average;
u32 buf_size;
u32 psd_data[450];
u32 psd_progress;
bool psd_result_running;
u32 psd_reg_backup[256];
};
#endif /*_HALRF_PSD_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_psd.h
|
C
|
agpl-3.0
| 1,113
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "halrf_precomp.h"
const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM] = {
/* elements not listed here will get NULL */
[PW_LMT_REGU_WW13] = "WW",
[PW_LMT_REGU_ETSI] = "ETSI",
[PW_LMT_REGU_FCC] = "FCC",
[PW_LMT_REGU_MKK] = "MKK",
[PW_LMT_REGU_NA] = "NONE",
[PW_LMT_REGU_IC] = "IC",
[PW_LMT_REGU_KCC] = "KCC",
[PW_LMT_REGU_ACMA] = "ACMA",
[PW_LMT_REGU_NCC] = "NCC",
[PW_LMT_REGU_MEXICO] = "MEXICO",
[PW_LMT_REGU_CHILE] = "CHILE",
[PW_LMT_REGU_UKRAINE] = "UKRAINE",
[PW_LMT_REGU_CN] = "CN",
[PW_LMT_REGU_QATAR] = "QATAR",
[PW_LMT_REGU_EXT_PWR] = "EXT",
[PW_LMT_REGU_NULL] = NULL,
};
int halrf_get_predefined_pw_lmt_regu_type_from_str(const char *str)
{
int i;
for (i = 0; i < PW_LMT_MAX_REGULATION_NUM; i++)
if (_pw_lmt_regu_type_str[i] && _os_strcmp(_pw_lmt_regu_type_str[i], str) == 0)
return i;
return -1;
}
const char * const *halrf_get_predefined_pw_lmt_regu_type_str_array(u8 *num)
{
if (num)
*num = PW_LMT_REGU_PREDEF_NUM;
return _pw_lmt_regu_type_str;
}
const enum halrf_pw_lmt_regulation_type _regulation_to_pw_lmt_regu_type[REGULATION_MAX] = {
/* elements not listed here will get PW_LMT_REGU_WW13(0) */
[REGULATION_WW] = PW_LMT_REGU_WW13,
[REGULATION_ETSI] = PW_LMT_REGU_ETSI,
[REGULATION_FCC] = PW_LMT_REGU_FCC,
[REGULATION_MKK] = PW_LMT_REGU_MKK,
[REGULATION_KCC] = PW_LMT_REGU_KCC,
[REGULATION_NCC] = PW_LMT_REGU_NCC,
[REGULATION_ACMA] = PW_LMT_REGU_ACMA,
[REGULATION_NA] = PW_LMT_REGU_NA,
[REGULATION_IC] = PW_LMT_REGU_IC,
[REGULATION_CHILE] = PW_LMT_REGU_CHILE,
[REGULATION_MEX] = PW_LMT_REGU_MEXICO,
};
const enum halrf_pw_lmt_regulation_type _tpo_to_pw_lmt_regu_type[TPO_NA] = {
/* elements not listed here will get PW_LMT_REGU_WW13(0) */
[TPO_CHILE] = PW_LMT_REGU_CHILE,
[TPO_QATAR] = PW_LMT_REGU_QATAR,
[TPO_UKRAINE] = PW_LMT_REGU_UKRAINE,
[TPO_CN] = PW_LMT_REGU_CN,
};
u8 halrf_get_regulation_info(struct rf_info *rf, u8 band)
{
struct rtw_regulation_info rg_info = {0};
struct halrf_pwr_info *pwr = &rf->pwr_info;
enum halrf_pw_lmt_regulation_type pw_lmt_type = PW_LMT_REGU_NULL;
u8 reg = REGULATION_NA;
u8 extra_regd_idx;
const char *bstr = NULL;
halrf_query_regulation_info(rf, &rg_info);
RF_DBG(rf, DBG_RF_INIT, "======>%s band=%d\n", __func__, band);
RF_DBG(rf, DBG_RF_INIT, "domain_code=%d regulation_2g=%d regulation_5g=%d chplan_ver=%d country_ver=%d rg_info.tpor=%d\n",
rg_info.domain_code, rg_info.regulation_2g, rg_info.regulation_5g, rg_info.chplan_ver, rg_info.country_ver, rg_info.tpo);
extra_regd_idx = halrf_get_power_limit_extra(rf);
if (extra_regd_idx != 0xff)
return extra_regd_idx;
#ifdef RTW_FLASH_98D
if (pwr->regulation_idx != 0xff)
return pwr->regulation_idx;
#else
if (band == BAND_ON_24G) {
reg = rg_info.regulation_2g;
bstr = "2g";
} else if (band == BAND_ON_5G) {
reg = rg_info.regulation_5g;
bstr = "5g";
} else if (band == BAND_ON_6G) {
/* TODO: 6G regulation */
bstr = "6g";
}
/* TODO: consider _hal_file_regd_ext */
if (rg_info.tpo != TPO_NA) {
pw_lmt_type = tpo_to_pw_lmt_regu_type(rg_info.tpo);
RF_DBG(rf, DBG_RF_INIT, "%s extra pw_lmt_regu=%s(%d)\n",
bstr, pw_lmt_regu_type_str(pw_lmt_type), pw_lmt_type);
} else {
if (reg == REGULATION_NA)
return PW_LMT_REGU_NULL; /* return this to distinguish from PW_LMT_REGU_NA done by NONE option from TXPWR_LMT.txt */
pw_lmt_type = regulation_to_pw_lmt_regu_type(reg);
}
if (pwr->regulation[band][pw_lmt_type] != true) {
RF_DBG(rf, DBG_RF_INIT, "%s pw_lmt_regu=%s(%d) is not exist return WW13 !!!\n",
bstr, pw_lmt_regu_type_str(pw_lmt_type), pw_lmt_type);
return PW_LMT_REGU_WW13;
}
#endif
if (rf->phl_com->drv_mode == RTW_DRV_MODE_MP)
return regulation_to_pw_lmt_regu_type(pwr->mp_regulation);
return pw_lmt_type;
}
const char *halrf_get_pw_lmt_regu_type_str(struct rf_info *rf, u8 band)
{
u8 reg = halrf_get_regulation_info(rf, band);
return pw_lmt_regu_type_str(reg);
}
void halrf_power_by_rate_store_to_array(struct rf_info *rf,
u32 band, u32 tx_num, u32 rate_id, u32 data)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
RF_DBG(rf, DBG_RF_INIT, "======>%s band=%d tx_num=%d rate_id=%d data=0x%x\n",
__func__, band, tx_num, rate_id, data);
if (band != (u32)BAND_ON_24G && band != (u32)BAND_ON_5G && band != (u32)BAND_ON_6G)
RF_DBG(rf, DBG_RF_INIT, "Invalid Band %d\n", band);
if (tx_num > 4 && tx_num != 15)
RF_DBG(rf, DBG_RF_INIT, "Invalid TxNum %d\n", tx_num);
if (band == 0 && tx_num == 0 && rate_id == 0) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK1] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK2] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK5_5] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK11] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 0 && rate_id == 1) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM6] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM9] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM12] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM18] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 0 && rate_id == 2) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM24] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM36] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM48] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM54] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 0 && rate_id == 3) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS2] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS3] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS2] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS3] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS2] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS3] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 0 && rate_id == 4) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS4] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS5] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS6] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS7] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS4] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS5] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS6] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS7] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS4] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS5] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS6] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS7] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 0 && rate_id == 5) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS8] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS1_MCS9] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS8] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS9] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS10] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS1_MCS11] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 0 && rate_id == 6) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS3] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS1_MCS4] = (s8)((data & 0xff000000) >> 24);
} else if (band == 0 && tx_num == 15 && rate_id == 7) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_OFFSET] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HT_OFFSET] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM_OFFSET] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_CCK_OFFSET] = (s8)((data & 0xff000000) >> 24);
} else if (band == 0 && tx_num == 15 && rate_id == 8) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_OFFSET] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 1 && rate_id == 3) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS8] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS9] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS10] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS11] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS2] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS3] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS2] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS3] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 1 && rate_id == 4) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS12] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS13] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS14] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_MCS15] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS4] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS5] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS6] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS7] = (s8)((data & 0xff000000) >> 24);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS4] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS5] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS6] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS7] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 1 && rate_id == 5) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS8] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_NSS2_MCS9] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS8] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS9] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS10] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HE_NSS2_MCS11] = (s8)((data & 0xff000000) >> 24);
} else if (tx_num == 1 && rate_id == 6) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS0] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS1] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS3] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_NSS2_MCS4] = (s8)((data & 0xff000000) >> 24);
} else if (band == 1 && tx_num == 15 && rate_id == 9) {
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HEDCM_OFFSET] = (s8)(data & 0xff);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_VHT_OFFSET] = (s8)((data & 0xff00) >> 8);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_HT_OFFSET] = (s8)((data & 0xff0000) >> 16);
pwr->tx_pwr_by_rate[band][HALRF_DATA_RATE_OFDM_OFFSET] = (s8)((data & 0xff000000) >> 24);
}
}
u8 halrf_get_ch_idx_to_limit_array(struct rf_info *rf, u8 channel)
{
u8 channelIndex;
if (channel >= 1 && channel <= 14)
channelIndex = channel - 1;
else if (channel >= 36 && channel <= 64)
channelIndex = (channel - 36) / 2;
else if (channel >= 100 && channel <= 144)
channelIndex = ((channel - 100) / 2) + 15;
else if (channel >= 149 && channel <= 177)
channelIndex = ((channel - 149) / 2) + 38;
else
channelIndex = 0;
return channelIndex;
}
u8 halrf_get_limit_ch_idx_to_ch_idx(struct rf_info *rf, u8 band, u8 channel)
{
u8 channelIndex;
if (band == PW_LMT_BAND_2_4G) {
if (channel >= 0 && channel <= 13)
channelIndex = channel + 1;
else
channelIndex = 0;
} else {
if (channel >= 0 && channel <= 14)
channelIndex = channel * 2 + 36;
else if (channel >= 15 && channel <= 37)
channelIndex = (channel - 15) * 2 + 100;
else if (channel >= 38 && channel <= 52)
channelIndex = (channel - 38) * 2 + 149;
else
channelIndex = 0;
}
return channelIndex;
}
u16 halrf_hw_rate_to_pwr_by_rate(struct rf_info *rf, u16 rate)
{
u16 ret_rate = HALRF_DATA_RATE_OFDM6;
switch(rate) {
case RTW_DATA_RATE_CCK1: ret_rate = HALRF_DATA_RATE_CCK1; break;
case RTW_DATA_RATE_CCK2: ret_rate = HALRF_DATA_RATE_CCK2; break;
case RTW_DATA_RATE_CCK5_5: ret_rate = HALRF_DATA_RATE_CCK5_5; break;
case RTW_DATA_RATE_CCK11: ret_rate = HALRF_DATA_RATE_CCK11; break;
case RTW_DATA_RATE_OFDM6: ret_rate = HALRF_DATA_RATE_OFDM6; break;
case RTW_DATA_RATE_OFDM9: ret_rate = HALRF_DATA_RATE_OFDM9; break;
case RTW_DATA_RATE_OFDM12: ret_rate = HALRF_DATA_RATE_OFDM12; break;
case RTW_DATA_RATE_OFDM18: ret_rate = HALRF_DATA_RATE_OFDM18; break;
case RTW_DATA_RATE_OFDM24: ret_rate = HALRF_DATA_RATE_OFDM24; break;
case RTW_DATA_RATE_OFDM36: ret_rate = HALRF_DATA_RATE_OFDM36; break;
case RTW_DATA_RATE_OFDM48: ret_rate = HALRF_DATA_RATE_OFDM48; break;
case RTW_DATA_RATE_OFDM54: ret_rate = HALRF_DATA_RATE_OFDM54; break;
case RTW_DATA_RATE_MCS0: ret_rate = HALRF_DATA_RATE_MCS0; break;
case RTW_DATA_RATE_MCS1: ret_rate = HALRF_DATA_RATE_MCS1; break;
case RTW_DATA_RATE_MCS2: ret_rate = HALRF_DATA_RATE_MCS2; break;
case RTW_DATA_RATE_MCS3: ret_rate = HALRF_DATA_RATE_MCS3; break;
case RTW_DATA_RATE_MCS4: ret_rate = HALRF_DATA_RATE_MCS4; break;
case RTW_DATA_RATE_MCS5: ret_rate = HALRF_DATA_RATE_MCS5; break;
case RTW_DATA_RATE_MCS6: ret_rate = HALRF_DATA_RATE_MCS6; break;
case RTW_DATA_RATE_MCS7: ret_rate = HALRF_DATA_RATE_MCS7; break;
case RTW_DATA_RATE_MCS8: ret_rate = HALRF_DATA_RATE_MCS8; break;
case RTW_DATA_RATE_MCS9: ret_rate = HALRF_DATA_RATE_MCS9; break;
case RTW_DATA_RATE_MCS10: ret_rate = HALRF_DATA_RATE_MCS10; break;
case RTW_DATA_RATE_MCS11: ret_rate = HALRF_DATA_RATE_MCS11; break;
case RTW_DATA_RATE_MCS12: ret_rate = HALRF_DATA_RATE_MCS12; break;
case RTW_DATA_RATE_MCS13: ret_rate = HALRF_DATA_RATE_MCS13; break;
case RTW_DATA_RATE_MCS14: ret_rate = HALRF_DATA_RATE_MCS14; break;
case RTW_DATA_RATE_MCS15: ret_rate = HALRF_DATA_RATE_MCS15; break;
case RTW_DATA_RATE_MCS16: ret_rate = HALRF_DATA_RATE_MCS16; break;
case RTW_DATA_RATE_MCS17: ret_rate = HALRF_DATA_RATE_MCS17; break;
case RTW_DATA_RATE_MCS18: ret_rate = HALRF_DATA_RATE_MCS18; break;
case RTW_DATA_RATE_MCS19: ret_rate = HALRF_DATA_RATE_MCS19; break;
case RTW_DATA_RATE_MCS20: ret_rate = HALRF_DATA_RATE_MCS20; break;
case RTW_DATA_RATE_MCS21: ret_rate = HALRF_DATA_RATE_MCS21; break;
case RTW_DATA_RATE_MCS22: ret_rate = HALRF_DATA_RATE_MCS22; break;
case RTW_DATA_RATE_MCS23: ret_rate = HALRF_DATA_RATE_MCS23; break;
case RTW_DATA_RATE_MCS24: ret_rate = HALRF_DATA_RATE_MCS24; break;
case RTW_DATA_RATE_MCS25: ret_rate = HALRF_DATA_RATE_MCS25; break;
case RTW_DATA_RATE_MCS26: ret_rate = HALRF_DATA_RATE_MCS26; break;
case RTW_DATA_RATE_MCS27: ret_rate = HALRF_DATA_RATE_MCS27; break;
case RTW_DATA_RATE_MCS28: ret_rate = HALRF_DATA_RATE_MCS28; break;
case RTW_DATA_RATE_MCS29: ret_rate = HALRF_DATA_RATE_MCS29; break;
case RTW_DATA_RATE_MCS30: ret_rate = HALRF_DATA_RATE_MCS30; break;
case RTW_DATA_RATE_MCS31: ret_rate = HALRF_DATA_RATE_MCS31; break;
case RTW_DATA_RATE_VHT_NSS1_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS0; break;
case RTW_DATA_RATE_VHT_NSS1_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS1; break;
case RTW_DATA_RATE_VHT_NSS1_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS2; break;
case RTW_DATA_RATE_VHT_NSS1_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS3; break;
case RTW_DATA_RATE_VHT_NSS1_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS4; break;
case RTW_DATA_RATE_VHT_NSS1_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS5; break;
case RTW_DATA_RATE_VHT_NSS1_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS6; break;
case RTW_DATA_RATE_VHT_NSS1_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS7; break;
case RTW_DATA_RATE_VHT_NSS1_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS8; break;
case RTW_DATA_RATE_VHT_NSS1_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS1_MCS9; break;
case RTW_DATA_RATE_VHT_NSS2_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS0; break;
case RTW_DATA_RATE_VHT_NSS2_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS1; break;
case RTW_DATA_RATE_VHT_NSS2_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS2; break;
case RTW_DATA_RATE_VHT_NSS2_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS3; break;
case RTW_DATA_RATE_VHT_NSS2_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS4; break;
case RTW_DATA_RATE_VHT_NSS2_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS5; break;
case RTW_DATA_RATE_VHT_NSS2_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS6; break;
case RTW_DATA_RATE_VHT_NSS2_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS7; break;
case RTW_DATA_RATE_VHT_NSS2_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS8; break;
case RTW_DATA_RATE_VHT_NSS2_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS2_MCS9; break;
case RTW_DATA_RATE_VHT_NSS3_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS0; break;
case RTW_DATA_RATE_VHT_NSS3_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS1; break;
case RTW_DATA_RATE_VHT_NSS3_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS2; break;
case RTW_DATA_RATE_VHT_NSS3_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS3; break;
case RTW_DATA_RATE_VHT_NSS3_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS4; break;
case RTW_DATA_RATE_VHT_NSS3_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS5; break;
case RTW_DATA_RATE_VHT_NSS3_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS6; break;
case RTW_DATA_RATE_VHT_NSS3_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS7; break;
case RTW_DATA_RATE_VHT_NSS3_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS8; break;
case RTW_DATA_RATE_VHT_NSS3_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS3_MCS9; break;
case RTW_DATA_RATE_VHT_NSS4_MCS0: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS0; break;
case RTW_DATA_RATE_VHT_NSS4_MCS1: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS1; break;
case RTW_DATA_RATE_VHT_NSS4_MCS2: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS2; break;
case RTW_DATA_RATE_VHT_NSS4_MCS3: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS3; break;
case RTW_DATA_RATE_VHT_NSS4_MCS4: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS4; break;
case RTW_DATA_RATE_VHT_NSS4_MCS5: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS5; break;
case RTW_DATA_RATE_VHT_NSS4_MCS6: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS6; break;
case RTW_DATA_RATE_VHT_NSS4_MCS7: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS7; break;
case RTW_DATA_RATE_VHT_NSS4_MCS8: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS8; break;
case RTW_DATA_RATE_VHT_NSS4_MCS9: ret_rate = HALRF_DATA_RATE_VHT_NSS4_MCS9; break;
case RTW_DATA_RATE_HE_NSS1_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS0; break;
case RTW_DATA_RATE_HE_NSS1_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS1; break;
case RTW_DATA_RATE_HE_NSS1_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS2; break;
case RTW_DATA_RATE_HE_NSS1_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS3; break;
case RTW_DATA_RATE_HE_NSS1_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS4; break;
case RTW_DATA_RATE_HE_NSS1_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS5; break;
case RTW_DATA_RATE_HE_NSS1_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS6; break;
case RTW_DATA_RATE_HE_NSS1_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS7; break;
case RTW_DATA_RATE_HE_NSS1_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS8; break;
case RTW_DATA_RATE_HE_NSS1_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS9; break;
case RTW_DATA_RATE_HE_NSS1_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS10; break;
case RTW_DATA_RATE_HE_NSS1_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS1_MCS11; break;
case RTW_DATA_RATE_HE_NSS2_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS0; break;
case RTW_DATA_RATE_HE_NSS2_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS1; break;
case RTW_DATA_RATE_HE_NSS2_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS2; break;
case RTW_DATA_RATE_HE_NSS2_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS3; break;
case RTW_DATA_RATE_HE_NSS2_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS4; break;
case RTW_DATA_RATE_HE_NSS2_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS5; break;
case RTW_DATA_RATE_HE_NSS2_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS6; break;
case RTW_DATA_RATE_HE_NSS2_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS7; break;
case RTW_DATA_RATE_HE_NSS2_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS8; break;
case RTW_DATA_RATE_HE_NSS2_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS9; break;
case RTW_DATA_RATE_HE_NSS2_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS10; break;
case RTW_DATA_RATE_HE_NSS2_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS2_MCS11; break;
case RTW_DATA_RATE_HE_NSS3_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS0; break;
case RTW_DATA_RATE_HE_NSS3_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS1; break;
case RTW_DATA_RATE_HE_NSS3_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS2; break;
case RTW_DATA_RATE_HE_NSS3_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS3; break;
case RTW_DATA_RATE_HE_NSS3_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS4; break;
case RTW_DATA_RATE_HE_NSS3_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS5; break;
case RTW_DATA_RATE_HE_NSS3_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS6; break;
case RTW_DATA_RATE_HE_NSS3_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS7; break;
case RTW_DATA_RATE_HE_NSS3_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS8; break;
case RTW_DATA_RATE_HE_NSS3_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS9; break;
case RTW_DATA_RATE_HE_NSS3_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS10; break;
case RTW_DATA_RATE_HE_NSS3_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS3_MCS11; break;
case RTW_DATA_RATE_HE_NSS4_MCS0: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS0; break;
case RTW_DATA_RATE_HE_NSS4_MCS1: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS1; break;
case RTW_DATA_RATE_HE_NSS4_MCS2: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS2; break;
case RTW_DATA_RATE_HE_NSS4_MCS3: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS3; break;
case RTW_DATA_RATE_HE_NSS4_MCS4: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS4; break;
case RTW_DATA_RATE_HE_NSS4_MCS5: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS5; break;
case RTW_DATA_RATE_HE_NSS4_MCS6: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS6; break;
case RTW_DATA_RATE_HE_NSS4_MCS7: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS7; break;
case RTW_DATA_RATE_HE_NSS4_MCS8: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS8; break;
case RTW_DATA_RATE_HE_NSS4_MCS9: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS9; break;
case RTW_DATA_RATE_HE_NSS4_MCS10: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS10; break;
case RTW_DATA_RATE_HE_NSS4_MCS11: ret_rate = HALRF_DATA_RATE_HE_NSS4_MCS11; break;
}
return ret_rate;
}
u16 halrf_get_dcm_offset_pwr_by_rate(struct rf_info *rf, u16 rate,
u8 dcm, u8 offset)
{
u16 rate_tmp = 0;
if (dcm == 0)
rate_tmp = halrf_hw_rate_to_pwr_by_rate(rf, rate);
else if (dcm == 1) {
if (rate == RTW_DATA_RATE_HE_NSS1_MCS0)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS0;
else if (rate == RTW_DATA_RATE_HE_NSS1_MCS1)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS1;
else if (rate == RTW_DATA_RATE_HE_NSS1_MCS3)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS3;
else if (rate == RTW_DATA_RATE_HE_NSS1_MCS4)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS1_MCS4;
else if (rate == RTW_DATA_RATE_HE_NSS2_MCS0)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS0;
else if (rate == RTW_DATA_RATE_HE_NSS2_MCS1)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS1;
else if (rate == RTW_DATA_RATE_HE_NSS2_MCS3)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS3;
else if (rate == RTW_DATA_RATE_HE_NSS2_MCS4)
rate_tmp = HALRF_DATA_RATE_HEDCM_NSS2_MCS4;
}
if (offset == 1) {
/*if (dcm == 1)*/
if (rate >= RTW_DATA_RATE_HE_NSS1_MCS0 && rate <= RTW_DATA_RATE_HE_NSS4_MCS11)
rate_tmp = HALRF_DATA_RATE_HEDCM_OFFSET;
if (rate >= RTW_DATA_RATE_VHT_NSS1_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS4_MCS9)
rate_tmp = HALRF_DATA_RATE_VHT_OFFSET;
if (rate >= RTW_DATA_RATE_MCS0 && rate <= RTW_DATA_RATE_MCS31)
rate_tmp = HALRF_DATA_RATE_HT_OFFSET;
if (rate >= RTW_DATA_RATE_OFDM6 && rate <= RTW_DATA_RATE_OFDM54)
rate_tmp = HALRF_DATA_RATE_OFDM_OFFSET;
if (rate >= RTW_DATA_RATE_CCK1 && rate <= RTW_DATA_RATE_CCK11)
rate_tmp = HALRF_DATA_RATE_CCK_OFFSET;
}
return rate_tmp;
}
u8 halrf_hw_rate_to_limit_rate_tx_num(struct rf_info *rf, u16 rate)
{
if (rate >= RTW_DATA_RATE_CCK1 && rate <= RTW_DATA_RATE_CCK11)
return PW_LMT_RS_CCK;
else if (rate >= RTW_DATA_RATE_OFDM6 && rate <= RTW_DATA_RATE_OFDM54)
return PW_LMT_RS_OFDM;
else if (rate >= RTW_DATA_RATE_MCS0 && rate <= RTW_DATA_RATE_MCS7)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_MCS8 && rate <= RTW_DATA_RATE_MCS15)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_MCS16 && rate <= RTW_DATA_RATE_MCS23)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_MCS24 && rate <= RTW_DATA_RATE_MCS31)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_VHT_NSS1_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS1_MCS9)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_VHT_NSS2_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS2_MCS9)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_VHT_NSS3_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS3_MCS9)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_VHT_NSS4_MCS0 && rate <= RTW_DATA_RATE_VHT_NSS4_MCS9)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_HE_NSS1_MCS0 && rate <= RTW_DATA_RATE_HE_NSS1_MCS11)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_HE_NSS2_MCS0 && rate <= RTW_DATA_RATE_HE_NSS2_MCS11)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_HE_NSS3_MCS0 && rate <= RTW_DATA_RATE_HE_NSS3_MCS11)
return PW_LMT_RS_HE;
else if (rate >= RTW_DATA_RATE_HE_NSS4_MCS0 && rate <= RTW_DATA_RATE_HE_NSS4_MCS11)
return PW_LMT_RS_HE;
else
return PW_LMT_RS_HE;
}
void halrf_power_limit_store_to_array(struct rf_info *rf,
u8 regulation, u8 band, u8 bandwidth, u8 rate,
u8 tx_num, u8 beamforming, u8 chnl, s8 val)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 ch = halrf_get_ch_idx_to_limit_array(rf, chnl);
RF_DBG(rf, DBG_RF_INIT, "======>%s regulation=%d band=%d bandwidth=%d rate=%d\n",
__func__, regulation, band, bandwidth, rate);
RF_DBG(rf, DBG_RF_INIT, "======>%s tx_num=%d beamforming=%d chnl=%d ch=%d val=%d\n",
__func__, tx_num, beamforming, chnl, ch, val);
if (band == PW_LMT_BAND_2_4G) {
pwr->tx_pwr_limit_2g[regulation][bandwidth][rate][beamforming][ch][tx_num] = val;
RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]\n",
val, regulation, bandwidth, rate, beamforming, ch, tx_num);
} else if (band == PW_LMT_BAND_5G) {
pwr->tx_pwr_limit_5g[regulation][bandwidth][rate][beamforming][ch][tx_num] = val;
RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]\n",
val, regulation, bandwidth, rate, beamforming, ch, tx_num);
}
}
void halrf_power_limit_set_worldwide(struct rf_info *rf)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u32 reg, bw, rate, bf, ch, tx_num;
s8 tmp;
RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__);
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) {
for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_MAX_2G_BANDWITH_NUM; bw++) {
tmp = 127;
for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) {
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]= %d\n",
reg, bw, rate, bf, ch, tx_num ,pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]);
if (tmp > pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] &&
pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] > 0) {
tmp = pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num];
}
}
if (tmp == 127)
tmp = 0;
pwr->tx_pwr_limit_2g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num] = tmp;
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]= %d\n",
PW_LMT_REGU_WW13, bw, rate, bf, ch, tx_num ,pwr->tx_pwr_limit_2g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num]);
}
}
}
}
}
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) {
for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_MAX_BANDWIDTH_NUM; bw++) {
tmp = 127;
for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) {
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n",
reg, bw, rate, bf, ch, tx_num, pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]);
if (tmp > pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] &&
pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] > 0) {
tmp = pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num];
}
}
if (tmp == 127)
tmp = 0;
pwr->tx_pwr_limit_5g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num] = tmp;
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n",
PW_LMT_REGU_WW13, bw, rate, bf, ch, tx_num, pwr->tx_pwr_limit_5g[PW_LMT_REGU_WW13][bw][rate][bf][ch][tx_num]);
}
}
}
}
}
RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__);
}
void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
u8 band, u8 bandwidth, u8 tx_num, u8 rate,
u8 regulation, u8 chnl, s8 val)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 ch = halrf_get_ch_idx_to_limit_array(rf, chnl);
RF_DBG(rf, DBG_RF_INIT, "======>%s regulation=%d band=%d bandwidth=%d rate=%d\n",
__func__, regulation, band, bandwidth, rate);
RF_DBG(rf, DBG_RF_INIT, "======>%s tx_num=%d chnl=%d ch=%d val=%d\n",
__func__, tx_num, chnl, ch, val);
if (band == PW_LMT_BAND_2_4G) {
pwr->tx_pwr_limit_ru_2g[regulation][bandwidth][rate][ch][tx_num] = val;
RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]\n",
val, regulation, bandwidth, rate, ch, tx_num);
} else if (band == PW_LMT_BAND_5G) {
pwr->tx_pwr_limit_ru_5g[regulation][bandwidth][rate][ch][tx_num] = val;
RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]\n",
val, regulation, bandwidth, rate, ch, tx_num);
}
}
void halrf_power_limit_ru_set_worldwide(struct rf_info *rf)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u32 reg, bw, rate, ch, tx_num;
s8 tmp;
RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__);
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) {
tmp = 127;
for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) {
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]= %d\n",
reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]);
if (tmp > pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] &&
pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] > 0) {
tmp = pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num];
}
}
if (tmp == 127)
tmp = 0;
pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num] = tmp;
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]= %d\n",
PW_LMT_REGU_WW13, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num]);
}
}
}
}
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) {
tmp = 127;
for (reg = 0; reg < PW_LMT_MAX_REGULATION_NUM; reg++) {
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n",
reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]);
if (tmp > pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] &&
pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] > 0) {
tmp = pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num];
}
}
if (tmp == 127)
tmp = 0;
pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num] = tmp;
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n",
PW_LMT_REGU_WW13, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_WW13][bw][rate][ch][tx_num]);
}
}
}
}
RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__);
}
void halrf_power_limit_set_ext_pwr_limit_table(struct rf_info *rf,
enum phl_phy_idx phy)
{
#ifdef SPF_PHL_RF_019_SAR
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_hal_com_t *hal = rf->hal_com;
u32 reg, bw, rate, bf, ch, tx_num;
s8 ext_pwr = 0;
u8 real_ch;
RF_DBG(rf, DBG_RF_INIT, "======>%s phy=%d\n", __func__, phy);
reg = (u32)halrf_get_regulation_info(rf, BAND_ON_24G);
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_2_4g[tx_num];
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) {
for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_MAX_2G_BANDWITH_NUM; bw++) {
RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_2_4g[%d]=%d pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]= %d\n",
tx_num, ext_pwr,
reg, bw, rate, bf, ch, tx_num , pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num]);
if (ext_pwr > 0) {
if (pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] > 0 &&
pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num] < ext_pwr) {
pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] =
pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num];
} else {
pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = ext_pwr;
}
} else {
pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] =
pwr->tx_pwr_limit_2g[reg][bw][rate][bf][ch][tx_num];
}
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d] = %d\n",
PW_LMT_REGU_EXT_PWR, bw, rate, bf, ch, tx_num ,
pwr->tx_pwr_limit_2g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num]);
}
}
}
}
}
reg = (u32)halrf_get_regulation_info(rf, BAND_ON_5G);
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) {
real_ch = halrf_get_limit_ch_idx_to_ch_idx(rf, PW_LMT_BAND_5G, (u8)ch);
if (real_ch >= 36 && real_ch <= 48)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band1[tx_num];
else if (real_ch >= 50 && real_ch <= 64)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band2[tx_num];
else if (real_ch >= 100 && real_ch <= 144)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band3[tx_num];
else if (real_ch >= 149 && real_ch <= 177)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band4[tx_num];
for (bf = 0; bf < PW_LMT_MAX_BF_NUM; bf++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_MAX_BANDWIDTH_NUM; bw++) {
RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_5g[%d]=%d pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n",
tx_num, ext_pwr,
reg, bw, rate, bf, ch, tx_num , pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num]);
if (ext_pwr > 0) {
if (pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] > 0 &&
pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num] < ext_pwr) {
pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] =
pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num];
} else {
pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] = ext_pwr;
}
} else {
pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num] =
pwr->tx_pwr_limit_5g[reg][bw][rate][bf][ch][tx_num];
}
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]= %d\n",
PW_LMT_REGU_EXT_PWR, bw, rate, bf, ch, tx_num,
pwr->tx_pwr_limit_5g[PW_LMT_REGU_EXT_PWR][bw][rate][bf][ch][tx_num]);
}
}
}
}
}
RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__);
#endif
}
void halrf_power_limit_set_ext_pwr_limit_ru_table(struct rf_info *rf,
enum phl_phy_idx phy)
{
#ifdef SPF_PHL_RF_019_SAR
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_hal_com_t *hal = rf->hal_com;
u32 reg, bw, rate, ch, tx_num;
s8 ext_pwr = 0;
u8 real_ch;
RF_DBG(rf, DBG_RF_INIT, "======>%s phy=%d\n", __func__, phy);
reg = (u32)halrf_get_regulation_info(rf, BAND_ON_24G);
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_2_4g[tx_num];
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_2G; ch++) {
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) {
RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_2_4g[%d]=%d pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]= %d\n",
tx_num, ext_pwr,
reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num]);
if (ext_pwr > 0) {
if (pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] > 0 &&
pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num] < ext_pwr) {
pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] =
pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num];
} else {
pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = ext_pwr;
}
} else {
pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] =
pwr->tx_pwr_limit_ru_2g[reg][bw][rate][ch][tx_num];
}
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d] = %d\n",
PW_LMT_REGU_EXT_PWR, bw, rate, ch, tx_num,
pwr->tx_pwr_limit_ru_2g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num]);
}
}
}
}
reg = (u32)halrf_get_regulation_info(rf, BAND_ON_5G);
for (tx_num = 0; tx_num < MAX_HALRF_PATH; tx_num++) {
for (ch = 0; ch < PW_LMT_MAX_CHANNEL_NUMBER_5G; ch++) {
real_ch = halrf_get_limit_ch_idx_to_ch_idx(rf, PW_LMT_BAND_5G, (u8)ch);
if (real_ch >= 36 && real_ch <= 48)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band1[tx_num];
else if (real_ch >= 50 && real_ch <= 64)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band2[tx_num];
else if (real_ch >= 100 && real_ch <= 144)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band3[tx_num];
else if (real_ch >= 149 && real_ch <= 177)
ext_pwr = hal->rtw_tpu_ext_pwr_lmt_i[phy].ext_pwr_lmt_5g_band4[tx_num];
for (rate = 0; rate < PW_LMT_MAX_RS_NUM; rate++) {
for (bw = 0; bw < PW_LMT_RU_BW_NULL; bw++) {
RF_DBG(rf, DBG_RF_INIT, "ext_pwr_lmt_5g[%d]=%d pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n",
tx_num, ext_pwr,
reg, bw, rate, ch, tx_num, pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num]);
if (ext_pwr > 0) {
if (pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] > 0 &&
pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num] < ext_pwr) {
pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] =
pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num];
} else {
pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] = ext_pwr;
}
} else {
pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num] =
pwr->tx_pwr_limit_ru_5g[reg][bw][rate][ch][tx_num];
}
RF_DBG(rf, DBG_RF_INIT, "pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]= %d\n",
PW_LMT_REGU_EXT_PWR, bw, rate, ch, tx_num,
pwr->tx_pwr_limit_ru_5g[PW_LMT_REGU_EXT_PWR][bw][rate][ch][tx_num]);
}
}
}
}
RF_DBG(rf, DBG_RF_INIT, "<======%s finish!!!\n", __func__);
#endif
}
s8 halrf_get_power_by_rate(struct rf_info *rf,
enum phl_phy_idx phy,
u8 rf_path, u16 rate, u8 dcm, u8 offset)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u8 band;
u16 rate_tmp;
s8 pwr_by_rate;
u8 channel = rf->hal_com->band[phy].cur_chandef.center_ch;
RF_DBG(rf, DBG_RF_POWER, "======>%s rf_path=%d rate=0x%x dcm=%d\n",
__func__, rf_path, rate, dcm);
if (channel >= 1 && channel <= 14)
band = PW_LMT_BAND_2_4G;
else
band = PW_LMT_BAND_5G;
rate_tmp = halrf_get_dcm_offset_pwr_by_rate(rf, rate, dcm, offset);
if ((rate_tmp >= HALRF_DATA_RATE_CCK1 && rate_tmp <= HALRF_DATA_RATE_CCK11) ||
rate_tmp == HALRF_DATA_RATE_CCK_OFFSET) {
pwr_by_rate = pwr->tx_pwr_by_rate[PW_LMT_BAND_2_4G][rate_tmp];
RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] channel=%d\n",
pwr_by_rate, PW_LMT_BAND_2_4G, rate_tmp, channel);
} else {
pwr_by_rate = pwr->tx_pwr_by_rate[band][rate_tmp];
RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] channel=%d\n",
pwr_by_rate, band, rate_tmp, channel);
}
return pwr_by_rate;
}
s8 halrf_get_power_by_rate_band(struct rf_info *rf,
enum phl_phy_idx phy, u16 rate, u8 dcm, u8 offset, u32 band)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
u16 rate_tmp;
s8 pwr_by_rate;
RF_DBG(rf, DBG_RF_POWER, "======>%s rate=0x%x dcm=%d band=%d\n",
__func__, rate, dcm, band);
rate_tmp = halrf_get_dcm_offset_pwr_by_rate(rf, rate, dcm, offset);
if ((rate_tmp >= HALRF_DATA_RATE_CCK1 && rate_tmp <= HALRF_DATA_RATE_CCK11) ||
rate_tmp == HALRF_DATA_RATE_CCK_OFFSET) {
pwr_by_rate = pwr->tx_pwr_by_rate[PW_LMT_BAND_2_4G][rate_tmp];
RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] band=%d\n",
pwr_by_rate, PW_LMT_BAND_2_4G, rate_tmp, band);
} else {
pwr_by_rate = pwr->tx_pwr_by_rate[band][rate_tmp];
RF_DBG(rf, DBG_RF_POWER, "pwr_by_rate(%d)=pwr->tx_pwr_by_rate[%d][%d] band=%d\n",
pwr_by_rate, band, rate_tmp, band);
}
return pwr_by_rate;
}
s8 halrf_get_power_limit(struct rf_info *rf,
enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
u8 beamforming, u8 tx_num, u8 channel)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_phl_com_t *phl = rf->phl_com;
#ifdef SPF_PHL_RF_019_SAR
struct rtw_hal_com_t *hal = rf->hal_com;
#endif
s8 pwr_limit;
u8 limit_rate = PW_LMT_RS_CCK, limit_ch, reg;
RF_DBG(rf, DBG_RF_POWER, "======>%s rf_path=%d rate=0x%x beamforming=%d\n",
__func__, rf_path, rate, beamforming);
limit_rate = halrf_hw_rate_to_limit_rate_tx_num(rf, rate);
limit_ch = halrf_get_ch_idx_to_limit_array(rf, channel);
if (channel >= 1 && channel <= 14) {
#ifdef SPF_PHL_RF_019_SAR
if (hal->ext_pwr_lmt_en == true)
reg = PW_LMT_REGU_EXT_PWR;
else
#endif
reg = halrf_get_regulation_info(rf, BAND_ON_24G);
pwr_limit = pwr->tx_pwr_limit_2g[reg][bandwidth][limit_rate][beamforming][limit_ch][tx_num];
RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]\n",
pwr_limit, reg, bandwidth, limit_rate, beamforming, limit_ch, tx_num);
} else {
#ifdef SPF_PHL_RF_019_SAR
if (hal->ext_pwr_lmt_en == true)
reg = PW_LMT_REGU_EXT_PWR;
else
#endif
reg = halrf_get_regulation_info(rf, BAND_ON_5G);
pwr_limit = pwr->tx_pwr_limit_5g[reg][bandwidth][limit_rate][beamforming][limit_ch][tx_num];
RF_DBG(rf, DBG_RF_POWER, "pwr_limit(%d) = pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]\n",
pwr_limit, reg, bandwidth, limit_rate, beamforming, limit_ch, tx_num);
}
if (pwr_limit == 127)
pwr_limit = 0;
return pwr_limit;
}
s8 halrf_get_power_limit_ru(struct rf_info *rf,
enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
u8 tx_num, u8 channel)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_phl_com_t *phl = rf->phl_com;
#ifdef SPF_PHL_RF_019_SAR
struct rtw_hal_com_t *hal = rf->hal_com;
#endif
s8 pwr_limit_ru;
u8 limit_rate = PW_LMT_RS_CCK, limit_ch, reg;
RF_DBG(rf, DBG_RF_POWER, "======>%s phy=%d rf_path=%d rate=0x%x\n",
__func__, phy, rf_path, rate);
limit_rate = halrf_hw_rate_to_limit_rate_tx_num(rf, rate);
limit_ch = halrf_get_ch_idx_to_limit_array(rf, channel);
if (channel >= 1 && channel <= 14) {
#ifdef SPF_PHL_RF_019_SAR
if (hal->ext_pwr_lmt_en == true)
reg = PW_LMT_REGU_EXT_PWR;
else
#endif
reg = halrf_get_regulation_info(rf, BAND_ON_24G);
pwr_limit_ru = pwr->tx_pwr_limit_ru_2g[reg][bandwidth][limit_rate][limit_ch][tx_num];
RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_2g[%d][%d][%d][%d][%d]\n",
pwr_limit_ru, reg, bandwidth, limit_rate, limit_ch, tx_num);
} else {
#ifdef SPF_PHL_RF_019_SAR
if (hal->ext_pwr_lmt_en == true)
reg = PW_LMT_REGU_EXT_PWR;
else
#endif
reg = halrf_get_regulation_info(rf, BAND_ON_5G);
pwr_limit_ru = pwr->tx_pwr_limit_ru_5g[reg][bandwidth][limit_rate][limit_ch][tx_num];
RF_DBG(rf, DBG_RF_POWER, "pwr_limit_ru(%d) = pwr->tx_pwr_limit_ru_5g[%d][%d][%d][%d][%d]\n",
pwr_limit_ru, reg, bandwidth, limit_rate, limit_ch, tx_num);
}
if (pwr_limit_ru == 127)
pwr_limit_ru = 0;
return pwr_limit_ru;
}
s16 halrf_get_power(void *rf_void,
u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth,
u8 beamforming, u8 channel)
{
struct rf_info *rf = (struct rf_info *)rf_void;
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_phl_com_t *phl = rf->phl_com;
u8 band, limit_rate = PW_LMT_RS_CCK, tx_num = PW_LMT_PH_1T, limit_ch;
u16 rate_tmp;
s16 pwr_by_rate, pwr_limit, power;
RF_DBG(rf, DBG_RF_INIT, "======>%s rf_path=%d rate=%d dcm=%d bw=%d bf=%d ch=%d\n",
__func__, rf_path, rate, dcm, bandwidth, beamforming, channel);
if (channel >= 1 && channel <= 14)
band = PW_LMT_BAND_2_4G;
else
band = PW_LMT_BAND_5G;
tx_num = rf_path;
rate_tmp = halrf_get_dcm_offset_pwr_by_rate(rf, rate, dcm, offset);
pwr_by_rate = (s16)pwr->tx_pwr_by_rate[band][rate_tmp];
RF_DBG(rf, DBG_RF_INIT, "pwr_by_rate(%d)=(s16)pwr->tx_pwr_by_rate[%d][%d]\n",
pwr_by_rate, band, rate_tmp);
limit_rate = halrf_hw_rate_to_limit_rate_tx_num(rf, rate);
limit_ch = halrf_get_ch_idx_to_limit_array(rf, channel);
if (channel >= 1 && channel <= 14) {
pwr_limit = (s16)pwr->tx_pwr_limit_2g[halrf_get_regulation_info(rf, BAND_ON_24G)][bandwidth][limit_rate][beamforming][limit_ch][tx_num];
RF_DBG(rf, DBG_RF_INIT, "pwr_limit(%d) = (s16)pwr->tx_pwr_limit_2g[%d][%d][%d][%d][%d][%d]\n",
pwr_limit, halrf_get_regulation_info(rf, BAND_ON_24G), bandwidth, limit_rate, beamforming, limit_ch, tx_num);
} else {
pwr_limit = (s16)pwr->tx_pwr_limit_5g[halrf_get_regulation_info(rf, BAND_ON_5G)][bandwidth][limit_rate][beamforming][limit_ch][tx_num];
RF_DBG(rf, DBG_RF_INIT, "pwr_limit(%d) = (s16)pwr->tx_pwr_limit_5g[%d][%d][%d][%d][%d][%d]\n",
pwr_limit, halrf_get_regulation_info(rf, BAND_ON_5G), bandwidth, limit_rate, beamforming, limit_ch, tx_num);
}
if (pwr_by_rate > pwr_limit)
power = pwr_limit;
else
power = pwr_by_rate;
RF_DBG(rf, DBG_RF_INIT, "power = %d\n", power);
return power;
}
bool halrf_set_power(struct rf_info *rf, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table)
{
struct rtw_hal_com_t *hal_com = rf->hal_com;
bool result = true;
#ifdef RF_8852A_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852A) {
halrf_set_power_8852a(rf, phy, pwr_table);
}
#endif
#ifdef RF_8852B_SUPPORT
if (hal_com->chip_id == CHIP_WIFI6_8852B) {
halrf_set_power_8852b(rf, phy, pwr_table);
}
#endif
return result;
}
bool halrf_get_efuse_power_table_switch(struct rf_info *rf, enum phl_phy_idx phy_idx)
{
struct rtw_phl_com_t *phl_com = rf->phl_com;
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_tpu_info *tpu = &rf->hal_com->band[phy_idx].rtw_tpu_i;
bool result = true;
pwr->pwr_table_switch_efuse = phl_com->dev_cap.rf_board_opt & 0x3;
pwr->pwr_by_rate_switch = phl_com->dev_cap.pwrbyrate_off;
pwr->pwr_limit_switch = phl_com->dev_cap.pwrlmt_type;
RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_by_rate_switch=%d\n",
__func__, pwr->pwr_by_rate_switch);
RF_DBG(rf, DBG_RF_POWER, "======>%s From Driver pwr->pwr_limit_switch=%d\n",
__func__, pwr->pwr_limit_switch);
RF_DBG(rf, DBG_RF_POWER, "======>%s From Efuse pwr->pwr_table_switch_efuse=%d\n",
__func__, pwr->pwr_table_switch_efuse);
if (pwr->pwr_limit_switch == PWLMT_DISABLE)
tpu->pwr_lmt_en = false;
else if (pwr->pwr_limit_switch == PWBYRATE_AND_PWLMT)
tpu->pwr_lmt_en = true;
else {
if (pwr->pwr_table_switch_efuse == 0)
tpu->pwr_lmt_en = false;
else if (pwr->pwr_table_switch_efuse == 2)
tpu->pwr_lmt_en = false;
else
tpu->pwr_lmt_en = true;
}
halrf_mac_write_pwr_limit_en(rf, phy_idx);
return result;
}
void halrf_set_power_table_switch(struct rf_info *rf,
enum phl_phy_idx phy, u8 pwr_by_rate, u8 pwr_limt)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
pwr->pwr_by_rate_switch = pwr_by_rate;
pwr->pwr_limit_switch = pwr_limt;
}
u8 halrf_get_power_limit_extra(struct rf_info *rf)
{
struct halrf_pwr_info *pwr = &rf->pwr_info;
struct rtw_para_pwrlmt_info_t *pwrlmt_info = NULL;
struct _halrf_file_regd_ext *pregd_codemap = NULL;
struct _halrf_file_regd_ext *array = NULL;
struct rtw_regulation_info rg_info = {0};
struct rtw_hal_com_t *hal = rf->hal_com;
u8 i, j, regd_idx = 0xff;
pwrlmt_info = &rf->phl_com->phy_sw_cap[HW_PHY_0].rf_txpwrlmt_info;
pregd_codemap = (struct _halrf_file_regd_ext *) pwrlmt_info->ext_reg_codemap;
if (pwrlmt_info->para_src == 0) {
RF_DBG(rf, DBG_RF_POWER, "======>%s is_form_folder=%d Return!!!\n",
__func__, pwrlmt_info->para_src);
return 0xff;
}
RF_DBG(rf, DBG_RF_POWER, "======>%s total_regd_idx=%d extra_limit_idx=%d\n",
__func__, pwrlmt_info->ext_regd_arridx, pwrlmt_info->ext_reg_map_num);
halrf_query_regulation_info(rf, &rg_info);
RF_DBG(rf, DBG_RF_POWER, "domain_code=0x%x country=%s regulation_2g=%d regulation_5g=%d chplan_ver=%d country_ver=%d\n",
rg_info.domain_code, rg_info.country, rg_info.regulation_2g, rg_info.regulation_5g, rg_info.chplan_ver, rg_info.country_ver);
for (i = 0; i <= pwrlmt_info->ext_regd_arridx; i++)
RF_DBG(rf, DBG_RF_POWER, "ext_regd_name[%d]=%s\n", i, pwrlmt_info->ext_regd_name[i]);
RF_DBG(rf, DBG_RF_POWER, "======> Start domain code Search\n");
for (i = 0; i < pwrlmt_info->ext_reg_map_num; i++) {
array = (struct _halrf_file_regd_ext *)&pregd_codemap[i];
RF_DBG(rf, DBG_RF_POWER, "======> %d\n", i);
RF_DBG(rf, DBG_RF_POWER, "ent->domain=0x%x\n", array->domain);
RF_DBG(rf, DBG_RF_POWER, "ent->country=%s\n", array->country);
RF_DBG(rf, DBG_RF_POWER, "ent->reg_name=%s\n", array->reg_name);
if (rg_info.domain_code == (u8)array->domain) {
RF_DBG(rf, DBG_RF_POWER, "Search rg_info.domain_code == Power limit array->domain\n");
for (j = 0; j <= pwrlmt_info->ext_regd_arridx; j++) {
if (_os_strcmp(array->reg_name, pwrlmt_info->ext_regd_name[j]) == 0) {
regd_idx = j;
i = (u8)pwrlmt_info->ext_reg_map_num;
RF_DBG(rf, DBG_RF_POWER, "======> Search regd_idx=%d\n", regd_idx);
break;
}
}
}
}
RF_DBG(rf, DBG_RF_POWER, "<====== End domain code Search\n");
RF_DBG(rf, DBG_RF_POWER, "======> Start Country code Search\n");
for (i = 0; i < pwrlmt_info->ext_reg_map_num; i++) {
array = (struct _halrf_file_regd_ext *)&pregd_codemap[i];
RF_DBG(rf, DBG_RF_POWER, "======> %d\n", i);
RF_DBG(rf, DBG_RF_POWER, "ent->domain=0x%x\n", array->domain);
RF_DBG(rf, DBG_RF_POWER, "ent->country=%s\n", array->country);
RF_DBG(rf, DBG_RF_POWER, "ent->reg_name=%s\n", array->reg_name);
if (hal_mem_cmp(hal, rg_info.country, array->country, 2) == 0 && _os_strcmp(rg_info.country, "") != 0) {
RF_DBG(rf, DBG_RF_POWER, "Search rg_info.country == Power limit array->country\n");
for (j = 0; j <= pwrlmt_info->ext_regd_arridx; j++) {
if (_os_strcmp(array->reg_name, pwrlmt_info->ext_regd_name[j]) == 0) {
regd_idx = j;
i = (u8)pwrlmt_info->ext_reg_map_num;
RF_DBG(rf, DBG_RF_POWER, "======> Search regd_idx=%d\n", regd_idx);
break;
}
}
}
}
RF_DBG(rf, DBG_RF_POWER, "<====== End Country code Search\n");
RF_DBG(rf, DBG_RF_POWER, "Return regd_idx = %d\n", regd_idx);
return regd_idx;
}
void halrf_reload_pwr_limit_tbl_and_set(struct rf_info *rf,
enum phl_phy_idx phy, enum phl_pwr_table pwr_table)
{
struct rtw_para_pwrlmt_info_t *pwrlmt_info = NULL;
bool is_form_folder;
u32 folder_len;
u32 *folder_array;
RF_DBG(rf, DBG_RF_POWER, "======>%s\n", __func__);
if (pwr_table == PWR_LIMIT) {
pwrlmt_info = &rf->phl_com->phy_sw_cap[HW_PHY_0].rf_txpwrlmt_info;
is_form_folder = pwrlmt_info->para_src;
folder_len = pwrlmt_info->para_data_len;
folder_array = pwrlmt_info->para_data;
RF_DBG(rf, DBG_RF_POWER, "Reload power limit table and set. is_form_folder=%d folder_len=%d\n",
is_form_folder, folder_len);
halrf_config_store_power_limit(rf , is_form_folder,
folder_len, folder_array);
halrf_set_power(rf, phy, pwr_table);
}
if (pwr_table == PWR_LIMIT_RU) {
pwrlmt_info = &rf->phl_com->phy_sw_cap[HW_PHY_0].rf_txpwrlmt_ru_info;
is_form_folder = pwrlmt_info->para_src;
folder_len = pwrlmt_info->para_data_len;
folder_array = pwrlmt_info->para_data;
RF_DBG(rf, DBG_RF_POWER, "Reload power limit RU table and set. is_form_folder=%d folder_len=%d\n",
is_form_folder, folder_len);
halrf_config_store_power_limit_ru(rf , is_form_folder,
folder_len, folder_array);
halrf_set_power(rf, phy, pwr_table);
}
RF_DBG(rf, DBG_RF_POWER, "<======%s finish!\n", __func__);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_pwr_table.c
|
C
|
agpl-3.0
| 55,746
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_PWR_TABLE_H_
#define _HALRF_PWR_TABLE_H_
/*@--------------------------Define Parameters-------------------------------*/
#define TX_PWR_BY_RATE_NUM_BAND 3
#define TX_PWR_BY_RATE_NUM_RF 4
#define PW_LMT_MAX_2G_BANDWITH_NUM 2
#define PW_LMT_MAX_CHANNEL_NUMBER_2G 14
#define PW_LMT_MAX_CHANNEL_NUMBER_5G 53
#define TX_PWR_BY_RATE_NUM_MAC 44
#define TX_PWR_LIMIT_NUM_MAC 80
#define TX_PWR_LIMIT_RU_NUM_MAC 30
#define RADIO_TO_FW_PAGE_SIZE 6
#define RADIO_TO_FW_DATA_SIZE 500
/*@-----------------------End Define Parameters-----------------------*/
/*power by rate*/
enum halrf_pw_by_rate_para_type {
PW_BYRATE_PARA_NSS1,
PW_BYRATE_PARA_NSS2,
PW_BYRATE_PARA_OFFS = 0xF
};
enum halrf_pw_by_rate_rate_type {
PW_BYRATE_RATE_11M_1M,
PW_BYRATE_RATE_18M_6M,
PW_BYRATE_RATE_54M_24M,
PW_BYRATE_RATE_MCS3_0,
PW_BYRATE_RATE_MCS7_4,
PW_BYRATE_RATE_MCS11_8,
PW_BYRATE_RATE_DCM4_0,
PW_BYRATE_RATE_AllRate2_1, /* CCK, OFDM, HT, VHT */
PW_BYRATE_RATE_AllRate2_2, /* HE_HEDCM */
PW_BYRATE_RATE_AllRate5_1, /* OFDM, HT, VHT, HE_HEDCM */
PW_BYRATE_RATE_NULL = 0xF
};
struct _halrf_file_regd_ext {
u16 domain;
char country[2];
char reg_name[10];
};
/*power limit*/
struct halrf_tx_pw_lmt {
u8 band;
u8 bw;
u8 ntx;
u8 rs;
u8 bf;
u8 reg;
u8 ch;
s8 val;
u8 tx_shap_idx;
};
struct halrf_tx_pw_lmt_ru {
u8 band;
u8 bw;
u8 ntx;
u8 rs;
u8 reg;
u8 ch;
s8 val;
u8 tx_shap_idx;
};
enum halrf_tx_pw_lmt_ru_bandwidth_type {
PW_LMT_RU_BW_RU26 = 0,
PW_LMT_RU_BW_RU52,
PW_LMT_RU_BW_RU106,
PW_LMT_RU_BW_NULL
};
enum halrf_pw_lmt_regulation_type {
PW_LMT_REGU_WW13 = 0,
PW_LMT_REGU_ETSI = 1,
PW_LMT_REGU_FCC = 2,
PW_LMT_REGU_MKK = 3,
PW_LMT_REGU_NA = 4,
PW_LMT_REGU_IC = 5,
PW_LMT_REGU_KCC = 6,
PW_LMT_REGU_ACMA = 7,
PW_LMT_REGU_NCC = 8,
PW_LMT_REGU_MEXICO = 9,
PW_LMT_REGU_CHILE = 10,
PW_LMT_REGU_UKRAINE = 11,
PW_LMT_REGU_CN = 12,
PW_LMT_REGU_QATAR = 13,
/* place predefined ones above */
PW_LMT_REGU_EXT_PWR,
PW_LMT_REGU_PREDEF_NUM,
PW_LMT_REGU_NULL, /* declare this to PW_LMT_MAX_REGULATION_NUM after limit array remove usage of PW_LMT_REGU_NULL */
PW_LMT_MAX_REGULATION_NUM = 32
};
enum halrf_tx_shape_modu_type {
TX_SHAPE_CCK,
TX_SHAPE_OFDM,
TX_SHAPE_MAX
};
enum halrf_pw_lmt_band_type {
PW_LMT_BAND_2_4G = 0,
PW_LMT_BAND_5G = 1,
PW_LMT_BAND_6G = 2,
PW_LMT_MAX_BAND = 3
};
enum halrf_pw_lmt_bandwidth_type {
PW_LMT_BW_20M = 0,
PW_LMT_BW_40M = 1,
PW_LMT_BW_80M = 2,
PW_LMT_BW_160M = 3,
PW_LMT_MAX_BANDWIDTH_NUM = 4
};
enum halrf_pw_lmt_ratesection_type {
PW_LMT_RS_CCK = 0,
PW_LMT_RS_OFDM = 1,
PW_LMT_RS_HT = 2,
PW_LMT_RS_VHT = 3,
PW_LMT_RS_HE = 4,
PW_LMT_MAX_RS_NUM = 5
};
enum halrf_pw_lmt_rfpath_type {
PW_LMT_PH_1T = 0,
PW_LMT_PH_2T = 1,
PW_LMT_PH_3T = 2,
PW_LMT_PH_4T = 3,
PW_LMT_MAX_PH_NUM = 4
};
enum halrf_pw_lmt_beamforming_type {
PW_LMT_NONBF = 0,
PW_LMT_BF = 1,
PW_LMT_MAX_BF_NUM = 2
};
enum halrf_data_rate {
HALRF_DATA_RATE_CCK1 = 0,
HALRF_DATA_RATE_CCK2 = 0x1,
HALRF_DATA_RATE_CCK5_5,
HALRF_DATA_RATE_CCK11,
HALRF_DATA_RATE_OFDM6,
HALRF_DATA_RATE_OFDM9,
HALRF_DATA_RATE_OFDM12,
HALRF_DATA_RATE_OFDM18,
HALRF_DATA_RATE_OFDM24,
HALRF_DATA_RATE_OFDM36,
HALRF_DATA_RATE_OFDM48 = 10,
HALRF_DATA_RATE_OFDM54,
HALRF_DATA_RATE_MCS0,
HALRF_DATA_RATE_MCS1,
HALRF_DATA_RATE_MCS2,
HALRF_DATA_RATE_MCS3,
HALRF_DATA_RATE_MCS4,
HALRF_DATA_RATE_MCS5,
HALRF_DATA_RATE_MCS6,
HALRF_DATA_RATE_MCS7,
HALRF_DATA_RATE_MCS8 = 20,
HALRF_DATA_RATE_MCS9,
HALRF_DATA_RATE_MCS10,
HALRF_DATA_RATE_MCS11,
HALRF_DATA_RATE_MCS12,
HALRF_DATA_RATE_MCS13,
HALRF_DATA_RATE_MCS14,
HALRF_DATA_RATE_MCS15,
HALRF_DATA_RATE_MCS16,
HALRF_DATA_RATE_MCS17,
HALRF_DATA_RATE_MCS18 = 30,
HALRF_DATA_RATE_MCS19,
HALRF_DATA_RATE_MCS20,
HALRF_DATA_RATE_MCS21,
HALRF_DATA_RATE_MCS22,
HALRF_DATA_RATE_MCS23,
HALRF_DATA_RATE_MCS24,
HALRF_DATA_RATE_MCS25,
HALRF_DATA_RATE_MCS26,
HALRF_DATA_RATE_MCS27,
HALRF_DATA_RATE_MCS28 = 40,
HALRF_DATA_RATE_MCS29,
HALRF_DATA_RATE_MCS30,
HALRF_DATA_RATE_MCS31,
HALRF_DATA_RATE_VHT_NSS1_MCS0,
HALRF_DATA_RATE_VHT_NSS1_MCS1,
HALRF_DATA_RATE_VHT_NSS1_MCS2,
HALRF_DATA_RATE_VHT_NSS1_MCS3,
HALRF_DATA_RATE_VHT_NSS1_MCS4,
HALRF_DATA_RATE_VHT_NSS1_MCS5,
HALRF_DATA_RATE_VHT_NSS1_MCS6 = 50,
HALRF_DATA_RATE_VHT_NSS1_MCS7,
HALRF_DATA_RATE_VHT_NSS1_MCS8,
HALRF_DATA_RATE_VHT_NSS1_MCS9,
HALRF_DATA_RATE_VHT_NSS2_MCS0,
HALRF_DATA_RATE_VHT_NSS2_MCS1,
HALRF_DATA_RATE_VHT_NSS2_MCS2,
HALRF_DATA_RATE_VHT_NSS2_MCS3,
HALRF_DATA_RATE_VHT_NSS2_MCS4,
HALRF_DATA_RATE_VHT_NSS2_MCS5,
HALRF_DATA_RATE_VHT_NSS2_MCS6 = 60,
HALRF_DATA_RATE_VHT_NSS2_MCS7,
HALRF_DATA_RATE_VHT_NSS2_MCS8,
HALRF_DATA_RATE_VHT_NSS2_MCS9,
HALRF_DATA_RATE_VHT_NSS3_MCS0,
HALRF_DATA_RATE_VHT_NSS3_MCS1,
HALRF_DATA_RATE_VHT_NSS3_MCS2,
HALRF_DATA_RATE_VHT_NSS3_MCS3,
HALRF_DATA_RATE_VHT_NSS3_MCS4,
HALRF_DATA_RATE_VHT_NSS3_MCS5,
HALRF_DATA_RATE_VHT_NSS3_MCS6 = 70,
HALRF_DATA_RATE_VHT_NSS3_MCS7,
HALRF_DATA_RATE_VHT_NSS3_MCS8,
HALRF_DATA_RATE_VHT_NSS3_MCS9,
HALRF_DATA_RATE_VHT_NSS4_MCS0,
HALRF_DATA_RATE_VHT_NSS4_MCS1,
HALRF_DATA_RATE_VHT_NSS4_MCS2,
HALRF_DATA_RATE_VHT_NSS4_MCS3,
HALRF_DATA_RATE_VHT_NSS4_MCS4,
HALRF_DATA_RATE_VHT_NSS4_MCS5,
HALRF_DATA_RATE_VHT_NSS4_MCS6 = 80,
HALRF_DATA_RATE_VHT_NSS4_MCS7,
HALRF_DATA_RATE_VHT_NSS4_MCS8,
HALRF_DATA_RATE_VHT_NSS4_MCS9,
HALRF_DATA_RATE_HE_NSS1_MCS0,
HALRF_DATA_RATE_HE_NSS1_MCS1,
HALRF_DATA_RATE_HE_NSS1_MCS2,
HALRF_DATA_RATE_HE_NSS1_MCS3,
HALRF_DATA_RATE_HE_NSS1_MCS4,
HALRF_DATA_RATE_HE_NSS1_MCS5,
HALRF_DATA_RATE_HE_NSS1_MCS6 = 90,
HALRF_DATA_RATE_HE_NSS1_MCS7,
HALRF_DATA_RATE_HE_NSS1_MCS8,
HALRF_DATA_RATE_HE_NSS1_MCS9,
HALRF_DATA_RATE_HE_NSS1_MCS10,
HALRF_DATA_RATE_HE_NSS1_MCS11,
HALRF_DATA_RATE_HE_NSS2_MCS0,
HALRF_DATA_RATE_HE_NSS2_MCS1,
HALRF_DATA_RATE_HE_NSS2_MCS2,
HALRF_DATA_RATE_HE_NSS2_MCS3,
HALRF_DATA_RATE_HE_NSS2_MCS4 = 100,
HALRF_DATA_RATE_HE_NSS2_MCS5,
HALRF_DATA_RATE_HE_NSS2_MCS6,
HALRF_DATA_RATE_HE_NSS2_MCS7,
HALRF_DATA_RATE_HE_NSS2_MCS8,
HALRF_DATA_RATE_HE_NSS2_MCS9,
HALRF_DATA_RATE_HE_NSS2_MCS10,
HALRF_DATA_RATE_HE_NSS2_MCS11,
HALRF_DATA_RATE_HE_NSS3_MCS0,
HALRF_DATA_RATE_HE_NSS3_MCS1,
HALRF_DATA_RATE_HE_NSS3_MCS2 = 110,
HALRF_DATA_RATE_HE_NSS3_MCS3,
HALRF_DATA_RATE_HE_NSS3_MCS4,
HALRF_DATA_RATE_HE_NSS3_MCS5,
HALRF_DATA_RATE_HE_NSS3_MCS6,
HALRF_DATA_RATE_HE_NSS3_MCS7,
HALRF_DATA_RATE_HE_NSS3_MCS8,
HALRF_DATA_RATE_HE_NSS3_MCS9,
HALRF_DATA_RATE_HE_NSS3_MCS10,
HALRF_DATA_RATE_HE_NSS3_MCS11,
HALRF_DATA_RATE_HE_NSS4_MCS0 = 120,
HALRF_DATA_RATE_HE_NSS4_MCS1,
HALRF_DATA_RATE_HE_NSS4_MCS2,
HALRF_DATA_RATE_HE_NSS4_MCS3,
HALRF_DATA_RATE_HE_NSS4_MCS4,
HALRF_DATA_RATE_HE_NSS4_MCS5,
HALRF_DATA_RATE_HE_NSS4_MCS6,
HALRF_DATA_RATE_HE_NSS4_MCS7,
HALRF_DATA_RATE_HE_NSS4_MCS8,
HALRF_DATA_RATE_HE_NSS4_MCS9,
HALRF_DATA_RATE_HE_NSS4_MCS10 = 130,
HALRF_DATA_RATE_HE_NSS4_MCS11,
HALRF_DATA_RATE_HEDCM_NSS1_MCS0,
HALRF_DATA_RATE_HEDCM_NSS1_MCS1,
HALRF_DATA_RATE_HEDCM_NSS1_MCS3,
HALRF_DATA_RATE_HEDCM_NSS1_MCS4,
HALRF_DATA_RATE_HEDCM_NSS2_MCS0,
HALRF_DATA_RATE_HEDCM_NSS2_MCS1,
HALRF_DATA_RATE_HEDCM_NSS2_MCS3,
HALRF_DATA_RATE_HEDCM_NSS2_MCS4,
HALRF_DATA_RATE_HEDCM_OFFSET = 140,
HALRF_DATA_RATE_VHT_OFFSET,
HALRF_DATA_RATE_HT_OFFSET,
HALRF_DATA_RATE_OFDM_OFFSET,
HALRF_DATA_RATE_CCK_OFFSET,
HALRF_DATA_RATE_MAX
};
struct halrf_pwr_info {
/*Power by Rate and Power Limit Switch*/
u8 pwr_table_switch_efuse;
u8 pwr_by_rate_switch;
u8 pwr_limit_switch;
bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_REGULATION_NUM];
u8 tx_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_REGULATION_NUM];
s8 tx_pwr_by_rate[TX_PWR_BY_RATE_NUM_BAND][HALRF_DATA_RATE_MAX];
s8 tx_pwr_limit_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_2G_BANDWITH_NUM]
[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
s8 tx_pwr_limit_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM]
[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
s8 tx_pwr_limit_ru_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
s8 tx_pwr_limit_ru_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
s8 tx_pwr_by_rate_mac[HW_PHY_MAX][TX_PWR_BY_RATE_NUM_MAC];
s8 tx_pwr_limit_mac[HW_PHY_MAX][TX_PWR_LIMIT_NUM_MAC];
s8 tx_pwr_limit_ru_mac[HW_PHY_MAX][TX_PWR_LIMIT_RU_NUM_MAC];
s16 tx_pwr_limit_ru26_mac[HW_PHY_MAX];
s16 tx_pwr_limit_ru52_mac[HW_PHY_MAX];
s16 tx_pwr_limit_ru106_mac[HW_PHY_MAX];
bool coex_pwr_ctl_enable;
bool dpk_pwr_ctl_enable;
s32 coex_pwr;
s32 dpk_pwr;
u8 mp_regulation;
u8 regulation_idx;
u8 regulation_str[10];
bool fix_power[MAX_HALRF_PATH];
s8 fix_power_dbm[MAX_HALRF_PATH];
bool set_tx_ptrn_shap_en;
u8 set_tx_ptrn_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX];
};
extern const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM];
#define pw_lmt_regu_type_str(lmt) ((lmt) < PW_LMT_MAX_REGULATION_NUM ? _pw_lmt_regu_type_str[(lmt)] : NULL)
extern const enum halrf_pw_lmt_regulation_type _regulation_to_pw_lmt_regu_type[REGULATION_MAX];
#define regulation_to_pw_lmt_regu_type(reg) ((reg) < REGULATION_MAX ? _regulation_to_pw_lmt_regu_type[(reg)] : PW_LMT_REGU_WW13)
extern const enum halrf_pw_lmt_regulation_type _tpo_to_pw_lmt_regu_type[TPO_NA];
#define tpo_to_pw_lmt_regu_type(reg) ((reg) < TPO_NA ? _tpo_to_pw_lmt_regu_type[(reg)] : PW_LMT_REGU_WW13)
u8 halrf_get_regulation_info(struct rf_info *rf, u8 band);
void halrf_power_by_rate_store_to_array(struct rf_info *rf,
u32 band, u32 tx_num, u32 rate_id, u32 data);
void halrf_power_limit_store_to_array(struct rf_info *rf,
u8 regulation, u8 band, u8 bandwidth, u8 rate,
u8 tx_num, u8 beamforming, u8 chnl, s8 val);
void halrf_power_limit_set_worldwide(struct rf_info *rf);
void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
u8 band, u8 bandwidth, u8 tx_num, u8 rate,
u8 regulation, u8 chnl, s8 val);
void halrf_power_limit_ru_set_worldwide(struct rf_info *rf);
u8 halrf_get_power_limit_extra(struct rf_info *rf);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_pwr_table.h
|
C
|
agpl-3.0
| 10,727
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_PWR_TRACK_H_
#define _HALRF_PWR_TRACK_H_
/*@--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM 8
#define MAX_RF_PATH 4
#define DELTA_SWINGIDX_SIZE 30
#define BAND_NUM 3
#define DELTA_SWINTSSI_SIZE 61
#define TSSI_EFUSE_RATE 2
#define TSSI_EFUSE_NUM 19
#define TSSI_HIDE_EFUSE_NUM 8
#define AVG_THERMAL_NUM_TSSI 2
#define MAX_CH_NUM 67
#define TSSI_ALIMK_VAULE_NUM 8
#define MAX_HALRF_PATH 2
/*@---------------------------End Define Parameters---------------------------*/
enum halrf_tssi_rate_type {
EFUSE_TSSI_CCK = 0,
EFUSE_TSSI_MCS
};
enum halrf_tssi_type{
TSSI_OFF = 0,
TSSI_ON,
TSSI_CAL
};
enum halrf_tssi_alimk_band{
TSSI_ALIMK_2G = 0,
TSSI_ALIMK_5GL,
TSSI_ALIMK_5GM,
TSSI_ALIMK_5GH,
TSSI_ALIMK_MAX
};
struct halrf_pwr_track_info {
/* u8 is_txpowertracking; */
u8 tx_powercount;
bool is_txpowertracking_init;
bool is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_path[MAX_RF_PATH];
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_avg_index_path[MAX_RF_PATH];
s8 power_index_offset_path[MAX_RF_PATH];
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
bool txpowertracking_in_progress;
bool is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset;
s8 delta_power_index;
s8 delta_power_index_path[MAX_RF_PATH];
s8 delta_power_index_last;
s8 delta_power_index_last_path[MAX_RF_PATH];
bool is_tx_power_changed;
/*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/
u8 delta_lck;
s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
u8 bb_swing_idx_ofdm_base;
u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
bool bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
bool bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
bool modify_tx_agc_flag_path_a;
bool modify_tx_agc_flag_path_b;
bool modify_tx_agc_flag_path_c;
bool modify_tx_agc_flag_path_d;
bool modify_tx_agc_flag_path_a_cck;
bool modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
struct halrf_tssi_info{
u8 thermal[MAX_HALRF_PATH];
u8 do_tssi_thermal[MAX_HALRF_PATH];
s32 tssi_de[MAX_HALRF_PATH];
u8 tssi_type;
s8 tssi_efuse[MAX_HALRF_PATH][TSSI_EFUSE_RATE][TSSI_EFUSE_NUM];
s8 tssi_trim[MAX_HALRF_PATH][TSSI_HIDE_EFUSE_NUM];
s32 tssi_xdbm;
s8 curr_tssi_cck_de[MAX_HALRF_PATH];
s8 curr_tssi_efuse_cck_de[MAX_HALRF_PATH];
s8 curr_tssi_ofdm_de[MAX_HALRF_PATH];
s8 curr_tssi_efuse_ofdm_de[MAX_HALRF_PATH];
s8 curr_tssi_trim_de[MAX_HALRF_PATH];
bool do_tssi;
bool base_thermal_check[MAX_HALRF_PATH];
u32 base_thermal[MAX_HALRF_PATH];
u32 tssi_stop_power[MAX_HALRF_PATH];
bool tssi_tracking_check[MAX_HALRF_PATH];
u8 ther_avg[MAX_HALRF_PATH][AVG_THERMAL_NUM_TSSI]; /*path*/
u8 ther_avg_idx[MAX_HALRF_PATH];
u8 ther_avg_fifo_idx[MAX_HALRF_PATH];
u32 ther_avg_final[MAX_HALRF_PATH];
s8 extra_ofst[MAX_HALRF_PATH];
/*bool normal_tssi_tracking;*/
u8 normal_tssi_tracking_times;
u8 default_txagc_offset_check;
u8 default_txagc_offset_times;
u32 default_txagc_offset[MAX_HALRF_PATH];
s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
s16 ref_pow_ofdm_offset;
u32 high_pwr_rst_cnt;
u8 cur_ch;
u8 cur_bw;
u32 backup_txagc_offset[MAX_HALRF_PATH][MAX_CH_NUM];
u8 backup_txagc_oft_ther[MAX_HALRF_PATH][MAX_CH_NUM];
bool check_backup_txagc[MAX_CH_NUM];
u32 start_time, finish_time;
u32 alignment_value[MAX_HALRF_PATH][TSSI_ALIMK_MAX][TSSI_ALIMK_VAULE_NUM];
bool alignment_done[MAX_HALRF_PATH][TSSI_ALIMK_MAX];
};
struct halrf_xtal_info{
s8 delta_swing_xtal_table_idx_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_xtal_table_idx_n[DELTA_SWINGIDX_SIZE];
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_pwr_track.h
|
C
|
agpl-3.0
| 7,734
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_STRUCT_H_
#define _HALRF_STRUCT_H_
struct hal_rf_t {
struct rtw_phl_com_t *phl_com;
struct rtw_hal_com_t *hal_com;
};
#endif /*_HALRF_STRUCT_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_struct.h
|
C
|
agpl-3.0
| 816
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALRF_TXGAPK_H_
#define _HALRF_TXGAPK_H_
#include "halrf_headers.h"
#define NUM 4
enum txgapk_id {
TXGAPK_TRACK = 0x00,
TXGAPK_PWR = 0x01,
TXGAPK_IQKBK = 0x02
};
struct halrf_gapk_info {
bool is_gapk_init;
u32 gapk_rf3f_bp[5][12][NUM]; /* band(2Gcck/2GOFDM/5GL/5GM/5GH)/idx/path */
bool gapk_bp_done;
s8 offset[12][NUM];
s8 fianl_offset[12][NUM];
u8 read_txgain;
bool is_gapk_enable;
u8 band[NUM];
u8 ch[NUM];
u8 bw[NUM];
s32 track_d[2][17];
s32 track_ta[2][17];
s32 power_d[2][17];
s32 power_ta[2][17];
bool is_txgapk_ok;
u32 r0x8010[2]; /* before and after txgapk */
u32 txgapk_chk_cnt[2][3][2]; /* path */ /* track pwr iqkbk*/ /* 0xbff8 0x80fc*/
/* u8 txgapk_mcc_ch[2][NUM]; */
/* u8 txgapk_table_idx[NUM]; */
u8 txgapk_mcc_ch[2]; /* channel */
u8 txgapk_table_idx;
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_txgapk.h
|
C
|
agpl-3.0
| 1,483
|
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_WPP_H__
#define __HALRF_WPP_H__
#define HALRF_WPP_CONTROL_GUIDS \
WPP_DEFINE_CONTROL_GUID( \
HalrfGuid, (C01A40AB,B69E,4CF6,BB09,4E0672EA2FC6), \
WPP_DEFINE_BIT(DBG_RF_TX_PWR_TRACK) \
WPP_DEFINE_BIT(DBG_RF_IQK) \
WPP_DEFINE_BIT(DBG_RF_LCK) \
WPP_DEFINE_BIT(DBG_RF_DPK) \
WPP_DEFINE_BIT(DBG_RF_TXGAPK) \
WPP_DEFINE_BIT(DBG_RF_DACK) \
WPP_DEFINE_BIT(DBG_RF_DPK_TRACK) \
WPP_DEFINE_BIT(DBG_RF_RXDCK) \
WPP_DEFINE_BIT(DBG_RF_RFK) \
WPP_DEFINE_BIT(DBG_RF_INIT) \
WPP_DEFINE_BIT(DBG_RF_POWER) \
WPP_DEFINE_BIT(DBG_RF_RXGAINK) \
WPP_DEFINE_BIT(DBG_RF_THER_TRIM) \
WPP_DEFINE_BIT(DBG_RF_PABIAS_TRIM) \
WPP_DEFINE_BIT(DBG_RF_TSSI_TRIM) \
WPP_DEFINE_BIT(DBG_RF_FW) \
WPP_DEFINE_BIT(DBG_RF_MP) \
WPP_DEFINE_BIT(DBG_RF_TMP) \
WPP_DEFINE_BIT(DBG_RF_PSD) \
)
#endif /* __HALRF_WPP_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/halrf_wpp.h
|
C
|
agpl-3.0
| 1,802
|
# All needed files would be added to _HAL_INTFS_FILES, and it would include
# hal_g6/phy/rf and all related files in directory hal_g6/phy/rf/.
# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC
# (CONFIG_RTL*) setting are all ready!
HAL = hal_g6
ifeq ($(CONFIG_PHL_ARCH), y)
phl_path := phl/hal_g6
phl_path_d1 := $(src)/phl/$(HAL)
else
phl_path := hal_g6
phl_path_d1 := $(src)/$(HAL)
endif
# Base directory
path_halrf_d1 := $(phl_path)/phy/rf
halrf-y += $(path_halrf_d1)/halrf.o \
$(path_halrf_d1)/halrf_pmac.o \
$(path_halrf_d1)/halrf_api.o \
$(path_halrf_d1)/halrf_dbg.o \
$(path_halrf_d1)/halrf_dbg_cmd.o \
$(path_halrf_d1)/halrf_ex.o \
$(path_halrf_d1)/halrf_hw_cfg.o \
$(path_halrf_d1)/halrf_init.o \
$(path_halrf_d1)/halrf_interface.o \
$(path_halrf_d1)/halrf_pwr_table.o \
$(path_halrf_d1)/halrf_iqk.o \
ifeq ($(CONFIG_RTL8852A), y)
ic := 8852a
# Level 2 directory
path_halrf_8852a := $(path_halrf_d1)/halrf_$(ic)
halrf-y += $(path_halrf_8852a)/halrf_8852a.o \
$(path_halrf_8852a)/halrf_8852a_api.o \
$(path_halrf_8852a)/halrf_hwimg_8852a.o\
$(path_halrf_8852a)/halrf_txgapk_8852a.o\
$(path_halrf_8852a)/halrf_iqk_8852a.o\
$(path_halrf_8852a)/halrf_reg_cfg_8852a.o\
$(path_halrf_8852a)/halrf_dpk_8852a.o\
$(path_halrf_8852a)/halrf_dack_8852a.o\
$(path_halrf_8852a)/halrf_set_pwr_table_8852a.o\
$(path_halrf_8852a)/halrf_efuse_8852a.o\
$(path_halrf_8852a)/halrf_tssi_8852a.o\
$(path_halrf_8852a)/halrf_kfree_8852a.o\
$(path_halrf_8852a)/halrf_psd_8852a.o
endif
ifeq ($(CONFIG_RTL8852B), y)
ic := 8852b
# Level 2 directory
path_halrf_8852b := $(path_halrf_d1)/halrf_$(ic)
halrf-y += $(path_halrf_8852b)/halrf_8852b.o\
$(path_halrf_8852b)/halrf_8852b_api.o \
$(path_halrf_8852b)/halrf_hwimg_8852b.o\
$(path_halrf_8852b)/halrf_txgapk_8852b.o\
$(path_halrf_8852b)/halrf_iqk_8852b.o\
$(path_halrf_8852b)/halrf_reg_cfg_8852b.o\
$(path_halrf_8852b)/halrf_dack_8852b.o \
$(path_halrf_8852b)/halrf_dpk_8852b.o \
$(path_halrf_8852b)/halrf_set_pwr_table_8852b.o\
$(path_halrf_8852b)/halrf_efuse_8852b.o\
$(path_halrf_8852b)/halrf_tssi_8852b.o\
$(path_halrf_8852b)/halrf_kfree_8852b.o\
$(path_halrf_8852b)/halrf_psd_8852b.o
endif
ifeq ($(CONFIG_RTL8852C), y)
ic := 8852c
# Level 2 directory
path_halrf_8852c := $(path_halrf_d1)/halrf_$(ic)
halrf-y += $(path_halrf_8852c)/halrf_8852c.o \
// $(path_halrf_8852a)/halrf_8852c_api.o \
// $(path_halrf_8852a)/halrf_hwimg_8852c.o\
// $(path_halrf_8852a)/halrf_txgapk_8852c.o\
// $(path_halrf_8852a)/halrf_iqk_8852c.o\
// $(path_halrf_8852a)/halrf_reg_cfg_8852c.o\
// $(path_halrf_8852a)/halrf_dpk_8852c.o\
// $(path_halrf_8852a)/halrf_dack_8852c.o\
// $(path_halrf_8852a)/halrf_set_pwr_table_8852c.o\
// $(path_halrf_8852a)/halrf_efuse_8852c.o\
// $(path_halrf_8852a)/halrf_tssi_8852c.o\
// $(path_halrf_8852a)/halrf_kfree_8852c.o\
// $(path_halrf_8852a)/halrf_psd_8852c.o
endif
_HAL_RF_FILES += $(halrf-y)
|
2301_81045437/rtl8852be
|
phl/hal_g6/phy/rf/rf.mk
|
Makefile
|
agpl-3.0
| 3,005
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TRX_8852B_C_
#include "../hal_headers.h"
#include "rtl8852b_hal.h"
static void _hal_trx_8852b_dump_rxcnt(struct hal_ppdu_sts *ppdu_sts)
{
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "ppdu_sts->rx_cnt_size = 0x%x\n", ppdu_sts->rx_cnt_size);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_OFDM_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_OFDM_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_OFDM_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_OFDM_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_OFDM_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_OFDM_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_CCK_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_CCK_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_CCK_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_CCK_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_CCK_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_CCK_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_PPDU = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_PPDU]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HT_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HT_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_PPDU = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_PPDU]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTSU_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTSU_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_PPDU = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_PPDU]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_VHTMU_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_VHTMU_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_PPDU = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_PPDU]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HESU_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HESU_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_PPDU = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_PPDU]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HEMU_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HEMU_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_OK = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_OK]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_FAIL = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_FAIL]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_PPDU = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_PPDU]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_HETB_FAM = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_HETB_FAM]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_FULLDRP = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_FULLDRP]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_FULLDRP_PKT = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_FULLDRP_PKT]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_PKTFLTR_DRP = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_PKTFLTR_DRP]);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_, "HAL_RXCNT_RXDMA = 0x%x\n",
ppdu_sts->rx_cnt.ppdu_cnt[HAL_RXCNT_RXDMA]);
}
static void _hal_dump_rxdesc(u8 *buf, struct rtw_r_meta_data *mdata)
{
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "%s ==>\n", __FUNCTION__);
debug_dump_data(buf, 56, "_hal_dump_rxdesc:: ");
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pktlen = 0x%X\n", mdata->pktlen);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->shift = 0x%X\n", mdata->shift);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->wl_hd_iv_len = 0x%X\n",
mdata->wl_hd_iv_len);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bb_sel = 0x%X\n",
mdata->bb_sel);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->mac_info_vld = 0x%X\n",
mdata->mac_info_vld);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rpkt_type = 0x%X\n",
mdata->rpkt_type);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->drv_info_size = 0x%X\n",
mdata->drv_info_size);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->long_rxd = 0x%X\n",
mdata->long_rxd);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ppdu_type = 0x%X\n",
mdata->ppdu_type);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ppdu_cnt = 0x%X\n",
mdata->ppdu_cnt);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sr_en = 0x%X\n",
mdata->sr_en);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->user_id = 0x%X\n",
mdata->user_id);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_rate = 0x%X\n",
mdata->rx_rate);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_gi_ltf = 0x%X\n",
mdata->rx_gi_ltf);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->non_srg_ppdu = 0x%X\n",
mdata->non_srg_ppdu);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->inter_ppdu = 0x%X\n",
mdata->inter_ppdu);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bw = 0x%X\n",
mdata->bw );
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->freerun_cnt = 0x%X\n",
mdata->freerun_cnt);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->a1_match = 0x%X\n",
mdata->a1_match);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sw_dec = 0x%X\n",
mdata->sw_dec);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->hw_dec = 0x%X\n",
mdata->hw_dec);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ampdu = 0x%X\n",
mdata->ampdu);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->ampdu_end_pkt = 0x%X\n",
mdata->ampdu_end_pkt);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->amsdu = 0x%X\n",
mdata->amsdu);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->amsdu_cut = 0x%X\n",
mdata->amsdu_cut);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->last_msdu = 0x%X\n",
mdata->last_msdu);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bypass = 0x%X\n",
mdata->bypass);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->crc32 = 0x%X\n",
mdata->crc32);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->icverr = 0x%X\n",
mdata->icverr);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->magic_wake = 0x%X\n",
mdata->magic_wake);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->unicast_wake = 0x%X\n",
mdata->unicast_wake);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pattern_wake = 0x%X\n",
mdata->pattern_wake);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->get_ch_info = 0x%X \n",
mdata->get_ch_info);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_statistics = 0x%X",
mdata->rx_statistics);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pattern_idx = 0x%X",
mdata->pattern_idx);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->target_idc = 0x%X",
mdata->target_idc);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->chksum_ofld_en = 0x%X",
mdata->chksum_ofld_en);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->with_llc = 0x%X",
mdata->with_llc);
if (mdata->long_rxd == 1) {
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->frame_type = 0x%X",
mdata->frame_type);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->mc = 0x%X",
mdata->mc);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->bc = 0x%X",
mdata->bc);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->more_data = 0x%X",
mdata->more_data);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->more_frag = 0x%X",
mdata->more_frag);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->pwr_bit = 0x%X",
mdata->pwr_bit);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->qos = 0x%X",
mdata->qos);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->tid = 0x%X",
mdata->tid);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->eosp = 0x%X",
mdata->eosp);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->htc = 0x%X",
mdata->htc);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->q_null = 0x%X",
mdata->q_null);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->seq = 0x%X",
mdata->seq);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->frag_num = 0x%X",
mdata->frag_num);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->sec_cam_idx = 0x%X",
mdata->sec_cam_idx);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_cam = 0x%X",
mdata->addr_cam);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->macid = 0x%X\n",
mdata->macid);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_pl_id = 0x%X",
mdata->rx_pl_id);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_cam_vld = 0x%X",
mdata->addr_cam_vld);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->addr_fwd_en = 0x%X",
mdata->addr_fwd_en);
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "mdata->rx_pl_match = 0x%X",
mdata->rx_pl_match);
debug_dump_data(mdata->mac_addr, 6, "mdata->mac_addr = \n");
}
}
static enum rtw_hal_status
hal_handle_chaninfo_8852b(struct hal_info_t *hal)
{
return RTW_HAL_STATUS_SUCCESS;
}
/**
* SW Parsing Rx Desc - hal_parsing_rx_wd_8852b
* description:
* Parsing Rx WiFi Desc by Halmac or SW Manually
* input:
* hal : hal ic adapter
* desc : pointer of the start of rx desc
* output:
* pkt : pointer of the start of pkt;
* pkt_len : the pkt length
* rxwd : rx desc
*/
static enum rtw_hal_status
_hal_parsing_rx_wd_8852b(struct hal_info_t *hal, u8 *desc,
struct rtw_r_meta_data *mdata)
{
/* ToDo: Parse word by word with byte swap once for
* each word
*/
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal->hal_com;
mdata->pktlen = GET_RX_AX_DESC_PKT_LEN_8852B(desc);
mdata->shift = GET_RX_AX_DESC_SHIFT_8852B(desc);
mdata->bb_sel = GET_RX_AX_DESC_BB_SEL_8852B(desc);
mdata->mac_info_vld = GET_RX_AX_DESC_MAC_INFO_VLD_8852B(desc);
mdata->rpkt_type = GET_RX_AX_DESC_RPKT_TYPE_8852B(desc);
mdata->drv_info_size = GET_RX_AX_DESC_DRV_INFO_SIZE_8852B(desc);
mdata->long_rxd = GET_RX_AX_DESC_LONG_RXD_8852B(desc);
if ( (mdata->rpkt_type == RX_8852B_DESC_PKT_T_WIFI)
|| (mdata->rpkt_type == RX_8852B_DESC_PKT_T_PPDU_STATUS)) {
mdata->wl_hd_iv_len = GET_RX_AX_DESC_HDR_IV_L_8852B(desc);
mdata->ppdu_type = GET_RX_AX_DESC_PPDU_TYPE_8852B(desc);
mdata->ppdu_cnt = GET_RX_AX_DESC_PPDU_CNT_8852B(desc);
mdata->sr_en = GET_RX_AX_DESC_SR_EN_8852B(desc);
mdata->user_id = GET_RX_AX_DESC_USER_ID_8852B(desc);
mdata->rx_rate = GET_RX_AX_DESC_RX_DATARATE_8852B(desc);
mdata->rx_gi_ltf = GET_RX_AX_DESC_RX_GI_LTF_8852B(desc);
mdata->non_srg_ppdu = GET_RX_AX_DESC_NON_SRG_PPDU_8852B(desc);
mdata->inter_ppdu = GET_RX_AX_DESC_INTER_PPDU_8852B(desc);
mdata->bw = GET_RX_AX_DESC_BW_8852B(desc);
mdata->freerun_cnt = GET_RX_AX_DESC_FREERUN_CNT_8852B(desc);
mdata->a1_match = GET_RX_AX_DESC_A1_MATCH_8852B(desc);
mdata->sw_dec = GET_RX_AX_DESC_SW_DEC_8852B(desc);
mdata->hw_dec = GET_RX_AX_DESC_HW_DEC_8852B(desc);
mdata->ampdu = GET_RX_AX_DESC_AMPDU_8852B(desc);
mdata->ampdu_end_pkt = GET_RX_AX_DESC_AMPDU_EDN_PKT_8852B(desc);
mdata->amsdu = GET_RX_AX_DESC_AMSDU_8852B(desc);
mdata->amsdu_cut = GET_RX_AX_DESC_AMSDU_CUT_8852B(desc);
mdata->last_msdu = GET_RX_AX_DESC_LAST_MSDU_8852B(desc);
mdata->bypass = GET_RX_AX_DESC_BYPASS_8852B(desc);
mdata->crc32 = GET_RX_AX_DESC_CRC32_8852B(desc);
mdata->icverr = GET_RX_AX_DESC_ICVERR_8852B(desc);
mdata->magic_wake = GET_RX_AX_DESC_MAGIC_WAKE_8852B(desc);
mdata->unicast_wake = GET_RX_AX_DESC_UNICAST_WAKE_8852B(desc);
mdata->pattern_wake = GET_RX_AX_DESC_PATTERN_WAKE_8852B(desc);
mdata->get_ch_info = GET_RX_AX_DESC_CH_INFO_8852B(desc);
mdata->rx_statistics = GET_RX_AX_DESC_STATISTICS_8852B(desc);
mdata->pattern_idx = GET_RX_AX_DESC_PATTERN_IDX_8852B(desc);
mdata->target_idc = GET_RX_AX_DESC_TARGET_IDC_8852B(desc);
mdata->chksum_ofld_en = GET_RX_AX_DESC_CHKSUM_OFFLOAD_8852B(desc);
mdata->with_llc = GET_RX_AX_DESC_WITH_LLC_8852B(desc);
if (mdata->long_rxd == 1) {
mdata->frame_type = GET_RX_AX_DESC_TYPE_8852B(desc);
mdata->mc = GET_RX_AX_DESC_MC_8852B(desc);
mdata->bc = GET_RX_AX_DESC_BC_8852B(desc);
mdata->more_data = GET_RX_AX_DESC_MD_8852B(desc);
mdata->more_frag = GET_RX_AX_DESC_MF_8852B(desc);
mdata->pwr_bit = GET_RX_AX_DESC_PWR_8852B(desc);
mdata->qos = GET_RX_AX_DESC_QOS_8852B(desc);
mdata->tid = GET_RX_AX_DESC_TID_8852B(desc);
mdata->eosp = GET_RX_AX_DESC_EOSP_8852B(desc);
mdata->htc = GET_RX_AX_DESC_HTC_8852B(desc);
mdata->q_null = GET_RX_AX_DESC_QNULL_8852B(desc);
mdata->seq = GET_RX_AX_DESC_SEQ_8852B(desc);
mdata->frag_num = GET_RX_AX_DESC_FRAG_8852B(desc);
mdata->sec_cam_idx = GET_RX_AX_DESC_CAM_IDX_8852B(desc);
mdata->addr_cam = GET_RX_AX_DESC_ADDR_CAM_8852B(desc);
mdata->addr_cam_vld = GET_RX_AX_DESC_CAM_VLD_8852B(desc);
if (mdata->addr_cam_vld == 0)
mdata->macid = 0xFF;
else
mdata->macid = GET_RX_AX_DESC_MACID_8852B(desc);
mdata->rx_pl_id = GET_RX_AX_DESC_PL_ID_8852B(desc);
mdata->addr_fwd_en = GET_RX_AX_DESC_FWD_EN_8852B(desc);
mdata->rx_pl_match = GET_RX_AX_DESC_PL_MATCH_8852B(desc);
_os_mem_cpy(hal_com->drv_priv,
(void*)&mdata->mac_addr, (void*)(desc + 24), MAC_ALEN);
mdata->sec_type = GET_RX_AX_DESC_SEC_TYPE_8852B(desc);
}
}
if(mdata->pktlen == 0)
hstatus = RTW_HAL_STATUS_FAILURE;
else
hstatus = RTW_HAL_STATUS_SUCCESS;
return hstatus;
}
/**
* hal_parsing_rx_wd_8852b
* description:
* Parsing Rx WiFi Desc by Halmac or SW Manually
* input:
* hal : hal ic adapter
* desc : pointer of the start of rx desc
* output:
* pkt : pointer of the start of pkt;
* pkt_len : the pkt length
* rxwd : rx desc
*/
enum rtw_hal_status
hal_parsing_rx_wd_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
u8 *buf, u8 **pkt, u16 *pkt_len,
struct rtw_r_meta_data *mdata)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
u8 halmac_rx = 0;
u8 shift = 0;
u8 *desc = NULL;
u8 desc_l = 0;
do {
if (NULL == buf)
break;
if (phl_com->hci_type == RTW_HCI_PCIE)
desc = buf + RX_BD_INFO_SIZE;
else
desc = buf;
if (!halmac_rx) {
hstatus = _hal_parsing_rx_wd_8852b(hal, desc, mdata);
} else {
/* halmac_ax_ops->parse_rxdesc( */
/* hm_info->halmac_ax_apter, */
/* rxpkt_info, */
/* buf, */
/* len); */
}
if (RTW_HAL_STATUS_SUCCESS != hstatus)
break;
/* TODO :: Need Double Check*/
desc_l = mdata->long_rxd ? RX_DESC_L_SIZE_8852B :
RX_DESC_S_SIZE_8852B;
shift = (u8)(mdata->shift * 2 + mdata->drv_info_size * 8 + desc_l);
if ((1 == mdata->mac_info_vld) &&
(RX_8852B_DESC_PKT_T_PPDU_STATUS != mdata->rpkt_type))
*pkt = desc + shift + RX_PPDU_MAC_INFO_SIZE_8852B;
else
*pkt = desc + shift;
*pkt_len = (u16)mdata->pktlen;
} while (false);
//_hal_dump_rxdesc(desc, mdata);
return hstatus;
}
static void
_hal_rx_wlanhdr_check_8852b(void *drvpriv, void *hdr, struct rtw_r_meta_data *mdata)
{
/*Check Retry BIT*/
u8 retry = 0;
u16 seq_num = 0;
u8 type = 0;
type = PHL_GET_80211_HDR_TYPE(hdr);
retry = PHL_GET_80211_HDR_RETRY(hdr);
seq_num = PHL_GET_80211_HDR_SEQUENCE(hdr);
PHL_GET_80211_HDR_ADDRESS2(drvpriv, hdr, mdata->ta);
if (retry) {
PHL_TRACE(COMP_PHL_RECV, _PHL_DEBUG_, "[TP Debug] RETRY PKT!!!! seq_num = %d \n", seq_num);
}
if (type == 9) { /* trigger */
PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_, "rx trigger\n");
PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_,
"addr cam hit=%d\n", mdata->addr_cam_vld);
PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_,
"addr cam idx=%d\n", mdata->addr_cam);
PHL_TRACE(COMP_PHL_TRIG, _PHL_DEBUG_,
"macid = %d\n", mdata->macid);
}
}
static void
_hal_rx_sts_8852b(struct hal_info_t *hal, struct rtw_r_meta_data *meta)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
struct rtw_trx_stat *trx_stat = &hal_com->trx_stat;
/* todo: shall drop rx in PHL if hw err */
if (meta->crc32 || meta->icverr)
trx_stat->rx_err_cnt++;
else
trx_stat->rx_ok_cnt++;
}
enum rtw_hal_status
hal_handle_rx_buffer_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
u8 *buf, u32 buf_len,
struct rtw_phl_rx_pkt *phl_rx)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
void *drv = hal_to_drvpriv(hal);
struct rtw_recv_pkt *r = &phl_rx->r;
struct rtw_pkt_buf_list *pkt = &r->pkt_list[0];
struct rtw_r_meta_data *mdata = &r->mdata;
#ifdef CONFIG_PHL_TEST_SUITE
struct test_bp_info bp_info;
#endif
hstatus = hal_parsing_rx_wd_8852b(phl_com, hal, buf,
&pkt->vir_addr, &pkt->length, mdata);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
return hstatus;
if( (pkt->vir_addr + pkt->length) > (buf + buf_len) )
return RTW_HAL_STATUS_FAILURE;
/* hana_todo */
r->pkt_cnt = 1;
switch (mdata->rpkt_type) {
case RX_8852B_DESC_PKT_T_WIFI :
{
phl_rx->type = RTW_RX_TYPE_WIFI;
_hal_rx_wlanhdr_check_8852b(drv, pkt->vir_addr, mdata);
_hal_rx_sts_8852b(hal, mdata);
hal_rx_ppdu_sts_normal_data(phl_com, pkt->vir_addr, mdata);
}
break;
case RX_8852B_DESC_PKT_T_TX_PD_RELEASE_HOST :
{
phl_rx->type = RTW_RX_TYPE_TX_WP_RELEASE_HOST;
}
break;
case RX_8852B_DESC_PKT_T_PPDU_STATUS :
{
struct hal_ppdu_sts ppdu_sts = {0};
u8 is_su = 1;
phl_rx->type = RTW_RX_TYPE_PPDU_STATUS;
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"==> RX_8852B_DESC_PKT_T_PPDU_STATUS :band %d ; ppdu_cnt %d ; freerun_cnt %d \n",
mdata->bb_sel, mdata->ppdu_cnt, mdata->freerun_cnt);
rtw_hal_mac_ax_parse_ppdu_sts(hal, mdata->mac_info_vld,
pkt->vir_addr, mdata->pktlen,
(void *)&ppdu_sts,
(void *)mdata);
if (ppdu_sts.rx_cnt_size != 0) {
_hal_trx_8852b_dump_rxcnt(&ppdu_sts);
}
if (ppdu_sts.phy_st_size != 0) {
if((mdata->ppdu_type == RX_8852B_DESC_PPDU_T_VHT_MU)||
(mdata->ppdu_type == RX_8852B_DESC_PPDU_T_HE_MU)||
(mdata->ppdu_type == RX_8852B_DESC_PPDU_T_HE_TB)) {
is_su = 0;
}
rtw_hal_bb_parse_phy_sts(hal, (void *)&ppdu_sts,
phl_rx, is_su);
hal_rx_ppdu_sts(phl_com, phl_rx, &ppdu_sts);
#ifdef CONFIG_PHL_TEST_SUITE
bp_info.type = BP_INFO_TYPE_MP_RX_PHYSTS;
bp_info.ptr = (void *)(ppdu_sts.phy_st_ptr);
bp_info.len = ppdu_sts.phy_st_size;
rtw_phl_test_setup_bp(phl_com, &bp_info, TEST_SUB_MODULE_MP);
#endif
}
}
break;
case RX_8852B_DESC_PKT_T_DFS_RPT :
{
#ifdef CONFIG_PHL_DFS
struct mac_ax_dfs_rpt dfs_rpt = {0};
struct hal_dfs_rpt hal_dfs = {0};
phl_rx->type = RTW_RX_TYPE_DFS_RPT;
rtw_hal_mac_parse_dfs(hal,pkt->vir_addr, mdata->pktlen, &dfs_rpt);
#ifdef DBG_PHL_DFS
PHL_INFO("RX DFS RPT, pkt_len:%d\n", mdata->pktlen);
PHL_INFO("[DFS] mac-hdr dfs_num:%d\n", dfs_rpt.dfs_num);
PHL_INFO("[DFS] mac-hdr drop_num:%d\n", dfs_rpt.drop_num);
PHL_INFO("[DFS] mac-hdr max_cont_drop:%d\n", dfs_rpt.max_cont_drop);
PHL_INFO("[DFS] mac-hdr total_drop:%d\n", dfs_rpt.total_drop);
#endif
hal_dfs.dfs_ptr = dfs_rpt.dfs_ptr;
hal_dfs.dfs_num = dfs_rpt.dfs_num;
hal_dfs.phy_idx = 0;
if (rtw_hal_bb_radar_detect(hal, &hal_dfs))
PHL_INFO("[DFS] radar detected\n");
#endif
}
break;
case RX_8852B_DESC_PKT_T_CHANNEL_INFO :
{
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status status= RTW_HAL_STATUS_SUCCESS;
u8* buf_addr;
struct ch_rpt_hdr_info ch_hdr_rpt = {0};
struct phy_info_rpt phy_rpt = {0};
struct ch_info_drv_rpt drv_rpt = {0};
u32 idle_num = CHAN_INFO_PKT_TOTAL;
struct chan_info_t *chan_info_old = NULL;
phl_rx->type = RTW_RX_TYPE_CHANNEL_INFO;
/* Channel Report */
/* TODO: need to discuss the final csi header format further.*/
idle_num = rtw_phl_get_chaninfo_idle_number(drv, phl_com);
if (idle_num == CHAN_INFO_PKT_TOTAL)
phl_com->chan_info = rtw_phl_query_idle_chaninfo(drv, phl_com);
if (phl_com->chan_info == NULL) {
/*hstatus = RTW_HAL_STATUS_SUCCESS is expected*/
PHL_INFO("channel info packet not avaialbe due to no pakcet handle\n");
break;
}
buf_addr = phl_com->chan_info->chan_info_buffer;
status = rtw_hal_bb_ch_info_parsing(hal, pkt->vir_addr,
mdata->pktlen,
buf_addr + phl_com->chan_info->length,
&ch_hdr_rpt, &phy_rpt, &drv_rpt);
if (status == RTW_HAL_STATUS_FAILURE)
phl_com->chan_info->length = 0;
else
phl_com->chan_info->length += drv_rpt.raw_data_len;
/* store phy info if seg#0 is success*/
if (drv_rpt.seg_idx_curr == 0 && status != RTW_HAL_STATUS_FAILURE)
_hal_fill_csi_header_phy_info(hal, &(phl_com->chan_info->csi_header),
&ch_hdr_rpt, &phy_rpt);
if (status == RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG) {
/* Fill remain csi header to buffer */
_hal_fill_csi_header_remain(hal,
&(phl_com->chan_info->csi_header), mdata);
/* push compelete channel info resourecs to busy queue */
chan_info_old = rtw_phl_recycle_busy_chaninfo(drv, phl_com, phl_com->chan_info);
if (chan_info_old)
rtw_phl_enqueue_idle_chaninfo(drv, phl_com, chan_info_old);
phl_com->chan_info = rtw_phl_query_idle_chaninfo(drv, phl_com);
if(phl_com->chan_info == NULL)
PHL_INFO("channel info packet not avaialbe after recycle\n");
}
#else
phl_rx->type = RTW_RX_TYPE_CHANNEL_INFO;
#endif /* CONFIG_PHL_CHANNEL_INFO */
}
break;
case RX_8852B_DESC_PKT_T_F2P_TX_CMD_RPT :
{
/* DL MU Report ; UL OFDMA Trigger Report */
}
break;
case RX_8852B_DESC_PKT_T_C2H :
{
struct rtw_c2h_info c = {0};
phl_rx->type = RTW_RX_TYPE_C2H;
rtw_hal_mac_parse_c2h(hal, pkt->vir_addr, mdata->pktlen, (void *)&c);
hal_c2h_post_process(phl_com, hal, (void *)&c);
}
break;
case RX_8852B_DESC_PKT_T_TX_RPT:
{
u8 expected_pkt_num = 0;
u8 diff_pkt_num = 0;
u8 tx_pkt_num = 0;
phl_rx->type = RTW_RX_TYPE_TX_RPT;
/*
* Write CR 0xC660[3:2] = 0, Dump TXRPT to driver
* TXRPT offset12[7:0]: PTCL expected_pkt_num
* TXRPT offset16[27:24]: diff_pkt_num
*/
expected_pkt_num = pkt->vir_addr[12];
diff_pkt_num = (pkt->vir_addr[19] & 0xF);
tx_pkt_num = expected_pkt_num - diff_pkt_num;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,
"expected_pkt_num: %d, diff_pkt_num: %d, tx_pkt_num: %d\n",
expected_pkt_num, diff_pkt_num, tx_pkt_num);
}
break;
default:
break;
}
return hstatus;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/hal_trx_8852b.c
|
C
|
agpl-3.0
| 23,740
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_TRX_8852B_H_
#define _HAL_TRX_8852B_H_
/* wifi packet(RXD.RPKT_TYPE = 0x0) = 32 bytes, otherwise 16 bytes */
#define RX_DESC_L_SIZE_8852B 32
#define RX_DESC_S_SIZE_8852B 16
#define RX_BD_INFO_SIZE 4
#define RX_PPDU_MAC_INFO_SIZE_8852B 4
#define ACH0_QUEUE_IDX_8852B 0x0
#define ACH1_QUEUE_IDX_8852B 0x1
#define ACH2_QUEUE_IDX_8852B 0x2
#define ACH3_QUEUE_IDX_8852B 0x3
#define ACH4_QUEUE_IDX_8852B 0x4
#define ACH5_QUEUE_IDX_8852B 0x5
#define ACH6_QUEUE_IDX_8852B 0x6
#define ACH7_QUEUE_IDX_8852B 0x7
#define MGQ_B0_QUEUE_IDX_8852B 0x8
#define HIQ_B0_QUEUE_IDX_8852B 0x9
#define FWCMD_QUEUE_IDX_8852B 0xc
/* AX RX DESC */
/* DWORD 0 ; Offset 00h */
#define GET_RX_AX_DESC_PKT_LEN_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
#define GET_RX_AX_DESC_SHIFT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 2)
#define GET_RX_AX_DESC_HDR_IV_L_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 6)
#define GET_RX_AX_DESC_BB_SEL_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 22, 1)
#define GET_RX_AX_DESC_MAC_INFO_VLD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1)
#define GET_RX_AX_DESC_RPKT_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 4)
#define GET_RX_AX_DESC_DRV_INFO_SIZE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 3)
#define GET_RX_AX_DESC_LONG_RXD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
/* DWORD 1 ; Offset 04h */
#define GET_RX_AX_DESC_PPDU_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 4)
#define GET_RX_AX_DESC_PPDU_CNT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 4, 3)
#define GET_RX_AX_DESC_SR_EN_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)
#define GET_RX_AX_DESC_USER_ID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 8)
#define GET_RX_AX_DESC_RX_DATARATE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 9)
#define GET_RX_AX_DESC_RX_GI_LTF_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 3)
#define GET_RX_AX_DESC_NON_SRG_PPDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 1)
#define GET_RX_AX_DESC_INTER_PPDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 29, 1)
#define GET_RX_AX_DESC_BW_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 2)
/* DWORD 2 ; Offset 08h */
#define GET_RX_AX_DESC_FREERUN_CNT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 32)
/* DWORD 3 ; Offset 0ch */
#define GET_RX_AX_DESC_A1_MATCH_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 1)
#define GET_RX_AX_DESC_SW_DEC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 1, 1)
#define GET_RX_AX_DESC_HW_DEC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 2, 1)
#define GET_RX_AX_DESC_AMPDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 3, 1)
#define GET_RX_AX_DESC_AMPDU_EDN_PKT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 4, 1)
#define GET_RX_AX_DESC_AMSDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 5, 1)
#define GET_RX_AX_DESC_AMSDU_CUT_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 6, 1)
#define GET_RX_AX_DESC_LAST_MSDU_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 1)
#define GET_RX_AX_DESC_BYPASS_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 8, 1)
#define GET_RX_AX_DESC_CRC32_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 9, 1)
#define GET_RX_AX_DESC_ICVERR_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
#define GET_RX_AX_DESC_MAGIC_WAKE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
#define GET_RX_AX_DESC_UNICAST_WAKE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 1)
#define GET_RX_AX_DESC_PATTERN_WAKE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 13, 1)
#define GET_RX_AX_DESC_CH_INFO_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 14, 1)
#define GET_RX_AX_DESC_STATISTICS_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 15, 1)
#define GET_RX_AX_DESC_PATTERN_IDX_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 5)
#define GET_RX_AX_DESC_TARGET_IDC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 21, 3)
#define GET_RX_AX_DESC_CHKSUM_OFFLOAD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 24, 1)
#define GET_RX_AX_DESC_WITH_LLC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 25, 1)
/* DWORD 4 ; Offset 10h */
#define GET_RX_AX_DESC_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 2)
#define GET_RX_AX_DESC_MC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 2, 1)
#define GET_RX_AX_DESC_BC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 3, 1)
#define GET_RX_AX_DESC_MD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 4, 1)
#define GET_RX_AX_DESC_MF_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 5, 1)
#define GET_RX_AX_DESC_PWR_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 6, 1)
#define GET_RX_AX_DESC_QOS_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 7, 1)
#define GET_RX_AX_DESC_TID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 4)
#define GET_RX_AX_DESC_EOSP_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 12, 1)
#define GET_RX_AX_DESC_HTC_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 13, 1)
#define GET_RX_AX_DESC_QNULL_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 14, 1)
#define GET_RX_AX_DESC_SEQ_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 12)
#define GET_RX_AX_DESC_FRAG_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 28, 4)
/* DWORD 5 ; Offset 14h */
#define GET_RX_AX_DESC_CAM_IDX_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 8)
#define GET_RX_AX_DESC_ADDR_CAM_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 8, 8)
#define GET_RX_AX_DESC_MACID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 16, 8)
#define GET_RX_AX_DESC_PL_ID_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 24, 4)
#define GET_RX_AX_DESC_CAM_VLD_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 28, 1)
#define GET_RX_AX_DESC_FWD_EN_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 29, 1)
#define GET_RX_AX_DESC_PL_MATCH_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 30, 1)
/* DWORD 6 ; Offset 18h */
//#define GET_RX_AX_DESC_MAC_ADDR_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+24, 0, 32)
/* DWORD 7 ; Offset 1ch */
//#define GET_RX_AX_DESC_MAC_ADDR_H_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+28, 0, 16)
#define GET_RX_AX_DESC_SEC_TYPE_8852B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+28, 17, 4)
/*
0000: WIFI packet
0001: PPDU status
0010: channel info
0011: BB scope mode
0100: F2P TX CMD report
0101: SS2FW report
0110: TX report
0111: TX payload release to host
1000: DFS report
1001: TX payload release to WLCPU
1010: C2H packet */
#define RX_8852B_DESC_PKT_T_WIFI 0
#define RX_8852B_DESC_PKT_T_PPDU_STATUS 1
#define RX_8852B_DESC_PKT_T_CHANNEL_INFO 2
#define RX_8852B_DESC_PKT_T_BB_SCOPE 3
#define RX_8852B_DESC_PKT_T_F2P_TX_CMD_RPT 4
#define RX_8852B_DESC_PKT_T_SS2FW_RPT 5
#define RX_8852B_DESC_PKT_T_TX_RPT 6
#define RX_8852B_DESC_PKT_T_TX_PD_RELEASE_HOST 7
#define RX_8852B_DESC_PKT_T_DFS_RPT 8
#define RX_8852B_DESC_PKT_T_TX_PD_RELEASE_WLCPU 9
#define RX_8852B_DESC_PKT_T_C2H 10
#define RX_8852B_DESC_PPDU_T_LCCK 0
#define RX_8852B_DESC_PPDU_T_SCCK 1
#define RX_8852B_DESC_PPDU_T_OFDM 2
#define RX_8852B_DESC_PPDU_T_HT 3
#define RX_8852B_DESC_PPDU_T_HTGF 4
#define RX_8852B_DESC_PPDU_T_VHT_SU 5
#define RX_8852B_DESC_PPDU_T_VHT_MU 6
#define RX_8852B_DESC_PPDU_T_HE_SU 7
#define RX_8852B_DESC_PPDU_T_HE_ERSU 8
#define RX_8852B_DESC_PPDU_T_HE_MU 9
#define RX_8852B_DESC_PPDU_T_HE_TB 10
#define RX_8852B_DESC_PPDU_T_UNKNOWN 15
struct rx_ppdu_status{
u32 mac_info_length;
u32 phy_info_length;
//struct mac_info macinfo;
//struct phy_info phyinfo;
};
enum rtw_hal_status
hal_handle_rx_buffer_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
u8 *buf, u32 buf_len,
struct rtw_phl_rx_pkt *phl_rx);
#endif /*_HAL_TRX_8852B_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/hal_trx_8852b.h
|
C
|
agpl-3.0
| 8,921
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TRX_8852BE_C_
#include "../../hal_headers.h"
#include "../rtl8852b_hal.h"
#include "hal_trx_8852be.h"
/**
* this function will query total hw tx dma channels number
*
* returns the number of hw tx dma channel
*/
static u8 hal_query_txch_num_8852be(void)
{
u8 ch_num = 0;
ch_num = TX_DMA_CHANNEL_ENTRY_8852BE;
return ch_num;
}
/**
* this function will query total hw rx dma channels number
*
* returns the number of hw rx dma channel
*/
static u8 hal_query_rxch_num_8852be(void)
{
u8 ch_num = 0;
ch_num = RX_DMA_CHANNEL_ENTRY_8852BE;
return ch_num;
}
static u8 hal_qsel_to_tid_8852be(struct hal_info_t *hal, u8 qsel_id, u8 tid_indic)
{
u8 tid = 0;
switch (qsel_id) {
case RTW_TXDESC_QSEL_BE_0:
case RTW_TXDESC_QSEL_BE_1:
case RTW_TXDESC_QSEL_BE_2:
case RTW_TXDESC_QSEL_BE_3:
tid = (1 == tid_indic) ? RTW_PHL_RING_CAT_TID3 : RTW_PHL_RING_CAT_TID0;
break;
case RTW_TXDESC_QSEL_BK_0:
case RTW_TXDESC_QSEL_BK_1:
case RTW_TXDESC_QSEL_BK_2:
case RTW_TXDESC_QSEL_BK_3:
tid = (1 == tid_indic) ? RTW_PHL_RING_CAT_TID2 : RTW_PHL_RING_CAT_TID1;
break;
case RTW_TXDESC_QSEL_VI_0:
case RTW_TXDESC_QSEL_VI_1:
case RTW_TXDESC_QSEL_VI_2:
case RTW_TXDESC_QSEL_VI_3:
tid = (1 == tid_indic) ? RTW_PHL_RING_CAT_TID5 : RTW_PHL_RING_CAT_TID4;
break;
case RTW_TXDESC_QSEL_VO_0:
case RTW_TXDESC_QSEL_VO_1:
case RTW_TXDESC_QSEL_VO_2:
case RTW_TXDESC_QSEL_VO_3:
tid = (1 == tid_indic) ? RTW_PHL_RING_CAT_TID7 : RTW_PHL_RING_CAT_TID6;
break;
case RTW_TXDESC_QSEL_MGT_0:
case RTW_TXDESC_QSEL_MGT_1:
tid = RTW_PHL_RING_CAT_MGNT;
break;
case RTW_TXDESC_QSEL_HIGH_0:
case RTW_TXDESC_QSEL_HIGH_1:
tid = RTW_PHL_RING_CAT_HIQ;
break;
default :
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown qsel_id (%d)\n",
qsel_id);
tid = 0;
break;
}
return tid;
}
/**
* Get target DMA channel's BD ram hw register of rtl8852b
* @dma_ch: input target dma channel with the hw definition of rtl8852BE
* return the BD ram hw register
*/
static u32 _hal_get_bd_ram_reg_8852be(u8 dma_ch)
{
u32 reg = 0;
switch (dma_ch) {
case ACH0_QUEUE_IDX_8852BE:
reg = R_AX_ACH0_BDRAM_CTRL;
break;
case ACH1_QUEUE_IDX_8852BE:
reg = R_AX_ACH1_BDRAM_CTRL;
break;
case ACH2_QUEUE_IDX_8852BE:
reg = R_AX_ACH2_BDRAM_CTRL;
break;
case ACH3_QUEUE_IDX_8852BE:
reg = R_AX_ACH3_BDRAM_CTRL;
break;
case ACH4_QUEUE_IDX_8852BE:
reg = R_AX_ACH4_BDRAM_CTRL;
break;
case ACH5_QUEUE_IDX_8852BE:
reg = R_AX_ACH5_BDRAM_CTRL;
break;
case ACH6_QUEUE_IDX_8852BE:
reg = R_AX_ACH6_BDRAM_CTRL;
break;
case ACH7_QUEUE_IDX_8852BE:
reg = R_AX_ACH7_BDRAM_CTRL;
break;
case MGQ_B0_QUEUE_IDX_8852BE:
reg = R_AX_CH8_BDRAM_CTRL;
break;
case HIQ_B0_QUEUE_IDX_8852BE:
reg = R_AX_CH9_BDRAM_CTRL;
break;
case MGQ_B1_QUEUE_IDX_8852BE:
reg = R_AX_CH10_BDRAM_CTRL;
break;
case HIQ_B1_QUEUE_IDX_8852BE:
reg = R_AX_CH11_BDRAM_CTRL;
break;
case FWCMD_QUEUE_IDX_8852BE:
reg = R_AX_CH12_BDRAM_CTRL;
break;
default :
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown channel (%d)\n",
dma_ch);
reg = 0xFFFF;
break;
}
return reg;
}
/**
* Get target DMA channel's BD num hw register of rtl8852b
* @dma_ch: input target dma channel with the hw definition of rtl8852BE
* return the BD num hw register
*/
static u32 _hal_get_bd_num_reg_8852be(u8 dma_ch)
{
u32 reg = 0;
switch (dma_ch) {
case ACH0_QUEUE_IDX_8852BE:
reg = R_AX_ACH0_TXBD_NUM;
break;
case ACH1_QUEUE_IDX_8852BE:
reg = R_AX_ACH1_TXBD_NUM;
break;
case ACH2_QUEUE_IDX_8852BE:
reg = R_AX_ACH2_TXBD_NUM;
break;
case ACH3_QUEUE_IDX_8852BE:
reg = R_AX_ACH3_TXBD_NUM;
break;
case ACH4_QUEUE_IDX_8852BE:
reg = R_AX_ACH4_TXBD_NUM;
break;
case ACH5_QUEUE_IDX_8852BE:
reg = R_AX_ACH5_TXBD_NUM;
break;
case ACH6_QUEUE_IDX_8852BE:
reg = R_AX_ACH6_TXBD_NUM;
break;
case ACH7_QUEUE_IDX_8852BE:
reg = R_AX_ACH7_TXBD_NUM;
break;
case MGQ_B0_QUEUE_IDX_8852BE:
reg = R_AX_CH8_TXBD_NUM;
break;
case HIQ_B0_QUEUE_IDX_8852BE:
reg = R_AX_CH9_TXBD_NUM;
break;
case MGQ_B1_QUEUE_IDX_8852BE:
reg = R_AX_CH10_TXBD_NUM;
break;
case HIQ_B1_QUEUE_IDX_8852BE:
reg = R_AX_CH11_TXBD_NUM;
break;
case FWCMD_QUEUE_IDX_8852BE:
reg = R_AX_CH12_TXBD_NUM;
break;
case RX_QUEUE_IDX_8852BE:
reg = R_AX_RXQ_RXBD_NUM;
break;
case RP_QUEUE_IDX_8852BE:
reg = R_AX_RPQ_RXBD_NUM;
break;
default :
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown channel (%d)\n",
dma_ch);
reg = 0xFFFF;
break;
}
return reg;
}
/**
* Get target DMA channel's BD Desc hw register of rtl8852b
* @dma_ch: input target dma channel with the hw definition of rtl8852BE
* return the BD Desc hw register
*/
static void _hal_get_bd_desc_reg_8852be(u8 dma_ch, u32 *addr_l, u32 *addr_h)
{
u32 reg = 0;
switch (dma_ch) {
case ACH0_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH0_TXBD_DESA_L;
*addr_h = R_AX_ACH0_TXBD_DESA_H;
break;
case ACH1_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH1_TXBD_DESA_L;
*addr_h = R_AX_ACH1_TXBD_DESA_H;
break;
case ACH2_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH2_TXBD_DESA_L;
*addr_h = R_AX_ACH2_TXBD_DESA_H;
break;
case ACH3_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH3_TXBD_DESA_L;
*addr_h = R_AX_ACH3_TXBD_DESA_H;
break;
case ACH4_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH4_TXBD_DESA_L;
*addr_h = R_AX_ACH4_TXBD_DESA_H;
break;
case ACH5_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH5_TXBD_DESA_L;
*addr_h = R_AX_ACH5_TXBD_DESA_H;
break;
case ACH6_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH6_TXBD_DESA_L;
*addr_h = R_AX_ACH6_TXBD_DESA_H;
break;
case ACH7_QUEUE_IDX_8852BE:
*addr_l = R_AX_ACH7_TXBD_DESA_L;
*addr_h = R_AX_ACH7_TXBD_DESA_H;
break;
case MGQ_B0_QUEUE_IDX_8852BE:
*addr_l = R_AX_CH8_TXBD_DESA_L;
*addr_h = R_AX_CH8_TXBD_DESA_H;
break;
case HIQ_B0_QUEUE_IDX_8852BE:
*addr_l = R_AX_CH9_TXBD_DESA_L;
*addr_h = R_AX_CH9_TXBD_DESA_H;
break;
case MGQ_B1_QUEUE_IDX_8852BE:
*addr_l = R_AX_CH10_TXBD_DESA_L;
*addr_h = R_AX_CH10_TXBD_DESA_H;
break;
case HIQ_B1_QUEUE_IDX_8852BE:
*addr_l = R_AX_CH11_TXBD_DESA_L;
*addr_h = R_AX_CH11_TXBD_DESA_H;
break;
case FWCMD_QUEUE_IDX_8852BE:
*addr_l = R_AX_CH12_TXBD_DESA_L;
*addr_h = R_AX_CH12_TXBD_DESA_H;
break;
case RX_QUEUE_IDX_8852BE:
*addr_l = R_AX_RXQ_RXBD_DESA_L;
*addr_h = R_AX_RXQ_RXBD_DESA_H;
break;
case RP_QUEUE_IDX_8852BE:
*addr_l = R_AX_RPQ_RXBD_DESA_L;
*addr_h = R_AX_RPQ_RXBD_DESA_H;
break;
default :
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown channel (%d)\n",
dma_ch);
reg = 0xFFFF;
break;
}
}
/**
* Get target DMA channel's BD Index hw register of rtl8852b
* @dma_ch: input target dma channel with the hw definition of rtl8852BE
* return the BD Index hw register
*/
static u32 _hal_get_bd_idx_reg_8852be(u8 dma_ch)
{
u32 reg = 0;
switch (dma_ch) {
case ACH0_QUEUE_IDX_8852BE:
reg = R_AX_ACH0_TXBD_IDX;
break;
case ACH1_QUEUE_IDX_8852BE:
reg = R_AX_ACH1_TXBD_IDX;
break;
case ACH2_QUEUE_IDX_8852BE:
reg = R_AX_ACH2_TXBD_IDX;
break;
case ACH3_QUEUE_IDX_8852BE:
reg = R_AX_ACH3_TXBD_IDX;
break;
case ACH4_QUEUE_IDX_8852BE:
reg = R_AX_ACH4_TXBD_IDX;
break;
case ACH5_QUEUE_IDX_8852BE:
reg = R_AX_ACH5_TXBD_IDX;
break;
case ACH6_QUEUE_IDX_8852BE:
reg = R_AX_ACH6_TXBD_IDX;
break;
case ACH7_QUEUE_IDX_8852BE:
reg = R_AX_ACH7_TXBD_IDX;
break;
case MGQ_B0_QUEUE_IDX_8852BE:
reg = R_AX_CH8_TXBD_IDX;
break;
case HIQ_B0_QUEUE_IDX_8852BE:
reg = R_AX_CH9_TXBD_IDX;
break;
case MGQ_B1_QUEUE_IDX_8852BE:
reg = R_AX_CH10_TXBD_IDX;
break;
case HIQ_B1_QUEUE_IDX_8852BE:
reg = R_AX_CH11_TXBD_IDX;
break;
case FWCMD_QUEUE_IDX_8852BE:
reg = R_AX_CH12_TXBD_IDX;
break;
case RX_QUEUE_IDX_8852BE:
reg = R_AX_RXQ_RXBD_IDX;
break;
case RP_QUEUE_IDX_8852BE:
reg = R_AX_RPQ_RXBD_IDX;
break;
default :
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown channel (%d)\n",
dma_ch);
reg = 0xFFFF;
break;
}
return reg;
}
/**
* this function maps the sw xmit ring identified by macid, tid and band
* to rtl8852BE hw tx dma channel
* @macid: input target macid range is 0 ~ 127
* @cat: input target packet category, see enum rtw_phl_ring_cat
* @band: input target band, 0 for band 0 / 1 for band 1
*
* returns the mapping hw dma channel defined by XXX_QUEUE_IDX_8852BE
* if the input parameter is unknown value, returns ACH0_QUEUE_IDX_8852BE
*/
static u8 hal_mapping_hw_tx_chnl_8852be(u16 macid, enum rtw_phl_ring_cat cat,
u8 band)
{
u8 dma_ch = 0;
/* hana_todo, decided by tid only currently,
we should consider more situation later */
if (0 == band) {
switch (cat) {
case RTW_PHL_RING_CAT_TID0:
case RTW_PHL_RING_CAT_TID3:
dma_ch = ACH0_QUEUE_IDX_8852BE;
break;
case RTW_PHL_RING_CAT_TID1:
case RTW_PHL_RING_CAT_TID2:
dma_ch = ACH1_QUEUE_IDX_8852BE;
break;
case RTW_PHL_RING_CAT_TID4:
case RTW_PHL_RING_CAT_TID5:
dma_ch = ACH2_QUEUE_IDX_8852BE;
break;
case RTW_PHL_RING_CAT_TID6:
case RTW_PHL_RING_CAT_TID7:
dma_ch = ACH3_QUEUE_IDX_8852BE;
break;
case RTW_PHL_RING_CAT_MGNT:
dma_ch = MGQ_B0_QUEUE_IDX_8852BE;
break;
case RTW_PHL_RING_CAT_HIQ:
dma_ch = HIQ_B0_QUEUE_IDX_8852BE;
break;
default:
dma_ch = ACH0_QUEUE_IDX_8852BE;
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown category (%d)\n",
cat);
break;
}
} else {
dma_ch = ACH0_QUEUE_IDX_8852BE;
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]unknown band (%d)\n",
band);
}
return dma_ch;
}
/**
* this function will return available txbd number of target dma channel
* @ch_idx: input, target dma channel index
* @host_idx: the ptr of current host index of this channel
* @hw_idx: the ptr of current hw index of this channel
*
* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
*/
static u16 hal_get_avail_txbd_8852be(struct rtw_hal_com_t *hal_com, u8 ch_idx,
u16 *host_idx, u16 *hw_idx)
{
struct bus_cap_t *bus_cap = &hal_com->bus_cap;
u16 avail_txbd = 0;
u32 tmp32 = 0, reg = 0;
u8 tx_dma_ch = 0;
tx_dma_ch = ACH0_QUEUE_IDX_8852BE + ch_idx;
reg = _hal_get_bd_idx_reg_8852be(tx_dma_ch);
if (0xFFFF == reg) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING]get dma channel register fail\n");
avail_txbd = 0;
} else {
tmp32 = hal_read32(hal_com, reg);
*host_idx = (u16)(tmp32 & 0x0FFF);
*hw_idx = (u16)((tmp32 >> 16) & 0x0FFF);
avail_txbd = hal_calc_avail_wptr(*hw_idx, *host_idx,
(u16)bus_cap->txbd_num);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"hal_get_avail_txbd_8852be => dma_ch %d, host_idx %d, "
"hw_idx %d, avail_txbd %d\n",
ch_idx, *host_idx, *hw_idx, avail_txbd);
}
return avail_txbd;
}
/**
* this function will return available txbd number of target dma channel
* @ch_idx: input, target dma channel index
* @host_idx: the ptr of current host index of this channel
* @hw_idx: the ptr of current hw index of this channel
*
* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
*/
static u16 hal_get_avail_rxbd_8852be(struct rtw_hal_com_t *hal_com, u8 ch_idx,
u16 *host_idx, u16 *hw_idx)
{
struct bus_cap_t *bus_cap = &hal_com->bus_cap;
u16 avail_rxbd = 0;
u32 tmp32 = 0, reg = 0;
u8 rx_dma_ch = 0;
rx_dma_ch = RX_QUEUE_IDX_8852BE + ch_idx;
reg = _hal_get_bd_idx_reg_8852be(rx_dma_ch);
if (0xFFFF == reg) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]get dma channel register fail\n");
avail_rxbd = 0;
} else {
tmp32 = hal_read32(hal_com, reg);
*host_idx = (u16)(tmp32 & 0x0FFF);
*hw_idx = (u16)((tmp32 >> 16) & 0x0FFF);
avail_rxbd = hal_calc_avail_rptr(*host_idx, *hw_idx,
(u16)bus_cap->rxbd_num);
}
return avail_rxbd;
}
void _hal_fill_wp_seq_field_8852be(u8 *seq_info, u16 wp_seq)
{
/* update sw wp seq */
SET_PCIE_SEQ_INFO_0(seq_info, wp_seq);
SET_PCIE_SEQ_INFO_0_VALID(seq_info, 1);
}
void _hal_fill_wp_addr_info_8852be(struct rtw_hal_com_t *hal_com,
u8 *addr_info, struct rtw_pkt_buf_list *pkt,
u8 num, u8 mpdu_ls, u8 msdu_ls)
{
SET_ADDR_INFO_LEN(addr_info, pkt->length);
SET_ADDR_INFO_NUM(addr_info, num);
SET_ADDR_INFO_MSDU_LS(addr_info, msdu_ls);
SET_ADDR_INFO_ADDR_LOW(addr_info, pkt->phy_addr_l);
SET_ADDR_INFO_ADDR_HIGH(addr_info, pkt->phy_addr_h);
}
u8 _hal_get_tid_indic_8852be(u8 tid)
{
u8 tid_indic = 0;
switch (tid) {
case RTW_PHL_RING_CAT_TID0:
case RTW_PHL_RING_CAT_TID1:
case RTW_PHL_RING_CAT_TID4:
case RTW_PHL_RING_CAT_TID6:
case RTW_PHL_RING_CAT_MGNT:
case RTW_PHL_RING_CAT_HIQ:
tid_indic = 0;
break;
case RTW_PHL_RING_CAT_TID3:
case RTW_PHL_RING_CAT_TID2:
case RTW_PHL_RING_CAT_TID5:
case RTW_PHL_RING_CAT_TID7:
tid_indic = 1;
break;
default:
PHL_ERR("unknown tid %d\n", tid);
break;
}
return tid_indic;
}
#ifdef CONFIG_PHL_TXSC
static u8 qsel_tbl[] = {
TID_0_QSEL/*0*/, TID_1_QSEL/*1*/, TID_2_QSEL/*1*/, TID_3_QSEL/*0*/,
TID_4_QSEL/*2*/, TID_5_QSEL/*2*/, TID_6_QSEL/*3*/, TID_7_QSEL/*2*/
};
static u8 tid_ind[] = {
TID_0_IND, TID_1_IND, TID_2_IND, TID_3_IND,
TID_4_IND, TID_5_IND, TID_6_IND, TID_7_IND
};
static enum rtw_hal_status
_hal_txsc_update_wd(struct hal_info_t *hal,
struct rtw_phl_pkt_req *req, u32 *wd_len)
{
struct rtw_xmit_req *tx_req = req ? req->tx_req : NULL;
struct rtw_t_meta_data *mdata;
u32 *wd_words;
u32 w0, w2, w3;
if (NULL == tx_req)
return RTW_HAL_STATUS_FAILURE;
if (req->wd_len == 0) {
rtw_hal_mac_ax_fill_txdesc(hal->mac, tx_req, req->wd_page,
wd_len);
req->wd_len = (u8)*wd_len;
} else {
mdata = &tx_req->mdata;
mdata->dma_ch = hal_mapping_hw_tx_chnl_8852be(mdata->macid, mdata->tid, mdata->band);
wd_words = (u32 *)req->wd_page;
w0 = le32_to_cpu(wd_words[0])
& ~((AX_TXD_HW_SSN_SEL_MSK << AX_TXD_HW_SSN_SEL_SH)
| (AX_TXD_CH_DMA_MSK << AX_TXD_CH_DMA_SH));
w2 = le32_to_cpu(wd_words[2])
& ~(AX_TXD_TID_IND
| (AX_TXD_QSEL_MSK << AX_TXD_QSEL_SH)
| (AX_TXD_TXPKTSIZE_MSK << AX_TXD_TXPKTSIZE_SH));
/* Update SSN SEL, DMA CH, QSEL, and TID indicator in WD cache */
w0 |= (((mdata->hw_ssn_sel & AX_TXD_HW_SSN_SEL_MSK) << AX_TXD_HW_SSN_SEL_SH)
| ((mdata->dma_ch & AX_TXD_CH_DMA_MSK) << AX_TXD_CH_DMA_SH));
wd_words[0] = cpu_to_le32(w0);
if (mdata->hw_seq_mode == 0) {
w3 = cpu_to_le32((mdata->sw_seq & 0xFFF) |
(mdata->ampdu_en ? BIT(12) : 0) |
((mdata->bk || mdata->ack_ch_info) ? BIT(13) : 0));
wd_words[3] = w3;
}
if (tid_ind[mdata->tid])
w2 |= AX_TXD_TID_IND;
w2 |= (qsel_tbl[mdata->tid] & AX_TXD_QSEL_MSK) << AX_TXD_QSEL_SH;
w2 |= (mdata->pktlen & AX_TXD_TXPKTSIZE_MSK) << AX_TXD_TXPKTSIZE_SH;
wd_words[2] = cpu_to_le32(w2);
*wd_len = req->wd_len;
}
return RTW_HAL_STATUS_SUCCESS;
}
#endif
/**
* the function update wd page, including wd info, wd body, seq info, addr info
* @hal: see struct hal_info_t
* @phl_pkt_req: see struct rtw_phl_pkt_req
*/
static enum rtw_hal_status
hal_update_wd_8852be(struct hal_info_t *hal,
struct rtw_phl_pkt_req *req)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal->hal_com;
struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap;
struct rtw_xmit_req *tx_req = NULL;
struct rtw_pkt_buf_list *pkt_list = NULL;
u32 wd_len = 0, seq_ofst = 0, addr_info_ofst = 0;
u16 wp_seq = 0;
u8 i = 0, wp_num = 0, mpdu_ls = 0, msdu_ls = 0, tid_indic = 0;
FUNCIN_WSTS(hstatus);
do {
if (NULL == req)
break;
tx_req = req->tx_req;
pkt_list = (struct rtw_pkt_buf_list *)tx_req->pkt_list;
#ifdef CONFIG_PHL_TXSC
_hal_txsc_update_wd(hal, req, &wd_len);
#else
/* connect with halmac */
rtw_hal_mac_ax_fill_txdesc(hal->mac, tx_req, req->wd_page,
&wd_len);
#endif
tid_indic = _hal_get_tid_indic_8852be(tx_req->mdata.tid);
seq_ofst = wd_len;
wp_seq = (1 == tid_indic) ?
(req->wp_seq | WP_TID_INDIC_RESERVED_BIT) : req->wp_seq;
_hal_fill_wp_seq_field_8852be(req->wd_page + seq_ofst, wp_seq);
addr_info_ofst = seq_ofst + bus_hw_cap->seq_info_size;
for (i = 0; i < tx_req->mdata.addr_info_num; i++) {
if (0 == i)
wp_num = tx_req->mdata.addr_info_num;
else
wp_num = 0;
if ((tx_req->mdata.addr_info_num - 1) == i)
msdu_ls = 1;
else
msdu_ls = 0;
_hal_fill_wp_addr_info_8852be(hal_com,
req->wd_page + addr_info_ofst,
&pkt_list[i], wp_num, mpdu_ls, msdu_ls);
addr_info_ofst += bus_hw_cap->addr_info_size;
//debug_dump_data(pkt_list[i].vir_addr, pkt_list[i].length, "dump wp");
}
/* 8852BE length in txbd(wd_len) should be fix to 128 */
if (addr_info_ofst != bus_hw_cap->max_wd_page_size)
req->wd_len = bus_hw_cap->max_wd_page_size;
} while (false);
#if 0 /* remove this for saving cpu cycle */
if (RTW_HAL_STATUS_SUCCESS == hstatus) {
debug_dump_data(req->wd_page, (u16)addr_info_ofst, "dump wd page");
}
#endif
FUNCOUT_WSTS(hstatus);
return hstatus;
}
/**
* the function update txbd
* @hal: see struct hal_info_t
* @txbd_ring: the target txbd ring buffer going to update, see struct tx_base_desc
* @wd: the wd page going to be filled in txbd, see struct rtw_wd_page
*/
static enum rtw_hal_status
hal_update_txbd_8852be(struct hal_info_t *hal,
struct tx_base_desc *txbd_ring,
struct rtw_wd_page *wd_page,
u8 ch_idx, u16 wd_num)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal->hal_com;
struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap;
u8 *ring_head = 0;
u8 *target_txbd = 0;
u16 host_idx = 0, txbd_host_idx = 0, hw_idx = 0;
u16 avail_txbd = 0, wcnt = 0;
u16 txbd_num = (u16)hal_com->bus_cap.txbd_num;
do {
if (NULL == wd_page)
break;
if (NULL == txbd_ring)
break;
/* connect with halmac */
host_idx = txbd_ring[ch_idx].host_idx;
avail_txbd = hal_get_avail_txbd_8852be(hal->hal_com, ch_idx,
&txbd_host_idx, &hw_idx);
wcnt = (wd_num > avail_txbd) ? avail_txbd : wd_num;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"hal_update_txbd_8852be => ch_idx %d, host_idx %d, "
"hw_idx %d, avail_txbd %d, wcnt %d\n",
ch_idx, txbd_host_idx, hw_idx, avail_txbd, wcnt);
while (wcnt > 0) {
ring_head = txbd_ring[ch_idx].vir_addr;
target_txbd = ring_head + (host_idx *
bus_hw_cap->txbd_len);
SET_TXBUFFER_DESC_LEN(target_txbd, wd_page->buf_len);
SET_TXBUFFER_DESC_LS(target_txbd, wd_page->ls);
SET_TXBUFFER_DESC_ADD_LOW(target_txbd,
wd_page->phy_addr_l);
SET_TXBUFFER_DESC_ADD_HIGH(target_txbd,
wd_page->phy_addr_h);
host_idx = (host_idx + 1) % txbd_num;
wd_page->host_idx = host_idx;
wcnt--;
//multi wd page in one update txbd
#if 0//S_TODO
if(wcnt > 0){
wd_page = list_first_entry(wd_page->list,
struct rtw_wd_page,
wd_page->list);
if(NULL == wd_page)
break;
}
#endif
}
txbd_ring[ch_idx].host_idx = host_idx;
} while (false);
return hstatus;
}
/**
* the function trigger tx start
* @hal: see struct hal_info_t
* @txbd_ring: the target txbd ring buffer going to update, see struct tx_base_desc
* @ch_idx: the dma channel index of this txbd_ring
*/
static enum rtw_hal_status
hal_trigger_txdma_8852be(struct hal_info_t *hal,
struct tx_base_desc *txbd_ring, u8 ch_idx)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
u8 tx_dma_ch;
u32 txbd_reg;
do {
/* connect with halmac */
tx_dma_ch = ACH0_QUEUE_IDX_8852BE + ch_idx;
txbd_reg = _hal_get_bd_idx_reg_8852be(tx_dma_ch);
if (0xFFFF == txbd_reg)
break;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"hal_trigger_txdma_8852be => dma_ch %d, host_idx %d.\n",
ch_idx, txbd_ring[ch_idx].host_idx);
hal_write16(hal->hal_com, txbd_reg, txbd_ring[ch_idx].host_idx);
#ifdef CONFIG_DBG_H2C_TX
if (tx_dma_ch == FWCMD_QUEUE_IDX_8852BE)
PHL_INFO("%s: 0x%x -> 0x%x\n", __func__,
_hal_get_bd_idx_reg_8852be(FWCMD_QUEUE_IDX_8852BE),
hal_read32(hal->hal_com, _hal_get_bd_idx_reg_8852be(FWCMD_QUEUE_IDX_8852BE)));
#endif /* CONFIG_DBG_H2C_TX */
hstatus = RTW_HAL_STATUS_SUCCESS;
} while (false);
return hstatus;
}
static enum rtw_hal_status hal_pltfm_tx_8852be(void *hal, struct rtw_h2c_pkt *h2c_pkt)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
#if 0
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_wd_page wd_page;
struct tx_base_desc *txbd_ring = NULL;
_os_mem_set(hal_to_drvpriv(hal_info), &wd_page, 0, sizeof(wd_page));
txbd_ring = (struct tx_base_desc *)hal_info->hal_com->fw_txbd;
wd_page.vir_addr = h2c_pkt->vir_addr;
wd_page.phy_addr_l = h2c_pkt->phy_addr_l;
wd_page.phy_addr_h= h2c_pkt->phy_addr_h;
wd_page.buf_len = h2c_pkt->buf_len;
wd_page.cache = 1;
_os_spinlock(hal_to_drvpriv(hal_info), &txbd_ring[FWCMD_QUEUE_IDX_8852BE].txbd_lock, _ps, NULL);
hstatus = hal_update_txbd_8852BE(hal_info, txbd_ring, &wd_page,
FWCMD_QUEUE_IDX_8852BE, 1);
_os_spinunlock(hal_to_drvpriv(hal_info), &txbd_ring[FWCMD_QUEUE_IDX_8852BE].txbd_lock, _ps, NULL);
/* enqueue busy queue */
hstatus = hal_trigger_txdma_8852BE(hal_info, txbd_ring, FWCMD_QUEUE_IDX_8852BE);
#endif
return hstatus;
}
u8 hal_get_fwcmd_queue_idx_8852be(void)
{
return FWCMD_QUEUE_IDX_8852BE;
}
static u8 hal_check_rxrdy_8852be(struct rtw_phl_com_t *phl_com, u8 *rxbd_info,
u8 ch_idx)
{
struct hal_spec_t *hal_spec = &phl_com->hal_spec;
u8 res = false;
u16 tag = 0, target_tag = 0;
u16 read_cnt = 0;
do {
if (rxbd_info == NULL) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING] input rx bd info is NULL!\n");
res = false;
break;
}
tag = (u16)GET_RX_BD_INFO_TAG(rxbd_info);
if (hal_spec->rx_tag[ch_idx] == 0x1fff ||
hal_spec->rx_tag[ch_idx] == 0)
target_tag = 1;
else
target_tag = hal_spec->rx_tag[ch_idx] + 1;
while (read_cnt < 10000) {
read_cnt++;
tag = (u16)GET_RX_BD_INFO_TAG(rxbd_info);
if (tag == target_tag) {
res = true;
break;
}
}
if (true == res) {
hal_spec->rx_tag[ch_idx] = tag;
} else {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING] polling Rx Tag fail, tag = %d, target_tag = %d\n",
tag, target_tag);
#ifdef RTW_WKARD_98D_RXTAG
if (tag) {
hal_spec->rx_tag[ch_idx] = tag;
res = true;
}
#endif
}
} while (false);
return res;
}
u16 hal_handle_rx_report_8852be(struct hal_info_t *hal, u8 *rp, u16 len,
u8 *sw_retry, u8 *dma_ch, u16 *wp_seq,
u8 *txsts)
{
u8 polluted = false;
u16 rsize = 0;
u16 macid = 0;
u8 tid = 0, qsel_value = 0, band = 0, tid_indic = 0;
do {
if (len < RX_RP_PACKET_SIZE)
break;
macid = (u8)GET_RX_RP_PKT_MAC_ID(rp);
qsel_value = (u8)GET_RX_RP_PKT_QSEL(rp);
*txsts = (u8)GET_RX_RP_PKT_TX_STS(rp);
*wp_seq = (u16)GET_RX_RP_PKT_PCIE_SEQ(rp);
polluted = (u8)GET_RX_RP_PKT_POLLUTED(rp);
band = (qsel_value & BIT3) ? 1 : 0;
tid_indic = (*wp_seq & WP_TID_INDIC_RESERVED_BIT) ? 1 : 0;
*wp_seq &= (WP_RESERVED_SEQ);
tid = hal_qsel_to_tid_8852be(hal, qsel_value, tid_indic);
*dma_ch = hal_mapping_hw_tx_chnl_8852be(macid, tid, band);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "Get recycle report: qsel = %d, macid = %d, wp_seq = 0x%x, tid_indic = %d,"
" tid = %d, band = %d, dma_ch = %d\n",
qsel_value, macid, *wp_seq, tid_indic, tid, band, *dma_ch);
if (TX_STATUS_TX_DONE != *txsts) {
*sw_retry = true;
/* hana_todo handle sw retry */
} else if (true == polluted) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "this wp is polluted\n");
*sw_retry = true;
/* hana_todo handle sw retry */
} else {
*sw_retry = false;
}
rsize = RX_RP_PACKET_SIZE;
} while (false);
return rsize;
}
/**
* Process Rx PPDU Status with HALMAC API and PHYDM API
*/
static enum rtw_hal_status
hal_handle_ppdusts_8852be(void *hal, u8 *psbuf, u16 sz,
struct rtw_r_meta_data *mdata, struct rx_ppdu_status *rxps)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
if (mdata->mac_info_vld) {
/*Call HALMAC API HALMAC API*/
rxps->mac_info_length = 4; //To DO
}
rxps->phy_info_length = sz - rxps->mac_info_length;
if (rxps->phy_info_length > 0) {
/* the remaining length > 4 the phy info is valid */
/* CALL PHYDM API Here*/
//rx_desc->mac_id
}
hstatus = RTW_HAL_STATUS_SUCCESS;
return hstatus;
}
/**
* SW Parsing Rx Desc
**/
static enum rtw_hal_status
_hal_parsing_rx_wd_8852be(struct hal_info_t *hal, u8 *desc,
struct rtw_r_meta_data *mdata)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
mdata->pktlen = GET_RX_AX_DESC_PKT_LEN_8852B(desc);
mdata->shift = GET_RX_AX_DESC_SHIFT_8852B(desc);
mdata->wl_hd_iv_len = GET_RX_AX_DESC_HDR_IV_L_8852B(desc);
mdata->bb_sel = GET_RX_AX_DESC_BB_SEL_8852B(desc);
mdata->mac_info_vld = GET_RX_AX_DESC_MAC_INFO_VLD_8852B(desc);
mdata->rpkt_type = GET_RX_AX_DESC_RPKT_TYPE_8852B(desc);
mdata->drv_info_size = GET_RX_AX_DESC_DRV_INFO_SIZE_8852B(desc);
mdata->long_rxd = GET_RX_AX_DESC_LONG_RXD_8852B(desc);
mdata->ppdu_type = GET_RX_AX_DESC_PPDU_TYPE_8852B(desc);
mdata->ppdu_cnt = GET_RX_AX_DESC_PPDU_CNT_8852B(desc);
mdata->sr_en = GET_RX_AX_DESC_SR_EN_8852B(desc);
mdata->user_id = GET_RX_AX_DESC_USER_ID_8852B(desc);
mdata->rx_rate = GET_RX_AX_DESC_RX_DATARATE_8852B(desc);
mdata->rx_gi_ltf = GET_RX_AX_DESC_RX_GI_LTF_8852B(desc);
mdata->non_srg_ppdu = GET_RX_AX_DESC_NON_SRG_PPDU_8852B(desc);
mdata->inter_ppdu = GET_RX_AX_DESC_INTER_PPDU_8852B(desc);
mdata->bw = GET_RX_AX_DESC_BW_8852B(desc);
mdata->freerun_cnt = GET_RX_AX_DESC_FREERUN_CNT_8852B(desc);
mdata->a1_match = GET_RX_AX_DESC_A1_MATCH_8852B(desc);
mdata->sw_dec = GET_RX_AX_DESC_SW_DEC_8852B(desc);
mdata->hw_dec = GET_RX_AX_DESC_HW_DEC_8852B(desc);
mdata->ampdu = GET_RX_AX_DESC_AMPDU_8852B(desc);
mdata->ampdu_end_pkt = GET_RX_AX_DESC_AMPDU_EDN_PKT_8852B(desc);
mdata->amsdu = GET_RX_AX_DESC_AMSDU_8852B(desc);
mdata->amsdu_cut = GET_RX_AX_DESC_AMSDU_CUT_8852B(desc);
mdata->last_msdu = GET_RX_AX_DESC_LAST_MSDU_8852B(desc);
mdata->bypass = GET_RX_AX_DESC_BYPASS_8852B(desc);
mdata->crc32 = GET_RX_AX_DESC_CRC32_8852B(desc);
mdata->icverr = GET_RX_AX_DESC_ICVERR_8852B(desc);
mdata->magic_wake = GET_RX_AX_DESC_MAGIC_WAKE_8852B(desc);
mdata->unicast_wake = GET_RX_AX_DESC_UNICAST_WAKE_8852B(desc);
mdata->pattern_wake = GET_RX_AX_DESC_PATTERN_WAKE_8852B(desc);
if (mdata->long_rxd==1) {
mdata->macid = GET_RX_AX_DESC_MACID_8852B(desc);
}
hstatus = RTW_HAL_STATUS_SUCCESS;
return hstatus;
}
static u8 hal_handle_rxbd_info_8852be(struct hal_info_t *hal,
u8 *rxbd_info, u16 *size)
{
u8 res = false;
u16 pld_size = 0;
u8 fs = 0, ls = 0;
u8 pkt_rdy = false;
do {
if (NULL == rxbd_info)
break;
if (NULL == size)
break;
fs = (u8)GET_RX_BD_INFO_FS(rxbd_info);
ls = (u8)GET_RX_BD_INFO_LS(rxbd_info);
pld_size = (u16)GET_RX_BD_INFO_HW_W_SIZE(rxbd_info);
if (fs == 1) {
if (ls == 1)
pkt_rdy = true;
else
pkt_rdy = false;
} else if (fs == 0) {
if (ls == 1)
pkt_rdy = false;
else
pkt_rdy = false;
}
if (pkt_rdy) {
*size = pld_size;
res = true;
} else {
*size = 0;
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING] need to handle RX FS/LS\n");
res = false;
}
}while(false);
return res;
}
/**
* the function update rxbd
*/
static enum rtw_hal_status
hal_update_rxbd_8852be(struct hal_info_t *hal, struct rx_base_desc *rxbd,
struct rtw_rx_buf *rx_buf)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal->hal_com;
struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap;
u8 *ring_head = NULL;
u8 *target_rxbd = NULL;
u16 rxbd_num = (u16)hal_com->bus_cap.rxbd_num;
do {
if (NULL == rxbd)
break;
if (NULL == rx_buf)
break;
ring_head = rxbd->vir_addr;
target_rxbd = ring_head + (rxbd->host_idx *
bus_hw_cap->rxbd_len);
/* connect with halmac */
SET_RX_BD_RXBUFFSIZE(target_rxbd, rx_buf->buf_len);
SET_RX_BD_PHYSICAL_ADDR_LOW(target_rxbd,
(u32)rx_buf->phy_addr_l);
SET_RX_BD_PHYSICAL_ADDR_HIGH(target_rxbd,
(u32)rx_buf->phy_addr_h);
rxbd->host_idx = (rxbd->host_idx + 1) % rxbd_num;
} while (false);
return hstatus;
}
/**
* the function notify rx done
*/
static enum rtw_hal_status
hal_notify_rxdone_8852be(struct hal_info_t *hal,
struct rx_base_desc *rxbd, u8 ch, u16 rxcnt)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
u32 reg = 0;
u8 rx_dma_ch = 0;
do {
rx_dma_ch = RX_QUEUE_IDX_8852BE + ch;
reg = _hal_get_bd_idx_reg_8852be(rx_dma_ch);
/* connect with halmac */
if (0xFFFF == reg)
break;
hal_write16(hal->hal_com, reg, rxbd->host_idx);
hstatus = RTW_HAL_STATUS_SUCCESS;
} while (false);
return hstatus;
}
struct bd_ram bdram_table_8852b[] = {
/* ACH0_QUEUE_IDX_8852BE */ {0, 25, 4},
/* ACH1_QUEUE_IDX_8852BE */ {25, 25, 4},
/* ACH2_QUEUE_IDX_8852BE */ {50, 25, 4},
/* ACH3_QUEUE_IDX_8852BE */ {75, 25, 4},
/* ACH4_QUEUE_IDX_8852BE */ {100, 25, 4},
/* ACH5_QUEUE_IDX_8852BE */ {125, 25, 4},
/* ACH6_QUEUE_IDX_8852BE */ {150, 25, 4},
/* ACH7_QUEUE_IDX_8852BE */ {175, 25, 4},
/* MGQ_B0_QUEUE_IDX_8852BE */ {185, 10, 4},
/* HIQ_B0_QUEUE_IDX_8852BE */ {195, 10, 4},
/* MGQ_B1_QUEUE_IDX_8852BE */ {205, 10, 4},
/* HIQ_B1_QUEUE_IDX_8852BE */ {215, 10, 4},
/* FWCMD_QUEUE_IDX_8852BE */ {225, 10, 4}
};
static void _hal_tx_init_bd_ram_8852be(struct hal_info_t *hal)
{
u32 reg = 0;
u32 value = 0;
u8 i = 0;
for (i = 0; i < TX_DMA_CHANNEL_ENTRY_8852BE; i++) {
/*if (FWCMD_QUEUE_IDX_8852BE == i)
continue;*/
value = 0;
value = bdram_table_8852b[i].sidx +
((bdram_table_8852b[i].max << 8) & 0xFF00) +
((bdram_table_8852b[i].min << 16) & 0xFF0000);
reg = _hal_get_bd_ram_reg_8852be(i);
if (0 != reg)
hal_write32(hal->hal_com, reg, value);
else
PHL_ERR("query txbd num reg fail (ch_idx = %d)\n", i);
}
value = hal_read32(hal->hal_com, R_AX_PCIE_INIT_CFG1);
value |= (B_AX_RST_BDRAM);
hal_write32(hal->hal_com, R_AX_PCIE_INIT_CFG1, value);
}
static void _hal_trx_init_bd_num_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
u16 txbd_num = (u16)hal_com->bus_cap.txbd_num;
u16 rxbd_num = (u16)hal_com->bus_cap.rxbd_num;
u32 reg = 0;
u16 value = 0;
u8 i = 0;
for (i = 0; i < TX_DMA_CHANNEL_ENTRY_8852BE; i++) {
/*if (FWCMD_QUEUE_IDX_8852BE == i)
continue;*/
value = txbd_num & B_AX_DESC_NUM_MSK;
reg = _hal_get_bd_num_reg_8852be(i);
if (0 != reg)
hal_write16(hal->hal_com, reg, value);
else
PHL_ERR("query txbd num reg fail (ch_idx = %d)\n", i);
}
for (i = RX_QUEUE_IDX_8852BE;
i < RX_QUEUE_IDX_8852BE + RX_DMA_CHANNEL_ENTRY_8852BE; i++) {
/*if (FWCMD_QUEUE_IDX_8852BE == i)
continue;*/
value = rxbd_num & B_AX_DESC_NUM_MSK;
reg = _hal_get_bd_num_reg_8852be(i);
if (0 != reg)
hal_write16(hal->hal_com, reg, value);
else
PHL_ERR("query rxbd num reg fail (ch_idx = %d)\n", i);
}
}
static void _hal_trx_init_bd_8852be(struct hal_info_t *hal, u8 *txbd_buf, u8 *rxbd_buf)
{
struct tx_base_desc *txbd = NULL;
struct rx_base_desc *rxbd = NULL;
u32 reg_addr_l = 0, reg_addr_h = 0;
u8 i = 0, rxch_idx = 0;
if (NULL != txbd_buf && NULL != rxbd_buf) {
txbd = (struct tx_base_desc *)txbd_buf;
rxbd = (struct rx_base_desc *)rxbd_buf;
for (i = 0; i < TX_DMA_CHANNEL_ENTRY_8852BE; i++) {
/*if (FWCMD_QUEUE_IDX_8852BE == i)
continue;*/
_hal_get_bd_desc_reg_8852be(i, ®_addr_l, ®_addr_h);
if (0 != reg_addr_l)
hal_write32(hal->hal_com, reg_addr_l, txbd[i].phy_addr_l);
else
PHL_ERR("query txbd desc reg_addr_l fail (ch_idx = %d)\n", i);
if (0 != reg_addr_h)
hal_write32(hal->hal_com, reg_addr_h, txbd[i].phy_addr_h);
else
PHL_ERR("query txbd desc reg_addr_h fail (ch_idx = %d)\n", i);
}
for (i = 0; i < RX_DMA_CHANNEL_ENTRY_8852BE; i++) {
rxch_idx = i + RX_QUEUE_IDX_8852BE;
_hal_get_bd_desc_reg_8852be(rxch_idx, ®_addr_l, ®_addr_h);
if (0 != reg_addr_l)
hal_write32(hal->hal_com, reg_addr_l, rxbd[i].phy_addr_l);
else
PHL_ERR("query rxbd desc reg_addr_l fail (ch_idx = %d)\n", i);
if (0 != reg_addr_h)
hal_write32(hal->hal_com, reg_addr_h, rxbd[i].phy_addr_h);
else
PHL_ERR("query rxbd desc reg_addr_h fail (ch_idx = %d)\n", i);
}
}
}
static void _hal_tx_enable_truncate_mode(struct hal_info_t *hal, u8 *txbd_buf,
u8 *rxbd_buf)
{
struct tx_base_desc *txbd = NULL;
struct rx_base_desc *rxbd = NULL;
u32 value = 0;
txbd = (struct tx_base_desc *)txbd_buf;
rxbd = (struct rx_base_desc *)rxbd_buf;
value = hal_read32(hal->hal_com, R_AX_PCIE_INIT_CFG1);
value |= (B_AX_TX_TRUNC_MODE | B_AX_RX_TRUNC_MODE);
hal_write32(hal->hal_com, R_AX_PCIE_INIT_CFG1, value);
hal_write32(hal->hal_com, R_AX_TXDMA_ADDR_H, txbd->phy_addr_h);
hal_write32(hal->hal_com, R_AX_RXDMA_ADDR_H, rxbd->phy_addr_h);
}
static void _hal_tx_disable_truncate_mode(struct hal_info_t *hal)
{
u32 value = 0;
value = hal_read32(hal->hal_com, R_AX_TX_ADDRESS_INFO_MODE_SETTING);
value &= ~(B_AX_HOST_ADDR_INFO_8B_SEL);
hal_write32(hal->hal_com, R_AX_TX_ADDRESS_INFO_MODE_SETTING, value);
value = hal_read32(hal->hal_com, R_AX_PKTIN_SETTING);
value |= (B_AX_WD_ADDR_INFO_LENGTH);
hal_write32(hal->hal_com, R_AX_PKTIN_SETTING, value);
}
static void _hal_select_rxbd_mode(struct hal_info_t *hal,
enum rxbd_mode_8852BE mode)
{
u32 value = 0;
if (RXBD_MODE_PACKET == mode) {
value = hal_read32(hal->hal_com, R_AX_PCIE_INIT_CFG1);
value &= ~(B_AX_RXBD_MODE);
hal_write32(hal->hal_com, R_AX_PCIE_INIT_CFG1, value);
} else if (RXBD_MODE_SEPARATION == mode) {
/*
value = hal_read32(hal->hal_com, R_AX_PCIE_INIT_CFG1);
value |= (B_AX_RXBD_MODE);
hal_write32(hal->hal_com, R_AX_PCIE_INIT_CFG1, value);
*/
/* hana_todo, append length setting */
} else {
PHL_WARN("Unknown Rx BD mode (%d)\n", mode);
}
}
static void hal_cfg_wow_txdma_8852be(struct hal_info_t *hal, u8 en)
{
struct mac_ax_txdma_ch_map ch_map;
ch_map.ch0 = en ? MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
ch_map.ch1 = en ? MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
ch_map.ch2 = en ? MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
ch_map.ch3 = en ? MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
ch_map.ch4 = MAC_AX_PCIE_IGNORE;
ch_map.ch5 = MAC_AX_PCIE_IGNORE;
ch_map.ch6 = MAC_AX_PCIE_IGNORE;
ch_map.ch7 = MAC_AX_PCIE_IGNORE;
ch_map.ch8 = en ? MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
ch_map.ch9 = en ? MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE;
ch_map.ch10 = MAC_AX_PCIE_IGNORE;
ch_map.ch11 = MAC_AX_PCIE_IGNORE;
ch_map.ch12 = MAC_AX_PCIE_IGNORE;
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_txdma(hal, &ch_map))
PHL_ERR("%s failure \n", __func__);
}
static u8 hal_poll_txdma_idle_8852be(struct hal_info_t *hal)
{
struct mac_ax_txdma_ch_map ch_map;
ch_map.ch0 = MAC_AX_PCIE_ENABLE;
ch_map.ch1 = MAC_AX_PCIE_ENABLE;
ch_map.ch2 = MAC_AX_PCIE_ENABLE;
ch_map.ch3 = MAC_AX_PCIE_ENABLE;
ch_map.ch4 = MAC_AX_PCIE_IGNORE;
ch_map.ch5 = MAC_AX_PCIE_IGNORE;
ch_map.ch6 = MAC_AX_PCIE_IGNORE;
ch_map.ch7 = MAC_AX_PCIE_IGNORE;
ch_map.ch8 = MAC_AX_PCIE_ENABLE;
ch_map.ch9 = MAC_AX_PCIE_ENABLE;
ch_map.ch10 = MAC_AX_PCIE_IGNORE;
ch_map.ch11 = MAC_AX_PCIE_IGNORE;
ch_map.ch12 = MAC_AX_PCIE_ENABLE;
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_poll_txdma_idle(hal, &ch_map)) {
PHL_ERR("%s failure \n", __func__);
return false;
}
return true;
}
static void _hal_clear_trx_state(struct hal_info_t *hal)
{
u32 value = 0;
/* disable hci */
value = hal_read32(hal->hal_com, R_AX_PCIE_INIT_CFG1);
value &= ~(B_AX_RXHCI_EN | B_AX_TXHCI_EN);
hal_write32(hal->hal_com, R_AX_PCIE_INIT_CFG1, value);
/* check mac power on status */
/* clear hci idx */
value = hal_read32(hal->hal_com, R_AX_TXBD_RWPTR_CLR1);
value |= (B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX |
B_AX_CLR_ACH3_IDX | B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX |
B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX | B_AX_CLR_CH8_IDX |
B_AX_CLR_CH9_IDX | B_AX_CLR_CH12_IDX);
hal_write32(hal->hal_com, R_AX_TXBD_RWPTR_CLR1, value);
value = hal_read32(hal->hal_com, R_AX_TXBD_RWPTR_CLR2);
value |= (B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX);
hal_write32(hal->hal_com, R_AX_TXBD_RWPTR_CLR2, value);
value = hal_read32(hal->hal_com, R_AX_RXBD_RWPTR_CLR);
value |= (B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX);
hal_write32(hal->hal_com, R_AX_RXBD_RWPTR_CLR, value);
}
/**
* the function will deinitializing 8852BE specific data and hw configuration
*/
static void hal_trx_deinit_8852be(struct hal_info_t *hal)
{
/*struct rtw_hal_com_t *hal_com = hal->hal_com;*/
}
/**
* the function will initializing 8852BE specific data and hw configuration
*/
static enum rtw_hal_status hal_trx_init_8852be(struct hal_info_t *hal, u8 *txbd_buf, u8 *rxbd_buf)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
/* Set AMPDU max agg number to 128 */
/* CR setting*/
rtw_hal_mac_set_hw_ampdu_cfg(hal, 0, 0x7F, 0xAB);
return hstatus;
}
static struct hal_trx_ops ops = {0};
void hal_trx_ops_init_8852be(void)
{
ops.init = hal_trx_init_8852be;
ops.deinit = hal_trx_deinit_8852be;
ops.query_tx_res = hal_get_avail_txbd_8852be;
ops.query_rx_res = hal_get_avail_rxbd_8852be;
ops.cfg_wow_txdma = hal_cfg_wow_txdma_8852be;
ops.poll_txdma_idle = hal_poll_txdma_idle_8852be;
ops.map_hw_tx_chnl = hal_mapping_hw_tx_chnl_8852be;
ops.qsel_to_tid = hal_qsel_to_tid_8852be;
ops.query_txch_num = hal_query_txch_num_8852be;
ops.query_rxch_num = hal_query_rxch_num_8852be;
ops.update_wd = hal_update_wd_8852be;
ops.update_txbd = hal_update_txbd_8852be;
ops.tx_start = hal_trigger_txdma_8852be;
ops.check_rxrdy = hal_check_rxrdy_8852be;
ops.handle_rxbd_info = hal_handle_rxbd_info_8852be;
ops.handle_rx_buffer = hal_handle_rx_buffer_8852b;
ops.update_rxbd = hal_update_rxbd_8852be;
ops.notify_rxdone = hal_notify_rxdone_8852be;
ops.handle_wp_rpt = hal_handle_rx_report_8852be;
ops.get_fwcmd_queue_idx = hal_get_fwcmd_queue_idx_8852be;
}
u32 hal_hook_trx_ops_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
if (NULL != hal_info) {
hal_trx_ops_init_8852be();
hal_info->trx_ops = &ops;
hstatus = RTW_HAL_STATUS_SUCCESS;
}
return hstatus;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/hal_trx_8852be.c
|
C
|
agpl-3.0
| 38,714
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_TX_8852BE_H_
#define _HAL_TX_8852BE_H_
#define MAX_RX_TAG_VALUE 0x1FFF
#define ACH0_QUEUE_IDX_8852BE 0x0
#define ACH1_QUEUE_IDX_8852BE 0x1
#define ACH2_QUEUE_IDX_8852BE 0x2
#define ACH3_QUEUE_IDX_8852BE 0x3
#define ACH4_QUEUE_IDX_8852BE 0x4
#define ACH5_QUEUE_IDX_8852BE 0x5
#define ACH6_QUEUE_IDX_8852BE 0x6
#define ACH7_QUEUE_IDX_8852BE 0x7
#define MGQ_B0_QUEUE_IDX_8852BE 0x8
#define HIQ_B0_QUEUE_IDX_8852BE 0x9
#define MGQ_B1_QUEUE_IDX_8852BE 0xa
#define HIQ_B1_QUEUE_IDX_8852BE 0xb
#define FWCMD_QUEUE_IDX_8852BE 0xc
#define RX_QUEUE_IDX_8852BE 0x10
#define RP_QUEUE_IDX_8852BE 0x11
#define RTW_TXDESC_QSEL_BE_0 0x0
#define RTW_TXDESC_QSEL_BK_0 0x1
#define RTW_TXDESC_QSEL_VI_0 0x2
#define RTW_TXDESC_QSEL_VO_0 0x3
#define RTW_TXDESC_QSEL_BE_1 0x4
#define RTW_TXDESC_QSEL_BK_1 0x5
#define RTW_TXDESC_QSEL_VI_1 0x6
#define RTW_TXDESC_QSEL_VO_1 0x7
#define RTW_TXDESC_QSEL_BE_2 0x8
#define RTW_TXDESC_QSEL_BK_2 0x9
#define RTW_TXDESC_QSEL_VI_2 0xa
#define RTW_TXDESC_QSEL_VO_2 0xb
#define RTW_TXDESC_QSEL_BE_3 0xc
#define RTW_TXDESC_QSEL_BK_3 0xd
#define RTW_TXDESC_QSEL_VI_3 0xe
#define RTW_TXDESC_QSEL_VO_3 0xf
#define RTW_TXDESC_QSEL_BCN_0 0x10
#define RTW_TXDESC_QSEL_HIGH_0 0x11
#define RTW_TXDESC_QSEL_MGT_0 0x12
#define RTW_TXDESC_QSEL_MGT_NOPS_0 0x13
#define RTW_TXDESC_QSEL_CPU_MGT_0 0x14
#define RTW_TXDESC_QSEL_BCN_1 0x18
#define RTW_TXDESC_QSEL_HIGH_1 0x19
#define RTW_TXDESC_QSEL_MGT_1 0x1a
#define RTW_TXDESC_QSEL_MGT_NOPS_1 0x1b
#define RTW_TXDESC_QSEL_CPU_MGT_1 0x1c
/* AC channel * 8 + MGQ * 2 + HIQ * 2 + FW CMDQ * 1 */
#define TX_DMA_CHANNEL_ENTRY_8852BE 13
/* RXQ * 1 + RPQ * 1 */
#define RX_DMA_CHANNEL_ENTRY_8852BE 2
/* temp register definitions, will be replaced by halmac */
#define R_AX_RXQ_RXBD_IDX 0x1050
#define R_AX_RPQ_RXBD_IDX 0x1054
#define R_AX_ACH0_TXBD_IDX 0x1058
#define R_AX_ACH1_TXBD_IDX 0x105C
#define R_AX_ACH2_TXBD_IDX 0x1060
#define R_AX_ACH3_TXBD_IDX 0x1064
#define R_AX_ACH4_TXBD_IDX 0x1068
#define R_AX_ACH5_TXBD_IDX 0x106C
#define R_AX_ACH6_TXBD_IDX 0x1070
#define R_AX_ACH7_TXBD_IDX 0x1074
#define R_AX_CH8_TXBD_IDX 0x1078 /* Mgnt Queue band 0 */
#define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
#define R_AX_CH10_TXBD_IDX 0x137C /* Mgnt Queue band 1 */
#define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
#define R_AX_CH12_TXBD_IDX 0x1080 /* FW CMD */
#define R_AX_ACH0_TXBD_DESA_L 0x1110
#define R_AX_ACH0_TXBD_DESA_H 0x1114
#define R_AX_ACH1_TXBD_DESA_L 0x1118
#define R_AX_ACH1_TXBD_DESA_H 0x111C
#define R_AX_ACH2_TXBD_DESA_L 0x1120
#define R_AX_ACH2_TXBD_DESA_H 0x1124
#define R_AX_ACH3_TXBD_DESA_L 0x1128
#define R_AX_ACH3_TXBD_DESA_H 0x112C
#define R_AX_ACH4_TXBD_DESA_L 0x1130
#define R_AX_ACH4_TXBD_DESA_H 0x1134
#define R_AX_ACH5_TXBD_DESA_L 0x1138
#define R_AX_ACH5_TXBD_DESA_H 0x113C
#define R_AX_ACH6_TXBD_DESA_L 0x1140
#define R_AX_ACH6_TXBD_DESA_H 0x1144
#define R_AX_ACH7_TXBD_DESA_L 0x1148
#define R_AX_ACH7_TXBD_DESA_H 0x114C
#define R_AX_CH8_TXBD_DESA_L 0x1150
#define R_AX_CH8_TXBD_DESA_H 0x1154
#define R_AX_CH9_TXBD_DESA_L 0x1158
#define R_AX_CH9_TXBD_DESA_H 0x115C
#define R_AX_CH10_TXBD_DESA_L 0x1358
#define R_AX_CH10_TXBD_DESA_H 0x135C
#define R_AX_CH11_TXBD_DESA_L 0x1360
#define R_AX_CH11_TXBD_DESA_H 0x1364
#define R_AX_CH12_TXBD_DESA_L 0x1160
#define R_AX_CH12_TXBD_DESA_H 0x1164
#define R_AX_RXQ_RXBD_DESA_L 0x1100
#define R_AX_RXQ_RXBD_DESA_H 0x1104
#define R_AX_RPQ_RXBD_DESA_L 0x1108
#define R_AX_RPQ_RXBD_DESA_H 0x110C
#define B_AX_DESC_NUM_MSK 0xfff
#define R_AX_RXQ_RXBD_NUM 0x1020
#define R_AX_RPQ_RXBD_NUM 0x1022
#define R_AX_ACH0_TXBD_NUM 0x1024
#define R_AX_ACH1_TXBD_NUM 0x1026
#define R_AX_ACH2_TXBD_NUM 0x1028
#define R_AX_ACH3_TXBD_NUM 0x102A
#define R_AX_ACH4_TXBD_NUM 0x102C
#define R_AX_ACH5_TXBD_NUM 0x102E
#define R_AX_ACH6_TXBD_NUM 0x1030
#define R_AX_ACH7_TXBD_NUM 0x1032
#define R_AX_CH8_TXBD_NUM 0x1034
#define R_AX_CH9_TXBD_NUM 0x1036
#define R_AX_CH10_TXBD_NUM 0x1338
#define R_AX_CH11_TXBD_NUM 0x133A
#define R_AX_CH12_TXBD_NUM 0x1038
#define R_AX_ACH0_BDRAM_CTRL 0x1200
#define R_AX_ACH1_BDRAM_CTRL 0x1204
#define R_AX_ACH2_BDRAM_CTRL 0x1208
#define R_AX_ACH3_BDRAM_CTRL 0x120C
#define R_AX_ACH4_BDRAM_CTRL 0x1210
#define R_AX_ACH5_BDRAM_CTRL 0x1214
#define R_AX_ACH6_BDRAM_CTRL 0x1218
#define R_AX_ACH7_BDRAM_CTRL 0x121C
#define R_AX_CH8_BDRAM_CTRL 0x1220
#define R_AX_CH9_BDRAM_CTRL 0x1224
#define R_AX_CH10_BDRAM_CTRL 0x1320
#define R_AX_CH11_BDRAM_CTRL 0x1324
#define R_AX_CH12_BDRAM_CTRL 0x1228
#define R_AX_PCIE_INIT_CFG1 0x1000
#define B_AX_PCIE_RXRST_KEEP_REG BIT(23)
#define B_AX_PCIE_TXRST_KEEP_REG BIT(22)
#define B_AX_PCIE_PERST_KEEP_REG BIT(21)
#define B_AX_PCIE_FLR_KEEP_REG BIT(20)
#define B_AX_PCIE_TRAIN_KEEP_REG BIT(19)
#define B_AX_RXBD_MODE BIT(18)
#define B_AX_PCIE_MAX_RXDMA_SH 14
#define B_AX_PCIE_MAX_RXDMA_MSK 0x7
#define B_AX_RXHCI_EN BIT(13)
#define B_AX_LATENCY_CONTROL BIT(12)
#define B_AX_TXHCI_EN BIT(11)
#define B_AX_PCIE_MAX_TXDMA_SH 8
#define B_AX_PCIE_MAX_TXDMA_MSK 0x7
#define B_AX_TX_TRUNC_MODE BIT(5)
#define B_AX_RX_TRUNC_MODE BIT(4)
#define B_AX_RST_BDRAM BIT(3)
#define B_AX_DIS_RXDMA_PRE BIT(2)
#define R_AX_TXDMA_ADDR_H 0x10F0
#define R_AX_RXDMA_ADDR_H 0x10F4
#define R_AX_PCIE_DMA_STOP1 0x1010
#define B_AX_STOP_WPDMA BIT(19)
#define B_AX_STOP_CH12 BIT(18)
#define B_AX_STOP_CH9 BIT(17)
#define B_AX_STOP_CH8 BIT(16)
#define B_AX_STOP_ACH7 BIT(15)
#define B_AX_STOP_ACH6 BIT(14)
#define B_AX_STOP_ACH5 BIT(13)
#define B_AX_STOP_ACH4 BIT(12)
#define B_AX_STOP_ACH3 BIT(11)
#define B_AX_STOP_ACH2 BIT(10)
#define B_AX_STOP_ACH1 BIT(9)
#define B_AX_STOP_ACH0 BIT(8)
#define B_AX_STOP_RPQ BIT(1)
#define B_AX_STOP_RXQ BIT(0)
#define R_AX_PCIE_DMA_STOP2 0x1310
#define B_AX_STOP_CH11 BIT(1)
#define B_AX_STOP_CH10 BIT(0)
#define R_AX_TXBD_RWPTR_CLR1 0x1014
#define B_AX_CLR_CH12_IDX BIT(10)
#define B_AX_CLR_CH9_IDX BIT(9)
#define B_AX_CLR_CH8_IDX BIT(8)
#define B_AX_CLR_ACH7_IDX BIT(7)
#define B_AX_CLR_ACH6_IDX BIT(6)
#define B_AX_CLR_ACH5_IDX BIT(5)
#define B_AX_CLR_ACH4_IDX BIT(4)
#define B_AX_CLR_ACH3_IDX BIT(3)
#define B_AX_CLR_ACH2_IDX BIT(2)
#define B_AX_CLR_ACH1_IDX BIT(1)
#define B_AX_CLR_ACH0_IDX BIT(0)
#define R_AX_RXBD_RWPTR_CLR 0x1018
#define B_AX_CLR_RPQ_IDX BIT(1)
#define B_AX_CLR_RXQ_IDX BIT(0)
#define R_AX_TXBD_RWPTR_CLR2 0x1314
#define B_AX_CLR_CH11_IDX BIT(1)
#define B_AX_CLR_CH10_IDX BIT(0)
#define R_AX_PCIE_DMA_BUSY2 0x131C
#define B_AX_CH11_BUSY BIT(1)
#define B_AX_CH10_BUSY BIT(0)
#define GET_RX_RP_PKT_POLLUTED(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 31, 1)
#define GET_RX_RP_PKT_PCIE_SEQ(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 16, 15)
#define GET_RX_RP_PKT_TX_STS(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 13, 3)
#define GET_RX_RP_PKT_QSEL(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 8, 5)
#define GET_RX_RP_PKT_MAC_ID(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 0, 8)
/* TX BD */
#define SET_TXBUFFER_DESC_LEN(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 0, 16, __Value)
#define SET_TXBUFFER_DESC_ADD_HIGH(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 22, 8, __Value)
#define SET_TXBUFFER_DESC_LS(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 30, 1, __Value)
#define SET_TXBUFFER_DESC_ADD_LOW(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 0, 32, __Value)
#define GET_TXBUFFER_DESC_LEN(_pTxDesc) \
LE_BITS_TO_4BYTE(_pTxDesc + 0x00, 0, 16)
#define GET_TXBUFFER_DESC_ADD_HIGH(_pTxDesc) \
LE_BITS_TO_4BYTE(_pTxDesc + 0x00, 22, 8)
#define GET_TXBUFFER_DESC_LS(_pTxDesc) \
LE_BITS_TO_4BYTE(_pTxDesc + 0x00, 30, 1)
#define GET_TXBUFFER_DESC_ADD_LOW(_pTxDesc) \
LE_BITS_TO_4BYTE(_pTxDesc + 0x04, 0, 32)
/* PCIE_SEQ Info */
#define SET_PCIE_SEQ_INFO_0(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 0, 15, __value)
#define SET_PCIE_SEQ_INFO_0_VALID(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 15, 1, __value)
#define SET_PCIE_SEQ_INFO_1(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 16, 15, __value)
#define SET_PCIE_SEQ_INFO_1_VALID(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 31, 1, __value)
#define SET_PCIE_SEQ_INFO_2(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 0, 15, __value)
#define SET_PCIE_SEQ_INFO_2_VALID(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 15, 1, __value)
#define SET_PCIE_SEQ_INFO_3(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 16, 15, __value)
#define SET_PCIE_SEQ_INFO_3_VALID(__seq_info, __value) \
SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 31, 1, __value)
/* PCIE_SEQ Info */
#define GET_PCIE_SEQ_INFO_0(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 0, 15)
#define GET_PCIE_SEQ_INFO_0_VALID(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 15, 1)
#define GET_PCIE_SEQ_INFO_1(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 16, 15)
#define GET_PCIE_SEQ_INFO_1_VALID(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 31, 1)
#define GET_PCIE_SEQ_INFO_2(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 0, 15)
#define GET_PCIE_SEQ_INFO_2_VALID(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 15, 1)
#define GET_PCIE_SEQ_INFO_3(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 16, 15)
#define GET_PCIE_SEQ_INFO_3_VALID(__seq_info) \
LE_BITS_TO_4BYTE(__seq_info + 0x00, 31, 1)
/* Addr Info */
#define SET_ADDR_INFO_LEN(__addr_info, __value) \
SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 0, 16, __value)
#define SET_ADDR_INFO_NUM(__addr_info, __value) \
SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 16, 6, __value)
#define SET_ADDR_INFO_ADDR_HIGH(__addr_info, __value) \
SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 22, 8, __value)
#define SET_ADDR_INFO_LS(__addr_info, __value) \
SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 30, 1, __value)
#define SET_ADDR_INFO_MSDU_LS(__addr_info, __value) \
SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 31, 1, __value)
#define SET_ADDR_INFO_ADDR_LOW(__addr_info, __value) \
SET_BITS_TO_LE_4BYTE(__addr_info + 0x04, 0, 32, __value)
/* Addr Info */
#define GET_ADDR_INFO_LEN(__addr_info) \
LE_BITS_TO_4BYTE(__addr_info + 0x00, 0, 16)
#define GET_ADDR_INFO_NUM(__addr_info) \
LE_BITS_TO_4BYTE(__addr_info + 0x00, 16, 6)
#define GET_ADDR_INFO_ADDR_HIGH(__addr_info) \
LE_BITS_TO_4BYTE(__addr_info + 0x00, 22, 8)
#define GET_ADDR_INFO_LS(__addr_info) \
LE_BITS_TO_4BYTE(__addr_info + 0x00, 30, 1)
#define GET_ADDR_INFO_MSDU_LS(__addr_info) \
LE_BITS_TO_4BYTE(__addr_info + 0x00, 31, 1)
#define GET_ADDR_INFO_ADDR_LOW(__addr_info) \
LE_BITS_TO_4BYTE(__addr_info + 0x04, 0, 32)
#define RX_RP_PACKET_SIZE 4
/* RX BD */
#define SET_RX_BD_RXBUFFSIZE(__pRxBd, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 0, 14, __Value)
#define SET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 22, 8, __Value)
#define SET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxBd + 0x04, 0, 32, __Value)
/* RX RD INFO */
#define SET_RX_BD_INFO_TAG(rxdesc, value) \
SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 16, 13, value)
#define SET_RX_BD_INFO_FS(rxdesc, value) \
SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 15, 1, value)
#define SET_RX_BD_INFO_LS(rxdesc, value) \
SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 14, 1, value)
#define SET_RX_BD_INFO_HW_W_SIZE(rxdesc, value) \
SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 0, 14, value)
#define GET_RX_BD_INFO_TAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 13)
#define GET_RX_BD_INFO_FS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1)
#define GET_RX_BD_INFO_LS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1)
#define GET_RX_BD_INFO_HW_W_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14)
/* RX RP PACKET */
#define SET_RX_RP_PKT_POLLUTED(rppkt, value) \
SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 31, 1, value)
#define SET_RX_RP_PKT_PCIE_SEQ(rppkt, value) \
SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 16, 15, value)
#define SET_RX_RP_PKT_TX_STS(rppkt, value) \
SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 13, 3, value)
#define SET_RX_RP_PKT_QSEL(rppkt, value) \
SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 8, 5, value)
#define SET_RX_RP_PKT_MAC_ID(rppkt, value) \
SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 0, 8, value)
#define GET_RX_RP_PKT_POLLUTED(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 31, 1)
#define GET_RX_RP_PKT_PCIE_SEQ(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 16, 15)
#define GET_RX_RP_PKT_TX_STS(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 13, 3)
#define GET_RX_RP_PKT_QSEL(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 8, 5)
#define GET_RX_RP_PKT_MAC_ID(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 0, 8)
/* CONFIG_PHL_TXSC */
#define TID_0_QSEL 0
#define TID_1_QSEL 1
#define TID_2_QSEL 1
#define TID_3_QSEL 0
#define TID_4_QSEL 2
#define TID_5_QSEL 2
#define TID_6_QSEL 3
#define TID_7_QSEL 3
#define TID_0_IND 0
#define TID_1_IND 0
#define TID_2_IND 1
#define TID_3_IND 1
#define TID_4_IND 0
#define TID_5_IND 1
#define TID_6_IND 0
#define TID_7_IND 1
enum rxbd_mode_8852BE {
RXBD_MODE_PACKET = 0,
RXBD_MODE_SEPARATION = 1,
RXBD_MODE_MAX = 0xFF
};
struct bd_ram {
u8 sidx;
u8 max;
u8 min;
};
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/hal_trx_8852be.h
|
C
|
agpl-3.0
| 13,560
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8852BE_H_
#define _RTL8852BE_H_
#include "../../hal_headers.h"
/*provide IC-BUS's function declaration or definition to IC*/
#endif /* _RTL8852BE_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be.h
|
C
|
agpl-3.0
| 815
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8852BE_HAL_H_
#define _RTL8852BE_HAL_H_
/* rtl8852BE_halinit.c */
#define R_AX_HIMR0 0x01A0
#define B_AX_HALT_C2H_INT_EN BIT(21)
#define B_AX_RON_INT_EN BIT(20)
#define B_AX_PDNINT_EN BIT(19)
#define B_AX_SPSANA_OCP_INT_EN BIT(18)
#define B_AX_SPS_OCP_INT_EN BIT(17)
#define B_AX_BTON_STS_UPDATE_INT_EN BIT(16)
#define B_AX_GPIOF_INT_EN BIT(15)
#define B_AX_GPIOE_INT_EN BIT(14)
#define B_AX_GPIOD_INT_EN BIT(13)
#define B_AX_GPIOC_INT_EN BIT(12)
#define B_AX_GPIOB_INT_EN BIT(11)
#define B_AX_GPIOA_INT_EN BIT(10)
#define B_AX_GPIO9_INT_EN BIT(9)
#define B_AX_GPIO8_INT_EN BIT(8)
#define B_AX_GPIO7_INT_EN BIT(7)
#define B_AX_GPIO6_INT_EN BIT(6)
#define B_AX_GPIO5_INT_EN BIT(5)
#define B_AX_GPIO4_INT_EN BIT(4)
#define B_AX_GPIO3_INT_EN BIT(3)
#define B_AX_GPIO2_INT_EN BIT(2)
#define B_AX_GPIO1_INT_EN BIT(1)
#define B_AX_GPIO0_INT_EN BIT(0)
#define R_AX_HISR0 0x01A4
#define B_AX_HALT_C2H_INT BIT(21)
#define B_AX_RON_INT BIT(20)
#define B_AX_PDNINT BIT(19)
#define B_AX_SPSANA_OCP_INT BIT(18)
#define B_AX_SPS_OCP_INT BIT(17)
#define B_AX_BTON_STS_UPDATE_INT BIT(16)
#define B_AX_GPIOF_INT BIT(15)
#define B_AX_GPIOE_INT BIT(14)
#define B_AX_GPIOD_INT BIT(13)
#define B_AX_GPIOC_INT BIT(12)
#define B_AX_GPIOB_INT BIT(11)
#define B_AX_GPIOA_INT BIT(10)
#define B_AX_GPIO9_INT BIT(9)
#define B_AX_GPIO8_INT BIT(8)
#define B_AX_GPIO7_INT BIT(7)
#define B_AX_GPIO6_INT BIT(6)
#define B_AX_GPIO5_INT BIT(5)
#define B_AX_GPIO4_INT BIT(4)
#define B_AX_GPIO3_INT BIT(3)
#define B_AX_GPIO2_INT BIT(2)
#define B_AX_GPIO1_INT BIT(1)
#define B_AX_GPIO0_INT BIT(0)
#define R_AX_PCIE_HIMR00 0x10B0
#define B_AX_HC00ISR_IND_INT_EN BIT(27)
#define B_AX_HD1ISR_IND_INT_EN BIT(26)
#define B_AX_HD0ISR_IND_INT_EN BIT(25)
#define B_AX_HS0ISR_IND_INT_EN BIT(24)
#define B_AX_RETRAIN_INT_EN BIT(21)
#define B_AX_RPQBD_FULL_INT_EN BIT(20)
#define B_AX_RDU_INT_EN BIT(19)
#define B_AX_RXDMA_STUCK_INT_EN BIT(18)
#define B_AX_TXDMA_STUCK_INT_EN BIT(17)
#define B_AX_PCIE_HOTRST_INT_EN BIT(16)
#define B_AX_PCIE_FLR_INT_EN BIT(15)
#define B_AX_PCIE_PERST_INT_EN BIT(14)
#define B_AX_TXDMA_CH12_INT_EN BIT(13)
#define B_AX_TXDMA_CH9_INT_EN BIT(12)
#define B_AX_TXDMA_CH8_INT_EN BIT(11)
#define B_AX_TXDMA_ACH7_INT_EN BIT(10)
#define B_AX_TXDMA_ACH6_INT_EN BIT(9)
#define B_AX_TXDMA_ACH5_INT_EN BIT(8)
#define B_AX_TXDMA_ACH4_INT_EN BIT(7)
#define B_AX_TXDMA_ACH3_INT_EN BIT(6)
#define B_AX_TXDMA_ACH2_INT_EN BIT(5)
#define B_AX_TXDMA_ACH1_INT_EN BIT(4)
#define B_AX_TXDMA_ACH0_INT_EN BIT(3)
#define B_AX_RPQDMA_INT_EN BIT(2)
#define B_AX_RXP1DMA_INT_EN BIT(1)
#define B_AX_RXDMA_INT_EN BIT(0)
#define R_AX_PCIE_HISR00 0x10B4
#define B_AX_HC00ISR_IND_INT BIT(27)
#define B_AX_HD1ISR_IND_INT BIT(26)
#define B_AX_HD0ISR_IND_INT BIT(25)
#define B_AX_HS0ISR_IND_INT BIT(24)
#define B_AX_RETRAIN_INT BIT(21)
#define B_AX_RPQBD_FULL_INT BIT(20)
#define B_AX_RDU_INT BIT(19)
#define B_AX_RXDMA_STUCK_INT BIT(18)
#define B_AX_TXDMA_STUCK_INT BIT(17)
#define B_AX_PCIE_HOTRST_INT BIT(16)
#define B_AX_PCIE_FLR_INT BIT(15)
#define B_AX_PCIE_PERST_INT BIT(14)
#define B_AX_TXDMA_CH12_INT BIT(13)
#define B_AX_TXDMA_CH9_INT BIT(12)
#define B_AX_TXDMA_CH8_INT BIT(11)
#define B_AX_TXDMA_ACH7_INT BIT(10)
#define B_AX_TXDMA_ACH6_INT BIT(9)
#define B_AX_TXDMA_ACH5_INT BIT(8)
#define B_AX_TXDMA_ACH4_INT BIT(7)
#define B_AX_TXDMA_ACH3_INT BIT(6)
#define B_AX_TXDMA_ACH2_INT BIT(5)
#define B_AX_TXDMA_ACH1_INT BIT(4)
#define B_AX_TXDMA_ACH0_INT BIT(3)
#define B_AX_RPQDMA_INT BIT(2)
#define B_AX_RXP1DMA_INT BIT(1)
#define B_AX_RXDMA_INT BIT(0)
#define R_AX_PCIE_HIMR10 0x13B0
#define B_AX_HC10ISR_IND_INT_EN BIT(28)
#define B_AX_TXDMA_CH11_INT_EN BIT(12)
#define B_AX_TXDMA_CH10_INT_EN BIT(11)
#define R_AX_PCIE_HISR10 0x13B4
#define B_AX_HC10ISR_IND_INT BIT(28)
#define B_AX_TXDMA_CH11_INT BIT(12)
#define B_AX_TXDMA_CH10_INT BIT(11)
enum rtw_hal_status hal_get_efuse_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status hal_init_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
void hal_deinit_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status hal_start_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status hal_stop_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
#ifdef CONFIG_WOWLAN
enum rtw_hal_status hal_wow_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status hal_wow_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
#endif /* CONFIG_WOWLAN */
enum rtw_hal_status hal_mp_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal);
enum rtw_hal_status hal_mp_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal);
void hal_init_default_value_8852be(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg);
u32 hal_hci_cfg_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
struct rtw_ic_info *ic_info);
void init_hal_spec_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
void hal_enable_int_8852be(struct hal_info_t *hal);
void hal_disable_int_8852be(struct hal_info_t *hal);
bool hal_recognize_int_8852be(struct hal_info_t *hal);
void hal_clear_int_8852be(struct hal_info_t *hal);
void hal_clear_int_mask_8852be(struct hal_info_t *hal);
void hal_restore_int_8852be(struct hal_info_t *hal);
u32 hal_int_hdler_8852be(struct hal_info_t *hal);
void hal_rx_int_restore_8852be(struct hal_info_t *hal);
/* rtl8852BE_ops.c */
#endif /* _RTL8852BE_HAL_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be_hal.h
|
C
|
agpl-3.0
| 6,245
|
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852BE_HALINIT_C_
#include "../../hal_headers.h"
#include "../rtl8852b_hal.h"
#include "hal_trx_8852be.h"
static enum mac_ax_pcie_func_ctrl
_hal_set_each_pcicfg(enum rtw_pcie_bus_func_cap_t ctrl)
{
switch(ctrl) {
case RTW_PCIE_BUS_FUNC_DISABLE:
return MAC_AX_PCIE_DISABLE;
case RTW_PCIE_BUS_FUNC_ENABLE:
return MAC_AX_PCIE_ENABLE;
default:
return MAC_AX_PCIE_DEFAULT;
}
}
enum rtw_hal_status _hal_set_pcicfg_8852be(struct hal_info_t *hal_info)
{
struct mac_ax_pcie_cfgspc_param pcicfg;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
_os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
pcicfg.write = 1;
pcicfg.l0s_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l0s_ctrl);
pcicfg.l1_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l1_ctrl);
pcicfg.l1ss_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l1ss_ctrl);
pcicfg.wake_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.wake_ctrl);
pcicfg.crq_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.crq_ctrl);
pcicfg.clkdly_ctrl = hal_com->bus_cap.clkdly_ctrl;
pcicfg.l0sdly_ctrl = hal_com->bus_cap.l0sdly_ctrl;
pcicfg.l1dly_ctrl = hal_com->bus_cap.l1dly_ctrl;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : l0s/l1/l1ss/wake/crq/l0sdly/l1dly/clkdly = %#X/%#X/%#X/%#X/%#X/%#X/%#X/%#X \n",
__func__, pcicfg.l0s_ctrl, pcicfg.l1_ctrl, pcicfg.l1ss_ctrl, pcicfg.wake_ctrl,
pcicfg.crq_ctrl, pcicfg.l0sdly_ctrl, pcicfg.l1dly_ctrl, pcicfg.clkdly_ctrl);
hsts = rtw_hal_mac_set_pcicfg(hal_info, &pcicfg);
return hsts;
}
enum rtw_hal_status _hal_ltr_sw_init_state_8852be(struct hal_info_t *hal_info)
{
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_pcie_ltr_state state;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s :sw state = %u \n",__func__, hal_com->bus_cap.ltr_init_state);
if (hal_com->bus_cap.ltr_init_state > 0) {
state = hal_com->bus_cap.ltr_init_state;
hsts = rtw_hal_mac_ltr_sw_trigger(hal_info,state);
} else {
hsts = RTW_HAL_STATUS_SUCCESS;
}
return hsts;
}
enum rtw_hal_status _hal_ltr_set_pcie_8852be(struct hal_info_t *hal_info)
{
enum rtw_hal_status hsts = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct bus_cap_t *bus_cap = &hal_com->bus_cap;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s :idle_ctrl/idle_val/act_ctrl/act_val = %u/%#X/%u/%#X \n",
__func__, bus_cap->ltr_idle.ctrl,
bus_cap->ltr_idle.val, bus_cap->ltr_act.ctrl, bus_cap->ltr_act.val);
if (bus_cap->ltr_idle.ctrl || bus_cap->ltr_act.ctrl) {
hsts = rtw_hal_mac_ltr_set_pcie(hal_info, RTW_PCIE_BUS_FUNC_IGNORE,
bus_cap->ltr_idle.ctrl, bus_cap->ltr_idle.val,
bus_cap->ltr_act.ctrl, bus_cap->ltr_act.val);
}
return hsts;
}
static void _hal_aspm_hw_cfg(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
/* func */
hal_com->bus_hw_cap.l0s_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
hal_com->bus_hw_cap.l1_ctrl = RTW_PCIE_BUS_FUNC_ENABLE;
hal_com->bus_hw_cap.l1ss_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
hal_com->bus_hw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
hal_com->bus_hw_cap.crq_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
/*delay*/
hal_com->bus_hw_cap.l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_DEF;
hal_com->bus_hw_cap.l1dly_ctrl = MAC_AX_PCIE_L1DLY_DEF;
hal_com->bus_hw_cap.clkdly_ctrl = MAC_AX_PCIE_CLKDLY_DEF;
}
static void _hal_tx_ch_config_8852be(struct hal_info_t *hal)
{
struct mac_ax_txdma_ch_map *txch_map = (struct mac_ax_txdma_ch_map *)hal->txch_map;
txch_map->ch0 = MAC_AX_PCIE_ENABLE;
txch_map->ch1 = MAC_AX_PCIE_ENABLE;
txch_map->ch2 = MAC_AX_PCIE_ENABLE;
txch_map->ch3 = MAC_AX_PCIE_ENABLE;
txch_map->ch4 = MAC_AX_PCIE_DISABLE;
txch_map->ch5 = MAC_AX_PCIE_DISABLE;
txch_map->ch6 = MAC_AX_PCIE_DISABLE;
txch_map->ch7 = MAC_AX_PCIE_DISABLE;
txch_map->ch8 = MAC_AX_PCIE_ENABLE;
txch_map->ch9 = MAC_AX_PCIE_ENABLE;
txch_map->ch10 = MAC_AX_PCIE_DISABLE;
txch_map->ch11 = MAC_AX_PCIE_DISABLE;
txch_map->ch12 = MAC_AX_PCIE_ENABLE;
}
static void _hal_pre_init_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_52be)
{
struct mac_ax_trx_info *trx_info = &init_52be->trx_info;
struct mac_ax_intf_info *intf_info = &init_52be->intf_info;
struct mac_ax_host_rpr_cfg *rpr_cfg = (struct mac_ax_host_rpr_cfg *)hal_info->rpr_cfg;
void *txbd_buf = NULL;
void *rxbd_buf = NULL;
/* trx_info */
if (true == phl_com->dev_cap.tx_mu_ru)
trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
else
trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
if (hal_info->hal_com->dbcc_en == false)
trx_info->qta_mode = MAC_AX_QTA_SCC;
else
trx_info->qta_mode = MAC_AX_QTA_DBCC;
#ifdef RTW_WKARD_LAMODE
PHL_INFO("%s : la_mode %d\n", __func__, phl_com->dev_cap.la_mode);
if (phl_com->dev_cap.la_mode)
trx_info->qta_mode = MAC_AX_QTA_LAMODE;
#endif
if (phl_com->dev_cap.rpq_agg_num) {
rpr_cfg->agg_def = 0;
rpr_cfg->agg = phl_com->dev_cap.rpq_agg_num;
} else {
rpr_cfg->agg_def = 1;
}
rpr_cfg->tmr_def = 1;
rpr_cfg->txok_en = MAC_AX_FUNC_DEF;
rpr_cfg->rty_lmt_en = MAC_AX_FUNC_DEF;
rpr_cfg->lft_drop_en = MAC_AX_FUNC_DEF;
rpr_cfg->macid_drop_en = MAC_AX_FUNC_DEF;
trx_info->rpr_cfg = rpr_cfg;
/* intf_info */
txbd_buf = rtw_phl_get_txbd_buf(phl_com);
rxbd_buf = rtw_phl_get_rxbd_buf(phl_com);
intf_info->txbd_trunc_mode = MAC_AX_BD_TRUNC;
intf_info->rxbd_trunc_mode = MAC_AX_BD_TRUNC;
intf_info->rxbd_mode = MAC_AX_RXBD_PKT;
intf_info->tag_mode = MAC_AX_TAG_MULTI;
intf_info->tx_burst = MAC_AX_TX_BURST_DEF;
intf_info->rx_burst = MAC_AX_RX_BURST_DEF;
intf_info->wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_DEF;
intf_info->wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_DEF;
intf_info->multi_tag_num = MAC_AX_TAG_NUM_DEF;
intf_info->rx_sep_append_len = 0;
intf_info->txbd_buf = txbd_buf;
intf_info->rxbd_buf = rxbd_buf;
intf_info->skip_all = false;
intf_info->autok_en = MAC_AX_PCIE_DISABLE;
_hal_tx_ch_config_8852be(hal_info);
intf_info->txch_map = (struct mac_ax_txdma_ch_map *)hal_info->txch_map;
intf_info->lbc_en = MAC_AX_PCIE_DEFAULT;
intf_info->lbc_tmr = MAC_AX_LBC_TMR_DEF;
/* others */
init_52be->ic_name = "rtl8852be";
}
void init_hal_spec_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal)
{
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
struct rtw_hal_com_t *hal_com = hal->hal_com;
struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap;
init_hal_spec_8852b(phl_com, hal);
hal_spec->rx_bd_info_sz = RX_BD_INFO_SIZE;
hal_spec->rx_tag[0] = 0;
hal_spec->rx_tag[1] = 0;
bus_hw_cap->max_txbd_num = 0x3FF;
bus_hw_cap->max_rxbd_num = 0x3FF;
bus_hw_cap->max_rpbd_num = 0x3FF;
bus_hw_cap->max_wd_page_size = 128;
bus_hw_cap->wdb_size = 24;
bus_hw_cap->wdi_size = 24;
bus_hw_cap->txbd_len = 8;
bus_hw_cap->rxbd_len = 8;
bus_hw_cap->addr_info_size = 8;
bus_hw_cap->seq_info_size = 8;
#ifdef RTW_WKARD_BUSCAP_IN_HALSPEC
hal_spec->phyaddr_num = 9;
#endif
phl_com->dev_cap.hw_sup_flags |= HW_SUP_PCIE_PLFH;/*PCIe payload from host*/
_hal_aspm_hw_cfg(hal);
if (hal_com->cv == CAV) {
bus_hw_cap->ltr_sw_ctrl = true;
bus_hw_cap->ltr_hw_ctrl = false;
} else {
bus_hw_cap->ltr_sw_ctrl = false;
bus_hw_cap->ltr_hw_ctrl = true;
}
hal_com->dev_hw_cap.ps_cap.lps_pause_tx = true;
}
enum rtw_hal_status hal_get_efuse_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct hal_init_info_t init_52be;
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
_hal_pre_init_8852be(phl_com, hal_info, &init_52be);
return hal_get_efuse_8852b(phl_com, hal_info, &init_52be);
}
enum rtw_hal_status hal_init_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
void *drv = phlcom_to_drvpriv(phl_com);
u32 len = 0;
u8 txch_num = 0;
txch_num = rtw_hal_query_txch_num(hal_info);
len = sizeof(struct rtw_wp_rpt_stats) * txch_num;
hal_com->trx_stat.wp_rpt_stats = _os_mem_alloc(drv, len);
if (hal_com->trx_stat.wp_rpt_stats == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s: alloc txch_map failed\n", __func__);
goto error_trx_stats_wp_rpt;
}
hal_info->txch_map = _os_mem_alloc(drv,
sizeof(struct mac_ax_txdma_ch_map));
if (hal_info->txch_map == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s: alloc txch_map failed\n", __func__);
goto error_txch_map;
}
hal_info->rpr_cfg = _os_mem_alloc(drv,
sizeof(struct mac_ax_host_rpr_cfg));
if (hal_info->rpr_cfg == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s: alloc rpr_cfg failed\n", __func__);
goto error_rpr_cfg;
}
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
error_rpr_cfg:
_os_mem_free(drv,
hal_info->txch_map,
sizeof(struct mac_ax_txdma_ch_map));
error_txch_map:
_os_mem_free(drv,
hal_com->trx_stat.wp_rpt_stats,
sizeof(struct rtw_wp_rpt_stats) * txch_num);
error_trx_stats_wp_rpt:
return hal_status;
}
void hal_deinit_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
u8 txch_num = 0;
txch_num = rtw_hal_query_txch_num(hal_info);
_os_mem_free(phlcom_to_drvpriv(phl_com),
hal_info->hal_com->trx_stat.wp_rpt_stats,
sizeof(struct rtw_wp_rpt_stats) * txch_num);
_os_mem_free(phlcom_to_drvpriv(phl_com),
hal_info->txch_map,
sizeof(struct mac_ax_txdma_ch_map));
_os_mem_free(phlcom_to_drvpriv(phl_com),
hal_info->rpr_cfg,
sizeof(struct mac_ax_host_rpr_cfg));
}
enum rtw_hal_status hal_start_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct hal_init_info_t init_52be;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
_hal_pre_init_8852be(phl_com, hal_info, &init_52be);
hal_status = hal_start_8852b(phl_com, hal_info, &init_52be);
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
PHL_ERR("hal_init_8852b: status = %u\n",hal_status);
return hal_status;
}
hal_status = _hal_set_pcicfg_8852be(hal_info);
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
PHL_ERR("_hal_set_pcicfg_8852be: status = %u\n",hal_status);
return hal_status;
}
hal_status = _hal_ltr_set_pcie_8852be(hal_info);
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
PHL_ERR("_hal_ltr_set_pcie_8852be: status = %u\n",hal_status);
return hal_status;
}
hal_status = _hal_ltr_sw_init_state_8852be(hal_info);
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
PHL_ERR("_hal_ltr_sw_init_state_8852be: status = %u\n",hal_status);
return hal_status;
}
return hal_status;
}
enum rtw_hal_status hal_stop_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = hal_stop_8852b(phl_com, hal);
return hal_status;
}
#ifdef CONFIG_WOWLAN
enum rtw_hal_status
hal_wow_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_init_info_t init_52be;
struct mac_ax_trx_info *trx_info = &init_52be.trx_info;
FUNCIN_WSTS(hal_status);
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
if (true == phl_com->dev_cap.tx_mu_ru)
trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
else
trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
trx_info->qta_mode = MAC_AX_QTA_SCC;
/*
if (hal_info->hal_com->dbcc_en == false)
trx_info->qta_mode = MAC_AX_QTA_SCC;
else
trx_info->qta_mode = MAC_AX_QTA_DBCC;
*/
init_52be.ic_name = "rtl8852be";
hal_status = hal_wow_init_8852b(phl_com, hal_info, sta, &init_52be);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
enum rtw_hal_status
hal_wow_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_init_info_t init_52be;
struct mac_ax_trx_info *trx_info = &init_52be.trx_info;
FUNCIN_WSTS(hal_status);
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
if (true == phl_com->dev_cap.tx_mu_ru)
trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
else
trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
trx_info->qta_mode = MAC_AX_QTA_SCC;
/*
if (hal_info->hal_com->dbcc_en == false)
trx_info->qta_mode = MAC_AX_QTA_SCC;
else
trx_info->qta_mode = MAC_AX_QTA_DBCC;
*/
init_52be.ic_name = "rtl8852be";
hal_status = hal_wow_deinit_8852b(phl_com, hal_info, sta, &init_52be);
if (RTW_HAL_STATUS_SUCCESS != hal_status) {
PHL_ERR("hal_wow_deinit_8852be: status = %u\n", hal_status);
return hal_status;
}
if (RTW_HAL_STATUS_SUCCESS != _hal_set_pcicfg_8852be(hal_info))
PHL_ERR("_hal_set_pcicfg_8852be: status = %u\n", hal_status);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
#endif /* CONFIG_WOWLAN */
u32 hal_hci_cfg_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal, struct rtw_ic_info *ic_info)
{
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
hal_spec->cts2_thres_en = true;
hal_spec->cts2_thres = 1792;
hal_spec->txbd_multi_tag = 8;
#ifdef RTW_WKARD_TXBD_UPD_LMT
hal_spec->txbd_upd_lmt = true;
#else
hal_spec->txbd_upd_lmt = false;
#endif
return RTW_HAL_STATUS_SUCCESS;
}
void hal_init_default_value_8852be(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
init_default_value_8852b(hal);
hal_com->int_mask_default[0] = (u32)(
B_AX_RPQBD_FULL_INT_EN | /* RPQBD full */
B_AX_RDU_INT_EN | /* Rx Descriptor Unavailable */
#if 0
B_AX_RXDMA_STUCK_INT_EN | /* PCIE RX DMA Stuck */
B_AX_TXDMA_STUCK_INT_EN | /* PCIE TX DMA Stuck */
B_AX_PCIE_HOTRST_INT_EN | /* PCIE HOT Reset */
B_AX_PCIE_FLR_INT_EN | /* PCIE FLR */
B_AX_PCIE_PERST_INT_EN | /* PCIE PERST */
#endif
B_AX_RPQDMA_INT_EN | /* RPQ DMA OK */
B_AX_RXDMA_INT_EN | /* RXQ (Packet mode or Part2) DMA OK */
B_AX_HS0ISR_IND_INT_EN | /* FW C2H*/
B_AX_HD0ISR_IND_INT_EN | /* watchdog timer*/
#if 0
B_AX_TXDMA_CH12_INT_EN | /* FWCMDQ */
B_AX_TXDMA_CH9_INT_EN | /* */
B_AX_TXDMA_CH8_INT_EN | /* */
B_AX_TXDMA_ACH7_INT_EN | /* */
B_AX_TXDMA_ACH6_INT_EN | /* */
B_AX_TXDMA_ACH5_INT_EN | /* */
B_AX_TXDMA_ACH4_INT_EN | /* */
B_AX_TXDMA_ACH3_INT_EN | /* */
B_AX_TXDMA_ACH2_INT_EN | /* */
B_AX_TXDMA_ACH1_INT_EN | /* */
B_AX_TXDMA_ACH0_INT_EN | /* */
#endif
0);
hal_com->int_mask_default[1] = (u32)(
#if 0
B_AX_TXDMA_CH11_INT |
B_AX_TXDMA_CH10_INT |
#endif
0);
hal_com->intr.halt_c2h_int.val_default = (u32)(
(cfg->halt_c2h_en == 1 ? B_AX_HALT_C2H_INT_EN : 0) |
0);
hal_com->intr.watchdog_timer_int.val_default = (u32)(
(cfg->wdt_en == 1 ? B_AX_WDT_PTFM_INT_EN : 0) |
0);
hal_com->int_mask[0] = hal_com->int_mask_default[0];
hal_com->int_mask[1] = hal_com->int_mask_default[1];
hal_com->intr.halt_c2h_int.val_mask = hal_com->intr.halt_c2h_int.val_default;
hal_com->intr.watchdog_timer_int.val_mask = hal_com->intr.watchdog_timer_int.val_default;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %08X, %08X, %08x, %08x\n", __func__,
hal_com->int_mask[0], hal_com->int_mask[1], hal_com->intr.halt_c2h_int.val_mask,
hal_com->intr.watchdog_timer_int.val_mask );
}
void hal_enable_int_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1]);
hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask);
hal_write32(hal_com, R_AX_HD0IMR, hal_com->intr.watchdog_timer_int.val_mask);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : \n%04X : %08X\n%04X : %08X\n%04X : %08X\n%04X : %08X\n",
__func__,
R_AX_PCIE_HIMR00, hal_read32(hal_com, R_AX_PCIE_HIMR00),
R_AX_PCIE_HIMR10, hal_read32(hal_com, R_AX_PCIE_HIMR10),
R_AX_HIMR0, hal_read32(hal_com, R_AX_HIMR0),
R_AX_HD0IMR, hal_read32(hal_com, R_AX_HD0IMR)
);
}
void hal_disable_int_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
hal_write32(hal_com, R_AX_HIMR0, 0);
}
bool hal_recognize_int_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
bool recognized = false;
#ifndef CONFIG_SYNC_INTERRUPT
/* disable imr before cleaning isr */
hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
hal_write32(hal_com, R_AX_HIMR0, 0);
#endif /* CONFIG_SYNC_INTERRUPT */
/* save isr for sw usage, handling interrupt */
/* isr00 */
hal_com->int_array[0] = hal_read32(hal_com, R_AX_PCIE_HISR00);
hal_com->int_array[0] &= hal_com->int_mask[0];
/* isr10 */
hal_com->int_array[1] = hal_read32(hal_com, R_AX_PCIE_HISR10);
hal_com->int_array[1] &= hal_com->int_mask[1];
/* isr0 */
hal_com->intr.halt_c2h_int.intr = hal_read32(hal_com, R_AX_HISR0);
hal_com->intr.halt_c2h_int.intr &= hal_com->intr.halt_c2h_int.val_mask;
/* isr0 */
if (hal_com->int_array[0] & B_AX_HD0ISR_IND_INT_EN) {
hal_com->intr.watchdog_timer_int.intr = B_AX_WDT_PTFM_INT;
hal_com->intr.watchdog_timer_int.intr &= hal_com->intr.watchdog_timer_int.val_mask;
/* clear int mask*/
hal_clear_int_mask_8852be(hal);
} else {
hal_com->intr.watchdog_timer_int.intr = 0;
}
if (hal_com->int_array[0] || hal_com->int_array[1] || hal_com->intr.halt_c2h_int.intr || hal_com->intr.watchdog_timer_int.intr)
recognized = true;
if (hal_com->intr.halt_c2h_int.intr)
PHL_WARN("%s : halt c2h interrupt is recognized (0x%x).\n", __func__, hal_com->intr.halt_c2h_int.intr);
if (hal_com->intr.watchdog_timer_int.intr)
PHL_WARN("%s : watchdog timer is recognized (0x%x).\n", __func__, hal_com->intr.watchdog_timer_int.intr);
#ifndef CONFIG_SYNC_INTERRUPT
/* clear isr */
hal_write32(hal_com, R_AX_HISR0, hal_com->intr.halt_c2h_int.intr);
hal_write32(hal_com, R_AX_PCIE_HISR00, hal_com->int_array[0]);
hal_write32(hal_com, R_AX_PCIE_HISR10, hal_com->int_array[1]);
/* restore imr */
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0] & 0xFFFFFFFF);
hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1] & 0xFFFFFFFF);
hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask & 0xFFFFFFFF);
#endif /* CONFIG_SYNC_INTERRUPT */
return recognized;
}
void hal_clear_int_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
hal_write32(hal_com, R_AX_PCIE_HISR00, hal_com->int_array[0]);
hal_write32(hal_com, R_AX_PCIE_HISR10, hal_com->int_array[1]);
hal_write32(hal_com, R_AX_HISR0, hal_com->intr.halt_c2h_int.intr);
}
void hal_clear_int_mask_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
hal_com->int_mask[0] = 0;
hal_com->int_mask[1] = 0;
hal_com->intr.halt_c2h_int.val_mask = 0;
hal_com->intr.watchdog_timer_int.val_mask = 0;
}
void hal_restore_int_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0] & 0xFFFFFFFF);
hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1] & 0xFFFFFFFF);
hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask & 0xFFFFFFFF);
}
#define BIT_BCNDERR0_MSK BIT(16)
#define BIT_BCNDMAINT0_MSK BIT(20)
#define BIT_TXBCN0OK_MSK BIT(25)
#define BIT_TXBCN0ERR_MSK BIT(26)
static u32 hal_bcn_handler_8852be(struct hal_info_t *hal, u32 *handled)
{
u32 ret = 0;
struct rtw_hal_com_t *hal_com = hal->hal_com;
if (hal_com->int_array[0] & BIT_TXBCN0OK_MSK){
handled[0] |= BIT_TXBCN0OK_MSK;
ret = 1;
}
if (hal_com->int_array[0] & BIT_TXBCN0ERR_MSK){
handled[0] |= BIT_TXBCN0ERR_MSK;
ret = 1;
}
if (hal_com->int_array[0] & BIT_BCNDERR0_MSK){
handled[0] |= BIT_BCNDERR0_MSK;
ret = 1;
}
if (hal_com->int_array[0] & BIT_BCNDMAINT0_MSK){
handled[0] |= BIT_BCNDMAINT0_MSK;
ret = 1;
}
return ret;
}
static u32 hal_rx_handler_8852be(struct hal_info_t *hal, u32 *handled)
{
u32 ret = 0;
struct rtw_hal_com_t *hal_com = hal->hal_com;
static const u32 rx_handle_irq = (
B_AX_RXDMA_INT_EN |
B_AX_RPQDMA_INT_EN|
B_AX_RDU_INT_EN |
B_AX_RPQBD_FULL_INT_EN);
u32 handled0 = (hal_com->int_array[0] & rx_handle_irq);
if (handled0 == 0)
return ret;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ B4 : %08X (%08X)\n", handled0, hal_com->int_array[0]);
/* Disable RX interrupts, RX tasklet will enable them after processed RX */
hal_com->int_mask[0] &= ~rx_handle_irq;
#ifndef CONFIG_SYNC_INTERRUPT
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
#endif /* CONFIG_SYNC_INTERRUPT */
handled[0] |= handled0;
ret = 1;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ A4 : %08X (%08X)\n", handled0, hal_com->int_array[0]);
return ret;
}
static u32 hal_tx_handler_8852be(struct hal_info_t *hal, u32 *handled)
{
u32 ret = 0;
struct rtw_hal_com_t *hal_com = hal->hal_com;
u32 event0 = 0x0;
u32 event1 = 0x0;
event0 = hal_com->int_array[0] & (
B_AX_TXDMA_ACH0_INT |
B_AX_TXDMA_ACH1_INT |
B_AX_TXDMA_ACH2_INT |
B_AX_TXDMA_ACH3_INT |
B_AX_TXDMA_ACH4_INT |
B_AX_TXDMA_ACH5_INT |
B_AX_TXDMA_ACH6_INT |
B_AX_TXDMA_ACH7_INT |
B_AX_TXDMA_CH8_INT |
B_AX_TXDMA_CH9_INT |
B_AX_TXDMA_CH12_INT);
event1 = hal_com->int_array[1] & (
B_AX_TXDMA_CH10_INT |
B_AX_TXDMA_CH11_INT);
if(event0 != 0 || event1 != 0)
ret = 1;
handled[0] |= event0;
handled[1] |= event1;
return ret;
}
#define BIT_SETH2CDOK_MASK BIT(16)
static u32 hal_cmd_handler_8852be(struct hal_info_t *hal, u32 *handled)
{
u32 ret = 0;
struct rtw_hal_com_t *hal_com = hal->hal_com;
if (hal_com->int_array[3] & BIT_SETH2CDOK_MASK) {
handled[3] |= BIT_SETH2CDOK_MASK;
ret = 1;
}
return ret;
}
static u32 hal_halt_c2h_handler_8852be(struct hal_info_t *hal, u32 *handled)
{
u32 ret = 0;
#if 1
struct rtw_hal_com_t *hal_com = hal->hal_com;
if (hal_com->intr.halt_c2h_int.intr& B_AX_HALT_C2H_INT_EN) {
handled[0] |= B_AX_HALT_C2H_INT_EN;
ret = 1;
}
#endif
return ret;
}
static u32 hal_watchdog_timer_handler_8852be(struct hal_info_t *hal, u32 *handled)
{
u32 ret = 0;
#if 1
struct rtw_hal_com_t *hal_com = hal->hal_com;
if (hal_com->intr.watchdog_timer_int.intr& B_AX_WDT_PTFM_INT_EN) {
handled[1] |= B_AX_WDT_PTFM_INT_EN;
ret = 1;
}
#endif
return ret;
}
u32 hal_int_hdler_8852be(struct hal_info_t *hal)
{
u32 int_hdler_msk = 0x0;
struct rtw_hal_com_t *hal_com = hal->hal_com;
u32 handled[4] = {0};
u32 generalhandled[8] = {0};
/* <1> beacon related */
int_hdler_msk |= (hal_bcn_handler_8852be(hal, handled)<<0);
/* <2> Rx related */
int_hdler_msk |= (hal_rx_handler_8852be(hal, handled)<<1);
/* <3> Tx related */
int_hdler_msk |= (hal_tx_handler_8852be(hal, handled)<<2);
/* <4> Cmd related */
int_hdler_msk |= (hal_cmd_handler_8852be(hal, handled)<<3);
/*Start General interrupt type*/
/* <5> Halt C2H related */
int_hdler_msk |= (hal_halt_c2h_handler_8852be(hal, generalhandled)<<4);
/* <6> watchdog timer related */
int_hdler_msk |= (hal_watchdog_timer_handler_8852be(hal, generalhandled)<<5);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : int_hdler_msk = 0x%x\n", __func__, int_hdler_msk);
if ((hal_com->int_array[0] & (~handled[0]))
|| (hal_com->int_array[1] & (~handled[1]))
|| (hal_com->int_array[2] & (~handled[2]))
|| (hal_com->int_array[3] & (~handled[3]))) {
/*if (printk_ratelimit()) */
{
PHL_WARN("Unhandled ISR => %x, %x, %x, %x\nIMR : %08X\nISR : %08X\n",
(hal_com->int_array[0] & (~handled[0])),
(hal_com->int_array[1] & (~handled[1])),
(hal_com->int_array[2] & (~handled[2])),
(hal_com->int_array[3] & (~handled[3])),
hal_read32(hal_com, R_AX_PCIE_HIMR00),
hal_read32(hal_com, R_AX_PCIE_HISR00)
);
}
}
//General interrupt type not handled.
if ((hal_com->intr.halt_c2h_int.intr & (~generalhandled[0])) ||
(hal_com->intr.watchdog_timer_int.intr & (~generalhandled[1]))) {
/*if (printk_ratelimit()) */
{
PHL_WARN("Unhandled ISR => %x\nIMR : %08X\nISR : %08X,\n%x\nIMR : %08X\nISR : %08X\n",
(hal_com->intr.halt_c2h_int.intr & (~generalhandled[0])),
hal_read32(hal_com, R_AX_HIMR0),
hal_read32(hal_com, R_AX_HISR0),
(hal_com->intr.watchdog_timer_int.intr & (~generalhandled[1])),
hal_read32(hal_com, R_AX_HD0IMR),
hal_read32(hal_com, R_AX_HD0ISR));
}
}
return int_hdler_msk;
}
void hal_rx_int_restore_8852be(struct hal_info_t *hal)
{
struct rtw_hal_com_t *hal_com = hal->hal_com;
hal_com->int_mask[0] |= (B_AX_RXDMA_INT_EN | B_AX_RPQDMA_INT_EN |
B_AX_RDU_INT_EN | B_AX_RPQBD_FULL_INT_EN);
#ifndef CONFIG_SYNC_INTERRUPT
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : \n%04X : %08X\n%04X : %08X\n",
__func__,
R_AX_PCIE_HIMR00, hal_read32(hal_com, R_AX_PCIE_HIMR00),
R_AX_PCIE_HIMR10, hal_read32(hal_com, R_AX_PCIE_HIMR10)
);
#endif /* CONFIG_SYNC_INTERRUPT */
}
enum rtw_hal_status
hal_mp_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_init_info_t init_52be;
FUNCIN_WSTS(hal_status);
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
init_52be.ic_name = "rtl8852be";
hal_status = hal_mp_init_8852b(phl_com, hal_info, &init_52be);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
enum rtw_hal_status
hal_mp_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_init_info_t init_52be;
FUNCIN_WSTS(hal_status);
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
init_52be.ic_name = "rtl8852be";
hal_status = hal_mp_deinit_8852b(phl_com, hal_info, &init_52be);
if (RTW_HAL_STATUS_SUCCESS != hal_status) {
PHL_ERR("hal_mp_deinit_8852be: status = %u\n", hal_status);
return hal_status;
}
FUNCOUT_WSTS(hal_status);
return hal_status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be_halinit.c
|
C
|
agpl-3.0
| 26,714
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852BE_HALMAC_C_
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be_halmac.c
|
C
|
agpl-3.0
| 680
|
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852B_IO_C_
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be_io.c
|
C
|
agpl-3.0
| 682
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be_led.c
|
C
|
agpl-3.0
| 650
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852BE_OPS_C_
#include "../rtl8852b_hal.h"
#include "rtl8852be.h"
void hal_set_ops_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal)
{
struct hal_ops_t *ops = hal_get_ops(hal);
hal_set_ops_8852b(phl_com, hal);
ops->init_hal_spec = init_hal_spec_8852be;
ops->hal_get_efuse = hal_get_efuse_8852be;
ops->hal_init = hal_init_8852be;
ops->hal_deinit = hal_deinit_8852be;
ops->hal_start = hal_start_8852be;
ops->hal_stop = hal_stop_8852be;
#ifdef CONFIG_WOWLAN
ops->hal_wow_init = hal_wow_init_8852be;
ops->hal_wow_deinit = hal_wow_deinit_8852be;
#endif /* CONFIG_WOWLAN */
ops->hal_mp_init = hal_mp_init_8852be;
ops->hal_mp_deinit = hal_mp_deinit_8852be;
ops->hal_hci_configure = hal_hci_cfg_8852be;
ops->init_default_value = hal_init_default_value_8852be;
ops->enable_interrupt = hal_enable_int_8852be;
ops->disable_interrupt = hal_disable_int_8852be;
ops->recognize_interrupt = hal_recognize_int_8852be;
ops->clear_interrupt = hal_clear_int_8852be;
ops->interrupt_handler = hal_int_hdler_8852be;
ops->restore_interrupt = hal_restore_int_8852be;
ops->restore_rx_interrupt = hal_rx_int_restore_8852be;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/pci/rtl8852be_ops.c
|
C
|
agpl-3.0
| 1,802
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8852B_H_
#define _RTL8852B_H_
#include "../hal_headers.h"
/*to communicate with upper-hal*/
#ifdef CONFIG_PCI_HCI
void hal_set_ops_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
u32 hal_hook_trx_ops_8852be(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
#endif
#ifdef CONFIG_USB_HCI
void hal_set_ops_8852bu(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
u32 hal_hook_trx_ops_8852bu(struct hal_info_t *hal_info);
#endif
#ifdef CONFIG_SDIO_HCI
void hal_set_ops_8852bs(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
u32 hal_hook_trx_ops_8852bs(struct hal_info_t *hal_info);
#endif
#endif /* _RTL8852B_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b.h
|
C
|
agpl-3.0
| 1,338
|
EXTRA_CFLAGS += -DCONFIG_RTL8852B
IC_NAME := rtl8852b
ifeq ($(CONFIG_MP_INCLUDED), y)
### 8852B Default Enable VHT MP HW TX MODE ###
#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
#CONFIG_MP_VHT_HW_TX_MODE = y
endif
ifeq ($(CONFIG_PHL_ARCH), y)
HAL = phl/hal_g6
else
HAL = hal_g6
endif
ifeq ($(CONFIG_USB_HCI), y)
FILE_NAME = rtl8852bu
endif
ifeq ($(CONFIG_PCI_HCI), y)
FILE_NAME = rtl8852be
endif
ifeq ($(CONFIG_SDIO_HCI), y)
FILE_NAME = rtl8852bs
endif
_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(IC_NAME)_halinit.o \
$(HAL)/$(IC_NAME)/$(IC_NAME)_mac.o \
$(HAL)/$(IC_NAME)/$(IC_NAME)_cmd.o \
$(HAL)/$(IC_NAME)/$(IC_NAME)_phy.o \
$(HAL)/$(IC_NAME)/$(IC_NAME)_ops.o \
$(HAL)/$(IC_NAME)/hal_trx_8852b.o
_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_halinit.o \
$(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_halmac.o \
$(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_io.o \
$(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_led.o \
$(HAL)/$(IC_NAME)/$(HCI_NAME)/$(FILE_NAME)_ops.o
#ifeq ($(CONFIG_SDIO_HCI), y)
#_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/hal_trx_8852bs.o
#endif
ifeq ($(CONFIG_USB_HCI), y)
_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/hal_trx_8852bu.o
endif
ifeq ($(CONFIG_PCI_HCI), y)
_HAL_IC_FILES += $(HAL)/$(IC_NAME)/$(HCI_NAME)/hal_trx_8852be.o
endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b.mk
|
Makefile
|
agpl-3.0
| 1,304
|
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852B_CMD_C_
#include "../hal_headers.h"
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_cmd.c
|
C
|
agpl-3.0
| 711
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8852B_HAL_H_
#define _RTL8852B_HAL_H_
#include "../hal_headers.h"
/*usage under rtl8852b folder*/
#include "rtl8852b_spec.h"
#include "hal_trx_8852b.h"
#ifdef CONFIG_PCI_HCI
#include "pci/rtl8852be_hal.h"
#endif
#ifdef CONFIG_USB_HCI
#include "usb/rtl8852bu_hal.h"
#endif
#ifdef CONFIG_SDIO_HCI
#include "sdio/rtl8852bs_hal.h"
#endif
enum hw_stype_8852b {
EFUSE_HW_STYPE_NONE_8852B = 0,
EFUSE_HW_STYPE_VF1_CG_8852B = 0xe,
EFUSE_HW_STYPE_GENERAL_8852B = 0xf
};
/* rtl8852b_halinit.c */
void init_hal_spec_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
enum rtw_hal_status hal_cfg_fw_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
char *ic_name,
enum rtw_fw_type fw_type);
/* rtl8852b_ops.c */
void hal_set_ops_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
/*void hal_set_trx_ops_8852b(struct hal_info_t *hal);*/
void init_default_value_8852b(struct hal_info_t *hal);
enum rtw_hal_status hal_get_efuse_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
struct hal_init_info_t *init_info);
enum rtw_hal_status hal_start_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
struct hal_init_info_t *init_info);
enum rtw_hal_status hal_stop_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal);
#ifdef CONFIG_WOWLAN
enum rtw_hal_status
hal_wow_init_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta,
struct hal_init_info_t *init_info);
enum rtw_hal_status
hal_wow_deinit_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta,
struct hal_init_info_t *init_info);
#endif /* CONFIG_WOWLAN */
#ifdef RTW_PHL_BCN
enum rtw_hal_status hal_config_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
enum rtw_hal_status hal_update_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
#endif
enum rtw_hal_status
hal_mp_init_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info);
enum rtw_hal_status
hal_mp_deinit_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info);
#endif /* _RTL8852B_HAL_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_hal.h
|
C
|
agpl-3.0
| 3,015
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852B_HALINIT_C_
#include "../hal_headers.h"
#include "../hal_api.h"
#include "rtl8852b_hal.h"
void init_hal_spec_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal)
{
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
struct rtw_hal_com_t *hal_com = hal->hal_com;
struct protocol_cap_t *hw_proto_cap = hal_com->proto_hw_cap;
hal_spec->ic_name = "rtl8852b";
hal_spec->macid_num = hal_mac_get_macid_num(hal);
/* hal_spec->sec_cam_ent_num follow halmac setting */
hal_spec->sec_cap = SEC_CAP_CHK_BMC;
hal_spec->rfpath_num_2g = 2;
hal_spec->rfpath_num_5g = 2;
hal_spec->rf_reg_path_num = 2;
hal_com->rfpath_rx_num = 2;
hal_com->rfpath_tx_num = 2;
hal_com->phy_hw_cap[0].rx_num = 2;
hal_com->phy_hw_cap[0].tx_num = 2;
hal_com->phy_hw_cap[1].rx_num = 2;
hal_com->phy_hw_cap[1].tx_num = 2;
hal_com->phy_hw_cap[0].hw_rts_time_th = 0;
hal_com->phy_hw_cap[1].hw_rts_time_th = 0;
hal_com->phy_hw_cap[0].hw_rts_len_th = 0;
hal_com->phy_hw_cap[1].hw_rts_len_th = 0;
hal_spec->max_tx_cnt = 2;
hal_spec->tx_nss_num = 2;
hal_spec->rx_nss_num = 2;
hal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G | BAND_CAP_6G;
hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M;
hal_spec->port_num = 5;
hal_spec->wmm_num = 2;
hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N |
PROTO_CAP_11AC | PROTO_CAP_11AX;
hal_spec->wl_func = 0
| WL_FUNC_P2P
| WL_FUNC_MIRACAST
| WL_FUNC_TDLS
;
hal_spec->max_csi_buf_su_nr = 2;
hal_spec->max_csi_buf_mu_nr = 6;
hal_spec->max_bf_ent_nr = 16;
hal_spec->max_su_sta_nr = 16;
hal_spec->max_mu_sta_nr = 6;
#ifdef RTW_WKARD_PHY_CAP
/* HE */
hw_proto_cap[0].he_su_bfme = 1;
hw_proto_cap[0].he_su_bfmr = 1;
hw_proto_cap[0].he_mu_bfme = 1;
hw_proto_cap[0].he_mu_bfmr = 1;
hw_proto_cap[1].he_su_bfme = 1;
hw_proto_cap[1].he_su_bfmr = 1;
hw_proto_cap[1].he_mu_bfme = 1;
hw_proto_cap[1].he_mu_bfmr = 0;
hw_proto_cap[0].trig_cqi_fb = 1;
hw_proto_cap[0].non_trig_cqi_fb = 1;
hw_proto_cap[1].trig_cqi_fb = 1;
hw_proto_cap[1].non_trig_cqi_fb = 1;
/* VHT */
hw_proto_cap[0].vht_su_bfmr = 1;
hw_proto_cap[0].vht_su_bfme = 1;
hw_proto_cap[0].vht_mu_bfmr = 1;
hw_proto_cap[0].vht_mu_bfme = 1;
hw_proto_cap[1].vht_su_bfmr = 1;
hw_proto_cap[1].vht_su_bfme = 1;
hw_proto_cap[1].vht_mu_bfmr = 0;
hw_proto_cap[1].vht_mu_bfme = 1;
/* HT */
hw_proto_cap[0].ht_su_bfmr = 1;
hw_proto_cap[0].ht_su_bfme = 1;
hw_proto_cap[1].ht_su_bfmr = 1;
hw_proto_cap[1].ht_su_bfme = 1;
/* STBC Tx*/
hw_proto_cap[0].stbc_tx = 1; /* Revmoe later */
hw_proto_cap[1].stbc_tx = 1; /* Revmoe later */
hw_proto_cap[0].stbc_ht_tx = 1;
hw_proto_cap[1].stbc_ht_tx = 1;
hw_proto_cap[0].stbc_vht_tx = 1;
hw_proto_cap[1].stbc_vht_tx = 1;
hw_proto_cap[0].stbc_he_tx = 1;
hw_proto_cap[1].stbc_he_tx = 1;
hw_proto_cap[0].stbc_tx_greater_80mhz = 0;
hw_proto_cap[1].stbc_tx_greater_80mhz = 0;
/* STBC Rx*/
hw_proto_cap[0].stbc_ht_rx = 1;
hw_proto_cap[1].stbc_ht_rx = 1;
hw_proto_cap[0].stbc_vht_rx = 1;
hw_proto_cap[1].stbc_vht_rx = 1;
hw_proto_cap[0].stbc_he_rx = 1;
hw_proto_cap[1].stbc_he_rx = 1;
hw_proto_cap[0].stbc_rx_greater_80mhz = 0;
hw_proto_cap[1].stbc_rx_greater_80mhz = 0;
#endif
/*get mac capability*/
phl_com->dev_cap.hw_sup_flags = HW_SUP_AMSDU |
HW_SUP_TCP_TX_CHKSUM |
HW_SUP_TCP_RX_CHKSUM |
HW_SUP_TXPKT_CONVR;
phl_com->dev_cap.hw_sup_flags |= HW_SUP_OFDMA | HW_SUP_CHAN_INFO;
phl_com->dev_cap.hw_sup_flags |= HW_SUP_TSSI | HW_SUP_TANK_K;
#ifdef RTW_WKARD_LAMODE
hal_com->dev_hw_cap.la_mode = true;/*TODO : get info from halbb*/
#endif
#ifdef CONFIG_DBCC_SUPPORT
if (phl_com->dev_cap.hw_sup_flags & HW_SUP_DBCC)
hal_com->dev_hw_cap.dbcc_sup = true;/*get info from efuse*/
#endif
hal_com->dev_hw_cap.hw_hdr_conv = true;
hal_com->dev_hw_cap.sta_ulru = RTW_HW_CAP_ULRU_ENABLE;
#ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
hal_com->dev_hw_cap.sta_ulru_2g40mhz = RTW_HW_CAP_ULRU_DISABLE;
#endif
hal_com->dev_hw_cap.tx_mu_ru = false;
#ifdef CONFIG_MCC_SUPPORT
hal_com->dev_hw_cap.mcc_sup = true;
#endif /* CONFIG_MCC_SUPPORT */
#ifdef CONFIG_PHL_TWT
/* wait for fw support sta twt */
hal_com->dev_hw_cap.twt_sup = 0;
#endif /* CONFIG_PHL_TWT */
hal_com->dev_hw_cap.ps_cap.ips_cap = PS_CAP_PWR_OFF;
hal_com->dev_hw_cap.ps_cap.ips_wow_cap = 0;
hal_com->dev_hw_cap.ps_cap.lps_cap =
PS_CAP_PWRON | PS_CAP_RF_OFF | PS_CAP_CLK_GATED | PS_CAP_PWR_GATED;
hal_com->dev_hw_cap.ps_cap.lps_wow_cap =
PS_CAP_PWRON | PS_CAP_RF_OFF | PS_CAP_CLK_GATED | PS_CAP_PWR_GATED;
hal_com->dev_hw_cap.hw_stype_cap = EFUSE_HW_STYPE_NONE_8852B;
hal_com->dev_hw_cap.wl_func_cap = EFUSE_WL_FUNC_NONE;
hal_com->dev_hw_cap.rpq_agg_num = 0;
}
void init_default_value_8852b(struct hal_info_t *hal)
{
}
u32 _hal_cfg_rom_fw_8852b(enum rtw_fw_type fw_type, struct rtw_fw_info_t *fw_info,
char *ic_name)
{
char *hal_phy_folder = FW_FILE_CONFIG_PATH;
char *filename_postfix = "";
switch (fw_type) {
case RTW_FW_NIC:
filename_postfix = FW_FILE_NIC_POSTFIX;
break;
case RTW_FW_WOWLAN:
filename_postfix = FW_FILE_WOWLAN_POSTFIX;
break;
case RTW_FW_SPIC:
filename_postfix = FW_FILE_SPIC_POSTFIX;
break;
case RTW_FW_AP:
filename_postfix = FW_FILE_AP_POSTFIX;
break;
default:
break;
}
_os_snprintf(fw_info->rom_path, MAX_PATH_LEN, "%s%s%s%s", hal_phy_folder,
ic_name, _os_path_sep, "rtl8852bfw_rom.bin");
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %s\n", __func__, fw_info->rom_path);
fw_info->rom_size = _os_read_file(fw_info->rom_path,
fw_info->rom_buff,
RTW_MAX_FW_SIZE);
if (!fw_info->rom_size)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
u32 _hal_cfg_intnal_fw_8852b(struct rtw_phl_com_t *phl_com,enum rtw_fw_type fw_type,struct rtw_fw_info_t *fw_info)
{
/* any related to fw from header can be defined here */
return RTW_HAL_STATUS_SUCCESS;
}
static u32 _hal_read_fw_8852b(enum rtw_fw_type fw_type,
u8 *tgt_buf, u32 *tgt_buf_size, char *ic_name)
{
char *hal_phy_folder = FW_FILE_CONFIG_PATH;
char *filename_postfix = "";
char path[256] = {0};
if (tgt_buf == NULL)
return RTW_HAL_STATUS_FAILURE;
switch (fw_type) {
case RTW_FW_NIC:
filename_postfix = FW_FILE_NIC_POSTFIX;
break;
case RTW_FW_WOWLAN:
filename_postfix = FW_FILE_WOWLAN_POSTFIX;
break;
case RTW_FW_SPIC:
filename_postfix = FW_FILE_SPIC_POSTFIX;
break;
case RTW_FW_AP:
filename_postfix = FW_FILE_AP_POSTFIX;
break;
default:
return RTW_HAL_STATUS_FAILURE;
}
_os_snprintf(path, MAX_PATH_LEN, "%s%s%s%s%s%s", hal_phy_folder,
ic_name, _os_path_sep, "rtl8852bfw", filename_postfix, ".bin");
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %s\n", __func__, path);
if (0 == *tgt_buf_size) {
*tgt_buf_size = _os_read_file(path, tgt_buf, RTW_MAX_FW_SIZE);
/* reading fw file failed */
if (0 == *tgt_buf_size)
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
static u32 _hal_cfg_extnal_fw_8852b(struct rtw_phl_com_t *phl_com,
enum rtw_fw_type fw_type, struct rtw_fw_info_t *fw_info, char *ic_name)
{
void *d = phlcom_to_drvpriv(phl_com);
u8 *tgt_buf = NULL;
u32 tgt_buf_size = 0;
switch (fw_type) {
case RTW_FW_NIC:
_hal_read_fw_8852b(RTW_FW_NIC, fw_info->buf,
&fw_info->buf_size, ic_name);
/* preload wowlan fw */
_hal_read_fw_8852b(RTW_FW_WOWLAN, fw_info->wow_buf,
&fw_info->wow_buf_size, ic_name);
/* target is still NIC */
tgt_buf = fw_info->buf;
tgt_buf_size = fw_info->buf_size;
break;
case RTW_FW_WOWLAN:
_hal_read_fw_8852b(RTW_FW_WOWLAN, fw_info->wow_buf,
&fw_info->wow_buf_size, ic_name);
tgt_buf = fw_info->wow_buf;
tgt_buf_size = fw_info->wow_buf_size;
break;
case RTW_FW_SPIC:
_hal_read_fw_8852b(RTW_FW_SPIC, fw_info->buf,
&fw_info->buf_size, ic_name);
tgt_buf = fw_info->buf;
tgt_buf_size = fw_info->buf_size;
break;
case RTW_FW_AP:
_hal_read_fw_8852b(RTW_FW_AP, fw_info->buf,
&fw_info->buf_size, ic_name);
tgt_buf = fw_info->buf;
tgt_buf_size = fw_info->buf_size;
break;
default:
return RTW_HAL_STATUS_FAILURE;
}
/* fw has been downloaded */
if (tgt_buf && (0 != tgt_buf_size)) {
_os_mem_cpy(d, fw_info->ram_buff, tgt_buf,
tgt_buf_size);
fw_info->ram_size = tgt_buf_size;
return RTW_HAL_STATUS_SUCCESS;
} else {
fw_info->ram_size = 0;
return _hal_read_fw_8852b(fw_type, fw_info->ram_buff,
&fw_info->ram_size, ic_name);
}
}
enum rtw_hal_status hal_cfg_fw_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
char *ic_name,
enum rtw_fw_type fw_type)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_fw_info_t *fw_info = &phl_com->fw_info;
struct rtw_fw_cap_t *fw_cap = &phl_com->dev_cap.fw_cap;
FUNCIN();
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : fw_src %d.\n", __func__,
fw_cap->fw_src);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : dlram_en %d.\n", __func__,
fw_cap->dlram_en);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : dlrom_en %d.\n", __func__,
fw_cap->dlrom_en);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : fw_type %d.\n", __func__,
fw_type);
fw_info->fw_en = false;
if (!fw_cap->dlram_en)
return hstatus;
/* Should handle fw src from header */
if (fw_cap->dlrom_en) {
if (RTW_HAL_STATUS_SUCCESS !=_hal_cfg_rom_fw_8852b(fw_type, fw_info,
ic_name))
goto init_fw_fail;
}
/* RAM */
if (fw_cap->fw_src == RTW_FW_SRC_EXTNAL) {
fw_info->fw_src = RTW_FW_SRC_EXTNAL;
if (RTW_HAL_STATUS_SUCCESS != _hal_cfg_extnal_fw_8852b(phl_com, fw_type,
fw_info, ic_name))
goto init_fw_fail;
} else if (fw_cap->fw_src == RTW_FW_SRC_INTNAL) {
fw_info->fw_src = RTW_FW_SRC_INTNAL;
if (RTW_HAL_STATUS_SUCCESS != _hal_cfg_intnal_fw_8852b(phl_com, fw_type,
fw_info))
goto init_fw_fail;
} else {
goto init_fw_fail;
}
fw_info->fw_type = fw_type;
fw_info->fw_en = true;
fw_info->dlram_en = fw_cap->dlram_en;
fw_info->dlrom_en = fw_cap->dlrom_en;
/* fw_en, dlram_en, dlrom_en, ram_buff, ram_size, rom_buff, rom_size are ready here. */
hstatus = RTW_HAL_STATUS_SUCCESS;
init_fw_fail:
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s : fw_en %d.\n", __func__, fw_info->fw_en);
return hstatus;
}
enum rtw_hal_status hal_get_efuse_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
struct hal_init_info_t *init_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
FUNCIN();
hal_status = rtw_hal_mac_hal_fast_init(phl_com, hal, init_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
goto hal_fast_init_fail;
rtw_hal_efuse_process(hal, init_info->ic_name);
hal_status = rtw_hal_mac_power_switch(phl_com, hal, 0);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
goto hal_power_off_fail;
FUNCOUT();
return RTW_HAL_STATUS_SUCCESS;
hal_power_off_fail:
hal_fast_init_fail:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "==> %s : hal get efuse fail\n", __func__);
return hal_status;
}
enum rtw_hal_status hal_start_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal,
struct hal_init_info_t *init_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct phy_cap_t *phy_cap = phl_com->phy_cap;
u8 val = 0;
/* Read phy parameter files */
rtw_hal_dl_all_para_file(phl_com, init_info->ic_name, hal);
hal_status = rtw_hal_mac_hal_init(phl_com, hal, init_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
goto hal_init_fail;
rtw_hal_set_rxfltr_by_mode(hal, HW_BAND_0, RX_FLTR_MODE_STA_NORMAL);
/* MAC Suggested : 11264 Byte */
rtw_hal_mac_set_rxfltr_mpdu_size(hal->hal_com, HW_BAND_0, 0x2c00);
rtw_hal_mac_set_hw_rts_th(hal, HW_BAND_0,
phy_cap[HW_BAND_0].hw_rts_time_th,
phy_cap[HW_BAND_0].hw_rts_len_th);
if (hal->hal_com->dbcc_en == true) {
rtw_hal_set_rxfltr_by_mode(hal, HW_BAND_1, RX_FLTR_MODE_STA_NORMAL);
rtw_hal_mac_set_rxfltr_mpdu_size(hal->hal_com, HW_BAND_1, 0x2c00);
rtw_hal_mac_set_hw_rts_th(hal, HW_BAND_1,
phy_cap[HW_BAND_1].hw_rts_time_th,
phy_cap[HW_BAND_1].hw_rts_len_th);
}
#ifdef CONFIG_BTCOEX
/* power on config for btc */
rtw_hal_btc_power_on_ntfy(hal);
#endif
/* EFUSE config */
rtw_hal_efuse_process(hal, init_info->ic_name);
rtw_hal_final_cap_decision(phl_com, hal);
/*[Pre-config BB/RF] BBRST / RFC reset */
rtw_hal_mac_enable_bb_rf(hal, 0);
rtw_hal_mac_enable_bb_rf(hal, 1);
/* load parameters or config mac, phy, btc, ... */
#ifdef USE_TRUE_PHY
rtw_hal_init_bb_reg(hal);
rtw_hal_init_rf_reg(phl_com, hal);
#endif
#ifdef CONFIG_BTCOEX
/* After mac/bb/rf initialized, set btc config */
rtw_hal_btc_init_coex_cfg_ntfy(hal);
#endif
/* start watchdog/dm */
rtw_hal_bb_dm_init(hal);
rtw_hal_rf_dm_init(hal);
hal_status = rtw_hal_mac_get_append_fcs(hal, &val);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
goto hal_init_fail;
else
phl_com->append_fcs = val;
hal_status = rtw_hal_mac_get_acpt_icv_err(hal, &val);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
goto hal_init_fail;
else
phl_com->append_fcs = val;
#ifdef RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
rtw_hal_mac_config_hw_mgnt_sec(hal, false);
#endif
PHL_INFO("==> Default ENABLE RX_PPDU_STS for Band0\n");
/* Enable PPDU STS in default for BAND-0 for phy status */
hal->hal_com->band[HW_BAND_0].ppdu_sts_appen_info = HAL_PPDU_MAC_INFO | HAL_PPDU_PLCP | HAL_PPDU_RX_CNT;
hal->hal_com->band[HW_BAND_0].ppdu_sts_filter = (HAL_PPDU_HAS_CRC_OK | HAL_PPDU_HAS_A1M);
rtw_hal_mac_ppdu_stat_cfg(
hal, HW_BAND_0, true,
hal->hal_com->band[HW_BAND_0].ppdu_sts_appen_info,
hal->hal_com->band[HW_BAND_0].ppdu_sts_filter);
phl_com->ppdu_sts_info.en_ppdu_sts[HW_BAND_0] = true;
/*TODO Enable PPDU STS in default for BAND-1 for phy status */
hal_status = rtw_hal_hdr_conv_cfg(hal, phl_com->dev_cap.hw_hdr_conv);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
goto hal_init_fail;
/* Enable FW basic logs */
hal_fw_en_basic_log(hal->hal_com);
return RTW_HAL_STATUS_SUCCESS;
hal_init_fail:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "==> %s : hal init fail\n", __func__);
return hal_status;
}
enum rtw_hal_status hal_stop_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#ifdef CONFIG_BTCOEX
/* power off config for btc */
rtw_hal_btc_power_off_ntfy(hal);
#endif
hal_status = rtw_hal_mac_hal_deinit(phl_com, hal);
rtw_hal_bb_dm_deinit(phl_com, hal);
return hal_status;
}
#ifdef CONFIG_WOWLAN
enum rtw_hal_status
hal_wow_init_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta,
struct hal_init_info_t *init_info)
{
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_WOWLAN);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
hal_status = rtw_hal_redownload_fw(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
hal_status = rtw_hal_update_sta_entry(hal_info, sta, true);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: update sta entry fail(%d)!!\n", __func__, hal_status);
goto exit;
}
#ifdef RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
rtw_hal_mac_config_hw_mgnt_sec(hal_info, true);
#endif
exit:
return hal_status;
}
enum rtw_hal_status
hal_wow_deinit_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info, struct rtw_phl_stainfo_t *sta,
struct hal_init_info_t *init_info)
{
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
/* AOAC Report */
hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_NIC);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
hal_status = rtw_hal_redownload_fw(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
hal_status = rtw_hal_update_sta_entry(hal_info, sta, true);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: update sta entry fail(%d)!!\n", __func__, hal_status);
goto exit;
}
/* To Do : Recover RA ? */
#ifdef RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
rtw_hal_mac_config_hw_mgnt_sec(hal_info, false);
#endif
exit:
return hal_status;
}
#endif /* CONFIG_WOWLAN */
#ifdef RTW_PHL_BCN /* fill 8852b bcn ops */
enum rtw_hal_status hal_config_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry)
{
if(hal_mac_ax_config_beacon(hal, bcn_entry) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status hal_update_beacon_8852b(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry)
{
if(hal_mac_ax_send_beacon(hal, bcn_entry) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#endif /* RTW_PHL_BCN */
enum rtw_hal_status
hal_mp_init_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info)
{
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_NIC);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
hal_status = rtw_hal_redownload_fw(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
exit:
return hal_status;
}
enum rtw_hal_status
hal_mp_deinit_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info)
{
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
hal_status = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, RTW_FW_NIC);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: cfg fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
hal_status = rtw_hal_redownload_fw(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s: redownload fw fail(%d)!!\n", __func__, hal_status);
goto exit;
}
exit:
return hal_status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_halinit.c
|
C
|
agpl-3.0
| 19,021
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852B_MAC_C_
#include "../hal_headers.h"
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_mac.c
|
C
|
agpl-3.0
| 704
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852B_OPS_C_
#include "../hal_headers.h"
#include "rtl8852b_hal.h"
static void read_chip_version_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal)
{
hal_mac_get_hwinfo(hal, &(phl_com->hal_spec));
}
/*******************temp common IO APIs *******************/
extern u32 hal_read_macreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask);
extern void hal_write_macreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask, u32 data);
extern u32 hal_read_bbreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask);
extern void hal_write_bbreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask, u32 data);
extern u32 hal_read_rfreg(struct hal_info_t *hal,
enum rf_path path, u32 offset, u32 bit_mask);
extern void hal_write_rfreg(struct hal_info_t *hal,
enum rf_path path, u32 offset, u32 bit_mask, u32 data);
void hal_set_ops_8852b(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal)
{
struct hal_ops_t *ops = hal_get_ops(hal);
/*** initialize section ***/
ops->read_chip_version = read_chip_version_8852b;
ops->hal_cfg_fw = hal_cfg_fw_8852b;
ops->read_macreg = hal_read_macreg;
ops->write_macreg = hal_write_macreg;
ops->read_bbreg = hal_read_bbreg;
ops->write_bbreg = hal_write_bbreg;
ops->read_rfreg = hal_read_rfreg;
ops->write_rfreg = hal_write_rfreg;
#ifdef RTW_PHL_BCN
ops->cfg_bcn = hal_config_beacon_8852b;
ops->upt_bcn = hal_update_beacon_8852b;
#endif
ops->pkt_ofld = rtw_hal_mac_pkt_ofld;
ops->pkt_update_ids = rtw_hal_mac_pkt_update_ids;
}
#if 0
void hal_set_trx_ops_8852b(struct hal_info_t *hal)
{
struct hal_trx_ops_t *ops = hal_get_trx_ops(hal);
ops->get_txdesc_len = get_txdesc_len_8852b;
ops->fill_txdesc_h2c = fill_txdesc_h2c_8852b;
ops->fill_txdesc_fwdl = fill_txdesc_fwdl_8852b;
ops->fill_txdesc_pkt = fill_txdesc_pkt_8852b;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_ops.c
|
C
|
agpl-3.0
| 2,473
|
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _RTL8852B_PHY_C_
#include "../hal_headers.h"
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_phy.c
|
C
|
agpl-3.0
| 710
|
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8852B_PHY_H__
#define __RTL8852B_PHY_H__
/* rtl8852b_phy.c */
#endif /*__RTL8852B_PHY_H__*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_phy.h
|
C
|
agpl-3.0
| 763
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8852B_SPEC_H__
#define __RTL8852B_SPEC_H__
#endif /* __RTL8852B_SPEC_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/rtl8852b/rtl8852b_spec.h
|
C
|
agpl-3.0
| 740
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MODULE_C_
#ifdef CONFIG_HAL_TEST_SUITE
#endif /*ifdef CONFIG_HAL_TEST_SUITE*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/hal_test_module.c
|
C
|
agpl-3.0
| 746
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#include "hal_test_mp_api.h"
#ifdef CONFIG_HAL_TEST_MP
void rtw_hal_mp_cfg(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
if (true == phl_is_mp_mode(phl_com))
hal_ops->hal_mp_init(phl_com, hal_info);
else
hal_ops->hal_mp_deinit(phl_com, hal_info);
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp.c
|
C
|
agpl-3.0
| 1,148
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_TEST_MP_H_
#define _HAL_TEST_MP_H_
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_cal_trigger(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_cal_set_capability(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_cal_get_capability(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_cal_get_tssi_de(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_cal_set_tssi_de(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_cal_get_txpwr_final_abs(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_cal_trigger_dpk_tracking(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_set_tssi_avg(
struct mp_context *mp, struct mp_cal_arg *arg);
/* PSD */
enum rtw_hal_status rtw_hal_mp_psd_init(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_psd_restore(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_psd_get_point_data(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_psd_query(
struct mp_context *mp, struct mp_cal_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_start_dut(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_get_dev_info(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_set_phy_idx(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_get_bw_mode(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_set_trx_path(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_reset_phy_cnt(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_config_reset_mac_cnt(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_config_reset_drv_cnt(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_config_set_modulation(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_get_modulation(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_set_rate(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_get_mac_addr(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_set_mac_addr(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_set_ch_bw(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_config_swith_btc_path(
struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_trigger_fw_conflict(struct mp_context *mp, struct mp_config_arg *arg);
enum rtw_hal_status rtw_hal_mp_ic_hw_setting_init(
struct mp_context *mp);
/* WIFI EFUSE */
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_read(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_write(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_update(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_reload(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_offset_mask(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_usage(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_log_size(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_size(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_get_avl_size(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_get_shadowmap_from_val(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_autoload_status(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_shadow2buf(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_file_map_load(
struct mp_context *mp, char *pfilepath);
enum rtw_hal_status rtw_hal_mp_efuse_file_mask_load(
struct mp_context *mp, char *pfilepath);
enum rtw_hal_status rtw_hal_mp_efuse_get_info(
struct mp_context *mp, struct mp_efuse_arg *arg);
/* BT EFUSE */
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_read(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_write(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_update(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_reload(
struct mp_context *mp);
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_offset_mask(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_usage(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_log_size(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_size(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_avl_size(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow2buf(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_file_map_load(
struct mp_context *mp, char *pfilepath);
enum rtw_hal_status rtw_hal_mp_efuse_bt_file_mask_load(
struct mp_context *mp, char *pfilepath);
enum rtw_hal_status rtw_hal_mp_efuse_bt_read_hidden(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_bt_write_hidden(
struct mp_context *mp, struct mp_efuse_arg *arg);
enum rtw_hal_status rtw_hal_mp_efuse_read_phy_map(
struct mp_context *mp, struct mp_efuse_arg *arg, u8 type);
enum rtw_hal_status rtw_hal_mp_efuse_renew(
struct mp_context *mp, struct mp_efuse_arg *arg, u8 type);
enum rtw_hal_status rtw_hal_mp_reg_read_macreg(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_write_macreg(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_read_rfreg(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_write_rfreg(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_read_rf_syn(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_write_rf_syn(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_read_bbreg(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_write_bbreg(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_get_xcap(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_set_xcap(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_get_xsi(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_reg_set_xsi(
struct mp_context *mp, struct mp_reg_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_phy_crc_ok(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_phy_crc_err(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_mac_crc_ok(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_mac_crc_err(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_drv_crc_ok(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_drv_crc_err(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_get_rssi(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_get_rssi_ex(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_get_rxevm(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_trigger_rxevm(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_rx_set_gain_offset(
struct mp_context *mp, struct mp_rx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_plcp_gen(
struct mp_context *mp, struct mp_tx_arg *arg,struct mp_plcp_param_t *plcp_tx_struct);
enum rtw_hal_status rtw_hal_mp_tx_pmac_packet(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_pmac_continuous(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_pmac_fw_trigger(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_single_tone(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_carrier_suppression(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_phy_ok_cnt(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_mode_switch(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_tx_f2p_cmd(
struct mp_context *mp, struct mp_tx_arg *arg, struct mp_mac_ax_f2p_test_para *f2p_para_struct,
struct mp_mac_ax_f2p_wd *f2p_wd_struct, struct mp_mac_ax_f2p_tx_cmd *f2p_tx_cmd_struct);
void rtw_hal_mp_check_tx_idle(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_set_dpd_bypass(
struct mp_context *mp, struct mp_tx_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_read_table(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwrtrack(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_set_pwrtrack(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_idx(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr_idx(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_thermal(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_tssi(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_online_tssi_de(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_set_pwr_lmt_en(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_get_pwr_lmt_en(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi_offset(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref_cw(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_get_txinfo_pwr(
struct mp_context *mp, struct mp_txpwr_arg *arg);
enum rtw_hal_status rtw_hal_mp_txpwr_ctrl_rf_mode(
struct mp_context *mp, struct mp_txpwr_arg *arg);
void rtw_hal_mp_set_tx_pow_patten_sharp(
struct mp_context *mp, struct mp_txpwr_arg *arg);
void rtw_hal_mp_cfg(struct rtw_phl_com_t *phl_com, void *hal);
#endif /* CONFIG_HAL_TEST_MP */
#endif /* _HAL_TEST_MP_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_api.h
|
C
|
agpl-3.0
| 12,150
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_CAL_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_cal_trigger(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: cal_type = %d. \n",__FUNCTION__, arg->cal_type);
switch(arg->cal_type){
case MP_CAL_CHL_RFK:
PHL_INFO("MP_CAL_CHL_RFK: cur_phy_idx = %d.\n", mp->cur_phy);
hal_status = rtw_hal_rf_chl_rfk_trigger(mp->hal, mp->cur_phy, false);
break;
case MP_CAL_DACK:
PHL_INFO("MP_CAL_DACK: . \n");
hal_status = rtw_hal_rf_dack_trigger(mp->hal, false);
break;
case MP_CAL_IQK:
PHL_INFO("MP_CAL_IQK: cur_phy_idx = %d.\n", mp->cur_phy);
hal_status = rtw_hal_rf_iqk_trigger(mp->hal, mp->cur_phy, false);
break;
case MP_CAL_LCK:
PHL_INFO("MP_CAL_LCK \n");
hal_status = rtw_hal_rf_lck_trigger(mp->hal);
break;
case MP_CAL_DPK:
PHL_INFO("MP_CAL_DPK: cur_phy_idx = %d.\n", mp->cur_phy);
hal_status = rtw_hal_rf_dpk_trigger(mp->hal, mp->cur_phy, false);
break;
case MP_CAL_TSSI:
PHL_INFO("MP_CAL_TSSI: cur_phy_idx = %d.\n", mp->cur_phy);
hal_status = rtw_hal_rf_tssi_trigger(mp->hal, mp->cur_phy);
break;
case MP_CAL_GAPK:
PHL_INFO("MP_CAL_GAPK: cur_phy_idx = %d.\n", mp->cur_phy);
hal_status = rtw_hal_rf_gapk_trigger(mp->hal, mp->cur_phy, false);
break;
default:
PHL_INFO("Unknown calibration type.\n");
break;
}
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_cal_set_capability(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: cal_type = %d, enable = %d\n",
__FUNCTION__, arg->cal_type, arg->enable);
switch(arg->cal_type){
case MP_CAL_DACK:
PHL_INFO("MP_CAL_DACK.\n");
hal_status = rtw_hal_rf_set_capability_dack(mp->hal,
arg->enable);
break;
case MP_CAL_IQK:
PHL_INFO("MP_CAL_IQK.\n");
hal_status = rtw_hal_rf_set_capability_iqk(mp->hal,
arg->enable);
break;
case MP_CAL_DPK:
PHL_INFO("MP_CAL_DPK.\n");
hal_status = rtw_hal_rf_set_capability_dpk(mp->hal,
arg->enable);
break;
case MP_CAL_DPK_TRACK:
PHL_INFO("MP_CAL_DPK_TRACK.\n");
hal_status = rtw_hal_rf_set_capability_dpk_track(mp->hal,
arg->enable);
break;
case MP_CAL_TSSI:
PHL_INFO("MP_CAL_TSSI.\n");
hal_status = rtw_hal_rf_set_capability_tssi(mp->hal,
arg->enable);
break;
case MP_CAL_GAPK:
PHL_INFO("MP_CAL_GAPK.\n");
hal_status = rtw_hal_rf_set_capability_gapk(mp->hal,
arg->enable);
break;
default:
PHL_INFO("Unknown calibration type.\n");
break;
}
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_cal_get_capability(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: cal_type = %d. \n",__FUNCTION__,arg->cal_type);
switch(arg->cal_type){
case MP_CAL_DACK:
PHL_INFO("MP_CAL_DACK.\n");
hal_status = rtw_hal_rf_get_capability_dack(mp->hal,
&arg->enable);
break;
case MP_CAL_IQK:
PHL_INFO("MP_CAL_IQK.\n");
hal_status = rtw_hal_rf_get_capability_iqk(mp->hal,
&arg->enable);
break;
case MP_CAL_DPK:
PHL_INFO("MP_CAL_DPK.\n");
hal_status = rtw_hal_rf_get_capability_dpk(mp->hal,
&arg->enable);
break;
case MP_CAL_DPK_TRACK:
PHL_INFO("MP_CAL_DPK_TRACK.\n");
hal_status = rtw_hal_rf_get_capability_dpk_track(mp->hal,
&arg->enable);
break;
case MP_CAL_TSSI:
PHL_INFO("MP_CAL_TSSI.\n");
hal_status = rtw_hal_rf_get_capability_tssi(mp->hal,
&arg->enable);
break;
case MP_CAL_GAPK:
PHL_INFO("MP_CAL_GAPK.\n");
hal_status = rtw_hal_rf_get_capability_gapk(mp->hal,
&arg->enable);
break;
default:
PHL_INFO("Unknown calibration type.\n");
break;
}
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_cal_get_tssi_de(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
/*hal_status = rtw_hal_rf_get_tssi_de_value(mp, arg);*/
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_cal_set_tssi_de(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
/*hal_status = rtw_hal_rf_set_tssi_de_tx_verify(mp->hal, arg);*/
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_cal_get_txpwr_final_abs(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
/*hal_status = rtw_hal_rf_get_txpwr_final_abs(mp->hal, arg);*/
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_cal_trigger_dpk_tracking(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_trigger_dpk_tracking(mp->hal);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_set_tssi_avg(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_set_tssi_avg(mp->hal, mp->cur_phy, arg->xdbm);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
/* PSD */
enum rtw_hal_status rtw_hal_mp_psd_init(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_psd_init(mp->hal, mp->cur_phy, arg->path,
arg->iq_path, arg->avg, arg->fft);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_psd_restore(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_psd_restore(mp->hal, mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_psd_get_point_data(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_psd_get_point_data(mp->hal, mp->cur_phy,
arg->point, &arg->buf);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_psd_query(
struct mp_context *mp, struct mp_cal_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_psd_query(mp->hal, mp->cur_phy, arg->upoint,
arg->start_point, arg->stop_point, arg->outbuf);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_cal.c
|
C
|
agpl-3.0
| 7,813
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_CONFIG_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_config_start_dut(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__);
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_get_dev_info(
struct mp_context *mp, struct mp_config_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
arg->bustype = 0;
// arg->bustype = mp->phl_com->hci_type;
switch(hal_info->hal_com->chip_id) {
case CHIP_WIFI6_8852A:
arg->chipid = 0x8852a;
break;
case CHIP_WIFI6_8834A:
arg->chipid = 0x8834a;
break;
case CHIP_WIFI6_8852B:
arg->chipid = 0x8852b;
break;
case CHIP_WIFI6_MAX:
default:
PHL_INFO("Unknown chip: %d\n", hal_info->hal_com->chip_id);
return RTW_HAL_STATUS_FAILURE;
break;
}
PHL_INFO("%s: bustype = 0x%x, chipid = 0x%x\n",
__FUNCTION__, arg->bustype, arg->chipid);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_config_set_phy_idx(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: phy index = 0x%x\n", __FUNCTION__, arg->cur_phy);
mp->cur_phy = arg->cur_phy;
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_get_bw_mode(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
/* call hal api*/
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_set_trx_path(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct rtw_phl_com_t *phl_com = mp->phl_com;
u8 bb_rx_path, bb_tx_path = 0;
PHL_INFO("%s: ant_tx=0x%x, ant_rx=0x%x\n",
__FUNCTION__, arg->ant_tx, arg->ant_rx);
if((hal_info->hal_com->chip_id == CHIP_WIFI6_8852A) &&
(phl_com->phy_cap[mp->cur_phy].txss == 1)) {
if(arg->ant_tx != RF_PATH_B){
hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: Invaled TX path (%d)\n",
__FUNCTION__, arg->ant_tx);
goto exit;
}
}
bb_tx_path = arg->ant_tx; /* warning !!! it should be convert to enum bb_path, to be discussed */
bb_rx_path = arg->ant_rx; /* warning !!! it should be convert to enum bb_path, to be discussed */
hal_status = rtw_hal_bb_cfg_tx_path(hal_info->hal_com, bb_tx_path);
if(hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_INFO("%s: rtw_hal_bb_cfg_tx_path fail (%x)\n",
__FUNCTION__, hal_status);
goto exit;
}
hal_status = rtw_hal_bb_cfg_rx_path(hal_info->hal_com, bb_rx_path);
if(hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_INFO("%s: rtw_hal_bb_cfg_rx_path fail (%x)\n",
__FUNCTION__, hal_status);
goto exit;
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_reset_phy_cnt(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s !\n", __FUNCTION__);
hal_status = rtw_hal_bb_set_reset_cnt(mp->hal);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_reset_mac_cnt(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s !\n", __FUNCTION__);
hal_status = rtw_hal_mac_set_reset_rx_cnt(mp->hal, mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_reset_drv_cnt(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_trx_stat *trx_stat = &hal_com->trx_stat;
PHL_INFO("%s !\n", __FUNCTION__);
trx_stat->rx_ok_cnt = 0;
trx_stat->rx_err_cnt = 0;
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_set_modulation(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("set modulation = 0x%x\n", arg->modulation);
/* need assign arg->modulation to driver current wirelessmode */
PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__);
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_get_modulation(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__);
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_set_rate(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: NOT READY!!!\n", __FUNCTION__);
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_get_mac_addr(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 mac_addr[6] = {0x00, 0xE0, 0x4C, 0xbb, 0xbb, 0xbb};
PHL_INFO("%s: NOT READY!!! Assign fixed mac address.\n", __FUNCTION__);
_os_mem_cpy(mp->phl_com->drv_priv, arg->mac_addr, mac_addr, 6);
hal_status = RTW_HAL_STATUS_SUCCESS;
/* [TEMP] need assign driver mac addr to arg->mac_addr */
PHL_INFO("%s: get mac addr = %x:%x:%x:%x:%x:%x\n", __FUNCTION__,
arg->mac_addr[0],arg->mac_addr[1],arg->mac_addr[2],
arg->mac_addr[3],arg->mac_addr[4],arg->mac_addr[5]);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_set_mac_addr(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 mac_addr[6] = {0};
PHL_INFO("%s: NOT READY!!! ignore it.\n", __FUNCTION__);
_os_mem_cpy(mp->phl_com->drv_priv, mac_addr, arg->mac_addr, 6);
hal_status = RTW_HAL_STATUS_SUCCESS;
/* [TEMP] need assign arg->mac_addr to driver mac addr */
PHL_INFO("%s: set mac addr = %x:%x:%x:%x:%x:%x\n", __FUNCTION__,
mac_addr[0],mac_addr[1],mac_addr[2],
mac_addr[3],mac_addr[4],mac_addr[5]);
return hal_status;
}
u8 hal_mp_primary_channel_decision(u8 cent_ch, enum channel_width bw, u8 tx_sc)
{
u8 pri_ch = 0;
if(bw == CHANNEL_WIDTH_20){
pri_ch = cent_ch;
}
else if(bw == CHANNEL_WIDTH_40){
if(tx_sc == 1)
pri_ch = cent_ch + 2;
else if(tx_sc == 2)
pri_ch = cent_ch - 2;
else
pri_ch = cent_ch - 2; /* tx_sc == 0 */
}
else if(bw == CHANNEL_WIDTH_80){
if((tx_sc == 10) || (tx_sc == 4))
pri_ch = cent_ch - 6;
else if((tx_sc == 9) || (tx_sc == 1))
pri_ch = cent_ch + 2;
else if(tx_sc == 2)
pri_ch = cent_ch - 2;
else if(tx_sc == 3)
pri_ch = cent_ch + 6;
else
pri_ch = cent_ch - 6; /* tx_sc == 0 */
}
else{
PHL_WARN("%s: 80+80 and 160 not consider yet!\n", __FUNCTION__);
}
return pri_ch;
}
enum chan_offset
hal_mp_chan_offset_decision(u8 pri_ch, u8 cent_ch, enum channel_width bw)
{
enum chan_offset offset = CHAN_OFFSET_NO_EXT;
if(bw == CHANNEL_WIDTH_20){
offset = CHAN_OFFSET_NO_EXT;
}
else if(bw == CHANNEL_WIDTH_40){
if(cent_ch > pri_ch)
offset = CHAN_OFFSET_UPPER;
else
offset = CHAN_OFFSET_LOWER;
}
else if(bw == CHANNEL_WIDTH_80){
if(cent_ch > pri_ch){
if((cent_ch - pri_ch) == 6)
offset = CHAN_OFFSET_UPPER;
else
offset = CHAN_OFFSET_LOWER;
}
else{
if((pri_ch - cent_ch) == 6)
offset = CHAN_OFFSET_LOWER;
else
offset = CHAN_OFFSET_UPPER;
}
}
else{
PHL_WARN("%s: 80+80 and 160 not consider yet!\n", __FUNCTION__);
}
return offset;
}
enum rtw_hal_status rtw_hal_mp_config_set_ch_bw(
struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 pri_chan = 0;
u8 cent_ch = arg->channel;
u8 tx_sc = arg->sc_idx;
struct rtw_chan_def chdef = {0};
enum channel_width bw = arg->bandwidth;
PHL_INFO("%s: phy index = %d.\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: central channel = %d.\n", __FUNCTION__, arg->channel);
PHL_INFO("%s: bandwith = %d.\n", __FUNCTION__, arg->bandwidth);
PHL_INFO("%s: sc_idx = %d.\n", __FUNCTION__, arg->sc_idx);
pri_chan = hal_mp_primary_channel_decision(cent_ch, bw, tx_sc);
if(pri_chan == 0){
PHL_ERR("%s Invalid primary channel!\n", __FUNCTION__);
hal_status = RTW_HAL_STATUS_FAILURE;
goto exit;
}
chdef.chan = pri_chan;
chdef.band = rtw_phl_get_band_type(pri_chan);
chdef.bw = bw;
chdef.offset = hal_mp_chan_offset_decision(pri_chan, cent_ch, bw);
PHL_INFO("%s: pri_ch(%d) bw(%d) offset(%d)\n",
__FUNCTION__, chdef.chan, chdef.bw, chdef.offset);
hal_status = rtw_hal_set_ch_bw(mp->hal,mp->cur_phy,
&chdef, false);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Set ch bw fail!\n", __FUNCTION__);
goto exit;
}
hal_status = rtw_hal_bb_set_txsc(mp->hal, arg->sc_idx, mp->cur_phy);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Set txsc fail!\n", __FUNCTION__);
goto exit;
}
hal_status = rtw_hal_rf_chl_rfk_trigger(mp->hal, mp->cur_phy, false);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s chl rfk fail!\n", __FUNCTION__);
goto exit;
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_config_swith_btc_path(
struct mp_context *mp, struct mp_config_arg *arg)
{
mp->phl_com->dev_cap.btc_mode = arg->btc_mode;
mp->phl_com->dev_sw_cap.btc_mode = arg->btc_mode;
PHL_INFO("%s: btc_mode = %d.\n", __FUNCTION__, arg->btc_mode);
PHL_INFO("%s: phl_com->dev_sw_cap.btc_mode = %d.\n", __FUNCTION__, mp->phl_com->dev_sw_cap.btc_mode);
#ifdef CONFIG_BTCOEX
rtw_hal_btc_init_coex_cfg_ntfy(mp->hal);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_trigger_fw_conflict(struct mp_context *mp, struct mp_config_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: offset = %d.\n", __FUNCTION__, arg->offset);
hal_status = rtw_hal_mac_trigger_fw_conflict(mp->hal, arg->offset, arg->voltag);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_ic_hw_setting_init(struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_bb_ic_hw_setting_init(mp->hal);
return hal_status;
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_config.c
|
C
|
agpl-3.0
| 11,291
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_EFUSE_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
/* WIFI EFUSE */
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_read(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset);
hal_status = rtw_hal_efuse_shadow_read(mp->hal,
arg->io_type,
arg->io_offset,
&arg->io_value,
true);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_write(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset);
PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value);
hal_status = rtw_hal_efuse_shadow_write(mp->hal,
arg->io_type,
arg->io_offset,
arg->io_value,
true);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_update(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
/* PG limit part of logical efuse map in MP*/
hal_status = rtw_hal_efuse_shadow_update(mp->hal, true);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_shadow_reload(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
/* Reload limit part of logical efuse map in MP*/
hal_status = rtw_hal_efuse_shadow_load(mp->hal, true);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_offset_mask(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_offset_mask(mp->hal,
arg->io_offset,
(u8 *)&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: wifi offset mask = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_usage(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_usage(mp->hal, (u32 *)&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: wifi usage(bytes/percentage) = %d\n",
__FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_log_size(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_logical_size(mp->hal, &arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: wifi logical size = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_wifi_get_size(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_size(mp->hal, &arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: wifi size = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_get_avl_size(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_avl(mp->hal, &arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: available size = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_get_shadowmap_from_val(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_shadowmap_from(mp->hal, (u8*)&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: val=%d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_autoload_status(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_mac_check_efuse_autoload(mp->hal, &arg->autoload);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: autoload status = %d\n", __FUNCTION__, arg->autoload);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_shadow2buf(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
if (arg->poutbuf != NULL && arg->buf_len != 0)
hal_status = rtw_hal_efuse_shadow2buf(mp->hal, arg->poutbuf, arg->buf_len);
else
PHL_INFO("%s: buf null, buf len = %d\n", __FUNCTION__, arg->buf_len);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_file_map_load(
struct mp_context *mp, char *pfilepath)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
if (pfilepath)
hal_status = rtw_hal_efuse_file_map_load(mp->hal, pfilepath, true);
else
PHL_INFO("%s: pfilepath null\n", __FUNCTION__);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_file_mask_load(
struct mp_context *mp, char *pfilepath)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
if (pfilepath)
hal_status = rtw_hal_efuse_file_mask_load(mp->hal, pfilepath, true);
else
PHL_INFO("%s: pfilepath null\n", __FUNCTION__);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_get_info(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_get_info(hal_info->hal_com,
arg->io_type,
arg->poutbuf,
(u8)arg->buf_len);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
/* BT EFUSE */
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_read(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset);
hal_status = rtw_hal_efuse_bt_shadow_read(mp->hal,
arg->io_type,
arg->io_offset,
&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_write(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: offset = 0x%x\n", __FUNCTION__, arg->io_offset);
PHL_INFO("%s: value = 0x%x\n", __FUNCTION__, arg->io_value);
hal_status = rtw_hal_efuse_bt_shadow_write(mp->hal,
arg->io_type,
arg->io_offset,
arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_update(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_shadow_update(mp->hal);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow_reload(
struct mp_context *mp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_shadow_load(mp->hal);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_offset_mask(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_get_offset_mask(mp->hal,
arg->io_offset,
(u8 *)&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: bt offset mask = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_usage(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_get_usage(mp->hal, (u32 *)&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: bt usage(bytes/percentage) = %d\n",
__FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_log_size(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_get_logical_size(mp->hal, &arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: bt logical size = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_size(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_get_size(mp->hal, &arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: bt size = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_shadow2buf(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
if (arg->poutbuf != NULL && arg->buf_len != 0)
hal_status = rtw_hal_efuse_bt_shadow2buf(mp->hal, arg->poutbuf, arg->buf_len);
else
PHL_INFO("%s: buf null, buf len = %d\n", __FUNCTION__, arg->buf_len);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_get_avl_size(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_bt_get_avl(mp->hal, &arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: bt available size = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_file_map_load(
struct mp_context *mp, char *pfilepath)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
if (pfilepath)
hal_status = rtw_hal_efuse_bt_file_map_load(mp->hal, pfilepath);
else
PHL_INFO("%s: pfilepath null\n", __FUNCTION__);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_file_mask_load(
struct mp_context *mp, char *pfilepath)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
if (pfilepath)
hal_status = rtw_hal_efuse_bt_file_mask_load(mp->hal, pfilepath);
else
PHL_INFO("%s: pfilepath null\n", __FUNCTION__);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_read_hidden(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 value = (u8)arg->io_value;
PHL_INFO("%s\n", __FUNCTION__);
PHL_INFO("%s: offset = %x size = %x\n", __FUNCTION__, arg->io_offset, arg->io_type);
hal_status = rtw_hal_efuse_bt_read_hidden(mp->hal, arg->io_offset, arg->io_type,
&value);
arg->io_value = value;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: io_value = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_bt_write_hidden(
struct mp_context *mp, struct mp_efuse_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
PHL_INFO("%s: offset = %x value = %x\n", __FUNCTION__, arg->io_offset, arg->io_value);
hal_status = rtw_hal_efuse_bt_write_hidden(mp->hal,arg->io_offset,
(u8)arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_read_phy_map(
struct mp_context *mp, struct mp_efuse_arg *arg, u8 type)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
PHL_INFO("%s: offset = %x size = %x\n", __FUNCTION__, arg->io_offset, arg->buf_len);
hal_status = rtw_hal_efuse_read_phy_efuse(mp->hal, arg->io_offset, arg->buf_len,
arg->poutbuf, type);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_efuse_renew(
struct mp_context *mp, struct mp_efuse_arg *arg, u8 type)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_efuse_renew(mp->hal, type);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_efuse.c
|
C
|
agpl-3.0
| 14,575
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_REG_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_reg_read_macreg(
struct mp_context *mp, struct mp_reg_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
u32 convert_mask = 0x0;
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
switch(arg->io_type){
case 1:
convert_mask = 0x000000ff;
break;
case 2:
convert_mask = 0x0000ffff;
break;
case 4:
convert_mask = 0xffffffff;
break;
default:
PHL_INFO("io_type error\n");
return RTW_HAL_STATUS_FAILURE;
}
arg->io_value = hal_ops->read_macreg(mp->hal,
arg->io_offset,
convert_mask);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_reg_write_macreg(
struct mp_context *mp, struct mp_reg_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
u32 convert_mask = 0x0;
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
switch(arg->io_type){
case 1:
convert_mask = 0x000000ff;
break;
case 2:
convert_mask = 0x0000ffff;
break;
case 4:
convert_mask = 0xffffffff;
break;
default:
PHL_INFO("io_type error\n");
return RTW_HAL_STATUS_FAILURE;
}
hal_ops->write_macreg(mp->hal, arg->io_offset,
convert_mask, arg->io_value);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_reg_read_rfreg(
struct mp_context *mp, struct mp_reg_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
u32 convert_mask = 0x0;
PHL_INFO("%s: rfpath = %d\n", __FUNCTION__, arg->rfpath);
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %x\n", __FUNCTION__, arg->io_offset);
switch(arg->io_type){
case 1:
convert_mask = 0x000000ff;
break;
case 2:
convert_mask = 0x0000ffff;
break;
case 4:
convert_mask = 0xffffffff;
break;
default:
PHL_INFO("io_type error\n");
return RTW_HAL_STATUS_FAILURE;
}
arg->io_value = hal_ops->read_rfreg(mp->hal, arg->rfpath,
arg->io_offset, convert_mask);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_reg_write_rfreg(
struct mp_context *mp, struct mp_reg_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
u32 convert_mask = 0x0;
PHL_INFO("%s: rfpath = %d\n", __FUNCTION__, arg->rfpath);
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
switch(arg->io_type){
case 1:
convert_mask = 0x000000ff;
break;
case 2:
convert_mask = 0x0000ffff;
break;
case 4:
convert_mask = 0xffffffff;
break;
default:
PHL_INFO("io_type error\n");
return RTW_HAL_STATUS_FAILURE;
}
hal_ops->write_rfreg(mp->hal, arg->rfpath, arg->io_offset,
convert_mask, arg->io_value);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_reg_read_rf_syn(
struct mp_context *mp, struct mp_reg_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
PHL_INFO("[MP] call hal api: not ready\n");
hal_status = RTW_HAL_STATUS_SUCCESS;
/*
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
*/
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_reg_write_rf_syn(
struct mp_context *mp, struct mp_reg_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
PHL_INFO("[MP] call hal api: not ready\n");
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_reg_read_bbreg(
struct mp_context *mp, struct mp_reg_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
u32 convert_mask = 0x0;
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
switch(arg->io_type){
case 1:
convert_mask = 0x000000ff;
break;
case 2:
convert_mask = 0x0000ffff;
break;
case 4:
convert_mask = 0xffffffff;
break;
default:
PHL_INFO("io_type error\n");
return RTW_HAL_STATUS_FAILURE;
}
arg->io_value = hal_ops->read_bbreg(mp->hal,
arg->io_offset,
convert_mask);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_reg_write_bbreg(
struct mp_context *mp, struct mp_reg_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
u32 convert_mask = 0x0;
PHL_INFO("%s: io_type = %d\n", __FUNCTION__, arg->io_type);
PHL_INFO("%s: io_offset = %d\n", __FUNCTION__, arg->io_offset);
PHL_INFO("%s: io_value = %x\n", __FUNCTION__, arg->io_value);
switch(arg->io_type){
case 1:
convert_mask = 0x000000ff;
break;
case 2:
convert_mask = 0x0000ffff;
break;
case 4:
convert_mask = 0xffffffff;
break;
default:
PHL_INFO("io_type error\n");
return RTW_HAL_STATUS_FAILURE;
}
hal_ops->write_bbreg(mp->hal, arg->io_offset,
convert_mask, arg->io_value);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_reg_get_xcap(
struct mp_context *mp, struct mp_reg_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_mac_get_xcap(hal_info->hal_com, arg->sc_xo,
&arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: xcap capability = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_reg_set_xcap(
struct mp_context *mp, struct mp_reg_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: xcap capability = %d\n", __FUNCTION__, arg->io_value);
hal_status = rtw_hal_mac_set_xcap(hal_info->hal_com, arg->sc_xo,
arg->io_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_reg_get_xsi(
struct mp_context *mp, struct mp_reg_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_mac_get_xsi(hal_info->hal_com,
arg->xsi_offset,
&arg->xsi_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: xsi = %d\n", __FUNCTION__, arg->io_value);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_reg_set_xsi(
struct mp_context *mp, struct mp_reg_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: xsi = %d\n", __FUNCTION__, arg->io_value);
hal_status = rtw_hal_mac_set_xsi(hal_info->hal_com,
arg->xsi_offset,
arg->xsi_value);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_reg.c
|
C
|
agpl-3.0
| 8,524
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_RX_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_rx_phy_crc_ok(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
hal_status = rtw_hal_bb_get_rx_ok(mp->hal,
mp->cur_phy, &arg->rx_ok);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: crc ok count = %d\n", __FUNCTION__, arg->rx_ok);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_phy_crc_err(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
hal_status = rtw_hal_bb_get_rx_crc(mp->hal, mp->cur_phy, &arg->rx_err);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: crc error count = %d\n", __FUNCTION__, arg->rx_err);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_mac_crc_ok(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_mac_get_rx_cnt(mp->hal, mp->cur_phy, MAC_AX_RX_CRC_OK, &arg->rx_ok);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: mac crc OK count = %d\n", __FUNCTION__, arg->rx_ok);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_mac_crc_err(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_mac_get_rx_cnt(mp->hal, mp->cur_phy, MAC_AX_RX_CRC_FAIL, &arg->rx_err);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: mac crc error count = %d\n", __FUNCTION__, arg->rx_err);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_drv_crc_ok(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_trx_stat *trx_stat = &hal_com->trx_stat;
PHL_INFO("%s\n", __FUNCTION__);
arg->rx_ok = trx_stat->rx_ok_cnt;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: drv ok count = %d\n", __FUNCTION__, arg->rx_ok);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_drv_crc_err(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_trx_stat *trx_stat = &hal_com->trx_stat;
PHL_INFO("%s\n", __FUNCTION__);
arg->rx_err = trx_stat->rx_err_cnt;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: drv err count = %d\n", __FUNCTION__, arg->rx_err);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_get_rssi(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rx_path: %d\n", __FUNCTION__, arg->rx_path);
hal_status = rtw_hal_bb_get_rssi(mp->hal, arg->rx_path, &arg->rssi);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: rssi = %d\n", __FUNCTION__, arg->rssi);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_get_rssi_ex(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rx_path: %d\n", __FUNCTION__, arg->rx_path);
hal_status = rtw_hal_bb_get_rssi_ex(mp->hal, arg->rx_path, &arg->rssi_ex, mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_get_rxevm(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
hal_status = rtw_hal_bb_get_rxevm(mp->hal, arg->user, arg->strm, arg->rxevm_table, &arg->rx_evm);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: rx_evm = %d\n", __FUNCTION__, arg->rx_evm);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_trigger_rxevm(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
hal_status = rtw_hal_bb_trigger_rxevm(mp->hal, mp->cur_phy,
&arg->phy0_user0_rxevm, &arg->phy0_user1_rxevm, &arg->phy0_user2_rxevm, &arg->phy0_user3_rxevm,
&arg->phy1_user0_rxevm, &arg->phy1_user1_rxevm, &arg->phy1_user2_rxevm, &arg->phy1_user3_rxevm);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: phy0_user0_rxevm = %d\n", __FUNCTION__, arg->phy0_user0_rxevm);
PHL_INFO("%s: phy0_user1_rxevm = %d\n", __FUNCTION__, arg->phy0_user1_rxevm);
PHL_INFO("%s: phy0_user2_rxevm = %d\n", __FUNCTION__, arg->phy0_user2_rxevm);
PHL_INFO("%s: phy0_user3_rxevm = %d\n", __FUNCTION__, arg->phy0_user3_rxevm);
PHL_INFO("%s: phy1_user0_rxevm = %d\n", __FUNCTION__, arg->phy1_user0_rxevm);
PHL_INFO("%s: phy1_user1_rxevm = %d\n", __FUNCTION__, arg->phy1_user1_rxevm);
PHL_INFO("%s: phy1_user2_rxevm = %d\n", __FUNCTION__, arg->phy1_user2_rxevm);
PHL_INFO("%s: phy1_user3_rxevm = %d\n", __FUNCTION__, arg->phy1_user3_rxevm);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_rx_set_gain_offset(
struct mp_context *mp, struct mp_rx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: offset: %d\n", __FUNCTION__, arg->offset);
PHL_INFO("%s: rf_path: %d\n", __FUNCTION__, arg->rf_path);
hal_status = rtw_hal_bb_set_gain_offset(mp->hal, arg->offset, arg->rf_path, mp->cur_phy, arg->iscck);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_rx.c
|
C
|
agpl-3.0
| 6,618
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_TEST_MP_TX_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_tx_plcp_gen(
struct mp_context *mp, struct mp_tx_arg *arg, struct mp_plcp_param_t *plcp_tx_struct)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
hal_status = rtw_hal_bb_set_plcp_tx(hal_info->hal_com,
plcp_tx_struct,
mp->usr,
mp->cur_phy,
&arg->plcp_sts);
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_pmac_packet(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx);
PHL_INFO("%s: is cck: %d\n", __FUNCTION__, arg->is_cck);
PHL_INFO("%s: tx count: %d\n", __FUNCTION__, arg->tx_cnt);
PHL_INFO("%s: period: %d\n", __FUNCTION__, arg->period);
PHL_INFO("%s: tx time: %d\n", __FUNCTION__, arg->tx_time);
hal_status = rtw_hal_bb_set_pmac_packet_tx(hal_info->hal_com,
arg->start_tx,
arg->is_cck,
arg->tx_cnt,
arg->period,
arg->tx_time,
mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_pmac_continuous(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx);
PHL_INFO("%s: is cck: %d\n", __FUNCTION__, arg->is_cck);
hal_status = rtw_hal_bb_set_pmac_cont_tx(hal_info->hal_com,
arg->start_tx,
arg->is_cck,
mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_pmac_fw_trigger(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx);
PHL_INFO("%s: is cck: %d\n", __FUNCTION__, arg->is_cck);
PHL_INFO("%s: tx count: %d\n", __FUNCTION__, arg->tx_cnt);
PHL_INFO("%s: tx duty: %d\n", __FUNCTION__, arg->tx_time);
hal_status = rtw_hal_bb_set_pmac_fw_trigger_tx(hal_info->hal_com,
arg->start_tx,
arg->is_cck,
arg->tx_cnt,
(u8)arg->tx_time,
mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_single_tone(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: start tx: %d\n", __FUNCTION__, arg->start_tx);
PHL_INFO("%s: rf path: %d\n", __FUNCTION__, arg->tx_path);
hal_status = rtw_hal_rf_set_singletone_tx(mp->hal,
arg->start_tx,
arg->tx_path);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_carrier_suppression(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_set_suppression_tx(mp->hal);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_phy_ok_cnt(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
/*
hal_status = rtw_hal_bb_get_tx_ok(phl_info->hal,
mp->cur_phy, &arg->tx_ok);
*/
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: phy ok cnt = %d\n", __FUNCTION__, arg->tx_ok);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_mode_switch(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s\n", __FUNCTION__);
/* mode: 0 = tmac, 1 = pmac */
hal_status = rtw_hal_bb_tx_mode_switch(hal_info->hal_com, mp->cur_phy, arg->tx_mode);
hal_status = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: tx_mode = %d\n", __FUNCTION__, arg->tx_mode);
PHL_INFO("%s: phy index = %d\n", __FUNCTION__, mp->cur_phy);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_tx_f2p_cmd(
struct mp_context *mp, struct mp_tx_arg *arg, struct mp_mac_ax_f2p_test_para *f2p_para_struct,
struct mp_mac_ax_f2p_wd *f2p_wd_struct, struct mp_mac_ax_f2p_tx_cmd *f2p_tx_cmd_struct
)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
u8 psigb_addr[64] = {0};
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_mac_f2p_test_cmd(hal_info, f2p_para_struct, f2p_wd_struct, f2p_tx_cmd_struct, psigb_addr);
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_set_dpd_bypass(
struct mp_context *mp, struct mp_tx_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: phy index: %d\n", __FUNCTION__, mp->cur_phy);
PHL_INFO("%s: dpd_bypass: %d\n", __FUNCTION__, arg->dpd_bypass);
hal_status = rtw_hal_bb_set_dpd_bypass(hal_info->hal_com,
arg->dpd_bypass,
mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
void rtw_hal_mp_check_tx_idle(struct mp_context *mp, struct mp_tx_arg *arg)
{
arg->tx_state = rtw_hal_bb_check_tx_idle(mp->hal, mp->cur_phy);
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_tx.c
|
C
|
agpl-3.0
| 6,749
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_TEST_MP_TXPWR_C_
#include "../../hal_headers.h"
#include "../../../test/mp/phl_test_mp_def.h"
#ifdef CONFIG_HAL_TEST_MP
enum rtw_hal_status rtw_hal_mp_txpwr_read_table(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath);
PHL_INFO("%s: rate = %d\n", __FUNCTION__, arg->rate);
PHL_INFO("%s: bandwidth = %d\n", __FUNCTION__, arg->bandwidth);
PHL_INFO("%s: channel = %d\n", __FUNCTION__, arg->channel);
hal_status = rtw_hal_rf_read_pwr_table(hal_info->hal_com, arg->rfpath,
arg->rate, arg->bandwidth,
arg->channel, arg->offset,
arg->dcm, arg->beamforming,
&arg->table_item);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwrtrack(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
hal_status = rtw_hal_rf_get_pwrtrack(mp->hal, &arg->txpwr_track_status);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: pwr track status = %d\n", __FUNCTION__,
arg->txpwr_track_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_set_pwrtrack(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: pwr track status = %d\n", __FUNCTION__, arg->txpwr_track_status);
hal_status = rtw_hal_rf_set_pwrtrack(mp->hal, mp->cur_phy, arg->txpwr_track_status);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: tx power = %d\n", __FUNCTION__, arg->txpwr);
PHL_INFO("%s: phy index = %d\n", __FUNCTION__, mp->cur_phy);
hal_status = rtw_hal_bb_set_power(hal_info->hal_com,
arg->txpwr, mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
PHL_INFO("%s: phy index = %d\n", __FUNCTION__, mp->cur_phy);
/* Call hal API */
hal_status = rtw_hal_bb_get_power(hal_info->hal_com,
&arg->txpwr, mp->cur_phy);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: tx power = %d\n", __FUNCTION__, arg->txpwr);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_idx(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: tx path = %d\n", __FUNCTION__, arg->tx_path);
PHL_INFO("%s: is ofdm = %d\n", __FUNCTION__, arg->is_cck);
hal_status = rtw_hal_bb_get_pwr_index(mp->hal,
&arg->txpwr_index,
arg->tx_path, arg->is_cck);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: tx power index = %d\n", __FUNCTION__, arg->txpwr_index);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_set_pwr_idx(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: tx path = %d\n", __FUNCTION__, arg->tx_path);
PHL_INFO("%s: is ofdm = %d\n", __FUNCTION__, arg->is_cck);
hal_status = rtw_hal_bb_set_pwr_index(mp->hal,
arg->txpwr_index,
arg->tx_path, arg->is_cck);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: tx power index = %d\n", __FUNCTION__, arg->txpwr_index);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_thermal(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath);
hal_status = rtw_hal_rf_get_thermal(mp->hal, arg->rfpath, &arg->thermal);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: thermal = %d\n", __FUNCTION__, arg->thermal);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath);
PHL_INFO("%s: tssi = %d\n", __FUNCTION__, arg->tssi);
hal_status = rtw_hal_rf_set_tssi(mp->hal, mp->cur_phy, arg->rfpath, arg->tssi);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_set_tssi_offset(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath);
PHL_INFO("%s: tssi_de_offset = %d\n", __FUNCTION__, arg->tssi_de_offset);
hal_status = rtw_hal_rf_set_tssi_offset(mp->hal, mp->cur_phy,arg->tssi_de_offset,arg->rfpath);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_tssi(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath);
hal_status = rtw_hal_rf_get_tssi(mp->hal, mp->cur_phy, arg->rfpath, &arg->tssi);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: tssi = %d\n", __FUNCTION__, arg->tssi);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_online_tssi_de(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: rf path = %d\n", __FUNCTION__, arg->rfpath);
PHL_INFO("%s: dbm = %d\n", __FUNCTION__, arg->dbm);
PHL_INFO("%s: pout = %d\n", __FUNCTION__, arg->pout);
hal_status = rtw_hal_rf_get_online_tssi_de(mp->hal, mp->cur_phy, arg->rfpath, arg->dbm, arg->pout, &arg->online_tssi_de);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: online tssi de = %d\n", __FUNCTION__, arg->online_tssi_de);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_set_pwr_lmt_en(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = mp->hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
PHL_INFO("%s: arg pwr_lmt_en = %d\n", __FUNCTION__, arg->pwr_lmt_en);
hal_status = rtw_hal_mac_set_pwr_lmt_en_val(hal_com, mp->cur_phy, arg->pwr_lmt_en);
PHL_INFO("%s: set_pwr_lmt_en_val status = %d\n", __FUNCTION__, hal_status);
if (hal_status == RTW_HAL_STATUS_FAILURE)
return hal_status;
hal_status = rtw_hal_mac_write_pwr_limit_en(hal_com, mp->cur_phy);
PHL_INFO("%s:write_pwr_limit_en status = %d\n", __FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_get_pwr_lmt_en(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
struct hal_info_t *hal_info = mp->hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
PHL_INFO("%s: \n", __FUNCTION__);
arg->pwr_lmt_en = rtw_hal_mac_get_pwr_lmt_en_val(hal_com, mp->cur_phy);
PHL_INFO("%s: pwr_lmt_en = %d\n", __FUNCTION__, arg->pwr_lmt_en);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: is cck=%d, tx path = %d\n", __FUNCTION__,
arg->is_cck, arg->tx_path);
/* Call hal API */
hal_status = rtw_hal_bb_get_txpwr_ref(mp->hal,
arg->is_cck,
arg->tx_path,
&arg->txpwr_ref);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: txpwr_ref = %d\n", __FUNCTION__, arg->txpwr_ref);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_pwr_ref_cw(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: is cck=%d, tx path = %d\n", __FUNCTION__,
arg->is_cck, arg->tx_path);
/* Call hal API */
hal_status = rtw_hal_bb_get_pwr_index(mp->hal,
&arg->txpwr_index,
arg->tx_path,
arg->is_cck
);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: txpwr_ref = %d\n", __FUNCTION__, arg->txpwr_index);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_get_txinfo_pwr(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
/* Call hal API */
hal_status = rtw_hal_bb_get_txinfo_power(mp->hal,
&arg->txpwr);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: txinfo power = %d\n", __FUNCTION__, arg->txpwr);
return hal_status;
}
enum rtw_hal_status rtw_hal_mp_txpwr_ctrl_rf_mode(
struct mp_context *mp, struct mp_txpwr_arg *arg)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
/* Call hal API */
hal_status = rtw_hal_bb_ctrl_rf_mode(mp->hal,
arg->rf_mode);
PHL_INFO("%s: status = %d\n", __FUNCTION__, hal_status);
PHL_INFO("%s: rf mode = %d\n", __FUNCTION__, arg->rf_mode);
return hal_status;
}
void rtw_hal_mp_set_tx_pow_patten_sharp(struct mp_context *mp, struct mp_txpwr_arg *arg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)mp->hal;
rtw_hal_bb_set_pow_patten_sharp(hal_info->hal_com, arg->channel, arg->is_cck, arg->sharp_id, mp->cur_phy);
}
#endif /* CONFIG_HAL_TEST_MP */
|
2301_81045437/rtl8852be
|
phl/hal_g6/test/mp/hal_test_mp_txpwr.c
|
C
|
agpl-3.0
| 10,288
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_TRX_DEF_PCIE_H_
#define _PHL_TRX_DEF_PCIE_H_
#ifdef RTW_WKARD_WD0_SER
#define MAX_WD_PAGE_NUM (256*2)
#else
#define MAX_WD_PAGE_NUM 256
#endif
#define WP_TID_INDIC_RESERVED_BIT BIT(14)
#define WP_RESERVED_SEQ 0xFFF
#define WP_MAX_SEQ_NUMBER WP_RESERVED_SEQ
struct tx_base_desc {
u8 *vir_addr;
u32 phy_addr_l;
u32 phy_addr_h;
u32 buf_len;
void *os_rsvd[1];
u8 cache;
u16 host_idx;
u16 avail_num;
_os_lock txbd_lock;
};
struct rtw_wd_page {
_os_list list;
u8 *vir_addr;
u32 phy_addr_l;
u32 phy_addr_h;
u32 buf_len;
void *os_rsvd[1];
u8 ls;
u8 cache;
u16 wp_seq;
u16 host_idx;
};
struct rtw_rx_buf {
_os_list list;
u8 *vir_addr;
u32 phy_addr_l;
u32 phy_addr_h;
u32 buf_len;
u8 cache;
u8 dynamic;
#ifdef CONFIG_DYNAMIC_RX_BUF
bool reuse;
#endif
void *os_priv;
};
struct rx_base_desc {
u8 *vir_addr;
u32 phy_addr_l;
u32 phy_addr_h;
u32 buf_len;
void *os_rsvd[1];
u8 cache;
u16 host_idx;
u16 avail_num;
};
#endif /* _PHL_TRX_DEF_PCIE_H_ */
|
2301_81045437/rtl8852be
|
phl/hci/phl_trx_def_pcie.h
|
C
|
agpl-3.0
| 1,639
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_TRX_PCIE_C_
#include "../phl_headers.h"
#include "phl_trx_pcie.h"
#define target_in_area(target, start, end) \
((target < start || target > end) ? false : true)
void phl_recycle_payload(struct phl_info_t *phl_info, u8 dma_ch, u16 wp_seq,
u8 txsts);
void phl_dump_link_list(void *phl, _os_list *list_head, u8 type)
{
struct rtw_wd_page *wd_page = NULL, *t = NULL;
struct rtw_h2c_pkt *h2c_pkt = NULL, *h2c_t = NULL;
struct rtw_phl_tring_list *phl_tring_list = NULL, *phl_t = NULL;
struct phl_ring_status *ring_sts = NULL, *rsts_t = NULL;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
void *drv_priv = phl_to_drvpriv(phl_info);
u8 *vir_addr = NULL;
u32 i = 0, j = 0;
u16 phl_idx = 0, phl_next_idx = 0;
switch (type) {
case TYPE_WD_PAGE:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===Dump WD Page===\n");
phl_list_for_loop_safe(wd_page, t, struct rtw_wd_page,
list_head, list) {
vir_addr = (u8 *)wd_page->vir_addr;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "vir_addr = %p, %x; phy_addr_l = %x; phy_addr_h = %x\n",
vir_addr, *vir_addr,
wd_page->phy_addr_l,
wd_page->phy_addr_h);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "cache = %d; buf_len = %d, wp_seq = %d\n",
wd_page->cache, wd_page->buf_len,
wd_page->wp_seq);
}
break;
case TYPE_PHL_RING:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===Dump PHL Ring===\n");
phl_list_for_loop_safe(phl_tring_list, phl_t,
struct rtw_phl_tring_list,
list_head, list) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"-- macid = %d, band = %d, wmm = %d --\n",
phl_tring_list->macid,
phl_tring_list->band,
phl_tring_list->wmm);
for (i = 0; i < MAX_PHL_RING_CAT_NUM; i++) {
phl_idx = (u16)_os_atomic_read(drv_priv,
&phl_tring_list->phl_ring[i].phl_idx);
phl_next_idx = (u16)_os_atomic_read(drv_priv,
&phl_tring_list->phl_ring[i].phl_next_idx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"tid = %d\n"
"dma_ch = %d\n"
"tx_thres = %d\n"
"core_idx = %d\n"
"phl_idx = %d\n"
"phl_next_idx = %d\n",
phl_tring_list->phl_ring[i].tid,
phl_tring_list->phl_ring[i].dma_ch,
phl_tring_list->phl_ring[i].tx_thres,
phl_tring_list->phl_ring[i].core_idx,
phl_idx,
phl_next_idx);
for (j = 0; j < 5; j++) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"entry[%d] = %p\n",
j,
phl_tring_list->phl_ring[i].entry[j]);
}
}
}
break;
case TYPE_RING_STS:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===Dump PHL Ring status===\n");
phl_list_for_loop_safe(ring_sts, rsts_t, struct phl_ring_status,
list_head, list) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"macid = %d\n"
"req_busy = %d\n"
"ring_ptr = %p\n",
ring_sts->macid,
ring_sts->req_busy,
ring_sts->ring_ptr);
}
break;
case TYPE_H2C_PKT:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===Dump H2C PKT===\n");
phl_list_for_loop_safe(h2c_pkt, h2c_t, struct rtw_h2c_pkt,
list_head, list) {
vir_addr = (u8 *)h2c_pkt->vir_head;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "vir_addr = %p, %x; phy_addr_l = %x; phy_addr_h = %x\n",
vir_addr, *vir_addr,
h2c_pkt->phy_addr_l,
h2c_pkt->phy_addr_h);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "type = %d; cache = %d; buf_len = %d\n",
h2c_pkt->type, h2c_pkt->cache, h2c_pkt->buf_len);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "vir_head = %p; vir_data = %p; vir_tail = %p; vir_end = %p\n",
(u8 *)h2c_pkt->vir_head,
(u8 *)h2c_pkt->vir_data,
(u8 *)h2c_pkt->vir_tail,
(u8 *)h2c_pkt->vir_end);
}
break;
default :
break;
}
}
void _phl_dump_wp_stats(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_wp_rpt_stats *rpt_stats = NULL;
u8 ch = 0;
rpt_stats = (struct rtw_wp_rpt_stats *)hal_com->trx_stat.wp_rpt_stats;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"\n== wp report statistics == \n");
for (ch = 0; ch < hci_info->total_txch_num; ch++) {
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"ch : %u\n", (int)ch);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"busy count : %u\n",
(int)rpt_stats[ch].busy_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"ok count : %u\n",
(int)rpt_stats[ch].tx_ok_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"retry fail count : %u\n",
(int)rpt_stats[ch].rty_fail_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"lifetime drop count : %u\n",
(int)rpt_stats[ch].lifetime_drop_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"macid drop count : %u\n",
(int)rpt_stats[ch].macid_drop_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"sw drop count : %u\n",
(int)rpt_stats[ch].sw_drop_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"recycle fail count : %u\n",
(int)rpt_stats[ch].recycle_fail_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"delay ok count : %u\n",
(int)rpt_stats[ch].delay_tx_ok_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"delay retry fail count : %u\n",
(int)rpt_stats[ch].delay_rty_fail_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"delay lifetime drop count : %u\n",
(int)rpt_stats[ch].delay_lifetime_drop_cnt);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"delay macid drop count : %u\n",
(int)rpt_stats[ch].delay_macid_drop_cnt);
}
}
void _phl_dump_busy_wp(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_wd_page_ring *wd_ring = NULL;
struct rtw_xmit_req *treq = NULL;
void *ptr = NULL;
u16 wp_seq = 0;
u8 ch = 0;
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"\n== dump busy wp == \n");
for (ch = 0; ch < hci_info->total_txch_num; ch++) {
for (wp_seq = 0; wp_seq < WP_MAX_SEQ_NUMBER; wp_seq++) {
if (NULL != wd_ring[ch].wp_tag[wp_seq].ptr) {
ptr = wd_ring[ch].wp_tag[wp_seq].ptr;
treq = (struct rtw_xmit_req *)ptr;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"dma_ch = %d, wp_seq = 0x%x, ptr = %p!\n",
ch, wp_seq, ptr);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"wifi seq = %d\n",
treq->mdata.sw_seq);
}
}
}
}
u8 _phl_check_recycle(u16 target, u16 rptr, u16 wptr, u16 bndy)
{
u8 recycle = false;
u8 init = 0; /* starting point */
if (wptr > rptr) {
if (true == target_in_area(target, wptr, (bndy-1)))
recycle = true;
else if (true == target_in_area(target, init, rptr))
recycle = true;
else
recycle = false;
} else if (rptr > wptr) {
if (true == target_in_area(target, wptr, rptr))
recycle = true;
else
recycle = false;
} else {
recycle = true;
}
return recycle;
}
void phl_tx_start_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_tx_sts, PHL_TX_STATUS_RUNNING);
}
void phl_tx_resume_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_tx_sts, PHL_TX_STATUS_RUNNING);
}
void phl_req_tx_stop_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_tx_sts,
PHL_TX_STATUS_STOP_INPROGRESS);
}
void phl_tx_stop_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_tx_sts, PHL_TX_STATUS_SW_PAUSE);
}
bool phl_is_tx_sw_pause_pcie(struct phl_info_t *phl_info)
{
void *drvpriv = phl_to_drvpriv(phl_info);
if (PHL_TX_STATUS_SW_PAUSE == _os_atomic_read(drvpriv,
&phl_info->phl_sw_tx_sts))
return true;
else
return false;
}
void phl_rx_start_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_rx_sts, PHL_RX_STATUS_RUNNING);
}
void phl_rx_resume_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_rx_sts, PHL_RX_STATUS_RUNNING);
}
void phl_req_rx_stop_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_rx_sts,
PHL_RX_STATUS_STOP_INPROGRESS);
}
void phl_rx_stop_pcie(struct phl_info_t *phl_info)
{
void *drv = phl_to_drvpriv(phl_info);
_os_atomic_set(drv, &phl_info->phl_sw_rx_sts, PHL_RX_STATUS_SW_PAUSE);
}
bool phl_is_rx_sw_pause_pcie(struct phl_info_t *phl_info)
{
void *drvpriv = phl_to_drvpriv(phl_info);
if (PHL_RX_STATUS_SW_PAUSE == _os_atomic_read(drvpriv,
&phl_info->phl_sw_rx_sts)) {
if (true == rtw_phl_is_phl_rx_idle(phl_info))
return true;
else
return false;
} else {
return false;
}
}
#ifdef RTW_WKARD_DYNAMIC_LTR
static bool _phl_judge_idle_ltr_switching_conditions(
struct phl_info_t *phl_info, u16 macid)
{
struct rtw_phl_stainfo_t *sta_info = NULL;
struct rtw_stats *stats = &phl_info->phl_com->phl_stats;
u16 ltr_thre = phl_info->phl_com->bus_sw_cap.ltr_sw_ctrl_thre;
u8 tx_thre = 0, rx_thre = 0;
u32 last_time = phl_ltr_get_last_trigger_time(phl_info->phl_com);
tx_thre = ltr_thre >> 8;
rx_thre = (u8)(ltr_thre & 0xFF);
sta_info = rtw_phl_get_stainfo_by_macid(phl_info, macid);
if (!rtw_hal_ltr_is_sw_ctrl(phl_info->phl_com, phl_info->hal))
return false;
if (sta_info == NULL)
return false;
if (sta_info->wrole == NULL)
return false;
if (stats->tx_traffic.lvl > tx_thre)
return false;
if (stats->rx_traffic.lvl > rx_thre)
return false;
if (RTW_PCIE_LTR_SW_IDLE == phl_ltr_get_cur_state(phl_info->phl_com))
return false;
if (phl_get_passing_time_us(last_time) < 500)
return false;
return true;
}
static bool _phl_judge_act_ltr_switching_conditions(
struct phl_info_t *phl_info, u8 ch)
{
u32 last_time = phl_ltr_get_last_trigger_time(phl_info->phl_com);
u8 fwcmd_queue_idx = 0;
fwcmd_queue_idx = rtw_hal_get_fwcmd_queue_idx(phl_info->hal);
if (!rtw_hal_ltr_is_sw_ctrl(phl_info->phl_com, phl_info->hal))
return true;
if (ch == fwcmd_queue_idx)
return true;
if (RTW_PCIE_LTR_SW_ACT == phl_ltr_get_cur_state(phl_info->phl_com))
return true;
if (phl_get_passing_time_us(last_time) < 500)
return false;
return true;
}
static void _phl_act_ltr_update_stats(struct phl_info_t *phl_info,
bool success, u8 ch, u16 pending_wd_page_cnt)
{
static bool bdly = false;
static u32 dly_start_time = 0;
if (!rtw_hal_ltr_is_sw_ctrl(phl_info->phl_com, phl_info->hal))
return;
if (success) {
/* only those have been delayed last time*/
if (bdly) {
PHL_INFO("%s() ch(%u), %u packets be transmitted after defering %uus\n"
, __func__, ch, pending_wd_page_cnt,
phl_get_passing_time_us(dly_start_time));
rtw_hal_ltr_update_stats(phl_info->hal, true);
}
bdly = false;
} else {
/* the first packet that is going to defer */
if (false == bdly)
dly_start_time = _os_get_cur_time_us();
PHL_DBG("%s() ch(%u), %u packets be delayed\n", __func__,
ch, pending_wd_page_cnt);
rtw_hal_ltr_update_stats(phl_info->hal, false);
bdly = true;
dly_start_time = _os_get_cur_time_us();
}
}
static void _phl_switch_act_ltr(struct phl_info_t *phl_info, u8 tx_dma_ch)
{
u8 fwcmd_queue_idx = 0;
if (!rtw_hal_ltr_is_sw_ctrl(phl_info->phl_com, phl_info->hal))
return;
if (RTW_PCIE_LTR_SW_ACT == phl_ltr_get_cur_state(phl_info->phl_com))
return;
fwcmd_queue_idx = rtw_hal_get_fwcmd_queue_idx(phl_info->hal);
if (tx_dma_ch != fwcmd_queue_idx)
phl_ltr_sw_trigger(phl_info->phl_com, phl_info->hal,
RTW_PCIE_LTR_SW_ACT);
}
static void _phl_switch_idle_ltr(struct phl_info_t *phl_info,
struct rtw_wp_rpt_stats *rpt_stats)
{
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
u8 ch = 0;
bool bempty = 1;
u8 fwcmd_queue_idx = 0;
fwcmd_queue_idx = rtw_hal_get_fwcmd_queue_idx(phl_info->hal);
for (ch = 0; ch < hci_info->total_txch_num; ch++) {
if (ch == fwcmd_queue_idx)
continue;
if (rpt_stats[ch].busy_cnt != 0)
bempty = 0;
}
if (bempty)
phl_ltr_sw_trigger(phl_info->phl_com, phl_info->hal,
RTW_PCIE_LTR_SW_IDLE);
}
#endif
#ifdef RTW_WKARD_TXBD_UPD_LMT
static void
_phl_free_h2c_work_ring(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring)
{
void *drv_priv = phl_to_drvpriv(phl_info);
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
struct rtw_h2c_work *h2c_work = &wd_page_ring->h2c_work;
struct rtw_h2c_pkt *cmd = h2c_work->cmd;
struct rtw_h2c_pkt *data = h2c_work->data;
struct rtw_h2c_pkt *ldata = h2c_work->ldata;
struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops;
u16 i = 0, buf_num = 0;
buf_num = hal_spec->txbd_multi_tag;
if (NULL != cmd) {
for (i = 0; i < buf_num; i++) {
if (NULL == cmd->vir_head)
continue;
hci_trx_ops->free_h2c_pkt_buf(phl_info, cmd);
cmd->vir_head = NULL;
cmd->cache = false;
cmd++;
}
_os_mem_free(drv_priv, h2c_work->cmd,
buf_num * sizeof(*h2c_work->cmd));
}
if (NULL != data) {
for (i = 0; i < buf_num; i++) {
if (NULL == data->vir_head)
continue;
hci_trx_ops->free_h2c_pkt_buf(phl_info, data);
data->vir_head = NULL;
data->cache = false;
data++;
}
_os_mem_free(drv_priv, h2c_work->data,
buf_num * sizeof(*h2c_work->data));
}
if (NULL != ldata) {
for (i = 0; i < buf_num; i++) {
if (NULL == ldata->vir_head)
continue;
hci_trx_ops->free_h2c_pkt_buf(phl_info, ldata);
ldata->vir_head = NULL;
ldata->cache = false;
ldata++;
}
_os_mem_free(drv_priv, h2c_work->ldata,
buf_num * sizeof(*h2c_work->ldata));
}
if (NULL != h2c_work->cmd_ring) {
_os_mem_free(drv_priv, h2c_work->cmd_ring,
buf_num * sizeof(struct rtw_h2c_pkt *));
}
if (NULL != h2c_work->data_ring) {
_os_mem_free(drv_priv, h2c_work->data_ring,
buf_num * sizeof(struct rtw_h2c_pkt *));
}
if (NULL != h2c_work->ldata_ring) {
_os_mem_free(drv_priv, h2c_work->ldata_ring,
buf_num * sizeof(struct rtw_h2c_pkt *));
}
h2c_work->cmd_cnt = 0;
h2c_work->cmd_idx = 0;
h2c_work->data_cnt = 0;
h2c_work->data_idx = 0;
h2c_work->ldata_cnt = 0;
h2c_work->ldata_idx = 0;
_os_spinlock_free(drv_priv, &h2c_work->lock);
}
static enum rtw_phl_status
_phl_alloc_h2c_work_ring(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops;
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
struct rtw_h2c_work *h2c_work = &wd_page_ring->h2c_work;
struct rtw_h2c_pkt *cmd = NULL, *data = NULL, *ldata = NULL;
u16 buf_num = 0, i = 0;
buf_num = hal_spec->txbd_multi_tag;
_os_spinlock_init(drv_priv, &h2c_work->lock);
h2c_work->cmd = _os_mem_alloc(drv_priv, buf_num * sizeof(*cmd));
h2c_work->data = _os_mem_alloc(drv_priv, buf_num * sizeof(*data));
h2c_work->ldata = _os_mem_alloc(drv_priv, buf_num * sizeof(*ldata));
if (!h2c_work->cmd || !h2c_work->data || !h2c_work->ldata) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
cmd = h2c_work->cmd;
data = h2c_work->data;
ldata = h2c_work->ldata;
_os_mem_set(drv_priv, cmd, 0, buf_num * sizeof(*cmd));
_os_mem_set(drv_priv, data, 0, buf_num * sizeof(*data));
_os_mem_set(drv_priv, ldata, 0, buf_num * sizeof(*ldata));
h2c_work->cmd_ring =
_os_mem_alloc(drv_priv,
buf_num * sizeof(struct rtw_h2c_pkt *));
h2c_work->data_ring =
_os_mem_alloc(drv_priv,
buf_num * sizeof(struct rtw_h2c_pkt *));
h2c_work->ldata_ring =
_os_mem_alloc(drv_priv,
buf_num * sizeof(struct rtw_h2c_pkt *));
if (!h2c_work->cmd_ring || !h2c_work->data_ring ||
!h2c_work->ldata_ring) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
_os_mem_set(drv_priv, h2c_work->cmd_ring, 0,
buf_num * sizeof(struct rtw_h2c_pkt *));
_os_mem_set(drv_priv, h2c_work->data_ring, 0,
buf_num * sizeof(struct rtw_h2c_pkt *));
_os_mem_set(drv_priv, h2c_work->ldata_ring, 0,
buf_num * sizeof(struct rtw_h2c_pkt *));
for (i = 0; i < buf_num; i++) {
cmd->type = H2CB_TYPE_CMD;
cmd->cache = false;
cmd->buf_len = FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_CMD_LEN;
hci_trx_ops->alloc_h2c_pkt_buf(phl_info, cmd, cmd->buf_len);
if (NULL == cmd->vir_head) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
cmd->vir_data = cmd->vir_head + FWCMD_HDR_LEN + _WD_BODY_LEN;
cmd->vir_tail = cmd->vir_data;
cmd->vir_end = cmd->vir_data + H2C_CMD_LEN;
INIT_LIST_HEAD(&cmd->list);
h2c_work->cmd_ring[i] = cmd;
h2c_work->cmd_cnt++;
cmd++;
}
for (i = 0; i < buf_num; i++) {
data->type = H2CB_TYPE_DATA;
data->cache = false;
data->buf_len = FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_DATA_LEN;
hci_trx_ops->alloc_h2c_pkt_buf(phl_info, data, data->buf_len);
if (NULL == data->vir_head) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
data->vir_data = data->vir_head + FWCMD_HDR_LEN + _WD_BODY_LEN;
data->vir_tail = data->vir_data;
data->vir_end = data->vir_data + H2C_DATA_LEN;
INIT_LIST_HEAD(&data->list);
h2c_work->data_ring[i] = data;
h2c_work->data_cnt++;
data++;
}
for (i = 0; i < buf_num; i++) {
ldata->type = H2CB_TYPE_LONG_DATA;
ldata->cache = false;
ldata->buf_len = FWCMD_HDR_LEN + _WD_BODY_LEN +
H2C_LONG_DATA_LEN;
hci_trx_ops->alloc_h2c_pkt_buf(phl_info, ldata, ldata->buf_len);
if (NULL == ldata->vir_head) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
ldata->vir_data = ldata->vir_head + FWCMD_HDR_LEN +
_WD_BODY_LEN;
ldata->vir_tail = ldata->vir_data;
ldata->vir_end = ldata->vir_data + H2C_LONG_DATA_LEN;
INIT_LIST_HEAD(&ldata->list);
h2c_work->ldata_ring[i] = ldata;
h2c_work->ldata_cnt++;
ldata++;
}
h2c_work->cmd_idx = 0;
h2c_work->data_idx = 0;
h2c_work->ldata_idx = 0;
psts = RTW_PHL_STATUS_SUCCESS;
out:
if (RTW_PHL_STATUS_SUCCESS != psts) {
_phl_free_h2c_work_ring(phl_info, wd_page_ring);
h2c_work->cmd = NULL;
h2c_work->data = NULL;
h2c_work->ldata = NULL;
h2c_work->cmd_ring = NULL;
h2c_work->data_ring = NULL;
h2c_work->ldata_ring = NULL;
}
return psts;
}
static void
_phl_free_wd_work_ring(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring)
{
void *drv_priv = phl_to_drvpriv(phl_info);
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
u16 i = 0, buf_num = 0;
buf_num = hal_spec->txbd_multi_tag;
if (NULL != wd_page_ring->wd_work) {
for (i = 0; i < buf_num; i++) {
if (NULL == wd_page_ring->wd_work[i].vir_addr)
continue;
wd_page_ring->wd_work[i].wp_seq = WP_RESERVED_SEQ;
_os_shmem_free(drv_priv,
wd_page_ring->wd_work[i].vir_addr,
(_dma *)&wd_page_ring->wd_work[i].phy_addr_l,
(_dma *)&wd_page_ring->wd_work[i].phy_addr_h,
wd_page_ring->wd_work[i].buf_len,
wd_page_ring->wd_work[i].cache,
PCI_DMA_FROMDEVICE,
wd_page_ring->wd_work[i].os_rsvd[0]);
wd_page_ring->wd_work[i].vir_addr = NULL;
wd_page_ring->wd_work[i].cache = 0;
}
_os_mem_free(drv_priv, wd_page_ring->wd_work,
buf_num * sizeof(*wd_page_ring->wd_work));
wd_page_ring->wd_work = NULL;
}
if (NULL != wd_page_ring->wd_work_ring) {
_os_mem_free(drv_priv, wd_page_ring->wd_work_ring,
buf_num * sizeof(struct rtw_wd_page *));
wd_page_ring->wd_work_ring = NULL;
}
wd_page_ring->wd_work_cnt = 0;
wd_page_ring->wd_work_idx = 0;
}
static enum rtw_phl_status
_phl_alloc_wd_work_ring(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
struct rtw_wd_page *wd_work = NULL;
u32 buf_len = 0;
u16 buf_num = 0, i = 0;
buf_num = hal_spec->txbd_multi_tag;
wd_page_ring->wd_work = _os_mem_alloc(drv_priv,
buf_num * sizeof(*wd_work));
if (!wd_page_ring->wd_work) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
wd_work = wd_page_ring->wd_work;
_os_mem_set(drv_priv, wd_work, 0, buf_num * sizeof(*wd_work));
wd_page_ring->wd_work_ring =
_os_mem_alloc(drv_priv,
buf_num * sizeof(struct rtw_wd_page *));
if (!wd_page_ring->wd_work_ring) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
_os_mem_set(drv_priv, wd_page_ring->wd_work_ring, 0,
buf_num * sizeof(struct rtw_wd_page *));
for (i = 0; i < buf_num; i++) {
wd_work[i].cache = true;
buf_len = WD_PAGE_SIZE;
wd_work[i].vir_addr = _os_shmem_alloc(drv_priv,
(_dma *)&wd_work[i].phy_addr_l,
(_dma *)&wd_work[i].phy_addr_h,
buf_len,
wd_work[i].cache,
PCI_DMA_TODEVICE,
&wd_work[i].os_rsvd[0]);
if (NULL == wd_work[i].vir_addr) {
psts = RTW_PHL_STATUS_RESOURCE;
goto out;
}
wd_work[i].buf_len = buf_len;
wd_work[i].wp_seq = WP_RESERVED_SEQ;
INIT_LIST_HEAD(&wd_work[i].list);
wd_page_ring->wd_work_ring[i] = &wd_work[i];
wd_page_ring->wd_work_cnt++;
/* hana_todo now check 4 byte align only */
/* if ((unsigned long)wd_page_buf & 0xF) { */
/* res = _FAIL; */
/* break; */
/* } */
}
wd_page_ring->wd_work_idx = 0;
psts = RTW_PHL_STATUS_SUCCESS;
out:
if (RTW_PHL_STATUS_SUCCESS != psts) {
_phl_free_wd_work_ring(phl_info, wd_page_ring);
wd_page_ring->wd_work = NULL;
wd_page_ring->wd_work_ring = NULL;
}
return psts;
}
#else
#define _phl_free_h2c_work_ring(_phl, _ring)
#define _phl_alloc_h2c_work_ring(_phl, _ring) RTW_PHL_STATUS_SUCCESS
#define _phl_free_wd_work_ring(_phl, _ring)
#define _phl_alloc_wd_work_ring(_phl, _ring) RTW_PHL_STATUS_SUCCESS
#endif
static enum rtw_phl_status enqueue_pending_wd_page(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
struct rtw_wd_page *wd_page, u8 pos)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *list = &wd_page_ring->pending_wd_page_list;
if (wd_page != NULL) {
_os_spinlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
if (_tail == pos)
list_add_tail(&wd_page->list, list);
else if (_first == pos)
list_add(&wd_page->list, list);
wd_page_ring->pending_wd_page_cnt++;
_os_spinunlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static enum rtw_phl_status enqueue_busy_wd_page(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
struct rtw_wd_page *wd_page, u8 pos)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *list = &wd_page_ring->busy_wd_page_list;
if (wd_page != NULL) {
_os_spinlock(drv_priv, &wd_page_ring->busy_lock, _bh, NULL);
if (_tail == pos)
list_add_tail(&wd_page->list, list);
else if (_first == pos)
list_add(&wd_page->list, list);
wd_page_ring->busy_wd_page_cnt++;
_os_spinunlock(drv_priv, &wd_page_ring->busy_lock, _bh, NULL);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static enum rtw_phl_status enqueue_idle_wd_page(
struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
struct rtw_wd_page *wd_page)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *list = &wd_page_ring->idle_wd_page_list;
if (wd_page != NULL) {
wd_page->buf_len = WD_PAGE_SIZE;
wd_page->wp_seq = WP_RESERVED_SEQ;
wd_page->host_idx = 0;
INIT_LIST_HEAD(&wd_page->list);
_os_spinlock(drv_priv, &wd_page_ring->idle_lock, _bh, NULL);
list_add_tail(&wd_page->list, list);
wd_page_ring->idle_wd_page_cnt++;
_os_spinunlock(drv_priv, &wd_page_ring->idle_lock, _bh, NULL);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
#ifdef RTW_WKARD_TXBD_UPD_LMT
static enum rtw_phl_status enqueue_h2c_work_ring(
struct phl_info_t *phl_info,
struct rtw_h2c_pkt *h2c)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_wd_page_ring *wd_ring = NULL;
struct rtw_h2c_work *h2c_work = NULL;
struct rtw_h2c_pkt *work_done_h2c = NULL;
struct rtw_h2c_pkt **ring = NULL;
u16 *idx = 0, *cnt = 0;
u8 fwcmd_qidx = 0;
fwcmd_qidx = rtw_hal_get_fwcmd_queue_idx(phl_info->hal);
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
h2c_work = &wd_ring[fwcmd_qidx].h2c_work;
if (h2c == NULL)
goto out;
_os_spinlock(drv_priv, &h2c_work->lock, _bh, NULL);
if (H2CB_TYPE_CMD == h2c->type) {
ring = h2c_work->cmd_ring;
idx = &h2c_work->cmd_idx;
cnt = &h2c_work->cmd_cnt;
} else if (H2CB_TYPE_DATA == h2c->type) {
ring = h2c_work->data_ring;
idx = &h2c_work->data_idx;
cnt = &h2c_work->data_cnt;
} else if (H2CB_TYPE_LONG_DATA == h2c->type) {
ring = h2c_work->ldata_ring;
idx = &h2c_work->ldata_idx;
cnt = &h2c_work->ldata_cnt;
} else {
_os_spinunlock(drv_priv, &h2c_work->lock, _bh, NULL);
goto out;
}
work_done_h2c = ring[*idx];
ring[*idx] = h2c;
*idx = (*idx + 1) % *cnt;
_os_spinunlock(drv_priv, &h2c_work->lock, _bh, NULL);
pstatus = phl_enqueue_idle_h2c_pkt(phl_info, work_done_h2c);
out:
return pstatus;
}
static enum rtw_phl_status enqueue_wd_work_ring(
struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
struct rtw_wd_page *wd_page)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
struct rtw_wd_page *work_done_wd = NULL;
struct rtw_wd_page **ring = wd_page_ring->wd_work_ring;
if (wd_page != NULL) {
_os_spinlock(drv_priv, &wd_page_ring->work_lock, _bh, NULL);
work_done_wd = ring[wd_page_ring->wd_work_idx];
ring[wd_page_ring->wd_work_idx] = wd_page;
wd_page_ring->wd_work_idx =
(wd_page_ring->wd_work_idx + 1) % wd_page_ring->wd_work_cnt;
_os_spinunlock(drv_priv, &wd_page_ring->work_lock, _bh, NULL);
enqueue_idle_wd_page(phl_info, wd_page_ring, work_done_wd);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
#else
#define enqueue_h2c_work_ring(_phl, _h2c) RTW_PHL_STATUS_FAILURE
#define enqueue_wd_work_ring(_phl, _ring, _wd) RTW_PHL_STATUS_FAILURE
#endif
static struct rtw_wd_page *query_pending_wd_page(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring)
{
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *pending_list = &wd_page_ring->pending_wd_page_list;
struct rtw_wd_page *wd_page = NULL;
_os_spinlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
if (true == list_empty(pending_list)) {
wd_page = NULL;
} else {
wd_page = list_first_entry(pending_list, struct rtw_wd_page,
list);
wd_page_ring->pending_wd_page_cnt--;
list_del(&wd_page->list);
}
_os_spinunlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
return wd_page;
}
static struct rtw_wd_page *query_idle_wd_page(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring)
{
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *idle_list = &wd_page_ring->idle_wd_page_list;
struct rtw_wd_page *wd_page = NULL;
_os_spinlock(drv_priv, &wd_page_ring->idle_lock, _bh, NULL);
if (true == list_empty(idle_list)) {
wd_page = NULL;
} else {
wd_page = list_first_entry(idle_list, struct rtw_wd_page, list);
wd_page_ring->idle_wd_page_cnt--;
list_del(&wd_page->list);
}
_os_spinunlock(drv_priv, &wd_page_ring->idle_lock, _bh, NULL);
return wd_page;
}
static enum rtw_phl_status rtw_release_target_wd_page(
struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
struct rtw_wd_page *wd_page)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
if (wd_page_ring != NULL && wd_page != NULL) {
enqueue_idle_wd_page(phl_info, wd_page_ring, wd_page);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static enum rtw_phl_status rtw_release_pending_wd_page(
struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
u16 release_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
_os_list *list = &wd_page_ring->pending_wd_page_list;
struct rtw_wd_page *wd_page = NULL;
if (wd_page_ring != NULL) {
while (release_num > 0 && true != list_empty(list)) {
wd_page = query_pending_wd_page(phl_info, wd_page_ring);
enqueue_idle_wd_page(phl_info, wd_page_ring, wd_page);
release_num--;
}
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static enum rtw_phl_status rtw_release_busy_wd_page(
struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring,
u16 release_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
_os_list *list = &wd_page_ring->busy_wd_page_list;
struct rtw_wd_page *wd_page = NULL;
void *drv_priv = phl_to_drvpriv(phl_info);
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
if (wd_page_ring != NULL) {
_os_spinlock(drv_priv, &wd_page_ring->busy_lock, _bh, NULL);
while (release_num > 0 && true != list_empty(list)) {
wd_page = list_first_entry(list, struct rtw_wd_page,
list);
wd_page_ring->busy_wd_page_cnt--;
list_del(&wd_page->list);
_os_spinunlock(drv_priv, &wd_page_ring->busy_lock, _bh, NULL);
if (true == hal_spec->txbd_upd_lmt) {
pstatus = enqueue_wd_work_ring(phl_info,
wd_page_ring,
wd_page);
} else {
pstatus = enqueue_idle_wd_page(phl_info,
wd_page_ring,
wd_page);
}
_os_spinlock(drv_priv, &wd_page_ring->busy_lock, _bh, NULL);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
release_num--;
}
_os_spinunlock(drv_priv, &wd_page_ring->busy_lock, _bh, NULL);
}
return pstatus;
}
static void _phl_reset_txbd(struct phl_info_t *phl_info,
struct tx_base_desc *txbd)
{
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
_os_mem_set(phl_to_drvpriv(phl_info), txbd->vir_addr, 0, txbd->buf_len);
txbd->host_idx = 0;
txbd->avail_num = (u16)hal_com->bus_cap.txbd_num;
}
static void _phl_reset_wp_tag(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_page_ring, u8 dma_ch)
{
u16 wp_seq = 0;
for (wp_seq = 0; wp_seq < WP_MAX_SEQ_NUMBER; wp_seq++) {
if (NULL != wd_page_ring->wp_tag[wp_seq].ptr)
phl_recycle_payload(phl_info, dma_ch, wp_seq,
TX_STATUS_TX_FAIL_SW_DROP);
}
}
static enum rtw_phl_status enqueue_pending_h2c_pkt(struct phl_info_t *phl_info,
struct phl_h2c_pkt_pool *h2c_pkt_pool,
struct rtw_h2c_pkt *h2c_pkt, u8 pos)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
#if 0
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *list = &wd_page_ring->pending_wd_page_list;
if (wd_page != NULL) {
_os_spinlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
if (_tail == pos)
list_add_tail(&wd_page->list, list);
else if (_first == pos)
list_add(&wd_page->list, list);
wd_page_ring->pending_wd_page_cnt++;
_os_spinunlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
#endif
return pstatus;
}
static struct rtw_h2c_pkt *query_pending_h2c_pkt(struct phl_info_t *phl_info,
struct phl_h2c_pkt_pool *h2c_pkt_pool)
{
//void *drv_priv = phl_to_drvpriv(phl_info);
//_os_list *pending_list = &wd_page_ring->pending_wd_page_list;
struct rtw_h2c_pkt *h2c_pkt = NULL;
#if 0
_os_spinlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
if (true == list_empty(pending_list)) {
wd_page = NULL;
} else {
wd_page = list_first_entry(pending_list, struct rtw_wd_page,
list);
wd_page_ring->pending_wd_page_cnt--;
list_del(&wd_page->list);
}
_os_spinunlock(drv_priv, &wd_page_ring->pending_lock, _bh, NULL);
#endif
return h2c_pkt;
}
static enum rtw_phl_status phl_release_busy_h2c_pkt(
struct phl_info_t *phl_info,
struct phl_h2c_pkt_pool *h2c_pkt_pool,
u16 release_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
_os_list *list = &h2c_pkt_pool->busy_h2c_pkt_list.queue;
struct rtw_h2c_pkt *h2c_pkt = NULL;
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
if (h2c_pkt_pool != NULL) {
while (release_num > 0 && true != list_empty(list)) {
h2c_pkt = phl_query_busy_h2c_pkt(phl_info);
if (!h2c_pkt)
break;
if (true == hal_spec->txbd_upd_lmt) {
pstatus = enqueue_h2c_work_ring(phl_info,
h2c_pkt);
} else {
pstatus = phl_enqueue_idle_h2c_pkt(phl_info,
h2c_pkt);
}
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
release_num--;
}
}
return pstatus;
}
static void phl_tx_reset_pcie(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_wd_page_ring *wd_ring = NULL;
struct tx_base_desc *txbd = NULL;
struct phl_h2c_pkt_pool *h2c_pool = NULL;
u8 ch = 0;
txbd = (struct tx_base_desc *)hci_info->txbd_buf;
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
h2c_pool = (struct phl_h2c_pkt_pool *)phl_info->h2c_pool;
for (ch = 0; ch < hci_info->total_txch_num; ch++) {
_phl_reset_txbd(phl_info, &txbd[ch]);
rtw_release_busy_wd_page(phl_info, &wd_ring[ch],
wd_ring[ch].busy_wd_page_cnt);
rtw_release_pending_wd_page(phl_info, &wd_ring[ch],
wd_ring[ch].pending_wd_page_cnt);
_phl_reset_wp_tag(phl_info, &wd_ring[ch], ch);
}
phl_release_busy_h2c_pkt(phl_info, h2c_pool,
(u16)h2c_pool->busy_h2c_pkt_list.cnt);
phl_dump_h2c_pool_stats(phl_info->h2c_pool);
}
#ifdef CONFIG_DYNAMIC_RX_BUF
void _phl_alloc_dynamic_rxbuf_pcie(struct rtw_rx_buf *rx_buf,
struct phl_info_t *phl_info)
{
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
void *drv_priv = phl_to_drvpriv(phl_info);
u32 buf_len = RX_BUF_SIZE;
if (rx_buf->reuse) {
rx_buf->reuse = false;
_os_pkt_buf_map_rx(drv_priv,
(_dma *)&rx_buf->phy_addr_l,
(_dma *)&rx_buf->phy_addr_h,
RX_BUF_SIZE + PHL_RX_HEADROOM,
rx_buf->os_priv);
return;
}
if (rx_buf != NULL) {
rx_buf->cache = true;
rx_buf->vir_addr = _os_pkt_buf_alloc_rx(
drv_priv,
(_dma *)&rx_buf->phy_addr_l,
(_dma *)&rx_buf->phy_addr_h,
buf_len,
&rx_buf->os_priv);
if (NULL == rx_buf->vir_addr) {
sts = RTW_PHL_STATUS_RESOURCE;
} else {
rx_buf->buf_len = buf_len;
rx_buf->dynamic = 1;
rx_buf->reuse = false;
/* enqueue_idle_rx_buf(phl_info, rx_buf_ring, rx_buf); */
sts = RTW_PHL_STATUS_SUCCESS;
}
}
}
#endif
static enum rtw_phl_status enqueue_busy_rx_buf(
struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring,
struct rtw_rx_buf *rx_buf, u8 pos)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
_os_list *list = &rx_buf_ring->busy_rxbuf_list;
if (rx_buf != NULL) {
_os_spinlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->busy_rxbuf_lock, _bh, NULL);
if (_tail == pos)
list_add_tail(&rx_buf->list, list);
else if (_first == pos)
list_add(&rx_buf->list, list);
rx_buf_ring->busy_rxbuf_cnt++;
_os_spinunlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->busy_rxbuf_lock, _bh, NULL);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static enum rtw_phl_status enqueue_idle_rx_buf(
struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring,
struct rtw_rx_buf *rx_buf)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
_os_list *list = &rx_buf_ring->idle_rxbuf_list;
if (rx_buf != NULL) {
_os_mem_set(phl_to_drvpriv(phl_info), rx_buf->vir_addr, 0,
RX_BUF_SIZE);
rx_buf->buf_len = RX_BUF_SIZE;
INIT_LIST_HEAD(&rx_buf->list);
_os_spinlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->idle_rxbuf_lock, _bh, NULL);
list_add_tail(&rx_buf->list, list);
rx_buf_ring->idle_rxbuf_cnt++;
_os_spinunlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->idle_rxbuf_lock, _bh, NULL);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static struct rtw_rx_buf *query_busy_rx_buf(struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring)
{
_os_list *busy_list = &rx_buf_ring->busy_rxbuf_list;
struct rtw_rx_buf *rx_buf = NULL;
_os_spinlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->busy_rxbuf_lock, _bh, NULL);
if (true == list_empty(busy_list)) {
rx_buf = NULL;
} else {
rx_buf = list_first_entry(busy_list, struct rtw_rx_buf, list);
rx_buf_ring->busy_rxbuf_cnt--;
list_del(&rx_buf->list);
}
_os_spinunlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->busy_rxbuf_lock, _bh, NULL);
return rx_buf;
}
static struct rtw_rx_buf *query_idle_rx_buf(struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring)
{
_os_list *idle_list = &rx_buf_ring->idle_rxbuf_list;
struct rtw_rx_buf *rx_buf = NULL;
_os_spinlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->idle_rxbuf_lock, _bh, NULL);
if (true == list_empty(idle_list)) {
rx_buf = NULL;
} else {
rx_buf = list_first_entry(idle_list, struct rtw_rx_buf, list);
rx_buf_ring->idle_rxbuf_cnt--;
list_del(&rx_buf->list);
}
_os_spinunlock(phl_to_drvpriv(phl_info),
&rx_buf_ring->idle_rxbuf_lock, _bh, NULL);
return rx_buf;
}
enum rtw_phl_status
phl_release_target_rx_buf(struct phl_info_t *phl_info, void *r, u8 ch,
enum rtw_rx_type type)
{
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_rx_buf_ring *rx_buf_ring = NULL;
struct rtw_rx_buf *rx_buf = (struct rtw_rx_buf *)r;
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool;
#ifdef CONFIG_DYNAMIC_RX_BUF
if(rx_buf && (type == RTW_RX_TYPE_WIFI))
_phl_alloc_dynamic_rxbuf_pcie(rx_buf, phl_info);
#endif
if (&rx_buf_ring[ch] != NULL && rx_buf != NULL) {
enqueue_idle_rx_buf(phl_info, &rx_buf_ring[ch], rx_buf);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
static enum rtw_phl_status phl_release_busy_rx_buf(
struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring,
u16 release_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_rx_buf *rx_buf = NULL;
if (rx_buf_ring != NULL) {
while (release_num > 0) {
rx_buf = query_busy_rx_buf(phl_info, rx_buf_ring);
if (NULL == rx_buf)
break;
enqueue_idle_rx_buf(phl_info, rx_buf_ring, rx_buf);
release_num--;
}
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
/* static void rtl8852ae_free_wd_page_buf(_adapter *adapter, void *vir_addr, */
/* dma_addr_t *bus_addr, size_t size) */
/* { */
/* struct platform_ops *ops = &adapter->platform_func; */
/* struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); */
/* struct pci_dev *pdev = dvobj->ppcidev; */
/* FUNCIN(); */
/* ops->free_cache_mem(pdev,vir_addr, bus_addr, size, PCI_DMA_TODEVICE); */
/* /\* NONCACHE hana_todo */
/* * ops->alloc_noncache_mem(pdev, vir_addr, bus_addr, size); */
/* *\/ */
/* FUNCOUT(); */
/* } */
static void _phl_free_rxbuf_pcie(struct phl_info_t *phl_info,
struct rtw_rx_buf *rx_buf)
{
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
u16 rxbuf_num = (u16)hal_com->bus_cap.rxbuf_num;
u16 i = 0;
if (NULL != rx_buf) {
for (i = 0; i < rxbuf_num; i++) {
if (NULL == rx_buf[i].vir_addr)
continue;
_os_pkt_buf_free_rx(phl_to_drvpriv(phl_info),
rx_buf[i].vir_addr,
(_dma)rx_buf[i].phy_addr_l,
(_dma)rx_buf[i].phy_addr_h,
rx_buf[i].buf_len,
rx_buf[i].os_priv);
rx_buf[i].vir_addr = NULL;
rx_buf[i].cache = 0;
}
_os_mem_free(phl_to_drvpriv(phl_info), rx_buf,
sizeof(struct rtw_rx_buf) * rxbuf_num);
}
}
static void _phl_free_rxbuf_pool_pcie(struct phl_info_t *phl_info,
u8 *rxbuf_pool, u8 ch_num)
{
struct rtw_rx_buf_ring *ring = NULL;
u8 i = 0;
FUNCIN();
ring = (struct rtw_rx_buf_ring *)rxbuf_pool;
if (NULL != ring) {
for (i = 0; i < ch_num; i++) {
ring[i].idle_rxbuf_cnt = 0;
if (NULL == ring[i].rx_buf)
continue;
_phl_free_rxbuf_pcie(phl_info, ring[i].rx_buf);
ring[i].rx_buf = NULL;
_os_spinlock_free(phl_to_drvpriv(phl_info),
&ring->idle_rxbuf_lock);
_os_spinlock_free(phl_to_drvpriv(phl_info),
&ring->busy_rxbuf_lock);
}
_os_mem_free(phl_to_drvpriv(phl_info), ring,
sizeof(struct rtw_rx_buf_ring) * ch_num);
}
FUNCOUT();
}
/* static void *rtl8852ae_alloc_wd_page_buf(_adapter *adapter, */
/* dma_addr_t *bus_addr, size_t size) */
/* { */
/* struct platform_ops *ops = &adapter->platform_func; */
/* struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); */
/* struct pci_dev *pdev = dvobj->ppcidev; */
/* void *vir_addr = NULL; */
/* FUNCIN(); */
/* vir_addr = ops->alloc_cache_mem(pdev, bus_addr, size, PCI_DMA_TODEVICE); */
/* /\* NONCACHE hana_todo */
/* * vir_addr = ops->alloc_noncache_mem(pdev, bus_addr, size); */
/* *\/ */
/* FUNCOUT(); */
/* return vir_addr; */
/* } */
static struct rtw_rx_buf *
_phl_alloc_rxbuf_pcie(struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_rx_buf *rx_buf = NULL;
u32 buf_len = 0;
u16 rxbuf_num = (u16)hal_com->bus_cap.rxbuf_num;
void *drv_priv = phl_to_drvpriv(phl_info);
int i;
buf_len = sizeof(*rx_buf) * rxbuf_num;
rx_buf = _os_mem_alloc(drv_priv, buf_len);
if (rx_buf != NULL) {
for (i = 0; i < rxbuf_num; i++) {
rx_buf[i].cache = true;
buf_len = RX_BUF_SIZE;
rx_buf[i].vir_addr = _os_pkt_buf_alloc_rx(
phl_to_drvpriv(phl_info),
(_dma *)&rx_buf[i].phy_addr_l,
(_dma *)&rx_buf[i].phy_addr_h,
buf_len,
&rx_buf[i].os_priv);
if (NULL == rx_buf[i].vir_addr) {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
rx_buf[i].buf_len = buf_len;
rx_buf[i].dynamic = 0;
#ifdef CONFIG_DYNAMIC_RX_BUF
rx_buf[i].reuse = false;
#endif
INIT_LIST_HEAD(&rx_buf[i].list);
enqueue_idle_rx_buf(phl_info, rx_buf_ring, &rx_buf[i]);
pstatus = RTW_PHL_STATUS_SUCCESS;
/* hana_todo now check 4 byte align only */
/* if ((unsigned long)wd_page_buf & 0xF) { */
/* res = _FAIL; */
/* break; */
/* } */
}
}
if (RTW_PHL_STATUS_SUCCESS != pstatus) {
_phl_free_rxbuf_pcie(phl_info, rx_buf);
rx_buf = NULL;
}
return rx_buf;
}
static enum rtw_phl_status
_phl_alloc_rxbuf_pool_pcie(struct phl_info_t *phl_info, u8 ch_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_rx_buf_ring *rx_buf_ring = NULL;
struct rtw_rx_buf *rx_buf = NULL;
u32 buf_len = 0;
u16 rxbuf_num = (u16)hal_com->bus_cap.rxbuf_num;
int i;
FUNCIN_WSTS(pstatus);
buf_len = sizeof(*rx_buf_ring) * ch_num;
rx_buf_ring = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len);
if (NULL != rx_buf_ring) {
for (i = 0; i < ch_num; i++) {
_os_spinlock_init(phl_to_drvpriv(phl_info),
&rx_buf_ring[i].idle_rxbuf_lock);
_os_spinlock_init(phl_to_drvpriv(phl_info),
&rx_buf_ring[i].busy_rxbuf_lock);
INIT_LIST_HEAD(&rx_buf_ring[i].idle_rxbuf_list);
INIT_LIST_HEAD(&rx_buf_ring[i].busy_rxbuf_list);
rx_buf = _phl_alloc_rxbuf_pcie(phl_info,
&rx_buf_ring[i]);
if (NULL == rx_buf) {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
rx_buf_ring[i].rx_buf = rx_buf;
rx_buf_ring[i].idle_rxbuf_cnt = rxbuf_num;
rx_buf_ring[i].busy_rxbuf_cnt = 0;
pstatus = RTW_PHL_STATUS_SUCCESS;
}
}
if (RTW_PHL_STATUS_SUCCESS == pstatus) {
phl_info->hci->rxbuf_pool = (u8 *)rx_buf_ring;
} else
_phl_free_rxbuf_pool_pcie(phl_info, (u8 *)rx_buf_ring, ch_num);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
/* static void rtl8852ae_free_wd_page_buf(_adapter *adapter, void *vir_addr, */
/* dma_addr_t *bus_addr, size_t size) */
/* { */
/* struct platform_ops *ops = &adapter->platform_func; */
/* struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); */
/* struct pci_dev *pdev = dvobj->ppcidev; */
/* FUNCIN(); */
/* ops->free_cache_mem(pdev,vir_addr, bus_addr, size, PCI_DMA_TODEVICE); */
/* /\* NONCACHE hana_todo */
/* * ops->alloc_noncache_mem(pdev, vir_addr, bus_addr, size); */
/* *\/ */
/* FUNCOUT(); */
/* } */
static void _phl_free_wd_page_pcie(struct phl_info_t *phl_info,
struct rtw_wd_page *wd_page)
{
u16 i = 0;
if (NULL != wd_page) {
for (i = 0; i < MAX_WD_PAGE_NUM; i++) {
if (NULL == wd_page[i].vir_addr)
continue;
wd_page[i].wp_seq = WP_RESERVED_SEQ;
_os_shmem_free(phl_to_drvpriv(phl_info),
wd_page[i].vir_addr,
(_dma *)&wd_page[i].phy_addr_l,
(_dma *)&wd_page[i].phy_addr_h,
wd_page[i].buf_len,
wd_page[i].cache,
PCI_DMA_FROMDEVICE,
wd_page[i].os_rsvd[0]);
wd_page[i].vir_addr = NULL;
wd_page[i].cache = 0;
}
_os_mem_free(phl_to_drvpriv(phl_info), wd_page,
sizeof(struct rtw_wd_page) * MAX_WD_PAGE_NUM);
}
}
static void _phl_free_wd_ring_pcie(struct phl_info_t *phl_info, u8 *wd_page_buf,
u8 ch_num)
{
struct rtw_wd_page_ring *wd_page_ring = NULL;
void *drv_priv = phl_to_drvpriv(phl_info);
u8 i = 0;
FUNCIN();
wd_page_ring = (struct rtw_wd_page_ring *)wd_page_buf;
if (NULL != wd_page_ring) {
for (i = 0; i < ch_num; i++) {
wd_page_ring[i].idle_wd_page_cnt = 0;
if (NULL == wd_page_ring[i].wd_page)
continue;
if (i == rtw_hal_get_fwcmd_queue_idx(phl_info->hal)) {
_phl_free_h2c_work_ring(phl_info,
&wd_page_ring[i]);
}
_phl_free_wd_work_ring(phl_info, &wd_page_ring[i]);
_phl_free_wd_page_pcie(phl_info,
wd_page_ring[i].wd_page);
wd_page_ring[i].wd_page = NULL;
_os_spinlock_free(drv_priv,
&wd_page_ring[i].idle_lock);
_os_spinlock_free(drv_priv,
&wd_page_ring[i].busy_lock);
_os_spinlock_free(drv_priv,
&wd_page_ring[i].pending_lock);
_os_spinlock_free(drv_priv,
&wd_page_ring[i].work_lock);
_os_spinlock_free(drv_priv,
&wd_page_ring[i].wp_tag_lock);
}
_os_mem_free(phl_to_drvpriv(phl_info), wd_page_ring,
sizeof(struct rtw_wd_page_ring) * ch_num);
}
FUNCOUT();
}
/* static void *rtl8852ae_alloc_wd_page_buf(_adapter *adapter, */
/* dma_addr_t *bus_addr, size_t size) */
/* { */
/* struct platform_ops *ops = &adapter->platform_func; */
/* struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); */
/* struct pci_dev *pdev = dvobj->ppcidev; */
/* void *vir_addr = NULL; */
/* FUNCIN(); */
/* vir_addr = ops->alloc_cache_mem(pdev, bus_addr, size, PCI_DMA_TODEVICE); */
/* /\* NONCACHE hana_todo */
/* * vir_addr = ops->alloc_noncache_mem(pdev, bus_addr, size); */
/* *\/ */
/* FUNCOUT(); */
/* return vir_addr; */
/* } */
static struct rtw_wd_page *_phl_alloc_wd_page_pcie(
struct phl_info_t *phl_info, _os_list *list)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_wd_page *wd_page = NULL;
u32 buf_len = 0;
int i;
buf_len = sizeof(*wd_page) * MAX_WD_PAGE_NUM;
wd_page = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len);
if (wd_page != NULL) {
for (i = 0; i < MAX_WD_PAGE_NUM; i++) {
wd_page[i].cache = true;
buf_len = WD_PAGE_SIZE;
wd_page[i].vir_addr = _os_shmem_alloc(
phl_to_drvpriv(phl_info),
(_dma *)&wd_page[i].phy_addr_l,
(_dma *)&wd_page[i].phy_addr_h,
buf_len,
wd_page[i].cache,
PCI_DMA_TODEVICE,
&wd_page[i].os_rsvd[0]);
if (NULL == wd_page[i].vir_addr) {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
wd_page[i].buf_len = buf_len;
wd_page[i].wp_seq = WP_RESERVED_SEQ;
INIT_LIST_HEAD(&wd_page[i].list);
list_add_tail(&wd_page[i].list, list);
pstatus = RTW_PHL_STATUS_SUCCESS;
/* hana_todo now check 4 byte align only */
/* if ((unsigned long)wd_page_buf & 0xF) { */
/* res = _FAIL; */
/* break; */
/* } */
}
}
if (RTW_PHL_STATUS_SUCCESS != pstatus) {
_phl_free_wd_page_pcie(phl_info, wd_page);
wd_page = NULL;
}
return wd_page;
}
static enum rtw_phl_status
_phl_alloc_wd_ring_pcie(struct phl_info_t *phl_info, u8 ch_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_wd_page_ring *wd_page_ring = NULL;
struct rtw_wd_page *wd_page = NULL;
void *drv_priv = NULL;
u32 buf_len = 0;
int i;
FUNCIN_WSTS(pstatus);
drv_priv = phl_to_drvpriv(phl_info);
buf_len = sizeof(struct rtw_wd_page_ring) * ch_num;
wd_page_ring = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len);
if (NULL != wd_page_ring) {
for (i = 0; i < ch_num; i++) {
INIT_LIST_HEAD(&wd_page_ring[i].idle_wd_page_list);
INIT_LIST_HEAD(&wd_page_ring[i].busy_wd_page_list);
INIT_LIST_HEAD(&wd_page_ring[i].pending_wd_page_list);
_os_spinlock_init(drv_priv,
&wd_page_ring[i].idle_lock);
_os_spinlock_init(drv_priv,
&wd_page_ring[i].busy_lock);
_os_spinlock_init(drv_priv,
&wd_page_ring[i].pending_lock);
_os_spinlock_init(drv_priv,
&wd_page_ring[i].work_lock);
_os_spinlock_init(drv_priv,
&wd_page_ring[i].wp_tag_lock);
wd_page = _phl_alloc_wd_page_pcie(phl_info,
&wd_page_ring[i].idle_wd_page_list);
if (NULL == wd_page) {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
pstatus = _phl_alloc_wd_work_ring(phl_info,
&wd_page_ring[i]);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
if (i == rtw_hal_get_fwcmd_queue_idx(phl_info->hal)) {
pstatus = _phl_alloc_h2c_work_ring(phl_info,
&wd_page_ring[i]);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
}
wd_page_ring[i].wd_page = wd_page;
wd_page_ring[i].idle_wd_page_cnt = MAX_WD_PAGE_NUM;
wd_page_ring[i].busy_wd_page_cnt = 0;
wd_page_ring[i].pending_wd_page_cnt = 0;
wd_page_ring[i].wp_seq = 1;
pstatus = RTW_PHL_STATUS_SUCCESS;
}
}
if (RTW_PHL_STATUS_SUCCESS == pstatus) {
phl_info->hci->wd_ring = (u8 *)wd_page_ring;
} else
_phl_free_wd_ring_pcie(phl_info, (u8 *)wd_page_ring, ch_num);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
static void _phl_free_h2c_pkt_buf_pcie(struct phl_info_t *phl_info,
struct rtw_h2c_pkt *_h2c_pkt)
{
struct rtw_h2c_pkt *h2c_pkt = _h2c_pkt;
_os_shmem_free(phl_to_drvpriv(phl_info),
h2c_pkt->vir_head,
(_dma *)&h2c_pkt->phy_addr_l,
(_dma *)&h2c_pkt->phy_addr_h,
h2c_pkt->buf_len,
h2c_pkt->cache,
PCI_DMA_FROMDEVICE,
h2c_pkt->os_rsvd[0]);
}
enum rtw_phl_status _phl_alloc_h2c_pkt_buf_pcie(struct phl_info_t *phl_info,
struct rtw_h2c_pkt *_h2c_pkt, u32 buf_len)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_h2c_pkt *h2c_pkt = _h2c_pkt;
h2c_pkt->vir_head = _os_shmem_alloc(
phl_to_drvpriv(phl_info),
(_dma *)&h2c_pkt->phy_addr_l,
(_dma *)&h2c_pkt->phy_addr_h,
buf_len,
h2c_pkt->cache,
PCI_DMA_TODEVICE,
&h2c_pkt->os_rsvd[0]);
if (h2c_pkt->vir_head)
pstatus = RTW_PHL_STATUS_SUCCESS;
return pstatus;
}
static void _phl_free_rxbd_pcie(struct phl_info_t *phl_info,
u8 *rxbd_buf, u8 ch_num)
{
struct rx_base_desc *rxbd = (struct rx_base_desc *)rxbd_buf;
u8 i = 0;
FUNCIN();
if (NULL != rxbd) {
for (i = 0; i < ch_num; i++) {
if (NULL == rxbd[i].vir_addr)
continue;
_os_shmem_free(phl_to_drvpriv(phl_info),
rxbd[i].vir_addr,
(_dma *)&rxbd[i].phy_addr_l,
(_dma *)&rxbd[i].phy_addr_h,
rxbd[i].buf_len,
rxbd[i].cache,
PCI_DMA_FROMDEVICE,
rxbd[i].os_rsvd[0]);
rxbd[i].vir_addr = NULL;
rxbd[i].cache = 0;
}
_os_mem_free(phl_to_drvpriv(phl_info), rxbd,
sizeof(struct rx_base_desc) * ch_num);
}
FUNCOUT();
}
static enum rtw_phl_status
_phl_alloc_rxbd_pcie(struct phl_info_t *phl_info, u8 ch_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rx_base_desc *rxbd = NULL;
u32 buf_len = 0;
u16 rxbd_num = (u16)hal_com->bus_cap.rxbd_num;
u8 addr_info_size = hal_com->bus_hw_cap.rxbd_len;
u8 i = 0;
FUNCIN_WSTS(pstatus);
buf_len = sizeof(struct rx_base_desc) * ch_num;
rxbd = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len);
if (NULL != rxbd) {
for (i = 0; i < ch_num; i++) {
rxbd[i].cache = false;
buf_len = addr_info_size * rxbd_num;
rxbd[i].vir_addr = _os_shmem_alloc(
phl_to_drvpriv(phl_info),
(_dma *)&rxbd[i].phy_addr_l,
(_dma *)&rxbd[i].phy_addr_h,
buf_len,
rxbd[i].cache,
PCI_DMA_TODEVICE,
&rxbd[i].os_rsvd[0]);
if (NULL == rxbd[i].vir_addr) {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
rxbd[i].buf_len = buf_len;
rxbd[i].host_idx = 0;
rxbd[i].avail_num = rxbd_num;
pstatus = RTW_PHL_STATUS_SUCCESS;
}
}
if (RTW_PHL_STATUS_SUCCESS == pstatus)
phl_info->hci->rxbd_buf = (u8 *)rxbd;
else
_phl_free_rxbd_pcie(phl_info, (u8 *)rxbd, ch_num);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
static void _phl_free_txbd_pcie(struct phl_info_t *phl_info, u8 *txbd_buf,
u8 ch_num)
{
struct tx_base_desc *txbd = (struct tx_base_desc *)txbd_buf;
u8 i = 0;
FUNCIN();
if (NULL != txbd) {
for (i = 0; i < ch_num; i++) {
if (NULL == txbd[i].vir_addr)
continue;
_os_shmem_free(phl_to_drvpriv(phl_info),
txbd[i].vir_addr,
(_dma *)&txbd[i].phy_addr_l,
(_dma *)&txbd[i].phy_addr_h,
txbd[i].buf_len,
txbd[i].cache,
PCI_DMA_FROMDEVICE,
txbd[i].os_rsvd[0]);
txbd[i].vir_addr = NULL;
txbd[i].cache = 0;
_os_spinlock_free(phl_to_drvpriv(phl_info),
&txbd[i].txbd_lock);
}
_os_mem_free(phl_to_drvpriv(phl_info), txbd,
sizeof(struct tx_base_desc) * ch_num);
}
FUNCOUT();
}
static enum rtw_phl_status
_phl_alloc_txbd_pcie(struct phl_info_t *phl_info, u8 ch_num)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct tx_base_desc *txbd = NULL;
u32 buf_len = 0;
u16 txbd_num = (u16)hal_com->bus_cap.txbd_num;
u8 addr_info_size = hal_com->bus_hw_cap.txbd_len;
u8 i = 0;
FUNCIN_WSTS(pstatus);
buf_len = sizeof(struct tx_base_desc) * ch_num;
txbd = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len);
if (NULL != txbd) {
for (i = 0; i < ch_num; i++) {
txbd[i].cache = false;
buf_len = addr_info_size * txbd_num;
txbd[i].vir_addr = _os_shmem_alloc(
phl_to_drvpriv(phl_info),
(_dma *)&txbd[i].phy_addr_l,
(_dma *)&txbd[i].phy_addr_h,
buf_len,
txbd[i].cache,
PCI_DMA_TODEVICE,
&txbd[i].os_rsvd[0]);
if (NULL == txbd[i].vir_addr) {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
txbd[i].buf_len = buf_len;
txbd[i].avail_num = txbd_num;
_os_spinlock_init(phl_to_drvpriv(phl_info),
&txbd[i].txbd_lock);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
}
if (RTW_PHL_STATUS_SUCCESS == pstatus)
phl_info->hci->txbd_buf = (u8 *)txbd;
else
_phl_free_txbd_pcie(phl_info, (u8 *)txbd, ch_num);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
enum rtw_phl_status _phl_update_default_rx_bd(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rx_base_desc *rxbd = NULL;
struct rtw_rx_buf_ring *ring = NULL;
struct rtw_rx_buf *rxbuf = NULL;
u32 i = 0, j = 0;
rxbd = (struct rx_base_desc *)hci_info->rxbd_buf;
ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool;
for (i = 0; i < hci_info->total_rxch_num; i++) {
for (j = 0; j < hal_com->bus_cap.rxbd_num; j++) {
rxbuf = query_idle_rx_buf(phl_info, &ring[i]);
if (NULL == rxbuf) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING] there is no resource for rx bd default setting\n");
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
hstatus = rtw_hal_update_rxbd(phl_info->hal, &rxbd[i],
rxbuf);
if (RTW_HAL_STATUS_SUCCESS == hstatus) {
enqueue_busy_rx_buf(phl_info, &ring[i], rxbuf, _tail);
pstatus = RTW_PHL_STATUS_SUCCESS;
} else {
enqueue_idle_rx_buf(phl_info, &ring[i], rxbuf);
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING] update rx bd fail\n");
pstatus = RTW_PHL_STATUS_FAILURE;
break;
}
}
}
return pstatus;
}
static void _phl_reset_rxbd(struct phl_info_t *phl_info,
struct rx_base_desc *rxbd)
{
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
_os_mem_set(phl_to_drvpriv(phl_info), rxbd->vir_addr, 0, rxbd->buf_len);
rxbd->host_idx = 0;
rxbd->avail_num = (u16)hal_com->bus_cap.rxbd_num;
}
static void phl_rx_reset_pcie(struct phl_info_t *phl_info)
{
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct hal_spec_t *hal_spec = &phl_com->hal_spec;
struct rx_base_desc *rxbd = NULL;
struct rtw_rx_buf_ring *ring = NULL;
u8 ch = 0;
rxbd = (struct rx_base_desc *)hci_info->rxbd_buf;
ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool;
for (ch = 0; ch < hci_info->total_rxch_num; ch++) {
_phl_reset_rxbd(phl_info, &rxbd[ch]);
phl_release_busy_rx_buf(phl_info, &ring[ch],
ring[ch].busy_rxbuf_cnt);
}
hal_spec->rx_tag[0] = 0;
hal_spec->rx_tag[1] = 0;
_phl_update_default_rx_bd(phl_info);
}
void _phl_sort_ring_by_hw_res(struct phl_info_t *phl_info)
{
_os_list *t_fctrl_result = &phl_info->t_fctrl_result;
struct phl_ring_status *ring_sts, *t;
u16 hw_res = 0, host_idx = 0, hw_idx = 0;
u32 avail = 0, no_res = 0;
_os_list *no_res_first = NULL;
phl_list_for_loop_safe(ring_sts, t, struct phl_ring_status,
t_fctrl_result, list) {
if (ring_sts->ring_ptr->dma_ch > 32)
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING] dma channel number larger than record map\n");
if (no_res & (BIT0 << ring_sts->ring_ptr->dma_ch)) {
if (&ring_sts->list == no_res_first)
break;
list_del(&ring_sts->list);
list_add_tail(&ring_sts->list, t_fctrl_result);
continue;
} else if (avail & (BIT0 << ring_sts->ring_ptr->dma_ch)) {
continue;
}
hw_res = rtw_hal_tx_res_query(phl_info->hal,
ring_sts->ring_ptr->dma_ch,
&host_idx, &hw_idx);
if (0 == hw_res) {
if (no_res_first == NULL)
no_res_first = &ring_sts->list;
list_del(&ring_sts->list);
list_add_tail(&ring_sts->list, t_fctrl_result);
no_res = no_res | (BIT0 << ring_sts->ring_ptr->dma_ch);
} else {
avail = avail | (BIT0 << ring_sts->ring_ptr->dma_ch);
}
}
}
void _phl_tx_flow_ctrl_pcie(struct phl_info_t *phl_info, _os_list *sta_list)
{
/* _phl_sort_ring_by_hw_res(phl_info); */
phl_tx_flow_ctrl(phl_info, sta_list);
}
static enum rtw_phl_status _phl_handle_xmit_ring_pcie
(struct phl_info_t *phl_info,
struct phl_ring_status *ring_sts)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops;
struct rtw_phl_tx_ring *tring = ring_sts->ring_ptr;
struct rtw_xmit_req *tx_req = NULL;
u16 rptr = 0, next_idx = 0;
void *drv_priv = phl_to_drvpriv(phl_info);
while (0 != ring_sts->req_busy) {
rptr = (u16)_os_atomic_read(drv_priv, &tring->phl_next_idx);
tx_req = (struct rtw_xmit_req *)tring->entry[rptr];
if (NULL == tx_req) {
PHL_ERR("tx_req is NULL!\n");
break;
}
tx_req->mdata.macid = ring_sts->macid;
tx_req->mdata.band = ring_sts->band;
tx_req->mdata.wmm = ring_sts->wmm;
tx_req->mdata.hal_port = ring_sts->port;
/*tx_req->mdata.mbssid = ring_sts->mbssid;*/
tx_req->mdata.tid = tring->tid;
tx_req->mdata.dma_ch = tring->dma_ch;
pstatus = hci_trx_ops->prepare_tx(phl_info, tx_req);
if (RTW_PHL_STATUS_SUCCESS == pstatus) {
ring_sts->req_busy--;
/* hana_todo, workaround here to update phl_index */
_os_atomic_set(drv_priv, &tring->phl_idx, rptr);
if (0 != ring_sts->req_busy) {
next_idx = rptr + 1;
if (next_idx >= MAX_PHL_RING_ENTRY_NUM) {
_os_atomic_set(drv_priv,
&tring->phl_next_idx, 0);
} else {
_os_atomic_inc(drv_priv,
&tring->phl_next_idx);
}
}
} else {
PHL_INFO("HCI prepare tx fail\n");
break;
}
}
return pstatus;
}
static void _phl_tx_callback_pcie(void *context)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_phl_handler *phl_handler
= (struct rtw_phl_handler *)phl_container_of(context,
struct rtw_phl_handler,
os_handler);
struct phl_info_t *phl_info = (struct phl_info_t *)phl_handler->context;
struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops;
struct phl_ring_status *ring_sts = NULL, *t;
void *drvpriv = phl_to_drvpriv(phl_info);
_os_list sta_list;
bool tx_pause = false;
FUNCIN_WSTS(pstatus);
INIT_LIST_HEAD(&sta_list);
/* check datapath sw state */
tx_pause = phl_datapath_chk_trx_pause(phl_info, PHL_CTRL_TX);
if (true == tx_pause)
goto end;
#ifdef CONFIG_POWER_SAVE
/* check ps state when tx is not paused */
if (false == phl_ps_is_datapath_allowed(phl_info)) {
PHL_WARN("%s(): datapath is not allowed now... may in low power.\n", __func__);
goto chk_stop;
}
#endif
if (true == phl_check_xmit_ring_resource(phl_info, &sta_list)) {
_phl_tx_flow_ctrl_pcie(phl_info, &sta_list);
phl_list_for_loop_safe(ring_sts, t, struct phl_ring_status,
&phl_info->t_fctrl_result, list) {
list_del(&ring_sts->list);
_phl_handle_xmit_ring_pcie(phl_info, ring_sts);
phl_release_ring_sts(phl_info, ring_sts);
}
}
pstatus = hci_trx_ops->tx(phl_info);
if (RTW_PHL_STATUS_FAILURE == pstatus) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING] phl_tx fail!\n");
}
#ifdef CONFIG_POWER_SAVE
chk_stop:
#endif
if (PHL_TX_STATUS_STOP_INPROGRESS ==
_os_atomic_read(drvpriv, &phl_info->phl_sw_tx_sts)) {
PHL_WARN("PHL_TX_STATUS_STOP_INPROGRESS, going to stop sw tx.\n");
phl_tx_stop_pcie(phl_info);
}
end:
phl_free_deferred_tx_ring(phl_info);
FUNCOUT_WSTS(pstatus);
}
static u8 _phl_check_rx_hw_resource(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = phl_info->hci;
u16 hw_res = 0, host_idx = 0, hw_idx = 0;
u8 i = 0;
u8 avail = 0;
for (i = 0; i < hci_info->total_rxch_num; i++) {
hw_res = rtw_hal_rx_res_query(phl_info->hal,
i,
&host_idx, &hw_idx);
if (0 != hw_res) {
avail = true;
break;
} else {
avail = false;
}
}
return avail;
}
static void _phl_rx_callback_pcie(void *context)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_phl_handler *phl_handler
= (struct rtw_phl_handler *)phl_container_of(context,
struct rtw_phl_handler,
os_handler);
struct phl_info_t *phl_info = (struct phl_info_t *)phl_handler->context;
struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops;
void *drvpriv = phl_to_drvpriv(phl_info);
bool rx_pause = false;
#ifdef CONFIG_SYNC_INTERRUPT
struct rtw_phl_evt_ops *ops = &phl_info->phl_com->evt_ops;
#endif /* CONFIG_SYNC_INTERRUPT */
FUNCIN_WSTS(pstatus);
/* check datapath sw state */
rx_pause = phl_datapath_chk_trx_pause(phl_info, PHL_CTRL_RX);
if (true == rx_pause)
goto end;
do {
if (false == phl_check_recv_ring_resource(phl_info))
break;
pstatus = hci_trx_ops->rx(phl_info);
if (RTW_PHL_STATUS_FAILURE == pstatus) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING] phl_rx fail!\n");
}
} while (false);
if (PHL_RX_STATUS_STOP_INPROGRESS ==
_os_atomic_read(drvpriv, &phl_info->phl_sw_rx_sts)) {
phl_rx_stop_pcie(phl_info);
}
end:
/* restore int mask of rx */
rtw_hal_restore_rx_interrupt(phl_info->hal);
#ifdef CONFIG_SYNC_INTERRUPT
ops->interrupt_restore(phl_to_drvpriv(phl_info), true);
#endif /* CONFIG_SYNC_INTERRUPT */
FUNCOUT_WSTS(pstatus);
}
void _phl_fill_tx_meta_data(struct rtw_xmit_req *tx_req,
u16 packet_len)
{
tx_req->mdata.wp_offset = 56;
tx_req->mdata.wd_page_size = 1;
tx_req->mdata.addr_info_num = tx_req->pkt_cnt;
tx_req->mdata.pktlen = packet_len;
}
void phl_trx_resume_pcie(struct phl_info_t *phl_info, u8 type)
{
if (PHL_CTRL_TX & type)
phl_tx_resume_pcie(phl_info);
if (PHL_CTRL_RX & type)
phl_rx_resume_pcie(phl_info);
}
void phl_trx_reset_pcie(struct phl_info_t *phl_info, u8 type)
{
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
struct rtw_stats *phl_stats = &phl_com->phl_stats;
PHL_INFO("%s\n", __func__);
if (PHL_CTRL_TX & type) {
phl_tx_reset_pcie(phl_info);
phl_reset_tx_stats(phl_stats);
}
if (PHL_CTRL_RX & type) {
phl_rx_reset_pcie(phl_info);
phl_reset_rx_stats(phl_stats);
}
}
void phl_trx_stop_pcie(struct phl_info_t *phl_info)
{
phl_trx_reset_pcie(phl_info, PHL_CTRL_TX|PHL_CTRL_RX);
}
void phl_trx_deinit_pcie(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = phl_info->hci;
FUNCIN();
_phl_free_rxbuf_pool_pcie(phl_info, hci_info->rxbuf_pool,
hci_info->total_rxch_num);
hci_info->rxbuf_pool = NULL;
_phl_free_rxbd_pcie(phl_info, hci_info->rxbd_buf,
hci_info->total_rxch_num);
hci_info->rxbd_buf = NULL;
_phl_free_wd_ring_pcie(phl_info, hci_info->wd_ring,
hci_info->total_txch_num);
hci_info->wd_ring = NULL;
_phl_free_txbd_pcie(phl_info, hci_info->txbd_buf,
hci_info->total_txch_num);
hci_info->txbd_buf = NULL;
FUNCOUT();
}
enum rtw_phl_status phl_trx_init_pcie(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct hci_info_t *hci_info = phl_info->hci;
struct rtw_phl_handler *tx_handler = &phl_info->phl_tx_handler;
struct rtw_phl_handler *rx_handler = &phl_info->phl_rx_handler;
void *drv_priv = phl_to_drvpriv(phl_info);
u8 txch_num = 0, rxch_num = 0;
u16 i = 0;
FUNCIN_WSTS(pstatus);
do {
#ifdef CONFIG_PHL_CPU_BALANCE_TX
_os_workitem *workitem = &tx_handler->os_handler.u.workitem;
_os_workitem_config_cpu(drv_priv, workitem, "TX_PHL_0", CPU_ID_TX_PHL_0);
tx_handler->type = RTW_PHL_HANDLER_PRIO_LOW;
#else
tx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH; /* tasklet */
#endif
tx_handler->callback = _phl_tx_callback_pcie;
tx_handler->context = phl_info;
tx_handler->drv_priv = drv_priv;
pstatus = phl_register_handler(phl_info->phl_com, tx_handler);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
rx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH;
rx_handler->callback = _phl_rx_callback_pcie;
rx_handler->context = phl_info;
rx_handler->drv_priv = drv_priv;
pstatus = phl_register_handler(phl_info->phl_com, rx_handler);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
/* pcie tx sw resource */
txch_num = rtw_hal_query_txch_num(phl_info->hal);
hci_info->total_txch_num = txch_num;
/* allocate tx bd */
pstatus = _phl_alloc_txbd_pcie(phl_info, txch_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
/* allocate wd page */
pstatus = _phl_alloc_wd_ring_pcie(phl_info, txch_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
for (i = 0; i < PHL_MACID_MAX_NUM; i++)
hci_info->wp_seq[i] = WP_RESERVED_SEQ;
/* pcie rx sw resource */
rxch_num = rtw_hal_query_rxch_num(phl_info->hal);
hci_info->total_rxch_num = rxch_num;
/* allocate rx bd */
pstatus = _phl_alloc_rxbd_pcie(phl_info, rxch_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
/* allocate wd page */
pstatus = _phl_alloc_rxbuf_pool_pcie(phl_info, rxch_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
} while (false);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
phl_trx_deinit_pcie(phl_info);
else
pstatus = _phl_update_default_rx_bd(phl_info);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
enum rtw_phl_status phl_trx_config_pcie(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hci_info_t *hci_info = phl_info->hci;
do {
hstatus = rtw_hal_trx_init(phl_info->hal, hci_info->txbd_buf,
hci_info->rxbd_buf);
if (RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_ERR("rtw_hal_trx_init fail with status 0x%08X\n",
hstatus);
pstatus = RTW_PHL_STATUS_FAILURE;
break;
}
else {
pstatus = RTW_PHL_STATUS_SUCCESS;
}
phl_tx_start_pcie(phl_info);
phl_rx_start_pcie(phl_info);
} while (false);
return pstatus;
}
#ifdef CONFIG_PHL_TXSC
u8 *_phl_txsc_apply_shortcut(struct phl_info_t *phl_info, struct rtw_xmit_req *tx_req,
struct rtw_phl_stainfo_t *phl_sta, struct rtw_phl_pkt_req *phl_pkt_req)
{
struct phl_txsc_entry *ptxsc = NULL;
if (phl_sta == NULL)
return (u8 *)ptxsc;
if (tx_req->shortcut_id >= PHL_TXSC_ENTRY_NUM) {
PHL_ERR("[PHL][TXSC] wrong shortcut_id:%d, plz check !!!\n", tx_req->shortcut_id);
return (u8 *)ptxsc;
}
ptxsc = &phl_sta->phl_txsc[tx_req->shortcut_id];
if ((tx_req->treq_type == RTW_PHL_TREQ_TYPE_CORE_TXSC)) {
if (ptxsc == NULL) {
PHL_ERR("[txsc][phl] fetal err: ptxsc = NULL, plz check.\n");
return (u8 *)ptxsc;
}
if (!ptxsc->txsc_wd_cached) {
PHL_ERR("[txsc][phl] fetal err: txsc_wd_cached = 0, plz check.\n");
return (u8 *)ptxsc;
}
_os_mem_cpy(phl_info, phl_pkt_req->wd_page, ptxsc->txsc_wd_cache, ptxsc->txsc_wd_len);
phl_pkt_req->wd_len = ptxsc->txsc_wd_len;
/* update pktlen in wd_page, wd_body[8:15] = pktsize */
#if 0
packet_len = cpu_to_le16(tx_req->mdata.pktlen);
_os_mem_cpy(phl_info, phl_pkt_req.wd_page+8, &packet_len, sizeof(u16));
#endif
ptxsc->txsc_cache_hit++;
}
return (u8 *)ptxsc;
}
enum rtw_phl_status
_phl_txsc_add_shortcut(struct phl_info_t *phl_info, struct rtw_xmit_req *tx_req,
struct rtw_phl_pkt_req *phl_pkt_req, struct phl_txsc_entry *ptxsc)
{
if (tx_req->shortcut_id >= PHL_TXSC_ENTRY_NUM) {
PHL_ERR("[PHL][TXSC] wrong shortcut_id:%d, plz check.\n", tx_req->shortcut_id);
return RTW_PHL_STATUS_FAILURE;
}
if (ptxsc == NULL) {
PHL_ERR("[txsc][phl] fetal err: ptxsc = NULL, shortcut_id = %d, plz check.\n", tx_req->shortcut_id);
return RTW_PHL_STATUS_FAILURE;
}
if (tx_req->treq_type & RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC) {
_os_mem_set(phl_info, ptxsc, 0x0, sizeof(struct phl_txsc_entry));
_os_mem_cpy(phl_info, ptxsc->txsc_wd_cache, phl_pkt_req->wd_page, phl_pkt_req->wd_len);
ptxsc->txsc_wd_len = phl_pkt_req->wd_len;
ptxsc->txsc_wd_cached = true;
#if 0
PHL_PRINT("\n[txsc][phl] shortcut_id:%d, wd_page cached, len:%d. SMH: %u (%u)\n\n",
tx_req->shortcut_id, ptxsc->txsc_wd_len, tx_req->mdata.smh_en,
tx_req->treq_type);
#endif
tx_req->treq_type &= ~RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC;
if (tx_req->treq_type != RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC)
PHL_PRINT("Updated WD for request type %u\n", tx_req->treq_type);
}
return RTW_PHL_STATUS_SUCCESS;
}
#endif
enum rtw_phl_status
phl_prepare_tx_pcie(struct phl_info_t *phl_info, struct rtw_xmit_req *tx_req)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_wp_rpt_stats *rpt_stats =
(struct rtw_wp_rpt_stats *)hal_com->trx_stat.wp_rpt_stats;
struct hci_info_t *hci_info = NULL;
struct rtw_pkt_buf_list *pkt_buf = NULL;
struct rtw_wd_page_ring *wd_ring = NULL;
struct rtw_wd_page *wd_page = NULL;
struct rtw_phl_pkt_req phl_pkt_req;
void *ptr = NULL;
u16 packet_len = 0, wp_seq = 0;
u8 dma_ch = 0, i = 0;
u16 mid = 0;
#ifdef CONFIG_PHL_TXSC
struct phl_txsc_entry *ptxsc = NULL;
struct rtw_phl_stainfo_t *phl_sta = rtw_phl_get_stainfo_by_macid(phl_info, tx_req->mdata.macid);
#endif
FUNCIN_WSTS(pstatus);
do {
if (NULL == phl_info->hci) {
PHL_ERR("phl_info->hci is NULL!\n");
break;
}
hci_info = (struct hci_info_t *)phl_info->hci;
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
if (NULL == tx_req) {
PHL_ERR("tx_req is NULL!\n");
break;
}
mid = tx_req->mdata.macid;
dma_ch = tx_req->mdata.dma_ch;
wp_seq = wd_ring[dma_ch].wp_seq;
if (NULL != wd_ring[dma_ch].wp_tag[wp_seq].ptr) {
ptr = wd_ring[dma_ch].wp_tag[wp_seq].ptr;
PHL_ERR("wp_tag out of resource!\n");
PHL_ERR("stuck wp info:\n");
PHL_ERR("dma_ch = %d, wp_seq = 0x%x, ptr = %p!\n",
dma_ch, wp_seq, ptr);
PHL_ERR("wifi seq = %d\n",
((struct rtw_xmit_req *)ptr)->mdata.sw_seq);
_phl_dump_busy_wp(phl_info);
break;
}
pkt_buf = (struct rtw_pkt_buf_list *)&tx_req->pkt_list[0];
for (i = 0; i < tx_req->pkt_cnt; i++) {
packet_len += pkt_buf->length;
pkt_buf++;
}
tx_req->total_len = packet_len;
wd_page = query_idle_wd_page(phl_info, &wd_ring[dma_ch]);
if (NULL == wd_page) {
PHL_ERR("query idle wd page fail!\n");
PHL_ERR("dma_ch = %d, idle wd num = %d, "
"busy wd num = %d, pending wd num = %d\n",
dma_ch,
wd_ring[dma_ch].idle_wd_page_cnt,
wd_ring[dma_ch].busy_wd_page_cnt,
wd_ring[dma_ch].pending_wd_page_cnt);
if (wd_ring[dma_ch].busy_wd_page_cnt > MAX_WD_PAGE_NUM * 4 / 5)
rtw_hal_tx_dbg_status_dump(phl_info->hal);
break;
}
/* hana_todo */
_phl_fill_tx_meta_data(tx_req, packet_len);
phl_pkt_req.wd_page = wd_page->vir_addr;
phl_pkt_req.wp_seq = wp_seq;
phl_pkt_req.tx_req = tx_req;
#ifdef CONFIG_PHL_TXSC
phl_pkt_req.wd_len = 0;
ptxsc = (struct phl_txsc_entry *)_phl_txsc_apply_shortcut(phl_info, tx_req, phl_sta, &phl_pkt_req);
#endif
hstatus = rtw_hal_update_wd_page(phl_info->hal, &phl_pkt_req);
wd_page->buf_len = phl_pkt_req.wd_len;
if (RTW_HAL_STATUS_SUCCESS == hstatus) {
hci_info->wp_seq[mid] = phl_pkt_req.wp_seq;
enqueue_pending_wd_page(phl_info, &wd_ring[dma_ch],
wd_page, _tail);
tx_req->tx_time = _os_get_cur_time_ms();
#ifdef CONFIG_PHL_TX_DBG
if (tx_req->tx_dbg.en_dbg) {
tx_req->tx_dbg.enq_pending_wd_t =
_os_get_cur_time_us();
}
#endif /* CONFIG_PHL_TX_DBG */
_os_spinlock(phl_to_drvpriv(phl_info),
&wd_ring[dma_ch].wp_tag_lock,
_bh, NULL);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"update tx req(%p) in ch(%d) with wp_seq(0x%x) and wifi seq(%d)!\n",
tx_req, dma_ch, wp_seq, tx_req->mdata.sw_seq);
wd_ring[dma_ch].wp_tag[wp_seq].ptr = (u8 *)tx_req;
rpt_stats[dma_ch].busy_cnt++;
_os_spinunlock(phl_to_drvpriv(phl_info),
&wd_ring[dma_ch].wp_tag_lock,
_bh, NULL);
wp_seq = (wp_seq + 1) % WP_MAX_SEQ_NUMBER;
if (0 == wp_seq)
wp_seq = 1;
wd_ring[dma_ch].wp_seq = wp_seq;
pstatus = RTW_PHL_STATUS_SUCCESS;
//wb wd page
if(wd_page->cache == true) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "[%s] wd page cache wback \n",
__FUNCTION__);
_os_cache_wback(phl_to_drvpriv(phl_info),
(_dma *)&wd_page->phy_addr_l,
(_dma *)&wd_page->phy_addr_h,
wd_page->buf_len, PCI_DMA_TODEVICE);
}
#ifdef CONFIG_PHL_TXSC
_phl_txsc_add_shortcut(phl_info, tx_req, &phl_pkt_req, ptxsc);
#endif
break;
} else {
rtw_release_target_wd_page(phl_info, &wd_ring[dma_ch],
wd_page);
pstatus = RTW_PHL_STATUS_FAILURE;
break;
}
} while(false);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
static enum rtw_phl_status
phl_handle_pending_wd(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_ring,
u16 txcnt, u8 ch)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct tx_base_desc *txbd = NULL;
struct rtw_wd_page *wd = NULL;
u16 cnt = 0;
#ifdef RTW_WKARD_DYNAMIC_LTR
if (true != _phl_judge_act_ltr_switching_conditions(phl_info, ch)) {
_phl_act_ltr_update_stats(phl_info, false, ch,
wd_ring->pending_wd_page_cnt);
return RTW_PHL_STATUS_FAILURE;
} else {
_phl_act_ltr_update_stats(phl_info, true, ch,
wd_ring->pending_wd_page_cnt);
}
#endif
txbd = (struct tx_base_desc *)hci_info->txbd_buf;
while (txcnt > cnt) {
wd = query_pending_wd_page(phl_info, wd_ring);
if (NULL == wd) {
pstatus = RTW_PHL_STATUS_RESOURCE;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "query Tx pending WD fail!\n");
break;
}
wd->ls = 1;//tmp set LS=1
hstatus = rtw_hal_update_txbd(phl_info->hal, txbd, wd, ch, 1);
if (RTW_HAL_STATUS_SUCCESS == hstatus) {
enqueue_busy_wd_page(phl_info, wd_ring, wd, _tail);
pstatus = RTW_PHL_STATUS_SUCCESS;
} else {
enqueue_pending_wd_page(phl_info, wd_ring, wd, _first);
pstatus = RTW_PHL_STATUS_RESOURCE;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "update Tx BD fail!\n");
break;
}
cnt++;
}
if (RTW_PHL_STATUS_SUCCESS == pstatus) {
#ifdef RTW_WKARD_DYNAMIC_LTR
_phl_switch_act_ltr(phl_info, ch);
#endif
hstatus = rtw_hal_trigger_txstart(phl_info->hal, txbd, ch);
if (RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]update Tx RW ptr fail!\n");
pstatus = RTW_PHL_STATUS_FAILURE;
}
}
return pstatus;
}
static enum rtw_phl_status
phl_handle_busy_wd(struct phl_info_t *phl_info,
struct rtw_wd_page_ring *wd_ring, u16 hw_idx)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
void *drv_priv = phl_to_drvpriv(phl_info);
_os_list *list = &wd_ring->busy_wd_page_list;
struct rtw_wd_page *wd = NULL;
u16 bndy = (u16)hal_com->bus_cap.txbd_num;
u16 target = 0;
u16 release_num = 0;
do {
_os_spinlock(drv_priv, &wd_ring->busy_lock, _bh, NULL);
if (list_empty(list)) {
pstatus = RTW_PHL_STATUS_SUCCESS;
_os_spinunlock(drv_priv, &wd_ring->busy_lock, _bh, NULL);
break;
}
if (wd_ring->busy_wd_page_cnt > (bndy - 1)) {
release_num = wd_ring->busy_wd_page_cnt - (bndy - 1);
_os_spinunlock(drv_priv, &wd_ring->busy_lock, _bh, NULL);
pstatus = rtw_release_busy_wd_page(phl_info, wd_ring,
release_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
else
_os_spinlock(drv_priv, &wd_ring->busy_lock, _bh, NULL);
}
wd = list_first_entry(list, struct rtw_wd_page, list);
target = wd->host_idx;
if (hw_idx >= target)
release_num = ((hw_idx - target) + 1) % bndy;
else
release_num = ((bndy - target) + (hw_idx + 1)) % bndy;
_os_spinunlock(drv_priv, &wd_ring->busy_lock, _bh, NULL);
pstatus = rtw_release_busy_wd_page(phl_info, wd_ring,
release_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
} while (false);
return pstatus;
}
enum rtw_phl_status phl_recycle_busy_wd(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_wd_page_ring *wd_ring = NULL;
u16 hw_res = 0, host_idx = 0, hw_idx = 0;
u8 ch = 0;
FUNCIN_WSTS(pstatus);
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
for (ch = 0; ch < hci_info->total_txch_num; ch++) {
hw_res = rtw_hal_tx_res_query(phl_info->hal, ch, &host_idx,
&hw_idx);
pstatus = phl_handle_busy_wd(phl_info, &wd_ring[ch], hw_idx);
}
FUNCOUT_WSTS(pstatus);
return pstatus;
}
static enum rtw_phl_status
phl_handle_busy_h2c(struct phl_info_t *phl_info,
struct phl_h2c_pkt_pool *h2c_pool, u16 hw_idx)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
void *drv_priv = phl_to_drvpriv(phl_info);
struct phl_queue *queue = &h2c_pool->busy_h2c_pkt_list;
_os_list *list = &h2c_pool->busy_h2c_pkt_list.queue;
struct rtw_h2c_pkt *h2c = NULL;
u16 bndy = (u16)hal_com->bus_cap.txbd_num;
u16 target = 0;
u16 release_num = 0;
u16 tmp_cnt = 0;
do {
_os_spinlock(drv_priv, &queue->lock, _bh, NULL);
if (list_empty(list)) {
pstatus = RTW_PHL_STATUS_SUCCESS;
_os_spinunlock(drv_priv, &queue->lock, _bh, NULL);
break;
}
tmp_cnt = (u16)queue->cnt;
if (tmp_cnt > (bndy - 1)) {
release_num = tmp_cnt - (bndy - 1);
_os_spinunlock(drv_priv, &queue->lock, _bh, NULL);
pstatus = phl_release_busy_h2c_pkt(phl_info, h2c_pool,
release_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
else
_os_spinlock(drv_priv, &queue->lock, _bh, NULL);
}
h2c = list_first_entry(list, struct rtw_h2c_pkt, list);
target = h2c->host_idx;
if (hw_idx >= target)
release_num = ((hw_idx - target) + 1) % bndy;
else
release_num = ((bndy - target) + (hw_idx + 1)) % bndy;
_os_spinunlock(drv_priv, &queue->lock, _bh, NULL);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : release_num %d.\n", __func__, release_num);
pstatus = phl_release_busy_h2c_pkt(phl_info, h2c_pool,
release_num);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
break;
} while (false);
return pstatus;
}
enum rtw_phl_status phl_recycle_busy_h2c(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct phl_h2c_pkt_pool *h2c_pool = NULL;
u16 hw_res = 0, host_idx = 0, hw_idx = 0;
u8 fwcmd_queue_idx = 0;
FUNCIN_WSTS(pstatus);
h2c_pool = (struct phl_h2c_pkt_pool *)phl_info->h2c_pool;
_os_spinlock(phl_to_drvpriv(phl_info), &h2c_pool->recycle_lock, _bh, NULL);
fwcmd_queue_idx = rtw_hal_get_fwcmd_queue_idx(phl_info->hal);
hw_res = rtw_hal_tx_res_query(phl_info->hal, fwcmd_queue_idx, &host_idx,
&hw_idx);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : host idx %d, hw_idx %d.\n",
__func__, host_idx, hw_idx);
pstatus = phl_handle_busy_h2c(phl_info, h2c_pool, hw_idx);
_os_spinunlock(phl_to_drvpriv(phl_info), &h2c_pool->recycle_lock, _bh, NULL);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
static enum rtw_phl_status phl_tx_pcie(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_wd_page_ring *wd_ring = NULL;
u16 hw_res = 0, host_idx = 0, hw_idx = 0, txcnt = 0;
u8 ch = 0;
FUNCIN_WSTS(pstatus);
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
for (ch = 0; ch < hci_info->total_txch_num; ch++) {
#ifndef RTW_WKARD_WIN_TRX_BALANCE
/* if wd_ring is empty, do not read hw_idx for saving cpu cycle */
if (wd_ring[ch].pending_wd_page_cnt == 0 && wd_ring[ch].busy_wd_page_cnt == 0){
pstatus = RTW_PHL_STATUS_SUCCESS;
continue;
}
#endif
/* hana_todo skip fwcmd queue */
hw_res = rtw_hal_tx_res_query(phl_info->hal, ch, &host_idx,
&hw_idx);
pstatus = phl_handle_busy_wd(phl_info, &wd_ring[ch], hw_idx);
if (list_empty(&wd_ring[ch].pending_wd_page_list))
continue;
if (RTW_PHL_STATUS_FAILURE == pstatus)
continue;
if (0 == hw_res) {
continue;
} else {
txcnt = (hw_res < wd_ring[ch].pending_wd_page_cnt) ?
hw_res : wd_ring[ch].pending_wd_page_cnt;
pstatus = phl_handle_pending_wd(phl_info, &wd_ring[ch],
txcnt, ch);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
continue;
}
}
FUNCOUT_WSTS(pstatus);
return pstatus;
}
enum rtw_phl_status _phl_refill_rxbd(struct phl_info_t *phl_info,
void* rx_buf_ring,
struct rx_base_desc *rxbd,
u8 ch, u16 refill_cnt)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_rx_buf *rxbuf = NULL;
u16 cnt = 0;
for (cnt = 0; cnt < refill_cnt; cnt++) {
rxbuf = query_idle_rx_buf(phl_info, rx_buf_ring);
if (NULL == rxbuf) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING] there is no resource for rx bd refill setting\n");
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
hstatus = rtw_hal_update_rxbd(phl_info->hal, rxbd, rxbuf);
if (RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING] update rxbd fail\n");
pstatus = RTW_PHL_STATUS_FAILURE;
break;
}
enqueue_busy_rx_buf(phl_info, rx_buf_ring, rxbuf, _tail);
pstatus = RTW_PHL_STATUS_SUCCESS;
}
/* hana_todo */
/* wmb(); */
if (cnt) {
hstatus = rtw_hal_notify_rxdone(phl_info->hal, rxbd, ch, cnt);
if (RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[WARNING] notify rxdone fail\n");
pstatus = RTW_PHL_STATUS_FAILURE;
}
}
return pstatus;
}
enum rtw_phl_status phl_get_single_rx(struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring,
u8 ch,
struct rtw_phl_rx_pkt **pphl_rx)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_rx_pkt *phl_rx = NULL;
struct rtw_rx_buf *rxbuf = NULL;
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_info->phl_com);
u16 buf_size = 0;
phl_rx = rtw_phl_query_phl_rx(phl_info);
rxbuf = query_busy_rx_buf(phl_info, rx_buf_ring);
do {
if (NULL == phl_rx) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s(%d) phl_rx out of resource\n",
__func__, __LINE__);
pstatus = RTW_PHL_STATUS_FAILURE;
break;
}
if (NULL == rxbuf) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "%s(%d) [WARNING] queried NULL rxbuf\n",
__func__, __LINE__);
pstatus = RTW_PHL_STATUS_FAILURE;
break;
}
phl_rx->rxbuf_ptr = (u8 *)rxbuf;
if(rxbuf->cache == true){
_os_cache_inv(phl_to_drvpriv(phl_info),
(_dma *)&rxbuf->phy_addr_l,
(_dma *)&rxbuf->phy_addr_h,
hal_spec->rx_bd_info_sz,
PCI_DMA_FROMDEVICE);
}
if (true != rtw_hal_check_rxrdy(phl_info->phl_com,
phl_info->hal,
rxbuf->vir_addr,
ch)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "RX:%s(%d) packet not ready\n",
__func__, __LINE__);
pstatus = RTW_PHL_STATUS_FAILURE;
#ifdef RTW_WKARD_98D_RXTAG
phl_rx->rxbuf_ptr = (u8 *)rxbuf;
goto drop;
#endif
break;
}
if (true != rtw_hal_handle_rxbd_info(phl_info->hal,
rxbuf->vir_addr,
&buf_size))
goto drop;
#ifdef CONFIG_DYNAMIC_RX_BUF
phl_rx->r.os_priv = rxbuf->os_priv;
#endif
/* hana_todo handle rx amsdu */
if(rxbuf->cache == true){
_os_cache_inv(phl_to_drvpriv(phl_info),
(_dma *)&rxbuf->phy_addr_l,
(_dma *)&rxbuf->phy_addr_h,
buf_size,
PCI_DMA_FROMDEVICE);
}
hstatus = rtw_hal_handle_rx_buffer(phl_info->phl_com,
phl_info->hal,
rxbuf->vir_addr,
buf_size, phl_rx);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
goto drop;
pstatus = RTW_PHL_STATUS_SUCCESS;
} while (false);
if (RTW_PHL_STATUS_SUCCESS != pstatus) {
/* hana_todo cache validate api */
if (NULL != rxbuf) {
enqueue_busy_rx_buf(phl_info, rx_buf_ring, rxbuf, _first);
}
if (NULL != phl_rx) {
phl_release_phl_rx(phl_info, phl_rx);
phl_rx = NULL;
}
}
*pphl_rx = phl_rx;
return pstatus;
drop:
#ifdef CONFIG_DYNAMIC_RX_BUF
/* avoid re-allocating buffer carried on rxbuf */
phl_rx->type = RTW_RX_TYPE_MAX;
#endif
phl_rx->r.mdata.dma_ch = ch;
phl_recycle_rx_buf(phl_info, phl_rx);
return RTW_PHL_STATUS_FRAME_DROP;
}
#define PHL_RX_HEADROOM 50
void phl_rx_handle_normal(struct phl_info_t *phl_info,
struct rtw_phl_rx_pkt *phl_rx)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
_os_list frames;
#ifdef CONFIG_DYNAMIC_RX_BUF
struct rtw_rx_buf *rxbuf = (struct rtw_rx_buf *)phl_rx->rxbuf_ptr;
#endif
FUNCIN_WSTS(pstatus);
INIT_LIST_HEAD(&frames);
/* unmap rx buffer */
#ifdef CONFIG_DYNAMIC_RX_BUF
_os_pkt_buf_unmap_rx(phl_to_drvpriv(phl_info), rxbuf->phy_addr_l,
rxbuf->phy_addr_h, RX_BUF_SIZE+PHL_RX_HEADROOM);
#endif
/* stat : rx rate counter */
if (phl_rx->r.mdata.rx_rate <= RTW_DATA_RATE_HE_NSS4_MCS11)
phl_info->phl_com->phl_stats.rx_rate_nmr[phl_rx->r.mdata.rx_rate]++;
pstatus = phl_rx_reorder(phl_info, phl_rx, &frames);
if (pstatus == RTW_PHL_STATUS_SUCCESS)
phl_handle_rx_frame_list(phl_info, &frames);
else
PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, "[WARNING]handle normal rx error (0x%08X)!\n", pstatus);
FUNCOUT_WSTS(pstatus);
}
void _phl_wp_rpt_statistics(struct phl_info_t *phl_info, u8 ch, u16 wp_seq,
u8 txsts, struct rtw_xmit_req *treq)
{
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_wp_rpt_stats *rpt_stats = NULL;
u32 diff_t = 0, cur_time = _os_get_cur_time_ms();
rpt_stats = (struct rtw_wp_rpt_stats *)hal_com->trx_stat.wp_rpt_stats;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"recycle tx req(%p) in ch(%d) with wp_seq(0x%x) and wifi seq(%d)!\n",
treq, ch, wp_seq, treq->mdata.sw_seq);
#ifdef CONFIG_PHL_TX_DBG
if (treq->tx_dbg.en_dbg) {
treq->tx_dbg.recycle_wd_t = _os_get_cur_time_us();
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "tx dbg rpt: macid(%02d), tx_dbg_pkt_type(%02d), txsts(%d), sw_seq(%04d), total tx time(%08d) us\n",
treq->mdata.macid, treq->tx_dbg.tx_dbg_pkt_type, txsts,
treq->mdata.sw_seq, phl_get_passing_time_us(
treq->tx_dbg.core_add_tx_t));
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "tx dbg rpt: core_add_tx_t(0x%08x), enq_pending_wd_t(0x%08x), recycle_wd_t(0x%08x)\n",
treq->tx_dbg.core_add_tx_t,
treq->tx_dbg.enq_pending_wd_t,
treq->tx_dbg.recycle_wd_t);
if(TX_STATUS_TX_DONE != txsts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "tx dbg rpt: tx fail(%d)\n", txsts);
if(NULL != treq->tx_dbg.statecb) {
treq->tx_dbg.statecb(phl_to_drvpriv(phl_info), treq->tx_dbg.pctx, false);
}
} else {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "tx dbg rpt: tx done(%d)\n", txsts);
if(NULL != treq->tx_dbg.statecb) {
treq->tx_dbg.statecb(phl_to_drvpriv(phl_info), treq->tx_dbg.pctx, true);
}
}
}
#endif /* CONFIG_PHL_TX_DBG */
if (cur_time >= treq->tx_time)
diff_t = cur_time - treq->tx_time;
else
diff_t = RTW_U32_MAX - treq->tx_time + cur_time;
if (diff_t > WP_DELAY_THRES_MS) {
if (TX_STATUS_TX_DONE == txsts)
rpt_stats[ch].delay_tx_ok_cnt++;
else if (TX_STATUS_TX_FAIL_REACH_RTY_LMT == txsts)
rpt_stats[ch].delay_rty_fail_cnt++;
else if (TX_STATUS_TX_FAIL_LIFETIME_DROP == txsts)
rpt_stats[ch].delay_lifetime_drop_cnt++;
else if (TX_STATUS_TX_FAIL_MACID_DROP == txsts)
rpt_stats[ch].delay_macid_drop_cnt++;
} else {
if (TX_STATUS_TX_DONE == txsts)
rpt_stats[ch].tx_ok_cnt++;
else if (TX_STATUS_TX_FAIL_REACH_RTY_LMT == txsts)
rpt_stats[ch].rty_fail_cnt++;
else if (TX_STATUS_TX_FAIL_LIFETIME_DROP == txsts)
rpt_stats[ch].lifetime_drop_cnt++;
else if (TX_STATUS_TX_FAIL_MACID_DROP == txsts)
rpt_stats[ch].macid_drop_cnt++;
}
}
void _phl_wp_rpt_chk_txsts(struct phl_info_t *phl_info, u8 ch, u16 wp_seq,
u8 txsts, struct rtw_xmit_req *treq)
{
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_wp_rpt_stats *rpt_stats = NULL;
struct rtw_pkt_buf_list *pkt_buf = (struct rtw_pkt_buf_list *)treq->pkt_list;
int i;
rpt_stats = (struct rtw_wp_rpt_stats *)hal_com->trx_stat.wp_rpt_stats;
if(TX_STATUS_TX_DONE != txsts) {
if (TX_STATUS_TX_FAIL_REACH_RTY_LMT == txsts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"this wp is tx fail (REACH_RTY_LMT): wp(%p), ch(%d), wp_seq(0x%x), macid(%d), Sw SN(%d), tid(%d), Rty_lmt_en/cnt(%d/%d)!\n",
treq, ch, wp_seq, treq->mdata.macid,
treq->mdata.sw_seq, treq->mdata.tid,
treq->mdata.data_tx_cnt_lmt_en,
treq->mdata.data_tx_cnt_lmt);
} else if (TX_STATUS_TX_FAIL_LIFETIME_DROP == txsts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"this wp is tx fail (LIFETIME_DROP): wp(%p), ch(%d), wp_seq(0x%x), macid(%d), Sw SN(%d), tid(%d), Rty_lmt_en/cnt(%d/%d)!\n",
treq, ch, wp_seq, treq->mdata.macid,
treq->mdata.sw_seq, treq->mdata.tid,
treq->mdata.data_tx_cnt_lmt_en,
treq->mdata.data_tx_cnt_lmt);
} else if (TX_STATUS_TX_FAIL_MACID_DROP == txsts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"this wp is tx fail (MACID_DROP): wp(%p), ch(%d), wp_seq(0x%x), macid(%d), Sw SN(%d), tid(%d), Rty_lmt_en/cnt(%d/%d)!\n",
treq, ch, wp_seq, treq->mdata.macid,
treq->mdata.sw_seq, treq->mdata.tid,
treq->mdata.data_tx_cnt_lmt_en,
treq->mdata.data_tx_cnt_lmt);
} else if(TX_STATUS_TX_FAIL_SW_DROP == txsts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"this wp is tx fail (SW_DROP): wp(%p), ch(%d), wp_seq(0x%x), macid(%d), Sw SN(%d), tid(%d), Rty_lmt_en/cnt(%d/%d)!\n",
treq, ch, wp_seq, treq->mdata.macid,
treq->mdata.sw_seq, treq->mdata.tid,
treq->mdata.data_tx_cnt_lmt_en,
treq->mdata.data_tx_cnt_lmt);
} else {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"this wp is tx fail (UNKNOWN(%d)): wp(%p), ch(%d), wp_seq(0x%x), macid(%d), Sw SN(%d), tid(%d), Rty_lmt_en/cnt(%d/%d)!\n",
txsts, treq, ch, wp_seq, treq->mdata.macid,
treq->mdata.sw_seq, treq->mdata.tid,
treq->mdata.data_tx_cnt_lmt_en,
treq->mdata.data_tx_cnt_lmt);
}
/* dump tx fail mac hdr */
if(MAC_HDR_LEN <= pkt_buf[0].length) {
PHL_DATA(COMP_PHL_XMIT, _PHL_INFO_, "=== Dump Tx MAC HDR ===");
for (i = 0; i < MAC_HDR_LEN; i++) {
if (!(i % 8))
PHL_DATA(COMP_PHL_XMIT, _PHL_INFO_, "\n");
PHL_DATA(COMP_PHL_XMIT, _PHL_INFO_, "%02X ", pkt_buf[0].vir_addr[i]);
}
PHL_DATA(COMP_PHL_XMIT, _PHL_INFO_, "\n");
}
}
if (treq->txfb) {
treq->txfb->txsts = txsts;
if (treq->txfb->txfb_cb)
treq->txfb->txfb_cb(treq->txfb);
}
}
void phl_recycle_payload(struct phl_info_t *phl_info, u8 dma_ch, u16 wp_seq,
u8 txsts)
{
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
struct rtw_wp_rpt_stats *rpt_stats =
(struct rtw_wp_rpt_stats *)hal_com->trx_stat.wp_rpt_stats;
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_phl_evt_ops *ops = &phl_info->phl_com->evt_ops;
struct rtw_wd_page_ring *wd_ring = NULL;
struct rtw_xmit_req *treq = NULL;
u16 macid = 0;
wd_ring = (struct rtw_wd_page_ring *)hci_info->wd_ring;
treq = (struct rtw_xmit_req *)wd_ring[dma_ch].wp_tag[wp_seq].ptr;
if (NULL == treq)
goto end;
macid = treq->mdata.macid;
_phl_wp_rpt_statistics(phl_info, dma_ch, wp_seq, txsts, treq);
_phl_wp_rpt_chk_txsts(phl_info, dma_ch, wp_seq, txsts, treq);
if (RTW_PHL_TREQ_TYPE_TEST_PATTERN == treq->treq_type) {
if (NULL == ops->tx_test_recycle)
goto end;
PHL_INFO("call tx_test_recycle\n");
sts = ops->tx_test_recycle(phl_info, treq);
} else if (RTW_PHL_TREQ_TYPE_NORMAL == treq->treq_type
#if defined(CONFIG_CORE_TXSC) || defined(CONFIG_PHL_TXSC)
|| RTW_PHL_TREQ_TYPE_CORE_TXSC == treq->treq_type
|| RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC == treq->treq_type
#endif
) {
if (NULL == ops->tx_recycle)
goto end;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "call tx_recycle\n");
sts = ops->tx_recycle(phl_to_drvpriv(phl_info), treq);
}
end:
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("tx recycle fail\n");
rpt_stats[dma_ch].recycle_fail_cnt++;
} else {
_os_spinlock(phl_to_drvpriv(phl_info),
&wd_ring[dma_ch].wp_tag_lock,
_bh, NULL);
wd_ring[dma_ch].wp_tag[wp_seq].ptr = NULL;
rpt_stats[dma_ch].busy_cnt--;
#ifdef RTW_WKARD_DYNAMIC_LTR
if (true ==
_phl_judge_idle_ltr_switching_conditions(phl_info, macid))
_phl_switch_idle_ltr(phl_info, rpt_stats);
#endif
_os_spinunlock(phl_to_drvpriv(phl_info),
&wd_ring[dma_ch].wp_tag_lock,
_bh, NULL);
}
/* phl_indic_pkt_complete(phl_info); */
}
void _phl_rx_handle_wp_report(struct phl_info_t *phl_info,
struct rtw_phl_rx_pkt *phl_rx)
{
struct rtw_recv_pkt *r = &phl_rx->r;
u8 *pkt = NULL;
u16 pkt_len = 0;
u16 wp_seq = 0, rsize = 0;
u8 sw_retry = 0, dma_ch = 0, txsts = 0;
pkt = r->pkt_list[0].vir_addr;
pkt_len = r->pkt_list[0].length;
while (pkt_len > 0) {
rsize = rtw_hal_handle_wp_rpt(phl_info->hal, pkt, pkt_len,
&sw_retry, &dma_ch, &wp_seq,
&txsts);
if (0 == rsize)
break;
if (false == sw_retry) {
phl_recycle_payload(phl_info, dma_ch, wp_seq, txsts);
} else {
/* hana_todo handle sw retry */
phl_recycle_payload(phl_info, dma_ch, wp_seq, txsts);
}
pkt += rsize;
pkt_len -= rsize;
}
}
static void phl_rx_process_pcie(struct phl_info_t *phl_info,
struct rtw_phl_rx_pkt *phl_rx)
{
switch (phl_rx->type) {
case RTW_RX_TYPE_WIFI:
#ifdef CONFIG_PHL_RX_PSTS_PER_PKT
if (false == phl_rx_proc_wait_phy_sts(phl_info, phl_rx)) {
PHL_TRACE(COMP_PHL_PSTS, _PHL_DEBUG_,
"phl_rx_proc_wait_phy_sts() return false \n");
phl_rx_handle_normal(phl_info, phl_rx);
}
#else
phl_rx_handle_normal(phl_info, phl_rx);
#endif
break;
case RTW_RX_TYPE_TX_WP_RELEASE_HOST:
_phl_rx_handle_wp_report(phl_info, phl_rx);
phl_recycle_rx_buf(phl_info, phl_rx);
break;
case RTW_RX_TYPE_PPDU_STATUS:
phl_rx_proc_ppdu_sts(phl_info, phl_rx);
#ifdef CONFIG_PHL_RX_PSTS_PER_PKT
phl_rx_proc_phy_sts(phl_info, phl_rx);
#endif
phl_recycle_rx_buf(phl_info, phl_rx);
break;
case RTW_RX_TYPE_C2H:
phl_recycle_rx_buf(phl_info, phl_rx);
break;
case RTW_RX_TYPE_CHANNEL_INFO:
case RTW_RX_TYPE_TX_RPT:
case RTW_RX_TYPE_DFS_RPT:
case RTW_RX_TYPE_MAX:
PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, "phl_rx_process_pcie(): Unsupported case:%d, please check it\n",
phl_rx->type);
phl_recycle_rx_buf(phl_info, phl_rx);
break;
default :
PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_, "[WARNING] unrecognize rx type\n");
phl_recycle_rx_buf(phl_info, phl_rx);
break;
}
}
static u16 _phl_get_idle_rxbuf_cnt(struct phl_info_t *phl_info,
struct rtw_rx_buf_ring *rx_buf_ring)
{
return rx_buf_ring->idle_rxbuf_cnt;
}
static enum rtw_phl_status phl_rx_pcie(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct hci_info_t *hci_info = (struct hci_info_t *)phl_info->hci;
struct rtw_rx_buf_ring *rx_buf_ring = NULL;
struct rx_base_desc *rxbd = NULL;
struct rtw_phl_rx_pkt *phl_rx = NULL;
u16 i = 0, rxcnt = 0, host_idx = 0, hw_idx = 0, idle_rxbuf_cnt = 0;
u8 ch = 0;
FUNCIN_WSTS(pstatus);
rx_buf_ring = (struct rtw_rx_buf_ring *)hci_info->rxbuf_pool;
rxbd = (struct rx_base_desc *)hci_info->rxbd_buf;
for (ch = 0; ch < hci_info->total_rxch_num; ch++) {
idle_rxbuf_cnt = _phl_get_idle_rxbuf_cnt(phl_info,
&rx_buf_ring[ch]);
if (idle_rxbuf_cnt == 0) {
PHL_WARN("%s, idle rxbuf is empty. (ch = %d)\n",
__func__, ch);
phl_dump_all_sta_rx_info(phl_info);
PHL_INFO("phl_rx_ring stored rx number = %d\n",
rtw_phl_query_new_rx_num(phl_info));
#ifdef PHL_RX_BATCH_IND
if (ch == 0)
_phl_indic_new_rxpkt(phl_info);
#endif
pstatus = RTW_PHL_STATUS_SUCCESS;
continue;
}
rxcnt = rtw_hal_rx_res_query(phl_info->hal, ch, &host_idx, &hw_idx);
if (rxcnt == 0) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,
"no avail hw rx\n");
pstatus = RTW_PHL_STATUS_SUCCESS;
continue;
}
/* only handle affordable amount of rxpkt */
if (rxcnt > idle_rxbuf_cnt) {
PHL_WARN("rxcnt %d is lager than idle rxbuf cnt %d.\n", rxcnt, idle_rxbuf_cnt);
rxcnt = idle_rxbuf_cnt;
}
for (i = 0; i < rxcnt; i++) {
pstatus = phl_get_single_rx(phl_info, &rx_buf_ring[ch],
ch, &phl_rx);
if (RTW_PHL_STATUS_FRAME_DROP == pstatus)
continue;
if (NULL == phl_rx) {
rxcnt = i;
break;
}
/* hana_todo */
phl_rx->r.mdata.dma_ch = ch;
phl_rx_process_pcie(phl_info, phl_rx);
}
#ifdef PHL_RX_BATCH_IND
if (ch == 0 && phl_info->rx_new_pending)
_phl_indic_new_rxpkt(phl_info);
#endif
pstatus = _phl_refill_rxbd(phl_info, &rx_buf_ring[ch],
&rxbd[ch], ch, rxcnt);
if (RTW_PHL_STATUS_RESOURCE == pstatus)
PHL_WARN("%s, rxcnt is not refilled %d.\n", __func__ , rxcnt);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
continue;
}
FUNCOUT_WSTS(pstatus);
return pstatus;
}
enum rtw_phl_status phl_pltfm_tx_pcie(struct phl_info_t *phl_info, void *pkt)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_h2c_pkt *h2c_pkt = (struct rtw_h2c_pkt *)pkt;
struct tx_base_desc *txbd = NULL;
struct phl_h2c_pkt_pool *h2c_pool = NULL;
struct rtw_wd_page wd;
u8 fwcmd_queue_idx = 0;
txbd = (struct tx_base_desc *)phl_info->hci->txbd_buf;
h2c_pool = (struct phl_h2c_pkt_pool *)phl_info->h2c_pool;
_os_mem_set(phl_to_drvpriv(phl_info), &wd, 0, sizeof(wd));
/* fowart h2c pkt information into the format of wd page */
wd.phy_addr_l = h2c_pkt->phy_addr_l;
wd.phy_addr_h= h2c_pkt->phy_addr_h;
wd.buf_len = h2c_pkt->data_len;
wd.ls = 1;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : wd.phy_addr_l %x, wd.phy_addr_h %x\n", __func__ , wd.phy_addr_l, wd.phy_addr_h);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : buf_len %x.\n", __func__ , wd.buf_len);
fwcmd_queue_idx = rtw_hal_get_fwcmd_queue_idx(phl_info->hal);
_os_spinlock(phl_to_drvpriv(phl_info), &txbd[fwcmd_queue_idx].txbd_lock, _bh, NULL);
hstatus = rtw_hal_update_txbd(phl_info->hal, txbd, &wd, fwcmd_queue_idx, 1);
_os_spinunlock(phl_to_drvpriv(phl_info), &txbd[fwcmd_queue_idx].txbd_lock, _bh, NULL);
h2c_pkt->host_idx = wd.host_idx;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : h2c_pkt->host_idx %d.\n", __func__, h2c_pkt->host_idx);
if (RTW_HAL_STATUS_SUCCESS == hstatus)
pstatus = phl_enqueue_busy_h2c_pkt(phl_info, h2c_pkt, _tail);
if (RTW_PHL_STATUS_SUCCESS == pstatus) {
_os_spinlock(phl_to_drvpriv(phl_info), &txbd[fwcmd_queue_idx].txbd_lock, _bh, NULL);
hstatus = rtw_hal_trigger_txstart(phl_info->hal, txbd, fwcmd_queue_idx);
_os_spinunlock(phl_to_drvpriv(phl_info), &txbd[fwcmd_queue_idx].txbd_lock, _bh, NULL);
if (RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "[WARNING]update Tx RW ptr fail!\n");
pstatus = RTW_PHL_STATUS_FAILURE;
}
}
return pstatus;
}
void *phl_get_txbd_buf_pcie(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = phl_info->hci;
return hci_info->txbd_buf;
}
void *phl_get_rxbd_buf_pcie(struct phl_info_t *phl_info)
{
struct hci_info_t *hci_info = phl_info->hci;
return hci_info->rxbd_buf;
}
void phl_recycle_rx_pkt_pcie(struct phl_info_t *phl_info,
struct rtw_phl_rx_pkt *phl_rx)
{
#ifdef CONFIG_DYNAMIC_RX_BUF
struct rtw_rx_buf *rx_buf = (struct rtw_rx_buf *)phl_rx->rxbuf_ptr;
rx_buf->reuse = true;
#endif
phl_recycle_rx_buf(phl_info, phl_rx);
}
enum rtw_phl_status phl_register_trx_hdlr_pcie(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct rtw_phl_handler *tx_handler = &phl_info->phl_tx_handler;
struct rtw_phl_handler *rx_handler = &phl_info->phl_rx_handler;
void *drv_priv = phl_to_drvpriv(phl_info);
tx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH; /* tasklet */
tx_handler->callback = _phl_tx_callback_pcie;
tx_handler->context = phl_info;
tx_handler->drv_priv = drv_priv;
pstatus = phl_register_handler(phl_info->phl_com, tx_handler);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
PHL_ERR("%s : register tx_handler fail.\n", __FUNCTION__);
rx_handler->type = RTW_PHL_HANDLER_PRIO_HIGH;
rx_handler->callback = _phl_rx_callback_pcie;
rx_handler->context = phl_info;
rx_handler->drv_priv = drv_priv;
pstatus = phl_register_handler(phl_info->phl_com, rx_handler);
if (RTW_PHL_STATUS_SUCCESS != pstatus)
PHL_ERR("%s : register rx_handler fail.\n", __FUNCTION__);
return pstatus;
}
void
phl_tx_watchdog_pcie(struct phl_info_t *phl_info)
{
struct rtw_stats *phl_stats = NULL;
phl_stats = &phl_info->phl_com->phl_stats;
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"\n=== Tx statistics === \n");
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"\nunicast tx bytes : %llu\n", phl_stats->tx_byte_uni);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"total tx bytes : %llu\n", phl_stats->tx_byte_total);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"tx throughput : %d(kbps)\n",
(int)phl_stats->tx_tp_kbits);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"last tx time : %d(ms)\n",
(int)phl_stats->last_tx_time_ms);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"tx request num to phl : %d\n",
(int)phl_stats->txreq_num);
#ifdef RTW_WKARD_DYNAMIC_LTR
if (rtw_hal_ltr_is_sw_ctrl(phl_info->phl_com, phl_info->hal)) {
PHL_INFO(
"ltr sw ctrl : %u\n",
rtw_hal_ltr_is_sw_ctrl(phl_info->phl_com, phl_info->hal) ? 1 : 0);
PHL_INFO(
"ltr current state : %u\n",
phl_ltr_get_cur_state(phl_info->phl_com));
PHL_INFO(
"ltr active trigger cnt : %lu\n",
phl_ltr_get_tri_cnt(phl_info->phl_com, RTW_PCIE_LTR_SW_ACT));
PHL_INFO(
"ltr idle trigger cnt : %lu\n",
phl_ltr_get_tri_cnt(phl_info->phl_com, RTW_PCIE_LTR_SW_IDLE));
PHL_INFO(
"ltr last trigger time : %lu\n",
phl_ltr_get_last_trigger_time(phl_info->phl_com));
}
#endif
_phl_dump_wp_stats(phl_info);
_phl_dump_busy_wp(phl_info);
PHL_TRACE(COMP_PHL_XMIT, _PHL_DEBUG_,
"\n===================== \n");
}
static struct phl_hci_trx_ops ops= {0};
void phl_hci_trx_ops_init(void)
{
ops.hci_trx_init = phl_trx_init_pcie;
ops.hci_trx_deinit = phl_trx_deinit_pcie;
ops.prepare_tx = phl_prepare_tx_pcie;
ops.recycle_rx_buf = phl_release_target_rx_buf;
ops.tx = phl_tx_pcie;
ops.rx = phl_rx_pcie;
ops.trx_cfg = phl_trx_config_pcie;
ops.trx_stop = phl_trx_stop_pcie;
ops.recycle_busy_wd = phl_recycle_busy_wd;
ops.recycle_busy_h2c = phl_recycle_busy_h2c;
ops.pltfm_tx = phl_pltfm_tx_pcie;
ops.alloc_h2c_pkt_buf = _phl_alloc_h2c_pkt_buf_pcie;
ops.free_h2c_pkt_buf = _phl_free_h2c_pkt_buf_pcie;
ops.trx_reset = phl_trx_reset_pcie;
ops.trx_resume = phl_trx_resume_pcie;
ops.req_tx_stop = phl_req_tx_stop_pcie;
ops.req_rx_stop = phl_req_rx_stop_pcie;
ops.is_tx_pause = phl_is_tx_sw_pause_pcie;
ops.is_rx_pause = phl_is_rx_sw_pause_pcie;
ops.get_txbd_buf = phl_get_txbd_buf_pcie;
ops.get_rxbd_buf = phl_get_rxbd_buf_pcie;
ops.recycle_rx_pkt = phl_recycle_rx_pkt_pcie;
ops.register_trx_hdlr = phl_register_trx_hdlr_pcie;
ops.rx_handle_normal = phl_rx_handle_normal;
ops.tx_watchdog = phl_tx_watchdog_pcie;
}
enum rtw_phl_status phl_hook_trx_ops_pci(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
if (NULL != phl_info) {
phl_hci_trx_ops_init();
phl_info->hci_trx_ops = &ops;
pstatus = RTW_PHL_STATUS_SUCCESS;
}
return pstatus;
}
enum rtw_phl_status phl_cmd_set_l2_leave(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
#ifdef CONFIG_CMD_DISP
pstatus = phl_cmd_enqueue(phl_info, HW_BAND_0, MSG_EVT_HAL_SET_L2_LEAVE, NULL, 0, NULL, PHL_CMD_WAIT, 0);
if (is_cmd_failure(pstatus)) {
/* Send cmd success, but wait cmd fail*/
pstatus = RTW_PHL_STATUS_FAILURE;
} else if (pstatus != RTW_PHL_STATUS_SUCCESS) {
/* Send cmd fail */
pstatus = RTW_PHL_STATUS_FAILURE;
}
#else
if (rtw_hal_set_l2_leave(phl_info->hal) == RTW_HAL_STATUS_SUCCESS)
pstatus = RTW_PHL_STATUS_SUCCESS;
#endif
return pstatus;
}
|
2301_81045437/rtl8852be
|
phl/hci/phl_trx_pcie.c
|
C
|
agpl-3.0
| 106,168
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_TRX_PCIE_H_
#define _PHL_TRX_PCIE_H_
#define WP_DELAY_THRES_MS 1000
#define WD_PAGE_SIZE 128
#define RX_BUF_SIZE 11460 /* Rx buffer size (without RXBD info length) to 8 byte alignment by DD suggestion */
enum dump_list_type {
TYPE_WD_PAGE = 0,
TYPE_PHL_RING = 1,
TYPE_RING_STS = 2,
TYPE_H2C_PKT = 3,
TYPE_MAX = 0xFF
};
struct rtw_rx_buf_ring {
struct rtw_rx_buf *rx_buf;
_os_list idle_rxbuf_list;
_os_list busy_rxbuf_list;
u16 idle_rxbuf_cnt;
u16 busy_rxbuf_cnt;
_os_lock idle_rxbuf_lock;
_os_lock busy_rxbuf_lock;
};
struct rtw_wp_tag {
u8 *ptr;
};
struct rtw_h2c_work {
struct rtw_h2c_pkt *cmd;
struct rtw_h2c_pkt *data;
struct rtw_h2c_pkt *ldata;
struct rtw_h2c_pkt **cmd_ring;
struct rtw_h2c_pkt **data_ring;
struct rtw_h2c_pkt **ldata_ring;
_os_lock lock;
u16 cmd_cnt;
u16 cmd_idx;
u16 data_cnt;
u16 data_idx;
u16 ldata_cnt;
u16 ldata_idx;
};
struct rtw_wd_page_ring {
struct rtw_wd_page *wd_page;
struct rtw_wd_page *wd_work;
struct rtw_wd_page **wd_work_ring;
_os_list idle_wd_page_list;
_os_list busy_wd_page_list;
_os_list pending_wd_page_list;
_os_lock idle_lock;
_os_lock busy_lock;
_os_lock pending_lock;
_os_lock work_lock;
_os_lock wp_tag_lock;
u16 idle_wd_page_cnt;
u16 busy_wd_page_cnt;
u16 pending_wd_page_cnt;
u16 wd_work_cnt;
u16 wd_work_idx;
struct rtw_h2c_work h2c_work;
struct rtw_wp_tag wp_tag[WP_MAX_SEQ_NUMBER];
u16 wp_seq;
};
struct phl_buf {
u8 *vir_addr;
_dma phy_addr;
u8 cache;
u16 buf_len;
};
/* struct hana_temp{ */
/* struct wp_tag wp_tag[DMA_CHANNEL_ENTRY][4096]; */
/* struct wp_tag wp_tag_hq_b0[4096]; */
/* struct wp_tag wp_tag_mq_b0[4096]; */
/* struct wp_tag wp_tag_mq_no_ps_b0[4096]; */
/* struct wp_tag wp_tag_hq_b1[4096]; */
/* struct wp_tag wp_tag_mq_b1[4096]; */
/* struct wp_tag wp_tag_mq_no_ps_b1[4096]; */
/* }; */
enum rtw_phl_status phl_hook_trx_ops_pci(struct phl_info_t *phl_info);
enum rtw_phl_status phl_cmd_set_l2_leave(struct phl_info_t *phl_info);
#endif /* _PHL_TRX_PCIE_H_ */
|
2301_81045437/rtl8852be
|
phl/hci/phl_trx_pcie.h
|
C
|
agpl-3.0
| 2,694
|
########### COMMON PATH #################################
ifeq ($(CONFIG_HWSIM), y)
HAL = hal_sim
else
ifeq ($(CONFIG_WIFI_6), y)
HAL = hal_g6
else
HAL = hal
endif
endif
ifeq ($(CONFIG_PHL_ARCH), y)
phl_path := phl/
phl_path_d1 := $(src)/phl/$(HAL)
else
phl_path :=
phl_path_d1 := $(src)/$(HAL)
endif
_PHL_FILES := $(phl_path)phl_init.o \
$(phl_path)phl_debug.o \
$(phl_path)phl_tx.o \
$(phl_path)phl_rx.o \
$(phl_path)phl_rx_agg.o \
$(phl_path)phl_api_drv.o \
$(phl_path)phl_role.o \
$(phl_path)phl_sta.o \
$(phl_path)phl_mr.o \
$(phl_path)phl_sec.o \
$(phl_path)phl_chan.o \
$(phl_path)phl_sw_cap.o \
$(phl_path)phl_util.o \
$(phl_path)phl_pkt_ofld.o \
$(phl_path)phl_connect.o \
$(phl_path)phl_chan_info.o \
$(phl_path)phl_wow.o\
$(phl_path)phl_dm.o \
$(phl_path)phl_chnlplan.o \
$(phl_path)phl_country.o \
$(phl_path)phl_chnlplan_6g.o \
$(phl_path)phl_regulation.o \
$(phl_path)phl_regulation_6g.o \
$(phl_path)phl_led.o \
$(phl_path)phl_trx_mit.o \
$(phl_path)phl_acs.o \
$(phl_path)phl_mcc.o \
$(phl_path)phl_ecsa.o \
$(phl_path)test/phl_dbg_cmd.o \
$(phl_path)test/phl_ser_dbg_cmd.o \
$(phl_path)phl_msg_hub.o \
$(phl_path)phl_sound.o \
$(phl_path)phl_twt.o \
$(phl_path)phl_notify.o \
$(phl_path)phl_sound_cmd.o \
$(phl_path)phl_p2pps.o \
$(phl_path)phl_thermal.o \
$(phl_path)phl_txpwr.o
ifeq ($(CONFIG_POWER_SAVE), y)
_PHL_FILES += $(phl_path)phl_ps.o \
$(phl_path)test/phl_ps_dbg_cmd.o \
$(phl_path)phl_cmd_ps.o
endif
ifeq ($(CONFIG_FSM), y)
_PHL_FILES += $(phl_path)phl_fsm.o \
$(phl_path)phl_cmd_fsm.o \
$(phl_path)phl_cmd_job.o \
$(phl_path)phl_ser_fsm.o \
$(phl_path)phl_btc_fsm.o \
$(phl_path)phl_scan_fsm.o \
$(phl_path)phl_sound_fsm.o
endif
_PHL_FILES += $(phl_path)phl_cmd_dispatch_engine.o\
$(phl_path)phl_cmd_dispatcher.o\
$(phl_path)phl_cmd_dispr_controller.o \
$(phl_path)phl_cmd_ser.o \
$(phl_path)phl_cmd_general.o \
$(phl_path)phl_cmd_scan.o \
$(phl_path)phl_cmd_btc.o \
$(phl_path)phl_sound_cmd.o \
$(phl_path)phl_watchdog.o
ifeq ($(CONFIG_PCI_HCI), y)
_PHL_FILES += $(phl_path)hci/phl_trx_pcie.o
endif
ifeq ($(CONFIG_USB_HCI), y)
_PHL_FILES += $(phl_path)hci/phl_trx_usb.o
endif
ifeq ($(CONFIG_SDIO_HCI), y)
_PHL_FILES += $(phl_path)hci/phl_trx_sdio.o
endif
ifeq ($(CONFIG_PHL_CUSTOM_FEATURE), y)
_PHL_FILES += $(phl_path)custom/phl_custom.o
ifeq ($(CONFIG_PHL_CUSTOM_FEATURE_FB), y)
_PHL_FILES += $(phl_path)custom/phl_custom_fb.o
endif
endif
ifeq ($(CONFIG_PHL_TEST_SUITE), y)
_PHL_FILES += $(phl_path)test/trx_test.o
_PHL_FILES += $(phl_path)test/test_module.o
_PHL_FILES += $(phl_path)test/cmd_disp_test.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_config.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_tx.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_rx.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_reg.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_efuse.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_txpwr.o
_PHL_FILES += $(phl_path)test/mp/phl_test_mp_cal.o
_PHL_FILES += $(phl_path)test/verify/phl_test_verify.o
_PHL_FILES += $(phl_path)test/verify/dbcc/phl_test_dbcc.o
endif
OBJS += $(_PHL_FILES)
EXTRA_CFLAGS += -I$(phl_path_d1)
include $(phl_path_d1)/hal.mk
|
2301_81045437/rtl8852be
|
phl/phl.mk
|
Makefile
|
agpl-3.0
| 3,375
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_ACS_C_
#include "phl_headers.h"
#ifdef CONFIG_RTW_ACS
void phl_acs_mntr_trigger(struct phl_info_t *phl_info, u8 idx, u16 channel, u16 monitor_time)
{
struct auto_chan_sel *acs = &phl_info->acs;
if ((idx < 0) || (idx >= MAX_CHANNEL_NUM)) {
PHL_ERR("[ACS][%s] idx(%d) invalid\n", __func__, idx);
return;
} else if (idx == 0) {
_os_mem_set(phl_to_drvpriv(phl_info), acs, 0, sizeof(struct auto_chan_sel));
}
acs->curr_idx = idx;
acs->chset[idx] = channel;
rtw_hal_acs_mntr_trigger(phl_info->hal, monitor_time);
}
void phl_acs_mntr_result(struct phl_info_t *phl_info)
{
struct auto_chan_sel *acs = &phl_info->acs;
u8 idx = acs->curr_idx;
enum rtw_hal_status status;
struct auto_chan_sel_report rpt = {0};
status = rtw_hal_acs_mntr_result(phl_info->hal, &rpt);
if (idx >= MAX_CHANNEL_NUM) {
PHL_ERR("[ACS][%s] idx(%d) invalid\n", __func__, idx);
return;
}
if (status == RTW_HAL_STATUS_SUCCESS) {
acs->clm_ratio[idx] = rpt.clm_ratio;
acs->nhm_pwr[idx] = rpt.nhm_pwr;
}
}
u16 rtw_phl_acs_get_channel_by_idx(void *phl, u8 idx)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct auto_chan_sel *acs = &phl_info->acs;
if (idx >= MAX_CHANNEL_NUM) {
PHL_ERR("[ACS][%s] idx(%d) invalid\n", __func__, idx);
return 0;
}
return acs->chset[idx];
}
u8 rtw_phl_acs_get_clm_ratio_by_idx(void *phl, u8 idx)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct auto_chan_sel *acs = &phl_info->acs;
if (idx >= MAX_CHANNEL_NUM) {
PHL_ERR("%s [ACS] idx(%d) is invalid\n", __func__, idx);
return 0;
}
return acs->clm_ratio[idx];
}
s8 rtw_phl_noise_query_by_idx(void *phl, u8 idx)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct auto_chan_sel *acs = &phl_info->acs;
if (idx >= MAX_CHANNEL_NUM) {
PHL_ERR("%s [ACS] idx(%d) is invalid\n", __func__, idx);
return 0;
}
/* dBm = RPL - 110 */
return acs->nhm_pwr[idx] - 110;
}
#endif /* CONFIG_RTW_ACS */
void rtw_phl_get_env_rpt(void *phl, struct rtw_env_report *env_rpt, struct rtw_wifi_role_t *wrole)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
rtw_hal_env_rpt(hal_com, env_rpt, wrole);
}
|
2301_81045437/rtl8852be
|
phl/phl_acs.c
|
C
|
agpl-3.0
| 2,875
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_ACS_H_
#define _PHL_ACS_H_
/* avoid clm/nhm result not ready when scan done */
#define MONITOR_TIME_TOLERANCE 15
void phl_acs_mntr_trigger(struct phl_info_t *phl_info, u8 ch_idx, u16 channel, u16 monitor_time);
void phl_acs_mntr_result(struct phl_info_t *phl_info);
#endif /*_PHL_ACS_H_*/
|
2301_81045437/rtl8852be
|
phl/phl_acs.h
|
C
|
agpl-3.0
| 954
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_API_H_
#define _PHL_API_H_
u8 rtw_phl_read8(void *phl, u32 addr);
u16 rtw_phl_read16(void *phl, u32 addr);
u32 rtw_phl_read32(void *phl, u32 addr);
void rtw_phl_write8(void *phl, u32 addr, u8 val);
void rtw_phl_write16(void *phl, u32 addr, u16 val);
void rtw_phl_write32(void *phl, u32 addr, u32 val);
u32 rtw_phl_read_macreg(void *phl, u32 offset, u32 bit_mask);
void rtw_phl_write_macreg(void *phl,
u32 offset, u32 bit_mask, u32 data);
u32 rtw_phl_read_bbreg(void *phl, u32 offset, u32 bit_mask);
void rtw_phl_write_bbreg(void *phl,
u32 offset, u32 bit_mask, u32 data);
u32 rtw_phl_read_rfreg(void *phl,
enum rf_path path, u32 offset, u32 bit_mask);
void rtw_phl_write_rfreg(void *phl,
enum rf_path path, u32 offset, u32 bit_mask, u32 data);
enum rtw_phl_status rtw_phl_interrupt_handler(void *phl);
void rtw_phl_enable_interrupt(void *phl);
void rtw_phl_disable_interrupt(void *phl);
bool rtw_phl_recognize_interrupt(void *phl);
void rtw_phl_clear_interrupt(void *phl);
void rtw_phl_restore_interrupt(void *phl);
#ifdef PHL_PLATFORM_LINUX
void rtw_phl_mac_reg_dump(void *sel, void *phl);
void rtw_phl_bb_reg_dump(void *sel, void *phl);
void rtw_phl_bb_reg_dump_ex(void *sel, void *phl);
void rtw_phl_rf_reg_dump(void *sel, void *phl);
#endif
bool rtw_phl_get_sec_cam(void *phl, u16 num, u8 *buf, u16 size);
bool rtw_phl_get_addr_cam(void *phl, u16 num, u8 *buf, u16 size);
struct rtw_phl_com_t *rtw_phl_get_com(void *phl);
enum rtw_phl_status rtw_phl_init(void *drv_priv, void **phl,
struct rtw_ic_info *ic_info);
void rtw_phl_deinit(void *phl);
void rtw_phl_watchdog_init(void *phl,
u16 period,
void (*core_sw_wdog)(void *drv_priv),
void (*core_hw_wdog)(void *drv_priv));
void rtw_phl_watchdog_deinit(void *phl);
void rtw_phl_watchdog_start(void *phl);
void rtw_phl_watchdog_stop(void *phl);
enum rtw_phl_status rtw_phl_trx_alloc(void *phl);
void rtw_phl_trx_free(void *phl);
void rtw_phl_trx_free_handler(void *phl);
void rtw_phl_trx_free_sw_rsc(void *phl);
void rtw_phl_cap_pre_config(void *phl);
enum rtw_phl_status rtw_phl_preload(void *phl);
enum rtw_phl_status rtw_phl_start(void *phl);
void rtw_phl_stop(void *phl);
bool rtw_phl_is_init_completed(void *phl);
void rtw_phl_ps_set_rt_cap(void *phl, u8 band_idx, bool ps_allow, enum phl_ps_rt_rson rt_rson);
enum rtw_phl_status rtw_phl_ps_set_rf_state(void *phl, u8 band_idx, enum rtw_rf_state rf_state);
enum rtw_phl_status rtw_phl_suspend(void *phl, struct rtw_phl_stainfo_t *sta, u8 wow_en);
enum rtw_phl_status rtw_phl_resume(void *phl, struct rtw_phl_stainfo_t *sta, u8 *hw_reinit);
enum rtw_phl_status rtw_phl_tx_req_notify(void *phl);
enum rtw_phl_status rtw_phl_add_tx_req(void *phl, struct rtw_xmit_req *tx_req);
void rtw_phl_tx_stop(void *phl);
void rtw_phl_tx_resume(void *phl);
u16 rtw_phl_tring_rsc(void *phl, u16 macid, u8 tid);
u16 rtw_phl_query_new_rx_num(void *phl);
struct rtw_recv_pkt *rtw_phl_query_rx_pkt(void *phl);
void rtw_phl_rx_deferred_In_token(void *phl);
void rtw_phl_post_in_complete(void *phl, void *rxobj, u32 inbuf_len, u8 status_code);
enum rtw_phl_status rtw_phl_return_rxbuf(void *phl, u8* rxpkt);
enum rtw_phl_status rtw_phl_recycle_tx_buf(void *phl, u8 *tx_buf_ptr);
enum rtw_phl_status
rtw_phl_cmd_cfg_ampdu(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
void rtw_phl_proc_cmd(void *phl, char proc_cmd,
struct rtw_proc_cmd *incmd, char *output, u32 out_len);
void rtw_phl_get_fw_ver(void *phl, char *ver_str, u16 len);
/* command thread jobs */
enum rtw_phl_status rtw_phl_job_run_func(void *phl,
void *func, void *priv, void *parm, char *name);
/*WIFI Role management section*/
u8 rtw_phl_wifi_role_alloc(void *phl, u8 *mac_addr, enum role_type type,
u8 ridx, struct rtw_wifi_role_t **wifi_role, bool ignore_hw_fail);
enum rtw_phl_status
rtw_phl_cmd_wrole_change(void *phl,
struct rtw_wifi_role_t *wrole,
enum wr_chg_id chg_id, u8 *chg_info, u8 chg_info_len,
enum phl_cmd_type cmd_type, u32 cmd_timeout);
void rtw_phl_wifi_role_free(void *phl, u8 role_idx);
/*WIFI sta_info management section*/
struct rtw_phl_stainfo_t *
rtw_phl_alloc_stainfo_sw(void *phl,
u8 *sta_addr,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status
rtw_phl_free_stainfo_sw(void *phl, struct rtw_phl_stainfo_t *sta);
enum rtw_phl_status
rtw_phl_cmd_alloc_stainfo(void *phl,
struct rtw_phl_stainfo_t **sta,
u8 *sta_addr,
struct rtw_wifi_role_t *wrole,
bool alloc,
bool only_hw,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_change_stainfo(void *phl,
struct rtw_phl_stainfo_t *sta, enum sta_chg_id chg_id,
u8 *chg_info, u8 chg_info_len,
enum phl_cmd_type cmd_type, u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_update_media_status(void *phl,
struct rtw_phl_stainfo_t *sta,
u8 *sta_addr,
bool is_connect,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
struct rtw_phl_stainfo_t *
rtw_phl_get_stainfo_self(void *phl, struct rtw_wifi_role_t *wrole);
struct rtw_phl_stainfo_t *
rtw_phl_get_stainfo_by_addr(void *phl, struct rtw_wifi_role_t *wrole, u8 *addr);
struct rtw_phl_stainfo_t *
rtw_phl_get_stainfo_by_macid(void *phl, u16 macid);
u8
rtw_phl_get_sta_rssi(struct rtw_phl_stainfo_t *sta);
enum rtw_phl_status
rtw_phl_query_rainfo(void *phl, struct rtw_phl_stainfo_t *phl_sta,
struct rtw_phl_rainfo *ra_info);
void rtw_phl_sta_up_rx_bcn(void *phl, struct rtw_bcn_pkt_info *info);
/*macid management section, temporary for debuge*/
u16
rtw_phl_get_macid_max_num(void *phl);
u16
rtw_phl_wrole_bcmc_id_get(void *phl, struct rtw_wifi_role_t *wrole);
u8
rtw_phl_macid_is_bmc(void *phl, u16 macid);
u8
rtw_phl_macid_is_used(void *phl, u16 macid);
enum rtw_phl_status
rtw_phl_cmd_add_key(void *phl,
struct rtw_phl_stainfo_t *sta,
struct phl_sec_param_h *crypt,
u8 *keybuf,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_del_key(void *phl,
struct rtw_phl_stainfo_t *sta,
struct phl_sec_param_h *crypt,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
/* phy msg forwarder functions*/
enum rtw_phl_status rtw_phl_msg_hub_register_recver(void* phl,
struct phl_msg_receiver* ctx, enum phl_msg_recver_layer layer);
enum rtw_phl_status rtw_phl_msg_hub_update_recver_mask(void* phl,
enum phl_msg_recver_layer layer, u8* mdl_id, u32 len, u8 clr);
enum rtw_phl_status rtw_phl_msg_hub_deregister_recver(void* phl,
enum phl_msg_recver_layer layer);
enum rtw_phl_status rtw_phl_msg_hub_send(void* phl,
struct phl_msg_attribute* attr, struct phl_msg* msg);
u8 rtw_phl_trans_sec_mode(u8 unicast, u8 multicast);
u8 rtw_phl_get_sec_cam_idx(void *phl, struct rtw_phl_stainfo_t *sta,
u8 keyid, u8 key_type);
void rtw_phl_test_txtb_cfg(struct rtw_phl_com_t* phl_com, void *buf,
u32 buf_len, u8 *cfg_bssid, u16 cfg_aid, u8 cfg_bsscolor);
/* command dispatcher module section*/
enum rtw_phl_status rtw_phl_register_module(void *phl, u8 band_idx,
enum phl_module_id id,
struct phl_bk_module_ops* ops);
enum rtw_phl_status rtw_phl_deregister_module(void *phl,u8 band_idx,
enum phl_module_id id);
u8 rtw_phl_is_fg_empty(void *phl, u8 band_idx);
/* opt: refer to enum phl_msg_opt */
enum rtw_phl_status rtw_phl_send_msg_to_dispr(void *phl, struct phl_msg* msg,
struct phl_msg_attribute* attr, u32* msg_hdl);
enum rtw_phl_status rtw_phl_cancel_dispr_msg(void *phl, u8 band_idx, u32* msg_hdl);
enum rtw_phl_status rtw_phl_add_cmd_token_req(void *phl, u8 band_idx,
struct phl_cmd_token_req* req, u32* req_hdl);
enum rtw_phl_status rtw_phl_cancel_cmd_token(void *phl, u8 band_idx, u32* req_hdl);
enum rtw_phl_status rtw_phl_set_cur_cmd_info(void *phl, u8 band_idx,
struct phl_module_op_info* op_info);
enum rtw_phl_status rtw_phl_query_cur_cmd_info(void *phl, u8 band_idx,
struct phl_module_op_info* op_info);
enum rtw_phl_status rtw_phl_free_cmd_token(void *phl, u8 band_idx, u32* req_hdl);
enum rtw_phl_status rtw_phl_set_bk_module_info(void *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info* op_info);
enum rtw_phl_status rtw_phl_query_bk_module_info(void *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info* op_info);
enum rtw_phl_status rtw_phl_set_msg_disp_seq(void *phl,
struct phl_msg_attribute *attr,
struct msg_self_def_seq* seq);
/* BA session management */
void rtw_phl_stop_rx_ba_session(void *phl, struct rtw_phl_stainfo_t *sta,
u16 tid);
enum rtw_phl_status
rtw_phl_start_rx_ba_session(void *phl, struct rtw_phl_stainfo_t *sta,
u8 dialog_token, u16 timeout, u16 start_seq_num,
u16 ba_policy, u16 tid, u16 buf_size);
void rtw_phl_rx_bar(void *phl, struct rtw_phl_stainfo_t *sta, u8 tid, u16 seq);
enum rtw_phl_status
rtw_phl_enter_mon_mode(void *phl, struct rtw_wifi_role_t *wrole);
enum rtw_phl_status
rtw_phl_leave_mon_mode(void *phl, struct rtw_wifi_role_t *wrole);
#ifdef RTW_PHL_BCN
enum rtw_phl_status rtw_phl_free_bcn_entry(void *phl, struct rtw_wifi_role_t *wrole);
enum rtw_phl_status
rtw_phl_cmd_issue_beacon(void *phl,
struct rtw_wifi_role_t *wifi_role,
struct rtw_bcn_info_cmn *bcn_cmn,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_stop_beacon(void *phl,
struct rtw_wifi_role_t *wifi_role,
u8 stop,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
#endif
#ifdef CONFIG_CMD_DISP
enum rtw_phl_status
rtw_phl_cmd_chg_op_chdef(struct rtw_wifi_role_t *wrole,
struct rtw_chan_def *new_chdef, bool cmd_wait, u32 cmd_timeout,
void (*chg_opch_done)(void *priv, u8 ridx, enum rtw_phl_status status));
enum rtw_phl_status
rtw_phl_cmd_set_ch_bw(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chdef,
bool do_rfk,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_enqueue(void *phl,
enum phl_band_idx band_idx,
enum phl_msg_evt_id evt_id,
u8 *cmd_buf,
u32 cmd_len,
void (*core_cmd_complete)(void *priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status),
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
#endif /*CONFIG_CMD_DISP*/
u8 rtw_phl_get_cur_ch(struct rtw_wifi_role_t *wifi_role);
enum rtw_phl_status
rtw_phl_get_cur_hal_chdef(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *cur_chandef);
enum band_type rtw_phl_get_band_type(u8 chan);
u8 rtw_phl_get_center_ch(u8 ch,
enum channel_width bw, enum chan_offset offset);
enum rtw_phl_status
rtw_phl_cmd_dfs_tx_pause(struct rtw_wifi_role_t *wifi_role, bool pause,
enum phl_cmd_type cmd_type, u32 cmd_timeout);
u8
rtw_phl_get_operating_class(
struct rtw_chan_def chan_def
);
bool
rtw_phl_get_chandef_from_operating_class(
u8 channel,
u8 operating_class,
struct rtw_chan_def *chan_def
);
/*
* export API from sw cap module
*/
void rtw_phl_final_cap_decision(void *phl);
enum rtw_phl_status
rtw_phl_get_dft_proto_cap(void *phl, u8 hw_band, enum role_type rtype,
struct protocol_cap_t *role_proto_cap);
enum rtw_phl_status
rtw_phl_get_dft_cap(void *phl, u8 hw_band, struct role_cap_t *role_cap);
void rtw_phl_mac_dbg_status_dump(void *phl, u32 *val, u8 *en);
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_phl_status
rtw_phl_dbcc_test(void *phl, enum dbcc_test_id id, void *param);
#endif
/*
* API for config channel info CR
*/
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_phl_status
rtw_phl_cmd_cfg_chinfo(void *phl, struct rtw_phl_stainfo_t *sta,
u8 enable, enum phl_cmd_type cmd_type, u32 cmd_timeout);
enum rtw_phl_status rtw_phl_query_chan_info(void *phl, u32 buf_len,
u8* chan_info_buffer, u32 *length, struct csi_header_t *csi_header);
#endif /* CONFIG_PHL_CHANNEL_INFO */
void rtw_phl_set_edcca_mode(void *phl, enum rtw_edcca_mode mode);
enum rtw_edcca_mode rtw_phl_get_edcca_mode(void *phl);
bool rtw_phl_set_user_def_chplan(void *phl, struct rtw_user_def_chplan *udef);
bool rtw_phl_valid_regulation_domain(u8 domain);
bool rtw_phl_regulation_set_domain(void *phl, u8 domain,
enum regulation_rsn reason);
bool rtw_phl_regulation_set_country(void *phl, char *country,
enum regulation_rsn reason);
bool rtw_phl_regulation_set_capability(void *phl,
enum rtw_regulation_capability capability);
bool rtw_phl_regulation_query_chplan(
void *phl, enum rtw_regulation_query type,
struct rtw_chlist *filter,
struct rtw_regulation_chplan *plan);
bool rtw_phl_query_specific_chplan(void *phl, u8 domain,
struct rtw_regulation_chplan *plan);
bool rtw_phl_query_country_chplan(char *country,
struct rtw_regulation_country_chplan *country_chplan);
bool rtw_phl_generate_scan_instance(struct instance_strategy *strategy,
struct rtw_regulation_chplan *chplan,
struct instance *inst);
bool rtw_phl_scan_instance_insert_ch(void *phl, struct instance *inst,
enum band_type band, u8 channel,
u8 strategy_period);
bool rtw_phl_regulation_valid_channel(void *phl, enum band_type band,
u16 channel, u8 reject);
bool rtw_phl_regulation_dfs_channel(void *phl, enum band_type band,
u16 channel, bool *dfs);
bool rtw_phl_query_regulation_info(void *phl, struct rtw_regulation_info *info);
bool rtw_phl_regulation_query_ch(void *phl, enum band_type band, u8 channel,
struct rtw_regulation_channel *ch);
u8 rtw_phl_get_domain_regulation_2g(u8 domain);
u8 rtw_phl_get_domain_regulation_5g(u8 domain);
enum rtw_phl_status rtw_phl_get_mac_addr_efuse(void* phl, u8 *addr);
/**
* rtw_phl_usb_tx_ep_id - query USB tx end point index
* identified by macid, tid and band
* @macid: input target macid is 0 ~ 127
* @tid: input target tid, range is 0 ~ 7
* @band: input target band, 0 for band 0 / 1 for band 1
*
* returns corresponding end point idx of a specific tid
*/
u8 rtw_phl_usb_tx_ep_id(void *phl, u16 macid, u8 tid, u8 band);
enum rtw_phl_status
rtw_phl_cfg_trx_path(void* phl, enum rf_path tx, u8 tx_nss,
enum rf_path rx, u8 rx_nss);
void rtw_phl_reset_stat_ma_rssi(struct rtw_phl_com_t *phl_com);
u8
rtw_phl_get_ma_rssi(struct rtw_phl_com_t *phl_com,
enum rtw_rssi_type rssi_type);
bool rtw_phl_chanctx_chk(void *phl, struct rtw_wifi_role_t *wifi_role,
u8 chan, enum channel_width bw, enum chan_offset offset);
bool rtw_phl_chanctx_add(void *phl, struct rtw_wifi_role_t *wifi_role,
u8 *chan, enum channel_width *bw, enum chan_offset *offset);
int rtw_phl_chanctx_del(void *phl, struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chan_def);
enum rtw_phl_status rtw_phl_chanctx_del_no_self(void *phl, struct rtw_wifi_role_t *wifi_role);
int rtw_phl_mr_get_chanctx_num(void *phl, struct rtw_wifi_role_t *wifi_role);
enum rtw_phl_status rtw_phl_mr_get_chandef(void *phl, struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chandef);
enum rtw_phl_status rtw_phl_mr_upt_chandef(void *phl, struct rtw_wifi_role_t *wifi_role);
#ifdef CONFIG_MCC_SUPPORT
u8 rtw_phl_mr_query_mcc_inprogress (void *phl, struct rtw_wifi_role_t *wrole,
enum rtw_phl_mcc_chk_inprocess_type check_type);
#endif
u8 rtw_phl_mr_dump_mac_addr(void *phl,
struct rtw_wifi_role_t *wifi_role);
u8 rtw_phl_mr_buddy_dump_mac_addr(void *phl,
struct rtw_wifi_role_t *wifi_role);
enum rtw_phl_status
rtw_phl_mr_rx_filter(void *phl, struct rtw_wifi_role_t *wrole);
#ifdef CONFIG_FSM
enum rtw_phl_status
rtw_phl_mr_offch_hdl(void *phl,
struct rtw_wifi_role_t *wrole,
bool off_ch,
void *obj_priv,
u8 (*issue_null_data)(void *priv, u8 ridx, bool ps),
struct rtw_chan_def *chandef);
#endif
void rtw_phl_mr_ops_init (void *phl, struct rtw_phl_mr_ops *mr_ops);
#ifdef PHL_MR_PROC_CMD
void rtw_phl_mr_dump_info(void *phl, bool show_caller);
void rtw_phl_mr_dump_band_ctl(void *phl, bool show_caller);
bool rtw_phl_chanctx_test(void *phl, struct rtw_wifi_role_t *wifi_role, bool is_add,
u8 *chan, enum channel_width *bw, enum chan_offset *offset);
#endif
void rtw_phl_sta_dump_info(void *phl, bool show_caller, struct rtw_wifi_role_t *wr, u8 mode);
bool rtw_phl_mr_query_info(void *phl, struct rtw_wifi_role_t *wrole,
struct mr_query_info *info);
u8 rtw_phl_mr_get_opch_list(void *phl, struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chdef_list, u8 list_size);
void rtw_phl_mr_dump_cur_chandef(void *phl, struct rtw_wifi_role_t *wifi_role);
enum mr_op_mode
rtw_phl_mr_get_opmode(void *phl, struct rtw_wifi_role_t *wrole);
void rtw_phl_led_set_ctrl_mode(void *phl, enum rtw_led_id led_id,
enum rtw_led_ctrl_mode ctrl_mode);
void rtw_phl_led_set_toggle_intervals(void *phl, u8 intervals_idx,
u32 *intervals, u8 intervals_len);
void rtw_phl_led_set_action(void *phl, enum rtw_led_event event,
enum rtw_led_state state_condition,
struct rtw_led_action_args_t *action_args_arr,
u8 action_args_arr_len, u32 toggle_delay_unit);
void rtw_phl_led_control(void *phl, enum rtw_led_event led_event);
#ifdef CONFIG_RTW_ACS
u16 rtw_phl_acs_get_channel_by_idx(void *phl, u8 ch_idx);
u8 rtw_phl_acs_get_clm_ratio_by_idx(void *phl, u8 ch_idx);
s8 rtw_phl_noise_query_by_idx(void *phl, u8 ch_idx);
#endif /* CONFIG_RTW_ACS */
void rtw_phl_get_env_rpt(void *phl, struct rtw_env_report *env_rpt, struct rtw_wifi_role_t *wrole);
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
enum rtw_phl_status
rtw_phl_bfee_ctrl(void *phl, struct rtw_wifi_role_t *wrole, bool ctrl);
#endif
enum rtw_phl_status
rtw_phl_snd_init_ops_send_ndpa(void *phl,
enum rtw_phl_status (*snd_send_ndpa)(void *,
struct rtw_wifi_role_t *,
u8 *,
u32 *,
enum channel_width));
u8 rtw_phl_snd_chk_in_progress(void *phl);
enum rtw_phl_status
rtw_phl_sound_start(void *phl, u8 wrole_idx, u8 st_dlg_tkn, u8 period, u8 test_flag);
enum rtw_phl_status
rtw_phl_sound_abort(void *phl);
enum rtw_phl_status
rtw_phl_set_power_lmt(void *phl, u8 hw_band);
s8 rtw_phl_get_power_limit(void *phl, u8 hw_band,
u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel);
void
rtw_phl_enable_ext_pwr_lmt(void *phl, u8 hw_band,
struct rtw_phl_ext_pwr_lmt_info *ext_pwr_lmt_info);
void rtw_phl_init_ppdu_sts_para(struct rtw_phl_com_t *phl_com,
bool en_psts_per_pkt, bool psts_ampdu,
u8 rx_fltr);
enum rtw_phl_status rtw_phl_rf_on(void *phl);
enum rtw_phl_status rtw_phl_rf_off(void *phl);
#ifdef CONFIG_PHL_TWT
enum rtw_phl_status
rtw_phl_twt_alloc_twt_config(void *phl, struct rtw_wifi_role_t *role,
struct rtw_phl_twt_setup_info setup_info, u8 benable, u8 *id);
enum rtw_phl_status
rtw_phl_twt_free_twt_config(void *phl, u8 id);
enum rtw_phl_status
rtw_phl_twt_enable_twt_config(void *phl, u8 id);
enum rtw_phl_status
rtw_phl_twt_free_all_twt_by_role(void *phl, struct rtw_wifi_role_t *role);
enum rtw_phl_status
rtw_phl_twt_disable_all_twt_by_role(void *phl, struct rtw_wifi_role_t *role);
enum rtw_phl_status
rtw_phl_twt_enable_all_twt_by_role(void *phl, struct rtw_wifi_role_t *role);
enum rtw_phl_status
rtw_phl_twt_add_sta_info(void *phl, struct rtw_phl_stainfo_t *phl_sta,
u8 config_id, u8 id);
enum rtw_phl_status
rtw_phl_twt_teardown_sta(void *phl, struct rtw_phl_stainfo_t *phl_sta,
struct rtw_phl_twt_flow_field *twt_flow, u8 *bitmap);
enum rtw_phl_status
rtw_phl_twt_get_new_flow_id(void *phl, struct rtw_phl_stainfo_t *phl_sta, u8 *id);
enum rtw_phl_status
rtw_phl_twt_accept_for_sta_mode(void *phl, struct rtw_phl_stainfo_t *phl_sta,
struct rtw_phl_twt_setup_info *setup_info, u8 *id);
enum rtw_phl_status
rtw_phl_twt_teardown_for_sta_mode(void *phl, struct rtw_phl_stainfo_t *phl_sta,
struct rtw_phl_twt_flow_field *twt_flow);
enum rtw_phl_status
rtw_phl_twt_delete_all_sta_info(void *phl, struct rtw_phl_stainfo_t *phl_sta,
u8 *bitmap);
enum rtw_phl_status
rtw_phl_twt_get_target_wake_time(void *phl, u8 port, u8 id, u16 offset, u32 *tsf_h,
u32 *tsf_l);
enum rtw_phl_status
rtw_phl_twt_sta_announce_to_fw(void *phl, u16 macid);
enum rtw_phl_status
rtw_phl_twt_handle_c2h(void *phl_com, void *c);
enum rtw_phl_status
rtw_phl_twt_fill_twt_element(struct rtw_phl_twt_element *twt_ele, u8 *buf,
u8 *length);
enum rtw_phl_status
rtw_phl_twt_fill_flow_field(struct rtw_phl_twt_flow_field *twt_flow, u8 *buf,
u16 *length);
enum rtw_phl_status
rtw_phl_twt_parse_element(u8 *twt_ele, u16 length,
struct rtw_phl_twt_element *twt_element);
enum rtw_phl_status
rtw_phl_twt_parse_setup_info(u8 *pkt, u16 length,
struct rtw_phl_twt_setup_info *setup_info);
enum rtw_phl_status
rtw_phl_twt_parse_flow_field(u8 *ie_twt_flow, u16 length,
struct rtw_phl_twt_flow_field *twt_flow);
#endif /* CONFIG_PHL_TWT */
enum rtw_phl_status
rtw_phl_snd_cmd_set_vht_gid(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_gid_pos_tbl *tbl);
enum rtw_phl_status
rtw_phl_snd_cmd_set_aid(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta,
u16 aid);
#ifdef RTW_WKARD_P2PPS_REFINE
#ifdef CONFIG_PHL_P2PPS
enum rtw_phl_status
rtw_phl_p2pps_noa_update(void *phl, struct rtw_phl_noa_desc *in_desc);
void
rtw_phl_p2pps_init_ops(void *phl, struct rtw_phl_p2pps_ops *ops);
void rtw_phl_p2pps_noa_disable_all(void *phl, struct rtw_wifi_role_t *w_role);
#endif
#endif
enum rtw_phl_status
rtw_phl_snd_cmd_set_vht_gid(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_gid_pos_tbl *tbl);
void rtw_phl_event_notify(void *phl, enum phl_msg_evt_id event,
struct rtw_wifi_role_t *wrole);
void rtw_phl_notification(void *phl,
enum phl_msg_evt_id event,
struct rtw_wifi_role_t *wrole);
void rtw_phl_dev_terminate_ntf(void *phl);
enum rtw_phl_status
rtw_phl_cmd_force_usb_switch(void *phl, u32 speed,
enum phl_band_idx band_idx,
enum phl_cmd_type cmd_type, u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_get_usb_speed(void *phl, u32* speed,
enum phl_band_idx band_idx,
enum phl_cmd_type cmd_type, u32 cmd_timeout);
enum rtw_phl_status
rtw_phl_cmd_get_usb_support_ability(void *phl, u32* ability,
enum phl_band_idx band_idx,
enum phl_cmd_type cmd_type, u32 cmd_timeout);
u8 rtw_phl_get_sta_mgnt_rssi(struct rtw_phl_stainfo_t *psta);
enum rtw_phl_status
rtw_phl_txsts_rpt_config(void *phl, struct rtw_phl_stainfo_t *phl_sta);
#ifdef CONFIG_USB_HCI
/* tx_ok/tx_fail are from release report*/
enum rtw_phl_status
rtw_phl_get_tx_ok_rpt(void *phl, struct rtw_phl_stainfo_t *phl_sta, u32 *tx_ok_cnt,
enum phl_ac_queue qsel);
enum rtw_phl_status
rtw_phl_get_tx_fail_rpt(void *phl, struct rtw_phl_stainfo_t *phl_sta, u32 *tx_fail_cnt,
enum phl_ac_queue qsel);
/* tx retry is from ra sts report.*/
enum rtw_phl_status
rtw_phl_get_tx_retry_rpt(void *phl, struct rtw_phl_stainfo_t *phl_sta, u32 *tx_retry_cnt,
enum phl_ac_queue qsel);
#endif /* CONFIG_USB_HCI */
void rtw_phl_dbg_dump_rx(void *phl, struct rtw_wifi_role_t *wrole);
/******************************************************************************
*
* TX power APIs
*
*****************************************************************************/
const char *rtw_phl_get_pw_lmt_regu_type_str(void *phl, enum band_type band);
bool rtw_phl_get_pwr_lmt_en(void *phl, u8 band_idx);
enum rtw_phl_status rtw_phl_set_tx_power(void *phl, u8 band_idx);
#endif /*_PHL_API_H_*/
|
2301_81045437/rtl8852be
|
phl/phl_api.h
|
C
|
agpl-3.0
| 24,882
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_API_DRV_C_
#include "phl_headers.h"
void *rtw_phl_get_txbd_buf(struct rtw_phl_com_t *phl_com)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
return phl_info->hci_trx_ops->get_txbd_buf(phl_info);
}
void *rtw_phl_get_rxbd_buf(struct rtw_phl_com_t *phl_com)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
return phl_info->hci_trx_ops->get_rxbd_buf(phl_info);
}
struct rtw_h2c_pkt *rtw_phl_query_h2c_pkt(struct rtw_phl_com_t *phl_com,
enum rtw_h2c_pkt_type type)
{
struct rtw_h2c_pkt *h2c_pkt = NULL;
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
h2c_pkt = (struct rtw_h2c_pkt *)phl_query_idle_h2c_pkt(phl_info, type);
if (!h2c_pkt)
phl_dump_h2c_pool_stats(phl_info->h2c_pool);
return h2c_pkt;
}
enum rtw_phl_status rtw_phl_pltfm_tx(struct rtw_phl_com_t *phl_com,
struct rtw_h2c_pkt *pkt)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
#ifdef CONFIG_PCI_HCI
struct phl_hci_trx_ops *hci_trx_ops = phl_info->hci_trx_ops;
hci_trx_ops->recycle_busy_h2c(phl_info);
#endif
pstatus = phl_info->hci_trx_ops->pltfm_tx(phl_info, pkt);
return pstatus;
}
void rtw_phl_proc_cmd(void *phl, char proc_cmd,
struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct hal_info_t *hal_info = (struct hal_info_t *)phl_info->hal;
if (RTW_PROC_CMD_PHL == proc_cmd)
rtw_phl_dbg_proc_cmd(phl_info, incmd, output, out_len);
else if (RTW_PROC_CMD_CORE == proc_cmd)
rtw_phl_dbg_core_cmd(phl_info, incmd, output, out_len);
else
rtw_hal_proc_cmd(hal_info, proc_cmd, incmd, output, out_len);
}
void rtw_phl_get_fw_ver(void *phl, char *ver_str, u16 len)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
rtw_hal_get_fw_ver(phl_info->hal, ver_str, len);
}
enum rtw_phl_status rtw_phl_msg_hub_hal_send(struct rtw_phl_com_t *phl_com,
struct phl_msg_attribute* attr, struct phl_msg* msg)
{
return phl_msg_hub_send((struct phl_info_t*)phl_com->phl_priv, attr, msg);
}
void rtw_phl_test_txtb_cfg(struct rtw_phl_com_t* phl_com,
void *buf, u32 buf_len, u8 *cfg_bssid, u16 cfg_aid, u8 cfg_bsscolor)
{
/* Get parameters from MP UL */
u8 ui_bssid[6]={0x00, 0x09, 0x08, 0x07, 0x06, 0x05};
u16 ui_aid = 2;
u8 ui_bsscolor = 1;
u8 cfg;
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
struct rtw_wifi_role_t *role = &phl_com->wifi_roles[0];
struct rtw_phl_stainfo_t *sta = rtw_phl_get_stainfo_self(
phl_com->phl_priv, role);
cfg = (u8)*((u8 *)buf);
switch (cfg) {
case 0:
/* disable */
role->mstate = MLME_NO_LINK;
_os_mem_cpy(phlcom_to_drvpriv(phl_com), sta->mac_addr,
role->mac_addr, MAC_ALEN);
rtw_hal_update_sta_entry(phl_info->hal, sta, false);
rtw_hal_role_cfg(phl_info->hal, role);
break;
case 1:
role->mstate = MLME_LINKED;
_os_mem_cpy(phlcom_to_drvpriv(phl_com), sta->mac_addr,
cfg_bssid, MAC_ALEN);
sta->wmode = WLAN_MD_MAX;
sta->aid = cfg_aid;
sta->asoc_cap.bsscolor = cfg_bsscolor;
sta->asoc_cap.pkt_padding = 2;
rtw_hal_update_sta_entry(phl_info->hal, sta, false);
rtw_hal_role_cfg(phl_info->hal, role);
break;
case 2:
role->mstate = MLME_LINKED;
_os_mem_cpy(phlcom_to_drvpriv(phl_com), sta->mac_addr,
ui_bssid, MAC_ALEN);
sta->wmode = WLAN_MD_MAX;
sta->aid = ui_aid;
sta->asoc_cap.bsscolor = ui_bsscolor;
sta->asoc_cap.pkt_padding = 2;
rtw_hal_update_sta_entry(phl_info->hal, sta, false);
rtw_hal_role_cfg(phl_info->hal, role);
break; default:
break;
}
}
void rtw_phl_pkt_ofld_reset_all_entry(struct rtw_phl_com_t* phl_com)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
phl_pkt_ofld_reset_all_entry(phl_info);
}
void rtw_phl_dbg_dump_rx(void *phl, struct rtw_wifi_role_t *wrole)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
phl_rx_dbg_dump(phl_info, wrole->hw_band);
}
|
2301_81045437/rtl8852be
|
phl/phl_api_drv.c
|
C
|
agpl-3.0
| 4,685
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_API_DRV_H_
#define _PHL_API_DRV_H_
void *rtw_phl_get_txbd_buf(struct rtw_phl_com_t *phl_com);
void *rtw_phl_get_rxbd_buf(struct rtw_phl_com_t *phl_com);
/**
* rtw_phl_query_h2c_pkt - provide h2c buffer for halmac
* @phl_com: see struct rtw_phl_com_t
* @type: the type of h2c buf
*
* returns struct rtw_h2c_pkt*
*/
struct rtw_h2c_pkt *rtw_phl_query_h2c_pkt(struct rtw_phl_com_t *phl_com,
enum rtw_h2c_pkt_type type);
/**
* rtw_phl_pltfm_tx - h2c platform transmit
* @phl_com: see struct rtw_phl_com_t
* @pkt: the h2c pkt
*
* returns enum RTW_PHL_STATUS
*/
enum rtw_phl_status rtw_phl_pltfm_tx(struct rtw_phl_com_t *phl_com,
struct rtw_h2c_pkt *pkt);
enum rtw_phl_status rtw_phl_msg_hub_hal_send(struct rtw_phl_com_t *phl_com,
struct phl_msg_attribute* attr, struct phl_msg* msg);
struct rtw_phl_stainfo_t *
rtw_phl_get_stainfo_self(void *phl, struct rtw_wifi_role_t *wrole);
struct rtw_phl_stainfo_t *
rtw_phl_get_stainfo_by_macid(void *phl, u16 macid);
/* For hal wow use */
void rtw_phl_pkt_ofld_reset_all_entry(struct rtw_phl_com_t *phl_com);
bool rtw_phl_query_regulation_info(void *phl, struct rtw_regulation_info *info);
enum band_type rtw_phl_get_band_type(u8 chan);
u8 rtw_phl_get_center_ch(u8 ch,
enum channel_width bw, enum chan_offset offset);
bool rtw_phl_btc_send_cmd(struct rtw_phl_com_t *phl_com,
u8 *buf, u32 len, u16 ev_id);
#ifdef CONFIG_PHL_CHANNEL_INFO
/* Channel info queue operation*/
u32 rtw_phl_get_chaninfo_idle_number(void *drvpriv, struct rtw_phl_com_t *phl_com);
u32 rtw_phl_get_chaninfo_busy_number(void *drvpriv, struct rtw_phl_com_t *phl_com);
struct chan_info_t *rtw_phl_query_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com);
struct chan_info_t *rtw_phl_query_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com);
struct chan_info_t *rtw_phl_query_busy_chaninfo_latest(void *drvpriv, struct rtw_phl_com_t *phl_com);
void rtw_phl_enqueue_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com,
struct chan_info_t *chan_info_pkt);
struct chan_info_t * rtw_phl_recycle_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com,
struct chan_info_t *chan_info_pkt);
#endif /* CONFIG_PHL_CHANNEL_INFO */
enum rtw_phl_status rtw_phl_ser_l2_notify(struct rtw_phl_com_t *phl_com);
#ifdef CONFIG_CMD_DISP
enum rtw_phl_status
rtw_phl_cmd_notify(struct rtw_phl_com_t *phl_com,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx);
#endif /* CONFIG_CMD_DISP */
enum rtw_phl_status phl_ps_hal_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req);
#endif /* _PHL_API_DRV_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_api_drv.h
|
C
|
agpl-3.0
| 3,318
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHL_BTC_H__
#define __PHL_BTC_H__
/* For EXTERNAL application to notify btc (expose) */
/* @phl: refer to phl_infi_t
* @notify: notification event
* @ntfy: notify information (optional)
* return value:
* 0: no wait
* 1: have to wait call back info->ntfy_cb()
* -1: Failure
*/
int rtw_phl_btc_notify(void *phl, enum RTW_PHL_BTC_NOTIFY notify,
struct rtw_phl_btc_ntfy *info);
void rtw_phl_btc_role_notify(void *phl, u8 role_id, enum role_state rstate);
void rtw_phl_btc_hub_msg_hdl(void *phl, struct phl_msg *msg);
void rtw_phl_btc_packet_event_notify(void *phl, u8 role_id, u8 pkt_evt_type);
u8 rtw_phl_btc_pkt_2_evt_type(u8 packet_type);
#endif /* __PHL_BTC_H__ */
|
2301_81045437/rtl8852be
|
phl/phl_btc.h
|
C
|
agpl-3.0
| 1,343
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHL_BTC_DEF_H__
#define __PHL_BTC_DEF_H__
#define RTW_PHL_BTC_CTRL_BUF 40
#define RTW_PHL_BTC_FWINFO_BUF 1280
/*****************************************
* Please contact the member of BTC submodule if you
* need to revise this section
*****************************************/
#define RTW_BTINFO_MAXLEN 10
#define RTW_SCBD_MAXLEN 10
#define BTC_C2H_CAT 2 /* C2H Category for OutSrc */
#define BTC_CLASS_MIN 0x10
#define BTC_CLASS_FEV 0x12
#define BTC_CLASS_MAX 0x17
enum {
BTC_FEV_REPORT = 0,
BTC_FEV_BT_INFO = 1,
BTC_FEV_BT_SCBD = 2,
BTC_FEV_BT_REG = 3
};
/*****************************************/
enum {
BTC_HMSG_TMR_EN = 0x0,
BTC_HMSG_BT_REG_READBACK = 0x1,
BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
BTC_HMSG_FW_EV = 0x3,
BTC_HMSG_BT_LINK_CHG = 0x4,
BTC_HMSG_MAX
};
enum {
BTC_CTRL_TYPE_MANUAL,
BTC_CTRL_TYPE_EN_REPORT,
BTC_CTRL_TYPE_SET_SLOTS,
BTC_CTRL_TYPE_SET_MREGS,
BTC_CTRL_TYPE_SET_TDMA,
BTC_CTRL_TYPE_SET_1SLOT,
BTC_CTRL_TYPE_SET_POLICY,
BTC_CTRL_TYPE_SET_GPIO_DBG,
BTC_CTRL_TYPE_SEND_HUB_MSG,
BTC_CTRL_TYPE_TEST,
BTC_CTRL_TYPE_MAX
};
enum {
BTC_TIMER_PERIODIC,
BTC_TIMER_WL_SPECPKT,
BTC_TIMER_WL_RFKTO,
BTC_TIMER_BT_A2DPPLAY,
BTC_TIMER_MAX
};
enum RTW_PHL_BTC_CTRL_TYPE {
PHL_BTC_CTRL_MANUAL,
PHL_BTC_CTRL_MAX
};
enum {
PHL_BTC_CNTFY_BTINFO,
PHL_BTC_CNTFY_MAX
};
enum PHL_BTC_NTFY_REASON {
PHL_BTC_NTFY_RSN_PERIOTIC
};
enum RTW_PHL_BTC_NOTIFY {
PHL_BTC_NTFY_SCAN_START,
PHL_BTC_NTFY_SCAN_STOP,
PHL_BTC_NTFY_COEX_INFO,
PHL_BTC_NTFY_ROLE_INFO,
PHL_BTC_NTFY_CTRL,
PHL_BTC_NTFY_FWINFO,
PHL_BTC_NTFY_RADIO_STATE,
PHL_BTC_NTFY_WLSTA,
PHL_BTC_NTFY_PACKET_EVT,
PHL_BTC_NTFY_TIMER,
PHL_BTC_NTFY_MAX
};
enum {
BTC_MODE_NORMAL,
BTC_MODE_WL,
BTC_MODE_BT,
BTC_MODE_WLOFF,
BTC_MODE_MAX
};
enum {
BTC_RFCTRL_WL_OFF,
BTC_RFCTRL_WL_ON,
BTC_RFCTRL_LPS_WL_ON,
BTC_RFCTRL_FW_CTRL,
BTC_RFCTRL_MAX
};
struct rtw_phl_btc_ops {
void (*print)(const char *msg);
};
struct rtw_phl_btc_coex_info_param {
u8 query_type;
};
struct rtw_phl_btc_role_info_param {
u8 role_id;
enum role_state rstate;
};
struct rtw_phl_btc_wl_sta_param {
u8 role_id;
u16 mac_id;
u8 reason;
};
struct rtw_phl_btc_pkt_param {
u8 role_id;
u8 pkt_evt_type;
};
struct rtw_phl_btc_ctrl_param {
u8 type;
u16 len;
u8 buf[RTW_PHL_BTC_CTRL_BUF];
};
struct rtw_phl_btc_fwinfo_param {
u8 c2h_class;
u8 c2h_func;
};
struct rtw_phl_btc_radio_state_param {
u8 rf_on;
};
struct rtw_phl_btc_tmr_param {
void *timer;
};
struct rtw_phl_btc_ntfy {
enum RTW_PHL_BTC_NOTIFY notify;
struct rtw_phl_btc_ops *ops;
/* real parameter for different notifications */
union {
struct rtw_phl_btc_coex_info_param cinfo;
struct rtw_phl_btc_role_info_param rinfo;
struct rtw_phl_btc_ctrl_param ctrl;
struct rtw_phl_btc_radio_state_param rfst;
struct rtw_phl_btc_fwinfo_param finfo;
struct rtw_phl_btc_wl_sta_param wsta;
struct rtw_phl_btc_pkt_param pkt;
struct rtw_phl_btc_tmr_param tmr;
} u;
void *priv;
int (*ntfy_cb)(void *priv, enum RTW_PHL_BTC_NOTIFY ntfy,
struct rtw_phl_btc_ntfy *info);
};
#endif /* __PHL_BTC_DEF_H__ */
|
2301_81045437/rtl8852be
|
phl/phl_btc_def.h
|
C
|
agpl-3.0
| 3,736
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "phl_headers.h"
#ifdef CONFIG_FSM
#include "phl_btc_fsm.h"
struct btc_obj {
struct fsm_main *fsm;
struct fsm_obj *fsm_obj;
struct phl_info_t *phl_info;
struct rtw_phl_btc_ntfy *ntfy;
};
enum BTC_STATE_ST {
BTC_ST_IDLE,
BTC_ST_SERVICE
};
enum BTC_EV_ID {
BTC_EV_START,
BTC_EV_UPDATE_ROLE_INFO,
BTC_EV_FWINFO,
BTC_EV_WLSTA,
BTC_EV_TIMER,
BTC_EV_PACKET_EVT,
BTC_EV_MAX
};
static int btc_idle_st_hdl(void *obj, u16 event, void *param);
static int btc_service_st_hdl(void *obj, u16 event, void *param);
/* STATE table */
static struct fsm_state_ent btc_state_tbl[] = {
ST_ENT(BTC_ST_IDLE, btc_idle_st_hdl),
ST_ENT(BTC_ST_SERVICE, btc_service_st_hdl)
//{BTC_ST_MAX, "BTC_ST_MAX", NULL} /* ST_MAX for fsm safety checking */
};
/* EVENT table */
static struct fsm_event_ent btc_event_tbl[] = {
EV_ENT(BTC_EV_START),
EV_ENT(BTC_EV_UPDATE_ROLE_INFO),
EV_ENT(BTC_EV_FWINFO),
EV_ENT(BTC_EV_WLSTA),
EV_DBG(BTC_EV_TIMER),
EV_ENT(BTC_EV_PACKET_EVT),
EV_ENT(BTC_EV_MAX) /* EV_MAX for fsm safety checking */
};
/*
* btc idle handler
*/
static int btc_idle_st_hdl(void *obj, u16 event, void *param)
{
struct btc_obj *pbtc = (struct btc_obj *)obj;
FSM_DBG(pbtc->fsm, "[BTC], %s, event : 0x%x\n", __func__, event);
switch (event) {
case FSM_EV_STATE_IN:
break;
case FSM_EV_TIMER_EXPIRE:
break;
case BTC_EV_START:
phl_fsm_state_goto(pbtc->fsm_obj, BTC_ST_SERVICE);
break;
case FSM_EV_STATE_OUT:
break;
default:
break;
}
return 0;
}
static int btc_service_st_hdl(void *obj, u16 event, void *param)
{
struct btc_obj *pbtc = (struct btc_obj *)obj;
struct phl_info_t *phl_info = pbtc->phl_info;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
int rtn = FSM_FREE_PARAM;
FSM_DBG(pbtc->fsm, "[BTC], %s, event : 0x%x\n", __func__, event);
switch (event) {
case FSM_EV_STATE_IN:
break;
case BTC_EV_UPDATE_ROLE_INFO:
if (param) {
struct rtw_phl_btc_role_info_param *prinfo = NULL;
struct rtw_wifi_role_t *wrole = NULL;
struct rtw_phl_stainfo_t *sta = NULL;
pbtc->ntfy = param;
prinfo = &pbtc->ntfy->u.rinfo;
if (prinfo->role_id < MAX_WIFI_ROLE_NUMBER) {
wrole = &phl_com->wifi_roles[prinfo->role_id];
sta = rtw_phl_get_stainfo_self(phl_info, wrole);
}
#ifdef CONFIG_BTCOEX
rtw_hal_btc_update_role_info_ntfy(phl_info->hal,
prinfo->role_id, wrole, sta, prinfo->rstate);
#endif
if (pbtc->ntfy->ntfy_cb)
pbtc->ntfy->ntfy_cb(pbtc->ntfy->priv,
pbtc->ntfy->notify,
pbtc->ntfy);
rtn = FSM_FREE_PARAM;
}
break;
case BTC_EV_FWINFO:
#ifdef CONFIG_BTCOEX
rtw_hal_btc_fwinfo_ntfy(phl_info->hal);
#endif
break;
case BTC_EV_TIMER:
{
#ifdef CONFIG_BTCOEX
struct rtw_phl_btc_tmr_param *tmr = NULL;
pbtc->ntfy = param;
tmr = &pbtc->ntfy->u.tmr;
rtw_hal_btc_timer(phl_info->hal, tmr->timer);
#endif
}
break;
case BTC_EV_PACKET_EVT:
if (param) {
struct rtw_phl_btc_pkt_param *pkt = NULL;
struct rtw_wifi_role_t *wrole = NULL;
pbtc->ntfy = param;
pkt = &pbtc->ntfy->u.pkt;
if (pkt->role_id < MAX_WIFI_ROLE_NUMBER) {
wrole = &phl_com->wifi_roles[pkt->role_id];
}
#ifdef CONFIG_BTCOEX
rtw_hal_btc_packet_event_ntfy(phl_info->hal,
pkt->pkt_evt_type);
#endif
if (pbtc->ntfy->ntfy_cb)
pbtc->ntfy->ntfy_cb(pbtc->ntfy->priv,
pbtc->ntfy->notify,
pbtc->ntfy);
rtn = FSM_FREE_PARAM;
}
break;
case FSM_EV_TIMER_EXPIRE:
break;
case FSM_EV_CANCEL:
phl_fsm_state_goto(pbtc->fsm_obj, BTC_ST_IDLE);
break;
case FSM_EV_STATE_OUT:
phl_fsm_cancel_alarm(pbtc->fsm_obj);
break;
default:
break;
}
return rtn;
}
static void btc_dump_obj(void *obj, char *s, int *sz)
{
/* nothing to do for now */
}
static void btc_dump_fsm(void *fsm, char *s, int *sz)
{
/* nothing to do for now */
}
/* For EXTERNAL application to create a btc FSM */
/* @root: FSM root structure
* @phl_info: private data structure to invoke hal/phl function
*
* return
* fsm_main: FSM main structure (Do NOT expose)
*/
struct fsm_main *phl_btc_new_fsm(struct fsm_root *root,
struct phl_info_t *phl_info)
{
void *d = phl_to_drvpriv(phl_info);
struct fsm_main *fsm = NULL;
struct rtw_phl_fsm_tb tb;
_os_mem_set(d, &tb, 0, sizeof(tb));
tb.max_state = sizeof(btc_state_tbl)/sizeof(btc_state_tbl[0]);
tb.max_event = sizeof(btc_event_tbl)/sizeof(btc_event_tbl[0]);
tb.state_tbl = btc_state_tbl;
tb.evt_tbl = btc_event_tbl;
tb.dump_obj = btc_dump_obj;
tb.dump_obj = btc_dump_fsm;
tb.dbg_level = FSM_DBG_INFO;
tb.evt_level = FSM_DBG_INFO;
fsm = phl_fsm_init_fsm(root, "btc", phl_info, &tb);
return fsm;
}
/* For EXTERNAL application to destory btc fsm */
/* @fsm: see fsm_main
*/
void phl_btc_destory_fsm(struct fsm_main *fsm)
{
if (fsm == NULL)
return;
/* deinit fsm local variable if has */
/* call FSM Framewro to deinit fsm */
phl_fsm_deinit_fsm(fsm);
}
/* For EXTERNAL application to create btcoex object */
/* @fsm: FSM main structure which created by phl_btc_new_fsm()
* @phl_info: private data structure to invoke hal/phl function
*
* return
* btc_obj: structure of command object (Do NOT expose)
*/
struct btc_obj *phl_btc_new_obj(struct fsm_main *fsm,
struct phl_info_t *phl_info)
{
struct fsm_obj *obj;
struct btc_obj *pbtc;
pbtc = phl_fsm_new_obj(fsm, (void **)&obj, sizeof(*pbtc));
if (pbtc == NULL || obj == NULL) {
/* TODO free fsm; currently will be freed in deinit process */
FSM_ERR(fsm, "btc: malloc obj fail\n");
return NULL;
}
pbtc->fsm = fsm;
pbtc->fsm_obj = obj;
pbtc->phl_info = phl_info;
return pbtc;
}
/* For EXTERNAL application to destory btc object */
/* @pbtc: local created command object
*
*/
void phl_btc_destory_obj(struct btc_obj *pbtc)
{
if (pbtc == NULL)
return;
/* inform FSM framewory to recycle fsm_obj */
phl_fsm_destory_obj(pbtc->fsm_obj);
}
/* For EXTERNAL application to start btcoex service (expose) */
/* @pbtc: btc object
*/
enum rtw_phl_status phl_btc_start(struct btc_obj *pbtc)
{
void *d = phl_to_drvpriv(pbtc->phl_info);
enum rtw_phl_status phl_status = RTW_PHL_STATUS_SUCCESS;
struct fsm_msg *msg;
/* Start FSM */
phl_status = phl_fsm_start_fsm(pbtc->fsm);
if (phl_status != RTW_PHL_STATUS_SUCCESS)
return phl_status;
if (pbtc->fsm_obj == NULL)
return RTW_PHL_STATUS_FAILURE;
/* NEW message to start btc object */
msg = phl_fsm_new_msg(pbtc->fsm_obj, BTC_EV_START);
if (msg == NULL) {
FSM_ERR(pbtc->fsm, "btc: alloc msg fail\n");
return RTW_PHL_STATUS_RESOURCE;
}
if (phl_fsm_sent_msg(pbtc->fsm_obj, msg) != RTW_PHL_STATUS_SUCCESS) {
_os_kmem_free(d, msg, sizeof(*msg));
return RTW_PHL_STATUS_FAILURE;
}
return phl_status;
}
/* For EXTERNAL application to stop btc service (expose) */
/* @pbtc: btc to be cancelled
*/
enum rtw_phl_status phl_btc_cancel(struct btc_obj *pbtc)
{
return phl_fsm_cancel_obj(pbtc->fsm_obj);
}
/* For EXTERNAL application to notify btc (expose) */
/* @phl: refer to phl_infi_t
* @notify: notification event
* @ntfy: notify information (optional)
* return value:
* 0: no wait
* 1: have to wait call back info->ntfy_cb()
* -1: Failure
*/
int rtw_phl_btc_notify(void *phl, enum RTW_PHL_BTC_NOTIFY notify,
struct rtw_phl_btc_ntfy *ntfy)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct btc_obj *pbtc = phl_info->btc_obj;
int wait = 0, sz = 0;
u16 event;
if (ntfy)
sz = sizeof(*ntfy);
switch (notify) {
case PHL_BTC_NTFY_ROLE_INFO:
event = BTC_EV_UPDATE_ROLE_INFO;
break;
case PHL_BTC_NTFY_FWINFO:
event = BTC_EV_FWINFO;
break;
case PHL_BTC_NTFY_PACKET_EVT:
event = BTC_EV_PACKET_EVT;
break;
case PHL_BTC_NTFY_MAX:
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "rtw_phl_btc_notify(): Unsupported case:%d, please check it\n",
notify);
return wait;
case PHL_BTC_NTFY_TIMER:
event = BTC_EV_TIMER;
break;
default:
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "rtw_phl_btc_notify(): Unrecognize case:%d, please check it\n",
notify);
return wait;
}
phl_fsm_gen_msg(phl, pbtc->fsm_obj, ntfy, sz, event);
return wait;
}
void rtw_phl_btc_role_notify(void *phl, u8 role_id, enum role_state rstate)
{
struct rtw_phl_btc_ntfy ntfy = {0};
struct rtw_phl_btc_role_info_param *prinfo = &ntfy.u.rinfo;
prinfo->role_id = role_id;
prinfo->rstate = rstate;
ntfy.notify = PHL_BTC_NTFY_ROLE_INFO;
ntfy.ops = NULL;
ntfy.priv = NULL;
ntfy.ntfy_cb = NULL;
rtw_phl_btc_notify(phl, ntfy.notify, &ntfy);
}
#ifndef CONFIG_PHL_CMD_BTC
void rtw_phl_btc_packet_event_notify(void *phl, u8 role_id, u8 pkt_evt_type)
{
struct rtw_phl_btc_ntfy ntfy = {0};
struct rtw_phl_btc_pkt_param *pkt = &ntfy.u.pkt;
pkt->role_id = role_id;
pkt->pkt_evt_type = pkt_evt_type;
ntfy.notify = PHL_BTC_NTFY_PACKET_EVT;
ntfy.ops = NULL;
ntfy.priv = NULL;
ntfy.ntfy_cb = NULL;
rtw_phl_btc_notify(phl, ntfy.notify, &ntfy);
}
u8 rtw_phl_btc_pkt_2_evt_type(u8 packet_type)
{
u8 pkt_evt_type = BTC_PKT_EVT_MAX;
switch (packet_type) {
case PACKET_NORMAL:
pkt_evt_type = BTC_PKT_EVT_NORMAL;
break;
case PACKET_DHCP:
pkt_evt_type = BTC_PKT_EVT_DHCP;
break;
case PACKET_ARP:
pkt_evt_type = BTC_PKT_EVT_ARP;
break;
case PACKET_EAPOL:
pkt_evt_type = BTC_PKT_EVT_EAPOL;
break;
case PACKET_EAPOL_START:
pkt_evt_type = BTC_PKT_EVT_EAPOL_START;
break;
default:
PHL_ERR("%s packet type(%d) not support\n",
__func__, packet_type);
break;
}
return pkt_evt_type;
}
#endif
static void _btc_fsm_tmr(void *phl, void *timer)
{
struct rtw_phl_btc_ntfy ntfy = {0};
struct rtw_phl_btc_tmr_param *tmr = &ntfy.u.tmr;
tmr->timer = timer;
ntfy.notify = PHL_BTC_NTFY_TIMER;
ntfy.ops = NULL;
ntfy.priv = NULL;
ntfy.ntfy_cb = NULL;
rtw_phl_btc_notify(phl, ntfy.notify, &ntfy);
}
void rtw_phl_btc_hub_msg_hdl(void *phl, struct phl_msg *msg)
{
u8 mdl_id = MSG_MDL_ID_FIELD(msg->msg_id);
u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
switch (mdl_id) {
case PHL_MDL_BTC:
if (evt_id == BTC_HMSG_TMR_EN) {
_btc_fsm_tmr(phl, msg->inbuf);
} else if (evt_id == BTC_HMSG_FW_EV) {
rtw_phl_btc_notify(phl, PHL_BTC_NTFY_FWINFO, NULL);
}
break;
default:
break;
}
}
#endif /*CONFIG_FSM*/
|
2301_81045437/rtl8852be
|
phl/phl_btc_fsm.c
|
C
|
agpl-3.0
| 10,742
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHL_BTC_FSM_H__
#define __PHL_BTC_FSM_H__
/* Header file for application to invoke btcoex service */
#define RTW_BTC_FWBUF_NUM 4
#define RTW_BTC_NAME_MAX 20
struct fsm_root;
struct fsm_main;
struct btc_obj;
/* function form btcoex service management */
struct fsm_main *phl_btc_new_fsm(struct fsm_root *fsm_m,
struct phl_info_t *phl_info);
void phl_btc_destory_fsm(struct fsm_main *fsm);
struct btc_obj *phl_btc_new_obj(struct fsm_main *fsm,
struct phl_info_t *phl_info);
void phl_btc_destory_obj(struct btc_obj *pbtc);
/* function form btcoex service */
enum rtw_phl_status phl_btc_start(struct btc_obj *pbtc);
enum rtw_phl_status phl_btc_cancel(struct btc_obj *pbtc);
#endif /* __PHL_BTC_FSM_H__ */
|
2301_81045437/rtl8852be
|
phl/phl_btc_fsm.h
|
C
|
agpl-3.0
| 1,376
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CHAN_C_
#include "phl_headers.h"
const char *const _band_str[] = {
"BAND_ON_24G",
"BAND_ON_5G",
"BAND_ON_6G",
"BAND_UNKNOWN"
};
#define _get_band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)])
const char *const _bw_str[] = {
"BW_20M",
"BW_40M",
"BW_80M",
"BW_160M",
"BW_80_80M",
"BW_5M",
"BW_10M",
"BW_UNKNOWN"
};
#define _get_bw_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _bw_str[CHANNEL_WIDTH_MAX] : _bw_str[((bw))])
#ifdef DBG_PHL_CHAN
void phl_chan_dump_chandef(const char *caller, const int line, bool show_caller,
struct rtw_chan_def *chandef)
{
if (show_caller)
PHL_INFO("###### FUN - %s LINE - %d #######\n", caller, line);
PHL_INFO("\t[CH] band:%s\n", _get_band_str(chandef->band));
PHL_INFO("\t[CH] chan:%d\n", chandef->chan);
PHL_INFO("\t[CH] center_ch:%d\n", chandef->center_ch);
PHL_INFO("\t[CH] bw:%s\n", _get_bw_str(chandef->bw));
PHL_INFO("\t[CH] offset:%d\n", chandef->offset);
PHL_INFO("\t[CH] center_freq1:%d\n", chandef->center_freq1);
PHL_INFO("\t[CH] center_freq2:%d\n", chandef->center_freq2);
PHL_INFO("\t[CH] hw_value:%d\n", chandef->hw_value);
if (show_caller)
PHL_INFO("#################################\n");
}
#endif
#ifdef CONFIG_PHL_DFS
static enum rtw_phl_status
phl_radar_detect_hdl(struct phl_info_t *phl_info,
u8 channel, enum channel_width bwmode, enum chan_offset offset)
{
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
struct rtw_dfs_t *dfs_info = &phl_com->dfs_info;
enum rtw_phl_status rst = RTW_PHL_STATUS_FAILURE;
bool overlap_radar_range;
overlap_radar_range = rtw_hal_in_radar_domain(phl_info->hal,
channel, bwmode);
if (overlap_radar_range)
PHL_INFO("chan in DFS domain ch:%d,bw:%d\n", channel, bwmode);
if (overlap_radar_range && !dfs_info->dfs_enabled) {
/*radar_detect_enable*/
if (rtw_hal_radar_detect_cfg(phl_info->hal, true) ==
RTW_HAL_STATUS_SUCCESS) {
dfs_info->dfs_enabled = true;
PHL_INFO("[DFS] chan(%d) in radar range, enable dfs\n",
channel);
rst = RTW_PHL_STATUS_SUCCESS;
}
else {
PHL_ERR("[DFS] chan(%d) in radar range, enable dfs failed\n",
channel);
}
} else if (!overlap_radar_range && dfs_info->dfs_enabled) {
/*radar_detect_disable*/
if (rtw_hal_radar_detect_cfg(phl_info->hal, false) ==
RTW_HAL_STATUS_SUCCESS) {
dfs_info->dfs_enabled = false;
PHL_INFO("[DFS] chan(%d) not in radar range, disable dfs\n",
channel);
rst = RTW_PHL_STATUS_SUCCESS;
}
else {
PHL_ERR("[DFS] chan(%d) not in radar range, disable dfs failed\n",
channel);
}
}
return rst;
}
#endif /*CONFIG_PHL_DFS*/
enum rtw_phl_status
phl_set_ch_bw(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chdef, bool do_rfk)
{
struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
chdef->band = rtw_phl_get_band_type(chdef->chan);
#ifdef CONFIG_PHL_DFS
phl_radar_detect_hdl(phl_info, chdef->chan, chdef->bw, chdef->offset);
#endif
hstatus = rtw_hal_set_ch_bw(phl_info->hal, wifi_role->hw_band,
chdef, do_rfk);
if (RTW_HAL_STATUS_SUCCESS != hstatus)
PHL_ERR("%s rtw_hal_set_ch_bw: statuts = %u\n", __func__, hstatus);
return RTW_PHL_STATUS_SUCCESS;
}
#ifdef CONFIG_CMD_DISP
struct setch_param {
struct rtw_wifi_role_t *wrole;
struct rtw_chan_def chdef;
bool do_rfk;
};
static void
_phl_chg_op_chdef_done(void *drv_priv, u8 *cmd, u32 cmd_len,
enum rtw_phl_status status)
{
if (cmd) {
struct chg_opch_param *param = (struct chg_opch_param *)cmd;
if (param->chg_opch_done) {
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
if (RTW_PHL_STATUS_CMD_SUCCESS == status &&
RTW_PHL_STATUS_CMD_SUCCESS == param->cmd_start_sts)
psts = RTW_PHL_STATUS_SUCCESS;
param->chg_opch_done(drv_priv, param->wrole->id,
psts);
}
_os_kmem_free(drv_priv, cmd, cmd_len);
cmd = NULL;
PHL_INFO("%s.....\n", __func__);
}
}
static void _phl_chg_op_chdef_start_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status)
{
if (cmd) {
struct chg_opch_param *param = (struct chg_opch_param *)cmd;
param->cmd_start_sts = status;
PHL_INFO("%s.....\n", __func__);
}
}
enum rtw_phl_status
phl_cmd_chg_op_chdef_start_hdl(struct phl_info_t *phl, u8 *param)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
struct chg_opch_param *ch_param = (struct chg_opch_param *)param;
void *drv = phl_to_drvpriv(phl);
enum phl_upd_mode mode = PHL_UPD_STA_INFO_CHANGE;
struct phl_queue *sta_queue = NULL;
struct rtw_phl_stainfo_t *sta = NULL;
struct rtw_chan_def chctx_result = {0};
sta = rtw_phl_get_stainfo_self(phl, ch_param->wrole);
if (NULL == sta) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: cannot get stainfo_self\n",
__FUNCTION__);
goto exit;
}
/* Update MR chctx */
if (RTW_PHL_STATUS_SUCCESS != phl_mr_chandef_chg(phl, ch_param->wrole,
&ch_param->new_chdef, &chctx_result)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: MR chang chdef failed!\n",
__FUNCTION__);
goto exit;
}
/* Up Role chdef */
_os_mem_cpy(drv, &ch_param->wrole->chandef, &ch_param->new_chdef,
sizeof(struct rtw_chan_def));
/* Update self Sta chdef */
_os_mem_cpy(drv, &sta->chandef, &ch_param->new_chdef,
sizeof(struct rtw_chan_def));
/* Notify rf for the suspended channel */
rtw_hal_disconnect_notify(phl->hal, &ch_param->ori_chdef);
/* Switch channel */
if (RTW_PHL_STATUS_SUCCESS != phl_set_ch_bw(ch_param->wrole,
&chctx_result, true)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Switch ch failed!\n",
__FUNCTION__);
goto exit;
}
if (ch_param->wrole->mstate == MLME_LINKED) {
/*Up STA setting(RA....) */
sta_queue = &ch_param->wrole->assoc_sta_queue;
_os_spinlock(drv, &sta_queue->lock, _bh, NULL);
phl_list_for_loop(sta, struct rtw_phl_stainfo_t,
&sta_queue->queue, list) {
if (sta)
phl_change_stainfo(phl, sta, mode);
}
_os_spinunlock(drv, &sta_queue->lock, _bh, NULL);
}
pstatus = RTW_PHL_STATUS_SUCCESS;
exit:
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: pstatus(%d)\n",
__FUNCTION__, pstatus);
return pstatus;
}
enum rtw_phl_status
rtw_phl_cmd_chg_op_chdef(struct rtw_wifi_role_t *wrole,
struct rtw_chan_def *new_chdef, bool cmd_wait, u32 cmd_timeout,
void (*chg_opch_done)(void *priv, u8 ridx, enum rtw_phl_status status))
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl = wrole->phl_com->phl_priv;
void *drv = phl_to_drvpriv(phl);
u32 param_len = sizeof(struct chg_opch_param);
struct chg_opch_param *param = _os_kmem_alloc(drv, param_len);
if (param == NULL) {
PHL_ERR("%s: alloc param failed!\n", __func__);
goto _exit;
}
param->wrole = wrole;
_os_mem_cpy(drv, ¶m->new_chdef, new_chdef,
sizeof(struct rtw_chan_def));
_os_mem_cpy(drv, ¶m->ori_chdef, &wrole->chandef,
sizeof(struct rtw_chan_def));
param->chg_opch_done = chg_opch_done;
psts = phl_cmd_enqueue(phl,
wrole->hw_band,
MSG_EVT_CHG_OP_CH_DEF_START,
(u8 *)param,
param_len,
_phl_chg_op_chdef_start_done,
PHL_CMD_NO_WAIT,
0);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_INFO("%s: Fail to issue change op chdef start!!\n",
__func__);
if (!is_cmd_failure(psts)) {
/* Send cmd fail */
_os_kmem_free(drv, param, param_len);
psts = RTW_PHL_STATUS_FAILURE;
}
goto _exit;
}
psts = phl_cmd_enqueue(phl,
wrole->hw_band,
MSG_EVT_CHG_OP_CH_DEF_END,
(u8 *)param,
param_len,
_phl_chg_op_chdef_done,
cmd_wait ? PHL_CMD_WAIT : PHL_CMD_NO_WAIT,
cmd_timeout);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_INFO("%s: Fail to issue change op chdef start!!\n",
__func__);
if (!is_cmd_failure(psts)) {
/* Send cmd fail */
_os_kmem_free(drv, param, param_len);
psts = RTW_PHL_STATUS_FAILURE;
}
goto _exit;
}
_exit:
PHL_INFO("%s: Issue cmd, status(%d)\n", __func__, psts);
return psts;
}
enum rtw_phl_status
phl_cmd_set_ch_bw_hdl(struct phl_info_t *phl_info, u8 *param)
{
struct setch_param *ch_param = (struct setch_param *)param;
return phl_set_ch_bw(ch_param->wrole,
&(ch_param->chdef),
ch_param->do_rfk);
}
static void _phl_set_ch_bw_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status)
{
if (cmd) {
_os_kmem_free(drv_priv, cmd, cmd_len);
cmd = NULL;
PHL_INFO("%s.....\n", __func__);
}
}
enum rtw_phl_status
rtw_phl_cmd_set_ch_bw(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chdef,
bool do_rfk,
enum phl_cmd_type cmd_type,
u32 cmd_timeout)
{
struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv;
void *drv = wifi_role->phl_com->drv_priv;
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct setch_param *param = NULL;
u32 param_len;
if (cmd_type == PHL_CMD_DIRECTLY) {
psts = phl_set_ch_bw(wifi_role, chdef, do_rfk);
goto _exit;
}
param_len = sizeof(struct setch_param);
param = _os_kmem_alloc(drv, param_len);
if (param == NULL) {
PHL_ERR("%s: alloc param failed!\n", __func__);
goto _exit;
}
param->wrole = wifi_role;
_os_mem_cpy(drv, ¶m->chdef, chdef, sizeof(struct rtw_chan_def));
param->do_rfk = do_rfk;
psts = phl_cmd_enqueue(phl_info,
wifi_role->hw_band,
MSG_EVT_SWCH_START,
(u8 *)param,
param_len,
_phl_set_ch_bw_done,
cmd_type,
cmd_timeout);
if (is_cmd_failure(psts)) {
/* Send cmd success, but wait cmd fail*/
psts = RTW_PHL_STATUS_FAILURE;
} else if (psts != RTW_PHL_STATUS_SUCCESS) {
/* Send cmd fail */
_os_kmem_free(drv, param, param_len);
psts = RTW_PHL_STATUS_FAILURE;
}
_exit:
return psts;
}
#endif /*CONFIG_CMD_DISP*/
u8 rtw_phl_get_cur_ch(struct rtw_wifi_role_t *wifi_role)
{
struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv;
return rtw_hal_get_cur_ch(phl_info->hal, wifi_role->hw_band);
}
enum rtw_phl_status
rtw_phl_get_cur_hal_chdef(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *cur_chandef)
{
struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv;
rtw_hal_get_cur_chdef(phl_info->hal, wifi_role->hw_band, cur_chandef);
return RTW_PHL_STATUS_SUCCESS;
}
static enum rtw_phl_status
_dfs_hw_tx_pause(struct rtw_wifi_role_t *wifi_role, bool tx_pause)
{
struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
hstatus = rtw_hal_dfs_pause_tx(phl_info->hal, wifi_role->hw_band, tx_pause);
if (RTW_HAL_STATUS_SUCCESS == hstatus) {
return RTW_PHL_STATUS_SUCCESS;
} else {
PHL_ERR("%s Failure :%u\n",__func__, hstatus);
return RTW_PHL_STATUS_FAILURE;
}
}
#ifdef CONFIG_CMD_DISP
struct dfs_txpause_param {
struct rtw_wifi_role_t *wrole;
bool pause;
};
enum rtw_phl_status
phl_cmd_dfs_tx_pause_hdl(struct phl_info_t *phl_info, u8 *param)
{
struct dfs_txpause_param *dfs = (struct dfs_txpause_param *)param;
PHL_INFO("%s(), dfs param, wrole = %p, pause = %d\n",
__func__, dfs->wrole, dfs->pause);
return _dfs_hw_tx_pause(dfs->wrole, dfs->pause);
}
static void _phl_dfs_tx_pause_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status)
{
if (cmd) {
_os_kmem_free(drv_priv, cmd, cmd_len);
cmd = NULL;
PHL_INFO("%s.....\n", __func__);
}
}
#endif /*CONFIG_CMD_DISP*/
enum rtw_phl_status
rtw_phl_cmd_dfs_tx_pause(struct rtw_wifi_role_t *wifi_role, bool pause,
enum phl_cmd_type cmd_type, u32 cmd_timeout)
{
#ifdef CONFIG_CMD_DISP
struct phl_info_t *phl_info = wifi_role->phl_com->phl_priv;
void *drv = wifi_role->phl_com->drv_priv;
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct dfs_txpause_param *param = NULL;
u32 param_len;
param_len = sizeof(struct dfs_txpause_param);
param = _os_kmem_alloc(drv, param_len);
if (param == NULL) {
PHL_ERR("%s: alloc param failed!\n", __func__);
goto _exit;
}
param->wrole = wifi_role;
param->pause = pause;
psts = phl_cmd_enqueue(phl_info,
wifi_role->hw_band,
MSG_EVT_DFS_PAUSE_TX,
(u8 *)param, param_len,
_phl_dfs_tx_pause_done,
cmd_type, cmd_timeout);
if (is_cmd_failure(psts)) {
/* Send cmd success, but wait cmd fail*/
psts = RTW_PHL_STATUS_FAILURE;
} else if (psts != RTW_PHL_STATUS_SUCCESS) {
/* Send cmd fail */
_os_kmem_free(drv, param, param_len);
psts = RTW_PHL_STATUS_FAILURE;
}
_exit:
return psts;
#else
PHL_ERR("%s(), CONFIG_CMD_DISP need to be enabled for MSG_EVT_DFS_PAUSE_TX \n",__func__);
return RTW_PHL_STATUS_FAILURE;
#endif
}
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_phl_status
rtw_phl_dbcc_test(void *phl, enum dbcc_test_id id, void *param)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
switch (id){
case DBCC_PRE_CFG :
{
bool dbcc_en = *(bool *)param;
PHL_INFO("[DBCC] PRE_CFG :%s\n", (dbcc_en) ? "EN" : "DIS");
hsts = rtw_hal_dbcc_pre_cfg(phl_info->hal, phl_info->phl_com, dbcc_en);
}
break;
case DBCC_CFG :
{
bool dbcc_en = *(bool *)param;
PHL_INFO("[DBCC] CFG :%s\n", (dbcc_en) ? "EN" : "DIS");
hsts = rtw_hal_dbcc_cfg(phl_info->hal, phl_info->phl_com, dbcc_en);
}
break;
case DBCC_CLEAN_TXQ :
hsts = rtw_hal_clean_tx_queue(phl_info->hal);
break;
default :
PHL_ERR("%s unknown DBCC Test ID:%d\n",__func__, id);
break;
}
return RTW_PHL_STATUS_SUCCESS;
}
#endif
#define MAX_CHANCTX_QUEUE_NUM 2
static enum rtw_phl_status
_phl_chanctx_add(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
list_add_tail(&chanctx->list, &chan_ctx_queue->queue);
chan_ctx_queue->cnt++;
if (chan_ctx_queue->cnt > MAX_CHANCTX_QUEUE_NUM) {
PHL_ERR("%s chan_ctx_queue cnt(%d) > 2\n", __func__, chan_ctx_queue->cnt);
_os_warn_on(1);
}
return RTW_PHL_STATUS_SUCCESS;
}
static enum rtw_phl_status
_phl_chanctx_add_with_lock(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
void *drv = phl_to_drvpriv(phl_info);
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
_phl_chanctx_add(phl_info, chan_ctx_queue, chanctx);
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
return RTW_PHL_STATUS_SUCCESS;
}
static enum rtw_phl_status
_phl_chanctx_del(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
/*if (!list_empty(&chan_ctx_queue->queue)) {*/
if (chan_ctx_queue->cnt) {
list_del(&chanctx->list);
chan_ctx_queue->cnt--;
if (chan_ctx_queue->cnt < 0) {
PHL_ERR("%s chan_ctx_queue cnt(%d) < 0\n", __func__, chan_ctx_queue->cnt);
_os_warn_on(1);
}
}
return RTW_PHL_STATUS_SUCCESS;
}
static enum rtw_phl_status
_phl_chanctx_del_with_lock(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
void *drv = phl_to_drvpriv(phl_info);
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
_phl_chanctx_del(phl_info, chan_ctx_queue, chanctx);
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
return RTW_PHL_STATUS_SUCCESS;
}
static inline enum rtw_phl_status
_phl_chanctx_rmap_set(struct phl_info_t *phl_info,
struct rtw_wifi_role_t *wifi_role,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
u8 ridx = wifi_role->id;
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
#ifdef DBG_CHCTX_RMAP
if (chanctx->role_map & BIT(ridx))
PHL_ERR("wifi_role idx(%d) has in chanctx->role_map(0x%02x)\n",
ridx, chanctx->role_map);
#endif
chanctx->role_map |= BIT(ridx);
wifi_role->chanctx = chanctx;
return RTW_PHL_STATUS_SUCCESS;
}
static enum rtw_phl_status
_phl_chanctx_rmap_set_with_lock(struct phl_info_t *phl_info,
struct rtw_wifi_role_t *wifi_role,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
void *drv = phl_to_drvpriv(phl_info);
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
_phl_chanctx_rmap_set(phl_info, wifi_role, chan_ctx_queue, chanctx);
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
return RTW_PHL_STATUS_SUCCESS;
}
static inline enum rtw_phl_status
_phl_chanctx_rmap_clr(struct phl_info_t *phl_info,
struct rtw_wifi_role_t *wifi_role,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
u8 ridx = wifi_role->id;
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
#ifdef DBG_CHCTX_RMAP
if (!(chanctx->role_map & BIT(ridx)))
PHL_ERR("ridx(%d) hasn't in chanctx->role_map(0x%02x)\n", ridx, chanctx->role_map);
#endif
wifi_role->chanctx = NULL;
chanctx->role_map &= ~BIT(ridx);
return RTW_PHL_STATUS_SUCCESS;
}
static enum rtw_phl_status
_phl_chanctx_rmap_clr_with_lock(struct phl_info_t *phl_info,
struct rtw_wifi_role_t *wifi_role,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
void *drv = phl_to_drvpriv(phl_info);
if (!chanctx)
return RTW_PHL_STATUS_FAILURE;
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
_phl_chanctx_rmap_clr(phl_info, wifi_role, chan_ctx_queue, chanctx);
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
return RTW_PHL_STATUS_SUCCESS;
}
u8 phl_chanctx_get_rnum(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
u8 i;
u8 role_num = 0;
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++)
if (chanctx->role_map & BIT(i))
role_num++;
return role_num;
}
u8 phl_chanctx_get_rnum_with_lock(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx)
{
void *drv = phl_to_drvpriv(phl_info);
u8 role_num = 0;
if (!chanctx)
return role_num;
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
role_num = phl_chanctx_get_rnum(phl_info, chan_ctx_queue, chanctx);
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
return role_num;
}
/**
* _phl_is_chbw_grouped - test if the two ch settings can be grouped together
* @ch_a: ch of set a
* @bw_a: bw of set a
* @offset_a: offset of set a
* @ch_b: ch of set b
* @bw_b: bw of set b
* @offset_b: offset of set b
*/
static bool _phl_is_chbw_grouped(u8 ch_a, enum channel_width bw_a, enum chan_offset offset_a
, u8 ch_b, enum channel_width bw_b, enum chan_offset offset_b)
{
bool is_grouped = false;
if (ch_a != ch_b) {
/* ch is different */
goto exit;
} else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80)
&& (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80)
) {
if (offset_a != offset_b)
goto exit;
}
is_grouped = true;
exit:
return is_grouped;
}
static inline bool
_phl_feature_check(struct rtw_phl_com_t *phl_com, u8 flg)
{
return (phl_com->dev_cap.hw_sup_flags & flg) ? true : false;
}
static u8 _phl_get_offset_by_chbw(u8 ch, enum channel_width bw, enum chan_offset *r_offset)
{
u8 valid = 1;
enum chan_offset offset = CHAN_OFFSET_NO_EXT;
if (bw == CHANNEL_WIDTH_20)
goto exit;
if (bw >= CHANNEL_WIDTH_80 && ch <= 14) {
valid = 0;
goto exit;
}
if (ch >= 1 && ch <= 4)
offset = CHAN_OFFSET_UPPER;
else if (ch >= 5 && ch <= 9) {
if (*r_offset == CHAN_OFFSET_UPPER || *r_offset == CHAN_OFFSET_LOWER)
offset = *r_offset; /* both lower and upper is valid, obey input value */
else
offset = CHAN_OFFSET_LOWER; /* default use upper */
} else if (ch >= 10 && ch <= 13)
offset = CHAN_OFFSET_LOWER;
else if (ch == 14) {
valid = 0; /* ch14 doesn't support 40MHz bandwidth */
goto exit;
} else if (ch >= 36 && ch <= 177) {
switch (ch) {
case 36:
case 44:
case 52:
case 60:
case 100:
case 108:
case 116:
case 124:
case 132:
case 140:
case 149:
case 157:
case 165:
case 173:
offset = CHAN_OFFSET_UPPER;
break;
case 40:
case 48:
case 56:
case 64:
case 104:
case 112:
case 120:
case 128:
case 136:
case 144:
case 153:
case 161:
case 169:
case 177:
offset = CHAN_OFFSET_LOWER;
break;
default:
valid = 0;
break;
}
} else
valid = 0;
exit:
if (valid && r_offset)
*r_offset = offset;
return valid;
}
/**
* _phl_adjust_chandef - obey g_ch, adjust g_bw, g_offset, bw, offset
* @req_ch: pointer of the request ch, may be modified further
* @req_bw: pointer of the request bw, may be modified further
* @req_offset: pointer of the request offset, may be modified further
* @g_ch: pointer of the ongoing group ch
* @g_bw: pointer of the ongoing group bw, may be modified further
* @g_offset: pointer of the ongoing group offset, may be modified further
*/
static void _phl_adjust_chandef(u8 *req_ch, enum channel_width *req_bw, enum chan_offset *req_offset,
u8 *g_ch, enum channel_width *g_bw, enum chan_offset *g_offset)
{
*req_ch = *g_ch;
if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) {
/*2.4G ch, downgrade to 40Mhz */
*req_bw = CHANNEL_WIDTH_40;
}
switch (*req_bw) {
case CHANNEL_WIDTH_80:
if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
*req_offset = *g_offset;
else if (*g_bw == CHANNEL_WIDTH_20)
_phl_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
if (*req_offset == CHAN_OFFSET_NO_EXT) {
PHL_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__);
_os_warn_on(1);
*req_bw = CHANNEL_WIDTH_20;
}
break;
case CHANNEL_WIDTH_40:
if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
*req_offset = *g_offset;
else if (*g_bw == CHANNEL_WIDTH_20)
_phl_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
if (*req_offset == CHAN_OFFSET_NO_EXT) {
PHL_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__);
_os_warn_on(1);
*req_bw = CHANNEL_WIDTH_20;
}
break;
case CHANNEL_WIDTH_20:
*req_offset = CHAN_OFFSET_NO_EXT;
break;
default:
PHL_ERR("%s req unsupported BW:%u\n", __func__, *req_bw);
_os_warn_on(1);
}
if (*req_bw > *g_bw) {
*g_bw = *req_bw;
*g_offset = *req_offset;
}
}
static enum rtw_phl_status
_phl_chanctx_create(struct phl_info_t *phl_info,
struct rtw_wifi_role_t *wifi_role,
enum band_type band, u8 chan,
enum channel_width bw, enum chan_offset offset)
{
enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE;
void *drv = phl_to_drvpriv(phl_info);
struct rtw_chan_ctx *chanctx = NULL;
struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_info->phl_com);
struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]);
chanctx = _os_kmem_alloc(drv, sizeof(struct rtw_chan_ctx));
if (chanctx == NULL) {
PHL_ERR("alloc chanctx failed\n");
goto _exit;
}
chanctx->chan_def.band = band;
chanctx->chan_def.chan = chan;
chanctx->chan_def.bw = bw;
chanctx->chan_def.offset = offset;
chanctx->chan_def.center_ch = rtw_phl_get_center_ch(chan, bw, offset);
phl_sts = _phl_chanctx_add_with_lock(phl_info, &band_ctrl->chan_ctx_queue, chanctx);
if (phl_sts == RTW_PHL_STATUS_SUCCESS)
_phl_chanctx_rmap_set_with_lock(phl_info, wifi_role,
&band_ctrl->chan_ctx_queue, chanctx);
_exit:
return phl_sts;
}
bool phl_chanctx_add(struct phl_info_t *phl_info, struct rtw_wifi_role_t *wifi_role,
u8 *chan, enum channel_width *bw, enum chan_offset *offset)
{
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE;
void *drv = phl_to_drvpriv(phl_info);
struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com);
struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]);
struct rtw_chan_ctx *chanctx = NULL;
struct rtw_chan_def *chandef = NULL;
_os_list *chan_ctx_list = &band_ctrl->chan_ctx_queue.queue;
bool is_ch_grouped = false;
enum band_type band = (*chan > 14) ? BAND_ON_5G : BAND_ON_24G;
int chanctx_num = 0;
if (wifi_role == NULL) {
PHL_ERR("%s wrole == NULL\n", __func__);
goto _exit;
}
PHL_INFO("%s new chan_def - hw_band_idx:%d, chan:%d, bw:%d, offset:%d\n",
__func__, wifi_role->hw_band, *chan, *bw, *offset);
chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl);
if (chanctx_num == 0) {
phl_sts = _phl_chanctx_create(phl_info, wifi_role,
band, *chan, *bw, *offset);
if (phl_sts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s failed\n", __func__);
_os_warn_on(1);
}
else {
is_ch_grouped = true;
}
}
else {
_os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
phl_list_for_loop(chanctx, struct rtw_chan_ctx, chan_ctx_list, list) {
chandef = &chanctx->chan_def;
is_ch_grouped = _phl_is_chbw_grouped(
chandef->chan, chandef->bw, chandef->offset,
*chan, *bw, *offset);
if (is_ch_grouped) {
_phl_adjust_chandef(chan, bw, offset,
&chandef->chan, &chandef->bw, &chandef->offset);
*chan = chandef->chan;
*bw = chandef->bw;
*offset = chandef->offset;
PHL_INFO("%s grouped chan_def - hw_band_idx:%d, chan:%d, bw:%d, offset:%d\n",
__func__, wifi_role->hw_band, *chan, *bw, *offset);
_phl_chanctx_rmap_set(phl_info, wifi_role,
&band_ctrl->chan_ctx_queue, chanctx);
break;
}
}
_os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
if (is_ch_grouped == false) { /*MCC or DBCC*/
PHL_INFO("%s chan:%d, bw:%d, offset:%d could not grouped\n",
__func__, *chan, *bw, *offset);
#ifdef CONFIG_MCC_SUPPORT
if (phl_com->dev_cap.mcc_sup == false) {
PHL_ERR("%s don't support MCC\n", __func__);
goto _exit;
}
if (chanctx_num >= 2) {
PHL_ERR("chan_ctx cnt(%d) >= 2\n", chanctx_num);
/*DBCC ?*/
goto _exit;
}
if (band == chandef->band) { /*MCC*/
phl_sts = _phl_chanctx_create(phl_info, wifi_role,
band, *chan, *bw, *offset);
if (phl_sts == RTW_PHL_STATUS_SUCCESS)
is_ch_grouped = true;
} else {
/*DBCC*/
#ifdef CONFIG_DBCC_SUPPORT
if (phl_com->dev_cap.dbcc_sup == true) {
PHL_INFO("%s support DBC\n", __func__);
goto _exit;
}
#endif
/*MCC*/
phl_sts = _phl_chanctx_create(phl_info, wifi_role,
band, *chan, *bw, *offset);
if (phl_sts == RTW_PHL_STATUS_SUCCESS)
is_ch_grouped = true;
}
#endif
}
}
_exit:
return is_ch_grouped;
}
enum rtw_phl_status
phl_chanctx_free(struct phl_info_t *phl_info, struct hw_band_ctl_t *band_ctl)
{
int chanctx_num = 0;
struct rtw_chan_ctx *chanctx = NULL;
struct phl_queue *chan_ctx_queue = &band_ctl->chan_ctx_queue;
void *drv = phl_to_drvpriv(phl_info);
chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctl);
if (chanctx_num == 0)
return RTW_PHL_STATUS_SUCCESS;
PHL_INFO("%s band_idx:%d chctx_num:%d\n", __func__, band_ctl->id, chanctx_num);
do {
_os_spinlock(drv, &band_ctl->chan_ctx_queue.lock, _ps, NULL);
if (list_empty(&chan_ctx_queue->queue)) {
chanctx = NULL;
} else {
chanctx = list_first_entry(&chan_ctx_queue->queue,
struct rtw_chan_ctx, list);
list_del(&chanctx->list);
chan_ctx_queue->cnt--;
}
_os_spinunlock(drv, &band_ctl->chan_ctx_queue.lock, _ps, NULL);
if (chanctx) {
_os_kmem_free(drv, chanctx, sizeof(struct rtw_chan_ctx));
}
} while (chanctx != NULL);
return RTW_PHL_STATUS_SUCCESS;
}
/* used for get all role under band_idx */
u8 phl_get_chanctx_rolemap(struct phl_info_t *phl_info, u8 band_idx)
{
void *drv = phl_to_drvpriv(phl_info);
struct hw_band_ctl_t *band_ctrl = get_band_ctrl(phl_info, band_idx);
_os_list *chan_ctx_list = &band_ctrl->chan_ctx_queue.queue;
struct rtw_chan_ctx *chanctx = NULL;
u8 role_map =0;
_os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
phl_list_for_loop(chanctx, struct rtw_chan_ctx, chan_ctx_list, list) {
role_map |= chanctx->role_map;
}
_os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
return role_map;
}
bool rtw_phl_chanctx_chk(void *phl, struct rtw_wifi_role_t *wifi_role,
u8 chan, enum channel_width bw, enum chan_offset offset)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
void *drv = phl_to_drvpriv(phl_info);
struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com);
u8 band_idx = wifi_role->hw_band;
bool is_ch_group = false;
struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[band_idx]);
int chanctx_num = 0;
struct rtw_chan_ctx *chanctx = NULL;
struct rtw_chan_def *chandef = NULL;
if (chan == 0) {
PHL_ERR("%s req chan = 0 \n", __func__);
goto _exit;
}
/*status check*/
if (mr_ctl->is_sb) {
if (band_idx == 1) {
PHL_ERR("wrole:%d in band_idx:%d\n", wifi_role->id, band_idx);
_os_warn_on(1);
goto _exit;
}
}
chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl);
if (chanctx_num > 0) {
_os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
phl_list_for_loop(chanctx, struct rtw_chan_ctx, &band_ctrl->chan_ctx_queue.queue, list) {
chandef = &chanctx->chan_def;
is_ch_group = _phl_is_chbw_grouped(
chandef->chan, chandef->bw, chandef->offset,
chan, bw, offset);
if (is_ch_group)
break;
}
/* consider MCC case (support max 2 diff ch for MCC currently) */
#ifdef CONFIG_MCC_SUPPORT
if (phl_com->dev_cap.mcc_sup == true && is_ch_group == false && chanctx_num < 2) {
is_ch_group = true;
}
#endif
_os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
} else {
is_ch_group = true;
}
_exit:
PHL_DUMP_MR_EX(phl_info);
return is_ch_group;
}
/*
* Add new operating chdef to MR.
* @new_chan: Input: new chdef; Output: the final operating ch ctx.
* ex: In the scc case, it will be the group chdef.
*/
bool rtw_phl_chanctx_add(void *phl, struct rtw_wifi_role_t *wifi_role,
u8 *chan, enum channel_width *bw, enum chan_offset *offset)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
void *drv = phl_to_drvpriv(phl_info);
struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com);
u8 band_idx = wifi_role->hw_band;
bool is_ch_grouped = false;
struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[band_idx]);
int chanctx_num = 0;
u8 chctx_role_num = 0;
if(!chan || !bw || !offset)
goto _exit;
if (*chan == 0) {
PHL_ERR("%s req chan = 0 \n", __func__);
goto _exit;
}
/*status check*/
if (mr_ctl->is_sb) {
if (band_idx == 1) {
PHL_ERR("wrole:%d in band_idx:%d\n", wifi_role->id, band_idx);
goto _exit;
}
}
is_ch_grouped = phl_chanctx_add(phl_info, wifi_role, chan, bw, offset);
if (is_ch_grouped) {
chanctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl);
if (chanctx_num == 2) {
band_ctrl->op_mode = MR_OP_MCC;
} else if (chanctx_num == 1) {
struct rtw_chan_ctx *chanctx = NULL;
struct phl_queue *chan_ctx_queue = &band_ctrl->chan_ctx_queue;
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
chanctx = list_first_entry(&chan_ctx_queue->queue,
struct rtw_chan_ctx, list);
chctx_role_num = phl_chanctx_get_rnum(phl_info, chan_ctx_queue, chanctx);
if (chctx_role_num >= 2)
band_ctrl->op_mode = MR_OP_SCC;
else
band_ctrl->op_mode = MR_OP_NON;
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
}
}
#ifdef CONFIG_DBCC_SUPPORT
else {
if ((phl_com->dev_cap.hw_sup_flags & HW_SUP_DBCC) && (phl_com->dev_cap.dbcc_sup)) {
/*TODO - info core layer */
}
}
#endif
_exit:
PHL_DUMP_MR_EX(phl_info);
return is_ch_grouped;
}
enum rtw_phl_status
rtw_phl_chanctx_del_no_self(void *phl, struct rtw_wifi_role_t *wifi_role)
{
enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
void *drv = phl_to_drvpriv(phl_info);
struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com);
struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]);
struct rtw_chan_ctx *chanctx = NULL;
int chctx_num = 0;
chctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl);
if (chctx_num > 2) {
PHL_ERR("%s ERR - chanctx_num(%d) > 2\n", __func__, chctx_num);
_os_warn_on(1);
goto _exit;
}
if (chctx_num == 0) {
phl_sts = RTW_PHL_STATUS_SUCCESS;
PHL_INFO("%s - chctx_num = 0\n", __func__);
goto _exit;
}
else if (chctx_num == 1) { /*SCC*/
_os_spinlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
if (!list_empty(&band_ctrl->chan_ctx_queue.queue)) {
chanctx = list_first_entry(&band_ctrl->chan_ctx_queue.queue,
struct rtw_chan_ctx, list);
phl_sts = _phl_chanctx_del(phl_info, &band_ctrl->chan_ctx_queue, chanctx);
if (phl_sts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("_phl_chanctx_del failed\n");
_os_warn_on(1);
}
}
_os_spinunlock(drv, &band_ctrl->chan_ctx_queue.lock, _ps, NULL);
_os_kmem_free(drv, chanctx, sizeof(struct rtw_chan_ctx));
}
else if (chctx_num == 2) { /*MCC*/
}
_exit:
PHL_DUMP_MR_EX(phl_info);
return phl_sts;
}
int rtw_phl_chanctx_del(void *phl, struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chan_def)
{
enum rtw_phl_status phl_sts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
void *drv = phl_to_drvpriv(phl_info);
struct mr_ctl_t *mr_ctl = phlcom_to_mr_ctrl(phl_com);
struct hw_band_ctl_t *band_ctrl = &(mr_ctl->band_ctrl[wifi_role->hw_band]);
struct phl_queue *chan_ctx_queue = &band_ctrl->chan_ctx_queue;
struct rtw_chan_ctx *target_chanctx = NULL;
struct rtw_chan_ctx *chanctx = NULL;
int chctx_num = 0;
u8 chctx_role_num = 0;
u8 band_role_num = 0;
if (wifi_role == NULL) {
PHL_ERR("%s wifi_role == NULL!!\n", __func__);
/*_os_warn_on(1);*/
goto _exit;
}
target_chanctx = wifi_role->chanctx;
if (target_chanctx == NULL) {
PHL_ERR("%s wifi_role->chanctx == NULL\n", __func__);
/*_os_warn_on(1);*/
goto _exit;
}
/*init chan_def*/
if (chan_def)
chan_def->chan = 0;
chctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl);
band_role_num = phl_mr_get_role_num(phl_info, band_ctrl);
chctx_role_num = phl_chanctx_get_rnum_with_lock(phl_info, chan_ctx_queue, target_chanctx);
if (chctx_num == 0 || chctx_role_num == 0) {
PHL_ERR("%s ERR - chanctx_num(%d), role_num(%d)\n", __func__, chctx_num, chctx_role_num);
_os_warn_on(1);
goto _exit;
}
if (chctx_num > 2) {
PHL_ERR("%s ERR - chanctx_num(%d) > 2\n", __func__, chctx_num);
_os_warn_on(1);
goto _exit;
}
if (chctx_role_num == 1) { /*single role on this chctx*/
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
phl_sts = _phl_chanctx_rmap_clr(phl_info, wifi_role,
chan_ctx_queue, target_chanctx);
if (phl_sts != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("_phl_chanctx_rmap_clr failed\n");
phl_sts = _phl_chanctx_del(phl_info, chan_ctx_queue, target_chanctx);
if (phl_sts != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("_phl_chanctx_del failed\n");
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
_os_kmem_free(drv, target_chanctx, sizeof(struct rtw_chan_ctx));
} else { /*multi roles on this chctx*/
phl_sts = _phl_chanctx_rmap_clr_with_lock(phl_info, wifi_role,
chan_ctx_queue, target_chanctx);
if (phl_sts != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("_phl_chanctx_rmap_clr_with_lock failed\n");
phl_sts = phl_mr_chandef_upt(phl_info, band_ctrl, target_chanctx);
if (phl_sts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("phl_mr_chandef_upt failed\n");
_os_warn_on(1);
goto _exit;
}
}
chctx_num = phl_mr_get_chanctx_num(phl_info, band_ctrl);
if (chctx_num == 0) {
band_ctrl->op_mode = MR_OP_NON;
}
else if (chctx_num == 1) {
_os_spinlock(drv, &chan_ctx_queue->lock, _ps, NULL);
chanctx = list_first_entry(&chan_ctx_queue->queue,
struct rtw_chan_ctx, list);
chctx_role_num = phl_chanctx_get_rnum(phl_info, chan_ctx_queue, chanctx);
if (chan_def)
_os_mem_cpy(drv, chan_def, &chanctx->chan_def, sizeof(struct rtw_chan_def));
_os_spinunlock(drv, &chan_ctx_queue->lock, _ps, NULL);
#ifdef DBG_PHL_MR
if (chctx_role_num == 0) {
PHL_ERR("chctx_num=1, chctx_role_num=0\n");
_os_warn_on(1);
}
#endif
band_ctrl->op_mode = (chctx_role_num == 1) ? MR_OP_NON : MR_OP_SCC;
} else if (chctx_num == 2) {
if (chan_def)
_os_mem_cpy(drv, chan_def, &target_chanctx->chan_def, sizeof(struct rtw_chan_def));
band_ctrl->op_mode = MR_OP_MCC;
}
phl_sts = RTW_PHL_STATUS_SUCCESS;
PHL_INFO("%s - Bidx(%d) - Total role_num:%d, chctx_num:%d, target-chctx rnum:%d, op_mode:%d\n",
__func__, band_ctrl->id, band_role_num, chctx_num, chctx_role_num, band_ctrl->op_mode);
_exit:
PHL_DUMP_MR_EX(phl_info);
return chctx_num;
}
#ifdef PHL_MR_PROC_CMD
bool rtw_phl_chanctx_test(void *phl, struct rtw_wifi_role_t *wifi_role, bool is_add,
u8 *chan, enum channel_width *bw, enum chan_offset *offset)
{
bool rst = true;
int chanctx_num = 0;
struct rtw_chan_def chan_def = {0};
if (is_add) {
rst = rtw_phl_chanctx_add(phl, wifi_role, chan, bw, offset);
}
else {
chanctx_num = rtw_phl_chanctx_del(phl, wifi_role, &chan_def);
PHL_ERR("%s chctx_num = %d\n", __func__, chanctx_num);
PHL_DUMP_CHAN_DEF(&chan_def);
}
return rst;
}
#endif
enum band_type rtw_phl_get_band_type(u8 chan)
{
/*TODO - BAND_ON_6G*/
return (chan > 14) ? BAND_ON_5G : BAND_ON_24G;
}
u8 rtw_phl_get_center_ch(u8 ch,
enum channel_width bw, enum chan_offset offset)
{
u8 cch = ch;
if (bw == CHANNEL_WIDTH_160) {
if (ch % 4 == 0) {
if (ch >= 36 && ch <= 64)
cch = 50;
else if (ch >= 100 && ch <= 128)
cch = 114;
} else if (ch % 4 == 1) {
if (ch >= 149 && ch <= 177)
cch = 163;
}
} else if (bw == CHANNEL_WIDTH_80) {
if (ch <= 14)
cch = 7; /* special case for 2.4G */
else if (ch % 4 == 0) {
if (ch >= 36 && ch <= 48)
cch = 42;
else if (ch >= 52 && ch <= 64)
cch = 58;
else if (ch >= 100 && ch <= 112)
cch = 106;
else if (ch >= 116 && ch <= 128)
cch = 122;
else if (ch >= 132 && ch <= 144)
cch = 138;
} else if (ch % 4 == 1) {
if (ch >= 149 && ch <= 161)
cch = 155;
else if (ch >= 165 && ch <= 177)
cch = 171;
}
} else if (bw == CHANNEL_WIDTH_40) {
if (offset == CHAN_OFFSET_UPPER)
cch = ch + 2;
else if (offset == CHAN_OFFSET_LOWER)
cch = ch - 2;
} else if (bw == CHANNEL_WIDTH_20
|| bw == CHANNEL_WIDTH_10
|| bw == CHANNEL_WIDTH_5) {
; /* the same as ch */
}
else {
PHL_ERR("%s failed\n", __func__);
}
return cch;
}
/*
* Refer to 80211 spec Annex E Table E-4 Global operating classes
* Handle 2.4G/5G Bandwidth 20/40/80/160
*/
u8
rtw_phl_get_operating_class(
struct rtw_chan_def chan_def
)
{
u8 operating_class = 0;
if(chan_def.bw == CHANNEL_WIDTH_20){
if(chan_def.chan <= 13)
operating_class = 81;
else if(chan_def.chan ==14)
operating_class = 82;
else if(chan_def.chan >= 36 && chan_def.chan <= 48)
operating_class = 115;
else if(chan_def.chan >= 52 && chan_def.chan <= 64)
operating_class = 118;
else if(chan_def.chan >= 100 && chan_def.chan <= 144)
operating_class = 121;
else if(chan_def.chan >= 149 && chan_def.chan <= 169)
operating_class = 125;
else
PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.chan);
}
else if(chan_def.bw == CHANNEL_WIDTH_40){
if(chan_def.offset == CHAN_OFFSET_UPPER){
if(chan_def.chan >= 1 && chan_def.chan <= 9)
operating_class = 83;
else if(chan_def.chan == 36 || chan_def.chan == 44)
operating_class = 116;
else if(chan_def.chan == 52 || chan_def.chan == 60)
operating_class = 119;
else if(chan_def.chan == 100 || chan_def.chan == 108 ||
chan_def.chan == 116 || chan_def.chan == 124 ||
chan_def.chan == 132 || chan_def.chan == 140)
operating_class = 122;
else if(chan_def.chan == 149 || chan_def.chan == 157)
operating_class = 126;
else
PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.chan);
}
else if(chan_def.offset == CHAN_OFFSET_LOWER){
if(chan_def.chan >= 5 && chan_def.chan <= 13)
operating_class = 84;
else if(chan_def.chan == 40 || chan_def.chan == 48)
operating_class = 117;
else if(chan_def.chan == 56 || chan_def.chan == 64)
operating_class = 120;
else if(chan_def.chan == 104 || chan_def.chan == 112 ||
chan_def.chan == 120 || chan_def.chan == 128 ||
chan_def.chan == 136 || chan_def.chan == 144)
operating_class = 123;
else if(chan_def.chan == 153 || chan_def.chan == 161)
operating_class = 127;
else
PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.chan);
}
else{
PHL_WARN("%s: Invalid offset(%d)\n",
__FUNCTION__, chan_def.offset);
}
}
else if(chan_def.bw == CHANNEL_WIDTH_80){
if(chan_def.center_ch == 42 || chan_def.center_ch == 58 ||
chan_def.center_ch == 106 || chan_def.center_ch == 122 ||
chan_def.center_ch == 138 || chan_def.center_ch == 155)
operating_class = 128;
else
PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.center_ch);
}
else if(chan_def.bw == CHANNEL_WIDTH_160){
if(chan_def.center_ch == 50 || chan_def.center_ch == 114)
operating_class = 129;
else
PHL_WARN("%s: Undefined channel (%d)\n", __FUNCTION__, chan_def.center_ch);
}
else{
PHL_WARN("%s: Not handle bandwidth (%d)\n", __FUNCTION__, chan_def.bw);
}
return operating_class;
}
bool
rtw_phl_get_chandef_from_operating_class(
u8 channel,
u8 operating_class,
struct rtw_chan_def *chan_def
)
{
bool ret = true;
if(operating_class == 81 || operating_class == 82 ||
operating_class == 115 || operating_class == 118 ||
operating_class == 118 || operating_class == 121 ||
operating_class == 125){
chan_def->chan = channel;
chan_def->bw = CHANNEL_WIDTH_20;
chan_def->offset = CHAN_OFFSET_NO_EXT;
chan_def->center_ch = rtw_phl_get_center_ch(channel,
CHANNEL_WIDTH_20,
CHAN_OFFSET_NO_EXT);
}
else if(operating_class == 83 || operating_class == 116 ||
operating_class == 119 || operating_class == 122 ||
operating_class == 126){
chan_def->chan = channel;
chan_def->bw = CHANNEL_WIDTH_40;
chan_def->offset = CHAN_OFFSET_UPPER;
chan_def->center_ch = rtw_phl_get_center_ch(channel,
CHANNEL_WIDTH_40,
CHAN_OFFSET_UPPER);
}
else if(operating_class == 84 || operating_class == 117 ||
operating_class == 120 || operating_class == 123 ||
operating_class == 127){
chan_def->chan = channel;
chan_def->bw = CHANNEL_WIDTH_40;
chan_def->offset = CHAN_OFFSET_LOWER;
chan_def->center_ch = rtw_phl_get_center_ch(channel,
CHANNEL_WIDTH_40,
CHAN_OFFSET_LOWER);
}
else if(operating_class == 128){
chan_def->chan = channel;
chan_def->bw = CHANNEL_WIDTH_80;
chan_def->offset = CHAN_OFFSET_NO_DEF;
chan_def->center_ch = rtw_phl_get_center_ch(channel,
CHANNEL_WIDTH_80,
CHAN_OFFSET_NO_DEF);
}
else if(operating_class == 129){
chan_def->chan = channel;
chan_def->bw = CHANNEL_WIDTH_160;
chan_def->offset = CHAN_OFFSET_NO_DEF;
chan_def->center_ch = rtw_phl_get_center_ch(channel,
CHANNEL_WIDTH_40,
CHAN_OFFSET_NO_DEF);
}
else{
PHL_ERR("%s: Unknown operating class (%d)\n", __FUNCTION__, operating_class);
ret = false;
}
return ret;
}
|
2301_81045437/rtl8852be
|
phl/phl_chan.c
|
C
|
agpl-3.0
| 43,923
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CHANA_H_
#define _PHL_CHANA_H_
u8 phl_chanctx_get_rnum(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx);
u8 phl_chanctx_get_rnum_with_lock(struct phl_info_t *phl_info,
struct phl_queue *chan_ctx_queue,
struct rtw_chan_ctx *chanctx);
u8 phl_get_chanctx_rolemap(struct phl_info_t *phl_info, u8 band_idx);
enum rtw_phl_status
phl_chanctx_free(struct phl_info_t *phl_info, struct hw_band_ctl_t *band_ctl);
enum rtw_phl_status
phl_set_ch_bw(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chdef, bool do_rfk);
bool rtw_phl_chanctx_add(void *phl, struct rtw_wifi_role_t *wifi_role,
u8 *chan, enum channel_width *bw, enum chan_offset *offset);
int rtw_phl_chanctx_del(void *phl, struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chan_def);
#ifdef CONFIG_CMD_DISP
enum rtw_phl_status
phl_cmd_chg_op_chdef_start_hdl(struct phl_info_t *phl, u8 *param);
enum rtw_phl_status
phl_cmd_set_ch_bw_hdl(struct phl_info_t *phl_info, u8 *param);
enum rtw_phl_status
rtw_phl_cmd_set_ch_bw(struct rtw_wifi_role_t *wifi_role,
struct rtw_chan_def *chdef,
bool do_rfk,
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
enum rtw_phl_status
phl_cmd_dfs_tx_pause_hdl(struct phl_info_t *phl_info, u8 *param);
#endif
#ifdef DBG_PHL_CHAN
void phl_chan_dump_chandef(const char *caller, const int line, bool show_caller,
struct rtw_chan_def *chandef);
#define PHL_DUMP_CHAN_DEF(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, false, _chandef);
#define PHL_DUMP_CHAN_DEF_EX(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, true, _chandef);
#else
#define PHL_DUMP_CHAN_DEF(_chandef)
#define PHL_DUMP_CHAN_DEF_EX(_chandef)
#endif
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_phl_status
rtw_phl_dbcc_test(void *phl, enum dbcc_test_id id, void *param);
#endif
enum band_type rtw_phl_get_band_type(u8 chan);
u8 rtw_phl_get_center_ch(u8 ch,
enum channel_width bw, enum chan_offset offset);
u8
rtw_phl_get_operating_class(
struct rtw_chan_def chan_def
);
bool
rtw_phl_get_chandef_from_operating_class(
u8 channel,
u8 operating_class,
struct rtw_chan_def *chan_def
);
#endif /*_PHL_CHANA_H_*/
|
2301_81045437/rtl8852be
|
phl/phl_chan.h
|
C
|
agpl-3.0
| 2,913
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CHAN_INFO_C_
#include "phl_headers.h"
#ifdef CONFIG_PHL_CHANNEL_INFO
struct chinfo_param {
struct rtw_phl_stainfo_t *sta;
u8 enable;
};
enum rtw_phl_status
_phl_cfg_chinfo(void *phl, struct rtw_phl_stainfo_t *sta, u8 enable)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
if (RTW_HAL_STATUS_SUCCESS == rtw_hal_cfg_chinfo(phl_info->hal, sta, enable))
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
#ifdef CONFIG_CMD_DISP
enum rtw_phl_status
phl_cmd_cfg_chinfo_hdl(struct phl_info_t *phl_info, u8 *param)
{
struct chinfo_param *chinfo = (struct chinfo_param *)param;
return _phl_cfg_chinfo(phl_info, chinfo->sta, chinfo->enable);
}
static void _phl_cfg_chinfo_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status)
{
if (cmd) {
_os_kmem_free(drv_priv, cmd, cmd_len);
cmd = NULL;
PHL_INFO("%s.....\n", __func__);
}
}
enum rtw_phl_status
_phl_cmd_cfg_chinfo(void *phl, struct rtw_phl_stainfo_t *sta, u8 enable,
enum phl_cmd_type cmd_type, u32 cmd_timeout)
{
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct chinfo_param *param = NULL;
u32 param_len;
if (cmd_type == PHL_CMD_DIRECTLY) {
return _phl_cfg_chinfo(phl, sta, enable);
}
param_len = sizeof(struct chinfo_param);
param = _os_kmem_alloc(phl_to_drvpriv(phl_info), param_len);
if (param == NULL) {
PHL_ERR("%s: alloc param failed!\n", __func__);
goto _exit;
}
param->enable = enable;
param->sta =sta;
sts = phl_cmd_enqueue(phl,
sta->wrole->hw_band,
MSG_EVT_CFG_CHINFO,
(u8 *)param,
param_len,
_phl_cfg_chinfo_done,
cmd_type, cmd_timeout);
if (is_cmd_failure(sts)) {
/* Send cmd success, but wait cmd fail*/
sts = RTW_PHL_STATUS_FAILURE;
} else if (sts != RTW_PHL_STATUS_SUCCESS) {
/* Send cmd fail */
_os_kmem_free(phl_to_drvpriv(phl_info), param, param_len);
sts = RTW_PHL_STATUS_FAILURE;
}
_exit:
return sts;
}
#endif
enum rtw_phl_status rtw_phl_cmd_cfg_chinfo(void *phl,
struct rtw_phl_stainfo_t *sta,
u8 enable,
enum phl_cmd_type cmd_type,
u32 cmd_timeout)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
#ifdef CONFIG_CMD_DISP
return _phl_cmd_cfg_chinfo(phl, sta, enable, cmd_type, cmd_timeout);
#else
return _phl_cfg_chinfo(phl_info, sta, enable);
#endif
}
enum rtw_phl_status rtw_phl_query_chan_info(void *phl, u32 buf_len,
u8* chan_info_buffer, u32 *length, struct csi_header_t *csi_header)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
void *drv_priv = phl_to_drvpriv(phl_info);
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
struct chan_info_t *chan_info_pkt_latest = NULL;
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
if(chan_info_buffer == NULL){
PHL_ERR("buffer is not ready.\n");
return status;
}
/* Get the latest channel info from busy queue. */
chan_info_pkt_latest = rtw_phl_query_busy_chaninfo_latest(drv_priv, phl_com);
if (chan_info_pkt_latest != NULL) {
if (buf_len < chan_info_pkt_latest->length) {
PHL_ERR("%s: Buffer length not sufficient! \n", __func__);
rtw_phl_enqueue_idle_chaninfo(drv_priv, phl_com, chan_info_pkt_latest);
return status;
}
/* copy raw data resources. */
_os_mem_cpy(drv_priv, chan_info_buffer,
chan_info_pkt_latest->chan_info_buffer, chan_info_pkt_latest->length);
_os_mem_cpy(drv_priv, csi_header,
&chan_info_pkt_latest->csi_header, sizeof(struct csi_header_t));
*length = chan_info_pkt_latest->length;
rtw_phl_enqueue_idle_chaninfo(drv_priv, phl_com, chan_info_pkt_latest);
status = RTW_PHL_STATUS_SUCCESS;
} else {
PHL_INFO("%s: There is no channel info packet.\n", __func__);
}
return status;
}
/*channel info packet pool init/deinit*/
static void _phl_chaninfo_deinit (struct phl_info_t *phl_info)
{
struct rx_chan_info_pool *chan_info_pool = NULL;
u8* chan_info_buffer = NULL;
u32 buf_len, i = 0;
FUNCIN();
chan_info_pool = (struct rx_chan_info_pool *)phl_info->phl_com->chan_info_pool;
if (NULL != chan_info_pool) {
_os_spinlock_free(phl_to_drvpriv(phl_info),
&chan_info_pool->idle_lock);
_os_spinlock_free(phl_to_drvpriv(phl_info),
&chan_info_pool->busy_lock);
for (i = 0; i < CHAN_INFO_PKT_TOTAL; i++) {
chan_info_buffer = chan_info_pool->channl_info_pkt[i].chan_info_buffer;
if (chan_info_buffer != NULL) {
_os_mem_free(phl_to_drvpriv(phl_info), chan_info_buffer,
CHAN_INFO_MAX_SIZE);
chan_info_pool->channl_info_pkt[i].chan_info_buffer = NULL;
}
}
buf_len = sizeof(*chan_info_pool);
_os_mem_free(phl_to_drvpriv(phl_info), chan_info_pool, buf_len);
}
FUNCOUT();
}
static enum rtw_phl_status _phl_chaninfo_init(struct phl_info_t *phl_info)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
struct rx_chan_info_pool *chan_info_pool = NULL;
struct chan_info_t *chan_info_pkt = NULL;
u32 buf_len = 0, i = 0;
FUNCIN_WSTS(pstatus);
buf_len = sizeof(*chan_info_pool);
chan_info_pool = _os_mem_alloc(phl_to_drvpriv(phl_info), buf_len);
if (NULL != chan_info_pool) {
_os_mem_set(phl_to_drvpriv(phl_info), chan_info_pool, 0, buf_len);
INIT_LIST_HEAD(&chan_info_pool->idle);
INIT_LIST_HEAD(&chan_info_pool->busy);
_os_spinlock_init(phl_to_drvpriv(phl_info),
&chan_info_pool->idle_lock);
_os_spinlock_init(phl_to_drvpriv(phl_info),
&chan_info_pool->busy_lock);
chan_info_pool->idle_cnt = 0;
for (i = 0; i < CHAN_INFO_PKT_TOTAL; i++) {
chan_info_pkt = &chan_info_pool->channl_info_pkt[i];
chan_info_pkt->chan_info_buffer = _os_mem_alloc(phl_to_drvpriv(phl_info),
CHAN_INFO_MAX_SIZE);
if (NULL != chan_info_pkt->chan_info_buffer) {
chan_info_pkt->length = 0;
INIT_LIST_HEAD(&chan_info_pkt->list);
list_add_tail(&chan_info_pkt->list, &chan_info_pool->idle);
chan_info_pool->idle_cnt++;
} else {
pstatus = RTW_PHL_STATUS_RESOURCE;
break;
}
}
phl_info->phl_com->chan_info_pool = chan_info_pool;
} else {
pstatus = RTW_PHL_STATUS_RESOURCE;
}
if (RTW_PHL_STATUS_SUCCESS != pstatus)
_phl_chaninfo_deinit(phl_info);
FUNCOUT_WSTS(pstatus);
return pstatus;
}
enum rtw_phl_status phl_chaninfo_init(struct phl_info_t *phl_info)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
phl_status = _phl_chaninfo_init(phl_info);
if (phl_status != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("channel info pool allocate fail\n");
return phl_status;
}
void phl_chaninfo_deinit(struct phl_info_t *phl_info)
{
_phl_chaninfo_deinit(phl_info);
}
u32 rtw_phl_get_chaninfo_idle_number(void* drv_priv, struct rtw_phl_com_t *phl_com)
{
u32 number;
struct rx_chan_info_pool *chan_info_pool = NULL;
chan_info_pool = phl_com->chan_info_pool;
number = chan_info_pool->idle_cnt;
return number;
}
u32 rtw_phl_get_chaninfo_busy_number(void* drv_priv, struct rtw_phl_com_t *phl_com)
{
u32 number;
struct rx_chan_info_pool *chan_info_pool = NULL;
chan_info_pool = phl_com->chan_info_pool;
number = chan_info_pool->busy_cnt;
return number;
}
struct chan_info_t *rtw_phl_query_idle_chaninfo(void* drv_priv, struct rtw_phl_com_t *phl_com)
{
struct rx_chan_info_pool *chan_info_pool = NULL;
struct chan_info_t *chan_info_pkt = NULL;
chan_info_pool = phl_com->chan_info_pool;
_os_spinlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL);
if (false == list_empty(&chan_info_pool->idle)) {
chan_info_pkt = list_first_entry(&chan_info_pool->idle,
struct chan_info_t, list);
list_del(&chan_info_pkt->list);
chan_info_pool->idle_cnt--;
}
_os_spinunlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL);
return chan_info_pkt;
}
struct chan_info_t *rtw_phl_query_busy_chaninfo(void* drv_priv, struct rtw_phl_com_t *phl_com)
{
struct rx_chan_info_pool *chan_info_pool = NULL;
struct chan_info_t *chan_info_pkt = NULL;
chan_info_pool = phl_com->chan_info_pool;
_os_spinlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL);
if (false == list_empty(&chan_info_pool->busy)) {
chan_info_pkt = list_first_entry(&chan_info_pool->busy,
struct chan_info_t, list);
list_del(&chan_info_pkt->list);
chan_info_pool->busy_cnt--;
}
_os_spinunlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL);
return chan_info_pkt;
}
struct chan_info_t *rtw_phl_query_busy_chaninfo_latest(void* drv_priv, struct rtw_phl_com_t *phl_com)
{
struct rx_chan_info_pool *chan_info_pool = NULL;
struct chan_info_t *chan_info_pkt = NULL;
chan_info_pool = phl_com->chan_info_pool;
_os_spinlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL);
if (false == list_empty(&chan_info_pool->busy)) {
chan_info_pkt = list_last_entry(&chan_info_pool->busy,
struct chan_info_t, list);
list_del(&chan_info_pkt->list);
chan_info_pool->busy_cnt--;
}
_os_spinunlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL);
return chan_info_pkt;
}
void rtw_phl_enqueue_idle_chaninfo(void* drv_priv, struct rtw_phl_com_t *phl_com,
struct chan_info_t *chan_info_pkt)
{
struct rx_chan_info_pool *chan_info_pool = NULL;
chan_info_pool = phl_com->chan_info_pool;
_os_spinlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL);
_os_mem_set(drv_priv, &chan_info_pkt->csi_header, 0,
sizeof( chan_info_pkt->csi_header));
_os_mem_set(drv_priv, chan_info_pkt->chan_info_buffer, 0,
CHAN_INFO_MAX_SIZE);
chan_info_pkt->length = 0;
INIT_LIST_HEAD(&chan_info_pkt->list);
list_add_tail(&chan_info_pkt->list, &chan_info_pool->idle);
chan_info_pool->idle_cnt++;
_os_spinunlock(drv_priv, &chan_info_pool->idle_lock, _bh, NULL);
}
struct chan_info_t * rtw_phl_recycle_busy_chaninfo(void* drv_priv,
struct rtw_phl_com_t *phl_com, struct chan_info_t *chan_info_pkt)
{
struct rx_chan_info_pool *chan_info_pool = NULL;
struct chan_info_t *chan_info_pkt_recycle = NULL;
chan_info_pool = phl_com->chan_info_pool;
_os_spinlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL);
/* enqueue the latest first. */
INIT_LIST_HEAD(&chan_info_pkt->list);
list_add_tail(&chan_info_pkt->list, &chan_info_pool->busy);
chan_info_pool->busy_cnt++;
/* if the number is greater than max, dequeue the oldest one.*/
if (chan_info_pool->busy_cnt > MAX_CHAN_INFO_PKT_KEEP) {
chan_info_pkt_recycle = list_first_entry(&chan_info_pool->busy,
struct chan_info_t, list);
list_del(&chan_info_pkt_recycle->list);
chan_info_pool->busy_cnt--;
}
_os_spinunlock(drv_priv, &chan_info_pool->busy_lock, _bh, NULL);
return chan_info_pkt_recycle;
}
#endif /* CONFIG_PHL_CHANNEL_INFO */
|
2301_81045437/rtl8852be
|
phl/phl_chan_info.c
|
C
|
agpl-3.0
| 11,134
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CHAN_INFO_H_
#define _PHL_CHAN_INFO_H_
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_phl_status phl_chaninfo_init(struct phl_info_t *phl_info);
void phl_chaninfo_deinit(struct phl_info_t *phl_info);
/* Channel info queue operation*/
u32 rtw_phl_get_chaninfo_idle_number(void *drvpriv, struct rtw_phl_com_t *phl_com);
u32 rtw_phl_get_chaninfo_busy_number(void *drvpriv, struct rtw_phl_com_t *phl_com);
struct chan_info_t *rtw_phl_query_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com);
struct chan_info_t *rtw_phl_query_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com);
struct chan_info_t *rtw_phl_query_busy_chaninfo_latest(void *drvpriv, struct rtw_phl_com_t *phl_com);
void rtw_phl_enqueue_idle_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com,
struct chan_info_t *chan_info_pkt);
struct chan_info_t * rtw_phl_recycle_busy_chaninfo(void *drvpriv, struct rtw_phl_com_t *phl_com,
struct chan_info_t *chan_info_pkt);
enum rtw_phl_status
phl_cmd_cfg_chinfo_hdl(struct phl_info_t *phl_info, u8 *param);
#endif /* CONFIG_PHL_CHANNEL_INFO */
#endif /* _PHL_CHAN_INFO_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_chan_info.h
|
C
|
agpl-3.0
| 1,767
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "phl_headers.h"
#include "phl_chnlplan.h"
const struct chdef_2ghz chdef2g[MAX_CHDEF_2GHZ] = {
{0, {0x00, 0x00}, {0x00, 0x00}},
{1, {0xff, 0x1f}, {0x00, 0x18}},
{2, {0xff, 0x1f}, {0x00, 0x00}},
{3, {0xff, 0x07}, {0x00, 0x00}},
{4, {0xff, 0x3f}, {0x00, 0x00}},
{5, {0x00, 0x1e}, {0x00, 0x00}},
{6, {0xff, 0x3f}, {0x00, 0x38}},
};
const struct chdef_5ghz chdef5g[MAX_CHDEF_5GHZ] = {
{0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00},
{1, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00},
{2, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x00, 0x00, 0x00},
{3, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x1f, 0x00, 0x00},
{4, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x01}, {0x00, 0x00}, {0xff, 0x01}, 0x1f, 0x00, 0x00},
{5, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x7f, 0x00}, {0x00, 0x00}, {0x7f, 0x00}, 0x0f, 0x00, 0x00},
{6, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{7, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{8, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x0f, 0x00, 0x00},
{9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{10, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00},
{11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x00, 0x00, 0x00},
{12, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00},
{13, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{14, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00},
{15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x0f, 0x00, 0x00},
{16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0xff, 0x07}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00},
{17, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x07}, {0x00, 0x00}, {0x00, 0x07}, 0x1f, 0x00, 0x00},
{18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00},
{19, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x00, 0x00, 0x00},
{20, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x0f, 0x00, 0x00},
{21, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x07}, {0x00, 0x00}, {0x00, 0x07}, 0x00, 0x00, 0x00},
{22, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0x1f, 0x00, 0x00},
{23, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x00}, {0x00, 0x00}, {0xff, 0x00}, 0x1f, 0x00, 0x00},
{24, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x1f, 0x00},
{25, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{26, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{27, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0x1f, 0x07}, {0x1f, 0x07}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{28, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{29, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{30, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x1f, 0x00},
{31, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x1f, 0x1f, 0x00},
{32, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x00, 0x00},
{33, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x0f}, {0x00, 0x00}, {0x1f, 0x0f}, 0x1f, 0x00, 0x00},
{34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00},
{35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x00, 0x00, 0x00},
{36, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x0f, {0xff, 0x0f}, {0xff, 0x0f}, {0xff, 0x0f}, 0x1f, 0x1f, 0x00},
{37, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x00, 0x00, 0x00},
{38, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0x00, 0x00, 0x00},
{39, 0x0f, 0x0f, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x00}, {0x00, 0x00}, {0xff, 0x00}, 0x1f, 0x00, 0x1f},
{40, 0x0f, 0x0f, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x07}, {0x00, 0x00}, {0x1f, 0x07}, 0x1f, 0x00, 0x00},
{41, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x1f, 0x1f, 0x00},
{42, 0x0f, 0x0f, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x07}, {0x00, 0x00}, {0xff, 0x07}, 0x1f, 0x1f, 0x00},
{43, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x06}, {0xff, 0x06}, {0x00, 0x00}, 0x1f, 0x1f, 0x00},
{44, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x1f, 0x07}, {0x1f, 0x07}, {0x00, 0x00}, 0x1f, 0x1f, 0x00},
{45, 0x0f, 0x0f, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x1f, 0x1f, 0x00},
{46, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, 0x0f, 0x00, 0x00},
{47, 0x0f, 0x00, 0x00, 0x0f, 0x0f, 0x00, {0xff, 0x07}, {0xff, 0x07}, {0x00, 0x00}, 0x00, 0x00, 0x00},
{48, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0x00, 0x00, 0x00},
{49, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x01}, {0x00, 0x00}, {0xff, 0x01}, 0x00, 0x00, 0x00},
{50, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x00, 0x0f}, {0x00, 0x00}, {0x00, 0x0f}, 0x1f, 0x00, 0x00},
{51, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x1f, 0x00}, {0x00, 0x00}, {0x1f, 0x00}, 0x00, 0x00, 0x00},
{52, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0xff, 0x0f}, {0x00, 0x00}, {0xff, 0x0f}, 0xff, 0x00, 0x00},
{53, 0x0f, 0x00, 0x00, 0x0f, 0x00, 0x0f, {0x0f, 0x00}, {0x00, 0x00}, {0x0f, 0x00}, 0x1f, 0x00, 0x00},
};
const struct regulatory_domain_mapping rdmap[MAX_RD_MAP_NUM] = {
{0x00, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 49}},
{0x01, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 50}},
{0x02, {REGULATION_ETSI, 3}, {REGULATION_ETSI, 7}},
{0x03, {REGULATION_ACMA, 2}, {REGULATION_ACMA, 33}},
{0x04, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 51}},
{0x05, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 6}},
{0x06, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 7}},
{0x07, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 23}},
{0x08, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 21}},
{0x09, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 17}},
{0x1b, {REGULATION_FCC, 2}, {REGULATION_FCC, 52}},
{0x1c, {REGULATION_KCC, 2}, {REGULATION_KCC, 53}},
{0x20, {REGULATION_WW, 1}, {REGULATION_NA, 0}},
{0x21, {REGULATION_ETSI, 2}, {REGULATION_NA, 0}},
{0x22, {REGULATION_FCC, 3}, {REGULATION_NA, 0}},
{0x23, {REGULATION_MKK, 4}, {REGULATION_NA, 0}},
{0x24, {REGULATION_ETSI, 5}, {REGULATION_NA, 0}},
{0x25, {REGULATION_FCC, 3}, {REGULATION_FCC, 3}},
{0x26, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 2}},
{0x27, {REGULATION_MKK, 4}, {REGULATION_MKK, 2}},
{0x28, {REGULATION_KCC, 1}, {REGULATION_KCC, 5}},
{0x29, {REGULATION_FCC, 1}, {REGULATION_FCC, 6}},
{0x2a, {REGULATION_FCC, 2}, {REGULATION_NA, 0}},
{0x2b, {REGULATION_IC, 2}, {REGULATION_IC, 33}},
{0x2c, {REGULATION_MKK, 2}, {REGULATION_NA, 0}},
{0x2d, {REGULATION_CHILE, 1}, {REGULATION_CHILE, 22}},
{0x2e, {REGULATION_WW, 3}, {REGULATION_WW, 37}},
{0x2f, {REGULATION_CHILE, 1}, {REGULATION_CHILE, 38}},
{0x30, {REGULATION_FCC, 1}, {REGULATION_FCC, 7}},
{0x31, {REGULATION_FCC, 1}, {REGULATION_FCC, 8}},
{0x32, {REGULATION_FCC, 1}, {REGULATION_FCC, 9}},
{0x33, {REGULATION_FCC, 1}, {REGULATION_FCC, 10}},
{0x34, {REGULATION_FCC, 3}, {REGULATION_FCC, 1}},
{0x35, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 3}},
{0x36, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 4}},
{0x37, {REGULATION_MKK, 4}, {REGULATION_MKK, 10}},
{0x38, {REGULATION_MKK, 4}, {REGULATION_MKK, 11}},
{0x39, {REGULATION_NCC, 3}, {REGULATION_NCC, 12}},
{0x3a, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 2}},
{0x3b, {REGULATION_ACMA, 2}, {REGULATION_ACMA, 1}},
{0x3c, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 10}},
{0x3d, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 15}},
{0x3e, {REGULATION_KCC, 2}, {REGULATION_KCC, 3}},
{0x3f, {REGULATION_FCC, 3}, {REGULATION_FCC, 22}},
{0x40, {REGULATION_NCC, 3}, {REGULATION_NCC, 13}},
{0x41, {REGULATION_WW, 6}, {REGULATION_NA, 0}},
{0x42, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 14}},
{0x43, {REGULATION_FCC, 3}, {REGULATION_FCC, 6}},
{0x44, {REGULATION_NCC, 3}, {REGULATION_NCC, 9}},
{0x45, {REGULATION_ACMA, 1}, {REGULATION_ACMA, 1}},
{0x46, {REGULATION_FCC, 3}, {REGULATION_FCC, 15}},
{0x47, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 10}},
{0x48, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 7}},
{0x49, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 6}},
{0x4a, {REGULATION_IC, 3}, {REGULATION_IC, 33}},
{0x4b, {REGULATION_KCC, 2}, {REGULATION_KCC, 22}},
{0x4c, {REGULATION_FCC, 3}, {REGULATION_FCC, 28}},
{0x4d, {REGULATION_MEX, 2}, {REGULATION_MEX, 1}},
{0x4e, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 42}},
{0x4f, {REGULATION_NA, 0}, {REGULATION_MKK, 43}},
{0x50, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 16}},
{0x51, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 9}},
{0x52, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 17}},
{0x53, {REGULATION_NCC, 3}, {REGULATION_NCC, 18}},
{0x54, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 15}},
{0x55, {REGULATION_FCC, 3}, {REGULATION_FCC, 1}},
{0x56, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 19}},
{0x57, {REGULATION_FCC, 3}, {REGULATION_FCC, 20}},
{0x58, {REGULATION_MKK, 2}, {REGULATION_MKK, 14}},
{0x59, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 21}},
{0x5a, {REGULATION_NA, 0}, {REGULATION_FCC, 44}},
{0x5b, {REGULATION_NA, 0}, {REGULATION_FCC, 45}},
{0x5c, {REGULATION_NA, 0}, {REGULATION_FCC, 43}},
{0x5d, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 8}},
{0x5e, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 3}},
{0x5f, {REGULATION_MKK, 2}, {REGULATION_MKK, 47}},
{0x60, {REGULATION_FCC, 3}, {REGULATION_FCC, 9}},
{0x61, {REGULATION_FCC, 2}, {REGULATION_FCC, 1}},
{0x62, {REGULATION_FCC, 2}, {REGULATION_FCC, 3}},
{0x63, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 23}},
{0x64, {REGULATION_MKK, 2}, {REGULATION_MKK, 24}},
{0x65, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 24}},
{0x66, {REGULATION_FCC, 3}, {REGULATION_FCC, 27}},
{0x67, {REGULATION_FCC, 3}, {REGULATION_FCC, 25}},
{0x68, {REGULATION_FCC, 2}, {REGULATION_FCC, 27}},
{0x69, {REGULATION_FCC, 2}, {REGULATION_FCC, 25}},
{0x6a, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 25}},
{0x6b, {REGULATION_FCC, 1}, {REGULATION_FCC, 29}},
{0x6c, {REGULATION_FCC, 1}, {REGULATION_FCC, 26}},
{0x6d, {REGULATION_FCC, 2}, {REGULATION_FCC, 28}},
{0x6e, {REGULATION_FCC, 1}, {REGULATION_FCC, 25}},
{0x6f, {REGULATION_NA, 0}, {REGULATION_ETSI, 6}},
{0x70, {REGULATION_NA, 0}, {REGULATION_ETSI, 30}},
{0x71, {REGULATION_NA, 0}, {REGULATION_ETSI, 25}},
{0x72, {REGULATION_NA, 0}, {REGULATION_ETSI, 31}},
{0x73, {REGULATION_FCC, 1}, {REGULATION_FCC, 1}},
{0x74, {REGULATION_FCC, 2}, {REGULATION_FCC, 19}},
{0x75, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 32}},
{0x76, {REGULATION_FCC, 2}, {REGULATION_FCC, 22}},
{0x77, {REGULATION_ETSI, 1}, {REGULATION_ETSI, 34}},
{0x78, {REGULATION_FCC, 3}, {REGULATION_FCC, 35}},
{0x79, {REGULATION_MKK, 2}, {REGULATION_MKK, 2}},
{0x7a, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 28}},
{0x7b, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 46}},
{0x7c, {REGULATION_ETSI, 2}, {REGULATION_ETSI, 47}},
{0x7d, {REGULATION_MKK, 4}, {REGULATION_MKK, 48}},
{0x7e, {REGULATION_MKK, 2}, {REGULATION_MKK, 48}},
{0x7f, {REGULATION_WW, 1}, {REGULATION_WW, 36}},
};
|
2301_81045437/rtl8852be
|
phl/phl_chnlplan.c
|
C
|
agpl-3.0
| 12,824
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CHNLPLAN_H_
#define _PHL_CHNLPLAN_H_
#define REGULATION_CHPLAN_VERSION 58
enum REGULATION {
REGULATION_WW = 0,
REGULATION_ETSI = 1,
REGULATION_FCC = 2,
REGULATION_MKK = 3,
REGULATION_KCC = 4,
REGULATION_NCC = 5,
REGULATION_ACMA = 6,
REGULATION_NA = 7,
REGULATION_IC = 8,
REGULATION_CHILE = 9,
REGULATION_MEX = 10,
REGULATION_MAX = 11,
};
struct chdef_2ghz {
/* ch_def index */
u8 idx;
/* support channel list
* support_ch[0]: bit(0~7) stands for ch(1~8)
* support_ch[1]: bit(0~5) stands for ch (9~14)
*/
u8 support_ch[2];
/* passive ch list
* passive[0]: bit(0~7) stands for ch(1~8)
* passive[1]: bit(0~5) stands for ch (9~14)
*/
u8 passive[2];
};
struct chdef_5ghz {
/* ch_def index */
u8 idx;
/*
* band1 support channel list, passive and dfs
* bit0 stands for ch36
* bit1 stands for ch40
* bit2 stands for ch44
* bit3 stands for ch48
*/
u8 support_ch_b1;
u8 passive_b1;
u8 dfs_b1;
/*
* band2 support channel list, passive and dfs
* bit0 stands for ch52
* bit1 stands for ch56
* bit2 stands for ch60
* bit3 stands for ch64
*/
u8 support_ch_b2;
u8 passive_b2;
u8 dfs_b2;
/*
* band3 support channel list, passive and dfs
* byte[0]:
* bit0 stands for ch100
* bit1 stands for ch104
* bit2 stands for ch108
* bit3 stands for ch112
* bit4 stands for ch116
* bit5 stands for ch120
* bit6 stands for ch124
* bit7 stands for ch128
* byte[1]:
* bit0 stands for ch132
* bit1 stands for ch136
* bit2 stands for ch140
* bit3 stands for ch144
*/
u8 support_ch_b3[2];
u8 passive_b3[2];
u8 dfs_b3[2];
/*
* band4 support channel list, passive and dfs
* bit0 stands for ch149
* bit1 stands for ch153
* bit2 stands for ch157
* bit3 stands for ch161
* bit4 stands for ch165
* bit5 stands for ch169
* bit6 stands for ch173
* bit7 stands for ch177
*/
u8 support_ch_b4;
u8 passive_b4;
u8 dfs_b4;
};
struct freq_plan {
u8 regulation;
u8 ch_idx;
};
struct regulatory_domain_mapping {
u8 domain_code;
struct freq_plan freq_2g;
struct freq_plan freq_5g;
};
#define MAX_CHDEF_2GHZ 7
#define MAX_CHDEF_5GHZ 54
#define MAX_RD_MAP_NUM 108
#endif /* _PHL_CHNLPLAN_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_chnlplan.h
|
C
|
agpl-3.0
| 3,228
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "phl_headers.h"
#include "phl_chnlplan.h"
#include "phl_chnlplan_6g.h"
const struct chdef_6ghz chdef6g[MAX_CHDEF_6GHZ] = {
{0, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}},
{1, {0xff, 0xff, 0xff}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}},
{2, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x3f, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}},
{3, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0xff, 0xff, 0x03}, {0x00, 0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}},
{4, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 0x00, 0x00, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0xff, 0x07}, {0x00, 0x00}},
{5, {0xff, 0xff, 0xff}, {0xff, 0xff, 0xff}, 0x3f, 0x3f, {0xff, 0xff, 0x03}, {0xff, 0xff, 0x03}, {0xff, 0x07}, {0xff, 0x07}},
};
const struct regulatory_domain_mapping_6g rdmap6[MAX_RD_MAP_NUM_6GHZ] = {
{0x00, REGULATION_NA, 0},
{0x01, REGULATION_FCC, 1},
{0x02, REGULATION_FCC, 2},
{0x03, REGULATION_FCC, 3},
{0x04, REGULATION_FCC, 4},
{0x7f, REGULATION_WW, 5},
};
|
2301_81045437/rtl8852be
|
phl/phl_chnlplan_6g.c
|
C
|
agpl-3.0
| 1,829
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CHNLPLAN_6GHZ_H_
#define _PHL_CHNLPLAN_6GHZ_H_
/*
* 6 GHz channel group from UNII-5 to UNII-8
* channel index diff is 4 : minimum working bandwidth : 20 MHz
* => next channel index = current index + 4
*/
struct chdef_6ghz {
/* ch_def index */
u8 idx;
/*
* UNII-5 support channel list, ch1 ~ ch93, total : 24
* bit0 stands for ch1
* bit1 stands for ch5
* bit2 stands for ch9
* ...
* bit23 stands for ch93
*/
u8 support_ch_u5[3];
u8 passive_u5[3];
/*
* UNII-6 support channel list, ch97 ~ ch117, total : 6
* bit0 stands for ch97
* bit1 stands for ch101
* bit2 stands for ch105
* bit3 stands for ch109
* bit4 stands for ch113
* bit5 stands for ch117
*/
u8 support_ch_u6;
u8 passive_u6;
/*
* UNII-7 support channel list, ch121 ~ ch189, total : 18
* bit0 stands for ch121
* bit1 stands for ch125
* bit2 stands for ch129
* ...
* bit17 stands for ch189
*/
u8 support_ch_u7[3];
u8 passive_u7[3];
/*
* UNII-8 support channel list, ch193 ~ ch237, total : 12
* bit0 stands for ch193
* bit1 stands for ch197
* bit2 stands for ch201
* ...
* bit10 stands for ch233
*/
u8 support_ch_u8[2];
u8 passive_u8[2];
};
struct regulatory_domain_mapping_6g {
u8 domain_code;
u8 regulation;
u8 ch_idx;
};
#define MAX_CHDEF_6GHZ 6
#define MAX_RD_MAP_NUM_6GHZ 6
#endif /* _PHL_CHNLPLAN_6GHZ_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_chnlplan_6g.h
|
C
|
agpl-3.0
| 2,159
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CMD_BTC_C_
#include "phl_headers.h"
#ifdef CONFIG_BTCOEX
#ifdef CONFIG_PHL_CMD_BTC
static void _fail_hdlr(void *phl, struct phl_msg *msg)
{
}
static void _hdl_tmr(void *phl, struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
rtw_hal_btc_timer(phl_info->hal, (void *)msg->inbuf);
}
static void _hdl_role_notify(void *phl, struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_role_cmd *rcmd = NULL;
struct rtw_wifi_role_t *wrole = NULL;
struct rtw_phl_stainfo_t *sta = NULL;
if (msg->inbuf && (msg->inlen == sizeof(struct rtw_role_cmd))) {
rcmd = (struct rtw_role_cmd *)msg->inbuf;
wrole = rcmd->wrole;
sta = rtw_phl_get_stainfo_self(phl_info, wrole);
rtw_hal_btc_update_role_info_ntfy(phl_info->hal,
rcmd->wrole->id, wrole, sta, rcmd->rstate);
} else {
PHL_ERR("%s: invalid msg, buf = %p, len = %d\n",
__func__, msg->inbuf, msg->inlen);
}
}
static void _hdl_pkt_evt_notify(void *phl, struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct rtw_pkt_evt_ntfy *pkt_evt = NULL;
struct rtw_wifi_role_t *wrole = NULL;
if (msg->inbuf && (msg->inlen == sizeof(struct rtw_pkt_evt_ntfy))) {
pkt_evt = (struct rtw_pkt_evt_ntfy *)msg->inbuf;
wrole = pkt_evt->wrole; /* not used currently */
rtw_hal_btc_packet_event_ntfy(phl_info->hal,
(u8)pkt_evt->type);
} else {
PHL_ERR("%s: invalid msg, buf = %p, len = %d\n",
__func__, msg->inbuf, msg->inlen);
}
}
static enum phl_mdl_ret_code _btc_cmd_init(void *phl, void *dispr,
void **priv)
{
PHL_INFO("[BTCCMD], %s(): \n", __func__);
*priv = phl;
return MDL_RET_SUCCESS;
}
static void _btc_cmd_deinit(void *dispr, void *priv)
{
PHL_INFO("[BTCCMD], %s(): \n", __func__);
}
static enum phl_mdl_ret_code _btc_cmd_start(void *dispr, void *priv)
{
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
PHL_INFO("[BTCCMD], %s(): \n", __func__);
return ret;
}
static enum phl_mdl_ret_code _btc_cmd_stop(void *dispr, void *priv)
{
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
PHL_INFO("[BTCCMD], %s(): \n", __func__);
return ret;
}
static enum phl_mdl_ret_code
_btc_internal_pre_msg_hdlr(struct phl_info_t *phl_info,
void *dispr,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
/*PHL_INFO("[BTCCMD], msg->band_idx = %d, msg->msg_id = 0x%x\n",
msg->band_idx, msg->msg_id);*/
switch(evt_id) {
case MSG_EVT_BTC_REQ_BT_SLOT:
PHL_INFO("[BTCCMD], MSG_EVT_BTC_REQ_BT_SLOT \n");
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_BTC_PKT_EVT_NTFY:
PHL_INFO("[BTCCMD], MSG_EVT_BTC_PKT_EVT_NTFY \n");
_hdl_pkt_evt_notify(phl_info, msg);
ret = MDL_RET_SUCCESS;
break;
default:
break;
}
return ret;
}
static enum phl_mdl_ret_code
_btc_internal_post_msg_hdlr(struct phl_info_t *phl_info,
void *dispr,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
switch(evt_id) {
case MSG_EVT_BTC_TMR:
PHL_DBG("[BTCCMD], MSG_EVT_BTC_TMR \n");
_hdl_tmr(phl_info, msg);
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_BTC_FWEVNT:
PHL_DBG("[BTCCMD], MSG_EVT_BTC_FWEVNT \n");
rtw_hal_btc_fwinfo_ntfy(phl_info->hal);
ret = MDL_RET_SUCCESS;
break;
default:
break;
}
return ret;
}
static enum phl_mdl_ret_code
_btc_internal_msg_hdlr(struct phl_info_t *phl_info,
void *dispr,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
ret = _btc_internal_pre_msg_hdlr(phl_info, dispr, msg);
else
ret = _btc_internal_post_msg_hdlr(phl_info, dispr, msg);
return ret;
}
static enum phl_mdl_ret_code
_btc_external_pre_msg_hdlr(struct phl_info_t *phl_info,
void *dispr,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
enum band_type band = BAND_ON_5G;
struct rtw_hal_com_t *hal_com = rtw_hal_get_halcom(phl_info->hal);
enum phl_phy_idx phy_idx = HW_PHY_0;
/*PHL_INFO("[BTCCMD], msg->band_idx = %d, msg->msg_id = 0x%x\n",
msg->band_idx, msg->msg_id);*/
switch(evt_id) {
case MSG_EVT_SCAN_START:
if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_SCAN)
break;
if (msg->band_idx == HW_BAND_1)
phy_idx = HW_PHY_1;
PHL_INFO("[BTCCMD], MSG_EVT_SCAN_START \n");
band = hal_com->band[msg->band_idx].cur_chandef.band;
rtw_hal_btc_scan_start_ntfy(phl_info->hal, phy_idx, band);
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_CONNECT_START:
if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_CONNECT)
break;
PHL_INFO("[BTCCMD], MSG_EVT_CONNECT_START \n");
ret = MDL_RET_SUCCESS;
break;
default:
break;
}
return ret;
}
static enum phl_mdl_ret_code
_btc_external_post_msg_hdlr(struct phl_info_t *phl_info,
void *dispr,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
struct hal_info_t *hal_info = (struct hal_info_t *)phl_info->hal;
enum phl_phy_idx phy_idx = HW_PHY_0;
switch(evt_id) {
case MSG_EVT_SCAN_END:
if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_SCAN)
break;
if (msg->band_idx == HW_BAND_1)
phy_idx = HW_PHY_1;
PHL_DBG("[BTCCMD], MSG_EVT_SCAN_END \n");
rtw_hal_btc_scan_finish_ntfy(hal_info, phy_idx);
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_CONNECT_END:
if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_FG_MDL_CONNECT)
break;
PHL_DBG("[BTCCMD], MSG_EVT_CONNECT_END \n");
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_ROLE_NTFY:
if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_MDL_MRC)
break;
PHL_DBG("[BTCCMD], MSG_EVT_ROLE_NTFY \n");
_hdl_role_notify(phl_info, msg);
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_BTC_TMR:
PHL_DBG("[BTCCMD], MSG_EVT_BTC_TMR \n");
_hdl_tmr(phl_info, msg);
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_BTC_FWEVNT:
PHL_DBG("[BTCCMD], MSG_EVT_BTC_FWEVNT \n");
rtw_hal_btc_fwinfo_ntfy(phl_info->hal);
ret = MDL_RET_SUCCESS;
break;
default:
break;
}
return ret;
}
static enum phl_mdl_ret_code
_btc_external_msg_hdlr(struct phl_info_t *phl_info,
void *dispr,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
ret = _btc_external_pre_msg_hdlr(phl_info, dispr, msg);
else
ret = _btc_external_post_msg_hdlr(phl_info, dispr, msg);
return ret;
}
static enum phl_mdl_ret_code
_btc_msg_hdlr(void *dispr, void *priv, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
FUNCIN();
if (IS_MSG_FAIL(msg->msg_id)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"%s: cmd dispatcher notify cmd failure: 0x%x.\n",
__FUNCTION__, msg->msg_id);
_fail_hdlr(phl_info, msg);
FUNCOUT();
return MDL_RET_FAIL;
}
if (IS_PRIVATE_MSG(msg->msg_id)) {
FUNCOUT();
return ret;
}
switch(MSG_MDL_ID_FIELD(msg->msg_id)) {
case PHL_MDL_BTC:
ret = _btc_internal_msg_hdlr(phl_info, dispr, msg);
break;
default:
ret = _btc_external_msg_hdlr(phl_info, dispr, msg);
break;
}
FUNCOUT();
return ret;
}
static enum phl_mdl_ret_code
_btc_set_info(void *dispr, void *priv,
struct phl_module_op_info *info)
{
PHL_INFO("[BTCCMD], %s(): \n", __func__);
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code
_btc_query_info(void *dispr, void *priv,
struct phl_module_op_info *info)
{
PHL_INFO("[BTCCMD], %s(): \n", __func__);
return MDL_RET_SUCCESS;
}
enum rtw_phl_status phl_register_btc_module(struct phl_info_t *phl_info)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_bk_module_ops bk_ops = {0};
PHL_INFO("[BTCCMD], %s(): \n", __func__);
bk_ops.init = _btc_cmd_init;
bk_ops.deinit = _btc_cmd_deinit;
bk_ops.start = _btc_cmd_start;
bk_ops.stop = _btc_cmd_stop;
bk_ops.msg_hdlr = _btc_msg_hdlr;
bk_ops.set_info = _btc_set_info;
bk_ops.query_info = _btc_query_info;
phl_status = phl_disp_eng_register_module(phl_info, HW_BAND_0,
PHL_MDL_BTC, &bk_ops);
if (RTW_PHL_STATUS_SUCCESS != phl_status) {
PHL_ERR("Failed to register BTC module in cmd dispr of hw band 0\n");
}
return phl_status;
}
bool rtw_phl_btc_send_cmd(struct rtw_phl_com_t *phl_com,
u8 *buf, u32 len, u16 ev_id)
{
struct phl_info_t *phl_info = phl_com->phl_priv;
u8 band_idx = HW_BAND_0;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
msg.inbuf = buf;
msg.inlen = len;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_BTC);
msg.band_idx = band_idx;
switch (ev_id) {
case BTC_HMSG_TMR_EN:
SET_MSG_EVT_ID_FIELD(msg.msg_id,
MSG_EVT_BTC_TMR);
break;
case BTC_HMSG_SET_BT_REQ_SLOT:
SET_MSG_EVT_ID_FIELD(msg.msg_id,
MSG_EVT_BTC_REQ_BT_SLOT);
break;
case BTC_HMSG_FW_EV:
SET_MSG_EVT_ID_FIELD(msg.msg_id,
MSG_EVT_BTC_FWEVNT);
break;
default:
PHL_ERR("%s: Unknown msg !\n", __func__);
return false;
}
if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) !=
RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s: [BTC] dispr_send_msg failed !\n", __func__);
return false;
}
return true;
}
static void
_phl_pkt_evt_ntfy_done(void* priv, struct phl_msg* msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
if(msg->inbuf && msg->inlen){
_os_mem_free(phl_to_drvpriv(phl_info),
msg->inbuf, msg->inlen);
}
}
void rtw_phl_btc_packet_event_notify(void *phl, u8 role_id, u8 pkt_evt_type)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
struct rtw_pkt_evt_ntfy *pkt_evt = NULL;
pkt_evt = (struct rtw_pkt_evt_ntfy *)_os_mem_alloc(
phl_to_drvpriv(phl_info), sizeof(struct rtw_pkt_evt_ntfy));
if (pkt_evt == NULL) {
PHL_ERR("%s: alloc packet cmd fail.\n", __func__);
return;
}
pkt_evt->type = pkt_evt_type;
msg.inbuf = (u8 *)pkt_evt;
msg.inlen = sizeof(struct rtw_pkt_evt_ntfy);
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_BTC);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_BTC_PKT_EVT_NTFY);
msg.band_idx = HW_BAND_0;
attr.completion.completion = _phl_pkt_evt_ntfy_done;
attr.completion.priv = phl_info;
if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) !=
RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s: dispr_send_msg failed !\n", __func__);
goto cmd_fail;
}
return;
cmd_fail:
_os_mem_free(phl_to_drvpriv(phl_info), pkt_evt,
sizeof(struct rtw_pkt_evt_ntfy));
}
u8 rtw_phl_btc_pkt_2_evt_type(u8 packet_type)
{
u8 pkt_evt_type = BTC_PKT_EVT_MAX;
switch (packet_type) {
case PACKET_NORMAL:
pkt_evt_type = BTC_PKT_EVT_NORMAL;
break;
case PACKET_DHCP:
pkt_evt_type = BTC_PKT_EVT_DHCP;
break;
case PACKET_ARP:
pkt_evt_type = BTC_PKT_EVT_ARP;
break;
case PACKET_EAPOL:
pkt_evt_type = BTC_PKT_EVT_EAPOL;
break;
case PACKET_EAPOL_START:
pkt_evt_type = BTC_PKT_EVT_EAPOL_START;
break;
default:
PHL_ERR("%s packet type(%d) not support\n",
__func__, packet_type);
break;
}
return pkt_evt_type;
}
#endif /*CONFIG_PHL_CMD_BTC*/
#ifndef CONFIG_FSM
int rtw_phl_btc_notify(void *phl, enum RTW_PHL_BTC_NOTIFY notify,
struct rtw_phl_btc_ntfy *ntfy)
{
PHL_ERR("CMD_BTC not support :%s\n", __func__);
return 0;
}
void rtw_phl_btc_role_notify(void *phl, u8 role_id, enum role_state rstate)
{
struct rtw_phl_btc_ntfy ntfy = {0};
struct rtw_phl_btc_role_info_param *prinfo = &ntfy.u.rinfo;
prinfo->role_id = role_id;
prinfo->rstate = rstate;
ntfy.notify = PHL_BTC_NTFY_ROLE_INFO;
ntfy.ops = NULL;
ntfy.priv = NULL;
ntfy.ntfy_cb = NULL;
rtw_phl_btc_notify(phl, ntfy.notify, &ntfy);
}
void rtw_phl_btc_hub_msg_hdl(void *phl, struct phl_msg *msg)
{
}
#endif
#endif /*CONFIG_BTCOEX*/
|
2301_81045437/rtl8852be
|
phl/phl_cmd_btc.c
|
C
|
agpl-3.0
| 12,687
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_BTC_DISPATCH_H_
#define _PHL_BTC_DISPATCH_H_
enum rtw_phl_status phl_register_btc_module(struct phl_info_t *phl_info);
#endif /* _PHL_BTC_DISPATCH_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_btc.h
|
C
|
agpl-3.0
| 818
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHL_CMD_DISP_ENG_H_
#define __PHL_CMD_DISP_ENG_H_
#define SHARE_THREAD_MODE (0x1)
#define SOLO_THREAD_MODE (0x2)
/**
* phl_cmd_dispatch_engine,
* @phl_info: for general reference usage.
* @dispatcher: array of cmd dispatcher,
* each dispatch is design to address coexist issue for each PHY instance.
* @phy_num: current PHY instance number
* @token_mgnt_thread: token mgnt thread
* @token_chk: semaphore to wake up token mgnt thread
* @thread_mode: indicate current thread operation mode.
* SHARE_THREAD_MODE means all dispatcher share an background thread
* SOLO_THREAD_MODE means each disaptcher has a dedicated background thread
* @msg_q_sema: (opt) only used in SHARE_THREAD_MODE, used to wake up shared background thread
* @share_thread: (opt) only used in SHARE_THREAD_MODE, context of shared background thread
*/
struct phl_cmd_dispatch_engine {
struct phl_info_t *phl_info;
void **dispatcher; //an array of struct cmd_dispatcher
u8 phy_num;
u8 thread_mode;
_os_sema msg_q_sema;
_os_thread share_thread;
#ifdef CONFIG_CMD_DISP_SOLO_MODE
_os_sema dispr_ctrl_sema; /* keep msg from different dispr sequentially forward to ctrl*/
#endif
};
/* functions called in phl layer*/
enum rtw_phl_status phl_disp_eng_init(struct phl_info_t *phl, u8 phy_num);
enum rtw_phl_status phl_disp_eng_deinit(struct phl_info_t *phl);
enum rtw_phl_status phl_disp_eng_start(struct phl_info_t *phl);
enum rtw_phl_status phl_disp_eng_stop(struct phl_info_t *phl);
/* bk module would be initialized in phl_disp_eng_register_module call
* as for de-initialization, user can use phl_disp_eng_deregister_module as pair-wise operation
* or phl_disp_eng_deinit would deinit all bk modules per dispatcher
*/
enum rtw_phl_status phl_disp_eng_register_module(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_bk_module_ops *ops);
enum rtw_phl_status phl_disp_eng_deregister_module(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id);
enum rtw_phl_status phl_dispr_get_idx(void *dispr, u8 *idx);
u8 phl_disp_eng_is_dispr_busy(struct phl_info_t *phl, u8 band_idx);
u8 phl_disp_eng_is_fg_empty(struct phl_info_t *phl, u8 band_idx);
enum rtw_phl_status phl_disp_eng_set_cur_cmd_info(struct phl_info_t *phl, u8 band_idx,
struct phl_module_op_info *op_info);
enum rtw_phl_status phl_disp_eng_query_cur_cmd_info(struct phl_info_t *phl, u8 band_idx,
struct phl_module_op_info *op_info);
enum rtw_phl_status phl_disp_eng_set_bk_module_info(struct phl_info_t *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info *op_info);
enum rtw_phl_status phl_disp_eng_query_bk_module_info(struct phl_info_t *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info *op_info);
enum rtw_phl_status phl_disp_eng_set_src_info(struct phl_info_t *phl, struct phl_msg *msg,
struct phl_module_op_info *op_info);
enum rtw_phl_status phl_disp_eng_query_src_info(struct phl_info_t *phl, struct phl_msg *msg,
struct phl_module_op_info *op_info);
enum rtw_phl_status phl_disp_eng_send_msg(struct phl_info_t *phl, struct phl_msg *msg,
struct phl_msg_attribute *attr, u32 *msg_hdl);
enum rtw_phl_status phl_disp_eng_cancel_msg(struct phl_info_t *phl, u8 band_idx, u32 *msg_hdl);
enum rtw_phl_status phl_disp_eng_clr_pending_msg(struct phl_info_t *phl, u8 band_idx);
enum rtw_phl_status phl_disp_eng_add_token_req(struct phl_info_t *phl, u8 band_idx,
struct phl_cmd_token_req *req, u32 *req_hdl);
enum rtw_phl_status phl_disp_eng_cancel_token_req(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl);
enum rtw_phl_status phl_disp_eng_free_token(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl);
enum rtw_phl_status phl_disp_eng_notify_dev_io_status(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id mdl_id,
bool allow_io);
void phl_disp_eng_notify_shall_stop(struct phl_info_t *phl);
enum rtw_phl_status phl_disp_eng_set_msg_disp_seq(struct phl_info_t *phl,
struct phl_msg_attribute *attr,
struct msg_self_def_seq *seq);
u8 phl_disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl);
#ifdef CONFIG_CMD_DISP
/* following functions are only used inside phl_cmd_dispatch_eng.c */
enum rtw_phl_status dispr_init(struct phl_info_t *phl, void **dispr, u8 idx);
enum rtw_phl_status dispr_deinit(struct phl_info_t *phl, void *dispr);
enum rtw_phl_status dispr_start(void *dispr);
bool is_dispr_started(void *dispr);
enum rtw_phl_status dispr_stop(void *dispr);
enum rtw_phl_status dispr_register_module(void *dispr,
enum phl_module_id id,
struct phl_bk_module_ops *ops);
enum rtw_phl_status dispr_deregister_module(void *dispr,
enum phl_module_id id);
enum rtw_phl_status dispr_module_init(void *dispr);
enum rtw_phl_status dispr_module_deinit(void *dispr);
enum rtw_phl_status dispr_module_start(void *dispr);
enum rtw_phl_status dispr_module_stop(void *dispr);
enum rtw_phl_status dispr_get_cur_cmd_req(void *dispr, void **handle);
enum rtw_phl_status dispr_set_cur_cmd_info(void *dispr,
struct phl_module_op_info *op_info);
enum rtw_phl_status dispr_query_cur_cmd_info(void *dispr,
struct phl_module_op_info *op_info);
enum rtw_phl_status dispr_get_bk_module_handle(void *dispr,
enum phl_module_id id,
void **handle);
enum rtw_phl_status dispr_set_bk_module_info(void *dispr, void *handle,
struct phl_module_op_info *op_info);
enum rtw_phl_status dispr_query_bk_module_info(void *dispr, void *handle,
struct phl_module_op_info *op_info);
enum rtw_phl_status dispr_set_src_info(void *dispr, struct phl_msg *msg,
struct phl_module_op_info *op_info);
enum rtw_phl_status dispr_query_src_info(void *dispr, struct phl_msg *msg,
struct phl_module_op_info *op_info);
enum rtw_phl_status dispr_send_msg(void *dispr, struct phl_msg *msg,
struct phl_msg_attribute *attr, u32 *msg_hdl);
enum rtw_phl_status dispr_cancel_msg(void *dispr, u32 *msg_hdl);
enum rtw_phl_status dispr_clr_pending_msg(void *dispr);
enum rtw_phl_status dispr_add_token_req(void *dispr,
struct phl_cmd_token_req *req, u32 *req_hdl);
enum rtw_phl_status dispr_cancel_token_req(void *dispr, u32 *req_hdl);
enum rtw_phl_status dispr_free_token(void *dispr, u32 *req_hdl);
enum rtw_phl_status dispr_notify_dev_io_status(void *dispr, enum phl_module_id mdl_id, bool allow_io);
void dispr_notify_shall_stop(void *dispr);
u8 dispr_is_fg_empty(void *dispr);
void dispr_share_thread_loop_hdl(void *dispr);
void dispr_share_thread_leave_hdl(void *dispr);
void dispr_share_thread_stop_prior_hdl(void *dispr);
void dispr_share_thread_stop_post_hdl(void *dispr);
enum rtw_phl_status dispr_set_dispatch_seq(void *dispr, struct phl_msg_attribute *attr,
struct msg_self_def_seq* seq);
/*ollowing functions are called inside phl_cmd_dispatcher.c */
#define IS_DISPR_CTRL(_mdl_id) ((_mdl_id) < PHL_BK_MDL_ROLE_START)
#define disp_eng_is_solo_thread_mode(_phl) \
((_phl)->disp_eng.thread_mode == SOLO_THREAD_MODE)
void disp_eng_notify_share_thread(struct phl_info_t *phl, void *dispr);
void dispr_ctrl_hook_ops(void *dispr, struct phl_bk_module_ops *ops);
u8 disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl);
#ifdef CONFIG_CMD_DISP_SOLO_MODE
void dispr_ctrl_sema_down(struct phl_info_t *phl);
void dispr_ctrl_sema_up(struct phl_info_t *phl);
#endif
#endif
#endif /* __PHL_PHY_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_dispatch.h
|
C
|
agpl-3.0
| 8,216
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_PHY_MGNT_C_
#include "phl_headers.h"
#ifdef CONFIG_CMD_DISP
enum rtw_phl_status phl_disp_eng_bk_module_deinit(struct phl_info_t *phl);
enum rtw_phl_status _disp_eng_get_dispr_by_idx(struct phl_info_t *phl,
u8 band_idx,
void **dispr);
int share_thread_hdl(void *param)
{
struct phl_info_t *phl_info = (struct phl_info_t *)param;
void *d = phl_to_drvpriv(phl_info);
struct phl_cmd_dispatch_engine *disp_eng = &(phl_info->disp_eng);
u8 i = 0;
PHL_INFO("%s enter\n", __FUNCTION__);
while (!_os_thread_check_stop(d, &(disp_eng->share_thread))) {
_os_sema_down(d, &disp_eng->msg_q_sema);
/* A simple for-loop would guarantee
* all dispatcher split entire bandwidth of shared thread evenly,
* if adopting FIFO rule here,
* would lead to disproportionate distribution of thread bandwidth.
*/
for (i = 0 ; i < disp_eng->phy_num; i++) {
if(_os_thread_check_stop(d, &(disp_eng->share_thread)))
break;
dispr_share_thread_loop_hdl(disp_eng->dispatcher[i]);
}
}
for (i = 0 ; i < disp_eng->phy_num; i++)
dispr_share_thread_leave_hdl(disp_eng->dispatcher[i]);
_os_thread_wait_stop(d, &(disp_eng->share_thread));
PHL_INFO("%s down\n", __FUNCTION__);
return 0;
}
enum rtw_phl_status
phl_disp_eng_init(struct phl_info_t *phl, u8 phy_num)
{
u8 i = 0;
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
void *d = phl_to_drvpriv(phl);
enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS;
if (disp_eng->dispatcher != NULL) {
PHL_ERR("[PHY]: %s, not empty\n",__FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
disp_eng->phl_info = phl;
disp_eng->phy_num = phy_num;
#ifdef CONFIG_CMD_DISP_SOLO_MODE
disp_eng->thread_mode = SOLO_THREAD_MODE;
#else
disp_eng->thread_mode = SHARE_THREAD_MODE;
#endif
disp_eng->dispatcher = _os_mem_alloc(d, sizeof(void*) * phy_num);
#ifdef CONFIG_CMD_DISP_SOLO_MODE
_os_sema_init(d, &(disp_eng->dispr_ctrl_sema), 1);
#endif
if (disp_eng->dispatcher == NULL) {
disp_eng->phy_num = 0;
PHL_ERR("[PHY]: %s, alloc fail\n",__FUNCTION__);
return RTW_PHL_STATUS_RESOURCE;
}
for (i = 0 ; i < phy_num; i++) {
status = dispr_init(phl, &(disp_eng->dispatcher[i]), i);
if(status != RTW_PHL_STATUS_SUCCESS)
break;
}
if (status != RTW_PHL_STATUS_SUCCESS)
phl_disp_eng_deinit(phl);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
phl_disp_eng_deinit(struct phl_info_t *phl)
{
u8 i = 0;
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
void *d = phl_to_drvpriv(phl);
if (disp_eng->dispatcher == NULL)
return RTW_PHL_STATUS_FAILURE;
phl_disp_eng_bk_module_deinit(phl);
for (i = 0 ; i < disp_eng->phy_num; i++) {
if(disp_eng->dispatcher[i] == NULL)
continue;
dispr_deinit(phl, disp_eng->dispatcher[i]);
disp_eng->dispatcher[i] = NULL;
}
#ifdef CONFIG_CMD_DISP_SOLO_MODE
_os_sema_free(d, &(disp_eng->dispr_ctrl_sema));
#endif
if (disp_eng->phy_num) {
_os_mem_free(d, disp_eng->dispatcher,
sizeof(void *) * (disp_eng->phy_num));
disp_eng->dispatcher = NULL;
disp_eng->phy_num = 0;
}
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
phl_disp_eng_bk_module_deinit(struct phl_info_t *phl)
{
u8 i = 0;
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
for (i = 0 ; i < disp_eng->phy_num; i++) {
if(disp_eng->dispatcher[i] == NULL)
continue;
dispr_module_deinit(disp_eng->dispatcher[i]);
}
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
phl_disp_eng_start(struct phl_info_t *phl)
{
u8 i = 0;
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
void *d = phl_to_drvpriv(phl);
_os_sema_init(d, &(disp_eng->msg_q_sema), 0);
if (!disp_eng_is_solo_thread_mode(phl)) {
_os_thread_init(d, &(disp_eng->share_thread), share_thread_hdl, phl,
"disp_eng_share_thread");
_os_thread_schedule(d, &(disp_eng->share_thread));
}
for (i = 0 ; i < disp_eng->phy_num; i++){
if(disp_eng->dispatcher[i] == NULL)
continue;
dispr_start(disp_eng->dispatcher[i]);
dispr_module_start(disp_eng->dispatcher[i]);
}
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
phl_disp_eng_stop(struct phl_info_t *phl)
{
u8 i = 0;
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
void *d = phl_to_drvpriv(phl);
u8 solo_mode = (disp_eng_is_solo_thread_mode(phl)) ? (true) : (false);
if (disp_eng->dispatcher == NULL) {
PHL_ERR("[PHY]: %s, abnomarl state\n",__FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
for (i = 0 ; i < disp_eng->phy_num; i++) {
if(disp_eng->dispatcher[i] == NULL)
continue;
dispr_module_stop(disp_eng->dispatcher[i]);
if (solo_mode == true)
dispr_stop(disp_eng->dispatcher[i]);
else
dispr_share_thread_stop_prior_hdl(disp_eng->dispatcher[i]);
}
if (solo_mode == false) {
_os_thread_stop(d, &(disp_eng->share_thread));
_os_sema_up(d, &(disp_eng->msg_q_sema));
_os_thread_deinit(d, &(disp_eng->share_thread));
for (i = 0 ; i < disp_eng->phy_num; i++)
dispr_share_thread_stop_post_hdl(disp_eng->dispatcher[i]);
}
_os_sema_free(d, &(disp_eng->msg_q_sema));
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
rtw_phl_register_module(void *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_bk_module_ops *ops)
{
return phl_disp_eng_register_module((struct phl_info_t *)phl,
band_idx, id, ops);
}
enum rtw_phl_status
rtw_phl_deregister_module(void *phl,u8 band_idx, enum phl_module_id id)
{
return phl_disp_eng_deregister_module((struct phl_info_t *)phl,
band_idx,
id);
}
u8 rtw_phl_is_fg_empty(void *phl,u8 band_idx)
{
return phl_disp_eng_is_fg_empty((struct phl_info_t *)phl, band_idx);
}
enum rtw_phl_status
rtw_phl_send_msg_to_dispr(void *phl,
struct phl_msg *msg,
struct phl_msg_attribute *attr,
u32 *msg_hdl)
{
return phl_disp_eng_send_msg(phl, msg, attr, msg_hdl);
}
enum rtw_phl_status
rtw_phl_cancel_dispr_msg(void *phl, u8 band_idx, u32 *msg_hdl)
{
return phl_disp_eng_cancel_msg(phl, band_idx, msg_hdl);
}
enum rtw_phl_status
rtw_phl_add_cmd_token_req(void *phl,
u8 band_idx,
struct phl_cmd_token_req *req,
u32 *req_hdl)
{
return phl_disp_eng_add_token_req(phl, band_idx, req, req_hdl);
}
enum rtw_phl_status
rtw_phl_cancel_cmd_token(void *phl, u8 band_idx, u32 *req_hdl)
{
return phl_disp_eng_cancel_token_req(phl, band_idx, req_hdl);
}
enum rtw_phl_status
rtw_phl_free_cmd_token(void *phl, u8 band_idx, u32 *req_hdl)
{
return phl_disp_eng_free_token(phl, band_idx, req_hdl);
}
enum rtw_phl_status
rtw_phl_set_cur_cmd_info(void *phl,
u8 band_idx,
struct phl_module_op_info* op_info)
{
return phl_disp_eng_set_cur_cmd_info(phl, band_idx, op_info);
}
enum rtw_phl_status
rtw_phl_query_cur_cmd_info(void *phl,
u8 band_idx,
struct phl_module_op_info* op_info)
{
return phl_disp_eng_query_cur_cmd_info(phl, band_idx, op_info);
}
enum rtw_phl_status
rtw_phl_set_bk_module_info(void *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_module_op_info *op_info)
{
return phl_disp_eng_set_bk_module_info(phl, band_idx, id, op_info);
}
enum rtw_phl_status
rtw_phl_query_bk_module_info(void *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_module_op_info *op_info)
{
return phl_disp_eng_query_bk_module_info(phl, band_idx, id, op_info);
}
enum rtw_phl_status
rtw_phl_set_msg_disp_seq(void *phl,
struct phl_msg_attribute *attr,
struct msg_self_def_seq* seq)
{
return phl_disp_eng_set_msg_disp_seq(phl, attr, seq);
}
enum rtw_phl_status
_disp_eng_get_dispr_by_idx(struct phl_info_t *phl, u8 band_idx, void **dispr)
{
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
if (band_idx > (disp_eng->phy_num - 1) || (dispr == NULL)) {
PHL_WARN("%s invalid input :%d\n", __func__, band_idx);
return RTW_PHL_STATUS_INVALID_PARAM;
}
(*dispr) = disp_eng->dispatcher[band_idx];
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
phl_disp_eng_register_module(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_bk_module_ops *ops)
{
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
u8 idx = band_idx;
if ((band_idx + 1) > disp_eng->phy_num) {
PHL_WARN("%s invalid input :%d\n", __func__, band_idx);
return RTW_PHL_STATUS_INVALID_PARAM;
}
return dispr_register_module(disp_eng->dispatcher[idx], id, ops);
}
enum rtw_phl_status
phl_disp_eng_deregister_module(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id)
{
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
u8 idx = band_idx;
if ((band_idx + 1) > disp_eng->phy_num) {
PHL_WARN("%s invalid input :%d\n", __func__, band_idx);
return RTW_PHL_STATUS_INVALID_PARAM;
}
return dispr_deregister_module(disp_eng->dispatcher[idx], id);
}
void disp_eng_notify_share_thread(struct phl_info_t *phl, void *dispr)
{
void *d = phl_to_drvpriv(phl);
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
_os_sema_up(d, &(disp_eng->msg_q_sema));
}
u8 phl_disp_eng_is_dispr_busy(struct phl_info_t *phl, u8 band_idx)
{
void* dispr = NULL;
void *handle = NULL;
if (_disp_eng_get_dispr_by_idx(phl, band_idx, &dispr) != RTW_PHL_STATUS_SUCCESS)
return false;
if (dispr_get_cur_cmd_req(dispr, &handle) == RTW_PHL_STATUS_SUCCESS)
return true;
else
return false;
}
enum rtw_phl_status
phl_disp_eng_set_cur_cmd_info(struct phl_info_t *phl,
u8 band_idx,
struct phl_module_op_info *op_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_set_cur_cmd_info(dispr, op_info);
}
enum rtw_phl_status
phl_disp_eng_query_cur_cmd_info(struct phl_info_t *phl,
u8 band_idx,
struct phl_module_op_info *op_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_query_cur_cmd_info(dispr, op_info);
}
enum rtw_phl_status
phl_disp_eng_set_bk_module_info(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_module_op_info *op_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
void* handle = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
status = dispr_get_bk_module_handle(dispr, id, &handle);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_set_bk_module_info(dispr, handle, op_info);
}
enum rtw_phl_status
phl_disp_eng_query_bk_module_info(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_module_op_info *op_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
void* handle = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
status = dispr_get_bk_module_handle(dispr, id, &handle);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_query_bk_module_info(dispr, handle, op_info);
}
enum rtw_phl_status
phl_disp_eng_set_src_info(struct phl_info_t *phl,
struct phl_msg *msg,
struct phl_module_op_info *op_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, msg->band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_set_src_info(dispr, msg, op_info);
}
enum rtw_phl_status
phl_disp_eng_query_src_info(struct phl_info_t *phl,
struct phl_msg *msg,
struct phl_module_op_info *op_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, msg->band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_query_src_info(dispr, msg, op_info);
}
enum rtw_phl_status
phl_disp_eng_send_msg(struct phl_info_t *phl,
struct phl_msg *msg,
struct phl_msg_attribute *attr,
u32 *msg_hdl)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, msg->band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_send_msg(dispr, msg, attr, msg_hdl);
}
enum rtw_phl_status
phl_disp_eng_cancel_msg(struct phl_info_t *phl, u8 band_idx, u32 *msg_hdl)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_cancel_msg(dispr, msg_hdl);
}
enum rtw_phl_status
phl_disp_eng_clr_pending_msg(struct phl_info_t *phl, u8 band_idx)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_clr_pending_msg(dispr);
}
enum rtw_phl_status
phl_disp_eng_add_token_req(struct phl_info_t *phl,
u8 band_idx,
struct phl_cmd_token_req *req,
u32 *req_hdl)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_add_token_req(dispr, req, req_hdl);
}
enum rtw_phl_status
phl_disp_eng_cancel_token_req(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_cancel_token_req(dispr, req_hdl);
}
enum rtw_phl_status
phl_disp_eng_free_token(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, band_idx, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_free_token(dispr, req_hdl);
}
enum rtw_phl_status
phl_disp_eng_notify_dev_io_status(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id mdl_id,
bool allow_io)
{
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
u8 i = 0;
band_idx = HW_BAND_MAX; /* force all band stop IO */
if (band_idx != HW_BAND_MAX)
return dispr_notify_dev_io_status(disp_eng->dispatcher[band_idx], mdl_id, allow_io);
for (i = 0; i < disp_eng->phy_num; i++)
dispr_notify_dev_io_status(disp_eng->dispatcher[i], mdl_id, allow_io);
return RTW_PHL_STATUS_SUCCESS;
}
void phl_disp_eng_notify_shall_stop(struct phl_info_t *phl)
{
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
u8 i = 0;
for (i = 0; i < disp_eng->phy_num; i++) {
if (is_dispr_started(disp_eng->dispatcher[i]))
dispr_notify_shall_stop(disp_eng->dispatcher[i]);
}
}
u8 phl_disp_eng_is_fg_empty(struct phl_info_t *phl, u8 band_idx)
{
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
u8 i = 0;
if (band_idx != HW_BAND_MAX)
return dispr_is_fg_empty(disp_eng->dispatcher[band_idx]);
for (i = 0; i < disp_eng->phy_num; i++)
if (false == dispr_is_fg_empty(disp_eng->dispatcher[i]))
return false;
return true;
}
#ifdef CONFIG_CMD_DISP_SOLO_MODE
void dispr_ctrl_sema_down(struct phl_info_t *phl_info)
{
_os_sema_down(phl_to_drvpriv(phl_info),
&(phl_info->disp_eng.dispr_ctrl_sema));
}
void dispr_ctrl_sema_up(struct phl_info_t *phl_info)
{
_os_sema_up(phl_to_drvpriv(phl_info),
&(phl_info->disp_eng.dispr_ctrl_sema));
}
#endif
enum rtw_phl_status
phl_disp_eng_set_msg_disp_seq(struct phl_info_t *phl,
struct phl_msg_attribute *attr,
struct msg_self_def_seq *seq)
{
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
struct phl_cmd_dispatch_engine *disp_eng = &(phl->disp_eng);
void* dispr = NULL;
status = _disp_eng_get_dispr_by_idx(phl, HW_BAND_0, &dispr);
if (RTW_PHL_STATUS_SUCCESS != status)
return status;
return dispr_set_dispatch_seq(dispr, attr, seq);
#else
return RTW_PHL_STATUS_FAILURE;
#endif
}
u8 phl_disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl)
{
return disp_query_mdl_id(phl, bk_mdl);
}
#else
enum rtw_phl_status rtw_phl_set_bk_module_info(void *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status rtw_phl_query_bk_module_info(void *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status phl_disp_eng_init(struct phl_info_t *phl, u8 phy_num)
{
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status phl_disp_eng_deinit(struct phl_info_t *phl)
{
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status phl_disp_eng_start(struct phl_info_t *phl)
{
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status phl_disp_eng_stop(struct phl_info_t *phl)
{
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status phl_disp_eng_register_module(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id,
struct phl_bk_module_ops *ops)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_deregister_module(struct phl_info_t *phl,
u8 band_idx,
enum phl_module_id id)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_dispr_get_idx(void *dispr, u8 *idx)
{
return RTW_PHL_STATUS_FAILURE;
}
u8 phl_disp_eng_is_dispr_busy(struct phl_info_t *phl, u8 band_idx)
{
return true;
}
enum rtw_phl_status phl_disp_eng_set_cur_cmd_info(struct phl_info_t *phl, u8 band_idx,
struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_query_cur_cmd_info(struct phl_info_t *phl, u8 band_idx,
struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_set_bk_module_info(struct phl_info_t *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_query_bk_module_info(struct phl_info_t *phl, u8 band_idx,
enum phl_module_id id, struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_set_src_info(struct phl_info_t *phl, struct phl_msg *msg,
struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_query_src_info(struct phl_info_t *phl, struct phl_msg *msg,
struct phl_module_op_info *op_info)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_send_msg(struct phl_info_t *phl, struct phl_msg *msg,
struct phl_msg_attribute *attr, u32 *msg_hdl)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_cancel_msg(struct phl_info_t *phl, u8 band_idx, u32 *msg_hdl)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_clr_pending_msg(struct phl_info_t *phl, u8 band_idx)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_add_token_req(struct phl_info_t *phl, u8 band_idx,
struct phl_cmd_token_req *req, u32 *req_hdl)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_cancel_token_req(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_free_token(struct phl_info_t *phl, u8 band_idx, u32 *req_hdl)
{
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status phl_disp_eng_notify_dev_io_status(struct phl_info_t *phl, u8 band_idx,
enum phl_module_id mdl_id, bool allow_io)
{
return RTW_PHL_STATUS_FAILURE;
}
}
void
phl_disp_eng_notify_shall_stop(struct phl_info_t *phl)
{
}
enum rtw_phl_status rtw_phl_set_msg_disp_seq(void *phl,
struct phl_msg_attribute *attr,
struct msg_self_def_seq* seq)
{
return RTW_PHL_STATUS_FAILURE;
}
u8 phl_disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl)
{
return PHL_MDL_ID_MAX;
}
#endif
|
2301_81045437/rtl8852be
|
phl/phl_cmd_dispatch_engine.c
|
C
|
agpl-3.0
| 21,978
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CMD_DISPR_C_
#include "phl_headers.h"
#ifdef CONFIG_CMD_DISP
#define MAX_PHL_MSG_NUM (24)
#define MAX_CMD_REQ_NUM (8)
#define MODL_MASK_LEN (PHL_BK_MDL_END/8)
#define GEN_VALID_HDL(_idx) ((u32)(BIT31 | (u32)(_idx)))
#define IS_HDL_VALID(_hdl) ((_hdl) & BIT31)
#define GET_IDX_FROM_HDL(_hdl) ((u8)((_hdl) & 0xFF))
#define GET_CUR_PENDING_EVT( _obj, _mdl_id) \
((u16)((_obj)->mdl_info[(_mdl_id)].pending_evt_id))
#define SET_CUR_PENDING_EVT( _obj, _mdl_id, _evt_id) \
((_obj)->mdl_info[(_mdl_id)].pending_evt_id = (_evt_id))
#define IS_EXCL_MDL(_obj, _mdl) ((_obj)->exclusive_mdl == (_mdl))
#define SET_EXCL_MDL(_obj, _mdl) ((_obj)->exclusive_mdl = (_mdl))
#define CLEAR_EXCL_MDL(_obj) ((_obj)->exclusive_mdl = PHL_MDL_ID_MAX)
#define STOP_DISPATCH_MSG(_ret) \
((_ret) != MDL_RET_SUCCESS && (_ret) != MDL_RET_IGNORE)
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
#define SET_MDL_HANDLE( _obj, _mdl_id, _handle) \
((_obj)->mdl_info[(_mdl_id)].handle = (void*)(_handle))
#define GET_MDL_HANDLE( _obj, _mdl_id) \
((_obj)->mdl_info[(_mdl_id)].handle)
#endif
enum phl_msg_status {
MSG_STATUS_ENQ = BIT0,
MSG_STATUS_RUN = BIT1,
MSG_STATUS_NOTIFY_COMPLETE = BIT2,
MSG_STATUS_CANCEL = BIT3,
MSG_STATUS_PRE_PHASE = BIT4,
MSG_STATUS_FAIL = BIT5,
MSG_STATUS_OWNER_BK_MDL = BIT6,
MSG_STATUS_OWNER_REQ = BIT7,
MSG_STATUS_CLR_SNDR_MSG_IF_PENDING = BIT8,
MSG_STATUS_PENDING = BIT9,
MSG_STATUS_FOR_ABORT = BIT10,
MSG_STATUS_PENDING_DURING_CANNOT_IO = BIT11,
};
enum cmd_req_status {
REQ_STATUS_ENQ = BIT0,
REQ_STATUS_RUN = BIT1,
REQ_STATUS_CANCEL = BIT2,
REQ_STATUS_LAST_PERMIT = BIT3,
REQ_STATUS_PREPARE = BIT4,
};
enum phl_mdl_status {
MDL_INIT = BIT0,
MDL_STARTED = BIT1,
};
enum dispatcher_status {
DISPR_INIT = BIT0,
DISPR_STARTED = BIT1,
DISPR_SHALL_STOP = BIT2,
DISPR_MSGQ_INIT = BIT3,
DISPR_REQ_INIT = BIT4,
DISPR_NOTIFY_IDLE = BIT5,
DISPR_CLR_PEND_MSG = BIT6,
DISPR_CTRL_PRESENT = BIT7,
DISPR_WAIT_ABORT_MSG_DONE = BIT8,
DISPR_CANNOT_IO = BIT9,
};
enum token_op_type {
TOKEN_OP_ADD_CMD_REQ = 1,
TOKEN_OP_FREE_CMD_REQ = 2,
TOKEN_OP_CANCEL_CMD_REQ = 3,
TOKEN_OP_RENEW_CMD_REQ = 4,
};
/**
* phl_bk_module - instance of phl background module,
* @status: contain mgnt status flags, refer to enum phl_mdl_status
* @id: refer to enum phl_module_id
* @priv: private context
* @ops: interface to interacting with phl_module
*/
struct phl_bk_module {
_os_list list;
u8 status;
u8 id;
void *priv;
struct phl_bk_module_ops ops;
};
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
struct dispr_msg_attr {
struct msg_self_def_seq self_def_seq;
};
#endif
/**
* phl_dispr_msg_ex - phl msg extension,
* @status: contain mgnt status flags, refer to enum phl_msg_status
* @idx: idx in original msg_ex pool
* @msg: msg content from external module
* @premap: notifty map in pre-role phase, refer to enum phl_module_id
* @postmap: notifty map in post-role phase, refer to enum phl_module_id
* @completion: msg completion routine.
* @priv: private context to completion routine.
* @module: module handle of msg source, only used when msg fails
*/
struct phl_dispr_msg_ex {
_os_list list;
u16 status;
u8 idx;
struct phl_msg msg;
u8 premap[MODL_MASK_LEN];
u8 postmap[MODL_MASK_LEN];
struct msg_completion_routine completion;
struct phl_bk_module *module; /* module handle which assign in msg_id*/
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
struct dispr_msg_attr *attr;
#endif
};
/**
* phl_token_op_info - for internal mgnt purpose,
* @info: mgnt data
*/
struct phl_token_op_info {
_os_list list;
u8 used;
enum token_op_type type;
u8 data;
};
/**
* phl_cmd_token_req_ex - cmd token request extension,
* @status: contain mgnt status flags, refer to enum cmd_req_status
* @idx: idx in original req_ex pool
* @req: req content from external module.
*/
struct phl_cmd_token_req_ex {
_os_list list;
u8 idx;
u8 status;
struct phl_cmd_token_req req;
struct phl_token_op_info add_req_info;
struct phl_token_op_info free_req_info;
};
struct mdl_mgnt_info {
u16 pending_evt_id;
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
void* handle;
#endif
};
/**
* cmd_dispatcher,
* @idx: idx in dispatch engine, corresponding to band idx
* @status: contain mgnt status flags, refer to enum dispatcher_status
* @phl_info: for general reference usage.
* @module_q: module queue that link each modules based on priority
* @msg_ex_pool: msg extension pool
* @bk_thread: background thread
* @token_req_ex_pool: req extension pool
* @token_cnt: current token count,
* cmd req can be executed when dispatcher's token count is 0
* @bitmap: cosist of existing background modules loaded in current dispatcher,
* refer to enum phl_module_id
* @basemap: BK modules that must be notified when handling msg
* @controller: instance of dispr controller module
* @renew_req_info: used to trigger next token req registration
* @exclusive_mdl: In certain conditions, like dev IO status change,
* dispr would only allow designated module to send msg and cancel the rest,
*/
struct cmd_dispatcher {
u8 idx;
u16 status;
struct phl_info_t *phl_info;
struct phl_queue module_q[PHL_MDL_PRI_MAX];
struct phl_dispr_msg_ex msg_ex_pool[MAX_PHL_MSG_NUM];
_os_sema msg_q_sema; /* wake up background thread in SOLO_THREAD_MODE*/
struct phl_queue msg_wait_q;
struct phl_queue msg_idle_q;
struct phl_queue msg_pend_q;
_os_thread bk_thread;
struct phl_cmd_token_req_ex token_req_ex_pool[MAX_CMD_REQ_NUM];
struct phl_queue token_req_wait_q;
struct phl_queue token_req_idle_q;
struct phl_queue token_op_q;
_os_lock token_op_q_lock;
_os_atomic token_cnt; // atomic
struct phl_cmd_token_req_ex *cur_cmd_req;
u8 bitmap[MODL_MASK_LEN];
u8 basemap[MODL_MASK_LEN];
struct mdl_mgnt_info mdl_info[PHL_MDL_ID_MAX];
struct phl_bk_module controller;
struct phl_token_op_info renew_req_info;
u8 exclusive_mdl;
};
enum rtw_phl_status dispr_process_token_req(struct cmd_dispatcher *obj);
void send_bk_msg_phy_on(struct cmd_dispatcher *obj);
void send_bk_msg_phy_idle(struct cmd_dispatcher *obj);
enum rtw_phl_status send_dev_io_status_change(struct cmd_dispatcher *obj, u8 allow_io);
void _notify_dispr_controller(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex);
static u8 dispr_enqueue_token_op_info(struct cmd_dispatcher *obj, struct phl_token_op_info *op_info,
enum token_op_type type, u8 data);
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
static void free_dispr_attr(void *d, struct dispr_msg_attr **dispr_attr);
static enum phl_mdl_ret_code run_self_def_seq(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex,
enum phl_bk_module_priority priority, u8 pre_prot_phase);
#endif
inline static
enum phl_bk_module_priority _get_mdl_priority(enum phl_module_id id)
{
if (id < PHL_BK_MDL_ROLE_START)
return PHL_MDL_PRI_MAX;
else if (id <= PHL_BK_MDL_ROLE_END)
return PHL_MDL_PRI_ROLE;
else if ( id <= PHL_BK_MDL_MDRY_END)
return PHL_MDL_PRI_MANDATORY;
else if (id <= PHL_BK_MDL_OPT_END)
return PHL_MDL_PRI_OPTIONAL;
else
return PHL_MDL_PRI_MAX;
}
inline static u8 _is_bitmap_empty(void *d, u8 *bitmap)
{
u8 empty[MODL_MASK_LEN] = {0};
return (!_os_mem_cmp(d, bitmap, empty, MODL_MASK_LEN))?(true):(false);
}
inline static void _print_bitmap(u8 *bitmap)
{
u8 k = 0;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "print bitmap: \n");
for (k = 0; k < MODL_MASK_LEN; k++) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_,"[%d]:0x%x\n", k, bitmap[k]);
}
}
static void notify_bk_thread(struct cmd_dispatcher *obj)
{
void *d = phl_to_drvpriv(obj->phl_info);
if (disp_eng_is_solo_thread_mode(obj->phl_info))
_os_sema_up(d, &(obj->msg_q_sema));
else
disp_eng_notify_share_thread(obj->phl_info, (void*)obj);
}
static void on_abort_msg_complete(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
/* since struct phl_token_op_info is used to synchronously handle token req in background thread
* here use add_req_info to notify background thread to run dispr_process_token_req again before handling next msg
*/
CLEAR_STATUS_FLAG(obj->status, DISPR_WAIT_ABORT_MSG_DONE);
dispr_enqueue_token_op_info(obj, &obj->renew_req_info, TOKEN_OP_RENEW_CMD_REQ, 0xff);
}
static u8 pop_front_idle_msg(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex **msg)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *new_msg = NULL;
(*msg) = NULL;
if (pq_pop(d, &(obj->msg_idle_q), &new_msg, _first, _bh)) {
(*msg) = (struct phl_dispr_msg_ex *)new_msg;
(*msg)->status = 0;
(*msg)->module = NULL;
(*msg)->completion.priv = NULL;
(*msg)->completion.completion = NULL;
_os_mem_set(d, (*msg)->premap, 0, MODL_MASK_LEN);
_os_mem_set(d, (*msg)->postmap, 0, MODL_MASK_LEN);
_os_mem_set(d, &((*msg)->msg), 0, sizeof(struct phl_msg));
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
(*msg)->attr = NULL;
#endif
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s: remain cnt(%d)\n", __FUNCTION__, obj->msg_idle_q.cnt);
return true;
} else {
return false;
}
}
static void push_back_idle_msg(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex *ex)
{
void *d = phl_to_drvpriv(obj->phl_info);
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_NOTIFY_COMPLETE) &&
ex->completion.completion) {
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL))
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANCEL);
ex->completion.completion(ex->completion.priv, &(ex->msg));
CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_NOTIFY_COMPLETE);
}
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_FOR_ABORT))
on_abort_msg_complete(obj, ex);
ex->status = 0;
if(GET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id)) == MSG_EVT_ID_FIELD(ex->msg.msg_id))
SET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id), MSG_EVT_MAX);
ex->msg.msg_id = 0;
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
free_dispr_attr(d, &(ex->attr));
#endif
pq_push(d, &(obj->msg_idle_q), &(ex->list), _tail, _bh);
}
static u8 pop_front_wait_msg(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex **msg)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *new_msg = NULL;
(*msg) = NULL;
if (pq_pop(d, &(obj->msg_wait_q), &new_msg, _first, _bh)) {
(*msg) = (struct phl_dispr_msg_ex *)new_msg;
SET_STATUS_FLAG((*msg)->status, MSG_STATUS_RUN);
CLEAR_STATUS_FLAG((*msg)->status, MSG_STATUS_ENQ);
CLEAR_STATUS_FLAG((*msg)->status, MSG_STATUS_PENDING);
return true;
} else {
return false;
}
}
static void push_back_wait_msg(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex *ex)
{
void *d = phl_to_drvpriv(obj->phl_info);
SET_STATUS_FLAG(ex->status, MSG_STATUS_ENQ);
CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_RUN);
pq_push(d, &(obj->msg_wait_q), &(ex->list), _tail, _bh);
notify_bk_thread(obj);
}
u8 is_higher_priority(void *d, void *priv,_os_list *input, _os_list *obj)
{
struct phl_dispr_msg_ex *ex_input = (struct phl_dispr_msg_ex *)input;
struct phl_dispr_msg_ex *ex_obj = (struct phl_dispr_msg_ex *)obj;
if (IS_DISPR_CTRL(MSG_MDL_ID_FIELD(ex_input->msg.msg_id)) &&
!IS_DISPR_CTRL(MSG_MDL_ID_FIELD(ex_obj->msg.msg_id)))
return true;
return false;
}
static void insert_msg_by_priority(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex *ex)
{
void *d = phl_to_drvpriv(obj->phl_info);
SET_STATUS_FLAG(ex->status, MSG_STATUS_ENQ);
CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_RUN);
pq_insert(d, &(obj->msg_wait_q), _bh, NULL, &(ex->list), is_higher_priority);
notify_bk_thread(obj);
}
static u8 pop_front_pending_msg(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex **msg)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *new_msg = NULL;
(*msg) = NULL;
if (pq_pop(d, &(obj->msg_pend_q), &new_msg, _first, _bh)) {
(*msg) = (struct phl_dispr_msg_ex *)new_msg;
return true;
} else {
return false;
}
}
static void push_back_pending_msg(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex *ex)
{
void *d = phl_to_drvpriv(obj->phl_info);
SET_STATUS_FLAG(ex->status, MSG_STATUS_ENQ);
CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_RUN);
if(TEST_STATUS_FLAG(ex->status, MSG_STATUS_CLR_SNDR_MSG_IF_PENDING))
SET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id), MSG_EVT_ID_FIELD(ex->msg.msg_id));
pq_push(d, &(obj->msg_pend_q), &(ex->list), _tail, _bh);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s: remain cnt(%d)\n", __FUNCTION__, obj->msg_pend_q.cnt);
}
static void clear_pending_msg(struct cmd_dispatcher *obj)
{
struct phl_dispr_msg_ex *ex = NULL;
if(!TEST_STATUS_FLAG(obj->status, DISPR_CLR_PEND_MSG))
return;
CLEAR_STATUS_FLAG(obj->status, DISPR_CLR_PEND_MSG);
while (pop_front_pending_msg(obj, &ex)) {
if (IS_DISPR_CTRL(MSG_EVT_ID_FIELD(ex->msg.msg_id)))
insert_msg_by_priority(obj, ex);
else
push_back_wait_msg(obj, ex);
}
}
static void clear_waiting_msg(struct cmd_dispatcher *obj)
{
struct phl_dispr_msg_ex *ex = NULL;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s: remain cnt(%d)\n", __FUNCTION__, obj->msg_idle_q.cnt);
while(obj->msg_idle_q.cnt != MAX_PHL_MSG_NUM) {
while (pop_front_pending_msg(obj, &ex))
push_back_wait_msg(obj, ex);
while (pop_front_wait_msg(obj, &ex))
push_back_idle_msg(obj, ex);
}
}
static bool is_special_msg(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
u8 mdl_id = MSG_MDL_ID_FIELD(ex->msg.msg_id);
u16 evt = MSG_EVT_ID_FIELD(ex->msg.msg_id);
if (TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) {
if ( IS_EXCL_MDL(obj, mdl_id) ||
evt == MSG_EVT_DEV_CANNOT_IO ||
evt == MSG_EVT_DEV_RESUME_IO ||
evt == MSG_EVT_PHY_ON ||
evt == MSG_EVT_PHY_IDLE)
return true;
}
return false;
}
static bool is_msg_canceled(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
u16 pending_evt = GET_CUR_PENDING_EVT(obj, MSG_MDL_ID_FIELD(ex->msg.msg_id));
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) ||
TEST_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL))
return true;
if (pending_evt != MSG_EVT_MAX && pending_evt != MSG_EVT_ID_FIELD(ex->msg.msg_id)) {
SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg canceled, cur pending evt(%d)\n", pending_evt);
return true;
}
if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg canceled due to SHALL STOP status\n");
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO);
SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL);
return true;
}
if (TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) {
if( is_special_msg(obj, ex)) {
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "special msg found, still sent with CANNOT IO flag set\n");
}
else if (!TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING_DURING_CANNOT_IO)) {
SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL);
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg canceled due to CANNOT IO status\n");
return true;
} else {
SET_STATUS_FLAG(ex->status, MSG_STATUS_PENDING);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "msg pending due to CANNOT IO status\n");
}
}
return false;
}
void init_dispr_msg_pool(struct cmd_dispatcher *obj)
{
u8 i = 0;
void *d = phl_to_drvpriv(obj->phl_info);
if (TEST_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT))
return;
pq_init(d, &(obj->msg_idle_q));
pq_init(d, &(obj->msg_wait_q));
pq_init(d, &(obj->msg_pend_q));
_os_mem_set(d, obj->msg_ex_pool, 0,
sizeof(struct phl_dispr_msg_ex) * MAX_PHL_MSG_NUM);
for (i = 0; i < MAX_PHL_MSG_NUM; i++) {
obj->msg_ex_pool[i].idx = i;
push_back_idle_msg(obj, &(obj->msg_ex_pool[i]));
}
SET_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT);
}
void deinit_dispr_msg_pool(struct cmd_dispatcher *obj)
{
void *d = phl_to_drvpriv(obj->phl_info);
if (!TEST_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT))
return;
CLEAR_STATUS_FLAG(obj->status, DISPR_MSGQ_INIT);
pq_deinit(d, &(obj->msg_idle_q));
pq_deinit(d, &(obj->msg_wait_q));
pq_deinit(d, &(obj->msg_pend_q));
}
void cancel_msg(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
void *d = phl_to_drvpriv(obj->phl_info);
/* zero bitmap to ensure msg would not be forward to
* any modules after cancel.
* */
_reset_bitmap(d, ex->premap, MODL_MASK_LEN);
_reset_bitmap(d, ex->postmap, MODL_MASK_LEN);
SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL);
}
void cancel_running_msg(struct cmd_dispatcher *obj)
{
u8 i = 0;
for (i = 0; i < MAX_PHL_MSG_NUM;i++) {
if(TEST_STATUS_FLAG(obj->msg_ex_pool[i].status, MSG_STATUS_RUN))
cancel_msg(obj, &(obj->msg_ex_pool[i]));
}
}
void set_msg_bitmap(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex, u8 mdl_id)
{
void *d = phl_to_drvpriv(obj->phl_info);
/* ensure mandatory & wifi role module recv all msg*/
_os_mem_cpy(d, ex->premap, obj->bitmap, MODL_MASK_LEN);
_os_mem_cpy(d, ex->postmap, obj->bitmap, MODL_MASK_LEN);
if(_chk_bitmap_bit(obj->bitmap, mdl_id)) {
_add_bitmap_bit(ex->premap, &mdl_id, 1);
_add_bitmap_bit(ex->postmap, &mdl_id, 1);
}
//_print_bitmap(ex->premap);
}
void set_msg_custom_bitmap(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex,
enum phl_msg_opt opt, u8 *id_arr, u32 len, u8 mdl_id)
{
void *d = phl_to_drvpriv(obj->phl_info);
if (opt & MSG_OPT_SKIP_NOTIFY_OPT_MDL) {
_os_mem_cpy(d, ex->premap, obj->basemap, MODL_MASK_LEN);
_os_mem_cpy(d, ex->postmap, obj->basemap, MODL_MASK_LEN);
}
if (opt & MSG_OPT_BLIST_PRESENT) {
_clr_bitmap_bit(ex->premap, id_arr, len);
_clr_bitmap_bit(ex->postmap, id_arr, len);
} else {
_add_bitmap_bit(ex->premap, id_arr, len);
_add_bitmap_bit(ex->postmap, id_arr, len);
}
if(_chk_bitmap_bit(obj->bitmap, mdl_id)) {
_add_bitmap_bit(ex->premap, &mdl_id, 1);
_add_bitmap_bit(ex->postmap, &mdl_id, 1);
}
}
u8 *get_msg_bitmap(struct phl_dispr_msg_ex *ex)
{
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_PRE_PHASE)) {
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_PRE_PHASE);
return ex->premap;
} else {
CLEAR_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_PRE_PHASE);
return ex->postmap;
}
}
void init_dispr_mdl_mgnt_info(struct cmd_dispatcher *obj)
{
u8 i = 0;
for (i = 0; i < PHL_MDL_ID_MAX; i++)
SET_CUR_PENDING_EVT(obj, i, MSG_EVT_MAX);
}
static u8 pop_front_idle_req(struct cmd_dispatcher *obj,
struct phl_cmd_token_req_ex **req)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *new_req = NULL;
(*req) = NULL;
if (pq_pop(d, &(obj->token_req_idle_q), &new_req, _first, _bh)) {
(*req) = (struct phl_cmd_token_req_ex*)new_req;
(*req)->status = 0;
_os_mem_set(d, &((*req)->req), 0,
sizeof(struct phl_cmd_token_req));
_os_mem_set(d, &((*req)->add_req_info), 0,
sizeof(struct phl_token_op_info));
_os_mem_set(d, &((*req)->free_req_info), 0,
sizeof(struct phl_token_op_info));
return true;
} else {
return false;
}
}
static void push_back_idle_req(struct cmd_dispatcher *obj,
struct phl_cmd_token_req_ex *req)
{
void *d = phl_to_drvpriv(obj->phl_info);
req->status = 0;
SET_CUR_PENDING_EVT(obj, req->req.module_id, MSG_EVT_MAX);
pq_push(d, &(obj->token_req_idle_q), &(req->list), _tail, _bh);
}
static u8 pop_front_wait_req(struct cmd_dispatcher *obj,
struct phl_cmd_token_req_ex **req)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *new_req = NULL;
(*req) = NULL;
if (pq_pop(d, &(obj->token_req_wait_q), &new_req, _first, _bh)) {
(*req) = (struct phl_cmd_token_req_ex*)new_req;
SET_STATUS_FLAG((*req)->status, REQ_STATUS_PREPARE);
CLEAR_STATUS_FLAG((*req)->status, REQ_STATUS_ENQ);
return true;
} else {
return false;
}
}
static void push_back_wait_req(struct cmd_dispatcher *obj,
struct phl_cmd_token_req_ex *req)
{
void *d = phl_to_drvpriv(obj->phl_info);
pq_push(d, &(obj->token_req_wait_q), &(req->list), _tail, _bh);
SET_STATUS_FLAG(req->status, REQ_STATUS_ENQ);
}
static void clear_wating_req(struct cmd_dispatcher *obj)
{
struct phl_cmd_token_req_ex *ex = NULL;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s: remain cnt(%d)\n", __FUNCTION__, obj->token_req_idle_q.cnt);
while(obj->token_req_idle_q.cnt != MAX_CMD_REQ_NUM) {
while (pop_front_wait_req(obj, &ex)) {
ex->req.abort(obj, ex->req.priv);
push_back_idle_req(obj, ex);
}
}
}
void deregister_cur_cmd_req(struct cmd_dispatcher *obj, u8 notify)
{
struct phl_cmd_token_req *req = NULL;
void *d = phl_to_drvpriv(obj->phl_info);
u8 i = 0;
struct phl_dispr_msg_ex *ex = NULL;
if (obj->cur_cmd_req) {
req = &(obj->cur_cmd_req->req);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, id(%d), status(%d)\n",
__FUNCTION__, req->module_id, obj->cur_cmd_req->status);
CLEAR_STATUS_FLAG(obj->cur_cmd_req->status, REQ_STATUS_RUN);
for (i = 0; i < MAX_PHL_MSG_NUM; i++) {
ex = &(obj->msg_ex_pool[i]);
if (req->module_id != MSG_MDL_ID_FIELD(ex->msg.msg_id))
continue;
CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_REQ);
cancel_msg(obj, ex);
if(TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING)) {
dispr_clr_pending_msg((void*)obj);
/* inserted pending msg from this sepecific sender back to wait Q before abort notify
* would guarantee msg sent in abort notify is exactly last msg from this sender
* */
clear_pending_msg(obj);
}
}
if (notify == true) {
SET_STATUS_FLAG(obj->cur_cmd_req->status, REQ_STATUS_LAST_PERMIT);
req->abort(obj, req->priv);
CLEAR_STATUS_FLAG(obj->cur_cmd_req->status, REQ_STATUS_LAST_PERMIT);
}
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
SET_MDL_HANDLE(obj, obj->cur_cmd_req->req.module_id, NULL);
#endif
push_back_idle_req(obj, obj->cur_cmd_req);
_os_atomic_set(d, &(obj->token_cnt),
_os_atomic_read(d, &(obj->token_cnt))-1);
}
obj->cur_cmd_req = NULL;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
}
u8 register_cur_cmd_req(struct cmd_dispatcher *obj,
struct phl_cmd_token_req_ex *req)
{
void *d = phl_to_drvpriv(obj->phl_info);
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
SET_STATUS_FLAG(req->status, REQ_STATUS_RUN);
CLEAR_STATUS_FLAG(req->status, REQ_STATUS_PREPARE);
obj->cur_cmd_req = req;
_os_atomic_set(d, &(obj->token_cnt),
_os_atomic_read(d, &(obj->token_cnt))+1);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, id(%d)\n", __FUNCTION__, obj->cur_cmd_req->req.module_id);
ret = obj->cur_cmd_req->req.acquired((void*)obj, obj->cur_cmd_req->req.priv);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, ret(%d)\n", __FUNCTION__, ret);
if (ret == MDL_RET_FAIL) {
deregister_cur_cmd_req(obj, false);
return false;
}
else {
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
SET_MDL_HANDLE(obj, req->req.module_id, req);
#endif
return true;
}
}
void cancel_all_cmd_req(struct cmd_dispatcher *obj)
{
u8 i = 0;
struct phl_cmd_token_req_ex* req_ex = NULL;
for (i = 0; i < MAX_CMD_REQ_NUM;i++) {
req_ex = &(obj->token_req_ex_pool[i]);
if (req_ex->status)
SET_STATUS_FLAG(req_ex->status, REQ_STATUS_CANCEL);
}
}
void init_cmd_req_pool(struct cmd_dispatcher *obj)
{
u8 i = 0;
void *d = phl_to_drvpriv(obj->phl_info);
if (TEST_STATUS_FLAG(obj->status, DISPR_REQ_INIT))
return;
pq_init(d, &(obj->token_req_wait_q));
pq_init(d, &(obj->token_req_idle_q));
pq_init(d, &(obj->token_op_q));
_os_mem_set(d, obj->token_req_ex_pool, 0,
sizeof(struct phl_cmd_token_req_ex) * MAX_CMD_REQ_NUM);
for (i = 0; i < MAX_CMD_REQ_NUM;i++) {
obj->token_req_ex_pool[i].idx = i;
pq_push(d, &(obj->token_req_idle_q),
&(obj->token_req_ex_pool[i].list), _tail, _bh);
}
SET_STATUS_FLAG(obj->status, DISPR_REQ_INIT);
}
void deinit_cmd_req_pool(struct cmd_dispatcher *obj)
{
void *d = phl_to_drvpriv(obj->phl_info);
CLEAR_STATUS_FLAG(obj->status, DISPR_REQ_INIT);
pq_deinit(d, &(obj->token_req_wait_q));
pq_deinit(d, &(obj->token_req_idle_q));
pq_deinit(d, &(obj->token_op_q));
}
u8 chk_module_ops(struct phl_bk_module_ops *ops)
{
if (ops == NULL ||
ops->init == NULL ||
ops->deinit == NULL ||
ops->msg_hdlr == NULL ||
ops->set_info == NULL ||
ops->query_info == NULL ||
ops->start == NULL ||
ops->stop == NULL)
return false;
return true;
}
u8 chk_cmd_req_ops(struct phl_cmd_token_req *req)
{
if (req == NULL ||
req->module_id < PHL_FG_MDL_START ||
req->abort == NULL ||
req->acquired == NULL ||
req->msg_hdlr == NULL ||
req->set_info == NULL ||
req->query_info == NULL)
return false;
return true;
}
static u8 pop_front_token_op_info(struct cmd_dispatcher *obj,
struct phl_token_op_info **op_info)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *new_info = NULL;
(*op_info) = NULL;
if (pq_pop(d, &(obj->token_op_q), &new_info, _first, _bh)) {
(*op_info) = (struct phl_token_op_info *)new_info;
return true;
} else {
return false;
}
}
static u8 push_back_token_op_info(struct cmd_dispatcher *obj,
struct phl_token_op_info *op_info,
enum token_op_type type,
u8 data)
{
void *d = phl_to_drvpriv(obj->phl_info);
_os_spinlockfg sp_flags;
_os_spinlock(d, &obj->token_op_q_lock, _bh, &sp_flags);
if (op_info->used == true) {
_os_spinunlock(d, &obj->token_op_q_lock, _bh, &sp_flags);
return false;
}
op_info->used = true;
op_info->type = type;
op_info->data = data;
_os_spinunlock(d, &obj->token_op_q_lock, _bh, &sp_flags);
pq_push(d, &(obj->token_op_q), &(op_info->list), _tail, _bh);
notify_bk_thread(obj);
return true;
}
void _handle_token_op_info(struct cmd_dispatcher *obj, struct phl_token_op_info *op_info)
{
struct phl_cmd_token_req_ex *req_ex = NULL;
void *d = phl_to_drvpriv(obj->phl_info);
switch (op_info->type) {
case TOKEN_OP_RENEW_CMD_REQ:
/* fall through*/
case TOKEN_OP_ADD_CMD_REQ:
dispr_process_token_req(obj);
break;
case TOKEN_OP_FREE_CMD_REQ:
if (op_info->data >= MAX_CMD_REQ_NUM)
return;
req_ex = &(obj->token_req_ex_pool[op_info->data]);
if (!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN))
break;
deregister_cur_cmd_req(obj, false);
dispr_process_token_req(obj);
break;
case TOKEN_OP_CANCEL_CMD_REQ:
if (op_info->data >= MAX_CMD_REQ_NUM)
return;
req_ex = &(obj->token_req_ex_pool[op_info->data]);
if (TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_ENQ)) {
pq_del_node(d, &(obj->token_req_wait_q), &(req_ex->list), _bh);
/*
* Call command abort handle, abort handle
* should decide it has been acquired or not.
*/
req_ex->req.abort(obj, req_ex->req.priv);
push_back_idle_req(obj, req_ex);
} else if (TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN)){
deregister_cur_cmd_req(obj, true);
dispr_process_token_req(obj);
}
break;
default:
break;
}
}
void token_op_hanler(struct cmd_dispatcher *obj)
{
struct phl_token_op_info *info = NULL;
while (pop_front_token_op_info(obj, &info)) {
_handle_token_op_info(obj, info);
info->used = false;
}
}
static u8
dispr_enqueue_token_op_info(struct cmd_dispatcher *obj,
struct phl_token_op_info *op_info,
enum token_op_type type,
u8 data)
{
return push_back_token_op_info(obj, op_info, type, data);
}
u8 bk_module_init(struct cmd_dispatcher *obj, struct phl_bk_module *module)
{
if (TEST_STATUS_FLAG(module->status, MDL_INIT)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s module_id:%d already init\n",
__FUNCTION__, module->id);
return false;
}
if (module->ops.init((void*)obj->phl_info, (void*)obj,
&(module->priv)) == MDL_RET_SUCCESS) {
SET_STATUS_FLAG(module->status, MDL_INIT);
return true;
} else {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s fail module_id: %d \n", __FUNCTION__, module->id);
return false;
}
}
void bk_module_deinit(struct cmd_dispatcher *obj, struct phl_bk_module *module)
{
if (TEST_STATUS_FLAG(module->status, MDL_INIT))
module->ops.deinit((void*)obj, module->priv);
CLEAR_STATUS_FLAG(module->status, MDL_INIT);
}
u8 bk_module_start(struct cmd_dispatcher *obj, struct phl_bk_module *module)
{
if (!TEST_STATUS_FLAG(module->status, MDL_INIT) ||
TEST_STATUS_FLAG(module->status, MDL_STARTED)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s module_id:%d already start\n", __FUNCTION__,
module->id);
return false;
}
if (module->ops.start((void*)obj, module->priv) == MDL_RET_SUCCESS) {
SET_STATUS_FLAG(module->status, MDL_STARTED);
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
SET_MDL_HANDLE(obj, module->id, module);
#endif
return true;
} else {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s fail module_id: %d \n", __FUNCTION__, module->id);
return false;
}
}
u8 bk_module_stop(struct cmd_dispatcher *obj, struct phl_bk_module *module)
{
if (!TEST_STATUS_FLAG(module->status, MDL_STARTED))
return false;
CLEAR_STATUS_FLAG(module->status, MDL_STARTED);
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
SET_MDL_HANDLE(obj, module->id, NULL);
#endif
if (module->ops.stop((void*)obj, module->priv) == MDL_RET_SUCCESS) {
return true;
} else {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s fail module_id: %d \n", __FUNCTION__,
module->id);
return false;
}
}
void cur_req_hdl(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req;
if (cur_req == NULL)
return;
if (!TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_RUN) ||
TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_CANCEL))
return;
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_FOR_ABORT))
return;
cur_req->req.msg_hdlr((void*)obj, cur_req->req.priv, &(ex->msg));
}
void notify_msg_fail(struct cmd_dispatcher *obj,
struct phl_dispr_msg_ex *ex,
enum phl_mdl_ret_code ret)
{
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
SET_STATUS_FLAG(ex->status, MSG_STATUS_FAIL);
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_FAIL);
if (ret == MDL_RET_CANNOT_IO)
SET_MSG_INDC_FIELD(ex->msg.msg_id, MSG_INDC_CANNOT_IO);
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_BK_MDL) &&
(IS_DISPR_CTRL(MSG_MDL_ID_FIELD(ex->msg.msg_id)) || _chk_bitmap_bit(obj->bitmap, ex->module->id))) {
ex->module->ops.msg_hdlr(obj, ex->module->priv, &(ex->msg));
}
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_REQ)) {
cur_req_hdl(obj, ex);
}
}
enum phl_mdl_ret_code feed_mdl_msg(struct cmd_dispatcher *obj,
struct phl_bk_module *mdl,
struct phl_dispr_msg_ex *ex)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
u8 *bitmap = NULL;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, "%s, id:%d \n", __FUNCTION__, mdl->id);
ret = mdl->ops.msg_hdlr(obj, mdl->priv, &(ex->msg));
if (ret == MDL_RET_FAIL || ret == MDL_RET_CANNOT_IO) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "id:%d evt:0x%x fail\n",
mdl->id, ex->msg.msg_id);
ex->msg.rsvd[0] = mdl;
notify_msg_fail(obj, ex, ret);
} else if (ret == MDL_RET_PENDING) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "id:%d evt:0x%x pending\n",
mdl->id, ex->msg.msg_id);
SET_STATUS_FLAG(ex->status, MSG_STATUS_PENDING);
} else {
if (MSG_INDC_FIELD(ex->msg.msg_id) & MSG_INDC_PRE_PHASE)
bitmap = ex->premap;
else
bitmap = ex->postmap;
_clr_bitmap_bit(bitmap, &(mdl->id), 1);
}
return ret;
}
void msg_pre_phase_hdl(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
s8 i = 0;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_bk_module *mdl = NULL;
_os_list *node = NULL;
struct phl_queue *q = NULL;
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
u8 owner_id = (ex->module)?(ex->module->id):(PHL_MDL_ID_MAX);
enum phl_bk_module_priority priority = PHL_MDL_PRI_MAX;
if (owner_id <= PHL_BK_MDL_END)
priority = _get_mdl_priority(owner_id);
for (i = PHL_MDL_PRI_MAX - 1 ; i >= PHL_MDL_PRI_ROLE ; i--) {
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
ret = run_self_def_seq(obj, ex, i, true);
if (STOP_DISPATCH_MSG(ret))
return;
#endif
if (priority == i && _chk_bitmap_bit(ex->premap, owner_id)) {
ret = feed_mdl_msg(obj, ex->module, ex);
if (STOP_DISPATCH_MSG(ret))
return;
}
q = &(obj->module_q[(u8)i]);
if (pq_get_front(d, q, &node, _bh) == false)
continue;
do {
mdl = (struct phl_bk_module*)node;
if (!_chk_bitmap_bit(ex->premap, mdl->id) ||
!TEST_STATUS_FLAG(mdl->status, MDL_STARTED))
continue;
ret = feed_mdl_msg(obj, mdl, ex);
if (STOP_DISPATCH_MSG(ret))
return;
} while(pq_get_next(d, q, node, &node, _bh));
}
}
void msg_post_phase_hdl(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
s8 i = 0;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_bk_module *mdl = NULL;
_os_list *node = NULL;
struct phl_queue *q = NULL;
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
u8 owner_id = (ex->module)?(ex->module->id):(PHL_MDL_ID_MAX);
enum phl_bk_module_priority priority = PHL_MDL_PRI_MAX;
if (owner_id <= PHL_BK_MDL_END)
priority = _get_mdl_priority(owner_id);
for (i = PHL_MDL_PRI_ROLE ; i < PHL_MDL_PRI_MAX ; i++) {
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
ret = run_self_def_seq(obj, ex, i, false);
if (STOP_DISPATCH_MSG(ret))
return;
#endif
if (priority == i && _chk_bitmap_bit(ex->postmap, owner_id)) {
ret = feed_mdl_msg(obj, ex->module, ex);
if (STOP_DISPATCH_MSG(ret))
return;
}
q = &(obj->module_q[(u8)i]);
if (pq_get_tail(d, q, &node, _bh) == false)
continue;
do {
mdl = (struct phl_bk_module*)node;
if (!_chk_bitmap_bit(ex->postmap, mdl->id)||
!TEST_STATUS_FLAG(mdl->status, MDL_STARTED))
continue;
ret = feed_mdl_msg(obj, mdl, ex);
if (STOP_DISPATCH_MSG(ret))
return;
} while(pq_get_prev(d, q, node, &node, _bh));
}
}
u8 get_cur_cmd_req_id(struct cmd_dispatcher *obj, u32 *req_status)
{
struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req;
if(req_status)
*req_status = 0;
if (cur_req == NULL )
return (u8)PHL_MDL_ID_MAX;
if(req_status)
*req_status = cur_req->status;
if(!TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_RUN) ||
TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_CANCEL))
return (u8)PHL_MDL_ID_MAX;
else
return cur_req->req.module_id;
}
#define MSG_REDIRECT_CHK(_ex) \
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_FAIL)|| \
TEST_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL)) \
goto recycle;\
if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING)) \
goto reschedule;
void msg_dispatch(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
u8 *bitmap = get_msg_bitmap(ex);
void *d = phl_to_drvpriv(obj->phl_info);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_,
"%s, msg_id:0x%x status: 0x%x\n", __FUNCTION__, ex->msg.msg_id, ex->status);
MSG_REDIRECT_CHK(ex);
_notify_dispr_controller(obj, ex);
MSG_REDIRECT_CHK(ex);
if ((MSG_INDC_FIELD(ex->msg.msg_id) & MSG_INDC_PRE_PHASE) &&
_is_bitmap_empty(d, bitmap) == false)
msg_pre_phase_hdl(obj, ex);
MSG_REDIRECT_CHK(ex);
if (_is_bitmap_empty(d, bitmap)) {
/* pre protocol phase done, switch to post protocol phase*/
CLEAR_STATUS_FLAG(ex->status, MSG_STATUS_PRE_PHASE);
bitmap = get_msg_bitmap(ex);
} else {
PHL_ERR("%s, invalid bitmap state, msg status:0x%x \n", __FUNCTION__, ex->status);
SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL);
goto recycle;
}
if (_is_bitmap_empty(d, bitmap) == false)
msg_post_phase_hdl(obj, ex);
MSG_REDIRECT_CHK(ex);
if (_is_bitmap_empty(d, bitmap)) {
/* post protocol phase done */
cur_req_hdl(obj, ex);
goto recycle;
} else {
PHL_ERR("%s, invalid bitmap state, msg status:0x%x \n", __FUNCTION__, ex->status);
SET_STATUS_FLAG(ex->status, MSG_STATUS_CANCEL);
goto recycle;
}
reschedule:
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, msg:0x%x reschedule \n", __FUNCTION__,
ex->msg.msg_id);
if(TEST_STATUS_FLAG(ex->status, MSG_STATUS_PENDING))
push_back_pending_msg(obj, ex);
else
push_back_wait_msg(obj, ex);
return;
recycle:
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_,
"%s, msg:0x%x recycle \n", __FUNCTION__,
ex->msg.msg_id);
push_back_idle_msg(obj, ex);
}
void dispr_thread_loop_hdl(struct cmd_dispatcher *obj)
{
struct phl_dispr_msg_ex *ex = NULL;
/* check pending msg need in advance.
* if pending msg is not empty before while loop breaks,
* these msg would be cleared in deinit_dispr_msg_pool.
*/
clear_pending_msg(obj);
/* token op Q in advance.
* if req wait Q is not empty before while loop breaks,
* these msg would be cleared in deinit_cmd_req_pool.
*/
token_op_hanler(obj);
if (pop_front_wait_msg(obj, &ex)) {
if (is_msg_canceled(obj, ex)) {
push_back_idle_msg(obj, ex);
return;
}
/* ensure all modules set in msg bitmap
exists in cur dispatcher*/
_and_bitmaps(obj->bitmap, ex->premap, MODL_MASK_LEN);
_and_bitmaps(obj->bitmap, ex->postmap, MODL_MASK_LEN);
msg_dispatch(obj, ex);
}
}
void dispr_thread_leave_hdl(struct cmd_dispatcher *obj)
{
deregister_cur_cmd_req(obj, true);
/* clear remaining pending & waiting msg */
clear_waiting_msg(obj);
/* pop out all waiting cmd req and notify abort. */
clear_wating_req(obj);
}
int background_thread_hdl(void *param)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)param;
void *d = phl_to_drvpriv(obj->phl_info);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s enter\n", __FUNCTION__);
while (!_os_thread_check_stop(d, &(obj->bk_thread))) {
_os_sema_down(d, &obj->msg_q_sema);
if(_os_thread_check_stop(d, &(obj->bk_thread)))
break;
dispr_thread_loop_hdl(obj);
}
dispr_thread_leave_hdl(obj);
_os_thread_wait_stop(d, &(obj->bk_thread));
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s down\n", __FUNCTION__);
return 0;
}
u8 search_mdl(void *d, void *mdl, void *priv)
{
enum phl_module_id id = *(enum phl_module_id *)priv;
struct phl_bk_module *module = NULL;
module = (struct phl_bk_module *)mdl;
if (module->id == id) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s :: id %d\n", __FUNCTION__, id);
return true;
}
else
return false;
}
u8 get_module_by_id(struct cmd_dispatcher *obj, enum phl_module_id id,
struct phl_bk_module **mdl)
{
void *d = phl_to_drvpriv(obj->phl_info);
u8 i = 0;
_os_list *node = NULL;
if (mdl == NULL)
return false;
if (IS_DISPR_CTRL(id)) {
if (!TEST_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT))
return false;
*mdl = &(obj->controller);
return true;
}
if (!_chk_bitmap_bit(obj->bitmap, id))
return false;
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
if(pq_search_node(d, &(obj->module_q[i]), &node, _bh, false, &id, search_mdl)) {
*mdl = (struct phl_bk_module*)node;
return true;
}
}
*mdl = NULL;
return false;
}
enum rtw_phl_status phl_dispr_get_idx(void *dispr, u8 *idx)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
if (dispr == NULL)
return RTW_PHL_STATUS_FAILURE;
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) || idx == NULL)
return RTW_PHL_STATUS_FAILURE;
*idx = obj->idx;
return RTW_PHL_STATUS_SUCCESS;
}
/* Each dispr has a controller.
* A dispr controller is designed for phl instance to interact with dispr modules that are belonged to a specific hw band,
* phl instance can perform follwing actions via dedicated controller:
* 1. allow (phl status/non-dispr phl modules) to monitor & drop msg
* 2. allow dispr modules, that are belonged to same dispr, to sequentially communicate with phl instance & call phl api,
* and also allow (phl status/non-dispr phl modules) to notify dispr by hw band.
* *Note*
* 1. when cmd dispatch engine is in solo thread mode (each dispr has its own dedicated thread).
* phl instance might receive msg from different dispr simutaneously and
* currently using semaphore (dispr_ctrl_sema) to prevent multi-thread condition.
* 2. when cmd dispatch engine is in share thread mode, msg from different dispr would pass to controller sequentially.
* PS:
* phl instance: means phl_info_t, which include phl mgnt status & non-dispr phl modules
* dispr modules: all existing background & foreground modules.
* non-dispr phl module : Data path (TX/Rx), etc
* phl mgnt status : stop/surprise remove/cannot io
*/
static enum rtw_phl_status _register_dispr_controller(struct cmd_dispatcher *obj)
{
struct phl_bk_module *ctrl = &(obj->controller);
dispr_ctrl_hook_ops(obj, &(ctrl->ops));
ctrl->id = PHL_MDL_PHY_MGNT;
if(bk_module_init(obj, &(obj->controller)) == true)
return RTW_PHL_STATUS_SUCCESS;
else {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s(): fail \n", __func__);
return RTW_PHL_STATUS_FAILURE;
}
}
static void _deregister_dispr_controller(struct cmd_dispatcher *obj)
{
bk_module_deinit(obj, &(obj->controller));
}
static enum rtw_phl_status _start_dispr_controller(struct cmd_dispatcher *obj)
{
if (bk_module_start(obj, &(obj->controller)) == true) {
SET_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT);
return RTW_PHL_STATUS_SUCCESS;
}
else {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s(): fail \n", __func__);
return RTW_PHL_STATUS_FAILURE;
}
}
static enum rtw_phl_status _stop_dispr_controller(struct cmd_dispatcher *obj)
{
CLEAR_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT);
if (bk_module_stop(obj, &(obj->controller)) == true)
return RTW_PHL_STATUS_SUCCESS;
else {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s(): fail \n", __func__);
return RTW_PHL_STATUS_FAILURE;
}
}
void _notify_dispr_controller(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex)
{
if (!TEST_STATUS_FLAG(obj->status, DISPR_CTRL_PRESENT))
return;
#ifdef CONFIG_CMD_DISP_SOLO_MODE
dispr_ctrl_sema_down(obj->phl_info);
#endif
feed_mdl_msg(obj, &(obj->controller), ex);
#ifdef CONFIG_CMD_DISP_SOLO_MODE
dispr_ctrl_sema_up(obj->phl_info);
#endif
}
void dispr_thread_stop_prior_hdl(struct cmd_dispatcher *obj)
{
CLEAR_STATUS_FLAG(obj->status, DISPR_STARTED);
_stop_dispr_controller(obj);
cancel_all_cmd_req(obj);
cancel_running_msg(obj);
}
void dispr_thread_stop_post_hdl(struct cmd_dispatcher *obj)
{
void *d = phl_to_drvpriv(obj->phl_info);
/* have to wait for bk thread ends before deinit msg & req*/
deinit_dispr_msg_pool(obj);
deinit_cmd_req_pool(obj);
_os_atomic_set(d, &(obj->token_cnt), 0);
_os_sema_free(d, &(obj->msg_q_sema));
}
enum rtw_phl_status dispr_init(struct phl_info_t *phl_info, void **dispr, u8 idx)
{
struct cmd_dispatcher *obj = NULL;
void *d = phl_to_drvpriv(phl_info);
u8 i = 0;
(*dispr) = NULL;
obj = (struct cmd_dispatcher *)_os_mem_alloc(d, sizeof(struct cmd_dispatcher));
if (obj == NULL) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, alloc fail\n", __FUNCTION__);
return RTW_PHL_STATUS_RESOURCE;
}
obj->phl_info = phl_info;
obj->idx = idx;
_os_atomic_set(d, &(obj->token_cnt), 0);
for (i = 0 ; i < PHL_MDL_PRI_MAX; i++)
pq_init(d, &(obj->module_q[i]));
(*dispr) = (void*)obj;
_os_spinlock_init(d, &(obj->token_op_q_lock));
SET_STATUS_FLAG(obj->status, DISPR_INIT);
SET_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE);
_register_dispr_controller(obj);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, size dispr(%d), msg_ex(%d), req_ex(%d) \n",
__FUNCTION__, (int)sizeof(struct cmd_dispatcher),
(int)sizeof(struct phl_dispr_msg_ex),
(int)sizeof(struct phl_cmd_token_req_ex));
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_deinit(struct phl_info_t *phl, void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
u8 i = 0;
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT))
return RTW_PHL_STATUS_SUCCESS;
dispr_stop(dispr);
_deregister_dispr_controller(obj);
for (i = 0 ; i < PHL_MDL_PRI_MAX; i++)
pq_deinit(d, &(obj->module_q[i]));
_os_spinlock_free(d, &(obj->token_op_q_lock));
_os_mem_free(d, obj, sizeof(struct cmd_dispatcher));
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_start(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
if (TEST_STATUS_FLAG(obj->status, DISPR_STARTED))
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
init_dispr_msg_pool(obj);
init_cmd_req_pool(obj);
init_dispr_mdl_mgnt_info(obj);
_os_mem_set(d, &(obj->renew_req_info), 0,
sizeof(struct phl_token_op_info));
_os_sema_init(d, &(obj->msg_q_sema), 0);
CLEAR_EXCL_MDL(obj);
if (disp_eng_is_solo_thread_mode(obj->phl_info)) {
_os_thread_init(d, &(obj->bk_thread), background_thread_hdl, obj,
"dispr_solo_thread");
_os_thread_schedule(d, &(obj->bk_thread));
}
SET_STATUS_FLAG(obj->status, DISPR_STARTED);
_start_dispr_controller(obj);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
bool is_dispr_started(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
if (TEST_STATUS_FLAG(obj->status, DISPR_STARTED))
return true;
return false;
}
enum rtw_phl_status dispr_stop(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED))
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
dispr_thread_stop_prior_hdl(obj);
if (disp_eng_is_solo_thread_mode(obj->phl_info)) {
_os_thread_stop(d, &(obj->bk_thread));
_os_sema_up(d, &(obj->msg_q_sema));
_os_thread_deinit(d, &(obj->bk_thread));
}
dispr_thread_stop_post_hdl(obj);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_register_module(void *dispr,
enum phl_module_id id,
struct phl_bk_module_ops *ops)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_bk_module *module = NULL;
u8 ret = true;
enum phl_bk_module_priority priority = _get_mdl_priority(id);
FUNCIN();
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) ||
priority == PHL_MDL_PRI_MAX ||
chk_module_ops(ops) == false ||
_chk_bitmap_bit(obj->bitmap, id) == true) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, register fail\n", __FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
module = (struct phl_bk_module *)_os_mem_alloc(d, sizeof(struct phl_bk_module));
if (module == NULL) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, allocte fail\n", __FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
module->id = id;
_os_mem_cpy(d, &(module->ops), ops, sizeof(struct phl_bk_module_ops));
pq_push(d, &(obj->module_q[priority]), &(module->list), _tail, _bh);
ret = bk_module_init(obj, module);
if (ret == true && TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) {
ret = bk_module_start(obj, module);
if (ret == true)
_add_bitmap_bit(obj->bitmap, &(module->id), 1);
if (ret == true && priority != PHL_MDL_PRI_OPTIONAL)
_add_bitmap_bit(obj->basemap, &(module->id), 1);
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s id:%d, ret:%d\n",__FUNCTION__, id, ret);
if (ret == true) {
return RTW_PHL_STATUS_SUCCESS;
} else {
bk_module_deinit(obj, module);
_os_mem_free(d, module, sizeof(struct phl_bk_module));
return RTW_PHL_STATUS_FAILURE;
}
}
enum rtw_phl_status dispr_deregister_module(void *dispr,
enum phl_module_id id)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_bk_module *module = NULL;
_os_list *mdl = NULL;
enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE;
enum phl_bk_module_priority priority = _get_mdl_priority(id);
FUNCIN();
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) ||
priority == PHL_MDL_PRI_MAX)
return phl_stat;
if(pq_search_node(d, &(obj->module_q[priority]), &mdl, _bh, true, &id, search_mdl)) {
module = (struct phl_bk_module *)mdl;
_clr_bitmap_bit(obj->bitmap, &(module->id), 1);
_clr_bitmap_bit(obj->basemap, &(module->id), 1);
bk_module_stop(obj, module);
bk_module_deinit(obj, module);
_os_mem_free(d, module, sizeof(struct phl_bk_module));
phl_stat = RTW_PHL_STATUS_SUCCESS;
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id: %d stat:%d\n", __FUNCTION__, id, phl_stat);
return phl_stat;
}
enum rtw_phl_status dispr_module_init(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *mdl = NULL;
u8 i = 0;
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT))
return RTW_PHL_STATUS_FAILURE;
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
if (pq_get_front(d, &(obj->module_q[i]), &mdl, _bh) == false)
continue;
do {
bk_module_init(obj, (struct phl_bk_module *)mdl);
} while(pq_get_next(d, &(obj->module_q[i]), mdl, &mdl, _bh));
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_module_deinit(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *mdl = NULL;
u8 i = 0;
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT))
return RTW_PHL_STATUS_FAILURE;
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
while (pq_pop(d, &(obj->module_q[i]), &mdl, _first, _bh)) {
bk_module_deinit(obj, (struct phl_bk_module *)mdl);
_os_mem_free(d, mdl, sizeof(struct phl_bk_module));
}
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_module_start(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *mdl = NULL;
struct phl_bk_module *module = NULL;
u8 i = 0;
u8 ret = false;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED))
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
if (pq_get_front(d, &(obj->module_q[i]), &mdl, _bh) == false)
continue;
do {
module = (struct phl_bk_module*)mdl;
ret = bk_module_start(obj, module);
if (ret == true)
_add_bitmap_bit(obj->bitmap, &(module->id), 1);
if (ret == true && i != PHL_MDL_PRI_OPTIONAL)
_add_bitmap_bit(obj->basemap, &(module->id), 1);
} while(pq_get_next(d, &(obj->module_q[i]), mdl, &mdl, _bh));
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
/*_print_bitmap(obj->bitmap);*/
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_module_stop(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *mdl = NULL;
struct phl_bk_module *module = NULL;
u8 i = 0;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED))
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
if (pq_get_front(d, &(obj->module_q[i]), &mdl, _bh) == false)
continue;
do {
module = (struct phl_bk_module *)mdl;
_clr_bitmap_bit(obj->bitmap, &(module->id), 1);
_clr_bitmap_bit(obj->basemap, &(module->id), 1);
bk_module_stop(obj, module);
} while(pq_get_next(d, &(obj->module_q[i]), mdl, &mdl, _bh));
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
/*_print_bitmap(obj->bitmap);*/
return RTW_PHL_STATUS_SUCCESS;
}
/**
* dispr_get_cur_cmd_req -- background module can call this function to
* check cmd dispatcher is idle to know the risk or conflict for the I/O.
* @dispr: dispatcher handler, get from _disp_eng_get_dispr_by_idx
* @handle: get current cmd request, NULL means cmd dispatcher is idle
* return RTW_PHL_STATUS_SUCCESS means cmd dispatcher is busy and can get
* current cmd request from handle parameter
* return RTW_PHL_STATUS_FAILURE means cmd dispatcher is idle
*/
enum rtw_phl_status
dispr_get_cur_cmd_req(void *dispr, void **handle)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
struct phl_cmd_token_req_ex *cur_req = NULL;
enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE;
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT|DISPR_STARTED) || handle == NULL) {
phl_stat = RTW_PHL_STATUS_UNEXPECTED_ERROR;
return phl_stat;
}
(*handle) = NULL;
cur_req = obj->cur_cmd_req;
if (cur_req == NULL ||
!TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_RUN) ||
TEST_STATUS_FLAG(cur_req->status, REQ_STATUS_CANCEL))
return phl_stat;
*handle = (void *)cur_req;
phl_stat = RTW_PHL_STATUS_SUCCESS;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_,
"%s, req module id:%d phl_stat:%d\n", __FUNCTION__,
cur_req->req.module_id, phl_stat);
return phl_stat;
}
enum rtw_phl_status
dispr_set_cur_cmd_info(void *dispr,
struct phl_module_op_info *op_info)
{
void *handle = NULL;
struct phl_cmd_token_req_ex *cmd_req = NULL;
struct phl_cmd_token_req *req = NULL;
if (RTW_PHL_STATUS_SUCCESS != dispr_get_cur_cmd_req(dispr, &handle))
return RTW_PHL_STATUS_FAILURE;
cmd_req = (struct phl_cmd_token_req_ex *)handle;
req = &(cmd_req->req);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id:%d\n", __FUNCTION__, req->module_id);
if (req->set_info(dispr, req->priv, op_info) == MDL_RET_SUCCESS)
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status
dispr_query_cur_cmd_info(void *dispr,
struct phl_module_op_info *op_info)
{
void *handle = NULL;
struct phl_cmd_token_req_ex *cmd_req = NULL;
struct phl_cmd_token_req *req = NULL;
if (RTW_PHL_STATUS_SUCCESS != dispr_get_cur_cmd_req(dispr, &handle))
return RTW_PHL_STATUS_FAILURE;
cmd_req = (struct phl_cmd_token_req_ex *)handle;
req = &(cmd_req->req);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_DEBUG_, "%s, id:%d\n", __FUNCTION__, req->module_id);
if (req->query_info(dispr, req->priv, op_info) == MDL_RET_SUCCESS)
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status
dispr_get_bk_module_handle(void *dispr,
enum phl_module_id id,
void **handle)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
_os_list *mdl = NULL;
enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE;
enum phl_bk_module_priority priority = _get_mdl_priority(id);
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) ||
handle == NULL ||
priority == PHL_MDL_PRI_MAX ||
!_chk_bitmap_bit(obj->bitmap, id))
return phl_stat;
(*handle) = NULL;
if(pq_search_node(d, &(obj->module_q[priority]), &mdl, _bh, false, &id, search_mdl)) {
(*handle) = mdl;
phl_stat = RTW_PHL_STATUS_SUCCESS;
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, id:%d phl_stat:%d\n", __FUNCTION__, id, phl_stat);
return phl_stat;
}
enum rtw_phl_status
dispr_set_bk_module_info(void *dispr,
void *handle,
struct phl_module_op_info *op_info)
{
struct phl_bk_module *module = (struct phl_bk_module *)handle;
struct phl_bk_module_ops *ops = &(module->ops);
if (!TEST_STATUS_FLAG(module->status, MDL_INIT))
return RTW_PHL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id:%d\n", __FUNCTION__, module->id);
if (ops->set_info(dispr, module->priv, op_info) == MDL_RET_SUCCESS)
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status
dispr_query_bk_module_info(void *dispr,
void *handle,
struct phl_module_op_info *op_info)
{
struct phl_bk_module *module = (struct phl_bk_module *)handle;
struct phl_bk_module_ops *ops = &(module->ops);
if (!TEST_STATUS_FLAG(module->status, MDL_INIT))
return RTW_PHL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, id:%d\n", __FUNCTION__, module->id);
if (ops->query_info(dispr, module->priv, op_info) == MDL_RET_SUCCESS)
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status
dispr_set_src_info(void *dispr,
struct phl_msg *msg,
struct phl_module_op_info *op_info)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE;
u8 id = MSG_MDL_ID_FIELD(msg->msg_id);
struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req;
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
struct phl_dispr_msg_ex *ex = (struct phl_dispr_msg_ex *)msg;
u8 cur_req_id = get_cur_cmd_req_id(obj, NULL);
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) ||
(!_chk_bitmap_bit(obj->bitmap, id) &&
cur_req_id != id))
return phl_stat;
if (cur_req_id == id) {
ret = cur_req->req.set_info(dispr, cur_req->req.priv, op_info);
} else if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_BK_MDL)) {
ret = ex->module->ops.set_info(dispr, ex->module->priv,
op_info);
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, id:%d phl_stat:%d\n", __FUNCTION__, id, phl_stat);
if (ret == MDL_RET_FAIL)
return RTW_PHL_STATUS_FAILURE;
else
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
dispr_query_src_info(void *dispr,
struct phl_msg *msg,
struct phl_module_op_info *op_info)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
enum rtw_phl_status phl_stat = RTW_PHL_STATUS_FAILURE;
u8 id = MSG_MDL_ID_FIELD(msg->msg_id);
struct phl_cmd_token_req_ex *cur_req = obj->cur_cmd_req;
struct phl_dispr_msg_ex *ex = (struct phl_dispr_msg_ex *)msg;
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
u8 cur_req_id = get_cur_cmd_req_id(obj, NULL);
if (!TEST_STATUS_FLAG(obj->status, DISPR_INIT) ||
(!_chk_bitmap_bit(obj->bitmap, id) &&
cur_req_id != id))
return phl_stat;
if (cur_req_id == id) {
ret = cur_req->req.query_info(dispr, cur_req->req.priv, op_info);
} else if (TEST_STATUS_FLAG(ex->status, MSG_STATUS_OWNER_BK_MDL)) {
ret = ex->module->ops.query_info(dispr, ex->module->priv,
op_info);
}
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, id:%d phl_stat:%d\n", __FUNCTION__, id, phl_stat);
if (ret == MDL_RET_FAIL)
return RTW_PHL_STATUS_FAILURE;
else
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
dispr_send_msg(void *dispr,
struct phl_msg *msg,
struct phl_msg_attribute *attr,
u32 *msg_hdl)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_dispr_msg_ex *msg_ex = NULL;
u8 module_id = MSG_MDL_ID_FIELD(msg->msg_id); /* msg src */
u32 req_status = 0;
u8 cur_req_id = get_cur_cmd_req_id(obj, &req_status);
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED)) {
sts = RTW_PHL_STATUS_UNEXPECTED_ERROR;
goto err;
}
if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)){
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,"%s: dispr shall stop\n", __FUNCTION__);
sts = RTW_PHL_STATUS_UNEXPECTED_ERROR;
goto err;
}
if(attr && attr->notify.id_arr == NULL && attr->notify.len) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s attribute err\n",__FUNCTION__);
sts = RTW_PHL_STATUS_INVALID_PARAM;
goto err;
}
if (!IS_DISPR_CTRL(module_id) &&
!_chk_bitmap_bit(obj->bitmap, module_id) &&
((cur_req_id != PHL_MDL_ID_MAX && cur_req_id != module_id) ||
(cur_req_id == PHL_MDL_ID_MAX && req_status == 0)||
(cur_req_id == PHL_MDL_ID_MAX && !TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT)))) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s module not allow to send\n", __FUNCTION__);
sts = RTW_PHL_STATUS_INVALID_PARAM;
goto err;
}
if (!pop_front_idle_msg(obj, &msg_ex)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s idle msg empty\n", __FUNCTION__);
sts = RTW_PHL_STATUS_RESOURCE;
goto err;
}
if (msg_hdl)
*msg_hdl = 0;
_os_mem_cpy(d, &msg_ex->msg, msg, sizeof(struct phl_msg));
set_msg_bitmap(obj, msg_ex, module_id);
if (attr) {
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
msg_ex->attr = (struct dispr_msg_attr *)attr->dispr_attr;
attr->dispr_attr = NULL;
#endif
set_msg_custom_bitmap(obj, msg_ex, attr->opt,
attr->notify.id_arr, attr->notify.len, module_id);
if (attr->completion.completion) {
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_NOTIFY_COMPLETE);
msg_ex->completion.completion = attr->completion.completion;
msg_ex->completion.priv = attr->completion.priv;
}
if (TEST_STATUS_FLAG(attr->opt, MSG_OPT_CLR_SNDR_MSG_IF_PENDING))
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_CLR_SNDR_MSG_IF_PENDING);
if (TEST_STATUS_FLAG(attr->opt, MSG_OPT_PENDING_DURING_CANNOT_IO))
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_PENDING_DURING_CANNOT_IO);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, opt:0x%x\n",__FUNCTION__, attr->opt);
}
if (get_module_by_id(obj, module_id, &(msg_ex->module)) == true) {
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_BK_MDL);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s module(%d) found\n", __FUNCTION__, module_id);
} else if ((cur_req_id == module_id) ||
(cur_req_id == PHL_MDL_ID_MAX && TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT))) {
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_REQ);
}
if(TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_REQ) &&
TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT) &&
(attr == NULL || !TEST_STATUS_FLAG(attr->opt, MSG_OPT_SEND_IN_ABORT))) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s msg not allow since cur req is going to unload\n", __FUNCTION__);
SET_MSG_INDC_FIELD(msg_ex->msg.msg_id, MSG_INDC_FAIL);
push_back_idle_msg(obj, msg_ex);
sts = RTW_PHL_STATUS_FAILURE;
goto exit;
}
if (TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_OWNER_REQ) &&
TEST_STATUS_FLAG(req_status,REQ_STATUS_LAST_PERMIT)) {
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_FOR_ABORT);
SET_STATUS_FLAG(obj->status, DISPR_WAIT_ABORT_MSG_DONE);
}
SET_STATUS_FLAG(msg_ex->status, MSG_STATUS_PRE_PHASE);
if (IS_DISPR_CTRL(module_id))
insert_msg_by_priority(obj, msg_ex);
else
push_back_wait_msg(obj, msg_ex);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, status:0x%x\n",__FUNCTION__, msg_ex->status);
if(msg_hdl)
*msg_hdl = GEN_VALID_HDL(msg_ex->idx);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s, msg_id:0x%x\n", __FUNCTION__, msg->msg_id);
return RTW_PHL_STATUS_SUCCESS;
err:
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
if(attr)
free_dispr_attr(d,(struct dispr_msg_attr **) &(attr->dispr_attr));
#endif
exit:
return sts;
}
enum rtw_phl_status dispr_cancel_msg(void *dispr, u32 *msg_hdl)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
struct phl_dispr_msg_ex *msg_ex = NULL;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || msg_hdl == NULL)
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
if (!IS_HDL_VALID(*msg_hdl) ||
GET_IDX_FROM_HDL(*msg_hdl) >= MAX_PHL_MSG_NUM) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, HDL invalid\n", __FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
msg_ex = &(obj->msg_ex_pool[GET_IDX_FROM_HDL(*msg_hdl)]);
*msg_hdl = 0;
if (!TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_ENQ) &&
!TEST_STATUS_FLAG(msg_ex->status, MSG_STATUS_RUN)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s, HDL status err\n", __FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
cancel_msg(obj, msg_ex);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status dispr_clr_pending_msg(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
SET_STATUS_FLAG(obj->status, DISPR_CLR_PEND_MSG);
notify_bk_thread(obj);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status
dispr_add_token_req(void *dispr,
struct phl_cmd_token_req *req,
u32 *req_hdl)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_cmd_token_req_ex *req_ex = NULL;
enum rtw_phl_status stat = RTW_PHL_STATUS_SUCCESS;
_os_list *node = NULL;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) ||
req_hdl == NULL ||
chk_cmd_req_ops(req) == false)
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)){
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,"%s: dispr shall stop\n", __FUNCTION__);
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
}
if (!pop_front_idle_req(obj, &req_ex)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_, "%s idle req empty\n", __FUNCTION__);
return RTW_PHL_STATUS_RESOURCE;
}
_os_mem_cpy(d, &(req_ex->req), req, sizeof(struct phl_cmd_token_req));
push_back_wait_req(obj, req_ex);
*req_hdl = GEN_VALID_HDL(req_ex->idx);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, id:%d, hdl:0x%x token_cnt:%d\n", __FUNCTION__,
req->module_id,
*req_hdl,
_os_atomic_read(d, &(obj->token_cnt)));
if (pq_get_front(d, &(obj->token_op_q), &node, _bh) == false &&
_os_atomic_read(d, &(obj->token_cnt)) == 0)
stat = RTW_PHL_STATUS_SUCCESS;
else
stat = RTW_PHL_STATUS_PENDING;
dispr_enqueue_token_op_info(obj, &req_ex->add_req_info, TOKEN_OP_ADD_CMD_REQ, req_ex->idx);
return stat;
}
enum rtw_phl_status dispr_cancel_token_req(void *dispr, u32 *req_hdl)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
struct phl_cmd_token_req_ex *req_ex = NULL;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || req_hdl == NULL)
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
if (!IS_HDL_VALID(*req_hdl) ||
GET_IDX_FROM_HDL(*req_hdl) >= MAX_CMD_REQ_NUM) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s, HDL(0x%x) invalid\n", __FUNCTION__, *req_hdl);
return RTW_PHL_STATUS_FAILURE;
}
req_ex = &(obj->token_req_ex_pool[GET_IDX_FROM_HDL(*req_hdl)]);
if (!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_ENQ) &&
!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN) &&
!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_PREPARE)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s, HDL(0x%x) status err\n", __FUNCTION__, *req_hdl);
return RTW_PHL_STATUS_FAILURE;
}
SET_STATUS_FLAG(req_ex->status, REQ_STATUS_CANCEL);
if (dispr_enqueue_token_op_info(obj, &req_ex->free_req_info, TOKEN_OP_CANCEL_CMD_REQ, req_ex->idx))
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status dispr_free_token(void *dispr, u32 *req_hdl)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_cmd_token_req_ex *req_ex = NULL;
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED) || req_hdl == NULL)
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
if (obj->cur_cmd_req == NULL ||
_os_atomic_read(d, &(obj->token_cnt)) == 0 ||
!IS_HDL_VALID(*req_hdl) ||
GET_IDX_FROM_HDL(*req_hdl) >= MAX_CMD_REQ_NUM) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s, HDL(0x%x) invalid\n", __FUNCTION__, *req_hdl);
return RTW_PHL_STATUS_FAILURE;
}
req_ex = &(obj->token_req_ex_pool[GET_IDX_FROM_HDL(*req_hdl)]);
if (!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_RUN) &&
!TEST_STATUS_FLAG(req_ex->status, REQ_STATUS_PREPARE)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_ERR_,
"%s, HDL(0x%x) mismatch\n", __FUNCTION__, *req_hdl);
return RTW_PHL_STATUS_FAILURE;
}
SET_STATUS_FLAG(req_ex->status, REQ_STATUS_CANCEL);
if (dispr_enqueue_token_op_info(obj, &req_ex->free_req_info, TOKEN_OP_FREE_CMD_REQ, req_ex->idx))
return RTW_PHL_STATUS_SUCCESS;
else
return RTW_PHL_STATUS_FAILURE;
}
enum rtw_phl_status dispr_notify_dev_io_status(void *dispr, enum phl_module_id mdl_id, bool allow_io)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS;
if (allow_io == false) {
if (!TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) {
SET_STATUS_FLAG(obj->status, DISPR_CANNOT_IO);
SET_EXCL_MDL(obj, mdl_id);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, mdl_id(%d) notify cannot io\n", __FUNCTION__, mdl_id);
status = send_dev_io_status_change(obj, allow_io);
}
}
else {
if (TEST_STATUS_FLAG(obj->status, DISPR_CANNOT_IO)) {
CLEAR_STATUS_FLAG(obj->status, DISPR_CANNOT_IO);
CLEAR_EXCL_MDL(obj);
status = send_dev_io_status_change(obj, allow_io);
dispr_clr_pending_msg(dispr);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, mdl_id(%d) notify io resume\n", __FUNCTION__, mdl_id);
}
}
return status;
}
void dispr_notify_shall_stop(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
if (!TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)) {
SET_STATUS_FLAG(obj->status, DISPR_SHALL_STOP);
dispr_clr_pending_msg(dispr);
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, notify shall stop\n", __FUNCTION__);
}
}
u8 dispr_is_fg_empty(void *dispr)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
bool is_empty = true;
void *drv = phl_to_drvpriv(obj->phl_info);
struct phl_queue *q = NULL;
_os_list *node = NULL;
do {
/* shall check wait queue first then check token op queue
* to avoid to get the incorrect empty state of fg cmd
*/
q = &(obj->token_req_wait_q);
_os_spinlock(drv, &(q->lock), _bh, NULL);
if(!list_empty(&q->queue) && (q->cnt > 0)) {
is_empty = false;
_os_spinunlock(drv, &(q->lock), _bh, NULL);
break;
}
_os_spinunlock(drv, &(q->lock), _bh, NULL);
if (pq_get_front(drv, &(obj->token_op_q), &node, _bh) == true ||
_os_atomic_read(drv, &(obj->token_cnt)) > 0) {
is_empty = false;
break;
}
} while(false);
return is_empty;
}
enum rtw_phl_status dispr_process_token_req(struct cmd_dispatcher *obj)
{
void *d = phl_to_drvpriv(obj->phl_info);
struct phl_cmd_token_req_ex *ex = NULL;
do {
if (!TEST_STATUS_FLAG(obj->status, DISPR_STARTED))
return RTW_PHL_STATUS_UNEXPECTED_ERROR;
if (TEST_STATUS_FLAG(obj->status, DISPR_SHALL_STOP)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s: dispr shall stop\n", __FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
if (_os_atomic_read(d, &(obj->token_cnt)) > 0)
return RTW_PHL_STATUS_FAILURE;
if (TEST_STATUS_FLAG(obj->status, DISPR_WAIT_ABORT_MSG_DONE)) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_,
"%s, wait for abort msg sent from prev req finish before register next req \n", __FUNCTION__);
return RTW_PHL_STATUS_FAILURE;
}
if (pop_front_wait_req(obj, &ex) == false) {
if (!TEST_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE)) {
SET_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE);
send_bk_msg_phy_idle(obj);
}
return RTW_PHL_STATUS_SUCCESS;
}
if (TEST_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE)) {
CLEAR_STATUS_FLAG(obj->status, DISPR_NOTIFY_IDLE);
send_bk_msg_phy_on(obj);
}
}while(!register_cur_cmd_req(obj, ex));
return RTW_PHL_STATUS_SUCCESS;
}
void dispr_share_thread_loop_hdl(void *dispr)
{
dispr_thread_loop_hdl( (struct cmd_dispatcher *)dispr);
}
void dispr_share_thread_leave_hdl(void *dispr)
{
dispr_thread_leave_hdl((struct cmd_dispatcher *)dispr);
}
void dispr_share_thread_stop_prior_hdl(void *dispr)
{
dispr_thread_stop_prior_hdl((struct cmd_dispatcher *)dispr);
}
void dispr_share_thread_stop_post_hdl(void *dispr)
{
dispr_thread_stop_post_hdl((struct cmd_dispatcher *)dispr);
}
u8 disp_query_mdl_id(struct phl_info_t *phl, void *bk_mdl)
{
struct phl_bk_module *mdl = NULL;
if (bk_mdl != NULL) {
mdl = (struct phl_bk_module *)bk_mdl;
return mdl->id;
} else {
return PHL_MDL_ID_MAX;
}
}
void send_bk_msg_phy_on(struct cmd_dispatcher *obj)
{
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PHY_ON);
dispr_send_msg((void*)obj, &msg, &attr, NULL);
}
void send_bk_msg_phy_idle(struct cmd_dispatcher *obj)
{
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PHY_IDLE);
dispr_send_msg((void*)obj, &msg, &attr, NULL);
}
enum rtw_phl_status send_dev_io_status_change(struct cmd_dispatcher *obj, u8 allow_io)
{
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
u16 event = (allow_io == true) ? (MSG_EVT_DEV_RESUME_IO) : (MSG_EVT_DEV_CANNOT_IO);
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, event);
return dispr_send_msg((void*)obj, &msg, &attr, NULL);
}
#ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ
enum phl_mdl_ret_code loop_through_map(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex,
enum phl_bk_module_priority priority, struct msg_notify_map *map, u8 pre_prot_phase)
{
u8 i = 0;
struct phl_bk_module *mdl = NULL;
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
u8 *bitmap = (pre_prot_phase == true) ? (ex->premap) : (ex->postmap);
for (i = 0 ; i < map->len; i++) {
if (map->id_arr[i] >= PHL_FG_MDL_START) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_WARNING_,
"%s, cmd req does not take precedence over bk module\n", __FUNCTION__);
continue;
}
mdl = (struct phl_bk_module *)GET_MDL_HANDLE(obj, map->id_arr[i]);
if (mdl == NULL || !_chk_bitmap_bit(bitmap, mdl->id))
continue;
/*only allow sequence rearrange for modules at the same priority*/
if ( _get_mdl_priority(mdl->id) != priority)
continue;
ret = feed_mdl_msg(obj, mdl, ex);
if (STOP_DISPATCH_MSG(ret))
return ret;
}
return ret;
}
static enum phl_mdl_ret_code run_self_def_seq(struct cmd_dispatcher *obj, struct phl_dispr_msg_ex *ex,
enum phl_bk_module_priority priority, u8 pre_prot_phase)
{
struct msg_notify_map *map = NULL;
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct msg_dispatch_seq* seq = NULL;
if (ex->attr == NULL)
return ret;
/*MANDATORY modules cannot change dispatch order*/
if (pre_prot_phase == true)
seq = &(ex->attr->self_def_seq.pre_prot_phase);
else
seq = &(ex->attr->self_def_seq.post_prot_phase);
return loop_through_map(obj, ex, priority, &(seq->map[priority]), pre_prot_phase);
}
void reset_self_def_seq(void *d, struct msg_self_def_seq* self_def_seq)
{
u8 i = 0;
u8 cnt = 0;
struct msg_dispatch_seq *seq = (struct msg_dispatch_seq *)self_def_seq;
while (cnt++ < 2) {
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
if (seq->map[i].len)
_os_kmem_free(d, seq->map[i].id_arr, seq->map[i].len);
seq->map[i].id_arr = NULL;
seq->map[i].len = 0;
}
seq++;
}
}
u8 copy_self_def_seq(void *d, struct msg_self_def_seq* self_def_dest, struct msg_self_def_seq* self_def_src)
{
u8 i = 0;
u8 cnt = 0;
struct msg_dispatch_seq *dest = (struct msg_dispatch_seq *)self_def_dest;
struct msg_dispatch_seq *src = (struct msg_dispatch_seq *)self_def_src;
while (cnt++ < 2) {
for (i = 0; i < PHL_MDL_PRI_MAX; i++) {
if (src->map[i].len) {
dest->map[i].id_arr = _os_kmem_alloc(d, src->map[i].len);
if (dest->map[i].id_arr == NULL)
return false;
dest->map[i].len = src->map[i].len;
_os_mem_cpy(d, dest->map[i].id_arr, src->map[i].id_arr, dest->map[i].len);
}
}
dest++;
src++;
}
return true;
}
inline static u8 alloc_dispr_attr(void *d, struct phl_msg_attribute *attr)
{
if (attr->dispr_attr == NULL)
attr->dispr_attr = _os_kmem_alloc(d, sizeof(struct dispr_msg_attr));
if (attr->dispr_attr != NULL)
_os_mem_set(d, attr->dispr_attr, sizeof(struct dispr_msg_attr));
return (attr->dispr_attr == NULL) ? (false) : (true);
}
enum rtw_phl_status dispr_set_dispatch_seq(void *dispr, struct phl_msg_attribute *attr,
struct msg_self_def_seq* seq)
{
struct cmd_dispatcher *obj = (struct cmd_dispatcher *)dispr;
void *d = phl_to_drvpriv(obj->phl_info);
struct dispr_msg_attr *dispr_attr = NULL;
if (attr == NULL || seq == NULL)
return RTW_PHL_STATUS_INVALID_PARAM;
if (alloc_dispr_attr(d, attr) == false)
goto err_attr_alloc;
dispr_attr = attr->dispr_attr;
reset_self_def_seq(d, &(dispr_attr->self_def_seq));
if (copy_self_def_seq(d, &(dispr_attr->self_def_seq), seq) == false)
goto err_seq_copy;
return RTW_PHL_STATUS_SUCCESS;
err_seq_copy:
free_dispr_attr(d, &(attr->dispr_attr));
err_attr_alloc:
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_WARNING_,
"%s, err\n", __FUNCTION__);
return RTW_PHL_STATUS_RESOURCE;
}
static void free_dispr_attr(void *d, struct dispr_msg_attr **dispr_attr)
{
struct dispr_msg_attr *attr = NULL;
if (dispr_attr == NULL || *dispr_attr == NULL)
return;
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "%s\n", __FUNCTION__);
attr = *dispr_attr;
reset_self_def_seq(d, &(attr->self_def_seq));
_os_kmem_free(d, attr, sizeof(struct dispr_msg_attr));
*dispr_attr = NULL;
}
#endif
#endif
|
2301_81045437/rtl8852be
|
phl/phl_cmd_dispatcher.c
|
C
|
agpl-3.0
| 76,361
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CMD_DISPR_CONTROLLER_C_
#include "phl_headers.h"
#ifdef CONFIG_CMD_DISP
struct cmd_controller {
struct phl_info_t *phl_info;
u32 mon_mdl_id; /* monitor module id */
bool mon_mdl;
};
/* Each dispr has a controller.
* A dispr controller is designed for phl instance to interact with dispr modules that are belonged to a specific hw band,
* phl instance can perform follwing actions via dedicated controller:
* 1. allow (phl status/non-dispr phl modules) to monitor & drop msg
* 2. allow dispr modules, that are belonged to same dispr, to sequentially communicate with phl instance & call phl api,
* and also allow (phl status/non-dispr phl modules) to notify dispr by hw band.
* *Note*
* 1. when cmd dispatch engine is in solo thread mode (each dispr has its own dedicated thread).
* phl instance might receive msg from different dispr simutaneously and
* currently using semaphore (dispr_ctrl_sema) to prevent multi-thread condition.
* 2. when cmd dispatch engine is in share thread mode, msg from different dispr would pass to controller sequentially.
* PS:
* phl instance: means phl_info_t, which include phl mgnt status & non-dispr phl modules
* dispr modules: all existing background & foreground modules.
* non-dispr phl module : Data path (TX/Rx), etc
* phl mgnt status : stop/surprise remove/cannot io
*/
enum phl_mdl_ret_code
_dispr_resume_io_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
do {
ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_XMIT, _PHL_WARNING_,
"[DATA_CTRL] SW Tx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
phl_info->pause_tx_id, ctl.id,
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
break;
}
ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_,
"[DATA_CTRL] SW Rx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
phl_info->pause_rx_id, ctl.id,
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
break;
}
ret = MDL_RET_SUCCESS;
} while (false);
return ret;
}
enum phl_mdl_ret_code
_dispr_cannot_io_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_TRX_SW_PAUSE;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_XMIT, _PHL_WARNING_,
"[DATA_CTRL] SW T/Rx pause fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_hw_trx_rst_resume_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_HW_TRX_RST_RESUME;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] HW T/Rx reset and resume fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_hw_trx_pause_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_HW_TRX_PAUSE;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] HW T/Rx pause fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_sw_tx_resume_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
enum phl_module_id mdl_id = MSG_MDL_ID_FIELD(msg->msg_id);
/* tx pause by MDL_POWER_MGNT, tx resume by MDL_TX/MDL_RX */
if (mdl_id == PHL_MDL_TX || mdl_id == PHL_MDL_RX)
ctl.id = PHL_MDL_POWER_MGNT;
else
ctl.id = mdl_id;
ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW Tx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
phl_info->pause_tx_id, ctl.id,
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_sw_rx_resume_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
enum phl_module_id mdl_id = MSG_MDL_ID_FIELD(msg->msg_id);
/* rx pause by MDL_POWER_MGNT, rx resume by MDL_TX/MDL_RX */
if (mdl_id == PHL_MDL_TX || mdl_id == PHL_MDL_RX)
ctl.id = PHL_MDL_POWER_MGNT;
else
ctl.id = mdl_id;
ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW Rx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
phl_info->pause_rx_id, ctl.id,
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_sw_tx_pause_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW Tx pause fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_sw_rx_pause_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_SW_RX_PAUSE;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW Rx pause fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_sw_tx_reset_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_SW_TX_RESET;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW Tx reset fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_sw_rx_reset_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_SW_RX_RESET;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW Rx reset fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_trx_sw_pause_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_TRX_SW_PAUSE;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW T/Rx pause fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_trx_sw_resume_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_TRX_SW_RESUME;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW T/Rx resume fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_trx_pause_w_rst_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_TRX_PAUSE_W_RST;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW T/Rx pause with reset fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_trx_resume_w_rst_ctrl(struct phl_info_t *phl_info,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.cmd = PHL_DATA_CTL_TRX_RESUME_W_RST;
ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
sts = phl_data_ctrler(phl_info, &ctl, msg);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"[DATA_CTRL] SW T/Rx resume with reset fail by module(%d) with event(%d)\n",
ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_mdl_stop_ctrl(struct phl_info_t *phl_info,
struct cmd_controller *cmd_ctrl)
{
if (cmd_ctrl->mon_mdl_id != 0) {
cmd_ctrl->mon_mdl = true;
return MDL_RET_PENDING;
} else {
return MDL_RET_SUCCESS;
}
}
enum phl_mdl_ret_code
_dispr_ctrl_init(void *phl,
void *dispr,
void **priv)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct cmd_controller *cmd_ctrl = NULL;
void *drv = phl_to_drvpriv(phl_info);
PHL_INFO("%s(): \n", __func__);
(*priv) = NULL;
cmd_ctrl = (struct cmd_controller *)_os_mem_alloc(drv,
sizeof(struct cmd_controller));
if (cmd_ctrl == NULL) {
PHL_ERR(" %s, alloc fail\n",__FUNCTION__);
return MDL_RET_FAIL;
}
cmd_ctrl->phl_info = phl_info;
(*priv) = (void*)cmd_ctrl;
return MDL_RET_SUCCESS;
}
void _dispr_ctrl_deinit(void *dispr, void *priv)
{
struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv;
void *drv = phl_to_drvpriv(cmd_ctrl->phl_info);
_os_mem_free(drv, cmd_ctrl, sizeof(struct cmd_controller));
PHL_INFO("%s(): \n", __func__);
}
enum phl_mdl_ret_code _dispr_ctrl_start(void *dispr, void *priv)
{
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv;
struct phl_info_t *phl_info = (struct phl_info_t *)cmd_ctrl->phl_info;
void *drv = phl_to_drvpriv(cmd_ctrl->phl_info);
PHL_INFO("%s(): \n", __func__);
_os_mem_set(drv, cmd_ctrl, 0, sizeof(struct cmd_controller));
cmd_ctrl->phl_info = phl_info;
return ret;
}
enum phl_mdl_ret_code _dispr_ctrl_stop(void *dispr, void *priv)
{
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
PHL_INFO("%s(): \n", __func__);
return ret;
}
static void _fail_hdlr(void *dispr, struct phl_info_t *phl_info, struct phl_msg *msg)
{
}
static enum phl_mdl_ret_code
_ctrler_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_DEV_RESUME_IO:
ret = _dispr_resume_io_ctrl(phl_info, msg);
break;
case MSG_EVT_DEV_CANNOT_IO:
ret = _dispr_cannot_io_ctrl(phl_info, msg);
break;
default:
break;
}
return ret;
}
static enum phl_mdl_ret_code
_tx_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_TRX_PWR_REQ:
/* ps module handle MSG_EVT_TRX_PWR_REQ itself */
default:
break;
}
return ret;
}
static enum phl_mdl_ret_code
_rx_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_TRX_PWR_REQ:
/* ps module handle MSG_EVT_TRX_PWR_REQ itself */
default:
break;
}
return ret;
}
static void _mon_msg_hdlr(struct cmd_controller *cmd_ctrl,
struct phl_msg *msg)
{
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_SER_L0_RESET:
case MSG_EVT_SER_M1_PAUSE_TRX:
case MSG_EVT_SER_M3_DO_RECOV:
cmd_ctrl->mon_mdl_id = PHL_MDL_SER;
break;
case MSG_EVT_SER_M5_READY:
cmd_ctrl->mon_mdl_id = 0;
if (cmd_ctrl->mon_mdl)
phl_disp_eng_clr_pending_msg(cmd_ctrl->phl_info, msg->band_idx);
cmd_ctrl->mon_mdl = false;
break;
}
}
static enum phl_mdl_ret_code _internal_msg_hdlr(void *dispr,
struct cmd_controller *cmd_ctrl, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct phl_info_t *phl_info = cmd_ctrl->phl_info;
/* sender is controller itself */
if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_PHY_MGNT) {
ret = _ctrler_msg_hdlr(phl_info, msg);
} else if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_TX) {
ret = _tx_msg_hdlr(phl_info, msg);
} else if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_RX) {
ret = _rx_msg_hdlr(phl_info, msg);
}
return ret;
}
static enum phl_mdl_ret_code
_external_msg_hdlr(void *dispr,
struct cmd_controller *cmd_ctrl, struct phl_msg *msg)
{
struct phl_info_t *phl_info = cmd_ctrl->phl_info;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
if (phl_com->dev_state & RTW_DEV_RESUMING) {
PHL_WARN("Controller: MDL_ID(%d)-EVT_ID(%d) is sent during RTW_DEV_RESUMING!\n",
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
}
if (phl_com->dev_state & RTW_DEV_SURPRISE_REMOVAL) {
PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "Controller: msg fail due to invalid device state\n");
return MDL_RET_FAIL;
}
_mon_msg_hdlr(cmd_ctrl, msg);
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_HW_TRX_RST_RESUME:
ret = _dispr_hw_trx_rst_resume_ctrl(phl_info, msg);
break;
case MSG_EVT_HW_TRX_PAUSE:
ret = _dispr_hw_trx_pause_ctrl(phl_info, msg);
break;
case MSG_EVT_SW_TX_RESUME:
ret = _dispr_sw_tx_resume_ctrl(phl_info, msg);
break;
case MSG_EVT_SW_RX_RESUME:
ret = _dispr_sw_rx_resume_ctrl(phl_info, msg);
break;
case MSG_EVT_SW_TX_PAUSE:
ret = _dispr_sw_tx_pause_ctrl(phl_info, msg);
break;
case MSG_EVT_SW_RX_PAUSE:
ret = _dispr_sw_rx_pause_ctrl(phl_info, msg);
break;
case MSG_EVT_SW_TX_RESET:
ret = _dispr_sw_tx_reset_ctrl(phl_info, msg);
break;
case MSG_EVT_SW_RX_RESET:
ret = _dispr_sw_rx_reset_ctrl(phl_info, msg);
break;
case MSG_EVT_TRX_SW_PAUSE:
ret = _dispr_trx_sw_pause_ctrl(phl_info, msg);
break;
case MSG_EVT_TRX_SW_RESUME:
ret = _dispr_trx_sw_resume_ctrl(phl_info, msg);
break;
case MSG_EVT_TRX_PAUSE_W_RST:
ret = _dispr_trx_pause_w_rst_ctrl(phl_info, msg);
break;
case MSG_EVT_TRX_RESUME_W_RST:
ret = _dispr_trx_resume_w_rst_ctrl(phl_info, msg);
break;
case MSG_EVT_MDL_CHECK_STOP:
ret = _dispr_mdl_stop_ctrl(phl_info, cmd_ctrl);
break;
default:
break;
}
return ret;
}
enum phl_mdl_ret_code
_dispr_ctrl_msg_hdlr(void *dispr,
void *priv,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv;
FUNCIN();
if (IS_MSG_FAIL(msg->msg_id)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"%s: cmd dispatcher notify cmd failure: 0x%x.\n",
__FUNCTION__, msg->msg_id);
_fail_hdlr(dispr, cmd_ctrl->phl_info, msg);
FUNCOUT();
return MDL_RET_FAIL;
}
if (IS_DISPR_CTRL(MSG_MDL_ID_FIELD(msg->msg_id)))
ret = _internal_msg_hdlr(dispr, cmd_ctrl, msg);
else
ret = _external_msg_hdlr(dispr, cmd_ctrl, msg);
FUNCOUT();
return ret;
}
enum phl_mdl_ret_code
_dispr_ctrl_set_info(void *dispr,
void *priv,
struct phl_module_op_info *info)
{
PHL_INFO("%s(): \n", __func__);
return MDL_RET_IGNORE;
}
enum phl_mdl_ret_code
_dispr_ctrl_query_info(void *dispr, void *priv,
struct phl_module_op_info *info)
{
PHL_INFO("%s(): \n", __func__);
return MDL_RET_IGNORE;
}
void dispr_ctrl_hook_ops(void *dispr, struct phl_bk_module_ops *ops)
{
if (ops == NULL)
return;
ops->init = _dispr_ctrl_init;
ops->deinit = _dispr_ctrl_deinit;
ops->start = _dispr_ctrl_start;
ops->stop = _dispr_ctrl_stop;
ops->msg_hdlr = _dispr_ctrl_msg_hdlr;
ops->set_info = _dispr_ctrl_set_info;
ops->query_info = _dispr_ctrl_query_info;
}
#endif
|
2301_81045437/rtl8852be
|
phl/phl_cmd_dispr_controller.c
|
C
|
agpl-3.0
| 19,509
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* Author: vincent_fann@realtek.com
*
*****************************************************************************/
#include "phl_headers.h"
#ifdef CONFIG_FSM
/* #define DEBUG_CMD_FSM_MODULE */
#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y))
#ifdef FSM_DBG_MEM_OVERWRITE
#define _os_kmem_alloc(a, b) fsm_kmalloc(b)
#define _os_kmem_free(a, b, c) fsm_kfree(b, c)
#endif
#define pstr(s) (s +_os_strlen((u8 *)s))
#define lstr(s, l) (size_t)(l - _os_strlen((u8 *)s))
#ifdef CONFIG_RTW_SCAN_FSM
struct _adapter;
#endif
#define MAX_POWER_ON_TIME 100
#define WDOG_ALARM_ID 1
#define WD_DURATION 2000 /* 2sec */
enum CMD_STATE_ST {
CMD_ST_IDLE,
CMD_ST_REQ_PWR,
CMD_ST_SERVICE
};
enum CMD_EV_ID {
CMD_EV_REQ_PWR,
CMD_EV_DO_JOB,
CMD_EV_JOB_NOTIFY,
CMD_EV_PWR_ON_OK,
CMD_EV_PWR_ON_TIMEOUT,
CMD_EV_PWR_EXPIRE,
CMD_EV_WD_EXPIRE,
CMD_EV_WD_DO_JOB,
CMD_EV_MAX
};
static int cmd_idle_st_hdl(void *obj, u16 event, void *param);
static int cmd_req_pwr_st_hdl(void *obj, u16 event, void *param);
static int cmd_service_st_hdl(void *obj, u16 event, void *param);
/* STATE table */
static struct fsm_state_ent cmd_state_tbl[] = {
ST_ENT(CMD_ST_IDLE, cmd_idle_st_hdl),
ST_ENT(CMD_ST_REQ_PWR, cmd_req_pwr_st_hdl),
ST_ENT(CMD_ST_SERVICE, cmd_service_st_hdl),
};
/* EVENT table */
static struct fsm_event_ent cmd_event_tbl[] = {
EV_ENT(CMD_EV_REQ_PWR),
EV_ENT(CMD_EV_DO_JOB),
EV_ENT(CMD_EV_JOB_NOTIFY),
EV_ENT(CMD_EV_PWR_ON_OK),
EV_ENT(CMD_EV_PWR_ON_TIMEOUT),
EV_ENT(CMD_EV_PWR_EXPIRE),
EV_DBG(CMD_EV_WD_EXPIRE),
EV_ENT(CMD_EV_WD_DO_JOB),
EV_ENT(CMD_EV_MAX) /* EV_MAX for fsm safety checking */
};
/*
* command thread state sub function
*/
void cmd_pm_cb(void *phl, void *hdl, void *ctx, enum rtw_phl_status stat)
{
struct _cmd_obj *pcmd = (struct _cmd_obj *)ctx;
if (stat == RTW_PHL_STATUS_SUCCESS)
phl_fsm_gen_msg(phl, pcmd->fsm_obj, NULL, 0, CMD_EV_PWR_ON_OK);
else
phl_fsm_gen_msg(phl, pcmd->fsm_obj, NULL, 0, FSM_EV_CANCEL);
}
int cmd_dequeue_job(struct _cmd_obj *pcmd)
{
void *d = phl_to_drvpriv(pcmd->phl_info);
struct fsm_msg *msg;
msg = phl_fsm_dequeue_ext(pcmd->fsm);
if (msg == NULL)
return -1;
if (phl_fsm_sent_msg(pcmd->fsm_obj, msg) != RTW_PHL_STATUS_SUCCESS) {
if (msg->param && msg->param_sz)
_os_kmem_free(d, (u8 *)msg->param, msg->param_sz);
_os_kmem_free(d, (u8 *)msg, sizeof(*msg));
return -1;
}
return 0;
}
static void cmd_do_wdog_job(struct _cmd_obj *pcmd)
{
#if defined(PHL_PLATFORM_LINUX)
void *d = phl_to_drvpriv(pcmd->phl_info);
struct phl_cmd_job *job;
/* Tempoary test in Linux,
* make sure Windows doesn't run to here
*/
_os_mutex_lock(d, &pcmd->wd_q_lock);
phl_list_for_loop(job, struct phl_cmd_job, &pcmd->wd_q, list) {
job->u.cmd.fptr(job->u.cmd.priv, job->u.cmd.parm, false);
#ifdef DEBUG_CMD_FSM_MODULE
FSM_INFO(pcmd->fsm, "%s: wdog %s:%s\n",
phl_fsm_obj_name(pcmd->fsm_obj),
job_name(pcmd, (u8)job->id),
(char *)job->u.cmd.name);
#endif
}
_os_mutex_unlock(d, &pcmd->wd_q_lock);
rtw_phl_watchdog_callback(pcmd->phl_info);
#endif
}
static void cmd_add_wdog_event(struct _cmd_obj *pcmd)
{
struct fsm_msg *msg;
msg = phl_fsm_new_msg(pcmd->fsm_obj, CMD_EV_WD_DO_JOB);
if (msg == NULL)
return;
/* Always enqueue msg to extra queue */
phl_fsm_enqueue_ext(pcmd->fsm, msg, 0);
}
/*
* CMD state handler
*/
/*
* cmd idle handler
* This state has no power; Able to run no_io job
* For jobs don't need to request power (no_io job)
*/
static int cmd_idle_st_hdl(void *obj, u16 event, void *param)
{
struct _cmd_obj *pcmd = (struct _cmd_obj *)obj;
int rtn = FSM_FREE_PARAM;
/* has no power */
switch (event) {
case FSM_EV_SWITCH_IN:
phl_fsm_set_alarm_ext(pcmd->fsm_obj,
WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL);
break;
case FSM_EV_STATE_IN:
break;
case CMD_EV_WD_EXPIRE:
/* restart watchdog alarm */
phl_fsm_set_alarm_ext(pcmd->fsm_obj,
WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL);
if (pcmd->wdog_pwr_level < PWR_BASIC_IO) {
cmd_do_wdog_job(pcmd);
break;
}
/* We need to request power */
cmd_add_wdog_event(pcmd);
/* fall through */
case CMD_EV_REQ_PWR:
phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_REQ_PWR);
break;
case CMD_EV_JOB_NOTIFY:
cmd_dequeue_job(pcmd);
break;
case CMD_EV_DO_JOB:
/* TODO check MUST BE no_io cmd */
rtn = phl_cmd_do_job(pcmd, param);
break;
case FSM_EV_STATE_OUT:
break;
case FSM_EV_SWITCH_OUT:
phl_fsm_cancel_alarm_ext(pcmd->fsm_obj, WDOG_ALARM_ID);
break;
default:
break;
}
return rtn;
}
/* This stete is designed to request power */
static int cmd_req_pwr_st_hdl(void *obj, u16 event, void *param)
{
struct _cmd_obj *pcmd = (struct _cmd_obj *)obj;
struct fsm_msg *msg;
int rtn = FSM_FREE_PARAM;
enum rtw_phl_status phl_st;
switch (event) {
case FSM_EV_STATE_IN:
/* TODO: request power */
phl_st = RTW_PHL_STATUS_SUCCESS;
if (phl_st == RTW_PHL_STATUS_PENDING) {
/* we have to wait CMD_EV_PWR_ON_OK */
phl_fsm_set_alarm(pcmd->fsm_obj,
MAX_POWER_ON_TIME, CMD_EV_PWR_ON_TIMEOUT);
break;
}
if (phl_st != RTW_PHL_STATUS_SUCCESS) {
FSM_ERR(pcmd->fsm, "%s: power on fail(%d)\n",
phl_fsm_obj_name(pcmd->fsm_obj), phl_st);
phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_IDLE);
/* drop fail cmd */
msg = phl_fsm_dequeue_ext(pcmd->fsm);
if (msg != NULL)
cmd_discard_msg_job(pcmd, msg);
break;
}
/* RTW_PHL_STATUS_SUCCESS */
/* fall through */
case CMD_EV_PWR_ON_OK:
pcmd->has_power = true;
phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_SERVICE);
break;
case CMD_EV_PWR_ON_TIMEOUT:
case FSM_EV_CANCEL:
phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_IDLE);
break;
case CMD_EV_WD_EXPIRE:
/* restart watchdog alarm */
phl_fsm_set_alarm_ext(pcmd->fsm_obj,
WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL);
/* enqueue watchdog job */
cmd_add_wdog_event(pcmd);
break;
case FSM_EV_STATE_OUT:
phl_fsm_cancel_alarm(pcmd->fsm_obj);
break;
default:
break;
}
return rtn;
}
/* This state has basic power supply.
* Able to do both PWR_BASIC_IO and PWR_NO_IO jobs.
*/
static int cmd_service_st_hdl(void *obj, u16 event, void *param)
{
struct _cmd_obj *pcmd = (struct _cmd_obj *)obj;
struct phl_cmd_job *job;
int rtn = FSM_FREE_PARAM;
switch (event) {
case FSM_EV_STATE_IN:
case CMD_EV_JOB_NOTIFY:
cmd_dequeue_job(pcmd);
break;
case CMD_EV_DO_JOB:
rtn = phl_cmd_do_job(pcmd, param);
/* hold power for a while */
job = (struct phl_cmd_job *)param;
if (job->pwr_level >= PWR_BASIC_IO)
phl_fsm_set_alarm(pcmd->fsm_obj,
MAX_POWER_ON_TIME, CMD_EV_PWR_EXPIRE);
/* dequeue jobs */
cmd_dequeue_job(pcmd);
break;
case CMD_EV_WD_EXPIRE:
case CMD_EV_WD_DO_JOB:
cmd_do_wdog_job(pcmd);
/* hold power for a while */
phl_fsm_set_alarm(pcmd->fsm_obj,
MAX_POWER_ON_TIME, CMD_EV_PWR_EXPIRE);
/* restart watchdog alarm */
phl_fsm_set_alarm_ext(pcmd->fsm_obj,
WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL);
break;
case CMD_EV_PWR_EXPIRE:
/* make sure no more commands */
if (cmd_dequeue_job(pcmd) >= 0)
break;
/* no more commands */
/* fall through */
case FSM_EV_CANCEL:
phl_fsm_state_goto(pcmd->fsm_obj, CMD_ST_IDLE);
break;
case FSM_EV_STATE_OUT:
phl_fsm_cancel_alarm(pcmd->fsm_obj);
pcmd->has_power = false;
break;
default:
break;
}
return rtn;
}
static void cmd_dump_obj(void *obj, char *p, int *sz)
{
/* nothing to do for now */
}
static void cmd_dump_fsm(void *fsm, char *p, int *sz)
{
/* nothing to do for now */
}
static void cmd_dbg_help(struct _cmd_obj *pcmd, char *p, int *sz)
{
int len = *sz;
_os_snprintf(pstr(p), lstr(p, len),
"usage:\n\t<%s> <wdog>,<pause|resume>\n",
phl_fsm_obj_name(pcmd->fsm_obj));
*sz = len;
}
static void cmd_debug(void *obj, char input[][MAX_ARGV], u32 input_num,
char *output, u32 *out_len)
{
struct _cmd_obj *pcmd = (struct _cmd_obj *)obj;
char *ptr = output;
int len = *out_len;
if (input_num < 2) {
cmd_dbg_help(pcmd, ptr, &len);
goto done;
}
if (!_os_strcmp(input[0], "wdog")) {
if (!_os_strcmp(input[1], "pause")) {
/* wdog,pause */
rtw_phl_cmd_pause_wdog(pcmd->phl_info, "debug cmd");
_os_snprintf(pstr(ptr), lstr(ptr, len),
"\n%s: pause watchdog\n",
phl_fsm_obj_name(pcmd->fsm_obj));
} else if (!_os_strcmp(input[1], "resume")) {
/* wdog,resume */
rtw_phl_cmd_resume_wdog(pcmd->phl_info, "debug cmd");
_os_snprintf(pstr(ptr), lstr(ptr, len),
"\n%s: resume watchdog\n",
phl_fsm_obj_name(pcmd->fsm_obj));
}
} else
cmd_dbg_help(pcmd, ptr, &len);
done:
*out_len = len;
}
/* return value
* 0: timeout
* >0: success
*/
static int wait_completion(void *d, struct phl_cmd_job *job, int m_sec)
{
job->wait.max_wait_time = m_sec;
job->wait.submit_time = _os_get_cur_time_ms();
_os_event_init(d, &(job->wait.done));
/* wait here */
return _os_event_wait(d, &(job->wait.done), m_sec);
}
/* For EXTERNAL application to create a cmd FSM */
/* @root: FSM root structure
* @phl_info: private data structure to invoke hal/phl function
*
* return
* fsm_main: FSM main structure (Do NOT expose)
*/
struct fsm_main *phl_cmd_new_fsm(struct fsm_root *root,
struct phl_info_t *phl_info)
{
void *d = phl_to_drvpriv(phl_info);
struct fsm_main *fsm = NULL;
struct rtw_phl_fsm_tb tb;
_os_mem_set(d, &tb, 0, sizeof(tb));
tb.max_state = sizeof(cmd_state_tbl)/sizeof(cmd_state_tbl[0]);
tb.max_event = sizeof(cmd_event_tbl)/sizeof(cmd_event_tbl[0]);
tb.state_tbl = cmd_state_tbl;
tb.evt_tbl = cmd_event_tbl;
tb.dump_obj = cmd_dump_obj;
tb.dump_fsm = cmd_dump_fsm;
tb.dbg_level = FSM_DBG_WARN;
tb.evt_level = FSM_DBG_WARN;
tb.debug = cmd_debug;
fsm = phl_fsm_init_fsm(root, "cmd", phl_info, &tb);
return fsm;
}
/* For EXTERNAL application to destory cmd fsm */
/* @fsm: see fsm_main
*/
void phl_cmd_destory_fsm(struct fsm_main *fsm)
{
if (fsm == NULL)
return;
/* deinit fsm local variable if has */
/* call FSM Framewro to deinit fsm */
phl_fsm_deinit_fsm(fsm);
}
/* For EXTERNAL application to create command object */
/* @fsm: FSM main structure which created by phl_cmd_new_fsm()
* @phl_info: private data structure to invoke hal/phl function
*
* return
* _cmd_obj: structure of command object (Do NOT expose)
*/
struct _cmd_obj *phl_cmd_new_obj(struct fsm_main *fsm,
struct phl_info_t *phl_info)
{
void *d = phl_to_drvpriv(phl_info);
struct fsm_obj *obj;
struct _cmd_obj *pcmd;
pcmd = phl_fsm_new_obj(fsm, (void **)&obj, sizeof(*pcmd));
if (pcmd == NULL) {
FSM_ERR(fsm, "cmd: malloc obj fail\n");
return NULL;
}
pcmd->fsm = fsm;
pcmd->fsm_obj = obj;
pcmd->phl_info = phl_info;
pcmd->has_power = false;
cmd_set_job_tbl(pcmd);
INIT_LIST_HEAD(&pcmd->wd_q);
_os_mutex_init(d, &pcmd->wd_q_lock);
return pcmd;
}
/* For EXTERNAL application to destory command object */
/* @pcmd: local created command object
*
*/
void phl_cmd_destory_obj(struct _cmd_obj *pcmd)
{
void *d;
struct phl_cmd_job *job, *job_t;
if (pcmd == NULL)
return;
d = phl_to_drvpriv(pcmd->phl_info);
/* deinit and free all local variables */
/* watchdog job */
/* TODO spin lock is not necessary */
phl_list_for_loop_safe(job, job_t,
struct phl_cmd_job, &pcmd->wd_q, list) {
_os_mutex_lock(d, &pcmd->wd_q_lock);
list_del(&job->list);
_os_mutex_unlock(d, &pcmd->wd_q_lock);
if (job->id == JOB_RUN_FUNC) {
if (job->u.cmd.parm && job->u.cmd.parm_sz != 0)
_os_kmem_free(d, (u8 *)job->u.cmd.parm,
job->u.cmd.parm_sz);
_os_kmem_free(d, (u8 *)job, sizeof(*job));
} else {
FSM_ERR(pcmd->fsm, "%s: free wdog %s fail\n",
phl_fsm_obj_name(pcmd->fsm_obj),
job_name(pcmd, (u8)job->id));
}
}
_os_mutex_deinit(d, &pcmd->wd_q_lock);
/* inform FSM framewory to recycle fsm_obj */
phl_fsm_destory_obj(pcmd->fsm_obj);
}
/* For EXTERNAL application to pause all watchdog jobs (expose) */
/* @phl: phl private structure
* @reason: reason for pause watchdog (option)
*/
enum rtw_phl_status rtw_phl_cmd_pause_wdog(void *phl, char *reason)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct _cmd_obj *pcmd = phl_info->cmd_obj;
phl_fsm_pause_alarm_ext(pcmd->fsm_obj, WDOG_ALARM_ID);
pcmd->wdog_pause_num++;
FSM_INFO(pcmd->fsm, "%s: pause wdog (%s) %d\n",
phl_fsm_obj_name(pcmd->fsm_obj),
(reason == NULL) ? "" : reason, pcmd->wdog_pause_num);
return RTW_PHL_STATUS_SUCCESS;
}
/* For EXTERNAL application to resume all watchdog jobs (expose) */
/* @phl: phl private structure
* @reason: reason for resume watchdog (option)
*/
enum rtw_phl_status rtw_phl_cmd_resume_wdog(void *phl, char *reason)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct _cmd_obj *pcmd = phl_info->cmd_obj;
FSM_INFO(pcmd->fsm, "%s: resume wdog (%s) %d\n",
phl_fsm_obj_name(pcmd->fsm_obj),
(reason == NULL) ? "" : reason, pcmd->wdog_pause_num);
if (pcmd->wdog_pause_num == 0)
return RTW_PHL_STATUS_FAILURE;
if (--(pcmd->wdog_pause_num) != 0)
return RTW_PHL_STATUS_SUCCESS;
/* reset timer to original period */
phl_fsm_set_alarm_ext(pcmd->fsm_obj,
WD_DURATION, CMD_EV_WD_EXPIRE, WDOG_ALARM_ID, NULL);
phl_fsm_resume_alarm_ext(pcmd->fsm_obj, WDOG_ALARM_ID);
return RTW_PHL_STATUS_SUCCESS;
}
/* For EXTERNAL application to register watchdog job (expose) */
/* @phl: phl private structure
* @func: function pointer to be runed
* @priv: 1st param of function pointer
* @parm: 2nd param of function pointer
* @name: function name for debug message (optional)
* @pwr: refers to enum PWR_LEVEL
*/
enum rtw_phl_status rtw_phl_job_reg_wdog(void *phl,
int (*fptr)(void *priv, void *param, bool discard),
void *priv, void *parm, int parm_sz, char *name, enum PWR_LEVEL pwr)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct _cmd_obj *pcmd = phl_info->cmd_obj;
struct phl_cmd_job *job;
void *d = phl_to_drvpriv(phl_info);
char wd[] = "wdog";
if (phl_info->cmd_obj == NULL) {
PHL_ERR("cmd: %s fsm module doesn't init \n", __func__);
return -1;
}
/* allocate memory for job parameter */
job = _os_kmem_alloc(d, sizeof(*job));
if (job == NULL) {
FSM_ERR(pcmd->fsm, "%s: alloc wdog job fail\n",
phl_fsm_obj_name(pcmd->fsm_obj));
return RTW_PHL_STATUS_RESOURCE;
}
_os_mem_set(d, job, 0, sizeof(job));
job->id = JOB_RUN_FUNC;
job->pwr_level = pwr;
job->u.cmd.fptr = fptr;
job->u.cmd.priv = priv;
job->u.cmd.parm = parm;
job->u.cmd.parm_sz = parm_sz;
_os_mem_set(d, job->u.cmd.name, 0, RTW_PHL_JOB_NAME_LEN);
if (name != NULL)
_os_mem_cpy(d, job->u.cmd.name, name,
MIN((RTW_PHL_JOB_NAME_LEN - 1),
_os_strlen((u8 *)name)));
else
_os_mem_cpy(d, job->u.cmd.name, wd,
MIN((RTW_PHL_JOB_NAME_LEN - 1),
_os_strlen((u8 *)wd)));
pcmd->wdog_pwr_level = (u8)MAX(pwr, pcmd->wdog_pwr_level);
_os_mutex_lock(d, &pcmd->wd_q_lock);
list_add_tail(&job->list, &pcmd->wd_q);
_os_mutex_unlock(d, &pcmd->wd_q_lock);
FSM_INFO(pcmd->fsm, "%s: wdog hooks %s, pwr_level = %d\n",
phl_fsm_obj_name(pcmd->fsm_obj),
job->u.cmd.name, pwr);
return RTW_PHL_STATUS_SUCCESS;
}
/* For EXTERNAL application to invoke command service (expose) */
/* @pcmd: cmd object
* @msg: refert to struct fsm_msg
*/
enum rtw_phl_status phl_cmd_enqueue_and_wait_job(struct _cmd_obj *pcmd,
struct fsm_msg *msg)
{
struct phl_cmd_job *job = (struct phl_cmd_job *)msg->param;
void *d = phl_to_drvpriv(pcmd->phl_info);
int max_wait_time = 1000;
int remain = 0;
#if 0
FSM_INFO(pcmd->fsm, "%s: enqueue %s:%s\n",
phl_fsm_obj_name(pcmd->fsm_obj),
job_name(pcmd, (u8)job->id), (char *)job->u.cmd.name);
#endif
/* Always enqueue msg to extra queue */
phl_fsm_enqueue_ext(pcmd->fsm, msg, 0);
if ((pcmd->has_power == false) && (job->pwr_level >= PWR_BASIC_IO))
/* request power */
phl_fsm_gen_msg(pcmd->phl_info,
pcmd->fsm_obj, NULL, 0, CMD_EV_REQ_PWR);
else
phl_fsm_gen_msg(pcmd->phl_info,
pcmd->fsm_obj, NULL, 0, CMD_EV_JOB_NOTIFY);
if (job->wait.sync == JOB_WAIT_COMPLETION) {
job->wait.result = JOB_SUCCESS;
/* WAIT completion; context switch */
remain = wait_completion(d, job, max_wait_time);
if (remain == 0) {
job->wait.result = JOB_TIMEOUT;
FSM_WARN(pcmd->fsm, "job: %s timeout %d ms\n",
job_name(pcmd, (u8)job->id), max_wait_time);
return RTW_PHL_STATUS_FAILURE;
}
}
return RTW_PHL_STATUS_SUCCESS;
}
/* For EXTERNAL application to invoke command service (expose) */
/* @phl: refer to struct phl_info_t
* @pjob: job to be completed
*/
enum rtw_phl_status phl_cmd_complete_job(void *phl, struct phl_cmd_job *pjob)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct _cmd_obj *pcmd = phl_info->cmd_obj;
struct phl_cmd_job *job;
struct fsm_msg *msg;
void *d = phl_to_drvpriv(pcmd->phl_info);
if (pjob == NULL)
return RTW_PHL_STATUS_FAILURE;
#ifdef HAS_NO_COMPLETION
if (pjob->wait.sync == JOB_WAIT_COMPLETION) {
pjob->wait.sync = JOB_ASYNC;
FSM_ERR(pcmd->fsm,
"cmd: %s doesn't support SYNC mdoe use ASYNC mode\n",
job_name(pcmd, (u8)pjob->id));
}
#endif
/* NEW message to start cmd service */
msg = phl_fsm_new_msg(pcmd->fsm_obj, CMD_EV_DO_JOB);
if (msg == NULL) {
FSM_ERR(pcmd->fsm, "cmd: alloc msg fail\n");
return RTW_PHL_STATUS_RESOURCE;
}
/* allocate memory for command parameter */
if (pjob->wait.sync == JOB_WAIT_COMPLETION) {
/* TODO check interrupt context */
/* SYNC mode, use call loacl job varable */
job = pjob;
} else {
/* ASYNC mode */
/* allocate memory for command parameter */
job = _os_kmem_alloc(d, sizeof(*job));
if (job == NULL) {
FSM_ERR(pcmd->fsm, "cmd: alloc job fail\n");
_os_kmem_free(d, (u8 *)msg, sizeof(*msg));
return RTW_PHL_STATUS_RESOURCE;
}
_os_mem_cpy(d, job, pjob, sizeof(*job));
}
msg->param = (void *)job;
msg->param_sz = sizeof(*job);
return phl_cmd_enqueue_and_wait_job(pcmd, msg);
}
/* For EXTERNAL application to start command service (expose) */
/* @pcmd: cmd object
*/
enum rtw_phl_status phl_cmd_start(struct _cmd_obj *pcmd)
{
/* Start FSM */
return phl_fsm_start_fsm(pcmd->fsm);
}
/* For EXTERNAL application to stop cmd obj
* @phl_info: private data structure to invoke hal/phl function
*
*/
void phl_fsm_cmd_stop(struct phl_info_t *phl_info)
{
struct _cmd_obj *pcmd = phl_info->cmd_obj;
//void *d = phl_to_drvpriv(pcmd->phl_info);
struct phl_cmd_job *job;
struct fsm_msg *msg;
while ((msg = phl_fsm_dequeue_ext(pcmd->fsm)) != NULL) {
job = (struct phl_cmd_job *)msg->param;
cmd_discard_msg_job(pcmd, msg);
}
phl_fsm_stop_fsm(phl_info->cmd_fsm);
}
/* For EXTERNAL application to stop cmd service (expose) */
/* @pcmd: cmd job will be cancelled
*/
enum rtw_phl_status phl_cmd_cancel(struct _cmd_obj *pcmd)
{
#ifdef PHL_INCLUDE_FSM
return phl_fsm_cancel_obj(pcmd->fsm_obj);
#else
return RTW_PHL_STATUS_FAILURE;
#endif /* PHL_INCLUDE_FSM */
}
#endif /*CONFIG_FSM*/
|
2301_81045437/rtl8852be
|
phl/phl_cmd_fsm.c
|
C
|
agpl-3.0
| 19,445
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHL_CMD_FSM_H__
#define __PHL_CMD_FSM_H__
#include "phl_cmd_job.h"
/* Header file for application to invoke command service */
struct phl_cmd_job;
struct job_hdl_ent;
struct fsm_root;
struct fsm_main;
struct _cmd_obj;
struct _cmd_obj {
struct fsm_main *fsm;
struct phl_info_t *phl_info;
struct fsm_obj *fsm_obj;
struct job_hdl_ent *job_tbl;
u8 wdog_pwr_level;
u32 wdog_pause_num;
bool has_power;
struct list_head wd_q;
_os_mutex wd_q_lock;
};
/* function form command service management */
struct fsm_main *phl_cmd_new_fsm(struct fsm_root *fsm_m,
struct phl_info_t *phl_info);
void phl_cmd_destory_fsm(struct fsm_main *fsm);
struct _cmd_obj *phl_cmd_new_obj(struct fsm_main *fsm,
struct phl_info_t *phl_info);
void phl_cmd_destory_obj(struct _cmd_obj *pcmd);
void phl_fsm_cmd_stop(struct phl_info_t *phl_info);
/* function form command service */
enum rtw_phl_status phl_cmd_start(struct _cmd_obj *pcmd);
enum rtw_phl_status phl_cmd_cancel(struct _cmd_obj *pcmd);
#endif /* __PHL_CMD_FSM_H__ */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_fsm.h
|
C
|
agpl-3.0
| 1,682
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CMD_GENERAL_C_
#include "phl_headers.h"
#ifdef CONFIG_CMD_DISP
enum phl_cmd_sts {
PHL_CMD_SUBMITTED = -1,
PHL_CMD_DONE_SUCCESS = 0,
PHL_CMD_DONE_TIMEOUT,
PHL_CMD_DONE_CMD_ERROR,
PHL_CMD_DONE_CMD_DROP,
PHL_CMD_DONE_CANNOT_IO,
PHL_CMD_DONE_UNKNOWN,
};
struct phl_sync {
u32 submit_time;
u32 timeout_ms; /* 0: wait forever, >0: up to ms waiting */
enum phl_cmd_sts status; /* status for operation */
_os_event done;
};
struct phl_cmd_sync {
enum phl_msg_evt_id evt_id;
struct phl_sync sync;
_os_lock lock;
};
struct phl_cmd_obj {
enum phl_msg_evt_id evt_id; /* u8 id */
u8 *buf;
u32 buf_len;
bool no_io;
void (*cmd_complete)(void* priv, u8 *buf, u32 buf_len, enum rtw_phl_status status);
/*cmd sync*/
bool is_cmd_wait;
_os_atomic ref_cnt;
struct phl_cmd_sync cmd_sync;
};
#define DBG_CMD_SYNC
#ifdef DBG_CMD_SYNC
static void _phl_cmd_sync_dump(struct phl_cmd_sync *cmd_sync, const char *caller)
{
PHL_INFO("[CMD_SYNC] %s\n", caller);
PHL_INFO("[CMD_SYNC] evt_id:%d status:%d\n", cmd_sync->evt_id, cmd_sync->sync.status);
PHL_INFO("[CMD_SYNC] take:%d ms\n", phl_get_passing_time_ms(cmd_sync->sync.submit_time));
}
#endif
static void _phl_cmd_sync_init(struct phl_info_t *phl_info,
enum phl_msg_evt_id evt_id,
struct phl_cmd_sync *cmd_sync, u32 timeout_ms)
{
void *drv = phl_to_drvpriv(phl_info);
_os_spinlock_init(drv, &cmd_sync->lock);
cmd_sync->evt_id = evt_id;
cmd_sync->sync.timeout_ms = timeout_ms;
cmd_sync->sync.submit_time = _os_get_cur_time_ms();
_os_event_init(drv, &(cmd_sync->sync.done));
cmd_sync->sync.status = PHL_CMD_SUBMITTED;
}
static void _phl_cmd_sync_deinit(struct phl_info_t *phl_info,
struct phl_cmd_sync *cmd_sync)
{
#ifdef DBG_CMD_SYNC
_phl_cmd_sync_dump(cmd_sync, __func__);
#endif
_os_event_free(phl_to_drvpriv(phl_info), &(cmd_sync->sync.done));
_os_spinlock_free(phl_to_drvpriv(phl_info), &cmd_sync->lock);
}
inline static enum rtw_phl_status _cmd_stat_2_phl_stat(enum phl_cmd_sts status)
{
if (status == PHL_CMD_DONE_TIMEOUT)
return RTW_PHL_STATUS_CMD_TIMEOUT;
else if(status == PHL_CMD_DONE_CANNOT_IO)
return RTW_PHL_STATUS_CMD_CANNOT_IO;
else if (status == PHL_CMD_DONE_CMD_ERROR)
return RTW_PHL_STATUS_CMD_ERROR;
else if (status == PHL_CMD_DONE_CMD_DROP)
return RTW_PHL_STATUS_CMD_DROP;
else
return RTW_PHL_STATUS_CMD_SUCCESS;
}
static enum rtw_phl_status
_phl_cmd_wait(struct phl_info_t *phl_info, struct phl_cmd_sync *cmd_sync)
{
void *drv = phl_to_drvpriv(phl_info);
u32 cmd_wait_ms = cmd_sync->sync.timeout_ms;/*0: wait forever, >0: up to ms waiting*/
#ifdef DBG_CMD_SYNC
PHL_INFO("evt_id:%d %s in...............\n", cmd_sync->evt_id, __func__);
#endif
if (_os_event_wait(drv, &cmd_sync->sync.done, cmd_wait_ms) == 0) {
_os_spinlock(drv, &cmd_sync->lock, _bh, NULL);
cmd_sync->sync.status = PHL_CMD_DONE_TIMEOUT;
_os_spinunlock(drv, &cmd_sync->lock, _bh, NULL);
PHL_ERR("%s evt_id:%d timeout\n", __func__, cmd_sync->evt_id);
}
#ifdef DBG_CMD_SYNC
PHL_INFO("evt_id:%d %s out...............\n", cmd_sync->evt_id, __func__);
_phl_cmd_sync_dump(cmd_sync, __func__);
#endif
return _cmd_stat_2_phl_stat(cmd_sync->sync.status);
}
static bool _phl_cmd_chk_wating_status(enum phl_cmd_sts status)
{
switch (status) {
case PHL_CMD_SUBMITTED:
/* fall through */
case PHL_CMD_DONE_UNKNOWN:
return true;
default:
return false;
}
}
static void _phl_cmd_done(struct phl_info_t *phl_info,
struct phl_cmd_sync *cmd_sync, enum phl_cmd_sts status)
{
void *drv = phl_to_drvpriv(phl_info);
if (!cmd_sync) {
PHL_ERR("%s cmd_sync is NULL\n", __func__);
_os_warn_on(1);
return;
}
#ifdef DBG_CMD_SYNC
PHL_INFO("evt_id:%d %s in...............\n", cmd_sync->evt_id, __func__);
#endif
_os_spinlock(drv, &cmd_sync->lock, _bh, NULL);
if (_phl_cmd_chk_wating_status(cmd_sync->sync.status)) {
PHL_INFO("%s status:%d\n", __func__, status);
cmd_sync->sync.status = status;
}
_os_spinunlock(drv, &cmd_sync->lock, _bh, NULL);
_os_event_set(drv, &cmd_sync->sync.done);
#ifdef DBG_CMD_SYNC
PHL_INFO("evt_id:%d %s out...............\n", cmd_sync->evt_id, __func__);
_phl_cmd_sync_dump(cmd_sync, __func__);
#endif
}
/********************************************************/
static enum rtw_phl_status
_phl_cmd_general_pre_phase_msg_hdlr(struct phl_info_t *phl_info, void *dispr,
struct phl_msg *msg)
{
enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_cmd_obj *phl_cmd = NULL;
phl_cmd = (struct phl_cmd_obj *)msg->inbuf;
switch (evt_id) {
case MSG_EVT_DBG_RX_DUMP:
/* Do Nothing */
psts = RTW_PHL_STATUS_SUCCESS;
break;
case MSG_EVT_NONE:
/* fall through */
default:
psts = RTW_PHL_STATUS_SUCCESS;
break;
}
return psts;
}
static enum rtw_phl_status
_phl_cmd_general_post_phase_msg_hdlr(struct phl_info_t *phl_info, void *dispr,
struct phl_msg *msg)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
enum phl_msg_evt_id evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
struct phl_cmd_obj *phl_cmd = NULL;
phl_cmd = (struct phl_cmd_obj *)msg->inbuf;
switch (evt_id) {
case MSG_EVT_CHG_OP_CH_DEF_START:
psts = phl_cmd_chg_op_chdef_start_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_SWCH_START:
psts = phl_cmd_set_ch_bw_hdl(phl_info, phl_cmd->buf);
break;
#if defined(CONFIG_PCI_HCI) && defined(PCIE_TRX_MIT_EN)
case MSG_EVT_PCIE_TRX_MIT:
psts = phl_evt_pcie_trx_mit_hdlr(phl_info, phl_cmd->buf);
break;
#endif
case MSG_EVT_DBG_RX_DUMP:
{
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> %s : MSG_EVT_DBG_RX_DUMP\n", __func__);
rtw_hal_notification(phl_info->hal, MSG_EVT_DBG_RX_DUMP, HW_PHY_0);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== %s : MSG_EVT_DBG_RX_DUMP\n", __func__);
psts = RTW_PHL_STATUS_SUCCESS;
}
break;
case MSG_EVT_WATCHDOG:
{
if (IS_MSG_CANNOT_IO(msg->msg_id))
psts = RTW_PHL_STATUS_CANNOT_IO;
else if (IS_MSG_FAIL(msg->msg_id))
psts = RTW_PHL_STATUS_FAILURE;
else if (IS_MSG_CANCEL(msg->msg_id))
psts = RTW_PHL_STATUS_FAILURE;
else
psts = RTW_PHL_STATUS_SUCCESS;
psts = phl_watchdog_cmd_hdl(phl_info, psts);
}
break;
#if defined(CONFIG_USB_HCI)
case MSG_EVT_FORCE_USB_SW:
psts = phl_force_usb_switch(phl_info, *(u32*)(phl_cmd->buf));
break;
case MSG_EVT_GET_USB_SPEED:
psts = phl_get_cur_usb_speed(phl_info, (u32*)(phl_cmd->buf));
break;
case MSG_EVT_GET_USB_SW_ABILITY:
psts = phl_get_usb_support_ability(phl_info, (u32*)(phl_cmd->buf));
break;
#endif
case MSG_EVT_CFG_AMPDU:
psts = phl_cmd_cfg_ampdu_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_DFS_PAUSE_TX:
psts = phl_cmd_dfs_tx_pause_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_ROLE_RECOVER:
psts = phl_role_recover(phl_info);
break;
case MSG_EVT_ROLE_SUSPEND:
psts = phl_role_suspend(phl_info);
break;
#if defined(CONFIG_PCI_HCI)
case MSG_EVT_HAL_SET_L2_LEAVE:
if (rtw_hal_set_l2_leave(phl_info->hal) == RTW_HAL_STATUS_SUCCESS)
psts = RTW_PHL_STATUS_SUCCESS;
break;
#endif
case MSG_EVT_NOTIFY_HAL:
psts = phl_notify_cmd_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_ISSUE_BCN:
#ifdef RTW_PHL_BCN
psts = phl_cmd_issue_bcn_hdl(phl_info, phl_cmd->buf);
#endif
break;
case MSG_EVT_STOP_BCN:
#ifdef RTW_PHL_BCN
psts = phl_cmd_stop_bcn_hdl(phl_info, phl_cmd->buf);
#endif
break;
case MSG_EVT_SEC_KEY:
psts = phl_cmd_set_key_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_ROLE_START:
psts = phl_wifi_role_start_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_ROLE_CHANGE:
psts = phl_wifi_role_chg_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_ROLE_STOP:
psts = phl_wifi_role_stop_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_STA_INFO_CTRL:
psts = phl_cmd_alloc_stainfo_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_STA_MEDIA_STATUS_UPT:
psts = phl_update_media_status_hdl(phl_info, phl_cmd->buf);
break;
case MSG_EVT_CFG_CHINFO:
#ifdef CONFIG_PHL_CHANNEL_INFO
psts = phl_cmd_cfg_chinfo_hdl(phl_info, phl_cmd->buf);
#endif
break;
case MSG_EVT_STA_CHG_STAINFO:
psts = phl_cmd_change_stainfo_hdl(phl_info, phl_cmd->buf);
break;
default:
psts = RTW_PHL_STATUS_SUCCESS;
break;
}
return psts;
}
static enum phl_mdl_ret_code _phl_cmd_general_init(void *phl, void *dispr,
void **priv)
{
*priv = phl;
return MDL_RET_SUCCESS;
}
static void _phl_cmd_general_deinit(void *dispr, void *priv)
{
}
static enum phl_mdl_ret_code _phl_cmd_general_start(void *dispr, void *priv)
{
u8 dispr_idx = 0;
if (RTW_PHL_STATUS_SUCCESS != phl_dispr_get_idx(dispr, &dispr_idx))
return MDL_RET_FAIL;
#if defined(CONFIG_PCI_HCI) && defined(PCIE_TRX_MIT_EN)
{
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
if (RTW_PHL_STATUS_SUCCESS !=
phl_pcie_trx_mit_start(phl_info, dispr_idx))
return MDL_RET_FAIL;
}
#endif
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code _phl_cmd_general_stop(void *dispr, void *priv)
{
return MDL_RET_SUCCESS;
}
static void _fail_evt_hdlr(void *dispr, void *priv, struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
u8 idx = 0;
#ifdef CONFIG_POWER_SAVE
struct phl_module_op_info op_info = {0};
#endif
phl_dispr_get_idx(dispr, &idx);
switch (evt_id) {
case MSG_EVT_WATCHDOG:
/* watchdog do not need to handle fail case */
PHL_DBG("%s do simple watchdog!\n", __func__);
rtw_hal_simple_watchdog(phl_info->hal, false);
break;
default:
#ifdef CONFIG_POWER_SAVE
op_info.op_code = PS_MDL_OP_CANCEL_PWR_REQ;
op_info.inbuf = (u8 *)&evt_id;
phl_disp_eng_set_bk_module_info(phl_info, idx,
PHL_MDL_POWER_MGNT, &op_info);
#endif
break;
}
}
static enum phl_mdl_ret_code _phl_cmd_general_msg_hdlr(void *dispr, void *priv,
struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
if (IS_MSG_FAIL(msg->msg_id)) {
PHL_INFO("%s :: MDL_ID(%d)_FAIL - MSG_EVT_ID=%d \n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id),
MSG_EVT_ID_FIELD(msg->msg_id));
_fail_evt_hdlr(dispr, priv, msg);
return MDL_RET_FAIL;
}
if (MSG_MDL_ID_FIELD(msg->msg_id) != PHL_MDL_GENERAL)
return MDL_RET_IGNORE;
/*
* GENERAL is optional module, msg pass through mandatory module,
* optional module, and wifi role(protocol). So msg shall be handled
* at post phase to make sure that wifi role is at valid state
* if the msg is relative to wifi role(protocol)
*/
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
status =
_phl_cmd_general_pre_phase_msg_hdlr(phl_info, dispr, msg);
else
status =
_phl_cmd_general_post_phase_msg_hdlr(phl_info, dispr, msg);
if (status != RTW_PHL_STATUS_SUCCESS)
return MDL_RET_FAIL;
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code
_phl_cmd_general_set_info(void *dispr, void *priv,
struct phl_module_op_info *info)
{
return MDL_RET_SUCCESS;
}
enum rtw_phl_status
phl_cmd_get_cur_cmdinfo(struct phl_info_t *phl_info,
u8 band_idx,
struct phl_msg *msg,
u8 **cmd,
u32 *cmd_len)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_cmd_obj *phl_cmd = NULL;
phl_cmd = (struct phl_cmd_obj *)msg->inbuf;
if (NULL != phl_cmd) {
*cmd = phl_cmd->buf;
*cmd_len = phl_cmd->buf_len;
psts = RTW_PHL_STATUS_SUCCESS;
}
return psts;
}
static enum phl_mdl_ret_code
_phl_cmd_general_query_info(void *dispr, void *priv,
struct phl_module_op_info *info)
{
return MDL_RET_SUCCESS;
}
enum rtw_phl_status phl_register_cmd_general(struct phl_info_t *phl_info)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
struct phl_cmd_dispatch_engine *disp_eng = &(phl_info->disp_eng);
struct phl_bk_module_ops bk_ops;
u8 band_idx = 0;
bk_ops.init = _phl_cmd_general_init;
bk_ops.deinit = _phl_cmd_general_deinit;
bk_ops.start = _phl_cmd_general_start;
bk_ops.stop = _phl_cmd_general_stop;
bk_ops.msg_hdlr = _phl_cmd_general_msg_hdlr;
bk_ops.set_info = _phl_cmd_general_set_info;
bk_ops.query_info = _phl_cmd_general_query_info;
for (band_idx = 0; band_idx < disp_eng->phy_num; band_idx++) {
status = phl_disp_eng_register_module(phl_info, band_idx,
PHL_MDL_GENERAL, &bk_ops);
if (status != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR(
"%s register MDL_GENRAL in cmd disp failed :%d\n",
__func__, band_idx + 1);
break;
}
}
return status;
}
static enum rtw_phl_status
_phl_cmd_obj_free(struct phl_info_t *phl_info, struct phl_cmd_obj *phl_cmd)
{
void *drv = phl_to_drvpriv(phl_info);
if(phl_cmd == NULL) {
PHL_ERR("%s phl_cmd is NULL\n", __func__);
_os_warn_on(1);
return RTW_PHL_STATUS_FAILURE;
}
if (phl_cmd->is_cmd_wait == true)
_phl_cmd_sync_deinit(phl_info, &phl_cmd->cmd_sync);
_os_kmem_free(drv, phl_cmd, sizeof(struct phl_cmd_obj));
phl_cmd = NULL;
return RTW_PHL_STATUS_SUCCESS;
}
static void _phl_cmd_complete(void *priv, struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
void *drv = phl_to_drvpriv(phl_info);
struct phl_cmd_obj *phl_cmd = (struct phl_cmd_obj *)msg->inbuf;
enum phl_cmd_sts csts = PHL_CMD_DONE_UNKNOWN;
enum rtw_phl_status pstst = RTW_PHL_STATUS_SUCCESS;
PHL_DBG("%s evt_id:%d\n", __func__, phl_cmd->evt_id);
if (IS_MSG_CANNOT_IO(msg->msg_id))
csts = PHL_CMD_DONE_CANNOT_IO;
else if (IS_MSG_FAIL(msg->msg_id))
csts = PHL_CMD_DONE_CMD_ERROR;
else if (IS_MSG_CANCEL(msg->msg_id))
csts = PHL_CMD_DONE_CMD_DROP;
else
csts = PHL_CMD_DONE_SUCCESS;
if (phl_cmd->is_cmd_wait)
_phl_cmd_done(phl_info, &phl_cmd->cmd_sync, csts);
pstst = _cmd_stat_2_phl_stat(csts);
if (phl_cmd->cmd_complete)
phl_cmd->cmd_complete(drv, phl_cmd->buf, phl_cmd->buf_len, pstst);
if (phl_cmd->is_cmd_wait) {
#define PHL_MAX_SCHEDULE_TIMEOUT 100000
u32 try_cnt = 0;
u32 start = _os_get_cur_time_ms();
do {
if (_os_atomic_read(drv, &(phl_cmd->ref_cnt)) == 1)
break;
_os_sleep_ms(drv, 10);
try_cnt++;
if (try_cnt == 50)
PHL_ERR("F-%s, L-%d polling is_cmd_wait to false\n",
__FUNCTION__, __LINE__);
} while (phl_get_passing_time_ms(start) < PHL_MAX_SCHEDULE_TIMEOUT);
}
_phl_cmd_obj_free(phl_info, phl_cmd);
}
enum rtw_phl_status
phl_cmd_enqueue(struct phl_info_t *phl_info,
enum phl_band_idx band_idx,
enum phl_msg_evt_id evt_id,
u8 *cmd_buf,
u32 cmd_len,
void (*cmd_complete)(void* priv, u8 *buf, u32 buf_len, enum rtw_phl_status status),
enum phl_cmd_type cmd_type,
u32 cmd_timeout)
{
void *drv = phl_to_drvpriv(phl_info);
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_cmd_obj *phl_cmd = NULL;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
phl_cmd = _os_kmem_alloc(drv, sizeof(struct phl_cmd_obj));
if (phl_cmd == NULL) {
PHL_ERR("%s: alloc phl_cmd failed!\n", __func__);
psts = RTW_PHL_STATUS_RESOURCE;
goto _exit;
}
phl_cmd->evt_id = evt_id;
phl_cmd->buf = cmd_buf;
phl_cmd->buf_len = cmd_len;
phl_cmd->cmd_complete = cmd_complete;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_GENERAL);
SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id);
msg.inbuf = (u8 *)phl_cmd;
msg.inlen = sizeof(struct phl_cmd_obj);
msg.band_idx = band_idx;
attr.completion.completion = _phl_cmd_complete;
attr.completion.priv = phl_info;
if (cmd_type == PHL_CMD_WAIT) {
phl_cmd->is_cmd_wait = true;
_os_atomic_set(drv, &phl_cmd->ref_cnt, 0);
_phl_cmd_sync_init(phl_info, evt_id, &phl_cmd->cmd_sync, cmd_timeout);
}
psts = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if (psts == RTW_PHL_STATUS_SUCCESS) {
if (cmd_type == PHL_CMD_WAIT) {
psts = _phl_cmd_wait(phl_info, &phl_cmd->cmd_sync);
/*ref_cnt++ for cmd wait done*/
_os_atomic_inc(drv, &phl_cmd->ref_cnt);
/* Check wait cmd status */
if (psts == RTW_PHL_STATUS_CMD_SUCCESS)
psts = RTW_PHL_STATUS_SUCCESS;
} else {
psts = RTW_PHL_STATUS_SUCCESS;
}
} else {
PHL_ERR("%s send msg failed\n", __func__);
_phl_cmd_obj_free(phl_info, phl_cmd);
}
_exit:
return psts;
}
enum rtw_phl_status
rtw_phl_cmd_enqueue(void *phl,
enum phl_band_idx band_idx,
enum phl_msg_evt_id evt_id,
u8 *cmd_buf,
u32 cmd_len,
void (*core_cmd_complete)(void *priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status),
enum phl_cmd_type cmd_type,
u32 cmd_timeout)
{
return phl_cmd_enqueue((struct phl_info_t *)phl,
band_idx,
evt_id,
cmd_buf,
cmd_len,
core_cmd_complete,
cmd_type,
cmd_timeout);
}
#endif /*CONFIG_CMD_DISP*/
|
2301_81045437/rtl8852be
|
phl/phl_cmd_general.c
|
C
|
agpl-3.0
| 17,452
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CMD_GENERAL_H_
#define _PHL_CMD_GENERAL_H_
enum rtw_phl_status
phl_cmd_get_cur_cmdinfo(struct phl_info_t *phl_info,
u8 band_idx,
struct phl_msg *msg,
u8 **cmd, u32 *cmd_len);
enum rtw_phl_status phl_register_cmd_general(struct phl_info_t *phl_info);
enum rtw_phl_status
phl_cmd_enqueue(struct phl_info_t *phl_info,
enum phl_band_idx band_idx,
enum phl_msg_evt_id evt_id,
u8 *cmd_buf,
u32 cmd_len,
void (*cmd_complete)(void *priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status),
enum phl_cmd_type cmd_type,
u32 cmd_timeout);
#endif /*_PHL_CMD_GENERAL_H_*/
|
2301_81045437/rtl8852be
|
phl/phl_cmd_general.h
|
C
|
agpl-3.0
| 1,350
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* Author: vincent_fann@realtek.com
*
*****************************************************************************/
#include "phl_headers.h"
#ifdef CONFIG_FSM
#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
/**
* Deal with original command thread comd
*/
char unknow_func[8] = "no_name";
void *cmd2hal(struct _cmd_obj *pcmd)
{
return pcmd->phl_info->hal;
}
/* usually called when stopping fsm */
void cmd_discard_msg_job(struct _cmd_obj *pcmd, struct fsm_msg *msg)
{
void *d = phl_to_drvpriv(pcmd->phl_info);
struct phl_cmd_job *job = (struct phl_cmd_job *)msg->param;
/* inform core to free param */
if (job->id == JOB_RUN_FUNC &&
(job->u.cmd.fptr || job->u.cmd.func)) {
FSM_INFO(pcmd->fsm, "%s: discard %s:%s\n",
phl_fsm_obj_name(pcmd->fsm_obj),
job_name(pcmd, (u8)job->id),
(char *)job->u.cmd.name);
/* we have to callback to core to free job
* Also release wait_complition if has
*/
job->u.cmd.fptr(job->u.cmd.priv, job->u.cmd.parm, true);
} else
FSM_INFO(pcmd->fsm, "%s: discard %s\n",
phl_fsm_obj_name(pcmd->fsm_obj),
job_name(pcmd, (u8)job->id));
_os_kmem_free(d, (u8 *)msg->param, msg->param_sz);
_os_kmem_free(d, (u8 *)msg, sizeof(*msg));
}
enum rtw_phl_status rtw_phl_job_fill_fptr(void *phl, struct phl_cmd_job *job,
void *func, void *priv, void *parm, char *name, enum PWR_LEVEL pwr)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
void *d = phl_to_drvpriv(phl_info);
job->id = JOB_RUN_FUNC;
job->pwr_level = pwr;
job->u.cmd.fptr = (int (*)(void *priv, void *param, bool discard))func;
job->u.cmd.priv = priv;
job->u.cmd.parm = parm;
_os_mem_set(d, job->u.cmd.name, 0, RTW_PHL_JOB_NAME_LEN);
if (name != NULL)
_os_mem_cpy(d, job->u.cmd.name, name,
MIN((RTW_PHL_JOB_NAME_LEN - 1),
_os_strlen((u8 *)name)));
else
_os_mem_cpy(d, job->u.cmd.name, unknow_func,
MIN((RTW_PHL_JOB_NAME_LEN - 1),
_os_strlen((u8 *)unknow_func)));
return RTW_PHL_STATUS_SUCCESS;
}
/**
* @phl: phl private structure
* @func: function pointer to be runed
* @priv: 1st param of function pointer
* @parm: 2nd param of function pointer
* @name: function name for debug message (optional)
* @pwr: refers to enum PWR_LEVEL
*/
/* TODO remove below when no reference */
enum rtw_phl_status rtw_phl_job_add_fptr(void *phl, void *func,
void *priv, void *parm, char *name, enum PWR_LEVEL pwr)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_cmd_job job;
_os_mem_set(phl_to_drvpriv(phl_info), &job, 0, sizeof(job));
rtw_phl_job_fill_fptr(phl, &job, func, priv, parm, name, pwr);
return phl_cmd_complete_job(phl, &job);
}
static int job_run_func_hdl(struct _cmd_obj *pcmd, void *param)
{
struct phl_cmd_job *job = (struct phl_cmd_job *)param;
if (job->u.cmd.fptr)
return job->u.cmd.fptr(job->u.cmd.priv, job->u.cmd.parm, false);
else /* TODO remove else */
return job->u.cmd.func(job->u.cmd.priv, job->u.cmd.parm);
}
/** JOB_ADD_STA
* For EXTERNAL application to add sta entry (expose)
* @phl: phl private structure
* @sta: see rtw_phl_stainfo_t
* @sync: Async or SYNC mode
*/
enum rtw_phl_status rtw_hal_add_sta_entry_job(void *phl,
struct rtw_phl_stainfo_t *sta, enum JOB_SYNC sync)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
void *d = phl_to_drvpriv(phl_info);
struct phl_cmd_job job;
_os_mem_set(d, &job, 0, sizeof(job));
job.id = JOB_ADD_STA_ENTRY;
job.u.sta.sta = sta;
job.wait.sync = sync;
return phl_cmd_complete_job(phl, &job);
}
static int job_add_sta_entry_hdl(struct _cmd_obj *pcmd, void *param)
{
struct phl_cmd_job *job = (struct phl_cmd_job *)param;
return rtw_hal_add_sta_entry(cmd2hal(pcmd), job->u.sta.sta);
}
static int job_add_macid_hdl(struct _cmd_obj *pcmd, void *param)
{
FSM_INFO(pcmd->fsm, "job: %s()\n", __func__);
return 0;
}
struct job_hdl_ent job_hdl_tbl[] = {
{JOB_RUN_FUNC, "JOB_RUN_FUNC", job_run_func_hdl},
{JOB_ADD_STA_ENTRY, "JOB_ADD_STA_ENTRY", job_add_sta_entry_hdl},
{JOB_ADD_MACID, "JOB_ADD_MACID", job_add_macid_hdl}
};
void cmd_set_job_tbl(struct _cmd_obj *pcmd)
{
pcmd->job_tbl = job_hdl_tbl;
}
char *job_name(struct _cmd_obj *pcmd, u8 id)
{
if (id >= JOB_MAX)
FSM_ERR(pcmd->fsm, "%s: job id %d not found\n",
phl_fsm_obj_name(pcmd->fsm_obj), id);
return job_hdl_tbl[id].name;
}
int phl_cmd_do_job(struct _cmd_obj *pcmd, void *param)
{
struct phl_cmd_job *job = (struct phl_cmd_job *)param;
void *d = phl_to_drvpriv(pcmd->phl_info);
int rtn = FSM_FREE_PARAM;
if (job->id == JOB_RUN_FUNC)
FSM_INFO(pcmd->fsm, "%s: %s (%s)\n",
phl_fsm_obj_name(pcmd->fsm_obj),
(char *)job_name(pcmd, (u8)job->id),
(char *)job->u.cmd.name);
else
FSM_INFO(pcmd->fsm, "%s: %s\n",
phl_fsm_obj_name(pcmd->fsm_obj),
(char *)job_name(pcmd, (u8)job->id));
job->wait.rtn = pcmd->job_tbl[job->id].job_func(pcmd, job);
if (job->wait.sync == JOB_WAIT_COMPLETION) {
_os_event_set(d, &(job->wait.done));
/* Inform fsm framwork do NOT free param
* SYNC mode use caller's local job variable
*/
rtn = FSM_KEEP_PARAM;
}
return rtn;
}
#endif /*CONFIG_FSM*/
|
2301_81045437/rtl8852be
|
phl/phl_cmd_job.c
|
C
|
agpl-3.0
| 5,642
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* Author: vincent_fann@realtek.com
*
*****************************************************************************/
#ifndef __PHL_CMD_JOB_H__
#define __PHL_CMD_JOB_H__
#define RTW_PHL_JOB_NAME_LEN 32
#ifndef MIN
#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
#endif
struct fsm_msg;
struct _cmd_obj;
/* command job */
enum JOB_ID {
JOB_RUN_FUNC,
JOB_ADD_STA_ENTRY,
JOB_ADD_MACID,
JOB_MAX,
};
struct job_hdl_ent {
u16 job_id;
char name[RTW_PHL_JOB_NAME_LEN];
int (*job_func)(struct _cmd_obj *pcmd, void *param);
};
enum JOB_RESULT {
JOB_SUCCESS,
/* caller thread will be schedule out until job is completed */
JOB_TIMEOUT,
JOB_FAILURE
};
struct wait_completion {
u8 sync;
u32 submit_time;
/* <0: not synchronous,
* 0: wait forever,
* >0: max waitting time (ms)
*/
int max_wait_time;
_os_event done;
/* JOB_WAIT_COMPLETION use */
int rtn; /* handle return value */
enum JOB_RESULT result; /* operation result */
};
struct phl_cmd_job {
_os_list list;
u16 id;
struct wait_completion wait;
u8 pwr_level;
union {
struct { /* JOB_RUN_FUNC */
int (*func)(void *priv, void *param); /* TODO remove */
int (*fptr)(void *priv, void *param, bool discard);
void *priv;
void *parm;
int parm_sz;
char name[RTW_PHL_JOB_NAME_LEN];
} cmd;
struct { /* JOB_ADD_STA_ENTRY */
struct rtw_phl_stainfo_t *sta;
} sta;
} u;
};
enum PWR_LEVEL {
PWR_DONT_CARE, /* able to run in any kind of power mode */
PWR_NO_IO, /* without register read write */
PWR_BASIC_IO /* leave 32K and PG */
};
enum JOB_SYNC {
JOB_ASYNC,
/* caller thread will be schedule out until job is completed */
JOB_WAIT_COMPLETION
};
char *job_name(struct _cmd_obj *pcmd, u8 id);
void cmd_set_job_tbl(struct _cmd_obj *pcmd);
void cmd_discard_msg_job(struct _cmd_obj *pcmd, struct fsm_msg *msg);
int phl_cmd_do_job(struct _cmd_obj *pcmd, void *param);
/* command thread jobs */
/* TODO remove below when no reference */
enum rtw_phl_status rtw_phl_job_add_fptr(void *phl, void *func,
void *priv, void *parm, char *name, enum PWR_LEVEL pwr);
enum rtw_phl_status rtw_phl_job_fill_fptr(void *phl, struct phl_cmd_job *job,
void *func, void *priv, void *parm, char *name, enum PWR_LEVEL pwr);
enum rtw_phl_status phl_cmd_enqueue_and_wait_job(struct _cmd_obj *pcmd,
struct fsm_msg *msg);
enum rtw_phl_status phl_cmd_complete_job(void *phl, struct phl_cmd_job *job);
enum rtw_phl_status rtw_phl_job_reg_wdog(void *phl,
int (*func)(void *priv, void *param, bool discard),
void *priv, void *parm, int parm_sz, char *name, enum PWR_LEVEL pwr);
enum rtw_phl_status rtw_phl_cmd_pause_wdog(void *phl, char *reason);
enum rtw_phl_status rtw_phl_cmd_resume_wdog(void *phl, char *reason);
enum rtw_phl_status rtw_hal_add_sta_entry_job(void *phl,
struct rtw_phl_stainfo_t *sta, enum JOB_SYNC sync);
#endif /* __PHL_CMD_JOB_H__ */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_job.h
|
C
|
agpl-3.0
| 3,421
|
/******************************************************************************
*
* Copyright(c) 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CMD_PS_C_
#include "phl_headers.h"
#ifdef CONFIG_POWER_SAVE
/* structure of a power request */
struct pwr_req {
_os_list list;
u16 evt_id;
};
struct rt_ps {
enum phl_ps_rt_rson rt_rson;
bool ps_allow;
};
enum {
PS_STATE_NONE = 0,
PS_STATE_LEAVED,
/**
* lps: protocol only
* ips: won't in this state
*/
PS_STATE_PROTO,
/**
* lps: protocol + power
* ips: power
*/
PS_STATE_ENTERED
};
static const char *_ps_state_to_str(u8 ps_state)
{
switch (ps_state) {
case PS_STATE_ENTERED:
return "PS_ENTERED";
case PS_STATE_PROTO:
return "PS_PROTOCOL";
case PS_STATE_LEAVED:
return "PS_LEAVED";
default:
return "NONE";
}
}
struct _ps_mr_info {
bool ap_active;
bool gc_active;
};
#define CMD_PS_TIMER_PERIOD 100
#define MAX_PWE_REQ_NUM 16
struct cmd_ps {
struct phl_info_t *phl_info;
void *dispr;
_os_timer ps_timer;
struct phl_queue req_busy_q;
struct phl_queue req_idle_q;
struct pwr_req req_pool[MAX_PWE_REQ_NUM];
bool rej_pwr_req; /* reject all pwr request */
bool btc_req_pwr; /* btc request pwr or not */
bool stop_datapath;
/* current state */
u8 cur_pwr_lvl;
u8 ps_state;
u8 ps_mode;
char enter_rson[MAX_CMD_PS_RSON_LENGTH];
char leave_rson[MAX_CMD_PS_RSON_LENGTH];
/* lps */
struct rtw_phl_stainfo_t *sta; /* sta entering/leaving lps */
u16 macid;
u32 null_token;
bool pre_phase_leave_ps;
/* refs. enum "phl_ps_rt_rson" */
enum phl_ps_rt_rson rt_stop_rson;
struct _ps_mr_info mr_info;
/* rssi */
u8 rssi_bcn_min;
};
/**
* determine leave lps or not
* return true if rssi variation reach threshold
* @ps: see cmd_ps
*/
static bool _chk_rssi_diff_reach_thld(struct cmd_ps *ps)
{
struct phl_info_t *phl_info = ps->phl_info;
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
u8 cur_rssi_bcn_min = 0;
u8 *rssi_bcn_min = &ps->rssi_bcn_min;
bool leave_ps = false;
cur_rssi_bcn_min = phl_get_min_rssi_bcn(phl_info);
do {
if (*rssi_bcn_min == 0 || *rssi_bcn_min == 0xFF) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): (criteria = %d, cur = %d) criteria invalid, set criteria to cur\n",
__func__, *rssi_bcn_min, cur_rssi_bcn_min);
*rssi_bcn_min = cur_rssi_bcn_min; /* update with current_rssi */
break;
}
if (DIFF(*rssi_bcn_min, cur_rssi_bcn_min) < ps_cap->lps_rssi_diff_threshold) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): (criteria = %d, cur = %d) RSSI diff < %d, do nothing\n",
__func__, *rssi_bcn_min, cur_rssi_bcn_min, ps_cap->lps_rssi_diff_threshold);
break;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): leave ps and update criteria from %d to %d\n", __func__, *rssi_bcn_min, cur_rssi_bcn_min);
leave_ps = true;
*rssi_bcn_min = cur_rssi_bcn_min;
} while (0);
return leave_ps;
}
/**
* determine leave lps or not
* return true if beacon offset changed
* @ps: see cmd_ps
*/
bool _chk_bcn_offset_changed(struct cmd_ps *ps)
{
struct phl_info_t *phl_info = ps->phl_info;
u8 ridx = MAX_WIFI_ROLE_NUMBER;
struct rtw_wifi_role_t *wrole = NULL;
struct rtw_bcn_offset *b_ofst_i = NULL;
bool leave_ps = false;
for (ridx = 0; ridx < MAX_WIFI_ROLE_NUMBER; ridx++) {
wrole = phl_get_wrole_by_ridx(phl_info, ridx);
if (wrole == NULL)
continue;
if (rtw_phl_role_is_client_category(wrole) && wrole->mstate == MLME_LINKED) {
b_ofst_i = phl_get_sta_bcn_offset_info(phl_info, wrole);
if (b_ofst_i->conf_lvl >= CONF_LVL_MID &&
b_ofst_i->offset != b_ofst_i->cr_tbtt_shift) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): update ridx(%d) bcn offset from %d to %d TU\n",
__func__, ridx, b_ofst_i->cr_tbtt_shift, b_ofst_i->offset);
leave_ps = true;
break;
}
}
}
return leave_ps;
}
/**
* check whether to leave/enter lps
* return true if ps need to change to the target state
* @ps: see cmd_ps
* @mac_id: macid of corresponding sta
* @cur_state: currently lps state
* @target_state: the target ps state
*/
static bool
_lps_state_judge_changed(struct cmd_ps *ps, u16 macid, u8 cur_state, u8 target_state)
{
struct phl_info_t *phl_info = ps->phl_info;
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
struct rtw_stats *phl_stats = &phl_info->phl_com->phl_stats;
struct rtw_phl_stainfo_t *sta = NULL;
bool change_state = false;
u8 rssi = 0;
sta = rtw_phl_get_stainfo_by_macid(phl_info, macid);
if (sta == NULL) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): cannot get sta of macid %d.\n", __func__, macid);
return false;
}
rssi = rtw_hal_get_sta_rssi(sta);
if (target_state == PS_STATE_ENTERED) {
if (cur_state == PS_STATE_LEAVED || cur_state == PS_STATE_PROTO) {
if (rssi > ps_cap->lps_rssi_enter_threshold &&
phl_stats->tx_traffic.lvl == RTW_TFC_IDLE &&
phl_stats->rx_traffic.lvl == RTW_TFC_IDLE) {
change_state = true;
}
}
} else {
if (cur_state == PS_STATE_ENTERED || cur_state == PS_STATE_PROTO) {
if (_chk_rssi_diff_reach_thld(ps) ||
_chk_bcn_offset_changed(ps) ||
rssi < ps_cap->lps_rssi_leave_threshold ||
phl_stats->tx_traffic.lvl != RTW_TFC_IDLE ||
phl_stats->rx_traffic.lvl != RTW_TFC_IDLE) {
change_state = true;
}
}
}
if (change_state) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): state %s -> %s, Tx(%s), Rx(%s), RSSI(%d)\n",
__func__, _ps_state_to_str(cur_state), _ps_state_to_str(target_state),
phl_tfc_lvl_to_str(phl_stats->tx_traffic.lvl),
phl_tfc_lvl_to_str(phl_stats->rx_traffic.lvl), rssi);
}
return change_state;
}
static void _set_ps_rson(struct cmd_ps *ps, u8 enter, char *rson)
{
if (enter) {
_os_mem_set(phl_to_drvpriv(ps->phl_info), ps->enter_rson, 0, MAX_CMD_PS_RSON_LENGTH);
_os_mem_cpy(phl_to_drvpriv(ps->phl_info), ps->enter_rson, rson, MAX_CMD_PS_RSON_LENGTH);
} else {
_os_mem_set(phl_to_drvpriv(ps->phl_info), ps->leave_rson, 0, MAX_CMD_PS_RSON_LENGTH);
_os_mem_cpy(phl_to_drvpriv(ps->phl_info), ps->leave_rson, rson, MAX_CMD_PS_RSON_LENGTH);
}
}
/**
* Leave power saving
* return RTW_PHL_STATUS_SUCCESS if leave ps ok
* @ps: see cmd_ps
* @leave_proto: whether to leave protocol
*/
enum rtw_phl_status _leave_ps(struct cmd_ps *ps, bool leave_proto, char *rson)
{
struct phl_info_t *phl_info = ps->phl_info;
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
struct ps_cfg cfg = {0};
if (ps->ps_state == PS_STATE_LEAVED) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): not in power saving.\n", __func__);
return RTW_PHL_STATUS_SUCCESS;
}
cfg.cur_pwr_lvl = ps->cur_pwr_lvl;
if (ps->ps_mode == PS_MODE_LPS) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): target macid to leave lps %d (leave_proto %d).\n",
__func__, ps->macid, leave_proto);
if (!leave_proto) {
if (ps->ps_state == PS_STATE_PROTO) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): in lps protocal only.\n", __func__);
return RTW_PHL_STATUS_SUCCESS;
}
cfg.pwr_cfg = true;
cfg.proto_cfg = false;
} else {
if (ps->ps_state == PS_STATE_PROTO) {
cfg.pwr_cfg = false;
cfg.proto_cfg = true;
} else {
cfg.pwr_cfg = true;
cfg.proto_cfg = true;
}
}
cfg.macid = ps->macid;
cfg.token = &ps->null_token;
cfg.pwr_lvl = PS_PWR_LVL_PWRON;
cfg.ps_mode = ps->ps_mode;
} else if (ps->ps_mode == PS_MODE_IPS) {
cfg.pwr_lvl = PS_PWR_LVL_PWRON;
cfg.ps_mode = ps->ps_mode;
} else {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): unknown ps mode!\n", __func__);
}
_set_ps_rson(ps, false, rson);
status = phl_ps_leave_ps(phl_info, &cfg);
if (status == RTW_PHL_STATUS_SUCCESS) {
ps->cur_pwr_lvl = cfg.pwr_lvl;
if (ps->ps_mode == PS_MODE_LPS) {
ps->ps_mode = (leave_proto != true) ? PS_MODE_LPS : PS_MODE_NONE;
ps->ps_state = (leave_proto != true) ? PS_STATE_PROTO : PS_STATE_LEAVED;
ps->macid = (leave_proto != true) ? ps->macid : 0xFFFF;
} else {
ps->ps_mode = PS_MODE_NONE;
ps->ps_state = PS_STATE_LEAVED;
ps->macid = 0xFFFF;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): leave ps success, reason(%s).\n", __func__, rson);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): ps mode(%s), pwr lvl(%s), ps state(%s)\n",
__func__, phl_ps_ps_mode_to_str(ps->ps_mode),
phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl), _ps_state_to_str(ps->ps_state));
} else {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): leave ps fail! reason(%s).\n", __func__, rson);
}
return status;
}
/**
* Enter power saving
* return RTW_PHL_STATUS_SUCCESS if enter ps ok
* @ps: see cmd_ps
* @ps_mode: target ps mode to enter
* @macid : target macid to enter lps
*/
enum rtw_phl_status _enter_ps(struct cmd_ps *ps, u8 ps_mode, u16 macid, char *rson)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
struct ps_cfg cfg = {0};
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
if (ps->ps_state == PS_STATE_ENTERED) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): already in power saving.\n", __func__);
return RTW_PHL_STATUS_SUCCESS;
}
cfg.cur_pwr_lvl = ps->cur_pwr_lvl;
if (ps_mode == PS_MODE_LPS) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): target macid to enter lps %d.\n", __func__, macid);
cfg.proto_cfg = (ps->ps_state == PS_STATE_PROTO) ? false : true;
cfg.pwr_cfg = true;
cfg.macid = macid;
cfg.token = &ps->null_token;
cfg.pwr_lvl = phl_ps_judge_pwr_lvl(ps_cap->lps_cap, ps_mode, true);
cfg.ps_mode = ps_mode;
cfg.awake_interval = ps_cap->lps_awake_interval;
cfg.listen_bcn_mode = ps_cap->lps_listen_bcn_mode;
cfg.smart_ps_mode = ps_cap->lps_smart_ps_mode;
} else if (ps_mode == PS_MODE_IPS) {
cfg.pwr_lvl = PS_PWR_LVL_PWROFF;
cfg.ps_mode = ps_mode;
} else {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): unknown ps mode!\n", __func__);
}
_set_ps_rson(ps, true, rson);
status = phl_ps_enter_ps(ps->phl_info, &cfg);
if (status == RTW_PHL_STATUS_SUCCESS) {
ps->cur_pwr_lvl = cfg.pwr_lvl;
ps->ps_mode = cfg.ps_mode;
ps->macid = cfg.macid;
ps->ps_state = PS_STATE_ENTERED;
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): enter ps success, reason(%s).\n", __func__, rson);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): ps mode(%s), pwr lvl(%s), ps state(%s)\n",
__func__, phl_ps_ps_mode_to_str(ps->ps_mode),
phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl), _ps_state_to_str(ps->ps_state));
} else {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): enter ps fail! reason(%s).\n", __func__, rson);
}
return status;
}
static bool _pop_idle_req(struct cmd_ps *ps, struct pwr_req **req)
{
void *d = phl_to_drvpriv(ps->phl_info);
_os_list *new_req = NULL;
bool ret = false;
(*req) = NULL;
if (pq_pop(d, &(ps->req_idle_q), &new_req, _first, _bh)) {
(*req) = (struct pwr_req *)new_req;
ret = true;
} else {
ret = false;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): remaining idle req cnt %d.\n", __func__, ps->req_idle_q.cnt);
return ret;
}
static void _push_idle_req(struct cmd_ps *ps, struct pwr_req *req)
{
void *d = phl_to_drvpriv(ps->phl_info);
pq_push(d, &(ps->req_idle_q), &(req->list), _tail, _bh);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): remaining idle req cnt %d.\n", __func__, ps->req_idle_q.cnt);
}
static bool _pop_busy_req(struct cmd_ps *ps, struct pwr_req **req)
{
void *d = phl_to_drvpriv(ps->phl_info);
_os_list *new_req = NULL;
bool ret = false;
(*req) = NULL;
if (pq_pop(d, &(ps->req_busy_q), &new_req, _tail, _bh)) {
(*req) = (struct pwr_req *)new_req;
ret = true;
} else {
ret = false;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): current busy req cnt %d.\n", __func__, ps->req_busy_q.cnt);
return ret;
}
static void _push_busy_req(struct cmd_ps *ps, struct pwr_req *req)
{
void *d = phl_to_drvpriv(ps->phl_info);
pq_push(d, &(ps->req_busy_q), &(req->list), _tail, _bh);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): current busy req cnt %d.\n", __func__, ps->req_busy_q.cnt);
}
static void _cancel_pwr_req(struct cmd_ps *ps, u16 evt_id)
{
struct pwr_req *req = NULL;
if (!_pop_busy_req(ps, &req)) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): busy queue is empty.\n", __func__);
return;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): evt_id %d\n", __func__, req->evt_id);
if (req->evt_id != evt_id && MSG_EVT_PHY_IDLE != evt_id)
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): evt_id mismatch.\n", __func__);
req->evt_id = MSG_EVT_NONE;
_push_idle_req(ps, req);
}
static enum rtw_phl_status _add_pwr_req(struct cmd_ps *ps, u16 evt_id)
{
enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS;
struct pwr_req *req = NULL;
if (!_pop_idle_req(ps, &req)) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): idle queue is empty.\n", __func__);
return RTW_PHL_STATUS_RESOURCE;
}
req->evt_id = evt_id;
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): evt_id %d\n", __func__, evt_id);
_push_busy_req(ps, req);
return status;
}
static void _init_pwr_req_q(struct cmd_ps *ps)
{
void *d = phl_to_drvpriv(ps->phl_info);
u8 i = 0;
pq_init(d, &ps->req_busy_q);
pq_init(d, &ps->req_idle_q);
_os_mem_set(d, ps->req_pool, 0,
sizeof(struct pwr_req) * MAX_PWE_REQ_NUM);
for (i = 0; i < MAX_PWE_REQ_NUM; i++) {
pq_push(d, &(ps->req_idle_q),
&(ps->req_pool[i].list), _tail, _bh);
}
}
static void _reset_pwr_req_q(struct cmd_ps *ps)
{
void *d = phl_to_drvpriv(ps->phl_info);
u8 i = 0;
pq_reset(d, &ps->req_busy_q, _bh);
pq_reset(d, &ps->req_idle_q, _bh);
_os_mem_set(d, ps->req_pool, 0,
sizeof(struct pwr_req) * MAX_PWE_REQ_NUM);
for (i = 0; i < MAX_PWE_REQ_NUM; i++) {
pq_push(d, &(ps->req_idle_q),
&(ps->req_pool[i].list), _tail, _bh);
}
}
static void _deinit_pwr_req_q(struct cmd_ps *ps)
{
void *d = phl_to_drvpriv(ps->phl_info);
pq_deinit(d, &ps->req_busy_q);
pq_deinit(d, &ps->req_idle_q);
}
static void _init_ps_dflt_sw_cap(struct cmd_ps *ps)
{
struct rtw_ps_cap_t *sw_cap = _get_ps_sw_cap(ps->phl_info);
sw_cap->init_rf_state = RTW_RF_ON;
sw_cap->init_rt_stop_rson = PS_RT_RSON_NONE;
sw_cap->leave_fail_act = PS_LEAVE_FAIL_ACT_NONE;
sw_cap->ips_en = PS_OP_MODE_DISABLED;
sw_cap->ips_cap = 0;
sw_cap->ips_wow_en = PS_OP_MODE_DISABLED;
sw_cap->ips_wow_cap = 0;
sw_cap->lps_en = PS_OP_MODE_DISABLED;
sw_cap->lps_cap = 0;
sw_cap->lps_awake_interval = 0;
sw_cap->lps_listen_bcn_mode = RTW_LPS_RLBM_MIN;
sw_cap->lps_smart_ps_mode = RTW_LPS_TRX_PWR0;
sw_cap->lps_rssi_enter_threshold = 40;
sw_cap->lps_rssi_leave_threshold = 35;
sw_cap->lps_rssi_diff_threshold = 5;
sw_cap->lps_wow_en = PS_OP_MODE_DISABLED;
sw_cap->lps_wow_cap = 0;
sw_cap->lps_wow_awake_interval = 0;
sw_cap->lps_wow_listen_bcn_mode = RTW_LPS_RLBM_MAX;
sw_cap->lps_wow_smart_ps_mode = RTW_LPS_TRX_PWR0;
}
static void _cmd_ps_timer_cb(void *context)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
struct cmd_ps *ps = (struct cmd_ps *)context;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
PHL_DBG("[PS_CMD], %s(): \n", __func__);
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PS_PERIOD_CHK);
msg.band_idx = HW_BAND_0;
pstatus = phl_disp_eng_send_msg(ps->phl_info, &msg, &attr, NULL);
if (pstatus != RTW_PHL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to send MSG_EVT_PS_PERIOD_CHK.\n", __func__);
}
}
static enum phl_mdl_ret_code _ps_mdl_init(void *phl, void *dispr, void **priv)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct cmd_ps *ps = NULL;
PHL_INFO("[PS_CMD], %s(): \n", __func__);
if (priv == NULL)
return MDL_RET_FAIL;
(*priv) = NULL;
ps = (struct cmd_ps *)_os_mem_alloc(phl_to_drvpriv(phl_info),
sizeof(struct cmd_ps));
if (ps == NULL) {
PHL_ERR("[PS_CMD], %s(): allocate cmd ps fail.\n", __func__);
return MDL_RET_FAIL;
}
_os_mem_set(phl_to_drvpriv(phl_info), ps, 0, sizeof(struct cmd_ps));
ps->phl_info = phl_info;
ps->dispr = dispr;
(*priv) = (void *)ps;
ps->cur_pwr_lvl = PS_PWR_LVL_PWRON;
ps->ps_state = PS_STATE_LEAVED;
ps->ps_mode = PS_MODE_NONE;
ps->rej_pwr_req = false;
ps->rt_stop_rson = PS_RT_RSON_NONE;
_os_init_timer(phl_to_drvpriv(phl_info),
&ps->ps_timer,
_cmd_ps_timer_cb,
ps,
"phl_cmd_ps_timer");
_init_pwr_req_q(ps);
_init_ps_dflt_sw_cap(ps);
return MDL_RET_SUCCESS;
}
static void _ps_mdl_deinit(void *dispr, void *priv)
{
struct cmd_ps *ps = (struct cmd_ps *)priv;
PHL_INFO("[PS_CMD], %s(): \n", __func__);
_os_release_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer);
_deinit_pwr_req_q(ps);
if (ps != NULL)
_os_mem_free(phl_to_drvpriv(ps->phl_info), ps, sizeof(struct cmd_ps));
}
static void _dump_ps_cap(struct cmd_ps *ps)
{
struct rtw_ps_cap_t *ps_cap = NULL;
ps_cap = _get_ps_cap(ps->phl_info);
PHL_INFO("[PS_CMD], %s(): \n", __func__);
PHL_INFO("[PS_CMD], init_rf_state: %d\n", ps_cap->init_rf_state);
PHL_INFO("[PS_CMD], init_rt_stop_rson: 0x%x\n", ps_cap->init_rt_stop_rson);
PHL_INFO("[PS_CMD], leave_fail_act: 0x%x\n", ps_cap->leave_fail_act);
PHL_INFO("[PS_CMD], ips_en: %d\n", ps_cap->ips_en);
PHL_INFO("[PS_CMD], ips_cap: %d\n", ps_cap->ips_cap);
PHL_INFO("[PS_CMD], ips_wow_en: %d\n", ps_cap->ips_wow_en);
PHL_INFO("[PS_CMD], ips_wow_cap: %d\n", ps_cap->ips_wow_cap);
PHL_INFO("[PS_CMD], lps_en: %d\n", ps_cap->lps_en);
PHL_INFO("[PS_CMD], lps_cap: %d\n", ps_cap->lps_cap);
PHL_INFO("[PS_CMD], lps_awake_interval: %d\n", ps_cap->lps_awake_interval);
PHL_INFO("[PS_CMD], lps_listen_bcn_mode: %d\n", ps_cap->lps_listen_bcn_mode);
PHL_INFO("[PS_CMD], lps_smart_ps_mode: %d\n", ps_cap->lps_smart_ps_mode);
PHL_INFO("[PS_CMD], lps_rssi_enter_threshold: %d\n", ps_cap->lps_rssi_enter_threshold);
PHL_INFO("[PS_CMD], lps_rssi_leave_threshold: %d\n", ps_cap->lps_rssi_leave_threshold);
PHL_INFO("[PS_CMD], lps_rssi_diff_threshold: %d\n", ps_cap->lps_rssi_diff_threshold);
PHL_INFO("[PS_CMD], lps_wow_en: %d\n", ps_cap->lps_wow_en);
PHL_INFO("[PS_CMD], lps_wow_cap: %d\n", ps_cap->lps_wow_cap);
PHL_INFO("[PS_CMD], lps_wow_awake_interval: %d\n", ps_cap->lps_wow_awake_interval);
PHL_INFO("[PS_CMD], lps_wow_listen_bcn_mode: %d\n", ps_cap->lps_wow_listen_bcn_mode);
PHL_INFO("[PS_CMD], lps_wow_smart_ps_mode: %d\n", ps_cap->lps_wow_smart_ps_mode);
PHL_INFO("[PS_CMD], lps_pause_tx: %d\n", ps_cap->lps_pause_tx);
}
static void _leave_success_hdlr(struct cmd_ps *ps)
{
struct phl_data_ctl_t ctl = {0};
if (ps->stop_datapath) {
/* resume tx datapath */
ctl.id = PHL_MDL_POWER_MGNT;
ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
phl_data_ctrler(ps->phl_info, &ctl, NULL);
ps->stop_datapath = false;
}
}
static void _leave_fail_hdlr(struct cmd_ps *ps)
{
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
PHL_WARN("[PS_CMD], %s(): action 0x%x\n", __func__, ps_cap->leave_fail_act);
/* reject all power operation */
if (ps_cap->leave_fail_act & PS_LEAVE_FAIL_ACT_REJ_PWR)
ps->rej_pwr_req = true;
/* L2 should be the last one */
if (ps_cap->leave_fail_act & PS_LEAVE_FAIL_ACT_L2)
phl_ser_send_msg(ps->phl_info, RTW_PHL_SER_L2_RESET);
}
static enum phl_mdl_ret_code _ps_mdl_start(void *dispr, void *priv)
{
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
struct cmd_ps *ps = (struct cmd_ps *)priv;
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
u8 idx = 0;
ps->rt_stop_rson = ps_cap->init_rt_stop_rson;
_reset_pwr_req_q(ps);
phl_dispr_get_idx(dispr, &idx);
if (idx == 0) {
_dump_ps_cap(ps);
PHL_INFO("[PS_CMD], %s(): init rf state %d, reject pwr req %d\n",
__func__, ps_cap->init_rf_state, ps->rej_pwr_req);
if (ps_cap->init_rf_state == RTW_RF_OFF)
ps->rej_pwr_req = true;
if (ps->rej_pwr_req == true)
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "mdl start with rf off");
_os_set_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer, CMD_PS_TIMER_PERIOD);
}
return ret;
}
static enum phl_mdl_ret_code _ps_mdl_stop(void *dispr, void *priv)
{
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
struct cmd_ps *ps = (struct cmd_ps *)priv;
if (ps->ps_state == PS_STATE_ENTERED) {
PHL_WARN("[PS_CMD], %s(): module stop in power saving!\n", __func__);
_leave_ps(ps, true, "mdl stop");
}
_os_cancel_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer);
PHL_INFO("[PS_CMD], %s(): \n", __func__);
return ret;
}
static bool _chk_role_all_inactive(struct cmd_ps *ps)
{
struct phl_info_t *phl_info = ps->phl_info;
u8 role_idx = 0;
bool ret = true;
for (role_idx = 0; role_idx < MAX_WIFI_ROLE_NUMBER; role_idx++) {
if (phl_info->phl_com->wifi_roles[role_idx].mstate != MLME_NO_LINK) {
ret = false;
break;
}
}
return ret;
}
static struct rtw_wifi_role_t *_get_role_of_ps_permitted(struct cmd_ps *ps)
{
struct phl_info_t *phl_info = ps->phl_info;
struct rtw_phl_com_t *phl_com = phl_info->phl_com;
u8 role_idx = 0;
for (role_idx = 0; role_idx < MAX_WIFI_ROLE_NUMBER; role_idx++) {
if (phl_com->wifi_roles[role_idx].active == false)
continue;
if (phl_com->wifi_roles[role_idx].type == PHL_RTYPE_STATION &&
phl_com->wifi_roles[role_idx].mstate == MLME_LINKED) {
return &(phl_com->wifi_roles[role_idx]);
}
}
return NULL;
}
/**
* go through all wifi roles and check whether input
* ps mode desired is allowed with existing wroles
* @ps: see cmd_ps
* @target_mode: the desired ps mode (lps or ips)
* @macid: target macid to enter lps
*/
static bool _chk_wrole_with_ps_mode(struct cmd_ps *ps,
u8 target_mode, u16 *macid)
{
struct rtw_wifi_role_t *role = NULL;
bool ret = false;
struct rtw_phl_stainfo_t *sta = NULL;
if (ps->mr_info.ap_active || ps->mr_info.gc_active) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): ap %d or gc %d, is active.\n", __func__,
ps->mr_info.ap_active, ps->mr_info.gc_active);
return false;
}
if (target_mode == PS_MODE_IPS) {
if (_chk_role_all_inactive(ps))
ret = true;
} else if (target_mode == PS_MODE_LPS) {
role = _get_role_of_ps_permitted(ps);
if (role == NULL) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): there is no suitable role to enter lps.\n", __func__);
return false;
}
sta = rtw_phl_get_stainfo_self(ps->phl_info, role);
if (sta == NULL) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): cannot get sta info.\n", __func__);
return false;
}
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): role id to enter ps (%d).\n", __func__, role->id);
ps->sta = sta;
*macid = sta->macid;
ret = true;
}
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): decide enter ps(%s), target mode(%s).\n",
__func__, (ret) ? "Yes" : "No", phl_ps_ps_mode_to_str(target_mode));
return ret;
}
static enum rtw_phl_status _stop_datapath(struct cmd_ps *ps)
{
struct phl_data_ctl_t ctl = {0};
/* stop tx datapath */
ctl.id = PHL_MDL_POWER_MGNT;
ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE;
if (phl_data_ctrler(ps->phl_info, &ctl, NULL) == RTW_PHL_STATUS_SUCCESS) {
ps->stop_datapath = true;
return RTW_PHL_STATUS_SUCCESS;
}
return RTW_PHL_STATUS_FAILURE;
}
static bool _is_datapath_active(struct cmd_ps *ps)
{
struct phl_info_t *phl_info = ps->phl_info;
return (_os_atomic_read(phl_to_drvpriv(phl_info), &phl_info->phl_sw_tx_sts)
!= PHL_TX_STATUS_SW_PAUSE) ? true : false;
}
/**
* check current capability of power saving
* return able to enter ps or not
* @ps: see cmd_ps
* @mode: the target ps mode to be check
*/
static bool _chk_ps_cap(struct cmd_ps *ps, u8 mode)
{
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): mode(%s), lps_en(%d), ips_en(%d), runtime stop reason(0x%x).\n",
__func__, phl_ps_ps_mode_to_str(mode), ps_cap->lps_en, ps_cap->ips_en, ps->rt_stop_rson);
switch (mode) {
case PS_MODE_LPS:
if (ps_cap->lps_en == PS_OP_MODE_DISABLED) {
return false;
} else if (ps_cap->lps_en == PS_OP_MODE_FORCE_ENABLED) {
/* force enable */
return true;
} else if (ps_cap->lps_en == PS_OP_MODE_AUTO) {
if (ps->rt_stop_rson == PS_RT_RSON_NONE)
return true;
}
break;
case PS_MODE_IPS:
if (ps_cap->ips_en == PS_OP_MODE_DISABLED) {
return false;
} else if (ps_cap->ips_en == PS_OP_MODE_FORCE_ENABLED) {
/* force enable */
return true;
} else if (ps_cap->ips_en == PS_OP_MODE_AUTO) {
if (ps->rt_stop_rson == PS_RT_RSON_NONE)
return true;
}
break;
default:
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): unknown ps mode.\n", __func__);
return false;
}
return false;
}
/**
* check the condition of ips
* return whether to enter ips or not
* @ps: see cmd_ps
*/
static bool _chk_ips_enter(struct cmd_ps *ps)
{
if (TEST_STATUS_FLAG(ps->phl_info->phl_com->dev_state, RTW_DEV_RESUMING)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): resume in progress.\n", __func__);
return false;
}
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return false;
}
if (!_chk_ps_cap(ps, PS_MODE_IPS)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): ips is not allowed.\n", __func__);
return false;
}
if (!phl_disp_eng_is_fg_empty(ps->phl_info, HW_BAND_0)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): fg exist.\n", __func__);
return false;
}
if (ps->req_busy_q.cnt) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): req q is not empty.\n", __func__);
return false;
}
if (ps->btc_req_pwr) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): btc req pwr.\n", __func__);
return false;
}
if (!_chk_wrole_with_ps_mode(ps, PS_MODE_IPS, NULL)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): no need to enter ips.\n", __func__);
return false;
}
return true;
}
/**
* check the condition of lps
* return whether to enter lps or not
* @ps: see cmd_ps
*/
static bool _chk_lps_enter(struct cmd_ps *ps, u16 *macid)
{
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(ps->phl_info);
/* check enter lps or not */
if (TEST_STATUS_FLAG(ps->phl_info->phl_com->dev_state, RTW_DEV_RESUMING)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): resume in progress.\n", __func__);
return false;
}
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return false;
}
/* check capability */
if (!_chk_ps_cap(ps, PS_MODE_LPS)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): lps is not allowed.\n", __func__);
return false;
}
/* check fg module */
if (!phl_disp_eng_is_fg_empty(ps->phl_info, HW_BAND_0)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): fg exist.\n", __func__);
return false;
}
/* ref cnt */
if (ps->req_busy_q.cnt) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): req q is not empty.\n", __func__);
return false;
}
/* btc */
if (ps->btc_req_pwr) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): btc req pwr.\n", __func__);
return false;
}
if (ps->pre_phase_leave_ps == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): just leave ps in watchdog prephase.\n", __func__);
return false;
}
/* check wifi role */
if (!_chk_wrole_with_ps_mode(ps, PS_MODE_LPS, macid)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): no need to enter lps.\n", __func__);
return false;
}
/* lps */
if (_lps_state_judge_changed(ps, *macid, ps->ps_state, PS_STATE_ENTERED)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): lps state changed.\n", __func__);
/* check data path stop or not */
if (ps_cap->lps_pause_tx) {
if (!_is_datapath_active(ps)) {
return true;
} else {
if (_stop_datapath(ps) == RTW_PHL_STATUS_SUCCESS)
return true;
}
} else {
return true;
}
}
return false;
}
static void _ps_watchdog_info_dump(struct cmd_ps *ps)
{
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "========== CMD PS Info ========== \n");
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "ps mode(%s), pwr lvl(%s), ps state(%s)\n",
phl_ps_ps_mode_to_str(ps->ps_mode),
phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl),
_ps_state_to_str(ps->ps_state));
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "req idle cnt(%d), req busy cnt(%d)\n",
ps->req_idle_q.cnt, ps->req_busy_q.cnt);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "ap active(%s), gc active(%s)\n",
(ps->mr_info.ap_active ? "yes" : "no"), (ps->mr_info.gc_active ? "yes" : "no"));
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "reject all pwr req(%s), btc req pwr(%s), runtime stop reason(0x%x)\n",
(ps->rej_pwr_req ? "yes" : "no"), (ps->btc_req_pwr ? "yes" : "no"), ps->rt_stop_rson);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "========== CMD PS Info ========== \n");
}
/**
* pre-phase handler of watchdog
* will check whether to leave lps or not
* @ps: see cmd_ps
*/
static enum phl_mdl_ret_code
_ps_watchdog_pre_hdlr(struct cmd_ps *ps)
{
/* check leave lps or not */
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): pwr lvl(%s).\n", __func__, phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl));
ps->pre_phase_leave_ps = false;
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return MDL_RET_CANNOT_IO;
}
if (ps->ps_mode == PS_MODE_IPS) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): power off.\n", __func__);
return MDL_RET_CANNOT_IO;
}
if (ps->ps_state == PS_STATE_LEAVED) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): not in power saving.\n", __func__);
return MDL_RET_SUCCESS;
} else {
if (_lps_state_judge_changed(ps, ps->macid, ps->ps_state, PS_STATE_LEAVED)) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): lps state changed.\n", __func__);
if (_leave_ps(ps, true, "watchdog") == RTW_PHL_STATUS_SUCCESS) {
ps->pre_phase_leave_ps = true;
_leave_success_hdlr(ps);
return MDL_RET_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): going to L2 reset!\n", __func__);
_leave_fail_hdlr(ps);
return MDL_RET_CANNOT_IO;
}
}
if (ps->ps_state == PS_STATE_PROTO)
return MDL_RET_SUCCESS;
else
return MDL_RET_CANNOT_IO;
}
}
/**
* post-phase handler of watchdog
* will check whether to enter lps or not
* @ps: see cmd_ps
*/
static enum phl_mdl_ret_code
_ps_watchdog_post_hdlr(struct cmd_ps *ps)
{
u16 macid = 0xFFFF;
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): pwr lvl(%s).\n", __func__, phl_ps_pwr_lvl_to_str(ps->cur_pwr_lvl));
if (_chk_lps_enter(ps, &macid))
_enter_ps(ps, PS_MODE_LPS, macid, "watchdog");
else if (_chk_ips_enter(ps))
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "watchdog");
_ps_watchdog_info_dump(ps);
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code _phy_on_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return MDL_RET_CANNOT_IO;
}
if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_PHY_ON\n");
if (_leave_ps(ps, true, "phy on") == RTW_PHL_STATUS_SUCCESS) {
_add_pwr_req(ps, MSG_EVT_ID_FIELD(msg->msg_id));
_leave_success_hdlr(ps);
ret = MDL_RET_SUCCESS;
} else {
_leave_fail_hdlr(ps);
}
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
static enum phl_mdl_ret_code _tx_pwr_req_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return MDL_RET_CANNOT_IO;
}
if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_TRX_PWR_REQ\n");
if (_leave_ps(ps, false, "tx req") == RTW_PHL_STATUS_SUCCESS) {
_leave_success_hdlr(ps);
ret = MDL_RET_SUCCESS;
} else {
_leave_fail_hdlr(ps);
}
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
static enum phl_mdl_ret_code _phy_idle_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_PHY_IDLE\n");
_cancel_pwr_req(ps, MSG_EVT_ID_FIELD(msg->msg_id));
/* check enter ips or not */
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): try enter ips.\n", __func__);
if (_chk_ips_enter(ps)) {
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "phy idle");
}
ret = MDL_RET_SUCCESS;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
/**
* pre-phase handler of msg
* leave ps and return corresponding status
* @ps: see cmd_ps
* @evt_id: evt id of msg
*/
static enum phl_mdl_ret_code
_ext_msg_pre_hdlr(struct cmd_ps *ps, u16 evt_id)
{
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return MDL_RET_CANNOT_IO;
}
/* power request */
if (_leave_ps(ps, true, "ext msg req") == RTW_PHL_STATUS_SUCCESS) {
_add_pwr_req(ps, evt_id);
_leave_success_hdlr(ps);
return MDL_RET_SUCCESS;
} else {
_leave_fail_hdlr(ps);
}
return MDL_RET_CANNOT_IO;
}
/**
* post-phase handler of msg
* cancel power req and chk enter ips or not
* @ps: see cmd_ps
* @evt_id: evt id of msg
*/
static enum phl_mdl_ret_code
_ext_msg_post_hdlr(struct cmd_ps *ps, u16 evt_id)
{
/* cancel power request */
_cancel_pwr_req(ps, evt_id);
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): try enter ips.\n", __func__);
if (_chk_ips_enter(ps)) {
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "ext msg done");
}
return MDL_RET_SUCCESS;
}
static void _ps_mr_info_upt(struct cmd_ps *ps, struct rtw_wifi_role_t *role)
{
struct phl_info_t *phl_info = ps->phl_info;
struct rtw_wifi_role_t *wr = NULL;
u8 role_idx = 0;
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): id %d, type %d, mstate %d\n", __func__,
role->id, role->type, role->mstate);
#ifdef RTW_WKARD_PHL_NTFY_MEDIA_STS
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): is_gc %d\n", __func__, role->is_gc);
#endif
_os_mem_set(phl_to_drvpriv(phl_info), &ps->mr_info, 0, sizeof(struct _ps_mr_info));
for (role_idx = 0; role_idx < MAX_WIFI_ROLE_NUMBER; role_idx++) {
wr = &(phl_info->phl_com->wifi_roles[role_idx]);
if (wr->active == false)
continue;
#ifdef RTW_WKARD_PHL_NTFY_MEDIA_STS
if (wr->type == PHL_RTYPE_STATION) {
if(wr->is_gc == true && wr->mstate != MLME_NO_LINK)
ps->mr_info.gc_active = true;
}
#endif
if (wr->type == PHL_RTYPE_AP || wr->type == PHL_RTYPE_VAP ||
wr->type == PHL_RTYPE_MESH ||wr->type == PHL_RTYPE_P2P_GO)
ps->mr_info.ap_active = (wr->mstate == MLME_NO_LINK) ? false : true;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): gc_active %d, ap_active %d\n", __func__,
ps->mr_info.gc_active, ps->mr_info.ap_active);
}
static bool _is_ignored_mrc_evt(u16 evt_id)
{
return false;
}
static enum phl_mdl_ret_code
_mrc_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
struct rtw_role_cmd *rcmd = NULL;
struct rtw_wifi_role_t *role = NULL;
if (_is_ignored_mrc_evt(MSG_EVT_ID_FIELD(msg->msg_id)))
return MDL_RET_SUCCESS;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_ROLE_NTFY:
if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
if (msg->inbuf && (msg->inlen == sizeof(struct rtw_role_cmd))) {
rcmd = (struct rtw_role_cmd *)msg->inbuf;
role = rcmd->wrole;
_ps_mr_info_upt(ps, role);
}
}
ret = MDL_RET_SUCCESS;
break;
default:
if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_CANNOT_IO;
} else {
ret = MDL_RET_SUCCESS;
}
break;
}
return ret;
}
static bool _is_ignored_ser_evt(u16 evt_id)
{
if (MSG_EVT_SER_M9_L2_RESET != evt_id)
return true;
return false;
}
static enum phl_mdl_ret_code
_ser_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (_is_ignored_ser_evt(MSG_EVT_ID_FIELD(msg->msg_id)))
return MDL_RET_SUCCESS;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_SER_M9_L2_RESET:
ret = MDL_RET_SUCCESS;
break;
default:
if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n",
__func__,
MSG_MDL_ID_FIELD(msg->msg_id),
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_CANNOT_IO;
} else {
ret = MDL_RET_SUCCESS;
}
break;
}
return ret;
}
static bool _is_ignored_general_evt(u16 evt_id)
{
return false;
}
#ifdef RTW_WKARD_LINUX_CMD_WKARD
static enum phl_mdl_ret_code
_linux_cmd_wkard_hdlr(struct cmd_ps *ps)
{
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return MDL_RET_CANNOT_IO;
}
/* power request */
if (_leave_ps(ps, true, "linux cmd wkard") == RTW_PHL_STATUS_SUCCESS) {
_leave_success_hdlr(ps);
return MDL_RET_SUCCESS;
} else {
_leave_fail_hdlr(ps);
}
return MDL_RET_CANNOT_IO;
}
#endif /* RTW_WKARD_LINUX_CMD_WKARD */
static enum phl_mdl_ret_code
_general_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (_is_ignored_general_evt(MSG_EVT_ID_FIELD(msg->msg_id)))
return MDL_RET_SUCCESS;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_CHG_OP_CH_DEF_START:
case MSG_EVT_CHG_OP_CH_DEF_END:
case MSG_EVT_SWCH_START:
case MSG_EVT_PCIE_TRX_MIT:
case MSG_EVT_FORCE_USB_SW:
case MSG_EVT_GET_USB_SPEED:
case MSG_EVT_GET_USB_SW_ABILITY:
case MSG_EVT_CFG_AMPDU:
case MSG_EVT_DFS_PAUSE_TX:
case MSG_EVT_ROLE_RECOVER:
case MSG_EVT_ROLE_SUSPEND:
case MSG_EVT_HAL_SET_L2_LEAVE:
case MSG_EVT_NOTIFY_HAL:
case MSG_EVT_ISSUE_BCN:
case MSG_EVT_STOP_BCN:
case MSG_EVT_SEC_KEY:
case MSG_EVT_ROLE_START:
case MSG_EVT_ROLE_CHANGE:
case MSG_EVT_ROLE_STOP:
case MSG_EVT_STA_INFO_CTRL:
case MSG_EVT_STA_MEDIA_STATUS_UPT:
case MSG_EVT_CFG_CHINFO:
case MSG_EVT_STA_CHG_STAINFO:
#ifdef RTW_WKARD_LINUX_CMD_WKARD
case MSG_EVT_LINUX_CMD_WRK_TRI_PS:
#endif /* RTW_WKARD_LINUX_CMD_WKARD */
case MSG_EVT_DBG_RX_DUMP:
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) in %s phase.\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id),
(IS_MSG_IN_PRE_PHASE(msg->msg_id) ? "pre-protocol" : "post-protocol"));
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
ret = _ext_msg_pre_hdlr(ps, MSG_EVT_ID_FIELD(msg->msg_id));
else
ret = _ext_msg_post_hdlr(ps, MSG_EVT_ID_FIELD(msg->msg_id));
break;
#ifdef RTW_WKARD_LINUX_CMD_WKARD
case MSG_EVT_LINUX_CMD_WRK:
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
ret = _linux_cmd_wkard_hdlr(ps);
else
ret = MDL_RET_SUCCESS;
break;
#endif /* RTW_WKARD_LINUX_CMD_WKARD */
case MSG_EVT_WATCHDOG:
if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
ret = _ps_watchdog_pre_hdlr(ps);
if (ret == MDL_RET_SUCCESS) {
ps->rssi_bcn_min = phl_get_min_rssi_bcn(ps->phl_info);
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): update rssi_bcn_min to %d\n", __func__, ps->rssi_bcn_min);
}
} else {
ret = _ps_watchdog_post_hdlr(ps);
}
break;
case MSG_EVT_RF_ON:
if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_RF_ON\n");
ps->rej_pwr_req = false;
}
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_RF_OFF:
if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], MSG_EVT_RF_OFF\n");
ps->rej_pwr_req = true;
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "msg rf off");
}
ret = MDL_RET_SUCCESS;
break;
case MSG_EVT_PHY_ON:
ret = _phy_on_msg_hdlr(ps, msg);
break;
case MSG_EVT_PHY_IDLE:
ret = _phy_idle_msg_hdlr(ps, msg);
break;
default:
if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n",
__func__,
MSG_MDL_ID_FIELD(msg->msg_id),
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_CANNOT_IO;
} else {
ret = MDL_RET_SUCCESS;
}
break;
}
return ret;
}
static bool _is_ignored_datapath_evt(u16 evt_id)
{
return false;
}
static enum phl_mdl_ret_code
_datapath_mdl_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (_is_ignored_datapath_evt(MSG_EVT_ID_FIELD(msg->msg_id)))
return MDL_RET_SUCCESS;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_TRX_PWR_REQ:
ret = _tx_pwr_req_msg_hdlr(ps, msg);
break;
default:
if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n",
__func__,
MSG_MDL_ID_FIELD(msg->msg_id),
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_CANNOT_IO;
} else {
ret = MDL_RET_SUCCESS;
}
break;
}
return ret;
}
/**
* bypass msg of specific module
* @msg: see phl_msg
*/
static bool _is_ignored_mdl(struct phl_msg *msg)
{
if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_BTC)
return true;
if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_LED)
return true;
return false;
}
static enum phl_mdl_ret_code
_ps_mdl_hdl_external_evt(void *dispr, struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
if (_is_ignored_mdl(msg)) {
/* PHL_INFO("[PS_CMD], %s(): ignore MDL_ID(%d)-EVT_ID(%d).\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id)); */
return MDL_RET_SUCCESS;
}
switch (MSG_MDL_ID_FIELD(msg->msg_id)) {
case PHL_MDL_GENERAL:
ret = _general_mdl_msg_hdlr(ps, msg);
break;
case PHL_MDL_MRC:
ret = _mrc_mdl_msg_hdlr(ps, msg);
break;
case PHL_MDL_TX:
case PHL_MDL_RX:
ret = _datapath_mdl_msg_hdlr(ps, msg);
break;
case PHL_MDL_SER:
ret = _ser_mdl_msg_hdlr(ps, msg);
break;
/* handle ohters mdl here */
default:
if (ps->cur_pwr_lvl != PS_PWR_LVL_PWRON) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) get cannot I/O!\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_CANNOT_IO;
} else {
ret = MDL_RET_SUCCESS;
}
break;
}
return ret;
}
static enum phl_mdl_ret_code _ps_cap_chg_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_ps_rt_rson rt_rson = PS_RT_RSON_NONE;
bool ps_allow = false;
struct rt_ps *rt_ps_info= NULL;
if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
rt_ps_info = (struct rt_ps *)msg->inbuf;
ps_allow = rt_ps_info->ps_allow;
rt_rson = rt_ps_info->rt_rson;
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): update -> ps_allow(%d), reason(%d).\n", __func__, ps_allow, rt_rson);
if (ps_allow) {
if (TEST_STATUS_FLAG(ps->rt_stop_rson, rt_rson) == true)
CLEAR_STATUS_FLAG(ps->rt_stop_rson, rt_rson);
else
return MDL_RET_SUCCESS;
} else {
if (TEST_STATUS_FLAG(ps->rt_stop_rson, rt_rson) == false)
SET_STATUS_FLAG(ps->rt_stop_rson, rt_rson);
else
return MDL_RET_SUCCESS;
}
if (ps->rej_pwr_req == true) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): reject pwr req.\n", __func__);
return MDL_RET_CANNOT_IO;
}
if (ps->rt_stop_rson != PS_RT_RSON_NONE) {
if (_leave_ps(ps, true, "cap chg") == RTW_PHL_STATUS_SUCCESS) {
_leave_success_hdlr(ps);
return MDL_RET_SUCCESS;
} else {
_leave_fail_hdlr(ps);
return MDL_RET_CANNOT_IO;
}
}
} else {
if (ps->rt_stop_rson == PS_RT_RSON_NONE) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): try enter ips.\n", __func__);
if (_chk_ips_enter(ps)) {
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "cap chg");
}
}
}
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code _ps_period_chk_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
u16 macid = 0xFFFF;
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
return MDL_RET_SUCCESS;
if (ps->ps_state == PS_STATE_LEAVED) {
PHL_TRACE(COMP_PHL_PS, _PHL_DEBUG_, "[PS_CMD], %s(): \n", __func__);
if (_chk_lps_enter(ps, &macid))
_enter_ps(ps, PS_MODE_LPS, macid, "period chk");
/* else if (_chk_ips_enter(ps))
_enter_ps(ps, PS_MODE_IPS, 0xFFFF, "period chk"); */
}
_os_set_timer(phl_to_drvpriv(ps->phl_info), &ps->ps_timer, CMD_PS_TIMER_PERIOD);
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code _ps_dbg_lps_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
u16 macid = 0xFFFF;
u16 evt_id = MSG_EVT_ID_FIELD(msg->msg_id);
if (evt_id == MSG_EVT_PS_DBG_LPS_ENTER) {
if (!IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
if (!_chk_wrole_with_ps_mode(ps, PS_MODE_LPS, &macid))
return MDL_RET_SUCCESS;
_enter_ps(ps, PS_MODE_LPS, macid, "dbg lps enter");
ps->rej_pwr_req = true;
}
} else { /* MSG_EVT_PS_DBG_LPS_LEAVE */
if (IS_MSG_IN_PRE_PHASE(msg->msg_id)) {
_leave_ps(ps, true, "dbg lps leave");
ps->rej_pwr_req = false;
}
}
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code _ps_dbg_ips_msg_hdlr(struct cmd_ps *ps, struct phl_msg *msg)
{
/* fw do not support ips currently */
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code
_ps_mdl_hdl_internal_evt(void *dispr, struct cmd_ps *ps, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_CANNOT_IO;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_PHY_ON:
ret = _phy_on_msg_hdlr(ps, msg);
break;
case MSG_EVT_PHY_IDLE:
ret = _phy_idle_msg_hdlr(ps, msg);
break;
case MSG_EVT_PS_CAP_CHG:
ret = _ps_cap_chg_msg_hdlr(ps, msg);
break;
case MSG_EVT_PS_PERIOD_CHK:
ret = _ps_period_chk_hdlr(ps, msg);
break;
case MSG_EVT_PS_DBG_LPS_ENTER:
case MSG_EVT_PS_DBG_LPS_LEAVE:
ret = _ps_dbg_lps_msg_hdlr(ps, msg);
break;
case MSG_EVT_PS_DBG_IPS_ENTER:
case MSG_EVT_PS_DBG_IPS_LEAVE:
ret = _ps_dbg_ips_msg_hdlr(ps, msg);
break;
default:
ret = MDL_RET_CANNOT_IO;
break;
}
return ret;
}
static enum phl_mdl_ret_code
_ps_mdl_msg_hdlr(void *dispr, void *priv, struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct cmd_ps *ps = (struct cmd_ps *)priv;
if (IS_MSG_FAIL(msg->msg_id)) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): MDL_ID(%d)-EVT_ID(%d) fail.\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
return MDL_RET_SUCCESS;
}
switch (MSG_MDL_ID_FIELD(msg->msg_id)) {
case PHL_MDL_POWER_MGNT:
ret = _ps_mdl_hdl_internal_evt(dispr, ps, msg);
break;
default:
ret = _ps_mdl_hdl_external_evt(dispr, ps, msg);
break;
}
return ret;
}
static enum phl_mdl_ret_code
_ps_mdl_set_info(void *dispr, void *priv, struct phl_module_op_info *info)
{
struct cmd_ps *ps = (struct cmd_ps *)priv;
switch (info->op_code) {
case PS_MDL_OP_CANCEL_PWR_REQ:
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): cancel pwr req, evt_id %d\n", __func__, *(u16 *)info->inbuf);
if (ps->rej_pwr_req == false)
_cancel_pwr_req(ps, *(u16 *)info->inbuf);
break;
case PS_MDL_OP_BTC_PWR_REQ:
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): btc req pwr %d\n", __func__, *(bool *)info->inbuf);
ps->btc_req_pwr = *(bool *)info->inbuf;
break;
}
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code
_ps_mdl_query_info(void *dispr, void *priv, struct phl_module_op_info *info)
{
struct cmd_ps *ps = (struct cmd_ps *)priv;
u8 pwr_lvl = PS_PWR_LVL_PWROFF;
struct phl_cmd_ps_basic_info *basic_info = NULL;
/* PHL_INFO("[PS_CMD], %s(): opcode %d.\n", __func__, info->op_code); */
switch (info->op_code) {
case PS_MDL_OP_CUR_PWR_LVL:
pwr_lvl = ps->cur_pwr_lvl;
_os_mem_cpy(phl_to_drvpriv(ps->phl_info), (void *)info->inbuf,
&pwr_lvl, sizeof(pwr_lvl));
break;
case PS_MDL_OP_BASIC_INFO:
basic_info = (struct phl_cmd_ps_basic_info *)info->inbuf;
basic_info->ps_mode = ps->ps_mode;
basic_info->cur_pwr_lvl = ps->cur_pwr_lvl;
basic_info->rej_pwr_req = ps->rej_pwr_req;
basic_info->btc_req_pwr = ps->btc_req_pwr;
basic_info->rt_stop_rson = ps->rt_stop_rson;
basic_info->ap_active = ps->mr_info.ap_active;
basic_info->gc_active = ps->mr_info.gc_active;
basic_info->sta = ps->sta;
/* enter/leave ps reason */
_os_mem_set(phl_to_drvpriv(ps->phl_info), basic_info->enter_rson, 0, MAX_CMD_PS_RSON_LENGTH);
_os_mem_cpy(phl_to_drvpriv(ps->phl_info), basic_info->enter_rson, ps->enter_rson, MAX_CMD_PS_RSON_LENGTH);
_os_mem_set(phl_to_drvpriv(ps->phl_info), basic_info->leave_rson, 0, MAX_CMD_PS_RSON_LENGTH);
_os_mem_cpy(phl_to_drvpriv(ps->phl_info), basic_info->leave_rson, ps->leave_rson, MAX_CMD_PS_RSON_LENGTH);
break;
}
return MDL_RET_SUCCESS;
}
enum rtw_phl_status phl_register_ps_module(struct phl_info_t *phl_info)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_cmd_dispatch_engine *disp_eng = &(phl_info->disp_eng);
struct phl_bk_module_ops bk_ops = {0};
u8 i = 0;
PHL_INFO("[PS_CMD], %s(): \n", __func__);
bk_ops.init = _ps_mdl_init;
bk_ops.deinit = _ps_mdl_deinit;
bk_ops.start = _ps_mdl_start;
bk_ops.stop = _ps_mdl_stop;
bk_ops.msg_hdlr = _ps_mdl_msg_hdlr;
bk_ops.set_info = _ps_mdl_set_info;
bk_ops.query_info = _ps_mdl_query_info;
for (i = 0; i < disp_eng->phy_num; i++) {
phl_status = phl_disp_eng_register_module(phl_info, i,
PHL_MDL_POWER_MGNT, &bk_ops);
if (phl_status != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("register cmd PS module of phy%d failed.\n", i + 1);
break;
}
}
return phl_status;
}
u8 phl_ps_get_cur_pwr_lvl(struct phl_info_t *phl_info)
{
struct phl_module_op_info op_info = {0};
u8 pwr_lvl = PS_PWR_LVL_MAX;
op_info.op_code = PS_MDL_OP_CUR_PWR_LVL;
op_info.inbuf = (u8 *)&pwr_lvl;
op_info.inlen = sizeof(pwr_lvl);
phl_disp_eng_query_bk_module_info(phl_info, HW_BAND_0,
PHL_MDL_POWER_MGNT, &op_info);
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): pwr lvl(%s)\n", __func__, phl_ps_pwr_lvl_to_str(pwr_lvl));
return pwr_lvl;
}
bool phl_ps_is_datapath_allowed(struct phl_info_t *phl_info)
{
struct phl_module_op_info op_info = {0};
bool io_allowed = false;
u8 pwr_lvl = PS_PWR_LVL_MAX;
struct rtw_ps_cap_t *ps_cap = _get_ps_cap(phl_info);
if (!ps_cap->lps_pause_tx)
return true;
op_info.op_code = PS_MDL_OP_CUR_PWR_LVL;
op_info.inbuf = (u8 *)&pwr_lvl;
op_info.inlen = sizeof(pwr_lvl);
phl_disp_eng_query_bk_module_info(phl_info, HW_BAND_0,
PHL_MDL_POWER_MGNT, &op_info);
if (pwr_lvl == PS_PWR_LVL_PWRON)
io_allowed = true;
return io_allowed;
}
static void _ps_set_rt_cap_done(void *priv, struct phl_msg *msg)
{
struct phl_info_t *phl_info = (struct phl_info_t *)priv;
if (msg->inbuf && msg->inlen) {
_os_mem_free(phl_to_drvpriv(phl_info),
msg->inbuf, msg->inlen);
}
}
void rtw_phl_ps_set_rt_cap(void *phl, u8 band_idx, bool ps_allow, enum phl_ps_rt_rson rt_rson)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
struct rt_ps *ps_rt_info = NULL;
ps_rt_info = (struct rt_ps *)_os_mem_alloc(phl_to_drvpriv(phl_info), sizeof(struct rt_ps));
if (ps_rt_info == NULL) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to alloc ps_rt_info memory.\n", __func__);
return;
}
ps_rt_info->rt_rson = rt_rson;
ps_rt_info->ps_allow = ps_allow;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_PS_CAP_CHG);
msg.band_idx = band_idx;
msg.inbuf = (u8*)ps_rt_info;
msg.inlen = sizeof(struct rt_ps);
attr.completion.completion = _ps_set_rt_cap_done;
attr.completion.priv = phl_info;
if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) !=
RTW_PHL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to notify batter change.\n", __func__);
goto cmd_fail;
}
return;
cmd_fail:
_os_mem_free(phl_to_drvpriv(phl_info), ps_rt_info, sizeof(ps_rt_info));
}
void phl_ps_dbg_set_ps(struct phl_info_t *phl_info, u8 ps_mode, bool enter)
{
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
u16 evt_id = 0;
if (ps_mode == PS_MODE_LPS) {
evt_id = (enter ? MSG_EVT_PS_DBG_LPS_ENTER : MSG_EVT_PS_DBG_LPS_LEAVE);
} else if (ps_mode == PS_MODE_IPS) {
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[PS_CMD], %s(): dbg ips is not support now.\n", __func__);
/* evt_id = (enter ? MSG_EVT_PS_DBG_IPS_ENTER : MSG_EVT_PS_DBG_IPS_LEAVE); */
} else {
return;
}
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_, "[PS_CMD], %s(): debug set %s %s\n", __func__,
phl_ps_ps_mode_to_str(ps_mode), (enter ? "enter" : "leave"));
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_POWER_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id);
msg.band_idx = HW_BAND_0;
if (phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) !=
RTW_PHL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[PS_CMD], %s(): fail to set dbg ps.\n", __func__);
}
return;
}
enum rtw_phl_status
rtw_phl_ps_set_rf_state(void *phl, u8 band_idx, enum rtw_rf_state rf_state)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
enum phl_msg_evt_id evt_id = (rf_state == RTW_RF_ON) ? MSG_EVT_RF_ON : MSG_EVT_RF_OFF;
phl_cmd_enqueue(phl_info, band_idx, evt_id, NULL, 0, NULL, PHL_CMD_WAIT, 0);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status phl_ps_hal_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl_com->phl_priv;
struct phl_module_op_info op_info = {0};
if (src != HAL_BTC_PWR_REQ)
return RTW_PHL_STATUS_FAILURE;
op_info.op_code = PS_MDL_OP_BTC_PWR_REQ;
op_info.inbuf = (u8 *)&pwr_req;
status = phl_disp_eng_set_bk_module_info(phl_info, HW_BAND_0,
PHL_MDL_POWER_MGNT, &op_info);
return status;
}
#endif
|
2301_81045437/rtl8852be
|
phl/phl_cmd_ps.c
|
C
|
agpl-3.0
| 54,185
|
/******************************************************************************
*
* Copyright(c) 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CMD_PS_H_
#define _PHL_CMD_PS_H_
#ifdef CONFIG_POWER_SAVE
enum ps_mdl_opcode {
PS_MDL_OP_NONE = 0,
PS_MDL_OP_CANCEL_PWR_REQ,
PS_MDL_OP_CUR_PWR_LVL,
PS_MDL_OP_BASIC_INFO,
PS_MDL_OP_BTC_PWR_REQ
};
#define MAX_CMD_PS_RSON_LENGTH 30
struct phl_cmd_ps_basic_info {
u8 ps_mode;
u8 cur_pwr_lvl;
bool rej_pwr_req;
bool btc_req_pwr;
enum phl_ps_rt_rson rt_stop_rson;
bool ap_active;
bool gc_active;
struct rtw_phl_stainfo_t *sta;
char enter_rson[MAX_CMD_PS_RSON_LENGTH];
char leave_rson[MAX_CMD_PS_RSON_LENGTH];
};
enum rtw_phl_status phl_register_ps_module(struct phl_info_t *phl_info);
u8 phl_ps_get_cur_pwr_lvl(struct phl_info_t *phl_info);
bool phl_ps_is_datapath_allowed(struct phl_info_t *phl_info);
void rtw_phl_ps_set_rt_cap(void *phl, u8 band_idx, bool ps_allow, enum phl_ps_rt_rson rt_rson);
void phl_ps_dbg_set_ps(struct phl_info_t *phl_info, u8 ps_mode, bool enter);
#endif
#endif /* _PHL_CMD_PS_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_ps.h
|
C
|
agpl-3.0
| 1,585
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* Author: vincent_fann@realtek.com
*
*****************************************************************************/
#define _PHL_CMD_SCAN_C_
#include "phl_headers.h"
#include "phl_scan.h"
#define param_to_phlcom(_param) (_param->wifi_role->phl_com)
#ifdef CONFIG_PHL_CMD_SCAN
enum _CMD_SCAN_STATE {
CMD_SCAN_ACQUIRE = BIT0,
CMD_SCAN_STARTED = BIT1,
CMD_SCAN_DF_IO = BIT2, /* Disable Function : IO */
};
static void _cmd_scan_timer(void* role);
#define DBG_SCAN_CHAN_DUMP
#ifdef DBG_SCAN_CHAN_DUMP
static void
_cmd_estimated_swch_seq(struct rtw_phl_scan_param *param, u8 op_num)
{
u8 chidx = 0;
u8 opidx = 0;
u8 total_ch_num = 0;
if ((param->back_op_mode == SCAN_BKOP_CNT) &&
(param->back_op_ch_cnt == 0)) {
PHL_ERR("%s bkop_cnt == 0\n", __func__);
_os_warn_on(1);
return;
}
/*swicth channel sequence by cmd_scan's estimated */
PHL_INFO("%s:: Estimated channel sequence:\n", __func__);
if (param->back_op_mode == SCAN_BKOP_CNT) {
PHL_INFO("[SCAN_BKOP_CNT]\n");
for(chidx = 0; chidx < param->ch_num; chidx++) {
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "%3d, ", param->ch[chidx].channel);
total_ch_num++;
if(!((chidx + 1) % param->back_op_ch_cnt)) {
if (op_num) {
for(opidx = 0; opidx < op_num; opidx++) {
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_,
"[%3d], ", param->back_op_ch[opidx].channel);
total_ch_num++;
}
}
}
if(!((chidx + 1) % (param->back_op_ch_cnt * 2)))
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n");
}
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n");
}
#ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME
else if (param->back_op_mode == SCAN_BKOP_TIMER) {
u16 ch_dur;
PHL_INFO("[SCAN_BKOP_TIMER]\n");
for(chidx = 0; chidx < param->ch_num; chidx++) {
total_ch_num++;
ch_dur = (op_num) ? param->back_op_off_ch_dur_ms : param->ch[chidx].duration;
PHL_INFO("\t%3d, dur:%d(ms)\n", param->ch[chidx].channel, ch_dur);
}
if (op_num) {
for(opidx = 0; opidx < op_num; opidx++) {
total_ch_num++;
PHL_INFO("\t[%3d], dur:%d(ms)\n",
param->back_op_ch[opidx].channel, param->back_op_ch[opidx].duration);
}
}
PHL_INFO("max_listen_time:%d (ms)\n", param->max_listen_time);
PHL_INFO("op_ch_dur_ms:%d, off_ch_dur_ms:%d, off_ch_ext_dur_ms:%d (ms)",
param->back_op_ch_dur_ms,
param->back_op_off_ch_dur_ms,
param->back_op_off_ch_ext_dur_ms);
}
#endif
else if (param->back_op_mode == SCAN_BKOP_NONE) {
PHL_INFO("[SCAN_BKOP_NONE]\n");
for(chidx = 0; chidx < param->ch_num; chidx++) {
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "%3d, ", param->ch[chidx].channel);
total_ch_num++;
if(!((chidx + 1) % 6))
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n");
}
PHL_DATA(COMP_PHL_DBG, _PHL_INFO_, "\n");
}
PHL_INFO("Scan chan num:%d , Total num:%d, repeat:%d\n",
param->ch_num, total_ch_num, param->repeat);
PHL_INFO("--------\n");
}
#endif /*DBG_SCAN_CHAN_DUMP*/
static void
_cmd_scan_update_chlist(void *drv, struct rtw_phl_scan_param *param)
{
u8 idx = 0;
INIT_LIST_HEAD(¶m->chlist.queue);
for(idx = 0; idx < param->ch_num; idx++) {
INIT_LIST_HEAD(¶m->ch[idx].list);
pq_push(drv, ¶m->chlist, ¶m->ch[idx].list, _tail, _ps);
}
}
/*
* Insert op channel list
* Ex. ch_intvl =3
* ch_idx : -1, 0, 1, 2, 3, 4, 5, 6
* ^ ^
* op0~op5 op0~op5
*
* => 0,1,2,[op0],[op1],3,4,5,[op0],[op1],6,7,8,[op0],[op1]
*/
static inline void
_cmd_scan_enqueue_opch(void *drv, struct rtw_phl_scan_param *param, struct phl_queue *q)
{
u8 idx = 0;
for(idx = 0; idx < MAX_WIFI_ROLE_NUMBER; idx ++) {
if(param->back_op_ch[idx].channel)
pq_push(drv, ¶m->chlist, ¶m->back_op_ch[idx].list, _first, _ps);
else
break;
}
}
static struct phl_scan_channel *_cmd_scan_select_chnl(
void *drv, struct rtw_phl_scan_param *param)
{
struct phl_scan_channel *scan_ch = NULL;
_os_list* obj = NULL;
bool back_op_is_required = (param->back_op_ch[0].channel)? true:false;
next_ch:
if(pq_pop(drv, ¶m->chlist, &obj, _first, _ps)) {
scan_ch = (struct phl_scan_channel*)obj;
if(scan_ch->scan_mode == NORMAL_SCAN_MODE) {
/* 1- enable, 2- BK_CNT mode, 3- prev is non-op, 4- ch_intvl's turn */
if (back_op_is_required && param->back_op_mode == SCAN_BKOP_CNT) {
if(param->scan_ch &&
!((param->ch_idx + 1) % param->back_op_ch_cnt)) {
_cmd_scan_enqueue_opch(drv, param, ¶m->chlist);
}
}
param->ch_idx++;
}
#ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME
else if (scan_ch->scan_mode == P2P_LISTEN_MODE) {
if (back_op_is_required && param->back_op_mode == SCAN_BKOP_TIMER) {
scan_ch->duration = param->back_op_off_ch_dur_ms;
_cmd_scan_enqueue_opch(drv, param, ¶m->chlist);
}
param->ch_idx++;
}
#endif
param->scan_ch = scan_ch;
}
else if(param->repeat > 0) {
_cmd_scan_update_chlist(drv, param);
param->ch_idx = 0;
/* 255 means loop forever */
if (param->repeat != 255)
param->repeat--;
goto next_ch;
}
else {
return NULL;
}
PHL_INFO("%s: repeat[%d] ch_idx=[%d/%d], ch_number=%d, scan_mode= %s\n", __func__,
param->repeat, param->ch_idx, param->ch_num, param->scan_ch->channel,
(param->scan_ch->scan_mode == BACKOP_MODE)? "OP_CH": "Non-OP");
return param->scan_ch;
}
/* Notification complete */
void _cmd_scan_timer_notify_cb(
void *role, struct phl_msg *msg)
{
if (IS_MSG_CANNOT_IO(msg->msg_id)) {
PHL_ERR("%s: SWCH_DONE failure by CANNOT IO\n", __func__);
return;
}
if (IS_MSG_CANCEL(msg->msg_id)) {
/* Last event occured MSG_STATUS_PENDING */
PHL_ERR("%s: SWCH_DONE pending or abort Occurred!\n", __func__);
_cmd_scan_timer(role);
}
}
static void _cmd_scan_timer(void* role)
{
struct rtw_wifi_role_t *wifi_role = (struct rtw_wifi_role_t *)role;
struct rtw_phl_com_t *phl_com = wifi_role->phl_com;
struct phl_info_t *phl_info = phl_com->phl_priv;
u8 band_idx = wifi_role->hw_band;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
PHL_INFO("%s \n", __func__);
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN);
/** When listen state of each channel entry expired,
* timer callback send MSG_EVT_LISTEN_STATE_EXPIRE for additional condition check
* If nothing specitail occured, then send MSG_EVT_SWCH_START to proceed for the rest of channel list
* therefore, additional process delay for MSG_EVT_LISTEN_STATE_EXPIRE would prolong listen period
* */
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_LISTEN_STATE_EXPIRE);
msg.rsvd[0] = (u8*)role;
msg.band_idx = band_idx;
attr.completion.completion = _cmd_scan_timer_notify_cb;
attr.completion.priv = role;
if(phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL) != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("%s: [SCAN_TIMER] phl_disp_eng_send_msg failed !\n", __func__);
}
/* Notification complete */
void _cmd_swch_done_notify_cb(
void *drv, struct phl_msg *msg)
{
if (msg->inbuf) {
_os_mem_free(drv, msg->inbuf, msg->inlen);
}
}
enum rtw_phl_status _cmd_swch_done_notify(
void *dispr, void *drv, struct rtw_phl_scan_param *param)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
struct phl_scan_channel *scan_ch = param->scan_ch;
struct rtw_phl_com_t *phl_com = param_to_phlcom(param);
struct phl_info_t *phl = (struct phl_info_t *) phl_com->phl_priv;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
u8 *info = NULL;
u8 idx = 0xff;
info = _os_mem_alloc(drv, sizeof(struct phl_scan_channel));
if (info == NULL) {
PHL_ERR("%s: [SWCH_DONE] alloc buffer failed!\n", __func__);
return RTW_PHL_STATUS_FAILURE;
}
_os_mem_cpy(drv, info, scan_ch, sizeof(*scan_ch));
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SWCH_DONE);
attr.opt = MSG_OPT_CLR_SNDR_MSG_IF_PENDING;
attr.completion.completion = _cmd_swch_done_notify_cb;
attr.completion.priv = drv;
msg.inbuf = info;
msg.inlen = sizeof(struct phl_scan_channel);
msg.rsvd[0] = (u8*)param->wifi_role;
phl_dispr_get_idx(dispr, &idx);
msg.band_idx = idx;
pstatus = phl_disp_eng_send_msg(phl, &msg, &attr, NULL);
if(pstatus != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s: [SWCH_DONE] phl_disp_eng_send_msg failed!\n", __func__);
_os_mem_free(drv, info, sizeof(struct phl_scan_channel));
}
return pstatus;
}
void _cmd_scan_end(
void *drv, struct rtw_phl_scan_param *param)
{
struct rtw_wifi_role_t *wifi_role = param->wifi_role;
struct rtw_phl_com_t *phl_com = wifi_role->phl_com;
struct phl_info_t *phl_info = phl_com->phl_priv;
PHL_INFO("_cmd_scan_end \n");
param->end_time = _os_get_cur_time_ms();
/* dump scan time */
param->total_scan_time =
phl_get_passing_time_ms(param->enqueue_time);
pq_deinit(drv, ¶m->chlist);
/* acquire state */
_os_cancel_timer(drv, ¶m->scan_timer);
_os_release_timer(drv, ¶m->scan_timer);
if(TEST_STATUS_FLAG(param->state, CMD_SCAN_STARTED) &&
!TEST_STATUS_FLAG(param->state, CMD_SCAN_DF_IO) )
{
rtw_hal_com_scan_restore_tx_lifetime(phl_info->hal, wifi_role->hw_band);
rtw_hal_scan_set_rxfltr_by_mode(phl_info->hal, wifi_role->hw_band,
false, ¶m->fltr_mode);
rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, false);
rtw_hal_notification(phl_info->hal, MSG_EVT_SCAN_END, wifi_role->hw_band);
}
if (param->ops->scan_complete)
param->ops->scan_complete(param->priv, param);
}
/* Notification complete */
void _cmd_abort_notify_cb(
void *drv, struct phl_msg *msg)
{
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param *)msg->inbuf;
if(IS_MSG_CANNOT_IO(msg->msg_id))
SET_STATUS_FLAG(param->state, CMD_SCAN_DF_IO);
_cmd_scan_end(drv, param);
}
void _cmd_abort_notify(void *dispr, void *drv,
struct rtw_phl_scan_param *param, bool abort)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
struct rtw_phl_com_t *phl_com = param_to_phlcom(param);
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
struct phl_info_t *phl = (struct phl_info_t *) phl_com->phl_priv;
u8 idx = 0xff;
if(TEST_STATUS_FLAG(param->state, CMD_SCAN_ACQUIRE))
{
param->result = SCAN_REQ_CANCEL;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SCAN_END);
if(abort)
attr.opt = MSG_OPT_SEND_IN_ABORT;
attr.completion.completion = _cmd_abort_notify_cb;
attr.completion.priv = drv;
msg.inbuf = (u8*)param;
msg.rsvd[0] = (u8*)param->wifi_role;
#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
msg.rsvd[1] = (u8*)param->ops->scan_issue_null_data;
#endif
phl_dispr_get_idx(dispr, &idx);
msg.band_idx = idx;
pstatus = phl_disp_eng_send_msg(phl, &msg, &attr, NULL);
if (RTW_PHL_STATUS_SUCCESS != pstatus) {
/* (1) dispr_stop
(2) idle msg empty .*/
PHL_ERR("%s :: [Abort] dispr_send_msg failed (0x%X)\n",
__func__, pstatus);
if(pstatus == RTW_PHL_STATUS_UNEXPECTED_ERROR ||
TEST_STATUS_FLAG(phl_com->dev_state, RTW_DEV_SURPRISE_REMOVAL)) {
/* clean sw resource only */
/* (1) driver is going to unload */
/* (2) Supprise remove */
SET_STATUS_FLAG(param->state, CMD_SCAN_DF_IO);
}
_cmd_abort_notify_cb(drv, &msg);
}
}
else {
param->result = SCAN_REQ_ABORT;
pq_deinit(drv, ¶m->chlist);
if (param->ops->scan_complete)
param->ops->scan_complete(param->priv, param);
}
}
enum phl_mdl_ret_code _cmd_scan_fail_ev_hdlr(
void* dispr, void* priv, struct phl_msg* msg)
{
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv;
struct rtw_wifi_role_t *wifi_role = param->wifi_role;
struct rtw_phl_com_t *phl_com = wifi_role->phl_com;
struct phl_info_t *phl_info = phl_com->phl_priv;
void *d = phlcom_to_drvpriv(phl_com);
u8 idx = 0xff;
struct phl_msg nextmsg = {0};
struct phl_msg_attribute attr = {0};
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_SCAN);
phl_dispr_get_idx(dispr, &idx);
nextmsg.band_idx = idx;
switch(MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_SCAN_START:
/* fall through */
case MSG_EVT_SWCH_START:
/* fall through */
case MSG_EVT_SWCH_DONE:
PHL_INFO("SCAN_START/SWCH_START/SWCH_DONE:: failed/timeout handler \n");
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SCAN_END);
nextmsg.rsvd[0] = (u8*)param->wifi_role;
#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
nextmsg.rsvd[1] = (u8*)param->ops->scan_issue_null_data;
#endif
pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL);
if(pstatus != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("%s :: [SWCH_START][1] phl_disp_eng_send_msg failed\n", __func__);
break;
case MSG_EVT_SCAN_END:
// free token
// release timer
PHL_INFO("MSG_EVT_SCAN_END:: failed/timeout handler \n");
pstatus = phl_disp_eng_free_token(phl_info, idx, ¶m->token);
if(pstatus == RTW_PHL_STATUS_SUCCESS)
{
if(IS_MSG_CANNOT_IO(msg->msg_id))
SET_STATUS_FLAG(param->state, CMD_SCAN_DF_IO);
_cmd_scan_end(d, param);
}
break;
default:
/* unknown state */
break;
}
return MDL_RET_SUCCESS;
}
enum phl_mdl_ret_code _cmd_scan_hdl_external_evt(
void* dispr, void* priv, struct phl_msg* msg)
{
PHL_DBG("%s :: From others MDL =%d , EVT_ID=%d\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
return MDL_RET_IGNORE;
}
u8 _cmd_chk_ext_act_scan(struct rtw_phl_scan_param *param)
{
#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN
/** suppose to query the time of last recieved beacon in current channel here
* then change state to EXT_ACT_SCAN_TRIGGER if needed
* but, PHL does not store bss list at the moment, therefore,
* core layer use set_info (FG_REQ_OP_NOTIFY_BCN_RCV) to notify scan module incoming bcn
* and change state to EXT_ACT_SCAN_TRIGGER accordingly.
*/
#endif
if (param->scan_ch->type == RTW_PHL_SCAN_PASSIVE &&
param->scan_ch->ext_act_scan == EXT_ACT_SCAN_TRIGGER) {
if (param->ops->scan_issue_pbreq)
param->ops->scan_issue_pbreq(param->priv, param);
param->scan_ch->ext_act_scan = EXT_ACT_SCAN_DONE;
return true;
}
return false;
}
void
_cmd_scan_start(struct phl_info_t *phl_info,
struct rtw_wifi_role_t *wifi_role,
struct rtw_phl_scan_param *param)
{
rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, true);
rtw_hal_scan_set_rxfltr_by_mode(phl_info->hal, wifi_role->hw_band,
true, ¶m->fltr_mode);
rtw_hal_com_scan_set_tx_lifetime(phl_info->hal, wifi_role->hw_band);
}
enum phl_mdl_ret_code _cmd_scan_hdl_internal_evt(
void* dispr, void* priv, struct phl_msg* msg)
{
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv;
struct rtw_wifi_role_t *wifi_role = param->wifi_role;
struct rtw_phl_com_t *phl_com = wifi_role->phl_com;
struct phl_info_t *phl_info = phl_com->phl_priv;
void *d = phlcom_to_drvpriv(phl_com);
u32 diff_time = 0;
struct phl_msg nextmsg = {0};
struct phl_msg_attribute attr = {0};
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
u8 idx = 0xff;
struct phl_scan_channel *scan_ch = NULL;
bool tx_pause = true;
struct rtw_chan_def chdef = {0};
phl_dispr_get_idx(dispr, &idx);
diff_time = phl_get_passing_time_ms(param->enqueue_time);
if (param->max_scan_time && diff_time >= param->max_scan_time) {
PHL_WARN("%s:: Timeout! %d > max_time %d\n",
__func__, diff_time, param->max_scan_time);
/* Abort scan request */
/* Based on [CN3AXSW-552]
* ex. max_scan_time = 4sec
* Usb dongle would abort scan_req in 29~33th chnl
* If chnllist insert op-chnl, scan_req would be aborted in 21~23th chnl.
* It means that usb dongle always can't do fully scan.
* So, abort scan_req or not, depend on core layer.
*/
/*_cmd_scan_fail_ev_hdlr(dispr, priv, msg);
return MDL_RET_FAIL; */
}
else {
PHL_INFO("%s:: TimeIntvl: %u \n", __func__, diff_time);
}
#ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME
if (param->max_listen_time && diff_time >= param->max_listen_time) {
PHL_WARN("%s:: Timeout! %d > max_listen_time %d\n",
__func__, diff_time, param->max_listen_time);
#if 0
_cmd_scan_fail_ev_hdlr(dispr, priv, msg);
return MDL_RET_FAIL;
#endif
}
#endif
SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_FG_MDL_SCAN);
nextmsg.band_idx = idx;
switch(MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_SCAN_START:
_cmd_scan_start(phl_info, wifi_role, param);
rtw_hal_notification(phl_info->hal, MSG_EVT_SCAN_START,
wifi_role->hw_band);
/* [scan start notify] */
if (param->ops->scan_start)
param->ops->scan_start(param->priv, param);
SET_STATUS_FLAG(param->state, CMD_SCAN_STARTED);
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SWCH_START);
nextmsg.rsvd[0] = (u8*)wifi_role;
pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL);
if(pstatus != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("%s :: [SCAN_START] phl_disp_eng_send_msg failed\n", __func__);
break;
case MSG_EVT_LISTEN_STATE_EXPIRE:
if (_cmd_chk_ext_act_scan(param)) {
_os_set_timer(d, ¶m->scan_timer, param->ext_act_scan_period);
PHL_INFO("%s :: extend listen state of ch %d by %d ms, and reset timer\n",
__func__, param->scan_ch->channel, param->ext_act_scan_period);
break;
}
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SWCH_START);
nextmsg.rsvd[0] = (u8*)wifi_role;
pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL);
if(pstatus != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("%s :: [LISTEN_STATE_EXPIRE] dispr_send_msg failed\n", __func__);
break;
case MSG_EVT_SWCH_START:
/* ycx++
ycx > length(yclist) ? SCAN_EV_END : switch channel */
PHL_INFO("MSG_EVT_SWCH_START \n");
/* For the first time, param->scan_ch would be NULL */
/* Current channel scan_mode */
if (param->scan_ch && param->scan_ch->scan_mode == BACKOP_MODE) {
tx_pause = false;
}
scan_ch = _cmd_scan_select_chnl(d, param);
if (scan_ch == NULL) {
/* no more channel, we are done */
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SCAN_END);
nextmsg.rsvd[0] = (u8*)param->wifi_role;
#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
nextmsg.rsvd[1] = (u8*)param->ops->scan_issue_null_data;
#endif
pstatus = phl_disp_eng_send_msg(phl_info, &nextmsg, &attr, NULL);
if(pstatus != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("%s :: [SWCH_START][1] dispr_send_msg failed\n", __func__);
break;
}
/* Next channel scan_mode */
if ((scan_ch->scan_mode != BACKOP_MODE) && !tx_pause) {
/* Tx pause */
rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, true);
tx_pause = true;
}
chdef.band = scan_ch->band;
chdef.chan = (u8)scan_ch->channel;
chdef.bw = scan_ch->bw;
chdef.offset = scan_ch->offset;
phl_set_ch_bw(wifi_role, &chdef, false);
if ((scan_ch->scan_mode != BACKOP_MODE) &&
(scan_ch->type == RTW_PHL_SCAN_ACTIVE)) {
/* Notify RF to do tssi backup */
rtw_hal_notification(phl_info->hal, MSG_EVT_SWCH_START, wifi_role->hw_band);
if (param->ops->scan_issue_pbreq)
param->ops->scan_issue_pbreq(param->priv, param);
}
if ((scan_ch->scan_mode == BACKOP_MODE) && tx_pause) {
/* Tx un-pause */
rtw_hal_scan_pause_tx_fifo(phl_info->hal, wifi_role->hw_band, false);
}
_os_set_timer(d, ¶m->scan_timer, scan_ch->duration);
#ifdef DBG_SCAN_CHAN_DUMP
PHL_INFO("[SCAN] band:%d chan:%d bw:%d offset:%d duration:%d (ms)\n",
scan_ch->band, scan_ch->channel, scan_ch->bw,
scan_ch->offset, scan_ch->duration);
#endif
pstatus = _cmd_swch_done_notify(dispr, d, param);
break;
case MSG_EVT_SWCH_DONE:
if (param->ops->scan_ch_ready)
param->ops->scan_ch_ready(param->priv, param);
PHL_INFO("MSG_EVT_SWCH_DONE :: duration=%d\n", param->scan_ch->duration);
break;
case MSG_EVT_SCAN_END:
PHL_INFO("MSG_EVT_SCAN_END \n");
pstatus = phl_disp_eng_free_token(phl_info, idx, ¶m->token);
if(pstatus == RTW_PHL_STATUS_SUCCESS) {
param->result = SCAN_REQ_COMPLETE;
_cmd_scan_end(d, param);
}
else
PHL_WARN("%s :: [SCAN_END] Abort occurred, skip!\n", __func__);
break;
default:
/* unknown state */
break;
}
return MDL_RET_SUCCESS;
}
enum phl_mdl_ret_code _phl_cmd_scan_req_acquired(
void* dispr, void* priv)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv;
struct rtw_phl_com_t *phl_com = param_to_phlcom(param);
void *d = phlcom_to_drvpriv(phl_com);
u32 diff_time = 0;
struct phl_info_t *phl_info = phl_com->phl_priv;
u8 idx = 0xff;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
FUNCIN();
param->start_time = _os_get_cur_time_ms();
/* check max scan time */
if (param->max_scan_time > 0) {
diff_time = phl_get_passing_time_ms(param->enqueue_time);
if (diff_time >= param->max_scan_time) {
PHL_WARN("%s:: Timeout! %u > max_time %d\n",
__func__, diff_time, param->max_scan_time);
goto error;
}
}
_os_init_timer(d, ¶m->scan_timer, _cmd_scan_timer,
param->wifi_role, "phl_cmd_scan_req_timer");
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_SCAN);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_SCAN_START);
msg.rsvd[0] = (u8*)param->wifi_role;
phl_dispr_get_idx(dispr, &idx);
msg.band_idx = idx;
pstatus = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(pstatus != RTW_PHL_STATUS_SUCCESS) {
_os_release_timer(d, ¶m->scan_timer);
goto error;
}
else {
SET_STATUS_FLAG(param->state, CMD_SCAN_ACQUIRE);
return MDL_RET_SUCCESS;
}
error:
_cmd_abort_notify(dispr, d, param, false);
return MDL_RET_FAIL;
}
enum phl_mdl_ret_code _phl_cmd_scan_req_abort(
void* dispr, void* priv)
{
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv;
struct rtw_phl_com_t *phl_com = param_to_phlcom(param);
void *d = phlcom_to_drvpriv(phl_com);
PHL_INFO("_phl_cmd_scan_req_abort \n");
_cmd_abort_notify(dispr, d, param, true);
return MDL_RET_SUCCESS;
}
enum phl_mdl_ret_code _phl_cmd_scan_req_ev_hdlr(
void* dispr, void* priv,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
if(IS_MSG_FAIL(msg->msg_id)) {
PHL_INFO("%s :: MSG(%d)_FAIL - EVT_ID=%d \n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
_cmd_scan_fail_ev_hdlr(dispr, priv, msg);
return MDL_RET_FAIL;
}
switch(MSG_MDL_ID_FIELD(msg->msg_id)) {
case PHL_FG_MDL_SCAN:
ret = _cmd_scan_hdl_internal_evt(dispr, priv, msg);
break;
default:
ret = _cmd_scan_hdl_external_evt(dispr, priv, msg);
break;
}
return ret;
}
enum phl_mdl_ret_code _phl_cmd_scan_req_set_info(
void* dispr, void* priv, struct phl_module_op_info* info)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
#ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN
switch(info->op_code) {
case FG_REQ_OP_NOTIFY_BCN_RCV:
{
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv;
u16 channel = 0;
/* this workaround might have race condition with background thread*/
channel = *(u8*)info->inbuf;
if (param->scan_ch &&
param->scan_ch->channel == channel &&
param->scan_ch->ext_act_scan == EXT_ACT_SCAN_ENABLE) {
param->scan_ch->ext_act_scan = EXT_ACT_SCAN_TRIGGER;
PHL_INFO(" %s :: channel %d extend for active scan\n", __func__, channel);
}
if (param->scan_ch &&
param->scan_ch->channel != channel)
PHL_INFO(" %s :: channel %d mismatch from listen channel %d\n", __func__, channel, param->scan_ch->channel);
ret = MDL_RET_SUCCESS;
}
break;
default:
break;
}
#endif
/* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */
return ret;
}
enum phl_mdl_ret_code _phl_cmd_scan_req_query_info(
void* dispr, void* priv, struct phl_module_op_info* info)
{
struct rtw_phl_scan_param *param = (struct rtw_phl_scan_param*)priv;
struct rtw_phl_com_t *phl_com = param_to_phlcom(param);
void *d = phlcom_to_drvpriv(phl_com);
u8 ucInfo = 0;
void* pInfo = NULL;
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
/* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */
switch(info->op_code) {
case FG_REQ_OP_GET_ROLE:
info->outbuf = (u8*)param->wifi_role;
ret = MDL_RET_SUCCESS;
break;
case FG_REQ_OP_GET_MDL_ID:
ucInfo= PHL_FG_MDL_SCAN;
pInfo = (void*) &ucInfo;
info->outlen=1;
_os_mem_cpy(d, (void*)info->outbuf, pInfo, info->outlen);
ret = MDL_RET_SUCCESS;
break;
#ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
case FG_REQ_OP_GET_SCAN_PARAM:
info->outbuf = (u8*)param;
ret = MDL_RET_SUCCESS;
break;
#endif
default:
break;
}
return ret;
}
#ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME
static void
_cmd_scan_update_chparam(void *drv, struct rtw_phl_scan_param *param)
{
u8 idx = 0;
u16 scan_section_ms = 0;
u16 total_scan_ms = 0;
for(idx = 0; idx < param->ch_num; idx++) {
if (param->ch[idx].scan_mode == P2P_LISTEN_MODE) {
param->max_listen_time = param->ch[idx].duration;
total_scan_ms = param->ch[idx].duration;
break;
}
}
scan_section_ms = param->back_op_ch_dur_ms + param->back_op_off_ch_dur_ms;
if (scan_section_ms)
param->repeat = total_scan_ms / scan_section_ms;
}
#endif
static void
_phl_cmd_scan_req_init(void *phl, struct phl_cmd_token_req *fgreq,
struct rtw_phl_scan_param *param)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
void *drv = phl_to_drvpriv(phl_info);
struct rtw_chan_def chdef_list[MAX_WIFI_ROLE_NUMBER] = {0};
u8 op_num = 0;
u8 idx = 0;
pq_init(drv, ¶m->chlist);
param->enqueue_time = _os_get_cur_time_ms();
_cmd_scan_update_chlist(drv, param);
if (param->back_op_mode != SCAN_BKOP_NONE) {
op_num = rtw_phl_mr_get_opch_list(phl_info, param->wifi_role,
chdef_list, (u8)MAX_WIFI_ROLE_NUMBER);
if(op_num) {
for(idx = 0; idx < op_num; idx++) {
if(chdef_list[idx].chan) {
INIT_LIST_HEAD(¶m->back_op_ch[idx].list);
param->back_op_ch[idx].channel = chdef_list[idx].chan;
param->back_op_ch[idx].bw = chdef_list[idx].bw;
param->back_op_ch[idx].offset = chdef_list[idx].offset;
param->back_op_ch[idx].duration = param->back_op_ch_dur_ms;
param->back_op_ch[idx].scan_mode = BACKOP_MODE;
}
}
}
#ifdef CONFIG_PHL_CMD_SCAN_BKOP_TIME
if (op_num && param->back_op_mode == SCAN_BKOP_TIMER)
_cmd_scan_update_chparam(drv, param);
#endif
}
#ifdef DBG_SCAN_CHAN_DUMP
/* debug information*/
_cmd_estimated_swch_seq(param, op_num);
#endif
/* Fill foreground command request */
fgreq->module_id= PHL_FG_MDL_SCAN;
fgreq->priv = param;
fgreq->role = param->wifi_role;
fgreq->acquired = _phl_cmd_scan_req_acquired;
fgreq->abort = _phl_cmd_scan_req_abort;
fgreq->msg_hdlr = _phl_cmd_scan_req_ev_hdlr;
fgreq->set_info = _phl_cmd_scan_req_set_info;
fgreq->query_info = _phl_cmd_scan_req_query_info;
}
/* For EXTERNAL application to request scan (expose) */
/* @pscan: scan object
* @pbuf: scan parameter, will be freed by caller after retrun
* @order: queuing order
*/
enum rtw_phl_status rtw_phl_cmd_scan_request(void *phl,
struct rtw_phl_scan_param *param, enum PRECEDE order)
{
enum rtw_phl_status pstatus = RTW_PHL_STATUS_FAILURE;
u8 band_idx = param->wifi_role->hw_band;
struct phl_cmd_token_req fgreq={0};
_phl_cmd_scan_req_init(phl, &fgreq, param);
/* cmd_dispatcher would copy whole phl_cmd_token_req */
pstatus = phl_disp_eng_add_token_req(phl, band_idx, &fgreq, ¶m->token);
if((pstatus != RTW_PHL_STATUS_SUCCESS) &&
(pstatus != RTW_PHL_STATUS_PENDING))
goto error;
pstatus = RTW_PHL_STATUS_SUCCESS;
error:
return pstatus;
}
enum rtw_phl_status rtw_phl_cmd_scan_cancel(void *phl,
struct rtw_phl_scan_param *param)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
u8 band_idx = param->wifi_role->hw_band;
return phl_disp_eng_cancel_token_req(phl_info, band_idx, ¶m->token);
}
int rtw_phl_cmd_scan_inprogress(void *phl, u8 band_idx)
{
struct phl_module_op_info op_info = {0};
u32 mdl = 0;
op_info.op_code = FG_REQ_OP_GET_MDL_ID;
op_info.outbuf = (u8*)&mdl;
op_info.outlen = 4;
if(phl_disp_eng_query_cur_cmd_info(phl, band_idx,
&op_info)== RTW_PHL_STATUS_SUCCESS ) {
if(mdl == PHL_FG_MDL_SCAN)
return true;
}
return false;
}
#endif /* CONFIG_PHL_CMD_SCAN */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_scan.c
|
C
|
agpl-3.0
| 28,603
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CMD_SER_C_
#include "phl_headers.h"
#include "phl_api.h"
#define CMD_SER_L0 0x00000001
#define CMD_SER_L1 0x00000002
#define CMD_SER_L2 0x00000004
enum _CMD_SER_EVENT_SOURCE {
CMD_SER_SRC_UNKNOWN = 0,
CMD_SER_SRC_INT = BIT0, // ser event from interrupt
CMD_SER_SRC_POLL = BIT1, // ser event by polling io
CMD_SER_SRC_INT_NOTIFY = BIT2, // ser event from interrupt and ser state from mac
};
enum _CMD_SER_TIMER_STATE {
CMD_SER_NOT_OCCUR = 0,
CMD_SER_M1 = BIT0, //POLL_IO
CMD_SER_M2 = BIT1, //POLL_FW
CMD_SER_M3 = BIT2,
CMD_SER_M4 = BIT3,
CMD_SER_M5 = BIT4,
CMD_SER_M9 = BIT5,
};
#define CMD_SER_FW_TIMEOUT 1000 /* ms */
#define CMD_SER_POLLING_INTERVAL 10 /* ms */
#define CMD_SER_USB_POLLING_INTERVAL_IDL 1000 /* ms */
#define CMD_SER_USB_POLLING_INTERVAL_ACT 10 /* ms */
#define CMD_SER_POLL_IO_TIMES 200
#define CMD_SER_USB_POLL_IO_TIMES 300
#define CMD_SER_LOG_SIZE 10
struct sts_l2 {
_os_list list;
u8 idx;
u8 ser_log;
};
struct cmd_ser {
struct phl_info_t *phl_info;
void* dispr;
u8 state;
_os_lock _lock;
u8 evtsrc;
int poll_cnt;
_os_timer poll_timer;
/* L2 log :
// If L2 triggered, set ser_log = state-of-cmd_ser
*/
struct phl_queue stslist;
struct sts_l2 stsl2[CMD_SER_LOG_SIZE];
u8 bserl2;
u8 (*ser_l2_hdlr)(void *drv);
};
static void _ser_int_ntfy_ctrl(struct phl_info_t *phl_info,
enum rtw_phl_config_int int_type)
{
if (RTW_PHL_CLR_HCI_INT == int_type)
rtw_hal_clear_interrupt(phl_info->hal);
else
rtw_hal_config_interrupt(phl_info->hal, int_type);
}
static enum rtw_phl_status
_ser_event_notify(void *phl, u8 *p_ntfy)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET;
struct phl_msg msg = {0};
u32 err = 0;
notify = rtw_hal_ser_get_error_status(phl_info->hal, &err);
if (p_ntfy != NULL)
*p_ntfy = notify;
phl_info->phl_com->phl_stats.ser_event[notify]++;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "_ser_event_notify, error 0x%x, notify 0x%x\n", err, notify);
if (notify == RTW_PHL_SER_L0_RESET) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "_ser_event_notify, hit L0 Reset\n");
return RTW_PHL_STATUS_SUCCESS;
}
if (notify == RTW_PHL_SER_LOG_ONLY) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "_ser_event_notify, RTW_PHL_SER_LOG_ONLY\n");
return RTW_PHL_STATUS_SUCCESS;
}
if (notify == RTW_PHL_SER_DUMP_FW_LOG) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "_ser_event_notify, RTW_PHL_SER_DUMP_FW_LOG\n");
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DUMP_PLE_BUFFER);
phl_msg_hub_send(phl_info, NULL, &msg);
return RTW_PHL_STATUS_SUCCESS;
}
return phl_ser_send_msg(phl, notify);
}
void _ser_dump_stsl2(struct cmd_ser *cser)
{
u8 idx =0;
for (idx = 0; idx < CMD_SER_LOG_SIZE; idx++) {
if (cser->stsl2[idx].ser_log || cser->stsl2[idx].idx >= CMD_SER_LOG_SIZE) {
PHL_ERR("%s :: [%d] %d - ser_log = 0x%X \n", __func__,
idx, cser->stsl2[idx].idx, cser->stsl2[idx].ser_log);
}
}
}
void _ser_reset_status(struct cmd_ser *cser)
{
void *drv = phl_to_drvpriv(cser->phl_info);
_os_spinlock(drv, &cser->_lock, _bh, NULL);
cser->state = CMD_SER_NOT_OCCUR;
_os_spinunlock(drv, &cser->_lock, _bh, NULL);
if (CMD_SER_SRC_POLL == cser->evtsrc) {
cser->poll_cnt = 0;
_os_set_timer(drv,
&cser->poll_timer,
CMD_SER_USB_POLLING_INTERVAL_IDL);
} else if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) {
_ser_int_ntfy_ctrl(cser->phl_info, RTW_PHL_EN_HCI_INT);
}
}
void _ser_set_status(struct cmd_ser *cser, u8 serstatus)
{
void *drv = phl_to_drvpriv(cser->phl_info);
_os_spinlock(drv, &cser->_lock, _bh, NULL);
cser->state |= serstatus;
_os_spinunlock(drv, &cser->_lock, _bh, NULL);
}
void _ser_clear_status(struct cmd_ser *cser, u8 serstatus)
{
void *drv = phl_to_drvpriv(cser->phl_info);
_os_spinlock(drv, &cser->_lock, _bh, NULL);
cser->state &= ~(serstatus);
_os_spinunlock(drv, &cser->_lock, _bh, NULL);
}
static void _ser_l1_notify(struct cmd_ser *cser)
{
struct phl_msg nextmsg = {0};
SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER);
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_L1);
phl_msg_hub_send(cser->phl_info, NULL, &nextmsg);
}
static void _ser_l2_notify(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
struct sts_l2 *stsl2 = NULL;
struct phl_msg nextmsg = {0};
_os_list* obj = NULL;
rtw_hal_ser_reset_wdt_intr(phl_info->hal);
if (pq_pop(drv, &cser->stslist, &obj, _first, _ps)) {
stsl2 = (struct sts_l2*)obj;
/* Rotate stslist : 0~ (CMD_SER_LOG_SIZE-1) are unused index */
stsl2->idx+= CMD_SER_LOG_SIZE;
stsl2->ser_log = cser->state;
pq_push(drv, &cser->stslist, &stsl2->list, _tail, _ps);
}
_ser_dump_stsl2(cser);
/* L2 can't be rescued, bserl2 wouldn't reset. */
/* comment out: wait for new ser flow to handle L2 */
cser->bserl2 = true;
if (cser->ser_l2_hdlr)
cser->ser_l2_hdlr(phl_to_drvpriv(phl_info));
phl_disp_eng_clr_pending_msg(cser->phl_info, HW_BAND_0);
SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER);
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_L2);
phl_msg_hub_send(cser->phl_info, NULL, &nextmsg);
}
static void _ser_m2_notify(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc)
_ser_int_ntfy_ctrl(phl_info, RTW_PHL_SER_HANDSHAKE_MODE);
_ser_clear_status(cser, CMD_SER_M1);
_ser_set_status(cser, CMD_SER_M2);
/* send M2 event to fw */
status = rtw_hal_ser_set_error_status(phl_info->hal, RTW_PHL_SER_L1_DISABLE_EN);
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "_ser_m2_notify:: RTW_PHL_SER_L1_DISABLE_EN, status 0x%x\n", status);
}
static void _ser_m3_m5_waiting(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
int poll_cnt = 0, intvl = CMD_SER_FW_TIMEOUT;
if (cser->evtsrc == CMD_SER_SRC_POLL) {
/* CMD_SER_POLLING_INTERVAL = CMD_SER_FW_TIMEOUT/ CMD_SER_USB_POLLING_INTERVAL_ACT */
poll_cnt = CMD_SER_POLLING_INTERVAL;
intvl = CMD_SER_USB_POLLING_INTERVAL_ACT;
}
cser->poll_cnt = poll_cnt;
/* wait M3 or M5 */
_os_set_timer(drv, &cser->poll_timer, intvl);
}
static void _ser_m4_notify(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc)
_ser_int_ntfy_ctrl(phl_info, RTW_PHL_SER_HANDSHAKE_MODE);
_ser_clear_status(cser, CMD_SER_M3);
_ser_set_status(cser, CMD_SER_M4);
/* send M4 event */
status = rtw_hal_ser_set_error_status(phl_info->hal, RTW_PHL_SER_L1_RCVY_EN);
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "_ser_m4_notify:: RTW_PHL_SER_L1_RCVY_EN, status 0x%x\n", status);
}
static void _ser_poll_timer_cb(void *priv)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
struct phl_msg nextmsg = {0};
struct phl_msg_attribute attr = {0};
enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER);
if (TEST_STATUS_FLAG(cser->state, CMD_SER_M1)) {
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_IO_TIMER_EXPIRE);
} else if (TEST_STATUS_FLAG(cser->state, CMD_SER_M2)) {
if (cser->poll_cnt > 0) /* polling mode */
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_POLLING_CHK);
else
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_FW_TIMER_EXPIRE);
} else if (TEST_STATUS_FLAG(cser->state, CMD_SER_M4)) {
if (cser->poll_cnt > 0) /* polling mode */
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_POLLING_CHK);
else
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_FW_TIMER_EXPIRE);
} else {
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, MSG_EVT_SER_POLLING_CHK);
}
nextmsg.band_idx = HW_BAND_0;
if (MSG_EVT_ID_FIELD(nextmsg.msg_id)) {
PHL_DBG("%s :: nextmsg->msg_id= 0x%X\n", __func__, MSG_EVT_ID_FIELD(nextmsg.msg_id));
pstatus = phl_disp_eng_send_msg(cser->phl_info, &nextmsg, &attr, NULL);
if (pstatus != RTW_PHL_STATUS_SUCCESS)
PHL_ERR("%s :: [SER_TIMER_CB] dispr_send_msg failed\n", __func__);
}
}
static void _ser_m1_pause_trx(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.id = PHL_MDL_SER;
ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): pause sw tx failure\n", __func__);
goto err;
}
ctl.cmd = PHL_DATA_CTL_HW_TRX_PAUSE;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): pause hw trx failure\n", __func__);
goto err;
}
ctl.cmd = PHL_DATA_CTL_SW_RX_PAUSE;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
#ifdef RTW_WKARD_SER_L1_EXPIRE
if (RTW_PHL_STATUS_SUCCESS != sts && RTW_PHL_STATUS_CMD_TIMEOUT != sts) {
PHL_WARN("%s(): pause sw rx failure\n", __func__);
goto err;
}
#else
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): pause sw rx failure\n", __func__);
goto err;
}
#endif
ctl.cmd = PHL_DATA_CTL_SW_TX_RESET;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): reset sw tx failure\n", __func__);
goto err;
}
ctl.cmd = PHL_DATA_CTL_SW_RX_RESET;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): reset sw rx failure\n", __func__);
goto err;
}
_ser_m2_notify(cser);
_ser_m3_m5_waiting(cser);
return;
err:
_ser_l2_notify(cser);
_ser_reset_status(cser);
return;
}
static void _ser_m3_reset_hw_trx(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
ctl.id = PHL_MDL_SER;
ctl.cmd = PHL_DATA_CTL_HW_TRX_RST_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): resume hw trx failure\n", __func__);
goto err;
}
ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts) {
PHL_WARN("%s(): resume sw rx failure\n", __func__);
goto err;
}
_ser_m4_notify(cser);
_ser_m3_m5_waiting(cser);
return;
err:
_ser_l2_notify(cser);
_ser_reset_status(cser);
return;
}
enum phl_mdl_ret_code
_ser_fail_ev_hdlr(void *dispr, void *priv, struct phl_msg *msg)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
PHL_INFO("%s :: [MSG_FAIL] MDL =%d , EVT_ID=%d\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
if (cser->evtsrc != CMD_SER_SRC_POLL)
return MDL_RET_SUCCESS;
_os_set_timer(drv, &cser->poll_timer, CMD_SER_USB_POLLING_INTERVAL_IDL);
return MDL_RET_SUCCESS;
}
enum phl_mdl_ret_code
_ser_hdl_external_evt(void *dispr, void *priv, struct phl_msg *msg)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
/*
1. SER inprogress: pending msg from others module
2. SER recovery fail: clr pending event from MDL_SER & msg return failed from others module
3. SER recovery done: clr pending event & msg return ignor from others module
4. SER NOT OCCUR: MDL_RET_IGNORE
*/
if (cser->bserl2) {
PHL_ERR("%s: [2] L2 Occured!! From others MDL =%d , EVT_ID=%d\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
return MDL_RET_FAIL;
} else if (cser->state) { /* non-CMD_SER_NOT_OCCUR */
PHL_WARN("%s: [1] Within SER!! From others MDL =%d , EVT_ID=%d\n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
return MDL_RET_PENDING;
}
return MDL_RET_IGNORE;
}
static void _ser_msg_hdl_polling_chk(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
if (CMD_SER_SRC_POLL != cser->evtsrc)
return;
if (true == rtw_hal_recognize_interrupt(phl_info->hal)) {
rtw_phl_interrupt_handler(phl_info);
} else {
if (cser->poll_cnt > 0) {
/* wait for m3/m5, polling 10*10 */
cser->poll_cnt--;
_os_set_timer(drv, &cser->poll_timer, CMD_SER_USB_POLLING_INTERVAL_ACT); /* 10ms */
} else {
/* no ser occur, set next polling timer */
_os_set_timer(drv, &cser->poll_timer, CMD_SER_USB_POLLING_INTERVAL_IDL); /* 1000ms */
}
}
}
static enum rtw_phl_status
_ser_msg_hdl_evt_chk(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
if (CMD_SER_SRC_INT == cser->evtsrc) {
psts = _ser_event_notify(phl_info, NULL);
} else if (CMD_SER_SRC_POLL == cser->evtsrc) {
psts = _ser_event_notify(phl_info, NULL);
} else if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc) {
u8 notify = RTW_PHL_SER_L0_RESET;
/* disable interrupt notification and read ser value */
if (true == rtw_hal_recognize_halt_c2h_interrupt(phl_info->hal)) {
psts = _ser_event_notify(phl_info, ¬ify);
if ((notify == RTW_PHL_SER_L0_RESET) || (notify == RTW_PHL_SER_L2_RESET))
_ser_int_ntfy_ctrl(phl_info, RTW_PHL_EN_HCI_INT);
} else {
_ser_int_ntfy_ctrl(phl_info, RTW_PHL_EN_HCI_INT);
}
}
return psts;
}
static void _ser_msg_hdl_m1(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
if (CMD_SER_SRC_POLL == cser->evtsrc)
_os_cancel_timer(drv, &cser->poll_timer);
else if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc)
_ser_int_ntfy_ctrl(phl_info, RTW_PHL_DIS_HCI_INT);
_ser_set_status(cser, CMD_SER_M1);
_ser_l1_notify(cser);
_ser_m1_pause_trx(cser);
}
static void _ser_msg_hdl_fw_expire(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
if (CMD_SER_SRC_POLL == cser->evtsrc) {
_ser_set_status(cser, CMD_SER_M9);
_os_set_timer(drv,
&cser->poll_timer,
CMD_SER_USB_POLLING_INTERVAL_IDL);
}
cser->bserl2 = true;
}
static void _ser_msg_hdl_m3(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
if (CMD_SER_SRC_INT_NOTIFY == cser->evtsrc)
_ser_int_ntfy_ctrl(phl_info, RTW_PHL_CLR_HCI_INT);
_os_cancel_timer(drv, &cser->poll_timer);
_ser_clear_status(cser, CMD_SER_M2);
_ser_set_status(cser, CMD_SER_M3);
_ser_m3_reset_hw_trx(cser);
}
static void _ser_msg_hdl_m5(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
_os_cancel_timer(drv, &cser->poll_timer);
_ser_clear_status(cser, CMD_SER_M4);
_ser_set_status(cser, CMD_SER_M5);
ctl.id = PHL_MDL_SER;
ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts)
PHL_WARN("%s(): resume sw tx failure\n", __func__);
_ser_reset_status(cser);
phl_disp_eng_clr_pending_msg(cser->phl_info, HW_BAND_0);
}
static void _ser_msg_hdl_m9(struct cmd_ser *cser)
{
struct phl_info_t *phl_info = cser->phl_info;
void *drv = phl_to_drvpriv(phl_info);
enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
struct phl_data_ctl_t ctl = {0};
_os_cancel_timer(drv, &cser->poll_timer);
_ser_set_status(cser, CMD_SER_M9);
if (cser->state > CMD_SER_NOT_OCCUR) {
ctl.id = PHL_MDL_SER;
ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts)
PHL_WARN("%s(): resume sw tx failure\n", __func__);
ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME;
sts = phl_data_ctrler(phl_info, &ctl, NULL);
if (RTW_PHL_STATUS_SUCCESS != sts)
PHL_WARN("%s(): resume sw rx failure\n", __func__);
}
_ser_l2_notify(cser);
_ser_reset_status(cser);
}
enum phl_mdl_ret_code
_ser_hdl_internal_evt(void *dispr, void *priv, struct phl_msg *msg)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_SER_POLLING_CHK:
PHL_DBG("MSG_EVT_SER_POLLING_CHK\n");
_ser_msg_hdl_polling_chk(cser);
break;
case MSG_EVT_SER_EVENT_CHK:
PHL_INFO("MSG_EVT_SER_EVENT_CHK\n");
_ser_msg_hdl_evt_chk(cser);
break;
case MSG_EVT_SER_M1_PAUSE_TRX:
PHL_WARN("MSG_EVT_SER_M1_PAUSE_TRX\n");
_ser_msg_hdl_m1(cser);
break;
case MSG_EVT_SER_IO_TIMER_EXPIRE:
PHL_INFO("MSG_EVT_SER_IO_TIMER_EXPIRE\n");
break;
case MSG_EVT_SER_FW_TIMER_EXPIRE:
PHL_WARN("MSG_EVT_SER_FW_TIMER_EXPIRE (state %d), do nothing and wait FW WDT\n",
cser->state);
_ser_msg_hdl_fw_expire(cser);
break;
case MSG_EVT_SER_M3_DO_RECOV:
PHL_INFO("MSG_EVT_SER_M3_DO_RECOV\n");
_ser_msg_hdl_m3(cser);
break;
case MSG_EVT_SER_M5_READY:
PHL_INFO("MSG_EVT_SER_M5_READY\n");
_ser_msg_hdl_m5(cser);
break;
case MSG_EVT_SER_M9_L2_RESET:
PHL_WARN("MSG_EVT_SER_M9_L2_RESET\n");
_ser_msg_hdl_m9(cser);
break;
}
return ret;
}
static enum phl_mdl_ret_code
_phl_ser_mdl_init(void *phl, void *dispr, void **priv)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
void *drv = phl_to_drvpriv(phl_info);
struct cmd_ser *cser = NULL;
u8 idx = 0;
FUNCIN();
if (priv == NULL)
return MDL_RET_FAIL;
(*priv) = NULL;
cser = (struct cmd_ser *)_os_mem_alloc(drv, sizeof(struct cmd_ser));
if (cser == NULL) {
PHL_ERR(" %s, alloc fail\n",__FUNCTION__);
return MDL_RET_FAIL;
}
_os_mem_set(drv, cser, 0, sizeof(struct cmd_ser));
_os_spinlock_init(drv, &cser->_lock);
_os_init_timer(drv,
&cser->poll_timer,
_ser_poll_timer_cb,
cser,
"cmd_ser_poll_timer");
INIT_LIST_HEAD(&cser->stslist.queue);
for (idx =0; idx < CMD_SER_LOG_SIZE; idx++) {
INIT_LIST_HEAD(&cser->stsl2[idx].list);
cser->stsl2[idx].idx = idx;
pq_push(drv, &cser->stslist, &cser->stsl2[idx].list, _tail, _ps);
}
cser->phl_info = phl_info;
cser->dispr = dispr;
(*priv) = (void*)cser;
if (phl_info->phl_com->hci_type == RTW_HCI_PCIE)
cser->evtsrc = CMD_SER_SRC_INT;
else if (phl_info->phl_com->hci_type == RTW_HCI_USB)
cser->evtsrc = CMD_SER_SRC_POLL;
else if (phl_info->phl_com->hci_type == RTW_HCI_SDIO)
cser->evtsrc = CMD_SER_SRC_INT_NOTIFY;
PHL_INFO("%s:: cser->evtsrc = %d\n", __func__, cser->evtsrc);
FUNCOUT();
return MDL_RET_SUCCESS;
}
static void _phl_ser_mdl_deinit(void *dispr, void *priv)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
void *drv = phl_to_drvpriv(cser->phl_info);
FUNCIN();
_os_cancel_timer(drv, &cser->poll_timer);
_os_release_timer(drv, &cser->poll_timer);
_os_spinlock_free(drv, &cser->_lock);
_os_mem_free(drv, cser, sizeof(struct cmd_ser));
PHL_INFO(" %s\n", __FUNCTION__);
}
static enum phl_mdl_ret_code
_phl_ser_mdl_start(void *dispr, void *priv)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
struct phl_info_t *phl_info = cser->phl_info;
if (CMD_SER_SRC_POLL == cser->evtsrc) {
/* Disable L0 Reset Notify from FW to driver */
rtw_hal_ser_set_error_status(phl_info->hal, RTW_PHL_SER_L0_CFG_DIS_NOTIFY);
}
_ser_reset_status(cser);
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code
_phl_ser_mdl_stop(void *dispr, void *priv)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
void *drv = phl_to_drvpriv(cser->phl_info);
_os_cancel_timer(drv, &cser->poll_timer);
return MDL_RET_SUCCESS;
}
static enum phl_mdl_ret_code
_phl_ser_mdl_msg_hdlr(void *dispr,
void *priv,
struct phl_msg *msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
if (IS_MSG_FAIL(msg->msg_id)) {
PHL_INFO("%s :: MSG(%d)_FAIL - EVT_ID=%d \n", __func__,
MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
return _ser_fail_ev_hdlr(dispr, priv, msg);
}
switch (MSG_MDL_ID_FIELD(msg->msg_id)) {
case PHL_MDL_SER:
if (IS_MSG_IN_PRE_PHASE(msg->msg_id))
ret = _ser_hdl_internal_evt(dispr, priv, msg);
break;
default:
ret = _ser_hdl_external_evt(dispr, priv, msg);
break;
}
return ret;
}
static enum phl_mdl_ret_code
_phl_ser_mdl_set_info(void *dispr,
void *priv,
struct phl_module_op_info *info)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
/* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */
switch (info->op_code) {
case BK_MODL_OP_INPUT_CMD:
if (info->inbuf) {
cser->ser_l2_hdlr=(u8 (*)(void *))info->inbuf;
}
ret = MDL_RET_SUCCESS;
break;
}
return ret;
}
static enum phl_mdl_ret_code
_phl_ser_mdl_query_info(void *dispr,
void *priv,
struct phl_module_op_info *info)
{
struct cmd_ser *cser = (struct cmd_ser *)priv;
void *drv = phl_to_drvpriv(cser->phl_info);
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
/* PHL_INFO(" %s :: info->op_code=%d \n", __func__, info->op_code); */
switch (info->op_code) {
case BK_MODL_OP_STATE:
_os_mem_cpy(drv, (void*)info->inbuf, &cser->state, 1);
ret = MDL_RET_SUCCESS;
break;
}
return ret;
}
static struct phl_bk_module_ops ser_ops= {
.init = _phl_ser_mdl_init,
.deinit = _phl_ser_mdl_deinit,
.start = _phl_ser_mdl_start,
.stop = _phl_ser_mdl_stop,
.msg_hdlr = _phl_ser_mdl_msg_hdlr,
.set_info = _phl_ser_mdl_set_info,
.query_info = _phl_ser_mdl_query_info,
};
enum rtw_phl_status
phl_register_ser_module(struct phl_info_t *phl_info)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
phl_status = phl_disp_eng_register_module(phl_info,
HW_BAND_0,
PHL_MDL_SER,
&ser_ops);
if (RTW_PHL_STATUS_SUCCESS != phl_status) {
PHL_ERR("%s register SER module in cmd disp failed! \n", __func__);
}
return phl_status;
}
#ifdef CONFIG_PHL_CMD_SER
u8 phl_ser_inprogress(void *phl)
{
struct phl_module_op_info op_info = {0};
u8 state = 0;
op_info.op_code = BK_MODL_OP_STATE;
op_info.inbuf = (u8*)&state;
op_info.inlen = 1;
if (rtw_phl_query_bk_module_info(phl,
HW_BAND_0,
PHL_MDL_SER,
&op_info) == RTW_PHL_STATUS_SUCCESS) {
if (state) /* non-CMD_SER_NOT_OCCUR */
return true;
}
return false;
}
enum rtw_phl_status
phl_ser_send_msg(void *phl, enum RTW_PHL_SER_NOTIFY_EVENT notify)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_msg nextmsg = {0};
struct phl_msg_attribute attr = {0};
u16 event = 0;
switch (notify) {
case RTW_PHL_SER_PAUSE_TRX: /* M1 */
event = MSG_EVT_SER_M1_PAUSE_TRX;
break;
case RTW_PHL_SER_DO_RECOVERY: /* M3 */
event = MSG_EVT_SER_M3_DO_RECOV;
break;
case RTW_PHL_SER_READY: /* M5 */
event = MSG_EVT_SER_M5_READY;
break;
case RTW_PHL_SER_L2_RESET: /* M9 */
event = MSG_EVT_SER_M9_L2_RESET;
break;
case RTW_PHL_SER_EVENT_CHK:
event = MSG_EVT_SER_EVENT_CHK;
break;
case RTW_PHL_SER_L0_RESET:
default:
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "phl_ser_send_msg(): unsupported case %d\n",
notify);
return RTW_PHL_STATUS_FAILURE;
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "phl_ser_send_msg(): event %d\n", event);
SET_MSG_MDL_ID_FIELD(nextmsg.msg_id, PHL_MDL_SER);
SET_MSG_EVT_ID_FIELD(nextmsg.msg_id, event);
nextmsg.band_idx = HW_BAND_0;
phl_status = rtw_phl_send_msg_to_dispr(phl,
&nextmsg,
&attr,
NULL);
if (phl_status != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("[CMD_SER] send_msg_to_dispr fail! (%d)\n", event);
}
return phl_status;
}
#endif
#ifndef CONFIG_FSM
/* The same as phl_fw_watchdog_timeout_notify of fsm-ser */
enum rtw_phl_status
phl_fw_watchdog_timeout_notify(void *phl)
{
enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "phl_fw_watchdog_timeout_notify triggle L2 Reset !!!\n");
return phl_ser_send_msg(phl, notify);
}
enum rtw_phl_status rtw_phl_ser_l2_notify(struct rtw_phl_com_t *phl_com)
{
enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_phl_ser_l2_notify triggle L2 Reset !!!\n");
return phl_ser_send_msg(phl_com->phl_priv, notify);
}
/* The same as rtw_phl_ser_dump_ple_buffer of fsm-ser */
enum rtw_phl_status
rtw_phl_ser_dump_ple_buffer(void *phl)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_, "rtw_phl_ser_dump_ple_buffer\n");
rtw_hal_dump_fw_rsvd_ple(phl_info->hal);
return RTW_PHL_STATUS_SUCCESS;
}
#endif /*#ifndef CONFIG_FSM*/
|
2301_81045437/rtl8852be
|
phl/phl_cmd_ser.c
|
C
|
agpl-3.0
| 25,203
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHL_CMD_SER_H__
#define __PHL_CMD_SER_H__
#ifndef CONFIG_FSM
enum rtw_phl_status phl_fw_watchdog_timeout_notify(void *phl);
enum rtw_phl_status rtw_phl_ser_dump_ple_buffer(void *phl);
#endif
enum rtw_phl_status phl_ser_send_msg(void *phl, enum RTW_PHL_SER_NOTIFY_EVENT notify);
#ifdef CONFIG_PHL_CMD_SER
enum rtw_phl_status
phl_register_ser_module(struct phl_info_t *phl_info);
#endif
#endif /* __PHL_CMD_SER_H__ */
|
2301_81045437/rtl8852be
|
phl/phl_cmd_ser.h
|
C
|
agpl-3.0
| 1,086
|
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CONFIG_H_
#define _PHL_CONFIG_H_
/* Define correspoding PHL Feature based on information from the Core */
#ifdef PHL_PLATFORM_AP
#define PHL_FEATURE_AP
#elif defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS)
#define PHL_FEATURE_NIC
#else
#define PHL_FEATURE_NONE
#endif
/******************* PLATFORM Section **************************/
#ifdef PHL_FEATURE_NONE/* enable compile flag for phl only compilation check */
#define CONFIG_DFS 1
#define CONFIG_USB_TX_AGGREGATION
#define CONFIG_USB_RX_AGGREGATION
#define CONFIG_USB_TX_PADDING_CHK
#define CONFIG_LOAD_PHY_PARA_FROM_FILE
#define CONFIG_WOW
#define CONFIG_WPA3_SUITEB_SUPPORT
#define CONFIG_SYNC_INTERRUPT
#define CONFIG_MR_SUPPORT
#ifdef CONFIG_MR_SUPPORT
#define CONFIG_SCC_SUPPORT
#define CONFIG_MCC_SUPPORT
#ifdef CONFIG_MCC_SUPPORT
#define MCC_ROLE_NUM 2
#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
#define RTW_WKARD_HALRF_MCC
#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
#endif /*CONFIG_MCC_SUPPORT*/
#define CONFIG_DBCC_SUPPORT
#define DBG_PHL_CHAN
#define DBG_PHL_MR
#define PHL_MR_PROC_CMD
#define DBG_CHCTX_RMAP
#endif /*CONFIG_MR_SUPPORT*/
#define DBG_PHL_MAC_REG_RW
#define CONFIG_RTW_ACS
#define CONFIG_RX_PSTS_PER_PKT
#define CONFIG_PHL_TXSC
#define RTW_PHL_BCN
#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
#define CONFIG_PHL_TWT
#define CONFIG_CMD_DISP
#ifdef CONFIG_CMD_DISP
#define CONFIG_PHL_ECSA
/*#define CONFIG_CMD_DISP_SOLO_MODE*/
#define CONFIG_PHL_CMD_SCAN
#define CONFIG_PHL_CMD_SER
#define CONFIG_PHL_CMD_BTC
#endif
#ifdef CONFIG_PCI_HCI
#define PCIE_TRX_MIT_EN
#endif
#define CONFIG_PHL_P2PPS
#define CONFIG_6GHZ
#define RTW_WKARD_BFEE_SET_AID
#define CONFIG_PHL_THERMAL_PROTECT
#define CONFIG_PHL_TX_DBG
#endif /* PHL_FEATURE_NONE */
#ifdef PHL_PLATFORM_WINDOWS
#ifndef CONFIG_FSM
#define CONFIG_FSM
#endif
#ifndef CONFIG_CMD_DISP
#define CONFIG_CMD_DISP
#endif
#endif
#ifdef PHL_PLATFORM_LINUX
/* comment out cfg temporarily */
/*
#define CONFIG_FSM
#ifndef CONFIG_FSM
#define CONFIG_CMD_DISP
#endif
*/
#endif
/******************* Feature flags **************************/
#ifdef CONFIG_PHL_TEST_SUITE
#define CONFIG_PHL_TEST_MP
#define CONFIG_PHL_TEST_VERIFY
#endif
#ifdef CONFIG_CORE_SYNC_INTERRUPT
#define CONFIG_SYNC_INTERRUPT
#endif
#ifdef CONFIG_WOW
#define CONFIG_WOWLAN
/* #define RTW_WKARD_WOW_SKIP_AOAC_RPT */
/* #define RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG */
#define RTW_WKARD_WOW_L2_PWR
#define DBG_RST_BDRAM_TIME
#endif
/*CONFIG_IFACE_NUMBER*/
#ifdef CONFIG_IFACE_NUMBER
#define MAX_WIFI_ROLE_NUMBER CONFIG_IFACE_NUMBER
#else
#define MAX_WIFI_ROLE_NUMBER 5
#endif
#ifdef CONFIG_CONCURRENT_MODE
#define CONFIG_MR_SUPPORT
#endif
#ifdef CONFIG_REUSED_FWDL_BUF
#define CONFIG_PHL_REUSED_FWDL_BUF
#endif
#ifdef CONFIG_MR_SUPPORT
#define CONFIG_SCC_SUPPORT
#define CONFIG_MCC_SUPPORT
#ifdef CONFIG_MCC_SUPPORT
#define MCC_ROLE_NUM 2
#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
#define RTW_WKARD_HALRF_MCC
#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
#endif /*CONFIG_MCC_SUPPORT*/
/*#define CONFIG_DBCC_SUPPORT*/
#define DBG_PHL_CHAN
#define DBG_PHL_MR
#define PHL_MR_PROC_CMD
#define DBG_CHCTX_RMAP
#endif
#define DBG_PHL_STAINFO
#define PHL_MAX_STA_NUM 128
/**** CONFIG_CMD_DISP ***/
#ifdef DISABLE_CMD_DISPR
#undef CONFIG_CMD_DISP
#endif
#ifdef CONFIG_CMD_DISP
/* enable SOLO mode define to create seperated background thread per dispatcher,
* otherwise, all dispatcher would share single background thread, which is in share mode.
*/
/*#define CONFIG_CMD_DISP_SOLO_MODE*/
/* Enable Self-Defined Sequence feature for sender to rearrange dispatch order,
* Since this is not a mandatory feature and would have addiional memory cost (arround 2200 Bytes)
* Disable by default.
*/
/*#define CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ*/
#ifndef CONFIG_FSM
#define CONFIG_SND_CMD
#endif
#define CONFIG_PHL_CMD_SCAN
#ifdef CONFIG_CMD_SER
#define CONFIG_PHL_CMD_SER
#endif
#define CONFIG_PHL_CMD_BTC
#endif /**** CONFIG_CMD_DISP ***/
#define CONFIG_GEN_GIT_INFO 1
/*#define CONFIG_NEW_HALMAC_INTERFACE*/
#define CONFIG_BTCOEX
#ifdef CONFIG_USB_TX_PADDING_CHK
#define CONFIG_PHL_USB_TX_PADDING_CHK
#endif
#ifdef CONFIG_USB_TX_AGGREGATION
#define CONFIG_PHL_USB_TX_AGGREGATION
#endif
#ifdef CONFIG_USB_RX_AGGREGATION
#define CONFIG_PHL_USB_RX_AGGREGATION
#endif
#if CONFIG_DFS
#define CONFIG_PHL_DFS
#endif
#ifdef CONFIG_PHL_DFS
/*#define CONFIG_PHL_DFS_REGD_FCC*/
/*#define CONFIG_PHL_DFS_REGD_JAP*/
#define CONFIG_PHL_DFS_REGD_ETSI
#endif
#ifdef CONFIG_WPP
#define CONFIG_PHL_WPP
#endif
#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
#define CONFIG_PHL_CSUM_OFFLOAD_RX
#endif
#ifdef CONFIG_RX_PSTS_PER_PKT
#define CONFIG_PHL_RX_PSTS_PER_PKT
#define RTW_WKARD_DISABLE_PSTS_PER_PKT_DATA
#endif
#ifdef CONFIG_SDIO_RX_NETBUF_ALLOC_IN_PHL
#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
#endif
#ifdef CONFIG_SDIO_READ_RXFF_IN_INT
#define CONFIG_PHL_SDIO_READ_RXFF_IN_INT
#endif
#ifdef CONFIG_ECSA
#define CONFIG_PHL_ECSA
#ifdef CONFIG_ECSA_EXTEND_OPTION
#define CONFIG_PHL_ECSA_EXTEND_OPTION
#endif
#endif
#ifdef CONFIG_TWT
#define CONFIG_PHL_TWT
#endif
#ifdef CONFIG_RA_TXSTS_DBG
#define CONFIG_PHL_RA_TXSTS_DBG
#endif
#ifdef CONFIG_USB_RELEASE_RPT
#define CONFIG_PHL_USB_RELEASE_RPT_ENABLE
#endif
#ifdef CONFIG_P2PPS
#define CONFIG_PHL_P2PPS
#endif
#ifdef CONFIG_TX_DBG
#define CONFIG_PHL_TX_DBG
#endif
#ifdef CONFIG_PCI_HCI
#ifdef CONFIG_PCIE_TRX_MIT
#define PCIE_TRX_MIT_EN
#endif
#endif
#ifdef CONFIG_THERMAL_PROTECT
#define CONFIG_PHL_THERMAL_PROTECT
#endif
#ifdef CONFIG_RX_BATCH_IND
#define PHL_RX_BATCH_IND
#endif
#ifdef CONFIG_TDLS
#define CONFIG_PHL_TDLS
#endif
#ifdef CONFIG_SDIO_HCI
/* For SDIO TX TP TST - START */
#define SDIO_TX_THREAD /* Use dedicate thread for SDIO TX */
/* For SDIO TX TP TST - ENDT */
#endif /* CONFIG_SDIO_HCI */
#ifdef CONFIG_MAC_REG_RW_CHK
#define DBG_PHL_MAC_REG_RW
#endif
/******************* WKARD flags **************************/
#define RTW_WKARD_P2PPS_REFINE
#define RTW_WKARD_P2PPS_SINGLE_NOA
#define RTW_WKARD_P2PPS_NOA_MCC
#ifdef PHL_PLATFORM_LINUX
#define RTW_WKARD_RF_CR_DUMP
#define RTW_WKARD_LINUX_CMD_WKARD
#endif
#ifdef PHL_PLATFORM_WINDOWS
/* Workaround for doing hal reset in changing MP mode will lost the mac entry */
#define RTW_WKARD_MP_MODE_CHANGE
#define RTW_WKARD_WIN_TRX_BALANCE
#define RTW_WKARD_DYNAMIC_LTR
#endif
#define RTW_WKARD_PHY_CAP
#define RTW_WKARD_LAMODE
#define RTW_WKARD_TXSC
#define RTW_WKARD_BB_C2H
/*
* One workaround of EFUSE operation
* 1. Dump EFUSE with FW fail
*/
#define RTW_WKARD_EFUSE_OPERATION
#define RTW_WKARD_STA_BCN_INTERVAL
#define RTW_WKARD_SER_L1_EXPIRE
#ifdef CONFIG_USB_HCI
#define RTW_WKARD_SER_USB_POLLING_EVENT
#endif
/* #define RTW_WKARD_SER_USB_DISABLE_L1_RCVY_FLOW */
#define RTW_WKARD_BTC_RFETYPE
#define RTW_WKARD_TXBD_UPD_LMT /* 8852AE/8852BE txbd index update limitation */
#ifdef CONFIG_WPA3_SUITEB_SUPPORT
#define RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
#endif
/* Workaround for cmac table config
* - Default is disabled until halbb is ready
* - This workaround will be removed once fw handles this cfg
*/
/*#define RTW_WKARD_DEF_CMACTBL_CFG*/
/* Workaround for efuse read hidden report
* - Default is disabled until halmac is ready
*/
#define RTW_WKARD_PRELOAD_TRX_RESET
/* Workaround for cmac table config
* - This workaround will be removed once fw handles this cfg
*/
#define RTW_WKARD_DEF_CMACTBL_CFG
#define RTW_WKARD_USB_TXAGG_BULK_END_WD
#ifdef CONFIG_HOMOLOGATION
#define CONFIG_PHL_HOMOLOGATION
#endif
#ifdef RTW_WKARD_TX_DISABLE_BFEE
#define RTW_WKARD_DYNAMIC_BFEE_CAP
#endif
#ifdef RTW_WKARD_NTFY_MEDIA_STS
#define RTW_WKARD_PHL_NTFY_MEDIA_STS
#endif
#ifdef RTW_WKARD_PHY_INFO_NTFY
#define CONFIG_PHY_INFO_NTFY
#endif
/* LPS should disable other role */
#define RTW_WKARD_LPS_ROLE_CONFIG
#ifdef PHL_PLATFORM_WINDOWS
#define CONFIG_WOW_WITH_SER
#endif
#ifdef PHL_PLATFORM_WINDOWS
#define CONFIG_DBG_H2C_TX
#endif
/*
* Workaround for MRC bk module call phl_mr_offch_hdl with scan_issue_null_data
* ops, this should be replaced with phl issue null data function.
*/
#define RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
/*
* Workaround for phl_mr_offch_hdl sleep after issue null data,
* - This workaround will be removed once tx report is ready
*/
#ifndef RTW_WKARD_TX_NULL_WD_RP
#define RTW_WKARD_ISSUE_NULL_SLEEP_PROTECTION
#endif
#ifdef RTW_WKARD_LPS_IQK_TWICE
#define RTW_WKARD_PHL_LPS_IQK_TWICE
#endif
#ifdef RTW_WKARD_FSM_SCAN_PASSIVE_TO_ACTIVE
#define RTW_WKARD_PHL_FSM_SCAN_PASSIVE_TO_ACTIVE
#endif
#define RTW_WKARD_BUSCAP_IN_HALSPEC
#define RTW_WKARD_IBSS_SNIFFER_MODE
#define RTW_WKARD_SINGLE_PATH_RSSI
/* #define CONFIG_6GHZ */
#define RTW_WKARD_BFEE_DISABLE_NG16
#define RTW_WKARD_HW_WMM_ALLOCATE
#ifdef RTW_WKARD_BFEE_AID
#define RTW_WKARD_BFEE_SET_AID
#endif
#define RTW_WKARD_AP_CLIENT_ADD_DEL_NTY
#ifdef RTW_WKARD_DISABLE_2G40M_ULOFDMA
#define RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
#endif
#endif /*_PHL_CONFIG_H_*/
|
2301_81045437/rtl8852be
|
phl/phl_config.h
|
C
|
agpl-3.0
| 9,677
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "phl_headers.h"
#ifdef CONFIG_STA_CMD_DISPR
enum rtw_phl_status rtw_phl_connect_prepare(void *phl,
struct rtw_wifi_role_t *wrole,
u8 *addr)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_CONNECT_START);
msg.band_idx = wrole->hw_band;
phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(phl_status != RTW_PHL_STATUS_SUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n",
__FUNCTION__);
goto exit;
}
exit:
return phl_status;
}
enum rtw_phl_status
rtw_phl_connect_linked(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta,
u8 *sta_addr)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_CONNECT_LINKED);
msg.band_idx = wrole->hw_band;
msg.rsvd[0] = sta;
msg.rsvd[1] = sta_addr;
phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(phl_status != RTW_PHL_STATUS_SUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n",
__FUNCTION__);
goto exit;
}
exit:
return phl_status;
}
enum rtw_phl_status rtw_phl_connected(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_CONNECT_END);
msg.band_idx = wrole->hw_band;
phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(phl_status != RTW_PHL_STATUS_SUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n",
__FUNCTION__);
goto exit;
}
exit:
return phl_status;
}
enum rtw_phl_status rtw_phl_disconnect(void *phl,
struct rtw_wifi_role_t *wrole,
bool is_disconnect)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
if(is_disconnect) {
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_DISCONNECT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT_PREPARE);
} else {
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_CONNECT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_DISCONNECT);
}
msg.band_idx = wrole->hw_band;
msg.rsvd[0] = (u8*)wrole;
phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(phl_status != RTW_PHL_STATUS_SUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n",
__FUNCTION__);
goto exit;
}
exit:
return phl_status;
}
#else /* CONFIG_STA_CMD_DISPR */
enum rtw_phl_status rtw_phl_connect_prepare(void *phl,
struct rtw_wifi_role_t *wrole,
u8 *addr)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
wrole->mstate = MLME_LINKING;
psts = phl_role_notify(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s role notify failed\n", __func__);
goto _exit;
}
psts = phl_mr_info_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s mr info upt failed\n", __func__);
goto _exit;
}
psts = rtw_phl_mr_rx_filter(phl, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_rx_filter failed\n", __func__);
goto _exit;
}
#ifdef CONFIG_PHL_P2PPS
/* pasue all NoA */
phl_p2pps_noa_all_role_pause(phl, wrole->hw_band);
#endif
PHL_DUMP_MR_EX(phl_info);
_exit:
FUNCOUT();
return psts;
}
enum rtw_phl_status rtw_phl_connected(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
if (wrole->type == PHL_RTYPE_STATION || wrole->type == PHL_RTYPE_P2P_GC) {
psts = phl_role_notify(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s role notify failed\n", __func__);
goto _exit;
}
}
psts = phl_mr_info_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s mr info upt failed\n", __func__);
goto _exit;
}
psts = rtw_phl_mr_rx_filter(phl, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_rx_filter failed\n", __func__);
goto _exit;
}
psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_STA_CONN_END);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_tsf_sync failed\n", __func__);
goto _exit;
}
#if 0
psts = phl_mr_state_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s phl_mr_state_upt failed\n", __func__);
goto _exit;
}
#endif
PHL_DUMP_MR_EX(phl_info);
_exit:
FUNCOUT();
return psts;
}
enum rtw_phl_status rtw_phl_disconnect_prepare(void *phl,
struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
#ifdef CONFIG_PHL_P2PPS
/* disable NoA for this role */
phl_p2pps_noa_disable_all(phl_info, wrole);
/* pasue buddy NoA */
phl_p2pps_noa_all_role_pause(phl_info, wrole->hw_band);
#endif
FUNCOUT();
return psts;
}
enum rtw_phl_status rtw_phl_disconnect(void *phl,
struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
if (wrole->type == PHL_RTYPE_STATION || wrole->type == PHL_RTYPE_P2P_GC) {
psts = phl_role_notify(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s role notify failed\n", __func__);
goto _exit;
}
}
psts = phl_mr_info_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s mr info upt failed\n", __func__);
goto _exit;
}
psts = rtw_phl_mr_rx_filter(phl, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_rx_filter failed\n", __func__);
goto _exit;
}
psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_STA_DIS_CONN);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_tsf_sync failed\n", __func__);
goto _exit;
}
psts = phl_mr_state_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s phl_mr_state_upt failed\n", __func__);
goto _exit;
}
rtw_hal_disconnect_notify(phl_info->hal, &wrole->chandef);
#ifdef CONFIG_PHL_P2PPS
/* resume buddy NoA */
phl_p2pps_noa_all_role_resume(phl, wrole->hw_band);
#endif
PHL_DUMP_MR_EX(phl_info);
_exit:
FUNCOUT();
return psts;
}
#endif
#ifdef CONFIG_AP_CMD_DISPR
enum rtw_phl_status rtw_phl_ap_started(void *phl, struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_START);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_START);
msg.band_idx = wrole->hw_band;
phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(phl_status != RTW_PHL_STATUS_SUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n",
__FUNCTION__);
goto exit;
}
exit:
return phl_status;
}
enum rtw_phl_status rtw_phl_ap_stop(void *phl, struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_FG_MDL_AP_STOP);
SET_MSG_EVT_ID_FIELD(msg.msg_id, MSG_EVT_AP_STOP_PREPARE);
msg.band_idx = wrole->hw_band;
msg.rsvd[0] = (u8*)wrole;
phl_status = phl_disp_eng_send_msg(phl_info, &msg, &attr, NULL);
if(phl_status != RTW_PHL_STATUS_SUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s: Dispr send msg fail!\n",
__FUNCTION__);
goto exit;
}
exit:
return phl_status;
}
#else /* CONFIG_AP_CMD_DISPR */
enum rtw_phl_status rtw_phl_ap_start_prepare(void *phl, struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS;
FUNCIN();
#ifdef CONFIG_PHL_P2PPS
/* pasue all NoA */
phl_p2pps_noa_all_role_pause(phl, wrole->hw_band);
#endif
FUNCOUT();
return psts;
}
enum rtw_phl_status rtw_phl_ap_started(void *phl, struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
psts = phl_role_notify(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s role notify failed\n", __func__);
goto _exit;
}
psts = phl_mr_info_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s mr info upt failed\n", __func__);
goto _exit;
}
psts = rtw_phl_mr_rx_filter(phl, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_rx_filter failed\n", __func__);
goto _exit;
}
psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_AP_START);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_tsf_sync failed\n", __func__);
goto _exit;
}
psts = phl_mr_state_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s phl_mr_state_upt failed\n", __func__);
goto _exit;
}
PHL_DUMP_MR_EX(phl_info);
_exit:
FUNCOUT();
return psts;
}
enum rtw_phl_status rtw_phl_ap_stop_prepare(void *phl, struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
#ifdef CONFIG_PHL_P2PPS
/* disable NoA for this role */
phl_p2pps_noa_disable_all(phl_info, wrole);
/* pasue buddy NoA */
phl_p2pps_noa_all_role_pause(phl_info, wrole->hw_band);
#endif
FUNCOUT();
return psts;
}
enum rtw_phl_status rtw_phl_ap_stop(void *phl, struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
FUNCIN();
wrole->mstate = MLME_NO_LINK;
psts = phl_role_notify(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s role notify failed\n", __func__);
goto _exit;
}
psts = phl_mr_info_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s mr info upt failed\n", __func__);
goto _exit;
}
psts = rtw_phl_mr_rx_filter(phl, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_rx_filter failed\n", __func__);
goto _exit;
}
psts = phl_mr_tsf_sync(phl, wrole, PHL_ROLE_MSTS_AP_STOP);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s set mr_tsf_sync failed\n", __func__);
goto _exit;
}
psts = phl_mr_state_upt(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s phl_mr_state_upt failed\n", __func__);
goto _exit;
}
#ifdef RTW_PHL_BCN
psts = rtw_phl_free_bcn_entry(phl_info, wrole);
if (psts != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s phl_free_bcn_entry failed\n", __func__);
goto _exit;
}
#endif
rtw_hal_disconnect_notify(phl_info->hal, &wrole->chandef);
#ifdef CONFIG_PHL_P2PPS
/* resume buddy NoA */
phl_p2pps_noa_all_role_resume(phl, wrole->hw_band);
#endif
PHL_DUMP_MR_EX(phl_info);
_exit:
FUNCOUT();
return psts;
}
#endif
#ifdef CONFIG_IBSS_CMD_DISPR
enum rtw_phl_status rtw_phl_ibss_started(void *phl, struct rtw_wifi_role_t *wrole)
{
PHL_ERR("%s failed, cmd dispatcher not support\n", __func__);
return RTW_PHL_STATUS_FAILURE;
}
#else /* CONFIG_IBSS_CMD_DISPR */
enum rtw_phl_status rtw_phl_ibss_started(void *phl, struct rtw_wifi_role_t *wrole)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
#ifdef RTW_WKARD_IBSS_SNIFFER_MODE
rtw_hal_set_rxfltr_by_mode(phl_info->hal, wrole->hw_band,
RX_FLTR_MODE_SNIFFER);
#endif
return RTW_PHL_STATUS_SUCCESS;
}
#endif
enum rtw_phl_status
rtw_phl_disconnected_resume_hdlr(void *phl,
struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s wrole->id(%d)\n",
__func__, wrole->id);
#ifdef CONFIG_PHL_P2PPS
/* resume buddy NoA */
phl_p2pps_noa_all_role_resume(phl_info, wrole->hw_band);
#endif
#ifdef CONFIG_MCC_SUPPORT
/* Enable MR coex mechanism(if needed) */
psts = phl_mr_coex_handle(phl_info, wrole, 0, wrole->hw_band,
MR_COEX_TRIG_BY_DIS_LINKING);
#endif
PHL_DUMP_MR_EX(phl_info);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s psts(%d)\n",
__func__, psts);
return psts;
}
enum rtw_phl_status
rtw_phl_ap_stop_resume_hdlr(void *phl,
struct rtw_wifi_role_t *wrole)
{
enum rtw_phl_status psts = RTW_PHL_STATUS_SUCCESS;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s wrole->id(%d)\n",
__func__, wrole->id);
#ifdef CONFIG_PHL_P2PPS
/* resume buddy NoA */
phl_p2pps_noa_all_role_resume(phl_info, wrole->hw_band);
#endif
#ifdef CONFIG_MCC_SUPPORT
/* Enable MR coex mechanism(if needed) */
psts = phl_mr_coex_handle(phl_info, wrole, 0, wrole->hw_band,
MR_COEX_TRIG_BY_DIS_LINKING);
#endif
PHL_DUMP_MR_EX(phl_info);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "%s psts(%d)\n",
__func__, psts);
return psts;
}
#ifdef RTW_WKARD_P2P_LISTEN
enum rtw_phl_status rtw_phl_p2p_listen_start(void *phl, struct rtw_wifi_role_t *wrole)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
rtw_hal_set_rxfltr_by_mode(phl_info->hal, wrole->hw_band,
RX_FLTR_MODE_SNIFFER);
return RTW_PHL_STATUS_SUCCESS;
}
enum rtw_phl_status rtw_phl_p2p_listen_end(void *phl, struct rtw_wifi_role_t *wrole)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
/* restore rx filter mode */
rtw_phl_mr_rx_filter(phl_info, wrole);
return RTW_PHL_STATUS_SUCCESS;
}
#endif /* RTW_WKARD_P2P_LISTEN */
|
2301_81045437/rtl8852be
|
phl/phl_connect.c
|
C
|
agpl-3.0
| 14,718
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CONNECT_H_
#define _PHL_CONNECT_H_
/**
* rtw_phl_connect_prepare() - Prepare hardware setting for connecting
* @phl: struct phl_info_t *
* @wrole: struct rtw_wifi_role_t *
* @addr: target mac address
*
* Do all necessary hardware setting for connecting.
*
* Return RTW_PHL_STATUS_SUCCESS for success, otherwise fail.
*/
enum rtw_phl_status rtw_phl_connect_prepare(void *phl,
struct rtw_wifi_role_t *wrole,
u8 *addr);
/**
* rtw_phl_connect_linked() - update media status
* @phl: struct phl_info_t *
* @wrole: struct rtw_wifi_role_t *
* @sta: struct rtw_phl_stainfo_t *
* @sta_addr: target mac address
*
* Do all necessary hardware setting for linked.
*
* Return RTW_PHL_STATUS_SUCCESS for success, otherwise fail.
*/
enum rtw_phl_status
rtw_phl_connect_linked(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta,
u8 *sta_addr);
/**
* rtw_phl_connected() - Config hardware setting for connected
* @phl: struct phl_info_t *
* @wrole: struct rtw_wifi_role_t *
* @sta: target station info
*
* Do all necessary hardware setting for connected.
*
* Return RTW_PHL_STATUS_SUCCESS for success, otherwise fail.
*/
enum rtw_phl_status rtw_phl_connected(void *phl,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta);
#ifdef CONFIG_STA_CMD_DISPR
enum rtw_phl_status rtw_phl_disconnect(void *phl,
struct rtw_wifi_role_t *wrole,
bool is_disconnect);
#else
enum rtw_phl_status rtw_phl_disconnect_prepare(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status rtw_phl_disconnect(void *phl,
struct rtw_wifi_role_t *wrole);
#endif
enum rtw_phl_status rtw_phl_ap_start_prepare(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status rtw_phl_ap_started(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status rtw_phl_ap_stop_prepare(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status rtw_phl_ap_stop(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status rtw_phl_ibss_started(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status
rtw_phl_disconnected_resume_hdlr(void *phl,
struct rtw_wifi_role_t *wrole);
enum rtw_phl_status
rtw_phl_ap_stop_resume_hdlr(void *phl,
struct rtw_wifi_role_t *wrole);
#ifdef RTW_WKARD_P2P_LISTEN
enum rtw_phl_status rtw_phl_p2p_listen_start(void *phl, struct rtw_wifi_role_t *wrole);
enum rtw_phl_status rtw_phl_p2p_listen_end(void *phl, struct rtw_wifi_role_t *wrole);
#endif /* RTW_WKARD_P2P_LISTEN */
#endif /* _PHL_CONNECT_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_connect.h
|
C
|
agpl-3.0
| 3,321
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "phl_headers.h"
#include "phl_country.h"
const struct country_domain_mapping cdmap[MAX_COUNTRY_NUM] = {
{0x4d, 0x00, {'A', 'R'}, TPO_NA, 0x0f}, /* 0000 */
{0x61, 0x00, {'B', 'O'}, TPO_NA, 0x0f}, /* 0001 */
{0x62, 0x00, {'B', 'R'}, TPO_NA, 0x0f}, /* 0002 */
{0x76, 0x00, {'C', 'L'}, TPO_CHILE, 0x0f}, /* 0003 */
{0x76, 0x00, {'C', 'O'}, TPO_NA, 0x0f}, /* 0004 */
{0x76, 0x00, {'C', 'R'}, TPO_NA, 0x0f}, /* 0005 */
{0x76, 0x00, {'E', 'C'}, TPO_NA, 0x0f}, /* 0006 */
{0x76, 0x00, {'S', 'V'}, TPO_NA, 0x0f}, /* 0007 */
{0x76, 0x00, {'G', 'T'}, TPO_NA, 0x0f}, /* 0008 */
{0x32, 0x00, {'H', 'N'}, TPO_NA, 0x0f}, /* 0009 */
{0x4d, 0x00, {'M', 'X'}, TPO_NA, 0x0f}, /* 0010 */
{0x76, 0x00, {'N', 'I'}, TPO_NA, 0x0f}, /* 0011 */
{0x76, 0x00, {'P', 'A'}, TPO_NA, 0x0f}, /* 0012 */
{0x76, 0x00, {'P', 'Y'}, TPO_NA, 0x0f}, /* 0013 */
{0x76, 0x00, {'P', 'E'}, TPO_NA, 0x0f}, /* 0014 */
{0x76, 0x7f, {'U', 'S'}, TPO_NA, 0x0f}, /* 0015 */
{0x30, 0x00, {'U', 'Y'}, TPO_NA, 0x0f}, /* 0016 */
{0x30, 0x00, {'V', 'E'}, TPO_NA, 0x0f}, /* 0017 */
{0x76, 0x00, {'P', 'R'}, TPO_NA, 0x0f}, /* 0018 */
{0x76, 0x00, {'D', 'O'}, TPO_NA, 0x0f}, /* 0019 */
{0x5e, 0x00, {'A', 'T'}, TPO_NA, 0x0f}, /* 0020 */
{0x5e, 0x00, {'B', 'E'}, TPO_NA, 0x0f}, /* 0021 */
{0x5e, 0x00, {'C', 'Y'}, TPO_NA, 0x0f}, /* 0022 */
{0x5e, 0x00, {'C', 'Z'}, TPO_NA, 0x0f}, /* 0023 */
{0x5e, 0x00, {'D', 'K'}, TPO_NA, 0x0f}, /* 0024 */
{0x5e, 0x00, {'E', 'E'}, TPO_NA, 0x0f}, /* 0025 */
{0x5e, 0x00, {'F', 'I'}, TPO_NA, 0x0f}, /* 0026 */
{0x5e, 0x00, {'F', 'R'}, TPO_NA, 0x0f}, /* 0027 */
{0x5e, 0x00, {'D', 'E'}, TPO_NA, 0x0f}, /* 0028 */
{0x5e, 0x00, {'G', 'R'}, TPO_NA, 0x0f}, /* 0029 */
{0x5e, 0x00, {'H', 'U'}, TPO_NA, 0x0f}, /* 0030 */
{0x5e, 0x00, {'I', 'S'}, TPO_NA, 0x0f}, /* 0031 */
{0x5e, 0x00, {'I', 'E'}, TPO_NA, 0x0f}, /* 0032 */
{0x5e, 0x00, {'I', 'T'}, TPO_NA, 0x0f}, /* 0033 */
{0x5e, 0x00, {'L', 'V'}, TPO_NA, 0x0f}, /* 0034 */
{0x5e, 0x00, {'L', 'I'}, TPO_NA, 0x0f}, /* 0035 */
{0x5e, 0x00, {'L', 'T'}, TPO_NA, 0x0f}, /* 0036 */
{0x5e, 0x00, {'L', 'U'}, TPO_NA, 0x0f}, /* 0037 */
{0x5e, 0x00, {'M', 'T'}, TPO_NA, 0x0f}, /* 0038 */
{0x5e, 0x00, {'M', 'C'}, TPO_NA, 0x0f}, /* 0039 */
{0x5e, 0x00, {'N', 'L'}, TPO_NA, 0x0f}, /* 0040 */
{0x5e, 0x00, {'N', 'O'}, TPO_NA, 0x0f}, /* 0041 */
{0x5e, 0x00, {'P', 'L'}, TPO_NA, 0x0f}, /* 0042 */
{0x5e, 0x00, {'P', 'T'}, TPO_NA, 0x0f}, /* 0043 */
{0x5e, 0x00, {'S', 'K'}, TPO_NA, 0x0f}, /* 0044 */
{0x5e, 0x00, {'S', 'I'}, TPO_NA, 0x0f}, /* 0045 */
{0x5e, 0x00, {'E', 'S'}, TPO_NA, 0x0f}, /* 0046 */
{0x5e, 0x00, {'S', 'E'}, TPO_NA, 0x0f}, /* 0047 */
{0x5e, 0x00, {'C', 'H'}, TPO_NA, 0x0f}, /* 0048 */
{0x5e, 0x00, {'G', 'B'}, TPO_NA, 0x0f}, /* 0049 */
{0x5e, 0x00, {'A', 'L'}, TPO_NA, 0x0f}, /* 0050 */
{0x5e, 0x00, {'A', 'Z'}, TPO_NA, 0x0f}, /* 0051 */
{0x06, 0x00, {'B', 'H'}, TPO_NA, 0x0f}, /* 0052 */
{0x5e, 0x00, {'B', 'A'}, TPO_NA, 0x0f}, /* 0053 */
{0x5e, 0x00, {'B', 'G'}, TPO_NA, 0x0f}, /* 0054 */
{0x5e, 0x00, {'H', 'R'}, TPO_NA, 0x0f}, /* 0055 */
{0x3c, 0x00, {'E', 'G'}, TPO_NA, 0x0f}, /* 0056 */
{0x5e, 0x00, {'G', 'H'}, TPO_NA, 0x0f}, /* 0057 */
{0x05, 0x00, {'I', 'Q'}, TPO_NA, 0x0f}, /* 0058 */
{0x5e, 0x00, {'I', 'L'}, TPO_NA, 0x0f}, /* 0059 */
{0x05, 0x00, {'J', 'O'}, TPO_NA, 0x0f}, /* 0060 */
{0x5e, 0x00, {'K', 'Z'}, TPO_NA, 0x0f}, /* 0061 */
{0x5e, 0x00, {'K', 'E'}, TPO_NA, 0x0f}, /* 0062 */
{0x5e, 0x00, {'K', 'W'}, TPO_NA, 0x0f}, /* 0063 */
{0x5e, 0x00, {'K', 'G'}, TPO_NA, 0x0f}, /* 0064 */
{0x5e, 0x00, {'L', 'B'}, TPO_NA, 0x0f}, /* 0065 */
{0x5e, 0x00, {'L', 'S'}, TPO_NA, 0x0f}, /* 0066 */
{0x3a, 0x00, {'M', 'K'}, TPO_NA, 0x0f}, /* 0067 */
{0x3c, 0x00, {'M', 'A'}, TPO_NA, 0x0f}, /* 0068 */
{0x5e, 0x00, {'M', 'Z'}, TPO_NA, 0x0f}, /* 0069 */
{0x5e, 0x00, {'N', 'A'}, TPO_NA, 0x0f}, /* 0070 */
{0x75, 0x00, {'N', 'G'}, TPO_NA, 0x0f}, /* 0071 */
{0x5e, 0x00, {'O', 'M'}, TPO_NA, 0x0f}, /* 0072 */
{0x5e, 0x00, {'Q', 'A'}, TPO_QATAR, 0x0f}, /* 0073 */
{0x5e, 0x00, {'R', 'O'}, TPO_NA, 0x0f}, /* 0074 */
{0x09, 0x00, {'R', 'U'}, TPO_NA, 0x0f}, /* 0075 */
{0x5e, 0x00, {'S', 'A'}, TPO_NA, 0x0f}, /* 0076 */
{0x3a, 0x00, {'S', 'N'}, TPO_NA, 0x0f}, /* 0077 */
{0x5e, 0x00, {'R', 'S'}, TPO_NA, 0x0f}, /* 0078 */
{0x3a, 0x00, {'M', 'E'}, TPO_NA, 0x0f}, /* 0079 */
{0x5e, 0x00, {'Z', 'A'}, TPO_NA, 0x0f}, /* 0080 */
{0x5e, 0x00, {'T', 'R'}, TPO_NA, 0x0f}, /* 0081 */
{0x5e, 0x00, {'U', 'A'}, TPO_UKRAINE, 0x0f}, /* 0082 */
{0x5e, 0x00, {'A', 'E'}, TPO_NA, 0x0f}, /* 0083 */
{0x3a, 0x00, {'Y', 'E'}, TPO_NA, 0x0f}, /* 0084 */
{0x5e, 0x00, {'Z', 'W'}, TPO_NA, 0x0f}, /* 0085 */
{0x5e, 0x00, {'B', 'D'}, TPO_NA, 0x0f}, /* 0086 */
{0x5e, 0x00, {'K', 'H'}, TPO_NA, 0x0f}, /* 0087 */
{0x06, 0x00, {'C', 'N'}, TPO_CN, 0x0f}, /* 0088 */
{0x5e, 0x00, {'H', 'K'}, TPO_NA, 0x0f}, /* 0089 */
{0x06, 0x00, {'I', 'N'}, TPO_NA, 0x0f}, /* 0090 */
{0x5d, 0x00, {'I', 'D'}, TPO_NA, 0x0f}, /* 0091 */
{0x4b, 0x00, {'K', 'R'}, TPO_NA, 0x0f}, /* 0092 */
{0x07, 0x00, {'M', 'Y'}, TPO_NA, 0x0f}, /* 0093 */
{0x51, 0x00, {'P', 'K'}, TPO_NA, 0x0f}, /* 0094 */
{0x5e, 0x00, {'P', 'H'}, TPO_NA, 0x0f}, /* 0095 */
{0x5e, 0x00, {'S', 'G'}, TPO_NA, 0x0f}, /* 0096 */
{0x5e, 0x00, {'L', 'K'}, TPO_NA, 0x0f}, /* 0097 */
{0x76, 0x00, {'T', 'W'}, TPO_NA, 0x0f}, /* 0098 */
{0x5e, 0x00, {'T', 'H'}, TPO_NA, 0x0f}, /* 0099 */
{0x5e, 0x00, {'V', 'N'}, TPO_NA, 0x0f}, /* 0100 */
{0x03, 0x00, {'A', 'U'}, TPO_NA, 0x0f}, /* 0101 */
{0x03, 0x00, {'N', 'Z'}, TPO_NA, 0x0f}, /* 0102 */
{0x5e, 0x00, {'P', 'G'}, TPO_NA, 0x0f}, /* 0103 */
{0x2b, 0x00, {'C', 'A'}, TPO_NA, 0x0f}, /* 0104 */
{0x7d, 0x00, {'J', 'P'}, TPO_NA, 0x0f}, /* 0105 */
{0x76, 0x00, {'J', 'M'}, TPO_NA, 0x0f}, /* 0106 */
{0x76, 0x00, {'A', 'N'}, TPO_NA, 0x0f}, /* 0107 */
{0x76, 0x00, {'T', 'T'}, TPO_NA, 0x0f}, /* 0108 */
{0x04, 0x00, {'T', 'N'}, TPO_NA, 0x0f}, /* 0109 */
{0x42, 0x00, {'A', 'F'}, TPO_NA, 0x0f}, /* 0110 */
{0x00, 0x00, {'D', 'Z'}, TPO_NA, 0x0f}, /* 0111 */
{0x76, 0x00, {'A', 'S'}, TPO_NA, 0x0f}, /* 0112 */
{0x3a, 0x00, {'A', 'D'}, TPO_NA, 0x0f}, /* 0113 */
{0x5e, 0x00, {'A', 'O'}, TPO_NA, 0x0f}, /* 0114 */
{0x5e, 0x00, {'A', 'I'}, TPO_NA, 0x0f}, /* 0115 */
{0x26, 0x00, {'A', 'Q'}, TPO_NA, 0x0f}, /* 0116 */
{0x76, 0x00, {'A', 'G'}, TPO_NA, 0x0f}, /* 0117 */
{0x5e, 0x00, {'A', 'M'}, TPO_NA, 0x0f}, /* 0118 */
{0x76, 0x00, {'A', 'W'}, TPO_NA, 0x0f}, /* 0119 */
{0x76, 0x00, {'B', 'S'}, TPO_NA, 0x0f}, /* 0120 */
{0x76, 0x00, {'B', 'B'}, TPO_NA, 0x0f}, /* 0121 */
{0x08, 0x00, {'B', 'Y'}, TPO_NA, 0x07}, /* 0122 */
{0x76, 0x00, {'B', 'Z'}, TPO_NA, 0x0f}, /* 0123 */
{0x3a, 0x00, {'B', 'J'}, TPO_NA, 0x0f}, /* 0124 */
{0x76, 0x00, {'B', 'M'}, TPO_NA, 0x0f}, /* 0125 */
{0x5e, 0x00, {'B', 'T'}, TPO_NA, 0x0f}, /* 0126 */
{0x5e, 0x00, {'B', 'W'}, TPO_NA, 0x0f}, /* 0127 */
{0x5e, 0x00, {'B', 'V'}, TPO_NA, 0x0f}, /* 0128 */
{0x3a, 0x00, {'I', 'O'}, TPO_NA, 0x0f}, /* 0129 */
{0x76, 0x00, {'V', 'G'}, TPO_NA, 0x0f}, /* 0130 */
{0x06, 0x00, {'B', 'N'}, TPO_NA, 0x0f}, /* 0131 */
{0x5e, 0x00, {'B', 'F'}, TPO_NA, 0x0f}, /* 0132 */
{0x3a, 0x00, {'M', 'M'}, TPO_NA, 0x0f}, /* 0133 */
{0x3a, 0x00, {'B', 'I'}, TPO_NA, 0x0f}, /* 0134 */
{0x5e, 0x00, {'C', 'M'}, TPO_NA, 0x0f}, /* 0135 */
{0x5e, 0x00, {'C', 'V'}, TPO_NA, 0x0f}, /* 0136 */
{0x76, 0x00, {'K', 'Y'}, TPO_NA, 0x0f}, /* 0137 */
{0x3a, 0x00, {'C', 'F'}, TPO_NA, 0x0f}, /* 0138 */
{0x3a, 0x00, {'T', 'D'}, TPO_NA, 0x0f}, /* 0139 */
{0x03, 0x00, {'C', 'X'}, TPO_NA, 0x0f}, /* 0140 */
{0x3a, 0x00, {'C', 'C'}, TPO_NA, 0x0f}, /* 0141 */
{0x3a, 0x00, {'K', 'M'}, TPO_NA, 0x0f}, /* 0142 */
{0x3a, 0x00, {'C', 'G'}, TPO_NA, 0x0f}, /* 0143 */
{0x3a, 0x00, {'C', 'D'}, TPO_NA, 0x0f}, /* 0144 */
{0x5e, 0x00, {'C', 'K'}, TPO_NA, 0x0f}, /* 0145 */
{0x42, 0x00, {'C', 'I'}, TPO_NA, 0x0f}, /* 0146 */
{0x3a, 0x00, {'D', 'J'}, TPO_NA, 0x0f}, /* 0147 */
{0x76, 0x00, {'D', 'M'}, TPO_NA, 0x0f}, /* 0148 */
{0x5e, 0x00, {'G', 'Q'}, TPO_NA, 0x0f}, /* 0149 */
{0x3a, 0x00, {'E', 'R'}, TPO_NA, 0x0f}, /* 0150 */
{0x3a, 0x00, {'E', 'T'}, TPO_NA, 0x0f}, /* 0151 */
{0x3a, 0x00, {'F', 'K'}, TPO_NA, 0x0f}, /* 0152 */
{0x3a, 0x00, {'F', 'O'}, TPO_NA, 0x0f}, /* 0153 */
{0x76, 0x00, {'F', 'J'}, TPO_NA, 0x0f}, /* 0154 */
{0x3a, 0x00, {'G', 'F'}, TPO_NA, 0x0f}, /* 0155 */
{0x3a, 0x00, {'P', 'F'}, TPO_NA, 0x0f}, /* 0156 */
{0x3a, 0x00, {'T', 'F'}, TPO_NA, 0x0f}, /* 0157 */
{0x5e, 0x00, {'G', 'A'}, TPO_NA, 0x0f}, /* 0158 */
{0x3a, 0x00, {'G', 'M'}, TPO_NA, 0x0f}, /* 0159 */
{0x5e, 0x00, {'G', 'E'}, TPO_NA, 0x0f}, /* 0160 */
{0x3a, 0x00, {'G', 'I'}, TPO_NA, 0x0f}, /* 0161 */
{0x5e, 0x00, {'G', 'L'}, TPO_NA, 0x0f}, /* 0162 */
{0x76, 0x00, {'G', 'D'}, TPO_NA, 0x0f}, /* 0163 */
{0x3a, 0x00, {'G', 'P'}, TPO_NA, 0x0f}, /* 0164 */
{0x76, 0x00, {'G', 'U'}, TPO_NA, 0x0f}, /* 0165 */
{0x5e, 0x00, {'G', 'G'}, TPO_NA, 0x0f}, /* 0166 */
{0x3a, 0x00, {'G', 'N'}, TPO_NA, 0x0f}, /* 0167 */
{0x3a, 0x00, {'G', 'W'}, TPO_NA, 0x0f}, /* 0168 */
{0x44, 0x00, {'G', 'Y'}, TPO_NA, 0x0f}, /* 0169 */
{0x76, 0x00, {'H', 'T'}, TPO_NA, 0x07}, /* 0170 */
{0x03, 0x00, {'H', 'M'}, TPO_NA, 0x0f}, /* 0171 */
{0x3a, 0x00, {'V', 'A'}, TPO_NA, 0x0f}, /* 0172 */
{0x3a, 0x00, {'I', 'M'}, TPO_NA, 0x0f}, /* 0173 */
{0x3a, 0x00, {'J', 'E'}, TPO_NA, 0x0f}, /* 0174 */
{0x5e, 0x00, {'K', 'I'}, TPO_NA, 0x0f}, /* 0175 */
{0x5e, 0x00, {'L', 'A'}, TPO_NA, 0x0f}, /* 0176 */
{0x5e, 0x00, {'L', 'R'}, TPO_NA, 0x0f}, /* 0177 */
{0x5e, 0x00, {'L', 'Y'}, TPO_NA, 0x0f}, /* 0178 */
{0x5e, 0x00, {'M', 'O'}, TPO_NA, 0x0f}, /* 0179 */
{0x5e, 0x00, {'M', 'G'}, TPO_NA, 0x0f}, /* 0180 */
{0x5e, 0x00, {'M', 'W'}, TPO_NA, 0x0f}, /* 0181 */
{0x3c, 0x00, {'M', 'V'}, TPO_NA, 0x0f}, /* 0182 */
{0x5e, 0x00, {'M', 'L'}, TPO_NA, 0x0f}, /* 0183 */
{0x76, 0x00, {'M', 'H'}, TPO_NA, 0x0f}, /* 0184 */
{0x3a, 0x00, {'M', 'Q'}, TPO_NA, 0x0f}, /* 0185 */
{0x5e, 0x00, {'M', 'R'}, TPO_NA, 0x0f}, /* 0186 */
{0x5e, 0x00, {'M', 'U'}, TPO_NA, 0x0f}, /* 0187 */
{0x5e, 0x00, {'Y', 'T'}, TPO_NA, 0x0f}, /* 0188 */
{0x76, 0x00, {'F', 'M'}, TPO_NA, 0x0f}, /* 0189 */
{0x5e, 0x00, {'M', 'D'}, TPO_NA, 0x0f}, /* 0190 */
{0x5e, 0x00, {'M', 'N'}, TPO_NA, 0x0f}, /* 0191 */
{0x3a, 0x00, {'M', 'S'}, TPO_NA, 0x0f}, /* 0192 */
{0x3a, 0x00, {'N', 'R'}, TPO_NA, 0x0f}, /* 0193 */
{0x06, 0x00, {'N', 'P'}, TPO_NA, 0x0f}, /* 0194 */
{0x3a, 0x00, {'N', 'C'}, TPO_NA, 0x0f}, /* 0195 */
{0x5e, 0x00, {'N', 'E'}, TPO_NA, 0x0f}, /* 0196 */
{0x03, 0x00, {'N', 'U'}, TPO_NA, 0x0f}, /* 0197 */
{0x03, 0x00, {'N', 'F'}, TPO_NA, 0x0f}, /* 0198 */
{0x76, 0x00, {'M', 'P'}, TPO_NA, 0x0f}, /* 0199 */
{0x76, 0x00, {'P', 'W'}, TPO_NA, 0x0f}, /* 0200 */
{0x3a, 0x00, {'R', 'E'}, TPO_NA, 0x0f}, /* 0201 */
{0x5e, 0x00, {'R', 'W'}, TPO_NA, 0x0f}, /* 0202 */
{0x3a, 0x00, {'S', 'H'}, TPO_NA, 0x0f}, /* 0203 */
{0x76, 0x00, {'K', 'N'}, TPO_NA, 0x0f}, /* 0204 */
{0x76, 0x00, {'L', 'C'}, TPO_NA, 0x0f}, /* 0205 */
{0x76, 0x00, {'M', 'F'}, TPO_NA, 0x0f}, /* 0206 */
{0x76, 0x00, {'S', 'X'}, TPO_NA, 0x0f}, /* 0207 */
{0x3a, 0x00, {'P', 'M'}, TPO_NA, 0x0f}, /* 0208 */
{0x76, 0x00, {'V', 'C'}, TPO_NA, 0x0f}, /* 0209 */
{0x76, 0x00, {'W', 'S'}, TPO_NA, 0x0f}, /* 0210 */
{0x3a, 0x00, {'S', 'M'}, TPO_NA, 0x0f}, /* 0211 */
{0x76, 0x00, {'S', 'T'}, TPO_NA, 0x0f}, /* 0212 */
{0x76, 0x00, {'S', 'C'}, TPO_NA, 0x0f}, /* 0213 */
{0x5e, 0x00, {'S', 'L'}, TPO_NA, 0x0f}, /* 0214 */
{0x3a, 0x00, {'S', 'B'}, TPO_NA, 0x0f}, /* 0215 */
{0x3a, 0x00, {'S', 'O'}, TPO_NA, 0x0f}, /* 0216 */
{0x3a, 0x00, {'G', 'S'}, TPO_NA, 0x0f}, /* 0217 */
{0x74, 0x00, {'S', 'R'}, TPO_NA, 0x0f}, /* 0218 */
{0x3a, 0x00, {'S', 'J'}, TPO_NA, 0x0f}, /* 0219 */
{0x5e, 0x00, {'S', 'Z'}, TPO_NA, 0x0f}, /* 0220 */
{0x5e, 0x00, {'T', 'J'}, TPO_NA, 0x0f}, /* 0221 */
{0x5e, 0x00, {'T', 'Z'}, TPO_NA, 0x0f}, /* 0222 */
{0x5e, 0x00, {'T', 'G'}, TPO_NA, 0x0f}, /* 0223 */
{0x03, 0x00, {'T', 'K'}, TPO_NA, 0x0f}, /* 0224 */
{0x3a, 0x00, {'T', 'O'}, TPO_NA, 0x0f}, /* 0225 */
{0x3a, 0x00, {'T', 'M'}, TPO_NA, 0x0f}, /* 0226 */
{0x3a, 0x00, {'T', 'C'}, TPO_NA, 0x0f}, /* 0227 */
{0x21, 0x00, {'T', 'V'}, TPO_NA, 0x01}, /* 0228 */
{0x3a, 0x00, {'U', 'G'}, TPO_NA, 0x0f}, /* 0229 */
{0x76, 0x00, {'V', 'I'}, TPO_NA, 0x0f}, /* 0230 */
{0x3c, 0x00, {'U', 'Z'}, TPO_NA, 0x0f}, /* 0231 */
{0x26, 0x00, {'V', 'U'}, TPO_NA, 0x0f}, /* 0232 */
{0x3a, 0x00, {'W', 'F'}, TPO_NA, 0x0f}, /* 0233 */
{0x3c, 0x00, {'E', 'H'}, TPO_NA, 0x0f}, /* 0234 */
{0x5e, 0x00, {'Z', 'M'}, TPO_NA, 0x0f}, /* 0235 */
{0x3a, 0x00, {'I', 'R'}, TPO_NA, 0x01}, /* 0236 */
{0x5e, 0x00, {'P', 'S'}, TPO_NA, 0x0f}, /* 0237 */
};
|
2301_81045437/rtl8852be
|
phl/phl_country.c
|
C
|
agpl-3.0
| 13,870
|
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_COUNTRY_H_
#define _PHL_COUNTRY_H_
#define REGULATION_COUNTRY_VERSION 31
#define MAX_COUNTRY_NUM 238
enum TP_OVERWRITE {
TPO_CHILE = 0,
TPO_QATAR = 1,
TPO_UKRAINE = 2,
TPO_CN = 3,
TPO_NA = 4
};
#define COUNTRY_CODE_LEN 2
struct country_domain_mapping {
u8 domain_code;
u8 domain_code_6g;
char char2[COUNTRY_CODE_LEN];
u8 tpo; /* tx power overwrite */
/*
* bit0: accept 11bgn
* bit1: accept 11a
* bit2: accept 11ac
* bit3: accept 11ax
*/
u8 support;
};
#endif /* _PHL_COUNTRY_H_ */
|
2301_81045437/rtl8852be
|
phl/phl_country.h
|
C
|
agpl-3.0
| 1,220
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_DEBUG_C_
#include "phl_headers.h"
#ifdef CONFIG_RTW_DEBUG
u32 phl_log_components = COMP_PHL_DBG |
COMP_PHL_XMIT |
COMP_PHL_WOW |
/* COMP_PHL_CMDDISP |*/
COMP_PHL_RECV |
COMP_PHL_MAC |
COMP_PHL_PS | 0;
u8 phl_log_level = _PHL_ERR_;
struct dbg_mem_ctx debug_memory_ctx;
void debug_dump_mac_address(u8 *mac_addr)
{
if (mac_addr == NULL) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[dump mac addr] mac_addr is NULL\n");
return;
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[MAC ADDRESS]\n");
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%02X-%02X-%02X-%02X-%02X-%02X\n",
mac_addr[0], mac_addr[1], mac_addr[2],
mac_addr[3], mac_addr[4], mac_addr[5]);
}
void debug_dump_data(u8 *buf, u32 buf_len, const char *prefix)
{
u32 i;
if (buf == NULL) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "[debug dump] buf is NULL\n");
return;
}
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "[debug dump] %s\n", prefix);
for (i = 0; i < buf_len; i++) {
if (!(i % 8))
PHL_DATA(COMP_PHL_DBG, _PHL_DEBUG_, "\n");
PHL_DATA(COMP_PHL_DBG, _PHL_DEBUG_, "%02X ", buf[i]);
}
PHL_DATA(COMP_PHL_DBG, _PHL_DEBUG_, "\n");
}
void rt_alloc_dbg_buf(void *phl, u8 *buf_ptr, u32 buf_size,
const u8 *file_name, u32 line_num, const u8 *func_name)
{
_os_list *list = &debug_memory_ctx.alloc_buf_list;
_os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock;
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
struct dbg_alloc_buf *dbg_buf = NULL;
u32 name_size = 0;
FUNCIN();
dbg_buf = _os_mem_alloc(phl_to_drvpriv(phl_info), sizeof(*dbg_buf));
dbg_buf->buf_ptr = buf_ptr;
dbg_buf->buf_size = buf_size;
name_size = (_os_strlen((u8 *)file_name) > DEBUG_MAX_NAME_LEN) ?
DEBUG_MAX_NAME_LEN : _os_strlen((u8 *)file_name);
_os_mem_cpy(phl_to_drvpriv(phl_info), dbg_buf->file_name, (u8 *)file_name, name_size);
dbg_buf->line_num = line_num;
name_size = (_os_strlen((u8 *)func_name) > DEBUG_MAX_NAME_LEN) ?
DEBUG_MAX_NAME_LEN : _os_strlen((u8 *)func_name);
_os_mem_cpy(phl_to_drvpriv(phl_info), dbg_buf->func_name, (u8 *)func_name, name_size);
_os_spinlock(phl_to_drvpriv(phl_info), lock, _bh, NULL);
list_add_tail(&(dbg_buf->list), list);
debug_memory_ctx.alloc_buf_cnt++;
_os_spinunlock(phl_to_drvpriv(phl_info), lock, _bh, NULL);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Allocate Memory: %p, size: %d, File: %s, Line: %d, Function: %s\n",
dbg_buf->buf_ptr, dbg_buf->buf_size, dbg_buf->file_name,
dbg_buf->line_num, dbg_buf->func_name);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Current allocated buffer count: %d",
debug_memory_ctx.alloc_buf_cnt);
FUNCOUT();
}
void rt_free_dbg_buf(void *phl, u8 *buf_ptr, u32 buf_size,
const u8 *file_name, u32 line_num, const u8 *func_name)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
_os_list *list = &debug_memory_ctx.alloc_buf_list;
_os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock;
struct dbg_alloc_buf *dbg_buf = NULL , *t;
u8 found = false;
FUNCIN();
_os_spinlock(phl_to_drvpriv(phl_info), lock, _bh, NULL);
phl_list_for_loop_safe(dbg_buf, t, struct dbg_alloc_buf, list, list) {
if (dbg_buf->buf_ptr == buf_ptr) {
list_del(&dbg_buf->list);
found = true;
break;
}
}
_os_spinunlock(phl_to_drvpriv(phl_info), lock, _bh, NULL);
if (true == found) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Free Memory: %p, size: %d, File: %s, Line: %d, Function: %s\n",
dbg_buf->buf_ptr, dbg_buf->buf_size, file_name,
line_num, func_name);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Current allocated buffer count: %d",
debug_memory_ctx.alloc_buf_cnt);
_os_mem_free(phl_to_drvpriv(phl_info), dbg_buf, sizeof(*dbg_buf));
debug_memory_ctx.alloc_buf_cnt--;
} else {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"WARNING, can not find allocated buffer in list\n");
}
FUNCOUT();
}
void rt_mem_dbg_init(void *phl)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
_os_list *list = &debug_memory_ctx.alloc_buf_list;
_os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock;
FUNCIN();
debug_memory_ctx.alloc_buf_cnt = 0;
INIT_LIST_HEAD(list);
_os_spinlock_init(phl_to_drvpriv(phl_info), lock);
FUNCOUT();
}
void rt_mem_dbg_deinit(void *phl)
{
struct phl_info_t *phl_info = (struct phl_info_t *)phl;
_os_list *list = &debug_memory_ctx.alloc_buf_list;
_os_lock *lock = &debug_memory_ctx.alloc_buf_list_lock;
struct dbg_alloc_buf *dbg_buf = NULL;
FUNCIN();
while (true != list_empty(list) ||
0 != debug_memory_ctx.alloc_buf_cnt) {
_os_spinlock(phl_to_drvpriv(phl_info), lock, _bh, NULL);
dbg_buf = list_first_entry(list, struct dbg_alloc_buf, list);
list_del(&dbg_buf->list);
_os_spinunlock(phl_to_drvpriv(phl_info), lock, _bh, NULL);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "FOUND non-freed Memory: %p, size: %d, File: %s, Line: %d, Function: %s\n",
dbg_buf->buf_ptr, dbg_buf->buf_size,
dbg_buf->file_name, dbg_buf->line_num,
dbg_buf->func_name);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Current allocated buffer count: %d",
debug_memory_ctx.alloc_buf_cnt);
_os_mem_free(phl_to_drvpriv(phl_info), dbg_buf, sizeof(*dbg_buf));
debug_memory_ctx.alloc_buf_cnt--;
}
_os_spinlock_init(phl_to_drvpriv(phl_info), lock);
FUNCOUT();
}
void phl_dbg_show_log_comp(u8 comp_bit)
{
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[DBG] phl_log_components = 0x%x \n", phl_log_components);
}
void phl_dbg_set_log_comp(u8 comp_bit)
{
phl_log_components |= BIT(comp_bit);
}
void phl_dbg_clear_log_comp(u8 comp_bit)
{
phl_log_components &= (~BIT(comp_bit));
}
u32 rtw_phl_dbg_ctrl_comp(u8 ctrl, u8 comp_bit)
{
if (1 == ctrl) {
phl_dbg_set_log_comp(comp_bit);
} else if (2 == ctrl) {
phl_dbg_clear_log_comp(comp_bit);
}
phl_dbg_show_log_comp(comp_bit);
return phl_log_components;
}
#endif /* #ifdef CONFIG_PHL_DEBUG */
|
2301_81045437/rtl8852be
|
phl/phl_debug.c
|
C
|
agpl-3.0
| 6,427
|