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/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include <linux/ctype.h> /* tolower() */
#include <drv_types.h>
#include "rtw_proc.h"
#include <rtw_btc.h>
#include "_hal_rate.h"
#ifdef CONFIG_PROC_DEBUG
static struct proc_dir_entry *rtw_proc = NULL;
inline struct proc_dir_entry *get_rtw_drv_proc(void)
{
return rtw_proc;
}
#define RTW_PROC_NAME DRV_NAME
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
#define file_inode(file) ((file)->f_dentry->d_inode)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
#define PDE_DATA(inode) PDE((inode))->data
#define proc_get_parent_data(inode) PDE((inode))->parent->data
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
#define get_proc_net proc_net
#else
#define get_proc_net init_net.proc_net
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
int single_open_size(struct file *file, int (*show)(struct seq_file *, void *),
void *data, size_t size)
{
char *buf = kmalloc(size, GFP_KERNEL);
int ret;
if (!buf)
return -ENOMEM;
ret = single_open(file, show, data);
if (ret) {
kfree(buf);
return ret;
}
((struct seq_file *)file->private_data)->buf = buf;
((struct seq_file *)file->private_data)->size = size;
return 0;
}
#endif
inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data)
{
struct proc_dir_entry *entry;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
entry = proc_mkdir_data(name, S_IRUGO | S_IXUGO, parent, data);
#else
/* entry = proc_mkdir_mode(name, S_IRUGO|S_IXUGO, parent); */
entry = proc_mkdir(name, parent);
if (entry)
entry->data = data;
#endif
return entry;
}
inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent,
const struct rtw_proc_ops *fops, void * data)
{
struct proc_dir_entry *entry;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
entry = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUGO, parent, fops, data);
#else
entry = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUGO, parent);
if (entry) {
entry->data = data;
entry->proc_fops = fops;
}
#endif
return entry;
}
static int proc_get_dummy(struct seq_file *m, void *v)
{
return 0;
}
static int proc_get_drv_version(struct seq_file *m, void *v)
{
dump_drv_version(m);
return 0;
}
static int proc_get_log_level(struct seq_file *m, void *v)
{
dump_log_level(m);
return 0;
}
static int proc_get_drv_cfg(struct seq_file *m, void *v)
{
dump_drv_cfg(m);
return 0;
}
static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
char tmp[32];
int log_level;
if (count < 1)
return -EINVAL;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
#ifdef CONFIG_RTW_DEBUG
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d ", &log_level);
if (num == 1 &&
log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) {
rtw_drv_log_level = log_level;
printk("rtw_drv_log_level:%d\n", rtw_drv_log_level);
}
} else
return -EFAULT;
#else
printk("CONFIG_RTW_DEBUG is disabled\n");
#endif
return count;
}
#ifdef DBG_MEM_ALLOC
static int proc_get_mstat(struct seq_file *m, void *v)
{
rtw_mstat_dump(m);
return 0;
}
#endif /* DBG_MEM_ALLOC */
static bool regd_info;
static int proc_get_country_chplan_map(struct seq_file *m, void *v)
{
dump_country_chplan_map(m, regd_info);
return 0;
}
static ssize_t proc_set_country_chplan_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
char tmp[32];
int regd_info_val;
if (count < 1)
return -EINVAL;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d", ®d_info_val);
if (num >= 1)
regd_info = regd_info_val ? 1 : 0;
} else
return -EFAULT;
return count;
}
static int proc_get_country_list(struct seq_file *m, void *v)
{
dump_country_list(m);
return 0;
}
static int proc_get_chplan_id_list(struct seq_file *m, void *v)
{
dump_chplan_id_list(m);
return 0;
}
static int proc_get_chplan_country_list(struct seq_file *m, void *v)
{
dump_chplan_country_list(m);
return 0;
}
#if CONFIG_IEEE80211_BAND_6GHZ
static int proc_get_chplan_6g_id_list(struct seq_file *m, void *v)
{
dump_chplan_6g_id_list(m);
return 0;
}
static int proc_get_chplan_6g_country_list(struct seq_file *m, void *v)
{
dump_chplan_6g_country_list(m);
return 0;
}
#endif
#ifdef CONFIG_RTW_DEBUG
static int proc_get_chplan_test(struct seq_file *m, void *v)
{
dump_chplan_test(m);
return 0;
}
#endif
static int proc_get_chplan_ver(struct seq_file *m, void *v)
{
dump_chplan_ver(m);
return 0;
}
static int proc_get_global_op_class(struct seq_file *m, void *v)
{
dump_global_op_class(m);
return 0;
}
extern void rtw_hal_get_version(char *str, u32 len);
static int proc_get_hal_info(struct seq_file *m, void *v)
{
char ver[30] = {0};
rtw_hal_get_version(ver, 30);
RTW_PRINT_SEL(m, "version: %s\n", ver);
return 0;
}
/*
* rtw_drv_proc:
* init/deinit when register/unregister driver
*/
const struct rtw_proc_hdl drv_proc_hdls[] = {
RTW_PROC_HDL_SSEQ("ver_info", proc_get_drv_version, NULL),
RTW_PROC_HDL_SSEQ("log_level", proc_get_log_level, proc_set_log_level),
RTW_PROC_HDL_SSEQ("drv_cfg", proc_get_drv_cfg, NULL),
#ifdef DBG_MEM_ALLOC
RTW_PROC_HDL_SSEQ("mstat", proc_get_mstat, NULL),
#endif /* DBG_MEM_ALLOC */
RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, proc_set_country_chplan_map),
RTW_PROC_HDL_SSEQ("country_list", proc_get_country_list, NULL),
RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL),
RTW_PROC_HDL_SSEQ("chplan_country_list", proc_get_chplan_country_list, NULL),
#if CONFIG_IEEE80211_BAND_6GHZ
RTW_PROC_HDL_SSEQ("chplan_6g_id_list", proc_get_chplan_6g_id_list, NULL),
RTW_PROC_HDL_SSEQ("chplan_6g_country_list", proc_get_chplan_6g_country_list, NULL),
#endif
#ifdef CONFIG_RTW_DEBUG
RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL),
#endif
RTW_PROC_HDL_SSEQ("chplan_ver", proc_get_chplan_ver, NULL),
RTW_PROC_HDL_SSEQ("global_op_class", proc_get_global_op_class, NULL),
RTW_PROC_HDL_SSEQ("hal_info", proc_get_hal_info, NULL),
};
const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl);
static int rtw_drv_proc_open(struct inode *inode, struct file *file)
{
/* struct net_device *dev = proc_get_parent_data(inode); */
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
ssize_t index = (ssize_t)PDE_DATA(inode);
#else
ssize_t index = (ssize_t)pde_data(inode);
#endif
const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
void *private = NULL;
if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
int res = seq_open(file, hdl->u.seq_op);
if (res == 0)
((struct seq_file *)file->private_data)->private = private;
return res;
} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
return single_open(file, show, private);
} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
return single_open_size(file, show, private, hdl->u.sz.size);
#else
return single_open(file, show, private);
#endif
} else {
return -EROFS;
}
}
static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
#else
ssize_t index = (ssize_t)pde_data(file_inode(file));
#endif
const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
if (write)
return write(file, buffer, count, pos, NULL);
return -EROFS;
}
static const struct rtw_proc_ops rtw_drv_proc_seq_fops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
.proc_open = rtw_drv_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = seq_release,
.proc_write = rtw_drv_proc_write,
#else
.owner = THIS_MODULE,
.open = rtw_drv_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
.write = rtw_drv_proc_write,
#endif
};
static const struct rtw_proc_ops rtw_drv_proc_sseq_fops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
.proc_open = rtw_drv_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = rtw_drv_proc_write,
#else
.owner = THIS_MODULE,
.open = rtw_drv_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.write = rtw_drv_proc_write,
#endif
};
int rtw_drv_proc_init(void)
{
int ret = _FAIL;
ssize_t i;
struct proc_dir_entry *entry = NULL;
if (rtw_proc != NULL) {
rtw_warn_on(1);
goto exit;
}
rtw_proc = rtw_proc_create_dir(RTW_PROC_NAME, get_proc_net, NULL);
if (rtw_proc == NULL) {
rtw_warn_on(1);
goto exit;
}
for (i = 0; i < drv_proc_hdls_num; i++) {
if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i);
else if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i);
else
entry = NULL;
if (!entry) {
rtw_warn_on(1);
goto exit;
}
}
ret = _SUCCESS;
exit:
return ret;
}
void rtw_drv_proc_deinit(void)
{
int i;
if (rtw_proc == NULL)
return;
for (i = 0; i < drv_proc_hdls_num; i++)
remove_proc_entry(drv_proc_hdls[i].name, rtw_proc);
remove_proc_entry(RTW_PROC_NAME, get_proc_net);
rtw_proc = NULL;
}
#ifndef RTW_SEQ_FILE_TEST
#define RTW_SEQ_FILE_TEST 0
#endif
#if RTW_SEQ_FILE_TEST
#define RTW_SEQ_FILE_TEST_SHOW_LIMIT 300
static void *proc_start_seq_file_test(struct seq_file *m, loff_t *pos)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
RTW_PRINT(FUNC_ADPT_FMT" pos:%llu, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
return NULL;
}
RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
return pos;
}
void proc_stop_seq_file_test(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
}
void *proc_next_seq_file_test(struct seq_file *m, void *v, loff_t *pos)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
(*pos)++;
if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
RTW_PRINT(FUNC_ADPT_FMT" pos:%lld, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
return NULL;
}
RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
return pos;
}
static int proc_get_seq_file_test(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
u32 pos = *((loff_t *)(v));
RTW_PRINT(FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
RTW_PRINT_SEL(m, FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
return 0;
}
struct seq_operations seq_file_test = {
.start = proc_start_seq_file_test,
.stop = proc_stop_seq_file_test,
.next = proc_next_seq_file_test,
.show = proc_get_seq_file_test,
};
#endif /* RTW_SEQ_FILE_TEST */
#ifdef CONFIG_SDIO_HCI
#include "rtw_sdio.h"
#define CCCR_LEN 0x100
static void sd_f0_reg_dump(void *sel, struct _ADAPTER *a)
{
struct dvobj_priv *d = adapter_to_dvobj(a);
u8 *cccr = NULL, *ptr, val;
u8 ret;
int i;
cccr = rtw_vmalloc(CCCR_LEN);
if (cccr) {
ret = rtw_sdio_f0_read(d, 0, cccr, CCCR_LEN);
if (ret == _FAIL) {
RTW_PRINT_SEL(sel, "Fail to read F0 register!");
goto exit;
}
} else {
RTW_WARN(FUNC_ADPT_FMT ": alloc memory FAIL!\n",
FUNC_ADPT_ARG(a));
ptr = &val;
}
for (i = 0x0; i < CCCR_LEN; i++) {
if (cccr) {
ptr = &cccr[i];
} else {
ret = rtw_sdio_f0_read(d, i, &val, 1);
if (ret == _FAIL) {
RTW_ERR(FUNC_ADPT_FMT ": Fail to read F0 "
"register 0x%02x!\n",
FUNC_ADPT_ARG(a), i);
RTW_PRINT_SEL(sel, "... error!\n");
goto exit;
}
}
if (i % 16 == 0)
RTW_PRINT_SEL(sel, "0x%02x ", i);
_RTW_PRINT_SEL(sel, "%02x ", *ptr);
if (i % 16 == 15)
_RTW_PRINT_SEL(sel, "\n");
else if (i % 8 == 7)
_RTW_PRINT_SEL(sel, "\t");
}
exit:
if (cccr)
rtw_vmfree(cccr, CCCR_LEN);
}
static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
// struct dvobj_priv *d = adapter_to_dvobj(adapter);
// rtw_hal_sd_f0_reg_dump(m, GET_PHL_INFO(d));
sd_f0_reg_dump(m, adapter);
return 0;
}
static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *d = adapter_to_dvobj(adapter);
rtw_hal_sdio_local_reg_dump(m, GET_PHL_INFO(d));
return 0;
}
static int proc_get_sdio_card_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_sdio_card_info(m, adapter_to_dvobj(adapter));
return 0;
}
#ifdef DBG_SDIO
static int proc_get_sdio_dbg(struct seq_file *m, void *v)
{
struct net_device *dev;
_adapter *a;
struct dvobj_priv *d;
struct sdio_data *sdio;
dev = m->private;
a = (_adapter *)rtw_netdev_priv(dev);
d = adapter_to_dvobj(a);
sdio = dvobj_to_sdio(d);
dump_sdio_card_info(m, d);
RTW_PRINT_SEL(m, "CMD52 error cnt: %d\n", sdio->cmd52_err_cnt);
RTW_PRINT_SEL(m, "CMD53 error cnt: %d\n", sdio->cmd53_err_cnt);
#if (DBG_SDIO >= 3)
RTW_PRINT_SEL(m, "dbg: %s\n", sdio->dbg_enable?"enable":"disable");
RTW_PRINT_SEL(m, "err_stop: %s\n", sdio->err_stop?"enable":"disable");
RTW_PRINT_SEL(m, "err_test: %s\n", sdio->err_test?"enable":"disable");
RTW_PRINT_SEL(m, "err_test_triggered: %s\n",
sdio->err_test_triggered?"yes":"no");
#endif /* DBG_SDIO >= 3 */
#if (DBG_SDIO >= 2)
RTW_PRINT_SEL(m, "I/O error dump mark: %d\n", sdio->reg_dump_mark);
if (sdio->reg_dump_mark) {
if (sdio->dbg_msg)
RTW_PRINT_SEL(m, "debug messages: %s\n", sdio->dbg_msg);
if (sdio->reg_mac)
RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "MAC register:",
_TRUE, sdio->reg_mac, 0x800);
if (sdio->reg_mac_ext)
RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "MAC EXT register:",
_TRUE, sdio->reg_mac_ext, 0x800);
if (sdio->reg_local)
RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "SDIO Local register:",
_TRUE, sdio->reg_local, 0x100);
if (sdio->reg_cia)
RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "SDIO CIA register:",
_TRUE, sdio->reg_cia, 0x200);
}
#endif /* DBG_SDIO >= 2 */
return 0;
}
#if (DBG_SDIO >= 2)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
#define strnicmp strncasecmp
#endif /* Linux kernel >= 4.0.0 */
void rtw_sdio_dbg_reg_free(struct dvobj_priv *d);
#endif /* DBG_SDIO >= 2 */
ssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer,
size_t count, loff_t *pos, void *data)
{
#if (DBG_SDIO >= 2)
struct net_device *dev = data;
struct dvobj_priv *d;
_adapter *a;
struct sdio_data *sdio;
char tmp[32], cmd[32] = {0};
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
a = (_adapter *)rtw_netdev_priv(dev);
d = adapter_to_dvobj(a);
sdio = dvobj_to_sdio(d);
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%s", cmd);
if (num >= 1) {
if (strnicmp(cmd, "reg_reset", 10) == 0) {
sdio->reg_dump_mark = 0;
goto exit;
}
if (strnicmp(cmd, "reg_free", 9) == 0) {
rtw_sdio_dbg_reg_free(d);
sdio->reg_dump_mark = 0;
goto exit;
}
#if (DBG_SDIO >= 3)
if (strnicmp(cmd, "dbg_enable", 11) == 0) {
sdio->dbg_enable = 1;
goto exit;
}
if (strnicmp(cmd, "dbg_disable", 12) == 0) {
sdio->dbg_enable = 0;
goto exit;
}
if (strnicmp(cmd, "err_stop", 9) == 0) {
sdio->err_stop = 1;
goto exit;
}
if (strnicmp(cmd, "err_stop_disable", 16) == 0) {
sdio->err_stop = 0;
goto exit;
}
if (strnicmp(cmd, "err_test", 9) == 0) {
sdio->err_test_triggered = 0;
sdio->err_test = 1;
goto exit;
}
#endif /* DBG_SDIO >= 3 */
}
return -EINVAL;
}
exit:
#endif /* DBG_SDIO >= 2 */
return count;
}
#endif /* DBG_SDIO */
#endif /* CONFIG_SDIO_HCI */
static int proc_get_mac_reg_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
rtw_phl_mac_reg_dump(m, GET_PHL_INFO(dvobj));
return 0;
}
static int proc_get_bb_reg_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
rtw_phl_bb_reg_dump(m, GET_PHL_INFO(dvobj));
return 0;
}
static int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
rtw_phl_bb_reg_dump_ex(m, GET_PHL_INFO(dvobj));
return 0;
}
static int proc_get_rf_reg_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
rtw_phl_rf_reg_dump(m, GET_PHL_INFO(dvobj));
return 0;
}
#if 0
int proc_get_led_config(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_led_config(m, adapter);
return 0;
}
ssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u8 strategy;
u8 iface_en_mask;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %hhx", &strategy, &iface_en_mask);
if (num >= 1)
rtw_led_set_strategy(adapter, strategy);
if (num >= 2)
rtw_led_set_iface_en_mask(adapter, iface_en_mask);
}
return count;
}
#endif /* CONFIG_RTW_LED */
#ifdef CONFIG_AP_MODE
int proc_get_aid_status(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_aid_status(m, adapter);
return 0;
}
ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct sta_priv *stapriv = &adapter->stapriv;
char tmp[32];
u8 rr;
u16 started_aid;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %hu", &rr, &started_aid);
if (num >= 1)
stapriv->rr_aid = rr ? 1 : 0;
if (num >= 2) {
started_aid = started_aid % (stapriv->max_aid + 1);
stapriv->started_aid = started_aid ? started_aid : 1;
}
}
return count;
}
#if CONFIG_RTW_AP_DATA_BMC_TO_UC
static int proc_get_ap_b2u_flags(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
if (MLME_IS_AP(adapter))
dump_ap_b2u_flags(m, adapter);
return 0;
}
static ssize_t proc_set_ap_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
u8 src, fwd;
int num = sscanf(tmp, "%hhx %hhx", &src, &fwd);
if (num >= 1)
adapter->b2u_flags_ap_src = src;
if (num >= 2)
adapter->b2u_flags_ap_fwd = fwd;
}
return count;
}
#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
#endif /* CONFIG_AP_MODE */
static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_tx_rate_bmp(m, adapter_to_dvobj(adapter));
return 0;
}
static int proc_get_dump_adapters_status(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_adapters_status(m, adapter_to_dvobj(adapter));
return 0;
}
#ifdef CONFIG_RTW_CUSTOMER_STR
static int proc_get_customer_str(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
u8 cstr[RTW_CUSTOMER_STR_LEN];
rtw_ps_deny(adapter, PS_DENY_IOCTL);
if (rtw_pwr_wakeup(adapter) == _FAIL)
goto exit;
if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS)
goto exit;
RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr));
exit:
rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
return 0;
}
#endif /* CONFIG_RTW_CUSTOMER_STR */
#ifdef CONFIG_SCAN_BACKOP
static int proc_get_backop_flags_sta(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext));
return 0;
}
static ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
char tmp[32];
u8 flags;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhx", &flags);
if (num == 1)
mlmeext_assign_scan_backop_flags_sta(mlmeext, flags);
}
return count;
}
#ifdef CONFIG_AP_MODE
static int proc_get_backop_flags_ap(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext));
return 0;
}
static ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
char tmp[32];
u8 flags;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhx", &flags);
if (num == 1)
mlmeext_assign_scan_backop_flags_ap(mlmeext, flags);
}
return count;
}
#endif /* CONFIG_AP_MODE */
#ifdef CONFIG_RTW_MESH
static int proc_get_backop_flags_mesh(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_mesh(mlmeext));
return 0;
}
static ssize_t proc_set_backop_flags_mesh(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
char tmp[32];
u8 flags;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhx", &flags);
if (num == 1)
mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags);
}
return count;
}
#endif /* CONFIG_RTW_MESH */
#endif /* CONFIG_SCAN_BACKOP */
#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)
static int proc_get_lps_pg_debug(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
struct dm_struct *dm = adapter_to_phydm(adapter);
rtw_run_in_thread_cmd(adapter, ((void *)(odm_lps_pg_debug_8822c)), dm);
return 0;
}
#endif
/* gpio setting */
#ifdef CONFIG_GPIO_API
static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int num = 0, gpio_pin = 0, gpio_mode = 0; /* gpio_mode:0 input 1:output; */
if (count < 2)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%d %d", &gpio_pin, &gpio_mode);
RTW_INFO("num=%d gpio_pin=%d mode=%d\n", num, gpio_pin, gpio_mode);
padapter->pre_gpio_pin = gpio_pin;
if (gpio_mode == 0 || gpio_mode == 1)
rtw_hal_config_gpio(padapter, gpio_pin, gpio_mode);
}
return count;
}
static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int num = 0, gpio_pin = 0, pin_mode = 0; /* pin_mode: 1 high 0:low */
if (count < 2)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%d %d", &gpio_pin, &pin_mode);
RTW_INFO("num=%d gpio_pin=%d pin_high=%d\n", num, gpio_pin, pin_mode);
padapter->pre_gpio_pin = gpio_pin;
if (pin_mode == 0 || pin_mode == 1)
rtw_hal_set_gpio_output_value(padapter, gpio_pin, pin_mode);
}
return count;
}
static int proc_get_gpio(struct seq_file *m, void *v)
{
u8 gpioreturnvalue = 0;
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (!padapter)
return -EFAULT;
gpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin);
RTW_PRINT_SEL(m, "get_gpio %d:%d\n", padapter->pre_gpio_pin, gpioreturnvalue);
return 0;
}
static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int num = 0, gpio_pin = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%d", &gpio_pin);
RTW_INFO("num=%d gpio_pin=%d\n", num, gpio_pin);
padapter->pre_gpio_pin = gpio_pin;
}
return count;
}
#endif
static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int phy_info_flag = 0;
if (!padapter)
return -EFAULT;
if (count < 1) {
RTW_INFO("argument size is less than 1\n");
return -EFAULT;
}
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d", &phy_info_flag);
}
return count;
}
static int proc_get_rx_info_msg(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
/*rtw_hal_set_phydm_var(padapter, HAL_PHYDM_RX_DATA_INFO, m, _FALSE);*/
return 0;
}
static int proc_get_tx_info_msg(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct sta_info *psta;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct sta_priv *pstapriv = &padapter->stapriv;
int i;
_list *plist, *phead;
u8 current_rate_id = 0, current_sgi = 0;
char *BW, *status;
_rtw_spinlock_bh(&pstapriv->sta_hash_lock);
if (MLME_IS_STA(padapter))
status = "station mode";
else if (MLME_IS_AP(padapter))
status = "AP mode";
else if (MLME_IS_MESH(padapter))
status = "mesh mode";
else
status = " ";
_RTW_PRINT_SEL(m, "status=%s\n", status);
for (i = 0; i < NUM_STA; i++) {
phead = &(pstapriv->sta_hash[i]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
plist = get_next(plist);
if ((_rtw_memcmp(psta->phl_sta->mac_addr, bc_addr, ETH_ALEN) != _TRUE)
&& (_rtw_memcmp(psta->phl_sta->mac_addr, null_addr, ETH_ALEN) != _TRUE)
&& (_rtw_memcmp(psta->phl_sta->mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) {
switch (psta->phl_sta->chandef.bw) {
case CHANNEL_WIDTH_20:
BW = "20M";
break;
case CHANNEL_WIDTH_40:
BW = "40M";
break;
case CHANNEL_WIDTH_80:
BW = "80M";
break;
case CHANNEL_WIDTH_160:
BW = "160M";
break;
default:
BW = "";
break;
}
current_rate_id = rtw_hal_get_current_tx_rate(adapter, psta);
current_sgi = rtw_get_current_tx_sgi(adapter, psta);
RTW_PRINT_SEL(m, "==============================\n");
_RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->phl_sta->mac_addr));
_RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id));
_RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi);
}
}
}
_rtw_spinunlock_bh(&pstapriv->sta_hash_lock);
return 0;
}
#ifdef ROKU_PRIVATE
static u32 rtw_tx_sts_total(u32 *tx_sts, u8 num)
{
u32 ret = 0;
int i = 0;
for (i = 0; i < num; i++)
ret += tx_sts[i];
return ret;
}
static int proc_get_roku_trx_info_msg(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
_list *plist, *phead;
struct sta_info *psta = NULL;
u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}};
uint mac_id[NUM_STA];
struct stainfo_stats *pstats = NULL;
struct sta_priv *pstapriv = &(adapter->stapriv);
u32 i, j, macid_rec_idx = 0;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
u32 tx_retry_cnt[PHL_AC_QUEUE_TOTAL] = {0};
u32 tx_fail_cnt[PHL_AC_QUEUE_TOTAL] = {0};
u32 tx_ok_cnt[PHL_AC_QUEUE_TOTAL] = {0};
#if 0
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
struct sta_recv_dframe_info *psta_dframe_info;
char cnt_str[168] = {0};
char tmp_str[21] = {0};
u8 rx_nss_num = hal_spec->rx_nss_num;
char *BW;
u8 isCCKrate = 0, rf_path = 0;
u8 tx_stats_category = 1; /* 0: pass, 1:drop */
#endif
#if 0
psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
if (psta) {
RTW_PRINT_SEL(m, "Interface Name: %s\n", ADPT_ARG(adapter));
RTW_PRINT_SEL(m, "===== TX and RX Count Statistics =====\n");
RTW_PRINT_SEL(m , "TX packets:%llu\n", pxmitpriv->tx_pkts);
RTW_PRINT_SEL(m , "RX packets:%llu\n", precvpriv->rx_pkts);
RTW_PRINT_SEL(m, "===== TX Drop Statistics =====\n");
RTW_PRINT_SEL(m, "[Driver] BK packets drop count: %llu\n", pxmitpriv->tx_bk_drop_cnt);
RTW_PRINT_SEL(m, "[Driver] BE packets drop count: %llu\n", pxmitpriv->tx_be_drop_cnt);
RTW_PRINT_SEL(m, "[Driver] VI packets drop count: %llu\n", pxmitpriv->tx_vi_drop_cnt);
RTW_PRINT_SEL(m, "[Driver] VO packets drop count: %llu\n", pxmitpriv->tx_vo_drop_cnt);
RTW_PRINT_SEL(m, "===== RX VO packets Statistics =====\n");
for(i = DESC_RATE1M ; i <= DESC_RATE11M ; i++) {
snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[i]);
strncat(cnt_str, tmp_str, strlen(tmp_str));
}
RTW_PRINT_SEL(m, "CCK (1M, 2M, 5.5M, 11M): [ %s]\n", cnt_str);
_rtw_memset(&cnt_str, '\0', sizeof(cnt_str));
for(i = DESC_RATE6M ; i <= DESC_RATE54M ; i++) {
snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[i]);
strncat(cnt_str, tmp_str, strlen(tmp_str));
}
RTW_PRINT_SEL(m, "OFDM (6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M): [ %s]\n", cnt_str);
_rtw_memset(&cnt_str, '\0', sizeof(cnt_str));
for(i = 0 ; i < rx_nss_num ; i++) {
for(j = DESC_RATEMCS0 ; j <= DESC_RATEMCS7 ; j++) {
snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[j + (i<<3)]);
strncat(cnt_str, tmp_str, strlen(tmp_str));
}
RTW_PRINT_SEL(m, "HT_MCS (%d-%d): [ %s]\n", (i<<3), (i<<3) + 7, cnt_str);
_rtw_memset(&cnt_str, '\0', sizeof(cnt_str));
}
if (rx_nss_num == 1)
RTW_PRINT_SEL(m, "HT_MCS (8-15): [ 0 0 0 0 0 0 0 0 ]\n");
for(i = 0 ; i < rx_nss_num ; i++) {
for(j = DESC_RATEVHTSS1MCS0 ; j <= DESC_RATEVHTSS1MCS9 ; j++) {
snprintf(tmp_str, sizeof(tmp_str), "%llu ", precvpriv->rx_vo_pkt_count_per_data_rate[j + (i * 10)]);
strncat(cnt_str, tmp_str, strlen(tmp_str));
}
RTW_PRINT_SEL(m, "VHT_%dSS_MCS (0-9): [ %s]\n", (i + 1), cnt_str);
_rtw_memset(&cnt_str, '\0', sizeof(cnt_str));
}
if (rx_nss_num == 1)
RTW_PRINT_SEL(m, "VHT_2SS_MCS (0-9): [ 0 0 0 0 0 0 0 0 0 0 ]\n");
RTW_PRINT_SEL(m, "RX counter for VO packets with retry bit set: %llu\n\n", precvpriv->rx_vo_pkt_retry_count);
}
#endif
_rtw_spinlock_bh(&pstapriv->sta_hash_lock);
for (i = 0; i < NUM_STA; i++) {
phead = &(pstapriv->sta_hash[i]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
plist = get_next(plist);
if ((_rtw_memcmp(psta->phl_sta->mac_addr, bc_addr, 6) != _TRUE)
&& (_rtw_memcmp(psta->phl_sta->mac_addr, null_addr, 6) != _TRUE)
&& (_rtw_memcmp(psta->phl_sta->mac_addr, adapter_mac_addr(adapter), 6) != _TRUE)) {
_rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->phl_sta->mac_addr, ETH_ALEN);
mac_id[macid_rec_idx] = psta->phl_sta->macid;
macid_rec_idx++;
}
}
}
_rtw_spinunlock_bh(&pstapriv->sta_hash_lock);
for (i = 0; i < macid_rec_idx; i++) {
psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]);
#if 0
if (psta) {
psta_dframe_info = &psta->sta_dframe_info;
isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
switch (psta_dframe_info->sta_bw_mode) {
case CHANNEL_WIDTH_20:
BW = "20M";
break;
case CHANNEL_WIDTH_40:
BW = "40M";
break;
case CHANNEL_WIDTH_80:
BW = "80M";
break;
case CHANNEL_WIDTH_160:
BW = "160M";
break;
default:
BW = "";
break;
}
RTW_PRINT_SEL(m, "========= STA("MAC_FMT") =========\n", MAC_ARG(psta->cmn.mac_addr));
RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n",
rtw_get_oper_ch(adapter), rtw_get_oper_bw(adapter), rtw_get_oper_choffset(adapter));
RTW_PRINT_SEL(m, "BW=%s, sgi =%d\n", BW, psta_dframe_info->sta_sgi);
RTW_PRINT_SEL(m, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
RTW_PRINT_SEL(m, "Rx_Data_Rate_Int = %d\n", (psta_dframe_info->sta_data_rate));
for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
if (!isCCKrate) {
RTW_PRINT_SEL(m , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
RTW_PRINT_SEL(m , "\nrx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
} else
RTW_PRINT_SEL(m , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
}
if (pHalData->NumTotalRFPath == 1) {
if (!isCCKrate) {
RTW_PRINT_SEL(m , "RF_PATH_1 RSSI:%d(dBm)", 0);
RTW_PRINT_SEL(m , "\nrx_ofdm_snr:%d(dB)\n", 0);
} else
RTW_PRINT_SEL(m , "RF_PATH_1 RSSI:%d(dBm)\n", 0);
}
RTW_PRINT_SEL(m , "Total False Alarm:%d / Cnt_CCA_all:%d\n", rtw_phydm_get_phy_cnt(adapter, FA_TOTAL) , rtw_phydm_get_phy_cnt(adapter, CCA_ALL));
} else
RTW_PRINT_SEL(m, "STA is gone\n");
#endif
if(psta) {
rtw_phl_get_tx_retry_rpt(GET_PHL_INFO(adapter_to_dvobj(adapter)),psta->phl_sta,
tx_retry_cnt, PHL_AC_QUEUE_TOTAL);
rtw_phl_get_tx_fail_rpt(GET_PHL_INFO(adapter_to_dvobj(adapter)), psta->phl_sta,
tx_fail_cnt, PHL_AC_QUEUE_TOTAL);
rtw_phl_get_tx_ok_rpt(GET_PHL_INFO(adapter_to_dvobj(adapter)), psta->phl_sta,
tx_ok_cnt, PHL_AC_QUEUE_TOTAL);
pstats = &psta->sta_stats;
pstats->tx_retry_cnt = rtw_tx_sts_total(tx_retry_cnt, PHL_AC_QUEUE_TOTAL);
pstats->tx_fail_cnt = rtw_tx_sts_total(tx_fail_cnt, PHL_AC_QUEUE_TOTAL);
pstats->tx_ok_cnt = rtw_tx_sts_total(tx_ok_cnt, PHL_AC_QUEUE_TOTAL);
pstats->total_tx_retry_cnt += pstats->tx_retry_cnt;
RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n",
MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt);
RTW_PRINT_SEL(m, "total_tx_retry: %llu, rx_retry: %u\n", pstats->total_tx_retry_cnt,
ATOMIC_READ((ATOMIC_T *)&pstats->rx_retry_cnt));
ATOMIC_SET((ATOMIC_T *)&pstats->rx_retry_cnt, 0);
RTW_PRINT_SEL(m, "[HW] BK packets drop count: %u\n", tx_fail_cnt[PHL_BE_QUEUE_SEL]);
RTW_PRINT_SEL(m, "[HW] BE packets drop count: %u\n", tx_fail_cnt[PHL_BK_QUEUE_SEL]);
RTW_PRINT_SEL(m, "[HW] VI packets drop count: %u\n", tx_fail_cnt[PHL_VI_QUEUE_SEL]);
RTW_PRINT_SEL(m, "[HW] VO packets drop count: %u\n", tx_fail_cnt[PHL_VO_QUEUE_SEL]);
} else {
RTW_PRINT_SEL(m, "STA is gone\n");
}
}
return 0;
}
#endif /* ROKU_PRIVATE */
static int proc_get_linked_info_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (padapter)
RTW_PRINT_SEL(m, "rtw_hal_linked_info_dump :%s\n", (padapter->bLinkInfoDump) ? "enable" : "disable");
return 0;
}
static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int mode = 0, pre_mode = 0;
int num = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
pre_mode = padapter->bLinkInfoDump;
RTW_INFO("pre_mode=%d\n", pre_mode);
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%d ", &mode);
RTW_INFO("num=%d mode=%d\n", num, mode);
if (num != 1) {
RTW_INFO("argument number is wrong\n");
return -EFAULT;
}
if (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
padapter->bLinkInfoDump = mode;
else if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */
/* RTW_INFO("rtw_hal_linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
rtw_hal_linked_info_dump(padapter, mode);
}
}
return count;
}
static int proc_get_sta_tp_dump(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (padapter)
RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable");
return 0;
}
static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int mode = 0;
int num = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%d ", &mode);
if (num != 1) {
RTW_INFO("argument number is wrong\n");
return -EFAULT;
}
if (padapter)
padapter->bsta_tp_dump = mode;
}
return count;
}
static int proc_get_sta_tp_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (padapter)
rtw_sta_traffic_info(m, padapter);
return 0;
}
static int proc_get_turboedca_ctrl(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (padapter->dis_turboedca == EN_TURBO)
RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Enable");
else if (padapter->dis_turboedca == DIS_TURBO)
RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Disable");
else
RTW_PRINT_SEL(m, "Turbo-EDCA : %s, mode=%d, edca_param_mode=0x%x\n",
"Disable", padapter->dis_turboedca, padapter->edca_param_mode);
_RTW_PRINT_SEL(m, "PARAM_BE:0x%x\n", padapter->edca_param_mode);
return 0;
}
static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
int mode = 0, num = 0;
u32 param_mode = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp))
return -EFAULT;
if (buffer && !copy_from_user(tmp, buffer, count)) {
num = sscanf(tmp, "%d %x", &mode, ¶m_mode);
if (num < 1 || num > 2) {
RTW_INFO("argument number is wrong\n");
return -EFAULT;
}
/* 0: enable turboedca,
1: disable turboedca,
2: disable turboedca and setting EDCA parameter based on the input parameter
> 2 : currently reset to 0 */
if (mode > 2)
mode = 0;
padapter->dis_turboedca = mode;
padapter->edca_param_mode = 0; /* init. value */
RTW_INFO("dis_turboedca mode = 0x%x\n", padapter->dis_turboedca);
if (num == 2) {
padapter->edca_param_mode = param_mode;
RTW_INFO("param_mode = 0x%x\n", param_mode);
}
}
return count;
}
static int proc_get_mac_qinfo(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m);
return 0;
}
int proc_get_wifi_spec(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregpriv = &padapter->registrypriv;
RTW_PRINT_SEL(m, "wifi_spec=%d\n", pregpriv->wifi_spec);
return 0;
}
static int proc_get_chan_plan(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_cur_chset(m, adapter_to_rfctl(adapter));
return 0;
}
static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u16 chplan = RTW_CHPLAN_UNSPECIFIED;
u16 chplan_6g = RTW_CHPLAN_6G_UNSPECIFIED;
if (!padapter)
return -EFAULT;
if (count < 1) {
RTW_INFO("argument size is less than 1\n");
return -EFAULT;
}
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hx %hx", &chplan, &chplan_6g);
if (num < 1)
return count;
rtw_chplan_ioctl_input_mapping(&chplan, &chplan_6g);
}
rtw_set_channel_plan(padapter, chplan, chplan_6g, RTW_REGD_SET_BY_USER);
return count;
}
static int proc_get_country_code(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
dump_cur_country(m, rfctl);
return 0;
}
static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
char alpha2[2];
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%c%c", &alpha2[0], &alpha2[1]);
if (num != 2)
return count;
rtw_set_country(padapter, alpha2, RTW_REGD_SET_BY_USER);
exit:
return count;
}
static int cap_spt_op_class_ch_detail = 0;
static int proc_get_cap_spt_op_class_ch(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_cap_spt_op_class_ch(m , adapter_to_rfctl(adapter), cap_spt_op_class_ch_detail);
return 0;
}
static ssize_t proc_set_cap_spt_op_class_ch(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%d", &cap_spt_op_class_ch_detail);
exit:
return count;
}
static int reg_spt_op_class_ch_detail = 0;
static int proc_get_reg_spt_op_class_ch(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_reg_spt_op_class_ch(m , adapter_to_rfctl(adapter), reg_spt_op_class_ch_detail);
return 0;
}
static ssize_t proc_set_reg_spt_op_class_ch(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%d", ®_spt_op_class_ch_detail);
exit:
return count;
}
static int cur_spt_op_class_ch_detail = 0;
static int proc_get_cur_spt_op_class_ch(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_cur_spt_op_class_ch(m , adapter_to_rfctl(adapter), cur_spt_op_class_ch_detail);
return 0;
}
static ssize_t proc_set_cur_spt_op_class_ch(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%d", &cur_spt_op_class_ch_detail);
exit:
return count;
}
#if CONFIG_RTW_MACADDR_ACL
static int proc_get_macaddr_acl(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_macaddr_acl(m, adapter);
return 0;
}
ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[17 * NUM_ACL + 32] = {0};
u8 period;
char cmd[32];
u8 mode;
u8 addr[ETH_ALEN];
#define MAC_ACL_CMD_MODE 0
#define MAC_ACL_CMD_ADD 1
#define MAC_ACL_CMD_DEL 2
#define MAC_ACL_CMD_CLR 3
#define MAC_ACL_CMD_NUM 4
static const char * const mac_acl_cmd_str[] = {
"mode",
"add",
"del",
"clr",
};
u8 cmd_id = MAC_ACL_CMD_NUM;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
/*
* <period> mode <mode> <macaddr> [<macaddr>]
* <period> mode <mode>
* <period> add <macaddr> [<macaddr>]
* <period> del <macaddr> [<macaddr>]
* <period> clr
*/
char *c, *next;
int i;
u8 is_bcast;
next = tmp;
c = strsep(&next, " \t");
if (!c || sscanf(c, "%hhu", &period) != 1)
goto exit;
if (period >= RTW_ACL_PERIOD_NUM) {
RTW_WARN(FUNC_ADPT_FMT" invalid period:%u", FUNC_ADPT_ARG(adapter), period);
goto exit;
}
c = strsep(&next, " \t");
if (!c || sscanf(c, "%s", cmd) != 1)
goto exit;
for (i = 0; i < MAC_ACL_CMD_NUM; i++)
if (strcmp(mac_acl_cmd_str[i], cmd) == 0)
cmd_id = i;
switch (cmd_id) {
case MAC_ACL_CMD_MODE:
c = strsep(&next, " \t");
if (!c || sscanf(c, "%hhu", &mode) != 1)
goto exit;
if (mode >= RTW_ACL_MODE_MAX) {
RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u", FUNC_ADPT_ARG(adapter), mode);
goto exit;
}
break;
case MAC_ACL_CMD_ADD:
case MAC_ACL_CMD_DEL:
break;
case MAC_ACL_CMD_CLR:
/* clear settings */
rtw_macaddr_acl_clear(adapter, period);
goto exit;
default:
RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"", FUNC_ADPT_ARG(adapter), cmd);
goto exit;
}
/* check for macaddr list */
c = strsep(&next, " \t");
if (!c && cmd_id == MAC_ACL_CMD_MODE) {
/* set mode only */
rtw_set_macaddr_acl(adapter, period, mode);
goto exit;
}
if (cmd_id == MAC_ACL_CMD_MODE) {
/* set mode and entire macaddr list */
rtw_macaddr_acl_clear(adapter, period);
rtw_set_macaddr_acl(adapter, period, mode);
}
while (c != NULL) {
if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
break;
is_bcast = is_broadcast_mac_addr(addr);
if (is_bcast
|| rtw_check_invalid_mac_address(addr, 0) == _FALSE
) {
if (cmd_id == MAC_ACL_CMD_DEL) {
rtw_acl_remove_sta(adapter, period, addr);
if (is_bcast)
break;
} else if (!is_bcast)
rtw_acl_add_sta(adapter, period, addr);
}
c = strsep(&next, " \t");
}
}
exit:
return count;
}
#endif /* CONFIG_RTW_MACADDR_ACL */
#if CONFIG_RTW_PRE_LINK_STA
static int proc_get_pre_link_sta(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_pre_link_sta_ctl(m, &adapter->stapriv);
return 0;
}
ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_priv *mlme = &adapter->mlmepriv;
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
char tmp[17 * RTW_PRE_LINK_STA_NUM + 32] = {0};
char arg0[16] = {0};
u8 addr[ETH_ALEN];
#define PRE_LINK_STA_CMD_RESET 0
#define PRE_LINK_STA_CMD_ADD 1
#define PRE_LINK_STA_CMD_DEL 2
#define PRE_LINK_STA_CMD_NUM 3
static const char * const pre_link_sta_cmd_str[] = {
"reset",
"add",
"del"
};
u8 cmd_id = PRE_LINK_STA_CMD_NUM;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
/* cmd [<macaddr>] */
char *c, *next;
int i;
next = tmp;
c = strsep(&next, " \t");
if (sscanf(c, "%s", arg0) != 1)
goto exit;
for (i = 0; i < PRE_LINK_STA_CMD_NUM; i++)
if (strcmp(pre_link_sta_cmd_str[i], arg0) == 0)
cmd_id = i;
switch (cmd_id) {
case PRE_LINK_STA_CMD_RESET:
rtw_pre_link_sta_ctl_reset(&adapter->stapriv);
goto exit;
case PRE_LINK_STA_CMD_ADD:
case PRE_LINK_STA_CMD_DEL:
break;
default:
goto exit;
}
/* macaddr list */
c = strsep(&next, " \t");
while (c != NULL) {
if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
break;
if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) {
if (cmd_id == PRE_LINK_STA_CMD_ADD)
rtw_pre_link_sta_add(&adapter->stapriv, addr);
else
rtw_pre_link_sta_del(&adapter->stapriv, addr);
}
c = strsep(&next, " \t");
}
}
exit:
return count;
}
#endif /* CONFIG_RTW_PRE_LINK_STA */
static int proc_get_ch_sel_policy(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
RTW_PRINT_SEL(m, "%-16s\n", "within_same_band");
RTW_PRINT_SEL(m, "%16d\n", rfctl->ch_sel_within_same_band);
return 0;
}
static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 within_sb;
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%hhu", &within_sb);
if (num >= 1)
rfctl->ch_sel_within_same_band = within_sb ? 1 : 0;
exit:
return count;
}
#ifdef CONFIG_80211D
static int proc_get_country_ie_slave_en_conds(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
RTW_PRINT_SEL(m, "%-4s %-5s\n", "role", "ifbmp");
RTW_PRINT_SEL(m, "0x%02x 0x%02x\n"
, rfctl->country_ie_slave_en_role
, rfctl->country_ie_slave_en_ifbmp
);
return 0;
}
static ssize_t proc_set_country_ie_slave_en_conds(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
u8 role, ifbmp;
int num = sscanf(tmp, "%hhx %hhx", &role, &ifbmp);
if (num >= 1)
rfctl->country_ie_slave_en_role = role;
if (num >= 2)
rfctl->country_ie_slave_en_ifbmp = ifbmp;
}
return count;
}
static int proc_get_country_ie_slave_records(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
dump_country_ie_slave_records(m, rfctl, 0);
return 0;
}
#endif /* CONFIG_80211D */
#ifdef CONFIG_DFS_MASTER
static int proc_get_dfs_test_case(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first");
RTW_PRINT_SEL(m, "%24hhu %19hhu\n"
, rfctl->dbg_dfs_radar_detect_trigger_non
, rfctl->dbg_dfs_choose_dfs_ch_first
);
return 0;
}
static ssize_t proc_set_dfs_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 radar_detect_trigger_non;
u8 choose_dfs_ch_first;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first);
if (num >= 1)
rfctl->dbg_dfs_radar_detect_trigger_non = radar_detect_trigger_non;
if (num >= 2)
rfctl->dbg_dfs_choose_dfs_ch_first = choose_dfs_ch_first;
}
return count;
}
ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 ch, bw = CHANNEL_WIDTH_20, offset = CHAN_OFFSET_NO_EXT;
int ms = -1;
bool updated = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms);
if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
goto exit;
if (bw == CHANNEL_WIDTH_20)
updated = rtw_chset_update_non_ocp_ms(rfctl->channel_set
, ch, bw, CHAN_OFFSET_NO_EXT, ms);
else
updated = rtw_chset_update_non_ocp_ms(rfctl->channel_set
, ch, bw, offset, ms);
if (updated) {
u8 cch = rtw_get_center_ch(ch, bw, offset);
rtw_nlrtw_nop_start_event(adapter, cch, bw);
}
}
exit:
return count;
}
ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 fake_radar_detect_cnt = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt);
if (num < 1)
goto exit;
rfctl->dbg_dfs_fake_radar_detect_cnt = fake_radar_detect_cnt;
}
exit:
return count;
}
static int proc_get_dfs_ch_sel_e_flags(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_e_flags);
return 0;
}
static ssize_t proc_set_dfs_ch_sel_e_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 e_flags;
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%hhx", &e_flags);
if (num != 1)
goto exit;
rfctl->dfs_ch_sel_e_flags = e_flags;
exit:
return count;
}
static int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_d_flags);
return 0;
}
static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 d_flags;
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%hhx", &d_flags);
if (num != 1)
goto exit;
rfctl->dfs_ch_sel_d_flags = d_flags;
exit:
return count;
}
#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
static int proc_get_dfs_slave_with_rd(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
RTW_PRINT_SEL(m, "%u\n", rfctl->dfs_slave_with_rd);
return 0;
}
static ssize_t proc_set_dfs_slave_with_rd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
char tmp[32];
u8 rd;
int num;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%hhu", &rd);
if (num != 1)
goto exit;
rd = rd ? 1 : 0;
if (rfctl->dfs_slave_with_rd != rd) {
rfctl->dfs_slave_with_rd = rd;
rtw_dfs_rd_en_decision_cmd(adapter);
}
exit:
return count;
}
#endif /* CONFIG_DFS_SLAVE_WITH_RADAR_DETECT */
#endif /* CONFIG_DFS_MASTER */
#ifdef CONFIG_80211N_HT
int proc_get_rx_ampdu_size_limit(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_regsty_rx_ampdu_size_limit(m, adapter);
return 0;
}
ssize_t proc_set_rx_ampdu_size_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *regsty = adapter_to_regsty(adapter);
char tmp[32];
u8 nss;
u8 limit_by_bw[4] = {0xFF};
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int i;
int num = sscanf(tmp, "%hhu %hhu %hhu %hhu %hhu"
, &nss, &limit_by_bw[0], &limit_by_bw[1], &limit_by_bw[2], &limit_by_bw[3]);
if (num < 2)
goto exit;
if (nss == 0 || nss > 4)
goto exit;
for (i = 0; i < num - 1; i++)
regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][i] = limit_by_bw[i];
rtw_rx_ampdu_apply(adapter);
}
exit:
return count;
}
#endif /* CONFIG_80211N_HT */
static int proc_get_rx_chk_limit(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
RTW_PRINT_SEL(m, "Rx chk limit : %d\n", rtw_get_rx_chk_limit(padapter));
return 0;
}
static ssize_t proc_set_rx_chk_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
char tmp[32];
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
int rx_chk_limit;
if (count < 1) {
RTW_INFO("argument size is less than 1\n");
return -EFAULT;
}
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d", &rx_chk_limit);
rtw_set_rx_chk_limit(padapter, rx_chk_limit);
}
return count;
}
static int proc_get_udpport(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct recv_info *precvinfo = &(padapter->recvinfo);
RTW_PRINT_SEL(m, "%d\n", precvinfo->sink_udpport);
return 0;
}
static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct recv_info *precvinfo = &(padapter->recvinfo);
int sink_udpport = 0;
char tmp[32];
if (!padapter)
return -EFAULT;
if (count < 1) {
RTW_INFO("argument size is less than 1\n");
return -EFAULT;
}
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d", &sink_udpport);
if (num != 1) {
RTW_INFO("invalid input parameter number!\n");
return count;
}
}
precvinfo->sink_udpport = sink_udpport;
return count;
}
#if 0
static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
u8 i;
for (i = 0; i < dvobj->iface_nums; i++)
RTW_PRINT_SEL(m, "iface_id:%d, mac_id && sec_cam_id = %d\n", i, macid_ctl->iface_bmc[i]);
return 0;
}
#endif
#if 0
static int proc_get_macid_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
u8 i;
u8 null_addr[ETH_ALEN] = {0};
u8 *macaddr;
RTW_PRINT_SEL(m, "max_num:%u\n", macid_ctl->num);
RTW_PRINT_SEL(m, "\n");
RTW_PRINT_SEL(m, "used:\n");
dump_macid_map(m, &macid_ctl->used, macid_ctl->num);
RTW_PRINT_SEL(m, "\n");
RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s"
, "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht");
if (GET_HAL_TX_NSS(dvobj) > 2)
_RTW_PRINT_SEL(m, " %-10s", "rate_bmp1");
_RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status");
for (i = 0; i < macid_ctl->num; i++) {
if (rtw_macid_is_used(macid_ctl, i)
|| macid_ctl->h2c_msr[i]
) {
if (macid_ctl->sta[i])
macaddr = macid_ctl->sta[i]->phl_sta->mac_addr;
else
macaddr = null_addr;
RTW_PRINT_SEL(m, "%3u %3u 0x%02x %4d "MAC_FMT" %6s %3u"
, i
, rtw_macid_is_bmc(macid_ctl, i)
, rtw_macid_get_iface_bmp(macid_ctl, i)
, rtw_macid_get_ch_g(macid_ctl, i)
, MAC_ARG(macaddr)
, ch_width_str(macid_ctl->bw[i])
, macid_ctl->vht_en[i]
);
if (GET_HAL_TX_NSS(dvobj) > 2)
_RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]);
#ifdef DBG_MACID_MSR_INFO
_RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n"
, macid_ctl->rate_bmp0[i]
, H2C_MSR_ARG(&macid_ctl->h2c_msr[i])
, rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]"
);
#endif
}
}
return 0;
}
#endif
static int proc_get_sec_cam(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
RTW_PRINT_SEL(m, "sec_cap:0x%02x\n", cam_ctl->sec_cap);
RTW_PRINT_SEL(m, "flags:0x%08x\n", cam_ctl->flags);
RTW_PRINT_SEL(m, "\n");
RTW_PRINT_SEL(m, "max_num:%u\n", cam_ctl->num);
RTW_PRINT_SEL(m, "used:\n");
dump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num);
RTW_PRINT_SEL(m, "\n");
#if 0 /*GEORGIA_TODO_REDEFINE_IO*/
RTW_PRINT_SEL(m, "reg_scr:0x%04x\n", rtw_read16(adapter, 0x680));
#endif
RTW_PRINT_SEL(m, "\n");
dump_sec_cam(m, adapter);
return 0;
}
static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
char tmp[32] = {0};
char cmd[4];
u8 id_1 = 0, id_2 = 0;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
/* c <id_1>: clear specific cam entry */
/* wfc <id_1>: write specific cam entry from cam cache */
/* sw <id_1> <id_2>: sec_cam 1/2 swap */
int num = sscanf(tmp, "%s %hhu %hhu", cmd, &id_1, &id_2);
if (num < 2)
return count;
if ((id_1 >= cam_ctl->num) || (id_2 >= cam_ctl->num)) {
RTW_ERR(FUNC_ADPT_FMT" invalid id_1:%u id_2:%u\n", FUNC_ADPT_ARG(adapter), id_1, id_2);
return count;
}
if (strcmp("c", cmd) == 0) {
_clear_cam_entry(adapter, id_1);
adapter->securitypriv.hw_decrypted = _FALSE; /* temporarily set this for TX path to use SW enc */
} else if (strcmp("wfc", cmd) == 0)
write_cam_from_cache(adapter, id_1);
else if (strcmp("sw", cmd) == 0)
rtw_sec_cam_swap(adapter, id_1, id_2);
else if (strcmp("cdk", cmd) == 0)
rtw_clean_dk_section(adapter);
#ifdef DBG_SEC_CAM_MOVE
else if (strcmp("sgd", cmd) == 0)
rtw_hal_move_sta_gk_to_dk(adapter);
else if (strcmp("rsd", cmd) == 0)
rtw_hal_read_sta_dk_key(adapter, id_1);
#endif
}
return count;
}
static int proc_get_sec_cam_cache(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_sec_cam_cache(m, adapter);
return 0;
}
#ifdef CONFIG_DBG_AX_CAM
static int proc_get_ax_address_cam(struct seq_file *m, void *v) {
struct net_device *dev = m->private;
struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);
get_ax_address_cam(m, adapter);
return 0;
}
static int proc_get_ax_sec_cam(struct seq_file *m, void *v) {
struct net_device *dev = m->private;
struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);
get_ax_sec_cam(m, adapter);
return 0;
}
static int proc_get_ax_valid_key(struct seq_file *m, void *v) {
struct net_device *dev = m->private;
struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);
get_ax_valid_key(m, adapter);
return 0;
}
#endif
static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
int i;
char tmp[32];
s16 ch;
s8 bw = REQ_BW_NONE, offset = REQ_OFFSET_NONE;
u8 ifbmp = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hd %hhd %hhd %hhx", &ch, &bw, &offset, &ifbmp);
if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
goto exit;
if (num < 4)
ifbmp = BIT(adapter->iface_id);
else
ifbmp &= (1 << dvobj->iface_nums) - 1;
for (i = 0; i < dvobj->iface_nums; i++) {
if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
continue;
if (!CHK_MLME_STATE(dvobj->padapters[i], WIFI_AP_STATE | WIFI_MESH_STATE)
|| !MLME_IS_ASOC(dvobj->padapters[i]))
ifbmp &= ~BIT(i);
}
if (ifbmp)
rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ifbmp, 0, ch, bw, offset);
}
exit:
return count;
}
static int proc_get_tx_bw_mode(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode);
RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter)));
RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter)));
return 0;
}
static void rtw_set_tx_bw_mode(_adapter *adapter, u8 bw_mode)
{
struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
/* macid_ctl move to phl */
/* struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; */
u8 update = _FALSE;
if ((MLME_STATE(adapter) & WIFI_ASOC_STATE)
&& ((mlmeext->chandef.chan <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter))
|| (mlmeext->chandef.chan >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter)))
) {
/* RA mask update needed */
update = _TRUE;
}
adapter->driver_tx_bw_mode = bw_mode;
#if 0
if (update == _TRUE) {
struct sta_info *sta;
int i;
/*for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {*/
//sta = macid_ctl->sta[i];
sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
if (sta && !is_broadcast_mac_addr(sta->phl_sta->mac_addr)) {
rtw_phl_cmd_change_stainfo(adapter_to_dvobj(adapter)->phl,
sta->phl_sta,
STA_CHG_RAMASK,
NULL,
0,
PHL_CMD_NO_WAIT, /*PHL_CMD_DIRECTLY,PHL_CMD_WAIT*/
0);
}
}
/*}*/
#endif
}
static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u8 bw_mode;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhx", &bw_mode);
if (num < 1 || bw_mode == adapter->driver_tx_bw_mode)
goto exit;
rtw_set_tx_bw_mode(adapter, bw_mode);
}
exit:
return count;
}
static int proc_get_hal_txpwr_info(struct seq_file *m, void *v)
{
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *devob = adapter_to_dvobj(adapter);
HAL_DATA_TYPE *hal_data = GET_PHL_COM(devob);
struct hal_spec_t *hal_spec = GET_HAL_SPEC(devob);
if (hal_data->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX) {
if (rtw_hw_is_band_support(devob, BAND_ON_24G))
dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_data->max_tx_cnt);
#if CONFIG_IEEE80211_BAND_5GHZ
if (rtw_hw_is_band_support(devob, BAND_ON_5G))
dump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_data->max_tx_cnt);
#endif
}
#endif
return 0;
}
static int proc_get_target_tx_power(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_hal_dump_target_tx_power(m, adapter);
return 0;
}
static int proc_get_tx_power_by_rate(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_hal_dump_tx_power_by_rate(m, adapter);
return 0;
}
#if CONFIG_TXPWR_LIMIT
static int proc_get_tx_power_limit(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_txpwr_lmt(m, adapter);
return 0;
}
#endif /* CONFIG_TXPWR_LIMIT */
static int proc_get_tx_power_ext_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_dump_phl_tx_power_ext_info(m, adapter);
return 0;
}
static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32] = {0};
char cmd[16] = {0};
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%s", cmd);
if (num < 1)
return count;
#if 0 /* TODO */
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE);
#endif
rtw_ps_deny(adapter, PS_DENY_IOCTL);
if (rtw_pwr_wakeup(adapter) == _FALSE)
goto clear_ps_deny;
if (strcmp("default", cmd) == 0)
rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter);
else
rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter);
rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
clear_ps_deny:
rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
#endif
}
return count;
}
#ifdef GEORGIA_TODO_TX_PWR
static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos)
{
u8 path = ((*pos) & 0xFF00) >> 8;
if (path >= RF_PATH_MAX)
return NULL;
return pos;
}
static void proc_stop_tx_power_idx(struct seq_file *m, void *v)
{
}
static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos)
{
u8 path = ((*pos) & 0xFF00) >> 8;
u8 rs = *pos & 0xFF;
rs++;
if (rs >= RATE_SECTION_NUM) {
rs = 0;
path++;
}
if (path >= RF_PATH_MAX)
return NULL;
*pos = (path << 8) | rs;
return pos;
}
static int proc_get_tx_power_idx(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
u32 pos = *((loff_t *)(v));
u8 path = (pos & 0xFF00) >> 8;
u8 rs = pos & 0xFF;
if (0)
RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs);
if (path == RF_PATH_A && rs == CCK)
dump_tx_power_idx_title(m, adapter);
dump_tx_power_idx_by_path_rs(m, adapter, path, rs);
return 0;
}
static struct seq_operations seq_ops_tx_power_idx = {
.start = proc_start_tx_power_idx,
.stop = proc_stop_tx_power_idx,
.next = proc_next_tx_power_idx,
.show = proc_get_tx_power_idx,
};
static void *proc_start_txpwr_total_dbm(struct seq_file *m, loff_t *pos)
{
u8 rs = *pos;
if (rs >= RATE_SECTION_NUM)
return NULL;
return pos;
}
static void proc_stop_txpwr_total_dbm(struct seq_file *m, void *v)
{
}
static void *proc_next_txpwr_total_dbm(struct seq_file *m, void *v, loff_t *pos)
{
u8 rs = *pos;
rs++;
if (rs >= RATE_SECTION_NUM)
return NULL;
*pos = rs;
return pos;
}
static int proc_get_txpwr_total_dbm(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
u32 pos = *((loff_t *)(v));
u8 rs = pos;
if (rs == CCK)
dump_txpwr_total_dbm_title(m, adapter);
dump_txpwr_total_dbm_by_rs(m, adapter, rs);
return 0;
}
static struct seq_operations seq_ops_txpwr_total_dbm = {
.start = proc_start_txpwr_total_dbm,
.stop = proc_stop_txpwr_total_dbm,
.next = proc_next_txpwr_total_dbm,
.show = proc_get_txpwr_total_dbm,
};
#endif
#ifdef CONFIG_BTC
static u8 btreg_read_type = 0;
static u16 btreg_read_addr = 0;
static int btreg_read_error = 0;
static u8 btreg_write_type = 0;
static u16 btreg_write_addr = 0;
static int btreg_write_error = 0;
static u8 *btreg_type[] = {
"rf",
"modem",
"bluewize",
"vendor",
"le"
};
static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val)
{
u32 num;
u8 str[80] = {0};
u8 t = 0;
u32 a, v;
u8 i, n;
num = sscanf(input, "%s %x %x", str, &a, &v);
if (num < 2) {
RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
return -EINVAL;
}
if ((num < 3) && val) {
RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
return -EINVAL;
}
n = sizeof(btreg_type) / sizeof(btreg_type[0]);
for (i = 0; i < n; i++) {
if (!strcasecmp(str, btreg_type[i])) {
t = i;
break;
}
}
if (i == n) {
RTW_INFO("%s: unknown type(%s)!\n", __FUNCTION__, str);
return -EINVAL;
}
switch (t) {
case 0:
/* RF */
if (a & 0xFFFFFF80) {
RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
__FUNCTION__, a, btreg_type[t], t);
return -EINVAL;
}
break;
case 1:
/* Modem */
if (a & 0xFFFFFE00) {
RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
__FUNCTION__, a, btreg_type[t], t);
return -EINVAL;
}
break;
default:
/* Others(Bluewize, Vendor, LE) */
if (a & 0xFFFFF000) {
RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
__FUNCTION__, a, btreg_type[t], t);
return -EINVAL;
}
break;
}
if (val) {
if (v & 0xFFFF0000) {
RTW_INFO("%s: INVALID value(0x%x)!\n", __FUNCTION__, v);
return -EINVAL;
}
*val = (u16)v;
}
*type = (u8)t;
*addr = (u16)a;
return 0;
}
int proc_get_btreg_read(struct seq_file *m, void *v)
{
#if 0
struct net_device *dev;
_adapter *padapter;
u16 ret;
u32 data;
if (btreg_read_error)
return btreg_read_error;
dev = m->private;
padapter = (_adapter *)rtw_netdev_priv(dev);
ret = rtw_btc_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data);
if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_read_type], btreg_read_addr, data);
else
RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_read_type], btreg_read_addr, ret);
#endif
return 0;
}
ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
#if 0
struct net_device *dev = data;
_adapter *padapter;
u8 tmp[80] = {0};
u32 num;
int err;
padapter = (_adapter *)rtw_netdev_priv(dev);
if (NULL == buffer) {
RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
FUNC_ADPT_ARG(padapter));
err = -EFAULT;
goto exit;
}
if (count < 1) {
RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
FUNC_ADPT_ARG(padapter));
err = -EFAULT;
goto exit;
}
num = count;
if (num > (sizeof(tmp) - 1))
num = (sizeof(tmp) - 1);
if (copy_from_user(tmp, buffer, num)) {
RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
FUNC_ADPT_ARG(padapter));
err = -EFAULT;
goto exit;
}
/* [Coverity] sure tmp end with '\0'(string terminal) */
tmp[sizeof(tmp) - 1] = 0;
err = btreg_parse_str(tmp, &btreg_read_type, &btreg_read_addr, NULL);
if (err)
goto exit;
RTW_INFO(FUNC_ADPT_FMT ": addr=(%s)0x%X\n",
FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr);
exit:
btreg_read_error = err;
#endif
return count;
}
int proc_get_btreg_write(struct seq_file *m, void *v)
{
#if 0
struct net_device *dev;
_adapter *padapter;
u16 ret;
u32 data;
if (btreg_write_error < 0)
return btreg_write_error;
else if (btreg_write_error > 0) {
RTW_PRINT_SEL(m, "BTREG write: (%s)0x%04X write fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, btreg_write_error);
return 0;
}
dev = m->private;
padapter = (_adapter *)rtw_netdev_priv(dev);
ret = rtw_btc_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data);
if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_write_type], btreg_write_addr, data);
else
RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, ret);
#endif
return 0;
}
ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
#if 0
struct net_device *dev = data;
_adapter *padapter;
u8 tmp[80] = {0};
u32 num;
u16 val;
u16 ret;
int err;
padapter = (_adapter *)rtw_netdev_priv(dev);
if (NULL == buffer) {
RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
FUNC_ADPT_ARG(padapter));
err = -EFAULT;
goto exit;
}
if (count < 1) {
RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
FUNC_ADPT_ARG(padapter));
err = -EFAULT;
goto exit;
}
num = count;
if (num > (sizeof(tmp) - 1))
num = (sizeof(tmp) - 1);
if (copy_from_user(tmp, buffer, num)) {
RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
FUNC_ADPT_ARG(padapter));
err = -EFAULT;
goto exit;
}
err = btreg_parse_str(tmp, &btreg_write_type, &btreg_write_addr, &val);
if (err)
goto exit;
RTW_INFO(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n",
FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val);
ret = rtw_btc_btreg_write(padapter, btreg_write_type, btreg_write_addr, val);
if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
err = ret;
exit:
btreg_write_error = err;
#endif
return count;
}
#endif /* CONFIG_BTC */
int proc_get_mac_addr(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_hal_dump_macaddr(m, adapter);
return 0;
}
static int proc_get_skip_band(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
int bandskip;
bandskip = RTW_GET_SCAN_BAND_SKIP(adapter);
RTW_PRINT_SEL(m, "bandskip:0x%02x\n", bandskip);
return 0;
}
static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[6];
u8 skip_band;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu", &skip_band);
if (num < 1)
return -EINVAL;
if (1 == skip_band)
RTW_SET_SCAN_BAND_SKIP(padapter, BAND_24G);
else if (2 == skip_band)
RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
else if (3 == skip_band)
RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_24G);
else if (4 == skip_band)
RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_5G);
}
return count;
}
#ifdef CONFIG_RTW_ACS
#ifdef WKARD_ACS
static void rtw_acs_chan_info_dump(struct seq_file *m, _adapter *a)
{
}
static void rtw_acs_info_dump(struct seq_file *m, _adapter *a)
{
}
static int proc_get_chan_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_acs_chan_info_dump(m, adapter);
return 0;
}
static int proc_get_best_chan(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (IS_ACS_ENABLE(adapter))
rtw_acs_info_dump(m, adapter);
else
_RTW_PRINT_SEL(m,"ACS disabled\n");
return 0;
}
static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
#ifdef CONFIG_RTW_ACS_DBG
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u8 acs_state = 0;
u16 scan_ch_ms= 0, acs_scan_ch_ms = 0;
u8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0;
u8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %hhu %hu %hhx %hhu",
&acs_state, &scan_type, &scan_ch_ms, &igi, &bw);
if (num < 1)
return -EINVAL;
if (acs_state)
rtw_acs_start(padapter);
else
rtw_acs_stop(padapter);
num = num -1;
if(num) {
if (num-- > 0)
acs_scan_type = scan_type;
if (num-- > 0)
acs_scan_ch_ms = scan_ch_ms;
if (num-- > 0)
acs_igi = igi;
if (num-- > 0)
acs_bw = bw;
rtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw);
}
}
#endif /*CONFIG_RTW_ACS_DBG*/
return count;
}
#endif /* WKARD_ACS */
#endif /*CONFIG_RTW_ACS*/
static int proc_get_env_rpt(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_dump_env_rpt(adapter, m);
return 0;
}
static int proc_get_hal_spec(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_hw_dump_hal_spec(m, adapter_to_dvobj(adapter));
return 0;
}
static int proc_get_hal_trx_mode(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
rtw_hal_dump_trx_mode(m, adapter);
return 0;
}
static int proc_get_phy_cap(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
#ifdef CONFIG_80211N_HT
rtw_dump_drv_phy_cap(m, adapter);
rtw_get_dft_phy_cap(m, adapter);
#endif /* CONFIG_80211N_HT */
return 0;
}
static int proc_dump_rsvd_page(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_hal_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num);
return 0;
}
static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u8 page_offset, page_num;
if (count < 2)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %hhu", &page_offset, &page_num);
if (num < 2)
return -EINVAL;
padapter->rsvd_page_offset = page_offset;
padapter->rsvd_page_num = page_num;
}
return count;
}
#ifdef CONFIG_SUPPORT_FIFO_DUMP
static int proc_dump_fifo(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
rtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size);
return 0;
}
static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u8 fifo_sel = 0;
u32 fifo_addr = 0;
u32 fifo_size = 0;
if (count < 3)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu %x %d", &fifo_sel, &fifo_addr, &fifo_size);
if (num < 3)
return -EINVAL;
padapter->fifo_sel = fifo_sel;
padapter->fifo_addr = fifo_addr;
padapter->fifo_size = fifo_size;
}
return count;
}
#endif
#ifdef CONFIG_WOWLAN
int proc_dump_pattern_cam(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
int i;
#if 0 /* WOW_ToDo */
struct rtl_wow_pattern context;
for (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) {
rtw_wow_pattern_read_cam_ent(padapter, i, &context);
rtw_dump_wow_pattern(m, &context, i);
}
#endif
return 0;
}
#endif
static int proc_get_napi_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregistrypriv = &adapter->registrypriv;
u8 napi = 0, gro = 0;
u32 weight = 0;
struct dvobj_priv *d;
d = adapter_to_dvobj(adapter);
#ifdef CONFIG_RTW_NAPI
if (pregistrypriv->en_napi) {
napi = 1;
weight = RTL_NAPI_WEIGHT;
}
#ifdef CONFIG_RTW_GRO
if (pregistrypriv->en_gro)
gro = 1;
#endif /* CONFIG_RTW_GRO */
#endif /* CONFIG_RTW_NAPI */
if (napi) {
RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight);
#ifdef CONFIG_RTW_NAPI_DYNAMIC
RTW_PRINT_SEL(m, "Dynamaic NAPI mechanism is on, current NAPI %s\n",
d->en_napi_dynamic ? "enable" : "disable");
RTW_PRINT_SEL(m, "Dynamaic NAPI info:\n"
"\ttcp_rx_threshold = %d Mbps\n"
"\tcur_rx_tp = %d Mbps\n",
pregistrypriv->napi_threshold,
d->traffic_stat.cur_rx_tp);
#endif /* CONFIG_RTW_NAPI_DYNAMIC */
} else {
RTW_PRINT_SEL(m, "NAPI disable\n");
}
RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable");
return 0;
}
#ifdef CONFIG_RTW_NAPI_DYNAMIC
static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *registry = &adapter->registrypriv;
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
_adapter *iface = NULL;
char tmp[32] = {0};
int thrshld = 0;
int num = 0, i = 0;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
RTW_INFO("%s: Last threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if (iface) {
if (buffer && !copy_from_user(tmp, buffer, count)) {
registry = &iface->registrypriv;
num = sscanf(tmp, "%d", &thrshld);
if (num > 0) {
if (thrshld > 0)
registry->napi_threshold = thrshld;
}
}
}
}
RTW_INFO("%s: New threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
RTW_INFO("%s: Current RX throughput = %d Mbps\n",
__FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp);
return count;
}
#endif /* CONFIG_RTW_NAPI_DYNAMIC */
ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
int enable = 0, i = 0;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
_adapter *iface = NULL;
int num = sscanf(tmp, "%d", &enable);
if (num != 1) {
RTW_INFO("invalid parameter!\n");
return count;
}
RTW_INFO("dynamic_agg_enable:%d\n", enable);
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if (iface)
iface->registrypriv.dynamic_agg_enable = enable;
}
}
return count;
}
static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregistrypriv = &adapter->registrypriv;
RTW_PRINT_SEL(m, "dynamic_agg_enable:%d\n", pregistrypriv->dynamic_agg_enable);
return 0;
}
#ifdef CONFIG_RTW_WDS
static int proc_get_wds_en(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
if (MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE))
RTW_PRINT_SEL(m, "%d\n", adapter_use_wds(adapter));
return 0;
}
static ssize_t proc_set_wds_en(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = rtw_netdev_priv(dev);
char tmp[32];
if (!(MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE)))
return -EFAULT;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
u8 enable;
int num = sscanf(tmp, "%hhu", &enable);
if (num >= 1)
adapter_set_use_wds(adapter, enable);
}
return count;
}
static ssize_t proc_set_sta_wds_en(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
u8 enable;
u8 addr[ETH_ALEN];
struct sta_info *sta;
int num = sscanf(tmp, "%hhu "MAC_SFMT, &enable, MAC_SARG(addr));
if (num != 7)
return -EINVAL;
if (IS_MCAST(addr) || _rtw_memcmp(adapter_mac_addr(adapter), addr, ETH_ALEN))
return -EINVAL;
sta = rtw_get_stainfo(&adapter->stapriv, addr);
if (!sta)
return -EINVAL;
if (enable)
sta->flags |= WLAN_STA_WDS;
else
sta->flags &= ~WLAN_STA_WDS;
}
return count;
}
static int proc_get_wds_gptr(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
if (MLME_IS_STA(adapter) && MLME_IS_ASOC(adapter))
dump_wgptr(m, adapter);
return 0;
}
#ifdef CONFIG_AP_MODE
static int proc_get_wds_path(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
if (MLME_IS_AP(adapter) && MLME_IS_ASOC(adapter))
dump_wpath(m, adapter);
return 0;
}
#endif /* CONFIG_AP_MODE */
#endif /* CONFIG_RTW_WDS */
#ifdef CONFIG_RTW_MULTI_AP
static int proc_get_multi_ap_opmode(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
if (MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE))
RTW_PRINT_SEL(m, "0x%02x\n", adapter->multi_ap);
return 0;
}
static ssize_t proc_set_multi_ap_opmode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = rtw_netdev_priv(dev);
char tmp[32];
if (!(MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE)))
return -EFAULT;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
u8 mode;
int num = sscanf(tmp, "%hhx", &mode);
if (num >= 1) {
if (MLME_IS_AP(adapter))
adapter->multi_ap = mode & (MULTI_AP_FRONTHAUL_BSS | MULTI_AP_BACKHAUL_BSS);
else
adapter->multi_ap = mode & MULTI_AP_BACKHAUL_STA;
if (adapter->multi_ap & (MULTI_AP_BACKHAUL_BSS | MULTI_AP_BACKHAUL_STA))
adapter_set_use_wds(adapter, 1);
}
}
return count;
}
static int proc_get_unassoc_sta(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
dump_unassoc_sta(m, adapter);
return 0;
}
ssize_t proc_set_unassoc_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
char tmp[17 * 10 + 32] = {0};
char cmd[32];
u8 mode;
u8 stype = 0;
u8 addr[ETH_ALEN];
#define UNASOC_STA_CMD_MODE 0
#define UNASOC_STA_CMD_ADD 1
#define UNASOC_STA_CMD_DEL 2
#define UNASOC_STA_CMD_CLR 3
#define UNASOC_STA_CMD_UNINT 4
#define UNASOC_STA_CMD_NUM 5
static const char * const unasoc_sta_cmd_str[] = {
"mode",
"add",
"del",
"clr",
"uninterest",
};
u8 cmd_id = UNASOC_STA_CMD_NUM;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
RTW_WARN(FUNC_ADPT_FMT" input string too long\n", FUNC_ADPT_ARG(adapter));
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
/*
* mode <stype>,<mode>
* add <macaddr> [<macaddr>]
* del <macaddr> [<macaddr>]
* clr
*/
char *c, *next;
int i;
u8 is_bcast;
next = tmp;
c = strsep(&next, " \t");
if (!c || sscanf(c, "%s", cmd) != 1)
goto exit;
for (i = 0; i < UNASOC_STA_CMD_NUM; i++)
if (strcmp(unasoc_sta_cmd_str[i], cmd) == 0)
cmd_id = i;
switch (cmd_id) {
case UNASOC_STA_CMD_MODE:
c = strsep(&next, " \t");
if (!c || sscanf(c, "%hhu,%hhu", &stype, &mode) != 2) {
RTW_WARN(FUNC_ADPT_FMT" invalid arguments of mode cmd\n", FUNC_ADPT_ARG(adapter));
goto exit;
}
if (stype >= UNASOC_STA_SRC_NUM) {
RTW_WARN(FUNC_ADPT_FMT" invalid stype:%u\n", FUNC_ADPT_ARG(adapter), stype);
goto exit;
}
if (mode >= UNASOC_STA_MODE_NUM) {
RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u\n", FUNC_ADPT_ARG(adapter), mode);
goto exit;
}
rtw_unassoc_sta_set_mode(adapter, stype, mode);
break;
case UNASOC_STA_CMD_ADD:
case UNASOC_STA_CMD_DEL:
case UNASOC_STA_CMD_UNINT:
/* check for macaddr list */
c = strsep(&next, " \t");
while (c != NULL) {
if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
break;
is_bcast = is_broadcast_mac_addr(addr);
if (is_bcast
|| rtw_check_invalid_mac_address(addr, 0) == _FALSE
) {
if (cmd_id == UNASOC_STA_CMD_DEL) {
if (is_bcast) {
rtw_del_unassoc_sta_queue(adapter);
break;
} else
rtw_del_unassoc_sta(adapter, addr);
} else if (cmd_id == UNASOC_STA_CMD_UNINT) {
if (is_bcast) {
rtw_undo_all_interested_unassoc_sta(adapter);
break;
} else
rtw_undo_interested_unassoc_sta(adapter, addr);
} else if (!is_bcast)
rtw_add_interested_unassoc_sta(adapter, addr);
}
c = strsep(&next, " \t");
}
break;
case UNASOC_STA_CMD_CLR:
/* clear sta list */
rtw_del_unassoc_sta_queue(adapter);
goto exit;
default:
RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"\n", FUNC_ADPT_ARG(adapter), cmd);
goto exit;
}
}
exit:
return count;
}
#ifdef CONFIG_IOCTL_CFG80211
static u8 assoc_req_mac_addr[6];
int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_AP(adapter)) {
struct sta_info *psta;
u8 *passoc_req = NULL;
u32 assoc_req_len = 0;
psta = rtw_get_stainfo(&adapter->stapriv, assoc_req_mac_addr);
if (psta == NULL) {
RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") not found\n",
FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr));
return 0;
}
RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") found\n",
FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr));
_rtw_spinlock_bh(&psta->lock);
if (psta->passoc_req && psta->assoc_req_len > 0) {
passoc_req = rtw_zmalloc(psta->assoc_req_len);
if (passoc_req) {
assoc_req_len = psta->assoc_req_len;
_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
}
}
_rtw_spinunlock_bh(&psta->lock);
if (passoc_req && assoc_req_len > IEEE80211_3ADDR_LEN) {
u8 *body = passoc_req + IEEE80211_3ADDR_LEN;
u32 body_len = assoc_req_len - IEEE80211_3ADDR_LEN;
u16 i;
for (i = 0; i < body_len; i++)
_RTW_PRINT_SEL(m, "%02X", body[i]);
_RTW_PRINT_SEL(m, "\n");
}
if (passoc_req && assoc_req_len > 0)
rtw_mfree(passoc_req, assoc_req_len);
}
return 0;
}
ssize_t proc_set_sta_assoc_req_frame_body(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[18] = {0};
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
if (sscanf(tmp, MAC_SFMT, MAC_SARG(assoc_req_mac_addr)) != 6) {
_rtw_memset(assoc_req_mac_addr, 0, 6);
RTW_PRINT(FUNC_ADPT_FMT" Invalid format\n",
FUNC_ADPT_ARG(adapter));
}
}
return count;
}
#endif /* CONFIG_IOCTL_CFG80211 */
static int proc_get_ch_util_threshold(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
RTW_PRINT_SEL(m, "%hhu\n", adapter->ch_util_threshold);
return 0;
}
static ssize_t proc_set_ch_util_threshold(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
char tmp[4];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
u8 threshold;
int num = sscanf(tmp, "%hhu", &threshold);
if (num == 1)
adapter->ch_util_threshold = threshold;
}
return count;
}
static int proc_get_ch_utilization(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
RTW_PRINT_SEL(m, "%hhu\n", rtw_get_ch_utilization(adapter));
return 0;
}
#endif /* CONFIG_RTW_MULTI_AP */
#ifdef CONFIG_RTW_MESH
static int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_mesh_peer_sel_policy(m, adapter);
return 0;
}
#if CONFIG_RTW_MESH_ACNODE_PREVENT
static int proc_get_mesh_acnode_prevent(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
dump_mesh_acnode_prevent_settings(m, adapter);
return 0;
}
static ssize_t proc_set_mesh_acnode_prevent(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
u8 enable;
u32 conf_timeout_ms;
u32 notify_timeout_ms;
int num = sscanf(tmp, "%hhu %u %u", &enable, &conf_timeout_ms, ¬ify_timeout_ms);
if (num >= 1)
peer_sel_policy->acnode_prevent = enable;
if (num >= 2)
peer_sel_policy->acnode_conf_timeout_ms = conf_timeout_ms;
if (num >= 3)
peer_sel_policy->acnode_notify_timeout_ms = notify_timeout_ms;
}
return count;
}
#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
#if CONFIG_RTW_MESH_OFFCH_CAND
static int proc_get_mesh_offch_cand(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
dump_mesh_offch_cand_settings(m, adapter);
return 0;
}
static ssize_t proc_set_mesh_offch_cand(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
u8 enable;
u32 find_int_ms;
int num = sscanf(tmp, "%hhu %u", &enable, &find_int_ms);
if (num >= 1)
peer_sel_policy->offch_cand = enable;
if (num >= 2)
peer_sel_policy->offch_find_int_ms = find_int_ms;
}
return count;
}
#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
#if CONFIG_RTW_MESH_PEER_BLACKLIST
static int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter)) {
dump_mesh_peer_blacklist_settings(m, adapter);
if (MLME_IS_ASOC(adapter))
dump_mesh_peer_blacklist(m, adapter);
}
return 0;
}
static ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
u32 conf_timeout_ms;
u32 blacklist_timeout_ms;
int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
if (num >= 1)
peer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms;
if (num >= 2)
peer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms;
}
return count;
}
#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
static int proc_get_mesh_cto_mgate_require(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
RTW_PRINT_SEL(m, "%u\n", adapter->mesh_cfg.peer_sel_policy.cto_mgate_require);
return 0;
}
static ssize_t proc_set_mesh_cto_mgate_require(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
u8 require;
int num = sscanf(tmp, "%hhu", &require);
if (num >= 1) {
peer_sel_policy->cto_mgate_require = require;
#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
if (rtw_mesh_cto_mgate_required(adapter))
rtw_netif_carrier_off(adapter->pnetdev);
else
rtw_netif_carrier_on(adapter->pnetdev);
#endif
}
}
return count;
}
static int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter)) {
dump_mesh_cto_mgate_blacklist_settings(m, adapter);
if (MLME_IS_ASOC(adapter))
dump_mesh_cto_mgate_blacklist(m, adapter);
}
return 0;
}
static ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
u32 conf_timeout_ms;
u32 blacklist_timeout_ms;
int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
if (num >= 1)
peer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms;
if (num >= 2)
peer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms;
}
return count;
}
#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
static int proc_get_mesh_networks(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
dump_mesh_networks(m, adapter);
return 0;
}
static int proc_get_mesh_plink_ctl(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
dump_mesh_plink_ctl(m, adapter);
return 0;
}
static int proc_get_mesh_mpath(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
dump_mpath(m, adapter);
return 0;
}
static int proc_get_mesh_mpp(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
dump_mpp(m, adapter);
return 0;
}
static int proc_get_mesh_known_gates(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
dump_known_gates(m, adapter);
return 0;
}
#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
static int proc_get_mesh_b2u_flags(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
dump_mesh_b2u_flags(m, adapter);
return 0;
}
static ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
u8 msrc, mfwd;
int num = sscanf(tmp, "%hhx %hhx", &msrc, &mfwd);
if (num >= 1)
mcfg->b2u_flags_msrc = msrc;
if (num >= 2)
mcfg->b2u_flags_mfwd = mfwd;
}
return count;
}
#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
static int proc_get_mesh_stats(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
dump_mesh_stats(m, adapter);
return 0;
}
static int proc_get_mesh_gate_timeout(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
if (MLME_IS_MESH(adapter))
RTW_PRINT_SEL(m, "%u factor\n",
adapter->mesh_cfg.path_gate_timeout_factor);
return 0;
}
static ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
u32 timeout;
int num = sscanf(tmp, "%u", &timeout);
if (num < 1)
goto exit;
mcfg->path_gate_timeout_factor = timeout;
}
exit:
return count;
}
static int proc_get_mesh_gate_state(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
u8 cto_mgate = 0;
if (MLME_IS_MESH(adapter)) {
if (rtw_mesh_is_primary_gate(adapter))
RTW_PRINT_SEL(m, "PG\n");
else if (mcfg->dot11MeshGateAnnouncementProtocol)
RTW_PRINT_SEL(m, "G\n");
else if (rtw_mesh_gate_num(adapter))
RTW_PRINT_SEL(m, "C\n");
else
RTW_PRINT_SEL(m, "N\n");
}
return 0;
}
static int proc_get_peer_alive_based_preq(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter= (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *rp = &adapter->registrypriv;
RTW_PRINT_SEL(m, "peer_alive_based_preq = %u\n",
rp->peer_alive_based_preq);
return 0;
}
static ssize_t
proc_set_peer_alive_based_preq(struct file *file, const char __user *buffer,
size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *rp = &adapter->registrypriv;
char tmp[8];
int num = 0;
u8 enable = 0;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%hhu", &enable);
if (num != 1) {
RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
goto exit;
}
if (enable > 1) {
RTW_ERR("%s: invalid value!\n", __FUNCTION__);
goto exit;
}
rp->peer_alive_based_preq = enable;
exit:
return count;
}
#endif /* CONFIG_RTW_MESH */
#ifdef RTW_BUSY_DENY_SCAN
static int proc_get_scan_interval_thr(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter= (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *rp = &adapter->registrypriv;
RTW_PRINT_SEL(m, "scan interval threshold = %u ms\n",
rp->scan_interval_thr);
return 0;
}
static ssize_t proc_set_scan_interval_thr(struct file *file,
const char __user *buffer,
size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter= (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *rp = &adapter->registrypriv;
char tmp[12];
int num = 0;
u32 thr = 0;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%u", &thr);
if (num != 1) {
RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
goto exit;
}
rp->scan_interval_thr = thr;
RTW_PRINT("%s: scan interval threshold = %u ms\n",
__FUNCTION__, rp->scan_interval_thr);
exit:
return count;
}
#endif /* RTW_BUSY_DENY_SCAN */
static int proc_get_scan_deny(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter= (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
RTW_PRINT_SEL(m, "scan_deny is %s\n", (dvobj->scan_deny == _TRUE) ? "enable":"disable");
return 0;
}
static ssize_t proc_set_scan_deny(struct file *file, const char __user *buffer,
size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
char tmp[8];
int num = 0;
int enable = 0;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (!buffer || copy_from_user(tmp, buffer, count))
goto exit;
num = sscanf(tmp, "%d", &enable);
if (num != 1) {
RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
goto exit;
}
dvobj->scan_deny = enable ? _TRUE : _FALSE;
RTW_PRINT("%s: scan_deny is %s\n",
__FUNCTION__, (dvobj->scan_deny == _TRUE) ? "enable":"disable");
exit:
return count;
}
int proc_get_cur_beacon_keys(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = rtw_netdev_priv(dev);
struct mlme_priv *mlme = &adapter->mlmepriv;
rtw_dump_bcn_keys(m, &mlme->cur_beacon_keys);
return 0;
}
#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P)
static int proc_get_go_hidden_ssid_mode(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregpriv = &padapter->registrypriv;
if (pregpriv)
RTW_PRINT_SEL(m, "0x%lx\n", pregpriv->go_hidden_ssid_mode);
return 0;
}
static ssize_t proc_set_go_hidden_ssid_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregpriv = &padapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
char tmp[32];
int go_hidden_ssid_mode, feature_bit;
if (!padapter)
return -EFAULT;
if (count < 1) {
RTW_INFO("argument size is less than 1\n");
return -EFAULT;
}
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d %d",&feature_bit, &go_hidden_ssid_mode);
if (num < 1)
return -EINVAL;
/* Cancel hide_ssid_timer and reset flag when unhide SSID by proc */
if (!feature_bit && !go_hidden_ssid_mode) {
ATOMIC_SET(&pregpriv->set_hide_ssid_timer, 0);
_cancel_timer_ex(&pmlmeext->hide_ssid_timer);
}
if (go_hidden_ssid_mode == 1)
rtw_set_bit(feature_bit, &pregpriv->go_hidden_ssid_mode);
else if (!go_hidden_ssid_mode)
rtw_clear_bit(feature_bit, &pregpriv->go_hidden_ssid_mode);
else
return -EFAULT;
RTW_INFO("go_hidden_ssid_mode:0x%lx\n", pregpriv->go_hidden_ssid_mode);
} else
return -EFAULT;
issue_beacon(padapter, 0);
return count;
}
#endif
static int proc_get_amsdu_mode(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregpriv = &padapter->registrypriv;
if (pregpriv) {
if (pregpriv->amsdu_mode == RTW_AMSDU_MODE_NON_SPP)
RTW_PRINT_SEL(m, "amsdu mode: NON-SPP\n");
else if (pregpriv->amsdu_mode == RTW_AMSDU_MODE_SPP)
RTW_PRINT_SEL(m, "amsdu mode: SPP\n");
else if (pregpriv->amsdu_mode == RTW_AMSDU_MODE_ALL_DROP)
RTW_PRINT_SEL(m, "amsdu mode: ALL DROP\n");
else
RTW_PRINT_SEL(m, "unexpected amsdu mode\n");
}
return 0;
}
static ssize_t proc_set_amsdu_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct registry_priv *pregpriv = &padapter->registrypriv;
char tmp[32];
u32 mode;
u8 bw_2g;
u8 bw_5g;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%d", &mode);
if (mode == RTW_AMSDU_MODE_NON_SPP
|| mode == RTW_AMSDU_MODE_SPP
|| mode == RTW_AMSDU_MODE_ALL_DROP) {
pregpriv->amsdu_mode = mode;
RTW_INFO("amsdu mode=%u\n", mode);
} else {
RTW_INFO("set unexpected mode = %d, won't apply\n", mode);
}
}
return count;
}
#ifdef ROKU_PRIVATE
static int proc_get_vendor_ie_filter(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_priv *mlmepriv = &adapter->mlmepriv;
int i, j;
if (!mlmepriv)
return -EFAULT;
RTW_PRINT_SEL(m, "enable: %u\n", mlmepriv->vendor_ie_filter_enable);
RTW_PRINT_SEL(m, "index\tcontent\n");
for (i = 0; i < MAX_VENDOR_IE_NUM; i++) {
RTW_PRINT_SEL(m, "%d\t", i);
if (mlmepriv->vendor_ie_len[i])
for (j = 0; j < mlmepriv->vendor_ie_len[i] + 2; j++)
RTW_PRINT_SEL(m, "%02x", mlmepriv->vendor_ie_filter[i][j]);
RTW_PRINT_SEL(m, "\n");
}
return 0;
}
static ssize_t proc_set_vendor_ie_filter(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_priv *mlmepriv = &adapter->mlmepriv;
char tmp[MAX_VENDOR_IE_PARAM_LEN];
u8 vendor_ie_num = 0;
u8 *vendor_ie;
u8 enable;
int num, i, len = 0;
vendor_ie = rtw_malloc(MAX_VENDOR_IE_LEN);
if (!vendor_ie || !adapter)
return -EFAULT;
if (count < 1) {
RTW_INFO("argument size is less than 1\n");
return -EFAULT;
}
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
if (count > 2) {
num = sscanf(tmp, "%hhu %s", &vendor_ie_num, vendor_ie);
if (num < 1)
return -EINVAL;
if (vendor_ie_num > MAX_VENDOR_IE_NUM - 1)
return -EINVAL;
if (_rtw_memcmp(vendor_ie, "0", 1)) {
_rtw_memset(mlmepriv->vendor_ie_filter[vendor_ie_num] , 0 , MAX_VENDOR_IE_LEN);
mlmepriv->vendor_ie_len[vendor_ie_num] = 0;
}
for (i = 0; i < strlen(vendor_ie); i += 2) {
mlmepriv->vendor_ie_filter[vendor_ie_num][len] = key_2char2num(vendor_ie[i], vendor_ie[i+1]);
if (len == 1)
mlmepriv->vendor_ie_len[vendor_ie_num] = mlmepriv->vendor_ie_filter[vendor_ie_num][len];
len++;
}
rtw_mfree(vendor_ie, MAX_VENDOR_IE_LEN);
} else if (count == 2) {
num = sscanf(tmp, "%hhu", &mlmepriv->vendor_ie_filter_enable);
} else {
RTW_INFO("argument size is wrong\n");
return -EINVAL;
}
} else {
return -EFAULT;
}
return count;
}
#endif
/*
* rtw_adapter_proc:
* init/deinit when register/unregister net_device
*/
const struct rtw_proc_hdl adapter_proc_hdls[] = {
#if RTW_SEQ_FILE_TEST
RTW_PROC_HDL_SEQ("seq_file_test", &seq_file_test, NULL),
#endif
RTW_PROC_HDL_SSEQ("write_reg", NULL, proc_set_write_reg),
RTW_PROC_HDL_SSEQ("read_reg", proc_get_read_reg, proc_set_read_reg),
RTW_PROC_HDL_SSEQ("mac_dbg_status_dump", NULL, proc_set_mac_dbg_status_dump),
RTW_PROC_HDL_SSEQ("tx_rate_bmp", proc_get_dump_tx_rate_bmp, NULL),
RTW_PROC_HDL_SSEQ("adapters_status", proc_get_dump_adapters_status, NULL),
#ifdef CONFIG_RTW_CUSTOMER_STR
RTW_PROC_HDL_SSEQ("customer_str", proc_get_customer_str, NULL),
#endif
RTW_PROC_HDL_SSEQ("fwstate", proc_get_fwstate, NULL),
RTW_PROC_HDL_SSEQ("sec_info", proc_get_sec_info, NULL),
RTW_PROC_HDL_SSEQ("mlmext_state", proc_get_mlmext_state, NULL),
RTW_PROC_HDL_SSEQ("qos_option", proc_get_qos_option, NULL),
RTW_PROC_HDL_SSEQ("ht_option", proc_get_ht_option, NULL),
RTW_PROC_HDL_SSEQ("rf_info", proc_get_rf_info, NULL),
RTW_PROC_HDL_SSEQ("scan_param", proc_get_scan_param, proc_set_scan_param),
RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, proc_set_scan_abort),
#ifdef CONFIG_SCAN_BACKOP
RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta),
#ifdef CONFIG_AP_MODE
RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap),
#endif
#ifdef CONFIG_RTW_MESH
RTW_PROC_HDL_SSEQ("backop_flags_mesh", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh),
#endif
#endif
RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info),
RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL),
#ifdef ROKU_PRIVATE
RTW_PROC_HDL_SSEQ("infra_ap", proc_get_infra_ap, NULL),
#endif /* ROKU_PRIVATE */
RTW_PROC_HDL_SSEQ("trx_info", proc_get_trx_info, proc_reset_trx_info),
RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset),
RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl),
RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl),
RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL),
/*RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL), */
/* RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL), */
RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam),
RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL),
#ifdef CONFIG_DBG_AX_CAM
RTW_PROC_HDL_SSEQ("dump_ax_valid_key", proc_get_ax_valid_key, NULL),
RTW_PROC_HDL_SSEQ("dump_ax_address_cam", proc_get_ax_address_cam, NULL),
RTW_PROC_HDL_SSEQ("dump_ax_security_cam", proc_get_ax_sec_cam, NULL),
#endif
RTW_PROC_HDL_SSEQ("ps_dbg_info", proc_get_ps_dbg_info, proc_set_ps_dbg_info),
RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL),
#ifdef CONFIG_LAYER2_ROAMING
RTW_PROC_HDL_SSEQ("roam_flags", proc_get_roam_flags, proc_set_roam_flags),
RTW_PROC_HDL_SSEQ("roam_param", proc_get_roam_param, proc_set_roam_param),
RTW_PROC_HDL_SSEQ("roam_tgt_addr", NULL, proc_set_roam_tgt_addr),
#endif /* CONFIG_LAYER2_ROAMING */
#ifdef CONFIG_RTW_MBO
RTW_PROC_HDL_SSEQ("non_pref_ch", rtw_mbo_proc_non_pref_chans_get, rtw_mbo_proc_non_pref_chans_set),
RTW_PROC_HDL_SSEQ("cell_data", rtw_mbo_proc_cell_data_get, rtw_mbo_proc_cell_data_set),
RTW_PROC_HDL_SSEQ("mbo_attr", rtw_mbo_proc_attr_get, rtw_mbo_proc_attr_set),
#endif
#ifdef CONFIG_RTW_80211R
RTW_PROC_HDL_SSEQ("ft_flags", rtw_ft_proc_flags_get, rtw_ft_proc_flags_set),
#endif
RTW_PROC_HDL_SSEQ("defs_param", proc_get_defs_param, proc_set_defs_param),
#ifdef CONFIG_SDIO_HCI
RTW_PROC_HDL_SSEQ("sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL),
RTW_PROC_HDL_SSEQ("sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL),
RTW_PROC_HDL_SSEQ("sdio_card_info", proc_get_sdio_card_info, NULL),
#ifdef DBG_SDIO
RTW_PROC_HDL_SSEQ("sdio_dbg", proc_get_sdio_dbg, proc_set_sdio_dbg),
#endif /* DBG_SDIO */
#endif /* CONFIG_SDIO_HCI */
RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case),
RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty),
RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test),
#ifdef CONFIG_AP_MODE
RTW_PROC_HDL_SSEQ("ap_linking_test", NULL, proc_set_ap_linking_test),
#endif
RTW_PROC_HDL_SSEQ("mac_reg_dump", proc_get_mac_reg_dump, NULL),
RTW_PROC_HDL_SSEQ("bb_reg_dump", proc_get_bb_reg_dump, NULL),
RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL),
RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL),
#if 0
RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config),
#endif
#ifdef CONFIG_AP_MODE
RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status),
RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL),
RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate),
#if CONFIG_RTW_AP_DATA_BMC_TO_UC
RTW_PROC_HDL_SSEQ("ap_b2u_flags", proc_get_ap_b2u_flags, proc_set_ap_b2u_flags),
#endif
#endif /* CONFIG_AP_MODE */
#ifdef DBG_MEMORY_LEAK
RTW_PROC_HDL_SSEQ("_malloc_cnt", proc_get_malloc_cnt, NULL),
#endif /* DBG_MEMORY_LEAK */
#ifdef CONFIG_FIND_BEST_CHANNEL
RTW_PROC_HDL_SSEQ("best_channel", proc_get_best_channel, proc_set_best_channel),
#endif
RTW_PROC_HDL_SSEQ("rx_signal", proc_get_rx_signal, proc_set_rx_signal),
RTW_PROC_HDL_SSEQ("rx_chk_limit", proc_get_rx_chk_limit, proc_set_rx_chk_limit),
RTW_PROC_HDL_SSEQ("hw_info", proc_get_hw_status, proc_set_hw_status),
RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL),
#ifdef CONFIG_80211N_HT
RTW_PROC_HDL_SSEQ("ht_enable", proc_get_ht_enable, proc_set_ht_enable),
RTW_PROC_HDL_SSEQ("bw_mode", proc_get_bw_mode, proc_set_bw_mode),
RTW_PROC_HDL_SSEQ("ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable),
RTW_PROC_HDL_SSEQ("rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu),
RTW_PROC_HDL_SSEQ("rx_ampdu_size_limit", proc_get_rx_ampdu_size_limit, proc_set_rx_ampdu_size_limit),
RTW_PROC_HDL_SSEQ("rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor),
RTW_PROC_HDL_SSEQ("rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density),
RTW_PROC_HDL_SSEQ("tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density),
RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num),
RTW_PROC_HDL_SSEQ("tx_quick_addba_req", proc_get_tx_quick_addba_req, proc_set_tx_quick_addba_req),
#ifdef CONFIG_TX_AMSDU
RTW_PROC_HDL_SSEQ("tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu),
RTW_PROC_HDL_SSEQ("tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate),
#endif
#endif /* CONFIG_80211N_HT */
#ifdef CONFIG_80211AC_VHT
RTW_PROC_HDL_SSEQ("vht_24g_enable", proc_get_vht_24g_enable, proc_set_vht_24g_enable),
#endif /* CONFIG_80211AC_VHT */
RTW_PROC_HDL_SSEQ("dynamic_rrsr", proc_get_dyn_rrsr, proc_set_dyn_rrsr),
RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps),
/* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL),
* RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */
#ifdef CONFIG_BTC
RTW_PROC_HDL_SSEQ("btc_dbg", proc_get_btc_dbg, proc_set_btc_dbg),
RTW_PROC_HDL_SSEQ("btc", proc_get_btc_info, NULL),
RTW_PROC_HDL_SSEQ("btreg_read", proc_get_btreg_read, proc_set_btreg_read),
RTW_PROC_HDL_SSEQ("btreg_write", proc_get_btreg_write, proc_set_btreg_write),
#endif /* CONFIG_BTC */
#if defined(DBG_CONFIG_ERROR_DETECT)
RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset),
#endif /* DBG_CONFIG_ERROR_DETECT */
RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL),
#ifdef CONFIG_HUAWEI_PROC
RTW_PROC_HDL_SSEQ("huawei_trx_info", proc_get_huawei_trx_info, NULL),
#endif
RTW_PROC_HDL_SSEQ("rtw_hal_linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump),
RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump),
RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL),
RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl),
RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL),
RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg),
#ifdef ROKU_PRIVATE
RTW_PROC_HDL_SSEQ("roku_trx_info_msg", proc_get_roku_trx_info_msg, NULL),
#endif
#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)
RTW_PROC_HDL_SSEQ("lps_pg_debug", proc_get_lps_pg_debug, NULL),
#endif
#ifdef CONFIG_GPIO_API
RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio),
RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value),
RTW_PROC_HDL_SSEQ("gpio_set_direction", NULL, proc_set_config_gpio),
#endif
#ifdef CONFIG_DBG_COUNTER
RTW_PROC_HDL_SSEQ("rx_logs", proc_get_rx_logs, NULL),
RTW_PROC_HDL_SSEQ("tx_logs", proc_get_tx_logs, NULL),
RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL),
#endif
#ifdef CONFIG_DBG_RF_CAL
RTW_PROC_HDL_SSEQ("iqk", proc_get_iqk_info, proc_set_iqk),
RTW_PROC_HDL_SSEQ("lck", proc_get_lck_info, proc_set_lck),
#endif
#ifdef CONFIG_PCI_HCI
RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL),
RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL),
#ifdef DBG_TXBD_DESC_DUMP
RTW_PROC_HDL_SSEQ("tx_ring_ext", proc_get_tx_ring_ext, proc_set_tx_ring_ext),
#endif
RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL),
RTW_PROC_HDL_SSEQ("pci_conf_space", proc_get_pci_conf_space, proc_set_pci_conf_space),
RTW_PROC_HDL_SSEQ("pci_bridge_conf_space", proc_get_pci_bridge_conf_space, proc_set_pci_bridge_conf_space),
#endif
#ifdef CONFIG_WOWLAN
RTW_PROC_HDL_SSEQ("wow_enable", proc_get_wow_enable, proc_set_wow_enable),
RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info),
RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event,
proc_set_wakeup_event),
RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL),
RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL),
#endif
#ifdef CONFIG_GPIO_WAKEUP
RTW_PROC_HDL_SSEQ("wowlan_gpio_info", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info),
#endif
#ifdef CONFIG_P2P_WOWLAN
RTW_PROC_HDL_SSEQ("p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL),
#endif
RTW_PROC_HDL_SSEQ("country_code", proc_get_country_code, proc_set_country_code),
RTW_PROC_HDL_SSEQ("chan_plan", proc_get_chan_plan, proc_set_chan_plan),
RTW_PROC_HDL_SSEQ("cap_spt_op_class_ch", proc_get_cap_spt_op_class_ch, proc_set_cap_spt_op_class_ch),
RTW_PROC_HDL_SSEQ("reg_spt_op_class_ch", proc_get_reg_spt_op_class_ch, proc_set_reg_spt_op_class_ch),
RTW_PROC_HDL_SSEQ("cur_spt_op_class_ch", proc_get_cur_spt_op_class_ch, proc_set_cur_spt_op_class_ch),
#if CONFIG_RTW_MACADDR_ACL
RTW_PROC_HDL_SSEQ("macaddr_acl", proc_get_macaddr_acl, proc_set_macaddr_acl),
#endif
#if CONFIG_RTW_PRE_LINK_STA
RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta),
#endif
RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy),
#ifdef CONFIG_80211D
RTW_PROC_HDL_SSEQ("country_ie_slave_en_conds", proc_get_country_ie_slave_en_conds, proc_set_country_ie_slave_en_conds),
RTW_PROC_HDL_SSEQ("country_ie_slave_records", proc_get_country_ie_slave_records, NULL),
#endif
#ifdef CONFIG_DFS_MASTER
RTW_PROC_HDL_SSEQ("dfs_test_case", proc_get_dfs_test_case, proc_set_dfs_test_case),
RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp),
RTW_PROC_HDL_SSEQ("radar_detect", NULL, proc_set_radar_detect),
RTW_PROC_HDL_SSEQ("dfs_ch_sel_e_flags", proc_get_dfs_ch_sel_e_flags, proc_set_dfs_ch_sel_e_flags),
RTW_PROC_HDL_SSEQ("dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags),
#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
RTW_PROC_HDL_SSEQ("dfs_slave_with_rd", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd),
#endif
#endif
RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport),
#ifdef DBG_RX_COUNTER_DUMP
RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump),
#endif
RTW_PROC_HDL_SSEQ("change_bss_chbw", NULL, proc_set_change_bss_chbw),
RTW_PROC_HDL_SSEQ("tx_bw_mode", proc_get_tx_bw_mode, proc_set_tx_bw_mode),
RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL),
RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL),
#if CONFIG_TXPWR_LIMIT
RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL),
#endif
RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info),
#ifdef GEORGIA_TODO_TX_PWR
RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, NULL),
RTW_PROC_HDL_SEQ("txpwr_total_dbm", &seq_ops_txpwr_total_dbm, NULL),
#endif
#ifdef CONFIG_POWER_SAVING
RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, proc_set_ps_info),
#ifdef CONFIG_WMMPS_STA
RTW_PROC_HDL_SSEQ("wmmps_info", proc_get_wmmps_info, proc_set_wmmps_info),
#endif /* CONFIG_WMMPS_STA */
#endif
#ifdef CONFIG_TDLS
RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL),
RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable),
#endif
RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor),
#ifdef CONFIG_RTW_ACS
#ifdef WKARD_ACS
RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs),
RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL),
#endif
#endif
RTW_PROC_HDL_SSEQ("env_info", proc_get_env_rpt, NULL),
RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL),
RTW_PROC_HDL_SSEQ("hal_trx_mode", proc_get_hal_trx_mode, NULL),
RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL),
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL),
#endif
RTW_PROC_HDL_SSEQ("efuse_map", proc_get_efuse_map, NULL),
#ifdef CONFIG_IEEE80211W
RTW_PROC_HDL_SSEQ("11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query),
RTW_PROC_HDL_SSEQ("11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth),
RTW_PROC_HDL_SSEQ("11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth),
#endif /* CONFIG_IEEE80211W */
RTW_PROC_HDL_SSEQ("mac_addr", proc_get_mac_addr, NULL),
RTW_PROC_HDL_SSEQ("skip_band", proc_get_skip_band, proc_set_skip_band),
RTW_PROC_HDL_SSEQ("rx_stat", proc_get_rx_stat, NULL),
RTW_PROC_HDL_SSEQ("tx_stat", proc_get_tx_stat, NULL),
/**** PHY Capability ****/
RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL),
#ifdef CONFIG_80211N_HT
RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap),
RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap),
#endif /* CONFIG_80211N_HT */
#ifdef CONFIG_BEAMFORMING
RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap),
#endif
RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL),
#ifdef CONFIG_RTW_NAPI_DYNAMIC
RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th),
#endif /* CONFIG_RTW_NAPI_DYNAMIC */
RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info),
#ifdef CONFIG_SUPPORT_FIFO_DUMP
RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info),
#endif
#ifdef CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST
RTW_PROC_HDL_SSEQ("ignore_go_and_low_rssi_in_scan",
proc_get_ignore_go_and_low_rssi_in_scan,
proc_set_ignore_go_and_low_rssi_in_scan),
#endif /*CONFIG_IGNORE_GO_AND_LOW_RSSI_IN_SCAN_LIST*/
#ifdef DBG_XMIT_BLOCK
RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block),
#endif
RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout),
RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable),
RTW_PROC_HDL_SSEQ("fw_offload", proc_get_fw_offload, proc_set_fw_offload),
#ifdef CONFIG_RTW_WDS
RTW_PROC_HDL_SSEQ("wds_en", proc_get_wds_en, proc_set_wds_en),
RTW_PROC_HDL_SSEQ("sta_wds_en", NULL, proc_set_sta_wds_en),
RTW_PROC_HDL_SSEQ("wds_gptr", proc_get_wds_gptr, NULL),
#ifdef CONFIG_AP_MODE
RTW_PROC_HDL_SSEQ("wds_path", proc_get_wds_path, NULL),
#endif
#endif
#ifdef CONFIG_RTW_MULTI_AP
RTW_PROC_HDL_SSEQ("multi_ap_opmode", proc_get_multi_ap_opmode, proc_set_multi_ap_opmode),
RTW_PROC_HDL_SSEQ("unassoc_sta", proc_get_unassoc_sta, proc_set_unassoc_sta),
#ifdef CONFIG_IOCTL_CFG80211
RTW_PROC_HDL_SSEQ("sta_assoc_req_frame_body", proc_get_sta_assoc_req_frame_body, proc_set_sta_assoc_req_frame_body),
#endif
RTW_PROC_HDL_SSEQ("ch_util_threshold", proc_get_ch_util_threshold, proc_set_ch_util_threshold),
RTW_PROC_HDL_SSEQ("ch_utilization", proc_get_ch_utilization, NULL),
#endif
#ifdef CONFIG_RTW_MESH
#if CONFIG_RTW_MESH_ACNODE_PREVENT
RTW_PROC_HDL_SSEQ("mesh_acnode_prevent", proc_get_mesh_acnode_prevent, proc_set_mesh_acnode_prevent),
#endif
#if CONFIG_RTW_MESH_OFFCH_CAND
RTW_PROC_HDL_SSEQ("mesh_offch_cand", proc_get_mesh_offch_cand, proc_set_mesh_offch_cand),
#endif
#if CONFIG_RTW_MESH_PEER_BLACKLIST
RTW_PROC_HDL_SSEQ("mesh_peer_blacklist", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist),
#endif
#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
RTW_PROC_HDL_SSEQ("mesh_cto_mgate_require", proc_get_mesh_cto_mgate_require, proc_set_mesh_cto_mgate_require),
RTW_PROC_HDL_SSEQ("mesh_cto_mgate_blacklist", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist),
#endif
RTW_PROC_HDL_SSEQ("mesh_peer_sel_policy", proc_get_mesh_peer_sel_policy, NULL),
RTW_PROC_HDL_SSEQ("mesh_networks", proc_get_mesh_networks, NULL),
RTW_PROC_HDL_SSEQ("mesh_plink_ctl", proc_get_mesh_plink_ctl, NULL),
RTW_PROC_HDL_SSEQ("mesh_mpath", proc_get_mesh_mpath, NULL),
RTW_PROC_HDL_SSEQ("mesh_mpp", proc_get_mesh_mpp, NULL),
RTW_PROC_HDL_SSEQ("mesh_known_gates", proc_get_mesh_known_gates, NULL),
#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
RTW_PROC_HDL_SSEQ("mesh_b2u_flags", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags),
#endif
RTW_PROC_HDL_SSEQ("mesh_stats", proc_get_mesh_stats, NULL),
RTW_PROC_HDL_SSEQ("mesh_gate_timeout_factor", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout),
RTW_PROC_HDL_SSEQ("mesh_gate_state", proc_get_mesh_gate_state, NULL),
RTW_PROC_HDL_SSEQ("mesh_peer_alive_based_preq", proc_get_peer_alive_based_preq, proc_set_peer_alive_based_preq),
#endif
#ifdef CONFIG_LPS_CHK_BY_TP
RTW_PROC_HDL_SSEQ("lps_chk_tp", proc_get_lps_chk_tp, proc_set_lps_chk_tp),
#endif
#ifdef CONFIG_SUPPORT_STATIC_SMPS
RTW_PROC_HDL_SSEQ("smps", proc_get_smps, proc_set_smps),
#endif
#ifdef RTW_BUSY_DENY_SCAN
RTW_PROC_HDL_SSEQ("scan_interval_thr", proc_get_scan_interval_thr, \
proc_set_scan_interval_thr),
#endif
RTW_PROC_HDL_SSEQ("scan_deny", proc_get_scan_deny, proc_set_scan_deny),
#ifdef CONFIG_CTRL_TXSS_BY_TP
RTW_PROC_HDL_SSEQ("txss_tp", proc_get_txss_tp, proc_set_txss_tp),
#ifdef DBG_CTRL_TXSS
RTW_PROC_HDL_SSEQ("txss_ctrl", proc_get_txss_ctrl, proc_set_txss_ctrl),
#endif
#endif
RTW_PROC_HDL_SSEQ("cur_beacon_keys", proc_get_cur_beacon_keys, NULL),
RTW_PROC_HDL_SSEQ("chan", proc_get_chan, proc_set_chan),
RTW_PROC_HDL_SSEQ("mr_test", proc_get_mr_test, proc_set_mr_test),
RTW_PROC_HDL_SSEQ("deny_legacy", proc_get_deny_legacy, proc_set_deny_legacy),
#if defined(ROKU_PRIVATE) && defined(CONFIG_P2P)
RTW_PROC_HDL_SSEQ("go_hidden_ssid_mode", proc_get_go_hidden_ssid_mode, proc_set_go_hidden_ssid_mode),
#endif
RTW_PROC_HDL_SSEQ("rtw_amsdu_mode", proc_get_amsdu_mode, proc_set_amsdu_mode),
#ifdef CONFIG_80211AX_HE
RTW_PROC_HDL_SSEQ("tx_ul_mu_disable", proc_get_tx_ul_mu_disable, proc_set_tx_ul_mu_disable),
#endif
#ifdef ROKU_PRIVATE
RTW_PROC_HDL_SSEQ("vendor_ie_filter", proc_get_vendor_ie_filter, proc_set_vendor_ie_filter),
#endif
};
const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl);
static int rtw_adapter_proc_open(struct inode *inode, struct file *file)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
ssize_t index = (ssize_t)PDE_DATA(inode);
#else
ssize_t index = (ssize_t)pde_data(inode);
#endif
const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
void *private = proc_get_parent_data(inode);
if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
int res = seq_open(file, hdl->u.seq_op);
if (res == 0)
((struct seq_file *)file->private_data)->private = private;
return res;
} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
return single_open(file, show, private);
} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
return single_open_size(file, show, private, hdl->u.sz.size);
#else
return single_open(file, show, private);
#endif
} else {
return -EROFS;
}
}
static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
#else
ssize_t index = (ssize_t)pde_data(file_inode(file));
#endif
const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
if (write)
return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
return -EROFS;
}
static const struct rtw_proc_ops rtw_adapter_proc_seq_fops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
.proc_open = rtw_adapter_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = seq_release,
.proc_write = rtw_adapter_proc_write,
#else
.owner = THIS_MODULE,
.open = rtw_adapter_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
.write = rtw_adapter_proc_write,
#endif
};
static const struct rtw_proc_ops rtw_adapter_proc_sseq_fops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
.proc_open = rtw_adapter_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = seq_release,
.proc_write = rtw_adapter_proc_write,
#else
.owner = THIS_MODULE,
.open = rtw_adapter_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.write = rtw_adapter_proc_write,
#endif
};
int proc_get_phy_adaptivity(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
rtw_cfg_adaptivity_config_msg(m, padapter);
rtw_hal_phy_adaptivity_parm_msg(m, padapter);
return 0;
}
ssize_t proc_set_phy_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u32 th_l2h_ini;
s8 th_edcca_hl_diff;
if (count < 1)
return -EFAULT;
if (count > sizeof(tmp)) {
rtw_warn_on(1);
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%x %hhd", &th_l2h_ini, &th_edcca_hl_diff);
if (num != 2)
return count;
rtw_hal_phy_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff);
}
return count;
}
static char *phydm_msg = NULL;
#define PHYDM_MSG_LEN 80*24*4
static int proc_get_phydm_cmd(struct seq_file *m, void *v)
{
struct net_device *netdev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(netdev);
if (NULL == phydm_msg) {
_RTW_PRINT_SEL(m, "(Nothing to output)\n");
return 0;
#if 0
phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
if (NULL == phydm_msg)
return -ENOMEM;
phydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN);
#endif
}
_RTW_PRINT_SEL(m, "%s\n", phydm_msg);
rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
phydm_msg = NULL;
return 0;
}
static int proc_get_phl_cmd(struct seq_file *m, void *v)
{
return proc_get_phydm_cmd(m, v);
}
static ssize_t proc_set_phydm_cmd(struct file *file, char *buffer, size_t count,
loff_t *pos, void *data,
enum rtw_proc_cmd_type type)
{
struct net_device *netdev = (struct net_device *)data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(netdev);
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct rtw_proc_cmd cmd;
if (count < 1)
return -EFAULT;
if (buffer) {
if (NULL == phydm_msg) {
phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
if (NULL == phydm_msg)
return -ENOMEM;
} else
_rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN);
cmd.in_type = RTW_ARG_TYPE_BUF;
cmd.in_cnt_len = count;
cmd.in.buf = buffer;
rtw_phl_proc_cmd(GET_PHL_INFO(dvobj), type, &cmd, phydm_msg, PHYDM_MSG_LEN);
if (strlen(phydm_msg) == 0) {
rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
phydm_msg = NULL;
}
}
return count;
}
static ssize_t proc_set_phl_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
char *buf, *p;
enum rtw_proc_cmd_type type;
ssize_t ret, len;
int type_len;
buf = _rtw_malloc(count + 1);
if (!buf)
return -ENOMEM;
if (copy_from_user(buf, buffer, count)) {
ret = -EFAULT;
goto err;
}
if (strncmp(buf, "bb ", 3) == 0) {
type = RTW_PROC_CMD_BB;
type_len = 3;
} else if (strncmp(buf, "rf ", 3) == 0) {
type = RTW_PROC_CMD_RF;
type_len = 3;
} else if (strncmp(buf, "mac ", 4) == 0) {
type = RTW_PROC_CMD_MAC;
type_len = 4;
} else if (strncmp(buf, "phl ", 4) == 0) {
type = RTW_PROC_CMD_PHL;
type_len = 4;
} else if (strncmp(buf, "core ", 5) == 0) {
printk("%s(%d)\n",__func__,__LINE__);
type = RTW_PROC_CMD_CORE;
type_len = 5;
} else if (strncmp(buf, "btc ", 4) == 0) {
printk("%s(%d)\n",__func__,__LINE__);
type = RTW_PROC_CMD_BTC;
type_len = 4;
} else if (strncmp(buf, "efuse ", 6) == 0) {
type = RTW_PROC_CMD_EFUSE;
type_len = 6;
} else {
ret = -EINVAL;
goto err;
}
/* skip first type token, like 'bb ', 'rf ' */
p = buf + type_len;
len = count - type_len;
/* remove trailing newline character, because BB/RF parser uses
* " ," as delimiter that leads the last token contains '\n' if
* we use 'echo' command without '-n' argument.
*/
if (p[len - 1] == '\n')
len--;
p[len++] = '\0';
ret = proc_set_phydm_cmd(file, p, len, pos, data, type);
err:
_rtw_mfree(buf, count + 1);
if (ret >= 0)
return count;
return ret;
}
/*
* rtw_odm_proc:
* init/deinit when register/unregister net_device, along with rtw_adapter_proc
*/
const struct rtw_proc_hdl odm_proc_hdls[] = {
RTW_PROC_HDL_SSEQ("adaptivity", proc_get_phy_adaptivity, proc_set_phy_adaptivity),
RTW_PROC_HDL_SZSEQ("phl_cmd", proc_get_phl_cmd, proc_set_phl_cmd, PHYDM_MSG_LEN),
};
const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl);
static int rtw_odm_proc_open(struct inode *inode, struct file *file)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
ssize_t index = (ssize_t)PDE_DATA(inode);
#else
ssize_t index = (ssize_t)pde_data(inode);
#endif
const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
void *private = proc_get_parent_data(inode);
if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
int res = seq_open(file, hdl->u.seq_op);
if (res == 0)
((struct seq_file *)file->private_data)->private = private;
return res;
} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
return single_open(file, show, private);
} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
return single_open_size(file, show, private, hdl->u.sz.size);
#else
return single_open(file, show, private);
#endif
} else {
return -EROFS;
}
}
static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
#else
ssize_t index = (ssize_t)pde_data(file_inode(file));
#endif
const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
if (write)
return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
return -EROFS;
}
static const struct rtw_proc_ops rtw_odm_proc_seq_fops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
.proc_open = rtw_odm_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = seq_release,
.proc_write = rtw_odm_proc_write,
#else
.owner = THIS_MODULE,
.open = rtw_odm_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
.write = rtw_odm_proc_write,
#endif
};
static const struct rtw_proc_ops rtw_odm_proc_sseq_fops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
.proc_open = rtw_odm_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = rtw_odm_proc_write,
#else
.owner = THIS_MODULE,
.open = rtw_odm_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.write = rtw_odm_proc_write,
#endif
};
struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev)
{
struct proc_dir_entry *dir_odm = NULL;
struct proc_dir_entry *entry = NULL;
_adapter *adapter = rtw_netdev_priv(dev);
ssize_t i;
if (adapter->dir_dev == NULL) {
rtw_warn_on(1);
goto exit;
}
if (adapter->dir_odm != NULL) {
rtw_warn_on(1);
goto exit;
}
dir_odm = rtw_proc_create_dir("odm", adapter->dir_dev, dev);
if (dir_odm == NULL) {
rtw_warn_on(1);
goto exit;
}
adapter->dir_odm = dir_odm;
for (i = 0; i < odm_proc_hdls_num; i++) {
if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_seq_fops, (void *)i);
else if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_sseq_fops, (void *)i);
else
entry = NULL;
if (!entry) {
rtw_warn_on(1);
goto exit;
}
}
exit:
return dir_odm;
}
void rtw_odm_proc_deinit(_adapter *adapter)
{
struct proc_dir_entry *dir_odm = NULL;
int i;
dir_odm = adapter->dir_odm;
if (dir_odm == NULL) {
rtw_warn_on(1);
return;
}
for (i = 0; i < odm_proc_hdls_num; i++)
remove_proc_entry(odm_proc_hdls[i].name, dir_odm);
remove_proc_entry("odm", adapter->dir_dev);
adapter->dir_odm = NULL;
if (phydm_msg) {
rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
phydm_msg = NULL;
}
}
struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev)
{
struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
struct proc_dir_entry *dir_dev = NULL;
struct proc_dir_entry *entry = NULL;
_adapter *adapter = rtw_netdev_priv(dev);
ssize_t i;
if (drv_proc == NULL) {
rtw_warn_on(1);
goto exit;
}
if (adapter->dir_dev != NULL) {
rtw_warn_on(1);
goto exit;
}
dir_dev = rtw_proc_create_dir(dev->name, drv_proc, dev);
if (dir_dev == NULL) {
rtw_warn_on(1);
goto exit;
}
adapter->dir_dev = dir_dev;
for (i = 0; i < adapter_proc_hdls_num; i++) {
if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_seq_fops, (void *)i);
else if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_sseq_fops, (void *)i);
else
entry = NULL;
if (!entry) {
rtw_warn_on(1);
goto exit;
}
}
rtw_odm_proc_init(dev);
exit:
return dir_dev;
}
void rtw_adapter_proc_deinit(struct net_device *dev)
{
struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
struct proc_dir_entry *dir_dev = NULL;
_adapter *adapter = rtw_netdev_priv(dev);
int i;
dir_dev = adapter->dir_dev;
if (dir_dev == NULL) {
rtw_warn_on(1);
return;
}
for (i = 0; i < adapter_proc_hdls_num; i++)
remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
rtw_odm_proc_deinit(adapter);
remove_proc_entry(dev->name, drv_proc);
adapter->dir_dev = NULL;
}
void rtw_adapter_proc_replace(struct net_device *dev)
{
struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
struct proc_dir_entry *dir_dev = NULL;
_adapter *adapter = rtw_netdev_priv(dev);
int i;
dir_dev = adapter->dir_dev;
if (dir_dev == NULL) {
rtw_warn_on(1);
return;
}
for (i = 0; i < adapter_proc_hdls_num; i++)
remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
rtw_odm_proc_deinit(adapter);
remove_proc_entry(adapter->old_ifname, drv_proc);
adapter->dir_dev = NULL;
rtw_adapter_proc_init(dev);
}
#endif /* CONFIG_PROC_DEBUG */
|
2301_81045437/rtl8852be
|
os_dep/linux/rtw_proc.c
|
C
|
agpl-3.0
| 152,840
|
/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTW_PROC_H__
#define __RTW_PROC_H__
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#define RTW_PROC_HDL_TYPE_SEQ 0
#define RTW_PROC_HDL_TYPE_SSEQ 1
#define RTW_PROC_HDL_TYPE_SZSEQ 2
struct rtw_proc_hdl {
char *name;
u8 type;
union {
int (*show)(struct seq_file *, void *);
struct seq_operations *seq_op;
struct {
int (*show)(struct seq_file *, void *);
size_t size;
} sz;
} u;
ssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
};
#define RTW_PROC_HDL_SEQ(_name, _seq_op, _write) \
{ .name = _name, .type = RTW_PROC_HDL_TYPE_SEQ, .u.seq_op = _seq_op, .write = _write}
#define RTW_PROC_HDL_SSEQ(_name, _show, _write) \
{ .name = _name, .type = RTW_PROC_HDL_TYPE_SSEQ, .u.show = _show, .write = _write}
#define RTW_PROC_HDL_SZSEQ(_name, _show, _write, _size) \
{ .name = _name, .type = RTW_PROC_HDL_TYPE_SZSEQ, .u.sz.show = _show, .write = _write, .u.sz.size = _size}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
#define rtw_proc_ops proc_ops
#else
#define rtw_proc_ops file_operations
#endif
#ifdef CONFIG_PROC_DEBUG
int rtw_drv_proc_init(void);
void rtw_drv_proc_deinit(void);
struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev);
void rtw_adapter_proc_deinit(struct net_device *dev);
void rtw_adapter_proc_replace(struct net_device *dev);
#else /* !CONFIG_PROC_DEBUG */
static inline int rtw_drv_proc_init(void) {return _FAIL;}
#define rtw_drv_proc_deinit() do {} while (0)
static inline struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) {return NULL;}
#define rtw_adapter_proc_deinit(dev) do {} while (0)
#define rtw_adapter_proc_replace(dev) do {} while (0)
#endif /* !CONFIG_PROC_DEBUG */
#endif /* __RTW_PROC_H__ */
|
2301_81045437/rtl8852be
|
os_dep/linux/rtw_proc.h
|
C
|
agpl-3.0
| 2,424
|
/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include <drv_types.h>
#if defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) /* for now, only promised for kernel versions we support mesh */
int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
rhashtable_walk_enter((ht), (iter));
return 0;
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
return rhashtable_walk_init((ht), (iter), GFP_ATOMIC);
#else
/* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */
iter->ht = ht;
iter->p = NULL;
iter->slot = 0;
iter->skip = 0;
iter->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC);
if (!iter->walker)
return -ENOMEM;
spin_lock(&ht->lock);
iter->walker->tbl =
rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
list_add(&iter->walker->list, &iter->walker->tbl->walkers);
spin_unlock(&ht->lock);
return 0;
#endif
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
static inline int is_vmalloc_addr(const void *x)
{
#ifdef CONFIG_MMU
unsigned long addr = (unsigned long)x;
return addr >= VMALLOC_START && addr < VMALLOC_END;
#else
return 0;
#endif
}
#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */
void kvfree(const void *addr)
{
if (is_vmalloc_addr(addr))
vfree(addr);
else
kfree(addr);
}
#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */
#include "rhashtable.c"
#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
#endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */
|
2301_81045437/rtl8852be
|
os_dep/linux/rtw_rhashtable.c
|
C
|
agpl-3.0
| 2,295
|
/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTW_RHASHTABLE_H__
#define __RTW_RHASHTABLE_H__
#if defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) /* for now, only promised for kernel versions we support mesh */
/* directly reference rhashtable in kernel */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
#include <linux/rhashtable.h>
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */
/* Use rhashtable from kernel 4.4 */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
#define NULLS_MARKER(value) (1UL | (((long)value) << 1))
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags)
{
if (size != 0 && n > ULONG_MAX / size)
return NULL;
return __kmalloc(n * size, flags);
}
#endif
#include "rhashtable.h"
#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
typedef struct rhashtable rtw_rhashtable;
typedef struct rhash_head rtw_rhash_head;
typedef struct rhashtable_params rtw_rhashtable_params;
#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params)
typedef struct rhashtable_iter rtw_rhashtable_iter;
int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter);
#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0))
#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start_check(iter)
#else
#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter)
#endif
#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter)
#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter)
#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg))
#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params))
#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params))
#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params))
#endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */
#endif /* __RTW_RHASHTABLE_H__ */
|
2301_81045437/rtl8852be
|
os_dep/linux/rtw_rhashtable.h
|
C
|
agpl-3.0
| 2,806
|
/******************************************************************************
*
* Copyright(c) 2009-2010 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include <drv_types.h>
#ifdef CONFIG_IOCTL_CFG80211
void rtw_chset_hook_os_channels(struct rf_ctl_t *rfctl)
{
struct wiphy *wiphy = dvobj_to_wiphy(rfctl_to_dvobj(rfctl));
RT_CHANNEL_INFO *channel_set = rfctl->channel_set;
u8 max_chan_nums = rfctl->max_chan_nums;
struct ieee80211_channel *ch;
unsigned int i;
u16 channel;
u32 freq;
for (i = 0; i < max_chan_nums; i++) {
channel = channel_set[i].ChannelNum;
#if CONFIG_IEEE80211_BAND_6GHZ
if (channel_set[i].band == BAND_ON_6G)
continue; /* TODO: wiphy with 6G band */
else
#endif
freq = rtw_ch2freq(channel);
ch = ieee80211_get_channel(wiphy, freq);
if (!ch) {
rtw_warn_on(1);
continue;
}
channel_set[i].os_chan = ch;
}
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
bool rtw_regd_is_wiphy_self_managed(struct wiphy *wiphy)
{
return rtw_rfctl_is_disable_sw_channel_plan(wiphy_to_dvobj(wiphy))
|| !REGSTY_REGD_SRC_FROM_OS(dvobj_to_regsty(wiphy_to_dvobj(wiphy)));
}
static struct ieee80211_reg_rule rtw_get_ieee80211_reg_rule(struct get_chplan_resp *chplan, enum band_type band, int last_end_freq, int start_freq, int end_freq, int next_start_freq, u32 flags)
{
struct ieee80211_reg_rule rule = REG_RULE(
start_freq - 10, end_freq + 10, 20, 6, 20,
((flags & RTW_CHF_NO_IR) ? NL80211_RRF_NO_IR : 0)
//| ((flags & RTW_CHF_DFS) ? NL80211_RRF_DFS : 0) /* TODO: DFS */
);
int regd_max_bw = 160;
int frange_max_bw = 160;
if (!(chplan->proto_en & CHPLAN_PROTO_EN_AC) || band == BAND_ON_24G)
regd_max_bw = 40;
/* TODO: !RFCTL_REG_EN_11HT(rfctl) limit to 20MHz */
while ((end_freq - start_freq + 20) < frange_max_bw) {
frange_max_bw /= 2;
if (frange_max_bw == 20)
break;
}
rule.freq_range.max_bandwidth_khz = MHZ_TO_KHZ(rtw_min(regd_max_bw, frange_max_bw));
if (regd_max_bw > frange_max_bw
&& (rtw_freq_consecutive(last_end_freq, start_freq)
|| rtw_freq_consecutive(end_freq, next_start_freq)
)
)
rule.flags |= NL80211_RRF_AUTO_BW;
if (regd_max_bw < 40)
rule.flags |= NL80211_RRF_NO_HT40;
if (regd_max_bw < 80)
rule.flags |= NL80211_RRF_NO_80MHZ;
if (regd_max_bw < 160)
rule.flags |= NL80211_RRF_NO_160MHZ;
return rule;
}
static int rtw_build_wiphy_regd(struct wiphy *wiphy, struct get_chplan_resp *chplan, struct ieee80211_regdomain **regd)
{
int i;
RT_CHANNEL_INFO *chinfo;
enum band_type start_band, band;
int last_end_freq, start_freq, end_freq, freq;
u32 start_flags, flags;
struct ieee80211_regdomain *r;
int rule_num = 0;
bool build = 0;
if (regd)
*regd = NULL;
loop:
start_band = BAND_MAX;
last_end_freq = 0;
for (i = 0; i < chplan->chset_num; i++) {
chinfo = &chplan->chset[i];
freq = rtw_ch2freq_by_band(chinfo->band, chinfo->ChannelNum);
if (!freq) {
RTW_WARN(FUNC_WIPHY_FMT" rtw_ch2freq_by_band(%s, %u) fail\n"
, FUNC_WIPHY_ARG(wiphy), band_str(chinfo->band), chinfo->ChannelNum);
continue;
}
band = chinfo->band;
flags = chinfo->flags & (RTW_CHF_NO_IR | RTW_CHF_DFS);
if (start_band == BAND_MAX) {
start_band = band;
start_freq = end_freq = freq;
start_flags = flags;
continue;
}
if (start_band == band
&& start_flags == flags
&& rtw_freq_consecutive(end_freq, freq)
) {
end_freq = freq;
continue;
}
/* create rule */
if (build) {
RTW_DBG("add rule_%02d(%s, %d, %d, 0x%x)\n"
, r->n_reg_rules, band_str(start_band), start_freq, end_freq, start_flags);
r->reg_rules[r->n_reg_rules++] = rtw_get_ieee80211_reg_rule(chplan, start_band
, last_end_freq, start_freq, end_freq, freq, start_flags);
} else
rule_num++;
/* start a new rule */
start_band = band;
last_end_freq = end_freq;
start_freq = end_freq = freq;
start_flags = flags;
}
if (start_band != BAND_MAX) {
/* create rule */
if (build) {
RTW_DBG("add rule_%02d(%s, %d, %d, 0x%x)\n"
, r->n_reg_rules, band_str(start_band), start_freq, end_freq, start_flags);
r->reg_rules[r->n_reg_rules++] = rtw_get_ieee80211_reg_rule(chplan, start_band
, last_end_freq, start_freq, end_freq, 0, start_flags);
} else
rule_num++;
}
if (!build) {
/* switch to build phase */
build = 1;
if (!regd)
goto exit;
r = rtw_zmalloc(sizeof(**regd) + sizeof(struct ieee80211_reg_rule) * rule_num);
if (!r) {
rule_num = -1;
goto exit;
}
_rtw_memcpy(r->alpha2, chplan->alpha2, 2);
r->alpha2[2] = 0;
r->dfs_region = NL80211_DFS_UNSET;
goto loop;
}
*regd = r;
exit:
return rule_num;
}
static void rtw_regd_disable_no_20mhz_chs(struct wiphy *wiphy)
{
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i, j;
for (i = 0; i < NUM_NL80211_BANDS; i++) {
sband = wiphy->bands[i];
if (!sband)
continue;
for (j = 0; j < sband->n_channels; j++) {
ch = &sband->channels[j];
if (!ch)
continue;
if (ch->flags & IEEE80211_CHAN_NO_20MHZ) {
RTW_INFO(FUNC_WIPHY_FMT" disable band:%d ch:%u w/o 20MHz\n", FUNC_WIPHY_ARG(wiphy), ch->band, ch->hw_value);
ch->flags = IEEE80211_CHAN_DISABLED;
}
}
}
}
void rtw_update_wiphy_regd(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed)
{
struct ieee80211_regdomain *regd;
int ret;
ret = rtw_build_wiphy_regd(wiphy, chplan, ®d);
if (ret == -1) {
RTW_WARN(FUNC_WIPHY_FMT" rtw_build_wiphy_regd() fail\n", FUNC_WIPHY_ARG(wiphy));
return;
}
if (ret == 0) {
RTW_WARN(FUNC_WIPHY_FMT" rtw_build_wiphy_regd() builds empty regd, bypass regd setting\n", FUNC_WIPHY_ARG(wiphy));
goto free_regd;
}
if (rtnl_lock_needed)
rtnl_lock();
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0))
ret = regulatory_set_wiphy_regd_sync(wiphy, regd);
#else
ret = regulatory_set_wiphy_regd_sync_rtnl(wiphy, regd);
#endif
rtw_regd_disable_no_20mhz_chs(wiphy);
if (rtnl_lock_needed)
rtnl_unlock();
if (ret != 0)
RTW_INFO(FUNC_WIPHY_FMT" regulatory_set_wiphy_regd_sync_rtnl return %d\n", FUNC_WIPHY_ARG(wiphy), ret);
free_regd:
rtw_mfree(regd, sizeof(*regd) + sizeof(struct ieee80211_reg_rule) * regd->n_reg_rules);
}
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */
static void rtw_regd_overide_flags(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed)
{
RT_CHANNEL_INFO *channel_set = chplan->chset;
u8 max_chan_nums = chplan->chset_num;
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i, j;
if (rtnl_lock_needed)
rtnl_lock();
/* all channels disable */
for (i = 0; i < NUM_NL80211_BANDS; i++) {
sband = wiphy->bands[i];
if (!sband)
continue;
for (j = 0; j < sband->n_channels; j++) {
ch = &sband->channels[j];
if (!ch)
continue;
ch->flags = IEEE80211_CHAN_DISABLED;
}
}
/* channels apply by channel plans. */
for (i = 0; i < max_chan_nums; i++) {
ch = channel_set[i].os_chan;
if (!ch)
continue;
/* enable */
ch->flags = 0;
if (channel_set[i].flags & RTW_CHF_DFS) {
/*
* before integrating with nl80211 flow
* bypass IEEE80211_CHAN_RADAR when configured with radar detection
* to prevent from hostapd blocking DFS channels
*/
#ifdef CONFIG_DFS_MASTER
if (chplan->dfs_domain == RTW_DFS_REGD_NONE)
#endif
ch->flags |= IEEE80211_CHAN_RADAR;
}
if (channel_set[i].flags & RTW_CHF_NO_IR) {
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
ch->flags |= IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN;
#else
ch->flags |= IEEE80211_CHAN_NO_IR;
#endif
}
}
if (rtnl_lock_needed)
rtnl_unlock();
}
#ifdef CONFIG_REGD_SRC_FROM_OS
static void rtw_regd_apply_dfs_flags(struct get_chplan_resp *chplan, bool rtnl_lock_needed)
{
RT_CHANNEL_INFO *channel_set = chplan->chset;
u8 max_chan_nums = chplan->chset_num;
unsigned int i;
struct ieee80211_channel *chan;
if (rtnl_lock_needed)
rtnl_lock();
/* channels apply by channel plans. */
for (i = 0; i < max_chan_nums; i++) {
chan = channel_set[i].os_chan;
if (!chan) {
rtw_warn_on(1);
continue;
}
if (channel_set[i].flags & RTW_CHF_DFS) {
/*
* before integrating with nl80211 flow
* clear IEEE80211_CHAN_RADAR when configured with radar detection
* to prevent from hostapd blocking DFS channels
*/
#ifdef CONFIG_DFS_MASTER
if (chplan->dfs_domain != RTW_DFS_REGD_NONE)
chan->flags &= ~IEEE80211_CHAN_RADAR;
#endif
}
}
if (rtnl_lock_needed)
rtnl_unlock();
}
/* init_channel_set_from_wiphy */
u8 rtw_os_init_channel_set(_adapter *padapter, RT_CHANNEL_INFO *channel_set)
{
struct wiphy *wiphy = adapter_to_wiphy(padapter);
struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct registry_priv *regsty = adapter_to_regsty(padapter);
struct ieee80211_channel *chan;
u8 chanset_size = 0;
int i, j;
_rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
for (i = NL80211_BAND_2GHZ; i <= NL80211_BAND_5GHZ; i++) {
if (!wiphy->bands[i])
continue;
for (j = 0; j < wiphy->bands[i]->n_channels; j++) {
chan = &wiphy->bands[i]->channels[j];
if (chan->flags & IEEE80211_CHAN_DISABLED)
continue;
if (rtw_regsty_is_excl_chs(regsty, chan->hw_value))
continue;
if (chanset_size >= MAX_CHANNEL_NUM) {
RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
i = NL80211_BAND_5GHZ + 1;
break;
}
channel_set[chanset_size].ChannelNum = chan->hw_value;
channel_set[chanset_size].band = nl80211_band_to_rtw_band(i);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
if (chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN))
#else
if (chan->flags & IEEE80211_CHAN_NO_IR)
#endif
channel_set[chanset_size].flags |= RTW_CHF_NO_IR;
if (chan->flags & IEEE80211_CHAN_RADAR)
channel_set[chanset_size].flags |= RTW_CHF_DFS;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
if (chan->flags & IEEE80211_CHAN_NO_HT40PLUS)
channel_set[chanset_size].flags |= RTW_CHF_NO_HT40U;
if (chan->flags & IEEE80211_CHAN_NO_HT40MINUS)
channel_set[chanset_size].flags |= RTW_CHF_NO_HT40L;
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
if (chan->flags & IEEE80211_CHAN_NO_80MHZ)
channel_set[chanset_size].flags |= RTW_CHF_NO_80MHZ;
if (chan->flags & IEEE80211_CHAN_NO_160MHZ)
channel_set[chanset_size].flags |= RTW_CHF_NO_160MHZ;
#endif
channel_set[chanset_size].os_chan = chan;
chanset_size++;
}
}
#if CONFIG_IEEE80211_BAND_5GHZ
#ifdef CONFIG_DFS_MASTER
for (i = 0; i < chanset_size; i++)
channel_set[i].non_ocp_end_time = rtw_get_current_time();
#endif
#endif /* CONFIG_IEEE80211_BAND_5GHZ */
if (chanset_size)
RTW_INFO(FUNC_ADPT_FMT" ch num:%d\n"
, FUNC_ADPT_ARG(padapter), chanset_size);
else
RTW_WARN(FUNC_ADPT_FMT" final chset has no channel\n"
, FUNC_ADPT_ARG(padapter));
return chanset_size;
}
s16 rtw_os_get_total_txpwr_regd_lmt_mbm(_adapter *adapter, u8 cch, enum channel_width bw)
{
struct wiphy *wiphy = adapter_to_wiphy(adapter);
s16 mbm = UNSPECIFIED_MBM;
u8 *op_chs;
u8 op_ch_num;
u8 i;
u32 freq;
struct ieee80211_channel *ch;
if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
goto exit;
for (i = 0; i < op_ch_num; i++) {
freq = rtw_ch2freq(op_chs[i]);
ch = ieee80211_get_channel(wiphy, freq);
if (!ch) {
rtw_warn_on(1);
continue;
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
mbm = rtw_min(mbm, ch->max_reg_power * MBM_PDBM);
#else
/* require max_power == 0 (therefore orig_mpwr set to 0) when wiphy registration */
mbm = rtw_min(mbm, ch->max_power * MBM_PDBM);
#endif
}
exit:
return mbm;
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
static enum rtw_dfs_regd nl80211_dfs_regions_to_rtw_dfs_region(enum nl80211_dfs_regions region)
{
switch (region) {
case NL80211_DFS_FCC:
return RTW_DFS_REGD_FCC;
case NL80211_DFS_ETSI:
return RTW_DFS_REGD_ETSI;
case NL80211_DFS_JP:
return RTW_DFS_REGD_MKK;
case NL80211_DFS_UNSET:
default:
return RTW_DFS_REGD_NONE;
}
};
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
#endif /* CONFIG_REGD_SRC_FROM_OS */
static enum rtw_regd_inr nl80211_reg_initiator_to_rtw_regd_inr(enum nl80211_reg_initiator initiator)
{
switch (initiator) {
case NL80211_REGDOM_SET_BY_DRIVER:
return RTW_REGD_SET_BY_DRIVER;
case NL80211_REGDOM_SET_BY_CORE:
return RTW_REGD_SET_BY_CORE;
case NL80211_REGDOM_SET_BY_USER:
return RTW_REGD_SET_BY_USER;
case NL80211_REGDOM_SET_BY_COUNTRY_IE:
return RTW_REGD_SET_BY_COUNTRY_IE;
}
rtw_warn_on(1);
return RTW_REGD_SET_BY_NUM;
};
#ifdef CONFIG_RTW_DEBUG
static const char *nl80211_reg_initiator_str(enum nl80211_reg_initiator initiator)
{
switch (initiator) {
case NL80211_REGDOM_SET_BY_DRIVER:
return "DRIVER";
case NL80211_REGDOM_SET_BY_CORE:
return "CORE";
case NL80211_REGDOM_SET_BY_USER:
return "USER";
case NL80211_REGDOM_SET_BY_COUNTRY_IE:
return "COUNTRY_IE";
}
rtw_warn_on(1);
return "UNKNOWN";
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
static const char *nl80211_user_reg_hint_type_str(enum nl80211_user_reg_hint_type type)
{
switch (type) {
case NL80211_USER_REG_HINT_USER:
return "USER";
case NL80211_USER_REG_HINT_CELL_BASE:
return "CELL_BASE";
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
case NL80211_USER_REG_HINT_INDOOR:
return "INDOOR";
#endif
}
rtw_warn_on(1);
return "UNKNOWN";
}
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
static const char *nl80211_dfs_regions_str(enum nl80211_dfs_regions region)
{
switch (region) {
case NL80211_DFS_UNSET:
return "UNSET";
case NL80211_DFS_FCC:
return "FCC";
case NL80211_DFS_ETSI:
return "ETSI";
case NL80211_DFS_JP:
return "JP";
}
rtw_warn_on(1);
return "UNKNOWN";
};
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
static const char *environment_cap_str(enum environment_cap cap)
{
switch (cap) {
case ENVIRON_ANY:
return "ANY";
case ENVIRON_INDOOR:
return "INDOOR";
case ENVIRON_OUTDOOR:
return "OUTDOOR";
}
rtw_warn_on(1);
return "UNKNOWN";
}
static void dump_requlatory_request(void *sel, struct regulatory_request *request)
{
u8 alpha2_len;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0))
alpha2_len = 3;
#else
alpha2_len = 2;
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
RTW_PRINT_SEL(sel, "initiator:%s, wiphy_idx:%d, type:%s\n"
, nl80211_reg_initiator_str(request->initiator)
, request->wiphy_idx
, nl80211_user_reg_hint_type_str(request->user_reg_hint_type));
#else
RTW_PRINT_SEL(sel, "initiator:%s, wiphy_idx:%d\n"
, nl80211_reg_initiator_str(request->initiator)
, request->wiphy_idx);
#endif
RTW_PRINT_SEL(sel, "alpha2:%.*s\n", alpha2_len, request->alpha2);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
RTW_PRINT_SEL(sel, "dfs_region:%s\n", nl80211_dfs_regions_str(request->dfs_region));
#endif
RTW_PRINT_SEL(sel, "intersect:%d\n", request->intersect);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
RTW_PRINT_SEL(sel, "processed:%d\n", request->processed);
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36))
RTW_PRINT_SEL(sel, "country_ie_checksum:0x%08x\n", request->country_ie_checksum);
#endif
RTW_PRINT_SEL(sel, "country_ie_env:%s\n", environment_cap_str(request->country_ie_env));
}
#endif /* CONFIG_RTW_DEBUG */
static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
{
struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
struct registry_priv *regsty = dvobj_to_regsty(dvobj);
enum rtw_regd_inr inr;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
rtw_set_rtnl_lock_holder(dvobj, current);
#endif
#ifdef CONFIG_RTW_DEBUG
if (rtw_drv_log_level >= _DRV_INFO_) {
RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
dump_requlatory_request(RTW_DBGDUMP, request);
}
#endif
inr = nl80211_reg_initiator_to_rtw_regd_inr(request->initiator);
#ifdef CONFIG_REGD_SRC_FROM_OS
if (REGSTY_REGD_SRC_FROM_OS(regsty)) {
enum rtw_dfs_regd dfs_region = RTW_DFS_REGD_NONE;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
dfs_region = nl80211_dfs_regions_to_rtw_dfs_region(request->dfs_region);
#endif
/* trigger command to sync regulatory form OS */
rtw_sync_os_regd_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_WAIT_ACK, request->alpha2, dfs_region, inr);
} else
#endif
{
/* use alpha2 as input to select the corresponding channel plan settings defined by Realtek */
struct get_chplan_resp *chplan;
switch (request->initiator) {
case NL80211_REGDOM_SET_BY_USER:
rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2, inr);
break;
case NL80211_REGDOM_SET_BY_DRIVER:
case NL80211_REGDOM_SET_BY_CORE:
case NL80211_REGDOM_SET_BY_COUNTRY_IE:
default:
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
rtw_warn_on(rtw_regd_is_wiphy_self_managed(wiphy));
#endif
if (rtw_get_chplan_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_WAIT_ACK, &chplan) == _SUCCESS)
rtw_regd_change_complete_sync(wiphy, chplan, 0);
else
rtw_warn_on(1);
break;
}
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
rtw_set_rtnl_lock_holder(dvobj, NULL);
#endif
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
static int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_request *request)
{
rtw_reg_notifier(wiphy, request);
return 0;
}
#endif
struct async_regd_change_evt {
_list list; /* async_regd_change_list */
struct wiphy *wiphy;
struct get_chplan_resp *chplan;
};
static void async_regd_change_work_hdl(_workitem *work)
{
struct rtw_wiphy_data *wiphy_data = container_of(work, struct rtw_wiphy_data, async_regd_change_work);
struct async_regd_change_evt *evt;
_list *list, *head = &wiphy_data->async_regd_change_list;
while (1) {
_rtw_mutex_lock_interruptible(&wiphy_data->async_regd_change_mutex);
list = rtw_is_list_empty(head) ? NULL : get_next(head);
if (list)
rtw_list_delete(list);
_rtw_mutex_unlock(&wiphy_data->async_regd_change_mutex);
if (!list)
break;
evt = LIST_CONTAINOR(list, struct async_regd_change_evt, list);
rtw_regd_change_complete_sync(evt->wiphy, evt->chplan, 1);
rtw_mfree(evt, sizeof(*evt));
}
}
int rtw_regd_init(struct wiphy *wiphy)
{
struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
wiphy->reg_notifier = rtw_reg_notifier_return;
#else
wiphy->reg_notifier = rtw_reg_notifier;
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
#else
wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;
wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF;
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
if (rtw_regd_is_wiphy_self_managed(wiphy))
wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED;
#endif
_rtw_init_listhead(&wiphy_data->async_regd_change_list);
_rtw_mutex_init(&wiphy_data->async_regd_change_mutex);
_init_workitem(&wiphy_data->async_regd_change_work, async_regd_change_work_hdl, NULL);
return 0;
}
static void rtw_regd_async_regd_change_list_free(struct wiphy *wiphy)
{
struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
struct async_regd_change_evt *evt;
struct get_chplan_resp *chplan;
_list *cur, *head;
_rtw_mutex_lock_interruptible(&wiphy_data->async_regd_change_mutex);
head = &wiphy_data->async_regd_change_list;
cur = get_next(head);
while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
evt = LIST_CONTAINOR(cur, struct async_regd_change_evt, list);
chplan = evt->chplan;
cur = get_next(cur);
rtw_list_delete(&evt->list);
rtw_vmfree(chplan, sizeof(*chplan) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num);
rtw_mfree(evt, sizeof(*evt));
}
_rtw_mutex_unlock(&wiphy_data->async_regd_change_mutex);
}
void rtw_regd_deinit(struct wiphy *wiphy)
{
struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
_cancel_workitem_sync(&wiphy_data->async_regd_change_work);
rtw_regd_async_regd_change_list_free(wiphy);
_rtw_mutex_free(&wiphy_data->async_regd_change_mutex);
}
void rtw_regd_change_complete_sync(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed)
{
if (chplan->regd_src == REGD_SRC_RTK_PRIV) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
if (rtw_regd_is_wiphy_self_managed(wiphy))
rtw_update_wiphy_regd(wiphy, chplan, rtnl_lock_needed);
else
#endif
rtw_regd_overide_flags(wiphy, chplan, rtnl_lock_needed);
}
#ifdef CONFIG_REGD_SRC_FROM_OS
else if (chplan->regd_src == REGD_SRC_OS)
rtw_regd_apply_dfs_flags(chplan, rtnl_lock_needed);
#endif
else
rtw_warn_on(1);
rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num);
}
int rtw_regd_change_complete_async(struct wiphy *wiphy, struct get_chplan_resp *chplan)
{
struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
struct async_regd_change_evt *evt;
evt = rtw_malloc(sizeof(*evt));
if (!evt) {
rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num);
return _FAIL;
}
_rtw_init_listhead(&evt->list);
evt->wiphy = wiphy;
evt->chplan = chplan;
_rtw_mutex_lock_interruptible(&wiphy_data->async_regd_change_mutex);
rtw_list_insert_tail(&evt->list, &wiphy_data->async_regd_change_list);
_rtw_mutex_unlock(&wiphy_data->async_regd_change_mutex);
_set_workitem(&wiphy_data->async_regd_change_work);
return _SUCCESS;
}
#endif /* CONFIG_IOCTL_CFG80211 */
|
2301_81045437/rtl8852be
|
os_dep/linux/wifi_regd.c
|
C
|
agpl-3.0
| 22,166
|
/******************************************************************************
*
* Copyright(c) 2009-2010 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __WIFI_REGD_H__
#define __WIFI_REGD_H__
void rtw_chset_hook_os_channels(struct rf_ctl_t *rfctl);
void rtw_regd_change_complete_sync(struct wiphy *wiphy, struct get_chplan_resp *chplan, bool rtnl_lock_needed);
int rtw_regd_change_complete_async(struct wiphy *wiphy, struct get_chplan_resp *chplan);
#ifdef CONFIG_REGD_SRC_FROM_OS
struct _RT_CHANNEL_INFO;
u8 rtw_os_init_channel_set(_adapter *padapter, struct _RT_CHANNEL_INFO *channel_set);
s16 rtw_os_get_total_txpwr_regd_lmt_mbm(_adapter *adapter, u8 cch, enum channel_width bw);
#endif
int rtw_regd_init(struct wiphy *wiphy);
void rtw_regd_deinit(struct wiphy *wiphy);
#endif /* __WIFI_REGD_H__ */
|
2301_81045437/rtl8852be
|
os_dep/linux/wifi_regd.h
|
C
|
agpl-3.0
| 1,322
|
/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _XMIT_OSDEP_C_
#include <drv_types.h>
#define DBG_DUMP_OS_QUEUE_CTL 0
uint rtw_remainder_len(struct pkt_file *pfile)
{
return pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start));
}
void _rtw_open_pktfile(struct sk_buff *pktptr, struct pkt_file *pfile)
{
pfile->pkt = pktptr;
pfile->cur_addr = pfile->buf_start = pktptr->data;
pfile->pkt_len = pfile->buf_len = pktptr->len;
pfile->cur_buffer = pfile->buf_start ;
}
uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen)
{
uint len = 0;
len = rtw_remainder_len(pfile);
len = (rlen > len) ? len : rlen;
if (rmem)
skb_copy_bits(pfile->pkt, pfile->buf_len - pfile->pkt_len, rmem, len);
pfile->cur_addr += len;
pfile->pkt_len -= len;
return len;
}
sint rtw_endofpktfile(struct pkt_file *pfile)
{
if (pfile->pkt_len == 0) {
return _TRUE;
}
return _FALSE;
}
void rtw_set_tx_chksum_offload(struct sk_buff *pkt, struct pkt_attrib *pattrib)
{
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
struct sk_buff *skb = (struct sk_buff *)pkt;
struct iphdr *iph = NULL;
struct ipv6hdr *i6ph = NULL;
struct udphdr *uh = NULL;
struct tcphdr *th = NULL;
u8 protocol = 0xFF;
if (skb->protocol == htons(ETH_P_IP)) {
iph = (struct iphdr *)skb_network_header(skb);
protocol = iph->protocol;
} else if (skb->protocol == htons(ETH_P_IPV6)) {
i6ph = (struct ipv6hdr *)skb_network_header(skb);
protocol = i6ph->nexthdr;
} else
{}
/* HW unable to compute CSUM if header & payload was be encrypted by SW(cause TXDMA error) */
if (pattrib->bswenc == _TRUE) {
if (skb->ip_summed == CHECKSUM_PARTIAL)
skb_checksum_help(skb);
return;
}
/* For HW rule, clear ipv4_csum & UDP/TCP_csum if it is UDP/TCP packet */
switch (protocol) {
case IPPROTO_UDP:
uh = (struct udphdr *)skb_transport_header(skb);
uh->check = 0;
if (iph)
iph->check = 0;
pattrib->hw_csum = _TRUE;
break;
case IPPROTO_TCP:
th = (struct tcphdr *)skb_transport_header(skb);
th->check = 0;
if (iph)
iph->check = 0;
pattrib->hw_csum = _TRUE;
break;
default:
break;
}
#endif
}
#if 0 /*CONFIG_CORE_XMITBUF*/
int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag)
{
if (alloc_sz > 0) {
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct usb_device *pusbd = dvobj_to_usb(pdvobjpriv)->pusbdev;
pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr);
pxmitbuf->pbuf = pxmitbuf->pallocated_buf;
if (pxmitbuf->pallocated_buf == NULL)
return _FAIL;
#else /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
if (pxmitbuf->pallocated_buf == NULL)
return _FAIL;
pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), SZ_ALIGN_XMITFRAME_EXT);
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
}
if (flag) {
#ifdef CONFIG_USB_HCI
int i;
for (i = 0; i < 8; i++) {
pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
if (pxmitbuf->pxmit_urb[i] == NULL) {
RTW_INFO("pxmitbuf->pxmit_urb[i]==NULL");
return _FAIL;
}
}
#endif
}
return _SUCCESS;
}
void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag)
{
if (flag) {
#ifdef CONFIG_USB_HCI
int i;
for (i = 0; i < 8; i++) {
if (pxmitbuf->pxmit_urb[i]) {
/* usb_kill_urb(pxmitbuf->pxmit_urb[i]); */
usb_free_urb(pxmitbuf->pxmit_urb[i]);
}
}
#endif
}
if (free_sz > 0) {
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct usb_device *pusbd = dvobj_to_usb(pdvobjpriv)->pusbdev;
rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr);
pxmitbuf->pallocated_buf = NULL;
pxmitbuf->dma_transfer_addr = 0;
#else /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
if (pxmitbuf->pallocated_buf)
rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
}
}
#else
u8 rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_frame *pxframe)
{
u32 alloc_sz = SZ_XMITFRAME_EXT + SZ_ALIGN_XMITFRAME_EXT;
#if 0 /*def CONFIG_USE_USB_BUFFER_ALLOC_TX*/
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct usb_device *pusbd = dvobj_to_usb(dvobj)->pusbdev;
pxframe->prealloc_buf_addr = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxframe->dma_transfer_addr);
if (pxframe->prealloc_buf_addr == NULL) {
RTW_ERR("%s prealloc_buf_addr failed\n", __func__);
rtw_warn_on(1);
return _FAIL;
}
pxframe->buf_addr = pxframe->prealloc_buf_addr;
#else
pxframe->prealloc_buf_addr = rtw_zmalloc(alloc_sz);
if (pxframe->prealloc_buf_addr == NULL) {
RTW_ERR("%s prealloc_buf_addr failed\n", __func__);
rtw_warn_on(1);
return _FAIL;
}
pxframe->buf_addr = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxframe->prealloc_buf_addr), SZ_ALIGN_XMITFRAME_EXT);
#endif
return _SUCCESS;
}
void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_frame *pxframe)
{
u32 free_sz = SZ_XMITFRAME_EXT + SZ_ALIGN_XMITFRAME_EXT;
#if 0 /*def CONFIG_USE_USB_BUFFER_ALLOC_TX*/
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct usb_device *pusbd = dvobj_to_usb(dvobj)->pusbdev;
if (pxframe->prealloc_buf_addr) {
rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxframe->prealloc_buf_addr, pxframe->dma_transfer_addr);
pxframe->prealloc_buf_addr = NULL;
pxframe->buf_addr = NULL;
pxframe->dma_transfer_addr = 0;
}
#else
if (pxframe->prealloc_buf_addr) {
rtw_mfree(pxframe->prealloc_buf_addr, free_sz);
pxframe->prealloc_buf_addr = NULL;
pxframe->buf_addr = NULL;
}
#endif
}
#endif
void dump_os_queue(void *sel, _adapter *padapter)
{
struct net_device *ndev = padapter->pnetdev;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
int i;
for (i = 0; i < 4; i++) {
RTW_PRINT_SEL(sel, "os_queue[%d]:%s\n"
, i, __netif_subqueue_stopped(ndev, i) ? "stopped" : "waked");
}
#else
RTW_PRINT_SEL(sel, "os_queue:%s\n"
, netif_queue_stopped(ndev) ? "stopped" : "waked");
#endif
}
#define WMM_XMIT_THRESHOLD (NR_XMITFRAME*2/5)
static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 os_qid)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter->registrypriv.wifi_spec) {
if (pxmitpriv->hwxmits[os_qid].accnt < WMM_XMIT_THRESHOLD)
return _TRUE;
#ifdef DBG_CONFIG_ERROR_DETECT
#ifdef DBG_CONFIG_ERROR_RESET
} else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) {
return _FALSE;
#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
} else {
return _TRUE;
}
return _FALSE;
#else
return _TRUE;
#endif
}
static inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 os_qid)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
if (padapter->registrypriv.wifi_spec) {
/* No free space for Tx, tx_worker is too slow */
if (pxmitpriv->hwxmits[os_qid].accnt > WMM_XMIT_THRESHOLD)
return _TRUE;
} else {
if (pxmitpriv->free_xmitframe_cnt <= 4)
return _TRUE;
}
#else
if (pxmitpriv->free_xmitframe_cnt <= 4)
return _TRUE;
#endif
return _FALSE;
}
void rtw_os_pkt_complete(_adapter *padapter, struct sk_buff *pkt)
{
rtw_skb_free(pkt);
}
void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe)
{
if (pxframe->pkt)
rtw_os_pkt_complete(padapter, pxframe->pkt);
pxframe->pkt = NULL;
}
void rtw_os_xmit_schedule(_adapter *padapter)
{
#if 0 /*defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/
_adapter *pri_adapter;
if (!padapter)
return;
pri_adapter = GET_PRIMARY_ADAPTER(padapter);
if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
_rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema);
#elif defined(CONFIG_PCI_HCI) || defined(CONFIG_USB_HCI)
struct xmit_priv *pxmitpriv;
if (!padapter)
return;
pxmitpriv = &padapter->xmitpriv;
_rtw_spinlock_bh(&pxmitpriv->lock);
if (rtw_txframes_pending(padapter))
rtw_tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
_rtw_spinunlock_bh(&pxmitpriv->lock);
#if 0 /*defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE)*/
if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
#endif
#endif
}
void rtw_os_check_wakup_queue(_adapter *padapter, u16 os_qid)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
if (rtw_os_need_wake_queue(padapter, os_qid)) {
if (DBG_DUMP_OS_QUEUE_CTL)
RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), os_qid);
netif_wake_subqueue(padapter->pnetdev, os_qid);
}
#else
if (rtw_os_need_wake_queue(padapter, 0)) {
if (DBG_DUMP_OS_QUEUE_CTL)
RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter));
netif_wake_queue(padapter->pnetdev);
}
#endif
}
bool rtw_os_check_stop_queue(_adapter *padapter, u16 os_qid)
{
bool busy = _FALSE;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
if (rtw_os_need_stop_queue(padapter, os_qid)) {
if (DBG_DUMP_OS_QUEUE_CTL)
RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), os_qid);
netif_stop_subqueue(padapter->pnetdev, os_qid);
busy = _TRUE;
}
#else
if (rtw_os_need_stop_queue(padapter, 0)) {
if (DBG_DUMP_OS_QUEUE_CTL)
RTW_INFO(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(padapter));
rtw_netif_stop_queue(padapter->pnetdev);
busy = _TRUE;
}
#endif
return busy;
}
void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
int i;
for (i = 0; i < 4; i++) {
if (qcnt_freed[i] == 0)
continue;
if (rtw_os_need_wake_queue(padapter, i)) {
if (DBG_DUMP_OS_QUEUE_CTL)
RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), i);
netif_wake_subqueue(padapter->pnetdev, i);
}
}
#else
if (qcnt_freed[0] || qcnt_freed[1] || qcnt_freed[2] || qcnt_freed[3]) {
if (rtw_os_need_wake_queue(padapter, 0)) {
if (DBG_DUMP_OS_QUEUE_CTL)
RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter));
netif_wake_queue(padapter->pnetdev);
}
}
#endif
}
int _rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev)
{
_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
struct sk_buff *skb = pkt;
struct sk_buff *segs, *nskb;
netdev_features_t features = padapter->pnetdev->features;
#endif
u16 os_qid = 0;
s32 res = 0;
if (padapter->registrypriv.mp_mode) {
RTW_INFO("MP_TX_DROP_OS_FRAME\n");
goto drop_packet;
}
DBG_COUNTER(padapter->tx_logs.os_tx);
if (rtw_if_up(padapter) == _FALSE) {
DBG_COUNTER(padapter->tx_logs.os_tx_err_up);
#ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__);
#endif
goto drop_packet;
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
os_qid = skb_get_queue_mapping(pkt);
#endif
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
if (skb_shinfo(skb)->gso_size) {
/* split a big(65k) skb into several small(1.5k) skbs */
features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
segs = skb_gso_segment(skb, features);
if (IS_ERR(segs) || !segs)
goto drop_packet;
do {
nskb = segs;
segs = segs->next;
nskb->next = NULL;
rtw_mstat_update( MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, nskb->truesize);
res = rtw_xmit(padapter, &nskb, os_qid);
if (res < 0) {
#ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
#endif
pxmitpriv->tx_drop++;
rtw_os_pkt_complete(padapter, nskb);
}
} while (segs);
rtw_os_pkt_complete(padapter, skb);
goto exit;
}
#endif
res = rtw_xmit(padapter, &pkt, os_qid);
if (res < 0) {
#ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
#endif
goto drop_packet;
}
goto exit;
drop_packet:
pxmitpriv->tx_drop++;
rtw_os_pkt_complete(padapter, pkt);
exit:
return 0;
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
/* copy from skbuff.c to be compatible with old kernel */
static void kfree_skb_list(struct sk_buff *segs)
{
while (segs) {
struct sk_buff *next = segs->next;
kfree_skb(segs);
segs = next;
}
}
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
netdev_tx_t rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev)
#else
int rtw_xmit_entry(struct sk_buff *pkt, _nic_hdl pnetdev)
#endif
{
_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
int ret = 0;
if (pkt) {
if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev);
#endif
}
else {
#ifdef CONFIG_RTW_NETIF_SG
/* After turning on SG, net stack may (0.0025%) TX
* strange skb that is skb_has_frag_list() but linear
* (i.e. skb_is_nonlinear() is false). This is out of
* our expectation, so I free fragment list to be
* compatible with our design.
*/
if (skb_has_frag_list(pkt)) {
if (!skb_is_nonlinear(pkt)) {
kfree_skb_list(skb_shinfo(pkt)->frag_list);
skb_shinfo(pkt)->frag_list = NULL;
RTW_DBG("%s:%d free frag list\n", __func__, __LINE__);
} else {
RTW_DBG("%s:%d nonlinear frag list\n", __func__, __LINE__);
}
}
#endif
rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize);
#ifdef CONFIG_TX_SKB_ORPHAN
skb_orphan(pkt);
#endif
ret = rtw_os_tx(pkt, pnetdev);
}
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
return (ret == 0) ? NETDEV_TX_OK : NETDEV_TX_BUSY;
#else
return ret;
#endif
}
#ifdef RTW_PHL_TX
int rtw_os_is_adapter_ready(_adapter *padapter, struct sk_buff *pkt)
{
if (padapter->registrypriv.mp_mode) {
RTW_INFO("MP_TX_DROP_OS_FRAME\n");
return _FALSE;
}
DBG_COUNTER(padapter->tx_logs.os_tx);
if (rtw_if_up(padapter) == _FALSE) {
PHLTX_LOG;
DBG_COUNTER(padapter->tx_logs.os_tx_err_up);
#ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__);
#endif
return _FALSE;
}
if (IS_CH_WAITING(adapter_to_rfctl(padapter))){
PHLTX_LOG;
return _FALSE;
}
if (rtw_linked_check(padapter) == _FALSE){
PHLTX_LOG;
return _FALSE;
}
return _TRUE;
}
int rtw_os_tx(struct sk_buff *pkt, _nic_hdl pnetdev)
{
_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
u16 os_qid = 0;
s32 res = 0;
#ifdef RTW_PHL_DBG_CMD
core_add_record(padapter, REC_TX_DATA, pkt);
#endif
PHLTX_LOG;
if (pkt->len == 0)
return 0;
if ((rtw_os_is_adapter_ready(padapter, pkt) == _FALSE)
#ifdef CONFIG_LAYER2_ROAMING
&& (!padapter->mlmepriv.roam_network)
#endif
)
goto drop_packet;
PHLTX_LOG;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
os_qid = skb_get_queue_mapping(pkt);
#endif
PHLTX_LOG;
if (rtw_core_tx(padapter, &pkt, NULL, os_qid) == FAIL)
goto inc_drop_cnt;
PHLTX_LOG;
goto exit;
drop_packet:
rtw_os_pkt_complete(padapter, pkt);
inc_drop_cnt:
pxmitpriv->tx_drop++;
exit:
return 0;
}
#endif
#ifdef CONFIG_TX_AMSDU_SW_MODE
static void ieee8023_header_to_rfc1042(struct sk_buff *skb, int pads)
{
void *data;
int pad;
__be16 len;
const int headroom = SNAP_SIZE + 2 + pads;
if (!skb)
return;
if (skb_headroom(skb) < headroom) {
RTW_WARN("%s: headroom=%d isn't enough\n", __func__, skb_headroom(skb));
if (pskb_expand_head(skb, headroom, 0, GFP_ATOMIC)) {
RTW_ERR("%s: no headroom=%d for skb\n",
__func__, headroom);
return;
}
}
data = skb_push(skb, headroom);
memset(data, 0, pads);
data += pads;
memmove(data, data + SNAP_SIZE + 2, 2 * ETH_ALEN);
data += 2 * ETH_ALEN;
len = cpu_to_be16(skb->len - pads - 2 * ETH_ALEN - 2);
memcpy(data, &len, 2);
memcpy(data + 2, rtw_rfc1042_header, SNAP_SIZE);
}
void rtw_coalesce_tx_amsdu(_adapter *padapter, struct xmit_frame *pxframes[],
int xf_nr, bool amsdu, u32 *pktlen)
{
struct xmit_frame *head_xframe;
struct xmit_frame *pxframe;
struct sk_buff *skb;
struct sk_buff *head_skb;
struct sk_buff **frag_tail;
int pads;
int i;
/* prepare head xmitframe */
head_xframe = pxframes[0];
head_skb = head_xframe->pkt;
ieee8023_header_to_rfc1042(head_skb, 0);
frag_tail = &skb_shinfo(head_skb)->frag_list;
while (*frag_tail)
frag_tail = &(*frag_tail)->next;
for (i = 1; i < xf_nr; i++) {
pxframe = pxframes[i];
skb = pxframe->pkt;
if (head_skb->len & 0x03)
pads = 4 - (head_skb->len & 0x03);
else
pads = 0;
ieee8023_header_to_rfc1042(skb, pads);
/* free sk accounting to have TP like doing skb_linearize() */
if (skb->destructor)
skb_orphan(skb);
/* add this skb to head_skb */
head_skb->len += skb->len;
head_skb->data_len += skb->len;
*frag_tail = skb;
while (*frag_tail)
frag_tail = &(*frag_tail)->next;
/* free this xframe */
pxframe->pkt = NULL; /* head xframe own */
core_tx_free_xmitframe(padapter, pxframe);
}
/* total skb length (includes all fragments) */
*pktlen = head_skb->len;
}
#endif /* CONFIG_TX_AMSDU_SW_MODE */
|
2301_81045437/rtl8852be
|
os_dep/linux/xmit_linux.c
|
C
|
agpl-3.0
| 17,869
|
/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _OSDEP_SERVICE_C_
#include <drv_types.h>
#ifdef CONFIG_HWSIM
#include "rtw_hwsim_intf.h"
inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb)
{
skb->dev = ndev;
rtw_hwsim_medium_pre_netif_rx(skb);
return netif_rx(skb);
}
#endif /* CONFIG_HWSIM */
u32 rtw_atoi(u8 *s)
{
int num = 0, flag = 0;
int i;
for (i = 0; i <= strlen(s); i++) {
if (s[i] >= '0' && s[i] <= '9')
num = num * 10 + s[i] - '0';
else if (s[0] == '-' && i == 0)
flag = 1;
else
break;
}
if (flag == 1)
num = num * -1;
return num;
}
#if defined(DBG_MEM_ALLOC)
struct rtw_mem_stat {
ATOMIC_T alloc; /* the memory bytes we allocate currently */
ATOMIC_T peak; /* the peak memory bytes we allocate */
ATOMIC_T alloc_cnt; /* the alloc count for alloc currently */
ATOMIC_T alloc_err_cnt; /* the error times we fail to allocate memory */
};
struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)];
#ifdef RTW_MEM_FUNC_STAT
struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)];
#endif
char *MSTAT_TYPE_str[] = {
"VIR",
"PHY",
"SKB",
"USB",
};
#ifdef RTW_MEM_FUNC_STAT
char *MSTAT_FUNC_str[] = {
"UNSP",
"IO",
"TXIO",
"RXIO",
"TX",
"RX",
};
#endif
void rtw_mstat_dump(void *sel)
{
int i;
int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)];
#ifdef RTW_MEM_FUNC_STAT
int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)];
#endif
for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
value_t[0][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc));
value_t[1][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].peak));
value_t[2][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_cnt));
value_t[3][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_err_cnt));
}
#ifdef RTW_MEM_FUNC_STAT
for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
value_f[0][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc));
value_f[1][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].peak));
value_f[2][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_cnt));
value_f[3][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_err_cnt));
}
#endif
RTW_PRINT_SEL(sel, "===================== MSTAT =====================\n");
RTW_PRINT_SEL(sel, "%4s %10s %10s %10s %10s\n", "TAG", "alloc", "peak", "aloc_cnt", "err_cnt");
RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++)
RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_TYPE_str[i], value_t[0][i], value_t[1][i], value_t[2][i], value_t[3][i]);
#ifdef RTW_MEM_FUNC_STAT
RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++)
RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_FUNC_str[i], value_f[0][i], value_f[1][i], value_f[2][i], value_f[3][i]);
#endif
}
void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz)
{
static systime update_time = 0;
int peak, alloc;
int i;
/* initialization */
if (!update_time) {
for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
ATOMIC_SET(&(rtw_mem_type_stat[i].alloc), 0);
ATOMIC_SET(&(rtw_mem_type_stat[i].peak), 0);
ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0);
ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0);
}
#ifdef RTW_MEM_FUNC_STAT
for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
ATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0);
ATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0);
ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0);
ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0);
}
#endif
}
switch (status) {
case MSTAT_ALLOC_SUCCESS:
ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
alloc = ATOMIC_ADD_RETURN(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
peak = ATOMIC_READ(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak));
if (peak < alloc)
ATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc);
#ifdef RTW_MEM_FUNC_STAT
ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
alloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
peak = ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak));
if (peak < alloc)
ATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc);
#endif
break;
case MSTAT_ALLOC_FAIL:
ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt));
#ifdef RTW_MEM_FUNC_STAT
ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt));
#endif
break;
case MSTAT_FREE:
ATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
ATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
#ifdef RTW_MEM_FUNC_STAT
ATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
ATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
#endif
break;
};
/* if (rtw_get_passing_time_ms(update_time) > 5000) { */
/* rtw_mstat_dump(RTW_DBGDUMP); */
update_time = rtw_get_current_time();
/* } */
}
#ifndef SIZE_MAX
#define SIZE_MAX (~(size_t)0)
#endif
struct mstat_sniff_rule {
enum mstat_f flags;
size_t lb;
size_t hb;
};
struct mstat_sniff_rule mstat_sniff_rules[] = {
{MSTAT_TYPE_VIR, 32, 32},
};
int mstat_sniff_rule_num = sizeof(mstat_sniff_rules) / sizeof(struct mstat_sniff_rule);
bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size)
{
int i;
for (i = 0; i < mstat_sniff_rule_num; i++) {
if (mstat_sniff_rules[i].flags == flags
&& mstat_sniff_rules[i].lb <= size
&& mstat_sniff_rules[i].hb >= size)
return _TRUE;
}
return _FALSE;
}
inline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
{
void *p;
if (match_mstat_sniff_rules(flags, sz))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p = _rtw_vmalloc((sz));
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, sz
);
return p;
}
inline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
{
void *p;
if (match_mstat_sniff_rules(flags, sz))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p = _rtw_zvmalloc((sz));
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, sz
);
return p;
}
inline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
{
if (match_mstat_sniff_rules(flags, sz))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
_rtw_vmfree((pbuf), (sz));
rtw_mstat_update(
flags
, MSTAT_FREE
, sz
);
}
inline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
{
void *p;
if (match_mstat_sniff_rules(flags, sz))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p = _rtw_malloc((sz));
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, sz
);
return p;
}
inline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
{
void *p;
if (match_mstat_sniff_rules(flags, sz))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
p = _rtw_zmalloc((sz));
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, sz
);
return p;
}
inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
{
if (match_mstat_sniff_rules(flags, sz))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
_rtw_mfree((pbuf), (sz));
rtw_mstat_update(
flags
, MSTAT_FREE
, sz
);
}
inline void dbg_rtw_skb_mstat_aid(struct sk_buff *skb_head, const enum mstat_f flags, enum mstat_status status)
{
unsigned int truesize = 0;
struct sk_buff *skb;
if (!skb_head)
return;
rtw_mstat_update(flags, status, skb_head->truesize);
skb_walk_frags(skb_head, skb)
rtw_mstat_update(flags, status, skb->truesize);
}
inline struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line)
{
struct sk_buff *skb;
unsigned int truesize = 0;
skb = _rtw_skb_alloc(size);
if (skb)
truesize = skb->truesize;
if (!skb || truesize < size || match_mstat_sniff_rules(flags, truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize);
rtw_mstat_update(
flags
, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, truesize
);
return skb;
}
inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
{
unsigned int truesize = skb->truesize;
if (match_mstat_sniff_rules(flags, truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
dbg_rtw_skb_mstat_aid(skb, flags, MSTAT_FREE);
_rtw_skb_free(skb);
}
inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
{
struct sk_buff *skb_cp;
unsigned int truesize = skb->truesize;
unsigned int cp_truesize = 0;
skb_cp = _rtw_skb_copy(skb);
if (skb_cp)
cp_truesize = skb_cp->truesize;
if (!skb_cp || cp_truesize < truesize || match_mstat_sniff_rules(flags, cp_truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize);
rtw_mstat_update(
flags
, skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, cp_truesize
);
return skb_cp;
}
inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
{
struct sk_buff *skb_cl;
unsigned int truesize = skb->truesize;
unsigned int cl_truesize = 0;
skb_cl = _rtw_skb_clone(skb);
if (skb_cl)
cl_truesize = skb_cl->truesize;
if (!skb_cl || cl_truesize < truesize || match_mstat_sniff_rules(flags, cl_truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize);
rtw_mstat_update(
flags
, skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, cl_truesize
);
return skb_cl;
}
inline int dbg_rtw_skb_linearize(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
{
unsigned int truesize = 0;
int ret;
dbg_rtw_skb_mstat_aid(skb, flags, MSTAT_FREE);
ret = _rtw_skb_linearize(skb);
dbg_rtw_skb_mstat_aid(skb, flags, MSTAT_ALLOC_SUCCESS);
return ret;
}
inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
{
int ret;
unsigned int truesize = skb->truesize;
if (match_mstat_sniff_rules(flags, truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
ret = _rtw_netif_rx(ndev, skb);
rtw_mstat_update(
flags
, MSTAT_FREE
, truesize
);
return ret;
}
#ifdef CONFIG_RTW_NAPI
inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
{
int ret;
unsigned int truesize = skb->truesize;
if (match_mstat_sniff_rules(flags, truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
ret = _rtw_netif_receive_skb(ndev, skb);
rtw_mstat_update(
flags
, MSTAT_FREE
, truesize
);
return ret;
}
#ifdef CONFIG_RTW_GRO
inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
{
int ret;
unsigned int truesize = skb->truesize;
if (match_mstat_sniff_rules(flags, truesize))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
ret = _rtw_napi_gro_receive(napi, skb);
rtw_mstat_update(
flags
, MSTAT_FREE
, truesize
);
return ret;
}
#endif /* CONFIG_RTW_GRO */
#endif /* CONFIG_RTW_NAPI */
inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line)
{
struct sk_buff *skb;
while ((skb = skb_dequeue(list)) != NULL)
dbg_rtw_skb_free(skb, flags, func, line);
}
#ifdef CONFIG_USB_HCI
inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)
{
void *p;
if (match_mstat_sniff_rules(flags, size))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
p = _rtw_usb_buffer_alloc(dev, size, dma);
rtw_mstat_update(
flags
, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
, size
);
return p;
}
inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line)
{
if (match_mstat_sniff_rules(flags, size))
RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
_rtw_usb_buffer_free(dev, size, addr, dma);
rtw_mstat_update(
flags
, MSTAT_FREE
, size
);
}
#endif /* CONFIG_USB_HCI */
#endif /* defined(DBG_MEM_ALLOC) */
void *rtw_malloc2d(int h, int w, size_t size)
{
int j;
void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size);
if (a == NULL) {
RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__);
return NULL;
}
for (j = 0; j < h; j++)
a[j] = ((char *)(a + h)) + j * w * size;
return a;
}
void rtw_mfree2d(void *pbuf, int h, int w, int size)
{
rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size);
}
int _rtw_memcmp2(const void *dst, const void *src, u32 sz)
{
const unsigned char *p1 = dst, *p2 = src;
if (sz == 0)
return 0;
while (*p1 == *p2) {
p1++;
p2++;
sz--;
if (sz == 0)
return 0;
}
return *p1 - *p2;
}
void _rtw_init_queue(_queue *pqueue)
{
_rtw_init_listhead(&(pqueue->queue));
_rtw_spinlock_init(&(pqueue->lock));
}
void _rtw_deinit_queue(_queue *pqueue)
{
_rtw_spinlock_free(&(pqueue->lock));
}
u32 _rtw_queue_empty(_queue *pqueue)
{
return rtw_is_list_empty(&(pqueue->queue));
}
u32 rtw_end_of_queue_search(_list *head, _list *plist)
{
if (head == plist)
return _TRUE;
else
return _FALSE;
}
/* the input parameter start use the same unit as returned by rtw_get_current_time */
inline s32 _rtw_get_passing_time_ms(systime start)
{
return _rtw_systime_to_ms(_rtw_get_current_time() - start);
}
inline s32 _rtw_get_remaining_time_ms(systime end)
{
return _rtw_systime_to_ms(end - _rtw_get_current_time());
}
inline s32 _rtw_get_time_interval_ms(systime start, systime end)
{
return _rtw_systime_to_ms(end - start);
}
bool rtw_macaddr_is_larger(const u8 *a, const u8 *b)
{
u32 va, vb;
va = be32_to_cpu(*((u32 *)a));
vb = be32_to_cpu(*((u32 *)b));
if (va > vb)
return 1;
else if (va < vb)
return 0;
return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4)));
}
/*
* Test if the specifi @param path is a readable file with valid size.
* If readable, @param sz is got
* @param path the path of the file to test
* @return _TRUE or _FALSE
*/
int rtw_readable_file_sz_chk(const char *path, u32 sz)
{
u32 fsz;
if (rtw_is_file_readable_with_size(path, &fsz) == _FALSE)
return _FALSE;
if (fsz > sz)
return _FALSE;
return _TRUE;
}
void rtw_buf_free(u8 **buf, u32 *buf_len)
{
u32 ori_len;
if (!buf || !buf_len)
return;
ori_len = *buf_len;
if (*buf) {
u32 tmp_buf_len = *buf_len;
*buf_len = 0;
rtw_mfree(*buf, tmp_buf_len);
*buf = NULL;
}
}
void rtw_buf_update(u8 **buf, u32 *buf_len, const u8 *src, u32 src_len)
{
u32 ori_len = 0, dup_len = 0;
u8 *ori = NULL;
u8 *dup = NULL;
if (!buf || !buf_len)
return;
if (!src || !src_len)
goto keep_ori;
/* duplicate src */
dup = rtw_malloc(src_len);
if (dup) {
dup_len = src_len;
_rtw_memcpy(dup, src, dup_len);
}
keep_ori:
ori = *buf;
ori_len = *buf_len;
/* replace buf with dup */
*buf_len = 0;
*buf = dup;
*buf_len = dup_len;
/* free ori */
if (ori && ori_len > 0)
rtw_mfree(ori, ori_len);
}
/**
* rtw_cbuf_full - test if cbuf is full
* @cbuf: pointer of struct rtw_cbuf
*
* Returns: _TRUE if cbuf is full
*/
inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf)
{
return (cbuf->write == cbuf->read - 1) ? _TRUE : _FALSE;
}
/**
* rtw_cbuf_empty - test if cbuf is empty
* @cbuf: pointer of struct rtw_cbuf
*
* Returns: _TRUE if cbuf is empty
*/
inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)
{
return (cbuf->write == cbuf->read) ? _TRUE : _FALSE;
}
/**
* rtw_cbuf_push - push a pointer into cbuf
* @cbuf: pointer of struct rtw_cbuf
* @buf: pointer to push in
*
* Lock free operation, be careful of the use scheme
* Returns: _TRUE push success
*/
bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf)
{
if (rtw_cbuf_full(cbuf))
return _FAIL;
if (0)
RTW_INFO("%s on %u\n", __func__, cbuf->write);
cbuf->bufs[cbuf->write] = buf;
cbuf->write = (cbuf->write + 1) % cbuf->size;
return _SUCCESS;
}
/**
* rtw_cbuf_pop - pop a pointer from cbuf
* @cbuf: pointer of struct rtw_cbuf
*
* Lock free operation, be careful of the use scheme
* Returns: pointer popped out
*/
void *rtw_cbuf_pop(struct rtw_cbuf *cbuf)
{
void *buf;
if (rtw_cbuf_empty(cbuf))
return NULL;
if (0)
RTW_INFO("%s on %u\n", __func__, cbuf->read);
buf = cbuf->bufs[cbuf->read];
cbuf->read = (cbuf->read + 1) % cbuf->size;
return buf;
}
/**
* rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization
* @size: size of pointer
*
* Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure
*/
struct rtw_cbuf *rtw_cbuf_alloc(u32 size)
{
struct rtw_cbuf *cbuf;
cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void *) * size);
if (cbuf) {
cbuf->write = cbuf->read = 0;
cbuf->size = size;
}
return cbuf;
}
/**
* rtw_cbuf_free - free the given rtw_cbuf
* @cbuf: pointer of struct rtw_cbuf to free
*/
void rtw_cbuf_free(struct rtw_cbuf *cbuf)
{
rtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size);
}
/**
* map_readN - read a range of map data
* @map: map to read
* @offset: start address to read
* @len: length to read
* @buf: pointer of buffer to store data read
*
* Returns: _SUCCESS or _FAIL
*/
int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf)
{
const struct map_seg_t *seg;
int ret = _FAIL;
int i;
if (len == 0) {
rtw_warn_on(1);
goto exit;
}
if (offset + len > map->len) {
rtw_warn_on(1);
goto exit;
}
_rtw_memset(buf, map->init_value, len);
for (i = 0; i < map->seg_num; i++) {
u8 *c_dst, *c_src;
u16 c_len;
seg = map->segs + i;
if (seg->sa + seg->len <= offset || seg->sa >= offset + len)
continue;
if (seg->sa >= offset) {
c_dst = buf + (seg->sa - offset);
c_src = seg->c;
if (seg->sa + seg->len <= offset + len)
c_len = seg->len;
else
c_len = offset + len - seg->sa;
} else {
c_dst = buf;
c_src = seg->c + (offset - seg->sa);
if (seg->sa + seg->len >= offset + len)
c_len = len;
else
c_len = seg->sa + seg->len - offset;
}
_rtw_memcpy(c_dst, c_src, c_len);
}
exit:
return ret;
}
/**
* map_read8 - read 1 byte of map data
* @map: map to read
* @offset: address to read
*
* Returns: value of data of specified offset. map.init_value if offset is out of range
*/
u8 map_read8(const struct map_t *map, u16 offset)
{
const struct map_seg_t *seg;
u8 val = map->init_value;
int i;
if (offset + 1 > map->len) {
rtw_warn_on(1);
goto exit;
}
for (i = 0; i < map->seg_num; i++) {
seg = map->segs + i;
if (seg->sa + seg->len <= offset || seg->sa >= offset + 1)
continue;
val = *(seg->c + offset - seg->sa);
break;
}
exit:
return val;
}
int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms)
{
struct blacklist_ent *ent;
_list *list, *head;
u8 exist = _FALSE, timeout = _FALSE;
_rtw_spinlock_bh(&blist->lock);
head = &blist->queue;
list = get_next(head);
while (rtw_end_of_queue_search(head, list) == _FALSE) {
ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
list = get_next(list);
if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
exist = _TRUE;
if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
timeout = _TRUE;
ent->exp_time = rtw_get_current_time()
+ rtw_ms_to_systime(timeout_ms);
break;
}
if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
rtw_list_delete(&ent->list);
rtw_mfree(ent, sizeof(struct blacklist_ent));
}
}
if (exist == _FALSE) {
ent = rtw_malloc(sizeof(struct blacklist_ent));
if (ent) {
_rtw_memcpy(ent->addr, addr, ETH_ALEN);
ent->exp_time = rtw_get_current_time()
+ rtw_ms_to_systime(timeout_ms);
rtw_list_insert_tail(&ent->list, head);
}
}
_rtw_spinunlock_bh(&blist->lock);
return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
}
int rtw_blacklist_del(_queue *blist, const u8 *addr)
{
struct blacklist_ent *ent = NULL;
_list *list, *head;
u8 exist = _FALSE;
_rtw_spinlock_bh(&blist->lock);
head = &blist->queue;
list = get_next(head);
while (rtw_end_of_queue_search(head, list) == _FALSE) {
ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
list = get_next(list);
if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
rtw_list_delete(&ent->list);
rtw_mfree(ent, sizeof(struct blacklist_ent));
exist = _TRUE;
break;
}
if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
rtw_list_delete(&ent->list);
rtw_mfree(ent, sizeof(struct blacklist_ent));
}
}
_rtw_spinunlock_bh(&blist->lock);
return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
}
int rtw_blacklist_search(_queue *blist, const u8 *addr)
{
struct blacklist_ent *ent = NULL;
_list *list, *head;
u8 exist = _FALSE;
_rtw_spinlock_bh(&blist->lock);
head = &blist->queue;
list = get_next(head);
while (rtw_end_of_queue_search(head, list) == _FALSE) {
ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
list = get_next(list);
if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
rtw_list_delete(&ent->list);
rtw_mfree(ent, sizeof(struct blacklist_ent));
} else
exist = _TRUE;
break;
}
if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
rtw_list_delete(&ent->list);
rtw_mfree(ent, sizeof(struct blacklist_ent));
}
}
_rtw_spinunlock_bh(&blist->lock);
return exist;
}
void rtw_blacklist_flush(_queue *blist)
{
struct blacklist_ent *ent;
_list *list, *head;
_list tmp;
_rtw_init_listhead(&tmp);
_rtw_spinlock_bh(&blist->lock);
rtw_list_splice_init(&blist->queue, &tmp);
_rtw_spinunlock_bh(&blist->lock);
head = &tmp;
list = get_next(head);
while (rtw_end_of_queue_search(head, list) == _FALSE) {
ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
list = get_next(list);
rtw_list_delete(&ent->list);
rtw_mfree(ent, sizeof(struct blacklist_ent));
}
}
void dump_blacklist(void *sel, _queue *blist, const char *title)
{
struct blacklist_ent *ent = NULL;
_list *list, *head;
_rtw_spinlock_bh(&blist->lock);
head = &blist->queue;
list = get_next(head);
if (rtw_end_of_queue_search(head, list) == _FALSE) {
if (title)
RTW_PRINT_SEL(sel, "%s:\n", title);
while (rtw_end_of_queue_search(head, list) == _FALSE) {
ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
list = get_next(list);
if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
RTW_PRINT_SEL(sel, MAC_FMT" expired\n", MAC_ARG(ent->addr));
else
RTW_PRINT_SEL(sel, MAC_FMT" %u\n", MAC_ARG(ent->addr)
, rtw_get_remaining_time_ms(ent->exp_time));
}
}
_rtw_spinunlock_bh(&blist->lock);
}
/**
* is_null -
*
* Return TRUE if c is null character
* FALSE otherwise.
*/
inline BOOLEAN is_null(char c)
{
if (c == '\0')
return _TRUE;
else
return _FALSE;
}
inline BOOLEAN is_all_null(char *c, int len)
{
for (; len > 0; len--)
if (c[len - 1] != '\0')
return _FALSE;
return _TRUE;
}
/**
* is_eol -
*
* Return TRUE if c is represent for EOL (end of line)
* FALSE otherwise.
*/
inline BOOLEAN is_eol(char c)
{
if (c == '\r' || c == '\n')
return _TRUE;
else
return _FALSE;
}
/**
* is_space -
*
* Return TRUE if c is represent for space
* FALSE otherwise.
*/
inline BOOLEAN is_space(char c)
{
if (c == ' ' || c == '\t')
return _TRUE;
else
return _FALSE;
}
/**
* is_decimal -
*
* Return TRUE if chTmp is represent for decimal digit
* FALSE otherwise.
*/
inline BOOLEAN is_decimal(char chTmp)
{
if ((chTmp >= '0' && chTmp <= '9'))
return _TRUE;
else
return _FALSE;
}
/**
* IsHexDigit -
*
* Return TRUE if chTmp is represent for hex digit
* FALSE otherwise.
*/
inline BOOLEAN IsHexDigit(char chTmp)
{
if ((chTmp >= '0' && chTmp <= '9') ||
(chTmp >= 'a' && chTmp <= 'f') ||
(chTmp >= 'A' && chTmp <= 'F'))
return _TRUE;
else
return _FALSE;
}
/**
* is_alpha -
*
* Return TRUE if chTmp is represent for alphabet
* FALSE otherwise.
*/
inline BOOLEAN is_alpha(char chTmp)
{
if ((chTmp >= 'a' && chTmp <= 'z') ||
(chTmp >= 'A' && chTmp <= 'Z'))
return _TRUE;
else
return _FALSE;
}
inline char alpha_to_upper(char c)
{
if ((c >= 'a' && c <= 'z'))
c = 'A' + (c - 'a');
return c;
}
int hex2num_i(char c)
{
if (c >= '0' && c <= '9')
return c - '0';
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
return -1;
}
int hex2byte_i(const char *hex)
{
int a, b;
a = hex2num_i(*hex++);
if (a < 0)
return -1;
b = hex2num_i(*hex++);
if (b < 0)
return -1;
return (a << 4) | b;
}
int hexstr2bin(const char *hex, u8 *buf, size_t len)
{
size_t i;
int a;
const char *ipos = hex;
u8 *opos = buf;
for (i = 0; i < len; i++) {
a = hex2byte_i(ipos);
if (a < 0)
return -1;
*opos++ = a;
ipos += 2;
}
return 0;
}
|
2301_81045437/rtl8852be
|
os_dep/osdep_service.c
|
C
|
agpl-3.0
| 26,218
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _OSDEP_SERVICE_LINUX_C_
#include <drv_types.h>
#ifdef DBG_MEMORY_LEAK
ATOMIC_T _malloc_cnt = ATOMIC_INIT(0);
ATOMIC_T _malloc_size = ATOMIC_INIT(0);
#endif /* DBG_MEMORY_LEAK */
/*
* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE
* @return: one of RTW_STATUS_CODE
*/
inline int RTW_STATUS_CODE(int error_code)
{
if (error_code >= 0)
return _SUCCESS;
switch (error_code) {
/* case -ETIMEDOUT: */
/* return RTW_STATUS_TIMEDOUT; */
default:
return _FAIL;
}
}
void _rtw_skb_queue_purge(struct sk_buff_head *list)
{
struct sk_buff *skb;
while ((skb = skb_dequeue(list)) != NULL)
_rtw_skb_free(skb);
}
void _rtw_memcpy(void *dst, const void *src, u32 sz)
{
memcpy(dst, src, sz);
}
inline void _rtw_memmove(void *dst, const void *src, u32 sz)
{
memmove(dst, src, sz);
}
int _rtw_memcmp(const void *dst, const void *src, u32 sz)
{
/* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */
if (!(memcmp(dst, src, sz)))
return _TRUE;
else
return _FALSE;
}
void _rtw_memset(void *pbuf, int c, u32 sz)
{
memset(pbuf, c, sz);
}
void _rtw_init_listhead(_list *list)
{
INIT_LIST_HEAD(list);
}
/*
For the following list_xxx operations,
caller must guarantee the atomic context.
Otherwise, there will be racing condition.
*/
u32 rtw_is_list_empty(_list *phead)
{
if (list_empty(phead))
return _TRUE;
else
return _FALSE;
}
void rtw_list_insert_head(_list *plist, _list *phead)
{
list_add(plist, phead);
}
void rtw_list_insert_tail(_list *plist, _list *phead)
{
list_add_tail(plist, phead);
}
inline void rtw_list_splice(_list *list, _list *head)
{
list_splice(list, head);
}
inline void rtw_list_splice_init(_list *list, _list *head)
{
list_splice_init(list, head);
}
inline void rtw_list_splice_tail(_list *list, _list *head)
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
if (!list_empty(list))
__list_splice(list, head);
#else
list_splice_tail(list, head);
#endif
}
inline void rtw_hlist_head_init(rtw_hlist_head *h)
{
INIT_HLIST_HEAD(h);
}
inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h)
{
hlist_add_head(n, h);
}
inline void rtw_hlist_del(rtw_hlist_node *n)
{
hlist_del(n);
}
inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h)
{
hlist_add_head_rcu(n, h);
}
inline void rtw_hlist_del_rcu(rtw_hlist_node *n)
{
hlist_del_rcu(n);
}
void rtw_init_timer(_timer *ptimer, void *pfunc, void *ctx)
{
_init_timer(ptimer, pfunc, ctx);
}
systime _rtw_get_current_time(void)
{
return jiffies;
}
inline u32 _rtw_systime_to_ms(systime stime)
{
return jiffies_to_msecs(stime);
}
inline u32 _rtw_systime_to_us(systime stime)
{
return jiffies_to_usecs(stime);
}
inline systime _rtw_ms_to_systime(u32 ms)
{
return msecs_to_jiffies(ms);
}
inline systime _rtw_us_to_systime(u32 us)
{
return usecs_to_jiffies(us);
}
inline bool _rtw_time_after(systime a, systime b)
{
return time_after(a, b);
}
void rtw_sleep_schedulable(int ms)
{
u32 delta;
delta = (ms * HZ) / 1000; /* (ms) */
if (delta == 0) {
delta = 1;/* 1 ms */
}
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(delta);
return;
}
void rtw_msleep_os(int ms)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
if (ms < 20) {
unsigned long us = ms * 1000UL;
usleep_range(us, us + 1000UL);
} else
#endif
msleep((unsigned int)ms);
}
void rtw_usleep_os(int us)
{
/* msleep((unsigned int)us); */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
usleep_range(us, us + 1);
#else
if (1 < (us / 1000))
msleep(1);
else
msleep((us / 1000) + 1);
#endif
}
#ifdef DBG_DELAY_OS
void _rtw_mdelay_os(int ms, const char *func, const int line)
{
RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
mdelay((unsigned long)ms);
}
void _rtw_udelay_os(int us, const char *func, const int line)
{
RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
udelay((unsigned long)us);
}
#else
void rtw_mdelay_os(int ms)
{
mdelay((unsigned long)ms);
}
void rtw_udelay_os(int us)
{
udelay((unsigned long)us);
}
#endif
void rtw_yield_os(void)
{
yield();
}
#define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic"
#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume"
#ifdef CONFIG_WAKELOCK
static struct wake_lock rtw_suspend_lock;
static struct wake_lock rtw_suspend_traffic_lock;
static struct wake_lock rtw_suspend_resume_lock;
#elif defined(CONFIG_ANDROID_POWER)
static android_suspend_lock_t rtw_suspend_lock = {
.name = RTW_SUSPEND_LOCK_NAME
};
static android_suspend_lock_t rtw_suspend_traffic_lock = {
.name = RTW_SUSPEND_TRAFFIC_LOCK_NAME
};
static android_suspend_lock_t rtw_suspend_resume_lock = {
.name = RTW_SUSPEND_RESUME_LOCK_NAME
};
#endif
inline void rtw_suspend_lock_init(void)
{
#ifdef CONFIG_WAKELOCK
wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);
wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME);
wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME);
#elif defined(CONFIG_ANDROID_POWER)
android_init_suspend_lock(&rtw_suspend_lock);
android_init_suspend_lock(&rtw_suspend_traffic_lock);
android_init_suspend_lock(&rtw_suspend_resume_lock);
#endif
}
inline void rtw_suspend_lock_uninit(void)
{
#ifdef CONFIG_WAKELOCK
wake_lock_destroy(&rtw_suspend_lock);
wake_lock_destroy(&rtw_suspend_traffic_lock);
wake_lock_destroy(&rtw_suspend_resume_lock);
#elif defined(CONFIG_ANDROID_POWER)
android_uninit_suspend_lock(&rtw_suspend_lock);
android_uninit_suspend_lock(&rtw_suspend_traffic_lock);
android_uninit_suspend_lock(&rtw_suspend_resume_lock);
#endif
}
inline void rtw_lock_suspend(void)
{
#ifdef CONFIG_WAKELOCK
wake_lock(&rtw_suspend_lock);
#elif defined(CONFIG_ANDROID_POWER)
android_lock_suspend(&rtw_suspend_lock);
#endif
#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
#endif
}
inline void rtw_unlock_suspend(void)
{
#ifdef CONFIG_WAKELOCK
wake_unlock(&rtw_suspend_lock);
#elif defined(CONFIG_ANDROID_POWER)
android_unlock_suspend(&rtw_suspend_lock);
#endif
#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
#endif
}
inline void rtw_resume_lock_suspend(void)
{
#ifdef CONFIG_WAKELOCK
wake_lock(&rtw_suspend_resume_lock);
#elif defined(CONFIG_ANDROID_POWER)
android_lock_suspend(&rtw_suspend_resume_lock);
#endif
#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
#endif
}
inline void rtw_resume_unlock_suspend(void)
{
#ifdef CONFIG_WAKELOCK
wake_unlock(&rtw_suspend_resume_lock);
#elif defined(CONFIG_ANDROID_POWER)
android_unlock_suspend(&rtw_suspend_resume_lock);
#endif
#if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
#endif
}
inline void rtw_lock_suspend_timeout(u32 timeout_ms)
{
#ifdef CONFIG_WAKELOCK
wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
#elif defined(CONFIG_ANDROID_POWER)
android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
#endif
}
inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms)
{
#ifdef CONFIG_WAKELOCK
wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
#elif defined(CONFIG_ANDROID_POWER)
android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
#endif
/* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */
}
inline void rtw_set_bit(int nr, unsigned long *addr)
{
set_bit(nr, addr);
}
inline void rtw_clear_bit(int nr, unsigned long *addr)
{
clear_bit(nr, addr);
}
inline int rtw_test_and_clear_bit(int nr, unsigned long *addr)
{
return test_and_clear_bit(nr, addr);
}
inline int rtw_test_and_set_bit(int nr, unsigned long *addr)
{
return test_and_set_bit(nr, addr);
}
/*
* Open a file with the specific @param path, @param flag, @param mode
* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success
* @param path the path of the file to open
* @param flag file operation flags, please refer to linux document
* @param mode please refer to linux document
* @return Linux specific error code
*/
static int openFile(struct file **fpp, const char *path, int flag, int mode)
{
struct file *fp;
fp = filp_open(path, flag, mode);
if (IS_ERR(fp)) {
*fpp = NULL;
return PTR_ERR(fp);
} else {
*fpp = fp;
return 0;
}
}
/*
* Close the file with the specific @param fp
* @param fp the pointer of struct file to close
* @return always 0
*/
static int closeFile(struct file *fp)
{
filp_close(fp, NULL);
return 0;
}
static int readFile(struct file *fp, char *buf, int len)
{
int rlen = 0, sum = 0;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
if (!(fp->f_mode & FMODE_CAN_READ))
#else
if (!fp->f_op || !fp->f_op->read)
#endif
return -EPERM;
while (sum < len) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos);
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos);
#else
rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos);
#endif
if (rlen > 0)
sum += rlen;
else if (0 != rlen)
return rlen;
else
break;
}
return sum;
}
#ifndef CONFIG_RTW_ANDROID
static int writeFile(struct file *fp, char *buf, int len)
{
int wlen = 0, sum = 0;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
if (!(fp->f_mode & FMODE_CAN_WRITE))
#else
if (!fp->f_op || !fp->f_op->write)
#endif
return -EPERM;
while (sum < len) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
wlen = kernel_write(fp, buf + sum, len - sum, &fp->f_pos);
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
wlen = __vfs_write(fp, buf + sum, len - sum, &fp->f_pos);
#else
wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos);
#endif
if (wlen > 0)
sum += wlen;
else if (0 != wlen)
return wlen;
else
break;
}
return sum;
}
/*
* Test if the specifi @param pathname is a direct and readable
* If readable, @param sz is not used
* @param pathname the name of the path to test
* @return Linux specific error code
*/
static int isDirReadable(const char *pathname, u32 *sz)
{
struct path path;
int error = 0;
return kern_path(pathname, LOOKUP_FOLLOW, &path);
}
#endif /* CONFIG_RTW_ANDROID */
/*
* Test if the specifi @param path is a file and readable
* If readable, @param sz is got
* @param path the path of the file to test
* @return Linux specific error code
*/
static int isFileReadable(const char *path, u32 *sz)
{
struct file *fp;
int ret = 0;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
mm_segment_t oldfs;
#endif
char buf;
fp = filp_open(path, O_RDONLY, 0);
if (IS_ERR(fp))
ret = PTR_ERR(fp);
else {
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
oldfs = get_fs();
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
set_fs(KERNEL_DS);
#else
set_fs(get_ds());
#endif
#endif
if (1 != readFile(fp, &buf, 1))
ret = PTR_ERR(fp);
if (ret == 0 && sz) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
*sz = i_size_read(fp->f_path.dentry->d_inode);
#else
*sz = i_size_read(fp->f_dentry->d_inode);
#endif
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
set_fs(oldfs);
#endif
filp_close(fp, NULL);
}
return ret;
}
/*
* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
* @param path the path of the file to open and read
* @param buf the starting address of the buffer to store file content
* @param sz how many bytes to read at most
* @return the byte we've read, or Linux specific error code
*/
static int retriveFromFile(const char *path, u8 *buf, u32 sz)
{
int ret = -1;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
mm_segment_t oldfs;
#endif
struct file *fp;
if (path && buf) {
ret = openFile(&fp, path, O_RDONLY, 0);
if (0 == ret) {
RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
oldfs = get_fs();
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
set_fs(KERNEL_DS);
#else
set_fs(get_ds());
#endif
#endif
ret = readFile(fp, buf, sz);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
set_fs(oldfs);
#endif
closeFile(fp);
RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret);
} else
RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
} else {
RTW_INFO("%s NULL pointer\n", __FUNCTION__);
ret = -EINVAL;
}
return ret;
}
#ifndef CONFIG_RTW_ANDROID
/*
* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
* @param path the path of the file to open and write
* @param buf the starting address of the data to write into file
* @param sz how many bytes to write at most
* @return the byte we've written, or Linux specific error code
*/
static int storeToFile(const char *path, u8 *buf, u32 sz)
{
int ret = 0;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
mm_segment_t oldfs;
#endif
struct file *fp;
if (path && buf) {
ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666);
if (0 == ret) {
RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
oldfs = get_fs();
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
set_fs(KERNEL_DS);
#else
set_fs(get_ds());
#endif
#endif
ret = writeFile(fp, buf, sz);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
set_fs(oldfs);
#endif
closeFile(fp);
RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret);
} else
RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
} else {
RTW_INFO("%s NULL pointer\n", __FUNCTION__);
ret = -EINVAL;
}
return ret;
}
/*
* Test if the specifi @param path is a direct and readable
* @param path the path of the direct to test
* @return _TRUE or _FALSE
*/
int rtw_is_dir_readable(const char *path)
{
if (isDirReadable(path, NULL) == 0)
return _TRUE;
else
return _FALSE;
}
#endif /* CONFIG_RTW_ANDROID */
/*
* Test if the specifi @param path is a file and readable
* @param path the path of the file to test
* @return _TRUE or _FALSE
*/
int rtw_is_file_readable(const char *path)
{
if (isFileReadable(path, NULL) == 0)
return _TRUE;
else
return _FALSE;
}
/*
* Test if the specifi @param path is a file and readable.
* If readable, @param sz is got
* @param path the path of the file to test
* @return _TRUE or _FALSE
*/
int rtw_is_file_readable_with_size(const char *path, u32 *sz)
{
if (isFileReadable(path, sz) == 0)
return _TRUE;
else
return _FALSE;
}
/*
* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
* @param path the path of the file to open and read
* @param buf the starting address of the buffer to store file content
* @param sz how many bytes to read at most
* @return the byte we've read
*/
int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz)
{
int ret = retriveFromFile(path, buf, sz);
return ret >= 0 ? ret : 0;
}
#ifndef CONFIG_RTW_ANDROID
/*
* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
* @param path the path of the file to open and write
* @param buf the starting address of the data to write into file
* @param sz how many bytes to write at most
* @return the byte we've written
*/
int rtw_store_to_file(const char *path, u8 *buf, u32 sz)
{
int ret = storeToFile(path, buf, sz);
return ret >= 0 ? ret : 0;
}
#endif /* CONFIG_RTW_ANDROID */
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv)
{
struct net_device *pnetdev;
struct rtw_netdev_priv_indicator *pnpi;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
#else
pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
#endif
if (!pnetdev)
goto RETURN;
pnpi = netdev_priv(pnetdev);
pnpi->priv = old_priv;
pnpi->sizeof_priv = sizeof_priv;
RETURN:
return pnetdev;
}
struct net_device *rtw_alloc_etherdev(int sizeof_priv)
{
struct net_device *pnetdev;
struct rtw_netdev_priv_indicator *pnpi;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
#else
pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
#endif
if (!pnetdev)
goto RETURN;
pnpi = netdev_priv(pnetdev);
pnpi->priv = rtw_zvmalloc(sizeof_priv);
if (!pnpi->priv) {
free_netdev(pnetdev);
pnetdev = NULL;
goto RETURN;
}
pnpi->sizeof_priv = sizeof_priv;
RETURN:
return pnetdev;
}
void rtw_free_netdev(struct net_device *netdev)
{
struct rtw_netdev_priv_indicator *pnpi;
if (!netdev)
goto RETURN;
pnpi = netdev_priv(netdev);
if (!pnpi->priv)
goto RETURN;
free_netdev(netdev);
RETURN:
return;
}
int rtw_change_ifname(_adapter *padapter, const char *ifname)
{
struct dvobj_priv *dvobj;
struct net_device *pnetdev;
struct net_device *cur_pnetdev;
struct rereg_nd_name_data *rereg_priv;
int ret;
u8 rtnl_lock_needed;
if (!padapter)
goto error;
dvobj = adapter_to_dvobj(padapter);
cur_pnetdev = padapter->pnetdev;
rereg_priv = &padapter->rereg_nd_name_priv;
/* free the old_pnetdev */
if (rereg_priv->old_pnetdev) {
free_netdev(rereg_priv->old_pnetdev);
rereg_priv->old_pnetdev = NULL;
}
rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
if (rtnl_lock_needed)
unregister_netdev(cur_pnetdev);
else
unregister_netdevice(cur_pnetdev);
rereg_priv->old_pnetdev = cur_pnetdev;
pnetdev = rtw_init_netdev(padapter);
if (!pnetdev) {
ret = -1;
goto error;
}
SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter)));
rtw_init_netdev_name(pnetdev, ifname);
_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
if (rtnl_lock_needed)
ret = register_netdev(pnetdev);
else
ret = register_netdevice(pnetdev);
if (ret != 0) {
goto error;
}
return 0;
error:
return -1;
}
#ifdef CONFIG_PLATFORM_SPRD
#ifdef do_div
#undef do_div
#endif
#include <asm-generic/div64.h>
#endif
u64 rtw_modular64(u64 x, u64 y)
{
return do_div(x, y);
}
u64 rtw_division64(u64 x, u64 y)
{
do_div(x, y);
return x;
}
inline u32 rtw_random32(void)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
return prandom_u32();
#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18))
u32 random_int;
get_random_bytes(&random_int , 4);
return random_int;
#else
return random32();
#endif
}
|
2301_81045437/rtl8852be
|
os_dep/osdep_service_linux.c
|
C
|
agpl-3.0
| 19,671
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CUSTOM_C_
#include "../phl_headers.h"
#include "phl_custom_fb.h"
#ifdef CONFIG_PHL_CUSTOM_FEATURE
#define MAX_DATA_SIZE (512)
enum custom_status {
CUS_STAT_CMD_USED = BIT0,
CUS_STAT_RPT_USED = BIT1,
CUS_STAT_RPT_SENDING = BIT2,
};
struct phl_custom_ctx {
struct phl_info_t *phl_info;
u8 status; /* refer to enum custom_status*/
u8 cmd_buf[MAX_DATA_SIZE];
u8 rpt_buf[MAX_DATA_SIZE];
#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB
struct _custom_facebook_ctx fb_ctx;
#endif
};
bool
_custom_rpt_notify_check(void* priv, struct phl_msg* msg)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv;
bool ret = true;
if (!TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED) ||
TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_SENDING)) {
ret = false;
}
return ret;
}
void
_custom_rpt_notify_complete(void* priv, struct phl_msg* msg)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv;
CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED);
CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_RPT_SENDING);
}
void
_custom_rpt_notify_start(void* priv,
struct phl_msg* msg,
struct phl_msg_attribute* attr)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv;
struct rtw_custom_decrpt *evt_rpt = (struct rtw_custom_decrpt *)ctx->rpt_buf;
SET_STATUS_FLAG(ctx->status, CUS_STAT_RPT_SENDING);
SET_MSG_MDL_ID_FIELD(msg->msg_id, PHL_MDL_CUSTOM);
SET_MSG_EVT_ID_FIELD(msg->msg_id, MSG_EVT_CUSTOM_CMD_DONE);
msg->inbuf = (u8*) evt_rpt;
msg->inlen = evt_rpt->len + sizeof(struct rtw_custom_decrpt);
attr->completion.completion = _custom_rpt_notify_complete;
attr->completion.priv = ctx;
}
static void
_indicate_custome_evt_rpt(struct phl_custom_ctx *ctx)
{
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
if (!_custom_rpt_notify_check((void*)ctx, &msg))
return;
_custom_rpt_notify_start((void*)ctx, &msg, &attr);
if (phl_msg_hub_send(ctx->phl_info,
&attr, &msg) != RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s send msg fail\n", __func__);
_custom_rpt_notify_complete((void*)ctx, &msg);
}
}
enum rtw_phl_status
_phl_custom_prepare_default_fail_rpt(struct phl_custom_ctx *ctx,
struct phl_msg* msg)
{
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
u8 ret = MDL_RET_FAIL;
if (TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED))
return RTW_PHL_STATUS_RESOURCE;
phl_custom_prepare_evt_rpt(ctx,
cmd->evt_id,
cmd->customer_id,
&ret,
1);
return RTW_PHL_STATUS_SUCCESS;
}
static enum phl_mdl_ret_code
_phl_custom_hdl_fail_evt(void* dispr,
struct phl_custom_ctx* ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct rtw_custom_decrpt *cmd = NULL;
cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_EDCA_ADJUST:
#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB
if(cmd->customer_id == CUS_ID_FB) {
ret = phl_custom_hdl_fb_fail_evt(dispr,
ctx,
&(ctx->fb_ctx),
msg);
}
#else
ret = MDL_RET_IGNORE;
#endif
break;
default:
ret = MDL_RET_IGNORE;
break;
}
return ret;
}
static enum phl_mdl_ret_code
_phl_custom_hdl_internal_evt(void* dispr,
struct phl_custom_ctx* ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
struct rtw_custom_decrpt *cmd = NULL;
cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_CUSTOME_FEATURE_ENABLE:
case MSG_EVT_CUSTOME_FEATURE_QUERY:
case MSG_EVT_CUSTOME_TESTMODE_PARAM:
case MSG_EVT_CUSTOME_SET_WIFI_ROLE:
case MSG_EVT_AMPDU_CFG:
case MSG_EVT_AMPDU_QUERY:
case MSG_EVT_PDTHR_CFG:
case MSG_EVT_PDTHR_QUERY:
case MSG_EVT_POP_CFG:
case MSG_EVT_POP_QUERY:
#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB
if(cmd->customer_id == CUS_ID_FB) {
ret = phl_custom_hdl_fb_evt(dispr,
ctx,
&(ctx->fb_ctx),
msg);
}
#else
ret = MDL_RET_IGNORE;
#endif
break;
default:
ret = MDL_RET_IGNORE;
break;
}
return ret;
}
static enum phl_mdl_ret_code
_phl_custom_hdl_external_evt(void* dispr,
struct phl_custom_ctx* ctx,
struct phl_msg* msg)
{
return MDL_RET_IGNORE;
}
void
_phl_custom_cmd_completion(void* priv, struct phl_msg* msg)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv;
CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED);
}
enum phl_mdl_ret_code
_phl_custom_mdl_init(void* phl_info,
void* dispr,
void** priv)
{
struct phl_info_t *phl = (struct phl_info_t *)phl_info;
struct phl_custom_ctx* ctx = NULL;
void *d = phl_to_drvpriv(phl);
FUNCIN();
if (priv == NULL)
return MDL_RET_FAIL;
(*priv) = NULL;
ctx = (struct phl_custom_ctx *)_os_mem_alloc(d, sizeof(struct phl_custom_ctx));
if (ctx == NULL) {
PHL_ERR(" %s, alloc fail\n",__FUNCTION__);
return MDL_RET_FAIL;
}
ctx->phl_info = phl_info;
(*priv) = (void*)ctx;
PHL_INFO(" %s, size phl_custom_ctx(%d)\n",
__FUNCTION__, (int)sizeof(struct phl_custom_ctx));
return MDL_RET_SUCCESS;
}
void
_phl_custom_mdl_deinit(void* dispr, void* priv)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx*)priv;
void *d = phl_to_drvpriv(ctx->phl_info);
_os_mem_free(d, ctx, sizeof(struct phl_custom_ctx));
PHL_INFO(" %s\n", __FUNCTION__);
}
enum phl_mdl_ret_code
_phl_custom_mdl_start(void* dispr, void* priv)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
FUNCIN();
FUNCOUT();
ret = MDL_RET_SUCCESS;
return ret;
}
enum phl_mdl_ret_code
_phl_custom_mdl_stop(void* dispr, void* priv)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
FUNCIN();
FUNCOUT();
ret = MDL_RET_SUCCESS;
return ret;
}
enum phl_mdl_ret_code
_phl_custom_mdl_msg_hdlr(void* dispr,
void* priv,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct phl_custom_ctx *ctx = (struct phl_custom_ctx*)priv;
FUNCIN();
if (IS_MSG_FAIL(msg->msg_id)) {
ret = _phl_custom_hdl_fail_evt(dispr, priv, msg);
_indicate_custome_evt_rpt(ctx);
return MDL_RET_IGNORE;
}
switch (MSG_MDL_ID_FIELD(msg->msg_id)) {
case PHL_MDL_CUSTOM:
ret = _phl_custom_hdl_internal_evt(dispr, priv, msg);
break;
default:
ret = _phl_custom_hdl_external_evt(dispr, priv, msg);
break;
}
_indicate_custome_evt_rpt(ctx);
FUNCOUT();
return ret;
}
enum phl_mdl_ret_code
_phl_custom_mdl_set_info(void* dispr,
void* priv,
struct phl_module_op_info* info)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv;
void *d = phl_to_drvpriv(ctx->phl_info);
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
struct rtw_custom_decrpt *cmd = NULL;
u8 idx = 0xff;
phl_dispr_get_idx(dispr, &idx);
FUNCIN();
switch (info->op_code) {
case BK_MODL_OP_INPUT_CMD:
if (TEST_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED) ||
info->inlen > MAX_DATA_SIZE) {
PHL_ERR("%s buf len err or used\n", __func__);
break;
}
SET_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED);
_os_mem_cpy(d, ctx->cmd_buf, info->inbuf, info->inlen);
cmd = (struct rtw_custom_decrpt *)ctx->cmd_buf;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_CUSTOM);
SET_MSG_EVT_ID_FIELD(msg.msg_id, (u16)cmd->evt_id);
msg.inbuf = ctx->cmd_buf;
msg.inlen = info->inlen;
attr.completion.priv = priv;
attr.completion.completion = _phl_custom_cmd_completion;
msg.band_idx = idx;
if (phl_disp_eng_send_msg(ctx->phl_info,
&msg,
&attr,
NULL) == RTW_PHL_STATUS_SUCCESS) {
ret = MDL_RET_SUCCESS;
} else {
CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED);
PHL_ERR("%s send msg fail\n", __func__);
ret = MDL_RET_FAIL;
}
break;
case BK_MODL_OP_CUS_SET_ROLE_CAP:
ret = phl_custom_fb_set_role_cap(dispr,
(void *)ctx,
&ctx->fb_ctx,
info);
break;
default:
break;
}
FUNCOUT();
return ret;
}
enum phl_mdl_ret_code
_phl_custom_mdl_query_info(void* dispr,
void* priv,
struct phl_module_op_info* info)
{
enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)priv;
void *d = phl_to_drvpriv(ctx->phl_info);
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
struct rtw_custom_decrpt *cmd = NULL;
u8 idx = 0xff;
FUNCIN();
switch(info->op_code) {
case BK_MODL_OP_INPUT_CMD:
if (TEST_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED) ||
info->inlen > MAX_DATA_SIZE) {
PHL_ERR("%s buf len err or used\n", __func__);
break;
}
SET_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED);
_os_mem_cpy(d, ctx->cmd_buf, info->inbuf, info->inlen);
_os_mem_cpy(d, ctx->rpt_buf, info->outbuf, info->outlen);
cmd = (struct rtw_custom_decrpt *)ctx->cmd_buf;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_CUSTOM);
SET_MSG_EVT_ID_FIELD(msg.msg_id, (u16)cmd->evt_id);
msg.inbuf = ctx->cmd_buf;
msg.inlen = info->inlen;
msg.outbuf = ctx->rpt_buf;
msg.outlen = info->outlen;
attr.completion.priv = priv;
attr.completion.completion = _phl_custom_cmd_completion;
msg.band_idx = idx;
if (phl_disp_eng_send_msg(ctx->phl_info,
&msg,
&attr,
NULL) == RTW_PHL_STATUS_SUCCESS) {
ret = MDL_RET_SUCCESS;
} else {
CLEAR_STATUS_FLAG(ctx->status, CUS_STAT_CMD_USED);
PHL_ERR("%s send msg fail\n", __func__);
ret = MDL_RET_FAIL;
}
break;
case BK_MODL_OP_CUS_UPDATE_ROLE_CAP:
ret = phl_custom_fb_update_opt_ie(dispr, (void*)ctx, &ctx->fb_ctx, info);
break;
default:
break;
}
FUNCOUT();
return ret;
}
enum rtw_phl_status
phl_register_custom_module(struct phl_info_t *phl_info, u8 band_idx)
{
enum rtw_phl_status phl_status = RTW_PHL_STATUS_FAILURE;
struct phl_bk_module_ops bk_ops = {0};
bk_ops.init = _phl_custom_mdl_init;
bk_ops.deinit = _phl_custom_mdl_deinit;
bk_ops.start = _phl_custom_mdl_start;
bk_ops.stop = _phl_custom_mdl_stop;
bk_ops.msg_hdlr = _phl_custom_mdl_msg_hdlr;
bk_ops.query_info = _phl_custom_mdl_query_info;
bk_ops.set_info = _phl_custom_mdl_set_info;
phl_status = phl_disp_eng_register_module(phl_info,
band_idx,
PHL_MDL_CUSTOM,
&bk_ops);
if (RTW_PHL_STATUS_SUCCESS != phl_status)
PHL_ERR("%s register Custom module in cmd disp failed\n", __func__);
return phl_status;
}
enum rtw_phl_status
phl_custom_prepare_evt_rpt(void *custom_ctx,
u32 evt_id,
u32 customer_id,
u8 *rpt,
u32 rpt_len)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)custom_ctx;
struct rtw_custom_decrpt *evt_rpt = (struct rtw_custom_decrpt *)ctx->rpt_buf;
void *d = phl_to_drvpriv(ctx->phl_info);
u8* val = (u8*)(evt_rpt +1);
if ((rpt_len > (MAX_DATA_SIZE - sizeof(struct rtw_custom_decrpt))) ||
TEST_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED))
return RTW_PHL_STATUS_RESOURCE;
SET_STATUS_FLAG(ctx->status, CUS_STAT_RPT_USED);
evt_rpt->evt_id = evt_id;
evt_rpt->customer_id = customer_id;
evt_rpt->len = rpt_len;
_os_mem_cpy(d, val, rpt, rpt_len);
return RTW_PHL_STATUS_SUCCESS;
}
struct phl_info_t*
phl_custom_get_phl_info(void *custom_ctx)
{
struct phl_custom_ctx *ctx = (struct phl_custom_ctx *)custom_ctx;
return ctx->phl_info;
}
/**
* phl_custom_init_role_cap
* 1. role cap customization
* input:
* @phl_info: (struct phl_info_t *)
* @hw_band:hw_band
* @role_cap: (struct role_cap_t)
* return: rtw_phl_status
*/
enum rtw_phl_status
phl_custom_init_role_cap(struct phl_info_t *phl_info,
u8 hw_band,
struct role_cap_t *role_cap)
{
enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS;
status = phl_custom_fb_init_role_cap(phl_info, hw_band, role_cap);
return status;
}
#endif
|
2301_81045437/rtl8852be
|
phl/custom/phl_custom.c
|
C
|
agpl-3.0
| 13,249
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CUSTOM_H_
#define _PHL_CUSTOM_H_
#ifdef CONFIG_PHL_CUSTOM_FEATURE
enum rtw_phl_status
phl_register_custom_module(struct phl_info_t *phl_info, u8 band_idx);
enum rtw_phl_status
phl_custom_prepare_evt_rpt(void *custom_ctx,
u32 evt_id,
u32 customer_id,
u8 *rpt,
u32 rpt_len);
struct phl_info_t *
phl_custom_get_phl_info(void *custom_ctx);
enum rtw_phl_status
phl_custom_init_role_cap(struct phl_info_t *phl_info,
u8 hw_band,
struct role_cap_t *role_cap);
#else
#define phl_register_custom_module(_phl_info, _band_idx) (RTW_PHL_STATUS_SUCCESS)
#define phl_custom_init_role_cap(_phl_info, _hw_band, _role_cap) (RTW_PHL_STATUS_SUCCESS)
#endif
#endif /*_PHL_CUSTOMIZE_FEATURE_H_*/
|
2301_81045437/rtl8852be
|
phl/custom/phl_custom.h
|
C
|
agpl-3.0
| 1,501
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CUSTOM_API_H_
#define _PHL_CUSTOM_API_H_
#endif /*_PHL_CUSTOM_API_H_*/
|
2301_81045437/rtl8852be
|
phl/custom/phl_custom_api.h
|
C
|
agpl-3.0
| 735
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CUSTOM_DEF_H_
#define _PHL_CUSTOM_DEF_H_
#define PRIVATE_EVT_START (BIT15)
enum rtw_customer_feature_id {
CUS_ID_NONE = 0,
CUS_ID_FB = 1,
CUS_ID_MAX
};
enum rtw_msg_custom_evt_id {
/* Reserved for Custom Feature
* be aware that the order of the following id are also used in
* upper layer application, thus, it shall not be changed to
* avoid mismatch error!!
*/
MSG_EVT_CUSTOME_NONE = PRIVATE_EVT_START,
MSG_EVT_CUSTOME_FEATURE_ENABLE = PRIVATE_EVT_START + 1,
MSG_EVT_CUSTOME_FEATURE_QUERY = PRIVATE_EVT_START + 2,
MSG_EVT_CUSTOME_TESTMODE_PARAM = PRIVATE_EVT_START + 3,
MSG_EVT_CUSTOME_SET_WIFI_ROLE = PRIVATE_EVT_START + 4,
MSG_EVT_EDCA_ADJUST = PRIVATE_EVT_START + 5,
MSG_EVT_EDCA_QUERY = PRIVATE_EVT_START + 6,
MSG_EVT_NAV_PADDING = PRIVATE_EVT_START + 7,
MSG_EVT_NAV_PADDING_QUERY = PRIVATE_EVT_START + 8,
MSG_EVT_CUSTOM_CMD_DONE = PRIVATE_EVT_START + 9,
MSG_EVT_AMPDU_CFG = PRIVATE_EVT_START + 10,
MSG_EVT_AMPDU_QUERY = PRIVATE_EVT_START + 11,
MSG_EVT_COLDBOOT_CALI = PRIVATE_EVT_START + 12,
MSG_EVT_PDTHR_CFG = PRIVATE_EVT_START + 13,
MSG_EVT_PDTHR_QUERY = PRIVATE_EVT_START + 14,
MSG_EVT_POP_CFG = PRIVATE_EVT_START + 15,
MSG_EVT_POP_QUERY = PRIVATE_EVT_START + 16,
MSG_EVT_STATS_RPT_CFG = PRIVATE_EVT_START + 17,
MSG_EVT_STATS_RPT_NOTIFY = PRIVATE_EVT_START + 18,
MSG_EVT_CHNL_SW = PRIVATE_EVT_START + 19,
MSG_EVT_STA_ASOC_NOTIFY = PRIVATE_EVT_START + 20,
MSG_EVT_BCN_OPT_IES_CFG = PRIVATE_EVT_START + 21,
MSG_EVT_BCN_VDR_IE_CFG = PRIVATE_EVT_START + 22,
MSG_EVT_SET_AP_START_CHNL = PRIVATE_EVT_START + 23,
};
enum custom_type {
CUSTOM_CORE = 0,
CUSTOM_PHL = 1,
CUSTOM_MAX
};
/*
* #pragma pack(1) would set the structure as 1-byte alignment .
*/
#pragma pack(1)
struct rtw_custom_decrpt {
u32 evt_id;
u32 customer_id;
enum custom_type type;
u32 len;
};
#pragma pack()
struct rtw_phl_custom_ampdu_cfg {
u32 max_agg_time_32us;
u32 max_agg_num;
};
#endif /*_PHL_CUSTOM_DEF_H_*/
|
2301_81045437/rtl8852be
|
phl/custom/phl_custom_def.h
|
C
|
agpl-3.0
| 2,597
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _PHL_CUSTOMIZE_FEATURE_C_
#include "../phl_headers.h"
#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB
#include "phl_custom_fb.h"
#define LLC_HDR_LENGTH 6
#define SNAP_HDR_LENGTH 2
enum phl_mdl_ret_code
_is_fb_mode_valid(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg, u32 size)
{
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
if (!fb_ctx->init.enable || cmd->len < size || fb_ctx->init.wifi_role == NULL) {
PHL_INFO(" %s, evt_id(%d) not accepted\n",
__FUNCTION__,
MSG_EVT_ID_FIELD(msg->msg_id));
ret = MDL_RET_FAIL;
return ret;
}
//check chanctx if wifi_role exists
if (fb_ctx->init.wifi_role->chanctx == NULL) {
PHL_INFO(" %s, wifi_role->chanctx is NULL\n", __FUNCTION__);
fb_ctx->init.wifi_role = NULL;
ret = MDL_RET_FAIL;
} else {
ret = MDL_RET_SUCCESS;
}
return ret;
}
enum phl_mdl_ret_code
_custom_fb_feature_enable(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
if (cmd->len < sizeof(u32))
return MDL_RET_FAIL;
fb_ctx->init.enable = *(u32*)(cmd + 1);
fb_ctx->init.test_mode = 0;
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&(fb_ctx->init.enable),
sizeof(u32));
return MDL_RET_SUCCESS;
}
enum phl_mdl_ret_code
_custom_fb_feature_query(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
if (cmd->len < sizeof(u32))
return ret;
PHL_INFO("%s, fb query feature enable(%d)\n",
__FUNCTION__,
fb_ctx->init.enable);
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&(fb_ctx->init.enable),
sizeof(u32));
ret = MDL_RET_SUCCESS;
return ret;
}
enum phl_mdl_ret_code
_custom_fb_testmode_param(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
if (cmd->len < sizeof(u32))
return ret;
fb_ctx->init.test_mode = *(u32*)(cmd + 1);
PHL_INFO("%s, test mode(0x%x)\n", __FUNCTION__,
fb_ctx->init.test_mode);
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&ret,
sizeof(u8));
ret = MDL_RET_SUCCESS;
return ret;
}
enum phl_mdl_ret_code
_custom_fb_set_wifi_role(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
u32 size = MAC_ADDRESS_LENGTH;
u8* val = (u8*)(cmd + 1);
if (cmd->len < MAC_ADDRESS_LENGTH)
return ret;
if (!(fb_ctx->init.test_mode & FB_TEST_MODE_USE_STA_MAC))
*val |= (BIT1 | BIT7);
PHL_INFO("val - MAC-Addr:%02x-%02x-%02x-%02x-%02x-%02x\n",
*val,*(val + 1),*(val + 2),
*(val + 3), *(val + 4),*(val + 5));
fb_ctx->init.wifi_role = phl_get_wrole_by_addr(phl, val);
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&ret,
sizeof(u8));
return ret;
}
enum phl_mdl_ret_code
_custom_fb_ampdu_cfg(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
void *d = phl_to_drvpriv(phl);
struct rtw_phl_stainfo_t *phl_sta = NULL;
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
struct rtw_phl_custom_ampdu_cfg custom_fb_ampdu_cfg = {0};
u32 size = sizeof(struct rtw_phl_custom_ampdu_cfg);
u8* val = (u8*)(cmd + 1);
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
if (ret != MDL_RET_SUCCESS) {
goto exit;
}
phl_sta = rtw_phl_get_stainfo_self(phl, fb_ctx->init.wifi_role);
_os_mem_cpy(d, &custom_fb_ampdu_cfg, val, size);
hal_status = rtw_hal_custom_cfg_tx_ampdu(phl->hal,
fb_ctx->init.wifi_role,
&custom_fb_ampdu_cfg);
phl_sta->asoc_cap.num_ampdu = (u8)custom_fb_ampdu_cfg.max_agg_num;
PHL_INFO("%s, halsta(%d) ampdu dur(%d) num(%d)\n",
__FUNCTION__,
hal_status,
custom_fb_ampdu_cfg.max_agg_time_32us,
custom_fb_ampdu_cfg.max_agg_num);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
ret = MDL_RET_FAIL;
exit:
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&ret,
sizeof(u8));
return ret;
}
enum phl_mdl_ret_code
_custom_fb_ampdu_query(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
struct rtw_phl_custom_ampdu_cfg custom_fb_ampdu_cfg = {0};
u32 size = sizeof(struct rtw_phl_custom_ampdu_cfg);
/* 0xffffffff is querying failed for SDK*/
custom_fb_ampdu_cfg.max_agg_num = 0xffffffff;
custom_fb_ampdu_cfg.max_agg_time_32us = 0xffffffff;
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
if (ret != MDL_RET_SUCCESS) {
goto exit;
}
hal_status = rtw_hal_get_ampdu_cfg(phl->hal,
fb_ctx->init.wifi_role,
&custom_fb_ampdu_cfg);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
ret = MDL_RET_FAIL;
PHL_INFO(" %s, ampdu dur(%d) time(%d)\n",
__FUNCTION__,
custom_fb_ampdu_cfg.max_agg_time_32us,
custom_fb_ampdu_cfg.max_agg_num);
exit:
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&custom_fb_ampdu_cfg,
sizeof(struct rtw_phl_custom_ampdu_cfg));
return ret;
}
enum phl_mdl_ret_code
_custom_fb_pdthr_cfg(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
int pd_thr = 0xff;
u32 size = sizeof(int);
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
if (ret != MDL_RET_SUCCESS) {
goto exit;
}
pd_thr = *(int*)(cmd + 1);
PHL_INFO("%s, pd_thr(%d)\n", __FUNCTION__, pd_thr);
PHL_INFO("%s, bw(%d) band(%d)\n", __FUNCTION__,
fb_ctx->init.wifi_role->chanctx->chan_def.bw,
fb_ctx->init.wifi_role->hw_band);
hal_status = rtw_hal_set_pkt_detect_thold(phl->hal, (u32)pd_thr);
PHL_INFO("%s, hal_status(%d)\n", __FUNCTION__, hal_status);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
ret = MDL_RET_FAIL;
exit:
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&ret,
sizeof(u8));
return ret;
}
enum phl_mdl_ret_code
_custom_fb_pdthr_query(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
int pd_thr = 0xff;
u32 size = sizeof(int);
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
if (ret != MDL_RET_SUCCESS) {
goto exit;
}
/*confirm whether pd thr is enabling or not*/
pd_thr = rtw_hal_query_pkt_detect_thold(phl->hal,
true,
fb_ctx->init.wifi_role->hw_band);
if (pd_thr == 0) {
PHL_INFO("%s, disable! pd_thr(%d)\n", __FUNCTION__, pd_thr);
} else {
pd_thr = rtw_hal_query_pkt_detect_thold(phl->hal,
false,
fb_ctx->init.wifi_role->hw_band);
PHL_INFO("%s, pd_thr(%d)\n", __FUNCTION__, pd_thr);
}
exit:
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&pd_thr,
sizeof(int));
return ret;
}
enum phl_mdl_ret_code
_custom_fb_pop_cfg(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
u32 size = sizeof(u32);
u32 pop_enable = 0xff;
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
if (ret != MDL_RET_SUCCESS) {
goto exit;
}
pop_enable = *(u32*)(cmd + 1);
PHL_INFO("%s, pop_enable(%d)\n", __FUNCTION__, pop_enable);
if (pop_enable != 0xff) {
hal_status = rtw_hal_set_pop_en(phl->hal,
(bool)pop_enable,
fb_ctx->init.wifi_role->hw_band);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
ret = MDL_RET_FAIL;
}
exit:
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&ret,
sizeof(u8));
return ret;
}
enum phl_mdl_ret_code
_custom_fb_pop_query(void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
struct rtw_custom_decrpt *cmd = (struct rtw_custom_decrpt *)(msg->inbuf);
u32 size = sizeof(u32);
u32 pop_enable = 0xff;
ret = _is_fb_mode_valid(custom_ctx, fb_ctx, msg, size);
if (ret != MDL_RET_SUCCESS){
goto exit;
}
pop_enable = rtw_hal_query_pop_en(phl->hal, fb_ctx->init.wifi_role->hw_band);
PHL_INFO("%s, pop_en(%d)\n", __FUNCTION__, pop_enable);
exit:
phl_custom_prepare_evt_rpt(custom_ctx,
cmd->evt_id,
cmd->customer_id,
(u8*)&pop_enable,
sizeof(u32));
return ret;
}
enum phl_mdl_ret_code
phl_custom_hdl_fb_evt(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
enum phl_mdl_ret_code ret = MDL_RET_FAIL;
u8 prephase = (IS_MSG_IN_PRE_PHASE(msg->msg_id)) ? (true) : (false);
if (prephase == true)
return MDL_RET_SUCCESS;
switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
case MSG_EVT_CUSTOME_FEATURE_ENABLE:
ret = _custom_fb_feature_enable(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_CUSTOME_FEATURE_QUERY:
ret = _custom_fb_feature_query(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_CUSTOME_TESTMODE_PARAM:
ret = _custom_fb_testmode_param(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_CUSTOME_SET_WIFI_ROLE:
ret = _custom_fb_set_wifi_role(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_AMPDU_CFG:
ret = _custom_fb_ampdu_cfg(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_AMPDU_QUERY:
ret = _custom_fb_ampdu_query(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_PDTHR_CFG:
ret = _custom_fb_pdthr_cfg(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_PDTHR_QUERY:
ret = _custom_fb_pdthr_query(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_POP_CFG:
ret = _custom_fb_pop_cfg(custom_ctx, fb_ctx, msg);
break;
case MSG_EVT_POP_QUERY:
ret = _custom_fb_pop_query(custom_ctx, fb_ctx, msg);
break;
default:
ret = MDL_RET_SUCCESS;
break;
}
PHL_INFO("%s, evt(%d), ret(%d)\n", __FUNCTION__,
MSG_EVT_ID_FIELD(msg->msg_id),
ret);
return ret;
}
enum phl_mdl_ret_code
phl_custom_hdl_fb_fail_evt(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg)
{
return MDL_RET_IGNORE;
}
enum phl_mdl_ret_code
phl_custom_fb_update_opt_ie(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_module_op_info* info)
{
enum phl_mdl_ret_code status = MDL_RET_SUCCESS;
struct phl_info_t *phl = phl_custom_get_phl_info(custom_ctx);
void *d = phl_to_drvpriv(phl);
if (info->outlen == 0)
return MDL_RET_FAIL;
_os_mem_cpy(d, info->outbuf, &fb_ctx->bcn_param, info->outlen);
return status;
}
enum phl_mdl_ret_code
phl_custom_fb_set_role_cap(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_module_op_info* info)
{
enum phl_mdl_ret_code status = MDL_RET_SUCCESS;
FUNCIN();
fb_ctx->bcn_param.enable = true;
fb_ctx->bcn_param.cus_wmode = *(u8*)info->inbuf;
FUNCOUT();
return status;
}
enum rtw_phl_status
phl_custom_fb_init_role_cap(struct phl_info_t *phl_info,
u8 hw_band,
struct role_cap_t *role_cap)
{
enum rtw_phl_status status = RTW_PHL_STATUS_SUCCESS;
struct phl_module_op_info op_info = {0};
struct _facebook_bcn_param bcn_param = {0};
op_info.op_code = BK_MODL_OP_CUS_UPDATE_ROLE_CAP;
op_info.outbuf = (u8*)&bcn_param;
op_info.outlen = sizeof(struct _facebook_bcn_param);
if (phl_disp_eng_query_bk_module_info(phl_info,
hw_band,
PHL_MDL_CUSTOM,
&op_info) == MDL_RET_SUCCESS) {
if (bcn_param.enable == true) {
role_cap->wmode &= bcn_param.cus_wmode;
}
PHL_INFO("%s, wmode(%d) cus_wmode(%d) enable(%d)\n", __FUNCTION__,
role_cap->wmode,
bcn_param.cus_wmode,
bcn_param.enable);
} else {
status = RTW_PHL_STATUS_FAILURE;
}
return status;
}
#endif
|
2301_81045437/rtl8852be
|
phl/custom/phl_custom_fb.c
|
C
|
agpl-3.0
| 16,095
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _PHL_CUSTOM_FB_H_
#define _PHL_CUSTOM_FB_H_
#ifdef CONFIG_PHL_CUSTOM_FEATURE_FB
#define TX_PKT_CYCLE (10)
#define FC_QOS_BIT BIT7
#define GET_80211_HDR_TO_DS(_hdr) LE_BITS_TO_2BYTE(_hdr, 8, 1)
#define GET_80211_HDR_FROM_DS(_hdr) LE_BITS_TO_2BYTE(_hdr, 9, 1)
#define GET_80211_HDR_WEP(_hdr) LE_BITS_TO_2BYTE(_hdr, 14, 1)
#define GET_80211_HDR_ORDER(_hdr) LE_BITS_TO_2BYTE(_hdr, 15, 1)
#define IS_DATA_FRAME(pdu) ( ((EF1Byte(pdu[0]) & 0x0C)==0x08) ? TRUE : FALSE )
#define IS_QOS_DATA_FRAME(pdu) (IS_DATA_FRAME(pdu) && (EF1Byte(pdu[0]) & FC_QOS_BIT) )
enum _fackbook_test_mode {
FB_TEST_MODE_FAKE_TX_CYCLE = BIT0,
FB_TEST_MODE_USE_STA_MAC = BIT1,
};
struct _facebook_init_param {
u32 enable;
u32 test_mode;
struct rtw_wifi_role_t *wifi_role;
};
struct _facebook_bcn_param {
u32 enable;
u8 cus_wmode;
};
struct _custom_facebook_ctx {
struct _facebook_init_param init;
struct _facebook_bcn_param bcn_param;
};
enum phl_mdl_ret_code
phl_custom_hdl_fb_evt(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg);
enum phl_mdl_ret_code
phl_custom_hdl_fb_fail_evt(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_msg* msg);
enum phl_mdl_ret_code
phl_custom_fb_update_opt_ie(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_module_op_info* info);
enum phl_mdl_ret_code
phl_custom_fb_set_role_cap(void* dispr,
void* custom_ctx,
struct _custom_facebook_ctx* fb_ctx,
struct phl_module_op_info* info);
enum rtw_phl_status
phl_custom_fb_init_role_cap(struct phl_info_t *phl_info,
u8 hw_band,
struct role_cap_t *role_cap);
#else
#define phl_custom_fb_update_opt_ie(_dispr, _ctx, _fb_ctx, _info) (MDL_RET_SUCCESS)
#define phl_custom_fb_set_role_cap(_dispr, _ctx, _fb_ctx, _info) (RTW_PHL_STATUS_SUCCESS)
#define phl_custom_fb_init_role_cap(_phl_info, _hw_band, _role_cap) (RTW_PHL_STATUS_SUCCESS)
#endif
#endif /*_PHL_CUSTOMIZE_FEATURE_H_*/
|
2301_81045437/rtl8852be
|
phl/custom/phl_custom_fb.h
|
C
|
agpl-3.0
| 2,969
|
# All needed files would be added to _HAL_INTFS_FILES, and it would include
# hal_g6/btc and all related files in directory hal_g6/btc/.
# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC
# (CONFIG_RTL*) setting are all ready!
HAL = hal_g6
ifeq ($(CONFIG_PHL_ARCH), y)
phl_path := phl/hal_g6
phl_path_d1 := $(src)/phl/$(HAL)
else
phl_path := hal_g6
phl_path_d1 := $(src)/$(HAL)
endif
# Base directory
path_halbtc_d1 := $(phl_path)/btc
halbtc-y += $(path_halbtc_d1)/hal_btc.o \
$(path_halbtc_d1)/halbtc_def.o \
$(path_halbtc_d1)/halbtc_action.o \
$(path_halbtc_d1)/halbtc_fw.o \
$(path_halbtc_d1)/halbtc_dbg_cmd.o
ifeq ($(CONFIG_RTL8852A), y)
ic := 8852a
# Level 2 directory
path_halbtc_8852a := $(path_halbtc_d1)/btc_$(ic)
halbtc-y += $(path_halbtc_8852a)/btc_8852a.o
endif
ifeq ($(CONFIG_RTL8852B), y)
ic := 8852b
# Level 2 directory
path_halbtc_8852b := $(path_halbtc_d1)/btc_$(ic)
halbtc-y += $(path_halbtc_8852b)/btc_8852b.o
endif
ifeq ($(CONFIG_RTL8852C), y)
ic := 8852c
# Level 2 directory
path_halbtc_8852c := $(path_halbtc_d1)/btc_$(ic)
halbtc-y += $(path_halbtc_8852c)/btc_8852c.o
endif
_BTC_FILES += $(halbtc-y)
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/btc.mk
|
Makefile
|
agpl-3.0
| 1,167
|
/******************************************************************************
*
* Copyright(c) 2016 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8852B_BTC_H__
#define __RTL8852B_BTC_H__
/* rtl8852b_btc.c */
extern const struct btc_chip chip_8852b;
void _8852b_rfe_type(struct btc_t *btc);
void _8852b_init_cfg(struct btc_t *btc);
void _8852b_wl_pri (struct btc_t *btc, u8 map, bool state);
void _8852b_wl_tx_power(struct btc_t *btc, u32 level);
void _8852b_wl_rx_gain(struct btc_t *btc, u32 level);
void _8852b_wl_s1_standby(struct btc_t *btc, u32 state);
void _8852b_wl_req_mac(struct btc_t *btc, u8 mac_id);
void _8852b_update_bt_cnt(struct btc_t *btc);
u8 _8852b_bt_rssi(struct btc_t *btc, u8 val);
#endif /*__RTL8852B_PHY_H__*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/btc_8852b/btc_8852b.h
|
C
|
agpl-3.0
| 1,257
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_BTC_C_
#include "../hal_headers_le.h"
#include "hal_btc.h"
#include "halbtc_fw.h"
#include "halbtc_def.h"
#include "halbtc_action.h"
#ifdef CONFIG_BTCOEX
/* [31:24] -> main-version
* [23:16] -> sub-version
* [15:8] -> Hot-Fix-version
* [7:0] -> branch ID, ex: 0x00-> Main-Branch
* Modify bt_8852x.c chip_8852x member: btcx_desired, wlcx_desired if required
* btcx_desired: BT FW coex version -> main-version + 1 if update.
* wlcx_desired: WL FW coex version -> sub-version + 1 if update
*/
const u32 coex_ver = 0x0601000f;
static struct btc_ops _btc_ops = {
_send_fw_cmd,
_ntfy_power_on,
_ntfy_power_off,
_ntfy_init_coex,
_ntfy_scan_start,
_ntfy_scan_finish,
_ntfy_switch_band,
_ntfy_specific_packet,
_ntfy_role_info,
_ntfy_radio_state,
_ntfy_customerize,
_ntfy_wl_rfk,
_ntfy_wl_sta,
_ntfy_fwinfo,
_ntfy_timer
};
#define _update_dbcc_band(phy_idx) \
btc->cx.wl.dbcc_info.real_band[phy_idx] =\
(btc->cx.wl.scan_info.phy_map & BIT(phy_idx) ?\
btc->cx.wl.dbcc_info.scan_band[phy_idx] :\
btc->cx.wl.dbcc_info.op_band[phy_idx])
/******************************************************************************
*
* coex internal functions
*
*****************************************************************************/
static void _set_btc_timer(struct btc_t *btc, u16 tmr_id, u32 ms)
{
struct btc_tmr *btmr = NULL;
if (tmr_id < BTC_TIMER_MAX) {
btmr = &btc->timer[tmr_id];
_os_set_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr, ms);
}
}
static void _btmr_stop(struct btc_t *btc)
{
struct btc_tmr *btmr = NULL;
u8 i = 0;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): stop btc timers!!\n",
__func__);
btc->tmr_stop = true;
for (i = 0; i < BTC_TIMER_MAX; i++) {
btmr = &btc->timer[i];
_os_cancel_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr);
}
_os_cancel_timer(halcom_to_drvpriv(btc->hal), &btc->delay_tmr);
}
static void _btmr_release(struct btc_t *btc)
{
struct btc_tmr *btmr = NULL;
u8 i = 0;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): release btc timers!!\n",
__func__);
for (i = 0; i < BTC_TIMER_MAX; i++) {
btmr = &btc->timer[i];
_os_release_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr);
}
_os_release_timer(halcom_to_drvpriv(btc->hal), &btc->delay_tmr);
}
static void _btmr_start(struct btc_t *btc)
{
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): start btc periodic timer!!\n",
__func__);
btc->tmr_stop = false;
/* Wait 2 sec for phl starting then periodic timer will be started */
_os_set_timer(halcom_to_drvpriv(btc->hal),
&btc->delay_tmr, BTC_DELAYED_PERIODIC_TIME);
}
static void _delay_tmr_cb(void *ctx)
{
struct btc_t *btc = NULL;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s() !!\n", __func__);
if (!ctx)
return;
btc = (struct btc_t *)ctx;
_set_btc_timer(btc, BTC_TIMER_PERIODIC, BTC_PERIODIC_TIME);
}
static void _btmr_cb(void *ctx)
{
struct btc_tmr *btmr = NULL;
struct btc_t *btc = NULL;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(), ctx = 0x%p !!\n",
__func__, ctx);
if (!ctx)
return;
btmr = (struct btc_tmr *)ctx;
btc = (struct btc_t *)btmr->btc;
if (!btc->tmr_init || btc->tmr_stop)
return;
hal_btc_send_event(btc, (u8 *)btmr, sizeof(struct btc_tmr *),
BTC_HMSG_TMR_EN);
}
static void _btmr_init(struct btc_t *btc)
{
struct btc_tmr *btmr = NULL;
u8 i = 0;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): !!\n", __func__);
for (i = 0; i < BTC_TIMER_MAX; i++) {
btmr = &btc->timer[i];
btmr->btc = btc;
btmr->id = i;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], init btc timer(%d) = 0x%p !!\n", i, btmr);
_os_init_timer(halcom_to_drvpriv(btc->hal), &btmr->tmr,
_btmr_cb, btmr, "btc_tmr");
}
_os_init_timer(halcom_to_drvpriv(btc->hal), &btc->delay_tmr,
_delay_tmr_cb, btc, NULL);
btc->tmr_init = true;
btc->tmr_stop = true;
}
static void _btmr_deinit(struct btc_t *btc)
{
if (btc->tmr_init) {
_btmr_stop(btc);
_btmr_release(btc);
btc->tmr_init = false;
}
}
static void
_send_fw_cmd(struct btc_t *btc, u8 h2c_class, u8 h2c_func, u8 *param, u16 len)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_wl_info *wl = &btc->cx.wl;
struct rtw_g6_h2c_hdr hdr = {0};
hdr.h2c_class = h2c_class;
hdr.h2c_func = h2c_func;
hdr.type = H2CB_TYPE_DATA;
hdr.content_len = len;
hdr.done_ack = 1;
if (!wl->status.map.init_ok) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return by btc not init!!\n",
__func__);
btc->fwinfo.cnt_h2c_fail++;
return;
} else if ((wl->status.map.rf_off_pre == 1 &&
wl->status.map.rf_off == 1) ||
(wl->status.map.lps_pre == 1 &&
wl->status.map.lps == 1)) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return by wl off!!\n",
__func__);
btc->fwinfo.cnt_h2c_fail++;
return;
}
btc->fwinfo.cnt_h2c++;
if (rtw_hal_mac_send_h2c(h, &hdr, (u32 *)param) != 0)
btc->fwinfo.cnt_h2c_fail++;
}
u32 _read_cx_reg(struct btc_t *btc, u32 offset)
{
u32 val = 0;
rtw_hal_mac_coex_reg_read(btc->hal, offset, &val);
return val;
}
u8 _read_cx_ctrl(struct btc_t *btc)
{
u32 val = 0;
rtw_hal_mac_get_coex_ctrl(btc->hal, &val);
return ((u8)val);
}
u32 _read_scbd(struct btc_t *btc)
{
const struct btc_chip *chip = btc->chip;
u32 scbd_val = 0;
if (!chip->scbd)
return 0;
rtw_hal_mac_get_scoreboard(btc->hal, &scbd_val);
PHL_INFO("[BTC], read scbd : 0x%08x \n", scbd_val);
btc->cx.cnt_bt[BTC_BCNT_SCBDREAD]++;
return (scbd_val);
}
void _write_scbd(struct btc_t *btc, u32 val, bool state)
{
const struct btc_chip *chip = btc->chip;
struct btc_wl_info *wl = &btc->cx.wl;
u32 scbd_val = 0;
if (!chip->scbd)
return;
/* only use bit23~0 */
scbd_val = (state ? (wl->scbd | val) : (wl->scbd & (~val)));
if (scbd_val != wl->scbd) {
rtw_hal_mac_set_scoreboard(btc->hal, &scbd_val);
PHL_INFO("[BTC], write scbd : 0x%08x \n", scbd_val);
wl->scbd = scbd_val;
btc->cx.cnt_wl[BTC_WCNT_SCBDUPDATE]++;
}
}
static u8
_update_rssi_state(struct btc_t *btc, u8 pre_state, u8 rssi, u8 thresh)
{
u8 next_state, tol = btc->chip->rssi_tol;
if (pre_state == BTC_RSSI_ST_LOW ||
pre_state == BTC_RSSI_ST_STAY_LOW) {
if (rssi >= (thresh + tol))
next_state = BTC_RSSI_ST_HIGH;
else
next_state = BTC_RSSI_ST_STAY_LOW;
} else {
if (rssi < thresh)
next_state = BTC_RSSI_ST_LOW;
else
next_state = BTC_RSSI_ST_STAY_HIGH;
}
return next_state;
}
void _write_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr, u32 val)
{
u8 buf[4] = {0};
/* set write address */
buf[0] = reg_type;
buf[1] = addr & bMASKB0;
buf[2] = (addr & bMASKB1) >> 8;
hal_btc_fw_set_bt(btc, SET_BT_WREG_ADDR, 3, buf);
/* set write value */
buf[0] = val & bMASKB0;
buf[1] = (val & bMASKB1) >> 8;
buf[2] = (val & bMASKB2) >> 16;
buf[3] = (val & bMASKB3) >> 23;
hal_btc_fw_set_bt(btc, SET_BT_WREG_VAL, 4, buf);
}
void _read_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr)
{
/* this function is only for API call.
* If BTC should use hal_btc_fw_set_monreg to read bt reg.
*/
u8 buf[3] = {0};
/* set write address */
buf[0] = reg_type;
buf[1] = addr & bMASKB0;
buf[2] = (addr & bMASKB1) >> 8;
hal_btc_fw_set_bt(btc, SET_BT_RREG_ADDR, sizeof(buf), buf);
/* To do wait FW event -> BTF_EVNT_BT_REG*/
}
void _set_bt_psd_report(struct btc_t *btc, u8 start_idx, u8 rpt_type)
{
u8 buf[2] = {0};
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): set bt psd\n",
__func__);
buf[0] = start_idx;
buf[1] = rpt_type;
hal_btc_fw_set_bt(btc, SET_BT_PSD_REPORT, 2, buf);
}
static void _set_bt_info_report(struct btc_t *btc, u8 trigger)
{
u8 buf = 0;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): query bt info\n",
__func__);
buf = trigger;
hal_btc_fw_set_bt(btc, SET_BT_INFO_REPORT, 1, &buf);
}
static void _reset_btc_var(struct btc_t *btc, u8 type)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_info *bt = &cx->bt;
struct btc_bt_link_info *bt_linfo = &bt->link_info;
struct btc_wl_link_info *wl_linfo = wl->link_info;
u8 i;
PHL_INFO("[BTC], %s()\n", __func__);
/* Reset Coex variable */
if (type & BTC_RESET_CX)
hal_mem_set(h, cx, 0, sizeof(struct btc_cx));
else if (type & BTC_RESET_BTINFO) /* only for BT enable */
hal_mem_set(h, bt, 0, sizeof(struct btc_bt_info));
if (type & BTC_RESET_CTRL)
hal_mem_set(h, &btc->ctrl, 0, sizeof(struct btc_ctrl));
/* Init Coex variables that are not zero */
if (type & BTC_RESET_DM) {
hal_mem_set(h, &btc->dm, 0, sizeof(struct btc_dm));
hal_mem_set(h, bt_linfo->rssi_state, 0, BTC_BT_RSSI_THMAX);
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++)
hal_mem_set(h, wl_linfo[i].rssi_state, 0,
BTC_WL_RSSI_THMAX);
/* set the slot_now table to original */
_tdma_cpy(&btc->dm.tdma_now, &t_def[CXTD_OFF]);
_tdma_cpy(&btc->dm.tdma, &t_def[CXTD_OFF]);
_slots_cpy(btc->dm.slot_now, s_def);
_slots_cpy(btc->dm.slot, s_def);
btc->policy_len = 0;
btc->bt_req_len = 0;
btc->hubmsg_cnt = 0;
btc->dm.coex_info_map = BTC_COEX_INFO_ALL;
btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF;
btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF;
}
if (type & BTC_RESET_MDINFO)
hal_mem_set(h, &btc->mdinfo, 0, sizeof(struct btc_module));
}
static bool _chk_wl_rfk_request(struct btc_t *btc)
{
struct btc_cx *cx = &btc->cx;
struct btc_bt_info *bt = &cx->bt;
_update_bt_scbd(btc, true);
cx->cnt_wl[BTC_WCNT_RFK_REQ]++;
if ((bt->rfk_info.map.run || bt->rfk_info.map.req) &&
(!bt->rfk_info.map.timeout)) {
cx->cnt_wl[BTC_WCNT_RFK_REJECT]++;
return BTC_WRFK_REJECT;
} else {
cx->cnt_wl[BTC_WCNT_RFK_GO]++;
return BTC_WRFK_ALLOW;
}
}
void _set_init_info(struct btc_t *btc)
{
struct btc_dm *dm = &btc->dm;
struct btc_wl_info *wl = &btc->cx.wl;
dm->init_info.wl_only = (u8)dm->wl_only;
dm->init_info.bt_only = (u8)dm->bt_only;
dm->init_info.wl_init_ok = (u8)wl->status.map.init_ok;
dm->init_info.dbcc_en = btc->hal->dbcc_en;
dm->init_info.cx_other = btc->cx.other.type;
dm->init_info.wl_guard_ch = btc->chip->afh_guard_ch;
dm->init_info.module = btc->mdinfo;
}
u8 _get_role_link_mode(struct btc_t *btc, u8 role)
{
switch(role) {
case PHL_RTYPE_STATION:
return BTC_WLINK_2G_STA;
case PHL_RTYPE_P2P_GO:
return BTC_WLINK_2G_GO;
case PHL_RTYPE_P2P_GC:
return BTC_WLINK_2G_GC;
case PHL_RTYPE_AP:
return BTC_WLINK_2G_AP;
default:
return BTC_WLINK_OTHER;
}
}
u8 _get_wl_role_idx(struct btc_t *btc, u8 role)
{
struct btc_wl_role_info *wl_rinfo = &btc->cx.wl.role_info;
u8 i, pid = 0;
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) {
if (wl_rinfo->active_role[i].role == role)
break;
}
pid = i;
return pid; /*cation: return MAX_WIFI_ROLE_NUMBER if role not found */
}
void _set_wl_req_mac(struct btc_t *btc, u8 mac_id)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_chip_ops *ops = btc->chip->ops;
if (mac_id == wl->pta_req_mac)
return;
if (ops && ops->wl_req_mac)
ops->wl_req_mac(btc, mac_id);
wl->pta_req_mac = mac_id;
}
static bool _chk_role_ch_group(struct btc_t *btc, struct rtw_chan_def r1, struct rtw_chan_def r2)
{
bool is_grouped = false;
if (r1.chan != r2.chan) {
/* primary ch is different */
goto exit;
} else if (r1.bw == CHANNEL_WIDTH_40 && r2.bw == CHANNEL_WIDTH_40) {
if (r1.offset != r2.offset)
goto exit;
}
is_grouped = true;
exit:
return is_grouped;
}
static void _update_wl_info(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_link_info *wl_linfo = wl->link_info;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info;
struct btc_wl_active_role *active_role = NULL;
struct rtw_hal_com_t *h = btc->hal;
struct rtw_chan_def cid_ch[MAX_WIFI_ROLE_NUMBER];
u8 i, j, k, cnt_connect = 0, cnt_connecting = 0, cnt_active = 0;
u8 cnt_2g = 0, cnt_5g = 0, max_role_cnt = BTC_TDMA_WLROLE_MAX;
u8 cid_phy[MAX_WIFI_ROLE_NUMBER] = {0};
u8 cid_role[MAX_WIFI_ROLE_NUMBER] = {0};
u8 dbcc_2g_phy = 0, dbcc_2g_cid = 0, dbcc_2g_role = 0;
u32 noa_duration = 0;
bool b2g = false, b5g = false, client_joined = false, noa_exist = false;
hal_mem_set(h, wl_rinfo, 0, sizeof(struct btc_wl_role_info));
hal_mem_set(h, wl_dinfo, 0, sizeof(struct btc_wl_dbcc_info));
hal_mem_set(h, cid_ch, 0, MAX_WIFI_ROLE_NUMBER * sizeof(struct rtw_chan_def));
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) {
/* check if role active? */
if (!wl_linfo[i].active || wl_linfo[i].phy >= HW_PHY_MAX)
continue;
cnt_active++;
active_role = &wl_rinfo->active_role[cnt_active-1];
active_role->role = wl_linfo[i].role;
active_role->pid = wl_linfo[i].pid;
active_role->phy = wl_linfo[i].phy;
active_role->band = wl_linfo[i].chdef.band;
active_role->noa = (u8)wl_linfo[i].noa;
active_role->noa_duration = wl_linfo[i].noa_duration/1000;
/* check if role connect? */
if (wl_linfo[i].connected == MLME_NO_LINK) {
wl_rinfo->active_role[cnt_active-1].connected = 0;
continue;
} else if (wl_linfo[i].connected == MLME_LINKING) {
cnt_connecting++;
} else {
cnt_connect++;
/* only if client connect for p2p-Go/AP */
if ((wl_linfo[i].role == PHL_RTYPE_P2P_GO ||
wl_linfo[i].role == PHL_RTYPE_AP) &&
wl_linfo[i].client_cnt > 1)
client_joined = true;
cid_phy[cnt_connect-1] = wl_linfo[i].phy;
hal_mem_cpy(h, &cid_ch[cnt_connect-1],
&wl_linfo[i].chdef, sizeof(struct rtw_chan_def));
cid_role[cnt_connect-1] = wl_linfo[i].role;
}
wl_rinfo->role_map.val |= BIT(wl_linfo[i].role);
active_role->ch = wl_linfo[i].chdef.center_ch;
active_role->bw = wl_linfo[i].chdef.bw;
active_role->connected = 1;
/* only one noa-role exist */
if (active_role->noa && active_role->noa_duration > 0) {
noa_exist = true;
noa_duration = active_role->noa_duration;
}
/* Check dbcc role,the last role may overwrite the former role,
* This will be modified in the below code.
*/
if (h->dbcc_en) {
wl_dinfo->role[wl_linfo[i].phy] = wl_linfo[i].role;
wl_dinfo->op_band[wl_linfo[i].phy] = wl_linfo[i].chdef.band;
max_role_cnt = BTC_TDMA_WLROLE_MAX + 1;
}
if (wl_linfo[i].chdef.band != BAND_ON_24G) {
cnt_5g++;
b5g = true;
} else {
cnt_2g++;
b2g = true;
}
}
wl_rinfo->connect_cnt = cnt_connect;
/* Be careful to change the following sequence!! */
if (cnt_connect == 0) {
wl_rinfo->link_mode = BTC_WLINK_NOLINK;
wl_rinfo->role_map.role.none = 1;
} else if (!b2g && b5g) {
wl_rinfo->link_mode = BTC_WLINK_5G;
} else if (wl_rinfo->role_map.role.nan) {
wl_rinfo->link_mode = BTC_WLINK_2G_NAN;
} else if (cnt_connect > max_role_cnt) {
wl_rinfo->link_mode = BTC_WLINK_OTHER;
} else if (h->dbcc_en) {
/* find out the 2G-PHY by connect-id ->ch */
for (j = 0; j < cnt_connect; j++) {
if (cid_ch[j].center_ch <= 14 || j == cnt_connect-1)
break;
}
dbcc_2g_cid = j;
dbcc_2g_phy = cid_phy[j];
dbcc_2g_role = cid_role[j];
/* find out the other role in the 2.4G_band-PHY*/
if (cnt_connect == 3) {
for (k = 0; k < cnt_connect; k++) {
if (k == j)
continue;
else if (cid_phy[k] == dbcc_2g_phy)
break;
}
if (k < cnt_connect) { /* if find -> DBCC + MCC/SCC */
if (cid_ch[k].center_ch > 14)
wl_rinfo->link_mode = BTC_WLINK_25G_MCC;
else if (_chk_role_ch_group(btc, cid_ch[j], cid_ch[k]))
wl_rinfo->link_mode = BTC_WLINK_2G_SCC;
else
wl_rinfo->link_mode = BTC_WLINK_2G_MCC;
/* correct 2G-located PHY role/band
* for gnt ctrl.
*/
wl_dinfo->role[dbcc_2g_phy] = dbcc_2g_role;
wl_dinfo->op_band[dbcc_2g_phy] = BAND_ON_24G;
goto exit;
}
}
wl_rinfo->link_mode = _get_role_link_mode(btc, cid_role[j]);
} else if (b2g && b5g && cnt_connect == 2) {
wl_rinfo->link_mode = BTC_WLINK_25G_MCC;
} else if (!b5g && cnt_connect == 2) { /* cnt_connect = 2 */
if (_chk_role_ch_group(btc, cid_ch[0], cid_ch[cnt_connect - 1]))
wl_rinfo->link_mode = BTC_WLINK_2G_SCC;
else
wl_rinfo->link_mode= BTC_WLINK_2G_MCC;
} else if (!b5g && cnt_connect == 1) { /* cnt_connect = 1 */
wl_rinfo->link_mode = _get_role_link_mode(btc, cid_role[0]);
}
/* if no client_joined, don't care P2P-GO/AP role */
if ((wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) &&
!client_joined) {
#if 0 /* work-around for Go/AP(no-client) can not move channel to same as STA*/
if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC ||
wl_rinfo->link_mode == BTC_WLINK_2G_MCC)
#else
if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC)
#endif
{
wl_rinfo->link_mode = BTC_WLINK_2G_STA;
wl_rinfo->connect_cnt--;
} else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO ||
wl_rinfo->link_mode == BTC_WLINK_2G_AP) {
wl_rinfo->link_mode = BTC_WLINK_NOLINK;
wl_rinfo->connect_cnt--;
}
}
exit:
/* Identify 2-Role type */
if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC ||
wl_rinfo->link_mode == BTC_WLINK_2G_MCC ||
wl_rinfo->link_mode == BTC_WLINK_25G_MCC ||
(wl_rinfo->link_mode == BTC_WLINK_5G && cnt_connect > 1)) {
if (wl_rinfo->role_map.role.p2p_go ||
wl_rinfo->role_map.role.ap) {
if (noa_exist)
wl_rinfo->mrole_type = BTC_WLMROLE_STA_GO_NOA;
else
wl_rinfo->mrole_type = BTC_WLMROLE_STA_GO;
} else if (wl_rinfo->role_map.role.p2p_gc) {
if (noa_exist)
wl_rinfo->mrole_type = BTC_WLMROLE_STA_GC_NOA;
else
wl_rinfo->mrole_type = BTC_WLMROLE_STA_GC;
} else {
wl_rinfo->mrole_type = BTC_WLMROLE_STA_STA;
}
wl_rinfo->mrole_noa_duration = noa_duration;
} else {
wl_rinfo->mrole_type = BTC_WLMROLE_NONE;
wl_rinfo->mrole_noa_duration = 0;
}
hal_btc_fw_set_drv_info(btc, CXDRVINFO_ROLE);
if (h->dbcc_en) {
_set_wl_req_mac(btc, dbcc_2g_phy);
_update_dbcc_band(HW_PHY_0);
_update_dbcc_band(HW_PHY_1);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC);
} else {
_set_wl_req_mac(btc, HW_PHY_0);
}
}
void _run_coex(struct btc_t *btc, const char *reason)
{
struct btc_dm *dm = &btc->dm;
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_info *bt = &cx->bt;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
u8 mode = wl_rinfo->link_mode;
PHL_INFO("[BTC], %s(): reason = %s, mode=%d\n", __func__, reason, mode);
_rsn_cpy(dm->run_reason, (char*)reason);
_update_dm_step(btc, reason);
#if BTC_CX_FW_OFFLOAD
if (wl->rfk_info.state != BTC_WRFK_STOP && mode != BTC_WLINK_5G) {
_action_wl_rfk(btc);
} else if (wl->rfk_info.state == BTC_WRFK_STOP) {
PHL_INFO("[BTC], %s(): offload to WL_FW\n", __func__);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_SMAP);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_RUN);
}
goto exit;
#else
_update_btc_state_map(btc);
_get_wl_nhm_dbm(btc);
/* Be careful to change the following function sequence!! */
if (btc->ctrl.manual) {
PHL_INFO("[BTC], %s(): return for Manual CTRL!!\n", __func__);
return;
}
if (btc->ctrl.igno_bt &&
(run_rsn("_update_bt_info") || run_rsn("_update_bt_scbd"))) {
PHL_INFO("[BTC], %s(): return for Stop Coex DM!!\n", __func__);
return;
}
if (!wl->status.map.init_ok) {
PHL_INFO("[BTC], %s(): return for WL init fail!!\n", __func__);
return;
}
if (wl->status.map.rf_off_pre == wl->status.map.rf_off &&
wl->status.map.lps_pre == wl->status.map.lps) {
if (run_rsn("_ntfy_power_off") ||
run_rsn("_ntfy_radio_state")) {
PHL_INFO("[BTC], %s(): return for WL rf off state no change!!\n",
__func__);
return;
}
if (wl->status.map.rf_off == 1 || wl->status.map.lps == 1) {
PHL_INFO("[BTC], %s(): return for WL rf off state!!\n",
__func__);
return;
}
}
dm->cnt_dm[BTC_DCNT_RUN]++;
dm->freerun = false;
btc->ctrl.igno_bt = false;
bt->scan_rx_low_pri = false;
if (btc->ctrl.always_freerun) {
_action_freerun(btc);
btc->ctrl.igno_bt = true;
goto exit;
}
if (dm->wl_only) {
_action_wl_only(btc);
btc->ctrl.igno_bt = true;
goto exit;
}
if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) {
_action_wl_off(btc);
btc->ctrl.igno_bt = true;
goto exit;
}
if (run_rsn("_ntfy_init_coex")) {
_action_wl_init(btc);
goto exit;
}
if (!cx->bt.enable.now && !cx->other.type) {
_action_bt_off(btc);
goto exit;
}
if (cx->bt.whql_test) {
_action_bt_whql(btc);
goto exit;
}
if (wl->rfk_info.state != BTC_WRFK_STOP) {
_action_wl_rfk(btc);
goto exit;
}
if (cx->state_map == BTC_WLINKING &&
(mode == BTC_WLINK_NOLINK || mode == BTC_WLINK_2G_STA ||
mode == BTC_WLINK_5G)) {
_action_wl_scan(btc);
goto exit;
}
if (wl->status.map.scan) {
_action_wl_scan(btc);
goto exit;
}
switch (mode) {
case BTC_WLINK_NOLINK:
_action_wl_nc(btc);
break;
case BTC_WLINK_2G_STA:
_action_wl_2g_sta(btc);
break;
case BTC_WLINK_2G_AP:
bt->scan_rx_low_pri = true;
_action_wl_2g_ap(btc);
break;
case BTC_WLINK_2G_GO:
bt->scan_rx_low_pri = true;
_action_wl_2g_go(btc);
break;
case BTC_WLINK_2G_GC:
bt->scan_rx_low_pri = true;
_action_wl_2g_gc(btc);
break;
case BTC_WLINK_2G_SCC:
bt->scan_rx_low_pri = true;
_action_wl_2g_scc(btc);
break;
case BTC_WLINK_2G_MCC:
bt->scan_rx_low_pri = true;
_action_wl_2g_mcc(btc);
break;
case BTC_WLINK_25G_MCC:
bt->scan_rx_low_pri = true;
_action_wl_25g_mcc(btc);
break;
case BTC_WLINK_5G:
_action_wl_5g(btc);
break;
case BTC_WLINK_2G_NAN:
_action_wl_2g_nan(btc);
break;
default:
_action_wl_other(btc);
break;
}
#endif
exit:
_action_common(btc);
}
static void _update_offload_runinfo(struct btc_t *btc, u8 *buf, u32 len)
{
#if BTC_CX_FW_OFFLOAD
u32 val;
struct btc_cxr_result *r = NULL;
if (!buf || buf[0] >= BTC_CXR_MAX)
return;
switch(buf[0]) {
case BTC_CXR_WSCBD:
val = (buf[4] << 24) + (buf[3] << 16) + (buf[2] << 8) + buf[1];
if (val & BIT(31)) /* if val & BIT(31) --> write scbd bit false */
_write_scbd(btc, val & 0x7fffffff, false);
else
_write_scbd(btc, val, true);
break;
case BTC_CXR_RESULT:
r = (struct btc_cxr_result*) &buf[1];
btc->dm.freerun = r->dm.freerun;
btc->dm.wl_ps_ctrl = r->dm.wl_ps_ctrl;
btc->dm.leak_ap = r->dm.leak_ap;
btc->ctrl.igno_bt = (u16)r->dm.igno_bt;
btc->dm.noisy_level = r->dm.noisy_level;
btc->dm.set_ant_path = r->dm.set_ant_path;
btc->dm.rf_trx_para = r->rf_trx_para;
btc->cx.state_map = r->cx_state_map;
btc->policy_type = (u16)r->policy_type;
btc->dm.cnt_dm[BTC_DCNT_RUN] = r->run_cnt;
hal_mem_cpy(btc->hal, btc->dm.run_reason, r->run_reason,
BTC_RSN_MAXLEN);
hal_mem_cpy(btc->hal, btc->dm.run_action, r->run_action,
BTC_ACT_MAXLEN);
break;
}
#endif
}
void _update_bt_scbd(struct btc_t *btc, bool only_update)
{
struct btc_cx *cx = &btc->cx;
struct btc_bt_info *bt = &cx->bt;
u32 val;
bool status_change = false, bt_link_change = false;
if (!btc->chip->scbd)
return;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()\n", __func__);
val = _read_scbd(btc);
if (val == 0xffffffff) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s return by invalid scbd value\n",
__func__);
return;
}
if (!(val & BTC_BSCB_ON) ||
btc->dm.cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX)
bt->enable.now = 0;
else
bt->enable.now = 1;
if (bt->enable.now != bt->enable.last) {
status_change = true;
bt_link_change = true;
}
/* reset bt info if bt re-enable */
if (bt->enable.now && !bt->enable.last) {
_reset_btc_var(btc, BTC_RESET_BTINFO);
cx->cnt_bt[BTC_BCNT_REENABLE]++;
bt->enable.now = 1;
}
bt->enable.last = bt->enable.now;
bt->scbd = val;
bt->mbx_avl = !!(val & BTC_BSCB_ACT);
if (bt->whql_test != (u32)(!!(val & BTC_BSCB_WHQL)))
status_change = true;
bt->whql_test = !!(val & BTC_BSCB_WHQL);
bt->btg_type = (val & BTC_BSCB_BT_S1 ? BTC_BT_BTG: BTC_BT_ALONE);
bt->link_info.a2dp_desc.active = !!(val & BTC_BSCB_A2DP_ACT);
/* if rfk run 1->0 */
if (bt->rfk_info.map.run && !(val & BTC_BSCB_RFK_RUN))
status_change = true;
bt->rfk_info.map.run = !!(val & BTC_BSCB_RFK_RUN);
bt->rfk_info.map.req = !!(val & BTC_BSCB_RFK_REQ);
bt->hi_lna_rx = !!(val & BTC_BSCB_BT_HILNA);
/* if connect change */
if ((bt->link_info.status.map.connect && (!(val & BTC_BSCB_BT_CONNECT))) ||
(!bt->link_info.status.map.connect && (val & BTC_BSCB_BT_CONNECT))) {
status_change = true;
bt_link_change = true;
}
bt->link_info.status.map.connect = !!(val & BTC_BSCB_BT_CONNECT);
bt->run_patch_code = !!(val & BTC_BSCB_PATCH_CODE);
#if !BTC_CX_FW_OFFLOAD
if (bt_link_change) {
PHL_INFO("[BTC], %s: bt status change!!\n", __func__);
hal_btc_send_event(btc, NULL, 0, BTC_HMSG_BT_LINK_CHG);
}
if (!only_update && status_change)
_run_coex(btc, __func__);
#endif
}
/******************************************************************************
*
* coexistence operations for external notifications
*
*****************************************************************************/
static void _ntfy_power_on(struct btc_t *btc)
{
/* no action for power on, beacuse power-on move halmac API
* the _ntfy_power_on = _ntfy_init_coex
*/
}
static void _ntfy_power_off(struct btc_t *btc)
{
PHL_INFO("[BTC], %s()\n", __func__);
btc->dm.cnt_notify[BTC_NCNT_POWER_OFF]++;
btc->cx.wl.status.map.rf_off = 1;
btc->cx.wl.status.map.busy = 0;
_os_delay_us(btc->hal, 1000);
_write_scbd(btc, BTC_WSCB_ALL, false);
_run_coex(btc, __func__);
hal_btc_fw_en_rpt(btc, RPT_EN_ALL, 0);
btc->cx.wl.status.map.rf_off_pre = btc->cx.wl.status.map.rf_off;
}
static void _ntfy_init_coex(struct btc_t *btc, u8 mode)
{
struct btc_dm *dm = &btc->dm;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_chip_ops *ops = btc->chip->ops;
PHL_INFO("[BTC], %s(): mode=%d\n", __func__, mode);
dm->cnt_notify[BTC_NCNT_INIT_COEX]++;
dm->wl_only = (mode == BTC_MODE_WL? 1 : 0);
dm->bt_only = (mode == BTC_MODE_BT? 1 : 0);
wl->status.map.rf_off = (mode == BTC_MODE_WLOFF? 1 : 0);
if (!wl->status.map.init_ok) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return for WL init fail!!\n",
__func__);
dm->error.map.init = true;
return;
}
/* Setup RF front end type from EFuse RFE type*/
if (ops && ops->set_rfe)
ops->set_rfe(btc);
if (ops && ops->init_cfg)
ops->init_cfg(btc);
_write_scbd(btc, BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true);
_update_bt_scbd(btc, true);
/* check PTA control owner to avoid BT coex issue */
if (_read_cx_ctrl(btc) == BTC_CTRL_BY_WL) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): PTA owner warning!!\n",
__func__);
dm->error.map.pta_owner = true;
}
_set_init_info(btc);
_set_wl_tx_power(btc, BTC_WL_DEF_TX_PWR); /* original tx power, no Tx power adjust */
hal_btc_fw_set_slots(btc, CXST_MAX, dm->slot);
hal_btc_fw_set_monreg(btc);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL);
_run_coex(btc, __func__);
_btmr_start(btc);
#if 0
hal_btc_fw_set_gpio_dbg(btc, CXDGPIO_EN_MAP,
BIT(BTC_DBG_GNT_WL) | BIT(BTC_DBG_GNT_BT));
#endif
}
static void _ntfy_scan_start(struct btc_t *btc, u8 phy_idx, u8 band)
{
struct btc_wl_info *wl = &btc->cx.wl;
PHL_INFO("[BTC], %s(): phy_idx=%d, band=%d\n", __func__, phy_idx, band);
btc->dm.cnt_notify[BTC_NCNT_SCAN_START]++;
wl->status.map.scan = true;
wl->scan_info.band[phy_idx] = band;
wl->scan_info.phy_map |= BIT(phy_idx);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_SCAN);
if (btc->hal->dbcc_en) {
wl->dbcc_info.scan_band[phy_idx] = band;
_update_dbcc_band(phy_idx);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC);
}
_run_coex(btc, __func__);
}
static void _ntfy_scan_finish(struct btc_t *btc, u8 phy_idx)
{
struct btc_wl_info *wl = &btc->cx.wl;
PHL_INFO("[BTC], %s(): phy_idx=%d\n", __func__, phy_idx);
btc->dm.cnt_notify[BTC_NCNT_SCAN_FINISH]++;
wl->status.map.scan = false;
wl->scan_info.phy_map &= ~BIT(phy_idx);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_SCAN);
if (btc->hal->dbcc_en) {
_update_dbcc_band(phy_idx);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC);
}
_run_coex(btc, __func__);
}
static void _ntfy_switch_band(struct btc_t *btc, u8 phy_idx, u8 band)
{
struct btc_wl_info *wl = &btc->cx.wl;
PHL_INFO("[BTC], %s(): phy_idx=%d, band=%d\n", __func__, phy_idx, band);
btc->dm.cnt_notify[BTC_NCNT_SWITCH_BAND]++;
wl->scan_info.band[phy_idx] = band;
wl->scan_info.phy_map |= BIT(phy_idx);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_SCAN);
if (btc->hal->dbcc_en) {
wl->dbcc_info.scan_band[phy_idx] = band;
_update_dbcc_band(phy_idx);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_DBCC);
}
_run_coex(btc, __func__);
}
static void _ntfy_specific_packet(struct btc_t *btc, u8 pkt_type)
{
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_link_info *b = &cx->bt.link_info;
struct btc_bt_hfp_desc *hfp = &b->hfp_desc;
struct btc_bt_hid_desc *hid = &b->hid_desc;
u32 cnt, delay = BTC_SPECPKT_MAXT;
switch (pkt_type) {
case BTC_PKT_EVT_DHCP:
cnt = ++cx->cnt_wl[BTC_WCNT_DHCP];
PHL_INFO("[BTC], %s(): pkt_type=%d, DHCP cnt=%d \n", __func__,
pkt_type, cnt);
wl->status.map.connecting = true;
_set_btc_timer(btc, BTC_TIMER_WL_SPECPKT, delay);
break;
case BTC_PKT_EVT_EAPOL:
cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL];
PHL_INFO("[BTC], %s(): pkt_type=%d, EAPOL cnt=%d \n", __func__,
pkt_type, cnt);
wl->status.map._4way = true;
if (hfp->exist || hid->exist)
delay = delay / 2;
_set_btc_timer(btc, BTC_TIMER_WL_SPECPKT, delay);
break;
case BTC_PKT_EVT_ADD_KEY:
cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL];
PHL_INFO("[BTC], %s(): pkt_type=%d, EAPOL_End cnt=%d \n", __func__,
pkt_type, cnt);
wl->status.map._4way = false;
break;
default:
case BTC_PKT_EVT_ARP:
cnt = ++cx->cnt_wl[BTC_WCNT_ARP];
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): pkt_type=%d, ARP cnt=%d\n",
__func__, pkt_type, cnt);
return;
}
btc->dm.cnt_notify[BTC_NCNT_SPECIAL_PACKET]++;
_run_coex(btc, __func__);
}
static void _update_bt_psd(struct btc_t *btc, u8 *buf, u32 len)
{
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s():\n", __func__);
}
void _update_dm_step(struct btc_t *btc, const char *strin)
{
struct btc_dm *dm = &btc->dm;
u32 store_index = 0;
dm->dm_step.cnt++;
if (dm->dm_step.cnt == 0)
dm->dm_step.cnt = 1;
store_index = ((dm->dm_step.cnt-1) % BTC_DM_MAXSTEP);
_rsn_cpy(dm->dm_step.step[store_index], (char*)strin);
}
static void _update_bt_info(struct btc_t *btc, u8 *buf, u32 len)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_cx *cx = &btc->cx;
struct btc_bt_info *bt = &cx->bt;
struct btc_bt_link_info *b = &bt->link_info;
struct btc_bt_hfp_desc *hfp = &b->hfp_desc;
struct btc_bt_hid_desc *hid = &b->hid_desc;
struct btc_bt_a2dp_desc *a2dp = &b->a2dp_desc;
struct btc_bt_pan_desc *pan = &b->pan_desc;
union btc_btinfo btinfo;
bool bt_link_change = false;
if (buf[BTC_BTINFO_L1] != BTC_BT_INFO_LEN)
return;
/* return if bt info match last bt-info */
if (!hal_mem_cmp(h, bt->raw_info, buf, BTC_BTINFO_MAX)) {
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s return by bt-info duplicate!!\n",
__func__);
cx->cnt_bt[BTC_BCNT_INFOSAME]++;
return;
}
hal_mem_cpy(h, bt->raw_info, buf, BTC_BTINFO_MAX);
PHL_INFO("[BTC], %s: bt_info[2]=0x%02x\n", __func__, bt->raw_info[2]);
/* reset to mo-connect before update */
b->profile_cnt.last = b->profile_cnt.now;
b->relink.last = b->relink.now;
a2dp->exist_last = a2dp->exist;
b->multi_link.last = b->multi_link.now;
bt->inq_pag.last = bt->inq_pag.now;
b->profile_cnt.now = 0;
hid->type = 0;
/* ======= parse raw info low-Byte2 ======= */
btinfo.val = bt->raw_info[BTC_BTINFO_L2];
b->status.map.connect = btinfo.lb2.connect;
b->status.map.sco_busy = btinfo.lb2.sco_busy;
b->status.map.acl_busy = btinfo.lb2.acl_busy;
b->status.map.inq_pag = btinfo.lb2.inq_pag;
bt->inq_pag.now = btinfo.lb2.inq_pag;
cx->cnt_bt[BTC_BCNT_INQPAG] += !!(bt->inq_pag.now && !bt->inq_pag.last);
hfp->exist = btinfo.lb2.hfp;
b->profile_cnt.now += (u8)hfp->exist;
hid->exist = btinfo.lb2.hid;
b->profile_cnt.now += (u8)hid->exist;
a2dp->exist = btinfo.lb2.a2dp;
b->profile_cnt.now += (u8)a2dp->exist;
pan->exist = btinfo.lb2.pan;
b->profile_cnt.now += (u8)pan->exist;
/* ======= parse raw info low-Byte3 ======= */
btinfo.val = bt->raw_info[BTC_BTINFO_L3];
if (btinfo.lb3.retry != 0)
cx->cnt_bt[BTC_BCNT_RETRY]++;
b->cqddr = btinfo.lb3.cqddr;
cx->cnt_bt[BTC_BCNT_INQ] += !!(btinfo.lb3.inq && !bt->inq);
bt->inq = btinfo.lb3.inq;
cx->cnt_bt[BTC_BCNT_PAGE] += !!(btinfo.lb3.pag && !bt->pag);
bt->pag = btinfo.lb3.pag;
b->status.map.mesh_busy = btinfo.lb3.mesh_busy;
/* ======= parse raw info high-Byte0 ======= */
btinfo.val = bt->raw_info[BTC_BTINFO_H0];
/* raw val is dBm unit, translate from -100~ 0dBm to 0~100%*/
b->rssi = btc->chip->ops->bt_rssi(btc, btinfo.hb0.rssi);
/* ======= parse raw info high-Byte1 ======= */
btinfo.val = bt->raw_info[BTC_BTINFO_H1];
b->status.map.ble_connect = btinfo.hb1.ble_connect;
if (btinfo.hb1.ble_connect)
hid->type |= (hid->exist? BTC_HID_BLE : BTC_HID_RCU);
cx->cnt_bt[BTC_BCNT_REINIT] += !!(btinfo.hb1.reinit && !bt->reinit);
bt->reinit = btinfo.hb1.reinit;
cx->cnt_bt[BTC_BCNT_RELINK] += !!(btinfo.hb1.relink && !b->relink.now);
b->relink.now = btinfo.hb1.relink;
cx->cnt_bt[BTC_BCNT_IGNOWL] += !!(btinfo.hb1.igno_wl && !bt->igno_wl);
bt->igno_wl = btinfo.hb1.igno_wl;
hid->type |= (btinfo.hb1.voice? BTC_HID_RCU_VOICE : 0);
bt->ble_scan_en = btinfo.hb1.ble_scan;
cx->cnt_bt[BTC_BCNT_ROLESW] += !!(btinfo.hb1.role_sw && !b->role_sw);
b->role_sw = btinfo.hb1.role_sw;
b->multi_link.now = btinfo.hb1.multi_link;
if (b->multi_link.now != b->multi_link.last)
bt_link_change = true;
/* ======= parse raw info high-Byte2 ======= */
btinfo.val = bt->raw_info[BTC_BTINFO_H2];
pan->active = !!btinfo.hb2.pan_active;
cx->cnt_bt[BTC_BCNT_AFH] += !!(btinfo.hb2.afh_update && !b->afh_update);
b->afh_update = btinfo.hb2.afh_update;
a2dp->active = btinfo.hb2.a2dp_active;
b->slave_role = btinfo.hb2.slave;
hid->slot_info = btinfo.hb2.hid_slot;
if (hid->pair_cnt != btinfo.hb2.hid_cnt)
bt_link_change = true;
hid->pair_cnt = btinfo.hb2.hid_cnt;
hid->type |= (hid->slot_info == BTC_HID_218? BTC_HID_218 : BTC_HID_418);
/* ======= parse raw info high-Byte3 ======= */
btinfo.val = bt->raw_info[BTC_BTINFO_H3];
a2dp->bitpool = btinfo.hb3.a2dp_bitpool;
if (b->tx_3M != (u32)btinfo.hb3.tx_3M)
cx->cnt_bt[BTC_BCNT_RATECHG]++;
b->tx_3M = (u32)btinfo.hb3.tx_3M;
a2dp->sink = btinfo.hb3.a2dp_sink;
#if !BTC_CX_FW_OFFLOAD
if (bt->igno_wl && !cx->wl.status.map.rf_off)
_set_bt_ignore_wlan_act(btc, false);
if (b->profile_cnt.now || b->status.map.ble_connect)
hal_btc_fw_en_rpt(btc, RPT_EN_BT_AFH_MAP, 1);
else
hal_btc_fw_en_rpt(btc, RPT_EN_BT_AFH_MAP, 0);
if (bt_link_change) {
PHL_INFO("[BTC], %s: bt link change!!\n", __func__);
hal_btc_send_event(btc, NULL, 0, BTC_HMSG_BT_LINK_CHG);
}
/* reset after A2DP stop->play */
if (!a2dp->exist_last && a2dp->exist) {
a2dp->vendor_id = 0;
a2dp->flush_time = 0;
a2dp->play_latency = 1;
_set_btc_timer(btc, BTC_TIMER_BT_A2DPPLAY, BTC_A2DP_RESUME_MAXT);
}
if (a2dp->exist && (a2dp->flush_time == 0 || a2dp->vendor_id == 0 ||
a2dp->play_latency == 1))
hal_btc_fw_en_rpt(btc, RPT_EN_BT_DEVICE_INFO, 1);
else
hal_btc_fw_en_rpt(btc, RPT_EN_BT_DEVICE_INFO, 0);
_run_coex(btc, __func__);
#endif
}
static void _ntfy_role_info(struct btc_t *btc, u8 rid,
struct btc_wl_link_info *info,
enum role_state reason)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_link_info *wlinfo = NULL;
PHL_INFO("[BTC], %s(), role_id=%d, reason=%d\n", __func__, rid, reason);
if (rid >= MAX_WIFI_ROLE_NUMBER)
return;
btc->dm.cnt_notify[BTC_NCNT_ROLE_INFO]++;
wlinfo = &wl->link_info[rid];
hal_mem_cpy(h, wlinfo, info, sizeof(struct btc_wl_link_info));
/* update wifi_link_info_ext variable */
_update_wl_info(btc);
if (wlinfo->role == PHL_RTYPE_STATION &&
wlinfo->connected == MLME_NO_LINK)
btc->dm.leak_ap = 0;
if (reason == PHL_ROLE_MSTS_STA_CONN_START)
wl->status.map.connecting = 1;
else
wl->status.map.connecting = 0;
if (reason == PHL_ROLE_MSTS_STA_DIS_CONN)
wl->status.map._4way = false;
_run_coex(btc, __func__);
}
static void _ntfy_radio_state(struct btc_t *btc, u8 rf_state)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_chip_ops *ops = btc->chip->ops;
PHL_INFO("[BTC], %s(): rf_state =%d\n", __func__, rf_state);
btc->dm.cnt_notify[BTC_NCNT_RADIO_STATE]++;
switch(rf_state) {
case BTC_RFCTRL_WL_OFF:
wl->status.map.rf_off = 1;
wl->status.map.lps = 0;
wl->status.map.busy = 0;
break;
case BTC_RFCTRL_FW_CTRL: /* LPS-PG, LPS-CG */
wl->status.map.rf_off = 0;
wl->status.map.lps = 1;
wl->status.map.busy = 0;
break;
case BTC_RFCTRL_LPS_WL_ON: /* LPS-Protocol (RFon) */
wl->status.map.rf_off = 0;
wl->status.map.lps = 2;
wl->status.map.busy = 0;
break;
case BTC_RFCTRL_WL_ON:
default:
wl->status.map.rf_off = 0;
wl->status.map.lps = 0;
break;
}
if (rf_state == BTC_RFCTRL_WL_ON) {
hal_btc_fw_en_rpt(btc, RPT_EN_MREG, 1);
_write_scbd(btc, BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true);
_update_bt_scbd(btc, true);
if (ops && ops->init_cfg)
ops->init_cfg(btc);
} else {
hal_btc_fw_en_rpt(btc, RPT_EN_ALL, 0);
/* for BT only isolated issue,
* clear all scbd if LPS-PG or "LPS-off to LPS-Protocol"
*/
if (rf_state == BTC_RFCTRL_LPS_WL_ON &&
wl->status.map.lps_pre != 0) {
_write_scbd(btc, BTC_WSCB_ON, true);
} else {
_os_delay_us(btc->hal, 1000);
_write_scbd(btc, BTC_WSCB_ALL, false);
}
}
_run_coex(btc, __func__);
wl->status.map.rf_off_pre = wl->status.map.rf_off;
wl->status.map.lps_pre = wl->status.map.lps;
}
static void _ntfy_customerize(struct btc_t *btc, u8 type, u16 len, u8 *buf)
{
struct btc_bt_info *bt = &btc->cx.bt;
if (!buf)
return;
PHL_INFO("[BTC], %s !! \n", __func__);
btc->dm.cnt_notify[BTC_NCNT_CUSTOMERIZE]++;
switch (type) {
case PHL_BTC_CNTFY_BTINFO:
if (len != 1)
return;
buf[0] = bt->raw_info[BTC_BTINFO_L2];
break;
}
}
static u8 _ntfy_wl_rfk(struct btc_t *btc, u8 phy_path, u8 type, u8 state)
{
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
bool result = BTC_WRFK_REJECT;
wl->rfk_info.type = type;
wl->rfk_info.path_map = phy_path & BTC_RFK_PATH_MAP;
wl->rfk_info.phy_map = (phy_path & BTC_RFK_PHY_MAP) >> 4;
wl->rfk_info.band = (phy_path & BTC_RFK_BAND_MAP) >> 6;
state &= (BIT(0) | BIT(1));
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()_start: phy=0x%x, path=0x%x, type=%d, state=%d\n",
__func__, wl->rfk_info.phy_map, wl->rfk_info.path_map,
type, state);
switch (state) {
case BTC_WRFK_START:
result = _chk_wl_rfk_request(btc);
wl->rfk_info.state = (result? BTC_WRFK_START : BTC_WRFK_STOP);
#if 0
hal_btc_fw_set_drv_info(btc, CXDRVINFO_RFK);
_write_scbd(btc, BTC_WSCB_WLRFK, result);
#endif
btc->dm.cnt_notify[BTC_NCNT_WL_RFK]++;
break;
case BTC_WRFK_ONESHOT_START:
case BTC_WRFK_ONESHOT_STOP:
if (wl->rfk_info.state == BTC_WRFK_STOP) {
result = BTC_WRFK_REJECT;
} else {
result = BTC_WRFK_ALLOW;
wl->rfk_info.state = state;
}
break;
case BTC_WRFK_STOP:
result = BTC_WRFK_ALLOW;
wl->rfk_info.state = BTC_WRFK_STOP;
#if 0
hal_btc_fw_set_drv_info(btc, CXDRVINFO_RFK);
_write_scbd(btc, BTC_WSCB_WLRFK, false);
#endif
break;
}
if (result == BTC_WRFK_ALLOW) {
/* Only update coex for RFK START and STOP
* because Start -> OneSHOT_START time is short
*/
if (wl->rfk_info.state == BTC_WRFK_START ||
wl->rfk_info.state == BTC_WRFK_STOP)
_run_coex(btc, __func__);
if (wl->rfk_info.state == BTC_WRFK_START) /* wait 300ms */
_set_btc_timer(btc, BTC_TIMER_WL_RFKTO, BTC_WRFK_MAXT);
}
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,"[BTC], %s()_finish: rfk_cnt=%d, result=%d\n",
__func__, btc->dm.cnt_notify[BTC_NCNT_WL_RFK], result);
return result;
}
static void _ntfy_wl_sta(struct btc_t *btc, u8 ntfy_num,
struct btc_wl_stat_info stat_info[], u8 reason)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_module *module = &btc->mdinfo;
struct btc_wl_stat_info *w = NULL;
struct btc_traffic *t = NULL, *link_info_t = NULL;
struct btc_wl_link_info *link_info = NULL;
u8 i, j, busy = 0, dir = 0, rssi_map = 0;
u8 busy_all = 0, dir_all = 0, rssi_map_all = 0;
bool is_sta_change = false, is_traffic_change = false;
u16 last_tx_rate, last_rx_rate, last_tx_lvl, last_rx_lvl;
u32 chk_intvl = 20;
/* rssi_map = 4 bits for rssi locate in which {60, 50, 40, 30}
* if rssi >= 60% (-50dBm) --> map = 4b'0000 --> rssi_level = 0
* if 50% <= rssi < 60% --> map = 4b'0001 --> rssi_level = 1
* if 40% <= rssi < 50% --> map = 4b'0011 --> rssi_level = 2
* if 30% <= rssi < 40% --> map = 4b'0111 --> rssi_level = 3
* if rssi < 20% --> map = 4b'1111 --> rssi_level = 4
*/
btc->dm.cnt_notify[BTC_NCNT_WL_STA]++;
for (i = 0; i < ntfy_num; i++) {
w = &stat_info[i];
t = &w->stat.traffic;
link_info = &wl->link_info[w->pid];
link_info_t = &link_info->stat.traffic;
rssi_map = 0;
if (link_info->connected == MLME_NO_LINK) {
link_info->rx_rate_drop_cnt = 0;
rssi_map_all |= rssi_map;
continue;
}
last_tx_rate = link_info_t->tx_rate;
last_rx_rate = link_info_t->rx_rate;
last_tx_lvl = (u16)link_info_t->tx_lvl;
last_rx_lvl = (u16)link_info_t->rx_lvl;
/* refresh link_info traffic/rssi related info from t */
hal_mem_cpy(h, (void *)link_info_t, (void *)t,
sizeof(struct btc_traffic));
link_info->stat.rssi = w->stat.rssi;
/* check if rssi across wl_rssi_thres boundary */
for (j = 0; j < BTC_WL_RSSI_THMAX; j++) {
link_info->rssi_state[j] =
_update_rssi_state(btc,
link_info->rssi_state[j],
link_info->stat.rssi,
btc->chip->wl_rssi_thres[j]);
/* fill rssi bit map 0~3 if rssi < threshold */
if (BTC_RSSI_LOW(link_info->rssi_state[j]))
rssi_map |= BIT(j);
if (module->ant.type == BTC_ANT_DEDICATED &&
BTC_RSSI_CHANGE(link_info->rssi_state[j]))
is_sta_change = true;
}
/* OR all role rssi map */
rssi_map_all |= rssi_map;
/* set busy once idle->busy immediately */
if (t->tx_lvl != RTW_TFC_IDLE || t->rx_lvl != RTW_TFC_IDLE) {
busy = 1;
link_info->busy_t = _os_get_cur_time_ms();
if (t->tx_lvl > t->rx_lvl)
dir = TRAFFIC_UL;
else
dir = TRAFFIC_DL;
} else {/*set idle if busy -> idle after BTC_BUSY2IDLE_THRES*/
if (phl_get_passing_time_ms(link_info->busy_t) >
BTC_BUSY2IDLE_THRES || !wl->role_info.role_map.role.station ||
wl->role_info.link_mode == BTC_WLINK_NOLINK) {
busy = 0;
dir = TRAFFIC_DL;
} else {
busy = link_info->busy;
dir = link_info->dir;
}
}
if (link_info->busy != busy || link_info->dir != dir) {
is_sta_change = true;
link_info->busy = busy;
link_info->dir = dir;
}
busy_all |= link_info->busy;
dir_all |= BIT(link_info->dir);
if (link_info_t->rx_rate <= RTW_DATA_RATE_CCK2 &&
last_rx_rate > RTW_DATA_RATE_CCK2 &&
link_info_t->rx_lvl > 0)
link_info->rx_rate_drop_cnt++;
if (last_tx_rate != link_info_t->tx_rate ||
last_rx_rate != link_info_t->rx_rate ||
last_tx_lvl != link_info_t->tx_lvl ||
last_rx_lvl != link_info_t->rx_lvl )
is_traffic_change = true;
wl->role_info.active_role[w->pid].tx_lvl = (u16)t->tx_lvl;
wl->role_info.active_role[w->pid].rx_lvl = (u16)t->rx_lvl;
wl->role_info.active_role[w->pid].tx_rate = t->tx_rate;
wl->role_info.active_role[w->pid].rx_rate = t->rx_rate;
}
wl->rssi_level = 0;
for (j = BTC_WL_RSSI_THMAX; j > 0; j--) {
/* set RSSI level 4 ~ 0 if rssi bit map match */
if (rssi_map_all & BIT(j-1)) {
wl->rssi_level = j;
break;
}
}
/* for TDD/FDD packet estimation in WL FW */
if (is_traffic_change)
hal_btc_fw_set_drv_info(btc, CXDRVINFO_ROLE);
chk_intvl = 2000/BTC_PERIODIC_TIME;
if (is_sta_change) {
wl->status.map.busy = (u32)busy_all;
wl->status.map.traffic_dir = (u32)dir_all;
_write_scbd(btc, BTC_WSCB_WLBUSY, (bool)(!!wl->status.map.busy));
_run_coex(btc, __func__);
} else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] >=
btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] + chk_intvl) {
_get_wl_nhm_dbm(btc);
btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] =
btc->dm.cnt_notify[BTC_NCNT_WL_STA];
} else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] <
btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST]) {
btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] =
btc->dm.cnt_notify[BTC_NCNT_WL_STA];
}
}
static void _ntfy_fwinfo(struct btc_t *btc, u8 *buf, u32 len, u8 cls, u8 func)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
if (!buf || !len)
return;
btc->dm.cnt_notify[BTC_NCNT_FWINFO]++;
pfwinfo->cnt_c2h++;
if (cls == BTFC_FW_EVENT) {
switch (func) {
case BTF_EVNT_RPT:
case BTF_EVNT_BUF_OVERFLOW:
pfwinfo->event[func]++;
hal_btc_fw_event(btc, func, buf, len);
break;
case BTF_EVNT_BT_INFO:
btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE]++;
_update_bt_info(btc, buf, len);
break;
case BTF_EVNT_BT_SCBD:
btc->cx.cnt_bt[BTC_BCNT_SCBDUPDATE]++;
_update_bt_scbd(btc, false);
break;
case BTF_EVNT_BT_PSD:
_update_bt_psd(btc, buf, len);
break;
case BTF_EVNT_BT_REG:
btc->dbg.rb_done = true;
btc->dbg.rb_val = ((buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | (buf[0]));
break;
case BTF_EVNT_C2H_LOOPBACK:
btc->dbg.rb_done = true;
btc->dbg.rb_val = buf[0];
break;
case BTF_EVNT_CX_RUNINFO:
btc->dm.cnt_dm[BTC_DCNT_CX_RUNINFO]++;
_update_offload_runinfo(btc, buf, len);
break;
}
}
}
static void _ntfy_timer(struct btc_t *btc, u16 tmr_id)
{
struct btc_dm *dm = &btc->dm;
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_a2dp_desc *a2dp = &cx->bt.link_info.a2dp_desc;
bool is_sta_change = false;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], %s(): tmr_id =%d\n", __func__, tmr_id);
dm->cnt_notify[BTC_NCNT_TIMER]++;
if (tmr_id == BTC_TIMER_PERIODIC) {
/* start next periodic timer */
_set_btc_timer(btc, BTC_TIMER_PERIODIC, BTC_PERIODIC_TIME);
} else if (tmr_id == BTC_TIMER_WL_RFKTO) {
if (wl->rfk_info.state != BTC_WRFK_STOP) {
cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]++;
dm->error.map.wl_rfk_timeout = true;
wl->rfk_info.state = BTC_WRFK_STOP;
/* _write_scbd(btc, BTC_WSCB_WLRFK, false); */
is_sta_change = true;
}
} else if (tmr_id == BTC_TIMER_WL_SPECPKT) {
wl->status.map._4way = false;
wl->status.map.connecting = 0;
is_sta_change = true;
} else if (tmr_id == BTC_TIMER_BT_A2DPPLAY) {
a2dp->play_latency = 0;
is_sta_change = true;
}
if (is_sta_change)
_run_coex(btc, __func__);
}
/******************************************************************************
*
* coexistence extern functions
*
*****************************************************************************/
/*
* btc related sw initialization
*/
bool hal_btc_init(struct btc_t *btc)
{
switch (btc->hal->chip_id) {
#ifdef BTC_8852A_SUPPORT
case CHIP_WIFI6_8852A:
PHL_INFO("[BTC], %s(): Init 8852A!!\n", __func__);
btc->chip = &chip_8852a;
break;
#endif
#ifdef BTC_8852B_SUPPORT
case CHIP_WIFI6_8852B:
PHL_INFO("[BTC], %s(): Init 8852B!!\n", __func__);
btc->chip = &chip_8852b;
break;
#endif
#ifdef BTC_8852C_SUPPORT
case CHIP_WIFI6_8852C:
PHL_INFO("[BTC], %s(): Init 8852C!!\n", __func__);
btc->chip = &chip_8852c;
break;
#endif
default:
PHL_ERR("[BTC], %s(): no matched IC!!\n", __func__);
btc->cx.wl.status.map.init_ok = false;
return false;
}
_reset_btc_var(btc, BTC_RESET_ALL);
_btmr_init(btc);
_rsn_cpy(btc->dm.run_reason, "None");
_act_cpy(btc->dm.run_action, "None");
btc->hal->btc_vc.btc_ver = coex_ver;
btc->ops = &_btc_ops;
btc->mlen = BTC_MSG_MAXLEN;
btc->ctrl.igno_bt = true;
btc->cx.wl.status.map.init_ok = true;
return true;
}
void hal_btc_deinit(struct btc_t *btc)
{
_btmr_deinit(btc);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/hal_btc.c
|
C
|
agpl-3.0
| 48,462
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_BTC_H_
#define _HAL_BTC_H_
#include "halbtc_fw.h"
#include "halbtc_dbg_cmd.h"
#ifdef CONFIG_RTL8852A
#define BTC_8852A_SUPPORT
#endif
#ifdef CONFIG_RTL8852B
#define BTC_8852B_SUPPORT
#endif
#ifdef CONFIG_RTL8852C
#define BTC_8852C_SUPPORT
#endif
#define BTC_GPIO_DBG_EN 1
#define BTC_CX_FW_OFFLOAD 0
#define BTC_PHY_MAX 2
#define BTC_NON_SHARED_ANT_FREERUN 0
#define BTC_MSG_MAXLEN 200
#define BTC_POLICY_MAXLEN 512
#define BTC_HUBMSG_MAXLEN 512
#define BTC_RPT_PERIOD 2000
#define BTC_RSN_MAXLEN 32
#define BTC_ACT_MAXLEN 32
#define BTC_DELAYED_PERIODIC_TIME 2000 /* 2000ms, delayed to start periodic timer */
#define BTC_PERIODIC_TIME 100 /* 100ms, must be non zero and < 2000 */
#define BTC_WRFK_MAXT 300 /* WL RFK 300ms */
#define BTC_BRFK_MAXT 800 /* BT RFK 800ms */
#define BTC_SPECPKT_MAXT 4000 /* special pkt unit: 4000ms */
#define BTC_A2DP_RESUME_MAXT 16000 /* for A2DP resume, 16sec = 16000ms */
#define BTC_RPT_HDR_SIZE 3
#define BTC_BUSY2IDLE_THRES 10000 /* wait time for WL busy-to-idle, 10sec = 10000ms */
#define BTC_WL_DEF_TX_PWR 255
/* reserved 5 rf_trx_para level for non-freerun case */
#define BTC_LEVEL_ID_OFFSET 5
/* Define MAC-Related Reg Addr and Bitmap
* These definitions should be removed if MACAPI support.
*/
#define BTC_DM_MAXSTEP 30
#define BTC_LEAK_AP_TH 10
#define BTC_CYSTA_CHK_PERIOD 100
#define BTC_SCC_CYCLE 100
#define BTC_NULL1_EBT_EARLY_T 10
#define R_BTC_CFG 0xDA00
#define R_BTC_WL_PRI_MSK 0xDA10
#define R_BTC_BREAK_TABLE 0xDA2C
#define R_BTC_BT_COEX_MSK_TABLE 0xDA30
#define R_BTC_CSR_MODE 0xDA40
#define R_BTC_BT_STAST_HIGH 0xDA44
#define R_BTC_BT_STAST_LOW 0xDA48
#define B_BTC_WL_SRC BIT(0)
#define B_BTC_DIS_BTC_CLK_G BIT(2)
#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
#define B_BTC_DBG_GNT_WL_BT BIT(27)
#define B_BTC_BT_CNT_REST BIT(16)
#define B_BTC_PTA_WL_PRI_MASK_BCNQ BIT(8)
#define B_BTC_PTA_WL_PRI_MASK_MGQ BIT(4)
struct btc_t;
#define NM_EXEC false
#define FC_EXEC true
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
#ifndef BIT
#define BIT(x) (1 << (x))
#endif
#define bMASKDW 0xffffffff
#define bMASKHW 0xffff0000
#define bMASKLW 0x0000ffff
#define bMASKB0 0x000000ff
#define bMASKB1 0x0000ff00
#define bMASKB2 0x00ff0000
#define bMASKB3 0xff000000
#define bMASKRF 0x000fffff
#define BTC_WL_RSSI_THMAX 4
#define BTC_BT_RSSI_THMAX 4
#define BTC_TDMA_WLROLE_MAX 2
#define BTC_TDMA_BTHID_MAX 2
#define BTC_FREERUN_ANTISO_MIN 30
#define BTC_BT_RX_NORMAL_LVL 7
#define BTC_BT_INFO_LEN 6
#define BTC_B1_MAX 250 /* unit:ms, used for Max A2DP retry adjust */
#define BTC_COEX_RTK_MODE 0
#define BTC_COEX_CSR_MODE 1
#define BTC_COEX_INNER 0
#define BTC_COEX_OUTPUT 1
#define BTC_COEX_INPUT 2
#define BTC_BLINK_NOCONNECT 0
#define BTC_WL_NONE 0
#define BTC_CHK_HANG_MAX 3
#define BTC_CHK_WLSLOT_DRIFT_MAX 15
#define BTC_CHK_BTSLOT_DRIFT_MAX 15
#define BTC_RFK_PATH_MAP 0xf
#define BTC_RFK_PHY_MAP 0x30
#define BTC_RFK_BAND_MAP 0xc0
#define _write_cx_reg(btc, offset, val) \
rtw_hal_mac_coex_reg_write(btc->hal, offset, val)
#define _read_wl_rf_reg(btc, path, addr, mask) \
rtw_hal_read_rf_reg(btc->hal, path, addr, mask);
#define _write_wl_rf_reg(btc, path, addr, mask, data) \
rtw_hal_write_rf_reg(btc->hal, path, addr, mask, data)
#define _update_poicy hal_btc_fw_set_policy
#define run_rsn(r) \
(hal_mem_cmp(btc->hal, btc->dm.run_reason, r, _os_strlen((u8*)r))? 0:1)
#define _rsn_cpy(dst, src) \
hal_mem_cpy(btc->hal, dst, src, BTC_RSN_MAXLEN)
#define _act_cpy(dst, src) \
hal_mem_cpy(btc->hal, dst, src, BTC_ACT_MAXLEN)
#define _tdma_cmp(dst, src) \
hal_mem_cmp(btc->hal, dst, src, sizeof(struct fbtc_tdma))
#define _tdma_cpy(dst, src) \
hal_mem_cpy(btc->hal, dst, src, sizeof(struct fbtc_tdma))
#define _tdma_set(tp,rxflc,txflc,wtg,lek,ext,flc_role) \
do { \
btc->dm.tdma.type = tp;\
btc->dm.tdma.rxflctrl = rxflc; \
btc->dm.tdma.txflctrl = txflc; \
btc->dm.tdma.wtgle_n = wtg; \
btc->dm.tdma.leak_n = lek; \
btc->dm.tdma.ext_ctrl = ext; \
btc->dm.tdma.rxflctrl_role = flc_role; \
} while (0)
#define _tdma_set_rxflctrl(rxflc) btc->dm.tdma.rxflctrl = rxflc
#define _tdma_set_txflctrl(txflc) btc->dm.tdma.txflctrl = txflc
#define _tdma_set_flctrl_role(role) btc->dm.tdma.rxflctrl_role = role
#define _tdma_set_tog(wtg) btc->dm.tdma.wtgle_n = wtg
#define _tdma_set_lek(lek) btc->dm.tdma.leak_n = lek
#define _slot_cmp(dst, src) \
hal_mem_cmp(btc->hal, dst, src, sizeof(struct fbtc_slot))
#define _slot_cpy(dst, src) \
hal_mem_cpy(btc->hal, dst, src, sizeof(struct fbtc_slot))
#define _slots_cpy(dst, src) \
hal_mem_cpy(btc->hal, dst, src, CXST_MAX*sizeof(struct fbtc_slot))
#define _slot_set(sid,dura,tbl,type) \
do { \
btc->dm.slot[sid].dur = dura;\
btc->dm.slot[sid].cxtbl = tbl; \
btc->dm.slot[sid].cxtype = type; \
} while (0)
#define _slot_set_dur(sid,dura) btc->dm.slot[sid].dur = dura
#define _slot_set_tbl(sid,tbl) btc->dm.slot[sid].cxtbl = tbl
#define _slot_set_type(sid,type) btc->dm.slot[sid].cxtype = type
enum btc_wl_gpio_debug {
BTC_DBG_GNT_BT = 0,
BTC_DBG_GNT_WL = 1,
/* The following signals should 0-1 tiggle by each function-call */
BTC_DBG_BCN_EARLY = 2,
BTC_DBG_WL_NULL0 = 3,
BTC_DBG_WL_NULL1 = 4,
BTC_DBG_WL_RXISR = 5,
BTC_DBG_TDMA_ENTRY = 6,
BTC_DBG_A2DP_EMPTY = 7,
BTC_DBG_BT_RETRY = 8,
/* The following signals should 0-1 tiggle by state L/H */
BTC_DBG_BT_RELINK = 9,
BTC_DBG_SLOT_WL = 10,
BTC_DBG_SLOT_BT = 11,
BTC_DBG_WL_RFK = 12,
BTC_DBG_BT_RFK = 13,
/* The following signals should appear only 1 "Hi" at same time */
BTC_DBG_SLOT_B2W = 14,
BTC_DBG_SLOT_W1 = 15,
BTC_DBG_SLOT_W2 = 16,
BTC_DBG_SLOT_W2B = 17,
BTC_DBG_SLOT_B1 = 18,
BTC_DBG_SLOT_B2 = 19,
BTC_DBG_SLOT_B3 = 20,
BTC_DBG_SLOT_B4 = 21,
BTC_DBG_SLOT_LK = 22,
BTC_DBG_SLOT_E2G = 23,
BTC_DBG_SLOT_E5G = 24,
BTC_DBG_SLOT_EBT = 25,
BTC_DBG_SLOT_ENULL = 26,
BTC_DBG_SLOT_WLK = 27,
BTC_DBG_SLOT_W1FDD = 28,
BTC_DBG_SLOT_B1FDD = 29,
BTC_DBG_BT_CHANGE = 30
};
enum btc_cx_run_info {
BTC_CXR_WSCBD = 0,
BTC_CXR_RESULT,
BTC_CXR_MAX
};
enum btc_bt_rfk_state {
BTC_BRFK_STOP = 0,
BTC_BRFK_START = 1
};
enum btc_wl_rfk_state {
BTC_WRFK_STOP = 0,
BTC_WRFK_START = 1,
BTC_WRFK_ONESHOT_START = 2,
BTC_WRFK_ONESHOT_STOP = 3
};
enum btc_wl_rfk_result {
BTC_WRFK_REJECT = 0,
BTC_WRFK_ALLOW = 1
};
enum {
BTC_CTRL_BY_BT = 0,
BTC_CTRL_BY_WL
};
enum {
BTC_3CX_NONE = 0,
BTC_3CX_LTE = 1,
BTC_3CX_ZB = 2,
BTC_3CX_MAX
};
enum {
BTC_PRI_MASK_RX_RESP = 0,
BTC_PRI_MASK_TX_RESP,
BTC_PRI_MASK_BEACON,
BTC_PRI_MASK_RX_CCK,
BTC_PRI_MASK_TX_MNGQ,
BTC_PRI_MASK_MAX
};
enum {
BTC_INIT_NORMAL,
BTC_INIT_WLONLY,
BTC_INIT_WLOFF
};
enum {
BTC_BRANCH_MAIN = 0,
BTC_BRANCH_HP,
BTC_BRANCH_LENOVO,
BTC_BRANCH_HUAWEI,
BTC_BRANCH_MAX
};
enum {
BTC_STR_ROLE = 0,
BTC_STR_MROLE,
BTC_STR_REG,
BTC_STR_SLOT,
BTC_STR_TDMA,
BTC_STR_TRACE,
BTC_STR_BRANCH,
BTC_STR_RXFLCTRL,
BTC_STR_WLLINK,
BTC_STR_ANTPATH,
BTC_STR_GDBG,
BTC_STR_CHIPID,
BTC_STR_EVENT,
BTC_STR_WLMODE,
BTC_STR_WLBW,
BTC_STR_RFTYPE,
BTC_STR_POLICY,
BTC_STR_MSTATE,
BTC_STR_RATE,
BTC_STR_POLUT,
BTC_STR_MAX
};
enum {
BTC_WL = 0,
BTC_BT,
BTC_ZB,
BTC_LTE,
BTC_MAX
};
enum {
BTC_BT_SS_GROUP = 0x0,
BTC_BT_TX_GROUP = 0x2,
BTC_BT_RX_GROUP = 0x3,
BTC_BT_MAX_GROUP,
};
enum btc_rssi_st {
BTC_RSSI_ST_LOW = 0x0,
BTC_RSSI_ST_HIGH,
BTC_RSSI_ST_STAY_LOW,
BTC_RSSI_ST_STAY_HIGH,
BTC_RSSI_ST_MAX
};
#define BTC_RSSI_HIGH(_rssi_) \
((_rssi_ == BTC_RSSI_ST_HIGH || _rssi_ == BTC_RSSI_ST_STAY_HIGH)? 1:0)
#define BTC_RSSI_LOW(_rssi_) \
((_rssi_ == BTC_RSSI_ST_LOW || _rssi_ == BTC_RSSI_ST_STAY_LOW)? 1:0)
#define BTC_RSSI_CHANGE(_rssi_) \
((_rssi_ == BTC_RSSI_ST_LOW || _rssi_ == BTC_RSSI_ST_HIGH)? 1:0)
enum btc_coex_info_map_en {
BTC_COEX_INFO_CX = BIT(0),
BTC_COEX_INFO_WL = BIT(1),
BTC_COEX_INFO_BT = BIT(2),
BTC_COEX_INFO_DM = BIT(3),
BTC_COEX_INFO_MREG = BIT(4),
BTC_COEX_INFO_SUMMARY = BIT(5),
BTC_COEX_INFO_ALL = 0xff
};
/* list all-chip scoreboard definition, remap at chip file */
enum btc_w2b_scoreboard {
BTC_WSCB_ACTIVE = BIT(0),
BTC_WSCB_ON = BIT(1),
BTC_WSCB_SCAN = BIT(2),
BTC_WSCB_UNDERTEST = BIT(3),
BTC_WSCB_RXGAIN = BIT(4), /* set BT LNA constrain for free-run */
BTC_WSCB_WLBUSY = BIT(7),
BTC_WSCB_EXTFEM = BIT(8),
BTC_WSCB_TDMA = BIT(9),
BTC_WSCB_FIX2M = BIT(10),
BTC_WSCB_WLRFK = BIT(11),
BTC_WSCB_RXSCAN_PRI = BIT(12), /* set BT Rx-Scan PTA pri */
BTC_WSCB_BT_HILNA = BIT(13), /* 1: request BT use Hi-LNA table for BTG */
BTC_WSCB_BTLOG = BIT(14), /* open BT log */
BTC_WSCB_ALL = 0xffffff /* driver only use bit0~23 */
};
enum btc_b2w_scoreboard {
BTC_BSCB_ACT = BIT(0),
BTC_BSCB_ON = BIT(1),
BTC_BSCB_WHQL = BIT(2),
BTC_BSCB_BT_S1 = BIT(3), /* 1-> BT at S1, 0-> BT at S0 */
BTC_BSCB_A2DP_ACT = BIT(4),
BTC_BSCB_RFK_RUN = BIT(5),
BTC_BSCB_RFK_REQ = BIT(6),
BTC_BSCB_LPS = BIT(7),
BTC_BSCB_WLRFK = BIT(11),
BTC_BSCB_BT_HILNA = BIT(13), /* reply if BT use Hi-LNA table for BTG */
BTC_BSCB_BT_CONNECT = BIT(16), /* If any BT connected */
BTC_BSCB_PATCH_CODE = BIT(30), /* BT use 1: patch code 2:ROM code */
BTC_BSCB_ALL = 0x7fffffff
};
enum btc_bt_link_status {
BTC_BLINK_CONNECT = BIT(0),
BTC_BLINK_BLE_CONNECT = BIT(1),
BTC_BLINK_ACL_BUSY = BIT(2),
BTC_BLINK_SCO_BUSY = BIT(3),
BTC_BLINK_MESH_BUSY = BIT(4),
BTC_BLINK_INQ_PAGE = BIT(5)
};
enum {
BTC_DCNT_RUN = 0x0,
BTC_DCNT_CX_RUNINFO,
BTC_DCNT_RPT,
BTC_DCNT_RPT_FREEZE,
BTC_DCNT_CYCLE,
BTC_DCNT_CYCLE_FREEZE,
BTC_DCNT_W1,
BTC_DCNT_W1_FREEZE,
BTC_DCNT_B1,
BTC_DCNT_B1_FREEZE,
BTC_DCNT_TDMA_NONSYNC,
BTC_DCNT_SLOT_NONSYNC,
BTC_DCNT_BTCNT_FREEZE,
BTC_DCNT_WL_SLOT_DRIFT,
BTC_DCNT_WL_STA_LAST,
BTC_DCNT_BT_SLOT_DRIFT,
BTC_DCNT_MAX
};
enum {
BTC_NCNT_POWER_ON = 0x0,
BTC_NCNT_POWER_OFF,
BTC_NCNT_INIT_COEX,
BTC_NCNT_SCAN_START,
BTC_NCNT_SCAN_FINISH,
BTC_NCNT_SPECIAL_PACKET,
BTC_NCNT_SWITCH_BAND,
BTC_NCNT_RFK_TIMEOUT,
BTC_NCNT_SHOW_COEX_INFO,
BTC_NCNT_ROLE_INFO,
BTC_NCNT_CONTROL,
BTC_NCNT_RADIO_STATE,
BTC_NCNT_CUSTOMERIZE,
BTC_NCNT_WL_RFK,
BTC_NCNT_WL_STA,
BTC_NCNT_FWINFO,
BTC_NCNT_TIMER,
BTC_NCNT_MAX
};
enum btc_wl_state_cnt {
BTC_WCNT_SCANAP = 0x0,
BTC_WCNT_DHCP,
BTC_WCNT_EAPOL,
BTC_WCNT_ARP,
BTC_WCNT_SCBDUPDATE,
BTC_WCNT_RFK_REQ,
BTC_WCNT_RFK_GO,
BTC_WCNT_RFK_REJECT,
BTC_WCNT_RFK_TIMEOUT,
BTC_WCNT_CH_UPDATE,
BTC_WCNT_MAX
};
enum btc_bt_state_cnt {
BTC_BCNT_RETRY = 0x0,
BTC_BCNT_REINIT,
BTC_BCNT_REENABLE,
BTC_BCNT_SCBDREAD,
BTC_BCNT_RELINK,
BTC_BCNT_IGNOWL,
BTC_BCNT_INQPAG,
BTC_BCNT_INQ,
BTC_BCNT_PAGE,
BTC_BCNT_ROLESW,
BTC_BCNT_AFH,
BTC_BCNT_INFOUPDATE,
BTC_BCNT_INFOSAME,
BTC_BCNT_SCBDUPDATE,
BTC_BCNT_HIPRI_TX,
BTC_BCNT_HIPRI_RX,
BTC_BCNT_LOPRI_TX,
BTC_BCNT_LOPRI_RX,
BTC_BCNT_RATECHG,
BTC_BCNT_MAX
};
enum btc_wl_link_mode {
BTC_WLINK_NOLINK = 0x0,
BTC_WLINK_2G_STA,
BTC_WLINK_2G_AP,
BTC_WLINK_2G_GO,
BTC_WLINK_2G_GC,
BTC_WLINK_2G_SCC,
BTC_WLINK_2G_MCC,
BTC_WLINK_25G_MCC,
BTC_WLINK_25G_DBCC,
BTC_WLINK_5G,
BTC_WLINK_2G_NAN,
BTC_WLINK_OTHER,
BTC_WLINK_MAX
};
enum btc_wl_mrole_type {
BTC_WLMROLE_NONE = 0x0,
BTC_WLMROLE_STA_GC,
BTC_WLMROLE_STA_GC_NOA,
BTC_WLMROLE_STA_GO,
BTC_WLMROLE_STA_GO_NOA,
BTC_WLMROLE_STA_STA,
BTC_WLMROLE_MAX
};
enum {
BTC_BTINFO_L0 = 0,
BTC_BTINFO_L1,
BTC_BTINFO_L2,
BTC_BTINFO_L3,
BTC_BTINFO_H0,
BTC_BTINFO_H1,
BTC_BTINFO_H2,
BTC_BTINFO_H3,
BTC_BTINFO_MAX
};
struct btc_btinfo_lb2 {
u8 connect: 1;
u8 sco_busy: 1;
u8 inq_pag: 1;
u8 acl_busy: 1;
u8 hfp: 1;
u8 hid: 1;
u8 a2dp: 1;
u8 pan: 1;
};
struct btc_btinfo_lb3 {
u8 retry: 4;
u8 cqddr: 1;
u8 inq: 1;
u8 mesh_busy: 1;
u8 pag: 1;
};
struct btc_btinfo_hb0 {
u8 rssi;
};
struct btc_btinfo_hb1 {
u8 ble_connect: 1;
u8 reinit: 1;
u8 relink: 1;
u8 igno_wl: 1;
u8 voice: 1;
u8 ble_scan: 1;
u8 role_sw: 1;
u8 multi_link: 1;
};
struct btc_btinfo_hb2 {
u8 pan_active: 1;
u8 afh_update: 1;
u8 a2dp_active: 1;
u8 slave: 1;
u8 hid_slot: 2;
u8 hid_cnt: 2;
};
struct btc_btinfo_hb3 {
u8 a2dp_bitpool: 6;
u8 tx_3M: 1;
u8 a2dp_sink: 1;
};
union btc_btinfo {
u8 val;
struct btc_btinfo_lb2 lb2;
struct btc_btinfo_lb3 lb3;
struct btc_btinfo_hb0 hb0;
struct btc_btinfo_hb1 hb1;
struct btc_btinfo_hb2 hb2;
struct btc_btinfo_hb3 hb3;
};
enum btc_rinfo_lo_b2 {
BTC_RINFO_INQPAG = BIT(2),
};
enum btc_bt_hfp_type {
BTC_HFP_SCO = 0,
BTC_HFP_ESCO = 1,
BTC_HFP_ESCO_2SLOT = 2,
};
enum btc_bt_hid_type {
BTC_HID_218 = BIT(0),
BTC_HID_418 = BIT(1),
BTC_HID_BLE = BIT(2),
BTC_HID_RCU = BIT(3),
BTC_HID_RCU_VOICE = BIT(4),
BTC_HID_OTHER_LEGACY = BIT(5)
};
enum btc_bt_a2dp_type {
BTC_A2DP_LEGACY = 0,
BTC_A2DP_TWS_SNIFF = 1, /* Airpod */
BTC_A2DP_TWS_RELAY = 2, /* RTL8763B */
};
enum btc_bt_PAN_type {
BTC_BT_PAN_ONLY = 0,
BTC_BT_OPP_ONLY = 1
};
enum btc_bt_scan_type {
BTC_SCAN_INQ = 0,
BTC_SCAN_PAGE,
BTC_SCAN_BLE,
BTC_SCAN_INIT,
BTC_SCAN_TV,
BTC_SCAN_ADV,
BTC_SCAN_MAX1
};
enum btc_bt_mailbox_id {
BTC_BTINFO_REPLY = 0x23,
BTC_BTINFO_AUTO = 0x27
};
enum {
BTC_BT_HFP = BIT(0),
BTC_BT_HID = BIT(1),
BTC_BT_A2DP = BIT(2),
BTC_BT_PAN = BIT(3),
BTC_PROFILE_MAX = 4
};
enum {
BTC_BT_IQK_OK = 0,
BTC_BT_IQK_START = 1,
BTC_BT_IQK_STOP = 2,
BTC_BT_IQK_MAX
};
enum {
BTC_ANT_SHARED = 0,
BTC_ANT_DEDICATED,
BTC_ANTTYPE_MAX
};
enum {
BTC_BT_ALONE = 0,
BTC_BT_BTG
};
enum {
BTC_SWITCH_INTERNAL = 0,
BTC_SWITCH_EXTERNAL
};
enum {
BTC_RESET_CX = BIT(0),
BTC_RESET_DM = BIT(1),
BTC_RESET_CTRL = BIT(2),
BTC_RESET_CXDM = BIT(0) | BIT(1),
BTC_RESET_BTINFO = BIT(3),
BTC_RESET_MDINFO = BIT(4),
BTC_RESET_ALL = 0xff
};
enum btc_gnt_state {
BTC_GNT_HW = 0,
BTC_GNT_SW_LO,
BTC_GNT_SW_HI,
BTC_GNT_MAX
};
enum btc_wl_max_tx_time {
BTC_MAX_TX_TIME_L1 = 500,
BTC_MAX_TX_TIME_L2 = 1000,
BTC_MAX_TX_TIME_L3 = 2000,
BTC_MAX_TX_TIME_DEF = 5280
};
enum btc_wl_max_tx_retry {
BTC_MAX_TX_RETRY_L1 = 7,
BTC_MAX_TX_RETRY_L2 = 15,
BTC_MAX_TX_RETRY_DEF = 31
};
struct btc_wl_tx_limit_para {
u16 enable;
u32 tx_time; /* unit: us */
u16 tx_retry;
};
struct btc_rf_trx_para {
u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
u32 wl_rx_gain; /* rx gain table index (TBD.) */
u32 bt_tx_power; /* decrease Tx power (dB) */
u32 bt_rx_gain; /* LNA constrain level */
};
struct btc_gnt_ctrl {
u8 gnt_bt_sw_en;
u8 gnt_bt;
u8 gnt_wl_sw_en;
u8 gnt_wl;
};
struct btc_fw_dm {
u32 freerun: 1;
u32 wl_ps_ctrl: 2; /* 0: off, 1: force on, 2:forec off */
u32 wl_mimo_ps: 1;
u32 leak_ap: 1;
u32 igno_bt: 1;
u32 noisy_level: 3;
u32 set_ant_path: 16;
u32 rsvd: 7;
};
struct btc_cxr_result {
struct btc_fw_dm dm;
struct btc_rf_trx_para rf_trx_para;
u32 cx_state_map;
u32 policy_type;
u32 run_cnt;
char run_reason[BTC_RSN_MAXLEN];
char run_action[BTC_ACT_MAXLEN];
};
struct btc_bt_hfp_desc {
u32 exist: 1;
u32 type: 2; /* refer to btc_bt_hfp_type */
u32 rsvd: 29;
};
struct btc_bt_hid_desc {
u32 exist: 1;
u32 slot_info: 2;
u32 pair_cnt: 2;
u32 type: 8; /* refer to btc_bt_hid_type */
u32 rsvd: 19;
};
struct btc_bt_a2dp_desc {
u8 exist: 1;
u8 exist_last: 1;
u8 play_latency: 1;
u8 type: 3; /* refer to btc_bt_a2dp_type */
u8 active: 1;
u8 sink: 1;
u8 bitpool;
u16 vendor_id;
u32 device_name;
u32 flush_time;
};
struct btc_bt_pan_desc {
u32 exist: 1;
u32 type: 1; /* refer to btc_bt_pan_type */
u32 active: 1;
u32 rsvd: 29;
};
struct btc_wl_nhm {
s8 instant_wl_nhm_dbm;
s8 instant_wl_nhm_per_mhz;
u16 valid_record_times;
s8 record_pwr[16];
u8 record_ratio[16];
s8 pwr; /* dbm_per_MHz */
u8 ratio;
u8 current_status;
u8 refresh;
bool start_flag;
u8 last_ccx_rpt_stamp;
};
struct btc_chip_ops {
void (*set_rfe)(struct btc_t *btc);
void (*init_cfg)(struct btc_t *btc);
void (*wl_pri)(struct btc_t *btc, u8 mask, bool state);
void (*wl_tx_power)(struct btc_t *btc, u32 level);
void (*wl_rx_gain)(struct btc_t *btc, u32 level);
void (*wl_s1_standby)(struct btc_t *btc, u32 state);
void (*wl_req_mac)(struct btc_t *btc, u8 mac_id);
void (*update_bt_cnt)(struct btc_t *btc);
u8 (*bt_rssi)(struct btc_t *btc, u8 val);
};
struct btc_chip {
u8 chip_id;
u32 para_ver; /* chip parameter version */
u8 btcx_desired; /* bt fw desired coex version */
u32 wlcx_desired; /* wl fw desired coex version */
u8 scbd; /* scoreboard version, 0: not support*/
u8 mailbox; /* mailbox version, 0: not support */
u8 pta_mode;
u8 pta_direction;
u8 afh_guard_ch;
const u8 *wl_rssi_thres; /* wl rssi thre level */
const u8 *bt_rssi_thres; /* bt rssi thre level */
u8 rssi_tol; /* rssi tolerance */
struct btc_chip_ops *ops;
u8 mon_reg_num;
struct fbtc_mreg *mon_reg;
u8 rf_para_ulink_num;
struct btc_rf_trx_para *rf_para_ulink;
u8 rf_para_dlink_num;
struct btc_rf_trx_para *rf_para_dlink;
};
struct btc_bt_scan_info {
u16 win;
u16 intvl;
u32 enable: 1;
u32 interlace: 1;
u32 rsvd: 30;
};
struct btc_bt_rfk_info {
u32 run: 1;
u32 req: 1;
u32 timeout: 1;
u32 rsvd: 29;
};
union btc_bt_rfk_info_map {
u32 val;
struct btc_bt_rfk_info map;
};
struct btc_bt_ver_info {
u32 fw_coex; /* match with which coex_ver */
u32 fw;
};
struct btc_bool_sta_chg { /* status change varible */
u32 now: 1;
u32 last: 1;
u32 remain: 1;
u32 srvd: 29;
};
struct btc_u8_sta_chg { /* status change varible */
u8 now;
u8 last;
u8 remain;
u8 rsvd;
};
struct btc_bit_remap {
u32 index;
u32 bpos;
};
struct btc_ant_info {
u8 type; /* shared, dedicated */
u8 num;
u8 isolation;
u8 single_pos: 1;/* Single antenna at S0 or S1 */
u8 diversity: 1;
};
struct btc_traffic {
enum rtw_tfc_lvl tx_lvl;
enum rtw_tfc_sts tx_sts;
enum rtw_tfc_lvl rx_lvl;
enum rtw_tfc_sts rx_sts;
u16 tx_rate;
u16 rx_rate;
};
struct btc_wl_scan_info {
u8 band[HW_PHY_MAX];
u8 phy_map;
u8 rsvd;
};
struct btc_wl_dbcc_info {
u8 op_band[HW_PHY_MAX]; /* op band in each phy */
u8 scan_band[HW_PHY_MAX]; /* scan band in each phy */
u8 real_band[HW_PHY_MAX];
u8 role[HW_PHY_MAX]; /* role in each phy */
};
struct btc_wl_active_role { /* struct size must be n*4 bytes */
u8 connected: 1;
u8 pid: 3;
u8 phy: 1;
u8 noa: 1;
u8 band: 2; /* enum band_type RF band: 2.4G/5G/6G */
u8 client_ps: 1;
u8 bw: 7; /* enum channel_width */
u8 role; /*enum role_type */
u8 ch;
u16 tx_lvl;
u16 rx_lvl;
u16 tx_rate;
u16 rx_rate;
u32 noa_duration; /* ms */
};
struct btc_wl_role_info_bpos {
u16 none: 1;
u16 station: 1;
u16 ap: 1;
u16 vap: 1;
u16 adhoc: 1;
u16 adhoc_master: 1;
u16 mesh: 1;
u16 moniter: 1;
u16 p2p_device: 1;
u16 p2p_gc: 1;
u16 p2p_go: 1;
u16 nan: 1;
};
union btc_wl_role_info_map {
u16 val;
struct btc_wl_role_info_bpos role;
};
struct btc_wl_scc_ctrl {
u8 null_role1;
u8 null_role2;
u8 ebt_null; /* if tx null at EBT slot */
u8 rsvd;
};
struct btc_wl_role_info { /* struct size must be n*4 bytes */
u8 connect_cnt;
u8 link_mode;
union btc_wl_role_info_map role_map;
struct btc_wl_active_role active_role[MAX_WIFI_ROLE_NUMBER];
u32 mrole_type; /* btc_wl_mrole_type */
u32 mrole_noa_duration; /* ms */
};
struct btc_statistic {
u8 rssi; /* 0%~110% (dBm = rssi -110) */
struct btc_traffic traffic;
};
struct btc_wl_stat_info {
u8 pid;
struct btc_statistic stat;
};
struct btc_wl_link_info {
struct btc_statistic stat;
enum rtw_traffic_dir dir;
struct rtw_chan_def chdef;
u8 mode; /* wl mode: 11b, 11g, 11n... */
u8 ch;
u8 bw;
u8 band; /* enum RF band: 2.4G/5G/6G */
u8 role; /*enum role_type */
u8 pid; /* MAC HW Port id: 0~4 */
u8 phy; /* PHY-0 or PHY-1*/
u8 dtim_period;
u8 busy;
u8 rssi_state[BTC_WL_RSSI_THMAX];
u8 mac_addr[6];
u8 tx_retry;
u16 mac_id; /* 0~63 */
u32 bcn_period;
u32 noa_duration; /* us */
u32 busy_t; /* busy start time */
u32 tx_time; /* the original max_tx_time */
u32 client_cnt; /* connected-client cnt for p2p-GO/soft-AP mode */
u32 rx_rate_drop_cnt;
u32 active: 1;
u32 noa: 1; /* Todo: for P2P */
u32 client_ps: 1; /* Todo: for soft-AP */
u32 connected: 2;
};
struct btc_wl_rfk_info {
u32 state: 2;
u32 path_map: 4;
u32 phy_map: 2;
u32 band: 2; /*0:2g, 1:5g, 2:6g */
u32 type: 8;
u32 rsvd: 14;
};
struct btc_wl_ver_info {
u32 fw_coex; /* match with which coex_ver */
u32 fw;
u32 mac;
u32 bb;
u32 rf;
};
struct btc_wl_afh_info {
u8 en;
u8 ch;
u8 bw;
u8 rsvd;
};
struct btc_ops {
void (*fw_cmd)(struct btc_t *btc, u8 h2c_class, u8 h2c_func,
u8 *param, u16 len);
void (*ntfy_power_on)(struct btc_t *btc);
void (*ntfy_power_off)(struct btc_t *btc);
void (*ntfy_init_coex)(struct btc_t *btc, u8 mode);
void (*ntfy_scan_start)(struct btc_t *btc, u8 band_idx, u8 band);
void (*ntfy_scan_finish)(struct btc_t *btc, u8 band_idx);
void (*ntfy_switch_band)(struct btc_t *btc, u8 band_idx, u8 band);
void (*ntfy_specific_packet)(struct btc_t *btc, u8 pkt_type);
void (*ntfy_role_info)(struct btc_t *btc, u8 rid,
struct btc_wl_link_info *info,
enum role_state reason);
void (*ntfy_radio_state)(struct btc_t *btc, u8 rf_state);
void (*ntfy_customerize)(struct btc_t *btc, u8 type, u16 len, u8 *buf);
u8 (*ntfy_wl_rfk)(struct btc_t *btc, u8 phy, u8 type, u8 state);
void (*ntfy_wl_sta)(struct btc_t *btc, u8 ntfy_num,
struct btc_wl_stat_info stat_info[], u8 reason);
void (*ntfy_fwinfo)(struct btc_t *btc, u8 *buf, u32 len, u8 cls,
u8 func);
void (*ntfy_timer)(struct btc_t *btc, u16 tmr_id);
};
struct btc_bt_smap {
u32 connect: 1;
u32 ble_connect: 1;
u32 acl_busy: 1;
u32 sco_busy: 1;
u32 mesh_busy: 1;
u32 inq_pag: 1;
};
union btc_bt_state_map {
u32 val;
struct btc_bt_smap map;
};
struct btc_bt_link_info {
struct btc_u8_sta_chg profile_cnt;
struct btc_bool_sta_chg multi_link;
struct btc_bool_sta_chg relink;
struct btc_bt_hfp_desc hfp_desc;
struct btc_bt_hid_desc hid_desc;
struct btc_bt_a2dp_desc a2dp_desc;
struct btc_bt_pan_desc pan_desc;
union btc_bt_state_map status;
u8 sut_pwr_level[BTC_PROFILE_MAX];
u8 golden_rx_shift[BTC_PROFILE_MAX];
u8 rssi_state[BTC_BT_RSSI_THMAX];
u8 afh_map[12];
u32 role_sw: 1;
u32 slave_role: 1;
u32 afh_update: 1;
u32 cqddr: 1;
u32 rssi: 8;
u32 tx_3M: 1;
u32 rsvd: 19;
};
struct btc_3rdcx_info {
u8 type; /* 0: none, 1:zigbee, 2:LTE */
u8 hw_coex;
u16 rsvd;
};
struct btc_rf_para {
u32 tx_pwr_freerun;
u32 rx_gain_freerun;
u32 tx_pwr_perpkt;
u32 rx_gain_perpkt;
};
struct btc_bt_info {
struct btc_bt_link_info link_info;
struct btc_bt_scan_info scan_info[BTC_SCAN_MAX1];
struct btc_bt_ver_info ver_info;
struct btc_bool_sta_chg enable;
struct btc_bool_sta_chg inq_pag;
struct btc_rf_para rf_para; /* for record */
union btc_bt_rfk_info_map rfk_info;
u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
u32 scbd; /* scoreboard value */
u32 feature;
u32 mbx_avl: 1; /* mailbox available */
u32 whql_test: 1;
u32 igno_wl: 1;
u32 reinit: 1;
u32 ble_scan_en: 1;
u32 btg_type: 1; /* BT located at BT only or BTG */
u32 inq: 1;
u32 pag: 1;
u32 run_patch_code: 1;
u32 hi_lna_rx: 1;
u32 scan_rx_low_pri: 1;
u32 rsvd: 21;
};
struct btc_wl_smap {
u32 busy: 1;
u32 scan: 1;
u32 connecting: 1;
u32 roaming: 1;
u32 _4way: 1;
u32 rf_off: 1;
u32 lps: 2; /* 1: LPS-Protocol + WL_power, 2:LPS_Protocol */
u32 ips: 1;
u32 init_ok: 1;
u32 traffic_dir : 2;
u32 rf_off_pre: 1;
u32 lps_pre: 2;
};
union btc_wl_state_map {
u32 val;
struct btc_wl_smap map;
};
struct btc_dm_emap {
u32 init: 1;
u32 pta_owner: 1;
u32 wl_rfk_timeout: 1;
u32 bt_rfk_timeout: 1;
u32 wl_fw_hang: 1;
u32 offload_mismatch: 1;
u32 cycle_hang: 1;
u32 w1_hang: 1;
u32 b1_hang: 1;
u32 tdma_no_sync: 1;
u32 wl_slot_drift: 1;
u32 bt_slot_drift: 1; /* for external slot control */
};
union btc_dm_error_map {
u32 val;
struct btc_dm_emap map;
};
struct btc_wl_info {
struct btc_wl_link_info link_info[MAX_WIFI_ROLE_NUMBER];
struct btc_wl_rfk_info rfk_info;
struct btc_wl_ver_info ver_info;
struct btc_wl_afh_info afh_info;
struct btc_wl_role_info role_info;
struct btc_wl_scan_info scan_info;
struct btc_wl_dbcc_info dbcc_info;
struct btc_bool_sta_chg cck_lock;
struct btc_rf_para rf_para; /* for record */
union btc_wl_state_map status;
struct btc_wl_nhm nhm;
u8 iot_peer;
u8 rssi_level;/* the overall-role rssi-level 0~4, "low_rssi->hi_level"*/
u8 bssid[6];
u8 pta_req_mac;
u8 bt_polut_type[2]; /* BT polluted WL-Tx type for phy0/1 */
u32 scbd;
};
struct btc_module {
struct btc_ant_info ant;
u8 rfe_type;
u8 kt_ver;
u8 bt_solo: 1;
u8 bt_pos: 1; /* wl-end view: get from efuse, must compare bt.btg_type */
u8 switch_type: 1; /* WL/BT switch type: 0: internal, 1: external */
u8 rsvd;
};
struct btc_init_info {
struct btc_module module;
u8 wl_guard_ch;
u8 wl_only: 1;
u8 wl_init_ok: 1;
u8 dbcc_en: 1;
u8 cx_other: 1;
u8 bt_only: 1;
u16 rsvd;
};
/* recird the last 20 reason/action */
struct btc_dm_step {
char step[BTC_DM_MAXSTEP][BTC_RSN_MAXLEN];
u32 cnt;
};
/* dynamic coex mechanism */
struct btc_dm {
struct fbtc_slot slot[CXST_MAX];
struct fbtc_slot slot_now[CXST_MAX];
struct fbtc_tdma tdma;
struct fbtc_tdma tdma_now;
struct btc_gnt_ctrl gnt[2];
struct btc_init_info init_info; /* pass to wl_fw if offload */
struct btc_rf_trx_para rf_trx_para;
struct btc_wl_tx_limit_para wl_tx_limit;
struct btc_wl_scc_ctrl wl_scc;
struct btc_dm_step dm_step;
union btc_dm_error_map error;
char run_reason[BTC_RSN_MAXLEN];
char run_action[BTC_ACT_MAXLEN];
u16 slot_dur[CXST_MAX]; /* for user-define slot duration */
u32 set_ant_path;
u32 cnt_dm[BTC_DCNT_MAX];
u32 cnt_notify[BTC_NCNT_MAX];
u32 wl_only: 1; /* drv->Fw if offload */
u32 wl_fw_cx_offload: 1; /* BTC_CX_FW_OFFLOAD from FW code */
u32 freerun: 1;
u32 wl_ps_ctrl: 2; /* 0: off, 1: force on, 2:forec off */
u32 wl_mimo_ps: 1;
u32 leak_ap: 1;
u32 noisy_level: 3;
u32 coex_info_map: 8;
u32 bt_only: 1; /* drv->Fw if offload */
u32 wl_btg_rx: 1; /* if wl rx shared with bt */
u32 trx_para_level: 8; /* trx parameter level */
u32 wl_stb_chg: 1; /* if change s1 WL standby mode table = Rx */
u32 rsvd: 3;
};
/* the wl/bt/zb cx instance */
struct btc_cx {
struct btc_wl_info wl;
struct btc_bt_info bt;
struct btc_3rdcx_info other;
struct btc_rf_trx_para rf_para;
u32 state_map; /* wl/bt combined state map */
u32 cnt_bt[BTC_BCNT_MAX];
u32 cnt_wl[BTC_WCNT_MAX];
};
struct btc_ctrl {
u32 manual: 1;
u32 igno_bt: 1;
u32 always_freerun: 1;
u32 rsvd: 29;
};
struct btc_dbg {
/* cmd "rb" */
bool rb_done;
u32 rb_val;
};
struct btc_tmr {
void *btc;
u16 id;
_os_timer tmr;
};
struct btc_t {
struct rtw_phl_com_t *phl;
struct rtw_hal_com_t *hal;
struct btc_ops *ops;
const struct btc_chip *chip;
struct btc_cx cx;
struct btc_dm dm;
struct btc_ctrl ctrl;
struct btc_module mdinfo;
struct btf_fwinfo fwinfo;
struct btc_dbg dbg;
/* btc timers */
bool tmr_init;
bool tmr_stop;
struct btc_tmr timer[BTC_TIMER_MAX];
_os_timer delay_tmr; /* a delayed timer to start periodic timer (wait phl started) */
char mbuf[BTC_MSG_MAXLEN]; /* msg buffer */
size_t mlen; /* max msg len */
u8 policy[BTC_POLICY_MAXLEN]; /* coex policy buffer */
u16 policy_len;
u16 policy_type;
u8 hubmsg[BTC_HUBMSG_MAXLEN]; /* phl hub msg */
u16 hubmsg_len;
u32 hubmsg_cnt;
u32 bt_req_len; /* request bt-slot in WL SCC/MCC +BT coex */
bool bt_req_en;
};
static void _send_fw_cmd(struct btc_t *btc, u8 h2c_class, u8 h2c_func,
u8 *param, u16 len);
static void _ntfy_power_on(struct btc_t *btc);
static void _ntfy_power_off(struct btc_t *btc);
static void _ntfy_init_coex(struct btc_t *btc, u8 mode);
static void _ntfy_scan_start(struct btc_t *btc, u8 phy_idx, u8 band);
static void _ntfy_scan_finish(struct btc_t *btc, u8 pyh_idx);
static void _ntfy_switch_band(struct btc_t *btc, u8 phy_idx, u8 band);
static void _ntfy_specific_packet(struct btc_t *btc, u8 pkt_type);
static void _ntfy_role_info(struct btc_t *btc, u8 rid,
struct btc_wl_link_info *info,
enum role_state reason);
static void _ntfy_radio_state(struct btc_t *btc, u8 rf_state);
static void _ntfy_customerize(struct btc_t *btc, u8 type, u16 len, u8 *buf);
static u8 _ntfy_wl_rfk(struct btc_t *btc, u8 phy_path, u8 type, u8 state);
static void _ntfy_wl_sta(struct btc_t *btc, u8 ntfy_num,
struct btc_wl_stat_info stat_info[], u8 reason);
static void _ntfy_fwinfo(struct btc_t *btc, u8 *buf, u32 len, u8 cls, u8 func);
static void _ntfy_timer(struct btc_t *btc, u16 tmr_id);
#ifdef BTC_8852A_SUPPORT
extern const struct btc_chip chip_8852a;
#endif
#ifdef BTC_8852B_SUPPORT
extern const struct btc_chip chip_8852b;
#endif
#ifdef BTC_8852C_SUPPORT
extern const struct btc_chip chip_8852c;
#endif
extern const u32 coex_ver;
void _update_bt_scbd(struct btc_t *btc, bool only_update);
bool hal_btc_init(struct btc_t *btc);
void hal_btc_deinit(struct btc_t *btc);
u32 _read_cx_reg(struct btc_t *btc, u32 offset);
u8 _read_cx_ctrl(struct btc_t *btc);
void _write_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr, u32 val);
void _read_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr);
u32 _read_scbd(struct btc_t *btc);
void _write_scbd(struct btc_t *btc, u32 val, bool state);
void _run_coex(struct btc_t *btc, const char *reason);
void _set_init_info(struct btc_t *btc);
void _set_bt_psd_report(struct btc_t *btc, u8 start_idx, u8 rpt_type);
void _update_dm_step(struct btc_t *btc, const char *strin);
void hal_btc_send_event(struct btc_t *btc, u8 *buf, u32 len, u16 ev_id);
u8 _get_wl_role_idx(struct btc_t *btc, u8 role);
#endif /*_HAL_BTC_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/hal_btc.h
|
C
|
agpl-3.0
| 29,941
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_BTC_ACTION_C_
#include "../hal_headers_le.h"
#include "hal_btc.h"
#include "halbtc_fw.h"
#include "halbtc_fwdef.h"
#include "halbtc_action.h"
#include "halbtc_def.h"
#ifdef CONFIG_BTCOEX
#define _set_cx_ctrl(btc, val) rtw_hal_mac_set_coex_ctrl(btc->hal, val)
/* tdma policy template */
struct fbtc_tdma t_def[] = {
{ CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /*CXTD_OFF*/
{ CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 1, 0, 0}, /*CXTD_B2*/
{ CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 2, 0, 0}, /*CXTD_OFF_EXT*/
{ CXTDMA_FIX, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /* CXTD_FIX */
{ CXTDMA_FIX, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, /* CXTD_PFIX */
{ CXTDMA_AUTO, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /* CXTD_AUTO */
{ CXTDMA_AUTO, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, /* CXTD_PAUTO */
{CXTDMA_AUTO2, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, /* CXTD_AUTO2 */
{CXTDMA_AUTO2, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0} /* CXTD_PAUTO2 */
};
/* slot policy template */
struct fbtc_slot s_def[] = {
{100, 0x55555555, SLOT_MIX}, /* CXST_OFF */
{ 5, 0xea5a5a5a, SLOT_ISO}, /* CXST_B2W */
{ 70, 0xea5a5a5a, SLOT_ISO}, /* CXST_W1 */
{ 15, 0xea5a5a5a, SLOT_ISO}, /* CXST_W2 */
{ 15, 0xea5a5a5a, SLOT_ISO}, /* CXST_W2B */
{250, 0xe5555555, SLOT_MIX}, /* CXST_B1 */
{ 7, 0xea5a5a5a, SLOT_MIX}, /* CXST_B2 */
{ 5, 0xe5555555, SLOT_MIX}, /* CXST_B3 */
{ 50, 0xe5555555, SLOT_MIX}, /* CXST_B4 */
{ 20, 0xea5a5a5a, SLOT_ISO}, /* CXST_LK */
{400, 0x55555555, SLOT_MIX}, /* CXST_BLK */
{ 0, 0xea5a5a5a, SLOT_MIX}, /* CXST_E2G */
{ 0, 0xffffffff, SLOT_MIX}, /* CXST_E5G */
{ 0, 0xe5555555, SLOT_MIX}, /* CXST_EBT */
{ 0, 0xaaaaaaaa, SLOT_ISO}, /* CXST_ENULL */
{250, 0xea5a5a5a, SLOT_MIX}, /* CXST_WLK */
{ 35, 0xfafafafa, SLOT_ISO}, /* CXST_W1FDD */
{250, 0xffffffff, SLOT_MIX} /* CXST_B1FDD */
};
const u32 cxtbl[] = {
0xffffffff, /* 0 */
0xaaaaaaaa, /* 1 */
0xe5555555, /* 2 */
0xee555555, /* 3 */
0xd5555555, /* 4 */
0x5a5a5a5a, /* 5 */
0x5a5a5aaa, /* 6 */
0xda5a5a5a, /* 7 */
0xea5a5a5a, /* 8 */
0x6a5a5aaa, /* 9 */
0x6a5a6a5a, /* 10 */
0x6a5a6aaa, /* 11 */
0x6afa5afa, /* 12 */
0xaaaa5aaa, /* 13 */
0xaaffffaa, /* 14 */
0xaa5555aa, /* 15 */
0xfafafafa, /* 16 */
0xffffddff, /* 17 */
0xdaffdaff, /* 18 */
0xfafadafa /* 19 */
};
void _set_bt_ignore_wlan_act(struct btc_t *btc, u8 enable)
{
u8 buf = 0;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): set bt %s wlan_act\n",
__func__, (enable? "ignore" : "do not ignore"));
buf = enable;
hal_btc_fw_set_bt(btc, SET_BT_IGNORE_WLAN_ACT, 1, &buf);
}
void _set_wl_tx_power(struct btc_t *btc, u32 level)
{
struct btc_wl_info *wl = &btc->cx.wl;
if (wl->rf_para.tx_pwr_freerun == level)
return;
wl->rf_para.tx_pwr_freerun = level;
btc->dm.rf_trx_para.wl_tx_power = level;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n",
__func__, level);
btc->chip->ops->wl_tx_power(btc, level);
}
void _set_wl_rx_gain(struct btc_t *btc, u32 level)
{
struct btc_wl_info *wl = &btc->cx.wl;
if (wl->rf_para.rx_gain_freerun == level)
return;
wl->rf_para.rx_gain_freerun = level;
btc->dm.rf_trx_para.wl_rx_gain = level;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n",
__func__, level);
btc->chip->ops->wl_rx_gain(btc, level);
}
void _set_bt_tx_power(struct btc_t *btc, u32 level)
{
struct btc_bt_info *bt = &btc->cx.bt;
u8 buf = 0;
if (bt->rf_para.tx_pwr_freerun == level)
return;
bt->rf_para.tx_pwr_freerun = level;
btc->dm.rf_trx_para.bt_tx_power = level;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n",
__func__, level);
buf = (0x100 - level) & bMASKB0;
hal_btc_fw_set_bt(btc, SET_BT_TX_PWR, 1, &buf);
}
void _set_bt_rx_gain(struct btc_t *btc, u32 level)
{
struct btc_bt_info *bt = &btc->cx.bt;
u8 buf = 0;
if (bt->rf_para.rx_gain_freerun == level ||
level > BTC_BT_RX_NORMAL_LVL)
return;
bt->rf_para.rx_gain_freerun = level;
btc->dm.rf_trx_para.bt_rx_gain = level;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): level = %d\n",
__func__, level);
buf = level & bMASKB0;
if (buf == BTC_BT_RX_NORMAL_LVL)
_write_scbd(btc, BTC_WSCB_RXGAIN, false);
else
_write_scbd(btc, BTC_WSCB_RXGAIN, true);
hal_btc_fw_set_bt(btc, SET_BT_LNA_CONSTRAIN, 1, &buf);
}
static void _set_rf_trx_para(struct btc_t *btc)
{
struct btc_dm *dm = &btc->dm;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_bt_link_info *b = &bt->link_info;
struct btc_rf_trx_para para;
u8 level_id = 0;
u32 wl_stb_chg = 0;
if (!dm->freerun) {
dm->trx_para_level = 0;
#if 1
/* fix LNA2 = level-5 for BT ACI issue at BTG */
if (btc->hal->chip_id == CHIP_WIFI6_8852A &&
btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
dm->trx_para_level = 1;
#endif
}
level_id = (u8)dm->trx_para_level;
if (level_id >= btc->chip->rf_para_dlink_num ||
level_id >= btc->chip->rf_para_ulink_num) {
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): invalid level_id: %d\n",
__func__, level_id);
return;
}
if (wl->status.map.traffic_dir & BIT(TRAFFIC_UL))
para = btc->chip->rf_para_ulink[level_id];
else
para = btc->chip->rf_para_dlink[level_id];
_set_wl_tx_power(btc, para.wl_tx_power);
_set_wl_rx_gain(btc, para.wl_rx_gain);
_set_bt_tx_power(btc, para.bt_tx_power);
_set_bt_rx_gain(btc, para.bt_rx_gain);
if (bt->enable.now == 0 || wl->status.map.rf_off == 1 ||
wl->status.map.lps)
wl_stb_chg = 0;
else
wl_stb_chg = 1;
if (wl_stb_chg != dm->wl_stb_chg) {
dm->wl_stb_chg = wl_stb_chg;
btc->chip->ops->wl_s1_standby(btc, dm->wl_stb_chg);
}
}
void _update_btc_state_map(struct btc_t *btc)
{
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_info *bt = &cx->bt;
struct btc_bt_link_info *bt_linfo = &bt->link_info;
if (wl->status.map.connecting || wl->status.map._4way ||
wl->status.map.roaming) {
cx->state_map = BTC_WLINKING;
} else if (wl->status.map.scan) { /* wl scan */
if (bt_linfo->status.map.inq_pag)
cx->state_map = BTC_WSCAN_BSCAN;
else
cx->state_map = BTC_WSCAN_BNOSCAN;
} else if (wl->status.map.busy) { /* only busy */
if (bt_linfo->status.map.inq_pag)
cx->state_map = BTC_WBUSY_BSCAN;
else
cx->state_map = BTC_WBUSY_BNOSCAN;
} else { /* wl idle */
cx->state_map = BTC_WIDLE;
}
}
static void _set_bt_golden_rx_range(struct btc_t *btc, u8 p_id, u8 level)
{
struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info;
u8 buf[2] = {0}, pos = 0, i;
if (p_id > BTC_BT_PAN)
return;
for (i = 0; i< BTC_PROFILE_MAX; i++) {
if ((p_id >> i) & 0x1) {
pos = i;
break;
}
}
if (bt_linfo->golden_rx_shift[pos] == level)
return;
bt_linfo->golden_rx_shift[pos] = level;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): p_id=%d, level=%d\n",
__func__, p_id, level);
buf[0] = level;
buf[1] = pos;
hal_btc_fw_set_bt(btc, SET_BT_GOLDEN_RX_RANGE, sizeof(buf), buf);
}
static void _set_bt_afh_info(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_bt_link_info *b = &bt->link_info;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
/*struct btc_module *module = &btc->mdinfo;*/
u8 en = 0, i, ch = 0, bw = CHANNEL_WIDTH_MAX;
u8 max_role_cnt = BTC_TDMA_WLROLE_MAX;
if (btc->ctrl.manual || wl->status.map.scan)
return;
if (btc->hal->dbcc_en)
max_role_cnt++;
/* TBD if include module->ant.type == BTC_ANT_SHARED */
if (wl->status.map.rf_off || bt->whql_test ||
wl_rinfo->link_mode == BTC_WLINK_NOLINK ||
wl_rinfo->link_mode == BTC_WLINK_5G ||
wl_rinfo->connect_cnt > max_role_cnt) {
en = false;
ch = 0;
bw = 0;
goto exit;
} else {
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) {
/* get p2p channel for MCC */
if (wl_rinfo->link_mode == BTC_WLINK_2G_MCC) {
if (wl_rinfo->active_role[i].role == PHL_RTYPE_AP ||
wl_rinfo->active_role[i].role == PHL_RTYPE_P2P_GO ||
wl_rinfo->active_role[i].role == PHL_RTYPE_P2P_GC) {
en = true;
ch = wl_rinfo->active_role[i].ch;
bw = wl_rinfo->active_role[i].bw;
break;
}
} else if (wl_rinfo->active_role[i].connected &&
wl_rinfo->active_role[i].band == BAND_ON_24G) {
en = true;
ch = wl_rinfo->active_role[i].ch;
bw = wl_rinfo->active_role[i].bw;
/* get the max bw if scc */
if (wl_rinfo->link_mode != BTC_WLINK_2G_SCC ||
wl_rinfo->active_role[i].bw == CHANNEL_WIDTH_40) {
break;
}
}
}
}
if (!en || ch > 14 || ch == 0)
bw = CHANNEL_WIDTH_MAX;
/* default AFH channel sapn = center-ch +- 6MHz */
switch (bw) {
case CHANNEL_WIDTH_20:
if (btc->dm.freerun)
bw = 48;
else
bw = 20 + btc->chip->afh_guard_ch * 2;
break;
case CHANNEL_WIDTH_40:
bw = 40 + btc->chip->afh_guard_ch * 2;
break;
case CHANNEL_WIDTH_5:
bw = 5 + btc->chip->afh_guard_ch * 2;
break;
case CHANNEL_WIDTH_10:
bw = 10 + btc->chip->afh_guard_ch * 2;
break;
default:
case CHANNEL_WIDTH_MAX:
en = false; /* turn off AFH info if invalid BW */
bw = 0;
ch = 0;
break;
}
exit:
if (wl->afh_info.en == en &&
wl->afh_info.ch == ch &&
wl->afh_info.bw == bw &&
b->profile_cnt.last == b->profile_cnt.now)
return;
wl->afh_info.en = en;
wl->afh_info.ch = ch;
wl->afh_info.bw = bw;
hal_btc_fw_set_bt(btc, SET_BT_WL_CH_INFO, 3, (u8*)&wl->afh_info);
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): en=%d, ch=%d, bw=%d\n",
__func__, en, ch, bw);
btc->cx.cnt_wl[BTC_WCNT_CH_UPDATE]++;
}
static void _set_halbb_btg_ctrl(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info;
bool is_btg = false;
if (btc->ctrl.manual)
return;
/* notify halbb ignore GNT_BT or not for WL BB Rx-AGC control */
if (wl_rinfo->link_mode == BTC_WLINK_5G) /* always 0 if 5G */
is_btg = false;
else if (btc->dm.freerun)
is_btg = false;
else if (wl_rinfo->link_mode == BTC_WLINK_25G_DBCC &&
wl_dinfo->real_band[1] != BAND_ON_24G)
is_btg = false;
else
is_btg = true;
if (!run_rsn("_ntfy_init_coex") && is_btg == btc->dm.wl_btg_rx)
return;
btc->dm.wl_btg_rx = is_btg;
/* rtw_hal_bb_ctrl_btg control the following:
* if btc->dm.wl_btg_rx = false (gnt_wl always = 1)
* Lte_rx: 0x10980[17]=1, 0x10980[29]=0
* Gnt_wl: 0x10980[18]=1, 0x10980[28]=1
* Gnt_bt_tx: 0x10980[19]=1, 0x10980[27]=0
* Gnt_bt: 0x10980[20]=1, 0x10980[26]=0
* if if btc->dm.wl_btg_rx = true (gnt from MAC)
* Lte_rx: 0x10980[17]=0, 0x10980[29]=0
* Gnt_wl: 0x10980[18]=0, 0x10980[28]=1
* Gnt_bt_tx: 0x10980[19]=0, 0x10980[27]=0
* Gnt_bt: 0x10980[20]=0, 0x10980[26]=0
*/
/* skip if MCC dual_band, call ctrl_btg8852a() in WL FW by slot */
if (wl_rinfo->link_mode == BTC_WLINK_25G_MCC)
return;
rtw_hal_bb_ctrl_btg(btc->hal, is_btg);
}
static void _set_bt_slot_req(struct btc_t *btc)
{
struct btc_bt_link_info *b = &btc->cx.bt.link_info;
u8 len = 0;
/* don't change bt slot req state during RFK for p2p/mcc case*/
if (!run_rsn("_ntfy_wl_rfk") &&
btc->cx.wl.rfk_info.state == BTC_WRFK_STOP)
btc->bt_req_en = false;
/* enable bt-slot req if ext-slot-control */
if (btc->dm.tdma_now.type == CXTDMA_OFF &&
btc->dm.tdma_now.ext_ctrl == CXECTL_EXT)
btc->bt_req_en = true;
if (!btc->bt_req_en) {
len = 0;
} else {
if (b->a2dp_desc.exist || b->a2dp_desc.active ||
(b->profile_cnt.now == 1 &&
b->hid_desc.pair_cnt == 1 &&
b->multi_link.now)) /*a2dp, hid + acl-idle */ {
if (b->profile_cnt.now >= 2)
len = BTC_BSLOT_A2DP_HID;
else
len = BTC_BSLOT_A2DP;
} else if (b->pan_desc.exist || b->status.map.inq_pag) {
len = BTC_BSLOT_INQ;
} else {
len = BTC_BSLOT_IDLE;
}
}
if (len == btc->bt_req_len)
return;
btc->bt_req_len = len;
hal_btc_send_event(btc, (u8*)&btc->bt_req_len, 4, BTC_HMSG_SET_BT_REQ_SLOT);
PHL_INFO("[BTC], %s(): bt_req_len=%d\n", __func__, btc->bt_req_len);
}
static void _set_bt_rx_agc(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
struct btc_bt_info *bt = &btc->cx.bt;
bool bt_hi_lna_rx = false;
if (wl_rinfo->link_mode != BTC_WLINK_NOLINK && btc->dm.wl_btg_rx)
bt_hi_lna_rx = true;
if (bt_hi_lna_rx == bt->hi_lna_rx)
return;
/* true: bt use Hi-LNA rx gain table (f/e/3/2) in -3x~-9xdBm for co-rx
* false: bt use original rx gain table (f/b/7/3/2)
*/
_write_scbd(btc, BTC_WSCB_BT_HILNA, bt_hi_lna_rx);
}
static void _set_bt_rx_scan_pri(struct btc_t *btc)
{
struct btc_bt_info *bt = &btc->cx.bt;
_write_scbd(btc, BTC_WSCB_RXSCAN_PRI, (bool)(!!bt->scan_rx_low_pri));
}
static void _set_halmac_tx_limit(struct btc_t *btc)
{
struct btc_cx *cx = &btc->cx;
struct btc_dm *dm = &btc->dm;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_info *bt = &cx->bt;
struct btc_bt_link_info *b = &bt->link_info;
struct btc_bt_hfp_desc *hfp = &b->hfp_desc;
struct btc_bt_hid_desc *hid = &b->hid_desc;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
struct btc_wl_link_info *plink = NULL;
u8 mode = wl_rinfo->link_mode, i;
u8 tx_retry = 0;
u32 tx_time = 0;
u16 enable = 0;
bool reenable = false;
if (btc->ctrl.manual)
return;
if (btc->dm.freerun || btc->ctrl.igno_bt || b->profile_cnt.now == 0 ||
mode == BTC_WLINK_5G || mode == BTC_WLINK_NOLINK) {
enable = 0;
tx_time = BTC_MAX_TX_TIME_DEF;
tx_retry = BTC_MAX_TX_RETRY_DEF;
} else if ((hfp->exist && hid->exist) || hid->pair_cnt > 1) {
enable = 1;
tx_time = BTC_MAX_TX_TIME_L2;
tx_retry = BTC_MAX_TX_RETRY_L1;
} else if (hfp->exist || hid->exist) {
enable = 1;
tx_time = BTC_MAX_TX_TIME_L3;
tx_retry = BTC_MAX_TX_RETRY_L1;
} else {
enable = 0;
tx_time = BTC_MAX_TX_TIME_DEF;
tx_retry = BTC_MAX_TX_RETRY_DEF;
}
if (dm->wl_tx_limit.enable == enable &&
dm->wl_tx_limit.tx_time == tx_time &&
dm->wl_tx_limit.tx_retry == tx_retry)
return;
if (!dm->wl_tx_limit.enable && enable)
reenable = true;
dm->wl_tx_limit.enable = enable;
dm->wl_tx_limit.tx_time = tx_time;
dm->wl_tx_limit.tx_retry = tx_retry;
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) {
plink = &wl->link_info[i];
if (!plink->connected)
continue;
/* backup the original tx time before tx-limit on */
if (reenable) {
rtw_hal_mac_get_tx_time(btc->hal,
(u8)plink->mac_id,
&plink->tx_time);
rtw_hal_mac_get_tx_retry_limit(btc->hal,
(u8)plink->mac_id,
&plink->tx_retry);
}
/* restore the original tx time if no tx-limit */
if (!enable) {
rtw_hal_mac_set_tx_time(btc->hal, 1, 1,
(u8)plink->mac_id,
plink->tx_time);
rtw_hal_mac_set_tx_retry_limit(btc->hal, 1, 1,
(u8)plink->mac_id,
plink->tx_retry);
} else {
rtw_hal_mac_set_tx_time(btc->hal, 1, 0,
(u8)plink->mac_id, tx_time);
rtw_hal_mac_set_tx_retry_limit(btc->hal, 1, 0,
(u8)plink->mac_id,
tx_retry);
}
}
}
static bool _check_freerun(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
struct btc_bt_link_info *bt_linfo = &bt->link_info;
struct btc_bt_hid_desc *hid = &bt_linfo->hid_desc;
u8 max_role_cnt = BTC_TDMA_WLROLE_MAX;
if (btc->hal->dbcc_en)
max_role_cnt++;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) {
btc->dm.trx_para_level = 0;
return false;
}
/* The below is dedicated antenna case */
if (wl_rinfo->connect_cnt > max_role_cnt) {
btc->dm.trx_para_level = 5;
return true;
}
if (bt_linfo->profile_cnt.now == 0) {
btc->dm.trx_para_level = 5;
return true;
}
if (hid->pair_cnt > BTC_TDMA_BTHID_MAX) {
btc->dm.trx_para_level = 5;
return true;
}
/* Todo: get isolation by BT psd */
if (btc->mdinfo.ant.isolation >= BTC_FREERUN_ANTISO_MIN) {
btc->dm.trx_para_level = 5;
return true;
}
if (!wl->status.map.busy) {/* wl idle -> freerun */
btc->dm.trx_para_level = 5;
return true;
} else if (wl->rssi_level > 1) {/* WL rssi < 50% (-60dBm) */
btc->dm.trx_para_level = 0;
return false;
} else if (wl->status.map.traffic_dir & BIT(TRAFFIC_UL)) { /* uplink */
if (wl->rssi_level == 0 && bt_linfo->rssi > 31) {
btc->dm.trx_para_level = 6;
return true;
} else if (wl->rssi_level == 1 && bt_linfo->rssi > 36) {
btc->dm.trx_para_level = 7;
return true;
} else {
btc->dm.trx_para_level = 0;
return false;
}
} else if (wl->status.map.traffic_dir & BIT(TRAFFIC_DL)) { /*downlink*/
if (bt_linfo->rssi > 28) {
btc->dm.trx_para_level = 6;
return true;
}
}
btc->dm.trx_para_level = 0;
return false;
}
static void _set_policy(struct btc_t *btc, u16 policy_type, const char* action)
{
struct btc_dm *dm = &btc->dm;
struct fbtc_tdma *t = &dm->tdma;
struct fbtc_slot *s = dm->slot;
struct btc_wl_role_info *wl_rinfo = &btc->cx.wl.role_info;
struct btc_bt_hid_desc *hid = &btc->cx.bt.link_info.hid_desc;
u8 type, null_role = 0;
u16 dur = 0;
u32 tbl_w1, tbl_b1, tbl_b4;
bool mode = NM_EXEC;
type = (u8)((policy_type & bMASKB1) >> 8);
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) {
if (btc->cx.wl.status.map._4way)
tbl_w1 = cxtbl[1];
else if (hid->exist && hid->type == BTC_HID_218)
tbl_w1 = cxtbl[7]; /* Ack/BA no break bt Hi-Pri-rx */
else
tbl_w1 = cxtbl[8];
if (dm->leak_ap &&
(type == BTC_CXP_PFIX || type == BTC_CXP_PAUTO2)) {
tbl_b1 = cxtbl[3];
tbl_b4 = cxtbl[3];
} else if (hid->exist && hid->type == BTC_HID_218) {
tbl_b1 = cxtbl[4]; /* Ack/BA no break bt Hi-Pri-rx */
tbl_b4 = cxtbl[4];
} else {
tbl_b1 = cxtbl[2];
tbl_b4 = cxtbl[2];
}
} else {
tbl_w1 = cxtbl[16]; /* 19 for HID exist */
tbl_b1 = cxtbl[17];
tbl_b4 = cxtbl[17];
}
switch(type) {
case BTC_CXP_USERDEF0:
mode = FC_EXEC;
_tdma_cpy(t, &t_def[CXTD_OFF]);
_slot_cpy(&s[CXST_OFF], &s_def[CXST_OFF]);
_slot_set_tbl(CXST_OFF, cxtbl[2]);
break;
case BTC_CXP_OFF: /* TDMA off */
_write_scbd(btc, BTC_WSCB_TDMA, false);
_tdma_cpy(t, &t_def[CXTD_OFF]);
_slot_cpy(&s[CXST_OFF], &s_def[CXST_OFF]);
switch (policy_type) {
case BTC_CXP_OFF_BT:
_slot_set_tbl(CXST_OFF, cxtbl[2]);
break;
case BTC_CXP_OFF_WL:
_slot_set_tbl(CXST_OFF, cxtbl[1]);
break;
case BTC_CXP_OFF_EQ0:
_slot_set_tbl(CXST_OFF, cxtbl[0]);
break;
case BTC_CXP_OFF_EQ1:
_slot_set_tbl(CXST_OFF, cxtbl[16]);
break;
case BTC_CXP_OFF_EQ2:
_slot_set_tbl(CXST_OFF, cxtbl[17]);
break;
case BTC_CXP_OFF_EQ3:
_slot_set_tbl(CXST_OFF, cxtbl[18]);
break;
case BTC_CXP_OFF_BWB0:
_slot_set_tbl(CXST_OFF, cxtbl[5]);
break;
case BTC_CXP_OFF_BWB1:
_slot_set_tbl(CXST_OFF, cxtbl[8]);
break;
case BTC_CXP_OFF_BWB2:
_slot_set_tbl(CXST_OFF, cxtbl[7]);
break;
}
break;
case BTC_CXP_OFFB: /* TDMA off + beacon protect */
_write_scbd(btc, BTC_WSCB_TDMA, false);
_tdma_cpy(t, &t_def[CXTD_OFF_B2]);
_slot_cpy(&s[CXST_OFF], &s_def[CXST_OFF]);
switch (policy_type) {
case BTC_CXP_OFFB_BWB0:
_slot_set_tbl(CXST_OFF, cxtbl[8]);
break;
}
break;
case BTC_CXP_OFFE: /* TDMA off + beacon protect + Ext_control */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_OFF_EXT]);
if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC &&
dm->wl_scc.ebt_null) {
_tdma_set_rxflctrl(1);
_tdma_set_txflctrl(1);
if ((wl_rinfo->mrole_noa_duration > 0) &&
(wl_rinfo->mrole_noa_duration +
2 * BTC_NULL1_EBT_EARLY_T < BTC_SCC_CYCLE))
dur = BTC_SCC_CYCLE - BTC_NULL1_EBT_EARLY_T -
wl_rinfo->mrole_noa_duration;
}
switch (policy_type) {
case BTC_CXP_OFFE_2GBWISOB: /* for normal-case */
_slot_set(CXST_E2G, dur, tbl_w1, SLOT_ISO);
_slot_cpy(&s[CXST_EBT], &s_def[CXST_EBT]);
break;
case BTC_CXP_OFFE_2GISOB: /* for bt no-link */
_slot_set(CXST_E2G, dur, cxtbl[1], SLOT_ISO);
_slot_cpy(&s[CXST_EBT], &s_def[CXST_EBT]);
break;
case BTC_CXP_OFFE_2GBWMIXB: /* for GC-only NOA < bt_slot_req */
_slot_set(CXST_E2G, dur, tbl_w1, SLOT_MIX);
_slot_cpy(&s[CXST_EBT], &s_def[CXST_EBT]);
break;
case BTC_CXP_OFFE_2GBWMIXB2: /* for GC+STA NOA < bt_slot_req */
_slot_set(CXST_E2G, dur, tbl_w1, SLOT_MIX);
_slot_set(CXST_EBT, BTC_BSLOT_A2DP_HID,
cxtbl[2], SLOT_MIX);
break;
case BTC_CXP_OFFE_WL: /*for 4-way */
_slot_set(CXST_E2G, dur, cxtbl[1], SLOT_MIX);
_slot_set(CXST_EBT, 0, cxtbl[1], SLOT_MIX);
break;
}
_slot_cpy(&s[CXST_E5G], &s_def[CXST_E5G]);
_slot_cpy(&s[CXST_ENULL], &s_def[CXST_ENULL]);
break;
case BTC_CXP_FIX: /* TDMA Fix-Slot */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_FIX]);
switch (policy_type) {
case BTC_CXP_FIX_TD3030: /* W1:B1 = 30:30 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD5050: /* W1:B1 = 50:50 */
_slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 50, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD2030: /* W1:B1 = 20:30 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD4010: /* W1:B1 = 40:10 */
_slot_set(CXST_W1, 40, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 10, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD4010ISO: /* W1:B1 = 40:10 for WL busy/scan */
_slot_set(CXST_W1, 40, cxtbl[1], SLOT_ISO);
_slot_set(CXST_B1, 10, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD7010: /* W1:B1 = 70:10 */
_slot_set(CXST_W1, 70, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 10, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD2060: /* W1:B1 = 20:60 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD3060: /* W1:B1 = 30:60 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TD2080: /* W1:B1 = 20:80 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 80, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_FIX_TDW1B1: /* W1:B1 = user-define */
_slot_set(CXST_W1, dm->slot_dur[CXST_W1],
tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, dm->slot_dur[CXST_B1],
tbl_b1, SLOT_MIX);
break;
}
break;
case BTC_CXP_PFIX: /* PS-TDMA Fix-Slot */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_PFIX]);
switch (policy_type) {
case BTC_CXP_PFIX_TD3030: /* W1:B1 = 30:30 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PFIX_TD5050: /* W1:B1 = 50:50 */
_slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 50, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PFIX_TD2030: /* W1:B1 = 20:30 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 30, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PFIX_TD2060: /* W1:B1 = 20:60 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PFIX_TD3070: /* W1:B1 = 30:60 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 60, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PFIX_TD2080: /* W1:B1 = 20:80 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, 80, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PFIX_TDW1B1: /* W1:B1 = user-define */
_slot_set(CXST_W1, dm->slot_dur[CXST_W1],
tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, dm->slot_dur[CXST_B1],
tbl_b1, SLOT_MIX);
break;
}
break;
case BTC_CXP_AUTO: /* TDMA Auto-Slot */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_AUTO]);
switch (policy_type) {
case BTC_CXP_AUTO_TD50B1: /* W1:B1 = 50:BTC_B1_MAX */
_slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_AUTO_TD60B1: /* W1:B1 = 60:BTC_B1_MAX */
_slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_AUTO_TD20B1: /* W1:B1 = 20:BTC_B1_MAX */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_AUTO_TDW1B1: /* W1:B1 = user-define */
_slot_set(CXST_W1, dm->slot_dur[CXST_W1],
tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, dm->slot_dur[CXST_B1],
tbl_b1, SLOT_MIX);
break;
}
break;
case BTC_CXP_PAUTO: /* PS-TDMA Auto-Slot */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_PAUTO]);
switch (policy_type) {
case BTC_CXP_PAUTO_TD50B1: /* W1:B1 = 50:BTC_B1_MAX */
_slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PAUTO_TD60B1: /* W1:B1 = 60:BTC_B1_MAX */
_slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PAUTO_TD20B1: /* W1:B1 = 20:BTC_B1_MAX */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
break;
case BTC_CXP_PAUTO_TDW1B1: /* W1:B1 = user-define */
_slot_set(CXST_W1, dm->slot_dur[CXST_W1],
tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, dm->slot_dur[CXST_B1],
tbl_b1, SLOT_MIX);
break;
}
break;
case BTC_CXP_AUTO2: /* TDMA Auto-Slot2 */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_AUTO2]);
switch (policy_type) {
case BTC_CXP_AUTO2_TD3050: /* W1:B4 = 30:50 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_AUTO2_TD3070: /* W1:B4 = 30:70 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 70, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_AUTO2_TD5050: /* W1:B4 = 50:50 */
_slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_AUTO2_TD6060: /* W1:B4 = 60:60 */
_slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 60, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_AUTO2_TD2080: /* W1:B4 = 20:80 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 80, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_AUTO2_TDW1B4: /* W1:B1 = user-define */
_slot_set(CXST_W1, dm->slot_dur[CXST_W1],
tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, dm->slot_dur[CXST_B1],
tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, dm->slot_dur[CXST_B4],
tbl_b4, SLOT_MIX);
break;
}
break;
case BTC_CXP_PAUTO2: /* PS-TDMA Auto-Slot2 */
_write_scbd(btc, BTC_WSCB_TDMA, true);
_tdma_cpy(t, &t_def[CXTD_PAUTO2]);
switch (policy_type) {
case BTC_CXP_PAUTO2_TD3050: /* W1:B4 = 30:50 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_PAUTO2_TD3070: /* W1:B4 = 30:70 */
_slot_set(CXST_W1, 30, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, cxtbl[3], SLOT_MIX);
_slot_set(CXST_B4, 70, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_PAUTO2_TD5050: /* W1:B4 = 50:50 */
_slot_set(CXST_W1, 50, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 50, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_PAUTO2_TD6060: /* W1:B4 = 60:60 */
_slot_set(CXST_W1, 60, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 60, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_PAUTO2_TD2080: /* W1:B4 = 20:80 */
_slot_set(CXST_W1, 20, tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, 80, tbl_b4, SLOT_MIX);
break;
case BTC_CXP_PAUTO2_TDW1B4: /* W1:B1 = user-define */
_slot_set(CXST_W1, dm->slot_dur[CXST_W1],
tbl_w1, SLOT_ISO);
_slot_set(CXST_B1, dm->slot_dur[CXST_B1],
tbl_b1, SLOT_MIX);
_slot_set(CXST_B4, dm->slot_dur[CXST_B4],
tbl_b4, SLOT_MIX);
break;
}
break;
}
if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC && dm->tdma.rxflctrl) {
null_role = (dm->wl_scc.null_role1 & 0xf) +
((dm->wl_scc.null_role2 & 0xf) << 4);
_tdma_set_flctrl_role(null_role);
}
/* enter leak_slot after each null-1 */
if (dm->leak_ap && dm->tdma.leak_n > 1)
_tdma_set_lek(1);
if (run_rsn("_cmd_set_coex"))
mode = FC_EXEC;
_update_poicy(btc, mode, policy_type, action);
}
void _set_gnt_wl(struct btc_t *btc, u8 phy_map, u8 state)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_dm *dm = &btc->dm;
struct btc_gnt_ctrl *g = dm->gnt;
u8 i;
if (phy_map > BTC_PHY_ALL)
return;
for (i = 0; i < BTC_PHY_MAX; i++) {
if (!(phy_map & BIT(i)))
continue;
switch (state) {
case BTC_GNT_HW:
g[i].gnt_wl_sw_en = 0;
g[i].gnt_wl = 0;
break;
case BTC_GNT_SW_LO:
g[i].gnt_wl_sw_en = 1;
g[i].gnt_wl = 0;
break;
case BTC_GNT_SW_HI:
g[i].gnt_wl_sw_en = 1;
g[i].gnt_wl = 1;
break;
}
}
rtw_hal_mac_set_grant(h, (u8*)g);
}
void _set_gnt_bt(struct btc_t *btc, u8 phy_map, u8 state)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_dm *dm = &btc->dm;
struct btc_gnt_ctrl *g = dm->gnt;
u8 i;
if (phy_map > BTC_PHY_ALL)
return;
for (i = 0; i < BTC_PHY_MAX; i++) {
if (!(phy_map & BIT(i)))
continue;
switch (state) {
case BTC_GNT_HW:
g[i].gnt_bt_sw_en = 0;
g[i].gnt_bt = 0;
break;
case BTC_GNT_SW_LO:
g[i].gnt_bt_sw_en = 1;
g[i].gnt_bt = 0;
break;
case BTC_GNT_SW_HI:
g[i].gnt_bt_sw_en = 1;
g[i].gnt_bt = 1;
break;
}
}
rtw_hal_mac_set_grant(h, (u8*)g);
}
static void _set_bt_plut(struct btc_t *btc, u8 phy_map, u8 tx_val, u8 rx_val)
{
if (phy_map & BTC_PHY_0) {
rtw_hal_mac_set_polluted(btc->hal, HW_PHY_0, tx_val, rx_val);
btc->cx.wl.bt_polut_type[HW_PHY_0] = tx_val;
}
if (!btc->hal->dbcc_en)
return;
if (phy_map & BTC_PHY_1) {
rtw_hal_mac_set_polluted(btc->hal, HW_PHY_1, tx_val, rx_val);
btc->cx.wl.bt_polut_type[HW_PHY_1] = tx_val;
}
}
static void _set_ant(struct btc_t *btc, bool force_exec, u8 phy_map, u8 type)
{
struct btc_dm *dm = &btc->dm;
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_bt_info *bt = &cx->bt;
struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info;
u8 gnt_wl_ctrl, gnt_bt_ctrl, plt_ctrl, i, b2g = 0;
u32 ant_path_type;
ant_path_type = ((phy_map << 8) + type);
if (run_rsn("_cmd_set_coex") || run_rsn("_ntfy_power_off") ||
run_rsn("_ntfy_radio_state"))
force_exec = FC_EXEC;
if (!force_exec && (ant_path_type == dm->set_ant_path)) {
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): return by no change!!\n",
__func__);
return;
} else if (bt->rfk_info.map.run) {
PHL_INFO("[BTC], %s(): return by bt rfk!!\n", __func__);
return;
} else if (!run_rsn("_ntfy_wl_rfk") &&
wl->rfk_info.state != BTC_WRFK_STOP) {
PHL_INFO("[BTC], %s(): return by wl rfk!!\n", __func__);
return;
}
dm->set_ant_path = ant_path_type;
PHL_INFO("[BTC], %s(): path=0x%x, set_type=%s\n", __func__,
phy_map, id_to_str(BTC_STR_ANTPATH, dm->set_ant_path & 0xff));
switch (type){
case BTC_ANT_WPOWERON:
_set_cx_ctrl(btc, BTC_CTRL_BY_BT);
break;
case BTC_ANT_WINIT:
/* To avoid BT MP driver case (bt_enable but no mailbox) */
if (bt->enable.now && bt->run_patch_code) {
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_LO);
_set_gnt_bt(btc, phy_map, BTC_GNT_SW_HI);
} else {
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI);
_set_gnt_bt(btc, phy_map, BTC_GNT_SW_LO);
}
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
_set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_BT, BTC_PLT_BT);
break;
case BTC_ANT_WONLY:
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI);
_set_gnt_bt(btc, phy_map, BTC_GNT_SW_LO);
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
_set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE);
break;
case BTC_ANT_WOFF:
_set_cx_ctrl(btc, BTC_CTRL_BY_BT);
_set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE);
break;
case BTC_ANT_W2G:
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
if (btc->hal->dbcc_en) {
for (i = 0; i < HW_PHY_MAX; i++) {
b2g = (wl_dinfo->real_band[i] == BAND_ON_24G);
gnt_wl_ctrl = (b2g? BTC_GNT_HW : BTC_GNT_SW_HI);
_set_gnt_wl(btc, BIT(i), gnt_wl_ctrl);
gnt_bt_ctrl = BTC_GNT_HW;
_set_gnt_bt(btc, BIT(i), gnt_bt_ctrl);
plt_ctrl = (b2g? BTC_PLT_BT : BTC_PLT_NONE);
_set_bt_plut(btc, BIT(i), plt_ctrl, plt_ctrl);
}
} else {
_set_gnt_wl(btc, phy_map, BTC_GNT_HW);
_set_gnt_bt(btc, phy_map, BTC_GNT_HW);
plt_ctrl = BTC_PLT_BT;
_set_bt_plut(btc, BTC_PHY_ALL, plt_ctrl, plt_ctrl);
}
break;
case BTC_ANT_W5G:
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI);
_set_gnt_bt(btc, phy_map, BTC_GNT_HW);
_set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE);
break;
case BTC_ANT_W25G:
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
if (btc->hal->dbcc_en) {
/* if BAND_ON_24G, the other role in the sane PHY = 5G*/
for (i = 0; i < HW_PHY_MAX; i++) {
b2g = (wl_dinfo->real_band[i] == BAND_ON_24G);
gnt_wl_ctrl = (b2g? BTC_GNT_HW : BTC_GNT_SW_HI);
_set_gnt_wl(btc, BIT(i), gnt_wl_ctrl);
gnt_bt_ctrl = BTC_GNT_HW;
_set_gnt_bt(btc, BIT(i), gnt_bt_ctrl);
plt_ctrl = (b2g? BTC_PLT_GNT_WL : BTC_PLT_NONE);
_set_bt_plut(btc, BIT(i), plt_ctrl, plt_ctrl);
}
} else {
_set_gnt_wl(btc, phy_map, BTC_GNT_HW);
_set_gnt_bt(btc, phy_map, BTC_GNT_HW);
plt_ctrl = BTC_PLT_GNT_WL;
_set_bt_plut(btc, BTC_PHY_ALL, plt_ctrl, plt_ctrl);
}
break;
case BTC_ANT_FREERUN:
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI);
_set_gnt_bt(btc, phy_map, BTC_GNT_SW_HI);
_set_bt_plut(btc, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE);
break;
case BTC_ANT_WRFK:
_set_cx_ctrl(btc, BTC_CTRL_BY_WL);
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_HI);
_set_gnt_bt(btc, phy_map, BTC_GNT_SW_LO);
_set_bt_plut(btc, phy_map, BTC_PLT_NONE, BTC_PLT_NONE);
break;
case BTC_ANT_BRFK:
_set_cx_ctrl(btc, BTC_CTRL_BY_BT);
_set_gnt_wl(btc, phy_map, BTC_GNT_SW_LO);
_set_gnt_bt(btc, phy_map, BTC_GNT_SW_HI);
_set_bt_plut(btc, phy_map, BTC_PLT_NONE, BTC_PLT_NONE);
break;
}
}
void _action_wl_only(struct btc_t *btc)
{
PHL_INFO("[BTC], %s !!\n", __func__);
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
void _action_wl_init(struct btc_t *btc)
{
PHL_INFO("[BTC], %s !!\n", __func__);
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WINIT);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
void _action_wl_off(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
PHL_INFO("[BTC], %s !!\n", __func__);
/* don't set PTA control if LPS */
if (wl->status.map.rf_off || btc->dm.bt_only) {
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_WOFF);
} else if (wl->status.map.lps == 2) {
if (wl->role_info.link_mode == BTC_WLINK_5G)
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W5G);
else
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
}
if (wl->role_info.link_mode == BTC_WLINK_5G) {
_set_policy(btc, BTC_CXP_OFF_EQ0, __func__);
} else if (wl->status.map.lps == 2) {
if (btc->cx.bt.link_info.a2dp_desc.active)
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
else
_set_policy(btc, BTC_CXP_OFF_BWB1, __func__);
} else {
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
}
void _action_freerun(struct btc_t *btc)
{
PHL_INFO("[BTC], %s !!\n", __func__);
btc->dm.freerun = true;
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
void _action_bt_whql(struct btc_t *btc)
{
PHL_INFO("[BTC], %s !!\n", __func__);
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
void _action_bt_rfk(struct btc_t *btc)
{
PHL_INFO("[BTC], %s !!\n", __func__);
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_BRFK);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
void _action_bt_off(struct btc_t *btc)
{
PHL_INFO("[BTC], %s !!\n", __func__);
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
static void _action_bt_idle(struct btc_t *btc)
{
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_bt_link_info *b = &btc->cx.bt.link_info;
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt idle*/
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */
if (b->status.map.connect)
policy_type = BTC_CXP_FIX_TD4010;
else
policy_type = BTC_CXP_FIX_TD4010ISO;
break;
case BTC_WBUSY_BSCAN: /*wl-busy + bt-inq */
if (bt->pag)
policy_type = BTC_CXP_PFIX_TD2080;
else
policy_type = BTC_CXP_PFIX_TD5050;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq */
if (bt->pag)
policy_type = BTC_CXP_FIX_TD2080;
else
policy_type = BTC_CXP_FIX_TD5050;
break;
case BTC_WLINKING: /* wl-connecting + bt-inq or bt-idle */
if (bt->pag)
policy_type = BTC_CXP_FIX_TD2080;
else
policy_type = BTC_CXP_FIX_TD7010;
break;
case BTC_WIDLE: /* wl-idle + bt-idle */
policy_type = BTC_CXP_OFF_BWB1;
break;
}
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_hfp(struct btc_t *btc)
{
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (btc->cx.wl.status.map._4way)
policy_type = BTC_CXP_OFF_WL;
else
policy_type = BTC_CXP_OFF_BWB1;
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ2;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_hid(struct btc_t *btc)
{
struct btc_bt_hid_desc *hid = &btc->cx.bt.link_info.hid_desc;
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (btc->cx.wl.status.map._4way) {
policy_type = BTC_CXP_OFF_WL;
} else if (hid->type == BTC_HID_218) {
btc->cx.bt.scan_rx_low_pri = true;
policy_type = BTC_CXP_OFF_BWB2;
} else {
policy_type = BTC_CXP_OFF_BWB1;
}
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ3;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_a2dp(struct btc_t *btc)
{
struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info;
struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc;
struct btc_dm *dm = &btc->dm;
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */
if (a2dp.vendor_id == 0x4c || dm->leak_ap ||
bt_linfo->slave_role) {
if (bt_linfo->slave_role)
dm->slot_dur[CXST_W1] = 20;
else
dm->slot_dur[CXST_W1] = 40;
dm->slot_dur[CXST_B1] = BTC_B1_MAX;
policy_type = BTC_CXP_PAUTO_TDW1B1;
} else {
policy_type = BTC_CXP_PAUTO_TD50B1;
}
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */
policy_type = BTC_CXP_PAUTO2_TD3050;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */
policy_type = BTC_CXP_AUTO2_TD3050;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */
case BTC_WLINKING: /* wl-connecting + bt-A2DP */
if (a2dp.vendor_id == 0x4c || dm->leak_ap ||
bt_linfo->slave_role) {
if (bt_linfo->slave_role)
dm->slot_dur[CXST_W1] = 20;
else
dm->slot_dur[CXST_W1] = 40;
dm->slot_dur[CXST_B1] = BTC_B1_MAX;
policy_type = BTC_CXP_AUTO_TDW1B1;
} else {
policy_type = BTC_CXP_AUTO_TD50B1;
}
break;
case BTC_WIDLE: /* wl-idle + bt-A2DP */
policy_type = BTC_CXP_AUTO_TD20B1;
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_a2dpsink(struct btc_t *btc)
{
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2dp_Sink */
policy_type = BTC_CXP_PFIX_TD2030;
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2dp_Sink */
policy_type = BTC_CXP_PFIX_TD2060;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2dp_Sink */
policy_type = BTC_CXP_FIX_TD2030;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2dp_Sink */
policy_type = BTC_CXP_FIX_TD2060;
break;
case BTC_WLINKING: /* wl-connecting + bt-A2dp_Sink */
policy_type = BTC_CXP_FIX_TD3030;
break;
case BTC_WIDLE: /* wl-idle + bt-A2dp_Sink */
policy_type = BTC_CXP_FIX_TD2080;
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_pan(struct btc_t *btc)
{
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN */
policy_type = BTC_CXP_PFIX_TD5050;
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN */
policy_type = BTC_CXP_PFIX_TD3070;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN */
policy_type = BTC_CXP_FIX_TD3030;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN */
policy_type = BTC_CXP_FIX_TD3060;
break;
case BTC_WLINKING: /* wl-connecting + bt-PAN */
policy_type = BTC_CXP_FIX_TD4010ISO;
break;
case BTC_WIDLE: /* wl-idle + bt-pan */
policy_type = BTC_CXP_PFIX_TD2080;
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_a2dp_hid(struct btc_t *btc)
{
struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info;
struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc;
struct btc_dm *dm = &btc->dm;
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */
case BTC_WIDLE: /* wl-idle + bt-A2DP */
if (a2dp.vendor_id == 0x4c || dm->leak_ap ||
bt_linfo->slave_role) {
if (bt_linfo->slave_role)
dm->slot_dur[CXST_W1] = 20;
else
dm->slot_dur[CXST_W1] = 40;
dm->slot_dur[CXST_W1] = 40;
dm->slot_dur[CXST_B1] = BTC_B1_MAX;
policy_type = BTC_CXP_PAUTO_TDW1B1;
} else {
policy_type = BTC_CXP_PAUTO_TD50B1;
}
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */
policy_type = BTC_CXP_PAUTO2_TD3050;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */
policy_type = BTC_CXP_AUTO2_TD3050;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */
case BTC_WLINKING: /* wl-connecting + bt-A2DP */
if (a2dp.vendor_id == 0x4c || dm->leak_ap ||
bt_linfo->slave_role) {
if (bt_linfo->slave_role)
dm->slot_dur[CXST_W1] = 20;
else
dm->slot_dur[CXST_W1] = 40;
dm->slot_dur[CXST_B1] = BTC_B1_MAX;
policy_type = BTC_CXP_AUTO_TDW1B1;
} else {
policy_type = BTC_CXP_AUTO_TD50B1;
}
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_a2dp_pan(struct btc_t *btc)
{
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN */
policy_type = BTC_CXP_PAUTO2_TD3070;
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN */
policy_type = BTC_CXP_PAUTO2_TD3070;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN */
policy_type = BTC_CXP_AUTO2_TD5050;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN */
policy_type = BTC_CXP_AUTO2_TD3070;
break;
case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN */
policy_type = BTC_CXP_AUTO2_TD3050;
break;
case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN */
policy_type = BTC_CXP_PAUTO2_TD2080;
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_pan_hid(struct btc_t *btc)
{
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN+HID */
policy_type = BTC_CXP_PFIX_TD3030;
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN+HID */
policy_type = BTC_CXP_PFIX_TD3070;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN+HID */
policy_type = BTC_CXP_FIX_TD3030;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN+HID */
policy_type = BTC_CXP_FIX_TD3060;
break;
case BTC_WLINKING: /* wl-connecting + bt-PAN+HID */
policy_type = BTC_CXP_FIX_TD4010;
break;
case BTC_WIDLE: /* wl-idle + bt-PAN+HID */
policy_type = BTC_CXP_PFIX_TD2080;
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
static void _action_bt_a2dp_pan_hid(struct btc_t *btc)
{
u16 policy_type = BTC_CXP_OFF_BT;
switch(btc->cx.state_map) {
case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN+HID */
policy_type = BTC_CXP_PAUTO2_TD3070;
break;
case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN+HID */
policy_type = BTC_CXP_PAUTO2_TD3070;
break;
case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN+HID */
policy_type = BTC_CXP_AUTO2_TD3070;
break;
case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN+HID */
case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN+HID */
policy_type = BTC_CXP_AUTO2_TD3050;
break;
case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN+HID */
policy_type = BTC_CXP_PAUTO2_TD2080;
break;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_5g(struct btc_t *btc)
{
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W5G);
_set_policy(btc, BTC_CXP_OFF_EQ0, __func__);
}
void _action_wl_other(struct btc_t *btc)
{
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
if (btc->mdinfo.ant.type == BTC_ANT_SHARED)
_set_policy(btc, BTC_CXP_OFFB_BWB0, __func__);
else
_set_policy(btc, BTC_CXP_OFF_EQ0, __func__);
}
void _action_wl_idle(struct btc_t *btc)
{
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
if (btc->mdinfo.ant.type == BTC_ANT_SHARED)
_set_policy(btc, BTC_CXP_OFFB_BWB0, __func__);
else
_set_policy(btc, BTC_CXP_OFF_EQ0, __func__);
}
void _action_wl_nc(struct btc_t *btc)
{
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, BTC_CXP_OFF_BT, __func__);
}
void _action_wl_rfk(struct btc_t *btc)
{
struct btc_wl_rfk_info rfk = btc->cx.wl.rfk_info;
if (rfk.state != BTC_WRFK_START)
return;
PHL_INFO("[BTC], %s(): band = %d\n", __func__, rfk.band);
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK);
_set_policy(btc, BTC_CXP_OFF_WL, __func__);
#if 0
if (rfk.band == BAND_ON_24G) {
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK);
_set_policy(btc, BTC_CXP_OFF_WL, __func__);
} else {
_set_ant(btc, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN);
_set_policy(btc, BTC_CXP_OFF_EQ0, __func__);
}
#endif
}
void _action_common(struct btc_t *btc)
{
_set_halbb_btg_ctrl(btc);
_set_halmac_tx_limit(btc);
_set_bt_afh_info(btc);
_set_bt_rx_agc(btc); /* must call after _set_halbb_btg_ctrl */
_set_bt_slot_req(btc);
_set_bt_rx_scan_pri(btc);
_set_rf_trx_para(btc);
}
static void _action_by_bt(struct btc_t *btc)
{
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_bt_link_info *bt_linfo = &bt->link_info;
struct btc_bt_hid_desc hid = bt_linfo->hid_desc;
struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc;
struct btc_bt_pan_desc pan = bt_linfo->pan_desc;
u8 profile_map = 0;
if (bt_linfo->hfp_desc.exist)
profile_map |= BTC_BT_HFP;
if (bt_linfo->hid_desc.exist)
profile_map |= BTC_BT_HID;
if (bt_linfo->a2dp_desc.exist)
profile_map |= BTC_BT_A2DP;
if (bt_linfo->pan_desc.exist)
profile_map |= BTC_BT_PAN;
switch (profile_map) {
case 0:
if (_check_freerun(btc))
_action_freerun(btc);
else if (a2dp.active || pan.active)
_action_bt_pan(btc);
else
_action_bt_idle(btc);
break;
case BTC_BT_HFP:
if (_check_freerun(btc))
_action_freerun(btc);
else
_action_bt_hfp(btc);
break;
case BTC_BT_HFP | BTC_BT_HID:
case BTC_BT_HID:
if (_check_freerun(btc))
_action_freerun(btc);
else
_action_bt_hid(btc);
break;
case BTC_BT_A2DP:
if (_check_freerun(btc))
_action_freerun(btc);
else if (a2dp.sink)
_action_bt_a2dpsink(btc);
else if (bt_linfo->multi_link.now && !hid.pair_cnt)
_action_bt_a2dp_pan(btc);
else
_action_bt_a2dp(btc);
break;
case BTC_BT_PAN:
_action_bt_pan(btc);
break;
case BTC_BT_A2DP | BTC_BT_HFP:
case BTC_BT_A2DP | BTC_BT_HID:
case BTC_BT_A2DP | BTC_BT_HFP | BTC_BT_HID:
if (_check_freerun(btc))
_action_freerun(btc);
else
_action_bt_a2dp_hid(btc);
break;
case BTC_BT_A2DP | BTC_BT_PAN:
_action_bt_a2dp_pan(btc);
break;
case BTC_BT_PAN | BTC_BT_HFP:
case BTC_BT_PAN | BTC_BT_HID:
case BTC_BT_PAN | BTC_BT_HFP | BTC_BT_HID:
_action_bt_pan_hid(btc);
break;
case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HID:
case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HFP:
default:
_action_bt_a2dp_pan_hid(btc);
break;
}
}
void _action_wl_2g_sta(struct btc_t *btc)
{
_action_by_bt(btc);
}
void _action_wl_scan(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info;
if (btc->hal->dbcc_en) {
if (wl_dinfo->real_band[HW_PHY_0] != BAND_ON_24G &&
wl_dinfo->real_band[HW_PHY_1] != BAND_ON_24G)
_action_wl_5g(btc);
else
_action_by_bt(btc);
} else {
if (wl->scan_info.band[HW_PHY_0] != BAND_ON_24G)
_action_wl_5g(btc);
else
_action_by_bt(btc);
}
}
void _action_wl_25g_mcc(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED)/* shared-antenna */ {
if (wl->status.map._4way)
policy_type = BTC_CXP_OFFE_WL;
else if (bt->link_info.status.map.connect == 0)
policy_type = BTC_CXP_OFFE_2GISOB;
else
policy_type = BTC_CXP_OFFE_2GBWISOB;
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_2g_mcc(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (wl->status.map._4way)
policy_type = BTC_CXP_OFFE_WL;
else if (bt->link_info.status.map.connect == 0)
policy_type = BTC_CXP_OFFE_2GISOB;
else
policy_type = BTC_CXP_OFFE_2GBWISOB;
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_2g_scc(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_dm *dm = &btc->dm;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
u16 policy_type = BTC_CXP_OFF_BT;
u32 dur;
if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED) {
policy_type = BTC_CXP_OFF_EQ0;
goto exit;
}
/* shared-antenna */
switch(wl_rinfo->mrole_type) {
default:
#if 0
case BTC_WLMROLE_STA_GO:
case BTC_WLMROLE_STA_GO_NOA:
dm->wl_scc.null_role1 = PHL_RTYPE_STATION;
dm->wl_scc.null_role2 = PHL_RTYPE_NONE;
dm->wl_scc.ebt_null = 0;
policy_type = BTC_CXP_OFF_BWB1;
#endif
break;
case BTC_WLMROLE_STA_GC:
dm->wl_scc.null_role1 = PHL_RTYPE_STATION;
dm->wl_scc.null_role2 = PHL_RTYPE_P2P_GC;
dm->wl_scc.ebt_null = 0; /* no ext-slot-control */
_action_by_bt(btc);
return;
case BTC_WLMROLE_STA_STA:
dm->wl_scc.null_role1 = PHL_RTYPE_STATION;
dm->wl_scc.null_role2 = PHL_RTYPE_STATION;
dm->wl_scc.ebt_null = 0; /* no ext-slot-control */
_action_by_bt(btc);
return;
case BTC_WLMROLE_STA_GC_NOA:
case BTC_WLMROLE_STA_GO:
case BTC_WLMROLE_STA_GO_NOA:
dm->wl_scc.null_role1 = PHL_RTYPE_STATION;
dm->wl_scc.null_role2 = PHL_RTYPE_NONE;
dur = wl_rinfo->mrole_noa_duration;
if (wl->status.map._4way) {
dm->wl_scc.ebt_null = 0;
policy_type = BTC_CXP_OFFE_WL;
} else if (bt->link_info.status.map.connect == 0) {
dm->wl_scc.ebt_null = 0;
policy_type = BTC_CXP_OFFE_2GISOB;
} else if (bt->link_info.a2dp_desc.exist &&
dur < btc->bt_req_len) {
dm->wl_scc.ebt_null = 1; /* tx null at EBT */
policy_type = BTC_CXP_OFFE_2GBWMIXB2;
} else if (bt->link_info.a2dp_desc.exist ||
bt->link_info.pan_desc.exist) {
dm->wl_scc.ebt_null = 1; /* tx null at EBT */
policy_type = BTC_CXP_OFFE_2GBWISOB;
}else {
dm->wl_scc.ebt_null = 0;
policy_type = BTC_CXP_OFFE_2GBWISOB;
}
break;
}
exit:
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_2g_ap(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
u16 policy_type = BTC_CXP_OFF_BT;
/* Todo:if client issue Null-P, ap should follow Null/Null-P slot */
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (wl->status.map._4way)
policy_type = BTC_CXP_OFFE_WL;
else if (bt->link_info.status.map.connect == 0)
policy_type = BTC_CXP_OFFE_2GISOB;
else
policy_type = BTC_CXP_OFFE_2GBWISOB;
} else {/* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_2g_go(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (wl->status.map._4way)
policy_type = BTC_CXP_OFFE_WL;
else if (bt->link_info.status.map.connect == 0)
policy_type = BTC_CXP_OFFE_2GISOB;
else
policy_type = BTC_CXP_OFFE_2GBWISOB;
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_2g_gc(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
u8 noa = 0, pid = 0;
u16 policy_type = BTC_CXP_OFF_BT;
u32 noa_duration = 0;
pid = _get_wl_role_idx(btc, PHL_RTYPE_P2P_GC);
if (pid < MAX_WIFI_ROLE_NUMBER) {
noa = wl_rinfo->active_role[pid].noa;
noa_duration = wl_rinfo->active_role[pid].noa_duration;
}
/* Check GC, GC+NOA */
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (!noa) { /* Gc without NOA */
_action_by_bt(btc);
return;
} else { /* Gc with NOA */
if (wl->status.map._4way)
policy_type = BTC_CXP_OFFE_WL;
else if (bt->link_info.status.map.connect == 0)
policy_type = BTC_CXP_OFFE_2GISOB;
else if (bt->link_info.a2dp_desc.exist &&
noa_duration < btc->bt_req_len)
policy_type = BTC_CXP_OFFE_2GBWMIXB;
else
policy_type = BTC_CXP_OFFE_2GBWISOB;
}
} else {/* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
void _action_wl_2g_nan(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
u16 policy_type = BTC_CXP_OFF_BT;
if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */
if (wl->status.map._4way)
policy_type = BTC_CXP_OFFE_WL;
else if (bt->link_info.status.map.connect == 0)
policy_type = BTC_CXP_OFFE_2GISOB;
else
policy_type = BTC_CXP_OFFE_2GBWISOB;
} else { /* dedicated-antenna */
policy_type = BTC_CXP_OFF_EQ0;
}
_set_ant(btc, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G);
_set_policy(btc, policy_type, __func__);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_action.c
|
C
|
agpl-3.0
| 56,234
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_BTC_ACTION_H__
#define __INC_BTC_ACTION_H__
enum {
BTC_PHY_0 = BIT(0),
BTC_PHY_1 = BIT(1),
BTC_PHY_ALL = BIT(0) | BIT(1),
};
enum btc_cx_state_map {
BTC_WIDLE = 0,
BTC_WBUSY_BNOSCAN,
BTC_WBUSY_BSCAN,
BTC_WSCAN_BNOSCAN,
BTC_WSCAN_BSCAN,
BTC_WLINKING
};
enum btc_ant_phase {
BTC_ANT_WPOWERON = 0,
BTC_ANT_WINIT,
BTC_ANT_WONLY,
BTC_ANT_WOFF,
BTC_ANT_W2G,
BTC_ANT_W5G,
BTC_ANT_W25G,
BTC_ANT_FREERUN,
BTC_ANT_WRFK,
BTC_ANT_BRFK,
BTC_ANT_MAX
};
enum {
BTC_PLT_NONE = 0,
BTC_PLT_LTE_RX = BIT(0),
BTC_PLT_GNT_BT_TX = BIT(1),
BTC_PLT_GNT_BT_RX = BIT(2),
BTC_PLT_GNT_WL = BIT(3),
BTC_PLT_BT = BIT(1) | BIT(2),
BTC_PLT_ALL = 0xf
};
enum btc_cx_poicy_main_type {
BTC_CXP_OFF = 0,
BTC_CXP_OFFB,
BTC_CXP_OFFE,
BTC_CXP_FIX,
BTC_CXP_PFIX,
BTC_CXP_AUTO,
BTC_CXP_PAUTO,
BTC_CXP_AUTO2,
BTC_CXP_PAUTO2,
BTC_CXP_MANUAL,
BTC_CXP_USERDEF0,
BTC_CXP_MAIN_MAX
};
enum {
BTC_BSLOT_A2DP_HID = 60,
BTC_BSLOT_A2DP = 50,
BTC_BSLOT_INQ = 30,
BTC_BSLOT_IDLE = 20,
};
enum btc_cx_poicy_type {
/* TDMA off + pri: BT > WL */
BTC_CXP_OFF_BT = (BTC_CXP_OFF << 8) | 0,
/* TDMA off + pri: WL > BT */
BTC_CXP_OFF_WL = (BTC_CXP_OFF << 8) | 1,
/* TDMA off + pri: BT = WL */
BTC_CXP_OFF_EQ0 = (BTC_CXP_OFF << 8) | 2,
/* TDMA off + pri: BT = WL > BT_Lo */
BTC_CXP_OFF_EQ1 = (BTC_CXP_OFF << 8) | 3,
/* TDMA off + pri: WL = BT, BT_Rx > WL_Lo_Tx */
BTC_CXP_OFF_EQ2 = (BTC_CXP_OFF << 8) | 4,
/* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */
BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5,
/* TDMA off + pri: BT_Hi > WL > BT_Lo */
BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 6,
/* TDMA off + pri: BT_Hi_Tx = WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */
BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 7,
/* TDMA off + pri: WL_Hi-Tx > BT, BT_Hi > other-WL > BT_Lo */
BTC_CXP_OFF_BWB2 = (BTC_CXP_OFF << 8) | 8,
/* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/
BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0,
/* TDMA off + Ext-Ctrl + pri: default */
BTC_CXP_OFFE_2GBWISOB = (BTC_CXP_OFFE << 8) | 0,
/* TDMA off + Ext-Ctrl + pri: E2G-slot block all BT */
BTC_CXP_OFFE_2GISOB = (BTC_CXP_OFFE << 8) | 1,
/* TDMA off + Ext-Ctrl + pri: E2G-slot WL > BT */
BTC_CXP_OFFE_2GBWMIXB = (BTC_CXP_OFFE << 8) | 2,
/* TDMA off + Ext-Ctrl + pri: E2G/EBT-slot WL > BT */
BTC_CXP_OFFE_WL = (BTC_CXP_OFFE << 8) | 3,
/* TDMA off + Ext-Ctrl + pri: default */
BTC_CXP_OFFE_2GBWMIXB2 = (BTC_CXP_OFFE << 8) | 4,
/* TDMA Fix slot-0: W1:B1 = 30:30 */
BTC_CXP_FIX_TD3030 = (BTC_CXP_FIX << 8) | 0,
/* TDMA Fix slot-1: W1:B1 = 50:50 */
BTC_CXP_FIX_TD5050 = (BTC_CXP_FIX << 8) | 1,
/* TDMA Fix slot-2: W1:B1 = 20:30 */
BTC_CXP_FIX_TD2030 = (BTC_CXP_FIX << 8) | 2,
/* TDMA Fix slot-3: W1:B1 = 40:10 */
BTC_CXP_FIX_TD4010 = (BTC_CXP_FIX << 8) | 3,
/* TDMA Fix slot-4: W1:B1 = 70:10 */
BTC_CXP_FIX_TD7010 = (BTC_CXP_FIX << 8) | 4,
/* TDMA Fix slot-5: W1:B1 = 20:60 */
BTC_CXP_FIX_TD2060 = (BTC_CXP_FIX << 8) | 5,
/* TDMA Fix slot-6: W1:B1 = 30:60 */
BTC_CXP_FIX_TD3060 = (BTC_CXP_FIX << 8) | 6,
/* TDMA Fix slot-7: W1:B1 = 20:80 */
BTC_CXP_FIX_TD2080 = (BTC_CXP_FIX << 8) | 7,
/* TDMA Fix slot-8: W1:B1 = user-define */
BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8,
/* TDMA Fix slot-9: W1:B1 = 40:10 */
BTC_CXP_FIX_TD4010ISO = (BTC_CXP_FIX << 8) | 9,
/* PS-TDMA Fix slot-0: W1:B1 = 30:30 */
BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0,
/* PS-TDMA Fix slot-1: W1:B1 = 50:50 */
BTC_CXP_PFIX_TD5050 = (BTC_CXP_PFIX << 8) | 1,
/* PS-TDMA Fix slot-2: W1:B1 = 20:30 */
BTC_CXP_PFIX_TD2030 = (BTC_CXP_PFIX << 8) | 2,
/* PS-TDMA Fix slot-3: W1:B1 = 20:60 */
BTC_CXP_PFIX_TD2060 = (BTC_CXP_PFIX << 8) | 3,
/* PS-TDMA Fix slot-4: W1:B1 = 30:70 */
BTC_CXP_PFIX_TD3070 = (BTC_CXP_PFIX << 8) | 4,
/* PS-TDMA Fix slot-5: W1:B1 = 20:80 */
BTC_CXP_PFIX_TD2080 = (BTC_CXP_PFIX << 8) | 5,
/* PS-TDMA Fix slot-6: W1:B1 = user-define */
BTC_CXP_PFIX_TDW1B1 = (BTC_CXP_PFIX << 8) | 6,
/* TDMA Auto slot-0: W1:B1 = 50:BTC_B1_MAX */
BTC_CXP_AUTO_TD50B1 = (BTC_CXP_AUTO << 8) | 0,
/* TDMA Auto slot-1: W1:B1 = 60:BTC_B1_MAX */
BTC_CXP_AUTO_TD60B1 = (BTC_CXP_AUTO << 8) | 1,
/* TDMA Auto slot-2: W1:B1 = 20:BTC_B1_MAX */
BTC_CXP_AUTO_TD20B1 = (BTC_CXP_AUTO << 8) | 2,
/* TDMA Auto slot-3: W1:B1 = user-define */
BTC_CXP_AUTO_TDW1B1 = (BTC_CXP_AUTO << 8) | 3,
/* PS-TDMA Auto slot-0: W1:B1 = 50:BTC_B1_MAX */
BTC_CXP_PAUTO_TD50B1 = (BTC_CXP_PAUTO << 8) | 0,
/* PS-TDMA Auto slot-1: W1:B1 = 60:BTC_B1_MAX */
BTC_CXP_PAUTO_TD60B1 = (BTC_CXP_PAUTO << 8) | 1,
/* PS-TDMA Auto slot-2: W1:B1 = 20:BTC_B1_MAX */
BTC_CXP_PAUTO_TD20B1 = (BTC_CXP_PAUTO << 8) | 2,
/* PS-TDMA Auto slot-3: W1:B1 = user-define */
BTC_CXP_PAUTO_TDW1B1 = (BTC_CXP_PAUTO << 8) | 3,
/* TDMA Auto slot2-0: W1:B4 = 30:50 */
BTC_CXP_AUTO2_TD3050 = (BTC_CXP_AUTO2 << 8) | 0,
/* TDMA Auto slot2-1: W1:B4 = 30:70 */
BTC_CXP_AUTO2_TD3070 = (BTC_CXP_AUTO2 << 8) | 1,
/* TDMA Auto slot2-2: W1:B4 = 50:50 */
BTC_CXP_AUTO2_TD5050 = (BTC_CXP_AUTO2 << 8) | 2,
/* TDMA Auto slot2-3: W1:B4 = 60:60 */
BTC_CXP_AUTO2_TD6060 = (BTC_CXP_AUTO2 << 8) | 3,
/* TDMA Auto slot2-4: W1:B4 = 20:80 */
BTC_CXP_AUTO2_TD2080 = (BTC_CXP_AUTO2 << 8) | 4,
/* TDMA Auto slot2-5: W1:B4 = user-define */
BTC_CXP_AUTO2_TDW1B4 = (BTC_CXP_AUTO2 << 8) | 5,
/* PS-TDMA Auto slot2-0: W1:B4 = 30:50 */
BTC_CXP_PAUTO2_TD3050 = (BTC_CXP_PAUTO2 << 8) | 0,
/* PS-TDMA Auto slot2-1: W1:B4 = 30:70 */
BTC_CXP_PAUTO2_TD3070 = (BTC_CXP_PAUTO2 << 8) | 1,
/* PS-TDMA Auto slot2-2: W1:B4 = 50:50 */
BTC_CXP_PAUTO2_TD5050 = (BTC_CXP_PAUTO2 << 8) | 2,
/* PS-TDMA Auto slot2-3: W1:B4 = 60:60 */
BTC_CXP_PAUTO2_TD6060 = (BTC_CXP_PAUTO2 << 8) | 3,
/* PS-TDMA Auto slot2-4: W1:B4 = 20:80 */
BTC_CXP_PAUTO2_TD2080 = (BTC_CXP_PAUTO2 << 8) | 4,
/* PS-TDMA Auto slot2-5: W1:B4 = user-define */
BTC_CXP_PAUTO2_TDW1B4 = (BTC_CXP_PAUTO2 << 8) | 5,
BTC_CXP_MAX = 0xffff
};
void _action_wl_25g_mcc(struct btc_t *btc);
void _action_wl_2g_ap(struct btc_t *btc);
void _action_wl_2g_go(struct btc_t *btc);
void _action_wl_2g_gc(struct btc_t *btc);
void _action_wl_2g_nan(struct btc_t *btc);
void _action_wl_2g_scc(struct btc_t *btc);
void _action_wl_2g_sta(struct btc_t *btc);
void _action_wl_scan(struct btc_t *btc);
void _action_wl_2g_mcc(struct btc_t *btc);
void _action_wl_5g(struct btc_t *btc);
void _action_wl_other(struct btc_t *btc);
void _action_wl_idle(struct btc_t *btc);
void _action_wl_nc(struct btc_t *btc);
void _action_wl_rfk(struct btc_t *btc);
void _action_wl_init(struct btc_t *btc);
void _action_wl_off(struct btc_t *btc);
void _action_freerun(struct btc_t *btc);
void _action_wl_only(struct btc_t *btc);
void _action_bt_off(struct btc_t *btc);
void _action_bt_rfk(struct btc_t *btc);
void _action_bt_whql(struct btc_t *btc);
void _action_common(struct btc_t *btc);
//extern const u32 cxtbl[];
void _update_btc_state_map(struct btc_t *btc);
void _set_bt_ignore_wlan_act(struct btc_t *btc, u8 enable);
void _set_wl_tx_power(struct btc_t *btc, u32 level);
void _set_wl_rx_gain(struct btc_t *btc, u32 level);
void _set_bt_tx_power(struct btc_t *btc, u32 level);
void _set_bt_rx_gain(struct btc_t *btc, u32 level);
void _set_gnt_wl(struct btc_t *btc, u8 phy_map, u8 state);
void _set_gnt_bt(struct btc_t *btc, u8 phy_map, u8 state);
extern struct fbtc_tdma t_def[];
extern struct fbtc_slot s_def[];
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_action.h
|
C
|
agpl-3.0
| 7,987
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_BTC_DBG_CMD_C_
#include "../hal_headers_le.h"
#include "hal_btc.h"
#include "halbtc_fw.h"
#include "halbtc_fwdef.h"
#include "halbtc_action.h"
#include "halbtc_def.h"
#ifdef CONFIG_BTCOEX
#define BTC_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
struct halbtc_cmd_info {
char name[16];
u8 id;
};
enum HALBTC_CMD_ID {
HALBTC_HELP,
HALBTC_SHOW,
HALBTC_READ_BT,
HALBTC_WRITE_BT,
HALBTC_SET_COEX,
HALBTC_UPDATE_POLICY,
HALBTC_TDMA,
HALBTC_SLOT,
HALBTC_SIG_GDBG_EN,
HALBTC_SGPIO_MAP,
HALBTC_TRACE_STEP,
HALBTC_WL_TX_POWER,
HALBTC_WL_RX_LNA,
HALBTC_BT_AFH_MAP,
HALBTC_BT_TX_POWER,
HALBTC_BT_RX_LNA,
HALBTC_BT_IGNO_WLAN,
HALBTC_SET_GNT_WL,
HALBTC_SET_GNT_BT,
HALBTC_SET_BT_PSD,
HALBTC_GET_WL_NHM_DBM,
HALBTC_DBG
};
struct halbtc_cmd_info halbtc_cmd_i[] = {
{"-h", HALBTC_HELP},
{"show", HALBTC_SHOW},
{"rb", HALBTC_READ_BT},
{"wb", HALBTC_WRITE_BT},
{"mode", HALBTC_SET_COEX},
{"update", HALBTC_UPDATE_POLICY},
{"tdma", HALBTC_TDMA},
{"slot", HALBTC_SLOT},
{"sig", HALBTC_SIG_GDBG_EN},
{"gpio", HALBTC_SGPIO_MAP},
{"wpwr", HALBTC_WL_TX_POWER},
{"wlna", HALBTC_WL_RX_LNA},
{"afh", HALBTC_BT_AFH_MAP},
{"bpwr", HALBTC_BT_TX_POWER},
{"blna", HALBTC_BT_RX_LNA},
{"igwl", HALBTC_BT_IGNO_WLAN},
{"gwl", HALBTC_SET_GNT_WL},
{"gbt", HALBTC_SET_GNT_BT},
{"bpsd", HALBTC_SET_BT_PSD},
{"wnhm", HALBTC_GET_WL_NHM_DBM},
{"dbg", HALBTC_DBG}
};
static void _cmd_rb(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 i = 0, type = 0, addr = 0;
if (input_num < 3)
goto help;
_os_sscanf(input[1], "%d", &type);
_os_sscanf(input[2], "%x", &addr);
if (type > 4)
goto help;
btc->dbg.rb_done = false;
btc->dbg.rb_val = 0xffffffff;
_read_bt_reg(btc, (u8)(type), (u16)addr);
for (i = 0; i < 50; i++) {
if (!btc->dbg.rb_done)
hal_mdelay(btc->hal, 10);
else
goto exit;
}
exit:
if (!btc->dbg.rb_done) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" timeout !! \n");
} else {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" rb %d(0x%x), val = 0x%x !! \n", type, addr, btc->dbg.rb_val);
}
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" rb <type --- 0:rf, 1:modem, 2:bluewize, 3:vendor, 4:LE> <addr:16bits> \n");
return;
}
static void _show_cx_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_dm *dm = &btc->dm;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_wl_info *wl = &btc->cx.wl;
struct rtw_hal_com_t *h = btc->hal;
u32 ver_main = 0, ver_sub = 0, ver_hotfix = 0, id_branch = 0;
if (!(dm->coex_info_map & BTC_COEX_INFO_CX))
return;
dm->cnt_notify[BTC_NCNT_SHOW_COEX_INFO]++;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r========== [BTC COEX INFO (%s)] ==========",
id_to_str(BTC_STR_CHIPID, (u32)btc->chip->chip_id));
ver_main = (coex_ver & bMASKB3) >> 24;
ver_sub = (coex_ver & bMASKB2) >> 16;
ver_hotfix = (coex_ver & bMASKB1) >> 8;
id_branch = coex_ver & bMASKB0;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : Coex:%d.%d.%d(branch:%d), ",
"[coex_version]", ver_main, ver_sub, ver_hotfix, id_branch);
ver_main = (wl->ver_info.fw_coex & bMASKB3) >> 24;
ver_sub = (wl->ver_info.fw_coex & bMASKB2) >> 16;
ver_hotfix = (wl->ver_info.fw_coex & bMASKB1) >> 8;
id_branch = wl->ver_info.fw_coex & bMASKB0;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"WL_FW_coex:%d.%d.%d(branch:%d)",
ver_main, ver_sub, ver_hotfix, id_branch);
ver_main = (btc->chip->wlcx_desired & bMASKB3) >> 24;
ver_sub = (btc->chip->wlcx_desired & bMASKB2) >> 16;
ver_hotfix = (btc->chip->wlcx_desired & bMASKB1) >> 8;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"(%s, desired:%d.%d.%d), ",
(wl->ver_info.fw_coex >= btc->chip->wlcx_desired ?
"Match" : "Mis-Match"),
ver_main, ver_sub, ver_hotfix);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"BT_FW_coex:%d(%s, desired:%d)",
bt->ver_info.fw_coex,
(bt->ver_info.fw_coex >= btc->chip->btcx_desired ?
"Match" : "Mis-Match"),
btc->chip->btcx_desired);
if (bt->enable.now && bt->ver_info.fw == 0)
hal_btc_fw_en_rpt(btc, RPT_EN_BT_VER_INFO, 1);
else
hal_btc_fw_en_rpt(btc, RPT_EN_BT_VER_INFO, 0);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : WL_FW:%d.%d.%d.%d, BT_FW:0x%x(%s)",
"[sub_module]", (wl->ver_info.fw & bMASKB3) >> 24,
(wl->ver_info.fw & bMASKB2) >> 16,
(wl->ver_info.fw & bMASKB1) >> 8,
(wl->ver_info.fw & bMASKB0), bt->ver_info.fw,
(bt->run_patch_code ? "patch" : "ROM"));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : kt_ver:%x, rfe_type:0x%x, hw_id:0x%x, ant_iso:%d, ant_pg:%d, %s",
"[hw_info]", btc->mdinfo.kt_ver, btc->mdinfo.rfe_type,
((btc->phl->id.id & 0xff00) >> 8),
btc->mdinfo.ant.isolation, btc->mdinfo.ant.num,
(btc->mdinfo.ant.num > 1? "" : (btc->mdinfo.ant.single_pos?
"1Ant_Pos:S1, " : "1Ant_Pos:S0, ")));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"3rd_coex:%d, dbcc:%d, tx_num:%d, rx_num:%d",
btc->cx.other.type, h->dbcc_en, h->rfpath_tx_num,
h->rfpath_rx_num);
}
static void _show_wl_role_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_wl_link_info *plink = NULL;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info;
struct btc_traffic t;
u8 i;
if (btc->hal->dbcc_en) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : PHY0_band(op:%d/scan:%d/real:%d), ",
"[dbcc_info]", wl_dinfo->op_band[HW_PHY_0],
wl_dinfo->scan_band[HW_PHY_0],
wl_dinfo->real_band[HW_PHY_0]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"PHY1_band(op:%d/scan:%d/real:%d)",
wl_dinfo->op_band[HW_PHY_1],
wl_dinfo->scan_band[HW_PHY_1],
wl_dinfo->real_band[HW_PHY_1]);
}
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) {
plink = &btc->cx.wl.link_info[i];
if (!plink->active)
continue;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r [port_%d] : role=%s(phy-%d), connect=%s(client_cnt=%d), mode=%s, ch=(ct:%d/pr:%d), bw=%s",
plink->pid,
id_to_str(BTC_STR_ROLE, (u32)plink->role),
plink->phy,
id_to_str(BTC_STR_MSTATE, (u32)plink->connected),
plink->client_cnt-1,
id_to_str(BTC_STR_WLMODE, (u32)plink->mode),
plink->chdef.center_ch, plink->chdef.chan,
id_to_str(BTC_STR_WLBW, (u32)plink->chdef.bw));
if (plink->connected == MLME_NO_LINK)
continue;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", mac_id=%d, noa(%d)=%d.%03dms",
plink->mac_id, plink->noa,
plink->noa_duration/1000, plink->noa_duration%1000);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r [port_%d] : rssi=-%ddBm(%d), busy=%d, dir=%s, ",
plink->pid, 110-plink->stat.rssi,
plink->stat.rssi, plink->busy,
(plink->dir == TRAFFIC_UL ? "UL" : "DL"));
t = plink->stat.traffic;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"tx[rate:%s/busy_level:%d/sts:0x%x], ",
id_to_str(BTC_STR_RATE, (u32)t.tx_rate),
t.tx_lvl, t.tx_sts);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"rx[rate:%s/busy_level:%d/sts:0x%x/drop:%d]",
id_to_str(BTC_STR_RATE, (u32)t.rx_rate),
t.rx_lvl, t.rx_sts, plink->rx_rate_drop_cnt);
}
}
static void _show_wl_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &cx->wl;
struct btc_wl_role_info *wl_rinfo = &wl->role_info;
if (!(btc->dm.coex_info_map & BTC_COEX_INFO_WL))
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r========== [WL Status] ==========");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : link_mode:%s, mrole:%s, ",
"[status]",
id_to_str(BTC_STR_WLLINK, (u32)wl_rinfo->link_mode),
id_to_str(BTC_STR_MROLE, wl_rinfo->mrole_type));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"rf_off:%s, power_save:%d, init_ok:%s, nhm:%d(status=%d, ratio:%d)",
(wl->status.map.rf_off? "Y" : "N"),
wl->status.map.lps,
(wl->status.map.init_ok? "Y" : "N"),
wl->nhm.pwr,
wl->nhm.current_status, wl->nhm.ratio);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : scan:%s(band:%d/phy_map:0x%x), connecting:%s, roam:%s, 4way:%s",
"[scan]", (wl->status.map.scan? "Y" : "N"),
wl->scan_info.band[HW_PHY_0], wl->scan_info.phy_map,
(wl->status.map.connecting? "Y" : "N"),
(wl->status.map.roaming? "Y" : "N"),
(wl->status.map._4way? "Y" : "N"));
_show_wl_role_info(btc, used, input, input_num, output, out_len);
}
static void _show_dm_step(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_dm *dm = &btc->dm;
u32 n_begin = 0, n_end = 0, i = 0, cnt = 0;
u32 step_cnt = dm->dm_step.cnt;
if (step_cnt == 0)
return;
if (step_cnt <= BTC_DM_MAXSTEP)
n_begin = 1;
else
n_begin = step_cnt - BTC_DM_MAXSTEP + 1;
n_end = step_cnt;
if (n_begin > n_end)
return;
for (i = n_begin; i <= n_end; i++) {
if (cnt % 6 == 0)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : ", "[dm_steps]");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"-> %s", dm->dm_step.step[(i-1) % BTC_DM_MAXSTEP]);
cnt++;
}
}
static void _show_bt_profile_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info;
struct btc_bt_hfp_desc hfp = bt_linfo->hfp_desc;
struct btc_bt_hid_desc hid = bt_linfo->hid_desc;
struct btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc;
struct btc_bt_pan_desc pan = bt_linfo->pan_desc;
if (hfp.exist) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : type:%s, sut_pwr:%d, golden-rx:%d",
"[HFP]",
(hfp.type == 0? "SCO" : "eSCO"),
bt_linfo->sut_pwr_level[0],
bt_linfo->golden_rx_shift[0]);
}
if (hid.exist) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : type:%s%s%s%s%s pair-cnt:%d, sut_pwr:%d, golden-rx:%d",
"[HID]",
(hid.type & BTC_HID_218? "2/18," : ""),
(hid.type & BTC_HID_418? "4/18," : ""),
(hid.type & BTC_HID_BLE? "BLE," : ""),
(hid.type & BTC_HID_RCU? "RCU," : ""),
(hid.type & BTC_HID_RCU_VOICE? "RCU-Voice," : ""),
hid.pair_cnt, bt_linfo->sut_pwr_level[1],
bt_linfo->golden_rx_shift[1]);
}
if (a2dp.exist) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : type:%s, bit-pool:%d, flush-time:%d, ",
"[A2DP]",
(a2dp.type == BTC_A2DP_LEGACY ? "Legacy" : "TWS"),
a2dp.bitpool, a2dp.flush_time);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"vid:0x%x, Dev-name:0x%x, sut_pwr:%d, golden-rx:%d",
a2dp.vendor_id, a2dp.device_name,
bt_linfo->sut_pwr_level[2],
bt_linfo->golden_rx_shift[2]);
}
if (pan.exist) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : sut_pwr:%d, golden-rx:%d",
"[PAN]",
bt_linfo->sut_pwr_level[3],
bt_linfo->golden_rx_shift[3]);
}
}
static void _show_bt_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_cx *cx = &btc->cx;
struct btc_bt_info *bt = &cx->bt;
struct btc_wl_info *wl = &cx->wl;
struct btc_module *module = &btc->mdinfo;
struct btc_bt_link_info *bt_linfo = &bt->link_info;
u8 *afh = bt_linfo->afh_map;
u16 polt_cnt = 0;
if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT))
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"%s", "\n\r========== [BT Status] ==========");
/*bt->btg_type = (bt->ver_info.fw & BIT(28) ? BTC_BT_BTG: BTC_BT_ALONE);*/
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : enable:%s, btg:%s%s, connect:%s, ",
"[status]", (bt->enable.now? "Y" : "N"),
(bt->btg_type? "Y" : "N"),
(bt->enable.now && (bt->btg_type != module->bt_pos)?
"(efuse-mismatch!!)" : ""),
(bt_linfo->status.map.connect? "Y" : "N"));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"igno_wl:%s, mailbox_avl:%s, rfk_state:0x%x",
(bt->igno_wl? "Y" : "N"),
(bt->mbx_avl? "Y" : "N"), bt->rfk_info.val);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : profile:%s%s%s%s%s ",
"[profile]",
((bt_linfo->profile_cnt.now == 0) ? "None," : ""),
(bt_linfo->hfp_desc.exist? "HFP," : ""),
(bt_linfo->hid_desc.exist? "HID," : ""),
(bt_linfo->a2dp_desc.exist?
(bt_linfo->a2dp_desc.sink ? "A2DP_sink," :"A2DP,") : ""),
(bt_linfo->pan_desc.exist? "PAN," : ""));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"multi-link:%s, role:%s, ble-connect:%s, CQDDR:%s, A2DP_active:%s, PAN_active:%s",
(bt_linfo->multi_link.now? "Y" : "N"),
(bt_linfo->slave_role ? "Slave" : "Master"),
(bt_linfo->status.map.ble_connect? "Y" : "N"),
(bt_linfo->cqddr? "Y" : "N"),
(bt_linfo->a2dp_desc.active? "Y" : "N"),
(bt_linfo->pan_desc.active? "Y" : "N"));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : rssi:%ddBm, tx_rate:%dM, %s%s%s%s",
"[link]", bt_linfo->rssi-100,
(bt_linfo->tx_3M? 3 : 2),
(bt->pag? " paging!!" : ""),
(bt->inq? " inquirying!!" : ""),
(bt_linfo->status.map.acl_busy? " acl_busy!!" : ""),
(bt_linfo->status.map.mesh_busy? " mesh_busy!!" : ""));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"%s afh_map[%02x%02x_%02x%02x_%02x%02x_%02x%02x_%02x%02x], ",
(bt_linfo->relink.now? " ReLink!!" : ""),
afh[0], afh[1], afh[2], afh[3], afh[4],
afh[5], afh[6], afh[7], afh[8], afh[9]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"wl_ch_map[en:%d/ch:%d/bw:%d]",
wl->afh_info.en, wl->afh_info.ch, wl->afh_info.bw);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : retry:%d, relink:%d, rate_chg:%d, reinit:%d, reenable:%d, ",
"[stat_cnt]", cx->cnt_bt[BTC_BCNT_RETRY],
cx->cnt_bt[BTC_BCNT_RELINK],
cx->cnt_bt[BTC_BCNT_RATECHG],
cx->cnt_bt[BTC_BCNT_REINIT],
cx->cnt_bt[BTC_BCNT_REENABLE]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"role-switch:%d, afh:%d, inq_page:%d(inq:%d/page:%d), igno_wl:%d",
cx->cnt_bt[BTC_BCNT_ROLESW],
cx->cnt_bt[BTC_BCNT_AFH],
cx->cnt_bt[BTC_BCNT_INQPAG],
cx->cnt_bt[BTC_BCNT_INQ],
cx->cnt_bt[BTC_BCNT_PAGE],
cx->cnt_bt[BTC_BCNT_IGNOWL]);
_show_bt_profile_info(btc, used, input, input_num, output, out_len);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)",
"[bt_info]",
bt->raw_info[2], bt->raw_info[3],
bt->raw_info[4], bt->raw_info[5],
bt->raw_info[6], bt->raw_info[7],
(bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply"),
cx->cnt_bt[BTC_BCNT_INFOUPDATE],
cx->cnt_bt[BTC_BCNT_INFOSAME]);
/* To avoid I/O if WL LPS or power-off */
if (wl->status.map.lps == 1 || wl->status.map.rf_off)
return;
btc->chip->ops->update_bt_cnt(btc);
_chk_btc_err(btc, BTC_DCNT_BTCNT_FREEZE, 0);
rtw_hal_mac_get_bt_polt_cnt(btc->hal, HW_PHY_0, &polt_cnt);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)",
"[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX],
cx->cnt_bt[BTC_BCNT_HIPRI_TX],
cx->cnt_bt[BTC_BCNT_LOPRI_RX],
cx->cnt_bt[BTC_BCNT_LOPRI_TX],
polt_cnt);
}
static void _show_fbtc_tdma(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct fbtc_tdma *t = NULL;
pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo;
if (!pcinfo->valid)
return;
t = &pfwinfo->rpt_fbtc_tdma.finfo.tdma;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : ", "[tdma_policy]");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"type:%s, rx_flow_ctrl:%d, tx_flow_ctrl:%d, ",
id_to_str(BTC_STR_TDMA, (u32)t->type),
t->rxflctrl, t->txflctrl);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"wl_toggle_n:%d, leak_n:%d, ext_ctrl:%d, null_role:0x%x, ",
t->wtgle_n, t->leak_n, t->ext_ctrl, t->rxflctrl_role);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"policy_type:%s",
id_to_str(BTC_STR_POLICY, (u32)btc->policy_type));
}
static void _show_dm_info(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_module *module = &btc->mdinfo;
struct btc_dm *dm = &btc->dm;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
if (!(dm->coex_info_map & BTC_COEX_INFO_DM))
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r========== [Mechanism Status %s] ==========",
(btc->ctrl.manual? "(Manual)":"(Auto)"));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : type:%s, reason:%s(), action:%s(), ant_path:%s, run_cnt:%d",
"[status]",
(module->ant.type == BTC_ANT_SHARED ? "shared" : "dedicated"),
dm->run_reason, dm->run_action,
id_to_str(BTC_STR_ANTPATH, dm->set_ant_path & 0xff),
dm->cnt_dm[BTC_DCNT_RUN]);
_show_fbtc_tdma(btc, used, input, input_num, output, out_len);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : wl_only:%d, bt_only:%d, igno_bt:%d, free_run:%d, wl_ps_ctrl:%d, ",
"[dm_flag]", dm->wl_only, dm->bt_only, btc->ctrl.igno_bt,
dm->freerun, btc->hal->btc_ctrl.lps);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"leak_ap:%d, fw_offload:%s%s, error_map:0x%x", dm->leak_ap,
(BTC_CX_FW_OFFLOAD? "Y" : "N"),
(dm->error.map.offload_mismatch?
"(Mis-Match!!)" : ""), dm->error.val);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : wl_tx_limit[en:%d/max_t:%dus/max_retry:%d], bt_slot_req:%d-TU, bt_scan_rx_low_pri:%d",
"[dm_drv_ctrl]", dm->wl_tx_limit.enable, dm->wl_tx_limit.tx_time,
dm->wl_tx_limit.tx_retry, btc->bt_req_len, bt->scan_rx_low_pri);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : wl[rssi_lvl:%d/para_lvl:%d/tx_pwr:%d/rx_lvl:%d/_btg_rx:%d/stb_chg:%d] ",
"[dm_rf_ctrl]", wl->rssi_level, dm->trx_para_level,
dm->rf_trx_para.wl_tx_power, dm->rf_trx_para.wl_rx_gain,
dm->wl_btg_rx, dm->wl_stb_chg);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"bt[tx_pwr_dec:%d/rx_lna:%d(%s-tbl)]",
dm->rf_trx_para.bt_tx_power, dm->rf_trx_para.bt_rx_gain,
(bt->hi_lna_rx? "Hi" : "Ori"));
_show_dm_step(btc, used, input, input_num, output, out_len);
}
static void _show_mreg(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct fbtc_mreg_val *pmreg = NULL;
struct fbtc_gpio_dbg *gdbg = NULL;
struct rtw_hal_com_t *h = btc->hal;
struct btc_cx *cx = &btc->cx;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_gnt_ctrl gnt[2] = {0};
u8 i = 0, type = 0, cnt = 0;
u32 val, offset;
if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG))
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r========== [HW Status] ==========");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)",
"[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE],
bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD],
cx->cnt_bt[BTC_BCNT_SCBDUPDATE]);
/* To avoid I/O if WL LPS or power-off */
if (wl->status.map.lps != 1 && !wl->status.map.rf_off) {
rtw_hal_mac_get_grant(h, (u8*)gnt);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : pta_owner:%s, pta_req_mac:MAC%d, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d/polut_type:%s]",
"[gnt_status]",
(_read_cx_ctrl(btc) == BTC_CTRL_BY_WL? "WL" : "BT"),
wl->pta_req_mac,
(gnt[0].gnt_wl_sw_en? "SW" : "HW"), gnt[0].gnt_wl,
(gnt[0].gnt_bt_sw_en? "SW" : "HW"), gnt[0].gnt_bt,
id_to_str(BTC_STR_POLUT, wl->bt_polut_type[HW_PHY_0]));
if (h->dbcc_en)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" ,phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d/polut_type:%s]",
(gnt[1].gnt_wl_sw_en? "SW" : "HW"),
gnt[1].gnt_wl,
(gnt[1].gnt_bt_sw_en? "SW" : "HW"),
gnt[1].gnt_bt,
id_to_str(BTC_STR_POLUT,
wl->bt_polut_type[HW_PHY_1]));
}
pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo;
if (!pcinfo->valid)
return;
pmreg = &pfwinfo->rpt_fbtc_mregval.finfo;
for (i = 0; i < pmreg->reg_num; i++) {
type = (u8)btc->chip->mon_reg[i].type;
offset = btc->chip->mon_reg[i].offset;
val = pmreg->mreg_val[i];
if (cnt % 6 == 0)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : %s_0x%x=0x%x",
"[reg]",
id_to_str(BTC_STR_REG, (u32)type),
offset, val);
else
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", %s_0x%x=0x%x",
id_to_str(BTC_STR_REG, (u32)type),
offset, val);
cnt++;
}
pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo;
if (!pcinfo->valid)
return;
gdbg = &pfwinfo->rpt_fbtc_gpio_dbg.finfo;
if (!gdbg->en_map)
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : enable_map:0x%08x",
"[gpio_dbg]", gdbg->en_map);
for (i = 0; i < BTC_DBG_MAX1; i++) {
if (!(gdbg->en_map & BIT(i)))
continue;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", %s->GPIO%d",
id_to_str(BTC_STR_GDBG, (u32)i),
gdbg->gpio_map[i]);
}
}
static void _show_summary(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct fbtc_rpt_ctrl *prptctrl = NULL;
struct btc_cx *cx = &btc->cx;
struct btc_dm *dm = &btc->dm;
struct btc_wl_info *wl = &cx->wl;
u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify;
u8 i;
if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY))
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"%s", "\n\r========== [Statistics] ==========");
pcinfo = &pfwinfo->rpt_ctrl.cinfo;
if (pcinfo->valid && wl->status.map.lps != 1 && !wl->status.map.rf_off) {
prptctrl = &pfwinfo->rpt_ctrl.finfo;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d, len:%d, max:%d), ",
"[summary]", pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail,
prptctrl->rpt_info.cnt_h2c, pfwinfo->cnt_c2h,
prptctrl->rpt_info.cnt_c2h, prptctrl->rpt_info.len_c2h,
RTW_PHL_BTC_FWINFO_BUF);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"rpt_cnt=%d(fw_send:%d), rpt_map=0x%x",
pfwinfo->event[BTF_EVNT_RPT], prptctrl->rpt_info.cnt,
prptctrl->rpt_info.en);
_chk_btc_err(btc, BTC_DCNT_RPT_FREEZE,
pfwinfo->event[BTF_EVNT_RPT]);
if (dm->error.map.wl_fw_hang)
BTC_CNSL(out_len, *used, output + *used,
out_len - *used, " (WL FW Hang!!)");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : send_ok:%d, send_fail:%d, recv:%d, ",
"[mailbox]", prptctrl->bt_mbx_info.cnt_send_ok,
prptctrl->bt_mbx_info.cnt_send_fail,
prptctrl->bt_mbx_info.cnt_recv);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"A2DP_empty:%d(stop:%d/tx:%d/ack:%d/nack:%d)",
prptctrl->bt_mbx_info.a2dp.cnt_empty,
prptctrl->bt_mbx_info.a2dp.cnt_flowctrl,
prptctrl->bt_mbx_info.a2dp.cnt_tx,
prptctrl->bt_mbx_info.a2dp.cnt_ack,
prptctrl->bt_mbx_info.a2dp.cnt_nack);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : wl_rfk[req:%d/go:%d/reject:%d/timeout:%d]",
"[RFK]", cx->cnt_wl[BTC_WCNT_RFK_REQ],
cx->cnt_wl[BTC_WCNT_RFK_GO],
cx->cnt_wl[BTC_WCNT_RFK_REJECT],
cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", bt_rfk[req:%d/go:%d/reject:%d/timeout:%d/fail:%d]",
prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REQ],
prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_GO],
prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REJECT],
prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT],
prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_FAIL]);
} else {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d",
"[summary]", pfwinfo->cnt_h2c,
pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" WL FW rpt error!!(valid=%d, lps=%d, rf_off=%d)",
pcinfo->valid, wl->status.map.lps,
wl->status.map.rf_off);
}
for (i = 0; i < BTC_NCNT_MAX; i++)
cnt_sum += dm->cnt_notify[i];
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ",
"[notify_cnt]", cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO],
cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d",
cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE],
cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK],
cnt[BTC_NCNT_WL_STA]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ",
"[notify_cnt]", cnt[BTC_NCNT_SCAN_START],
cnt[BTC_NCNT_SCAN_FINISH], cnt[BTC_NCNT_SWITCH_BAND],
cnt[BTC_NCNT_SPECIAL_PACKET]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"timer=%d, control=%d, customerize=%d, hub_msg=%d",
cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL],
cnt[BTC_NCNT_CUSTOMERIZE], btc->hubmsg_cnt);
}
static void _show_error(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct fbtc_cysta *pcysta = NULL;
pcysta = &pfwinfo->rpt_fbtc_cysta.finfo;
if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW] == 0 &&
pcysta->except_cnt == 0 &&
!pfwinfo->len_mismch && !pfwinfo->fver_mismch)
return;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : ", "[error]");
if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"overflow-cnt: %d, ",
pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]);
}
if (pfwinfo->len_mismch) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"len-mismatch: 0x%x, ",
pfwinfo->len_mismch);
}
if (pfwinfo->fver_mismch) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"fver-mismatch: 0x%x, ",
pfwinfo->fver_mismch);
}
/* cycle statistics exceptions */
if (pcysta->except_map || pcysta->except_cnt) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"exception-type: 0x%x, exception-cnt = %d",
pcysta->except_map, pcysta->except_cnt);
}
}
static void _show_fbtc_slots(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_dm *dm = &btc->dm;
struct fbtc_slot s;
u8 i = 0;
for (i = 0; i < CXST_MAX; i++) {
s = dm->slot_now[i];
if (i % 5 == 0)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : %s[%d/0x%x/%d]",
"[slot_list]",
id_to_str(BTC_STR_SLOT, (u32)i),
s.dur, s.cxtbl, s.cxtype);
else
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", %s[%d/0x%x/%d]",
id_to_str(BTC_STR_SLOT, (u32)i),
s.dur, s.cxtbl, s.cxtype);
}
}
static void _show_fbtc_cysta(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct btc_dm *dm = &btc->dm;
struct btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct fbtc_cysta *pcysta = NULL;
u8 i, cnt = 0, slot_pair, divide_cnt = 12;
u16 cycle, c_begin, c_end, s_id;
pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo;
if (!pcinfo->valid)
return;
pcysta = &pfwinfo->rpt_fbtc_cysta.finfo;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]",
"[slot_cnt]", pcysta->bcn_cnt[CXBCN_ALL],
pcysta->bcn_cnt[CXBCN_ALL_OK], pcysta->bcn_cnt[CXBCN_BT_SLOT],
pcysta->bcn_cnt[CXBCN_BT_OK]);
for (i = 0; i < CXST_MAX; i++) {
if (!pcysta->slot_cnt[i])
continue;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", %s:%d",
id_to_str(BTC_STR_SLOT, (u32)i),
pcysta->slot_cnt[i]);
}
if (dm->tdma_now.rxflctrl) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", leak_rx:%d", pcysta->leak_slot.cnt_rximr);
}
if (pcysta->collision_cnt) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", collision:%d", pcysta->collision_cnt);
}
if (pcysta->skip_cnt) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", skip:%d", pcysta->skip_cnt);
}
_chk_btc_err(btc, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]);
_chk_btc_err(btc, BTC_DCNT_B1_FREEZE, pcysta->slot_cnt[CXST_B1]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : cycle:%d, avg_t[wl:%d/bt:%d/lk:%d.%03d]",
"[cycle_time]",
pcysta->cycles,
pcysta->cycle_time.tavg[CXT_WL],
pcysta->cycle_time.tavg[CXT_BT],
pcysta->leak_slot.tavg/1000, pcysta->leak_slot.tavg%1000);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", max_t[wl:%d/bt:%d/lk:%d.%03d]",
pcysta->cycle_time.tmax[CXT_WL],
pcysta->cycle_time.tmax[CXT_BT],
pcysta->leak_slot.tamx/1000, pcysta->leak_slot.tamx%1000);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", maxdiff_t[wl:%d/bt:%d]",
pcysta->cycle_time.tmaxdiff[CXT_WL],
pcysta->cycle_time.tmaxdiff[CXT_BT]);
_chk_btc_err(btc, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles);
if (a2dp->exist) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : a2dp_ept:%d, a2dp_late:%d",
"[a2dp_t_sta]",
pcysta->a2dp_ept.cnt, pcysta->a2dp_ept.cnt_timeout);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
", avg_t:%d, max_t:%d",
pcysta->a2dp_ept.tavg, pcysta->a2dp_ept.tmax);
}
if (pcysta->cycles <= 1)
return;
/* 1 cycle = 1 wl-slot + 1 bt-slot */
slot_pair = BTC_CYCLE_SLOT_MAX/2;
if (pcysta->cycles <= slot_pair)
c_begin = 1;
else
c_begin = pcysta->cycles - slot_pair + 1;
c_end = pcysta->cycles;
if (a2dp->exist)
divide_cnt = 3;
else
divide_cnt = 12;
if (c_begin > c_end)
return;
for (cycle = c_begin; cycle <= c_end; cycle++) {
cnt++;
s_id = ((cycle-1) % slot_pair)*2;
if (cnt % divide_cnt == 1)
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"\n\r %-15s : ", "[cycleT_ermtan]");
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"->b%d", pcysta->slot_step_time[s_id]);
#if 1
if (a2dp->exist)
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"(%d/%d/%dM/%d/%d/%d)",
pcysta->a2dp_trx[s_id].empty_cnt,
pcysta->a2dp_trx[s_id].retry_cnt,
(pcysta->a2dp_trx[s_id].tx_rate ? 3:2),
pcysta->a2dp_trx[s_id].tx_cnt,
pcysta->a2dp_trx[s_id].ack_cnt,
pcysta->a2dp_trx[s_id].nack_cnt);
#endif
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"->w%d", pcysta->slot_step_time[s_id+1]);
#if 1
if (a2dp->exist)
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"(%d/%d/%dM/%d/%d/%d)",
pcysta->a2dp_trx[s_id+1].empty_cnt,
pcysta->a2dp_trx[s_id+1].retry_cnt,
(pcysta->a2dp_trx[s_id+1].tx_rate ? 3:2),
pcysta->a2dp_trx[s_id+1].tx_cnt,
pcysta->a2dp_trx[s_id+1].ack_cnt,
pcysta->a2dp_trx[s_id+1].nack_cnt);
#endif
}
}
static void _show_fbtc_nullsta(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct fbtc_cynullsta *ns = NULL;
u8 i = 0;
if (!btc->dm.tdma_now.rxflctrl)
return;
pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo;
if (!pcinfo->valid)
return;
ns = &pfwinfo->rpt_fbtc_nullsta.finfo;
for (i = CXNULL_STATE_0; i <= CXNULL_STATE_1; i++) {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : ", "[null_status]");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"null-%d", i);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"[Tx:%d/", ns->result[i][CXNULL_TX]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"ok:%d/", ns->result[i][CXNULL_OK]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"late:%d/", ns->result[i][CXNULL_LATE]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"fail:%d/", ns->result[i][CXNULL_FAIL]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"retry:%d/", ns->result[i][CXNULL_RETRY]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"avg_t:%d.%03d/",
ns->tavg[i]/1000, ns->tavg[i]%1000);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"max_t:%d.%03d]",
ns->tmax[i]/1000, ns->tmax[i]%1000);
}
}
static void _show_fbtc_step(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct fbtc_steps *pstep = NULL;
u8 type, val;
u16 diff_t;
u32 i, cnt = 0, n_begin = 0, n_end = 0, array_idx = 0;
PHL_INFO("[BTC], %s(), rpt_en_map=0x%x\n", __func__, pfwinfo->rpt_en_map);
if ((pfwinfo->rpt_en_map & RPT_EN_FW_STEP_INFO) == 0)
return;
pcinfo = &pfwinfo->rpt_fbtc_step.cinfo;
if (!pcinfo->valid)
return;
pstep = &pfwinfo->rpt_fbtc_step.finfo;
if (pcinfo->req_fver != pstep->fver || !pstep->cnt)
return;
if (pstep->cnt <= FCXDEF_STEP)
n_begin = 1;
else
n_begin = pstep->cnt - FCXDEF_STEP + 1;
n_end = pstep->cnt;
if (n_begin > n_end)
return;
/* restore step info by using ring instead of FIFO */
for (i = n_begin; i <= n_end; i++) {
array_idx = (i - 1) % FCXDEF_STEP;
type = pstep->step[array_idx].type;
val = pstep->step[array_idx].val;
diff_t = pstep->step[array_idx].difft;
if (type == CXSTEP_NONE || type >= CXSTEP_MAX)
continue;
if (cnt % 10 == 0)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"\n\r %-15s : ", "[fw_steps]");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"-> %s(%d)", (type == CXSTEP_SLOT?
id_to_str(BTC_STR_SLOT, (u32)val) :
id_to_str(BTC_STR_EVENT, (u32)val)),
diff_t);
cnt++;
}
}
static void _show_fw_dm_msg(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
if (!(btc->dm.coex_info_map & BTC_COEX_INFO_DM))
return;
_show_error(btc, used, input, input_num, output, out_len);
_show_fbtc_slots(btc, used, input, input_num, output, out_len);
_show_fbtc_cysta(btc, used, input, input_num, output, out_len);
_show_fbtc_nullsta(btc, used, input, input_num, output, out_len);
_show_fbtc_step(btc, used, input, input_num, output, out_len);
}
static void _cmd_show(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 show_map = 0xff;
if (input_num > 1)
_os_sscanf(input[1], "%x", &show_map);
btc->dm.coex_info_map = show_map & 0xff;
_show_cx_info(btc, used, input, input_num, output, out_len);
_show_wl_info(btc, used, input, input_num, output, out_len);
_show_bt_info(btc, used, input, input_num, output, out_len);
_show_dm_info(btc, used, input, input_num, output, out_len);
_show_fw_dm_msg(btc, used, input, input_num, output, out_len);
_show_mreg(btc, used, input, input_num, output, out_len);
_show_summary(btc, used, input, input_num, output, out_len);
}
static void _cmd_dbg(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct btc_ops *ops = btc->ops;
u8 buf[8] = {0};
u32 len, n;
u32 val = 0, type = 0, i;
if ((input_num < 3) || (input_num > 10))
goto help;
len = input_num - 1;
_os_sscanf(input[1], "%d", &type);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" test type=%d", type);
buf[0] = (u8)(type & 0xff);
for (n = 2; n <= len; n++) {
_os_sscanf(input[n], "%x", &val);
buf[n-1] = (u8)(val & 0xff);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" para%d=0x%x", n-1, buf[n-1]);
}
BTC_CNSL(out_len, *used, output + *used, out_len - *used, " \n");
switch (type) {
case 0: /* H2C-C2H loopback */
ops->fw_cmd(btc, BTFC_SET, SET_H2C_TEST, buf, (u16)len);
btc->dbg.rb_done = false;
btc->dbg.rb_val = 0xff;
for (i = 0; i < 50; i++) {
if (!btc->dbg.rb_done) {
hal_mdelay(btc->hal, 10);
} else {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
" H2C-C2H loopback data = 0x%x !!\n",
btc->dbg.rb_val);
return;
}
}
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" timeout !!\n");
break;
case 1: /* H2C-mailbox */
ops->fw_cmd(btc, BTFC_SET, SET_H2C_TEST, buf, (u16)len);
break;
case 2: /* bt slot request */
btc->bt_req_len = (u32)buf[1];
hal_btc_send_event(btc, (u8*)&btc->bt_req_len, 4,
BTC_HMSG_SET_BT_REQ_SLOT);
break;
case 3: /* fw_step debug */
if (buf[1] > 0)
hal_btc_fw_en_rpt(btc, RPT_EN_FW_STEP_INFO, 1);
else
hal_btc_fw_en_rpt(btc, RPT_EN_FW_STEP_INFO, 0);
break;
}
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" dbg <type> <para1:8bits> <para2:8bits>... \n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" dbg = 0: H2C-C2H loopback <para1: loopback data>\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" dbg = 1: H2C-mailbox <para1~para8: mailbox data>\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" dbg = 2: slot request for P2P+BT coex <para1: slot length (hex)>\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" dbg = 3: enable fw_step debug <para1:8bits>\n");
return;
}
static void _cmd_wb(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 type = 0, addr = 0, val = 0;
if (input_num < 4)
goto help;
_os_sscanf(input[1], "%d", &type);
_os_sscanf(input[2], "%x", &addr);
_os_sscanf(input[3], "%x", &val);
if (type > 4)
goto help;
_write_bt_reg(btc, (u8)type, (u16)addr, val);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" wb type=%d, addr=0x%x, val=0x%x !! \n", type, addr, val);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" wb <type --- 0:rf, 1:modem, 2:bluewize, 3:vendor, 4:LE> <addr:16bits> <val> \n");
return;
}
static void _cmd_set_coex(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 mode = 0;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%d", &mode);
switch(mode) {
case 0: /* original */
btc->ctrl.manual = 0;
btc->ctrl.always_freerun = 0;
btc->dm.wl_only = 0;
btc->dm.bt_only = 0;
_set_init_info(btc);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL);
_run_coex(btc, __func__);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" recovery original coex mechanism !! \n");
break;
case 1: /* freeze */
btc->ctrl.manual = 1;
hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL);
_run_coex(btc, __func__);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" freeze coex mechanism !! \n");
break;
case 2: /* fix freerun */
btc->ctrl.always_freerun = 1;
hal_btc_fw_set_drv_info(btc, CXDRVINFO_CTRL);
_run_coex(btc, __func__);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" freerun coex mechanism !! \n");
break;
case 3: /* fix wl only */
btc->dm.wl_only = 1;
_set_init_info(btc);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT);
_run_coex(btc, __func__);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" always WL-only coex mechanism!! \n");
break;
case 4: /* fix bt only */
btc->dm.bt_only = 1;
_set_init_info(btc);
hal_btc_fw_set_drv_info(btc, CXDRVINFO_INIT);
_run_coex(btc, __func__);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" always BT-only coex mechanism!! \n");
break;
}
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" mode <val--- 0:original, 1:freeze coex, 2:always-freerun, 3:always-WLonly, 4:always-BTonly> \n");
return;
}
static void _cmd_update_policy(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
hal_btc_fw_set_policy(btc, FC_EXEC, (u16)BTC_CXP_MANUAL<<8, __func__);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" Update tdma/slot policy !! \n");
}
static void _cmd_tdma(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 para1 = 0, para2 = 0;
u8 buf[8] = {0};
if (input_num < 3)
goto help;
_os_sscanf(input[1], "%x", ¶1);
_os_sscanf(input[2], "%x", ¶2);
buf[0] = (u8)((para1 & bMASKB3) >> 24);
buf[1] = (u8)((para1 & bMASKB2) >> 16);
buf[2] = (u8)((para1 & bMASKB1) >> 8);
buf[3] = (u8)(para1 & bMASKB0);
buf[4] = (u8)((para2 & bMASKB3) >> 24);
buf[5] = (u8)((para2 & bMASKB2) >> 16);
buf[6] = (u8)((para2 & bMASKB1) >> 8);
buf[7] = (u8)(para2 & bMASKB0);
if (!hal_btc_fw_set_1tdma(btc, (u16)sizeof(struct fbtc_tdma), buf))
goto help;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set tdma parameters1 type=%s, rxflctrl=0x%x, txflctrl=%d, wtgle_n=%d\n",
id_to_str(BTC_STR_TDMA, (u32)buf[0]), buf[1], buf[2], buf[3]);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set tdma parameters2 leak_n=%d, ext_ctrl=%x, rxflctrl_role=0x%x\n",
buf[4], buf[5], buf[6]);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" tdma <para1:32bits> <para2:32bits>\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" <para1> bit[31:24]-> type --- 0:off, 1:fix, 2:auto, 3:auto2\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[23:19]-> rx_flow_ctrl --- send rx flow ctrl every n*w2b-slot\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[18:16]-> rx_flow_ctrl_type --- type 0:off, 1:null, 2:Qos-null, 3:cts\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[15:8] -> tx_flow_ctrl --- 0:off, 1:on\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[7:0] -> wtgle_n --- toggle coex table every n*w1-slot\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" <para2> bit[31:24]-> leak_n --- enter leak slot every n*w2b-slot\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[23:16]-> ext_ctrl --- 0:off, 1:bcn-early_protect only 2:ext\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[15:8] -> resevrd\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bit[7:0] -> resevrd\n");
return;
}
static void _cmd_slot(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 sid = 0, dur = 0, cx_tbl = 0, cx_type = 0, i;
u32 *tmp32 = NULL;
u8 buf[9] = {0};
if (input_num < 5)
goto help;
_os_sscanf(input[1], "%d", &sid);
_os_sscanf(input[2], "%d", &dur);
_os_sscanf(input[3], "%x", &cx_tbl);
_os_sscanf(input[4], "%d", &cx_type);
buf[0] = (u8) sid;
buf[1] = (u8)(dur & bMASKB0);
buf[2] = (u8)((dur & bMASKB1) >> 8);
tmp32 = (u32 *)&buf[3];
*tmp32 = cx_tbl;
buf[7] = (u8)(cx_type & bMASKB0);
buf[8] = (u8)((cx_type & bMASKB1) >> 8);
if (!hal_btc_fw_set_1slot(btc, (u16)sizeof(struct fbtc_slot)+1, buf))
goto help;
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set slot parameters: slot:%s, duration:%d, table:%08x, type=%s!!\n",
id_to_str(BTC_STR_SLOT, sid), dur, cx_tbl,
(cx_type? "iso" : "mix"));
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" slot <slot_id:8bits> <slot_duration:16bits> <coex_table:32bits> <type:16bits>\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" <slot_id> \n");
for (i = 0; i < CXST_MAX; i++) {
if ((i+1) % 5 == 1)
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
" %d: %s",
i, id_to_str(BTC_STR_SLOT, i));
else
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
", %d: %s", i, id_to_str(BTC_STR_SLOT, i));
if (((i+1) % 5 == 0) || (i == CXST_MAX - 1))
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"\n");
}
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" <slot_duration> unit: ms\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" <coex_table> 32bits coex table\n");
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" <type> BT packet at WL slot 0: allowed, 1: isolated\n");
return;
}
static void _cmd_sig_gdbg_en(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 map = 0, i;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%x", &map);
hal_btc_fw_set_gpio_dbg(btc, CXDGPIO_EN_MAP, map);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" signal to gpio debug map = 0x%08x!!\n", map);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" sig <enable_map:hex/32bits> \n");
for (i = 0; i < BTC_DBG_MAX1; i++) {
if ((i+1) % 8 == 1)
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
" %d: %s",
i, id_to_str(BTC_STR_GDBG, i));
else
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
", %d: %s", i, id_to_str(BTC_STR_GDBG, i));
if (((i+1) % 8 == 0) || (i == BTC_DBG_MAX1 - 1))
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"\n");
}
return;
}
static void _cmd_sgpio_map(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 sig = 0, gpio = 0;
if (input_num < 3)
goto help;
_os_sscanf(input[1], "%d", &sig);
_os_sscanf(input[2], "%d", &gpio);
if ((sig > 31) || (gpio > 7))
goto help;
hal_btc_fw_set_gpio_dbg(btc, CXDGPIO_MUX_MAP, ((gpio << 8) + sig));
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" signal-%s -> gpio-%d\n", id_to_str(BTC_STR_GDBG, sig), gpio);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" gpio <sig:0~31> <gpio:0~7>\n");
return;
}
static void _cmd_wl_tx_power(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 pwr = 0;
u8 is_negative = 0;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%d", &pwr);
if (pwr & BIT(31)) {
pwr = ~pwr + 1;
is_negative = 1;
}
pwr = pwr & bMASKB0;
if ((pwr != 255) && (pwr > 20))
goto help;
if (is_negative)
pwr |= BIT(7);
_set_wl_tx_power(btc, pwr);
if (pwr == 0xff)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set wl tx power level to original!!\n");
else if (is_negative)
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set wl tx power level = -%d dBm!!\n", pwr & 0x7f);
else
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set wl tx power level = +%d dBm!!\n", pwr & 0x7f);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" wpwr <wl_tx_power(dBm): -20dbm ~ +20dBm, 255-> original tx power\n");
return;
}
static void _cmd_wl_rx_lna(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 lna = 0;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%d", &lna);
_set_wl_rx_gain(btc, lna);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set wl rx level = %d!!\n", lna);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" wlna <wl_rx_level: 0~7> \n");
return;
}
static void _cmd_bt_afh_map(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 en = 0, ch = 0, bw = 0;
if (input_num < 4)
goto help;
_os_sscanf(input[1], "%d", &en);
_os_sscanf(input[2], "%d", &ch);
_os_sscanf(input[3], "%d", &bw);
btc->cx.wl.afh_info.en = (u8)en;
btc->cx.wl.afh_info.ch = (u8)ch;
btc->cx.wl.afh_info.bw = (u8)bw;
hal_btc_fw_set_bt(btc, SET_BT_WL_CH_INFO, 3, (u8*)&btc->cx.wl.afh_info);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set bt afh map: en=%d, ch=%d, map=%d!!\n", en, ch, bw);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" afh <en: 0/1> <ch: 0~255> <bw: 0~255>\n");
return;
}
static void _cmd_bt_tx_power(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 pwr = 0;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%d", &pwr);
_set_bt_tx_power(btc, pwr);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" decrease bt tx power level = %d!!\n", pwr);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bpwr <decrease power: 0~255 > \n");
return;
}
static void _cmd_bt_rx_lna(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 lna = 0;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%d", &lna);
if (lna > 7)
goto help;
_set_bt_rx_gain(btc, lna);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set bt rx lna constrain level = %d!!\n", lna);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" blna <lna_constrain: 0~7> \n");
return;
}
static void _cmd_bt_igno_wlan(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 igno = 0;
if (input_num < 2)
goto help;
_os_sscanf(input[1], "%d", &igno);
igno = igno & BIT(0);
_set_bt_ignore_wlan_act(btc, (u8)igno);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set bt ignore wlan = %d!!\n", igno);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" igwl <0: don't ignore wlan, 1: ignore wlan > \n");
return;
}
static void _cmd_set_gnt_wl(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 gwl = 0, phy_map = BTC_PHY_ALL;
if ((input_num != 2) && (input_num != 3))
goto help;
_os_sscanf(input[1], "%d", &gwl);
if (input_num == 3) {
_os_sscanf(input[2], "%d", &phy_map);
phy_map = (phy_map == 0? BTC_PHY_0 : BTC_PHY_1);
}
switch(gwl) {
case 0:
_set_gnt_wl(btc, (u8)phy_map, BTC_GNT_SW_LO);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set gnt_wl = SW-0 (phy_map=0x%x)\n", phy_map);
break;
case 1:
_set_gnt_wl(btc, (u8)phy_map, BTC_GNT_SW_HI);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set gnt_wl = SW-1 (phy_map=0x%x)\n", phy_map);
break;
case 2:
_set_gnt_wl(btc, (u8)phy_map, BTC_GNT_HW);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set gnt_wl = HW-PTA ctrl (phy_map=0x%x)\n", phy_map);
break;
}
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" gwl <0:SW_0, 1:SW_1, 2:HW_PTA> <0:PHY-0, 1:PHY-1, none:All> \n");
return;
}
static void _cmd_set_gnt_bt(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 gbt = 0, phy_map = BTC_PHY_ALL;
if ((input_num != 2) && (input_num != 3))
goto help;
_os_sscanf(input[1], "%d", &gbt);
if (input_num == 3) {
_os_sscanf(input[2], "%d", &phy_map);
phy_map = (phy_map == 0? BTC_PHY_0 : BTC_PHY_1);
}
switch(gbt) {
case 0:
_set_gnt_bt(btc, (u8)phy_map, BTC_GNT_SW_LO);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set gnt_bt = SW-0 (phy_map=0x%x)\n", phy_map);
break;
case 1:
_set_gnt_bt(btc, (u8)phy_map, BTC_GNT_SW_HI);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set gnt_bt = SW-1 (phy_map=0x%x)\n", phy_map);
break;
case 2:
_set_gnt_bt(btc, (u8)phy_map, BTC_GNT_HW);
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" set gnt_bt = HW-PTA ctrl (phy_map=0x%x)\n", phy_map);
break;
}
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" gbt <0:SW_0, 1:SW_1, 2:HW_PTA> <0:PHY-0, 1:PHY-1, none:All> \n");
return;
}
static void _cmd_set_bt_psd(struct btc_t *btc, u32 *used, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 idx = 0, type = 0;
if (input_num < 3)
goto help;
_os_sscanf(input[1], "%d", &idx);
_os_sscanf(input[2], "%d", &type);
_set_bt_psd_report(btc, (u8)idx, (u8)type);
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" bpsd <start_idex, dec-8bit> <report_type, dec-8bit> \n");
return;
}
void _get_wl_nhm_dbm(struct btc_t *btc)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_nhm *wl_nhm = &wl->nhm;
u8 set_result = false;
s8 bw_att_db = 13;
s8 nhm_pwr_dbm = 0;
s8 pwr = 0;
s8 cur_pwr = 0;
u16 save_index = 0;
bool new_data_flag = false;
struct watchdog_nhm_report nhm_rpt = {0};
if (wl->afh_info.bw < CHANNEL_WIDTH_5) {
if (wl->afh_info.bw != CHANNEL_WIDTH_80_80) {
bw_att_db =
13 + 3 * (s8)(wl->afh_info.bw - CHANNEL_WIDTH_20);
} else {
bw_att_db = 13 + 3 * 3;
}
}
rtw_hal_bb_nhm_mntr_result(btc->hal, &nhm_rpt, HW_PHY_0);
set_result = nhm_rpt.ccx_rpt_result;
if (set_result) {
nhm_pwr_dbm = nhm_rpt.nhm_pwr_dbm;
wl_nhm->instant_wl_nhm_dbm = nhm_pwr_dbm;
if (wl_nhm->start_flag == false) {
wl_nhm->start_flag = true;
pwr = nhm_pwr_dbm - bw_att_db;
new_data_flag = true;
} else {
pwr = wl_nhm->pwr;
if (wl_nhm->last_ccx_rpt_stamp !=
nhm_rpt.ccx_rpt_stamp) {
new_data_flag = true;
wl_nhm->current_status = 1; // new data
} else {
wl_nhm->current_status = 2; //duplicated data
}
}
if (new_data_flag) {
wl_nhm->last_ccx_rpt_stamp = nhm_rpt.ccx_rpt_stamp;
cur_pwr = nhm_pwr_dbm - bw_att_db;
wl_nhm->instant_wl_nhm_per_mhz = cur_pwr;
wl_nhm->valid_record_times += 1;
if (wl_nhm->valid_record_times == 0) {
wl_nhm->valid_record_times = 16;
}
save_index = (wl_nhm->valid_record_times + 16 - 1) % 16;
wl_nhm->ratio = nhm_rpt.nhm_ratio;
if (cur_pwr < pwr) {
pwr = cur_pwr;
wl_nhm->refresh = true;
} else {
pwr = (pwr >> 1) + (cur_pwr >> 1);
wl_nhm->refresh = false;
}
wl_nhm->pwr = pwr;
wl_nhm->record_pwr[(save_index & 0xF)] = pwr;
wl_nhm->record_ratio[(save_index & 0xF)] = nhm_rpt.nhm_ratio;
}
}
}
static void _cmd_get_wl_nhm_dbm(struct btc_t *btc, u32 *used,
char input[][MAX_ARGV], u32 input_num,
char *output, u32 out_len)
{
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_wl_nhm *wl_nhm = &wl->nhm;
u16 start_index = 0;
u16 stop_index = 0;
u16 i;
u32 show_record_num = 16;
if (input_num >= 3)
goto help;
_get_wl_nhm_dbm(btc);
_os_sscanf(input[1], "%d", &show_record_num);
if (show_record_num >= 16)
show_record_num = 16;
else if (show_record_num == 0)
show_record_num = 1;
if (wl_nhm->valid_record_times > 0) {
if (wl_nhm->current_status == 0) {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used, "wl nhm failed this time\n");
}
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"nhm_psd = %d dBm/MHz, nhm_ratio = %d, status = %d, "
"valid_record_times = %d\n",
wl_nhm->pwr, wl_nhm->ratio,
wl_nhm->current_status, wl_nhm->valid_record_times);
stop_index = wl_nhm->valid_record_times;
if (wl_nhm->valid_record_times > (u16)show_record_num) {
start_index =
wl_nhm->valid_record_times - (u16)show_record_num;
}
for (i = start_index; i < stop_index; i++) {
if (i == start_index) {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"record_pwr(old->new) = %4d",
wl_nhm->record_pwr[(i + 16) & 0xF]);
} else if (i == (stop_index - 1)) {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used, ", %4d dBm/MHz\n",
wl_nhm->record_pwr[(i + 16) & 0xF]);
} else {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used, ", %4d",
wl_nhm->record_pwr[(i + 16) & 0xF]);
}
}
for (i = start_index; i < stop_index; i++) {
if (i == start_index) {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used,
"record_ratio(old->new) = %4d",
wl_nhm->record_ratio[(i + 16) & 0xF]);
} else if (i == (stop_index - 1)) {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used, ", %4d percent\n",
wl_nhm->record_ratio[(i + 16) & 0xF]);
} else {
BTC_CNSL(out_len, *used, output + *used,
out_len - *used, ", %4d",
wl_nhm->record_ratio[(i + 16) & 0xF]);
}
}
} else {
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
"wl nhm not ready\n");
}
return;
help:
BTC_CNSL(out_len, *used, output + *used, out_len - *used,
" wnhm <last_record_num, dec,1-16, default:16> \n");
return;
}
void halbtc_cmd_parser(struct btc_t *btc, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
u32 used = 0;
u8 id = 0;
u32 i;
u32 array_size = sizeof(halbtc_cmd_i) / sizeof(struct halbtc_cmd_info);
BTC_CNSL(out_len, used, output + used, out_len - used, "\n");
/* Parsing Cmd ID */
if (input_num) {
for (i = 0; i < array_size; i++) {
if (_os_strcmp(halbtc_cmd_i[i].name, input[0]) == 0) {
id = halbtc_cmd_i[i].id;
break;
}
}
}
switch (id) {
case HALBTC_DBG:
_cmd_dbg(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SHOW:
_cmd_show(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_WRITE_BT:
_cmd_wb(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_READ_BT:
_cmd_rb(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SET_COEX:
_cmd_set_coex(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_UPDATE_POLICY:
_cmd_update_policy(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_TDMA:
_cmd_tdma(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SLOT:
_cmd_slot(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SIG_GDBG_EN:
_cmd_sig_gdbg_en(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SGPIO_MAP:
_cmd_sgpio_map(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_WL_TX_POWER:
_cmd_wl_tx_power(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_WL_RX_LNA:
_cmd_wl_rx_lna(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_BT_AFH_MAP:
_cmd_bt_afh_map(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_BT_TX_POWER:
_cmd_bt_tx_power(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_BT_RX_LNA:
_cmd_bt_rx_lna(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_BT_IGNO_WLAN:
_cmd_bt_igno_wlan(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SET_GNT_WL:
_cmd_set_gnt_wl(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SET_GNT_BT:
_cmd_set_gnt_bt(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_SET_BT_PSD:
_cmd_set_bt_psd(btc, &used, input, input_num, output, out_len);
break;
case HALBTC_GET_WL_NHM_DBM:
_cmd_get_wl_nhm_dbm(btc, &used, input, input_num, output, out_len);
break;
default:
BTC_CNSL(out_len, used, output + used, out_len - used,
"command not supported !!\n");
/* fall through */
case HALBTC_HELP:
BTC_CNSL(out_len, used, output + used, out_len - used,
"BTC cmd ==>\n");
for (i = 0; i < array_size - 1; i++)
BTC_CNSL(out_len, used, output + used, out_len - used,
" %s\n", halbtc_cmd_i[i + 1].name);
break;
}
}
s32 halbtc_cmd(struct btc_t *btc, char *input, char *output, u32 out_len)
{
char *token;
u32 argc = 0;
char argv[MAX_ARGC][MAX_ARGV];
do {
token = _os_strsep(&input, ", ");
if (token) {
if (_os_strlen((u8 *)token) <= MAX_ARGV)
_os_strcpy(argv[argc], token);
argc++;
} else {
break;
}
} while (argc < MAX_ARGC);
#if 0
if (argc == 1)
argv[0][_os_strlen((u8 *)argv[0]) - 1] = '\0';
#endif
halbtc_cmd_parser(btc, argv, argc, output, out_len);
return 0;
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_dbg_cmd.c
|
C
|
agpl-3.0
| 62,007
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBTC_DBG_CMD_H_
#define _HALBTC_DBG_CMD_H_
void halbtc_cmd_parser(struct btc_t *btc, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len);
s32 halbtc_cmd(struct btc_t *btc, char *input, char *output, u32 out_len);
void _get_wl_nhm_dbm(struct btc_t *btc);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_dbg_cmd.h
|
C
|
agpl-3.0
| 946
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_BTC_DEF_C_
#include "../hal_headers_le.h"
#include "hal_btc.h"
#include "halbtc_fw.h"
#include "halbtc_action.h"
#ifdef CONFIG_BTCOEX
#define case_role(src) \
case PHL_RTYPE_##src: return #src
#define case_mrole(src) \
case BTC_WLMROLE_##src: return #src
#define case_slot(src) \
case CXST_##src: return #src
#define case_reg(src) \
case REG_##src: return #src
#define case_tdma(src) \
case CXTDMA_##src: return #src
#define case_trace(src) \
case CXSTEP_##src: return #src
#define case_branch(src) \
case BTC_BRANCH_##src: return #src
#define case_rxflctrl_(src) \
case CXFLC_##src: return #src
#define case_wllink(src) \
case BTC_WLINK_##src: return #src
#define case_antpath(src) \
case BTC_ANT_##src: return #src
#define case_gdbg(src) \
case BTC_DBG_##src: return #src
#define case_chip(src) \
case CHIP_##src: return #src
#define case_event(src) \
case CXEVNT_##src: return #src
#define case_wlmode(src) \
case WLAN_MD_##src: return #src
#define case_wlbw(src) \
case CHANNEL_WIDTH_##src: return #src
#define case_cxp(src) \
case BTC_CXP_##src: return #src
#define case_rftype(src) \
case RF_##src: return #src
#define case_mstate(src) \
case MLME_##src: return #src
#define case_rate(src) \
case RTW_DATA_RATE_##src: return #src
#define case_polut(src) \
case BTC_PLT_##src: return #src
const char *id_to_str(u8 type, u32 id)
{
switch(type) {
case BTC_STR_ROLE:
switch (id) {
case_role(NONE);
case_role(STATION);
case_role(AP);
case_role(VAP);
case_role(ADHOC);
case_role(ADHOC_MASTER);
case_role(MESH);
case_role(MONITOR);
case_role(P2P_DEVICE);
case_role(P2P_GC);
case_role(P2P_GO);
case_role(NAN);
}
break;
case BTC_STR_MROLE:
switch (id) {
case_mrole(NONE);
case_mrole(STA_GC);
case_mrole(STA_GC_NOA);
case_mrole(STA_GO);
case_mrole(STA_GO_NOA);
case_mrole(STA_STA);
}
break;
case BTC_STR_SLOT:
switch (id) {
case_slot(OFF);
case_slot(B2W);
case_slot(W1);
case_slot(W2);
case_slot(W2B);
case_slot(B1);
case_slot(B2);
case_slot(B3);
case_slot(B4);
case_slot(LK);
case_slot(BLK);
case_slot(E2G);
case_slot(E5G);
case_slot(EBT);
case_slot(ENULL);
case_slot(WLK);
case_slot(W1FDD);
case_slot(B1FDD);
}
break;
case BTC_STR_REG:
switch (id) {
case_reg(MAC);
case_reg(BB);
case_reg(RF);
case_reg(BT_RF);
case_reg(BT_MODEM);
case_reg(BT_BLUEWIZE);
case_reg(BT_VENDOR);
case_reg(BT_LE);
}
break;
case BTC_STR_TDMA:
switch (id) {
case_tdma(OFF);
case_tdma(FIX);
case_tdma(AUTO);
case_tdma(AUTO2);
}
break;
case BTC_STR_TRACE:
switch (id) {
case_trace(NONE);
case_trace(EVNT);
case_trace(SLOT);
}
break;
case BTC_STR_BRANCH:
switch (id) {
case_branch(MAIN);
case_branch(HP);
case_branch(LENOVO);
case_branch(HUAWEI);
}
break;
case BTC_STR_RXFLCTRL:
switch (id) {
case_rxflctrl_(OFF);
case_rxflctrl_(NULLP);
case_rxflctrl_(QOSNULL);
case_rxflctrl_(CTS);
}
break;
case BTC_STR_WLLINK:
switch (id) {
case_wllink(NOLINK);
case_wllink(2G_STA);
case_wllink(2G_GO);
case_wllink(2G_GC);
case_wllink(2G_AP);
case_wllink(2G_SCC);
case_wllink(2G_MCC);
case_wllink(25G_MCC);
case_wllink(25G_DBCC);
case_wllink(5G);
case_wllink(2G_NAN);
case_wllink(OTHER);
}
break;
case BTC_STR_ANTPATH:
switch (id) {
case_antpath(WPOWERON);
case_antpath(WINIT);
case_antpath(WONLY);
case_antpath(WOFF);
case_antpath(W2G);
case_antpath(W5G);
case_antpath(W25G);
case_antpath(FREERUN);
case_antpath(WRFK);
case_antpath(BRFK);
}
break;
case BTC_STR_GDBG:
switch (id) {
case_gdbg(GNT_BT);
case_gdbg(GNT_WL);
case_gdbg(BCN_EARLY);
case_gdbg(WL_NULL0);
case_gdbg(WL_NULL1);
case_gdbg(WL_RXISR);
case_gdbg(TDMA_ENTRY);
case_gdbg(A2DP_EMPTY);
case_gdbg(BT_RETRY);
case_gdbg(BT_RELINK);
case_gdbg(SLOT_WL);
case_gdbg(SLOT_BT);
case_gdbg(WL_RFK);
case_gdbg(BT_RFK);
case_gdbg(SLOT_B2W);
case_gdbg(SLOT_W1);
case_gdbg(SLOT_W2);
case_gdbg(SLOT_W2B);
case_gdbg(SLOT_B1);
case_gdbg(SLOT_B2);
case_gdbg(SLOT_B3);
case_gdbg(SLOT_B4);
case_gdbg(SLOT_LK);
case_gdbg(SLOT_E2G);
case_gdbg(SLOT_E5G);
case_gdbg(SLOT_EBT);
case_gdbg(SLOT_ENULL);
case_gdbg(SLOT_WLK);
case_gdbg(SLOT_W1FDD);
case_gdbg(SLOT_B1FDD);
case_gdbg(BT_CHANGE);
}
break;
case BTC_STR_CHIPID:
switch (id) {
case_chip(WIFI6_8852A);
case_chip(WIFI6_8852B);
case_chip(WIFI6_8852C);
}
break;
case BTC_STR_POLUT:
switch (id) {
case_polut(NONE);
case_polut(GNT_BT_TX);
case_polut(GNT_BT_RX);
case_polut(GNT_WL);
case_polut(BT);
case_polut(ALL);
}
break;
case BTC_STR_EVENT:
switch(id) {
case_event(TDMA_ENTRY);
case_event(WL_TMR);
case_event(B1_TMR);
case_event(B2_TMR);
case_event(B3_TMR);
case_event(B4_TMR);
case_event(W2B_TMR);
case_event(B2W_TMR);
case_event(BCN_EARLY);
case_event(A2DP_EMPTY);
case_event(LK_END);
case_event(RX_ISR);
case_event(RX_FC0);
case_event(RX_FC1);
case_event(BT_RELINK);
case_event(BT_RETRY);
case_event(E2G);
case_event(E5G);
case_event(EBT);
case_event(ENULL);
case_event(DRV_WLK);
case_event(BCN_OK);
case_event(BT_CHANGE);
case_event(EBT_EXTEND);
case_event(E2G_NULL1);
}
break;
case BTC_STR_WLMODE:
switch(id) {
case_wlmode(INVALID);
case_wlmode(11B);
case_wlmode(11A);
case_wlmode(11G);
case_wlmode(11N);
case_wlmode(11AC);
case_wlmode(11AX);
case_wlmode(11BG);
case_wlmode(11GN);
case_wlmode(11AN);
case_wlmode(11BN);
case_wlmode(11BGN);
case_wlmode(11BGAC);
case_wlmode(11BGAX);
case_wlmode(11A_AC);
case_wlmode(11A_AX);
case_wlmode(11AGN);
case_wlmode(11ABGN);
case_wlmode(24G_MIX);
case_wlmode(5G_MIX);
case_wlmode(MAX);
}
break;
case BTC_STR_WLBW:
switch(id) {
case_wlbw(20);
case_wlbw(40);
case_wlbw(80);
case_wlbw(160);
case_wlbw(80_80);
case_wlbw(5);
case_wlbw(10);
case_wlbw(MAX);
}
break;
case BTC_STR_RFTYPE:
switch(id) {
case_rftype(1T1R);
case_rftype(1T2R);
case_rftype(2T3R);
case_rftype(2T4R);
case_rftype(3T3R);
case_rftype(3T4R);
case_rftype(4T4R);
}
break;
case BTC_STR_POLICY:
switch(id) {
case_cxp(OFF_BT);
case_cxp(OFF_WL);
case_cxp(OFF_EQ0);
case_cxp(OFF_EQ1);
case_cxp(OFF_EQ2);
case_cxp(OFF_EQ3);
case_cxp(OFF_BWB0);
case_cxp(OFF_BWB1);
case_cxp(OFF_BWB2);
case_cxp(OFFB_BWB0);
case_cxp(OFFE_2GBWISOB);
case_cxp(OFFE_2GISOB);
case_cxp(OFFE_2GBWMIXB);
case_cxp(OFFE_2GBWMIXB2);
case_cxp(OFFE_WL);
case_cxp(FIX_TD3030);
case_cxp(FIX_TD5050);
case_cxp(FIX_TD2030);
case_cxp(FIX_TD4010);
case_cxp(FIX_TD7010);
case_cxp(FIX_TD2060);
case_cxp(FIX_TD3060);
case_cxp(FIX_TD2080);
case_cxp(FIX_TDW1B1);
case_cxp(FIX_TD4010ISO);
case_cxp(PFIX_TD3030);
case_cxp(PFIX_TD5050);
case_cxp(PFIX_TD2030);
case_cxp(PFIX_TD2060);
case_cxp(PFIX_TD3070);
case_cxp(PFIX_TD2080);
case_cxp(PFIX_TDW1B1);
case_cxp(AUTO_TD50B1);
case_cxp(AUTO_TD60B1);
case_cxp(AUTO_TD20B1);
case_cxp(AUTO_TDW1B1);
case_cxp(PAUTO_TD50B1);
case_cxp(PAUTO_TD60B1);
case_cxp(PAUTO_TD20B1);
case_cxp(PAUTO_TDW1B1);
case_cxp(AUTO2_TD3050);
case_cxp(AUTO2_TD3070);
case_cxp(AUTO2_TD5050);
case_cxp(AUTO2_TD6060);
case_cxp(AUTO2_TD2080);
case_cxp(AUTO2_TDW1B4);
case_cxp(PAUTO2_TD3050);
case_cxp(PAUTO2_TD3070);
case_cxp(PAUTO2_TD5050);
case_cxp(PAUTO2_TD6060);
case_cxp(PAUTO2_TD2080);
case_cxp(PAUTO2_TDW1B4);
}
break;
case BTC_STR_MSTATE:
switch(id) {
case_mstate(NO_LINK);
case_mstate(LINKING);
case_mstate(LINKED);
}
break;
case BTC_STR_RATE:
switch(id) {
case_rate(CCK1);
case_rate(CCK2);
case_rate(CCK5_5);
case_rate(CCK11);
case_rate(OFDM6);
case_rate(OFDM9);
case_rate(OFDM12);
case_rate(OFDM18);
case_rate(OFDM24);
case_rate(OFDM36);
case_rate(OFDM48);
case_rate(OFDM54);
case_rate(MCS0);
case_rate(MCS1);
case_rate(MCS2);
case_rate(MCS3);
case_rate(MCS4);
case_rate(MCS5);
case_rate(MCS6);
case_rate(MCS7);
case_rate(MCS8);
case_rate(MCS9);
case_rate(MCS10);
case_rate(MCS11);
case_rate(MCS12);
case_rate(MCS13);
case_rate(MCS14);
case_rate(MCS15);
case_rate(MCS16);
case_rate(MCS17);
case_rate(MCS18);
case_rate(MCS19);
case_rate(MCS20);
case_rate(MCS21);
case_rate(MCS22);
case_rate(MCS23);
case_rate(MCS24);
case_rate(MCS25);
case_rate(MCS26);
case_rate(MCS27);
case_rate(MCS28);
case_rate(MCS29);
case_rate(MCS30);
case_rate(MCS31);
case_rate(VHT_NSS1_MCS0);
case_rate(VHT_NSS1_MCS1);
case_rate(VHT_NSS1_MCS2);
case_rate(VHT_NSS1_MCS3);
case_rate(VHT_NSS1_MCS4);
case_rate(VHT_NSS1_MCS5);
case_rate(VHT_NSS1_MCS6);
case_rate(VHT_NSS1_MCS7);
case_rate(VHT_NSS1_MCS8);
case_rate(VHT_NSS1_MCS9);
case_rate(VHT_NSS2_MCS0);
case_rate(VHT_NSS2_MCS1);
case_rate(VHT_NSS2_MCS2);
case_rate(VHT_NSS2_MCS3);
case_rate(VHT_NSS2_MCS4);
case_rate(VHT_NSS2_MCS5);
case_rate(VHT_NSS2_MCS6);
case_rate(VHT_NSS2_MCS7);
case_rate(VHT_NSS2_MCS8);
case_rate(VHT_NSS2_MCS9);
case_rate(VHT_NSS3_MCS0);
case_rate(VHT_NSS3_MCS1);
case_rate(VHT_NSS3_MCS2);
case_rate(VHT_NSS3_MCS3);
case_rate(VHT_NSS3_MCS4);
case_rate(VHT_NSS3_MCS5);
case_rate(VHT_NSS3_MCS6);
case_rate(VHT_NSS3_MCS7);
case_rate(VHT_NSS3_MCS8);
case_rate(VHT_NSS3_MCS9);
case_rate(VHT_NSS4_MCS0);
case_rate(VHT_NSS4_MCS1);
case_rate(VHT_NSS4_MCS2);
case_rate(VHT_NSS4_MCS3);
case_rate(VHT_NSS4_MCS4);
case_rate(VHT_NSS4_MCS5);
case_rate(VHT_NSS4_MCS6);
case_rate(VHT_NSS4_MCS7);
case_rate(VHT_NSS4_MCS8);
case_rate(VHT_NSS4_MCS9);
case_rate(HE_NSS1_MCS0);
case_rate(HE_NSS1_MCS1);
case_rate(HE_NSS1_MCS2);
case_rate(HE_NSS1_MCS3);
case_rate(HE_NSS1_MCS4);
case_rate(HE_NSS1_MCS5);
case_rate(HE_NSS1_MCS6);
case_rate(HE_NSS1_MCS7);
case_rate(HE_NSS1_MCS8);
case_rate(HE_NSS1_MCS9);
case_rate(HE_NSS1_MCS10);
case_rate(HE_NSS1_MCS11);
case_rate(HE_NSS2_MCS0);
case_rate(HE_NSS2_MCS1);
case_rate(HE_NSS2_MCS2);
case_rate(HE_NSS2_MCS3);
case_rate(HE_NSS2_MCS4);
case_rate(HE_NSS2_MCS5);
case_rate(HE_NSS2_MCS6);
case_rate(HE_NSS2_MCS7);
case_rate(HE_NSS2_MCS8);
case_rate(HE_NSS2_MCS9);
case_rate(HE_NSS2_MCS10);
case_rate(HE_NSS2_MCS11);
case_rate(HE_NSS3_MCS0);
case_rate(HE_NSS3_MCS1);
case_rate(HE_NSS3_MCS2);
case_rate(HE_NSS3_MCS3);
case_rate(HE_NSS3_MCS4);
case_rate(HE_NSS3_MCS5);
case_rate(HE_NSS3_MCS6);
case_rate(HE_NSS3_MCS7);
case_rate(HE_NSS3_MCS8);
case_rate(HE_NSS3_MCS9);
case_rate(HE_NSS3_MCS10);
case_rate(HE_NSS3_MCS11);
case_rate(HE_NSS4_MCS0);
case_rate(HE_NSS4_MCS1);
case_rate(HE_NSS4_MCS2);
case_rate(HE_NSS4_MCS3);
case_rate(HE_NSS4_MCS4);
case_rate(HE_NSS4_MCS5);
case_rate(HE_NSS4_MCS6);
case_rate(HE_NSS4_MCS7);
case_rate(HE_NSS4_MCS8);
case_rate(HE_NSS4_MCS9);
case_rate(HE_NSS4_MCS10);
case_rate(HE_NSS4_MCS11);
case_rate(MAX);
}
break;
}
return "Undefine";
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_def.c
|
C
|
agpl-3.0
| 11,650
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_BTC_DEF_H__
#define __INC_BTC_DEF_H__
const char *id_to_str(u8 type, u32 id);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_def.h
|
C
|
agpl-3.0
| 750
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_BTC_FW_C_
#include "../hal_headers_le.h"
#include "hal_btc.h"
#include "halbtc_fw.h"
#include "halbtc_def.h"
#ifdef CONFIG_BTCOEX
void _chk_btc_err(struct btc_t *btc, u8 type, u32 cnt)
{
struct btc_cx *cx = &btc->cx;
struct btc_dm *dm = &btc->dm;
struct btc_bt_info *bt = &cx->bt;
switch (type) {
case BTC_DCNT_RPT_FREEZE:
if (dm->cnt_dm[BTC_DCNT_RPT] == cnt && btc->fwinfo.rpt_en_map)
dm->cnt_dm[BTC_DCNT_RPT_FREEZE]++;
else
dm->cnt_dm[BTC_DCNT_RPT_FREEZE] = 0;
if (dm->cnt_dm[BTC_DCNT_RPT_FREEZE] >= BTC_CHK_HANG_MAX)
dm->error.map.wl_fw_hang = true;
else
dm->error.map.wl_fw_hang = false;
dm->cnt_dm[BTC_DCNT_RPT] = cnt;
break;
case BTC_DCNT_CYCLE_FREEZE:
if (dm->cnt_dm[BTC_DCNT_CYCLE] == cnt &&
(dm->tdma_now.type != CXTDMA_OFF ||
dm->tdma_now.ext_ctrl == CXECTL_EXT))
dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE]++;
else
dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] = 0;
if (dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] >= BTC_CHK_HANG_MAX)
dm->error.map.cycle_hang = true;
else
dm->error.map.cycle_hang = false;
dm->cnt_dm[BTC_DCNT_CYCLE] = cnt;
break;
case BTC_DCNT_W1_FREEZE:
if (dm->cnt_dm[BTC_DCNT_W1] == cnt &&
dm->tdma_now.type != CXTDMA_OFF)
dm->cnt_dm[BTC_DCNT_W1_FREEZE]++;
else
dm->cnt_dm[BTC_DCNT_W1_FREEZE] = 0;
if (dm->cnt_dm[BTC_DCNT_W1_FREEZE] >= BTC_CHK_HANG_MAX)
dm->error.map.w1_hang = true;
else
dm->error.map.w1_hang = false;
dm->cnt_dm[BTC_DCNT_W1] = cnt;
break;
case BTC_DCNT_B1_FREEZE:
if (dm->cnt_dm[BTC_DCNT_B1] == cnt &&
dm->tdma_now.type != CXTDMA_OFF)
dm->cnt_dm[BTC_DCNT_B1_FREEZE]++;
else
dm->cnt_dm[BTC_DCNT_B1_FREEZE] = 0;
if (dm->cnt_dm[BTC_DCNT_B1_FREEZE] >= BTC_CHK_HANG_MAX)
dm->error.map.b1_hang = true;
else
dm->error.map.b1_hang = false;
dm->cnt_dm[BTC_DCNT_B1] = cnt;
break;
case BTC_DCNT_TDMA_NONSYNC:
if (cnt != 0) /* if tdma not sync between drv/fw */
dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC]++;
else
dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] = 0;
if (dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] >= BTC_CHK_HANG_MAX)
dm->error.map.tdma_no_sync = true;
else
dm->error.map.tdma_no_sync = false;
break;
case BTC_DCNT_SLOT_NONSYNC:
if (cnt != 0) /* if slot not sync between drv/fw */
dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC]++;
else
dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] = 0;
if (dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] >= BTC_CHK_HANG_MAX)
dm->error.map.tdma_no_sync = true;
else
dm->error.map.tdma_no_sync = false;
break;
case BTC_DCNT_BTCNT_FREEZE:
cnt = cx->cnt_bt[BTC_BCNT_HIPRI_RX] +
cx->cnt_bt[BTC_BCNT_HIPRI_TX] +
cx->cnt_bt[BTC_BCNT_LOPRI_RX] +
cx->cnt_bt[BTC_BCNT_LOPRI_TX];
if (cnt == 0)
dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE]++;
else
dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] = 0;
if ((dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX &&
bt->enable.now) || (!dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] &&
!bt->enable.now))
_update_bt_scbd(btc, false);
break;
case BTC_DCNT_WL_SLOT_DRIFT:
if (cnt >= BTC_CHK_WLSLOT_DRIFT_MAX)
dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT]++;
else
dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] = 0;
if (dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] >= BTC_CHK_HANG_MAX)
dm->error.map.wl_slot_drift = true;
else
dm->error.map.wl_slot_drift = false;
break;
case BTC_DCNT_BT_SLOT_DRIFT:
if (cnt >= BTC_CHK_BTSLOT_DRIFT_MAX)
dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT]++;
else
dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] = 0;
if (dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] >= BTC_CHK_HANG_MAX)
dm->error.map.bt_slot_drift = true;
else
dm->error.map.bt_slot_drift = false;
break;
}
}
static void _update_bt_report(struct btc_t *btc, u8 rpt_type, u8* pfinfo)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_bt_info *bt = &btc->cx.bt;
struct btc_bt_link_info *bt_linfo = &bt->link_info;
struct btc_bt_a2dp_desc *a2dp = &bt_linfo->a2dp_desc;
struct fbtc_btver* pver = (struct fbtc_btver*) pfinfo;
struct fbtc_btscan* pscan = (struct fbtc_btscan*) pfinfo;
struct fbtc_btafh* pafh = (struct fbtc_btafh*) pfinfo;
struct fbtc_btdevinfo* pdev = (struct fbtc_btdevinfo*) pfinfo;
switch (rpt_type) {
case BTC_RPT_TYPE_BT_VER:
bt->ver_info.fw = pver->fw_ver;
bt->ver_info.fw_coex = (pver->coex_ver & bMASKB0);
bt->feature = pver->feature;
break;
case BTC_RPT_TYPE_BT_SCAN:
hal_mem_cpy(h, bt->scan_info, pscan->scan, BTC_SCAN_MAX1);
break;
case BTC_RPT_TYPE_BT_AFH:
hal_mem_cpy(h, &bt_linfo->afh_map[0], pafh->afh_l, 4);
hal_mem_cpy(h, &bt_linfo->afh_map[4], pafh->afh_m, 4);
hal_mem_cpy(h, &bt_linfo->afh_map[8], pafh->afh_h, 2);
break;
case BTC_RPT_TYPE_BT_DEVICE:
a2dp->device_name = pdev->dev_name;
a2dp->vendor_id = pdev->vendor_id;
a2dp->flush_time = pdev->flush_time;
break;
default:
break;
}
}
static u32 _chk_btc_report(struct btc_t *btc, struct btf_fwinfo *pfwinfo,
u8 *prptbuf, u32 index)
{
struct btc_dm *dm = &btc->dm;
struct rtw_hal_com_t *hal = btc->hal;
struct btc_rpt_cmn_info *pcinfo = NULL;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_bt_info *bt = &btc->cx.bt;
struct fbtc_rpt_ctrl *prpt = NULL;
struct fbtc_cysta *pcysta = NULL;
u8 rpt_type = 0, *rpt_content = NULL, *pfinfo = NULL;
u16 wl_slot_set = 0;
u32 rpt_len = 0, diff_t, bt_slot_real = 0;
if (!prptbuf) {
pfwinfo->err[BTFRE_INVALID_INPUT]++;
return 0;
}
rpt_type = prptbuf[index];
rpt_len = (prptbuf[index+2] << 8) + prptbuf[index+1];
rpt_content = &prptbuf[index+3];
switch (rpt_type) {
case BTC_RPT_TYPE_CTRL:
pcinfo = &pfwinfo->rpt_ctrl.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_ctrl.finfo);
pcinfo->req_len = sizeof(struct fbtc_rpt_ctrl);
pcinfo->req_fver = FCX_BTCRPT_VER;
pcinfo->rsp_fver = *rpt_content;
break;
case BTC_RPT_TYPE_TDMA:
pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_tdma.finfo);
pcinfo->req_len = sizeof(struct fbtc_1tdma);
pcinfo->req_fver = FCX_TDMA_VER;
break;
case BTC_RPT_TYPE_SLOT:
pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_slots.finfo);
pcinfo->req_len = sizeof(struct fbtc_slots);
pcinfo->req_fver = FCX_SLOT_VER;
break;
case BTC_RPT_TYPE_CYSTA:
pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo);
pcysta = &pfwinfo->rpt_fbtc_cysta.finfo;
pcinfo->req_len = sizeof(struct fbtc_cysta);
pcinfo->req_fver = FCX_CYSTA_VER;
break;
case BTC_RPT_TYPE_STEP:
pcinfo = &pfwinfo->rpt_fbtc_step.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_step.finfo);
pcinfo->req_len = 8 + sizeof(struct fbtc_step) * FCXDEF_STEP;
pcinfo->req_fver = FCX_STEP_VER;
break;
case BTC_RPT_TYPE_NULLSTA:
pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_nullsta.finfo);
pcinfo->req_len = sizeof(struct fbtc_cynullsta);
pcinfo->req_fver = FCX_NULLSTA_VER;
break;
case BTC_RPT_TYPE_MREG:
pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_mregval.finfo);
pcinfo->req_len = sizeof(struct fbtc_mreg_val);
pcinfo->req_fver = FCX_MREG_VER;
break;
case BTC_RPT_TYPE_GPIO_DBG:
pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_gpio_dbg.finfo);
pcinfo->req_len = sizeof(struct fbtc_gpio_dbg);
pcinfo->req_fver = FCX_GPIODBG_VER;
break;
case BTC_RPT_TYPE_BT_VER:
pcinfo = &pfwinfo->rpt_fbtc_btver.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btver.finfo);
pcinfo->req_len = sizeof(struct fbtc_btver);
pcinfo->req_fver = FCX_BTVER_VER;
break;
case BTC_RPT_TYPE_BT_SCAN:
pcinfo = &pfwinfo->rpt_fbtc_btscan.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btscan.finfo);
pcinfo->req_len = sizeof(struct fbtc_btscan);
pcinfo->req_fver = FCX_BTSCAN_VER;
break;
case BTC_RPT_TYPE_BT_AFH:
pcinfo = &pfwinfo->rpt_fbtc_btafh.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btafh.finfo);
pcinfo->req_len = sizeof(struct fbtc_btafh);
pcinfo->req_fver = FCX_BTAFH_VER;
break;
case BTC_RPT_TYPE_BT_DEVICE:
pcinfo = &pfwinfo->rpt_fbtc_btdev.cinfo;
pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btdev.finfo);
pcinfo->req_len = sizeof(struct fbtc_btdevinfo);
pcinfo->req_fver = FCX_BTDEVINFO_VER;
break;
default:
pfwinfo->err[BTFRE_UNDEF_TYPE]++;
return 0;
}
pcinfo->rsp_fver = *rpt_content;
pcinfo->rx_len = rpt_len;
pcinfo->rx_cnt++;
if (rpt_len != pcinfo->req_len) {
if (rpt_type < BTC_RPT_TYPE_MAX)
pfwinfo->len_mismch |= (0x1 << rpt_type);
else
pfwinfo->len_mismch |= BIT31;
pcinfo->valid = 0;
return 0;
} else if (pcinfo->req_fver != pcinfo->rsp_fver) {
if (rpt_type < BTC_RPT_TYPE_MAX)
pfwinfo->fver_mismch |= (0x1 << rpt_type);
else
pfwinfo->fver_mismch |= BIT31;
pcinfo->valid = 0;
return 0;
} else if (!pfinfo || !rpt_content || !pcinfo->req_len) {
pfwinfo->err[BTFRE_EXCEPTION]++;
pcinfo->valid = 0;
return 0;
}
hal_mem_cpy(hal, (void *)pfinfo, (void *)rpt_content, pcinfo->req_len);
pcinfo->valid = 1;
if (rpt_type == BTC_RPT_TYPE_TDMA) {
#if BTC_CX_FW_OFFLOAD /* update tdma_now if fw offload for debug */
_tdma_cpy(&dm->tdma_now, &pfwinfo->rpt_fbtc_tdma.finfo.tdma);
#else
_chk_btc_err(btc, BTC_DCNT_TDMA_NONSYNC,
_tdma_cmp(&dm->tdma_now,
&pfwinfo->rpt_fbtc_tdma.finfo.tdma));
#endif
}
if (rpt_type == BTC_RPT_TYPE_SLOT) {
#if BTC_CX_FW_OFFLOAD /* update slot_now if fw offload for debug */
_slots_cpy(dm->slot_now, pfwinfo->rpt_fbtc_slots.finfo.slot);
#else
_chk_btc_err(btc, BTC_DCNT_SLOT_NONSYNC,
_tdma_cmp(dm->slot_now,
pfwinfo->rpt_fbtc_slots.finfo.slot));
#endif
}
if (rpt_type == BTC_RPT_TYPE_CYSTA &&
pcysta->cycles >= BTC_CYSTA_CHK_PERIOD) {
/* Check Leak-AP */
if (pcysta->slot_cnt[CXST_LK] != 0 &&
pcysta->leak_slot.cnt_rximr != 0 && dm->tdma_now.rxflctrl) {
if (pcysta->slot_cnt[CXST_LK] <
BTC_LEAK_AP_TH * pcysta->leak_slot.cnt_rximr)
dm->leak_ap = 1;
}
/* Check diff time between real WL slot and W1 slot */
if (dm->tdma_now.type != CXTDMA_OFF) {
wl_slot_set = dm->slot_now[CXST_W1].dur;
if (pcysta->cycle_time.tavg[CXT_WL] > wl_slot_set) {
diff_t = pcysta->cycle_time.tavg[CXT_WL] -
wl_slot_set;
_chk_btc_err(btc, BTC_DCNT_WL_SLOT_DRIFT, diff_t);
}
}
/* Check diff time between real BT slot and EBT/E5G slot */
if (dm->tdma_now.type == CXTDMA_OFF &&
dm->tdma_now.ext_ctrl == CXECTL_EXT &&
btc->bt_req_len != 0) {
bt_slot_real = pcysta->cycle_time.tavg[CXT_BT];
if (btc->bt_req_len > bt_slot_real) {
diff_t = btc->bt_req_len - bt_slot_real;
_chk_btc_err(btc, BTC_DCNT_BT_SLOT_DRIFT, diff_t);
}
}
}
if (rpt_type == BTC_RPT_TYPE_CTRL) {
prpt = &pfwinfo->rpt_ctrl.finfo;
btc->fwinfo.rpt_en_map = prpt->rpt_info.en;
wl->ver_info.fw_coex = prpt->wl_fw_info.cx_ver;
wl->ver_info.fw = prpt->wl_fw_info.fw_ver;
dm->wl_fw_cx_offload = !!(prpt->wl_fw_info.cx_offload);
if (dm->wl_fw_cx_offload != BTC_CX_FW_OFFLOAD)
dm->error.map.offload_mismatch = true;
else
dm->error.map.offload_mismatch = false;
if (prpt->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT] > 0)
bt->rfk_info.map.timeout = 1;
else
bt->rfk_info.map.timeout = 0;
dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout;
}
if (rpt_type >= BTC_RPT_TYPE_BT_VER &&
rpt_type <= BTC_RPT_TYPE_BT_DEVICE)
_update_bt_report(btc, rpt_type, pfinfo);
return (rpt_len + BTC_RPT_HDR_SIZE);
}
static void _parse_btc_report(struct btc_t *btc, struct btf_fwinfo *pfwinfo,
u8 *pbuf, u32 buf_len)
{
u32 index = 0, rpt_len = 0;
while (pbuf) {
if (index+2 >= RTW_PHL_BTC_FWINFO_BUF)
break;
/* At least 3 bytes: type(1) & len(2) */
rpt_len = (pbuf[index+2] << 8) + pbuf[index+1];
if ((index + rpt_len + BTC_RPT_HDR_SIZE) > buf_len)
break;
rpt_len = _chk_btc_report(btc, pfwinfo, pbuf, index);
if (!rpt_len)
break;
index += rpt_len;
}
}
static void _append_tdma(struct btc_t *btc, bool force_exec)
{
struct btc_dm *dm = &btc->dm;
struct btf_tlv *tlv = NULL;
struct fbtc_1tdma *v = NULL;
u16 len = btc->policy_len;
if (!force_exec && !_tdma_cmp(&dm->tdma, &dm->tdma_now)) {
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s(): tdma no change!\n",
__func__);
return;
}
tlv = (struct btf_tlv *)&btc->policy[len];
tlv->type = CXPOLICY_TDMA;
tlv->len = sizeof(struct fbtc_1tdma);
v = (struct fbtc_1tdma *)&tlv->val[0];
v->fver = FCX_TDMA_VER;
_tdma_cpy(&v->tdma, &dm->tdma);
btc->policy_len = len + 2 + sizeof(struct fbtc_1tdma);
PHL_INFO("[BTC], %s: type:%d, rxflctrl=%d, txflctrl=%d, wtgle_n=%d, leak_n=%d, ext_ctrl=%d, rxflctrl_role=0x%x\n",
__func__, dm->tdma.type, dm->tdma.rxflctrl, dm->tdma.txflctrl,
dm->tdma.wtgle_n, dm->tdma.leak_n, dm->tdma.ext_ctrl,
dm->tdma.rxflctrl_role);
}
static void _append_slot(struct btc_t *btc, bool force_exec)
{
struct btc_dm *dm = &btc->dm;
struct btf_tlv *tlv = NULL;
struct fbtc_1slot *v = NULL;
u16 len = 0;
u8 i, cnt = 0;
for (i = 0; i < CXST_MAX; i++) {
if (!force_exec && !_slot_cmp(&dm->slot[i], &dm->slot_now[i]))
continue;
len = btc->policy_len;
tlv = (struct btf_tlv *)&btc->policy[len];
tlv->type = CXPOLICY_SLOT;
tlv->len = sizeof(struct fbtc_1slot);
v = (struct fbtc_1slot *)&tlv->val[0];
v->fver = FCX_SLOT_VER;
v->sid = i;
_slot_cpy(&v->slot, &dm->slot[i]);
PHL_INFO("[BTC], %s: slot-%d: dur=%d, table=0x%08x, type=%d\n",
__func__, i,dm->slot[i].dur, dm->slot[i].cxtbl,
dm->slot[i].cxtype);
cnt++;
btc->policy_len = len + 2 + sizeof(struct fbtc_1slot);
}
if (cnt > 0)
PHL_INFO("[BTC], %s: slot update (cnt=%d)!!\n", __func__, cnt);
}
/*
* extern functions
*/
void hal_btc_fw_en_rpt(struct btc_t *btc, u32 rpt_map, u32 rpt_state)
{
struct btc_ops *ops = btc->ops;
struct btf_set_report r = {0};
struct btf_fwinfo* fwinfo = &btc->fwinfo;
u32 val = 0;
u8 en;
if (!ops || !ops->fw_cmd)
return;
en = rpt_state & 0x1;
if (en)
val = fwinfo->rpt_en_map | rpt_map;
else
val = fwinfo->rpt_en_map & (~rpt_map);
if (val == fwinfo->rpt_en_map)
return;
fwinfo->rpt_en_map = val;
r.fver = FCX_BTCRPT_VER;
r.enable = val;
r.para = en;
ops->fw_cmd(btc, BTFC_SET, SET_REPORT_EN, (u8 *)&r, sizeof(r));
}
void hal_btc_fw_set_slots(struct btc_t *btc, u8 num, struct fbtc_slot *s)
{
#if !BTC_CX_FW_OFFLOAD
struct rtw_hal_com_t *h = btc->hal;
struct btc_ops *ops = btc->ops;
struct btf_set_slot_table *tbl = NULL;
u8 *ptr = NULL;
u16 n = 0;
if (!ops || !ops->fw_cmd)
return;
n = (sizeof(struct fbtc_slot) * num) + sizeof(*tbl) - 1;
tbl = hal_mem_alloc(h, n);
if (!tbl)
return;
tbl->fver = FCX_SLOT_VER;
tbl->tbl_num = num;
ptr = &tbl->buf[0];
hal_mem_cpy(h, (void*)ptr, s, num * sizeof(struct fbtc_slot));
ops->fw_cmd(btc, BTFC_SET, SET_SLOT_TABLE, (u8*)tbl, n);
hal_mem_free(h, (void*)tbl, n);
#endif
}
/* set RPT_EN_MREG = 0 to stop 2s monitor timer in WL FW,
* before SET_MREG_TABLE, and set RPT_EN_MREG = 1 after
* SET_MREG_TABLE
*/
void hal_btc_fw_set_monreg(struct btc_t *btc)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_ops *ops = btc->ops;
struct btf_set_mon_reg *monreg = NULL;
u8 n, *ptr = NULL, ulen;
u16 sz = 0;
if (!ops || !ops->fw_cmd)
return;
n = btc->chip->mon_reg_num;
if (n > CXMREG_MAX) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], mon reg count %d > %d\n",
n, CXMREG_MAX);
return;
}
ulen = sizeof(struct fbtc_mreg);
sz = (ulen * n) + sizeof(*monreg) - 1;
monreg = hal_mem_alloc(h, sz);
if (!monreg)
return;
monreg->fver = FCX_MREG_VER;
monreg->reg_num = n;
ptr = &monreg->buf[0];
hal_mem_cpy(h, (void *)ptr, btc->chip->mon_reg, n * ulen);
ops->fw_cmd(btc, BTFC_SET, SET_MREG_TABLE, (u8 *)monreg, sz);
hal_mem_free(h, (void *)monreg, sz);
hal_btc_fw_en_rpt(btc, RPT_EN_MREG, 1);
}
bool hal_btc_fw_set_1tdma(struct btc_t *btc, u16 len, u8 *buf)
{ /* for wlcli manual control */
struct btc_dm *dm = &btc->dm;
if (len != sizeof(struct fbtc_tdma)) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because len != %d\n",
__func__, (int)sizeof(struct fbtc_tdma));
return false;
} else if (buf[0] >= CXTDMA_MAX) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because tdma_type >= %d\n",
__func__, CXTDMA_MAX);
return false;
}
_tdma_cpy(&dm->tdma, buf);
return true;
}
bool hal_btc_fw_set_1slot(struct btc_t *btc, u16 len, u8 *buf)
{ /* for wlcli manual control */
struct btc_dm *dm = &btc->dm;
if (len != sizeof(struct fbtc_slot) + 1) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because len != %d\n",
__func__, (int)sizeof(struct fbtc_slot) + 1);
return false;
} else if (buf[0] >= CXST_MAX) {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): return because slot_id >= %d\n",
__func__, CXST_MAX);
return false;
}
_slot_cpy(&dm->slot[buf[0]], &buf[1]);
return true;
}
bool hal_btc_fw_set_policy(struct btc_t *btc, bool force_exec, u16 policy_type,
const char* action)
{
struct btc_dm *dm = &btc->dm;
struct btc_ops *ops = btc->ops;
if (!ops || !ops->fw_cmd)
return false;
_act_cpy(dm->run_action, (char*)action);
_update_dm_step(btc, action);
_update_dm_step(btc, id_to_str(BTC_STR_POLICY, (u32)policy_type));
btc->policy_len = 0; /* clear length before append */
btc->policy_type = policy_type;
_append_tdma(btc, force_exec);
_append_slot(btc, force_exec);
if (btc->policy_len == 0 || btc->policy_len > BTC_POLICY_MAXLEN)
return false;
PHL_INFO("[BTC], %s(): action=%s -> policy type/len: 0x%04x/%d\n",
__func__, action, policy_type, btc->policy_len);
if (dm->tdma.rxflctrl == CXFLC_NULLP)
btc->hal->btc_ctrl.lps = 1;
else
btc->hal->btc_ctrl.lps = 0;
if (btc->hal->btc_ctrl.lps == 1)
hal_btc_notify_ps_tdma(btc, btc->hal->btc_ctrl.lps);
ops->fw_cmd(btc, BTFC_SET, SET_CX_POLICY, btc->policy, btc->policy_len);
_tdma_cpy(&dm->tdma_now, &dm->tdma);
_slots_cpy(dm->slot_now, dm->slot);
if (btc->hal->btc_ctrl.lps == 0)
hal_btc_notify_ps_tdma(btc, btc->hal->btc_ctrl.lps);
return true;
}
void hal_btc_fw_set_gpio_dbg(struct btc_t *btc, u8 type, u32 val)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_ops *ops = btc->ops;
u8 data[7] = {0}, len = 0;
if (!ops || !ops->fw_cmd || type >= CXDGPIO_MAX)
return;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()\n", __func__);
data[0] = FCX_GPIODBG_VER;
data[1] = 0;
data[2] = type;
switch(type) {
case CXDGPIO_EN_MAP:
len = sizeof(u32) + 3;
hal_mem_cpy(h, &data[3], &val, sizeof(u32));
break;
case CXDGPIO_MUX_MAP:
len = sizeof(8) * 2 + 3;
data[3] = (u8)(val & bMASKB0);
data[4] = (u8)((val & bMASKB1) >> 8);
break;
default:
return;
}
ops->fw_cmd(btc, BTFC_SET, SET_GPIO_DBG, data, len);
}
void hal_btc_fw_set_drv_info(struct btc_t *btc, u8 type)
{
struct rtw_hal_com_t *h = btc->hal;
struct btc_wl_info *wl = &btc->cx.wl;
struct btc_dm *dm = &btc->dm;
struct btc_ops *ops = btc->ops;
u8 buf[256] = {0};
u8 sz = 0, n = 0;
if (!ops || !ops->fw_cmd || type >= CXDRVINFO_MAX)
return;
switch (type) {
case CXDRVINFO_INIT:
n = sizeof(dm->init_info);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_INIT;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &dm->init_info, n);
break;
case CXDRVINFO_ROLE:
n = sizeof(wl->role_info);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_ROLE;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &wl->role_info, n);
break;
case CXDRVINFO_CTRL:
n = sizeof(btc->ctrl);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_CTRL;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &btc->ctrl, n);
break;
case CXDRVINFO_RFK:
n = sizeof(wl->rfk_info);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_RFK;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &wl->rfk_info, n);
break;
#if BTC_CX_FW_OFFLOAD
case CXDRVINFO_DBCC:
n = sizeof(wl->dbcc_info);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_DBCC;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &wl->dbcc_info, n);
break;
case CXDRVINFO_SMAP:
n = sizeof(wl->status);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_SMAP;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &wl->status, n);
break;
case CXDRVINFO_RUN:
n = BTC_RSN_MAXLEN;
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_RUN;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], dm->run_reason, n);
break;
case CXDRVINFO_SCAN:
n = sizeof(wl->scan_info);
sz = n + 2;
if (sz > sizeof(buf))
return;
buf[0] = CXDRVINFO_SCAN;
buf[1] = n;
hal_mem_cpy(h, (void *)&buf[2], &wl->scan_info, n);
break;
#endif
default:
return;
}
ops->fw_cmd(btc, BTFC_SET, SET_DRV_INFO, (u8*)buf, sz);
}
void hal_btc_fw_set_drv_event(struct btc_t *btc, u8 type)
{
struct btc_ops *ops = btc->ops;
if (!ops || !ops->fw_cmd)
return;
ops->fw_cmd(btc, BTFC_SET, SET_DRV_EVENT, &type, 1);
}
void hal_btc_fw_set_bt(struct btc_t *btc, u8 type, u16 len, u8* buf)
{
struct btc_ops *ops = btc->ops;
if (!ops || !ops->fw_cmd ||
(type < SET_BT_WREG_ADDR || type > SET_BT_GOLDEN_RX_RANGE))
return;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "[BTC], %s()\n", __func__);
ops->fw_cmd(btc, BTFC_SET, type, buf, len);
}
void hal_btc_fw_event(struct btc_t *btc, u8 evt_id, void *data, u32 len)
{
struct btf_fwinfo *pfwinfo = &btc->fwinfo;
if (!len || !data)
return;
switch (evt_id) {
case BTF_EVNT_RPT:
_parse_btc_report(btc, pfwinfo, data, len);
break;
default:
break;
}
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_fw.c
|
C
|
agpl-3.0
| 22,126
|
#ifndef __INC_BTC_FW_H__
#define __INC_BTC_FW_H__
#include "halbtc_fwdef.h"
#pragma pack(push)
#pragma pack(1)
struct btc_t;
struct btf_tlv {
u8 type;
u8 len;
u8 val[1];
};
enum btf_reg_type {
REG_MAC = 0x0,
REG_BB = 0x1,
REG_RF = 0x2,
REG_BT_RF = 0x3,
REG_BT_MODEM = 0x4,
REG_BT_BLUEWIZE = 0x5,
REG_BT_VENDOR = 0x6,
REG_BT_LE = 0x7,
REG_MAX_TYPE
};
/*
* h2c_class : 0x10~0x17: BTC
* Please see : struct rtw_g6_h2c_hdr
*/
enum bt_h2c_class {
BTFC_SET = 0x10, /* 0x10~0x17 for BTC */
BTFC_GET = 0x11,
BTFC_FW_EVENT = 0x12,
BTFC_MAX
};
/* =======================================
* BTFC_SET class 0x10 ->function
*/
enum btf_set {
SET_REPORT_EN = 0x0,
SET_SLOT_TABLE, /* Slot table */
SET_MREG_TABLE, /* moniter register */
SET_CX_POLICY,
SET_GPIO_DBG,
SET_DRV_INFO,
SET_DRV_EVENT,
SET_BT_WREG_ADDR,
SET_BT_WREG_VAL,
SET_BT_RREG_ADDR,
SET_BT_WL_CH_INFO,
SET_BT_INFO_REPORT,
SET_BT_IGNORE_WLAN_ACT,
SET_BT_TX_PWR,
SET_BT_LNA_CONSTRAIN,
SET_BT_GOLDEN_RX_RANGE,
SET_BT_PSD_REPORT,
SET_H2C_TEST,
SET_MAX1
};
/* SET_REPORT_EN function 0x0 -> TLV sub-function */
enum btf_set_report_en {
RPT_EN_TDMA = BIT0,
RPT_EN_CYCLE = BIT1,
RPT_EN_MREG = BIT2,
RPT_EN_BT_VER_INFO = BIT3, /* FW, Coex, Feature*/
RPT_EN_BT_SCAN_INFO = BIT4, /* BT scan parameter */
RPT_EN_BT_AFH_MAP = BIT5, /* AFH map H/M/L */
RPT_EN_BT_DEVICE_INFO = BIT6, /* vendor id, device name, flush-val*/
RPT_EN_FW_STEP_INFO = BIT7,
RPT_EN_WL_ALL = 0x7,
RPT_EN_BT_ALL = 0x78,
RPT_EN_ALL = 0x7f
};
/* SET_SLOT_TABLE function 0x1 -> sub-function */
struct btf_set_report {
u8 fver;
u32 enable;
u32 para;
};
struct btf_set_slot_table {
u8 fver;
u8 tbl_num;
u8 buf[1];
};
/* SET_MREG_TABLE function 0x2 -> sub-function */
struct btf_set_mon_reg {
u8 fver;
u8 reg_num;
u8 buf[1];
};
/* SET_CX_POLICY function 0x3 -> TLV sub-function */
enum btf_set_cx_policy {
CXPOLICY_TDMA = 0x0,
CXPOLICY_SLOT = 0x1,
CXPOLICY_TYPE = 0x2,
CXPOLICY_MAX
};
/* SET_GPIO_DBG function 0x4 -> TLV sub-function */
enum {
CXDGPIO_EN_MAP = 0x0,
CXDGPIO_MUX_MAP = 0x1,
CXDGPIO_MAX
};
/* SET_DRV_INFO function 0x5 -> TLV sub-function */
enum {
CXDRVINFO_INIT = 0, /* wl_only, dbcc_en...*/
CXDRVINFO_ROLE, /* Role */
CXDRVINFO_DBCC, /* DBCC */
CXDRVINFO_SMAP, /* status map */
CXDRVINFO_RFK, /* wl rfk info */
CXDRVINFO_RUN, /* wl run reason */
CXDRVINFO_CTRL, /* ctrl info */
CXDRVINFO_SCAN, /* scan info */
CXDRVINFO_MAX
};
/* SET_DRV_EVENT function 0x6 -> TLV sub-function */
enum {
CXDRVEVNT_1 = 0x0,
CXDRVEVNT_2 = 0x1,
CXDRVEVNT_MAX
};
/* =======================================
* BTFC_GET class 0x11 ->function
*/
enum btf_get {
GET_BT_REG,
GET_MAX
};
/* =======================================
* BTFC_FW_EVENT class 0x12 ->function
*/
enum btf_fw_event {
BTF_EVNT_RPT = 0,
BTF_EVNT_BT_INFO = 1,
BTF_EVNT_BT_SCBD = 2,
BTF_EVNT_BT_REG = 3,
BTF_EVNT_CX_RUNINFO = 4,
BTF_EVNT_BT_PSD = 5,
BTF_EVNT_BUF_OVERFLOW,
BTF_EVNT_C2H_LOOPBACK,
BTF_EVNT_MAX
};
struct btf_event {
u8 event;
u8 reserved;
u16 length;
u8 buf[1];
};
/* BTF_EVNT_RPT function 0x0 -> TLV type */
enum btf_fw_event_report {
BTC_RPT_TYPE_CTRL = 0x0,
BTC_RPT_TYPE_TDMA,
BTC_RPT_TYPE_SLOT,
BTC_RPT_TYPE_CYSTA,
BTC_RPT_TYPE_STEP,
BTC_RPT_TYPE_NULLSTA,
BTC_RPT_TYPE_MREG,
BTC_RPT_TYPE_GPIO_DBG,
BTC_RPT_TYPE_BT_VER,
BTC_RPT_TYPE_BT_SCAN,
BTC_RPT_TYPE_BT_AFH,
BTC_RPT_TYPE_BT_DEVICE,
BTC_RPT_TYPE_TEST,
BTC_RPT_TYPE_MAX = 31
};
struct btc_rpt_cmn_info {
u32 rx_cnt;
u32 rx_len;
u32 req_len; /* expected rsp len */
u8 req_fver; /* expected rsp fver */
u8 rsp_fver; /* fver from fw */
u8 valid;
};
#pragma pack(pop)
struct btc_report_ctrl_state {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_rpt_ctrl finfo; /* info from fw */
};
struct btc_fbtc_tdma {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_1tdma finfo; /* info from fw */
};
struct btc_fbtc_slots {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_slots finfo; /* info from fw */
};
struct btc_fbtc_cysta {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_cysta finfo; /* info from fw */
};
struct btc_fbtc_step {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_steps finfo; /* info from fw */
};
struct btc_fbtc_nullsta {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_cynullsta finfo; /* info from fw */
};
struct btc_fbtc_mreg {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_mreg_val finfo; /* info from fw */
};
struct btc_fbtc_gpio_dbg {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_gpio_dbg finfo; /* info from fw */
};
struct btc_fbtc_btver {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_btver finfo; /* info from fw */
};
struct btc_fbtc_btscan {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_btscan finfo; /* info from fw */
};
struct btc_fbtc_btafh {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_btafh finfo; /* info from fw */
};
struct btc_fbtc_btdev {
struct btc_rpt_cmn_info cinfo; /* common info, by driver */
struct fbtc_btdevinfo finfo; /* info from fw */
};
enum {
BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
BTFRE_UNDEF_TYPE,
BTFRE_EXCEPTION,
BTFRE_MAX
};
struct btf_fwinfo {
u32 cnt_c2h; /* total c2h cnt */
u32 cnt_h2c; /* total h2c cnt */
u32 cnt_h2c_fail; /* total h2c fail cnt */
u32 event[BTF_EVNT_MAX]; /* event statistics */
u32 err[BTFRE_MAX]; /* counters for statistics */
u32 len_mismch; /* req/rsp length mis match */
u32 fver_mismch; /* req/rsp fver mis match */
u32 rpt_en_map;
struct btc_report_ctrl_state rpt_ctrl;
struct btc_fbtc_tdma rpt_fbtc_tdma;
struct btc_fbtc_slots rpt_fbtc_slots;
struct btc_fbtc_cysta rpt_fbtc_cysta;
struct btc_fbtc_step rpt_fbtc_step;
struct btc_fbtc_nullsta rpt_fbtc_nullsta;
struct btc_fbtc_mreg rpt_fbtc_mregval;
struct btc_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
struct btc_fbtc_btver rpt_fbtc_btver;
struct btc_fbtc_btscan rpt_fbtc_btscan;
struct btc_fbtc_btafh rpt_fbtc_btafh;
struct btc_fbtc_btdev rpt_fbtc_btdev;
};
/*
* extern functions
*/
void _chk_btc_err(struct btc_t *btc, u8 type, u32 cnt);
void hal_btc_fw_event(struct btc_t *btc, u8 evt_id, void *data, u32 len);
void hal_btc_fw_en_rpt(struct btc_t *btc, u32 rpt_map, u32 rpt_state);
void hal_btc_fw_set_slots(struct btc_t *btc, u8 num, struct fbtc_slot *s);
void hal_btc_fw_set_monreg(struct btc_t *btc);
bool hal_btc_fw_set_1tdma(struct btc_t *btc, u16 len, u8 *buf);
bool hal_btc_fw_set_1slot(struct btc_t *btc, u16 len, u8 *buf);
bool hal_btc_fw_set_policy(struct btc_t *btc, bool force_exec, u16 policy_type,
const char* action);
void hal_btc_fw_set_gpio_dbg(struct btc_t *btc, u8 type, u32 val);
void hal_btc_fw_set_drv_info(struct btc_t *btc, u8 type);
void hal_btc_fw_set_bt(struct btc_t *btc, u8 type, u16 len, u8* buf);
void hal_btc_fw_set_drv_event(struct btc_t *btc, u8 type);
void hal_btc_notify_ps_tdma(struct btc_t *btc, bool tdma_start);
#endif /* __INC_BTC_FW_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_fw.h
|
C
|
agpl-3.0
| 7,161
|
#ifndef __INC_BTC_FW_DEF_H__
#define __INC_BTC_FW_DEF_H__
#pragma pack(push)
#pragma pack(1)
/*
* shared FW Definition
*/
#define CXMREG_MAX 30
#define FCXDEF_STEP 50 /* MUST fw_step size*/
#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
enum btc_bt_rfk_counter {
BTC_BCNT_RFK_REQ = 0,
BTC_BCNT_RFK_GO = 1,
BTC_BCNT_RFK_REJECT = 2,
BTC_BCNT_RFK_FAIL = 3,
BTC_BCNT_RFK_TIMEOUT = 4,
BTC_BCNT_RFK_MAX
};
struct btc_rpt_ctrl_wl_fw_info {
u32 cx_ver; /* match which driver's coex version */
u32 cx_offload;
u32 fw_ver;
};
struct btc_rpt_ctrl_info {
u32 cnt; /* fw report counter */
u32 en; /* report map */
u32 para; /* not used */
u32 cnt_c2h; /* fw send c2h counter */
u32 cnt_h2c; /* fw recv h2c counter */
u32 len_c2h; /* The total length of the last C2H */
};
struct btc_rpt_ctrl_a2dp_empty {
u32 cnt_empty; /* a2dp empty count */
u32 cnt_flowctrl; /* a2dp empty flow control counter */
u32 cnt_tx;
u32 cnt_ack;
u32 cnt_nack;
};
struct btc_rpt_ctrl_bt_mailbox {
u32 cnt_send_ok; /* fw send mailbox ok counter */
u32 cnt_send_fail; /* fw send mailbox fail counter */
u32 cnt_recv; /* fw recv mailbox counter */
struct btc_rpt_ctrl_a2dp_empty a2dp;
};
#define FCX_BTCRPT_VER 2
struct fbtc_rpt_ctrl {
u8 fver;
u8 rsvd;
u16 rsvd1;
struct btc_rpt_ctrl_info rpt_info;
struct btc_rpt_ctrl_wl_fw_info wl_fw_info;
struct btc_rpt_ctrl_bt_mailbox bt_mbx_info;
u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];
};
/*
* ============== TDMA related ==============
*/
enum fbtc_tdma_template {
CXTD_OFF = 0x0,
CXTD_OFF_B2,
CXTD_OFF_EXT,
CXTD_FIX,
CXTD_PFIX,
CXTD_AUTO,
CXTD_PAUTO,
CXTD_AUTO2,
CXTD_PAUTO2,
CXTD_MAX
};
enum fbtc_tdma_type {
CXTDMA_OFF = 0x0, /* tdma off */
CXTDMA_FIX = 0x1, /* fixed slot */
CXTDMA_AUTO = 0x2, /* auto slot */
CXTDMA_AUTO2 = 0x3, /* extended auto slot */
CXTDMA_MAX
};
enum fbtc_tdma_rx_flow_ctrl {
CXFLC_OFF = 0x0, /* rx flow off */
CXFLC_NULLP = 0x1, /* Null/Null-P */
CXFLC_QOSNULL = 0x2, /* QOS Null/Null-P */
CXFLC_CTS = 0x3, /* CTS to Self control */
CXFLC_MAX
};
enum fbtc_tdma_wlan_tx_pause {
CXTPS_OFF = 0x0, /* no wl tx pause*/
CXTPS_ON = 0x1,
CXTPS_MAX
};
/* define if ext-ctrl-slot allowed while TDMA off */
enum fbtc_ext_ctrl_type {
CXECTL_OFF = 0x0, /* tdma off */
CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
CXECTL_EXT = 0x2,
CXECTL_MAX
};
union fbtc_rxflct {
u8 val;
u8 type: 3;
u8 tgln_n: 5;
};
#define FCX_TDMA_VER 2
struct fbtc_tdma {
u8 type; /* refer to fbtc_tdma_type*/
u8 rxflctrl; /* refer to fbtc_tdma_rx_flow_ctrl */
u8 txflctrl; /* If WL stop Tx while enter BT-slot */
u8 wtgle_n; /* wl slot toggle every toggle_n cycles */
u8 leak_n; /* every leak_n cycle do leak detection */
u8 ext_ctrl; /* refer to fbtc_ext_ctrl_type*/
/* send rxflctrl to which role
* enum role_type, default: 0 for single-role
* if multi-role: [7:4] second-role, [3:0] fisrt-role
*/
u8 rxflctrl_role;
u8 rsvd;
};
struct fbtc_1tdma {
u8 fver;
u8 rsvd;
u16 rsvd1;
struct fbtc_tdma tdma;
};
/*
* ============== SLOT related ==============
*/
enum { /* slot */
CXST_OFF = 0x0,
CXST_B2W = 0x1,
CXST_W1 = 0x2,
CXST_W2 = 0x3,
CXST_W2B = 0x4,
CXST_B1 = 0x5,
CXST_B2 = 0x6,
CXST_B3 = 0x7,
CXST_B4 = 0x8,
CXST_LK = 0x9,
CXST_BLK = 0xa,
CXST_E2G = 0xb, /* for ext-control-slot 2G*/
CXST_E5G = 0xc, /* for ext-control-slot 5G*/
CXST_EBT = 0xd, /* for ext-control-slot BT*/
CXST_ENULL = 0xe, /* for ext-control-slot Null*/
CXST_WLK = 0xf, /* for WL link slot */
CXST_W1FDD = 0x10,
CXST_B1FDD = 0x11,
CXST_MAX = 0x12 /* The max slot must be even*/
};
enum {
CXEVNT_TDMA_ENTRY = 0x0,
CXEVNT_WL_TMR,
CXEVNT_B1_TMR,
CXEVNT_B2_TMR,
CXEVNT_B3_TMR,
CXEVNT_B4_TMR,
CXEVNT_W2B_TMR,
CXEVNT_B2W_TMR,
CXEVNT_BCN_EARLY,
CXEVNT_A2DP_EMPTY,
CXEVNT_LK_END,
CXEVNT_RX_ISR,
CXEVNT_RX_FC0,
CXEVNT_RX_FC1,
CXEVNT_BT_RELINK,
CXEVNT_BT_RETRY,
CXEVNT_E2G,
CXEVNT_E5G,
CXEVNT_EBT,
CXEVNT_ENULL,
CXEVNT_DRV_WLK,
CXEVNT_BCN_OK,
CXEVNT_BT_CHANGE,
CXEVNT_EBT_EXTEND,
CXEVNT_E2G_NULL1,
CXEVNT_MAX
};
enum {
CXBCN_ALL = 0x0,
CXBCN_ALL_OK,
CXBCN_BT_SLOT,
CXBCN_BT_OK,
CXBCN_MAX
};
/* Slot isolation Definition
* Same definition as WL RX Definition
*/
enum {
SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
CXSTYPE_MAX
};
enum { /* TIME */
CXT_BT = 0x0,
CXT_WL = 0x1,
CXT_MAX
};
enum { /* TIME-A2DP */
CXT_FLCTRL_OFF = 0x0,
CXT_FLCTRL_ON = 0x1,
CXT_FLCTRL_MAX
};
enum { /* STEP TYPE */
CXSTEP_NONE = 0x0,
CXSTEP_EVNT = 0x1,
CXSTEP_SLOT = 0x2,
CXSTEP_MAX
};
enum {
CXNULL_STATE_0 = 0,
CXNULL_STATE_1 = 1,
CXNULL_STATE_MAX = 2
};
enum {
CXNULL_FAIL = 0,
CXNULL_OK = 1,
CXNULL_LATE = 2,
CXNULL_RETRY = 3,
CXNULL_TX = 4,
CXNULL_MAX = 5
};
struct fbtc_set_drvinfo {
u8 type;
u8 len;
u8 buf[1];
};
#define FCX_GPIODBG_VER 1
#define BTC_DBG_MAX1 32
struct fbtc_gpio_dbg {
u8 fver;
u8 rsvd;
u16 rsvd2;
u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
u32 pre_state; /* the debug signal is 1 or 0 */
u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position mapping */
};
#define FCX_MREG_VER 1
struct fbtc_mreg_val {
u8 fver;
u8 reg_num;
u16 rsvd;
u32 mreg_val[CXMREG_MAX];
};
struct fbtc_mreg {
u16 type;
u16 bytes;
u32 offset;
};
#define FCX_SLOT_VER 1
struct fbtc_slot {
u16 dur; /* slot duration */
u32 cxtbl;
u16 cxtype;
};
struct fbtc_1slot {
u8 fver;
u8 sid; /* slot id */
struct fbtc_slot slot;
};
struct fbtc_slots {
u8 fver;
u8 tbl_num;
u16 rsvd;
u32 update_map;
struct fbtc_slot slot[CXST_MAX];
};
#define FCX_STEP_VER 3
struct fbtc_step {
u8 type;
u8 val;
u16 difft;
};
struct fbtc_steps {
u8 fver;
u8 en;
u16 rsvd;
u32 cnt;
struct fbtc_step step[FCXDEF_STEP];
};
#define FCX_CYSTA_VER 3
struct fbtc_fdd_try_info {
u16 cycles[CXT_FLCTRL_MAX];
u16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
u16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
};
struct fbtc_cycle_time_info {
u16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
u16 tmax[CXT_MAX]; /* max wl/bt cycle time */
u16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
};
struct fbtc_a2dp_trx_stat {
u8 empty_cnt;
u8 retry_cnt;
u8 tx_rate;
u8 tx_cnt;
u8 ack_cnt;
u8 nack_cnt;
u8 rsvd1;
u8 rsvd2;
};
struct fbtc_cycle_a2dp_empty_info {
u16 cnt; /* a2dp empty cnt */
u16 cnt_timeout; /* a2dp empty timeout cnt*/
u16 tavg; /* avg a2dp empty time */
u16 tmax; /* max a2dp empty time */
};
struct fbtc_cycle_leak_info {
u32 cnt_rximr; /* the rximr occur at leak slot */
u16 tavg; /* avg leak-slot time */
u16 tamx; /* max leak-slot time */
};
struct fbtc_cysta { /* statistics for cycles */
u8 fver;
u8 rsvd;
u16 cycles; /* total cycle number */
u16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /*record the wl/bt slot time, max_step = BTC_CYCLE_SLOT_MAX */
struct fbtc_cycle_time_info cycle_time;
struct fbtc_fdd_try_info fdd_try;
struct fbtc_cycle_a2dp_empty_info a2dp_ept;
struct fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
struct fbtc_cycle_leak_info leak_slot;
u32 slot_cnt[CXST_MAX]; /* slot count */
u32 bcn_cnt[CXBCN_MAX];
u32 collision_cnt; /* counter for event/timer occur at the same time */
u32 skip_cnt;
u32 except_cnt;
u32 except_map;
};
#define FCX_NULLSTA_VER 2
struct fbtc_cynullsta { /* cycle null statistics */
u8 fver;
u8 rsvd;
u16 rsvd2;
u32 tmax[CXNULL_STATE_MAX]; /* max_t for 0:null0/1:null1 */
u32 tavg[CXNULL_STATE_MAX]; /* avg_t for 0:null0/1:null1 */
u32 result[CXNULL_STATE_MAX][CXNULL_MAX]; /* result for null , 0:fail, 1:ok, 2:late, 3:retry */
};
#define FCX_BTVER_VER 1
struct fbtc_btver {
u8 fver;
u8 rsvd;
u16 rsvd2;
u32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
u32 fw_ver;
u32 feature;
};
#define FCX_BTSCAN_VER 1
struct fbtc_btscan {
u8 fver;
u8 rsvd;
u16 rsvd2;
u8 scan[6];
};
#define FCX_BTAFH_VER 1
struct fbtc_btafh {
u8 fver;
u8 rsvd;
u16 rsvd2;
u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
};
#define FCX_BTDEVINFO_VER 1
struct fbtc_btdevinfo {
u8 fver;
u8 rsvd;
u16 vendor_id;
u32 dev_name; /* only 24 bits valid */
u32 flush_time;
};
/*
* End of FW Definition
*/
#pragma pack(pop)
#endif /* __INC_BTC_FW_DEF_H__ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/btc/halbtc_fwdef.h
|
C
|
agpl-3.0
| 8,473
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*
The purpose of hal_efuse.c
Provide efuse operations.
a. efuse init function
b. efuse shadow map read/write/update
c. efuse information query, map size/used bytes...
*/
#define _HAL_EFUSE_C_
#include "../hal_headers.h"
#include "hal_efuse.h"
#include "hal_efuse_export.h"
/* WIFI EFUSE API */
void efuse_shadow_read_one_byte(struct efuse_t *efuse, u16 offset, u8 *value)
{
*value = efuse->shadow_map[offset];
}
void efuse_shadow_read_two_byte(struct efuse_t *efuse, u16 offset, u16 *value)
{
*value = efuse->shadow_map[offset];
*value |= efuse->shadow_map[offset+1] << 8;
}
void efuse_shadow_read_four_byte(struct efuse_t *efuse, u16 offset, u32 *value)
{
*value = efuse->shadow_map[offset];
*value |= efuse->shadow_map[offset+1] << 8;
*value |= efuse->shadow_map[offset+2] << 16;
*value |= efuse->shadow_map[offset+3] << 24;
}
void efuse_shadow_write_one_byte(struct efuse_t *efuse, u16 offset, u16 value)
{
efuse->shadow_map[offset] = (u8)(value&0x00FF);
}
void efuse_shadow_write_two_byte(struct efuse_t *efuse, u16 offset, u16 value)
{
efuse->shadow_map[offset] = (u8)(value&0x00FF);
efuse->shadow_map[offset+1] = (u8)((value&0xFF00) >> 8);
}
void efuse_shadow_write_four_byte(struct efuse_t *efuse, u16 offset, u32 value)
{
efuse->shadow_map[offset] = (u8)(value&0x000000FF);
efuse->shadow_map[offset+1] = (u8)((value&0x0000FF00) >> 8);
efuse->shadow_map[offset+2] = (u8)((value&0x00FF0000) >> 16);
efuse->shadow_map[offset+3] = (u8)((value&0xFF000000) >> 24);
}
u32 efuse_check_autoload(struct efuse_t *efuse)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_check_efuse_autoload(efuse->hal_com,
&efuse->is_map_valid);
if (efuse->is_map_valid != true)
efuse->map_from_status = DEFAULT_MAP;
return hal_status;
}
u32 efuse_hidden_handle(struct efuse_t *efuse)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_read_hidden_rpt(efuse->hal_com);
return hal_status;
}
enum rtw_hal_status efuse_set_hw_cap(struct efuse_t *efuse)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = efuse->hal_com;
u8 pkg_type = 0xFF;
u8 rfe_type = 0xFF;
u8 xcap = 0xFF;
u8 domain = 0xFF;
u8 rf_board_opt = 0xFF;
status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_PKG_TYPE, &pkg_type,
sizeof(pkg_type));
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("%s: Get pkg type fail! Status(%x)\n", __FUNCTION__, status);
}
status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_RFE, &rfe_type,
sizeof(rfe_type));
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("%s: Get rfe type fail! Status(%x)\n", __FUNCTION__, status);
}
status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_XTAL, &xcap,
sizeof(xcap));
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("%s: Get xcap fail! Status(%x)\n", __FUNCTION__, status);
}
status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_CHAN_PLAN, &domain,
sizeof(domain));
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("%s: Get domain fail! Status(%x)\n", __FUNCTION__, status);
}
status = rtw_efuse_get_info(efuse, EFUSE_INFO_RF_BOARD_OPTION, &rf_board_opt,
sizeof(rf_board_opt));
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("%s: Get domain fail! Status(%x)\n", __FUNCTION__, status);
}
hal_com->dev_hw_cap.pkg_type = pkg_type;
hal_com->dev_hw_cap.rfe_type = rfe_type;
hal_com->dev_hw_cap.xcap = xcap;
hal_com->dev_hw_cap.domain = domain;
hal_com->dev_hw_cap.rf_board_opt = rf_board_opt;
return status;
}
enum rtw_hal_status rtw_efuse_logicmap_buf_load(void *efuse, u8* buf, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_read_log_efuse_map(efuse_info->hal_com,
buf,
is_limit);
return status;
}
enum rtw_hal_status rtw_efuse_shadow_load(void *efuse, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_read_log_efuse_map(efuse_info->hal_com,
efuse_info->shadow_map,
is_limit);
if (efuse_info->is_map_valid == true && status == RTW_HAL_STATUS_SUCCESS)
efuse_info->map_from_status = HW_LOG_MAP;
return status;
}
enum rtw_hal_status rtw_efuse_shadow_file_load(void *efuse, char *ic_name, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
#ifdef CONFIG_EFUSE_CONFIG_FILE
struct efuse_t *efuse_info = efuse;
if (efuse_info->is_map_valid != true ||
rtw_hal_rf_check_efuse_data(efuse_info->hal_com, HW_PHY_0) != true) {
if (rtw_hal_efuse_shadow_file_load(efuse_info->hal_com ,
ic_name, is_limit) == RTW_HAL_STATUS_SUCCESS) {
if (rtw_hal_rf_check_efuse_data(efuse_info->hal_com, HW_PHY_0) == true) {
efuse_info->is_map_valid = true;
PHL_INFO(" %s() hal_rf check file efuse is_map_valid.\n", __FUNCTION__);
} else {
status = RTW_HAL_STATUS_FAILURE;
PHL_WARN(" %s() efuse Power invalid !\n", __FUNCTION__);
}
} else {
PHL_WARN("%s: efuse shadow_file_load fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_FAILURE;
}
}
#endif
return status;
}
enum rtw_hal_status rtw_efuse_shadow_update(void *efuse, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
enum rtw_hal_status reload_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 map_size = 0, mask_size = 0;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) {
PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_UNINIT;
goto exit;
}
/* Load efuse mask file before PG */
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_MASK_FILE_LOADED) == false) {
PHL_WARN("%s: efuse mask not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
goto exit;
}
/*
* If driver does not load external map file,
* assign the map version with the mask version for the version check.
*/
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_MAP_FILE_LOADED) == false) {
_os_mem_cpy(efuse_info->hal_com->drv_priv, efuse_info->map_version,
efuse_info->mask_version, efuse_info->version_len);
}
if(is_limit) {
map_size = efuse_info->limit_efuse_size;
mask_size = efuse_info->limit_mask_size;
}
else {
map_size = efuse_info->log_efuse_size;
mask_size = efuse_info->mask_size;
}
status = rtw_hal_mac_write_log_efuse_map(efuse_info->hal_com,
efuse_info->shadow_map,
map_size,
efuse_info->mask,
mask_size,
efuse_info->map_version,
efuse_info->mask_version,
efuse_info->version_len,
0,
is_limit);
if(status != RTW_HAL_STATUS_SUCCESS)
PHL_WARN("%s: PG Fail!\n", __FUNCTION__);
/* Reload shadow map after PG */
reload_status = rtw_hal_mac_read_log_efuse_map(efuse_info->hal_com,
efuse_info->shadow_map,
is_limit);
if(reload_status != RTW_HAL_STATUS_SUCCESS)
PHL_WARN("%s: Reload shadow map Fail!\n", __FUNCTION__);
/*
* Clear the load external map file flag and map version
* after reloading the map.
*/
if(TEST_STATUS_FLAG(efuse_info->status,
EFUSE_STATUS_MAP_FILE_LOADED) == true) {
CLEAR_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_MAP_FILE_LOADED);
}
_os_mem_set(efuse_info->hal_com->drv_priv,
efuse_info->map_version,
0,
efuse_info->version_len);
exit:
return status;
}
enum rtw_hal_status
rtw_efuse_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value,
bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 efuse_size = 0;
if(is_limit)
efuse_size = efuse_info->limit_efuse_size;
else
efuse_size = efuse_info->log_efuse_size;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) {
PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_UNINIT;
goto exit;
}
if((u32)(offset+byte_count) > efuse_size) {
PHL_WARN("%s: Invalid offset!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET;
goto exit;
}
if (byte_count == 1)
efuse_shadow_read_one_byte(efuse_info, offset, (u8 *)value);
else if (byte_count == 2)
efuse_shadow_read_two_byte(efuse_info, offset, (u16 *)value);
else if (byte_count == 4)
efuse_shadow_read_four_byte(efuse_info, offset, (u32 *)value);
status = RTW_HAL_STATUS_SUCCESS;
exit:
return status;
}
enum rtw_hal_status
rtw_efuse_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value,
bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 efuse_size = 0;
if(is_limit)
efuse_size = efuse_info->limit_efuse_size;
else
efuse_size = efuse_info->log_efuse_size;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) {
PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_UNINIT;
goto exit;
}
if((u32)(offset+byte_count) > efuse_size) {
PHL_WARN("%s: Invalid offset!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET;
goto exit;
}
if (byte_count == 1)
efuse_shadow_write_one_byte(efuse_info, offset, (u8)value);
else if (byte_count == 2)
efuse_shadow_write_two_byte(efuse_info, offset, (u16)value);
else if (byte_count == 4)
efuse_shadow_write_four_byte(efuse_info, offset, (u32)value);
status = RTW_HAL_STATUS_SUCCESS;
exit:
return status;
}
/*
* This API is used for original mp dll command.
* usage = used percentage(1 Byte) + used bytes(2 Bytes)
*/
enum rtw_hal_status rtw_efuse_get_usage(void *efuse, u32 *usage)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 avl_size = 0;
u16 used_byte = 0;
u32 total_size = 0;
u8 used_percentage = 0;
status = rtw_hal_mac_get_efuse_avl(efuse_info->hal_com, &avl_size);
status = rtw_hal_mac_get_efuse_size(efuse_info->hal_com, &total_size);
if(total_size != 0){
used_byte = (u16)(total_size - avl_size);
used_percentage = (u8)(used_byte*100/total_size);
*usage = (used_percentage<<16)|(used_byte);
}
return status;
}
enum rtw_hal_status rtw_efuse_shadow2buf(void *efuse, u8 *destbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct efuse_t *efuse_info = efuse;
_os_mem_cpy(efuse_info->hal_com->drv_priv, (void *)destbuf,
(void *)efuse_info->shadow_map , buflen);
return status;
}
enum rtw_hal_status
efuse_map_buf2shadow(struct efuse_t *efuse, u8 *srcbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
_os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->shadow_map,
(void *)srcbuf, buflen);
SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_MAP_FILE_LOADED);
return status;
}
enum rtw_hal_status
efuse_file_map2version(struct efuse_t *efuse, u8 *srcbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
_os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->map_version,
(void *)srcbuf, buflen);
debug_dump_data(efuse->map_version, efuse->version_len,
"[HAL EFUSE] map version =");
return status;
}
enum rtw_hal_status
efuse_file_mask2buf(struct efuse_t *efuse, u8 *srcbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
_os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->mask, (void *)srcbuf,
buflen);
SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_MASK_FILE_LOADED);
status = RTW_HAL_STATUS_SUCCESS;
debug_dump_data(efuse->mask, efuse->mask_size, "[HAL EFUSE] mask data =");
return status;
}
enum rtw_hal_status
efuse_file_mask2version(struct efuse_t *efuse, u8 *srcbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
if (buflen <= efuse->version_len) {
_os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->mask_version,
(void *)srcbuf, buflen);
debug_dump_data(efuse->mask_version, efuse->version_len,
"[HAL EFUSE] mask ver =");
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
static u16 efuse_file_open(void *d, char *filepath, u8 *buf, u32 buflen)
{
char *ptmpbuf = NULL, *ptr;
u32 bufsize = 5120;
u8 val8 = 0;
u32 file_size = 0, i = 0, j= 0, tmp = 0;
int err = 0;
ptmpbuf = _os_mem_alloc(d, bufsize);
if (ptmpbuf == NULL) {
PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__);
return 0;
}
file_size = _os_read_file(filepath, (u8*)ptmpbuf, bufsize);
if (file_size > 0) {
if (file_size <= 90) {
_os_mem_free(d, (void*)ptmpbuf, bufsize);
PHL_INFO("%s, filepatch %s, size=%d not over 90, FAIL!!\n",
__FUNCTION__, filepath, file_size);
return 0;
}
i = 0;
j = 0;
ptr = ptmpbuf;
while ((j < buflen) && (i < file_size)) {
if (ptmpbuf[i] == '\0')
break;
ptr = _os_strpbrk((char *)&ptmpbuf[i], " \t\n\r");
if (ptr) {
if (ptr == &ptmpbuf[i]) {
i++;
continue;
}
/* Add string terminating null */
*ptr = 0;
} else {
ptr = &ptmpbuf[file_size-1];
}
err = _os_sscanf((char *)&ptmpbuf[i], "%x", &tmp);
if (err != 1) {
PHL_INFO("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]);
} else {
val8 = (u8)tmp;
buf[j] = val8;
PHL_INFO("i=%d, j=%d, 0x%02x\n", i, j, buf[j]);
j++;
}
i = (u32)(ptr - ptmpbuf + 1);
}
}
if (ptmpbuf)
_os_mem_free(d, (void*)ptmpbuf, bufsize);
PHL_INFO("%s, filepatch %s, size=%d, done\n", __FUNCTION__, filepath, file_size);
return (u16)j;
}
enum rtw_hal_status
rtw_efuse_file_map_load(void *efuse, char *file_path, u8 is_limit)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
void *d = efuse_info->hal_com->drv_priv;
u8 *mapbuf = NULL;
u16 data_len = 0;
u32 map_sz = 0, full_map_sz = 0;
if (is_limit)
map_sz = efuse_info->limit_efuse_size;
else
map_sz = efuse_info->log_efuse_size;
if (map_sz == 0) {
map_sz = MAX_EFUSE_MAP_LEN;
full_map_sz = MAX_EFUSE_MAP_LEN + MAX_EFUSE_FILE_VERSION_LENGTH;
} else
full_map_sz = map_sz + efuse_info->version_len;
if (file_path && full_map_sz != 0) {
mapbuf= _os_mem_alloc(d, full_map_sz);
if (mapbuf == NULL) {
PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__);
goto exit;
}
_os_mem_set(d, mapbuf, 0xFF, full_map_sz);
data_len = efuse_file_open(d, file_path, mapbuf, full_map_sz);
if ((data_len > map_sz) && (data_len <= full_map_sz)) {
efuse_file_map2version(efuse_info, mapbuf + map_sz,
efuse_info->version_len);
if (data_len > map_sz)
data_len -= efuse_info->version_len;
PHL_INFO("%s , File eFuse map to shadow len %d\n", __FUNCTION__, data_len);
hal_status = efuse_map_buf2shadow(efuse_info, mapbuf, data_len);
efuse_info->map_from_status = FILE_MAP;
} else {
PHL_INFO("Error No Map Version !, File Map Data Len %d not over 1536.\n", data_len);
goto exit;
}
}
exit:
if (mapbuf)
_os_mem_free(d, (void*)mapbuf, full_map_sz);
return hal_status;
}
enum rtw_hal_status
rtw_efuse_file_mask_load(void *efuse, char *file_path, u8 is_limit)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
void *d = efuse_info->hal_com->drv_priv;
u8 *maskbuf = NULL;
u16 data_len = 0;
u32 mask_sz = 0, full_mask_sz = 0;
if (is_limit)
mask_sz = efuse_info->limit_mask_size;
else
mask_sz = efuse_info->mask_size;
if (mask_sz == 0) {
mask_sz = EFUSE_MASK_FILE_LEN;
full_mask_sz = EFUSE_MASK_FILE_LEN + MAX_EFUSE_FILE_VERSION_LENGTH;
} else
full_mask_sz = mask_sz + efuse_info->version_len;
if (file_path) {
maskbuf= _os_mem_alloc(d, full_mask_sz);
if (maskbuf == NULL) {
PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__);
goto exit;
}
_os_mem_set(d, maskbuf, 0xFF, full_mask_sz);
data_len = efuse_file_open(d, file_path, maskbuf, full_mask_sz);
if ((data_len > mask_sz) && (data_len <= full_mask_sz)) {
efuse_file_mask2version(efuse_info, maskbuf + mask_sz,
efuse_info->version_len);
if (data_len > mask_sz)
data_len -= efuse_info->version_len;
PHL_INFO("Mask File data 2 buf len %d\n", data_len);
hal_status = efuse_file_mask2buf(efuse_info, maskbuf, data_len);
} else {
PHL_INFO("Error No Map Version !, File Map Data Len %d not over 102.\n", data_len);
goto exit;
}
}
exit:
if (maskbuf)
_os_mem_free(d, (void*)maskbuf, full_mask_sz);
return hal_status;
}
enum rtw_hal_status rtw_efuse_get_logical_size(void *efuse, u32 *size,
bool is_limited)
{
struct efuse_t *efuse_info = efuse;
if(is_limited == true)
*size = efuse_info->limit_efuse_size;
else
*size = efuse_info->log_efuse_size;
PHL_INFO("%s: size = %d\n", __FUNCTION__, *size);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_efuse_get_size(void *efuse, u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_get_efuse_size(efuse_info->hal_com, size);
PHL_INFO("%s: size = %d\n", __FUNCTION__, *size);
return status;
}
enum rtw_hal_status rtw_efuse_get_avl(void *efuse, u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_get_efuse_avl(efuse_info->hal_com, size);
/* [TEMP] Set avl size for testing */
/* size = 512; */
PHL_INFO("%s: size = %d\n", __FUNCTION__, *size);
return status;
}
enum rtw_hal_status rtw_efuse_get_offset_mask(void *efuse, u16 offset, u8 *mask)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false)
return RTW_HAL_STATUS_EFUSE_UNINIT;
if(offset >= efuse_info->limit_mask_size)
return RTW_HAL_STATUS_EFUSE_IVALID_OFFSET;
*mask = efuse_info->mask[offset];
PHL_INFO("%s: offset = %x mask = %x\n", __FUNCTION__, offset, *mask);
return status;
}
enum rtw_hal_status rtw_efuse_get_shadowmap_from(void *efuse, u8 *val)
{
struct efuse_t *efuse_info = efuse;
*val = efuse_info->map_from_status;
PHL_INFO("%s:get efuse %s\n", __FUNCTION__, SHADOWMAP_FROM2STR(*val));
return RTW_HAL_STATUS_SUCCESS;
}
char* rtw_efuse_get_shadowmap_from_to_str(void *efuse)
{
struct efuse_t *efuse_info = efuse;
return SHADOWMAP_FROM2STR(efuse_info->map_from_status);
}
enum rtw_hal_status rtw_efuse_get_info(void *efuse,
enum rtw_efuse_info info_type,
void *value,
u8 size)
{
struct efuse_t *efuse_info = efuse;
struct rtw_hal_com_t *hal_com = efuse_info->hal_com;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false)
return RTW_HAL_STATUS_EFUSE_UNINIT;
if(info_type <= EFUSE_INFO_MAC_MAX)
hal_status = rtw_hal_mac_get_efuse_info(hal_com,
efuse_info->shadow_map,
info_type,
value,
size,
efuse_info->is_map_valid);
else if (info_type <= EFUSE_INFO_BB_MAX)
hal_status = rtw_hal_bb_get_efuse_info(hal_com,
efuse_info->shadow_map,
info_type,
value,
size,
efuse_info->is_map_valid);
else if (info_type <= EFUSE_INFO_RF_MAX)
hal_status = rtw_hal_rf_get_efuse_info(hal_com,
efuse_info->shadow_map,
info_type,
value,
size,
efuse_info->is_map_valid);
else
hal_status = rtw_hal_btc_get_efuse_info(hal_com,
efuse_info->shadow_map,
info_type,
value,
size,
efuse_info->is_map_valid);
return hal_status;
}
void rtw_efuse_process(void *efuse, char *ic_name)
{
struct efuse_t *efuse_info = (struct efuse_t *)efuse;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == true) {
PHL_INFO("%s EFUSE module is already initialized.\n", __FUNCTION__);
return;
}
efuse_check_autoload(efuse_info);
/* Load wifi full map to shadow map */
rtw_efuse_shadow_load(efuse_info, false);
rtw_efuse_shadow_file_load(efuse_info, ic_name, true);
debug_dump_data(efuse_info->shadow_map, efuse_info->log_efuse_size,
"Logical EFUSE MAP:");
efuse_hidden_handle(efuse_info);
SET_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS);
/*
* We can set the hw cap after we got the shadow map.
* The efuse get info API will check the efuse is processed or not.
*/
efuse_set_hw_cap(efuse_info);
if (RTW_DRV_MODE_EQC == efuse_info->phl_com->drv_mode) {
rtw_hal_rf_get_default_rfe_type(efuse_info->hal_com);
rtw_hal_rf_get_default_xtal(efuse_info->hal_com);
PHL_WARN("%s: Use default RFE type(0x%x) / XTAL(0x%x) configuration for EQC mode\n",
__FUNCTION__,
efuse_info->hal_com->dev_hw_cap.rfe_type,
efuse_info->hal_com->dev_hw_cap.xcap);
}
}
u32 rtw_efuse_init(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, void **efuse)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = NULL;
efuse_info = _os_mem_alloc(hal_com->drv_priv, sizeof(struct efuse_t));
if(efuse_info == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
goto error_efuse_init;
}
/* Allocate shadow map memory */
hal_status = rtw_hal_mac_get_log_efuse_size(hal_com,
&(efuse_info->log_efuse_size),
false);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Get full logical efuse map size fail!\n",__FUNCTION__);
goto error_efuse_shadow_init;
}
efuse_info->shadow_map = _os_mem_alloc(hal_com->drv_priv,
efuse_info->log_efuse_size);
if(efuse_info->shadow_map == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s Allocate shadow efuse map fail!\n", __FUNCTION__);
goto error_efuse_shadow_init;
}
hal_status = rtw_hal_mac_get_log_efuse_size(hal_com,
&(efuse_info->limit_efuse_size),
true);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Get limited logical efuse map size fail!\n", __FUNCTION__);
goto error_efuse_shadow_init;
}
/* Allocate mask memory */
hal_status = rtw_hal_mac_get_efuse_mask_size(hal_com,
&(efuse_info->mask_size),
false);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Get full efuse mask size fail!\n", __FUNCTION__);
goto error_efuse_mask_init;
}
efuse_info->mask = _os_mem_alloc(hal_com->drv_priv,
efuse_info->mask_size);
if(efuse_info->mask == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s Allocate efuse mask fail!\n", __FUNCTION__);
goto error_efuse_mask_init;
}
hal_status = rtw_hal_mac_get_efuse_mask_size(hal_com,
&(efuse_info->limit_mask_size),
true);
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Get limited efuse mask size fail!\n", __FUNCTION__);
goto error_efuse_mask_init;
}
efuse_info->version_len = rtw_hal_mac_get_efuse_ver_len(hal_com);
efuse_info->map_version = _os_mem_alloc(hal_com->drv_priv,
efuse_info->version_len);
if(efuse_info->map_version == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
goto error_map_version_init;
}
efuse_info->mask_version = _os_mem_alloc(hal_com->drv_priv,
efuse_info->version_len);
if(efuse_info->mask_version == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
goto error_mask_version_init;
}
/* Allocate bt shadow map memory */
hal_status = rtw_hal_mac_get_log_efuse_bt_size(hal_com,
&(efuse_info->bt_log_efuse_size));
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Get full logical efuse map size fail!\n",__FUNCTION__);
goto error_efuse_bt_shadow_init;
}
efuse_info->bt_shadow_map = _os_mem_alloc(hal_com->drv_priv,
efuse_info->bt_log_efuse_size);
if(efuse_info->bt_shadow_map == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s Allocate shadow efuse map fail!\n", __FUNCTION__);
goto error_efuse_bt_shadow_init;
}
/* Allocate mask memory */
hal_status = rtw_hal_mac_get_efuse_bt_mask_size(hal_com,
&(efuse_info->bt_mask_size));
if(hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s Get full efuse mask size fail!\n", __FUNCTION__);
goto error_efuse_bt_mask_init;
}
efuse_info->bt_mask = _os_mem_alloc(hal_com->drv_priv,
efuse_info->bt_mask_size);
if(efuse_info->bt_mask == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("%s Allocate efuse mask fail!\n", __FUNCTION__);
goto error_efuse_bt_mask_init;
}
efuse_info->phl_com = phl_com;
efuse_info->hal_com = hal_com;
*efuse = efuse_info;
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
error_efuse_bt_mask_init:
_os_mem_free(hal_com->drv_priv, efuse_info->bt_shadow_map,
efuse_info->bt_log_efuse_size);
error_efuse_bt_shadow_init:
_os_mem_free(hal_com->drv_priv, efuse_info->mask_version,
efuse_info->version_len);
error_mask_version_init:
_os_mem_free(hal_com->drv_priv, efuse_info->map_version,
efuse_info->version_len);
error_map_version_init:
_os_mem_free(hal_com->drv_priv, efuse_info->mask,
efuse_info->mask_size);
error_efuse_mask_init:
_os_mem_free(hal_com->drv_priv, efuse_info->shadow_map,
efuse_info->log_efuse_size);
error_efuse_shadow_init:
_os_mem_free(hal_com->drv_priv, efuse_info, sizeof(struct efuse_t));
error_efuse_init:
return hal_status;
}
void rtw_efuse_deinit(struct rtw_hal_com_t *hal_com, void *efuse)
{
struct efuse_t *efuse_info = efuse;
if(efuse_info->bt_mask) {
_os_mem_free(hal_com->drv_priv, efuse_info->bt_mask,
efuse_info->bt_mask_size);
efuse_info->bt_mask = NULL;
}
if(efuse_info->bt_shadow_map) {
_os_mem_free(hal_com->drv_priv, efuse_info->bt_shadow_map,
efuse_info->bt_log_efuse_size);
efuse_info->bt_shadow_map = NULL;
}
if(efuse_info->mask) {
_os_mem_free(hal_com->drv_priv, efuse_info->mask,
efuse_info->mask_size);
efuse_info->mask = NULL;
}
if(efuse_info->map_version) {
_os_mem_free(hal_com->drv_priv, efuse_info->map_version,
efuse_info->version_len);
efuse_info->map_version = NULL;
}
if(efuse_info->mask_version) {
_os_mem_free(hal_com->drv_priv, efuse_info->mask_version,
efuse_info->version_len);
efuse_info->mask_version = NULL;
}
if(efuse_info->shadow_map) {
_os_mem_free(hal_com->drv_priv, efuse_info->shadow_map,
efuse_info->log_efuse_size);
efuse_info->shadow_map = NULL;
}
if (efuse_info) {
_os_mem_free(hal_com->drv_priv, efuse_info, sizeof(struct efuse_t));
efuse_info = NULL;
}
}
/* BT EFUSE API */
void efuse_bt_shadow_read_one_byte(struct efuse_t *efuse, u16 offset, u8 *value)
{
*value = efuse->bt_shadow_map[offset];
}
void efuse_bt_shadow_read_two_byte(struct efuse_t *efuse, u16 offset, u16 *value)
{
*value = efuse->bt_shadow_map[offset];
*value |= efuse->bt_shadow_map[offset+1] << 8;
}
void efuse_bt_shadow_read_four_byte(struct efuse_t *efuse, u16 offset, u32 *value)
{
*value = efuse->bt_shadow_map[offset];
*value |= efuse->bt_shadow_map[offset+1] << 8;
*value |= efuse->bt_shadow_map[offset+2] << 16;
*value |= efuse->bt_shadow_map[offset+3] << 24;
}
void efuse_bt_shadow_write_one_byte(struct efuse_t *efuse, u16 offset, u16 value)
{
efuse->bt_shadow_map[offset] = (u8)(value&0x00FF);
}
void efuse_bt_shadow_write_two_byte(struct efuse_t *efuse, u16 offset, u16 value)
{
efuse->bt_shadow_map[offset] = (u8)(value&0x00FF);
efuse->bt_shadow_map[offset+1] = (u8)((value&0xFF00) >> 8);
}
void efuse_bt_shadow_write_four_byte(struct efuse_t *efuse, u16 offset, u32 value)
{
efuse->bt_shadow_map[offset] = (u8)(value&0x000000FF);
efuse->bt_shadow_map[offset+1] = (u8)((value&0x0000FF00) >> 8);
efuse->bt_shadow_map[offset+2] = (u8)((value&0x00FF0000) >> 16);
efuse->bt_shadow_map[offset+3] = (u8)((value&0xFF000000) >> 24);
}
enum rtw_hal_status rtw_efuse_bt_shadow_load(void *efuse)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_read_log_efuse_bt_map(efuse_info->hal_com,
efuse_info->bt_shadow_map);
return status;
}
enum rtw_hal_status rtw_efuse_bt_shadow_update(void *efuse)
{
enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
enum rtw_hal_status reload_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 map_size = 0, mask_size = 0;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) {
PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_UNINIT;
goto exit;
}
/* Load efuse mask file before PG */
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_BT_MASK_FILE_LOADED) == false) {
PHL_WARN("%s: efuse mask not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
goto exit;
}
map_size = efuse_info->bt_log_efuse_size;
mask_size = efuse_info->bt_mask_size;
status = rtw_hal_mac_write_log_efuse_bt_map(efuse_info->hal_com,
efuse_info->bt_shadow_map,
map_size,
efuse_info->bt_mask,
mask_size);
if(status != RTW_HAL_STATUS_SUCCESS)
PHL_WARN("%s: BT PG Fail!\n", __FUNCTION__);
/* Reload shadow map after PG */
reload_status = rtw_hal_mac_read_log_efuse_bt_map(efuse_info->hal_com,
efuse_info->bt_shadow_map);
if(reload_status != RTW_HAL_STATUS_SUCCESS)
PHL_WARN("%s: Reload bt shadow map Fail!\n", __FUNCTION__);
/*
* Clear the load external map file flag and map version
* after reloading the map.
*/
if(TEST_STATUS_FLAG(efuse_info->status,
EFUSE_STATUS_BT_MAP_FILE_LOADED) == true) {
CLEAR_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_BT_MAP_FILE_LOADED);
}
exit:
return status;
}
enum rtw_hal_status
rtw_efuse_bt_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 efuse_bt_size = 0;
efuse_bt_size = efuse_info->bt_log_efuse_size;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) {
PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_UNINIT;
goto exit;
}
if((u32)(offset+byte_count) > efuse_bt_size) {
PHL_WARN("%s: Invalid offset!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET;
goto exit;
}
if (byte_count == 1)
efuse_bt_shadow_read_one_byte(efuse_info, offset, (u8 *)value);
else if (byte_count == 2)
efuse_bt_shadow_read_two_byte(efuse_info, offset, (u16 *)value);
else if (byte_count == 4)
efuse_bt_shadow_read_four_byte(efuse_info, offset, (u32 *)value);
status = RTW_HAL_STATUS_SUCCESS;
exit:
return status;
}
enum rtw_hal_status
rtw_efuse_bt_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 efuse_bt_size = 0;
efuse_bt_size = efuse_info->bt_log_efuse_size;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false) {
PHL_WARN("%s: efuse map not load yet!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_UNINIT;
goto exit;
}
if((u32)(offset+byte_count) > efuse_bt_size) {
PHL_WARN("%s: Invalid offset!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_IVALID_OFFSET;
goto exit;
}
if (byte_count == 1)
efuse_bt_shadow_write_one_byte(efuse_info, offset, (u8)value);
else if (byte_count == 2)
efuse_bt_shadow_write_two_byte(efuse_info, offset, (u16)value);
else if (byte_count == 4)
efuse_bt_shadow_write_four_byte(efuse_info, offset, (u32)value);
status = RTW_HAL_STATUS_SUCCESS;
exit:
return status;
}
/*
* This API is used for original mp dll command.
* usage = used percentage(1 Byte) + used bytes(2 Bytes)
*/
enum rtw_hal_status rtw_efuse_bt_get_usage(void *efuse, u32 *usage)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
u32 avl_size = 0;
u16 used_byte = 0;
u32 total_size = 0;
u8 used_percentage = 0;
status = rtw_hal_mac_get_efuse_bt_avl(efuse_info->hal_com, &avl_size);
status = rtw_hal_mac_get_efuse_bt_size(efuse_info->hal_com, &total_size);
if(total_size != 0){
used_byte = (u16)(total_size - avl_size);
used_percentage = (u8)(used_byte*100/total_size);
*usage = (used_percentage<<16)|(used_byte);
}
return status;
}
enum rtw_hal_status rtw_efuse_bt_shadow2buf(void *efuse, u8 *destbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct efuse_t *efuse_info = efuse;
_os_mem_cpy(efuse_info->hal_com->drv_priv, (void *)destbuf,
(void *)efuse_info->bt_shadow_map , buflen);
return status;
}
enum rtw_hal_status
efuse_bt_map_buf2shadow(struct efuse_t *efuse, u8 *srcbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
_os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->bt_shadow_map,
(void *)srcbuf, buflen);
SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_BT_MAP_FILE_LOADED);
status = RTW_HAL_STATUS_SUCCESS;
return status;
}
enum rtw_hal_status
efuse_bt_file_mask2buf(struct efuse_t *efuse, u8 *srcbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
_os_mem_cpy(efuse->hal_com->drv_priv, (void *)efuse->bt_mask, (void *)srcbuf,
buflen);
SET_STATUS_FLAG(efuse->status, EFUSE_STATUS_BT_MASK_FILE_LOADED);
status = RTW_HAL_STATUS_SUCCESS;
debug_dump_data(efuse->bt_mask, efuse->bt_mask_size, "[HAL EFUSE] bt mask data =");
return status;
}
enum rtw_hal_status
rtw_efuse_bt_file_map_load(void *efuse, char *file_path)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
void *d = efuse_info->hal_com->drv_priv;
u8 *mapbuf = NULL;
u16 data_len = 0;
u32 bt_map_sz = 0;
bt_map_sz = efuse_info->bt_log_efuse_size;
if (bt_map_sz == 0)
bt_map_sz = MAX_EFUSE_MAP_LEN;
if (file_path) {
mapbuf= _os_mem_alloc(d, bt_map_sz);
if (mapbuf == NULL) {
PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__);
goto exit;
}
_os_mem_set(d, mapbuf, 0xFF, bt_map_sz);
data_len = efuse_file_open(d, file_path, mapbuf, bt_map_sz);
if (data_len <= bt_map_sz) {
PHL_INFO("%s , File eFuse bt map to shadow len %d\n", __FUNCTION__, data_len);
hal_status = efuse_bt_map_buf2shadow(efuse_info, mapbuf, data_len);
} else {
PHL_INFO("Error No bt Map Version !, File Map Data Len %d not over 1024.\n", data_len);
goto exit;
}
}
exit:
if (mapbuf)
_os_mem_free(d, (void*)mapbuf, bt_map_sz);
return hal_status;
}
enum rtw_hal_status
rtw_efuse_bt_file_mask_load(void *efuse, char *file_path)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
void *d = efuse_info->hal_com->drv_priv;
u8 *maskbuf = NULL;
u16 data_len = 0;
u32 bt_mask_sz = 0;
bt_mask_sz = efuse_info->bt_mask_size;
if (bt_mask_sz == 0)
goto exit;
if (file_path) {
maskbuf= _os_mem_alloc(d, bt_mask_sz);
if (maskbuf == NULL) {
PHL_INFO("%s, alloc buf FAIL!!\n", __FUNCTION__);
goto exit;
}
_os_mem_set(d, maskbuf, 0xFF, bt_mask_sz);
data_len = efuse_file_open(d, file_path, maskbuf, bt_mask_sz);
if (data_len <= bt_mask_sz) {
PHL_INFO("Mask File data 2 buf len %d\n", data_len);
hal_status = efuse_bt_file_mask2buf(efuse_info, maskbuf, data_len);
} else {
PHL_INFO("Error No Map Version !, File Map Data Len %d not over 96.\n", data_len);
goto exit;
}
}
exit:
if (maskbuf)
_os_mem_free(d, (void*)maskbuf, bt_mask_sz);
return hal_status;
}
enum rtw_hal_status rtw_efuse_bt_get_logical_size(void *efuse, u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_get_log_efuse_bt_size(efuse_info->hal_com, size);
PHL_INFO("%s: size = %d\n", __FUNCTION__, *size);
return status;
}
enum rtw_hal_status rtw_efuse_bt_get_size(void *efuse, u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_get_efuse_bt_size(efuse_info->hal_com, size);
PHL_INFO("%s: size = %d\n", __FUNCTION__, *size);
return status;
}
enum rtw_hal_status rtw_efuse_bt_get_avl(void *efuse, u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_get_efuse_bt_avl(efuse_info->hal_com, size);
PHL_INFO("%s: size = %d\n", __FUNCTION__, *size);
return status;
}
enum rtw_hal_status rtw_efuse_bt_get_offset_mask(void *efuse, u16 offset, u8 *mask)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
if(TEST_STATUS_FLAG(efuse_info->status, EFUSE_STATUS_PROCESS) == false)
return RTW_HAL_STATUS_EFUSE_UNINIT;
if(offset >= efuse_info->bt_mask_size)
return RTW_HAL_STATUS_EFUSE_IVALID_OFFSET;
*mask = efuse_info->bt_mask[offset];
PHL_INFO("%s: bt offset = %x mask = %x\n", __FUNCTION__, offset, *mask);
return status;
}
enum rtw_hal_status rtw_efuse_bt_read_hidden(void *efuse, u32 addr, u32 size, u8 *val)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_read_efuse_bt_hidden(efuse_info->hal_com, addr, size, val);
if(status == RTW_HAL_STATUS_SUCCESS)
{
PHL_INFO("%s: bt hidden read ok!\n", __FUNCTION__);
}else{
PHL_INFO("%s: bt hidden read fail!\n", __FUNCTION__);
}
return status;
}
enum rtw_hal_status rtw_efuse_bt_write_hidden(void *efuse, u32 addr, u8 val)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
status = rtw_hal_mac_write_efuse_bt_hidden(efuse_info->hal_com, addr, val);
if(status == RTW_HAL_STATUS_SUCCESS)
{
PHL_INFO("%s: bt hidden PG ok!\n", __FUNCTION__);
}else{
PHL_INFO("%s: bt hidden PG fail!\n", __FUNCTION__);
}
return status;
}
enum rtw_hal_status rtw_efuse_read_phy_wifi(void *efuse, u32 addr, u32 size, u8 *data, u8 type)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct efuse_t *efuse_info = efuse;
if(type == HAL_MP_EFUSE_WIFI)
status = rtw_hal_mac_read_phy_efuse(efuse_info->hal_com, addr, size, data);
else if(type == HAL_MP_EFUSE_BT)
status = rtw_hal_mac_read_bt_phy_efuse(efuse_info->hal_com, addr, size, data);
if(status == RTW_HAL_STATUS_SUCCESS)
{
PHL_INFO("%s: real raw read ok!\n", __FUNCTION__);
}else{
PHL_INFO("%s: real raw read fail!\n", __FUNCTION__);
}
return status;
}
enum rtw_hal_status rtw_efuse_renew(void *efuse, u8 type)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct efuse_t *efuse_info = efuse;
if (type == HAL_MP_EFUSE_WIFI) {
rtw_hal_bb_get_efuse_init(efuse_info->hal_com);
rtw_hal_rf_get_efuse_ex(efuse_info->hal_com, HW_PHY_MAX);
PHL_INFO("%s: hal efuse renew done\n", __FUNCTION__);
} else if (type == HAL_MP_EFUSE_BT) {
PHL_INFO("%s: Not ready\n", __FUNCTION__);
}
return status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/efuse/hal_efuse.c
|
C
|
agpl-3.0
| 39,206
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_EFUSE_H_
#define _HAL_EFUSE_H_
#define MAX_EFUSE_FILE_VERSION_LENGTH 6
#define EFUSE_MASK_FILE_LEN 96
#define MAX_EFUSE_MAP_LEN 1536
enum EFUSE_STATUS_FLAGS {
EFUSE_STATUS_PROCESS = BIT0,
EFUSE_STATUS_MAP_FILE_LOADED = BIT1,
EFUSE_STATUS_MASK_FILE_LOADED = BIT2,
EFUSE_STATUS_BT_MAP_FILE_LOADED = BIT3,
EFUSE_STATUS_BT_MASK_FILE_LOADED = BIT4
};
enum EFUSE_SHADOW_MAP_STATUS {
DEFAULT_MAP = 0,
HW_LOG_MAP = 1,
FILE_MAP = 2,
EFUSE_UNKNOWN,
};
#define SHADOWMAP_FROM2STR(status)\
(status == DEFAULT_MAP) ? "DEFAULT" :\
(status == HW_LOG_MAP) ? "HW_LOG_EFUSE" :\
(status == FILE_MAP) ? "FILE_EFUSE" :\
"UNknow"
/*
* @phl_com
* @hal_com
* @shadow_map: Buffer pointer for limited size logical map
* @mask: Buffer pointer for limited size mask read from mask file
* @map_version: Buffer pointer for map version read from map file
* @mask_version: Buffer pointer for mask version read from mask file
* @log_efuse_size: Limited logical map size
* @mask_size: Limited mask size
* @version_len: Length of verion field in map/mask
* @status: Efuse status
* @is_map_valid: Flag to check autoload status
* @reserved
*/
struct efuse_t {
struct rtw_phl_com_t *phl_com;
struct rtw_hal_com_t *hal_com;
u8 *shadow_map;
u8 *mask;
u8 *map_version;
u8 *mask_version;
u32 log_efuse_size;
u32 mask_size;
u32 limit_efuse_size;
u32 limit_mask_size;
u8 version_len;
u8 status;
u8 is_map_valid;
u8 reserved;
u8 map_from_status;
/* BT*/
u8 *bt_shadow_map;
u8 *bt_mask;
u32 bt_log_efuse_size;
u32 bt_efuse_size;
u32 bt_mask_size;
};
#endif /* _HAL_EFUSE_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/efuse/hal_efuse.h
|
C
|
agpl-3.0
| 2,242
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_EFUSE_EXPORT_H_
#define _HAL_EFUSE_EXPORT_H_
enum HAL_EFUSE_CMD_ID {
HAL_EFUSE_HELP,
HAL_EFUSE_WIFI_DUMP_MAP,
HAL_EFUSE_WIFI_LOGIC_DUMP_MAP
};
static const struct hal_cmd_info hal_efuse_cmd_i[] = {
{"-h", HAL_EFUSE_HELP},
{"dump_map", HAL_EFUSE_WIFI_DUMP_MAP},
{"dump_hw_map", HAL_EFUSE_WIFI_LOGIC_DUMP_MAP},
};
/* efuse exported API */
u32
rtw_efuse_init(struct rtw_phl_com_t *phl_com, struct rtw_hal_com_t *hal_com,
void **efuse);
void rtw_efuse_deinit(struct rtw_hal_com_t *hal_com, void *efuse);
enum rtw_hal_status
rtw_efuse_get_info(void *efuse, enum rtw_efuse_info info_type, void *value,
u8 size);
void rtw_efuse_process(void *efuse, char *ic_name);
enum rtw_hal_status
rtw_efuse_logicmap_buf_load(void *efuse, u8* buf, bool is_limit);
enum rtw_hal_status
rtw_efuse_shadow_load(void *efuse, bool is_limit);
enum rtw_hal_status
rtw_efuse_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value,
bool is_limit);
enum rtw_hal_status
rtw_efuse_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value,
bool is_limit);
enum rtw_hal_status
rtw_efuse_shadow_update(void *efuse, bool is_limit);
enum rtw_hal_status
rtw_efuse_shadow2buf(void *efuse, u8 *destbuf, u16 buflen);
enum rtw_hal_status
rtw_efuse_file_map_load(void *efuse, char *file_path, u8 is_limit);
enum rtw_hal_status
rtw_efuse_file_mask_load(void *efuse, char *file_path, u8 is_limit);
enum rtw_hal_status
rtw_efuse_get_usage(void *efuse, u32 *usage);
enum rtw_hal_status
rtw_efuse_get_logical_size(void *efuse, u32 *size, bool is_limited);
enum rtw_hal_status
rtw_efuse_get_size(void *efuse, u32 *size);
enum rtw_hal_status
rtw_efuse_get_avl(void *efuse, u32 *size);
enum rtw_hal_status
rtw_efuse_get_shadowmap_from(void *efuse, u8 *val);
char*
rtw_efuse_get_shadowmap_from_to_str(void *efuse);
enum rtw_hal_status
rtw_efuse_get_offset_mask(void *efuse, u16 offset, u8 *mask);
/* BT EFUSE */
enum rtw_hal_status
rtw_efuse_bt_shadow_load(void *efuse);
enum rtw_hal_status
rtw_efuse_bt_shadow_read(void *efuse, u8 byte_count, u16 offset, u32 *value);
enum rtw_hal_status
rtw_efuse_bt_shadow_write(void *efuse, u8 byte_count, u16 offset, u32 value);
enum rtw_hal_status
rtw_efuse_bt_shadow_update(void *efuse);
enum rtw_hal_status
rtw_efuse_bt_shadow2buf(void *efuse, u8 *destbuf, u16 buflen);
enum rtw_hal_status
rtw_efuse_bt_file_map_load(void *efuse, char *file_path);
enum rtw_hal_status
rtw_efuse_bt_file_mask_load(void *efuse, char *file_path);
enum rtw_hal_status
rtw_efuse_bt_get_usage(void *efuse, u32 *usage);
enum rtw_hal_status
rtw_efuse_bt_get_logical_size(void *efuse, u32 *size);
enum rtw_hal_status
rtw_efuse_bt_get_size(void *efuse, u32 *size);
enum rtw_hal_status
rtw_efuse_bt_get_avl(void *efuse, u32 *size);
enum rtw_hal_status
rtw_efuse_bt_get_offset_mask(void *efuse, u16 offset, u8 *mask);
enum rtw_hal_status rtw_efuse_bt_read_hidden(void *efuse, u32 addr, u32 size, u8 *val);
enum rtw_hal_status rtw_efuse_bt_write_hidden(void *efuse, u32 addr, u8 val);
enum rtw_hal_status rtw_efuse_read_phy_wifi(void *efuse, u32 addr, u32 size, u8 *data, u8 type);
enum rtw_hal_status rtw_efuse_renew(void *efuse, u8 type);
#endif /* _HAL_EFUSE_EXPORT_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/efuse/hal_efuse_export.h
|
C
|
agpl-3.0
| 3,880
|
########### HAL PATH #################################
HAL = hal_g6
ifeq ($(CONFIG_PHL_ARCH), y)
phl_path := phl/
phl_path_d1 := $(src)/phl/$(HAL)
else
phl_path :=
phl_path_d1 := $(src)/$(HAL)
endif
_HAL_FILES := $(phl_path)$(HAL)/hal_api_mac.o \
$(phl_path)$(HAL)/hal_api_bb.o \
$(phl_path)$(HAL)/hal_api_rf.o \
$(phl_path)$(HAL)/hal_api_btc.o \
$(phl_path)$(HAL)/hal_api_efuse.o \
$(phl_path)$(HAL)/hal_com_i.o \
$(phl_path)$(HAL)/hal_init.o \
$(phl_path)$(HAL)/hal_io.o \
$(phl_path)$(HAL)/hal_rx.o \
$(phl_path)$(HAL)/hal_tx.o \
$(phl_path)$(HAL)/hal_sta.o \
$(phl_path)$(HAL)/hal_cam.o \
$(phl_path)$(HAL)/hal_csi_buffer.o \
$(phl_path)$(HAL)/hal_beamform.o \
$(phl_path)$(HAL)/hal_sound.o \
$(phl_path)$(HAL)/hal_chan.o \
$(phl_path)$(HAL)/hal_str_proc.o \
$(phl_path)$(HAL)/hal_fw.o \
$(phl_path)$(HAL)/hal_cap.o \
$(phl_path)$(HAL)/hal_ser.o \
$(phl_path)$(HAL)/hal_ps.o \
$(phl_path)$(HAL)/hal_c2h.o \
$(phl_path)$(HAL)/hal_dbcc.o \
$(phl_path)$(HAL)/hal_chan_info.o \
$(phl_path)$(HAL)/hal_wow.o \
$(phl_path)$(HAL)/hal_ld_file.o \
$(phl_path)$(HAL)/hal_regulation.o \
$(phl_path)$(HAL)/hal_led.o \
$(phl_path)$(HAL)/hal_trx_mit.o \
$(phl_path)$(HAL)/hal_acs.o \
$(phl_path)$(HAL)/hal_mcc.o \
$(phl_path)$(HAL)/hal_api.o \
$(phl_path)$(HAL)/hal_twt.o \
$(phl_path)$(HAL)/hal_notify.o \
$(phl_path)$(HAL)/hal_p2pps.o \
$(phl_path)$(HAL)/hal_thermal.o \
$(phl_path)$(HAL)/hal_txpwr.o
ifeq ($(CONFIG_PCI_HCI), y)
_HAL_FILES += $(phl_path)$(HAL)/hal_pci.o
endif
ifeq ($(CONFIG_USB_HCI), y)
_HAL_FILES += $(phl_path)$(HAL)/hal_usb.o
endif
ifeq ($(CONFIG_SDIO_HCI), y)
_HAL_FILES += $(phl_path)$(HAL)/hal_sdio.o
endif
########### hal test #################################
ifeq ($(CONFIG_PHL_TEST_SUITE), y)
_HAL_FILES += $(phl_path)$(HAL)/test/hal_test_module.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_cal.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_config.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_efuse.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_reg.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_rx.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_tx.o
_HAL_FILES += $(phl_path)$(HAL)/test/mp/hal_test_mp_txpwr.o
endif
_HAL_FILES += $(phl_path)$(HAL)/efuse/hal_efuse.o
include $(phl_path_d1)/mac/mac.mk
ifeq ($(USE_TRUE_PHY), y)
include $(phl_path_d1)/phy/bb/bb.mk
include $(phl_path_d1)/phy/rf/rf.mk
endif
########### HALBTC #######################################
include $(phl_path_d1)/btc/btc.mk
########### HAL_RTL8852A #################################
ifeq ($(CONFIG_RTL8852A), y)
include $(phl_path_d1)/$(IC_NAME)/rtl8852a.mk
endif
########### HAL_RTL8852B #################################
ifeq ($(CONFIG_RTL8852B), y)
include $(phl_path_d1)/$(IC_NAME)/rtl8852b.mk
endif
########### HAL_RTL8852C #################################
ifeq ($(CONFIG_RTL8852C), y)
include $(phl_path_d1)/$(IC_NAME)/rtl8852c.mk
endif
OBJS += $(_HAL_FILES) $(_HAL_MAC_FILES) $(_BTC_FILES) $(_HAL_IC_FILES)
OBJS += $(_HAL_BB_FILES) $(_HAL_RF_FILES) $(_HAL_EFUSE_FILES)
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal.mk
|
Makefile
|
agpl-3.0
| 3,188
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_ACS_C_
#include "hal_headers.h"
#ifdef CONFIG_RTW_ACS
void rtw_hal_acs_mntr_trigger(void *hal, u16 monitor_time)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
rtw_hal_bb_acs_mntr_trigger(hal_info, monitor_time);
}
enum rtw_hal_status rtw_hal_acs_mntr_result(void *hal, void *rpt)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_bb_acs_mntr_result(hal_info, rpt);
}
#endif /* CONFIG_RTW_ACS */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_acs.c
|
C
|
agpl-3.0
| 1,099
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_ACS_H_
#define _HAL_ACS_H_
void rtw_hal_acs_mntr_trigger(void *hal, u16 monitor_time);
enum rtw_hal_status rtw_hal_acs_mntr_result(void *hal, void *rpt);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_acs.h
|
C
|
agpl-3.0
| 823
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_API_C_
#include "hal_headers.h"
enum rtw_hal_status rtw_hal_get_tsf(void *hal, u8 port, u32 *tsf_h, u32 *tsf_l)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_hal_mac_get_tsf(hal, &port, tsf_h, tsf_l);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_get_tsf(): get failed\n");
}
return status;
}
enum rtw_hal_status
rtw_hal_tsf_sync(void *hal, u8 port_sync_from,
u8 port_sync_to, enum phl_band_idx band,
s32 sync_offset_tu, enum hal_tsf_sync_act act)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_tsf_sync(hal_info, port_sync_from,
port_sync_to, band, sync_offset_tu, act);
}
enum rtw_hal_status
rtw_hal_config_rts_th(void *hal, u8 band_idx, u16 rts_time_th, u16 rts_len_th)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_set_hw_rts_th(hal_info, band_idx, rts_time_th, rts_len_th);
}
u32 rtw_hal_get_btc_req_slot(void *hal)
{
return rtw_hal_btc_req_bt_slot_t(hal);
}
/**
* This function is used to pause/unpause multiple macid
* @hal: see hal_info_t
* @macid_arr: macid array to be pause/unpause
* 1 means to be set (pause/unpause)
* 0 means don't care
* @macid_arr_sz: size of macid array
* @pause: all macid of this array to be paused/unpaused
* 1=paused,0=unpaused
*/
enum rtw_hal_status
rtw_hal_set_macid_grp_pause(void *hal, u32 *macid_arr, u8 arr_size, bool pause)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return rtw_hal_mac_set_macid_grp_pause(hal_com, macid_arr, arr_size, pause);
}
/**
* This function is used to pause/unpause single macid
* @hal: see hal_info_t
* @macid: macid be pause/unpause
* @pause: all macid of this array to be paused/unpaused
* 1=paused,0=unpaused
*/
enum rtw_hal_status
rtw_hal_set_macid_pause(void *hal, u16 macid, bool pause)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return rtw_hal_mac_set_macid_pause(hal_com, macid, pause);
}
enum rtw_hal_status rtw_hal_set_dfs_tb_ctrl(void *hal, u8 set)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_set_dfs_tb_ctrl(hal_info, set);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api.c
|
C
|
agpl-3.0
| 2,923
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_H_
#define _HAL_API_H_
/******************* IO APIs *******************/
u8 rtw_hal_read8(void *h, u32 addr);
u16 rtw_hal_read16(void *h, u32 addr);
u32 rtw_hal_read32(void *h, u32 addr);
void rtw_hal_write8(void *h, u32 addr, u8 val);
void rtw_hal_write16(void *h, u32 addr, u16 val);
void rtw_hal_write32(void *h, u32 addr, u32 val);
u32 rtw_hal_read_macreg(void *h, u32 offset, u32 bit_mask);
void rtw_hal_write_macreg(void *h,
u32 offset, u32 bit_mask, u32 data);
u32 rtw_hal_read_bbreg(void *h, u32 offset, u32 bit_mask);
void rtw_hal_write_bbreg(void *h,
u32 offset, u32 bit_mask, u32 data);
u32 rtw_hal_read_rfreg(void *h,
enum rf_path path, u32 offset, u32 bit_mask);
void rtw_hal_write_rfreg(void *h,
enum rf_path path, u32 offset, u32 bit_mask, u32 data);
#ifdef PHL_PLATFORM_LINUX
void rtw_hal_mac_reg_dump(void *sel, void *h);
void rtw_hal_bb_reg_dump(void *sel, void *h);
void rtw_hal_bb_reg_dump_ex(void *sel, void *h);
void rtw_hal_rf_reg_dump(void *sel, void *h);
#endif
enum rtw_hal_status
rtw_hal_get_addr_cam(void *h, u16 num, u8 *buf, u16 size);
enum rtw_hal_status
rtw_hal_get_sec_cam(void *h, u16 num, u8 *buf, u16 size);
void rtw_hal_enable_interrupt(struct rtw_phl_com_t *phl_com, void *h);
void rtw_hal_disable_interrupt(struct rtw_phl_com_t *phl_com, void *h);
void rtw_hal_config_interrupt(void *h, enum rtw_phl_config_int int_mode);
bool rtw_hal_recognize_interrupt(void *h);
bool rtw_hal_recognize_halt_c2h_interrupt(void *h);
void rtw_hal_clear_interrupt(void *h);
void rtw_hal_restore_interrupt(struct rtw_phl_com_t *phl_com, void *h);
u32 rtw_hal_interrupt_handler(void *h);
void rtw_hal_restore_rx_interrupt(void *h);
enum rtw_hal_status rtw_hal_get_pwr_state(void *h, enum rtw_mac_pwr_st *pwr_state);
enum rtw_hal_status rtw_hal_init(void *drv_priv,
struct rtw_phl_com_t *phl_com, void **hal, enum rtl_ic_id chip_id);
struct rtw_hal_com_t *rtw_hal_get_halcom(void *hal);
void rtw_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal);
bool rtw_hal_is_inited(struct rtw_phl_com_t *phl_com, void *hal);
u32 rtw_hal_hci_cfg(struct rtw_phl_com_t *phl_com, void *hal,
struct rtw_ic_info *ic_info);
u32 rtw_hal_read_chip_info(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_set_default_var(void *hal, enum rtw_hal_set_def_var_rsn rsn);
u32 rtw_hal_var_init(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status rtw_hal_ser_ctrl(void *hal, bool en);
u32
rtw_hal_ser_get_error_status(void *hal, u32 *err);
enum rtw_hal_status rtw_hal_ser_set_error_status(void *hal, u32 err);
enum rtw_hal_status rtw_hal_trigger_cmac_err(void *hal);
enum rtw_hal_status rtw_hal_trigger_dmac_err(void *hal);
enum rtw_hal_status rtw_hal_lv1_rcvy(void *hal, u32 step);
void
rtw_hal_dump_fw_rsvd_ple(void *phl);
void
rtw_hal_ser_reset_wdt_intr(void *hal);
enum rtw_hal_status rtw_hal_cfg_fw_ps_log(void *hal, u8 en);
enum rtw_hal_status rtw_hal_cfg_fw_mcc_log(void *hal, u8 en);
enum rtw_hal_status
rtw_hal_download_fw(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status
rtw_hal_redownload_fw(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_fw_dbg_dump(void *hal, u8 is_low_power);
enum rtw_hal_status rtw_hal_preload(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status rtw_hal_start(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_stop(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status rtw_hal_restart(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status rtw_hal_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal);
#ifdef CONFIG_WOWLAN
enum rtw_hal_status rtw_hal_get_wake_rsn(void *hal, enum rtw_wow_wake_reason *wake_rsn, u8 *reset);
enum rtw_hal_status rtw_hal_cfg_wow_sleep(void *hal, u8 sleep);
enum rtw_hal_status rtw_hal_get_wow_aoac_rpt(void *hal, struct rtw_aoac_report *aoac_info, u8 rx_ready);
enum rtw_hal_status rtw_hal_get_wow_fw_status(void *hal, u8 *status);
enum rtw_hal_status rtw_hal_wow_cfg_txdma(void *hal, u8 en);
enum rtw_hal_status rtw_hal_wow_init(struct rtw_phl_com_t *phl_com, void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status rtw_hal_wow_deinit(struct rtw_phl_com_t *phl_com, void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status rtw_hal_wow_func_en(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg);
enum rtw_hal_status rtw_hal_wow_func_dis(struct rtw_phl_com_t *phl_com, void *hal, u16 macid);
enum rtw_hal_status rtw_hal_wow_func_start(struct rtw_phl_com_t *phl_com, void *hal, u16 macid, struct rtw_hal_wow_cfg *cfg);
enum rtw_hal_status rtw_hal_wow_func_stop(struct rtw_phl_com_t *phl_com, void *hal, u16 macid);
enum rtw_hal_status rtw_hal_set_wowlan(struct rtw_phl_com_t *phl_com, void *hal, u8 enter);
enum rtw_hal_status rtw_hal_sw_gpio_ctrl(struct rtw_phl_com_t *phl_com, void *hal, u8 high, u8 gpio);
enum rtw_hal_status rtw_hal_set_sw_gpio_mode(struct rtw_phl_com_t *phl_com, void *hal, enum rtw_gpio_mode mode, u8 gpio);
enum rtw_hal_status rtw_hal_wow_drop_tx(void *hal, u8 band);
#endif /* CONFIG_WOWLAN */
void
rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, char *ic_name, void *hal);
enum rtw_hal_status rtw_hal_trx_init(void *hal, u8 *txbd_buf, u8 *rxbd_buf);
void rtw_hal_trx_deinit(void *hal);
enum rtw_hal_status
rtw_hal_role_cfg(void *hal, struct rtw_wifi_role_t *wrole);
enum rtw_hal_status
rtw_hal_role_cfg_ex(void *hal, struct rtw_wifi_role_t *wrole,
enum pcfg_type type, void *param);
enum rtw_hal_status
rtw_hal_beacon_stop(void *hal, struct rtw_wifi_role_t *wrole, bool stop);
enum rtw_hal_status
rtw_hal_stainfo_init(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_stainfo_deinit(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_add_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_del_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_update_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta,
bool is_connect);
enum rtw_hal_status
rtw_hal_change_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta,
enum phl_upd_mode mode);
u8 rtw_hal_get_sta_rssi(struct rtw_phl_stainfo_t *sta);
u8 rtw_hal_get_sta_rssi_bcn(struct rtw_phl_stainfo_t *sta);
bool rtw_hal_is_sta_linked(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_set_sta_rx_sts(struct rtw_phl_stainfo_t *sta, u8 rst,
struct rtw_r_meta_data *meta);
enum rtw_hal_status
rtw_hal_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta,
struct rtw_phl_rainfo *phl_rainfo);
enum rtw_hal_status
rtw_hal_start_ba_session(void *hal, struct rtw_phl_stainfo_t *sta,
u8 dialog_token, u16 timeout, u16 start_seq_num,
u16 ba_policy, u16 tid, u16 buf_size);
enum rtw_hal_status
rtw_hal_stop_ba_session(void *hal, struct rtw_phl_stainfo_t *sta, u16 tid);
/**
* rtw_hal_set_edca() - setup WMM EDCA parameter
* @hal: struct hal_info_t *
* @wrole: struct rtw_wifi_role_t *
* @ac: Access Category, 0:BE, 1:BK, 2:VI, 3:VO
* @param: AIFS:BIT[7:0], CWMIN:BIT[11:8], CWMAX:BIT[15:12],
* TXOP:BIT[31:16]
*
* Setup WMM EDCA parameter set for sending packets.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status
rtw_hal_set_edca(void *hal, struct rtw_wifi_role_t *wrole, u8 ac, u32 edca);
enum rtw_hal_status
rtw_hal_cfg_tx_ampdu(void *hal, struct rtw_phl_stainfo_t *sta);
#ifdef CONFIG_PHL_CUSTOM_FEATURE
enum rtw_hal_status
rtw_hal_custom_cfg_tx_ampdu(void *hal,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_custom_ampdu_cfg *ampdu);
enum rtw_hal_status
rtw_hal_get_ampdu_cfg(void *hal,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_custom_ampdu_cfg *cfg);
enum rtw_hal_status
rtw_hal_set_pop_en(void *hal, bool en, enum phl_phy_idx phy_idx);
bool
rtw_hal_query_pop_en(void *hal, enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_set_pkt_detect_thold(void *hal, u32 bound);
u8
rtw_hal_query_pkt_detect_thold(void *hal,
bool get_en_info,
enum phl_phy_idx phy_idx);
#endif
enum rtw_hal_status
rtw_hal_thermal_protect_cfg_tx_duty(
void *hal,
u16 tx_duty_interval,
u8 ratio);
enum rtw_hal_status
rtw_hal_thermal_protect_stop_tx_duty(
void *hal);
enum rtw_hal_status
rtw_hal_set_key(void *hal, struct rtw_phl_stainfo_t *sta, u8 type, u8 ext_key, u8 spp,
u8 keyid, u8 keytype, u8 *keybuf);
u32
rtw_hal_search_key_idx(void *hal, struct rtw_phl_stainfo_t *sta,
u8 keyid, u8 keytype);
/**
* rtw_hal_tx_chnl_mapping - query hw tx dma channel mapping to the sw xmit ring
* identified by macid, tid and band
* @hal: see struct hal_info_t
* @macid: input target macid is 0 ~ 127
* @cat: input target packet category, see enum rtw_phl_ring_cat
* @band: input target band, 0 for band 0 / 1 for band 1
*
* returns the mapping hw tx dma channel
*/
u8 rtw_hal_tx_chnl_mapping(void *hal, u16 macid,
enum rtw_phl_ring_cat cat, u8 band);
/**
* rtw_hal_convert_qsel_to_tid - convert qsel to tid value
* @hal: see struct hal_info_t
* @qsel: HW queue selection
* @tid_indic: tid indicator
*
* returns enum RTW_HAL_STATUS
*/
u8 rtw_hal_convert_qsel_to_tid(void *hal, u8 qsel_id, u8 tid_indic);
/**
* rtw_hal_tx_res_query - query current HW tx resource with specifc dma channel
* @hal: see struct hal_info_t
* @dma_ch: the target dma channel
* @host_idx: current host index of this channel
* @hw_idx: current hw index of this channel
*
* this function returns the number of available tx resource
* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
*/
u16 rtw_hal_tx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx);
/**
* rtw_hal_rx_res_query - query current HW rx resource with specifc dma channel
* @hal: see struct hal_info_t
* @dma_ch: the target dma channel
* @host_idx: current host index of this channel
* @hw_idx: current hw index of this channel
*
* this function returns the number of available tx resource
* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
*/
u16 rtw_hal_rx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx);
/**
* rtw_hal_query_txch_num - query total hw tx dma channels number
*
* returns the number of hw tx dma channel
*/
u8 rtw_hal_query_txch_num(void *hal);
/**
* rtw_hal_query_rxch_num - query total hw rx dma channels number
*
* returns the number of hw rx dma channel
*/
u8 rtw_hal_query_rxch_num(void *hal);
/**
* rtw_hal_update_wd_page - update wd page for xmit packet
* @hal: see struct hal_info_t
* @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req
*
* returns enum RTW_HAL_STATUS
*/
enum rtw_hal_status rtw_hal_update_wd_page(void *hal, void *phl_pkt_req);
enum rtw_hal_status
rtw_hal_handle_rx_buffer(struct rtw_phl_com_t *phl_com, void* hal,
u8 *buf, u32 buf_size,
struct rtw_phl_rx_pkt *rxpkt);
enum rtw_hal_status
rtw_hal_query_info(void* hal, u8 info_id, void *value);
#ifdef CONFIG_PHL_DFS
bool rtw_hal_in_radar_domain(void *hal, u8 ch, enum channel_width bw);
enum rtw_hal_status rtw_hal_radar_detect_cfg(void *hal, bool dfs_enable);
#endif /*CONFIG_PHL_DFS*/
enum rtw_hal_status
rtw_hal_set_ch_bw(void *hal, u8 band_idx,
struct rtw_chan_def *chdef, bool do_rfk);
u8 rtw_hal_get_cur_ch(void *hal, u8 band_idx);
void rtw_hal_get_cur_chdef(void *hal, u8 band_idx,
struct rtw_chan_def *cur_chandef);
void rtw_hal_sync_cur_ch(void *hal, u8 band_idx, struct rtw_chan_def chandef);
u8 rtw_hal_get_fwcmd_queue_idx(void* hal);
void rtw_hal_cfg_txhci(void *hal, u8 en);
void rtw_hal_cfg_rxhci(void *hal, u8 en);
enum rtw_hal_status rtw_hal_chk_allq_empty(void *hal, u8 *empty);
s8 rtw_hal_rf_get_power_limit(void *hal, enum phl_phy_idx phy,
u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel);
enum rtw_hal_status rtw_hal_set_power_lmt(void *hal, u8 band_idx);
void rtw_hal_enable_ext_pwr_lmt(void *hal, u8 hw_band,
struct rtw_tpu_ext_pwr_lmt_info *ext_pwr_lmt_info);
#ifdef CONFIG_RTW_ACS
void rtw_hal_acs_mntr_trigger(void *hal, u16 monitor_time);
enum rtw_hal_status rtw_hal_acs_mntr_result(void *hal, void *rpt);
#endif /* CONFIG_RTW_ACS */
/*watchdog update env result*/
void rtw_hal_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt,
struct rtw_wifi_role_t *wrole);
#ifdef CONFIG_PCI_HCI
/**
* rtw_hal_update_txbd - update tx bd for xmit packet
* @hal: see struct hal_info_t
* @txbd: the target txbd to update
* @wd: buffer pointer of wd page to fill in txbd
*
* returns enum RTW_HAL_STATUS
* NOTE, this function is PCIe specific function
*/
enum rtw_hal_status
rtw_hal_update_txbd(void *hal, void *txbd, void *wd, u8 dma_ch, u16 wd_num);
/**
* rtw_hal_update_rxbd - update rx bd for recv packet
* @hal: see struct hal_info_t
* @rxbd: the target rxbd to update
* @wd: buffer pointer of wd page to fill in rxbd
*
* returns enum RTW_HAL_STATUS
* NOTE, this function is PCIe specific function
*/
enum rtw_hal_status
rtw_hal_update_rxbd(void *hal, struct rx_base_desc *rxbd,
struct rtw_rx_buf *rxbuf);
/**
* rtw_hal_update_trigger_txstart - trigger hw to start tx
* @hal: see struct hal_info_t
* @txbd: the target txbd to update
* @dma_ch: the dma channel index of this txbd_ring
*
* returns enum RTW_HAL_STATUS
*/
enum rtw_hal_status rtw_hal_trigger_txstart(void *hal, void *txbd, u8 dma_ch);
/**
* rtw_hal_notify_rxdone - notify hw rx done
* @hal: see struct hal_info_t
* @rxbd: the target rxbd to update
* @ch: the target rx channel
* @rxcnt: handling done rx count this function will notify hw
*
* returns enum RTW_HAL_STATUS
*/
enum rtw_hal_status rtw_hal_notify_rxdone(void* hal, void *rxbd, u8 ch,
u16 rxcnt);
/**
* rtw_hal_handle_wp_rpt -parsing the wp recycle report packet
* @hal: see struct hal_info_t
* @rp: input, the pointer of target recycle report buffer to parse
* @len: input, the length of this report buffer
* @sw_retry: output, the packet mentioned in this report needs sw retry if sw_retry == 1
* @dma_ch: output, the tx dma channel of this packet mentioned in this report
* @wp_seq: output, the wp_seq of this packet mentioned in this report
* @txsts: output, the tx status of this packet mentioned in this report
*
* returns the length of report buffer which has been parsed in this function
*/
u16 rtw_hal_handle_wp_rpt(void *hal, u8 *rp, u16 len, u8 *sw_retry, u8 *dma_ch,
u16 *wp_seq, u8 *txsts);
u8 rtw_hal_check_rxrdy(struct rtw_phl_com_t *phl_com, void* hal, u8 *rxbuf, u8 dma_ch);
u8 rtw_hal_handle_rxbd_info(void* hal, u8 *rxbuf, u16 *buf_size);
enum rtw_hal_status rtw_hal_set_l2_leave(void *hal);
void rtw_hal_clear_bdidx(void *hal);
void rtw_hal_rst_bdram(void *hal);
bool rtw_hal_poll_txdma_idle(void *hal);
void rtw_hal_cfg_dma_io(void *hal, u8 en);
enum rtw_hal_status rtw_hal_ltr_sw_trigger(void *hal,
enum rtw_pcie_ltr_state state);
enum rtw_hal_status rtw_hal_ltr_en_hw_mode(void *hal, bool hw_mode);
#ifdef RTW_WKARD_DYNAMIC_LTR
void rtw_hal_ltr_update_stats(void *hal, bool clear);
bool rtw_hal_ltr_is_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal);
bool rtw_hal_ltr_is_hw_ctrl(struct rtw_phl_com_t *phl_com, void *hal);
#endif
#endif /*CONFIG_PCI_HCI*/
#ifdef CONFIG_USB_HCI
u8 rtw_hal_get_bulkout_id(void *hal, u8 dma_ch, u8 mode);
enum rtw_hal_status rtw_hal_fill_wd(void *hal,
struct rtw_xmit_req *tx_req,
u8 *wd_buf, u32 *wd_len);
enum rtw_hal_status
rtw_hal_usb_tx_agg_cfg(void *hal, u8* wd_buf, u8 agg_num);
enum rtw_hal_status
rtw_hal_usb_rx_agg_cfg(void *hal, u8 mode, u8 agg_mode,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num);
u8 rtw_hal_get_max_bulkout_wd_num(void *hal);
u32 rtwl_hal_get_cur_usb_mode(void *h);
u32 rtwl_hal_get_usb_support_ability(void *h);
enum rtw_hal_status rtw_hal_force_usb_switch(void *h, enum usb_type type);
/**
* rtw_hal_handle_wp_rpt_usb -parsing the wp recycle report packet
* @hal: see struct hal_info_t
* @rp: input, the pointer of target recycle report buffer to parse
* @len: input, the length of this report buffer
* @macid: output, the mac_id of this packet mentioned in this report
* @ac_queue: output, the tid of this packet mentioned in this report
* @txsts: output, the tx status of this packet mentioned in this report
*
* returns the length of report buffer which has been parsed in this function
*/
u16 rtw_hal_handle_wp_rpt_usb(void *hal, u8 *rp, u16 len, u8 *macid, u8 *ac_queue,
u8 *txsts);
#endif
#ifdef CONFIG_SDIO_HCI
/**
* rtw_hal_sdio_tx_cfg - SDIO TX related setting
* @hal: pointer of struct hal_info_t
*
* Configure setting for SDIO TX.
*
* No return value for this function.
*/
void rtw_hal_sdio_tx_cfg(void *hal);
enum rtw_hal_status rtw_hal_sdio_tx(void *hal, u8 dma_ch, u8 *buf, u32 buf_len,
u8 agg_count, u16 *pkt_len, u8 *wp_offset);
void rtw_hal_sdio_rx_agg_cfg(void *hal, bool enable, u8 drv_define,
u8 timeout, u8 size, u8 pkt_num);
int rtw_hal_sdio_rx(void *hal, struct rtw_rx_buf *rxbuf);
int rtw_hal_sdio_parse_rx(void *hal, struct rtw_rx_buf *rxbuf);
#endif /* CONFIG_SDIO_HCI */
/* HAL SOUND API */
enum rtw_hal_status rtw_hal_snd_query_proc_sta_res(
void *hal, struct rtw_phl_stainfo_t *sta,
bool mu, enum channel_width bw, bool en_swap);
enum rtw_hal_status
rtw_hal_snd_release_proc_sta_res(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_snd_proc_pre_cfg_sta(void *hal, struct rtw_phl_stainfo_t *sta);
void
rtw_hal_snd_ndpa_sta_info_vht(struct rtw_phl_stainfo_t *psta_info,
u32 *ndpa, u8 mu);
void
rtw_hal_snd_ndpa_sta_info_he(struct rtw_phl_stainfo_t *psta_info,
u32 *ndpa, enum channel_width bw, u8 fb_type);
enum rtw_hal_status
rtw_hal_snd_proc_post_cfg_sta(void *hal,
struct rtw_phl_stainfo_t *sta, bool mu);
enum rtw_hal_status
rtw_hal_snd_proc_post_cfg_gid(void *hal, u8 gid, void *ba_info);
enum rtw_hal_status
rtw_hal_snd_proc_post_cfg(void *hal, bool he, bool mu, bool en_fixed_mode);
enum rtw_hal_status
rtw_hal_snd_mac_ctrl(void *hal, u8 band, u8 ctrl);
enum rtw_hal_status
rtw_hal_snd_chk_bf_res(void *hal, struct rtw_phl_stainfo_t *sta,
bool mu, enum channel_width bw);
void
rtw_hal_snd_polling_snd_sts(void *hal, struct rtw_phl_stainfo_t *sta);
/* fw sounding commmand ralated */
void rtw_hal_snd_set_fw_cmd_dialogtkn(void *hal, u8 *buf, u8 he, u8 token);
void rtw_hal_snd_vht_fwcmd_su(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u32 *npda_sta);
void rtw_hal_snd_vht_fwcmd_mu_pri(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u8 sta_nr, u32 *ndpa_sta);
void rtw_hal_snd_vht_fwcmd_mu_add_sta(void *hal, u8 *buf, u32 *ndpa_sta,
struct rtw_phl_stainfo_t *sta,
u8 ndpa_idx, u8 last);
void rtw_hal_snd_ax_fwcmd_nontb(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u32 *npda_sta);
void rtw_hal_snd_ax_fwcmd_tb_pri(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u8 sta_nr1, u8 sta_nr2);
void rtw_hal_snd_ax_fwcmd_tb_add_sta(void *hal, u8 *buf, u32 *ndpa_sta,
struct rtw_phl_stainfo_t *sta, u8 ru_idx,
u8 ndpa_idx, u8 bfrp_idx, u8 bfrp_u_idx);
u8 *rtw_hal_snd_prepare_snd_cmd(void *hal);
enum rtw_hal_status rtw_hal_snd_release_snd_cmd(void *hal, u8 *buf);
enum rtw_hal_status rtw_hal_snd_send_fw_cmd(void *hal, u8 *cmd);
/*HAL CSI Buffer Mgnt APIs*/
enum channel_width
rtw_hal_get_csi_buf_bw(void *buf);
bool
rtw_hal_get_csi_buf_type(void *buf);
/*HAL Beamform Mgnt APIs*/
void rtw_hal_bf_dbg_dump_entry(void *entry);
void rtw_hal_bf_dbg_dump_entry_all(void *hal);
u8 rtw_hal_bf_get_sumu_idx(void *hal, void *entry);
bool rtw_hal_bf_chk_bf_type(void *hal_info,
struct rtw_phl_stainfo_t *sta, bool mu);
void rtw_hal_bf_preset_mu_ba_info(void *hal,
struct rtw_phl_stainfo_t *psta, void *hal_ba_info);
void rtw_hal_bf_set_txmu_para(void *hal, u8 gid , u8 en,
enum rtw_hal_protection_type rts_type,
enum rtw_hal_ack_resp_type ack_type);
enum rtw_hal_status
rtw_hal_bf_set_fix_mode(void *hal, bool mu, bool he);
enum rtw_hal_status
rtw_hal_bf_get_entry_snd_sts(void *entry);
void rtw_hal_beamform_set_vht_gid(void *hal, u8 band,
struct rtw_phl_gid_pos_tbl *tbl);
/******************************************************************************
*
* BTC APIs
*
*****************************************************************************/
#ifdef CONFIG_BTCOEX
void rtw_hal_btc_scan_start_ntfy(void *hinfo, enum phl_phy_idx phy_idx,
enum band_type band);
void rtw_hal_btc_scan_finish_ntfy(void *hinfo, enum phl_phy_idx phy_idx);
void rtw_hal_btc_update_role_info_ntfy(void *hinfo, u8 role_id,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta,
enum role_state rstate);
void rtw_hal_btc_packet_event_ntfy(void *hinfo, u8 pkt_evt_type);
void rtw_hal_btc_radio_state_ntfy(void *hinfo, u8 rf_state);
void rtw_hal_btc_customerize_ntfy(void *hinfo, u8 type, u16 len, u8 *buf);
void rtw_hal_btc_wl_status_ntfy(void *hinfo, struct rtw_phl_com_t *phl_com, u8 ntfy_num,
struct rtw_phl_stainfo_t *sta[],
u8 reason);
void rtw_hal_btc_timer(void *hinfo, void *timer);
void rtw_hal_btc_fwinfo_ntfy(void *hinfo);
#endif
enum rtw_hal_status rtw_hal_scan_set_rxfltr_by_mode(void *hinfo,
enum phl_phy_idx phy_idx, bool off_channel, u8 *mode);
enum rtw_hal_status
rtw_hal_enter_mon_mode(void *hinfo, enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_leave_mon_mode(void *hinfo, enum phl_phy_idx phy_idx);
#ifdef CONFIG_FSM
enum rtw_hal_status rtw_hal_scan_flush_queue(void *hinfo,
struct rtw_wifi_role_t *wrole);
#endif
enum rtw_hal_status rtw_hal_scan_pause_tx_fifo(void *hinfo,
u8 band_idx, bool off_ch);
enum rtw_hal_status rtw_hal_dfs_pause_tx(void *hinfo,
u8 band_idx, bool off_ch);
/*****************************************************************************/
void rtw_hal_com_scan_set_tx_lifetime(void *hal, u8 band);
void rtw_hal_com_scan_restore_tx_lifetime(void *hal, u8 band);
#ifdef RTW_PHL_BCN
enum rtw_hal_status
rtw_hal_add_beacon(struct rtw_phl_com_t *phl_com, void *hal, void *bcn_cmn);
enum rtw_hal_status
rtw_hal_update_beacon(struct rtw_phl_com_t *phl_com, void *hal, u8 bcn_id);
enum rtw_hal_status
rtw_hal_free_beacon(struct rtw_phl_com_t *phl_com, void *hal, u8 bcn_id);
#endif
enum rtw_hal_status
rtw_hal_proc_cmd(void *hal, char proc_cmd, struct rtw_proc_cmd *incmd,
char *output, u32 out_len);
void rtw_hal_get_fw_ver(void *hal, char *ver_str, u16 len);
enum rtw_hal_status
rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com,
u8 band_idx, bool tx_pause, enum tx_pause_rson rson);
enum rtw_hal_status rtw_hal_set_macid_pause(void *hinfo,
u16 macid,
bool pause);
/**
* rtw_hal_set_rxfltr_by_mode - Set rx filter option by scenario
* @hal: pointer of struct hal_info_t
* @band: 0x0: band0, 0x1: band1
* @mode: scenario mode
*
* Set RX filter setting by scenario.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status rtw_hal_set_rxfltr_by_mode(void *hal, u8 band,
enum rtw_rx_fltr_mode mode);
/**
* rtw_hal_get_rxfltr_mode - Get rx filter option
* @hal: pointer of struct hal_info_t
* @band: 0x0: band0, 0x1: band1
*
* Get RX filter mode
*
* Return rtw_rx_fltr_mode
*/
enum rtw_rx_fltr_mode rtw_hal_get_rxfltr_mode(void *hal, u8 band);
/**
* rtw_hal_mac_acpt_crc_err_pkt - Accept CRC error packets or not
* @hal: pointer of struct rtw_hal_info_t
* @band: 0x0: band0, 0x1: band1
* @enable: 0: deny, 1: accept
*
* Control accepting CRC error packets or not.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status rtw_hal_acpt_crc_err_pkt(void *hal, u8 band, u8 enable);
/**
* rtw_hal_set_rxfltr_mpdu_size - Set max MPDU size
* @hal: pointer of struct hal_info_t
* @band: 0x0: band0, 0x1: band1
* @size: MPDU max size, unit: byte. 0 for no limit.
*
* MPDU size exceed max size would be dropped.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status rtw_hal_set_rxfltr_mpdu_size(void *hal, u8 band, u16 size);
enum rtw_hal_status rtw_hal_set_rxfltr_by_type(void *hal, u8 band, u8 type,u8 target);
enum rtw_hal_status
rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value);
void rtw_hal_dbg_status_dump(void *hal, struct hal_mac_dbg_dump_cfg *cfg);
/******************************************************************************
*
* Packet Offload APIs
*
*****************************************************************************/
enum rtw_hal_status rtw_hal_reset_pkt_ofld_state(void *hal);
enum rtw_hal_status rtw_hal_pkt_ofld(void *hal, u8 *id, u8 op,
u8 *pkt, u16 *len);
enum rtw_hal_status rtw_hal_pkt_update_ids(void *hal,
struct pkt_ofld_entry *entry);
void rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_fw_final_cap_config(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_final_cap_decision(struct rtw_phl_com_t *phl_com, void *hal);
/******************************************************************************
*
* Power Save APIs
*
*****************************************************************************/
enum rtw_hal_status
rtw_hal_ps_pwr_lvl_cfg(struct rtw_phl_com_t *phl_com, void *hal,
u32 req_pwr_lvl);
enum rtw_hal_status
rtw_hal_ps_lps_cfg(void *hal, struct rtw_hal_lps_info *lps_info);
enum rtw_hal_status
rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
u8 band, struct protocol_cap_t *proto_cap);
enum rtw_hal_status
rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
u8 band, struct protocol_cap_t *proto_cap);
enum rtw_hal_status rtw_hal_rf_chl_rfk_trigger(void *hal, u8 phy_idx, u8 force);
enum rtw_hal_status rtw_hal_watchdog(void *hal);
enum rtw_hal_status rtw_hal_simple_watchdog(void *hal, u8 io_en);
/******************************************************************************
*
* TWT APIs
*
*****************************************************************************/
#ifdef CONFIG_PHL_TWT
enum rtw_hal_status
rtw_hal_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info,
struct rtw_wifi_role_t *role, u8 action);
enum rtw_hal_status
rtw_hal_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action);
enum rtw_hal_status
rtw_hal_twt_sta_announce(void *hal, u8 macid);
#endif /* CONFIG_PHL_TWT */
/******************************************************************************
*
* BB APIs
*
*****************************************************************************/
/*@--------------------------[Prptotype]-------------------------------------*/
/**
* rtw_hal_bb_get_txsc input arguments:
* @hal_com: hal com info
* @pri_ch: Spec-defined primary channel index
* @central_ch: Spec-defined central channel index
* @cbw: Channel BW
* @dbw: Data BW
*/
u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch,
u8 central_ch, enum channel_width cbw, enum channel_width dbw);
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_hal_status
rtw_hal_dbcc_pre_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en);
enum rtw_hal_status
rtw_hal_dbcc_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en);
enum rtw_hal_status
rtw_hal_clean_tx_queue(void *hal);
enum rtw_hal_status
rtw_hal_dbcc_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band);
enum rtw_hal_status
rtw_hal_dbcc_reset_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band);
#endif
/*
* API for config channel info CR
*/
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status
rtw_hal_cfg_chinfo(void *hal, struct rtw_phl_stainfo_t *sta, u8 enable);
#endif /* CONFIG_PHL_CHANNEL_INFO */
enum rtw_hal_status
rtw_hal_get_efuse_info(void *hal, enum rtw_efuse_info info_type,
void *value, u8 size);
enum rtw_hal_status
rtw_hal_cfg_trx_path(void *hal, enum rf_path tx, u8 tx_nss,
enum rf_path rx, u8 rx_nss);
enum rtw_hal_status
rtw_hal_tsf_sync(void *hal, u8 wrole_sync_from, u8 wrole_sync_to,
enum phl_band_idx band, s32 sync_offset_tu,
enum hal_tsf_sync_act act);
/**
* rtw_hal_fill_txdesc() - Fill hardware tx header
* @hal: pointer of struct hal_info_t
* @treq: the xmit request for this tx descriptor
* @wd_buf: the wd buffer to fill
* @wd_len: output, return the total length of filled wd
*
* Fill hardware tx header/tx descriptor/wifi descriptor
*
* Return RTW_HAL_STATUS_SUCCESS when everything is ok.
*/
enum rtw_hal_status rtw_hal_fill_txdesc(void *hal, struct rtw_xmit_req *treq,
u8 *wd_buf, u32 *wd_len);
enum rtw_hal_status rtw_hal_poll_hw_tx_done(void *hal);
enum rtw_hal_status rtw_hal_hw_tx_resume(void *hal);
enum rtw_hal_status rtw_hal_poll_hw_rx_done(void *hal);
enum rtw_hal_status rtw_hal_hw_rx_resume(void *hal);
void rtw_hal_tx_dbg_status_dump(void *hal);
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
enum rtw_hal_status rtw_hal_bf_bfee_ctrl(void *hal, u8 band, bool ctrl);
#endif
enum rtw_hal_status
rtw_hal_set_mu_edca(void *hal, u8 band, u8 ac,
u16 timer, u8 cw_min, u8 cw_max, u8 aifsn);
enum rtw_hal_status
rtw_hal_set_mu_edca_ctrl(void *hal, u8 band, u8 wmm, u8 set);
enum rtw_hal_status rtw_hal_led_set_ctrl_mode(void *hal, enum rtw_led_id led_id,
enum rtw_led_ctrl_mode ctrl_mode);
enum rtw_hal_status rtw_hal_led_control(void *hal, enum rtw_led_id led_id,
u8 high);
enum rtw_hal_status rtw_hal_pcie_trx_mit(void *hal, u32 tx_timer, u8 tx_counter,
u32 rx_timer, u8 rx_counter);
enum rtw_hal_status rtw_hal_get_tsf(void *hal, u8 port, u32 *tsf_h, u32 *tsf_l);
u32 rtw_hal_get_btc_req_slot(void *hal);
enum rtw_hal_status
rtw_hal_set_macid_pause(void *hal, u16 macid, bool pause);
enum rtw_hal_status
rtw_hal_set_macid_grp_pause(void *hal, u32 *macid_arr, u8 arr_size, bool pause);
#ifdef CONFIG_MCC_SUPPORT
enum rtw_hal_status rtw_hal_mcc_get_2ports_tsf(void *hal, u8 group,
u16 macid_x, u16 macid_y, u32 *tsf_x_h, u32 *tsf_x_l,
u32 *tsf_y_h, u32 *tsf_y_l);
enum rtw_hal_status rtw_hal_mcc_update_macid_bitmap(void *hal, u8 group,
u16 macid, struct rtw_phl_mcc_macid_bitmap *info);
enum rtw_hal_status rtw_hal_mcc_sync_enable(void *hal,
struct rtw_phl_mcc_en_info *info);
enum rtw_hal_status rtw_hal_mcc_change_pattern(void *hal,
struct rtw_phl_mcc_en_info *ori_info,
struct rtw_phl_mcc_en_info *new_info,
struct rtw_phl_mcc_bt_info *new_bt_info);
enum rtw_hal_status rtw_hal_mcc_disable(void *hal, u8 group, u16 macid);
enum rtw_hal_status rtw_hal_mcc_enable(void *hal, struct rtw_phl_mcc_en_info *info,
struct rtw_phl_mcc_bt_info *bt_info);
#endif /* CONFIG_MCC_SUPPORT */
#ifdef CONFIG_PHL_P2PPS
enum rtw_hal_status rtw_hal_noa_enable(void *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid);
enum rtw_hal_status rtw_hal_noa_disable(void *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid);
enum rtw_hal_status rtw_hal_tsf32_tog_enable(void *hal,
struct rtw_wifi_role_t *w_role);
enum rtw_hal_status rtw_hal_tsf32_tog_disable(void *hal,
struct rtw_wifi_role_t *w_role);
enum rtw_hal_status rtw_hal_get_tsf32_tog_rpt(void *hal,
struct rtw_phl_tsf32_tog_rpt *rpt);
#endif
void rtw_hal_disconnect_notify(void *hal, struct rtw_chan_def *chandef);
bool rtw_hal_check_ch_rfk(void *hal, struct rtw_chan_def *chandef);
enum rtw_hal_status rtw_hal_ppdu_sts_cfg(void *hal, u8 band_idx, bool en);
void rtw_hal_notification(void *hal, enum phl_msg_evt_id event, u8 hw_idx);
void rtw_hal_cmd_notification(void *hal,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx);
enum rtw_hal_status
rtw_hal_config_rts_th(void *hal, u8 band_idx, u16 rts_time_th, u16 rts_len_th);
enum rtw_hal_status
rtw_hal_query_txsts_rpt(void *hal, u16 macid);
enum rtw_hal_status rtw_hal_set_dfs_tb_ctrl(void *hal, u8 set);
enum rtw_hal_status
rtw_hal_thermal_protect_cfg_tx_ampdu(
void *hal,
struct rtw_phl_stainfo_t *sta,
u8 ratio);
bool rtw_hal_check_thermal_protect(
struct rtw_phl_com_t *phl_com,
void *hal);
enum rtw_hal_status
rtw_hal_beamform_set_aid(void *hal, struct rtw_phl_stainfo_t *sta, u16 aid);
/******************************************************************************
*
* TX power APIs
*
*****************************************************************************/
const char *rtw_hal_get_pw_lmt_regu_type_str(void *hal, enum band_type band);
bool rtw_hal_get_pwr_lmt_en(void *hal, u8 band_idx);
enum rtw_hal_status rtw_hal_set_tx_power(void *hal, u8 band_idx,
enum phl_pwr_table pwr_table);
#endif /*_HAL_API_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api.h
|
C
|
agpl-3.0
| 33,489
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_API_BB_C_
#include "hal_headers.h"
#include "phy/bb/halbb_export_fun.h"
//kevin-cmd
#include "phy/bb/halbb_hw_cfg_ex.h"
#ifdef USE_TRUE_PHY
enum phl_phy_idx rtw_hal_bb_band_to_phy_idx(struct rtw_hal_com_t *hal_com, u8 band_idx)
{
enum phl_phy_idx p_idx = HW_PHY_0;
if (band_idx == 1)
p_idx = HW_PHY_1;
return p_idx;
}
void rtw_hal_bb_dfs_en(struct hal_info_t *hal_info, bool en)
{
halbb_dfs_en(hal_info->bb, en);
}
void rtw_hal_bb_tssi_cont_en(struct hal_info_t *hal_info, bool en, enum rf_path path)
{
halbb_tssi_cont_en(hal_info->bb, en, path);
}
void rtw_hal_bb_adc_en(struct hal_info_t *hal_info, bool en)
{
halbb_adc_en(hal_info->bb, en);
}
void rtw_hal_bb_reset_en(struct hal_info_t *hal_info, bool en, enum phl_phy_idx phy_idx)
{
halbb_bb_reset_en(hal_info->bb, en, phy_idx);
}
bool rtw_hal_bb_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
if(incmd->in_type == RTW_ARG_TYPE_BUF)
halbb_cmd(hal_info->bb, incmd->in.buf, output, out_len);
else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){
halbb_cmd_parser(hal_info->bb, incmd->in.vector,
incmd->in_cnt_len, output, out_len);
}
return true;
}
enum rtw_hal_status rtw_hal_bb_watchdog(struct hal_info_t *hal_info, u8 is_lps)
{
enum bb_watchdog_mode_t mode = BB_WATCHDOG_NORMAL;
if (is_lps)
mode = BB_WATCHDOG_LOW_IO;
halbb_watchdog(hal_info->bb, mode, HW_PHY_0);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_simple_watchdog(struct hal_info_t *hal_info, u8 io_en)
{
enum bb_watchdog_mode_t mode = BB_WATCHDOG_NON_IO;
if (io_en)
mode = BB_WATCHDOG_LOW_IO;
halbb_watchdog(hal_info->bb, mode, HW_PHY_0);
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_reset(struct hal_info_t *hal_info)
{
halbb_watchdog_reset(hal_info->bb);
}
void rtw_hal_bb_fw_edcca(struct hal_info_t *hal_info)
{
PHL_INFO("[Cert], %s() ==> !! \n", __func__);
halbb_fw_edcca(hal_info->bb);
}
void rtw_hal_bb_dm_init(struct hal_info_t *hal_info)
{
halbb_dm_init(hal_info->bb, HW_PHY_0);
}
void rtw_hal_bb_dm_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
halbb_dm_deinit(phl_com, hal_info->bb);
}
enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com,
bool cca_en, enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
halbb_ctrl_rx_cca(hal->bb, cca_en, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_ctrl_dbcc(struct hal_info_t *hal_info, bool dbcc_en)
{
halbb_ctrl_dbcc(hal_info->bb, dbcc_en);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_cfg_dbcc(struct hal_info_t *hal_info, bool dbcc_en)
{
halbb_cfg_dbcc(hal_info->bb, dbcc_en);
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_bb_init(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hal_status;
hal_status = halbb_buffer_init(phl_com, hal_com, &(hal_info->bb));
if ((hal_status != RTW_HAL_STATUS_SUCCESS) || (hal_info->bb == NULL))
PHL_ERR("[PHL] rtw_hal_bb_init failed status(%d), hal_info->bb(%p)\n",
hal_status, hal_info->bb);
return hal_status;
}
void rtw_hal_bb_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
halbb_buffer_deinit(phl_com, hal_com, hal_info->bb);
}
void rtw_hal_init_bb_reg(struct hal_info_t *hal_info)
{
halbb_init_reg(hal_info->bb);
halbb_reset_bb(hal_info->bb);
}
u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
return halbb_read_rf_reg(hal->bb, path, addr, mask);
}
bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask, u32 data)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
return halbb_write_rf_reg(hal->bb, path, addr, mask, data);
}
u32 rtw_hal_read_bb_reg(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
return halbb_get_reg(hal->bb, addr, mask);
}
bool rtw_hal_write_bb_reg(struct rtw_hal_com_t *hal_com,
u32 addr, u32 mask, u32 data)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
halbb_set_reg(hal->bb, addr, mask, data);
return true;
}
u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
return halbb_rf_get_bb_reg(hal->bb, addr, mask);
}
bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com,
u32 addr, u32 mask, u32 data)
{
struct hal_info_t *hal = (struct hal_info_t *)hal_com->hal_priv;
return halbb_rf_set_bb_reg(hal->bb, addr, mask, data);
}
enum rtw_hal_status
rtw_hal_bb_stainfo_init(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if (halbb_sta_info_init(hal_info->bb, sta))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
PHL_ERR("[HAL] halbb_stainfo_init failed status(%d)\n",
hal_status);
return hal_status;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_deinit(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if (halbb_sta_info_deinit(hal_info->bb, sta))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
PHL_ERR("[HAL] rtw_hal_bb_stainfo_deinit failed status(%d)\n",
hal_status);
return hal_status;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_add(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if (halbb_sta_info_add_entry(hal_info->bb, sta))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
PHL_ERR("[HAL] halbb_stainfo_init failed status(%d)\n",
hal_status);
return hal_status;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_delete(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if (halbb_sta_info_delete_entry(hal_info->bb, sta))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
PHL_ERR("[HAL] rtw_hal_bb_stainfo_deinit failed status(%d)\n",
hal_status);
return hal_status;
}
void rtw_hal_bb_media_status_update(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta, bool is_connected)
{
halbb_media_status_update(hal_info->bb, sta, is_connected);
}
enum rtw_hal_status
rtw_hal_bb_upt_ramask(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
if (!rtw_halbb_dft_mask(hal_info->bb, sta)) {
PHL_ERR("rtw_halbb_set_dft_mask failed\n");
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("sta's cur_ra_mask : 0x%016llx\n", sta->hal_sta->ra_info.cur_ra_mask);
if (sta->hal_sta->ra_info.ra_mask) {
sta->hal_sta->ra_info.cur_ra_mask &= sta->hal_sta->ra_info.ra_mask;
PHL_INFO("ra_mask : 0x%016llx, cur_ra_mask : 0x%016llx\n",
sta->hal_sta->ra_info.ra_mask, sta->hal_sta->ra_info.cur_ra_mask);
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ra_register(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
if (!rtw_halbb_raregistered(hal_info->bb, sta))
return RTW_HAL_STATUS_FAILURE;
sta->hal_sta->ra_info.ra_registered = true;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ra_deregister(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
if (!rtw_halbb_ra_deregistered(hal_info->bb, sta))
PHL_ERR("rtw_halbb_ra_deregistered failed\n");
sta->hal_sta->ra_info.ra_registered = false;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ra_update(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
if (!sta->hal_sta->ra_info.ra_registered) {
PHL_WARN("%s mac-id:%d not register RA\n", __func__, sta->macid);
return RTW_HAL_STATUS_SUCCESS;
}
if (sta->hal_sta->ra_info.ra_mask) {
sta->hal_sta->ra_info.cur_ra_mask &= sta->hal_sta->ra_info.ra_mask;
PHL_INFO("ra_mask : 0x%016llx, cur_ra_mask : 0x%016llx\n",
sta->hal_sta->ra_info.ra_mask, sta->hal_sta->ra_info.cur_ra_mask);
}
if (rtw_halbb_raupdate(hal_info->bb, sta) == true)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_bb_query_txsts_rpt(struct hal_info_t *hal_info,
u16 macid0, u16 macid1)
{
if (!rtw_halbb_query_txsts(hal_info->bb, macid0, macid1))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#define INVALID_ARFR_IDX 0xFF
#define rtw_halbb_get_arfr_idx(_bb, _sta) INVALID_ARFR_IDX
u8 rtw_hal_bb_get_arfr_idx(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return rtw_halbb_get_arfr_idx(hal_info->bb, sta);
}
enum rtw_hal_status
rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid)
{
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
u8 hal_get_primary_channel_idx(u8 pri_ch,
u8 central_ch, enum channel_width bw,
enum chan_offset bw_offset)
{
u8 idx = 255;
if(bw == CHANNEL_WIDTH_80) {
if(bw_offset == CHAN_OFFSET_NO_EXT ||
bw_offset == CHAN_OFFSET_NO_DEF) {
PHL_ERR("%s invalid bw offset\n",__FUNCTION__);
return idx;
}
if (central_ch > pri_ch)
idx = (bw_offset == CHAN_OFFSET_UPPER) ? (4) : (2);
else
idx = (bw_offset == CHAN_OFFSET_UPPER) ? (1) : (3);
}
else if(bw == CHANNEL_WIDTH_40) {
if(bw_offset == CHAN_OFFSET_NO_EXT ||
bw_offset == CHAN_OFFSET_NO_DEF) {
PHL_ERR("%s invalid bw offset\n",__FUNCTION__);
return idx;
}
idx = (bw_offset == CHAN_OFFSET_UPPER) ? (2) : (1);
}
else {
idx = 0;
}
PHL_INFO("Using SC index %u for P%u C%u B%u O%u\n",
idx, pri_ch, central_ch, bw, bw_offset);
return idx;
}
enum rtw_hal_status rtw_hal_bb_set_ch_bw(struct hal_info_t *hal_info,
enum phl_phy_idx phy_idx,
u8 pri_ch,
u8 central_ch_seg0,
u8 central_ch_seg1,
enum band_type band,
enum channel_width bw)
{
if(halbb_ctrl_bw_ch(hal_info->bb, pri_ch, central_ch_seg0,
central_ch_seg1, band, bw, phy_idx) == false)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef CONFIG_PHL_CUSTOM_FEATURE
/**
* Early Weak Interference Rejection (EWIR)
* rtw_hal_bb_set_pop_en: configure bb feature about packet on packet.
* @hal_info: see struct hal_info_t
* @en: enable: true, disable: false
* @phy_idx: corresponding to the hw_band in wifi_role.
* returns enum rtw_hal_status
*/
enum rtw_hal_status rtw_hal_bb_set_pop_en(struct hal_info_t *hal_info,
bool en,
enum phl_phy_idx phy_idx)
{
PHL_INFO(" %s, pop_enable(%d)\n", __FUNCTION__, en);
halbb_pop_en(hal_info->bb, en, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
/**
* Early Weak Interference Rejection (EWIR)
* rtw_hal_bb_query_pop_en: query the status of packet on packet operation.
* @hal_info: see struct hal_info_t
* @phy_idx: corresponding to the hw_band in wifi_role.
* returns true: running; false: not running.
*/
bool rtw_hal_bb_query_pop_en(struct hal_info_t *hal_info,
enum phl_phy_idx phy_idx)
{
return halbb_querry_pop_en(hal_info->bb, phy_idx);
}
/**
* rtw_hal_bb_set_pkt_detect_thold: configure packet threshold(dbm) detection
* It would pause DIG while pd threshold enabling(value > 0)
* @hal_info: see struct hal_info_t
* @bound: pd threshold value
* returns enum rtw_hal_status
*/
enum rtw_hal_status rtw_hal_bb_set_pkt_detect_thold(struct hal_info_t *hal_info,
u32 bound)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
enum halbb_pause_type pause_type = HALBB_PAUSE;
u8 pause_result = 0;
u32 val[5] = {0};
val[0] = bound;
val[1] = 0;
if (bound == 0) {
pause_type = HALBB_RESUME;
} else if ((bound > 102) || (bound < 40)) {
PHL_INFO(" %s, invalid boundary!\n", __FUNCTION__);
return hal_status;
}
pause_result = halbb_pause_func(hal_info->bb,
F_DIG, pause_type,
HALBB_PAUSE_LV_2,
2,
val);
if (pause_result == PAUSE_SUCCESS)
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
/**
* rtw_hal_bb_query_pkt_detect_thold: query packet threshold(dbm) value.
* @hal_info: see struct hal_info_t
* @get_en_info: Caller can confirm the feature running or not with true value.
* 1. true: for query pd threshold detection enabling or not.
* 2. false:for query pd threshold value.
* @phy_idx: corresponding to the hw_band in wifi_role.
* returns pd threshold value
*/
u8 rtw_hal_bb_query_pkt_detect_thold(struct hal_info_t *hal_info,
bool get_en_info,
enum phl_phy_idx phy_idx)
{
return halbb_querry_pd_lower_bound(hal_info->bb, get_en_info, phy_idx);
}
#endif
#ifdef CONFIG_PHL_DFS
bool rtw_hal_in_radar_domain(void *hal,
u8 ch, enum channel_width bw)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return halbb_is_dfs_band(hal_info->bb, ch, bw);
}
enum rtw_hal_status
rtw_hal_bb_dfs_rpt_cfg(struct hal_info_t *hal_info, bool dfs_en)
{
if (dfs_en)
halbb_radar_detect_enable(hal_info->bb);
else
halbb_radar_detect_disable(hal_info->bb);
return RTW_HAL_STATUS_SUCCESS;
}
bool
rtw_hal_bb_radar_detect(struct hal_info_t *hal_info,
struct hal_dfs_rpt *hal_dfs)
{
return halbb_radar_detect(hal_info->bb, hal_dfs);
}
#endif /*CONFIG_PHL_DFS*/
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status
rtw_hal_bb_ch_info_parsing(struct hal_info_t *hal_info,
u8 *addr, u32 len, u8 *rpt_buf, struct ch_rpt_hdr_info *ch_hdr_rpt,
struct phy_info_rpt *phy_rpt, struct ch_info_drv_rpt *drv)
{
enum bb_ch_info_t chinfo_status = BB_CH_INFO_SUCCESS;
chinfo_status = halbb_ch_info_parsing(hal_info->bb, addr, len, rpt_buf
, (void*)ch_hdr_rpt, (void *)phy_rpt, (void *)drv);
if (chinfo_status == BB_CH_INFO_SUCCESS)
return RTW_HAL_STATUS_SUCCESS;
else if (chinfo_status == BB_CH_INFO_LAST_SEG)
return RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG;
else
return RTW_HAL_STATUS_FAILURE;
}
void
rtw_hal_bb_chan_info_cfg(struct hal_info_t *hal_info, struct chinfo_bbcr_cfg *bbcr)
{
halbb_cfg_ch_info_cr(hal_info->bb, (void*)bbcr);
}
#endif /* CONFIG_PHL_CHANNEL_INFO */
enum rtw_hal_status
rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("[HAL] call rtw_hal_bb_ctrl_btg !!!\n");
halbb_ctrl_btg(hal_info->bb, btg);
return status;
}
enum rtw_hal_status
rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("[HAL] call rtw_hal_bb_ctrl_btc_preagc !!!\n");
halbb_ctrl_btc_preagc(hal_info->bb, bt_en);
return status;
}
enum rtw_hal_status
rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("[HAL] call halbb_ctrl_rx_path !!!\n");
if(halbb_ctrl_rx_path(hal_info->bb, rx_path))
status = RTW_HAL_STATUS_SUCCESS;
else
status = RTW_HAL_STATUS_FAILURE;
return status;
}
enum rtw_hal_status
rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("[HAL] call halbb_ctrl_tx_path !!!\n");
if(halbb_ctrl_tx_path(hal_info->bb, tx_path))
status = RTW_HAL_STATUS_SUCCESS;
else
status = RTW_HAL_STATUS_FAILURE;
return status;
}
enum rtw_hal_status rtw_hal_bb_get_rx_ok(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_ok)
{
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL BB API]%s\n", __FUNCTION__);
*rx_ok = halbb_mp_get_rx_crc_ok(hal_info->bb, cur_phy_idx);
return ret;
}
enum rtw_hal_status rtw_hal_bb_get_rx_crc(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_crc_err)
{
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL BB API]%s\n", __FUNCTION__);
*rx_crc_err = halbb_mp_get_rx_crc_err(hal_info->bb, cur_phy_idx);
return ret;
}
enum rtw_hal_status rtw_hal_bb_set_reset_cnt(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_INFO("[HAL] call halbb_mp_seset_cnt !!!\n");
halbb_mp_reset_cnt(hal_info->bb);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm,
enum phl_phy_idx phy_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
PHL_INFO("[MP HAL API] %s: call halbb_set_txpwr_dbm \n", __FUNCTION__);
PHL_INFO("[MP HAL API] %s: power_dbm = %d\n", __FUNCTION__, power_dbm);
if(halbb_set_txpwr_dbm(hal_info->bb, power_dbm, phy_idx))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
hal_status = RTW_HAL_STATUS_FAILURE;
return hal_status;
}
enum rtw_hal_status
rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm,
enum phl_phy_idx phy_idx)
{
int ret = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
PHL_INFO("[MP HAL API] %s: call halbb_get_txpwr_dbm \n", __FUNCTION__);
*power_dbm = halbb_get_txpwr_dbm(hal_info->bb, phy_idx);
PHL_INFO("[MP HAL API] %s: power_dbm = %d\n", __FUNCTION__, *power_dbm);
return ret;
}
enum rtw_hal_status
rtw_hal_bb_set_pwr_index(void *hal, u16 pwr_idx, enum rf_path tx_path, bool is_cck)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_INFO("[MP HAL API] %s: call halbb_set_txpwr_idx\n", __FUNCTION__);
if (is_cck) {
if(halbb_set_cck_txpwr_idx(hal_info->bb, pwr_idx, tx_path))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
hal_status = RTW_HAL_STATUS_FAILURE;
} else {
if(halbb_set_ofdm_txpwr_idx(hal_info->bb, pwr_idx, tx_path))
hal_status = RTW_HAL_STATUS_SUCCESS;
else
hal_status = RTW_HAL_STATUS_FAILURE;
}
return hal_status;
}
enum rtw_hal_status rtw_hal_bb_get_pwr_index(void *hal, u16 *pwr_idx, enum rf_path tx_path, bool is_cck){
int ret = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_INFO("[MP HAL API] %s: call halbb_get_txpwr_idx\n", __FUNCTION__);
if (is_cck) {
PHL_INFO("[MP HAL API] call halbb_get_cck_txpwr_idx\n");
*pwr_idx = halbb_get_cck_txpwr_idx(hal_info->bb, tx_path);
} else {
PHL_INFO("[MP HAL API] call halbb_get_ofdm_txpwr_idx\n");
*pwr_idx = halbb_get_ofdm_txpwr_idx(hal_info->bb, tx_path);
}
return ret;
}
enum rtw_hal_status rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com,
struct mp_plcp_param_t *plcp_tx_struct,
struct mp_usr_plcp_gen_in *plcp_usr_info,
enum phl_phy_idx plcp_phy_idx,
u8 *plcp_sts)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
PHL_INFO("%s\n", __FUNCTION__);
*plcp_sts = halbb_plcp_gen(hal_info->bb, (void*)plcp_tx_struct,(void*)plcp_usr_info,plcp_phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable, u8 is_cck,
enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct halbb_pmac_info tx_info = {0};
PHL_INFO("%s: enable = %d is_cck = %d phy_idx = %d\n",
__FUNCTION__, enable, is_cck, phy_idx);
tx_info.en_pmac_tx = enable;
tx_info.is_cck = is_cck;
tx_info.mode = CONT_TX;
halbb_set_pmac_tx(hal_info->bb, &tx_info, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time,
enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct halbb_pmac_info tx_info = {0};
PHL_INFO("%s: enable = %d is_cck = %d phy_idx = %d\n",
__FUNCTION__, enable, is_cck, phy_idx);
PHL_INFO("%s: tx_cnt = %d period = %d tx_time = %d\n",
__FUNCTION__, tx_cnt, period, tx_time);
tx_info.en_pmac_tx = enable;
tx_info.is_cck = is_cck;
tx_info.mode = PKTS_TX;
tx_info.tx_cnt = tx_cnt;
tx_info.period = period;
tx_info.tx_time = tx_time;
halbb_set_pmac_tx(hal_info->bb, &tx_info, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, u16 tx_cnt, u8 tx_duty,
enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct halbb_pmac_info tx_info = {0};
PHL_INFO("%s: enable = %d is_cck = %d phy_idx = %d\n",
__FUNCTION__, enable, is_cck, phy_idx);
PHL_INFO("%s: tx_cnt = %d\n", __FUNCTION__, tx_cnt);
PHL_INFO("%s: tx_duty = %d\n", __FUNCTION__, tx_duty);
tx_info.en_pmac_tx = enable;
tx_info.is_cck = is_cck;
tx_info.mode = FW_TRIG_TX;
tx_info.tx_cnt = tx_cnt;
tx_info.duty_cycle = tx_duty;
halbb_set_pmac_tx(hal_info->bb, &tx_info, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_parse_phy_sts(void *hal, void *ppdu_sts,
struct rtw_phl_rx_pkt *phl_rx, u8 is_su)
{
enum rtw_hal_status hstutus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ppdu_sts *hal_ppdu = (struct hal_ppdu_sts *)ppdu_sts;
struct rtw_r_meta_data *mdata = &(phl_rx->r.mdata);
struct rtw_phl_ppdu_phy_info *phy_info = &(phl_rx->r.phy_info);
struct physts_rxd rxdesc = {0};
struct physts_result bb_rpt = {0};
u8 i = 0;
rxdesc.data_rate = mdata->rx_rate;
rxdesc.gi_ltf = mdata->rx_gi_ltf;
rxdesc.is_su = is_su;
rxdesc.macid_su = (u8)mdata->macid;
rxdesc.user_num = hal_ppdu->usr_num;
rxdesc.is_to_self = mdata->a1_match;
rxdesc.phy_idx = (mdata->bb_sel == 0) ? HW_PHY_0 : HW_PHY_1;
for (i = 0; i < rxdesc.user_num; i++) {
rxdesc.user_i[i].macid = (u8)hal_ppdu->usr[i].macid;
rxdesc.user_i[i].is_data = hal_ppdu->usr[i].has_data;
rxdesc.user_i[i].is_ctrl = hal_ppdu->usr[i].has_ctrl;
rxdesc.user_i[i].is_mgnt = hal_ppdu->usr[i].has_ctrl;
rxdesc.user_i[i].is_bcn = hal_ppdu->usr[i].has_bcn;
}
halbb_physts_parsing(hal_info->bb, hal_ppdu->phy_st_ptr,
(u16)hal_ppdu->phy_st_size,
&rxdesc, &bb_rpt);
if ((bb_rpt.rssi_avg != 0) || (bb_rpt.physts_rpt_valid == 1)) {
phy_info->is_valid = true;
/* rssi from bb rpt, bit 0 is 0.0 ~ 0.9, removed it */
phy_info->rssi = (bb_rpt.rssi_avg >> 1);
phy_info->ch_idx = bb_rpt.ch_idx;
phy_info->tx_bf = bb_rpt.is_bf;
for (i = 0; i < RTW_PHL_MAX_RF_PATH; i++) {
/* rssi from bb rpt, bit 0 is 0.0 ~ 0.9, removed it */
phy_info->rssi_path[i] = (bb_rpt.rssi[i] >> 1);
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"phy_info->rssi_path[%d] = %d\n",
i, phy_info->rssi_path[i]);
}
#ifdef RTW_WKARD_SINGLE_PATH_RSSI
if (RF_PATH_A == hal_info->hal_com->cur_rx_rfpath) {
phy_info->rssi = phy_info->rssi_path[0];
} else if (RF_PATH_B == hal_info->hal_com->cur_rx_rfpath) {
phy_info->rssi = phy_info->rssi_path[1];
} else if (RF_PATH_C == hal_info->hal_com->cur_rx_rfpath) {
phy_info->rssi = phy_info->rssi_path[2];
} else if (RF_PATH_D == hal_info->hal_com->cur_rx_rfpath) {
phy_info->rssi = phy_info->rssi_path[3];
}
#endif
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"avg_rssi %d ; ch_idx %d\n",
phy_info->rssi, phy_info->ch_idx);
}
return hstutus;
}
enum rtw_hal_status rtw_hal_bb_get_tx_ok(void *hal, u8 cur_phy_idx, u32 *tx_ok)
{
/* struct hal_info_t *hal_info = (struct hal_info_t *)hal; */
PHL_INFO("[HAL] call get halbb_mp_get_tx_ok !!!\n");
/*tx_ok = halbb_mp_get_tx_ok(hal_info->bb, cur_phy_idx);*/
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_txpwr_ref(struct hal_info_t *hal_info, u8 is_cck, u8 tx_path, s16 *txpwr_ref)
{
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API]%s\n", __FUNCTION__);
if (is_cck)
*txpwr_ref = halbb_get_cck_ref_dbm(hal_info->bb, tx_path);
else
*txpwr_ref = halbb_get_ofdm_ref_dbm(hal_info->bb, tx_path);
PHL_INFO("[MP HAL API] %s: txpwr_ref = %x\n", __FUNCTION__, *txpwr_ref);
return ret;
}
enum rtw_hal_status rtw_hal_bb_get_rssi(struct hal_info_t *hal_info, enum rf_path rx_path, u8 *rssi)
{
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API]%s\n", __FUNCTION__);
*rssi = halbb_mp_get_rssi(hal_info->bb, rx_path);
return ret;
}
enum rtw_hal_status rtw_hal_bb_get_rssi_ex(struct hal_info_t *hal_info, enum rf_path rx_path, s16 *rssi, u8 cur_phy_idx)
{
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API]%s\n", __FUNCTION__);
/*
ToDo: Should follow halbb master
[HALBB][8852A][B-Cut] Refine rssi structure from s32 to s8
sha-1:f301ebb0e7cd0c1521d3c67e94c2dd4434d87f44
struct rssi_physts rssi_t;
*rssi_t = halbb_get_mp_rssi_physts(hal_info->bb, RF_PATH_AB, cur_phy_idx);
*rssi = rssi_t.rssi_seg[cur_phy_idx].rssi[0];
*rssi = (*rssi<<8)|rssi_t.rssi_seg[cur_phy_idx].rssi[1];
*/
return ret;
}
enum rtw_hal_status rtw_hal_bb_get_rxevm(struct hal_info_t *hal_info, u8 user, u8 strm, u8 rxevm_table, u8 *rx_evm)
{
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API]%s\n", __FUNCTION__);
*rx_evm = halbb_mp_get_rxevm(hal_info->bb, user, strm, rxevm_table);
return ret;
}
enum rtw_hal_status rtw_hal_bb_trigger_rxevm(struct hal_info_t *hal_info, u8 cur_phy_idx,
u32 *phy0_user0_rxevm, u32 *phy0_user1_rxevm, u32 *phy0_user2_rxevm, u32 *phy0_user3_rxevm,
u32 *phy1_user0_rxevm, u32 *phy1_user1_rxevm, u32 *phy1_user2_rxevm, u32 *phy1_user3_rxevm)
{
struct rxevm_physts evm;
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API]%s\n", __FUNCTION__);
evm = halbb_mp_get_rxevm_physts(hal_info->bb, cur_phy_idx);
*phy0_user0_rxevm = evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_3;
*phy0_user0_rxevm = (*phy0_user0_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_2;
*phy0_user0_rxevm = (*phy0_user0_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_1;
*phy0_user0_rxevm = (*phy0_user0_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[0].rxevm_ss_0;
*phy0_user1_rxevm = evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_3;
*phy0_user1_rxevm = (*phy0_user1_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_2;
*phy0_user1_rxevm = (*phy0_user1_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_1;
*phy0_user1_rxevm = (*phy0_user1_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[1].rxevm_ss_0;
*phy0_user2_rxevm = evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_3;
*phy0_user2_rxevm = (*phy0_user2_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_2;
*phy0_user2_rxevm = (*phy0_user2_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_1;
*phy0_user2_rxevm = (*phy0_user2_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[2].rxevm_ss_0;
*phy0_user3_rxevm = evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_3;
*phy0_user3_rxevm = (*phy0_user3_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_2;
*phy0_user3_rxevm = (*phy0_user3_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_1;
*phy0_user3_rxevm = (*phy0_user3_rxevm<<8)|evm.rxevm_seg[0].rxevm_user[3].rxevm_ss_0;
*phy1_user0_rxevm = evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_3;
*phy1_user0_rxevm = (*phy1_user0_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_2;
*phy1_user0_rxevm = (*phy1_user0_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_1;
*phy1_user0_rxevm = (*phy1_user0_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[0].rxevm_ss_0;
*phy1_user1_rxevm = evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_3;
*phy1_user1_rxevm = (*phy1_user1_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_2;
*phy1_user1_rxevm = (*phy1_user1_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_1;
*phy1_user1_rxevm = (*phy1_user1_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[1].rxevm_ss_0;
*phy1_user2_rxevm = evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_3;
*phy1_user2_rxevm = (*phy1_user2_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_2;
*phy1_user2_rxevm = (*phy1_user2_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_1;
*phy1_user2_rxevm = (*phy1_user2_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[2].rxevm_ss_0;
*phy1_user3_rxevm = evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_3;
*phy1_user3_rxevm = (*phy1_user3_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_2;
*phy1_user3_rxevm = (*phy1_user3_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_1;
*phy1_user3_rxevm = (*phy1_user3_rxevm<<8)|evm.rxevm_seg[1].rxevm_user[3].rxevm_ss_0;
return ret;
}
/* mode: 0 = tmac, 1 = pmac */
enum rtw_hal_status
rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx,
u8 mode)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
if(mode == 0) {
PHL_INFO("%s: tmac mode\n", __FUNCTION__);
halbb_set_tmac_tx(hal_info->bb, phy_idx);
}
else {
PHL_INFO("%s: pmac mode\n", __FUNCTION__);
}
return ret;
}
enum rtw_hal_status rtw_hal_bb_set_txsc(struct hal_info_t *hal_info, u8 txsc,
enum phl_phy_idx phy_idx)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
PHL_INFO("[HAL] call halbb_set_txsc !!!\n");
if(halbb_set_txsc(hal_info->bb, txsc, phy_idx))
status = RTW_HAL_STATUS_SUCCESS;
else
status = RTW_HAL_STATUS_FAILURE;
return status;
}
u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch,
u8 central_ch, enum channel_width cbw, enum channel_width dbw)
{
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
return halbb_get_txsc(hal_info->bb, pri_ch, central_ch, cbw, dbw);
}
u32 rtw_hal_bb_process_c2h(void *hal, struct rtw_c2h_info *c2h)
{
#ifdef RTW_WKARD_BB_C2H
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 cls = c2h->c2h_class;
u8 func = c2h->c2h_func;
u16 len = c2h->content_len;
u8 *buf = c2h->content;
return rtw_halbb_c2h_parsing(hal_info->bb, cls, func, (u8)len, buf);
#else
return 0;
#endif
}
u16 rtw_hal_bb_get_su_rx_rate(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
struct bb_pkt_cnt_su_info rpt;
u16 max_num_tmp = 0;
u16 rx_rate = 0;
u16 i = 0;
u16 *pkt_cnt_tmp;
u8 rate_num_tmp;
u16 ofst_mode = 0;
u16 ofst_ss = 0;
u16 idx = 0;
bool is_ht_mode = false;
bool is_legacy_rate = true;
halbb_get_rx_pkt_cnt_rpt_su(hal_info->bb, &rpt);
/*Legacy rate*/
if (rpt.pkt_cnt_cck || rpt.pkt_cnt_ofdm) {
for (i = 0; i < 12; i++) {
if (rpt.pkt_cnt_legacy[i] >= max_num_tmp) {
max_num_tmp = rpt.pkt_cnt_legacy[i];
rx_rate = i;
}
}
}
if (rpt.pkt_cnt_t == 0) {
return rx_rate;
}
/*HT, VHT, HE*/
if (rpt.he_pkt_not_zero) {
pkt_cnt_tmp = rpt.pkt_cnt_he;
rate_num_tmp = 24;
ofst_mode = 0x180;
} else if (rpt.vht_pkt_not_zero) {
pkt_cnt_tmp = rpt.pkt_cnt_vht;
rate_num_tmp = 24;
ofst_mode = 0x100;
} else if (rpt.ht_pkt_not_zero) {
pkt_cnt_tmp = rpt.pkt_cnt_ht;
rate_num_tmp = 16;
ofst_mode = 0x80;
is_ht_mode = true;
} else {
return rx_rate;
}
for (i = 0; i < rate_num_tmp; i++) {
if (pkt_cnt_tmp[i] >= max_num_tmp) {
max_num_tmp = pkt_cnt_tmp[i];
idx = i;
is_legacy_rate = false;
}
}
if (is_legacy_rate)
return rx_rate;
if (!is_ht_mode) {
ofst_ss = idx / HE_VHT_NUM_MCS;
if (ofst_ss >= 0) /*>=2SS*/
idx -= (ofst_ss * HE_VHT_NUM_MCS);
}
rx_rate = ofst_mode + (ofst_ss << 4) + idx;
return rx_rate;
}
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_hal_status
rtw_hal_phy_dbcc_pre_cfg(struct hal_info_t *hal_info,
struct rtw_phl_com_t *phl_com, bool dbcc_en)
{
rtw_hal_init_bb_reg(hal_info);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_phy_dbcc_cfg(struct hal_info_t *hal_info,
struct rtw_phl_com_t *phl_com, bool dbcc_en)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
/* BB DBCC Settings */
rtw_hal_bb_cfg_dbcc(hal_info, dbcc_en);
/* enable/disable rf */
hal_status = rtw_hal_rf_ctrl_dbcc(hal_info->hal_com, dbcc_en);
if (RTW_HAL_STATUS_SUCCESS != hal_status) {
hal_status = RTW_HAL_STATUS_FAILURE;
}
return hal_status;
}
#endif
enum rtw_hal_status
rtw_hal_bb_get_txinfo_power(struct hal_info_t *hal_info,
s16 *txinfo_power_dbm)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s: call halbb_get_txinfo_txpwr_dbm \n",
__FUNCTION__);
*txinfo_power_dbm = halbb_get_txinfo_txpwr_dbm(hal_info->bb);
PHL_INFO("[MP HAL API] %s: txinfo_power_dbm = %d\n",
__FUNCTION__, *txinfo_power_dbm);
return ret;
}
enum rtw_hal_status
rtw_hal_bb_ctrl_rf_mode(struct hal_info_t *hal_info,
enum phl_rf_mode rf_mode){
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s: call rtw_hal_bb_ctrl_rf_mode \n",
__FUNCTION__);
halbb_ctrl_rf_mode(hal_info->bb, rf_mode);
return ret;
}
enum rtw_hal_status
rtw_hal_bb_set_sta_id(struct hal_info_t *hal_info,
u16 staid, enum phl_phy_idx phy_idx)
{
int ret = RTW_HAL_STATUS_SUCCESS;
halbb_set_sta_id(hal_info->bb, staid, phy_idx);
return ret;
}
enum rtw_hal_status
rtw_hal_bb_set_bss_color(struct hal_info_t *hal_info,
u8 bsscolor, enum phl_phy_idx phy_idx)
{
int ret = RTW_HAL_STATUS_SUCCESS;
halbb_set_bss_color(hal_info->bb, bsscolor, phy_idx);
return ret;
}
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
enum rtw_hal_status
rtw_hal_bb_trx_path_cfg(struct hal_info_t *hal_info,
enum rf_path tx, u8 tx_nss, enum rf_path rx, u8 rx_nss)
{
int ret = RTW_HAL_STATUS_SUCCESS;
halbb_ctrl_trx_path(hal_info->bb, tx, tx_nss, rx, rx_nss);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"tx_ant(%d) tx_nss(%d) rx_ant(%d) rx_nss(%d)\n",
tx, tx_nss, rx, rx_nss);
return ret;
}
u16 rtw_hal_bb_cfg_cmac_tx_ant(struct hal_info_t *hal_info,
enum rf_path tx_path)
{
u16 ret;
ret = (BIT(RF_PATH_A) | BIT(RF_PATH_B))|(RF_PATH_A<<4)|(RF_PATH_B<<6);
ret = halbb_cfg_cmac_tx_ant(hal_info->bb, tx_path);
return ret;
}
#endif
enum rtw_hal_status
rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s ==>start\n", __FUNCTION__);
halbb_backup_info(hal_info->bb, cur_phy_idx);
PHL_INFO("[MP HAL API] %s ==>end\n", __FUNCTION__);
return ret;
}
enum rtw_hal_status
rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s ==>start\n", __FUNCTION__);
halbb_restore_info(hal_info->bb, cur_phy_idx);
PHL_INFO("[MP HAL API] %s ==>end\n", __FUNCTION__);
return ret;
}
void rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
halbb_set_tx_pow_ref(hal_info->bb, phy_idx);
}
#ifdef CONFIG_RTW_ACS
void rtw_hal_bb_acs_mntr_trigger(struct hal_info_t *hal_info, u16 monitor_time)
{
struct ccx_para_info para = {0};
struct env_trig_rpt trig_rpt = {0};
para.rac_lv = RAC_LV_3;
para.mntr_time = monitor_time;
/*clm para*/
para.clm_app = CLM_ACS;
para.clm_input_opt = CLM_CCA_P20;
/*nhm para*/
para.nhm_app = NHM_ACS;
para.nhm_incld_cca = NHM_INCLUDE_CCA;
halbb_env_mntr_trigger(hal_info->bb, ¶, &trig_rpt);
}
enum rtw_hal_status rtw_hal_bb_acs_mntr_result(struct hal_info_t *hal_info, void *rpt)
{
u8 result = 0;
struct env_mntr_rpt mntr_rpt = {0};
struct auto_chan_sel_report *acs_rpt = (struct auto_chan_sel_report *)rpt;
result = halbb_env_mntr_result(hal_info->bb, &mntr_rpt);
if ((result & (CLM_SUCCESS | NHM_SUCCESS)) != (CLM_SUCCESS | NHM_SUCCESS)) {
return RTW_HAL_STATUS_FAILURE;
} else {
acs_rpt->clm_ratio = mntr_rpt.clm_ratio;
acs_rpt->nhm_pwr = mntr_rpt.nhm_pwr;
return RTW_HAL_STATUS_SUCCESS;
}
}
#endif /* CONFIG_RTW_ACS */
enum rtw_hal_status
rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
halbb_tssi_bb_reset(hal_info->bb);
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
void rtw_hal_bb_dcr_en(struct hal_info_t *hal_info, bool en)
{
halbb_dcr_en(hal_info->bb, en);
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,
"rtw_hal_bb_dcr_en : %d \n", (en ? 1 : 0));
return;
}
bool rtw_hal_bb_csi_rsp(struct hal_info_t *hal_info)
{
bool ret = true;
if (0 == halbb_dyn_csi_rsp_rlt_get(hal_info->bb)) {
ret = false;
}
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,
"rtw_hal_bb_csi_rsp : %d \n", (ret ? 1 : 0));
return ret;
}
#endif
void rtw_hal_bb_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
enum phl_phy_idx phy_idx)
{
halbb_wifi_event_notify(hal_info->bb, event, phy_idx);
}
void rtw_hal_bb_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
enum phl_phy_idx phy_idx)
{
halbb_bb_cmd_notify(hal_info->bb, hal_cmd, phy_idx);
}
enum rtw_hal_status
rtw_hal_bb_set_gain_offset(struct hal_info_t *hal_info, s8 rx_gain_offset,
enum rf_path rx_path, enum phl_phy_idx phy_idx, u8 iscck)
{
if(iscck)
halbb_normal_efuse_verify_cck(hal_info->bb, rx_gain_offset, rx_path, phy_idx);
else
halbb_normal_efuse_verify(hal_info->bb, rx_gain_offset, rx_path, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_get_efuse_init(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
halbb_get_efuse_init(hal_info->bb);
PHL_INFO("[HAL API] %s ==>end\n", __FUNCTION__);
}
enum rtw_hal_status
rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass,
enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
PHL_INFO("%s: pdp_bypass = %d phy_idx = %d\n",
__FUNCTION__, pdp_bypass, phy_idx);
halbb_dpd_bypass(hal_info->bb, pdp_bypass, phy_idx);
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_gpio_setting(struct rtw_hal_com_t *hal_com, u8 gpio_idx, u8 path,
bool inv, u8 src)
{
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
halbb_gpio_setting(hal_info->bb, gpio_idx, path, inv, src);
}
void rtw_hal_bb_gpio_setting_all(struct rtw_hal_com_t *hal_com, u8 rfe_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
halbb_gpio_setting_all(hal_info->bb, rfe_idx);
}
bool rtw_hal_bb_check_tx_idle(struct hal_info_t *hal_info, enum phl_phy_idx phy_idx)
{
return halbb_chk_tx_idle(hal_info->bb, phy_idx);
}
static enum rtw_hal_status
_cnvrt_rainfo_to_rate(enum hal_rate_mode rate_mode, u8 mcs_ss_idx,
enum rtw_data_rate *data_rate)
{
enum rtw_hal_status hal_sts = RTW_HAL_STATUS_FAILURE;
u16 rate_idx = 0, ss = 0;
switch(rate_mode) {
case HAL_LEGACY_MODE:
rate_idx = (u16)(mcs_ss_idx & 0xf);
ss = 0;
hal_sts = RTW_HAL_STATUS_SUCCESS;
break;
case HAL_HT_MODE:
rate_idx = (u16)(mcs_ss_idx & 0x1f);
ss = 0;
hal_sts = RTW_HAL_STATUS_SUCCESS;
break;
case HAL_VHT_MODE:
case HAL_HE_MODE:
rate_idx = (u16)(mcs_ss_idx & 0xf);
ss = (mcs_ss_idx & 0x30) >> 4;
hal_sts = RTW_HAL_STATUS_SUCCESS;
break;
default:
PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_,
"%s : incorrect rate mode(0x%x), fail to covert rate\n",
__func__, rate_mode);
hal_sts = RTW_HAL_STATUS_FAILURE;
break;
}
if (RTW_HAL_STATUS_SUCCESS == hal_sts)
*data_rate = rate_idx | (ss << 4) | (rate_mode << 7);
return hal_sts;
}
enum rtw_hal_status
rtw_hal_bb_ic_hw_setting_init(struct hal_info_t *hal_info)
{
halbb_dm_init(hal_info->bb, HW_PHY_0);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta,
struct rtw_phl_rainfo *phl_rainfo)
{
enum rtw_hal_status hal_sts = RTW_HAL_STATUS_FAILURE;
struct rtw_rate_info *rainfo = NULL;
do {
if (NULL == hal_sta) {
PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_,
"%s : hal_sta is NULL\n",
__func__);
break;
}
if (NULL == phl_rainfo) {
PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_,
"%s : Input parameter is NULL\n",
__func__);
break;
}
rainfo = &hal_sta->ra_info.rpt_rt_i;
phl_rainfo->gi_ltf = rainfo->gi_ltf;
if (HAL_RATE_BW_20 == rainfo->bw) {
phl_rainfo->bw = CHANNEL_WIDTH_20;
} else if (HAL_RATE_BW_40 == rainfo->bw) {
phl_rainfo->bw = CHANNEL_WIDTH_40;
} else if (HAL_RATE_BW_80 == rainfo->bw) {
phl_rainfo->bw = CHANNEL_WIDTH_80;
} else if (HAL_RATE_BW_160 == rainfo->bw) {
phl_rainfo->bw = CHANNEL_WIDTH_160;
} else {
PHL_TRACE(COMP_PHL_XMIT, _PHL_ERR_,
"%s : incorrect bw(0x%x), fail to covert rate\n",
__func__, rainfo->bw);
break;
}
if (RTW_HAL_STATUS_SUCCESS ==
_cnvrt_rainfo_to_rate(rainfo->mode,
rainfo->mcs_ss_idx,
&phl_rainfo->rate)) {
hal_sts = RTW_HAL_STATUS_SUCCESS;
break;
} else {
break;
}
} while (false);
return hal_sts;
}
void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
struct env_mntr_rpt mntr_rpt = {0};
struct watchdog_nhm_report *nhm_rpt = (struct watchdog_nhm_report *)rpt;
halbb_env_mntr_get_bg_result(hal_info->bb, &mntr_rpt, phy_idx);
nhm_rpt->ccx_rpt_stamp = mntr_rpt.ccx_rpt_stamp;
nhm_rpt->ccx_rpt_result = mntr_rpt.ccx_rpt_result;
nhm_rpt->nhm_pwr_dbm = (s8) ((s16) mntr_rpt.nhm_pwr - 110);
nhm_rpt->nhm_ratio = mntr_rpt.nhm_ratio;
}
void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx)
{
u8 is_ofdm = (is_cck == 0)?1:0;
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
struct rtw_tpu_info *tpu = &hal_info->hal_com->band[phy_idx].rtw_tpu_i;
tpu->tx_ptrn_shap_idx = sharp_id;
halbb_set_tx_pow_pattern_shap(hal_info->bb, channel, is_ofdm, phy_idx);
}
void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt,
enum phl_phy_idx phy_indx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)(hal_com->hal_priv);
struct env_mntr_rpt bg_rpt = {0};
u8 env_rpt_status = 0;
halbb_env_mntr_get_bg_result(hal_info->bb, &bg_rpt, phy_indx);
env_rpt_status = bg_rpt.ccx_rpt_result;
env_rpt_status = env_rpt_status & CCX_SUCCESS;
/*if ok update env rpt */
if (env_rpt_status == CCX_SUCCESS) {
env_rpt->clm_ratio = bg_rpt.clm_ratio;
env_rpt->nhm_pwr = bg_rpt.nhm_pwr;
env_rpt->nhm_ratio = bg_rpt.nhm_ratio;
env_rpt->nhm_cca_ratio = bg_rpt.nhm_cca_ratio;
env_rpt->rpt_status = 1;
} else {
env_rpt->rpt_status = 0;
}
}
enum rtw_hal_status
rtw_hal_bb_set_tb_pwr_ofst(struct hal_info_t *hal_info,
s16 ofst, enum phl_phy_idx phy_idx)
{
bool ret = false;
ret = halbb_set_pwr_ul_tb_ofst(hal_info->bb, ofst, phy_idx);
if (ret == true)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
#else /*ifndef USE_TRUE_PHY*/
enum phl_phy_idx rtw_hal_bb_band_to_phy_idx(struct rtw_hal_com_t *hal_com, u8 band_idx)
{
return HW_PHY_0;
}
void rtw_hal_bb_dfs_en(struct hal_info_t *hal_info, bool en)
{
}
void rtw_hal_bb_tssi_cont_en(struct hal_info_t *hal_info, bool en, enum rf_path path)
{
}
void rtw_hal_bb_adc_en(struct hal_info_t *hal_info, bool en)
{
}
void rtw_hal_bb_reset_en(struct hal_info_t *hal_info, bool en, enum phl_phy_idx phy_idx)
{
}
bool rtw_hal_bb_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
return true;
}
enum rtw_hal_status rtw_hal_bb_watchdog(struct hal_info_t *hal_info, u8 is_lps)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_simple_watchdog(struct hal_info_t *hal_info, u8 io_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_reset(struct hal_info_t *hal_info)
{
}
void rtw_hal_bb_fw_edcca(struct hal_info_t *hal_info)
{
}
void rtw_hal_bb_dm_init(struct hal_info_t *hal_info)
{
}
void rtw_hal_bb_dm_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
}
enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com,
bool cca_en, enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_ctrl_dbcc(struct hal_info_t *hal_info, bool dbcc_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_cfg_dbcc(struct hal_info_t *hal_info, bool dbcc_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_bb_init(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
}
void rtw_hal_init_bb_reg(struct hal_info_t *hal_info)
{
}
void rtw_hal_bb_init_reg_by_hdr(struct hal_info_t *hal_info, u32 *folder_array,
u32 folder_len, u8 is_form_folder, enum phl_phy_idx phy_idx)
{
}
u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask, u32 data)
{
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_read_bb_reg(struct rtw_hal_com_t *hal_com,
u32 addr, u32 mask)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_write_bb_reg(struct rtw_hal_com_t *hal_com,
u32 addr, u32 mask, u32 data)
{
return true;
}
u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask,
u32 data)
{
return true;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_init(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_deinit(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_add(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_stainfo_delete(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_media_status_update(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta, bool is_connected)
{
}
enum rtw_hal_status
rtw_hal_bb_upt_ramask(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ra_register(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ra_deregister(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ra_update(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
u8 rtw_hal_bb_get_arfr_idx(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com, u8 *efuse_map,
enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid)
{
return RTW_HAL_STATUS_SUCCESS;
}
u8 hal_get_primary_channel_idx(u8 pri_ch, u8 central_ch, enum channel_width bw,
enum chan_offset bw_offset)
{
return 0;
}
enum rtw_hal_status rtw_hal_bb_set_ch_bw(struct hal_info_t *hal_info,
enum phl_phy_idx phy_idx,
u8 pri_ch,
u8 central_ch_seg0,
u8 central_ch_seg1,
enum band_type band,
enum channel_width bw)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_in_radar_domain(void *hal, u8 ch, enum channel_width bw)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_dfs_rpt_cfg(struct hal_info_t *hal_info, bool dfs_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_bb_radar_detect(struct hal_info_t *hal_info,
struct hal_dfs_rpt *hal_dfs)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_rx_ok(struct hal_info_t *hal_info,
u8 cur_phy_idx, u32 *rx_ok)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_rx_crc(struct hal_info_t *hal_info,
u8 cur_phy_idx, u32 *rx_crc_err)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_set_reset_cnt(void *hal)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm,
enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm,
enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pwr_index(void *hal, u16 pwr_idx, enum rf_path tx_path, bool is_cck)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_pwr_index(void *hal, u16 *pwr_idx,
enum rf_path tx_path, bool is_cck)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com,
struct mp_plcp_param_t *plcp_tx_struct,
struct mp_usr_plcp_gen_in *plcp_usr_info,
enum phl_phy_idx plcp_phy_idx,
u8 *plcp_sts)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time,
enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, u16 tx_cnt, u8 tx_duty,
enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_parse_phy_sts(void *hal, void *ppdu_sts,
struct rtw_phl_rx_pkt *phl_rx, u8 is_su)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_tx_ok(void *hal, u8 cur_phy_idx, u32 *tx_ok)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_get_txpwr_ref(struct hal_info_t *hal_info, u8 is_cck, u8 tx_path,
s16 *txpwr_ref)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_rssi(struct hal_info_t *hal_info,
enum rf_path rx_path, u8 *rssi)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_rssi_ex(struct hal_info_t *hal_info,
enum rf_path rx_path, s16 *rssi, u8 cur_phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_get_rxevm(struct hal_info_t *hal_info, u8 user,
u8 strm, u8 rxevm_table, u8 *rx_evm)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_trigger_rxevm(struct hal_info_t *hal_info, u8 cur_phy_idx,
u32 *phy0_user0_rxevm, u32 *phy0_user1_rxevm, u32 *phy0_user2_rxevm, u32 *phy0_user3_rxevm,
u32 *phy1_user0_rxevm, u32 *phy1_user1_rxevm, u32 *phy1_user2_rxevm, u32 *phy1_user3_rxevm)
{
return RTW_HAL_STATUS_SUCCESS;
}
/* mode: 0 = tmac, 1 = pmac */
enum rtw_hal_status
rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx, u8 mode)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_bb_set_txsc(struct hal_info_t *hal_info, u8 txsc,
enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_FAILURE;
}
u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch,
u8 central_ch, enum channel_width cbw, enum channel_width dbw)
{
return 0;
}
u32 rtw_hal_bb_process_c2h(void *hal, struct rtw_c2h_info *c2h)
{
return 0;
}
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_hal_status
rtw_hal_phy_dbcc_pre_cfg(struct hal_info_t *hal_info,
struct rtw_phl_com_t *phl_com, bool dbcc_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_phy_dbcc_cfg(struct hal_info_t *hal_info,
struct rtw_phl_com_t *phl_com, bool dbcc_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
#endif
enum rtw_hal_status
rtw_hal_bb_get_txinfo_power(struct hal_info_t *hal_info,
s16 *txinfo_power_dbm)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_ctrl_rf_mode(struct hal_info_t *hal_info,
enum phl_rf_mode rf_mode){
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_sta_id(struct hal_info_t *hal_info,
u16 staid, enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_bss_color(struct hal_info_t *hal_info,
u8 bsscolor, enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
enum rtw_hal_status
rtw_hal_bb_trx_path_cfg(struct hal_info_t *hal_info,
enum rf_path tx, u8 tx_nss, enum rf_path rx, u8 rx_nss)
{
return RTW_HAL_STATUS_SUCCESS;
}
u16 rtw_hal_bb_cfg_cmac_tx_ant(struct hal_info_t *hal_info,
enum rf_path tx_path)
{
return 0;
}
#endif
enum rtw_hal_status
rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx)
{
}
enum rtw_hal_status
rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com)
{
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef CONFIG_RTW_ACS
void rtw_hal_bb_acs_mntr_trigger(struct hal_info_t *hal_info, u16 monitor_time)
{
}
enum rtw_hal_status rtw_hal_bb_acs_mntr_result(struct hal_info_t *hal_info, void *rpt)
{
return RTW_HAL_STATUS_FAILURE;
}
#endif /* CONFIG_RTW_ACS */
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
void rtw_hal_bb_dcr_en(struct hal_info_t *hal_info, bool en)
{
return;
}
bool rtw_hal_bb_csi_rsp(struct hal_info_t *hal_info)
{
return true;
}
#endif
void rtw_hal_bb_get_efuse_init(struct rtw_hal_com_t *hal_com)
{
}
void rtw_hal_bb_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
enum phl_phy_idx phy_idx)
{
}
void rtw_hal_bb_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
enum phl_phy_idx phy_idx)
{
}
enum rtw_hal_status
rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass,
enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_bb_set_gain_offset(struct hal_info_t *hal_info, s8 rx_gain_offset,
enum rf_path rx_path, enum phl_phy_idx phy_idx, u8 iscck)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_bb_check_tx_idle(struct hal_info_t *hal_info, enum phl_phy_idx phy_idx)
{
return false;
}
enum rtw_hal_status
rtw_hal_bb_ic_hw_setting_init(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta,
struct rtw_phl_rainfo *phl_rainfo)
{
return RTW_HAL_STATUS_FAILURE;
}
void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx)
{
}
void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx)
{
}
void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt,
enum phl_phy_idx phy_indx)
{
}
enum rtw_hal_status
rtw_hal_bb_set_tb_pwr_ofst(struct hal_info_t *hal_info,
s16 ofst, enum phl_phy_idx phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
#endif /*ifdef USE_TRUE_PHY*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_bb.c
|
C
|
agpl-3.0
| 56,663
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_BB_H_
#define _HAL_API_BB_H_
enum phl_phy_idx rtw_hal_bb_band_to_phy_idx(struct rtw_hal_com_t *hal_com, u8 band_idx);
void rtw_hal_bb_dfs_en(struct hal_info_t *hal_info, bool en);
void rtw_hal_bb_tssi_cont_en(struct hal_info_t *hal_info, bool en, enum rf_path path);
void rtw_hal_bb_adc_en(struct hal_info_t *hal_info,bool en);
void rtw_hal_bb_reset_en(struct hal_info_t *hal_info,bool en, enum phl_phy_idx phy_idx);
bool rtw_hal_bb_proc_cmd(struct hal_info_t *hal_info,
struct rtw_proc_cmd *incmd,
char *output, u32 out_len);
enum rtw_hal_status rtw_hal_bb_watchdog(struct hal_info_t *hal_info, u8 is_lps);
enum rtw_hal_status rtw_hal_bb_simple_watchdog(struct hal_info_t *hal_info, u8 io_en);
void rtw_hal_bb_fw_edcca(struct hal_info_t *hal_info);
void rtw_hal_bb_reset(struct hal_info_t *hal_info);
void rtw_hal_bb_dm_init(struct hal_info_t *hal_info);
void rtw_hal_bb_dm_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com,
bool cca_en, enum phl_phy_idx phy_idx);
enum rtw_hal_status rtw_hal_bb_ctrl_dbcc(struct hal_info_t *hal_info, bool dbcc_en);
enum rtw_hal_status rtw_hal_bb_cfg_dbcc(struct hal_info_t *hal_info, bool dbcc_en);
u32 rtw_hal_bb_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_bb_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_init_bb_reg(struct hal_info_t *hal_info);
u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask);
bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask, u32 data);
u32 rtw_hal_read_bb_reg(struct rtw_hal_com_t *hal_com,
u32 addr, u32 mask);
bool rtw_hal_write_bb_reg(struct rtw_hal_com_t *hal_com,
u32 addr, u32 mask, u32 data);
enum rtw_hal_status
rtw_hal_bb_stainfo_init(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_stainfo_deinit(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_stainfo_add(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_stainfo_delete(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
void rtw_hal_bb_media_status_update(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta, bool is_connected);
enum rtw_hal_status
rtw_hal_bb_upt_ramask(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_ra_update(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_ra_register(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_ra_deregister(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
u8
rtw_hal_bb_get_arfr_idx(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bb_set_ch_bw(struct hal_info_t *hal_info,
enum phl_phy_idx phy_idx,
u8 pri_ch,
u8 central_ch_seg0,
u8 central_ch_seg1,
enum band_type band,
enum channel_width bw);
#ifdef CONFIG_PHL_CUSTOM_FEATURE
enum rtw_hal_status
rtw_hal_bb_set_pop_en(struct hal_info_t *hal_info,
bool en,
enum phl_phy_idx phy_idx);
bool
rtw_hal_bb_query_pop_en(struct hal_info_t *hal_info,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_pkt_detect_thold(struct hal_info_t *hal_info, u32 bound);
u8
rtw_hal_bb_query_pkt_detect_thold(struct hal_info_t *hal_info,
bool get_en_info,
enum phl_phy_idx phy_idx);
#endif
#ifdef CONFIG_RTW_ACS
void rtw_hal_bb_acs_mntr_trigger(struct hal_info_t *hal_info, u16 monitor_time);
enum rtw_hal_status rtw_hal_bb_acs_mntr_result(struct hal_info_t *hal_info, void *rpt);
#endif /* CONFIG_RTW_ACS */
#ifdef CONFIG_PHL_DFS
enum rtw_hal_status
rtw_hal_bb_dfs_rpt_cfg(struct hal_info_t *hal_info, bool dfs_en);
bool
rtw_hal_bb_radar_detect(struct hal_info_t *hal_info,
struct hal_dfs_rpt *hal_dfs);
#endif
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status
rtw_hal_bb_ch_info_parsing(struct hal_info_t *hal_info,
u8 *addr, u32 len, u8 *rpt_buf, struct ch_rpt_hdr_info *ch_hdr_rpt,
struct phy_info_rpt *phy_rpt, struct ch_info_drv_rpt *drv);
void
rtw_hal_bb_chan_info_cfg(struct hal_info_t *hal_info, struct chinfo_bbcr_cfg *bbcr);
#endif /* CONFIG_PHL_CHANNEL_INFO */
enum rtw_hal_status rtw_hal_bb_get_rx_ok(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_ok);
enum rtw_hal_status rtw_hal_bb_get_rx_crc(struct hal_info_t *hal_info, u8 cur_phy_idx, u32 *rx_crc_err);
enum rtw_hal_status rtw_hal_bb_set_reset_cnt(void *hal);
enum rtw_hal_status rtw_hal_bb_set_pwr_index(void *hal, u16 pwr_idx, enum rf_path tx_path, bool is_cck);
enum rtw_hal_status rtw_hal_bb_get_pwr_index(void *hal, u16 *pwr_idx, enum rf_path tx_path, bool is_cck);
enum rtw_hal_status
rtw_hal_bb_parse_phy_sts(void *hal, void *ppdu_sts,
struct rtw_phl_rx_pkt *phl_rx, u8 is_su);
enum rtw_hal_status rtw_hal_bb_get_tx_ok(void *hal, u8 cur_phy_idx, u32 *tx_ok);
enum rtw_hal_status rtw_hal_bb_get_txpwr_ref(struct hal_info_t *hal_info, u8 is_cck, u8 tx_path, s16 *txpwr_ref);
enum rtw_hal_status rtw_hal_bb_get_rssi(struct hal_info_t *hal_info, enum rf_path rx_path, u8 *rssi);
enum rtw_hal_status rtw_hal_bb_get_rssi_ex(struct hal_info_t *hal_info, enum rf_path rx_path, s16 *rssi, u8 cur_phy_idx);
enum rtw_hal_status rtw_hal_bb_get_rxevm(struct hal_info_t *hal_info, u8 user, u8 strm, u8 rxevm_table, u8 *rx_evm);
enum rtw_hal_status rtw_hal_bb_trigger_rxevm(struct hal_info_t *hal_info, u8 cur_phy_idx,
u32 *phy0_user0_rxevm, u32 *phy0_user1_rxevm, u32 *phy0_user2_rxevm, u32 *phy0_user3_rxevm,
u32 *phy1_user0_rxevm, u32 *phy1_user1_rxevm, u32 *phy1_user2_rxevm, u32 *phy1_user3_rxevm);
enum rtw_hal_status rtw_hal_bb_set_txsc(struct hal_info_t *hal_info, u8 txsc,
enum phl_phy_idx phy_idx);
u32 rtw_hal_bb_process_c2h(void *hal, struct rtw_c2h_info *c2h);
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_hal_status
rtw_hal_phy_dbcc_pre_cfg(struct hal_info_t *hal_info,
struct rtw_phl_com_t *phl_com, bool dbcc_en);
enum rtw_hal_status
rtw_hal_phy_dbcc_cfg(struct hal_info_t *hal_info,
struct rtw_phl_com_t *phl_com, bool dbcc_en);
#endif
enum rtw_hal_status
rtw_hal_bb_get_txinfo_power(struct hal_info_t *hal_info,
s16 *txinfo_power_dbm);
enum rtw_hal_status
rtw_hal_bb_ctrl_rf_mode(struct hal_info_t *hal_info,
enum phl_rf_mode rf_mode);
enum rtw_hal_status
rtw_hal_bb_set_sta_id(struct hal_info_t *hal_info,
u16 staid, enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_bss_color(struct hal_info_t *hal_info,
u8 bsscolor, enum phl_phy_idx phy_idx);
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
enum rtw_hal_status
rtw_hal_bb_trx_path_cfg(struct hal_info_t *hal_info,
enum rf_path tx, u8 tx_nss, enum rf_path rx, u8 rx_nss);
u16 rtw_hal_bb_cfg_cmac_tx_ant(struct hal_info_t *hal_info,
enum rf_path tx_path);
#endif
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
void rtw_hal_bb_dcr_en(struct hal_info_t *hal_info, bool en);
bool rtw_hal_bb_csi_rsp(struct hal_info_t *hal_info);
#endif
void rtw_hal_bb_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
enum phl_phy_idx phy_idx);
void rtw_hal_bb_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_gain_offset(struct hal_info_t *hal_info, s8 rx_gain_offset,
enum rf_path rx_path, enum phl_phy_idx phy_idx, u8 iscck);
void rtw_hal_bb_get_efuse_init(struct rtw_hal_com_t *hal_com);
enum rtw_hal_status
rtw_hal_bb_ic_hw_setting_init(struct hal_info_t *hal_info);
bool rtw_hal_bb_check_tx_idle(struct hal_info_t *hal_info, enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta,
struct rtw_phl_rainfo *phl_rainfo);
enum rtw_hal_status
rtw_hal_bb_query_txsts_rpt(struct hal_info_t *hal_info,
u16 macid0, u16 macid1);
enum rtw_hal_status
rtw_hal_bb_set_tb_pwr_ofst(struct hal_info_t *hal_info,
s16 ofst, enum phl_phy_idx phy_idx);
#endif /*_HAL_API_BB_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_bb.h
|
C
|
agpl-3.0
| 9,045
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_API_BTC_C_
#include "hal_headers.h"
#include "btc/hal_btc.h"
#ifdef CONFIG_BTCOEX
/*******************************************
* C2H FW message
*******************************************/
#define BTC_FWBUF_NUM 4
struct fw_msg_entry {
_os_list list;
u8 c2h_class;
u8 c2h_func;
u16 len;
u8 buf[RTW_PHL_BTC_FWINFO_BUF];
};
static void _bt_msg_init(struct rtw_hal_com_t *hal_com,
struct hal_bt_msg *msg)
{
void *d = halcom_to_drvpriv(hal_com);
_os_spinlock_init(d, &msg->lock);
_os_mem_set(d, &msg->latest[0], 0, RTW_BTC_OVERWRITE_BUF_LEN);
_os_mem_set(d, &msg->working[0], 0, RTW_BTC_OVERWRITE_BUF_LEN);
msg->len = 0;
msg->cnt = 0;
}
static void _bt_msg_deinit(struct rtw_hal_com_t *hal_com,
struct hal_bt_msg *msg)
{
void *d = halcom_to_drvpriv(hal_com);
_os_spinlock_free(d, &msg->lock);
}
static void _msg_enq(struct rtw_hal_com_t *hal_com,
struct phl_queue *q, struct fw_msg_entry *entry)
{
pq_push(halcom_to_drvpriv(hal_com), q, &entry->list, _tail, _bh);
}
static struct fw_msg_entry *_msg_deq(struct rtw_hal_com_t *hal_com,
struct phl_queue *q)
{
struct fw_msg_entry *entry = NULL;
_os_list *list = NULL;
if (pq_pop(halcom_to_drvpriv(hal_com), q, &list, _first, _bh))
entry = (struct fw_msg_entry *)list;
return entry;
}
static bool _fw_msg_init(struct rtw_hal_com_t *hal_com)
{
void *d = halcom_to_drvpriv(hal_com);
struct btc_fw_msg *fw_msg = &hal_com->btc_msg;
struct fw_msg_entry *entry = NULL;
u16 i = 0;
_os_spinlock_init(d, &fw_msg->lock);
fw_msg->fev_cnt = 0;
_bt_msg_init(hal_com, &fw_msg->btinfo);
_bt_msg_init(hal_com, &fw_msg->scbd);
pq_init(d, &fw_msg->idleq);
pq_init(d, &fw_msg->waitq);
for (i = 0; i < BTC_FWBUF_NUM; i++) {
entry = (struct fw_msg_entry *)_os_kmem_alloc(d,
sizeof(struct fw_msg_entry));
if (entry)
_msg_enq(hal_com, &fw_msg->idleq, entry);
else
return false;
}
return true;
}
static void _fw_msg_free(struct rtw_hal_com_t *hal_com)
{
void *d = halcom_to_drvpriv(hal_com);
struct btc_fw_msg *fw_msg = &hal_com->btc_msg;
struct fw_msg_entry *entry = NULL;
_bt_msg_deinit(hal_com, &fw_msg->btinfo);
_bt_msg_deinit(hal_com, &fw_msg->scbd);
while (1) {
entry = _msg_deq(hal_com, &fw_msg->waitq);
if (entry)
_os_kmem_free(d, entry, sizeof(struct fw_msg_entry));
else
break;
}
pq_deinit(d, &fw_msg->waitq);
while (1) {
entry = _msg_deq(hal_com, &fw_msg->idleq);
if (entry)
_os_kmem_free(d, entry, sizeof(struct fw_msg_entry));
else
break;
}
pq_deinit(d, &fw_msg->idleq);
_os_spinlock_free(d, &fw_msg->lock);
}
static void _copy_btmsg(struct rtw_hal_com_t *hal_com,
struct hal_bt_msg *msg, u16 len, u8 *buf)
{
void *d = halcom_to_drvpriv(hal_com);
if (len > RTW_BTC_OVERWRITE_BUF_LEN)
return;
_os_spinlock(d, &msg->lock, _bh, NULL);
msg->cnt++;
msg->len = len;
_os_mem_cpy(d, &msg->latest[0], buf, len);
_os_spinunlock(d, &msg->lock, _bh, NULL);
}
static bool _fw_evnt_enq(struct rtw_hal_com_t *hal_com,
u8 cls, u8 func, u16 len, u8 *buf)
{
struct btc_fw_msg *fmsg = &hal_com->btc_msg;
void *d = halcom_to_drvpriv(hal_com);
struct fw_msg_entry *entry = NULL;
entry = _msg_deq(hal_com, &fmsg->idleq);
if (!entry)
return false;
entry->c2h_class = cls;
entry->c2h_func = func;
entry->len = len;
_os_mem_cpy(d, &entry->buf[0], buf, len);
_msg_enq(hal_com, &fmsg->waitq, entry);
return true;
}
enum rtw_hal_status rtw_hal_btc_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct btc_t *btc = NULL;
void *drv_priv = NULL;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "%s\n", __FUNCTION__);
drv_priv = halcom_to_drvpriv(hal_info->hal_com);
btc = _os_mem_alloc(drv_priv, sizeof(struct btc_t));
if (!btc) {
hal_status = RTW_HAL_STATUS_RESOURCE;
goto error_btc_init;
}
/* assign phl_com & hal_com */
btc->phl = phl_com;
btc->hal = hal_info->hal_com;
if (!hal_btc_init(btc)) {
hal_status = RTW_HAL_STATUS_BTC_INIT_FAILURE;
goto error_btc_init;
}
if (!_fw_msg_init(hal_info->hal_com)) {
hal_status = RTW_HAL_STATUS_BTC_INIT_FAILURE;
goto error_msg_init;
}
hal_status = RTW_HAL_STATUS_SUCCESS;
hal_info->btc = btc;
return hal_status;
error_msg_init:
_fw_msg_free(hal_info->hal_com);
error_btc_init:
if (btc) {
_os_mem_free(drv_priv, (void *)btc, sizeof(struct btc_t));
hal_info->btc = NULL;
}
return hal_status;
}
void rtw_hal_btc_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct btc_t *btc = hal_info->btc;
void *drv_priv = NULL;
_fw_msg_free(hal_info->hal_com);
drv_priv = halcom_to_drvpriv(hal_info->hal_com);
if (drv_priv && btc) {
hal_btc_deinit(btc);
_os_mem_free(drv_priv, (void *)btc, sizeof(struct btc_t));
}
}
/**********************/
/* called by non-hal layers */
/**********************/
void rtw_hal_btc_update_role_info_ntfy(void *hinfo, u8 role_id,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_stainfo_t *sta,
enum role_state rstate)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
struct btc_wl_link_info r = {0};
#ifdef CONFIG_PHL_P2PPS
u8 i =0;
#endif /* CONFIG_PHL_P2PPS */
if (role_id >= MAX_WIFI_ROLE_NUMBER)
return;
if (wrole) {
r.role = wrole->type;
#ifdef RTW_WKARD_ROLE_TYPE
if (wrole->mstate != MLME_NO_LINK &&
wrole->real_type != PHL_RTYPE_NONE) {
r.role = wrole->real_type;
PHL_INFO("[BTC], rtw_hal_btc_update_role_info_ntfy(): set r.role from type(%d) to real_type(%d)\n",
wrole->type, wrole->real_type);
}
#endif /* RTW_WKARD_ROLE_TYPE */
#ifdef CONFIG_PHL_P2PPS
r.noa = 0;
r.noa_duration = 0;
for (i = 0; i < MAX_NOA_DESC; i++) {
if (wrole->noa_desc[i].enable) {
r.noa = 1;
r.noa_duration = wrole->noa_desc[i].duration;
break;
}
}
#endif /* CONFIG_PHL_P2PPS */
r.phy = wrole->hw_band;
r.pid = wrole->hw_port;
r.active = wrole->active;
r.connected = wrole->mstate;
r.mode = wrole->cap.wmode;
r.client_cnt = wrole->assoc_sta_queue.cnt;
#ifdef RTW_PHL_BCN
r.bcn_period = wrole->bcn_cmn.bcn_interval;
r.dtim_period = wrole->dtim_period;
#endif
/* Remove it after btc ready */
r.band = wrole->chandef.band;
r.ch = wrole->chandef.center_ch;
r.bw = wrole->chandef.bw;
hal_mem_cpy(h->hal_com, &r.chdef, &wrole->chandef,
sizeof(struct rtw_chan_def));
hal_mem_cpy(h->hal_com, r.mac_addr, wrole->mac_addr, MAC_ALEN);
}
if (sta && wrole->type == PHL_RTYPE_STATION) {/*associated node info??*/
r.mac_id = sta->macid;
r.mode = (u8)sta->wmode;
}
if (ops && ops->ntfy_role_info)
ops->ntfy_role_info(btc, role_id, &r, rstate);
}
void rtw_hal_btc_power_on_ntfy(void *hinfo)
{
}
void rtw_hal_btc_power_off_ntfy(void *hinfo)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_power_off)
ops->ntfy_power_off(btc);
}
void rtw_hal_btc_init_coex_cfg_ntfy(void *hinfo)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
u8 mode = btc->phl->dev_cap.btc_mode;
if (ops && ops->ntfy_init_coex)
ops->ntfy_init_coex(btc, mode);
}
void rtw_hal_btc_scan_start_ntfy(void *hinfo, enum phl_phy_idx phy_idx,
enum band_type band)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_scan_start)
ops->ntfy_scan_start(btc, phy_idx, band);
}
void rtw_hal_btc_scan_finish_ntfy(void *hinfo, enum phl_phy_idx phy_idx)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_scan_finish)
ops->ntfy_scan_finish(btc, phy_idx);
}
void rtw_hal_btc_switch_band_ntfy(void *hinfo, enum phl_phy_idx phy_idx,
enum band_type band)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_switch_band)
ops->ntfy_switch_band(btc, phy_idx, band);
}
void rtw_hal_btc_packet_event_ntfy(void *hinfo, u8 pkt_evt_type)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_specific_packet)
ops->ntfy_specific_packet(btc, pkt_evt_type);
}
void rtw_hal_btc_radio_state_ntfy(void *hinfo, u8 rf_state)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_radio_state)
ops->ntfy_radio_state(btc, rf_state);
}
void rtw_hal_btc_customerize_ntfy(void *hinfo, u8 type, u16 len, u8 *buf)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
if (ops && ops->ntfy_customerize)
ops->ntfy_customerize(btc, type, len, buf);
}
u8 rtw_hal_btc_wl_rfk_ntfy(struct rtw_hal_com_t *hal_com, u8 phy_idx, u8 rfk_type, u8 rfk_process)
{
struct hal_info_t *h = hal_com->hal_priv;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
u8 val = 0;
if (ops && ops->ntfy_wl_rfk)
val = ops->ntfy_wl_rfk(btc, phy_idx, rfk_type, rfk_process);
return val;
}
void rtw_hal_btc_wl_status_ntfy(void *hinfo, struct rtw_phl_com_t *phl_com, u8 ntfy_num,
struct rtw_phl_stainfo_t *sta[], u8 reason)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
struct btc_wl_stat_info stat_info[MAX_WIFI_ROLE_NUMBER] = {0};
struct btc_traffic *t;
struct rtw_stats *phl_stats = &phl_com->phl_stats;
struct rtw_phl_rainfo ra_info = {0};
u8 i;
if(ntfy_num == 0)
return;
for (i = 0; i < ntfy_num; i++) {
_os_mem_set(halcom_to_drvpriv(h->hal_com), &ra_info, 0,
sizeof(ra_info));
stat_info[i].pid = sta[i]->wrole->id;
stat_info[i].stat.rssi = sta[i]->hal_sta->rssi_stat.rssi >> 1;
t = &stat_info[i].stat.traffic;
t->tx_lvl = phl_stats->tx_traffic.lvl;
t->tx_sts = phl_stats->tx_traffic.sts;
t->rx_lvl = phl_stats->rx_traffic.lvl;
t->rx_sts = phl_stats->rx_traffic.sts;
if (RTW_HAL_STATUS_SUCCESS ==
rtw_hal_bb_query_rainfo(h, sta[i]->hal_sta, &ra_info))
t->tx_rate = ra_info.rate;
else
t->tx_rate = RTW_DATA_RATE_MAX;
t->rx_rate = h->hal_com->trx_stat.rx_rate_plurality;
}
if (ops && ops->ntfy_wl_sta)
ops->ntfy_wl_sta(btc, ntfy_num, stat_info, reason);
}
void rtw_hal_btc_fwinfo_ntfy(void *hinfo)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
struct rtw_hal_com_t *hal_com = h->hal_com;
void *d = halcom_to_drvpriv(hal_com);
struct btc_fw_msg *fmsg = &hal_com->btc_msg;
struct hal_bt_msg *bmsg = NULL;
struct fw_msg_entry *entry = NULL;
_os_spinlock(d, &fmsg->lock, _bh, NULL);
fmsg->fev_cnt = 0;
_os_spinunlock(d, &fmsg->lock, _bh, NULL);
if (!ops || !ops->ntfy_fwinfo)
return;
/* bt score board notification */
while (1) {
bmsg = &fmsg->scbd;
if (bmsg->cnt) {
_os_spinlock(d, &bmsg->lock, _bh, NULL);
bmsg->cnt = 0;
_os_mem_cpy(d, &bmsg->working[0],
&bmsg->latest[0], bmsg->len);
_os_spinunlock(d, &bmsg->lock, _bh, NULL);
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], scoreboard notify !! \n");
ops->ntfy_fwinfo(btc, &bmsg->working[0], bmsg->len,
BTC_CLASS_FEV, BTC_FEV_BT_SCBD);
} else
break;
}
/* bt info notification */
while (1) {
bmsg = &fmsg->btinfo;
if (bmsg->cnt) {
_os_spinlock(d, &bmsg->lock, _bh, NULL);
bmsg->cnt = 0;
_os_mem_cpy(d, &bmsg->working[0],
&bmsg->latest[0], bmsg->len);
_os_spinunlock(d, &bmsg->lock, _bh, NULL);
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], bt info notify !! \n");
ops->ntfy_fwinfo(btc, &bmsg->working[0], bmsg->len,
BTC_CLASS_FEV, BTC_FEV_BT_INFO);
} else
break;
}
/* common btc fw events */
while (1) {
entry = _msg_deq(hal_com, &fmsg->waitq);
if (entry) {
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], fw event notify !! \n");
ops->ntfy_fwinfo(btc, entry->buf, entry->len,
entry->c2h_class, entry->c2h_func);
_msg_enq(hal_com, &fmsg->idleq, entry);
}
else
break;
}
}
void rtw_hal_btc_timer(void *hinfo, void *timer)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
struct btc_ops *ops = btc->ops;
struct btc_tmr *btmr = NULL;
u8 i = 0;
bool found = false;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], %s(), timer = 0x%p !!\n", __func__, timer);
if (!hinfo || !timer)
return;
btmr = (struct btc_tmr *)timer;
for (i = 0; i < BTC_TIMER_MAX; i++) {
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], %s(): btmr = 0x%p, &btc->timer[%d] = 0x%p \n",
__func__, btmr, i, &btc->timer[i]);
if (btmr == &btc->timer[i]) {
found = true;
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], %s(): found timer %p, id = %d \n",
__func__, btmr, btmr->id);
break;
}
}
if (ops && found) {
if (btmr->id == BTC_TIMER_PERIODIC) {
struct rtw_wifi_role_t *wrole = NULL;
struct rtw_phl_stainfo_t *sta = NULL;
struct rtw_phl_stainfo_t *wrole_sta[MAX_WIFI_ROLE_NUMBER] = {0};
u8 ntfy_num = 0;
for (i = 0; i < MAX_WIFI_ROLE_NUMBER; i++) {
wrole = &(btc->phl->wifi_roles[i]);
if(wrole->mstate == MLME_LINKED) {
sta = rtw_phl_get_stainfo_self(
btc->phl->phl_priv, wrole);
if(sta != NULL) {
wrole_sta[ntfy_num] = sta;
ntfy_num++;
}
}
}
rtw_hal_btc_wl_status_ntfy(hinfo, btc->phl, ntfy_num,
wrole_sta, PHL_BTC_NTFY_RSN_PERIOTIC);
}
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_,
"[BTC], %s(): btmr->id = %d \n",
__func__, btmr->id);
if(ops->ntfy_timer)
ops->ntfy_timer(btc, btmr->id);
} else {
PHL_INFO("[BTC], %s(): not found, ops = 0x%p, found = %d \n",
__func__, ops, found);
}
}
u32 rtw_hal_btc_req_bt_slot_t(void *hinfo)
{
struct hal_info_t *h = (struct hal_info_t *)hinfo;
struct btc_t *btc = (struct btc_t *)h->btc;
return btc->bt_req_len;
}
/***********************/
/* Called by BTC submodule */
/***********************/
void hal_btc_send_event(struct btc_t *btc, u8 *buf, u32 len, u16 ev_id)
{
#ifdef CONFIG_PHL_CMD_BTC
rtw_phl_btc_send_cmd(btc->phl, buf, len, ev_id);
#endif
}
void hal_btc_notify_ps_tdma(struct btc_t *btc, bool tdma_start)
{
#ifdef CONFIG_POWER_SAVE
enum rtw_hal_status hstatus;
hstatus = rtw_hal_ps_pwr_req(btc->phl, HAL_BTC_PWR_REQ, (tdma_start ? true : false));
if (hstatus != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("[BTC], %s, TDMA (%d) request pwr fail, status: %d \n",
__func__, tdma_start, hstatus);
}
#endif
}
bool rtw_hal_btc_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
if(incmd->in_type == RTW_ARG_TYPE_BUF)
halbtc_cmd(hal_info->btc, incmd->in.buf, output, out_len);
else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){
halbtc_cmd_parser(hal_info->btc, incmd->in.vector,
incmd->in_cnt_len, output, out_len);
}
return true;
}
#endif
enum rtw_hal_status
rtw_hal_btc_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid)
{
PHL_TRACE(COMP_PHL_BTC, _PHL_DEBUG_, "%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_btc_process_c2h(void *hal, struct rtw_c2h_info *c2h)
{
struct hal_info_t *h = (struct hal_info_t *)hal;
struct btc_t *btc = (struct btc_t *)h->btc;
struct rtw_hal_com_t *hal_com = h->hal_com;
struct btc_fw_msg *fmsg = &hal_com->btc_msg;
void *d = halcom_to_drvpriv(hal_com);
u8 cls = c2h->c2h_class;
u8 func = c2h->c2h_func;
u16 len = c2h->content_len;
u8 *buf = c2h->content;
if (len && len < RTW_PHL_BTC_FWINFO_BUF) {
if (cls == BTC_CLASS_FEV && func == BTC_FEV_BT_INFO)
_copy_btmsg(hal_com, &fmsg->btinfo, len, buf);
else if (cls == BTC_CLASS_FEV && func == BTC_FEV_BT_SCBD)
_copy_btmsg(hal_com, &fmsg->scbd, len, buf);
else
_fw_evnt_enq(hal_com, cls, func, len, buf);
_os_spinlock(d, &fmsg->lock, _bh, NULL);
if (fmsg->fev_cnt == 0) {
if (rtw_phl_btc_send_cmd(btc->phl, NULL, 0,
BTC_HMSG_FW_EV))
fmsg->fev_cnt++;
}
_os_spinunlock(d, &fmsg->lock, _bh, NULL);
} else {
PHL_TRACE(COMP_PHL_BTC, _PHL_ERR_, "[BTC], %s(): Invalid c2h packet len : %d\n",
__func__, len);
}
return 0;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_btc.c
|
C
|
agpl-3.0
| 17,203
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_BTC_H_
#define _HAL_API_BTC_H_
#ifdef CONFIG_BTCOEX
enum rtw_hal_status
rtw_hal_btc_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_btc_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
#else
#define rtw_hal_btc_init(_phl_com_, _hal_info_) RTW_HAL_STATUS_SUCCESS
#define rtw_hal_btc_deinit(_phl_com_, _hal_info_)
#endif
void rtw_hal_btc_switch_band_ntfy(void *hinfo, enum phl_phy_idx phy_idx,
enum band_type band);
void rtw_hal_btc_radio_state_ntfy(void *hinfo, u8 rf_state);
u32 rtw_hal_btc_process_c2h(void *hal, struct rtw_c2h_info *c2h);
void rtw_hal_btc_init_coex_cfg_ntfy(void *hinfo);
bool rtw_hal_btc_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd,
char *output, u32 out_len);
u32 rtw_hal_btc_req_bt_slot_t(void *hinfo);
#endif /*_HAL_API_BTC_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_btc.h
|
C
|
agpl-3.0
| 1,513
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_DRV_H_
#define _HAL_API_DRV_H_
u32 rtw_hal_mac_coex_init(struct rtw_hal_com_t *hal_com, u8 pta_mode, u8 direction);
u32 rtw_hal_mac_coex_reg_read(struct rtw_hal_com_t *hal_com, u32 offset, u32 *value);
u32 rtw_hal_mac_coex_reg_write(struct rtw_hal_com_t *hal_com, u32 offset, u32 value);
u32 rtw_hal_mac_set_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value);
u32 rtw_hal_mac_get_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value);
u32 rtw_hal_mac_set_grant(struct rtw_hal_com_t *hal_com, u8 *value);
u32 rtw_hal_mac_get_grant(struct rtw_hal_com_t *hal_com, u8 *value);
u32 rtw_hal_mac_set_polluted(struct rtw_hal_com_t *hal_com, u8 band, u8 tx_val, u8 rx_val);
u32 rtw_hal_mac_set_tx_time(struct rtw_hal_com_t *hal_com, u8 is_btc,
u8 is_resume, u8 macid, u32 tx_time);
u32 rtw_hal_mac_get_tx_time(struct rtw_hal_com_t *hal_com, u8 macid, u32 *tx_time);
u32 rtw_hal_mac_set_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 is_btc,
u8 is_resume, u8 macid, u8 tx_retry);
u32 rtw_hal_mac_get_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 macid,
u8 *tx_retry);
u32 rtw_hal_mac_get_bt_polt_cnt(struct rtw_hal_com_t *hal_com, u8 band,
u16 *cnt);
u32 rtw_hal_mac_set_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 val);
u32 rtw_hal_mac_get_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 *val);
u32 rtw_hal_mac_send_h2c(struct rtw_hal_com_t *hal_com,
struct rtw_g6_h2c_hdr *hdr, u32 *pvalue);
u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask);
bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com,
enum rf_path path, u32 addr, u32 mask, u32 data);
u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask);
bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask,
u32 data);
u32 rtw_hal_mac_write_msk_pwr_reg(
struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 mask, u32 val);
u32 rtw_hal_mac_set_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 val);
u32 rtw_hal_mac_get_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 *val);
enum rtw_hal_status
rtw_hal_mac_get_log_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val,
bool is_limited);
enum rtw_hal_status
rtw_hal_mac_read_log_efuse_map(struct rtw_hal_com_t *hal_com, u8 *map,
bool is_limited);
enum rtw_hal_status
rtw_hal_mac_write_log_efuse_map(struct rtw_hal_com_t *hal_com,
u8 *map,
u32 map_size,
u8 *mask,
u32 mask_size,
u8 *map_version,
u8 *mask_version,
u8 version_length,
u8 part,
bool is_limited);
enum rtw_hal_status
rtw_hal_mac_read_hidden_rpt(struct rtw_hal_com_t *hal_com);
enum rtw_hal_status
rtw_hal_mac_check_efuse_autoload(struct rtw_hal_com_t *hal_com, u8 *autoload);
enum rtw_hal_status
rtw_hal_mac_get_efuse_avl(struct rtw_hal_com_t *hal_com, u32 *val);
enum rtw_hal_status
rtw_hal_mac_get_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val);
enum rtw_hal_status
rtw_hal_mac_get_efuse_mask_size(struct rtw_hal_com_t *hal_com, u32 *val,
bool is_limited);
enum rtw_hal_status
rtw_hal_mac_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid);
enum rtw_hal_status
rtw_hal_mac_read_phy_efuse(struct rtw_hal_com_t *hal_com,
u32 addr, u32 size, u8 *value);
enum rtw_hal_status
rtw_hal_mac_read_bt_phy_efuse(struct rtw_hal_com_t *hal_com,
u32 addr, u32 size, u8 *value);
enum rtw_hal_status
rtw_hal_mac_get_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 *value);
enum rtw_hal_status
rtw_hal_mac_set_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 value);
enum rtw_hal_status
rtw_hal_mac_get_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 *val);
enum rtw_hal_status
rtw_hal_mac_set_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 val);
enum rtw_hal_status
rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid);
enum rtw_hal_status
rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid);
void
rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx,
u8 pwrbyrate_type, u8 pwrlmt_type);
void
rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx);
enum rtw_hal_status rtw_hal_rf_read_pwr_table(
struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate,
u8 bandwidth, u8 channel, u8 offset, u8 dcm,
u8 beamforming, s16 *get_item);
enum rtw_hal_status rtw_hal_rf_wl_tx_power_control(
struct rtw_hal_com_t *hal_com,
u32 tx_power_val);
enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com,
bool dbcc_en);
void rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx, enum rf_path path);
enum rtw_hal_status
rtw_hal_btc_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid);
enum rtw_hal_status rtw_hal_efuse_get_info(struct rtw_hal_com_t *hal_com,
enum rtw_efuse_info info_type, void *value, u8 size);
enum rtw_hal_status rtw_hal_notify_switch_band(void *hinfo,
enum band_type band, enum phl_phy_idx phy_idx);
enum rtw_hal_status rtw_hal_reset(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx, u8 band_idx, bool reset);
#ifndef CONFIG_BTCOEX
#define rtw_hal_btc_wl_rfk_ntfy(hal_com, phy_idx, rfk_type, rfk_process) 0
#else
u8 rtw_hal_btc_wl_rfk_ntfy(struct rtw_hal_com_t *hal_com, u8 phy_idx, u8 rfk_type, u8 rfk_process);
#endif
void rtw_hal_btc_power_on_ntfy(void *hinfo);
void rtw_hal_btc_power_off_ntfy(void *hinfo);
enum rtw_hal_status
rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com,
u8 band_idx, bool tx_pause, enum tx_pause_rson rson);
enum rtw_hal_status
rtw_hal_mac_set_macid_pause(struct rtw_hal_com_t *hal_com,
u16 macid, bool pause);
enum rtw_hal_status
rtw_hal_mac_set_macid_grp_pause(struct rtw_hal_com_t *hal_com,
u32 *macid_arr, u8 macid_arr_sz, bool pause);
u32
rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig);
enum rtw_hal_status
rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel,
u32 *addr_start, u32 *addr_end);
enum rtw_hal_status
rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en,
u8 restart_en, u8 timeout_en, u8 timeout_val,
u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val);
enum rtw_hal_status
rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state,
u16 *la_finish_addr, bool *la_round_up,
bool *la_loss_data);
void
rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr,
u8 *buf, u32 len, u32 dbg_path);
enum rtw_hal_status
rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value);
/* HALBB APIs for HW TX */
enum rtw_hal_status
rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com,
struct mp_plcp_param_t *plcp_tx_struct,
struct mp_usr_plcp_gen_in *plcp_usr_info,
enum phl_phy_idx plcp_phy_idx,
u8 *plcp_sts);
enum rtw_hal_status
rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable, u8 is_cck,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable,
u8 is_cck, u16 tx_cnt, u8 tx_duty,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm,
enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg);
enum rtw_hal_status
rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en);
enum rtw_hal_status
rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path);
enum rtw_hal_status
rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path);
/* mode: 0 = tmac, 1 = pmac */
enum rtw_hal_status
rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx,
u8 mode);
/* HALBB APIs for HW TX END*/
/*@--------------------------[Prptotype]-------------------------------------*/
/**
* rtw_hal_bb_get_txsc input arguments:
* @hal_com: hal com info
* @pri_ch: Spec-defined primary channel index
* @central_ch: Spec-defined central channel index
* @cbw: Channel BW
* @dbw: Data BW
*/
u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch,
u8 central_ch, enum channel_width cbw, enum channel_width dbw);
void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx);
bool rtw_hal_query_regulation(void *phl, struct rtw_regulation_info *info);
enum rtw_hal_status
rtw_hal_mac_set_tpu_mode(struct rtw_hal_com_t *hal_com,
enum rtw_tpu_op_mode op_mode_new, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_get_efuse_bt_avl(struct rtw_hal_com_t *hal_com, u32 *val);
enum rtw_hal_status
rtw_hal_mac_get_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val);
enum rtw_hal_status
rtw_hal_mac_get_efuse_bt_mask_size(struct rtw_hal_com_t *hal_com, u32 *val);
enum rtw_hal_status
rtw_hal_mac_get_log_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val);
enum rtw_hal_status
rtw_hal_mac_read_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, u8 *map);
enum rtw_hal_status
rtw_hal_mac_write_log_efuse_bt_map(struct rtw_hal_com_t *hal_com,
u8 *map,
u32 map_size,
u8 *mask,
u32 mask_size);
enum rtw_hal_status
rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx);
enum rtw_hal_status
rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx);
enum rtw_hal_status
rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com);
enum rtw_hal_status
rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta,
struct rtw_phl_rainfo *phl_rainfo);
enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com,
bool cca_en, enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_mac_write_pwr_ofst_mode(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_ofst_bw(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_ref_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_en(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_set_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band, bool en_val);
bool
rtw_hal_mac_get_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band);
enum rtw_hal_status
rtw_hal_mac_read_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u32 size, u8 *val);
enum rtw_hal_status
rtw_hal_mac_write_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u8 val);
enum rtw_hal_status
rtw_hal_mac_ax_init_bf_role(struct rtw_hal_com_t *hal_com, u8 bf_role, u8 band);
enum rtw_hal_status
rtw_hal_mac_ax_deinit_bfee(struct rtw_hal_com_t *hal_com, u8 band);
void rtw_hal_bb_gpio_setting_all(struct rtw_hal_com_t *hal_com, u8 rfe_idx);
void rtw_hal_bb_gpio_setting(struct rtw_hal_com_t *hal_com, u8 gpio_idx, u8 path,
bool inv, u8 src);
enum rtw_hal_status
rtw_hal_mac_set_gpio_func(struct rtw_hal_com_t *hal_com, u8 func, s8 gpio_cfg);
enum rtw_phl_status
rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx);
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
enum rtw_hal_status rtw_hal_mac_add_cmd_ofld(struct rtw_hal_com_t *hal_com, struct rtw_mac_cmd *cmd);
#endif
void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt,
enum phl_phy_idx phy_indx);
void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx);
#endif /*_HAL_API_DRV_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_drv.h
|
C
|
agpl-3.0
| 13,580
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_API_EFUSE_C_
#include "hal_headers.h"
#include "efuse/hal_efuse_export.h"
/*WIFI Efuse*/
enum rtw_hal_status
rtw_hal_efuse_shadow_load(struct hal_info_t *hal_info, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_shadow_load(hal_info->efuse, is_limit);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_shadow_update(struct hal_info_t *hal_info, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
status = rtw_efuse_shadow_update(hal_info->efuse, is_limit);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_shadow_read(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 *value, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_shadow_read(hal_info->efuse, byte_count, offset, value,
is_limit);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_shadow_write(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 value, bool is_limit)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_shadow_write(hal_info->efuse, byte_count, offset, value,
is_limit);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_shadow2buf(struct hal_info_t *hal_info, u8 *pbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
status = rtw_efuse_shadow2buf(hal_info->efuse, pbuf, buflen);
return status;
}
enum rtw_hal_status rtw_hal_efuse_file_map_load(
struct hal_info_t *hal_info, char *file_path, u8 is_limit)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_efuse_file_map_load(hal_info->efuse, file_path ,is_limit);
return hal_status;
}
enum rtw_hal_status rtw_hal_efuse_file_mask_load(
struct hal_info_t *hal_info, char *file_path, u8 is_limit)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_efuse_file_mask_load(hal_info->efuse, file_path, is_limit);
return hal_status;
}
/* usage = used percentage(1 Byte) + used bytes(2 Bytes) */
enum rtw_hal_status rtw_hal_efuse_get_usage(struct hal_info_t *hal_info,
u32 *usage)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_usage(hal_info->efuse, usage);
return status;
}
enum rtw_hal_status rtw_hal_efuse_get_logical_size(struct hal_info_t *hal_info,
u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_logical_size(hal_info->efuse, size, true);
return status;
}
enum rtw_hal_status rtw_hal_efuse_get_size(struct hal_info_t *hal_info,
u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_size(hal_info->efuse, size);
return status;
}
enum rtw_hal_status rtw_hal_efuse_get_avl(struct hal_info_t *hal_info,
u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_avl(hal_info->efuse, size);
return status;
}
enum rtw_hal_status rtw_hal_efuse_get_shadowmap_from(struct hal_info_t *hal_info,
u8 *val)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_shadowmap_from(hal_info->efuse, val);
return status;
}
enum rtw_hal_status rtw_hal_efuse_get_offset_mask(struct hal_info_t *hal_info,
u16 offset, u8 *mask)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_offset_mask(hal_info->efuse, offset, mask);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_get_info(struct rtw_hal_com_t *hal_com,
enum rtw_efuse_info info_type,
void *value,
u8 size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = hal_com->hal_priv;
status = rtw_efuse_get_info(hal_info->efuse, info_type, value, size);
return status;
}
/* API export to PHL : rtw_hal_get_efuse_info */
enum rtw_hal_status
rtw_hal_get_efuse_info(void *hal,
enum rtw_efuse_info info_type,
void *value,
u8 size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
status = rtw_efuse_get_info(hal_info->efuse, info_type, value, size);
return status;
}
void rtw_hal_efuse_process(struct hal_info_t *hal_info, char *ic_name)
{
rtw_efuse_process(hal_info->efuse, ic_name);
}
enum rtw_hal_status rtw_hal_efuse_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
status = rtw_efuse_init(phl_com, hal_com, &(hal_info->efuse));
return status;
}
void rtw_hal_efuse_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
rtw_efuse_deinit(hal_com, hal_info->efuse);
}
enum rtw_hal_status
rtw_hal_efuse_bt_shadow_load(struct hal_info_t *hal_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_shadow_load(hal_info->efuse);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_bt_shadow_update(struct hal_info_t *hal_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
status = rtw_efuse_bt_shadow_update(hal_info->efuse);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_bt_shadow_read(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 *value)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_shadow_read(hal_info->efuse, byte_count, offset, value);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_bt_shadow_write(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 value)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_shadow_write(hal_info->efuse, byte_count, offset, value);
return status;
}
enum rtw_hal_status
rtw_hal_efuse_bt_shadow2buf(struct hal_info_t *hal_info, u8 *pbuf, u16 buflen)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
status = rtw_efuse_bt_shadow2buf(hal_info->efuse, pbuf, buflen);
return status;
}
enum rtw_hal_status rtw_hal_efuse_bt_file_map_load(
struct hal_info_t *hal_info, char *file_path)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_efuse_bt_file_map_load(hal_info->efuse, file_path);
return hal_status;
}
enum rtw_hal_status rtw_hal_efuse_bt_file_mask_load(
struct hal_info_t *hal_info, char *file_path)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_efuse_bt_file_mask_load(hal_info->efuse, file_path);
return hal_status;
}
/* usage = used percentage(1 Byte) + used bytes(2 Bytes) */
enum rtw_hal_status rtw_hal_efuse_bt_get_usage(struct hal_info_t *hal_info,
u32 *usage)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_get_usage(hal_info->efuse, usage);
return status;
}
enum rtw_hal_status rtw_hal_efuse_bt_get_logical_size(struct hal_info_t *hal_info,
u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_get_logical_size(hal_info->efuse, size);
return status;
}
enum rtw_hal_status rtw_hal_efuse_bt_get_size(struct hal_info_t *hal_info,
u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_get_size(hal_info->efuse, size);
return status;
}
enum rtw_hal_status rtw_hal_efuse_bt_get_avl(struct hal_info_t *hal_info,
u32 *size)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_get_avl(hal_info->efuse, size);
return status;
}
enum rtw_hal_status rtw_hal_efuse_bt_get_offset_mask(struct hal_info_t *hal_info,
u16 offset, u8 *mask)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_bt_get_offset_mask(hal_info->efuse, offset, mask);
return status;
}
enum rtw_hal_status rtw_hal_efuse_bt_read_hidden(
struct hal_info_t *hal_info, u32 addr, u32 size, u8 *val)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_efuse_bt_read_hidden(hal_info->efuse, addr, size, val);
return hal_status;
}
enum rtw_hal_status rtw_hal_efuse_bt_write_hidden(
struct hal_info_t *hal_info, u32 addr, u8 val)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_efuse_bt_write_hidden(hal_info->efuse, addr, val);
return hal_status;
}
enum rtw_hal_status rtw_hal_efuse_read_phy_efuse(
struct hal_info_t *hal_info, u32 addr, u32 size, u8 *data, u8 type)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_read_phy_wifi(hal_info->efuse, addr, size, data, type);
return status;
}
enum rtw_hal_status rtw_hal_efuse_renew(
struct hal_info_t *hal_info, u8 type)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_efuse_renew(hal_info->efuse, type);
return status;
}
void hal_efuse_dump_wifi_map(
struct hal_info_t *hal_info,
u32 *used_len,
char *output,
u32 *out_len
)
{
void *d = hal_info->hal_com->drv_priv;
u32 _used_len = *used_len;
u32 _out_len = *out_len;
u32 map_len = 0;
u32 i = 0, j = 0;
u8 *buf = NULL;
rtw_efuse_get_logical_size(hal_info->efuse, &map_len, true);
if(map_len == 0){
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "map length is 0!\n");
goto exit;
}
buf = _os_mem_alloc(d, map_len);
if(buf == NULL){
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "Allocate buffer fail!\n");
goto exit;
}
rtw_efuse_shadow2buf(hal_info->efuse, buf, (u16)map_len);
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len,
"EFUSE Wifi shadow map from %s\n\n",
rtw_efuse_get_shadowmap_from_to_str(hal_info->efuse));
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len,
"%14s%-6s%-6s%-6s%-6s%-6s%-6s%-6s%-6s\n",
" ", "00", "02", "04", "06", "08", "0A", "0C", "0E");
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len,
"%14s%s\n",
" ", "================================================\n");
for(i = 0; i < map_len; i+=16){
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "0x%08X%4s", i, "");
for(j = 0; j<16;j++){
if((i+j) >= map_len)
break;
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "%02X ", buf[i+j]);
}
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "\n");
}
if(buf)
_os_mem_free(d, buf, map_len);
exit:
*used_len = _used_len;
*out_len = _out_len;
}
void hal_efuse_dump_wifi_logic_map(
struct hal_info_t *hal_info,
u32 *used_len,
char *output,
u32 *out_len
)
{
void *d = hal_info->hal_com->drv_priv;
u32 _used_len = *used_len;
u32 _out_len = *out_len;
u32 map_len = 0;
u32 i = 0, j = 0;
u8 *data = NULL;
rtw_efuse_get_logical_size(hal_info->efuse, &map_len, true);
if(map_len == 0){
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "map length is 0!\n");
goto exit;
}
data = _os_mem_alloc(d, map_len);
if(data == NULL){
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "Allocate buffer fail!\n");
goto exit;
}
rtw_efuse_logicmap_buf_load(hal_info->efuse, data, false);
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len,
"EFUSE Wifi map from HW\n");
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len,
"%14s%-6s%-6s%-6s%-6s%-6s%-6s%-6s%-6s\n",
" ", "00", "02", "04", "06", "08", "0A", "0C", "0E");
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len, _out_len - _used_len,
"%14s%s\n",
" ", "================================================\n");
for(i = 0; i < map_len; i+=16){
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "0x%08X%4s", i, "");
for(j = 0; j<16;j++){
if((i+j) >= map_len)
break;
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "%02X ", data[i+j]);
}
PHL_DBG_OUTBUF(_out_len, _used_len, output + _used_len,
_out_len - _used_len, "\n");
}
if(data)
_os_mem_free(d, data, map_len);
exit:
*used_len = _used_len;
*out_len = _out_len;
}
void hal_efuse_cmd_parser(
struct hal_info_t *hal_info,
char input[][MAX_ARGV],
u32 input_num,
char *output,
u32 out_len
)
{
u32 hal_cmd_ary_size = sizeof(hal_efuse_cmd_i) / sizeof(struct hal_cmd_info);
u32 i = 0;
u8 id = 0;
u32 used = 0;
PHL_DBG_OUTBUF(out_len, used, output + used, out_len - used, "\n");
if (hal_cmd_ary_size == 0)
return;
/* Parsing Cmd ID */
if (input_num) {
for (i = 0; i < hal_cmd_ary_size; i++) {
if (_os_strcmp(hal_efuse_cmd_i[i].name, input[0]) == 0) {
id = hal_efuse_cmd_i[i].id;
PHL_INFO("enter EFUSE cmd %s\n", hal_efuse_cmd_i[i].name);
break;
}
}
if (i == hal_cmd_ary_size) {
PHL_DBG_OUTBUF(out_len, used, output + used,
out_len - used,
"EFUSE command not found!\n");
return;
}
}
switch (id) {
case HAL_EFUSE_HELP:
PHL_DBG_OUTBUF(out_len, used, output + used,
out_len - used,
"EFUSE cmd =>\n");
for (i = 0; i < hal_cmd_ary_size - 1; i++)
PHL_DBG_OUTBUF(out_len, used, output + used,
out_len - used," %s\n", hal_efuse_cmd_i[i].name);
break;
case HAL_EFUSE_WIFI_DUMP_MAP:
hal_efuse_dump_wifi_map(hal_info, &used, output, &out_len);
break;
case HAL_EFUSE_WIFI_LOGIC_DUMP_MAP:
hal_efuse_dump_wifi_logic_map(hal_info, &used, output, &out_len);
break;
default:
PHL_DBG_OUTBUF(out_len, used, output + used,
out_len - used,"Do not support this command\n");
break;
}
}
s32 hal_efuse_cmd(
struct hal_info_t *hal_info,
char *input,
char *output,
u32 out_len
)
{
char *token;
u32 argc = 0;
char argv[MAX_ARGC][MAX_ARGV];
do {
token = _os_strsep(&input, ", ");
if (token) {
if (_os_strlen((u8*)token) <= MAX_ARGV)
_os_strcpy(argv[argc], token);
argc++;
} else {
break;
}
} while (argc < MAX_ARGC);
hal_efuse_cmd_parser(hal_info, argv, argc, output, out_len);
return 0;
}
bool rtw_hal_efuse_proc_cmd(
struct hal_info_t *hal_info,
struct rtw_proc_cmd *incmd,
char *output,
u32 out_len
)
{
if(incmd->in_type == RTW_ARG_TYPE_BUF)
hal_efuse_cmd(hal_info, incmd->in.buf, output, out_len);
else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){
hal_efuse_cmd_parser(hal_info, incmd->in.vector,
incmd->in_cnt_len, output, out_len);
}
return true;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_efuse.c
|
C
|
agpl-3.0
| 14,998
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_EFUSE_H_
#define _HAL_API_EFUSE_H_
/* efuse exported API */
/* WIFI EFUSE */
enum rtw_hal_status rtw_hal_efuse_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_efuse_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_efuse_process(struct hal_info_t *hal_info, char *ic_name);
enum rtw_hal_status
rtw_hal_efuse_shadow_load(struct hal_info_t *hal_info, bool is_limit);
enum rtw_hal_status
rtw_hal_efuse_shadow_read(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 *value, bool is_limit);
enum rtw_hal_status
rtw_hal_efuse_shadow_write(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 value, bool is_limit);
enum rtw_hal_status
rtw_hal_efuse_shadow_update(struct hal_info_t *hal_info, bool is_limit);
enum rtw_hal_status rtw_hal_efuse_shadow2buf(struct hal_info_t *hal_info,
u8 *pbuf, u16 buflen);
enum rtw_hal_status rtw_hal_efuse_file_map_load(struct hal_info_t *hal_info,
char *file_path, u8 is_limit);
enum rtw_hal_status rtw_hal_efuse_file_mask_load(struct hal_info_t *hal_info,
char *file_path, u8 is_limit);
enum rtw_hal_status rtw_hal_efuse_get_usage(struct hal_info_t *hal_info,
u32 *usage);
enum rtw_hal_status rtw_hal_efuse_get_logical_size(struct hal_info_t *hal_info,
u32 *size);
enum rtw_hal_status rtw_hal_efuse_get_size(struct hal_info_t *hal_info,
u32 *size);
enum rtw_hal_status rtw_hal_efuse_get_avl(struct hal_info_t *hal_info,
u32 *size);
enum rtw_hal_status rtw_hal_efuse_get_shadowmap_from(struct hal_info_t *hal_info,
u8 *val);
enum rtw_hal_status rtw_hal_efuse_get_offset_mask(struct hal_info_t *hal_info,
u16 offset, u8 *mask);
/* BT EFUSE */
enum rtw_hal_status rtw_hal_efuse_bt_shadow_load(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_efuse_bt_shadow_read(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 *value);
enum rtw_hal_status rtw_hal_efuse_bt_shadow_write(struct hal_info_t *hal_info, u8 byte_count,
u16 offset, u32 value);
enum rtw_hal_status rtw_hal_efuse_bt_shadow_update(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_efuse_bt_shadow2buf(struct hal_info_t *hal_info,
u8 *pbuf, u16 buflen);
enum rtw_hal_status rtw_hal_efuse_bt_file_map_load(
struct hal_info_t *hal_info, char *file_path);
enum rtw_hal_status rtw_hal_efuse_bt_file_mask_load(
struct hal_info_t *hal_info, char *file_path);
enum rtw_hal_status rtw_hal_efuse_bt_get_usage(struct hal_info_t *hal_info,
u32 *usage);
enum rtw_hal_status rtw_hal_efuse_bt_get_logical_size(struct hal_info_t *hal_info,
u32 *size);
enum rtw_hal_status rtw_hal_efuse_bt_get_size(struct hal_info_t *hal_info,
u32 *size);
enum rtw_hal_status rtw_hal_efuse_bt_get_avl(struct hal_info_t *hal_info,
u32 *size);
enum rtw_hal_status rtw_hal_efuse_bt_get_offset_mask(struct hal_info_t *hal_info,
u16 offset, u8 *mask);
enum rtw_hal_status rtw_hal_efuse_bt_read_hidden(
struct hal_info_t *hal_info, u32 addr, u32 size, u8 *val);
enum rtw_hal_status rtw_hal_efuse_bt_write_hidden(
struct hal_info_t *hal_info, u32 addr, u8 val);
enum rtw_hal_status rtw_hal_efuse_read_phy_efuse(
struct hal_info_t *hal_info, u32 addr, u32 size, u8 *data, u8 type);
enum rtw_hal_status rtw_hal_efuse_renew(
struct hal_info_t *hal_info, u8 type);
bool rtw_hal_efuse_proc_cmd(
struct hal_info_t *hal_info,
struct rtw_proc_cmd *incmd,
char *output,
u32 out_len
);
#endif /* _HAL_API_EFUSE_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_efuse.h
|
C
|
agpl-3.0
| 4,114
|
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_API_MAC_C_
#include "mac/mac_ax.h"
#include "hal_headers.h"
#ifdef RTW_PHL_BCN
#include "mac/mac_ax/fwcmd.h"
#endif
#define RTL8852A_FPGA_VERIFICATION 1
u16 hal_mac_get_macid_num(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
return mac->hw_info->macid_num;
}
void hal_mac_get_hwinfo(struct hal_info_t *hal, struct hal_spec_t *hal_spec)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_hw_info *mac_info = mac->hw_info;
struct mac_ax_ops *ops = mac->ops;
/*struct mac_ax_hw_info* (*get_hw_info)(struct mac_ax_adapter *adapter);*/
mac_info = ops->get_hw_info(mac);
hal_spec->macid_num = mac_info->macid_num;
hal->hal_com->cv = mac_info->cv;
PHL_INFO("[MAC-INFO]- CV : %d\n", mac_info->cv);
PHL_INFO("[MAC-INFO]- tx_ch_num: %d\n", mac_info->tx_ch_num);
PHL_INFO("[MAC-INFO]- tx_data_ch_num: %d\n", mac_info->tx_data_ch_num);
PHL_INFO("[MAC-INFO]- wd_body_len: %d\n", mac_info->wd_body_len);
PHL_INFO("[MAC-INFO]- wd_info_len: %d\n", mac_info->wd_info_len);
PHL_INFO("[MAC-INFO]- pwr_seq_ver: %d\n", mac_info->pwr_seq_ver);
PHL_INFO("[MAC-INFO]- fifo_size: %d\n", mac_info->fifo_size);
PHL_INFO("[MAC-INFO]- macid_num: %d\n", mac_info->macid_num);
PHL_INFO("[MAC-INFO]- wl_efuse_size: %d\n", mac_info->wl_efuse_size);
PHL_INFO("[MAC-INFO]- efuse_size: %d\n", mac_info->efuse_size);
PHL_INFO("[MAC-INFO]- log_efuse_size: %d\n", mac_info->log_efuse_size);
PHL_INFO("[MAC-INFO]- bt_efuse_size: %d\n", mac_info->bt_efuse_size);
PHL_INFO("[MAC-INFO]- sec_ctrl_efuse_size: %d\n", mac_info->sec_ctrl_efuse_size);
PHL_INFO("[MAC-INFO]- sec_data_efuse_size: %d\n", mac_info->sec_data_efuse_size);
}
#ifdef CONFIG_PCI_HCI
enum rtw_hal_status rtw_hal_mac_set_pcicfg(struct hal_info_t *hal_info,
struct mac_ax_pcie_cfgspc_param *pci_cfgspc)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 ret = 0;
ret = mac->ops->set_hw_value(mac, MAC_AX_HW_PCIE_CFGSPC_SET, pci_cfgspc);
return (ret == 0) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_ltr_sw_trigger(struct hal_info_t *hal_info, enum rtw_pcie_ltr_state state)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
enum mac_ax_pcie_ltr_sw_ctrl ctrl;
enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE;
u32 ret = 0;
switch (state) {
case RTW_PCIE_LTR_SW_ACT:
ctrl = MAC_AX_PCIE_LTR_SW_ACT;
break;
case RTW_PCIE_LTR_SW_IDLE:
ctrl = MAC_AX_PCIE_LTR_SW_IDLE;
break;
default:
PHL_INFO("%s: state = %u, fail to trigger \n", __func__, state);
return RTW_HAL_STATUS_FAILURE;
}
ret = mac->ops->set_hw_value(mac, MAX_AX_HW_PCIE_LTR_SW_TRIGGER, &ctrl);
if (ret == 0)
hstats = RTW_HAL_STATUS_SUCCESS;
else
hstats = RTW_HAL_STATUS_FAILURE;
return hstats;
}
enum rtw_hal_status rtw_hal_mac_ltr_set_pcie(struct hal_info_t *hal_info,
enum rtw_pcie_bus_func_cap_t hw_ctrl,
u8 idle_ctrl, u32 idle_val, u8 act_ctrl, u32 act_val)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_pcie_ltr_param param;
u32 ret = 0;
enum mac_ax_pcie_func_ctrl ctrl;
switch (hw_ctrl) {
case RTW_PCIE_BUS_FUNC_ENABLE:
ctrl = MAC_AX_PCIE_ENABLE;
break;
case RTW_PCIE_BUS_FUNC_DISABLE:
ctrl = MAC_AX_PCIE_DISABLE;
break;
case RTW_PCIE_BUS_FUNC_DEFAULT:
ctrl = MAC_AX_PCIE_DEFAULT;
break;
default:
ctrl = MAC_AX_PCIE_IGNORE;
}
param.write = 1;
param.read = 0;
param.ltr_ctrl = MAC_AX_PCIE_IGNORE;
param.ltr_hw_ctrl = ctrl;
param.ltr_spc_ctrl = MAC_AX_PCIE_LTR_SPC_IGNORE;
param.ltr_idle_timer_ctrl = MAC_AX_PCIE_LTR_IDLE_TIMER_IGNORE;
param.ltr_rx0_th_ctrl.ctrl = MAC_AX_PCIE_IGNORE;
param.ltr_rx0_th_ctrl.val = 0;
param.ltr_rx1_th_ctrl.ctrl = MAC_AX_PCIE_IGNORE;
param.ltr_rx1_th_ctrl.val = 0;
/* when ctrl is not equal to 0, setting ignore to make hw control the value */
if (idle_ctrl) {
param.ltr_idle_lat_ctrl.ctrl = MAC_AX_PCIE_ENABLE;
param.ltr_idle_lat_ctrl.val = idle_val;
} else {
param.ltr_idle_lat_ctrl.ctrl = MAC_AX_PCIE_IGNORE;
param.ltr_idle_lat_ctrl.val = 0;
}
if (act_ctrl) {
param.ltr_act_lat_ctrl.ctrl = MAC_AX_PCIE_ENABLE;
param.ltr_act_lat_ctrl.val = act_val;
} else {
param.ltr_act_lat_ctrl.ctrl = MAC_AX_PCIE_IGNORE;
param.ltr_act_lat_ctrl.val = 0;
}
PHL_INFO("%s: ltr_hw_ctrl %u \n", __func__, param.ltr_hw_ctrl);
PHL_INFO("%s: ltr_idle_lat_ctrl, ctrl %u, val %u\n", __func__,
param.ltr_idle_lat_ctrl.ctrl, param.ltr_idle_lat_ctrl.val);
PHL_INFO("%s: ltr_act_lat_ctrl, ctrl %u, val %u\n", __func__,
param.ltr_act_lat_ctrl.ctrl, param.ltr_act_lat_ctrl.val);
ret = mac->ops->intf_ops->ltr_set_pcie(mac, ¶m);
return (ret == 0) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status hal_mac_set_l2_leave(struct hal_info_t *hal_info)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 ret = 0;
u8 set = true;
ret = mac->ops->set_hw_value(mac, MAX_AX_HW_PCIE_L2_LEAVE, &set);
return (ret == MACSUCCESS) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_poll_txdma_idle(struct hal_info_t *hal,
struct mac_ax_txdma_ch_map *ch_map)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
u32 ret = 0;
ret = hal_mac_ops->intf_ops->poll_txdma_ch_idle(mac, ch_map);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_poll_rxdma_idle(struct hal_info_t *hal,
struct mac_ax_rxdma_ch_map *ch_map)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
u32 ret = 0;
ret = hal_mac_ops->intf_ops->poll_rxdma_ch_idle(mac, ch_map);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_cfg_txdma(struct hal_info_t *hal,
struct mac_ax_txdma_ch_map *ch_map)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
u32 ret = 0;
ret = hal_mac_ops->intf_ops->ctrl_txdma_ch(mac, ch_map);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_clr_bdidx(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
u32 ret = 0;
ret = hal_mac_ops->intf_ops->clr_idx_all(mac);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_rst_bdram(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
u32 ret = 0;
u8 val;
ret = hal_mac_ops->set_hw_value(mac, MAC_AX_HW_PCIE_RST_BDRAM, &val);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_cfg_dma_io(struct hal_info_t *hal, u8 en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
enum mac_ax_func_sw ctrl;
u32 ret = 0;
if (en)
ctrl = MAC_AX_FUNC_EN;
else
ctrl = MAC_AX_FUNC_DIS;
ret = hal_mac_ops->intf_ops->ctrl_dma_io(mac, ctrl);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
#endif
#ifdef CONFIG_USB_HCI
u8 hal_mac_get_bulkout_id(struct hal_info_t *hal, u8 dma_ch, u8 mode)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
return mac->ops->intf_ops->get_bulkout_id(mac, dma_ch, mode);
}
u32 hal_mac_usb_tx_agg_cfg(struct hal_info_t *hal, u8* wd_buf, u8 agg_num)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_usb_tx_agg_cfg agg;
agg.pkt = wd_buf;
agg.agg_num = agg_num;
return mac->ops->intf_ops->usb_tx_agg_cfg(mac, &agg);
}
u32 hal_mac_usb_rx_agg_cfg(struct hal_info_t *hal, u8 agg_mode,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_rx_agg_cfg cfg;
cfg.mode = agg_mode;
cfg.thold.drv_define = drv_define;
cfg.thold.timeout = timeout;
cfg.thold.size = size;
cfg.thold.pkt_num = pkt_num;
return mac->ops->intf_ops->usb_rx_agg_cfg(mac, &cfg);
}
enum rtw_hal_status hal_mac_force_usb_switch(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
if(mac->ops->intf_ops->u2u3_switch(mac) == MACSUCCESS) {
PHL_INFO("%s,success!\n", __func__);
return RTW_HAL_STATUS_SUCCESS;
}
else {
PHL_INFO("%s,fail!\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
}
u32 hal_mac_get_cur_usb_mode(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
return mac->ops->intf_ops->get_usb_mode(mac);
}
u32 hal_mac_get_usb_support_ability(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
return mac->ops->intf_ops->get_usb_support_ability(mac);
}
u8 hal_mac_usb_get_max_bulkout_wd_num(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
return mac->usb_info.max_bulkout_wd_num;
}
#endif
#ifdef CONFIG_SDIO_HCI
u8 hal_mac_sdio_read8(struct rtw_hal_com_t *hal, u32 addr)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
return mac_intf_ops->reg_read8(mac, addr);
}
u16 hal_mac_sdio_read16(struct rtw_hal_com_t *hal, u32 addr)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
return mac_intf_ops->reg_read16(mac, addr);
}
u32 hal_mac_sdio_read32(struct rtw_hal_com_t *hal, u32 addr)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
return mac_intf_ops->reg_read32(mac, addr);
}
int hal_mac_sdio_write8(struct rtw_hal_com_t *hal, u32 addr, u8 value)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
mac_intf_ops->reg_write8(mac, addr, value);
return 0;
}
int hal_mac_sdio_write16(struct rtw_hal_com_t *hal, u32 addr, u16 value)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
mac_intf_ops->reg_write16(mac, addr, value);
return 0;
}
int hal_mac_sdio_write32(struct rtw_hal_com_t *hal, u32 addr, u32 value)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
mac_intf_ops->reg_write32(mac, addr, value);
return 0;
}
static void _read_register(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *buf)
{
u32 i, n;
u16 val16;
u32 val32;
i = addr & 0x3;
/* Handle address not start from 4 bytes alignment case */
if (i) {
val32 = cpu_to_le32(hal_read32(hal, addr & ~0x3));
n = 4 - i;
_os_mem_cpy(hal->drv_priv, buf, ((u8 *)&val32) + i, n);
i = n;
cnt -= n;
}
while (cnt) {
if (cnt >= 4)
n = 4;
else if (cnt >= 2)
n = 2;
else
n = 1;
cnt -= n;
switch (n) {
case 1:
buf[i] = hal_read8(hal, addr+i);
i++;
break;
case 2:
val16 = cpu_to_le16(hal_read16(hal, addr+i));
_os_mem_cpy(hal->drv_priv, &buf[i], &val16, 2);
i += 2;
break;
case 4:
val32 = cpu_to_le32(hal_read32(hal, addr+i));
_os_mem_cpy(hal->drv_priv, &buf[i], &val32, 4);
i += 4;
break;
}
}
}
static int _sdio_read_local(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *buf)
{
/*struct hal_info_t *hal_info = hal->hal_priv;*/
/*struct mac_ax_adapter *mac = hal_to_mac(hal_info);*/
/*struct mac_ax_ops *mac_api = mac->ops;*/
/*struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;*/
if (buf == NULL)
return -1;
/*GEORGIA_TODO_FIXIT_ASKFORMAC*/
/*mac_intf_ops->reg_readrn(mac, addr, cnt, buf);*/
return 0;
}
void hal_mac_sdio_read_mem(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem)
{
if (pmem == NULL) {
PHL_ERR("pmem is NULL\n");
return;
}
if (addr & 0xFFFF0000) {
int err = 0;
err = _sdio_read_local(hal, addr, cnt, pmem);
if (!err)
return;
}
_read_register(hal, addr, cnt, pmem);
}
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 hal_mac_sdio_iread8(struct rtw_hal_com_t *hal, u32 addr)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
return mac_intf_ops->reg_read8(mac, addr);
}
u16 hal_mac_sdio_iread16(struct rtw_hal_com_t *hal, u32 addr)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
return mac_intf_ops->reg_read16(mac, addr);
}
u32 hal_mac_sdio_iread32(struct rtw_hal_com_t *hal, u32 addr)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *mac_api = mac->ops;
struct mac_ax_intf_ops *mac_intf_ops = mac_api->intf_ops;
return 0;
}
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#ifndef CONFIG_NEW_HALMAC_INTERFACE
#ifdef CONFIG_SDIO_HCI
static u8 hal_mac_sdio_cmd52_r8(void *h, u32 addr)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_sdio_cmd52_r8(hal->drv_priv, addr);
}
static u8 hal_mac_sdio_cmd53_r8(void *h, u32 addr)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_sdio_cmd53_r8(hal->drv_priv, addr);
}
static u16 hal_mac_sdio_cmd53_r16(void *h, u32 addr)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_sdio_cmd53_r16(hal->drv_priv, addr);
}
static u32 hal_mac_sdio_cmd53_r32(void *h, u32 addr)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_sdio_cmd53_r32(hal->drv_priv, addr);
}
static u8 hal_mac_sdio_cmd53_rn(void *h, u32 addr, u32 size, u8 *val)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_sdio_cmd53_rn(hal->drv_priv, addr, size,val);
}
static void hal_mac_sdio_cmd52_w8(void *h, u32 addr, u8 val)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_sdio_cmd52_w8(hal->drv_priv, addr, val);
}
static void hal_mac_sdio_cmd53_w8(void *h, u32 addr, u8 val)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_sdio_cmd53_w8(hal->drv_priv, addr, val);
}
static void hal_mac_sdio_cmd53_w16(void *h, u32 addr, u16 val)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_sdio_cmd53_w16(hal->drv_priv, addr, val);
}
static void hal_mac_sdio_cmd53_w32(void *h, u32 addr, u32 val)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_sdio_cmd53_w32(hal->drv_priv, addr, val);
}
static u8 hal_mac_sdio_cmd53_wn(void *h, u32 addr, u32 size, u8 *val)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_sdio_cmd53_wn(hal->drv_priv, addr, size, val);
return true;
}
static u8 hal_mac_sdio_cmd52_cia_r8(void *h, u32 addr)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_sdio_read_cia_r8(hal->drv_priv, addr);
}
#endif /*CONFIG_SDIO_HCI*/
static u8 hal_mac_reg_r8(void *h, u32 addr)
{
return hal_read8((struct rtw_hal_com_t *)h, addr);
}
static u16 hal_mac_reg_r16(void *h, u32 addr)
{
return hal_read16((struct rtw_hal_com_t *)h, addr);
}
static u32 hal_mac_reg_r32(void *h, u32 addr)
{
return hal_read32((struct rtw_hal_com_t *)h, addr);
}
static void hal_mac_reg_w8(void *h, u32 addr, u8 val)
{
hal_write8((struct rtw_hal_com_t *)h, addr, val);
}
static void hal_mac_reg_w16(void *h, u32 addr, u16 val)
{
hal_write16((struct rtw_hal_com_t *)h, addr, val);
}
static void hal_mac_reg_w32(void *h, u32 addr, u32 val)
{
hal_write32((struct rtw_hal_com_t *)h, addr, val);
}
#ifdef DBG_HAL_MAC_MEM_MOINTOR
static void hal_mac_mem_free(void *h, void *buf, u32 size)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
/*PHL_INFO("MAC free mem - :%d\n", size);*/
_os_atomic_sub(hal->drv_priv, &(hal->hal_mac_mem), size);
_os_mem_free(hal->drv_priv, buf, size);
}
static void* hal_mac_mem_alloc(void *h, u32 size)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
/*PHL_INFO("MAC Alloc mem - :%d\n", size);*/
_os_atomic_add_return(hal->drv_priv, &(hal->hal_mac_mem), size);
return _os_mem_alloc(hal->drv_priv, size);
}
#else
static void hal_mac_mem_free(void *h, void *buf, u32 size)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mem_free(hal->drv_priv, buf, size);
}
static void* hal_mac_mem_alloc(void *h, u32 size)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_mem_alloc(hal->drv_priv, size);
}
#endif /*DBG_HAL_MAC_MEM_MOINTOR*/
static void hal_mac_mem_cpy(void *h, void *dest, void *src, u32 size)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mem_cpy(hal->drv_priv, dest, src, size);
}
static void hal_mac_mem_set(void *h, void *addr, u8 val, u32 size)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mem_set(hal->drv_priv, addr, val, size);
}
static s32 hal_mac_mem_cmp(void *h, void *ptr1, void *ptr2, u32 num)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
return _os_mem_cmp(hal->drv_priv, ptr1, ptr2, num);
}
static void hal_mac_udelay(void *h, u32 us)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_delay_us(hal->drv_priv, us);
}
static void hal_mac_mdelay(void *h, u32 ms)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_delay_ms(hal->drv_priv, ms);
}
static void hal_mac_mutex_init(void *h, mac_ax_mutex *mutex)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mutex_init(hal->drv_priv, mutex);
}
static void hal_mac_mutex_deinit(void *h, mac_ax_mutex *mutex)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mutex_deinit(hal->drv_priv, mutex);
}
static void hal_mac_mutex_lock(void *h, mac_ax_mutex *mutex)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mutex_lock(hal->drv_priv, mutex);
}
static void hal_mac_mutex_unlock(void *h, mac_ax_mutex *mutex)
{
struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
_os_mutex_unlock(hal->drv_priv, mutex);
}
static void hal_mac_event_notify(void *h,
enum mac_ax_feature mac_ft,
enum mac_ax_status stat, u8 *buf, u32 size)
{
//struct rtw_hal_com_t *hal = (struct rtw_hal_com_t *)h;
}
struct rtw_h2c_pkt *hal_query_h2c_pkt(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com,
enum h2c_buf_class type)
{
struct rtw_h2c_pkt *h2c_pkt = NULL;
enum rtw_h2c_pkt_type pkt_type = H2CB_TYPE_MAX;
switch (type) {
case H2CB_CLASS_CMD:
pkt_type = H2CB_TYPE_CMD;
break;
case H2CB_CLASS_DATA:
pkt_type = H2CB_TYPE_DATA;
break;
case H2CB_CLASS_LONG_DATA:
pkt_type = H2CB_TYPE_LONG_DATA;
break;
case H2CB_CLASS_LAST:
pkt_type = H2CB_TYPE_MAX;
break;
default:
PHL_ERR("%s: Unknown type(%d)\n", __func__, type);
break;
}
h2c_pkt = rtw_phl_query_h2c_pkt(phl_com, pkt_type);
if (!h2c_pkt)
PHL_ERR("hal_query_h2c_pkt fail (type %d).\n", type);
return h2c_pkt;
}
enum rtw_hal_status hal_pltfm_tx(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com,
struct rtw_h2c_pkt *pkt)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
if (rtw_phl_pltfm_tx(phl_com, pkt) == RTW_PHL_STATUS_SUCCESS)
hstatus = RTW_HAL_STATUS_SUCCESS;
else
PHL_ERR("hal_pltfm_tx fail.\n");
return hstatus;
}
void hal_ser_l2_notify(void *phl, void *hal)
{
struct rtw_phl_com_t *phl_com = (struct rtw_phl_com_t *)phl;
rtw_phl_ser_l2_notify(phl_com);
}
static s32 hal_mac_sprintf(void *drv_adapter, char *buf, size_t size, const char *fmt, ...)
{
#if defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS)
s32 ret;
va_list args;
va_start(args, fmt);
ret = _os_vsnprintf(buf, size, fmt, args);
if (ret >= 0)
ret = _os_strlen((u8 *)buf);
/* PHL_PRINT("[HAL_MMAC]%s", buf); */
va_end(args);
return ret;
#else
return 0;
#endif
}
static s32 hal_mac_strcmp(void *drv_adapter, const char *s1, const char *s2)
{
return _os_strcmp(s1, s2);
}
static char* hal_mac_strsep(void *drv_adapter, char **s, const char *ct)
{
return _os_strsep(s, ct);
}
static u32 hal_mac_strlen(void *drv_adapter, char *buf)
{
return _os_strlen((u8 *)buf);
}
static char* hal_mac_strcpy(void *drv_adapter, char *dest, const char *src)
{
return _os_strcpy(dest, src);
}
static char* hal_mac_strpbrk(void *drv_adapter, const char *cs, const char *ct)
{
return _os_strpbrk(cs, ct);
}
static u32 hal_mac_strtoul(void *drv_adapter, const char *buf, u32 base)
{
#if 1
u32 ret = 0, val = 0;
if (base == 10)
ret = _os_sscanf(buf, "%d", &val);
else if (base == 16)
ret = _os_sscanf(buf, "%x", &val);
else
ret = _os_sscanf(buf, "%d", &val);
return val;
#else
//stdlib strtoul
#endif
}
static u8
hal_mac_ld_fw_symbol(void *phl_com, void *hal_com, const char *name,
u8 **buf, u32 *buf_size)
{
return rtw_hal_ld_fw_symbol((struct rtw_phl_com_t *)phl_com,
(struct rtw_hal_com_t *)hal_com, name, buf, buf_size);
}
#define RTW_HALMAC_FAIL 0
#define RTW_HALMAC_SUCCESS 1
#define MSG_PREFIX "[MAC]"
void hal_mac_msg_print(void *p, u8 dbg_level, s8 *fmt, ...)
{
#if defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS)
#define MSG_LEN 100
va_list args;
char str[MSG_LEN] = {0};
int err;
u8 ret = RTW_HALMAC_SUCCESS;
str[0] = '\n';
va_start(args, fmt);
err = _os_vsnprintf(str, MSG_LEN, fmt, args);
va_end(args);
/* An output error is encountered */
if (err < 0)
return;
/* Output may be truncated due to size limit */
if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
ret = RTW_HALMAC_FAIL;
PHL_TRACE(COMP_PHL_MAC, dbg_level, MSG_PREFIX " %s", str);
#endif
}
struct mac_ax_pltfm_cb rtw_plt_cb = {0};
void rtw_plt_cb_init(void)
{
/* R/W register */
#ifdef CONFIG_SDIO_HCI
rtw_plt_cb.sdio_cmd52_r8 = hal_mac_sdio_cmd52_r8;
rtw_plt_cb.sdio_cmd53_r8 = hal_mac_sdio_cmd53_r8;
rtw_plt_cb.sdio_cmd53_r16 = hal_mac_sdio_cmd53_r16;
rtw_plt_cb.sdio_cmd53_r32 = hal_mac_sdio_cmd53_r32;
rtw_plt_cb.sdio_cmd53_rn = hal_mac_sdio_cmd53_rn;
rtw_plt_cb.sdio_cmd52_w8 = hal_mac_sdio_cmd52_w8;
rtw_plt_cb.sdio_cmd53_w8 = hal_mac_sdio_cmd53_w8;
rtw_plt_cb.sdio_cmd53_w16 = hal_mac_sdio_cmd53_w16;
rtw_plt_cb.sdio_cmd53_w32 = hal_mac_sdio_cmd53_w32;
rtw_plt_cb.sdio_cmd53_wn = hal_mac_sdio_cmd53_wn;
rtw_plt_cb.sdio_cmd52_cia_r8 = hal_mac_sdio_cmd52_cia_r8;
#endif /* CONFIG_SDIO_HCI */
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
rtw_plt_cb.reg_r8 = hal_mac_reg_r8;
rtw_plt_cb.reg_r16 = hal_mac_reg_r16;
rtw_plt_cb.reg_r32 = hal_mac_reg_r32;
rtw_plt_cb.reg_w8 = hal_mac_reg_w8;
rtw_plt_cb.reg_w16 = hal_mac_reg_w16;
rtw_plt_cb.reg_w32 = hal_mac_reg_w32;
#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
/* Memory allocate */
rtw_plt_cb.rtl_free = hal_mac_mem_free;
rtw_plt_cb.rtl_malloc = hal_mac_mem_alloc;
rtw_plt_cb.rtl_memcpy = hal_mac_mem_cpy;
rtw_plt_cb.rtl_memset = hal_mac_mem_set;
rtw_plt_cb.rtl_memcmp = hal_mac_mem_cmp;
/* Sleep */
rtw_plt_cb.rtl_delay_us = hal_mac_udelay;
rtw_plt_cb.rtl_delay_ms = hal_mac_mdelay;
/* Process Synchronization */
rtw_plt_cb.rtl_mutex_init = hal_mac_mutex_init;
rtw_plt_cb.rtl_mutex_deinit = hal_mac_mutex_deinit;
rtw_plt_cb.rtl_mutex_lock = hal_mac_mutex_lock;
rtw_plt_cb.rtl_mutex_unlock = hal_mac_mutex_unlock;
rtw_plt_cb.msg_print = hal_mac_msg_print;
rtw_plt_cb.event_notify = hal_mac_event_notify;
rtw_plt_cb.ser_l2_notify = hal_ser_l2_notify;
rtw_plt_cb.ld_fw_symbol = hal_mac_ld_fw_symbol;
/*.tx = ; */
#if MAC_AX_PHL_H2C
rtw_plt_cb.tx = hal_pltfm_tx;
rtw_plt_cb.rtl_query_h2c = hal_query_h2c_pkt;
#endif
#if MAC_AX_FEATURE_DBGCMD
rtw_plt_cb.rtl_sprintf = hal_mac_sprintf;
rtw_plt_cb.rtl_strcmp = hal_mac_strcmp;
rtw_plt_cb.rtl_strsep = hal_mac_strsep;
rtw_plt_cb.rtl_strlen = hal_mac_strlen;
rtw_plt_cb.rtl_strcpy = hal_mac_strcpy;
rtw_plt_cb.rtl_strpbrk = hal_mac_strpbrk;
rtw_plt_cb.rtl_strtoul = hal_mac_strtoul;
#endif
}
#endif /*CONFIG_NEW_HALMAC_INTERFACE*/
/* halmac wrapper API for hal and proto type is at hal_api_mac.h */
#define MAC_STATUS_MAX MACSDIOSEQERR+1 /* Wrong interface */
const char *const ma_status[] = {
"MAC Success",
"Callback of platform is null",
"Endian of platform error",
"Invalid base address",
"Leave suspend error",
"Pointer is null",
"Chip ID is undefined",
"Can not get MAC adapter",
"Unexpected structure alignment",
"Buffer space is not enough",
"Buffer size error",
"Invalid item",
"Polling timeout",
"Power switch fail",
"Work queue is busy",
"Failed compare result",
"Wrong interface",
"Incorrect FW bin file",
"Wrong FIFO configuration",
"Same MACID",
"MACID full",
"There is no FW",
"Process is busy",
"state machine error",
"switch efuse bank fail",
"read efuse fail",
"write efuse fail",
"efuse size error",
"eeprom parsing fail",
"compare efuse fail",
"secure on, no host indirect access",
"invalid tx dma channel",
"address cam update error",
"Power state error",
"SDIO Tx mix mode",
"SDIO Tx sequence error",
};
#define mac_sstr(status) (((status) >= MAC_STATUS_MAX) ? "unknown" : ma_status[(status)])
/**
* rtw_hal_mac_get_version() - Get HALMAC version
* @ver_str: string buffer for storing version string
* @len: string buffer length
*
* HALMAC version format is "V[major].[prototype].[sub ver].[sub index]",
* ex: V0.16.1.0
*
*/
void rtw_hal_mac_get_version(char *ver_str, u16 len)
{
_os_snprintf(ver_str, len, "V%u.%u.%u.%u",
MAC_AX_MAJOR_VER, MAC_AX_PROTOTYPE_VER,
MAC_AX_SUB_VER, MAC_AX_SUB_INDEX);
}
/**
* rtw_hal_mac_get_fw_ver() - Get Firmware version
* @hal_info: struct hal_info_t *
* @ver_str: string buffer for storing version string
* @len: string buffer length
*
* Firmware version format is "V[major].[ver].[sub ver].[sub index]",
* ex: V0.5.0
*
*/
void rtw_hal_mac_get_fw_ver(struct hal_info_t *hal_info, char *ver_str, u16 len)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
_os_snprintf(ver_str, len, "V%u.%u.%u.%u",
mac->fw_info.major_ver,mac->fw_info.minor_ver,
mac->fw_info.sub_ver, mac->fw_info.sub_idx);
}
#define _IS_FW_READY(hal_info) \
(hal_to_mac(hal_info)->sm.fwdl == MAC_AX_FWDL_INIT_RDY)
void hal_mac_print_fw_version(struct hal_info_t *hal_info)
{
char ver[20] = {0};
rtw_hal_mac_get_fw_ver(hal_info, ver, 20);
PHL_PRINT("%s: FW version %s, %sReady\n", __func__, ver,
_IS_FW_READY(hal_info) ? "" : "Not ");
}
u32 rtw_hal_mac_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_adapter *mac = NULL;
struct mac_ax_ops *mac_ops;
u32 status;
#ifdef DBG_HAL_MAC_MEM_MOINTOR
_os_atomic_set(hal_com->drv_priv, &(hal_com->hal_mac_mem), 0);
#endif
hal_info->mac = NULL;
#ifdef CONFIG_NEW_HALMAC_INTERFACE
status = new_mac_ax_ops_init(phl_com, hal_com, &mac, &mac_ops);
#else
{
enum mac_ax_intf intf = MAC_AX_INTF_INVALID;
if (phl_com->hci_type == RTW_HCI_PCIE)
intf = MAC_AX_INTF_PCIE;
else if (phl_com->hci_type == RTW_HCI_USB)
intf = MAC_AX_INTF_USB;
else if ((phl_com->hci_type == RTW_HCI_SDIO) ||
(phl_com->hci_type == RTW_HCI_GSPI))
intf = MAC_AX_INTF_SDIO;
rtw_plt_cb_init();
status = mac_ax_ops_init(hal_com,
&rtw_plt_cb, intf, &mac, &mac_ops);
#if MAC_AX_PHL_H2C
if (status == MACSUCCESS && mac != NULL)
mac_ax_phl_init(phl_com, mac);
#endif
}
#endif
if (status != MACSUCCESS) {
PHL_ERR("%s: halmac_init_adapter fail!(status=%d-%s)\n",
__func__, status, mac_sstr(status));
hal_status = RTW_HAL_STATUS_MAC_INIT_FAILURE;
goto error_mac_init;
}
if (!mac) {
PHL_ERR("halmac alloc failed\n");
hal_status = RTW_HAL_STATUS_MAC_INIT_FAILURE;
/*_os_warn_on(1);*/
goto error_mac_init;
}
hal_com->cv = mac->hw_info->cv;
hal_info->mac = mac;
return hal_status;
error_mac_init:
if (mac) {
mac_ax_ops_exit(mac);
hal_info->mac = NULL;
}
return hal_status;
}
u32 rtw_hal_mac_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
#ifdef DBG_HAL_MAC_MEM_MOINTOR
struct rtw_hal_com_t *hal = hal_info->hal_com;
#endif
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
if (mac) {
if(mac_ax_ops_exit(mac) == MACSUCCESS) {
hal_status = RTW_HAL_STATUS_FAILURE;
hal_info->mac = NULL;
} else {
PHL_ERR("%s failed\n", __func__);
}
}
#ifdef DBG_HAL_MAC_MEM_MOINTOR
PHL_INFO("[PHL-MEM] %s HALMAC memory :%d\n", __func__,
_os_atomic_read(hal_to_drvpriv(hal_info), &(hal->hal_mac_mem)));
#endif
return hal_status;
}
u8 _hal_mac_ax_dmach2datach(u8 dmach)
{
u8 data_ch = MAC_AX_DATA_CH0;
if ((MAC_AX_DMA_B0HI == dmach) ||
(MAC_AX_DMA_B1HI == dmach))
data_ch = MAC_AX_DATA_HIQ;
else if ((MAC_AX_DMA_B0MG == dmach) ||
(MAC_AX_DMA_B1MG == dmach))
data_ch = 0;
else {
data_ch = dmach;
}
return data_ch;
}
#ifdef CONFIG_SDIO_HCI
void rtw_hal_mac_sdio_cfg(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct rtw_ic_info *ic_info)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_sdio_info info;
_os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info));
info.sdio_4byte = (ic_info->sdio_info.io_align_sz == 4)
? MAC_AX_SDIO_4BYTE_MODE_RW : MAC_AX_SDIO_4BYTE_MODE_DISABLE;
if (ic_info->sdio_info.sd3_bus_mode)
info.spec_ver = MAC_AX_SDIO_SPEC_VER_3_00;
else
info.spec_ver = MAC_AX_SDIO_SPEC_VER_2_00;
info.block_size = ic_info->sdio_info.block_sz;
if (ic_info->sdio_info.tx_512_by_byte_mode)
info.opn_mode = MAC_AX_SDIO_OPN_MODE_BYTE;
else
info.opn_mode = MAC_AX_SDIO_OPN_MODE_BLOCK;
/*
* MAC_AX_HW_SDIO_INFO always return MACSUCCESS,
* so don't check return value here.
*/
mac->ops->set_hw_value(mac, MAC_AX_HW_SDIO_INFO, &info);
}
/**
* rtw_hal_mac_sdio_tx_cfg - SDIO TX related setting
* @hal: pointer of struct rtw_hal_com_t
*
* Configure setting for SDIO TX.
* All tx related setting which need to be config after mac init(power on)
* should be included here.
*
* Config tx mode to DUMMY_AUTO to release (32K-4) bytes TX size limitation,
* but this mode only work on SDIO host supporting block mode.
*
* No return value for this function.
*/
void rtw_hal_mac_sdio_tx_cfg(struct rtw_hal_com_t *hal)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum mac_ax_sdio_tx_mode mode = MAC_AX_SDIO_TX_MODE_DUMMY_AUTO;
u32 err;
err = mac->ops->set_hw_value(mac, MAC_AX_HW_SDIO_TX_MODE, &mode);
if (err != MACSUCCESS)
PHL_ERR("%s: set TX mode(%u) FAIL!(%u)\n", __func__, mode, err);
}
/**
* rtw_hal_mac_sdio_rx_agg_cfg - SDIO RX aggregation setting
* @hal: pointer of struct rtw_hal_com_t
* @enable: enable function or not
* @drv_define: use driver's parameters or not
* @timeout: timeout threshold, unit 1us
* @size: size threshold, unit 1KB
* @pkt_num: packet number threshold
*
* Configure setting for SDIO RX aggregation.
*
* No return value for this function.
*/
void rtw_hal_mac_sdio_rx_agg_cfg(struct rtw_hal_com_t *hal, bool enable,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_rx_agg_cfg cfg = {MAC_AX_RX_AGG_MODE_NONE};
if (enable) {
cfg.mode = MAC_AX_RX_AGG_MODE_DMA;
cfg.thold.drv_define = drv_define;
cfg.thold.timeout = timeout;
cfg.thold.size = size;
cfg.thold.pkt_num = pkt_num;
}
mac->ops->set_hw_value(mac, MAC_AX_HW_SDIO_RX_AGG, &cfg);
}
/* AX TX DESC */
/* DWORD 0 ; Offset 00h */
#define GET_TX_AX_DESC_CHANNEL_DMA(_wd) LE_BITS_TO_4BYTE(_wd, 16, 4)
#define GET_TX_AX_DESC_WP_OFFSET(_wd) LE_BITS_TO_4BYTE(_wd, 24, 8)
/* DWORD 2 ; Offset 08h */
#define GET_TX_AX_DESC_PKT_LEN(_wd) LE_BITS_TO_2BYTE(_wd+8, 0, 14)
/**
* rtw_hal_mac_sdio_check_tx_allow - Check hardware resource enough to xmit
* @hal: pointer of struct rtw_hal_com_t
* @dma_ch: dma channel to xmit, should be the same as field "CHANNEL_DMA "in WD
* @buf: data buffer to xmit
* @len: data buffer length
* @agg_count: how many packets aggregated in this buffer
* @pkt_len: array to store each packet's lenght in this buffer,
* pkt_len should be the same as field "PKT_LEN" in WD
* @wp_offset: array to store each packet's wp_offset in this buffer
* wp_offset should be the same as field "WP_OFFSET" in WD
* @txaddr: return SDIO TX address for this tx buffer, and only valid when
* function's return value is true.
* @txlen: return SDIO TX length for this tx buffer, and only valid when
* function's return value is true. txlen would >= len and align
* to particular size by IC.
*
* Check if hardware resource is enough to send this tx buffer and return
* SDIO TX address.
*
* Return true if hardware resource is enough, otherwise false.
*/
bool rtw_hal_mac_sdio_check_tx_allow(struct rtw_hal_com_t *hal, u8 dma_ch,
u8 *buf, u32 len, u8 agg_count,
u16 *pkt_len, u8 *wp_offset, u32 *txaddr,
u32 *txlen)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_sdio_tx_info info = {0};
int i;
u32 err;
u16 pkt_len_tmp;
u8 wp_offset_tmp;
u8 wd_ch;
/* For H2C, pkt_len & wp_offset may be invalid */
if (!pkt_len && (agg_count == 1)) {
pkt_len_tmp = GET_TX_AX_DESC_PKT_LEN(buf);
pkt_len = &pkt_len_tmp;
}
if (!wp_offset && (agg_count == 1)) {
wp_offset_tmp = (u8)GET_TX_AX_DESC_WP_OFFSET(buf);
wp_offset = &wp_offset_tmp;
}
/* check tx wd */
wd_ch = (u8)GET_TX_AX_DESC_CHANNEL_DMA(buf);
if (wd_ch != dma_ch) {
PHL_ERR("%s: tx channel abnormal, %u(wd) != %u(input)\n",
__func__, wd_ch, dma_ch);
debug_dump_data(buf, len&0xFFFF0000?0xFFFF:(u16)len, "wd:");
}
info.total_size = len;
info.dma_txagg_num = agg_count;
info.ch_dma = dma_ch;
/* halmac request pkt_size should be little endian */
for (i = 0; i < agg_count; i++)
pkt_len[i] = cpu_to_le16(pkt_len[i]);
info.pkt_size = (u8*)pkt_len;
info.wp_offset = wp_offset;
info.chk_cnt = 5;
err = mac->ops->intf_ops->tx_allow_sdio(mac, &info);
if (err != MACSUCCESS) {
PHL_DBG("%s: tx allow fail! (%d)\n", __func__, err);
goto err_exit;
}
err = mac->ops->intf_ops->tx_cmd_addr_sdio(mac, &info, txaddr);
if (err != MACSUCCESS) {
PHL_ERR("%s: get tx addr fail! (%d)\n", __func__, err);
goto err_exit;
}
/*
* TX I/O size should align to 8 bytes on SDIO byte count mode,
* or hardware would go wrong.
*
* TODO: alignment size would be get from HALMAC return.
*/
*txlen = _ALIGN(len, 8);
return true;
err_exit:
/* Revert pkt_len to CPU endian */
for (i = 0; i < agg_count; i++)
pkt_len[i] = le16_to_cpu(pkt_len[i]);
return false;
}
static enum rtw_rx_type _pkt_type_mac2phl(enum mac_ax_pkt_t mac_type)
{
enum rtw_rx_type t = RTW_RX_TYPE_MAX;
switch (mac_type) {
case MAC_AX_PKT_DATA:
t = RTW_RX_TYPE_WIFI;
break;
case MAC_AX_PKT_MGNT:
case MAC_AX_PKT_CTRL:
case MAC_AX_PKT_8023:
case MAC_AX_PKT_H2C:
case MAC_AX_PKT_FWDL:
/* TODO: unknown */
PHL_WARN("%s: unhandled RX type(%d)\n", __func__, mac_type);
break;
case MAC_AX_PKT_C2H:
t = RTW_RX_TYPE_C2H;
break;
case MAC_AX_PKT_PPDU:
t = RTW_RX_TYPE_PPDU_STATUS;
break;
case MAC_AX_PKT_CH_INFO:
t = RTW_RX_TYPE_CHANNEL_INFO;
break;
case MAC_AX_PKT_DFS:
t = RTW_RX_TYPE_DFS_RPT;
break;
default:
PHL_WARN("%s: unknon RX type(%d)\n", __func__, mac_type);
break;
}
return t;
}
static void hal_mac_parse_rxpkt_info(struct mac_ax_rxpkt_info *info,
struct rtw_r_meta_data *meta)
{
meta->pktlen = (u16)info->pktsize; /* DW0 [0:13] */
meta->shift = info->shift; /* DW0 [14:15] */
meta->rpkt_type = _pkt_type_mac2phl(info->type); /* DW0 [24:27] */
meta->drv_info_size = info->drvsize; /* DW0 [28:30] */
meta->long_rxd = (info->rxdlen == RXD_LONG_LEN) ? 1 : 0; /* DW0 [31:31] */
if (info->type == MAC_AX_PKT_DATA) {
#if 0
meta->dma_ch;
meta->hal_port;
meta->ta[6]; /* Transmitter Address */
#endif
#if 0
meta->wl_hd_iv_len; /* DW0 [16:21] */
meta->bb_sel; /* DW0 [22:22] */
meta->mac_info_vld; /* DW0 [23:23] */
#endif
#if 0
meta->long_rxd; /* DW0 [31:31] */
meta->ppdu_type; /* DW1 [0:3] */
meta->ppdu_cnt; /* DW1 [4:6] */
meta->sr_en; /* DW1 [7:7] */
meta->user_id; /* DW1 [8:15] */
meta->rx_rate; /* DW1 [16:24] */
meta->rx_gi_ltf; /* DW1 [25:27] */
meta->non_srg_ppdu; /* DW1 [28:28] */
meta->inter_ppdu; /* DW1 [29:29] */
meta->bw; /* DW1 [30:31] */
meta->freerun_cnt; /* DW2 [0:31] */
meta->a1_match; /* DW3 [0:0] */
meta->sw_dec; /* DW3 [1:1] */
meta->hw_dec; /* DW3 [2:2] */
meta->ampdu; /* DW3 [3:3] */
meta->ampdu_end_pkt; /* DW3 [4:4] */
meta->amsdu; /* DW3 [5:5] */
meta->amsdu_cut; /* DW3 [6:6] */
meta->last_msdu; /* DW3 [7:7] */
meta->bypass; /* DW3 [8:8] */
#endif
meta->crc32 = info->u.data.crc_err; /* DW3 [9:9] */
meta->icverr = info->u.data.icv_err; /* DW3 [10:10] */
#if 0
meta->magic_wake; /* DW3 [11:11] */
meta->unicast_wake; /* DW3 [12:12] */
meta->pattern_wake; /* DW3 [13:13] */
meta->get_ch_info; /* DW3 [14:15] */
meta->pattern_idx; /* DW3 [16:20] */
meta->target_idc; /* DW3 [21:23] */
meta->chksum_ofld_en; /* DW3 [24:24] */
meta->with_llc; /* DW3 [25:25] */
meta->rx_statistics; /* DW3 [26:26] */
meta->frame_type; /* DW4 [0:1] */
meta->mc; /* DW4 [2:2] */
meta->bc; /* DW4 [3:3] */
meta->more_data; /* DW4 [4:4] */
meta->more_frag; /* DW4 [5:5] */
meta->pwr_bit; /* DW4 [6:6] */
meta->qos; /* DW4 [7:7] */
meta->tid; /* DW4 [8:11] */
meta->eosp; /* DW4 [12:12] */
meta->htc; /* DW4 [13:13] */
meta->q_null; /* DW4 [14:14] */
meta->seq; /* DW4 [16:27] */
meta->frag_num; /* DW4 [28:31] */
meta->sec_cam_idx; /* DW5 [0:7] */
meta->addr_cam; /* DW5 [8:15] */
meta->macid; /* DW5 [16:23] */
meta->rx_pl_id; /* DW5 [24:27] */
meta->addr_cam_vld; /* DW5 [28:28] */
meta->addr_fwd_en; /* DW5 [29:29] */
meta->rx_pl_match; /* DW5 [30:30] */
meta->mac_addr[6]; /* DW6 [0:31] DW7 [0:15] */
meta->smart_ant; /* DW7 [16:16] */
meta->sec_type; /* DW7 [17:20] */
#endif
} else if (info->type == MAC_AX_PKT_PPDU) {
meta->mac_info_vld = info->u.ppdu.mac_info; /* DW0 [23:23] */
}
}
/* AX RX DESC */
/* DWORD 0 ; Offset 00h */
#define GET_RX_AX_DESC_PKT_LEN(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
#define GET_RX_AX_DESC_SHIFT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 2)
#define GET_RX_AX_DESC_HDR_IV_L(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 6)
#define GET_RX_AX_DESC_BB_SEL(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 22, 1)
#define GET_RX_AX_DESC_MAC_INFO_VLD(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1)
#define GET_RX_AX_DESC_RPKT_TYPE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 4)
#define GET_RX_AX_DESC_DRV_INFO_SIZE(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 3)
#define GET_RX_AX_DESC_LONG_RXD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
/* DWORD 1 ; Offset 04h */
#define GET_RX_AX_DESC_PPDU_TYPE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 4)
#define GET_RX_AX_DESC_PPDU_CNT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 4, 3)
#define GET_RX_AX_DESC_SR_EN(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)
#define GET_RX_AX_DESC_USER_ID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 8)
#define GET_RX_AX_DESC_RX_DATARATE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 9)
#define GET_RX_AX_DESC_RX_GI_LTF(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 3)
#define GET_RX_AX_DESC_NON_SRG_PPDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 1)
#define GET_RX_AX_DESC_INTER_PPDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 29, 1)
#define GET_RX_AX_DESC_BW(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 2)
/* DWORD 2 ; Offset 08h */
#define GET_RX_AX_DESC_FREERUN_CNT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 32)
/* DWORD 3 ; Offset 0ch */
#define GET_RX_AX_DESC_A1_MATCH(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 1)
#define GET_RX_AX_DESC_SW_DEC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 1, 1)
#define GET_RX_AX_DESC_HW_DEC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 2, 1)
#define GET_RX_AX_DESC_AMPDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 3, 1)
#define GET_RX_AX_DESC_AMPDU_EDN_PKT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 4, 1)
#define GET_RX_AX_DESC_AMSDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 5, 1)
#define GET_RX_AX_DESC_AMSDU_CUT(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 6, 1)
#define GET_RX_AX_DESC_LAST_MSDU(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 1)
#define GET_RX_AX_DESC_BYPASS(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 8, 1)
#define GET_RX_AX_DESC_CRC32(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 9, 1)
#define GET_RX_AX_DESC_ICVERR(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
#define GET_RX_AX_DESC_MAGIC_WAKE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
#define GET_RX_AX_DESC_UNICAST_WAKE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 1)
#define GET_RX_AX_DESC_PATTERN_WAKE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 13, 1)
#define GET_RX_AX_DESC_CH_INFO(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 14, 1)
#define GET_RX_AX_DESC_STATISTICS(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 15, 1)
#define GET_RX_AX_DESC_PATTERN_IDX(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 5)
#define GET_RX_AX_DESC_TARGET_IDC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 21, 3)
#define GET_RX_AX_DESC_CHKSUM_OFFLOAD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 24, 1)
#define GET_RX_AX_DESC_WITH_LLC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 25, 1)
/* DWORD 4 ; Offset 10h */
#define GET_RX_AX_DESC_TYPE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 2)
#define GET_RX_AX_DESC_MC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 2, 1)
#define GET_RX_AX_DESC_BC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 3, 1)
#define GET_RX_AX_DESC_MD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 4, 1)
#define GET_RX_AX_DESC_MF(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 5, 1)
#define GET_RX_AX_DESC_PWR(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 6, 1)
#define GET_RX_AX_DESC_QOS(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 7, 1)
#define GET_RX_AX_DESC_TID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 4)
#define GET_RX_AX_DESC_EOSP(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 12, 1)
#define GET_RX_AX_DESC_HTC(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 13, 1)
#define GET_RX_AX_DESC_QNULL(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 14, 1)
#define GET_RX_AX_DESC_SEQ(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 12)
#define GET_RX_AX_DESC_FRAG(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 28, 4)
/* DWORD 5 ; Offset 14h */
#define GET_RX_AX_DESC_CAM_IDX(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 8)
#define GET_RX_AX_DESC_ADDR_CAM(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 8, 8)
#define GET_RX_AX_DESC_MACID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 16, 8)
#define GET_RX_AX_DESC_PL_ID(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 24, 4)
#define GET_RX_AX_DESC_CAM_VLD(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 28, 1)
#define GET_RX_AX_DESC_FWD_EN(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 29, 1)
#define GET_RX_AX_DESC_PL_MATCH(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 30, 1)
#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
static void hal_mac_parse_rxd_checksume(struct rtw_hal_com_t *hal,
struct rtw_r_meta_data *meta, u8 status)
{
if ((status == MAC_AX_CHKSUM_OFD_IPV4_TCP_OK) ||
(status == MAC_AX_CHKSUM_OFD_IPV6_TCP_OK) ||
(status == MAC_AX_CHKSUM_OFD_IPV4_UDP_OK) ||
(status == MAC_AX_CHKSUM_OFD_IPV6_UDP_OK))
meta->chksum_status = 0;
else
meta->chksum_status = 1;
}
#endif
static void hal_mac_parse_rxd(struct rtw_hal_com_t *hal,
u8 *rxd, struct rtw_r_meta_data *meta)
{
#if 0
meta->pktlen = GET_RX_AX_DESC_PKT_LEN(rxd);
meta->shift = GET_RX_AX_DESC_SHIFT(rxd);
meta->wl_hd_iv_len = GET_RX_AX_DESC_HDR_IV_L(rxd);
meta->bb_sel = GET_RX_AX_DESC_BB_SEL(rxd);
meta->mac_info_vld = GET_RX_AX_DESC_MAC_INFO_VLD(rxd);
meta->rpkt_type = GET_RX_AX_DESC_RPKT_TYPE(rxd);
meta->drv_info_size = GET_RX_AX_DESC_DRV_INFO_SIZE(rxd);
meta->long_rxd = GET_RX_AX_DESC_LONG_RXD(rxd);
meta->ppdu_type = GET_RX_AX_DESC_PPDU_TYPE(rxd);
meta->ppdu_cnt = GET_RX_AX_DESC_PPDU_CNT(rxd);
meta->sr_en = GET_RX_AX_DESC_SR_EN(rxd);
meta->user_id = GET_RX_AX_DESC_USER_ID(rxd);
meta->rx_rate = GET_RX_AX_DESC_RX_DATARATE(rxd);
meta->rx_gi_ltf = GET_RX_AX_DESC_RX_GI_LTF(rxd);
meta->non_srg_ppdu = GET_RX_AX_DESC_NON_SRG_PPDU(rxd);
meta->inter_ppdu = GET_RX_AX_DESC_INTER_PPDU(rxd);
meta->bw = GET_RX_AX_DESC_BW(rxd);
meta->freerun_cnt = GET_RX_AX_DESC_FREERUN_CNT(rxd);
meta->a1_match = GET_RX_AX_DESC_A1_MATCH(rxd);
#endif
meta->sw_dec = GET_RX_AX_DESC_SW_DEC(rxd);
meta->hw_dec = GET_RX_AX_DESC_HW_DEC(rxd);
#if 0
meta->ampdu = GET_RX_AX_DESC_AMPDU(rxd);
meta->ampdu_end_pkt = GET_RX_AX_DESC_AMPDU_EDN_PKT(rxd);
meta->amsdu = GET_RX_AX_DESC_AMSDU(rxd);
#endif
meta->amsdu_cut = GET_RX_AX_DESC_AMSDU_CUT(rxd);
meta->last_msdu = GET_RX_AX_DESC_LAST_MSDU(rxd);
#if 0
meta->bypass = GET_RX_AX_DESC_BYPASS(rxd);
meta->crc32 = GET_RX_AX_DESC_CRC32(rxd);
meta->icverr = GET_RX_AX_DESC_ICVERR(rxd);
meta->magic_wake = GET_RX_AX_DESC_MAGIC_WAKE(rxd);
meta->unicast_wake = GET_RX_AX_DESC_UNICAST_WAKE(rxd);
meta->pattern_wake = GET_RX_AX_DESC_PATTERN_WAKE(rxd);
meta->get_ch_info = GET_RX_AX_DESC_CH_INFO(rxd);
meta->rx_statistics = GET_RX_AX_DESC_STATISTICS(rxd);
meta->pattern_idx = GET_RX_AX_DESC_PATTERN_IDX(rxd);
meta->target_idc = GET_RX_AX_DESC_TARGET_IDC(rxd);
meta->chksum_ofld_en = GET_RX_AX_DESC_CHKSUM_OFFLOAD(rxd);
meta->with_llc = GET_RX_AX_DESC_WITH_LLC(rxd);
#endif
meta->chksum_ofld_en = GET_RX_AX_DESC_CHKSUM_OFFLOAD(rxd);
if (meta->long_rxd == 1) {
#if 0
meta->frame_type = GET_RX_AX_DESC_TYPE(rxd);
#endif
meta->mc = GET_RX_AX_DESC_MC(rxd);
meta->bc = GET_RX_AX_DESC_BC(rxd);
#if 0
meta->more_data = GET_RX_AX_DESC_MD(rxd);
#endif
meta->more_frag = GET_RX_AX_DESC_MF(rxd);
#if 0
meta->pwr_bit = GET_RX_AX_DESC_PWR(rxd);
#endif
meta->qos = GET_RX_AX_DESC_QOS(rxd);
meta->tid = GET_RX_AX_DESC_TID(rxd);
#if 0
meta->eosp = GET_RX_AX_DESC_EOSP(rxd);
meta->htc = GET_RX_AX_DESC_HTC(rxd);
#endif
meta->q_null = GET_RX_AX_DESC_QNULL(rxd);
meta->seq = GET_RX_AX_DESC_SEQ(rxd);
meta->frag_num = GET_RX_AX_DESC_FRAG(rxd);
#if 0
meta->sec_cam_idx = GET_RX_AX_DESC_CAM_IDX(rxd);
meta->addr_cam = GET_RX_AX_DESC_ADDR_CAM(rxd);
meta->macid = GET_RX_AX_DESC_MACID(rxd);
meta->rx_pl_id = GET_RX_AX_DESC_PL_ID(rxd);
meta->addr_cam_vld = GET_RX_AX_DESC_CAM_VLD(rxd);
meta->addr_fwd_en = GET_RX_AX_DESC_FWD_EN(rxd);
meta->rx_pl_match = GET_RX_AX_DESC_PL_MATCH(rxd);
#endif
_os_mem_cpy(hal->drv_priv,
(void*)&meta->mac_addr, (void*)(rxd + 24), MAC_ALEN);
}
}
int rtw_hal_mac_sdio_parse_rx(struct rtw_hal_com_t *hal,
struct rtw_rx_buf *rxbuf)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_rxpkt_info info;
struct sdio_rx_pkt *pkt;
u8 *ptr;
u32 len;
int i;
u32 offset;
u32 err = MACSUCCESS;
rxbuf->agg_cnt = 0;
rxbuf->agg_start = 0;
ptr = rxbuf->ptr;
len = rxbuf->len;
for (i = 0; i < MAX_BUS_RX_AGG; i++) {
_os_mem_set(hal->drv_priv, &info, 0, sizeof(info));
err = mac->ops->parse_rxdesc(mac, &info, ptr, len);
if (err != MACSUCCESS) {
PHL_ERR("%s: agg_idx=%d, len=%u(%u), parse_rxdesc FAIL!(%u)\n",
__func__, i, len, rxbuf->len, err);
rxbuf->len -= len;
len = 0;
break;
}
pkt = &rxbuf->pkt[i];
_os_mem_set(hal->drv_priv, pkt, 0, sizeof(*pkt));
pkt->wd = ptr;
pkt->wd_len = (u8)info.rxdlen;
offset = info.rxdlen + (info.drvsize * 8) + (info.shift * 2);
pkt->pkt = ptr + offset;
pkt->pkt_len = (u16)info.pktsize;
hal_mac_parse_rxpkt_info(&info, &pkt->meta);
hal_mac_parse_rxd(hal, ptr, &pkt->meta);
_os_mem_cpy(hal->drv_priv, pkt->meta.ta, pkt->pkt + 10, 6);
offset += info.pktsize;
offset = _ALIGN(offset, 8);
#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
if (pkt->meta.chksum_ofld_en) {
u8 status;
u32 result;
status = *(ptr + offset);
result = mac->ops->chk_rx_tcpip_chksum_ofd(mac, status);
hal_mac_parse_rxd_checksume(hal, &pkt->meta, result);
offset += 8;
}
#endif /* CONFIG_PHL_CSUM_OFFLOAD_RX */
ptr += offset;
if (offset >= len) {
len = 0;
i++;
break;
}
len -= offset;
}
rxbuf->agg_cnt = (u8)i;
if (len) {
/* not finish yet */
rxbuf->next_ptr = ptr;
offset = (u32)(ptr - rxbuf->ptr);
} else {
rxbuf->next_ptr = NULL;
offset = rxbuf->len;
}
return offset;
}
int rtw_hal_mac_sdio_rx(struct rtw_hal_com_t *hal, struct rtw_rx_buf *rxbuf)
{
u32 len;
len = hal_read32(hal, R_AX_SDIO_RX_REQ_LEN) & B_AX_RX_REQ_LEN_MSK;
if (!len)
return 0;
if (len > rxbuf->buf_len) {
/* TODO: read and drop */
return 0;
}
if (_FAIL == hal_sdio_cmd53_r(hal, SDIO_CMD_ADDR_RXFF, len, rxbuf->buffer))
return 0;
rxbuf->used_len = len;
rxbuf->ptr = rxbuf->buffer;
rxbuf->len = len;
#ifndef CONFIG_PHL_SDIO_READ_RXFF_IN_INT
len = rtw_hal_mac_sdio_parse_rx(hal, rxbuf);
#endif
return len;
}
#endif /*CONFIG_SDIO_HCI*/
enum rtw_hal_status rtw_hal_mac_get_pwr_state(struct hal_info_t *hal_info,
enum rtw_mac_pwr_st *pwr_state)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
enum mac_ax_mac_pwr_st st;
if (hal_mac_ops->get_hw_value(mac, MAC_AX_HW_GET_PWR_STATE, &st) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s : retrieve WL MAC state %u\n", __func__, st);
switch (st) {
case MAC_AX_MAC_OFF:
*pwr_state = RTW_MAC_PWR_OFF;
break;
case MAC_AX_MAC_ON:
*pwr_state = RTW_MAC_PWR_ON;
break;
case MAC_AX_MAC_LPS:
*pwr_state = RTW_MAC_PWR_LPS;
break;
default:
*pwr_state = RTW_MAC_PWR_NONE;
break;
}
return RTW_HAL_STATUS_SUCCESS;
}
/* halmac wrapper API for hal and proto type is at hal_api_mac.h */
enum rtw_hal_status
rtw_hal_mac_power_switch(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
u8 on_off)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
//u8 pwr_state = 0;
/*pwr_state = hal_mac_get_pwr_state(mac);
if(pwr_state != on_off)*/
if (mac->ops->pwr_switch(mac, on_off) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef DBG_PHL_MAC_REG_RW
#define HALPHY_BASE_OFFSET 0x10000
bool rtw_hal_mac_reg_chk(struct rtw_hal_com_t *hal_com, u32 addr)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
bool rst = true;
u32 mac_rst;
if (addr & HALPHY_BASE_OFFSET)
goto _exit;
if (mac != NULL && mac->ops->io_chk_access) {
mac_rst = mac->ops->io_chk_access(mac, addr);
if (mac_rst != MACSUCCESS) {
rst = false;
PHL_ERR("%s failed - addr(0x%08x) is err code(%d)\n",
__func__, addr, mac_rst);
_os_warn_on(1);
}
}
_exit:
return rst;
}
#endif
/* halmac wrapper API for hal and proto type is at hal_api_mac.h */
enum rtw_hal_status rtw_hal_mac_dbcc_pre_cfg(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
u8 dbcc_en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_trx_info trx_info = { 0 };
struct mac_ax_pkt_drop_info drop_info = { 0 };
if (dbcc_en) {
if (true == phl_com->dev_cap.tx_mu_ru)
trx_info.trx_mode = MAC_AX_TRX_SW_MODE;
else
trx_info.trx_mode = MAC_AX_TRX_HW_MODE;
trx_info.qta_mode = MAC_AX_QTA_DBCC;
if (mac->ops->dbcc_enable(mac, &trx_info, dbcc_en) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
} else {
/* disable FW band 1 feature (H2C) */
drop_info.sel = MAC_AX_PKT_DROP_SEL_BAND;
drop_info.band = MAC_AX_BAND_1;
if (mac->ops->pkt_drop(mac, &drop_info) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_dbcc_cfg(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
u8 dbcc_en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_trx_info trx_info = { 0 };
if (dbcc_en) {
/* Pass Throught, mac already enable at pre_cfg */
} else {
if (true == phl_com->dev_cap.tx_mu_ru)
trx_info.trx_mode = MAC_AX_TRX_SW_MODE;
else
trx_info.trx_mode = MAC_AX_TRX_HW_MODE;
trx_info.qta_mode = MAC_AX_QTA_SCC;
if (mac->ops->dbcc_enable(mac, &trx_info, dbcc_en) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_mac_coex_init(struct rtw_hal_com_t *hal_com, u8 pta_mode, u8 direction)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_coex pta_para;
pta_para.pta_mode = pta_mode;
pta_para.direction = direction;
return (ops->coex_init(mac, &pta_para));
}
u32 rtw_hal_mac_coex_reg_read(struct rtw_hal_com_t *hal_com, u32 offset, u32 *value)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
/* valid offset -> 0xda00~0xdaff */
offset = offset & 0xff;
return (ops->coex_read(mac, offset, value));
}
u32 rtw_hal_mac_set_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
return (ops->set_hw_value(mac, MAC_AX_HW_SET_SCOREBOARD, value));
}
u32 rtw_hal_mac_get_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
return (ops->get_hw_value(mac, MAC_AX_HW_GET_SCOREBOARD, value));
}
u32 rtw_hal_mac_set_grant(struct rtw_hal_com_t *hal_com, u8 *value)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_coex_gnt gnt_val;
gnt_val.band0.gnt_bt_sw_en = value[0];
gnt_val.band0.gnt_bt = value[1];
gnt_val.band0.gnt_wl_sw_en = value[2];
gnt_val.band0.gnt_wl = value[3];
gnt_val.band1.gnt_bt_sw_en = value[4];
gnt_val.band1.gnt_bt = value[5];
gnt_val.band1.gnt_wl_sw_en = value[6];
gnt_val.band1.gnt_wl = value[7];
return (ops->set_hw_value(mac, MAC_AX_HW_SET_COEX_GNT, &gnt_val));
}
u32 rtw_hal_mac_get_grant(struct rtw_hal_com_t *hal_com, u8 *value)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
return (ops->get_hw_value(mac, MAC_AX_HW_GET_COEX_GNT, value));
}
u32 rtw_hal_mac_set_polluted(struct rtw_hal_com_t *hal_com, u8 band, u8 tx_val, u8 rx_val)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_plt plt_val;
plt_val.band = band;
plt_val.tx = tx_val;
plt_val.rx = rx_val;
return (ops->set_hw_value(mac, MAC_AX_HW_SET_POLLUTED, &plt_val));
}
u32 rtw_hal_mac_set_tx_time(struct rtw_hal_com_t *hal_com, u8 is_btc, u8 is_resume, u8 macid, u32 tx_time)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_max_tx_time max_tx_time;
u32 result = 0xffffffff;
max_tx_time.macid = macid;
max_tx_time.is_cctrl = 1;
max_tx_time.max_tx_time = tx_time;
if (is_btc && !is_resume) { /* for btc control tx time case */
hal_com->btc_ctrl.tx_time = true;
result = ops->set_hw_value(mac, MAC_AX_HW_SET_MAX_TX_TIME, &max_tx_time);
} else if (is_btc && is_resume) { /* for btc release tx time case */
result = ops->set_hw_value(mac, MAC_AX_HW_SET_MAX_TX_TIME, &max_tx_time);
hal_com->btc_ctrl.tx_time = false;
} else { /* not btc control case */
if (hal_com->btc_ctrl.tx_time)
return result;
else
result = ops->set_hw_value(mac, MAC_AX_HW_SET_MAX_TX_TIME, &max_tx_time);
}
return result;
}
u32 rtw_hal_mac_get_tx_time(struct rtw_hal_com_t *hal_com, u8 macid, u32 *tx_time)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_max_tx_time max_tx_time;
u32 result;
max_tx_time.macid = macid;
max_tx_time.is_cctrl = 1;
max_tx_time.max_tx_time = *tx_time;
result = ops->get_hw_value(mac, MAC_AX_HW_GET_MAX_TX_TIME, &max_tx_time);
*tx_time = max_tx_time.max_tx_time;
return (result);
}
u32 rtw_hal_mac_set_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 is_btc, u8 is_resume, u8 macid, u8 tx_retry)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_cctl_rty_lmt_cfg tx_retry_limit;
u32 result = 0xffffffff;
tx_retry_limit.macid = macid;
tx_retry_limit.data_lmt_sel = 1;
tx_retry_limit.data_lmt_val = tx_retry;
tx_retry_limit.rts_lmt_sel = 0;
tx_retry_limit.rts_lmt_val = 0;
if (is_btc && !is_resume) { /* for btc control tx time case */
hal_com->btc_ctrl.tx_retry = true;
result = ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &tx_retry_limit);
} else if (is_btc && is_resume) { /* for btc release tx time case */
result = ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &tx_retry_limit);
hal_com->btc_ctrl.tx_retry = false;
} else { /* not btc control case */
if (hal_com->btc_ctrl.tx_retry)
return result;
else
result = ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &tx_retry_limit);
}
return result;
}
u32 rtw_hal_mac_get_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 macid, u8 *tx_retry)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_rty_lmt tx_retry_limit;
u32 result;
tx_retry_limit.macid = macid;
tx_retry_limit.tx_cnt = *tx_retry;
result = ops->get_hw_value(mac, MAC_AX_HW_GET_DATA_RTY_LMT, &tx_retry_limit);
*tx_retry = (u8)tx_retry_limit.tx_cnt;
return (result);
}
u32 rtw_hal_mac_get_bt_polt_cnt(struct rtw_hal_com_t *hal_com, u8 band, u16 *cnt)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_bt_polt_cnt polt;
u32 result;
polt.band = band;
polt.cnt = *cnt;
result = ops->get_hw_value(mac, MAC_AX_HW_GET_POLLUTED_CNT, &polt);
*cnt = polt.cnt;
return (result);
}
u32 rtw_hal_mac_set_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 val)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
return (ops->set_hw_value(mac, MAC_AX_HW_SET_COEX_CTRL, &val));
}
u32 rtw_hal_mac_get_coex_ctrl(struct rtw_hal_com_t *hal_com, u32* val)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
return (ops->get_hw_value(mac, MAC_AX_HW_GET_COEX_CTRL, val));
}
u32 rtw_hal_mac_coex_reg_write(struct rtw_hal_com_t *hal_com, u32 offset, u32 value)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
/* valid offset -> 0xda00~0xdaff */
offset = offset & 0xff;
return (ops->coex_write(mac, offset, value));
}
/* halmac wrapper API for hal and proto type is at hal_api_drv.h */
u32 rtw_hal_mac_send_h2c(struct rtw_hal_com_t *hal_com,
struct rtw_g6_h2c_hdr *hdr, u32 *pvalue)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
u32 mac_err = 0;
mac_err = ops->outsrc_h2c_common(mac, hdr, pvalue);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
static enum mac_ax_net_type
_rtype_to_mac_nettype(struct rtw_wifi_role_t *wifi_role)
{
enum mac_ax_net_type net_type = MAC_AX_NET_TYPE_NO_LINK;
switch (wifi_role->type) {
case PHL_RTYPE_STATION:
case PHL_RTYPE_TDLS:
net_type = (wifi_role->mstate == MLME_NO_LINK)
? MAC_AX_NET_TYPE_NO_LINK
: MAC_AX_NET_TYPE_INFRA;
break;
case PHL_RTYPE_MONITOR:
case PHL_RTYPE_P2P_DEVICE:
net_type = MAC_AX_NET_TYPE_NO_LINK;
break;
case PHL_RTYPE_P2P_GC:
net_type = MAC_AX_NET_TYPE_INFRA;
break;
case PHL_RTYPE_AP:
case PHL_RTYPE_P2P_GO:
case PHL_RTYPE_MESH:
net_type = MAC_AX_NET_TYPE_AP;
break;
case PHL_RTYPE_ADHOC:
case PHL_RTYPE_ADHOC_MASTER:
net_type = MAC_AX_NET_TYPE_ADHOC;
break;
case PHL_RTYPE_NAN: /*TODO*/
default:
net_type = MAC_AX_NET_TYPE_NO_LINK;
break;
}
return net_type;
}
enum rtw_hal_status
rtw_hal_mac_port_init(struct hal_info_t *hal_info,
struct rtw_wifi_role_t *wifi_role)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_port_init_para ppara = {0};
struct rtw_phl_stainfo_t *phl_sta;
ppara.net_type = _rtype_to_mac_nettype(wifi_role);
ppara.band_idx = wifi_role->hw_band;
ppara.port_idx = wifi_role->hw_port;
/*#ifdef CONFIG_AP*/
ppara.hiq_win = wifi_role->hiq_win;
ppara.dtim_period = wifi_role->dtim_period;
ppara.mbid_num = wifi_role->mbid_num;/*max mbid number*/
/*#endif - CONFIG_AP*/
if (ppara.net_type == MAC_AX_NET_TYPE_INFRA) {
phl_sta = rtw_phl_get_stainfo_self(wifi_role->phl_com->phl_priv,
wifi_role);
if (phl_sta->asoc_cap.bcn_interval)
ppara.bcn_interval = phl_sta->asoc_cap.bcn_interval;
else
ppara.bcn_interval = 100;
ppara.bss_color = phl_sta->asoc_cap.bsscolor;
} else if (ppara.net_type == MAC_AX_NET_TYPE_AP) {
#ifdef RTW_PHL_BCN
ppara.bcn_interval = (u16)wifi_role->bcn_cmn.bcn_interval;
#else
ppara.bcn_interval = 100;
#endif
ppara.bss_color = wifi_role->proto_role_cap.bsscolor;
} else if (ppara.net_type == MAC_AX_NET_TYPE_ADHOC) {
/* TODO */
ppara.bcn_interval = 100;
} else {
/* other net_type, i.e. MAC_AX_NO_LINK */
ppara.bcn_interval = 100;
}
if (mac->ops->port_init(mac, &ppara) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_port_cfg(struct hal_info_t *hal_info,
struct rtw_wifi_role_t *wifi_role,
enum pcfg_type type, void *param)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum mac_ax_port_cfg_type ptype = MAC_AX_PCFG_FUNC_SW;
struct mac_ax_port_cfg_para ppara = {0};
switch (type){
case PCFG_FUNC_SW :
ptype = MAC_AX_PCFG_FUNC_SW;
break;
case PCFG_TBTT_AGG :
ptype = MAC_AX_PCFG_TBTT_AGG;
break;
case PCFG_TBTT_SHIFT :
ptype = MAC_AX_PCFG_TBTT_SHIFT;
break;
case PCFG_HIQ_WIN :
ptype = MAC_AX_PCFG_HIQ_WIN;
break;
case PCFG_HIQ_DTIM :
ptype = MAC_AX_PCFG_HIQ_DTIM;
break;
case PCFG_BCN_INTERVAL :
ptype = MAC_AX_PCFG_BCN_INTV;
break;
case PCFG_BSS_CLR :
ptype = MAC_AX_PCFG_BSS_CLR;
break;
case PCFG_BCN_EN :
ptype = MAC_AX_PCFG_TX_SW;
break;
default :
PHL_ERR("Unknown port cfg type %d\n", type);
goto _error;
}
ppara.band = wifi_role->hw_band;
ppara.port = wifi_role->hw_port;
#ifdef RTW_PHL_BCN/*#ifdef CONFIG_AP*/
ppara.mbssid_idx = wifi_role->hw_mbssid;
#endif
ppara.val = *(u32 *)param;
if (mac->ops->port_cfg(mac, ptype, &ppara) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
_error:
return RTW_HAL_STATUS_FAILURE;
}
static enum mac_ax_wifi_role
_rtype_to_mac_wifirole(struct rtw_wifi_role_t *wifi_role)
{
enum mac_ax_wifi_role mac_wifi_role = MAC_AX_WIFI_ROLE_NONE;
switch (wifi_role->type) {
case PHL_RTYPE_NONE:
mac_wifi_role = MAC_AX_WIFI_ROLE_NONE;
break;
case PHL_RTYPE_STATION:
case PHL_RTYPE_TDLS:
mac_wifi_role = MAC_AX_WIFI_ROLE_STATION;
break;
case PHL_RTYPE_AP:
mac_wifi_role = MAC_AX_WIFI_ROLE_AP;
break;
case PHL_RTYPE_VAP:
mac_wifi_role = MAC_AX_WIFI_ROLE_VAP;
break;
case PHL_RTYPE_ADHOC:
mac_wifi_role = MAC_AX_WIFI_ROLE_ADHOC;
break;
case PHL_RTYPE_ADHOC_MASTER:
mac_wifi_role = MAC_AX_WIFI_ROLE_ADHOC_MASTER;
break;
case PHL_RTYPE_MESH:
mac_wifi_role = MAC_AX_WIFI_ROLE_MESH;
break;
case PHL_RTYPE_MONITOR:
mac_wifi_role = MAC_AX_WIFI_ROLE_MONITOR;
break;
case PHL_RTYPE_P2P_DEVICE:
mac_wifi_role = MAC_AX_WIFI_ROLE_P2P_DEVICE;
break;
case PHL_RTYPE_P2P_GC:
mac_wifi_role = MAC_AX_WIFI_ROLE_P2P_GC;
break;
case PHL_RTYPE_P2P_GO:
mac_wifi_role = MAC_AX_WIFI_ROLE_P2P_GO;
break;
case PHL_RTYPE_NAN:
mac_wifi_role = MAC_AX_WIFI_ROLE_NAN;
break;
default:
mac_wifi_role = MAC_AX_WIFI_ROLE_STATION;
break;
}
return mac_wifi_role;
}
static enum mac_ax_upd_mode
_hal_updmode_to_mac_upt_mode(enum phl_upd_mode mode)
{
enum mac_ax_upd_mode upd_mode = MAC_AX_ROLE_INFO_CHANGE;
switch (mode) {
case PHL_UPD_ROLE_CREATE:
upd_mode = MAC_AX_ROLE_CREATE;
break;
case PHL_UPD_ROLE_REMOVE:
upd_mode = MAC_AX_ROLE_REMOVE;
break;
case PHL_UPD_ROLE_TYPE_CHANGE:
upd_mode = MAC_AX_ROLE_TYPE_CHANGE;
break;
case PHL_UPD_ROLE_INFO_CHANGE:
case PHL_UPD_STA_INFO_CHANGE:
upd_mode = MAC_AX_ROLE_INFO_CHANGE;
break;
case PHL_UPD_STA_CON_DISCONN:
upd_mode = MAC_AX_ROLE_CON_DISCONN;
break;
case PHL_UPD_ROLE_MAX:
/* fallthrough */
default:
PHL_ERR("error upt mode %d\n", mode);
break;
}
return upd_mode;
}
static void _hal_stainfo_to_macrinfo(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta,
struct mac_ax_role_info *rinfo,
enum phl_upd_mode mode,
bool is_connect)
{
struct rtw_wifi_role_t *wifi_role = sta->wrole;
void *drv = hal_to_drvpriv(hal_info);
bool is_self = false;
rinfo->macid = (u8)sta->macid;
rinfo->band = wifi_role->hw_band;
rinfo->port = wifi_role->hw_port;
rinfo->wmm = wifi_role->hw_wmm;
rinfo->net_type = _rtype_to_mac_nettype(wifi_role);
rinfo->wifi_role = _rtype_to_mac_wifirole(wifi_role);
rinfo->bcn_hit_cond = sta->bcn_hit_cond;
rinfo->hit_rule = sta->hit_rule;
rinfo->tsf_sync = wifi_role->hw_port;
rinfo->aid = sta->aid;
rinfo->wapi = sta->wapi;
rinfo->sec_ent_mode = sta->sec_mode;
rinfo->upd_mode = _hal_updmode_to_mac_upt_mode(mode);
rinfo->opmode = (is_connect == true) ? MAC_AX_ROLE_CONNECT : MAC_AX_ROLE_DISCONN;
if (rinfo->net_type == MAC_AX_NET_TYPE_AP) {
if (_os_mem_cmp(drv, wifi_role->mac_addr, sta->mac_addr, MAC_ALEN) == 0)
is_self = true;
if(is_self == true) {
rinfo->self_role = MAC_AX_SELF_ROLE_AP;
} else {
rinfo->self_role = MAC_AX_SELF_ROLE_AP_CLIENT;
/* for ap client disconnect case,
need to set no-link only for MAC_AX_ROLE_CON_DISCONN mode */
if (is_connect == false && rinfo->upd_mode == MAC_AX_ROLE_CON_DISCONN)
rinfo->net_type = MAC_AX_NET_TYPE_NO_LINK;
/* only for client under AX SoftAP mode */
if (sta->wmode & WLAN_MD_11AX)
rinfo->tf_mac_padding = sta->asoc_cap.trig_padding;
}
} else if (rinfo->net_type == MAC_AX_NET_TYPE_INFRA || rinfo->net_type == MAC_AX_NET_TYPE_NO_LINK) {
rinfo->self_role = MAC_AX_SELF_ROLE_CLIENT;
}
if ((sta->wmode & WLAN_MD_11AX) && (wifi_role->mstate == MLME_LINKED)) {
rinfo->trigger = sta->tf_trs;
rinfo->bss_color = sta->asoc_cap.bsscolor;
rinfo->addr_mask = (sta->addr_msk > 0)?MAC_AX_BYTE5:MAC_AX_MSK_NONE;
rinfo->mask_sel = (sta->addr_sel > 0)?MAC_AX_BSSID_MSK:MAC_AX_NO_MSK;
}
//TODO
switch (rinfo->net_type) {
case MAC_AX_NET_TYPE_NO_LINK :
_os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN);
break;
case MAC_AX_NET_TYPE_ADHOC :
_os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN);
break;
case MAC_AX_NET_TYPE_INFRA :
rinfo->aid = sta->aid;
_os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN);
_os_mem_cpy(drv, rinfo->target_mac, sta->mac_addr, MAC_ALEN);
_os_mem_cpy(drv, rinfo->bssid, sta->mac_addr, MAC_ALEN);
break;
case MAC_AX_NET_TYPE_AP :
_os_mem_cpy(drv, rinfo->self_mac, wifi_role->mac_addr, MAC_ALEN);
_os_mem_cpy(drv, rinfo->target_mac, sta->mac_addr, MAC_ALEN);
_os_mem_cpy(drv, rinfo->bssid, wifi_role->mac_addr, MAC_ALEN);
break;
default :
break;
}
}
enum rtw_hal_status
rtw_hal_mac_addr_cam_add_entry(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_role_info mac_rinfo = {0};
u32 rst = 0;
_hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, PHL_UPD_ROLE_CREATE, false);
rst = mac->ops->add_role(mac, &mac_rinfo);
if ((rst == MACSUCCESS) || (rst == MACSAMACID))
return RTW_HAL_STATUS_SUCCESS;
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_addr_cam_change_entry(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta,
enum phl_upd_mode mode,
bool is_connect)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_role_info mac_rinfo = {0};
_hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, mode, is_connect);
if (mac->ops->change_role(mac, &mac_rinfo) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_addr_cam_set_aid(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta,
u16 aid)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_role_info mac_rinfo = {0};
_hal_stainfo_to_macrinfo(hal_info, sta, &mac_rinfo, PHL_UPD_STA_INFO_CHANGE, true);
mac_rinfo.aid = aid;
if (mac->ops->change_role(mac, &mac_rinfo) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_addr_cam_del_entry(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->remove_role(mac, (u8)sta->macid) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_add_key(struct hal_info_t *hal_info, u8 macid, u8 type, u8 ext_key,
u8 spp, u8 keyid, u8 keytype, u8 *keybuf)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
void *drv = hal_to_drvpriv(hal_info);
struct mac_ax_sec_cam_info sec_cam;
u32 mac_err;
sec_cam.type = type;
sec_cam.ext_key = ext_key;
sec_cam.spp_mode = spp;
sec_cam.len = 20;
sec_cam.offset = 0;
_os_mem_set(drv, &sec_cam.key, 0, sizeof(sec_cam.key));
switch (type)
{
case RTW_ENC_WEP40:
_os_mem_cpy(drv, &sec_cam.key, keybuf, 5);
break;
case RTW_ENC_WEP104:
_os_mem_cpy(drv, &sec_cam.key, keybuf, 13);
break;
case RTW_ENC_TKIP:
case RTW_ENC_CCMP:
case RTW_ENC_CCMP256:
case RTW_ENC_GCMP:
case RTW_ENC_GCMP256:
case RTW_ENC_BIP_CCMP128:
case RTW_ENC_WAPI:
case RTW_ENC_GCMSMS4:
_os_mem_cpy(drv, &sec_cam.key, keybuf, 16);
break;
default:
break;
}
mac_err = mac->ops->sta_add_key(mac, &sec_cam, macid, keyid, keytype);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_delete_key(struct hal_info_t *hal_info, u8 macid, u8 type,
u8 ext_key, u8 spp, u8 keyid, u8 keytype)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_err;
mac_err = mac->ops->sta_del_key(mac, macid, keyid, keytype);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
u32
rtw_hal_mac_search_key_idx(struct hal_info_t *hal_info, u8 macid,
u8 keyid, u8 keytype)
{
u32 sec_cam_idx;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
sec_cam_idx = mac->ops->sta_search_key_idx(mac, macid, keyid, keytype);
return sec_cam_idx;
}
u32
rtw_hal_mac_ser_reset_wdt_intr(struct hal_info_t *hal_info)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
u8 dummyval = 0;
u32 result = 0xffffffff;
result = ops->set_hw_value(mac, MAC_AX_HW_SET_WDT_ISR_RST, &dummyval);
return result;
}
enum rtw_hal_status
rtw_hal_mac_ser_get_error_status(struct hal_info_t *hal_info, u32 *err)
{
u32 mac_err = 0;
enum mac_ax_err_info err_info = 0;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac_err = mac->ops->get_err_status(mac, &err_info);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
*err = err_info;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_ser_set_error_status(struct hal_info_t *hal_info, enum RTW_PHL_SER_RCVY_STEP err)
{
u32 mac_err = 0;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 err_info = 0;
if (err == RTW_PHL_SER_L1_DISABLE_EN) {
err_info = MAC_AX_ERR_L1_DISABLE_EN;
} else if (err == RTW_PHL_SER_L1_RCVY_EN) {
err_info = MAC_AX_ERR_L1_RCVY_EN;
} else if (err == RTW_PHL_SER_L0_CFG_NOTIFY) {
err_info = MAC_AX_ERR_L0_CFG_NOTIFY;
} else if (err == RTW_PHL_SER_L0_CFG_DIS_NOTIFY) {
err_info = MAC_AX_ERR_L0_CFG_DIS_NOTIFY;
} else if (err == RTW_PHL_SER_L0_CFG_HANDSHAKE) {
err_info = MAC_AX_ERR_L0_CFG_HANDSHAKE;
} else if (err == RTW_PHL_SER_L0_RCVY_EN) {
err_info = MAC_AX_ERR_L0_RCVY_EN;
}
PHL_INFO("%s : error info to mac 0x%x.\n", __func__, err_info);
mac_err = mac->ops->set_err_status(mac, err_info);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_trigger_cmac_err(struct hal_info_t *hal_info)
{
u32 mac_err = 0;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac_err = mac->ops->trigger_cmac_err(mac);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_trigger_dmac_err(struct hal_info_t *hal_info)
{
u32 mac_err = 0;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac_err = mac->ops->trigger_dmac_err(mac);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_lv1_rcvy(struct hal_info_t *hal_info, enum rtw_phl_ser_lv1_recv_step step)
{
u32 mac_err = 0;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac_err = mac->ops->lv1_rcvy(mac, step);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_ser_ctrl(struct hal_info_t *hal_info, bool en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_err = 0;
enum mac_ax_func_sw cfg = (en == true) ? MAC_AX_FUNC_EN : MAC_AX_FUNC_DIS;
u32 start_t = 0;
start_t = _os_get_cur_time_us();
PHL_INFO("%s\n", __func__);
mac_err = mac->ops->ser_ctrl(mac, cfg);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s : %s ser success with %d us.\n", __func__,
(en ? "start" : "stop"), phl_get_passing_time_us(start_t));
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_poll_hw_tx_done(struct hal_info_t *hal_info)
{
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "poll hw tx done is not supported now!\n");
return RTW_HAL_STATUS_MAC_API_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_hw_tx_resume(struct hal_info_t *hal_info)
{
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "resume hw tx is not supported now!\n");
return RTW_HAL_STATUS_MAC_API_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_poll_hw_rx_done(struct hal_info_t *hal_info)
{
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "poll hw rx done is not supported now!\n");
return RTW_HAL_STATUS_MAC_API_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_hw_rx_resume(struct hal_info_t *hal_info)
{
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "resume hw rx is not supported now!\n");
return RTW_HAL_STATUS_MAC_API_FAILURE;
}
#define FW_PLE_SIZE 0x800
#define FW_PLE_SEGMENT_SIZE 512 /*Because PHL_PRINT have prefix 5 bytes "PHL: "*/
void
_hal_fw_dbg_dump(struct hal_info_t *hal_info, u8 *buffer, u16 bufsize)
{
char str[FW_PLE_SEGMENT_SIZE + 1] = {0};
u16 i = 0, ofst = 0;
for (ofst = 0; ofst < bufsize; ofst += FW_PLE_SEGMENT_SIZE) {
for (i = 0; i < FW_PLE_SEGMENT_SIZE; i++) {
_os_snprintf(str + i, 1, "%c",
buffer[i + ofst]);
}
PHL_PRINT("%s\n", str);
_os_mem_set(hal_to_drvpriv(hal_info), str, 0, sizeof(str));
}
}
enum rtw_hal_status
rtw_hal_mac_dump_fw_rsvd_ple(struct hal_info_t *hal_info)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u8 *buffer = NULL;
u16 bufSize = FW_PLE_SIZE;
if(mac->ops->dump_fw_rsvd_ple(mac, &buffer) != 0) {
PHL_ERR("%s fail!\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
if (buffer != NULL) {
PHL_PRINT("=======================\n");
PHL_PRINT("Start to dump fw rsvd ple :\n\n");
_hal_fw_dbg_dump(hal_info, buffer, bufSize);
PHL_PRINT("\n=======================\n");
_os_mem_free(hal_info->hal_com->drv_priv, buffer, bufSize);
} else {
PHL_ERR("dump_fw_rsvd_ple return invalid buffer!\n");
}
return RTW_HAL_STATUS_SUCCESS;
}
/*
* halmac wrapper API for hal and proto type is at hal_api_mac.h
* init HW scope or start HW scope?
*/
enum rtw_hal_status
rtw_hal_mac_init_mac(void *mac,struct hal_init_info_t *init_info)
{
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct mac_ax_ops *hal_mac_ops = mac_info->ops;
struct mac_ax_trx_info trx_info;
trx_info.trx_mode = init_info->trx_info.trx_mode;
trx_info.qta_mode = init_info->trx_info.qta_mode;
if (hal_mac_ops->sys_init(mac_info))
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
if (hal_mac_ops->trx_init(mac_info, &trx_info))
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_trx_init(void *mac, struct hal_init_info_t *init_info)
{
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct mac_ax_ops *hal_mac_ops = mac_info->ops;
struct mac_ax_trx_info trx_info;
trx_info.trx_mode = init_info->trx_info.trx_mode;
trx_info.qta_mode = init_info->trx_info.qta_mode;
if (hal_mac_ops->trx_init(mac_info, &trx_info))
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
void _hal_mac_get_ofld_cap(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_status = 0;
mac_status = mac->ops->get_hw_value(mac, MAC_AX_HW_GET_FW_CAP,
&(hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap));
if (mac_status == MACSUCCESS) {
phl_com->dev_cap.fw_cap.offload_cap = phl_com->dev_sw_cap.fw_cap.offload_cap &
hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap;
PHL_INFO("%s: sw ofld cap: 0x%x, fw ofld cap 0x%x, final ofld cap: 0x%x!\n", __func__,
phl_com->dev_sw_cap.fw_cap.offload_cap,
hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap,
phl_com->dev_cap.fw_cap.offload_cap);
} else {
hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap = 0;
phl_com->dev_cap.fw_cap.offload_cap = 0;
PHL_WARN("%s: fw ofld cap not enabled.\n", __func__);
}
#else
hal_info->hal_com->dev_hw_cap.fw_cap.offload_cap = 0;
phl_com->dev_cap.fw_cap.offload_cap = 0;
PHL_INFO("%s: fw ofld cap not enabled.\n", __func__);
#endif
}
enum rtw_hal_status
rtw_hal_mac_hal_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_fw_info_t *fw_info = &phl_com->fw_info;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
struct mac_ax_fwdl_info fwdl_info;
u32 mac_status = 0;
enum rtw_fw_type fw_type = RTW_FW_MAX;
#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
u8 tx_chksum_offload = 0;
u8 rx_chksum_offload = 0;
#endif
FUNCIN_WSTS(hstatus);
#ifdef PHL_FEATURE_NIC
fw_type = RTW_FW_NIC;
#elif defined(PHL_FEATURE_AP)
fw_type = RTW_FW_AP;
#else
fw_type = RTW_FW_MAX;
#endif
hstatus = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, fw_type);
if(RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_ERR("%s : Cfg FW Failed: %d!\n", __func__, hstatus);
return hstatus;
}
/* fwdl_info */
fwdl_info.fw_en = fw_info->fw_en;
fwdl_info.dlram_en = fw_info->dlram_en;
fwdl_info.dlrom_en = fw_info->dlrom_en;
fwdl_info.ram_buff = fw_info->ram_buff;
fwdl_info.ram_size = fw_info->ram_size;
fwdl_info.rom_buff = fw_info->rom_buff;
fwdl_info.rom_size = fw_info->rom_size;
fwdl_info.fw_cat = fw_info->fw_type;
if(fw_info->fw_src == RTW_FW_SRC_EXTNAL)
fwdl_info.fw_from_hdr = 0;
else
fwdl_info.fw_from_hdr = 1;
mac_status = mac->ops->hal_init(mac, &init_info->trx_info, &fwdl_info, &init_info->intf_info);
if (mac_status == MACSUCCESS) {
hstatus = RTW_HAL_STATUS_SUCCESS;
hal_mac_print_fw_version(hal_info);
} else {
hstatus = RTW_HAL_STATUS_MAC_INIT_FAILURE;
PHL_ERR("%s : mac_status %d!\n", __func__, mac_status);
}
_hal_mac_get_ofld_cap(phl_com, hal_info);
#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
rx_chksum_offload = 1;
mac_status = mac->ops->tcpip_chksum_ofd(mac, tx_chksum_offload, rx_chksum_offload);
if (mac_status != MACSUCCESS)
PHL_ERR("%s : tcpip_chksum_ofd mac_status %d!!!!!!!\n", __func__, mac_status);
#endif
FUNCOUT_WSTS(hstatus);
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_hal_fast_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_fw_info_t *fw_info = &phl_com->fw_info;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
struct mac_ax_fwdl_info fwdl_info;
u32 mac_status = 0;
enum rtw_fw_type fw_type = RTW_FW_MAX;
FUNCIN_WSTS(hstatus);
#ifdef PHL_FEATURE_NIC
fw_type = RTW_FW_NIC;
#elif defined(PHL_FEATURE_AP)
fw_type = RTW_FW_AP;
#else
fw_type = RTW_FW_MAX;
#endif
hstatus = hal_ops->hal_cfg_fw(phl_com, hal_info, init_info->ic_name, fw_type);
if(RTW_HAL_STATUS_SUCCESS != hstatus) {
PHL_ERR("%s : Cfg FW Failed: %d!\n", __func__, hstatus);
return hstatus;
}
/* fwdl_info */
fwdl_info.fw_en = fw_info->fw_en;
fwdl_info.dlram_en = fw_info->dlram_en;
fwdl_info.dlrom_en = fw_info->dlrom_en;
fwdl_info.ram_buff = fw_info->ram_buff;
fwdl_info.ram_size = fw_info->ram_size;
fwdl_info.rom_buff = fw_info->rom_buff;
fwdl_info.rom_size = fw_info->rom_size;
fwdl_info.fw_cat = fw_info->fw_type;
if(fw_info->fw_src == RTW_FW_SRC_EXTNAL)
fwdl_info.fw_from_hdr = 0;
else
fwdl_info.fw_from_hdr = 1;
mac_status = mac->ops->hal_fast_init(mac, &init_info->trx_info, &fwdl_info, &init_info->intf_info);
if (mac_status == MACSUCCESS)
hstatus = RTW_HAL_STATUS_SUCCESS;
else {
hstatus = RTW_HAL_STATUS_HAL_INIT_FAILURE;
PHL_ERR("%s : mac_status %d!\n", __func__, mac_status);
}
FUNCOUT_WSTS(hstatus);
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_hal_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_status = 0;
mac_status = mac->ops->hal_deinit(mac);
if (mac_status == MACSUCCESS)
hstatus = RTW_HAL_STATUS_SUCCESS;
else
PHL_ERR("%s : mac_status %d!\n", __func__, mac_status);
FUNCOUT_WSTS(hstatus);
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_chk_allq_empty(struct hal_info_t *hal_info, u8 *empty)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
if (hal_mac_ops->chk_allq_empty(mac, empty))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef CONFIG_WOWLAN
enum rtw_hal_status
rtw_hal_mac_cfg_wow_sleep(struct hal_info_t *hal_info, u8 sleep)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
if (hal_mac_ops->cfg_wow_sleep(mac,sleep))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_wow_fw_status(struct hal_info_t *hal_info, u8 *status, u8 func_en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
if (hal_mac_ops->get_wow_fw_status(mac,status, func_en))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_keep_alive(struct hal_info_t *hal_info, u16 macid, u8 en,
struct rtw_keep_alive_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_keep_alive_info info = {0};
if (en && cfg == NULL)
return RTW_HAL_STATUS_FAILURE;
_os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info));
if (en) {
info.keepalive_en = cfg->keep_alive_en;
info.period = cfg->keep_alive_period;
info.packet_id = cfg->null_pkt_id;
}
if (hal_mac_ops->cfg_keepalive(mac, (u8)macid, &info))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_disc_dec(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_disc_det_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_disconnect_det_info info = {0};
if (en && cfg == NULL)
return RTW_HAL_STATUS_FAILURE;
_os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info));
if (en) {
info.disconnect_detect_en = cfg->disc_det_en;
info.disconnect_en = (cfg->disc_wake_en == 1) ? 0 : 1;
info.check_period = cfg->check_period;
info.try_pkt_count = cfg->try_pkt_count;
info.tryok_bcnfail_count_en = cfg->cnt_bcn_lost_en;
info.tryok_bcnfail_count_limit = cfg->cnt_bcn_lost_limit;
}
if (hal_mac_ops->cfg_disconnect_det(mac, (u8)macid, &info))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_dev2hst_gpio(struct hal_info_t *hal_info, u8 en, struct rtw_wow_gpio_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_dev2hst_gpio_info info = {0};
if (en && cfg == NULL)
return RTW_HAL_STATUS_FAILURE;
_os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info));
if (en) {
info.dev2hst_gpio_en = cfg->dev2hst_gpio_en;
info.disable_inband = cfg->disable_inband;
info.gpio_output_input = cfg->gpio_output_input;
info.gpio_active = cfg->gpio_active;
info.toggle_pulse = cfg->toggle_pulse;
info.data_pin_wakeup = cfg->data_pin_wakeup;
info.gpio_pulse_nonstop = cfg->gpio_pulse_nonstop;
info.gpio_time_unit = cfg->gpio_time_unit;
info.gpio_num = cfg->dev2hst_gpio;
info.gpio_pulse_dura = cfg->gpio_pulse_dura;
info.gpio_pulse_period = cfg->gpio_pulse_period;
info.gpio_pulse_count = cfg->gpio_pulse_count;
info.customer_id = cfg->customer_id;
info.gpio_pulse_en_a = cfg->gpio_pulse_en_a;
info.gpio_duration_unit_a = cfg->gpio_duration_unit_a;
info.gpio_pulse_nonstop_a = cfg->gpio_pulse_nonstop_a;
info.special_reason_a = cfg->special_reason_a;
info.gpio_duration_a = cfg->gpio_duration_a;
info.gpio_pulse_count_a = cfg->gpio_pulse_count_a;
}
if (hal_mac_ops->cfg_dev2hst_gpio(mac, &info))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_wow_wake(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_wow_wake_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_wow_wake_info info = {0};
struct mac_ax_remotectrl_info_parm_ *content = NULL;
struct mac_ax_remotectrl_info_parm_ param;
if (en && cfg == NULL)
return RTW_HAL_STATUS_FAILURE;
_os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info));
if (en) {
info.wow_en = cfg->wow_en;
info.drop_all_pkt = cfg->drop_all_pkt;
info.rx_parse_after_wake = cfg->rx_parse_after_wake;
info.pairwise_sec_algo = cfg->pairwise_sec_algo;
info.group_sec_algo = cfg->group_sec_algo;
/*
info.bip_sec_algo = cfg->bip_sec_algo;
*/
info.pattern_match_en = cfg->pattern_match_en;
info.magic_en = cfg->magic_pkt_en;
info.hw_unicast_en = cfg->hw_unicast_en;
info.fw_unicast_en = cfg->fw_unicast_en;
info.deauth_wakeup = cfg->deauth_wakeup;
info.rekey_wakeup = cfg->rekey_wakeup;
info.eap_wakeup = cfg->eap_wakeup;
info.all_data_wakeup = cfg->all_data_wakeup;
if (cfg->pairwise_sec_algo) {
param.validcheck = cfg->remote_wake_ctrl_info.valid_check;
param.symbolchecken = cfg->remote_wake_ctrl_info.symbol_check_en;
param.lastkeyid = cfg->remote_wake_ctrl_info.gtk_key_idx;
_os_mem_cpy(hal_to_drvpriv(hal_info), param.ptktxiv, cfg->remote_wake_ctrl_info.ptk_tx_iv, IV_LENGTH);
_os_mem_cpy(hal_to_drvpriv(hal_info), param.rxptkiv, cfg->remote_wake_ctrl_info.ptk_rx_iv, IV_LENGTH);
_os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_0, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx0, IV_LENGTH);
_os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_1, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx1, IV_LENGTH);
_os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_2, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx2, IV_LENGTH);
_os_mem_cpy(hal_to_drvpriv(hal_info), param.rxgtkiv_3, cfg->remote_wake_ctrl_info.gtk_rx_iv_idx3, IV_LENGTH);
content = ¶m;
}
}
/* should pass cfg->remote_wake_ctrl_info to halmac */
if (hal_mac_ops->cfg_wow_wake(mac, (u8)macid, &info, content))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_wake_rsn(struct hal_info_t *hal_info, u8 *wake_rsn, u8 *reset)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
if (hal_mac_ops->get_wow_wake_rsn(mac, wake_rsn, reset) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_ndp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_ndp_ofld_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_ndp_ofld_info info = {0};
struct mac_ax_ndp_info_parm_ content[2];
void* drv_priv = hal_to_drvpriv(hal_info);
u8 idx = 0;
if (en && cfg == NULL)
return RTW_HAL_STATUS_FAILURE;
_os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_ndp_ofld_info));
_os_mem_set(drv_priv, content, 0, sizeof(struct mac_ax_ndp_info_parm_)*2);
if (en) {
info.ndp_en = cfg->ndp_en;
info.na_id = cfg->ndp_id;
for (idx = 0; idx < 2; idx++) {
content[idx].enable = cfg->ndp_ofld_content[idx].ndp_en;
_os_mem_cpy(drv_priv,content[idx].targetlinkaddress,
cfg->ndp_ofld_content[idx].mac_addr, MAC_ADDRESS_LENGTH);
content[idx].checkremoveip = cfg->ndp_ofld_content[idx].chk_remote_ip;
_os_mem_cpy(drv_priv,content[idx].remoteipv6address,
cfg->ndp_ofld_content[idx].remote_ipv6_addr, IPV6_ADDRESS_LENGTH);
content[idx].numberoftargetip = cfg->ndp_ofld_content[0].num_target_ip;
_os_mem_cpy(drv_priv,&(content[idx].targetip[0][0]),
&(cfg->ndp_ofld_content[idx].target_ipv6_addr[0][0]), IPV6_ADDRESS_LENGTH*2);
}
}
if (hal_mac_ops->cfg_ndp_ofld(mac, (u8)macid, &info, content))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_arp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en,
struct rtw_arp_ofld_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_arp_ofld_info info = {0};
if (en && cfg == NULL)
return RTW_HAL_STATUS_FAILURE;
if (en) {
info.arp_en = cfg->arp_en;
info.arp_rsp_id = cfg->arp_rsp_id;
info.arp_action = cfg->arp_action;
}
if (hal_mac_ops->cfg_arp_ofld(mac, (u8)macid, &info, NULL))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_wow_cam(struct hal_info_t *hal_info, u16 macid, u8 en,
struct rtw_pattern_match_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct rtw_wowcam_upd_info *wowcam_info = NULL;
struct mac_ax_wowcam_upd_info info;
void* drv_priv = hal_to_drvpriv(hal_info);
u8 i = 0;
u8 j = 0;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s (en: %u) ==>\n", __func__, en);
if (en && cfg == NULL) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for input cfg == NULL\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
/* config each wow cam, no matter valid or not */
for (i = 0; i < MAX_WOW_CAM_NUM; ++i) {
_os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_wowcam_upd_info));
if (en) {
wowcam_info = &(cfg->wowcam_info[i]);
info.idx = wowcam_info->wow_cam_idx;
info.r_w = wowcam_info->rw;
info.valid = wowcam_info->valid;
if (wowcam_info->valid != 0) {
info.wkfm1 = wowcam_info->wake_mask[0];
info.wkfm2 = wowcam_info->wake_mask[1];
info.wkfm3 = wowcam_info->wake_mask[2];
info.wkfm4 = wowcam_info->wake_mask[3];
info.crc = wowcam_info->match_crc;
info.negative_pattern_match = wowcam_info->is_negative_pattern_match;
info.skip_mac_hdr = wowcam_info->skip_mac_hdr;
info.uc = wowcam_info->uc;
info.mc = wowcam_info->mc;
info.bc = wowcam_info->bc;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "wow_cam [%u]:\n", info.idx);
for (j = 0; j < 4; ++j)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- wake_mask[%u] = 0x%08x\n", j, wowcam_info->wake_mask[j]);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rw, crc = (%u, 0x%08x)\n", info.r_w, info.crc);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- Neg_ptn_mtch = %u\n", info.negative_pattern_match);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- SkipMacHdr = %u\n", info.skip_mac_hdr);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- (UC, MC, BC) = (%u, %u, %u)\n", info.uc, info.mc, info.bc);
} else {
continue;
}
} else {
info.idx = i;
info.r_w = 1;
info.valid = 0;
}
if (hal_mac_ops->cfg_wowcam_upd(mac, &info)) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for cfg wowcam(%u)\n", __func__, info.idx);
return RTW_HAL_STATUS_FAILURE;
}
}
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s() <==\n", __func__);
return RTW_HAL_STATUS_SUCCESS;
}
static u32 _hal_mac_recv_aoac_report(struct mac_ax_adapter *mac, struct mac_ax_aoac_report *buf, u8 rx_rdy)
{
struct mac_ax_ops *hal_mac_ops = mac->ops;
u32 mac_status = 0;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s(): request aoac report.\n", __func__);
mac_status = hal_mac_ops->request_aoac_report(mac, rx_rdy);
if (mac_status) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== mac_status(%u) from request_aoac_report()\n", __func__, mac_status);
return mac_status;
}
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s(): read aoac report\n", __func__);
mac_status = hal_mac_ops->read_aoac_report(mac, buf, rx_rdy);
if (mac_status) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== get mac_status(%u) from read_aoac_report()\n", __func__, mac_status);
return mac_status;
}
return mac_status;
}
#define KEY_ID_MASK 0x3
#define KEY_ID_OFFSET 6
enum rtw_hal_status _hal_mac_aoac_rpt_chk(struct rtw_aoac_report *aoac_info)
{
u8 key_id_from_iv = 0;
u32 rx_iv = *((u32 *)aoac_info->ptk_rx_iv);
/* Case I. Aoac report is all zero in phase 0 */
if (rx_iv == 0) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): ptk_rx_iv is Zero, treating this case as error.\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
/* Case II. KEY_IDX does not match with GTK_RX_IV */
key_id_from_iv = (aoac_info->gtk_rx_iv[aoac_info->key_idx][3] >> KEY_ID_OFFSET) & KEY_ID_MASK;
if (key_id_from_iv != aoac_info->key_idx) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): Key_idx(%u) not match with the one(%u) parsed from GTK_RX_IV[%u]\n",
__func__, aoac_info->key_idx, key_id_from_iv, aoac_info->key_idx);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
/*
AOAC_RPT - PHASE 0:
Halmac will get aoac report through c2h reg.
(Cuz at this moment, the rx is still blocked by host.
The rx cannot be resume only if those IV be updated by aoac_rpt)
In PHASE 0, Fw will transfer some necessary info,
such as RX_IV, GTK_KEY_ID, GTK_RX_IV, Rekey_OK and iGTK_ipn.
*/
enum rtw_hal_status
_hal_mac_read_aoac_rpt_phase_0(void* drv_priv, struct mac_ax_aoac_report *aoac_rpt_buf, struct rtw_aoac_report *aoac_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
aoac_info->rekey_ok = aoac_rpt_buf->rekey_ok;
aoac_info->key_idx = aoac_rpt_buf->key_idx;
_os_mem_cpy(drv_priv, aoac_info->ptk_rx_iv, aoac_rpt_buf->ptk_rx_iv, IV_LENGTH);
switch (aoac_info->key_idx) {
case 0:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[0], aoac_rpt_buf->gtk_rx_iv_0, IV_LENGTH);
break;
case 1:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[1], aoac_rpt_buf->gtk_rx_iv_1, IV_LENGTH);
break;
case 2:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[2], aoac_rpt_buf->gtk_rx_iv_2, IV_LENGTH);
break;
case 3:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[3], aoac_rpt_buf->gtk_rx_iv_3, IV_LENGTH);
break;
default:
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): Unknown gtk_key_idx(%u)\n", __func__, aoac_info->key_idx);
break;
}
if (aoac_info->rekey_ok)
_os_mem_cpy(drv_priv, aoac_info->igtk_ipn, aoac_rpt_buf->igtk_ipn, sizeof(aoac_rpt_buf->igtk_ipn));
hal_status = _hal_mac_aoac_rpt_chk(aoac_info);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "PHASE 0:\n");
debug_dump_data((u8 *)aoac_rpt_buf, sizeof(struct mac_ax_aoac_report), "aoac_report");
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rekey_ok = %u\n", aoac_info->rekey_ok);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- key_idx = %u\n", aoac_info->key_idx);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- ptk_rx_iv = 0x%08x%08x\n", *((u32*)(aoac_info->ptk_rx_iv)+1), *((u32*)(aoac_info->ptk_rx_iv)));
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- gtk_rx_iv[%u] = 0x%08x%08x\n",
aoac_info->key_idx,
*((u32*)(aoac_info->gtk_rx_iv[aoac_info->key_idx])+1),
*((u32*)(aoac_info->gtk_rx_iv[aoac_info->key_idx])));
if (aoac_info->rekey_ok)
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- igtk_ipn = 0x%08x%08x\n", *((u32*)(aoac_info->igtk_ipn)+1), *((u32*)(aoac_info->igtk_ipn)));
return hal_status;
}
/*
AOAC_RPT - PHASE 1:
Halmac will get aoac report through c2h pkt.
(Cuz at this moment,
the host has resumed the rx, c2h pkt can be used here.)
In PHASE 1, Fw will transfer all info in aoac report.
Those entries got in phase 0 should remain the same value in phase 1.
*/
enum rtw_hal_status
_hal_mac_read_aoac_rpt_phase_1(void* drv_priv, struct mac_ax_aoac_report *aoac_rpt_buf, struct rtw_aoac_report *aoac_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
u8 i = 0;
aoac_info->rpt_ver = aoac_rpt_buf->rpt_ver;
aoac_info->sec_type = aoac_rpt_buf->sec_type;
aoac_info->pattern_idx = aoac_rpt_buf->pattern_idx;
_os_mem_cpy(drv_priv, aoac_info->ptk_tx_iv, aoac_rpt_buf->ptk_tx_iv, IV_LENGTH);
for (i = 0; i < 4; ++i) {
switch (i) {
case 0:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[0], aoac_rpt_buf->gtk_rx_iv_0, IV_LENGTH);
break;
case 1:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[1], aoac_rpt_buf->gtk_rx_iv_1, IV_LENGTH);
break;
case 2:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[2], aoac_rpt_buf->gtk_rx_iv_2, IV_LENGTH);
break;
case 3:
_os_mem_cpy(drv_priv, aoac_info->gtk_rx_iv[3], aoac_rpt_buf->gtk_rx_iv_3, IV_LENGTH);
break;
default:
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s(): Unknown gtk_key_idx(%u)\n", __func__, aoac_info->key_idx);
break;
}
}
_os_mem_cpy(drv_priv, aoac_info->gtk, aoac_rpt_buf->gtk, sizeof(aoac_rpt_buf->gtk));
_os_mem_cpy(drv_priv, aoac_info->eapol_key_replay_count, aoac_rpt_buf->eapol_key_replay_count, sizeof(aoac_rpt_buf->eapol_key_replay_count));
_os_mem_cpy(drv_priv, aoac_info->igtk_key_id, aoac_rpt_buf->igtk_key_id, sizeof(aoac_rpt_buf->igtk_key_id));
_os_mem_cpy(drv_priv, aoac_info->igtk, aoac_rpt_buf->igtk, sizeof(aoac_rpt_buf->igtk));
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "PHASE 1:\n");
debug_dump_data((u8 *)aoac_rpt_buf, sizeof(struct mac_ax_aoac_report), "aoac_report");
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rekey_ok = %u\n", aoac_info->rekey_ok);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- key_idx = %u\n", aoac_info->key_idx);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- ptk_rx_iv = 0x%08x%08x\n", *((u32*)(aoac_info->ptk_rx_iv)+1), *((u32*)(aoac_info->ptk_rx_iv)));
for(i = 0; i < 4; ++i) {
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- gtk_rx_iv[%u] = 0x%08x%08x\n",
i,
*((u32*)(aoac_info->gtk_rx_iv[i])+1),
*((u32*)(aoac_info->gtk_rx_iv[i])));
}
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- ptk_tx_iv = 0x%08x%08x\n", *((u32*)(aoac_info->ptk_tx_iv)+1), *((u32*)(aoac_info->ptk_tx_iv)));
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- rpt_ver = %u\n", aoac_info->rpt_ver);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- sec_type = %u\n", aoac_info->sec_type);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- pattern_idx = %u\n", aoac_info->pattern_idx);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- eapol_key_replay_cnt = 0x%08x%08x\n", *((u32*)(aoac_info->eapol_key_replay_count)+1), *((u32*)(aoac_info->eapol_key_replay_count)));
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "- igtk_key_id = 0x%08x%08x\n", *((u32*)(aoac_info->igtk_key_id)+1), *((u32*)(aoac_info->igtk_key_id)));
debug_dump_data(aoac_info->gtk, sizeof(aoac_rpt_buf->gtk), "GTK:");
debug_dump_data(aoac_info->igtk, sizeof(aoac_rpt_buf->igtk), "iGTK:");
return hal_status;
}
enum rtw_hal_status
rtw_hal_mac_get_aoac_rpt(struct hal_info_t *hal_info, struct rtw_aoac_report *aoac_info, u8 rx_ready)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#ifndef RTW_WKARD_WOW_SKIP_AOAC_RPT
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
#endif
struct mac_ax_aoac_report aoac_rpt_buf;
void* drv_priv = hal_to_drvpriv(hal_info);
u32 mac_status = 0;
if (aoac_info == NULL) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for input info == NULL\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
#ifdef RTW_WKARD_WOW_SKIP_AOAC_RPT
mac_status = MACPROCERR;
#else
mac_status = _hal_mac_recv_aoac_report(mac, &aoac_rpt_buf, rx_ready);
#endif
if (mac_status) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for _hal_mac_recv_aoac_report fail with mac_status(%u).\n",
__func__, mac_status);
hal_status = RTW_HAL_STATUS_FAILURE;
} else {
if (rx_ready == 0)
hal_status = _hal_mac_read_aoac_rpt_phase_0(drv_priv, &aoac_rpt_buf, aoac_info);
else
hal_status = _hal_mac_read_aoac_rpt_phase_1(drv_priv, &aoac_rpt_buf, aoac_info);
}
return hal_status;
}
enum rtw_hal_status
rtw_hal_mac_cfg_gtk_ofld(struct hal_info_t *hal_info, u16 macid, u8 en,
struct rtw_gtk_ofld_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_gtk_ofld_info info;
struct mac_ax_gtk_info_parm_ param;
void* drv_priv = hal_to_drvpriv(hal_info);
_os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_gtk_ofld_info));
_os_mem_set(drv_priv, ¶m, 0, sizeof(struct mac_ax_gtk_info_parm_));
if (en && cfg == NULL) {
PHL_TRACE(COMP_PHL_WOW, _PHL_WARNING_, "%s() <== RTW_HAL_STATUS_FAILURE for input cfg == NULL\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
if (en) {
info.gtk_en = cfg->gtk_en;
info.tkip_en = cfg->tkip_en;
info.ieee80211w_en = cfg->ieee80211w_en;
info.pairwise_wakeup = cfg->pairwise_wakeup;
info.gtk_rsp_id = cfg->gtk_rsp_id;
info.algo_akm_suit = cfg->akmtype_byte3;
if (info.gtk_en) {
_os_mem_cpy(drv_priv, param.kck, cfg->gtk_ofld_content.kck, cfg->gtk_ofld_content.kck_len);
_os_mem_cpy(drv_priv, param.kek, cfg->gtk_ofld_content.kek, cfg->gtk_ofld_content.kek_len);
if (info.tkip_en)
_os_mem_cpy(drv_priv, param.rxmickey, cfg->gtk_ofld_content.rxmickey, TKIP_MIC_KEY_LENGTH);
}
if (info.ieee80211w_en) {
info.bip_sec_algo = cfg->bip_sec_algo;
info.pmf_sa_query_id = cfg->sa_query_id;
_os_mem_cpy(drv_priv, param.igtk_keyid, cfg->gtk_ofld_content.igtk_keyid, cfg->gtk_ofld_content.igtk_len);
_os_mem_cpy(drv_priv, param.ipn, cfg->gtk_ofld_content.ipn, IGTK_PKT_NUM_LENGTH);
_os_mem_cpy(drv_priv, param.igtk, &(cfg->gtk_ofld_content.igtk[0]), cfg->gtk_ofld_content.igtk_len);
if (cfg->hw_11w_en == 0)
_os_mem_cpy(drv_priv, param.sk, cfg->gtk_ofld_content.psk, cfg->gtk_ofld_content.psk_len);
}
} else {
info.gtk_en = false;
info.ieee80211w_en = false;
}
if (hal_mac_ops->cfg_gtk_ofld(mac, (u8)macid, &info, ¶m))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_cfg_realwow(struct hal_info_t *hal_info, u16 macid, u8 en,
struct rtw_realwow_info *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_realwow_info info = {0};
struct mac_ax_realwowv2_info_parm_ param = {0};
void *drv_priv = hal_to_drvpriv(hal_info);
_os_mem_set(drv_priv, &info, 0, sizeof(struct mac_ax_realwow_info));
_os_mem_set(drv_priv, ¶m, 0, sizeof(struct mac_ax_realwowv2_info_parm_));
if (en) {
info.realwow_en = cfg->realwow_en;
info.auto_wakeup = cfg->auto_wakeup;
info.keepalive_id = cfg->keepalive_id;
info.wakeup_pattern_id = cfg->wakeup_pattern_id;
info.ack_pattern_id = cfg->ack_pattern_id;
if (info.realwow_en) {
param.interval = cfg->realwow_ofld_content.interval;
param.kapktsize = cfg->realwow_ofld_content.keep_alive_pkt_size;
param.acklostlimit = cfg->realwow_ofld_content.ack_lost_limit;
param.ackpatternsize = cfg->realwow_ofld_content.ack_ptrn_size;
param.wakeuppatternsize = cfg->realwow_ofld_content.wakeup_ptrn_size;
param.wakeupsecnum = cfg->realwow_ofld_content.wakeup_sec_num;
}
} else {
info.realwow_en = false;
}
if (hal_mac_ops->cfg_realwow(mac, (u8)macid, &info, ¶m))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_set_wowlan(struct hal_info_t *hal, u8 enter)
{
u32 mac_err = 0;
struct mac_ax_adapter *mac = hal_to_mac(hal);
enum mac_ax_wow_ctrl ctrl = (enter == 1) ? MAC_AX_WOW_ENTER : MAC_AX_WOW_LEAVE;
mac_err = mac->ops->intf_ops->set_wowlan(mac, ctrl);
if (mac_err != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
static bool _wow_is_txq_empty(struct mac_ax_tx_queue_empty *val)
{
u8 i = 0;
u8 size = ARRAY_SIZE(val->macid_txq_empty);
if (!val->others_empty)
return false;
if (!val->band0_mgnt_empty)
return false;
if (!val->band1_mgnt_empty)
return false;
for (i = 0; i < size; i++) {
if (val->macid_txq_empty[i] != 0xFF)
return false;
}
PHL_INFO("%s : others_empty %d.\n", __func__, val->others_empty);
PHL_INFO("%s : band0_mgnt_empty %d.\n", __func__, val->band0_mgnt_empty);
PHL_INFO("%s : band1_mgnt_empty %d.\n", __func__, val->band1_mgnt_empty);
for (i = 0; i < size; i++)
PHL_INFO("%s : macid_txq_empty[%d] %d.\n", __func__, i, val->macid_txq_empty[i]);
return true;
}
#define MAX_WOW_POLLNG_TXQ_EMPTY_TIME 50000 /* us */
#define MAX_WOW_CHK_TXQ_EMPTY_CNT 2 /* continously check ok should satisfied this value */
enum rtw_hal_status rtw_hal_mac_wow_chk_txq_empty(struct hal_info_t *hal, u8 *empty)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_tx_queue_empty val = {0};
u32 start_t = _os_get_cur_time_us();
u8 chk_cnt = 0;
while (1) {
if (phl_get_passing_time_us(start_t) >= MAX_WOW_POLLNG_TXQ_EMPTY_TIME) {
PHL_ERR("%s : reach maximum polling time.\n", __func__);
break;
}
for (chk_cnt = 0; chk_cnt < MAX_WOW_CHK_TXQ_EMPTY_CNT; chk_cnt++) {
if (mac->ops->is_txq_empty(mac, &val) != MACSUCCESS)
break;
if (!_wow_is_txq_empty(&val)) {
break;
} else {
*empty = 1;
}
}
if (*empty)
break;
_os_delay_us(hal_to_drvpriv(hal), 50);
}
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : polling empty %d with duration %d.\n",
__func__, *empty, phl_get_passing_time_us(start_t));
return hstatus;
}
enum rtw_hal_status rtw_hal_mac_wow_wde_drop(struct hal_info_t *hal, u8 band)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_pkt_drop_info info = {0};
u32 mac_err = 0;
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s with band %d.\n", __func__, band);
info.sel = MAC_AX_PKT_DROP_SEL_BAND_ONCE;
info.band = band;
mac_err = mac->ops->pkt_drop(mac, &info);
if (mac_err != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#endif /* CONFIG_WOWLAN */
static enum rtw_hal_status
hal_mac_read_efuse(struct mac_ax_adapter *mac, u32 addr, u32 size,
u8 *val, enum mac_ax_efuse_bank bank)
{
if (mac->ops->read_efuse(mac, addr, size, val, bank) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
static enum rtw_hal_status
hal_mac_write_efuse(struct mac_ax_adapter *mac, u32 addr, u8 val,
enum mac_ax_efuse_bank bank)
{
if (mac->ops->write_efuse(mac, addr, val, bank) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_enable_cpu(struct hal_info_t *hal_info, u8 reason, u8 dlfw)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->enable_cpu(mac, reason, dlfw) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_disable_cpu(struct hal_info_t *hal_info)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->disable_cpu(mac) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_romdl(struct hal_info_t *hal_info, u8 *rom_buf, u32 rom_size)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 rom_addr = 0x18900000;
if (mac->ops->romdl(mac, rom_buf, rom_addr, rom_size) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_fwdl(struct hal_info_t *hal_info, u8 *fw_buf, u32 fw_size)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_err;
mac_err = mac->ops->fwdl(mac, fw_buf, fw_size);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
hal_mac_print_fw_version(hal_info);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_enable_fw(struct hal_info_t *hal_info, u8 fw_type)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_err;
mac_err = mac->ops->enable_fw(mac, fw_type);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
hal_mac_print_fw_version(hal_info);
return RTW_HAL_STATUS_SUCCESS;
}
/* */
/**
* rtw_hal_mac_ax_fill_txdesc
* @mac: see struct mac_ax_adapter
* @treq: the xmit request for this tx descriptor
* @wd_buf: the wd buffer to fill
* @wd_len: output, return the total length of filled wd
*
* Note,halmac API for hal and proto type is at hal_api_mac.h
*/
enum rtw_hal_status
rtw_hal_mac_ax_fill_txdesc(void *mac, struct rtw_xmit_req *treq,
u8 *wd_buf, u32 *wd_len)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
*wd_len = mac_info->ops->txdesc_len(
mac_info,
&treq->mdata);
hal_status = mac_info->ops->build_txdesc(
mac_info,
&treq->mdata, wd_buf, *wd_len);
return hal_status;
}
/**
* rtw_hal_mac_set_hw_ampdu_cfg
* @hal_info: see struct hal_info_t
* @band: target band this AMPDU going to send
* @max_agg_num: AMPDU maximum aggregation number
* @max_agg_time: AMPDU maximum aggregation time, in unit of 32 us
*
* Note,
* (1) halmac API for hal and proto type is at hal_api_mac.h
*/
enum rtw_hal_status
rtw_hal_mac_set_hw_ampdu_cfg(struct hal_info_t *hal_info,
u8 band,
u16 max_agg_num, u8 max_agg_time)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_ampdu_cfg info;
u32 mac_err;
_os_mem_set(hal_to_drvpriv(hal_info), &info, 0, sizeof(info));
info.band = band;
info.wdbk_mode = MAC_AX_WDBK_MODE_SINGLE_BK;
info.rty_bk_mode = MAC_AX_RTY_BK_MODE_AGG;
info.max_agg_num = max_agg_num;
info.max_agg_time_32us = max_agg_time;
mac_err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_AMPDU_CFG, &info);
if (mac_err != MACSUCCESS)
goto fail;
return RTW_HAL_STATUS_SUCCESS;
fail:
return RTW_HAL_STATUS_MAC_API_FAILURE;
}
/**
* the function to update DMAC control info by halmac api
* @hal_info: see struct hal_info_t
* @dctl_info: structure of dmac control information, define by halmac
* @macid: the macid corresponding to this cmac control info
*
* return RTW_HAL_STATUS_MAC_API_FAILURE if update fail
*/
enum rtw_hal_status rtw_hal_dmc_tbl_cfg(struct hal_info_t *hal_info,
struct mac_ax_dctl_info *dctl_info,
struct mac_ax_dctl_info *dctl_info_mask,
u16 macid)
{
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 ret = 0;
ret = mac->ops->upd_dctl_info(mac, dctl_info, dctl_info_mask, (u8)macid, 1);
if (0 == ret) {
sts = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "mac_upd_dctl_info fail (0x%08X)\n",
ret);
sts = RTW_HAL_STATUS_MAC_API_FAILURE;
}
return sts;
}
/**
* the function to update CMAC control info by halmac api
* @hal_info: see struct hal_info_t
* @cctl_info: structure of cmac control information, define by halmac
* @macid: the macid corresponding to this cmac control info
*
* return RTW_HAL_STATUS_MAC_API_FAILURE if update fail
*/
enum rtw_hal_status rtw_hal_cmc_tbl_cfg(struct hal_info_t *hal_info,
struct mac_ax_cctl_info *cctl_info,
struct mac_ax_cctl_info *cctl_info_mask,
u16 macid)
{
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 ret = 0;
cctl_info_mask->addr_cam_index = 0;
ret = mac->ops->upd_cctl_info(mac, cctl_info, cctl_info_mask, (u8)macid, 1);
if (0 == ret) {
sts = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "mac_upd_cctl_info fail (0x%08X)\n",
ret);
sts = RTW_HAL_STATUS_MAC_API_FAILURE;
}
return sts;
}
/**
* the function to update BA CAM entry by halmac api
* @hal_info: see struct hal_info_t
* @ba_cam: structure of ba cam entry, define by halmac
*
* return RTW_HAL_STATUS_MAC_API_FAILURE if update fail
*/
enum rtw_hal_status rtw_hal_bacam_cfg(struct hal_info_t *hal_info,
struct mac_ax_bacam_info *ba_cam)
{
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 ret = 0;
ret = mac->ops->bacam_info(mac, ba_cam);
if (0 == ret) {
sts = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "mac_bacam_info fail (0x%08X)\n",
ret);
sts = RTW_HAL_STATUS_MAC_API_FAILURE;
}
return sts;
}
/**
* rtw_hal_mac_set_bw() - Update channel and bandwdith related setting
* @hal_info: struct hal_info_t*
* @band_idx: 0x0: band0, 0x1: band1
* @ch: center channel
* @band: band
* @bw: bandwidth
*
* All channel and bandwidth related MAC setting would be done in
* this function.
* Following setting may be done in this functions:
* a. Enable changing CCK data rate to OFDM 6M function
* to avoid BB/RF abnormal when channel is not 2.4G.
*
* Return RTW_HAL_STATUS_SUCCESS when operation success.
*/
enum rtw_hal_status rtw_hal_mac_set_bw(struct hal_info_t *hal_info,
u8 band_idx, u8 pri_ch, u8 central_ch_seg0,
u8 central_ch_seg1, enum band_type band,
enum channel_width bw)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_cfg_bw mac_bw = {0};
u32 ret = 0;
mac_bw.cbw = bw;
mac_bw.band = band_idx;
mac_bw.pri_ch = pri_ch;
mac_bw.central_ch = central_ch_seg0;
ret = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_BW_CFG, &mac_bw);
return (ret == 0) ? (RTW_HAL_STATUS_SUCCESS): (RTW_HAL_STATUS_FAILURE);
}
/**
* rtw_hal_mac_ax_init_bf_role
* @bf_role: 0 = BFEE, 1 = BFER
* @band: 0 = BAND0, 1 = BAND1
*/
enum rtw_hal_status
rtw_hal_mac_ax_init_bf_role(struct rtw_hal_com_t *hal_com, u8 bf_role, u8 band)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac_info = hal_to_mac(hal_info);
if (bf_role == HAL_BF_ROLE_BFEE) {
hal_status = mac_info->ops->init_snd_mee(
mac_info, band);
} else {
hal_status = mac_info->ops->init_snd_mer(
mac_info, band);
};
return hal_status;
}
/**
* rtw_hal_mac_ax_disable_bfee
* @band: 0 = BAND0, 1 = BAND1
*/
enum rtw_hal_status
rtw_hal_mac_ax_deinit_bfee(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "--> %s : Warning BFee is going to deinit\n", __func__);
hal_status = mac_info->ops->deinit_mee(mac_info, band);
return hal_status;
}
/**
* rtw_hal_mac_ax_bfee_para_reg
* Set BFee capability with STA info by method : Control Register
* input:
* @sta: (struct rtw_phl_stainfo_t *)
*/
enum rtw_hal_status
rtw_hal_mac_ax_bfee_para_reg(void *mac, struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)mac_info->drv_adapter;
struct mac_reg_csi_para csi_para;
_os_mem_set(hal_com->drv_priv, &csi_para, 0, sizeof(csi_para));
csi_para.band = sta->wrole->hw_band;
csi_para.portsel = (sta->wrole->hw_port == 0) ? 0 : 1;
csi_para.nc = (sta->wrole->proto_role_cap.max_nc > sta->asoc_cap.num_snd_dim) ?
sta->asoc_cap.num_snd_dim :
sta->wrole->proto_role_cap.max_nc;
csi_para.nr = (sta->wrole->proto_role_cap.bfme_sts >
sta->asoc_cap.num_snd_dim) ?
sta->asoc_cap.num_snd_dim :
sta->wrole->proto_role_cap.bfme_sts;
/**
* For HE/VHT, Ng = 0 can provide the most detail information.
* Ng do not care bfer cap.
**/
csi_para.ng = 0;
/**
* for HE/VHT, Cb = 1 {6,4}/{9,7} can provide the most detail information
* Cb do not care bfer cap, only care bfee self capabiltiy.
**/
if (sta->wmode & WLAN_MD_11AX)
csi_para.cb = sta->wrole->proto_role_cap.cb_sz_su_fb;
else if (sta->wmode & WLAN_MD_11AC)
csi_para.cb = sta->wrole->proto_role_cap.ht_vht_cb;
else
csi_para.cb = 0;
csi_para.cs = 1; /* Carrier Sense */
if (sta->asoc_cap.ht_ldpc &&
sta->asoc_cap.vht_ldpc &&
sta->asoc_cap.he_ldpc)
csi_para.ldpc_en = 1;
if (sta->asoc_cap.stbc_ht_rx &&
sta->asoc_cap.stbc_vht_rx &&
sta->asoc_cap.stbc_he_rx)
csi_para.stbc_en = 1;
csi_para.bf_en = 0;
hal_status = mac_info->ops->set_csi_para_reg(mac_info, &csi_para);
return hal_status;
}
/**
* rtw_hal_mac_ax_bfee_para_cctl
* Set BFee capability with STA info by method : CMAC Control Table
* input:
* @sta: (struct rtw_phl_stainfo_t *)
*/
enum rtw_hal_status
rtw_hal_mac_ax_bfee_para_cctl(void *mac, struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct rtw_hal_com_t *hal_com =
(struct rtw_hal_com_t *)mac_info->drv_adapter;
struct mac_cctl_csi_para csi_para;
_os_mem_set(hal_com->drv_priv, &csi_para, 0, sizeof(csi_para));
csi_para.macid = (u8)sta->macid;
csi_para.band = sta->wrole->hw_band;
csi_para.nc = (sta->wrole->proto_role_cap.max_nc > sta->asoc_cap.num_snd_dim) ?
sta->asoc_cap.num_snd_dim :
sta->wrole->proto_role_cap.max_nc;
csi_para.nr = (sta->wrole->proto_role_cap.bfme_sts >
sta->asoc_cap.num_snd_dim) ?
sta->asoc_cap.num_snd_dim :
sta->wrole->proto_role_cap.bfme_sts;
/**
* For HE/VHT, Ng = 0 can provide the most detail information.
* Ng do not care bfer cap.
**/
csi_para.ng = 0;
/**
* for HE/VHT, Cb = 1 {6,4}/{9,7} can provide the most detail information
* Cb do not care bfer cap.
**/
if (sta->wmode & WLAN_MD_11AX)
csi_para.cb = sta->wrole->proto_role_cap.cb_sz_su_fb;
else if (sta->wmode & WLAN_MD_11AC)
csi_para.cb = sta->wrole->proto_role_cap.ht_vht_cb;
else
csi_para.cb = 0;
csi_para.cs = 1;
csi_para.bf_en = 0;
if (sta->asoc_cap.stbc_ht_rx &&
sta->asoc_cap.stbc_vht_rx &&
sta->asoc_cap.stbc_he_rx)
csi_para.stbc_en = 1;
if (sta->asoc_cap.ht_ldpc &&
sta->asoc_cap.vht_ldpc &&
sta->asoc_cap.he_ldpc)
csi_para.ldpc_en = 1;
csi_para.rate = MAC_AX_OFDM54;
csi_para.gi_ltf = MAC_AX_SGI_4XHE08;
csi_para.gid_sel = 1;
csi_para.bw = MAC_AX_BW_20M;
hal_status = mac_info->ops->set_csi_para_cctl(mac_info, &csi_para);
return hal_status;
}
enum rtw_hal_status
rtw_hal_mac_ax_bfee_set_csi_rrsc(void *mac, u8 band, u32 rrsc)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
hal_status = mac_info->ops->csi_rrsc(mac_info, band, rrsc);
return hal_status;
}
/**
* rtw_hal_mac_ax_bfee_forced_csi_rate
* set bf report frame rate
* @mac:(struct mac_ax_adapter *)
* @ht_rate:
* @vht_rate:
* @he_rate:
*/
enum rtw_hal_status
rtw_hal_mac_ax_bfee_forced_csi_rate(void *mac, struct rtw_phl_stainfo_t *sta,
u8 ht_rate, u8 vht_rate, u8 he_rate)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
hal_status = mac_info->ops->csi_force_rate(mac_info,
sta->wrole->hw_band, ht_rate, vht_rate, he_rate);
return hal_status;
}
/**
* rtw_hal_mac_ax_set_bf_entry
* set HW BF entry for sounding and TxBF
* input :
* @band: BF Entry is band0 or band1;
* @macid: BF Entry's macid
* @bfee_idx: SU/MU HW Entry Index
* @txbf_idx: Tx BF CSI Entry Index
* @buffer_idx: CSI Buffer idx used by TxBF entry
*/
enum rtw_hal_status
rtw_hal_mac_ax_set_bf_entry(void *mac, u8 band,
u8 macid, u8 bfee_idx, u16 txbf_idx, u16 buffer_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
/* 1. CSI Buffer Idx */
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "set_csi_buffer_index : band 0x%x macid 0x%x txbf_idx 0x%x buffer_idx 0x%x\n",
band, macid, txbf_idx, buffer_idx);
hal_status = mac_info->ops->set_csi_buffer_index(mac_info, band, macid,
txbf_idx, buffer_idx);
/*TODO: this api might revised in the future */
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "set_snd_sts_index: band 0x%x macid 0x%x bf_idx 0x%x\n",
band, macid, bfee_idx);
hal_status = mac_info->ops->set_snd_sts_index(
mac_info, band, macid, bfee_idx);
return hal_status;
}
/**
* rtw_hal_mac_ax_get_snd_sts
* Get HW BF entry sounding status
* input :
* @band: BF Entry is band0 or band1;
* @bfee_idx: SU/MU HW Entry Index
* return
* @hal_status: enum rtw_hal_status
* RTW_HAL_STATUS_SUCCESS = Sounding Success
* RTW_HAL_STATUS_FAILURE = Sounding Fail
*/
enum rtw_hal_status
rtw_hal_mac_ax_get_snd_sts(void *mac, u8 band, u8 bfee_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
u32 sts = 0;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "get_snd_sts_index: band 0x%x bf_idx 0x%x\n", band, bfee_idx);
/*TODO: This API shall modify to return sounding status instead of CR value*/
/*MAC Define : #define B_AX_MER_SU_BFMEE0_SND_STS BIT(9)*/
sts = mac_info->ops->get_snd_sts_index(mac_info, band, bfee_idx);
if (sts & B_AX_MER_SU_BFMEE0_SND_STS)
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
/**
* rtw_hal_mac_ax_hw_snd_control
* @band: 0 = BAND0, 1 = BAND1
* @hw_snd_ctrl: 0 = HW_SND_PAUSE 1 = HW_SND_RELEASE
*/
enum rtw_hal_status
rtw_hal_mac_ax_hw_snd_control(
void *mac,
u8 band,
u8 hw_snd_ctrl)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"mac_hw_snd_pause_release: band 0x%x hw_snd_ctrl 0x%x\n",
band, hw_snd_ctrl);
hal_status = mac_info->ops->hw_snd_pause_release(
mac_info,
band,
hw_snd_ctrl);
return hal_status;
}
/* Tx Frame Exchange Related : MU */
/**
* rtw_hal_mac_ax_mu_sta_upd
* @mac: (struct mac_ax_adapter *)
* @macid: sta macid for configuration
* @bfmu_idx: 0~5, MU STA Index
* @prot_type: RTS/CTS type for the group : enum rtw_hal_protection_type
* @resp_type: Ack Policy for the group : enum rtw_hal_ack_resp_type
* @grp_bitmap: group bitmap for STA,
**/
enum rtw_hal_status
rtw_hal_mac_ax_mu_sta_upd(void *mac, u8 macid, u8 bfmu_idx,
enum rtw_hal_protection_type prot_type,
enum rtw_hal_ack_resp_type resp_type, u8 mugrp_bm)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct rtw_hal_com_t *hal_com =
(struct rtw_hal_com_t *)mac_info->drv_adapter;
struct mac_ax_mu_sta_upd sta_info;
u8 i = 0;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> rtw_hal_mac_ax_mu_sta_upd \n");
_os_mem_set(hal_com->drv_priv, &sta_info, 0, sizeof(sta_info));
sta_info.macid = macid;
sta_info.mu_idx = bfmu_idx;
for (i = 0; i < 5; i++) {
if (mugrp_bm & BIT(i)) {
sta_info.prot_rsp_type[i].u.feld_type.protect =
prot_type & 0xF;
sta_info.prot_rsp_type[i].u.feld_type.rsp =
resp_type & 0xF;
} else {
sta_info.prot_rsp_type[i].u.feld_type.protect = 0;
sta_info.prot_rsp_type[i].u.feld_type.rsp = 0;
}
}
sta_info.mugrp_bitmap = mugrp_bm & 0x1F;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta_info.macid = 0x%x \n", sta_info.macid);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta_info.mu_idx = 0x%x \n", sta_info.mu_idx);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta_info.mugrp_bitmap = 0x%x \n", sta_info.mugrp_bitmap);
hal_status = mac_info->ops->mu_sta_upd(mac_info, &sta_info);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "<== rtw_hal_mac_ax_mu_sta_upd \n");
return hal_status;
}
/**
* rtw_hal_mac_ax_mu_decision_para
* @mac: (struct mac_ax_adapter *)
* @mu_thold: MU MIMO pkt Threshold
* @bypass_thold: by pass mu_thold
* @bypass_tp: by pass MU TP > SU TP check.
**/
enum rtw_hal_status
rtw_hal_mac_ax_mu_decision_para(void *mac, u32 mu_thold,
bool bypass_thold, bool bypass_tp)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct rtw_hal_com_t *hal_com =
(struct rtw_hal_com_t *)mac_info->drv_adapter;
struct mac_ax_mudecision_para mu_d_para;
_os_mem_set(hal_com->drv_priv, &mu_d_para, 0, sizeof(mu_d_para));
mu_d_para.mu_thold = mu_thold;
mu_d_para.bypass_thold = bypass_thold ? 1 : 0;
mu_d_para.bypass_tp = bypass_tp ? 1 : 0;
hal_status = mac_info->ops->upd_mudecision_para(mac_info, &mu_d_para);
return hal_status;
}
/**
* rtw_hal_mac_ax_set_mu_fix_mode
* @mac: (struct mac_ax_adapter *)
* @gid: GID for STA X + STAY
* @prot_type: RTS/CTS type for the group : enum rtw_hal_protection_type
* @resp_type: Ack Policy for the group : enum rtw_hal_ack_resp_type
* @fix_mu: true = Fix FW decision = MU
* @he: true = Fix TX HE MU, false = Fix TX VHT MU;
* @fix_resp: fix frame exchange ack policy
* @fix_prot: fix frame exchange protection type
**/
enum rtw_hal_status
rtw_hal_mac_ax_set_mu_fix_mode(
void *mac, u8 gid, enum rtw_hal_protection_type prot_type,
enum rtw_hal_ack_resp_type resp_type,
bool fix_mu, bool he, bool fix_resp, bool fix_prot)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct rtw_hal_com_t *hal_com =
(struct rtw_hal_com_t *)mac_info->drv_adapter;
struct mac_ax_fixmode_para fix_info;
PHL_INFO("===>rtw_hal_mac_ax_set_mu_fix_mode\n");
_os_mem_set(hal_com->drv_priv, &fix_info, 0, sizeof(fix_info));
fix_info.force_sumuru_en = fix_mu ? 1:0 ;
fix_info.forcemu = fix_mu ? 1:0 ;
if (fix_mu) {
if (!he){
fix_info.fix_fe_vhtmu_en = fix_prot ? 1 : 0;
fix_info.fix_frame_seq_vhtmu = fix_resp ? 1 : 0;
fix_info.prot_type_vhtmu = fix_prot ? prot_type : 5;/*default hw setting*/
fix_info.resp_type_vhtmu = fix_resp ? resp_type : 4;/*default hw setting*/
PHL_INFO("fix_info.prot_type_vhtmu = 0x%x\n", fix_info.prot_type_vhtmu);
PHL_INFO("fix_info.resp_type_vhtmu = 0x%x\n", fix_info.resp_type_vhtmu);
} else {
fix_info.fix_fe_hemu_en = fix_prot ? 1 : 0;;
fix_info.fix_frame_seq_hemu = fix_resp ? 1 : 0;
fix_info.prot_type_hemu = fix_prot ? prot_type : 5;/*default hw setting*/
fix_info.resp_type_hemu = fix_resp ? resp_type : 4;/*default hw setting*/
PHL_INFO("fix_info.prot_type_hemu = 0x%x\n", fix_info.prot_type_hemu);
PHL_INFO("fix_info.resp_type_hemu = 0x%x\n", fix_info.resp_type_hemu);
}
fix_info.mugrpid = gid;
PHL_INFO("fix_info.mugrpid = 0x%x\n", fix_info.mugrpid);
}
hal_status = mac_info->ops->set_fw_fixmode(mac_info, &fix_info);
PHL_INFO("<===rtw_hal_mac_ax_set_mu_fix_mode\n");
return hal_status;
}
void
_hal_mac_fill_mu_sc_tbl_row(u32 *mac_score, void *hal_score)
{
struct hal_mu_score_tbl_score *h_score =
(struct hal_mu_score_tbl_score *)hal_score;
*mac_score = (u32)h_score->score[0] |
((u32)h_score->score[1] << 8) | ((u32)h_score->valid << 10) |
((u32)h_score->macid << 11);
}
/**
* rtw_hal_mac_ax_set_mu_table_whole
* @mac: (struct mac_ax_adapter *)
*@hal_score_tbl: struct hal_mu_score_tbl *
*/
enum rtw_hal_status
rtw_hal_mac_ax_set_mu_table_whole(void *mac, void *hal_score_tbl)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac_info = (struct mac_ax_adapter *)mac;
struct rtw_hal_com_t *hal_com =
(struct rtw_hal_com_t *)mac_info->drv_adapter;
struct mac_mu_table mu_table;
struct hal_mu_score_tbl *score_tbl = (struct hal_mu_score_tbl *)hal_score_tbl;
_os_mem_set(hal_com->drv_priv, &mu_table, 0, sizeof(mu_table));
/*TODO: halmac api shall refine!!!*/
mu_table.mu_score_tbl_ctrl = (score_tbl->mu_ctrl.mu_sc_thr) |
(score_tbl->mu_ctrl.mu_opt << 2);
/*TODO: if next IC has more than 6 MU STAs!!! */
_hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_0, &score_tbl->mu_score[0]);
_hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_1, &score_tbl->mu_score[1]);
_hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_2, &score_tbl->mu_score[2]);
_hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_3, &score_tbl->mu_score[3]);
_hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_4, &score_tbl->mu_score[4]);
_hal_mac_fill_mu_sc_tbl_row(&mu_table.mu_score_tbl_5, &score_tbl->mu_score[5]);
hal_status = mac_info->ops->set_mu_table(mac_info, &mu_table);
return hal_status;
}
enum rtw_hal_status
rtw_hal_mac_parse_c2h(void *hal, u8 *buf, u32 buf_len, void *c2h)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
hal_status = mac->ops->process_c2h(mac, buf, buf_len, (u8 *)c2h);
return hal_status;
}
/**
* Required information in (hal_handle_rx_buffer_XXXXX case RX_DESC_PKT_TYPE_PPDU_STATUS),
* it cannot be used by core/phl/other hal module
**/
void
_hal_mac_ax_ppdu_sts_to_hal_ppdu_sts(
struct mac_ax_ppdu_rpt *mac_ppdu, void *hal_ppdu_sts)
{
struct hal_ppdu_sts *hal_ppdu =
(struct hal_ppdu_sts *)hal_ppdu_sts;
u8 i = 0;
u32 j = 0;
hal_ppdu->rx_cnt_ptr = mac_ppdu->rx_cnt_ptr;
hal_ppdu->phy_st_ptr = mac_ppdu->phy_st_ptr;
hal_ppdu->plcp_ptr = mac_ppdu->plcp_ptr;
hal_ppdu->plcp_size = mac_ppdu->plcp_size;
hal_ppdu->phy_st_size = mac_ppdu->phy_st_size;
hal_ppdu->rx_cnt_size = mac_ppdu->rx_cnt_size;
hal_ppdu->usr_num = mac_ppdu->usr_num;
for(i = 0; i < mac_ppdu->usr_num; i++) {
if(1 == mac_ppdu->usr[i].vld) {
hal_ppdu->usr[i].vld = 1;
hal_ppdu->usr[i].macid = mac_ppdu->usr[i].macid;
hal_ppdu->usr[i].has_data = mac_ppdu->usr[i].has_data;
hal_ppdu->usr[i].has_ctrl = mac_ppdu->usr[i].has_ctrl;
hal_ppdu->usr[i].has_mgnt = mac_ppdu->usr[i].has_mgnt;
hal_ppdu->usr[i].has_bcn = mac_ppdu->usr[i].has_bcn;
}
}
/* process / decode rx cnt report */
/* TODO: Halmac api shall provid decoder */
if ((0 != hal_ppdu->rx_cnt_size) && (NULL != hal_ppdu->rx_cnt_ptr)) {
for(j = 0; (j < (hal_ppdu->rx_cnt_size/2)) &&
(j < HAL_RXCNT_MAX); j++) {
hal_ppdu->rx_cnt.ppdu_cnt[j] =
((u16)*(hal_ppdu->rx_cnt_ptr + 2 * j));
}
}
}
/**
* if any information is required for other core/phl module,
* copy to rx meta data or hal_info from halmac ax ppdu status.
**/
void
_hal_mac_ax_ppdu_sts_to_hal_info(struct hal_info_t *hal_info,
struct mac_ax_ppdu_rpt *mac_ppdu, void *rx_mdata)
{
/* struct rtw_r_meta_data *mdata =
(struct rtw_r_meta_data *)rx_mdata; */
return;
}
/**
* rtw_hal_mac_ax_parse_ppdu_sts
* @hal:(struct hal_info_t *)
* @mac_valid:if mac information invalid (from rx desc)
* @buf: pointer of ppdu status, point to header of mac_info
* @buf_l:ppdu status payload size
* @ppdu_sts: (struct hal_ppdu_sts *) for return value to hal
* @rx_mdata: (struct rtw_r_meta_data *) for saving ppdu status
*/
enum rtw_hal_status
rtw_hal_mac_ax_parse_ppdu_sts(void *hal, u8 mac_valid, u8 *buf, u16 buf_l,
void *ppdu_sts, void *rx_mdata)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_ppdu_rpt ppdu_rpt = {0};
PHL_DBG("%s\n", __FUNCTION__);
hal_status = mac->ops->parse_ppdu(hal_info->mac, buf, buf_l,
mac_valid, &ppdu_rpt);
if (hal_status == RTW_HAL_STATUS_SUCCESS) {
_hal_mac_ax_ppdu_sts_to_hal_ppdu_sts(&ppdu_rpt, ppdu_sts);
_hal_mac_ax_ppdu_sts_to_hal_info(hal_info ,&ppdu_rpt,
rx_mdata);
}
return hal_status;
}
/**
* the function to enable HW header conversion function
* @hal_info: see struct hal_info_t
* @en_hdr_conv: true to enable, false to disable
*
* return RTW_HAL_STATUS_MAC_API_FAILURE if update fail
*/
enum rtw_hal_status rtw_hal_hdr_conv_cfg(struct hal_info_t *hal_info,
u8 en_hdr_conv)
{
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 ret = 0;
ret = mac->ops->hdr_conv(mac, en_hdr_conv);
if (MACSUCCESS == ret) {
sts = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MAC, _PHL_WARNING_, "hdr_conv fail (0x%08X)\n",
ret);
sts = RTW_HAL_STATUS_MAC_API_FAILURE;
}
return sts;
}
#ifdef RTW_PHL_BCN //fill hal mac ops
enum rtw_hal_status
hal_mac_ax_config_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct rtw_bcn_info_cmn *bcn_cmn = bcn_entry->bcn_cmn;
struct rtw_bcn_info_hw *bcn_hw = &bcn_entry->bcn_hw;
enum mac_ax_port_cfg_type ptype;
struct mac_ax_port_cfg_para ppara = {0};
ppara.band = bcn_hw->band;
ppara.port = bcn_hw->port;
ppara.mbssid_idx = bcn_hw->mbssid;
ptype = MAC_AX_PCFG_BCN_INTV;
ppara.val = bcn_cmn->bcn_interval;
if (mac->ops->port_cfg(mac, ptype, &ppara) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
ptype = MAC_AX_PCFG_HIQ_DTIM;
ppara.val = bcn_cmn->bcn_dtim;
if (mac->ops->port_cfg(mac, ptype, &ppara) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
hal_mac_ax_send_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct rtw_bcn_info_cmn *bcn_cmn = bcn_entry->bcn_cmn;
struct rtw_bcn_info_hw *bcn_hw = &bcn_entry->bcn_hw;
struct mac_ax_bcn_info info = {0};
if(!mac->ops->send_bcn_h2c)
return RTW_HAL_STATUS_FAILURE;
info.pld_buf = bcn_cmn->bcn_buf;
info.pld_len = (u16)bcn_cmn->bcn_length;
info.band = bcn_hw->band;
info.port = bcn_hw->port;
info.mbssid = bcn_hw->mbssid;
info.grp_ie_ofst = (u8)bcn_cmn->ie_offset_tim;
info.macid = bcn_hw->mac_id;
if(bcn_cmn->bcn_offload & BIT(BCN_HW_TIM))
info.grp_ie_ofst |= BIT(7);
if(bcn_cmn->bcn_offload & BIT(BCN_HW_SEQ)){
info.ssn_sel = 1;
info.ssn_mode = 1;
}
else {
info.ssn_sel = 0;
info.ssn_mode = 0;
}
info.rate_sel = (u16)bcn_cmn->bcn_rate;
mac->ops->send_bcn_h2c(mac, &info);
return RTW_HAL_STATUS_SUCCESS;
}
#endif //RTW_PHL_BCN
enum rtw_hal_status
rtw_hal_mac_ppdu_stat_cfg(struct hal_info_t *hal_info,
u8 band_idx,
bool ppdu_stat_en,
u8 appen_info,
u8 filter)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_phy_rpt_cfg cfg = {0};
cfg.en = ppdu_stat_en;
cfg.type = MAC_AX_PPDU_STATUS;
/*cfg.dest = MAC_AX_PRPT_DEST_HOST;*/
cfg.u.ppdu.band = band_idx;
if (ppdu_stat_en) {
if (appen_info&HAL_PPDU_MAC_INFO)
cfg.u.ppdu.bmp_append_info |= MAC_AX_PPDU_MAC_INFO;
if (appen_info&HAL_PPDU_PLCP)
cfg.u.ppdu.bmp_append_info |= MAC_AX_PPDU_PLCP;
if (appen_info&HAL_PPDU_RX_CNT)
cfg.u.ppdu.bmp_append_info |= MAC_AX_PPDU_RX_CNT;
if (filter&HAL_PPDU_HAS_A1M)
cfg.u.ppdu.bmp_filter |= MAC_AX_PPDU_HAS_A1M;
if (filter&HAL_PPDU_HAS_CRC_OK)
cfg.u.ppdu.bmp_filter |= MAC_AX_PPDU_HAS_CRC_OK;
cfg.u.ppdu.dup2fw_en = false;
cfg.u.ppdu.dup2fw_len = 0;
}
if (mac->ops->cfg_phy_rpt(mac, &cfg) != MACSUCCESS) {
PHL_ERR("%s fault\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_config_hw_mgnt_sec(struct hal_info_t *hal_info, u8 en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *hal_mac_ops = mac->ops;
hal_mac_ops->sta_hw_security_support(mac, SEC_UC_MGNT_ENC, en);
hal_mac_ops->sta_hw_security_support(mac, SEC_BMC_MGNT_ENC, en);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_get_append_fcs(struct hal_info_t *hal_info, u8 *val)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
if (ops->get_hw_value(mac, MAC_AX_HW_GET_APP_FCS, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
else
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_get_acpt_icv_err(struct hal_info_t *hal_info, u8 *val)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
if (ops->get_hw_value(mac, MAC_AX_HW_GET_RX_ICVERR, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
else
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status
rtw_hal_mac_chan_info_cfg(struct hal_info_t *hal_info,
bool chinfo_en, u8 macid,
u8 mode, u8 filter, u8 sg_size)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_phy_rpt_cfg cfg = {0};
cfg.en = chinfo_en;
cfg.type = MAC_AX_CH_INFO;
/*cfg.dest = MAC_AX_PRPT_DEST_HOST;*/
cfg.u.chif.macid = macid;
if (chinfo_en) {
/*ToDo - mode*/
cfg.u.chif.trigger = MAC_AX_CH_INFO_MACID;
/*ToDo - filter*/
cfg.u.chif.bmp_filter = MAC_AX_CH_INFO_DATA_FRM;
cfg.u.chif.dis_to = 0;
/*ToDo - sg_size*/
cfg.u.chif.seg_size = MAC_AX_CH_IFNO_SEG_512;
}
if (mac->ops->cfg_phy_rpt(mac, &cfg) != MACSUCCESS) {
PHL_ERR("%s fault\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
#endif /* CONFIG_PHL_CHANNEL_INFO */
void rtw_hal_mac_dbg_status_dump(struct hal_info_t *hal, struct hal_mac_dbg_dump_cfg *cfg)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_dbgpkg pkg = {0};
struct mac_ax_dbgpkg_en pkg_en = {0};
pkg.ss_dbg_0 = cfg->ss_dbg_0;
pkg.ss_dbg_1 = cfg->ss_dbg_1;
pkg_en.ss_dbg = cfg->ss_dbg;
pkg_en.dle_dbg = cfg->dle_dbg;
pkg_en.dmac_dbg = cfg->dmac_dbg;
pkg_en.cmac_dbg = cfg->cmac_dbg;
pkg_en.mac_dbg_port = cfg->mac_dbg_port;
pkg_en.plersvd_dbg = cfg->plersvd_dbg;
pkg_en.tx_flow_dbg = cfg->tx_flow_dbg;
PHL_INFO("%s: ss_dbg_0 %d, ss_dbg_1 %d, ss_dbg %d\n", __func__, pkg.ss_dbg_0, pkg.ss_dbg_1, pkg_en.ss_dbg);
PHL_INFO("%s: dle_dbg %d, dmac_dbg %d, cmac_dbg %d\n", __func__, pkg_en.dle_dbg, pkg_en.dmac_dbg, pkg_en.cmac_dbg);
PHL_INFO("%s: mac_dbg_port %d, plersvd_dbg %d, tx_flow_dbg %d\n", __func__, pkg_en.mac_dbg_port, pkg_en.plersvd_dbg, pkg_en.tx_flow_dbg);
mac->ops->dbg_status_dump(mac, &pkg, &pkg_en);
}
#ifdef CONFIG_PHL_DFS
enum rtw_hal_status
rtw_hal_mac_dfs_rpt_cfg(struct hal_info_t *hal_info,
bool rpt_en, u8 rpt_num, u8 rpt_to)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_phy_rpt_cfg cfg = {0};
cfg.en = rpt_en;
cfg.type = MAC_AX_DFS;
/*cfg.dest = MAC_AX_PRPT_DEST_HOST;*/
if (rpt_en) {
cfg.u.dfs.num_th = rpt_num;
cfg.u.dfs.en_timeout = rpt_to;
}
if (mac->ops->cfg_phy_rpt(mac, &cfg) != MACSUCCESS) {
PHL_ERR("%s fault\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_parse_dfs(struct hal_info_t *hal_info,
u8 *buf, u32 buf_len, struct mac_ax_dfs_rpt *dfs_rpt)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
if (mac->ops->parse_dfs(mac, buf, buf_len, dfs_rpt) != MACSUCCESS) {
PHL_ERR("%s fault\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
#endif /*CONFIG_PHL_DFS*/
enum rtw_hal_status
_hal_mac_get_pkt_ofld(struct hal_info_t *hal_info, u8 *id)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u8 *pkt_buf = NULL;
u16 pkt_len;
if(mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
if (mac->ops->pkt_ofld_packet(mac, &pkt_buf, &pkt_len, id) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
debug_dump_data((u8 *)pkt_buf, pkt_len, "pkt ofld");
_os_mem_free(hal_com->drv_priv, pkt_buf, pkt_len);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
_hal_mac_chk_pkt_ofld(struct hal_info_t *hal_info)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
void *d = hal_to_drvpriv(hal_info);
u16 loop_cnt = 0;
if(mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
do
{
if (mac->ops->check_fwofld_done(mac, 1) == MACSUCCESS)
break;
_os_sleep_ms(d, POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if ( loop_cnt < POLLING_HALMAC_CNT) {
PHL_PRINT("%s, check count = %d.\n", __func__, loop_cnt);
return RTW_HAL_STATUS_SUCCESS;
} else {
PHL_ERR("%s, polling timeout!!!\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
}
enum rtw_hal_status
_hal_mac_add_pkt_ofld(struct hal_info_t *hal_info, u8 *pkt, u16 len, u8 *id)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 status;
if(mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
PHL_PRINT("%s: len %d.\n", __func__, len);
status = mac->ops->add_pkt_ofld(mac, pkt, len, id);
if (status != MACSUCCESS) {
PHL_ERR("%s fault, status = %d.\n", __func__, status);
return RTW_HAL_STATUS_FAILURE;
}
PHL_PRINT("%s: id %d.\n", __func__, *id);
status = _hal_mac_chk_pkt_ofld(hal_info);
return status;
}
enum rtw_hal_status
_hal_mac_del_pkt_ofld(struct hal_info_t *hal_info, u8 *id)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 status;
if(mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
PHL_PRINT("%s: id %d.\n", __func__, *id);
status = mac->ops->del_pkt_ofld(mac, *id);
if (status != MACSUCCESS) {
PHL_ERR("%s fault, status = %d.\n", __func__, status);
return RTW_HAL_STATUS_FAILURE;
}
status = _hal_mac_chk_pkt_ofld(hal_info);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
_hal_mac_read_pkt_ofld(struct hal_info_t *hal_info, u8 *id)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 status;
if(mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
PHL_PRINT("%s: id %d.\n", __func__, *id);
status = mac->ops->read_pkt_ofld(mac, *id);
if (status != MACSUCCESS) {
PHL_ERR("%s fault, status = %d.\n", __func__, status);
return RTW_HAL_STATUS_FAILURE;
}
status = _hal_mac_chk_pkt_ofld(hal_info);
if (status != MACSUCCESS) {
return RTW_HAL_STATUS_FAILURE;
}
status = _hal_mac_get_pkt_ofld(hal_info, id);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_pkt_ofld(struct hal_info_t *hal, u8 *id, u8 op,
u8 *pkt, u16 *len)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
switch(op) {
case PKT_OFLD_ADD:
status = _hal_mac_add_pkt_ofld(hal, pkt, *len, id);
break;
case PKT_OFLD_DEL:
status = _hal_mac_del_pkt_ofld(hal, id);
break;
case PKT_OFLD_READ:
status = _hal_mac_read_pkt_ofld(hal, id);
break;
default:
PHL_ERR("%s op(%d) not define.\n", __func__, op);
break;
}
return status;
}
enum rtw_hal_status rtw_hal_mac_pkt_update_ids(struct hal_info_t *hal,
struct pkt_ofld_entry *entry)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal->mac;
struct mac_ax_general_pkt_ids mac_ids = {0};
u32 status;
mac_ids.macid = (u8)entry->macid;
mac_ids.probersp = entry->pkt_info[PKT_TYPE_PROBE_RSP].id;
mac_ids.pspoll = entry->pkt_info[PKT_TYPE_PS_POLL].id;
mac_ids.nulldata = entry->pkt_info[PKT_TYPE_NULL_DATA].id;
mac_ids.qosnull = entry->pkt_info[PKT_TYPE_QOS_NULL].id;
mac_ids.cts2self = entry->pkt_info[PKT_TYPE_CTS2SELF].id;
PHL_PRINT("macid %d, probersp %d, pspoll %d, nulldata %d, qosnull %d, cts2self %d.\n",
mac_ids.macid,
mac_ids.probersp,
mac_ids.pspoll,
mac_ids.nulldata,
mac_ids.qosnull,
mac_ids.cts2self);
status = mac->ops->general_pkt_ids(mac, &mac_ids);
if (status != MACSUCCESS) {
PHL_ERR("%s fault, status = %d.\n", __func__, status);
return RTW_HAL_STATUS_FAILURE;
}
return status;
}
enum rtw_hal_status
rtw_hal_mac_reset_pkt_ofld_state(struct hal_info_t *hal_info)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
if (mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
if (mac->ops->reset_fwofld_state(mac, 1) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
else
return RTW_HAL_STATUS_SUCCESS;
}
/* comment temporary and review it later */
#if 0
u4Byte hal_mac_ax_dbg_h2cpkt_lb(RT_HAL_MAC_INFO *hm_info, u32 size)
{
PADAPTER adapter = hm_info->adapter;
u32 ret = 0;
u8 *h2cbuf = NULL;
FunctionIn(COMP_HAL_MAC_API);
//ret = hm_info->halmac_ax_ops->fwcmd_lb(hm_info->halmac_ax_apter,
// 100, 0);
PlatformAllocateMemory(adapter, (PVOID *)&h2cbuf, size);
PlatformZeroMemory(h2cbuf,size);
for (u4Byte tmpc = 0; tmpc < size - 32; tmpc++) {
h2cbuf[32 + tmpc] = (u8)tmpc & 0xFF;
}
hal_mac_ax_send_h2c_pkt(adapter, h2cbuf, size);
PlatformFreeMemory(h2cbuf, size);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_update_table_dl_swru(RT_HAL_MAC_INFO *hm_info,
struct ofdma_dl_group *dl_group)
{
PADAPTER adapter = hm_info->adapter;
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->upd_dlru_grptbl(
hm_info->halmac_ax_apter,
&dl_group->dl_grp_table);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_update_table_dl_swfix(RT_HAL_MAC_INFO *hm_info,
struct ofdma_dl_group *dl_group)
{
PADAPTER adapter = hm_info->adapter;
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->upd_dlru_fixtbl(
hm_info->halmac_ax_apter,
&dl_group->fixed_mode_group);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_update_table_ul_rufix(RT_HAL_MAC_INFO *hm_info,
struct ofdma_ul_group *ul_group)
{
PADAPTER adapter = hm_info->adapter;
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->upd_ulru_fixtbl(
hm_info->halmac_ax_apter,
&ul_group->fixed_mode_group);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_update_table_ul_ru_table(RT_HAL_MAC_INFO *hm_info,
struct ofdma_ul_group *ul_group)
{
PADAPTER adapter = hm_info->adapter;
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->upd_ulru_grptbl(
hm_info->halmac_ax_apter,
&ul_group->ul_grp_table);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_update_table_ul_drvfix(RT_HAL_MAC_INFO *hm_info,
struct ofdma_ul_group *ul_group)
{
PADAPTER adapter = hm_info->adapter;
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->upd_ul_fixinfo(
hm_info->halmac_ax_apter,
&ul_group->drv_fixed_info);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_issue_bsrp(RT_HAL_MAC_INFO *hm_info,
struct ofdma_ul_group *ul_group)
{
PADAPTER adapter = hm_info->adapter;
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->upd_ul_fixinfo(
hm_info->halmac_ax_apter,
&ul_group->drv_fixed_info
);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_update_ru_sta(RT_HAL_MAC_INFO *hm_info,
u8 *ru_sta_info)
{
/* upd_rusta_info */
struct mac_ax_bb_stainfo *bb_stainfo = (struct mac_ax_bb_stainfo *)ru_sta_info;
hm_info->halmac_ax_ops->upd_rusta_info(
hm_info->halmac_ax_apter,
bb_stainfo
);
return 0;
}
u4Byte hal_mac_ax_update_ba_info_table(RT_HAL_MAC_INFO *hm_info,
u8 ba_info)
{
/* upd_ba_infotbl */
struct mac_ax_ba_infotbl *ba_info_tbl = (struct mac_ax_ba_infotbl *)ba_info;
hm_info->halmac_ax_ops->upd_ba_infotbl(
hm_info->halmac_ax_apter,
ba_info_tbl
);
return 0;
}
u4Byte hal_mac_ax_Test_H2C(RT_HAL_MAC_INFO *hm_info,
u32 length, u8 Burst)
{
u32 ret =0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->fwcmd_lb(
hm_info->halmac_ax_apter,
length,
Burst
);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
u4Byte hal_mac_ax_compare_h2c_c2h(RT_HAL_MAC_INFO *hm_info,
u8 *buf, u32 len)
{
u32 ret=0;
FunctionIn(COMP_HAL_MAC_API);
ret = hm_info->halmac_ax_ops->process_c2h(
hm_info->halmac_ax_apter,
buf,
len
);
FunctionOut(COMP_HAL_MAC_API);
return ret;
}
#endif
//====================================================================
/*
* halmac wrapper API for hal and proto type is at hal_api_mac.h
* Efuse part.
*/
enum rtw_hal_status
rtw_hal_mac_get_log_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val,
bool is_limited)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if(is_limited == true) {
if(mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_LIMIT_LOG_EFUSE_SIZE, val) != MACSUCCESS){
PHL_ERR("%s: Get limited logical efuse size fail!\n",
__FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
}
else {
if(mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_LOGICAL_EFUSE_SIZE, val) != MACSUCCESS){
PHL_ERR("%s: Get logical efuse size fail!\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
}
PHL_INFO("%s: Logical efuse size = %d!\n", __FUNCTION__, *val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_read_log_efuse_map(struct rtw_hal_com_t *hal_com, u8 *map,
bool is_limited)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->dump_log_efuse(mac,
MAC_AX_EFUSE_PARSER_MAP,
#ifdef RTW_WKARD_EFUSE_OPERATION
MAC_AX_EFUSE_R_DRV,
#else
MAC_AX_EFUSE_R_AUTO,
#endif
map,
is_limited
) != MACSUCCESS) {
PHL_INFO("%s: Dump logical efuse fail!\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s: Dump logical efuse ok!\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
/*
* HALMAC PG EFUSE API put version length at the tail of map/mask buffer
*/
enum rtw_hal_status
rtw_hal_mac_write_log_efuse_map(struct rtw_hal_com_t *hal_com,
u8 *map,
u32 map_size,
u8 *mask,
u32 mask_size,
u8 *map_version,
u8 *mask_version,
u8 version_length,
u8 part,
bool is_limited)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_pg_efuse_info info;
enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
u8 *tmp_map = NULL;
u8 *tmp_mask = NULL;
tmp_map = _os_mem_alloc(hal_com->drv_priv, (map_size + version_length));
if(tmp_map == NULL) {
PHL_WARN("%s: Allocate pg map buffer fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_RESOURCE;
goto err_mem_tmp_map;
}
tmp_mask = _os_mem_alloc(hal_com->drv_priv, (mask_size + version_length));
if(tmp_mask == NULL) {
PHL_WARN("%s: Allocate pg mask buffer fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_RESOURCE;
goto err_mem_tmp_mask;
}
/* Copy efuse map and map version to tmp_map buffer */
_os_mem_cpy(hal_com->drv_priv, tmp_map, map, map_size);
_os_mem_cpy(hal_com->drv_priv, tmp_map+map_size, map_version,
version_length);
/* Copy efuse mask and mask version to tmp_mask buffer */
_os_mem_cpy(hal_com->drv_priv, tmp_mask, mask, mask_size);
_os_mem_cpy(hal_com->drv_priv, tmp_mask+mask_size, mask_version,
version_length);
#if 0 /* For debug usage */
debug_dump_data(map, (u16)map_size, "logical map:");
debug_dump_data(map_version, version_length, "logical map version:");
debug_dump_data(mask, (u16)mask_size, "mask:");
debug_dump_data(mask_version, version_length, "mask version:");
debug_dump_data(tmp_map, (u16)(map_size + version_length), "tmp_map:");
debug_dump_data(tmp_mask, (u16)(mask_size + version_length), "tmp_mask:");
#endif
info.efuse_map = tmp_map;
info.efuse_map_size = map_size;
info.efuse_mask = tmp_mask;
info.efuse_mask_size= mask_size;
if (mac->ops->pg_efuse_by_map(mac,
&info,
MAC_AX_EFUSE_R_DRV,
part,
is_limited) != MACSUCCESS) {
PHL_INFO("%s: PG Fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
}
else {
PHL_INFO("%s: PG ok!\n", __FUNCTION__);
status = RTW_HAL_STATUS_SUCCESS;
}
_os_mem_free(hal_com->drv_priv, tmp_map, (map_size + version_length));
_os_mem_free(hal_com->drv_priv, tmp_mask, (mask_size + version_length));
return status;
err_mem_tmp_mask:
_os_mem_free(hal_com->drv_priv, tmp_map, (map_size + version_length));
err_mem_tmp_map:
return status;
}
enum rtw_hal_status
rtw_hal_mac_read_hidden_rpt(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_defeature_value rpt;
u32 err;
err = mac->ops->read_hidden_rpt(mac, &rpt);
if (err != MACSUCCESS) {
PHL_TRACE(COMP_PHL_TRIG, _PHL_INFO_, "err=0x%x\n", err);
return RTW_HAL_STATUS_FAILURE;
}
if (rpt.tx_spatial_stream != 7 && rpt.tx_spatial_stream > 0) {
hal_com->phy_hw_cap[0].tx_num = rpt.tx_spatial_stream;
hal_com->phy_hw_cap[1].tx_num = rpt.tx_spatial_stream;
hal_com->rfpath_tx_num = rpt.tx_spatial_stream;
}
if (rpt.rx_spatial_stream != 7 && rpt.rx_spatial_stream > 0) {
hal_com->phy_hw_cap[0].rx_num = rpt.rx_spatial_stream;
hal_com->phy_hw_cap[1].rx_num = rpt.rx_spatial_stream;
hal_com->rfpath_rx_num = rpt.rx_spatial_stream;
}
if (rpt.hw_special_type > EFUSE_HW_STYPE_NONE &&
rpt.hw_special_type < EFUSE_HW_STYPE_GENERAL)
hal_com->dev_hw_cap.hw_stype_cap = rpt.hw_special_type;
if (rpt.wl_func_support > EFUSE_WL_FUNC_NONE &&
rpt.wl_func_support < EFUSE_WL_FUNC_GENERAL)
hal_com->dev_hw_cap.wl_func_cap = rpt.wl_func_support;
PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden tx=%d hidden rx=%d\n",
rpt.tx_spatial_stream, rpt.rx_spatial_stream);
PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden bw=%d\n", rpt.bandwidth);
PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden protocol = %d\n",
rpt.protocol_80211);
PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden nic=%d\n", rpt.NIC_router);
PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden hw special type=%d\n",
rpt.hw_special_type);
PHL_TRACE(COMP_PHL_MAC, _PHL_INFO_, "hidden wl func=%d\n",
rpt.wl_func_support);
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_check_efuse_autoload(struct rtw_hal_com_t *hal_com, u8 *autoload)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->check_efuse_autoload(mac, autoload) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
if(*autoload == true)
PHL_INFO("%s: efuse auto load SUCCESS!\n", __FUNCTION__);
else
PHL_INFO("%s: efuse auto load FAIL!\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_avl(struct rtw_hal_com_t *hal_com, u32 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->get_efuse_avl_size(mac, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_EFUSE_SIZE, val) != MACSUCCESS){
PHL_ERR("%s: Get efuse size fail!\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s: Efuse size = %d!\n", __FUNCTION__, *val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_mask_size(struct rtw_hal_com_t *hal_com, u32 *val,
bool is_limited)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if(is_limited == true) {
if(mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_LIMIT_EFUSE_MASK_SIZE, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
}
else {
if(mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_EFUSE_MASK_SIZE, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s: efuse mask size = %d\n", __FUNCTION__, *val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
PHL_INFO("%s\n", __FUNCTION__);
if (mac->ops->get_efuse_info(mac, efuse_map, info_type, value, size,
&map_valid) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_read_phy_efuse(struct rtw_hal_com_t *hal_com,
u32 addr, u32 size, u8 *value)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
PHL_INFO("%s\n", __FUNCTION__);
if (mac->ops->read_efuse(mac, addr, size, value,
MAC_AX_EFUSE_BANK_WIFI) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_read_bt_phy_efuse(struct rtw_hal_com_t *hal_com,
u32 addr, u32 size, u8 *value)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
PHL_INFO("%s\n", __FUNCTION__);
if (mac->ops->read_efuse(mac, addr, size, value,
MAC_AX_EFUSE_BANK_BT) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_mac_write_msk_pwr_reg(
struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 mask, u32 val)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
u32 result = 0;
result = ops->write_msk_pwr_reg(mac, band, offset, mask, val);
if (result != MACSUCCESS)
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_,
"Write power register failure, status = %d\n", result);
return result;
}
u32 rtw_hal_mac_set_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 val){
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
u32 result = 0;
result = ops->write_pwr_reg(mac, band, offset, val);
if (result != MACSUCCESS)
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set power register failure, status = %d\n", result);
return result;
}
u32 rtw_hal_mac_get_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 *val){
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
u32 result = 0;
result = ops->read_pwr_reg(mac, band, offset, val);
if (result != MACSUCCESS)
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Get power register failure, status = %d\n", result);
return result;
}
enum rtw_hal_status
rtw_hal_mac_get_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 *value){
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
ret = ops->read_xcap_reg(mac, sc_xo, value);
if (ret != MACSUCCESS)
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Get xacp failure, status = %d\n", ret);
return ret;
}
enum rtw_hal_status
rtw_hal_mac_set_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 value){
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
ret = ops->write_xcap_reg(mac, sc_xo, value);
if (ret != MACSUCCESS)
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set xacp failure, status = %d\n", ret);
return ret;
}
enum rtw_hal_status
rtw_hal_mac_get_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8* val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
/* Because mac si function is not support mac ops*/
/* we call mac si function temporarily until mac team feedback.*/
if (mac_read_xtal_si(mac, offset, val) != MACSUCCESS) {
PHL_INFO("Get xsi failure, status = %s\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_set_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
/* Because mac si function is not support mac ops*/
/* we call mac si function temporarily until mac team feedback.*/
if (mac_write_xtal_si(mac, offset, val, 0xff) != MACSUCCESS) {
PHL_INFO("Set xsi failure, status = %s\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_fw_dbg_dump(struct hal_info_t *hal_info, u8 is_low_power)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u8 *buffer = NULL;
u16 bufSize = FW_PLE_SIZE;
struct mac_ax_fwdbg_en en;
u32 mac_err = 0;
en.status_dbg = 1;
en.ps_dbg = 1;
en.rsv_ple_dbg = 0;
mac_err = mac->ops->fw_dbg_dump(mac, &buffer, &en);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
if (en.rsv_ple_dbg && buffer) {
/*fw buffer is 2048, but Windows DbgPrint only 512 Bytes, so we split buffer to 4 segments*/
if (buffer != NULL) {
PHL_PRINT("=======================\n");
PHL_PRINT("Start to dump fw rsvd ple:\n\n");
_hal_fw_dbg_dump(hal_info, buffer, bufSize);
PHL_PRINT("\n=======================\n");
}
}
if (buffer != NULL)
_os_mem_free(hal_info->hal_com->drv_priv, buffer, bufSize);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_req_pwr_state(struct hal_info_t *hal_info, u8 pwr_state)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if(mac->ops->lps_pwr_state(mac, MAC_AX_PWR_STATE_ACT_REQ, pwr_state)
== MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_chk_pwr_state(struct hal_info_t *hal_info, u8 pwr_state, u32 *mac_sts)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
*mac_sts = mac->ops->lps_pwr_state(mac, MAC_AX_PWR_STATE_ACT_CHK, pwr_state);
if(*mac_sts == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_lps_cfg(struct hal_info_t *hal_info,
struct rtw_hal_lps_info *lps_info)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum mac_ax_ps_mode ax_ps_mode;
struct mac_ax_lps_info ax_lps_info;
if (lps_info->lps_en) {
ax_ps_mode = MAC_AX_PS_MODE_LEGACY;
} else {
ax_ps_mode = MAC_AX_PS_MODE_ACTIVE;
}
ax_lps_info.listen_bcn_mode = lps_info->listen_bcn_mode;
ax_lps_info.awake_interval = lps_info->awake_interval;
ax_lps_info.smart_ps_mode = lps_info->smart_ps_mode;
if (mac->ops->cfg_lps(mac, (u8)lps_info->macid, ax_ps_mode,
&ax_lps_info) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_lps_chk_leave(struct hal_info_t *hal_info, u16 macid, u32 *mac_sts)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
*mac_sts = mac->ops->chk_leave_lps(mac, (u8)macid);
if(*mac_sts == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_lps_chk_access(struct hal_info_t *hal_info, u32 offset)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if(mac->ops->io_chk_access(mac, offset) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_mac_get_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx, u8 type_idx, u32 *ret_value){
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_rx_cnt rx_cnt;
u16 rx_cnt_buff[MAC_AX_RX_PPDU_MAX];
u32 rx_cnt_total=0;
u16 ppdu_idx;
rx_cnt.type = type_idx;
rx_cnt.op = MAC_AX_RXCNT_R;
rx_cnt.buf = rx_cnt_buff;
rx_cnt.band = cur_phy_idx;
ret = ops->rx_cnt(mac, &rx_cnt);
for(ppdu_idx=0;ppdu_idx<MAC_AX_RX_PPDU_MAX;ppdu_idx++)
{
rx_cnt_total+=rx_cnt_buff[ppdu_idx];
}
*ret_value = rx_cnt_total;
if (ret != MACSUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "mac get rx counter fail, status=%d\n",ret);
}
return ret;
}
enum rtw_hal_status
rtw_hal_mac_set_reset_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_rx_cnt rx_cnt;
u16 rx_cnt_buff[MAC_AX_RX_PPDU_MAX];
rx_cnt.type = MAC_AX_RX_IDX;
rx_cnt.op = MAC_AX_RXCNT_RST_ALL;
rx_cnt.buf = rx_cnt_buff;
rx_cnt.band = cur_phy_idx;
ret = ops->rx_cnt(mac, &rx_cnt);
if (ret != MACSUCCESS){
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "mac reset rx cnt fail, status=%d\n",ret);
}
return ret;
}
enum rtw_hal_status
rtw_hal_mac_tx_idle_poll(struct rtw_hal_com_t *hal_com, u8 band_idx)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_tx_idle_poll_cfg cfg = {0};
u32 err = 0;
cfg.sel = MAC_AX_TX_IDLE_POLL_SEL_BAND;
cfg.band = band_idx;
err = mac->ops->tx_idle_poll(mac, &cfg);
if (err != MACSUCCESS) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_,
"Polling tx idle failure(%d)!\n", err);
return RTW_HAL_STATUS_TIMEOUT;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_sch_txen_cfg {
RTW_TXEN_BE0 = 1 << 0,
RTW_TXEN_BK0 = 1 << 1,
RTW_TXEN_VI0 = 1 << 2,
RTW_TXEN_VO0 = 1 << 3,
RTW_TXEN_BE1 = 1 << 4,
RTW_TXEN_BK1 = 1 << 5,
RTW_TXEN_VI1 = 1 << 6,
RTW_TXEN_VO1 = 1 << 7,
RTW_TXEN_MG0 = 1 << 8,
RTW_TXEN_MG1 = 1 << 9,
RTW_TXEN_MG2 = 1 << 10,
RTW_TXEN_HI = 1 << 11,
RTW_TXEN_BCN = 1 << 12,
RTW_TXEN_UL = 1 << 13,
RTW_TXEN_TWT0 = 1 << 14,
RTW_TXEN_TWT1 = 1 << 15,
RTW_TXEN_DRV_MASK = 0x19FF,
RTW_TXEN_ALL = 0xFFFF,
};
enum rtw_hal_status
rtw_hal_mac_set_sch_tx_en(struct rtw_hal_com_t *hal_com, u8 band_idx,
u16 tx_en, u16 tx_en_mask)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_sch_tx_en_cfg cfg;
enum rtw_hal_status ret;
u32 result = 0;
ret = RTW_HAL_STATUS_SUCCESS;
cfg.band = band_idx;
cfg.tx_en.be0 = ((tx_en & RTW_TXEN_BE0) ? 1 : 0);
cfg.tx_en.bk0 = ((tx_en & RTW_TXEN_BK0) ? 1 : 0);
cfg.tx_en.vi0 = ((tx_en & RTW_TXEN_VI0) ? 1 : 0);
cfg.tx_en.vo0 = ((tx_en & RTW_TXEN_VO0) ? 1 : 0);
cfg.tx_en.be1 = ((tx_en & RTW_TXEN_BE1) ? 1 : 0);
cfg.tx_en.bk1 = ((tx_en & RTW_TXEN_BK1) ? 1 : 0);
cfg.tx_en.vi1 = ((tx_en & RTW_TXEN_VI1) ? 1 : 0);
cfg.tx_en.vo1 = ((tx_en & RTW_TXEN_VO1) ? 1 : 0);
cfg.tx_en.mg0 = ((tx_en & RTW_TXEN_MG0) ? 1 : 0);
cfg.tx_en.mg1 = ((tx_en & RTW_TXEN_MG1) ? 1 : 0);
cfg.tx_en.mg2 = ((tx_en & RTW_TXEN_MG2) ? 1 : 0);
cfg.tx_en.hi = ((tx_en & RTW_TXEN_HI) ? 1 : 0);
cfg.tx_en.bcn = ((tx_en & RTW_TXEN_BCN) ? 1 : 0);
cfg.tx_en.ul = ((tx_en & RTW_TXEN_UL) ? 1 : 0);
cfg.tx_en.twt0 = ((tx_en & RTW_TXEN_TWT0) ? 1 : 0);
cfg.tx_en.twt1 = ((tx_en & RTW_TXEN_TWT1) ? 1 : 0);
cfg.tx_en_mask.be0 = ((tx_en_mask & RTW_TXEN_BE0) ? 1 : 0);
cfg.tx_en_mask.bk0 = ((tx_en_mask & RTW_TXEN_BK0) ? 1 : 0);
cfg.tx_en_mask.vi0 = ((tx_en_mask & RTW_TXEN_VI0) ? 1 : 0);
cfg.tx_en_mask.vo0 = ((tx_en_mask & RTW_TXEN_VO0) ? 1 : 0);
cfg.tx_en_mask.be1 = ((tx_en_mask & RTW_TXEN_BE1) ? 1 : 0);
cfg.tx_en_mask.bk1 = ((tx_en_mask & RTW_TXEN_BK1) ? 1 : 0);
cfg.tx_en_mask.vi1 = ((tx_en_mask & RTW_TXEN_VI1) ? 1 : 0);
cfg.tx_en_mask.vo1 = ((tx_en_mask & RTW_TXEN_VO1) ? 1 : 0);
cfg.tx_en_mask.mg0 = ((tx_en_mask & RTW_TXEN_MG0) ? 1 : 0);
cfg.tx_en_mask.mg1 = ((tx_en_mask & RTW_TXEN_MG1) ? 1 : 0);
cfg.tx_en_mask.mg2 = ((tx_en_mask & RTW_TXEN_MG2) ? 1 : 0);
cfg.tx_en_mask.hi = ((tx_en_mask & RTW_TXEN_HI) ? 1 : 0);
cfg.tx_en_mask.bcn = ((tx_en_mask & RTW_TXEN_BCN) ? 1 : 0);
cfg.tx_en_mask.ul = ((tx_en_mask & RTW_TXEN_UL) ? 1 : 0);
cfg.tx_en_mask.twt0 = ((tx_en_mask & RTW_TXEN_TWT0) ? 1 : 0);
cfg.tx_en_mask.twt1 = ((tx_en_mask & RTW_TXEN_TWT1) ? 1 : 0);
result = ops->set_hw_value(mac, MAC_AX_HW_SET_SCH_TXEN_CFG, &cfg);
if (result != MACSUCCESS) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set Tx pause failure, status = %d\n", result);
ret = RTW_HAL_STATUS_FAILURE;
}
return ret;
}
enum rtw_hal_status
rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com,
u8 band_idx, bool tx_pause, enum tx_pause_rson rson)
{
u16 *tx_off;
enum tx_pause_rson i;
u16 tx_cfg = 0;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
tx_off = &hal_com->band[band_idx].tx_pause[rson];
if (tx_pause == true) {
switch (rson) {
case PAUSE_RSON_NOR_SCAN:
*tx_off = (u16)~RTW_TXEN_MG0;
break;
case PAUSE_RSON_RFK:
case PAUSE_RSON_PSD:
case PAUSE_RSON_DFS:
case PAUSE_RSON_DBCC:
case PAUSE_RSON_RESET:
*tx_off = (u16)RTW_TXEN_ALL;
break;
default:
PHL_ERR("Unknow pause reason:%d\n", rson);
goto _error;
}
} else {
*tx_off = 0;
}
tx_off = hal_com->band[band_idx].tx_pause;
for (i = 0; (i < PAUSE_RSON_MAX) && (tx_cfg != RTW_TXEN_ALL); i++)
if (tx_off[i])
tx_cfg |= tx_off[i];
/* tx_cfg is white list, but tx_pause of struct rtw_hw_band is black list */
tx_cfg = ~tx_cfg;
PHL_INFO("TX %sPause - Reason(%d) for band-%u, final tx_cfg(0x%04x)\n",
tx_pause?"":"Un-", rson, band_idx, tx_cfg);
hstatus = rtw_hal_mac_set_sch_tx_en(hal_com, band_idx,
tx_cfg, RTW_TXEN_ALL);
if (hstatus != RTW_HAL_STATUS_SUCCESS)
goto _error;
if ((rson == PAUSE_RSON_RFK) && tx_pause) {
hstatus = rtw_hal_mac_tx_idle_poll(hal_com, band_idx);
if (hstatus != RTW_HAL_STATUS_SUCCESS)
goto _error;
}
_error:
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_set_macid_pause(struct rtw_hal_com_t *hal_com,
u16 macid, bool pause)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_macid_pause_cfg cfg = {0};
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
cfg.macid = (u8)macid;
cfg.pause = pause;
PHL_INFO("%s macid:%d(%s) \n", __func__, macid, pause ? "pause":"unpause");
/*TODO - MAC_AX_HW_SET_MULTI_ID_PAUSE*/
if (ops->set_hw_value(mac, MAC_AX_HW_SET_ID_PAUSE, &cfg) != MACSUCCESS) {
PHL_ERR("%s failed\n", __func__);
hstatus = RTW_HAL_STATUS_FAILURE;
}
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_set_macid_grp_pause(struct rtw_hal_com_t *hal_com,
u32 *macid_arr, u8 macid_arr_sz, bool pause)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *ops = mac->ops;
struct mac_ax_macid_pause_grp cfg = {0};
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
u8 pause_grp_sz = 0, mac_grp_sz = 0, arr_idx = 0, bit_idx = 0;
u32 mac_ret = MACSUCCESS;
/* size check */
mac_grp_sz = sizeof(cfg.pause_grp) / sizeof(cfg.pause_grp[0]);
pause_grp_sz = MIN(mac_grp_sz, macid_arr_sz);
for (arr_idx = 0; arr_idx < pause_grp_sz; arr_idx++) {
for (bit_idx = 0; bit_idx < 32; bit_idx++) {
if (macid_arr[arr_idx] & BIT(bit_idx)) {
cfg.mask_grp[arr_idx] |= BIT(bit_idx);
if (pause)
cfg.pause_grp[arr_idx] |= BIT(bit_idx);
else
cfg.pause_grp[arr_idx] &= ~BIT(bit_idx);
}
}
}
PHL_INFO("%s cfg pause_grp:0x%x,0x%x,0x%x,0x%x, mask_grp:0x%x,0x%x,0x%x,0x%x(%s)\n", __func__,
cfg.pause_grp[0], cfg.pause_grp[1], cfg.pause_grp[2], cfg.pause_grp[3],
cfg.mask_grp[0], cfg.mask_grp[1], cfg.mask_grp[2], cfg.mask_grp[3],
pause ? "pause":"unpause");
mac_ret = ops->set_hw_value(mac, MAC_AX_HW_SET_MULTI_ID_PAUSE, &cfg);
if (mac_ret != MACSUCCESS) {
PHL_ERR("%s failed(mac ret:%d)\n", __func__, mac_ret);
hstatus = RTW_HAL_STATUS_FAILURE;
}
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_fw_log_cfg(struct rtw_hal_com_t *hal_com,
struct rtw_hal_fw_log_cfg *fl_cfg)
{
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_fw_log log_cfg = {0};
u32 status;
if(mac == NULL)
return RTW_HAL_STATUS_MAC_INIT_FAILURE;
log_cfg.level = fl_cfg->level;
log_cfg.output = fl_cfg->output;
log_cfg.comp = fl_cfg->comp;
log_cfg.comp_ext = fl_cfg->comp_ext;
PHL_PRINT("%s: level %d, output 0x%08x, comp 0x%08x, comp ext 0x%08x.\n",
__func__,
log_cfg.level,
log_cfg.output,
log_cfg.comp,
log_cfg.comp_ext);
if(log_cfg.output == MAC_AX_FL_LV_UART)
{
mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_TX_GPIO5);
mac->ops->sel_uart_tx_pin(mac, MAC_AX_UART_TX_GPIO5);
mac->ops->pinmux_set_func(mac, MAC_AX_GPIO_UART_RX_GPIO6);
mac->ops->sel_uart_rx_pin(mac, MAC_AX_UART_RX_GPIO6);
}
status = mac->ops->fw_log_cfg(mac, &log_cfg);
if (status != MACSUCCESS) {
PHL_ERR("%s fault, status = %d.\n", __func__, status);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
u32
rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 rpt = 0;
rpt = mac->ops->lamode_trigger(mac, trig);
return rpt;
}
enum rtw_hal_status
rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel,
u32 *addr_start, u32 *addr_end)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_la_buf_param param;
param.la_buf_sel = buf_sel;
mac->ops->lamode_buf_cfg(mac, ¶m);
*addr_start = param.start_addr;
*addr_end = param.end_addr;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en,
u8 restart_en, u8 timeout_en, u8 timeout_val,
u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_la_cfg cfg;
cfg.la_func_en = func_en;
cfg.la_restart_en = restart_en;
cfg.la_timeout_en = timeout_en;
cfg.la_timeout_val = timeout_val;
cfg.la_data_loss_imr = data_loss_imr;
cfg.la_tgr_tu_sel = la_tgr_tu_sel;
cfg.la_tgr_time_val = tgr_time_val;
mac->ops->lamode_cfg(mac, &cfg);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state,
u16 *la_finish_addr, bool *la_round_up,
bool *la_loss_data)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_la_status info;
info = mac->ops->get_lamode_st(mac);
*la_state = info.la_sw_fsmst;
*la_finish_addr = info.la_buf_wptr;
*la_round_up = info.la_buf_rndup_ind;
*la_loss_data = info.la_data_loss;
return RTW_HAL_STATUS_SUCCESS;
}
static inline void _hal_set_dft_rxfltr(struct mac_ax_rx_fltr_ctrl_t *ctrl,
struct mac_ax_rx_fltr_ctrl_t *mask)
{
/* filter packets by address */
ctrl->sniffer_mode = 0;
mask->sniffer_mode = 1;
/* check unicast */
ctrl->acpt_a1_match_pkt = 1;
mask->acpt_a1_match_pkt = 1;
ctrl->uc_pkt_chk_cam_match = 1;
mask->uc_pkt_chk_cam_match = 1;
/* check broadcast */
ctrl->acpt_bc_pkt = 1;
mask->acpt_bc_pkt = 1;
ctrl->bc_pkt_chk_cam_match = 1;
mask->bc_pkt_chk_cam_match = 1;
/* check multicast */
ctrl->acpt_mc_pkt = 1;
mask->acpt_mc_pkt = 1;
/* black list filter */
ctrl->mc_pkt_white_lst_mode = 0;
mask->mc_pkt_white_lst_mode = 1;
/* check beacon */
ctrl->bcn_chk_en = 1;
mask->bcn_chk_en = 1;
ctrl->bcn_chk_rule = 0; /* 2: A2&A3 match */
mask->bcn_chk_rule = 0x3;
/* misc */
ctrl->acpt_pwr_mngt_pkt = 1;
mask->acpt_pwr_mngt_pkt = 1;
ctrl->acpt_ftm_req_pkt = 1;
mask->acpt_ftm_req_pkt = 1;
}
/**
* rtw_hal_mac_set_rxfltr_by_mode - Set rx filter option by scenario
* @hal_com: pointer of struct rtw_hal_com_t
* @band: 0x0: band0, 0x1: band1
* @mode: scenario mode
*
* Set RX filter setting by scenario.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status
rtw_hal_mac_set_rxfltr_by_mode(struct rtw_hal_com_t *hal_com,
u8 band, enum rtw_rx_fltr_mode mode)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_rx_fltr_ctrl_t ctrl = {0};
struct mac_ax_rx_fltr_ctrl_t mask = {0};
u32 err;
switch (mode) {
case RX_FLTR_MODE_RESTORE:
break;
case RX_FLTR_MODE_SNIFFER:
ctrl.sniffer_mode = 1;
mask.sniffer_mode = 1;
break;
case RX_FLTR_MODE_SCAN:
ctrl.acpt_a1_match_pkt = 1;
mask.acpt_a1_match_pkt = 1;
ctrl.acpt_bc_pkt = 1;
mask.acpt_bc_pkt = 1;
ctrl.acpt_mc_pkt = 1;
mask.acpt_mc_pkt = 1;
ctrl.uc_pkt_chk_cam_match = 0;
mask.uc_pkt_chk_cam_match = 1;
ctrl.bc_pkt_chk_cam_match = 0;
mask.bc_pkt_chk_cam_match = 1;
/* Do NOT check B_AX_A_BCN_CHK_RULE
* when receiving beacon and probe_response
*/
ctrl.bcn_chk_en = 0;
mask.bcn_chk_en = 1;
break;
case RX_FLTR_MODE_STA_NORMAL:
#if 1
_hal_set_dft_rxfltr(&ctrl, &mask);
#else
/* filter packets by address */
ctrl.sniffer_mode = 0;
mask.sniffer_mode = 1;
/* check unicast */
ctrl.acpt_a1_match_pkt = 1;
mask.acpt_a1_match_pkt = 1;
ctrl.uc_pkt_chk_cam_match = 1;
mask.uc_pkt_chk_cam_match = 1;
/* check broadcast */
ctrl.acpt_bc_pkt = 1;
mask.acpt_bc_pkt = 1;
ctrl.bc_pkt_chk_cam_match = 1;
mask.bc_pkt_chk_cam_match = 1;
if ((hal_com->chip_id == CHIP_WIFI6_8852A)
&& (hal_com->cv == CAV)) {
/* don't check address cam for multicast, accept all */
ctrl.acpt_mc_pkt = 0;
mask.acpt_mc_pkt = 1;
} else {
/* check multicast */
ctrl.acpt_mc_pkt = 1;
mask.acpt_mc_pkt = 1;
/* black list filter */
ctrl.mc_pkt_white_lst_mode = 0;
mask.mc_pkt_white_lst_mode = 1;
}
/* check beacon */
ctrl.bcn_chk_en = 1;
mask.bcn_chk_en = 1;
ctrl.bcn_chk_rule = 2; /* 2: A2&A3 match */
mask.bcn_chk_rule = 0x3;
/* misc */
ctrl.acpt_pwr_mngt_pkt = 1;
mask.acpt_pwr_mngt_pkt = 1;
ctrl.acpt_ftm_req_pkt = 1;
mask.acpt_ftm_req_pkt = 1;
#endif
break;
case RX_FLTR_MODE_STA_LINKING:
#if 1
_hal_set_dft_rxfltr(&ctrl, &mask);
/* check broadcast */
ctrl.acpt_bc_pkt = 1;
mask.acpt_bc_pkt = 1;
ctrl.bc_pkt_chk_cam_match = 0;
mask.bc_pkt_chk_cam_match = 1;
/* check beacon */
ctrl.bcn_chk_en = 0;
mask.bcn_chk_en = 1;
#else
/* filter packets by address */
ctrl.sniffer_mode = 0;
mask.sniffer_mode = 1;
/* check unicast */
ctrl.acpt_a1_match_pkt = 1;
mask.acpt_a1_match_pkt = 1;
ctrl.uc_pkt_chk_cam_match = 1;
mask.uc_pkt_chk_cam_match = 1;
/* check broadcast */
ctrl.acpt_bc_pkt = 1;
mask.acpt_bc_pkt = 1;
ctrl.bc_pkt_chk_cam_match = 0;
mask.bc_pkt_chk_cam_match = 1;
if ((hal_com->chip_id == CHIP_WIFI6_8852A)
&& (hal_com->cv == CAV)) {
/* don't check address cam for multicast, accept all */
ctrl.acpt_mc_pkt = 0;
mask.acpt_mc_pkt = 1;
} else {
/* check multicast */
ctrl.acpt_mc_pkt = 1;
mask.acpt_mc_pkt = 1;
/* black list filter */
ctrl.mc_pkt_white_lst_mode = 0;
mask.mc_pkt_white_lst_mode = 1;
}
/* check beacon */
ctrl.bcn_chk_en = 0;
mask.bcn_chk_en = 1;
ctrl.bcn_chk_rule = 2; /* 2: A2&A3 match */
mask.bcn_chk_rule = 0x3;
/* misc */
ctrl.acpt_pwr_mngt_pkt = 1;
mask.acpt_pwr_mngt_pkt = 1;
ctrl.acpt_ftm_req_pkt = 1;
mask.acpt_ftm_req_pkt = 1;
#endif
break;
case RX_FLTR_MODE_AP_NORMAL:
#if 1
_hal_set_dft_rxfltr(&ctrl, &mask);
/* check unicast */
ctrl.acpt_a1_match_pkt = 1;
mask.acpt_a1_match_pkt = 1;
ctrl.uc_pkt_chk_cam_match = 0;
mask.uc_pkt_chk_cam_match = 1;
/* check broadcast (for probe req) */
ctrl.acpt_bc_pkt = 1;
mask.acpt_bc_pkt = 1;
ctrl.bc_pkt_chk_cam_match = 0;
mask.bc_pkt_chk_cam_match = 1;
#else
/*
* SNIFFER: OFF
* UC address CAM A1: ON
* UC addr CAM match: OFF
* BC accept: ON
* BC address CAM: OFF
* Beacon check: OFF
*/
/* filter packets by address */
ctrl.sniffer_mode = 0;
mask.sniffer_mode = 1;
/* Unicast
* Do not enable address CAM matching filtering but all A1
* matched ones. AP should accept all UC requests from
* unknown STAs.
*/
ctrl.acpt_a1_match_pkt = 1;
mask.acpt_a1_match_pkt = 1;
ctrl.uc_pkt_chk_cam_match = 0;
mask.uc_pkt_chk_cam_match = 1;
/* check broadcast (Probe req) */
ctrl.acpt_bc_pkt = 1;
mask.acpt_bc_pkt = 1;
ctrl.bc_pkt_chk_cam_match = 0;
mask.bc_pkt_chk_cam_match = 1;
if ((hal_com->chip_id == CHIP_WIFI6_8852A)
&& (hal_com->cv == CAV)) {
/* don't check address cam for multicast, accept all */
ctrl.acpt_mc_pkt = 1;
mask.acpt_mc_pkt = 1;
} else {
/* check multicast */
ctrl.acpt_mc_pkt = 1;
mask.acpt_mc_pkt = 1;
/* black list filter */
ctrl.mc_pkt_white_lst_mode = 0;
mask.mc_pkt_white_lst_mode = 1;
}
/* check beacon */
ctrl.bcn_chk_en = 1;
mask.bcn_chk_en = 1;
ctrl.bcn_chk_rule = 2; /* 2: A2&A3 match */
mask.bcn_chk_rule = 0x3;
/* bcn_chk_rule
0: A3 hit
1: A2 hit
2: A2 & A3 hit
3: A2 | A3 hit
*/
/* accept power management frame */
ctrl.acpt_pwr_mngt_pkt = 1;
mask.acpt_pwr_mngt_pkt = 1;
ctrl.acpt_ftm_req_pkt = 1;
mask.acpt_ftm_req_pkt = 1;
#endif
break;
}
err = mac->ops->set_rx_fltr_opt(mac, &ctrl, &mask, band);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_set_rxfltr_acpt_crc_err - Accept CRC error packets or not
* @hal_com: pointer of struct rtw_hal_com_t
* @band: 0x0: band0, 0x1: band1
* @enable: 0: deny, 1: accept
*
* Control accepting CRC error packets or not.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status rtw_hal_mac_set_rxfltr_acpt_crc_err(
struct rtw_hal_com_t *hal_com, u8 band, u8 enable)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_rx_fltr_ctrl_t ctrl = {0};
struct mac_ax_rx_fltr_ctrl_t mask = {0};
u32 err;
if (enable)
ctrl.acpt_crc32_err_pkt = 1;
else
ctrl.acpt_crc32_err_pkt = 0;
mask.acpt_crc32_err_pkt = 1;
err = mac->ops->set_rx_fltr_opt(mac, &ctrl, &mask, band);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_set_rxfltr_mpdu_size - Set max MPDU size
* @hal_com: pointer of struct rtw_hal_com_t
* @band: 0x0: band0, 0x1: band1
* @size: MPDU max size, unit: byte. 0 for no limit.
*
* MPDU size exceed Max size would be dropped.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status rtw_hal_mac_set_rxfltr_mpdu_size(
struct rtw_hal_com_t *hal_com, u8 band, u16 size)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_rx_fltr_ctrl_t ctrl = {0};
struct mac_ax_rx_fltr_ctrl_t mask = {0};
u32 err;
/* unit of pkt_len_fltr is 512 bytes */
ctrl.pkt_len_fltr = size >> 9;
ctrl.pkt_len_fltr += (size & 0x7F) ? 1 : 0;
mask.pkt_len_fltr = 0x3F;
err = mac->ops->set_rx_fltr_opt(mac, &ctrl, &mask, band);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_set_rxfltr_by_type - Filter RX frame by frame type
* @hal_com: pointer of struct rtw_hal_com_t
* @band: 0x0: band0, 0x1: band1
* @type: 802.11 frame type, b'00: mgmt, b'01: ctrl, b'10: data
* @target: 0: drop, 1: accept(driver), 2: firmware
*
* Set RX filter setting by 802.11 frame type and frame would be dropped or
* forward to specific target.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok, otherwise fail.
*/
enum rtw_hal_status rtw_hal_mac_set_rxfltr_by_type(
struct rtw_hal_com_t *hal_com, u8 band, u8 type, u8 target)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum mac_ax_pkt_t ftype;
enum mac_ax_fwd_target fwd;
u32 err;
switch (type) {
case RTW_PHL_PKT_TYPE_MGNT:
ftype = MAC_AX_PKT_MGNT;
break;
case RTW_PHL_PKT_TYPE_CTRL:
ftype = MAC_AX_PKT_CTRL;
break;
case RTW_PHL_PKT_TYPE_DATA:
ftype = MAC_AX_PKT_DATA;
break;
default:
return RTW_HAL_STATUS_FAILURE;
}
if (target > MAC_AX_FWD_TO_WLAN_CPU)
return RTW_HAL_STATUS_FAILURE;
fwd = (enum mac_ax_fwd_target)target;
err = mac->ops->set_rx_fltr_typ_opt(mac, ftype, fwd, band);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_set_rxfltr_by_subtype - Filter RX frame by frame type & subtype
* @hal_com: pointer of struct rtw_hal_com_t
* @band: 0x0: band0, 0x1: band1
* @type: 802.11 frame type, b'00: mgmt, b'01: ctrl, b'10: data
* @subtype: 802.11 frame subtype, value range is 0x00~0xFF.
* @target: 0: drop, 1: accept(driver), 2: firmware
*
* Set RX filter setting by 802.11 frame type and subtype, then frame would be
* dropped or forward to specific target.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok, otherwise fail.
*/
enum rtw_hal_status rtw_hal_mac_set_rxfltr_by_subtype(
struct rtw_hal_com_t *hal_com, u8 band,
u8 type, u8 subtype, u8 target)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum mac_ax_pkt_t ftype;
enum mac_ax_fwd_target fwd;
u32 err;
switch (type) {
case 0:
ftype = MAC_AX_PKT_MGNT;
break;
case 1:
ftype = MAC_AX_PKT_CTRL;
break;
case 2:
ftype = MAC_AX_PKT_DATA;
break;
default:
return RTW_HAL_STATUS_FAILURE;
}
if (subtype > 0xFF)
return RTW_HAL_STATUS_FAILURE;
if (target > MAC_AX_FWD_TO_WLAN_CPU)
return RTW_HAL_STATUS_FAILURE;
fwd = (enum mac_ax_fwd_target)target;
err = mac->ops->set_rx_fltr_typstyp_opt(mac, ftype, subtype, fwd, band);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_enable_bb_rf(struct hal_info_t *hal_info, u8 enable)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
mac->ops->set_hw_value(mac, MAC_AX_HW_EN_BB_RF, &enable);
return RTW_HAL_STATUS_SUCCESS;
}
void
rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr,
u8 *buf, u32 len, u32 dbg_path)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac_mem_dump(mac, MAC_AX_MEM_SHARED_BUF, strt_addr, buf, len, dbg_path);
}
void
rtl_hal_dump_sec_cam_tbl(struct rtw_hal_com_t *hal_com)
{
u32 i = 0;
u32 sec_cam_tbl_sz = 128;
struct hal_info_t *hal = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct sec_cam_table_t *sec_cam_table = mac->hw_info->sec_cam_table;
struct sec_cam_entry_t *entry = NULL;
PHL_PRINT("===== HW Info Security CAM Table =====\n");
PHL_PRINT("entry valid mac_id key_id key_type\n");
for (i = 0; i < sec_cam_tbl_sz; i++) {
entry = sec_cam_table->sec_cam_entry[i];
if (entry == NULL)
continue;
PHL_PRINT(" %3d %3d %3d %3d %3d\n",
i, entry->valid, entry->mac_id, entry->key_id, entry->key_type);
}
}
void halmac_cmd_parser(struct hal_info_t *hal_info, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac->ops->halmac_cmd_parser(mac, input, input_num, output, out_len);
}
s32 halmac_cmd(struct hal_info_t *hal_info, char *input, char *output, u32 out_len)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
return mac->ops->halmac_cmd(mac, input, output, out_len);
}
bool rtw_hal_mac_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
if(incmd->in_type == RTW_ARG_TYPE_BUF)
halmac_cmd(hal_info, incmd->in.buf, output, out_len);
else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){
halmac_cmd_parser(hal_info, incmd->in.vector,
incmd->in_cnt_len, output, out_len);
}
return true;
}
static enum mac_ax_cmac_path_sel _ac_drv2mac(u8 ac, u8 wmm)
{
enum mac_ax_cmac_path_sel sel = MAC_AX_CMAC_PATH_SEL_INVALID;
switch (ac) {
case 0:
/* BE */
sel = MAC_AX_CMAC_PATH_SEL_BE0;
break;
case 1:
/* BK */
sel = MAC_AX_CMAC_PATH_SEL_BK0;
break;
case 2:
/* VI */
sel = MAC_AX_CMAC_PATH_SEL_VI0;
break;
case 3:
/* VO */
sel = MAC_AX_CMAC_PATH_SEL_VO0;
break;
}
if (sel != MAC_AX_CMAC_PATH_SEL_INVALID && wmm)
/* wmm == 1 */
sel += 4;
return sel;
}
/**
* rtw_hal_mac_set_edca() - setup WMM EDCA parameter
* @hal_com: struct rtw_hal_com_t *
* @band: 0x0: band0, 0x1: band1
* @wmm: hardware wmm index
* @ac: Access Category, 0:BE, 1:BK, 2:VI, 3:VO
* @param: AIFS:BIT[7:0], CWMIN:BIT[11:8], CWMAX:BIT[15:12],
* TXOP:BIT[31:16]
*
* Setup WMM EDCA parameter set for specific AC.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status
rtw_hal_mac_set_edca(struct rtw_hal_com_t *hal_com, u8 band, u8 wmm, u8 ac,
u32 param)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_edca_param edca = {0};
u32 err = 0;
edca.band = band;
edca.path = _ac_drv2mac(ac, wmm);
edca.txop_32us = param >> 16;
edca.ecw_max = (param >> 12) & 0xF;
edca.ecw_min = (param >> 8) & 0xF;
edca.aifs_us = param & 0xFF;
err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_EDCA_PARAM, &edca);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#ifdef CONFIG_PHL_TWT
enum rtw_hal_status
rtw_hal_mac_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, struct rtw_wifi_role_t *role, u8 action)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_twt_para mac_twt_para = {0};
u32 mac_status = MACSUCCESS;
switch (twt_info.nego_type)
{
case RTW_PHL_INDIV_TWT:
mac_twt_para.nego_tp = MAC_AX_TWT_NEGO_TP_IND;
mac_twt_para.flow_id = 0;
break;
case RTW_PHL_WAKE_TBTT_INR:
mac_twt_para.nego_tp = MAC_AX_TWT_NEGO_TP_WAKE;
mac_twt_para.flow_id = 0;
break;
case RTW_PHL_BCAST_TWT:
mac_twt_para.nego_tp = MAC_AX_TWT_NEGO_TP_BRC;
mac_twt_para.flow_id = twt_info.bcast_twt_id;
break;
default:
PHL_ERR("%s : Error TWT nego type %d\n", __func__, twt_info.nego_type);
return RTW_HAL_STATUS_FAILURE;
}
switch (action) {
case TWT_CFG_ADD:
mac_twt_para.act = MAC_AX_TWT_ACT_TP_ADD;
break;
case TWT_CFG_DELETE:
mac_twt_para.act = MAC_AX_TWT_ACT_TP_DEL;
break;
case TWT_CFG_MODIFY:
mac_twt_para.act = MAC_AX_TWT_ACT_TP_MOD;
break;
default:
PHL_ERR("%s : Error TWT action %d\n", __func__, action);
return RTW_HAL_STATUS_FAILURE;
}
mac_twt_para.trig = twt_info.trigger;
mac_twt_para.flow_tp = twt_info.flow_type;
mac_twt_para.proct = twt_info.twt_protection;
mac_twt_para.id = twt_info.twt_id;
mac_twt_para.wake_exp = twt_info.twt_wake_int_exp;
mac_twt_para.band = role->hw_band;
mac_twt_para.port = role->hw_port;
mac_twt_para.rsp_pm = twt_info.responder_pm_mode;
mac_twt_para.wake_unit = twt_info.wake_dur_unit;
mac_twt_para.impt = twt_info.implicit_lastbcast;
mac_twt_para.wake_man = twt_info.twt_wake_int_mantissa;
mac_twt_para.dur = twt_info.nom_min_twt_wake_dur;
mac_twt_para.trgt_l = twt_info.target_wake_time_l;
mac_twt_para.trgt_h = twt_info.target_wake_time_h;
/* HalMac API to setup/delete TWT config*/
mac_status = mac->ops->twt_info_upd_h2c(mac, &mac_twt_para);
if (MACSUCCESS != mac_status){
PHL_TRACE(COMP_PHL_TWT, _PHL_DEBUG_, "rtw_hal_mac_twt_info_update(): mac_twt_info_upd_h2c fail(%d)\n",
mac_status);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_twtact_para mac_twtact_para = {0};
u32 mac_status = MACSUCCESS;
switch (action) {
case TWT_STA_ADD_MACID:
mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_ADD;
break;
case TWT_STA_DEL_MACID:
mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_DEL;
break;
case TWT_STA_TETMINATW_SP:
mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_TRMNT;
break;
case TWT_STA_SUSPEND_TWT:
mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_SUS;
break;
case TWT_STA_RESUME_TWT:
mac_twtact_para.act = MAC_AX_TWTACT_ACT_TP_RSUM;
break;
default:
PHL_ERR("%s : Error TWT action %d\n", __func__, action);
return RTW_HAL_STATUS_FAILURE;
}
mac_twtact_para.macid = macid;
mac_twtact_para.id = twt_id;
/* Call HalMac API to setup/delete TWT STA config*/
mac_status = mac->ops->twt_act_h2c(mac, &mac_twtact_para);
if (MACSUCCESS != mac_status) {
PHL_TRACE(COMP_PHL_TWT, _PHL_DEBUG_, "rtw_hal_mac_twt_sta_update(): mac_twt_act_h2c fail(%d)\n",
mac_status);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_twt_sta_announce(void *hal, u8 macid)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_twtanno_para mac_twtanno_para = {0};
u32 mac_status = MACSUCCESS;
mac_twtanno_para.macid = macid;
mac_status = mac->ops->twt_anno_h2c(mac, &mac_twtanno_para);
if (MACSUCCESS != mac_status) {
PHL_TRACE(COMP_PHL_TWT, _PHL_DEBUG_, "rtw_hal_mac_twt_sta_announce(): mac_twt_anno_h2c fail(%d)\n",
mac_status);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
#endif /* CONFIG_PHL_TWT */
/**
* rtw_hal_mac_get_ampdu_cfg() - get ampdu config
* @hal_com: struct rtw_hal_com_t *
* @band: 0x0: band0, 0x1: band1
* @cfg: struct hal_ax_ampdu_cfg *
* Get ampdu config.
* Return RTW_HAL_STATUS_SUCCESS when query is done.
*/
enum rtw_hal_status
rtw_hal_mac_get_ampdu_cfg(struct rtw_hal_com_t *hal_com,
u8 band,
struct mac_ax_ampdu_cfg *cfg)
{
/* To Do: need to refine after Mac api updating*/
#if 0
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 err = 0;
cfg->band = band;
err = mac->ops->get_hw_value(mac, MAC_AX_HW_GET_AMPDU_CFG, cfg);
if (err)
return RTW_HAL_STATUS_FAILURE;
#endif
return RTW_HAL_STATUS_SUCCESS;
}
/*
* rtw_hal_mac_set_rty_lmt() - setup retry limit parameter
* @hal_com: struct rtw_hal_com_t *
* @macid:
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status
rtw_hal_mac_set_rty_lmt(struct rtw_hal_com_t *hal_com, u8 macid,
u8 rts_lmt_sel, u8 rts_lmt_val, u8 data_lmt_sel, u8 data_lmt_val)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_cctl_rty_lmt_cfg cfg = {0};
u32 err = 0;
cfg.macid = macid;
cfg.data_lmt_sel = data_lmt_sel;
cfg.data_lmt_val = data_lmt_val;
cfg.rts_lmt_sel = rts_lmt_sel;
cfg.rts_lmt_val = rts_lmt_val;
err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_CCTL_RTY_LMT, &cfg);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_is_tx_mgnt_empty() - Get tx mgnt queue status
* @hal_info: struct rtw_hal_info_t *
* @band: 0x0: band0, 0x1: band1
* @st: queue status, 1 for empty and 0 for not empty.
*
* Return RTW_HAL_STATUS_SUCCESS when setting is ok.
*/
enum rtw_hal_status
rtw_hal_mac_is_tx_mgnt_empty(struct hal_info_t *hal_info, u8 band, u8 *st)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_tx_queue_empty q_st = {{0}};
u32 err;
err = mac->ops->is_txq_empty(mac, &q_st);
if (err != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
if ((band == 0) && (q_st.band0_mgnt_empty == DLE_QUEUE_EMPTY))
*st = 1;
else if ((band == 1) && (q_st.band1_mgnt_empty == DLE_QUEUE_EMPTY))
*st = 1;
else
*st = 0;
return RTW_HAL_STATUS_SUCCESS;
}
/* FW Sounding Command */
/* 1. NDPA Content */
void _hal_max_ax_snd_cmd_ndpa(struct mac_ax_ndpa_para *mac_ndpa,
struct hal_ndpa_para *hal_ndpa,
bool he, u8 sta_nr)
{
u8 i = 0;
struct hal_he_ndpa_sta_info *hal_he_sta = NULL;
struct hal_vht_ndpa_sta_info *hal_vht_sta = NULL;
mac_ndpa->common.frame_ctl = hal_ndpa->common.frame_ctl;
mac_ndpa->common.duration = hal_ndpa->common.duration;
for (i = 0; i < MAC_ALEN; i++) {
mac_ndpa->common.addr1[i] = hal_ndpa->common.addr1[i];
mac_ndpa->common.addr2[i] = hal_ndpa->common.addr2[i];
}
mac_ndpa->snd_dialog.dialog = hal_ndpa->snd_dialog.token;
mac_ndpa->snd_dialog.he = hal_ndpa->snd_dialog.he;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "halmac he 0x%x sta_nr %d \n", he, sta_nr);
if (he) {
for (i = 0; (i < sta_nr)&&(i < HAL_MAX_HE_SND_STA_NUM); i++) {
hal_he_sta = (struct hal_he_ndpa_sta_info *)
&hal_ndpa->ndpa_sta_info[i];
mac_ndpa->he_para.sta_info[i].aid = hal_he_sta->aid;
mac_ndpa->he_para.sta_info[i].bw = hal_he_sta->bw;
mac_ndpa->he_para.sta_info[i].fb_ng = hal_he_sta->fb_ng;
mac_ndpa->he_para.sta_info[i].disambiguation = 1;
mac_ndpa->he_para.sta_info[i].cb = hal_he_sta->cb;//cb nc
mac_ndpa->he_para.sta_info[i].nc = hal_he_sta->nc;//cb nc
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "halmac cmd buf HE (%d) : aid 0x%x bw 0x%x fbng 0x%x cb 0x%x nc 0x%x\n",
i, mac_ndpa->he_para.sta_info[i].aid,
mac_ndpa->he_para.sta_info[i].bw,
mac_ndpa->he_para.sta_info[i].fb_ng,
mac_ndpa->he_para.sta_info[i].cb,
mac_ndpa->he_para.sta_info[i].nc);
}
} else {
for (i = 0; (i < sta_nr)&&(i < HAL_MAX_VHT_SND_STA_NUM); i++) {
hal_vht_sta = (struct hal_vht_ndpa_sta_info *)
&hal_ndpa->ndpa_sta_info[i];
mac_ndpa->vht_para.sta_info[i].aid =
(u16)hal_vht_sta->aid12;
mac_ndpa->vht_para.sta_info[i].fb_type =
(u16)hal_vht_sta->feedback_type;
mac_ndpa->vht_para.sta_info[i].nc =
(u16)hal_vht_sta->nc;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "halmac cmd buf VHT(%d) : aid 0x%x fb 0x%x nc 0x%x\n",
i,
mac_ndpa->vht_para.sta_info[i].aid,
mac_ndpa->vht_para.sta_info[i].fb_type,
mac_ndpa->vht_para.sta_info[i].nc);
}
}
}
/* 2-1. BFRP Content - VHT */
void _hal_max_ax_snd_cmd_bfrp_vht(struct mac_ax_bfrp_para *mac_bfrp,
struct hal_bfrp_para *hal_bfrp, u8 bfrp_num)
{
struct mac_ax_vht_bfrp_para *mac_vht_bfrp = NULL;
struct hal_bfrp_vht *hal_vht_bfrp = NULL;
u8 i = 0, j = 0;
for (i = 0; (i <= bfrp_num)&&(i < HAL_MAX_VHT_BFRP_NUM); i++){
mac_bfrp->hdr[i].frame_ctl = hal_bfrp->hdr[i].frame_ctl;
mac_bfrp->hdr[i].duration = hal_bfrp->hdr[i].duration;
for (j = 0; j < MAC_ALEN; j++) {
mac_bfrp->hdr[i].addr1[j] = hal_bfrp->hdr[i].addr1[j];
mac_bfrp->hdr[i].addr2[j] = hal_bfrp->hdr[i].addr2[j];
}
mac_vht_bfrp = &mac_bfrp->vht_para[i];
hal_vht_bfrp = &hal_bfrp->vht_para[i];
mac_vht_bfrp->retransmission_bitmap = hal_vht_bfrp->rexmit_bmp;
}
}
/* 2-2. BFRP Content - HE */
void _hal_max_ax_snd_cmd_bfrp_he(struct mac_ax_bfrp_para *mac_bfrp,
struct hal_bfrp_para *hal_bfrp,
u8 num_1, u8 num_2)
{
u8 i = 0;
struct mac_ax_he_bfrp_para *mac_he_bfrp = NULL;
struct hal_bfrp_he *hal_he_bfrp = NULL;
/* BFRP-0 */
if (num_1) {
mac_bfrp->hdr[0].frame_ctl = hal_bfrp->hdr[0].frame_ctl;
mac_bfrp->hdr[0].duration = hal_bfrp->hdr[0].duration;
for (i = 0; i < MAC_ALEN; i++) {
mac_bfrp->hdr[0].addr1[i] = hal_bfrp->hdr[0].addr1[i];
mac_bfrp->hdr[0].addr2[i] = hal_bfrp->hdr[0].addr2[i];
}
mac_he_bfrp = &mac_bfrp->he_para[0];
hal_he_bfrp = &hal_bfrp->he_para[0];
mac_he_bfrp->common.tgr_info = hal_he_bfrp->common.tgr_info;
mac_he_bfrp->common.ul_len = hal_he_bfrp->common.ul_len;
mac_he_bfrp->common.more_tf = hal_he_bfrp->common.more_tf;
mac_he_bfrp->common.cs_rqd = hal_he_bfrp->common.cs_rqd;
mac_he_bfrp->common.ul_bw = hal_he_bfrp->common.ul_bw;
mac_he_bfrp->common.gi_ltf = hal_he_bfrp->common.gi_ltf;
mac_he_bfrp->common.mimo_ltfmode =
hal_he_bfrp->common.mimo_ltfmode;
mac_he_bfrp->common.num_heltf = hal_he_bfrp->common.num_heltf;
mac_he_bfrp->common.ul_pktext = hal_he_bfrp->common.ul_pktext;
mac_he_bfrp->common.ul_stbc = hal_he_bfrp->common.ul_stbc;
mac_he_bfrp->common.ldpc_extra_sym =
hal_he_bfrp->common.ldpc_extra_sym;
mac_he_bfrp->common.dplr = hal_he_bfrp->common.dplr;
mac_he_bfrp->common.ap_tx_pwr = hal_he_bfrp->common.ap_tx_pwr;
mac_he_bfrp->common.ul_sr = hal_he_bfrp->common.ul_sr;
mac_he_bfrp->common.ul_siga2_rsvd =
hal_he_bfrp->common.ul_siga2_rsvd;
for( i = 0; (i < num_1)&&(i < HAL_MAX_HE_BFRP_STA_NUM); i++) {
mac_he_bfrp->user[i].aid12 =
hal_he_bfrp->user[i].aid12;
mac_he_bfrp->user[i].fbseg_rexmit_bmp =
hal_he_bfrp->fbseg_rexmit_bmp[i];
mac_he_bfrp->user[i].ru_pos =
hal_he_bfrp->user[i].ru_pos;
mac_he_bfrp->user[i].ss_alloc =
hal_he_bfrp->user[i].ss_alloc;
mac_he_bfrp->user[i].ul_dcm =
hal_he_bfrp->user[i].ul_dcm;
mac_he_bfrp->user[i].ul_fec_code =
hal_he_bfrp->user[i].ul_fec_code;
mac_he_bfrp->user[i].ul_mcs =
hal_he_bfrp->user[i].ul_mcs;
mac_he_bfrp->user[i].ul_tgt_rssi =
hal_he_bfrp->user[i].ul_tgt_rssi;
}
}
/* BFRP - 1 */
if (num_2) {
mac_bfrp->hdr[1].frame_ctl = hal_bfrp->hdr[1].frame_ctl;
mac_bfrp->hdr[1].duration = hal_bfrp->hdr[1].duration;
for (i = 0; i < MAC_ALEN; i++) {
mac_bfrp->hdr[1].addr1[i] = hal_bfrp->hdr[1].addr1[i];
mac_bfrp->hdr[1].addr2[i] = hal_bfrp->hdr[1].addr2[i];
}
mac_he_bfrp = &mac_bfrp->he_para[1];
hal_he_bfrp = &hal_bfrp->he_para[1];
mac_he_bfrp->common.tgr_info = hal_he_bfrp->common.tgr_info;
mac_he_bfrp->common.ul_len = hal_he_bfrp->common.ul_len;
mac_he_bfrp->common.more_tf = hal_he_bfrp->common.more_tf;
mac_he_bfrp->common.cs_rqd = hal_he_bfrp->common.cs_rqd;
mac_he_bfrp->common.ul_bw = hal_he_bfrp->common.ul_bw;
mac_he_bfrp->common.gi_ltf = hal_he_bfrp->common.gi_ltf;
mac_he_bfrp->common.mimo_ltfmode =
hal_he_bfrp->common.mimo_ltfmode;
mac_he_bfrp->common.num_heltf = hal_he_bfrp->common.num_heltf;
mac_he_bfrp->common.ul_pktext = hal_he_bfrp->common.ul_pktext;
mac_he_bfrp->common.ul_stbc = hal_he_bfrp->common.ul_stbc;
mac_he_bfrp->common.ldpc_extra_sym =
hal_he_bfrp->common.ldpc_extra_sym;
mac_he_bfrp->common.dplr = hal_he_bfrp->common.dplr;
mac_he_bfrp->common.ap_tx_pwr = hal_he_bfrp->common.ap_tx_pwr;
mac_he_bfrp->common.ul_sr = hal_he_bfrp->common.ul_sr;
mac_he_bfrp->common.ul_siga2_rsvd =
hal_he_bfrp->common.ul_siga2_rsvd;
for( i = 0; (i < num_1)&&(i < HAL_MAX_HE_BFRP_STA_NUM); i++) {
mac_he_bfrp->user[i].aid12 =
hal_he_bfrp->user[i].aid12;
mac_he_bfrp->user[i].fbseg_rexmit_bmp =
hal_he_bfrp->fbseg_rexmit_bmp[i];
mac_he_bfrp->user[i].ru_pos =
hal_he_bfrp->user[i].ru_pos;
mac_he_bfrp->user[i].ss_alloc =
hal_he_bfrp->user[i].ss_alloc;
mac_he_bfrp->user[i].ul_dcm =
hal_he_bfrp->user[i].ul_dcm;
mac_he_bfrp->user[i].ul_fec_code =
hal_he_bfrp->user[i].ul_fec_code;
mac_he_bfrp->user[i].ul_mcs =
hal_he_bfrp->user[i].ul_mcs;
mac_he_bfrp->user[i].ul_tgt_rssi =
hal_he_bfrp->user[i].ul_tgt_rssi;
}
}
}
/* 2-3 he bfrp f2p cmd */
void _hal_max_ax_snd_cmd_bfrp_he_f2p(struct mac_ax_snd_f2P *mac_bfrp_f2p,
struct hal_bfrp_para *hal_bfrp,
u8 num_1, u8 num_2)
{
struct hal_bfrp_he *hal_he_bfrp = NULL;
if (num_1) {
hal_he_bfrp = &hal_bfrp->he_para[0];
mac_bfrp_f2p[0].csi_len_bfrp =
hal_he_bfrp->f2p_info.csi_len_bfrp;
mac_bfrp_f2p[0].tb_t_pe_bfrp =
hal_he_bfrp->f2p_info.tb_t_pe_bfrp;
mac_bfrp_f2p[0].tri_pad_bfrp =
hal_he_bfrp->f2p_info.tri_pad_bfrp;
mac_bfrp_f2p[0].ul_cqi_rpt_tri_bfrp =
hal_he_bfrp->f2p_info.ul_cqi_rpt_tri_bfrp;
mac_bfrp_f2p[0].rf_gain_idx_bfrp =
hal_he_bfrp->f2p_info.rf_gain_idx_bfrp;
mac_bfrp_f2p[0].fix_gain_en_bfrp =
hal_he_bfrp->f2p_info.fix_gain_en_bfrp;
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"==> _hal_max_ax_snd_cmd_bfrp_he_f2p[0] \n");
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[0].csi_len_bfrp = 0x%x \n",
mac_bfrp_f2p[0].csi_len_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[0].tb_t_pe_bfrp = 0x%x \n",
mac_bfrp_f2p[0].tb_t_pe_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[0].tri_pad_bfrp = 0x%x \n",
mac_bfrp_f2p[0].tri_pad_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[0].ul_cqi_rpt_tri_bfrp = 0x%x \n",
mac_bfrp_f2p[0].ul_cqi_rpt_tri_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[0].rf_gain_idx_bfrp = 0x%x \n",
mac_bfrp_f2p[0].rf_gain_idx_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[0].fix_gain_en_bfrp = 0x%x \n",
mac_bfrp_f2p[0].fix_gain_en_bfrp);
}
if (num_2) {
hal_he_bfrp = &hal_bfrp->he_para[1];
mac_bfrp_f2p[1].csi_len_bfrp =
hal_he_bfrp->f2p_info.csi_len_bfrp;
mac_bfrp_f2p[1].tb_t_pe_bfrp =
hal_he_bfrp->f2p_info.tb_t_pe_bfrp;
mac_bfrp_f2p[1].tri_pad_bfrp =
hal_he_bfrp->f2p_info.tri_pad_bfrp;
mac_bfrp_f2p[1].ul_cqi_rpt_tri_bfrp =
hal_he_bfrp->f2p_info.ul_cqi_rpt_tri_bfrp;
mac_bfrp_f2p[1].rf_gain_idx_bfrp =
hal_he_bfrp->f2p_info.rf_gain_idx_bfrp;
mac_bfrp_f2p[1].fix_gain_en_bfrp =
hal_he_bfrp->f2p_info.fix_gain_en_bfrp;
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"==> _hal_max_ax_snd_cmd_bfrp_he_f2p[1] \n");
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[1].csi_len_bfrp = 0x%x \n",
mac_bfrp_f2p[1].csi_len_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[1].tb_t_pe_bfrp = 0x%x \n",
mac_bfrp_f2p[1].tb_t_pe_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[1].tri_pad_bfrp = 0x%x \n",
mac_bfrp_f2p[1].tri_pad_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[1].ul_cqi_rpt_tri_bfrp = 0x%x \n",
mac_bfrp_f2p[1].ul_cqi_rpt_tri_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[1].rf_gain_idx_bfrp = 0x%x \n",
mac_bfrp_f2p[1].rf_gain_idx_bfrp);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_,
"mac_bfrp_f2p[1].fix_gain_en_bfrp = 0x%x \n",
mac_bfrp_f2p[1].fix_gain_en_bfrp);
}
}
/* 3. WD Content */
void _hal_max_ax_snd_cmd_wd(struct mac_ax_snd_wd_para *mac_wd,
struct hal_snd_wd_para *hal_wd)
{
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> _hal_max_ax_snd_cmd_wd \n");
mac_wd->txpktsize = hal_wd->txpktsize;
mac_wd->ndpa_duration = hal_wd->ndpa_duration;
mac_wd->datarate = hal_wd->datarate;
mac_wd->macid = hal_wd->macid;
mac_wd->force_txop = hal_wd->force_txop;
mac_wd->data_bw = hal_wd->data_bw;
mac_wd->gi_ltf = hal_wd->gi_ltf;
mac_wd->data_er = hal_wd->data_er;
mac_wd->data_dcm = hal_wd->data_dcm;
mac_wd->data_stbc = hal_wd->data_stbc;
mac_wd->data_ldpc = hal_wd->data_ldpc;
mac_wd->data_bw_er = hal_wd->data_bw_er;
mac_wd->multiport_id = hal_wd->multiport_id;
mac_wd->mbssid = hal_wd->mbssid;
mac_wd->signaling_ta_pkt_sc = hal_wd->signaling_ta_pkt_sc;
mac_wd->sw_define = hal_wd->sw_define;
mac_wd->txpwr_ofset_type = hal_wd->txpwr_ofset_type;
mac_wd->lifetime_sel = hal_wd->lifetime_sel;
mac_wd->stf_mode = hal_wd->stf_mode;
mac_wd->disdatafb = hal_wd->disdatafb;
mac_wd->data_txcnt_lmt_sel = hal_wd->data_txcnt_lmt_sel;
mac_wd->data_txcnt_lmt = hal_wd->data_txcnt_lmt;
mac_wd->sifs_tx = hal_wd->sifs_tx;
mac_wd->snd_pkt_sel = hal_wd->snd_pkt_sel;
mac_wd->ndpa = hal_wd->ndpa;
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->txpktsize = 0x%x \n", mac_wd->txpktsize);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->ndpa_duration = 0x%x \n", mac_wd->ndpa_duration);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->datarate = 0x%x \n", mac_wd->datarate);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac_wd->macid = 0x%x \n", mac_wd->macid);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->force_txop = 0x%x \n", mac_wd->force_txop);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_bw = 0x%x \n", mac_wd->data_bw);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->gi_ltf = 0x%x \n", mac_wd->gi_ltf);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_er = 0x%x \n", mac_wd->data_er);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_dcm = 0x%x \n", mac_wd->data_dcm);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_stbc = 0x%x \n", mac_wd->data_stbc);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_ldpc = 0x%x \n", mac_wd->data_ldpc);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_bw_er = 0x%x \n", mac_wd->data_bw_er);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->multiport_id = 0x%x \n", mac_wd->multiport_id);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->mbssid = 0x%x \n", mac_wd->mbssid);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->signaling_ta_pkt_sc = 0x%x \n", mac_wd->signaling_ta_pkt_sc);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->sw_define = 0x%x \n", mac_wd->sw_define);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->txpwr_ofset_type = 0x%x \n", mac_wd->txpwr_ofset_type);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->lifetime_sel = 0x%x \n", mac_wd->lifetime_sel);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->stf_mode = 0x%x \n", mac_wd->stf_mode);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->disdatafb = 0x%x \n", mac_wd->disdatafb);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_txcnt_lmt_sel = 0x%x \n", mac_wd->data_txcnt_lmt_sel);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->data_txcnt_lmt = 0x%x \n", mac_wd->data_txcnt_lmt);
PHL_TRACE(COMP_PHL_SOUND, _PHL_DEBUG_, "mac_wd->sifs_tx = 0x%x \n", mac_wd->sifs_tx);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac_wd->snd_pkt_sel = 0x%x \n", mac_wd->snd_pkt_sel);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac_wd->ndpa = 0x%x \n", mac_wd->ndpa);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "<== _hal_max_ax_snd_cmd_wd \n");
}
enum rtw_hal_status
hal_mac_ax_send_fw_snd(struct hal_info_t *hal_info,
struct hal_ax_fwcmd_snd *hal_cmd)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_fwcmd_snd snd_cmd = {0};
u8 i = 0, he = 0, sta_nr = 0;
/* 1. COMMAND Common */
snd_cmd.frexgtype = hal_cmd->frame_ex_type;
snd_cmd.bfrp0_user_num = hal_cmd->bfrp0_sta_nr;
snd_cmd.bfrp1_user_num = hal_cmd->bfrp1_sta_nr;
for (i = 0; i < HAL_MAX_HE_SND_STA_NUM; i++) {
snd_cmd.macid[i] = (u8)hal_cmd->macid[i];
}
he = (hal_cmd->frame_ex_type >= HAL_FEXG_TYPE_AX_SU) ? 1 : 0;
if (hal_cmd->frame_ex_type == HAL_FEXG_TYPE_AX_SU) {
sta_nr = 1;
} else {
sta_nr = he ? (hal_cmd->bfrp0_sta_nr + hal_cmd->bfrp1_sta_nr) :
(hal_cmd->frame_ex_type - HAL_FEXG_TYPE_AC_SU + 1);
}
/* 2. NDPA Content */
_hal_max_ax_snd_cmd_ndpa(&snd_cmd.pndpa, &hal_cmd->ndpa,
he, sta_nr);
/* 3. BFRP Content */
if (he) {
_hal_max_ax_snd_cmd_bfrp_he(&snd_cmd.pbfrp, &hal_cmd->bfrp,
hal_cmd->bfrp0_sta_nr, hal_cmd->bfrp1_sta_nr);
_hal_max_ax_snd_cmd_bfrp_he_f2p(snd_cmd.f2p, &hal_cmd->bfrp,
hal_cmd->bfrp0_sta_nr, hal_cmd->bfrp1_sta_nr);
} else {
_hal_max_ax_snd_cmd_bfrp_vht(&snd_cmd.pbfrp, &hal_cmd->bfrp,
(sta_nr - 1));
}
/* 4. WD Content */
/* 4-1 NDPA */
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "NDPA WD: \n");
_hal_max_ax_snd_cmd_wd(&snd_cmd.wd[0], &hal_cmd->wd[0]);
/* 4-2 NDP */
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "NDP WD: \n");
_hal_max_ax_snd_cmd_wd(&snd_cmd.wd[1], &hal_cmd->wd[1]);
/* 4-3 BFRP*/
if (he) {
if (hal_cmd->bfrp0_sta_nr) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "HE BFRP-1 WD: \n");
_hal_max_ax_snd_cmd_wd(&snd_cmd.wd[2],
&hal_cmd->wd[2]);
}
if (hal_cmd->bfrp1_sta_nr) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "HE BFRP-2 WD: \n");
_hal_max_ax_snd_cmd_wd(&snd_cmd.wd[3],
&hal_cmd->wd[3]);
}
} else {
for (i = 0; i < (sta_nr - 1)&&(i < HAL_MAX_VHT_BFRP_NUM);
i++) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "VHT BFRP %d WD: \n", i);
_hal_max_ax_snd_cmd_wd(&snd_cmd.wd[2 + i],
&hal_cmd->wd[2 + i]);
}
}
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.macid[0] = 0x%x \n", snd_cmd.macid[0]);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.bfrp0_user_num = 0x%x \n", snd_cmd.bfrp0_user_num);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.bfrp1_user_num = 0x%x \n", snd_cmd.bfrp1_user_num);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.mode = 0x%x \n", snd_cmd.mode);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] snd_cmd.frexgtype = 0x%x \n", snd_cmd.frexgtype);
hstatus = mac->ops->set_snd_para(mac, &snd_cmd);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[fw_snd] hal_mac_ax_send_fw_snd hstatus = 0x%x\n", hstatus);
return hstatus;
}
enum rtw_hal_status
rtw_hal_mac_tx_mode_sel(struct hal_info_t *hal_info, u8 fw_tx, u8 txop_wmm_en_bm)
{
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_mac_tx_mode_sel mode_sel = {0};
if (fw_tx)
mode_sel.sw_mode_band0_en = 1;
if (txop_wmm_en_bm & BIT(0))
mode_sel.txop_rot_wmm0_en = 1;
if (txop_wmm_en_bm & BIT(1))
mode_sel.txop_rot_wmm1_en = 1;
if (txop_wmm_en_bm & BIT(2))
mode_sel.txop_rot_wmm2_en = 1;
if (txop_wmm_en_bm & BIT(3))
mode_sel.txop_rot_wmm3_en = 1;
mac->ops->tx_mode_sel(mac, &mode_sel);
return RTW_HAL_STATUS_SUCCESS;
}
u32 rtw_hal_mac_process_c2h(void *hal, struct rtw_c2h_info *c2h)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
struct mac_ax_ccxrpt mac_ccx = {0};
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL
u32 retry_limit = 32;
#endif
u32 retid = 0;
hal_status = mac->ops->get_c2h_event(mac, c2h, (enum phl_msg_evt_id *)&retid, (u8 *)&mac_ccx);
/*PHL_INFO("%s, hal_status=%d, retid=%d\n", __func__, hal_status, retid);*/
if (hal_status == RTW_HAL_STATUS_SUCCESS && (retid == MSG_EVT_CCX_REPORT_TX_OK || retid == MSG_EVT_CCX_REPORT_TX_FAIL)) {
#if 0
PHL_INFO("%s, mac_ccx.tx_state=%d\n", __func__, mac_ccx.tx_state);
PHL_INFO("%s, mac_ccx.sw_define=%d\n", __func__, mac_ccx.sw_define);
PHL_INFO("%s, mac_ccx.macid=%d\n", __func__, mac_ccx.macid);
PHL_INFO("%s, mac_ccx.pkt_ok_num=%d\n", __func__, mac_ccx.pkt_ok_num);
PHL_INFO("%s, mac_ccx.data_txcnt=%d\n", __func__, mac_ccx.data_txcnt);
#endif
#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL
if (hal_info->hal_com->spe_pkt_cnt_lmt)
retry_limit = hal_info->hal_com->spe_pkt_cnt_lmt;
if (retid == MSG_EVT_CCX_REPORT_TX_FAIL && mac_ccx.data_txcnt != retry_limit)
retid = 0;
#endif
}
return retid;
}
enum rtw_hal_status
rtw_hal_mac_f2p_test_cmd(struct hal_info_t *hal_info,
struct mp_mac_ax_f2p_test_para *info,
struct mp_mac_ax_f2p_wd *f2pwd,
struct mp_mac_ax_f2p_tx_cmd *ptxcmd,
u8 *psigb_addr)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 ret = RTW_HAL_STATUS_FAILURE;
if (mac->ops->f2p_test_cmd(mac, (void*)info, (void*)f2pwd, (void*)ptxcmd, psigb_addr) == MACSUCCESS)
ret = RTW_HAL_STATUS_SUCCESS;
return ret;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_ofst_mode(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_ofst_mode(mac, band, tpu);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_ofst_bw(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_ofst_bw(mac, band, tpu);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_ref_reg(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_ref_reg(mac, band, tpu);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_en(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_limit_en(mac, band, tpu);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_set_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band, bool en_val)
{
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
tpu->pwr_lmt_en = en_val;
return RTW_HAL_STATUS_SUCCESS;
}
bool
rtw_hal_mac_get_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band)
{
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
return tpu->pwr_lmt_en;
}
enum rtw_hal_status
rtw_hal_mac_set_tpu_mode(struct rtw_hal_com_t *hal_com,
enum rtw_tpu_op_mode op_mode_new, u8 band)
{
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (op_mode_new == TPU_DBG_MODE) {
tpu->op_mode = TPU_DBG_MODE;
tpu->normal_mode_lock_en = true;
} else {
tpu->op_mode = TPU_NORMAL_MODE;
tpu->normal_mode_lock_en = false;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_limit_rua_reg(mac, band, tpu);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
struct rtw_tpu_pwr_imt_info *lmt = &tpu->rtw_tpu_pwr_imt_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_limit_reg(mac, band, lmt);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct rtw_tpu_info *tpu = &hal_com->band[band].rtw_tpu_i;
struct rtw_tpu_pwr_by_rate_info *by_rate = &tpu->rtw_tpu_pwr_by_rate_i;
if (tpu->normal_mode_lock_en)
return RTW_HAL_STATUS_FAILURE;
mac->ops->write_pwr_by_rate_reg(mac, band, by_rate);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_log_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_BT_LOGICAL_EFUSE_SIZE, val) != MACSUCCESS){
PHL_ERR("%s: Get bt efuse size fail!\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s: BT Efuse log size = %d!\n", __FUNCTION__, *val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_bt_mask_size(struct rtw_hal_com_t *hal_com, u32 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if(mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_BT_EFUSE_MASK_SIZE, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s: bt efuse mask size = %d\n", __FUNCTION__, *val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_log_efuse_bt_map(struct rtw_hal_com_t *hal_com,
u8 *map,
u32 map_size,
u8 *mask,
u32 mask_size)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_pg_efuse_info info;
enum rtw_hal_status status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
u8 *tmp_map = NULL;
u8 *tmp_mask = NULL;
tmp_map = _os_mem_alloc(hal_com->drv_priv, map_size);
if(tmp_map == NULL) {
PHL_WARN("%s: Allocate pg map buffer fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_RESOURCE;
goto err_mem_tmp_map;
}
tmp_mask = _os_mem_alloc(hal_com->drv_priv, mask_size);
if(tmp_mask == NULL) {
PHL_WARN("%s: Allocate pg mask buffer fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_RESOURCE;
goto err_mem_tmp_mask;
}
/* Copy efuse map to tmp_map buffer */
_os_mem_cpy(hal_com->drv_priv, tmp_map, map, map_size);
/* Copy efuse mask to tmp_mask buffer */
_os_mem_cpy(hal_com->drv_priv, tmp_mask, mask, mask_size);
info.efuse_map = tmp_map;
info.efuse_map_size = map_size;
info.efuse_mask = tmp_mask;
info.efuse_mask_size= mask_size;
if (mac->ops->pg_efuse_by_map_bt(mac,
&info,
MAC_AX_EFUSE_R_DRV) != MACSUCCESS) {
PHL_INFO("%s: BT PG Fail!\n", __FUNCTION__);
status = RTW_HAL_STATUS_EFUSE_PG_FAIL;
}
else {
PHL_INFO("%s: BT PG ok!\n", __FUNCTION__);
status = RTW_HAL_STATUS_SUCCESS;
}
_os_mem_free(hal_com->drv_priv, tmp_map, map_size);
_os_mem_free(hal_com->drv_priv, tmp_mask, mask_size);
return status;
err_mem_tmp_mask:
_os_mem_free(hal_com->drv_priv, tmp_mask, mask_size);
err_mem_tmp_map:
_os_mem_free(hal_com->drv_priv, tmp_map, map_size);
return status;
}
enum rtw_hal_status
rtw_hal_mac_read_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, u8 *map)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->dump_log_efuse_bt(mac,
MAC_AX_EFUSE_PARSER_MAP,
#ifdef RTW_WKARD_EFUSE_OPERATION
MAC_AX_EFUSE_R_DRV,
#else
MAC_AX_EFUSE_R_AUTO,
#endif
map
) != MACSUCCESS) {
PHL_INFO("%s: Dump bt logical efuse fail!\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s: Dump bt logical efuse ok!\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_bt_avl(struct rtw_hal_com_t *hal_com, u32 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->get_efuse_avl_size_bt(mac, val) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_get_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->get_hw_value(mac,
MAC_AX_HW_GET_BT_EFUSE_SIZE, val) != MACSUCCESS){
PHL_ERR("%s: Get efuse bt size fail!\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s: Efuse size = %d!\n", __FUNCTION__, *val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_set_mu_edca(struct rtw_hal_com_t *hal_com, u8 band, u8 ac,
u16 timer, u8 cw_min, u8 cw_max, u8 aifs)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_muedca_param edca = {0};
u32 err = 0;
edca.band = band;
edca.ac = ac;
edca.aifs_us = aifs;
edca.ecw_min = cw_min;
edca.ecw_max = cw_max;
edca.muedca_timer_32us = timer;
err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_MUEDCA_PARAM, &edca);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_set_mu_edca_ctrl(struct rtw_hal_com_t *hal_com,
u8 band, u8 wmm, u8 set)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_muedca_cfg cfg = {0};
u32 err = 0;
cfg.band = band;
cfg.wmm_sel = wmm;
cfg.countdown_en = set;
cfg.tb_update_en = set;
err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_MUEDCA_CTRL, &cfg);
if (err)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_led_set_ctrl_mode(struct hal_info_t *hal_info,
enum mac_ax_led_mode mode,
u8 led_id)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->set_led_mode(mac, mode, led_id) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_led_ctrl(struct hal_info_t *hal_info, u8 high,
u8 led_id)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->led_ctrl(mac, high, led_id) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_sw_gpio_ctrl(struct hal_info_t *hal_info, u8 high,
u8 gpio)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->sw_gpio_ctrl(mac, high, gpio) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_set_sw_gpio_mode(struct hal_info_t *hal_info, enum rtw_gpio_mode mode,
u8 gpio)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->set_sw_gpio_mode(mac, mode, gpio) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_pcie_trx_mit(struct hal_info_t *hal_info,
struct mac_ax_pcie_trx_mitigation *mit_info)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (MACSUCCESS !=
mac->ops->set_hw_value(mac, MAX_AX_HW_PCIE_MIT, mit_info))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_read_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u32 size, u8 *val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
if (mac->ops->read_efuse(mac, addr, size, val, MAC_AX_EFUSE_BANK_BT) != MACSUCCESS)
return RTW_HAL_STATUS_FAILURE;
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_write_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u8 val)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u8 tmp_value;
if (mac->ops->read_efuse(mac, addr, 1, &tmp_value, MAC_AX_EFUSE_BANK_BT) != MACSUCCESS) {
PHL_INFO("%s read bt efuse hideen block fail.\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
if(tmp_value != 0xFF) {
PHL_INFO("%s bt efuse hidden offset = 0x%x has value = 0x%x.\n", __FUNCTION__, addr, tmp_value);
return RTW_HAL_STATUS_FAILURE;
}
if (mac->ops->write_efuse(mac, addr, val, MAC_AX_EFUSE_BANK_BT) != MACSUCCESS) {
PHL_INFO("%s write bt efuse hideen block fail.\n", __FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_tsf_sync(struct hal_info_t *hal_info,
u8 from_port, u8 to_port, enum phl_band_idx band,
s32 sync_offset_tu, enum hal_tsf_sync_act action)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum mac_ax_tsf_sync_act mac_action = MAC_AX_TSF_SYNC_NOW_ONCE;
s32 sync_offset_unit = 0;/* for halmac API use, unit is 32us */
switch (action){
case HAL_TSF_SYNC_NOW_ONCE :
mac_action = MAC_AX_TSF_SYNC_NOW_ONCE;
break;
case HAL_TSF_EN_SYNC_AUTO :
mac_action = MAC_AX_TSF_EN_SYNC_AUTO;
break;
case HAL_TSF_DIS_SYNC_AUTO :
mac_action = MAC_AX_TSF_DIS_SYNC_AUTO;
break;
default :
PHL_ERR("Unknown tsf sync action %d\n", action);
goto _error;
}
/* covert TU to unit(unit is 32us, 1TU=1024us=32*32us) */
sync_offset_unit = sync_offset_tu * 32;
if (mac->ops->tsf_sync(mac, from_port, to_port,
sync_offset_unit, mac_action) == MACSUCCESS)
return RTW_HAL_STATUS_SUCCESS;
_error:
return RTW_HAL_STATUS_FAILURE;
}
/**
* rtw_hal_mac_get_sec_cam() - get the security cam raw data from HW
* @hal_info: struct hal_info_t *
* @num: How many cam you wnat to dump from the first one.
* @buf: ptr to buffer which store the content from HW.
* If buf is NULL, use console as debug path.
* @size Size of allocated memroy for @buf.
* The size should be @num * size of security cam offset(0x20).
*
* Return RTW_HAL_STATUS_SUCCESS when function successfully works,
* otherwise, return RTW_HAL_STATUS_FAILURE.
*/
enum rtw_hal_status
rtw_hal_mac_get_sec_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
int i = 0;
/* ToDO: fix the magic number later */
u8 sec_cam_offset_sz = 0x20;
if (buf == NULL) {
/* to console */
for (i = 0; i < num; i++) {
PHL_INFO("======= SEC CAM (%d)DUMP =======\n", i);
mac_mem_dump(mac, MAC_AX_MEM_SECURITY_CAM, i*sec_cam_offset_sz\
, NULL, sec_cam_offset_sz, 0);
PHL_INFO("\n");
}
} else {
/* to buffer */
if (size < sec_cam_offset_sz*num) {
PHL_ERR("%s buf size is not enough to dump security cam\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
for (i = 0; i < num; i++)
mac_mem_dump(mac, MAC_AX_MEM_SECURITY_CAM, i*sec_cam_offset_sz\
, buf + (i*sec_cam_offset_sz), sec_cam_offset_sz, 1);
}
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_get_addr_cam() - get the address cam raw data from HW
* @hal_info: struct hal_info_t *
* @num: How many cam you wnat to dump from the first one.
* @buf: ptr to buffer which store the content from HW.
* If buf is NULL, use console as debug path.
* @size Size of allocated memroy for @buf.
* The size should be @num * size of Addr cam offset(0x40).
*
* Return RTW_HAL_STATUS_SUCCESS when function successfully works,
* otherwise, return RTW_HAL_STATUS_FAILURE.
*/
enum rtw_hal_status
rtw_hal_mac_get_addr_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
int i = 0;
/* ToDO: fix the magic number later */
u8 addr_cam_offset_sz = 0x40;
if (buf == NULL) {
/* to console */
for (i = 0; i < num; i++) {
PHL_INFO("======= ADDR CAM (%d)DUMP =======\n", i);
mac_mem_dump(mac, MAC_AX_MEM_ADDR_CAM, i*addr_cam_offset_sz\
, NULL, addr_cam_offset_sz, 0);
PHL_INFO("\n");
}
} else {
/* to buffer */
if (size < addr_cam_offset_sz*num) {
PHL_ERR("%s buf size is not enough to dump addr cam\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
for (i = 0; i < num; i++)
mac_mem_dump(mac, MAC_AX_MEM_ADDR_CAM, i*addr_cam_offset_sz\
, buf + (i*addr_cam_offset_sz), addr_cam_offset_sz, 1);
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_get_tsf(struct hal_info_t *hal, u8 *port,
u32 *tsf_h, u32 *tsf_l)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
struct mac_ax_port_tsf val = {0};
val.port = *port;
if (hal_mac_ops->get_hw_value(mac, MAC_AX_HW_GET_TSF, &val))
return RTW_HAL_STATUS_FAILURE;
*tsf_h = val.tsf_h;
*tsf_l = val.tsf_l;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_mac_cfg_txhci(struct hal_info_t *hal, u8 en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
enum mac_ax_func_sw mac_en;
u32 ret = 0;
if (en)
mac_en = MAC_AX_FUNC_EN;
else
mac_en = MAC_AX_FUNC_DIS;
ret = hal_mac_ops->intf_ops->ctrl_txhci(mac, mac_en);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS):(RTW_HAL_STATUS_FAILURE);
}
enum rtw_hal_status rtw_hal_mac_cfg_rxhci(struct hal_info_t *hal, u8 en)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_ops *hal_mac_ops = mac->ops;
enum mac_ax_func_sw mac_en;
u32 ret = 0;
if (en)
mac_en = MAC_AX_FUNC_EN;
else
mac_en = MAC_AX_FUNC_DIS;
ret = hal_mac_ops->intf_ops->ctrl_rxhci(mac, mac_en);
return (ret == MACSUCCESS) ?
(RTW_HAL_STATUS_SUCCESS):(RTW_HAL_STATUS_FAILURE);
}
#ifdef CONFIG_MCC_SUPPORT
void _hal_mac_mcc_fill_role_info(struct rtw_phl_mcc_role *mcc_role,
struct mac_ax_mcc_role *info)
{
struct rtw_phl_mcc_policy_info *policy = &mcc_role->policy;
if (mcc_role->bt_role) {
info->group = mcc_role->group;
info->btc_in_2g = true;
info->duration = policy->dur_info.dur;
} else {
info->macid = mcc_role->macid;
info->central_ch_seg0 = mcc_role->chandef->center_ch;
info->central_ch_seg1 = (u8)mcc_role->chandef->center_freq2;
info->primary_ch = mcc_role->chandef->chan;
info->bandwidth = mcc_role->chandef->bw;
info->group = mcc_role->group;
info->c2h_rpt = policy->c2h_rpt;
info->dis_tx_null = policy->dis_tx_null;
info->dis_sw_retry = policy->dis_sw_retry;
info->in_curr_ch = policy->in_curr_ch;
info->sw_retry_count = policy->sw_retry_count;
info->tx_null_early= policy->tx_null_early;
info->duration = policy->dur_info.dur;
info->courtesy_en = policy->courtesy_en;
info->courtesy_num = policy->courtesy_num;
info->courtesy_target = policy->courtesy_target;
}
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): macid(%d), central_ch_seg0(%d), central_ch_seg1(%d)\n",
info->macid, info->central_ch_seg0, info->central_ch_seg1);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): primary_ch(%d), bandwidth(%d), group(%d), c2h_rpt(%d)\n",
info->primary_ch, info->bandwidth, info->group, info->c2h_rpt);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): dis_tx_null(%d), dis_sw_retry(%d), in_curr_ch(%d)\n",
info->dis_tx_null, info->dis_sw_retry, info->in_curr_ch);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): sw_retry_count(%d), tx_null_early(%d), btc_in_2g(%d)\n",
info->sw_retry_count, info->tx_null_early, info->btc_in_2g);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): duration(%d)\n",
info->duration);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_role_info(): courtesy_en(%d), courtesy_num(%d), courtesy_target(0x%x)\n",
info->courtesy_en, info->courtesy_num, info->courtesy_target);
}
void _hal_mac_mcc_fill_duration_info(struct rtw_phl_mcc_en_info *en_info,
struct rtw_phl_mcc_bt_info *bt_info,
struct mac_ax_mcc_duration_info *info)
{
info->group = en_info->mcc_role[0].group;
info->btc_in_group = (bt_info->bt_dur > 0) ? 1 : 0;
info->start_macid = en_info->mcc_role[en_info->ref_role_idx].macid;
info->macid_x = en_info->mcc_role[0].macid;
info->macid_y = en_info->mcc_role[1].macid;
info->duration_x = en_info->mcc_role[0].policy.dur_info.dur;
info->duration_y = en_info->mcc_role[1].policy.dur_info.dur;
info->start_tsf_low = en_info->tsf_low;
info->start_tsf_high = en_info->tsf_high;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_duration_info(): info->group(%d), btc_in_group(%d), start_macid(%d), macid_x(%d), macid_y(%d)\n",
info->group, info->btc_in_group, info->start_macid,
info->macid_x, info->macid_y);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_duration_info(): duration_x(%d), duration_y(%d), start_tsf(0x%08x %08x)\n",
info->duration_x, info->duration_y, info->start_tsf_high,
info->start_tsf_low);
}
void _hal_mac_mcc_fill_start_info(u8 group, u8 macid, u32 tsf_high, u32 tsf_low,
u8 btc_in_group, u8 old_group_action, u8 old_group,
struct mac_ax_mcc_start *info)
{
info->group = group;
info->btc_in_group = btc_in_group;
info->old_group_action = old_group_action;
info->old_group = old_group;
info->macid = macid;
info->tsf_low = tsf_low;
info->tsf_high = tsf_high;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_hal_mac_mcc_fill_start_info(): info->group(%d), btc_in_group(%d), old_group_action(%d), old_group(%d), macid(%d), Tsf(0x%08x %08x)\n",
info->group, info->btc_in_group, info->old_group_action,
info->old_group, info->macid, info->tsf_high, info->tsf_low);
}
enum rtw_hal_status rtw_hal_mac_add_mcc(struct hal_info_t *hal,
struct rtw_phl_mcc_role *mcc_role)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
u16 loop_cnt = 0;
struct mac_ax_mcc_role info = {0};
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_add_mcc()\n");
if (mac == NULL)
goto exit;
_hal_mac_mcc_fill_role_info(mcc_role, &info);
mac_status = mac->ops->add_mcc(mac, &info);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_add_mcc(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_add_mcc_done(mac, (u8)info.group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_add_mcc(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_add_mcc(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_start_mcc(struct hal_info_t *hal,
u8 group, u8 macid, u32 tsf_high, u32 tsf_low,
u8 btc_in_group, u8 old_group_action, u8 old_group)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_mcc_start info = {0};
u32 mac_status = MACSUCCESS;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_start_mcc(): group(%d), macid(%d) Start tsf(0x%08X %08X), btc_in_group(%d)\n",
group, macid, tsf_high, tsf_low, btc_in_group);
if (mac == NULL)
goto exit;
_hal_mac_mcc_fill_start_info(group, macid, tsf_high, tsf_low,
btc_in_group, old_group_action,
old_group, &info);
mac_status = mac->ops->start_mcc(mac, &info);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_start_mcc(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_start_mcc_done(mac, group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_start_mcc(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_start_mcc(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_stop_mcc(struct hal_info_t *hal, u8 group,
u8 macid)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_stop_mcc(): group(%d), macid(%d)\n",
group, macid);
if (mac == NULL)
goto exit;
/*prev_groups always set to 1, driver stop all group pattern in the same hw band.*/
mac_status = mac->ops->stop_mcc(mac, group, macid, 1);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_stop_mcc(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_stop_mcc_done(mac, group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_stop_mcc(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_stop_mcc(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_del_mcc_group(struct hal_info_t *hal, u8 group)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_del_mcc_group(): group(%d)\n",
group);
if (mac == NULL)
goto exit;
/*prev_groups always set to 1, driver stop all group pattern in the same hw band.*/
mac_status = mac->ops->del_mcc_group(mac, group, 1);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_del_mcc_group(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_del_mcc_group_done(mac, group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_del_mcc_group(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_del_mcc_group(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_mcc_request_tsf(struct hal_info_t *hal,
u8 group, u8 macid_x, u8 macid_y)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_mcc_request_tsf(): group(%d), macid_x(%d), macid_y(%d)\n",
group, macid_x, macid_y);
if (mac == NULL)
goto exit;
mac_status = mac->ops->mcc_request_tsf(mac, group, macid_x, macid_y);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_request_tsf(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_mcc_request_tsf_done(mac, group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_mcc_request_tsf(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_request_tsf(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_mcc_macid_bitmap(struct hal_info_t *hal,
u8 group, u8 macid, u8 *bitmap, u8 len)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_mcc_macid_bitmap(): group(%d), macid(%d)\n",
group, macid);
if (mac == NULL)
goto exit;
mac_status = mac->ops->mcc_macid_bitmap(mac, group, macid, bitmap, len);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_macid_bitmap(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_mcc_macid_bitmap_done(mac, group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_mcc_macid_bitmap(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_mcc_macid_bitmap(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_mcc_sync_enable(struct hal_info_t *hal,
u8 group, u8 source, u8 target, u8 offset)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_mcc_sync_enable(): group(%d), source macid(%d), target macid(%d), offset(%d)\n",
group, source, target, offset);
if (mac == NULL)
goto exit;
mac_status = mac->ops->mcc_sync_enable(mac, group, source, target, offset);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "mac_mcc_sync_enable(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_mcc_sync_enable_done(mac, group) ==
MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "mac_mcc_sync_enable(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "mac_mcc_sync_enable(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_set_duration(struct hal_info_t *hal,
struct rtw_phl_mcc_en_info *en_info,
struct rtw_phl_mcc_bt_info *bt_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_mcc_duration_info info = {0};
u32 mac_status;
u16 loop_cnt = 0;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> rtw_hal_mac_set_duration()\n");
_hal_mac_mcc_fill_duration_info(en_info, bt_info, &info);
mac_status = mac->ops->mcc_set_duration(mac, &info);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_set_duration(): fault, status = %d.\n",
mac_status);
goto exit;
}
do {
if (mac->ops->check_mcc_set_duration_done(mac, (u8)info.group)
== MACSUCCESS)
break;
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
loop_cnt++;
} while (loop_cnt < POLLING_HALMAC_CNT);
if (loop_cnt < POLLING_HALMAC_CNT) {
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mac_set_duration(): polling ok, count(%d)\n",
loop_cnt);
hal_status = RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_set_duration(): polling timeout\n");
}
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_get_mcc_tsf_rpt(struct hal_info_t *hal,
u8 group, u32 *tsf_x_h, u32 *tsf_x_l,
u32 *tsf_y_h, u32 *tsf_y_l)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
if (mac == NULL)
goto exit;
mac_status = mac->ops->get_mcc_tsf_rpt(mac, group, tsf_x_h, tsf_x_l,
tsf_y_h, tsf_y_l);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_get_mcc_tsf_rpt(): fault, status = %d.\n",
mac_status);
goto exit;
}
hal_status = RTW_HAL_STATUS_SUCCESS;
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_get_mcc_status_rpt(struct hal_info_t *hal,
u8 group, u8 *status, u32 *tsf_h, u32 *tsf_l)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
if (mac == NULL)
goto exit;
mac_status = mac->ops->get_mcc_status_rpt(mac, group, status, tsf_h,
tsf_l);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "mac_mcc_sync_enable(): fault, status = %d.\n",
mac_status);
goto exit;
}
hal_status = RTW_HAL_STATUS_SUCCESS;
exit:
return hal_status;
}
enum rtw_hal_status rtw_hal_mac_get_mcc_group(struct hal_info_t *hal, u8 *group)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status;
if (mac == NULL)
goto exit;
mac_status = mac->ops->get_mcc_group(mac, group);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mac_get_mcc_group(): fault, status = %d.\n",
mac_status);
goto exit;
}
hal_status = RTW_HAL_STATUS_SUCCESS;
exit:
return hal_status;
}
#endif /* CONFIG_MCC_SUPPORT */
#ifdef CONFIG_PHL_P2PPS
#define P2P_ACT_INIT 0
#define P2P_ACT_UPDATE 1
#define P2P_ACT_REMOVE 2
#define P2P_ACT_TERMINATE 3
#define P2P_TYPE_GO 0
#define P2P_TYPE_GC 1
void _hal_mac_dump_p2p_act_struct(struct mac_ax_p2p_act_info *mac_p2p_info)
{
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): macid = %d\n",
mac_p2p_info->macid);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): noaid = %d\n",
mac_p2p_info->noaid);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): act = %d\n",
mac_p2p_info->act);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): type = %d\n",
mac_p2p_info->type);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): all_slep = %d\n",
mac_p2p_info->all_slep);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): srt = %x\n",
mac_p2p_info->srt);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): itvl = %d\n",
mac_p2p_info->itvl);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): dur = %d\n",
mac_p2p_info->dur);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): cnt = %d\n",
mac_p2p_info->cnt);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_dump_p2p_act_struct(): ctw = %d\n",
mac_p2p_info->ctw);
}
void _hal_mac_noa_fill_info(u8 action,
struct rtw_phl_noa_desc *desc,
u16 macid,
struct mac_ax_p2p_act_info *mac_p2p_info)
{
struct rtw_wifi_role_t *wrole = desc->w_role;
mac_p2p_info->macid = (u8)macid;
mac_p2p_info->noaid = desc->noa_id;
mac_p2p_info->act = action;
if (wrole->type == PHL_RTYPE_AP)
mac_p2p_info->type = P2P_TYPE_GO;
else if (wrole->type == PHL_RTYPE_STATION)
mac_p2p_info->type = P2P_TYPE_GC;
mac_p2p_info->srt = desc->start_t_l;
mac_p2p_info->itvl = desc->interval;
mac_p2p_info->dur = desc->duration;
mac_p2p_info->cnt = desc->count;
}
enum rtw_hal_status _hal_mac_get_p2p_stat(struct hal_info_t *hal)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
u16 loop_cnt;
u32 m_stat;
for (loop_cnt = 0; loop_cnt < POLLING_HALMAC_CNT; loop_cnt++) {
m_stat = mac->ops->get_p2p_stat(mac) ;
if (m_stat == MACSUCCESS) {
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]_hal_mac_get_p2p_stat(): polling ok, count(%d)\n",
loop_cnt);
return RTW_HAL_STATUS_SUCCESS;
} else if (m_stat == MACP2PSTFAIL) {
PHL_TRACE(COMP_PHL_P2PPS, _PHL_ERR_, "[NoA]_hal_mac_get_p2p_stat(): polling error, count(%d)\n",
loop_cnt);
return RTW_HAL_STATUS_FAILURE;
}
_os_sleep_ms(hal_to_drvpriv(hal), POLLING_HALMAC_TIME);
}
PHL_TRACE(COMP_PHL_P2PPS, _PHL_ERR_, "[NoA]_hal_mac_get_p2p_stat(): polling timeout!\n");
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status _hal_mac_set_p2p_act(struct hal_info_t *hal,
struct mac_ax_p2p_act_info *mac_p2p_info)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 m_stat;
m_stat = mac->ops->p2p_act_h2c(mac, mac_p2p_info);
if (m_stat != MACSUCCESS) {
PHL_TRACE(COMP_PHL_P2PPS, _PHL_ERR_, "[NoA]_hal_mac_set_noa_act(): Fault, status = %d, Action = %d\n",
m_stat, mac_p2p_info->act);
return RTW_HAL_STATUS_MAC_API_FAILURE;
}
h_stat = _hal_mac_get_p2p_stat(hal);
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_noa_init(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_p2p_act_info mac_p2p_info = {0};
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_init()\n");
_hal_mac_noa_fill_info(P2P_ACT_INIT, in_desc, macid, &mac_p2p_info);
_hal_mac_dump_p2p_act_struct(&mac_p2p_info);
h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info);
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_noa_update(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_p2p_act_info mac_p2p_info = {0};
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_update()\n");
_hal_mac_noa_fill_info(P2P_ACT_UPDATE, in_desc, macid, &mac_p2p_info);
_hal_mac_dump_p2p_act_struct(&mac_p2p_info);
h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info);
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_noa_remove(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_p2p_act_info mac_p2p_info = {0};
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_remove()\n");
_hal_mac_noa_fill_info(P2P_ACT_REMOVE, in_desc, macid, &mac_p2p_info);
_hal_mac_dump_p2p_act_struct(&mac_p2p_info);
h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info);
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_noa_terminate(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_p2p_act_info mac_p2p_info = {0};
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_noa_terminate()\n");
_hal_mac_noa_fill_info(P2P_ACT_TERMINATE, in_desc, macid, &mac_p2p_info);
_hal_mac_dump_p2p_act_struct(&mac_p2p_info);
h_stat = _hal_mac_set_p2p_act(hal, &mac_p2p_info);
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_tsf32_tog_enable(struct hal_info_t *hal,
u8 hw_band,
u8 port,
u16 early)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_t32_togl_info mac_t32_tog_info = {0};
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 m_stat;
mac_t32_tog_info.band = hw_band;
mac_t32_tog_info.port = port;
mac_t32_tog_info.en = true;
mac_t32_tog_info.early = early;
m_stat = mac->ops->tsf32_togl_h2c(mac, &mac_t32_tog_info);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_tsf32_tog_enable() m_stat = %d\n",
m_stat);
if(m_stat == MACSUCCESS)
h_stat = RTW_HAL_STATUS_SUCCESS;
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_tsf32_tog_disable(struct hal_info_t *hal,
u8 hw_band,
u8 port)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct mac_ax_t32_togl_info mac_t32_tog_info = {0};
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 m_stat;
mac_t32_tog_info.band = hw_band;
mac_t32_tog_info.port = port;
mac_t32_tog_info.en = false;
m_stat = mac->ops->tsf32_togl_h2c(mac, &mac_t32_tog_info);
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_tsf32_tog_disable() m_stat = %d\n",
m_stat);
if(m_stat == MACSUCCESS)
h_stat = RTW_HAL_STATUS_SUCCESS;
return h_stat;
}
enum rtw_hal_status rtw_hal_mac_get_tsf32_tog_rpt(struct hal_info_t *hal,
struct rtw_phl_tsf32_tog_rpt *rpt)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_t32_togl_rpt m_rpt = {0};
u32 m_stat = 0;
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_get_tsf32_tog_rpt()\n");
m_stat = mac->ops->get_t32_togl_rpt(mac, &m_rpt);
if (m_stat != MACSUCCESS) {
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]rtw_hal_mac_get_tsf32_tog_rpt() MAC FAIL(%d)!\n",
m_stat);
return RTW_HAL_STATUS_FAILURE;
}
rpt->band = m_rpt.band;
rpt->port = m_rpt.port;
rpt->valid = m_rpt.valid;
rpt->early = m_rpt.early;
rpt->status = m_rpt.status;
rpt->tsf_l = m_rpt.tsf_l;
rpt->tsf_h = m_rpt.tsf_h;
return RTW_HAL_STATUS_SUCCESS;
}
#endif
void rtw_hal_mac_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
u8 band)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
mac->ops->event_notify(mac, event, band);
}
void rtw_hal_mac_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
u8 band)
{
/*todo*/
}
enum rtw_hal_status
rtw_hal_mac_trigger_fw_conflict(struct hal_info_t *hal_info, u32 addr, u8 vol)
{
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 i = 0;
u32 convert_mask = 0xffffffff;
u32 val;
/* Switch voltage */
mac->ops->set_hw_value(mac, MAC_AX_HW_SET_CORE_SWR_VOLT, &vol);
/* Trigger method: H2C Halt */
hal_ops->write_macreg(hal_info, 0x168, convert_mask, 0x5dc0007);
hal_ops->write_macreg(hal_info, 0x160, convert_mask, 0x1);
/* loop read reg */
for(i = 0; i<1000; i++){
val = hal_ops->read_macreg(hal_info,
addr,
convert_mask);
PHL_INFO("%s: voltag %d count %d io_value = %x\n", __FUNCTION__,vol, i, val);
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_set_gpio_func(struct rtw_hal_com_t *hal_com, u8 func, s8 gpio_cfg){
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
struct mac_ax_ops *ops = mac->ops;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
ret = ops->set_gpio_func(mac, func, gpio_cfg);
if (ret != MACSUCCESS)
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "Set GPIO failure, status = %d\n", ret);
return ret;
}
enum rtw_hal_status
rtw_hal_mac_bfee_set_vht_gid(struct hal_info_t *hal,
u8 band, struct rtw_phl_gid_pos_tbl *tbl)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct mac_gid_pos gid_pos = {0};
struct mac_ax_adapter *mac = hal_to_mac(hal);
u32 mac_status = 0;
u8 i = 0;
gid_pos.band = band;
/* For GID 0~31 */
for (i = 0; i < 4; i++) {
gid_pos.gid_tab[0] |= (tbl->gid_vld[i] << (i << 3));
}
for (i = 0; i < 8; i++) {
if (i < 4)
gid_pos.user_pos[0] |= (tbl->pos[i] << (i << 3));
else
gid_pos.user_pos[1] |= (tbl->pos[i] << ((i - 4) << 3));
}
/* For GID 32~64 */
for (i = 4; i < 8; i++) {
gid_pos.gid_tab[1] |= (tbl->gid_vld[i] << ((i - 4) << 3));
}
for (i = 8; i < 16; i++) {
if (i < 12)
gid_pos.user_pos[2] |= (tbl->pos[i] << ((i - 8) << 3));
else
gid_pos.user_pos[3] |= (tbl->pos[i] << ((i - 12) << 3));
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s() : Set VHT GID for band %d;\n",
__func__, band);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s() : band %d ; gid tbl 0x%x 0x%x;\n",
__func__, band,
gid_pos.gid_tab[0], gid_pos.gid_tab[1]);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s() : user position 0x%x 0x%x 0x%x 0x%x;\n",
__func__,
gid_pos.user_pos[0], gid_pos.user_pos[1],
gid_pos.user_pos[2], gid_pos.user_pos[3]);
mac_status = mac->ops->gidpos(mac, &gid_pos);
if (mac_status != MACSUCCESS) {
hal_status = RTW_HAL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n",
__func__, mac_status);
}
return hal_status;
}
/* acq_val/mgq_val , input unit : us */
enum rtw_hal_status
rtw_hal_mac_set_tx_lifetime(struct hal_info_t *hal, enum phl_band_idx band,
bool acq_en, bool mgq_en, u16 acq_val, u16 mgq_val)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_lifetime_cfg cfg = {0};
u32 mac_status = 0;
u16 tmp = 0;
#define HAL_MAC_TX_LIFETIME_UNIT_US_SHT 8 /* 256 us */
if (HW_BAND_1 == band)
cfg.band = 1;
else
cfg.band = 0;
if(true == acq_en) {
cfg.en.acq_en = 1;
tmp = acq_val >> HAL_MAC_TX_LIFETIME_UNIT_US_SHT;
cfg.val.acq_val_1 = tmp;
cfg.val.acq_val_2 = tmp;
cfg.val.acq_val_3 = tmp;
cfg.val.acq_val_4 = tmp;
}
if (true == mgq_en) {
cfg.en.mgq_en = 1;
tmp = mgq_val >> HAL_MAC_TX_LIFETIME_UNIT_US_SHT;
cfg.val.mgq_val = tmp;
}
mac_status = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_LIFETIME_CFG, (void *)&cfg);
if (mac_status != MACSUCCESS) {
hal_status = RTW_HAL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n",
__func__, mac_status);
}
return hal_status;
}
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
enum rtw_hal_status rtw_hal_mac_add_cmd_ofld(struct rtw_hal_com_t *hal_com, struct rtw_mac_cmd *cmd)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u32 mac_status;
if (mac == NULL)
goto exit;
mac_status = mac->ops->add_cmd_ofld(mac, cmd);
if (mac_status != MACSUCCESS) {
PHL_TRACE(COMP_PHL_MAC, _PHL_ERR_, "%s(): fault, status = %d.\n",
__func__, mac_status);
goto exit;
}
hal_status = RTW_HAL_STATUS_SUCCESS;
exit:
return hal_status;
}
#endif
enum rtw_hal_status rtw_hal_mac_set_hw_rts_th(struct hal_info_t *hal, u8 band,
u16 time_th, u16 len_th)
{
struct mac_ax_adapter *mac = hal_to_mac(hal);
struct mac_ax_hw_rts_th hw_rts_th = {0};
u32 mac_err;
PHL_INFO("%s\n", __func__);
_os_mem_set(hal_to_drvpriv(hal), &hw_rts_th, 0, sizeof(hw_rts_th));
hw_rts_th.band = band;
hw_rts_th.time_th = time_th;
hw_rts_th.len_th = len_th;
mac_err = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_HW_RTS_TH,
&hw_rts_th);
if (mac_err != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, mac_err);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
u8 rtw_hal_mac_get_efuse_ver_len(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
return mac->hw_info->efuse_version_size;
}
enum rtw_hal_status
rtw_hal_mac_set_dfs_tb_ctrl(struct hal_info_t *hal_info, u8 set)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
u8 dis_ru_26 = 0;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
if (set)
dis_ru_26 = 1;
ret = mac->ops->set_hw_value(mac, MAC_AX_HW_SET_TX_RU26_TB, &dis_ru_26);
if (ret != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, ret);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_mac_patch_rx_rate(struct hal_info_t *hal_info, struct rtw_r_meta_data *mdata)
{
struct mac_ax_adapter *mac = hal_to_mac(hal_info);
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
ret = mac->ops->patch_rx_rate(mac, mdata);
if (ret != MACSUCCESS) {
PHL_ERR("%s : mac status %d.\n", __func__, ret);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_mac_set_tx_duty() - Set tx pause/un-pause interval
* @hal_info: struct hal_info_t*
* @pause_interval: tx pause interval (ms)
* @tx_interval: tx interval (ms)
*
* Return RTW_HAL_STATUS_SUCCESS when operation success.
*/
enum rtw_hal_status
rtw_hal_mac_set_tx_duty(struct hal_info_t *hal_info,
u16 pause_interval,
u16 tx_interval)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 mac_status = 0;
mac_status = mac->ops->tx_duty(mac, pause_interval, tx_interval);
if (mac_status != MACSUCCESS) {
hal_status = RTW_HAL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n",
__func__, mac_status);
}
return hal_status;
}
/**
* rtw_hal_mac_stop_tx_duty() - Stop previous tx duty config
* @hal_info: struct hal_info_t*
*
* Return RTW_HAL_STATUS_SUCCESS when operation success.
*/
enum rtw_hal_status
rtw_hal_mac_stop_tx_duty(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct mac_ax_adapter *mac = (struct mac_ax_adapter *)hal_info->mac;
u32 mac_status = 0;
mac_status = mac->ops->tx_duty_stop(mac);
if (mac_status != MACSUCCESS) {
hal_status = RTW_HAL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s() : fail, status = %d.\n",
__func__, mac_status);
}
return hal_status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_mac.c
|
C
|
agpl-3.0
| 265,208
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_MAC_H_
#define _HAL_API_MAC_H_
#include "mac/mac_ax.h"
#define POLLING_HALMAC_TIME 5
#define POLLING_HALMAC_CNT 100
#define hal_to_mac(_halinfo) ((struct mac_ax_adapter *)((_halinfo)->mac))
#ifdef CONFIG_SDIO_HCI
u8 hal_mac_sdio_read8(struct rtw_hal_com_t *hal, u32 addr);
u16 hal_mac_sdio_read16(struct rtw_hal_com_t *hal, u32 addr);
u32 hal_mac_sdio_read32(struct rtw_hal_com_t *hal, u32 addr);
int hal_mac_sdio_write8(struct rtw_hal_com_t *hal, u32 addr, u8 value);
int hal_mac_sdio_write16(struct rtw_hal_com_t *hal, u32 addr, u16 value);
int hal_mac_sdio_write32(struct rtw_hal_com_t *hal, u32 addr, u32 value);
void hal_mac_sdio_read_mem(struct rtw_hal_com_t *hal,
u32 addr, u32 cnt, u8 *pmem);
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 hal_mac_sdio_iread8(struct rtw_hal_com_t *hal, u32 addr);
u16 hal_mac_sdio_iread16(struct rtw_hal_com_t *hal, u32 addr);
u32 hal_mac_sdio_iread32(struct rtw_hal_com_t *hal, u32 addr);
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
void rtw_hal_mac_get_version(char *ver_str, u16 len);
void rtw_hal_mac_get_fw_ver(struct hal_info_t *hal_info, char *ver_str, u16 len);
u16 hal_mac_get_macid_num(struct hal_info_t *hal);
void hal_mac_get_hwinfo(struct hal_info_t *hal, struct hal_spec_t *hal_spec);
#ifdef DBG_PHL_MAC_REG_RW
bool rtw_hal_mac_reg_chk(struct rtw_hal_com_t *hal_com, u32 addr);
#endif
u32 rtw_hal_mac_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
u32 rtw_hal_mac_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
bool rtw_hal_mac_proc_cmd(struct hal_info_t *hal_info, struct rtw_proc_cmd *incmd,
char *output, u32 out_len);
enum rtw_hal_status rtw_hal_mac_get_pwr_state(struct hal_info_t *hal_info,
enum rtw_mac_pwr_st *pwr_state);
enum rtw_hal_status rtw_hal_mac_power_switch(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
u8 on_off);
enum rtw_hal_status rtw_hal_mac_dbcc_pre_cfg(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
u8 dbcc_en);
enum rtw_hal_status rtw_hal_mac_dbcc_cfg(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
u8 dbcc_en);
enum rtw_hal_status
rtw_hal_mac_poll_hw_tx_done(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_hw_tx_resume(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_poll_hw_rx_done(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_hw_rx_resume(struct hal_info_t *hal_info);
#ifdef CONFIG_PCI_HCI
enum rtw_hal_status rtw_hal_mac_set_pcicfg(struct hal_info_t *hal_info,
struct mac_ax_pcie_cfgspc_param *pci_cfgspc);
enum rtw_hal_status rtw_hal_mac_ltr_set_pcie(struct hal_info_t *hal_info,
enum rtw_pcie_bus_func_cap_t hw_ctrl,
u8 idle_ctrl, u32 idle_val, u8 act_ctrl, u32 act_val);
enum rtw_hal_status rtw_hal_mac_ltr_sw_trigger(struct hal_info_t *hal_info, enum rtw_pcie_ltr_state state);
enum rtw_hal_status hal_mac_set_l2_leave(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_mac_poll_txdma_idle(struct hal_info_t *hal,
struct mac_ax_txdma_ch_map *ch_map);
enum rtw_hal_status rtw_hal_mac_poll_rxdma_idle(struct hal_info_t *hal,
struct mac_ax_rxdma_ch_map *ch_map);
enum rtw_hal_status rtw_hal_mac_clr_bdidx(struct hal_info_t *hal);
enum rtw_hal_status rtw_hal_mac_rst_bdram(struct hal_info_t *hal);
enum rtw_hal_status rtw_hal_mac_cfg_txdma(struct hal_info_t *hal,
struct mac_ax_txdma_ch_map *ch_map);
enum rtw_hal_status rtw_hal_mac_cfg_dma_io(struct hal_info_t *hal, u8 en);
#endif
#ifdef CONFIG_USB_HCI
u8 hal_mac_get_bulkout_id(struct hal_info_t *hal, u8 ch_dma, u8 mode);
u32 hal_mac_usb_tx_agg_cfg(struct hal_info_t *hal, u8* wd_buf, u8 agg_num);
u32 hal_mac_usb_rx_agg_cfg(struct hal_info_t *hal, u8 agg_mode,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num);
u8 hal_mac_usb_get_max_bulkout_wd_num(struct hal_info_t *hal);
enum rtw_hal_status hal_mac_force_usb_switch(struct hal_info_t *hal);
u32 hal_mac_get_cur_usb_mode(struct hal_info_t *hal);
u32 hal_mac_get_usb_support_ability(struct hal_info_t *hal);
#endif
#ifdef CONFIG_SDIO_HCI
void rtw_hal_mac_sdio_cfg(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info, struct rtw_ic_info *ic_info);
void rtw_hal_mac_sdio_tx_cfg(struct rtw_hal_com_t *hal);
void rtw_hal_mac_sdio_rx_agg_cfg(struct rtw_hal_com_t *hal, bool enable,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num);
bool rtw_hal_mac_sdio_check_tx_allow(struct rtw_hal_com_t *hal, u8 dma_ch,
u8 *buf, u32 len, u8 agg_count,
u16 *pkt_len, u8 *wp_offset, u32 *txaddr,
u32 *txlen);
int rtw_hal_mac_sdio_parse_rx(struct rtw_hal_com_t *hal,
struct rtw_rx_buf *rxbuf);
int rtw_hal_mac_sdio_rx(struct rtw_hal_com_t *hal,
struct rtw_rx_buf *rxbuf);
#endif
struct hal_init_info_t {
struct mac_ax_trx_info trx_info;
struct mac_ax_intf_info intf_info;
char *ic_name;
};
enum rtw_hal_status
rtw_hal_mac_init_mac(void *mac, struct hal_init_info_t *init_info);
enum rtw_hal_status
rtw_hal_mac_trx_init(void *mac, struct hal_init_info_t *init_info);
enum rtw_hal_status
rtw_hal_mac_hal_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info);
enum rtw_hal_status
rtw_hal_mac_hal_fast_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info,
struct hal_init_info_t *init_info);
enum rtw_hal_status
rtw_hal_mac_hal_deinit(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_mac_chk_allq_empty(struct hal_info_t *hal_info, u8 *empty);
#ifdef CONFIG_WOWLAN
enum rtw_hal_status
rtw_hal_mac_cfg_wow_sleep(struct hal_info_t *hal_info, u8 sleep);
enum rtw_hal_status
rtw_hal_mac_get_wow_fw_status(struct hal_info_t *hal_info, u8 *status, u8 func_en);
enum rtw_hal_status
rtw_hal_mac_cfg_wow_wake(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_wow_wake_info *info);
enum rtw_hal_status
rtw_hal_mac_cfg_disc_dec(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_disc_det_info *info);
enum rtw_hal_status
rtw_hal_mac_cfg_dev2hst_gpio(struct hal_info_t *hal_info, u8 en, struct rtw_wow_gpio_info *cfg);
enum rtw_hal_status
rtw_hal_mac_cfg_keep_alive(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_keep_alive_info *info);
enum rtw_hal_status
rtw_hal_mac_cfg_ndp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_ndp_ofld_info *cfg);
enum rtw_hal_status
rtw_hal_mac_cfg_arp_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_arp_ofld_info *cfg);
enum rtw_hal_status
rtw_hal_mac_cfg_gtk_ofld(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_gtk_ofld_info *cfg);
enum rtw_hal_status
rtw_hal_mac_cfg_realwow(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_realwow_info *cfg);
enum rtw_hal_status rtw_hal_mac_get_wake_rsn(struct hal_info_t *hal_info, u8 *wake_rsn, u8 *reset);
enum rtw_hal_status
rtw_hal_mac_cfg_wow_cam(struct hal_info_t *hal_info, u16 macid, u8 en, struct rtw_pattern_match_info *cfg);
enum rtw_hal_status
rtw_hal_mac_get_aoac_rpt(struct hal_info_t *hal_info, struct rtw_aoac_report *aoac_info, u8 rx_ready);
enum rtw_hal_status rtw_hal_mac_set_wowlan(struct hal_info_t *hal, u8 enter);
enum rtw_hal_status rtw_hal_mac_wow_chk_txq_empty(struct hal_info_t *hal, u8 *empty);
enum rtw_hal_status rtw_hal_mac_wow_wde_drop(struct hal_info_t *hal, u8 band);
#endif /* CONFIG_WOWLAN */
enum rtw_hal_status
rtw_hal_mac_ax_fill_txdesc(void *mac, struct rtw_xmit_req *treq,
u8 *wd_buf, u32 *wd_len);
enum rtw_hal_status
rtw_hal_mac_enable_cpu(struct hal_info_t *hal_info, u8 reason, u8 dlfw);
enum rtw_hal_status
rtw_hal_mac_disable_cpu(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_romdl(struct hal_info_t *hal_info, u8 *rom_buf, u32 rom_size);
enum rtw_hal_status
rtw_hal_mac_fwdl(struct hal_info_t *hal_info, u8 *fw_buf, u32 fw_size);
enum rtw_hal_status
rtw_hal_mac_enable_fw(struct hal_info_t *hal_info, u8 fw_type);
enum rtw_hal_status
rtw_hal_mac_set_hw_ampdu_cfg(struct hal_info_t *hal_info, u8 band,
u16 max_agg_num, u8 max_agg_time);
enum rtw_hal_status rtw_hal_dmc_tbl_cfg(struct hal_info_t *hal_info,
struct mac_ax_dctl_info *dctl_info,
struct mac_ax_dctl_info *dctl_info_mask,
u16 macid);
enum rtw_hal_status rtw_hal_cmc_tbl_cfg(struct hal_info_t *hal_info,
struct mac_ax_cctl_info *cctl_info,
struct mac_ax_cctl_info *cctl_info_mask,
u16 macid);
enum rtw_hal_status rtw_hal_bacam_cfg(struct hal_info_t *hal_info,
struct mac_ax_bacam_info *ba_cam);
enum rtw_hal_status
rtw_hal_mac_port_init(struct hal_info_t *hal_info,
struct rtw_wifi_role_t *wifi_role);
enum rtw_hal_status
rtw_hal_mac_port_cfg(struct hal_info_t *hal_info,
struct rtw_wifi_role_t *wifi_role,
enum pcfg_type type, void *param);
enum rtw_hal_status
rtw_hal_mac_addr_cam_add_entry(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_mac_addr_cam_change_entry(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta,
enum phl_upd_mode mode,
bool is_connect);
enum rtw_hal_status
rtw_hal_mac_addr_cam_del_entry(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_mac_add_key(struct hal_info_t *hal_info, u8 macid, u8 type, u8 ext_key,
u8 spp, u8 keyid, u8 keytype, u8 *keybuf);
enum rtw_hal_status
rtw_hal_mac_delete_key(struct hal_info_t *hal_info, u8 macid, u8 type,
u8 ext_key, u8 spp, u8 keyid, u8 keytype);
u32
rtw_hal_mac_search_key_idx(struct hal_info_t *hal_info, u8 macid, u8 keyid, u8 keytype);
u32
rtw_hal_mac_ser_reset_wdt_intr(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_ser_get_error_status(struct hal_info_t *hal_info, u32 *err);
enum rtw_hal_status
rtw_hal_mac_ser_set_error_status(struct hal_info_t *hal_info, enum RTW_PHL_SER_RCVY_STEP err);
enum rtw_hal_status
rtw_hal_mac_trigger_cmac_err(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_trigger_dmac_err(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_lv1_rcvy(struct hal_info_t *hal_info, enum rtw_phl_ser_lv1_recv_step step);
enum rtw_hal_status rtw_hal_mac_ser_ctrl(struct hal_info_t *hal_info, bool en);
enum rtw_hal_status
rtw_hal_mac_dump_fw_rsvd_ple(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_set_bw(struct hal_info_t *hal_info, u8 band_idx, u8 pri_ch,
u8 central_ch_seg0, u8 central_ch_seg1, enum band_type band, enum channel_width bw);
enum rtw_hal_status
rtw_hal_mac_ax_set_bf_entry(void *mac, u8 band, u8 macid,
u8 bfee_idx, u16 txbf_idx, u16 buffer_idx);
enum rtw_hal_status
rtw_hal_mac_ax_get_snd_sts(void *mac, u8 band, u8 bfee_idx);
enum rtw_hal_status
rtw_hal_mac_ax_bfee_para_reg(void *mac, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_mac_ax_bfee_para_cctl(void *mac, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_mac_bfee_set_vht_gid(struct hal_info_t *hal,
u8 band, struct rtw_phl_gid_pos_tbl *tbl);
enum rtw_hal_status
rtw_hal_mac_ax_hw_snd_control(void *mac, u8 band, u8 hw_snd_ctrl);
enum rtw_hal_status
rtw_hal_mac_ax_mu_sta_upd(void *mac, u8 macid, u8 bfmu_idx,
enum rtw_hal_protection_type prot_type,
enum rtw_hal_ack_resp_type resp_type, u8 mugrp_bm);
enum rtw_hal_status
rtw_hal_mac_ax_mu_decision_para(void *mac, u32 mu_thold,
bool bypass_thold, bool bypass_tp);
enum rtw_hal_status
rtw_hal_mac_ax_set_mu_fix_mode(
void *mac, u8 gid, enum rtw_hal_protection_type prot_type,
enum rtw_hal_ack_resp_type resp_type,
bool fix_mu, bool he, bool fix_resp, bool fix_prot);
enum rtw_hal_status
rtw_hal_mac_ax_set_mu_table_whole(void *mac, void *hal_score_tbl);
enum rtw_hal_status
rtw_hal_mac_ax_snd_fx_cmd(void *mac, u8 *cmd_buf);
enum rtw_hal_status
rtw_hal_mac_parse_c2h(void *hal, u8 *buf, u32 buf_len, void *c2h);
enum rtw_hal_status
rtw_hal_mac_ax_parse_ppdu_sts(void *hal, u8 mac_valid, u8 *buf, u16 buf_l,
void *ppdu_sts, void *rx_mdata);
enum rtw_hal_status
rtw_hal_hdr_conv_cfg(struct hal_info_t *hal_info, u8 en_hdr_conv);
enum rtw_hal_status
rtw_hal_mac_enable_bb_rf(struct hal_info_t *hal_info, u8 enable);
#ifdef RTW_PHL_BCN
enum rtw_hal_status
hal_mac_ax_config_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
enum rtw_hal_status
hal_mac_ax_send_beacon(struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
#endif
enum rtw_hal_status
rtw_hal_mac_ppdu_stat_cfg(struct hal_info_t *hal_info,
u8 band_idx, bool ppdu_stat_en,
u8 appen_info, u8 filter);
enum rtw_hal_status rtw_hal_mac_config_hw_mgnt_sec( struct hal_info_t *hal_info, u8 en);
enum rtw_hal_status rtw_hal_mac_get_append_fcs(struct hal_info_t *hal_info, u8 *val);
enum rtw_hal_status rtw_hal_mac_get_acpt_icv_err(struct hal_info_t *hal_info, u8 *val);
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status
rtw_hal_mac_chan_info_cfg(struct hal_info_t *hal_info,
bool chinfo_en, u8 macid,
u8 mode, u8 filter, u8 sg_size);
#endif
void rtw_hal_mac_dbg_status_dump(struct hal_info_t *hal, struct hal_mac_dbg_dump_cfg *cfg);
#ifdef CONFIG_PHL_DFS
enum rtw_hal_status
rtw_hal_mac_dfs_rpt_cfg(struct hal_info_t *hal_info,
bool rpt_en, u8 rpt_num, u8 rpt_to);
enum rtw_hal_status
rtw_hal_mac_parse_dfs(struct hal_info_t *hal_info,
u8 *buf, u32 buf_len, struct mac_ax_dfs_rpt *dfs_rpt);
#endif /*CONFIG_PHL_DFS*/
u32
rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig);
enum rtw_hal_status
rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel,
u32 *addr_start, u32 *addr_end);
enum rtw_hal_status
rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en,
u8 restart_en, u8 timeout_en, u8 timeout_val,
u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val);
enum rtw_hal_status
rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state,
u16 *la_finish_addr, bool *la_round_up,
bool *la_loss_data);
void
rtl_hal_dump_sec_cam_tbl(struct rtw_hal_com_t *hal_com);
enum rtw_hal_status
rtw_hal_mac_set_rxfltr_by_mode(struct rtw_hal_com_t *hal_com, u8 band,
enum rtw_rx_fltr_mode mode);
enum rtw_hal_status
rtw_hal_mac_set_rxfltr_acpt_crc_err(struct rtw_hal_com_t *hal_com,
u8 band, u8 enable);
enum rtw_hal_status
rtw_hal_mac_set_rxfltr_mpdu_size(struct rtw_hal_com_t *hal_com,
u8 band, u16 size);
enum rtw_hal_status
rtw_hal_mac_set_rxfltr_by_type(struct rtw_hal_com_t *hal_com, u8 band,
u8 type, u8 target);
enum rtw_hal_status
rtw_hal_mac_set_rxfltr_by_subtype(struct rtw_hal_com_t *hal_com, u8 band,
u8 type, u8 subtype, u8 target);
enum rtw_hal_status
rtw_hal_mac_fw_log_cfg(struct rtw_hal_com_t *hal_com,
struct rtw_hal_fw_log_cfg *fl_cfg);
enum rtw_hal_status rtw_hal_set_macid_pause(void *hinfo,
u16 macid,
bool pause);
void
rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr,
u8 *buf, u32 len, u32 dbg_path);
enum rtw_hal_status rtw_hal_mac_pkt_ofld(struct hal_info_t *hal, u8 *id, u8 op,
u8 *pkt, u16 *len);
enum rtw_hal_status rtw_hal_mac_pkt_update_ids(struct hal_info_t *hal,
struct pkt_ofld_entry *entry);
enum rtw_hal_status rtw_hal_mac_reset_pkt_ofld_state(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_mac_set_edca(struct rtw_hal_com_t *hal_com,
u8 band,
u8 wmm,
u8 ac,
u32 param);
enum rtw_hal_status
rtw_hal_mac_get_ampdu_cfg(struct rtw_hal_com_t *hal_com,
u8 band,
struct mac_ax_ampdu_cfg *cfg);
enum rtw_hal_status
rtw_hal_mac_set_rty_lmt(struct rtw_hal_com_t *hal_com, u8 macid,
u8 rts_lmt_sel, u8 rts_lmt_val, u8 data_lmt_sel, u8 data_lmt_val);
enum rtw_hal_status
rtw_hal_mac_is_tx_mgnt_empty(struct hal_info_t *hal_info, u8 band, u8 *st);
enum rtw_hal_status
rtw_hal_mac_fw_dbg_dump(struct hal_info_t *hal_info, u8 is_low_pwr);
enum rtw_hal_status
rtw_hal_mac_req_pwr_state(struct hal_info_t *hal_info, u8 pwr_state);
enum rtw_hal_status
rtw_hal_mac_chk_pwr_state(struct hal_info_t *hal_info, u8 pwr_state, u32 *mac_sts);
enum rtw_hal_status
rtw_hal_mac_lps_cfg(struct hal_info_t *hal_info,
struct rtw_hal_lps_info *lps_info);
enum rtw_hal_status
rtw_hal_mac_lps_chk_leave(struct hal_info_t *hal_info, u16 macid, u32 *mac_sts);
enum rtw_hal_status
rtw_hal_mac_lps_chk_access(struct hal_info_t *hal_info, u32 offset);
enum rtw_hal_status
hal_mac_ax_send_fw_snd(struct hal_info_t *hal_info,
struct hal_ax_fwcmd_snd *hal_cmd);
enum rtw_hal_status
rtw_hal_mac_tx_mode_sel(struct hal_info_t *hal_info, u8 fw_tx, u8 txop_wmm_en_bm);
enum rtw_hal_status
rtw_hal_mac_get_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx, u8 type_idx, u32 *ret_value);
enum rtw_hal_status
rtw_hal_mac_set_reset_rx_cnt(struct hal_info_t *hal_info, u8 cur_phy_idx);
#ifdef CONFIG_PHL_TWT
enum rtw_hal_status
rtw_hal_mac_twt_info_update(void *hal, struct rtw_phl_twt_info twt_info, struct rtw_wifi_role_t *role, u8 action);
enum rtw_hal_status
rtw_hal_mac_twt_sta_update(void *hal, u8 macid, u8 twt_id, u8 action);
enum rtw_hal_status
rtw_hal_mac_twt_sta_announce(void *hal, u8 macid);
#endif /* CONFIG_PHL_TWT */
enum rtw_hal_status
rtw_hal_mac_ax_bfee_set_csi_rrsc(void *mac, u8 band, u32 rrsc);
u32 rtw_hal_mac_process_c2h(void *hal, struct rtw_c2h_info *c2h);
enum rtw_hal_status
rtw_hal_mac_f2p_test_cmd(struct hal_info_t *hal_info,
struct mp_mac_ax_f2p_test_para *info,
struct mp_mac_ax_f2p_wd *f2pwd,
struct mp_mac_ax_f2p_tx_cmd *ptxcmd,
u8 *psigb_addr);
enum rtw_hal_status
rtw_hal_mac_set_mu_edca(struct rtw_hal_com_t *hal_com, u8 band, u8 ac,
u16 timer, u8 cw_min, u8 cw_max, u8 aifs);
enum rtw_hal_status
rtw_hal_mac_set_mu_edca_ctrl(struct rtw_hal_com_t *hal_com,
u8 band, u8 wmm, u8 set);
enum rtw_hal_status rtw_hal_mac_led_set_ctrl_mode(struct hal_info_t *hal_info,
enum mac_ax_led_mode mode,
u8 led_id);
enum rtw_hal_status rtw_hal_mac_led_ctrl(struct hal_info_t *hal_info, u8 high,
u8 led_id);
enum rtw_hal_status rtw_hal_mac_sw_gpio_ctrl(struct hal_info_t *hal_info, u8 high,
u8 gpio);
enum rtw_hal_status rtw_hal_mac_set_sw_gpio_mode(struct hal_info_t *hal_info, enum rtw_gpio_mode mode,
u8 gpio);
enum rtw_hal_status
rtw_hal_mac_pcie_trx_mit(struct hal_info_t *hal_info,
struct mac_ax_pcie_trx_mitigation *mit_info);
enum rtw_hal_status
rtw_hal_mac_tsf_sync(struct hal_info_t *hal_info,
u8 from_port, u8 to_port, enum phl_band_idx band,
s32 sync_offset_tu, enum hal_tsf_sync_act action);
enum rtw_hal_status
rtw_hal_mac_get_sec_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size);
enum rtw_hal_status
rtw_hal_mac_get_addr_cam(struct hal_info_t *hal_info, u16 num, u8 *buf, u16 size);
enum rtw_hal_status rtw_hal_mac_get_tsf(struct hal_info_t *hal, u8 *port,
u32 *tsf_h, u32 *tsf_l);
enum rtw_hal_status rtw_hal_mac_cfg_txhci(struct hal_info_t *hal,u8 en);
enum rtw_hal_status rtw_hal_mac_cfg_rxhci(struct hal_info_t *hal,u8 en);
#ifdef CONFIG_MCC_SUPPORT
enum rtw_hal_status rtw_hal_mac_add_mcc(struct hal_info_t *hal,
struct rtw_phl_mcc_role *mcc_role);
enum rtw_hal_status rtw_hal_mac_start_mcc(struct hal_info_t *hal,
u8 group, u8 macid, u32 tsf_high, u32 tsf_low, u8 btc_in_group,
u8 old_group_action, u8 old_group);
enum rtw_hal_status rtw_hal_mac_stop_mcc(struct hal_info_t *hal, u8 group,
u8 macid);
enum rtw_hal_status rtw_hal_mac_del_mcc_group(struct hal_info_t *hal, u8 group);
enum rtw_hal_status rtw_hal_mac_mcc_request_tsf(struct hal_info_t *hal,
u8 group, u8 macid_x, u8 macid_y);
enum rtw_hal_status rtw_hal_mac_mcc_macid_bitmap(struct hal_info_t *hal,
u8 group, u8 macid, u8 *bitmap, u8 len);
enum rtw_hal_status rtw_hal_mac_mcc_sync_enable(struct hal_info_t *hal,
u8 group, u8 source, u8 target, u8 offset);
enum rtw_hal_status rtw_hal_mac_set_duration(struct hal_info_t *hal,
struct rtw_phl_mcc_en_info *en_info,
struct rtw_phl_mcc_bt_info *bt_info);
enum rtw_hal_status rtw_hal_mac_get_mcc_tsf_rpt(struct hal_info_t *hal,
u8 group, u32 *tsf_x_h, u32 *tsf_x_l,
u32 *tsf_y_h, u32 *tsf_y_l);
enum rtw_hal_status rtw_hal_mac_get_mcc_status_rpt(struct hal_info_t *hal,
u8 group, u8 *status, u32 *tsf_h, u32 *tsf_l);
enum rtw_hal_status rtw_hal_mac_get_mcc_group(struct hal_info_t *hal, u8 *group);
#endif /* CONFIG_MCC_SUPPORT */
void rtw_hal_mac_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
u8 band);
void rtw_hal_mac_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
u8 band);
enum rtw_hal_status rtw_hal_mac_set_hw_rts_th(struct hal_info_t *hal, u8 band,
u16 time_th, u16 len_th);
enum rtw_hal_status rtw_hal_mac_set_dfs_tb_ctrl(struct hal_info_t *hal, u8 set);
enum rtw_hal_status
rtw_hal_mac_trigger_fw_conflict(struct hal_info_t *hal_com, u32 addr, u8 vol);
u8 rtw_hal_mac_get_efuse_ver_len(struct rtw_hal_com_t *hal_com);
#ifdef CONFIG_PHL_P2PPS
enum rtw_hal_status rtw_hal_mac_noa_init(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid);
enum rtw_hal_status rtw_hal_mac_noa_update(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid);
enum rtw_hal_status rtw_hal_mac_noa_remove(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid);
enum rtw_hal_status rtw_hal_mac_noa_terminate(struct hal_info_t *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid);
enum rtw_hal_status rtw_hal_mac_tsf32_tog_enable(struct hal_info_t *hal,
u8 hw_band,
u8 port,
u16 early);
enum rtw_hal_status rtw_hal_mac_tsf32_tog_disable(struct hal_info_t *hal,
u8 hw_band,
u8 port);
enum rtw_hal_status rtw_hal_mac_get_tsf32_tog_rpt(struct hal_info_t *hal,
struct rtw_phl_tsf32_tog_rpt *rpt);
#endif
enum rtw_hal_status
rtw_hal_mac_addr_cam_set_aid(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta,
u16 aid);
enum rtw_hal_status
rtw_hal_mac_set_tx_lifetime(struct hal_info_t *hal, enum phl_band_idx band,
bool acq_en, bool mgq_en, u16 acq_val, u16 mgq_val);
enum rtw_hal_status
rtw_hal_mac_patch_rx_rate(struct hal_info_t *hal_info, struct rtw_r_meta_data *mdata);
enum rtw_hal_status
rtw_hal_mac_set_tx_duty(struct hal_info_t *hal_info,
u16 pause_interval,
u16 tx_interval);
enum rtw_hal_status
rtw_hal_mac_stop_tx_duty(struct hal_info_t *hal_info);
#endif /*_HAL_API_MAC_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_mac.h
|
C
|
agpl-3.0
| 23,439
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_API_RF_C_
#include "hal_headers.h"
#include "phy/rf/halrf_api.h"
#include "phy/rf/halrf_export_fun.h"
#ifdef USE_TRUE_PHY
enum rtw_hal_status
rtw_hal_rf_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = halrf_init(phl_com, hal_com, &(hal_info->rf));
if ((hal_status != RTW_HAL_STATUS_SUCCESS) ||
(hal_info->rf == NULL)) {
PHL_ERR("[PHL] rtw_halrf_init failed status(%d), hal_info->rf(%p)\n",
hal_status, hal_info->rf);
}
return hal_status;
}
void rtw_hal_rf_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
halrf_deinit(phl_com, hal_com, hal_info->rf);
}
void rtw_hal_init_rf_reg(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_para_info_t *phy_reg_info = NULL;
struct rtw_para_pwrlmt_info_t *pwrlmt_info = NULL;
u8 phy_idx = 0;
for (phy_idx = 0; phy_idx < 1 ; phy_idx++) {
phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_a_info;
halrf_config_radio_a_reg(hal_info->rf, phy_reg_info->para_src,
phy_reg_info->para_data_len, phy_reg_info->para_data);
}
for (phy_idx = 0; phy_idx < 1 ; phy_idx++) {
phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_b_info;
halrf_config_radio_b_reg(hal_info->rf , phy_reg_info->para_src,
phy_reg_info->para_data_len, phy_reg_info->para_data);
}
for (phy_idx = 0; phy_idx < 1 ; phy_idx++) {
phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwr_byrate_info;
halrf_config_store_power_by_rate(hal_info->rf , phy_reg_info->para_src,
phy_reg_info->para_data_len, phy_reg_info->para_data);
}
for (phy_idx = 0; phy_idx < 1 ; phy_idx++) {
phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrtrack_info;
halrf_config_store_power_track(hal_info->rf , phy_reg_info->para_src,
phy_reg_info->para_data_len, phy_reg_info->para_data);
}
for (phy_idx = 0; phy_idx < 1 ; phy_idx++) {
pwrlmt_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrlmt_info;
halrf_config_store_power_limit(hal_info->rf , pwrlmt_info->para_src,
pwrlmt_info->para_data_len, pwrlmt_info->para_data);
}
for (phy_idx = 0; phy_idx < 1 ; phy_idx++) {
pwrlmt_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrlmt_ru_info;
halrf_config_store_power_limit_ru(hal_info->rf , pwrlmt_info->para_src,
pwrlmt_info->para_data_len, pwrlmt_info->para_data);
}
}
void rtw_hal_rf_dm_init(struct hal_info_t *hal_info)
{
halrf_dm_init(hal_info->rf);
}
enum rtw_hal_status
rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com,
u8 *efuse_map, enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
PHL_INFO("%s\n", __FUNCTION__);
if(halrf_get_efuse_info(hal_info->rf, efuse_map, info_type, value, size,
map_valid))
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
}
void
rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx,
u8 pwrbyrate_type, u8 pwrlmt_type)
{
/* struct hal_info_t *hal_info = hal_com->hal_priv;
halrf_set_power_table_switch(hal_info->rf, phy_idx,
pwrbyrate_type, pwrlmt_type);*/
}
int rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str(const char *str)
{
return halrf_get_predefined_pw_lmt_regu_type_from_str(str);
}
const char * const *rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(u8 *num)
{
return halrf_get_predefined_pw_lmt_regu_type_str_array(num);
}
const char *rtw_hal_rf_get_pw_lmt_regu_type_str(struct hal_info_t *hal_info, enum band_type band)
{
return halrf_get_pw_lmt_regu_type_str(hal_info->rf, band);
}
enum rtw_hal_status rtw_hal_rf_read_pwr_table(
struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate,
u8 bandwidth, u8 channel, u8 offset, u8 dcm,
u8 beamforming, s16 *get_item)
{
int ret = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
*get_item = halrf_get_power(hal_info->rf, rf_path, rate, dcm,offset, bandwidth, beamforming, channel);
return ret;
}
enum rtw_hal_status rtw_hal_rf_wl_tx_power_control(struct rtw_hal_com_t *hal_com,
u32 tx_power_val)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
PHL_INFO("%s\n", __FUNCTION__);
halrf_wl_tx_power_control(hal_info->rf, tx_power_val);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_pwrtrack(struct hal_info_t *hal_info, u8 *txpwr_track_status)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
*txpwr_track_status = halrf_get_power_track(hal_info->rf);
return ret;
}
enum rtw_hal_status rtw_hal_rf_set_pwrtrack(struct hal_info_t *hal_info, u8 phy_idx, u8 txpwr_track_status)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
halrf_set_power_track(hal_info->rf, phy_idx, txpwr_track_status);
return ret;
}
enum rtw_hal_status rtw_hal_rf_get_thermal(struct hal_info_t *hal_info, u8 rf_path, u8 *thermal)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
*thermal = halrf_get_thermal(hal_info->rf, rf_path);
return ret;
}
enum rtw_hal_status rtw_hal_rf_set_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 tssi_de)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
halrf_set_tssi_de_for_tx_verify(hal_info->rf, phy_idx, tssi_de, rf_path);
return ret;
}
enum rtw_hal_status rtw_hal_rf_set_tssi_offset(struct hal_info_t *hal_info, u8 phy_idx, u32 tssi_de_offset, u8 rf_path)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
halrf_set_tssi_de_offset(hal_info->rf, phy_idx, tssi_de_offset, rf_path);
return ret;
}
enum rtw_hal_status rtw_hal_rf_get_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 *tssi_de)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
*tssi_de = halrf_get_tssi_de(hal_info->rf, phy_idx, rf_path);
return ret;
}
enum rtw_hal_status rtw_hal_rf_get_online_tssi_de(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path,s32 dbm, s32 pout, s32 *tssi_de)
{
int ret = RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API] %s \n", __FUNCTION__);
*tssi_de = halrf_get_online_tssi_de(hal_info->rf, phy_idx, rf_path, dbm, pout);
return ret;
}
enum rtw_hal_status
rtw_hal_rf_set_continuous_tx(struct hal_info_t *hal_info)
{
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_singletone_tx(struct hal_info_t *hal_info,
u8 is_on,enum rf_path path)
{
PHL_INFO("%s: enable = %d path = %x\n", __FUNCTION__, is_on, path);
halrf_lo_test(hal_info->rf, is_on, path);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_suppression_tx(struct hal_info_t *hal_info)
{
PHL_INFO("%s\n", __FUNCTION__);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com,
bool dbcc_en)
{
/*need replace with rf api*/
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
if (halrf_set_dbcc(hal_info->rf, dbcc_en))
hal_status = RTW_HAL_STATUS_SUCCESS;
return hal_status;
}
#define DBG_RFK_TIME
enum rtw_hal_status rtw_hal_rf_chl_rfk_trigger(void *hal,
u8 phy_idx, u8 force)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
#ifdef DBG_RFK_TIME
u32 iqk_start = _os_get_cur_time_ms();
#endif
PHL_INFO("[DBG_RFK]%s: phy_idx(%d), force(%d)\n", __func__,
phy_idx, force);
rtw_hal_mac_ser_ctrl(hal_info, false);
hal_status = halrf_chl_rfk_trigger(hal_info->rf, phy_idx, force);
#ifdef DBG_RFK_TIME
PHL_INFO("[DBG_RFK]%s: RFK take %d (ms)\n", __func__,
phl_get_passing_time_ms(iqk_start));
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
rtw_hal_mac_ser_ctrl(hal_info, true);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_dack_trigger(struct hal_info_t *hal_info,
u8 force)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_dack_trigger(hal_info->rf, force);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_iqk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = halrf_iqk_trigger(hal_info->rf, phy_idx, force);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_lck_trigger(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_lck_trigger(hal_info->rf);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_dpk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = halrf_dpk_trigger(hal_info->rf, phy_idx, force);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_tssi_trigger(struct hal_info_t *hal_info,
u8 phy_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_tssi_trigger(hal_info->rf, phy_idx);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_gapk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_gapk_trigger(hal_info->rf, phy_idx, force);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_set_capability_dack(struct hal_info_t *hal_info,
u8 enable)
{
#if 0
halrf_dack_onoff(hal_info->rf, enable);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_iqk(struct hal_info_t *hal_info,
u8 enable)
{
#if 0
halrf_iqk_onoff(hal_info->rf, enable);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_dpk(struct hal_info_t *hal_info,
u8 enable)
{
#if 0
halrf_dpk_onoff(hal_info->rf, enable);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_dpk_track(struct hal_info_t *hal_info,
u8 enable)
{
#if 0
halrf_dpk_track_onoff(hal_info->rf, enable);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_tssi(struct hal_info_t *hal_info,
u8 enable)
{
#if 0
halrf_tssi_onoff(hal_info->rf, enable);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_gapk(struct hal_info_t *hal_info,
u8 enable)
{
#if 0
halrf_gapk_onoff(hal_info->rf, enable);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_dack(struct hal_info_t *hal_info,
u8 *enable)
{
#if 0
*enable = halrf_get_dack_onoff(hal_info->rf);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_iqk(struct hal_info_t *hal_info,
u8 *enable)
{
#if 0
*enable = halrf_get_iqk_onoff(hal_info->rf);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_dpk(struct hal_info_t *hal_info,
u8 *enable)
{
#if 0
*enable = halrf_get_dpk_onoff(hal_info->rf);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_dpk_track(struct hal_info_t *hal_info,
u8 *enable)
{
#if 0
*enable = halrf_get_dpk_track_onoff(hal_info->rf);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_tssi(struct hal_info_t *hal_info,
u8 *enable)
{
#if 0
*enable = halrf_get_tssi_onoff(hal_info->rf);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_gapk(struct hal_info_t *hal_info,
u8 *enable)
{
#if 0
*enable = halrf_get_gapk_onoff(hal_info->rf);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_tssi_de_value(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_get_tssi_de_value(hal_info->rf);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_set_tssi_de_tx_verify(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_set_tssi_de_tx_verify(hal_info->rf);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_get_txpwr_final_abs(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
#if 0
hal_status = halrf_get_txpwr_final_abs(hal_info->rf);
#else
hal_status = RTW_HAL_STATUS_SUCCESS;
#endif
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
bool
rtw_hal_rf_proc_cmd(struct hal_info_t *hal_info,
struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
if(incmd->in_type == RTW_ARG_TYPE_BUF)
halrf_cmd(hal_info->rf, incmd->in.buf, output, out_len);
else if(incmd->in_type == RTW_ARG_TYPE_ARRAY){
halrf_cmd_parser(hal_info->rf, incmd->in.vector,
incmd->in_cnt_len, output, out_len);
}
return true;
}
enum rtw_hal_status rtw_hal_rf_watchdog(struct hal_info_t *hal_info)
{
halrf_watchdog(hal_info->rf);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_power(struct hal_info_t *hal_info, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if(halrf_set_power(hal_info->rf, phy, pwr_table))
{
hal_status = RTW_HAL_STATUS_SUCCESS;
}
else
{
hal_status = RTW_HAL_STATUS_FAILURE;
}
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_set_gain_offset(struct hal_info_t *hal_info, u8 cur_phy_idx,
s8 offset, u8 rf_path)
{
enum rtw_hal_status ret=RTW_HAL_STATUS_SUCCESS;
PHL_INFO("[MP HAL API]%s\n", __FUNCTION__);
halrf_set_rx_gain_offset_for_rx_verify(hal_info->rf, cur_phy_idx, offset, rf_path);
return ret;
}
enum rtw_hal_status rtw_hal_rf_trigger_dpk_tracking(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = halrf_dpk_tracking(hal_info->rf);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("[MP HAL API] %s failed status(%d)\n",__FUNCTION__, hal_status);
return hal_status;
}
enum rtw_hal_status
rtw_hal_rf_get_default_rfe_type(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
hal_com->dev_hw_cap.rfe_type = halrf_get_default_rfe_type(hal_info->rf);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_get_default_xtal(struct rtw_hal_com_t *hal_com)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
hal_com->dev_hw_cap.xcap = halrf_get_default_xtal(hal_info->rf);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_tssi_avg(struct hal_info_t *hal_info, u8 cur_phy_idx,
s32 xdbm)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
halrf_set_tssi_avg_mp(hal_info->rf, cur_phy_idx, xdbm);
return hal_status;
}
void rtw_hal_rf_do_tssi_scan(struct hal_info_t *hal_info, u8 cur_phy_idx)
{
halrf_do_tssi_scan(hal_info->rf, cur_phy_idx);
}
enum rtw_hal_status
rtw_hal_rf_update_ext_pwr_lmt_table(struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
halrf_power_limit_set_ext_pwr_limit_table(hal_info->rf, HW_PHY_0);
halrf_power_limit_set_ext_pwr_limit_ru_table(hal_info->rf, HW_PHY_0);
return hal_status;
}
enum rtw_hal_status
rtw_hal_rf_config_radio_to_fw(struct hal_info_t *hal_info)
{
halrf_config_radio_to_fw(hal_info->rf);
return RTW_HAL_STATUS_SUCCESS;
}
bool
rtw_hal_rf_check_efuse_data(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
return halrf_tssi_check_efuse_data(hal_info->rf, phy_idx);
}
void
rtw_hal_rf_disconnect_notify(void *hal, struct rtw_chan_def *chandef)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
halrf_disconnect_notify(hal_info->rf, chandef);
}
bool
rtw_hal_rf_check_mcc_ch(void *hal, struct rtw_chan_def *chandef)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return halrf_check_mcc_ch(hal_info->rf, chandef);
}
void
rtw_hal_rf_dpk_switch(void *hal, bool enable)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_rf_dpk_switch(): enable(%d)\n",
enable);
halrf_dpk_switch(hal_info->rf, enable);
}
void
rtw_hal_rf_tssi_config(void *hal, enum phl_phy_idx phy_idx, bool enable)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_rf_tssi_config(): enable(%d), phy_idx(%d)\n",
enable, phy_idx);
if (enable)
halrf_tssi_enable(hal_info->rf, phy_idx);
else
halrf_tssi_disable(hal_info->rf, phy_idx);
}
enum rtw_hal_status
rtw_hal_rf_set_ch_bw(struct hal_info_t *hal_info, enum phl_phy_idx phy, u8 center_ch,
enum band_type band, enum channel_width bw)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
halrf_ctrl_bw_ch(hal_info->rf, phy, center_ch, band, bw);
return hal_status;
}
void
rtw_hal_rf_get_efuse_ex(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
halrf_tssi_get_efuse_ex(hal_info->rf, phy_idx);
}
/* PSD */
enum rtw_hal_status rtw_hal_rf_psd_init(struct hal_info_t *hal_info, u8 cur_phy_idx,
u8 path, u8 iq_path, u32 avg, u32 fft)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
halrf_psd_init(hal_info->rf, cur_phy_idx, path, iq_path, avg, fft);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_psd_restore(struct hal_info_t *hal_info, u8 cur_phy_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
halrf_psd_restore(hal_info->rf, cur_phy_idx);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_psd_get_point_data(struct hal_info_t *hal_info, u8 cur_phy_idx,
s32 point, u32 *value)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
*value = halrf_psd_get_point_data(hal_info->rf, cur_phy_idx, point);
return hal_status;
}
enum rtw_hal_status rtw_hal_rf_psd_query(struct hal_info_t *hal_info, u8 cur_phy_idx,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
halrf_psd_query(hal_info->rf, cur_phy_idx, point, start_point, stop_point, outbuf);
return hal_status;
}
void rtw_hal_rf_rx_ant(struct hal_info_t *hal_info, /*enum halrf_ant*/u8 ant)
{
halrf_2g_rxant(hal_info->rf, ant);
}
enum halrf_thermal_status
rtw_hal_rf_get_ther_protected_threshold(
struct hal_info_t *hal_info
)
{
s8 val = 0;
enum halrf_thermal_status status = HALRF_THERMAL_STATUS_UNKNOWN;
val = halrf_get_ther_protected_threshold(hal_info->rf);
if(val == -1){
status = HALRF_THERMAL_STATUS_ABOVE_THRESHOLD;
PHL_TRACE(COMP_PHL_RF, _PHL_INFO_, "[HALRF] Thermal above threshold!\n");
}
else if(val == 0){
status = HALRF_THERMAL_STATUS_STAY_THRESHOLD;
PHL_TRACE(COMP_PHL_RF, _PHL_INFO_, "[HALRF] Thermal stay at threshold!\n");
}
else if(val == 1){
status = HALRF_THERMAL_STATUS_BELOW_THRESHOLD;
PHL_TRACE(COMP_PHL_RF, _PHL_INFO_, "[HALRF] Thermal below threshold!\n");
}
else{
status = HALRF_THERMAL_STATUS_UNKNOWN;
PHL_TRACE(COMP_PHL_RF, _PHL_WARNING_, "[HALRF] Thermal unknown status!\n");
}
return status;
}
void rtw_hal_rf_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
enum phl_phy_idx phy_idx)
{
halrf_wifi_event_notify(hal_info->rf, event, phy_idx);
}
void
rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx, enum rf_path path)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
halrf_tssi_scan_ch(hal_info->rf, path);
halrf_tssi_set_efuse_to_de(hal_info->rf, phy_idx);
}
s8 rtw_hal_rf_get_power_limit(void *hal, enum phl_phy_idx phy,
u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return halrf_get_power_limit(hal_info->rf, phy, RF_PATH_A, rate,
bandwidth, beamforming, tx_num, channel);
}
void rtw_hal_rf_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
enum phl_phy_idx phy_idx)
{
/*to do*/
}
#else /*ifdef USE_TRUE_PHY*/
enum rtw_hal_status
rtw_hal_rf_init(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_rf_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
}
void rtw_hal_init_rf_reg(struct rtw_phl_com_t *phl_com, void *hal)
{
}
void rtw_hal_rf_dm_init(struct hal_info_t *hal_info)
{
}
enum rtw_hal_status
rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com, u8 *efuse_map,
enum rtw_efuse_info info_type, void *value,
u8 size, u8 map_valid)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_read_pwr_table(struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate,
u8 bandwidth, u8 channel, u8 offset, u8 dcm,
u8 beamforming, s16 *get_item)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_wl_tx_power_control(struct rtw_hal_com_t *hal_com,
u32 tx_power_val)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_pwrtrack(struct hal_info_t *hal_info,
u8 *txpwr_track_status)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_pwrtrack(struct hal_info_t *hal_info,
u8 phy_idx, u8 txpwr_track_status)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_thermal(struct hal_info_t *hal_info,
u8 rf_path, u8 *thermal)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_get_default_xtal(struct rtw_hal_com_t *hal_com)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_get_default_rfe_type(struct rtw_hal_com_t *hal_com)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_tssi(struct hal_info_t *hal_info,
u8 phy_idx, u8 rf_path, u32 tssi_de)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_tssi_offset(struct hal_info_t *hal_info, u8 phy_idx, u32 tssi_de_offset, u8 rf_path)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_tssi(struct hal_info_t *hal_info,
u8 phy_idx, u8 rf_path, u32 *tssi_de)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_online_tssi_de(
struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path,
s32 dbm, s32 pout, s32 *tssi_de)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_continuous_tx(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_singletone_tx(struct hal_info_t *hal_info,
u8 is_on,enum rf_path path)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_suppression_tx(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com,
bool dbcc_en)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_chl_rfk_trigger(void *hal, u8 phy_idx, u8 force)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_dack_trigger(struct hal_info_t *hal_info,
u8 force)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_iqk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_lck_trigger(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_dpk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_tssi_trigger(struct hal_info_t *hal_info,
u8 phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_gapk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_dack(struct hal_info_t *hal_info,
u8 enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_iqk(struct hal_info_t *hal_info,
u8 enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_dpk(struct hal_info_t *hal_info,
u8 enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_capability_dpk_track(struct hal_info_t *hal_info, u8 enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_capability_tssi(struct hal_info_t *hal_info, u8 enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_capability_gapk(struct hal_info_t *hal_info,
u8 enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_dack(struct hal_info_t *hal_info,
u8 *enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_iqk(struct hal_info_t *hal_info,
u8 *enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_dpk(struct hal_info_t *hal_info,
u8 *enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_get_capability_dpk_track(struct hal_info_t *hal_info, u8 *enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_tssi(struct hal_info_t *hal_info,
u8 *enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_capability_gapk(struct hal_info_t *hal_info,
u8 *enable)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_tssi_de_value(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_tssi_de_tx_verify(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_get_txpwr_final_abs(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool rtw_hal_rf_proc_cmd(struct hal_info_t *hal_info,
struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
return true;
}
enum rtw_hal_status rtw_hal_rf_watchdog(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_rf_set_power(struct hal_info_t *hal_info, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_gain_offset(struct hal_info_t *hal_info, u8 cur_phy_idx,
s8 offset, u8 rf_path)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_trigger_dpk_tracking(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
void rtw_hal_rf_do_tssi_scan(struct hal_info_t *hal_info, u8 cur_phy_idx)
{
}
enum rtw_hal_status
rtw_hal_rf_config_radio_to_fw(struct hal_info_t *hal_info)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_set_tssi_avg(struct hal_info_t *hal_info, u8 cur_phy_idx,
s32 xdbm)
{
return RTW_HAL_STATUS_SUCCESS;
}
bool
rtw_hal_rf_check_efuse_data(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx)
{
return true;
}
enum rtw_hal_status
rtw_hal_rf_set_ch_bw(struct hal_info_t *hal_info, enum phl_phy_idx phy, u8 center_ch,
enum band_type band, enum channel_width bw)
{
return RTW_HAL_STATUS_SUCCESS;
}
/* PSD */
enum rtw_hal_status rtw_hal_rf_psd_init(struct hal_info_t *hal_info, u8 cur_phy_idx,
u8 path, u8 iq_path, u32 avg, u32 fft)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_psd_restore(struct hal_info_t *hal_info, u8 cur_phy_idx)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_psd_get_point_data(struct hal_info_t *hal_info, u8 cur_phy_idx,
s32 point, u32 *value)
{
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_rf_psd_query(struct hal_info_t *hal_info, u8 cur_phy_idx,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf)
{
return RTW_HAL_STATUS_SUCCESS;
}
void
rtw_hal_rf_disconnect_notify(void *hal, struct rtw_chan_def *chandef)
{
}
bool
rtw_hal_rf_check_mcc_ch(void *hal, struct rtw_chan_def *chandef)
{
return false;
}
void
rtw_hal_rf_dpk_switch(void *hal, bool enable)
{
}
void
rtw_hal_rf_tssi_config(void *hal, enum phl_phy_idx phy_idx, bool enable)
{
}
void
rtw_hal_rf_get_efuse_ex(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx)
{
}
void
rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx,
u8 pwrbyrate_type, u8 pwrlmt_type)
{
return;
}
int rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str(const char *str)
{
return -1;
}
const char * const *rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(u8 *num)
{
return NULL;
}
const char *rtw_hal_rf_get_pw_lmt_regu_type_str(struct hal_info_t *hal_info, enum band_type band)
{
return NULL;
}
void rtw_hal_rf_rx_ant(struct hal_info_t *hal_info, /*enum halrf_ant*/u8 ant)
{
}
enum halrf_thermal_status
rtw_hal_rf_get_ther_protected_threshold(
struct hal_info_t *hal_info
)
{
return HALRF_THERMAL_STATUS_BELOW_THRESHOLD;
}
void rtw_hal_rf_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
enum phl_phy_idx phy_idx)
{
return;
}
void
rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com,
enum phl_phy_idx phy_idx, enum rf_path path)
{
return;
}
s8 rtw_hal_rf_get_power_limit(void *hal, enum phl_phy_idx phy,
u16 rate, u8 bandwidth, u8 beamforming, u8 tx_num, u8 channel)
{
return 0;
}
void rtw_hal_rf_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
enum phl_phy_idx phy_idx)
{
}
#endif /*ifdef USE_TRUE_PHY*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_rf.c
|
C
|
agpl-3.0
| 31,494
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_API_RF_H_
#define _HAL_API_RF_H_
enum halrf_thermal_status{
HALRF_THERMAL_STATUS_BELOW_THRESHOLD,
HALRF_THERMAL_STATUS_STAY_THRESHOLD,
HALRF_THERMAL_STATUS_ABOVE_THRESHOLD,
HALRF_THERMAL_STATUS_UNKNOWN
};
enum rtw_hal_status
rtw_hal_rf_init(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_rf_deinit(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info);
void rtw_hal_init_rf_reg(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status rtw_hal_rf_get_pwrtrack(struct hal_info_t *hal_info, u8 *txpwr_track_status);
void rtw_hal_rf_dm_init(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_rf_set_pwrtrack(struct hal_info_t *hal_info, u8 phy_idx, u8 txpwr_track_status);
void rtw_hal_rf_dm_init(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_rf_get_thermal(struct hal_info_t *hal_info, u8 rf_path, u8 *thermal);
enum rtw_hal_status rtw_hal_rf_set_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 tssi_de);
enum rtw_hal_status rtw_hal_rf_get_tssi(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path, u32 *tssi);
enum rtw_hal_status rtw_hal_rf_get_online_tssi_de(struct hal_info_t *hal_info, u8 phy_idx, u8 rf_path,s32 dbm, s32 pout, s32 *tssi_de);
enum rtw_hal_status rtw_hal_rf_set_tssi_offset(struct hal_info_t *hal_info, u8 phy_idx, u32 tssi_de_offset, u8 rf_path);
enum rtw_hal_status rtw_hal_rf_set_continuous_tx(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_rf_set_singletone_tx(struct hal_info_t *hal_info,
u8 is_on,enum rf_path path);
enum rtw_hal_status rtw_hal_rf_set_suppression_tx(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_rf_chl_rfk_trigger(void *hal, u8 phy_idx, u8 force);
enum rtw_hal_status rtw_hal_rf_dack_trigger(struct hal_info_t *hal_info,
u8 force);
enum rtw_hal_status rtw_hal_rf_iqk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force);
enum rtw_hal_status rtw_hal_rf_lck_trigger(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_rf_dpk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force);
enum rtw_hal_status rtw_hal_rf_tssi_trigger(struct hal_info_t *hal_info,
u8 phy_idx);
enum rtw_hal_status rtw_hal_rf_gapk_trigger(struct hal_info_t *hal_info,
u8 phy_idx, u8 force);
enum rtw_hal_status rtw_hal_rf_set_capability_dack(struct hal_info_t *hal_info,
u8 enable);
enum rtw_hal_status rtw_hal_rf_set_capability_iqk(struct hal_info_t *hal_info,
u8 enable);
enum rtw_hal_status rtw_hal_rf_set_capability_dpk(struct hal_info_t *hal_info,
u8 enable);
enum rtw_hal_status rtw_hal_rf_set_capability_dpk_track(struct hal_info_t *hal_info,
u8 enable);
enum rtw_hal_status rtw_hal_rf_set_capability_tssi(struct hal_info_t *hal_info,
u8 enable);
enum rtw_hal_status rtw_hal_rf_set_capability_gapk(struct hal_info_t *hal_info,
u8 enable);
enum rtw_hal_status rtw_hal_rf_get_capability_dack(struct hal_info_t *hal_info,
u8 *enable);
enum rtw_hal_status rtw_hal_rf_get_capability_iqk(struct hal_info_t *hal_info,
u8 *enable);
enum rtw_hal_status rtw_hal_rf_get_capability_dpk(struct hal_info_t *hal_info,
u8 *enable);
enum rtw_hal_status rtw_hal_rf_get_capability_dpk_track(struct hal_info_t *hal_info,
u8 *enable);
enum rtw_hal_status rtw_hal_rf_get_capability_tssi(struct hal_info_t *hal_info,
u8 *enable);
enum rtw_hal_status rtw_hal_rf_get_capability_gapk(struct hal_info_t *hal_info,
u8 *enable);
enum rtw_hal_status rtw_hal_rf_get_tssi_de_value(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_rf_set_tssi_de_tx_verify(struct hal_info_t *hal_info);
enum rtw_hal_status rtw_hal_rf_get_txpwr_final_abs(struct hal_info_t *hal_info);
int rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str(const char *str);
const char * const *rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(u8 *num);
const char *rtw_hal_rf_get_pw_lmt_regu_type_str(struct hal_info_t *hal_info, enum band_type band);
bool
rtw_hal_rf_proc_cmd(struct hal_info_t *hal_info,
struct rtw_proc_cmd *incmd,
char *output, u32 out_len);
enum rtw_hal_status
rtw_hal_rf_recover(struct hal_info_t *hal_info, u32 offset, u32 val, enum rf_path path);
enum rtw_hal_status rtw_hal_rf_watchdog(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_rf_set_power(struct hal_info_t *hal_info, enum phl_phy_idx phy,
enum phl_pwr_table pwr_table);
enum rtw_hal_status rtw_hal_rf_set_gain_offset(struct hal_info_t *hal_info, u8 cur_phy_idx,
s8 offset, u8 rf_path);
enum rtw_hal_status rtw_hal_rf_trigger_dpk_tracking(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_rf_get_default_rfe_type(struct rtw_hal_com_t *hal_com);
enum rtw_hal_status
rtw_hal_rf_get_default_xtal(struct rtw_hal_com_t *hal_com);
enum rtw_hal_status rtw_hal_rf_set_tssi_avg(struct hal_info_t *hal_info, u8 cur_phy_idx,
s32 xdbm);
void
rtw_hal_rf_do_tssi_scan(struct hal_info_t *hal_ionfo, u8 cur_phy_idx);
enum rtw_hal_status
rtw_hal_rf_update_ext_pwr_lmt_table(struct hal_info_t *hal_info);
enum rtw_hal_status
rtw_hal_rf_config_radio_to_fw(struct hal_info_t *hal_info);
bool
rtw_hal_rf_check_efuse_data(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx);
void
rtw_hal_rf_disconnect_notify(void *hal, struct rtw_chan_def *chandef);
bool
rtw_hal_rf_check_mcc_ch(void *hal, struct rtw_chan_def *chandef);
void
rtw_hal_rf_dpk_switch(void *hal, bool enable);
void
rtw_hal_rf_tssi_config(void *hal, enum phl_phy_idx phy_idx, bool enable);
enum rtw_hal_status
rtw_hal_rf_set_ch_bw(struct hal_info_t *hal_info, enum phl_phy_idx phy, u8 center_ch,
enum band_type band, enum channel_width bw);
void
rtw_hal_rf_get_efuse_ex(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx);
/* PSD */
enum rtw_hal_status rtw_hal_rf_psd_init(struct hal_info_t *hal_info, u8 cur_phy_idx,
u8 path, u8 iq_path, u32 avg, u32 fft);
enum rtw_hal_status rtw_hal_rf_psd_restore(struct hal_info_t *hal_info, u8 cur_phy_idx);
enum rtw_hal_status rtw_hal_rf_psd_get_point_data(struct hal_info_t *hal_info, u8 cur_phy_idx,
s32 point, u32 *value);
enum rtw_hal_status rtw_hal_rf_psd_query(struct hal_info_t *hal_info, u8 cur_phy_idx,
u32 point, u32 start_point, u32 stop_point, u32 *outbuf);
void rtw_hal_rf_rx_ant(struct hal_info_t *hal_info, /*enum halrf_ant*/ u8 ant);
enum halrf_thermal_status
rtw_hal_rf_get_ther_protected_threshold(
struct hal_info_t *hal_info
);
void rtw_hal_rf_notification(struct hal_info_t *hal_info,
enum phl_msg_evt_id event,
enum phl_phy_idx phy_idx);
void rtw_hal_rf_cmd_notification(struct hal_info_t *hal_info,
void *hal_cmd,
enum phl_phy_idx phy_idx);
#endif /*_HAL_API_RF_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_api_rf.h
|
C
|
agpl-3.0
| 7,432
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "hal_headers.h"
/**
* rtw_hal_bf_dbg_dump_entry
* @entry: hal_bf_entry for dump content
**/
void rtw_hal_bf_dbg_dump_entry(void *entry)
{
struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry;
if (bf_entry == NULL) {
return;
}
PHL_INFO("-----DUMP BF ENTRY-----\n");
PHL_INFO("bf_entry->bf_idx 0x%x \n", bf_entry->bf_idx);
PHL_INFO("bf_entry->macid 0x%x \n", bf_entry->macid);
PHL_INFO("bf_entry->aid12 0x%x \n", bf_entry->aid12);
PHL_INFO("bf_entry->band 0x%x \n", bf_entry->band);
PHL_INFO("bf_entry->en_swap 0x%x \n", bf_entry->en_swap ? 1 : 0);
PHL_INFO("bf_entry->counter 0x%x \n", bf_entry->couter);
PHL_INFO("bf_entry->csi_buf 0x%x \n", bf_entry->csi_buf);
PHL_INFO("bf_entry->csi_buf_swap 0x%x \n", bf_entry->csi_buf_swap);
if (bf_entry->bfee != NULL) {
PHL_INFO("bf_entry->bfee->type 0x%x \n", bf_entry->bfee->type);
}
}
/**
* rtw_hal_bf_dbg_dump_entry_all
* @hal: hal_info_t
**/
void rtw_hal_bf_dbg_dump_entry_all(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_entry *bf_entry;
_os_list *busy_list = &bf_obj->bf_busy_list;
_os_list *idle_list = &bf_obj->bf_idle_list;
PHL_INFO("-----DUMP BF BUSY LIST-----\n");
if(list_empty(busy_list)) {
PHL_INFO("BF Entry BUSY LIST is Empty\n");
} else {
phl_list_for_loop(bf_entry, struct hal_bf_entry, busy_list,
list) {
PHL_INFO("bf_entry->bf_idx 0x%x \n", bf_entry->bf_idx);
PHL_INFO("bf_entry->macid 0x%x \n", bf_entry->macid);
PHL_INFO("bf_entry->aid12 0x%x \n", bf_entry->aid12);
PHL_INFO("bf_entry->band 0x%x \n", bf_entry->band);
PHL_INFO("bf_entry->en_swap 0x%x \n", bf_entry->en_swap ? 1 : 0);
PHL_INFO("bf_entry->counter 0x%x \n", bf_entry->couter);
PHL_INFO("bf_entry->csi_buf 0x%x \n",
bf_entry->csi_buf);
PHL_INFO("bf_entry->csi_buf_swap 0x%x \n",
bf_entry->csi_buf_swap);
if (NULL!=bf_entry->bfee) {
PHL_INFO("bfee->idx 0x%x \n",
bf_entry->bfee->idx);
PHL_INFO("bfee->type 0x%x \n",
bf_entry->bfee->type);
}
}
}
PHL_INFO("-----DUMP BF IDLE LIST-----\n");
if(list_empty(idle_list)) {
PHL_INFO("BF Entry IDLE LIST is Empty\n");
} else {
phl_list_for_loop(bf_entry, struct hal_bf_entry, idle_list,
list) {
PHL_INFO("bf_entry->bf_idx 0x%x \n", bf_entry->bf_idx);
PHL_INFO("bf_entry->macid 0x%x \n", bf_entry->macid);
PHL_INFO("bf_entry->aid12 0x%x \n", bf_entry->aid12);
PHL_INFO("bf_entry->band 0x%x \n", bf_entry->band);
PHL_INFO("bf_entry->csi_buf 0x%x \n",
bf_entry->csi_buf);
}
}
}
void _reset_bf_entry(struct hal_bf_entry *bf_entry)
{
bf_entry->macid = 0;
bf_entry->aid12 = 0;
bf_entry->csi_buf = 0;
bf_entry->bfee = NULL;
bf_entry->csi_buf_swap = 0;
bf_entry->couter = 0;
}
void _reset_sumu_entry(struct hal_sumu_entry *entry)
{
entry->snd_sts = 0;
return;
}
/* START of tx bf entry */
static struct hal_bf_entry *_query_idle_bf_entry(struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj)
{
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *idle_list = &bf_obj->bf_idle_list;
struct hal_bf_entry *bf_entry = NULL;
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
if (true == list_empty(idle_list)) {
bf_entry = NULL;
} else {
bf_entry = list_first_entry(idle_list, struct hal_bf_entry,
list);
bf_obj->num_idle_bf_entry--;
list_del(&bf_entry->list);
}
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
return bf_entry;
}
static enum rtw_hal_status _enqueue_idle_bf_entry(
struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj,
struct hal_bf_entry *bf_entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *list = &bf_obj->bf_idle_list;
if (bf_entry != NULL) {
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_add(&bf_entry->list, list);
bf_obj->num_idle_bf_entry++;
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
static enum rtw_hal_status _enqueue_busy_bf_entry(
struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj,
struct hal_bf_entry *bf_entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *list = &bf_obj->bf_busy_list;
if (bf_entry != NULL) {
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_add_tail(&bf_entry->list, list);
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
/*su entry*/
static struct hal_sumu_entry *_query_idle_su_entry(struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj)
{
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *idle_list = &bf_obj->su_idle_list;
struct hal_sumu_entry *su_entry = NULL;
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
if (true == list_empty(idle_list)) {
su_entry = NULL;
} else {
su_entry = list_first_entry(idle_list, struct hal_sumu_entry,
list);
bf_obj->num_idle_su_entry--;
list_del(&su_entry->list);
}
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
return su_entry;
}
static enum rtw_hal_status _enqueue_idle_su_entry(
struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj,
struct hal_sumu_entry *su_entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *list = &bf_obj->su_idle_list;
if (su_entry != NULL) {
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_add(&su_entry->list, list);
bf_obj->num_idle_su_entry++;
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
static enum rtw_hal_status _enqueue_busy_su_entry(
struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj,
struct hal_sumu_entry *su_entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *list = &bf_obj->su_busy_list;
if (su_entry != NULL) {
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_add_tail(&su_entry->list, list);
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
/*mu entry*/
static struct hal_sumu_entry *_query_idle_mu_entry(struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj)
{
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *idle_list = &bf_obj->mu_idle_list;
struct hal_sumu_entry *mu_entry = NULL;
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
if (true == list_empty(idle_list)) {
mu_entry = NULL;
} else {
mu_entry = list_first_entry(idle_list, struct hal_sumu_entry,
list);
bf_obj->num_idle_mu_entry--;
list_del(&mu_entry->list);
}
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
return mu_entry;
}
static enum rtw_hal_status _enqueue_idle_mu_entry(
struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj,
struct hal_sumu_entry *mu_entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *list = &bf_obj->mu_idle_list;
if (mu_entry != NULL) {
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_add(&mu_entry->list, list);
bf_obj->num_idle_mu_entry++;
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
static enum rtw_hal_status _enqueue_busy_mu_entry(
struct hal_info_t *hal_info,
struct hal_bf_obj *bf_obj,
struct hal_sumu_entry *mu_entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
void *drv_priv = hal_to_drvpriv(hal_info);
_os_list *list = &bf_obj->mu_busy_list;
if (mu_entry != NULL) {
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_add_tail(&mu_entry->list, list);
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
/* hal bf init */
enum rtw_hal_status _hal_bf_init_su_entry(
struct hal_info_t *hal_info,
u8 num)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
void *drv_priv = hal_to_drvpriv(hal_info);
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_sumu_entry *su_entry = NULL;
u8 i;
do {
bf_obj->su_entry = _os_mem_alloc(drv_priv,
sizeof(*su_entry) * num);
if (NULL == bf_obj->su_entry) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
_os_mem_set(drv_priv, bf_obj->su_entry, 0,
sizeof(*su_entry) * num);
su_entry = bf_obj->su_entry;
for ( i = 0 ; i < num; i++) {
su_entry[i].idx = i;
su_entry[i].type = HAL_BFEE_SU;
_reset_sumu_entry(&su_entry[i]);
INIT_LIST_HEAD(&su_entry[i].list);
list_add_tail(&su_entry[i].list, &bf_obj->su_idle_list);
bf_obj->num_idle_su_entry++;
}
} while (0);
return status;
}
enum rtw_hal_status _hal_bf_init_mu_entry(
struct hal_info_t *hal_info,
u8 num)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
void *drv_priv = hal_to_drvpriv(hal_info);
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_sumu_entry *mu_entry = NULL;
u8 i;
do {
bf_obj->mu_entry = _os_mem_alloc(drv_priv,
sizeof(*mu_entry) * num);
if (NULL == bf_obj->mu_entry) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
_os_mem_set(drv_priv, bf_obj->mu_entry, 0,
sizeof(*mu_entry) * num);
mu_entry = bf_obj->mu_entry;
for ( i = 0 ; i < num; i++) {
mu_entry[i].idx = i;
mu_entry[i].type = HAL_BFEE_MU;
_reset_sumu_entry(&mu_entry[i]);
INIT_LIST_HEAD(&mu_entry[i].list);
list_add_tail(&mu_entry[i].list, &bf_obj->mu_idle_list);
bf_obj->num_idle_mu_entry++;
}
} while (0);
return status;
}
enum rtw_hal_status _hal_bf_init_bf_entry(
struct hal_info_t *hal_info,
u8 num)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
void *drv_priv = hal_to_drvpriv(hal_info);
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_entry *bf_entry = NULL;
u8 i;
do {
bf_obj->bf_entry = _os_mem_alloc(drv_priv,
sizeof(*bf_entry) * num);
if (NULL == bf_obj->bf_entry) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
_os_mem_set(drv_priv, bf_obj->bf_entry, 0,
sizeof(*bf_entry) * num);
bf_entry = bf_obj->bf_entry;
for ( i = 0 ; i < num; i++) {
bf_entry[i].bf_idx = i;
_reset_bf_entry(&bf_entry[i]);
INIT_LIST_HEAD(&bf_entry[i].list);
list_add_tail(&bf_entry[i].list,
&bf_obj->bf_idle_list);
bf_obj->num_idle_bf_entry++;
}
} while (0);
return status;
}
/* Start of HAL API for other HAL modules */
/**
* hal_bf_init:
* initialize of beamform resource mgnt module
* input :
* @hal_info: (struct hal_info_t *)
* @bf_entry_nr: Number of HW support TxBF Entry
* @su_entry_nr: Number of HW support BFee-SU Entry
* @mu_entry_nr: Number of HW support BFee-MU Entry
**/
enum rtw_hal_status hal_bf_init(
struct hal_info_t *hal_info,
u8 bf_entry_nr,
u8 su_entry_nr,
u8 mu_entry_nr)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = NULL;
void *drv_priv = hal_to_drvpriv(hal_info);
FUNCIN();
do {
bf_obj = _os_mem_alloc(drv_priv, sizeof(*bf_obj));
if (bf_obj == NULL) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
hal_com->bf_obj = bf_obj;
_os_spinlock_init(drv_priv, &bf_obj->bf_lock);
INIT_LIST_HEAD(&bf_obj->bf_idle_list);
INIT_LIST_HEAD(&bf_obj->bf_busy_list);
INIT_LIST_HEAD(&bf_obj->su_idle_list);
INIT_LIST_HEAD(&bf_obj->su_busy_list);
INIT_LIST_HEAD(&bf_obj->mu_idle_list);
INIT_LIST_HEAD(&bf_obj->mu_busy_list);
if (RTW_HAL_STATUS_SUCCESS !=
_hal_bf_init_bf_entry(hal_info, bf_entry_nr)) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
bf_obj->max_bf_entry_nr = bf_entry_nr;
if (RTW_HAL_STATUS_SUCCESS !=
_hal_bf_init_su_entry(hal_info, su_entry_nr)) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
bf_obj->max_su_bfee_nr = su_entry_nr;
if (RTW_HAL_STATUS_SUCCESS !=
_hal_bf_init_mu_entry(hal_info, mu_entry_nr)) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
bf_obj->max_mu_bfee_nr = mu_entry_nr;
bf_obj->self_bf_cap[0] = 0;
bf_obj->self_bf_cap[1] = 0;
} while (0);
if (RTW_HAL_STATUS_SUCCESS != status) {
hal_bf_deinit(hal_info);
}
FUNCOUT();
return status;
}
/**
* hal_bf_deinit
* deinitialize of beamform resource mgnt module
* input :
* @hal_info: (struct hal_info_t *)
**/
void hal_bf_deinit(struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
void *drv_priv = hal_to_drvpriv(hal_info);
struct hal_bf_entry *bf_entry = bf_obj->bf_entry;
struct hal_sumu_entry *mu_entry = bf_obj->mu_entry;
struct hal_sumu_entry *su_entry = bf_obj->su_entry;
if (bf_obj != NULL) {
if (bf_entry != NULL) {
_os_mem_free(hal_to_drvpriv(hal_info), bf_entry,
sizeof(*bf_entry) * bf_obj->max_bf_entry_nr);
bf_obj->bf_entry = NULL;
}
if (su_entry != NULL) {
_os_mem_free(hal_to_drvpriv(hal_info), su_entry,
sizeof(*su_entry) * bf_obj->max_su_bfee_nr);
bf_obj->su_entry = NULL;
}
if (mu_entry != NULL) {
_os_mem_free(hal_to_drvpriv(hal_info), mu_entry,
sizeof(*mu_entry) * bf_obj->max_mu_bfee_nr);
bf_obj->mu_entry = NULL;
}
_os_spinlock_free(drv_priv, &bf_obj->bf_lock);
/* bf obj need free as last */
_os_mem_free(hal_to_drvpriv(hal_info), bf_obj,
sizeof(struct hal_bf_obj));
hal_com->bf_obj = NULL;
}
}
/**
* hal_bf_release_target_bf_entry
* Release the bf entry resource
* input
* @hal_info: (struct hal_info_t *)
* @entry: hal_bf_entry to be released
**/
enum rtw_hal_status hal_bf_release_target_bf_entry(
struct hal_info_t *hal_info,
void *entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry;
void *drv_priv = hal_to_drvpriv(hal_info);
u8 bfee_idx = 0;
u16 macid_rsvd = 0;
FUNCIN();
if (bf_obj != NULL && bf_entry != NULL) {
if (bf_entry->bfee != NULL) {
bfee_idx = bf_entry->bfee->idx +
((bf_entry->bfee->type == HAL_BFEE_MU) ?
bf_obj->max_su_bfee_nr : 0);
/* Clear HW CR to avoid TxBF when sounding is abort */
rtw_hal_mac_ax_set_bf_entry(hal_info->mac,
bf_entry->band, (u8)macid_rsvd,
bfee_idx, bf_entry->bf_idx, 0);
_reset_sumu_entry(bf_entry->bfee);
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_del(&bf_entry->bfee->list);
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
if (bf_entry->bfee->type == HAL_BFEE_MU) {
_enqueue_idle_mu_entry(
hal_info, bf_obj, bf_entry->bfee);
} else {
_enqueue_idle_su_entry(
hal_info, bf_obj, bf_entry->bfee);
}
}
_reset_bf_entry(bf_entry);
_os_spinlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
list_del(&bf_entry->list);
_os_spinunlock(drv_priv, &bf_obj->bf_lock, _ps, NULL);
_enqueue_idle_bf_entry(hal_info, bf_obj, bf_entry);
status = RTW_HAL_STATUS_SUCCESS;
}
FUNCOUT();
return status;
}
/**
* hal_bf_query_idle_bf_entry
* Get available beamformee entry
* @hal_info: (struct hal_info_t *)
* @mu: Is MU BFee ? 1 = MU / 0 = SU
* return :
* @hal_bf_entry: hal_bf_entry pointer
**/
struct hal_bf_entry *
hal_bf_query_idle_bf_entry(
struct hal_info_t *hal_info,
bool mu)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_entry *bf_entry = NULL;
struct hal_sumu_entry *sumu_entry;
FUNCIN();
do {
if (bf_obj == NULL)
break;
bf_entry = _query_idle_bf_entry(hal_info, bf_obj);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"_query_idle_bf_entry bf_entry %p \n", bf_entry);
if (NULL == bf_entry)
break;
if (true == mu)
bf_entry->bfee = _query_idle_mu_entry(hal_info, bf_obj);
else
bf_entry->bfee = _query_idle_su_entry(hal_info, bf_obj);
if (NULL == bf_entry->bfee)
break;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"_query_idle_bf_entry sumu_entry %p \n", bf_entry->bfee);
sumu_entry = bf_entry->bfee;
status = _enqueue_busy_bf_entry(hal_info, bf_obj, bf_entry);
if (RTW_HAL_STATUS_SUCCESS != status) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :hal_bf_entry add busy queue fail !!!\n");
break;
}
if (true == mu)
status = _enqueue_busy_mu_entry(
hal_info, bf_obj, sumu_entry);
else
status = _enqueue_busy_su_entry(
hal_info, bf_obj, sumu_entry);
if (RTW_HAL_STATUS_SUCCESS != status) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :sumu_entry add busy queue fail !!!\n");
break;
}
} while (0);
if((status != RTW_HAL_STATUS_SUCCESS) && (bf_entry != NULL)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "Get BF Entry Fail !!!\n");
hal_bf_release_target_bf_entry(hal_info, (void *)bf_entry);
}
FUNCOUT();
return bf_entry;
}
/**
* hal_bf_cfg_swbf_entry
* Fill BF Entry SW Content
* input:
* @sta: rtw_phl_stainfo_t
**/
enum rtw_hal_status
hal_bf_cfg_swbf_entry(struct rtw_phl_stainfo_t *sta, bool swap)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct hal_bf_entry *bf_entry =
(struct hal_bf_entry *)sta->hal_sta->bf_entry;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "hal_bf_cfg_swbf_entry bf_entry->idx = 0x%x\n",
bf_entry->bf_idx);
bf_entry->macid = sta->macid;
bf_entry->aid12 = sta->aid;
bf_entry->band = sta->wrole->hw_band; //TODO: :BSOD in snd_test whole = NULL
bf_entry->csi_buf = sta->hal_sta->bf_csi_buf;
if (swap) {
bf_entry->en_swap = true;
bf_entry->csi_buf_swap = sta->hal_sta->bf_csi_buf_swap;
}
return status;
}
/**
* hal_bf_set_entry_hwcfg
* Configure BF Entry HW Setting
* input
* @hal_info: (struct hal_info_t *)
* @entry: struct hal_bf_entry
**/
enum rtw_hal_status hal_bf_set_entry_hwcfg(
struct hal_info_t *hal_info,
void *entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry;
u8 bfee_idx = 0;
u16 csi_buf = 0;
/*TODO: 8852A : SU : 0 ~ N-1; MU : N ~ M*/
bfee_idx = bf_entry->bfee->idx +
((bf_entry->bfee->type == HAL_BFEE_MU) ?
bf_obj->max_su_bfee_nr : 0);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"hal_bf_set_entry_hwcfg set bf sts idx = 0x%x \n", bfee_idx);
/*1. HALMAC Settings*/
if ((bf_entry->bfee->type == HAL_BFEE_MU) && bf_entry->en_swap) {
/*swap mode*/
if(0 == (bf_entry->couter % 2))
csi_buf = bf_entry->csi_buf&CSI_BUF_IDX_HW_MSK;
else
csi_buf = bf_entry->csi_buf_swap&CSI_BUF_IDX_HW_MSK;
rtw_hal_mac_ax_set_bf_entry(
hal_info->mac, bf_entry->band,
(u8)(bf_entry->macid&0xFF), bfee_idx,
bf_entry->bf_idx, csi_buf);
bf_entry->couter++;
} else {
rtw_hal_mac_ax_set_bf_entry(
hal_info->mac, bf_entry->band,
(u8)(bf_entry->macid&0xFF), bfee_idx,
bf_entry->bf_idx,
bf_entry->csi_buf&CSI_BUF_IDX_HW_MSK);
}
/*2.TODO: HALBB Settings if needed*/
return status;
}
/**
* hal_bf_update_entry_snd_sts
* Update BF Entry Sounding Status
* input
* @hal_info: (struct hal_info_t *)
* @entry: struct hal_bf_entry
**/
void hal_bf_update_entry_snd_sts(struct hal_info_t *hal_info, void *entry)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry;
u8 bfee_idx = 0;
/*TODO: 8852A : SU : 0 ~ N-1; MU : N ~ M*/
if (NULL == bf_entry) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[ERROR] hal_bf_update_entry_snd_sts BF_Entry = NULL\n");
return;
}
if (NULL == bf_entry->bfee) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->macid = 0x%x\n", bf_entry->macid);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->bfee = NULL\n");
return;
}
bfee_idx = bf_entry->bfee->idx +
((bf_entry->bfee->type == HAL_BFEE_MU) ?
bf_obj->max_su_bfee_nr : 0);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "hal_bf_update_entry_snd_sts idx = 0x%x \n", bfee_idx);
status = rtw_hal_mac_ax_get_snd_sts(hal_info->mac,
bf_entry->band, bfee_idx);
bf_entry->bfee->snd_sts = (status == RTW_HAL_STATUS_SUCCESS) ? 1 : 0;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "hal_bf_update_entry_snd_sts bf_entry->bfee->snd_sts = 0x%x \n",
bf_entry->bfee->snd_sts);
}
enum rtw_hal_status
hal_bf_hw_mac_deinit_bfee(struct hal_info_t *hal_info, u8 band)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
do {
if (band >= 2) {
status = RTW_HAL_STATUS_FAILURE;
break;
}
if ((0 == (bf_obj->self_bf_cap[band]&BF_CAP_HE_BFEE)) &&
(0 == (bf_obj->self_bf_cap[band]&BF_CAP_VHT_BFEE))) {
/* already disable */
break;
}
status = rtw_hal_mac_ax_deinit_bfee(hal_info->hal_com, band);
if (status != RTW_HAL_STATUS_SUCCESS)
break;
bf_obj->self_bf_cap[band] &= ~(BF_CAP_HE_BFEE|BF_CAP_VHT_BFEE);
} while (0);
return status;
}
/**
* rtw_hal_bf_get_entry_snd_sts
* Get BF Entry Sounding Status
* input
* @hal_info: (struct hal_info_t *)
* @entry: struct hal_bf_entry
* return
* rtw_hal_status : RTW_HAL_STATUS_FAILURE or RTW_HAL_STATUS_SUCCESS
**/
enum rtw_hal_status
rtw_hal_bf_get_entry_snd_sts(void *entry)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry;
if (NULL == bf_entry) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[ERROR] rtw_hal_bf_get_entry_snd_sts BF_Entry = NULL\n");
return hstatus;
}
if (NULL == bf_entry->bfee) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->macid = 0x%x\n", bf_entry->macid);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"[ERROR] rtw_hal_bf_get_entry_snd_sts bf_entry->bfee = NULL\n");
return hstatus;
}
if (1 == bf_entry->bfee->snd_sts)
hstatus = RTW_HAL_STATUS_SUCCESS;
return hstatus;
}
/**
* hal_bf_hw_mac_init_bfee
* Initialize BFee HW Settings
* input
* @hal_info: struct hal_info_t
* @band: Band 0 / Band 1
**/
enum rtw_hal_status hal_bf_hw_mac_init_bfee(
struct hal_info_t *hal_info,
u8 band)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
do {
if (band >= 2) {
status = RTW_HAL_STATUS_FAILURE;
break;
}
status = rtw_hal_mac_ax_init_bf_role(
hal_info->hal_com, HAL_BF_ROLE_BFEE, band);
if(status != RTW_HAL_STATUS_SUCCESS)
break;
/*TODO: Check Wireless Mode*/
bf_obj->self_bf_cap[band] |= BF_CAP_HE_BFEE|BF_CAP_VHT_BFEE;
} while (0);
return status;
}
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
enum rtw_hal_status
rtw_hal_bf_bfee_ctrl(void *hal, u8 band, bool ctrl)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
bool cur_bfee_cap = false;
if ((bf_obj->self_bf_cap[band] & BF_CAP_HE_BFEE) ||
(bf_obj->self_bf_cap[band] & BF_CAP_VHT_BFEE)) {
cur_bfee_cap = true;
}
/* BB Workaround */
if ((ctrl != cur_bfee_cap) && (true == ctrl)) {
/* From Tx to Rx (need Enable BFee) */
rtw_hal_bb_dcr_en(hal_info, true);
} else if ((ctrl != cur_bfee_cap) && (false == ctrl)) {
rtw_hal_bb_dcr_en(hal_info, false);
}
if ((ctrl == true) &&
(false == rtw_hal_bb_csi_rsp(hal_info))) {
ctrl = false;
}
if (ctrl != cur_bfee_cap) {
status = ((true == ctrl) ?
hal_bf_hw_mac_init_bfee(hal_info, band) :
hal_bf_hw_mac_deinit_bfee(hal_info, band));
}
return status;
}
#endif
/**
* hal_bf_set_bfee_csi_para
* Set self bfee hw capability.
* input:
* @hal_info: struct hal_info_t *
* @cr_cctl: set bfee capabiliy method
* true = by register (only support 2 sets, Port 0 / Port 1-4 )
* false = by cmac control table
* @sta: struct rtw_phl_stainfo_t * (self)
*/
enum rtw_hal_status hal_bf_set_bfee_csi_para(struct hal_info_t *hal_info,
bool cr_cctl, struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
u32 rrsc = BIT(HAL_BF_RRSC_6M) | BIT(HAL_BF_RRSC_24M);
if (false == cr_cctl) {
status = rtw_hal_mac_ax_bfee_para_reg(hal_info->mac, sta);
} else {
status = rtw_hal_mac_ax_bfee_para_cctl(hal_info->mac, sta);
}
/* mac/bb csi rate settings initialize */
if (RTW_HAL_STATUS_SUCCESS == status) {
/* Initialize CSI rate RA parameters */
sta->hal_sta->ra_info.fixed_csi_rate_en = false;
sta->hal_sta->ra_info.ra_csi_rate_en = true;
sta->hal_sta->ra_info.band_num = sta->wrole->hw_band;
if (sta->chandef.bw >= CHANNEL_WIDTH_80)
sta->hal_sta->ra_info.csi_rate.bw = HAL_RATE_BW_80;
else if (sta->chandef.bw == CHANNEL_WIDTH_40)
sta->hal_sta->ra_info.csi_rate.bw = HAL_RATE_BW_40;
else
sta->hal_sta->ra_info.csi_rate.bw = HAL_RATE_BW_20;
sta->hal_sta->ra_info.csi_rate.gi_ltf = RTW_GILTF_LGI_4XHE32;
sta->hal_sta->ra_info.csi_rate.mcs_ss_idx = 5;
if (sta->wmode & WLAN_MD_11N) {
rrsc |= (BIT(HAL_BF_RRSC_HT_MSC0) |
BIT(HAL_BF_RRSC_HT_MSC3) |
BIT(HAL_BF_RRSC_HT_MSC5));
sta->hal_sta->ra_info.csi_rate.mode = HAL_HT_MODE;
}
if (sta->wmode & WLAN_MD_11AC) {
rrsc |= (BIT(HAL_BF_RRSC_VHT_MSC0) |
BIT(HAL_BF_RRSC_VHT_MSC3) |
BIT(HAL_BF_RRSC_VHT_MSC5));
sta->hal_sta->ra_info.csi_rate.mode = HAL_VHT_MODE;
}
if (sta->wmode & WLAN_MD_11AX) {
rrsc |= (BIT(HAL_BF_RRSC_HE_MSC0) |
BIT(HAL_BF_RRSC_HE_MSC3) |
BIT(HAL_BF_RRSC_HE_MSC5));
sta->hal_sta->ra_info.csi_rate.mode = HAL_HE_MODE;
}
/* Initialize mac rrsc function */
rtw_hal_mac_ax_bfee_set_csi_rrsc(hal_info->mac,
sta->wrole->hw_band, rrsc);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, " set bfee csi rrsc = 0x%x\n", rrsc);
}
return status;
}
/**
* hal_bf_hw_mac_init_bfer
* Initialize BFer HW Settings
* @hal_info: struct hal_info_t
* @band: Band 0 / Band 1
**/
enum rtw_hal_status hal_bf_hw_mac_init_bfer(
struct hal_info_t *hal_info,
u8 band)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
do {
if (band >= 2) {
status = RTW_HAL_STATUS_FAILURE;
break;
}
status = rtw_hal_mac_ax_init_bf_role(hal_info->hal_com,
HAL_BF_ROLE_BFER, band);
if(status != RTW_HAL_STATUS_SUCCESS)
break;
/*TODO: Check Wireless Mode*/
bf_obj->self_bf_cap[band] |= BF_CAP_HE_BFER|BF_CAP_VHT_BFER;
} while (0);
return status;
}
/**
* rtw_hal_bf_chk_bf_type
* Check the STA's BF Entry Type
* @hal_info: struct hal_info_t
* @sta: rtw_phl_stainfo_t *
* @mu: check condition MU or SU?
* return :
* @ret: true : bf entry type is same to flag(mu)
* false : bf entry is not same to flag(mu) or bf entry is NULL
**/
bool rtw_hal_bf_chk_bf_type(
void *hal_info,
struct rtw_phl_stainfo_t *sta,
bool mu)
{
struct hal_bf_entry *bf_entry =
(struct hal_bf_entry *)sta->hal_sta->bf_entry;
bool ret = false;
do {
if (NULL == bf_entry)
break;
if (bf_entry->bfee == NULL)
break;
if (true == mu) {
if (HAL_BFEE_MU != bf_entry->bfee->type)
break;
} else {
if (HAL_BFEE_SU != bf_entry->bfee->type)
break;
}
ret = true;
} while(0);
return ret;
}
u8 rtw_hal_bf_get_sumu_idx(void *hal, void *entry)
{
struct hal_bf_entry *bf_entry = (struct hal_bf_entry *)entry;
u8 ret = 0xFF;
if (bf_entry->bfee != NULL)
ret = bf_entry->bfee->idx;
return ret;
}
void
rtw_hal_bf_preset_mu_ba_info(
void *hal,
struct rtw_phl_stainfo_t *psta,
void *hal_ba_info)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
void *drv_priv = hal_to_drvpriv(hal_info);
struct rtw_hal_muba_info *ba_info =
(struct rtw_hal_muba_info *)hal_ba_info;
if (1 == bf_obj->fixed_para.fix_ba_info.fix_ba) {
/*Fixed BA info*/
_os_mem_cpy(drv_priv, ba_info, &bf_obj->fixed_para.fix_ba_info, sizeof(*ba_info));
} else {
/* TODO: Config BA by STA Capabiliy or default value*/
ba_info->fix_ba = 0;
ba_info->ru_psd = 0;
ba_info->tf_rate = RTW_DATA_RATE_OFDM24;
ba_info->rf_gain_fix = 0;
ba_info->rf_gain_idx = 0;
ba_info->tb_ppdu_bw = (psta->chandef.bw == CHANNEL_WIDTH_80) ? 2 : 0;
ba_info->dcm = 0;
ba_info->ss = 0;
ba_info->mcs = 3;
ba_info->gi_ltf = 2;
ba_info->doppler = 0;
ba_info->stbc = 0;
ba_info->sta_coding = 0;
ba_info->tb_t_pe_nom = 0;
ba_info->pr20_bw_en = 0;
ba_info->ma_type = 0;
}
}
void
rtw_hal_bf_set_txmu_para(void *hal, u8 gid , u8 en,
enum rtw_hal_protection_type rts_type,
enum rtw_hal_ack_resp_type ack_type)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_fixed_m_para *para = &bf_obj->fixed_para;
para->fix_m = (1 == en) ? HAL_BF_FIX_M_MU : HAL_BF_FIX_M_DISABLE;
para->gid = gid;
para->fix_resp = en;
para->fix_prot = en;
if (en) {
para->prot_type = rts_type;
para->resp_type = ack_type;
}
}
enum rtw_hal_status
rtw_hal_bf_set_fix_mode(void *hal, bool mu, bool he)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_bf_obj *bf_obj = (struct hal_bf_obj *)hal_com->bf_obj;
struct hal_bf_fixed_m_para *para = &bf_obj->fixed_para;
if (mu) {
status = rtw_hal_mac_ax_set_mu_fix_mode(
hal_info->mac,
para->gid,
para->prot_type,
para->resp_type,
(para->fix_m == HAL_BF_FIX_M_MU) ? true : false,
he,
para->fix_resp,
para->fix_prot);
} else {
/*TODO: Force SU*/
}
return status;
}
enum rtw_hal_status
hal_bf_set_mu_sta_fw(void *hal, struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_bf_entry *bf_entry =
(struct hal_bf_entry *)sta->hal_sta->bf_entry;
struct hal_sumu_entry *mu_entry = NULL;
do {
if (NULL == bf_entry)
break;
if (NULL == bf_entry->bfee)
break;
mu_entry = bf_entry->bfee;
if (HAL_BFEE_MU != mu_entry->type)
break;
status = rtw_hal_mac_ax_mu_sta_upd(
hal_info->mac,
(u8)(sta->macid&0xFF),
mu_entry->idx,
sta->hal_sta->prot_type,
sta->hal_sta->resp_type,
sta->hal_sta->mugrp_bmp);
} while (0);
return status;
}
void rtw_hal_beamform_set_vht_gid(void *hal, u8 band,
struct rtw_phl_gid_pos_tbl *tbl)
{
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "--> %s()\n", __func__);
if (RTW_HAL_STATUS_SUCCESS !=
rtw_hal_mac_bfee_set_vht_gid(hal, band, tbl)) {
PHL_INFO("%s : Error to set VHT GID Position to MAC !!! \n",
__func__);
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<-- %s()\n", __func__);
}
enum rtw_hal_status rtw_hal_beamform_set_aid(void *hal, struct rtw_phl_stainfo_t *sta, u16 aid)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "--> %s() : set aid = %d\n", __func__, aid);
/*TODO: halmac need provide api that only change AID */
status = rtw_hal_mac_addr_cam_set_aid(hal_info, sta, aid);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_mac_addr_cam_change_entry failed\n");
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<-- %s()\n", __func__);
return status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_beamform.c
|
C
|
agpl-3.0
| 32,786
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_BEAMFORM_H__
#define __HAL_BEAMFORM_H__
#define BF_MU_IDX_INVALID 0xFF
#define BF_CAP_HT_BFEE BIT(0)
#define BF_CAP_HT_BFER BIT(1)
#define BF_CAP_VHT_BFEE BIT(2)
#define BF_CAP_VHT_BFER BIT(3)
#define BF_CAP_HE_BFEE BIT(4)
#define BF_CAP_HE_BFER BIT(5)
#define IS_SUPPORT_ACT_AS_BFER(_cap) \
(_cap & BF_CAP_HE_BFER) || (_cap & BF_CAP_VHT_BFER) \
|| (_cap & BF_CAP_HT_BFER)
#define IS_SUPPORT_ACT_AS_BFEE(_cap) \
(_cap & BF_CAP_HE_BFEE) || (_cap & BF_CAP_VHT_BFEE) \
|| (_cap & BF_CAP_HT_BFEE)
//B[0:7] = {6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M}
//B[8:15] = HT MCS0~MCS7
//B[16:23] = VHT 1SSMCS0~MCS7
//B[24:31] = HE 1SSMCS0~MCS7
enum hal_bf_rrsc_rata {
HAL_BF_RRSC_6M = 0,
HAL_BF_RRSC_9M = 1,
HAL_BF_RRSC_12M,
HAL_BF_RRSC_18M,
HAL_BF_RRSC_24M,
HAL_BF_RRSC_36M,
HAL_BF_RRSC_48M,
HAL_BF_RRSC_54M,
HAL_BF_RRSC_HT_MSC0,
HAL_BF_RRSC_HT_MSC1,
HAL_BF_RRSC_HT_MSC2,
HAL_BF_RRSC_HT_MSC3,
HAL_BF_RRSC_HT_MSC4,
HAL_BF_RRSC_HT_MSC5,
HAL_BF_RRSC_HT_MSC6,
HAL_BF_RRSC_HT_MSC7,
HAL_BF_RRSC_VHT_MSC0,
HAL_BF_RRSC_VHT_MSC1,
HAL_BF_RRSC_VHT_MSC2,
HAL_BF_RRSC_VHT_MSC3,
HAL_BF_RRSC_VHT_MSC4,
HAL_BF_RRSC_VHT_MSC5,
HAL_BF_RRSC_VHT_MSC6,
HAL_BF_RRSC_VHT_MSC7,
HAL_BF_RRSC_HE_MSC0,
HAL_BF_RRSC_HE_MSC1,
HAL_BF_RRSC_HE_MSC2,
HAL_BF_RRSC_HE_MSC3,
HAL_BF_RRSC_HE_MSC4,
HAL_BF_RRSC_HE_MSC5,
HAL_BF_RRSC_HE_MSC6,
HAL_BF_RRSC_HE_MSC7 = 31,
HAL_BF_RRSC_MAX = 32
};
enum hal_bf_role {
HAL_BF_ROLE_BFEE,
HAL_BF_ROLE_BFER
};
enum hal_bfee_type {
HAL_BFEE_SU,
HAL_BFEE_MU
};
struct hal_sumu_entry {
_os_list list;
enum hal_bfee_type type;
u8 idx;
u8 snd_sts; /*0: Fail or Not Sound, 1: Sound Success*/
};
struct hal_bf_entry {
_os_list list;
u8 bf_idx;
u16 macid;
u16 aid12;
u8 band;
u16 csi_buf;
/* csi_buf for swap mode */
bool en_swap;
u16 csi_buf_swap;
u8 couter; /*for swap*/
struct hal_sumu_entry *bfee;
};
enum hal_bf_forced_mode{
HAL_BF_FIX_M_DISABLE = 0,
HAL_BF_FIX_M_SU = 1,
HAL_BF_FIX_M_MU = 2
};
struct hal_bf_fixed_m_para {
enum hal_bf_forced_mode fix_m;
u8 gid;
u8 fix_resp;
u8 fix_prot;
enum rtw_hal_protection_type prot_type;
enum rtw_hal_ack_resp_type resp_type;
struct rtw_hal_muba_info fix_ba_info;
};
struct hal_bf_obj {
/*tx bf entry*/
u8 max_bf_entry_nr;
struct hal_bf_entry *bf_entry;
_os_list bf_idle_list;
_os_list bf_busy_list;
u8 num_idle_bf_entry;
/*su entry*/
u8 max_su_bfee_nr;
struct hal_sumu_entry *su_entry;
_os_list su_idle_list;
_os_list su_busy_list;
u8 num_idle_su_entry;
/*mu entry*/
u8 max_mu_bfee_nr;
struct hal_sumu_entry *mu_entry;
_os_list mu_idle_list;
_os_list mu_busy_list;
u8 num_idle_mu_entry;
_os_lock bf_lock;
u8 self_bf_cap[2];
/*for fixed mode*/
struct hal_bf_fixed_m_para fixed_para;
};
enum rtw_hal_status hal_bf_init(
struct hal_info_t *hal_info,
u8 bf_entry_nr,
u8 su_entry_nr,
u8 mu_entry_nr);
void hal_bf_deinit(struct hal_info_t *hal_info);
struct hal_bf_entry *
hal_bf_query_idle_bf_entry(
struct hal_info_t *hal_info,
bool mu);
enum rtw_hal_status
hal_bf_release_target_bf_entry(
struct hal_info_t *hal_info,
void *entry);
enum rtw_hal_status hal_bf_hw_mac_init_bfee(
struct hal_info_t *hal_info,
u8 band);
enum rtw_hal_status hal_bf_hw_mac_init_bfer(
struct hal_info_t *hal_info,
u8 band);
enum rtw_hal_status hal_bf_set_entry_hwcfg(
struct hal_info_t *hal_info, void *entry);
void hal_bf_update_entry_snd_sts(struct hal_info_t *hal_info, void *entry);
enum rtw_hal_status hal_bf_cfg_swbf_entry(struct rtw_phl_stainfo_t *sta,
bool swap);
enum rtw_hal_status
hal_bf_set_mu_sta_fw(void *hal, struct rtw_phl_stainfo_t *sta);
enum rtw_hal_status
rtw_hal_bf_set_fix_mode(void *hal, bool mu, bool he);
bool rtw_hal_bf_chk_bf_type(void *hal_info,
struct rtw_phl_stainfo_t *sta, bool mu);
enum rtw_hal_status
hal_bf_set_bfee_csi_para(struct hal_info_t *hal_info, bool cr_cctl,
struct rtw_phl_stainfo_t *sta);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_beamform.h
|
C
|
agpl-3.0
| 4,543
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_C2H_C_
#include "hal_headers.h"
struct hal_c2h_hdl c2h_list[] =
{
{C2H_CAT_OUTSRC, C2H_CLS_PHYDM_MIN, C2H_CLS_PHYDM_MAX,
rtw_hal_bb_process_c2h},
{C2H_CAT_OUTSRC, C2H_CLS_BTC_MIN, C2H_CLS_BTC_MAX,
rtw_hal_btc_process_c2h},
{C2H_CAT_MAC, C2H_CLS_MAC_MIN, C2H_CLS_MAC_MAX,
rtw_hal_mac_process_c2h},
{C2H_CAT_MAX, C2H_CLS_MAX, C2H_CLS_MAX, NULL}
};
void hal_c2h_post_process(void *phl, void *hal, void *c2h)
{
struct rtw_phl_com_t *phl_com = (struct rtw_phl_com_t *)phl;
struct rtw_c2h_info *c = (struct rtw_c2h_info *)c2h;
u8 i = 0;
u32 ret = 0;
for (i = 0; C2H_CAT_MAX != c2h_list[i].cat; i++) {
if (c->c2h_cat == c2h_list[i].cat) {
if (c->c2h_class >= c2h_list[i].cls_min &&
c->c2h_class <= c2h_list[i].cls_max) {
ret = c2h_list[i].c2h_hdl(hal, c2h);
break;
}
}
}
if (ret > 0) {
/* submit phl msg hub */
struct phl_msg msg = {0};
struct phl_msg_attribute attr = {0};
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_RX);
SET_MSG_EVT_ID_FIELD(msg.msg_id, (u16)ret);
if (rtw_phl_msg_hub_hal_send(phl_com, &attr, &msg) !=
RTW_PHL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_phl_msg_hub_hal_send failed\n", __func__);
}
}
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_c2h.c
|
C
|
agpl-3.0
| 1,831
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_C2H_H_
#define _HAL_C2H_H_
void hal_c2h_post_process(void *phl, void *hal, void *c2h);
#endif /*_HAL_C2H_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_c2h.h
|
C
|
agpl-3.0
| 775
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_CAM_C_
#include "hal_headers.h"
/**
* This function calls halmac api to configure security cam
* @hal: see struct hal_info_t
* @sta: sta info of specified address cam entry
* @type: encryption type of this key
* @ext_key: whether 256bit key or not
* @spp: spp mode
* @keyid: key index
* @keytype: specify unicast or multicast or bip key type
* @keybuf: key buffer length according to ext_key
* return enum RTW_HAL_STATUS
*/
enum rtw_hal_status
rtw_hal_set_key(void *hal, struct rtw_phl_stainfo_t *sta, u8 type, u8 ext_key, u8 spp,
u8 keyid, u8 keytype, u8 *keybuf)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 macid = (u8)sta->macid;
if (keybuf == NULL) {
/* delete key */
hal_status = rtw_hal_mac_delete_key(hal_info, macid, type, ext_key,
spp, keyid, keytype);
} else {
/* add key */
if (ext_key) {
hal_status = rtw_hal_mac_add_key(hal_info, macid, type, ext_key,
spp, keyid, keytype, keybuf);
hal_status = rtw_hal_mac_add_key(hal_info, macid, type, ext_key, spp,
keyid, keytype, (keybuf+16));
} else {
hal_status = rtw_hal_mac_add_key(hal_info, macid, type, 0,
spp, keyid, keytype, keybuf);
}
}
return hal_status;
}
u32
rtw_hal_search_key_idx(void *hal, struct rtw_phl_stainfo_t *sta,
u8 keyid, u8 keytype)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u32 sec_cam_idx = 0;
u8 macid = (u8)sta->macid;
sec_cam_idx = rtw_hal_mac_search_key_idx(hal_info,
macid,
keyid,
keytype);
return sec_cam_idx;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_cam.c
|
C
|
agpl-3.0
| 2,248
|
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "hal_headers.h"
static void _hal_bus_cap_pre_decision(struct rtw_phl_com_t *phl_com,
void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap;
struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap;
struct bus_cap_t *bus_cap = &hal_com->bus_cap;
#ifdef CONFIG_PCI_HCI
bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->l0s_ctrl : bus_sw->l0s_ctrl;
bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->l1_ctrl : bus_sw->l1_ctrl;
bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl;
bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->wake_ctrl : bus_sw->wake_ctrl;
bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->crq_ctrl : bus_sw->crq_ctrl;
bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl;
bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl;
bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl;
bus_cap->txbd_num = (bus_sw->txbd_num) ?
((bus_sw->txbd_num > bus_hw->max_txbd_num) ?
bus_hw->max_txbd_num : bus_sw->txbd_num) :
bus_hw->max_txbd_num;
bus_cap->rxbd_num = (bus_sw->rxbd_num) ?
((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ?
bus_hw->max_rxbd_num : bus_sw->rxbd_num) :
bus_hw->max_rxbd_num;
bus_cap->rpbd_num = (bus_sw->rpbd_num) ?
((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ?
bus_hw->max_rpbd_num : bus_sw->rpbd_num) :
bus_hw->max_rpbd_num;
/* rx buffer number must be larger or equal to rx bd number */
bus_cap->rxbuf_num = (bus_sw->rxbuf_num < bus_cap->rxbd_num) ?
bus_cap->rxbd_num : bus_sw->rxbuf_num;
bus_cap->rpbuf_num = (bus_sw->rpbuf_num < bus_cap->rpbd_num) ?
bus_cap->rpbd_num : bus_sw->rpbuf_num;
bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl;
bus_cap->ltr_act.val = bus_sw->ltr_act.val;
bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl;
bus_cap->ltr_idle.val = bus_sw->ltr_idle.val;
bus_cap->ltr_init_state = bus_sw->ltr_init_state;
bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ?
(bus_sw->ltr_sw_ctrl ? true : false) : false;
bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ?
(bus_sw->ltr_hw_ctrl ? true : false) : false;
#elif defined (CONFIG_USB_HCI)
bus_cap->tx_buf_size = (bus_sw->tx_buf_size) ?
((bus_sw->tx_buf_size < bus_hw->tx_buf_size) ?
bus_sw->tx_buf_size : bus_hw->tx_buf_size) :
bus_hw->tx_buf_size;
bus_cap->tx_buf_num = (bus_sw->tx_buf_num) ?
((bus_sw->tx_buf_num < bus_hw->tx_buf_num) ?
bus_sw->tx_buf_num : bus_hw->tx_buf_num) :
bus_hw->tx_buf_num;
bus_cap->tx_mgnt_buf_size = (bus_sw->tx_mgnt_buf_size) ?
((bus_sw->tx_mgnt_buf_size < bus_hw->tx_mgnt_buf_size) ?
bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size) :
bus_hw->tx_mgnt_buf_size;
bus_cap->tx_mgnt_buf_num = (bus_sw->tx_mgnt_buf_num) ?
((bus_sw->tx_mgnt_buf_num < bus_hw->tx_mgnt_buf_num) ?
bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num) :
bus_hw->tx_mgnt_buf_num;
bus_cap->tx_h2c_buf_num = (bus_sw->tx_h2c_buf_num) ?
((bus_sw->tx_h2c_buf_num < bus_hw->tx_h2c_buf_num) ?
bus_sw->tx_h2c_buf_num : bus_hw->tx_h2c_buf_num) :
bus_hw->tx_h2c_buf_num;
bus_cap->rx_buf_size = (bus_sw->rx_buf_size) ?
((bus_sw->rx_buf_size < bus_hw->rx_buf_size) ?
bus_sw->rx_buf_size : bus_hw->rx_buf_size) :
bus_hw->rx_buf_size;
bus_cap->rx_buf_num = (bus_sw->rx_buf_num) ?
((bus_sw->rx_buf_num < bus_hw->rx_buf_num) ?
bus_sw->rx_buf_num : bus_hw->rx_buf_num) :
bus_hw->rx_buf_num;
bus_cap->in_token_num = (bus_sw->in_token_num) ?
((bus_sw->in_token_num < bus_hw->in_token_num) ?
bus_sw->in_token_num : bus_hw->in_token_num) :
bus_hw->in_token_num;
#elif defined(CONFIG_SDIO_HCI)
bus_cap->tx_buf_size = bus_sw->tx_buf_size ?
bus_sw->tx_buf_size : bus_hw->tx_buf_size;
bus_cap->tx_buf_num = bus_sw->tx_buf_num ?
bus_sw->tx_buf_num : bus_hw->tx_buf_num;
bus_cap->tx_mgnt_buf_size = bus_sw->tx_mgnt_buf_size ?
bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size;
bus_cap->tx_mgnt_buf_num = bus_sw->tx_mgnt_buf_num ?
bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num;
bus_cap->rx_buf_size = bus_sw->rx_buf_size ?
bus_sw->rx_buf_size : bus_hw->rx_buf_size;
bus_cap->rx_buf_num = bus_sw->rx_buf_num ?
bus_sw->rx_buf_num : bus_hw->rx_buf_num;
#endif
}
#ifdef CONFIG_PCI_HCI
static void _hal_bus_final_cap_decision(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com)
{
struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap;
struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap;
struct bus_cap_t *bus_cap = &hal_com->bus_cap;
bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->l0s_ctrl : bus_sw->l0s_ctrl;
bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->l1_ctrl : bus_sw->l1_ctrl;
bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl;
bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->wake_ctrl : bus_sw->wake_ctrl;
bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
bus_hw->crq_ctrl : bus_sw->crq_ctrl;
bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl;
bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl;
bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl;
bus_cap->txbd_num = (bus_sw->txbd_num) ?
((bus_sw->txbd_num > bus_hw->max_txbd_num) ?
bus_hw->max_txbd_num : bus_sw->txbd_num) :
bus_hw->max_txbd_num;
bus_cap->rxbd_num = (bus_sw->rxbd_num) ?
((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ?
bus_hw->max_rxbd_num : bus_sw->rxbd_num) :
bus_hw->max_rxbd_num;
bus_cap->rpbd_num = (bus_sw->rpbd_num) ?
((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ?
bus_hw->max_rpbd_num : bus_sw->rpbd_num) :
bus_hw->max_rpbd_num;
bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl;
bus_cap->ltr_act.val = bus_sw->ltr_act.val;
bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl;
bus_cap->ltr_idle.val = bus_sw->ltr_idle.val;
bus_cap->ltr_init_state = bus_sw->ltr_init_state;
bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ?
(bus_sw->ltr_sw_ctrl ? true : false) : false;
bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ?
(bus_sw->ltr_hw_ctrl ? true : false) : false;
}
#endif
static void _hal_ps_final_cap_decision(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com)
{
struct rtw_ps_cap_t *ps_cap = &phl_com->dev_cap.ps_cap;
struct rtw_ps_cap_t *ps_sw_cap = &phl_com->dev_sw_cap.ps_cap;
struct rtw_ps_cap_t *ps_hw_cap = &hal_com->dev_hw_cap.ps_cap;
/* sw */
ps_cap->init_rf_state = ps_sw_cap->init_rf_state;
ps_cap->init_rt_stop_rson = ps_sw_cap->init_rt_stop_rson;
ps_cap->leave_fail_act = ps_sw_cap->leave_fail_act;
ps_cap->ips_en = ps_sw_cap->ips_en;
ps_cap->ips_wow_en = ps_sw_cap->ips_wow_en;
ps_cap->lps_en = ps_sw_cap->lps_en;
ps_cap->lps_awake_interval = ps_sw_cap->lps_awake_interval;
ps_cap->lps_listen_bcn_mode = ps_sw_cap->lps_listen_bcn_mode;
ps_cap->lps_smart_ps_mode = ps_sw_cap->lps_smart_ps_mode;
ps_cap->lps_rssi_enter_threshold = ps_sw_cap->lps_rssi_enter_threshold;
ps_cap->lps_rssi_leave_threshold = ps_sw_cap->lps_rssi_leave_threshold;
ps_cap->lps_rssi_diff_threshold = ps_sw_cap->lps_rssi_diff_threshold;
ps_cap->lps_wow_en = ps_sw_cap->lps_wow_en;
ps_cap->lps_wow_awake_interval = ps_sw_cap->lps_wow_awake_interval;
ps_cap->lps_wow_listen_bcn_mode = ps_sw_cap->lps_wow_listen_bcn_mode;
ps_cap->lps_wow_smart_ps_mode = ps_sw_cap->lps_wow_smart_ps_mode;
/* hw */
ps_cap->lps_pause_tx = ps_hw_cap->lps_pause_tx;
/* sw & hw */
ps_cap->ips_cap = (ps_sw_cap->ips_cap & ps_hw_cap->ips_cap);
ps_cap->lps_wow_cap = (ps_sw_cap->lps_wow_cap & ps_hw_cap->lps_wow_cap);
ps_cap->lps_cap = (ps_sw_cap->lps_cap & ps_hw_cap->lps_cap);
ps_cap->lps_wow_cap = (ps_sw_cap->lps_wow_cap & ps_hw_cap->lps_wow_cap);
}
static void _hal_edcca_final_cap_decision(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com)
{
struct rtw_edcca_cap_t *edcca_cap = &phl_com->dev_cap.edcca_cap;
struct rtw_edcca_cap_t *edcca_sw_cap = &phl_com->dev_sw_cap.edcca_cap;
struct rtw_edcca_cap_t *edcca_hw_cap = &hal_com->dev_hw_cap.edcca_cap;
edcca_cap->edcca_adap_th_2g = (edcca_sw_cap->edcca_adap_th_2g)?
(edcca_sw_cap->edcca_adap_th_2g):
(edcca_hw_cap->edcca_adap_th_2g);
edcca_cap->edcca_adap_th_5g = (edcca_sw_cap->edcca_adap_th_5g)?
(edcca_sw_cap->edcca_adap_th_5g):
(edcca_hw_cap->edcca_adap_th_5g);
edcca_cap->edcca_carrier_sense_th = (edcca_sw_cap->edcca_carrier_sense_th)?
(edcca_sw_cap->edcca_carrier_sense_th):
(edcca_hw_cap->edcca_carrier_sense_th);
}
void rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal)
{
struct dev_cap_t *dev_cap = &phl_com->dev_cap;
struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
/* leaving for fw hw cap
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
*/
dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src;
dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en;
dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en;
}
void rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal)
{
_hal_bus_cap_pre_decision(phl_com, hal);
}
void rtw_hal_fw_final_cap_config(struct rtw_phl_com_t *phl_com, void *hal)
{
struct dev_cap_t *dev_cap = &phl_com->dev_cap;
struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
/* leaving for fw hw cap
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
*/
dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src;
dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en;
dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en;
}
void rtw_hal_final_cap_decision(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct phy_hw_cap_t *phy_hw = hal_com->phy_hw_cap;
struct phy_sw_cap_t *phy_sw = phl_com->phy_sw_cap;
struct phy_cap_t *phy_cap = phl_com->phy_cap;
struct dev_cap_t *dev_cap = &phl_com->dev_cap;
struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
#ifdef RTW_WKARD_PHY_CAP
phy_cap[0].proto_sup = phy_sw[0].proto_sup;
phy_cap[1].proto_sup = phy_sw[1].proto_sup;
phy_cap[0].band_sup = phy_sw[0].band_sup;
phy_cap[1].band_sup = phy_sw[1].band_sup;
phy_cap[0].bw_sup = phy_sw[0].bw_sup;
phy_cap[1].bw_sup = phy_sw[1].bw_sup;
phy_cap[0].txss = (phy_sw[0].txss)?((phy_sw[0].txss > phy_hw[0].tx_num)?
phy_hw[0].tx_num:phy_sw[0].txss):phy_hw[0].tx_num;
phy_cap[0].rxss = (phy_sw[0].rxss)?((phy_sw[0].rxss > phy_hw[0].rx_num)?
phy_hw[0].rx_num:phy_sw[0].rxss):phy_hw[0].rx_num;
phy_cap[1].txss = (phy_sw[1].txss)?((phy_sw[1].txss > phy_hw[1].tx_num)?
phy_hw[1].tx_num:phy_sw[1].txss):phy_hw[1].tx_num;
phy_cap[1].rxss = (phy_sw[1].rxss)?((phy_sw[1].rxss > phy_hw[1].rx_num)?
phy_hw[1].rx_num:phy_sw[1].rxss):phy_hw[1].rx_num;
phy_cap[0].hw_rts_time_th = (phy_sw[0].hw_rts_time_th)?
phy_sw[0].hw_rts_time_th:phy_hw[0].hw_rts_time_th;
phy_cap[1].hw_rts_time_th = (phy_sw[1].hw_rts_time_th)?
phy_sw[1].hw_rts_time_th:phy_hw[1].hw_rts_time_th;
phy_cap[0].hw_rts_len_th = (phy_sw[0].hw_rts_len_th)?
phy_sw[0].hw_rts_len_th:phy_hw[0].hw_rts_len_th;
phy_cap[1].hw_rts_len_th = (phy_sw[1].hw_rts_len_th)?
phy_sw[1].hw_rts_len_th:phy_hw[1].hw_rts_len_th;
/* fw */
rtw_hal_fw_final_cap_config(phl_com,hal);
#endif
#ifdef RTW_WKARD_LAMODE
if (dev_sw_cap->la_mode && dev_hw_cap->la_mode)
dev_cap->la_mode = true;
#endif
/* wow, to be refined along with hw cap */
dev_cap->wow_cap.magic_sup = dev_sw_cap->wow_cap.magic_sup;
dev_cap->wow_cap.pattern_sup = dev_sw_cap->wow_cap.pattern_sup;
dev_cap->wow_cap.arp_ofld_sup = dev_sw_cap->wow_cap.arp_ofld_sup;
dev_cap->wow_cap.ns_oflod_sup = dev_sw_cap->wow_cap.ns_oflod_sup;
dev_cap->wow_cap.gtk_ofld_sup = dev_sw_cap->wow_cap.gtk_ofld_sup;
dev_cap->wow_cap.ping_pattern_wake_sup = dev_sw_cap->wow_cap.ping_pattern_wake_sup;
if (dev_sw_cap->pkg_type != 0xFF)
dev_cap->pkg_type = dev_sw_cap->pkg_type;
else
dev_cap->pkg_type = dev_hw_cap->pkg_type;
if (dev_sw_cap->rfe_type != 0xFF)
dev_cap->rfe_type = dev_sw_cap->rfe_type;
else
dev_cap->rfe_type = dev_hw_cap->rfe_type;
dev_cap->bypass_rfe_chk = dev_sw_cap->bypass_rfe_chk;
hal_com->dbcc_en = false;/*init default value*/
#ifdef CONFIG_DBCC_SUPPORT
if (dev_sw_cap->dbcc_sup && dev_hw_cap->dbcc_sup)
dev_cap->dbcc_sup = true;
/*TODO - update dbcc_en from sw & hw cap
if (dev_cap->dbcc_sup && dft->dbcc_en)
hal_com->dbcc_en = true;
*/
#endif
#ifdef CONFIG_MCC_SUPPORT
if (dev_sw_cap->mcc_sup && dev_hw_cap->mcc_sup)
dev_cap->mcc_sup = true;
#endif /*CONFIG_MCC_SUPPORT*/
#ifdef CONFIG_PHL_TWT
dev_cap->twt_sup = (dev_sw_cap->twt_sup & dev_hw_cap->twt_sup);
#endif /*CONFIG_PHL_TWT*/
if (dev_sw_cap->hw_hdr_conv && dev_hw_cap->hw_hdr_conv)
dev_cap->hw_hdr_conv = true;
if (dev_sw_cap->tx_mu_ru && dev_hw_cap->tx_mu_ru)
dev_cap->tx_mu_ru = true;
dev_cap->xcap = dev_hw_cap->xcap;
dev_cap->domain = dev_hw_cap->domain;
dev_cap->btc_mode = dev_sw_cap->btc_mode;
#ifdef CONFIG_PCI_HCI
_hal_bus_final_cap_decision(phl_com, hal_com);
#endif
if (dev_sw_cap->pwrbyrate_off != 0xFF)
dev_cap->pwrbyrate_off = dev_sw_cap->pwrbyrate_off;
else
dev_cap->pwrbyrate_off = PW_BY_RATE_ON;
if (dev_sw_cap->pwrlmt_type != 0xFF)
dev_cap->pwrlmt_type = dev_sw_cap->pwrlmt_type;
else
dev_cap->pwrlmt_type = PWLMT_BY_EFUSE;
if (dev_sw_cap->rf_board_opt != 0xFF)
dev_cap->rf_board_opt = dev_sw_cap->rf_board_opt;
else
dev_cap->rf_board_opt = dev_hw_cap->rf_board_opt;
if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru) {
/* auto : use hw default setting */
dev_cap->sta_ulru = dev_hw_cap->sta_ulru;
} else {
/* forced use sw settings */
dev_cap->sta_ulru = dev_sw_cap->sta_ulru;
}
PHL_INFO("sta_ulru final : 0x%x ; sw 0x%x ; hw 0x%x\n",
dev_cap->sta_ulru, dev_sw_cap->sta_ulru, dev_hw_cap->sta_ulru);
#ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
/* 2.4G 40MHz UL OFDAM : bb ask to disable */
if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru_2g40mhz) {
/* auto : use hw default setting */
dev_cap->sta_ulru_2g40mhz = dev_hw_cap->sta_ulru_2g40mhz;
} else {
/* forced use sw settings */
dev_cap->sta_ulru_2g40mhz = dev_sw_cap->sta_ulru_2g40mhz;
}
PHL_INFO("sta_ulru_2g40mhz final : 0x%x ; sw 0x%x ; hw 0x%x\n",
dev_cap->sta_ulru_2g40mhz, dev_sw_cap->sta_ulru_2g40mhz, dev_hw_cap->sta_ulru_2g40mhz);
#endif
_hal_ps_final_cap_decision(phl_com, hal_com);
_hal_edcca_final_cap_decision(phl_com, hal_com);
if (dev_hw_cap->hw_stype_cap != EFUSE_HW_STYPE_GENERAL)
dev_cap->hw_stype_cap = dev_hw_cap->hw_stype_cap;
else
dev_cap->hw_stype_cap = EFUSE_HW_STYPE_NONE;
if (dev_hw_cap->wl_func_cap != EFUSE_WL_FUNC_GENERAL)
dev_cap->wl_func_cap = dev_hw_cap->wl_func_cap;
else
dev_cap->wl_func_cap = EFUSE_WL_FUNC_NONE;
dev_cap->rpq_agg_num = dev_sw_cap->rpq_agg_num ?
dev_sw_cap->rpq_agg_num : dev_hw_cap->rpq_agg_num;
}
/**
* rtw_hal_get_bf_proto_cap
* input:
* @phl: (struct phl_info_t *phl_info)
* @band:
* input_output:
* @proto_cap: (struct protocol_cap_t *proto_cap) the variable to save the bf_cap result.
* return:
* @rtw_hal_status:
*/
enum rtw_hal_status
rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
u8 band, struct protocol_cap_t *proto_cap)
{
#ifdef RTW_WKARD_PHY_CAP
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct protocol_cap_t *hw_cap = NULL;
struct protocol_cap_t *sw_cap = NULL;
if (band >= HW_BAND_MAX) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : invalid band index \n");
return RTW_HAL_STATUS_FAILURE;
}
if (proto_cap == NULL) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : input proto_cap is NULL \n");
return RTW_HAL_STATUS_FAILURE;
}
hw_cap = &hal_com->proto_hw_cap[band];
sw_cap = &phl_com->proto_sw_cap[band];
proto_cap->he_su_bfmr =
(sw_cap->he_su_bfmr && hw_cap->he_su_bfmr) ? 1 : 0;
proto_cap->he_su_bfme =
(sw_cap->he_su_bfme && hw_cap->he_su_bfme) ? 1 : 0;
proto_cap->he_mu_bfmr =
(sw_cap->he_mu_bfmr && hw_cap->he_mu_bfmr) ? 1 : 0;
proto_cap->he_mu_bfme =
(sw_cap->he_mu_bfme && hw_cap->he_mu_bfme) ? 1 : 0;
proto_cap->non_trig_cqi_fb =
(sw_cap->non_trig_cqi_fb && hw_cap->non_trig_cqi_fb) ? 1 : 0;
proto_cap->trig_cqi_fb =
(sw_cap->trig_cqi_fb && hw_cap->trig_cqi_fb) ? 1 : 0;
proto_cap->vht_su_bfme =
(sw_cap->vht_su_bfme && hw_cap->vht_su_bfme) ? 1 : 0;
proto_cap->vht_su_bfmr =
(sw_cap->vht_su_bfmr && hw_cap->vht_su_bfmr) ? 1 : 0;
proto_cap->vht_mu_bfme =
(sw_cap->vht_mu_bfme && hw_cap->vht_mu_bfme) ? 1 : 0;
proto_cap->vht_mu_bfmr =
(sw_cap->vht_mu_bfmr && hw_cap->vht_mu_bfmr) ? 1 : 0;
proto_cap->ht_su_bfme =
(sw_cap->ht_su_bfme && hw_cap->ht_su_bfme) ? 1 : 0;
proto_cap->ht_su_bfmr =
(sw_cap->ht_su_bfmr && hw_cap->ht_su_bfmr) ? 1 : 0;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfmr = 0x%x \n",
proto_cap->he_su_bfmr);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfme = 0x%x \n",
proto_cap->he_su_bfme);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfmr = 0x%x \n",
proto_cap->he_mu_bfmr);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfme = 0x%x \n",
proto_cap->he_mu_bfme);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->non_trig_cqi_fb = 0x%x \n",
proto_cap->non_trig_cqi_fb);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->trig_cqi_fb = 0x%x \n",
proto_cap->trig_cqi_fb);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfme = 0x%x \n",
proto_cap->vht_su_bfme);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfmr = 0x%x \n",
proto_cap->vht_su_bfmr);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfme = 0x%x \n",
proto_cap->vht_mu_bfme);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfmr = 0x%x \n",
proto_cap->vht_mu_bfmr);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfme = 0x%x \n",
proto_cap->ht_su_bfme);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfmr = 0x%x \n",
proto_cap->ht_su_bfmr);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
/**
* rtw_hal_get_stbc_proto_cap() - Get the intersection proto_cap of the proto_hw_cap and proto_sw_cap
* @phl_com: input, the pointer of phl_com (struct rtw_phl_com_t)
* @hal: input, the pointer of hal (struct hal_info_t)
* @band: input, the band index
* @proto_cap: input_output (struct protocol_cap_t)
* The variable pointer to save the ouput proto_cap results.
* Here, we update STBC cap into STBC fileds of proto_cap.
* Return: return the result of getting proto_cap (enum @rtw_hal_status)
*/
enum rtw_hal_status
rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
u8 band, struct protocol_cap_t *proto_cap)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct protocol_cap_t *hw_cap = NULL;
struct protocol_cap_t *sw_cap = NULL;
if (band >= HW_BAND_MAX) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : invalid band index \n");
return RTW_HAL_STATUS_FAILURE;
}
if (proto_cap == NULL) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : input proto_cap is NULL \n");
return RTW_HAL_STATUS_FAILURE;
}
hw_cap = &hal_com->proto_hw_cap[band];
sw_cap = &phl_com->proto_sw_cap[band];
proto_cap->stbc_tx =
(sw_cap->stbc_tx && hw_cap->stbc_tx) ? 1 : 0; /* Remove later */
proto_cap->stbc_ht_tx =
(sw_cap->stbc_ht_tx && hw_cap->stbc_ht_tx) ? 1 : 0;
proto_cap->stbc_vht_tx =
(sw_cap->stbc_vht_tx && hw_cap->stbc_vht_tx) ? 1 : 0;
proto_cap->stbc_he_tx =
(sw_cap->stbc_he_tx && hw_cap->stbc_he_tx) ? 1 : 0;
proto_cap->stbc_tx_greater_80mhz =
(sw_cap->stbc_tx_greater_80mhz && hw_cap->stbc_tx_greater_80mhz) ? 1 : 0;
proto_cap->stbc_ht_rx =
(sw_cap->stbc_ht_rx <= hw_cap->stbc_ht_rx) ?
sw_cap->stbc_ht_rx : hw_cap->stbc_ht_rx;
proto_cap->stbc_vht_rx =
(sw_cap->stbc_vht_rx <= hw_cap->stbc_vht_rx) ?
sw_cap->stbc_vht_rx : hw_cap->stbc_vht_rx;
proto_cap->stbc_he_rx =
(sw_cap->stbc_he_rx && hw_cap->stbc_he_rx) ? 1 : 0;
proto_cap->stbc_rx_greater_80mhz =
(sw_cap->stbc_rx_greater_80mhz && hw_cap->stbc_rx_greater_80mhz) ? 1 : 0;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_tx = 0x%x \n",
__func__, proto_cap->stbc_tx); /* Remove later */
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_ht_tx = 0x%x \n",
__func__, proto_cap->stbc_ht_tx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_vht_tx = 0x%x \n",
__func__, proto_cap->stbc_vht_tx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_he_tx = 0x%x \n",
__func__, proto_cap->stbc_he_tx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_tx_greater_80mhz = 0x%x \n",
__func__, proto_cap->stbc_tx_greater_80mhz);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_ht_rx = 0x%x \n",
__func__, proto_cap->stbc_ht_rx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_vht_rx = 0x%x \n",
__func__, proto_cap->stbc_vht_rx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_he_rx = 0x%x \n",
__func__, proto_cap->stbc_he_rx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : proto_cap->stbc_rx_greater_80mhz = 0x%x \n",
__func__, proto_cap->stbc_rx_greater_80mhz);
return RTW_HAL_STATUS_SUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_cap.c
|
C
|
agpl-3.0
| 23,167
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_CHAN_C_
#include "hal_headers.h"
#ifdef CONFIG_PHL_DFS
enum rtw_hal_status
rtw_hal_radar_detect_cfg(void *hal, bool dfs_enable)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 rpt_num = 0;/*52A - 29/61/93/125 pkt*/
u8 rpt_to = 1;/*52A CAV - 0 , 80us ,2ms, CBV - 0 / 20ms / 40ms / 80ms*/
PHL_INFO("====>%s dfs_en:%d ============\n", __func__, dfs_enable);
if (dfs_enable) {
rtw_hal_mac_dfs_rpt_cfg(hal_info, true, rpt_num, rpt_to);
rtw_hal_bb_dfs_rpt_cfg(hal_info, true);
}
else {
rtw_hal_mac_dfs_rpt_cfg(hal_info, false, 0, 0);
rtw_hal_bb_dfs_rpt_cfg(hal_info, true);
}
return RTW_HAL_STATUS_SUCCESS;
}
#endif /*CONFIG_PHL_DFS*/
enum rtw_hal_status rtw_hal_set_ch_bw(void *hal, u8 band_idx,
struct rtw_chan_def *chdef, bool do_rfk)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_chan_def *cur_chdef = &(hal_com->band[band_idx].cur_chandef);
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
u8 center_ch = 0;
u8 central_ch_seg1 = 0;
enum band_type change_band;
enum phl_phy_idx phy_idx = HW_PHY_0;
if ((chdef->chan != cur_chdef->chan) ||
(chdef->bw != cur_chdef->bw) ||
(chdef->offset != cur_chdef->offset)) {
if (band_idx == 1)
phy_idx = HW_PHY_1;
status = rtw_hal_reset(hal_com, phy_idx, band_idx, true);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_reset en - failed\n", __func__);
_os_warn_on(1);
}
/* if central channel changed, reset BB & MAC */
center_ch = rtw_phl_get_center_ch(chdef->chan, chdef->bw, chdef->offset);
PHL_INFO("Using central channel %u for primary channel %u BW %u\n",
center_ch, chdef->chan, chdef->bw);
change_band = chdef->band;
status = rtw_hal_mac_set_bw(hal_info, band_idx, chdef->chan,
center_ch, central_ch_seg1, change_band,
chdef->bw);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_mac_set_bw - failed\n", __func__);
return status;
}
if(chdef->bw == CHANNEL_WIDTH_80_80 && central_ch_seg1 == 0) {
PHL_ERR("%s mising info for 80+80M configuration\n", __func__);
return RTW_HAL_STATUS_FAILURE;
}
status = rtw_hal_bb_set_ch_bw(hal_info, phy_idx, chdef->chan,
center_ch, central_ch_seg1, change_band,
chdef->bw);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_bb_set_ch_bw - failed\n", __func__);
return status;
}
status = rtw_hal_rf_set_ch_bw(hal_info, phy_idx, center_ch, change_band, chdef->bw);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_rf_set_ch_bw - failed\n", __func__);
return status;
}
cur_chdef->chan = chdef->chan;
cur_chdef->bw = chdef->bw;
cur_chdef->center_ch = center_ch;
if (cur_chdef->band != change_band) {
cur_chdef->band = change_band;
rtw_hal_notify_switch_band(hal, change_band, phy_idx);
}
status = rtw_hal_rf_set_power(hal_info, phy_idx, PWR_LIMIT);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_rf_set_power - failed\n", __func__);
return status;
}
status = rtw_hal_rf_set_power(hal_info, phy_idx, PWR_LIMIT_RU);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_rf_set_power - failed\n", __func__);
return status;
}
PHL_INFO("%s band_idx:%d, ch:%d, bw:%d, offset:%d\n",
__func__, band_idx, chdef->chan, chdef->bw, chdef->offset);
status = rtw_hal_reset(hal_com, phy_idx, band_idx, false);
if(status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s rtw_hal_reset dis- failed\n", __func__);
_os_warn_on(1);
}
/*PHL_DUMP_CHAN_DEF_EX(chandef);*/
}
if (do_rfk) {
status = rtw_hal_rf_chl_rfk_trigger(hal_info, phy_idx, true);
if (status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("rtw_hal_rf_chl_rfk_trigger fail!\n");
}
PHL_INFO("%s: Switch chdef done, do_rfk:%s\n", __func__,
(do_rfk) ? "Y" : "N");
return status;
}
u8 rtw_hal_get_cur_ch(void *hal, u8 band_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_chan_def *chandef = &(hal_com->band[band_idx].cur_chandef);
return chandef->chan;
}
void rtw_hal_get_cur_chdef(void *hal, u8 band_idx,
struct rtw_chan_def *cur_chandef)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_chan_def *chandef = &(hal_com->band[band_idx].cur_chandef);
void *drv = hal_com->drv_priv;
_os_mem_cpy(drv, cur_chandef, chandef, sizeof(struct rtw_chan_def));
}
void rtw_hal_sync_cur_ch(void *hal, u8 band_idx, struct rtw_chan_def chandef)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_chan_def *cur_chandef = &(hal_com->band[band_idx].cur_chandef);
PHL_INFO("%s: Sync cur chan to ch:%d bw:%d offset:%d\n",
__FUNCTION__, chandef.chan, chandef.bw, chandef.offset);
cur_chandef->chan = chandef.chan;
cur_chandef->bw = chandef.bw;
cur_chandef->offset = chandef.offset;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_chan.c
|
C
|
agpl-3.0
| 5,665
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_CHAN_H_
#define _HAL_CHAN_H_
enum rtw_hal_status rtw_hal_set_ch_bw(void *hal, u8 band_idx,
struct rtw_chan_def *chdef, bool do_rfk);
#ifdef DBG_PHL_CHAN
void phl_chan_dump_chandef(const char *caller, const int line, bool show_caller,
struct rtw_chan_def *chandef);
#define PHL_DUMP_CHAN_DEF(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, false, _chandef);
#define PHL_DUMP_CHAN_DEF_EX(_chandef) phl_chan_dump_chandef(__FUNCTION__, __LINE__, true, _chandef);
#else
#define PHL_DUMP_CHAN_DEF(_chandef)
#define PHL_DUMP_CHAN_DEF_EX(_chandef)
#endif
#endif /* _HAL_CHAN_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_chan.h
|
C
|
agpl-3.0
| 1,255
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_CHAN_INFO_C_
#include "hal_headers.h"
#ifdef CONFIG_PHL_CHANNEL_INFO
enum rtw_hal_status
rtw_hal_cfg_chinfo(void *hal, struct rtw_phl_stainfo_t *sta, u8 enable)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct chinfo_bbcr_cfg bbcr = {0};
u8 mode = 0, filter = 0, sg_size = 0;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 macid = (u8)sta->macid;
/*
*TODO: Discuss how to config accroding to different mode.
* Currently, macid, mode, filter, sg_size use default value,
* which is hard code in rtw_hal_mac_chan_info_cfg.
*/
hal_status = rtw_hal_mac_chan_info_cfg(hal_info, enable, macid, mode, filter, sg_size);
if (hal_status == RTW_HAL_STATUS_SUCCESS) {
if (enable) {
/*
*Below is Example code for BBCR set to Legacy channel 80MHz
*TODO 1: need to calculate channel raw data size to see if
* it is acceptable.
*TODO 2: there should be 10 sets of pre-defined configuration for BBCR.
* need to decide which CR to use.
*/
bbcr.ch_i_phy0_en =1;
bbcr.ch_i_phy1_en = 0;
bbcr.ch_i_grp_num_he = 1;
bbcr.ch_i_grp_num_non_he = 1;
bbcr.ch_i_data_src = 0; /*LS, channel estimation*/
bbcr.ch_i_cmprs = 0; /*8 bits*/
bbcr.ch_i_ele_bitmap = 0x101;
bbcr.ch_i_blk_start_idx = 1;
bbcr.ch_i_blk_end_idx = 10;
bbcr.ch_i_type = 0; /* legacy channel*/
bbcr.ch_i_seg_len = 0; /*12*/
rtw_hal_bb_chan_info_cfg(hal_info, &bbcr);
}
}
return hal_status;
}
void
_hal_fill_csi_header_remain(void* hal, struct csi_header_t *csi_header
, struct rtw_r_meta_data *mdata)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *h = hal_info->hal_com;
/* from mdata */
csi_header->hw_assigned_timestamp = mdata->freerun_cnt;
csi_header->rx_data_rate = mdata->rx_rate;
csi_header->bandwidth = mdata->bw;
csi_header->ch_matrix_report = mdata->get_ch_info;
/* TODO: from drv define, get value from other side.*/
csi_header->channel = 0;
csi_header->num_sub_carrier = 0;
csi_header->num_bit_per_tone = 0;
/* Others: mac addres not from TA ? */
/* hal_mem_cpy(h, &(csi_header->mac_addr[0]), &(mdata->ta[0]), MAC_ALEN); */
}
void
_hal_fill_csi_header_phy_info(void* hal, struct csi_header_t *csi_header
, struct ch_rpt_hdr_info *ch_hdr_rpt, struct phy_info_rpt *phy_info)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *h = hal_info->hal_com;
/* Initialize csi header */
hal_mem_set(h, csi_header, 0, sizeof(struct csi_header_t));
/* from phy_info_rpt */
hal_mem_cpy(h, &(csi_header->rssi[0]), &(phy_info->rssi[0]), 2);
csi_header->rxsc = phy_info->rxsc;
/* from ch_rpt_hdr_info */
csi_header->nc = ch_hdr_rpt->n_rx;
csi_header->nr = ch_hdr_rpt->n_sts;
csi_header->avg_idle_noise_pwr = ch_hdr_rpt->avg_noise_pow;
csi_header->csi_data_length = (ch_hdr_rpt->total_len_l <<16 | ch_hdr_rpt->total_len_m)
- 16; /* header(8byte) + Phy_info_in_seg_0(8byte) */
csi_header->csi_valid = ch_hdr_rpt->set_valid;
hal_mem_cpy(h, &(csi_header->evm[0]), &(ch_hdr_rpt->evm[0]), 2);
}
#endif /* CONFIG_PHL_CHANNEL_INFO */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_chan_info.c
|
C
|
agpl-3.0
| 3,733
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_CHAN_INFO_H_
#define _HAL_CHAN_INFO_H_
#ifdef CONFIG_PHL_CHANNEL_INFO
void
_hal_fill_csi_header_remain(void* hal, struct csi_header_t *csi_header
, struct rtw_r_meta_data *mdata);
void
_hal_fill_csi_header_phy_info(void* hal, struct csi_header_t *csi_header
, struct ch_rpt_hdr_info *ch_hdr_rpt, struct phy_info_rpt *phy_info);
#endif /* CONFIG_PHL_CHANNEL_INFO */
#endif /* _HAL_CHAN_INFO_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_chan_info.h
|
C
|
agpl-3.0
| 1,064
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_COM_I_C_
#define _HAL_COM_I_C_
#include "hal_headers.h"
void
rtw_hal_com_scan_set_tx_lifetime(void *hal, u8 band)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
/* set mgnt queue pkt lifetime */
#define HAL_COM_MGQ_TX_LIFETIME_MS 19
rtw_hal_mac_set_tx_lifetime(hal_info, band, false, true, 0,
(HAL_COM_MGQ_TX_LIFETIME_MS * 1000));
}
void rtw_hal_com_scan_restore_tx_lifetime(void *hal, u8 band)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
/* reset data/mgnt queue pkt lifetime to 0 */
rtw_hal_mac_set_tx_lifetime(hal_info, band, false, false, 0, 0);
}
enum rtw_hal_status rtw_hal_scan_pause_tx_fifo(void *hinfo,
u8 band_idx, bool off_ch)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hinfo;
hal_status = rtw_hal_tx_pause(hal_info->hal_com, band_idx,
off_ch, PAUSE_RSON_NOR_SCAN);
return hal_status;
}
enum rtw_hal_status rtw_hal_dfs_pause_tx(void *hinfo,
u8 band_idx, bool off_ch)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hinfo;
hal_status = rtw_hal_tx_pause(hal_info->hal_com, band_idx,
off_ch, PAUSE_RSON_DFS);
return hal_status;
}
#ifdef CONFIG_FSM
enum rtw_hal_status rtw_hal_scan_flush_queue(void *hinfo,
struct rtw_wifi_role_t *wrole)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hinfo;
int wait = 5/* 10ms */, hal_status;
u8 val8;
#if 0
struct phl_queue *sta_queue;
struct rtw_phl_stainfo_t *sta;
void *drv = hal_to_drvpriv(hal_info);
_os_list *sta_list;
u8 rts_txcnt_lmt_sel = 1;
u8 rts_txcnt_lmt = 1;
u8 data_txcnt_lmt_sel = 1;
u8 data_tx_cnt_lmt = 1;
#endif
hal_status = rtw_hal_mac_is_tx_mgnt_empty(hal_info, wrole->hw_band, &val8);
if (val8)
return RTW_HAL_STATUS_SUCCESS;
#if 0
sta_queue = &wrole->assoc_sta_queue;
sta_list = &sta_queue->queue;
/* TODO wait halmac api */
/* shorten retry limit */
_os_spinlock(drv, &sta_queue->lock, _bh, NULL);
phl_list_for_loop(sta, struct rtw_phl_stainfo_t, sta_list, list) {
rtw_hal_mac_set_rty_lmt(hal_info->hal_com, sta->macid,
rts_txcnt_lmt_sel, rts_txcnt_lmt,
data_txcnt_lmt_sel, data_tx_cnt_lmt);
}
_os_spinunlock(drv, &sta_queue->lock, _bh, NULL);
#endif
while (wait-- && (!val8)) {
_os_delay_ms(hal_info->hal_com->drv_priv, 2);
rtw_hal_mac_is_tx_mgnt_empty(hal_info, wrole->hw_band, &val8);
}
#if 0
/* restore retry limit */
if (wrole->cap.rty_lmt_rts == 0xFF)
rts_txcnt_lmt_sel = 0;
else
rts_txcnt_lmt = wrole->cap.rty_lmt_rts & 0xF;
if (wrole->cap.rty_lmt == 0xFF)
data_txcnt_lmt_sel = 0;
else
data_tx_cnt_lmt = wrole->cap.rty_lmt & 0x3F;
rtw_hal_mac_set_rty_lmt(hal_info->hal_com, sta->macid,
rts_txcnt_lmt_sel, rts_txcnt_lmt,
data_txcnt_lmt_sel, data_tx_cnt_lmt);
#endif
if (val8 == DLE_QUEUE_EMPTY)
return RTW_HAL_STATUS_SUCCESS;
return RTW_HAL_STATUS_FAILURE;
}
#endif
enum rtw_hal_status rtw_hal_notify_switch_band(void *hinfo,
enum band_type band, enum phl_phy_idx phy_idx)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hinfo;
#ifdef CONFIG_BTCOEX
rtw_hal_btc_switch_band_ntfy(hal_info, phy_idx, band);
#endif
rtw_hal_bb_fw_edcca(hal_info);
rtw_hal_rf_set_power(hal_info, phy_idx, PWR_BY_RATE);
rtw_hal_rf_do_tssi_scan(hal_info, phy_idx);
return hal_status;
}
enum rtw_hal_status
rtw_hal_proc_cmd(void *hal, char proc_cmd, struct rtw_proc_cmd *incmd,
char *output, u32 out_len)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if(proc_cmd == RTW_PROC_CMD_BB){
if(rtw_hal_bb_proc_cmd(hal_info, incmd, output, out_len))
hal_status = RTW_HAL_STATUS_SUCCESS;
}
if(proc_cmd == RTW_PROC_CMD_RF){
if(rtw_hal_rf_proc_cmd(hal_info, incmd, output, out_len))
hal_status = RTW_HAL_STATUS_SUCCESS;
}
if(proc_cmd == RTW_PROC_CMD_MAC){
if(rtw_hal_mac_proc_cmd(hal_info, incmd, output, out_len))
hal_status = RTW_HAL_STATUS_SUCCESS;
}
#ifdef CONFIG_BTCOEX
if(proc_cmd == RTW_PROC_CMD_BTC){
if(rtw_hal_btc_proc_cmd(hal_info, incmd, output, out_len))
hal_status = RTW_HAL_STATUS_SUCCESS;
}
#endif
if(proc_cmd == RTW_PROC_CMD_EFUSE){
if(rtw_hal_efuse_proc_cmd(hal_info, incmd, output, out_len))
hal_status = RTW_HAL_STATUS_SUCCESS;
}
return hal_status;
}
void rtw_hal_get_fw_ver(void *hal, char *ver_str, u16 len)
{
rtw_hal_mac_get_fw_ver((struct hal_info_t *)hal, ver_str, len);
}
enum rtw_hal_status
rtw_hal_set_mu_edca(void *hal, u8 band, u8 ac,
u16 timer, u8 cw_min, u8 cw_max, u8 aifsn)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u16 timer_32us;
u8 aifs_us;
u8 slot_time, sifs;
/* TODO: Get aSlotTime and aSIFS according to current PHY */
slot_time = 9;
sifs = 16;
timer_32us = (timer<<8);
aifs_us = (aifsn == 0)?0:(aifsn*slot_time + sifs);
hal_status = rtw_hal_mac_set_mu_edca(hal_info->hal_com,
band, ac, timer_32us, cw_min, cw_max, aifs_us);
return hal_status;
}
enum rtw_hal_status
rtw_hal_set_mu_edca_ctrl(void *hal, u8 band, u8 wmm, u8 set)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_set_mu_edca_ctrl(hal_info->hal_com,
band, wmm, set);
return hal_status;
}
enum rtw_hal_status
rtw_hal_reset(struct rtw_hal_com_t *hal_com, enum phl_phy_idx phy_idx, u8 band_idx, bool reset)
{
struct hal_info_t *hal_info = hal_com->hal_priv;
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
if (reset){
/* disable contention */
status = rtw_hal_tx_pause(hal_com, band_idx, true, PAUSE_RSON_RESET);
if(status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("%s rtw_hal_tx_pause - failed\n", __func__);
return status;
}
/* disable ppdu_sts */
status = rtw_hal_mac_ppdu_stat_cfg(hal_info, band_idx, false, 0, 0);
if(status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("%s rtw_hal_mac_ppdu_stat_cfg - failed\n", __func__);
return status;
}
/*disable DFS/TSSI*/
rtw_hal_bb_dfs_en(hal_info, false);
if (!hal_com->dbcc_en) {
rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_A);
rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_B);
}else{
if(phy_idx == HW_PHY_0)
rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_A);
else
rtw_hal_bb_tssi_cont_en(hal_info, false, RF_PATH_B);
}
/*disable ADC*/
rtw_hal_bb_adc_en(hal_info, false);
/* wait 40us*/
_os_delay_us(hal_com->drv_priv, 40);
/* reset BB*/
rtw_hal_bb_reset_en(hal_info, false, phy_idx);
}else{
/*enable ppdu_sts*/
status = rtw_hal_mac_ppdu_stat_cfg(
hal_info, band_idx, true,
hal_com->band[band_idx].ppdu_sts_appen_info,
hal_com->band[band_idx].ppdu_sts_filter);
if(status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("%s rtw_hal_mac_ppdu_stat_cfg - failed\n", __func__);
return status;
}
/*enable ADC*/
rtw_hal_bb_adc_en(hal_info, true);
/*enable DFS/TSSI*/
rtw_hal_bb_dfs_en(hal_info, true);
if (!hal_com->dbcc_en) {
rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_A);
rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_B);
}else{
if(phy_idx == HW_PHY_0)
rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_A);
else
rtw_hal_bb_tssi_cont_en(hal_info, true, RF_PATH_B);
}
/*BB reset set to 1*/
rtw_hal_bb_reset_en(hal_info, true, phy_idx);
status = rtw_hal_tx_pause(hal_com, band_idx, false, PAUSE_RSON_RESET);
if(status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("%s rtw_hal_tx_pause - failed\n", __func__);
return status;
}
}
return status;
}
enum rtw_hal_status rtw_hal_ppdu_sts_cfg(void *hal, u8 band_idx, bool en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
if (en) {
hal_status = rtw_hal_mac_ppdu_stat_cfg(
hal_info, band_idx, true,
hal_com->band[band_idx].ppdu_sts_appen_info,
hal_com->band[band_idx].ppdu_sts_filter);
} else {
hal_status = rtw_hal_mac_ppdu_stat_cfg(hal_info, band_idx, false, 0, 0);
}
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("%s (en %d) - failed\n", __func__, en);
return hal_status;
}
void
rtw_hal_disconnect_notify(void *hal, struct rtw_chan_def *chandef)
{
rtw_hal_rf_disconnect_notify(hal, chandef);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_disconnect_notify(): chandef band(%d), chan(%d), bw(%d), offset(%d)\n",
chandef->band, chandef->chan, chandef->bw, chandef->offset);
}
bool rtw_hal_check_ch_rfk(void *hal, struct rtw_chan_def *chandef)
{
bool check = false;
check = rtw_hal_rf_check_mcc_ch(hal, chandef);
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_check_ch_rfk(): check ok(%d), band(%d), chan(%d), bw(%d), offset(%d)\n",
check, chandef->band, chandef->chan, chandef->bw, chandef->offset);
return check;
}
void rtw_hal_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt,
struct rtw_wifi_role_t *wrole)
{
enum phl_phy_idx p_idx = HW_PHY_0;
p_idx = rtw_hal_bb_band_to_phy_idx(hal_com, wrole->hw_band);
rtw_hal_bb_env_rpt(hal_com, env_rpt, p_idx);
}
#endif /* _HAL_COM_I_C_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_com_i.c
|
C
|
agpl-3.0
| 9,862
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_CONFIG_H_
#define _HAL_CONFIG_H_
#ifdef CONFIG_PHL_TEST_MP
#define CONFIG_HAL_TEST_MP
#endif
#define MAX_PATH_LEN 256
#define MAX_LINES_HWCONFIG_TXT 2000
#define MAX_BYTES_LINE_HWCONFIG_TXT 256
#define MAX_HWCONFIG_FILE_CONTENT MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT
/* Disable HALBB Features */
#ifndef CONFIG_PHL_DFS
#define DRV_BB_DFS_DISABLE
#endif
#ifdef CONFIG_BB_TIMER_SUPPORT_DISABLE
#define DRV_BB_TIMER_SUPPORT_DISABLE
#endif
/* Compile flag for fw for different cut versions.
* This should be wrapped with the compile flags from core, and need to be discussed
*/
#ifdef CONFIG_RTL8852A
#define MAC_FW_8852A_U1 1
#define MAC_FW_8852A_U2 1
#define MAC_FW_8852A_U3 1
#endif
#ifdef CONFIG_RTL8852B
#define MAC_FW_8852B_U1 1
#define MAC_FW_8852B_U2 1
#endif
#ifdef CONFIG_WPP
#define DRV_BB_DBG_TRACE_DISABLE
#endif
/* HALRF Features */
#ifdef RTW_WKARD_PHL_LPS_IQK_TWICE
#define RTW_WKARD_HAL_LPS_IQK_TWICE
#endif
#endif /*_HAL_CONFIG_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_config.h
|
C
|
agpl-3.0
| 1,640
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "hal_headers.h"
/**
* _dump_csi_buf_status
* Dump all of the csi buffer status;
* @csi_obj: (struct hal_csi_obj *)
**/
void _dump_csi_buf_status(struct hal_csi_obj *csi_obj)
{
struct hal_csi_buf *csi_buf = NULL;
u8 i = 0;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> DUMP HAL CSI Buffer Status\n");
for (i = 0; i < csi_obj->max_csi_buf_nr; i++) {
csi_buf = &csi_obj->csi_buf[i];
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF][%d] status 0x%x \n",
csi_buf->idx, csi_buf->sub_idx);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20UU (%d) \n",
IS_SUB20_BUSY(csi_buf, 3));
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20UL (%d) \n",
IS_SUB20_BUSY(csi_buf, 2));
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20LU (%d) \n",
IS_SUB20_BUSY(csi_buf, 1));
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "[CSI BUF] 20LL (%d) \n",
IS_SUB20_BUSY(csi_buf, 0));
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== DUMP HAL CSI Buffer Status\n");
}
/**
* __query_avl_buf_idx_20
* Get available sub 20MHz csi buffer
* input :
* @csi_buf: (struct hal_csi_buf *) 80MHz hal csi buffer for checking avaible
* return
* @sub_idx: (u8) csi buffer sub index
**/
u8 __query_avl_buf_idx_20(struct hal_csi_buf *csi_buf)
{
u8 sub_idx = CSI_BUF_SUB_IDX_NON;
do {
if (IS_SUB20_BUSY(csi_buf, 0) == CSI_BUF_STS_IDLE) {
SET_SUB20_BUSY(csi_buf, 0);
sub_idx = CSI_BUF_SUB_IDX_20_LL;
break;
}
if (IS_SUB20_BUSY(csi_buf, 1) == CSI_BUF_STS_IDLE) {
SET_SUB20_BUSY(csi_buf, 1);
sub_idx = CSI_BUF_SUB_IDX_20_LU;
break;
}
if (IS_SUB20_BUSY(csi_buf, 2) == CSI_BUF_STS_IDLE) {
SET_SUB20_BUSY(csi_buf, 2);
sub_idx = CSI_BUF_SUB_IDX_20_UL;
break;
}
if (IS_SUB20_BUSY(csi_buf, 3) == CSI_BUF_STS_IDLE) {
SET_SUB20_BUSY(csi_buf, 3);
sub_idx = CSI_BUF_SUB_IDX_20_UU;
break;
}
} while (0);
return sub_idx;
}
/**
* __query_avl_buf_idx_40
* Get available sub 40MHz csi buffer
* input :
* @csi_buf: (struct hal_csi_buf *) 80MHz hal csi buffer for checking avaible
* return
* @sub_idx: (u8) csi buffer sub index
**/
u8 __query_avl_buf_idx_40(struct hal_csi_buf *csi_buf)
{
u8 sub_idx = CSI_BUF_SUB_IDX_NON;
do {
if(IS_40L_BUSY(csi_buf) == CSI_BUF_STS_IDLE) {
SET_40L_BUSY(csi_buf);
sub_idx = CSI_BUF_SUB_IDX_40_L;
break;
}
if (IS_40U_BUSY(csi_buf) == CSI_BUF_STS_IDLE) {
SET_40U_BUSY(csi_buf);
sub_idx = CSI_BUF_SUB_IDX_40_U;
break;
}
} while (0);
return sub_idx;
}
/**
* __query_avl_buf_idx_80
* Get available sub 80MHz csi buffer
* input :
* @csi_buf: (struct hal_csi_buf *) 80MHz hal csi buffer for checking avaible
* return
* @sub_idx: (u8) csi buffer sub index
**/
u8 __query_avl_buf_idx_80(struct hal_csi_buf *csi_buf)
{
u8 sub_idx = CSI_BUF_SUB_IDX_NON;
if (csi_buf->sub_idx == CSI_BUF_STS_IDLE) {
sub_idx = CSI_BUF_SUB_IDX_80;
csi_buf->sub_idx = 0xF;
}
return sub_idx;
}
/**
* _query_csi_buf_su
* Get available sub 40MHz csi buffer
* input :
* @hal_info: (struct hal_info_t *)
* @size:enum hal_csi_buf_size 20/40/80 MHz
* return
* @sub_id: (u8) available csi buffer sub index
* @csi_buf: (struct hal_csi_buf *) original hal csi buffer
**/
struct hal_csi_buf *_query_csi_buf_su(
struct hal_info_t *hal_info,
enum hal_csi_buf_size size,
u8 *sub_id)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj;
struct hal_csi_buf *csi_buf = NULL;
u8 i = 0;
u8 e_idx_su = csi_obj->max_csi_buf_nr_su;
*sub_id = CSI_BUF_SUB_IDX_NON;
switch (size) {
case HAL_CSI_BUF_SIZE_20:
for (i = 0; i < e_idx_su; i++) {
*sub_id = __query_avl_buf_idx_20(&csi_obj->csi_buf[i]);
if(*sub_id != CSI_BUF_SUB_IDX_NON) {
csi_buf = &csi_obj->csi_buf[i];
break;
}
}
break;
case HAL_CSI_BUF_SIZE_40:
for (i = 0; i < e_idx_su; i++) {
*sub_id = __query_avl_buf_idx_40(&csi_obj->csi_buf[i]);
if(*sub_id != CSI_BUF_SUB_IDX_NON) {
csi_buf = &csi_obj->csi_buf[i];
break;
}
}
break;
case HAL_CSI_BUF_SIZE_80:
for (i = 0; i < e_idx_su; i++) {
*sub_id = __query_avl_buf_idx_80(&csi_obj->csi_buf[i]);
if(*sub_id != CSI_BUF_SUB_IDX_NON) {
csi_buf = &csi_obj->csi_buf[i];
break;
}
}
break;
default:
break;
}
if (*sub_id == CSI_BUF_SUB_IDX_NON) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :_query_csi_buf_su fail !!!\n");
}
return csi_buf;
}
/**
* _query_csi_buf_mu
* Get available sub 40MHz csi buffer
* input :
* @hal_info: (struct hal_info_t *)
* @size:enum hal_csi_buf_size 20/40/80 MHz
* return
* @sub_id: (u8) available csi buffer sub index
* @csi_buf: (struct hal_csi_buf *) original hal csi buffer
**/
struct hal_csi_buf *_query_csi_buf_mu(
struct hal_info_t *hal_info,
enum hal_csi_buf_size size,
u8 *sub_id)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj;
struct hal_csi_buf *csi_buf = NULL;
u8 i = 0;
u8 s_idx_mu = csi_obj->max_csi_buf_nr_su;
u8 e_idx_mu = csi_obj->max_csi_buf_nr;
*sub_id = CSI_BUF_SUB_IDX_NON;
switch (size) {
case HAL_CSI_BUF_SIZE_20:
for (i = s_idx_mu; i < e_idx_mu; i++) {
*sub_id = __query_avl_buf_idx_20(&csi_obj->csi_buf[i]);
if(*sub_id != CSI_BUF_SUB_IDX_NON) {
csi_buf = &csi_obj->csi_buf[i];
break;
}
}
break;
case HAL_CSI_BUF_SIZE_40:
for (i = s_idx_mu; i < e_idx_mu; i++) {
*sub_id = __query_avl_buf_idx_40(&csi_obj->csi_buf[i]);
if(*sub_id != CSI_BUF_SUB_IDX_NON) {
csi_buf = &csi_obj->csi_buf[i];
break;
}
}
break;
case HAL_CSI_BUF_SIZE_80:
for (i = s_idx_mu; i < e_idx_mu; i++) {
*sub_id = __query_avl_buf_idx_80(&csi_obj->csi_buf[i]);
if(*sub_id != CSI_BUF_SUB_IDX_NON) {
csi_buf = &csi_obj->csi_buf[i];
break;
}
}
break;
default:
break;
}
if (*sub_id == CSI_BUF_SUB_IDX_NON) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "warring :_query_csi_buf_mu fail !!!\n");
}
return csi_buf;
}
/**
* _bw2csi
* phl channel width to hal csi buffer size
* input :
* @bw: (struct hal_info_t *)
* return
* @ret: enum hal_csi_buf_size
**/
enum hal_csi_buf_size
_bw2csi(enum channel_width bw)
{
enum hal_csi_buf_size ret = HAL_CSI_BUF_SIZE_NONE;
switch (bw){
case CHANNEL_WIDTH_20:
ret = HAL_CSI_BUF_SIZE_20;
break;
case CHANNEL_WIDTH_40:
ret = HAL_CSI_BUF_SIZE_40;
break;
case CHANNEL_WIDTH_80:
ret = HAL_CSI_BUF_SIZE_80;
break;
default:
break;
}
return ret;
}
enum rtw_hal_status _hal_csi_init_buf(struct hal_info_t *hal_info, u8 num)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
void *drv_priv = hal_to_drvpriv(hal_info);
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = hal_com->csi_obj;
struct hal_csi_buf *csi_buf = NULL;
u8 idx = 0;
do {
csi_obj->csi_buf = _os_mem_alloc(drv_priv,
sizeof(*csi_buf) * num);
_os_mem_set(drv_priv, csi_obj->csi_buf, 0,
sizeof(*csi_buf) * num);
if (NULL == csi_obj->csi_buf) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
csi_buf = csi_obj->csi_buf;
for (idx = 0; idx < num ; idx++) {
csi_buf[idx].idx = idx;
csi_buf[idx].sub_idx = 0;
}
} while (0);
return status;
}
/**
* hal_csi_init
* hal csi module initialize
* input :
* @hal_info: struct hal_info_t
* @su_buf_nr: Number of HW SU CSI Buffer for HAL
* @mu_buf_nr: Number of HW MU CSI Buffer for HAL
**/
enum rtw_hal_status
hal_csi_init(struct hal_info_t *hal_info, u8 su_buf_nr, u8 mu_buf_nr)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = NULL;
void *drv_priv = hal_to_drvpriv(hal_info);
u8 idx = 0;
FUNCIN();
do {
csi_obj = _os_mem_alloc(drv_priv, sizeof(*csi_obj));
if (csi_obj == NULL) {
status = RTW_HAL_STATUS_RESOURCE;
break;
}
hal_com->csi_obj = csi_obj;
_os_spinlock_init(drv_priv, &csi_obj->csi_lock);
if ((su_buf_nr + mu_buf_nr) == 0) {
PHL_ERR("hal_csi_init fail : csi buffer number = 0\n");
status = RTW_HAL_STATUS_RESOURCE;
break;
}
_hal_csi_init_buf(hal_info, mu_buf_nr + su_buf_nr);
csi_obj->max_csi_buf_nr_mu = mu_buf_nr;
csi_obj->max_csi_buf_nr_su = su_buf_nr;
csi_obj->max_csi_buf_nr = su_buf_nr + mu_buf_nr;
for (idx = su_buf_nr; idx < csi_obj->max_csi_buf_nr; idx++){
csi_obj->csi_buf[idx].type = HAL_CSI_BUF_TYPE_MU;
}
} while (0);
if (RTW_HAL_STATUS_SUCCESS != status) {
hal_csi_deinit(hal_info);
}
FUNCOUT();
return status;
}
/**
* hal_csi_deinit
* hal csi module deinitialize
* input :
* @hal_info: struct hal_info_t
**/
void hal_csi_deinit(struct hal_info_t *hal_info)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj;
void *drv_priv = hal_to_drvpriv(hal_info);
struct hal_csi_buf *csi_buf = csi_obj->csi_buf;
if (csi_obj != NULL) {
if (csi_buf != NULL) {
_os_mem_free(hal_to_drvpriv(hal_info), csi_buf,
sizeof(struct hal_csi_buf) * csi_obj->max_csi_buf_nr);
csi_obj->csi_buf = NULL;
}
_os_spinlock_free(drv_priv, &csi_obj->csi_lock);
/* bf obj need free as last */
_os_mem_free(hal_to_drvpriv(hal_info), csi_obj,
sizeof(struct hal_csi_obj));
hal_com->csi_obj = NULL;
}
}
/**
* hal_csi_query_idle_csi_buf
* Get available CSI buffer
* input :
* @hal_info: struct hal_info_t
* @mu: Request CSI Type : 1 = MU / 0 = SU
* @bw: Request CSI BW : enum channel_width (20/40/80MHz)
* @buf: (struct hal_csi_buf *)input/return : memory for CSI buffer index+subindex
* (the call shall provied 1byte memory to save csi index)
**/
enum rtw_hal_status hal_csi_query_idle_csi_buf(
struct hal_info_t *hal_info,
u8 mu,
enum channel_width bw,
void *buf)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj;
void *drv_priv = hal_to_drvpriv(hal_info);
struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf;
struct hal_csi_buf *tmp_csi_buf = NULL;
u8 sub_idx = CSI_BUF_SUB_IDX_NON;
enum hal_csi_buf_size size = HAL_CSI_BUF_SIZE_NONE;
enum hal_csi_buf_type type = HAL_CSI_BUF_TYPE_SU;
FUNCIN();
if (csi_buf == NULL) {
return status;
}
size = _bw2csi(bw);
type = mu ? HAL_CSI_BUF_TYPE_MU : HAL_CSI_BUF_TYPE_SU;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "size = 0x%x , type = 0x%x \n",
size, type);
switch (type) {
case HAL_CSI_BUF_TYPE_SU:
{
_os_spinlock(drv_priv, &csi_obj->csi_lock, _ps, NULL);
tmp_csi_buf = _query_csi_buf_su(hal_info, size, &sub_idx);
_os_spinunlock(drv_priv, &csi_obj->csi_lock, _ps, NULL);
}
break;
case HAL_CSI_BUF_TYPE_MU:
{
_os_spinlock(drv_priv, &csi_obj->csi_lock, _ps, NULL);
tmp_csi_buf = _query_csi_buf_mu(hal_info, size, &sub_idx);
_os_spinunlock(drv_priv, &csi_obj->csi_lock, _ps, NULL);
}
break;
default:
break;
}
if (tmp_csi_buf == NULL || sub_idx == CSI_BUF_SUB_IDX_NON) {
status = RTW_HAL_STATUS_RESOURCE;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "hal_csi_query_idle_csi_buf Fail\n");
} else {
csi_buf->idx = tmp_csi_buf->idx;
csi_buf->sub_idx = sub_idx;
csi_buf->type = type;
status = RTW_HAL_STATUS_SUCCESS;
}
FUNCOUT();
return status;
}
/**
* hal_csi_release_csi_buf
* Release the CSI buffer
* input :
* @hal_info: struct hal_info_t
* @buf: (struct hal_csi_buf *)input/return : CSI buffer index to release
**/
enum rtw_hal_status hal_csi_release_csi_buf(
struct hal_info_t *hal_info,
void *buf)
{
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj;
void *drv_priv = hal_to_drvpriv(hal_info);
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_csi_buf *tmp_csi_buf = NULL;
struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf;
if (csi_buf == NULL) {
return status;
}
if (csi_buf->idx < csi_obj->max_csi_buf_nr) {
tmp_csi_buf = &csi_obj->csi_buf[csi_buf->idx];
_os_spinlock(drv_priv, &csi_obj->csi_lock, _ps, NULL);
switch (csi_buf->sub_idx) {
case CSI_BUF_SUB_IDX_80:
tmp_csi_buf->sub_idx = 0;
break;
case CSI_BUF_SUB_IDX_40_U:
CLEAR_CSI_STS_BIT(tmp_csi_buf, 3);
CLEAR_CSI_STS_BIT(tmp_csi_buf, 2);
break;
case CSI_BUF_SUB_IDX_40_L:
CLEAR_CSI_STS_BIT(tmp_csi_buf, 1);
CLEAR_CSI_STS_BIT(tmp_csi_buf, 0);
break;
case CSI_BUF_SUB_IDX_20_UU:
CLEAR_CSI_STS_BIT(tmp_csi_buf, 3);
break;
case CSI_BUF_SUB_IDX_20_UL:
CLEAR_CSI_STS_BIT(tmp_csi_buf, 2);
break;
case CSI_BUF_SUB_IDX_20_LU:
CLEAR_CSI_STS_BIT(tmp_csi_buf, 1);
break;
case CSI_BUF_SUB_IDX_20_LL:
CLEAR_CSI_STS_BIT(tmp_csi_buf, 0);
break;
default:
break;
}
csi_buf->idx = 0;
csi_buf->sub_idx = CSI_BUF_SUB_IDX_NON;
_os_spinunlock(drv_priv, &csi_obj->csi_lock, _ps, NULL);
status = RTW_HAL_STATUS_SUCCESS;
}
return status;
}
/**
* hal_is_csi_buf_valid : check the csi buffer index is valid or not.
* @hal_info: struct hal_info_t
* @buf: (struct hal_csi_buf *)input/return : CSI buffer index to release
**/
u8 hal_is_csi_buf_valid(struct hal_info_t *hal_info, void *buf)
{
struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_csi_obj *csi_obj = (struct hal_csi_obj *)hal_com->csi_obj;
u8 ret = _SUCCESS;
do {
if(csi_buf->idx >= csi_obj->max_csi_buf_nr){
ret = _FAIL;
break;
}
if(csi_buf->sub_idx == CSI_BUF_SUB_IDX_NON) {
ret = _FAIL;
break;
}
} while(0);
return ret;
}
/**
* rtw_hal_get_csi_buf_bw : Get the csi buf bandwidth;
* @buf: (struct hal_csi_buf *)
* return
* @ret: enum channel_width
**/
enum channel_width
rtw_hal_get_csi_buf_bw(void *buf)
{
struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf;
enum channel_width bw = CHANNEL_WIDTH_20;
switch (csi_buf->sub_idx) {
case CSI_BUF_SUB_IDX_80:
bw = CHANNEL_WIDTH_80;
break;
case CSI_BUF_SUB_IDX_40_U:
case CSI_BUF_SUB_IDX_40_L:
bw = CHANNEL_WIDTH_40;
break;
case CSI_BUF_SUB_IDX_20_UU:
case CSI_BUF_SUB_IDX_20_UL:
case CSI_BUF_SUB_IDX_20_LU:
case CSI_BUF_SUB_IDX_20_LL:
bw = CHANNEL_WIDTH_20;
break;
case CSI_BUF_SUB_IDX_NON:
default:
bw = CHANNEL_WIDTH_MAX;
break;
}
return bw;
}
/**
* rtw_hal_get_csi_buf_type : check the csi buffer index is valid or not.
* @buf: (struct hal_csi_buf *)
* return:
* @ret: true = TYPE MU ; false = TYPE SU
**/
bool
rtw_hal_get_csi_buf_type(void *buf)
{
struct hal_csi_buf *csi_buf = (struct hal_csi_buf *)buf;
bool ret = false;
if (csi_buf != NULL) {
ret = (csi_buf->type == HAL_CSI_BUF_TYPE_MU) ? true : false;
}
return ret;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_csi_buffer.c
|
C
|
agpl-3.0
| 15,207
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_CSI_BUFFER_H__
#define __HAL_CSI_BUFFER_H__
#define CSI_BUF_IDX_HW_MSK 0x7FF
#define CSI_BUF_SUB_IDX_80 0b0
#define CSI_BUF_SUB_IDX_40_U 0b100100
#define CSI_BUF_SUB_IDX_40_L 0b101000
#define CSI_BUF_SUB_IDX_20_UU 0b000100
#define CSI_BUF_SUB_IDX_20_UL 0b001000
#define CSI_BUF_SUB_IDX_20_LU 0b001100
#define CSI_BUF_SUB_IDX_20_LL 0b010000
#define CSI_BUF_SUB_IDX_NON 0b111111
#define CSI_BUF_STS_BUSY 1
#define CSI_BUF_STS_IDLE 0
#define IS_SUB20_BUSY(_csi, _idx) \
(((_csi->sub_idx&BIT(_idx)) == BIT(_idx)) ? CSI_BUF_STS_BUSY : CSI_BUF_STS_IDLE)
#define SET_SUB20_BUSY(_csi, _idx) _csi->sub_idx |= BIT(_idx)
#define IS_40L_BUSY(_csi) \
(((_csi->sub_idx & (BIT(0)|BIT(1)))==(BIT(0)|BIT(1))) ? CSI_BUF_STS_BUSY : CSI_BUF_STS_IDLE)
#define IS_40U_BUSY(_csi) \
(((_csi->sub_idx & (BIT(2)|BIT(3)))==(BIT(2)|BIT(3))) ? CSI_BUF_STS_BUSY : CSI_BUF_STS_IDLE)
#define SET_40L_BUSY(_csi) _csi->sub_idx |= (BIT(0)|BIT(1))
#define SET_40U_BUSY(_csi) _csi->sub_idx |= (BIT(2)|BIT(3))
#define CLEAR_CSI_STS_BIT(_csi, _x) _csi->sub_idx &= ~(1 << _x)
enum hal_csi_buf_type {
HAL_CSI_BUF_TYPE_SU = 0,
HAL_CSI_BUF_TYPE_MU = 1
};
enum hal_csi_buf_size {
HAL_CSI_BUF_SIZE_NONE = 0,
HAL_CSI_BUF_SIZE_20,
HAL_CSI_BUF_SIZE_40,
HAL_CSI_BUF_SIZE_80,
HAL_CSI_BUF_SIZE_160
};
struct hal_csi_buf {
u16 sub_idx:6;
u16 idx:5;
u16 type:1;
u16 rsvd:4;
};
struct hal_csi_obj {
u8 max_csi_buf_nr;
u8 max_csi_buf_nr_su;
u8 max_csi_buf_nr_mu;
struct hal_csi_buf *csi_buf;
_os_lock csi_lock;
};
enum rtw_hal_status
hal_csi_init(struct hal_info_t *hal_info, u8 su_buf_nr, u8 mu_buf_nr);
void hal_csi_deinit(struct hal_info_t *hal_info);
enum rtw_hal_status hal_csi_query_idle_csi_buf(
struct hal_info_t *hal_info, u8 mu, enum channel_width bw, void *buf);
enum rtw_hal_status hal_csi_release_csi_buf(
struct hal_info_t *hal_info,
void *buf);
u8 hal_is_csi_buf_valid(struct hal_info_t *hal_info, void *buf);
enum channel_width
rtw_hal_get_csi_buf_bw(void *buf);
bool
rtw_hal_get_csi_buf_type(void *buf);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_csi_buffer.h
|
C
|
agpl-3.0
| 2,679
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_CUSTOM_C_
#include "hal_headers.h"
#ifdef CONFIG_PHL_CUSTOM_FEATURE
enum rtw_hal_status
rtw_hal_custom_cfg_tx_ampdu(void *hal,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_custom_ampdu_cfg *ampdu)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
if (wrole == NULL || ampdu == NULL)
return hsts;
hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info,
wrole->hw_band,
(u16)ampdu->max_agg_num,
(u8)ampdu->max_agg_time_32us);
return hsts;
}
enum rtw_hal_status
rtw_hal_get_ampdu_cfg(void *hal,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_custom_ampdu_cfg *cfg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_ampdu_cfg ampdu_cfg = {0};
if (wrole == NULL || cfg == NULL)
return hsts;
hsts = rtw_hal_mac_get_ampdu_cfg(hal_info->hal_com,
wrole->hw_band,
&du_cfg);
if (hsts == RTW_HAL_STATUS_SUCCESS) {
cfg->max_agg_num = ampdu_cfg.max_agg_num;
cfg->max_agg_time_32us = ampdu_cfg.max_agg_time_32us;
}
return hsts;
}
enum rtw_hal_status
rtw_hal_set_pop_en(void *hal, bool en, enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_bb_set_pop_en(hal_info, en, phy_idx);
}
bool
rtw_hal_query_pop_en(void *hal, enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_bb_query_pop_en(hal_info, phy_idx);
}
enum rtw_hal_status
rtw_hal_set_pkt_detect_thold(void *hal, u32 bound)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_bb_set_pkt_detect_thold(hal_info, bound);
}
u8
rtw_hal_query_pkt_detect_thold(void *hal,
bool get_en_info,
enum phl_phy_idx phy_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_bb_query_pkt_detect_thold(hal_info, get_en_info, phy_idx);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_custom.c
|
C
|
agpl-3.0
| 2,870
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_CUSTOM_H_
#define _HAL_CUSTOM_H_
#ifdef CONFIG_PHL_CUSTOM_FEATURE
enum rtw_hal_status
rtw_hal_custom_cfg_tx_ampdu(void *hal,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_custom_ampdu_cfg *ampdu);
enum rtw_hal_status
rtw_hal_get_ampdu_cfg(void *hal,
struct rtw_wifi_role_t *wrole,
struct rtw_phl_custom_ampdu_cfg *cfg);
enum rtw_hal_status
rtw_hal_set_pop_en(void *hal, bool en, enum phl_phy_idx phy_idx);
bool
rtw_hal_query_pop_en(void *hal, enum phl_phy_idx phy_idx);
enum rtw_hal_status
rtw_hal_set_pkt_detect_thold(void *hal, u32 bound);
u8
rtw_hal_query_pkt_detect_thold(void *hal,
bool get_en_info,
enum phl_phy_idx phy_idx);
#endif
#endif /*_HAL_CUSTOM_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_custom.h
|
C
|
agpl-3.0
| 1,495
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_DBCC_C_
#include "hal_headers.h"
#ifdef CONFIG_DBCC_SUPPORT
enum rtw_hal_status
rtw_hal_dbcc_pre_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
hal_com->dbcc_en = (dbcc_en) ? true : false;
/*mac_dbcc_pre_cfg*/
hsts = rtw_hal_mac_dbcc_pre_cfg(phl_com, hal_info, dbcc_en);
if (hsts != RTW_HAL_STATUS_SUCCESS) {
PHL_ASSERT("%s mac_dbcc_pre_cfg failed\n", __func__);
hal_com->dbcc_en = false;
goto exit_func;
}
/*phy_dbcc_pre_cfg*/
hsts = rtw_hal_phy_dbcc_pre_cfg(hal_info, phl_com, dbcc_en);
if (hsts != RTW_HAL_STATUS_SUCCESS) {
PHL_ASSERT("%s phy_dbcc_pre_cfg failed\n", __func__);
hal_com->dbcc_en = false;
goto exit_func;
}
PHL_INFO("%s-%s done and success\n", __func__, (dbcc_en) ? "EN" : "DIS");
exit_func:
return hsts;
}
enum rtw_hal_status
rtw_hal_dbcc_cfg(void *hal, struct rtw_phl_com_t *phl_com, bool dbcc_en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
/*if(phl_com->drv_mode == RTW_DRV_MODE_MP)*/
if(hal_info->hal_com->chip_id ==CHIP_WIFI6_8852B)
{
PHL_ASSERT("%s 8852B doesn't support dbcc\n", __func__);
hal_com->dbcc_en = false;
goto exit_func;
}
#if 1
/* band 0 tx pause */
rtw_hal_tx_pause(hal_com, HW_BAND_0, true, PAUSE_RSON_DBCC);
#else
/* mac-id pause - rtw_hal_mac_set_macid_pause */
rtw_hal_mac_set_macid_pause(hal_info->hal_com, 0, true);
rtw_hal_mac_set_macid_pause(hal_info->hal_com, 1, true);
#endif
/* FW tx pause , BT tx pause*/
/* bb cca pause */
rtw_hal_bb_ctrl_rx_cca(hal_info->hal_com, false, HW_PHY_0);
/*mac_dbcc_cfg*/
hsts = rtw_hal_mac_dbcc_cfg(phl_com, hal_info, dbcc_en);
if (hsts != RTW_HAL_STATUS_SUCCESS) {
PHL_ASSERT("%s mac_dbcc_cfg failed\n", __func__);
hal_com->dbcc_en = false;
goto exit_func;
}
/*bb_dbcc_cfg*/
hsts = rtw_hal_phy_dbcc_cfg(hal_info, phl_com, dbcc_en);
if (hsts != RTW_HAL_STATUS_SUCCESS) {
PHL_ASSERT("%s phy_dbcc_cfg failed\n", __func__);
hal_com->dbcc_en = false;
goto exit_func;
}
#if 1
/* band 0 tx unpause */
rtw_hal_tx_pause(hal_com, HW_BAND_0, false, PAUSE_RSON_DBCC);
#else
/* mac-id unpause - rtw_hal_mac_set_macid_pause */
rtw_hal_mac_set_macid_pause(hal_info->hal_com, 0, false);
rtw_hal_mac_set_macid_pause(hal_info->hal_com, 1, false);
#endif
/* FW tx unpause , BT tx unpause*/
/* bb cca unpause */
rtw_hal_bb_ctrl_rx_cca(hal_info->hal_com, true, HW_PHY_0);
PHL_INFO("%s-%s done and success\n", __func__, (dbcc_en) ? "EN" : "DIS");
/*mac role recovery*/
/*if (has_ap)*/
/*mac_port_cfg(BCN_EN-MAC_AX_PCFG_TX_SW)*/
/*mac_port_cfg(BCN_DIS-MAC_AX_PCFG_MBSSID_EN)*/
exit_func:
return hsts;
}
enum rtw_hal_status
rtw_hal_clean_tx_queue(void *hal)
{
#if 0
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
u32 start_time;
start_time = _os_get_cur_time_ms();
// set retry limit =1 -rtw_hal_mac_set_rty_lmt
/* rtw_hal_mac_set_rty_lmt(hal_com, sta->macid,
rts_txcnt_lmt_sel, rts_txcnt_lmt,
data_txcnt_lmt_sel, data_tx_cnt_lmt);*/
//polling mac_is_txq_empty - rtw_hal_mac_is_txq_empty
//chk_allq_empty - rtw_hal_mac_is_allq_empty
//polling TX idle
//FW tx pause/unpause
// if (has ap)
//polling HIQ & WLCPU queue,
//disable beacon TX mode
//mac_port_cfg(BCN_DIS-MAC_AX_PCFG_TX_SW)
//mac_port_cfg(BCN_DIS-MAC_AX_PCFG_MBSSID_EN)
PHL_INFO("[DBCC] %s: pass %u ms\n", __FUNCTION__,
_get_passing_time_ms(start_time));
#endif
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_dbcc_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band)
{
#if 1 /* no rtw_hal_mac_get_tx_cnt api */
return RTW_HAL_STATUS_SUCCESS;
#else
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_get_tx_cnt(hal_info, band, MAC_AX_TX_ALLTYPE, NULL);
#endif
}
enum rtw_hal_status
rtw_hal_dbcc_reset_tx_cnt(void *hal, struct rtw_phl_com_t *phl_com, u8 band)
{
#if 1 /* no rtw_hal_mac_set_reset_tx_cnt */
return RTW_HAL_STATUS_SUCCESS;
#else
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_set_reset_tx_cnt(hal_info, band);
#endif
}
#endif /*CONFIG_DBCC_SUPPORT*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_dbcc.c
|
C
|
agpl-3.0
| 5,005
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_DBCC_H_
#define _HAL_DBCC_H_
#endif /* _HAL_DBCC_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_dbcc.h
|
C
|
agpl-3.0
| 719
|
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_DEF_H_
#define _HAL_DEF_H_
#define halcom_to_drvpriv(_hcom) (_hcom->drv_priv)
#define MAX_WD_LEN (48)
#define MAX_WD_BODY_LEN (24)
#define MAX_BAENTRY 2
enum HAL_CMD_ID {
HAL_HELP,
MAC_DD_DBG,
MAC_DUMP_SEC_CAM_TBL
};
struct hal_cmd_info {
char name[16];
u8 id;
};
static const struct hal_cmd_info hal_cmd_i[] = {
{"-h", HAL_HELP},
{"dd_dbg", MAC_DD_DBG},/*@do not move this element to other position*/
{"sec_cam_tbl", MAC_DUMP_SEC_CAM_TBL}
};
enum rtw_hal_status {
RTW_HAL_STATUS_SUCCESS, /* 0 */
RTW_HAL_STATUS_FAILURE, /* 1 */
RTW_HAL_STATUS_RESOURCE, /* 2 */
RTW_HAL_STATUS_IO_INIT_FAILURE, /* 3 */
RTW_HAL_STATUS_MAC_INIT_FAILURE, /* 4 */
RTW_HAL_STATUS_BB_INIT_FAILURE, /* 5 */
RTW_HAL_STATUS_RF_INIT_FAILURE, /* 6 */
RTW_HAL_STATUS_BTC_INIT_FAILURE, /* 7 */
RTW_HAL_STATUS_HAL_INIT_FAILURE, /* 8 */
RTW_HAL_STATUS_EFUSE_UNINIT, /* 9 */
RTW_HAL_STATUS_EFUSE_IVALID_OFFSET, /* 10 */
RTW_HAL_STATUS_EFUSE_PG_FAIL, /* 11 */
RTW_HAL_STATUS_MAC_API_FAILURE, /* 12 */
RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG, /*13*/
RTW_HAL_STATUS_UNKNOWN_RFE_TYPE, /* 14 */
RTW_HAL_STATUS_TIMEOUT, /* 15 */
};
#define FW_FILE_NIC_POSTFIX ""
#define FW_FILE_WOWLAN_POSTFIX "_wowlan"
#define FW_FILE_SPIC_POSTFIX "_spic"
#define FW_FILE_AP_POSTFIX "_ap"
enum rtw_fw_type {
RTW_FW_NIC, /* 1 */
RTW_FW_WOWLAN, /* 2 */
RTW_FW_AP, /* 3 */
RTW_FW_ROM, /* 4 */
RTW_FW_SPIC, /* 5 */
RTW_FW_NIC_MP, /* 6 */
RTW_FW_AP_MP, /* 7 */
RTW_FW_VRAP, /* 8 */
RTW_FW_MAX
};
enum _rtw_hal_query_info {
RTW_HAL_RXDESC_SIZE,
};
enum rtw_h2c_pkt_type {
H2CB_TYPE_CMD = 0,
H2CB_TYPE_DATA = 1,
H2CB_TYPE_LONG_DATA = 2,
H2CB_TYPE_MAX = 0x3
};
enum tx_pause_rson {
PAUSE_RSON_NOR_SCAN, /*normal scan*/
PAUSE_RSON_UNSPEC_BY_MACID, /*P2P_SCAN*/
PAUSE_RSON_RFK,
PAUSE_RSON_PSD,
PAUSE_RSON_DFS,
PAUSE_RSON_DBCC,
PAUSE_RSON_RESET,
PAUSE_RSON_MAX
};
enum rtw_hal_config_int {
RTW_HAL_EN_DEFAULT_INT,
RTW_HAL_DIS_DEFAULT_INT,
RTW_HAL_STOP_RX_INT,
RTW_HAL_RESUME_RX_INT,
RTW_HAL_SER_HANDSHAKE_MODE,
RTW_HAL_EN_HCI_INT,
RTW_HAL_DIS_HCI_INT,
RTW_HAL_CONFIG_INT_MAX
};
enum hal_mp_efuse_type {
HAL_MP_EFUSE_WIFI = 0,
HAL_MP_EFUSE_BT,
HAL_MP_EFUSE_NONE,
};
struct rtw_g6_h2c_hdr {
u8 h2c_class; //0x0~0x7: Phydm; 0x8~0xF: RF; 0x10~0x17: BTC
u8 h2c_func;
u8 seq_valid:1;
u8 seq:3;
u8 seq_stop:1;
enum rtw_h2c_pkt_type type; //0:cmd ; 1:cmd+data ; 2:cmd+long data
u16 content_len:12;
u16 rec_ack:1; //Ack when receive H2C
u16 done_ack:1; //Ack when FW execute H2C cmd done
u16 rsvd2:2;
};
/**
* @c2h_cat: target category of this c2h / c2h ack
* @c2h_class: target class of this c2h / c2h ack
* @c2h_func: target function of this c2h / c2h ack
* @type_rec_ack: set 1 as a receive ack to this c2h
* @type_done_ack: set 1 as a done ack to this c2h
* @h2c_return: status code of done ack responding to h2c
*
*/
struct rtw_c2h_info {
u8 c2h_cat;
u8 c2h_class;
u8 c2h_func;
u8 type_rec_ack:1;
u8 type_done_ack:1;
u8 rsvd:6;
u8 h2c_return;/*H2C return value, 0 = success*/
u8 h2c_seq;
u16 content_len;
u8 *content;
};
#define RTW_BTC_OVERWRITE_BUF_LEN 10
struct hal_bt_msg {
_os_lock lock;
u16 len;
u16 cnt; /* update cnt */
u8 latest[RTW_BTC_OVERWRITE_BUF_LEN];
u8 working[RTW_BTC_OVERWRITE_BUF_LEN];
};
struct btc_fw_msg {
_os_lock lock;
u32 fev_cnt; /* fw event cnt, need to be protected by lock */
struct hal_bt_msg btinfo;
struct hal_bt_msg scbd;
/* common fwinfo queue */
struct phl_queue idleq;
struct phl_queue waitq;
};
struct btc_ctrl_t {
u8 lps;
u8 tx_time;
u8 tx_retry;
};
/*except version*/
struct ver_ctrl_t {
u64 mac_ver;
u64 bb_ver;
u64 rf_ver;
u64 btc_ver;
u64 fw_ver;
};
struct hal_mu_score_tbl_ctrl {
u32 mu_sc_thr:2;
u32 mu_opt:1;
u32 rsvd:29;
};
#define HAL_MAX_MU_SCORE_SIZE 8 /* Unit: Byte */
struct hal_mu_score_tbl_score {
u8 valid;
u16 macid;
u8 score[HAL_MAX_MU_SCORE_SIZE]; /*by case: [1:0], [3:2], ..... */
};
#define HAL_MAX_MU_STA_NUM 6
struct hal_mu_score_tbl {
struct hal_mu_score_tbl_ctrl mu_ctrl;
_os_lock lock;
u8 num_mu_sta; /*By IC, shall alway <= than HAL_MAX_MU_STA_NUM , 0 = tbl invalid */
u8 sz_mu_score; /*By IC, shall alway <= than HAL_MAX_MU_SCORE_SIZE , 0 = score invalid */
struct hal_mu_score_tbl_score mu_score[HAL_MAX_MU_STA_NUM]; /* mu_score[num_mu_sta] */
};
#define HAL_MAX_VHT_BFRP_NUM 3
#define HAL_MAX_HE_BFRP_NUM 2
#define HLA_MAX_BFRP_NUM ((HAL_MAX_VHT_BFRP_NUM > HAL_MAX_HE_BFRP_NUM) ?\
HAL_MAX_VHT_BFRP_NUM : HAL_MAX_HE_BFRP_NUM)
#define HAL_MAX_VHT_SND_STA_NUM HAL_MAX_VHT_BFRP_NUM + 1
#define HAL_MAX_HE_BFRP_STA_NUM 4
#define HAL_MAX_HE_SND_STA_NUM HAL_MAX_HE_BFRP_NUM * HAL_MAX_HE_BFRP_STA_NUM
struct hal_frame_hdr {
u16 frame_ctl;
u16 duration;
u8 addr1[MAC_ALEN];
u8 addr2[MAC_ALEN];
};
struct hal_npda_dialog_token {
u8 rsvd:1;
u8 he:1;
u8 token:6;
};
#define HAL_NPDA_AC_SU 0
#define HAL_NPDA_AC_MU 1
#define HAL_NDPA_AX_FB_SU_NG_4 0
#define HAL_NDPA_AX_FB_SU_NG_16 2
#define HAL_NDPA_AX_FB_MU_NG_4 1
#define HAL_NDPA_AX_FB_MU_NG_16 3
#define HAL_NDPA_AX_FB_CQI 3
#define HAL_NPDA_AX_CB_SU42_MU75 0
#define HAL_NPDA_AX_CB_SU64_MU97 1
struct hal_he_snd_f2p {
u16 csi_len_bfrp:12;
u16 tb_t_pe_bfrp:2;
u16 tri_pad_bfrp:2;
u16 ul_cqi_rpt_tri_bfrp:1;
u16 rf_gain_idx_bfrp:10;
u16 fix_gain_en_bfrp:1;
u16 rsvd:4;
};
struct hal_vht_ndpa_sta_info {
u32 aid12:12;
u32 feedback_type:1;
u32 nc:3;
u32 rsvd:16;
};
struct hal_he_ndpa_sta_info {
u32 aid:11;
u32 bw:14;
u32 fb_ng:2;
u32 disambiguation:1;
u32 cb:1;
u32 nc:3;
};
struct hal_ndpa_para {
struct hal_frame_hdr common;
struct hal_npda_dialog_token snd_dialog;
u32 ndpa_sta_info[HAL_MAX_HE_SND_STA_NUM];
};
struct hal_he_trg_frm_cmn {
u32 tgr_info: 4;
u32 ul_len: 12;
u32 more_tf: 1;
u32 cs_rqd: 1;
u32 ul_bw: 2;
u32 gi_ltf: 2;
u32 mimo_ltfmode: 1;
u32 num_heltf: 3;
u32 ul_pktext: 3;
u32 ul_stbc: 1;
u32 ldpc_extra_sym: 1;
u32 dplr: 1;
u32 ap_tx_pwr: 6;
u32 ul_sr: 16;
u32 ul_siga2_rsvd: 9;
u32 rsvd: 1;
};
struct hal_he_trg_fm_user {
u16 aid12;
u8 ru_pos;
u8 ul_fec_code;
u8 ul_mcs;
u8 ul_dcm;
u8 ss_alloc;
u8 ul_tgt_rssi;
};
struct hal_bfrp_he {
struct hal_he_trg_frm_cmn common;
struct hal_he_trg_fm_user user[HAL_MAX_HE_BFRP_STA_NUM];
u8 fbseg_rexmit_bmp[HAL_MAX_HE_BFRP_STA_NUM];/*BFRP only*/
struct hal_he_snd_f2p f2p_info;
};
struct hal_bfrp_vht {
u8 rexmit_bmp;
};
struct hal_bfrp_para {
struct hal_frame_hdr hdr[HLA_MAX_BFRP_NUM];
struct hal_bfrp_he he_para[HAL_MAX_HE_BFRP_NUM];
struct hal_bfrp_vht vht_para[HAL_MAX_VHT_BFRP_NUM];
};
struct hal_snd_wd_para {
u16 txpktsize;
u16 ndpa_duration;
u16 datarate:9;
u16 macid:7;
u8 force_txop:1;
u8 data_bw:2;
u8 gi_ltf:3;
u8 data_er:1;
u8 data_dcm:1;
u8 data_stbc:1;
u8 data_ldpc:1;
u8 data_bw_er:1;
u8 multiport_id:1;
u8 mbssid:4;
u8 signaling_ta_pkt_sc:4;
u8 sw_define:4;
u8 txpwr_ofset_type:3;
u8 lifetime_sel:3;
u8 stf_mode:1;
u8 disdatafb:1;
u8 data_txcnt_lmt_sel:1;
u8 data_txcnt_lmt:6;
u8 sifs_tx:1;
u8 snd_pkt_sel:3;
u8 ndpa:2;
u8 rsvd:3;
};
#define HAL_FEXG_TYPE_AC_SU 31
#define HAL_FEXG_TYPE_AC_MU_1 32
#define HAL_FEXG_TYPE_AC_MU_2 33
#define HAL_FEXG_TYPE_AC_MU_3 34
#define HAL_FEXG_TYPE_AX_SU 35
#define HAL_FEXG_TYPE_AX_MU_1 36
#define HAL_FEXG_TYPE_AX_MU_2 37
struct hal_ax_fwcmd_snd {
u8 frame_ex_type;
u8 bfrp0_sta_nr;
u8 bfrp1_sta_nr;
u16 macid[8];
struct hal_ndpa_para ndpa;
struct hal_bfrp_para bfrp;
/**
* HE: NDPA NDP HE_Trigger_BFRP (CSI) BFRP (CSI)
* VHT: NDPA NDP (CSI) VHT_BFRP (CSI) BFRP (CSI) BFRP (CSI)
**/
struct hal_snd_wd_para wd[HLA_MAX_BFRP_NUM + 2];
};
struct rtw_hal_com_t;
struct hal_io_ops {
u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr);
u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr);
u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr);
void (*_read_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem);
int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
int (*_write_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 length, u8 *pdata);
#ifdef RTW_WKARD_BUS_WRITE
int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
#endif
#ifdef CONFIG_SDIO_HCI
u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr);
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr);
u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr);
u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr);
int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif
};
struct hal_io_priv {
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
_os_mutex sd_indirect_access_mutex;
#endif
struct hal_io_ops io_ops;
};
#define halcom_to_drvpriv(_hcom) (_hcom->drv_priv)
#define hal_get_chip_id(_halcom) (_halcom->chip_id)
enum pcfg_type {
PCFG_FUNC_SW,
PCFG_TBTT_AGG,
PCFG_TBTT_SHIFT,
PCFG_HIQ_WIN,
PCFG_HIQ_DTIM,
PCFG_HIQ_MAX,
PCFG_BCN_INTERVAL, /* Beacon Interval */
PCFG_BSS_CLR,
PCFG_BCN_EN
};
/*
* refers to _usb.h
* #define USB11 0x1
* #define USB2 0x2
* #define USB3 0x3
* */
enum usb_type {
USB_1_1 = 1,
USB_2_0,
USB_3_0,
};
#ifdef RTW_PHL_BCN
struct bcn_entry_pool {
u8 bcn_num;
_os_list bcn_list;
_os_lock bcn_lock;
};
#endif
enum rtw_hal_set_def_var_rsn {
SET_DEF_RSN_HAL_INIT,
SET_DEF_RSN_WOW_RESUME_HNDL_RX,
SET_DEF_RSN_WOW_RESUME_DONE
};
struct hal_intr_mask_cfg {
u8 halt_c2h_en;
u8 wdt_en;
};
struct hal_halt_c2h_int {
/* halt c2h */
u32 intr;
u32 val_mask;
u32 val_default;
};
struct hal_watchdog_timer_int {
/* watchdog timer */
u32 intr;
u32 val_mask;
u32 val_default;
};
struct hal_int_array {
struct hal_halt_c2h_int halt_c2h_int;
struct hal_watchdog_timer_int watchdog_timer_int;
};
/* c2h event id for hal/phl layer */
enum rtw_hal_c2h_ev {
HAL_C2H_EV_DO_NOTHING = 0,
HAL_C2H_EV_BB_MUGRP_DOWN = 1,/* BB Process C2H mu-score-tbl done */
HAL_C2H_EV_BTC_INFO = 2, /* BTC event */
HAL_C2H_EV_BTC_SCBD = 3, /* BTC event */
HAL_C2H_EV_MAC_TSF32_TOG = 4, /* MAC event */
HAL_C2H_EV_MAX
};
/* ppdu status : per user info */
struct hal_ppdu_sts_usr {
/* MAC */
u8 vld:1;
u8 has_data:1;
u8 has_ctrl:1;
u8 has_mgnt:1;
u8 has_bcn:1;
u16 macid;
};
enum hal_rxcnt_sel {
HAL_RXCNT_OFDM_OK = 0,
HAL_RXCNT_OFDM_FAIL = 1,
HAL_RXCNT_OFDM_FAM = 2,
HAL_RXCNT_CCK_OK = 3,
HAL_RXCNT_CCK_FAIL = 4,
HAL_RXCNT_CCK_FAM = 5,
HAL_RXCNT_HT_OK = 6,
HAL_RXCNT_HT_FAIL = 7,
HAL_RXCNT_HT_PPDU = 8,
HAL_RXCNT_HT_FAM = 9,
HAL_RXCNT_VHTSU_OK = 0xA,
HAL_RXCNT_VHTSU_FAIL = 0xB,
HAL_RXCNT_VHTSU_PPDU = 0xC,
HAL_RXCNT_VHTSU_FAM = 0xD,
HAL_RXCNT_VHTMU_OK = 0xE,
HAL_RXCNT_VHTMU_FAIL = 0xF,
HAL_RXCNT_VHTMU_PPDU = 0x10,
HAL_RXCNT_VHTMU_FAM = 0x11,
HAL_RXCNT_HESU_OK = 0x12,
HAL_RXCNT_HESU_FAIL = 0x13,
HAL_RXCNT_HESU_PPDU = 0x14,
HAL_RXCNT_HESU_FAM = 0x15,
HAL_RXCNT_HEMU_OK = 0x16,
HAL_RXCNT_HEMU_FAIL = 0x17,
HAL_RXCNT_HEMU_PPDU = 0x18,
HAL_RXCNT_HEMU_FAM = 0x19,
HAL_RXCNT_HETB_OK = 0x1A,
HAL_RXCNT_HETB_FAIL = 0x1B,
HAL_RXCNT_HETB_PPDU = 0x1C,
HAL_RXCNT_HETB_FAM = 0x1D,
HAL_RXCNT_INVD = 0x1E,
HAL_RXCNT_RECCA = 0x1F,
HAL_RXCNT_FULLDRP = 0x20,
HAL_RXCNT_FULLDRP_PKT = 0x21,
HAL_RXCNT_RXDMA = 0x22,
HAL_RXCNT_USER0 = 0x23,
HAL_RXCNT_USER1 = 0x24,
HAL_RXCNT_USER2 = 0x25,
HAL_RXCNT_USER3 = 0x26,
HAL_RXCNT_CONT_FCS = 0x27,
HAL_RXCNT_PKTFLTR_DRP = 0x28,
HAL_RXCNT_CSIPKT_DMA_OK = 0x29,
HAL_RXCNT_CSIPKT_DMA_DROP = 0x2A,
HAL_RXCNT_MAX
};
enum hal_rate_mode {
HAL_LEGACY_MODE = 0,
HAL_HT_MODE = 1,
HAL_VHT_MODE = 2,
HAL_HE_MODE = 3
};
enum hal_rate_bw {
HAL_RATE_BW_20 = 0,
HAL_RATE_BW_40 = 1,
HAL_RATE_BW_80 = 2,
HAL_RATE_BW_160 = 3,
};
struct hal_ppdu_rx_cnt {
u16 ppdu_cnt[HAL_RXCNT_MAX];
};
/* ppdu sts mac bmp_append_info */
#define HAL_PPDU_MAC_INFO BIT(1)
#define HAL_PPDU_PLCP BIT(3)
#define HAL_PPDU_RX_CNT BIT(2)
/* ppdu sts mac bmp_filter */
#define HAL_PPDU_HAS_A1M BIT(4)
#define HAL_PPDU_HAS_CRC_OK BIT(5)
/* ppdu status (mac info + phy info) */
struct hal_ppdu_sts {
#define RTW_HAL_PPDU_STS_MAX_USR 4
/* MAC */
/* NOTE: (rx_cnt, plcp, phy_st)_ptr are only available before phl_recycle_rx_buf() */
u8 *rx_cnt_ptr;
u8 *plcp_ptr;
u8 *phy_st_ptr; /* for bb phy status */
u8 plcp_size;
u32 phy_st_size;/* for bb phy status */
u32 rx_cnt_size;
u8 usr_num;
struct hal_ppdu_sts_usr usr[RTW_HAL_PPDU_STS_MAX_USR];
struct hal_ppdu_rx_cnt rx_cnt;
};
#define HAL_RSSI_MAVG_NUM 16
#define STA_UPDATE_MA_RSSI_FAST(_RSSI, _VAL) _RSSI = ((_RSSI * \
(HAL_RSSI_MAVG_NUM - 1)) + _VAL) \
/ HAL_RSSI_MAVG_NUM
struct rtw_cfo_info {
s32 cfo_tail;
s32 pre_cfo_avg;
s32 cfo_avg;
u16 cfo_cnt;
u32 tp;
};
struct rtw_rssi_info {
u8 rssi; /* u(8,1), hal-bb provide, read only : 0~110 (dBm = rssi -110) */
u16 rssi_ma; /* u(16,5), hal-bb provide, read only : u16 U(12,4)*/
u16 rssi_ma_path[4];
u16 pkt_cnt_data;
u8 rssi_bcn; /* u(8,1), beacon RSSI, hal-bb provide, read only : 0~110 (dBm = rssi -110) */
u16 rssi_bcn_ma; /* u(16,5), beacon RSSI, hal-bb provide, read only*/
u16 pkt_cnt_bcn;
u8 ma_factor:4;
u8 ma_factor_bcn:4;
u8 rssi_ofdm; /* u(8,1), hal-bb provide, read only : packet, for debug */
u8 rssi_cck; /* u(8,1), hal-bb provide, read only : packet, for debug */
u8 assoc_rssi; /* phl_rx provide, read only */
/* phl_rx provide, read only : Moving Average RSSI information for the STA */
u8 ma_rssi; /* moving average : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */
u8 ma_rssi_mgnt; /* moving average rssi for beacon/probe : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */
u16 snr_ma; /* u(16,4), hal-bb provide, read only, SNR= snr_ma dBm*/
};
struct rtw_rate_info {
enum rtw_gi_ltf gi_ltf; /* 3bit GILTF */
enum hal_rate_mode mode; /* 2bit 0:legacy, 1:HT, 2:VHT, 3:HE*/
enum hal_rate_bw bw; /*2bit 0:5M/10M/20M, 1:40M, 2:80M, 3:160M or 80+80*/
u8 mcs_ss_idx; /*HE: 3bit SS + 4bit MCS; non-HE: 5bit MCS/rate idx */
};
/* from cmn_sta_info */
struct rtw_ra_sta_info {
/*u8 rate_id; remove !!! use wmode in phl, [PHYDM] ratr_idx*/
/*u8 rssi_level; [PHYDM]*/
/*u8 is_first_connect:1; change connect flow, [PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
/*u8 is_support_sgi:1; mov to phl [driver]*/
/*u8 is_vht_enable:2; mov to phl [driver]*/
/*u8 disable_ra:1; mov to hal [driver]*/
/*u8 disable_pt:1; remove for no PT, [driver] remove is_disable_power_training*/
/*u8 txrx_state:2; ///////////////need to check if needed, [PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/
/*u8 is_noisy:1; ///////////////need to check if needed, [PHYDM]*/
u16 curr_tx_rate; /*use struct bb_rate_info, [PHYDM] FW->Driver*/
enum channel_width ra_bw_mode; /*remove to phl, [Driver] max bandwidth, for RA only*/
enum channel_width curr_tx_bw; /*bb_rate_info, [PHYDM] FW->Driver*/
/* u8 drv_ractrl; */
/* Ctrl */
bool dis_ra; /*move from rtw_hal_stainfo_t*/
bool ra_registered;/*move from rtw_hal_stainfo_t*/
u64 ra_mask;/*move from rtw_hal_stainfo_t*/ /*drv decide by specific req*/
u64 cur_ra_mask;/*move from rtw_hal_stainfo_t*/
/*halbb create, mod by driver and decide by rssi or other*/
u8 cal_giltf; /* 3bit gi_ltf ctrl by driver*/
bool fix_giltf_en; /*giltf from cal_giltf or halbb*/
bool fixed_rt_en;
struct rtw_rate_info fixed_rt_i;
u8 rainfo_cfg1; /* prepare for other control*/
u8 rainfo_cfg2; /* prepare for other control*/
/* Report */
struct rtw_rate_info rpt_rt_i;
u8 curr_retry_ratio; /*[HALBB] FW->Driver*/
bool ra_csi_rate_en;
bool fixed_csi_rate_en;
u8 band_num;
struct rtw_rate_info csi_rate;
u8 avg_agg;
u32 tx_ok_cnt[4];
u32 tx_retry_cnt[4];
u32 tx_total_cnt;
/*u64 ramask;*/
};
struct rtw_mura_info {
/* Ctrl */
bool fixed_rt_en;
struct rtw_rate_info fixed_rt_i;
/* Report */
struct rtw_rate_info rpt_rt_i;
u8 curr_retry_ratio; /*[PHYDM] FW->Driver*/
};
/* from cmn_sta_info */
struct rtw_dtp_info {
u8 dyn_tx_power; /*Dynamic Tx power offset*/
u8 last_tx_power;
u8 sta_tx_high_power_lvl:4;
u8 sta_last_dtp_lvl:4;
};
struct rtw_hal_muba_info {
u32 fix_ba:1;
u32 ru_psd:9;
u32 tf_rate:9;
u32 rf_gain_fix:1;
u32 rf_gain_idx:10;
u32 tb_ppdu_bw:2;
u8 dcm:1;
u8 ss:3;
u8 mcs:4;
u8 gi_ltf:3;
u8 doppler:1;
u8 stbc:1;
u8 sta_coding:1;
u8 tb_t_pe_nom:2;
u8 pr20_bw_en:1;
u8 ma_type: 1;
u8 rsvd1: 6;
};
enum rtw_hal_protection_type {
HAL_PROT_NO_PROETCT = 0,
HAL_PROT_PRIUSER_HW_RTS = 1,
HAL_PROT_RTS = 2,
HAL_PROT_CTS2SELF = 3,
HAL_PROT_MU_RTS = 4,
HAL_PROT_HW_DEFAULT_ = 5
};
enum rtw_hal_ack_resp_type {
HAL_ACK_N_MINUS_1USER_BA = 0,
HAL_ACK_N_USER_BA = 1,
HAL_ACK_MU_BAR = 2,
HAL_ACK_HTP_ACK = 3,
HAL_ACK_HW_DEFAULT = 4
};
struct rtw_wp_rpt_stats {
u32 busy_cnt;
u32 tx_ok_cnt;
u32 rty_fail_cnt;
u32 lifetime_drop_cnt;
u32 macid_drop_cnt;
u32 sw_drop_cnt;
u32 recycle_fail_cnt;
u32 delay_tx_ok_cnt;
u32 delay_rty_fail_cnt;
u32 delay_lifetime_drop_cnt;
u32 delay_macid_drop_cnt;
};
struct rtw_trx_stat {
u32 rx_ok_cnt;
u32 rx_err_cnt;
u16 rx_rate_plurality;
/* add lock for tx statistics */
_os_lock tx_sts_lock;
/* Below info is for release report*/
u32 tx_fail_cnt;
u32 tx_ok_cnt;
#ifdef CONFIG_USB_HCI
struct rtw_wp_rpt_stats wp_rpt_stats[PHL_AC_QUEUE_TOTAL];
#endif
#ifdef CONFIG_PCI_HCI
u8 *wp_rpt_stats;
u32 ltr_tx_dly_count;
u32 ltr_last_tx_dly_time;
#endif
};
struct bacam_ctrl_t {
u8 used_map[MAX_BAENTRY];
u8 tid[MAX_BAENTRY];
u8 count;
};
struct rtw_hal_stainfo_t {
/* from cmn_sta_info */
u16 dm_ctrl;
/* struct su_ra_info */
struct rtw_rssi_info rssi_stat;
struct rtw_cfo_info cfo_stat;
/* Beamform Related */
u8 bf_cap;/* sta's beamform capability : ht/vht/he + bfee/bfer */
void *bf_entry;
u16 bf_csi_buf;
u16 bf_csi_buf_swap;/*used in mu swap mode*/
/* BFee capability */
u8 max_nc;
u8 nr;
u8 ng16;/* 0:non-support ; BIT0:support SU ; BIT1:support MU */
u8 cb_sz;/* 0:non-support ; BIT0:support (4,2) SU ; BIT1:support (7,5) MU */
u8 support_cqi_fb;
/*mu group*/
u8 mugrp_bmp;
u32 mu_score;
/*FW Frame Exchange : when STA is primary STA, prefer protect type and ack resp type in MU*/
enum rtw_hal_protection_type prot_type;
enum rtw_hal_ack_resp_type resp_type;
struct bacam_ctrl_t ba_ctl;
/* from cmn_sta_info */
struct rtw_ra_sta_info ra_info;
/* from cmn_sta_info */
struct rtw_dtp_info dtp_stat;
struct rtw_trx_stat trx_stat;
void *hw_cfg_tab;
void *bb_sta;
};
struct bus_hw_cap_t {
#ifdef CONFIG_PCI_HCI
enum rtw_pcie_bus_func_cap_t l0s_ctrl;
enum rtw_pcie_bus_func_cap_t l1_ctrl;
enum rtw_pcie_bus_func_cap_t l1ss_ctrl;
enum rtw_pcie_bus_func_cap_t wake_ctrl;
enum rtw_pcie_bus_func_cap_t crq_ctrl;
u8 clkdly_ctrl;
u8 l0sdly_ctrl;
u8 l1dly_ctrl;
u8 ltr_sw_ctrl; /* whether ltr can be controlled by sw */
u8 ltr_hw_ctrl;
u32 max_txbd_num;
u32 max_rxbd_num;
u32 max_rpbd_num;
u8 max_phyaddr_num;
u8 max_wd_page_size;
u8 txbd_len;
u8 rxbd_len;
u8 wdb_size;
u8 wdi_size;
u8 addr_info_size;
u8 seq_info_size;
#elif defined (CONFIG_USB_HCI)
u32 tx_buf_size;
u32 tx_buf_num;
u32 tx_mgnt_buf_size;
u32 tx_mgnt_buf_num;
u32 tx_h2c_buf_num;
u32 rx_buf_size;
u32 rx_buf_num;
u32 in_token_num;
#elif defined (CONFIG_SDIO_HCI)
u32 tx_buf_size;
u32 tx_buf_num;
u32 tx_mgnt_buf_size;
u32 tx_mgnt_buf_num;
u32 rx_buf_size;
u32 rx_buf_num;
#else
u8 temp_for_struct_empty; /* for undefined interface */
#endif
};
/* phy capability of phy */
struct phy_hw_cap_t {
#ifdef RTW_WKARD_BTC_RFETYPE
u8 rfe_type;
#endif
u8 tx_num;
u8 rx_num;
u16 hw_rts_time_th;
u16 hw_rts_len_th;
};
/*PHYx + Sx*/
enum phl_phy_idx {
HW_PHY_0,
HW_PHY_1,
HW_PHY_MAX
};
enum phl_pwr_table {
PWR_BY_RATE = BIT0,
PWR_LIMIT = BIT1,
PWR_LIMIT_RU = BIT2
};
enum phl_rf_mode {
RF_MODE_NORMAL = 0,
RF_MODE_SHUTDOWN = 1,
RF_MODE_STANDBY = 2,
RF_MODE_RX = 3,
RF_MODE_TX = 4,
RF_MODE_MAX
};
/*--------------------------------------------------------------------------*/
/*[TX Power Unit(TPU) array size]*/
#define TPU_SIZE_PWR_TAB 16 /*MCS0~MCS11(12) + {dcm_0,1,3,4}4 = 16*/
#define TPU_SIZE_PWR_TAB_lGCY 12 /*cck(4) + ofdm(8) = 12*/
#define TPU_SIZE_MODE 5 /*0~4: HE, VHT, HT, Legacy, CCK, */
#define TPU_SIZE_BW 5 /*0~4: 80_80, 160, 80, 40, 20*/
#define TPU_SIZE_RUA 3 /*{26, 52, 106}*/
#define TPU_SIZE_BW20_SC 8 /*8 * 20M = 160M*/
#define TPU_SIZE_BW40_SC 4 /*4 * 40M = 160M*/
#define TPU_SIZE_BW80_SC 2 /*2 * 80M = 160M*/
#define TPU_SIZE_BF 2 /*{NON_BF, BF}*/
#if defined(CONFIG_RTL8851A)
#define HAL_COMPILE_IC_1SS
#endif
#if (defined(CONFIG_RTL8852A) || defined(CONFIG_RTL8852B) || defined(CONFIG_RTL8852C))
#define HAL_COMPILE_IC_2SS
#endif
#if defined(CONFIG_RTL8853A)
#define HAL_COMPILE_IC_3SS
#endif
#if defined(CONFIG_RTL8834A)
#define HAL_COMPILE_IC_4SS
#endif
/*@==========================================================================*/
#if (defined(HAL_COMPILE_IC_4SS))
#define HAL_COMPILE_ABOVE_4SS
#endif
#if (defined(HAL_COMPILE_IC_3SS) || defined(HAL_COMPILE_ABOVE_4SS))
#define HAL_COMPILE_ABOVE_3SS
#endif
#if (defined(HAL_COMPILE_IC_2SS) || defined(HAL_COMPILE_ABOVE_3SS))
#define HAL_COMPILE_ABOVE_2SS
#endif
#if (defined(HAL_COMPILE_IC_1SS) || defined(HAL_COMPILE_ABOVE_2SS))
#define HAL_COMPILE_ABOVE_1SS
#endif
#if (defined(HAL_COMPILE_ABOVE_4SS))
#define HAL_MAX_PATH 4
#elif (defined(HAL_COMPILE_ABOVE_3SS))
#define HAL_MAX_PATH 3
#elif (defined(HAL_COMPILE_ABOVE_2SS))
#define HAL_MAX_PATH 2
#else
#define HAL_MAX_PATH 1
#endif
/*--------------------------[Structure]-------------------------------------*/
enum rtw_tpu_op_mode {
TPU_NORMAL_MODE = 0,
TPU_DBG_MODE = 1
};
struct rtw_tpu_pwr_by_rate_info { /*TX Power Unit (TPU)*/
s8 pwr_by_rate_lgcy[TPU_SIZE_PWR_TAB_lGCY];
s8 pwr_by_rate[HAL_MAX_PATH][TPU_SIZE_PWR_TAB];
};
struct rtw_tpu_ext_pwr_lmt_info { /*TX Power Unit (TPU)*/
s8 ext_pwr_lmt_2_4g[HAL_MAX_PATH];
s8 ext_pwr_lmt_5g_band1[HAL_MAX_PATH]; /*CH36 ~ CH48*/
s8 ext_pwr_lmt_5g_band2[HAL_MAX_PATH]; /*CH52 ~ CH64*/
s8 ext_pwr_lmt_5g_band3[HAL_MAX_PATH]; /*CH100 ~ CH144*/
s8 ext_pwr_lmt_5g_band4[HAL_MAX_PATH]; /*CH149 ~ CH165*/
};
struct rtw_tpu_pwr_imt_info { /*TX Power Unit (TPU)*/
s8 pwr_lmt_cck_20m[HAL_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_cck_40m[HAL_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_lgcy_20m[HAL_MAX_PATH][TPU_SIZE_BF]; /*ofdm*/
s8 pwr_lmt_20m[HAL_MAX_PATH][TPU_SIZE_BW20_SC][TPU_SIZE_BF];
s8 pwr_lmt_40m[HAL_MAX_PATH][TPU_SIZE_BW40_SC][TPU_SIZE_BF];
s8 pwr_lmt_80m[HAL_MAX_PATH][TPU_SIZE_BW80_SC][TPU_SIZE_BF];
s8 pwr_lmt_160m[HAL_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_40m_0p5[HAL_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_40m_2p5[HAL_MAX_PATH][TPU_SIZE_BF];
};
struct rtw_tpu_info { /*TX Power Unit (TPU)*/
enum rtw_tpu_op_mode op_mode; /*In debug mode, only debug tool control TPU APIs*/
bool normal_mode_lock_en;
s8 ofst_int; /*SW: S(8,3) -16 ~ +15.875 (dB)*/
u8 ofst_fraction; /*[0:3] * 0.125(dBm)*/
u8 base_cw_0db; /*[63~39~15]: [+24~0~-24 dBm]*/
u16 tssi_16dBm_cw;
/*[Ref Pwr]*/
s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
s16 ref_pow_cck; /*-> HW: s(9,2)*/
u16 ref_pow_ofdm_cw; /*BBCR 0x58E0[9:0]*/
u16 ref_pow_cck_cw; /*BBCR 0x58E0[21:12]*/
/*[Pwr Ofsset]*/ /*-> HW: s(7,1)*/
s8 pwr_ofst_mode[TPU_SIZE_MODE]; /*0~4: HE, VHT, HT, Legacy, CCK, */
s8 pwr_ofst_bw[TPU_SIZE_BW]; /*0~4: 80_80, 160, 80, 40, 20*/
/*[Pwr By rate]*/ /*-> HW: s(7,1)*/
struct rtw_tpu_pwr_by_rate_info rtw_tpu_pwr_by_rate_i;
/*[Pwr Limit]*/ /*-> HW: s(7,1)*/
struct rtw_tpu_pwr_imt_info rtw_tpu_pwr_imt_i;
/*[Pwr Limit RUA]*/ /*-> HW: s(7,1)*/
s8 pwr_lmt_ru[HAL_MAX_PATH][TPU_SIZE_RUA][TPU_SIZE_BW20_SC];
u16 pwr_lmt_ru_mem_size;
bool pwr_lmt_en;
u8 tx_ptrn_shap_idx;
u8 tx_ptrn_shap_idx_cck;
};
struct rtw_hal_stat_info {
u32 cnt_fail_all;
u32 cnt_cck_fail;
u32 cnt_ofdm_fail;
u32 cnt_cca_all;
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_crc32_error_all;
u32 cnt_he_crc32_error;
u32 cnt_vht_crc32_error;
u32 cnt_ht_crc32_error ;
u32 cnt_ofdm_crc32_error;
u32 cnt_cck_crc32_error;
u32 cnt_crc32_ok_all;
u32 cnt_he_crc32_ok;
u32 cnt_vht_crc32_ok;
u32 cnt_ht_crc32_ok;
u32 cnt_ofdm_crc32_ok;
u32 cnt_cck_crc32_ok;
u32 igi_fa_rssi;
};
struct rtw_hw_band {
struct rtw_chan_def cur_chandef;
u8 ppdu_sts_appen_info;
u8 ppdu_sts_filter;
struct rtw_tpu_info rtw_tpu_i; /*TX Power Unit (TPU)*/
u16 tx_pause[PAUSE_RSON_MAX]; /* ref: enum rtw_sch_txen_cfg */
struct rtw_hal_stat_info stat_info;
};
struct rtw_hal_com_t {
enum rtw_chip_id chip_id;
enum rtw_cv cv;
struct ver_ctrl_t mac_vc;
struct ver_ctrl_t bb_vc;
struct ver_ctrl_t rf_vc;
struct ver_ctrl_t btc_vc;
struct ver_ctrl_t fw_vc;
struct protocol_cap_t proto_hw_cap[MAX_BAND_NUM]; /* wifi protocol capability from EFUSE/halmac/halbb/halrf/... */
struct phy_hw_cap_t phy_hw_cap[MAX_BAND_NUM]; /* phy capability from EFUSE/halmac/halbb/halrf/... */
struct dev_cap_t dev_hw_cap;
struct bus_hw_cap_t bus_hw_cap; /* Bus HW capability */
struct bus_cap_t bus_cap; /* Final bus capability */
struct hal_io_priv iopriv;
#ifdef DBG_HAL_MAC_MEM_MOINTOR
_os_atomic hal_mac_mem;
#endif
#ifdef DBG_HAL_MEM_MOINTOR
_os_atomic hal_mem;
#endif
bool is_hal_init;
struct rtw_hw_band band[MAX_BAND_NUM];/*band0/band1 for DBCC*/
bool dbcc_en;
u8 assoc_sta_cnt; /*number of associated nodes (sta or ap)*/
u8 rfpath_tx_num; /* rf path - instead of rf_type -1T1R.... */
u8 rfpath_rx_num;
#ifdef RTW_WKARD_SINGLE_PATH_RSSI
enum rf_path cur_rx_rfpath;
#endif
bool ext_pwr_lmt_en;
struct rtw_tpu_ext_pwr_lmt_info rtw_tpu_ext_pwr_lmt_i[MAX_BAND_NUM];/*for phy0 & phy1 exetend power limit*/
#ifdef CONFIG_PCI_HCI /*TODO move to hal_info_t*/
/*interrupt*/
u32 int_array[4];
u32 int_mask[4];
u32 int_mask_default[4];
#endif /* CONFIG_PCI_HCI */
#ifdef CONFIG_SDIO_HCI /*TODO move to hal_info_t*/
u32 block_sz;
/*interrupt*/
/*
* Change type of int_mask from u32 to unsigned long for bit operation
* API, ex: _os_test_and_clear_bit() and _os_test_and_set_bit() .
*/
unsigned long int_mask;
u32 int_mask_default;
#endif /* CONFIG_SDIO_HCI */
struct hal_int_array intr;
#ifdef RTW_PHL_BCN
struct bcn_entry_pool bcn_pool;
#endif
struct rtw_trx_stat trx_stat;
void *hal_priv;/*pointer to hal_info*/
void *drv_priv; /*drv priv*/
void *csi_obj;
void *bf_obj;
void *snd_obj;
struct hal_mu_score_tbl bb_mu_score_tbl;
bool csi_para_ctrl_sel;
struct btc_ctrl_t btc_ctrl;
struct btc_fw_msg btc_msg;
#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL
u8 spe_pkt_cnt_lmt;
#endif
};
#define FL_CFG_OP_SET 0
#define FL_CFG_OP_CLR 1
#define FL_CFG_OP_INFO 2
#define FL_CFG_TYPE_LEVEL 0
#define FL_CFG_TYPE_OUTPUT 1
#define FL_CFG_TYPE_COMP 2
#define FL_CFG_TYPE_COMP_EXT 3
#define FL_LV_OFF 0
#define FL_LV_CRT 1
#define FL_LV_SER 2
#define FL_LV_WARN 3
#define FL_LV_LOUD 4
#define FL_LV_TR 5
#define FL_OP_UART BIT0
#define FL_OP_C2H BIT1
#define FL_OP_SNI BIT2
#define FL_COMP_VER BIT0
#define FL_COMP_INIT BIT1
#define FL_COMP_TASK BIT2
#define FL_COMP_CNS BIT3
#define FL_COMP_H2C BIT4
#define FL_COMP_C2H BIT5
#define FL_COMP_TX BIT6
#define FL_COMP_RX BIT7
#define FL_COMP_IPSEC BIT8
#define FL_COMP_TIMER BIT9
#define FL_COMP_DBGPKT BIT10
#define FL_COMP_PS BIT11
#define FL_COMP_BB BIT16
struct rtw_hal_fw_log_cfg {
u32 level;
u32 output;
u32 comp;
u32 comp_ext;
};
enum pkt_ofld_op_type {
PKT_OFLD_ADD = 0,
PKT_OFLD_DEL = 1,
PKT_OFLD_READ = 2,
PKT_OFLD_MAX
};
struct pkt_ofld_info {
struct list_head req_q;
u32 req_cnt;
u8 id;
};
struct pkt_ofld_entry {
struct list_head list;
u16 macid;
struct pkt_ofld_info pkt_info[PKT_OFLD_TYPE_MAX];
};
enum rtw_c2h_cat {
C2H_CAT_TEST = 0,
C2H_CAT_MAC = 1,
C2H_CAT_OUTSRC = 2,
C2H_CAT_MAX = 3
};
enum rtw_c2h_clas {
C2H_CLS_PHYDM_MIN = 0,
C2H_CLS_PHYDM_MAX = 7,
C2H_CLS_RF_MIN = 8,
C2H_CLS_RF_MAX = 0xf,
C2H_CLS_BTC_MIN = 0x10,
C2H_CLS_BTC_MAX = 0x17,
C2H_CLS_MAX = 0x18
};
#define C2H_CLS_MAC_MIN 0x00
#define C2H_CLS_MAC_MAX 0xFF
enum rtw_hal_ps_pwr_req_src {
HAL_BB_PWR_REQ = 0,
HAL_RF_PWR_REQ = 1,
HAL_MAC_PWR_REQ = 2,
HAL_BTC_PWR_REQ = 3
};
struct rtw_hal_lps_info {
u8 lps_en;
u16 macid;
enum rtw_lps_listen_bcn_mode listen_bcn_mode;
u8 awake_interval;
enum rtw_lps_smart_ps_mode smart_ps_mode;
};
enum ps_pwr_state {
PS_PWR_STATE_ACTIVE = 0,
PS_PWR_STATE_BAND0_RFON = 1,
PS_PWR_STATE_BAND1_RFON = 2,
PS_PWR_STATE_BAND0_RFOFF = 3,
PS_PWR_STATE_BAND1_RFOFF = 4,
PS_PWR_STATE_CLK_GATED = 5,
PS_PWR_STATE_PWR_GATED = 6,
PS_PWR_STATE_MAX,
};
#ifdef CONFIG_PHL_DFS
struct hal_dfs_rpt {
u8 *dfs_ptr;
u16 dfs_num;
u8 phy_idx; /*phy0,phy1*/
};
#endif
#ifdef CONFIG_WOWLAN
struct rtw_hal_wow_cfg {
struct rtw_keep_alive_info *keep_alive_cfg;
struct rtw_disc_det_info *disc_det_cfg;
struct rtw_nlo_info *nlo_cfg;
struct rtw_arp_ofld_info *arp_ofld_cfg;
struct rtw_ndp_ofld_info *ndp_ofld_cfg;
struct rtw_gtk_ofld_info *gtk_ofld_cfg;
struct rtw_realwow_info *realwow_cfg;
struct rtw_wow_wake_info *wow_wake_cfg;
struct rtw_pattern_match_info *pattern_match_info;
struct rtw_wow_gpio_info *wow_gpio;
};
#endif /* CONFIG_WOWLAN */
enum hal_tsf_sync_act {
HAL_TSF_SYNC_NOW_ONCE = 0,
HAL_TSF_EN_SYNC_AUTO = 1,
HAL_TSF_DIS_SYNC_AUTO = 2,
};
#ifdef CONFIG_RTW_ACS
struct auto_chan_sel_report {
u8 clm_ratio;
u8 nhm_pwr;
};
#endif
struct watchdog_nhm_report {
u8 ccx_rpt_stamp;
u8 ccx_rpt_result;
s8 nhm_pwr_dbm;
u8 nhm_ratio;
};
struct hal_mac_dbg_dump_cfg {
u32 ss_dbg_0;
u32 ss_dbg_1;
u8 ss_dbg;
u8 dle_dbg;
u8 dmac_dbg;
u8 cmac_dbg;
u8 mac_dbg_port;
u8 plersvd_dbg;
u8 tx_flow_dbg;
};
#endif /*_HAL_DEF_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_def.h
|
C
|
agpl-3.0
| 30,252
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_DEF_BTC_H_
#define _HAL_DEF_BTC_H_
#endif /*_HAL_DEF_BTC_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_def_btc.h
|
C
|
agpl-3.0
| 725
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_DEF_MAC_H_
#define _HAL_DEF_MAC_H_
#endif /*_HAL_DEF_MAC_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_def_mac.h
|
C
|
agpl-3.0
| 725
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_DEF_PHY_H_
#define _HAL_DEF_PHY_H_
#endif /*_HAL_DEF_PHY_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_def_phy.h
|
C
|
agpl-3.0
| 725
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_EXT_TX_PWR_LMT_C_
#include "hal_headers.h"
enum rtw_hal_status
rtw_hal_set_power_lmt(void *hal, u8 band_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
enum phl_phy_idx phy_idx = HW_PHY_0;
if (band_idx == 1)
phy_idx = HW_PHY_1;
status = rtw_hal_rf_set_power(hal_info, phy_idx, PWR_LIMIT);
return status;
}
void
rtw_hal_enable_ext_pwr_lmt(void *hal, u8 hw_band,
struct rtw_tpu_ext_pwr_lmt_info *ext_pwr_lmt_info)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct rtw_tpu_ext_pwr_lmt_info *tpu_ext_pwr_lmt_info;
u8 i;
PHL_INFO("%s\n", __func__);
tpu_ext_pwr_lmt_info = &(hal_com->rtw_tpu_ext_pwr_lmt_i[hw_band]);
/* enable external tx power limit mechanism */
hal_com->ext_pwr_lmt_en = true;
/* Fill external tx power limit into hal_com->rtw_tpu_ext_pwr_lmt_info */
for (i = 0; i < HAL_MAX_PATH; i++) {
tpu_ext_pwr_lmt_info->ext_pwr_lmt_2_4g[i]
= ext_pwr_lmt_info->ext_pwr_lmt_2_4g[i];
tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band1[i]
= ext_pwr_lmt_info->ext_pwr_lmt_5g_band1[i];
tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band2[i]
= ext_pwr_lmt_info->ext_pwr_lmt_5g_band2[i];
tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band3[i]
= ext_pwr_lmt_info->ext_pwr_lmt_5g_band3[i];
tpu_ext_pwr_lmt_info->ext_pwr_lmt_5g_band4[i]
= ext_pwr_lmt_info->ext_pwr_lmt_5g_band4[i];
}
rtw_hal_rf_update_ext_pwr_lmt_table(hal_info);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ext_tx_pwr_lmt.c
|
C
|
agpl-3.0
| 2,157
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_FW_C_
#include "hal_headers.h"
static void _hal_send_fwdl_hub_msg(struct rtw_phl_com_t *phl_com, u8 dl_ok)
{
struct phl_msg msg = {0};
u16 evt_id = (dl_ok) ? MSG_EVT_FWDL_OK : MSG_EVT_FWDL_FAIL;
msg.inbuf = NULL;
msg.inlen = 0;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id);
msg.band_idx = HW_BAND_0;
rtw_phl_msg_hub_hal_send(phl_com, NULL, &msg);
}
static void _hal_fw_log_set(struct rtw_hal_fw_log_cfg *fl_cfg, u8 type, u32 value)
{
switch(type) {
case FL_CFG_TYPE_LEVEL:
fl_cfg->level = value;
break;
case FL_CFG_TYPE_OUTPUT:
fl_cfg->output |= value;
break;
case FL_CFG_TYPE_COMP:
fl_cfg->comp |= value;
break;
case FL_CFG_TYPE_COMP_EXT:
fl_cfg->comp_ext |= value;
break;
default:
break;
}
}
static void _hal_fw_log_clr(struct rtw_hal_fw_log_cfg *fl_cfg, u8 type, u32 value)
{
switch(type) {
case FL_CFG_TYPE_LEVEL:
break;
case FL_CFG_TYPE_OUTPUT:
fl_cfg->output &= (~value);
break;
case FL_CFG_TYPE_COMP:
fl_cfg->comp &= (~value);
break;
case FL_CFG_TYPE_COMP_EXT:
fl_cfg->comp_ext &= (~value);
break;
default:
break;
}
}
static void _hal_fw_log_info(struct rtw_hal_fw_log_cfg *fl_cfg)
{
PHL_PRINT("%s: level %d, output 0x%08x, comp 0x%08x, comp ext 0x%08x.\n",
__func__,
fl_cfg->level,
fl_cfg->output,
fl_cfg->comp,
fl_cfg->comp_ext);
}
enum rtw_hal_status rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value)
{
struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)hal;
static struct rtw_hal_fw_log_cfg fl_cfg = {0};
switch(op) {
case FL_CFG_OP_SET:
_hal_fw_log_set(&fl_cfg, type, value);
break;
case FL_CFG_OP_CLR:
_hal_fw_log_clr(&fl_cfg, type, value);
break;
case FL_CFG_OP_INFO:
_hal_fw_log_info(&fl_cfg);
break;
default:
break;
}
return rtw_hal_mac_fw_log_cfg(hal_com, &fl_cfg);
}
void hal_fw_en_basic_log(struct rtw_hal_com_t *hal_com)
{
rtw_hal_fw_log_cfg(hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_LEVEL,
FL_LV_LOUD);
rtw_hal_fw_log_cfg(hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_OUTPUT,
FL_OP_C2H);
rtw_hal_fw_log_cfg(hal_com, FL_CFG_OP_SET, FL_CFG_TYPE_COMP,
FL_COMP_TASK);
}
enum rtw_hal_status rtw_hal_cfg_fw_ps_log(void *hal, u8 en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
if(en)
return rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_SET,
FL_CFG_TYPE_COMP, FL_COMP_PS);
else
return rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_CLR,
FL_CFG_TYPE_COMP, FL_COMP_PS);
}
enum rtw_hal_status rtw_hal_cfg_fw_mcc_log(void *hal, u8 en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
if(en)
status = rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_SET,
FL_CFG_TYPE_COMP, MAC_AX_FL_COMP_MCC);
else
status = rtw_hal_fw_log_cfg(hal_info->hal_com, FL_CFG_OP_CLR,
FL_CFG_TYPE_COMP, MAC_AX_FL_COMP_MCC);
PHL_INFO("rtw_hal_cfg_fw_mcc_log(): status(%d), en(%d)\n", status, en);
return status;
}
enum rtw_hal_status
rtw_hal_download_fw(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct rtw_fw_info_t *fw_info = &phl_com->fw_info;
FUNCIN_WSTS(hal_status);
if (!fw_info->fw_en)
return hal_status;
if (fw_info->dlrom_en) {
hal_status = rtw_hal_mac_romdl(hal_info, fw_info->rom_buff,
fw_info->rom_size);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
}
hal_status = rtw_hal_mac_disable_cpu(hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("disable cpu fail!\n");
return hal_status;
}
hal_status = rtw_hal_mac_enable_cpu(hal_info, 0, true);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("enable cpu fail!\n");
return hal_status;
}
if (fw_info->dlram_en) {
hal_status = rtw_hal_mac_fwdl(hal_info, fw_info->ram_buff,
fw_info->ram_size);
}
_hal_send_fwdl_hub_msg(phl_com, (!hal_status) ? true : false);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
enum rtw_hal_status
rtw_hal_redownload_fw(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct rtw_fw_info_t *fw_info = &phl_com->fw_info;
FUNCIN_WSTS(hal_status);
/* Disable/Enable CPU is necessary first when FWDL from files */
if(fw_info->dlram_en && fw_info->fw_src == RTW_FW_SRC_EXTNAL) {
hal_status = rtw_hal_mac_disable_cpu(hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("disable cpu fail!\n");
return hal_status;
}
hal_status = rtw_hal_mac_enable_cpu(hal_info, 0, true);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("enable cpu fail!\n");
return hal_status;
}
}
if (fw_info->dlram_en) {
if(fw_info->fw_src == RTW_FW_SRC_EXTNAL) {
hal_status = rtw_hal_mac_fwdl(hal_info, fw_info->ram_buff,
fw_info->ram_size);
} else {
hal_status = rtw_hal_mac_enable_fw(hal_info, fw_info->fw_type);
}
}
rtw_phl_pkt_ofld_reset_all_entry(phl_com);
rtw_hal_rf_config_radio_to_fw(hal_info);
_hal_send_fwdl_hub_msg(phl_com, (!hal_status) ? true : false);
FUNCOUT_WSTS(hal_status);
return hal_status;
}
void rtw_hal_fw_dbg_dump(void *hal, u8 is_low_power)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
rtw_hal_mac_fw_dbg_dump(hal_info, is_low_power);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_fw.c
|
C
|
agpl-3.0
| 6,079
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_FW_H_
#define _HAL_FW_H_
enum rtw_hal_status
rtw_hal_download_fw(struct rtw_phl_com_t *phl_com, void *hal);
enum rtw_hal_status
rtw_hal_redownload_fw(struct rtw_phl_com_t *phl_com, void *hal);
void rtw_hal_fw_dbg_dump(void *hal, u8 is_low_power);
enum rtw_hal_status
rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value);
void hal_fw_en_basic_log(struct rtw_hal_com_t *hal_com);
#endif /* _HAL_FW_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_fw.h
|
C
|
agpl-3.0
| 1,074
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_GENERAL_DEF_H_
#define _HAL_GENERAL_DEF_H_
enum rtw_chip_id {
CHIP_WIFI6_8852A,
CHIP_WIFI6_8834A,
CHIP_WIFI6_8852B,
CHIP_WIFI6_8852C,
CHIP_WIFI6_MAX
};
enum rtw_efuse_info {
/* MAC Part */
EFUSE_INFO_MAC_ADDR,
EFUSE_INFO_MAC_PID,
EFUSE_INFO_MAC_DID,
EFUSE_INFO_MAC_VID,
EFUSE_INFO_MAC_SVID,
EFUSE_INFO_MAC_SMID,
EFUSE_INFO_MAC_MAX,
/* BB Part */
EFUSE_INFO_BB_ANTDIV,
EFUSE_INFO_BB_MAX,
/* RF Part */
EFUSE_INFO_RF_PKG_TYPE,
EFUSE_INFO_RF_PA,
EFUSE_INFO_RF_VALID_PATH,
EFUSE_INFO_RF_RFE,
EFUSE_INFO_RF_TXPWR,
EFUSE_INFO_RF_BOARD_OPTION,
EFUSE_INFO_RF_CHAN_PLAN,
EFUSE_INFO_RF_CHAN_PLAN_FORCE_HW,
EFUSE_INFO_RF_COUNTRY,
EFUSE_INFO_RF_THERMAL,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_14,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_14,
EFUSE_INFO_RF_THERMAL_A,
EFUSE_INFO_RF_THERMAL_B,
EFUSE_INFO_RF_THERMAL_C,
EFUSE_INFO_RF_THERMAL_D,
EFUSE_INFO_RF_XTAL,
/*RX Gain K*/
EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK,
EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD,
EFUSE_INFO_RF_RX_GAIN_K_A_5GL,
EFUSE_INFO_RF_RX_GAIN_K_A_5GM,
EFUSE_INFO_RF_RX_GAIN_K_A_5GH,
EFUSE_INFO_RF_MAX,
/* BTCOEX Part */
EFUSE_INFO_BTCOEX_COEX,
EFUSE_INFO_BTCOEX_ANT_NUM,
EFUSE_INFO_BTCOEX_ANT_PATH,
EFUSE_INFO_BTCOEX_MAX,
};
enum rtw_cv {
CAV,
CBV,
CCV,
CDV,
CEV,
CFV,
CGV,
CTV,
CMAXV,
};
enum rtw_fv {
FTV,
FUV,
FSV,
};
enum rtw_dv_sel {
DAV,
DDV,
};
enum hal_pwr_by_rate_setting {
PW_BY_RATE_ON = 0,
PW_BY_RATE_ALL_SAME = 1
};
enum hal_pwr_limit_type {
PWLMT_BY_EFUSE = 0,
PWLMT_DISABLE = 1,
PWBYRATE_AND_PWLMT = 2
};
enum rtw_mac_gfunc {
RTW_MAC_GPIO_WL_PD,
RTW_MAC_GPIO_BT_PD,
RTW_MAC_GPIO_WL_EXTWOL,
RTW_MAC_GPIO_BT_GPIO,
RTW_MAC_GPIO_WL_SDIO_INT,
RTW_MAC_GPIO_BT_SDIO_INT,
RTW_MAC_GPIO_WL_FLASH,
RTW_MAC_GPIO_BT_FLASH,
RTW_MAC_GPIO_SIC,
RTW_MAC_GPIO_LTE_UART,
RTW_MAC_GPIO_LTE_3W,
RTW_MAC_GPIO_WL_PTA,
RTW_MAC_GPIO_BT_PTA,
RTW_MAC_GPIO_MAILBOX,
RTW_MAC_GPIO_WL_LED,
RTW_MAC_GPIO_OSC,
RTW_MAC_GPIO_XTAL_CLK,
RTW_MAC_GPIO_EXT_XTAL_CLK,
RTW_MAC_GPIO_DBG_GNT,
RTW_MAC_GPIO_WL_RFE_CTRL,
RTW_MAC_GPIO_BT_UART_RQB,
RTW_MAC_GPIO_BT_WAKE_HOST,
RTW_MAC_GPIO_HOST_WAKE_BT,
RTW_MAC_GPIO_DBG,
RTW_MAC_GPIO_WL_UART_TX,
RTW_MAC_GPIO_WL_UART_RX,
RTW_MAC_GPIO_WL_JTAG,
RTW_MAC_GPIO_SW_IO,
/* keep last */
RTW_MAC_GPIO_LAST,
RTW_MAC_GPIO_MAX = RTW_MAC_GPIO_LAST,
RTW_MAC_GPIO_INVALID = RTW_MAC_GPIO_LAST,
RTW_MAC_GPIO_DFLT = RTW_MAC_GPIO_LAST,
};
#ifdef CONFIG_FW_IO_OFLD_SUPPORT
enum rtw_mac_src_cmd_ofld {
RTW_MAC_BB_CMD_OFLD = 0,
RTW_MAC_RF_CMD_OFLD,
RTW_MAC_MAC_CMD_OFLD,
RTW_MAC_OTHER_CMD_OFLD
};
enum rtw_mac_cmd_type_ofld {
RTW_MAC_WRITE_OFLD = 0,
RTW_MAC_COMPARE_OFLD,
RTW_MAC_DELAY_OFLD
};
enum rtw_mac_rf_path {
RTW_MAC_RF_PATH_A = 0, //Radio Path A
RTW_MAC_RF_PATH_B, //Radio Path B
RTW_MAC_RF_PATH_C, //Radio Path C
RTW_MAC_RF_PATH_D, //Radio Path D
};
struct rtw_mac_cmd {
enum rtw_mac_src_cmd_ofld src;
enum rtw_mac_cmd_type_ofld type;
u8 lc;
enum rtw_mac_rf_path rf_path;
u16 offset;
u16 id;
u32 value;
u32 mask;
};
enum rtw_fw_ofld_cap {
FW_CAP_IO_OFLD = BIT(0),
};
#endif
enum wl_func {
EFUSE_WL_FUNC_NONE = 0,
EFUSE_WL_FUNC_DRAGON = 0xe,
EFUSE_WL_FUNC_GENERAL = 0xf
};
enum hw_stype{
EFUSE_HW_STYPE_NONE = 0x0,
EFUSE_HW_STYPE_GENERAL = 0xf
};
#endif /* _HAL_GENERAL_DEF_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_general_def.h
|
C
|
agpl-3.0
| 7,543
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_HEADERS_H_
#define _HAL_HEADERS_H_
#include "../rtw_general_def.h"
#include "../phl_list.h"
#include "../phl_status.h"
#include "../pltfm_ops.h"
#include "../phl_config.h"
#include "../phl_types.h"
#include "../phl_util.h"
#include "../phl_def.h"
#include "../phl_debug.h"
#include "../phl_trx_def.h"
#include "../phl_wow_def.h"
#include "../phl_p2pps_def.h"
#include "../phl_btc_def.h"
#include "../phl_test_def.h"
#include "../phl_ser_def.h"
#include "../phl_regulation_def.h"
#include "../phl_led_def.h"
#include "../custom/phl_custom_def.h"
#include "../custom/phl_custom_api.h"
#ifdef CONFIG_PCI_HCI
#include "../hci/phl_trx_def_pcie.h"
#endif
#ifdef CONFIG_USB_HCI
#include "../hci/phl_trx_def_usb.h"
#endif
#ifdef CONFIG_SDIO_HCI
#include "../hci/phl_trx_def_sdio.h"
#endif
#include "hal_general_def.h"
#include "hal_def.h"
#include "hal_config.h"
#include "../phl_api_drv.h"
#include "hal_struct.h"
#include "hal_io.h"
#include "hal_api_mac.h"
#include "hal_api_bb.h"
#include "hal_api_rf.h"
#include "hal_api_btc.h"
#include "hal_api_efuse.h"
#include "hal_str_proc.h"
#include "hal_tx.h"
#include "hal_rx.h"
#include "hal_sta.h"
#include "hal_chan.h"
#ifdef CONFIG_PHL_CHANNEL_INFO
#include "hal_chan_info.h"
#endif /* CONFIG_PHL_CHANNEL_INFO */
#include "hal_fw.h"
#include "hal_wow.h"
#include "hal_csi_buffer.h"
#include "hal_beamform.h"
#include "hal_sound.h"
#include "hal_ser.h"
#include "hal_c2h.h"
#include "hal_acs.h"
#include "hal_mcc_def.h"
#include "hal_ld_file.h"
#include "hal_notify.h"
#include "hal_ps.h"
#include "hal_custom.h"
#include "hal_txpwr.h"
#define hal_to_drvpriv(_halinfo) (_halinfo->hal_com->drv_priv)
#endif /*_HAL_HEADERS_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_headers.h
|
C
|
agpl-3.0
| 2,337
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_HEADERS_LE_H_
#define _HAL_HEADERS_LE_H_
/* Common definition from PHL */
#include "../rtw_general_def.h"
#include "../phl_list.h"
#include "../phl_status.h"
#include "../pltfm_ops.h"
#include "../phl_config.h"
#include "../phl_types.h"
#include "../phl_regulation_def.h"
#include "../phl_chnlplan.h"
#include "../phl_country.h"
#include "../phl_txpwr.h"
/* Exported structure/definition from PHL */
#include "../phl_util.h"
#include "../phl_def.h"
#include "../phl_trx_def.h"
#include "../phl_wow_def.h"
#include "../phl_btc_def.h"
#include "../phl_test_def.h"
#include "../phl_debug.h"
#ifdef CONFIG_PCI_HCI
#include "../hci/phl_trx_def_pcie.h"
#endif
#ifdef CONFIG_USB_HCI
#include "../hci/phl_trx_def_usb.h"
#endif
#ifdef CONFIG_SDIO_HCI
#include "../hci/phl_trx_def_sdio.h"
#endif
/* Common definition from HAL*/
#include "hal_general_def.h"
/* Exported structure/definition from HAL */
#include "hal_def.h"
#include "hal_config.h"
/*
Exported hal API from HAL
Prevent HAL mac/bb/ rf/ btc cross referencing
*/
#include "hal_api_drv.h"
#include "hal_io.h" /*exported hal_read, hal_write API from HAL */
#include "hal_fw.h"
#if 1
static inline void hal_mdelay(struct rtw_hal_com_t *h, int ms)
{
_os_delay_ms(halcom_to_drvpriv(h), ms);
}
static inline void hal_udelay(struct rtw_hal_com_t *h, int us)
{
_os_delay_ms(halcom_to_drvpriv(h), us);
}
static inline void hal_msleep(struct rtw_hal_com_t *h, int ms)
{
_os_sleep_ms(halcom_to_drvpriv(h),ms);
}
static inline void hal_usleep(struct rtw_hal_com_t *h, int us)
{
_os_sleep_us(halcom_to_drvpriv(h), us);
}
#ifdef DBG_HAL_MEM_MOINTOR
static inline void *hal_mem_alloc(struct rtw_hal_com_t *h, u32 buf_sz)
{
_os_atomic_sub(halcom_to_drvpriv(h), &(h->hal_mem), buf_sz);
return _os_mem_alloc(halcom_to_drvpriv(h), buf_sz);
}
static inline void hal_mem_free(struct rtw_hal_com_t *h, void *buf, u32 buf_sz)
{
_os_atomic_add_return(halcom_to_drvpriv(h), &(h->hal_mem), buf_sz);
_os_mem_free(halcom_to_drvpriv(h), buf, buf_sz);
}
#else
static inline void *hal_mem_alloc(struct rtw_hal_com_t *h, u32 buf_sz)
{
return _os_mem_alloc(halcom_to_drvpriv(h), buf_sz);
}
static inline void hal_mem_free(struct rtw_hal_com_t *h, void *buf, u32 buf_sz)
{
_os_mem_free(halcom_to_drvpriv(h), buf, buf_sz);
}
#endif /*DBG_HAL_MEM_MOINTOR*/
static inline void hal_mem_set(struct rtw_hal_com_t *h, void *buf, s8 value, u32 size)
{
_os_mem_set(halcom_to_drvpriv(h), buf, value, size);
}
static inline void hal_mem_cpy(struct rtw_hal_com_t *h, void *dest,
void *src, u32 size)
{
_os_mem_cpy(halcom_to_drvpriv(h), dest, src, size);
}
static inline int hal_mem_cmp(struct rtw_hal_com_t *h, void *dest,
void *src, u32 size)
{
return _os_mem_cmp(halcom_to_drvpriv(h), dest, src, size);
}
static inline void hal_mutex_init(struct rtw_hal_com_t *h, _os_mutex *mutex)
{
_os_mutex_init(halcom_to_drvpriv(h), mutex);
}
static inline void hal_mutex_deinit(struct rtw_hal_com_t *h, _os_mutex *mutex)
{
_os_mutex_deinit(halcom_to_drvpriv(h), mutex);
}
static inline void hal_mutex_lock(struct rtw_hal_com_t *h, _os_mutex *mutex)
{
_os_mutex_lock(halcom_to_drvpriv(h), mutex);
}
static inline void hal_mutex_unlock(struct rtw_hal_com_t *h, _os_mutex *mutex)
{
_os_mutex_unlock(halcom_to_drvpriv(h), mutex);
}
static inline void hal_init_timer(struct rtw_hal_com_t *h, _os_timer *timer,
void (*call_back_func)(void* context),
void *context, const char *sz_id)
{
_os_init_timer(halcom_to_drvpriv(h), timer, call_back_func, context, sz_id);
}
static inline void hal_set_timer(struct rtw_hal_com_t *h, _os_timer *timer,
u32 ms_delay)
{
_os_set_timer(halcom_to_drvpriv(h), timer, ms_delay);
}
static inline void hal_cancel_timer(struct rtw_hal_com_t *h, _os_timer *timer)
{
_os_cancel_timer(halcom_to_drvpriv(h), timer);
}
static inline void hal_release_timer(struct rtw_hal_com_t *h, _os_timer *timer)
{
_os_release_timer(halcom_to_drvpriv(h), timer);
}
/*IO OPS*/
#ifdef CONFIG_PCI_HCI
static inline u8 hal_pci_read8(struct rtw_hal_com_t *h,u32 addr)
{
return _os_read8_pcie(halcom_to_drvpriv(h), addr);
}
static inline u16 hal_pci_read16(struct rtw_hal_com_t *h,u32 addr)
{
return _os_read16_pcie(halcom_to_drvpriv(h), addr);
}
static inline u32 hal_pci_read32(struct rtw_hal_com_t *h,u32 addr)
{
return _os_read32_pcie(halcom_to_drvpriv(h), addr);
}
static inline int hal_pci_write8(struct rtw_hal_com_t *h, u32 addr, u8 val)
{
return _os_write8_pcie(halcom_to_drvpriv(h), addr, val);
}
static inline int hal_pci_write16(struct rtw_hal_com_t *h, u32 addr, u16 val)
{
return _os_write16_pcie(halcom_to_drvpriv(h), addr, val);
}
static inline int hal_pci_write32(struct rtw_hal_com_t *h, u32 addr, u32 val)
{
return _os_write32_pcie(halcom_to_drvpriv(h), addr, val);
}
#endif
#ifdef CONFIG_USB_HCI
static inline int hal_usb_vendor_req(struct rtw_hal_com_t *h,
u8 request, u16 value, u16 index,
void *pdata, u16 len, u8 requesttype)
{
return _os_usbctrl_vendorreq(halcom_to_drvpriv(h), request, value,
index, pdata, len, requesttype);
}
#endif /*CONFIG_USB_HCI*/
#ifdef CONFIG_SDIO_HCI
static inline u8 hal_sdio_cmd52_r8(struct rtw_hal_com_t *h, u32 offset)
{
return _os_sdio_cmd52_r8(halcom_to_drvpriv(h), offset);
}
static inline u8 hal_sdio_cmd53_r8(struct rtw_hal_com_t *h, u32 offset)
{
return _os_sdio_cmd53_r8(halcom_to_drvpriv(h), offset);
}
static inline u16 hal_sdio_cmd53_r16(struct rtw_hal_com_t *h, u32 offset)
{
return _os_sdio_cmd53_r16(halcom_to_drvpriv(h), offset);
}
static inline u32 hal_sdio_cmd53_r32(struct rtw_hal_com_t *h, u32 offset)
{
return _os_sdio_cmd53_r32(halcom_to_drvpriv(h), offset);
}
static inline u8 hal_sdio_cmd53_rn(struct rtw_hal_com_t *h,
u32 offset, u32 size, u8 *data)
{
return _os_sdio_cmd53_rn(halcom_to_drvpriv(h), offset, size, data);
}
static inline u8 hal_sdio_cmd53_r(struct rtw_hal_com_t *h,
u32 offset, u32 size, u8 *val)
{
size = _ALIGN(size, 4);
if (size > h->block_sz)
size = _ALIGN(size, h->block_sz);
return _os_sdio_cmd53_r(halcom_to_drvpriv(h), offset, size, val);
}
static inline void hal_sdio_cmd52_w8(struct rtw_hal_com_t *h,
u32 offset, u8 val)
{
_os_sdio_cmd52_w8(halcom_to_drvpriv(h), offset, val);
}
static inline void hal_sdio_cmd53_w8(struct rtw_hal_com_t *h,
u32 offset, u8 val)
{
_os_sdio_cmd53_w8(halcom_to_drvpriv(h), offset, val);
}
static inline void hal_sdio_cmd53_w16(struct rtw_hal_com_t *h,
u32 offset, u16 val)
{
_os_sdio_cmd53_w16(halcom_to_drvpriv(h), offset, val);
}
static inline void hal_sdio_cmd53_w32(struct rtw_hal_com_t *h,
u32 offset, u32 val)
{
_os_sdio_cmd53_w32(halcom_to_drvpriv(h), offset, val);
}
static inline void hal_sdio_cmd53_wn(struct rtw_hal_com_t *h,
u32 offset, u32 size, u8 *val)
{
_os_sdio_cmd53_wn(halcom_to_drvpriv(h), offset, size, val);
}
static inline void hal_sdio_cmd53_w(struct rtw_hal_com_t *h,
u32 offset, u32 size, u8 *val)
{
size = _ALIGN(size, 4);
if (size > h->block_sz)
size = _ALIGN(size, h->block_sz);
_os_sdio_cmd53_w(halcom_to_drvpriv(h), offset, size, val);
}
static inline u8 hal_sdio_f0_read(struct rtw_hal_com_t *h,
u32 addr, void *buf, u32 len)
{
return _os_sdio_f0_read(halcom_to_drvpriv(h), addr, buf, len);
}
static inline u8 hal_sdio_read_cia_r8(struct rtw_hal_com_t *h, u32 addr)
{
return _os_sdio_read_cia_r8(halcom_to_drvpriv(h), addr);
}
#endif /*CONFIG_SDIO_HCI*/
#else
/*please refer to hal_pltfm_ops.h*/
#define hal_mdelay(h, ms) _os_delay_ms(halcom_to_drvpriv(h), ms)
#define hal_udelay(h, us) _os_delay_ms(halcom_to_drvpriv(h), us)
#define hal_msleep(h, ms) _os_sleep_ms(halcom_to_drvpriv(h),ms)
#define hal_usleep(h, us) _os_sleep_us(halcom_to_drvpriv(h), us)
#define hal_mem_alloc(h, buf_sz) _os_mem_alloc(halcom_to_drvpriv(h), buf_sz)
#define hal_mem_free(h, buf, buf_sz) _os_mem_free(halcom_to_drvpriv(h), buf, buf_sz)
#define hal_mem_set(h, buf, value, size) _os_mem_set(halcom_to_drvpriv(h), buf, value, size)
#define hal_mem_cpy(h, dest, src, size) _os_mem_cpy(halcom_to_drvpriv(h), dest, src, size)
#define hal_mem_cmp(h, dest, src, size) _os_mem_cmp(halcom_to_drvpriv(h), dest, src, size)
#define hal_mutex_init(h, mutex) _os_mutex_init(halcom_to_drvpriv(h), mutex)
#define hal_mutex_deinit(h, hmutex) _os_mutex_deinit(halcom_to_drvpriv(h), mutex)
#define hal_mutex_lock(h, mutex) _os_mutex_lock(halcom_to_drvpriv(h), mutex)
#define hal_mutex_unlock(h, mutex) _os_mutex_unlock(halcom_to_drvpriv(h), mutex)
#define hal_init_timer(h, timer, call_back_func, context, sz_id) \
_os_init_timer(halcom_to_drvpriv(h), timer, call_back_func, context, sz_id)
#define hal_set_timer(h, timer, ms_delay) _os_set_timer(halcom_to_drvpriv(h), timer, ms_delay)
#define hal_cancel_timer(h, timer) _os_cancel_timer(halcom_to_drvpriv(h), timer)
#define hal_release_timer(h, timer) _os_release_timer(halcom_to_drvpriv(h), timer)
/*IO OPS*/
#ifdef CONFIG_PCI_HCI
#define hal_pci_read8(h, addr) _os_read8_pcie(halcom_to_drvpriv(h), addr)
#define hal_pci_read16(h, addr) _os_read16_pcie(halcom_to_drvpriv(h), addr)
#define hal_pci_read32(h, addr) _os_read32_pcie(halcom_to_drvpriv(h), addr)
#define hal_pci_write8(h, addr, val) _os_write8_pcie(halcom_to_drvpriv(h), addr, val)
#define hal_pci_write16(h, addr, val) _os_write16_pcie(halcom_to_drvpriv(h), addr, val)
#define hal_pci_write32(h, addr, val) _os_write32_pcie(halcom_to_drvpriv(h), addr, val)
#endif
#ifdef CONFIG_USB_HCI
#define hal_usb_vendor_req(h, request, value, index, pdata, len, requesttype) \
_os_usbctrl_vendorreq(halcom_to_drvpriv(h), request, value, index, pdata, len, requesttype)
#endif /*CONFIG_USB_HCI*/
#ifdef CONFIG_SDIO_HCI
#define hal_sdio_cmd52_r8(h, offset) _os_sdio_cmd52_r8(halcom_to_drvpriv(h), offset)
#define hal_sdio_cmd53_r8(h, offset) _os_sdio_cmd53_r8(halcom_to_drvpriv(h), offset)
#define hal_sdio_cmd53_r16(h, offset) _os_sdio_cmd53_r16(halcom_to_drvpriv(h), offset)
#define hal_sdio_cmd53_r32(h, offset) _os_sdio_cmd53_r32(halcom_to_drvpriv(h), offset)
#define hal_sdio_cmd53_rn(h, offset, size, data) _os_sdio_cmd53_rn(halcom_to_drvpriv(h), offset, size, data)
#define hal_sdio_cmd52_w8(h, offset, val) _os_sdio_cmd52_w8(halcom_to_drvpriv(h), offset, val)
#define hal_sdio_cmd53_w8(h, offset, val) _os_sdio_cmd53_w8(halcom_to_drvpriv(h), offset, val)
#define hal_sdio_cmd53_w16(h, offset, val) _os_sdio_cmd53_w16(halcom_to_drvpriv(h), offset, val)
#define hal_sdio_cmd53_w32(h, offset, val) _os_sdio_cmd53_w32(halcom_to_drvpriv(h), offset, val)
#define hal_sdio_f0_read(h, addr, buf, len) _os_sdio_f0_read(halcom_to_drvpriv(h), addr, buf, len)
#define hal_sdio_read_cia_r8(h, addr) _os_sdio_read_cia_r8(halcom_to_drvpriv(h), addr)
#endif /*CONFIG_SDIO_HCI*/
#endif
#endif /*_HAL_HEADERS_LE_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_headers_le.h
|
C
|
agpl-3.0
| 11,384
|
/******************************************************************************
*
* Copyright(c) 2019 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_INIT_C_
#include "hal_headers.h"
#if defined(CONFIG_PCI_HCI)
#include "hal_pci.h"
#elif defined(CONFIG_USB_HCI)
#include "hal_usb.h"
#elif defined(CONFIG_SDIO_HCI)
#include "hal_sdio.h"
#endif
/******************* IO APIs *******************/
u8 rtw_hal_read8(void *h, u32 addr)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return hal_read8(hal_com, addr);
}
u16 rtw_hal_read16(void *h, u32 addr)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return hal_read16(hal_com, addr);
}
u32 rtw_hal_read32(void *h, u32 addr)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return hal_read32(hal_com, addr);
}
void rtw_hal_write8(void *h, u32 addr, u8 val)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
hal_write8(hal_com, addr, val);
}
void rtw_hal_write16(void *h, u32 addr, u16 val)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
hal_write16(hal_com, addr, val);
}
void rtw_hal_write32(void *h, u32 addr, u32 val)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
hal_write32(hal_com, addr, val);
}
u32 rtw_hal_read_macreg(void *h, u32 offset, u32 bit_mask)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
return hal_ops->read_macreg(hal, offset, bit_mask);
}
void rtw_hal_write_macreg(void *h,
u32 offset, u32 bit_mask, u32 data)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
hal_ops->write_macreg(hal, offset, bit_mask, data);
}
u32 rtw_hal_read_bbreg(void *h, u32 offset, u32 bit_mask)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
return hal_ops->read_bbreg(hal, offset, bit_mask);
}
void rtw_hal_write_bbreg(void *h,
u32 offset, u32 bit_mask, u32 data)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
hal_ops->write_bbreg(hal, offset, bit_mask, data);
}
u32 rtw_hal_read_rfreg(void *h,
enum rf_path path, u32 offset, u32 bit_mask)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
return hal_ops->read_rfreg(hal, path, offset, bit_mask);
}
void rtw_hal_write_rfreg(void *h,
enum rf_path path, u32 offset, u32 bit_mask, u32 data)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
hal_ops->write_rfreg(hal, path, offset, bit_mask, data);
}
#ifdef PHL_PLATFORM_LINUX
void rtw_hal_mac_reg_dump(void *sel, void *h)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal = hal_info->hal_com;
int i, j = 1;
RTW_PRINT_SEL(sel, "======= MAC REG =======\n");
for (i = 0x0; i < 0x800; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
#if 1
for (i = 0x1000; i < 0xF000; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
#endif
}
void rtw_hal_bb_reg_dump(void *sel, void *h)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal = hal_info->hal_com;
int i, j = 1;
RTW_PRINT_SEL(sel, "======= BB REG =======\n");
for (i = 0x800; i < 0x1000; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
#if 0
for (i = 0x1800; i < 0x2000; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
#endif
#if 0
for (i = 0x2c00; i < 0x2c60; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
for (i = 0x2d00; i < 0x2df0; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
for (i = 0x4000; i < 0x4060; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
for (i = 0x4100; i < 0x4200; i += 4) {
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
#endif
}
void rtw_hal_bb_reg_dump_ex(void *sel, void *h)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal = hal_info->hal_com;
int i;
RTW_PRINT_SEL(sel, "======= BB REG =======\n");
for (i = 0x800; i < 0x1000; i += 4) {
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
_RTW_PRINT_SEL(sel, "\n");
}
#if 0
for (i = 0x1800; i < 0x2000; i += 4) {
RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
_RTW_PRINT_SEL(sel, "\n");
}
#endif
}
void rtw_hal_rf_reg_dump(void *sel, void *h)
{
#ifdef RTW_WKARD_RF_CR_DUMP
int i, j = 1, path;
struct hal_info_t *hal_info = (struct hal_info_t *)h;
struct rtw_hal_com_t *hal = hal_info->hal_com;
u32 value;
u8 path_nums;
if (hal->rfpath_tx_num > hal->rfpath_rx_num)
path_nums = hal->rfpath_tx_num;
else
path_nums = hal->rfpath_rx_num;
RTW_PRINT_SEL(sel, "======= RF REG =======\n");
for (path = 0; path < path_nums; path++) {
RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path);
for (i = 0; i < 0x100; i++) {
value = rtw_hal_read_rfreg(hal_info, path, i, 0xfffff);
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%02x ", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", value);
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
j = 1;
#ifdef CONFIG_RTL8852B
for (i = 0x10000; i < 0x10100; i++) {
value = rtw_hal_read_rfreg(hal_info, path, i, 0xfffff);
if (j % 4 == 1)
RTW_PRINT_SEL(sel, "0x%02x ", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", value);
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
_RTW_PRINT_SEL(sel, "\n");
#endif
}
#endif/*RTW_WKARD_RF_CR_DUMP*/
}
#endif
/**
* rtw_hal_get_sec_cam() - get the security cam raw data from HW
* @h: struct hal_info_t *
* @num: How many cam you wnat to dump from the first one.
* @buf: ptr to buffer which store the content from HW.
* If buf is NULL, use console as debug path.
* @size Size of allocated memroy for @buf.
* The size should be @num * size of security cam offset(0x20).
*
* Return rtw_hal_mac_get_addr_cam's return value in enum rtw_hal_status type.
*/
enum rtw_hal_status
rtw_hal_get_sec_cam(void *h, u16 num, u8 *buf, u16 size)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
ret = rtw_hal_mac_get_sec_cam(hal_info, num, buf, size);
return ret;
}
/**
* rtw_hal_get_addr_cam() - get the address cam raw data from HW
* @h: struct hal_info_t *
* @num: How many cam you wnat to dump from the first one.
* @buf: ptr to buffer which store the content from HW.
* If buf is NULL, use console as debug path.
* @size Size of allocated memroy for @buf.
* The size should be @num * size of Addr cam offset(0x40).
*
* Return rtw_hal_mac_get_addr_cam's return value in enum rtw_hal_status type.
*/
enum rtw_hal_status
rtw_hal_get_addr_cam(void *h, u16 num, u8 *buf, u16 size)
{
struct hal_info_t *hal_info = (struct hal_info_t *)h;
enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
ret = rtw_hal_mac_get_addr_cam(hal_info, num, buf, size);
return ret;
}
void rtw_hal_enable_interrupt(struct rtw_phl_com_t *phl_com, void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->enable_interrupt)
hal_ops->enable_interrupt(hal);
}
void rtw_hal_disable_interrupt(struct rtw_phl_com_t *phl_com, void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->disable_interrupt)
hal_ops->disable_interrupt(hal);
}
void rtw_hal_config_interrupt(void *h, enum rtw_phl_config_int int_mode)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->config_interrupt)
hal_ops->config_interrupt(hal, int_mode);
}
bool rtw_hal_recognize_interrupt(void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->recognize_interrupt)
return hal_ops->recognize_interrupt(hal);
else
return false;
}
bool rtw_hal_recognize_halt_c2h_interrupt(void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->recognize_halt_c2h_interrupt)
return hal_ops->recognize_halt_c2h_interrupt(hal);
else
return false;
}
void rtw_hal_clear_interrupt(void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->clear_interrupt)
hal_ops->clear_interrupt(hal);
}
u32 rtw_hal_interrupt_handler(void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
u32 ret = 0;
if (hal_ops->interrupt_handler)
ret = hal_ops->interrupt_handler(hal);
else
PHL_DBG("hal_ops->interrupt_handler is NULL\n");
PHL_DBG("hal_ops->interrupt_handler ret=0x%x\n", ret);
return ret;
}
void rtw_hal_restore_interrupt(struct rtw_phl_com_t *phl_com, void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->restore_interrupt)
hal_ops->restore_interrupt(hal);
}
void rtw_hal_restore_rx_interrupt(void *h)
{
struct hal_info_t *hal = (struct hal_info_t *)h;
struct hal_ops_t *hal_ops = hal_get_ops(hal);
if (hal_ops->restore_rx_interrupt)
hal_ops->restore_rx_interrupt(hal);
else
PHL_DBG("hal_ops->restore_rx_interrupt is NULL\n");
}
static enum rtw_hal_status hal_ops_check(struct hal_info_t *hal)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct hal_ops_t *ops = hal_get_ops(hal);
struct hal_trx_ops *trx_ops = hal_get_trx_ops(hal);
/***hal_ops initialize section ***/
if (!ops->init_hal_spec) {
hal_error_msg("init_hal_spec");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->read_chip_version) {
hal_error_msg("read_chip_version");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_init) {
hal_error_msg("hal_init");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_deinit) {
hal_error_msg("hal_deinit");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_start) {
hal_error_msg("hal_start");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_stop) {
hal_error_msg("hal_stop");
status = RTW_HAL_STATUS_FAILURE;
}
#ifdef CONFIG_WOWLAN
if (!ops->hal_wow_init) {
hal_error_msg("hal_wow_init");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_wow_deinit) {
hal_error_msg("hal_wow_deinit");
status = RTW_HAL_STATUS_FAILURE;
}
#endif /* CONFIG_WOWLAN */
if (!ops->hal_mp_init) {
hal_error_msg("hal_mp_init");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_mp_deinit) {
hal_error_msg("hal_mp_deinit");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_cfg_fw) {
hal_error_msg("hal_cfg_fw");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->init_default_value) {
hal_error_msg("init_default_value");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->hal_hci_configure) {
hal_error_msg("hal_hci_configure");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->read_macreg) {
hal_error_msg("read_macreg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->write_macreg) {
hal_error_msg("write_macreg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->read_bbreg) {
hal_error_msg("read_bbreg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->write_bbreg) {
hal_error_msg("write_bbreg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->read_rfreg) {
hal_error_msg("read_rfreg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->write_rfreg) {
hal_error_msg("write_rfreg");
status = RTW_HAL_STATUS_FAILURE;
}
#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)
if (!ops->enable_interrupt) {
hal_error_msg("enable_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->disable_interrupt) {
hal_error_msg("disable_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
#ifdef CONFIG_SDIO_HCI
if (!ops->config_interrupt) {
hal_error_msg("config_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->recognize_halt_c2h_interrupt) {
hal_error_msg("recognize_halt_c2h_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
#endif
if (!ops->recognize_interrupt) {
hal_error_msg("recognize_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->clear_interrupt) {
hal_error_msg("clear_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->interrupt_handler) {
hal_error_msg("interrupt_handler");
status = RTW_HAL_STATUS_FAILURE;
}
if (!ops->restore_interrupt) {
hal_error_msg("restore_interrupt");
status = RTW_HAL_STATUS_FAILURE;
}
#endif /*defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)*/
/***hal_trx_ops section ***/
if (!trx_ops->init) {
hal_error_msg("trx init");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->deinit) {
hal_error_msg("trx deinit");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->map_hw_tx_chnl) {
hal_error_msg("trx map_hw_tx_chnl");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->get_fwcmd_queue_idx) {
hal_error_msg("trx get_fwcmd_queue_idx");
status = RTW_HAL_STATUS_FAILURE;
}
#ifdef CONFIG_PCI_HCI
if (!trx_ops->query_tx_res) {
hal_error_msg("trx query_tx_res");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->query_rx_res) {
hal_error_msg("trx query_rx_res");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->cfg_wow_txdma) {
hal_error_msg("trx cfg_wow_txdma");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->poll_txdma_idle) {
hal_error_msg("trx poll_txdma_idle");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->qsel_to_tid) {
hal_error_msg("trx qsel_to_tid");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->query_txch_num) {
hal_error_msg("trx query_txch_num");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->query_rxch_num) {
hal_error_msg("trx query_rxch_num");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->update_wd) {
hal_error_msg("trx update_wd");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->update_txbd) {
hal_error_msg("trx update_txbd");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->tx_start) {
hal_error_msg("trx tx_start");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->check_rxrdy) {
hal_error_msg("trx check_rxrdy");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->handle_rxbd_info) {
hal_error_msg("trx handle_rxbd_info");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->handle_rx_buffer) {
hal_error_msg("trx handle_rx_buffer");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->update_rxbd) {
hal_error_msg("trx update_rxbd");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->notify_rxdone) {
hal_error_msg("trx notify_rxdone");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->handle_wp_rpt) {
hal_error_msg("trx handle_wp_rpt");
status = RTW_HAL_STATUS_FAILURE;
}
#endif /*CONFIG_PCIE_HCI*/
#ifdef CONFIG_USB_HCI
if (!trx_ops->hal_fill_wd) {
hal_error_msg("trx hal_fill_wd");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->get_bulkout_id) {
hal_error_msg("trx get_bulkout_id");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->handle_rx_buffer) {
hal_error_msg("trx handle_rx_buffer");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->usb_tx_agg_cfg) {
hal_error_msg("trx usb_tx_agg_cfg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->usb_rx_agg_cfg) {
hal_error_msg("trx usb_rx_agg_cfg");
status = RTW_HAL_STATUS_FAILURE;
}
if (!trx_ops->handle_wp_rpt) {
hal_error_msg("trx handle_wp_rpt");
status = RTW_HAL_STATUS_FAILURE;
}
#endif
#ifdef CONFIG_SDIO_HCI
#endif
return status;
}
static enum rtw_hal_status hal_set_ops(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
#ifdef CONFIG_PCI_HCI
if (phl_get_hci_type(phl_com) == RTW_HCI_PCIE)
hal_set_ops_pci(phl_com, hal_info);
#endif
#ifdef CONFIG_USB_HCI
if (phl_get_hci_type(phl_com) == RTW_HCI_USB)
hal_set_ops_usb(phl_com, hal_info);
#endif
#ifdef CONFIG_SDIO_HCI
if (phl_get_hci_type(phl_com) == RTW_HCI_SDIO)
hal_set_ops_sdio(phl_com, hal_info);
#endif
return hal_ops_check(hal_info);
}
#ifdef RTW_PHL_BCN
enum rtw_hal_status hal_bcn_init(struct hal_info_t *hal_info)
{
struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
hal_info->hal_com->bcn_pool.bcn_num = 0;
INIT_LIST_HEAD(&bcn_pool->bcn_list);
_os_spinlock_init(hal_to_drvpriv(hal_info), &hal_info->hal_com->bcn_pool.bcn_lock);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status hal_bcn_deinit(struct hal_info_t *hal_info)
{
void *drv_priv = hal_to_drvpriv(hal_info);
struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
struct rtw_bcn_entry *tmp_entry, *type = NULL;
_os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
phl_list_for_loop_safe(tmp_entry, type,
struct rtw_bcn_entry, &bcn_pool->bcn_list, list)
{
list_del(&tmp_entry->list);
_os_mem_free(drv_priv, tmp_entry, sizeof(struct rtw_bcn_entry));
}
_os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status hal_alloc_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
struct rtw_bcn_entry **bcn_entry, struct rtw_bcn_info_cmn *bcn_cmn)
{
void *drv_priv = hal_to_drvpriv(hal_info);
struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
struct rtw_bcn_entry *new_entry = _os_mem_alloc(drv_priv, sizeof(struct rtw_bcn_entry));
if(new_entry == NULL)
return RTW_HAL_STATUS_FAILURE;
_os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
list_add_tail(&new_entry->list, &bcn_pool->bcn_list);
bcn_pool->bcn_num ++;
_os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
*bcn_entry = new_entry;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status hal_free_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
u8 bcn_id)
{
void *drv_priv = hal_to_drvpriv(hal_info);
struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
struct rtw_bcn_entry *tmp_entry, *type = NULL;
u8 is_found = 0;
_os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
phl_list_for_loop_safe(tmp_entry, type,
struct rtw_bcn_entry, &bcn_pool->bcn_list, list)
{
if(tmp_entry->bcn_cmn->bcn_id == bcn_id){
is_found = 1;
break;
}
}
_os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
if(is_found){
list_del(&tmp_entry->list);
_os_mem_free(drv_priv, tmp_entry, sizeof(struct rtw_bcn_entry));
bcn_pool->bcn_num --;
return RTW_HAL_STATUS_SUCCESS;
}
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status hal_get_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
struct rtw_bcn_entry **bcn_entry, u8 bcn_id)
{
void *drv_priv = hal_to_drvpriv(hal_info);
struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
struct rtw_bcn_entry *tmp_entry, *type = NULL;
u8 is_found = 0;
_os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
phl_list_for_loop_safe(tmp_entry, type,
struct rtw_bcn_entry, &bcn_pool->bcn_list, list)
{
if(tmp_entry->bcn_cmn->bcn_id == bcn_id){
is_found = 1;
break;
}
}
_os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
if(is_found){
*bcn_entry = tmp_entry;
return RTW_HAL_STATUS_SUCCESS;
}
else
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status hal_update_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
struct rtw_bcn_entry *bcn_entry, struct rtw_bcn_info_cmn *bcn_cmn)
{
struct rtw_wifi_role_t *wrole = &phl_com->wifi_roles[bcn_cmn->role_idx];
struct rtw_phl_stainfo_t *phl_sta = rtw_phl_get_stainfo_self(phl_com->phl_priv, wrole);
bcn_entry->bcn_cmn = bcn_cmn;
bcn_entry->bcn_hw.band = wrole->hw_band;
bcn_entry->bcn_hw.port = wrole->hw_port;
bcn_entry->bcn_hw.mbssid = wrole->hw_mbssid;
bcn_entry->bcn_hw.mac_id = (u8)phl_sta->macid;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_add_beacon(struct rtw_phl_com_t *phl_com, void *hal,
void *bcn_cmn)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
struct rtw_bcn_entry *bcn_entry = NULL;
if(hal_alloc_bcn_entry(phl_com, hal_info, &bcn_entry, (struct rtw_bcn_info_cmn *)bcn_cmn) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
if(hal_update_bcn_entry(phl_com, hal_info, bcn_entry, (struct rtw_bcn_info_cmn *)bcn_cmn) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
if(hal_ops->cfg_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
if(hal_ops->upt_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_update_beacon(struct rtw_phl_com_t *phl_com, void *hal,
u8 bcn_id)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
struct rtw_bcn_entry *bcn_entry = NULL;
if(hal_get_bcn_entry(phl_com, hal_info, &bcn_entry, bcn_id) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
if(hal_ops->upt_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status rtw_hal_free_beacon(struct rtw_phl_com_t *phl_com, void *hal,
u8 bcn_id)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
if(hal_free_bcn_entry(phl_com, hal_info, bcn_id) == RTW_HAL_STATUS_FAILURE)
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
#endif
enum rtw_hal_status rtw_hal_pkt_ofld(void *hal, u8 *id, u8 op,
u8 *pkt_buf, u16 *pkt_len)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
return hal_ops->pkt_ofld(hal, id, op, pkt_buf, pkt_len);
}
enum rtw_hal_status rtw_hal_pkt_update_ids(void *hal,
struct pkt_ofld_entry *entry)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
return hal_ops->pkt_update_ids(hal, entry);
}
enum rtw_hal_status rtw_hal_get_pwr_state(void *hal, enum rtw_mac_pwr_st *pwr_state)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_get_pwr_state(hal_info, pwr_state);
}
enum rtw_hal_status rtw_hal_init(void *drv_priv,
struct rtw_phl_com_t *phl_com, void **hal, enum rtl_ic_id ic_id)
{
struct hal_info_t *hal_info = NULL;
struct rtw_hal_com_t *hal_com = NULL;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops) = NULL;
enum rtw_chip_id chip_id = CHIP_WIFI6_MAX;
if (ic_id == RTL8852A)
chip_id = CHIP_WIFI6_8852A;
else if(ic_id == RTL8834A)
chip_id = CHIP_WIFI6_8834A;
else if(ic_id == RTL8852B)
chip_id = CHIP_WIFI6_8852B;
else if(ic_id == RTL8852C)
chip_id = CHIP_WIFI6_8852C;
else
return RTW_HAL_STATUS_FAILURE;
hal_info = _os_mem_alloc(drv_priv, sizeof(struct hal_info_t));
if (hal_info == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("alloc hal_info failed\n");
goto error_hal_mem;
}
*hal = hal_info;
hal_com = _os_mem_alloc(drv_priv, sizeof(struct rtw_hal_com_t));
if (hal_com == NULL) {
hal_status = RTW_HAL_STATUS_RESOURCE;
PHL_ERR("alloc hal_com failed\n");
goto error_hal_com_mem;
}
hal_info->hal_com = hal_com;
hal_com->drv_priv = drv_priv;
hal_com->hal_priv = hal_info;
hal_com->chip_id = chip_id;
hal_com->dbcc_en = false;
#ifdef DBG_HAL_MEM_MOINTOR
_os_atomic_set(drv_priv, &(hal_com->hal_mem), 0);
#endif
/*set io_ops*/
#ifdef CONFIG_PCI_HCI
if (phl_com->hci_type == RTW_HCI_PCIE)
set_intf_ops = hal_pci_set_io_ops;
#endif
#ifdef CONFIG_USB_HCI
if (phl_com->hci_type == RTW_HCI_USB)
set_intf_ops = hal_usb_set_io_ops;
#endif
#ifdef CONFIG_SDIO_HCI
if (phl_com->hci_type == RTW_HCI_SDIO)
set_intf_ops = hal_sdio_set_io_ops;
#endif
hal_status = hal_init_io_priv(hal_info->hal_com, set_intf_ops);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("hal_init_io_priv failed\n");
goto error_io_priv;
}
/*set hal_ops and hal_hook_trx_ops*/
hal_status = hal_set_ops(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("hal_set_ops failed\n");
goto error_hal_ops;
}
hal_status = hal_info->hal_ops.hal_init(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("hal_ops.hal_init failed\n");
goto error_hal_init;
}
hal_status = rtw_hal_mac_init(phl_com, hal_info);
if ((hal_status != RTW_HAL_STATUS_SUCCESS) || (hal_info->mac == NULL)) {
PHL_ERR("rtw_hal_mac_init failed\n");
goto error_mac_init;
}
hal_status = rtw_hal_efuse_init(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_efuse_init failed\n");
goto error_efuse_init;
}
hal_status = rtw_hal_bb_init(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_bb_init failed\n");
goto error_bb_init;
}
hal_status = rtw_hal_rf_init(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_rf_init failed\n");
goto error_rf_init;
}
hal_status = rtw_hal_btc_init(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("rtw_hal_btc_init failed\n");
goto error_btc_init;
}
#ifdef RTW_PHL_BCN
hal_status = hal_bcn_init(hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("hal_bcn_init failed\n");
goto error_bcn_init;
}
#endif
return RTW_HAL_STATUS_SUCCESS;
#ifdef RTW_PHL_BCN
error_bcn_init:
rtw_hal_btc_deinit(phl_com, hal_info);
#endif
error_btc_init:
rtw_hal_rf_deinit(phl_com, hal_info);
error_rf_init:
rtw_hal_bb_deinit(phl_com, hal_info);
error_bb_init:
rtw_hal_efuse_deinit(phl_com, hal_info);
error_efuse_init:
rtw_hal_mac_deinit(phl_com, hal_info);
error_mac_init:
hal_info->hal_ops.hal_deinit(phl_com, hal_info);
error_hal_init:
error_hal_ops:
hal_deinit_io_priv(hal_com);
error_io_priv:
if (hal_com) {
_os_mem_free(drv_priv, hal_com, sizeof(struct rtw_hal_com_t));
hal_com = NULL;
}
error_hal_com_mem:
if (hal_info) {
_os_mem_free(drv_priv, hal_info, sizeof(struct hal_info_t));
*hal = hal_info = NULL;
}
error_hal_mem:
return hal_status;
}
struct rtw_hal_com_t *rtw_hal_get_halcom(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return hal_info->hal_com;
}
void rtw_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
void *drv_priv = hal_to_drvpriv(hal_info);
if(hal_info == NULL)
return;
/* stop mechanism / disassociate hal ops */
#ifdef RTW_PHL_BCN
hal_bcn_deinit(hal_info);
#endif
rtw_hal_btc_deinit(phl_com, hal_info);
rtw_hal_rf_deinit(phl_com, hal_info);
rtw_hal_bb_deinit(phl_com, hal_info);
rtw_hal_efuse_deinit(phl_com, hal_info);
rtw_hal_mac_deinit(phl_com, hal_info);
hal_info->hal_ops.hal_deinit(phl_com, hal_info);
hal_deinit_io_priv(hal_info->hal_com);
#ifdef DBG_HAL_MEM_MOINTOR
PHL_INFO("[PHL-MEM] %s HAL memory :%d\n", __func__,
_os_atomic_read(hal_to_drvpriv(hal_info), &(hal_info->hal_com->hal_mem)));
#endif
if (hal_info->hal_com) {
if(hal_info->hal_com->bf_obj)
hal_bf_deinit(hal_info);
if(hal_info->hal_com->csi_obj)
hal_csi_deinit(hal_info);
if(hal_info->hal_com->snd_obj)
hal_snd_obj_deinit(hal_info);
_os_mem_free(drv_priv,
hal_info->hal_com, sizeof(struct rtw_hal_com_t));
hal_info->hal_com = NULL;
}
if (hal_info) {
_os_mem_free(drv_priv,
hal_info, sizeof(struct hal_info_t));
hal_info = NULL;
}
}
bool rtw_hal_is_inited(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return hal_info->hal_com->is_hal_init;
}
u32 rtw_hal_hci_cfg(struct rtw_phl_com_t *phl_com, void *hal,
struct rtw_ic_info *ic_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
#ifdef CONFIG_SDIO_HCI
hal_info->hal_com->block_sz = ic_info->sdio_info.block_sz;
#endif
hal_ops->hal_hci_configure(phl_com, hal_info, ic_info);
return hal_status;
}
u32 rtw_hal_read_chip_info(struct rtw_phl_com_t *phl_com, void *hal)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
hal_ops->read_chip_version(phl_com, hal_info);
/*get mac,bb,rf capability*/
hal_ops->init_hal_spec(phl_com, hal_info);
return hal_status;
}
static void _hal_reset_chandef(struct rtw_hal_com_t *hal_com)
{
struct rtw_chan_def *chandef = NULL;
u8 bid = 0;
for (bid = 0; bid < HW_BAND_MAX; bid++) {
chandef = &(hal_com->band[bid].cur_chandef);
chandef->bw = CHANNEL_WIDTH_MAX;
chandef->chan = 0;
chandef->offset = CHAN_OFFSET_NO_EXT;
}
}
void rtw_hal_set_default_var(void *hal, enum rtw_hal_set_def_var_rsn rsn)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
struct hal_intr_mask_cfg intr_cfg = {0};
switch (rsn) {
case SET_DEF_RSN_HAL_INIT:
intr_cfg.halt_c2h_en = 1;
intr_cfg.wdt_en = 1;
hal_info->hal_com->assoc_sta_cnt = 0;
_hal_reset_chandef(hal_info->hal_com);
break;
case SET_DEF_RSN_WOW_RESUME_HNDL_RX:
intr_cfg.halt_c2h_en = 0;
intr_cfg.wdt_en = 1;
break;
case SET_DEF_RSN_WOW_RESUME_DONE:
intr_cfg.halt_c2h_en = 1;
intr_cfg.wdt_en = 1;
break;
default:
intr_cfg.halt_c2h_en = 1;
intr_cfg.wdt_en = 1;
hal_info->hal_com->assoc_sta_cnt = 0;
_hal_reset_chandef(hal_info->hal_com);
break;
}
PHL_INFO("%s : rsn %d.\n", __func__, rsn);
hal_ops->init_default_value(hal_info, &intr_cfg);
}
u32 rtw_hal_var_init(struct rtw_phl_com_t *phl_com, void *hal)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
hal_com->is_hal_init = false;
rtw_hal_set_default_var(hal_info, SET_DEF_RSN_HAL_INIT);
/*csi init shall after read hw chip info*/
hal_status = hal_csi_init(
hal_info,
phl_com->hal_spec.max_csi_buf_su_nr,
phl_com->hal_spec.max_csi_buf_mu_nr);
if (hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("rtw_hal_csi_init failed\n");
}
/*bf init shall after read hw chip info*/
hal_status = hal_bf_init(
hal_info,
phl_com->hal_spec.max_bf_ent_nr,
phl_com->hal_spec.max_su_sta_nr,
phl_com->hal_spec.max_mu_sta_nr);
if (hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("rtw_hal_bf_init failed\n");
}
hal_status = hal_snd_obj_init(hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("hal_snd_obj_init failed\n");
}
return hal_status;
}
static int
_hal_parse_macreg(void *drv_priv, u32 *pdest_buf, u8 *psrc_buf, u32 buflen)
{
return 0;
}
enum rf_path _get_path_from_ant_num(u8 antnum)
{
enum rf_path ret = RF_PATH_B;
switch (antnum) {
default:
break;
case 1:
ret = RF_PATH_B;
break;
case 2:
ret = RF_PATH_AB;
break;
case 3:
ret = RF_PATH_ABC;
break;
}
return ret;
}
static void _hal_send_hal_init_hub_msg(struct rtw_phl_com_t *phl_com, u8 init_ok)
{
struct phl_msg msg = {0};
u16 evt_id = (init_ok) ? MSG_EVT_HAL_INIT_OK : MSG_EVT_HAL_INIT_FAIL;
msg.inbuf = NULL;
msg.inlen = 0;
SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT);
SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id);
msg.band_idx = HW_BAND_0;
rtw_phl_msg_hub_hal_send(phl_com, NULL, &msg);
}
enum rtw_hal_status rtw_hal_preload(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
FUNCIN();
hal_status = hal_ops->hal_get_efuse(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
return hal_status;
}
enum rtw_hal_status hal_rfe_type_chk(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_UNKNOWN_RFE_TYPE;
if(phl_com->dev_cap.rfe_type != 0xff){
hal_status = RTW_HAL_STATUS_SUCCESS;
}
else {
if(phl_com->dev_cap.bypass_rfe_chk == true){
rtw_hal_rf_get_default_rfe_type(hal_info->hal_com);
rtw_hal_rf_get_default_xtal(hal_info->hal_com);
PHL_WARN("%s: Use default RFE type(0x%x) / XTAL(0x%x) configuration for empty EFUSE\n",
__FUNCTION__,
hal_info->hal_com->dev_hw_cap.rfe_type,
hal_info->hal_com->dev_hw_cap.xcap);
hal_status = RTW_HAL_STATUS_SUCCESS;
}
}
return hal_status;
}
enum rtw_hal_status rtw_hal_start(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
enum rf_path tx, rx;
#endif
hal_status = hal_rfe_type_chk(phl_com, hal_info);
if(hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_ERR("%s: Unknown RFE type!!!\n", __FUNCTION__);
return hal_status;
}
hal_status = hal_ops->hal_start(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
hal_status = RTW_HAL_STATUS_SUCCESS;
hal_info->hal_com->is_hal_init = true;
rtw_hal_set_default_var(hal_info, SET_DEF_RSN_HAL_INIT);
rtw_hal_rf_set_power(hal_info, HW_PHY_0, PWR_BY_RATE);
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
if (phl_com->phy_cap[0].txss < hal_info->hal_com->rfpath_tx_num)
hal_info->hal_com->rfpath_tx_num = phl_com->phy_cap[0].txss;
if (phl_com->phy_cap[0].rxss < hal_info->hal_com->rfpath_rx_num)
hal_info->hal_com->rfpath_rx_num = phl_com->phy_cap[0].rxss;
tx = _get_path_from_ant_num(hal_info->hal_com->rfpath_tx_num);
rx = _get_path_from_ant_num(hal_info->hal_com->rfpath_rx_num);
rtw_hal_bb_trx_path_cfg(hal_info, tx, phl_com->phy_cap[0].txss,
rx, phl_com->phy_cap[0].rxss);
#endif
#ifdef RTW_WKARD_SINGLE_PATH_RSSI
hal_info->hal_com->cur_rx_rfpath =
_get_path_from_ant_num(hal_info->hal_com->rfpath_rx_num);
#endif
#ifdef CONFIG_BTCOEX
rtw_hal_btc_radio_state_ntfy(hal_info, true);
#endif
return hal_status;
}
void rtw_hal_stop(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
do {
if (true == TEST_STATUS_FLAG(phl_com->dev_state,
RTW_DEV_SURPRISE_REMOVAL)) {
PHL_WARN("%s(): Device has removed, skip HW stop functions!\n", __func__);
break;
}
#ifdef CONFIG_BTCOEX
rtw_hal_btc_radio_state_ntfy(hal_info, false);
#endif
hal_status = hal_ops->hal_stop(phl_com, hal_info);
hal_info->hal_com->is_hal_init = false;
} while (false);
}
enum rtw_hal_status rtw_hal_restart(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
#ifdef CONFIG_BTCOEX
rtw_hal_btc_radio_state_ntfy(hal_info, false);
#endif
hal_status = hal_ops->hal_stop(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
hal_status = hal_ops->hal_start(phl_com, hal_info);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
return hal_status;
#ifdef CONFIG_BTCOEX
rtw_hal_btc_radio_state_ntfy(hal_info, true);
#endif
hal_info->hal_com->is_hal_init = true;
return hal_status;
}
enum rtw_hal_status rtw_hal_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
hstatus = rtw_hal_mac_hal_deinit(phl_com, hal_info);
return hstatus;
}
enum rtw_hal_status
rtw_hal_role_cfg(void *hal, struct rtw_wifi_role_t *wrole)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
/*enable & configure mac hw-port*/
hal_status = rtw_hal_mac_port_init(hal_info, wrole);
/* init hal mac bfer function if wrole cap if any of bfer cap is true*/
if (wrole->proto_role_cap.he_su_bfmr ||
wrole->proto_role_cap.he_mu_bfmr ||
wrole->proto_role_cap.vht_su_bfmr ||
wrole->proto_role_cap.vht_mu_bfmr ||
wrole->proto_role_cap.ht_su_bfmr) {
if ((PHL_RTYPE_AP == wrole->type) ||
((PHL_RTYPE_STATION == wrole->type) &&
(MLME_LINKED == wrole->mstate))) {
hal_status = hal_bf_hw_mac_init_bfer(hal_info,
wrole->hw_band);
}
}
return hal_status;
}
enum rtw_hal_status
rtw_hal_role_cfg_ex(void *hal, struct rtw_wifi_role_t *wrole,
enum pcfg_type type, void *param)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_port_cfg(hal_info, wrole, type, param);
return hal_status;
}
enum rtw_hal_status
rtw_hal_beacon_stop(void *hal, struct rtw_wifi_role_t *wrole, bool stop)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
u32 bcn_en = (stop) ? 0 : 1;
PHL_INFO("%s wr-%d, bcn_en:%s\n", __func__, wrole->id, (bcn_en) ? "E" : "D");
hsts = rtw_hal_mac_port_cfg(hal_info, wrole, PCFG_BCN_EN, &bcn_en);
return hsts;
}
enum rtw_hal_status
hal_ver_check(struct rtw_hal_com_t *hal_com)
{
if ((hal_com->mac_vc.mac_ver < hal_com->bb_vc.mac_ver) ||
(hal_com->mac_vc.mac_ver < hal_com->rf_vc.mac_ver) ||
(hal_com->mac_vc.mac_ver < hal_com->btc_vc.mac_ver) ||
(hal_com->mac_vc.mac_ver < hal_com->fw_vc.mac_ver))
return RTW_HAL_STATUS_FAILURE;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_watchdog(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_bb_watchdog(hal_info, false);
if(hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_INFO("%s fail (%x)\n",
__FUNCTION__, hal_status);
goto exit;
}
hal_status = rtw_hal_rf_watchdog(hal_info);
if(hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_INFO("%s fail (%x)\n",
__FUNCTION__, hal_status);
goto exit;
}
exit:
return hal_status;
}
enum rtw_hal_status
rtw_hal_simple_watchdog(void *hal, u8 io_en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_bb_simple_watchdog(hal_info, io_en);
if(hal_status != RTW_HAL_STATUS_SUCCESS){
PHL_INFO("%s fail (%x)\n",
__FUNCTION__, hal_status);
goto exit;
}
exit:
return hal_status;
}
enum rtw_hal_status
rtw_hal_cfg_trx_path(void *hal, enum rf_path tx, u8 tx_nss,
enum rf_path rx, u8 rx_nss)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
if (tx < RF_PATH_AB) {
/* forced tx nss = 1*/
tx_nss = 1;
}
if (rx < RF_PATH_AB) {
/* forced rx nss = 1*/
rx_nss = 1;
}
hal_status = rtw_hal_bb_trx_path_cfg(
hal_info,
tx,
((tx_nss > hal_info->hal_com->rfpath_tx_num) ?
hal_info->hal_com->rfpath_tx_num : tx_nss),
rx,
((rx_nss > hal_info->hal_com->rfpath_rx_num) ?
hal_info->hal_com->rfpath_rx_num : rx_nss));
#ifdef RTW_WKARD_SINGLE_PATH_RSSI
hal_info->hal_com->cur_rx_rfpath = rx;
#endif
return hal_status;
}
enum rtw_hal_status rtw_hal_set_sw_gpio_mode(struct rtw_phl_com_t *phl_com, void *hal, enum rtw_gpio_mode mode, u8 gpio)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_set_sw_gpio_mode(hal_info, mode, gpio);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
return hal_status;
}
enum rtw_hal_status rtw_hal_sw_gpio_ctrl(struct rtw_phl_com_t *phl_com, void *hal, u8 high, u8 gpio)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
hal_status = rtw_hal_mac_sw_gpio_ctrl(hal_info, high, gpio);
PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
return hal_status;
}
void rtw_hal_dbg_status_dump(void *hal, struct hal_mac_dbg_dump_cfg *cfg)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
rtw_hal_mac_dbg_status_dump(hal_info, cfg);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_init.c
|
C
|
agpl-3.0
| 41,726
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*
The purpose of hal_io.c
a. provides the API
b. provides the protocol engine
c. provides the software interface between caller and the hardware interface
Compiler Flag Option:
1. CONFIG_SDIO_HCI:
a. USE_SYNC_IRP: Only sync operations are provided.
b. USE_ASYNC_IRP:Both sync/async operations are provided.
2. CONFIG_USB_HCI:
a. USE_ASYNC_IRP: Both sync/async operations are provided.
3. CONFIG_CFIO_HCI:
b. USE_SYNC_IRP: Only sync operations are provided.
Only sync read/rtw_write_mem operations are provided.
*/
#define _HAL_IO_C_
#include "hal_headers.h"
u8 _hal_read8(struct rtw_hal_com_t *hal, u32 addr)
{
u8 r_val;
struct hal_io_priv *io_priv = &hal->iopriv;
u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr);
#ifdef DBG_PHL_MAC_REG_RW
if (rtw_hal_mac_reg_chk(hal, addr) == false) {
r_val = 0xEA;
return r_val;
}
#endif
_read8 = io_priv->io_ops._read8;
r_val = _read8(hal, addr);
return r_val;
}
u16 _hal_read16(struct rtw_hal_com_t *hal, u32 addr)
{
u16 r_val;
struct hal_io_priv *io_priv = &hal->iopriv;
u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr);
#ifdef DBG_PHL_MAC_REG_RW
if (rtw_hal_mac_reg_chk(hal, addr) == false) {
r_val = 0xEAEA;
return r_val;
}
#endif
_read16 = io_priv->io_ops._read16;
r_val = _read16(hal, addr);
return r_val;
}
u32 _hal_read32(struct rtw_hal_com_t *hal, u32 addr)
{
u32 r_val;
struct hal_io_priv *io_priv = &hal->iopriv;
u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr);
#ifdef DBG_PHL_MAC_REG_RW
if (rtw_hal_mac_reg_chk(hal, addr) == false) {
r_val = 0xEAEAEAEA;
return r_val;
}
#endif
_read32 = io_priv->io_ops._read32;
r_val = _read32(hal, addr);
return r_val;
}
int _hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
{
struct hal_io_priv *io_priv = &hal->iopriv;
int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
#ifdef RTW_WKARD_BUS_WRITE
int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr,
u32 value) = NULL;
#endif
int ret;
#ifdef DBG_PHL_MAC_REG_RW
if (rtw_hal_mac_reg_chk(hal, addr) == false)
return 0;
#endif
_write8 = io_priv->io_ops._write8;
ret = _write8(hal, addr, val);
#ifdef RTW_WKARD_BUS_WRITE
_write_post_cfg = io_priv->io_ops._write_post_cfg;
if(NULL != _write_post_cfg) {
ret = _write_post_cfg(hal, addr, val);
}
#endif
return ret;
}
int _hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
{
struct hal_io_priv *io_priv = &hal->iopriv;
int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
#ifdef RTW_WKARD_BUS_WRITE
int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr,
u32 value) = NULL;
#endif
int ret;
#ifdef DBG_PHL_MAC_REG_RW
if (rtw_hal_mac_reg_chk(hal, addr) == false)
return 0;
#endif
_write16 = io_priv->io_ops._write16;
ret = _write16(hal, addr, val);
#ifdef RTW_WKARD_BUS_WRITE
_write_post_cfg = io_priv->io_ops._write_post_cfg;
if(NULL != _write_post_cfg) {
ret = _write_post_cfg(hal, addr, val);
}
#endif
return ret;
}
int _hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
{
struct hal_io_priv *io_priv = &hal->iopriv;
int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
#ifdef RTW_WKARD_BUS_WRITE
int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr,
u32 value) = NULL;
#endif
int ret;
#ifdef DBG_PHL_MAC_REG_RW
if (rtw_hal_mac_reg_chk(hal, addr) == false)
return 0;
#endif
_write32 = io_priv->io_ops._write32;
ret = _write32(hal, addr, val);
#ifdef RTW_WKARD_BUS_WRITE
_write_post_cfg = io_priv->io_ops._write_post_cfg;
if(NULL != _write_post_cfg) {
ret = _write_post_cfg(hal, addr, val);
}
#endif
return ret;
}
#ifdef CONFIG_SDIO_HCI
u8 _hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr)
{
u8 r_val = 0x00;
struct hal_io_priv *io_priv = &hal->iopriv;
u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr);
_sd_f0_read8 = io_priv->io_ops._sd_f0_read8;
if (_sd_f0_read8)
r_val = _sd_f0_read8(hal, addr);
return r_val;
}
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 _hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr)
{
u8 r_val = 0x00;
struct hal_io_priv *io_priv = &hal->iopriv;
u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr);
_sd_iread8 = io_priv->io_ops._sd_iread8;
if (_sd_iread8)
r_val = _sd_iread8(hal, addr);
return r_val;
}
u16 _hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr)
{
u16 r_val = 0x00;
struct hal_io_priv *io_priv = &hal->iopriv;
u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr);
_sd_iread16 = io_priv->io_ops._sd_iread16;
if (_sd_iread16)
r_val = _sd_iread16(hal, addr);
return r_val;
}
u32 _hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr)
{
u32 r_val = 0x00;
struct hal_io_priv *io_priv = &hal->iopriv;
u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr);
_sd_iread32 = io_priv->io_ops._sd_iread32;
if (_sd_iread32)
r_val = _sd_iread32(hal, addr);
return r_val;
}
int _hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
{
struct hal_io_priv *io_priv = &hal->iopriv;
int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
int ret = -1;
_sd_iwrite8 = io_priv->io_ops._sd_iwrite8;
if (_sd_iwrite8)
ret = _sd_iwrite8(hal, addr, val);
return ret;
}
int _hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
{
struct hal_io_priv *io_priv = &hal->iopriv;
int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
int ret = -1;
_sd_iwrite16 = io_priv->io_ops._sd_iwrite16;
if (_sd_iwrite16)
ret = _sd_iwrite16(hal, addr, val);
return ret;
}
int _hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
{
struct hal_io_priv *io_priv = &hal->iopriv;
int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
int ret = -1;
_sd_iwrite32 = io_priv->io_ops._sd_iwrite32;
if (_sd_iwrite32)
ret = _sd_iwrite32(hal, addr, val);
return ret;
}
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
u32 hal_init_io_priv(struct rtw_hal_com_t *hal,
void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops))
{
struct hal_io_priv *iopriv = &hal->iopriv;
if (set_intf_ops == NULL)
return RTW_HAL_STATUS_IO_INIT_FAILURE;
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
_os_mutex_init(hal->drv_priv, &iopriv->sd_indirect_access_mutex);
#endif
set_intf_ops(hal, &iopriv->io_ops);
return RTW_HAL_STATUS_SUCCESS;
}
u32 hal_deinit_io_priv(struct rtw_hal_com_t *hal)
{
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
struct hal_io_priv *iopriv = &hal->iopriv;
_os_mutex_init(hal->drv_priv, &iopriv->sd_indirect_access_mutex);
#endif
return RTW_HAL_STATUS_SUCCESS;
}
/*******************common IO APIs *******************/
static inline u32 _bit_shift(u32 mask)
{
u32 i;
for (i = 0; i <= 31; i++)
if (mask & BIT(i))
break;
return i;
}
u32 hal_read_macreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask)
{
u32 val = 0, val32, shift;
val32 = hal_read32(hal->hal_com, offset);
if (bit_mask != 0xFFFFFFFF) {
shift = _bit_shift(bit_mask);
val = (val32 & bit_mask) >> shift;
return val;
}
else {
return val32;
}
}
void hal_write_macreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask, u32 data)
{
u32 val32, shift;
if (bit_mask != 0xFFFFFFFF) {
val32 = hal_read32(hal->hal_com, offset);
shift = _bit_shift(bit_mask);
data = ((val32 & (~bit_mask)) | ((data << shift) & bit_mask));
}
hal_write32(hal->hal_com, offset, data);
}
u32 hal_read_bbreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask)
{
u32 val32 = 0;
val32 = rtw_hal_read_bb_reg(hal->hal_com, offset, bit_mask);
return val32;
}
void hal_write_bbreg(struct hal_info_t *hal,
u32 offset, u32 bit_mask, u32 data)
{
rtw_hal_write_bb_reg(hal->hal_com, offset, bit_mask, data);
}
u32 hal_read_rfreg(struct hal_info_t *hal,
enum rf_path path, u32 offset, u32 bit_mask)
{
u32 val32 = 0;
val32 = rtw_hal_read_rf_reg(hal->hal_com, path, offset, bit_mask);
#ifdef DBG_IO
if (match_rf_read_sniff_ranges(hal->hal_com, path, offset, bit_mask)) {
PHL_INFO("DBG_IO hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
, path, offset, bit_mask, (val32 << _bit_shift(bit_mask)), val32);
}
#endif
return val32;
}
void hal_write_rfreg(struct hal_info_t *hal,
enum rf_path path, u32 offset, u32 bit_mask, u32 data)
{
rtw_hal_write_rf_reg(hal->hal_com, path, offset, bit_mask, data);
#ifdef DBG_IO
if (match_rf_write_sniff_ranges(hal->hal_com, path, offset, bit_mask)) {
PHL_INFO("DBG_IO hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
, path, offset, bit_mask, (data << _bit_shift(bit_mask)), data);
}
#endif
}
static u32 _cal_bit_shift(u32 bit_mask)
{
u32 i;
for (i = 0; i <= 31; i++) {
if (((bit_mask >> i) & 0x1) == 1)
break;
}
return (i);
}
void hal_write32_mask(struct rtw_hal_com_t *hal, u16 addr, u32 mask, u32 val)
{
u32 original_value, new_value;
u32 bit_shift;
if (mask == 0xFFFFFFFF) {
hal_write32(hal, addr, val);
} else {
original_value = hal_read32(hal, addr);
bit_shift = _cal_bit_shift(mask);
new_value = (((original_value) & (~mask)) | ((val << bit_shift) & mask));
hal_write32(hal, addr, new_value);
}
}
#ifdef DBG_IO
#define RTW_IO_SNIFF_TYPE_RANGE 0 /* specific address range is accessed */
#define RTW_IO_SNIFF_TYPE_VALUE 1 /* value match for sniffed range */
struct rtw_io_sniff_ent {
u8 chip;
u8 hci;
u32 addr;
u8 type;
union {
u32 end_addr;
struct {
u32 mask;
u32 val;
bool equal;
} vm; /* value match */
} u;
bool trace;
char *tag;
};
#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \
{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \
{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
/* part or all sniffed range is enabled (not all 0) */
#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
/* part or all sniffed range is disabled (not all 1) */
#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
const struct rtw_io_sniff_ent read_sniff[] = {
#ifdef DBG_IO_HCI_EN_CHK
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
#endif
#ifdef DBG_IO_SNIFF_EXAMPLE
RTW_IO_SNIFF_RANGE_ENT(CHIP_WIFI6_MAX, 0, 0x522, 0x522, 0, "read TXPAUSE"),
RTW_IO_SNIFF_DIS_ENT(CHIP_WIFI6_MAX, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
#endif
};
const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent);
const struct rtw_io_sniff_ent write_sniff[] = {
#ifdef DBG_IO_HCI_EN_CHK
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
#endif
#ifdef DBG_IO_SNIFF_EXAMPLE
RTW_IO_SNIFF_RANGE_ENT(CHIP_WIFI6_MAX, 0, 0x522, 0x522, 0, "write TXPAUSE"),
RTW_IO_SNIFF_DIS_ENT(CHIP_WIFI6_MAX, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
#endif
};
const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent);
static bool match_io_sniff_ranges(struct rtw_hal_com_t *hal
, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len)
{
/* check if IO range after sniff end address */
if (addr > sniff->u.end_addr)
return 0;
return 1;
}
static bool match_io_sniff_value(struct rtw_hal_com_t *hal
, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
{
u8 sniff_len;
s8 mask_shift;
u32 mask;
s8 value_shift;
u32 value;
bool ret = 0;
/* check if IO range after sniff end address */
sniff_len = 4;
while (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) {
sniff_len--;
if (sniff_len == 0)
goto exit;
}
if (sniff->addr + sniff_len <= addr)
goto exit;
/* align to IO addr */
mask_shift = (sniff->addr - addr) * 8;
value_shift = mask_shift + bitshift(sniff->u.vm.mask);
if (mask_shift > 0)
mask = sniff->u.vm.mask << mask_shift;
else if (mask_shift < 0)
mask = sniff->u.vm.mask >> -mask_shift;
else
mask = sniff->u.vm.mask;
if (value_shift > 0)
value = sniff->u.vm.val << value_shift;
else if (mask_shift < 0)
value = sniff->u.vm.val >> -value_shift;
else
value = sniff->u.vm.val;
if ((sniff->u.vm.equal && (mask & val) == (mask & value))
|| (!sniff->u.vm.equal && (mask & val) != (mask & value))
) {
ret = 1;
if (0)
PHL_INFO(" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\n"
, addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal);
}
exit:
return ret;
}
static bool match_io_sniff(struct rtw_hal_com_t *hal
, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
{
bool ret = 0;
if (sniff->chip != CHIP_WIFI6_MAX
&& sniff->chip != hal_get_chip_id(hal))
goto exit;
/*
if (sniff->hci
&& !(sniff->hci & hal_get_hci_type(hal)))
goto exit;
*/
if (sniff->addr >= addr + len) /* IO range below sniff start address */
goto exit;
switch (sniff->type) {
case RTW_IO_SNIFF_TYPE_RANGE:
ret = match_io_sniff_ranges(hal, sniff, i, addr, len);
break;
case RTW_IO_SNIFF_TYPE_VALUE:
if (len == 1 || len == 2 || len == 4)
ret = match_io_sniff_value(hal, sniff, i, addr, len, val);
break;
default:
/*_os_warn_on(1);*/
break;
}
exit:
return ret;
}
u32 match_read_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val)
{
int i;
bool trace = 0;
u32 match = 0;
for (i = 0; i < read_sniff_num; i++) {
if (match_io_sniff(hal, &read_sniff[i], i, addr, len, val)) {
match++;
trace |= read_sniff[i].trace;
if (read_sniff[i].tag)
PHL_INFO("DBG_IO TAG %s\n", read_sniff[i].tag);
}
}
/*_os_warn_on(trace);*/
return match;
}
u32 match_write_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val)
{
int i;
bool trace = 0;
u32 match = 0;
for (i = 0; i < write_sniff_num; i++) {
if (match_io_sniff(hal, &write_sniff[i], i, addr, len, val)) {
match++;
trace |= write_sniff[i].trace;
if (write_sniff[i].tag)
PHL_INFO("DBG_IO TAG %s\n", write_sniff[i].tag);
}
}
/*_os_warn_on(trace);*/
return match;
}
struct rf_sniff_ent {
u8 path;
u16 reg;
u32 mask;
};
struct rf_sniff_ent rf_read_sniff_ranges[] = {
/* example for all path addr 0x55 with all RF Reg mask */
/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
};
struct rf_sniff_ent rf_write_sniff_ranges[] = {
/* example for all path addr 0x55 with all RF Reg mask */
/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
};
int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent);
int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent);
bool match_rf_read_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask)
{
int i;
for (i = 0; i < rf_read_sniff_num; i++) {
if (rf_read_sniff_ranges[i].path == MAX_RF_PATH ||
rf_read_sniff_ranges[i].path == path)
if ((addr == rf_read_sniff_ranges[i].reg) &&
(mask & rf_read_sniff_ranges[i].mask))
return true;
}
return false;
}
bool match_rf_write_sniff_ranges(struct rtw_hal_com_t *hal,
u8 path, u32 addr, u32 mask)
{
int i;
for (i = 0; i < rf_write_sniff_num; i++) {
if (rf_write_sniff_ranges[i].path == MAX_RF_PATH ||
rf_write_sniff_ranges[i].path == path)
if ((addr == rf_write_sniff_ranges[i].reg) &&
(mask & rf_write_sniff_ranges[i].mask))
return true;
}
return false;
}
u8 dbg_hal_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u8 val = _hal_read8(hal, addr);
if (match_read_sniff(hal, addr, 1, val)) {
PHL_INFO("DBG_IO %s:%d hal_read8(0x%04x) return 0x%02x\n"
, caller, line, addr, val);
}
return val;
}
u16 dbg_hal_read16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u16 val = _hal_read16(hal, addr);
if (match_read_sniff(hal, addr, 2, val)) {
PHL_INFO("DBG_IO %s:%d hal_read16(0x%04x) return 0x%04x\n"
, caller, line, addr, val);
}
return val;
}
u32 dbg_hal_read32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u32 val = _hal_read32(hal, addr);
if (match_read_sniff(hal, addr, 4, val)) {
PHL_INFO("DBG_IO %s:%d hal_read32(0x%04x) return 0x%08x\n"
, caller, line, addr, val);
}
return val;
}
int dbg_hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line)
{
if (match_write_sniff(hal, addr, 1, val)) {
PHL_INFO("DBG_IO %s:%d hal_write8(0x%04x, 0x%02x)\n"
, caller, line, addr, val);
}
return _hal_write8(hal, addr, val);
}
int dbg_hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line)
{
if (match_write_sniff(hal, addr, 2, val)) {
PHL_INFO("DBG_IO %s:%d hal_write16(0x%04x, 0x%04x)\n"
, caller, line, addr, val);
}
return _hal_write16(hal, addr, val);
}
int dbg_hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line)
{
if (match_write_sniff(hal, addr, 4, val)) {
PHL_INFO("DBG_IO %s:%d hal_write32(0x%04x, 0x%08x)\n"
, caller, line, addr, val);
}
return _hal_write32(hal, addr, val);
}
#ifdef CONFIG_SDIO_HCI
u8 dbg_hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u8 val = _hal_sd_f0_read8(hal, addr);
#if 0
if (match_read_sniff(adapter, addr, 1, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_f0_read8(0x%04x) return 0x%02x\n"
, caller, line, addr, val);
}
#endif
return val;
}
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 dbg_hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u8 val = hal_sd_iread8(hal, addr);
if (match_read_sniff(hal, addr, 1, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_iread8(0x%04x) return 0x%02x\n"
, caller, line, addr, val);
}
return val;
}
u16 dbg_hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u16 val = _hal_sd_iread16(hal, addr);
if (match_read_sniff(hal, addr, 2, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_iread16(0x%04x) return 0x%04x\n"
, caller, line, addr, val);
}
return val;
}
u32 dbg_hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
{
u32 val = _hal_sd_iread32(hal, addr);
if (match_read_sniff(hal, addr, 4, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_iread32(0x%04x) return 0x%08x\n"
, caller, line, addr, val);
}
return val;
}
int dbg_hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line)
{
if (match_write_sniff(hal, addr, 1, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_iwrite8(0x%04x, 0x%02x)\n"
, caller, line, addr, val);
}
return _hal_sd_iwrite8(hal, addr, val);
}
int dbg_hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line)
{
if (match_write_sniff(hal, addr, 2, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_iwrite16(0x%04x, 0x%04x)\n"
, caller, line, addr, val);
}
return _hal_sd_iwrite16(hal, addr, val);
}
int dbg_hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line)
{
if (match_write_sniff(hal, addr, 4, val)) {
PHL_INFO("DBG_IO %s:%d hal_sd_iwrite32(0x%04x, 0x%08x)\n"
, caller, line, addr, val);
}
return _hal_sd_iwrite32(hal, addr, val);
}
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_io.c
|
C
|
agpl-3.0
| 20,688
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_IO_H_
#define _HAL_IO_H_
/*
Below is the data structure used by _io_handler
*/
extern u8 _hal_read8(struct rtw_hal_com_t *hal, u32 addr);
extern u16 _hal_read16(struct rtw_hal_com_t *hal, u32 addr);
extern u32 _hal_read32(struct rtw_hal_com_t *hal, u32 addr);
extern void _hal_read_mem(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem);
extern int _hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val);
extern int _hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val);
extern int _hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val);
#ifdef CONFIG_SDIO_HCI
u8 _hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr);
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 _hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr);
u16 _hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr);
u32 _hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr);
int _hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val);
int _hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val);
int _hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val);
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#ifdef DBG_IO
u32 match_read_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val);
u32 match_write_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val);
bool match_rf_read_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask);
bool match_rf_write_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask);
extern u8 dbg_hal_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
extern u16 dbg_hal_read16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
extern u32 dbg_hal_read32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
extern int dbg_hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line);
extern int dbg_hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line);
extern int dbg_hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line);
extern int dbg_hal_writeN(struct rtw_hal_com_t *hal, u32 addr , u32 length , u8 *data, const char *caller, const int line);
#ifdef CONFIG_SDIO_HCI
u8 dbg_hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
u8 dbg_hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
u16 dbg_hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
u32 dbg_hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line);
int dbg_hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line);
int dbg_hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line);
int dbg_hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line);
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#define hal_read8(hal, addr) dbg_hal_read8((hal), (addr), __FUNCTION__, __LINE__)
#define hal_read16(hal, addr) dbg_hal_read16((hal), (addr), __FUNCTION__, __LINE__)
#define hal_read32(hal, addr) dbg_hal_read32((hal), (addr), __FUNCTION__, __LINE__)
#define hal_write8(hal, addr, val) dbg_hal_write8((hal), (addr), (val), __FUNCTION__, __LINE__)
#define hal_write16(hal, addr, val) dbg_hal_write16((hal), (addr), (val), __FUNCTION__, __LINE__)
#define hal_write32(hal, addr, val) dbg_hal_write32((hal), (addr), (val), __FUNCTION__, __LINE__)
#ifdef CONFIG_SDIO_HCI
#define hal_sd_f0_read8(hal, addr) dbg_hal_sd_f0_read8((hal), (addr), __func__, __LINE__)
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
#define hal_sd_iread8(hal, addr) dbg_hal_sd_iread8((hal), (addr), __func__, __LINE__)
#define hal_sd_iread16(hal, addr) dbg_hal_sd_iread16((hal), (addr), __func__, __LINE__)
#define hal_sd_iread32(hal, addr) dbg_hal_sd_iread32((hal), (addr), __func__, __LINE__)
#define hal_sd_iwrite8(hal, addr, val) dbg_hal_sd_iwrite8((hal), (addr), (val), __func__, __LINE__)
#define hal_sd_iwrite16(hal, addr, val) dbg_hal_sd_iwrite16((hal), (addr), (val), __func__, __LINE__)
#define hal_sd_iwrite32(hal, addr, val) dbg_hal_sd_iwrite32((hal), (addr), (val), __func__, __LINE__)
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#else /* DBG_IO */
#define hal_read8(hal, addr) _hal_read8((hal), (addr))
#define hal_read16(hal, addr) _hal_read16((hal), (addr))
#define hal_read32(hal, addr) _hal_read32((hal), (addr))
#define hal_write8(hal, addr, val) _hal_write8((hal), (addr), (val))
#define hal_write16(hal, addr, val) _hal_write16((hal), (addr), (val))
#define hal_write32(hal, addr, val) _hal_write32((hal), (addr), (val))
#ifdef CONFIG_SDIO_HCI
#define hal_sd_f0_read8(hal, addr) _hal_sd_f0_read8((hal), (addr))
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
#define hal_sd_iread8(hal, addr) _hal_sd_iread8((hal), (addr))
#define hal_sd_iread16(hal, addr) _hal_sd_iread16((hal), (addr))
#define hal_sd_iread32(hal, addr) _hal_sd_iread32((hal), (addr))
#define hal_sd_iwrite8(hal, addr, val) _hal_sd_iwrite8((hal), (addr), (val))
#define hal_sd_iwrite16(hal, addr, val) _hal_sd_iwrite16((hal), (addr), (val))
#define hal_sd_iwrite32(hal, addr, val) _hal_sd_iwrite32((hal), (addr), (val))
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#endif /* DBG_IO */
void hal_write32_mask(struct rtw_hal_com_t *hal, u16 addr, u32 mask, u32 val);
u32 hal_init_io_priv(struct rtw_hal_com_t *hal,
void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops));
u32 hal_deinit_io_priv(struct rtw_hal_com_t *hal);
#endif /* _RTW_IO_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_io.h
|
C
|
agpl-3.0
| 6,379
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_LD_FILE_C_
#include "hal_headers.h"
#include "hal_ld_file.h"
static int
_hal_parse_phyreg(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen)
{
struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t;
u32 *pdest_buf = para_info->para_data;
char *sz_line, *ptmp;
u32 dest_buf_idx = 0;
u32 u4bregoffset, u4bregvalue, u4bmove;
ptmp = (char *)psrc_buf;
for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) {
if (!hal_is_comment_string(sz_line)) {
/* Get 1st hex value as register offset. */
if (hal_get_hexvalue_fromstring(sz_line, &u4bregoffset, &u4bmove)) {
pdest_buf[dest_buf_idx] = u4bregoffset;
dest_buf_idx++;
if (u4bregoffset == 0xffff) {
/* Ending. */
pdest_buf[dest_buf_idx] = 0xffff;
PHL_INFO(" dest_buf_len: %d \n", dest_buf_idx);
break;
}
/* Get 2nd hex value as register value. */
sz_line += u4bmove;
if (hal_get_hexvalue_fromstring(sz_line, &u4bregvalue, &u4bmove)) {
/* PHL_INFO("[BB-ADDR]%03lX=%08lX\n", u4bregoffset, u4bregvalue); */
pdest_buf[dest_buf_idx] = u4bregvalue;
dest_buf_idx++;
}
}
}
}
#if 0
{ /*debug dump buf*/
u32 i = 0;
for (i = 0; i <= dest_buf_idx; i+=2)
PHL_INFO("[BB-ADDR] 0x%x :[0x%x]\n", pdest_buf[i], pdest_buf[i+1]);
}
#endif
return dest_buf_idx;
}
static u32 phypg_combvalue_fromstring( char *sz_line)
{
u32 u4bmove;
u32 combvalue = 0;
u8 integer = 0, fraction = 0;
u8 txgi_pdbm = 4;
if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove))
sz_line += u4bmove;
else
goto exit;
combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100));
if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove))
sz_line += u4bmove;
else
goto exit;
combvalue <<= 8;
combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100));
if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove))
sz_line += u4bmove;
else
goto exit;
combvalue <<= 8;
combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100));
if (hal_get_fractionvalue_fromstring(sz_line, &integer, &fraction, &u4bmove))
sz_line += u4bmove;
else
goto exit;
combvalue <<= 8;
combvalue |= ((integer * txgi_pdbm) + (fraction * txgi_pdbm / 100));
/*PHL_DBG("[combvalue 4] 0x%x , hex = %x\n", combvalue , integer);*/
exit:
return combvalue;
}
static int
_hal_parse_txpwr_by_rate(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen)
{
struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t;
u32 *pdest_buf = para_info->para_data;
char *sz_line, *ptmp;
u8 band = 0;
u8 phy_reg_pg_version = 0;
u8 phy_reg_pg_value_type = 0;
u32 pwrhexval = 0;
u32 line_idx = 0;
u32 buf_idx = 0;
bool firstline = true;
ptmp = (char*)psrc_buf;
for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) {
if (hal_is_allspace_tab(sz_line, sizeof(*sz_line)))
continue;
if (!hal_is_comment_string(sz_line)) {
if (firstline) {
if (_os_strncmp(sz_line, "#[v2]", 5) == 0
|| _os_strncmp(sz_line, "#[v3]", 5) == 0) {
phy_reg_pg_version = sz_line[3] - '0'; /* store pg version*/
PHL_INFO("phy_reg_pg_version %d\n", phy_reg_pg_version);
} else {
PHL_ERR("The format in PHY_REG_PG are invalid %s\n", sz_line);
goto exit;
}
if (_os_strncmp(sz_line + 5, "[Exact]#", 8) == 0) {
phy_reg_pg_value_type = 1; /* store PHY_REG_PG_EXACT_VALUE*/
firstline = false;
PHL_INFO("REG_PG_EXACT_VALUE\n");
continue;
} else {
PHL_ERR("The values in PHY_REG_PG are invalid %s\n", sz_line);
goto exit;
}
}
if (_os_strncmp(sz_line , "#[2.4G]#", 8) == 0) {
band = 0;
continue;
}
if (_os_strncmp(sz_line , "#[5G]#", 6) == 0) {
band = 1;
continue;
}
if ((_os_strncmp(sz_line , "#[START]#", 9) == 0) || (_os_strncmp(sz_line , "#[END]#", 9) == 0) ) {
continue;
}
if (_os_strncmp(sz_line , "[Nss1]", 6) == 0) {
line_idx = 0;
pwrhexval = 0;
pdest_buf[buf_idx++] = band;
pdest_buf[buf_idx++] = PHYPG_RF1Tx;
line_idx += 6;
PHL_INFO("[Line]%s , line_idx %d \n", sz_line, line_idx);
while (sz_line[line_idx] == ' ' || sz_line[line_idx] == '\0' || sz_line[line_idx] == '\t')
++line_idx;
sz_line += line_idx;
if (_os_strncmp(sz_line , "11M_1M", 6) == 0) {
pdest_buf[buf_idx++] = CCK_11M_1M;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "18M_6M", 6) == 0) {
pdest_buf[buf_idx++] = OFDM_18M_6M;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "54M_24M", 7) == 0) {
pdest_buf[buf_idx++] = OFDM_54M_24M;
sz_line += 7;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "MCS3_0", 6) == 0) {
pdest_buf[buf_idx++] = HE1SS_MCS3_0;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "MCS7_4", 6) == 0) {
pdest_buf[buf_idx++] = HE1SS_MCS7_4;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "MCS11_8", 6) == 0) {
pdest_buf[buf_idx++] = HE1SS_MCS11_8;
sz_line += 7;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "DCM4_0", 6) == 0) {
pdest_buf[buf_idx++] = HE1SS_DCM4_0;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
}
} else if (_os_strncmp(sz_line , "[Nss2]", 6) == 0) {
line_idx = 0;
pwrhexval = 0;
pdest_buf[buf_idx++] = band;
pdest_buf[buf_idx++] = PHYPG_RF2Tx;
PHL_INFO("[Line]%s , line_idx %d \n", sz_line, line_idx);
line_idx += 6;
while (sz_line[line_idx] == ' ' || sz_line[line_idx] == '\0' || sz_line[line_idx] == '\t')
++line_idx;
sz_line += line_idx;
if (_os_strncmp(sz_line , "MCS3_0", 6) == 0) {
pdest_buf[buf_idx++] = HE2SS_MCS3_0;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "MCS7_4", 6) == 0) {
pdest_buf[buf_idx++] = HE2SS_MCS7_4;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "MCS11_8", 6) == 0) {
pdest_buf[buf_idx++] = HE2SS_MCS11_8;
sz_line += 7;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
} else if (_os_strncmp(sz_line , "DCM4_0", 6) == 0) {
pdest_buf[buf_idx++] = HE2SS_DCM4_0;
sz_line += 6;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
}
} else if (_os_strncmp(sz_line , "[Offset]", 8) == 0) {
line_idx = 0;
pwrhexval = 0;
pdest_buf[buf_idx++] = band;
pdest_buf[buf_idx++] = PHYPG_OFFSET;
PHL_INFO("[Line]%s , line_idx %d \n", sz_line, line_idx);
line_idx += 8;
while (sz_line[line_idx] == ' ' || sz_line[line_idx] == '\t' || sz_line[line_idx] == '\0')
++line_idx;
sz_line += line_idx;
if (band == 0) {
if (_os_strncmp(sz_line , "AllRate1", 8) == 0) {
pdest_buf[buf_idx++] = Legacy_AllRate;
sz_line += 8;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
}
else if (_os_strncmp(sz_line , "AllRate2", 8) == 0) {
pdest_buf[buf_idx++] = HE_AllRate;
sz_line += 8;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
}
}
if (band == 1) {
if (_os_strncmp(sz_line , "AllRate1", 8) == 0) {
pdest_buf[buf_idx++] = Legacy_AllRate; /* 5G band all rate only OFDM upper */
sz_line += 8;
PHL_INFO("[Line]%s, line_idx %d \n", sz_line, line_idx);
pwrhexval = phypg_combvalue_fromstring(sz_line);
PHL_INFO("combine Value Get Pwr hex Val = %x\n", pwrhexval);
pdest_buf[buf_idx++] = pwrhexval;
}
}
}
}
}
return buf_idx;
exit:
#if 0 /*dbg dump*/
{
u32 i = 0 ;
char *strbuf , *pextra;
strbuf = _os_mem_alloc(drv_priv, buf_idx * sizeof(u32));
pextra = strbuf;
sprintf(strbuf, "\n");
pextra = strbuf + _os_strlen(strbuf);
for (i = 0; i <= buf_idx; i ++) {
pextra += sprintf(pextra, " %x \t", pdest_buf[i]);
if ( ((i+1)%4 == 0) && (i != 0))
pextra += sprintf(pextra, "\n");
}
printk( "%s \n" , strbuf);
_os_mem_free(drv_priv, strbuf, buf_idx * sizeof(u32));
}
#endif
return 0;
}
static int
_hal_parse_radio(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen)
{
struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t;
u32 *pdest_buf = para_info->para_data;
char *sz_line, *ptmp;
u32 dest_buf_idx = 0;
u32 u4bregoffset, u4bregvalue, u4bmove;
ptmp = (char *)psrc_buf;
for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) {
if (!hal_is_comment_string(sz_line)) {
/* Get 1st hex value as register offset. */
if (hal_get_hexvalue_fromstring(sz_line, &u4bregoffset, &u4bmove)) {
pdest_buf[dest_buf_idx] = u4bregoffset;
dest_buf_idx++;
if (u4bregoffset == 0xffff) {
/* Ending. */
pdest_buf[dest_buf_idx] = 0xffff;
PHL_INFO(" dest_buf_len: %d \n", dest_buf_idx);
break;
}
/* Get 2nd hex value as register value. */
sz_line += u4bmove;
if (hal_get_hexvalue_fromstring(sz_line, &u4bregvalue, &u4bmove)) {
/*PHL_INFO("[RF-ADDR]%03lx=%08lx\n", u4bregoffset, u4bregvalue);*/
pdest_buf[dest_buf_idx] = u4bregvalue;
dest_buf_idx++;
}
}
}
}
#if 0
{ /*debug dump buf*/
u32 i = 0;
for (i = 0; i <= dest_buf_idx; i+=2)
PHL_INFO("[Radio-ADDR] 0x%x :[0x%x]\n", pdest_buf[i], pdest_buf[i+1]);
}
#endif
return dest_buf_idx;
}
static int
hal_phy_find_ext_regd_num(struct rtw_para_pwrlmt_info_t *para_info,
char *regd_name)
{
int i = 0;
for (i = 0; i <= para_info->ext_regd_arridx ; i++) {
if (_os_strcmp(regd_name, para_info->ext_regd_name[i]) == 0) {
return i;
}
}
return -1;
}
static void
_hal_add_ext_reg_codemap(void *d,
struct rtw_para_pwrlmt_info_t *para_info,
const char *country,
u16 domain,
const char *regd_name,
u32 nlen)
{
struct _hal_file_regd_ext *pregd_codemap;
struct _hal_file_regd_ext *ent;
if (!regd_name || !nlen) {
PHL_ERR("regd_name || nlen Null\n");
goto exit;
}
pregd_codemap = (struct _hal_file_regd_ext *)para_info->ext_reg_codemap;
ent = &pregd_codemap[para_info->ext_reg_map_num];
if (regd_name && _os_strlen((u8*)regd_name) < 10) {
if (hal_phy_find_ext_regd_num(para_info, (char *)regd_name) == -1) {
u8 idx = (u8)(para_info->ext_regd_arridx + 1);
if (idx < regd_name_max_size) {
_os_strcpy(para_info->ext_regd_name[idx], regd_name);
para_info->ext_regd_arridx++;
PHL_INFO("extrea reg [%d] = [%s]\n",
idx, para_info->ext_regd_name[idx]);
} else {
PHL_ERR("extrea reg [%d] over size\n", idx);
goto exit;
}
}
_os_mem_cpy(d, ent->reg_name, (void*)regd_name, nlen);
PHL_INFO("store reg_name = [%s]\n", ent->reg_name);
} else {
PHL_ERR("reg_name = [%s]\n", ent->reg_name);
goto exit;
}
if (domain != 0)
ent->domain = domain;
else
ent->domain = 0xffff;
PHL_INFO("Store DomainCode = [0x%x]\n", ent->domain);
if (country) {
_os_mem_cpy(d, ent->country, (void*)country, 2);
PHL_INFO("Store country = [%c%c]\n", ent->country[0], ent->country[1]);
} else
_os_mem_set(d, ent->country, '\0', 2);
para_info->ext_reg_map_num++;
exit:
return;
}
/*
* @@Ver=2.0
* or
* @@DomainCode=0x28, Regulation=C6
* or
* @@CountryCode=GB, Regulation=C7
*/
static u8
parse_reg_exc_config(void *drv_priv,
char *sz_line ,
struct rtw_para_pwrlmt_info_t *para_info)
{
#define VER_PREFIX "Ver="
#define DOMAIN_PREFIX "DomainCode=0x"
#define COUNTRY_PREFIX "CountryCode="
#define REG_PREFIX "Regulation="
const u8 ver_prefix_len = (u8)_os_strlen((u8*)VER_PREFIX);
const u8 domain_prefix_len = (u8)_os_strlen((u8*)DOMAIN_PREFIX);
const u8 country_prefix_len = (u8)_os_strlen((u8*)COUNTRY_PREFIX);
const u8 reg_prefix_len = (u8)_os_strlen((u8*)REG_PREFIX);
u32 i, i_val_s, i_val_e;
u32 j;
u16 domain = 0;
char *country = NULL;
u8 parse_reg = 0;
if (sz_line[0] != '@' || sz_line[1] != '@')
return false;
i = 2;
if (_os_strncmp(sz_line + i, VER_PREFIX, ver_prefix_len) == 0)
; /* nothing to do */
else if (_os_strncmp(sz_line + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
/* get string after domain prefix to ',' */
i += domain_prefix_len;
i_val_s = i;
while (sz_line[i] != ',') {
if (sz_line[i] == '\0')
return false;
i++;
}
i_val_e = i;
/* check if all hex */
for (j = i_val_s; j < i_val_e; j++)
if (hal_ishexdigit(sz_line[j]) == false)
return false;
/* get value from hex string */
if (_os_sscanf(sz_line + i_val_s, "%hx", &domain) != 1)
return false;
parse_reg = 1;
} else if (_os_strncmp(sz_line + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
/* get string after country prefix to ',' */
i += country_prefix_len;
i_val_s = i;
while (sz_line[i] != ',') {
if (sz_line[i] == '\0')
return false;
i++;
}
i_val_e = i;
if (i_val_e - i_val_s != 2)
return false;
/* check if all alpha */
for (j = i_val_s; j < i_val_e; j++)
if (hal_is_alpha(sz_line[j]) == false)
return false;
country = sz_line + i_val_s;
parse_reg = 1;
} else
return false;
if (parse_reg) {
/* move to 'R' */
while (sz_line[i] != 'R') {
if (sz_line[i] == '\0')
return false;
i++;
}
/* check if matching regulation prefix */
if (_os_strncmp(sz_line + i, REG_PREFIX, reg_prefix_len) != 0)
return false;
/* get string after regulation prefix ending with space */
i += reg_prefix_len;
i_val_s = i;
while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0')
i++;
if (i == i_val_s)
return false;
_hal_add_ext_reg_codemap(drv_priv, para_info,
country, domain,
sz_line + i_val_s, i - i_val_s);
}
return true;
}
static void hal_phy_store_tx_power_limit (void *drv_priv,
u8 *sregulation,
u8 *sband,
u8 *sbandwidth,
u8 *sratesection,
u8 *sbf,
u8 *sntx,
u8 *schannel,
u8 *spwrlimit,
u8 *spshape_idx,
void *pstc_txpwr_lmt,
struct rtw_para_pwrlmt_info_t *para_info)
{
u8 band = 0, bandwidth = 0, ratesec = 0, channel = 0;
u8 ntx_idx = 0 , bf = 0 , pshape_idx = 0;
int regulation = -1;
s8 powerlimit = 0;
struct hal_txpwr_lmt_t *array_tc_8852a_txpwr_lmt = (struct hal_txpwr_lmt_t *)pstc_txpwr_lmt;
if (hal_get_u1bint_fromstr_indec((char *)schannel, &channel) == false
|| hal_get_s1bint_fromstr_indec((char *)spwrlimit, &powerlimit) == false) {
PHL_INFO("Illegal index of power limit table [ch %s][val %s]\n",
(char *)schannel, (char *)spwrlimit);
return;
}
if (spshape_idx != NULL) {
if (hal_get_u1bint_fromstr_indec((char *)spshape_idx, &pshape_idx) == false) {
PHL_INFO("Illegal index of pshape idx [val %s]\n", (char *)spshape_idx);
return;
}
}
if (_os_strncmp((char *)sratesection, (const char *)"CCK", 3) == 0)
ratesec = _PW_LMT_RS_CCK;
else if (_os_strncmp((char *)sratesection, (const char *)"OFDM", 4) == 0)
ratesec = _PW_LMT_RS_OFDM;
else if (_os_strncmp((char *)sratesection, (const char *)"HT", 2) == 0)
ratesec = _PW_LMT_RS_HT;
else if (_os_strncmp((char *)sratesection, (const char *)"VHT", 3) == 0)
ratesec = _PW_LMT_RS_VHT;
else if (_os_strncmp((char *)sratesection, (const char *)"HE", 2) == 0)
ratesec = _PW_LMT_RS_HE;
else {
PHL_INFO("Wrong rate section:%s\n", (char *)sratesection);
return;
}
if (_os_strncmp((char *)sntx, (const char *)"1T", 2) == 0)
ntx_idx = _PW_LMT_PH_1T;
else if (_os_strncmp((char *)sntx, (const char *)"2T", 2) == 0)
ntx_idx = _PW_LMT_PH_2T;
else if (_os_strncmp((char *)sntx, (const char *)"3T", 2) == 0)
ntx_idx = _PW_LMT_PH_3T;
else if (_os_strncmp((char *)sntx, (const char *)"4T", 2) == 0)
ntx_idx = _PW_LMT_PH_4T;
else {
PHL_INFO("Wrong tx num:%s\n", (char *)sntx);
return;
}
if (_os_strncmp((char *)sbandwidth, (const char *)"20M", 3) == 0)
bandwidth = _PW_LMT_BW_20M;
else if (_os_strncmp((char *)sbandwidth, (const char *)"40M", 3) == 0)
bandwidth = _PW_LMT_BW_40M;
else if (_os_strncmp((char *)sbandwidth, (const char *)"80M", 3) == 0)
bandwidth = _PW_LMT_BW_80M;
else if (_os_strncmp((char *)sbandwidth, (const char *)"160M", 4) == 0)
bandwidth = _PW_LMT_BW_160M;
else {
PHL_INFO("unknown bandwidth: %s\n", (char *)sbandwidth);
return;
}
if (_os_strncmp((char *)sband, (const char *)"2.4G", 4) == 0)
band = _PW_LMT_BAND_2_4G;
else if (_os_strncmp((char *)sband, (const char *)"5G", 2) == 0)
band = _PW_LMT_BAND_5G;
else {
PHL_INFO("unknown band: %s\n", (char *)sband);
return;
}
if (_os_strncmp((char *)sbf, (const char *)"Non-BF", 6) == 0 || _os_strncmp((char *)sbf, (const char *)"NA", 2) == 0)
bf = _PW_LMT_NONBF;
else if (_os_strncmp((char *)sbf, (const char *)"BF", 2) == 0)
bf = _PW_LMT_BF;
else {
PHL_INFO("unknown BF: %s\n", (char *)sbf);
return;
}
regulation = rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str((char *)sregulation);
if (regulation == -1) {
int regd_num = hal_phy_find_ext_regd_num(para_info, (char *)sregulation);
if (regd_num != -1) {
regulation = (u8)regd_num;
PHL_INFO("new regulation num: %d\n", regulation);
} else {
PHL_INFO("unknown regulation: %s\n", (char *)sregulation);
return;
}
}
array_tc_8852a_txpwr_lmt->band = band;
array_tc_8852a_txpwr_lmt->bw = bandwidth;
array_tc_8852a_txpwr_lmt->ch = channel;
array_tc_8852a_txpwr_lmt->rs = ratesec;
array_tc_8852a_txpwr_lmt->ntx = ntx_idx;
array_tc_8852a_txpwr_lmt->bf = bf;
array_tc_8852a_txpwr_lmt->val = powerlimit;
array_tc_8852a_txpwr_lmt->reg = (u8)regulation;
array_tc_8852a_txpwr_lmt->tx_shap_idx = pshape_idx;
PHL_INFO("Store of power limit table [regulation %d][band %d][bw %d]"\
"[rate section %d][ntx %d][BF %d][chnl %d][val %d] [sphape_idx %d]\n",
array_tc_8852a_txpwr_lmt->reg, array_tc_8852a_txpwr_lmt->band,
array_tc_8852a_txpwr_lmt->bw , array_tc_8852a_txpwr_lmt->rs,
array_tc_8852a_txpwr_lmt->ntx, array_tc_8852a_txpwr_lmt->bf,
array_tc_8852a_txpwr_lmt->ch, array_tc_8852a_txpwr_lmt->val,
array_tc_8852a_txpwr_lmt->tx_shap_idx);
}
static int
_hal_parse_txpwrlmt(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen)
{
#define LD_STAGE_EXC_MAPPING 0
#define LD_STAGE_TAB_DEFINE 1
#define LD_STAGE_TAB_START 2
#define LD_STAGE_COLUMN_DEFINE 3
#define LD_STAGE_COLUMN_REG 4
#define LD_STAGE_CH_ROW 5
#define LD_STAGE_PSHAPE_NUM 6
struct rtw_para_pwrlmt_info_t *para_info = (struct rtw_para_pwrlmt_info_t *)para_info_t;
u32 *pdest_buf = para_info->para_data;
char **regulation = NULL;
char **pshape = NULL;
char *sz_line = NULL, *ptmp = NULL;
char band[10], bandwidth[10], ratesection[10], ntx[10], colnumbuf[10], bf_type[10];
u8 colnum = 0;
u8 loadingstage = LD_STAGE_EXC_MAPPING;
u32 struct_idx = 0;
u32 i = 0, forcnt = 0;
PHAL_TXPWR_LMT_T array_tc_8852a_txpwr_lmt;
if (pdest_buf == NULL || psrc_buf == NULL) {
PHL_INFO("%s, fail !!! NULL buf !!!\n", __func__);
return 0;
}
array_tc_8852a_txpwr_lmt = (PHAL_TXPWR_LMT_T)pdest_buf;
ptmp = (char *)psrc_buf;
for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) {
line_start:
if (hal_is_allspace_tab(sz_line, sizeof(*sz_line)))
continue;
if (hal_is_comment_string(sz_line))
continue;
if (loadingstage == LD_STAGE_EXC_MAPPING) {
if (sz_line[0] == '#' || sz_line[1] == '#') {
loadingstage = LD_STAGE_TAB_DEFINE;
} else {
if (parse_reg_exc_config(drv_priv, sz_line, para_info) == false) {
PHL_ERR("Fail to parse regulation exception ruls!\n");
goto exit;
}
continue;
}
}
if (loadingstage == LD_STAGE_TAB_DEFINE) {
/* read "## 2.4G, 20M, 1T, CCK" */
if (sz_line[0] != '#' || sz_line[1] != '#')
continue;
/* skip the space */
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
sz_line[--i] = ' '; /* return the space in front of the regulation info */
/* Parse the label of the table */
_os_mem_set(drv_priv, (void *) band, 0, 10);
_os_mem_set(drv_priv, (void *) bandwidth, 0, 10);
_os_mem_set(drv_priv, (void *) ntx, 0, 10);
_os_mem_set(drv_priv, (void *) ratesection, 0, 10);
_os_mem_set(drv_priv, (void *) bf_type, 0, 10);
if (!hal_parse_fiedstring(sz_line, &i, band, ' ', ',')) {
PHL_ERR("Fail to parse band!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, bandwidth, ' ', ',')) {
PHL_ERR("Fail to parse bandwidth!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, ntx, ' ', ',')) {
PHL_ERR("Fail to parse ntx!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, ratesection, ' ', ',')) {
PHL_ERR("Fail to parse rate!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, bf_type, ' ', '/')) {
PHL_ERR("Fail to parse BF!\n");
struct_idx = 0;
goto exit;
}
loadingstage = LD_STAGE_TAB_START;
} else if (loadingstage == LD_STAGE_TAB_START) {
/* read "## START" */
if (sz_line[0] != '#' || sz_line[1] != '#')
continue;
/* skip the space */
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
if (_os_strncmp((char *)(sz_line + i), (const char *)"START", 5)) {
PHL_ERR("Missing \"## START\" label\n");
struct_idx = 0;
goto exit;
}
loadingstage = LD_STAGE_COLUMN_DEFINE;
} else if (loadingstage == LD_STAGE_COLUMN_DEFINE) {
/* read "## #5# " */
if (sz_line[0] != '#' || sz_line[1] != '#')
/* skip the space */
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
_os_mem_set(drv_priv, (void *) colnumbuf, 0, 10);
if (!hal_parse_fiedstring(sz_line, &i, colnumbuf, '#', '#')) {
PHL_ERR("Fail to parse column number!\n");
struct_idx = 0;
goto exit;
}
if (!hal_get_u1bint_fromstr_indec(colnumbuf, &colnum)) {
PHL_ERR("Column number \"%s\" is not unsigned decimal\n", colnumbuf);
struct_idx = 0;
goto exit;
}
if (colnum == 0) {
PHL_ERR("Column number is 0\n");
struct_idx = 0;
goto exit;
}
PHL_INFO("[%s][%s][%s][%s][%s] column num:%d\n",
band, bandwidth, ratesection, ntx, bf_type, colnum);
regulation = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * colnum);
if (!regulation) {
PHL_ERR("Regulation alloc fail\n");
struct_idx = 0;
goto exit;
}
pshape = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * colnum);
if (!pshape) {
PHL_ERR("Regulation alloc fail\n");
struct_idx = 0;
goto exit;
}
loadingstage = LD_STAGE_COLUMN_REG;
} else if (loadingstage == LD_STAGE_COLUMN_REG) {
/* read "## FCC ETSI MKK IC KCC" */
if (sz_line[0] != '#' || sz_line[1] != '#')
continue;
/* skip the space */
i = 2;
for (forcnt = 0; forcnt < colnum; ++forcnt) {
u32 i_ns;
/* skip the space */
while (sz_line[i] == ' ' || sz_line[i] == '\t')
i++;
i_ns = i;
while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0')
i++;
regulation[forcnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1);
if (!regulation[forcnt]) {
PHL_ERR("Regulation alloc fail\n");
struct_idx = 0;
goto exit;
}
_os_mem_cpy(drv_priv, regulation[forcnt], sz_line + i_ns, i - i_ns);
regulation[forcnt][i - i_ns] = '\0';
}
if (1) {
PHL_INFO("column name:");
for (forcnt = 0; forcnt < colnum; ++forcnt)
PHL_INFO(" %s", regulation[forcnt]);
PHL_INFO("\n");
}
loadingstage = LD_STAGE_PSHAPE_NUM;
}else if (loadingstage == LD_STAGE_PSHAPE_NUM) {
if (sz_line[0] == '#' || sz_line[1] == '#')
continue;
if ((sz_line[0] != 'p' && sz_line[0] != 'P') ||
(sz_line[1] != 's' && sz_line[1] != 'S')) {
PHL_INFO("No PShape prefix: '%c','%c'(%d,%d), continue to CH ROW\n",
sz_line[0], sz_line[1], sz_line[0], sz_line[1]);
loadingstage = LD_STAGE_CH_ROW;
goto line_start;
}
PHL_INFO("1.sz_line[0 1] %c %c", sz_line[0], sz_line[1]);
i = 6;/* move to the location behind 'e' */
for (forcnt = 0; forcnt < colnum; ++forcnt) {
u32 i_ns;
/* skip the space */
while (sz_line[i] == ' ' || sz_line[i] == '\t')
i++;
i_ns = i;
PHL_INFO("1.sz_line[%d] %c\n", i ,sz_line[i]);
while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0')
i++;
pshape[forcnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1);
if (!pshape[forcnt]) {
PHL_ERR("Regulation alloc fail, pshape [%d]\n", forcnt);
goto exit;
}
PHL_INFO("2.pshape [%d] = %s\n", forcnt, pshape[forcnt]);
_os_mem_cpy(drv_priv, pshape[forcnt], sz_line + i_ns, i - i_ns);
pshape[forcnt][i - i_ns] = '\0';
PHL_INFO(" forcnt %d shape idx: %s:", forcnt, pshape[forcnt]);
}
if (1) {
PHL_INFO("pshape idx:");
for (forcnt = 0; forcnt < colnum; ++forcnt)
PHL_INFO(" %s", pshape[forcnt]);
PHL_INFO("\n");
}
loadingstage = LD_STAGE_CH_ROW;
} else if (loadingstage == LD_STAGE_CH_ROW) {
char channel[10] = {0}, powerlimit[10] = {0};
u8 cnt = 0;
/* the table ends */
if (sz_line[0] == '#' && sz_line[1] == '#') {
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
if (_os_strncmp((char *)(sz_line + i), (const char *)"END", 3) == 0) {
loadingstage = LD_STAGE_TAB_DEFINE;
if (regulation) {
for (forcnt = 0; forcnt < colnum; ++forcnt) {
if (regulation[forcnt]) {
_os_mem_free(drv_priv,
(u8 *)regulation[forcnt],
_os_strlen((u8 *)regulation[forcnt]) + 1);
regulation[forcnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * colnum);
regulation = NULL;
}
if (pshape) {
for (forcnt = 0; forcnt < colnum; ++forcnt) {
if (pshape[forcnt]) {
_os_mem_free(drv_priv,
(u8 *)pshape[forcnt],
_os_strlen((u8 *)pshape[forcnt]) + 1);
pshape[forcnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * colnum);
pshape = NULL;
}
colnum = 0;
continue;
} else {
PHL_ERR("Missing \"## END\" label\n");
struct_idx = 0;
goto exit;
}
}
if ((sz_line[0] != 'c' && sz_line[0] != 'C') ||
(sz_line[1] != 'h' && sz_line[1] != 'H')) {
PHL_ERR("Wrong channel prefix: '%c','%c'(%d,%d)\n",
sz_line[0], sz_line[1], sz_line[0], sz_line[1]);
continue;
}
i = 2;/* move to the location behind 'h' */
/* load the channel number */
cnt = 0;
while (sz_line[i] >= '0' && sz_line[i] <= '9') {
channel[cnt] = sz_line[i];
++cnt;
++i;
}
PHL_INFO("chnl %s!\n", channel);
for (forcnt = 0; forcnt < colnum; ++forcnt) {
/* skip the space between channel number and the power limit value */
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
/* load the power limit value */
_os_mem_set(drv_priv, (void *) powerlimit, 0, 10);
if (sz_line[i] == 'W' && sz_line[i + 1] == 'W') {
/*
* case "WW" assign special ww value
* means to get minimal limit in other regulations at same channel
*/
s8 ww_value = -63;
_os_snprintf(powerlimit, 10, "%d", ww_value);
i += 2;
} else if (sz_line[i] == 'N' && sz_line[i + 1] == 'A') {
/*
* case "NA" assign max txgi value
* means no limitation
*/
_os_snprintf(powerlimit, 10, "%d", 63);
i += 2;
} else if ((sz_line[i] >= '0' && sz_line[i] <= '9') || sz_line[i] == '.'
|| sz_line[i] == '+' || sz_line[i] == '-') {
/* case of dBm value */
u8 integer = 0, fraction = 0, negative = 0;
u32 u4bmove;
s8 lmt = 0;
if (sz_line[i] == '+' || sz_line[i] == '-') {
if (sz_line[i] == '-')
negative = 1;
i++;
}
if (hal_get_fractionvalue_fromstring(&sz_line[i], &integer, &fraction, &u4bmove))
i += u4bmove;
else {
PHL_ERR("Limit \"%s\" is not valid decimal\n", &sz_line[i]);
struct_idx = 0;
goto exit;
}
/* transform to string of value in unit of txgi */
lmt = (integer * 4) + ((u16)fraction * 4 / 100);
if (negative)
lmt = -lmt;
_os_snprintf(powerlimit, 10, "%d", lmt);
} else {
PHL_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
, sz_line[i], sz_line[i + 1], sz_line[i], sz_line[i + 1]);
struct_idx = 0;
goto exit;
}
/* store the power limit value */
hal_phy_store_tx_power_limit(drv_priv, (u8 *)regulation[forcnt],
(u8 *)band, (u8 *)bandwidth, (u8 *)ratesection,
(u8 *)bf_type, (u8 *)ntx, (u8 *)channel,
(u8 *)powerlimit, (u8 *)pshape[forcnt],
(void*)&array_tc_8852a_txpwr_lmt[struct_idx], para_info);
struct_idx++;
}
}
}
exit:
if (regulation) {
for (forcnt = 0; forcnt < colnum; ++forcnt) {
if (regulation[forcnt]) {
_os_mem_free(drv_priv,
(u8 *)regulation[forcnt],
_os_strlen((u8 *)regulation[forcnt]) + 1);
regulation[forcnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * colnum);
regulation = NULL;
}
if (pshape) {
for (forcnt = 0; forcnt < colnum; ++forcnt) {
if (pshape[forcnt]) {
_os_mem_free(drv_priv,
(u8 *)pshape[forcnt],
_os_strlen((u8 *)pshape[forcnt]) + 1);
pshape[forcnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * colnum);
pshape = NULL;
}
return struct_idx;
}
static void hal_phy_store_tx_power_limit_ru (void *drv_priv,
u8 *sregulation,
u8 *sband,
u8 *sbandwidth,
u8 *sratesection,
u8 *sntx,
u8 *schannel,
u8 *spwrlimit,
u8 *spshape_idx,
void *pstc_txpwr_lmt_ru,
struct rtw_para_pwrlmt_info_t *para_info)
{
u8 band = 0, bandwidth = 0, ratesec = 0, channel = 0;
u8 ntx_idx = 0 , pshape_idx = 0;
int regulation = -1;
s8 powerlimit = 0;
struct hal_txpwr_lmt_ru_t *array_tc_8852a_txpwr_lmt_ru = (struct hal_txpwr_lmt_ru_t *)pstc_txpwr_lmt_ru;
if (hal_get_u1bint_fromstr_indec((char *)schannel, &channel) == false
|| hal_get_s1bint_fromstr_indec((char *)spwrlimit, &powerlimit) == false) {
PHL_INFO("Illegal index of power limit table [ch %s][val %s]\n",
(char *)schannel, (char *)spwrlimit);
return;
}
if (spshape_idx != NULL) {
if (hal_get_u1bint_fromstr_indec((char *)spshape_idx, &pshape_idx) == false) {
PHL_INFO("Illegal index of pshape idx [val %s]\n", (char *)spshape_idx);
return;
}
}
if (_os_strncmp((char *)sband, (const char *)"2.4G", 4) == 0)
band = _PW_LMT_BAND_2_4G;
else if (_os_strncmp((char *)sband, (const char *)"5G", 2) == 0)
band = _PW_LMT_BAND_5G;
else {
PHL_INFO("unknown band: %s\n", (char *)sband);
return;
}
if (_os_strncmp((char *)sbandwidth, (const char *)"RU26", 4) == 0)
bandwidth = _PW_LMT_RU_BW_RU26;
else if (_os_strncmp((char *)sbandwidth, (const char *)"RU52", 4) == 0)
bandwidth = _PW_LMT_RU_BW_RU52;
else if (_os_strncmp((char *)sbandwidth, (const char *)"RU106", 5) == 0)
bandwidth = _PW_LMT_RU_BW_RU106;
else {
PHL_INFO("unknown RU bandwidth: %s\n", (char *)sbandwidth);
return;
}
if (_os_strncmp((char *)sntx, (const char *)"1T", 2) == 0)
ntx_idx = _PW_LMT_PH_1T;
else if (_os_strncmp((char *)sntx, (const char *)"2T", 2) == 0)
ntx_idx = _PW_LMT_PH_2T;
else if (_os_strncmp((char *)sntx, (const char *)"3T", 2) == 0)
ntx_idx = _PW_LMT_PH_3T;
else if (_os_strncmp((char *)sntx, (const char *)"4T", 2) == 0)
ntx_idx = _PW_LMT_PH_4T;
else {
PHL_INFO("Wrong tx num:%s\n", (char *)sntx);
return;
}
if (_os_strncmp((char *)sratesection, (const char *)"HE", 2) == 0)
ratesec = _PW_LMT_RS_HE;
else {
PHL_INFO("Wrong RU rate section:%s\n", (char *)sratesection);
return;
}
regulation = rtw_hal_rf_get_predefined_pw_lmt_regu_type_from_str((char *)sregulation);
if (regulation == -1) {
int regd_num = hal_phy_find_ext_regd_num(para_info, (char *)sregulation);
if (regd_num != -1) {
regulation = (u8)regd_num;
PHL_INFO("new regulation num: %d\n", regulation);
} else {
PHL_INFO("unknown regulation: %s\n", (char *)sregulation);
return;
}
}
array_tc_8852a_txpwr_lmt_ru->band = band;
array_tc_8852a_txpwr_lmt_ru->rubw = bandwidth;
array_tc_8852a_txpwr_lmt_ru->ntx = ntx_idx;
array_tc_8852a_txpwr_lmt_ru->rs = ratesec;
array_tc_8852a_txpwr_lmt_ru->reg = (u8)regulation;
array_tc_8852a_txpwr_lmt_ru->ch = channel;
array_tc_8852a_txpwr_lmt_ru->val = powerlimit;
array_tc_8852a_txpwr_lmt_ru->tx_shap_idx = pshape_idx;
PHL_INFO("Store of power limit RU table [band %d][bw %d][ntx %d]"\
"[rate section %d][regulation %d][chnl %d][val %d] [sphape_idx %d]\n",
array_tc_8852a_txpwr_lmt_ru->band , array_tc_8852a_txpwr_lmt_ru->rubw,
array_tc_8852a_txpwr_lmt_ru->ntx, array_tc_8852a_txpwr_lmt_ru->rs,
array_tc_8852a_txpwr_lmt_ru->reg, array_tc_8852a_txpwr_lmt_ru->ch,
array_tc_8852a_txpwr_lmt_ru->val, array_tc_8852a_txpwr_lmt_ru->tx_shap_idx);
}
static int
_hal_parse_txpwrlmt_ru(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen)
{
#define LD_STAGE_EXC_MAPPING 0
#define LD_STAGE_TAB_DEFINE 1
#define LD_STAGE_TAB_START 2
#define LD_STAGE_COLUMN_DEFINE 3
#define LD_STAGE_COLUMN_REG 4
#define LD_STAGE_CH_ROW 5
#define LD_STAGE_PSHAPE_NUM 6
struct rtw_para_pwrlmt_info_t *para_info = (struct rtw_para_pwrlmt_info_t *)para_info_t;
u32 *pdest_buf = para_info->para_data;
char **regulation = NULL;
char **pshape = NULL;
char *sz_line = NULL, *ptmp = NULL;
char band[10], bandwidth[10], ratesection[10], ntx[10], col_num_buf[10];
u8 col_num = 0;
u8 loadingstage = LD_STAGE_EXC_MAPPING;
u32 struct_idx = 0;
u32 i = 0, for_cnt = 0;
pHal_Txpwr_lmt_Ru_t array_tc_8852a_txpwr_lmt_ru;
if (pdest_buf == NULL || psrc_buf == NULL) {
PHL_INFO("%s, fail !!! NULL buf !!!\n", __func__);
return 0;
}
array_tc_8852a_txpwr_lmt_ru = (pHal_Txpwr_lmt_Ru_t)pdest_buf;
ptmp = (char *)psrc_buf;
for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL; sz_line = hal_getLinefrombuffer(ptmp)) {
line_start:
if (hal_is_allspace_tab(sz_line, sizeof(*sz_line)))
continue;
if (hal_is_comment_string(sz_line))
continue;
if (loadingstage == LD_STAGE_EXC_MAPPING) {
if (sz_line[0] == '#' || sz_line[1] == '#') {
loadingstage = LD_STAGE_TAB_DEFINE;
} else {
if (parse_reg_exc_config(drv_priv, sz_line, para_info) == false) {
PHL_ERR("Fail to parse regulation exception ruls!\n");
goto exit;
}
continue;
}
}
if (loadingstage == LD_STAGE_TAB_DEFINE) {
/* read "## 2.4G, RU26, 1T, HE //" */
if (sz_line[0] != '#' || sz_line[1] != '#')
continue;
/* skip the space */
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
sz_line[--i] = ' '; /* return the space in front of the regulation info */
/* Parse the label of the table */
_os_mem_set(drv_priv, (void *) band, 0, 10);
_os_mem_set(drv_priv, (void *) bandwidth, 0, 10);
_os_mem_set(drv_priv, (void *) ntx, 0, 10);
_os_mem_set(drv_priv, (void *) ratesection, 0, 10);
if (!hal_parse_fiedstring(sz_line, &i, band, ' ', ',')) {
PHL_ERR("Fail to parse band!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, bandwidth, ' ', ',')) {
PHL_ERR("Fail to parse bandwidth!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, ntx, ' ', ',')) {
PHL_ERR("Fail to parse ntx!\n");
struct_idx = 0;
goto exit;
}
if (!hal_parse_fiedstring(sz_line, &i, ratesection, ' ', ' ')) {
PHL_ERR("Fail to parse rate!\n");
struct_idx = 0;
goto exit;
}
loadingstage = LD_STAGE_TAB_START;
} else if (loadingstage == LD_STAGE_TAB_START) {
/* read "## START" */
if (sz_line[0] != '#' || sz_line[1] != '#')
continue;
/* skip the space */
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
if (_os_strncmp((char *)(sz_line + i), (const char *)"START", 5)) {
PHL_ERR("Missing \"## START\" label\n");
struct_idx = 0;
goto exit;
}
loadingstage = LD_STAGE_COLUMN_DEFINE;
} else if (loadingstage == LD_STAGE_COLUMN_DEFINE) {
/* read "## #5# " */
if (sz_line[0] != '#' || sz_line[1] != '#')
/* skip the space */
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
_os_mem_set(drv_priv, (void *) col_num_buf, 0, 10);
if (!hal_parse_fiedstring(sz_line, &i, col_num_buf, '#', '#')) {
PHL_ERR("Fail to parse column number!\n");
struct_idx = 0;
goto exit;
}
if (!hal_get_u1bint_fromstr_indec(col_num_buf, &col_num)) {
PHL_ERR("Column number \"%s\" is not unsigned decimal\n", col_num_buf);
struct_idx = 0;
goto exit;
}
if (col_num == 0) {
PHL_ERR("Column number is 0\n");
struct_idx = 0;
goto exit;
}
PHL_INFO("[%s][%s][%s][%s] column num:%d\n",
band, bandwidth, ratesection, ntx, col_num);
regulation = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * col_num);
if (!regulation) {
PHL_ERR("Regulation alloc fail\n");
struct_idx = 0;
goto exit;
}
pshape = (char **)_os_mem_alloc(drv_priv, sizeof(char *) * col_num);
if (!pshape) {
PHL_ERR("Regulation alloc fail\n");
struct_idx = 0;
goto exit;
}
loadingstage = LD_STAGE_COLUMN_REG;
}else if (loadingstage == LD_STAGE_COLUMN_REG) {
/* read "## FCC ETSI MKK IC KCC" */
if (sz_line[0] != '#' || sz_line[1] != '#')
continue;
/* skip the space */
i = 2;
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
u32 i_ns;
/* skip the space */
while (sz_line[i] == ' ' || sz_line[i] == '\t')
i++;
i_ns = i;
while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0')
i++;
regulation[for_cnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1);
if (!regulation[for_cnt]) {
PHL_ERR("Regulation alloc fail\n");
struct_idx = 0;
goto exit;
}
_os_mem_cpy(drv_priv, regulation[for_cnt], sz_line + i_ns, i - i_ns);
regulation[for_cnt][i - i_ns] = '\0';
}
if (1) {
PHL_INFO("column name:");
for (for_cnt = 0; for_cnt < col_num; ++for_cnt)
PHL_INFO(" %s", regulation[for_cnt]);
PHL_INFO("\n");
}
loadingstage = LD_STAGE_PSHAPE_NUM;
}else if (loadingstage == LD_STAGE_PSHAPE_NUM) {
if (sz_line[0] == '#' || sz_line[1] == '#')
continue;
if ((sz_line[0] != 'p' && sz_line[0] != 'P') ||
(sz_line[1] != 's' && sz_line[1] != 'S')) {
PHL_INFO("No PShape prefix: '%c','%c'(%d,%d), continue to CH ROW\n",
sz_line[0], sz_line[1], sz_line[0], sz_line[1]);
loadingstage = LD_STAGE_CH_ROW;
goto line_start;
}
PHL_INFO("1.sz_line[0 1] %c %c", sz_line[0], sz_line[1]);
i = 6;/* move to the location behind 'e' */
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
u32 i_ns;
/* skip the space */
while (sz_line[i] == ' ' || sz_line[i] == '\t')
i++;
i_ns = i;
PHL_INFO("1.sz_line[%d] %c\n", i ,sz_line[i]);
while (sz_line[i] != ' ' && sz_line[i] != '\t' && sz_line[i] != '\0')
i++;
pshape[for_cnt] = (char *)_os_mem_alloc(drv_priv, i - i_ns + 1);
if (!pshape[for_cnt]) {
PHL_ERR("Regulation alloc fail, pshape [%d]\n", for_cnt);
goto exit;
}
PHL_INFO("2.pshape [%d] = %s\n", for_cnt, pshape[for_cnt]);
_os_mem_cpy(drv_priv, pshape[for_cnt], sz_line + i_ns, i - i_ns);
pshape[for_cnt][i - i_ns] = '\0';
PHL_INFO(" forcnt %d shape idx: %s:", for_cnt, pshape[for_cnt]);
}
if (1) {
PHL_INFO("pshape idx:");
for (for_cnt = 0; for_cnt < col_num; ++for_cnt)
PHL_INFO(" %s", pshape[for_cnt]);
PHL_INFO("\n");
}
loadingstage = LD_STAGE_CH_ROW;
} else if (loadingstage == LD_STAGE_CH_ROW) {
char channel[10] = {0}, powerlimit[10] = {0};
u8 cnt = 0;
/* the table ends */
if (sz_line[0] == '#' && sz_line[1] == '#') {
i = 2;
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
if (_os_strncmp((char *)(sz_line + i), (const char *)"END", 3) == 0) {
loadingstage = LD_STAGE_TAB_DEFINE;
if (regulation) {
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
if (regulation[for_cnt]) {
_os_mem_free(drv_priv,
(u8 *)regulation[for_cnt],
_os_strlen((u8 *)regulation[for_cnt]) + 1);
regulation[for_cnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * col_num);
regulation = NULL;
}
if (pshape) {
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
if (pshape[for_cnt]) {
_os_mem_free(drv_priv,
(u8 *)pshape[for_cnt],
_os_strlen((u8 *)pshape[for_cnt]) + 1);
pshape[for_cnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * col_num);
pshape = NULL;
}
col_num = 0;
continue;
} else {
PHL_ERR("Missing \"## END\" label\n");
struct_idx = 0;
goto exit;
}
}
if ((sz_line[0] != 'c' && sz_line[0] != 'C') ||
(sz_line[1] != 'h' && sz_line[1] != 'H')) {
PHL_ERR("Wrong channel prefix: '%c','%c'(%d,%d)\n",
sz_line[0], sz_line[1], sz_line[0], sz_line[1]);
continue;
}
i = 2;/* move to the location behind 'h' */
/* load the channel number */
cnt = 0;
while (sz_line[i] >= '0' && sz_line[i] <= '9') {
channel[cnt] = sz_line[i];
++cnt;
++i;
}
PHL_INFO("chnl %s!\n", channel);
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
/* skip the space between channel number and the power limit value */
while (sz_line[i] == ' ' || sz_line[i] == '\t')
++i;
/* load the power limit value */
_os_mem_set(drv_priv, (void *) powerlimit, 0, 10);
if (sz_line[i] == 'W' && sz_line[i + 1] == 'W') {
/*
* case "WW" assign special ww value
* means to get minimal limit in other regulations at same channel
*/
s8 ww_value = -63;//phy_txpwr_ww_lmt_value(Adapter);
_os_snprintf(powerlimit, 10, "%d", ww_value);
i += 2;
} else if (sz_line[i] == 'N' && sz_line[i + 1] == 'A') {
/*
* case "NA" assign max txgi value
* means no limitation
*/
_os_snprintf(powerlimit, 10, "%d", 127);
i += 2;
} else if ((sz_line[i] >= '0' && sz_line[i] <= '9') || sz_line[i] == '.'
|| sz_line[i] == '+' || sz_line[i] == '-') {
/* case of dBm value */
u8 integer = 0, fraction = 0, negative = 0;
u32 u4bmove;
s8 lmt = 0;
if (sz_line[i] == '+' || sz_line[i] == '-') {
if (sz_line[i] == '-')
negative = 1;
i++;
}
if (hal_get_fractionvalue_fromstring(&sz_line[i], &integer, &fraction, &u4bmove))
i += u4bmove;
else {
PHL_ERR("Limit \"%s\" is not valid decimal\n", &sz_line[i]);
struct_idx = 0;
goto exit;
}
/* transform to string of value in unit of txgi */
lmt = (integer * 4) + ((u16)fraction * 4 / 100);
if (negative)
lmt = -lmt;
_os_snprintf(powerlimit, 10, "%d", lmt);
} else {
PHL_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
, sz_line[i], sz_line[i + 1], sz_line[i], sz_line[i + 1]);
struct_idx = 0;
goto exit;
}
/* store the power limit value */
hal_phy_store_tx_power_limit_ru(drv_priv,
(u8 *)regulation[for_cnt], (u8 *)band,
(u8 *)bandwidth, (u8 *)ratesection,
(u8 *)ntx, (u8 *)channel, (u8 *)powerlimit,
(u8 *)pshape[for_cnt],
(void*)&array_tc_8852a_txpwr_lmt_ru[struct_idx],
para_info);
PHL_INFO("array_tc_8852a_txpwr_lmt_ru[%d] \n", struct_idx);
struct_idx++;
}
}
}
exit:
if (regulation) {
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
if (regulation[for_cnt]) {
_os_mem_free(drv_priv,
(u8 *)regulation[for_cnt],
_os_strlen((u8 *)regulation[for_cnt]) + 1);
regulation[for_cnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)regulation, sizeof(char *) * col_num);
regulation = NULL;
}
if (pshape) {
for (for_cnt = 0; for_cnt < col_num; ++for_cnt) {
if (pshape[for_cnt]) {
_os_mem_free(drv_priv,
(u8 *)pshape[for_cnt],
_os_strlen((u8 *)pshape[for_cnt]) + 1);
pshape[for_cnt] = NULL;
}
}
_os_mem_free(drv_priv, (u8 *)pshape, sizeof(char *) * col_num);
pshape = NULL;
}
return struct_idx;
}
static void hal_phy_store_tx_power_track(
void *drv_priv,
char *band,
char *path,
char *sign,
char *channel,
char *rate,
char *data,
void *txpwr_track_table)
{
#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
((_os_strcmp(band, _band) == 0) && (_os_strcmp(path, _path) == 0) && (_os_strcmp(sign, _sign) == 0) &&\
(_os_strcmp(rate, _rate) == 0) && (_os_strcmp(channel, _chnl) == 0)\
)
#define STR_EQUAL_2G(_band, _path, _sign, _rate) \
((_os_strcmp(band, _band) == 0) && (_os_strcmp(path, _path) == 0) && (_os_strcmp(sign, _sign) == 0) &&\
(_os_strcmp(rate, _rate) == 0)\
)
#define STORE_SWING_TABLE(_array, _iteratedIdx) \
do { \
for (token = (char *)_os_strsep(&data, delim); token != (char *)NULL; token = (char *)_os_strsep(&data, delim)) {\
_os_sscanf(token, "%d", &idx);\
_array[_iteratedIdx++] = (s8)idx;\
} } while (0)\
struct hal_txpwr_track_t *prfcalibrateInfo = (struct hal_txpwr_track_t *)txpwr_track_table;
u32 j = 0;
char *token;
char delim[] = ",";
u32 idx = 0;
PHL_INFO("===>initDeltaSwingIndexTables():"\
"Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n",
band, path, sign, channel, rate, data);
if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2ga_p, j);
else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2ga_n, j);
else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2gb_p, j);
else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_2gb_n, j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
STORE_SWING_TABLE(prfcalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
else
PHL_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
}
static int
_hal_parse_txpwrtrack(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen)
{
struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t;
u32 *pdest_buf = para_info->para_data;
char *sz_line = NULL, *ptmp = NULL;
u32 i = 0;
struct hal_txpwr_track_t *txpwr_track;
if (pdest_buf == NULL || psrc_buf == NULL) {
PHL_INFO("%s, fail !!! NULL buf !!!\n", __func__);
return 0;
}
/* Assing destination buffer to be Txpwr_track table format*/
txpwr_track = (struct hal_txpwr_track_t *)pdest_buf;
ptmp = (char *)psrc_buf;
for (sz_line = hal_getLinefrombuffer(ptmp); sz_line != NULL;
sz_line = hal_getLinefrombuffer(ptmp))
{
if (!hal_is_comment_string(sz_line)) {
char band[5] = "", path[5] = "", sign[5] = "";
char chnl[5] = "", rate[10] = "";
char data[300] = ""; /* 100 is too small */
if (_os_strlen((u8 *)sz_line) < 10 || sz_line[0] != '[')
continue;
_os_strncpy(band, sz_line + 1, 2);
_os_strncpy(path, sz_line + 5, 1);
_os_strncpy(sign, sz_line + 8, 1);
i = 10; /* sz_line+10 */
if (!hal_parse_fiedstring(sz_line, &i, rate, '[', ']')) {
PHL_ERR("Fail to parse rate!\n");
}
if (!hal_parse_fiedstring(sz_line, &i, chnl, '[', ']')) {
if (!_os_strcmp("5G",band))
PHL_ERR("Fail to parse channel group!\n");
}
while (i < _os_strlen((u8 *)sz_line) && '{' != sz_line[i])
i++;
if (!hal_parse_fiedstring(sz_line, &i, data, '{', '}')) {
PHL_ERR("Fail to parse data!\n");
}
hal_phy_store_tx_power_track(drv_priv,
band, path, sign,
chnl, rate, data,
(void*)txpwr_track);
}
}
return 1;
}
void
_hal_dl_para_file(struct rtw_phl_com_t *phl_com,
void *para_info_t, char *ic_name,
int (*parser_fun)(void *drv_priv, void *para_info_t, u8 *psrc_buf, u32 buflen),
const char *file_name)
{
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
void *drv = phl_com->drv_priv;
char *hal_phy_folder = HAL_FILE_CONFIG_PATH;
u32 para_size = 0;
u8 *para_buf = NULL;
struct rtw_para_info_t *para_info = (struct rtw_para_info_t *)para_info_t;
if (para_info->para_src == RTW_PARA_SRC_INTNAL) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s.parser_fun=NULL \n", file_name);
return;
}
if (!parser_fun || (!para_info->para_data)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s.parser_fun=NULL \n", file_name);
para_info->para_src = RTW_PARA_SRC_INTNAL;
return;
}
if ((para_info->para_data_len != 0) && (para_info->para_src == RTW_PARA_SRC_EXTNAL)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s. para_data_len != 0 !!!\n", file_name);
return;
}
para_buf = _os_mem_alloc(drv, MAX_HWCONFIG_FILE_CONTENT);
if (!para_buf) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "para_buf=NULL \n");
para_info->para_src = RTW_PARA_SRC_INTNAL;
return;
}
if (para_info->para_src == RTW_PARA_SRC_EXTNAL) {
_os_snprintf(para_info->para_path, MAX_PATH_LEN, "%s%s%s%s",
hal_phy_folder ,ic_name, _os_path_sep, file_name);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s:: %s\n",__FUNCTION__,
para_info->para_path);
para_size = _os_read_file(para_info->para_path, para_buf,
MAX_HWCONFIG_FILE_CONTENT);
} else if (para_info->para_src == RTW_PARA_SRC_CUSTOM) {
_os_mem_cpy(drv, para_buf, para_info->para_data, para_info->para_data_len);
_os_mem_set(drv, para_info->para_data, 0, para_info->para_data_len);
para_size = para_info->para_data_len;
para_info->para_data_len = 0;
}
if (para_size != 0) {
/* Parsing file content */
para_info->para_data_len = parser_fun(drv, para_info, para_buf,
para_size);
if (para_info->para_data_len) {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,
"%s:: Download file ok.\n", __FUNCTION__);
} else {
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_,
"%s:: Failed to parser %s\n",
__FUNCTION__, file_name);
para_info->para_src = RTW_PARA_SRC_INTNAL;
}
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s:: Download file ok.\n",
file_name);
} else {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "%s:: Error reading file.\n",
file_name);
para_info->para_src = RTW_PARA_SRC_INTNAL;
para_info->para_data_len = 0;
}
_os_mem_free(drv, para_buf, MAX_HWCONFIG_FILE_CONTENT);
#endif
}
enum rtw_hal_status
_phl_pwrlmt_para_alloc(struct rtw_phl_com_t* phl_com,
struct rtw_para_pwrlmt_info_t *para_info)
{
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (para_info->para_src == RTW_PARA_SRC_EXTNAL) {
u32 file_buf_sz = MAX_HWCONFIG_FILE_CONTENT;
u32 buf_sz = MAX_LINES_HWCONFIG_TXT;
void *drv = phl_com->drv_priv;
u8 para_regd_str_arridx;
const char * const *_para_regd_str = rtw_hal_rf_get_predefined_pw_lmt_regu_type_str_array(¶_regd_str_arridx);
u8 i = 0;
for (i = 0; i < para_regd_str_arridx ; i++) {
_os_strcpy(para_info->ext_regd_name[i] , _para_regd_str[i]);
PHL_INFO(" prepare ext_regd_name[%d] = %s",
i , para_info->ext_regd_name[i]);
}
para_info->ext_regd_arridx = para_regd_str_arridx;
para_info->para_data = _os_mem_alloc(drv, file_buf_sz * sizeof(u32));
if (!para_info->para_data) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_,
"%s::para_data allocmem fail\n",__FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
para_info->ext_reg_codemap = _os_mem_alloc(drv, buf_sz * sizeof(u8));
if (!para_info->ext_reg_codemap) {
if (para_info->para_data)
_os_mem_free(drv, para_info->para_data, file_buf_sz * sizeof(u32));
para_info->para_data = NULL;
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_,
"%s::ext_reg_codemap allocmem fail\n",__FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
} else
return RTW_HAL_STATUS_FAILURE;
#else
return RTW_HAL_STATUS_FAILURE;
#endif
}
enum rtw_hal_status
phl_load_file_data_alloc(struct rtw_phl_com_t* phl_com, struct rtw_para_info_t *para_info)
{
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
u32 buf_sz = MAX_HWCONFIG_FILE_CONTENT;
void *drv = phl_com->drv_priv;
if (para_info->para_src == RTW_PARA_SRC_EXTNAL) {
if (para_info->para_data_len == 0) {
para_info->para_data = _os_mem_alloc(drv, buf_sz * sizeof(u32));
}
if (!para_info->para_data) {
PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_,
"%s:: allocmem fail\n",__FUNCTION__);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
} else
return RTW_HAL_STATUS_FAILURE;
#else
return RTW_HAL_STATUS_FAILURE;
#endif
}
void
rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com,
char *ic_name, void *hal)
{
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
struct hal_info_t *hal_info = hal;
struct phy_sw_cap_t *phy_sw_cap = NULL;
u8 idx=0;
u8 max_phy_num = 1;
if (hal_info->hal_com->dbcc_en == true)
max_phy_num = 2;
for (idx=0; idx < max_phy_num; idx++) {/*Temp modiy for 1 BB phy Reg file */
phy_sw_cap = &phl_com->phy_sw_cap[idx];
if (phl_load_file_data_alloc(phl_com,
&phy_sw_cap->bb_phy_reg_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->bb_phy_reg_info,
ic_name,
_hal_parse_phyreg,
"PHY_REG.txt");
if (phl_load_file_data_alloc(phl_com,
&phy_sw_cap->bb_phy_reg_gain_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->bb_phy_reg_gain_info,
ic_name,
_hal_parse_phyreg,
"PHY_REG_GAIN.txt");
if (phl_load_file_data_alloc(phl_com,
&phy_sw_cap->rf_radio_a_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->rf_radio_a_info,
ic_name,
_hal_parse_radio,
"RadioA.txt");
if (phl_load_file_data_alloc(phl_com,
&phy_sw_cap->rf_radio_b_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->rf_radio_b_info,
ic_name,
_hal_parse_radio,
"RadioB.txt");
if (phl_load_file_data_alloc(phl_com,
&phy_sw_cap->rf_txpwr_byrate_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->rf_txpwr_byrate_info,
ic_name,
_hal_parse_txpwr_by_rate,
"TXPWR_ByRate.txt");
if (phl_load_file_data_alloc(phl_com,
&phy_sw_cap->rf_txpwrtrack_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->rf_txpwrtrack_info,
ic_name,
_hal_parse_txpwrtrack,
"TXPWR_TrackTSSI.txt");
if (_phl_pwrlmt_para_alloc(phl_com,
&phy_sw_cap->rf_txpwrlmt_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->rf_txpwrlmt_info,
ic_name,
_hal_parse_txpwrlmt,
"TXPWR_LMT.txt");
if (_phl_pwrlmt_para_alloc(phl_com,
&phy_sw_cap->rf_txpwrlmt_ru_info) == RTW_HAL_STATUS_SUCCESS)
_hal_dl_para_file(phl_com,
&phy_sw_cap->rf_txpwrlmt_ru_info,
ic_name,
_hal_parse_txpwrlmt_ru,
"TXPWR_LMT_RU.txt");
}
#endif
}
u8 rtw_hal_ld_fw_symbol(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, const char *name, u8 **buf, u32 *buf_size)
{
struct rtw_fw_info_t *fw_info = &phl_com->fw_info;
char path[256] = {0};
char *ic_name = NULL;
char *intf = NULL;
void *d = phlcom_to_drvpriv(phl_com);
switch (phl_com->hci_type) {
case RTW_HCI_PCIE:
intf = "e";
break;
case RTW_HCI_USB:
intf = "u";
break;
case RTW_HCI_SDIO:
intf = "s";
break;
default:
PHL_WARN("%s unknown hci type %u \n", __func__, phl_com->hci_type);
return (u8)RTW_HAL_STATUS_FAILURE;
}
switch (hal_com->chip_id) {
case CHIP_WIFI6_8852A:
ic_name = "rtl8852a";
break;
case CHIP_WIFI6_8852B:
ic_name = "rtl8852b";
break;
default:
PHL_WARN("%s unknown chip id %u \n", __func__, hal_com->chip_id);
return (u8)RTW_HAL_STATUS_FAILURE;
}
if (name == NULL || buf_size == NULL)
return (u8)RTW_HAL_STATUS_FAILURE;
if (!fw_info->sym_buf) {
fw_info->sym_buf = _os_mem_alloc(d, RTW_MAX_FW_SIZE);
if (!fw_info->sym_buf) {
PHL_WARN("%s : buf for fw symbol allocate fail!!\n", __func__);
return (u8)RTW_HAL_STATUS_FAILURE;
}
}
_os_snprintf(path, MAX_PATH_LEN, "%s%s%s%s%s", FW_FILE_CONFIG_PATH,
ic_name, intf, _os_path_sep, name);
PHL_INFO("%s : %s\n", __func__, path);
fw_info->sym_buf_size = _os_read_file(path, fw_info->sym_buf,
RTW_MAX_FW_SIZE);
/* reading fw file failed */
if (0 == fw_info->sym_buf_size)
return (u8)RTW_HAL_STATUS_FAILURE;
*buf = fw_info->sym_buf;
*buf_size = fw_info->sym_buf_size;
return (u8)RTW_HAL_STATUS_SUCCESS;
}
u8 rtw_hal_efuse_shadow_file_load(void *hal, char *ic_name, bool is_limit)
{
u8 status = true;
#ifdef CONFIG_EFUSE_CONFIG_FILE
struct rtw_hal_com_t *hal_com = (struct rtw_hal_com_t *)hal;
struct hal_info_t *hal_info = (struct hal_info_t *)hal_com->hal_priv;
char *hal_phy_folder = HAL_FILE_CONFIG_PATH;
char file_path[256];
_os_snprintf(file_path, MAX_PATH_LEN, "%s%s%s%s",
hal_phy_folder , ic_name, _os_path_sep, "efuse.map");
PHL_INFO("%s::open map path: %s\n", __FUNCTION__, file_path);
status = rtw_hal_efuse_file_map_load(hal_info, file_path, is_limit);
if (status == RTW_HAL_STATUS_FAILURE) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"%s:: %s FAIL\n", __FUNCTION__, file_path);
status = false;
goto exit;
}
_os_snprintf(file_path, MAX_PATH_LEN, "%s%s%s%s",
hal_phy_folder , ic_name, _os_path_sep, "efuse.mask");
PHL_INFO("%s::open mask path: %s\n", __FUNCTION__, file_path);
status = rtw_hal_efuse_file_mask_load(hal_info, file_path, is_limit);
if (status == RTW_HAL_STATUS_FAILURE) {
PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
"%s:: %s FAIL\n", __FUNCTION__, file_path);
status = false;
goto exit;
}
exit:
#endif
return status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ld_file.c
|
C
|
agpl-3.0
| 62,863
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_LD_FILE_H_
#define _HAL_LD_FILE_H_
#define PHYPG_BAND2G 0
#define PHYPG_BAND5G 1
#define PHYPG_RF1Tx 0
#define PHYPG_RF2Tx 1
#define PHYPG_OFFSET 15
enum PHY_PG_RATE_def {
CCK_11M_1M = 0,
OFDM_18M_6M = 1,
OFDM_54M_24M = 2,
HE1SS_MCS3_0 = 3,
HE1SS_MCS7_4 = 4,
HE1SS_MCS11_8 = 5,
HE1SS_DCM4_0 = 6,
HE2SS_MCS3_0 = 3,
HE2SS_MCS7_4 = 4,
HE2SS_MCS11_8 = 5,
HE2SS_DCM4_0 = 6,
Legacy_AllRate = 7,
HE_AllRate = 8,
};
struct _hal_file_regd_ext {
u16 domain;
char country[2];
char reg_name[10];
};
typedef struct hal_txpwr_lmt_t {
u8 band;
u8 bw;
u8 ntx;
u8 rs;
u8 bf;
u8 reg;
u8 ch;
s8 val;
u8 tx_shap_idx;
} HAL_TXPWR_LMT_T , *PHAL_TXPWR_LMT_T;
typedef struct hal_txpwr_lmt_ru_t {
u8 band;
u8 rubw;
u8 ntx;
u8 rs;
u8 reg;
u8 ch;
s8 val;
u8 tx_shap_idx;
} Hal_Txpwr_lmt_Ru_t , *pHal_Txpwr_lmt_Ru_t;
enum _halrf_tx_pw_lmt_ru_bandwidth_type {
_PW_LMT_RU_BW_RU26,
_PW_LMT_RU_BW_RU52,
_PW_LMT_RU_BW_RU106,
_PW_LMT_RU_BW_NULL
};
enum _halrf_pw_lmt_band_type {
_PW_LMT_BAND_2_4G = 0,
_PW_LMT_BAND_5G = 1
};
enum _halrf_pw_lmt_bandwidth_type {
_PW_LMT_BW_20M = 0,
_PW_LMT_BW_40M = 1,
_PW_LMT_BW_80M = 2,
_PW_LMT_BW_160M = 3,
_PW_LMT_MAX_BANDWIDTH_NUM = 4
};
enum _halrf_pw_lmt_ratesection_type {
_PW_LMT_RS_CCK = 0,
_PW_LMT_RS_OFDM = 1,
_PW_LMT_RS_HT = 2,
_PW_LMT_RS_VHT = 3,
_PW_LMT_RS_HE = 4,
_PW_LMT_MAX_RS_NUM = 5
};
enum _halrf_pw_lmt_rfpath_type {
_PW_LMT_PH_1T = 0,
_PW_LMT_PH_2T = 1,
_PW_LMT_PH_3T = 2,
_PW_LMT_PH_4T = 3,
_PW_LMT_MAX_PH_NUM = 4
};
enum _halrf_pw_lmt_beamforming_type {
_PW_LMT_NONBF = 0,
_PW_LMT_BF = 1,
_PW_LMT_MAX_BF_NUM = 2
};
/*@--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM 8
#define MAX_RF_PATH 4
#define DELTA_SWINGIDX_SIZE 30
#define BAND_NUM 4
#define DELTA_SWINTSSI_SIZE 61
/*@---------------------------End Define Parameters---------------------------*/
struct hal_txpwr_track_t {
/* u8 is_txpowertracking; */
u8 tx_powercount;
bool is_txpowertracking_init;
bool is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_path[MAX_RF_PATH];
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_avg_index_path[MAX_RF_PATH];
s8 power_index_offset_path[MAX_RF_PATH];
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
bool txpowertracking_in_progress;
bool is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset;
s8 delta_power_index;
s8 delta_power_index_path[MAX_RF_PATH];
s8 delta_power_index_last;
s8 delta_power_index_last_path[MAX_RF_PATH];
bool is_tx_power_changed;
/*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/
u8 delta_lck;
s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
u8 bb_swing_idx_ofdm_base;
u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
bool bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
bool bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
bool modify_tx_agc_flag_path_a;
bool modify_tx_agc_flag_path_b;
bool modify_tx_agc_flag_path_c;
bool modify_tx_agc_flag_path_d;
bool modify_tx_agc_flag_path_a_cck;
bool modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
void rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, char *ic_name, void *hal);
u8 rtw_hal_efuse_shadow_file_load(void *hal, char *ic_name, bool is_limit);
u8 rtw_hal_ld_fw_symbol(struct rtw_phl_com_t *phl_com,
struct rtw_hal_com_t *hal_com, const char *name, u8 **buf, u32 *buf_size);
#endif /*_HAL_LD_FILE_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ld_file.h
|
C
|
agpl-3.0
| 7,534
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_LED_C_
#include "hal_headers.h"
#define HAL_LED_GET_CTRL_MODE(m) \
((m) == RTW_LED_CTRL_SW_PP_MODE \
? MAC_AX_LED_MODE_SW_CTRL_PP \
: ((m) == RTW_LED_CTRL_SW_OD_MODE \
? MAC_AX_LED_MODE_SW_CTRL_OD \
: ((m) == RTW_LED_CTRL_HW_TX_MODE \
? MAC_AX_LED_MODE_TX_ON \
: ((m) == RTW_LED_CTRL_HW_RX_MODE \
? MAC_AX_LED_MODE_RX_ON \
: MAC_AX_LED_MODE_TRX_ON))))
#define HAL_LED_GET_ID(i) \
((i) == RTW_LED_ID_0 ? 0 : ((i) == RTW_LED_ID_1 ? 1 : 0))
enum rtw_hal_status rtw_hal_led_set_ctrl_mode(void *hal, enum rtw_led_id led_id,
enum rtw_led_ctrl_mode ctrl_mode)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_LED, _PHL_INFO_,
"%s: led_id == %d, ctrl_mode == %d\n", __func__, led_id,
ctrl_mode);
if (ctrl_mode == RTW_LED_CTRL_NOT_SUPPORT)
return RTW_HAL_STATUS_SUCCESS;
return rtw_hal_mac_led_set_ctrl_mode(
hal_info, HAL_LED_GET_CTRL_MODE(ctrl_mode), HAL_LED_GET_ID(led_id));
}
enum rtw_hal_status rtw_hal_led_control(void *hal, enum rtw_led_id led_id,
u8 high)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_LED, _PHL_INFO_, "===> hal_led_ctrl()\n");
if (high) {
PHL_TRACE(COMP_PHL_LED, _PHL_INFO_,
"hal_led_ctrl() : LED HIGH\n");
status =
rtw_hal_mac_led_ctrl(hal_info, 1, HAL_LED_GET_ID(led_id));
} else {
PHL_TRACE(COMP_PHL_LED, _PHL_INFO_,
"hal_led_ctrl() : LED LOW\n");
status =
rtw_hal_mac_led_ctrl(hal_info, 0, HAL_LED_GET_ID(led_id));
}
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_LED, _PHL_INFO_,
"hal_led_ctrl() : rtw_hal_mac_led_ctrl() failed\n");
}
return status;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_led.c
|
C
|
agpl-3.0
| 2,730
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_MCC_C_
#include "hal_headers.h"
#include "hal_mcc.h"
#ifdef CONFIG_MCC_SUPPORT
#define _mcc_fill_slot_bt_coex(_dbg_hal_i, _en) ((struct rtw_phl_mcc_dbg_hal_info *)_dbg_hal_i)->btc_in_group = _en;
void _mcc_update_slot_dbg_info(struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i,
bool bt_role, u16 macid, u16 dur)
{
struct rtw_phl_mcc_dbg_slot_info *dbg_slot_i = NULL;
u8 idx = 0;
for (idx = 0; idx < dbg_hal_i->slot_num; idx++) {
dbg_slot_i = &dbg_hal_i->dbg_slot_i[idx];
if (dbg_slot_i->bt_role) {
if (bt_role) {
dbg_slot_i->dur = dur;
break;
}
} else if (false == bt_role && dbg_slot_i->macid == macid) {
dbg_slot_i->dur = dur;
break;
}
}
}
void _mcc_update_dbg_info(struct rtw_phl_mcc_en_info *info,
struct rtw_phl_mcc_bt_info *bt_info)
{
u8 idx = 0;
if (bt_info->bt_dur > 0) {
_mcc_fill_slot_bt_coex(&info->dbg_hal_i, true);
} else {
_mcc_fill_slot_bt_coex(&info->dbg_hal_i, false);
}
for (idx = 0; idx < info->mrole_num; idx++) {
_mcc_update_slot_dbg_info(&info->dbg_hal_i, false,
info->mcc_role[idx].macid,
info->mcc_role[idx].policy.dur_info.dur);
}
}
void _mcc_fill_slot_dbg_info(struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i,
struct rtw_phl_mcc_role *mrole)
{
struct rtw_phl_mcc_dbg_slot_info *dbg_slot_i = NULL;
if (dbg_hal_i->slot_num >= SLOT_NUM) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_hal_dbg_info(): Fill fail, dbg_hal_i->slot_num(%d) >= SLOT_NUM(%d), please check code\n",
dbg_hal_i->slot_num, SLOT_NUM);
goto exit;
}
dbg_slot_i = &dbg_hal_i->dbg_slot_i[dbg_hal_i->slot_num];
dbg_slot_i->bt_role = mrole->bt_role ? true : false;
dbg_slot_i->dur = mrole->policy.dur_info.dur;
if (false == dbg_slot_i->bt_role) {
dbg_slot_i->ch = mrole->chandef->chan;
dbg_slot_i->macid = mrole->macid;
}
dbg_hal_i->slot_num++;
exit:
return;
}
enum rtw_hal_status _mcc_add_bt_role(struct hal_info_t *hal, u8 group,
struct rtw_phl_mcc_slot_info *slot_i,
struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_mcc_role mrole = {0};
mrole.policy.dur_info.dur = (u8)slot_i->slot;
mrole.bt_role = true;
mrole.group = group;
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_bt_role(): add bt role\n");
_mcc_fill_slot_dbg_info(dbg_hal_i, &mrole);
status = rtw_hal_mac_add_mcc(hal, &mrole);
return status;
}
enum rtw_hal_status _mcc_add_wifi_role(struct hal_info_t *hal,
u8 group, struct rtw_phl_mcc_slot_info *slot_i,
struct rtw_phl_mcc_dbg_hal_info *dbg_hal_i)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_mcc_role *mrole = slot_i->mrole;
if (NULL == mrole) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): Fail, NULL == mrole, Please check code\n");
goto exit;
}
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): add wifi role\n");
mrole->group = group;
_mcc_fill_slot_dbg_info(dbg_hal_i, mrole);
status = rtw_hal_mac_add_mcc(hal, mrole);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): Add mcc failed\n");
goto exit;
}
status = rtw_hal_mcc_update_macid_bitmap(hal, group,
(u8)mrole->macid,
&mrole->used_macid);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_add_wifi_role(): Add MACID bitmap failed\n");
goto exit;
}
exit:
return status;
}
enum rtw_hal_status _mcc_fill_role_setting(struct hal_info_t *hal,
struct rtw_phl_mcc_en_info *info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_mcc_slot_info *slot_i = info->m_pattern.slot_order;
u8 i = 0;
if (info->m_pattern.slot_num > SLOT_NUM) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Fial, slot_num(%d) > SLOT_NUM(%d), please check code\n",
info->m_pattern.slot_num, SLOT_NUM);
goto exit;
} else if (info->m_pattern.slot_num < MIN_TDMRA_SLOT_NUM) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Fial, slot_num(%d) < MIN_TDMRA_SLOT_NUM(%d), please check code\n",
info->m_pattern.slot_num, MIN_TDMRA_SLOT_NUM);
goto exit;
}
for (i = 0; i < info->m_pattern.slot_num; i++) {
if (!slot_i[i].bt_role) {
if (RTW_HAL_STATUS_SUCCESS!= _mcc_add_wifi_role(hal,
info->group, &slot_i[i], &info->dbg_hal_i)) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Add wifi role failed\n");
goto exit;
}
} else {
if (RTW_HAL_STATUS_SUCCESS != _mcc_add_bt_role(hal,
info->group, &slot_i[i], &info->dbg_hal_i)) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_fill_role_setting(): Add bt role failed\n");
goto exit;
}
}
}
status = RTW_HAL_STATUS_SUCCESS;
exit:
return status;
}
enum rtw_hal_status _mcc_replace_pattern(struct hal_info_t *hal,
struct rtw_phl_mcc_en_info *ori_info,
struct rtw_phl_mcc_en_info *new_info,
struct rtw_phl_mcc_bt_info *new_bt_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_mcc_role *ref_role =
&new_info->mcc_role[new_info->ref_role_idx];
bool btc_in_group = false;
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, ">>> _mcc_replace_pattern\n");
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_get_mcc_group(hal, &new_info->group)) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Allocate group fail\n");
goto exit;
}
_os_mem_set(hal_to_drvpriv(hal), &new_info->dbg_hal_i, 0,
sizeof(struct rtw_phl_mcc_dbg_hal_info));
status = _mcc_fill_role_setting(hal, new_info);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Fail fill role setting\n");
goto exit;
}
if (new_info->sync_tsf_info.sync_en) {
status = rtw_hal_mcc_sync_enable(hal, new_info);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Sync enable failed\n");
goto exit;
}
}
if (new_bt_info->bt_dur > 0) {
btc_in_group = true;
_mcc_fill_slot_bt_coex(&new_info->dbg_hal_i, true);
} else {
_mcc_fill_slot_bt_coex(&new_info->dbg_hal_i, false);
}
status = rtw_hal_mac_start_mcc(hal, new_info->group,
(u8)ref_role->macid, new_info->tsf_high,
new_info->tsf_low, btc_in_group, 1, ori_info->group);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_replace_pattern(): Start MCC failed\n");
goto exit;
}
status = RTW_HAL_STATUS_SUCCESS;
exit:
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "<<< _mcc_replace_pattern(): Ststus(%d)\n",
status);
return status;
}
enum rtw_hal_status rtw_hal_mcc_get_2ports_tsf(void *hal, u8 group,
u16 macid_x, u16 macid_y, u32 *tsf_x_h, u32 *tsf_x_l,
u32 *tsf_y_h, u32 *tsf_y_l)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_hal_mac_mcc_request_tsf(hal, group, (u8)macid_x, (u8)macid_y);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_get_2ports_tsf(): Req tsf failed\n");
goto exit;
}
status = rtw_hal_mac_get_mcc_tsf_rpt(hal, group, tsf_x_h, tsf_x_l,
tsf_y_h, tsf_y_l);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_get_2ports_tsf(): Get tsf rpt failed\n");
goto exit;
}
exit:
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_get_2ports_tsf(): Ststus(%d)\n",
status);
return status;
}
enum rtw_hal_status rtw_hal_mcc_update_macid_bitmap(void *hal, u8 group,
u16 macid, struct rtw_phl_mcc_macid_bitmap *info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_hal_mac_mcc_macid_bitmap(hal, group, (u8)macid,
(u8 *)info->bitmap, info->len);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_update_macid_bitmap(): Add MACID bitmap failed\n");
}
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_update_macid_bitmap(): Ststus(%d)\n",
status);
return status;
}
enum rtw_hal_status rtw_hal_mcc_sync_enable(void *hal,
struct rtw_phl_mcc_en_info *info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_mcc_role *ref_role = &info->mcc_role[info->ref_role_idx];
if (info->sync_tsf_info.sync_en) {
status = rtw_hal_mac_mcc_sync_enable(hal, ref_role->group,
(u8)info->sync_tsf_info.source,
(u8)info->sync_tsf_info.target,
(u8)info->sync_tsf_info.offset);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_sync_enable(): Sync enable failed\n");
goto exit;
}
} else {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_sync_enable(): sync_en == false, please check code\n");
goto exit;
}
status = RTW_HAL_STATUS_SUCCESS;
exit:
return status;
}
enum rtw_hal_status _mcc_set_duration(void *hal,
struct rtw_phl_mcc_en_info *info,
struct rtw_phl_mcc_bt_info *bt_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_hal_mac_set_duration(hal, info, bt_info);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "_mcc_set_duration(): set duration failed\n");
} else {
_mcc_update_dbg_info(info, bt_info);
}
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "_mcc_set_duration(): Ststus(%d)\n",
status);
return status;
}
enum rtw_hal_status rtw_hal_mcc_change_pattern(void *hal,
struct rtw_phl_mcc_en_info *ori_info,
struct rtw_phl_mcc_en_info *new_info,
struct rtw_phl_mcc_bt_info *new_bt_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
/* mcc_set_duration only can change 2 wifi slot,
otherwise we shall create new pattern and replace previous pattern*/
if (new_info->m_pattern.slot_num == 2 &&
new_info->m_pattern.bt_slot_num == 0 &&
ori_info->m_pattern.slot_num == 2 &&
ori_info->m_pattern.bt_slot_num == 0) {
status = _mcc_set_duration(hal, new_info, new_bt_info);
} else {
status = _mcc_replace_pattern(hal, ori_info, new_info,
new_bt_info);
}
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_change_pattern(): status(%d)\n",
status);
return status;
}
enum rtw_hal_status rtw_hal_mcc_disable(void *hal, u8 group, u16 macid)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
status = rtw_hal_mac_stop_mcc(hal, group, (u8)macid);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_disable(): Stop mcc failed\n");
goto exit;
}
status = rtw_hal_mac_del_mcc_group(hal, group);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_disable(): Delete group failed\n");
goto exit;
}
#ifdef RTW_WKARD_HALRF_MCC
rtw_hal_rf_dpk_switch(hal, true);
#endif /* RTW_WKARD_HALRF_MCC */
status = RTW_HAL_STATUS_SUCCESS;
exit:
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_disable(): Ststus(%d)\n",
status);
return status;
}
enum rtw_hal_status rtw_hal_mcc_enable(void *hal, struct rtw_phl_mcc_en_info *info,
struct rtw_phl_mcc_bt_info *bt_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct rtw_phl_mcc_role *ref_role = &info->mcc_role[info->ref_role_idx];
bool btc_in_group = false;
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_get_mcc_group(hal, &info->group)) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Allocate group fail\n");
goto exit;
}
#ifdef RTW_WKARD_HALRF_MCC
rtw_hal_rf_dpk_switch(hal, false);
#endif /* RTW_WKARD_HALRF_MCC */
if (RTW_HAL_STATUS_SUCCESS != _mcc_fill_role_setting(hal, info)) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Fail fill role setting\n");
goto exit;
}
/*fill start setting*/
if (info->sync_tsf_info.sync_en) {
status = rtw_hal_mcc_sync_enable(hal, info);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Sync enable failed\n");
goto exit;
}
}
if (bt_info->bt_dur > 0) {
btc_in_group = true;
_mcc_fill_slot_bt_coex(&info->dbg_hal_i, true);
} else {
_mcc_fill_slot_bt_coex(&info->dbg_hal_i, false);
}
status = rtw_hal_mac_start_mcc(hal, info->group,
(u8)ref_role->macid, info->tsf_high,
info->tsf_low, btc_in_group, 0, 0);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_mcc_enable(): Start MCC failed\n");
goto exit;
}
status = RTW_HAL_STATUS_SUCCESS;
exit:
PHL_TRACE(COMP_PHL_MCC, _PHL_INFO_, "rtw_hal_mcc_enable(): Ststus(%d)\n",
status);
return status;
}
#endif /* CONFIG_MCC_SUPPORT */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_mcc.c
|
C
|
agpl-3.0
| 12,924
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_MCC_H_
#define _HAL_MCC_H_
/* MCC definition for private usage */
#ifdef CONFIG_MCC_SUPPORT
enum rtw_hal_status rtw_hal_mcc_update_macid_bitmap(void *hal, u8 group,
u16 macid, struct rtw_phl_mcc_macid_bitmap *info);
enum rtw_hal_status rtw_hal_mcc_sync_enable(void *hal,
struct rtw_phl_mcc_en_info *info);
#endif /*CONFIG_MCC_SUPPORT*/
#endif /*_HAL_MCC_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_mcc.h
|
C
|
agpl-3.0
| 1,030
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_MCC_DEF_H_
#define _HAL_MCC_DEF_H_
/* MCC definition for public usage in hal layer */
#endif /*_HAL_MCC_DEF_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_mcc_def.h
|
C
|
agpl-3.0
| 776
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_NOTIFY_C_
#include "hal_headers.h"
void rtw_hal_notification(void *hal, enum phl_msg_evt_id event, u8 hw_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 idx = 0;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: event(%d), hw_idx(%d)\n",
__func__, event, hw_idx);
if (hw_idx == HW_BAND_MAX) {
for (idx = 0; idx < hw_idx; idx++) {
rtw_hal_bb_notification(hal_info, event, idx);
rtw_hal_mac_notification(hal_info, event, idx);
rtw_hal_rf_notification(hal_info, event, idx);
}
} else {
rtw_hal_bb_notification(hal_info, event, hw_idx);
rtw_hal_mac_notification(hal_info, event, hw_idx);
rtw_hal_rf_notification(hal_info, event, idx);
}
}
void rtw_hal_cmd_notification(void *hal,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
if (event == MSG_EVT_NOTIFY_BB)
rtw_hal_bb_cmd_notification(hal_info, hal_cmd, hw_idx);
else if (event == MSG_EVT_NOTIFY_RF)
rtw_hal_rf_cmd_notification(hal_info, hal_cmd, hw_idx);
else if (event == MSG_EVT_NOTIFY_MAC)
rtw_hal_mac_cmd_notification(hal_info, hal_cmd, hw_idx);
else
PHL_ERR("%s unexpect eve id = 0x%x\n", __func__, event);
}
enum rtw_phl_status
rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx)
{
#ifdef CONFIG_CMD_DISP
return rtw_phl_cmd_notify(phl_com, event, hal_cmd, hw_idx);
#else
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: not support cmd notify\n",
__func__);
return RTW_PHL_STATUS_FAILURE;
#endif /* CONFIG_CMD_DISP */
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_notify.c
|
C
|
agpl-3.0
| 2,375
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_NOTIFY_H_
#define _HAL_NOTIFY_H_
void rtw_hal_notification(void *hal, enum phl_msg_evt_id event, u8 hw_idx);
void rtw_hal_cmd_notification(void *hal,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx);
enum rtw_phl_status
rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com,
enum phl_msg_evt_id event,
void *hal_cmd,
u8 hw_idx);
#endif /*_HAL_NOTIFY_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_notify.h
|
C
|
agpl-3.0
| 1,137
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_P2PPS_C_
#include "hal_headers.h"
#ifdef CONFIG_PHL_P2PPS
#define TSF32_TOG_EARLY_T 2000 /*2ms*/
enum rtw_hal_status rtw_hal_noa_enable(void *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid)
{
enum rtw_hal_status ret = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 cur_en_desc_num = noa_info->en_desc_num;
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]%s: macid(0x%x), cur_en_desc_num(%d)\n",
__func__, macid, cur_en_desc_num);
if (cur_en_desc_num == 0) {
ret = rtw_hal_mac_noa_init(hal_info, noa_info, in_desc, macid);
} else {
ret = rtw_hal_mac_noa_update(hal_info, noa_info, in_desc, macid);
}
return ret;
}
enum rtw_hal_status rtw_hal_noa_disable(void *hal,
struct rtw_phl_noa_info *noa_info,
struct rtw_phl_noa_desc *in_desc,
u16 macid)
{
enum rtw_hal_status ret = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 cur_en_desc_num = noa_info->en_desc_num;
PHL_TRACE(COMP_PHL_P2PPS, _PHL_INFO_, "[NoA]%s(): cur_en_desc_num(%d)\n",
__func__, cur_en_desc_num);
if (cur_en_desc_num == 1) {
ret = rtw_hal_mac_noa_terminate(hal_info, noa_info, in_desc,
macid);
} else {
ret = rtw_hal_mac_noa_remove(hal_info, noa_info, in_desc, macid);
}
return ret;
}
enum rtw_hal_status rtw_hal_tsf32_tog_enable(void *hal,
struct rtw_wifi_role_t *w_role)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = hal;
h_stat = rtw_hal_mac_tsf32_tog_enable(hal_info, w_role->hw_band,
w_role->hw_port,
TSF32_TOG_EARLY_T);
return h_stat;
}
enum rtw_hal_status rtw_hal_tsf32_tog_disable(void *hal,
struct rtw_wifi_role_t *w_role)
{
enum rtw_hal_status h_stat = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = hal;
h_stat = rtw_hal_mac_tsf32_tog_disable(hal_info, w_role->hw_band,
w_role->hw_port);
return h_stat;
}
enum rtw_hal_status rtw_hal_get_tsf32_tog_rpt(void *hal,
struct rtw_phl_tsf32_tog_rpt *rpt)
{
struct hal_info_t *hal_info = hal;
return rtw_hal_mac_get_tsf32_tog_rpt(hal_info, rpt);
}
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_p2pps.c
|
C
|
agpl-3.0
| 2,766
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_PCI_C_
#include "hal_headers.h"
#ifdef CONFIG_PCI_HCI
static u8 pci_read8(struct rtw_hal_com_t *hal, u32 addr)
{
return _os_read8_pcie(hal->drv_priv, addr);
}
static u16 pci_read16(struct rtw_hal_com_t *hal, u32 addr)
{
return _os_read16_pcie(hal->drv_priv, addr);
}
static u32 pci_read32(struct rtw_hal_com_t *hal, u32 addr)
{
return _os_read32_pcie(hal->drv_priv, addr);
}
static int pci_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
{
return _os_write8_pcie(hal->drv_priv, addr, val);
}
static int pci_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
{
return _os_write16_pcie(hal->drv_priv, addr, val);
}
static int pci_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
{
return _os_write32_pcie(hal->drv_priv, addr, val);
}
#ifdef RTW_WKARD_BUS_WRITE
static int pci_write_post_cfg(struct rtw_hal_com_t *hal, u32 addr, u32 val)
{
struct hal_info_t *hal_info = hal->hal_priv;
struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
if(NULL != hal_ops->write_reg_post_cfg) {
hal_status = hal_ops->write_reg_post_cfg(hal_info, addr, val);
}
return hal_status;
}
#endif
void hal_pci_set_io_ops(struct rtw_hal_com_t *hal, struct hal_io_ops *pops)
{
/*_rtw_memset((u8 *)pops, 0, sizeof(struct hal_io_ops));*/
_os_mem_set(hal->drv_priv, (u8 *)pops, 0, sizeof(struct hal_io_ops));
pops->_read8 = &pci_read8;
pops->_read16 = &pci_read16;
pops->_read32 = &pci_read32;
pops->_write8 = &pci_write8;
pops->_write16 = &pci_write16;
pops->_write32 = &pci_write32;
#ifdef RTW_WKARD_BUS_WRITE
pops->_write_post_cfg = &pci_write_post_cfg;
#endif
}
enum rtw_hal_status rtw_hal_set_l2_leave(void *hal)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
/* Only AON registers are accessed */
status = hal_mac_set_l2_leave(hal_info);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s : fail\n", __func__);
}
return status;
}
void rtw_hal_clear_bdidx(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
FUNCIN();
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_clr_bdidx(hal_info))
PHL_ERR("%s failure \n", __func__);
}
void rtw_hal_rst_bdram(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
FUNCIN();
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_rst_bdram(hal_info))
PHL_ERR("%s failure \n", __func__);
}
void rtw_hal_cfg_dma_io(void *hal, u8 en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %u.\n", __func__, en);
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_dma_io(hal_info, en))
PHL_ERR("%s failure \n", __func__);
}
#ifdef RTW_WKARD_DYNAMIC_LTR
enum rtw_hal_status
rtw_hal_ltr_en_hw_mode(void *hal, bool hw_mode)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
status = rtw_hal_mac_ltr_set_pcie(hal_info,
hw_mode ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE_BUS_FUNC_DISABLE,
0, 0, 0, 0);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("%s : fail\n", __func__);
return status;
}
return status;
}
enum rtw_hal_status
rtw_hal_ltr_sw_trigger(void *hal, enum rtw_pcie_ltr_state state)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
status = rtw_hal_mac_ltr_sw_trigger(hal_info, state);
if (status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("%s : fail\n", __func__);
return status;
}
void rtw_hal_ltr_update_stats(void *hal, bool clear)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_trx_stat *trx_stat = &hal_info->hal_com->trx_stat;
static u32 dly_start_time = 0;
if(clear) {
dly_start_time = 0;
} else {
/* first in */
if (dly_start_time == 0) {
dly_start_time = _os_get_cur_time_us();
trx_stat->ltr_last_tx_dly_time = 0;
}
trx_stat->ltr_tx_dly_count++;
trx_stat->ltr_last_tx_dly_time =
phl_get_passing_time_us(dly_start_time);
}
}
bool rtw_hal_ltr_is_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct bus_cap_t *bus_cap = &hal_info->hal_com->bus_cap;
return bus_cap->ltr_sw_ctrl ?
(phl_com->bus_sw_cap.ltr_sw_ctrl ? true : false) : false;
}
bool rtw_hal_ltr_is_hw_ctrl(struct rtw_phl_com_t *phl_com, void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct bus_cap_t *bus_cap = &hal_info->hal_com->bus_cap;
return bus_cap->ltr_hw_ctrl ?
(phl_com->bus_sw_cap.ltr_hw_ctrl ? true : false) : false;
}
#endif
#endif /*CONFIG_PCI_HCI*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_pci.c
|
C
|
agpl-3.0
| 5,260
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_PCI_H_
#define _HAL_PCI_H_
#ifdef CONFIG_PCI_HCI
void hal_pci_set_io_ops(struct rtw_hal_com_t *hal, struct hal_io_ops *pops);
#ifdef CONFIG_RTL8852A
#include "rtl8852a/rtl8852a.h"
#endif
#ifdef CONFIG_RTL8852B
#include "rtl8852b/rtl8852b.h"
#endif
#ifdef CONFIG_RTL8852C
#include "rtl8852c/rtl8852c.h"
#endif
static inline void hal_set_ops_pci(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal)
{
#ifdef CONFIG_RTL8852A
if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852A) {
hal_set_ops_8852ae(phl_com, hal);
hal_hook_trx_ops_8852ae(phl_com, hal);
}
#endif
#ifdef CONFIG_RTL8852B
if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852B) {
hal_set_ops_8852be(phl_com, hal);
hal_hook_trx_ops_8852be(phl_com, hal);
}
#endif
#ifdef CONFIG_RTL8852C
if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852C) {
hal_set_ops_8852ce(phl_com, hal);
hal_hook_trx_ops_8852ce(phl_com, hal);
}
#endif
/*
else if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8834A)
rtl8834ae_set_hal_ops(hal);
else if (hal_get_chip_id(hal->hal_com) == CHIP_WIFI6_8852B)
rtl8852be_set_hal_ops(hal);
*/
}
#endif /*CONFIG_PCI_HCI*/
#endif /*_HAL_PCI_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_pci.h
|
C
|
agpl-3.0
| 1,821
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_PS_C_
#include "hal_headers.h"
#ifdef CONFIG_POWER_SAVE
#define case_pwr_state(src) \
case PS_PWR_STATE_##src: return #src
const char *hal_ps_pwr_state_to_str(u8 pwr_state)
{
switch (pwr_state) {
case_pwr_state(ACTIVE);
case_pwr_state(BAND0_RFON);
case_pwr_state(BAND1_RFON);
case_pwr_state(BAND0_RFOFF);
case_pwr_state(BAND1_RFOFF);
case_pwr_state(CLK_GATED);
case_pwr_state(PWR_GATED);
case_pwr_state(MAX);
default:
return "Undefined";
}
}
#define LPS_PROTOCAL_LEAVE_TOLERANCE 50 /* ms */
#define PWR_LVL_CHANGE_TOLERANCE 50 /* ms */
#define MAX_CHK_PWR_STATE_CHANGE_CNT 5
static enum rtw_hal_status
_hal_ps_lps_chk_leave(struct hal_info_t *hal_info, u16 macid)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
u32 mac_sts = 0;
u32 priv_mac_sts = 0;
u32 start_time = _os_get_cur_time_ms();
u32 pass_time = 0;
do {
status = rtw_hal_mac_lps_chk_leave(hal_info, macid, &mac_sts);
if (status == RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_,
"[HALPS], %s(): pass time = %d ms.\n",
__func__, pass_time);
break;
}
if (mac_sts != priv_mac_sts) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_,
"[HALPS], %s(): mac status %u.\n",
__func__, mac_sts);
priv_mac_sts = mac_sts;
}
pass_time = phl_get_passing_time_ms(start_time);
if (pass_time > LPS_PROTOCAL_LEAVE_TOLERANCE)
break;
_os_sleep_us(hal_to_drvpriv(hal_info), 50);
} while (1);
rtw_hal_fw_dbg_dump(hal_info, false);
if (status != RTW_HAL_STATUS_SUCCESS)
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): polling timeout!\n", __func__);
return status;
}
static enum rtw_hal_status
_hal_ps_lps_cfg(struct hal_info_t *hal_info,
struct rtw_hal_lps_info *lps_info)
{
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_,
"[HALPS], %s(): mode(%d), listen bcn mode(%d), awake interval(%d), smart_ps_mode(%d).\n",
__func__, lps_info->lps_en, lps_info->listen_bcn_mode,
lps_info->awake_interval, lps_info->smart_ps_mode);
return rtw_hal_mac_lps_cfg(hal_info, lps_info);
}
static enum rtw_hal_status
_hal_ps_pwr_state_chk(struct hal_info_t *hal_info, u8 req_pwr_state)
{
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
u32 mac_sts = 0;
u32 priv_mac_sts = 0;
u32 start_time = _os_get_cur_time_ms();
u32 pass_time = 0;
do {
status = rtw_hal_mac_chk_pwr_state(hal_info, req_pwr_state, &mac_sts);
if (status == RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_,
"[HALPS], %s(): pass time = %d ms.\n",
__func__, pass_time);
break;
}
if (mac_sts != priv_mac_sts) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_,
"[HALPS], %s(): mac status %u.\n",
__func__, mac_sts);
priv_mac_sts = mac_sts;
}
pass_time = phl_get_passing_time_ms(start_time);
if (pass_time > PWR_LVL_CHANGE_TOLERANCE)
break;
_os_sleep_us(hal_to_drvpriv(hal_info), 50);
} while (1);
rtw_hal_fw_dbg_dump(hal_info, true);
if (status != RTW_HAL_STATUS_SUCCESS)
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): polling timeout!\n", __func__);
return status;
}
static enum rtw_hal_status
_hal_ps_cfg_pwr_state(struct hal_info_t *hal_info, u8 req_pwr_state)
{
#if (HAL_LPS_SKIP_HW_CFG == 0)
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
u8 cnt = 0;
for (cnt = 0; cnt < MAX_CHK_PWR_STATE_CHANGE_CNT; cnt++) {
/* rpwm */
status = rtw_hal_mac_req_pwr_state(hal_info, req_pwr_state);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_,
"[HALPS], %s(): set pwr state %s fail!\n",
__func__, hal_ps_pwr_state_to_str(req_pwr_state));
return RTW_HAL_STATUS_FAILURE;
}
/* cpwm */
status = _hal_ps_pwr_state_chk(hal_info, req_pwr_state);
if (status == RTW_HAL_STATUS_SUCCESS)
break;
}
if (cnt < MAX_CHK_PWR_STATE_CHANGE_CNT) {
PHL_TRACE(COMP_PHL_PS, _PHL_INFO_,
"[HALPS], %s(): chk pwr state %s success, cnt %d.\n",
__func__, hal_ps_pwr_state_to_str(req_pwr_state), cnt);
return RTW_HAL_STATUS_SUCCESS;
} else {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_,
"[HALPS], %s(): chk pwr state %s fail!\n",
__func__, hal_ps_pwr_state_to_str(req_pwr_state));
return RTW_HAL_STATUS_FAILURE;
}
#else
return RTW_HAL_STATUS_SUCCESS;
#endif
}
static enum rtw_hal_status
_hal_ps_cfg_pwr_on(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_phl_evt_ops *ops = &phl_com->evt_ops;
enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
if (hal_info->hal_com->is_hal_init) {
#if (HAL_LPS_SKIP_HW_CFG == 0)
status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_ACTIVE);
#else
status = RTW_HAL_STATUS_SUCCESS;
#endif
} else {
#if (HAL_IPS_SKIP_HW_CFG == 0)
if (ops->set_rf_state(phlcom_to_drvpriv(phl_com), RTW_RF_ON) == true)
status = RTW_HAL_STATUS_SUCCESS;
else
status = RTW_HAL_STATUS_FAILURE;
#else
status = RTW_HAL_STATUS_SUCCESS;
#endif
}
return status;
}
static enum rtw_hal_status
_hal_ps_cfg_pwr_off(struct rtw_phl_com_t *phl_com,
struct hal_info_t *hal_info)
{
struct rtw_phl_evt_ops *ops = &phl_com->evt_ops;
#if (HAL_IPS_SKIP_HW_CFG == 0)
if (ops->set_rf_state(phlcom_to_drvpriv(phl_com), RTW_RF_OFF) == true)
return RTW_HAL_STATUS_SUCCESS;
else
return RTW_HAL_STATUS_FAILURE;
#else
return RTW_HAL_STATUS_SUCCESS;
#endif
}
static enum rtw_hal_status
_hal_ps_pwr_lvl_cfg(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
u8 req_pwr_lvl)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
switch (req_pwr_lvl) {
case PS_PWR_LVL_PWROFF:
status = _hal_ps_cfg_pwr_off(phl_com, hal_info);
break;
case PS_PWR_LVL_PWR_GATED:
status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_PWR_GATED);
break;
case PS_PWR_LVL_CLK_GATED:
status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_CLK_GATED);
break;
case PS_PWR_LVL_RF_OFF:
status = _hal_ps_cfg_pwr_state(hal_info, PS_PWR_STATE_BAND0_RFOFF);
break;
case PS_PWR_LVL_PWRON:
status = _hal_ps_cfg_pwr_on(phl_com, hal_info);
break;
default:
PHL_TRACE(COMP_PHL_PS, _PHL_WARNING_, "[HALPS], %s(): undefined pwr lvl!\n", __func__);
break;
}
return status;
}
/**
* configured requested power level
* return success if configure power level ok
* @phl_com: see rtw_phl_com_t
* @hal: see hal_info_t
* @req_pwr_lvl: target power level to configured
*/
enum rtw_hal_status
rtw_hal_ps_pwr_lvl_cfg(struct rtw_phl_com_t *phl_com, void *hal,
u8 req_pwr_lvl)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
status = _hal_ps_pwr_lvl_cfg(phl_com, hal_info, req_pwr_lvl);
if (status != RTW_HAL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): pwr lvl cfg fail!\n", __func__);
}
return status;
}
/**
* configure the legacy power save (protocol)
* return configure lps fail or not
* @hal: see hal_info_t
* @lps: see rtw_hal_lps_info
*/
enum rtw_hal_status
rtw_hal_ps_lps_cfg(void *hal, struct rtw_hal_lps_info *lps_info)
{
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
status = _hal_ps_lps_cfg(hal_info, lps_info);
if (status == RTW_HAL_STATUS_SUCCESS) {
if (lps_info->lps_en == false)
status = _hal_ps_lps_chk_leave(hal_info, lps_info->macid);
}
return status;
}
enum rtw_hal_status rtw_hal_ps_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req)
{
enum rtw_phl_status status = RTW_PHL_STATUS_FAILURE;
status = phl_ps_hal_pwr_req(phl_com, src, pwr_req);
if (status != RTW_PHL_STATUS_SUCCESS) {
PHL_TRACE(COMP_PHL_PS, _PHL_ERR_, "[HALPS], %s(): fail (pwr_req %d).\n", __func__, pwr_req);
return RTW_HAL_STATUS_FAILURE;
}
return RTW_HAL_STATUS_SUCCESS;
}
#endif /* CONFIG_POWER_SAVE */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ps.c
|
C
|
agpl-3.0
| 8,315
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_PS_H_
#define _HAL_PS_H_
#ifdef CONFIG_POWER_SAVE
/* Can be used to verify sw flow without configure hw */
#define HAL_LPS_SKIP_HW_CFG 0
#define HAL_IPS_SKIP_HW_CFG 0
enum rtw_hal_status rtw_hal_ps_pwr_req(struct rtw_phl_com_t *phl_com, u8 src, bool pwr_req);
#endif
#endif /*_HAL_PS_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ps.h
|
C
|
agpl-3.0
| 952
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_REGULATION_C_
#include "hal_headers.h"
bool rtw_hal_query_regulation(void *phl, struct rtw_regulation_info *info)
{
return rtw_phl_query_regulation_info(phl, info);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_regulation.c
|
C
|
agpl-3.0
| 833
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_RX_C_
#include "hal_headers.h"
void rtw_hal_cfg_rxhci(void *hal, u8 en)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en);
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_rxhci(hal_info, en))
PHL_ERR("%s failure \n", __func__);
}
enum rtw_hal_status
rtw_hal_set_rxfltr_by_mode(void *hal, u8 band, enum rtw_rx_fltr_mode mode)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
enum rtw_rx_fltr_mode set_mode = -1;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : band(%d), mode(%d)\n",
__func__, band, mode);
/* Note: @hal_info_t.rx_fltr_mode is used to recored any mode other than
* sniffer mode, it effectively records the mode before entering monitor
* mode and the subsequent modes set after entering monitor mode.
*/
if ((mode == RX_FLTR_MODE_SNIFFER && hal_info->monitor_mode) ||
(mode == RX_FLTR_MODE_RESTORE && !hal_info->monitor_mode))
return RTW_HAL_STATUS_FAILURE;
if (hal_info->monitor_mode && mode != RX_FLTR_MODE_RESTORE) {
hal_info->rx_fltr_mode = mode;
return RTW_HAL_STATUS_SUCCESS;
}
set_mode = (mode == RX_FLTR_MODE_RESTORE) ?
hal_info->rx_fltr_mode : mode;
hstatus = rtw_hal_mac_set_rxfltr_by_mode(hal_com, band, set_mode);
if (hstatus != RTW_HAL_STATUS_SUCCESS)
return hstatus;
hal_info->monitor_mode = (mode == RX_FLTR_MODE_SNIFFER);
/* Record @hal_info_t.rx_fltr_mode only when the mode is not monitor and
* restore, otherwise, it is kept intact.
* TODO: The rx fltr mode should be recorded separately for each band.
*/
if (mode != RX_FLTR_MODE_SNIFFER &&
mode != RX_FLTR_MODE_RESTORE)
hal_info->rx_fltr_mode = mode;
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_rx_fltr_mode rtw_hal_get_rxfltr_mode(void *hal, u8 band)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return (hal_info->monitor_mode) ? RX_FLTR_MODE_SNIFFER :
hal_info->rx_fltr_mode;
}
enum rtw_hal_status rtw_hal_scan_set_rxfltr_by_mode(void *hinfo,
enum phl_phy_idx phy_idx, bool off_channel, u8 *mode)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
if (off_channel) {
/* backup rx filter mode */
*mode = rtw_hal_get_rxfltr_mode(hinfo, phy_idx);
hal_status = rtw_hal_set_rxfltr_by_mode(hinfo,
phy_idx, RX_FLTR_MODE_SCAN);
} else {
/* restore rx filter mode */
hal_status = rtw_hal_set_rxfltr_by_mode(hinfo,
phy_idx, *mode);
}
return hal_status;
}
enum rtw_hal_status
rtw_hal_enter_mon_mode(void *hinfo, enum phl_phy_idx phy_idx)
{
return rtw_hal_set_rxfltr_by_mode(hinfo, phy_idx, RX_FLTR_MODE_SNIFFER);
}
enum rtw_hal_status
rtw_hal_leave_mon_mode(void *hinfo, enum phl_phy_idx phy_idx)
{
return rtw_hal_set_rxfltr_by_mode(hinfo, phy_idx, RX_FLTR_MODE_RESTORE);
}
enum rtw_hal_status rtw_hal_acpt_crc_err_pkt(void *hal, u8 band, u8 enable)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return rtw_hal_mac_set_rxfltr_acpt_crc_err(hal_com, band, enable);
}
enum rtw_hal_status rtw_hal_set_rxfltr_mpdu_size(void *hal, u8 band, u16 size)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
return rtw_hal_mac_set_rxfltr_mpdu_size(hal_com, band, size);
}
enum rtw_hal_status rtw_hal_set_rxfltr_by_type(void *hal, u8 band, u8 type, u8 target)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hstats = RTW_HAL_STATUS_FAILURE;
hstats = rtw_hal_mac_set_rxfltr_by_type(hal_info->hal_com, band, type, target);
if (RTW_HAL_STATUS_SUCCESS != hstats)
PHL_ERR("%s : type %u status %u target %u.band %u \n", __func__, type, hstats, target, band);
return hstats;
}
enum rtw_hal_status
rtw_hal_poll_hw_rx_done(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
sts = rtw_hal_mac_poll_hw_rx_done(hal_info);
return sts;
}
enum rtw_hal_status
rtw_hal_hw_rx_resume(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
sts = rtw_hal_mac_hw_rx_resume(hal_info);
return sts;
}
#ifdef CONFIG_PCI_HCI
/**
* rtw_hal_rx_res_query - query current HW rx resource with specifc dma channel
* @hal: see struct hal_info_t
* @dma_ch: the target dma channel
* @host_idx: current host index of this channel
* @hw_idx: current hw index of this channel
*
* this function returns the number of available tx resource
* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
*/
u16 rtw_hal_rx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u16 res_num = 0;
res_num = trx_ops->query_rx_res(hal_info->hal_com, dma_ch, host_idx,
hw_idx);
return res_num;
}
/**
* rtw_hal_query_rxch_num - query total hw rx dma channels number
*
* returns the number of hw rx dma channel
*/
u8 rtw_hal_query_rxch_num(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u8 ch_num = 0;
ch_num = trx_ops->query_rxch_num();
return ch_num;
}
u8 rtw_hal_check_rxrdy(struct rtw_phl_com_t *phl_com, void* hal, u8 *rxbuf, u8 dma_ch)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u8 res = 0;
res = trx_ops->check_rxrdy(phl_com, rxbuf, dma_ch);
return res;
}
u8 rtw_hal_handle_rxbd_info(void* hal, u8 *rxbuf, u16 *buf_size)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u8 res = 0;
res = trx_ops->handle_rxbd_info(hal_info, rxbuf, buf_size);
return res;
}
enum rtw_hal_status
rtw_hal_update_rxbd(void *hal, struct rx_base_desc *rxbd,
struct rtw_rx_buf *rxbuf)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->update_rxbd(hal_info, rxbd, rxbuf);
return hstatus;
}
enum rtw_hal_status rtw_hal_notify_rxdone(void* hal,
struct rx_base_desc *rxbd, u8 ch, u16 rxcnt)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->notify_rxdone(hal_info, rxbd, ch, rxcnt);
return hstatus;
}
u16 rtw_hal_handle_wp_rpt(void *hal, u8 *rp, u16 len, u8 *sw_retry, u8 *dma_ch,
u16 *wp_seq, u8 *txsts)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u16 rsize = 0;
rsize = trx_ops->handle_wp_rpt(hal_info, rp, len, sw_retry, dma_ch,
wp_seq, txsts);
return rsize;
}
#endif /*CONFIG_PCI_HCI*/
#ifdef CONFIG_USB_HCI
enum rtw_hal_status
rtw_hal_query_info(void* hal, u8 info_id, void *value)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->query_hal_info(hal_info, info_id, value);
return hstatus;
}
enum rtw_hal_status
rtw_hal_usb_rx_agg_cfg(void *hal, u8 mode, u8 agg_mode,
u8 drv_define, u8 timeout, u8 size, u8 pkt_num)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->usb_rx_agg_cfg(hal, mode, agg_mode,
drv_define, timeout, size, pkt_num);
return hstatus;
}
u16 rtw_hal_handle_wp_rpt_usb(void *hal, u8 *rp, u16 len, u8 *macid, u8 *ac_queue,
u8 *txsts)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
u16 rsize = 0;
rsize = trx_ops->handle_wp_rpt(hal_info, rp, len, macid, ac_queue, txsts);
return rsize;
}
#endif
enum rtw_hal_status
rtw_hal_handle_rx_buffer(struct rtw_phl_com_t *phl_com, void* hal,
u8 *buf, u32 buf_size,
struct rtw_phl_rx_pkt *rxpkt)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_trx_ops *trx_ops = hal_info->trx_ops;
hstatus = trx_ops->handle_rx_buffer(phl_com, hal_info,
buf, buf_size, rxpkt);
return hstatus;
}
#ifdef CONFIG_SDIO_HCI
void rtw_hal_sdio_rx_agg_cfg(void *hal, bool enable, u8 drv_define,
u8 timeout, u8 size, u8 pkt_num)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
rtw_hal_mac_sdio_rx_agg_cfg(hal_info->hal_com, enable, drv_define,
timeout, size, pkt_num);
}
int rtw_hal_sdio_rx(void *hal, struct rtw_rx_buf *rxbuf)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_sdio_rx(hal_info->hal_com, rxbuf);
}
int rtw_hal_sdio_parse_rx(void *hal, struct rtw_rx_buf *rxbuf)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_sdio_parse_rx(hal_info->hal_com, rxbuf);
}
#endif /* CONFIG_SDIO_HCI */
void
hal_rx_ppdu_sts_normal_data(struct rtw_phl_com_t *phl_com,
void *hdr,
struct rtw_r_meta_data *meta)
{
struct rtw_phl_ppdu_sts_info *ppdu_info = NULL;
enum phl_band_idx band = HW_BAND_0;
do {
if ((NULL == phl_com) || (NULL == meta))
break;
ppdu_info = &phl_com->ppdu_sts_info;
band = (meta->bb_sel > 0) ? HW_BAND_1 : HW_BAND_0;
if ((ppdu_info->cur_rx_ppdu_cnt[band] == meta->ppdu_cnt) &&
(false == ppdu_info->latest_rx_is_psts[band])) {
/**
* add condition to avoid check fail for ppdu cnt run around 0 -> 1 -> ... -> 0
* example :
* [frame_A(ppdu_cnt = 0)] -> [ppdu_sts(ppdu_cnt = 0)]
* ->[ppdu_sts(ppdu_cnt = 1)] -> [ppdu_sts(ppdu_cnt = 2)] ...
* ... ->[ppdu_sts(ppdu_cnt = 7)] -> [frame_B(ppdu_cnt = 0)] ...
* Therefore, frame_B has same ppdu_cnt with frame_A.
* But they are different PPDU.
**/
break;
}
meta->ppdu_cnt_chg = true;
/* start of the PPDU */
ppdu_info->latest_rx_is_psts[band] = false;
ppdu_info->sts_ent[band][meta->ppdu_cnt].addr_cam_vld = meta->addr_cam_vld;
ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type = PHL_GET_80211_HDR_TYPE(hdr);
ppdu_info->sts_ent[band][meta->ppdu_cnt].crc32 = meta->crc32;
ppdu_info->sts_ent[band][meta->ppdu_cnt].rx_rate = meta->rx_rate;
ppdu_info->sts_ent[band][meta->ppdu_cnt].ppdu_type = meta->ppdu_type;
if(RTW_IS_BEACON_OR_PROBE_RESP_PKT(ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type)) {
PHL_GET_80211_HDR_ADDRESS3(phl_com->drv_priv, hdr,
ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr);
}
else if (meta->a1_match &&
RTW_IS_ASOC_REQ_PKT(ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type)) {
PHL_GET_80211_HDR_ADDRESS2(phl_com->drv_priv, hdr,
ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr);
#ifdef DBG_AP_CLIENT_ASSOC_RSSI
{
u8 *src = NULL;
src = ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr;
PHL_INFO("%s [Rx-ASOC_REQ] - MAC-Addr:%02x-%02x-%02x-%02x-%02x-%02x, a1_match:%d ppdu_cnt:%d\n",
__func__,
src[0], src[1], src[2], src[3], src[4], src[5],
meta->a1_match,
meta->ppdu_cnt);
}
#endif
}
else {
_os_mem_cpy(phl_com->drv_priv,
ppdu_info->sts_ent[band][meta->ppdu_cnt].src_mac_addr,
meta->ta, MAC_ADDRESS_LENGTH);
}
ppdu_info->sts_ent[band][meta->ppdu_cnt].valid = false;
ppdu_info->cur_rx_ppdu_cnt[band] = meta->ppdu_cnt;
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"Start of the PPDU : band %d ; ppdu_cnt %d ; frame_type %d ; addr_cam_vld %d ; size %d ; rate 0x%x ; crc32 %d\n",
band,
ppdu_info->cur_rx_ppdu_cnt[band],
ppdu_info->sts_ent[band][meta->ppdu_cnt].frame_type,
ppdu_info->sts_ent[band][meta->ppdu_cnt].addr_cam_vld,
meta->pktlen,
meta->rx_rate,
meta->crc32);
} while (false);
}
void
hal_rx_ppdu_sts(struct rtw_phl_com_t *phl_com,
struct rtw_phl_rx_pkt *phl_rx,
struct hal_ppdu_sts *ppdu_sts)
{
struct rtw_phl_ppdu_sts_info *ppdu_info = NULL;
struct rtw_phl_rssi_stat *rssi_stat = NULL;
struct rtw_r_meta_data *meta = &(phl_rx->r.mdata);
struct rtw_phl_ppdu_phy_info *phy_info = &(phl_rx->r.phy_info);
u8 i = 0;
enum phl_band_idx band = HW_BAND_0;
struct rtw_phl_ppdu_sts_ent *sts_ent = NULL;
if ((NULL == phl_com) || (NULL == meta) || (NULL == ppdu_sts))
return;
ppdu_info = &phl_com->ppdu_sts_info;
rssi_stat = &phl_com->rssi_stat;
band = (meta->bb_sel > 0) ? HW_BAND_1 : HW_BAND_0;
ppdu_info->latest_rx_is_psts[band] = true;
if (0 == phy_info->is_valid)
return;
if (ppdu_info->cur_rx_ppdu_cnt[band] != meta->ppdu_cnt) {
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"[WARNING] ppdu cnt mis-match (band %d ; cur : %d , rxmeta : %d)\n",
band,
ppdu_info->cur_rx_ppdu_cnt[band],
meta->ppdu_cnt);
}
sts_ent = &(ppdu_info->sts_ent[band][meta->ppdu_cnt]);
if (meta->crc32 || sts_ent->crc32) {
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN,
phy_info->rssi);
return;
}
if (sts_ent->rx_rate != meta->rx_rate) {
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"[WARNING] PPDU STS rx rate mis-match\n");
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN,
phy_info->rssi);
return;
}
if (sts_ent->ppdu_type != meta->ppdu_type) {
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"[WARNING] PPDU STS ppdu_type mis-match\n");
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN,
phy_info->rssi);
return;
}
if (sts_ent->valid == true) {
PHL_TRACE(COMP_PHL_PSTS, _PHL_INFO_,
"[WARNING] PPDU STS is already updated, skip this ppdu status\n");
return;
}
/* update ppdu_info entry */
sts_ent->freerun_cnt = meta->freerun_cnt;
_os_mem_cpy(phl_com->drv_priv,
&(sts_ent->phy_info),
phy_info, sizeof(struct rtw_phl_ppdu_phy_info));
sts_ent->usr_num = ppdu_sts->usr_num;
for (i = 0; i < ppdu_sts->usr_num; i++) {
if (ppdu_sts->usr[i].vld) {
sts_ent->sta[i].macid =
ppdu_sts->usr[i].macid;
sts_ent->sta[i].vld = 1;
} else {
sts_ent->sta[i].vld = 0;
}
}
sts_ent->phl_done = false;
sts_ent->valid = true;
/* update rssi stat */
_os_spinlock(phl_com->drv_priv, &rssi_stat->lock, _bh, NULL);
switch (sts_ent->frame_type &
(BIT(1) | BIT(0))) {
case RTW_FRAME_TYPE_MGNT :
if (sts_ent->addr_cam_vld) {
UPDATE_MA_RSSI(rssi_stat,
(1 == meta->a1_match) ?
RTW_RSSI_MGNT_ACAM_A1M :
RTW_RSSI_MGNT_ACAM,
phy_info->rssi);
} else {
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_MGNT_OTHER,
phy_info->rssi);
}
break;
case RTW_FRAME_TYPE_CTRL :
if (sts_ent->addr_cam_vld) {
UPDATE_MA_RSSI(rssi_stat,
(1 == meta->a1_match) ?
RTW_RSSI_CTRL_ACAM_A1M :
RTW_RSSI_CTRL_ACAM,
phy_info->rssi);
} else {
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_CTRL_OTHER,
phy_info->rssi);
}
break;
case RTW_FRAME_TYPE_DATA :
if (sts_ent->addr_cam_vld) {
UPDATE_MA_RSSI(rssi_stat,
(1 == meta->a1_match) ?
RTW_RSSI_DATA_ACAM_A1M :
RTW_RSSI_DATA_ACAM,
phy_info->rssi);
} else {
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_DATA_OTHER,
phy_info->rssi);
}
break;
default:
UPDATE_MA_RSSI(rssi_stat, RTW_RSSI_UNKNOWN,
phy_info->rssi);
break;
}
_os_spinunlock(phl_com->drv_priv, &rssi_stat->lock, _bh, NULL);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_rx.c
|
C
|
agpl-3.0
| 16,014
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_RX_H_
#define _HAL_RX_H_
void
hal_rx_ppdu_sts_normal_data(struct rtw_phl_com_t *phl_com,
void *hdr,
struct rtw_r_meta_data *meta);
void
hal_rx_ppdu_sts(struct rtw_phl_com_t *phl_com,
struct rtw_phl_rx_pkt *phl_rx,
struct hal_ppdu_sts *ppdu_sts);
#ifdef CONFIG_PCI_HCI
/**
* rtw_hal_query_rxch_num - query total hw rx dma channels number
*
* returns the number of hw rx dma channel
*/
u8 rtw_hal_query_rxch_num(void *hal);
#endif
#endif /*_HAL_RX_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_rx.h
|
C
|
agpl-3.0
| 1,141
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_SER_C_
#include "hal_headers.h"
enum rtw_hal_status rtw_hal_ser_ctrl(void *hal, bool en)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
hstatus = rtw_hal_mac_ser_ctrl(hal_info, en);
return hstatus;
}
u32
rtw_hal_ser_get_error_status(void *hal, u32 *err)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET;
rtw_hal_mac_ser_get_error_status(hal_info, err);
if ((*err == MAC_AX_ERR_L1_ERR_DMAC) || (*err == MAC_AX_ERR_L0_PROMOTE_TO_L1)) {
notify = RTW_PHL_SER_PAUSE_TRX;
} else if (*err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) {
notify = RTW_PHL_SER_DO_RECOVERY;
} else if (*err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) {
notify = RTW_PHL_SER_READY;
} else if (*err < MAC_AX_ERR_L0_PROMOTE_TO_L1) {
notify = RTW_PHL_SER_L0_RESET;
} else if (*err == MAC_AX_DUMP_SHAREBUFF_INDICATOR) {
notify = RTW_PHL_SER_DUMP_FW_LOG;
} else if (*err == MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC) {
notify = RTW_PHL_SER_LOG_ONLY;
} else if ((*err == MAC_AX_ERR_L1_PROMOTE_TO_L2) ||
((*err >= MAC_AX_ERR_L2_ERR_AH_DMA) && (*err <= MAC_AX_GET_ERR_MAX))) {
notify = RTW_PHL_SER_L2_RESET;
}
return notify;
}
enum rtw_hal_status rtw_hal_ser_set_error_status(void *hal, u32 err)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_ser_set_error_status(hal_info, err);
}
enum rtw_hal_status rtw_hal_trigger_cmac_err(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_trigger_cmac_err(hal_info);
}
enum rtw_hal_status rtw_hal_trigger_dmac_err(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
return rtw_hal_mac_trigger_dmac_err(hal_info);
}
enum rtw_hal_status rtw_hal_lv1_rcvy(void *hal, u32 step)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> rtw_hal_lv1_rcvy step %d\n", step);
status = rtw_hal_mac_lv1_rcvy(hal_info, step);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== rtw_hal_lv1_rcvy step %d, status 0x%x\n", step, status);
return status;
}
void rtw_hal_dump_fw_rsvd_ple(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u32 mac_err;
mac_err = rtw_hal_mac_dump_fw_rsvd_ple(hal_info);
}
void
rtw_hal_ser_reset_wdt_intr(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u32 mac_err;
mac_err = rtw_hal_mac_ser_reset_wdt_intr(hal_info);
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "rtw_hal_ser_reset_wdt_intr status 0x%x\n",mac_err);
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ser.c
|
C
|
agpl-3.0
| 3,287
|
/******************************************************************************
*
* Copyright(c)2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_SER_H_
#define _HAL_SER_H_
#endif /* _HAL_SER_H_ */
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_ser.h
|
C
|
agpl-3.0
| 714
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_SOUND_C_
#include "hal_headers.h"
struct csi_rpt_na {
u8 nr;
u8 nc;
u8 na;
};
#define CSI_NA_MATRIX_SIZE 35
static const struct csi_rpt_na csi_na[CSI_NA_MATRIX_SIZE] =
{
{2, 1, 2}, {2, 2, 2},
{3, 1, 4}, {3, 2, 6}, {3, 3, 6},
{4, 1, 6}, {4, 2, 10}, {4, 3, 12}, {4, 4, 12},
{5, 1, 8}, {5, 2, 14}, {5, 3, 18}, {5, 4, 20}, {5, 5, 20},
{6, 1, 10}, {6, 2, 18}, {6, 3, 24}, {6, 4, 28}, {6, 5, 30},
{6, 6, 30},
{7, 1, 12}, {7, 2, 22}, {7, 3, 30}, {7, 4, 36},
{7, 5, 40}, {7, 6, 42}, {7, 7, 42},
{8, 1, 14}, {8, 2, 26}, {8, 3, 36}, {8, 4, 55},
{8, 5, 50}, {8, 6, 54}, {8, 7, 56}, {8, 8, 56}
};
u32 _cal_he_csi_size(u8 mu, enum channel_width bw, u8 nr, u8 nc, u8 ng, u8 cb)
{
u8 na = 0;
u8 ns = 0;
u8 i = 0;
u32 csi_size = 0;
u8 cb_s = 0;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"%s : mu(%d) ; bw(%d) ; nr(%d) ; nc(%d), ng(%d), cb(%d)\n",
__func__, mu, bw, nr, nc, ng ,cb);
do {
if (CHANNEL_WIDTH_80 == bw)
ns = (ng == 4) ? 250 : 64;
else if(CHANNEL_WIDTH_40 == bw)
ns = (ng == 4) ? 122 : 32;
else if(CHANNEL_WIDTH_20 == bw)
ns = (ng == 4) ? 64 : 20;
else
break;
for (i = 0; i < CSI_NA_MATRIX_SIZE; i++) {
if ((nr == csi_na[i].nr) && (nc ==csi_na[i].nc)) {
na = csi_na[i].na;
break;
}
}
if (na == 0)
break;
if (cb) {
if(mu)
cb_s = 8;
else
cb_s = 5;
} else {
if(mu)
cb_s = 6;
else
cb_s = 3;
}
} while(0);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"%s : na %d ; ns %d ; cb_s %d",__func__, na, ns, cb_s);
if ((0 != na) && (0 != ns) && (0 != cb_s)) {
csi_size = ((8 * (u32)nc) +
((u32)na * (u32)cb_s * (u32)ns)) / 8;
if(mu)
csi_size += (4 * (u32)nc * (u32)ns) / 8;
}
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_,
"%s : expected he csi report size = %d byte",
__func__, csi_size);
return csi_size;
}
u32 _cal_he_cqi_only_rpt_size(enum channel_width bw, u8 nc)
{
u32 ret = 0;
if (CHANNEL_WIDTH_80 == bw)
ret = (u32)nc * 37;
else if(CHANNEL_WIDTH_40 == bw)
ret = (u32)nc * 18;
else if(CHANNEL_WIDTH_20 == bw)
ret = (u32)nc * 9;
return ret;
}
/*1. BF Resource Related*/
u8 _get_bw_ru_end_idx(enum channel_width bw) {
u8 ru_end_idx = 0;
switch (bw) {
case CHANNEL_WIDTH_20:
ru_end_idx = HAL_NPDA_RU_IDX_END_20MHZ;
break;
case CHANNEL_WIDTH_40:
ru_end_idx = HAL_NPDA_RU_IDX_END_40MHZ;
break;
case CHANNEL_WIDTH_80:
ru_end_idx = HAL_NPDA_RU_IDX_END_80MHZ;
break;
case CHANNEL_WIDTH_160:
case CHANNEL_WIDTH_80_80:
ru_end_idx = HAL_NPDA_RU_IDX_END_160MHZ;
default:
break;
}
return ru_end_idx;
}
void _hal_snd_set_default_var(struct hal_snd_obj *snd_obj)
{
snd_obj->ndpa_xpara.bw = CHANNEL_WIDTH_20;
snd_obj->ndpa_xpara.rate = RTW_DATA_RATE_OFDM6;
snd_obj->ndpa_xpara.gi_ltf = RTW_GILTF_LGI_4XHE32;
snd_obj->ndpa_xpara.stbc = 0;
snd_obj->ndpa_xpara.ldpc = 0;
snd_obj->bfrp_xpara.bw = CHANNEL_WIDTH_20;
snd_obj->bfrp_xpara.rate = RTW_DATA_RATE_OFDM6;
snd_obj->bfrp_xpara.gi_ltf = RTW_GILTF_LGI_4XHE32;
snd_obj->bfrp_xpara.stbc = 0;
snd_obj->bfrp_xpara.ldpc = 0;
}
enum rtw_hal_status
hal_snd_obj_init(void *hal)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
struct hal_snd_obj *snd_obj = NULL;
do {
hal_com->snd_obj = _os_mem_alloc(hal_to_drvpriv(hal_info),
sizeof(struct hal_snd_obj));
if (NULL == hal_com->snd_obj) {
break;
}
snd_obj = hal_com->snd_obj;
/* preset hal sounding default values */
_hal_snd_set_default_var(snd_obj);
hstatus = RTW_HAL_STATUS_SUCCESS;
} while (0);
return hstatus;
}
enum rtw_hal_status
hal_snd_obj_deinit(void *hal)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
do {
if (hal_com->snd_obj == NULL)
break;
_os_mem_free(hal_to_drvpriv(hal_info), hal_com->snd_obj,
sizeof(struct hal_snd_obj));
hal_com->snd_obj = NULL;
} while (0);
return hstatus;
}
/**
* rtw_hal_snd_release_proc_sta_res
* free the resource for a STA used in sounding process
* input:
* @hal: (struct hal_info_t *)
* @sta: (struct rtw_phl_stainfo_t *)
**/
enum rtw_hal_status
rtw_hal_snd_release_proc_sta_res(void *hal, struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta;
do {
if (hal_sta->bf_entry != NULL) {
hal_status = hal_bf_release_target_bf_entry(
hal_info, hal_sta->bf_entry);
}
if (hal_is_csi_buf_valid(hal_info, &hal_sta->bf_csi_buf)) {
hal_status = hal_csi_release_csi_buf(
hal_info, &hal_sta->bf_csi_buf);
}
if (hal_is_csi_buf_valid(hal_info, &hal_sta->bf_csi_buf_swap)) {
hal_status = hal_csi_release_csi_buf(
hal_info, &hal_sta->bf_csi_buf_swap);
}
} while(0);
return hal_status;
}
/**
* rtw_hal_snd_query_proc_sta_res
* input:
* @hal: hal_info
* @sta: rtw_phl_stainfo_t
* @mu: is this MU-MIMO STA resource request
* @bw: enum channel_width sounding bandwidth
**/
enum rtw_hal_status
rtw_hal_snd_query_proc_sta_res(
void *hal,
struct rtw_phl_stainfo_t *sta,
bool mu,
enum channel_width bw,
bool en_swap)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta;
do {
if (hal_sta->bf_entry != NULL) {
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "[WARNING] sta->bf_entry != NULL\n");
/* TODO:Shall Release First ?*/
/* rtw_hal_snd_release_proc_sta_res(hal, sta); */
}
hal_sta->bf_entry =
(void *)hal_bf_query_idle_bf_entry(hal_info, mu);
if (hal_sta->bf_entry == NULL)
break;
hal_status = hal_csi_query_idle_csi_buf(
hal_info, mu, bw, &hal_sta->bf_csi_buf);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
break;
if (mu && en_swap) {
hal_status = hal_csi_query_idle_csi_buf(
hal_info, mu, bw, &hal_sta->bf_csi_buf_swap);
}
if (hal_status == RTW_HAL_STATUS_FAILURE) {
PHL_INFO("Cannot Enable Swap Mode! Because of the CSI resource is not enougth.\n");
break;
}
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta->bf_csi_buf 0x%x \n",
hal_sta->bf_csi_buf);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "sta->bf_csi_buf_swap 0x%x \n",
hal_sta->bf_csi_buf_swap);
/* Set STA-INFO info to BF Entry */
hal_status = hal_bf_cfg_swbf_entry(sta, en_swap);
} while (0);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_INFO("rtw_hal_snd_query_proc_sta_res FAIL \n");
rtw_hal_snd_release_proc_sta_res(hal, sta);
}
return hal_status;
}
/**
* rtw_hal_snd_proc_pre_cfg_sta
* hw preconfiguration for a sounding sta
* input:
* @hal: hal_info
* @sta: (struct rtw_phl_stainfo_t *)
**/
enum rtw_hal_status
rtw_hal_snd_proc_pre_cfg_sta(
void *hal,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta;
/* 1. MAC HW BF Entry Settings */
hal_status = hal_bf_set_entry_hwcfg(
hal_info, hal_sta->bf_entry);
/* 2. Add other HAL setting here */
/*TODO:*/
return hal_status;
}
/**
* rtw_hal_snd_proc_post_cfg
* hw/fw post configuration for a sounding event
* input:
* @hal: hal_info
**/
enum rtw_hal_status
rtw_hal_snd_proc_post_cfg(void *hal, bool he, bool mu, bool en_fixed_mode)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_mu_score_tbl *hal_score_table = &hal_info->hal_com->bb_mu_score_tbl;
if (mu) {
/*1. MU Score Board */
hal_status = rtw_hal_mac_ax_set_mu_table_whole(
hal_info->mac, hal_score_table);
/*2. (optional) MU Fixed Mode */
if (en_fixed_mode)
hal_status = rtw_hal_bf_set_fix_mode(hal, mu, he);
}
return hal_status;
}
/**
* rtw_hal_snd_proc_post_cfg_gid
* hw/fw post configuration for a vht/he gid
* input:
* @hal: hal_info
* @gid: wifi protolcol gid (PLCP) for configuration
* @ba_info: pointer of struct rtw_hal_muba_info
**/
enum rtw_hal_status
rtw_hal_snd_proc_post_cfg_gid(void *hal, u8 gid, void *ba_info)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
/*
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct rtw_hal_muba_info *hal_ba_info = (struct rtw_hal_muba_info *)ba_info;
*/
/*TODO:*/
/*1. MU BAR Table : Table ID = GID, GID = STA-x + sSTA-y*/
return hal_status;
}
/**
* rtw_hal_snd_proc_post_cfg_sta
* hw/fw post configuration for a single sounding sta
* input:
* @hal: hal_info
* @sta: (struct rtw_phl_stainfo_t *)
**/
enum rtw_hal_status
rtw_hal_snd_proc_post_cfg_sta(
void *hal,
struct rtw_phl_stainfo_t *sta,
bool mu)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
/* MAC/FW Settings */
if (mu) {
/*1. FW MU STA Update */
hal_status = hal_bf_set_mu_sta_fw(hal, sta);
/*2. MU Score Board */
/* mac->mac_set_mu_table_single_sta */
}
/* BB/FW Settings */
/*TODO:*/
/* 2. Add other setting here */
/*TODO:*/
return hal_status;
}
/**
* rtw_hal_snd_mac_ctrl
* control sounding process : pause or start.
* @hal: hal_info
* @band: band0 / band1
* @ctrl: 0 = pause souning / 1 = start sounding
**/
enum rtw_hal_status
rtw_hal_snd_mac_ctrl(void *hal, u8 band, u8 ctrl)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
hstatus = rtw_hal_mac_ax_hw_snd_control(hal_info->mac, band, ctrl);
return hstatus;
}
/**
* rtw_hal_snd_chk_bf_res
* check the sta's sounding resource is enough for sounding
* input :
* @hal: hal_info
* @sta: (struct rtw_hal_stainfo_t *)
* @mu: true = mu / false = su
* @bw: enum channel_width
* return :
* @hstatus: RTW_HAL_STATUS_FAILURE = need release and query bf entry and CSI buffer
* RTW_HAL_STATUS_SUCCESS = STA's BF Entry and CSI Buffer is same to condition.
**/
enum rtw_hal_status
rtw_hal_snd_chk_bf_res(void *hal, struct rtw_phl_stainfo_t *sta,
bool mu, enum channel_width bw)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_hal_stainfo_t *hal_sta = sta->hal_sta;
do {
if (sta == NULL)
break;
if (false == rtw_hal_bf_chk_bf_type(hal, sta, mu))
break;
if (mu != rtw_hal_get_csi_buf_type(&hal_sta->bf_csi_buf))
break;
if (bw != rtw_hal_get_csi_buf_bw(&hal_sta->bf_csi_buf))
break;
hstatus = RTW_HAL_STATUS_SUCCESS;
} while (0);
return hstatus;
}
/**
* rtw_hal_snd_polling_snd_sts
* update the sta's sounding status into sta->hal_sta->bf_entry->bfee
* input :
* @hal: hal_info
* @sta: (struct rtw_hal_stainfo_t *)
**/
void
rtw_hal_snd_polling_snd_sts(void *hal, struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
do {
if (sta == NULL)
break;
hal_bf_update_entry_snd_sts(hal_info, sta->hal_sta->bf_entry);
} while (0);
}
/* SND H2C CMD related functions */
void
rtw_hal_snd_ndpa_sta_info_vht(struct rtw_phl_stainfo_t *psta_info,
u32 *ndpa, u8 mu)
{
struct hal_vht_ndpa_sta_info *ndpa_sta =
(struct hal_vht_ndpa_sta_info *)ndpa;
if (PHL_RTYPE_STATION == psta_info->wrole->type)
ndpa_sta->aid12 = 0; /* Target is an AP, AID = 0 */
else
ndpa_sta->aid12 = psta_info->aid;
ndpa_sta->feedback_type = (mu == 0) ? HAL_NPDA_AC_SU : HAL_NPDA_AC_MU;
/* Nc shall alwary <= Nr */
if (psta_info->asoc_cap.max_nc >
psta_info->wrole->proto_role_cap.num_snd_dim) {
ndpa_sta->nc = psta_info->wrole->proto_role_cap.num_snd_dim;
} else {
ndpa_sta->nc = psta_info->asoc_cap.max_nc;
}
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "vht ndpa_sta aid12 0x%x ; fb 0x%x ; nc 0x%x\n",
ndpa_sta->aid12, ndpa_sta->feedback_type, ndpa_sta->nc);
}
void
rtw_hal_snd_ndpa_sta_info_he(struct rtw_phl_stainfo_t *psta_info,
u32 *ndpa, enum channel_width bw, u8 fb_type)
{
struct hal_he_ndpa_sta_info *ndpa_sta =
(struct hal_he_ndpa_sta_info *)ndpa;
u16 ru_start = HAL_NPDA_RU_IDX_START;
u16 ru_end = _get_bw_ru_end_idx(bw);
if (PHL_RTYPE_STATION == psta_info->wrole->type)
ndpa_sta->aid = 0; /* Target is and AP, AID = 0 */
else
ndpa_sta->aid = (psta_info->aid&0x7FF);
ndpa_sta->bw = ((ru_start&0x7F) << 0) | ((ru_end&0x7F) << 7);
if (0 == fb_type) {
ndpa_sta->fb_ng = psta_info->asoc_cap.ng_16_su_fb ?
HAL_NDPA_AX_FB_SU_NG_16 : HAL_NDPA_AX_FB_SU_NG_4;
ndpa_sta->cb = psta_info->asoc_cap.cb_sz_su_fb ?
HAL_NPDA_AX_CB_SU42_MU75 : HAL_NPDA_AX_CB_SU64_MU97;
} else if (1 == fb_type) {
ndpa_sta->fb_ng = psta_info->asoc_cap.ng_16_mu_fb ?
HAL_NDPA_AX_FB_MU_NG_16 : HAL_NDPA_AX_FB_MU_NG_4;
ndpa_sta->cb = psta_info->asoc_cap.cb_sz_mu_fb ?
HAL_NPDA_AX_CB_SU42_MU75 : HAL_NPDA_AX_CB_SU64_MU97;
} else {
ndpa_sta->fb_ng = HAL_NDPA_AX_FB_CQI;
ndpa_sta->cb = 1;
}
ndpa_sta->disambiguation = 1;
/* Nc shall alwary <= Nr */
if (psta_info->asoc_cap.max_nc >
psta_info->wrole->proto_role_cap.num_snd_dim) {
ndpa_sta->nc = psta_info->wrole->proto_role_cap.num_snd_dim;
} else {
ndpa_sta->nc = psta_info->asoc_cap.max_nc;
}
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "HE NDPA : aid 0x%x fb_ng 0x%x cb 0x%x nc 0x%x \n",
ndpa_sta->aid, ndpa_sta->fb_ng, ndpa_sta->cb, ndpa_sta->nc);
}
/**
* rtw_hal_snd_set_fw_cmd_dialogtkn()
* Set cmd dialog token value in NDPA
* input
* @he: is NDPA HE or not(VHT).
* @token: dialog token value.
**/
void rtw_hal_snd_set_fw_cmd_dialogtkn(void *hal, u8 *buf, u8 he, u8 token)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
cmd->ndpa.snd_dialog.he = he;
cmd->ndpa.snd_dialog.token = token;
}
/**
* rtw_hal_snd_vht_fwcmd_su()
* Prepared VHT SU Sounding Fw Cmd.
* @hal:
* @buf: (struct hal_ax_fwcmd_snd *) cmd buffer pointer.
* @psta: (struct rtw_phl_stainfo_t *) STA to be sounding.
* @npda_sta: NPDA sta_info value
**/
void rtw_hal_snd_vht_fwcmd_su(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u32 *npda_sta)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_snd_obj *snd_obj =
(struct hal_snd_obj *)hal_info->hal_com->snd_obj;
u8 i = 0;
cmd->frame_ex_type = HAL_FEXG_TYPE_AC_SU;
cmd->macid[0] = psta->macid;
cmd->ndpa.common.frame_ctl = HAL_SND_VHT_NDPA_FRM_CTRL; /*TODO*/
for (i = 0; i < 6;i++) {
cmd->ndpa.common.addr1[i] = psta->mac_addr[i]; /* NDPA-RA*/
cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/
}
cmd->ndpa.common.duration = 100;
cmd->ndpa.ndpa_sta_info[0] = *npda_sta;
/* NDPA WD */
cmd->wd[0].txpktsize = 21;/* 2 + 2 + 6 + 6 + 1 + 4, NO FCS */
cmd->wd[0].ndpa_duration = 100;
cmd->wd[0].disdatafb = 1;
cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate;
cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw;
cmd->wd[0].macid = psta->macid;
cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf;
cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc;
cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc;
cmd->wd[0].sifs_tx = 1;
cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_UST_NDPA;/* unicast ndpa */
cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_VHT;
/* NDP WD */
cmd->wd[1].disdatafb = 1;
if (1 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0;
else if (2 ==psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS3_MCS0;
else if (3 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS4_MCS0;
else
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "psta->asoc_cap.nss_rx = 0x%x\n", psta->asoc_cap.nss_rx);
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "cmd->wd[1].datarate = 0x%x\n", cmd->wd[1].datarate);
cmd->wd[1].data_bw = bw;
cmd->wd[1].macid = psta->macid;
cmd->wd[1].gi_ltf = RTW_GILTF_LGI_4XHE32;
cmd->wd[1].sifs_tx = 0;
cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_NDP;
cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_VHT;
}
void rtw_hal_snd_vht_fwcmd_mu_add_sta(void *hal, u8 *buf, u32 *ndpa_sta,
struct rtw_phl_stainfo_t *sta,
u8 ndpa_idx, u8 last)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_snd_obj *snd_obj =
(struct hal_snd_obj *)hal_info->hal_com->snd_obj;
u8 i = 0;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> rtw_hal_snd_vht_fwcmd_mu_add_sta\n");
if (ndpa_idx >= HAL_MAX_VHT_SND_STA_NUM)
return;
cmd->macid[ndpa_idx] = sta->macid;
/* NDPA sta_info*/
cmd->ndpa.ndpa_sta_info[ndpa_idx] = *ndpa_sta;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "mac id 0x%x ; ndpa sta_info 0x%x\n",
cmd->macid[ndpa_idx], cmd->ndpa.ndpa_sta_info[ndpa_idx]);
/* VHT BFRP */
cmd->bfrp.hdr[ndpa_idx - 1].frame_ctl = HAL_SND_VHT_BFRP_FRM_CTRL;
cmd->bfrp.hdr[ndpa_idx - 1].duration = 100;
for (i = 0; i < 6; i++) {
cmd->bfrp.hdr[ndpa_idx - 1].addr1[i] = sta->mac_addr[i]; /* NDPA-RA = Broadcast*/
cmd->bfrp.hdr[ndpa_idx - 1].addr2[i] = sta->wrole->mac_addr[i]; /* NDPA-TA*/
}
cmd->bfrp.vht_para[ndpa_idx - 1].rexmit_bmp = 0;
/*BFRP WD*/
cmd->wd[1 + ndpa_idx].txpktsize = 17; /* 2 + 2 + 6 + 6 + 1 */
cmd->wd[1 + ndpa_idx].ndpa_duration = 100;
cmd->wd[1 + ndpa_idx].datarate = snd_obj->bfrp_xpara.rate;
cmd->wd[1 + ndpa_idx].data_ldpc = snd_obj->bfrp_xpara.ldpc;
cmd->wd[1 + ndpa_idx].data_stbc = snd_obj->bfrp_xpara.stbc;
cmd->wd[1 + ndpa_idx].macid = sta->macid;
cmd->wd[1 + ndpa_idx].data_bw = snd_obj->bfrp_xpara.bw;
cmd->wd[1 + ndpa_idx].gi_ltf = snd_obj->bfrp_xpara.gi_ltf;
cmd->wd[1 + ndpa_idx].disdatafb = 1;
if(last) {
cmd->wd[1 + ndpa_idx].sifs_tx = 0;
cmd->wd[1 + ndpa_idx].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_BFRP;/* Final BFRP */
} else {
cmd->wd[1 + ndpa_idx].sifs_tx = 1;
cmd->wd[1 + ndpa_idx].snd_pkt_sel = HAL_SND_PKT_SEL_MID_BFRP;
}
cmd->wd[1 + ndpa_idx].ndpa = HAL_SND_PKT_NDPA_VHT;
}
void rtw_hal_snd_vht_fwcmd_mu_pri(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u8 sta_nr, u32 *ndpa_sta)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_snd_obj *snd_obj =
(struct hal_snd_obj *)hal_info->hal_com->snd_obj;
u8 i = 0;
if (sta_nr == 4)
cmd->frame_ex_type = HAL_FEXG_TYPE_AC_MU_3;
else if(sta_nr == 3)
cmd->frame_ex_type = HAL_FEXG_TYPE_AC_MU_2;
else if(sta_nr == 2)
cmd->frame_ex_type = HAL_FEXG_TYPE_AC_MU_1;
else
PHL_INFO("rtw_hal_snd_vht_fwcmd_mu_pri : ERROR!!!!!!!!!!!!!!!");
cmd->macid[0] = psta->macid;
/* NDPA */
cmd->ndpa.common.frame_ctl = HAL_SND_VHT_NDPA_FRM_CTRL;
for (i = 0; i < 6;i++) {
/**
* Addr1: In VHT Case, Fill User_0's MAC Address to match BF Entry,
* HW will auto re-fill to Broadcast Address
**/
cmd->ndpa.common.addr1[i] = psta->mac_addr[i];
cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/
}
cmd->ndpa.common.duration = 150;/*TODO:*/
/* primary sta ndpa sta_info*/
cmd->ndpa.ndpa_sta_info[0] = *ndpa_sta;
/* VHT BFRP ==> by STA */
/* NDPA WD */
cmd->wd[0].txpktsize = 17 + HAL_SND_VHT_NDPA_STA_SZ * sta_nr;/* 2 + 2 + 6 + 6 + 1 + 2, NO FCS */
cmd->wd[0].ndpa_duration = 150;
cmd->wd[0].disdatafb = 1;
cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate;
cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw;
cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc;
cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc;
cmd->wd[0].macid = psta->macid;
cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf;
cmd->wd[0].sifs_tx = 1;
cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_BST_NDPA;
cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_VHT;
/* NDP WD */
cmd->wd[1].disdatafb = 1;
if (1 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0;
else if (2 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS3_MCS0;
else if (3 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS4_MCS0;
else
cmd->wd[1].datarate = RTW_DATA_RATE_VHT_NSS2_MCS0;
cmd->wd[1].data_bw = bw;
cmd->wd[1].macid = psta->macid;
cmd->wd[1].gi_ltf = RTW_GILTF_LGI_4XHE32;
cmd->wd[1].sifs_tx = 1;
cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_MID_NDP;/*Last NDP*/
cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_VHT;
}
/* HE FW Command */
/**
* rtw_hal_snd_ax_fwcmd_su()
* fill the fw cmd for HE sounding type HE Non-TB : NDPA - NDP - CSI Report
*
**/
void rtw_hal_snd_ax_fwcmd_nontb(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u32 *npda_sta)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_snd_obj *snd_obj =
(struct hal_snd_obj *)hal_info->hal_com->snd_obj;
u8 i = 0;
cmd->frame_ex_type = HAL_FEXG_TYPE_AX_SU;
cmd->macid[0] = psta->macid;
cmd->ndpa.common.frame_ctl = HAL_SND_HE_NDPA_FRM_CTRL;
for (i = 0; i < 6;i++) {
cmd->ndpa.common.addr1[i] = psta->mac_addr[i]; /* NDPA-RA*/
cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/
}
cmd->ndpa.common.duration = 100;
cmd->ndpa.ndpa_sta_info[0] = *npda_sta;
/* NDPA WD */
cmd->wd[0].txpktsize = 21;/* 2 + 2 + 6 + 6 + 1 + 4, NO FCS */
cmd->wd[0].ndpa_duration = 100;
cmd->wd[0].disdatafb = 1;
cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate;
cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw;
cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc;
cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc;
cmd->wd[0].macid = psta->macid;
cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf;
cmd->wd[0].sifs_tx = 1;
cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_UST_NDPA;/*unicast ndpa*/
cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_HE;
/* NDP WD */
cmd->wd[1].disdatafb = 1;
if (1 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0;
else if (2 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS3_MCS0;
else if (3 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS4_MCS0;
else
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0;
cmd->wd[1].data_bw = bw;
cmd->wd[1].macid = psta->macid;
cmd->wd[1].gi_ltf = RTW_GILTF_2XHE16; /* TODO: if psta->asoc_cap.ltf_gi support NDP 4XHE32;*/
cmd->wd[1].sifs_tx = 0;
cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_NDP;
cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_HE;
}
/**
* rtw_hal_snd_ax_fwcmd_tb_add_sta()
* fill fw cmd for HE sounding with TB case.
* shall call rtw_hal_snd_ax_fwcmd_tb_pri() first, and add STA by this api.
* Note that RU-Allocation shall dicide from phl caller,
* and shall avoid same with others
* function input:
* @hal:
* @buf: (struct hal_ax_fwcmd_snd *) command buf pointer.
* @ndpa_sta:
* @sta: (struct rtw_phl_stainfo_t *)
* @ru_idx: RU Allocation index;
* @ndpa_idx: 0-7 for 8852a
* @bfrp_idx: 0-1 for 8852a
* @bfrp_u_idx: 0-3 for 8852a
**/
void rtw_hal_snd_ax_fwcmd_tb_add_sta(void *hal, u8 *buf, u32 *ndpa_sta,
struct rtw_phl_stainfo_t *sta, u8 ru_idx,
u8 ndpa_idx, u8 bfrp_idx, u8 bfrp_u_idx)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
struct hal_he_ndpa_sta_info *ndpa =
(struct hal_he_ndpa_sta_info *)ndpa_sta;
u8 mu = 0, ng = 4;
u32 rpt_size = 0;
if (ndpa_idx > HAL_MAX_HE_SND_STA_NUM)
return;
if (bfrp_idx > HAL_MAX_HE_BFRP_NUM)
return;
cmd->macid[ndpa_idx] = sta->macid;
/* NDPA sta_info*/
cmd->ndpa.ndpa_sta_info[ndpa_idx] = *ndpa_sta;
/* BFRP user_info */
cmd->bfrp.he_para[bfrp_idx].fbseg_rexmit_bmp[bfrp_u_idx] = 0;
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].aid12 = sta->aid;
if (cmd->bfrp.he_para[bfrp_idx].common.ul_bw > CHANNEL_WIDTH_80) {
ru_idx = (ru_idx << 1) | BIT(0);
} else {
ru_idx = (ru_idx << 1) &(~BIT(0));
}
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ru_pos = ru_idx;
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_fec_code = 0;
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_mcs = 3;/* HE-MCS3, TODO: Default value of golden */
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_dcm = 0 ;
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ss_alloc = 0;/* 1SS, TODO: Default value of golden */
cmd->bfrp.he_para[bfrp_idx].user[bfrp_u_idx].ul_tgt_rssi =
(u8)(sta->hal_sta->rssi_stat.rssi >> 1);/*TODO: From Rx ST SU RSSI */
if (ndpa->fb_ng == HAL_NDPA_AX_FB_MU_NG_4) {
mu = 1;
ng = 4;
} else if (ndpa->fb_ng == HAL_NDPA_AX_FB_MU_NG_16) {
mu = 1;
ng = 16;
} else if (ndpa->fb_ng == HAL_NDPA_AX_FB_SU_NG_4) {
mu = 0;
ng = 4;
} else if (ndpa->fb_ng == HAL_NDPA_AX_FB_SU_NG_16) {
mu = 0;
ng = 4;
}
rpt_size = _cal_he_csi_size(mu, sta->chandef.bw,
(sta->wrole->proto_role_cap.num_snd_dim + 1),
((u8)ndpa->nc + 1), ng, (u8)ndpa->cb);
if (cmd->bfrp.he_para[bfrp_idx].f2p_info.csi_len_bfrp < (rpt_size/64))
cmd->bfrp.he_para[bfrp_idx].f2p_info.csi_len_bfrp =
(u16)(rpt_size / 64); /*unit 64 byte*/
}
void rtw_hal_snd_ax_fwcmd_tb_pri(void *hal, u8 *buf, enum channel_width bw,
struct rtw_phl_stainfo_t *psta, u8 sta_nr1, u8 sta_nr2)
{
struct hal_ax_fwcmd_snd *cmd = (struct hal_ax_fwcmd_snd *)buf;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
struct hal_snd_obj *snd_obj =
(struct hal_snd_obj *)hal_info->hal_com->snd_obj;
u8 i = 0;
u8 sta_nr = sta_nr1 + sta_nr2;
if (sta_nr2 != 0)
cmd->frame_ex_type = HAL_FEXG_TYPE_AX_MU_2;
else
cmd->frame_ex_type = HAL_FEXG_TYPE_AX_MU_1;
cmd->bfrp0_sta_nr = sta_nr1;
cmd->bfrp1_sta_nr = sta_nr2;
cmd->macid[0] = psta->macid;
/* NDPA */
cmd->ndpa.common.frame_ctl = HAL_SND_HE_NDPA_FRM_CTRL; /*TODO:*/
for (i = 0; i < 6;i++) {
cmd->ndpa.common.addr1[i] = 0xFF; /* NDPA-RA = Broadcast*/
cmd->ndpa.common.addr2[i] = psta->wrole->mac_addr[i]; /* NDPA-TA*/
/* BFRP - 1*/
cmd->bfrp.hdr[0].addr1[i] = 0xFF;
cmd->bfrp.hdr[0].addr2[i] = psta->wrole->mac_addr[i];
if (sta_nr2 != 0) {
/* BFRP - 2*/
cmd->bfrp.hdr[1].addr1[i] = 0xFF;
cmd->bfrp.hdr[1].addr2[i] = psta->wrole->mac_addr[i];
}
}
cmd->ndpa.common.duration = 150;/*TODO:*/
/*TODO: ndpa user info in other api */
/* BFRP #1 */
cmd->bfrp.hdr[0].frame_ctl = HAL_SND_HE_BFRP_FRM_CTRL; /* Trigger Frame */
cmd->bfrp.hdr[0].duration = 100;
cmd->bfrp.he_para[0].common.tgr_info = HAL_SND_TRIG_INFO_BFRP;/*BFRP*/
cmd->bfrp.he_para[0].common.ul_len = 0xFFF;/*TODO: LSIG Length : sw provide or fw calculate */
cmd->bfrp.he_para[0].common.more_tf = 0;
cmd->bfrp.he_para[0].common.cs_rqd = 1;
cmd->bfrp.he_para[0].common.ul_bw = bw;
cmd->bfrp.he_para[0].common.gi_ltf = RTW_TB_GILTF_4XHE32;/* 8852A Limitation of UL OFDMA */
cmd->bfrp.he_para[0].common.num_heltf = 0;/* TODO: Default value of golden */
cmd->bfrp.he_para[0].common.ul_pktext = 0;/* TODO: fw? hw? */
cmd->bfrp.he_para[0].common.ap_tx_pwr = 0x3C;/* TODO: Default value of golden */
/* F2P cmd parameters */
cmd->bfrp.he_para[0].f2p_info.tb_t_pe_bfrp = 2;
cmd->bfrp.he_para[0].f2p_info.tri_pad_bfrp = 2;
cmd->bfrp.he_para[0].f2p_info.ul_cqi_rpt_tri_bfrp = 0;
cmd->bfrp.he_para[0].f2p_info.rf_gain_idx_bfrp = 0;/* ?? */
cmd->bfrp.he_para[0].f2p_info.fix_gain_en_bfrp = 0;/* ?? */
if (sta_nr2) {
cmd->bfrp.hdr[1].frame_ctl = HAL_SND_HE_BFRP_FRM_CTRL; /* Trigger Frame */
cmd->bfrp.hdr[1].duration = 100;
cmd->bfrp.he_para[1].common.tgr_info = HAL_SND_TRIG_INFO_BFRP;/*BFRP*/
cmd->bfrp.he_para[1].common.ul_len = 0xFFF;/*TODO: LSIG Length : sw provide or fw calculate */
cmd->bfrp.he_para[1].common.more_tf = 0;
cmd->bfrp.he_para[1].common.cs_rqd = 1;
cmd->bfrp.he_para[1].common.ul_bw = bw;
cmd->bfrp.he_para[1].common.gi_ltf = RTW_TB_GILTF_4XHE32;/* 8852A Limitation of UL OFDMA */
cmd->bfrp.he_para[1].common.num_heltf = 0;/* TODO: Default value of golden */
cmd->bfrp.he_para[1].common.ul_pktext = 0;/* TODO: fw? hw? */
cmd->bfrp.he_para[1].common.ap_tx_pwr = 0x32;/* TODO: Default value of golden */
cmd->bfrp.he_para[1].f2p_info.tb_t_pe_bfrp = 2;
cmd->bfrp.he_para[1].f2p_info.tri_pad_bfrp = 2;
cmd->bfrp.he_para[1].f2p_info.ul_cqi_rpt_tri_bfrp = 0;
cmd->bfrp.he_para[1].f2p_info.rf_gain_idx_bfrp = 0;
cmd->bfrp.he_para[1].f2p_info.fix_gain_en_bfrp = 0;
}
/* NDPA WD */
cmd->wd[0].txpktsize = 17 + HAL_SND_HE_NDPA_STA_SZ * sta_nr;/* 2 + 2 + 6 + 6 + 1 + 4, NO FCS */
cmd->wd[0].ndpa_duration = 100;
cmd->wd[0].disdatafb = 1;
cmd->wd[0].datarate = snd_obj->ndpa_xpara.rate;
cmd->wd[0].data_bw = snd_obj->ndpa_xpara.bw;
cmd->wd[0].data_stbc = snd_obj->ndpa_xpara.stbc;
cmd->wd[0].data_ldpc = snd_obj->ndpa_xpara.ldpc;
cmd->wd[0].macid = psta->macid;
cmd->wd[0].gi_ltf = snd_obj->ndpa_xpara.gi_ltf;
cmd->wd[0].sifs_tx = 1;
cmd->wd[0].snd_pkt_sel = HAL_SND_PKT_SEL_BST_NDPA;
cmd->wd[0].ndpa = HAL_SND_PKT_NDPA_HE;
/* NDP WD */
cmd->wd[1].disdatafb = 1;
if (1 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0;
else if (2 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS3_MCS0;
else if(3 == psta->wrole->proto_role_cap.num_snd_dim)
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS4_MCS0;
else
cmd->wd[1].datarate = RTW_DATA_RATE_HE_NSS2_MCS0;
cmd->wd[1].data_bw = bw;
cmd->wd[1].macid = psta->macid;
cmd->wd[1].gi_ltf = RTW_GILTF_2XHE16; /* TODO: if support 4x32 NDP */
cmd->wd[1].sifs_tx = 0;
cmd->wd[1].snd_pkt_sel = HAL_SND_PKT_SEL_MID_NDP;
cmd->wd[1].ndpa = HAL_SND_PKT_NDPA_HE;
/* BFRP #1 WD */
cmd->wd[2].txpktsize = 24 + HAL_SND_HE_BFRP_STA_SZ * sta_nr1; /* 2 + 2 + 6 + 6 + 8 + 5*N */
cmd->wd[2].ndpa_duration = 100;
cmd->wd[2].datarate = snd_obj->bfrp_xpara.rate;
//cmd->wd[2].macid
cmd->wd[2].data_bw = snd_obj->bfrp_xpara.bw;
cmd->wd[2].data_stbc = snd_obj->bfrp_xpara.stbc;
cmd->wd[2].data_ldpc = snd_obj->bfrp_xpara.ldpc;
cmd->wd[2].gi_ltf = snd_obj->bfrp_xpara.gi_ltf;
cmd->wd[2].disdatafb = 1;
if(sta_nr2) {
cmd->wd[2].sifs_tx = 1;
cmd->wd[2].snd_pkt_sel = HAL_SND_PKT_SEL_MID_BFRP;
} else {
cmd->wd[2].sifs_tx = 0;/* Final BFRP */
cmd->wd[2].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_BFRP;
}
cmd->wd[2].ndpa = HAL_SND_PKT_NDPA_HE;
if (sta_nr2) {
cmd->wd[3].txpktsize = 24 + HAL_SND_HE_BFRP_STA_SZ * sta_nr2; /* 2 + 2 + 6 + 6 + 8 + 5*N */
cmd->wd[3].ndpa_duration = 100;
cmd->wd[3].datarate = snd_obj->bfrp_xpara.rate;
cmd->wd[3].data_bw = snd_obj->bfrp_xpara.bw;
cmd->wd[3].data_stbc = snd_obj->bfrp_xpara.stbc;
cmd->wd[3].data_ldpc = snd_obj->bfrp_xpara.ldpc;
cmd->wd[3].gi_ltf = snd_obj->bfrp_xpara.gi_ltf;
cmd->wd[3].disdatafb = 1;
cmd->wd[3].sifs_tx = 0;/* Final BFRP */
cmd->wd[3].snd_pkt_sel = HAL_SND_PKT_SEL_LAST_BFRP;
cmd->wd[3].ndpa = HAL_SND_PKT_NDPA_HE;
}
}
u8 *
rtw_hal_snd_prepare_snd_cmd(void *hal)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
u8 *buf = NULL;
buf = _os_mem_alloc(hal_to_drvpriv(hal_info),
sizeof(struct hal_ax_fwcmd_snd));
return buf;
}
enum rtw_hal_status
rtw_hal_snd_release_snd_cmd(void *hal, u8 *buf)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
do {
if (buf == NULL)
break;
_os_mem_free(hal_to_drvpriv(hal_info), buf,
sizeof(struct hal_ax_fwcmd_snd));
} while (0);
return hstatus;
}
enum rtw_hal_status
rtw_hal_snd_send_fw_cmd(void *hal, u8 *cmd)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "==> rtw_hal_snd_send_fw_cmd \n");
hstatus = hal_mac_ax_send_fw_snd(hal_info,
(struct hal_ax_fwcmd_snd *)cmd);
/*TODO: Dump CMD content */
PHL_TRACE(COMP_PHL_SOUND, _PHL_INFO_, "<== rtw_hal_snd_send_fw_cmd \n");
return hstatus;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_sound.c
|
C
|
agpl-3.0
| 32,242
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_SOUND_H_
#define _HAL_SOUND_H_
#define HAL_NPDA_RU_IDX_START 0
#define HAL_NPDA_RU_IDX_END_20MHZ 8
#define HAL_NPDA_RU_IDX_END_40MHZ 17
#define HAL_NPDA_RU_IDX_END_80MHZ 36
#define HAL_NPDA_RU_IDX_END_160MHZ 73
#define HAL_SND_HE_BFRP_STA_SZ 5
#define HAL_SND_HE_NDPA_STA_SZ 4
#define HAL_SND_VHT_NDPA_STA_SZ 2
#define HAL_SND_VHT_NDPA_FRM_CTRL 0x54
#define HAL_SND_HE_NDPA_FRM_CTRL 0x54
#define HAL_SND_VHT_BFRP_FRM_CTRL 0x44
#define HAL_SND_HE_BFRP_FRM_CTRL 0x24 /* Trigger Frame */
#define HAL_SND_TRIG_INFO_BFRP 0x1
enum hal_snd_pkt_sel {
HAL_SND_PKT_SEL_UST_NDPA = 0,
HAL_SND_PKT_SEL_BST_NDPA =1,
HAL_SND_PKT_SEL_LAST_NDP = 2,
HAL_SND_PKT_SEL_MID_NDP = 3,
HAL_SND_PKT_SEL_MID_BFRP = 4,
HAL_SND_PKT_SEL_LAST_BFRP = 5,
HAL_SND_PKT_SEL_MAX
};
enum hal_snd_pkt_ndpa_type {
HAL_SND_PKT_NDPA_HT = 1,
HAL_SND_PKT_NDPA_VHT = 2,
HAL_SND_PKT_NDPA_HE = 3,
HAL_SND_PKT_NDPA_MAX
};
struct hal_snd_pkt_xmit_para {
enum channel_width bw;
enum rtw_data_rate rate;
enum rtw_gi_ltf gi_ltf;
u8 stbc;
u8 ldpc;
};
struct hal_snd_obj {
struct hal_snd_pkt_xmit_para ndpa_xpara;
struct hal_snd_pkt_xmit_para bfrp_xpara;
};
enum rtw_hal_status hal_snd_obj_init(void *hal);
enum rtw_hal_status hal_snd_obj_deinit(void *hal);
#endif
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_sound.h
|
C
|
agpl-3.0
| 1,902
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HAL_STA_C_
#include "hal_headers.h"
void
_hal_sta_rssi_init(struct rtw_phl_stainfo_t *sta)
{
sta->hal_sta->rssi_stat.assoc_rssi = 0;
sta->hal_sta->rssi_stat.ma_rssi = 0;
}
static enum rtw_hal_status
_hal_bfee_init(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
struct rtw_wifi_role_t *wrole = NULL;
bool enable_bfee = false;
do {
if(NULL == sta)
break;
wrole = sta->wrole;
if(NULL == wrole)
break;
/*only init BFee when wrole cap's bfee and sta cap 's bfer matched */
if ((wrole->proto_role_cap.he_su_bfme ||
wrole->proto_role_cap.he_mu_bfme) &&
(sta->asoc_cap.he_su_bfmr || sta->asoc_cap.he_mu_bfmr)) {
enable_bfee = true;
}
if ((wrole->proto_role_cap.vht_su_bfme ||
wrole->proto_role_cap.vht_mu_bfme) &&
(sta->asoc_cap.vht_su_bfmr || sta->asoc_cap.vht_mu_bfmr)) {
enable_bfee = true;
}
if (wrole->proto_role_cap.ht_su_bfme &&
sta->asoc_cap.ht_su_bfmr)
enable_bfee = true;
if (true == enable_bfee) {
/* BFee Functions */
if (RTW_HAL_STATUS_SUCCESS !=
hal_bf_hw_mac_init_bfee(hal_info,
sta->wrole->hw_band)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : Init HW MAC BFee Fail\n",
__func__);
break;
}
/* BFee CSI parameters*/
hal_info->hal_com->csi_para_ctrl_sel = false;
if (RTW_HAL_STATUS_SUCCESS !=
hal_bf_set_bfee_csi_para(hal_info,
hal_info->hal_com->csi_para_ctrl_sel,
sta)) {
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : Set BFee CSI Para Fail\n",
__func__);
break;
}
#ifdef RTW_WKARD_DYNAMIC_BFEE_CAP
/* BB Workaround */
rtw_hal_bb_dcr_en(hal_info, true);
#endif
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
"%s : Enable HW BFee Function Success\n",
__func__);
}
hstatus = RTW_HAL_STATUS_SUCCESS;
} while (0);
return hstatus;
}
static enum rtw_hal_status
_hal_set_default_cctrl_tbl(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_cctl_info cctrl, cctl_info_mask;
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
u16 cfg;
enum rf_path path = (hal_info->hal_com->rfpath_tx_num == 1)?RF_PATH_B:RF_PATH_AB;
#endif
_os_mem_set(hal_to_drvpriv(hal_info), &cctrl, 0, sizeof(struct mac_ax_cctl_info));
_os_mem_set(hal_to_drvpriv(hal_info), &cctl_info_mask, 0, sizeof(struct mac_ax_cctl_info));
if (NULL == sta)
goto out;
cctrl.txpwr_mode = 0;
cctl_info_mask.txpwr_mode = 0x7;
#ifdef RTW_WKARD_DEF_CMACTBL_CFG
cfg = rtw_hal_bb_cfg_cmac_tx_ant(hal_info, path);
cctrl.ntx_path_en = cfg & 0x0f;
cctl_info_mask.ntx_path_en = 0xF;
cctrl.path_map_a = ((cfg>>4) & 0x03);
cctl_info_mask.path_map_a = 0x3;
cctrl.path_map_b = ((cfg>>6) & 0x03);
cctl_info_mask.path_map_b = 0x3;
cctrl.path_map_c = ((cfg>>8) & 0x03);
cctl_info_mask.path_map_c = 0x3;
cctrl.path_map_d = ((cfg>>10) & 0x03);
cctl_info_mask.path_map_d = 0x3;
#else
cctrl.ntx_path_en = 0x3;
cctl_info_mask.ntx_path_en = 0xF;
cctrl.path_map_a = 0x0;
cctl_info_mask.path_map_a = 0x3;
cctrl.path_map_b = 0x1;
cctl_info_mask.path_map_b = 0x3;
cctrl.path_map_c = 0x2;
cctl_info_mask.path_map_c = 0x3;
cctrl.path_map_d = 0x3;
cctl_info_mask.path_map_d = 0x3;
#endif
cctrl.antsel_a = 0x0;
cctl_info_mask.antsel_a = 0x1;
cctrl.antsel_b = 0x0;
cctl_info_mask.antsel_b = 0x1;
cctrl.antsel_c = 0x0;
cctl_info_mask.antsel_c = 0x1;
cctrl.antsel_d = 0x0;
cctl_info_mask.antsel_d = 0x1;
cctrl.doppler_ctrl = 0;
cctl_info_mask.doppler_ctrl = 0x3;
cctrl.txpwr_tolerence = 0;
cctl_info_mask.txpwr_tolerence = 0xF;
#ifdef CONFIG_PHL_DEFAULT_MGNT_Q_RPT_EN
cctrl.mgq_rpt_en = 1;
cctl_info_mask.mgq_rpt_en = 1;
#endif
sts = rtw_hal_cmc_tbl_cfg(hal_info, &cctrl ,&cctl_info_mask, sta->macid);
out:
return sts;
}
static enum rtw_hal_status
_hal_update_cctrl_tbl(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
struct rtw_wifi_role_t *wrole = sta->wrole;
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_cctl_info cctrl, cctl_info_mask;
_os_mem_set(hal_to_drvpriv(hal_info), &cctrl, 0, sizeof(struct mac_ax_cctl_info));
_os_mem_set(hal_to_drvpriv(hal_info), &cctl_info_mask, 0, sizeof(struct mac_ax_cctl_info));
if (NULL == sta)
goto out;
/*TODO - update cctrl tab from stainfo*/
cctrl.disrtsfb = 1;
cctl_info_mask.disrtsfb = 1;
cctrl.disdatafb = 1;
cctl_info_mask.disdatafb = 1;
/*
if (!cctrl.disdatafb)
cctrl.arfr_ctrl = rtw_hal_bb_get_arfr_idx(hal_info, sta);
*/
if (wrole->cap.rty_lmt_rts == 0xFF) {
cctrl.rts_txcnt_lmt_sel = 0;
} else {
cctrl.rts_txcnt_lmt_sel = 1;
cctrl.rts_txcnt_lmt = wrole->cap.rty_lmt_rts & 0xF;
cctl_info_mask.rts_txcnt_lmt = 0xF;
}
cctl_info_mask.rts_txcnt_lmt_sel = 1;
cctrl.rts_rty_lowest_rate = (sta->chandef.band == BAND_ON_24G) ? (RTW_DATA_RATE_CCK1) : (RTW_DATA_RATE_OFDM6);
cctl_info_mask.rts_rty_lowest_rate = 0xF;
if (wrole->cap.rty_lmt == 0xFF) {
cctrl.data_txcnt_lmt_sel = 0;
} else {
cctrl.data_txcnt_lmt_sel = 1;
cctrl.data_tx_cnt_lmt = wrole->cap.rty_lmt & 0x3F;
cctl_info_mask.data_tx_cnt_lmt = 0x3F;
}
cctl_info_mask.data_txcnt_lmt_sel = 1;
/* hana_todo: follow wd agg_num settings before updating cmac tbl while addba handshake is ready */
/* cctrl.max_agg_num_sel = 1;
cctl_info_mask.max_agg_num_sel = 1;
cctrl.max_agg_num = sta->asoc_cap.num_ampdu - 1;
cctl_info_mask.max_agg_num = 0xFF;
*/
if (cctrl.max_agg_num > 0x3F) {
cctrl.ba_bmap = 1;
cctl_info_mask.ba_bmap = 0x3;
}
if (sta->wrole->type == PHL_RTYPE_STATION || sta->wrole->type == PHL_RTYPE_TDLS) {
cctrl.uldl = 1;
cctl_info_mask.uldl = 1;
} else {
cctrl.uldl = 0;
cctl_info_mask.uldl = 1;
}
cctrl.multi_port_id = sta->wrole->hw_port;
cctl_info_mask.multi_port_id = 0x7;
if (sta->wrole->type == PHL_RTYPE_AP) {
cctrl.data_dcm = 0; /*(sta->asoc_cap.dcm_max_const_rx > 0)*/
cctl_info_mask.data_dcm = 1;
}
if (sta->asoc_cap.pkt_padding == 3) {
/* follow PPE threshold */
u8 ppe16 = 0, ppe8 = 0;
u8 nss = sta->asoc_cap.nss_rx;
/* bw = 20MHz */
ppe16 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_20] & 0x7);
ppe8 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_20]>>3) & 0x7;
if ((ppe16 != 7) && (ppe8 == 7)) {
cctrl.nominal_pkt_padding = 2;
cctl_info_mask.nominal_pkt_padding = 0x3;
} else if (ppe8 != 7) {
cctrl.nominal_pkt_padding = 1;
cctl_info_mask.nominal_pkt_padding = 0x3;
} else {
cctrl.nominal_pkt_padding = 0;
cctl_info_mask.nominal_pkt_padding = 0x3;
}
/* bw = 40MHz */
ppe16 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_40] & 0x7);
ppe8 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_40]>>3) & 0x7;
if ((ppe16 != 7) && (ppe8 == 7)) {
cctrl.nominal_pkt_padding40 = 2;
cctl_info_mask.nominal_pkt_padding40 = 0x3;
} else if (ppe8 != 7) {
cctrl.nominal_pkt_padding40 = 1;
cctl_info_mask.nominal_pkt_padding40 = 0x3;
} else {
cctrl.nominal_pkt_padding40 = 0;
cctl_info_mask.nominal_pkt_padding40 = 0x3;
}
/* bw = 80MHz */
ppe16 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_80] & 0x7);
ppe8 = (sta->asoc_cap.ppe_thr[nss - 1][CHANNEL_WIDTH_80]>>3) & 0x7;
if ((ppe16 != 7) && (ppe8 == 7)) {
cctrl.nominal_pkt_padding80 = 2;
cctl_info_mask.nominal_pkt_padding80 = 0x3;
} else if (ppe8 != 7) {
cctrl.nominal_pkt_padding80 = 1;
cctl_info_mask.nominal_pkt_padding80 = 0x3;
} else {
cctrl.nominal_pkt_padding80 = 0;
cctl_info_mask.nominal_pkt_padding80 = 0x3;
}
} else {
cctrl.nominal_pkt_padding = sta->asoc_cap.pkt_padding;
cctrl.nominal_pkt_padding40 = sta->asoc_cap.pkt_padding;
cctrl.nominal_pkt_padding80 = sta->asoc_cap.pkt_padding;
cctl_info_mask.nominal_pkt_padding = 0x3;
cctl_info_mask.nominal_pkt_padding40 = 0x3;
cctl_info_mask.nominal_pkt_padding80 = 0x3;
}
if (sta->wmode&WLAN_MD_11AX) {
/**
* bsr_queue_size_format:
* 1: buffer status unit is 802.11, HE mode
* 0: buffer status unit is 802.11, legacy mode
**/
cctrl.bsr_queue_size_format = 1;
cctl_info_mask.bsr_queue_size_format = 1;
}
sts = rtw_hal_cmc_tbl_cfg(hal_info, &cctrl, &cctl_info_mask, sta->macid);
out:
return sts;
}
static enum rtw_hal_status
_hal_update_dctrl_tbl(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
struct mac_ax_dctl_info dctrl, dctl_info_mask;
if (NULL == sta)
goto out;
_os_mem_set(hal_to_drvpriv(hal_info), &dctrl, 0, sizeof(struct mac_ax_dctl_info));
_os_mem_set(hal_to_drvpriv(hal_info), &dctl_info_mask, 0, sizeof(struct mac_ax_dctl_info));
#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
dctrl.chksum_offload_en = 1;
dctl_info_mask.chksum_offload_en = 1;
dctrl.with_llc = 1;
dctl_info_mask.with_llc = 1;
#endif /*CONFIG_PHL_CSUM_OFFLOAD_RX*/
sts = rtw_hal_dmc_tbl_cfg(hal_info, &dctrl, &dctl_info_mask, sta->macid);
out:
return sts;
}
enum rtw_hal_status
_hal_update_ba_cam(struct hal_info_t *hal_info, u8 valid, u16 macid,
u8 dialog_token, u16 timeout, u16 start_seq_num,
u16 ba_policy, u16 tid, u16 buf_size, u8 camid)
{
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
void *drv = hal_to_drvpriv(hal_info);
struct mac_ax_bacam_info ba_cam = {0};
FUNCIN();
_os_mem_set(drv, &ba_cam, 0, sizeof(ba_cam));
ba_cam.valid = valid;
ba_cam.init_req = 1;
ba_cam.entry_idx = camid;
ba_cam.tid = tid;
ba_cam.macid = (u8)macid;
if (buf_size > 64)
ba_cam.bmap_size = 4;
else
ba_cam.bmap_size = 0;
ba_cam.ssn = start_seq_num;
PHL_INFO("[BACAM] ba_cam.valid = %d, ba_cam.init_req = %d, ba_cam.entry_idx = %d\n",
ba_cam.valid,
ba_cam.init_req,
ba_cam.entry_idx);
PHL_INFO("[BACAM] ba_cam.tid = %d, ba_cam.macid = %d, ba_cam.bmap_size = %d\n",
ba_cam.tid,
ba_cam.macid,
ba_cam.bmap_size);
PHL_INFO("[BACAM] ba_cam.ssn = 0x%X\n",
ba_cam.ssn);
hal_status = rtw_hal_bacam_cfg(hal_info, &ba_cam);
if (RTW_HAL_STATUS_FAILURE == hal_status) {
PHL_WARN("rtw_hal_bacam_cfg fail 0x%08X\n", hal_status);
}
FUNCOUT();
return hal_status;
}
enum rtw_hal_status
rtw_hal_start_ba_session(void *hal, struct rtw_phl_stainfo_t *sta,
u8 dialog_token, u16 timeout, u16 start_seq_num,
u16 ba_policy, u16 tid, u16 buf_size)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 idx = 0;
if (sta->hal_sta->ba_ctl.count == MAX_BAENTRY) {
PHL_INFO("No avail standard entry found\n");
if (tid != 0)
goto out;
else {
for (idx = 0; idx < MAX_BAENTRY; idx++) {
if (sta->hal_sta->ba_ctl.tid[idx] != 0) {
PHL_INFO("Remove old entry(%d) tid(%d)\n",
idx, sta->hal_sta->ba_ctl.tid[idx]);
hal_status = _hal_update_ba_cam(hal_info, 0, sta->macid, 0,
0, 0, 0, 0, 0, idx);
if (hal_status == RTW_HAL_STATUS_SUCCESS) {
sta->hal_sta->ba_ctl.used_map[idx] = false;
sta->hal_sta->ba_ctl.count--;
break;
}
} else {
PHL_INFO("Use existing entry(%d)\n", idx);
sta->hal_sta->ba_ctl.used_map[idx] = false;
sta->hal_sta->ba_ctl.count--;
break;
}
}
}
}
for (idx = 0; idx < MAX_BAENTRY; idx++) {
if (!sta->hal_sta->ba_ctl.used_map[idx])
break;
}
if (idx == MAX_BAENTRY) {
PHL_WARN("No avail standard entry found but count is(%d)\n",
sta->hal_sta->ba_ctl.count);
goto out;
}
hal_status = _hal_update_ba_cam(hal_info, 1, sta->macid, dialog_token,
timeout, start_seq_num, ba_policy, tid,
buf_size, idx);
if (RTW_HAL_STATUS_SUCCESS != hal_status)
goto out;
sta->hal_sta->ba_ctl.used_map[idx] = 1;
sta->hal_sta->ba_ctl.tid[idx] = (u8)tid;
sta->hal_sta->ba_ctl.count++;
out:
return hal_status;
}
enum rtw_hal_status
rtw_hal_stop_ba_session(void *hal, struct rtw_phl_stainfo_t *sta, u16 tid)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
u8 i;
for (i = 0; i < MAX_BAENTRY; i++) {
if (sta->hal_sta->ba_ctl.used_map[i] &&
((u8)tid == sta->hal_sta->ba_ctl.tid[i])) {
hal_status = _hal_update_ba_cam(hal_info, 0, sta->macid, 0,
0, 0, 0, 0, 0, i);
break;
}
}
if (RTW_HAL_STATUS_SUCCESS != hal_status)
goto out;
sta->hal_sta->ba_ctl.used_map[i] = 0;
sta->hal_sta->ba_ctl.tid[i] = 0xff;
sta->hal_sta->ba_ctl.count--;
out:
return hal_status;
}
enum rtw_hal_status
rtw_hal_stainfo_init(void *hal, struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
void *drv = hal_to_drvpriv(hal_info);
sta->hal_sta = _os_mem_alloc(drv, sizeof(struct rtw_hal_stainfo_t));
if (sta->hal_sta == NULL) {
PHL_ERR("alloc hal_sta failed\n");
goto error_exit;
}
sta->hal_sta->hw_cfg_tab =
_os_mem_alloc(drv, sizeof(struct rtw_hw_cfg_tab));
if (sta->hal_sta->hw_cfg_tab == NULL) {
PHL_ERR("alloc hw_cfg_tab failed\n");
goto error_hsta_mem;
}
hal_status = rtw_hal_bb_stainfo_init(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("alloc bb_stainfo failed\n");
goto error_hw_cfg_tab;
}
/* Init lock for tx statistics */
_os_spinlock_init(drv, &sta->hal_sta->trx_stat.tx_sts_lock);
/* Init STA RSSI Statistics */
_hal_sta_rssi_init(sta);
return hal_status;
error_hw_cfg_tab :
if (sta->hal_sta->hw_cfg_tab) {
_os_mem_free(drv, sta->hal_sta->hw_cfg_tab,
sizeof(struct rtw_hw_cfg_tab));
sta->hal_sta->hw_cfg_tab = NULL;
}
error_hsta_mem :
if (sta->hal_sta) {
_os_mem_free(drv, sta->hal_sta,
sizeof(struct rtw_hal_stainfo_t));
sta->hal_sta = NULL;
}
error_exit :
return hal_status;
}
enum rtw_hal_status
rtw_hal_stainfo_deinit(void *hal, struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
void *drv = hal_to_drvpriv(hal_info);
if (sta->hal_sta) {
/* Free lock for tx statistics */
_os_spinlock_free(drv, &sta->hal_sta->trx_stat.tx_sts_lock);
hal_status = rtw_hal_bb_stainfo_deinit(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("bb_stainfo deinit failed\n");
if (sta->hal_sta->hw_cfg_tab) {
_os_mem_free(drv, sta->hal_sta->hw_cfg_tab,
sizeof(struct rtw_hw_cfg_tab));
sta->hal_sta->hw_cfg_tab = NULL;
}
_os_mem_free(drv, sta->hal_sta,
sizeof(struct rtw_hal_stainfo_t));
sta->hal_sta = NULL;
}
return hal_status;
}
static void _hal_sta_set_default_value(struct hal_info_t *hal_info,
struct rtw_phl_stainfo_t *sta)
{
u8 i;
sta->hal_sta->ra_info.ra_registered = false;
sta->hal_sta->ba_ctl.count = 0;
for (i = 0; i<MAX_BAENTRY; i++) {
sta->hal_sta->ba_ctl.tid[i] = 0xff;
sta->hal_sta->ba_ctl.used_map[i] = 0;
}
}
enum rtw_hal_status
rtw_hal_add_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
_hal_sta_set_default_value(hal_info, sta);
/*add mac address-cam*/
if (rtw_hal_mac_addr_cam_add_entry(hal_info, sta) !=
RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_mac_addr_cam_add_entry failed\n");
goto _exit;
}
/*update default cmac table*/
if (_hal_set_default_cctrl_tbl(hal_info, sta) !=
RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("_hal_set_default_cctrl_tbl failed\n");
/* goto _exit; */ /* shall be unmark after header FW is ready */
}
if (_hal_update_dctrl_tbl(hal_info, sta) !=
RTW_HAL_STATUS_SUCCESS) {
PHL_WARN("_hal_set_default_dctrl_tbl failed\n");
/* goto _exit; */
}
/*add bb stainfo*/
if (rtw_hal_bb_stainfo_add(hal_info, sta) !=
RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_bb_stainfo_add failed\n");
goto _err_bbsta_add;
}
return RTW_HAL_STATUS_SUCCESS;
_err_bbsta_add:
rtw_hal_mac_addr_cam_del_entry(hal_info, sta);
_exit:
return RTW_HAL_STATUS_FAILURE;
}
enum rtw_hal_status
rtw_hal_update_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta,
bool is_connect)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
enum phl_upd_mode mode = PHL_UPD_STA_CON_DISCONN;
/*update cmac table*/
if (RTW_HAL_STATUS_SUCCESS != _hal_update_cctrl_tbl(hal_info, sta))
PHL_WARN("_hal_update_cctrl_tbl failed\n");
/*update dmac table*/
if (RTW_HAL_STATUS_SUCCESS != _hal_update_dctrl_tbl(hal_info, sta))
PHL_WARN("_hal_update_dctrl_tbl failed\n");
/*change mac address-cam & mac_h2c_join_info*/
hal_status = rtw_hal_mac_addr_cam_change_entry(hal_info, sta, mode, is_connect);
if (hal_status != RTW_HAL_STATUS_SUCCESS) {
PHL_ERR("rtw_hal_mac_addr_cam_change_entry failed\n");
}
if (is_connect) {
if (RTW_HAL_STATUS_SUCCESS != _hal_bfee_init(hal_info, sta)) {
PHL_ERR("_hal_bfee_init Fail!\n");
}
if (sta->hal_sta->rssi_stat.assoc_rssi == 0
#ifdef CONFIG_PHL_TDLS
/* There is no association frame for TDLS connection */
&& sta->wrole->type != PHL_RTYPE_TDLS
#endif
) {
PHL_ERR("%s macid:%d assoc_rssi == 0\n", __func__, sta->macid);
_os_warn_on(1);
}
hal_status = rtw_hal_bb_upt_ramask(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("rtw_hal_bb_upt_ramask failed\n");
hal_status = rtw_hal_bb_ra_register(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("rtw_hal_bb_ra_register failed\n");
hal_info->hal_com->assoc_sta_cnt++;
if (sta->wmode & WLAN_MD_11AX) {
rtw_hal_bb_set_sta_id(hal_info, sta->aid, sta->wrole->hw_band);
rtw_hal_bb_set_bss_color(hal_info, sta->asoc_cap.bsscolor,
sta->wrole->hw_band);
rtw_hal_bb_set_tb_pwr_ofst(hal_info, 0, sta->wrole->hw_band);
}
/* reset rssi stat value */
sta->hal_sta->rssi_stat.ma_rssi_mgnt = 0;
}
else {
hal_status = rtw_hal_bb_ra_deregister(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("rtw_hal_bb_ra_deregister failed\n");
hal_info->hal_com->assoc_sta_cnt--;
/* reset drv rssi_stat */
_hal_sta_rssi_init(sta);
_hal_sta_set_default_value(hal_info, sta);
}
/* reset bb rssi_stat */
rtw_hal_bb_media_status_update(hal_info, sta, is_connect);
return hal_status;
}
enum rtw_hal_status
rtw_hal_change_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta,
enum phl_upd_mode mode)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
bool is_connect = false;
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s: sta->macid(0x%X), mode(%d)\n",
__FUNCTION__, sta->macid , mode);
/*update cmac table*/
if (RTW_HAL_STATUS_SUCCESS != _hal_update_cctrl_tbl(hal_info, sta))
PHL_WARN("_hal_update_cctrl_tbl failed\n");
/*update dmac table*/
if (RTW_HAL_STATUS_SUCCESS != _hal_update_dctrl_tbl(hal_info, sta))
PHL_WARN("_hal_update_dctrl_tbl failed\n");
/*change mac address-cam & mac_h2c_join_info */
is_connect = (sta->wrole->mstate == MLME_LINKED) ? true : false;
hal_status = rtw_hal_mac_addr_cam_change_entry(hal_info, sta, mode, is_connect);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("rtw_hal_mac_addr_cam_change_entry failed\n");
hal_status = rtw_hal_bb_ra_update(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("rtw_hal_bb_ra_update failed\n");
return hal_status;
}
enum rtw_hal_status
rtw_hal_del_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
_hal_sta_set_default_value(hal_info, sta);
hal_status = rtw_hal_mac_addr_cam_del_entry(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("mac_addr_cam_del_entry failed\n");
hal_status = rtw_hal_bb_stainfo_delete(hal_info, sta);
if (hal_status != RTW_HAL_STATUS_SUCCESS)
PHL_ERR("bb_stainfo deinit failed\n");
return hal_status;
}
u8 rtw_hal_get_sta_rssi(struct rtw_phl_stainfo_t *sta)
{
u8 rssi = (sta->hal_sta->rssi_stat.rssi >> 1);
return rssi;
}
u8 rtw_hal_get_sta_rssi_bcn(struct rtw_phl_stainfo_t *sta)
{
u8 rssi = (sta->hal_sta->rssi_stat.rssi_bcn >> 1);
return rssi;
}
bool rtw_hal_is_sta_linked(void *hal, struct rtw_phl_stainfo_t *sta)
{
return (sta->hal_sta->ra_info.ra_registered == true) ? true : false;
}
enum rtw_hal_status
rtw_hal_set_edca(void *hal, struct rtw_wifi_role_t *wrole, u8 ac, u32 edca)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hal_status;
hal_status = rtw_hal_mac_set_edca(hal_info->hal_com, wrole->hw_band,
wrole->hw_wmm, ac, edca);
return hal_status;
}
enum rtw_hal_status
rtw_hal_cfg_tx_ampdu(void *hal, struct rtw_phl_stainfo_t *sta)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
/* update ampdu configuration */
if (64 == sta->asoc_cap.num_ampdu)
hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, 0, 0x3F, 0xA5);
else if (128 == sta->asoc_cap.num_ampdu)
hsts = rtw_hal_mac_set_hw_ampdu_cfg(hal_info, 0, 0x7F, 0xAB);
if (RTW_HAL_STATUS_SUCCESS != hsts)
goto out;
/* todo: update cmac table */
out:
return hsts;
}
enum rtw_hal_status
rtw_hal_set_sta_rx_sts(struct rtw_phl_stainfo_t *sta, u8 rst,
struct rtw_r_meta_data *meta)
{
if (rst) {
sta->hal_sta->trx_stat.rx_ok_cnt = 0;
sta->hal_sta->trx_stat.rx_err_cnt = 0;
} else {
if (meta->crc32 || meta->icverr)
sta->hal_sta->trx_stat.rx_err_cnt++;
else
sta->hal_sta->trx_stat.rx_ok_cnt++;
}
/* TODO: rx_rate_plurality */
return RTW_HAL_STATUS_SUCCESS;
}
enum rtw_hal_status
rtw_hal_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta,
struct rtw_phl_rainfo *phl_rainfo)
{
enum rtw_hal_status hal_sts = RTW_HAL_STATUS_FAILURE;
hal_sts = rtw_hal_bb_query_rainfo(hal, hal_sta, phl_rainfo);
return hal_sts;
}
/**
* rtw_hal_query_txsts_rpt() - get txok and tx retry info
* @hal: struct hal_info_t *
* @macid: indicate the first macid that you want to query.
* Return rtw_hal_bb_query_txsts_rpt's return value in enum rtw_hal_status type.
*/
enum rtw_hal_status
rtw_hal_query_txsts_rpt(void *hal, u16 macid)
{
struct hal_info_t *hal_info = (struct hal_info_t *)hal;
/*get tx ok and tx retry statistics*/
if (RTW_HAL_STATUS_SUCCESS != rtw_hal_bb_query_txsts_rpt(hal_info, macid, 0xFFFF))
return RTW_HAL_STATUS_FAILURE;
else
return RTW_HAL_STATUS_SUCCESS;
}
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_sta.c
|
C
|
agpl-3.0
| 23,025
|
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_STA_H_
#define _HAL_STA_H_
struct rtw_hw_cfg_tab {
u8 dummy;
};
enum rtw_hal_status
rtw_hal_update_sta_entry(void *hal, struct rtw_phl_stainfo_t *sta,
bool is_connect);
#endif /*_HAL_STA_H_*/
|
2301_81045437/rtl8852be
|
phl/hal_g6/hal_sta.h
|
C
|
agpl-3.0
| 866
|