repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 1,701 | sim/testsuite/bfin/c_dsp32alu_bytepack.s | //Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp
// Spec Reference: dsp32alu bytepack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0... |
stsp/binutils-ia16 | 3,122 | sim/testsuite/bfin/c_dsp32mac_pair_a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp
// Spec Reference: dsp32mac pair a0 m (M, MNOP)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa... |
stsp/binutils-ia16 | 1,075 | sim/testsuite/bfin/c_brcc_brf_brt_nbp.s | //Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp
// Spec Reference: brcc brf brt no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7,... |
stsp/binutils-ia16 | 5,543 | sim/testsuite/bfin/viterbi2.s | # mach: bfin
// The assembly program uses two instructions to speed the decoder inner loop:
// R6= VMAX/VMAX (R5, R4) A0>>2;
// R2 =H+L (SGN(R0)*R1);
// VMAX is a 2-way parallel comparison of four updated path metrics, resulting
// in 2 new path metrics as well as a 2 bit field indicating the selection
// res... |
stsp/binutils-ia16 | 1,952 | sim/testsuite/bfin/c_ldimmhalf_lzhi_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lzhi_pr/c_ldimmhalf_lzhi_pr.dsp
// Spec Reference: ldimmhalf lzhi preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Preg
//lz(p0)=0x0001;
//h(p0) =0x0000;
P1 = 0x0003 (Z);
P1.H = 0x0002;
P2 = 0x0005 (Z);
P2.H = 0x0004;
P3 = 0x0007 (Z);... |
stsp/binutils-ia16 | 2,175 | sim/testsuite/bfin/c_ccmv_cc_pr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_cc_pr_pr/c_ccmv_cc_pr_pr.dsp
// Spec Reference: ccmv cc preg = preg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 p1, 0xd0021053;
imm32 p2, 0x2f041405;
imm32 p3, 0x60b61507;
imm32 p4, 0x50487609;
imm32 p5, 0x3005900b;
imm32 sp, 0x2a0c660... |
stsp/binutils-ia16 | 4,133 | sim/testsuite/bfin/c_alu2op_conv_xb.s | //Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp
// Spec Reference: alu2op convert xb
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89... |
stsp/binutils-ia16 | 2,751 | sim/testsuite/bfin/abs_acc.s | // ACP 5.7 ABS(A1) sets AV0
# mach: bfin
.include "testutils.inc"
start
r1=0x80 (z);
A0=0;
A0.x=r1;
A0=abs A0;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x3);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
db... |
stsp/binutils-ia16 | 6,227 | sim/testsuite/bfin/se_bug_ui.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include... |
stsp/binutils-ia16 | 23,117 | sim/testsuite/bfin/se_undefinedinstruction4.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction4/se_undefinedinstruction4.dsp
// Description: 64 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
... |
stsp/binutils-ia16 | 1,575 | sim/testsuite/bfin/push-pop.s | # Blackfin testcase for push/pop instructions
# mach: bfin
.include "testutils.inc"
start
# This uses R0/R1 as scratch ... assume those work fine in general
.macro check loader:req, reg:req
\loader \reg, 0x12345678
[--SP] = \reg;
R0 = [SP];
R1 = \reg;
CC = R0 == R1;
IF !CC JUMP 8f;
\loader \reg, 0x8765432... |
stsp/binutils-ia16 | 9,518 | sim/testsuite/bfin/lmu_excpt_prot0.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp
// Description: LMU protection exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test ... |
stsp/binutils-ia16 | 1,850 | sim/testsuite/bfin/c_compi2opp_pr_eq_i7_p.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_p/c_compi2opp_pr_eq_i7_p.dsp
// Spec Reference: compi2opd pregs = imm7 positive
# mach: bfin
.include "testutils.inc"
start
//R0 = 0;
P1 = 1;
P2 = 2;
P3 = 3;
P4 = 4;
P5 = 5;
SP = 6;
FP = 7;
CHECKREG p1, 1;
CHECKREG p2, 2;
CHECKREG p3, 3;
CHE... |
stsp/binutils-ia16 | 1,688 | sim/testsuite/bfin/s3.s | // SHIFT test program.
// Test A0 = ASHIFT (A0 by r3);
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0000001f
// load r1=0x00000020
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x00000001
// load r5=0x00000080
loadsym P0, data0;
P1 = P0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R... |
stsp/binutils-ia16 | 1,570,263 | sim/testsuite/bfin/se_all32bitopcodes.S | /*
* Blackfin testcase for testing illegal/legal 32-bit opcodes from userspace
* we track all instructions which cause some sort of exception when run from
* userspace, this is normally EXCAUSE :
* - 0x21 : illegal instruction
* - 0x22 : illegal instruction combination
* - 0x2e : use of supervisor resource fro... |
stsp/binutils-ia16 | 5,625 | sim/testsuite/bfin/c_regmv_imlb_dep_stall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp
// Spec Reference: regmv imlb-depepency stall
# mach: bfin
.include "testutils.inc"
start
// R-reg to I,M-reg to R-reg: stall
imm32 r0, 0x00001110;
imm32 r1, 0x00213330;
imm32 r2, 0x04015550;
imm32 r3, 0x06607770;
imm32 r... |
stsp/binutils-ia16 | 9,027 | sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_rtx_lsmmrj_mvp/c_seq_wb_rtx_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( rtx ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
stsp/binutils-ia16 | 5,502 | sim/testsuite/bfin/c_logi2op_arith_shft.s | //Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp
// Spec Reference: Logi2op >>>=
# mach: bfin
.include "testutils.inc"
start
// Arithmetic >>>= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5... |
stsp/binutils-ia16 | 14,881 | sim/testsuite/bfin/c_logi2op_nbittst.s | //Original:/testcases/core/c_logi2op_nbittst/c_logi2op_nbittst.dsp
// Spec Reference: Logi2op !bittst
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00... |
stsp/binutils-ia16 | 1,456 | sim/testsuite/bfin/a23.s | // Test ALU ABS accumulators
# mach: bfin
.include "testutils.inc"
start
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000001;
A0.w = R0;
R0 = 0x80 (X);... |
stsp/binutils-ia16 | 4,523 | sim/testsuite/bfin/c_dsp32alu_disalnexcpt.s | //Original:/testcases/core/c_dsp32alu_disalnexcpt/c_dsp32alu_disalnexcpt.dsp
// Spec Reference: c_dsp32alu_disalgnexcpt
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym P0, DATA1;
P0 += 1; I0 = P0;
loadsym P0, DATA2;
P0 += 1; I1 = P0;
loadsym P0, DATA3;
P0 += 1; I2 = P0;
loadsym P0, DATA4;... |
stsp/binutils-ia16 | 1,209 | sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp
// Spec Reference: ccmv !cc dpreg = dpreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x138d2301;
imm32 r1, 0x20421053;
imm32 r2, 0x3f051405;
imm32 r3, 0x40b66507;
imm32 r4, 0x50487709;
imm32 r5, 0x60... |
stsp/binutils-ia16 | 4,425 | sim/testsuite/bfin/c_alu2op_divs.s | //Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp
// Spec Reference: alu2op divide s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R... |
stsp/binutils-ia16 | 2,825 | sim/testsuite/bfin/c_dsp32alu_byteunpack.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp
// Spec Reference: dsp32alu byteunpack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r... |
stsp/binutils-ia16 | 1,036 | sim/testsuite/bfin/m16.s | // Test various moves to single register half
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7fffffff
// load r1=0x00ffffff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extract... |
stsp/binutils-ia16 | 11,801 | sim/testsuite/bfin/se_loop_mv2lb_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lb_stall/se_loop_mv2lb_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
stsp/binutils-ia16 | 1,470 | sim/testsuite/bfin/c_ldimmhalf_h_dr.s | //Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp
// Spec Reference: ldimmhalf h dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.H = 0x0000;
R1.H = 0x0002;
R2.H = 0x0004;
R3.H = 0x0006;
R4.H = 0x0008;
R5.H = 0x000a;
R6.H = 0x000c;
R7.H = 0x000e;
CHECKREG r0, 0x0000... |
stsp/binutils-ia16 | 1,232 | sim/testsuite/bfin/stk6.s | // setup a dummy stack and put values in memory 0,1,2,3...n
// then restore registers with pop instruction.
# mach: bfin
.include "testutils.inc"
start
SP += -12;
P1 = SP;
R1 = 0;
P5.L = 0xdead;
SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5
P4 = (8+6); // 8 data re... |
stsp/binutils-ia16 | 8,302 | sim/testsuite/bfin/c_ldstpmod_ld_h_xh.s | //Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp
// Spec Reference: c_ldstpmod load dreg h & xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0002;
P2 = 0x0002;
P... |
stsp/binutils-ia16 | 3,020 | sim/testsuite/bfin/c_dsp32shiftim_lmix.s | //Original:/testcases/core/c_dsp32shiftim_lmix/c_dsp32shiftim_lmix.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: mix
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Lshift (Logical )
// Lshift : positive data, count (+)=left... |
stsp/binutils-ia16 | 1,107 | sim/testsuite/bfin/c_ldimmhalf_dreg.s | //Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp
// Spec Reference: ldimmhalf dreg imm16
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0123 (X);
R1 = 0x1234 (X);
R2 = 0x2345 (X);
R3 = 0x3456 (X);
R4 = 0x4567 (X);
R5 = 0x5678 (X);
R6 = 0x6789 (X);
R7 = 0x789a (X);
... |
stsp/binutils-ia16 | 3,770 | sim/testsuite/bfin/c_regmv_dr_dr.s | //Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp
// Spec Reference: regmv dreg-to-dreg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to R-reg move
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000... |
stsp/binutils-ia16 | 8,716 | sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_rti_lsmmrj_mvp/c_seq_wb_rti_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( rti ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
stsp/binutils-ia16 | 8,348 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_ln.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
im... |
stsp/binutils-ia16 | 8,819 | sim/testsuite/bfin/c_ccflag_pr_imm3.s | //Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp
// Spec Reference: ccflag pr-imm3
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00000001;
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000001;
imm32 p5, 0x00000002;
imm32 sp, 0x00000003;
i... |
stsp/binutils-ia16 | 2,744 | sim/testsuite/bfin/c_ldimmhalf_l_ibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp
// Spec Reference: ldimmhalf l ibml
# mach: bfin
.include "testutils.inc"
start
INIT_I_REGS -1;
INIT_L_REGS -1;
INIT_M_REGS -1;
INIT_B_REGS -1;
I0.L = 0x2001;
I1.L = 0x2003;
I2.L = 0x2005;
I3.L = 0x2007;
L0.L = 0x2009;
L1.L ... |
stsp/binutils-ia16 | 7,970 | sim/testsuite/bfin/c_ldstpmod_ld_dreg.s | //Original:testcases/core/c_ldstpmod_ld_dreg/c_ldstpmod_ld_dreg.dsp
// Spec Reference: c_ldstpmod load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0004;
P2 = 0x0004;
P3 = 0x0004;
P4 = 0x00... |
stsp/binutils-ia16 | 3,192 | sim/testsuite/bfin/c_dsp32mac_pair_a1.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp
// Spec Reference: dsp32mac pair a1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 ... |
stsp/binutils-ia16 | 3,836 | sim/testsuite/bfin/c_ccflag_dr_imm3_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3_uu/c_ccflag_dr_imm3_uu.dsp
// Spec Reference: ccflag dr-imm3 (uu)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00000002;
imm32 r2, 0x00000003;
imm32 r3, 0x00000004;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb... |
stsp/binutils-ia16 | 5,429 | sim/testsuite/bfin/c_dsp32alu_rmp.s | //Original:/testcases/core/c_dsp32alu_rmp/c_dsp32alu_rmp.dsp
// Spec Reference: dsp32alu dreg = -/+ ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm... |
stsp/binutils-ia16 | 4,130 | sim/testsuite/bfin/c_alu2op_conv_h.s | //Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp
// Spec Reference: alu2op convert h
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abc... |
stsp/binutils-ia16 | 6,286 | sim/testsuite/bfin/c_dsp32mult_dr_s.s | //Original:/testcases/core/c_dsp32mult_dr_s/c_dsp32mult_dr_s.dsp
// Spec Reference: dsp32mult single dr s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
stsp/binutils-ia16 | 1,096 | sim/testsuite/bfin/c_brcc_brf_brt_bp.s | //Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp
// Spec Reference: brcc brfbrt
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000444;
imm32 r5, 0x00000555;
imm32 r6, 0x00000000;
imm32 r7, 0x000000... |
stsp/binutils-ia16 | 1,052 | sim/testsuite/bfin/c_brcc_bp1.s | //Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT =... |
stsp/binutils-ia16 | 9,932 | sim/testsuite/bfin/c_dsp32shift_ahalf_rp.s | //Original:/testcases/core/c_dsp32shift_ahalf_rp/c_dsp32shift_ahalf_rp.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
imm32... |
stsp/binutils-ia16 | 2,930 | sim/testsuite/bfin/c_loopsetup_overlap.s | //Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp
// Spec Reference: loopsetup overlap
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50... |
stsp/binutils-ia16 | 11,845 | sim/testsuite/bfin/dbg_brtkn_nprd_src_kill.S | //Original:/proj/frio/dv/testcases/debug/dbg_brtkn_nprd_src_kill/dbg_brtkn_nprd_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a
// branch source instruction that is taken but not predicted getting killed
// at each stage in the pipe. The test consists of 8 instances of an EXCPT
// ... |
stsp/binutils-ia16 | 1,462 | sim/testsuite/bfin/stk3.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 =... |
stsp/binutils-ia16 | 1,671 | sim/testsuite/bfin/c_dsp32alu_r_negneg.s | //Original:/testcases/core/c_dsp32alu_r_negneg/c_dsp32alu_r_negneg.dsp
// Spec Reference: dsp32alu dregs = neg / neg dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3b44b515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x744... |
stsp/binutils-ia16 | 1,820 | sim/testsuite/bfin/cec-raise-reti.S | # Blackfin testcase for having RETI set correctly
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
start
# First mark all EVTs as fails (t... |
stsp/binutils-ia16 | 5,247 | sim/testsuite/bfin/acc-rot.s | # Blackfin testcase for Accumulator Rotates (ROT)
# mach: bfin
.include "testutils.inc"
.macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req
imm32 R0, \val_w
imm32 R1, \val_x
R2 = \cc;
R3 = \shift
\acc\().W = R0;
\acc\().X = R1;
CC = R2;
.endm
.macro atest_check acc:req, exp_x:req, exp_w:re... |
stsp/binutils-ia16 | 3,017 | sim/testsuite/bfin/s11.s | # mach: bfin
// Shift test program.
// Test instructions
// RL0 = CC = BXOR (A0 AND R1) << 1;
// RL0 = CC = BXOR A0 AND R1;
// A0 <<=1 (BXOR A0 AND A1 CC);
// RL3 = CC = BXOR A0 AND A1 CC;
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// RL0 = CC = BXOR (A0 AND R1) << 1;
R0.L = 0x1000;
R0.H... |
stsp/binutils-ia16 | 14,926 | sim/testsuite/bfin/c_compi2opd_flags.S | //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp
// Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = R0; // initialize astat
// AZ for R0
imm32 r0, 0x00000000;
R0 += 0; // az = 1 a... |
stsp/binutils-ia16 | 5,109 | sim/testsuite/bfin/c_dsp32shift_expadj_h.s | //Original:/testcases/core/c_dsp32shift_expadj_h/c_dsp32shift_expadj_h.dsp
// Spec Reference: dsp32shift expadj rh
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x80000008;
imm32 r1, 0x80010008;
imm32 r2, 0x80020008;
imm32 r3, 0x80030008;
imm32 r4, 0x80040008;
imm32 r5, 0x80050008;
imm32 r6, 0x80060008;
i... |
stsp/binutils-ia16 | 4,341 | sim/testsuite/bfin/c_dsp32shift_af.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_af/c_dsp32shift_af.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// ashift : mix data, count (+)= (half reg)
// d_reg = ashift (d BY d_lo)
// Rx by ... |
stsp/binutils-ia16 | 10,050 | sim/testsuite/bfin/c_dsp32shift_ahalf_lp.s | //Original:/testcases/core/c_dsp32shift_ahalf_lp/c_dsp32shift_ahalf_lp.dsp
// Spec Reference: dsp32shift ashift half reg left positive
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000... |
stsp/binutils-ia16 | 2,606 | sim/testsuite/bfin/random_0037.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x1880c200 | _VS | _AV1S | _AV0S | _AC1);
dmm32 A0.w, 0x2b9a5661;
dmm32 A0.x, 0x00000032;
dmm32 A1.w, 0x1a0c4c8c;
dmm32 A1.x, 0xffffff80;
imm32 R0, 0x694a9cb0;
imm32 R6, 0x651cc0dd;
A1 += R0.L * R0.H (M), R6.L = (A0 += R0.L * R0.H) (... |
stsp/binutils-ia16 | 1,177 | sim/testsuite/bfin/m12.s | // Test extraction from accumulators:
// SCALE in SIGNED INTEGER mode
# mach: bfin
.include "testutils.inc"
start
// load r0=0x00000fff
// load r1=0x00007fff
// load r2=0xffffffff
// load r3=0xffff0fff
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R... |
stsp/binutils-ia16 | 2,983 | sim/testsuite/bfin/a6.s | // ALU test program.
// Test instructions
// r7 = +/+ (r0,r1);
// r7 = +/+ (r0,r1) s;
// r7 = +/+ (r0,r1) sx;
# mach: bfin
.include "testutils.inc"
start
// one result overflows positive
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x8000... |
stsp/binutils-ia16 | 8,478 | sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_raisecs_lsmmrj_mvp/c_seq_wb_raisecs_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb (raise csync ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
inc... |
stsp/binutils-ia16 | 11,838 | sim/testsuite/bfin/c_ldstpmod_st_lohi.s | //Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp
// Spec Reference: c_ldstpmod store dreg lo & hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e600... |
stsp/binutils-ia16 | 3,937 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0_iutsh.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp
// Spec Reference: dsp32mac dr_a1a0 iutsh
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0x... |
stsp/binutils-ia16 | 4,591 | sim/testsuite/bfin/c_dsp32mult_pair_is.s | //Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp
// Spec Reference: dsp32mult pair is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0... |
stsp/binutils-ia16 | 2,713 | sim/testsuite/bfin/se_regmv_usp_sysreg.S | //Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp
// Description: RegMV USP to SYSREG
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(symtable.inc)
//*********... |
stsp/binutils-ia16 | 6,096 | sim/testsuite/bfin/c_dsp32mac_pair_a1_i.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp
// Spec Reference: dsp32mac pair a1 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
... |
stsp/binutils-ia16 | 10,449 | sim/testsuite/bfin/se_stall_if2.S | //Original:/proj/frio/dv/testcases/seq/se_stall_if2/se_stall_if2.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
... |
stsp/binutils-ia16 | 1,157 | sim/testsuite/bfin/m11.s | // Test extraction from accumulators:
// SCALE in SIGNED FRACTIONAL mode
# mach: bfin
.include "testutils.inc"
start
// load r0=0x3fff0000
// load r1=0x0fffc000
// load r2=0x7ff00000
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];... |
stsp/binutils-ia16 | 7,160 | sim/testsuite/bfin/c_ldstpmod_ld_dr_hi.s | //Original:testcases/core/c_ldstpmod_ld_dr_hi/c_ldstpmod_ld_dr_hi.dsp
// Spec Reference: c_ldstpmod load dr hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = ... |
stsp/binutils-ia16 | 10,985 | sim/testsuite/bfin/ashift.s | # Blackfin testcase for ashift
# mach: bfin
.include "testutils.inc"
.macro ashift_test in:req, shift:req, out:req, opt
r0 = \in (Z);
r2.L = \shift;
r2.h = ASHIFT R0.L BY R2.L \opt;
DBGA (r2.h, \out);
.endm
start
/*
* 16-bit ashift and lshift uses a 6-bit signed magnitude, which
* gives a range from -... |
stsp/binutils-ia16 | 3,232 | sim/testsuite/bfin/s18.s | // Immediate dual 16b SHIFT test program.
// Test r4 = ASHIFT/ASHIFT (r2 by 10);
// Test r4 = ASHIFT/ASHIFT (r2 by 10) S;
// Test r4 = LSHIFT/LSHIFT (r2 by 10);
# mach: bfin
.include "testutils.inc"
start
// arithmetic
// left by largest positive magnitude of 15 (0xf)
// 8001 -> 8000
R7 = 0;
ASTAT = R7;
... |
stsp/binutils-ia16 | 5,142 | sim/testsuite/bfin/c_dsp32mac_dr_a1.s | //Original:/testcases/core/c_dsp32mac_dr_a1/c_dsp32mac_dr_a1.dsp
// Spec Reference: dsp32mac dr_a1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0... |
stsp/binutils-ia16 | 7,990 | sim/testsuite/bfin/c_comp3op_dr_or_dr.s | //Original:/testcases/core/c_comp3op_dr_or_dr/c_comp3op_dr_or_dr.dsp
// Spec Reference: comp3op dregs | dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 ... |
stsp/binutils-ia16 | 5,417 | sim/testsuite/bfin/c_dsp32alu_rm.s | //Original:/testcases/core/c_dsp32alu_rm/c_dsp32alu_rm.dsp
// Spec Reference: dsp32alu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34345515;
imm32 r3, 0x46637717;
imm32 r4, 0x5567391b;
imm32 r5, 0x6789a31d;
imm32 r6, 0x744455a5;
imm32 r7, 0x866677a7;
R0 = R0... |
stsp/binutils-ia16 | 4,134 | sim/testsuite/bfin/c_alu2op_conv_xh.s | //Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp
// Spec Reference: alu2op convert xh
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8... |
stsp/binutils-ia16 | 4,780 | sim/testsuite/bfin/c_dsp32mult_dr_m_t.s | //Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp
// Spec Reference: dsp32mult single dr munop t
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
stsp/binutils-ia16 | 3,576 | sim/testsuite/bfin/c_dsp32mac_dr_a1_s.s | //Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp
// Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbabcfec7;
imm32 r2... |
stsp/binutils-ia16 | 8,454 | sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_raise_ls_mmrj_mvp/c_seq_ex3_raise_ls_mmrj_mvp.dsp
// Spec Reference: sequencer stage ex3 (raise+ ldst + mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfchec... |
stsp/binutils-ia16 | 5,532 | sim/testsuite/bfin/c_interr_nested.S | //Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp
// Spec Reference: interrupt nested using raises
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_... |
stsp/binutils-ia16 | 5,957 | sim/testsuite/bfin/c_dsp32alu_rl_rnd20_m.s | //Original:/testcases/core/c_dsp32alu_rl_rnd20_m/c_dsp32alu_rl_rnd20_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x4b677717;
imm32 r4, 0x5678791b;
imm32 r5, 0xc789a71d;
imm32 r6, 0x74445515;
imm3... |
stsp/binutils-ia16 | 14,760 | sim/testsuite/bfin/c_logi2op_bittst.s | //Original:/testcases/core/c_logi2op_bittst/c_logi2op_bittst.dsp
// Spec Reference: Logi2op functions: bittst
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r... |
stsp/binutils-ia16 | 4,640 | sim/testsuite/bfin/c_alu2op_shadd_1.s | //Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp
// Spec Reference: alu2op shadd 1
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bc... |
stsp/binutils-ia16 | 6,097 | sim/testsuite/bfin/c_dsp32mult_dr_ih.s | //Original:/testcases/core/c_dsp32mult_dr_ih/c_dsp32mult_dr_ih.dsp
// Spec Reference: dsp32mult single dr ih
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, ... |
stsp/binutils-ia16 | 5,510 | sim/testsuite/bfin/c_progctrl_csync_mmr.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_csync_mmr/c_progctrl_csync_mmr.dsp
// Spec Reference: csync mmr timer
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS... |
stsp/binutils-ia16 | 4,076 | sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s | //Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp
// Spec Reference: ccflag pr-imm3 (uu)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00000001;
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000004;
imm32 p5, 0x00000005;
imm32 sp, ... |
stsp/binutils-ia16 | 5,667 | sim/testsuite/bfin/c_mode_supervisor.S | //Original:/proj/frio/dv/testcases/core/c_mode_supervisor/c_mode_supervisor.dsp
// Spec Reference: mode_supervisor
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); ... |
stsp/binutils-ia16 | 5,190 | sim/testsuite/bfin/c_interr_pending_2.S | //Original:/proj/frio/dv/testcases/core/c_interr_pending_2/c_interr_pending_2.dsp
// Spec Reference: interr pending (raise)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
#ifnde... |
stsp/binutils-ia16 | 2,839 | sim/testsuite/bfin/c_dsp32mac_dr_a0_i.s | //Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp
// Spec Reference: dsp32mac dr a0 i (signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0x9dbcfec7;
imm32 r2, 0xc9248679;
imm32 r3, 0xd0... |
stsp/binutils-ia16 | 14,295 | sim/testsuite/bfin/c_ldst_st_p_d_pp.s | //Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp
// Spec Reference: c_ldst st_p++ d
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r... |
stsp/binutils-ia16 | 6,562 | sim/testsuite/bfin/c_dsp32alu_rrpm.s | //Original:/testcases/core/c_dsp32alu_rrpm/c_dsp32alu_rrpm.dsp
// Spec Reference: dsp32alu (dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x46677717;
imm32 r0, 0x5567a91b;
imm32 r1, 0x6789aa1d;
imm32 r2, 0x744455a5;
imm32 r3, 0x... |
stsp/binutils-ia16 | 10,027 | sim/testsuite/bfin/c_dsp32shift_lhalf_lp.s | //Original:/testcases/core/c_dsp32shift_lhalf_lp/c_dsp32shift_lhalf_lp.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x0000... |
stsp/binutils-ia16 | 3,011 | sim/testsuite/bfin/c_dsp32mac_pair_a1_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp
// Spec Reference: dsp32mac pair a1 M MNOP
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x63547abd;
imm32 r1, 0x86bc8ec7;
imm32 r2, 0xa86956... |
stsp/binutils-ia16 | 2,315 | sim/testsuite/bfin/dsp_a7.s | /* ALU test program.
* Test instructions
* r7 = +/- (r0,r1);
* r7 = -/+ (r0,r1);
* r7 = -/- (r0,r1);
*/
# mach: bfin
.include "testutils.inc"
start
// test subtraction
R0.L = 0x000f;
R0.H = 0x0010;
R1.L = 0x000f;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|- R1;
DBGA ( R7.L , 0x0000 );
DBGA ( R7... |
stsp/binutils-ia16 | 2,632 | sim/testsuite/bfin/a7.s | # mach: bfin
.include "testutils.inc"
start
R1 = 0;
R0 = 0;
R0 = R1 ^ R0;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 1 );
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
... |
stsp/binutils-ia16 | 2,263 | sim/testsuite/bfin/se_kills2.S | //Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp
// Description: Test se_kill for all supported types of RTL1 instructions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(symtable... |
stsp/binutils-ia16 | 6,107 | sim/testsuite/bfin/c_mmr_ppopm_illegal_adr.S | //Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp
// Spec Reference: mmr ppopm illegal address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef ... |
stsp/binutils-ia16 | 3,002 | sim/testsuite/bfin/c_dsp32shift_bxor.s | //Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp
// Spec Reference: dsp32shift bxor
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
R1 = 58;
A0 = R1;
ASTAT = R0;
imm32 r0, 0x12345678;
imm32 r1, 0x22334455;
imm32 r2, 0x66778890;
imm32 r3, 0xaabbccdd;
imm32 r4, 0x34567890;
imm32 r5, 0xa2d3d5f6;... |
stsp/binutils-ia16 | 4,171 | sim/testsuite/bfin/c_alu2op_log_l_sft.s | //Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp
// Spec Reference: alu2op logical left
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x9... |
stsp/binutils-ia16 | 10,646 | sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s | //Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp
// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I... |
stsp/binutils-ia16 | 8,410 | sim/testsuite/bfin/c_ldst_st_p_d_mm_b.s | //Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp
// Spec Reference: c_ldst st_p-- b byte
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729... |
stsp/binutils-ia16 | 1,660 | sim/testsuite/bfin/m13.s | // Test extraction from accumulators:
// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffffff0
// load r1=0xfffffff0
// load r2=0x0fffffff
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ ... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.