repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 2,963 | sim/testsuite/bfin/c_loopsetup_nested_prelc.s | //Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp
// Spec Reference: loopsetup nested preload lc0 lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x12;
R3 = 0x14;... |
stsp/binutils-ia16 | 1,114 | sim/testsuite/bfin/cec-system-call.S | # Blackfin testcase for returning to the right place while bouncing between
# multiple CEC levels (like in a Linux system call)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym... |
stsp/binutils-ia16 | 5,610 | sim/testsuite/bfin/c_ccflag_dr_dr_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp
// Spec Reference: ccflags dr-dr_uu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
i... |
stsp/binutils-ia16 | 3,814 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp
// Spec Reference: dsp32mac dr_a1a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
imm32 r... |
stsp/binutils-ia16 | 1,626 | sim/testsuite/bfin/c_cc_flag_ccmv_depend.S | //Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp
// Spec Reference: ccflag followed by ccmv (# stalls)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;... |
stsp/binutils-ia16 | 2,025 | sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s | //Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp
// Spec Reference: ldimmhalf lz & hi dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0001 (Z);
R0.H = 0x0000;
R1 = 0x0003 (Z);
R1.H = 0x0002;
R2 = 0x0005 (Z);
R2.H = 0x0004;
R3 = 0x0007 (Z);
R3.H = 0x0006;
... |
stsp/binutils-ia16 | 2,290 | sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s | //Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp
// Spec Reference: ccmv !cc dreg = dreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x808d2301;
imm32 r1, 0x90021053;
imm32 r2, 0x21041405;
imm32 r3, 0x60261507;
imm32 r4, 0x50447609;
imm32 r5, 0xdfe5500b;
imm32 r6, 0x2a0... |
stsp/binutils-ia16 | 1,478 | sim/testsuite/bfin/c_pushpopmultiple_preg.s | //Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp
// Spec Reference: pushpopmultiple preg
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
P1 = 0xa1 (X);
P2 = 0xa2 (X);
P3 = 0xa3 (X);
P4 = 0xa4 (X);
P5 = 0xa5 (X);
[ -- SP ] = ( P5:1 );
P1 =... |
stsp/binutils-ia16 | 4,247 | sim/testsuite/bfin/c_multi_issue_dsp_ldst_1.s | //Original:/testcases/core/c_multi_issue_dsp_ldst_1/c_multi_issue_dsp_ldst_1.dsp
// Spec Reference: dsp32mac and 2 load/store
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0;
loadsym I1, DATA1;
loadsym P1, DATA0;
loadsym P2, ... |
stsp/binutils-ia16 | 4,130 | sim/testsuite/bfin/c_alu2op_conv_b.s | //Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp
// Spec Reference: alu2op convert b
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abc... |
stsp/binutils-ia16 | 2,901 | sim/testsuite/bfin/c_dsp32mac_dr_a0_is.s | //Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp
// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm3... |
stsp/binutils-ia16 | 4,815 | sim/testsuite/bfin/c_dsp32mac_dr_a1_m.s | //Original:/testcases/core/c_dsp32mac_dr_a1_m/c_dsp32mac_dr_a1_m.dsp
// Spec Reference: dsp32mac dr a1 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0... |
stsp/binutils-ia16 | 3,115 | sim/testsuite/bfin/s9.s | // Test rl3 = ashift (rh0 by 7);
// Test rl3 = lshift (rh0 by 7);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
R0 = 0;
ASTAT = R0;
R0.L = 0x1;
R0.H = 0x1;
R7.L = R0.L << 4;
DBGA ( R7.L , 0x0010 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.... |
stsp/binutils-ia16 | 5,914 | sim/testsuite/bfin/c_dsp32alu_rl_p.s | //Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x19678911;
imm32 r1, 0x2799ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x8... |
stsp/binutils-ia16 | 3,795 | sim/testsuite/bfin/c_ccflag_dr_imm3.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp
// Spec Reference: ccflag dr-imm3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00000002;
imm32 r2, 0x00000003;
imm32 r3, 0x00000004;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32... |
stsp/binutils-ia16 | 1,669 | sim/testsuite/bfin/c_dsp32alu_search.s | //Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp
// Spec Reference: dsp32alu search
# mach: bfin
.include "testutils.inc"
start
imm32 p0, 0x11234556;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444... |
stsp/binutils-ia16 | 3,100 | sim/testsuite/bfin/a5.s | // ALU test program.
// Test instructions
// rL4= L+L (r2,r3);
// rH4= L+H (r2,r3) S;
// rL4= L-L (r2,r3);
// rH4= L-H (r2,r3) S;
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// overflow positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R7 = 0;
ASTAT =... |
stsp/binutils-ia16 | 1,355 | sim/testsuite/bfin/random_0021.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5c604280 | _VS | _AV1S | _AV0S);
imm32 R3, 0xfe0103fe;
imm32 R5, 0x1e53cdd8;
R3.H = R5.L * R3.H (M, IU);
checkreg R3, 0x800003fe;
checkreg ASTAT, (0x5c604280 | _VS | _V | _AV1S | _AV0S | _V_COPY);
dmm32 ASTAT, (0x74a04c00 | _VS | _... |
stsp/binutils-ia16 | 11,635 | sim/testsuite/bfin/se_popkill.S | //Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp
// Description: Kill pops to sysregs in WB
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files... |
stsp/binutils-ia16 | 9,384 | sim/testsuite/bfin/se_rts_rti.S | //Original:/proj/frio/dv/testcases/seq/se_rts_rti/se_rts_rti.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////... |
stsp/binutils-ia16 | 7,522 | sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc... |
stsp/binutils-ia16 | 10,005 | sim/testsuite/bfin/c_ldstii_st_preg.s | //Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp
// Spec Reference: c_ldstii store preg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r... |
stsp/binutils-ia16 | 7,996 | sim/testsuite/bfin/c_comp3op_dr_minus_dr.s | //Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp
// Spec Reference: comp3op dregs - dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
... |
stsp/binutils-ia16 | 6,135 | sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678911;
imm32 r1, 0x9189ab1d;
imm32 r2, 0xa4245515;
imm32 r3, 0xb6637717;
imm32 r4, 0xc678491b;
imm32... |
stsp/binutils-ia16 | 4,760 | sim/testsuite/bfin/c_dsp32shift_fdepx.s | //Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp
// Spec Reference: dsp32shift fdep x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x0... |
stsp/binutils-ia16 | 5,915 | sim/testsuite/bfin/c_ldst_ld_d_p_xh.s | //Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp
// Spec Reference: c_ldst ld d [p] xh
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_... |
stsp/binutils-ia16 | 9,932 | sim/testsuite/bfin/c_dsp32shift_ahalf_rn.s | //Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32... |
stsp/binutils-ia16 | 6,681 | sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s | //Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp
// Spec Reference: dsp32mac dr a1 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0... |
stsp/binutils-ia16 | 1,057 | sim/testsuite/bfin/c_brcc_bp2.s | //Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT =... |
stsp/binutils-ia16 | 6,338 | sim/testsuite/bfin/c_progctrl_clisti_interr.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp
// Spec Reference: CLI STI interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifnd... |
stsp/binutils-ia16 | 5,912 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_h.s | //Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp
// Spec Reference: c_ldst ld d [p++] h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_4;
.endif
loadsym p4, DATA_A... |
stsp/binutils-ia16 | 6,193 | sim/testsuite/bfin/c_ldst_ld_d_p.s | //Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp
// Spec Reference: c_ldst ld d [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ];
R1 = [ P2 ];
R3... |
stsp/binutils-ia16 | 6,642 | sim/testsuite/bfin/c_mmr_loop_user_except.S | //Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp
// Spec Reference: c_mmr_loop_user_except
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACK... |
stsp/binutils-ia16 | 9,484 | sim/testsuite/bfin/c_ldstii_ld_dr_h.s | //Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp
// Spec Reference: c_ldstii load dreg h
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
lo... |
stsp/binutils-ia16 | 1,346 | sim/testsuite/bfin/mc_s2.s | /* SHIFT test program.
* Test r0, r1, A0 <<= BITMUX;
*/
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// load r0=0x90000001
// load r1=0x90000002
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x20000002
// load r5=0x00000000
loadsym P1, data0;
// insert two bits, both equal... |
stsp/binutils-ia16 | 4,524 | sim/testsuite/bfin/c_dsp32mult_pair_i.s | //Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp
// Spec Reference: dsp32mult pair i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2... |
stsp/binutils-ia16 | 4,925 | sim/testsuite/bfin/c_progctrl_excpt.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_excpt/c_progctrl_excpt.dsp
// Spec Reference: progctrl excpt uimm4
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0)... |
stsp/binutils-ia16 | 4,586 | sim/testsuite/bfin/c_dsp32shift_signbits_rl.s | //Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp
// Spec Reference: dsp32shift signbits dregs_lo
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, ... |
stsp/binutils-ia16 | 3,495 | sim/testsuite/bfin/cc-alu.S | # Blackfin testcase for CC/A0/A1 compares
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
/* Clear ASTAT before test */
#define CHECK_ASTAT(op, exp) ASTAT = R2; CC = A0 op A1; check_astat exp
.macro check_astat exp:req
R5 = ASTAT;
R6 = \exp;
CC = R5 == R6;
IF !CC JUMP 1f;
.endm
.macro _acc_te... |
stsp/binutils-ia16 | 14,252 | sim/testsuite/bfin/random_0013.S | # Ensure that dsp insns with IH modifiers saturate first, then round
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24304400 | _VS | _AV1S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x3883de11;
dmm32 A0.x, 0x00000025;
imm32 R2, 0xeb641947;
imm32 R3, 0x66d10863;
imm... |
stsp/binutils-ia16 | 8,487 | sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
stsp/binutils-ia16 | 2,555 | sim/testsuite/bfin/c_brcc_kills_dhits.s | //Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x000000... |
stsp/binutils-ia16 | 2,470 | sim/testsuite/bfin/dsp_a4.s | /* ALU test program.
* Test instructions
* r3= + (r0,r0);
* r3= + (r0,r0) s;
* r3= - (r0,r0);
* r3= - (r0,r0) s;
*/
# mach: bfin
.include "testutils.inc"
start
// overflow positive
R0.L = 0xffff;
R0.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0xffff )... |
stsp/binutils-ia16 | 1,211 | sim/testsuite/bfin/c_dsp32alu_absabs.s | //Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp
// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6,... |
stsp/binutils-ia16 | 2,735 | sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp
// Spec Reference: compi2opp pregs += imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_P_REGS 0;
imm32 sp, 0x00000000;
imm32 fp, 0x00000000;
P1 += -1;
P2 += -2;
P3 += -3;
P4 += -4;
P5 +... |
stsp/binutils-ia16 | 5,188 | sim/testsuite/bfin/c_dsp32mac_a1a0.s | //Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp
// Spec Reference: dsp32mac a1 a0
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x55567... |
stsp/binutils-ia16 | 2,422 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s | //Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x0730... |
stsp/binutils-ia16 | 4,653 | sim/testsuite/bfin/c_logi2op_bittgl.s | //Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp
// Spec Reference: Logi2op functions: bittgl
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r... |
stsp/binutils-ia16 | 3,633 | sim/testsuite/bfin/c_dsp32alu_byteop1ew.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop1ew/c_dsp32alu_byteop1ew.dsp
// Spec Reference: dsp32alu byteop1ew
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, ... |
stsp/binutils-ia16 | 9,103 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0... |
stsp/binutils-ia16 | 1,212 | sim/testsuite/bfin/c_dsp32shiftim_af_s.s | //Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift saturated
imm32 r0, 0x81230001;
imm32 r1, 0x19345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x3ed6789a;
imm32 r4, 0x85d789ab;
imm32 r5, 0x967f9abc;
imm32 r6,... |
stsp/binutils-ia16 | 6,686 | sim/testsuite/bfin/c_dsp32alu_rrpmmp.s | //Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x67889b1d;
... |
stsp/binutils-ia16 | 4,740 | sim/testsuite/bfin/s21.s | // Test A0 = ROT (A0 by imm6);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
// rot
// left by 1
// 00 8000 0001 -> 01 0000 0002 cc=0
R0.L = 0x0001;
R0.H = 0x8000;
R7 = 0;
CC = R7;
A1 = A0 = 0;
A0.w = R0;
A0 = ROT A0 BY 1;
R1 = A0.w;
DBGA ( R1.L , 0x0002 );
D... |
stsp/binutils-ia16 | 4,049 | sim/testsuite/bfin/random_0034.S | # Verify sign extension behavior with simultaneous acc additions, and
# verify that no ASTAT bits get changed as a result
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
dmm32 A0.w, 0x589145b7;
dmm32 A0.x, 0xffffffee;
dmm32 A1.w, 0x0b247b05;
dm... |
stsp/binutils-ia16 | 9,304 | sim/testsuite/bfin/c_dsp32shift_lf.s | //Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : mix data, count (+)= (half reg)
// d_reg = lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01210001;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x345178... |
stsp/binutils-ia16 | 1,827 | sim/testsuite/bfin/dsp_d1.s | /* DAG test program.
* Test circular buffers
*/
# mach: bfin
.include "testutils.inc"
start
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x10 (X);
M1 = 8 (X);
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 )... |
stsp/binutils-ia16 | 1,470 | sim/testsuite/bfin/m9.s | // Test extraction from accumulators:
// ROUND/TRUNCATE in SIGNED FRACTIONAL mode
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffef000
// load r1=0x7ffff000
// load r2=0x00008000
// load r3=0x00018000
// load r4=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 =... |
stsp/binutils-ia16 | 4,305 | sim/testsuite/bfin/c_cc2stat_cc_ac.S | //Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp
// Spec Reference: cc2stat cc ac
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, _UNSET;
imm32 r1, _UNSET;
imm32 r2, _UNSET;
imm32 r3, _UNSET;
imm32 r4, _UNSET;
imm32 r5, _UNSET;
imm32 r6, _UNSET;
imm32 r7, _UNSET;
// tes... |
stsp/binutils-ia16 | 1,303 | sim/testsuite/bfin/c_dsp32shiftim_rot.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp
// Spec Reference: dsp32shiftimm rot:
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x9... |
stsp/binutils-ia16 | 1,458 | sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s | //Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp
// Spec Reference: dsp32alu r(lh) = ( a0 += a1)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x0125ab2d;
imm32 r2, 0x04445535;
imm32 r3, 0x00567747;
imm32 r4, 0x0566895b;
imm32 r5, 0x07897b6d;
imm32 r6, 0x044... |
stsp/binutils-ia16 | 1,530 | sim/testsuite/bfin/c_ldimmhalf_drlo.s | //Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
// Spec Reference: ldimmhalf dreg lo
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xFFFF... |
stsp/binutils-ia16 | 5,771 | sim/testsuite/bfin/se_excpt_dagprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp
// Description: EXCPT instruction combined with DAG Misaligned Access
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(m... |
stsp/binutils-ia16 | 2,869 | sim/testsuite/bfin/m5.s | // Test result extraction of mac instructions.
// Test basic edge values
// SIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym... |
stsp/binutils-ia16 | 10,670 | sim/testsuite/bfin/se_brtarget_stall.S | //Original:/proj/frio/dv/testcases/seq/se_brtarget_stall/se_brtarget_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////... |
stsp/binutils-ia16 | 2,424 | sim/testsuite/bfin/cc-astat-bits.s | # Blackfin testcase for setting all ASTAT bits via CC
# mach: bfin
# We encode the opcodes directly since we test reserved bits
# which lack an insn in the ISA for it. It's a 16bit insn;
# the low 8 bits are always 0x03 while the encoding for the
# high 8 bits are:
# bit 7 - direction
# 0: CC=...;
# ... |
stsp/binutils-ia16 | 1,910 | sim/testsuite/bfin/hwloop-branch-in.s | # Blackfin testcase for branching into the middle of a hardware loop
# mach: bfin
.include "testutils.inc"
.macro test_prep lc:req
loadsym P5, 1f;
dmm32 LC0, \lc
R5 = 0;
R6 = 0;
R7 = 0;
.endm
.macro test_check exp5:req, exp6:req, exp7:req, expLC:req
1:
imm32 R4, \exp5;
CC = R4 == R5;
IF !CC JUMP 2f;
imm... |
stsp/binutils-ia16 | 10,244 | sim/testsuite/bfin/se_mv2lp.S | //Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////////... |
stsp/binutils-ia16 | 1,990 | sim/testsuite/bfin/l0.s | // simple test to ensure that we can load data from memory.
# mach: bfin
.include "testutils.inc"
start
loadsym P0, tab;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
R6 = [ P0 ++ ];
R7 = [ P0 ++ ];
DBGA ( R0.H , 0x1111 );
DBGA ( R1.H , 0x2222 );
DBGA ( ... |
stsp/binutils-ia16 | 8,575 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x1000c000;
imm32... |
stsp/binutils-ia16 | 3,885 | sim/testsuite/bfin/c_alu2op_conv_toggle.s | //Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp
// Spec Reference: alu2op (~) toggle
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r... |
stsp/binutils-ia16 | 5,171 | sim/testsuite/bfin/se_more_ret_haz.S | //Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp
// Description: Return insts following pop, move.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include... |
stsp/binutils-ia16 | 4,138 | sim/testsuite/bfin/c_alu2op_arith_r_sft.s | //Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp
// Spec Reference: alu2op arith right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 ... |
stsp/binutils-ia16 | 2,919 | sim/testsuite/bfin/random_0023.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0xf41fbf3f;
dmm32 A1.x, 0x00000000;
imm32 R5, 0xd8d95310;
imm32 R6, 0xd0457fff;
R5.H = (A1 -= R6.L * R6.H) (M, FU);
checkreg R5, 0x7fff5310;
checkreg A1.... |
stsp/binutils-ia16 | 3,885 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_m/c_dsp32mac_dr_a1a0_m.dsp
// Spec Reference: dsp32mac dr_a1a0 m
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
i... |
stsp/binutils-ia16 | 103,044 | sim/testsuite/bfin/se_undefinedinstruction3.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp
// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
# xfail: "missing checks in A0/A1 macfunc" *-*
#include "test.h"
.include "testutils.inc"
start
//
// ... |
stsp/binutils-ia16 | 2,356 | sim/testsuite/bfin/c_regmv_pr_dr.s | //Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp
// Spec Reference: regmv preg to dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e00... |
stsp/binutils-ia16 | 1,711 | sim/testsuite/bfin/c_loopsetup_preg_div2_lc1.s | //Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp
// Spec Reference: loopsetup preg lc1 / 2
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40... |
stsp/binutils-ia16 | 1,464 | sim/testsuite/bfin/c_ldimmhalf_lz_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp
// Spec Reference: ldimmhalf lz preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Preg
P1 = 0x0003 (Z);
P2 = 0x0005 (Z);
P3 = 0x0007 (Z);
P4 = 0x0009 (Z);
P5 = 0x000b (Z);
FP = 0x000d (Z);
SP = 0x000f (Z);... |
stsp/binutils-ia16 | 1,517 | sim/testsuite/bfin/stk4.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 = ... |
stsp/binutils-ia16 | 2,796 | sim/testsuite/bfin/push-pop-multiple.s | # Blackfin testcase for push/pop multiples instructions
# mach: bfin
.include "testutils.inc"
# Tests follow the pattern:
# - do the push multiple
# - write a garbage value to all registers pushed
# - do the pop multiple
# - check all registers popped against known values
start
# Repeat the same operati... |
stsp/binutils-ia16 | 5,833 | sim/testsuite/bfin/random_0029.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0xdf7ce5c7;
dmm32 A1.x, 0xffffff9c;
imm32 R0, 0x098ecb70;
imm32 R1, 0x80000000;
R1.H = (A1 += R0.L * R1.H) (M, ISS2);
checkreg R1, 0x80000000;... |
stsp/binutils-ia16 | 6,542 | sim/testsuite/bfin/c_except_user_mode.S | //Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp
// Spec Reference: except_mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0)... |
stsp/binutils-ia16 | 4,358 | sim/testsuite/bfin/c_dsp32mult_pair.s | //Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp
// Spec Reference: dsp32mult pair
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029... |
stsp/binutils-ia16 | 7,512 | sim/testsuite/bfin/c_seq_ex2_mmr_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmr_mvpop/c_seq_ex2_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_R... |
stsp/binutils-ia16 | 1,672 | sim/testsuite/bfin/random_0007.S | # Make sure the acc regs are updated even when the search criteria is not met
# (this implicitly affects the top 8 bits)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x08e00690 | _VS | _AC1 | _AN);
dmm32 A0.w, 0x42357aea;
dmm32 A0.x, 0x00000001;
dmm32 A1.w, 0x3a3f0000;
dmm32 A1.x,... |
stsp/binutils-ia16 | 10,540 | sim/testsuite/bfin/se_oneins_zoff.S | //Original:/proj/frio/dv/testcases/seq/se_oneins_zoff/se_oneins_zoff.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////////... |
stsp/binutils-ia16 | 2,862 | sim/testsuite/bfin/byteop1p.s | # Blackfin testcase for BYTEOP1P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP1P (R1:0, R3:2);
check_it \res
R6 =... |
stsp/binutils-ia16 | 3,313 | sim/testsuite/bfin/a2.s | # mach: bfin
.include "testutils.inc"
start
loadsym P0, middle;
R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 );
R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 );
R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 );
R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 );
R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 );
R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 );
R0 = [ P0 + 24 ]; D... |
stsp/binutils-ia16 | 7,286 | sim/testsuite/bfin/c_dsp32alu_rrppmm_sft.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717... |
stsp/binutils-ia16 | 6,835 | sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp
// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
I... |
stsp/binutils-ia16 | 6,034 | sim/testsuite/bfin/c_dsp32alu_maxmax.s | //Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp
// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xe6657717;
imm32 r4, 0x5a67891b;
imm32 r5, 0x67b9ab1d;
imm32 r6,... |
stsp/binutils-ia16 | 4,029 | sim/testsuite/bfin/c_dsp32mult_pair_m_s.s | //Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp
// Spec Reference: dsp32mult pair MUNOP s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm3... |
stsp/binutils-ia16 | 5,752 | sim/testsuite/bfin/m2.s | // MAC test program.
// Test basic edge values
// SIGNED FRACTIONAL mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ]... |
stsp/binutils-ia16 | 2,790 | sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s | //Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp
// Spec Reference: compi2opd dregs += imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += -1;
R2 += -2;
R3 += -3;
R4 += -4;
R5 += -5;
R6 += -6;
R7 += -7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFF... |
stsp/binutils-ia16 | 23,178 | sim/testsuite/bfin/random_0025.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x10cfffff;
imm32 R6, 0x06a1ea20;
R0.H = R6.H >>> 0x1b;
checkreg R0, 0xd420ffff;
checkreg ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);... |
stsp/binutils-ia16 | 1,335 | sim/testsuite/bfin/add_sub_acc.s | // ACP 5.9 A0 -= A1 doesn't set flags
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x0);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x1 (z);
astat=r0;
... |
stsp/binutils-ia16 | 7,994 | sim/testsuite/bfin/c_comp3op_dr_plus_dr.s | //Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp
// Spec Reference: comp3op dregs + dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
im... |
stsp/binutils-ia16 | 11,066 | sim/testsuite/bfin/c_ldstidxl_st_dr_b.s | //Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f5080;
imm32 r1, 0x204e6091;
imm3... |
stsp/binutils-ia16 | 1,056 | sim/testsuite/bfin/c_dsp32alu_sgn.s | //Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L;
R5.H = R5.L = SIGN(... |
stsp/binutils-ia16 | 3,385 | sim/testsuite/bfin/c_dsp32shiftim_amix.s | //Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: mix
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Ashift : positive data, count (+)=left (half reg)
imm32 r0, 0... |
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