repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 7,100 | sim/testsuite/bfin/random_0028.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x44004010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0x851fa4fc;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R2, 0x80000000;
imm32 R5, 0x139d77b4;
R5.H = (A1 += R2.L * R0.L) (M, S2RND);
checkre... |
stsp/binutils-ia16 | 5,343 | sim/testsuite/bfin/c_ldst_st_p_d.s | //Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp
// Spec Reference: c_ldst st_p_d
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7... |
stsp/binutils-ia16 | 1,066 | sim/testsuite/bfin/c_brcc_brf_bp.s | //Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp
// Spec Reference: brcc brf bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
beg... |
stsp/binutils-ia16 | 6,094 | sim/testsuite/bfin/c_dsp32mult_dr_i.s | //Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp
// Spec Reference: dsp32mult single dr i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
stsp/binutils-ia16 | 9,517 | sim/testsuite/bfin/c_dsp32shift_pack.s | //Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp
// Spec Reference: dsp32shift pack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01230000;
imm32 r1, 0x02345678;
imm32 r2, 0x03456789;
imm32 r3, 0x0456789a;
imm32 r4, 0x056789ab;
imm32 r5, 0x06789abc;
imm32 r6, 0x0789abcd;
imm32 r7, 0x089... |
stsp/binutils-ia16 | 2,085 | sim/testsuite/bfin/s5.s | // Test r4 = ROT (r2 by r3);
# mach: bfin
.include "testutils.inc"
start
R0.L = 0x0001;
R0.H = 0x8000;
// rot
// left by 1
// 8000 0001 -> 0000 0002 cc=1
R7 = 0;
CC = R7;
R1 = 1;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right... |
stsp/binutils-ia16 | 1,219 | sim/testsuite/bfin/s10.s | // Shifter test program.
// Test instructions
// RL0 = SIGNBITS R1;
// RL0 = SIGNBITS RL1;
// RL0 = SIGNBITS RH1;
# mach: bfin
.include "testutils.inc"
start
// on 32-b word
R1.L = 0xffff;
R1.H = 0x7fff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0000 );
R1.L = 0xffff;
R1.H = 0x30ff;
R0.L = SIGNBITS R1;
DB... |
stsp/binutils-ia16 | 8,862 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32... |
stsp/binutils-ia16 | 2,761 | sim/testsuite/bfin/c_dsp32mac_dr_a0_iu.s | //Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp
// Spec Reference: dsp32mac dr a0 iu (unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x83545abd;
imm32 r1, 0x78bcfec7;
imm32 r2, 0xc7948679;
imm32 r3,... |
stsp/binutils-ia16 | 2,682 | sim/testsuite/bfin/c_dsp32shift_vmaxvmax.s | //Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp
// Spec Reference: dsp32shift vmax / vmax
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x11002001;
imm32 r1, 0x12001001;
imm32 r2, 0x11301302;
imm32 r3, 0x43001003;
imm32 r4, 0x11601604;
imm32 r5, 0x71001705;
imm32 r6, 0x81008006;
... |
stsp/binutils-ia16 | 1,384 | sim/testsuite/bfin/issue139.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
ASTAT = R0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x66;
R1.H = 0x77;
R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR);
_DBG R7;
CHECKREG R7, 0x0066004c;
CHECKREG R6, 0x00190011;
R7 = ... |
stsp/binutils-ia16 | 4,138 | sim/testsuite/bfin/c_dsp32mac_dr_a1_u.s | //Original:/testcases/core/c_dsp32mac_dr_a1_u/c_dsp32mac_dr_a1_u.dsp
// Spec Reference: dsp32mac dr_a1 u (unsigned fraction & unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbabcfec7;
imm32 r2, 0xc... |
stsp/binutils-ia16 | 7,129 | sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s | //Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp
// Spec Reference: c_ldstpmod store dreg hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;... |
stsp/binutils-ia16 | 5,914 | sim/testsuite/bfin/c_dsp32alu_rh_m.s | //Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x89678911;
imm32 r1, 0x2189ab1d;
imm32 r2, 0x34145515;
imm32 r3, 0x46617717;
imm32 r4, 0x5678191b;
imm32 r5, 0x6789a11d;
imm32 r6, 0x74445515;
imm32 r7, 0x8... |
stsp/binutils-ia16 | 9,487 | sim/testsuite/bfin/se_loop_ppm_int.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////... |
stsp/binutils-ia16 | 7,454 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp
// Spec Reference: dsp32mac pair a1a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645... |
stsp/binutils-ia16 | 7,512 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp
// Spec Reference: dsp32mac pair a1a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8... |
stsp/binutils-ia16 | 5,800 | sim/testsuite/bfin/c_dsp32mult_dr.s | //Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp
// Spec Reference: dsp32mult single dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd246702... |
stsp/binutils-ia16 | 3,646 | sim/testsuite/bfin/c_dsp32shift_amix.s | //Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp
// Spec Reference: dsp32shift ashift mix
# mach: bfin
.include "testutils.inc"
start
// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1)
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Ashift : posi... |
stsp/binutils-ia16 | 2,474 | sim/testsuite/bfin/c_logi2op_bitset.s | //Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp
// Spec Reference: Logi2op
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
//... |
stsp/binutils-ia16 | 2,559 | sim/testsuite/bfin/random_0010.S | # Test logical left shift (vector) insns with larger shift values
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN);
imm32 R5, 0xb0b40000;
imm32 R6, 0xf43a5d3c;
R6 = R5 << 0x19 (V, S);
checkreg R6, 0xff610000;
checkreg ASTAT, (0x30400e90 | ... |
stsp/binutils-ia16 | 6,516 | sim/testsuite/bfin/c_seq_ac_raise_mv.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp
// Spec Reference: sequencer stage AC (raise + regmv)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0... |
stsp/binutils-ia16 | 1,045 | sim/testsuite/bfin/stk.s | # mach: bfin
.include "testutils.inc"
start
// load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
R0 = 1;
R1 = 2;
R2 = 3;
R3 ... |
stsp/binutils-ia16 | 2,063 | sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp
// Spec Reference: compi2opp pregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 fp, 0x00000000;
P1 += 1;
P2 += 2;
P3 += 3;
P4 += 4;
P5 += 5;
FP += 7;
CHECKREG p1, 0x00000001;
... |
stsp/binutils-ia16 | 5,034 | sim/testsuite/bfin/c_ldst_st_p_d_h.s | //Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp
// Spec Reference: c_ldst st_p d h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6... |
stsp/binutils-ia16 | 1,856 | sim/testsuite/bfin/byteop2p.s | # Blackfin testcase for BYTEOP2P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req
dmm32 I0, \i0
R6 = BYTEOP2P (R1:0... |
stsp/binutils-ia16 | 11,033 | sim/testsuite/bfin/c_ldstiifp_st_dreg.s | //Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp
// Spec Reference: c_ldstiifp store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
stsp/binutils-ia16 | 4,334 | sim/testsuite/bfin/c_interr_loopsetup_stld.S | //Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp
// Spec Reference: interrupt loopsetup_ldst
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
A0 = 0; // reset accumulators
A1 = 0;
P1 = 3;
P2 = 4;
LD32(r0, 0x00200005);
LD32(r1, 0x00300010);
LD32... |
stsp/binutils-ia16 | 2,256 | sim/testsuite/bfin/c_ccmv_cc_dr_dr.s | //Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp
// Spec Reference: ccmv cc dreg = dreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa08d2301;
imm32 r1, 0xd0021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x60b61507;
imm32 r4, 0x50487609;
imm32 r5, 0x3005900b;
imm32 r6, 0x2a0c6... |
stsp/binutils-ia16 | 77,422 | sim/testsuite/bfin/divq.s | # Blackfin testcase for divide instructions
# mach: bfin
.include "testutils.inc"
start
/*
* Evaluate given a signed integer dividend and signed interger divisor
* input is:
* r0 = dividend, or numerator
* r1 = divisor, or denominator
* output is:
* r0 = quotient (16-bits)
*/
.macro divide num:... |
stsp/binutils-ia16 | 6,030 | sim/testsuite/bfin/c_dsp32mult_dr_t.s | //Original:/testcases/core/c_dsp32mult_dr_t/c_dsp32mult_dr_t.dsp
// Spec Reference: dsp32mult single dr t
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
stsp/binutils-ia16 | 2,888 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s | //Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, ... |
stsp/binutils-ia16 | 3,312 | sim/testsuite/bfin/random_0009.S | # Verify ASTAT bits are set correctly during dsp mac insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x16ba2677;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x80007fff;
A0 -= R4.H * R4.H (... |
stsp/binutils-ia16 | 1,531 | sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s | //Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp
// Spec Reference: dagmodim L=0, I incremented & decremented (by M)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x10001000;
imm32 i1, 0x02001100;
imm32 i2, 0x00301010;
imm32 i3, 0x00041001;
imm32 m0, 0x00000005;
im... |
stsp/binutils-ia16 | 9,982 | sim/testsuite/bfin/se_loop_nest_ppm_1.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////... |
stsp/binutils-ia16 | 2,414 | sim/testsuite/bfin/c_dsp32alu_alhwx.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp
// Spec Reference: dsp32alu alhwx
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
A1 = A0 = 0;
imm32 r0, 0xa5678911;
imm32 r1, 0xaa89ab1d;
imm32 r2, 0xd4b45515;
imm32 r3, 0xf66e7717;
imm32 r4, 0xe567f91b;
imm32 r5... |
stsp/binutils-ia16 | 1,135 | sim/testsuite/bfin/cec-syscfg-ssstep.S | # Blackfin testcase for hardware single stepping
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set up exception handler
imm32 P4, EVT3;
loadsym R1, _evx;
[P4] = R1;
# Enable single stepping
R0 = 1;
SYSCFG = R0;
# Lower to the code we want to single step th... |
stsp/binutils-ia16 | 5,429 | sim/testsuite/bfin/c_dsp32alu_rpm.s | //Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp
// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x65678911;
imm... |
stsp/binutils-ia16 | 4,737 | sim/testsuite/bfin/c_dspldst_st_dr_ippm.s | //Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp
// Spec Reference: c_dspldst st_dr_ippm
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;... |
stsp/binutils-ia16 | 1,426 | sim/testsuite/bfin/c_br_preg_stall_ac.s | //Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
/* This test likes to assume the current [SP] is valid */
SP += -12;
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x0000... |
stsp/binutils-ia16 | 1,313 | sim/testsuite/bfin/c_dsp32alu_a0a1s.s | //Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp
// Spec Reference: dsp32alu a0a1s
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0xf6667717;
imm32 r4, 0xe567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xb4445515;
imm3... |
stsp/binutils-ia16 | 1,555 | sim/testsuite/bfin/x1.s | # mach: bfin
.include "testutils.inc"
start
// 0.5
imm32 r0, 0x40004000;
imm32 r1, 0x40004000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x40004000;
checkreg r3, 0;
imm32 r1, 0x10001000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x28002800;
checkreg r3, 0x18001800;
R0 = R2 +|+... |
stsp/binutils-ia16 | 5,485 | sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0)... |
stsp/binutils-ia16 | 2,844 | sim/testsuite/bfin/conv_enc_gen.s | # mach: bfin
// GENERIC CONVOLUTIONAL ENCODER
// This a generic rate 1/n convolutional encoder. It computes n output
// bits for each input bit, based on n generic polynomials.
// It uses the set of BXOR_CC instructions to compute bit XOR
// reduction from a state masked by a polynomial. For an alternate
// solution ... |
stsp/binutils-ia16 | 10,384 | sim/testsuite/bfin/c_dsp32shift_ahalf_rp_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
im... |
stsp/binutils-ia16 | 8,465 | sim/testsuite/bfin/c_mmr_loop.S | //Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp
// Spec Reference: mmr loop (interr control) no exception
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#... |
stsp/binutils-ia16 | 1,233 | sim/testsuite/bfin/c_dsp32shiftim_lhh.s | //Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift / lshift
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0... |
stsp/binutils-ia16 | 1,159 | sim/testsuite/bfin/m6.s | // Test result extraction of mac instructions.
// Test basic edge values
// SIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P... |
stsp/binutils-ia16 | 4,973 | sim/testsuite/bfin/dbg_tr_tbuf0.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
// This test embeds .text offsets, s... |
stsp/binutils-ia16 | 11,110 | sim/testsuite/bfin/se_loop_kill_01.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////... |
stsp/binutils-ia16 | 10,753 | sim/testsuite/bfin/lmu_excpt_illaddr.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp
// Description: LMU illegal address exceptions
// Illegal core MMR: addr[19:16] != 0
// Illegal core MMR: Illegal peripheral
// Illegal core MMR: Illegal addr in peripheral
# mach: bfin
# sim: --environment operating
#include "test.h"
.incl... |
stsp/binutils-ia16 | 2,077 | sim/testsuite/bfin/PN_generator.s | # mach: bfin
// GENERIC PN SEQUENCE GENERATOR
// Linear Feedback Shift Register
// -------------------------------
// This solution implements an LFSR by applying an XOR reduction
// function to the 40 bit accumulator, XORing the contents of the
// CC bit, shifting by one the accumulator, and inserting the
// resultin... |
stsp/binutils-ia16 | 5,717 | sim/testsuite/bfin/se_excpt_ifprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp
// Description: EXCPT instruction and IF Prot Viol priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
inc... |
stsp/binutils-ia16 | 4,211 | sim/testsuite/bfin/c_dsp32shiftim_a0alr.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x11140000;
imm32 r1, 0x012C003E;
imm32 r2, 0x81359E24;
imm32 r3, 0x81459E24;
imm32 r4, 0xD159E2... |
stsp/binutils-ia16 | 1,470 | sim/testsuite/bfin/c_ldimmhalf_l_dr.s | //Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp
// Spec Reference: ldimmhalf l dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xffff... |
stsp/binutils-ia16 | 4,386 | sim/testsuite/bfin/a10.s | // ALU test program.
// Test dual 16 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0002;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0002 ... |
stsp/binutils-ia16 | 4,000 | sim/testsuite/bfin/c_dsp32mult_pair_m_is.s | //Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp
// Spec Reference: dsp32mult pair MUNOP is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
i... |
stsp/binutils-ia16 | 7,235 | sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
IN... |
stsp/binutils-ia16 | 9,418 | sim/testsuite/bfin/c_ldstidxl_ld_dreg.s | //Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp
// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
// initial values
loadsym p1, DATA_ADDR_1,... |
stsp/binutils-ia16 | 1,181 | sim/testsuite/bfin/algnbug2.s | # mach: bfin
.include "testutils.inc"
start
M0 = 1 (X);
loadsym I0, blocka;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP |... |
stsp/binutils-ia16 | 9,699 | sim/testsuite/bfin/c_dsp32shift_rot_mix.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp
// Spec Reference: dsp32shift rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x83456789;
imm32 r3, 0x9456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb... |
stsp/binutils-ia16 | 6,161 | sim/testsuite/bfin/c_dsp32mult_dr_tu.s | //Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp
// Spec Reference: dsp32mult single dr tu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, ... |
stsp/binutils-ia16 | 8,752 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY imm5)
// RLx by imm5
imm32 r0, 0x00100a... |
stsp/binutils-ia16 | 1,064 | sim/testsuite/bfin/c_brcc_bp3.s | //Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT... |
stsp/binutils-ia16 | 2,822 | sim/testsuite/bfin/c_dsp32mac_dr_a0_t.s | //Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp
// Spec Reference: dsp32mac dr a0 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0... |
stsp/binutils-ia16 | 94,871 | sim/testsuite/bfin/lmu_cplb_multiple0.S | //Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp
// Description: Multiple CPLB Hit exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
... |
stsp/binutils-ia16 | 4,307 | sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s | //Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp
// Spec Reference: dagmodik l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000100e;
imm32 b1, 0x0000110c;... |
stsp/binutils-ia16 | 3,441 | sim/testsuite/bfin/disalnexcpt_implicit.S | # Blackfin testcase for insns that implicitly have DISALGNEXCPT behavior
# when used in parallel insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
LINK 0x100;
# Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes
init_l_regs 0
init_m_regs 0
R0 = SP;
BITCLR (R0, 0);
BITCLR (R0, 1);
I0 = R... |
stsp/binutils-ia16 | 2,019 | sim/testsuite/bfin/c_ldst_st_p_p.s | //Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp
// Spec Reference: c_ldst st_p_p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7... |
stsp/binutils-ia16 | 3,104 | sim/testsuite/bfin/c_dspldst_st_dr_i.s | //Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp
// Spec Reference: c_dspldst st_dr_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 ... |
stsp/binutils-ia16 | 8,707 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6... |
stsp/binutils-ia16 | 4,000 | sim/testsuite/bfin/c_dsp32alu_mix.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp
// Spec Reference: dsp32alu mix
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit
// and 32-bit data. If an operation use a single ALU only, it ... |
stsp/binutils-ia16 | 1,668 | sim/testsuite/bfin/c_loopsetup_topbotcntr.s | //Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp
// Spec Reference: loopsetup top bot counter
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x08;
loadsym R6, start1;
loadsym R7, end1;
... |
stsp/binutils-ia16 | 4,072 | sim/testsuite/bfin/c_alu2op_log_r_sft.s | //Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp
// Spec Reference: alu2op logical right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0x... |
stsp/binutils-ia16 | 9,855 | sim/testsuite/bfin/lmu_excpt_prot1.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp
// Description: LMU protection exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test ... |
stsp/binutils-ia16 | 6,136 | sim/testsuite/bfin/c_dsp32alu_rh_rnd12_p.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_p/c_dsp32alu_rh_rnd12_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x45678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xf4445515;
imm32 r3, 0x46667717;
imm32 r4, 0xe678891b;
imm3... |
stsp/binutils-ia16 | 1,849 | sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s | //Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp
// Spec Reference: compi2opd dregs = imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
CHECKREG r0, 0;
CHECKREG r1, 1;
CHECKREG r2, 2;
CHECKREG r3, 3;
... |
stsp/binutils-ia16 | 3,831 | sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp
// Spec Reference: ptr2op shadd preg, pregs, 1 (2)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4,... |
stsp/binutils-ia16 | 1,202 | sim/testsuite/bfin/m17.s | // Test various moves to single register
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7fffffff
// load r1=0x00ffffff
// load r2=0xf0000000
// load r3=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
// extract only to high register
R5 = 0;
R4 = 0;
A... |
stsp/binutils-ia16 | 3,363 | sim/testsuite/bfin/c_dsp32shift_lmix.s | //Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp
// Spec Reference: dsp32shift lshift: mix
# mach: bfin
.include "testutils.inc"
start
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// lshift : positive data, count (+)=left (half reg)
imm32 r0, 0x00010001... |
stsp/binutils-ia16 | 3,444 | sim/testsuite/bfin/cec-multi-pending.S | # Blackfin testcase for multiple pending IVGs vs masked state
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
.macro check_cec mmr:req, val... |
stsp/binutils-ia16 | 1,403 | sim/testsuite/bfin/m7.s | // Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf000ffff
// load r3=0x0000007f
// load r4=0x00000080
loads... |
stsp/binutils-ia16 | 9,487 | sim/testsuite/bfin/c_ldstii_ld_dr_xh.s | //Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp
// Spec Reference: c_ldstii load dreg xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
... |
stsp/binutils-ia16 | 2,885 | sim/testsuite/bfin/c_loopsetup_nested_top.s | //Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp
// Spec Reference: loopsetup nested top
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
... |
stsp/binutils-ia16 | 7,994 | sim/testsuite/bfin/c_comp3op_dr_xor_dr.s | //Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp
// Spec Reference: comp3op dregs xor dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
im... |
stsp/binutils-ia16 | 5,431 | sim/testsuite/bfin/c_dsp32alu_rpp.s | //Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp
// Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm... |
stsp/binutils-ia16 | 4,778 | sim/testsuite/bfin/c_dsp32shift_align8.s | //Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp
// Spec Reference: dsp32shift align8
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0... |
stsp/binutils-ia16 | 1,189 | sim/testsuite/bfin/se_ssync.S | //Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp
// Description: Test SSYNC by writing a bunch of MMRs and verifying read
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
i... |
stsp/binutils-ia16 | 6,180 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_xh.s | //Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 ... |
stsp/binutils-ia16 | 6,857 | sim/testsuite/bfin/c_dsp32mac_a1a0_m.s | //Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp
// Spec Reference: dsp32mac a1 a0 m MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1
imm32 r0, 0... |
stsp/binutils-ia16 | 5,477 | sim/testsuite/bfin/c_dsp32mult_dr_mix.s | //Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp
// Spec Reference: dsp32mult single dr (mix) u i t is tu ih
# mach: bfin
.include "testutils.inc"
start
// test the default (signed fraction) rounding U=0 I=0 T=0
imm32 r0, 0xab235615;
imm32 r1, 0xcfba5117;
imm32 r2, 0x13246715;
imm32 r3, 0x0006001... |
stsp/binutils-ia16 | 10,799 | sim/testsuite/bfin/se_loop_lr.S | //Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////... |
stsp/binutils-ia16 | 21,914 | sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s | //Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp
// Spec Reference: dsp32mac a1 a0 iuw32 MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the (signed integer: no ) I=1
imm32 r0, 0x22345628;
imm32 r1, 0x23456729;
im... |
stsp/binutils-ia16 | 5,401 | sim/testsuite/bfin/c_ccflag_dr_dr.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp
// Spec Reference: ccflags dr-dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, ... |
stsp/binutils-ia16 | 2,330 | sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s | //Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
A0 = 0;
A1 = 0;
imm32 r0, 0x00000020; // cc=1
imm32 r1, 0x00000000; // cc=0
imm32 r2, 0x62b61557;
imm32 r3, 0x073... |
stsp/binutils-ia16 | 5,457 | sim/testsuite/bfin/c_ldst_ld_p_p_pp.s | //Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp
// Spec Reference: c_ldst ld p [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ++ ];
P1 +=... |
stsp/binutils-ia16 | 1,750 | sim/testsuite/bfin/a21.s | // Test ALU RND RND12 RND20
# mach: bfin
.include "testutils.inc"
start
// positive saturation
R0 = 0xffffffff;
A0.w = R0;
A1.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// n... |
stsp/binutils-ia16 | 6,888 | sim/testsuite/bfin/random_0019.S | # Test a few (W32) corner cases
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV0S | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x70da33ff;
dmm32 A1.x, 0x0000000f;
imm32 R0, 0x5e29f819;
imm32 R1, 0x3f59520b;
A1 += R0.L * R1.L (M, W32);
checkreg A1.w, 0x... |
stsp/binutils-ia16 | 4,030 | sim/testsuite/bfin/c_regmv_pr_dep_stall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp
// Spec Reference: regmv pr-dependency stall
# mach: bfin
.include "testutils.inc"
start
INIT_M_REGS 0;
// R-reg to P-reg to R reg: stall
imm32 r0, 0x00001110;
imm32 r1, 0x00213330;
imm32 r2, 0x04015550;
imm32 r3, 0x06607770... |
stsp/binutils-ia16 | 6,034 | sim/testsuite/bfin/c_dsp32alu_minmin.s | //Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp
// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x2a445345;
imm32 r3, 0x46657717;
imm32 r4, 0xd567e91b;
imm32 r5, 0x6789af1d;
imm32 r6,... |
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