repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 8,487 | sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
I... |
stsp/binutils-ia16 | 3,816 | sim/testsuite/bfin/c_ldimmhalf_pibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp
// Spec Reference: ldimmhalf p i b m l
# mach: bfin
.include "testutils.inc"
start
// set all reg=-1
//p0 =0x0123;
P1 = 0x1234 (X);
P2 = 0x2345 (X);
P3 = 0x3456 (X);
P4 = 0x4567 (X);
P5 = 0x5678 (X);
FP = 0x6789 (X);
SP = 0x789a... |
stsp/binutils-ia16 | 2,905 | sim/testsuite/bfin/byteop16m.s | # Blackfin testcase for BYTEOP16M
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
#DBG R4
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
#DBG R5
.endm
.macro test_byteop16m i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:re... |
stsp/binutils-ia16 | 2,118 | sim/testsuite/bfin/cir1.s | # Blackfin testcase for circular buffers
# mach: bfin
.include "testutils.inc"
.macro daginit i:req, b:req, l:req, m:req
imm32 I0, \i
imm32 B0, \b
imm32 L0, \l
imm32 M0, \m
.endm
.macro dagcheck newi:req
DBGA ( I0.L, \newi & 0xFFFF );
DBGA ( I0.H, \newi >> 16 );
.endm
.macro dagadd i:req, b:req, l:req, m... |
stsp/binutils-ia16 | 3,226 | sim/testsuite/bfin/c_dsp32mac_pair_a0.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0/c_dsp32mac_pair_a0.dsp
// Spec Reference: dsp32mac pair a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 ... |
stsp/binutils-ia16 | 1,661 | sim/testsuite/bfin/c_loopsetup_preg_lc1.s | //Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp
// Spec Reference: loopsetup preg lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50... |
stsp/binutils-ia16 | 8,468 | sim/testsuite/bfin/random_0024.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ);
imm32 R2, 0x00000000;
imm32 R4, 0x00000000;
imm32 R7, 0x00000000;
R2 = ASHIFT R7 BY R4.L (S);
checkreg ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ);
checkreg R2, 0x00000000;
che... |
stsp/binutils-ia16 | 3,881 | sim/testsuite/bfin/c_alu2op_conv_neg.s | //Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp
// Spec Reference: alu2op (-) negative
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0... |
stsp/binutils-ia16 | 6,193 | sim/testsuite/bfin/c_dsp32mac_pair_a1_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_s/c_dsp32mac_pair_a1_s.dsp
// Spec Reference: dsp32mac pair a1 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
... |
stsp/binutils-ia16 | 9,660 | sim/testsuite/bfin/c_ldstidxl_ld_dr_b.s | //Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp
// Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
// initial values
loadsym p1, DATA_ADDR_... |
stsp/binutils-ia16 | 2,770 | sim/testsuite/bfin/c_dspldst_st_drhi_i.s | //Original:/testcases/core/c_dspldst_st_drhi_i/c_dspldst_st_drhi_i.dsp
// Spec Reference: c_dspldst st_drhi_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
i... |
stsp/binutils-ia16 | 54,870 | sim/testsuite/bfin/se_undefinedinstruction2.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction2/se_undefinedinstruction2.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
... |
stsp/binutils-ia16 | 4,196 | sim/testsuite/bfin/s4.s | // Immediate SHIFT test program.
// Test r4 = ASHIFT (r2 by 10);
// Test r4 = LSHIFT (r2 by 10);
// Test r4 = ROT (r2 by 10);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// load r0=0x80000001
// load r1=0x00000000
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x00000... |
stsp/binutils-ia16 | 4,681 | sim/testsuite/bfin/c_regmv_pr_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp
// Spec Reference: regmv pr-dep no stall
# mach: bfin
.include "testutils.inc"
start
//imm32 p0, 0x00001111;
imm32 p1, 0x32213330;
imm32 p2, 0x34415550;
imm32 p3, 0x36617770;
imm32 p4, 0x38819990;
imm32 p5, 0x3aa1bbb0;
im... |
stsp/binutils-ia16 | 3,933 | sim/testsuite/bfin/c_dsp32mult_pair_m_i.s | //Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp
// Spec Reference: dsp32mult pair MUNOP i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm3... |
stsp/binutils-ia16 | 5,030 | sim/testsuite/bfin/s13.s | // Test rl3 = ashift (rh0 by r5;
// Test rl3 = lshift (rh0 by r5);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
R0 = 0;
ASTAT = R0;
R0.L = 0x1;
R0.H = 0x1;
R5.L = 4;
R7.L = ASHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0010 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = A... |
stsp/binutils-ia16 | 1,469 | sim/testsuite/bfin/c_ldimmhalf_l_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp
// Spec Reference: ldimmhalf l preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
INIT_P_REGS -1;
imm32 sp, 0xffffffff;
imm32 fp, 0xffffffff;
// test Preg
P1.L = 0x0003;
P2.L = 0x0005;
P3.L = 0x0007;
P4.L = 0x0009;
... |
stsp/binutils-ia16 | 3,546 | sim/testsuite/bfin/c_logi2op_alshft_mix.s | //Original:/testcases/core/c_logi2op_alshft_mix/c_logi2op_alshft_mix.dsp
// Spec Reference: Logi2op >>>=, >>=, <<=
# mach: bfin
.include "testutils.inc"
start
// Arithmetic >>>= : positive data
imm32 r0, 0x40000000;
imm32 r1, 0x01111111;
imm32 r2, 0x22222222;
imm32 r3, 0x33333333;
imm32 r4, 0x44444444;
imm32 r5, 0x5... |
stsp/binutils-ia16 | 2,210 | sim/testsuite/bfin/c_ccmv_ncc_pr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_pr_pr/c_ccmv_ncc_pr_pr.dsp
// Spec Reference: ccmv !cc preg = preg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 p1, 0xd0021053;
imm32 p2, 0x2f041405;
imm32 p3, 0x60b61507;
imm32 p4, 0x50487609;
imm32 p5, 0x3005900b;
imm32 sp, 0x2a0c... |
stsp/binutils-ia16 | 11,001 | sim/testsuite/bfin/c_ldstidxl_st_dr_h.s | //Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
stsp/binutils-ia16 | 4,425 | sim/testsuite/bfin/c_alu2op_divq.s | //Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp
// Spec Reference: alu2op divide q
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R... |
stsp/binutils-ia16 | 7,342 | sim/testsuite/bfin/c_interr_disable_enable.S | //Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)... |
stsp/binutils-ia16 | 6,307 | sim/testsuite/bfin/c_ldst_ld_d_p_pp.s | //Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp
// Spec Reference: c_ldst ld d [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P5 ++ ];
R1 = ... |
stsp/binutils-ia16 | 1,441 | sim/testsuite/bfin/c_ldimmhalf_h_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_pr/c_ldimmhalf_h_pr.dsp
// Spec Reference: ldimmhalf h preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
INIT_P_REGS -1;
imm32 sp, 0xffffffff;
imm32 fp, 0xffffffff;
// test Preg
P1.H = 0x0002;
P2.H = 0x0004;
P3.H = 0x0006;
P4.H = 0x0008;
... |
stsp/binutils-ia16 | 1,533,086 | sim/testsuite/bfin/se_all64bitg0opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 0)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0xC0000000 to 0xffffffff
* (... |
stsp/binutils-ia16 | 1,536 | sim/testsuite/bfin/c_ldimmhalf_lz_dr.s | //Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp
// Spec Reference: ldimmhalf lz dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0001 (Z);
R1 = 0x0003 (Z);
R2 = 0x0005 (Z);
R3 = 0x0007 (Z);
R4 = 0x0009 (Z);
R5 = 0x000b (Z);
R6 = 0x000d (Z);
R7 = 0x000f (Z);
C... |
stsp/binutils-ia16 | 4,017 | sim/testsuite/bfin/c_cc2stat_cc_az.s | //Original:/testcases/core/c_cc2stat_cc_az/c_cc2stat_cc_az.dsp
// Spec Reference: cc2stat cc az
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;... |
stsp/binutils-ia16 | 7,770 | sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft_x.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x4666... |
stsp/binutils-ia16 | 6,382 | sim/testsuite/bfin/random_0026.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x4c60c810 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x7fffffff;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R5, 0x00007fff;
imm32 R7, 0x00000000;
R7.L = (A0 += R0.L * R5.L) (IH);
checkreg R7, 0x00007fff;
c... |
stsp/binutils-ia16 | 1,598 | sim/testsuite/bfin/c_br_preg_killed_ex1.s | //Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x000... |
stsp/binutils-ia16 | 4,520 | sim/testsuite/bfin/c_comp3op_dr_mix.s | //Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp
// Spec Reference: comp3op dregs mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12... |
stsp/binutils-ia16 | 9,629 | sim/testsuite/bfin/c_ldst_st_p_d_mm_h.s | //Original:testcases/core/c_ldst_st_p_d_mm_h/c_ldst_st_p_d_mm_h.dsp
// Spec Reference: c_ldst st_p-- h half
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 ... |
stsp/binutils-ia16 | 2,782 | sim/testsuite/bfin/random_0014.S | # Test a few corner cases with various shift insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xf53d356e;
dmm32 A0.x, 0xffffffff;
imm32 R5, 0xaa156b54;
A0 = ASHIFT A0 BY R5.L;
checkreg A0.w, 0x56e0000... |
stsp/binutils-ia16 | 3,520 | sim/testsuite/bfin/c_dsp32mac_dr_a1_ih.s | //Original:/testcases/core/c_dsp32mac_dr_a1_ih/c_dsp32mac_dr_a1_ih.dsp
// Spec Reference: dsp32mac dr_a1 ih (int multiplication with word extraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x1dbcfec7;
imm... |
stsp/binutils-ia16 | 6,250 | sim/testsuite/bfin/c_dsp32mac_pair_a0_i.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp
// Spec Reference: dsp32mac pair a0 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
stsp/binutils-ia16 | 3,767 | sim/testsuite/bfin/c_dsp32mult_pair_m.s | //Original:/testcases/core/c_dsp32mult_pair_m/c_dsp32mult_pair_m.dsp
// Spec Reference: dsp32mult pair MUNOP
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, ... |
stsp/binutils-ia16 | 1,310 | sim/testsuite/bfin/c_dsp32shiftim_ahh_s.s | //Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789ab... |
stsp/binutils-ia16 | 1,125 | sim/testsuite/bfin/issue83.s | # mach: bfin
.include "testutils.inc"
start
R0.H = -32768;
R0.L = 0;
R0 >>= 0x1;
_DBG R0;
R7 = ASTAT;
_DBG R7;
//DBGA ( R7.H , 0x0000 );
//DBGA ( R7.L , 0x0000 );
cc = az;
r0 = cc;
dbga( r0.l, 0);
cc = an;
r0 = cc;
dbga( r0.l, 0);
cc = av0;
r0 = cc;
dbga( r0.l, 0);
cc = av0s;
r0 = cc;
dbga( r0.l... |
stsp/binutils-ia16 | 5,467 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_b.s | //Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp
// Spec Reference: c_ldst ld d [p++] b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = B [ P5 ++ ... |
stsp/binutils-ia16 | 6,197 | sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s | //Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp
// Spec Reference: c_dspldst ld_dr_i++/--
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 ... |
stsp/binutils-ia16 | 7,692 | sim/testsuite/bfin/c_dsp32alu_rrppmm_sft_x.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft_x/c_dsp32alu_rrppmm_sft_x.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << X
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46... |
stsp/binutils-ia16 | 3,583 | sim/testsuite/bfin/c_alu2op_conv_mix.s | //Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp
// Spec Reference: alu2op convert mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0x... |
stsp/binutils-ia16 | 11,054 | sim/testsuite/bfin/se_loop_kill.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill/se_loop_kill.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
... |
stsp/binutils-ia16 | 6,583 | sim/testsuite/bfin/c_seq_dec_raise_pushpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_dec_raise_pushpop/c_seq_dec_raise_pushpop.dsp
// Spec Reference: sequencer stage DEC (raise + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_... |
stsp/binutils-ia16 | 4,150 | sim/testsuite/bfin/c_ccflag_pr_pr_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp
// Spec Reference: ccflag pr-pr (uu)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00110022;
imm32 p1, 0x00110022;
imm32 p2, 0x00330044;
imm32 p3, 0x00550066;
imm32 p4, 0x00770088;
imm32 p5, 0x009900aa;
imm32... |
stsp/binutils-ia16 | 6,402 | sim/testsuite/bfin/c_ldst_st_p_p_pp.s | //Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp
// Spec Reference: c_ldst st p++ p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, ... |
stsp/binutils-ia16 | 1,411 | sim/testsuite/bfin/stk2.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 =... |
stsp/binutils-ia16 | 1,081 | sim/testsuite/bfin/c_logi2op_log_r_shft_astat.S | # Test ASTAT bits with logical right shift (>>=)
# mach: bfin
.include "testutils.inc"
#include "test.h"
start
.macro __do val:req, shift:req, exp:req
# First test when ASTAT starts with all bits cleared
imm32 R2, \val;
ASTAT = R0;
R2 >>= \shift;
R3 = ASTAT;
CHECKREG R2, (\val >> \shift);
CHECKREG R3, \exp;
... |
stsp/binutils-ia16 | 2,096 | sim/testsuite/bfin/hwloop-branch-out.s | # Blackfin testcase for branching out of the middle of a hardware loop
# mach: bfin
.include "testutils.inc"
.macro test_prep lc:req, sym:req
imm32 P0, \lc
loadsym P1, \sym
R5 = 0;
R6 = 0;
R7 = 0;
LSETUP (1f, 2f) LC0 = P0;
.endm
.macro test_check exp5:req, exp6:req, exp7:req, expLC
imm32 R4, \exp5;
CC = ... |
stsp/binutils-ia16 | 8,772 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_lp/c_dsp32shiftim_ahalf_lp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x01010100;... |
stsp/binutils-ia16 | 6,139 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_b.s | //Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp
// Spec Reference: c_ldst ld d [p--] b
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2... |
stsp/binutils-ia16 | 2,562 | sim/testsuite/bfin/c_brcc_kills_dmiss.s | //Original:/testcases/core/c_brcc_kills_dmiss/c_brcc_kills_dmiss.dsp
// Spec Reference: brcc kills data cache miss
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x000000... |
stsp/binutils-ia16 | 7,005 | sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh1.s | //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp
// Spec Reference: comp3op pregs + pregs << 1
# mach: bfin
.include "testutils.inc"
start
imm32 p1, 0x89ab1def;
imm32 p2, 0x56781abc;
imm32 p3, 0xdef01234;
imm32 p4, 0x23451899;
imm32 p5, 0x78911345;
imm32 sp, 0x98... |
stsp/binutils-ia16 | 4,167 | sim/testsuite/bfin/c_regmv_dr_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp
// Spec Reference: regmv dr-dep no stall
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00110001;
imm32 r2, 0x00220002;
imm32 r3, 0x00330003;
imm32 r4, 0x00440004;
imm32 r5, 0x00550005;
imm... |
stsp/binutils-ia16 | 11,958 | sim/testsuite/bfin/dbg_brprd_ntkn_src_kill.S | //Original:/proj/frio/dv/testcases/debug/dbg_brprd_ntkn_src_kill/dbg_brprd_ntkn_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a
// branch source instruction that is predicted but not taken getting killed
// at each stage in the pipe. The test consists of 8 instances of an EXCPT
// ... |
stsp/binutils-ia16 | 4,804 | sim/testsuite/bfin/c_ccflag_pr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr/c_ccflag_pr_pr.dsp
// Spec Reference: ccflag pr-pr
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
INIT_R_REGS 0;
//imm32 p0, 0x00110022;
imm32 p1, 0x00110022;
imm32 p2, 0x00330044;
imm32 p3, 0x00550066;
imm32 p4, 0x00770088;
imm32 p5, 0x009900aa;
... |
stsp/binutils-ia16 | 1,898 | sim/testsuite/bfin/c_cactrl_iflush_pr.s | //Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp
// Spec Reference: c_cactrl iflush_pr
# mach: bfin
.include "testutils.inc"
start
// initial values
//p1=0x448;
//imm32 p1, CODE_ADDR_1;
loadsym p1, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1... |
stsp/binutils-ia16 | 8,524 | sim/testsuite/bfin/c_regmv_dr_imlb.s | //Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp
// Spec Reference: regmv dreg-to-imlb
# mach: bfin
.include "testutils.inc"
start
// check DR-reg to imlb-reg move
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r... |
stsp/binutils-ia16 | 19,424 | sim/testsuite/bfin/se_undefinedinstruction1.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction1/se_undefinedinstruction1.dsp
// Description: 16 bit "holes" Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
includ... |
stsp/binutils-ia16 | 9,741 | sim/testsuite/bfin/se_event_quad.S | //Original:/proj/frio/dv/testcases/seq/se_event_quad/se_event_quad.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////////... |
stsp/binutils-ia16 | 10,521 | sim/testsuite/bfin/c_ldstii_st_dr_h.s | //Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp
// Spec Reference: c_ldstii store dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r... |
stsp/binutils-ia16 | 5,448 | sim/testsuite/bfin/c_ldst_st_p_d_b.s | //Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp
// Spec Reference: c_ldst st_p d b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6... |
stsp/binutils-ia16 | 7,277 | sim/testsuite/bfin/c_ldst_ld_d_p_mm.s | //Original:testcases/core/c_ldst_ld_d_p_mm/c_ldst_ld_d_p_mm.dsp
// Spec Reference: c_ldst ld d [p--]
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loa... |
stsp/binutils-ia16 | 2,080 | sim/testsuite/bfin/cec-snen-reti.S | # Blackfin testcase for having RETI LSB set correctly when self nested
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set our handler
imm32 P5, EVT11;
loadsym R1, _ivg11;
[P5] = R1;
loadsym R1, _fail_lvl;
[P5 + 4] = R1; /* IVG12 */
[P5 + 12] = R1; /* IVG14 */
... |
stsp/binutils-ia16 | 8,568 | sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_rtn_lsmmrj_mvp/c_seq_wb_rtn_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( rtn ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
stsp/binutils-ia16 | 6,993 | sim/testsuite/bfin/c_ldst_st_p_p_mm.s | //Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp
// Spec Reference: c_ldst st p-- p
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 ... |
stsp/binutils-ia16 | 9,359 | sim/testsuite/bfin/se_loop_disable.S | //Original:/proj/frio/dv/testcases/seq/se_loop_disable/se_loop_disable.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////... |
stsp/binutils-ia16 | 9,511 | sim/testsuite/bfin/c_dsp32shift_rot.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp
// Spec Reference: dsp32shift rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x01230001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;... |
stsp/binutils-ia16 | 10,643 | sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s | //Original:testcases/core/c_ldstidxl_ld_dr_h/c_ldstidxl_ld_dr_h.dsp
// Spec Reference: c_ldstidxl load dreg H (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 =... |
stsp/binutils-ia16 | 6,056 | sim/testsuite/bfin/se_ssstep_dagprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_ssstep_dagprotviol/se_ssstep_dagprotviol.dsp
// Description: prioritize DAG Protection Violation and Supervisor Single Step
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
includ... |
stsp/binutils-ia16 | 3,408 | sim/testsuite/bfin/s19.s | // REG-BASED dual 16b SHIFT test program.
// Test r4 = ASHIFT/ASHIFT (r2 by rl1);
// Test r4 = ASHIFT/ASHIFT (r2 by rl1) S;
// Test r4 = LSHIFT/LSHIFT (r2 by rl1);
# mach: bfin
.include "testutils.inc"
start
// arithmetic
// left by largest positive magnitude of 15 (0xf)
// 8001 -> 8000
R7 = 0;
ASTAT = R7... |
stsp/binutils-ia16 | 2,286 | sim/testsuite/bfin/c_loopsetup_prelc.s | //Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp
// Spec Reference: loopsetup preload lc0 lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = ... |
stsp/binutils-ia16 | 10,475 | sim/testsuite/bfin/c_ldstiifp_st_preg.s | //Original:testcases/core/c_ldstiifp_st_preg/c_ldstiifp_st_preg.dsp
// Spec Reference: c_ldstiifp store preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
... |
stsp/binutils-ia16 | 2,312 | sim/testsuite/bfin/random_0018.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x40204090 | _AV1S | _AV0S | _AV0 | _AQ | _AN | _AZ);
imm32 R1, 0x33e91405;
imm32 R4, 0x3fa1377c;
R4.H = R1.H >>> 0x1d;
checkreg R4, 0x9f48377c;
checkreg ASTAT, (0x40204090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AN);
dm... |
stsp/binutils-ia16 | 5,236 | sim/testsuite/bfin/c_regmv_imlb_pr.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_pr/c_regmv_imlb_pr.dsp
// Spec Reference: regmv imlb to dr
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
// i to preg
R0 = I0;
P1 = I0;
P2 = I0;... |
stsp/binutils-ia16 | 7,005 | sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s | //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp
// Spec Reference: comp3op pregs + pregs << 2
# mach: bfin
.include "testutils.inc"
start
imm32 p1, 0x89ab1def;
imm32 p2, 0x56781abc;
imm32 p3, 0xdef01234;
imm32 p4, 0x23451899;
imm32 p5, 0x78911345;
imm32 sp, 0x98... |
stsp/binutils-ia16 | 10,881 | sim/testsuite/bfin/se_loop_nest_ppm_2.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_2/se_loop_nest_ppm_2.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////... |
stsp/binutils-ia16 | 17,518 | sim/testsuite/bfin/se_loop_kill_dcr.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////... |
stsp/binutils-ia16 | 12,214 | sim/testsuite/bfin/se_cc2stat_haz.S | //Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp
// Description:
// Verify CC hazards under the following condition:
//
// (1a) cc2stat (that modifies CC) followed by that uses CC
// (1b) same as (1a) but kill cc2stat instruction in WB
//
// (2a) cc2stat (that modifies CC) foll... |
stsp/binutils-ia16 | 10,645 | sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s | //Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp
// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1... |
stsp/binutils-ia16 | 1,288 | sim/testsuite/bfin/random_0008.S | # check ASTAT ac/av flags are handled correctly when doing Acc = -Acc
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5020ca80 | _VS | _AV1S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x549e07b3;
dmm32 A1.x, 0x0000002a;
A1 = -A1;
checkreg A1.w, 0xab61f84d;
checkreg ... |
stsp/binutils-ia16 | 1,693 | sim/testsuite/bfin/c_dagmodim_lnz_imgebl.s | //Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp
// Spec Reference: dagmodim l not zero & i+m >= b+l
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x00001000;
imm32 b1, 0x000010... |
stsp/binutils-ia16 | 10,594 | sim/testsuite/bfin/c_dsp32shift_ahalf_ln_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_ln_s/c_dsp32shift_ahalf_ln_s.dsp
// Spec Reference: <a pointer to reference the section of the spec>
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1,... |
stsp/binutils-ia16 | 1,204 | sim/testsuite/bfin/issue205.s | # mach: bfin
.include "testutils.inc"
start
R0 = 0; R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0;
P0 = 0; P1 = 0; P2 = 0; P4 = 0; P5 = 0;
I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X);
M0 = 0 (X); M1 = 0 (X); M2 = 0 (X); M3 = 0 (X);
L0 = 0 (X); L1 = 0 (X); L2 = 0 (X); L3 = 0 (X);
B0 = 0 (X); B1 = 0... |
stsp/binutils-ia16 | 6,851 | sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp
// Spec Reference: sequencer stage AC (regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_RE... |
stsp/binutils-ia16 | 3,142 | sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_sn.S | //Original:/proj/frio/dv/testcases/core/c_cc_regmvlogi_mvbrsft_sn/c_cc_regmvlogi_mvbrsft_sn.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
INIT_I_REGS 0;
INIT_M_REGS 0;
INIT_L_REGS 0;
INIT_B_REGS 0;
INIT_R_REGS 0;
INI... |
stsp/binutils-ia16 | 14,785 | sim/testsuite/bfin/se_lsetup_kill.S | //Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////////... |
stsp/binutils-ia16 | 4,845 | sim/testsuite/bfin/c_dsp32shift_align16.s | //Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp
// Spec Reference: dsp32shift align16
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7... |
stsp/binutils-ia16 | 4,640 | sim/testsuite/bfin/c_alu2op_shadd_2.s | //Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp
// Spec Reference: alu2op shadd 2
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bc... |
stsp/binutils-ia16 | 3,380 | sim/testsuite/bfin/c_regmv_dr_acc_acc.s | //Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp
// Spec Reference: regmv dreg-acc-acc
# mach: bfin
.include "testutils.inc"
start
// check R-reg to ACC
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x91234567;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm... |
stsp/binutils-ia16 | 2,860 | sim/testsuite/bfin/c_dsp32mac_dr_a0_u.s | //Original:/testcases/core/c_dsp32mac_dr_a0_u/c_dsp32mac_dr_a0_u.dsp
// Spec Reference: dsp32mac dr a0 u (unsigned fraction and unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0x9abcfec7;
imm32 r2, 0x... |
stsp/binutils-ia16 | 10,098 | sim/testsuite/bfin/c_dsp32shift_ahh.s | //Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp
// Spec Reference: dsp32shift ashift/ashift
# mach: bfin
.include "testutils.inc"
start
// ashift/ashift : positive data, count (+)=left (half reg)
// d_reg = ashift/ashift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2... |
stsp/binutils-ia16 | 11,453 | sim/testsuite/bfin/c_ldstpmod_st_dreg.s | //Original:testcases/core/c_ldstpmod_st_dreg/c_ldstpmod_st_dreg.dsp
// Spec Reference: c_ldstpmod store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm3... |
stsp/binutils-ia16 | 1,777 | sim/testsuite/bfin/dsp_a8.s | /* ALU test program.
* Test instructions
* (r7,r6) = +/- (r0,r1);
* (r7,r6) = +/- (r0,r1)s;
*/
# mach: bfin
.include "testutils.inc"
start
// test positive overflow
R0.L = 0xffff;
R0.H = 0x7fff;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R6 = R0 + R1, R7 = R0 - R1 (NS);
DBGA ( R6.L , 0x0000 )... |
stsp/binutils-ia16 | 3,821 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0/c_dsp32mac_pair_a1a0.dsp
// Spec Reference: dsp32mac pair a1a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
stsp/binutils-ia16 | 6,280 | sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp
// Spec Reference: dsp32mac pair a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa864567... |
stsp/binutils-ia16 | 11,276 | sim/testsuite/bfin/c_dsp32shift_bitmux.s | //Original:/testcases/core/c_dsp32shift_bitmux/c_dsp32shift_bitmux.dsp
// Spec Reference: dsp32shift bitmux
# mach: bfin
.include "testutils.inc"
start
A0 = 0;
imm32 r0, 0x01230000;
imm32 r1, 0x12340678;
imm32 r2, 0x23450089;
imm32 r3, 0x3456089a;
imm32 r4, 0x456709ab;
imm32 r5, 0x56780abc;
imm32 r6, 0x678... |
stsp/binutils-ia16 | 14,915 | sim/testsuite/bfin/c_compi2opd_flags_2.S | //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp
// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = R0; // initialize astat
// AZ for R0
imm32 r0, 0x00000000;
R0 += 0; // az... |
stsp/binutils-ia16 | 1,409 | sim/testsuite/bfin/a22.s | // Test ALU NEG accumulators
# mach: bfin
.include "testutils.inc"
start
R0 = 0xffffffff;
A0.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A0 = - A0;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 );
R0 = 0x1;
A0.w = R0;
R0 = 0x0;
A0.... |
stsp/binutils-ia16 | 10,070 | sim/testsuite/bfin/c_dsp32shift_lhalf_ln.s | //Original:/testcases/core/c_dsp32shift_lhalf_ln/c_dsp32shift_lhalf_ln.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;... |
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