repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 4,916 | sim/testsuite/bfin/c_dsp32mult_dr_m_iutsh.s | //Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp
// Spec Reference: dsp32mult single dr munop iu tu is ih
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r... |
stsp/binutils-ia16 | 10,963 | sim/testsuite/bfin/se_loop_ppm_1.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////////... |
stsp/binutils-ia16 | 1,500 | sim/testsuite/bfin/random_0003.S | # Test for ASTAT AN setting when overflows occur
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x18204a80 | _AV1S | _AV0 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x1098e30b;
dmm32 A1.x, 0x0000001f;
imm32 R0, 0x440ed6ae;
imm32 R5, 0x3272c296;
R0.H = (A1 += R0.L * R5.H);
... |
stsp/binutils-ia16 | 7,686 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp
// Spec Reference: dsp32mac pair a1a0 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645... |
stsp/binutils-ia16 | 3,835 | sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s | //Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp
// Spec Reference: pushpopmultiple dreg preg in group pair
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;... |
stsp/binutils-ia16 | 1,967 | sim/testsuite/bfin/c_dsp32alu_byteop2.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop2/c_dsp32alu_byteop2.dsp
// Spec Reference: dsp32alu byteop2
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444... |
stsp/binutils-ia16 | 5,857 | sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s | //Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm3... |
stsp/binutils-ia16 | 1,239 | sim/testsuite/bfin/c_dsp32alu_rlh_rnd.s | //Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cd... |
stsp/binutils-ia16 | 9,410 | sim/testsuite/bfin/lmu_excpt_default.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp
// Description: Default protection checks (CPLB disabled)
// - MMR access in User mode
// - DAG1 Access MMRs (supv/user mode, read/write)
// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write)
# mach: bfin
# sim: --environmen... |
stsp/binutils-ia16 | 5,916 | sim/testsuite/bfin/c_ldst_ld_d_p_h.s | //Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp
// Spec Reference: c_ldst ld d [p] h
# mach: bfin
.include "testutils.inc"
start
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_... |
stsp/binutils-ia16 | 4,503 | sim/testsuite/bfin/c_dsp32mult_dr_m.s | //Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp
// Spec Reference: dsp32mult single dr (mix) MUNOP
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm... |
stsp/binutils-ia16 | 2,252 | sim/testsuite/bfin/c_regmv_acc_acc.s | //Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp
// Spec Reference: regmv acc-acc
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa9627911;
imm32 r1, 0xd0158978;
imm32 r2, 0xc1234567;
imm32 r3, 0x10060007;
imm32 r4, 0x02080009;
imm32 r5, 0x003a000b;
imm32 r6, 0x0004000d;
imm32 r7, 0x000... |
stsp/binutils-ia16 | 5,517 | sim/testsuite/bfin/c_interr_excpt.S | //Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp
// Spec Reference: interr excpt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // ini... |
stsp/binutils-ia16 | 2,911 | sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s | //Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp
// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x83545abd;
imm32 r1, 0x98bcfec7;
imm32 r... |
stsp/binutils-ia16 | 13,554 | sim/testsuite/bfin/c_ldstidxl_st_dreg.s | //Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
stsp/binutils-ia16 | 2,738 | sim/testsuite/bfin/c_dspldst_ld_dr_i.s | //Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: c_dspldst ld_dr_i
// set all regs
INIT_R_REGS 0;
// initial values
loadsym I0, DATA1
loadsym I1, DATA2
loadsym I2, DATA3
loadsym I3, DATA4
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I... |
stsp/binutils-ia16 | 6,219 | sim/testsuite/bfin/se_bug_ui3.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp
// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
inclu... |
stsp/binutils-ia16 | 13,476 | sim/testsuite/bfin/c_regmv_imlb_imlb.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp
// Spec Reference: regmv imlb-imlb
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
imm32 m0, 0x55555555;
imm32 m1, 0x6666... |
stsp/binutils-ia16 | 13,726 | sim/testsuite/bfin/se_loop_mv2lc.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc/se_loop_mv2lc.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////////... |
stsp/binutils-ia16 | 6,235 | sim/testsuite/bfin/se_bug_ui2.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
inclu... |
stsp/binutils-ia16 | 6,169 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_xb.s | //Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp
// Spec Reference: c_ldst ld d [p++] xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = ... |
stsp/binutils-ia16 | 5,922 | sim/testsuite/bfin/c_ldst_ld_d_p_b.s | //Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp
// Spec Reference: c_ldst ld d [p] b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
... |
stsp/binutils-ia16 | 7,285 | sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_call_mv_pop/c_seq_ex1_raise_call_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ call + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
inclu... |
stsp/binutils-ia16 | 5,561 | sim/testsuite/bfin/dbg_tr_simplejp.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp
// Description: This test performs simple jumps and verifies the trace buffer
// recording for simple jumps.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.in... |
stsp/binutils-ia16 | 5,619 | sim/testsuite/bfin/c_dspldst_st_dr_ipp.s | //Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp
// Spec Reference: c_dspldst st_dr_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
//INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x... |
stsp/binutils-ia16 | 4,735 | sim/testsuite/bfin/c_except_sys_sstep.S | //Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp
// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
#ifndef S... |
stsp/binutils-ia16 | 1,071 | sim/testsuite/bfin/c_logi2op_log_l_shft_astat.S | # Test ASTAT bits with logical left shift (<<=)
# mach: bfin
.include "testutils.inc"
#include "test.h"
start
.macro __do val:req, shift:req, exp:req
# First test when ASTAT starts with all bits cleared
imm32 R2, \val;
ASTAT = R0;
R2 <<= \shift;
R3 = ASTAT;
CHECKREG R2, (\val << \shift);
CHECKREG R3, \exp;
#... |
stsp/binutils-ia16 | 5,243 | sim/testsuite/bfin/c_dsp32shift_expexp_r.s | //Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp
// Spec Reference: dsp32shift expadj / expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0800d001;
imm32 r1, 0x08000001;
imm32 r2, 0x0800d002;
imm32 r3, 0x0800d003;
imm32 r4, 0x0800d004;
imm32 r5, 0x0800d005;
imm32 r6, 0x080... |
stsp/binutils-ia16 | 7,367 | sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x4666771... |
stsp/binutils-ia16 | 3,649 | sim/testsuite/bfin/pushpopreg_1.s | # mach: bfin
.include "testutils.inc"
start
r0.l = 0x1111;
r0.h = 0x0011;
r1.l = 0x2222;
r1.h = 0x0022;
r2.l = 0x3333;
r2.h = 0x0033;
r3.l = 0x4444;
r3.h = 0x0044;
r4.l = 0x5555;
r4.h = 0x0055;
r5.l = 0x6666;
r5.h = 0x0066;
r6.l = 0x7777;
r6.h = 0x0077;
r7.l = 0x8888;
r7.h = 0x0088;
p1.l = 0x5a5a;
... |
stsp/binutils-ia16 | 9,178 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00100a00;
imm32 r1, 0x00100a01;
imm32 r2, 0x00100a02;
imm32 r3, 0x00100a03;
imm32 r4, 0x0010... |
stsp/binutils-ia16 | 2,857 | sim/testsuite/bfin/c_dsp32mac_dr_a0.s | //Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp
// Spec Reference: dsp32mac dr_a0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcaba5127;
imm32 r2, 0x13a46705;
imm32 r3, 0x000a0007;
imm32 r4, 0x90abad09;
imm32 r5, 0x10aceadb;
imm32 r6, 0x000c00ad;
imm32 r7, 0x12467... |
stsp/binutils-ia16 | 10,611 | sim/testsuite/bfin/c_dsp32shift_ahh_s.s | //Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp
// Spec Reference: dsp32shift ashift/ashift s
# mach: bfin
.include "testutils.inc"
start
// ashift/ashift s : positive data, count (+)=left (half reg)
// d_reg = ashift/ashift (d BY d_lo) saturation
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0... |
stsp/binutils-ia16 | 1,042 | sim/testsuite/bfin/m8.s | // MAC test program.
// Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000002
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r... |
stsp/binutils-ia16 | 4,507 | sim/testsuite/bfin/c_dsp32shift_af_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// ashift : mix data, count (+)= (half reg)
// d_reg = ashift (d BY d_lo)
// R... |
stsp/binutils-ia16 | 1,468 | sim/testsuite/bfin/dsp_s1.s | /* SHIFT test program.
* Test r0, r1, A0 >>= BITMUX;
*/
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = r0;
// load r0=0x80000009
// load r1=0x10000009
// load r2=0x0000000f
// load r3=0x00000000
// load r4=0x80000008
// load r5=0x00000000
loadsym P0, data0;
loadsym P1, data0;
R0 = [ P0 ... |
stsp/binutils-ia16 | 2,204 | sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s | //Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp
// Spec Reference: compi2opd dregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = -0;
R1 = -1;
R2 = -2;
R3 = -3;
R4 = -4;
R5 = -5;
R6 = -6;
R7 = -7;
CHECKREG r0, -0;
CHECKREG r1, -1;
CHECKREG r2, -2;
CHEC... |
stsp/binutils-ia16 | 2,889 | sim/testsuite/bfin/byteop16p.s | # Blackfin testcase for BYTEOP16P
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0... |
stsp/binutils-ia16 | 1,050 | sim/testsuite/bfin/c_brcc_brf_nbp.s | //Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp
// Spec Reference: brcc brf no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
... |
stsp/binutils-ia16 | 1,203 | sim/testsuite/bfin/byteunpack.s | # Blackfin testcase for playing with BYTEUNPACK
# mach: bfin
.include "testutils.inc"
start
.macro _bu_pre_test i0:req, src0:req, src1:req
dmm32 I0, \i0
imm32 R0, \src0
imm32 R1, \src1
.endm
.macro _bu_chk_test dst0:req, dst1:req
imm32 R2, \dst0
imm32 R3, \dst1
CC = R5 == R2;
IF !CC jump 1f;
CC = R6 == ... |
stsp/binutils-ia16 | 6,136 | sim/testsuite/bfin/c_dsp32alu_rl_rnd12_p.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678011;
imm32 r1, 0x9189a11d;
imm32 r2, 0xa4245235;
imm32 r3, 0xb6637747;
imm32 r4, 0xc67849db;
imm3... |
stsp/binutils-ia16 | 4,328 | sim/testsuite/bfin/c_cc2stat_cc_av0.S | //Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp
// Spec Reference: cc2stat cc av0
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x000... |
stsp/binutils-ia16 | 4,120 | sim/testsuite/bfin/load.s | # Blackfin testcase for register load instructions
# mach: bfin
.include "testutils.inc"
start
.macro load32 num:req, reg0:req, reg1:req
imm32 \reg0 \num
imm32 \reg1 \num
CC = \reg0 == \reg1
if CC jump 2f;
fail
2:
.endm
.macro load32p num:req preg:req
imm32 r0 \num
imm32 \preg \num
r1 = \preg
cc = r0... |
stsp/binutils-ia16 | 7,130 | sim/testsuite/bfin/c_ldstpmod_st_dr_lo.s | //Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp
// Spec Reference: c_ldstpmod store dreg lo
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
... |
stsp/binutils-ia16 | 9,363 | sim/testsuite/bfin/se_kill_wbbr.S | //Original:/proj/frio/dv/testcases/seq/se_kill_wbbr/se_kill_wbbr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
... |
stsp/binutils-ia16 | 9,029 | sim/testsuite/bfin/c_ldstiifp_ld_dreg.s | //Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp
// Spec Reference: c_ldstiifp load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0000;
P2 = 0x0004;
P3 = 0x0... |
stsp/binutils-ia16 | 2,538 | sim/testsuite/bfin/s30.s | // Test signbits40
# mach: bfin
.include "testutils.inc"
start
// positive value in accum, smaller than 1.0
A1 = A0 = 0;
R0.L = 0xffff;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA... |
stsp/binutils-ia16 | 6,911 | sim/testsuite/bfin/random_0022.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2090c600 | _VS | _AC1 | _AQ | _CC | _AN);
dmm32 A0.w, 0xf041e418;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x51296cc2;
imm32 R7, 0xca05cb74;
R4.L = (A0 += R7.H * R4.L) (TFU);
checkreg R4, 0x5129ffff;
checkreg A0.w, 0xffffffff;
checkreg A... |
stsp/binutils-ia16 | 6,225 | sim/testsuite/bfin/c_dsp32mult_dr_is.s | //Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp
// Spec Reference: dsp32mult single dr is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, ... |
stsp/binutils-ia16 | 1,240 | sim/testsuite/bfin/c_dsp32shiftim_ahh.s | //Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift / ashift
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0... |
stsp/binutils-ia16 | 2,946 | sim/testsuite/bfin/c_dspldst_ld_drhi_i.s | //Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp
// Spec Reference: c_dspldst ld_drhi_i
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load upper half of Dr... |
stsp/binutils-ia16 | 3,583 | sim/testsuite/bfin/a0shift.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
// 0xfffffe371c
r0 = 0;
r1 = 0;
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
a1 = a0 =0;
astat = R0;
R6.L = 0x8000;
R5.H = 0x8000;
// load acc with values;
R0.L = 0xc062;
R0.H = 0xffee;
A0.w = R0;
R0.L = 0xc52c;
A0.x = R0;
R0.L = 0x... |
stsp/binutils-ia16 | 1,709 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s | //Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5,... |
stsp/binutils-ia16 | 1,803 | sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s | //Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000020; // cc=1
imm32 r1, 0x00000000; // cc=0
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00... |
stsp/binutils-ia16 | 6,542 | sim/testsuite/bfin/c_interr_timer_tscale.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp
// Spec Reference: interrupt on HW TIMER tscale
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNT... |
stsp/binutils-ia16 | 4,342 | sim/testsuite/bfin/c_dsp32shift_a0alr.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x11140000;
imm32 r1, 0x012C003E;
imm32 r2, 0x81359E24;
imm32 r3, 0x81459E24;
imm32 r4, 0xD159E268;
... |
stsp/binutils-ia16 | 5,914 | sim/testsuite/bfin/c_dsp32alu_rl_m.s | //Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x55678911;
imm32 r1, 0x2759ab1d;
imm32 r2, 0x34455515;
imm32 r3, 0x46665717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789a51d;
imm32 r6, 0x74445515;
imm32 r7, 0x8... |
stsp/binutils-ia16 | 11,801 | sim/testsuite/bfin/se_loop_mv2lt_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lt_stall/se_loop_mv2lt_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
stsp/binutils-ia16 | 6,439 | sim/testsuite/bfin/a11.S | // Test ALU RND RND12 RND20
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R7 = 0;
ASTAT = R7;
// 7ffffff0
// + 00008000
// -> 7fff0000
R0 = 0xfff0 (Z);
R0.H = 0x7fff;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff;
CHECKREG R0, (_VS|_V|_V_COPY);
// 7ffffff0
// + 00008000
// ->... |
stsp/binutils-ia16 | 5,570 | sim/testsuite/bfin/a9.s | // ALU test program.
// Test 32 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R... |
stsp/binutils-ia16 | 5,622 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_xh.s | //Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp
// Spec Reference: c_ldst ld d [p++] xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// initial values
loadsym p5, DATA_ADDR_1, 0x08;
loadsym p1, DATA... |
stsp/binutils-ia16 | 5,702 | sim/testsuite/bfin/c_dsp32alu_max.s | //Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp
// Spec Reference: dsp32alu dregs = max ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x85678911;
imm32 r1, 0x9789ab1d;
imm32 r2, 0xa4445b15;
imm32 r3, 0x46667717;
imm32 r4, 0xd567f91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;... |
stsp/binutils-ia16 | 1,131 | sim/testsuite/bfin/se_all64bitg2opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 2)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach:... |
stsp/binutils-ia16 | 4,844 | sim/testsuite/bfin/c_dsp32mult_dr_m_u.s | //Original:/testcases/core/c_dsp32mult_dr_m_u/c_dsp32mult_dr_m_u.dsp
// Spec Reference: dsp32mult single dr munop u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
stsp/binutils-ia16 | 7,095 | sim/testsuite/bfin/c_dsp32shift_lhh.s | //Original:/testcases/core/c_dsp32shift_lhh/c_dsp32shift_lhh.dsp
// Spec Reference: dsp32shift lshift/lshift
# mach: bfin
.include "testutils.inc"
start
// lshift/lshift : = (half reg)
// d_reg = lshift/lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x34... |
stsp/binutils-ia16 | 1,817 | sim/testsuite/bfin/c_regmv_dr_pr.s | //Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp
// Spec Reference: regmv dreg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to R-reg move
imm32 r0, 0x20001001;
imm32 r1, 0x20021003;
imm32 r2, 0x20041005;
imm32 r3, 0x20061007;
imm32 r4, 0x20081009;
imm32 r5, 0x200a100b;
imm32 r6... |
stsp/binutils-ia16 | 1,744 | sim/testsuite/bfin/double_prec_mult.s | # mach: bfin
.include "testutils.inc"
start
// This function computes an integer 32x32 multiply,
// and returns the upper 32 bits of the result.
// If the complete 64 bit result is required, one must
// write the partial results as they are computed.
// To change this code for a fractional 32x32, one needs
// to adj... |
stsp/binutils-ia16 | 10,134 | sim/testsuite/bfin/random_0036.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x3ce04490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x7d8d8272;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe0004138;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x7d8e7fff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 ... |
stsp/binutils-ia16 | 12,557 | sim/testsuite/bfin/se_illegalcombination.S | //Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp
// Description: Multi-issue Illegal Combinations
# mach: bfin
# sim: --environment operating
# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
#include "test.h"
.include "testutils.inc"
start
//
// Constants a... |
stsp/binutils-ia16 | 8,703 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x... |
stsp/binutils-ia16 | 2,876 | sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s | //Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp
// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm32 r2, 0xc7fff... |
stsp/binutils-ia16 | 3,683 | sim/testsuite/bfin/max_min_flags.s | // Check Flag Settings for MAX/MIN
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
r0=1;
r1= -1;
r2=min(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);... |
stsp/binutils-ia16 | 12,527 | sim/testsuite/bfin/c_ldstidxl_st_preg.s | //Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp
// Spec Reference: c_ldstidxl store preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm3... |
stsp/binutils-ia16 | 11,605 | sim/testsuite/bfin/dbg_jmp_src_kill.S | //Original:/proj/frio/dv/testcases/debug/dbg_jmp_src_kill/dbg_jmp_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a JUMP
// source instruction getting killed at each stage in the pipe. The test
// consists of 8 instances of an EXCPT instruction followed by 0 to 7 NOPs
// and a JUMP, ... |
stsp/binutils-ia16 | 6,433 | sim/testsuite/bfin/c_mode_user_superivsor.S | //Original:/proj/frio/dv/testcases/core/c_mode_user_superivsor/c_mode_user_superivsor.dsp
// Spec Reference: mode_user_supervisor
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
IN... |
stsp/binutils-ia16 | 10,386 | sim/testsuite/bfin/c_dsp32shift_ahalf_rn_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
... |
stsp/binutils-ia16 | 4,303 | sim/testsuite/bfin/c_cc2stat_cc_av1.S | //Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp
// Spec Reference: cc2stat cc av1
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000... |
stsp/binutils-ia16 | 5,483 | sim/testsuite/bfin/c_regmv_pr_imlb.s | //Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp
// Spec Reference: regmv preg-to-imlb reg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to imlb-reg move
imm32 r0, 0x00000001;
imm32 p1, 0x00020003;
imm32 p2, 0x00040005;
imm32 p3, 0x00060007;
imm32 p4, 0x00080009;
imm32 p5, 0x000a000b;
imm... |
stsp/binutils-ia16 | 8,604 | sim/testsuite/bfin/random_0027.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2850c890 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xa605868e;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x56dd0982;
imm32 R4, 0x50e37862;
imm32 R5, 0x597fc81a;
R4.H = (A1 -= R5.L * R1.L) (M, IS);
checkreg R4, 0x7fff7862;... |
stsp/binutils-ia16 | 7,992 | sim/testsuite/bfin/c_comp3op_dr_and_dr.s | //Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp
// Spec Reference: comp3op dregs & dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm3... |
stsp/binutils-ia16 | 8,629 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x0000000... |
stsp/binutils-ia16 | 10,550 | sim/testsuite/bfin/c_ldst_st_p_d_mm.s | //Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp
// Spec Reference: c_ldst st_p++/p--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32... |
stsp/binutils-ia16 | 5,551 | sim/testsuite/bfin/random_0030.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN);
dmm32 A1.w, 0x8f7fea28;
dmm32 A1.x, 0x00000005;
imm32 R2, 0x000014f2;
imm32 R4, 0x7fff7fff;
imm32 R7, 0x14d3a258;
R7.H = (A1 -= R4.L * R2.H) (M, T);
checkreg R7, 0x7fffa258;
checkreg A1.w... |
stsp/binutils-ia16 | 2,624 | sim/testsuite/bfin/c_ldimmhalf_lz_ibml.s | //Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: ldimmhalf lz ibml
I0 = 0x2001 (Z);
I1 = 0x2003 (Z);
I2 = 0x2005 (Z);
I3 = 0x2007 (Z);
L0 = 0x2009 (Z);
L1 = 0x200b (Z);
L2 = 0x200d (Z);
L3 = 0x200f (Z);
R0 = I0;
R1 = I1;
R2 =... |
stsp/binutils-ia16 | 1,217 | sim/testsuite/bfin/c_ccmv_cc_dr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp
// Spec Reference: ccmv cc dpreg = dpreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x138d2301;
imm32 r1, 0x20421053;
imm32 r2, 0x3f051405;
imm32 r3, 0x40b66507;
imm32 r4, 0x50487709;
imm32 r5, 0x60059... |
stsp/binutils-ia16 | 1,700 | sim/testsuite/bfin/c_dsp32mac_pair_mix.s | //Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp
// Spec Reference: dsp32mac pair mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00060007;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7,... |
stsp/binutils-ia16 | 1,158 | sim/testsuite/bfin/c_dsp32shiftim_lf.s | //Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
i... |
stsp/binutils-ia16 | 1,791 | sim/testsuite/bfin/c_progctrl_except_rtx.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp
// Spec Reference: c_progctrl_except_rtx
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe0000... |
stsp/binutils-ia16 | 5,300 | sim/testsuite/bfin/c_ldst_ld_p_p.s | //Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp
// Spec Reference: c_ldst ld p [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ];
P4 = [ P1 ];
P5... |
stsp/binutils-ia16 | 3,526 | sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s | //Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp
// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc12486... |
stsp/binutils-ia16 | 10,413 | sim/testsuite/bfin/se_loop_ppm.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm/se_loop_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
//... |
stsp/binutils-ia16 | 1,691 | sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s | //Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp
// Spec Reference: dagmodim l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000110e;
imm32 b1, 0x0000110c;... |
stsp/binutils-ia16 | 9,187 | sim/testsuite/bfin/c_ldstii_ld_dreg.s | //Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp
// Spec Reference: c_ldstii load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loads... |
stsp/binutils-ia16 | 5,504 | sim/testsuite/bfin/saatest.s | # mach: bfin
.include "testutils.inc"
start
I0 = 0 (X);
I1 = 0 (X);
A0 = A1 = 0;
init_r_regs 0;
ASTAT = R0;
// This section of code will test the SAA instructions and sum of accumulators;
loadsym I0, tstvecI;
R0 = [ I0 ++ ];
R2 = [ I0 ++ ];
// +++++++++++++++ TG11.001 +++++++++++++ //
// ... |
stsp/binutils-ia16 | 8,498 | sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.i... |
stsp/binutils-ia16 | 3,054 | sim/testsuite/bfin/c_pushpopmultiple_dreg.s | //Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp
// Spec Reference: pushpopmultiple dreg
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
[ -- SP ] =... |
stsp/binutils-ia16 | 1,775 | sim/testsuite/bfin/c_regmv_pr_pr.s | //Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp
// Spec Reference: regmv preg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
imm32 p1, 0x20021003;
imm32 p... |
stsp/binutils-ia16 | 4,199 | sim/testsuite/bfin/c_logi2op_log_l_shft.s | //Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp
// Spec Reference: Logi2op <<=
# mach: bfin
.include "testutils.inc"
start
// Logical <<= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81... |
stsp/binutils-ia16 | 1,135 | sim/testsuite/bfin/c_dsp32alu_abs.s | //Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp
// Spec Reference: dsp32alu dregs = abs ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;... |
stsp/binutils-ia16 | 6,260 | sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s | //Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp
// Spec Reference: c_dspldst st_drlo_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
im... |
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