repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 1,605 | sim/testsuite/bfin/addsub_flags.S | // ACP 5.17 Dual ALU ops
// AZ, AN, AC0, AC1, V and VS are affected
// AV0, AV0S, AV1, AV1S are unaffected
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
r0=0;
r0.h=0x7fff;
r2=0;
r2.h=0x7000;
r1=r0+r2,r3=r0-r2;
r7=astat;
_dbg r1;
_dbg r3;
_dbg astat... |
stsp/binutils-ia16 | 2,045 | sim/testsuite/bfin/random_0033.S | # Verify registers saturate and ASTAT bits are updated correctly
# with the RND12 subtract insn
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN);
imm32 R5, 0x0fb35119;
imm32 R6, 0xffffffff;
imm32 R7, 0x80000000;
R6.H = R5 - R7 ... |
stsp/binutils-ia16 | 2,492 | sim/testsuite/bfin/c_logi2op_bitclr.s | //Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp
// Spec Reference: Logi2op functions: bitclr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xffffffff;
imm32 r1, 0xffffffff;
imm32 r2, 0xffffffff;
imm32 r3, 0xffffffff;
imm32 r4, 0xffffffff;
imm32 r5, 0xffffffff;
imm32 r6, 0xffffffff;
imm32 r... |
stsp/binutils-ia16 | 1,166 | sim/testsuite/bfin/c_dsp32shiftim_af.s | //Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
i... |
stsp/binutils-ia16 | 4,974 | sim/testsuite/bfin/c_dsp32shift_expadj_r.s | //Original:/testcases/core/c_dsp32shift_expadj_r/c_dsp32shift_expadj_r.dsp
// Spec Reference: dsp32shift expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x08000800;
imm32 r1, 0x08000801;
imm32 r2, 0x08000802;
imm32 r3, 0x08000803;
imm32 r4, 0x08000804;
imm32 r5, 0x08000805;
imm32 r6, 0x08000806;
imm... |
stsp/binutils-ia16 | 11,826 | sim/testsuite/bfin/se_loop_mv2lc_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc_stall/se_loop_mv2lc_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
stsp/binutils-ia16 | 6,415 | sim/testsuite/bfin/c_interr_pending.S | //Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
... |
stsp/binutils-ia16 | 96,673 | sim/testsuite/bfin/lmu_cplb_multiple1.S | //Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp
// Description: Multiple CPLB Hit exceptions (DAG1)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------... |
stsp/binutils-ia16 | 3,068 | sim/testsuite/bfin/c_dsp32mac_mix.s | //Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp
// Spec Reference: dsp32mac mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
A1 ... |
stsp/binutils-ia16 | 2,772 | sim/testsuite/bfin/c_dspldst_st_drlo_i.s | //Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp
// Spec Reference: c_dspldst st_drlo_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
i... |
stsp/binutils-ia16 | 1,667 | sim/testsuite/bfin/c_br_preg_killed_ac.s | //Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000... |
stsp/binutils-ia16 | 1,128 | sim/testsuite/bfin/lsetup.s | # Blackfin testcase for playing with LSETUP
# mach: bfin
.include "testutils.inc"
start
R0 = 0x123;
P0 = R0;
LSETUP (.L1, .L1) LC0 = P0;
.L1:
R0 += -1;
R1 = 0;
CC = R1 == R0;
IF CC JUMP 1f;
fail
1:
p0=10;
loadsym i0, _buf
imm32 r0, 0x12345678
LSETUP(.L2, .L3) lc0 = p0;
.L2:
[i0++] = r0;
.L3:
[i0++]... |
stsp/binutils-ia16 | 6,546 | sim/testsuite/bfin/c_mode_user.S | //Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp
// Spec Reference: mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize t... |
stsp/binutils-ia16 | 7,791 | sim/testsuite/bfin/c_mmr_interr_ctl.s | # Blackfin testcase for the CEC
# mach: bfin
# sim: --environment operating
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_P_REGS 0;
INIT_I_REGS 0;
INIT_M_REGS 0;
INIT_L_REGS 0;
INIT_B_REGS 0;
CLI R1; // inhibit events during MMR writes
loadsym sp, USTACK; // setup the user stack poin... |
stsp/binutils-ia16 | 3,933 | sim/testsuite/bfin/c_dsp32mult_pair_m_u.s | //Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp
// Spec Reference: dsp32mult pair MUNOP u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm3... |
stsp/binutils-ia16 | 5,875 | sim/testsuite/bfin/c_interr_timer_reload.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp
// Spec Reference: interrupt on HW TIMER auto-reload
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef... |
stsp/binutils-ia16 | 5,036 | sim/testsuite/bfin/c_dsp32mult_dr_m_s.s | //Original:/testcases/core/c_dsp32mult_dr_m_s/c_dsp32mult_dr_m_s.dsp
// Spec Reference: dsp32mult single dr munop s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
stsp/binutils-ia16 | 8,283 | sim/testsuite/bfin/c_interr_timer.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp
// Spec Reference: interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL ... |
stsp/binutils-ia16 | 7,518 | sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
in... |
stsp/binutils-ia16 | 2,387 | sim/testsuite/bfin/m4.s | // MAC test program.
// Test basic edge values
// SIGNED INTEGER mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
... |
stsp/binutils-ia16 | 4,864 | sim/testsuite/bfin/c_interr_timer_tcount.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp
// Spec Reference: interrupt on HW TIMER tcount
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNT... |
stsp/binutils-ia16 | 1,806 | sim/testsuite/bfin/se_all64bitg1opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 1)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach:... |
stsp/binutils-ia16 | 3,322 | sim/testsuite/bfin/s15.s | // reg-based SHIFT test program.
# mach: bfin
.include "testutils.inc"
start
// Test FEXT with no sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0810; // pos=8 len=16
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x34de );
DBGA ( R7.H , 0 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0814; // pos=8 le... |
stsp/binutils-ia16 | 9,721 | sim/testsuite/bfin/c_ldstii_ld_preg.s | //Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp
// Spec Reference: c_ldstii load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loads... |
stsp/binutils-ia16 | 5,857 | sim/testsuite/bfin/c_dsp32alu_rl_rnd20_p.s | //Original:/testcases/core/c_dsp32alu_rl_rnd20_p/c_dsp32alu_rl_rnd20_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x4b677717;
imm32 r4, 0x5678791b;
imm32 r5, 0xc789a71d;
imm32 r6, 0x74445515;
imm3... |
stsp/binutils-ia16 | 5,756 | sim/testsuite/bfin/dbg_tr_basic.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfche... |
stsp/binutils-ia16 | 4,621 | sim/testsuite/bfin/c_dsp32mult_pair_s.s | //Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp
// Spec Reference: dsp32mult pair s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2... |
stsp/binutils-ia16 | 2,922 | sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s | //Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp
// Spec Reference: dsp32mac dr_a0 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0... |
stsp/binutils-ia16 | 1,885 | sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s | //Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp
// Spec Reference: c_cactrl iflush_pr [p++]
# mach: bfin
.include "testutils.inc"
start
loadsym p2, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0... |
stsp/binutils-ia16 | 4,017 | sim/testsuite/bfin/c_cc2stat_cc_an.s | //Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp
// Spec Reference: cc2stat cc an
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;... |
stsp/binutils-ia16 | 6,388 | sim/testsuite/bfin/random_0031.S | # Check that VS in ASTAT is set with add/sub insns (and not just V)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x27f3a149;
imm32 R3, 0x3cae7c58;
imm32 R4, 0x33c97634;
R3.H = R0.L - R4.H (NS);
checkre... |
stsp/binutils-ia16 | 14,115 | sim/testsuite/bfin/random_0020.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xfcdbede4;
dmm32 A1.x, 0xffffffff;
imm32 R5, 0x14c5c1c7;
imm32 R7, 0x006a5040;
R5 = (A1 += R7.L * R7.H) (M, IU);
checkreg R5, 0xfcfd2864;
checkreg A1.w, 0xfcfd2864;... |
stsp/binutils-ia16 | 1,513 | sim/testsuite/bfin/c_dsp32alu_rrpm_aa.s | //Original:/testcases/core/c_dsp32alu_rrpm_aa/c_dsp32alu_rrpm_aa.dsp
// Spec Reference: dsp32alu (dregs, dregs) = +/- (a, a) amod1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab2d;
imm32 r2, 0x34745515;
imm32 r3, 0x46677757;
imm32 r4, 0xb567a96b;
imm32 r5, 0x6789... |
stsp/binutils-ia16 | 4,235 | sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s | //Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp
// Spec Reference: dsp32mac and 2 loads
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0
loadsym I1, DATA1
loadsym P1, DATA0
loadsym P2, DATA1
// t... |
stsp/binutils-ia16 | 3,798 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp
// Spec Reference: dsp32mac pair a1a0 M MNOP
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0... |
stsp/binutils-ia16 | 7,214 | sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
inclu... |
stsp/binutils-ia16 | 1,432 | sim/testsuite/bfin/m14.s | // Test extraction from accumulators:
// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffffff0
// load r1=0xfffffff0
// load r2=0x0fffffff
// load r3=0x00000001
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = ... |
stsp/binutils-ia16 | 6,210 | sim/testsuite/bfin/c_dsp32mac_pair_a0_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_u/c_dsp32mac_pair_a0_u.dsp
// Spec Reference: dsp32mac pair a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
stsp/binutils-ia16 | 2,438 | sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s | //Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp
// Spec Reference: compi2opd dregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += 1;
R2 += 2;
R3 += 3;
R4 += 4;
R5 += 5;
R6 += 6;
R7 += 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHE... |
stsp/binutils-ia16 | 6,606 | sim/testsuite/bfin/c_dsp32alu_rrppmm.s | //Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5597891b;
imm32 r5, 0x6989ab1d;
... |
stsp/binutils-ia16 | 8,188 | sim/testsuite/bfin/c_ldstpmod_ld_lohi.s | //Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp
// Spec Reference: c_ldstpmod load dreg lo & hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0002;
P2 = 0x0002;
... |
stsp/binutils-ia16 | 4,351 | sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s | //Original:/testcases/core/c_multi_issue_dsp_ldst_2/c_multi_issue_dsp_ldst_2.dsp
// Spec Reference: dsp32mac and 2 load/store
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0;
loadsym I1, DATA1;
loadsym P1, DATA0... |
stsp/binutils-ia16 | 4,611 | sim/testsuite/bfin/c_dsp32shift_signbits_rh.s | //Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp
// Spec Reference: dsp32shift signbits dregs_hi
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xd1000000;
imm32 r1, 0xd2000001;
imm32 r2, 0xd3000002;
imm32 r3, 0xd4000003;
imm32 r4, 0xd5000004;
imm32 r5, 0xd6000005;
imm32 r6,... |
stsp/binutils-ia16 | 5,233 | sim/testsuite/bfin/byteop3p.s | # Blackfin testcase for BYTEOP3P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP3P (R1:0, R3:2) (LO);
check_it \re... |
stsp/binutils-ia16 | 4,081 | sim/testsuite/bfin/c_cc2stat_cc_aq.s | //Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp
// Spec Reference: cc2stat cc aq
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;... |
stsp/binutils-ia16 | 3,151 | sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp
// Spec Reference: ptr2op preg -= preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0021003;
imm32 p2, 0x2e041005;
imm32 p3, 0x20d61007;
imm32 p4, 0x200a1009;
imm32 p5, 0x200a300b;
imm32 ... |
stsp/binutils-ia16 | 1,412 | sim/testsuite/bfin/cc5.S | // ALU test program.
// Test instructions reg = (A0+=A1)
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// add accums and transfer result
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R6 =... |
stsp/binutils-ia16 | 10,162 | sim/testsuite/bfin/lmu_excpt_align.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp
// Description: LMU data alignment exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
CHECK_INIT(p5, 0xE0000000);
// test addres... |
stsp/binutils-ia16 | 6,170 | sim/testsuite/bfin/dbg_tr_umode.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfche... |
stsp/binutils-ia16 | 6,164 | sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp
// Spec Reference: dsp32mac pair a1 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa894567... |
stsp/binutils-ia16 | 1,638 | sim/testsuite/bfin/random_0012.S | # test VIT_MAX behavior when high Acc bits are set
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0xd81562e8;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x15c2d815;
imm32 R5, 0xc9bd3a6b;
R4.L = VIT_MAX (R5) (ASR);
checkr... |
stsp/binutils-ia16 | 7,450 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_i.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_i/c_dsp32mac_pair_a1a0_i.dsp
// Spec Reference: dsp32mac pair a1a0 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645... |
stsp/binutils-ia16 | 2,891 | sim/testsuite/bfin/c_loopsetup_nested_bot.s | //Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp
// Spec Reference: loopsetup nested same bottom
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 2;
P2 = 4;
P3 = 6;
P4 = 8;
P5 = 10;
SP = 12;
FP = 14;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x32;
R4 = ... |
stsp/binutils-ia16 | 1,999 | sim/testsuite/bfin/c_regmv_dag_lz_dep.s | //Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp
// Spec Reference: regmv dag lz dep forward
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x11111111;
imm32 r1, 0x22223331;
imm32 r2, 0x44445551;
imm32 r3, 0x66667771;
imm32 r4, 0x88889991;
imm32 r5, 0xaaaabbb1;
imm32 r6, 0... |
stsp/binutils-ia16 | 2,571 | sim/testsuite/bfin/c_dsp32shift_vmax.s | //Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp
// Spec Reference: dsp32shift vmax
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x11001001;
imm32 r1, 0x11001001;
imm32 r2, 0x12345678;
imm32 r3, 0x11001003;
imm32 r4, 0x11001004;
imm32 r5, 0x11001005;
imm32 r6, 0x11001006;
imm32 r7, 0x110... |
stsp/binutils-ia16 | 1,347 | sim/testsuite/bfin/c_dsp32alu_saa.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp
// Spec Reference: dsp32alu saa
# mach: bfin
.include "testutils.inc"
start
A1 = 0;
A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6,... |
stsp/binutils-ia16 | 13,148 | sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s | //Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6... |
stsp/binutils-ia16 | 2,927 | sim/testsuite/bfin/c_dspldst_ld_drlo_i.s | //Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp
// Spec Reference: c_dspldst ld_drlo_i
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.L = W [ I... |
stsp/binutils-ia16 | 9,135 | sim/testsuite/bfin/se_all16bitopcodes.S | /*
* Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace
* we track all instructions which cause some sort of exception when run from
* userspace, this is normally EXCAUSE :
* - 0x21 : illegal instruction
* - 0x22 : illegal instruction combination
* - 0x2e : use of supervisor resource fro... |
stsp/binutils-ia16 | 2,246 | sim/testsuite/bfin/cec-no-snen-reti.S | # Blackfin testcase for having RETI LSB set correctly when not self nested
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set our handler
imm32 P5, EVT11;
loadsym R1, _ivg11;
[P5] = R1;
loadsym R1, _fail_lvl;
[P5 + 4] = R1; /* IVG12 */
[P5 + 12] = R1; /* IVG14... |
stsp/binutils-ia16 | 5,691 | sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s | //Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp
// Spec Reference: c_dspldst ld_dr_i++m
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
M0 = 0 (X);
M1 = 0x4 (X);
M2 = 0x0 (X);
M3 = 0x4 (X);
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loads... |
stsp/binutils-ia16 | 2,744 | sim/testsuite/bfin/c_ldimmhalf_h_ibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp
// Spec Reference: ldimmhalf h ibml
# mach: bfin
.include "testutils.inc"
start
INIT_I_REGS -1;
INIT_L_REGS -1;
INIT_B_REGS -1;
INIT_M_REGS -1;
I0.H = 0x2000;
I1.H = 0x2002;
I2.H = 0x2004;
I3.H = 0x2006;
L0.H = 0x2008;
L1.H ... |
stsp/binutils-ia16 | 4,524 | sim/testsuite/bfin/c_dsp32mult_pair_u.s | //Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp
// Spec Reference: dsp32mult pair u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2... |
stsp/binutils-ia16 | 9,974 | sim/testsuite/bfin/a3.s | # mach: bfin
.include "testutils.inc"
start
loadsym P1, middle;
R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 );
R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 );
R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 );
R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 );
R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 );
R0 = W [ P1 + -12 ] ... |
stsp/binutils-ia16 | 1,919 | sim/testsuite/bfin/c_dsp32alu_byteop3.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp
// Spec Reference: dsp32alu byteop3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444... |
stsp/binutils-ia16 | 11,060 | sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp
// Spec Reference: regmv imlb-dep no stall
# mach: bfin
.include "testutils.inc"
start
// P-reg to I,M-reg to R-reg: no stall
//imm32 p0, 0x00001111;
imm32 p1, 0x12213330;
imm32 p2, 0x14415550;
imm32 p3, 0x16617770;
imm... |
stsp/binutils-ia16 | 5,635 | sim/testsuite/bfin/se_misaligned_fetch.S | //Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp
// Description: attempt to fetch code from misaligned address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
incl... |
stsp/binutils-ia16 | 3,203 | sim/testsuite/bfin/random_0011.S | # test acc shifts larger than they should be, and ASTAT flags
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x1890bdbc;
dmm32 A0.x, 0x00000079;
A0 = A0 << 0x2;
checkreg A0.w, 0x6242f6f0;
checkreg A0.x,... |
stsp/binutils-ia16 | 4,311 | sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s | //Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp
// Spec Reference: dagmodik l not zero & i+m >= b+l
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x00001000;
imm32 b1, 0x000010... |
stsp/binutils-ia16 | 5,096 | sim/testsuite/bfin/c_dsp32shift_fextx.s | //Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp
// Spec Reference: dsp32shift fext x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x0... |
stsp/binutils-ia16 | 1,549 | sim/testsuite/bfin/s12.s | // Shifter test program.
// Test instructions
// RL5 = EXPADJ R4 BY RL2;
# mach: bfin
.include "testutils.inc"
start
R0.L = 30; // large norm of small value
R0.H = 1; // make sure high half is not used
R1.L = 0x0000;
R1.H = 0x1000; // small norm (2) of large value
R7.L = EXPADJ( R1 , R0.L );
DBGA ( R7.L , ... |
stsp/binutils-ia16 | 8,708 | sim/testsuite/bfin/c_ldstiifp_ld_preg.s | //Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp
// Spec Reference: c_ldstiifp load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
... |
stsp/binutils-ia16 | 3,298 | sim/testsuite/bfin/c_loopsetup_preg_stld.s | //Original:/testcases/core/c_loopsetup_preg_stld/c_loopsetup_preg_stld.dsp
// Spec Reference: loopsetup preg st & ld
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
A0 = 0;
A1 = 0;
ASTAT = r0;
P1 = 9;
P2 = 8;
P0 = 7;
P4 = 6;
P5 = 5;
FP = 3;
imm32 r0, 0x00200005;
imm32 r1, 0x00300010;
imm32... |
stsp/binutils-ia16 | 7,480 | sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(g... |
stsp/binutils-ia16 | 3,574 | sim/testsuite/bfin/s16.s | // reg-based SHIFT test program.
# mach: bfin
.include "testutils.inc"
start
// Test FDEP with no sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x123f );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c... |
stsp/binutils-ia16 | 6,097 | sim/testsuite/bfin/c_dsp32mult_dr_iu.s | //Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp
// Spec Reference: dsp32mult single dr iu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00010002;
imm32 r1, 0x00023004;
imm32 r2, 0x03843725;
imm32 r3, 0x00084027;
imm32 r4, 0x00ab5d29;
imm32 r5, 0x00ac682b;
imm32 r6, 0x000c708d;
imm32 r7, ... |
stsp/binutils-ia16 | 6,095 | sim/testsuite/bfin/c_interr_nmi.S | //Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); ... |
stsp/binutils-ia16 | 6,609 | sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s | //Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp
// Spec Reference: c_dspldst ld_drhi_i++/--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
// initial values
//i0=0x3000;
//i1=0x4000;
//i2=0x5000;
//i3=0x6000;
loadsym I0, DATA_ADDR_3;
loadsym I1, DATA_ADDR_4... |
stsp/binutils-ia16 | 6,340 | sim/testsuite/bfin/se_usermode_protviol.S | //Original:/proj/frio/dv/testcases/seq/se_usermode_protviol/se_usermode_protviol.dsp
// Description: User mode "Illegal Use Supervsor Resource" Exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck... |
stsp/binutils-ia16 | 6,303 | sim/testsuite/bfin/c_dsp32mac_pair_a0_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_s/c_dsp32mac_pair_a0_s.dsp
// Spec Reference: dsp32mac pair a0 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
stsp/binutils-ia16 | 5,914 | sim/testsuite/bfin/c_dsp32alu_rh_p.s | //Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34645515;
imm32 r3, 0x46667717;
imm32 r4, 0xd678891b;
imm32 r5, 0x6e89ab1d;
imm32 r6, 0x74b45515;
imm32 r7, 0x8... |
stsp/binutils-ia16 | 10,070 | sim/testsuite/bfin/c_dsp32shift_ahalf_ln.s | //Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;... |
stsp/binutils-ia16 | 3,031 | sim/testsuite/bfin/dotproduct.s | # Blackfin testcase for a simple vector dot product using hard
# wired input buffers of 128 samples each. These values are in
# 1.15 signed .
# mach: bfin
.include "testutils.inc"
start
loadsym P0, _buf0
loadsym P1, _buf1
/* loop control
* number of loop iterations is 2^N with r4|=1<<N
* to process 128 sa... |
stsp/binutils-ia16 | 6,264 | sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s | //Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp
// Spec Reference: c_dspldst st_drhi_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
i... |
stsp/binutils-ia16 | 1,831 | sim/testsuite/bfin/c_except_illopcode.S | //Original:/proj/frio/dv/testcases/core/c_except_illopcode/c_except_illopcode.dsp
// Spec Reference: c_exception illegal opcode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe00000... |
stsp/binutils-ia16 | 9,978 | sim/testsuite/bfin/se_loop_nest_ppm.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////... |
stsp/binutils-ia16 | 4,845 | sim/testsuite/bfin/c_dsp32shift_align24.s | //Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp
// Spec Reference: dsp32shift align24
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7... |
stsp/binutils-ia16 | 2,078 | sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s | //Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp
// Spec Reference: dagmodik L=0, I incremented & decremented
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001200;
imm32 i3, 0x00001300;
imm32 m0, 0x00000000;
imm32 m1, ... |
stsp/binutils-ia16 | 5,681 | sim/testsuite/bfin/iir.s | # mach: bfin
// GENERIC BIQUAD:
// ---------------
// x ---------+---------|---------+-------y
// | |t1 |
// | D |
// | a1 | b1 |
// +---<-----|---->----+
// | | |
// | D | ... |
stsp/binutils-ia16 | 3,485 | sim/testsuite/bfin/dotproduct2.s | /* Vector Dot Product
* This program computes a simple vector dot product using hard
* wired input buffers of 128 samples each. These values are in
* 1.15 signed .
*/
# mach: bfin
.include "testutils.inc"
start
// load buffer addresses into pointer regs
loadsym I0, data0;
loadsym I1, data1;
// loop contro... |
stsp/binutils-ia16 | 9,932 | sim/testsuite/bfin/c_dsp32shift_lhalf_rp.s | //Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
imm32... |
stsp/binutils-ia16 | 3,498 | sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s | //Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp
// Spec Reference: dsp32mac dr_a1 iu (unsigned integer)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x7890afc7;
imm32 r2, 0x52248679;
imm3... |
stsp/binutils-ia16 | 1,180 | sim/testsuite/bfin/ashift_flags.s | # mach: bfin
.include "testutils.inc"
start
// load r1=0x7fffffff
// load r2=0x80000000
// load r3=0x000000ff
// load r4=0x00000000
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
_dbg r0;
_dbg r1;
_dbg r2;
_dbg r3;
_dbg r4;
R7 = 0;
ASTAT = R7;... |
stsp/binutils-ia16 | 4,914 | sim/testsuite/bfin/fir.s | # mach: bfin
// FIR FILTER COMPTUED DIRECTLY ON INPUT WITH NO
// INTERNAL STATE
// TWO OUTPUTS PER ITERATION
// This program computes a FIR filter without maintaining a buffer of internal
// state.
// This example computes two output samples per inner loop. The following
// diagram shows the alignment required for... |
stsp/binutils-ia16 | 6,094 | sim/testsuite/bfin/c_dsp32mult_dr_u.s | //Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp
// Spec Reference: dsp32mult single dr u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
stsp/binutils-ia16 | 2,626 | sim/testsuite/bfin/m3.s | // MAC test program.
// Test basic edge values
// UNSIGNED FRACTIONAL mode U
// test ops: "+=" "-="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
// load r5=0xffffffff
loadsym P0, data0;
R0 = [ P0 ++ ];... |
stsp/binutils-ia16 | 7,160 | sim/testsuite/bfin/c_ldstpmod_ld_dr_lo.s | //Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp
// Spec Reference: c_ldstpmod load dr lo
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS(0);
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = ... |
stsp/binutils-ia16 | 5,107 | sim/testsuite/bfin/c_dsp32shift_expadj_l.s | //Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp
// Spec Reference: dsp32shift expadj rl
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
i... |
stsp/binutils-ia16 | 4,844 | sim/testsuite/bfin/c_dsp32mult_dr_m_i.s | //Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp
// Spec Reference: dsp32mult single dr munop i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
stsp/binutils-ia16 | 7,579 | sim/testsuite/bfin/c_ldst_st_p_d_pp_h.s | //Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp
// Spec Reference: c_ldst st_p++/p-- h half
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm3... |
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