repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 8,456 | sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmrj_mvp/c_seq_ex3_ls_mmrj_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_... |
stsp/binutils-ia16 | 4,200 | sim/testsuite/bfin/c_dsp32shift_ones.s | //Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp
// Spec Reference: dsp32shift ones
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x88880000;
imm32 r1, 0x34560001;
imm32 r2, 0x08000002;
imm32 r3, 0x08000003;
imm32 r4, 0x08000004;
imm32 r5, 0x08000005;
imm32 r6, 0x08000006;
imm32 r7, 0x08... |
stsp/binutils-ia16 | 1,280 | sim/testsuite/bfin/c_br_preg_stall_ex1.s | //Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000... |
stsp/binutils-ia16 | 10,840 | sim/testsuite/bfin/c_ldstii_st_dreg.s | //Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp
// Spec Reference: c_ldstii store dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r... |
stsp/binutils-ia16 | 7,291 | sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp
// Spec Reference: sequencer stage ex1 ( call + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
IN... |
stsp/binutils-ia16 | 9,934 | sim/testsuite/bfin/c_dsp32shift_lhalf_rn.s | //Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm3... |
stsp/binutils-ia16 | 1,523 | sim/testsuite/bfin/s6.s | // Test r4 = VMAX/VMAX (r5,r1) A0<<2;
# mach: bfin
.include "testutils.inc"
start
// Both max values are in high half, hence both bits
// into A0 are 1
A0 = 0;
R1.L = 0x2; // max in r1 is 3
R1.H = 0x3;
R0.L = 0x6; // max in r0 is 7
R0.H = 0x7;
R6 = VIT_MAX( R1 , R0 ) (ASL);
DBGA ( R6.L , 0x0007 );
DBG... |
stsp/binutils-ia16 | 4,973 | sim/testsuite/bfin/c_regmv_imlb_dr.s | //Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp
// Spec Reference: regmv imlb to dr
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
// i to dreg
R0 = I0;
R1 = I0;
R2 = I0;
R3 = I0;
R4 =... |
stsp/binutils-ia16 | 7,255 | sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp
// Spec Reference: sequencer stage ex2 ( brcc (mis-pred)+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include... |
stsp/binutils-ia16 | 11,608 | sim/testsuite/bfin/c_ldstidxl_ld_preg.s | //Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp
// Spec Reference: c_ldstidxl load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
... |
stsp/binutils-ia16 | 6,719 | sim/testsuite/bfin/c_dsp32mac_dr_a1_i.s | //Original:/testcases/core/c_dsp32mac_dr_a1_i/c_dsp32mac_dr_a1_i.dsp
// Spec Reference: dsp32mac dr a1 i (signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd00... |
stsp/binutils-ia16 | 5,431 | sim/testsuite/bfin/c_logi2op_log_r_shft.s | //Original:/testcases/core/c_logi2op_log_r_shft/c_logi2op_log_r_shft.dsp
// Spec Reference: Logi2op >>=
# mach: bfin
.include "testutils.inc"
start
// Logical >>= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81... |
stsp/binutils-ia16 | 5,801 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_xb.s | //Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp
// Spec Reference: c_ldst ld d [p--] xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP ... |
stsp/binutils-ia16 | 7,980 | sim/testsuite/bfin/s14.s | // reg-based SHIFT test program.
// Test r4 = ASHIFT (r2 by rl3);
// Test r4 = LSHIFT (r2 by rl3);
# mach: bfin
.include "testutils.inc"
start
R0.L = 0x0001;
R0.H = 0x8000;
// arithmetic
// left by 31
// 8000 0001 -> 8000 0000
R7 = 0;
ASTAT = R7;
R3.L = 31;
R3.H = 0;
R6 = ASHIFT R0 BY R3.L;
DBGA ( R... |
stsp/binutils-ia16 | 5,417 | sim/testsuite/bfin/c_dsp32alu_rp.s | //Original:/testcases/core/c_dsp32alu_rp/c_dsp32alu_rp.dsp
// Spec Reference: dsp32alu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0 = R0... |
stsp/binutils-ia16 | 1,701 | sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s | //Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp
// Spec Reference: loopsetup preg lc0 / 2
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P5 = 20;
P1 = 30;
P2 = 40;
P3 = 50;
P4 = 60;
//p5 = 7;
SP = 80 (X);
FP = 90 (X);
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 ... |
stsp/binutils-ia16 | 8,846 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;... |
stsp/binutils-ia16 | 1,068 | sim/testsuite/bfin/c_brcc_bp4.s | //Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT ... |
stsp/binutils-ia16 | 6,112 | sim/testsuite/bfin/c_dsp32alu_rh_rnd12_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x45678ad1;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xf4445545;
imm32 r3, 0x46667767;
imm32 r4, 0xe678891b;
imm32 r5, 0x6f89ab1d;
imm32... |
stsp/binutils-ia16 | 3,350 | sim/testsuite/bfin/c_ldimmhalf_lzhi_ibml.s | //Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: ldimmhalf lzhi ibml
I0 = 0x2001 (Z);
I0.H = 0x2000;
I1 = 0x2003 (Z);
I1.H = 0x2002;
I2 = 0x2005 (Z);
I2.H = 0x2004;
I3 = 0x2007 (Z);
I3.H = 0x2006;
L0 = 0x2009 (Z);
L0.H = 0x... |
stsp/binutils-ia16 | 5,691 | sim/testsuite/bfin/se_excpt_ssstep.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp
// Description: EXCPT instruction vs Single Step Exception Priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
includ... |
stsp/binutils-ia16 | 5,591 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_h.s | //Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp
// Spec Reference: c_ldst ld d [p--] h
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// initial values
loadsym p5, DATA_ADDR_1, 0x10;
loadsym p1, DATA_AD... |
stsp/binutils-ia16 | 1,523 | sim/testsuite/bfin/s7.s | // Test r4 = VMAX/VMAX (r5,r1) A0>>2;
# mach: bfin
.include "testutils.inc"
start
// Both max values are in high half, hence both bits
// into A0 are 1
A0 = 0;
R1.L = 0x2; // max in r1 is 3
R1.H = 0x3;
R0.L = 0x6; // max in r0 is 7
R0.H = 0x7;
R6 = VIT_MAX( R1 , R0 ) (ASR);
DBGA ( R6.L , 0x0007 );
DBG... |
stsp/binutils-ia16 | 8,717 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_rn.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0... |
stsp/binutils-ia16 | 7,126 | sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_j_mv_pop/c_seq_ex1_j_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_RE... |
stsp/binutils-ia16 | 1,637 | sim/testsuite/bfin/c_loopsetup_preg_lc0.s | //Original:/testcases/core/c_loopsetup_preg_lc0/c_loopsetup_preg_lc0.dsp
// Spec Reference: loopsetup preg lc0
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0... |
stsp/binutils-ia16 | 1,452 | sim/testsuite/bfin/c_ldimmhalf_drhi.s | //Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp
// Spec Reference: ldimmhalf dreg hi
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.H = 0x0001;
R1.H = 0x0003;
R2.H = 0x0005;
R3.H = 0x0007;
R4.H = 0x0009;
R5.H = 0x000b;
R6.H = 0x000d;
R7.H = 0x000f;
CHECKREG r0, 0x0001... |
stsp/binutils-ia16 | 1,453 | sim/testsuite/bfin/loop_strncpy.s | # Blackfin testcase for loop counter values when jumping out from the last insn
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
loadsym r1, dest;
r0 = r1;
loadsym r1, src;
r2 = 0x10;
_strncpy:
CC = R2 == 0;
if CC JUMP 4f;
P2 = R2 ; /* size */
P0 = R0 ; /* dst*/
P1 = R... |
stsp/binutils-ia16 | 1,725 | sim/testsuite/bfin/brcc.s | # mach: bfin
.include "testutils.inc"
start
/* Stall tests */
r0 = 0;
r1 = 1;
loadsym p0, foo;
p1 = p0;
pass_1:
cc = r0;
nop;
nop;
if cc jump _fail_1;
[p0++] = p0;
[p0++] = p0;
r7 = p0;
r5 = CC;
P1 += 8;
r6 = p1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if !cc jump over;
_fail_1:
[p0++... |
stsp/binutils-ia16 | 7,545 | sim/testsuite/bfin/c_ldst_st_p_d_pp_b.s | //Original:/testcases/core/c_ldst_st_p_d_pp_b/c_ldst_st_p_d_pp_b.dsp
// Spec Reference: c_ldst st_p++ b byte
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
im... |
stsp/binutils-ia16 | 4,824 | sim/testsuite/bfin/random_0032.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x74308400 | _VS | _AV1S | _AV0S | _CC | _AN);
dmm32 A0.w, 0x5d4cf98c;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0xba16ffff;
imm32 R4, 0x8000109d;
imm32 R6, 0x8000b212;
R6.L = (A0 -= R4.L * R0.L) (IH);
checkreg R6, 0x80008000;
checkreg A0.w... |
stsp/binutils-ia16 | 5,459 | sim/testsuite/bfin/c_ldst_ld_d_p_xb.s | //Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp
// Spec Reference: c_ldst ld d [p] xb
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 8 bits from me... |
stsp/binutils-ia16 | 5,702 | sim/testsuite/bfin/c_dsp32alu_min.s | //Original:/testcases/core/c_dsp32alu_min/c_dsp32alu_min.dsp
// Spec Reference: dsp32alu dregs = min ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0xf6667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;... |
stsp/binutils-ia16 | 2,209 | sim/testsuite/mips/mdmx-ob-sb1.s | # MDMX .OB op tests.
# mach: sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-mdmx.inc"
setup
.set noreorder
.ent DIAG
DIAG:
enable_mdmx
# set Status.SBX to enable SB-1 extensions.
mfc0 $2, $12
or $2, $2, (1 << 16)
mtc0 $2, $12
###
###... |
stsp/binutils-ia16 | 1,089 | sim/testsuite/mips/fpu64-ps-sb1.s | # mips test sanity, expected to pass.
# mach: sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.macro check_ps psval, upperval, lowerval
.set push
.set noreorder
cvt.s.pu $f0, \psval # upper
cvt.s.pl $f2, \psval # lower
li.s $f4, \upperval
li.s $f6, ... |
stsp/binutils-ia16 | 3,397 | sim/testsuite/mips/r6-64.s | # mips64 specific r6 tests (non FPU)
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
.data
d0: .dword 0
dval: .dword 0xaa55bb66cc77dd88
d1: .dword 0xaaaabbbbccccdddd
d2: .dword 256
dlo: .dword 0xa... |
stsp/binutils-ia16 | 1,054 | sim/testsuite/mips/hilo-hazard-4.s | # Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
#
# mach: all
# as: -mabi=eabi -mmicromips
# ld: -N -Ttext=0x80010000
# output: pass\\n
# Copyright (C) 2013-2022 Free Software Foundation, Inc.
# Contributed by Andrew Bennett (andrew.bennett@imgtec.com)
#
# This file is part of the MIPS sim.
#
# Th... |
stsp/binutils-ia16 | 36,048 | sim/testsuite/mips/mips32-dsp.s | # MIPS32 DSP ASE test
# mach: mips32r2 mips64r2
#as: -mdsp
#ld: -N -Ttext=0x80010000
#output: *\\npass\\n
# Copyright (C) 2005-2022 Free Software Foundation, Inc.
# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.
#
# This file is part of the GNU simulators.
#
# This program is free software; you ca... |
stsp/binutils-ia16 | 3,637 | sim/testsuite/mips/r6.s | # mips r6 tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.data
dval1: .word 0xabcd1234
dval2: .word 0x1234eeff
.fill 248,1,0
dval3: .word 0x55555555
.fill 260,1,0
dval4: .word 0xaa... |
stsp/binutils-ia16 | 3,374 | sim/testsuite/mips/r6-branch.s | # mips r6 branch tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
li $14, 0xffffffff
li $13, 0x123
li $12, 0x45
li $7, 0x45
li $8, 0xfffffffe
li ... |
stsp/binutils-ia16 | 6,187 | sim/testsuite/mips/fpu64-ps.s | # mips test sanity, expected to pass.
# mach: mips64 sb1
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.macro check_ps psval, upperval, lowerval
.set push
.set noreorder
cvt.s.pu $f0, \psval # upper
cvt.s.pl $f2, \psval # lower
li.s $f4, \upperval
li.s... |
stsp/binutils-ia16 | 1,017,027 | sim/testsuite/mips/mips32-dsp2.s | # MIPS32 DSP REV 2 ASE test
# mach: mips32r2 mips64r2
#as: -mdspr2
#ld: -N -Ttext=0x80010000
#output: *\\npass\\n
# Copyright (C) 2006 MIPS Technologies, Inc.
# All rights reserved.
# Contributed by Chao-ying Fu (fu@mips.com).
#
# This file is part of the GNU simulators.
#
# This program is free software; you can r... |
stsp/binutils-ia16 | 21,770 | sim/testsuite/mips/r6-fpu.s | # mips r6 fpu test for FMADD/FMSUB etc.
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test qNaN format is 754-2008"
li $4, 0x0
li $5, 0x0
li $6, 0x7fc000... |
stsp/binutils-ia16 | 15,703 | sim/testsuite/mips/mdmx-ob.s | # MDMX .OB op tests.
# mach: mips64 sb1
# as: -mabi=eabi
# as(mips64): -mabi=eabi -mdmx
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-mdmx.inc"
setup
.set noreorder
.ent DIAG
DIAG:
enable_mdmx
###
### Non-accumulator, non-CC-using .ob format ops.
###
### K... |
stsp/binutils-ia16 | 1,540 | sim/testsuite/aarch64/xtl.s | #mach: aarch64
# Check the extend long instructions: sxtl, sxtl2, uxtl, uxtl2.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0xfcfdfeff
.word 0xf8f9fafb
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
uxtl v1.8h, v0.8b
uxtl2 v2.8h, v0.16b
addv h3, v1.8h
addv h4... |
stsp/binutils-ia16 | 1,600 | sim/testsuite/aarch64/mla.s | # mach: aarch64
# Check the vector multiply add instruction: mla.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
m8b:
.word 0x110a0502
.word 0x4132251a
m16b:
.word 0x110a0502
.word 0x4132251a
.word 0x917a6552
.word 0x01e2c5aa
m4h:
.word... |
stsp/binutils-ia16 | 1,212 | sim/testsuite/aarch64/xtn.s | # mach: aarch64
# Check the extract narrow instructions: xtn, xtn2.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
input2:
.word 0x14131211
.word 0x18171615
.word 0x1c1b1a19
.word 0x201f1e1d
x16b:
.word 0x07050301
.word 0x0f0d0b09
.word... |
stsp/binutils-ia16 | 3,460 | sim/testsuite/aarch64/fcvtz.s | # mach: aarch64
# Check the FP convert to int round toward zero instructions: fcvtszs32,
# fcvtszs, fcvtszd32, fcvtszd, fcvtzu.
# For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN.
# For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN.
# For 32-bit unsigned convert, test values 1.5, INT... |
stsp/binutils-ia16 | 1,341 | sim/testsuite/aarch64/sumov.s | # mach: aarch64
# Check the mov from asimd to general reg instructions: smov, umov.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0xf4f3f2f1
.word 0xf8f7f6f5
start
adrp x0, input
ldr q0, [x0, #:lo12:input]
smov w0, v0.b[0]
smov w3, v0.b[12]
cmp w0, #1
bne .Lfai... |
stsp/binutils-ia16 | 1,394 | sim/testsuite/aarch64/bit.s | # mach: aarch64
# Check the bitwise vector instructions: bif, bit, bsl, eor.
.include "testutils.inc"
.data
.align 4
inputa:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
inputb:
.word 0x40302010
.word 0x80706050
.word 0xc0b0a090
.word 0x01f0e0d0
mask:
.word 0xFF00FF00
.word 0x00FF0... |
stsp/binutils-ia16 | 1,216 | sim/testsuite/aarch64/fminnm.s | # mach: aarch64
# Check the FP min/max number instructions: fminnm, fmaxnm, dminnm, dmaxnm.
# For min, check 2/1, 1/0, -1/-Inf.
# For max, check 1/2, -1/0, 1/+inf.
.include "testutils.inc"
start
fmov s0, #2.0
fmov s1, #1.0
fminnm s2, s0, s1
fcmp s2, s1
bne .Lfailure
fmov d0, #2.0
fmov d1, #1.0
fminnm d2, d0... |
stsp/binutils-ia16 | 2,948 | sim/testsuite/aarch64/ldnr.s | # mach: aarch64
# Check the load single 1-element structure and replicate to all lanes insns:
# ld1r, ld2r, ld3r, ld4r.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0... |
stsp/binutils-ia16 | 1,155 | sim/testsuite/aarch64/fcmXX.s | # mach: aarch64
# Check the FP scalar compare zero instructions: fcmeq, fcmle, fcmlt, fcmge,
# fcmgt.
# Check values -1, 0, and 1.
.include "testutils.inc"
start
fmov s0, wzr
fcmeq s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #-1
bne .Lfailure
fmov s0, #-1.0
fcmeq s1, s0, #0.0
mov w0, v1.s[0]
cmp w0, #0
bne .Lfai... |
stsp/binutils-ia16 | 2,068 | sim/testsuite/aarch64/fstur.s | # mach: aarch64
# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq.
# Check the values -1, and XXX_MAX, which tests all bits.
# Check with offsets -256 and 255, which tests all bits.
# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq.
.include "testutils.inc"
.data
... |
stsp/binutils-ia16 | 1,619 | sim/testsuite/aarch64/cmtst.s | # mach: aarch64
# Check the vector compare bitwise test instruction: cmtst.
.include "testutils.inc"
.data
.align 4
inputb:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
inputh:
.word 0x00020001
.word 0x00040003
.word 0x00060005
.word 0x00800007
inputs:
.word 0x00000001
.word 0x0000... |
stsp/binutils-ia16 | 1,510 | sim/testsuite/aarch64/adds.s | # mach: aarch64
# Check the basic integer compare instructions: adds, adds64, subs, subs64.
# For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C),
# and MIN_INT and -1 (V),
# Also check -2 and 1 (not C).
# For sub, negate the second value.
.include "testutils.inc"
start
mov w0, #1
mov w1, #-1
a... |
stsp/binutils-ia16 | 2,162 | sim/testsuite/aarch64/stn_single.s | # mach: aarch64
# Check the store single 1-element structure to one lane instructions:
# st1, st2, st3, st4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.wor... |
stsp/binutils-ia16 | 2,209 | sim/testsuite/aarch64/fcmp.s | # mach: aarch64
# Check the FP compare instructions: fcmps, fcmpzs, fcmpes, fcmpzes, fcmpd,
# fcmpzd, fcmped, fcmpzed.
# For 1 operand compares, check 0, 1, -1, +Inf, -Inf.
# For 2 operand compares, check 1/1, 1/-2, -1/2, +Inf/+Inf, +Inf/-Inf.
# FIXME: Check for qNaN and sNaN when exception raising support added.
.in... |
stsp/binutils-ia16 | 1,605 | sim/testsuite/aarch64/mls.s | # mach: aarch64
# Check the vector multiply subtract instruction: mls.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
m8b:
.word 0xf1f8fd00
.word 0xc1d0dde8
m16b:
.word 0xf1f8fd00
.word 0xc1d0dde8
.word 0x71889db0
.word 0x01203d58
m4h:
... |
stsp/binutils-ia16 | 1,828 | sim/testsuite/aarch64/ldn_single.s | # mach: aarch64
# Check the load single 1-element structure to one lane instructions:
# ld1, ld2, ld3, ld4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word... |
stsp/binutils-ia16 | 2,142 | sim/testsuite/aarch64/ldn_multiple.s | # mach: aarch64
# Check the load multiple structure instructions: ld1, ld2, ld3, ld4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0xf... |
stsp/binutils-ia16 | 2,672 | sim/testsuite/aarch64/stn_multiple.s | # mach: aarch64
# Check the store multiple structure instructions: st1, st2, st3, st4.
# Check the addressing modes: no offset, post-index immediate offset,
# post-index register offset.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
.word 0x... |
stsp/binutils-ia16 | 3,445 | sim/testsuite/aarch64/uzp.s | # mach: aarch64
# Check the unzip instructions: uzp1, uzp2.
.include "testutils.inc"
.data
.align 4
input1:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
input2:
.word 0x14131211
.word 0x18171615
.word 0x1c1b1a19
.word 0x201f1e1d
zl8b:
.word 0x07050301
.word 0x17151311
zu8b:
.word ... |
stsp/binutils-ia16 | 1,512 | sim/testsuite/aarch64/mul.s | # mach: aarch64
# Check the non-widening multiply vector instruction: mul.
.include "testutils.inc"
.data
.align 4
input:
.word 0x04030201
.word 0x08070605
.word 0x0c0b0a09
.word 0x100f0e0d
m8b:
.word 0x10090401
.word 0x40312419
m16b:
.word 0x10090401
.word 0x40312419
.word 0x90796451
.word 0x00e1c4a9
m4... |
stsp/binutils-ia16 | 17,132 | sim/testsuite/ft32/basic.s | # check that basic insns work.
# mach: ft32
.include "testutils.inc"
start
ldk $r0,__PMSIZE
EXPECT $r0,0x00040000
ldk $r0,__RAMSIZE
EXPECT $r0,0x00010000
ldk $r4,10
add $r4,$r4,23
EXPECT $r4,33
# lda, sta
.data
tmp: .long 0
.text
xor.l $r0,$r0,$r0
EXPECT $r0,0x0000... |
stsp/binutils-ia16 | 1,283 | sim/testsuite/msp430/mpyull_hwmult.s | # Test that unsigned widening multiplication of 32-bit operands to produce a
# 64-bit result is simulated correctly, when using 32-bit or F5series hardware
# multiply functionality.
# 0xffff fffc * 0x2 = 0x1 ffff fff8
# mach: msp430
# 32-bit hwmult register addresses
.set MPY32L, 0x0140
.set MPY32H, 0x0142
.set OP2L, ... |
stsp/binutils-ia16 | 1,713 | sim/testsuite/pru/dram.s | # Check that DRAM memory access works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General ... |
stsp/binutils-ia16 | 1,026 | sim/testsuite/pru/dmem-zero-trap.s | # Check that DMEM zero address access can be trapped.
# mach: pru
# sim: --error-null-deref
# xerror:
# output: core: 4 byte read to unmapped address 0x0 at *\n
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
#... |
stsp/binutils-ia16 | 1,057 | sim/testsuite/pru/loop-imm.s | # Check that loop insn works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public Li... |
stsp/binutils-ia16 | 1,071 | sim/testsuite/pru/loop-reg.s | # Check that loop insn works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public Li... |
stsp/binutils-ia16 | 1,290 | sim/testsuite/pru/lmbd.s | # Check that lmbd insn works.
# mach: pru
# Copyright (C) 2020-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public Li... |
stsp/binutils-ia16 | 1,847 | sim/testsuite/pru/mul.s | # Check that multiplication works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Publ... |
stsp/binutils-ia16 | 1,125 | sim/testsuite/pru/subreg.s | # Check that subregister addressing works.
# mach: pru
# Copyright (C) 2016-2022 Free Software Foundation, Inc.
# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU Gene... |
stsp/binutils-ia16 | 10,261 | sim/testsuite/h8300/biand.s | # Hitachi H8 testcase 'biand', 'bior', 'bixor', 'bild', 'bist', 'bistz'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.i... |
stsp/binutils-ia16 | 3,531 | sim/testsuite/h8300/rotxl.s | # Hitachi H8 testcase 'rotxl'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte... |
stsp/binutils-ia16 | 14,357 | sim/testsuite/h8300/bset.s | # Hitachi H8 testcase 'bset', 'bclr'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
#
# ... |
stsp/binutils-ia16 | 1,551 | sim/testsuite/h8300/tas.s | # Hitachi H8 testcase 'tas'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_dst: .byte 0
star... |
stsp/binutils-ia16 | 3,566 | sim/testsuite/h8300/shal.s | # Hitachi H8 testcase 'shal'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
stsp/binutils-ia16 | 11,552 | sim/testsuite/h8300/band.s | # Hitachi H8 testcase 'band', 'bor', 'bxor', 'bld', 'bst', 'bstz'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
... |
stsp/binutils-ia16 | 8,647 | sim/testsuite/h8300/xorb.s | # Hitachi H8 testcase 'xor.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# xor.b #xx... |
stsp/binutils-ia16 | 3,129 | sim/testsuite/h8300/bra.s | # Hitachi H8 testcase 'bra'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx)
.data
.al... |
stsp/binutils-ia16 | 3,836 | sim/testsuite/h8300/ldm.s | # Hitachi H8 testcase 'ldm', 'stm'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
.align 4
_stack: .long 0,1,... |
stsp/binutils-ia16 | 20,967 | sim/testsuite/h8300/neg.s | # Hitachi H8 testcase 'neg.b, neg.w, neg.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:... |
stsp/binutils-ia16 | 2,231 | sim/testsuite/h8300/jmp.s | # Hitachi H8 testcase 'jmp'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
vector_area:
.fill 0x400, 1, 0
... |
stsp/binutils-ia16 | 18,401 | sim/testsuite/h8300/addb.s | # Hitachi H8 testcase 'add.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.b #xx:8,... |
stsp/binutils-ia16 | 4,684 | sim/testsuite/h8300/mac.s | # Hitachi H8 testcase 'mac'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
src1: .word 0
src2: .word ... |
stsp/binutils-ia16 | 25,098 | sim/testsuite/h8300/mova.s | # Hitachi H8 testcase 'mova'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
foo: .long 0x01010101
.long 0x1... |
stsp/binutils-ia16 | 1,994 | sim/testsuite/h8300/cmpl.s | # Hitachi H8 testcase 'cmp.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu ==... |
stsp/binutils-ia16 | 1,711 | sim/testsuite/h8300/orl.s | # Hitachi H8 testcase 'or.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu ==... |
stsp/binutils-ia16 | 1,441 | sim/testsuite/h8300/subs.s | # Hitachi H8 testcase 'subs'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
... |
stsp/binutils-ia16 | 23,825 | sim/testsuite/h8300/cmpb.s | # Hitachi H8 testcase 'cmp.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# cmp.b #xx:... |
stsp/binutils-ia16 | 20,865 | sim/testsuite/h8300/not.s | # Hitachi H8 testcase 'not.b, not.w, not.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:... |
stsp/binutils-ia16 | 2,224 | sim/testsuite/h8300/subl.s | # Hitachi H8 testcase 'sub.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == ... |
stsp/binutils-ia16 | 7,908 | sim/testsuite/h8300/ldc.s | # Hitachi H8 testcase 'ldc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_pre:
.byte 0
byte_src:
.byte... |
stsp/binutils-ia16 | 6,902 | sim/testsuite/h8300/subb.s | # Hitachi H8 testcase 'sub.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# sub.b #xx... |
stsp/binutils-ia16 | 12,009 | sim/testsuite/h8300/andb.s | # Hitachi H8 testcase 'and.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# and.b #xx... |
stsp/binutils-ia16 | 2,168 | sim/testsuite/h8300/addw.s | # Hitachi H8 testcase 'add.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.w xx:3, ... |
stsp/binutils-ia16 | 1,503 | sim/testsuite/h8300/orw.s | # Hitachi H8 testcase 'or.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ... |
stsp/binutils-ia16 | 26,009 | sim/testsuite/h8300/rotl.s | # Hitachi H8 testcase 'rotl'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte ... |
stsp/binutils-ia16 | 23,163 | sim/testsuite/h8300/extl.s | # Hitachi H8 testcase 'exts.l, extu.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data... |
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