repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/newlib-ia16 | 2,442 | winsup/cygwin/math/ceil.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "ceil.S"
.text
.align 4
.globl __MINGW_USYMBOL(ceil)
.def __MINGW_US... |
stsp/newlib-ia16 | 1,975 | winsup/cygwin/math/frexpl.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
/*
* frexpl(long double x, int* expnt) extracts the exponent from x.
* It ret... |
stsp/newlib-ia16 | 1,082 | winsup/cygwin/math/nearbyintl.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "nearbyintl.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif... |
stsp/newlib-ia16 | 1,237 | winsup/cygwin/math/copysignl.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
/*
* Written by J.T. Conklin <jtc@netbsd.org>.
* Changes for long double by Ulrich Drepper <drepper@cy... |
stsp/newlib-ia16 | 1,940 | winsup/cygwin/math/exp2l.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "exp2l.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.glo... |
stsp/newlib-ia16 | 1,085 | winsup/cygwin/math/nearbyint.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "nearbyint.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
... |
stsp/newlib-ia16 | 1,715 | winsup/cygwin/math/log1pl.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "log1pl.S"
.text
/* The fyl2xp1 can only be used for values in
-1 ... |
stsp/newlib-ia16 | 1,557 | winsup/cygwin/math/internal_logl.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "internal_logl.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#en... |
stsp/newlib-ia16 | 1,088 | winsup/cygwin/math/nearbyintf.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "nearbyintf.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif... |
stsp/newlib-ia16 | 1,707 | winsup/cygwin/math/log2l.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "log2l.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
one:... |
stsp/newlib-ia16 | 1,977 | winsup/cygwin/math/exp2.S | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "exp2.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.glob... |
stsp/binutils-ia16 | 24,567 | gold/testsuite/dwp_test_2.s | .file "dwp_test_2.cc"
.text
.Ltext0:
.section .text._Z4f13iv,"axG",@progbits,_Z4f13iv,comdat
.weak _Z4f13iv
.type _Z4f13iv, @function
_Z4f13iv:
.LFB0:
.file 1 "dwp_test.h"
.loc 1 70 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 70 0
p... |
stsp/binutils-ia16 | 1,085 | gold/testsuite/arm_thm_jump8.s | # arm_thm_jump8.s
# Test R_ARM_THM_JUMP8 relocations just within the branch range limits.
.syntax unified
.arch armv5te
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx ... |
stsp/binutils-ia16 | 22,230 | gold/testsuite/dwp_test_main.s | .file "dwp_test_main.cc"
.text
.Ltext0:
.section .rodata
.LC0:
.string "dwp_test_main.cc"
.LC1:
.string "c1.testcase1()"
.LC2:
.string "c1.t1a()"
.LC3:
.string "c1.testcase2()"
.LC4:
.string "c1.testcase3()"
.LC5:
.string "c1.testcase4()"
.LC6:
.string "c2.testcase1()"
.LC7:
.string "c2.testcase2()"
.LC8:
.... |
stsp/binutils-ia16 | 8,232 | gold/testsuite/dwp_test_1b.s | .file "dwp_test_1b.cc"
.text
.Ltext0:
.globl c3
.bss
.align 4
.type c3, @object
.size c3, 4
c3:
.zero 4
.text
.globl _Z4t16av
.type _Z4t16av, @function
_Z4t16av:
.LFB1:
.file 1 "dwp_test_1b.cc"
.loc 1 33 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cf... |
stsp/binutils-ia16 | 1,297 | gold/testsuite/thumb_bl_out_of_range_local.s | # thumb_bl_out_of_range_local.s
# Test THUMB/THUMB-2 bl instructions just out of the branch range limits
# and with local branch targets.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 6
.code 16
.thumb_func
.type .Lbackward_target, %function
.Lbackw... |
stsp/binutils-ia16 | 1,345 | gold/testsuite/thumb_blx_in_range.s | # thumb_blx_in_range.s
#
# Test THUMB/THUMB-2 blx instructions just within the branch range limits.
# Because bit 1 of the branch target comes from the branch instruction
# address, the branch range from PC (branch instruction address + 4) is
# acutally -((1<<22) + 2) to ((1<<22) - 4) for THUMB and -((1<<24) + 2) to
# ... |
stsp/binutils-ia16 | 1,304 | gold/testsuite/aarch64_relocs.s | .text
test_R_AARCH64_MOVW_UABS_G0:
movz x4, :abs_g0:abs_0x1234
movz x4, :abs_g0:abs_0x1234 + 4
test_R_AARCH64_MOVW_UABS_G0_NC:
movz x4, :abs_g0_nc:abs_0x1234
movz x4, :abs_g0_nc:abs_0x1234 + 0x45000
test_R_AARCH64_MOVW_UABS_G1:
movz x4, :abs_g1:abs_0x1234 - 4
movz x4, :abs_g1:abs_0x11000
movz x4, :abs_g1:abs_... |
stsp/binutils-ia16 | 1,071 | gold/testsuite/thumb_bl_in_range.s | # thumb_bl_in_range.s
# Test THUMB/THUMB-2 bl instructions just within the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size... |
stsp/binutils-ia16 | 1,301 | gold/testsuite/thumb_bl_out_of_range.s | # thumb_bl_out_of_range.s
# Test THUMB/THUMB-2 bl instructions just out of the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 6
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
b... |
stsp/binutils-ia16 | 1,549 | gold/testsuite/thumb_blx_out_of_range.s | # thumb_blx_out_of_range.s
# Test THUMB/THUMB-2 blx instructions just out of the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 4
.global _forward_target
.global _backward_target
.type _backword_target, %function
_backward_target... |
stsp/binutils-ia16 | 1,433 | gold/testsuite/pr20308_gd.S | .text
.p2align 4,,15
.globl get_gd
.type get_gd, @function
get_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@PLT
addl $8, %esp
popl %ebx
ret
.size get_gd, .-get_gd
.p2align 4,,15
.globl set_gd
.type set_gd, @f... |
stsp/binutils-ia16 | 1,074 | gold/testsuite/gnu_property_b.S | #define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEO... |
stsp/binutils-ia16 | 1,565 | gold/testsuite/pr20308_ld.S | .text
.p2align 4,,15
.globl get_ld
.type get_ld, @function
get_ld:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal ld@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
leal ld@dtpoff(%eax), %eax
addl $8, %esp
popl %ebx
ret
.size get_ld, .-get_ld
.p2align 4,,15
.glob... |
stsp/binutils-ia16 | 1,083 | gold/testsuite/arm_thm_jump11.s | # arm_thm_jump11.s
# Test R_ARM_THM_JUMP11 relocations just within the branch range limits.
.syntax unified
.arch armv5te
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
b... |
stsp/binutils-ia16 | 38,771 | gold/testsuite/dwp_test_1.s | .file "dwp_test_1.cc"
.text
.Ltext0:
.section .text._Z4f13iv,"axG",@progbits,_Z4f13iv,comdat
.weak _Z4f13iv
.type _Z4f13iv, @function
_Z4f13iv:
.LFB0:
.file 1 "dwp_test.h"
.loc 1 70 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 70 0
p... |
stsp/binutils-ia16 | 1,116 | gold/testsuite/gnu_property_a.S | #define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
... |
stsp/binutils-ia16 | 1,642 | gold/testsuite/retain_1.s | .global discard0
.section .bss.discard0,"aw"
.type discard0, %object
discard0:
.zero 2
.global discard1
.section .bss.discard1,"aw"
.type discard1, %object
discard1:
.zero 2
.global discard2
.section .data.discard2,"aw"
.type discard2, %object
discard2:
.word 1
.section .bss.sdiscard0,"aw"
.type sdisca... |
stsp/binutils-ia16 | 1,244 | gold/testsuite/gnu_property_c.S | #define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEO... |
stsp/binutils-ia16 | 1,568 | sim/bfin/linux-fixed-code.s | /* Linux fixed code userspace ABI
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the... |
stsp/binutils-ia16 | 1,029 | sim/testsuite/sh/fsrra.s | # sh testcase for fsrra
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsrra_single:
set_grs_a5a5
set_fprs_a5a5
# 1/sqrt(0.0) = +infinity.
fldi0 fr0
fsrra fr0
assert_fpreg_x 0x7f800000, fr0
# 1/sqrt(1.0) = 1.0.
fldi1 fr0
fsrra fr0
asser... |
stsp/binutils-ia16 | 3,058 | sim/testsuite/sh/pshai.s | # sh testcase for psha <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_imm: ! shift arithmetic, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, a0
psha #0, a0
asser... |
stsp/binutils-ia16 | 1,167 | sim/testsuite/sh/fadd.s | # sh testcase for fadd
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fadd_freg_freg_b0:
set_grs_a5a5
set_fprs_a5a5
bank0
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 2 fr1
fldi0 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
fldi1 fr0
fldi0 fr1
fadd fr0, fr1
assert_fp... |
stsp/binutils-ia16 | 2,259 | sim/testsuite/sh/bset.s | # sh testcase for bset
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bset_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bset.b #0, @(3, r1)
assertmem _x, 0x1
bset.b #1, @(3, r1)
assertmem _x, 0x3
bset.b ... |
stsp/binutils-ia16 | 1,807 | sim/testsuite/sh/pdec.s | # sh testcase for pdec
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pdecx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pdec x0, y0
assert_sreg 0xa5a40000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
... |
stsp/binutils-ia16 | 1,557 | sim/testsuite/sh/fdiv.s | # sh testcase for fdiv
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fdiv_single:
# Single test
set_grs_a5a5
set_fprs_a5a5
single_prec
# 1.0 / 0.0 should be INF
# (and not crash the sim).
fldi0 fr0
fldi1 fr1
fdiv fr0, fr1
assert_fpreg_x 0x7f800000, fr1
# 0.0 / 1.0 == 0.0.
fldi0... |
stsp/binutils-ia16 | 1,589 | sim/testsuite/sh/bld.s | # sh testcase for bld
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bld_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bld.b #0, @(0, r1)
bf8k mfail
bld.b #1, @(0, r1)
bt8k mfail
bld.b #2, @(0, r... |
stsp/binutils-ia16 | 1,730 | sim/testsuite/sh/fsca.s | # sh testcase for fsca
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsca:
set_grs_a5a5
set_fprs_a5a5
# Start with angle zero
mov.l zero, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
mov.l plus_90, r0
lds... |
stsp/binutils-ia16 | 1,326 | sim/testsuite/sh/fmac.s | # sh testcase for fmac
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fmac_:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * x + y = y.
fldi0 fr0
fldi1 fr1
fldi1 fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fcmp/eq fr0, fr2
bt .L0
fail
.L0:
# x * y + 0.0 = x * y.
fldi1 fr0
fldi1 fr1
... |
stsp/binutils-ia16 | 1,593 | sim/testsuite/sh/ldrc.s | # sh testcase for ldrc, strc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
setrc_imm:
set_grs_a5a5
# Test setrc
#
ldrs lstart
ldre lend
setrc #0xff
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xff, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc... |
stsp/binutils-ia16 | 2,717 | sim/testsuite/sh/movua.s | # sh testcase for movua
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movua_1:
set_grs_a5a5
mov.l srcp, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg... |
stsp/binutils-ia16 | 1,665 | sim/testsuite/sh/fmul.s | # sh testcase for fmul
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
.endm
start
fmul_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * 0.0 = 0.0.
init
fmul fr0, fr0
assert_fpreg_i 0, fr0
# 0.0 * 1.0 = 0.0.
init
fmul fr1, fr0
asse... |
stsp/binutils-ia16 | 2,619 | sim/testsuite/sh/mulr.s | # sh testcase for mulr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
mulr_1: ! multiply by one
set_grs_a5a5
mov #1, r0
mulr r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
... |
stsp/binutils-ia16 | 2,500 | sim/testsuite/sh/pushpop.s | # sh testcase for push/pop (mov,movml,movmu...) insns.
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movml_1:
set_greg 0, r0
set_greg 1, r1
set_greg 2, r2
set_greg 3, r3
set_greg 4, r4
set_greg 5, r5
set_greg 6, r6
set_greg 7, r7
set_greg 8, r8... |
stsp/binutils-ia16 | 2,256 | sim/testsuite/sh/bst.s | # sh testcase for bst
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bst_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bst.b #0, @(3, r1)
assertmem _x, 0x1
bst.b #1, ... |
stsp/binutils-ia16 | 1,142 | sim/testsuite/sh/movi.s | # sh testcase for all mov <#imm> instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
mov_i_reg: # Test <imm8>
set_grs_a5a5
mov #-0x55, r1
assertreg 0xffffffab, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 ... |
stsp/binutils-ia16 | 4,383 | sim/testsuite/sh/pshar.s | # sh testcase for psha <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, x0
set_sreg 0x0, y0
p... |
stsp/binutils-ia16 | 4,699 | sim/testsuite/sh/fmov.s | # sh testcase for all fmov instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fldi1 fr3
.endm
start
fmov1: # Test fr -> fr.
set_grs_a5a5
set_fprs_a5a5
init
single_prec
sz_32
fmov fr0, fr1
# Ensure fr0 and fr1 are now equal.
fcmp/eq ... |
stsp/binutils-ia16 | 1,911 | sim/testsuite/sh/mov.s | # sh testcase for all mov.[bwl] instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.align 2
_lsrc: .long 0x55555555
_wsrc: .long 0x55550000
_bsrc: .long 0x55000000
.align 2
_ldst: .long 0
_wdst: .long 0
_bdst: .long 0
start
movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr
set_grs_a5... |
stsp/binutils-ia16 | 2,169 | sim/testsuite/sh/float.s | # sh testcase for float
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
float_pos:
set_grs_a5a5
set_fprs_a5a5
single_prec
mov #3, r0
lds r0, fpul
float fpul, fr2
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fcmp/eq fr1, fr2
bt float_neg
fail
float_neg: ... |
stsp/binutils-ia16 | 1,896 | sim/testsuite/sh/pshli.s | # sh testcase for pshl <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_imm: ! shift logical, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, a0
pshl #0, a0
asse... |
stsp/binutils-ia16 | 1,647 | sim/testsuite/sh/bxor.s | # sh testcase for bxor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bxor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bxor.b #0, @(3, r1)
bt8k mfail
bxor.b #1, @(3, r1)
bt8k ... |
stsp/binutils-ia16 | 1,643 | sim/testsuite/sh/fcmpgt.s | # sh testcase for fcmpgt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpgt_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L0
fail
.L0:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt .L1
fail
.L1:
# 1.0 > 0.0.
fldi1 fr0
fl... |
stsp/binutils-ia16 | 1,325 | sim/testsuite/sh/and.s | # sh testcase for and
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
and_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
and r1, r2
test_gr0_a5a5
assertreg 0xa5a5a5a5 r1
assertreg 0xa0a0a... |
stsp/binutils-ia16 | 1,619 | sim/testsuite/sh/fcmpeq.s | # sh testcase for fcmpeq
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpeq_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 == 1.0.
fldi1 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# 0.0 != 1.0.
fldi0 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L1
fail
.L1:
# 1.0 != 0.0.
fldi1 fr0
... |
stsp/binutils-ia16 | 1,585 | sim/testsuite/sh/fneg.s | # sh testcase for fneg
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fneg_single:
set_grs_a5a5
set_fprs_a5a5
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr1
fneg fr0
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# neg(1.0) = fsub(0,1)
fldi1 fr0
fneg fr0
fldi0 fr1
fldi1 fr2
fsub fr2, fr1
fcmp/eq f... |
stsp/binutils-ia16 | 1,484 | sim/testsuite/sh/bldnot.s | # sh testcase for bldnot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bldnot_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bldnot.b #0, @(0, r1)
bt8k mfail
bldnot.b #1, @(0, r1)
bf8k mfail
bldn... |
stsp/binutils-ia16 | 1,715 | sim/testsuite/sh/fsqrt.s | # sh testcase for fsqrt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsqrt_single:
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
fsqrt fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# sqrt(1.0) = 1.0.
fldi1 fr0
fsqrt fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1... |
stsp/binutils-ia16 | 2,985 | sim/testsuite/sh/pswap.s | # sh testcase for pswap
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pswapx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
pswap x0, y0
assert_sreg 0x7777a5a5, y0
set... |
stsp/binutils-ia16 | 1,609 | sim/testsuite/sh/fabs.s | # sh testcase for fabs
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fabs_freg_b0:
single_prec
bank0
set_grs_a5a5
set_fprs_a5a5
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
... |
stsp/binutils-ia16 | 2,323 | sim/testsuite/sh/ftrc.s | # sh testcase for ftrc
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
ftrc_single:
set_grs_a5a5
set_fprs_a5a5
# ftrc(0.0) = 0.
fldi0 fr0
ftrc fr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L0
fail
.L0:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr1
fldi1 fr2
# dou... |
stsp/binutils-ia16 | 1,911 | sim/testsuite/sh/fsub.s | # sh testcase for fsub
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsub_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr1
fsub fr0, fr1
fldi1 fr2
fcmp/eq... |
stsp/binutils-ia16 | 1,433 | sim/testsuite/sh/prnd.s | # sh testcase for prnd
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
# FIXME: opcode table ambiguity in ignored bits 4-7.
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
# prnd(0xa5a5a5a5) = 0xa5a60000
prnd ... |
stsp/binutils-ia16 | 1,247 | sim/testsuite/sh/add.s | # sh testcase for add
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 1
_y: .long 1
start
add_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
add r1, r2
test_gr0_a5a5
assertreg 2 r1
assertreg 4 r2
test_gr_a5a5 r3
test_gr_a5a... |
stsp/binutils-ia16 | 2,387 | sim/testsuite/sh/bclr.s | # sh testcase for bclr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xffffffff
_y: .long 0x55555555
start
bclr_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bclr.b #0, @(3, r1)
assertmem _x, 0xfffffffe
bclr.b #1, @(3, r1)
assertmem ... |
stsp/binutils-ia16 | 1,638 | sim/testsuite/sh/bandor.s | # sh testcase for band, bor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
band.b #0, @(3, r1)
bf8k mfail
bor.b #1, @(3, r1)
... |
stsp/binutils-ia16 | 1,805 | sim/testsuite/sh/pinc.s | # sh testcase for pinc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pincx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pinc x0, y0
assert_sreg 0xa5a60000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
... |
stsp/binutils-ia16 | 3,257 | sim/testsuite/sh/div.s | # sh testcase for divs and divu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
divs_1: ! divide by one
set_grs_a5a5
mov #1, r0
divs r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a... |
stsp/binutils-ia16 | 2,568 | sim/testsuite/sh/pshlr.s | # sh testcase for pshl <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, x0
set_sreg 0x0, y... |
stsp/binutils-ia16 | 6,051 | sim/testsuite/sh/loop.s | # sh testcase for loop control
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
loop1:
set_grs_a5a5
ldrs Loop1_start0+8
ldre Loop1_start0+4
setrc #5
Loop1_start0:
add #1, r1 ! Before loop
# Loop should execute one instruction five times.
Loop1_begin:
add #1, r1 ! Within loo... |
stsp/binutils-ia16 | 4,107 | sim/testsuite/sh/resbank.s | # sh testcase for ldbank stbank resbank
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.macro SEND reg bankno regno
set_greg ((\bankno << 7) + (\regno << 2)), \reg
.endm
start
stbank_1:
set_grs_a5a5
mov #0, r0
SEND r1, 0, 0
stbank r0, @r1
mov #1, r0
... |
stsp/binutils-ia16 | 32,830 | sim/testsuite/sh/movxy.s | # sh testcase for movxy
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
src1: .word 1
src2: .word 2
src3: .word 3
src4: .word 4
src5: .word 5
src6: .word 6
src7: .word 7
src8: .word 8
src9: .word 9
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dst1: .word 0... |
stsp/binutils-ia16 | 4,646 | sim/testsuite/sh/pdmsb.s | # sh testcase for pdmsb
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x0, x0
L0: pdmsb x0, x1
# assert_sreg 31<<16, x1
set_sreg 0x1, x0
L1: pdmsb x0, x... |
stsp/binutils-ia16 | 1,740 | sim/testsuite/sh/bandornot.s | # sh testcase for bandnot, bornot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bandnot.b #0, @(3, r1)
bt8k mfail
bornot.b #... |
stsp/binutils-ia16 | 1,318 | sim/testsuite/sh/shll.s | # sh testcase for shll
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll:
set_grs_a5a5
mov #1, r1
shll r1
assertreg 2, r1
shll r1
assertreg 4, r1
shll r1
assertreg 8, r1
shll r1
assertreg 16, r1
shll r1
assertreg 32, r1
shll r1
assertreg... |
stsp/binutils-ia16 | 2,333 | sim/testsuite/sh/fipr.s | # sh testcase for fipr $fvm, $fvn
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
initv0:
set_grs_a5a5
set_fprs_a5a5
# Load 1 into fr0.
fldi1 fr0
# Load 2 into fr1.
fldi1 fr1
fadd fr1, fr1
# Load 4 into fr2.
fldi1 fr2
fadd fr2, fr2
fadd fr2, fr2
# Load 8 into fr3.
fmov fr2, fr3
f... |
stsp/binutils-ia16 | 1,361 | sim/testsuite/sh/clip.s | # sh testcase for clips, clipu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
clips_b:
set_grs_a5a5
clips.b r1
test_gr0_a5a5
assertreg 0xffffff80 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r... |
stsp/binutils-ia16 | 3,329 | sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp
// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1)
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4, 0xa00a1089;
imm32 p5, 0x... |
stsp/binutils-ia16 | 6,520 | sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s | //Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp
// Spec Reference: c_dspldst ld_drlo_i++/--
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.... |
stsp/binutils-ia16 | 5,720 | sim/testsuite/bfin/c_mmr_timer.S | //Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp
// Spec Reference: mmr timer
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
... |
stsp/binutils-ia16 | 6,093 | sim/testsuite/bfin/c_dsp32mac_pair_a1_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_u/c_dsp32mac_pair_a1_u.dsp
// Spec Reference: dsp32mac pair a1 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
... |
stsp/binutils-ia16 | 3,994 | sim/testsuite/bfin/c_pushpopmultiple_dp.s | //Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp
// Spec Reference: pushpopmultiple dreg preg single group
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08... |
stsp/binutils-ia16 | 5,857 | sim/testsuite/bfin/c_dsp32alu_rh_rnd20_p.s | //Original:/testcases/core/c_dsp32alu_rh_rnd20_p/c_dsp32alu_rh_rnd20_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm3... |
stsp/binutils-ia16 | 6,086 | sim/testsuite/bfin/c_mmr_ppop_illegal_adr.S | //Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp
// Spec Reference: mmr ppop illegal address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STA... |
stsp/binutils-ia16 | 3,544 | sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s | //Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp
// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679... |
stsp/binutils-ia16 | 2,920 | sim/testsuite/bfin/c_loopsetup_nested.s | //Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp
// Spec Reference: loopsetup nested inside
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = ... |
stsp/binutils-ia16 | 2,875 | sim/testsuite/bfin/c_dsp32mac_dr_a0_ih.s | //Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp
// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfe... |
stsp/binutils-ia16 | 5,429 | sim/testsuite/bfin/c_dsp32alu_rmm.s | //Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp
// Spec Reference: dsp32alu dreg = -/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm... |
stsp/binutils-ia16 | 4,478 | sim/testsuite/bfin/c_dsp32shift_signbits_r.s | //Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp
// Spec Reference: dsp32shift signbits dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x88880000;
imm32 r1, 0x34560001;
imm32 r2, 0x08000002;
imm32 r3, 0x08000003;
imm32 r4, 0x08000004;
imm32 r5, 0x08000005;
imm32 r6, 0x0... |
stsp/binutils-ia16 | 7,121 | sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen... |
stsp/binutils-ia16 | 1,476 | sim/testsuite/bfin/hwloop-bits.S | # Blackfin testcase for HW Loops and user->super transitions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
.macro check_hwloop_regs lc:req, lt:req, lb:req
R0 = LC0;
CC = R0 == \lc;
IF !CC JUMP fail;
R0 = LT0;
CC = R0 == \lt;
IF !CC JUMP fail;
R0 = LB0;
CC = R0 == \... |
stsp/binutils-ia16 | 1,417 | sim/testsuite/bfin/m15.s | // Test extraction from accumulators:
// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0ffffff0
// load r1=0x7ffffff0
// load r2=0x0fffffff
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ... |
stsp/binutils-ia16 | 8,907 | sim/testsuite/bfin/se_cc_kill.S | //Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp
// Description:
// Verify CC kill under the following condition:
//
// (1) CC = AZ killed in WB
// (2) CC = AN killed in WB
// (3) CC = AC killed in WB
// (4) CC = AV0 killed in WB
// (5) CC = AV1 killed in WB
... |
stsp/binutils-ia16 | 9,385 | sim/testsuite/bfin/se_cof.S | //Original:/proj/frio/dv/testcases/seq/se_cof/se_cof.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
////////////... |
stsp/binutils-ia16 | 2,651 | sim/testsuite/bfin/c_ccflag_a0a1.S | //Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp
// Spec Reference: ccflag a0-a1 (==, <, <=)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x12345778;
imm32 r1, 0x12345678;
imm32 r2, 0x056789ab;
imm32 r3, 0x80231345;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x... |
stsp/binutils-ia16 | 17,730 | sim/testsuite/bfin/se_loop_kill_dcr_01.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
stsp/binutils-ia16 | 6,378 | sim/testsuite/bfin/c_interr_disable.S | //Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
... |
stsp/binutils-ia16 | 10,526 | sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0... |
stsp/binutils-ia16 | 7,027 | sim/testsuite/bfin/c_ldst_ld_p_p_mm.s | //Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp
// Spec Reference: c_ldst ld p [p--]
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
load... |
stsp/binutils-ia16 | 2,415 | sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp
// Spec Reference: compi2opp pregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
R0 = -0;
P1 = -1;
P2 = -2;
P3 = -3;
P4 = -4;
P5 = -5;
SP = -6;
FP = -7;
CHECKREG r0, -0;
CHECKREG p1, -1;
CHECKREG p2, ... |
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