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github-python-corpus

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class MoveNot(Arm64Instruction):
''' MVN - move not
'''
opcodes = ['mvn']
imm_width = 64
def emit_riscv(self):
if self.operand_types[1] == 'immediate':
op = 'li'
elif self.operand_types[1] == 'label':
op = 'la'
else:
op = 'mv'
dest, src = self.get_args()
self.riscv_instructions = [
f'{op} {dest}, {src}',
f'not {dest}, {dest}'
]
class MoveWideWithKeep(Arm64Instruction):
''' MOVK --> A relatively complex sequence of operations
Arm64 docs:
"Move wide with keep moves an optionally-shifted 16-bit immediate value into a register, keeping other bits unchanged."
(https://developer.arm.com/docs/ddi0596/e/base-instructions-alphabetic-order/movk-move-wide-with-keep)
There's no such primitive instruction in RISC-V, so we're gonna put it together here.
Broadly, we'll:
(1) Clear the bits we're going to load into in the destination (ANDing a mask)
(2) Move the bits to the parallel area
(3) or them together
Yay Turing Machines!
'''
opcodes = ['movk']
imm_width = 64 # we will handle our own immediates here
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.required_temp_regs = ['temp', 'shift_temp']
self.shift = False
if len(self.operands) > 2: # Not just a movk, but shifted
self.shift = True
# Operands are e.g. movk x0, 0x41df, lsl 48
# We never need to pull the shift, since it can only be LSL
self.shamt = self.operands[3]['immediate']
def emit_riscv(self):
temp, shift_temp = self.required_temp_regs
dest = self.specific_regs[0]
imm = self.operands[1]['immediate']
self.riscv_instructions = [
f'not {temp}, x0 # set reg to all ones',
f"srli {temp}, {temp}, 48 # this clears the upper 48 bits in the mask. We'll invert it to get the final mask",
f"li {shift_temp}, {imm} # load our immediate value"
]
if self.shift:
self.riscv_instructions += [
f'slli {shift_temp}, {shift_temp}, {self.shamt} # move the immediate to the parallel place',
f'slli {temp}, {temp}, {self.shamt} # move the mask to the parallel place'
]
self.riscv_instructions += [
f'not {temp}, {temp} # flip the mask to AND against',
f'and {dest}, {dest}, {temp} # clear the target bits in mask',
f'or {dest}, {dest}, {shift_temp} # or in the bits from the immediate to load'
]
class LoadStorePair(Arm64Instruction):
"""Load and Store pair have almost identical behavior.
Most of the weird stuff is just accounting for writeback.
"""
opcodes = ['ldp', 'stp']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.num_reg_writes = 0 if opcode == 'stp' else 2
# Becomes either lw or ld, depending on reg width
addon = 'w' if self.wflag else 'd'
self.base_op = self.opcode[0] + addon
if len(operands) == 4:
post_index = True
self.final_offset = operands[3]['immediate']
elif self.operands[2]['writeback']:
pre_index = True
self.final_offset = self.offset
else: # Signed Offset
self.final_offset = None
def emit_riscv(self):
r1, r2, sp = self.specific_regs
self.riscv_instructions = [
f'{self.base_op} {r1}, {self.offset}({sp})',
f'{self.base_op} {r2}, {self.offset + 8}({sp})'
]