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if self.final_offset:
self.riscv_instructions.append(
f'addi {sp}, {sp}, {self.final_offset} # writeback'
)
class Return(Arm64Instruction):
"""Convert Return - trivial conversion
"""
opcodes = ['ret']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.riscv_instructions = ['ret']
class MultiplyDivide (Arm64Instruction):
"""Combining multiply and divide since should be the same
converting mul, udiv or sdiv: simple 1:1
"""
opcodes = ['mul', 'udiv', 'sdiv']
map_op = {
'mul': 'mul',
'udiv': 'divu',
'sdiv': 'div',
}
# TODO: check type safety!
def emit_riscv(self):
op = self.map_op[self.opcode]
xd, xa, xb = self.specific_regs
self.riscv_instructions = [
f'{op}{self.wflag} {xd}, {xa}, {xb}'
]
class Negate(Arm64Instruction):
""" Converts negate
TODO: Do we need a word level op?
"""
opcodes = ['neg']
def emit_riscv(self):
dest, source = self.specific_regs
self.riscv_instructions = [
f'sub {dest}, x0, {source}'
]
class Subtract(Arm64Instruction):
"""Handle Subtract
Along with updating flags if it's `subs`
If possible, switches a sub with immediate to addi with flipped sign.
"""
opcodes = ['sub', 'subs']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.op = 'sub'
if self.is_safe_imm(self.operands[2]):
self.op = 'addi'
self.immediate_value = -self.operands[2]['immediate']
self.op += self.wflag
if self.opcode == 'subs':
self.specific_regs.append(COMPARE)
def emit_riscv(self):
super().emit_riscv()
dest, s1, s2 = self.get_args()
if self.immediate_value:
s2 = self.immediate_value
self.riscv_instructions += [
f'{self.op} {dest}, {s1}, {s2}'
]
if self.opcode == 'subs':
cond = self.specific_regs[-1]
self.riscv_instructions.append(
f'mv {cond}, {dest} # simulating updating flags'
)
class Branch(Arm64Instruction):
""" Branch is jump, nothing else to it """
opcodes = ['b']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
target = operands[0]['label']
self.riscv_instructions = [
f'j {target}'
]
class Shifts(Arm64Instruction):