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""" convert shifts to corresponding name in RISC-V
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"""
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opcodes = ['lsl', 'lsr', 'asr']
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opmap = {
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'lsl': 'sll',
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'lsr': 'srl',
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'asr': 'sra',
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}
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def emit_riscv(self):
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dest, s1, s2 = self.get_args()
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self.riscv_instructions = [
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f'{self.opmap[self.opcode]}{self.iflag}{self.wflag} {dest}, {s1}, {s2}'
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]
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"""
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RISC-V Load Types
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LB rd,offset(rs1) Load Byte rd ← s8[rs1 + offset]
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LH rd,offset(rs1) Load Half rd ← s16[rs1 + offset]
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LW rd,offset(rs1) Load Word rd ← s32[rs1 + offset]
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LBU rd,offset(rs1) Load Byte Unsigned rd ← u8[rs1 + offset]
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LHU rd,offset(rs1) Load Half Unsigned rd ← u16[rs1 + offset]
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LWU rd,offset(rs1) Load Word Unsigned rd ← u32[rs1 + offset]
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LD rd,offset(rs1) Load Double rd ← u64[rs1 + offset]
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RISC-V stores
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SB rs2,offset(rs1) Store Byte u8[rs1 + offset] ← rs2
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SH rs2,offset(rs1) Store Half u16[rs1 + offset] ← rs2
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SW rs2,offset(rs1) Store Word u32[rs1 + offset] ← rs2
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SD rs2,offset(rs1) Store Double u64[rs1 + offset] ← rs2
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"""
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class LoadStoreRegister(Arm64Instruction):
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"""The behavior here is roughly equivalent for L/S.
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Load and Store are mixed together because the SP behavior (the complicated part here) is basically identical.
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"""
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opcodes = ['ldr', 'ldrb', 'ldrsw', 'ldrsh', 'str', 'strh', 'strb']
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opmap = {
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'ldrb': 'lb',
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'ldrsh': 'lh',
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'ldrsw': 'lw',
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'ldr': 'ld',
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'str': 'sd',
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'strh': 'sh',
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'strb': 'sb'
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}
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def __init__(self, opcode, operands):
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super().__init__(opcode, operands)
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if self.opcode[0] == 's':
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self.num_reg_writes = 0
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r1, sp = operands[:2]
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self.base_op = self.opmap[self.opcode]
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if self.opcode not in ('ldr', 'str'):
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pass
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elif r1['type'] == 'fp':
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self.base_op = 'f' + self.opcode[0] + get_fl_flag(r1)
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self.float_st = True
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elif self.wflag:
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self.base_op = self.opcode[0] + 'w'
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self.reg_offset = False
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if len(operands) == 3:
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post_index = True
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self.final_offset = operands[2]['immediate']
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elif sp['writeback']:
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pre_index = True
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self.final_offset = self.offset
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else: # Signed Offset
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self.final_offset = None
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if sp.get('original_mode'):
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if 'got' in sp['original_mode']: # GOT -- relocation
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self.base_op = 'add' # this is weird but that's what the Arm docs say 🤷🏻♂️
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self.offset = sp['offset']
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def emit_riscv(self):
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super().emit_riscv()
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dest, sp, *reg_offset = self.specific_regs
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if self.base_op == 'add':
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self.riscv_instructions.append(
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f'{self.base_op} {dest}, {sp}, {self.offset} # load from GOT -> ADD!'
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)
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return
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load_src = sp
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if self.set_offset_reg:
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load_src = self.required_temp_regs[0]
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self.riscv_instructions.append(
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f'{self.base_op} {dest}, {self.offset}({load_src})'
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)
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if self.final_offset:
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