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jblitzar
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github-python-corpus

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def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.cc = operands[1]['label'].lower()
self.specific_regs.append(COMPARE)
def emit_riscv(self):
dest, cmp = self.specific_regs
self.riscv_instructions = [
f'li {dest}, 1',
f'b{self.cc} {cmp}, x0, 999999f', # f -- only forward.
f'mv {dest}, x0',
f'999999:',
f'nop' # nothing further needed, we just need to conditionally skip setting to 0
]
class BitwiseOperations(Arm64Instruction):
""" Convert Bitwise operations (same pattern)
"""
opcodes = ['eor', 'orr', 'and']
opmap = {
'eor': 'xor',
'orr': 'or',
'and': 'and',
}
def emit_riscv(self):
dest, s1, s2 = self.get_args()
self.riscv_instructions += [
f'{self.opmap[self.opcode]}{self.iflag} {dest}, {s1}, {s2}'
]
class Nop(Arm64Instruction):
""" This is pretty self-explanatory
"""
opcodes = ['nop']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.riscv_instructions = ['nop']
# Floating Point Instructions
class FloatingPointMove(Arm64Instruction):
opcodes = ['fmov']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
if self.fp_wflag:
self.op = f'fmv.{self.fp_wflag}.x'
else:
self.op = f'fmv.x.{get_fl_flag(operands[1])}'
def emit_riscv(self):
dest, src = self.get_args()
self.riscv_instructions += [
f'{self.op} {dest}, {src}'
]
class FloatingPointConvert(Arm64Instruction):
''' Things like UCVTF, SCVTF -- converting from fixed point or integer
'''
opcodes = ['ucvtf', 'scvtf']
def emit_riscv(self):
unsigned = 'u' if self.opcode == 'ucvtf' else ''
float_dest, integer_src = self.specific_regs
wl = 'w' if is_half_width(self.operands[1]) else 'l'
self.riscv_instructions = [
f'fcvt.d.{wl}{unsigned} {float_dest}, {integer_src}'
]
class FloatingPointCompare(Arm64Instruction):
''' Floating point compare
Requires a couple tricks to synthesize the compare result as an int.
'''
opcodes = ['fcmpe', 'fcmp']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.specific_regs.append(COMPARE)
self.required_temp_regs = ['temp'] # we need the temp to get the two results in
def emit_riscv(self):
arg1, arg2, compare = self.specific_regs
temp = self.required_temp_regs[0]
self.riscv_instructions = [
f'flt.d {compare}, {arg1}, {arg2} # this is less than, RHS is bigger',
f'slli {compare}, {compare}, 63 # move it to the sign bit location',
f'flt.d {temp}, {arg2}, {arg1} # if LHS is bigger',
f'or {compare}, {compare}, {temp} # or the results together',
]