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jblitzar
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github-python-corpus

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class FloatingPointSimplex(Arm64Instruction):
"""for the simple FP args -- 1:1
"""
opcodes = ['fadd', 'fsub', 'fdiv', 'fmul', 'fmax', 'fmin']
def emit_riscv(self):
dst, s1, s2 = self.specific_regs
self.riscv_instructions = [
f'{self.opcode}.{self.fp_wflag} {dst}, {s1}, {s2}'
]
class FloatingPointSingleArg(Arm64Instruction):
opcodes = ['fneg', 'fsqrt']
def emit_riscv(self):
dst, s1 = self.specific_regs
self.riscv_instructions = [
f'{self.opcode}.{self.fp_wflag} {dst}, {s1}'
]
class FloatingPointFused(Arm64Instruction):
opcodes = ['fmadd', 'fmsub', 'fnmadd', 'fnmsub']
opmap = {
'fmadd': 'fmadd',
'fnmadd': 'fnmadd',
'fmsub': 'fnmsub', # not sure why but fmsub and fnmsub are swapped in the syntax
'fnmsub': 'fmsub',
}
def emit_riscv(self):
dst, s1, s2, s3 = self.specific_regs
self.riscv_instructions = [
f'{self.opmap[self.opcode]}.{self.fp_wflag} {dst}, {s1}, {s2}, {s3}'
]
class AtomicLoadExclusive(Arm64Instruction):
''' LDAXR has a direct parallel -- LR = 'load-reserved' in RISC-V.
This is an atomic.
'''
opcodes = ['ldaxr']
def emit_riscv(self):
dst, src = self.specific_regs
size = 'w' if self.wflag else 'd'
self.riscv_instructions = [
f'lr.{size} {dst}, {self.offset}({src})'
]
class AtomicStoreExclusive(Arm64Instruction):
''' Atomic store ops - direct 1:1
'''
opcodes = ['stlxr']
def emit_riscv(self):
dst, desired, addr = self.specific_regs
size = 'w' if self.wflag else 'd'
self.riscv_instructions = [
f'sc.{size} {dst}, {desired}, {self.offset}({addr})'
]
class LoadAcquireFence(Arm64Instruction):
''' LDAR is has an implicit fence semantic. We make it explicit here.
'''
opcodes = ['ldar']
def emit_riscv(self):
dst, src = self.specific_regs
size = 'w' if self.wflag else 'd'
self.riscv_instructions = [
f'l{size} {dst}, {self.offset}({src})',
f'fence iorw,iorw # making implicit fence semantics explicit',
]
class StoreReleaseFence(Arm64Instruction):
''' Atomic store ops - direct 1:1
'''
opcodes = ['stlr']
def emit_riscv(self):
desired, addr = self.specific_regs
size = 'w' if self.wflag else 'd'
self.riscv_instructions = [
f'fence iorw,iorw # making implicit fence semantics explicit',
f's{size} {desired}, {self.offset}({addr})'
]
class AtomicOperations(Arm64Instruction):
''' Grouping together Arm64 Atomics, e.g. LDADD, CAS, etc.
Translation is one to one op, with acquire-release semantics as well.
'''
opcodes = ['swp', 'ldadd', 'ldeor', 'ldset', 'ldsmin', 'ldsmax', 'ldumin', 'ldumax'] +\