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github-python-corpus

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self.riscv_instructions.append(
f'add {self.required_temp_regs[-1]}, {x}, {y} # converting offset register to add'
)
class UnsignedMultiplyAddLong(Arm64Instruction):
"""converting umaddl: one arm instruction into two riscv instructions using one temp register
"""
opcodes = ['umaddl']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.required_temp_regs = ['temp']
def emit_riscv(self):
temp = self.required_temp_regs[0]
xd, wm, wn, xa = self.specific_regs
self.riscv_instructions = [
f'mulw {temp}, {wm}, {wn}',
f'add {xd}, {xa}, {temp}'
]
class SignExtendWord(Arm64Instruction):
""" Convert sign extension
"""
opcodes = ['sxtw']
def emit_riscv(self):
xd, wn = self.specific_regs
self.riscv_instructions = [
f'sext.w {xd}, {wn}'
]
class BranchAndLink(Arm64Instruction):
"""BL is completely equivalent to a 'call'
"""
opcodes = ['bl']
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
label = operands[0]['label']
self.riscv_instructions = [
f'call {label}'
]
class Add(Arm64Instruction):
"""Converts Add
Adjusts for immediate and width
"""
opcodes = ['add']
def emit_riscv(self):
super().emit_riscv()
dest, s1, s2 = self.get_args()
self.riscv_instructions += [
f'add{self.iflag}{self.wflag} {dest}, {s1}, {s2}'
]
class AddressPCRelative(Arm64Instruction):
"""ADRP works like LUI in practice, at least w/ GCC
"""
opcodes = ['adrp']
imm_width = 20
def __init__(self, opcode, operands):
super().__init__(opcode, operands)
self.label = operands[1]['label']
if 'is_load' not in operands[1].keys():
self.label = f'%hi({self.label})'
def emit_riscv(self):
dest = self.specific_regs[0]
self.riscv_instructions = [
f'lui {dest}, {self.label}'
]
class Move(Arm64Instruction):
"""Rewritten Move -- using simplified constructor
Operation is li, la, or mv depending on argument type
"""
opcodes = ['mov']
imm_width = 64
def emit_riscv(self):
if self.operand_types[1] == 'immediate':
op = 'li'
elif self.operand_types[1] == 'label':
op = 'la'
else:
op = 'mv'
dest, src = self.get_args()
self.riscv_instructions = [
f'{op} {dest}, {src}'