code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module and31 (
a1,
a2,
a3,
z
);
input a1;
input a2;
input a3;
output z;
wire z;
assign z = a1 & a2 & a3;
endmodule
| 7.970924 |
module and32 (
input [31:0] A,
input [31:0] B,
output [31:0] res
);
assign res = A & B; //32λ
endmodule
| 7.599517 |
module And32b (
leftOperand,
rightOperand,
result
);
input wire [31:0] leftOperand;
input wire [31:0] rightOperand;
output wire [31:0] result;
assign result[0] = leftOperand[0] & rightOperand[0];
assign result[1] = leftOperand[1] & rightOperand[1];
assign result[2] = leftOperand[2] & rightOperand[2];
assign result[3] = leftOperand[3] & rightOperand[3];
assign result[4] = leftOperand[4] & rightOperand[4];
assign result[5] = leftOperand[5] & rightOperand[5];
assign result[6] = leftOperand[6] & rightOperand[6];
assign result[7] = leftOperand[7] & rightOperand[7];
assign result[8] = leftOperand[8] & rightOperand[8];
assign result[9] = leftOperand[9] & rightOperand[9];
assign result[10] = leftOperand[10] & rightOperand[10];
assign result[11] = leftOperand[11] & rightOperand[11];
assign result[12] = leftOperand[12] & rightOperand[12];
assign result[13] = leftOperand[13] & rightOperand[13];
assign result[14] = leftOperand[14] & rightOperand[14];
assign result[15] = leftOperand[15] & rightOperand[15];
assign result[16] = leftOperand[16] & rightOperand[16];
assign result[17] = leftOperand[17] & rightOperand[17];
assign result[18] = leftOperand[18] & rightOperand[18];
assign result[19] = leftOperand[19] & rightOperand[19];
assign result[20] = leftOperand[20] & rightOperand[20];
assign result[21] = leftOperand[21] & rightOperand[21];
assign result[22] = leftOperand[22] & rightOperand[22];
assign result[23] = leftOperand[23] & rightOperand[23];
assign result[24] = leftOperand[24] & rightOperand[24];
assign result[25] = leftOperand[25] & rightOperand[25];
assign result[26] = leftOperand[26] & rightOperand[26];
assign result[27] = leftOperand[27] & rightOperand[27];
assign result[28] = leftOperand[28] & rightOperand[28];
assign result[29] = leftOperand[29] & rightOperand[29];
assign result[30] = leftOperand[30] & rightOperand[30];
assign result[31] = leftOperand[31] & rightOperand[31];
endmodule
| 7.833017 |
module And32b (
input [31:0] A,
B,
output [31:0] And
);
assign And = A & B;
endmodule
| 7.833017 |
module AND3B1 (
O,
I0,
I1,
I2
);
output O;
input I0, I1, I2;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1, I2);
endmodule
| 6.919382 |
module AND3B2 (
O,
I0,
I1,
I2
);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, I2);
endmodule
| 7.110075 |
module AND3B3 (
O,
I0,
I1,
I2
);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv);
endmodule
| 7.334747 |
module testandgate;
reg a, b, c;
wire s;
andgate ANDGATE1 (
s,
a,
b,
c
);
initial begin : start
a = 0;
b = 0;
c = 0;
end
initial begin
$display("Bernardo MP Olimpio - 451542");
$display("Test AND 3 entradas");
a = 0;
b = 0;
$monitor("%b & %b & %b = %b", a, b, c, s);
#1 a = 0;
b = 0;
c = 0;
#1 a = 0;
b = 0;
c = 1;
#1 a = 0;
b = 1;
c = 0;
#1 a = 0;
b = 1;
c = 1;
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0;
c = 1;
#1 a = 1;
b = 1;
c = 0;
#1 a = 1;
b = 1;
c = 1;
end
endmodule
| 6.553783 |
module andG2 (
output s,
input x,
input y
);
assign s = x & y;
endmodule
| 8.053772 |
module andG3 (
output s,
input p,
input q,
input r
);
wire s1;
andG2 AND1 (
s1,
p,
q
);
andG2 AND2 (
s,
r,
s1
);
endmodule
| 7.737659 |
module And3 (
input [2:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8080)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.30935 |
module And3x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And3 inst0 (
.I({I2[0], I1[0], I0[0]}),
.O(inst0_O)
);
And3 inst1 (
.I({I2[1], I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.983586 |
module main (
input [5:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And3x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.I2({J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And3 (
input [2:0] I,
output O
);
wire inst0_O;
LUT3 #(
.INIT(8'h80)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.30935 |
module And3x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And3 inst0 (
.I({I2[0], I1[0], I0[0]}),
.O(inst0_O)
);
And3 inst1 (
.I({I2[1], I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.983586 |
module main (
input [5:0] SWITCH,
output [1:0] LED
);
wire [1:0] inst0_O;
And3x2 inst0 (
.I0({SWITCH[1], SWITCH[0]}),
.I1({SWITCH[3], SWITCH[2]}),
.I2({SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module And3 (
input [2:0] I,
output O
);
wire inst0_O;
LUT3 #(
.INIT(8'h80)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.30935 |
module And3x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And3 inst0 (
.I({I2[0], I1[0], I0[0]}),
.O(inst0_O)
);
And3 inst1 (
.I({I2[1], I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.983586 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And2x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module AND3_core (
Data,
Result
);
input [2:0] Data;
output Result;
AND3 Start (
.A(Data[0]),
.B(Data[1]),
.C(Data[2]),
.Y(Result)
);
endmodule
| 6.624038 |
module AND_3_GATE (
input A_t, //true data in #1
input A_f,
input B_t, //true data in #2
input B_f,
input C_t, //true data in #3
input C_f,
output O_t, //true data out
output O_f
);
wire tmp_OT, tmp_OF;
AND_GATE a0 (
.A_t(A_t),
.A_f(A_f),
.B_t(B_t),
.B_f(B_f), //true data in #1
.O_t(tmp_OT), //true data out
.O_f(tmp_OF) //false data out
);
AND_GATE a1 (
.A_t(tmp_OT),
.A_f(tmp_OF),
.B_t(C_t),
.B_f(C_f), //true data in #1
.O_t(O_t), //true data out
.O_f(O_f) //false data out
);
endmodule
| 6.718908 |
module AND4 (
O,
I0,
I1,
I2,
I3
);
output O;
input I0, I1, I2, I3;
and A1 (O, I0, I1, I2, I3);
endmodule
| 7.008074 |
module and41 (
a1,
a2,
a3,
z,
a4
);
input a1;
input a2;
input a3;
input a4;
output z;
wire z;
assign z = a1 & a2 & a3 & a4;
endmodule
| 8.341527 |
module AND4B1 (
O,
I0,
I1,
I2,
I3
);
output O;
input I0, I1, I2, I3;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1, I2, I3);
endmodule
| 7.417533 |
module AND4B2 (
O,
I0,
I1,
I2,
I3
);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, I2, I3);
endmodule
| 7.411181 |
module AND4B3 (
O,
I0,
I1,
I2,
I3
);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, I3);
endmodule
| 7.592573 |
module AND4B4 (
O,
I0,
I1,
I2,
I3
);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv);
endmodule
| 7.571178 |
module And4 (
input [3:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8000)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.444531 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And4 inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(inst0_O)
);
And4 inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.971612 |
module main (
input [7:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And4x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.I2({J1[5], J1[4]}),
.I3({J1[7], J1[6]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h8000)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.444531 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And4 inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(inst0_O)
);
And4 inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.971612 |
module main (
input [7:0] SWITCH,
output [1:0] LED
);
wire [1:0] inst0_O;
And4x2 inst0 (
.I0({SWITCH[1], SWITCH[0]}),
.I1({SWITCH[3], SWITCH[2]}),
.I2({SWITCH[5], SWITCH[4]}),
.I3({SWITCH[7], SWITCH[6]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module And4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h8000)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.444531 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And4 inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(inst0_O)
);
And4 inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.971612 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And2x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module and4_f (
I1,
I2,
X
); // and gate for the final circuit
input [3:0] I1, I2;
output [4:0] X;
wire [3:0] Z1;
assign Z2 = 1'b0; // calling structures of 4 bit and gate and the concatenation buffer
pvs_and M1 (
.I1(I1),
.I2(I2),
.O (Z1)
);
buf145 M2 (
.C(Z2),
.I(Z1),
.O(X)
);
endmodule
| 6.613562 |
module AND5 (
O,
I0,
I1,
I2,
I3,
I4
);
output O;
input I0, I1, I2, I3, I4;
and A1 (O, I0, I1, I2, I3, I4);
endmodule
| 6.66086 |
module AND5B1 (
O,
I0,
I1,
I2,
I3,
I4
);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1, I2, I3, I4);
endmodule
| 7.077018 |
module AND5B2 (
O,
I0,
I1,
I2,
I3,
I4
);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, I2, I3, I4);
endmodule
| 7.31657 |
module AND5B3 (
O,
I0,
I1,
I2,
I3,
I4
);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, I3, I4);
endmodule
| 7.156273 |
module AND5B4 (
O,
I0,
I1,
I2,
I3,
I4
);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4);
endmodule
| 7.313956 |
module AND5B5 (
O,
I0,
I1,
I2,
I3,
I4
);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
wire i4_inv;
not N4 (i4_inv, I4);
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv);
endmodule
| 7.160558 |
module ANDer (
A,
B
);
input [3:0] A, B;
output C;
assign C = A & B;
endmodule
| 7.289839 |
module andGate (
a,
b,
y
);
input [7:0] a;
input [7:0] b;
output [7:0] y;
reg [7:0] y;
always @(a or b) begin
y = a & b;
end
endmodule
| 9.12182 |
module AndGateModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire I1,
input wire I2,
output wire O
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire Inputs_I1;
wire Inputs_I2;
wire AndGateModule_L7F26T48_Expr;
wire AndGateModule_L7F26T48_Expr_1;
wire AndGateModule_L7F26T48_Expr_2;
assign AndGateModule_L7F26T48_Expr = AndGateModule_L7F26T48_Expr_1 & AndGateModule_L7F26T48_Expr_2;
assign AndGateModule_L7F26T48_Expr_1 = Inputs_I1;
assign AndGateModule_L7F26T48_Expr_2 = Inputs_I2;
assign Inputs_I1 = I1;
assign Inputs_I2 = I2;
assign O = AndGateModule_L7F26T48_Expr;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.241037 |
module: andgate_u_mux
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module andgate_u_muxtb;
// Inputs
reg i0;
reg i1;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
andgate_u_mux uut (
.i0(i0),
.i1(i1),
.y(y)
);
initial begin
$monitor ($time ," i0=%b i1=%b y=%b ",i0,i1,y);
end
initial begin
i0=0;i1=0;
#100;i0=0;i1=1;
#100;i0=1;i1=0;
#100;i0=1;i1=1;
end
endmodule
| 6.581016 |
module notgate (
output s,
input p
);
assign s = ~p;
endmodule
| 7.575943 |
module andgate;
reg a, b, c;
wire s0, s1, n1, n2, n3;
notgate NOT1 (
n1,
a
);
notgate NOT2 (
n2,
b
);
notgate NOT3 (
n3,
c
);
orgate OR1 (
s1,
n1,
n2,
n3
);
notgate NOT4 (
s0,
s1
);
initial begin : start
a = 0;
b = 0;
c = 0;
end
initial begin
$display("ANDGATE 3 entradas por De Morgan - Rama Alvim Sales Schiavo - 305056");
$display("\n ~(~a | ~b | ~c ) = s\n");
$monitor("%b | %b | %b = %b", a, b, c, s0);
#1 a = 0;
b = 0;
c = 0;
#1 a = 0;
b = 0;
c = 1;
#1 a = 0;
b = 1;
c = 0;
#1 a = 0;
b = 1;
c = 1;
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0;
c = 1;
#1 a = 1;
b = 1;
c = 0;
#1 a = 1;
b = 1;
c = 1;
end
endmodule
| 7.412109 |
modules larger than 4 inputs
module and5$(output out,
input in0,
input in1,
input in2,
input in3,
input in4);
wire AND0, AND1, AND_OUT;
and3$ g_and0(.in0(in0), .in1(in1), .in2(in2), .out(AND0));
and2$ g_and1(.in0(in3), .in1(in4), .out(AND1));
and2$ g_and_out(.in0(AND0), .in1(AND1), .out(out));
endmodule
| 7.148318 |
module ANDN(in0, in1, out);
parameter WIDTH = 32;
input [WIDTH-1:0] in0;
input [WIDTH-1:0] in1;
output [WIDTH-1:0] out;
genvar i;
generate
for(i = 0; i < WIDTH; i = i+1) begin : andn_and_block
and2$ instance(.out(out[i]), .in0(in0[i]), .in1(in1[i]));
end
endgenerate
endmodule
| 7.643059 |
module nor16bit (
input [15:0] A,
B,
output [15:0] out
);
assign out = ~(A | B);
endmodule
| 8.552193 |
module and16bit_tb ();
reg [15:0] A;
reg [15:0] B;
reg [15:0] out;
wire [15:0] OUT;
real i;
initial begin
$display("Simulation of 16 Bit AND");
end
and16bit DUT (
.A (A),
.B (B),
.out(OUT)
);
initial begin
A = 0;
B = 0;
end
always @(A, B) begin
for (i = 0; i < 1000; i = i + 1) begin
#1 A = $random;
B = $random;
assign out = A & B;
#1
//$monitor("%d ns: A + B + cin = %b + %b + %b = cout sum = %b %b", $time, A, B, cin, cout, S);
if (OUT !== out) begin
$display("ERROR");
$display("A = %b", A);
$display("B = %b", B);
$display("out = %b", out);
$display("OUT = %b", OUT);
//$monitor("%d ns: A + B + cin = %b + %b + %b = cout sum = %b %d", $time, A, B, cin, cout, S);
end
end
#10 $stop;
end
endmodule
| 6.69379 |
module AndOp (
a,
b,
AndOut
);
input a, b;
output reg AndOut;
always @(a, b) begin
AndOut <= a & b;
end
endmodule
| 6.971573 |
module represents simple combinational logic including
// and AND and an OR expression.
// ===========================================================
module AndOr(output X, Y, input A, B, C);
//
assign #10 X = A & B;
assign #10 Y = B | C;
//
endmodule
| 6.503042 |
module AndOr (
AandB,
AorB,
A,
B
);
output [1:0] AandB, AorB;
input [1:0] A, B;
and myAnd[1:0] (AandB[1:0], A[1:0], B[1:0]);
or myOr[1:0] (AorB[1:0], A[1:0], B[1:0]);
endmodule
| 7.227608 |
module andorTop0;
// connect the two modules
wire [1:0] X, Y;
wire [1:0] XandY, XorY;
// declare an instance of the AND module
AndOr myAndOr (
XandY[1:0],
XorY[1:0],
X[1:0],
Y[1:0]
);
// declare an instance of the testIt module
Tester aTester (
X[1:0],
Y[1:0],
XandY[1:0],
XorY[1:0]
);
// file for gtkwave
initial begin
$dumpfile("andor0.vcd");
$dumpvars(1, myAndOr);
end
endmodule
| 7.084151 |
module andgate_tb;
wire t_y;
reg t_a, t_b;
andgate my_gate (
.a(t_a),
.b(t_b),
.y(t_y)
);
initial begin
$monitor("%b AND %b:%b", t_a, t_b, t_y);
t_a = 1'b0;
t_b = 1'b0;
#5 t_a = 1'b0;
t_b = 1'b1;
#5 t_a = 1'b1;
t_b = 1'b0;
#5 t_a = 1'b1;
t_b = 1'b1;
end
endmodule
| 6.52824 |
module and_ (
out,
a,
b
);
input a, b;
output out;
assign out = a & b;
endmodule
| 7.136729 |
module and_16 (
input [15:0] in1,
input in2,
output [15:0] and_out
);
and_4 a0 (
in1[3:0],
in2,
and_out[3:0]
);
and_4 a1 (
in1[7:4],
in2,
and_out[7:4]
);
and_4 a2 (
in1[11:8],
in2,
and_out[11:8]
);
and_4 a3 (
in1[15:12],
in2,
and_out[15:12]
);
endmodule
| 6.716311 |
module AND_16BIT (
out,
in0,
in1
);
input [15:0] in0, in1;
output [15:0] out;
AND and0[15:0] (
out,
in0,
in1
);
endmodule
| 7.270171 |
module And_1bit (
dataA,
dataB,
ans
);
input dataA;
input dataB;
output ans;
assign ans = (dataA == 1 && dataB == 1) ? 1 : 0;
endmodule
| 6.843288 |
module And_1bit_in_aanb (
out,
a,
b
);
input a;
input b;
output out;
wire b_n;
Not_1bit_in_aanb not_1bit_in_aanb_0 (
b_n,
b
);
A_and_not_b_1bit aanb0 (
out,
a,
b_n
);
endmodule
| 6.708547 |
module And_1bit_in_nand (
out,
a,
b
);
input a;
input b;
output out;
wire out_n;
nand nand0 (out_n, a, b);
Not_1bit_in_nand not_1bit_in_nand_0 (
out,
out_n
);
endmodule
| 7.105106 |
module And_1bit_in_nor (
out,
a,
b
);
input a;
input b;
output out;
wire a_n;
wire b_n;
Not_1bit_in_nor not_1bit_in_nor_0 (
a_n,
a
);
Not_1bit_in_nor not_1bit_in_nor_1 (
b_n,
b
);
nor nor0 (out, a_n, b_n);
endmodule
| 7.105106 |
module and_1_4 (
out,
in0,
in1,
in2,
in3
);
input in0, in1, in2, in3;
output out;
wire w1, w2;
and and1 (w1, in0, in1);
and and2 (w2, in2, in3);
and and3 (out, w1, w2);
endmodule
| 7.17268 |
module and_1_5 (
out,
a,
b,
c,
d,
e
);
input a, b, c, d, e;
output out;
wire w1, w2, w3;
and a1 (w1, a, b);
and a2 (w2, w1, c);
and a3 (w3, w2, d);
and a4 (out, w3, e);
endmodule
| 6.714638 |
module and_1_8 (
out,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
);
input in0, in1, in2, in3, in4, in5, in6, in7;
output out;
wire w1, w2;
and_1_4 a1 (
w1,
in0,
in1,
in2,
in3
);
and_1_4 a2 (
w2,
in4,
in5,
in6,
in7
);
and a3 (out, w1, w2);
endmodule
| 6.504497 |
module and_21 (
in1,
in2,
out
);
input in1, in2;
output out;
assign out = in1 & in2;
endmodule
| 7.932357 |
module and_gate (
a,
b,
out
);
input a;
input b;
output out;
assign out = a && b;
endmodule
| 8.887051 |
module AND_2x1 (
a,
b,
out
);
input a, b;
output out;
assign out = a & b;
endmodule
| 7.493338 |
module AND_2_1 (
input wire IN_1,
input wire IN_0,
output wire OUT
);
assign OUT = IN_1 & IN_0;
endmodule
| 7.682028 |
module AND_32bit (
A,
B,
Out
);
parameter width = 32;
input [width-1:0] A;
input [width-1:0] B;
output [width-1:0] Out;
and AND1[width-1:0] (Out[width-1:0], A, B);
endmodule
| 8.382031 |
module and_32bit_testbench ();
reg [31:0] A, B;
wire [31:0] S;
and_32bit call (
S,
A,
B
);
initial begin
A = 32'b00000000011111111111000000000001;
B = 32'b11111111100000000000111111111111;
#`DELAY;
end
initial begin
$monitor("time = %2d, A =%32b, B=%32b,RESULT=%32b", $time, A, B, S);
end
endmodule
| 6.988353 |
module and_32_3 (
out,
a,
b,
c
);
input [31:0] a, b, c;
output [31:0] out;
wire [31:0] w1, out1;
and_32 and1 (
w1,
a,
b
);
and_32 and2 (
out,
c,
w1
);
endmodule
| 7.138238 |
module AND_32_Bit (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
assign {out} = in1 & in2;
endmodule
| 8.503043 |
module tb32bitand;
reg [31:0] IN1, IN2;
wire [31:0] OUT;
AND_32_Bit a1 (
OUT,
IN1,
IN2
);
initial begin
$monitor("IN1=%b, IN2=%b, OUT=%b", IN1, IN2, OUT);
IN1 = 32'hA5A5;
IN2 = 32'h5A5A;
#100 IN1 = 32'h5A5A;
#400 $finish;
end
endmodule
| 6.511751 |
module And_3bits_in_nor (
out,
a,
b,
c
);
input a;
input b;
input c;
output out;
wire a_n;
wire b_n;
wire c_n;
Not_1bit_in_nor not_1bit_in_nor_0 (
a_n,
a
);
Not_1bit_in_nor not_1bit_in_nor_1 (
b_n,
b
);
Not_1bit_in_nor not_1bit_in_nor_2 (
c_n,
c
);
nor nor0 (out, a_n, b_n, c_n);
endmodule
| 7.295932 |
module and_3entradas (
input A,
B,
C,
output S1
);
assign S1 = A & B & C;
endmodule
| 8.784598 |
module and_gate (
a,
b,
c,
out
);
input a;
input b;
input c;
output out;
assign out = (a & b & c);
endmodule
| 8.887051 |
module and_4 (
input in1_0,
input in1_1,
input in1_2,
input in1_3,
input in2_0,
input in2_1,
input in2_2,
input in2_3,
output [3:0] out
);
and a0 (out[0], in1_0, in2_0);
and a1 (out[1], in1_1, in2_1);
and a2 (out[2], in1_2, in2_2);
and a3 (out[3], in1_3, in2_3);
endmodule
| 6.78879 |
module and_4input (
S,
A,
B,
C,
D
);
input A, B, C, D;
output S;
and and0 (S, A, B, C, D);
endmodule
| 6.657285 |
module and_5 (
out,
a,
b
);
input [4:0] a, b;
output [4:0] out;
and_4 a1 (
out[3:0],
a[3:0],
b[3:0]
);
and a2 (out[4], a[4], b[4]);
endmodule
| 6.784415 |
module AND_64 (
out,
a,
b
);
parameter n = 64;
input signed [n-1:0] a, b;
output signed [n-1:0] out;
genvar i;
generate // Using generate statement to instantiate AND gate 64 times to implement the 64 bit AND operation
for (i = 0; i < n; i = i + 1) begin
and f (out[i], a[i], b[i]);
end
endgenerate
endmodule
| 7.969185 |
module AND_64_test;
parameter n = 64;
reg [n-1:0] a, b;
wire [n-1:0] out;
AND_64 a1 (
out,
a,
b
);
genvar i;
initial begin
$dumpfile("AND_64_test.vcd");
$dumpvars(0, AND_64_test);
a = 4;
b = 4;
#100;
$display("%b & %b = %b", a, b, out);
$display("Test Completed");
end
endmodule
| 6.699605 |
module and_8_bit (
input [7:0] a,
input [7:0] b,
output reg [7:0] op
);
integer i;
always @(*) begin
for (i = 0; i < 8; i = i + 1) begin
op[i] = a[i] & b[i];
end
end
endmodule
| 6.772322 |
module and_add (
P,
A,
b,
Out
);
input wire [8:0] P;
input wire [7:0] A;
input wire b;
output wire [8:0] Out;
assign Out = b ? (P + A) : P;
//assign Out = (P+A) * b + P * !b;
endmodule
| 7.0703 |
module and_ALU (
a,
b,
a_and_b
);
input a, b;
output a_and_b;
and and_a_b (a_and_b, a, b);
endmodule
| 8.537003 |
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