code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module am74ls139_testbench;
reg a, b;
reg g1;
wire [3:0] y;
am74ls139 dut (
.a (a),
.b (b),
.g_(g1),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input bval, aval, g1val;
begin
a <= aval;
b <= bval;
g1 <= g1val;
#1 $display("%5g: %1b %1b %... | 7.633259 |
module am74ls157 (
a,
b,
g_,
s,
y
);
parameter WIDTH = 4;
input [WIDTH-1:0] a, b;
input g_;
input s;
output [WIDTH-1:0] y;
assign y = (g_ == 1'b1) ? {WIDTH{1'b0}} : ((s == 1'b0) ? a : b);
endmodule
| 7.846002 |
module am74ls157_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] a, b;
reg g;
reg s;
wire [WIDTH-1:0] y;
am74ls157 #(
.WIDTH(WIDTH)
) dut (
.a (a),
.b (b),
.g_(g),
.s (s),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] aval, bval;
i... | 7.371408 |
module am74ls158 (
a,
b,
g_,
s,
y
);
parameter WIDTH = 4;
input [WIDTH-1:0] a, b;
input g_;
input s;
output [WIDTH-1:0] y;
assign y = ~((g_ == 1'b1) ? {WIDTH{1'b0}} : ((s == 1'b0) ? a : b));
endmodule
| 8.412113 |
module am74ls158_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] a, b;
reg g;
reg s;
wire [WIDTH-1:0] y;
am74ls158 #(
.WIDTH(WIDTH)
) dut (
.a (a),
.b (b),
.g_(g),
.s (s),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] aval, bval;
i... | 7.534878 |
module am74ls251 (
d,
a,
b,
c,
s_,
y,
w_
);
input [7:0] d;
input a, b, c;
input s_;
output y, w_;
assign y = (s_ == 1'b0) ? d[{c, b, a}] : 1'bz;
assign w_ = (s_ == 1'b0) ? ~y : 1'bz;
endmodule
| 6.561701 |
module am74ls251_testbench;
reg [7:0] d;
reg a, b, c, s_;
wire y, w_;
am74ls251 dut (
.d (d),
.a (a),
.b (b),
.c (c),
.s_(s_),
.y (y),
.w_(w_)
);
task tester;
input [80*8-1:0] descr;
input [7:0] dval;
input cval, bval, aval, sval;
begin
d ... | 6.610744 |
module AmbaMaster #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 32
) (
// Global signals
input wire ACLK,
input wire ARESETn,
// Write address channel signals
input wire AWREADY,
output reg [ADDR_WIDTH-1:0] AWADDR,
output reg [2:0] AWPROT,
output reg AWVALID,
// Write data ch... | 6.634617 |
module ahb_m2s_m2 (
input wire HRESETn
, input wire HCLK
, input wire HREADY
, input wire [ 3:0] HMASTER
, output reg [31:0] HADDR
, output reg [ 3:0] HPROT
, output reg [ 1:0] HTRANS
, output reg HWRITE
, output reg [ 2:0] HSIZE
, output re... | 6.565726 |
module ahb_decoder_s4 #(
parameter P_NUM = 4
, P_HSEL0_START = 32'h00000000,
P_HSEL0_SIZE = 32'h00010000
, P_HSEL0_END = P_HSEL0_START + P_HSEL0_SIZE
, P_HSEL1_START = 32'h10000000,
P_HSEL1_SIZE = 32'h00010000
, P_HSEL1_E... | 7.159616 |
module ahb_s2m_s4 (
input wire HRESETn
, input wire HCLK
, input wire HSELd
, input wire HSEL0
, input wire HSEL1
, input wire HSEL2
, input wire HSEL3
, output reg [31:0] HRDATA
, output reg [ 1:0] HRESP
, output reg ... | 7.097077 |
module ahb_default_slave (
input wire HRESETn
, input wire HCLK
, input wire HSEL
, input wire [31:0] HADDR
, input wire [ 1:0] HTRANS
, input wire HWRITE
, input wire [ 2:0] HSIZE
, input wire [ 2:0] HBURST
, input wire [31:0] HWDATA
, outp... | 6.712259 |
module address_decoder (
HSEL,
HADDR_DEC
);
//----------------------------I/O PORTS DECLARATIONS--------------------------------------//
output [2:0] HSEL; //3 slaves HSEL[1],HSEL[2],HSEL[3]
input [31:0] HADDR_DEC; //32bit slave address
parameter hsel_1_addr = 8'b00_00_00_00; //pre configured high ... | 7.247981 |
module address_control_mux (
HADDR_MUX,
HADDR_M1,
HADDR_M2,
HGRANT
);
output [31:0] HADDR_MUX;
input [31:0] HADDR_M1, HADDR_M2;
input HGRANT;
assign HADDR_MUX = (HGRANT == 1'b1) ? HADDR_M1 : HADDR_M2; //2:1 MUX with HGRANT as Select Line
endmodule
| 8.472432 |
module amba_apb (
pclk,
preset,
psel,
penable,
pwrite,
paddr,
pwdata,
prdata,
pready
);
input pclk; // clock signal
input preset; // 1bit reset signal
input psel; // 1bit select signal
input penable; // 1bit enable signal
input pwrite; // direction signal (1=write/0=r... | 8.345971 |
module amba_apb (
pclk,
preset,
psel,
penable,
pwrite,
paddr,
pwdata,
prdata,
pready
);
input pclk; // clock signal
input preset; // reset signal
input psel; // select signal
input penable; // enable signal
input pwrite; // direction signal
input [0:31] paddr; // 3... | 8.345971 |
module amba_apb_top ();
wire [0:31] prdata;
reg pclk, preset, psel, penable, pwrite, pready;
reg [0:31] paddr, pwdata;
amba_apb AMBA_APB (
pclk,
preset,
psel,
penable,
pwrite,
paddr,
pwdata,
prdata,
pready
);
initial begin
pclk = 0;
psel = 0;
... | 7.540293 |
module axi_arbiter_stom_s3 #(
parameter NUM = 3
) // num of slaves
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input ... | 7.648984 |
module amba__write_channel (
input clk,
reset,
input [5:0] m2i_AWID, // ID of the slave to wchich data has to be written
input [32:0] m2i_AWADDR, // Starting Address of the periphera whose ID is transferred
input [3:0] m2i_AWLEN, // Maximum 8 burst at a time
input [3:0] m2i_AWSIZE, // Maxim... | 8.584265 |
module generic_sram_byte_en #(
parameter DATA_WIDTH = 32,
parameter ADDRESS_WIDTH = 4
) (
input i_clk,
input [ DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
input [ DATA_WIDTH/8-1... | 7.001881 |
module AmbientLightSensorDemo (
input wire clk,
input wire rst,
input wire oe,
input wire trigger,
input wire sdata,
output wire cs,
output wire sclk,
output wire done
);
wire [31:0] data;
wire not_oe;
wire not_trigger;
assign not_oe = ~oe;
assign not_trigger = ~trigger;... | 6.501672 |
module AmbientLightSensor (
input wire clk,
input wire rst,
input wire oe, // output enable
input wire trigger, // trigger/start ADC conversion
input wire sdata, // ADC serial data output
output reg sclk, // ADC serial clock driver
output reg cs, // ADC chip select
output reg done, ... | 6.501672 |
module music (
clk,
speaker
);
input clk;
output speaker;
parameter clkdivider = 25000000 / 440 / 2;
reg [23:0] tone;
always @(posedge clk) tone <= tone + 1;
reg [14:0] counter;
always @(posedge clk)
if (counter == 0) counter <= (tone[23] ? clkdivider - 1 : clkdivider / 2 - 1);
else coun... | 6.77205 |
module amc7823 #(
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 16,
parameter SPIMODE = "passthrough"
) (
output ss,
input miso,
output mosi,
output sclk,
input clk,
input spi... | 7.256599 |
module amc7823_sim (
input ss,
output miso,
input mosi,
input sclk
);
// pin ss is IO_L18N_T2_32 bank 32 bus_digitizer_U15[2] AB20
// pin miso is IO_L18P_T2_32 bank 32 bus_digitizer_U15[1] AB19
// pin mosi is IO_L23N_T3_32 bank 32 bus_digitizer_U18[3] ... | 6.79974 |
module amf (
dataOut,
addrOut,
addrIn,
filterF,
dataIn,
M,
N,
filterEn,
clk,
rst
);
// Parameter
parameter DATA_WIDTH = 8, ADDR_WIDTH = 8, WINDOW_N = 2, T1 = 0, T2 = 255;
parameter WINDOW_W = 2 * WINDOW_N + 1; // Window's width : W = 2n + 1
parameter WINDOW_S = WINDOW_W... | 8.560382 |
module amiga_clk (
input clk_28, // 28MHz output clock ( 28.375160MHz)
output clk7_en, // 7MHz output clock enable (on 28MHz clock domain)
output clk7n_en, // 7MHz negedge output clock enable (on 28MHz clock domain)
output reg c1, // clk28m clock domain signal synchronous with clk signal
output ... | 8.114158 |
module amiga_clk_xilinx (
input wire areset,
input wire inclk0,
output wire c0,
output wire c1,
output wire c2,
output wire locked
);
// internal wires
wire pll_114;
wire dll_114;
wire dll_28;
reg [1:0] clk_7 = 0;
// pll
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,... | 7.447877 |
module amm_master_qsys_with_pcie_altpll_qsys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
//... | 6.962337 |
module amm_master_qsys_with_pcie_altpll_qsys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
amm_master_qsys_with_pcie_altpll_qsys_dffpipe_l2c dffpipe3 (
.clock(clk),
.c... | 6.962337 |
module amm_master_qsys_with_pcie_altpll_qsys (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
... | 6.962337 |
module amm_master_qsys_with_pcie (
clk_clk,
reset_reset_n,
pcie_ip_reconfig_togxb_data,
pcie_ip_refclk_export,
pcie_ip_test_in_test_in,
pcie_ip_pcie_rstn_export,
pcie_ip_clocks_sim_clk250_export,
pcie_ip_clocks_sim_clk500_export,
pcie_ip_clocks_sim_clk125_export,
pcie_ip_reconfig... | 6.962337 |
module amm_master_qsys_with_pcie_reconf_registers (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "amm_master_qsys_with_pcie_reconf_registers.hex";
output [31:0] readdata;
... | 6.962337 |
module amm_master_qsys_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [60:0] rd_data;
in... | 6.962337 |
module amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
... | 6.962337 |
module amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
);
output m_writefifo_empty;
output m_writef... | 6.962337 |
module amm_master_qsys_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0]... | 6.962337 |
module amm_master_qsys_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
ou... | 6.962337 |
module amm_master_qsys_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
ou... | 6.962337 |
module AMOALU (
input clock,
input reset,
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out,
output [63:0] io_out_unmasked
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = i... | 8.467919 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apx2... | 7.233653 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4)... | 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));... | 7.725792 |
module cprs_4_2_apx1 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
assign err = x1 & x2 & x3 & x4;
assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
endmodule
| 7.110479 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apx2... | 7.233653 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4)... | 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));... | 7.725792 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apx2... | 7.233653 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4)... | 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));... | 7.725792 |
module cprs_4_2_apxe4 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// ap... | 7.211389 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4)... | 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));... | 7.725792 |
module AMP (
input [1:0] divisor,
input [7:0] inp,
output [7:0] out
);
assign out = inp >> divisor;
endmodule
| 8.20315 |
modules: N/A
*- Description: Adjust the amplitude of a 10-bit digital signal
*-
*- Example of Usage:
- This code allows you to adjust the amplitude for a 10-bit digital signal. Most of the cases
you can connect this module directly to the digital sinusoidal wave generator 'sin_anyfreq'.
- The output ... | 6.670404 |
module amplifier (
output reg [23:0] out_data,
output reg out_valid,
input [23:0] in_data,
input wren,
input clk,
input reset,
input [3:0] gain
);
always @(posedge clk or posedge reset)
if (reset) begin
out_data <= 0;
out_valid <= 1'b0;
end else if (wren) begin
c... | 7.334477 |
module ampliTB ();
wire clk;
inverter #(5, 2) inv (
1'b1,
clk
);
reg rst;
reg cnt, ld;
wire co1, co2;
wire [3:0] out1, out2;
reg [12:0] SW;
wire [7:0] signal;
wire [7:0] signal_out;
reg clk_in;
initial begin
clk_in = 1'b0;
end
frequency_divider fre1 (
clk,
rs... | 6.701225 |
module amplitude (
input [7:0] signal_in,
input [1:0] am,
output [7:0] signal_out
);
assign signal_out = (am == 2'b00) ? (signal_in >>> 1) :
(am == 2'b01) ? (signal_in >>> 2) :
(am == 2'b10) ? (signal_in >>> 3) :
(am == 2'b11) ? (signal_in >>> 4) : signal_in;
endmodule
| 7.443866 |
module AmplitudeSelector (
input [1:0] select,
input [7:0] in,
output [7:0] out
);
assign out = in >> select;
endmodule
| 7.783462 |
module amplitude_adjust (
input clk,
input [9:0] amplitude,
input signed [11:0] ast_sink_data,
input ast_sink_valid,
input [1:0] ast_sink_error,
output signed [11:0] ast_source_data,
output reg ast_source_valid,
output reg [1:0] ast_source_error
);
//
reg signed [21:0] signed_result... | 8.752326 |
module Amplitude_selector (
amp_sel,
amp_in,
amp_out
);
input [1:0] amp_sel;
input [7:0] amp_in;
output [7:0] amp_out;
assign amp_out = amp_in >> amp_sel;
endmodule
| 7.982747 |
module amplitude_set (
input clk,
input rst_n,
input key2_in,
output reg [4:0] amplitude
);
reg [2:0] cnt ;
wire key_flag ;
wire key_state ;
key_filter amplitude_key (
.clk (clk),
.rst_n (rst_n),
.key_in (key2_in),
.key_flag (key_flag),
.key_state(... | 8.93875 |
module amp_adj (
input wire clk,
input wire rst_n,
input wire [7:0] wave,
input wire [4:0] amp_factor,
output reg [7:0] wave_adj
);
always @(posedge clk or negedge rst_n)
if (!rst_n) wave_adj <= 10'd0;
else wave_adj <= wave * amp_factor / 10;
endmodule
| 9.032654 |
module NCO_AMP_CONTROLLER #(
parameter DAC_WIDTH = 14,
parameter IN_WIDTH = 14
) (
input clk,
input rst,
input signed [IN_WIDTH-1:0] INPUT_NCO,
input signed [DAC_WIDTH-1:0] MAX_VOLTAGE,
output signed [DAC_WIDTH-1:0] OUTPUT_NCO
);
wire [IN_WIDTH-1:0] IN_T;
assign IN_T = INPUT_NCO[IN_WID... | 7.980459 |
module amp_control_max (
input ENABLE,
input FF_CLOCK,
input CLOCK_2HZ,
input CLOCK_8HZ,
input CLOCK_32HZ,
input CLOCK_128HZ,
input CLOCK_512HZ,
input UP,
input DOWN,
input [31:0] MIN_AMP,
output reg [31:0] MAX_AMP = 32'd4095
);
wire CLOCK;
reg [3:0] COUNT = 6'd0;
reg ... | 7.302448 |
module amp_control_min (
input ENABLE,
input FF_CLOCK,
input CLOCK_2HZ,
input CLOCK_8HZ,
input CLOCK_32HZ,
input CLOCK_128HZ,
input CLOCK_512HZ,
input UP,
input DOWN,
input [31:0] MAX_AMP,
output reg [31:0] MIN_AMP = 32'd1
);
wire CLOCK;
reg [3:0] COUNT = 6'd0;
reg [15... | 7.302448 |
module AMP_TB ();
reg rst = 1, inp = 1, ld = 1, preset = 0;
reg [7:0] phaseControll = 8'd1;
reg [12:0] SW = 13'b0000111111101;
wire [7:0] wave;
wire clk;
WFG_DDS_FS_AMP CUT (
.wave(wave),
.preset(preset),
.clk(clk),
.SW(SW),
.rst(rst),
.ld(ld),
.phaseControll(phase... | 7.1397 |
module PP_HIGH (
ONEPOS,
ONENEG,
TWOPOS,
TWONEG,
INA,
INB,
PPBIT
);
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = ~((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG));
endmodule
| 6.512332 |
module R_GATE (
INA,
INB,
INC,
PPBIT
);
input INA;
input INB;
input INC;
output PPBIT;
assign PPBIT = (~(INA & INB)) & INC;
endmodule
| 8.459695 |
module DECODER (
INA,
INB,
INC,
TWOPOS,
TWONEG,
ONEPOS,
ONENEG
);
input INA;
input INB;
input INC;
output TWOPOS;
output TWONEG;
output ONEPOS;
output ONENEG;
assign TWOPOS = ~(~(INA & INB & (~INC)));
assign TWONEG = ~(~((~INA) & (~INB) & INC));
assign ONEPOS = ((~INA) & ... | 6.800244 |
module HALF_ADDER (
DATA_A,
DATA_B,
SAVE,
CARRY
);
input DATA_A;
input DATA_B;
output SAVE;
output CARRY;
assign SAVE = DATA_A ^ DATA_B;
assign CARRY = DATA_A & DATA_B;
endmodule
| 6.537169 |
module FLIPFLOP (
DIN,
RST,
CLK,
DOUT
);
input DIN;
input RST;
input CLK;
output DOUT;
reg DOUT_reg;
always @(posedge RST or posedge CLK) begin
if (RST) DOUT_reg <= 1'b0;
else DOUT_reg <= DIN;
end
assign DOUT = DOUT_reg;
endmodule
| 7.654726 |
module XXOR1 (
A,
B,
GIN,
PHI,
SUM
);
input A;
input B;
input GIN;
input PHI;
output SUM;
assign SUM = (~(A ^ B)) ^ GIN;
endmodule
| 7.036883 |
module BLOCK0 (
A,
B,
PHI,
POUT,
GOUT
);
input A;
input B;
input PHI;
output POUT;
output GOUT;
assign POUT = ~(A | B);
assign GOUT = ~(A & B);
endmodule
| 7.437441 |
module BLOCK1 (
PIN1,
PIN2,
GIN1,
GIN2,
PHI,
POUT,
GOUT
);
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~(PIN1 | PIN2);
assign GOUT = ~(GIN2 & (PIN2 | GIN1));
endmodule
| 7.87169 |
module BLOCK2 (
PIN1,
PIN2,
GIN1,
GIN2,
PHI,
POUT,
GOUT
);
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~(PIN1 & PIN2);
assign GOUT = ~(GIN2 | (PIN2 & GIN1));
endmodule
| 8.324076 |
module BLOCK1A (
PIN2,
GIN1,
GIN2,
PHI,
GOUT
);
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~(GIN2 & (PIN2 | GIN1));
endmodule
| 7.952894 |
module BLOCK2A (
PIN2,
GIN1,
GIN2,
PHI,
GOUT
);
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~(GIN2 | (PIN2 & GIN1));
endmodule
| 8.386736 |
module MULTIPLIER_33_32 (
MULTIPLICAND,
MULTIPLIER,
RST,
CLK,
PHI,
RESULT
);
input [0:32] MULTIPLICAND;
input [0:31] MULTIPLIER;
input RST;
input CLK;
input PHI;
output [0:63] RESULT;
wire [0:575] PPBIT;
wire [0:64] INT_CARRY;
wire [0:63] INT_SUM;
wire LOGIC_ZERO;
wire [0:6... | 7.769651 |
module aMux (
a_flag,
PC,
DR,
R1,
R2,
R3,
R4,
R5,
A_bus
);
input [2:0] a_flag;
input [15:0] PC, DR, R1, R2, R3, R4, R5;
output [15:0] A_bus;
reg [15:0] A_bus;
always @(*) begin
case (a_flag)
3'd1: A_bus = PC;
3'd2: A_bus = DR;
3'd3: A_bus = R1;
3... | 7.934675 |
module AMUX2_3V (
input wire real VDD3V3,
input wire real VDD1V8,
input wire real VSSA,
input wire real AIN1,
input wire real AIN2,
output wire real AOUT,
input SEL
);
wire SEL;
real NaN;
initial begin
NaN = 0.0 / 0.0;
end
assign AOUT = (SEL == 1'b1) ? AIN2 : (SEL == 1'b0) ? ... | 7.882222 |
module AMUX4_3V (
input wire real VDD3V3,
input wire real VDD1V8,
input wire real VSSA,
input wire real AIN1,
input wire real AIN2,
input wire real AIN3,
input wire real AIN4,
output wire real AOUT,
input [1:0] SEL
);
wire [1:0] SEL;
real NaN;
initial begin
NaN = 0.0 / 0.0... | 7.508087 |
module am_demod #(
parameter BITS = 16
) (
input CLK,
input RSTb,
input signed [BITS - 1 : 0] I_in,
input signed [BITS - 1 : 0] Q_in,
input load_tick, /* tick should go high when new sample is ready */
output reg signed [BITS - 1:0] demod_out,
output reg out_tick /* tick will go high... | 6.996844 |
module am_FIFO (
clk,
clear_b,
a_in,
b_in,
sign_q,
exponent_q,
state_cnt,
sign_passed,
exponent_passed,
product
);
//-----------------------Input Ports-----------------------//
input wire clk;
input wire clear_b;
input wire [23:0] a_in; //24-bit extended mantissa of ei... | 6.662127 |
module am_gen (
input CLK,
input RSTb,
output reg one_bit_rf
);
/* Carrier */
wire [39:0] phase_inc = 40'h2656abde3; // 936 kHz
wire signed [15:0] sin;
wire signed [15:0] cos;
nco nco0 (
CLK,
RSTb,
phase_inc,
sin,
cos
);
/* Modulation */
/* phase inc => ... | 6.674582 |
module am_insertion #(
parameter LEN_CODED_BLOCK = 66,
parameter AM_ENCODING_LOW = 24'd0, //{M0,M1,M2} tabla 82-2
parameter AM_ENCODING_HIGH = 24'd0, //{M4,M5,M6} tabla 82-2
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
inp... | 7.003169 |
module am_insertion #(
parameter LEN_CODED_BLOCK = 66,
parameter AM_ENCODING_LOW = 24'd0, //{M0,M1,M2} tabla 82-2
parameter AM_ENCODING_HIGH = 24'd0, //{M4,M5,M6} tabla 82-2
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
inp... | 7.003169 |
module am_lock_comparator #(
parameter LEN_AM = 48,
parameter N_ALIGNER = 20
) (
input wire i_enable_mask, // input from fsm
input wire i_timer_done,
input wire [ LEN_AM-1 : 0] i_am_value,
input wire [N_ALIGNER-1 : 0] i_match_mask,
input wire ... | 7.126741 |
module am_lock_comparator_v2
#(
parameter NB_AM = 48,
parameter N_ALIGNER = 20
)
( input wire i_enable_mask, // input from fsm
input wire i_timer_done ,
input wire [NB_AM-1 : 0] i_am_value ,
input wire [NB_AM-1 : 0] i_compare_mask , //mascara configurable para permitir flexibilidad en la... | 7.126741 |
module am_mask_handler
#(
parameter NB_AM = 48,
)
(
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_config,
input wire [NB_AM-1 : 0] i_mask_config,
output wire [NB_AM-1 : 0] o_compare_mask
);
//INTERNAL SIGNALS
reg [NB_AM-1 : 0] se... | 6.745844 |
module AM_MODE (
input clk,
rst_n,
output dac_clk,
output adc_clk,
output [13:0] am
);
wire rst;
wire clk_200M;
wire [14:0] out;
wire [7:0] add1_temp; //加法数据
wire [8:0] add1_s;
wire [13:0] carrier_signal; //载波信号
wire signed [8:0] depth; //调制深度
wire [8:0] add_out; //加法... | 6.787392 |
module am_modulator (
input wire clk,
input wire [7:0] signal,
input wire signed [15:0] mod_sin,
output wire [5:0] out
);
//make signed 16bit signal from input unsigned 8bit signal
reg signed [15:0] ssignal;
always @(posedge clk) ssignal <= {signal, 8'h00} - 16'h8000;
//modulate by multiplying... | 7.730983 |
module am_mod_counter #(
parameter N_BLOCKS = 16383, //[REVISAR] cantidad de bloquen entre am y am
parameter N_LANES = 20
) (
input wire i_reset,
input wire i_clock,
input wire i_enable,
input wire i_valid, // coontrol de flujo de cgmii, puede estar siempre en 1
output wire o_block_coun... | 6.625695 |
module am_shift (
input [15:0] a_m,
input [ 4:0] tmp_cnt,
output [15:0] a_m_shift
);
assign a_m_shift = a_m << tmp_cnt;
endmodule
| 7.120022 |
module am_shifter (
input [15:0] datain,
input right,
input [1:0] bitnum,
output [15:0] dataout
);
wire [14:0] right_temp = datain[15:1];
wire [14:0] left_temp = datain[14:0];
wire [15:0] data_temp = (right == 1'b1) ? {datain[15], right_temp} : {left_temp, 1'b0};
assign dataout[3:0] = {
(... | 6.53352 |
module am_shift_t (
input [5:0] a_e,
input [5:0] sub_a_e,
input [15:0] a_m,
output reg [27:0] a_m_shift
);
always @(a_e or sub_a_e or a_m) begin
if (a_e <= 15 && a_e >= 0) begin
a_m_shift = {a_m, 12'b0} >> sub_a_e;
end else begin
a_m_shift = 24'h0;
end
end
endmodule
| 7.742958 |
module am_sol_timer #(
parameter N_BLOCKS = 16383, //[check]
parameter EXTRA_DELAY = 0 //depends on reset conditiones
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_restart,
output reg o_start_of_lane
);
//LOCALPARAMS
localp... | 6.577716 |
module Decoder_2_to_4 (
out,
a,
b
);
output [3:0] out;
input a, b;
wire n1, n2;
NOR2X1 U1 (
.A(n1),
.B(n2),
.Y(out[3])
);
NOR2X1 U2 (
.A(b),
.B(n1),
.Y(out[2])
);
CLKINVX1 U3 (
.A(a),
.Y(n1)
);
NOR2X1 U4 (
.A(a),
.B(n2),
... | 6.672456 |
module Decoder_2_to_4_2 (
out,
a,
b
);
output [3:0] out;
input a, b;
wire n1, n2;
NOR2X1 U7 (
.A(n1),
.B(n2),
.Y(out[3])
);
NOR2X1 U8 (
.A(b),
.B(n1),
.Y(out[2])
);
CLKINVX1 U9 (
.A(a),
.Y(n1)
);
NOR2X1 U10 (
.A(a),
.B(n2),
... | 6.672456 |
module Decoder_2_to_4_1 (
out,
a,
b
);
output [3:0] out;
input a, b;
wire n1, n2;
NOR2X1 U7 (
.A(n1),
.B(n2),
.Y(out[3])
);
NOR2X1 U8 (
.A(b),
.B(n1),
.Y(out[2])
);
CLKINVX1 U9 (
.A(a),
.Y(n1)
);
NOR2X1 U10 (
.A(a),
.B(n2),
... | 6.672456 |
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