code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module am74ls139_testbench;
reg a, b;
reg g1;
wire [3:0] y;
am74ls139 dut (
.a (a),
.b (b),
.g_(g1),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input bval, aval, g1val;
begin
a <= aval;
b <= bval;
g1 <= g1val;
#1 $display("%5g: %1b %1b %1b | %4b | %0s", $time, b, a, g1, y, descr);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am74ls139.vcd");
$dumpvars;
$display("-time: b a g1 | y | description");
// -b-- -a-- -g1-
tester("disable g1", 1'bx, 1'bx, 1'b1);
tester("y0 = low", 1'b0, 1'b0, 1'b0);
tester("y1 = low", 1'b0, 1'b1, 1'b0);
tester("y2 = low", 1'b1, 1'b0, 1'b0);
tester("y3 = low", 1'b1, 1'b1, 1'b0);
#10 $finish;
end
endmodule
| 7.633259 |
module am74ls157 (
a,
b,
g_,
s,
y
);
parameter WIDTH = 4;
input [WIDTH-1:0] a, b;
input g_;
input s;
output [WIDTH-1:0] y;
assign y = (g_ == 1'b1) ? {WIDTH{1'b0}} : ((s == 1'b0) ? a : b);
endmodule
| 7.846002 |
module am74ls157_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] a, b;
reg g;
reg s;
wire [WIDTH-1:0] y;
am74ls157 #(
.WIDTH(WIDTH)
) dut (
.a (a),
.b (b),
.g_(g),
.s (s),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] aval, bval;
input gval, sval;
input [WIDTH-1:0] expecty;
begin
a <= aval;
b <= bval;
g <= gval;
s <= sval;
#1 $display("%5g: %b %b %1b %1b | %4b | %0s", $time, b, a, g, s, y, descr);
if (expecty != y) begin
$display("Error: y should be %4b, but is %4b", expecty, y);
end
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am74ls157.vcd");
$dumpvars;
$display("-time: -a-- -b-- g s | -y-- | description");
// ---a--- ---b--- -g_- -s-- -expect-
tester("disable", 4'bxxxx, 4'bxxxx, 1'b1, 1'bx, 4'b0000);
tester("select A", 4'b0000, 4'bxxxx, 1'b0, 1'b0, 4'b0000);
tester("", 4'b1111, 4'bxxxx, 1'b0, 1'b0, 4'b1111);
tester("select B", 4'bxxxx, 4'b0000, 1'b0, 1'b1, 4'b0000);
tester("", 4'bxxxx, 4'b1111, 1'b0, 1'b1, 4'b1111);
#10 $finish;
end
endmodule
| 7.371408 |
module am74ls158 (
a,
b,
g_,
s,
y
);
parameter WIDTH = 4;
input [WIDTH-1:0] a, b;
input g_;
input s;
output [WIDTH-1:0] y;
assign y = ~((g_ == 1'b1) ? {WIDTH{1'b0}} : ((s == 1'b0) ? a : b));
endmodule
| 8.412113 |
module am74ls158_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] a, b;
reg g;
reg s;
wire [WIDTH-1:0] y;
am74ls158 #(
.WIDTH(WIDTH)
) dut (
.a (a),
.b (b),
.g_(g),
.s (s),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] aval, bval;
input gval, sval;
input [WIDTH-1:0] expecty;
begin
a <= aval;
b <= bval;
g <= gval;
s <= sval;
#1 $display("%5g: %b %b %1b %1b | %4b | %0s", $time, b, a, g, s, y, descr);
if (expecty != y) begin
$display("Error: y should be %4b, but is %4b", expecty, y);
end
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am74ls157.vcd");
$dumpvars;
$display("-time: -a-- -b-- g s | -y-- | description");
// ---a--- ---b--- -g_- -s-- -expect-
tester("disable", 4'bxxxx, 4'bxxxx, 1'b1, 1'bx, 4'b1111);
tester("select A", 4'b0000, 4'bxxxx, 1'b0, 1'b0, 4'b1111);
tester("", 4'b1111, 4'bxxxx, 1'b0, 1'b0, 4'b0000);
tester("select B", 4'bxxxx, 4'b0000, 1'b0, 1'b1, 4'b1111);
tester("", 4'bxxxx, 4'b1111, 1'b0, 1'b1, 4'b0000);
#10 $finish;
end
endmodule
| 7.534878 |
module am74ls251 (
d,
a,
b,
c,
s_,
y,
w_
);
input [7:0] d;
input a, b, c;
input s_;
output y, w_;
assign y = (s_ == 1'b0) ? d[{c, b, a}] : 1'bz;
assign w_ = (s_ == 1'b0) ? ~y : 1'bz;
endmodule
| 6.561701 |
module am74ls251_testbench;
reg [7:0] d;
reg a, b, c, s_;
wire y, w_;
am74ls251 dut (
.d (d),
.a (a),
.b (b),
.c (c),
.s_(s_),
.y (y),
.w_(w_)
);
task tester;
input [80*8-1:0] descr;
input [7:0] dval;
input cval, bval, aval, sval;
begin
d <= dval;
a <= aval;
b <= bval;
c <= cval;
s_ <= sval;
#1
$display(
"%5g: %8b %1b %1b %1b %1b | %1b %1b | %0s", $time, d, a, b, c, s_, y, w_, descr
);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am74ls251.vcd");
$dumpvars;
$display("-time: ---d---- c b a s_ | y w_ | description");
// ---d----- --c-- --b-- --a-- -s_-
tester("tristate", 8'bxxxxxxxx, 1'bx, 1'bx, 1'bx, 1'b1);
tester("d0 = low", 8'bxxxxxxx0, 1'b0, 1'b0, 1'b0, 1'b0);
tester("d0 = high", 8'bxxxxxxx1, 1'b0, 1'b0, 1'b0, 1'b0);
tester("d1 = low", 8'bxxxxxx0x, 1'b0, 1'b0, 1'b1, 1'b0);
tester("d1 = high", 8'bxxxxxx1x, 1'b0, 1'b0, 1'b1, 1'b0);
tester("d2 = low", 8'bxxxxx0xx, 1'b0, 1'b1, 1'b0, 1'b0);
tester("d2 = high", 8'bxxxxx1xx, 1'b0, 1'b1, 1'b0, 1'b0);
tester("d3 = low", 8'bxxxx0xxx, 1'b0, 1'b1, 1'b1, 1'b0);
tester("d3 = high", 8'bxxxx1xxx, 1'b0, 1'b1, 1'b1, 1'b0);
tester("d4 = low", 8'bxxx0xxxx, 1'b1, 1'b0, 1'b0, 1'b0);
tester("d4 = high", 8'bxxx1xxxx, 1'b1, 1'b0, 1'b0, 1'b0);
tester("d5 = low", 8'bxx0xxxxx, 1'b1, 1'b0, 1'b1, 1'b0);
tester("d5 = high", 8'bxx1xxxxx, 1'b1, 1'b0, 1'b1, 1'b0);
tester("d6 = low", 8'bx0xxxxxx, 1'b1, 1'b1, 1'b0, 1'b0);
tester("d6 = high", 8'bx1xxxxxx, 1'b1, 1'b1, 1'b0, 1'b0);
tester("d7 = low", 8'b0xxxxxxx, 1'b1, 1'b1, 1'b1, 1'b0);
tester("d7 = high", 8'b1xxxxxxx, 1'b1, 1'b1, 1'b1, 1'b0);
#10 $finish;
end
endmodule
| 6.610744 |
module AmbaMaster #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 32
) (
// Global signals
input wire ACLK,
input wire ARESETn,
// Write address channel signals
input wire AWREADY,
output reg [ADDR_WIDTH-1:0] AWADDR,
output reg [2:0] AWPROT,
output reg AWVALID,
// Write data channel
input wire WREADY,
output reg [DATA_WIDTH-1:0] WDATA,
output reg [DATA_WIDTH/8 - 1 : 0] WSTRB,
output reg WVALID,
// Write response channel signals
input wire [1:0] BRESP,
input wire BVALID,
output reg BREADY,
// Read address channel signals
input wire ARREADY,
output reg [ADDR_WIDTH-1:0] ARADDR,
output reg [2:0] ARPROT,
output reg ARVALID,
// Read data channel signals
input wire [DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RVALID,
output reg RREADY,
output wire [31:0] MouseState
);
// Write FSM
wire reset = ~ARESETn;
reg [ADDR_WIDTH-1:0] AWADDR_next;
reg [2:0] AWPROT_next;
reg [DATA_WIDTH-1:0] WDATA_next;
reg [DATA_WIDTH/8 - 1 : 0] WSTRB_next;
reg WVALID_next, BREADY_next, AWVALID_next;
reg [1:0] wstate, wstate_next;
localparam RESET = 0, VALID = 1, READY = 2, RESP = 3;
// Read FSM
reg [ADDR_WIDTH-1:0] ARADDR_next;
reg [2:0] ARPROT_next;
reg ARVALID_next, RREADY_next;
reg [1:0] rstate, rstate_next;
assign MouseState = RDATA;
always @(posedge reset, posedge ACLK)
if (reset) begin
ARVALID <= 0;
ARADDR <= 0;
rstate <= RESET;
end else begin
ARADDR <= ARADDR_next;
ARPROT <= ARPROT_next;
ARVALID <= ARVALID_next;
RREADY <= RREADY_next;
rstate <= rstate_next;
end
always @* begin
ARADDR_next = ARADDR;
ARPROT_next = ARPROT;
ARVALID_next = ARVALID;
RREADY_next = RREADY;
case (rstate)
RESET: rstate_next = VALID;
VALID: begin
ARVALID_next = 1;
ARADDR_next = 8'h02; // STATE
ARPROT_next = 3'b010;
RREADY_next = 1;
rstate_next = READY;
end
READY:
if (ARREADY) begin
ARVALID_next = 0;
rstate_next = RESP;
end
RESP:
if (RVALID) begin
// add read code
//MouseState <= RDATA;
RREADY_next = 0;
rstate_next = VALID;
end
endcase
end
endmodule
| 6.634617 |
module ahb_m2s_m2 (
input wire HRESETn
, input wire HCLK
, input wire HREADY
, input wire [ 3:0] HMASTER
, output reg [31:0] HADDR
, output reg [ 3:0] HPROT
, output reg [ 1:0] HTRANS
, output reg HWRITE
, output reg [ 2:0] HSIZE
, output reg [ 2:0] HBURST
, output reg [31:0] HWDATA
, input wire [31:0] HADDR0
, input wire [ 3:0] HPROT0
, input wire [ 1:0] HTRANS0
, input wire HWRITE0
, input wire [ 2:0] HSIZE0
, input wire [ 2:0] HBURST0
, input wire [31:0] HWDATA0
, input wire [31:0] HADDR1
, input wire [ 3:0] HPROT1
, input wire [ 1:0] HTRANS1
, input wire HWRITE1
, input wire [ 2:0] HSIZE1
, input wire [ 2:0] HBURST1
, input wire [31:0] HWDATA1
);
reg [3:0] hmaster_delay = 4'h0;
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) begin
hmaster_delay <= 4'b0;
end else begin
if (HREADY) begin
hmaster_delay <= HMASTER;
end
end
end
always @(HMASTER or HADDR0 or HADDR1) begin
case (HMASTER)
4'h0: HADDR = HADDR0;
4'h1: HADDR = HADDR1;
default: HADDR = ~32'b0;
endcase
end
always @(HMASTER or HPROT0 or HPROT1) begin
case (HMASTER)
4'h0: HPROT = HPROT0;
4'h1: HPROT = HPROT1;
default: HPROT = 4'b0;
endcase
end
always @(HMASTER or HTRANS0 or HTRANS1) begin
case (HMASTER)
4'h0: HTRANS = HTRANS0;
4'h1: HTRANS = HTRANS1;
default: HTRANS = 2'b0;
endcase
end
always @(HMASTER or HWRITE0 or HWRITE1) begin
case (HMASTER)
4'h0: HWRITE = HWRITE0;
4'h1: HWRITE = HWRITE1;
default: HWRITE = 1'b0;
endcase
end
always @(HMASTER or HSIZE0 or HSIZE1) begin
case (HMASTER)
4'h0: HSIZE = HSIZE0;
4'h1: HSIZE = HSIZE1;
default: HSIZE = 3'b0;
endcase
end
always @(HMASTER or HBURST0 or HBURST1) begin
case (HMASTER)
4'h0: HBURST = HBURST0;
4'h1: HBURST = HBURST1;
default: HBURST = 3'b0;
endcase
end
always @(hmaster_delay or HWDATA0 or HWDATA1) begin
case (hmaster_delay)
4'h0: HWDATA = HWDATA0;
4'h1: HWDATA = HWDATA1;
default: HWDATA = 3'b0;
endcase
end
endmodule
| 6.565726 |
module ahb_decoder_s4 #(
parameter P_NUM = 4
, P_HSEL0_START = 32'h00000000,
P_HSEL0_SIZE = 32'h00010000
, P_HSEL0_END = P_HSEL0_START + P_HSEL0_SIZE
, P_HSEL1_START = 32'h10000000,
P_HSEL1_SIZE = 32'h00010000
, P_HSEL1_END = P_HSEL1_START + P_HSEL1_SIZE
, P_HSEL2_START = 32'h20000000,
P_HSEL2_SIZE = 32'h00010000
, P_HSEL2_END = P_HSEL2_START + P_HSEL2_SIZE
, P_HSEL3_START = 32'h30000000,
P_HSEL3_SIZE = 32'h00010000
, P_HSEL3_END = P_HSEL3_START + P_HSEL3_SIZE
) (
input wire [31:0] HADDR
, output wire HSELd // default slave
, output wire HSEL0
, output wire HSEL1
, output wire HSEL2
, output wire HSEL3
, input wire REMAP
);
wire [3:0] ihsel;
wire ihseld = ~|ihsel;
assign HSELd = ihseld;
assign HSEL0 = (REMAP) ? ihsel[1] : ihsel[0];
assign HSEL1 = (REMAP) ? ihsel[0] : ihsel[1];
assign HSEL2 = ihsel[2];
assign HSEL3 = ihsel[3];
assign ihsel[0] = ((P_NUM>0)&&(HADDR>=P_HSEL0_START)&&(HADDR<P_HSEL0_END)) ? 1'b1 : 1'b0;
assign ihsel[1] = ((P_NUM>1)&&(HADDR>=P_HSEL1_START)&&(HADDR<P_HSEL1_END)) ? 1'b1 : 1'b0;
assign ihsel[2] = ((P_NUM>2)&&(HADDR>=P_HSEL2_START)&&(HADDR<P_HSEL2_END)) ? 1'b1 : 1'b0;
assign ihsel[3] = ((P_NUM>3)&&(HADDR>=P_HSEL3_START)&&(HADDR<P_HSEL3_END)) ? 1'b1 : 1'b0;
`ifdef RIGOR
// synthesis translate_off
initial begin
if (P_HSEL0_SIZE == 0) $display("%m ERROR P_HSEL0_SIZE should be positive 32-bit");
if (P_HSEL1_SIZE == 0) $display("%m ERROR P_HSEL1_SIZE should be positive 32-bit");
if (P_HSEL2_SIZE == 0) $display("%m ERROR P_HSEL2_SIZE should be positive 32-bit");
if (P_HSEL3_SIZE == 0) $display("%m ERROR P_HSEL3_SIZE should be positive 32-bit");
if ((P_HSEL0_END > P_HSEL1_START) && (P_HSEL0_END <= P_HSEL1_END))
$display("%m ERROR address range overlapped 0:1");
if ((P_HSEL0_END > P_HSEL2_START) && (P_HSEL0_END <= P_HSEL2_END))
$display("%m ERROR address range overlapped 0:2");
if ((P_HSEL0_END > P_HSEL3_START) && (P_HSEL0_END <= P_HSEL3_END))
$display("%m ERROR address range overlapped 0:3");
if ((P_HSEL1_END > P_HSEL0_START) && (P_HSEL1_END <= P_HSEL0_END))
$display("%m ERROR address range overlapped 1:0");
if ((P_HSEL1_END > P_HSEL2_START) && (P_HSEL1_END <= P_HSEL2_END))
$display("%m ERROR address range overlapped 1:2");
if ((P_HSEL1_END > P_HSEL3_START) && (P_HSEL1_END <= P_HSEL3_END))
$display("%m ERROR address range overlapped 1:3");
if ((P_HSEL2_END > P_HSEL0_START) && (P_HSEL2_END <= P_HSEL0_END))
$display("%m ERROR address range overlapped 2:0");
if ((P_HSEL2_END > P_HSEL1_START) && (P_HSEL2_END <= P_HSEL1_END))
$display("%m ERROR address range overlapped 2:1");
if ((P_HSEL2_END > P_HSEL3_START) && (P_HSEL2_END <= P_HSEL3_END))
$display("%m ERROR address range overlapped 2:3");
if ((P_HSEL3_END > P_HSEL0_START) && (P_HSEL3_END <= P_HSEL0_END))
$display("%m ERROR address range overlapped 3:0");
if ((P_HSEL3_END > P_HSEL1_START) && (P_HSEL3_END <= P_HSEL1_END))
$display("%m ERROR address range overlapped 3:1");
if ((P_HSEL3_END > P_HSEL2_START) && (P_HSEL3_END <= P_HSEL2_END))
$display("%m ERROR address range overlapped 3:2");
end
// synthesis translate_on
`endif
endmodule
| 7.159616 |
module ahb_s2m_s4 (
input wire HRESETn
, input wire HCLK
, input wire HSELd
, input wire HSEL0
, input wire HSEL1
, input wire HSEL2
, input wire HSEL3
, output reg [31:0] HRDATA
, output reg [ 1:0] HRESP
, output reg HREADY
, input wire [31:0] HRDATA0
, input wire [ 1:0] HRESP0
, input wire HREADY0
, input wire [31:0] HRDATA1
, input wire [ 1:0] HRESP1
, input wire HREADY1
, input wire [31:0] HRDATA2
, input wire [ 1:0] HRESP2
, input wire HREADY2
, input wire [31:0] HRDATA3
, input wire [ 1:0] HRESP3
, input wire HREADY3
, input wire [31:0] HRDATAd
, input wire [ 1:0] HRESPd
, input wire HREADYd
);
localparam D_HSEL0 = 5'h1;
localparam D_HSEL1 = 5'h2;
localparam D_HSEL2 = 5'h4;
localparam D_HSEL3 = 5'h8;
localparam D_HSELd = 5'h10;
wire [4:0] _hsel = {HSELd, HSEL3, HSEL2, HSEL1, HSEL0};
reg [4:0] _hsel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) _hsel_reg <= 5'h0;
else if (HREADY) _hsel_reg <= _hsel; // default HREADY must be 1'b1
end
always @(_hsel_reg or HREADYd or HREADY0 or HREADY1 or HREADY2 or HREADY3) begin
case (_hsel_reg)
D_HSEL0: HREADY = HREADY0;
D_HSEL1: HREADY = HREADY1;
D_HSEL2: HREADY = HREADY2;
D_HSEL3: HREADY = HREADY3;
D_HSELd: HREADY = HREADYd;
default: HREADY = 1'b1;
endcase
end
always @(_hsel_reg or HRDATAd or HRDATA0 or HRDATA1 or HRDATA2 or HRDATA3) begin
case (_hsel_reg)
D_HSEL0: HRDATA = HRDATA0;
D_HSEL1: HRDATA = HRDATA1;
D_HSEL2: HRDATA = HRDATA2;
D_HSEL3: HRDATA = HRDATA3;
D_HSELd: HRDATA = HRDATAd;
default: HRDATA = 32'b0;
endcase
end
always @(_hsel_reg or HRESPd or HRESP0 or HRESP1 or HRESP2 or HRESP3) begin
case (_hsel_reg)
D_HSEL0: HRESP = HRESP0;
D_HSEL1: HRESP = HRESP1;
D_HSEL2: HRESP = HRESP2;
D_HSEL3: HRESP = HRESP3;
D_HSELd: HRESP = HRESPd;
default: HRESP = 2'b01; //`HRESP_ERROR;
endcase
end
endmodule
| 7.097077 |
module ahb_default_slave (
input wire HRESETn
, input wire HCLK
, input wire HSEL
, input wire [31:0] HADDR
, input wire [ 1:0] HTRANS
, input wire HWRITE
, input wire [ 2:0] HSIZE
, input wire [ 2:0] HBURST
, input wire [31:0] HWDATA
, output wire [31:0] HRDATA
, output reg [ 1:0] HRESP = 2'b01
, input wire HREADYin
, output reg HREADYout = 1'b1
);
assign HRDATA = 32'h0;
localparam STH_IDLE = 2'h0, STH_WRITE = 2'h1, STH_READ0 = 2'h2;
reg [1:0] state = STH_IDLE;
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 0) begin
HRESP <= 2'b00; //`HRESP_OKAY;
HREADYout <= 1'b1;
state <= STH_IDLE;
end else begin // if (HRESETn==0) begin
case (state)
STH_IDLE: begin
if (HSEL && HREADYin) begin
case (HTRANS)
//`HTRANS_IDLE, `HTRANS_BUSY: begin
2'b00, 2'b01: begin
HREADYout <= 1'b1;
HRESP <= 2'b00; //`HRESP_OKAY;
state <= STH_IDLE;
end // HTRANS_IDLE or HTRANS_BUSY
//`HTRANS_NONSEQ, `HTRANS_SEQ: begin
2'b10, 2'b11: begin
HREADYout <= 1'b0;
HRESP <= 2'b01; //`HRESP_ERROR;
if (HWRITE) begin
state <= STH_WRITE;
end else begin
state <= STH_READ0;
end
end // HTRANS_NONSEQ or HTRANS_SEQ
endcase // HTRANS
end else begin // if (HSEL && HREADYin)
HREADYout <= 1'b1;
HRESP <= 2'b00; //`HRESP_OKAY;
end
end // STH_IDLE
STH_WRITE: begin
HREADYout <= 1'b1;
HRESP <= 2'b01; //`HRESP_ERROR;
state <= STH_IDLE;
end // STH_WRITE
STH_READ0: begin
HREADYout <= 1'b1;
HRESP <= 2'b01; //`HRESP_ERROR;
state <= STH_IDLE;
end // STH_READ0
endcase // state
end // if (HRESETn==0)
end // always
endmodule
| 6.712259 |
module address_decoder (
HSEL,
HADDR_DEC
);
//----------------------------I/O PORTS DECLARATIONS--------------------------------------//
output [2:0] HSEL; //3 slaves HSEL[1],HSEL[2],HSEL[3]
input [31:0] HADDR_DEC; //32bit slave address
parameter hsel_1_addr = 8'b00_00_00_00; //pre configured high order (8 bits or 1 byte) address for slave 1
parameter hsel_2_addr = 8'b00_00_00_01; //pre comfigured high order (8 bits or 1 byte) address for slave 2
parameter hsel_3_addr = 8'b00_00_00_10; //pre comfigured high order (8 bits or 1 byte) address for slave 3
assign HSEL[0] = (HADDR_DEC[31:24] == hsel_1_addr) ? 1'b1 : 1'b0;
assign HSEL[1] = (HADDR_DEC[31:24] == hsel_2_addr) ? 1'b1 : 1'b0;
assign HSEL[2] = (HADDR_DEC[31:24] == hsel_3_addr) ? 1'b1 : 1'b0;
endmodule
| 7.247981 |
module address_control_mux (
HADDR_MUX,
HADDR_M1,
HADDR_M2,
HGRANT
);
output [31:0] HADDR_MUX;
input [31:0] HADDR_M1, HADDR_M2;
input HGRANT;
assign HADDR_MUX = (HGRANT == 1'b1) ? HADDR_M1 : HADDR_M2; //2:1 MUX with HGRANT as Select Line
endmodule
| 8.472432 |
module amba_apb (
pclk,
preset,
psel,
penable,
pwrite,
paddr,
pwdata,
prdata,
pready
);
input pclk; // clock signal
input preset; // 1bit reset signal
input psel; // 1bit select signal
input penable; // 1bit enable signal
input pwrite; // direction signal (1=write/0=read)
input [0:31] paddr; // 32 bit address bus
input [0:31] pwdata; // 32 bit wire data bus
output reg [0:31] prdata; // 32 bit read data bus
input pready; // ready signal
reg [0:1] state, next; //2 bit state change variable
parameter idle = 2'b00; //initial idle state
parameter setup = 2'b01; //data is made stable in this state to be accessed in the next
parameter access = 2'b10; //data is accessed in this state
reg [0:31] pwdata_temp; //temp reg to store data to be written
reg temp_psel;
reg temp_penable;
always @(posedge pclk or negedge preset)
if (!preset) state <= idle;
else state <= next;
always @(state or preset or psel or penable or pwrite or paddr or pwdata) begin
case (state)
idle: begin
temp_psel = 1'b0;
temp_penable = 1'b0;
if (psel == 1) next = setup;
else next = idle;
end
setup: begin
temp_psel = 1'b1;
temp_penable = 1'b0;
pwdata_temp = 32'h0;
next = access;
end
access: begin
if (pwrite == 1 && penable == 1) begin
pwdata_temp = pwdata;
next = idle;
end else if (pwrite == 0 && penable == 1) begin
//prdata=32'haa;
prdata = pwdata_temp;
next = idle;
end else next = idle;
end
endcase
end
endmodule
| 8.345971 |
module amba_apb (
pclk,
preset,
psel,
penable,
pwrite,
paddr,
pwdata,
prdata,
pready
);
input pclk; // clock signal
input preset; // reset signal
input psel; // select signal
input penable; // enable signal
input pwrite; // direction signal
input [0:31] paddr; // 32 bit address bus
input [0:31] pwdata; // 32 bit wire data bus
output reg [0:31] prdata; // 32 bit read data bus
input pready; // ready signal
reg [0:1] state, next;
parameter idle = 2'b00;
parameter setup = 2'b01;
parameter access = 2'b10;
reg p_sel;
reg p_enable;
reg p_write;
reg [0:31] p_addr;
reg [0:31] p_wdata;
reg p_ready;
always @(posedge pclk or negedge preset)
if (!preset) state <= idle;
else state <= next;
always @(state, psel, penable, pwrite, paddr, pwdata, pready) begin
case (state)
idle: begin
p_sel = 0;
p_enable = 0;
next = setup;
end
setup: begin
p_sel = #2 1'b1; //SETUP state starts
p_enable = 0;
p_addr = 32'hff;
p_write = 0;
p_wdata = 32'haa;
next = access;
end
access: begin
p_sel = 1'b1;
p_enable = #2 1'b1; //access starts
end
endcase
end
endmodule
| 8.345971 |
module amba_apb_top ();
wire [0:31] prdata;
reg pclk, preset, psel, penable, pwrite, pready;
reg [0:31] paddr, pwdata;
amba_apb AMBA_APB (
pclk,
preset,
psel,
penable,
pwrite,
paddr,
pwdata,
prdata,
pready
);
initial begin
pclk = 0;
psel = 0;
penable = 0;
preset = 1;
paddr = 0;
pwdata = 0;
#2 preset = 0;
#1 preset = 1;
end
initial begin
//write cycle inputs
#14 psel = 1;
paddr = 8'h60;
penable = 0;
pwrite = 1;
pwdata = 32'haa;
#10 penable = 1;
//idle state inputs
#12 paddr = 0;
pwdata = 0;
pwrite = 0;
pwdata = 32'hz;
//read cycle inputs
#8 psel = 1;
paddr = 8'h60;
penable = 0;
pwrite = 0;
#10 penable = 1;
//idle state inputs after read cycle
#12 penable = 0;
psel = 0;
paddr = 0;
pwdata = 0;
pwrite = 0;
end
always #5 pclk = ~pclk;
endmodule
| 7.540293 |
module axi_arbiter_stom_s3 #(
parameter NUM = 3
) // num of slaves
(
input wire ARESETn
, input wire ACLK
//-----------------------------------------------------------
, input wire [NUM:0] BSELECT // selected by comparing trans_id
, input wire [NUM:0] BVALID
, input wire [NUM:0] BREADY
, output wire [NUM:0] BGRANT
//-----------------------------------------------------------
, input wire [NUM:0] RSELECT // selected by comparing trans_id
, input wire [NUM:0] RVALID
, input wire [NUM:0] RREADY
, input wire [NUM:0] RLAST
, output wire [NUM:0] RGRANT
);
//-----------------------------------------------------------
// read-data arbiter
//-----------------------------------------------------------
reg [NUM:0] rgrant_reg;
//-----------------------------------------------------------
localparam STR_RUN = 'h0, STR_WAIT = 'h1;
reg stateR = STR_RUN;
always @(posedge ACLK or negedge ARESETn) begin
if (ARESETn == 1'b0) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end else begin
case (stateR)
STR_RUN: begin
if (|RGRANT) begin
if (~|(RGRANT & RREADY & RLAST)) begin
rgrant_reg <= RGRANT;
stateR <= STR_WAIT;
end
end
end // STR_RUN
STR_WAIT: begin
if (|(RGRANT & RVALID & RREADY & RLAST)) begin
rgrant_reg <= 'h0;
stateR <= STR_RUN;
end
end // STR_WAIT
endcase
end
end
//-----------------------------------------------------------
assign RGRANT = (stateR == STR_RUN) ? priority_sel(RSELECT & RVALID) : rgrant_reg;
//-----------------------------------------------------------
// write-response arbiter
//-----------------------------------------------------------
reg [NUM:0] bgrant_reg;
localparam STB_RUN = 'h0, STB_WAIT = 'h1;
reg stateB = STB_RUN;
always @(posedge ACLK or negedge ARESETn) begin
if (ARESETn == 1'b0) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end else begin
case (stateB)
STB_RUN: begin
if (|BGRANT) begin
if (~|(BGRANT & BREADY)) begin
bgrant_reg <= BGRANT;
stateB <= STB_WAIT;
end
end
end // STB_RUN
STB_WAIT: begin
if (|(BGRANT & BVALID & BREADY)) begin
bgrant_reg <= 'h0;
stateB <= STB_RUN;
end
end // STB_WAIT
endcase
end
end
//-----------------------------------------------------------
assign BGRANT = (stateB == STB_RUN) ? priority_sel(BSELECT & BVALID) : bgrant_reg;
//-----------------------------------------------------------
function [NUM:0] priority_sel;
input [NUM:0] request;
begin
casex (request)
4'bxxx1: priority_sel = 4'h1;
4'bxx10: priority_sel = 4'h2;
4'bx100: priority_sel = 4'h4;
4'b1000: priority_sel = 4'h8;
default: priority_sel = 4'h0;
endcase
end
endfunction
//-----------------------------------------------------------
endmodule
| 7.648984 |
module amba__write_channel (
input clk,
reset,
input [5:0] m2i_AWID, // ID of the slave to wchich data has to be written
input [32:0] m2i_AWADDR, // Starting Address of the periphera whose ID is transferred
input [3:0] m2i_AWLEN, // Maximum 8 burst at a time
input [3:0] m2i_AWSIZE, // Maximum size of each burst is 1 Byte
input [1:0] m2i_AWBURST, // Defines the next write address calculation
input m2i_AWVALID, // Master sends this signal if the the address being sent is valid.
input [3:0] m2i_WID, // Maximum 8 words(Bursts) transferred in one transaction
input [7:0] m2i_WDATA, // Maximum size of data
input m2i_WSTRB, // Becomes 1 and the becomes 0 sfter each burst transfer
input m2i_WLAST, //gets active when the last byte of a burst get transfered
input m2i_WVALID, // Becomes 1 when the master sends valid data
input m2i_BREADY, // Master can accept a write response
output reg i2m_WREADY,
output reg i2m_BID,
output reg i2m_BVALID,
output reg i2m_BRESP
);
reg [5:0] m2i_AWID_reg;
reg [3:0] m2i_AWLEN_reg;
reg [32:0] m2i_AWADDR_reg;
reg [3:0] m2i_AWSIZE_reg;
reg [1:0] m2i_AWBURST_reg;
reg m2i_AWVALID_reg;
reg [3:0] m2i_WID_reg;
reg [7:0] m2i_WDATA_reg;
reg m2i_WSTRB_reg;
reg m2i_WVALID_reg;
reg m2i_BREADY_reg;
reg [7:0] data_reg[0:7]; // Memory element to store all the incoming data
reg [7:0] count = 0;
reg FLAG = 0;
always @(posedge clk) begin
if (reset) begin
m2i_AWID_reg = 0;
m2i_AWLEN_reg = 0;
m2i_AWADDR_reg = 0;
m2i_AWSIZE_reg = 0;
m2i_AWBURST_reg = 0;
m2i_AWVALID_reg = 0;
m2i_WID_reg = 0;
m2i_WDATA_reg = 0;
m2i_WSTRB_reg = 0;
m2i_WVALID_reg = 0;
m2i_BREADY_reg = 0;
i2m_WREADY = 0;
//count=0;
end else begin
m2i_AWID_reg = m2i_AWID;
m2i_AWADDR_reg = m2i_AWADDR;
m2i_AWLEN_reg = m2i_AWLEN;
m2i_AWSIZE_reg = m2i_AWSIZE;
m2i_AWBURST_reg = m2i_AWBURST;
m2i_AWVALID_reg = m2i_AWVALID;
m2i_WID_reg = m2i_WID;
m2i_WDATA_reg = m2i_WDATA;
m2i_WSTRB_reg = m2i_WSTRB;
m2i_WVALID_reg = m2i_WVALID;
m2i_BREADY_reg = m2i_BREADY;
count = 0;
i2m_WREADY = 1; //interface write-ready
//FLAG=1 when wlast pulse is sent
end
end
always @(posedge i2m_WREADY) begin
if (m2i_AWVALID && m2i_WVALID) begin
data_reg[count] = m2i_WDATA;
end
end
always @(negedge m2i_WSTRB) begin
if (m2i_AWVALID && m2i_WVALID && i2m_WREADY == 1) begin
count = count + 1;
data_reg[count] = m2i_WDATA;
end
end
always @(posedge m2i_WLAST) begin
FLAG = 1;
end
always @(posedge clk) begin
if (m2i_BREADY == 1) begin
i2m_BID = m2i_WID_reg;
i2m_BVALID = 1;
if (FLAG == 1) i2m_BRESP = 1;
end
end
endmodule
| 8.584265 |
module generic_sram_byte_en #(
parameter DATA_WIDTH = 32,
parameter ADDRESS_WIDTH = 4
) (
input i_clk,
input [ DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
input [ DATA_WIDTH/8-1:0] i_byte_enable,
output reg [ DATA_WIDTH-1:0] o_read_data
);
reg [DATA_WIDTH-1:0] mem[0:2**ADDRESS_WIDTH-1];
integer i;
always @(posedge i_clk) begin
// read
o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
// write
if (i_write_enable)
for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin
mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0];
mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1];
mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2];
mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3];
mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4];
mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5];
mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6];
mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7];
end
end
endmodule
| 7.001881 |
module AmbientLightSensorDemo (
input wire clk,
input wire rst,
input wire oe,
input wire trigger,
input wire sdata,
output wire cs,
output wire sclk,
output wire done
);
wire [31:0] data;
wire not_oe;
wire not_trigger;
assign not_oe = ~oe;
assign not_trigger = ~trigger;
AmbientLightSensor U0 (
.clk(clk),
.rst(rst),
.oe(not_oe),
.trigger(not_trigger),
.sdata(sdata),
.sclk(sclk),
.cs(cs),
.done(done),
.data(data)
);
endmodule
| 6.501672 |
module AmbientLightSensor (
input wire clk,
input wire rst,
input wire oe, // output enable
input wire trigger, // trigger/start ADC conversion
input wire sdata, // ADC serial data output
output reg sclk, // ADC serial clock driver
output reg cs, // ADC chip select
output reg done, // done flag when ADC conversion and serial transfer has completed
inout wire [7:0] data
);
// ==================================
//// Internal Parameter Field
// ==================================
parameter IDLE = 0;
parameter ACQUIRE_DATA = 1;
parameter CLOCK_WAIT = 2;
parameter LATCH_DATA = 3;
parameter CLOCK_DIVIDER = 500; // 10Mhz -> 100Khz
// ==================================
//// Registers
// ==================================
reg [15:0] out;
reg [15:0] shift_in;
reg [ 3:0] counter;
reg [ 3:0] clk_counter;
reg [ 1:0] state;
// ==================================
//// Wires
// ==================================
// ==================================
//// Wire Assignments
// ==================================
assign data = oe ? out[7:0] : 8'bz;
// ==================================
//// Modules
// ==================================
// ==================================
//// Behavioral Block
// ==================================
always @(posedge clk or posedge rst) begin
if (rst) begin
out = 0;
counter = 0;
state = IDLE;
clk_counter = 0;
done = 0;
sclk = 0;
shift_in = 0;
end else begin
case (state)
IDLE: begin
if (trigger) begin
counter = 0;
done = 0;
cs = 0;
state = ACQUIRE_DATA;
end
end
ACQUIRE_DATA: begin
if (counter == 16) begin
state = LATCH_DATA;
end else begin
counter = counter + 1;
clk_counter = 0;
shift_in = {shift_in[14:1], sdata};
state = CLOCK_WAIT;
end
end
CLOCK_WAIT: begin
if (clk_counter >= CLOCK_DIVIDER * 2) begin
state = ACQUIRE_DATA;
end else if (clk_counter >= CLOCK_DIVIDER) begin
sclk = 1;
end else begin
sclk = 0;
end
clk_counter = clk_counter + 1;
end
LATCH_DATA: begin
cs = 0;
done = 1;
out = shift_in;
state = IDLE;
end
endcase
end
end
endmodule
| 6.501672 |
module music (
clk,
speaker
);
input clk;
output speaker;
parameter clkdivider = 25000000 / 440 / 2;
reg [23:0] tone;
always @(posedge clk) tone <= tone + 1;
reg [14:0] counter;
always @(posedge clk)
if (counter == 0) counter <= (tone[23] ? clkdivider - 1 : clkdivider / 2 - 1);
else counter <= counter - 1;
reg speaker;
always @(posedge clk) if (counter == 0) speaker <= ~speaker;
endmodule
| 6.77205 |
module amc7823 #(
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 16,
parameter SPIMODE = "passthrough"
) (
output ss,
input miso,
output mosi,
output sclk,
input clk,
input spi_start,
output spi_busy, // For handshaking; can be ignored
input [ADDR_WIDTH-1:0] spi_addr,
input spi_read,
input [DATA_WIDTH-1:0] spi_data,
output [ADDR_WIDTH-1:0] sdo_addr,
output [DATA_WIDTH-1:0] spi_rdbk,
output spi_ready,
output sdio_as_sdo,
input sclk_in,
input mosi_in,
output miso_out,
input ss_in,
input spi_ssb_in,
output spi_ssb_out
);
// pin ss is IO_L18N_T2_32 bank 32 bus_digitizer_U15[2] AB20
// pin miso is IO_L18P_T2_32 bank 32 bus_digitizer_U15[1] AB19
// pin mosi is IO_L23N_T3_32 bank 32 bus_digitizer_U18[3] V19
// pin sclk is IO_L17N_T2_34 bank 34 bus_digitizer_U18[4] Y5
wire sclk_7823, mosi_7823;
wire miso_7823, ss_7823;
generate
if (SPIMODE == "passthrough") begin : passthrough
assign sclk = sclk_in;
assign mosi = mosi_in;
assign ss = ss_in;
assign miso_out = miso;
end else if (SPIMODE == "chain") begin : no_passthrough
assign sclk = spi_ssb_in ? sclk_7823 : sclk_in;
assign mosi = spi_ssb_in ? mosi_7823 : mosi_in;
assign ss = ss_7823;
assign miso_7823 = miso;
end else if (SPIMODE == "standalone") begin
assign sclk = sclk_7823;
assign mosi = mosi_7823;
assign ss = ss_7823;
assign miso_7823 = miso;
end
endgenerate
wire start_7823 = spi_start;
assign spi_ssb_out = spi_ssb_in & ss;
spi_master #(
.TSCKHALF(16),
.ADDR_WIDTH(16),
.DATA_WIDTH(16),
.SCK_RISING_SHIFT(1)
) amc7823_spi (
.cs(ss_7823),
.sck(sclk_7823),
.sdi(mosi_7823),
.sdo(miso_7823),
.clk(clk),
.spi_start(start_7823),
.spi_busy(spi_busy),
.spi_read(spi_read),
.spi_addr(spi_addr),
.spi_data(spi_data),
.sdo_addr(sdo_addr),
.spi_rdbk(spi_rdbk),
.spi_ready(spi_ready),
.sdio_as_sdo(sdio_as_sdo)
);
endmodule
| 7.256599 |
module amc7823_sim (
input ss,
output miso,
input mosi,
input sclk
);
// pin ss is IO_L18N_T2_32 bank 32 bus_digitizer_U15[2] AB20
// pin miso is IO_L18P_T2_32 bank 32 bus_digitizer_U15[1] AB19
// pin mosi is IO_L23N_T3_32 bank 32 bus_digitizer_U18[3] V19
// pin sclk is IO_L17N_T2_34 bank 34 bus_digitizer_U18[4] Y5
reg value = 0;
always @(posedge sclk) begin
value <= ~value;
end
assign miso = value;
endmodule
| 6.79974 |
module amf (
dataOut,
addrOut,
addrIn,
filterF,
dataIn,
M,
N,
filterEn,
clk,
rst
);
// Parameter
parameter DATA_WIDTH = 8, ADDR_WIDTH = 8, WINDOW_N = 2, T1 = 0, T2 = 255;
parameter WINDOW_W = 2 * WINDOW_N + 1; // Window's width : W = 2n + 1
parameter WINDOW_S = WINDOW_W * WINDOW_W; // Window's Size : S = W * W
parameter WINDOW_BITS = WINDOW_S * DATA_WIDTH; // Window's Bits : BITS = S * DATA_WIDTH
parameter WINDOW_CENTER = WINDOW_S / 2; // Window's Center Pixel Location : CENTER = S / 2
// Outputs
output wire [DATA_WIDTH - 1 : 0] dataOut;
output reg [ADDR_WIDTH - 1 : 0] addrOut;
output wire filterF;
output wire [ADDR_WIDTH - 1 : 0] addrIn;
// Inputs
input wire [DATA_WIDTH - 1 : 0] dataIn;
input wire [15 : 0] M, N;
input wire filterEn, clk, rst;
// Registers
// Wires
wire [ADDR_WIDTH - 1 : 0] addrP;
wire [WINDOW_BITS - 1 : 0] pack_w, pack_wBuffer;
wire [DATA_WIDTH - 1 : 0] wCenter, min3, med3, max3, min5, med5, max5, f;
wire nextPixel, windowF, lastPixelF, WBT, noiseF;
// Instantiation of modules
slider #(
.ADDR_WIDTH(ADDR_WIDTH)
) slider0 (
addrP,
lastPixelF,
nextPixel,
M,
N,
clk,
rst
);
window #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.WINDOW_N (`WINDOW_N)
) window0 (
pack_w,
addrIn,
windowF,
dataIn,
addrP,
N,
clk,
rst
);
windowBuffer #(
.WINDOW_BITS(WINDOW_BITS),
.DATA_WIDTH(DATA_WIDTH),
.CENTER(WINDOW_CENTER)
) windowBuffer0 (
pack_wBuffer,
wCenter,
pack_w,
WBT
);
noiseDetection #(
.DATA_WIDTH(DATA_WIDTH),
.T1(T1),
.T2(T2)
) noiseDetection0 (
noiseF,
wCenter
);
median #(
.WINDOW_BITS(WINDOW_BITS),
.WINDOW_S(WINDOW_S),
.DATA_WIDTH(DATA_WIDTH)
) median0 (
min3,
med3,
max3,
min5,
med5,
max5,
pack_wBuffer
);
adaptive #(
.DATA_WIDTH(DATA_WIDTH)
) adaptive0 (
f,
min3,
med3,
max3,
min5,
med5,
max5,
wCenter
);
outputSelection #(
.DATA_WIDTH(DATA_WIDTH)
) outputSelection0 (
dataOut,
wCenter,
f,
noiseF
);
// Dataflow Description
assign nextPixel = filterEn & windowF;
assign WBT = lastPixelF | windowF;
assign filterF = lastPixelF;
// Behavioral Description
always @(posedge nextPixel) addrOut = addrP;
endmodule
| 8.560382 |
module amiga_clk (
input clk_28, // 28MHz output clock ( 28.375160MHz)
output clk7_en, // 7MHz output clock enable (on 28MHz clock domain)
output clk7n_en, // 7MHz negedge output clock enable (on 28MHz clock domain)
output reg c1, // clk28m clock domain signal synchronous with clk signal
output reg c3, // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
output reg cck, // colour clock output (3.54 MHz)
output [9:0] eclk, // 0.709379 MHz clock enable output (clk domain pulse)
input reset_n
);
//// generated clocks ////
// 7MHz
reg [1:0] clk7_cnt = 2'b10;
reg clk7_en_reg = 1'b1;
reg clk7n_en_reg = 1'b1;
reg [9:0] shifter;
always @(posedge clk_28, negedge reset_n) begin
if (!reset_n) begin
clk7_cnt <= 2'b10;
clk7_en_reg <= 1'b1;
clk7n_en_reg <= 1'b1;
cck <= 1;
shifter <= 1;
end else begin
clk7_cnt <= clk7_cnt + 2'b01;
clk7_en_reg <= (clk7_cnt == 2'b00);
clk7n_en_reg <= (clk7_cnt == 2'b10);
if (clk7_cnt == 2'b01) begin
cck <= ~cck;
shifter <= {shifter[8:0], shifter[9]};
if (!shifter) shifter <= 1;
end
end
end
wire clk_7 = clk7_cnt[1];
assign clk7_en = clk7_en_reg;
assign clk7n_en = clk7n_en_reg;
// amiga clocks & clock enables
// __ __ __ __ __
// clk_28 __/ \__/ \__/ \__/ \__/
// ___________ __
// clk_7 __/ \___________/
// ___________ __
// c1 __/ \___________/ <- clk28m domain
// ___________
// c3 ________/ \________ <- clk28m domain
//
// clk_28 clock domain signal synchronous with clk signal delayed by 90 degrees
always @(posedge clk_28) c3 <= clk_7;
// clk28m clock domain signal synchronous with clk signal
always @(posedge clk_28) c1 <= ~c3;
// 0.709379 MHz clock enable output (clk domain pulse)
assign eclk = shifter;
endmodule
| 8.114158 |
module amiga_clk_xilinx (
input wire areset,
input wire inclk0,
output wire c0,
output wire c1,
output wire c2,
output wire locked
);
// internal wires
wire pll_114;
wire dll_114;
wire dll_28;
reg [1:0] clk_7 = 0;
// pll
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(17), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(29), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(15.015), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) pll (
.CLKIN(inclk0), // Clock input (from IBUFG, BUFG or DCM)
.CLKFX(pll_114) // DCM CLK synthesis out (M/D) (113.611765 MHz)
);
// dll
DCM #(
.CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(8.802), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("FIXED"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(104), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) dll (
.RST(areset),
.CLKIN(pll_114), // Clock input (from IBUFG, BUFG or DCM)
.CLK0(dll_114),
.CLKDV(dll_28),
.CLKFB(c0),
.LOCKED(locked)
);
// 7MHz clock
always @(posedge c1) begin
clk_7 <= #1 clk_7 + 2'd1;
end
// global clock buffers
BUFG BUFG_SDR (
.I(pll_114),
.O(c2)
);
BUFG BUFG_114 (
.I(dll_114),
.O(c0)
);
BUFG BUFG_28 (
.I(dll_28),
.O(c1)
);
//BUFG BUFG_7 (.I(clk_7[1]), .O(c3));
endmodule
| 7.447877 |
module amm_master_qsys_with_pcie_altpll_qsys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial dffe4a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~sclr));
// synopsys translate_off
initial dffe5a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~sclr));
// synopsys translate_off
initial dffe6a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~sclr));
assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0;
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_altpll_qsys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
amm_master_qsys_with_pcie_altpll_qsys_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q)
);
assign dout = wire_dffpipe3_q;
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_altpll_qsys (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
amm_master_qsys_with_pcie_altpll_qsys_stdsync_sv6 stdsync2 (
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~reset))
);
amm_master_qsys_with_pcie_altpll_qsys_altpll_drn2 sd1 (
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked)
);
// synopsys translate_off
initial pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @(posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial prev_reset = 0;
// synopsys translate_on
always @(posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
c2 = wire_sd1_clk[2],
c3 = wire_sd1_clk[3],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {
{30{1'b0}},
(read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))),
(read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))
},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~address[1]) & address[0]),
w_select_status = ((~address[1]) & (~address[0]));
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie (
clk_clk,
reset_reset_n,
pcie_ip_reconfig_togxb_data,
pcie_ip_refclk_export,
pcie_ip_test_in_test_in,
pcie_ip_pcie_rstn_export,
pcie_ip_clocks_sim_clk250_export,
pcie_ip_clocks_sim_clk500_export,
pcie_ip_clocks_sim_clk125_export,
pcie_ip_reconfig_busy_busy_altgxb_reconfig,
pcie_ip_pipe_ext_pipe_mode,
pcie_ip_pipe_ext_phystatus_ext,
pcie_ip_pipe_ext_rate_ext,
pcie_ip_pipe_ext_powerdown_ext,
pcie_ip_pipe_ext_txdetectrx_ext,
pcie_ip_pipe_ext_rxelecidle0_ext,
pcie_ip_pipe_ext_rxdata0_ext,
pcie_ip_pipe_ext_rxstatus0_ext,
pcie_ip_pipe_ext_rxvalid0_ext,
pcie_ip_pipe_ext_rxdatak0_ext,
pcie_ip_pipe_ext_txdata0_ext,
pcie_ip_pipe_ext_txdatak0_ext,
pcie_ip_pipe_ext_rxpolarity0_ext,
pcie_ip_pipe_ext_txcompl0_ext,
pcie_ip_pipe_ext_txelecidle0_ext,
pcie_ip_rx_in_rx_datain_0,
pcie_ip_tx_out_tx_dataout_0,
pcie_ip_reconfig_fromgxb_0_data,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
altpll_sdram_clk,
pcie_ip_powerdown_pll_powerdown,
pcie_ip_powerdown_gxb_powerdown,
user_module_conduit_rdwr_cntl,
user_module_conduit_n_action,
user_module_conduit_add_data_sel,
user_module_conduit_rdwr_address,
user_module_conduit_debug_flag,
user_module_conduit_display_data
);
input clk_clk;
input reset_reset_n;
input [3:0] pcie_ip_reconfig_togxb_data;
input pcie_ip_refclk_export;
input [39:0] pcie_ip_test_in_test_in;
input pcie_ip_pcie_rstn_export;
output pcie_ip_clocks_sim_clk250_export;
output pcie_ip_clocks_sim_clk500_export;
output pcie_ip_clocks_sim_clk125_export;
input pcie_ip_reconfig_busy_busy_altgxb_reconfig;
input pcie_ip_pipe_ext_pipe_mode;
input pcie_ip_pipe_ext_phystatus_ext;
output pcie_ip_pipe_ext_rate_ext;
output [1:0] pcie_ip_pipe_ext_powerdown_ext;
output pcie_ip_pipe_ext_txdetectrx_ext;
input pcie_ip_pipe_ext_rxelecidle0_ext;
input [7:0] pcie_ip_pipe_ext_rxdata0_ext;
input [2:0] pcie_ip_pipe_ext_rxstatus0_ext;
input pcie_ip_pipe_ext_rxvalid0_ext;
input pcie_ip_pipe_ext_rxdatak0_ext;
output [7:0] pcie_ip_pipe_ext_txdata0_ext;
output pcie_ip_pipe_ext_txdatak0_ext;
output pcie_ip_pipe_ext_rxpolarity0_ext;
output pcie_ip_pipe_ext_txcompl0_ext;
output pcie_ip_pipe_ext_txelecidle0_ext;
input pcie_ip_rx_in_rx_datain_0;
output pcie_ip_tx_out_tx_dataout_0;
output [4:0] pcie_ip_reconfig_fromgxb_0_data;
output [11:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [31:0] sdram_dq;
output [3:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
output altpll_sdram_clk;
input pcie_ip_powerdown_pll_powerdown;
input pcie_ip_powerdown_gxb_powerdown;
input user_module_conduit_rdwr_cntl;
input user_module_conduit_n_action;
input user_module_conduit_add_data_sel;
input [27:0] user_module_conduit_rdwr_address;
output [15:0] user_module_conduit_debug_flag;
output [31:0] user_module_conduit_display_data;
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_reconf_registers (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "amm_master_qsys_with_pcie_reconf_registers.hex";
output [31:0] readdata;
input [6:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
reg [31:0] readdata;
wire [31:0] readdata_ram;
wire wren;
always @(posedge clk) begin
if (clken) readdata <= readdata_ram;
end
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata_ram),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=RCNF",
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 128,
the_altsyncram.numwords_a = 128, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 7;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [60:0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [60:0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1:0] entries;
reg [60:0] entry_0;
reg [60:0] entry_1;
wire full;
reg rd_address;
reg [60:0] rd_data;
wire [ 1:0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address) begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full) begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty) begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk) begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
output [68:0] m_readfifo_q;
output [4:0] m_readfifo_usedw;
input clk;
input [68:0] m_readfifo_data;
input m_readfifo_rdreq;
input m_readfifo_wrreq;
input reset;
wire m_readfifo_empty;
wire m_readfifo_full;
wire [68:0] m_readfifo_q;
wire [ 4:0] m_readfifo_usedw;
scfifo amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo (
.aclr(reset),
.clock(clk),
.data(m_readfifo_data),
.empty(m_readfifo_empty),
.full(m_readfifo_full),
.q(m_readfifo_q),
.rdreq(m_readfifo_rdreq),
.usedw(m_readfifo_usedw),
.wrreq(m_readfifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.add_ram_output_register
= "ON",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.intended_device_family =
"CYCLONEIVGX", amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_numwords =
32, amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_width = 69,
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_widthu = 5,
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.use_eab = "ON";
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
);
output m_writefifo_empty;
output m_writefifo_full;
output [68:0] m_writefifo_q;
output [8:0] m_writefifo_usedw;
input clk;
input [68:0] m_writefifo_data;
input m_writefifo_rdreq;
input m_writefifo_wrreq;
input reset;
wire m_writefifo_empty;
wire m_writefifo_full;
wire [68:0] m_writefifo_q;
wire [ 8:0] m_writefifo_usedw;
scfifo amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo (
.aclr(reset),
.clock(clk),
.data(m_writefifo_data),
.empty(m_writefifo_empty),
.full(m_writefifo_full),
.q(m_writefifo_q),
.rdreq(m_writefifo_rdreq),
.usedw(m_writefifo_usedw),
.wrreq(m_writefifo_wrreq)
);
defparam
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.add_ram_output_register =
"ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.intended_device_family =
"CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_numwords = 512,
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_showahead = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_width = 69,
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_widthu = 9,
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.use_eab = "ON";
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] command_fifo_q;
input clk;
input [103:0] command_fifo_data;
input command_fifo_rdreq;
input command_fifo_wrreq;
input reset;
wire command_fifo_empty;
wire command_fifo_full;
wire [103:0] command_fifo_q;
scfifo amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo (
.aclr(reset),
.clock(clk),
.data(command_fifo_data),
.empty(command_fifo_empty),
.full(command_fifo_full),
.q(command_fifo_q),
.rdreq(command_fifo_rdreq),
.wrreq(command_fifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.add_ram_output_register = "ON",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.intended_device_family =
"CYCLONEIVGX", amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_numwords = 2,
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_width = 104,
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_widthu = 1,
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.use_eab = "ON";
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output desc_address_fifo_full;
output [31:0] desc_address_fifo_q;
input clk;
input [31:0] desc_address_fifo_data;
input desc_address_fifo_rdreq;
input desc_address_fifo_wrreq;
input reset;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [31:0] desc_address_fifo_q;
scfifo amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo (
.aclr(reset),
.clock(clk),
.data(desc_address_fifo_data),
.empty(desc_address_fifo_empty),
.full(desc_address_fifo_full),
.q(desc_address_fifo_q),
.rdreq(desc_address_fifo_rdreq),
.wrreq(desc_address_fifo_wrreq)
);
defparam
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.add_ram_output_register =
"ON",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.intended_device_family =
"CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_width = 32,
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
endmodule
| 6.962337 |
module amm_master_qsys_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
output status_token_fifo_full;
output [23:0] status_token_fifo_q;
input clk;
input reset;
input [23:0] status_token_fifo_data;
input status_token_fifo_rdreq;
input status_token_fifo_wrreq;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [23:0] status_token_fifo_q;
scfifo amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo (
.aclr(reset),
.clock(clk),
.data(status_token_fifo_data),
.empty(status_token_fifo_empty),
.full(status_token_fifo_full),
.q(status_token_fifo_q),
.rdreq(status_token_fifo_rdreq),
.wrreq(status_token_fifo_wrreq)
);
defparam
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.add_ram_output_register =
"ON",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.intended_device_family =
"CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_numwords = 2,
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_width = 24,
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_widthu = 1,
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.use_eab = "ON";
endmodule
| 6.962337 |
module AMOALU (
input clock,
input reset,
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out,
output [63:0] io_out_unmasked
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd == 5'h8; // @[AMOALU.scala 66:20]
wire _T_4 = io_cmd == 5'ha; // @[AMOALU.scala 67:26]
wire logic_and = io_cmd == 5'ha | io_cmd == 5'hb; // @[AMOALU.scala 67:38]
wire logic_xor = io_cmd == 5'h9 | _T_4; // @[AMOALU.scala 68:39]
wire _T_9 = ~io_mask[3]; // @[AMOALU.scala 72:63]
wire [31:0] _T_10 = {_T_9, 31'h0}; // @[AMOALU.scala 72:79]
wire [63:0] _T_11 = {{32'd0}, _T_10}; // @[AMOALU.scala 72:98]
wire [63:0] _T_12 = ~_T_11; // @[AMOALU.scala 72:16]
wire [63:0] _T_13 = io_lhs & _T_12; // @[AMOALU.scala 73:13]
wire [63:0] _T_14 = io_rhs & _T_12; // @[AMOALU.scala 73:31]
wire [63:0] adder_out = _T_13 + _T_14; // @[AMOALU.scala 73:21]
wire [4:0] _T_18 = io_cmd & 5'h2; // @[AMOALU.scala 86:17]
wire _T_20 = _T_18 == 5'h0; // @[AMOALU.scala 86:25]
wire _T_32 = io_lhs[31:0] < io_rhs[31:0]; // @[AMOALU.scala 79:35]
wire _T_34 = io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & _T_32; // @[AMOALU.scala 80:38]
wire _T_37 = _T_20 ? io_lhs[63] : io_rhs[63]; // @[AMOALU.scala 88:58]
wire _T_38 = io_lhs[63] == io_rhs[63] ? _T_34 : _T_37; // @[AMOALU.scala 88:10]
wire _T_52 = _T_20 ? io_lhs[31] : io_rhs[31]; // @[AMOALU.scala 88:58]
wire _T_53 = io_lhs[31] == io_rhs[31] ? _T_32 : _T_52; // @[AMOALU.scala 88:10]
wire less = io_mask[4] ? _T_38 : _T_53; // @[Mux.scala 47:69]
wire _T_54 = less ? min : max; // @[AMOALU.scala 94:23]
wire [63:0] minmax = _T_54 ? io_lhs : io_rhs; // @[AMOALU.scala 94:19]
wire [63:0] _T_55 = io_lhs & io_rhs; // @[AMOALU.scala 96:27]
wire [63:0] _T_56 = logic_and ? _T_55 : 64'h0; // @[AMOALU.scala 96:8]
wire [63:0] _T_57 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27]
wire [63:0] _T_58 = logic_xor ? _T_57 : 64'h0; // @[AMOALU.scala 97:8]
wire [63:0] logic_ = _T_56 | _T_58; // @[AMOALU.scala 96:42]
wire [63:0] _T_60 = logic_and | logic_xor ? logic_ : minmax; // @[AMOALU.scala 100:8]
wire [63:0] out = add ? adder_out : _T_60; // @[AMOALU.scala 99:8]
wire [7:0] _T_70 = io_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_72 = io_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_74 = io_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_76 = io_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_78 = io_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_80 = io_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_82 = io_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_84 = io_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [63:0] wmask = {
_T_84, _T_82, _T_80, _T_78, _T_76, _T_74, _T_72, _T_70
}; // @[Cat.scala 29:58]
wire [63:0] _T_91 = wmask & out; // @[AMOALU.scala 104:19]
wire [63:0] _T_92 = ~wmask; // @[AMOALU.scala 104:27]
wire [63:0] _T_93 = _T_92 & io_lhs; // @[AMOALU.scala 104:34]
assign io_out = _T_91 | _T_93; // @[AMOALU.scala 104:25]
assign io_out_unmasked = add ? adder_out : _T_60; // @[AMOALU.scala 99:8]
endmodule
| 8.467919 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apx2, ED=2
wire x1_xor_x2, x3_xor_x4, x1_and_x2, x3_and_x4, x1_or_x2, x3_or_x4;
assign x1_or_x2 = x1 | x2;
assign x3_or_x4 = x3 | x4;
assign x1_and_x2 = x1 & x2;
assign x3_and_x4 = x3 & x4;
assign x1_xor_x2 = x1 ^ x2;
assign x3_xor_x4 = x3 ^ x4;
assign summ = x1_xor_x2 ^ x3_xor_x4;
assign carry = x1_and_x2 | x3_and_x4 | (x1_or_x2 & x3_or_x4);
assign err = x1_and_x2 & x3_and_x4;
// apx4, ED=4
//wire x1_xor_x2 ,x3_xor_x4 ,x1_and_x2 ,x3_and_x4, x1_or_x2, x3_or_x4 ;
//assign x1_or_x2 = x1 | x2;
//assign x3_or_x4 = x3 | x4;
//assign x1_and_x2 = x1 & x2;
//assign x3_and_x4 = x3 & x4;
//assign x1_xor_x2 = x1 ^ x2;
//assign x3_xor_x4 = x3 ^ x4;
//
//assign summ = x1_xor_x2 ^ x3_xor_x4;
////assign carry = (x1_xor_x2 & x3_or_x4) | (~x1_or_x2 & x3_and_x4) | (x1_and_x2 & ~x3_and_x4);
////assign carry = (x1_xor_x2 & x3_or_x4) | ~x1&~x2&x3&x4 + x1&x2&~(x3&x4);
//assign carry = (x1_xor_x2 & x3_or_x4) | (x3_and_x4 ? ~x1_or_x2 : x1_and_x2);
//assign err = x1_and_x2 & x3_and_x4;
endmodule
| 7.233653 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
// in1, cin, t1
assign summ = x1 ^ cin ^ xor234;
assign carry = !(!(x1 & cin) & !(x1 & xor234) & !(cin & xor234));
endmodule
| 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
assign carry = cin & xor234;
assign summ = cin ^ xor234;
endmodule
| 7.725792 |
module cprs_4_2_apx1 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
assign err = x1 & x2 & x3 & x4;
assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
endmodule
| 7.110479 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apx2, ED=2
wire x1_xor_x2, x3_xor_x4, x1_and_x2, x3_and_x4, x1_or_x2, x3_or_x4;
assign x1_or_x2 = x1 | x2;
assign x3_or_x4 = x3 | x4;
assign x1_and_x2 = x1 & x2;
assign x3_and_x4 = x3 & x4;
assign x1_xor_x2 = x1 ^ x2;
assign x3_xor_x4 = x3 ^ x4;
assign summ = x1_xor_x2 ^ x3_xor_x4;
assign carry = x1_and_x2 | x3_and_x4 | (x1_or_x2 & x3_or_x4);
assign err = x1_and_x2 & x3_and_x4;
// apx4, ED=4
//wire x1_xor_x2 ,x3_xor_x4 ,x1_and_x2 ,x3_and_x4, x1_or_x2, x3_or_x4 ;
//assign x1_or_x2 = x1 | x2;
//assign x3_or_x4 = x3 | x4;
//assign x1_and_x2 = x1 & x2;
//assign x3_and_x4 = x3 & x4;
//assign x1_xor_x2 = x1 ^ x2;
//assign x3_xor_x4 = x3 ^ x4;
//
//assign summ = x1_xor_x2 ^ x3_xor_x4;
////assign carry = (x1_xor_x2 & x3_or_x4) | (~x1_or_x2 & x3_and_x4) | (x1_and_x2 & ~x3_and_x4);
////assign carry = (x1_xor_x2 & x3_or_x4) | ~x1&~x2&x3&x4 + x1&x2&~(x3&x4);
//assign carry = (x1_xor_x2 & x3_or_x4) | (x3_and_x4 ? ~x1_or_x2 : x1_and_x2);
//assign err = x1_and_x2 & x3_and_x4;
endmodule
| 7.233653 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
// in1, cin, t1
assign summ = x1 ^ cin ^ xor234;
assign carry = !(!(x1 & cin) & !(x1 & xor234) & !(cin & xor234));
endmodule
| 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
assign carry = cin & xor234;
assign summ = cin ^ xor234;
endmodule
| 7.725792 |
module cprs_4_2_apx2 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apx2, ED=2
wire x1_xor_x2, x3_xor_x4, x1_and_x2, x3_and_x4, x1_or_x2, x3_or_x4;
assign x1_or_x2 = x1 | x2;
assign x3_or_x4 = x3 | x4;
assign x1_and_x2 = x1 & x2;
assign x3_and_x4 = x3 & x4;
assign x1_xor_x2 = x1 ^ x2;
assign x3_xor_x4 = x3 ^ x4;
assign summ = x1_xor_x2 ^ x3_xor_x4;
assign carry = x1_and_x2 | x3_and_x4 | (x1_or_x2 & x3_or_x4);
assign err = x1_and_x2 & x3_and_x4;
// apx4, ED=4
//wire x1_xor_x2 ,x3_xor_x4 ,x1_and_x2 ,x3_and_x4, x1_or_x2, x3_or_x4 ;
//assign x1_or_x2 = x1 | x2;
//assign x3_or_x4 = x3 | x4;
//assign x1_and_x2 = x1 & x2;
//assign x3_and_x4 = x3 & x4;
//assign x1_xor_x2 = x1 ^ x2;
//assign x3_xor_x4 = x3 ^ x4;
//
//assign summ = x1_xor_x2 ^ x3_xor_x4;
////assign carry = (x1_xor_x2 & x3_or_x4) | (~x1_or_x2 & x3_and_x4) | (x1_and_x2 & ~x3_and_x4);
////assign carry = (x1_xor_x2 & x3_or_x4) | ~x1&~x2&x3&x4 + x1&x2&~(x3&x4);
//assign carry = (x1_xor_x2 & x3_or_x4) | (x3_and_x4 ? ~x1_or_x2 : x1_and_x2);
//assign err = x1_and_x2 & x3_and_x4;
endmodule
| 7.233653 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
// in1, cin, t1
assign summ = x1 ^ cin ^ xor234;
assign carry = !(!(x1 & cin) & !(x1 & xor234) & !(cin & xor234));
endmodule
| 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
assign carry = cin & xor234;
assign summ = cin ^ xor234;
endmodule
| 7.725792 |
module cprs_4_2_apxe4 (
input x1,
input x2,
input x3,
input x4,
output carry,
output summ,
output err
);
// apx1, ED=1
//assign err = x1 & x2 & x3 & x4;
//assign summ = (x1 ^ x2 ^ x3 ^ x4) | err;
//assign carry = ((x1 ^ x2) & (x3 ^ x4)) | ((x1 & x2) ^ (x3 & x4)) | err;
// apxe4, ED=4
wire x1_xor_x2, x3_xor_x4, x1_and_x2, x3_and_x4, x1_or_x2, x3_or_x4;
assign x1_or_x2 = x1 | x2;
assign x3_or_x4 = x3 | x4;
assign x1_and_x2 = x1 & x2;
assign x3_and_x4 = x3 & x4;
assign x1_xor_x2 = x1 ^ x2;
assign x3_xor_x4 = x3 ^ x4;
assign summ = x1_xor_x2 ^ x3_xor_x4;
//assign carry = (x1_xor_x2 & x3_or_x4) | (~x1_or_x2 & x3_and_x4) | (x1_and_x2 & ~x3_and_x4);
//assign carry = (x1_xor_x2 & x3_or_x4) | ~x1&~x2&x3&x4 + x1&x2&~(x3&x4);
assign carry = (x1_xor_x2 & x3_or_x4) | (x3_and_x4 ? ~x1_or_x2 : x1_and_x2);
assign err = x1_and_x2 & x3_and_x4;
endmodule
| 7.211389 |
module cprs_4_2_mfa (
input x1,
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
// in1, cin, t1
assign summ = x1 ^ cin ^ xor234;
assign carry = !(!(x1 & cin) & !(x1 & xor234) & !(cin & xor234));
endmodule
| 7.954498 |
module cprs_3_2_mfa (
input x2,
input x3,
input x4,
input cin,
output cout,
output carry,
output summ
);
wire xor234;
//assign {cout,s} = x1 + x2 + x3;
//assign {carry,summ} = cin + x4 + s;
assign xor234 = x2 ^ x3 ^ x4;
assign cout = !(!(x2 & x3) & !(x3 & x4) & !(x2 & x4));
assign carry = cin & xor234;
assign summ = cin ^ xor234;
endmodule
| 7.725792 |
module AMP (
input [1:0] divisor,
input [7:0] inp,
output [7:0] out
);
assign out = inp >> divisor;
endmodule
| 8.20315 |
modules: N/A
*- Description: Adjust the amplitude of a 10-bit digital signal
*-
*- Example of Usage:
- This code allows you to adjust the amplitude for a 10-bit digital signal. Most of the cases
you can connect this module directly to the digital sinusoidal wave generator 'sin_anyfreq'.
- The output of this module is also 10-bit, but by adjusting the parameter 'numerator' from 1 to 256
will set the amplitude from 1/256 (0.4%) to 256/256 (100%).
* - You can connect a parallel input 10 bit DAC to view the analog sinusoidal wave
- Or you can connect it to 'sigma2delta' to generate a 1-bit DAC using PDM.
* - Read more details in Chapter 5 of the tutorial book.
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module ampAdjust
#(parameter numerator = 256) // Divide the amplitude into 256 pieces, the amplitude resolution is 1/256
(
input clk,
input [9:0] digitalSignal,
output[9:0] dac_Data
);
reg [17:0] amp_data;
always @(posedge clk)
amp_data = digitalSignal * numerator;
assign dac_Data = amp_data[17:8]; // Take the 10 most significant bits; equaivlent to right shift 8 bits
endmodule
| 6.670404 |
module amplifier (
output reg [23:0] out_data,
output reg out_valid,
input [23:0] in_data,
input wren,
input clk,
input reset,
input [3:0] gain
);
always @(posedge clk or posedge reset)
if (reset) begin
out_data <= 0;
out_valid <= 1'b0;
end else if (wren) begin
casez (gain)
4'b1000: out_data <= 0;
4'b0000: out_data <= $signed(in_data);
default: out_data <= $signed(in_data) + ($signed(in_data) >>> 3) * $signed(gain);
endcase
out_valid <= 1'b1;
end else begin
out_data <= 0;
out_valid <= 1'b0;
end
endmodule
| 7.334477 |
module ampliTB ();
wire clk;
inverter #(5, 2) inv (
1'b1,
clk
);
reg rst;
reg cnt, ld;
wire co1, co2;
wire [3:0] out1, out2;
reg [12:0] SW;
wire [7:0] signal;
wire [7:0] signal_out;
reg clk_in;
initial begin
clk_in = 1'b0;
end
frequency_divider fre1 (
clk,
rst,
cnt,
ld || co2,
SW[3:0],
co1,
out1
);
frequency_divider fre2 (
co1,
rst,
cnt,
ld || co2,
SW[7:4],
co2,
out2
);
waveform_generator WG (
clk_in,
rst,
SW[10:8],
signal
);
amplitude ampli (
signal,
SW[12:11],
signal_out
);
always @(co2) begin
clk_in = co2 ? ~clk_in : clk_in;
end
initial begin
SW = 13'b0000000000011;
rst = 1'b0;
cnt = 1'b1;
#100 ld = 1'b1;
#500 ld = 1'b0;
///////////////
SW = 13'b0000000000011;
#5000000;
SW = 13'b0100000000011;
#5000000;
/////////////////
SW = 13'b1000100000011;
#5000000;
SW = 13'b0100100000011;
#5000000;
///////////////////
SW = 13'b1001000000011;
#5000000;
SW = 13'b1101000000011;
#5000000;
/////////////////
SW = 13'b0101100000011;
#5000000;
SW = 13'b1001100000011;
#5000000;
////////////////
SW = 13'b0101000000011;
#5000000;
SW = 13'b0001000000011;
#5000000;
///////////////////
SW = 13'b0110100000011;
#5000000;
SW = 13'b1010100000011;
#5000000;
///////////////////
SW = 13'b0111000000011;
#5000000;
SW = 13'b11111000000011;
#5000000;
/////////////////////
#100000 $stop;
end
endmodule
| 6.701225 |
module amplitude (
input [7:0] signal_in,
input [1:0] am,
output [7:0] signal_out
);
assign signal_out = (am == 2'b00) ? (signal_in >>> 1) :
(am == 2'b01) ? (signal_in >>> 2) :
(am == 2'b10) ? (signal_in >>> 3) :
(am == 2'b11) ? (signal_in >>> 4) : signal_in;
endmodule
| 7.443866 |
module AmplitudeSelector (
input [1:0] select,
input [7:0] in,
output [7:0] out
);
assign out = in >> select;
endmodule
| 7.783462 |
module amplitude_adjust (
input clk,
input [9:0] amplitude,
input signed [11:0] ast_sink_data,
input ast_sink_valid,
input [1:0] ast_sink_error,
output signed [11:0] ast_source_data,
output reg ast_source_valid,
output reg [1:0] ast_source_error
);
//
reg signed [21:0] signed_result;
// Keep sign bit
// Drop bit created by conversion of unsigned amplitude
assign ast_source_data = {signed_result[21], signed_result[19:9]};
always @(posedge clk) begin
signed_result <= $signed(ast_sink_data) * $signed({1'b0, amplitude});
ast_source_valid <= ast_sink_valid;
ast_source_error <= ast_sink_error;
end
endmodule
| 8.752326 |
module Amplitude_selector (
amp_sel,
amp_in,
amp_out
);
input [1:0] amp_sel;
input [7:0] amp_in;
output [7:0] amp_out;
assign amp_out = amp_in >> amp_sel;
endmodule
| 7.982747 |
module amplitude_set (
input clk,
input rst_n,
input key2_in,
output reg [4:0] amplitude
);
reg [2:0] cnt ;
wire key_flag ;
wire key_state ;
key_filter amplitude_key (
.clk (clk),
.rst_n (rst_n),
.key_in (key2_in),
.key_flag (key_flag),
.key_state(key_state)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 3'd0;
end else if (key_flag) begin
if (cnt == 3'd4) begin
cnt <= 3'd0;
end else begin
cnt <= cnt + 1'b1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
amplitude <= 0;
end else begin
case (cnt)
3'd0: amplitude <= 5'd1;
3'd1: amplitude <= 5'd2;
3'd2: amplitude <= 5'd4;
3'd3: amplitude <= 5'd8;
3'd4: amplitude <= 5'd16;
default: amplitude <= 5'd1;
endcase
end
end
endmodule
| 8.93875 |
module amp_adj (
input wire clk,
input wire rst_n,
input wire [7:0] wave,
input wire [4:0] amp_factor,
output reg [7:0] wave_adj
);
always @(posedge clk or negedge rst_n)
if (!rst_n) wave_adj <= 10'd0;
else wave_adj <= wave * amp_factor / 10;
endmodule
| 9.032654 |
module NCO_AMP_CONTROLLER #(
parameter DAC_WIDTH = 14,
parameter IN_WIDTH = 14
) (
input clk,
input rst,
input signed [IN_WIDTH-1:0] INPUT_NCO,
input signed [DAC_WIDTH-1:0] MAX_VOLTAGE,
output signed [DAC_WIDTH-1:0] OUTPUT_NCO
);
wire [IN_WIDTH-1:0] IN_T;
assign IN_T = INPUT_NCO[IN_WIDTH-1] ? ~INPUT_NCO + 1 : INPUT_NCO;
wire [DAC_WIDTH-1:0] TEMP;
wire [DAC_WIDTH-1:0] P[IN_WIDTH-2:0];
genvar i;
generate
for (i = 0; i < IN_WIDTH - 1; i = i + 1) begin : loop
//wire [DAC_WIDTH-1:0] P;
assign P[i] = (IN_T[IN_WIDTH-2-i] ? (MAX_VOLTAGE >> (i + 1)) : 0);
end
endgenerate
integer k;
reg [DAC_WIDTH-1:0] TEMP_r;
always @* begin
TEMP_r = 0; // all zero
for (k = 0; k < IN_WIDTH - 1; k = k + 1) TEMP_r = TEMP_r + P[k];
end
assign TEMP = TEMP_r;
assign OUTPUT_NCO = INPUT_NCO[IN_WIDTH-1] ? ~TEMP + 1 : TEMP;
endmodule
| 7.980459 |
module amp_control_max (
input ENABLE,
input FF_CLOCK,
input CLOCK_2HZ,
input CLOCK_8HZ,
input CLOCK_32HZ,
input CLOCK_128HZ,
input CLOCK_512HZ,
input UP,
input DOWN,
input [31:0] MIN_AMP,
output reg [31:0] MAX_AMP = 32'd4095
);
wire CLOCK;
reg [3:0] COUNT = 6'd0;
reg [15:0] SECONDS = 16'd0;
assign CLOCK = (ENABLE == 0 || COUNT == 0) ? 1'b0 : (SECONDS <= 16'd1) ? CLOCK_2HZ : (SECONDS <= 16'd2) ? CLOCK_8HZ : (SECONDS <= 16'd4) ? CLOCK_32HZ : (SECONDS <= 16'd7) ? CLOCK_128HZ : CLOCK_512HZ;
always @(posedge FF_CLOCK) begin
if (ENABLE == 1 && (UP == 1 || DOWN == 1)) begin
COUNT = COUNT + 1;
SECONDS = (COUNT == 6'd0) ? SECONDS + 1 : SECONDS;
end else begin
COUNT <= 0;
SECONDS <= 0;
end
end
always @(posedge CLOCK) begin
if (UP == 1 && MAX_AMP < 32'd4095) MAX_AMP <= MAX_AMP + 1;
else if (DOWN == 1 && MAX_AMP > 32'd0 && MAX_AMP != MIN_AMP) MAX_AMP <= MAX_AMP - 1;
end
endmodule
| 7.302448 |
module amp_control_min (
input ENABLE,
input FF_CLOCK,
input CLOCK_2HZ,
input CLOCK_8HZ,
input CLOCK_32HZ,
input CLOCK_128HZ,
input CLOCK_512HZ,
input UP,
input DOWN,
input [31:0] MAX_AMP,
output reg [31:0] MIN_AMP = 32'd1
);
wire CLOCK;
reg [3:0] COUNT = 6'd0;
reg [15:0] SECONDS = 16'd0;
assign CLOCK = (ENABLE == 0 || COUNT == 0) ? 1'b0 : (SECONDS <= 16'd1) ? CLOCK_2HZ : (SECONDS <= 16'd2) ? CLOCK_8HZ : (SECONDS <= 16'd4) ? CLOCK_32HZ : (SECONDS <= 16'd7) ? CLOCK_128HZ : CLOCK_512HZ;
always @(posedge FF_CLOCK) begin
if (ENABLE == 1 && (UP == 1 || DOWN == 1)) begin
COUNT = COUNT + 1;
SECONDS = (COUNT == 6'd0) ? SECONDS + 1 : SECONDS;
end else begin
COUNT <= 0;
SECONDS <= 0;
end
end
always @(posedge CLOCK) begin
if (UP == 1 && MIN_AMP < 32'd4095 && MIN_AMP != MAX_AMP) MIN_AMP <= MIN_AMP + 1;
else if (DOWN == 1 && MIN_AMP > 32'd0) MIN_AMP <= MIN_AMP - 1;
end
endmodule
| 7.302448 |
module AMP_TB ();
reg rst = 1, inp = 1, ld = 1, preset = 0;
reg [7:0] phaseControll = 8'd1;
reg [12:0] SW = 13'b0000111111101;
wire [7:0] wave;
wire clk;
WFG_DDS_FS_AMP CUT (
.wave(wave),
.preset(preset),
.clk(clk),
.SW(SW),
.rst(rst),
.ld(ld),
.phaseControll(phaseControll)
);
ring_oscillator #(5, 2) ro (
inp,
clk
);
initial begin
#20 inp = 0;
#10 preset = 1'b1;
#10 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b0100111111101;
#50 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b1000111111101;
#50 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b1100111111101;
#50 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b0001111111101;
#50 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b0101111111101;
#50 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b1001111111101;
#50 rst = 1'b0;
#20000 rst = 1'b1;
SW = 13'b1101111111101;
#50 rst = 1'b0;
#10000 $stop;
end
endmodule
| 7.1397 |
module PP_HIGH (
ONEPOS,
ONENEG,
TWOPOS,
TWONEG,
INA,
INB,
PPBIT
);
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = ~((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG));
endmodule
| 6.512332 |
module R_GATE (
INA,
INB,
INC,
PPBIT
);
input INA;
input INB;
input INC;
output PPBIT;
assign PPBIT = (~(INA & INB)) & INC;
endmodule
| 8.459695 |
module DECODER (
INA,
INB,
INC,
TWOPOS,
TWONEG,
ONEPOS,
ONENEG
);
input INA;
input INB;
input INC;
output TWOPOS;
output TWONEG;
output ONEPOS;
output ONENEG;
assign TWOPOS = ~(~(INA & INB & (~INC)));
assign TWONEG = ~(~((~INA) & (~INB) & INC));
assign ONEPOS = ((~INA) & INB & (~INC)) | ((~INC) & (~INB) & INA);
assign ONENEG = (INA & (~INB) & INC) | (INC & INB & (~INA));
endmodule
| 6.800244 |
module HALF_ADDER (
DATA_A,
DATA_B,
SAVE,
CARRY
);
input DATA_A;
input DATA_B;
output SAVE;
output CARRY;
assign SAVE = DATA_A ^ DATA_B;
assign CARRY = DATA_A & DATA_B;
endmodule
| 6.537169 |
module FLIPFLOP (
DIN,
RST,
CLK,
DOUT
);
input DIN;
input RST;
input CLK;
output DOUT;
reg DOUT_reg;
always @(posedge RST or posedge CLK) begin
if (RST) DOUT_reg <= 1'b0;
else DOUT_reg <= DIN;
end
assign DOUT = DOUT_reg;
endmodule
| 7.654726 |
module XXOR1 (
A,
B,
GIN,
PHI,
SUM
);
input A;
input B;
input GIN;
input PHI;
output SUM;
assign SUM = (~(A ^ B)) ^ GIN;
endmodule
| 7.036883 |
module BLOCK0 (
A,
B,
PHI,
POUT,
GOUT
);
input A;
input B;
input PHI;
output POUT;
output GOUT;
assign POUT = ~(A | B);
assign GOUT = ~(A & B);
endmodule
| 7.437441 |
module BLOCK1 (
PIN1,
PIN2,
GIN1,
GIN2,
PHI,
POUT,
GOUT
);
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~(PIN1 | PIN2);
assign GOUT = ~(GIN2 & (PIN2 | GIN1));
endmodule
| 7.87169 |
module BLOCK2 (
PIN1,
PIN2,
GIN1,
GIN2,
PHI,
POUT,
GOUT
);
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~(PIN1 & PIN2);
assign GOUT = ~(GIN2 | (PIN2 & GIN1));
endmodule
| 8.324076 |
module BLOCK1A (
PIN2,
GIN1,
GIN2,
PHI,
GOUT
);
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~(GIN2 & (PIN2 | GIN1));
endmodule
| 7.952894 |
module BLOCK2A (
PIN2,
GIN1,
GIN2,
PHI,
GOUT
);
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~(GIN2 | (PIN2 & GIN1));
endmodule
| 8.386736 |
module MULTIPLIER_33_32 (
MULTIPLICAND,
MULTIPLIER,
RST,
CLK,
PHI,
RESULT
);
input [0:32] MULTIPLICAND;
input [0:31] MULTIPLIER;
input RST;
input CLK;
input PHI;
output [0:63] RESULT;
wire [0:575] PPBIT;
wire [0:64] INT_CARRY;
wire [0:63] INT_SUM;
wire LOGIC_ZERO;
wire [0:63] ARESULT;
reg [0:63] RESULT;
assign LOGIC_ZERO = 0;
BOOTHCODER_33_32 B (
.OPA(MULTIPLICAND[0:32]),
.OPB(MULTIPLIER[0:31]),
.SUMMAND(PPBIT[0:575])
);
WALLACE_33_32 W (
.SUMMAND(PPBIT[0:575]),
.RST(RST),
.CLK(CLK),
.CARRY(INT_CARRY[1:63]),
.SUM(INT_SUM[0:63])
);
assign INT_CARRY[0] = LOGIC_ZERO;
DBLCADDER_64_64 D (
.OPA (INT_SUM[0:63]),
.OPB (INT_CARRY[0:63]),
.CIN (LOGIC_ZERO),
.PHI (PHI),
.SUM (ARESULT[0:63]),
.COUT()
);
always @(posedge CLK or posedge RST)
if (RST) RESULT <= 64'h0000_0000_0000_0000;
else RESULT <= ARESULT;
endmodule
| 7.769651 |
module aMux (
a_flag,
PC,
DR,
R1,
R2,
R3,
R4,
R5,
A_bus
);
input [2:0] a_flag;
input [15:0] PC, DR, R1, R2, R3, R4, R5;
output [15:0] A_bus;
reg [15:0] A_bus;
always @(*) begin
case (a_flag)
3'd1: A_bus = PC;
3'd2: A_bus = DR;
3'd3: A_bus = R1;
3'd4: A_bus = R2;
3'd5: A_bus = R3;
3'd6: A_bus = R4;
3'd7: A_bus = R5;
default: A_bus = 16'dz;
endcase
end
endmodule
| 7.934675 |
module AMUX2_3V (
input wire real VDD3V3,
input wire real VDD1V8,
input wire real VSSA,
input wire real AIN1,
input wire real AIN2,
output wire real AOUT,
input SEL
);
wire SEL;
real NaN;
initial begin
NaN = 0.0 / 0.0;
end
assign AOUT = (SEL == 1'b1) ? AIN2 : (SEL == 1'b0) ? AIN1 : NaN;
endmodule
| 7.882222 |
module AMUX4_3V (
input wire real VDD3V3,
input wire real VDD1V8,
input wire real VSSA,
input wire real AIN1,
input wire real AIN2,
input wire real AIN3,
input wire real AIN4,
output wire real AOUT,
input [1:0] SEL
);
wire [1:0] SEL;
real NaN;
initial begin
NaN = 0.0 / 0.0;
end
assign AOUT = (SEL == 2'b11) ? AIN4 :
(SEL == 2'b10) ? AIN3 :
(SEL == 2'b01) ? AIN2 :
(SEL == 2'b00) ? AIN1 :
NaN;
endmodule
| 7.508087 |
module am_demod #(
parameter BITS = 16
) (
input CLK,
input RSTb,
input signed [BITS - 1 : 0] I_in,
input signed [BITS - 1 : 0] Q_in,
input load_tick, /* tick should go high when new sample is ready */
output reg signed [BITS - 1:0] demod_out,
output reg out_tick /* tick will go high when the new AM demodulated sample is ready */
);
wire signed [2*BITS - 1 : 0] I_sq;
mult #(
.BITS(BITS)
) m0 (
I_in,
I_in,
I_sq
);
wire signed [2*BITS - 1 : 0] Q_sq;
mult #(
.BITS(BITS)
) m1 (
Q_in,
Q_in,
Q_sq
);
localparam st_idle = 3'd0;
localparam st_load_sq = 3'd1;
localparam st_add_sq = 3'd2;
localparam st_start_sqrt = 3'd3;
localparam st_wait_sqrt = 3'd4;
reg [2:0] state;
reg sqrt_done = 1'b0;
reg signed [2*BITS - 1 : 0] I_sq_q;
reg signed [2*BITS - 1 : 0] Q_sq_q;
reg signed [2*BITS : 0] sum;
always @(posedge CLK) begin
if (RSTb == 1'b0) begin
I_sq_q <= {2 * BITS{1'b0}};
Q_sq_q <= {2 * BITS{1'b0}};
state <= st_idle;
end else begin
case (state)
st_idle: if (load_tick == 1'b1) state <= st_load_sq;
st_load_sq: begin
I_sq_q <= I_sq;
Q_sq_q <= Q_sq;
state <= st_add_sq;
end
st_add_sq: begin
sum <= I_sq_q + Q_sq_q;
state <= st_start_sqrt;
end
st_start_sqrt: state <= st_wait_sqrt;
st_wait_sqrt: if (sqrt_done == 1'b1) state <= st_idle;
default: state <= st_idle;
endcase
end
end
reg [1:0] sqrt_state;
/*
* We Pipeline the "non-restoring" Square root algorithm used by
* Alberto: https://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html
* In this way, we (hopefully) do not have to create a new clock domain for the amplitude demodulation.
*
*/
reg [BITS*2-1:0] a;
reg [BITS-1:0] q;
reg [BITS+1:0] left, right, r;
reg [1:0] count;
reg [3:0] count2;
localparam BITS_PLUS_2 = BITS + 2;
always @(posedge CLK) begin
if (RSTb == 1'b0) begin
sqrt_state <= 2'd0;
demod_out <= {BITS{1'b0}};
out_tick <= 1'b0;
end else begin
case (sqrt_state)
2'd0: begin
out_tick <= 1'b0;
sqrt_done <= 1'b0;
if (state == st_start_sqrt) sqrt_state <= sqrt_state + 1;
end
2'd1: begin
a <= sum[2*BITS:1];
left <= {BITS_PLUS_2{1'b0}};
right <= {BITS_PLUS_2{1'b0}};
r <= {BITS_PLUS_2{1'b0}};
q <= {BITS{1'b0}};
sqrt_state <= sqrt_state + 1;
count <= 2'd0;
count2 <= 4'd0;
end
2'd2: begin
case (count)
2'd0: begin
right <= {q, r[BITS_PLUS_2-1], 1'b1};
left <= {r[BITS-1:0], a[2*BITS-1:2*BITS-2]};
a <= {a[2*BITS-3:0], 2'b00}; //left shift by 2 bits.
count <= count + 1;
end
2'd1: begin
if (r[BITS_PLUS_2-1] == 1'b1) //add if r is negative
r <= left + right;
else //subtract if r is positive
r <= left - right;
count <= count + 1;
end
2'd2: begin
q <= {q[BITS-2:0], !r[BITS_PLUS_2-1]};
count <= 2'd0;
count2 <= count2 + 1;
if (count2 == 4'd15) sqrt_state <= sqrt_state + 1;
end
endcase
end
2'd3: begin
out_tick <= 1'b1;
sqrt_state <= 2'd0;
demod_out <= q;
sqrt_done <= 1'b1;
end
default: sqrt_state <= 2'd0;
endcase
end
end
endmodule
| 6.996844 |
module am_FIFO (
clk,
clear_b,
a_in,
b_in,
sign_q,
exponent_q,
state_cnt,
sign_passed,
exponent_passed,
product
);
//-----------------------Input Ports-----------------------//
input wire clk;
input wire clear_b;
input wire [23:0] a_in; //24-bit extended mantissa of either D or N
input wire [23:0] b_in; //24-bit correction factor F
input wire sign_q; //the sign bit needs to be passed down along the pipeline
input wire [ 7:0] exponent_q; //the difference in exponents needs to be passed down along the pipeline
input wire [4:0] state_cnt; //keeps track of which cycle it currently is within one division
//provided by higher-heirarchy module
//-----------------------Input Ports-----------------------//
output wire [47:0] product;
output reg sign_passed;
output reg [7:0] exponent_passed;
//------------------Internal Variables--------------------//
reg wr_en;
reg rd_en;
wire stage0_sign;
wire stage1_sign;
wire [7:0] stage0_exponent;
wire [7:0] stage1_exponent;
wire [23:0] stage0_a;
wire [23:0] stage1_a;
wire [23:0] stage0_b;
wire [23:0] stage1_b;
//-----------------Code Starts Here--------------------//
always @(negedge clk) begin : SET_WR_EN
if (clear_b) begin
if ((state_cnt % 4) == 0 && state_cnt != 20) wr_en <= 1;
else if ((state_cnt % 4) == 2) wr_en <= 0;
end else if (~clear_b) wr_en <= 0;
end
always @(negedge clk) begin : SET_RD_EN
if (clear_b) begin
if ((state_cnt % 4) == 1) rd_en <= 1;
else if ((state_cnt % 4) == 0) rd_en <= 0;
end else if (~clear_b) rd_en <= 0;
end
always @(posedge clk) begin : LATCH_SIGN_AND_EXPONENT
if (clear_b) begin
sign_passed <= stage1_sign;
exponent_passed <= stage1_exponent;
end else if (~clear_b) begin
sign_passed <= 1'bz;
exponent_passed <= 8'bz;
end
end
mul_input_FIFO fifo (
.clk(clk),
.clear_b(clear_b),
.a_in(a_in),
.b_in(b_in),
.sign_q(sign_q),
.exponent_q(exponent_q),
.wr_en(wr_en),
.rd_en(rd_en),
.stage0_a(stage0_a),
.stage1_a(stage1_a),
.stage0_b(stage0_b),
.stage1_b(stage1_b),
.stage0_sign(stage0_sign),
.stage1_sign(stage1_sign),
.stage0_exponent(stage0_exponent),
.stage1_exponent(stage1_exponent)
);
ArrayMultiplier am_2stage (
.clk(clk),
.a(stage0_a),
.x(stage0_b),
.product_reg(product)
);
endmodule
| 6.662127 |
module am_gen (
input CLK,
input RSTb,
output reg one_bit_rf
);
/* Carrier */
wire [39:0] phase_inc = 40'h2656abde3; // 936 kHz
wire signed [15:0] sin;
wire signed [15:0] cos;
nco nco0 (
CLK,
RSTb,
phase_inc,
sin,
cos
);
/* Modulation */
/* phase inc => print("%x" % int(1e3 / (a / (1<<40)))) where a is the clock rate */
wire [39:0] phase_inc_mod = 40'ha7c5ac; // 1 kHz
wire signed [15:0] sin_mod;
wire signed [15:0] cos_mod;
nco nco1 (
CLK,
RSTb,
phase_inc_mod,
sin_mod,
cos_mod
);
/* State machine */
reg signed [15:0] cos_q;
reg signed [15:0] cos_mod_q;
wire signed [15:0] mod_scale = 16'hccc;
wire signed [31:0] mod_scaled;
mult m0 (
mod_scale,
cos_mod_q,
mod_scaled
);
reg signed [15:0] cos_mod_scaled;
reg signed [15:0] cos_mod_plus_dc;
wire signed [31:0] mod_wave;
mult m1 (
cos_mod_plus_dc,
cos_q,
mod_wave
);
reg signed [15:0] mod_wave_q;
wire signed [15:0] noise_val;
reg [9:0] count = 10'd0;
always @(posedge CLK) count += 1;
noiseTable noise0 (
CLK,
count,
noise_val
);
reg signed [15:0] mod_wave_q_noise;
always @(posedge CLK) begin
cos_mod_q <= cos_mod;
cos_q <= cos;
cos_mod_scaled <= mod_scaled[31:16];
cos_mod_plus_dc <= cos_mod_scaled + 16'h2ccc;
mod_wave_q <= mod_wave[31:16];
mod_wave_q_noise <= mod_wave_q + noise_val;
one_bit_rf <= (mod_wave_q_noise > 0) ? 1'b1 : 1'b0;
end
endmodule
| 6.674582 |
module am_insertion #(
parameter LEN_CODED_BLOCK = 66,
parameter AM_ENCODING_LOW = 24'd0, //{M0,M1,M2} tabla 82-2
parameter AM_ENCODING_HIGH = 24'd0, //{M4,M5,M6} tabla 82-2
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_am_insert,
input wire [LEN_CODED_BLOCK-1 : 0] i_data,
output wire [LEN_CODED_BLOCK-1 : 0] o_data
);
localparam CTRL_SH = 2'b10;
//Internal signals
reg [LEN_CODED_BLOCK-1 : 0] data;
wire [NB_BIP-1 : 0] bip3, bip7;
reg [7:0] br;
always @(posedge i_clock) begin
if (i_reset) begin
data <= {LEN_CODED_BLOCK{1'b0}};
br <= {NB_BIP{1'b1}};
end else if (i_enable && ~i_am_insert) begin
data <= i_data;
br <= bip3;
end else if (i_enable && i_am_insert) begin
data <= {CTRL_SH, AM_ENCODING_LOW, br, AM_ENCODING_HIGH, (~br)};
br <= bip3;
end
end
//PORTS
assign o_data = data;
//instances
bip_calculator #(
.LEN_CODED_BLOCK(LEN_CODED_BLOCK)
) u_bip_calculator (
.i_clock (i_clock),
.i_reset (i_reset),
.i_data (data), // data from internal reg. [FIX]
.i_enable (i_enable),
.i_am_insert(i_am_insert),
.o_bip3 (bip3),
.o_bip7 (bip7),
.i_bip (br)
);
endmodule
| 7.003169 |
module am_insertion #(
parameter LEN_CODED_BLOCK = 66,
parameter AM_ENCODING_LOW = 24'd0, //{M0,M1,M2} tabla 82-2
parameter AM_ENCODING_HIGH = 24'd0, //{M4,M5,M6} tabla 82-2
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_am_insert,
input wire [LEN_CODED_BLOCK-1 : 0] i_data,
output wire [LEN_CODED_BLOCK-1 : 0] o_data
);
localparam CTRL_SH = 2'b10;
//Internal signals
reg [LEN_CODED_BLOCK-1 : 0] data;
wire [NB_BIP-1 : 0] bip3, bip7;
always @(posedge i_clock) begin
if (i_reset) data <= {LEN_CODED_BLOCK{1'b0}};
else if (i_enable && ~i_am_insert) data <= i_data;
else if (i_enable && i_am_insert)
data <= {CTRL_SH, AM_ENCODING_LOW, bip3, AM_ENCODING_HIGH, bip7};
end
//PORTS
assign o_data = data;
//instances
bip_calculator #(
.LEN_CODED_BLOCK(LEN_CODED_BLOCK)
) u_bip_calculator (
.i_clock (i_clock),
.i_reset (i_reset),
.i_data (data), // data from internal reg. [FIX]
.i_enable (i_enable),
.i_am_insert(i_am_insert),
.o_bip3 (bip3),
.o_bip7 (bip7)
);
endmodule
| 7.003169 |
module am_lock_comparator #(
parameter LEN_AM = 48,
parameter N_ALIGNER = 20
) (
input wire i_enable_mask, // input from fsm
input wire i_timer_done,
input wire [ LEN_AM-1 : 0] i_am_value,
input wire [N_ALIGNER-1 : 0] i_match_mask,
input wire i_sh_valid,
output wire o_am_match,
output wire [N_ALIGNER-1 : 0] o_match_vector
);
localparam AM_LANE_0 = 48'hC168213E97DE;
localparam AM_LANE_1 = 48'h9D718E628E71;
localparam AM_LANE_2 = 48'h594BE8A6B417;
localparam AM_LANE_3 = 48'h4D957BB26A84;
localparam AM_LANE_4 = 48'hF507090AF8F6;
localparam AM_LANE_5 = 48'hDD14C222EB3D;
localparam AM_LANE_6 = 48'h9A4A2665B5D9;
localparam AM_LANE_7 = 48'h7B456684BA99;
localparam AM_LANE_8 = 48'hA024765FDB89;
localparam AM_LANE_9 = 48'h68C9FB973604;
localparam AM_LANE_10 = 48'hFD6C99029366; //check
localparam AM_LANE_11 = 48'hB99155466EAA;
localparam AM_LANE_12 = 48'h5CB9B2A3464D;
localparam AM_LANE_13 = 48'h1AF8BDE50742;
localparam AM_LANE_14 = 48'h83C7CA7C3835;
localparam AM_LANE_15 = 48'h3536CDCAC932;
localparam AM_LANE_16 = 48'hC4314C3BCEB3;
localparam AM_LANE_17 = 48'hADD6B7522948;
localparam AM_LANE_18 = 48'h5F662AA099D5;
localparam AM_LANE_19 = 48'hC0F0E53F0F1A;
integer i;
reg [LEN_AM*N_ALIGNER-1 : 0] aligners;
reg [ N_ALIGNER-1 : 0] match_mask; //salida de fsm
reg [ N_ALIGNER-1 : 0] match_vector; //salida de comparadores
reg [ N_ALIGNER-1 : 0] match_expected_am;
reg [ LEN_AM-1 : 0] am_value; // bits
reg match_payload;
reg enable;
reg match;
always @* begin
aligners = {
AM_LANE_19,
AM_LANE_18,
AM_LANE_17,
AM_LANE_16,
AM_LANE_15,
AM_LANE_14,
AM_LANE_13
, AM_LANE_12,
AM_LANE_11,
AM_LANE_10,
AM_LANE_9,
AM_LANE_8,
AM_LANE_7,
AM_LANE_6
, AM_LANE_5,
AM_LANE_4,
AM_LANE_3,
AM_LANE_2,
AM_LANE_1,
AM_LANE_0
};
match_vector = 0;
match_expected_am = 0;
match_payload = 0;
enable = 0;
match = 0;
for (i = 0; i < N_ALIGNER; i = i + 1) begin
if ((aligners[i*LEN_AM+:LEN_AM] == i_am_value) && i_match_mask[i]) begin
match_expected_am[i] = 1;
match_vector[i] = 1;
end
end
match_payload = |match_expected_am; // se encontro un match
enable = (i_timer_done | i_enable_mask);
match = match_payload & enable & i_sh_valid; //input to fsm
end
assign o_am_match = match;
assign o_match_vector = match_vector;
endmodule
| 7.126741 |
module am_lock_comparator_v2
#(
parameter NB_AM = 48,
parameter N_ALIGNER = 20
)
( input wire i_enable_mask, // input from fsm
input wire i_timer_done ,
input wire [NB_AM-1 : 0] i_am_value ,
input wire [NB_AM-1 : 0] i_compare_mask , //mascara configurable para permitir flexibilidad en la comparacion
input wire [N_ALIGNER-1 : 0] i_match_mask , //expected am mask
output wire o_am_match , //flag signaling match
output wire [N_ALIGNER-1 : 0] o_match_vector
);
localparam AM_LANE_0 = 48'hC168213E97DE;
localparam AM_LANE_1 = 48'h9D718E628E71;
localparam AM_LANE_2 = 48'h594BE8A6B417;
localparam AM_LANE_3 = 48'h4D957BB26A84;
localparam AM_LANE_4 = 48'hF507090AF8F6;
localparam AM_LANE_5 = 48'hDD14C222EB3D;
localparam AM_LANE_6 = 48'h9A4A2665B5D9;
localparam AM_LANE_7 = 48'h7B456684BA99;
localparam AM_LANE_8 = 48'hA024765FDB89;
localparam AM_LANE_9 = 48'h68C9FB973604;
localparam AM_LANE_10 = 48'hFD6C99029366; //check
localparam AM_LANE_11 = 48'hB99155466EAA;
localparam AM_LANE_12 = 48'h5CB9B2A3464D;
localparam AM_LANE_13 = 48'h1AF8BDE50742;
localparam AM_LANE_14 = 48'h83C7CA7C3835;
localparam AM_LANE_15 = 48'h3536CDCAC932;
localparam AM_LANE_16 = 48'hC4314C3BCEB3;
localparam AM_LANE_17 = 48'hADD6B7522948;
localparam AM_LANE_18 = 48'h5F662AA099D5;
localparam AM_LANE_19 = 48'hC0F0E53F0F1A;
integer i;
reg [NB_AM*N_ALIGNER-1 : 0] aligners;
reg [N_ALIGNER-1 : 0] match_mask; //salida de fsm
reg [N_ALIGNER-1 : 0] match_vector;//salida de comparadores
reg [N_ALIGNER-1 : 0] match_expected_am;
reg [NB_AM-1 : 0] am_value_masked;// bits
reg match_payload;
reg enable;
reg match;
reg aux; //TODO pensar un nombre mejor
always @ *
begin
aligners = { AM_LANE_19, AM_LANE_18, AM_LANE_17, AM_LANE_16, AM_LANE_15, AM_LANE_14, AM_LANE_13,
AM_LANE_12, AM_LANE_11, AM_LANE_10, AM_LANE_9 , AM_LANE_8 , AM_LANE_7 , AM_LANE_6 ,
AM_LANE_5 , AM_LANE_4 , AM_LANE_3 , AM_LANE_2 , AM_LANE_1 , AM_LANE_0 };
match_vector = 0;
match_expected_am = 0;
match_payload = 0;
enable = 0;
match = 0;
aux = 0;
for(i=0;i<N_ALIGNER;i=i+1)
begin
am_value_masked = i_am_value & i_compare_mask;
aux = |(am_value_masked ^ aligners[i*LEN_AM +: LEN_AM])
if (!aux && i_match_mask[i])
begin
match_expected_am[i] = 1;
match_vector[i] = 1;
end
end
match_payload = | match_expected_am; // se encontro un match
enable = (i_timer_done | i_enable_mask);//se cumplio el tiempo en el que debe llegar otro bloque o todavia no encontre el primero
match = match_payload & enable & i_sh_valid;//input to fsm
end
assign o_am_match = match;
assign o_match_vector = match_vector;
endmodule
| 7.126741 |
module am_mask_handler
#(
parameter NB_AM = 48,
)
(
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_config,
input wire [NB_AM-1 : 0] i_mask_config,
output wire [NB_AM-1 : 0] o_compare_mask
);
//INTERNAL SIGNALS
reg [NB_AM-1 : 0] selected_mask;
always @ (posedge i_clock)
begin
if (i_reset)
selected_mask <= {NB_AM{1'b1}};
else if (i_config && i_enable)
selected_mask <= i_mask_config;
end
assign o_compare_mask = selected_mask;
endmodule
| 6.745844 |
module AM_MODE (
input clk,
rst_n,
output dac_clk,
output adc_clk,
output [13:0] am
);
wire rst;
wire clk_200M;
wire [14:0] out;
wire [7:0] add1_temp; //加法数据
wire [8:0] add1_s;
wire [13:0] carrier_signal; //载波信号
wire signed [8:0] depth; //调制深度
wire [8:0] add_out; //加法器输出
wire [8:0] mult_in; //乘法器输入
wire [5:0] mult_in_a; //乘法器载波输入
reg [13:0] out_data;
assign rst = ~rst_n;
assign depth = 9'd180;
assign mult_in = add_out;
assign mult_in_a = carrier_signal[13:8];
assign dac_clk = clk_200M;
assign adc_clk = clk;
always @(posedge clk_200M) out_data <= out[14:1];
//数字信号产生
reg [31:0] timer;
reg binary_data;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
timer <= 32'd0;
binary_data <= 1'b1;
end else if (timer == 32'd249_999) begin
timer <= 32'd0;
binary_data <= ~binary_data;
end else timer <= timer + 1'b1;
end
//有符号转无符号
reg [13:0] am_u;
always @(posedge clk_200M) begin
if (out_data[13] == 0) begin
am_u <= {{~out_data[13]}, out_data[12:0]};
end else begin
am_u <= {{~out_data[13]}, out_data[12:0]} - 14'd1;
end
end
assign am = am_u; //定义增益
//无符号转有符号
reg [7:0] add_s; //有符号数调制信号
always @(posedge clk_200M) begin
if (add1_temp[7] == 1) begin
add_s <= {{~add1_temp[7]}, add1_temp[6:0]};
end else begin
add_s <= {{~add1_temp[7]}, add1_temp[6:0]} + 8'd1;
end
end
assign add1_s = {add_s[7], add_s};
add add_inst (
.dataa (add1_s),
.datab (depth),
.result(add_out)
);
mult mult_inst (
.clock (clk_200M),
.dataa (mult_in_a),
.datab (mult_in),
.result(out)
);
adda_out adda_out_inst (
.clk(clk),
.rst_n(rst_n),
.dacdata(add1_temp)
);
//fsk
FskMod FskMod_inst (
.rst(rst),
.clk(clk),
.din(binary_data),
.dout(carrier_signal),
.dac_clk(clk_200M)
);
endmodule
| 6.787392 |
module am_modulator (
input wire clk,
input wire [7:0] signal,
input wire signed [15:0] mod_sin,
output wire [5:0] out
);
//make signed 16bit signal from input unsigned 8bit signal
reg signed [15:0] ssignal;
always @(posedge clk) ssignal <= {signal, 8'h00} - 16'h8000;
//modulate by multiplying useful signal on modulation freq sinusoida
reg signed [31:0] multiplied;
always @(posedge clk) multiplied <= ssignal * mod_sin;
reg signed [15:0] multiplied_th; //top half
always @(posedge clk) multiplied_th <= multiplied[31:16];
//add modulation freq carrier to signal
reg signed [15:0] s_after_mod;
always @(posedge clk) s_after_mod <= ((mod_sin >>> 1) + multiplied_th);
//make unsigned
reg [15:0] after_mod;
always @(posedge clk) after_mod <= s_after_mod + 16'h8000;
assign out = after_mod[15:10];
/*
//add modulation freq carrier to signal
reg signed [31:0]s_after_mod;
always @(posedge clk)
s_after_mod <= ( $signed( {mod_sin[15], mod_sin[15], mod_sin, 14'h0000} ) + $signed(multiplied>>>1) );
//make unsigned
reg [31:0]after_mod;
always @(posedge clk)
after_mod <= s_after_mod + 32'h80000000;
assign out = after_mod[31:26];
*/
endmodule
| 7.730983 |
module am_mod_counter #(
parameter N_BLOCKS = 16383, //[REVISAR] cantidad de bloquen entre am y am
parameter N_LANES = 20
) (
input wire i_reset,
input wire i_clock,
input wire i_enable,
input wire i_valid, // coontrol de flujo de cgmii, puede estar siempre en 1
output wire o_block_count_done,
output wire o_insert_am_idle,
output wire o_enable_fifo_read
);
//LOCALPARAMS
localparam MAX_COUNT = N_LANES * N_BLOCKS;
localparam NB_COUNT = $clog2(N_LANES * N_BLOCKS);
//INTERNAL SIGNALS
reg [NB_COUNT-1 : 0] counter;
//Update counter
always @(posedge i_clock) begin
if (i_reset) counter <= {NB_COUNT{1'b0}};
else if (i_enable && i_valid) begin
if (counter == MAX_COUNT - 1) counter <= 0;
else counter <= counter + 1;
end
end
//PORTS
assign o_block_count_done = (counter == {NB_COUNT{1'b0}}) ? 1'b1 : 1'b0;
assign o_insert_am_idle = (counter < N_LANES) ? 1'b1 : 1'b0;
assign o_enable_fifo_read = (counter > N_LANES) ? 1'b1 : 1'b0;
endmodule
| 6.625695 |
module am_shift (
input [15:0] a_m,
input [ 4:0] tmp_cnt,
output [15:0] a_m_shift
);
assign a_m_shift = a_m << tmp_cnt;
endmodule
| 7.120022 |
module am_shifter (
input [15:0] datain,
input right,
input [1:0] bitnum,
output [15:0] dataout
);
wire [14:0] right_temp = datain[15:1];
wire [14:0] left_temp = datain[14:0];
wire [15:0] data_temp = (right == 1'b1) ? {datain[15], right_temp} : {left_temp, 1'b0};
assign dataout[3:0] = {
(bitnum == 2'b00)? {(right==1'b1)?datain[3]:data_temp[3], data_temp[2:0]} :{data_temp[3:0]}
};
assign dataout[7:4] = {
(bitnum == 2'b10) ? {data_temp[7]} : {(right == 1'b1) ? datain[7] : data_temp[7]},
data_temp[6:5],
(bitnum == 2'b00) ? {right & data_temp[4]} : {data_temp[4]}
};
assign dataout[11:8] = {
(bitnum == 2'b00) ? {(right == 1'b1) ? datain[11] : data_temp[11]} : data_temp[11],
data_temp[10:9],
(bitnum == 2'b10) ? {data_temp[8]} : {right & data_temp[8]}
};
assign dataout[15:12] = {
data_temp[15:13], (bitnum == 2'b00) ? {right & data_temp[12]} : {data_temp[12]}
};
endmodule
| 6.53352 |
module am_shift_t (
input [5:0] a_e,
input [5:0] sub_a_e,
input [15:0] a_m,
output reg [27:0] a_m_shift
);
always @(a_e or sub_a_e or a_m) begin
if (a_e <= 15 && a_e >= 0) begin
a_m_shift = {a_m, 12'b0} >> sub_a_e;
end else begin
a_m_shift = 24'h0;
end
end
endmodule
| 7.742958 |
module am_sol_timer #(
parameter N_BLOCKS = 16383, //[check]
parameter EXTRA_DELAY = 0 //depends on reset conditiones
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_restart,
output reg o_start_of_lane
);
//LOCALPARAMS
localparam NB_COUNTER = $clog2(N_BLOCKS);
localparam N_STATES = 2;
localparam INIT = 2'b10;
localparam LOCKED = 2'b01;
//INTERNAL SIGNALS
reg [NB_COUNTER-1 : 0] counter;
reg [NB_COUNTER-1 : 0] counter_next;
reg [ N_STATES-1 : 0] state;
reg [ N_STATES-1 : 0] state_next;
//Update counter
always @(posedge i_clock) begin
if (i_reset || i_restart) begin
counter <= 0;
state <= INIT;
end else if (i_enable && i_valid) begin
counter <= counter_next;
state <= state_next;
end
end
always @* begin
state_next = state;
counter_next = counter + 1;
o_start_of_lane = 0;
case (state)
INIT: begin
if (counter == N_BLOCKS - EXTRA_DELAY) begin
o_start_of_lane = 1;
counter_next = {NB_COUNTER{1'b0}};
state_next = LOCKED;
end
end
LOCKED: begin
if (counter == N_BLOCKS) begin
counter_next = {NB_COUNTER{1'b0}};
o_start_of_lane = 1;
state_next = LOCKED;
end
end
endcase
end
//PORTS
/*
State INIT
La cuenta se realiza hasta 2 menos que el periodo entre alineadores debido a que la fms introduce
1 ciclo de clock de delay para setear la flag que resetea el timer y el contador interno
demora 1 ciclo mas en volverse a cero.
State LOCKED
La cuenta se realiza durante todo el periodo entre alineadores.
*/
endmodule
| 6.577716 |
module Decoder_2_to_4 (
out,
a,
b
);
output [3:0] out;
input a, b;
wire n1, n2;
NOR2X1 U1 (
.A(n1),
.B(n2),
.Y(out[3])
);
NOR2X1 U2 (
.A(b),
.B(n1),
.Y(out[2])
);
CLKINVX1 U3 (
.A(a),
.Y(n1)
);
NOR2X1 U4 (
.A(a),
.B(n2),
.Y(out[1])
);
CLKINVX1 U5 (
.A(b),
.Y(n2)
);
NOR2X1 U6 (
.A(b),
.B(a),
.Y(out[0])
);
endmodule
| 6.672456 |
module Decoder_2_to_4_2 (
out,
a,
b
);
output [3:0] out;
input a, b;
wire n1, n2;
NOR2X1 U7 (
.A(n1),
.B(n2),
.Y(out[3])
);
NOR2X1 U8 (
.A(b),
.B(n1),
.Y(out[2])
);
CLKINVX1 U9 (
.A(a),
.Y(n1)
);
NOR2X1 U10 (
.A(a),
.B(n2),
.Y(out[1])
);
CLKINVX1 U11 (
.A(b),
.Y(n2)
);
NOR2X1 U12 (
.A(b),
.B(a),
.Y(out[0])
);
endmodule
| 6.672456 |
module Decoder_2_to_4_1 (
out,
a,
b
);
output [3:0] out;
input a, b;
wire n1, n2;
NOR2X1 U7 (
.A(n1),
.B(n2),
.Y(out[3])
);
NOR2X1 U8 (
.A(b),
.B(n1),
.Y(out[2])
);
CLKINVX1 U9 (
.A(a),
.Y(n1)
);
NOR2X1 U10 (
.A(a),
.B(n2),
.Y(out[1])
);
CLKINVX1 U11 (
.A(b),
.Y(n2)
);
NOR2X1 U12 (
.A(b),
.B(a),
.Y(out[0])
);
endmodule
| 6.672456 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.