code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ADD (
x,
y,
sum,
OF
);
input signed [63:0] x, y;
output signed [63:0] sum;
output signed OF;
wire signed [63:0] ci;
wire carry_in;
assign carry_in = 1'b0;
full_adder FA1 (
x[0],
y[0],
carry_in,
sum[0],
ci[0]
);
genvar i;
generate
for (i = 1; i < 64; i = i + 1) begin
full_adder FA0 (
x[i],
y[i],
ci[i-1],
sum[i],
ci[i]
);
end
endgenerate
xor (OF, ci[62], ci[63]);
endmodule
| 6.891749 |
module SUB (
x,
y,
z,
OF
);
input signed [63:0] x, y;
output signed [63:0] z;
output OF;
wire signed [63:0] u, v, w;
wire signed [63:0] k;
twocomp comp (
y,
u
);
ADD sub_add (
x,
u,
w,
OF
);
assign z = w;
endmodule
| 6.850044 |
module twocomp (
x,
y
);
input signed [63:0] x;
output signed [63:0] y;
wire signed [63:0] w;
wire c_out;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
not (w[i], x[i]);
end
endgenerate
ADD twocomp1 (
w,
64'b1,
y,
c_out
);
endmodule
| 6.570209 |
module alu_upper_immediate_auipc (
input clock,
input alu_upper_immediate_auipc_enable,
input [31:0] immediate20_utype,
input [31:0] rs1_value,
output reg [31:0] rd_value,
input [31:0] pc
);
always @(posedge clock & alu_upper_immediate_auipc_enable) begin
rd_value <= pc + immediate20_utype;
end
always @(posedge clock & !alu_upper_immediate_auipc_enable) begin
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 6.534627 |
module alu_upper_immediate_lui (
input clock,
input alu_upper_immediate_lui_enable,
input [31:0] immediate20_utype,
input [31:0] rs1_value,
output reg [31:0] rd_value,
input [31:0] pc
);
always @(posedge clock & alu_upper_immediate_lui_enable) begin
rd_value <= immediate20_utype;
end
always @(posedge clock & !alu_upper_immediate_lui_enable) begin
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 6.534627 |
module ALU_v1 (
input [3:0] ALU_operation,
input [31:0] A,
B,
output overflow,
zero,
output [31:0] res
);
wire [32:0] ADC_out;
wire [31:0] ADC_B, signalext_out;
wire [31:0] and_res, or_res, xor_res, nor_res, srl_res, sll_res, slt_res;
wire SLT;
and32 and32 (
.A (A),
.B (B),
.res(and_res)
);
or32 or32 (
.A (A),
.B (B),
.res(or_res)
);
xor32 xor32 (
.A (A),
.B (B),
.res(xor_res)
);
nor32 nor32 (
.A (A),
.B (B),
.res(nor_res)
);
srl32 srl32 (
.A (A),
.B (B),
.res(srl_res)
);
sll32 sll32 (
.A (A),
.B (B),
.res(sll_res)
);
SignalExt_32 signalext (
.S (ALU_operation[2]),
.So(signalext_out)
);
assign ADC_B = signalext_out ^ B;
ADC32 adder (
.A(A),
.B(ADC_B),
.C0(ALU_operation[2]),
.S(ADC_out),
.overflow(overflow)
);
or_bit_32 zeroJudge (
.A(res),
.o(zero)
);
assign SLT = ~(A[31] ^ B[31]) & ADC_out[31] | A & ~B;
assign slt_res = {31'h0, SLT};
MUX16T1_32 mux (
.I0 (and_res),
.I1 (or_res),
.I2 (ADC_out[31:0]),
.I3 (xor_res),
.I4 (nor_res),
.I5 (srl_res),
.I6 (ADC_out[31:0]),
.I7 (slt_res),
.I8 (sll_res),
.I9 (),
.I10(),
.I11(),
.I12(),
.I13(),
.I14(),
.I15(),
.s (ALU_operation),
.o (res)
);
endmodule
| 7.073619 |
module meiaSoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR1 (s0, a, b);
and AND1 (s1, a, b);
endmodule
| 7.280431 |
module meiaSoma
//-----------------
//-- Soma Completa
//-----------------
module somaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaSoma MS1 (s2, s3, a, b);
meiaSoma MS2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.661006 |
module somaCompleta
// ----------------------
// -- Somador de 4 bits
// ----------------------
module somador4bits(s0, s1, s2, s3, carry, comparador, a0, a1, a2, a3, b0 ,b1, b2, b3);
output s0, s1, s2, s3, carry, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
somaCompleta SM1(s0, w1, b0, a1, 0'b0);
somaCompleta SM2(s1, w2, b1, a1, w1);
somaCompleta SM3(s2, w3, b2, a2, w2);
somaCompleta SM4(s3, carry, b3, a3, w3);
not NOT1(comparador, w3);
endmodule
| 7.41852 |
module somador
//------------------
//-- Meia Diferena
//------------------
module meiaDiferenca(s0, s1, a ,b);
output s0, s1;
input a, b;
wire s2;
xor XOR1 (s0, a, b);
not NOT1 (s2, a);
and AND1 (s1, b, s2);
endmodule
| 7.81062 |
module Meia Diferena
//----------------------
//-- Diferena Completa
//----------------------
module diferencaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaDiferenca MD1 (s2, s3, a, b);
meiaDiferenca MD2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.055737 |
module Diferenca Completa
// ----------------------
// -- Subtrator de 4 bits
// ----------------------
module subtrator4bits(s0, s1, s2, s3, comparador, a0, a1, a2, a3, b0, b1, b2, b3);
output s0, s1, s2, s3, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
diferencaCompleta DC1 (s0, w1, a0 ,b0, 0'b0);
diferencaCompleta DC2 (s1, w2, a1, b1, w1);
diferencaCompleta DC3 (s2, w3, a2, b2, w2);
diferencaCompleta DC4 (s3, comparador, a3, b3, w3);
endmodule
| 6.693215 |
module comparadorLogico
// ------
// -- ALU
// ------
module aLU(s0 ,s1, s2, s3, carry, overFlow, x0, y0, y1, y2, y3, comparador, k0, s00, s01, s02, s03, s10, s11, s12, s13, a0, a1, a2, a3, b0, b1, b2, b3);
output s0 ,s1, s2, s3, carry, overFlow, x0, y0, y1, y2, y3, comparador, k0, s00, s01, s02, s03, s10, s11, s12, s13;
input a0, a1, a2, a3, b0, b1, b2, b3;
wire w1;
somador4bits S4B(s0, s1, s2, s3, carry, w1, a0, a1, a2, a3, b0 ,b1, b2, b3);
and AND1(overFlow, carry, w1);
comparadorLogico CL (x0, a0, a1, a2, a3, b0 ,b1, b2, b3);
subtrator4bits Su4B(y0, y1, y2, y3, comparador, a0, a1, a2, a3, b0, b1, b2, b3);
//igual a zero
xor XOR1(k0, a0, a1, a2, a3, b0, b1, b2, b3);
complementode1 C1(s00, s01, s02, s03, s10, s11, s12, s13, a0 ,a1, a2, a3, b0 ,b1, b2, b3);
endmodule
| 7.063838 |
module alu_wb_queue (
in_rfa_queue_entry_serviced,
in_vgpr_dest_data,
in_sgpr_dest_data,
in_exec_wr_vcc_value,
in_vgpr_wr_mask,
in_wfid,
in_instr_pc,
in_vgpr_dest_addr,
in_sgpr_dest_addr,
in_instr_done,
in_vgpr_dest_wr_en,
in_sgpr_dest_wr_en,
in_vcc_wr_en,
out_vgpr_dest_data,
out_sgpr_dest_data,
out_exec_wr_vcc_value,
out_vgpr_wr_mask,
out_wfid,
out_instr_pc,
out_vgpr_dest_addr,
out_sgpr_dest_addr,
out_instr_done,
out_vgpr_dest_wr_en,
out_sgpr_dest_wr_en,
out_vcc_wr_en,
out_queue_ready,
out_queue_empty,
clk,
rst
);
parameter BITS = 2;
parameter SIZE = 4;
input in_rfa_queue_entry_serviced;
input [2047:0] in_vgpr_dest_data;
input [63:0] in_sgpr_dest_data;
input [63:0] in_exec_wr_vcc_value;
input [63:0] in_vgpr_wr_mask;
input [5:0] in_wfid;
input [31:0] in_instr_pc;
input [9:0] in_vgpr_dest_addr;
input [8:0] in_sgpr_dest_addr;
input in_instr_done;
input in_vgpr_dest_wr_en;
input in_sgpr_dest_wr_en;
input in_vcc_wr_en;
output [2047:0] out_vgpr_dest_data;
output [63:0] out_sgpr_dest_data;
output [63:0] out_exec_wr_vcc_value;
output [63:0] out_vgpr_wr_mask;
output [5:0] out_wfid;
output [31:0] out_instr_pc;
output [9:0] out_vgpr_dest_addr;
output [8:0] out_sgpr_dest_addr;
output out_instr_done;
output out_vgpr_dest_wr_en;
output out_sgpr_dest_wr_en;
output out_vcc_wr_en;
output out_queue_ready;
output out_queue_empty;
input clk;
input rst;
wire out_queue_writable;
wire [2300:0] queue_wr_data;
wire [2300:0] queue_rd_data;
assign queue_wr_data = {
in_vgpr_dest_data,
in_sgpr_dest_data,
in_exec_wr_vcc_value,
in_vgpr_wr_mask,
in_wfid,
in_instr_pc,
in_vgpr_dest_addr,
in_sgpr_dest_addr,
in_instr_done,
in_vgpr_dest_wr_en,
in_sgpr_dest_wr_en,
in_vcc_wr_en
};
assign {out_vgpr_dest_data, out_sgpr_dest_data, out_exec_wr_vcc_value, out_vgpr_wr_mask, out_wfid, out_instr_pc, out_vgpr_dest_addr, out_sgpr_dest_addr, out_instr_done, out_vgpr_dest_wr_en, out_sgpr_dest_wr_en, out_vcc_wr_en} = queue_rd_data;
wire [BITS - 1:0] tail;
wire [BITS - 1:0] head;
wire [BITS - 1:0] next_tail;
wire [BITS - 1:0] next_next_tail;
wire [BITS - 1:0] next_head;
wire inc_tail;
wire inc_head;
wire [31:0] next_tail_dummy;
wire [31:0] next_next_tail_dummy;
wire [31:0] next_head_dummy;
assign next_tail_dummy = tail + 1;
assign next_next_tail_dummy = tail + 2;
assign next_head_dummy = head + 1;
assign next_tail = next_tail_dummy[BITS-1:0];
assign next_next_tail = next_next_tail_dummy[BITS-1:0];
assign next_head = next_head_dummy[BITS-1:0];
assign inc_tail = in_instr_done & out_queue_writable;
assign inc_head = in_rfa_queue_entry_serviced;
assign out_queue_writable = (head != next_tail);
assign out_queue_ready = (head != next_next_tail) & out_queue_writable;
assign out_queue_empty = (head == tail);
dff_en Tail[BITS - 1:0] (
.q (tail),
.d (next_tail),
.en (inc_tail),
.clk(clk),
.rst(rst)
);
dff_en Head[BITS - 1:0] (
.q (head),
.d (next_head),
.en (inc_head),
.clk(clk),
.rst(rst)
);
queue_param_1r_1w #(
.BITS (BITS),
.SIZE (SIZE),
.WIDTH(2301)
) queue_reg (
.in_wr_en(inc_tail),
.in_wr_addr(tail),
.in_wr_data(queue_wr_data),
.in_rd_addr(head),
.out_rd_data(queue_rd_data),
.clk(clk),
.rst(rst)
);
endmodule
| 7.414255 |
module f_adder (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule
| 7.216325 |
module alu_with_register_file (
input [25:0] instruction,
input clock,
output [15:0] out,
output overflow,
output c_out
);
wire [7:0] a, b, y;
reg_file x1 (
.clock(clock),
.data(instruction[23:0]),
.result(out),
.a(a),
.b(b),
.y(y)
);
alu x2 (
.a(a),
.b(b),
.op_code(instruction[25:24]),
.out(out),
.overflow(overflow),
.c_out(c_out)
);
endmodule
| 7.34057 |
module alu_with_register_file_tb;
// Inputs
reg [25:0] instruction;
reg clock;
// Outputs
wire [15:0] out;
wire overflow;
wire c_out;
// Instantiate the Unit Under Test (UUT)
alu_with_register_file uut (
.instruction(instruction),
.clock(clock),
.out(out),
.overflow(overflow),
.c_out(c_out)
);
initial begin
instruction = 26'b00010011100001001000000000;
clock = 0;
#100 instruction = 26'b01010011100001001000000000;
#100 instruction = 26'b11010011100001001000000000;
#100 instruction = 26'b10010011100001001000000000;
#100 instruction = 26'b00011110000111110000000000;
#100 $stop;
end
always #33 clock = !clock;
endmodule
| 7.34057 |
module Adder #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] d0,
input [WIDTH-1:0] d1,
output [WIDTH-1:0] out
);
assign out = d0 + d1;
endmodule
| 9.509237 |
module Increment (
input [15:0] d,
output [15:0] out
);
assign out = d + 1;
endmodule
| 6.536633 |
module alu_xor (
A,
B,
Z
);
// parameter definitions
parameter WIDTH = 8;
//port definitions
input wire [WIDTH-1:0] A, B;
output wire [WIDTH-1:0] Z;
// instantiate module's hardware
assign Z = A ^ B;
endmodule
| 8.939182 |
module alu_xor_4 (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input clk,
input [3:0] A0,
B0,
A1,
B1, // ALU 8-bit Inputs
input [1:0] ALU_Sel1,
ALU_Sel2, // ALU Selection
output [3:0] ALU_Out1,
ALU_Out2, // ALU 8-bit Output
output CarryOut1,
CarryOut2, // Carry Out Flag
output [3:0] x,
output y,
input [1:0] active
);
alu_4 alu_4_1 (
.A(A0),
.B(B0),
.ALU_Sel(ALU_Sel1),
.ALU_Out(ALU_Out1),
.CarryOut(CarryOut1)
);
alu_4 alu_4_2 (
.A(A1),
.B(B1),
.ALU_Sel(ALU_Sel2),
.ALU_Out(ALU_Out2),
.CarryOut(CarryOut2)
);
assign x[3:0] = ALU_Out1[3:0] ^ ALU_Out2[3:0];
assign y = CarryOut1 ^ CarryOut2;
always @(*) begin
$display("A0", A0[3:0]);
$display("B0", B0[3:0]);
$display("A1", A1[3:0]);
$display("B1", B1[3:0]);
$display("ALU_Sel1", ALU_Sel1[1:0]);
$display("ALU_Sel2", ALU_Sel2[1:0]);
#1000;
$display("ALU_Out1", ALU_Out1[3:0]);
$display("ALU_Out2", ALU_Out2[3:0]);
$display("CarryOut1", CarryOut1);
$display("CarryOut2", CarryOut2);
$display("x", x[3:0]);
$display("y", y);
#1000;
if (x != 0) $display("Faulty ALU");
else $display("ALU is right");
if (y != 0) $display("Faulty Carry");
else $display("Carry is right");
end
endmodule
| 8.042765 |
module alu_4 (
input [3:0] A,
B, // ALU 8-bit Inputs
input [1:0] ALU_Sel, // ALU Selection
output [3:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [4:0] ALU_Result;
assign ALU_Out = ALU_Result[3:0]; // ALU out
assign CarryOut = ALU_Result[4];
always @(*) begin
case (ALU_Sel)
2'b00: // Addition
ALU_Result = A + B;
2'b01: // Subtraction
ALU_Result = A - B;
2'b10: // and
ALU_Result = A & B;
2'b11: // or
ALU_Result = A | B;
default: ALU_Result = A + B;
endcase
end
endmodule
| 8.906529 |
module: alu_xor_test
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_xor_test;
// parameter
parameter WIDTH = 32;
// test module variables
reg [WIDTH-1:0] i;
// Inputs
reg [WIDTH-1:0] A;
reg [WIDTH-1:0] B;
// Outputs
wire [WIDTH-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_xor #(.N(WIDTH)) uut (
.A(A),
.B(B),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_xor_test.vcd");
$dumpvars(0, alu_xor_test);
// Initialize Inputs
i = 32'h0x0;
A = 32'h0x0;
B = 32'h0x0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (i = 0; i < 16; i = i + 1) begin
#100;
A = i;
B = ~i;
$display("Inputs: %b, %b ; Output: %b", A, B, Z);
end
$finish;
end
endmodule
| 7.158688 |
module alu (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] x, y;
input [2:0] opcode;
output overflow, zero, cout;
output [31:0] f;
wire [2:0] opoverflow;
wire [31:0] f0, f1, f2, f3, f4, result;
wire w5, zero, isoverflowed, cout;
add op0 (
x,
y,
f0,
opoverflow[0],
zero
);
bitwiseor op1 (
x,
y,
f1
);
bitwiseand op2 (
x,
y,
f2
);
sub op3 (
x,
y,
f3,
opoverflow[1]
);
slt op4 (
x,
y,
f4,
opoverflow[2]
);
out outputselector (
f0,
f1,
f2,
f3,
f4,
opcode[0],
opcode[1],
opcode[2],
opoverflow[0],
opoverflow[1],
opoverflow[2],
f,
isoverflowed,
cout
);
iszero zerochecker (
f,
zero
);
endmodule
| 7.914753 |
module fulladder (
a,
b,
c,
s,
cout
);
input a, b, c;
output s, cout;
xor g1 (w1, a, b), g2 (s, w1, c);
and g3 (w2, c, b), g4 (w3, c, a), g5 (w4, a, b);
or g6 (cout, w2, w3, w4);
endmodule
| 7.454465 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
d7,
s0,
s1,
w2
);
mux2to1 mux2 (
w1,
w2,
s2,
f
);
endmodule
| 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and (w17, d1, s0);
not (w15, s0);
and (w18, w15, d0);
or (f, w17, w18);
endmodule
| 7.107199 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
end
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b001: out = data1;
3'b010: out = data2;
3'b011: out = data3;
3'b100: out = data4;
3'b101: out = data5;
default: out = 4'b0000;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
case (in)
4'd1: pos = 2'd0;
4'd2: pos = 2'd1;
4'd3: pos = 2'd0;
4'd4: pos = 2'd2;
4'd5: pos = 2'd0;
4'd6: pos = 2'd1;
4'd7: pos = 2'd0;
4'd8: pos = 2'd3;
4'd9: pos = 2'd0;
4'd10: pos = 2'd1;
4'd11: pos = 2'd0;
4'd12: pos = 2'd2;
4'd13: pos = 2'd0;
4'd14: pos = 2'd1;
4'd15: pos = 2'd0;
default: pos = 2'd0;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzzzzz1: pos = 3'd0;
8'bzzzzzz1z: pos = 3'd1;
8'bzzzzz1zz: pos = 3'd2;
8'bzzzz1zzz: pos = 3'd3;
8'bzzz1zzzz: pos = 3'd4;
8'bzz1zzzzz: pos = 3'd5;
8'bz1zzzzzz: pos = 3'd6;
8'b1zzzzzzz: pos = 3'd7;
default: pos = 3'd0;
endcase
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) begin
if (sel_b1 & sel_b2) begin
out_always = b;
end else begin
out_always = a;
end
end
endmodule
| 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) begin
shut_off_computer = 1;
end else begin
shut_off_computer = 0;
end
end
always @(*) begin
if (~arrived & ~gas_tank_empty) begin
keep_driving = 1;
end else begin
keep_driving = 0;
end
end
endmodule
| 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
up = 0;
down = 0;
right = 0;
left = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
| 7.203305 |
module AlwaysNTPredictor (
input [`WORD_SIZE-1:0] PC,
input Correct,
input [`WORD_SIZE-1:0] ActualBranchTarget,
output [`WORD_SIZE-1:0] Prediction
);
/*
[Always not-taken branch predictor module]
Purpose:
A placeholder(or framework) for future possibility of implementing a better branch predictor.
Always predicts PC+1 for any jump or branch instruction.
*/
assign Prediction = PC + 1;
endmodule
| 8.225705 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
end
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'd0: out = data0;
3'd1: out = data1;
3'd2: out = data2;
3'd3: out = data3;
3'd4: out = data4;
3'd5: out = data5;
default: out = 4'b0;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0]) pos = 2'd0;
else if (in[1]) pos = 2'd1;
else if (in[2]) pos = 2'd2;
else if (in[3]) pos = 2'd3;
else pos = 2'd0;
end
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzz_zzz1: pos = 3'd0;
8'bzzzz_zz10: pos = 3'd1;
8'bzzzz_z100: pos = 3'd2;
8'bzzzz_1000: pos = 3'd3;
8'bzzz1_0000: pos = 3'd4;
8'bzz10_0000: pos = 3'd5;
8'bz100_0000: pos = 3'd6;
8'b1000_0000: pos = 3'd7;
default: pos = 3'd0;
endcase
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
// assign
assign out_assign = (sel_b1 & sel_b2) ? b : a;
// always
always @(*) begin
if (sel_b1 & sel_b2) begin
out_always = b;
end else begin
out_always = a;
end
end
endmodule
| 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
// add else
else
// we can simply output '0'
shut_off_computer = 0;
end
always @(*) begin
if (~arrived) keep_driving = ~gas_tank_empty;
else keep_driving = 0;
end
endmodule
| 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
up = 1'b0;
down = 1'b0;
left = 1'b0;
right = 1'b0;
case (scancode)
16'he06b: left = 1'b1;
16'he072: down = 1'b1;
16'he074: right = 1'b1;
16'he075: up = 1'b1;
endcase
end
endmodule
| 7.203305 |
module ALW_NR_OPSL (
clk,
port_a,
port_b
);
input clk;
input port_a;
output port_b;
reg port_b;
always @(clk || port_a) begin
port_b <= port_a;
end
endmodule
| 6.683028 |
module ALW_NR_TCST (
out_a
);
output reg [1:0] out_a;
always @(posedge 1) out_a <= 2'b00;
endmodule
| 7.096444 |
module AL_LOGIC_FIFO (
rst,
di, clkw, we, csw,
do, clkr, re, csr, ore,
empty_flag, aempty_flag,
full_flag, afull_flag
);
// 1kx9 by default
parameter DATA_WIDTH_W = 9; // 1 ... 9*48
parameter DATA_WIDTH_R = DATA_WIDTH_W; // 1 ... 9*48
parameter DATA_DEPTH_W = 1024; // 512, 1024, 2048, 4096, 8192
parameter DATA_DEPTH_R = DATA_WIDTH_W * DATA_DEPTH_W / DATA_WIDTH_R; // 512, 1024, 2048, 4096, 8192
input rst;
input [DATA_WIDTH_W-1:0] di;
output [DATA_WIDTH_R-1:0] do;
input clkw, we;
input clkr, re, ore; //DEFAULT := '0'
input [2:0] csw, csr;
output empty_flag, aempty_flag; //DEFAULT := '0'
output full_flag, afull_flag; //DEFAULT := '0'
parameter MODE = "FIFO8K";
parameter REGMODE_W = "NOREG"; //NOREG, OUTREG
parameter REGMODE_R = "NOREG"; //NOREG, OUTREG
parameter E = 0;
parameter AE = 6;
parameter AF = 1017;
parameter F = 1023;
parameter GSR = "ENABLE"; //DISABLE, ENABLE
parameter RESETMODE = "ASYNC"; //SYNC, ASYNC
parameter ASYNC_RESET_RELEASE = "SYNC"; //SYNC, ASYNC
// TO BE FILLED
endmodule
| 8.086213 |
module AL_LOGIC_MULT (
p,
a,
b,
cea,
ceb,
cepd,
clk,
rstan,
rstbn,
rstpdn
);
parameter INPUT_WIDTH_A = 18;
parameter INPUT_WIDTH_B = 18;
parameter OUTPUT_WIDTH = 36;
output [OUTPUT_WIDTH-1:0] p;
input [INPUT_WIDTH_A-1:0] a;
input [INPUT_WIDTH_B-1:0] b;
input cea; //DEFAULT := '0'
input ceb; //DEFAULT := '0'
input cepd; //DEFAULT := '0'
input clk; //DEFAULT := '0'
input rstan; //DEFAULT := '0'
input rstbn; //DEFAULT := '0'
input rstpdn; //DEFAULT := '0'
parameter INPUTFORMAT = "SIGNED"; // SIGNED, UNSIGNED
parameter INPUTREGA = "ENABLE"; // ENABLE, DISABLE
parameter INPUTREGB = "ENABLE"; // ENABLE, DISABLE
parameter OUTPUTREG = "ENABLE"; // ENABLE, DISABLE
parameter SRMODE = "ASYNC"; // ASYNC, SYNC
parameter IMPLEMENT = "AUTO"; // AUTO, DSP, GATE
// TO BE FILLED
endmodule
| 6.701601 |
module AL_PHY_IOCLK (
clki,
stop,
clko
);
input clki;
input stop;
output clko;
parameter STOPCLK = "DISABLE"; // ENABLE,DISABLE
reg ck_en1, ck_en2;
reg stop_en;
initial begin
ck_en1 = 1'b0;
ck_en2 = 1'b0;
end
initial begin
case (STOPCLK)
"DISABLE": stop_en = 1'b0;
"ENABLE": stop_en = 1'b1;
default: begin
$display(
"Parameter Warning : The attribute STOPCLK on ECLK instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.",
STOPCLK);
//$finish;
end
endcase
end
assign clksel = ~(stop & stop_en);
always @(negedge clki)
if (clksel == 1'b0) begin
ck_en1 <= 1'b0;
ck_en2 <= ck_en1;
end else begin
ck_en1 <= 1'b1;
ck_en2 <= ck_en1;
end
assign clko = stop_en ? (clki & ck_en2) : clki;
endmodule
| 7.125784 |
module pfb_lsliceomux (
f,
fx,
f_n,
sum0,
sum1,
lut4f,
lut4g,
func6,
mc1_fxmuxlut4g,
mc1_fxmuxrip_n,
mc1_fmuxrip,
mc1_fmuxlut5,
in5
);
output f, fx, f_n;
input sum0, sum1, lut4f, lut4g, func6, mc1_fxmuxlut4g, mc1_fxmuxrip_n, mc1_fmuxrip, mc1_fmuxlut5;
input in5;
reg f, fx;
wire f_n;
always @(mc1_fxmuxlut4g, mc1_fxmuxrip_n, sum1, lut4g, func6) begin
case ({
mc1_fxmuxlut4g, mc1_fxmuxrip_n
})
2'b00: fx = 1'b0;
2'b10: fx = sum1;
2'b01: fx = lut4g;
2'b11: fx = func6;
endcase
end
///
// begin
//wire in5__mc1_fmuxlut5 = (in5 === 1'bx)?mc1_fmuxlut5:(in5&mc1_fmuxlut5);
//wire sg = mc1_fmuxrip? 1'b0 : (in5__mc1_fmuxlut5);
//wire sf = mc1_fmuxrip? 1'b0 : ~(in5__mc1_fmuxlut5);
// end
///
wire sg = mc1_fmuxrip ? 1'b0 : (in5 & mc1_fmuxlut5);
wire sf = mc1_fmuxrip ? 1'b0 : ~(in5 & mc1_fmuxlut5);
wire [2:0] fsel = {sg, sf, mc1_fmuxrip};
always @(fsel, sum0, lut4f, lut4g) begin
case (fsel)
3'b100: f = lut4g;
3'b010: f = lut4f;
3'b001: f = sum0;
default:
f = 1'bx; //$display("maybe circuit Error : LSLICE FMUX select signal non ONE-HOT %b", fsel);
endcase
end
assign f_n = ~f;
endmodule
| 6.686815 |
module pfb_slice01_lut4 (
lut4_o,
lut00_n,
mc1_ripmode,
I0,
I1,
I2,
I3,
dpram_mode,
dpram_di,
dpram_we,
dpram_wclk,
dpram_waddr
);
output lut4_o;
output lut00_n;
input mc1_ripmode;
input I0, I1, I2, I3;
parameter INIT = 16'h0000;
//dpram interface
input dpram_mode;
input dpram_di, dpram_we, dpram_wclk;
input [3:0] dpram_waddr;
reg [15:0] value_lut4;
reg lut4_o;
reg lut00, lut01, lut10, lut11;
initial begin
value_lut4 = INIT;
end
wire dpram_weclk = dpram_mode & dpram_wclk;
always @(posedge dpram_weclk) begin
if (dpram_we) begin
value_lut4[dpram_waddr] = dpram_di;
end
end
always @(I1 or I0 or value_lut4[3:0]) begin
case ({
I1, I0
})
2'b00: lut00 = value_lut4[0];
2'b01: lut00 = value_lut4[1];
2'b10: lut00 = value_lut4[2];
2'b11: lut00 = value_lut4[3];
endcase
end
always @(I1 or I0 or value_lut4[7:4]) begin
case ({
I1, I0
})
2'b00: lut01 = value_lut4[4];
2'b01: lut01 = value_lut4[5];
2'b10: lut01 = value_lut4[6];
2'b11: lut01 = value_lut4[7];
endcase
end
always @(I1 or I0 or value_lut4[11:8]) begin
case ({
I1, I0
})
2'b00: lut10 = value_lut4[8];
2'b01: lut10 = value_lut4[9];
2'b10: lut10 = value_lut4[10];
2'b11: lut10 = value_lut4[11];
endcase
end
always @(I1 or I0 or value_lut4[15:12]) begin
case ({
I1, I0
})
2'b00: lut11 = value_lut4[12];
2'b01: lut11 = value_lut4[13];
2'b10: lut11 = value_lut4[14];
2'b11: lut11 = value_lut4[15];
endcase
end
always @(lut00 or lut01 or lut10 or lut11 or I3 or I2) begin
case ({
I3, I2
})
2'b00: lut4_o = lut00;
2'b01: lut4_o = lut01;
2'b10: lut4_o = lut10;
2'b11: lut4_o = lut11;
endcase
end
nand (lut00_n, mc1_ripmode, lut00);
endmodule
| 6.540541 |
module top (
input clk,
input rst_n,
output [6:0] seg,
input all_sw, //高为弹球，低为钢琴
output [3:0] seg_sel,
input [2:0] move, //0为左，2为右
input [9:0] sw,
input displaymode,
output beep,
// output add_cnt0,
output warn_flag,
output vga_clk,
output hs,
output vs,
output [15:0] regrgb1
);
wire sys_clk;
wire [2:0] OutRed;
wire [2:0] OutGreen;
wire [2:1] OutBlue;
wire [15:0] regrgb;
assign regrgb1[15:13] = all_sw ? OutRed : regrgb[15:13];
assign regrgb1[12:11] = all_sw ? 2'b0 : regrgb[12:11];
assign regrgb1[10:8] = all_sw ? OutGreen : regrgb[11:9];
assign regrgb1[7:5] = all_sw ? 3'b0 : regrgb[8:5];
assign regrgb1[4:3] = all_sw ? OutBlue : regrgb[4:3];
assign regrgb1[2:0] = all_sw ? 3'b0 : regrgb[2:0];
//always@(*)begin
// regrgb[15:13] = all_sw ? OutRed : regrgb[15:13];
// regrgb[12:11] = all_sw ? 2'b0 : regrgb[12:11];
// regrgb[11:9] = all_sw ? OutGreen : regrgb[11:9];
// regrgb[8:5] = all_sw ? 3'b0 : regrgb[8:5];
// regrgb[4:3] = all_sw ? OutBlue : regrgb[4:3];
// regrgb[2:0] = all_sw ? 3'b0 : regrgb[2:0];
//end
wire VSync;
wire cys;
assign vs = all_sw ? VSync : cys;
wire HSync;
wire hys;
assign hs = all_sw ? HSync : hys;
wire clk_vga;
wire add_cnt0;
assign vga_clk = all_sw ? clk_vga : add_cnt0;
//[9:0]sw
wire [3:0] bar_move_speed;
wire [3:0] an;
wire [1:0] an_back;
assign an = sw[9:6];
assign an_back = sw[5:4];
assign bar_move_speed = sw[3:0];
wire seg_LED;
wire seg_p;
assign seg = all_sw ? seg_LED : seg_p;
wire [3:0] seg_select;
wire [3:0] we;
assign seg_sel = all_sw ? seg_select : we;
wire to_left;
wire to_right;
wire [2:0] key;
assign to_left = all_sw ? move[0] : 0;
assign to_right = all_sw ? move[2] : 0;
assign key = all_sw ? 0 : move;
pll u_pll (
.refclk(clk),
.reset(!rst_n),
.extlock(),
.clk0_out(),
.clk1_out(sys_clk)
);
SBgame u_SBgame (
.sys_clk (sys_clk),
.rst_n (rst_n),
.to_left (to_left),
.to_right (to_right),
.bar_move_speed(bar_move_speed),
.HSync (HSync),
.VSync (VSync),
.OutBlue (OutBlue),
.OutGreen (OutGreen),
.OutRed (OutRed),
.clk_vga (clk_vga),
.seg_select (seg_select),
.seg_LED (seg_LED)
);
VGA_piano u_VGA_piano (
.sys_clk (sys_clk),
.rst_n (rst_n),
.an (an),
.an_back (an_back),
.displaymode(displaymode),
.key (key),
.seg (seg_p),
.we (we),
.rgb (regrgb),
.hys (hys),
.cys (cys),
.beep (beep),
.add_cnt0 (add_cnt0),
.warn_flag (warn_flag)
);
endmodule
| 7.233807 |
module al_ver (
input clk_i,
input rst_i,
input uart_rx,
output uart_tx
);
wire rstn_i;
wire locked_w;
wire clk_w;
clk_wiz_0 clk_wzrd (
.reset(rst_i),
.clk_in1(clk_i),
.clk_out1(clk_w),
.locked(locked_w)
);
assign rstn_i = !rst_i && locked_w;
localparam BAUD_DIV = `CLK_HZ / `BAUD_RATE;
wire [7:0] alici_veri_o;
wire alici_gecerli_o;
uart_alici alici (
.clk_i (clk_w),
.rstn_i (rstn_i),
.alinan_veri_o (alici_veri_o),
.alinan_gecerli_o(alici_gecerli_o),
.baud_div_i (BAUD_DIV),
.rx_i (uart_rx)
);
wire [7:0] fifo_rd_data_w;
wire fifo_rd_en_w;
wire fifo_empty_w;
wire fifo_full_w;
fifo #(
.DATA_WIDTH(8),
.DATA_DEPTH(32)
) rx_buffer (
.clk_i (clk_w),
.rstn_i (rstn_i),
.data_i (alici_veri_o),
.wr_en_i(alici_gecerli_o),
.data_o (fifo_rd_data_w),
.rd_en_i(fifo_rd_en_w),
.full_o (fifo_full_w),
.empty_o(fifo_empty_w)
);
uart_verici verici (
.clk_i (clk_w),
.rstn_i (rstn_i),
.veri_gecerli_i(!fifo_empty_w),
.consume_o (fifo_rd_en_w),
.gelen_veri_i (fifo_rd_data_w),
.baud_div_i (BAUD_DIV),
.tx_o (uart_tx)
);
endmodule
| 6.757465 |
module array (
a,
b,
p
);
parameter N = 16;
parameter M = 16;
input [N-1:0] a;
input [M-1:0] b;
output [M+N-1:0] p;
genvar i, j;
generate
wire [M*N-1:0] w;
for (i = 0; i < M; i = i + 1) begin : loop1
for (j = 0; j < N; j = j + 1) begin : loop2
and (w[i*N+j], a[j], b[i]);
end
end
endgenerate
//assign p[0] = w[0]; // first bit of 1st partial product
// 0-15 : b0
// 16-31 :b1
// 32-47 :b2
// 47-63 :b3
// 64-79 :b4
// 80-95 :b5
// 96-111 :b6
// 112-127 :b7
// 128-143 :b8
// 144-159 :b9
// 160-175 :b10
// 176-191 :b11
// 192-207 :b12
// 208-223 :b13
// 224-239 :b14
// 240-255 :b15
genvar k;
generate
for (k = 1; k < N; k = k + 1) begin : S
wire [31:0] sum1, sum2, sout, temp;
wire cout, cin;
if (k == 1) begin
assign sum1 = w[N-1:0];
assign sum2 = {w[(2*N)-1:N], 1'b0};
FullAdder32bit FA (
sum1,
sum2,
1'b0,
sout,
cout
);
assign cin = cout;
end else begin
assign sum1 = S[k-1].sout;
assign temp = w[((k+1)*N)-1:(k)*N];
assign sum2 = temp << k;
FullAdder32bit FA (
sum1,
sum2,
S[k-1].cin,
sout,
cout
);
assign cin = cout;
if (k == N - 1) begin
assign p = sout;
end
end
end
endgenerate
endmodule
| 6.857364 |
module FullAdder4bit (
A,
B,
Cin,
Sum,
Cout
);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
wire carry0;
wire carry1;
wire carry2;
FullAdder FA0 (
A[0],
B[0],
Cin,
Sum[0],
carry0
);
FullAdder FA1 (
A[1],
B[1],
carry0,
Sum[1],
carry1
);
FullAdder FA2 (
A[2],
B[2],
carry1,
Sum[2],
carry2
);
FullAdder FA3 (
A[3],
B[3],
carry2,
Sum[3],
Cout
);
endmodule
| 7.241024 |
module FullAdder16bit (
A,
B,
Cin,
Sum,
Cout
);
input [15:0] A, B;
input Cin;
output [15:0] Sum;
output Cout;
wire carry3;
wire carry7;
wire carry11;
FullAdder4bit FA40 (
A[3:0],
B[3:0],
Cin,
Sum[3:0],
carry3
);
FullAdder4bit FA41 (
A[7:4],
B[7:4],
carry3,
Sum[7:4],
carry7
);
FullAdder4bit FA42 (
A[11:8],
B[11:8],
carry7,
Sum[11:8],
carry11
);
FullAdder4bit FA43 (
A[15:12],
B[15:12],
carry11,
Sum[15:12],
Cout
);
endmodule
| 6.849148 |
module FullAdder32bit (
input [31:0] A,
B,
input Cin,
output [31:0] Sum,
output Cout
);
wire carry15;
FullAdder16bit FA160 (
.A(A[15:0]),
.B(B[15:0]),
.Cin(Cin),
.Sum(Sum[15:0]),
.Cout(carry15)
);
FullAdder16bit FA161 (
.A(A[31:16]),
.B(B[31:16]),
.Cin(carry15),
.Sum(Sum[31:16]),
.Cout(Cout)
);
endmodule
| 6.574057 |
module am25ls08 (
d,
q,
q_,
clk,
e_
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output [WIDTH-1:0] q_;
input clk;
input e_;
reg [WIDTH-1:0] q;
always @(posedge clk) begin
if (e_ == 1'b0) begin
q = d;
end
end
assign q_ = ~q;
endmodule
| 7.71803 |
module am25ls153_testbench;
reg [1:0] sel;
reg g;
reg [3:0] c;
wire y;
am25ls153 dut (
.sel(sel),
.g (g),
.c (c),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input [1:0] sval;
input [3:0] cval;
input gval;
begin
sel <= sval;
c <= cval;
g <= gval;
#1 $display("%5g: %2b %4b %1b | %1b | %0s", $time, sel, c, g, y, descr);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am25ls153.vcd");
$dumpvars;
$display("-time: -sel- --c--- -g- | -y- |");
// --sel- ---c--- -g--
tester("G disable", 2'bxx, 4'bxxxx, 1'b1);
tester("SEL=0, C=L", 2'b00, 4'bxxx0, 1'b0);
tester("SEL=0, C=H", 2'b00, 4'bxxx1, 1'b0);
tester("SEL=1, C=L", 2'b01, 4'bxx0x, 1'b0);
tester("SEL=1, C=H", 2'b01, 4'bxx1x, 1'b0);
tester("SEL=2, C=L", 2'b10, 4'bx0xx, 1'b0);
tester("SEL=2, C=H", 2'b10, 4'bx1xx, 1'b0);
tester("SEL=3, C=L", 2'b11, 4'b0xxx, 1'b0);
tester("SEL=3, C=H", 2'b11, 4'b1xxx, 1'b0);
#10 $finish;
end
endmodule
| 7.200512 |
module am25ls174 (
d,
q,
q_,
clk,
clr_
);
parameter WIDTH = 6;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output [WIDTH-1:0] q_;
input clk;
input clr_;
reg [WIDTH-1:0] q;
always @(clr_) begin
q = {WIDTH{1'b0}};
end
always @(posedge clk) begin
if (clr_ == 1'b1) begin
q = d;
end
end
assign q_ = ~q;
endmodule
| 7.168672 |
module am25ls174_testbench;
parameter WIDTH = 6;
reg [WIDTH-1:0] d;
reg clr_, clk;
wire [WIDTH-1:0] q, q_;
am25ls174 #(
.WIDTH(WIDTH)
) dut (
.d(d),
.clk(clk),
.clr_(clr_),
.q(q),
.q_(q_)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input clrval;
input clkval;
begin
d <= dval;
clr_ <= clrval;
clk <= clkval;
#1 $display("%5g: %6b %1b %1b | %6b %6b | %0s", $time, d, clr_, clk, q, q_, descr);
$display("");
end
endtask
task clocker;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input clrval;
begin
d <= dval;
clr_ <= clrval;
clk <= 1'b0;
#1 $display("%5g: %6b %1b %1b | %6b %6b | %0s", $time, d, clr_, clk, q, q_, descr);
clk <= 1'b1;
#1 $display("%5g: %6b %1b r | %6b %6b |", $time, d, clr_, q, q_);
clk <= 1'b0;
#1 $display("%5g: %6b %1b f | %6b %6b |", $time, d, clr_, q, q_);
$display("");
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am25ls174.vcd");
$dumpvars;
$display("-time: --d--- clr clk | --q--- --q_-- |");
// ---d----- -clr- -clk-
tester("clear", 6'bxxxxxx, 1'b0, 1'bx);
clocker("clear hold", 6'b101010, 1'b0);
clocker("load 1's", 6'b111111, 1'b1);
clocker("load 0's", 6'b000000, 1'b1);
clocker("load 10's", 6'b101010, 1'b1);
clocker("load 01's", 6'b010101, 1'b1);
#10 $finish;
end
endmodule
| 6.657238 |
module am25ls191 (
in,
load_,
ent_,
ud,
clk,
q,
rco_,
mxmn
);
parameter WIDTH = 4;
input [WIDTH-1:0] in;
input load_, ent_, ud, clk;
output [WIDTH-1:0] q;
output rco_, mxmn;
reg [WIDTH-1:0] ctr;
wire all0, all1;
always @(posedge (clk)) begin
if (ent_ == 'b0) begin
if (load_ == 'b0) ctr <= in;
else if (ud == 'b0) ctr <= ctr + 1;
else ctr <= ctr - 1;
end
end
assign all0 = |ctr;
assign all1 = &ctr;
assign mxmn = (ud == 'b0) ? all1 : ~all0;
assign rco_ = ~(mxmn & ~clk);
assign q = ctr;
endmodule
| 6.821231 |
module am25ls2521 (
a,
b,
ein_,
eout_
);
parameter WIDTH = 8;
input [WIDTH-1:0] a, b;
input ein_;
output eout_;
assign eout_ = ein_ | |(a ^ b);
endmodule
| 7.383562 |
module am25ls2521_test;
parameter WIDTH = 8;
reg [WIDTH-1:0] a, b;
reg ein;
wire eout;
`define HEADER(title)\
$display("%0s", title);\
$display("-----: ---a---- ---b---- ein | eout | description");
`define SHOW(a, b, ein, eout, descr)\
$display("%5d: %8b %8b %b | %b | %0s",\
$time, a, b, ein, eout, descr);
`define assert(name, val, expectval)\
if (val !== expectval)\
$display("Error: %0s should be %b but is %b", name , expectval, val);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] aval, bval;
input einval;
input expecteout;
begin
a <= aval;
b <= bval;
ein <= einval;
#1 `SHOW(a, b, ein, eout, descr);
`assert("EOUT", eout, expecteout);
end
endtask
am25ls2521 #(
.WIDTH(WIDTH)
) dut (
.a(a),
.b(b),
.ein_(ein),
.eout_(eout)
);
initial begin
//Dump results of the simulation to am25ls2521.vcd
$dumpfile("am25ls2521.vcd");
$dumpvars;
// ------descr------------------- ----a----- ----b----- ein expo
`HEADER("");
tester("Test EIN=1", 'bXXXXXXXX, 'bXXXXXXXX, 'b1, 'b1);
tester("Test EQUAL all 0", 'b00000000, 'b00000000, 'b0, 'b0);
tester("Test EQUAL all 1", 'b11111111, 'b11111111, 'b0, 'b0);
tester("Test EQUAL checker", 'b11001100, 'b11001100, 'b0, 'b0);
tester("Test EQUAL alternate", 'b01010101, 'b01010101, 'b0, 'b0);
tester("Test NOT EQUAL Bit0", 'bXXXXXXX0, 'bXXXXXXX1, 'b0, 'b1);
tester("Test NOT EQUAL Bit1", 'bXXXXXX0X, 'bXXXXXX1X, 'b0, 'b1);
tester("Test NOT EQUAL Bit2", 'bXXXXX0XX, 'bXXXXX1XX, 'b0, 'b1);
tester("Test NOT EQUAL Bit3", 'bXXXX0XXX, 'bXXXX1XXX, 'b0, 'b1);
tester("Test NOT EQUAL Bit4", 'bXXX1XXXX, 'bXXX0XXXX, 'b0, 'b1);
tester("Test NOT EQUAL Bit5", 'bXX1XXXXX, 'bXX0XXXXX, 'b0, 'b1);
tester("Test NOT EQUAL Bit6", 'bX1XXXXXX, 'bX0XXXXXX, 'b0, 'b1);
tester("Test NOT EQUAL Bit7", 'b1XXXXXXX, 'b0XXXXXXX, 'b0, 'b1);
end
endmodule
| 6.551644 |
module am25ls377 (
d,
q,
clk,
e_
);
parameter WIDTH = 8;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
input clk;
input e_;
reg [WIDTH-1:0] q;
always @(posedge clk) begin
if (e_ == 1'b0) begin
q = d;
end
end
endmodule
| 6.773584 |
module am25ls377_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg e_, clk;
wire [WIDTH-1:0] q;
am25ls377 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.clk(clk),
.e_ (e_),
.q (q)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input eval;
begin
d <= dval;
e_ <= eval;
clk <= 1'b0;
#1 $display("%5g: %8b %1b | %6b | %0s", $time, d, e_, q, descr);
clk <= 1'b1;
#1 $display("%5g: %8b %1b r | %6b |", $time, d, e_, q);
clk <= 1'b0;
#1 $display("%5g: %8b %1b f | %6b |", $time, d, e_, q);
$display("");
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am25ls377.vcd");
$dumpvars;
$display("-time: ---d---- e_ clk | ---q---- | descr");
// -----d----- -e--
tester("load 1's", 8'b11111111, 1'b0);
tester("load 0's", 8'b00000000, 1'b0);
tester("hold", 8'bxxxxxxxx, 1'b1);
tester("load 10's", 8'b10101010, 1'b0);
tester("load 01's", 8'b01010101, 1'b0);
#10 $finish;
end
endmodule
| 6.667555 |
module am25s174 (
d,
q,
q_,
clk,
clr_
);
parameter WIDTH = 6;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output [WIDTH-1:0] q_;
input clk;
input clr_;
reg [WIDTH-1:0] q;
always @(clr_) begin
q = {WIDTH{1'b0}};
end
always @(posedge clk) begin
if (clr_ == 1'b1) begin
q = d;
end
end
assign q_ = ~q;
endmodule
| 6.821664 |
module am25s174_testbench;
parameter WIDTH = 6;
reg [WIDTH-1:0] d;
reg clr_, clk;
wire [WIDTH-1:0] q, q_;
am25s174 #(
.WIDTH(WIDTH)
) dut (
.d(d),
.clk(clk),
.clr_(clr_),
.q(q),
.q_(q_)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input clrval;
input clkval;
begin
d <= dval;
clr_ <= clrval;
clk <= clkval;
#1 $display("%5g: %6b %1b %1b | %6b %6b | %0s", $time, d, clr_, clk, q, q_, descr);
$display("");
end
endtask
task clocker;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input clrval;
begin
d <= dval;
clr_ <= clrval;
clk <= 1'b0;
#1 $display("%5g: %6b %1b %1b | %6b %6b | %0s", $time, d, clr_, clk, q, q_, descr);
clk <= 1'b1;
#1 $display("%5g: %6b %1b r | %6b %6b |", $time, d, clr_, q, q_);
clk <= 1'b0;
#1 $display("%5g: %6b %1b f | %6b %6b |", $time, d, clr_, q, q_);
$display("");
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am25s174.vcd");
$dumpvars;
$display("-time: --d--- clr clk | --q--- --q_-- |");
// ---d----- -clr- -clk-
tester("clear", 6'bxxxxxx, 1'b0, 1'bx);
clocker("clear hold", 6'b101010, 1'b0);
clocker("load 1's", 6'b111111, 1'b1);
clocker("load 0's", 6'b000000, 1'b1);
clocker("load 10's", 6'b101010, 1'b1);
clocker("load 01's", 6'b010101, 1'b1);
#10 $finish;
end
endmodule
| 6.685146 |
module am27s13 (
a,
q,
cs_
);
parameter WIDTH = 4;
parameter HEIGHT = 9;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs_;
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
) u0 (
.a(a),
.q(q),
.cs1_(cs_),
.cs2_(1'b0)
);
endmodule
| 6.589618 |
module am27s181 (
a,
q,
cs1_,
cs2_,
cs3,
cs4
);
parameter WIDTH = 8;
parameter HEIGHT = 10;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs1_, cs2_, cs3, cs4;
wire cs;
assign cs = cs1_ | cs2_ | (~cs3) | (~cs4);
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(10),
.INITH (INITH),
.INITB (INITB)
) u0 (
.a(a),
.q(q),
.cs1_(cs),
.cs2_(1'b0)
);
endmodule
| 7.330218 |
module am27s21 (
a,
q,
cs1_,
cs2_
);
parameter WIDTH = 4;
parameter HEIGHT = 8;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs1_, cs2_;
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
) u0 (
.a(a),
.q(q),
.cs1_(cs1_),
.cs2_(cs2_)
);
endmodule
| 6.628458 |
module am27s25 (
a,
q,
ps_,
clr_,
clk,
e1_,
e2_
);
parameter WIDTH = 8;
parameter HEIGHT = 9;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input ps_, clr_;
input clk;
input e1_, e2_;
wire [WIDTH-1:0] romout;
reg [WIDTH-1:0] pipeline;
reg dff;
initial begin
dff = 1'b1;
end
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
) u0 (
.a(a),
.q(romout),
.cs1_(1'b0),
.cs2_(1'b0)
);
always @(posedge clk or negedge ps_ or negedge clr_) begin
if (clr_ == 1'b0) pipeline = {WIDTH{1'b0}};
else if (ps_ == 1'b0) pipeline = {WIDTH{1'b1}};
if (clk == 1'b1) begin
dff = e2_;
if (clr_ != 1'b0 && ps_ != 1'b0) begin
pipeline = romout;
end
end
end
assign q = (e1_ == 1'b0 && dff == 1'b0) ? pipeline : {WIDTH{1'bz}};
endmodule
| 6.716306 |
module am27s21 (
a,
q,
cs1_,
cs2_
);
parameter WIDTH = 4;
parameter HEIGHT = 10;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs1_, cs2_;
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
) u0 (
.a(a),
.q(q),
.cs1_(cs1_),
.cs2_(cs2_)
);
endmodule
| 6.628458 |
module am2902_testbench;
reg [3:0] g, p;
reg cn;
wire go, po;
wire cnx, cny, cnz;
am2902 dut (
.cn(cn),
.g_(g),
.p_(p),
.cnx(cnx),
.cny(cny),
.cnz(cnz),
.go_(go),
.po_(po)
);
task tester;
input [80*8-1:0] descr;
input [3:0] gval, pval;
input cnval;
begin
g <= gval;
p <= pval;
cn <= cnval;
#1
$display(
"%5g: %4b %4b %1b | %1b %1b %1b %1b %1b | %0s",
$time,
g,
p,
cn,
cnx,
cny,
cnz,
go,
po,
descr
);
end
endtask
initial begin
$display("-----: -g-- -p-- cn | cnx cny cnz go po | description");
// ---g--- ---p--- -cn- --din-- -oe- -cin- -q0- -q3- -r0- -r3-
tester("CNX = high", 4'bxxx0, 4'bxxxx, 1'bx);
tester("", 4'bxxxx, 4'bxxx0, 1'b1);
tester("CNX = low", 4'bxxx1, 4'bxxx1, 1'bx);
tester("", 4'bxxx1, 4'bxxxx, 1'b0);
tester("CNY = high", 4'bxx0x, 4'bxxxx, 1'bx);
tester("", 4'bxxx0, 4'bxx0x, 1'bx);
tester("", 4'bxxxx, 4'bxx00, 1'b1);
tester("CNY = low", 4'bxx1x, 4'bxx1x, 1'bx);
tester("", 4'bxx11, 4'bxxx1, 1'bx);
tester("", 4'bxx11, 4'bxxxx, 1'b0);
tester("CNZ = high", 4'bx0xx, 4'bxxxx, 1'bx);
tester("", 4'bxx0x, 4'bx0xx, 1'bx);
tester("", 4'bxxx0, 4'bx00x, 1'bx);
tester("", 4'bxxxx, 4'bx000, 1'b1);
tester("CNZ = low", 4'bx1xx, 4'bx1xx, 1'bx);
tester("", 4'bx11x, 4'bxx1x, 1'bx);
tester("", 4'bx111, 4'bxxx1, 1'bx);
tester("", 4'bx111, 4'bxxxx, 1'b0);
tester("GO = high", 4'b1xxx, 4'b1xxx, 1'bx);
tester("", 4'b11xx, 4'bx1xx, 1'bx);
tester("", 4'b111x, 4'bxx1x, 1'bx);
tester("", 4'b1111, 4'bxxxx, 1'bx);
tester("GO = low", 4'b0xxx, 4'bxxxx, 1'bx);
tester("", 4'bx0xx, 4'b0xxx, 1'bx);
tester("", 4'bxx0x, 4'b00xx, 1'bx);
tester("", 4'bxxx0, 4'b000x, 1'bx);
tester("PO = high", 4'bxxxx, 4'bxxx1, 1'bx);
tester("", 4'bxxxx, 4'bxx1x, 1'bx);
tester("", 4'bxxxx, 4'bx1xx, 1'bx);
tester("", 4'bxxxx, 4'b1xxx, 1'bx);
tester("PO = low", 4'bxxxx, 4'b0000, 1'bx);
#10 $finish;
end
endmodule
| 6.55075 |
module implements the AMD 2909 bit slice microprogram sequencer.
*
* It closely follows the Am2909 data sheet.
*
* See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2909_am2911.pdf
*/
module Am2909(input wire clock, input wire [3:0] din, input wire [3:0] rin, input wire [3:0] orin,
input wire s0, input wire s1, input wire zero, input wire cin, input wire re, input wire fe,
input wire pup, output reg [3:0] yout, output reg cout);
integer i;
initial begin
pc = 0;
ar = 0;
sp = 3;
yout = 0;
cout = 0;
mux = 0;
stackWr = 0;
for (i=0;i<4;i=i+1) stack[i] = 0;
end
reg [3:0] pc;
reg [3:0] ar;
reg [1:0] sp, stackAddr;
reg [3:0] mux;
reg stackWr;
reg [3:0] stack[0:3];
// Guideline #3: When modeling combinational logic with an "always"
// block, use blocking assignments.
always @(*) begin
stackWr = 0;
stackAddr = sp;
if (fe == 0) begin
if (pup == 1) begin
stackWr = 1;
// Lookahead to pre-increment stack pointer
stackAddr = sp + 1;
end
end
case ({s1, s0})
2'b00: mux = pc;
2'b01: mux = ar;
2'b10: mux = stack[stackAddr];
2'b11: mux = din;
default: mux = 0;
endcase
if (zero == 0) begin
yout = 0;
end else begin
yout = mux | orin;
end
cout = 0;
if (yout == 4'hf && cin == 1) begin
cout = 1;
end
end
// Guideline #1: When modeling sequential logic, use nonblocking
// assignments.
always @(posedge clock) begin
if (stackWr == 1) begin
stack[stackAddr] <= pc;
end
if (re == 0) begin
ar <= rin;
end
if (fe == 0) begin
if (pup == 1) begin
sp <= sp + 1;
end else begin
sp <= sp - 1;
end
end
pc <= yout;
if (cin == 1) begin
pc <= yout + 1;
end
end
endmodule
| 7.842559 |
module implements the AMD 2911 bit slice microprogram sequencer.
*
* It closely follows the Am2911 data sheet.
*
* See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2909_am2911.pdf
*/
module Am2911(input wire clock, input wire [3:0] din,
input wire s0, input wire s1, input wire zero, input wire cin, input wire re, input wire fe,
input wire pup, output reg [3:0] yout, output reg cout);
integer i;
initial begin
pc = 0;
ar = 0;
sp = 3;
yout = 0;
cout = 0;
mux = 0;
stackWr = 0;
for (i=0;i<4;i=i+1) stack[i] = 0;
end
reg [3:0] pc;
reg [3:0] ar;
reg [1:0] sp, stackAddr;
reg [3:0] mux;
reg stackWr;
reg [3:0] stack[0:3];
always @(*) begin
stackWr = 0;
stackAddr = sp;
if (fe == 0) begin
if (pup == 1) begin
stackWr = 1;
// Lookahead to pre-increment stack pointer
stackAddr = sp + 1;
end
end
case ({s1, s0})
2'b00: mux = pc;
2'b01: mux = ar;
2'b10: mux = stack[stackAddr];
2'b11: mux = din;
default: mux = 0;
endcase
if (zero == 0) begin
yout = 0;
end else begin
yout = mux;
end
cout = 0;
if (yout == 4'hf && cin == 1) begin
cout = 1;
end
end
always @(posedge clock) begin
if (stackWr == 1) begin
stack[stackAddr] <= pc;
end
if (re == 0) begin
ar <= din;
end
if (fe == 0) begin
if (pup == 1) begin
sp <= sp + 1;
end else begin
sp <= sp - 1;
end
end
pc <= yout;
if (cin == 1) begin
pc <= yout + 1;
end
end
endmodule
| 7.842559 |
module am2912 (
i,
e_,
b_,
z
);
parameter WIDTH = 4;
input [WIDTH-1:0] i;
input e_;
inout [WIDTH-1:0] b_;
output [WIDTH-1:0] z;
genvar n;
for (n = 0; n < WIDTH; n = n + 1) begin
assign b_[n] = (e_ == 'b0 && i[n] == 'b1) ? 'b0 : 'bZ;
assign z[n] = (b_[n] === 'b0) ? 'b1 : 'b0;
end
endmodule
| 7.276096 |
module am2918 (
d,
cp,
oe_,
q,
y
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
input cp;
input oe_;
output [WIDTH-1:0] q;
output [WIDTH-1:0] y;
reg [WIDTH-1:0] q;
initial begin
q = 'b0;
end
always @(posedge cp) begin
q <= d;
end
assign y = oe_ ? 'bz : q;
endmodule
| 7.194412 |
module am2926 (
d,
be,
re_,
bus_,
r
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
input be, re_;
inout [WIDTH-1:0] bus_;
output [WIDTH-1:0] r;
assign bus_ = (be == 'b0) ? {WIDTH{1'bZ}} : d;
assign r = (re_ == 'b0) ? ~(~bus_) : {WIDTH{1'bZ}};
endmodule
| 6.733054 |
module am2929 (
d,
be,
re_,
bus_,
r
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
input be, re_;
inout [WIDTH-1:0] bus_;
output [WIDTH-1:0] r;
assign bus_ = (be == 'b0) ? {WIDTH{1'bZ}} : ~d;
assign r = (re_ == 'b0) ? ~bus_ : {WIDTH{1'bZ}};
endmodule
| 7.161033 |
module am2929_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] d;
reg [WIDTH-1:0] busin;
reg be, re;
wire [WIDTH-1:0] r, bus;
`define assert(signame, value, expval) \
if (expval !== value) begin \
$display("Error: %s should be %b, but is %b", signame, expval, value); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval, businval;
input beval, reval;
input [WIDTH-1:0] expectr, expectbus;
begin
d <= dval;
busin <= businval;
be <= beval;
re <= reval;
#1 $display("%5g: %4b %b %b | %4b %4b | %0s", $time, d, be, re, r, bus, descr);
`assert("R", r, expectr);
`assert("BUS_", bus, expectbus);
end
endtask
assign bus = busin;
am2929 #(
.WIDTH(WIDTH)
) dut (
.d(d),
.be(be),
.re_(re),
.bus_(bus),
.r(r)
);
initial begin
//Dump results of the simulation
$dumpfile("am2929.vcd");
$dumpvars;
$display("-time: -d-- be re | -y-- -bus | descr");
// ---a-- --bus- -be -re ex_r__ ex_bus
tester("Tristate BUS_", 'bXXXX, 'bZZZZ, 'b0, 'bX, 'bXXXX, 'bZZZZ);
tester("Tristate R", 'bXXXX, 'bXXXX, 'bX, 'b1, 'bZZZZ, 'bXXXX);
tester("Drive BUS", 'b1010, 'bZZZZ, 'b1, 'bX, 'bXXXX, 'b0101);
tester("Drive BUS and receive", 'b0011, 'bZZZZ, 'b1, 'b0, 'b0011, 'b1100);
tester("Receive BUS", 'bXXXX, 'b1101, 'b0, 'b0, 'b0010, 'b1101);
#10 $finish;
end
endmodule
| 7.026986 |
module am2948 (
a,
b,
tr_,
rc_
);
parameter WIDTH = 8;
inout [WIDTH-1:0] a, b;
input tr_, rc_;
always @(rc_ or tr_) begin
if (rc_ == 'b0 && tr_ == 'b0) begin
$display("Error: AM2948: RC and TR may not both be 0");
$stop;
end
end
assign a = (rc_ == 'b1) ? {WIDTH{1'bZ}} : ~b;
assign b = (tr_ == 'b1) ? {WIDTH{1'bZ}} : ~a;
endmodule
| 6.713465 |
module am2949 (
a,
b,
tr_,
rc_
);
parameter WIDTH = 8;
inout [WIDTH-1:0] a, b;
input tr_, rc_;
always @(rc_ or tr_) begin
if (rc_ == 'b0 && tr_ == 'b0) begin
$display("Error: AM2949: RC and TR may not both be 0");
$stop;
end
end
assign a = (rc_ == 'b1) ? {WIDTH{1'bZ}} : b;
assign b = (tr_ == 'b1) ? {WIDTH{1'bZ}} : a;
endmodule
| 6.510966 |
module am2954_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, cp;
wire [WIDTH-1:0] y;
am2954 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.cp (cp),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but is %b", signame, value, signal); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input oeval;
input [WIDTH-1:0] expecty;
begin
d <= dval;
oe <= oeval;
cp <= 1'b0;
#1 // $display("%5g: %8b %1b | %8b |", $time, d, oe, y);
cp <= 1'b1;
#1 $display("%5g: %8b %1b ^ | %8b | %0s", $time, d, oe, y, descr);
cp <= 1'b0;
#1 // $display("%5g: %8b %1b | %8b |", $time, d, oe, y);
`ASSERT(
"Y", y, expecty);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am2954.vcd");
$dumpvars;
$display("-time: ---d---- e_ clk | ---q---- | descr");
// -----d---- -oe -expecty--
tester("Tristate", 'bXXXXXXXX, 'b1, 'bZZZZZZZZ);
tester("load 1's", 'b11111111, 'b1, 'bZZZZZZZZ);
tester("OE=0", 'b11111111, 'b0, 'b11111111);
tester("load 10's", 'b10101010, 'b0, 'b10101010);
tester("load 01's", 'b01010101, 'b0, 'b01010101);
#10 $finish;
end
endmodule
| 6.835335 |
module am2955 (
d,
y,
cp,
oe_
);
parameter WIDTH = 8;
input [WIDTH-1:0] d;
output [WIDTH-1:0] y;
input cp;
input oe_;
reg [WIDTH-1:0] q;
always @(posedge cp) begin
if (cp == 'b1) begin
q <= d;
end
end
assign y = (oe_ == 'b1) ? {WIDTH{1'bZ}} : ~q;
endmodule
| 6.635962 |
module am2955_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, cp;
wire [WIDTH-1:0] y;
am2955 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.cp (cp),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but is %b", signame, value, signal); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input oeval;
input [WIDTH-1:0] expecty;
begin
d <= dval;
oe <= oeval;
cp <= 1'b0;
#1 // $display("%5g: %8b %1b | %8b |", $time, d, oe, y);
cp <= 1'b1;
#1 $display("%5g: %8b %1b ^ | %8b | %0s", $time, d, oe, y, descr);
cp <= 1'b0;
#1 // $display("%5g: %8b %1b | %8b |", $time, d, oe, y);
`ASSERT(
"Y", y, expecty);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am2955.vcd");
$dumpvars;
$display("-time: ---d---- e_ clk | ---q---- | descr");
// -----d---- -oe -expecty--
tester("Tristate", 'bXXXXXXXX, 'b1, 'bZZZZZZZZ);
tester("load 1's", 'b11111111, 'b1, 'bZZZZZZZZ);
tester("OE=0", 'b11111111, 'b0, 'b00000000);
tester("load 10's", 'b10101010, 'b0, 'b01010101);
tester("load 01's", 'b01010101, 'b0, 'b10101010);
#10 $finish;
end
endmodule
| 7.145273 |
module am2956_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, g;
wire [WIDTH-1:0] y;
am2956 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.g (g),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but is %b", signame, value, signal); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input gval, oeval;
input [WIDTH-1:0] expecty;
begin
d <= dval;
g <= gval;
oe <= oeval;
#1 $display("%5g: %8b %1b %1b | %8b | %0s", $time, d, g, oe, y, descr);
`ASSERT("Y", y, expecty);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am2956.vcd");
$dumpvars;
$display("-time: ---d---- oe g | ---q---- | descr");
// -----d---- -g- -oe -expecty--
tester("Tristate", 'bXXXXXXXX, 'bX, 'b1, 'bZZZZZZZZ);
tester("Transparent", 'b11111111, 'b1, 'b0, 'b11111111);
tester("Transparent", 'b10101010, 'b1, 'b0, 'b10101010);
tester("Latch", 'b01010101, 'b0, 'b0, 'b01010101);
tester("Hold", 'b11001100, 'b0, 'b0, 'b01010101);
#10 $finish;
end
endmodule
| 6.733001 |
module am2957 (
d,
y,
g,
oe_
);
parameter WIDTH = 8;
input [WIDTH-1:0] d;
output [WIDTH-1:0] y;
input g;
input oe_;
reg [WIDTH-1:0] q;
always @(negedge g) begin
if (g == 'b0) begin
q <= d;
end
end
assign y = (oe_ == 'b1) ? {WIDTH{1'bZ}} : ~((g == 'b1) ? d : q);
endmodule
| 6.792232 |
module am2957_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, g;
wire [WIDTH-1:0] y;
am2957 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.g (g),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but is %b", signame, value, signal); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input gval, oeval;
input [WIDTH-1:0] expecty;
begin
d <= dval;
g <= gval;
oe <= oeval;
#1 $display("%5g: %8b %1b %1b | %8b | %0s", $time, d, g, oe, y, descr);
`ASSERT("Y", y, expecty);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am2957.vcd");
$dumpvars;
$display("-time: ---d---- oe g | ---q---- | descr");
// -----d---- -g- -oe -expecty--
tester("Tristate", 'bXXXXXXXX, 'bX, 'b1, 'bZZZZZZZZ);
tester("Transparent", 'b11111111, 'b1, 'b0, 'b00000000);
tester("Transparent", 'b10101010, 'b1, 'b0, 'b01010101);
tester("Latch", 'b01010101, 'b0, 'b0, 'b10101010);
tester("Hold", 'b11001100, 'b0, 'b0, 'b10101010);
#10 $finish;
end
endmodule
| 6.939247 |
modules, if separate G is needed
module am2958(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? ~a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
modules, if separate G is needed
module am2959(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
module am29705 (
a,
b,
d,
we1_,
we2_,
le_,
oea_,
oeb_,
alo_,
ya,
yb
);
input [3:0] a, b;
input [3:0] d;
input we1_, we2_, le_;
input oea_, oeb_;
input alo_;
output [3:0] ya, yb;
reg [3:0] ram[0:15];
reg [3:0] alatch, blatch;
// RAM latches
always @(negedge le_) begin
if (le_ == 'b0) begin
alatch <= ram[a];
blatch <= ram[b];
end
end
// RAM write
always @(we1_ or we2_ or d) begin
if (~(we1_ | we2_)) ram[b] <= d;
end
// outputs
assign ya = (oea_ == 'b1) ? 'bZZZZ : (alo_ == 'b0) ? 'b0000 : (le_ == 'b1) ? ram[a] : alatch;
assign yb = (oeb_ == 'b1) ? 'bZZZZ : (le_ == 'b1) ? ram[b] : blatch;
endmodule
| 6.825868 |
module am29811 (
i,
test,
oe_,
cntload_,
cnte_,
mape_,
ple_,
fe_,
pup,
s
);
input [3:0] i;
input test;
input oe_;
output cntload_, cnte_;
output mape_, ple_;
output fe_, pup;
output [1:0] s;
reg [7:0] tmp;
always @(i, test) begin
case (i)
`JZ: tmp = {`NAS_D, `F_HOLD, `CT_LL, 1'b1, 1'b0};
`CJS:
tmp = (test==1'b0) ? {`NAS_PC, `F_HOLD, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_D, `F_PUSH, `CT_HOLD, 1'b1, 1'b0};
`JMAP: tmp = {`NAS_D, `F_HOLD, `CT_HOLD, 1'b0, 1'b1};
`CJP:
tmp = (test==1'b0) ? {`NAS_PC, `F_HOLD, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_D, `F_HOLD, `CT_HOLD, 1'b1, 1'b0};
`PUSH:
tmp = (test==1'b0) ? {`NAS_PC, `F_PUSH, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_PC, `F_PUSH, `CT_LOAD, 1'b1, 1'b0};
`JSRP:
tmp = (test==1'b0) ? {`NAS_R, `F_PUSH, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_D, `F_PUSH, `CT_HOLD, 1'b1, 1'b0};
`CJV:
tmp = (test==1'b0) ? {`NAS_PC, `F_HOLD, `CT_HOLD, 1'b1, 1'b1}:
{`NAS_D, `F_HOLD, `CT_HOLD, 1'b1, 1'b1};
`JRP:
tmp = (test==1'b0) ? {`NAS_R, `F_HOLD, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_D, `F_HOLD, `CT_HOLD, 1'b1, 1'b0};
`RFCT:
tmp = (test==1'b0) ? {`NAS_F, `F_HOLD0, `CT_DEC, 1'b1, 1'b0}:
{`NAS_PC, `F_POP, `CT_HOLD, 1'b1, 1'b0};
`RPCT:
tmp = (test==1'b0) ? {`NAS_D, `F_HOLD, `CT_DEC, 1'b1, 1'b0}:
{`NAS_PC, `F_HOLD, `CT_HOLD, 1'b1, 1'b0};
`CRTN:
tmp = (test==1'b0) ? {`NAS_PC, `F_HOLD0, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_F, `F_POP, `CT_HOLD, 1'b1, 1'b0};
`CJPP:
tmp = (test==1'b0) ? {`NAS_PC, `F_HOLD0, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_D, `F_POP, `CT_HOLD, 1'b1, 1'b0};
`LDCT: tmp = {`NAS_PC, `F_HOLD, `CT_LOAD, 1'b1, 1'b0};
`LOOP:
tmp = (test==1'b0) ? {`NAS_F, `F_HOLD0, `CT_HOLD, 1'b1, 1'b0}:
{`NAS_PC, `F_POP, `CT_HOLD, 1'b1, 1'b0};
`CONT: tmp = {`NAS_PC, `F_HOLD, `CT_HOLD, 1'b1, 1'b0};
`JP: tmp = {`NAS_D, `F_HOLD, `CT_HOLD, 1'b1, 1'b0};
default: tmp = 8'bxxxxxxxx;
endcase
end
assign s = tmp[7:6];
assign fe_ = tmp[5];
assign pup = tmp[4];
assign cntload_ = tmp[3];
assign cnte_ = tmp[2];
assign mape_ = tmp[1];
assign ple_ = tmp[0];
endmodule
| 7.47623 |
module in main.v.
//
// This is set up to work within the limitations of the pinout of a
// BeagleWire board connected to a BeagleBone Black, where only a subset of
// the GPMC pins are connected to the FPGA. In particular, this is required to
// work in synchronous mode because the async "wait" pin is not connected.
// We also have only one chip select exposed, and so we use the highest-order
// address pin to distinguish RAM vs. register writes (RAM on low addresses,
// registers on high addresses).
module am335x_gpmc(
input reset,
// GPMC signals: these are connected to the relevant pins of the
// AM335x package where the GPMC peripheral is active.
inout [15:0] gpmc_ad, // multiplexed address/data
input gpmc_advn, // Address valid (active low)
input gpmc_csn1, // GPMC peripheral chip select 1 (active low)
input gpmc_wein, // Write enable (active low)
input gpmc_oen, // Output enable (active low)
input gpmc_clk, // GPMC peripheral external clock
// Queue signals: incoming GPMC requests are queued so that they can be
// processed either in the video RAM clock domain (for video RAM writes)
// or in the pixel clock domain (for register writes) while freeing up
// the GPMC bus for further writes (at least, until the queues fill).
//
// These signals all belong to the gpmc_clk domain; the calling module
// is responsible for configuring the target queue to transfer into the
// appropriate target clock domain.
output reg [15:0] vram_write_addr,
output reg [15:0] vram_write_data,
output reg vram_write,
input vram_can_write,
output reg [15:0] reg_write_addr,
output reg [15:0] reg_write_data,
output reg reg_write,
input reg_can_write
);
// We'll manage the bidirectional gpmc_ad signals safely using a SB_IO
// primitive, which is ICE40-specific (described in the "SiliconBlue
// Technology Library" documentation). That makes this particular module
// ICE40-specific, but we're accepting that because it's here primarily
// to support the BeagleWire-based development environment setup and
// therefore we know we only need to deal with ICE40 devices there.
reg [15:0] gpmc_data_out;
wire [15:0] gpmc_data_in;
SB_IO # (
.PIN_TYPE(6'b1010_01),
.PULLUP(1'b 0)
) gpmc_ad_tristate [15:0] (
.PACKAGE_PIN(gpmc_ad),
.OUTPUT_ENABLE(!gpmc_csn1 && gpmc_advn && !gpmc_oen && gpmc_wein),
.D_OUT_0(gpmc_data_out),
.D_IN_0(gpmc_data_in)
);
// The above deals with gpmc_ad being bidirectional, but we also need to
// deal with it being multiplexed: it's initially also the address, which
// we need to copy into a register before then using the same signals
// for data.
reg [15:0] gpmc_addr;
always @(negedge gpmc_clk) begin
if (!gpmc_csn1 && !gpmc_advn && gpmc_wein && gpmc_oen) begin
gpmc_addr <= gpmc_data_in;
end
end
always @(negedge gpmc_clk) begin
// If gpmc_advn is unasserted (high) then gpmc_data_in is data to
// be written. (assuming this is a write -- we only actually support
// writes, so reads are entirely ignored.)
// TODO: We're just assuming everything is a video RAM write for now.
// Ultimately we'll need to decode part of the address space as
// registers, but we don't need that for initial prototyping and when
// we do it it'll steal away from our already-teeny 16-bit VRAM address
// space that this interface provides. :(
if (!gpmc_csn1 && gpmc_advn && !gpmc_wein && !gpmc_oen) begin
vram_write_addr <= gpmc_addr;
vram_write_data <= gpmc_data_in;
vram_write <= 1;
end else begin
vram_write_addr <= 0;
vram_write_data <= 0;
vram_write <= 0;
end
end
endmodule
| 7.135577 |
module am29811 (
input tst, // entry for conditional instructions
input [3:0] i, // microcode instruction
//
output [1:0] s, // address selector
output fe_n, // file enable
output pup, // push/pop_n
output ctl_n, // counter load
output cte_n, // counter enable
output me_n // map enable
);
reg [6:0] mx;
assign s[1] = mx[6]; // 00 - pc, 01 - ra
assign s[0] = mx[5]; // 10 - sp, 11 - di
assign fe_n = mx[4]; //
assign pup = mx[3]; // 1/0 - push/pop
assign ctl_n = mx[2];
assign cte_n = mx[1];
assign me_n = mx[0];
//
// Unconditional commands
//
// 0000: jz di, ctl, cte
// 0010: jmap di, me
// 1100: ldct pc, ctl
// 1110: cont pc
// 1111: jp di
//
// Conditional commands
// miss taken
// 0001: cjs pc di, push
// 0011: cjp pc di
// 0100: push pc, push pc, push, ctl
// 0101: jsrp ra, push di, push
// 0110: cjv pc di
// 0111: jrp ra di
// 1000: rfct sp, cte pc, pop
// 1001: rpct di, cte pc
// 1010: crtn pc sp, pop
// 1011: cjpp pc di, pop
// 1101: loop sp pc, pop
//
always @(*)
case (i[3:0])
4'b0000: mx = 7'b1111001; // jz - jump zero
4'b0001: mx = ~tst ? 7'b0011111 : 7'b1101111; // cjs - cond jsb pl
4'b0010: mx = 7'b1111110; // jmap - jump map
4'b0011: mx = ~tst ? 7'b0011111 : 7'b1111111; // cjp - cond jump pl
4'b0100: mx = ~tst ? 7'b0001111 : 7'b0001011; // push - push/cond ld cntr
4'b0101: mx = ~tst ? 7'b0101111 : 7'b1101111; // jsrp - cond jsb r/pl
4'b0110: mx = ~tst ? 7'b0011111 : 7'b1111111; // cjv - cond jump vector
4'b0111: mx = ~tst ? 7'b0111111 : 7'b1111111; // jrp - cond jump r/pl
4'b1000: mx = ~tst ? 7'b1010101 : 7'b0000111; // rfct - repeat loop, ctr != 0
4'b1001: mx = ~tst ? 7'b1111101 : 7'b0011111; // rpct - repeat pl, ctr != 0
4'b1010: mx = ~tst ? 7'b0010111 : 7'b1000111; // crtn - cond return
4'b1011: mx = ~tst ? 7'b0010111 : 7'b1100111; // cjpp - cond jump pl & pop
4'b1100: mx = 7'b0011011; // ldct - ld cntr & continue
4'b1101: mx = ~tst ? 7'b1010111 : 7'b0000111; // loop - test end loop
4'b1110: mx = 7'b0011111; // cont - continue
4'b1111: mx = 7'b1111111; // jp - jump pl
endcase
endmodule
| 7.47623 |
module am4_pulse #(
parameter
//
// Monovibrator pulse width in clock periods
//
AM4_PULSE_WIDTH_CLK = 100
) (
input clk, // input clock
input reset_n, // negative reset
input a_n, // negative start
input b, // positive start
output q // output
);
localparam CNT_WIDTH = log2(AM4_PULSE_WIDTH_CLK);
reg [CNT_WIDTH-1:0] cnt;
reg qout;
reg start;
initial begin
qout = 0;
start = 0;
end
assign q = qout;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
cnt <= 0;
qout <= 1'b0;
start <= 1'b0;
end else begin
if (~start & ~a_n & b) cnt <= AM4_PULSE_WIDTH_CLK;
else if (|cnt) cnt <= cnt - 1'b1;
qout <= |cnt;
start <= ~a_n & b;
end
end
function integer log2(input integer value);
begin
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
endmodule
| 6.670204 |
module mcrom (
input clk, // input clock
input ena, // clock enable
input [ 9:0] addr, // instruction address
output [55:0] data // output read opcode
);
//______________________________________________________________________________
//
// Memory array and its inititialization with K1656RE1-001/007 content
//
reg [55:0] rom[0:1023];
reg [55:0] q;
integer i;
initial begin
end
initial begin
for (i = 0; i < 1023; i = i + 1) begin
rom[i] = 56'h00000000000000;
end
//
// The filename for MicROM content might be explicitly
// specified in synthesys/simulating tool settings
//
`ifdef M4_FILE_MICROM
$readmemh(`M4_FILE_MICROM, rom);
`else
$readmemh("../../rom/mc.rom", rom);
`endif
end
//______________________________________________________________________________
//
assign data = q;
always @(posedge clk) if (ena) q <= rom[addr];
endmodule
| 6.539659 |
module mcrom (
input clk, // input clock
input ena, // clock enable
input [ 9:0] addr, // instruction address
output [55:0] data // output read opcode
);
wire [55:0] q;
//
// Instantiate the ROM IP based on top of BRAM9K
//
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(56),
.ADDR_WIDTH_A(10),
.DATA_DEPTH_A(1024),
.DATA_WIDTH_B(56),
.ADDR_WIDTH_B(10),
.DATA_DEPTH_B(1024),
.MODE("SP"),
.REGMODE_A("NOREG"),
.RESETMODE("SYNC"),
.IMPLEMENT("9K(FAST)"),
.DEBUGGABLE("NO"),
.PACKABLE("NO"),
.INIT_FILE("../../../am4/rom/mc.mif"),
.FILL_ALL("NONE")
) inst (
.dia ({56{1'b0}}),
.dib ({56{1'b0}}),
.addra(addr),
.addrb({10{1'b0}}),
.cea (ena),
.ceb (1'b0),
.ocea (1'b0),
.oceb (1'b0),
.clka (clk),
.clkb (1'b0),
.wea (1'b0),
.web (1'b0),
.bea (1'b0),
.beb (1'b0),
.rsta (1'b0),
.rstb (1'b0),
.doa (q),
.dob ()
);
assign data[55:0] = q[55:0];
endmodule
| 6.539659 |
module am74ls138_testbench;
reg a, b, c;
reg g1, g2a, g2b;
wire [7:0] y;
am74ls138 dut (
.a(a),
.b(b),
.c(c),
.g1(g1),
.g2a_(g2a),
.g2b_(g2b),
.y(y)
);
task tester;
input [80*8-1:0] descr;
input cval, bval, aval, g1val, g2aval, g2bval;
begin
a <= aval;
b <= bval;
c <= cval;
g1 <= g1val;
g2a <= g2aval;
g2b <= g2bval;
#1
$display(
"%5g: %1b %1b %1b %1b %1b %1b | %8b | %0s", $time, c, b, a, g1, g2a, g2b, y, descr
);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("am74ls138.vcd");
$dumpvars;
$display("-time: c b a g1 g2a g2b | y | description");
// -c-- -b-- -a-- -g1- -g2a -g2b
tester("disable g1", 1'bx, 1'bx, 1'bx, 1'b0, 1'bx, 1'bx);
tester("disable g2a", 1'bx, 1'bx, 1'bx, 1'bx, 1'b1, 1'bx);
tester("disable g2b", 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'b1);
tester("y0 = low", 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0);
tester("y1 = low", 1'b0, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0);
tester("y2 = low", 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
tester("y3 = low", 1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0);
tester("y4 = low", 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0);
tester("y5 = low", 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0);
tester("y6 = low", 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
tester("y7 = low", 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0);
#10 $finish;
end
endmodule
| 6.977244 |
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