code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ADD (
x,
y,
sum,
OF
);
input signed [63:0] x, y;
output signed [63:0] sum;
output signed OF;
wire signed [63:0] ci;
wire carry_in;
assign carry_in = 1'b0;
full_adder FA1 (
x[0],
y[0],
carry_in,
sum[0],
ci[0]
);
genvar i;
generate
for (i = 1... | 6.891749 |
module SUB (
x,
y,
z,
OF
);
input signed [63:0] x, y;
output signed [63:0] z;
output OF;
wire signed [63:0] u, v, w;
wire signed [63:0] k;
twocomp comp (
y,
u
);
ADD sub_add (
x,
u,
w,
OF
);
assign z = w;
endmodule
| 6.850044 |
module twocomp (
x,
y
);
input signed [63:0] x;
output signed [63:0] y;
wire signed [63:0] w;
wire c_out;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
not (w[i], x[i]);
end
endgenerate
ADD twocomp1 (
w,
64'b1,
y,
c_out
);
endmodule
| 6.570209 |
module alu_upper_immediate_auipc (
input clock,
input alu_upper_immediate_auipc_enable,
input [31:0] immediate20_utype,
input [31:0] rs1_value,
output reg [31:0] rd_value,
input [31:0] pc
);
always @(posedge clock & alu_upper_immediate_auipc_enable) begi... | 6.534627 |
module alu_upper_immediate_lui (
input clock,
input alu_upper_immediate_lui_enable,
input [31:0] immediate20_utype,
input [31:0] rs1_value,
output reg [31:0] rd_value,
input [31:0] pc
);
always @(posedge clock & alu_upper_immediate_lui_enable) begin
... | 6.534627 |
module ALU_v1 (
input [3:0] ALU_operation,
input [31:0] A,
B,
output overflow,
zero,
output [31:0] res
);
wire [32:0] ADC_out;
wire [31:0] ADC_B, signalext_out;
wire [31:0] and_res, or_res, xor_res, nor_res, srl_res, sll_res, slt_res;
wire SLT;
and32 and32 (
.A (A),
.B ... | 7.073619 |
module meiaSoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR1 (s0, a, b);
and AND1 (s1, a, b);
endmodule
| 7.280431 |
module meiaSoma
//-----------------
//-- Soma Completa
//-----------------
module somaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaSoma MS1 (s2, s3, a, b);
meiaSoma MS2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.661006 |
module somaCompleta
// ----------------------
// -- Somador de 4 bits
// ----------------------
module somador4bits(s0, s1, s2, s3, carry, comparador, a0, a1, a2, a3, b0 ,b1, b2, b3);
output s0, s1, s2, s3, carry, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
somaCompleta SM1(s0, w1, b0, a1, 0... | 7.41852 |
module somador
//------------------
//-- Meia Diferena
//------------------
module meiaDiferenca(s0, s1, a ,b);
output s0, s1;
input a, b;
wire s2;
xor XOR1 (s0, a, b);
not NOT1 (s2, a);
and AND1 (s1, b, s2);
endmodule
| 7.81062 |
module Meia Diferena
//----------------------
//-- Diferena Completa
//----------------------
module diferencaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaDiferenca MD1 (s2, s3, a, b);
meiaDiferenca MD2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.055737 |
module Diferenca Completa
// ----------------------
// -- Subtrator de 4 bits
// ----------------------
module subtrator4bits(s0, s1, s2, s3, comparador, a0, a1, a2, a3, b0, b1, b2, b3);
output s0, s1, s2, s3, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
diferencaCompleta DC1 (s0, w1, a0 ,b0, ... | 6.693215 |
module comparadorLogico
// ------
// -- ALU
// ------
module aLU(s0 ,s1, s2, s3, carry, overFlow, x0, y0, y1, y2, y3, comparador, k0, s00, s01, s02, s03, s10, s11, s12, s13, a0, a1, a2, a3, b0, b1, b2, b3);
output s0 ,s1, s2, s3, carry, overFlow, x0, y0, y1, y2, y3, comparador, k0, s00, s01, s02, s03, s10, s11, s12... | 7.063838 |
module alu_wb_queue (
in_rfa_queue_entry_serviced,
in_vgpr_dest_data,
in_sgpr_dest_data,
in_exec_wr_vcc_value,
in_vgpr_wr_mask,
in_wfid,
in_instr_pc,
in_vgpr_dest_addr,
in_sgpr_dest_addr,
in_instr_done,
in_vgpr_dest_wr_en,
in_sgpr_dest_wr_en,
in_vcc_wr_en,
out_vgp... | 7.414255 |
module f_adder (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule
| 7.216325 |
module alu_with_register_file (
input [25:0] instruction,
input clock,
output [15:0] out,
output overflow,
output c_out
);
wire [7:0] a, b, y;
reg_file x1 (
.clock(clock),
.data(instruction[23:0]),
.result(out),
.a(a),
.b(b),
.y(y)
);
alu x2 (
.a(a),... | 7.34057 |
module alu_with_register_file_tb;
// Inputs
reg [25:0] instruction;
reg clock;
// Outputs
wire [15:0] out;
wire overflow;
wire c_out;
// Instantiate the Unit Under Test (UUT)
alu_with_register_file uut (
.instruction(instruction),
.clock(clock),
.out(out),
.overflow(overflow... | 7.34057 |
module Adder #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] d0,
input [WIDTH-1:0] d1,
output [WIDTH-1:0] out
);
assign out = d0 + d1;
endmodule
| 9.509237 |
module Increment (
input [15:0] d,
output [15:0] out
);
assign out = d + 1;
endmodule
| 6.536633 |
module alu_xor (
A,
B,
Z
);
// parameter definitions
parameter WIDTH = 8;
//port definitions
input wire [WIDTH-1:0] A, B;
output wire [WIDTH-1:0] Z;
// instantiate module's hardware
assign Z = A ^ B;
endmodule
| 8.939182 |
module alu_xor_4 (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input clk,
input [3:0] A0,
B0,
A1,
B1, // ALU 8-bit Inputs
input [1:0] ALU_Sel1,
ALU_Sel2, // ALU Selection
output [3:0] ALU_Out1,
ALU_Out2, ... | 8.042765 |
module alu_4 (
input [3:0] A,
B, // ALU 8-bit Inputs
input [1:0] ALU_Sel, // ALU Selection
output [3:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [4:0] ALU_Result;
assign ALU_Out = ALU_Result[3:0]; // ALU out
assign CarryOut = ALU_Result[4];
always @(*) be... | 8.906529 |
module: alu_xor_test
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_xor_test;
// parameter
parameter WIDTH = 32;
// test module variables
reg [WIDTH-1:0] i;
// Inputs
re... | 7.158688 |
module alu (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] x, y;
input [2:0] opcode;
output overflow, zero, cout;
output [31:0] f;
wire [2:0] opoverflow;
wire [31:0] f0, f1, f2, f3, f4, result;
wire w5, zero, isoverflowed, cout;
add op0 (
x,
y,
f0,
... | 7.914753 |
module fulladder (
a,
b,
c,
s,
cout
);
input a, b, c;
output s, cout;
xor g1 (w1, a, b), g2 (s, w1, c);
and g3 (w2, c, b), g4 (w3, c, a), g5 (w4, a, b);
or g6 (cout, w2, w3, w4);
endmodule
| 7.454465 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
... | 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and (w17, d1, s0);
not (w15, s0);
and (w18, w15, d0);
or (f, w17, w18);
endmodule
| 7.107199 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
end
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b... | 7.203305 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
case (in)
4'd1: pos = 2'd0;
4'd2: pos = 2'd1;
4'd3: pos = 2'd0;
4'd4: pos = 2'd2;
4'd5: pos = 2'd0;
4'd6: pos = 2'd1;
4'd7: pos = 2'd0;
4'd8: pos = 2'd3;
4'd9: pos = 2'd0;
... | 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzzzzz1: pos = 3'd0;
8'bzzzzzz1z: pos = 3'd1;
8'bzzzzz1zz: pos = 3'd2;
8'bzzzz1zzz: pos = 3'd3;
8'bzzz1zzzz: pos = 3'd4;
8'bzz1zzzzz: pos = 3'd5;
8'bz1zzzzzz: pos = 3'd6;... | 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) begin
if (sel_b1 & sel_b2) begin
out_always = b;
end else begin
out_always = a;
end
end
en... | 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) begin
shut_off_computer = 1;
end else begin
shut_off_computer = 0;
end
end
... | 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
up = 0;
down = 0;
right = 0;
left = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he07... | 7.203305 |
module AlwaysNTPredictor (
input [`WORD_SIZE-1:0] PC,
input Correct,
input [`WORD_SIZE-1:0] ActualBranchTarget,
output [`WORD_SIZE-1:0] Prediction
);
/*
[Always not-taken branch predictor module]
Purpose:
A placeholder(or framework) for future possibility of implementing a better branc... | 8.225705 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
end
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'd0: out = data0;
3'd1: ... | 7.203305 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0]) pos = 2'd0;
else if (in[1]) pos = 2'd1;
else if (in[2]) pos = 2'd2;
else if (in[3]) pos = 2'd3;
else pos = 2'd0;
end
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzz_zzz1: pos = 3'd0;
8'bzzzz_zz10: pos = 3'd1;
8'bzzzz_z100: pos = 3'd2;
8'bzzzz_1000: pos = 3'd3;
8'bzzz1_0000: pos = 3'd4;
8'bzz10_0000: pos = 3'd5;
8'bz100_0000: pos ... | 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
// assign
assign out_assign = (sel_b1 & sel_b2) ? b : a;
// always
always @(*) begin
if (sel_b1 & sel_b2) begin
out_always = b;
end else begin
out_alwa... | 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
// add else
else
// we can simply output '0'
shut_off_com... | 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
up = 1'b0;
down = 1'b0;
left = 1'b0;
right = 1'b0;
case (scancode)
16'he06b: left = 1'b1;
16'he072: down = 1'b1;
16'he074: right ... | 7.203305 |
module ALW_NR_OPSL (
clk,
port_a,
port_b
);
input clk;
input port_a;
output port_b;
reg port_b;
always @(clk || port_a) begin
port_b <= port_a;
end
endmodule
| 6.683028 |
module ALW_NR_TCST (
out_a
);
output reg [1:0] out_a;
always @(posedge 1) out_a <= 2'b00;
endmodule
| 7.096444 |
module AL_LOGIC_FIFO (
rst,
di, clkw, we, csw,
do, clkr, re, csr, ore,
empty_flag, aempty_flag,
full_flag, afull_flag
);
// 1kx9 by default
parameter DATA_WIDTH_W = 9; // 1 ... 9*48
parameter DATA_WIDTH_R = DATA_WIDTH_W; // 1 ... 9*48
parameter DATA_DEPTH_W = 1024; ... | 8.086213 |
module AL_LOGIC_MULT (
p,
a,
b,
cea,
ceb,
cepd,
clk,
rstan,
rstbn,
rstpdn
);
parameter INPUT_WIDTH_A = 18;
parameter INPUT_WIDTH_B = 18;
parameter OUTPUT_WIDTH = 36;
output [OUTPUT_WIDTH-1:0] p;
input [INPUT_WIDTH_A-1:0] a;
input [INPUT_WIDTH_B-1:0] b;
input cea; /... | 6.701601 |
module AL_PHY_IOCLK (
clki,
stop,
clko
);
input clki;
input stop;
output clko;
parameter STOPCLK = "DISABLE"; // ENABLE,DISABLE
reg ck_en1, ck_en2;
reg stop_en;
initial begin
ck_en1 = 1'b0;
ck_en2 = 1'b0;
end
initial begin
case (STOPCLK)
"DISABLE": stop_en = 1'b0;
... | 7.125784 |
module pfb_lsliceomux (
f,
fx,
f_n,
sum0,
sum1,
lut4f,
lut4g,
func6,
mc1_fxmuxlut4g,
mc1_fxmuxrip_n,
mc1_fmuxrip,
mc1_fmuxlut5,
in5
);
output f, fx, f_n;
input sum0, sum1, lut4f, lut4g, func6, mc1_fxmuxlut4g, mc1_fxmuxrip_n, mc1_fmuxrip, mc1_fmuxlut5;
input in5;... | 6.686815 |
module pfb_slice01_lut4 (
lut4_o,
lut00_n,
mc1_ripmode,
I0,
I1,
I2,
I3,
dpram_mode,
dpram_di,
dpram_we,
dpram_wclk,
dpram_waddr
);
output lut4_o;
output lut00_n;
input mc1_ripmode;
input I0, I1, I2, I3;
parameter INIT = 16'h0000;
//dpram interface
input dpr... | 6.540541 |
module top (
input clk,
input rst_n,
output [6:0] seg,
input all_sw, //高为弹球，低为钢琴
output [3:0] seg_sel,
input [2:0] move, //0为左，2为右
input [9:0] sw,
input displaymode,
output beep,
// output add_cnt0,
output warn_flag,
output vga_clk,
output hs,
output vs,
... | 7.233807 |
module al_ver (
input clk_i,
input rst_i,
input uart_rx,
output uart_tx
);
wire rstn_i;
wire locked_w;
wire clk_w;
clk_wiz_0 clk_wzrd (
.reset(rst_i),
.clk_in1(clk_i),
.clk_out1(clk_w),
.locked(locked_w)
);
assign rstn_i = !rst_i && locked_w;
localparam BAUD_D... | 6.757465 |
module array (
a,
b,
p
);
parameter N = 16;
parameter M = 16;
input [N-1:0] a;
input [M-1:0] b;
output [M+N-1:0] p;
genvar i, j;
generate
wire [M*N-1:0] w;
for (i = 0; i < M; i = i + 1) begin : loop1
for (j = 0; j < N; j = j + 1) begin : loop2
and (w[i*N+j], a[j], b[i... | 6.857364 |
module FullAdder4bit (
A,
B,
Cin,
Sum,
Cout
);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
wire carry0;
wire carry1;
wire carry2;
FullAdder FA0 (
A[0],
B[0],
Cin,
Sum[0],
carry0
);
FullAdder FA1 (
A[1],
B[1],
carr... | 7.241024 |
module FullAdder16bit (
A,
B,
Cin,
Sum,
Cout
);
input [15:0] A, B;
input Cin;
output [15:0] Sum;
output Cout;
wire carry3;
wire carry7;
wire carry11;
FullAdder4bit FA40 (
A[3:0],
B[3:0],
Cin,
Sum[3:0],
carry3
);
FullAdder4bit FA41 (
A[7:4]... | 6.849148 |
module FullAdder32bit (
input [31:0] A,
B,
input Cin,
output [31:0] Sum,
output Cout
);
wire carry15;
FullAdder16bit FA160 (
.A(A[15:0]),
.B(B[15:0]),
.Cin(Cin),
.Sum(Sum[15:0]),
.Cout(carry15)
);
FullAdder16bit FA161 (
.A(A[31:16]),
.B(B[31:16]),... | 6.574057 |
module am25ls08 (
d,
q,
q_,
clk,
e_
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output [WIDTH-1:0] q_;
input clk;
input e_;
reg [WIDTH-1:0] q;
always @(posedge clk) begin
if (e_ == 1'b0) begin
q = d;
end
end
assign q_ = ~q;
endmodule
| 7.71803 |
module am25ls153_testbench;
reg [1:0] sel;
reg g;
reg [3:0] c;
wire y;
am25ls153 dut (
.sel(sel),
.g (g),
.c (c),
.y (y)
);
task tester;
input [80*8-1:0] descr;
input [1:0] sval;
input [3:0] cval;
input gval;
begin
sel <= sval;
c <= cval;
... | 7.200512 |
module am25ls174 (
d,
q,
q_,
clk,
clr_
);
parameter WIDTH = 6;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output [WIDTH-1:0] q_;
input clk;
input clr_;
reg [WIDTH-1:0] q;
always @(clr_) begin
q = {WIDTH{1'b0}};
end
always @(posedge clk) begin
if (clr_ == 1'b1) begin
... | 7.168672 |
module am25ls174_testbench;
parameter WIDTH = 6;
reg [WIDTH-1:0] d;
reg clr_, clk;
wire [WIDTH-1:0] q, q_;
am25ls174 #(
.WIDTH(WIDTH)
) dut (
.d(d),
.clk(clk),
.clr_(clr_),
.q(q),
.q_(q_)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
... | 6.657238 |
module am25ls191 (
in,
load_,
ent_,
ud,
clk,
q,
rco_,
mxmn
);
parameter WIDTH = 4;
input [WIDTH-1:0] in;
input load_, ent_, ud, clk;
output [WIDTH-1:0] q;
output rco_, mxmn;
reg [WIDTH-1:0] ctr;
wire all0, all1;
always @(posedge (clk)) begin
if (ent_ == 'b0) begin
... | 6.821231 |
module am25ls2521 (
a,
b,
ein_,
eout_
);
parameter WIDTH = 8;
input [WIDTH-1:0] a, b;
input ein_;
output eout_;
assign eout_ = ein_ | |(a ^ b);
endmodule
| 7.383562 |
module am25ls2521_test;
parameter WIDTH = 8;
reg [WIDTH-1:0] a, b;
reg ein;
wire eout;
`define HEADER(title)\
$display("%0s", title);\
$display("-----: ---a---- ---b---- ein | eout | description");
`define SHOW(a, b, ein, eout, descr)\
$display("%5d: %8b %8b %b | %b | %0s",\
... | 6.551644 |
module am25ls377 (
d,
q,
clk,
e_
);
parameter WIDTH = 8;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
input clk;
input e_;
reg [WIDTH-1:0] q;
always @(posedge clk) begin
if (e_ == 1'b0) begin
q = d;
end
end
endmodule
| 6.773584 |
module am25ls377_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg e_, clk;
wire [WIDTH-1:0] q;
am25ls377 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.clk(clk),
.e_ (e_),
.q (q)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
input eval;
begi... | 6.667555 |
module am25s174 (
d,
q,
q_,
clk,
clr_
);
parameter WIDTH = 6;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output [WIDTH-1:0] q_;
input clk;
input clr_;
reg [WIDTH-1:0] q;
always @(clr_) begin
q = {WIDTH{1'b0}};
end
always @(posedge clk) begin
if (clr_ == 1'b1) begin
... | 6.821664 |
module am25s174_testbench;
parameter WIDTH = 6;
reg [WIDTH-1:0] d;
reg clr_, clk;
wire [WIDTH-1:0] q, q_;
am25s174 #(
.WIDTH(WIDTH)
) dut (
.d(d),
.clk(clk),
.clr_(clr_),
.q(q),
.q_(q_)
);
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] dval;
in... | 6.685146 |
module am27s13 (
a,
q,
cs_
);
parameter WIDTH = 4;
parameter HEIGHT = 9;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs_;
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
) u0 (
.a(a... | 6.589618 |
module am27s181 (
a,
q,
cs1_,
cs2_,
cs3,
cs4
);
parameter WIDTH = 8;
parameter HEIGHT = 10;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs1_, cs2_, cs3, cs4;
wire cs;
assign cs = cs1_ | cs2_ | (~cs3) | (~cs4);
_genrom #(
... | 7.330218 |
module am27s21 (
a,
q,
cs1_,
cs2_
);
parameter WIDTH = 4;
parameter HEIGHT = 8;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs1_, cs2_;
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
... | 6.628458 |
module am27s25 (
a,
q,
ps_,
clr_,
clk,
e1_,
e2_
);
parameter WIDTH = 8;
parameter HEIGHT = 9;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input ps_, clr_;
input clk;
input e1_, e2_;
wire [WIDTH-1:0] romout;
reg [WIDTH-1:0] p... | 6.716306 |
module am27s21 (
a,
q,
cs1_,
cs2_
);
parameter WIDTH = 4;
parameter HEIGHT = 10;
parameter INITH = "";
parameter INITB = "";
input [HEIGHT-1:0] a;
output [WIDTH-1:0] q;
input cs1_, cs2_;
_genrom #(
.WIDTH (WIDTH),
.HEIGHT(HEIGHT),
.INITH (INITH),
.INITB (INITB)
... | 6.628458 |
module am2902_testbench;
reg [3:0] g, p;
reg cn;
wire go, po;
wire cnx, cny, cnz;
am2902 dut (
.cn(cn),
.g_(g),
.p_(p),
.cnx(cnx),
.cny(cny),
.cnz(cnz),
.go_(go),
.po_(po)
);
task tester;
input [80*8-1:0] descr;
input [3:0] gval, pval;
input... | 6.55075 |
module implements the AMD 2909 bit slice microprogram sequencer.
*
* It closely follows the Am2909 data sheet.
*
* See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2909_am2911.pdf
*/
module Am2909(input wire clock, input wire [3:0] din, input wire [3:0] rin, input wire... | 7.842559 |
module implements the AMD 2911 bit slice microprogram sequencer.
*
* It closely follows the Am2911 data sheet.
*
* See https://github.com/Nakazoto/CenturionComputer/blob/main/Computer/CPU6%20Board/Datasheets/am2909_am2911.pdf
*/
module Am2911(input wire clock, input wire [3:0] din,
input wire s0, input wire s1... | 7.842559 |
module am2912 (
i,
e_,
b_,
z
);
parameter WIDTH = 4;
input [WIDTH-1:0] i;
input e_;
inout [WIDTH-1:0] b_;
output [WIDTH-1:0] z;
genvar n;
for (n = 0; n < WIDTH; n = n + 1) begin
assign b_[n] = (e_ == 'b0 && i[n] == 'b1) ? 'b0 : 'bZ;
assign z[n] = (b_[n] === 'b0) ? 'b1 : 'b0;
e... | 7.276096 |
module am2918 (
d,
cp,
oe_,
q,
y
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
input cp;
input oe_;
output [WIDTH-1:0] q;
output [WIDTH-1:0] y;
reg [WIDTH-1:0] q;
initial begin
q = 'b0;
end
always @(posedge cp) begin
q <= d;
end
assign y = oe_ ? 'bz : q;
endmodule... | 7.194412 |
module am2926 (
d,
be,
re_,
bus_,
r
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
input be, re_;
inout [WIDTH-1:0] bus_;
output [WIDTH-1:0] r;
assign bus_ = (be == 'b0) ? {WIDTH{1'bZ}} : d;
assign r = (re_ == 'b0) ? ~(~bus_) : {WIDTH{1'bZ}};
endmodule
| 6.733054 |
module am2929 (
d,
be,
re_,
bus_,
r
);
parameter WIDTH = 4;
input [WIDTH-1:0] d;
input be, re_;
inout [WIDTH-1:0] bus_;
output [WIDTH-1:0] r;
assign bus_ = (be == 'b0) ? {WIDTH{1'bZ}} : ~d;
assign r = (re_ == 'b0) ? ~bus_ : {WIDTH{1'bZ}};
endmodule
| 7.161033 |
module am2929_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] d;
reg [WIDTH-1:0] busin;
reg be, re;
wire [WIDTH-1:0] r, bus;
`define assert(signame, value, expval) \
if (expval !== value) begin \
$display("Error: %s should be %b, but is %b", signame, expval, value); \
end
task tester... | 7.026986 |
module am2948 (
a,
b,
tr_,
rc_
);
parameter WIDTH = 8;
inout [WIDTH-1:0] a, b;
input tr_, rc_;
always @(rc_ or tr_) begin
if (rc_ == 'b0 && tr_ == 'b0) begin
$display("Error: AM2948: RC and TR may not both be 0");
$stop;
end
end
assign a = (rc_ == 'b1) ? {WIDTH{1'bZ}} :... | 6.713465 |
module am2949 (
a,
b,
tr_,
rc_
);
parameter WIDTH = 8;
inout [WIDTH-1:0] a, b;
input tr_, rc_;
always @(rc_ or tr_) begin
if (rc_ == 'b0 && tr_ == 'b0) begin
$display("Error: AM2949: RC and TR may not both be 0");
$stop;
end
end
assign a = (rc_ == 'b1) ? {WIDTH{1'bZ}} :... | 6.510966 |
module am2954_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, cp;
wire [WIDTH-1:0] y;
am2954 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.cp (cp),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s... | 6.835335 |
module am2955 (
d,
y,
cp,
oe_
);
parameter WIDTH = 8;
input [WIDTH-1:0] d;
output [WIDTH-1:0] y;
input cp;
input oe_;
reg [WIDTH-1:0] q;
always @(posedge cp) begin
if (cp == 'b1) begin
q <= d;
end
end
assign y = (oe_ == 'b1) ? {WIDTH{1'bZ}} : ~q;
endmodule
| 6.635962 |
module am2955_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, cp;
wire [WIDTH-1:0] y;
am2955 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.cp (cp),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s... | 7.145273 |
module am2956_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, g;
wire [WIDTH-1:0] y;
am2956 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.g (g),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s s... | 6.733001 |
module am2957 (
d,
y,
g,
oe_
);
parameter WIDTH = 8;
input [WIDTH-1:0] d;
output [WIDTH-1:0] y;
input g;
input oe_;
reg [WIDTH-1:0] q;
always @(negedge g) begin
if (g == 'b0) begin
q <= d;
end
end
assign y = (oe_ == 'b1) ? {WIDTH{1'bZ}} : ~((g == 'b1) ? d : q);
endmod... | 6.792232 |
module am2957_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] d;
reg oe, g;
wire [WIDTH-1:0] y;
am2957 #(
.WIDTH(WIDTH)
) dut (
.d (d),
.g (g),
.oe_(oe),
.y (y)
);
`define ASSERT(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s s... | 6.939247 |
modules, if separate G is needed
module am2958(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? ~a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
modules, if separate G is needed
module am2959(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
module am29705 (
a,
b,
d,
we1_,
we2_,
le_,
oea_,
oeb_,
alo_,
ya,
yb
);
input [3:0] a, b;
input [3:0] d;
input we1_, we2_, le_;
input oea_, oeb_;
input alo_;
output [3:0] ya, yb;
reg [3:0] ram[0:15];
reg [3:0] alatch, blatch;
// RAM latches
always @(neged... | 6.825868 |
module am29811 (
i,
test,
oe_,
cntload_,
cnte_,
mape_,
ple_,
fe_,
pup,
s
);
input [3:0] i;
input test;
input oe_;
output cntload_, cnte_;
output mape_, ple_;
output fe_, pup;
output [1:0] s;
reg [7:0] tmp;
always @(i, test) begin
case (i)
`JZ: tmp = ... | 7.47623 |
module in main.v.
//
// This is set up to work within the limitations of the pinout of a
// BeagleWire board connected to a BeagleBone Black, where only a subset of
// the GPMC pins are connected to the FPGA. In particular, this is required to
// work in synchronous mode because the async "wait" pin is not connected.
/... | 7.135577 |
module am29811 (
input tst, // entry for conditional instructions
input [3:0] i, // microcode instruction
//
output [1:0] s, // address selector
output fe_n, // file enable
output pup, // push/pop_n
output ctl_n, // counter lo... | 7.47623 |
module am4_pulse #(
parameter
//
// Monovibrator pulse width in clock periods
//
AM4_PULSE_WIDTH_CLK = 100
) (
input clk, // input clock
input reset_n, // negative reset
input a_n, // negative start
input b, // positive start
output q // output
);
... | 6.670204 |
module mcrom (
input clk, // input clock
input ena, // clock enable
input [ 9:0] addr, // instruction address
output [55:0] data // output read opcode
);
//______________________________________________________________________________
//
// Memory array and its inititializ... | 6.539659 |
module mcrom (
input clk, // input clock
input ena, // clock enable
input [ 9:0] addr, // instruction address
output [55:0] data // output read opcode
);
wire [55:0] q;
//
// Instantiate the ROM IP based on top of BRAM9K
//
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(56),
... | 6.539659 |
module am74ls138_testbench;
reg a, b, c;
reg g1, g2a, g2b;
wire [7:0] y;
am74ls138 dut (
.a(a),
.b(b),
.c(c),
.g1(g1),
.g2a_(g2a),
.g2b_(g2b),
.y(y)
);
task tester;
input [80*8-1:0] descr;
input cval, bval, aval, g1val, g2aval, g2bval;
begin
a ... | 6.977244 |
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