code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module alu_i (
input [31:0] A,
input [31:0] B,
input [ 3:0] Code,
input Sel,
output reg [31:0] C,
output Less,
output Equal,
output Greater
);
//Codes (see defines.v) : Add=0 Shift_l=1 Shift_r=2 XOR=3 OR=4 AND=5 Comp=6 nop=7
//Sel : 0=signed 1=unsigned/subtraction
//Adder Signals
wire cout;
wire [31:0] b_adder;
assign b_adder = (Sel) ? (~B + 1) : B; //Sel add/sub encoding
//Comparator Signals
wire lt_s;
wire eq_s;
wire gt_s;
reg lt_u;
reg eq_u;
reg gt_u;
//Output selection signals
wire [31:0] y_adder, y_shift_l, y_shift_r;
wire y_lt;
assign y_lt = (Sel) ? lt_u : lt_s;
assign Less = y_lt;
assign Equal = (Sel) ? eq_u : eq_s;
assign Greater = (Sel) ? gt_u : gt_s;
//Submodule Instantiation
carry_select_adder u1 (
A,
b_adder,
1'b0,
y_adder,
cout
); //A, B, Cin, Y, Cout
magnitude_comparator u2 (
A,
B,
lt_s,
eq_s,
gt_s
); //A, B, Sel, Less, Equal, Greater
barrel_shifter u3 (
A,
B[4:0],
1'b0,
y_shift_l
); //A, Shamt, Sign_Extend, Y
barrel_shifter #(
.LEFT(0)
) u4 (
A,
B[4:0],
Sel,
y_shift_r
); //A, Shamt, Sign_Extend, Y
//Comparator Unsigned
always @(*) begin : comp_u
if (A[31] == B[31]) begin //A - B cannot overflow
if (y_adder[31] == 1'b0) begin
lt_u = 0;
if (y_adder[30:0] == 31'b0) begin
eq_u = 1;
gt_u = 0;
end else begin
eq_u = 0;
gt_u = 1;
end
end else begin
lt_u = 1;
eq_u = 0;
gt_u = 0;
end
end else if (A[31] == 1) begin //Automatically implies A is larger
lt_u = 0;
eq_u = 0;
gt_u = 1;
end else begin //Automatically implies A is smaller
lt_u = 1;
eq_u = 0;
gt_u = 0;
end
end
//Output Selection Block
always @(*) begin
case (Code)
`ADD: C = y_adder;
`SHIFT_L: C = y_shift_l;
`SHIFT_R: C = y_shift_r;
`XOR: C = A ^ B;
`OR: C = A | B;
`AND: C = A & B;
`COMP: C = {31'd0, y_lt};
default: begin
C = 32'd0;
end
endcase
end
endmodule
| 6.657808 |
module fulladder (
input x,
input y,
input cin,
output wire c_out,
output wire sum_out
);
wire carry1;
wire carry2;
wire sum1;
assign c_out = carry1 | carry2;
adder a1 (
.a(x),
.b(y),
.sum(sum1),
.cout(carry1)
);
adder a2 (
.a(sum1),
.b(cin),
.sum(sum_out),
.cout(carry2)
);
endmodule
| 7.454465 |
module ripple (
input [1:0] p,
input [1:0] q,
input c_in,
output [3:0] sum_out
);
wire take1;
assign sum_out[3] = 0;
fulladder f1 (
.x(p[0]),
.y(q[0]),
.cin(c_in),
.c_out(take1),
.sum_out(sum_out[0])
);
fulladder f2 (
.x(p[1]),
.y(q[1]),
.cin(take1),
.c_out(sum_out[2]),
.sum_out(sum_out[1])
);
endmodule
| 6.679037 |
module alu (
data1,
data2,
contr_in,
out,
zero_flag
);
input [31:0] data1;
input [31:0] data2;
input [3:0] contr_in;
output reg [31:0] out;
output reg zero_flag;
always @(data1 or data2 or contr_in) begin
case (contr_in)
4'b0010: begin
out = data1 + data2;
end
4'b0011: begin
out = data1 - data2;
end
4'b0000: begin
out = data1 * data2;
end
4'b0001: begin
out = data1 | data2;
end
endcase
if (out == 0) begin
zero_flag = 1;
end
end
endmodule
| 6.813467 |
module alu_input_stage (
alu_data1,
alu_data2,
hold1_data1,
hold1_data2,
hold2_data1,
hold2_data2,
hold3_data1,
hold3_data2,
hold4_data1,
hold4_data2,
prio_alu_in_cmd,
prio_alu_in_req_id
);
output [0:63] alu_data1, alu_data2;
wire [0:63] alu_data1, alu_data2;
input [0:31] hold1_data1, hold1_data2,
hold2_data1, hold2_data2,
hold3_data1, hold3_data2,
hold4_data1, hold4_data2;
input [0:3] prio_alu_in_cmd;
input [0:1] prio_alu_in_req_id;
assign alu_data1[32:63] =
prio_alu_in_req_id[0:1] == 2'b00 ? hold1_data1[0:31] :
prio_alu_in_req_id[0:1] == 2'b01 ? hold2_data1[0:31] :
prio_alu_in_req_id[0:1] == 2'b10 ? hold3_data1[0:31] :
prio_alu_in_req_id[0:1] == 2'b11 ? hold4_data1[0:31] :
32'b0;
assign alu_data2[32:63] =
prio_alu_in_req_id[0:1] == 2'b00 ? hold1_data2[0:31] :
prio_alu_in_req_id[0:1] == 2'b01 ? hold2_data2[0:31] :
prio_alu_in_req_id[0:1] == 2'b10 ? hold3_data2[0:31] :
prio_alu_in_req_id[0:1] == 2'b11 ? hold4_data2[0:31] :
32'b0;
assign alu_data1[0:31] = 32'b0;
assign alu_data2[0:31] = 32'b0;
endmodule
| 6.778653 |
module alu_shreg #(
parameter p = 3
) (
input wire clk,
input wire rst,
input wire [3:0] dm_re_i,
input wire [`REG_ADDR_WIDTH-1:0] rd_addr_i,
input wire regwrite_i,
input wire regwriteui_i,
input wire [1:0] regwritehilo_i,
input wire sr_i,
input wire branchen_i,
input wire [2:0] branchtype_i,
input wire [15:0] branchtarget_i,
input wire cmpsel_i,
output reg [ 3:0] dm_re_o, // should be named as sel_dm
output reg [`REG_ADDR_WIDTH-1:0] rd_addr_o,
output reg regwrite_o,
output reg regwriteui_o,
output reg [ 1:0] regwritehilo_o,
output reg sr_o,
output reg branchen_o,
output reg [ 2:0] branchtype_o,
output reg [ 15:0] branchtarget_o,
output reg cmpsel_o
);
reg [ 3:0] shreg_dm_re [0:p];
reg [`REG_ADDR_WIDTH-1:0] shreg_rd_addr [0:p];
reg shreg_regwrite [0:p];
reg shreg_regwriteui [0:p];
reg [ 1:0] shreg_regwritehilo[0:p];
reg shreg_sr [0:p];
reg shreg_branchen [0:p];
reg [ 2:0] shreg_branchtype [0:p];
reg [ 15:0] shreg_branchtarget[0:p];
reg shreg_cmpsel [0:p];
always@ (*) // Input
begin
shreg_dm_re[0] = dm_re_i;
shreg_rd_addr[0] = rd_addr_i;
shreg_regwrite[0] = regwrite_i;
shreg_regwriteui[0] = regwriteui_i;
shreg_regwritehilo[0] = regwritehilo_i;
shreg_sr[0] = sr_i;
shreg_branchen[0] = branchen_i;
shreg_branchtype[0] = branchtype_i;
shreg_branchtarget[0] = branchtarget_i;
shreg_cmpsel[0] = cmpsel_i;
end
always@ (*) // Ouput
begin
dm_re_o = shreg_dm_re[p];
rd_addr_o = shreg_rd_addr[p];
regwrite_o = shreg_regwrite[p];
regwriteui_o = shreg_regwriteui[p];
regwritehilo_o = shreg_regwritehilo[p];
sr_o = shreg_sr[p];
branchen_o = shreg_branchen[p];
branchtype_o = shreg_branchtype[p];
branchtarget_o = shreg_branchtarget[p];
cmpsel_o = shreg_cmpsel[p];
end
genvar i;
generate
for (i = 0; i < p; i = i + 1) begin : shregister_alu_shreg
always @(posedge clk) begin
if (rst) begin
shreg_dm_re[i+1] <= {4{1'b0}};
shreg_rd_addr[i+1] <= {`REG_ADDR_WIDTH{1'b0}};
shreg_regwrite[i+1] <= 1'b0;
shreg_regwriteui[i+1] <= 1'b0;
shreg_regwritehilo[i+1] <= {2{1'b0}};
shreg_sr[i+1] <= 1'b0;
shreg_branchen[i+1] <= 1'b0;
shreg_branchtype[i+1] <= {3{1'b0}};
shreg_branchtarget[i+1] <= {16{1'b0}};
shreg_cmpsel[i+1] <= 1'b0;
end else begin
shreg_dm_re[i+1] <= shreg_dm_re[i];
shreg_rd_addr[i+1] <= shreg_rd_addr[i];
shreg_regwrite[i+1] <= shreg_regwrite[i];
shreg_regwriteui[i+1] <= shreg_regwriteui[i];
shreg_regwritehilo[i+1] <= shreg_regwritehilo[i];
shreg_sr[i+1] <= shreg_sr[i];
shreg_branchen[i+1] <= shreg_branchen[i];
shreg_branchtype[i+1] <= shreg_branchtype[i];
shreg_branchtarget[i+1] <= shreg_branchtarget[i];
shreg_cmpsel[i+1] <= shreg_cmpsel[i];
end
end
end
endgenerate
endmodule
| 6.626683 |
module alu_internal (
A,
B,
Cin,
Op,
invA,
invB,
sign,
Out,
Ofl,
Z,
Cout,
neg
);
input [15:0] A;
input [15:0] B;
input Cin;
input [2:0] Op;
input invA;
input invB;
input sign;
output [15:0] Out;
output Ofl;
output Z;
output Cout; // carry out from addition
output neg;
wire [15:0] out_A, out_B; // versions of A and B to be used in datapath
wire [15:0] out_bs; // output of barrel shifter
wire [15:0] out_add; // output of adder
wire [15:0] out_or; // output of logical or operation
wire [15:0] out_xor; // output of logical xor operation
wire [15:0] out_and; // output of logical and operation
wire [15:0] out_logadd; // output of logical and add 4:1 mux
wire overflow_det; // overflow detection signal
// simplifies the code for the logic and add 4:1 mux
localparam ADD = 2'b00;
localparam OR = 2'b01;
localparam XOR = 2'b10;
localparam AND = 2'b11;
// inversion logic for inputs A and B
assign out_A = invA ? ~A : A;
assign out_B = invB ? ~B : B;
// barrel shifter logic
shifter barrel_shift (
.In (out_A),
.Cnt(out_B[3:0]),
.Op (Op[1:0]),
.Out(out_bs)
);
// carry look ahead adder logic
cla_16 adder (
.A(out_A),
.B(out_B),
.Cin(Cin),
.S(out_add),
.Cout(Cout)
);
// OR operation logic
assign out_or = out_A | out_B;
// XOR operation logic
assign out_xor = out_A ^ out_B;
// AND operation logic
assign out_and = out_A & out_B;
// logical and add 4:1 mux -- uses lower two bits of op code
assign out_logadd = Op[1:0] == ADD ? (out_add) :
(Op[1:0] == OR ? (out_or) :
(Op[1:0] == XOR ? (out_xor) :
(out_and))); // Op[1:0] == AND
// 2:1 for final Out bus
assign Out = Op[2] ? out_logadd : out_bs;
// create the zero output signal -- high when Out is zero
assign Z = (Out == 16'h0000) ? 1'b1 : 1'b0;
// create neg output signal -- high when output is negative
assign neg = ((Out[15] == 1'b1) && sign == 1'b1) ? (1'b1) : (1'b0);
assign overflow_det = sign ? ((out_add[15] & ~out_A[15] & ~out_B[15]) | (~out_add[15] & out_A[15] & out_B[15])) : (Cout);
assign Ofl = overflow_det & (Op == 3'b100);
endmodule
| 7.218787 |
module Alu (
Z,
A,
B,
INST,
FLAGS,
FirstCyc,
CLOCK
);
input [31:0] A;
input [31:0] B;
input [3:0] INST;
input FirstCyc;
input CLOCK;
output reg [31:0] Z;
output [3:0] FLAGS;
//data
wire [31:0] adder_out;
wire adder_co;
reg [31:0] ain, bin;
wire cin;
wire not_A_adder, not_B_adder;
wire not_A_logic, not_B_logic;
wire [31:0] and_AB, or_AB, xor_AB;
//controls
reg control_add_c;
reg [1:0] control_add_a;
reg [1:0] control_add_b;
wire skip_adder;
//input gating
wire gated_clock_adder, gated_clock_logic;
reg [31:0] adder_reg_A, adder_reg_B, adder_reg_C;
reg [31:0] logic_reg_A, logic_reg_B;
reg [3:0] adder_inst;
wire Cout, OVF;
reg abs_sig;
// Instructions supported by this ALU
localparam [3:0] add_1 = 4'b0000, sub_1 = 4'b0001, add_ab=4'b0010, sub_ab = 4'b0011,
abs_a = 4'b0100, neg_a = 4'b0101, neg_b =4'b0111, and_ab = 4'b1000,
or_ab = 4'b1001, xor_ab = 4'b1010, not_b =4'b1011, i_a = 4'b1100,
not_a = 4'b1101, i_0 = 4'b1110, i_1 = 4'b1111;
assign skip_adder = (adder_inst[3]);
assign gated_clock_adder = (CLOCK & ~skip_adder);
assign gated_clock_logic = (CLOCK & skip_adder);
//input gating registers
always @(posedge CLOCK) adder_inst = INST;
always @(posedge gated_clock_adder) begin
adder_reg_A = A;
adder_reg_B = B;
end
always @(posedge gated_clock_logic) begin
logic_reg_A = A;
logic_reg_B = B;
end
initial begin
adder_reg_A = 32'h0;
adder_reg_B = 32'h0;
adder_inst = 4'b0010;
adder_reg_C = 1'b0;
end
always @(*) begin
ain = adder_reg_A;
bin = 32'b0;
control_add_c = 1'b0;
abs_sig = 1'b0;
Z = adder_out;
case (adder_inst)
//input gating block 1 (adder)
add_1: begin
control_add_c = 1'b1;
end
sub_1: begin
bin = 32'hFFFF_FFFF;
end
add_ab: begin
bin = adder_reg_B;
end
sub_ab: begin
bin = ~adder_reg_B;
control_add_c = 1'b1;
end
abs_a: begin
if (adder_reg_A[31]) begin
ain = ~adder_reg_A;
control_add_c = 1'b1;
end
end
neg_a: begin
ain = ~adder_reg_A;
control_add_c = 1'b1;
end
neg_b: begin
ain = 32'b0;
bin = ~adder_reg_B;
control_add_c = 1'b1;
end
//input gating block 2 (logic)
and_ab: begin
Z = and_AB;
end
or_ab: begin
Z = or_AB;
end
xor_ab: begin
Z = xor_AB;
end
not_b: begin
Z = ~logic_reg_B;
end
i_a: begin
Z = logic_reg_A;
end
not_a: begin
Z = ~logic_reg_A;
end
i_0: begin
Z = 32'b0;
end
i_1: begin
Z = 32'hFFFFFFFF;
end
endcase
end
assign cin = (control_add_c);
adder a1 (
.A(ain),
.B(bin),
.Cin(cin),
.S(adder_out),
.Cout(Cout),
.OVF(OVF)
);
assign FLAGS[1] = Cout;
assign FLAGS[0] = OVF;
assign FLAGS[2] = ~(|Z);
//logic functions
assign and_AB = logic_reg_A & logic_reg_B;
assign or_AB = logic_reg_A | logic_reg_B;
assign xor_AB = logic_reg_A ^ logic_reg_B;
endmodule
| 7.167973 |
module alu_jump (
input wire [31:0] pc,
input wire [31:0] register,
input wire [25:0] target,
input wire [ 5:0] alu_opcode,
input wire nop,
input wire enable,
output reg [31:0] out_pc
// output reg [31:0] reg31
);
always @(*) begin
if (enable == 1) begin
if (!nop) begin
case (alu_opcode)
`j: begin
out_pc = ((pc & 32'hf0000000) | (target << 2));
end
`jr: begin
out_pc = register;
end
`jal: begin
out_pc = ((pc & 32'hf0000000) | (target << 2));
end
`jalr: begin
out_pc = register;
end
default: $display("not a jump");
endcase
end
end
end
endmodule
| 7.57796 |
module
*/
`include "adder_struct.v"
module Alu( Z, A, B, INST, SEL, EN );
////////
// IO //
////////
output [31:0] Z; // output data
input [31:0] A; // First Input Data, subtract is A-B
input [31:0] B; // Second Input Data, this is added to or subtracted from A
input [3:0] INST; // Instructions are defined in the localparam sectionnnnn
input SEL; // Select bit for select operations
input EN; // Enable to latches
////////////////////////////////////////
// Instructions supported by this ALU //
////////////////////////////////////////
localparam [3:0] add_ab = 4'b0000,
neg_a = 4'b0001,
and_ab = 4'b0010,
or_ab = 4'b0011,
xor_ab = 4'b0100,
inv_a = 4'b0101,
sel_ab = 4'b0110,
sel_ba = 4'b0111,
sub_ab = 4'b1000,
a_lt_b = 4'b1001,
a_lte_b = 4'b1010,
a_gt_b = 4'b1011,
a_gte_b = 4'b1100,
a_eq_b = 4'b1101,
a_ne_b = 4'b1110,
sel_xor_b = 4'b1111;
////////////
// Output //
////////////
reg [31:0] Z;
////////////////////////
// Intermediate Nodes //
////////////////////////
reg [31:0] adder_a, adder_b;
wire [31:0] adder_out;
reg adder_cin;
reg [31:0] A_latch, B_latch;
reg SEL_latch;
// Latch inputs (A, B, SEL)
always @ (*)
if (EN == 1'b1) begin
A_latch = A;
B_latch = B;
SEL_latch = SEL;
end
/////////////////////////
// Set up Adder inputs //
/////////////////////////
always @ (*) begin
case (INST)
add_ab: begin
adder_a = A_latch;
adder_b = B_latch;
adder_cin = 1'b0;
end
neg_a: begin
adder_a = ~A_latch;
adder_b = 0;
adder_cin = 1'b1;
end
//and_ab:// don't use adder
//or_ab: begin // don't use adder
//xor_ab:// don't use adder
//inv_a: // don't use adder
//sel_ab: begin // don't use adder
//sel_ba: begin // don't use adder
sub_ab: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
a_lt_b: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
a_lte_b: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
a_gt_b: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
a_gte_b: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
a_eq_b: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
a_ne_b: begin
adder_a = A_latch;
adder_b = ~B_latch;
adder_cin = 1'b1;
end
//sel_xor_b: // don't use adder
default: begin
// default latch inputs to adder
adder_a = adder_a;
adder_b = adder_b;
adder_cin = adder_cin;
end
endcase
end
///////////
// Adder //
///////////
adder struct_adder (.A(adder_a),.B(adder_b),.Cin(adder_cin),.S(adder_out),
.OVF(overflow));
assign zero = ~(|adder_out);
////////////////
// Output MUX //
////////////////
always @ (*) begin
case (INST)
// add_ab:
// neg_a:
and_ab: Z = A_latch & B_latch;
or_ab: Z = A_latch | B_latch;
xor_ab: Z = A_latch ^ B_latch;
inv_a: Z = ~A_latch;
sel_ab:
if (~SEL_latch) Z = A_latch;
else Z = B_latch;
sel_ba:
if (SEL_latch) Z = A_latch;
else Z = B_latch;
// sub_ab:
a_lt_b: Z = {31'b0,adder_out[31]^overflow};
a_lte_b: Z = {31'b0,(adder_out[31]^overflow)|zero};
a_gt_b: Z = {31'b0,~adder_out[31]^overflow};
a_gte_b: Z = {31'b0,(~adder_out[31]^overflow)|zero};
a_eq_b: Z = {31'b0,zero};
a_ne_b: Z = {31'b0,~zero};
sel_xor_b: Z = {31'b0,SEL_latch^B_latch};
default: Z = adder_out;
endcase
end
endmodule
| 7.722981 |
module ALU_LEGv8 (
input [63:0] Ain,
Bin,
input carryIn,
input [4:0] ALUCtl,
output logic [63:0] ALUOut,
output logic [3:0] status
);
logic [63:0] A, B;
logic [64:0] sum;
always_comb begin
A = ALUCtl[1] ? ~Ain : Ain;
B = ALUCtl[0] ? ~Bin : Bin;
sum = A + B + carryIn;
case (ALUCtl[4:2])
0: ALUOut = A & B;
1: ALUOut = A | B;
2: ALUOut = sum[63:0];
3: ALUOut = A ^ B;
4: ALUOut = Ain << Bin[5:0];
5: ALUOut = Ain >> Bin[5:0];
default: ALUOut = 0;
endcase //overflow, carry, negative, zero
status = {~(A[63] ^ B[63]) & (ALUOut[63] ^ A[63]), 1'b0, ALUOut[63], ALUOut == 0};
end
endmodule
| 7.309055 |
module alu (
A,
B,
cin,
select,
out,
status
);
input [63:0] A, B;
input cin;
input [4:0] select;
output [63:0] out;
output [3:0] status;
// SELECT CODES
// xxxx1 Invert A
// xxx1x Invert B
// 000xx A AND B
// 001xx A OR B
// 010xx A XOR B
// 011xx ADD A B
// 100xx A << B
// 101xx A >> B
// 110xx 0
// 111xx 0
wire [63:0] ASignal, BSignal;
inversion inv (
A,
B,
select[1:0],
ASignal,
BSignal
);
wire [63:0] andAB, orAB, xorAB, addAB, left, right;
wire overflow, cout, negative, zero;
assign status = {overflow, cout, negative, zero};
logicOut log (
ASignal,
BSignal,
andAB,
orAB,
xorAB
);
adder add (
ASignal,
BSignal,
cin,
addAB,
cout
);
shift shifter (
A,
B,
left,
right
);
muxOut mux (
select[4:2],
out,
andAB,
orAB,
xorAB,
addAB,
left,
right
);
assign negative = out[63];
assign overflow = ~(ASignal[63] ^ BSignal[63]) & (out[63] ^ ASignal[63]);
assign zero = (out == 64'b0) ? 1'b1 : 1'b0;
endmodule
| 7.41692 |
module inversion (
A,
B,
select,
AOut,
BOut
);
input [63:0] A, B;
input [1:0] select;
output [63:0] AOut, BOut;
assign AOut = select[0] ? ~A : A;
assign BOut = select[1] ? ~B : B;
endmodule
| 7.129544 |
module logicOut (
A,
B,
andAB,
orAB,
xorAB
);
input [63:0] A, B;
output [63:0] andAB, orAB, xorAB;
assign andAB = A & B;
assign orAB = A | B;
assign xorAB = A ^ B;
endmodule
| 6.873034 |
module shift (
A,
B,
left,
right
);
input [63:0] A, B;
output [63:0] left, right;
assign left = A << B[5:0];
assign right = A >> B[5:0];
endmodule
| 6.608895 |
module muxOut (
select,
out,
andAB,
orAB,
xorAB,
addAB,
shiftLA,
shiftRA
);
input [2:0] select;
output reg [63:0] out;
input [63:0] andAB, orAB, xorAB, addAB, shiftLA, shiftRA;
always @(*) begin
case (select)
3'b000: out <= andAB;
3'b001: out <= orAB;
3'b010: out <= xorAB;
3'b011: out <= addAB;
3'b100: out <= shiftLA;
3'b101: out <= shiftRA;
default: out <= 64'b0;
endcase
end
endmodule
| 8.714561 |
module ALU_LEGv8 (
A,
B,
FS,
C0,
F,
status
);
input [63:0] A, B;
input [4:0] FS;
// FS0 - b invert
// FS1 - a invert
// FS4:2 - op. select
// 000 - AND
// 001 - OR
// 010 - ADD
// 011 - XOR
// 100 - shift left
// 101 - shift right
// 110 - none / 0
// 111 - none / 0
input C0;
output [63:0] F;
output [3:0] status;
wire Z, N, C, V;
assign status = {V, C, N, Z};
wire [63:0] A_Signal, B_Signal;
// A Mux
assign A_Signal = FS[1] ? ~A : A;
// B Mux
assign B_Signal = FS[0] ? ~B : B;
assign N = F[63];
assign Z = (F == 64'b0) ? 1'b1 : 1'b0;
assign V = ~(A_Signal[63] ^ B_Signal[63]) & (F[63] ^ A_Signal[63]);
wire [63:0] and_output, or_output, xor_output, add_output, shift_left, shift_right;
assign and_output = A_Signal & B_Signal;
assign or_output = A_Signal | B_Signal;
assign xor_output = A_Signal ^ B_Signal;
Adder adder_inst (
add_output,
C,
A_Signal,
B_Signal,
C0
);
Shifter shift_inst (
shift_left,
shift_right,
A,
B[5:0]
);
Mux8to1Nbit main_mux (
F,
FS[4:2],
and_output,
or_output,
add_output,
xor_output,
shift_left,
shift_right,
64'b0,
64'b0
);
endmodule
| 7.309055 |
module Adder (
S,
Cout,
A,
B,
Cin
);
input [63:0] A, B;
input Cin;
output [63:0] S;
output Cout;
wire [64:0] carry;
assign carry[0] = Cin;
assign Cout = carry[64];
// use generate block to instantiate 64 full adders
genvar i;
generate
for (
i = 0; i < 64; i = i + 1
) begin : full_adders // blocks within a generate block need to be named
FullAdder adder_inst (
S[i],
carry[i+1],
A[i],
B[i],
carry[i]
);
end
endgenerate
// this will generate the following code:
// FullAdder full_adders[0].adder_inst (S[0], carry[1], A[0], B[0], carry[0]);
// FullAdder full_adders[1].adder_inst (S[1], carry[2], A[1], B[1], carry[1]);
// ...
// FullAdder full_adders[63].adder_inst (S[63], carry[64], A[63], B[63], carry[63]);
endmodule
| 8.145585 |
module FullAdder (
S,
Cout,
A,
B,
Cin
);
input A, B, Cin;
output S, Cout;
assign S = A ^ B ^ Cin;
assign Cout = A & B | A & Cin | B & Cin;
endmodule
| 7.610141 |
module ALU_LEGv8_Testbench ();
reg [63:0] A, B;
reg [4:0] FS;
reg C0;
wire [63:0] F;
wire [3:0] status;
ALU_LEGv8 dut (
A,
B,
FS,
C0,
F,
status
);
integer errors;
initial begin
errors <= 0;
FS <= 5'b00000; // A AND B
/*
A <= 64'b110;
B <= 64'b011;
#5
FS <= 5'b00100; // A OR B
#5
FS <= 5'b01000; // A + B
C0 <= 1'b0;
#5 FS <= 5'b01100; // A XOR B
#5 A <= {$random, $random};
B <= {$random, $random};
#5 FS <= 5'b00011; // ~A AND ~B = A NOR B
#5 FS <= 5'b00111; // ~A OR ~B = A NAND B
#5 FS <= 5'b10000; // shift left
A <= 64'b1; // shift 1 a random number of times
#5 FS <= 5'b10100; // shift right
A <= 64'h8000000000000000;*/
#320 $display("total errors: %d", errors);
$stop;
end
// every 5 ticks select a random operation with random operands
always begin
#10 FS <= FS + 1;
A <= 64'b11;
B <= 64'b10;
C0 <= 1'b0;
end
// implement the ALU a second time in behavior verilog to come up with an expected value
// then compare the two
reg [63:0] Fexp;
// implement the A/Anot and B/Bnot muxes
wire [63:0] A2, B2;
assign A2 = FS[1] ? ~A : A;
assign B2 = FS[0] ? ~B : B;
always @(*) begin
case (FS[4:2])
3'b000: Fexp <= A2 & B2;
3'b001: Fexp <= A2 | B2;
3'b010: Fexp <= A2 + B2 + C0;
3'b011: Fexp <= A2 ^ B2;
3'b100: Fexp <= A << B[5:0];
3'b101: Fexp <= A >> B[5:0];
3'b110: Fexp <= 64'b0;
3'b111: Fexp <= 64'b0;
endcase
end
// create a signal that will indicate if the expected and actual values match
// and display a message if they don't with what is being done
reg good;
always begin
#5 good = (F == Fexp) ? 1'b1 : 1'b0;
if (F != Fexp) begin
$display("time %d, F %x, Fexp %x, FS %b, A %x, B %x", $time, F, Fexp, FS, A, B);
errors <= errors + 1;
end
end
endmodule
| 7.492239 |
module NOT (
input wire a,
output wire y
);
assign y = !a;
endmodule
| 7.525099 |
module NAND (
input wire a,
b,
output wire y
);
wire x;
AND p (
a,
b,
x
);
NOT q (
x,
y
);
endmodule
| 7.731629 |
module NOR (
input wire a,
b,
output wire y
);
wire x;
OR p (
a,
b,
x
);
NOT q (
x,
y
);
endmodule
| 7.366253 |
module two_to_one_mux (
input wire [1:0] i,
input wire s,
output wire y
);
assign y = s ? i[1] : i[0];
endmodule
| 7.326213 |
module four_to_one_mux (
input wire [3:0] i,
input wire [1:0] s,
output wire y
);
wire [1:0] r;
two_to_one_mux m1 (
i[1:0],
s[0],
r[0]
);
two_to_one_mux m2 (
i[3:2],
s[0],
r[1]
);
two_to_one_mux m3 (
r[1:0],
s[1],
y
);
endmodule
| 6.763352 |
module eight_to_one_mux (
input wire [7:0] i,
input wire [2:0] s,
output wire y
);
wire [1:0] x;
four_to_one_mux m1 (
i[3:0],
s[1:0],
x[0]
);
four_to_one_mux m2 (
i[7:4],
s[1:0],
x[1]
);
two_to_one_mux m3 (
x[1:0],
s[2],
y
);
endmodule
| 6.584362 |
module ALU_LL (
input [3:0] G_sel,
input [31:0] A,
input [31:0] B,
output reg [31:0] G,
output [3:0] ZCNVFlags
);
//reg carry_in;
wire carry_out;
wire [31:0] Arithmetic_result, Logical_result;
//TODO new adder topology needed
ripple_carry_adder_subtractor #(
.N(32)
) rcas (
.A(A),
.B(B),
.Cin(G_sel[0]),
.Cout(ZCNVFlags[2]),
.S(Arithmetic_result)
);
logical_unit lu (
.L_sel(G_sel[2:1]),
.A(A),
.B(B),
.G(Logical_result)
);
parameter ADD = 4'b0000, SUB = 4'b0001, XOR = 4'b1000, OR = 4'b1100, AND = 4'b1110;
wire signed [31:0] A_signed = A, B_signed = B;
always @(*) begin
if (G_sel[3]) G = Logical_result;
else G = Arithmetic_result;
end
//Overflow detection circuit
//ADD => G_sel[0] == 0
//SUB => G_sel[0] == 1
//if in addition both A and B are positive and the result is negative or both A and B are negative and the result is positive OR
//in subtraction A is negative and B is positive and the result is positive or A is positive and B is negative and the result is negative
//then overflow is detected
assign ZCNVFlags[0] = (!G_sel[0] & A_signed[31] & B_signed[31] & !Arithmetic_result[31]) |
(!G_sel[0] & !A_signed[31] & !B_signed[31] & Arithmetic_result[31])|
(G_sel[0] & A_signed[31] & !B_signed[31] & !Arithmetic_result[31])|
(G_sel[0] & !A_signed[31] & B_signed[31] & Arithmetic_result[31]);
//Negative flag checks the sign bit of the result
assign ZCNVFlags[1] = Arithmetic_result[31];
//Zero detection is done by ORing the bits of the result
assign ZCNVFlags[3] = !(|Arithmetic_result);
endmodule
| 7.21199 |
module Rev 0.0 07/17/2011 **/
/** **/
/*******************************************************************************************/
module alu_log (logic_c, logic_hc, logic_out, alua_in, alub_in, aluop_reg, carry_bit);
input carry_bit; /* cpu carry flag */
input [15:0] alua_in; /* alu a input */
input [15:0] alub_in; /* alu b input */
input [`AOP_IDX:0] aluop_reg; /* alu operation control */
output logic_c; /* alu logic carry result */
output logic_hc; /* alu logic half-carry result */
output [15:0] logic_out; /* alu logic result */
/*****************************************************************************************/
/* */
/* signal declarations */
/* */
/*****************************************************************************************/
reg logic_c; /* logic carry output */
reg logic_hc; /* logic half-carry output */
reg [15:0] logic_out; /* logic output */
/*****************************************************************************************/
/* */
/* alu logic function */
/* */
/*****************************************************************************************/
always @ (aluop_reg or carry_bit) begin
casex (aluop_reg)
`AOP_CCF: logic_c = !carry_bit;
`AOP_SCF: logic_c = 1'b1;
default: logic_c = 1'b0;
endcase
end
always @ (aluop_reg or carry_bit) begin
casex (aluop_reg)
`AOP_BAND: logic_hc = 1'b1;
`AOP_CCF: logic_hc = carry_bit;
default: logic_hc = 1'b0;
endcase
end
always @ (aluop_reg or alua_in or alub_in) begin
casex (aluop_reg)
`AOP_BAND: logic_out = {8'h00, alua_in[7:0] & alub_in[7:0]};
`AOP_BOR: logic_out = {8'h00, alua_in[7:0] | alub_in[7:0]};
`AOP_BXOR: logic_out = {8'h00, alua_in[7:0] ^ alub_in[7:0]};
`AOP_RLD1: logic_out = {8'h00, alub_in[3:0], alua_in[3:0]};
`AOP_RLD2: logic_out = {8'h00, alua_in[7:4], alub_in[7:4]};
`AOP_RRD1: logic_out = {8'h00, alua_in[3:0], alub_in[7:4]};
`AOP_RRD2: logic_out = {8'h00, alua_in[7:4], alub_in[3:0]};
`AOP_APAS: logic_out = alua_in;
`AOP_PASS: logic_out = alub_in;
default: logic_out = 16'h0000;
endcase
end
endmodule
| 8.238592 |
module W0RM_ALU_Logic #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
output wire [ 3:0] result_flags
);
localparam MSB = DATA_WIDTH - 1;
localparam ALU_OPCODE_AND = 4'h0;
localparam ALU_OPCODE_OR = 4'h1;
localparam ALU_OPCODE_XOR = 4'h2;
localparam ALU_OPCODE_NOT = 4'h3;
localparam ALU_OPCODE_NEG = 4'h4;
localparam ALU_FLAG_ZERO = 4'h0;
localparam ALU_FLAG_NEG = 4'h1;
localparam ALU_FLAG_OVER = 4'h2;
localparam ALU_FLAG_CARRY = 4'h3;
reg [DATA_WIDTH-1:0] result_r = 0, data_a_r = 0, data_b_r = 0;
reg result_valid_r = 0;
reg [DATA_WIDTH-1:0] result_i = 0;
reg result_valid_i = 0;
assign result = result_r;
assign result_valid = result_valid_r;
assign result_flags[ALU_FLAG_ZERO] = result_r == 0;
assign result_flags[ALU_FLAG_NEG] = result_r[MSB];
assign result_flags[ALU_FLAG_OVER] = ((~result_r[MSB]) && data_a_r[MSB] && data_b_r[MSB]) ||
(result_r[MSB] && (~data_a_r[MSB]) && (~data_b_r[MSB]));
assign result_flags[ALU_FLAG_CARRY] = 1'b0; // Carry not defined for logic ops
always @(data_valid, opcode, data_a, data_b) begin
result_valid_i = data_valid;
if (data_valid) begin
case (opcode)
ALU_OPCODE_AND: begin
result_i = data_a & data_b;
end
ALU_OPCODE_OR: begin
result_i = data_a | data_b;
end
ALU_OPCODE_XOR: begin
result_i = data_a ^ data_b;
end
ALU_OPCODE_NOT: begin
result_i = ~data_a;
end
ALU_OPCODE_NEG: begin
result_i = ~data_a + 1;
end
default: begin
result_i = {DATA_WIDTH{1'b0}};
end
endcase
end else begin
result_i = {DATA_WIDTH{1'b0}};
end
end
generate
if (SINGLE_CYCLE) begin
always @(data_a, data_b, result_i, result_valid_i) begin
data_a_r = data_a;
data_b_r = data_b;
result_r = result_i;
result_valid_r = result_valid_i;
end
end else begin
always @(posedge clk) begin
result_valid_r <= data_valid;
if (data_valid) begin
data_a_r <= data_a;
data_b_r <= data_b;
result_r <= result_i;
end
end
end
endgenerate
endmodule
| 7.236663 |
module ALU_logical (
A,
B,
C,
Y
);
input [3:0] A, B;
input [2:0] C;
output reg [6:0] Y;
wire [3:0] t_no_Cin;
wire [6:0] result0, result1, result2, result3, result4, result5, result6, result7;
assign result0[4:0] = A + B;
assign result0[5] = (A[3] == B[3]) && (A[3] != result0[3]); // overflow
assign result0[6] = ~(|result0[3:0]); // zero
assign t_no_Cin = ~B;
assign result1[4:0] = A + t_no_Cin + 1; // {carry, result}
assign result1[5] = (A[3] == t_no_Cin[3]) && (A[3] != result1[3]); // overflow
assign result1[6] = ~(|result1[3:0]); // zero
assign result2[6:4] = 3'b0;
assign result3[6:4] = 3'b0;
assign result4[6:4] = 3'b0;
assign result5[6:4] = 3'b0;
assign result6[6:1] = 6'b0;
assign result7[6:1] = 6'b0;
assign result2[3:0] = ~A;
assign result3[3:0] = A & B;
assign result4[3:0] = A | B;
assign result5[3:0] = A ^ B;
assign result6[0] = (A[3] == B[3] && A[2:0] > B[2:0]) || (A[3] == 0) && (B[3] == 1); // A > B
assign result7[0] = (A == B);
always @(*)
case (C)
3'd0: Y = result0;
3'd1: Y = result1;
3'd2: Y = result2;
3'd3: Y = result3;
3'd4: Y = result4;
3'd5: Y = result5;
3'd6: Y = result6;
3'd7: Y = result7;
default: Y = 7'bx;
endcase
endmodule
| 6.657799 |
module alu_logic_arithmetic (
input [3:0] alu_op,
input [31:0] A,
input [31:0] B,
output reg [31:0] C
);
always @(*) begin
case (alu_op)
`AND: C = A & B;
`OR: C = A | B;
`XOR: C = A ^ B;
default: C = 32'b0;
endcase
end
endmodule
| 7.316552 |
module ALU_Logic_1_tb (
output wire done,
error
);
ALU_Logic_base_tb #(
.DATA_WIDTH (8),
.FILE_SOURCE ("../testbench/data/core/ALU_Logic_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_Logic_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.206317 |
module alu_logic_arithmetic (
input [3:0] alu_op,
input [31:0] A,
input [31:0] B,
output reg [31:0] C
);
always @(*) begin
case (alu_op)
`AND: C = A & B;
`OR: C = A | B;
`XOR: C = A ^ B;
default: C = 32'b0;
endcase
end
endmodule
| 7.316552 |
module ALU_Logic_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = FLAGS_WIDTH + DATA_WIDTH;
reg clk = 0;
reg fs_go = 0;
wire fs_done;
wire valid;
wire [DATA_WIDTH-1:0] data_a, data_b;
wire [ 3:0] opcode;
wire result_valid;
wire [ DATA_WIDTH-1:0] result;
wire [FLAGS_WIDTH-1:0] result_flags;
always #2.5 clk <= ~clk;
initial #50 fs_go <= 1'b1;
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk (clk),
.ready(fs_go),
.valid(valid),
.empty(fs_done),
.data ({data_valid, opcode, data_a, data_b})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(result_valid),
.data ({result_flags, result}),
.done (done),
.error(error)
);
W0RM_ALU_Logic #(
.SINGLE_CYCLE(0),
.DATA_WIDTH (8)
) dut (
.clk(clk),
.data_valid(valid & data_valid),
.opcode(opcode),
.data_a(data_a),
.data_b(data_b),
.result(result),
.result_valid(result_valid),
.result_flags(result_flags)
);
endmodule
| 7.424547 |
module alu_lsl (
input [15:0] operand1,
input [ 3:0] immediate_offset,
output [15:0] dout
);
assign dout = operand1 << immediate_offset;
endmodule
| 7.520451 |
module alu_lsr (
input [15:0] operand1,
input [ 3:0] immediate_offset,
output [15:0] dout
);
assign dout = operand1 >> immediate_offset;
endmodule
| 7.480446 |
module ALU_Main (
input clk,
input S,
input [31:0] B,
input [31:0] A,
input [3:0] ALU_op,
input Shift_carry_out,
input CF,
input VF,
output reg [31:0] F,
output reg [ 3:0] NZCV
);
reg Cout;
localparam FN = 3, FZ = 2, FC = 1, FV = 0;
always @(*) begin
case (ALU_op)
4'h0: begin
F <= A & B;
end
4'h1: begin
F <= A ^ B;
end
4'h2: begin
{Cout, F} <= A - B;
end
4'h3: begin
{Cout, F} <= B - A;
end
4'h4: begin
{Cout, F} <= A + B;
end
4'h5: begin
{Cout, F} <= A + B + CF;
end
4'h6: begin
{Cout, F} <= A - B + CF - 1;
end
4'h7: begin
{Cout, F} <= B - A + CF - 1;
end
4'h8: begin
F <= A;
end
4'hA: begin
{Cout, F} <= A - B + 32'h4;
end
4'hC: begin
F <= A | B;
end
4'hD: begin
F <= B;
end
4'hE: begin
F <= A & (~B);
end
4'hF: begin
F <= ~B;
end
endcase
end
always @(negedge clk) begin
if (S == 1) begin
NZCV[FN] <= F[31];
if (F != 32'b0) NZCV[FZ] <= 0;
else NZCV[FZ] <= 1;
case (ALU_op)
4'h0, 4'h1, 4'hC, 4'hE, 4'hF, 4'h8, 4'hD: begin
NZCV[FC] <= Shift_carry_out;
NZCV[FV] <= VF;
end
4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7, 4'hA: begin
NZCV[FC] <= ALU_op[1] ^ Cout;
NZCV[FV] <= A[31] ^ B[31] ^ F[31] ^ Cout;
end
endcase
end
end
endmodule
| 6.856935 |
module ALU_MD (
ALU_MD_ctrl,
A,
B,
ALU_MD_out
);
input [2:0] ALU_MD_ctrl; //3'b000 signed *
//3'b001 unsigned *
//3'b010 signed /
//3'b011 unsigned /
//3'b100 mfhi
//3'b101 mflo
input [31:0] A, B; //rs data,rt data
output [31:0] ALU_MD_out; //hi data or lo data
reg [31:0] hi, lo;
always @(*) begin
case (ALU_MD_ctrl)
3'b000: {hi, lo} <= $signed(A) * $signed(B);
3'b001: {hi, lo} <= A * B;
3'b010: begin
lo <= $signed(A) / $signed(B);
hi <= $signed(A) % $signed(B);
end
3'b011: begin
lo <= A / B;
hi <= A % B;
end
endcase
end
assign ALU_MD_out = (ALU_MD_ctrl == 3'b100) ? hi : lo;
endmodule
| 7.54397 |
module ALU_MEM (
input wire [ `ALUOp] aluop,
input wire [`DataBus] alures_i,
input wire [ `DWord] mulhi,
input wire [ `DWord] mullo,
input wire mul_s,
input wire [ `DWord] divres,
input wire [ `DWord] hilo_i,
input wire [`CP0Addr] cp0sel,
input wire exc_flag,
output reg [`DataBus] alures_o,
output wire [`DataBus] mulres,
output reg hilo_wen,
output reg [ `DWord] hilo_o,
output reg cp0_wen,
output reg [`CP0Addr] cp0_addr,
output reg [`DataBus] cp0_wdata,
input wire [`DataBus] cp0_rdata,
output reg resnrdy
);
wire [ 47:0] reslo = mullo[31:0] + (mullo[63:32] << 16);
wire [ 47:0] reshi = mulhi[31:0] + (mulhi[63:32] << 16);
wire [`DWord] umres = reslo + (reshi << 16);
wire [`DWord] smres = mul_s ? ~umres + 64'b1 : umres;
assign mulres = smres;
always @(*) begin
alures_o <= alures_i;
cp0_addr <= `CP0_ZeroReg;
cp0_wen <= `false;
cp0_wdata <= `ZeroWord;
case (aluop)
`ALU_MFHI: alures_o <= hilo_i[`Hi];
`ALU_MFLO: alures_o <= hilo_i[`Lo];
`ALU_MFC0: begin
cp0_addr <= cp0sel;
alures_o <= cp0_rdata;
end
`ALU_MTC0: begin
cp0_addr <= cp0sel;
cp0_wen <= !exc_flag;
cp0_wdata <= alures_i;
end
endcase
case (aluop)
`ALU_MTHI: begin
hilo_wen <= `true;
hilo_o <= {alures_i, hilo_i[`Lo]};
end
`ALU_MTLO: begin
hilo_wen <= `true;
hilo_o <= {hilo_i[`Hi], alures_i};
end
`ALU_MULT: begin
hilo_wen <= `true;
hilo_o <= smres;
end
`ALU_MULTU: begin
hilo_wen <= `true;
hilo_o <= umres;
end
`ALU_MADD: begin
hilo_wen <= `true;
hilo_o <= hilo_i + smres;
end
`ALU_MADDU: begin
hilo_wen <= `true;
hilo_o <= hilo_i + umres;
end
`ALU_MSUB: begin
hilo_wen <= `true;
hilo_o <= hilo_i - smres;
end
`ALU_MSUBU: begin
hilo_wen <= `true;
hilo_o <= hilo_i - umres;
end
`ALU_DIV, `ALU_DIVU: begin
hilo_wen <= `true;
hilo_o <= divres;
end
default: begin
hilo_wen <= `false;
hilo_o <= hilo_i;
end
endcase
case (aluop)
`ALU_MUL, `ALU_LB, `ALU_LBU, `ALU_LH, `ALU_LHU, `ALU_LW, `ALU_LWL, `ALU_LWR, `ALU_LL:
resnrdy <= `true;
default: resnrdy <= `false;
endcase
end
endmodule
| 6.646939 |
module Logic_unit (
input wire [0:2] COMMAND,
input wire A,
input wire B,
output wire NOT_B,
output wire A_OR_B,
output wire A_AND_B
);
assign NOT_B = COMMAND[2] & (~B);
assign A_OR_B = ((COMMAND[1] & A) | (COMMAND[1] & B));
assign A_AND_B = ((COMMAND[0] & A) & (COMMAND[0] & B));
endmodule
| 6.91066 |
module Alu (
input wire A,
input wire B,
input wire [0:1] COMMAND,
output wire RES,
output wire CARRY
);
wire [0:3] Q;
wire NOT_B, A_AND_B, A_OR_B, SUM;
Command_decoder com_imp (
COMMAND,
Q
);
Sum sum_imp (
Q[0],
A,
B,
SUM,
CARRY
);
Logic_unit logic_imp (
Q[1:3],
A,
B,
NOT_B,
A_OR_B,
A_AND_B
);
assign RES = NOT_B | A_AND_B | A_OR_B | SUM;
endmodule
| 6.778546 |
module Memory (
input wire CLK, // Тактирование
input wire LOAD, // Сигнал разрешения рагрузки
input wire RST, // Сброс
input wire [0:3] INPUT_DATA, // Шина входных слов
output reg [0:3] OUTPUT_COMMAND // Шина выходных слов
);
reg [0:3] memory[0:7]; // Внутренняя память (ОЗУ)
reg [0:2] input_count = 0; // Счетчик количества считанных слов
integer i = 0;
reg [0:2] output_count = 0; // Счетчик количества выданных слов
always @(posedge CLK or posedge RST) begin
if (RST) begin // Очищаем все регистры
for (i = 0; i < 8; i = i + 1) memory[i] = 3'hx;
OUTPUT_COMMAND = 3'hx;
output_count = 0;
input_count = 0;
end else begin // Cчитываем с входной шины слова в память
if (LOAD) begin
if (input_count != 8) begin
memory[input_count] = INPUT_DATA;
input_count = input_count + 1;
end
end else begin // Считываем слова из памяти
OUTPUT_COMMAND = memory[output_count];
if (output_count > 7) begin
output_count = 0;
end else begin
output_count = output_count + 1;
end
end // end of else if (LOAD)
end // end of else if (RST)
end // end of always @(posedge CLK or posedge RST)
endmodule
| 7.051739 |
module alu_mem_buff #(
parameter WbSize = 2,
MemSize = 9,
flagSize = 4
) (
input rst,
input clk,
enable,
input [MemSize-1:0] i_Mem,
input [WbSize-1 : 0] i_WB,
input [31:0] i_pc,
input [2:0] i_Rdst,
input [15:0] i_alu,
i_read_data1,
input [flagSize-1:0] i_flag,
output reg [WbSize-1 : 0] o_WB,
output reg [MemSize-1:0] o_Mem,
output reg [31:0] o_pc,
output reg [2:0] o_Rdst,
output reg [15:0] o_alu,
o_read_data1,
output reg [flagSize-1:0] o_flag
);
always @(negedge clk) begin
if (rst == 1'b1) begin
o_WB <= 0;
o_Mem <= 0;
o_pc <= 0;
o_read_data1 <= 0;
o_Rdst <= 0;
o_alu <= 0;
o_flag <= 0;
end else if (enable == 1'b1) begin
o_WB <= i_WB;
o_Mem <= i_Mem;
o_pc <= i_pc;
o_read_data1 <= i_read_data1;
o_Rdst <= i_Rdst;
o_alu <= i_alu;
o_flag <= i_flag;
end
end
endmodule
| 6.821875 |
module alu_mem_pipeline_reg (
alu_result,
base_reg_content_load_post,
mem_data_write,
wb_address,
base_register_address,
mem_control,
wb_control,
clock,
alu_result_out,
base_reg_content_out,
mem_data_write_out,
wb_address_out,
base_register_address_out,
mem_control_out,
wb_control_out
);
parameter mem_control_word_width = 7;
parameter wb_control_word_width = 2;
input wire [31:0] alu_result, base_reg_content_load_post, mem_data_write;
input wire [3:0] wb_address, base_register_address;
input wire [mem_control_word_width-1:0] mem_control;
input wire [wb_control_word_width-1:0] wb_control;
input wire clock;
output wire [31:0] alu_result_out, base_reg_content_out, mem_data_write_out;
output wire [3:0] wb_address_out, base_register_address_out;
output wire [mem_control_word_width-1:0] mem_control_out;
output wire [wb_control_word_width-1:0] wb_control_out;
reg [31:0] alu_result_reg, base_reg_content_reg, mem_data_write_reg;
reg [3:0] wb_address_reg, base_register_address_reg;
reg [mem_control_word_width-1:0] mem_control_reg;
reg [ wb_control_word_width-1:0] wb_control_reg;
initial begin
alu_result_reg = 32'h0;
base_reg_content_reg = 32'h0;
mem_data_write_reg = 32'h0;
wb_address_reg = 4'b0;
base_register_address_reg = 4'b0;
mem_control_reg = 0;
wb_control_reg = 0;
end
assign alu_result_out = alu_result_reg,
base_reg_content_out = base_reg_content_reg,
mem_data_write_out = mem_data_write_reg,
wb_address_out = wb_address_reg,
base_register_address_out = base_register_address_reg,
mem_control_out = mem_control_reg,
wb_control_out = wb_control_reg;
always @(posedge clock) begin
alu_result_reg <= alu_result;
base_reg_content_reg <= base_reg_content_load_post;
mem_data_write_reg <= mem_data_write;
wb_address_reg <= wb_address;
base_register_address_reg <= base_register_address;
mem_control_reg <= mem_control;
wb_control_reg <= wb_control;
end
endmodule
| 7.626534 |
module ALU (
input wire [31:0] A,
B, // Entradas A e B da ALU, sendo A o primeiro operando e B o segundo
input wire [2:0] func, // Entrada seletora de func proveniente da C.U.
input wire sub_sra, // Entrada que ativa / desativa subtração e shift aritmético
output reg [31:0] alu_val, // Saída, que é selecionada pela entrada func
output wire EQ,
LU,
LS // Saídas de comparador, são sempre expostas para a C.U.
);
wire [31:0] ADD, bXOR, bAND, bOR, SR, SL; // Guardam valores de possíveis operações que podem ser selecionados pelo func
wire COUT; // Fio que contém o carry out da soma / subtração
Adder32b A0 (
.A(A),
.B(B),
.S(ADD),
.SUB(sub_sra),
.COUT(COUT)
); // Módulo de soma
And32b bAND0 (
.A (A),
.B (B),
.And(bAND)
); // Módulo and bitwise
Or32b bOR0 (
.A(A),
.B(B),
.O(bOR)
); // Módulo or bitwise
Xor32b bXOR0 (
.A (A),
.B (B),
.Xor(bXOR)
); // Módulo xor bitwise
LeftLShifter LeftS0 (
.A(A),
.B(B),
.S(SL)
); // Módulo barrel left shifter
RightShifter RightS0 (
.A(A),
.B(B),
.SRA(sub_sra),
.Shifted(SR)
); // Módulo barrel right shifter
Comparator C0 (
.A_S(A[31]),
.B_S(B[31]),
.S(ADD),
.COUT(COUT),
.EQ(EQ),
.LS(LS),
.LU(LU)
);
// módulo comparadores (só funciona quando sub_sra = 1)
// Bloco always para síntese de multiplexador para selecionar as saídas
always @(*) begin
// Case baseado nas instruções presentes na ISA, para poupar o máximo da C.U.
case (func)
3'b000: alu_val = ADD;
3'b001: alu_val = SL;
3'b010: alu_val = LS;
3'b011: alu_val = LU;
3'b100: alu_val = bXOR;
3'b101: alu_val = SR;
3'b110: alu_val = bOR;
3'b111: alu_val = bAND;
endcase
end
endmodule
| 7.960621 |
module alu_mov (
input wire [15:0] operand1,
output wire [15:0] dout
);
assign dout = operand1;
endmodule
| 8.146148 |
module alu_movn (
input wire [ 6:0] immediate_offset,
output wire [15:0] dout
);
assign dout = immediate_offset;
endmodule
| 7.755752 |
module ALU_mul #(
parameter DATA_WIDTH = 4
) (
input clk,
input enable,
output busy,
input [DATA_WIDTH - 1 : 0] operand1,
input [DATA_WIDTH - 1 : 0] operand2,
output [DATA_WIDTH - 1 : 0] result
);
// cnt: counter
reg [DATA_WIDTH - 1 : 0] cnt;
always @(posedge clk) begin
if (!enable) begin
cnt <= 0;
end else begin
if (cnt == operand2) begin
cnt <= 0;
end else begin
cnt <= cnt + 1'b1;
end
end
end
// result
reg [DATA_WIDTH - 1 : 0] result_r;
assign result = result_r;
always @(posedge clk) begin
if (!enable) begin
result_r <= 0;
end else begin
if (cnt == operand2) begin
result_r <= 0;
end else begin
result_r <= result_r + operand1;
end
end
end
// busy
assign busy = enable & (cnt != operand2);
endmodule
| 8.229833 |
module alu_muldiv (
a_in,
b_in,
op_in,
clk,
a_reset_l,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
c_out,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out,
valid_out,
op_active
);
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input [op_wl -1:0] op_in;
output [data_wl-1:0] c_out;
input clk;
input a_reset_l;
input z_flag_in;
input s_flag_in;
input c_flag_in;
input ovr_flag_in;
output z_flag_out;
output s_flag_out;
output c_flag_out;
output ovr_flag_out;
output valid_out;
output op_active;
// arith ops
parameter I_MUL = 8'h02;
parameter I_SMUL = 8'h22;
parameter I_DIV = 8'h0F;
reg ld_mul, ld_div;
reg signd_int;
reg [data_wl-1:0] c_out_int;
reg valid_int;
reg z_flag_int, s_flag_int, ovr_flag_int;
wire z_flag_mul, s_flag_mul;
wire z_flag_div, ovr_flag_div;
wire [data_wl-1:0] c_out_div;
wire [data_wl-1:0] c_out_mul;
wire valid_div, valid_mul;
reg op_active_int;
assign c_flag_out = c_flag_in; // no change in this block
always @ ( op_in or z_flag_in or s_flag_in or ovr_flag_in or valid_mul or c_out_mul or z_flag_mul or s_flag_mul or
valid_div or ovr_flag_div or c_out_div or z_flag_div or s_flag_in)
begin
ld_mul = 1'b0;
ld_div = 1'b0;
signd_int = 1'b0;
valid_int = 1'b0;
c_out_int = 'b0;
z_flag_int = z_flag_in;
s_flag_int = s_flag_in;
ovr_flag_int = ovr_flag_in;
//valid_in = 1'b0;
op_active_int = 1'b0;
case (op_in)
I_MUL: begin
ld_mul = 1'b1;
signd_int = 1'b0;
valid_int = valid_mul;
c_out_int = c_out_mul;
z_flag_int = z_flag_mul;
s_flag_int = s_flag_mul;
op_active_int = 1'b1;
end
I_SMUL: begin
ld_mul = 1'b1;
signd_int = 1'b1;
valid_int = valid_mul;
c_out_int = c_out_mul;
z_flag_int = z_flag_mul;
s_flag_int = s_flag_mul;
op_active_int = 1'b1;
end
I_DIV: begin
ld_div = 1'b1;
ld_mul = 1'b0;
valid_int = valid_div;
c_out_int = c_out_div;
z_flag_int = z_flag_div;
s_flag_int = s_flag_in;
ovr_flag_int = ovr_flag_div;
op_active_int = 1'b1;
end
default: begin
valid_int = 1'b0;
op_active_int = 1'b0;
end
endcase
end
alu_mul alu_mul_i (
.a_in(a_in),
.b_in(b_in),
.signd(signd_int),
.clk(clk),
.a_reset_l(a_reset_l),
.ld(ld_mul),
.p_out(c_out_mul),
.valid(valid_mul),
.z_flag(z_flag_mul),
.s_flag(s_flag_mul)
);
alu_div alu_div_i (
.a_in(a_in), // divided
.b_in(b_in), // divisor
.clk(clk),
.a_reset_l(a_reset_l),
.ld(ld_div),
.p_out(c_out_div),
.valid(valid_div),
.z_flag(z_flag_div),
.ovr_flag(ovr_flag_div)
);
assign c_out = c_out_int;
assign z_flag_out = z_flag_int;
assign s_flag_out = s_flag_int;
assign ovr_flag_out = ovr_flag_int;
assign valid_out = valid_int;
assign op_active = op_active_int;
endmodule
| 7.222296 |
module Divider (
clk,
rst_n,
start,
done,
dividend,
divisor,
quotient,
remainder
);
// dividend / divisor = quotient ... remainder
input clk;
input rst_n;
input start;
output done;
input [31:0] dividend;
input [31:0] divisor;
output [31:0] quotient;
output [31:0] remainder;
reg [1:0] state, state_next;
parameter S_IDLE = 2'd0;
parameter S_CALC = 2'd1;
reg [5:0] counter, counter_next;
reg done, done_next;
reg [31:0] quotient, quotient_next;
reg [31:0] remainder, remainder_next;
reg [63:0] data, data_next;
reg [31:0] diff;
wire [31:0] dividend_sign, divisor_sign;
wire dividend_neg, divisor_neg;
assign dividend_neg = dividend[31];
assign divisor_neg = divisor[31];
assign dividend_sign = dividend_neg ? (~dividend + 1'b1) : dividend;
assign divisor_sign = divisor_neg ? (~divisor + 1'b1) : divisor;
always @(*) begin
state_next = state;
done_next = 1'b0;
data_next = data;
remainder_next = (dividend_neg) ? (~data[63:32] + 1'b1) : data[63:32];
quotient_next = (dividend_neg != divisor_neg) ? (~data[31:0] + 1'b1) : data[31:0];
if (state == S_IDLE) begin
counter_next = 6'd0;
if (start) begin
data_next = {32'b0, dividend_sign};
state_next = S_CALC;
end
end else begin
counter_next = counter + 1;
if (counter == 6'd32) begin
data_next = data;
done_next = 1'b1;
state_next = S_IDLE;
end else begin
data_next = data << 1;
diff = data_next[63:32] - divisor_sign;
if (~diff[31]) data_next = {diff, data[30:0], 1'b1};
end
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
done <= 1'b0;
counter <= 6'b0;
quotient <= 32'b0;
remainder <= 32'b0;
data <= 64'b0;
state <= S_IDLE;
end else begin
done <= done_next;
counter <= counter_next;
quotient <= quotient_next;
remainder <= remainder_next;
data <= data_next;
state <= state_next;
end
end
endmodule
| 7.440694 |
module multiplier_ns_logic (
op_start,
op_clear,
cnt,
state,
next_state,
next_cnt
); //next state logic
input [1:0] state;
input op_start, op_clear;
input [5:0] cnt;
output reg [1:0] next_state;
output reg [5:0] next_cnt;
//state encoding
parameter IDLE = 2'b00;
parameter EXEC = 2'b01;
parameter DONE = 2'b10;
//when inputs changes
always @(state or op_clear or op_start or cnt) begin
case (state)
IDLE: begin //state == IDLE
if (op_clear == 1'b1) begin
next_state <= IDLE; //if op_clear == 1 -> IDLE
next_cnt <= 6'b0; //count = 0
end else if (op_start == 1'b0) begin //if op_start == 0 -> IDLE
next_state <= IDLE;
next_cnt <= 6'b0; //count = 0
end else if (op_start == 1'b1) begin //if op_start == 1 -> EXEC
next_state <= EXEC;
next_cnt <= cnt + 1'b1; //count++
end else begin //error handling
next_state <= 2'bx;
next_cnt <= 6'bx;
end
end
EXEC: begin //state == EXEC
if (op_clear == 1'b1) begin //op_clear == 1 -> IDLE
next_state <= IDLE;
next_cnt <= 6'b0; //count = 0
end else if (cnt === 6'b01_1111) begin //if count == 63 -> DONE
next_state <= DONE;
next_cnt <= cnt + 1'b1; //count ++
end else if (cnt !== 6'b01_1111) begin //if count < 63 -> EXEC
next_state <= EXEC;
next_cnt <= cnt + 1'b1; //count ++
end else begin
next_state <= 2'bx; //error handling
next_cnt <= 6'bx;
end
end
DONE: begin //state == DONE
if (op_clear == 1'b1) begin //if op_clear == 1 -> IDLE
next_state <= IDLE;
next_cnt <= 6'b0; //count = 0
end else if (op_clear == 1'b0) begin //else -> DONE
next_state <= DONE;
next_cnt <= cnt; //prev value
end else begin
next_state <= 2'bx; //error handling
next_cnt <= 6'bx;
end
end
default: begin
next_state <= 2'bx; //error handling
next_cnt <= 6'bx;
end
endcase
end
endmodule
| 6.96487 |
module multiplier_o_logic (
state,
result_in,
result_out,
op_done
); //output logic
input [1:0] state;
input [63:0] result_in;
output [63:0] result_out;
output reg op_done;
//encode state
parameter IDLE = 2'b00;
parameter EXEC = 2'b01;
parameter DONE = 2'b10;
always @(state) begin //when state, op_done changes
case (state)
IDLE: op_done <= 1'b0; //IDLE : 0
EXEC: op_done <= 1'b0; //EXEC : 0
DONE: op_done <= 1'b1; //DONE : 1
default op_done <= 1'bx; //error handling
endcase
end
assign result_out = result_in; //print result
endmodule
| 7.216559 |
module W0RM_ALU_Multiply #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
output wire [ 3:0] result_flags
);
localparam MSB = DATA_WIDTH - 1;
localparam ALU_OPCODE_MUL = 4'h5;
localparam ALU_FLAG_ZERO = 4'h0;
localparam ALU_FLAG_NEG = 4'h1;
localparam ALU_FLAG_OVER = 4'h2;
localparam ALU_FLAG_CARRY = 4'h3;
reg [DATA_WIDTH-1:0] result_r = 0, data_a_r = 0, data_b_r = 0;
reg flag_carry_r = 0, result_valid_r = 0;
wire [(2*DATA_WIDTH)-1:0] result_i;
wire result_valid_i;
assign result_flags[ALU_FLAG_ZERO] = result_r == 0;
assign result_flags[ALU_FLAG_NEG] = result_r[MSB];
assign result_flags[ALU_FLAG_OVER] = ((~result_r[MSB]) && data_a_r[MSB] && data_b_r[MSB]) ||
(result_r[MSB] && (~data_a_r[MSB]) && (~data_b_r[MSB]));
assign result_flags[ALU_FLAG_CARRY] = flag_carry_r; // Carry generated by IP core
assign result = result_r;
assign result_valid = result_valid_r;
always @(posedge clk) begin
if (result_valid_i) begin
flag_carry_r <= result_i[DATA_WIDTH];
result_r <= result_i[DATA_WIDTH-1:0];
end
if (data_valid) begin
data_a_r <= data_a;
data_b_r <= data_b;
end
result_valid_r <= result_valid_i;
end
W0RM_Static_Timer #(
.LOAD (0),
.LIMIT(14)
) valid_delay (
.clk(clk),
.start(data_valid),
.stop (result_valid_i)
);
W0RM_Int_Mul mul (
.clk(clk),
.a(data_a),
.b(data_b),
.p(result_i)
);
endmodule
| 6.502774 |
module alu_mult_altera (
clock,
dataa,
datab,
result
);
input clock;
input [31:0] dataa;
input [31:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
lpm_mult lpm_mult_component (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(sub_wire0),
.aclr(1'b0),
.clken(1'b1),
.sum(1'b0)
);
defparam lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9", lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED", lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 32, lpm_mult_component.lpm_widthb = 32,
lpm_mult_component.lpm_widthp = 64;
endmodule
| 6.607273 |
module ALU_Mul_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = (FLAGS_WIDTH - 1) + DATA_WIDTH;
reg clk = 0;
reg fs_go = 0;
reg fs_pause = 1;
reg first_run = 1;
wire fs_done;
wire valid;
wire [DATA_WIDTH-1:0] data_a, data_b;
wire [ 3:0] opcode;
wire result_valid;
wire [ DATA_WIDTH-1:0] result;
wire [FLAGS_WIDTH-1:0] result_flags;
always #2.5 clk <= ~clk;
initial #50 fs_pause <= 1'b0;
always @(posedge clk) begin
if (fs_pause) begin
fs_go <= 0;
end else begin
if (first_run) begin
if (fs_go) begin
fs_go <= 0;
first_run <= 0;
end else begin
fs_go <= 1;
end
end else begin
fs_go <= result_valid;
end
end
end
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk (clk),
.ready(fs_go),
.valid(valid),
.empty(fs_done),
.data ({data_valid, opcode, data_a, data_b})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(result_valid),
.data ({result_flags[2:0], result}),
.done (done),
.error(error)
);
W0RM_ALU_Multiply #(
.SINGLE_CYCLE(0),
.DATA_WIDTH (DATA_WIDTH)
) dut (
.clk(clk),
.data_valid(valid & data_valid),
.opcode(opcode),
.data_a(data_a),
.data_b(data_b),
.result(result),
.result_valid(result_valid),
.result_flags(result_flags)
);
endmodule
| 7.074993 |
module alu_mul_div (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input i_clk,
input i_rst,
input [`RW-1:0] i_a,
i_b,
output [`RW-1:0] o_d,
input i_mul,
input i_div,
input i_mod,
input i_submit,
input i_flush,
output o_busy
);
`define RWLOG 4
reg [`RWLOG-1:0] cbit;
reg comp;
always @(posedge i_clk) begin
if (i_rst | i_flush) begin
comp <= 1'b0;
end else if (i_submit) begin
cbit <= (i_mul ? `RWLOG'b1 : `RWLOG'b0);
comp <= 1'b1;
end else if (comp) begin
cbit <= cbit + 1'b1;
if (cbit == `RWLOG'd15) begin
comp <= 1'b0;
end
end
end
reg [`RW-1:0] mul_res;
always @(posedge i_clk) begin
if (i_submit & i_mul) begin
mul_res <= (i_b[0] ? i_a : `RW'b0);
end else if (comp & i_b[cbit] & i_mul) begin
mul_res <= mul_res + (i_a << cbit);
end
end
reg [`RW-1:0] div_res, div_cur;
wire [`RW-1:0] div_diff = div_cur - i_b;
always @(posedge i_clk) begin
if (i_submit & (i_div | i_mod)) begin
div_res <= `RW'b0;
div_cur <= {{`RW - 1{1'b0}}, i_a[`RW-1]};
end else if (comp & (i_div | i_mod)) begin
if (div_cur >= i_b) begin
div_res[`RW-cbit-1] <= 1'b1;
if (cbit != `RWLOG'd15) div_cur <= {div_diff[14:0], i_a[`RW-cbit-2]};
else div_cur <= div_diff;
end else begin
if (cbit != `RWLOG'd15) div_cur <= {div_cur[14:0], i_a[`RW-cbit-2]};
end
end
end
assign o_d = (i_mod ? div_cur : (i_div ? div_res : mul_res));
assign o_busy = (i_submit | comp);
endmodule
| 6.725414 |
module alu_mux (
input [3:0] alu_op,
input [31:0] mux_i_0,
input [31:0] mux_i_1,
input [31:0] mux_i_2,
input [31:0] mux_i_3,
output reg [31:0] mux_o
);
always @(*) begin
case (alu_op)
`ADD: mux_o = mux_i_0;
`SUB: mux_o = mux_i_0;
`AND: mux_o = mux_i_1;
`OR: mux_o = mux_i_1;
`XOR: mux_o = mux_i_1;
`SLL: mux_o = mux_i_2;
`SRL: mux_o = mux_i_2;
`SRA: mux_o = mux_i_2;
`SEL_B: mux_o = mux_i_3;
default: mux_o = 32'b0;
endcase
end
endmodule
| 7.302804 |
module alu_nor (
A,
B,
Z
);
// parameter definitions
parameter WIDTH = 32;
//port definitions
input wire [WIDTH-1:0] A, B;
output wire [WIDTH-1:0] Z;
// instantiate module's hardware
assign Z = ~(A | B);
endmodule
| 8.617848 |
module adding_one (
a,
s,
cin,
cout
); // adding one to first number (a) n bits if selection inputs are s0=0,s1=0,s2=0 ( 0 0 0 )
parameter N = `NUM_BITS - 1;
input [N:0] a;
input cin;
output cout;
output [N+1:0] s; ///////////////////////////////////////////////////
wire [N:0] b = 8'b00000001; // WE CHANGE b ACCORDING TO NUMBER OF BITS ( N ) //
wire [N:0] carry; ///////////////////////////////////////////////////
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
if (i == 0)
full_adder fa1 (
a[i],
b[i],
cin,
s[i],
carry[i]
);
else
full_adder fa2 (
a[i],
b[i],
carry[i-1],
s[i],
carry[i]
);
end
endgenerate
full_adder fa3 (
1'b0,
1'b0,
carry[N],
s[N+1],
cout
);
endmodule
| 6.515227 |
module arithmetic_shift_right (
A,
C
); // arithmetic shift right for first number (a) n bits if selection inputs are s0=0,s1=0,s2=1 ( 0 0 1 )
parameter N = `NUM_BITS - 1;
input [N:0] A;
output [N+1:0] C;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
if (i == N) buf b1 (C[i], 1'b0);
else buf b2 (C[i], A[i+1]);
end
endgenerate
buf b2 (C[N+1], 1'b0);
endmodule
| 7.423881 |
module AND (
a,
b,
c
); // AND operation of 2 Numbers A and B if selection inputs are s0=1,s1=0,s2=1 ( 1 0 1 )
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
output [N+1:0] c;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
and (c[i], a[i], b[i]);
end
endgenerate
endmodule
| 7.053445 |
module OR (
a,
b,
c
); // OR operation of 2 Numbers A and B if selection inputs are s0=1,s1=1,s2=0 ( 1 1 0 )
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
output [N+1:0] c;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
or (c[i], a[i], b[i]);
end
endgenerate
endmodule
| 7.086775 |
module XOR (
a,
b,
c
); // XOR operation of 2 Numbers A and B if selection inputs are s0=1,s1=1,s2=1 ( 1 1 1 )
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
output [N+1:0] c;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
xor (c[i], a[i], b[i]);
end
endgenerate
endmodule
| 7.915029 |
module mux_8to_1 (
out,
i0,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
s0,
s1,
s2
); // 8:1 multiplexer
input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
output out;
wire w1, w2, w3, w4, w5, w6, w7, w8, s00, s01, s02;
not (s00, s0);
not (s01, s1);
not (s02, s2);
and (w1, i0, s00, s01, s02);
and (w2, i1, s00, s01, s2);
and (w3, i2, s00, s1, s02);
and (w4, i3, s00, s1, s2);
and (w5, i4, s0, s01, s02);
and (w6, i5, s0, s01, s2);
and (w7, i6, s0, s1, s02);
and (w8, i7, s0, s1, s2);
or (out, w1, w2, w3, w4, w5, w6, w7, w8);
endmodule
| 7.202391 |
module ALU (
a,
b,
outp,
s0,
s1,
s2
);
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
input s0, s1, s2;
output cout;
wire [N+1:0] c1, c2, c3, c4, c5, c6, c7, c8;
output [N+1:0] outp;
adding_one fa0 (
a,
c1,
1'b0,
cout
); // carry = 0
arithmetic_shift_right fa1 (
a,
c2
);
full_adder_test fa2 (
a,
b,
c3,
1'b0,
cout
); // carry = 0
substract_test fa3 (
a,
b,
c4
);
substract_one fa4 (
a,
c5
);
AND fa5 (
a,
b,
c6
);
OR fa6 (
a,
b,
c7
);
XOR fa7 (
a,
b,
c8
);
generate
genvar i;
for (i = 0; i <= N + 1; i = i + 1) begin
mux_8to_1 mux_obj (
outp[i],
c1[N+1-i],
c2[N+1-i],
c3[N+1-i],
c4[N+1-i],
c5[N+1-i],
c6[N+1-i],
c7[N+1-i],
c8[N+1-i],
s0,
s1,
s2
);
end
endgenerate
endmodule
| 7.650109 |
module alu_operand_decode (
instr,
rsVal,
rtVal,
opA,
opB
);
input [15:0] instr;
input [15:0] rsVal;
input [15:0] rtVal;
output [15:0] opA;
output [15:0] opB;
// wires and regs
reg [15:0] opBVal;
wire [ 6:0] op;
// assigns
assign opA = rsVal;
assign opB = opBVal;
assign op = {instr[15:11], instr[1:0]};
always @(*) begin
casex (op)
7'b1101100 : // ADD
opBVal = rtVal;
7'b1101101 : // SUB
opBVal = rtVal;
7'b1101110 : // OR
opBVal = rtVal;
7'b1101111 : // AND
opBVal = rtVal;
7'b1101000 : // ROL
opBVal = rtVal;
7'b1101001 : // SLL
opBVal = rtVal;
7'b1101010 : // ROR
opBVal = rtVal;
7'b1101011 : // SRA
opBVal = rtVal;
7'b00000xx : // HALT
opBVal = 16'b0; // TODO what val?
7'b00001xx : // NOP;
opBVal = 16'b0; // TODO what val?
7'b01000xx : // ADDI
opBVal = {{11{instr[4]}}, instr[4:0]}; // sign extended immediate
7'b01001xx : // SUBI
opBVal = {{11{instr[4]}}, instr[4:0]}; // sign extended immediate
7'b01010xx : // ORI
opBVal = {11'b0, instr[4:0]}; // zero-extended immediate
7'b01011xx : // ANDI
opBVal = {11'b0, instr[4:0]}; // zero-extended immediate
7'b10100xx : // ROLI
opBVal = {11'b0, instr[4:0]}; // zero-extended immediate
7'b10101xx : // SLLI
opBVal = {11'b0, instr[4:0]}; // zero-extended immediate
7'b10110xx : // RORI
opBVal = {11'b0, instr[4:0]}; // zero-extended immediate
7'b10111xx : // SRAI
opBVal = {11'b0, instr[4:0]}; // zero-extended immediate
7'b10000xx : // ST
opBVal = {{11{instr[4]}}, instr[4:0]}; // sign extended immediate
7'b10001xx : // LD
opBVal = {{11{instr[4]}}, instr[4:0]}; // sign extended immediate
7'b10011xx : // STU
opBVal = {{11{instr[4]}}, instr[4:0]}; // sign extended immediate
7'b11001xx : // BTR
opBVal = 16'b1; // don't care what opB is
7'b11100xx : // SEQ
opBVal = rtVal;
7'b11101xx : // SLT
opBVal = rtVal;
7'b11110xx : // SLE
opBVal = rtVal;
7'b11111xx : // SCO
opBVal = rtVal;
7'b01100xx : // BEQZ
opBVal = {{8{instr[7]}}, instr[7:0]}; // sign extended immediate
7'b01101xx : // BNEZ
opBVal = {{8{instr[7]}}, instr[7:0]}; // sign extended immediate
7'b01111xx : // BLTZ
opBVal = {{8{instr[7]}}, instr[7:0]}; // sign extended immediate
7'b11000xx : // LBI
opBVal = {{8{instr[7]}}, instr[7:0]}; // sign extended immediate
7'b10010xx : // SLBI
opBVal = {8'b0, instr[7:0]}; // zero extended immediate
7'b00100xx : // JINST
opBVal = {{5{instr[10]}}, instr[10:0]}; // sign extended displacement
7'b00101xx : // JR
opBVal = {{8{instr[7]}}, instr[7:0]}; // sign extended immediate
7'b00110xx : // JAL
opBVal = {{5{instr[10]}}, instr [10:0]}; // sign extended displacement
7'b00111xx : // JALR
opBVal = {{8{instr[7]}}, instr[7:0]}; // sign extended immediate
7'b01110xx : // RET
opBVal = rtVal;
7'b00010xx : // SIIC
opBVal = 16'b0; // Don't care
7'b00011xx : // RTI
opBVal = 16'b0; // Don't care
default : opBVal = 16'b1;
endcase
end
endmodule
| 6.909198 |
module A_NOP (
A,
B,
Y2,
Y1
); //no opertaion
input [31:0] A, B;
output [31:0] Y2, Y1;
assign Y1 = 32'h0000_0000;
assign Y2 = 32'h0000_0000; //sign extension
endmodule
| 7.456359 |
module A_NOTA (
A,
B,
Y2,
Y1
); //NOT A
input [31:0] A, B;
output [31:0] Y2;
output [31:0] Y1;
assign Y1 = ~A;
assign Y2[7:0] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[15:8] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[23:16] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[31:24] = {
Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]
}; //sign extension
endmodule
| 7.229655 |
module A_NOTB (
A,
B,
Y2,
Y1
); //NOT B
input [31:0] A, B;
output [31:0] Y2, Y1;
assign Y1 = ~B;
assign Y2[7:0] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[15:8] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[23:16] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[31:24] = {
Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]
}; //sign extension
endmodule
| 6.764727 |
module A_LSLA (
A,
B,
S,
Y2,
Y1
); //LSLA
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = A;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b01) //shift 1 bit
begin
Y1 = A;
//A[31] is meaningless in Y1
Y1[31:1] = A[30:0];
Y1[0] = 1'b0;
//A[31] is meaningful in Y2
Y2[0] = A[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b10) //shift 2 bit
begin
Y1 = A;
//A[31:30] is meaningless in Y1
Y1[31:2] = A[29:0];
Y1[1:0] = 2'b00;
//A[31:30] is meaningful in Y2
Y2[1:0] = Y1[31:30];
Y2[3:2] = {Y2[1], Y2[1]};
Y2[7:4] = {Y2[1], Y2[1], Y2[1], Y2[1]};
Y2[15:8] = {Y2[1], Y2[1], Y2[1], Y2[1], Y2[1], Y2[1], Y2[1], Y2[1]};
Y2[31:16] = {
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1]
};
//sign extension
end
else if(S == 2'b11) //shift 3 bit
begin
Y1 = A;
//A[31:29] is meaningless in Y1
Y1[31:3] = A[28:0];
Y1[2:0] = 3'b000;
//A[31:29] is meaningful in Y2
Y2[2:0] = Y1[31:29];
Y2[3] = {Y2[2]};
Y2[7:4] = {Y2[2], Y2[2], Y2[2], Y2[2]};
Y2[15:8] = {Y2[2], Y2[2], Y2[2], Y2[2], Y2[2], Y2[2], Y2[2], Y2[2]};
Y2[31:16] = {
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2]
};
//sign extension
end else //wrong shift
begin
Y1 = 32'hxxxx_xxxx;
Y2 = 32'hxxxx_xxxx;
end
end
endmodule
| 7.089916 |
module A_LSLB (
A,
B,
S,
Y2,
Y1
); //LSLB
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = B;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b01) //shift 1 bit
begin
Y1 = B;
//B[31] is meaningless in Y1
Y1[31:1] = B[30:0];
Y1[0] = 1'b0;
//B[31] is meaningful in Y2
Y2[0] = B[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b10) //shift 2 bit
begin
Y1 = B;
//B[31:30] is meaningless in Y1
Y1[31:2] = B[29:0];
Y1[1:0] = 2'b00;
//B[31:30] is meaningful in Y2
Y2[1:0] = Y1[31:30];
Y2[3:2] = {Y2[1], Y2[1]};
Y2[7:4] = {Y2[1], Y2[1], Y2[1], Y2[1]};
Y2[15:8] = {Y2[1], Y2[1], Y2[1], Y2[1], Y2[1], Y2[1], Y2[1], Y2[1]};
Y2[31:16] = {
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1],
Y2[1]
};
//sign extension
end
else if(S == 2'b11) //shift 3 bit
begin
Y1 = B;
//B[31:29] is meaningless in Y1
Y1[31:3] = B[28:0];
Y1[2:0] = 3'b000;
//B[31:29] is meaningful in Y2
Y2[2:0] = Y1[31:29];
Y2[3] = {Y2[2]};
Y2[7:4] = {Y2[2], Y2[2], Y2[2], Y2[2]};
Y2[15:8] = {Y2[2], Y2[2], Y2[2], Y2[2], Y2[2], Y2[2], Y2[2], Y2[2]};
Y2[31:16] = {
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2],
Y2[2]
};
//sign extension
end else //wrong shift
begin
Y1 = 32'hxxxx_xxxx;
Y2 = 32'hxxxx_xxxx;
end
end
endmodule
| 7.488285 |
module A_LSRA (
A,
B,
S,
Y2,
Y1
); //LSRA
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = A;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b01) //shift 1 bit
begin
Y1 = A;
//A[0] is meaningless
Y1[30:0] = A[31:1];
//Y1[31] = Y2[0]
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]};
Y2[31] = 1'b0;
//sign extension
end
else if(S == 2'b10) //shift 2 bit
begin
Y1 = A;
//A[1:0] is meaningless
Y1[29:0] = A[31:2];
Y1[30] = Y1[31];
//Y1[31] = Y2[0]
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]};
Y2[31:30] = 2'b00;
//sign extension
end
else if(S == 2'b11) //shift 3 bit
begin
Y1 = A;
//A[2:0] is meaningless
Y1[28:0] = A[31:3];
Y1[30:29] = {Y1[31], Y1[31]};
//Y1[31] = Y2[0]
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]};
Y2[31:29] = 3'b000;
//sign extension
end else //wrong shift
begin
Y1 = 32'hxxxx_xxxx;
Y2 = 32'hxxxx_xxxx;
end
end
endmodule
| 7.763736 |
module A_LSRB (
A,
B,
S,
Y2,
Y1
); //LSRB
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = B;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b01) //shift 1 bit
begin
Y1 = B;
//B[0] is meaningless
Y1[30:0] = B[31:1];
//Y1[31] = Y2[0]
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]};
Y2[31] = 1'b0;
//sign extension
end
else if(S == 2'b10) //shift 2 bit
begin
Y1 = B;
//B[1:0] is meaningless
Y1[29:0] = B[31:2];
Y1[30] = Y1[31];
//Y1[31] = Y2[0]
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]};
Y2[31:30] = 2'b00;
//sign extension
end
else if(S == 2'b11) //shift 3 bit
begin
Y1 = B;
//B[2:0] is meaningless
Y1[28:0] = B[31:3];
Y1[30:29] = {Y1[31], Y1[31]};
//Y1[31] = Y2[0]
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]};
Y2[31:29] = 3'b000;
//sign extension
end else //wrong shift
begin
Y1 = 32'hxxxx_xxxx;
Y2 = 32'hxxxx_xxxx;
end
end
endmodule
| 7.519697 |
module A_ASRA (
A,
B,
S,
Y2,
Y1
); //ASRA
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = A;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b01) //shift 1 bit
begin
Y1 = A;
//A[0] is meaningless
Y1[30:0] = A[31:1];
Y1[31] = A[31];
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b10) //shift 2 bit
begin
Y1 = A;
//A[1:0] is meaningless
Y1[29:0] = A[31:2];
Y1[31:30] = {A[31], A[31]};
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b11) //shift 3 bit
begin
Y1 = A;
//A[2:0] is meaningless
Y1[28:0] = A[31:3];
Y1[31:29] = {A[31], A[31], A[31]};
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end else //wrong shift
begin
Y1 = 32'hxxxx_xxxx;
Y2 = 32'hxxxx_xxxx;
end
end
endmodule
| 7.879591 |
module A_ASRB (
A,
B,
S,
Y2,
Y1
); //ASRB
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = B;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b01) //shift 1 bit
begin
Y1 = B;
//B[0] is meaningless
Y1[30:0] = B[31:1];
Y1[31] = B[31];
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b10) //shift 2 bit
begin
Y1 = B;
//B[1:0] is meaningless
Y1[29:0] = B[31:2];
Y1[31:30] = {B[31], B[31]};
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end
else if(S == 2'b11) //shift 3 bit
begin
Y1 = B;
//B[2:0] is meaningless
Y1[28:0] = B[31:3];
Y1[31:29] = {B[31], B[31], B[31]};
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] = {Y2[3:0], Y2[3:0]};
Y2[15:0] = {Y2[7:0], Y2[7:0]};
Y2[31:0] = {Y2[15:0], Y2[15:0]}; //sign extension
end else //wrong shift
begin
Y1 = 32'hxxxx_xxxx;
Y2 = 32'hxxxx_xxxx;
end
end
endmodule
| 7.812936 |
module alu_op_decode (
instr,
alu_op
);
input [15:0] instr;
output [4:0] alu_op;
parameter ADD = 0;
parameter SUB = 1;
parameter OR = 2;
parameter AND = 3;
parameter ROL = 4;
parameter SLL = 5;
parameter ROR = 6;
parameter SRA = 7;
parameter ST = 8;
parameter LD = 9;
parameter STU = 10;
parameter BTR = 11;
parameter SEQ = 12;
parameter SLT = 13;
parameter SLE = 14;
parameter SCO = 15;
parameter BEQZ = 16;
parameter BNEZ = 17;
parameter BLTZ = 18;
parameter LBI = 19;
parameter SLBI = 20;
parameter JINST = 21;
parameter JAL = 22;
parameter JR = 23;
parameter JALR = 24;
parameter RET = 25;
parameter SIIC = 26;
parameter RTI = 27;
parameter NOP = 28;
parameter HALT = 29;
// wires and reg vars
reg [4:0] op;
wire [6:0] instr_op;
// assigns
assign instr_op = {instr[15:11], instr[1:0]};
assign alu_op = op;
// case statement/decode logic
always @(*) begin
casex (instr_op)
7'b1101100 : op = ADD;
7'b1101101 : op = SUB;
7'b1101110 : op = OR;
7'b1101111 : op = AND;
7'b1101000 : op = ROL;
7'b1101001 : op = SLL;
7'b1101010 : op = ROR;
7'b1101011 : op = SRA;
7'b00000xx : op = HALT;
7'b00001xx : op = NOP;
7'b01000xx : op = ADD;
7'b01001xx : op = SUB;
7'b01010xx : op = OR;
7'b01011xx : op = AND;
7'b10100xx : op = ROL;
7'b10101xx : op = SLL;
7'b10110xx : op = ROR;
7'b10111xx : op = SRA;
7'b10000xx : op = ST;
7'b10001xx : op = LD;
7'b10011xx : op = STU;
7'b11001xx : op = BTR;
7'b11100xx : op = SEQ;
7'b11101xx : op = SLT;
7'b11110xx : op = SLE;
7'b11111xx : op = SCO;
7'b01100xx : op = BEQZ;
7'b01101xx : op = BNEZ;
7'b01111xx : op = BLTZ;
7'b11000xx : op = LBI;
7'b10010xx : op = SLBI;
7'b00100xx : op = JINST;
7'b00101xx : op = JR;
7'b00110xx : op = JAL;
7'b00111xx : op = JALR;
7'b01110xx : op = RET;
7'b00010xx : op = SIIC;
7'b00011xx : op = RTI;
default : op = 5'b11111;
endcase
end
endmodule
| 6.816088 |
module alu_or (
A,
B,
Z
);
parameter WIDTH = 32;
//port definitions
input wire [(WIDTH - 1):0] A, B;
output wire [(WIDTH - 1):0] Z;
assign Z = A | B;
endmodule
| 8.948799 |
module alu_orr (
input [15:0] operand1,
input [15:0] operand2,
output [15:0] dout
);
assign dout = operand1 | operand2;
endmodule
| 7.889208 |
module OrModule (
bigMuxIn4,
inA,
inB
);
output [7:0] bigMuxIn4;
input [7:0] inA;
input [7:0] inB;
or (bigMuxIn4[0], inA[0], inB[0]);
or (bigMuxIn4[1], inA[1], inB[1]);
or (bigMuxIn4[2], inA[2], inB[2]);
or (bigMuxIn4[3], inA[3], inB[3]);
or (bigMuxIn4[4], inA[4], inB[4]);
or (bigMuxIn4[5], inA[5], inB[5]);
or (bigMuxIn4[6], inA[6], inB[6]);
or (bigMuxIn4[7], inA[7], inB[7]);
or (bigMuxIn4[8], inA[8], inB[8]);
or (bigMuxIn4[9], inA[9], inB[9]);
or (bigMuxIn4[10], inA[10], inB[10]);
or (bigMuxIn4[11], inA[11], inB[11]);
or (bigMuxIn4[12], inA[12], inB[12]);
or (bigMuxIn4[13], inA[13], inB[13]);
or (bigMuxIn4[14], inA[14], inB[14]);
or (bigMuxIn4[15], inA[15], inB[15]);
endmodule
| 7.948939 |
module ALU_output (
input [31:0] input_data,
input clk,
output reg [31:0] output_data
);
always @(negedge clk) begin
output_data = input_data;
end
endmodule
| 7.397489 |
module alu_output_stage (
out_data1,
out_data2,
out_data3,
out_data4,
out_resp1,
out_resp2,
out_resp3,
out_resp4,
c_clk,
alu_overflow,
alu_result,
local_error_found,
prio_alu_out_req_id,
prio_alu_out_vld,
reset
);
output [0:31] out_data1, out_data2, out_data3, out_data4;
output [0:1] out_resp1, out_resp2, out_resp3, out_resp4;
input [0:63] alu_result;
input [0:1] prio_alu_out_req_id;
input [1:7] reset;
input c_clk, alu_overflow, local_error_found, prio_alu_out_vld;
wire [0:31] hold_data;
wire [0:1] hold_resp, hold_id;
assign hold_id[0:1] = prio_alu_out_req_id[0:1];
assign hold_resp[0:1] =
(~prio_alu_out_vld) ? 2'b00 :
(~local_error_found) ? 2'b01 :
(alu_result[31]) ? 2'b10 :
2'b01;
assign hold_data[0:31] = (prio_alu_out_vld) ? alu_result[32:63] : 32'b0;
assign out_resp1[0:1] = (hold_id[0:1] == 2'b00) ? hold_resp[0:1] : 2'b00;
assign out_resp2[0:1] = (hold_id[0:1] == 2'b01) ? hold_resp[0:1] : 2'b00;
assign out_resp3[0:1] = (hold_id[0:1] == 2'b10) ? hold_resp[0:1] : 2'b00;
assign out_resp4[0:1] = (hold_id[0:1] == 2'b11) ? hold_resp[0:1] : 2'b00;
assign out_data1[0:31] = (hold_id[0:1] == 2'b00) ? hold_data[0:31] : 32'b0;
assign out_data2[0:31] = (hold_id[0:1] == 2'b01) ? hold_data[0:31] : 32'b0;
assign out_data3[0:31] = (hold_id[0:1] == 2'b10) ? hold_data[0:31] : 32'b0;
assign out_data4[0:31] = (hold_id[0:1] == 2'b11) ? hold_data[0:31] : 32'b0;
endmodule
| 6.877864 |
module ALU_OUT_EX_MEM (
input [31:0] data_from_ALU,
input clock,
output reg [31:0] data_for_Mem_stage
);
always @(posedge clock) begin
data_for_Mem_stage = data_from_ALU;
end
endmodule
| 7.297428 |
module ALU_Out_Reg (
ALUResult,
Clk,
Reset,
Result
);
input [31:0] ALUResult;
input Clk, Reset;
output reg [31:0] Result;
always @(posedge Clk) begin
if (Reset) Result <= 32'b0;
else Result <= ALUResult;
end
endmodule
| 6.710175 |
module D_ff (
input clk,
input reset,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.58165 |
module decoder3to8 (
input [2:0] destReg,
output reg [7:0] decOut
);
always @(destReg) begin
case (destReg)
3'b000: decOut = 8'b00000001;
3'b001: decOut = 8'b00000010;
3'b010: decOut = 8'b00000100;
3'b011: decOut = 8'b00001000;
3'b100: decOut = 8'b00010000;
3'b101: decOut = 8'b00100000;
3'b110: decOut = 8'b01000000;
3'b111: decOut = 8'b10000000;
endcase
end
endmodule
| 8.532605 |
module mux8to1 (
input [15:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
input [2:0] Sel,
output reg [15:0] outBus
);
always @(outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or Sel) begin
case (Sel)
3'b000: outBus = outR0;
3'b001: outBus = outR1;
3'b010: outBus = outR2;
3'b011: outBus = outR3;
3'b100: outBus = outR4;
3'b101: outBus = outR5;
3'b110: outBus = outR6;
3'b111: outBus = outR7;
endcase
end
endmodule
| 7.465042 |
module registerFile (
input clk,
input reset,
input regWrite,
input regWriteDoosra,
input [2:0] srcRegA
, input [2:0] srcRegB,
input [2:0] srcRegC,
input [2:0] srcRegD,
input [2:0] destReg,
input [2:0] destRegDoosra,
input [15:0] writeData,
input [15:0] writeDataDoosra,
output [15:0] outBusA,
output [15:0] outBusB,
output [15:0] outBusC,
output [15:0] outBusD
);
wire [7:0] decOut, decOutDoosra;
wire [15:0] outR0, outR1, outR2, outR3, outR4, outR5, outR6, outR7;
decoder3to8 d0 (
destReg,
decOut
);
decoder3to8 d1 (
destRegDoosra,
decOutDoosra
);
registerSet rSet0 (
clk,
reset,
regWrite,
regWriteDoosra,
decOut,
decOutDoosra,
writeData,
writeDataDoosra,
outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7
);
mux8to1 m1 (
outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
srcRegA,
outBusA
);
mux8to1 m2 (
outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
srcRegB,
outBusB
);
mux8to1 m3 (
outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
srcRegC,
outBusC
);
mux8to1 m4 (
outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
srcRegD,
outBusD
);
endmodule
| 6.674499 |
module D_ff_Mem (
input clk,
input reset,
input regWrite,
input decOut1b,
input init,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1) q = init;
else if (regWrite == 1 && decOut1b == 1) begin
q = d;
end
end
endmodule
| 6.84774 |
module decoder4to16 (
input [3:0] destReg,
output reg [15:0] decOut
);
always @(destReg)
case (destReg)
4'b0000: decOut = 16'b0000000000000001;
4'b0001: decOut = 16'b0000000000000010;
4'b0010: decOut = 16'b0000000000000100;
4'b0011: decOut = 16'b0000000000001000;
4'b0100: decOut = 16'b0000000000010000;
4'b0101: decOut = 16'b0000000000100000;
4'b0110: decOut = 16'b0000000001000000;
4'b0111: decOut = 16'b0000000010000000;
4'b1000: decOut = 16'b0000000100000000;
4'b1001: decOut = 16'b0000001000000000;
4'b1010: decOut = 16'b0000010000000000;
4'b1011: decOut = 16'b0000100000000000;
4'b1100: decOut = 16'b0001000000000000;
4'b1101: decOut = 16'b0010000000000000;
4'b1110: decOut = 16'b0100000000000000;
4'b1111: decOut = 16'b1000000000000000;
endcase
endmodule
| 8.126959 |
module mux16to1 (
input [15:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [15:0] outBus
);
always@(outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel)
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
endmodule
| 7.318793 |
module mux16to1_8 (
input [7:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [7:0] outBus
);
always@(outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel)
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
endmodule
| 7.319464 |
module pcAdder (
input [15:0] pc,
output reg [15:0] newPC
);
always @(pc) begin
newPC = pc + 4;
end
endmodule
| 7.400415 |
module adderModule (
input [15:0] inp1,
input [15:0] inp2,
output reg [15:0] adderKaResult
);
always @(inp1, inp2) begin
adderKaResult = inp1 + inp2;
end
endmodule
| 6.960076 |
module IF_ID (
input clk,
input reset,
input regWrite,
input decOut1b,
input [31:0] instr,
input [15:0] PC,
output [15:0] p0_intr,
output [15:0] p0_intr2,
output [15:0] PCOut
);
register16bit PC_reg (
clk,
reset,
regWrite,
decOut1b,
PC,
PCOut
);
register16bit instr_fetch_reg (
clk,
reset,
regWrite,
decOut1b,
instr[15:0],
p0_intr
);
register16bit instr_fetch_reg_2 (
clk,
reset,
regWrite,
decOut1b,
instr[31:16],
p0_intr2
);
endmodule
| 7.719833 |
module ID_EX (
input clk,
input reset,
input regWrite,
input decOut1b,
input [15:0] insFetchOutput,
input [15:0] regOut1,
input [15:0] regOut2,
input [15:0] sExtOut,
input [2:0] ctr_Rd,
input [1:0] ctr_aluSrcA,
input ctr_aluSrcB,
input [1:0] ctr_aluOp,
input ctr_regWrite,
input [15:0] PC,
input [15:0] regOut3,
input [15:0] regOut4,
input [15:0] sExtOutNeecheWaala,
input [2:0] RdNeecheWaala,
input regWriteNeeche,
output [15:0] p1_regOut1,
output [15:0] p1_regOut2,
output [15:0] p1_sExtOut,
output [2:0] p1_Rd,
output [1:0] p1_aluSrcA,
output p1_aluSrcB,
output [1:0] p1_aluOp,
output p1_regWrite,
output [15:0] p1_PC,
output [15:0] p1_regOut3,
output [15:0] p1_regOut4,
output [15:0] p1_sExtOutNeecheWaala,
output [2:0] p1_RdNeecheWaala,
output p1_regWriteNeeche,
output [15:0] p1_insFetchOutput
);
register16bit regout1_reg (
clk,
reset,
regWrite,
decOut1b,
regOut1,
p1_regOut1
);
register16bit regout2_reg (
clk,
reset,
regWrite,
decOut1b,
regOut2,
p1_regOut2
);
register16bit sext_reg (
clk,
reset,
regWrite,
decOut1b,
sExtOut,
p1_sExtOut
);
register16bit fetchOut_reg (
clk,
reset,
regWrite,
decOut1b,
insFetchOutput,
p1_insFetchOutput
);
register2bit aluSrcA_reg (
clk,
reset,
regWrite,
decOut1b,
ctr_aluSrcA,
p1_aluSrcA
);
register3bit Rd_reg (
clk,
reset,
regWrite,
decOut1b,
ctr_Rd,
p1_Rd
);
register1bit aluSrcB_reg (
clk,
reset,
regWrite,
decOut1b,
ctr_aluSrcB,
p1_aluSrcB
);
register2bit aluop_reg (
clk,
reset,
regWrite,
decOut1b,
ctr_aluOp,
p1_aluOp
);
register1bit regwrite_reg (
clk,
reset,
regWrite,
decOut1b,
ctr_regWrite,
p1_regWrite
);
register16bit regout3_reg (
clk,
reset,
regWrite,
decOut1b,
regOut3,
p1_regOut3
);
register16bit regout4_reg (
clk,
reset,
regWrite,
decOut1b,
regOut4,
p1_regOut4
);
register16bit PC_reg (
clk,
reset,
regWrite,
decOut1b,
PC,
p1_PC
);
register16bit signExtNeeche_reg (
clk,
reset,
regWrite,
decOut1b,
sExtOutNeecheWaala,
p1_sExtOutNeecheWaala
);
register3bit Rd_regNeeche (
clk,
reset,
regWrite,
decOut1b,
RdNeecheWaala,
p1_RdNeecheWaala
);
register1bit regWriteNeeche_reg (
clk,
reset,
regWriteNeeche,
decOut1b,
regWriteNeeche,
p1_regWriteNeeche
);
endmodule
| 8.23208 |
module signExtModule (
input [4:0] offset5,
input [10:0] offset11,
input [7:0] offset8,
input [1:0] ctrSignExt,
output reg [15:0] signExtModuleOutput
);
always @(offset5, offset11, offset8, ctrSignExt) begin
if (ctrSignExt == 2'b00) signExtModuleOutput = {{11{offset5[4]}}, offset5[4:0]};
else if (ctrSignExt == 2'b01) signExtModuleOutput = {{5{offset11[10]}}, offset11[10:0]};
else if (ctrSignExt == 2'b10) signExtModuleOutput = {{8{offset8[7]}}, offset8[7:0]};
end
endmodule
| 7.391111 |
module ALU (
input [15:0] AluIn1,
input [15:0] AluIn2,
input [1:0] AluOp,
output reg [15:0] AluOut,
output reg [3:0] flag
);
always @(AluIn1, AluIn2, AluOp) begin
if (AluOp == 2'b10) AluOut = AluIn1 + AluIn2;
else if (AluOp == 2'b11) AluOut = AluIn1 - AluIn2;
else if (AluOp == 2'b01) AluOut = AluIn1 & AluIn2;
if (AluOut == 0) flag[2] = 1;
else flag[2] = 0;
end
endmodule
| 7.960621 |
module adderforbranch (
input [15:0] PC,
input [15:0] shiftedvalue,
input opcodebit,
input zeroflag,
output reg [15:0] BranchAddress
);
always @(PC, shiftedvalue, opcodebit, zeroflag) begin
if (zeroflag == 1 && opcodebit == 1) BranchAddress = PC + shiftedvalue;
else if (zeroflag == 0 && opcodebit == 0) BranchAddress = PC + shiftedvalue;
else BranchAddress = PC + 4;
end
endmodule
| 7.472959 |
module signExt (
input [2:0] immShort,
input [7:0] immLong,
input immSrc,
output reg [15:0] sextOutput
);
always @(immShort, immLong, immSrc) begin
if (immSrc == 1'b0) sextOutput = {{13{immShort[2]}}, immShort[2:0]};
else sextOutput = {{8{immLong[7]}}, immLong[7:0]};
end
endmodule
| 7.404229 |
module mux2to1 (
input [2:0] inp1,
input [2:0] inp2,
input sel,
output reg [2:0] muxOut
);
always @(inp1, inp2, sel) begin
if (sel == 1'b0) muxOut = inp1;
else muxOut = inp2;
end
endmodule
| 7.107199 |
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