code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module alu_i (
input [31:0] A,
input [31:0] B,
input [ 3:0] Code,
input Sel,
output reg [31:0] C,
output Less,
output Equal,
output Greater
);
//Codes (see defines.v) : Add=0 Shift_l=1 Shift_r=2 XOR=3 OR=4 AND=5 Comp=6 nop=7
//Sel : 0=signed 1=unsigned/subtraction
//Adder... | 6.657808 |
module fulladder (
input x,
input y,
input cin,
output wire c_out,
output wire sum_out
);
wire carry1;
wire carry2;
wire sum1;
assign c_out = carry1 | carry2;
adder a1 (
.a(x),
.b(y),
.sum(sum1),
.cout(carry1)
);
adder a2 (
.a(sum1),
.b(cin),
.... | 7.454465 |
module ripple (
input [1:0] p,
input [1:0] q,
input c_in,
output [3:0] sum_out
);
wire take1;
assign sum_out[3] = 0;
fulladder f1 (
.x(p[0]),
.y(q[0]),
.cin(c_in),
.c_out(take1),
.sum_out(sum_out[0])
);
fulladder f2 (
.x(p[1]),
.y(q[1]),
.cin(tak... | 6.679037 |
module alu (
data1,
data2,
contr_in,
out,
zero_flag
);
input [31:0] data1;
input [31:0] data2;
input [3:0] contr_in;
output reg [31:0] out;
output reg zero_flag;
always @(data1 or data2 or contr_in) begin
case (contr_in)
4'b0010: begin
out = data1 + data2;
end
... | 6.813467 |
module alu_input_stage (
alu_data1,
alu_data2,
hold1_data1,
hold1_data2,
hold2_data1,
hold2_data2,
hold3_data1,
hold3_data2,
hold4_data1,
hold4_data2,
prio_alu_in_cmd,
prio_alu_in_req_id
);
output [0:63] alu_data1, alu_data2;
wire [0:63] alu_data1, alu_data2;
inp... | 6.778653 |
module alu_shreg #(
parameter p = 3
) (
input wire clk,
input wire rst,
input wire [3:0] dm_re_i,
input wire [`REG_ADDR_WIDTH-1:0] rd_addr_i,
input wire regwrite_i,
input wire regwriteui_i,
input wire [1:0] regwritehilo_i,
input wire sr_i,
input wire branche... | 6.626683 |
module alu_internal (
A,
B,
Cin,
Op,
invA,
invB,
sign,
Out,
Ofl,
Z,
Cout,
neg
);
input [15:0] A;
input [15:0] B;
input Cin;
input [2:0] Op;
input invA;
input invB;
input sign;
output [15:0] Out;
output Ofl;
output Z;
output Cout; // carry out from ... | 7.218787 |
module Alu (
Z,
A,
B,
INST,
FLAGS,
FirstCyc,
CLOCK
);
input [31:0] A;
input [31:0] B;
input [3:0] INST;
input FirstCyc;
input CLOCK;
output reg [31:0] Z;
output [3:0] FLAGS;
//data
wire [31:0] adder_out;
wire adder_co;
reg [31:0] ain, bin;
wire cin;
wire not_A_add... | 7.167973 |
module alu_jump (
input wire [31:0] pc,
input wire [31:0] register,
input wire [25:0] target,
input wire [ 5:0] alu_opcode,
input wire nop,
input wire enable,
output reg [31:0] out_pc
// output reg [31:0] reg31
);
always @(*) begin
if (enable == 1) begin
if ... | 7.57796 |
module
*/
`include "adder_struct.v"
module Alu( Z, A, B, INST, SEL, EN );
////////
// IO //
////////
output [31:0] Z; // output data
input [31:0] A; // First Input Data, subtract is A-B
input [31:0] B; // Second Input Data, this is added to or subtracted from A
input [3:0] INST; // Instructions are... | 7.722981 |
module ALU_LEGv8 (
input [63:0] Ain,
Bin,
input carryIn,
input [4:0] ALUCtl,
output logic [63:0] ALUOut,
output logic [3:0] status
);
logic [63:0] A, B;
logic [64:0] sum;
always_comb begin
A = ALUCtl[1] ? ~Ain : Ain;
B = ALUCtl[0] ? ~Bin : Bin;
sum = A + B + carryIn;
c... | 7.309055 |
module alu (
A,
B,
cin,
select,
out,
status
);
input [63:0] A, B;
input cin;
input [4:0] select;
output [63:0] out;
output [3:0] status;
// SELECT CODES
// xxxx1 Invert A
// xxx1x Invert B
// 000xx A AND B
// 001xx A OR B
// 010xx A XOR B
// 011xx ADD A B
// 100xx A <<... | 7.41692 |
module inversion (
A,
B,
select,
AOut,
BOut
);
input [63:0] A, B;
input [1:0] select;
output [63:0] AOut, BOut;
assign AOut = select[0] ? ~A : A;
assign BOut = select[1] ? ~B : B;
endmodule
| 7.129544 |
module logicOut (
A,
B,
andAB,
orAB,
xorAB
);
input [63:0] A, B;
output [63:0] andAB, orAB, xorAB;
assign andAB = A & B;
assign orAB = A | B;
assign xorAB = A ^ B;
endmodule
| 6.873034 |
module shift (
A,
B,
left,
right
);
input [63:0] A, B;
output [63:0] left, right;
assign left = A << B[5:0];
assign right = A >> B[5:0];
endmodule
| 6.608895 |
module muxOut (
select,
out,
andAB,
orAB,
xorAB,
addAB,
shiftLA,
shiftRA
);
input [2:0] select;
output reg [63:0] out;
input [63:0] andAB, orAB, xorAB, addAB, shiftLA, shiftRA;
always @(*) begin
case (select)
3'b000: out <= andAB;
3'b001: out <= orAB;
3'b... | 8.714561 |
module ALU_LEGv8 (
A,
B,
FS,
C0,
F,
status
);
input [63:0] A, B;
input [4:0] FS;
// FS0 - b invert
// FS1 - a invert
// FS4:2 - op. select
// 000 - AND
// 001 - OR
// 010 - ADD
// 011 - XOR
// 100 - shift left
// 101 - shift right
// 110 - none / 0
// 11... | 7.309055 |
module Adder (
S,
Cout,
A,
B,
Cin
);
input [63:0] A, B;
input Cin;
output [63:0] S;
output Cout;
wire [64:0] carry;
assign carry[0] = Cin;
assign Cout = carry[64];
// use generate block to instantiate 64 full adders
genvar i;
generate
for (
i = 0; i < 64; i = i + 1
... | 8.145585 |
module FullAdder (
S,
Cout,
A,
B,
Cin
);
input A, B, Cin;
output S, Cout;
assign S = A ^ B ^ Cin;
assign Cout = A & B | A & Cin | B & Cin;
endmodule
| 7.610141 |
module ALU_LEGv8_Testbench ();
reg [63:0] A, B;
reg [4:0] FS;
reg C0;
wire [63:0] F;
wire [3:0] status;
ALU_LEGv8 dut (
A,
B,
FS,
C0,
F,
status
);
integer errors;
initial begin
errors <= 0;
FS <= 5'b00000; // A AND B
/*
A <= 64'b110;
B <= 64'b011... | 7.492239 |
module NOT (
input wire a,
output wire y
);
assign y = !a;
endmodule
| 7.525099 |
module NAND (
input wire a,
b,
output wire y
);
wire x;
AND p (
a,
b,
x
);
NOT q (
x,
y
);
endmodule
| 7.731629 |
module NOR (
input wire a,
b,
output wire y
);
wire x;
OR p (
a,
b,
x
);
NOT q (
x,
y
);
endmodule
| 7.366253 |
module two_to_one_mux (
input wire [1:0] i,
input wire s,
output wire y
);
assign y = s ? i[1] : i[0];
endmodule
| 7.326213 |
module four_to_one_mux (
input wire [3:0] i,
input wire [1:0] s,
output wire y
);
wire [1:0] r;
two_to_one_mux m1 (
i[1:0],
s[0],
r[0]
);
two_to_one_mux m2 (
i[3:2],
s[0],
r[1]
);
two_to_one_mux m3 (
r[1:0],
s[1],
y
);
endmodule
| 6.763352 |
module eight_to_one_mux (
input wire [7:0] i,
input wire [2:0] s,
output wire y
);
wire [1:0] x;
four_to_one_mux m1 (
i[3:0],
s[1:0],
x[0]
);
four_to_one_mux m2 (
i[7:4],
s[1:0],
x[1]
);
two_to_one_mux m3 (
x[1:0],
s[2],
y
);
endmodule
| 6.584362 |
module ALU_LL (
input [3:0] G_sel,
input [31:0] A,
input [31:0] B,
output reg [31:0] G,
output [3:0] ZCNVFlags
);
//reg carry_in;
wire carry_out;
wire [31:0] Arithmetic_result, Logical_result;
//TODO new adder topology needed
ripple_carry_adder_subtractor #(
.N(32)
) rcas (
... | 7.21199 |
module Rev 0.0 07/17/2011 **/
/** **/
/*******************************************************************************************/
module alu_log (logic_c, logic_hc, logic_out, alua_... | 8.238592 |
module W0RM_ALU_Logic #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
... | 7.236663 |
module ALU_logical (
A,
B,
C,
Y
);
input [3:0] A, B;
input [2:0] C;
output reg [6:0] Y;
wire [3:0] t_no_Cin;
wire [6:0] result0, result1, result2, result3, result4, result5, result6, result7;
assign result0[4:0] = A + B;
assign result0[5] = (A[3] == B[3]) && (A[3] != result0[3]); // over... | 6.657799 |
module alu_logic_arithmetic (
input [3:0] alu_op,
input [31:0] A,
input [31:0] B,
output reg [31:0] C
);
always @(*) begin
case (alu_op)
`AND: C = A & B;
`OR: C = A | B;
`XOR: C = A ^ B;
default: C = 32'b0;
endcase
end
endmodule
| 7.316552 |
module ALU_Logic_1_tb (
output wire done,
error
);
ALU_Logic_base_tb #(
.DATA_WIDTH (8),
.FILE_SOURCE ("../testbench/data/core/ALU_Logic_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_Logic_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.206317 |
module alu_logic_arithmetic (
input [3:0] alu_op,
input [31:0] A,
input [31:0] B,
output reg [31:0] C
);
always @(*) begin
case (alu_op)
`AND: C = A & B;
`OR: C = A | B;
`XOR: C = A ^ B;
default: C = 32'b0;
endcase
end
endmodule
| 7.316552 |
module ALU_Logic_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = ... | 7.424547 |
module alu_lsl (
input [15:0] operand1,
input [ 3:0] immediate_offset,
output [15:0] dout
);
assign dout = operand1 << immediate_offset;
endmodule
| 7.520451 |
module alu_lsr (
input [15:0] operand1,
input [ 3:0] immediate_offset,
output [15:0] dout
);
assign dout = operand1 >> immediate_offset;
endmodule
| 7.480446 |
module ALU_Main (
input clk,
input S,
input [31:0] B,
input [31:0] A,
input [3:0] ALU_op,
input Shift_carry_out,
input CF,
input VF,
output reg [31:0] F,
output reg [ 3:0] NZCV
);
reg Cout;
localparam FN = 3, FZ = 2, FC = 1, FV = 0;
always @(*) begin
case (ALU_op)... | 6.856935 |
module ALU_MD (
ALU_MD_ctrl,
A,
B,
ALU_MD_out
);
input [2:0] ALU_MD_ctrl; //3'b000 signed *
//3'b001 unsigned *
//3'b010 signed /
//3'b011 unsigned /
//3'b100 mfhi
... | 7.54397 |
module ALU_MEM (
input wire [ `ALUOp] aluop,
input wire [`DataBus] alures_i,
input wire [ `DWord] mulhi,
input wire [ `DWord] mullo,
input wire mul_s,
input wire [ `DWord] divres,
input wire [ `DWord] hilo_i,
input wire [`CP0Addr] cp0sel,
input wire exc_fla... | 6.646939 |
module Logic_unit (
input wire [0:2] COMMAND,
input wire A,
input wire B,
output wire NOT_B,
output wire A_OR_B,
output wire A_AND_B
);
assign NOT_B = COMMAND[2] & (~B);
assign A_OR_B = ((COMMAND[1] & A) | (COMMAND[1] & B));
assign A_AND_B = ((COMMAND[0] & A) & (COMMAND[0] & B));
en... | 6.91066 |
module Alu (
input wire A,
input wire B,
input wire [0:1] COMMAND,
output wire RES,
output wire CARRY
);
wire [0:3] Q;
wire NOT_B, A_AND_B, A_OR_B, SUM;
Command_decoder com_imp (
COMMAND,
Q
);
Sum sum_imp (
Q[0],
A,
B,
SUM,
CARRY
);
Logic_un... | 6.778546 |
module Memory (
input wire CLK, // Тактирование
input wire LOAD, // Сигнал разрешения рагрузки
input wire RST, // Сброс
input wire [0:3] INPUT_DATA, // Шина входных слов
output reg [0:3] OUTPUT_COMMAND // Шина выходных слов
);
reg [0:3] ... | 7.051739 |
module alu_mem_buff #(
parameter WbSize = 2,
MemSize = 9,
flagSize = 4
) (
input rst,
input clk,
enable,
input [MemSize-1:0] i_Mem,
input [WbSize-1 : 0] i_WB,
input [31:0] i_pc,
input [2:0] i_Rdst,
input [15:0] i_alu,
i_read_data1,
input [flagSize-1:0] i_flag,
ou... | 6.821875 |
module alu_mem_pipeline_reg (
alu_result,
base_reg_content_load_post,
mem_data_write,
wb_address,
base_register_address,
mem_control,
wb_control,
clock,
alu_result_out,
base_reg_content_out,
mem_data_write_out,
wb_address_out,
base_register_address_out,
mem_contro... | 7.626534 |
module ALU (
input wire [31:0] A,
B, // Entradas A e B da ALU, sendo A o primeiro operando e B o segundo
input wire [2:0] func, // Entrada seletora de func proveniente da C.U.
input wire sub_sra, // Entrada que ativa / desativa subtração e shift aritmético
output reg [31:0] alu_val, // Saída, qu... | 7.960621 |
module alu_mov (
input wire [15:0] operand1,
output wire [15:0] dout
);
assign dout = operand1;
endmodule
| 8.146148 |
module alu_movn (
input wire [ 6:0] immediate_offset,
output wire [15:0] dout
);
assign dout = immediate_offset;
endmodule
| 7.755752 |
module ALU_mul #(
parameter DATA_WIDTH = 4
) (
input clk,
input enable,
output busy,
input [DATA_WIDTH - 1 : 0] operand1,
input [DATA_WIDTH - 1 : 0] operand2,
output [DATA_WIDTH - 1 : 0] result
);
// cnt: counter
reg [DATA_WIDTH - 1 : 0] cnt;
always @(posedge clk) begin
if (!enable... | 8.229833 |
module alu_muldiv (
a_in,
b_in,
op_in,
clk,
a_reset_l,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
c_out,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out,
valid_out,
op_active
);
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_... | 7.222296 |
module Divider (
clk,
rst_n,
start,
done,
dividend,
divisor,
quotient,
remainder
);
// dividend / divisor = quotient ... remainder
input clk;
input rst_n;
input start;
output done;
input [31:0] dividend;
input [31:0] divisor;
output [31:0] quotient;
output [31:0] remain... | 7.440694 |
module multiplier_ns_logic (
op_start,
op_clear,
cnt,
state,
next_state,
next_cnt
); //next state logic
input [1:0] state;
input op_start, op_clear;
input [5:0] cnt;
output reg [1:0] next_state;
output reg [5:0] next_cnt;
//state encoding
parameter IDLE = 2'b00;
parameter EXEC ... | 6.96487 |
module multiplier_o_logic (
state,
result_in,
result_out,
op_done
); //output logic
input [1:0] state;
input [63:0] result_in;
output [63:0] result_out;
output reg op_done;
//encode state
parameter IDLE = 2'b00;
parameter EXEC = 2'b01;
parameter DONE = 2'b10;
always @(state) begin ... | 7.216559 |
module W0RM_ALU_Multiply #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
... | 6.502774 |
module alu_mult_altera (
clock,
dataa,
datab,
result
);
input clock;
input [31:0] dataa;
input [31:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
lpm_mult lpm_mult_component (
.clock(clock),
.dataa(dataa),
.datab(datab),
... | 6.607273 |
module ALU_Mul_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = (F... | 7.074993 |
module alu_mul_div (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input i_clk,
input i_rst,
input [`RW-1:0] i_a,
i_b,
output [`RW-1:0] o_d,
input i_mul,
input i_div,
input i_mod,
input i_submit,
input i_flush,
output o_busy
);
`define RWLOG 4
re... | 6.725414 |
module alu_mux (
input [3:0] alu_op,
input [31:0] mux_i_0,
input [31:0] mux_i_1,
input [31:0] mux_i_2,
input [31:0] mux_i_3,
output reg [31:0] mux_o
);
always @(*) begin
case (alu_op)
`ADD: mux_o = mux_i_0;
`SUB: mux_o = mux_i_0;
`AND: mux_o = mux_i_1;
`OR: mux_o =... | 7.302804 |
module alu_nor (
A,
B,
Z
);
// parameter definitions
parameter WIDTH = 32;
//port definitions
input wire [WIDTH-1:0] A, B;
output wire [WIDTH-1:0] Z;
// instantiate module's hardware
assign Z = ~(A | B);
endmodule
| 8.617848 |
module adding_one (
a,
s,
cin,
cout
); // adding one to first number (a) n bits if selection inputs are s0=0,s1=0,s2=0 ( 0 0 0 )
parameter N = `NUM_BITS - 1;
input [N:0] a;
input cin;
output cout;
output [N+1:0] s; ///////////////////////////////////////////////////
wire [N:0] b = 8'b00000... | 6.515227 |
module arithmetic_shift_right (
A,
C
); // arithmetic shift right for first number (a) n bits if selection inputs are s0=0,s1=0,s2=1 ( 0 0 1 )
parameter N = `NUM_BITS - 1;
input [N:0] A;
output [N+1:0] C;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
if (i == N) buf b1 (C[i], 1'... | 7.423881 |
module AND (
a,
b,
c
); // AND operation of 2 Numbers A and B if selection inputs are s0=1,s1=0,s2=1 ( 1 0 1 )
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
output [N+1:0] c;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
and (c[i], a[i], b[i]);
end
endgenerate
endm... | 7.053445 |
module OR (
a,
b,
c
); // OR operation of 2 Numbers A and B if selection inputs are s0=1,s1=1,s2=0 ( 1 1 0 )
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
output [N+1:0] c;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
or (c[i], a[i], b[i]);
end
endgenerate
endmo... | 7.086775 |
module XOR (
a,
b,
c
); // XOR operation of 2 Numbers A and B if selection inputs are s0=1,s1=1,s2=1 ( 1 1 1 )
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
output [N+1:0] c;
generate
genvar i;
for (i = 0; i <= N; i = i + 1) begin
xor (c[i], a[i], b[i]);
end
endgenerate
endmod... | 7.915029 |
module mux_8to_1 (
out,
i0,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
s0,
s1,
s2
); // 8:1 multiplexer
input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
output out;
wire w1, w2, w3, w4, w5, w6, w7, w8, s00, s01, s02;
not (s00, s0);
not (s01, s1);
not (s02, s2);
and (w1,... | 7.202391 |
module ALU (
a,
b,
outp,
s0,
s1,
s2
);
parameter N = `NUM_BITS - 1;
input [N:0] a, b;
input s0, s1, s2;
output cout;
wire [N+1:0] c1, c2, c3, c4, c5, c6, c7, c8;
output [N+1:0] outp;
adding_one fa0 (
a,
c1,
1'b0,
cout
); // carry = 0
arithmetic_sh... | 7.650109 |
module alu_operand_decode (
instr,
rsVal,
rtVal,
opA,
opB
);
input [15:0] instr;
input [15:0] rsVal;
input [15:0] rtVal;
output [15:0] opA;
output [15:0] opB;
// wires and regs
reg [15:0] opBVal;
wire [ 6:0] op;
// assigns
assign opA = rsVal;
assign opB = opBVal;
assign o... | 6.909198 |
module A_NOP (
A,
B,
Y2,
Y1
); //no opertaion
input [31:0] A, B;
output [31:0] Y2, Y1;
assign Y1 = 32'h0000_0000;
assign Y2 = 32'h0000_0000; //sign extension
endmodule
| 7.456359 |
module A_NOTA (
A,
B,
Y2,
Y1
); //NOT A
input [31:0] A, B;
output [31:0] Y2;
output [31:0] Y1;
assign Y1 = ~A;
assign Y2[7:0] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[15:8] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2... | 7.229655 |
module A_NOTB (
A,
B,
Y2,
Y1
); //NOT B
input [31:0] A, B;
output [31:0] Y2, Y1;
assign Y1 = ~B;
assign Y2[7:0] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[15:8] = {Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31], Y1[31]};
assign Y2[23:16] = {Y1[31... | 6.764727 |
module A_LSLA (
A,
B,
S,
Y2,
Y1
); //LSLA
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = A;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] =... | 7.089916 |
module A_LSLB (
A,
B,
S,
Y2,
Y1
); //LSLB
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = B;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] =... | 7.488285 |
module A_LSRA (
A,
B,
S,
Y2,
Y1
); //LSRA
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = A;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] =... | 7.763736 |
module A_LSRB (
A,
B,
S,
Y2,
Y1
); //LSRB
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = B;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] =... | 7.519697 |
module A_ASRA (
A,
B,
S,
Y2,
Y1
); //ASRA
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = A;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] =... | 7.879591 |
module A_ASRB (
A,
B,
S,
Y2,
Y1
); //ASRB
input [31:0] A, B;
input [1:0] S;
output reg [31:0] Y2, Y1;
always @(A or B or S) begin
if(S == 2'b00) //no shift
begin
Y1 = B;
Y2[0] = Y1[31];
Y2[1:0] = {Y2[0], Y2[0]};
Y2[3:0] = {Y2[1:0], Y2[1:0]};
Y2[7:0] =... | 7.812936 |
module alu_op_decode (
instr,
alu_op
);
input [15:0] instr;
output [4:0] alu_op;
parameter ADD = 0;
parameter SUB = 1;
parameter OR = 2;
parameter AND = 3;
parameter ROL = 4;
parameter SLL = 5;
parameter ROR = 6;
parameter SRA = 7;
parameter ST = 8;
parameter LD = 9;
parameter STU = ... | 6.816088 |
module alu_or (
A,
B,
Z
);
parameter WIDTH = 32;
//port definitions
input wire [(WIDTH - 1):0] A, B;
output wire [(WIDTH - 1):0] Z;
assign Z = A | B;
endmodule
| 8.948799 |
module alu_orr (
input [15:0] operand1,
input [15:0] operand2,
output [15:0] dout
);
assign dout = operand1 | operand2;
endmodule
| 7.889208 |
module OrModule (
bigMuxIn4,
inA,
inB
);
output [7:0] bigMuxIn4;
input [7:0] inA;
input [7:0] inB;
or (bigMuxIn4[0], inA[0], inB[0]);
or (bigMuxIn4[1], inA[1], inB[1]);
or (bigMuxIn4[2], inA[2], inB[2]);
or (bigMuxIn4[3], inA[3], inB[3]);
or (bigMuxIn4[4], inA[4], inB[4]);
or (bigMuxIn4... | 7.948939 |
module ALU_output (
input [31:0] input_data,
input clk,
output reg [31:0] output_data
);
always @(negedge clk) begin
output_data = input_data;
end
endmodule
| 7.397489 |
module alu_output_stage (
out_data1,
out_data2,
out_data3,
out_data4,
out_resp1,
out_resp2,
out_resp3,
out_resp4,
c_clk,
alu_overflow,
alu_result,
local_error_found,
prio_alu_out_req_id,
prio_alu_out_vld,
reset
);
output [0:31] out_data1, out_data2, out_dat... | 6.877864 |
module ALU_OUT_EX_MEM (
input [31:0] data_from_ALU,
input clock,
output reg [31:0] data_for_Mem_stage
);
always @(posedge clock) begin
data_for_Mem_stage = data_from_ALU;
end
endmodule
| 7.297428 |
module ALU_Out_Reg (
ALUResult,
Clk,
Reset,
Result
);
input [31:0] ALUResult;
input Clk, Reset;
output reg [31:0] Result;
always @(posedge Clk) begin
if (Reset) Result <= 32'b0;
else Result <= ALUResult;
end
endmodule
| 6.710175 |
module D_ff (
input clk,
input reset,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.58165 |
module decoder3to8 (
input [2:0] destReg,
output reg [7:0] decOut
);
always @(destReg) begin
case (destReg)
3'b000: decOut = 8'b00000001;
3'b001: decOut = 8'b00000010;
3'b010: decOut = 8'b00000100;
3'b011: decOut = 8'b00001000;
3'b100: decOut = 8'b00010000;
3'b101: decO... | 8.532605 |
module mux8to1 (
input [15:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
input [2:0] Sel,
output reg [15:0] outBus
);
always @(outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or Sel) begin
case (Sel)
3'b000: outBus = outR0;
3'b0... | 7.465042 |
module registerFile (
input clk,
input reset,
input regWrite,
input regWriteDoosra,
input [2:0] srcRegA
, input [2:0] srcRegB,
input [2:0] srcRegC,
input [2:0] srcRegD,
input [2:0] destReg,
input [2:0] destRegDoosra,
input [15:0] writeData,
input [15:0] writeDataDoosra,
... | 6.674499 |
module D_ff_Mem (
input clk,
input reset,
input regWrite,
input decOut1b,
input init,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1) q = init;
else if (regWrite == 1 && decOut1b == 1) begin
q = d;
end
end
endmodule
| 6.84774 |
module decoder4to16 (
input [3:0] destReg,
output reg [15:0] decOut
);
always @(destReg)
case (destReg)
4'b0000: decOut = 16'b0000000000000001;
4'b0001: decOut = 16'b0000000000000010;
4'b0010: decOut = 16'b0000000000000100;
4'b0011: decOut = 16'b0000000000001000;
4'b0100: dec... | 8.126959 |
module mux16to1 (
input [15:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [15:0] outBus
);
always@(outR0 or outR1 or outR2 or outR3 or outR4 or... | 7.318793 |
module mux16to1_8 (
input [7:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [7:0] outBus
);
always@(outR0 or outR1 or outR2 or outR3 or outR4 or... | 7.319464 |
module pcAdder (
input [15:0] pc,
output reg [15:0] newPC
);
always @(pc) begin
newPC = pc + 4;
end
endmodule
| 7.400415 |
module adderModule (
input [15:0] inp1,
input [15:0] inp2,
output reg [15:0] adderKaResult
);
always @(inp1, inp2) begin
adderKaResult = inp1 + inp2;
end
endmodule
| 6.960076 |
module IF_ID (
input clk,
input reset,
input regWrite,
input decOut1b,
input [31:0] instr,
input [15:0] PC,
output [15:0] p0_intr,
output [15:0] p0_intr2,
output [15:0] PCOut
);
register16bit PC_reg (
clk,
reset,
regWrite,
decOut1b,
PC,
PCOut
... | 7.719833 |
module ID_EX (
input clk,
input reset,
input regWrite,
input decOut1b,
input [15:0] insFetchOutput,
input [15:0] regOut1,
input [15:0] regOut2,
input [15:0] sExtOut,
input [2:0] ctr_Rd,
input [1:0] ctr_aluSrcA,
input ctr_aluSrcB,
input [1:0] ctr_aluOp,
input ctr_regWr... | 8.23208 |
module signExtModule (
input [4:0] offset5,
input [10:0] offset11,
input [7:0] offset8,
input [1:0] ctrSignExt,
output reg [15:0] signExtModuleOutput
);
always @(offset5, offset11, offset8, ctrSignExt) begin
if (ctrSignExt == 2'b00) signExtModuleOutput = {{11{offset5[4]}}, offset5[4:0]};
e... | 7.391111 |
module ALU (
input [15:0] AluIn1,
input [15:0] AluIn2,
input [1:0] AluOp,
output reg [15:0] AluOut,
output reg [3:0] flag
);
always @(AluIn1, AluIn2, AluOp) begin
if (AluOp == 2'b10) AluOut = AluIn1 + AluIn2;
else if (AluOp == 2'b11) AluOut = AluIn1 - AluIn2;
else if (AluOp == 2'b01) A... | 7.960621 |
module adderforbranch (
input [15:0] PC,
input [15:0] shiftedvalue,
input opcodebit,
input zeroflag,
output reg [15:0] BranchAddress
);
always @(PC, shiftedvalue, opcodebit, zeroflag) begin
if (zeroflag == 1 && opcodebit == 1) BranchAddress = PC + shiftedvalue;
else if (zeroflag == 0 && op... | 7.472959 |
module signExt (
input [2:0] immShort,
input [7:0] immLong,
input immSrc,
output reg [15:0] sextOutput
);
always @(immShort, immLong, immSrc) begin
if (immSrc == 1'b0) sextOutput = {{13{immShort[2]}}, immShort[2:0]};
else sextOutput = {{8{immLong[7]}}, immLong[7:0]};
end
endmodule
| 7.404229 |
module mux2to1 (
input [2:0] inp1,
input [2:0] inp2,
input sel,
output reg [2:0] muxOut
);
always @(inp1, inp2, sel) begin
if (sel == 1'b0) muxOut = inp1;
else muxOut = inp2;
end
endmodule
| 7.107199 |
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